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9878760c | 1 | /* Subroutines used for code generation on IBM RS/6000. |
9ebbca7d | 2 | Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, |
93c9d1ba | 3 | 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc. |
fab3bcc3 | 4 | Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu) |
9878760c | 5 | |
5de601cf | 6 | This file is part of GCC. |
9878760c | 7 | |
5de601cf NC |
8 | GCC is free software; you can redistribute it and/or modify it |
9 | under the terms of the GNU General Public License as published | |
10 | by the Free Software Foundation; either version 2, or (at your | |
11 | option) any later version. | |
9878760c | 12 | |
5de601cf NC |
13 | GCC is distributed in the hope that it will be useful, but WITHOUT |
14 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
15 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
16 | License for more details. | |
9878760c | 17 | |
5de601cf NC |
18 | You should have received a copy of the GNU General Public License |
19 | along with GCC; see the file COPYING. If not, write to the | |
20 | Free Software Foundation, 59 Temple Place - Suite 330, Boston, | |
21 | MA 02111-1307, USA. */ | |
9878760c | 22 | |
956d6950 | 23 | #include "config.h" |
c4d38ccb | 24 | #include "system.h" |
4977bab6 ZW |
25 | #include "coretypes.h" |
26 | #include "tm.h" | |
9878760c RK |
27 | #include "rtl.h" |
28 | #include "regs.h" | |
29 | #include "hard-reg-set.h" | |
30 | #include "real.h" | |
31 | #include "insn-config.h" | |
32 | #include "conditions.h" | |
9878760c RK |
33 | #include "insn-attr.h" |
34 | #include "flags.h" | |
35 | #include "recog.h" | |
9878760c | 36 | #include "obstack.h" |
9b30bae2 | 37 | #include "tree.h" |
dfafc897 | 38 | #include "expr.h" |
2fc1c679 | 39 | #include "optabs.h" |
2a430ec1 | 40 | #include "except.h" |
a7df97e6 | 41 | #include "function.h" |
296b8152 | 42 | #include "output.h" |
d5fa86ba | 43 | #include "basic-block.h" |
d0101753 | 44 | #include "integrate.h" |
296b8152 | 45 | #include "toplev.h" |
c8023011 | 46 | #include "ggc.h" |
9ebbca7d GK |
47 | #include "hashtab.h" |
48 | #include "tm_p.h" | |
672a6f42 NB |
49 | #include "target.h" |
50 | #include "target-def.h" | |
3ac88239 | 51 | #include "langhooks.h" |
24ea750e | 52 | #include "reload.h" |
117dca74 | 53 | #include "cfglayout.h" |
79ae11c4 | 54 | #include "sched-int.h" |
1bc7c5b6 ZW |
55 | #if TARGET_XCOFF |
56 | #include "xcoffout.h" /* get declarations of xcoff_*_section_name */ | |
57 | #endif | |
9b30bae2 | 58 | |
7509c759 MM |
59 | #ifndef TARGET_NO_PROTOTYPE |
60 | #define TARGET_NO_PROTOTYPE 0 | |
61 | #endif | |
62 | ||
d744e06e AH |
63 | #define EASY_VECTOR_15(n, x, y) ((n) >= -16 && (n) <= 15 \ |
64 | && easy_vector_same (x, y)) | |
65 | ||
66 | #define EASY_VECTOR_15_ADD_SELF(n, x, y) ((n) >= 0x10 && (n) <= 0x1e \ | |
67 | && !((n) & 1) \ | |
68 | && easy_vector_same (x, y)) | |
69 | ||
9878760c RK |
70 | #define min(A,B) ((A) < (B) ? (A) : (B)) |
71 | #define max(A,B) ((A) > (B) ? (A) : (B)) | |
72 | ||
d1d0c603 JJ |
73 | /* Structure used to define the rs6000 stack */ |
74 | typedef struct rs6000_stack { | |
75 | int first_gp_reg_save; /* first callee saved GP register used */ | |
76 | int first_fp_reg_save; /* first callee saved FP register used */ | |
77 | int first_altivec_reg_save; /* first callee saved AltiVec register used */ | |
78 | int lr_save_p; /* true if the link reg needs to be saved */ | |
79 | int cr_save_p; /* true if the CR reg needs to be saved */ | |
80 | unsigned int vrsave_mask; /* mask of vec registers to save */ | |
81 | int toc_save_p; /* true if the TOC needs to be saved */ | |
82 | int push_p; /* true if we need to allocate stack space */ | |
83 | int calls_p; /* true if the function makes any calls */ | |
84 | enum rs6000_abi abi; /* which ABI to use */ | |
85 | int gp_save_offset; /* offset to save GP regs from initial SP */ | |
86 | int fp_save_offset; /* offset to save FP regs from initial SP */ | |
87 | int altivec_save_offset; /* offset to save AltiVec regs from initial SP */ | |
88 | int lr_save_offset; /* offset to save LR from initial SP */ | |
89 | int cr_save_offset; /* offset to save CR from initial SP */ | |
90 | int vrsave_save_offset; /* offset to save VRSAVE from initial SP */ | |
91 | int spe_gp_save_offset; /* offset to save spe 64-bit gprs */ | |
92 | int toc_save_offset; /* offset to save the TOC pointer */ | |
93 | int varargs_save_offset; /* offset to save the varargs registers */ | |
94 | int ehrd_offset; /* offset to EH return data */ | |
95 | int reg_size; /* register size (4 or 8) */ | |
96 | int varargs_size; /* size to hold V.4 args passed in regs */ | |
97 | HOST_WIDE_INT vars_size; /* variable save area size */ | |
98 | int parm_size; /* outgoing parameter size */ | |
99 | int save_size; /* save area size */ | |
100 | int fixed_size; /* fixed size of stack frame */ | |
101 | int gp_size; /* size of saved GP registers */ | |
102 | int fp_size; /* size of saved FP registers */ | |
103 | int altivec_size; /* size of saved AltiVec registers */ | |
104 | int cr_size; /* size to hold CR if not in save_size */ | |
105 | int lr_size; /* size to hold LR if not in save_size */ | |
106 | int vrsave_size; /* size to hold VRSAVE if not in save_size */ | |
107 | int altivec_padding_size; /* size of altivec alignment padding if | |
108 | not in save_size */ | |
109 | int spe_gp_size; /* size of 64-bit GPR save size for SPE */ | |
110 | int spe_padding_size; | |
111 | int toc_size; /* size to hold TOC if not in save_size */ | |
112 | HOST_WIDE_INT total_size; /* total bytes allocated for stack */ | |
113 | int spe_64bit_regs_used; | |
114 | } rs6000_stack_t; | |
115 | ||
5248c961 RK |
116 | /* Target cpu type */ |
117 | ||
118 | enum processor_type rs6000_cpu; | |
8e3f41e7 MM |
119 | struct rs6000_cpu_select rs6000_select[3] = |
120 | { | |
815cdc52 MM |
121 | /* switch name, tune arch */ |
122 | { (const char *)0, "--with-cpu=", 1, 1 }, | |
123 | { (const char *)0, "-mcpu=", 1, 1 }, | |
124 | { (const char *)0, "-mtune=", 1, 0 }, | |
8e3f41e7 | 125 | }; |
5248c961 | 126 | |
79ae11c4 DN |
127 | /* Support adjust_priority scheduler hook |
128 | and -mprioritize-restricted-insns= option. */ | |
129 | const char *rs6000_sched_restricted_insns_priority_str; | |
130 | int rs6000_sched_restricted_insns_priority; | |
131 | ||
569fa502 DN |
132 | /* Support for -msched-costly-dep option. */ |
133 | const char *rs6000_sched_costly_dep_str; | |
134 | enum rs6000_dependence_cost rs6000_sched_costly_dep; | |
135 | ||
cbe26ab8 DN |
136 | /* Support for -minsert-sched-nops option. */ |
137 | const char *rs6000_sched_insert_nops_str; | |
138 | enum rs6000_nop_insertion rs6000_sched_insert_nops; | |
139 | ||
6fa3f289 ZW |
140 | /* Size of long double */ |
141 | const char *rs6000_long_double_size_string; | |
142 | int rs6000_long_double_type_size; | |
143 | ||
144 | /* Whether -mabi=altivec has appeared */ | |
145 | int rs6000_altivec_abi; | |
146 | ||
08b57fb3 AH |
147 | /* Whether VRSAVE instructions should be generated. */ |
148 | int rs6000_altivec_vrsave; | |
149 | ||
150 | /* String from -mvrsave= option. */ | |
151 | const char *rs6000_altivec_vrsave_string; | |
152 | ||
a3170dc6 AH |
153 | /* Nonzero if we want SPE ABI extensions. */ |
154 | int rs6000_spe_abi; | |
155 | ||
156 | /* Whether isel instructions should be generated. */ | |
157 | int rs6000_isel; | |
158 | ||
993f19a8 AH |
159 | /* Whether SPE simd instructions should be generated. */ |
160 | int rs6000_spe; | |
161 | ||
5da702b1 AH |
162 | /* Nonzero if floating point operations are done in the GPRs. */ |
163 | int rs6000_float_gprs = 0; | |
164 | ||
165 | /* String from -mfloat-gprs=. */ | |
166 | const char *rs6000_float_gprs_string; | |
a3170dc6 AH |
167 | |
168 | /* String from -misel=. */ | |
169 | const char *rs6000_isel_string; | |
170 | ||
993f19a8 AH |
171 | /* String from -mspe=. */ |
172 | const char *rs6000_spe_string; | |
173 | ||
a0ab749a | 174 | /* Set to nonzero once AIX common-mode calls have been defined. */ |
bbfb86aa | 175 | static GTY(()) int common_mode_defined; |
c81bebd7 | 176 | |
9878760c RK |
177 | /* Save information from a "cmpxx" operation until the branch or scc is |
178 | emitted. */ | |
9878760c RK |
179 | rtx rs6000_compare_op0, rs6000_compare_op1; |
180 | int rs6000_compare_fp_p; | |
874a0744 | 181 | |
874a0744 MM |
182 | /* Label number of label created for -mrelocatable, to call to so we can |
183 | get the address of the GOT section */ | |
184 | int rs6000_pic_labelno; | |
c81bebd7 | 185 | |
b91da81f | 186 | #ifdef USING_ELFOS_H |
c81bebd7 | 187 | /* Which abi to adhere to */ |
9739c90c | 188 | const char *rs6000_abi_name; |
d9407988 MM |
189 | |
190 | /* Semantics of the small data area */ | |
191 | enum rs6000_sdata_type rs6000_sdata = SDATA_DATA; | |
192 | ||
193 | /* Which small data model to use */ | |
815cdc52 | 194 | const char *rs6000_sdata_name = (char *)0; |
9ebbca7d GK |
195 | |
196 | /* Counter for labels which are to be placed in .fixup. */ | |
197 | int fixuplabelno = 0; | |
874a0744 | 198 | #endif |
4697a36c | 199 | |
c4501e62 JJ |
200 | /* Bit size of immediate TLS offsets and string from which it is decoded. */ |
201 | int rs6000_tls_size = 32; | |
202 | const char *rs6000_tls_size_string; | |
203 | ||
b6c9286a MM |
204 | /* ABI enumeration available for subtarget to use. */ |
205 | enum rs6000_abi rs6000_current_abi; | |
206 | ||
0ac081f6 AH |
207 | /* ABI string from -mabi= option. */ |
208 | const char *rs6000_abi_string; | |
209 | ||
38c1f2d7 | 210 | /* Debug flags */ |
815cdc52 | 211 | const char *rs6000_debug_name; |
38c1f2d7 MM |
212 | int rs6000_debug_stack; /* debug stack applications */ |
213 | int rs6000_debug_arg; /* debug argument handling */ | |
214 | ||
6035d635 | 215 | /* Opaque types. */ |
2abe3e28 | 216 | static GTY(()) tree opaque_V2SI_type_node; |
2abe3e28 | 217 | static GTY(()) tree opaque_V2SF_type_node; |
6035d635 | 218 | static GTY(()) tree opaque_p_V2SI_type_node; |
2abe3e28 | 219 | |
57ac7be9 AM |
220 | const char *rs6000_traceback_name; |
221 | static enum { | |
222 | traceback_default = 0, | |
223 | traceback_none, | |
224 | traceback_part, | |
225 | traceback_full | |
226 | } rs6000_traceback; | |
227 | ||
38c1f2d7 MM |
228 | /* Flag to say the TOC is initialized */ |
229 | int toc_initialized; | |
9ebbca7d | 230 | char toc_label_name[10]; |
38c1f2d7 | 231 | |
9ebbca7d | 232 | /* Alias set for saves and restores from the rs6000 stack. */ |
f103e34d | 233 | static GTY(()) int rs6000_sr_alias_set; |
c8023011 | 234 | |
a5c76ee6 ZW |
235 | /* Call distance, overridden by -mlongcall and #pragma longcall(1). |
236 | The only place that looks at this is rs6000_set_default_type_attributes; | |
237 | everywhere else should rely on the presence or absence of a longcall | |
238 | attribute on the function declaration. */ | |
239 | int rs6000_default_long_calls; | |
240 | const char *rs6000_longcall_switch; | |
241 | ||
a3c9585f KH |
242 | /* Control alignment for fields within structures. */ |
243 | /* String from -malign-XXXXX. */ | |
025d9908 KH |
244 | const char *rs6000_alignment_string; |
245 | int rs6000_alignment_flags; | |
246 | ||
a3170dc6 AH |
247 | struct builtin_description |
248 | { | |
249 | /* mask is not const because we're going to alter it below. This | |
250 | nonsense will go away when we rewrite the -march infrastructure | |
251 | to give us more target flag bits. */ | |
252 | unsigned int mask; | |
253 | const enum insn_code icode; | |
254 | const char *const name; | |
255 | const enum rs6000_builtins code; | |
256 | }; | |
257 | ||
a2369ed3 DJ |
258 | static bool rs6000_function_ok_for_sibcall (tree, tree); |
259 | static int num_insns_constant_wide (HOST_WIDE_INT); | |
260 | static void validate_condition_mode (enum rtx_code, enum machine_mode); | |
261 | static rtx rs6000_generate_compare (enum rtx_code); | |
262 | static void rs6000_maybe_dead (rtx); | |
263 | static void rs6000_emit_stack_tie (void); | |
264 | static void rs6000_frame_related (rtx, rtx, HOST_WIDE_INT, rtx, rtx); | |
265 | static rtx spe_synthesize_frame_save (rtx); | |
266 | static bool spe_func_has_64bit_regs_p (void); | |
b20a9cca | 267 | static void emit_frame_save (rtx, rtx, enum machine_mode, unsigned int, |
d1d0c603 | 268 | int, HOST_WIDE_INT); |
a2369ed3 DJ |
269 | static rtx gen_frame_mem_offset (enum machine_mode, rtx, int); |
270 | static void rs6000_emit_allocate_stack (HOST_WIDE_INT, int); | |
271 | static unsigned rs6000_hash_constant (rtx); | |
272 | static unsigned toc_hash_function (const void *); | |
273 | static int toc_hash_eq (const void *, const void *); | |
274 | static int constant_pool_expr_1 (rtx, int *, int *); | |
275 | static bool constant_pool_expr_p (rtx); | |
276 | static bool toc_relative_expr_p (rtx); | |
277 | static bool legitimate_small_data_p (enum machine_mode, rtx); | |
278 | static bool legitimate_offset_address_p (enum machine_mode, rtx, int); | |
279 | static bool legitimate_indexed_address_p (rtx, int); | |
280 | static bool legitimate_indirect_address_p (rtx, int); | |
4c81e946 | 281 | static bool macho_lo_sum_memory_operand (rtx x, enum machine_mode mode); |
a2369ed3 DJ |
282 | static bool legitimate_lo_sum_address_p (enum machine_mode, rtx, int); |
283 | static struct machine_function * rs6000_init_machine_status (void); | |
284 | static bool rs6000_assemble_integer (rtx, unsigned int, int); | |
5add3202 | 285 | #ifdef HAVE_GAS_HIDDEN |
a2369ed3 | 286 | static void rs6000_assemble_visibility (tree, int); |
5add3202 | 287 | #endif |
a2369ed3 DJ |
288 | static int rs6000_ra_ever_killed (void); |
289 | static tree rs6000_handle_longcall_attribute (tree *, tree, tree, int, bool *); | |
b86fe7b4 | 290 | extern const struct attribute_spec rs6000_attribute_table[]; |
a2369ed3 DJ |
291 | static void rs6000_set_default_type_attributes (tree); |
292 | static void rs6000_output_function_prologue (FILE *, HOST_WIDE_INT); | |
293 | static void rs6000_output_function_epilogue (FILE *, HOST_WIDE_INT); | |
b20a9cca AM |
294 | static void rs6000_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT, |
295 | tree); | |
a2369ed3 | 296 | static rtx rs6000_emit_set_long_const (rtx, HOST_WIDE_INT, HOST_WIDE_INT); |
c6e8c921 | 297 | static bool rs6000_return_in_memory (tree, tree); |
a2369ed3 | 298 | static void rs6000_file_start (void); |
7c262518 | 299 | #if TARGET_ELF |
a2369ed3 DJ |
300 | static unsigned int rs6000_elf_section_type_flags (tree, const char *, int); |
301 | static void rs6000_elf_asm_out_constructor (rtx, int); | |
302 | static void rs6000_elf_asm_out_destructor (rtx, int); | |
303 | static void rs6000_elf_select_section (tree, int, unsigned HOST_WIDE_INT); | |
304 | static void rs6000_elf_unique_section (tree, int); | |
305 | static void rs6000_elf_select_rtx_section (enum machine_mode, rtx, | |
b20a9cca | 306 | unsigned HOST_WIDE_INT); |
a56d7372 | 307 | static void rs6000_elf_encode_section_info (tree, rtx, int) |
0e5dbd9b | 308 | ATTRIBUTE_UNUSED; |
a2369ed3 | 309 | static bool rs6000_elf_in_small_data_p (tree); |
7c262518 | 310 | #endif |
cbaaba19 | 311 | #if TARGET_XCOFF |
a2369ed3 DJ |
312 | static void rs6000_xcoff_asm_globalize_label (FILE *, const char *); |
313 | static void rs6000_xcoff_asm_named_section (const char *, unsigned int); | |
314 | static void rs6000_xcoff_select_section (tree, int, unsigned HOST_WIDE_INT); | |
315 | static void rs6000_xcoff_unique_section (tree, int); | |
316 | static void rs6000_xcoff_select_rtx_section (enum machine_mode, rtx, | |
b20a9cca | 317 | unsigned HOST_WIDE_INT); |
a2369ed3 DJ |
318 | static const char * rs6000_xcoff_strip_name_encoding (const char *); |
319 | static unsigned int rs6000_xcoff_section_type_flags (tree, const char *, int); | |
320 | static void rs6000_xcoff_file_start (void); | |
321 | static void rs6000_xcoff_file_end (void); | |
f1384257 AM |
322 | #endif |
323 | #if TARGET_MACHO | |
a2369ed3 | 324 | static bool rs6000_binds_local_p (tree); |
f1384257 | 325 | #endif |
a2369ed3 DJ |
326 | static int rs6000_use_dfa_pipeline_interface (void); |
327 | static int rs6000_variable_issue (FILE *, int, rtx, int); | |
328 | static bool rs6000_rtx_costs (rtx, int, int, int *); | |
329 | static int rs6000_adjust_cost (rtx, rtx, rtx, int); | |
cbe26ab8 | 330 | static bool is_microcoded_insn (rtx); |
79ae11c4 | 331 | static int is_dispatch_slot_restricted (rtx); |
cbe26ab8 DN |
332 | static bool is_cracked_insn (rtx); |
333 | static bool is_branch_slot_insn (rtx); | |
a2369ed3 DJ |
334 | static int rs6000_adjust_priority (rtx, int); |
335 | static int rs6000_issue_rate (void); | |
569fa502 | 336 | static bool rs6000_is_costly_dependence (rtx, rtx, rtx, int, int); |
cbe26ab8 DN |
337 | static rtx get_next_active_insn (rtx, rtx); |
338 | static bool insn_terminates_group_p (rtx , enum group_termination); | |
339 | static bool is_costly_group (rtx *, rtx); | |
340 | static int force_new_group (int, FILE *, rtx *, rtx, bool *, int, int *); | |
341 | static int redefine_groups (FILE *, int, rtx, rtx); | |
342 | static int pad_groups (FILE *, int, rtx, rtx); | |
343 | static void rs6000_sched_finish (FILE *, int); | |
a2369ed3 DJ |
344 | static int rs6000_use_sched_lookahead (void); |
345 | ||
346 | static void rs6000_init_builtins (void); | |
347 | static rtx rs6000_expand_unop_builtin (enum insn_code, tree, rtx); | |
348 | static rtx rs6000_expand_binop_builtin (enum insn_code, tree, rtx); | |
349 | static rtx rs6000_expand_ternop_builtin (enum insn_code, tree, rtx); | |
350 | static rtx rs6000_expand_builtin (tree, rtx, rtx, enum machine_mode, int); | |
351 | static void altivec_init_builtins (void); | |
352 | static void rs6000_common_init_builtins (void); | |
c15c90bb | 353 | static void rs6000_init_libfuncs (void); |
a2369ed3 | 354 | |
b20a9cca AM |
355 | static void enable_mask_for_builtins (struct builtin_description *, int, |
356 | enum rs6000_builtins, | |
357 | enum rs6000_builtins); | |
a2369ed3 DJ |
358 | static void spe_init_builtins (void); |
359 | static rtx spe_expand_builtin (tree, rtx, bool *); | |
360 | static rtx spe_expand_predicate_builtin (enum insn_code, tree, rtx); | |
361 | static rtx spe_expand_evsel_builtin (enum insn_code, tree, rtx); | |
362 | static int rs6000_emit_int_cmove (rtx, rtx, rtx, rtx); | |
d1d0c603 JJ |
363 | static rs6000_stack_t *rs6000_stack_info (void); |
364 | static void debug_stack_info (rs6000_stack_t *); | |
a2369ed3 DJ |
365 | |
366 | static rtx altivec_expand_builtin (tree, rtx, bool *); | |
367 | static rtx altivec_expand_ld_builtin (tree, rtx, bool *); | |
368 | static rtx altivec_expand_st_builtin (tree, rtx, bool *); | |
369 | static rtx altivec_expand_dst_builtin (tree, rtx, bool *); | |
370 | static rtx altivec_expand_abs_builtin (enum insn_code, tree, rtx); | |
371 | static rtx altivec_expand_predicate_builtin (enum insn_code, | |
372 | const char *, tree, rtx); | |
b4a62fa0 | 373 | static rtx altivec_expand_lv_builtin (enum insn_code, tree, rtx); |
a2369ed3 DJ |
374 | static rtx altivec_expand_stv_builtin (enum insn_code, tree); |
375 | static void rs6000_parse_abi_options (void); | |
376 | static void rs6000_parse_alignment_option (void); | |
377 | static void rs6000_parse_tls_size_option (void); | |
5da702b1 | 378 | static void rs6000_parse_yes_no_option (const char *, const char *, int *); |
a2369ed3 DJ |
379 | static int first_altivec_reg_to_save (void); |
380 | static unsigned int compute_vrsave_mask (void); | |
381 | static void is_altivec_return_reg (rtx, void *); | |
382 | static rtx generate_set_vrsave (rtx, rs6000_stack_t *, int); | |
383 | int easy_vector_constant (rtx, enum machine_mode); | |
384 | static int easy_vector_same (rtx, enum machine_mode); | |
385 | static bool is_ev64_opaque_type (tree); | |
386 | static rtx rs6000_dwarf_register_span (rtx); | |
387 | static rtx rs6000_legitimize_tls_address (rtx, enum tls_model); | |
388 | static rtx rs6000_tls_get_addr (void); | |
389 | static rtx rs6000_got_sym (void); | |
390 | static inline int rs6000_tls_symbol_ref_1 (rtx *, void *); | |
391 | static const char *rs6000_get_some_local_dynamic_name (void); | |
392 | static int rs6000_get_some_local_dynamic_name_1 (rtx *, void *); | |
ded9bf77 | 393 | static rtx rs6000_complex_function_value (enum machine_mode); |
b20a9cca | 394 | static rtx rs6000_spe_function_arg (CUMULATIVE_ARGS *, |
a2369ed3 | 395 | enum machine_mode, tree); |
b78d48dd FJ |
396 | static rtx rs6000_mixed_function_arg (CUMULATIVE_ARGS *, |
397 | enum machine_mode, tree, int); | |
5985c7a6 | 398 | static void rs6000_move_block_from_reg(int regno, rtx x, int nregs); |
c6e8c921 GK |
399 | static void setup_incoming_varargs (CUMULATIVE_ARGS *, |
400 | enum machine_mode, tree, | |
401 | int *, int); | |
efdba735 SH |
402 | #if TARGET_MACHO |
403 | static void macho_branch_islands (void); | |
404 | static void add_compiler_branch_island (tree, tree, int); | |
405 | static int no_previous_def (tree function_name); | |
406 | static tree get_prev_label (tree function_name); | |
407 | #endif | |
408 | ||
c35d187f | 409 | static tree rs6000_build_builtin_va_list (void); |
17211ab5 GK |
410 | |
411 | /* Hash table stuff for keeping track of TOC entries. */ | |
412 | ||
413 | struct toc_hash_struct GTY(()) | |
414 | { | |
415 | /* `key' will satisfy CONSTANT_P; in fact, it will satisfy | |
416 | ASM_OUTPUT_SPECIAL_POOL_ENTRY_P. */ | |
417 | rtx key; | |
418 | enum machine_mode key_mode; | |
419 | int labelno; | |
420 | }; | |
421 | ||
422 | static GTY ((param_is (struct toc_hash_struct))) htab_t toc_hash_table; | |
c81bebd7 MM |
423 | \f |
424 | /* Default register names. */ | |
425 | char rs6000_reg_names[][8] = | |
426 | { | |
802a0058 MM |
427 | "0", "1", "2", "3", "4", "5", "6", "7", |
428 | "8", "9", "10", "11", "12", "13", "14", "15", | |
429 | "16", "17", "18", "19", "20", "21", "22", "23", | |
430 | "24", "25", "26", "27", "28", "29", "30", "31", | |
431 | "0", "1", "2", "3", "4", "5", "6", "7", | |
432 | "8", "9", "10", "11", "12", "13", "14", "15", | |
433 | "16", "17", "18", "19", "20", "21", "22", "23", | |
434 | "24", "25", "26", "27", "28", "29", "30", "31", | |
435 | "mq", "lr", "ctr","ap", | |
436 | "0", "1", "2", "3", "4", "5", "6", "7", | |
0ac081f6 AH |
437 | "xer", |
438 | /* AltiVec registers. */ | |
0cd5e3a1 AH |
439 | "0", "1", "2", "3", "4", "5", "6", "7", |
440 | "8", "9", "10", "11", "12", "13", "14", "15", | |
441 | "16", "17", "18", "19", "20", "21", "22", "23", | |
442 | "24", "25", "26", "27", "28", "29", "30", "31", | |
59a4c851 AH |
443 | "vrsave", "vscr", |
444 | /* SPE registers. */ | |
445 | "spe_acc", "spefscr" | |
c81bebd7 MM |
446 | }; |
447 | ||
448 | #ifdef TARGET_REGNAMES | |
8b60264b | 449 | static const char alt_reg_names[][8] = |
c81bebd7 | 450 | { |
802a0058 MM |
451 | "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7", |
452 | "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15", | |
453 | "%r16", "%r17", "%r18", "%r19", "%r20", "%r21", "%r22", "%r23", | |
454 | "%r24", "%r25", "%r26", "%r27", "%r28", "%r29", "%r30", "%r31", | |
455 | "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7", | |
456 | "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15", | |
457 | "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23", | |
458 | "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31", | |
459 | "mq", "lr", "ctr", "ap", | |
460 | "%cr0", "%cr1", "%cr2", "%cr3", "%cr4", "%cr5", "%cr6", "%cr7", | |
0ac081f6 | 461 | "xer", |
59a4c851 | 462 | /* AltiVec registers. */ |
0ac081f6 | 463 | "%v0", "%v1", "%v2", "%v3", "%v4", "%v5", "%v6", "%v7", |
59a4c851 AH |
464 | "%v8", "%v9", "%v10", "%v11", "%v12", "%v13", "%v14", "%v15", |
465 | "%v16", "%v17", "%v18", "%v19", "%v20", "%v21", "%v22", "%v23", | |
466 | "%v24", "%v25", "%v26", "%v27", "%v28", "%v29", "%v30", "%v31", | |
467 | "vrsave", "vscr", | |
468 | /* SPE registers. */ | |
469 | "spe_acc", "spefscr" | |
c81bebd7 MM |
470 | }; |
471 | #endif | |
9878760c | 472 | \f |
daf11973 MM |
473 | #ifndef MASK_STRICT_ALIGN |
474 | #define MASK_STRICT_ALIGN 0 | |
475 | #endif | |
ffcfcb5f AM |
476 | #ifndef TARGET_PROFILE_KERNEL |
477 | #define TARGET_PROFILE_KERNEL 0 | |
478 | #endif | |
3961e8fe RH |
479 | |
480 | /* The VRSAVE bitmask puts bit %v0 as the most significant bit. */ | |
481 | #define ALTIVEC_REG_BIT(REGNO) (0x80000000 >> ((REGNO) - FIRST_ALTIVEC_REGNO)) | |
c4501e62 JJ |
482 | |
483 | /* Return 1 for a symbol ref for a thread-local storage symbol. */ | |
484 | #define RS6000_SYMBOL_REF_TLS_P(RTX) \ | |
485 | (GET_CODE (RTX) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (RTX) != 0) | |
672a6f42 NB |
486 | \f |
487 | /* Initialize the GCC target structure. */ | |
91d231cb JM |
488 | #undef TARGET_ATTRIBUTE_TABLE |
489 | #define TARGET_ATTRIBUTE_TABLE rs6000_attribute_table | |
a5c76ee6 ZW |
490 | #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES |
491 | #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES rs6000_set_default_type_attributes | |
daf11973 | 492 | |
301d03af RS |
493 | #undef TARGET_ASM_ALIGNED_DI_OP |
494 | #define TARGET_ASM_ALIGNED_DI_OP DOUBLE_INT_ASM_OP | |
495 | ||
496 | /* Default unaligned ops are only provided for ELF. Find the ops needed | |
497 | for non-ELF systems. */ | |
498 | #ifndef OBJECT_FORMAT_ELF | |
cbaaba19 | 499 | #if TARGET_XCOFF |
ae6c1efd | 500 | /* For XCOFF. rs6000_assemble_integer will handle unaligned DIs on |
301d03af RS |
501 | 64-bit targets. */ |
502 | #undef TARGET_ASM_UNALIGNED_HI_OP | |
503 | #define TARGET_ASM_UNALIGNED_HI_OP "\t.vbyte\t2," | |
504 | #undef TARGET_ASM_UNALIGNED_SI_OP | |
505 | #define TARGET_ASM_UNALIGNED_SI_OP "\t.vbyte\t4," | |
506 | #undef TARGET_ASM_UNALIGNED_DI_OP | |
507 | #define TARGET_ASM_UNALIGNED_DI_OP "\t.vbyte\t8," | |
508 | #else | |
509 | /* For Darwin. */ | |
510 | #undef TARGET_ASM_UNALIGNED_HI_OP | |
511 | #define TARGET_ASM_UNALIGNED_HI_OP "\t.short\t" | |
512 | #undef TARGET_ASM_UNALIGNED_SI_OP | |
513 | #define TARGET_ASM_UNALIGNED_SI_OP "\t.long\t" | |
514 | #endif | |
515 | #endif | |
516 | ||
517 | /* This hook deals with fixups for relocatable code and DI-mode objects | |
518 | in 64-bit code. */ | |
519 | #undef TARGET_ASM_INTEGER | |
520 | #define TARGET_ASM_INTEGER rs6000_assemble_integer | |
521 | ||
93638d7a AM |
522 | #ifdef HAVE_GAS_HIDDEN |
523 | #undef TARGET_ASM_ASSEMBLE_VISIBILITY | |
524 | #define TARGET_ASM_ASSEMBLE_VISIBILITY rs6000_assemble_visibility | |
525 | #endif | |
526 | ||
c4501e62 JJ |
527 | #undef TARGET_HAVE_TLS |
528 | #define TARGET_HAVE_TLS HAVE_AS_TLS | |
529 | ||
530 | #undef TARGET_CANNOT_FORCE_CONST_MEM | |
531 | #define TARGET_CANNOT_FORCE_CONST_MEM rs6000_tls_referenced_p | |
532 | ||
08c148a8 NB |
533 | #undef TARGET_ASM_FUNCTION_PROLOGUE |
534 | #define TARGET_ASM_FUNCTION_PROLOGUE rs6000_output_function_prologue | |
535 | #undef TARGET_ASM_FUNCTION_EPILOGUE | |
536 | #define TARGET_ASM_FUNCTION_EPILOGUE rs6000_output_function_epilogue | |
537 | ||
b54cf83a DE |
538 | #undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE |
539 | #define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE rs6000_use_dfa_pipeline_interface | |
b54cf83a DE |
540 | #undef TARGET_SCHED_VARIABLE_ISSUE |
541 | #define TARGET_SCHED_VARIABLE_ISSUE rs6000_variable_issue | |
542 | ||
c237e94a ZW |
543 | #undef TARGET_SCHED_ISSUE_RATE |
544 | #define TARGET_SCHED_ISSUE_RATE rs6000_issue_rate | |
545 | #undef TARGET_SCHED_ADJUST_COST | |
546 | #define TARGET_SCHED_ADJUST_COST rs6000_adjust_cost | |
547 | #undef TARGET_SCHED_ADJUST_PRIORITY | |
548 | #define TARGET_SCHED_ADJUST_PRIORITY rs6000_adjust_priority | |
569fa502 DN |
549 | #undef TARGET_SCHED_IS_COSTLY_DEPENDENCE |
550 | #define TARGET_SCHED_IS_COSTLY_DEPENDENCE rs6000_is_costly_dependence | |
cbe26ab8 DN |
551 | #undef TARGET_SCHED_FINISH |
552 | #define TARGET_SCHED_FINISH rs6000_sched_finish | |
c237e94a | 553 | |
be12c2b0 VM |
554 | #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD |
555 | #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD rs6000_use_sched_lookahead | |
556 | ||
0ac081f6 AH |
557 | #undef TARGET_INIT_BUILTINS |
558 | #define TARGET_INIT_BUILTINS rs6000_init_builtins | |
559 | ||
560 | #undef TARGET_EXPAND_BUILTIN | |
561 | #define TARGET_EXPAND_BUILTIN rs6000_expand_builtin | |
562 | ||
c15c90bb ZW |
563 | #undef TARGET_INIT_LIBFUNCS |
564 | #define TARGET_INIT_LIBFUNCS rs6000_init_libfuncs | |
565 | ||
f1384257 | 566 | #if TARGET_MACHO |
0e5dbd9b DE |
567 | #undef TARGET_BINDS_LOCAL_P |
568 | #define TARGET_BINDS_LOCAL_P rs6000_binds_local_p | |
f1384257 | 569 | #endif |
0e5dbd9b | 570 | |
3961e8fe RH |
571 | #undef TARGET_ASM_OUTPUT_MI_THUNK |
572 | #define TARGET_ASM_OUTPUT_MI_THUNK rs6000_output_mi_thunk | |
573 | ||
3961e8fe | 574 | #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK |
5b71a4e7 | 575 | #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_tree_hwi_hwi_tree_true |
00b960c7 | 576 | |
4977bab6 ZW |
577 | #undef TARGET_FUNCTION_OK_FOR_SIBCALL |
578 | #define TARGET_FUNCTION_OK_FOR_SIBCALL rs6000_function_ok_for_sibcall | |
579 | ||
3c50106f RH |
580 | #undef TARGET_RTX_COSTS |
581 | #define TARGET_RTX_COSTS rs6000_rtx_costs | |
dcefdf67 RH |
582 | #undef TARGET_ADDRESS_COST |
583 | #define TARGET_ADDRESS_COST hook_int_rtx_0 | |
3c50106f | 584 | |
c8e4f0e9 AH |
585 | #undef TARGET_VECTOR_OPAQUE_P |
586 | #define TARGET_VECTOR_OPAQUE_P is_ev64_opaque_type | |
62e1dfcf | 587 | |
96714395 AH |
588 | #undef TARGET_DWARF_REGISTER_SPAN |
589 | #define TARGET_DWARF_REGISTER_SPAN rs6000_dwarf_register_span | |
590 | ||
c6e8c921 GK |
591 | /* On rs6000, function arguments are promoted, as are function return |
592 | values. */ | |
593 | #undef TARGET_PROMOTE_FUNCTION_ARGS | |
594 | #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true | |
595 | #undef TARGET_PROMOTE_FUNCTION_RETURN | |
596 | #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true | |
597 | ||
c6e8c921 GK |
598 | #undef TARGET_RETURN_IN_MEMORY |
599 | #define TARGET_RETURN_IN_MEMORY rs6000_return_in_memory | |
600 | ||
601 | #undef TARGET_SETUP_INCOMING_VARARGS | |
602 | #define TARGET_SETUP_INCOMING_VARARGS setup_incoming_varargs | |
603 | ||
604 | /* Always strict argument naming on rs6000. */ | |
605 | #undef TARGET_STRICT_ARGUMENT_NAMING | |
606 | #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true | |
607 | #undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED | |
608 | #define TARGET_PRETEND_OUTGOING_VARARGS_NAMED hook_bool_CUMULATIVE_ARGS_true | |
609 | ||
c35d187f RH |
610 | #undef TARGET_BUILD_BUILTIN_VA_LIST |
611 | #define TARGET_BUILD_BUILTIN_VA_LIST rs6000_build_builtin_va_list | |
612 | ||
f6897b10 | 613 | struct gcc_target targetm = TARGET_INITIALIZER; |
672a6f42 | 614 | \f |
5248c961 RK |
615 | /* Override command line options. Mostly we process the processor |
616 | type and sometimes adjust other TARGET_ options. */ | |
617 | ||
618 | void | |
d779d0dc | 619 | rs6000_override_options (const char *default_cpu) |
5248c961 | 620 | { |
c4d38ccb | 621 | size_t i, j; |
8e3f41e7 | 622 | struct rs6000_cpu_select *ptr; |
66188a7e | 623 | int set_masks; |
5248c961 | 624 | |
66188a7e | 625 | /* Simplifications for entries below. */ |
85638c0d | 626 | |
66188a7e GK |
627 | enum { |
628 | POWERPC_BASE_MASK = MASK_POWERPC | MASK_NEW_MNEMONICS, | |
629 | POWERPC_7400_MASK = POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_ALTIVEC | |
630 | }; | |
85638c0d | 631 | |
66188a7e GK |
632 | /* This table occasionally claims that a processor does not support |
633 | a particular feature even though it does, but the feature is slower | |
634 | than the alternative. Thus, it shouldn't be relied on as a | |
635 | complete description of the processor's support. | |
636 | ||
637 | Please keep this list in order, and don't forget to update the | |
638 | documentation in invoke.texi when adding a new processor or | |
639 | flag. */ | |
5248c961 RK |
640 | static struct ptt |
641 | { | |
8b60264b KG |
642 | const char *const name; /* Canonical processor name. */ |
643 | const enum processor_type processor; /* Processor type enum value. */ | |
644 | const int target_enable; /* Target flags to enable. */ | |
8b60264b | 645 | } const processor_target_table[] |
66188a7e | 646 | = {{"401", PROCESSOR_PPC403, POWERPC_BASE_MASK | MASK_SOFT_FLOAT}, |
49a0b204 | 647 | {"403", PROCESSOR_PPC403, |
66188a7e GK |
648 | POWERPC_BASE_MASK | MASK_SOFT_FLOAT | MASK_STRICT_ALIGN}, |
649 | {"405", PROCESSOR_PPC405, POWERPC_BASE_MASK | MASK_SOFT_FLOAT}, | |
650 | {"405fp", PROCESSOR_PPC405, POWERPC_BASE_MASK}, | |
651 | {"440", PROCESSOR_PPC440, POWERPC_BASE_MASK | MASK_SOFT_FLOAT}, | |
652 | {"440fp", PROCESSOR_PPC440, POWERPC_BASE_MASK}, | |
653 | {"505", PROCESSOR_MPCCORE, POWERPC_BASE_MASK}, | |
5248c961 | 654 | {"601", PROCESSOR_PPC601, |
66188a7e GK |
655 | MASK_POWER | POWERPC_BASE_MASK | MASK_MULTIPLE | MASK_STRING}, |
656 | {"602", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT}, | |
657 | {"603", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT}, | |
658 | {"603e", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT}, | |
659 | {"604", PROCESSOR_PPC604, POWERPC_BASE_MASK | MASK_PPC_GFXOPT}, | |
660 | {"604e", PROCESSOR_PPC604e, POWERPC_BASE_MASK | MASK_PPC_GFXOPT}, | |
7ddb6568 AM |
661 | {"620", PROCESSOR_PPC620, |
662 | POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64}, | |
663 | {"630", PROCESSOR_PPC630, | |
664 | POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64}, | |
66188a7e GK |
665 | {"740", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT}, |
666 | {"7400", PROCESSOR_PPC7400, POWERPC_7400_MASK}, | |
667 | {"7450", PROCESSOR_PPC7450, POWERPC_7400_MASK}, | |
668 | {"750", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT}, | |
669 | {"801", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT}, | |
670 | {"821", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT}, | |
671 | {"823", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT}, | |
672 | {"8540", PROCESSOR_PPC8540, POWERPC_BASE_MASK | MASK_PPC_GFXOPT}, | |
673 | {"860", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT}, | |
7177e720 | 674 | {"970", PROCESSOR_POWER4, |
66188a7e GK |
675 | POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64}, |
676 | {"common", PROCESSOR_COMMON, MASK_NEW_MNEMONICS}, | |
677 | {"ec603e", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_SOFT_FLOAT}, | |
678 | {"G3", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT}, | |
679 | {"G4", PROCESSOR_PPC7450, POWERPC_7400_MASK}, | |
49ffe578 | 680 | {"G5", PROCESSOR_POWER4, |
66188a7e GK |
681 | POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64}, |
682 | {"power", PROCESSOR_POWER, MASK_POWER | MASK_MULTIPLE | MASK_STRING}, | |
683 | {"power2", PROCESSOR_POWER, | |
684 | MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING}, | |
7ddb6568 AM |
685 | {"power3", PROCESSOR_PPC630, |
686 | POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64}, | |
687 | {"power4", PROCESSOR_POWER4, | |
688 | POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64}, | |
66188a7e GK |
689 | {"powerpc", PROCESSOR_POWERPC, POWERPC_BASE_MASK}, |
690 | {"powerpc64", PROCESSOR_POWERPC64, | |
691 | POWERPC_BASE_MASK | MASK_POWERPC64}, | |
692 | {"rios", PROCESSOR_RIOS1, MASK_POWER | MASK_MULTIPLE | MASK_STRING}, | |
693 | {"rios1", PROCESSOR_RIOS1, MASK_POWER | MASK_MULTIPLE | MASK_STRING}, | |
694 | {"rios2", PROCESSOR_RIOS2, | |
695 | MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING}, | |
696 | {"rsc", PROCESSOR_PPC601, MASK_POWER | MASK_MULTIPLE | MASK_STRING}, | |
697 | {"rsc1", PROCESSOR_PPC601, MASK_POWER | MASK_MULTIPLE | MASK_STRING}, | |
7ddb6568 | 698 | {"rs64a", PROCESSOR_RS64A, POWERPC_BASE_MASK | MASK_POWERPC64}, |
66188a7e | 699 | }; |
5248c961 | 700 | |
ca7558fc | 701 | const size_t ptt_size = ARRAY_SIZE (processor_target_table); |
5248c961 | 702 | |
a4f6c312 SS |
703 | /* Save current -mmultiple/-mno-multiple status. */ |
704 | int multiple = TARGET_MULTIPLE; | |
705 | /* Save current -mstring/-mno-string status. */ | |
706 | int string = TARGET_STRING; | |
8a61d227 | 707 | |
66188a7e GK |
708 | /* Some OSs don't support saving the high part of 64-bit registers on |
709 | context switch. Other OSs don't support saving Altivec registers. | |
710 | On those OSs, we don't touch the MASK_POWERPC64 or MASK_ALTIVEC | |
711 | settings; if the user wants either, the user must explicitly specify | |
712 | them and we won't interfere with the user's specification. */ | |
713 | ||
714 | enum { | |
715 | POWER_MASKS = MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING, | |
716 | POWERPC_MASKS = (POWERPC_BASE_MASK | MASK_PPC_GPOPT | |
717 | | MASK_PPC_GFXOPT | MASK_POWERPC64 | MASK_ALTIVEC | |
718 | | MASK_MFCRF) | |
719 | }; | |
720 | set_masks = POWER_MASKS | POWERPC_MASKS | MASK_SOFT_FLOAT; | |
721 | #ifdef OS_MISSING_POWERPC64 | |
722 | if (OS_MISSING_POWERPC64) | |
723 | set_masks &= ~MASK_POWERPC64; | |
724 | #endif | |
725 | #ifdef OS_MISSING_ALTIVEC | |
726 | if (OS_MISSING_ALTIVEC) | |
727 | set_masks &= ~MASK_ALTIVEC; | |
728 | #endif | |
729 | ||
a4f6c312 | 730 | /* Identify the processor type. */ |
8e3f41e7 | 731 | rs6000_select[0].string = default_cpu; |
3cb999d8 | 732 | rs6000_cpu = TARGET_POWERPC64 ? PROCESSOR_DEFAULT64 : PROCESSOR_DEFAULT; |
8e3f41e7 | 733 | |
b6a1cbae | 734 | for (i = 0; i < ARRAY_SIZE (rs6000_select); i++) |
5248c961 | 735 | { |
8e3f41e7 MM |
736 | ptr = &rs6000_select[i]; |
737 | if (ptr->string != (char *)0 && ptr->string[0] != '\0') | |
5248c961 | 738 | { |
8e3f41e7 MM |
739 | for (j = 0; j < ptt_size; j++) |
740 | if (! strcmp (ptr->string, processor_target_table[j].name)) | |
741 | { | |
742 | if (ptr->set_tune_p) | |
743 | rs6000_cpu = processor_target_table[j].processor; | |
744 | ||
745 | if (ptr->set_arch_p) | |
746 | { | |
66188a7e GK |
747 | target_flags &= ~set_masks; |
748 | target_flags |= (processor_target_table[j].target_enable | |
749 | & set_masks); | |
8e3f41e7 MM |
750 | } |
751 | break; | |
752 | } | |
753 | ||
4406229e | 754 | if (j == ptt_size) |
8e3f41e7 | 755 | error ("bad value (%s) for %s switch", ptr->string, ptr->name); |
5248c961 RK |
756 | } |
757 | } | |
8a61d227 | 758 | |
993f19a8 | 759 | if (TARGET_E500) |
a3170dc6 AH |
760 | rs6000_isel = 1; |
761 | ||
dff9f1b6 DE |
762 | /* If we are optimizing big endian systems for space, use the load/store |
763 | multiple and string instructions. */ | |
ef792183 | 764 | if (BYTES_BIG_ENDIAN && optimize_size) |
dff9f1b6 | 765 | target_flags |= MASK_MULTIPLE | MASK_STRING; |
ef792183 | 766 | |
8a61d227 MM |
767 | /* If -mmultiple or -mno-multiple was explicitly used, don't |
768 | override with the processor default */ | |
b21fb038 | 769 | if ((target_flags_explicit & MASK_MULTIPLE) != 0) |
8a61d227 | 770 | target_flags = (target_flags & ~MASK_MULTIPLE) | multiple; |
7e69e155 | 771 | |
a4f6c312 SS |
772 | /* If -mstring or -mno-string was explicitly used, don't override |
773 | with the processor default. */ | |
b21fb038 | 774 | if ((target_flags_explicit & MASK_STRING) != 0) |
1f5515bf | 775 | target_flags = (target_flags & ~MASK_STRING) | string; |
938937d8 | 776 | |
a4f6c312 SS |
777 | /* Don't allow -mmultiple or -mstring on little endian systems |
778 | unless the cpu is a 750, because the hardware doesn't support the | |
779 | instructions used in little endian mode, and causes an alignment | |
780 | trap. The 750 does not cause an alignment trap (except when the | |
781 | target is unaligned). */ | |
bef84347 | 782 | |
b21fb038 | 783 | if (!BYTES_BIG_ENDIAN && rs6000_cpu != PROCESSOR_PPC750) |
7e69e155 MM |
784 | { |
785 | if (TARGET_MULTIPLE) | |
786 | { | |
787 | target_flags &= ~MASK_MULTIPLE; | |
b21fb038 | 788 | if ((target_flags_explicit & MASK_MULTIPLE) != 0) |
7e69e155 MM |
789 | warning ("-mmultiple is not supported on little endian systems"); |
790 | } | |
791 | ||
792 | if (TARGET_STRING) | |
793 | { | |
794 | target_flags &= ~MASK_STRING; | |
b21fb038 | 795 | if ((target_flags_explicit & MASK_STRING) != 0) |
938937d8 | 796 | warning ("-mstring is not supported on little endian systems"); |
7e69e155 MM |
797 | } |
798 | } | |
3933e0e1 | 799 | |
38c1f2d7 MM |
800 | /* Set debug flags */ |
801 | if (rs6000_debug_name) | |
802 | { | |
bfc79d3b | 803 | if (! strcmp (rs6000_debug_name, "all")) |
38c1f2d7 | 804 | rs6000_debug_stack = rs6000_debug_arg = 1; |
bfc79d3b | 805 | else if (! strcmp (rs6000_debug_name, "stack")) |
38c1f2d7 | 806 | rs6000_debug_stack = 1; |
bfc79d3b | 807 | else if (! strcmp (rs6000_debug_name, "arg")) |
38c1f2d7 MM |
808 | rs6000_debug_arg = 1; |
809 | else | |
c725bd79 | 810 | error ("unknown -mdebug-%s switch", rs6000_debug_name); |
38c1f2d7 MM |
811 | } |
812 | ||
57ac7be9 AM |
813 | if (rs6000_traceback_name) |
814 | { | |
815 | if (! strncmp (rs6000_traceback_name, "full", 4)) | |
816 | rs6000_traceback = traceback_full; | |
817 | else if (! strncmp (rs6000_traceback_name, "part", 4)) | |
818 | rs6000_traceback = traceback_part; | |
819 | else if (! strncmp (rs6000_traceback_name, "no", 2)) | |
820 | rs6000_traceback = traceback_none; | |
821 | else | |
822 | error ("unknown -mtraceback arg `%s'; expecting `full', `partial' or `none'", | |
823 | rs6000_traceback_name); | |
824 | } | |
825 | ||
6fa3f289 ZW |
826 | /* Set size of long double */ |
827 | rs6000_long_double_type_size = 64; | |
828 | if (rs6000_long_double_size_string) | |
829 | { | |
830 | char *tail; | |
831 | int size = strtol (rs6000_long_double_size_string, &tail, 10); | |
832 | if (*tail != '\0' || (size != 64 && size != 128)) | |
833 | error ("Unknown switch -mlong-double-%s", | |
834 | rs6000_long_double_size_string); | |
835 | else | |
836 | rs6000_long_double_type_size = size; | |
837 | } | |
838 | ||
0ac081f6 AH |
839 | /* Handle -mabi= options. */ |
840 | rs6000_parse_abi_options (); | |
841 | ||
025d9908 KH |
842 | /* Handle -malign-XXXXX option. */ |
843 | rs6000_parse_alignment_option (); | |
844 | ||
5da702b1 AH |
845 | /* Handle generic -mFOO=YES/NO options. */ |
846 | rs6000_parse_yes_no_option ("vrsave", rs6000_altivec_vrsave_string, | |
847 | &rs6000_altivec_vrsave); | |
848 | rs6000_parse_yes_no_option ("isel", rs6000_isel_string, | |
849 | &rs6000_isel); | |
850 | rs6000_parse_yes_no_option ("spe", rs6000_spe_string, &rs6000_spe); | |
851 | rs6000_parse_yes_no_option ("float-gprs", rs6000_float_gprs_string, | |
852 | &rs6000_float_gprs); | |
993f19a8 | 853 | |
c4501e62 JJ |
854 | /* Handle -mtls-size option. */ |
855 | rs6000_parse_tls_size_option (); | |
856 | ||
a7ae18e2 AH |
857 | #ifdef SUBTARGET_OVERRIDE_OPTIONS |
858 | SUBTARGET_OVERRIDE_OPTIONS; | |
859 | #endif | |
860 | #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS | |
861 | SUBSUBTARGET_OVERRIDE_OPTIONS; | |
862 | #endif | |
863 | ||
5da702b1 AH |
864 | if (TARGET_E500) |
865 | { | |
866 | /* The e500 does not have string instructions, and we set | |
867 | MASK_STRING above when optimizing for size. */ | |
868 | if ((target_flags & MASK_STRING) != 0) | |
869 | target_flags = target_flags & ~MASK_STRING; | |
b6e59a3a AH |
870 | |
871 | /* No SPE means 64-bit long doubles, even if an E500. */ | |
872 | if (rs6000_spe_string != 0 | |
873 | && !strcmp (rs6000_spe_string, "no")) | |
874 | rs6000_long_double_type_size = 64; | |
5da702b1 AH |
875 | } |
876 | else if (rs6000_select[1].string != NULL) | |
877 | { | |
878 | /* For the powerpc-eabispe configuration, we set all these by | |
879 | default, so let's unset them if we manually set another | |
880 | CPU that is not the E500. */ | |
881 | if (rs6000_abi_string == 0) | |
882 | rs6000_spe_abi = 0; | |
883 | if (rs6000_spe_string == 0) | |
884 | rs6000_spe = 0; | |
885 | if (rs6000_float_gprs_string == 0) | |
886 | rs6000_float_gprs = 0; | |
887 | if (rs6000_isel_string == 0) | |
888 | rs6000_isel = 0; | |
b6e59a3a AH |
889 | if (rs6000_long_double_size_string == 0) |
890 | rs6000_long_double_type_size = 64; | |
5da702b1 | 891 | } |
b5044283 | 892 | |
a5c76ee6 ZW |
893 | /* Handle -m(no-)longcall option. This is a bit of a cheap hack, |
894 | using TARGET_OPTIONS to handle a toggle switch, but we're out of | |
895 | bits in target_flags so TARGET_SWITCHES cannot be used. | |
896 | Assumption here is that rs6000_longcall_switch points into the | |
897 | text of the complete option, rather than being a copy, so we can | |
898 | scan back for the presence or absence of the no- modifier. */ | |
899 | if (rs6000_longcall_switch) | |
900 | { | |
901 | const char *base = rs6000_longcall_switch; | |
902 | while (base[-1] != 'm') base--; | |
903 | ||
904 | if (*rs6000_longcall_switch != '\0') | |
905 | error ("invalid option `%s'", base); | |
906 | rs6000_default_long_calls = (base[0] != 'n'); | |
907 | } | |
908 | ||
cbe26ab8 | 909 | /* Handle -mprioritize-restricted-insns option. */ |
79ae11c4 DN |
910 | rs6000_sched_restricted_insns_priority = DEFAULT_RESTRICTED_INSNS_PRIORITY; |
911 | if (rs6000_sched_restricted_insns_priority_str) | |
912 | rs6000_sched_restricted_insns_priority = | |
913 | atoi (rs6000_sched_restricted_insns_priority_str); | |
914 | ||
569fa502 DN |
915 | /* Handle -msched-costly-dep option. */ |
916 | rs6000_sched_costly_dep = DEFAULT_SCHED_COSTLY_DEP; | |
917 | if (rs6000_sched_costly_dep_str) | |
918 | { | |
919 | if (! strcmp (rs6000_sched_costly_dep_str, "no")) | |
920 | rs6000_sched_costly_dep = no_dep_costly; | |
921 | else if (! strcmp (rs6000_sched_costly_dep_str, "all")) | |
922 | rs6000_sched_costly_dep = all_deps_costly; | |
923 | else if (! strcmp (rs6000_sched_costly_dep_str, "true_store_to_load")) | |
924 | rs6000_sched_costly_dep = true_store_to_load_dep_costly; | |
925 | else if (! strcmp (rs6000_sched_costly_dep_str, "store_to_load")) | |
926 | rs6000_sched_costly_dep = store_to_load_dep_costly; | |
cbe26ab8 DN |
927 | else |
928 | rs6000_sched_costly_dep = atoi (rs6000_sched_costly_dep_str); | |
929 | } | |
930 | ||
931 | /* Handle -minsert-sched-nops option. */ | |
932 | rs6000_sched_insert_nops = DEFAULT_SCHED_FINISH_NOP_INSERTION_SCHEME; | |
933 | if (rs6000_sched_insert_nops_str) | |
934 | { | |
935 | if (! strcmp (rs6000_sched_insert_nops_str, "no")) | |
936 | rs6000_sched_insert_nops = sched_finish_none; | |
937 | else if (! strcmp (rs6000_sched_insert_nops_str, "pad")) | |
938 | rs6000_sched_insert_nops = sched_finish_pad_groups; | |
939 | else if (! strcmp (rs6000_sched_insert_nops_str, "regroup_exact")) | |
940 | rs6000_sched_insert_nops = sched_finish_regroup_exact; | |
941 | else | |
942 | rs6000_sched_insert_nops = atoi (rs6000_sched_insert_nops_str); | |
569fa502 DN |
943 | } |
944 | ||
c81bebd7 | 945 | #ifdef TARGET_REGNAMES |
a4f6c312 SS |
946 | /* If the user desires alternate register names, copy in the |
947 | alternate names now. */ | |
c81bebd7 | 948 | if (TARGET_REGNAMES) |
4e135bdd | 949 | memcpy (rs6000_reg_names, alt_reg_names, sizeof (rs6000_reg_names)); |
c81bebd7 MM |
950 | #endif |
951 | ||
6fa3f289 ZW |
952 | /* Set TARGET_AIX_STRUCT_RET last, after the ABI is determined. |
953 | If -maix-struct-return or -msvr4-struct-return was explicitly | |
954 | used, don't override with the ABI default. */ | |
b21fb038 | 955 | if ((target_flags_explicit & MASK_AIX_STRUCT_RET) == 0) |
6fa3f289 ZW |
956 | { |
957 | if (DEFAULT_ABI == ABI_V4 && !DRAFT_V4_STRUCT_RET) | |
958 | target_flags = (target_flags & ~MASK_AIX_STRUCT_RET); | |
959 | else | |
960 | target_flags |= MASK_AIX_STRUCT_RET; | |
961 | } | |
962 | ||
fcce224d DE |
963 | if (TARGET_LONG_DOUBLE_128 |
964 | && (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)) | |
70a01792 | 965 | REAL_MODE_FORMAT (TFmode) = &ibm_extended_format; |
fcce224d | 966 | |
9ebbca7d GK |
967 | /* Allocate an alias set for register saves & restores from stack. */ |
968 | rs6000_sr_alias_set = new_alias_set (); | |
969 | ||
970 | if (TARGET_TOC) | |
971 | ASM_GENERATE_INTERNAL_LABEL (toc_label_name, "LCTOC", 1); | |
71f123ca | 972 | |
301d03af RS |
973 | /* We can only guarantee the availability of DI pseudo-ops when |
974 | assembling for 64-bit targets. */ | |
ae6c1efd | 975 | if (!TARGET_64BIT) |
301d03af RS |
976 | { |
977 | targetm.asm_out.aligned_op.di = NULL; | |
978 | targetm.asm_out.unaligned_op.di = NULL; | |
979 | } | |
980 | ||
2792d578 DE |
981 | /* Set maximum branch target alignment at two instructions, eight bytes. */ |
982 | align_jumps_max_skip = 8; | |
983 | align_loops_max_skip = 8; | |
984 | ||
71f123ca FS |
985 | /* Arrange to save and restore machine status around nested functions. */ |
986 | init_machine_status = rs6000_init_machine_status; | |
5248c961 | 987 | } |
5accd822 | 988 | |
5da702b1 AH |
989 | /* Handle generic options of the form -mfoo=yes/no. |
990 | NAME is the option name. | |
991 | VALUE is the option value. | |
992 | FLAG is the pointer to the flag where to store a 1 or 0, depending on | |
993 | whether the option value is 'yes' or 'no' respectively. */ | |
993f19a8 | 994 | static void |
5da702b1 | 995 | rs6000_parse_yes_no_option (const char *name, const char *value, int *flag) |
993f19a8 | 996 | { |
5da702b1 | 997 | if (value == 0) |
993f19a8 | 998 | return; |
5da702b1 AH |
999 | else if (!strcmp (value, "yes")) |
1000 | *flag = 1; | |
1001 | else if (!strcmp (value, "no")) | |
1002 | *flag = 0; | |
08b57fb3 | 1003 | else |
5da702b1 | 1004 | error ("unknown -m%s= option specified: '%s'", name, value); |
08b57fb3 AH |
1005 | } |
1006 | ||
0ac081f6 | 1007 | /* Handle -mabi= options. */ |
00b960c7 | 1008 | static void |
863d938c | 1009 | rs6000_parse_abi_options (void) |
0ac081f6 AH |
1010 | { |
1011 | if (rs6000_abi_string == 0) | |
1012 | return; | |
1013 | else if (! strcmp (rs6000_abi_string, "altivec")) | |
6fa3f289 | 1014 | rs6000_altivec_abi = 1; |
76a773f3 AH |
1015 | else if (! strcmp (rs6000_abi_string, "no-altivec")) |
1016 | rs6000_altivec_abi = 0; | |
a3170dc6 | 1017 | else if (! strcmp (rs6000_abi_string, "spe")) |
01f4962d NS |
1018 | { |
1019 | rs6000_spe_abi = 1; | |
1020 | if (!TARGET_SPE_ABI) | |
1021 | error ("not configured for ABI: '%s'", rs6000_abi_string); | |
1022 | } | |
1023 | ||
a3170dc6 AH |
1024 | else if (! strcmp (rs6000_abi_string, "no-spe")) |
1025 | rs6000_spe_abi = 0; | |
0ac081f6 | 1026 | else |
c725bd79 | 1027 | error ("unknown ABI specified: '%s'", rs6000_abi_string); |
0ac081f6 AH |
1028 | } |
1029 | ||
025d9908 KH |
1030 | /* Handle -malign-XXXXXX options. */ |
1031 | static void | |
863d938c | 1032 | rs6000_parse_alignment_option (void) |
025d9908 | 1033 | { |
b20a9cca AM |
1034 | if (rs6000_alignment_string == 0) |
1035 | return; | |
1036 | else if (! strcmp (rs6000_alignment_string, "power")) | |
025d9908 KH |
1037 | rs6000_alignment_flags = MASK_ALIGN_POWER; |
1038 | else if (! strcmp (rs6000_alignment_string, "natural")) | |
1039 | rs6000_alignment_flags = MASK_ALIGN_NATURAL; | |
1040 | else | |
1041 | error ("unknown -malign-XXXXX option specified: '%s'", | |
1042 | rs6000_alignment_string); | |
1043 | } | |
1044 | ||
c4501e62 JJ |
1045 | /* Validate and record the size specified with the -mtls-size option. */ |
1046 | ||
1047 | static void | |
863d938c | 1048 | rs6000_parse_tls_size_option (void) |
c4501e62 JJ |
1049 | { |
1050 | if (rs6000_tls_size_string == 0) | |
1051 | return; | |
1052 | else if (strcmp (rs6000_tls_size_string, "16") == 0) | |
1053 | rs6000_tls_size = 16; | |
1054 | else if (strcmp (rs6000_tls_size_string, "32") == 0) | |
1055 | rs6000_tls_size = 32; | |
1056 | else if (strcmp (rs6000_tls_size_string, "64") == 0) | |
1057 | rs6000_tls_size = 64; | |
1058 | else | |
1059 | error ("bad value `%s' for -mtls-size switch", rs6000_tls_size_string); | |
1060 | } | |
1061 | ||
5accd822 | 1062 | void |
a2369ed3 | 1063 | optimization_options (int level ATTRIBUTE_UNUSED, int size ATTRIBUTE_UNUSED) |
5accd822 | 1064 | { |
5accd822 | 1065 | } |
3cfa4909 MM |
1066 | \f |
1067 | /* Do anything needed at the start of the asm file. */ | |
1068 | ||
1bc7c5b6 | 1069 | static void |
863d938c | 1070 | rs6000_file_start (void) |
3cfa4909 | 1071 | { |
c4d38ccb | 1072 | size_t i; |
3cfa4909 | 1073 | char buffer[80]; |
d330fd93 | 1074 | const char *start = buffer; |
3cfa4909 | 1075 | struct rs6000_cpu_select *ptr; |
1bc7c5b6 ZW |
1076 | const char *default_cpu = TARGET_CPU_DEFAULT; |
1077 | FILE *file = asm_out_file; | |
1078 | ||
1079 | default_file_start (); | |
1080 | ||
1081 | #ifdef TARGET_BI_ARCH | |
1082 | if ((TARGET_DEFAULT ^ target_flags) & MASK_64BIT) | |
1083 | default_cpu = 0; | |
1084 | #endif | |
3cfa4909 MM |
1085 | |
1086 | if (flag_verbose_asm) | |
1087 | { | |
1088 | sprintf (buffer, "\n%s rs6000/powerpc options:", ASM_COMMENT_START); | |
1089 | rs6000_select[0].string = default_cpu; | |
1090 | ||
b6a1cbae | 1091 | for (i = 0; i < ARRAY_SIZE (rs6000_select); i++) |
3cfa4909 MM |
1092 | { |
1093 | ptr = &rs6000_select[i]; | |
1094 | if (ptr->string != (char *)0 && ptr->string[0] != '\0') | |
1095 | { | |
1096 | fprintf (file, "%s %s%s", start, ptr->name, ptr->string); | |
1097 | start = ""; | |
1098 | } | |
1099 | } | |
1100 | ||
b91da81f | 1101 | #ifdef USING_ELFOS_H |
3cfa4909 MM |
1102 | switch (rs6000_sdata) |
1103 | { | |
1104 | case SDATA_NONE: fprintf (file, "%s -msdata=none", start); start = ""; break; | |
1105 | case SDATA_DATA: fprintf (file, "%s -msdata=data", start); start = ""; break; | |
1106 | case SDATA_SYSV: fprintf (file, "%s -msdata=sysv", start); start = ""; break; | |
1107 | case SDATA_EABI: fprintf (file, "%s -msdata=eabi", start); start = ""; break; | |
1108 | } | |
1109 | ||
1110 | if (rs6000_sdata && g_switch_value) | |
1111 | { | |
307b599c MK |
1112 | fprintf (file, "%s -G " HOST_WIDE_INT_PRINT_UNSIGNED, start, |
1113 | g_switch_value); | |
3cfa4909 MM |
1114 | start = ""; |
1115 | } | |
1116 | #endif | |
1117 | ||
1118 | if (*start == '\0') | |
949ea356 | 1119 | putc ('\n', file); |
3cfa4909 MM |
1120 | } |
1121 | } | |
5248c961 | 1122 | \f |
a0ab749a | 1123 | /* Return nonzero if this function is known to have a null epilogue. */ |
9878760c RK |
1124 | |
1125 | int | |
863d938c | 1126 | direct_return (void) |
9878760c | 1127 | { |
4697a36c MM |
1128 | if (reload_completed) |
1129 | { | |
1130 | rs6000_stack_t *info = rs6000_stack_info (); | |
1131 | ||
1132 | if (info->first_gp_reg_save == 32 | |
1133 | && info->first_fp_reg_save == 64 | |
00b960c7 | 1134 | && info->first_altivec_reg_save == LAST_ALTIVEC_REGNO + 1 |
c81fc13e DE |
1135 | && ! info->lr_save_p |
1136 | && ! info->cr_save_p | |
00b960c7 | 1137 | && info->vrsave_mask == 0 |
c81fc13e | 1138 | && ! info->push_p) |
4697a36c MM |
1139 | return 1; |
1140 | } | |
1141 | ||
1142 | return 0; | |
9878760c RK |
1143 | } |
1144 | ||
1145 | /* Returns 1 always. */ | |
1146 | ||
1147 | int | |
a2369ed3 DJ |
1148 | any_operand (rtx op ATTRIBUTE_UNUSED, |
1149 | enum machine_mode mode ATTRIBUTE_UNUSED) | |
9878760c RK |
1150 | { |
1151 | return 1; | |
1152 | } | |
1153 | ||
a4f6c312 | 1154 | /* Returns 1 if op is the count register. */ |
38c1f2d7 | 1155 | int |
a2369ed3 | 1156 | count_register_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
b6c9286a MM |
1157 | { |
1158 | if (GET_CODE (op) != REG) | |
1159 | return 0; | |
1160 | ||
1161 | if (REGNO (op) == COUNT_REGISTER_REGNUM) | |
1162 | return 1; | |
1163 | ||
1164 | if (REGNO (op) > FIRST_PSEUDO_REGISTER) | |
1165 | return 1; | |
1166 | ||
1167 | return 0; | |
1168 | } | |
1169 | ||
0ec4e2a8 AH |
1170 | /* Returns 1 if op is an altivec register. */ |
1171 | int | |
a2369ed3 | 1172 | altivec_register_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
0ec4e2a8 AH |
1173 | { |
1174 | ||
1175 | return (register_operand (op, mode) | |
1176 | && (GET_CODE (op) != REG | |
1177 | || REGNO (op) > FIRST_PSEUDO_REGISTER | |
1178 | || ALTIVEC_REGNO_P (REGNO (op)))); | |
1179 | } | |
1180 | ||
38c1f2d7 | 1181 | int |
a2369ed3 | 1182 | xer_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
802a0058 MM |
1183 | { |
1184 | if (GET_CODE (op) != REG) | |
1185 | return 0; | |
1186 | ||
9ebbca7d | 1187 | if (XER_REGNO_P (REGNO (op))) |
802a0058 MM |
1188 | return 1; |
1189 | ||
802a0058 MM |
1190 | return 0; |
1191 | } | |
1192 | ||
c859cda6 | 1193 | /* Return 1 if OP is a signed 8-bit constant. Int multiplication |
6f317ef3 | 1194 | by such constants completes more quickly. */ |
c859cda6 DJ |
1195 | |
1196 | int | |
a2369ed3 | 1197 | s8bit_cint_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
c859cda6 DJ |
1198 | { |
1199 | return ( GET_CODE (op) == CONST_INT | |
1200 | && (INTVAL (op) >= -128 && INTVAL (op) <= 127)); | |
1201 | } | |
1202 | ||
9878760c RK |
1203 | /* Return 1 if OP is a constant that can fit in a D field. */ |
1204 | ||
1205 | int | |
a2369ed3 | 1206 | short_cint_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
9878760c | 1207 | { |
5f59ecb7 DE |
1208 | return (GET_CODE (op) == CONST_INT |
1209 | && CONST_OK_FOR_LETTER_P (INTVAL (op), 'I')); | |
9878760c RK |
1210 | } |
1211 | ||
5519a4f9 | 1212 | /* Similar for an unsigned D field. */ |
9878760c RK |
1213 | |
1214 | int | |
a2369ed3 | 1215 | u_short_cint_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
9878760c | 1216 | { |
19684119 | 1217 | return (GET_CODE (op) == CONST_INT |
c1f11548 | 1218 | && CONST_OK_FOR_LETTER_P (INTVAL (op) & GET_MODE_MASK (mode), 'K')); |
9878760c RK |
1219 | } |
1220 | ||
dcfedcd0 RK |
1221 | /* Return 1 if OP is a CONST_INT that cannot fit in a signed D field. */ |
1222 | ||
1223 | int | |
a2369ed3 | 1224 | non_short_cint_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
dcfedcd0 RK |
1225 | { |
1226 | return (GET_CODE (op) == CONST_INT | |
a7653a2c | 1227 | && (unsigned HOST_WIDE_INT) (INTVAL (op) + 0x8000) >= 0x10000); |
dcfedcd0 RK |
1228 | } |
1229 | ||
2bfcf297 DB |
1230 | /* Returns 1 if OP is a CONST_INT that is a positive value |
1231 | and an exact power of 2. */ | |
1232 | ||
1233 | int | |
a2369ed3 | 1234 | exact_log2_cint_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
2bfcf297 DB |
1235 | { |
1236 | return (GET_CODE (op) == CONST_INT | |
1237 | && INTVAL (op) > 0 | |
1238 | && exact_log2 (INTVAL (op)) >= 0); | |
1239 | } | |
1240 | ||
9878760c RK |
1241 | /* Returns 1 if OP is a register that is not special (i.e., not MQ, |
1242 | ctr, or lr). */ | |
1243 | ||
1244 | int | |
a2369ed3 | 1245 | gpc_reg_operand (rtx op, enum machine_mode mode) |
9878760c RK |
1246 | { |
1247 | return (register_operand (op, mode) | |
802a0058 | 1248 | && (GET_CODE (op) != REG |
9ebbca7d GK |
1249 | || (REGNO (op) >= ARG_POINTER_REGNUM |
1250 | && !XER_REGNO_P (REGNO (op))) | |
1251 | || REGNO (op) < MQ_REGNO)); | |
9878760c RK |
1252 | } |
1253 | ||
1254 | /* Returns 1 if OP is either a pseudo-register or a register denoting a | |
1255 | CR field. */ | |
1256 | ||
1257 | int | |
a2369ed3 | 1258 | cc_reg_operand (rtx op, enum machine_mode mode) |
9878760c RK |
1259 | { |
1260 | return (register_operand (op, mode) | |
1261 | && (GET_CODE (op) != REG | |
1262 | || REGNO (op) >= FIRST_PSEUDO_REGISTER | |
1263 | || CR_REGNO_P (REGNO (op)))); | |
1264 | } | |
1265 | ||
815cdc52 MM |
1266 | /* Returns 1 if OP is either a pseudo-register or a register denoting a |
1267 | CR field that isn't CR0. */ | |
1268 | ||
1269 | int | |
a2369ed3 | 1270 | cc_reg_not_cr0_operand (rtx op, enum machine_mode mode) |
815cdc52 MM |
1271 | { |
1272 | return (register_operand (op, mode) | |
1273 | && (GET_CODE (op) != REG | |
1274 | || REGNO (op) >= FIRST_PSEUDO_REGISTER | |
1275 | || CR_REGNO_NOT_CR0_P (REGNO (op)))); | |
1276 | } | |
1277 | ||
a4f6c312 SS |
1278 | /* Returns 1 if OP is either a constant integer valid for a D-field or |
1279 | a non-special register. If a register, it must be in the proper | |
1280 | mode unless MODE is VOIDmode. */ | |
9878760c RK |
1281 | |
1282 | int | |
a2369ed3 | 1283 | reg_or_short_operand (rtx op, enum machine_mode mode) |
9878760c | 1284 | { |
f5a28898 | 1285 | return short_cint_operand (op, mode) || gpc_reg_operand (op, mode); |
9878760c RK |
1286 | } |
1287 | ||
a4f6c312 SS |
1288 | /* Similar, except check if the negation of the constant would be |
1289 | valid for a D-field. */ | |
9878760c RK |
1290 | |
1291 | int | |
a2369ed3 | 1292 | reg_or_neg_short_operand (rtx op, enum machine_mode mode) |
9878760c RK |
1293 | { |
1294 | if (GET_CODE (op) == CONST_INT) | |
1295 | return CONST_OK_FOR_LETTER_P (INTVAL (op), 'P'); | |
1296 | ||
cd2b37d9 | 1297 | return gpc_reg_operand (op, mode); |
9878760c RK |
1298 | } |
1299 | ||
768070a0 TR |
1300 | /* Returns 1 if OP is either a constant integer valid for a DS-field or |
1301 | a non-special register. If a register, it must be in the proper | |
1302 | mode unless MODE is VOIDmode. */ | |
1303 | ||
1304 | int | |
a2369ed3 | 1305 | reg_or_aligned_short_operand (rtx op, enum machine_mode mode) |
768070a0 TR |
1306 | { |
1307 | if (gpc_reg_operand (op, mode)) | |
1308 | return 1; | |
1309 | else if (short_cint_operand (op, mode) && !(INTVAL (op) & 3)) | |
1310 | return 1; | |
1311 | ||
1312 | return 0; | |
1313 | } | |
1314 | ||
1315 | ||
a4f6c312 SS |
1316 | /* Return 1 if the operand is either a register or an integer whose |
1317 | high-order 16 bits are zero. */ | |
9878760c RK |
1318 | |
1319 | int | |
a2369ed3 | 1320 | reg_or_u_short_operand (rtx op, enum machine_mode mode) |
9878760c | 1321 | { |
e675f625 | 1322 | return u_short_cint_operand (op, mode) || gpc_reg_operand (op, mode); |
9878760c RK |
1323 | } |
1324 | ||
1325 | /* Return 1 is the operand is either a non-special register or ANY | |
1326 | constant integer. */ | |
1327 | ||
1328 | int | |
a2369ed3 | 1329 | reg_or_cint_operand (rtx op, enum machine_mode mode) |
9878760c | 1330 | { |
a4f6c312 | 1331 | return (GET_CODE (op) == CONST_INT || gpc_reg_operand (op, mode)); |
f6bf7de2 DE |
1332 | } |
1333 | ||
1334 | /* Return 1 is the operand is either a non-special register or ANY | |
1335 | 32-bit signed constant integer. */ | |
1336 | ||
1337 | int | |
a2369ed3 | 1338 | reg_or_arith_cint_operand (rtx op, enum machine_mode mode) |
f6bf7de2 | 1339 | { |
a4f6c312 SS |
1340 | return (gpc_reg_operand (op, mode) |
1341 | || (GET_CODE (op) == CONST_INT | |
f6bf7de2 | 1342 | #if HOST_BITS_PER_WIDE_INT != 32 |
a4f6c312 SS |
1343 | && ((unsigned HOST_WIDE_INT) (INTVAL (op) + 0x80000000) |
1344 | < (unsigned HOST_WIDE_INT) 0x100000000ll) | |
f6bf7de2 | 1345 | #endif |
a4f6c312 | 1346 | )); |
9878760c RK |
1347 | } |
1348 | ||
2bfcf297 DB |
1349 | /* Return 1 is the operand is either a non-special register or a 32-bit |
1350 | signed constant integer valid for 64-bit addition. */ | |
1351 | ||
1352 | int | |
a2369ed3 | 1353 | reg_or_add_cint64_operand (rtx op, enum machine_mode mode) |
2bfcf297 | 1354 | { |
a4f6c312 SS |
1355 | return (gpc_reg_operand (op, mode) |
1356 | || (GET_CODE (op) == CONST_INT | |
a65c591c | 1357 | #if HOST_BITS_PER_WIDE_INT == 32 |
a4f6c312 | 1358 | && INTVAL (op) < 0x7fff8000 |
a65c591c | 1359 | #else |
a4f6c312 SS |
1360 | && ((unsigned HOST_WIDE_INT) (INTVAL (op) + 0x80008000) |
1361 | < 0x100000000ll) | |
2bfcf297 | 1362 | #endif |
a4f6c312 | 1363 | )); |
2bfcf297 DB |
1364 | } |
1365 | ||
1366 | /* Return 1 is the operand is either a non-special register or a 32-bit | |
1367 | signed constant integer valid for 64-bit subtraction. */ | |
1368 | ||
1369 | int | |
a2369ed3 | 1370 | reg_or_sub_cint64_operand (rtx op, enum machine_mode mode) |
2bfcf297 | 1371 | { |
a4f6c312 SS |
1372 | return (gpc_reg_operand (op, mode) |
1373 | || (GET_CODE (op) == CONST_INT | |
a65c591c | 1374 | #if HOST_BITS_PER_WIDE_INT == 32 |
a4f6c312 | 1375 | && (- INTVAL (op)) < 0x7fff8000 |
a65c591c | 1376 | #else |
a4f6c312 SS |
1377 | && ((unsigned HOST_WIDE_INT) ((- INTVAL (op)) + 0x80008000) |
1378 | < 0x100000000ll) | |
2bfcf297 | 1379 | #endif |
a4f6c312 | 1380 | )); |
2bfcf297 DB |
1381 | } |
1382 | ||
9ebbca7d GK |
1383 | /* Return 1 is the operand is either a non-special register or ANY |
1384 | 32-bit unsigned constant integer. */ | |
1385 | ||
1386 | int | |
a2369ed3 | 1387 | reg_or_logical_cint_operand (rtx op, enum machine_mode mode) |
9ebbca7d | 1388 | { |
1d328b19 GK |
1389 | if (GET_CODE (op) == CONST_INT) |
1390 | { | |
1391 | if (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT) | |
1392 | { | |
1393 | if (GET_MODE_BITSIZE (mode) <= 32) | |
a4f6c312 | 1394 | abort (); |
1d328b19 GK |
1395 | |
1396 | if (INTVAL (op) < 0) | |
1397 | return 0; | |
1398 | } | |
1399 | ||
1400 | return ((INTVAL (op) & GET_MODE_MASK (mode) | |
0858c623 | 1401 | & (~ (unsigned HOST_WIDE_INT) 0xffffffff)) == 0); |
1d328b19 GK |
1402 | } |
1403 | else if (GET_CODE (op) == CONST_DOUBLE) | |
1404 | { | |
1405 | if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT | |
1406 | || mode != DImode) | |
a4f6c312 | 1407 | abort (); |
1d328b19 GK |
1408 | |
1409 | return CONST_DOUBLE_HIGH (op) == 0; | |
1410 | } | |
1411 | else | |
1412 | return gpc_reg_operand (op, mode); | |
9ebbca7d GK |
1413 | } |
1414 | ||
51d3e7d6 | 1415 | /* Return 1 if the operand is an operand that can be loaded via the GOT. */ |
766a866c MM |
1416 | |
1417 | int | |
a2369ed3 | 1418 | got_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
766a866c MM |
1419 | { |
1420 | return (GET_CODE (op) == SYMBOL_REF | |
1421 | || GET_CODE (op) == CONST | |
1422 | || GET_CODE (op) == LABEL_REF); | |
1423 | } | |
1424 | ||
38c1f2d7 MM |
1425 | /* Return 1 if the operand is a simple references that can be loaded via |
1426 | the GOT (labels involving addition aren't allowed). */ | |
1427 | ||
1428 | int | |
a2369ed3 | 1429 | got_no_const_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
38c1f2d7 MM |
1430 | { |
1431 | return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF); | |
1432 | } | |
1433 | ||
4e74d8ec MM |
1434 | /* Return the number of instructions it takes to form a constant in an |
1435 | integer register. */ | |
1436 | ||
1437 | static int | |
a2369ed3 | 1438 | num_insns_constant_wide (HOST_WIDE_INT value) |
4e74d8ec MM |
1439 | { |
1440 | /* signed constant loadable with {cal|addi} */ | |
5f59ecb7 | 1441 | if (CONST_OK_FOR_LETTER_P (value, 'I')) |
0865c631 GK |
1442 | return 1; |
1443 | ||
4e74d8ec | 1444 | /* constant loadable with {cau|addis} */ |
5f59ecb7 | 1445 | else if (CONST_OK_FOR_LETTER_P (value, 'L')) |
4e74d8ec MM |
1446 | return 1; |
1447 | ||
5f59ecb7 | 1448 | #if HOST_BITS_PER_WIDE_INT == 64 |
c81fc13e | 1449 | else if (TARGET_POWERPC64) |
4e74d8ec | 1450 | { |
a65c591c DE |
1451 | HOST_WIDE_INT low = ((value & 0xffffffff) ^ 0x80000000) - 0x80000000; |
1452 | HOST_WIDE_INT high = value >> 31; | |
4e74d8ec | 1453 | |
a65c591c | 1454 | if (high == 0 || high == -1) |
4e74d8ec MM |
1455 | return 2; |
1456 | ||
a65c591c | 1457 | high >>= 1; |
4e74d8ec | 1458 | |
a65c591c | 1459 | if (low == 0) |
4e74d8ec | 1460 | return num_insns_constant_wide (high) + 1; |
4e74d8ec MM |
1461 | else |
1462 | return (num_insns_constant_wide (high) | |
e396202a | 1463 | + num_insns_constant_wide (low) + 1); |
4e74d8ec MM |
1464 | } |
1465 | #endif | |
1466 | ||
1467 | else | |
1468 | return 2; | |
1469 | } | |
1470 | ||
1471 | int | |
a2369ed3 | 1472 | num_insns_constant (rtx op, enum machine_mode mode) |
4e74d8ec | 1473 | { |
4e74d8ec | 1474 | if (GET_CODE (op) == CONST_INT) |
0d30d435 DE |
1475 | { |
1476 | #if HOST_BITS_PER_WIDE_INT == 64 | |
4e2c1c44 DE |
1477 | if ((INTVAL (op) >> 31) != 0 && (INTVAL (op) >> 31) != -1 |
1478 | && mask64_operand (op, mode)) | |
0d30d435 DE |
1479 | return 2; |
1480 | else | |
1481 | #endif | |
1482 | return num_insns_constant_wide (INTVAL (op)); | |
1483 | } | |
4e74d8ec | 1484 | |
6fc48950 MM |
1485 | else if (GET_CODE (op) == CONST_DOUBLE && mode == SFmode) |
1486 | { | |
1487 | long l; | |
1488 | REAL_VALUE_TYPE rv; | |
1489 | ||
1490 | REAL_VALUE_FROM_CONST_DOUBLE (rv, op); | |
1491 | REAL_VALUE_TO_TARGET_SINGLE (rv, l); | |
e72247f4 | 1492 | return num_insns_constant_wide ((HOST_WIDE_INT) l); |
6fc48950 MM |
1493 | } |
1494 | ||
47ad8c61 | 1495 | else if (GET_CODE (op) == CONST_DOUBLE) |
4e74d8ec | 1496 | { |
47ad8c61 MM |
1497 | HOST_WIDE_INT low; |
1498 | HOST_WIDE_INT high; | |
1499 | long l[2]; | |
1500 | REAL_VALUE_TYPE rv; | |
1501 | int endian = (WORDS_BIG_ENDIAN == 0); | |
4e74d8ec | 1502 | |
47ad8c61 MM |
1503 | if (mode == VOIDmode || mode == DImode) |
1504 | { | |
1505 | high = CONST_DOUBLE_HIGH (op); | |
1506 | low = CONST_DOUBLE_LOW (op); | |
1507 | } | |
1508 | else | |
1509 | { | |
1510 | REAL_VALUE_FROM_CONST_DOUBLE (rv, op); | |
1511 | REAL_VALUE_TO_TARGET_DOUBLE (rv, l); | |
1512 | high = l[endian]; | |
1513 | low = l[1 - endian]; | |
1514 | } | |
4e74d8ec | 1515 | |
47ad8c61 MM |
1516 | if (TARGET_32BIT) |
1517 | return (num_insns_constant_wide (low) | |
1518 | + num_insns_constant_wide (high)); | |
4e74d8ec MM |
1519 | |
1520 | else | |
47ad8c61 | 1521 | { |
e72247f4 | 1522 | if (high == 0 && low >= 0) |
47ad8c61 MM |
1523 | return num_insns_constant_wide (low); |
1524 | ||
e72247f4 | 1525 | else if (high == -1 && low < 0) |
47ad8c61 MM |
1526 | return num_insns_constant_wide (low); |
1527 | ||
a260abc9 DE |
1528 | else if (mask64_operand (op, mode)) |
1529 | return 2; | |
1530 | ||
47ad8c61 MM |
1531 | else if (low == 0) |
1532 | return num_insns_constant_wide (high) + 1; | |
1533 | ||
1534 | else | |
1535 | return (num_insns_constant_wide (high) | |
1536 | + num_insns_constant_wide (low) + 1); | |
1537 | } | |
4e74d8ec MM |
1538 | } |
1539 | ||
1540 | else | |
1541 | abort (); | |
1542 | } | |
1543 | ||
a4f6c312 SS |
1544 | /* Return 1 if the operand is a CONST_DOUBLE and it can be put into a |
1545 | register with one instruction per word. We only do this if we can | |
1546 | safely read CONST_DOUBLE_{LOW,HIGH}. */ | |
9878760c RK |
1547 | |
1548 | int | |
a2369ed3 | 1549 | easy_fp_constant (rtx op, enum machine_mode mode) |
9878760c | 1550 | { |
9878760c RK |
1551 | if (GET_CODE (op) != CONST_DOUBLE |
1552 | || GET_MODE (op) != mode | |
4e74d8ec | 1553 | || (GET_MODE_CLASS (mode) != MODE_FLOAT && mode != DImode)) |
9878760c RK |
1554 | return 0; |
1555 | ||
a4f6c312 | 1556 | /* Consider all constants with -msoft-float to be easy. */ |
a3170dc6 AH |
1557 | if ((TARGET_SOFT_FLOAT || !TARGET_FPRS) |
1558 | && mode != DImode) | |
b6c9286a MM |
1559 | return 1; |
1560 | ||
a4f6c312 | 1561 | /* If we are using V.4 style PIC, consider all constants to be hard. */ |
f607bc57 | 1562 | if (flag_pic && DEFAULT_ABI == ABI_V4) |
a7273471 MM |
1563 | return 0; |
1564 | ||
5ae4759c | 1565 | #ifdef TARGET_RELOCATABLE |
a4f6c312 SS |
1566 | /* Similarly if we are using -mrelocatable, consider all constants |
1567 | to be hard. */ | |
5ae4759c MM |
1568 | if (TARGET_RELOCATABLE) |
1569 | return 0; | |
1570 | #endif | |
1571 | ||
fcce224d DE |
1572 | if (mode == TFmode) |
1573 | { | |
1574 | long k[4]; | |
1575 | REAL_VALUE_TYPE rv; | |
1576 | ||
1577 | REAL_VALUE_FROM_CONST_DOUBLE (rv, op); | |
1578 | REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv, k); | |
1579 | ||
1580 | return (num_insns_constant_wide ((HOST_WIDE_INT) k[0]) == 1 | |
1581 | && num_insns_constant_wide ((HOST_WIDE_INT) k[1]) == 1 | |
1582 | && num_insns_constant_wide ((HOST_WIDE_INT) k[2]) == 1 | |
1583 | && num_insns_constant_wide ((HOST_WIDE_INT) k[3]) == 1); | |
1584 | } | |
1585 | ||
1586 | else if (mode == DFmode) | |
042259f2 DE |
1587 | { |
1588 | long k[2]; | |
1589 | REAL_VALUE_TYPE rv; | |
1590 | ||
1591 | REAL_VALUE_FROM_CONST_DOUBLE (rv, op); | |
1592 | REAL_VALUE_TO_TARGET_DOUBLE (rv, k); | |
9878760c | 1593 | |
a65c591c DE |
1594 | return (num_insns_constant_wide ((HOST_WIDE_INT) k[0]) == 1 |
1595 | && num_insns_constant_wide ((HOST_WIDE_INT) k[1]) == 1); | |
042259f2 | 1596 | } |
4e74d8ec MM |
1597 | |
1598 | else if (mode == SFmode) | |
042259f2 DE |
1599 | { |
1600 | long l; | |
1601 | REAL_VALUE_TYPE rv; | |
1602 | ||
1603 | REAL_VALUE_FROM_CONST_DOUBLE (rv, op); | |
1604 | REAL_VALUE_TO_TARGET_SINGLE (rv, l); | |
9878760c | 1605 | |
4e74d8ec | 1606 | return num_insns_constant_wide (l) == 1; |
042259f2 | 1607 | } |
4e74d8ec | 1608 | |
a260abc9 | 1609 | else if (mode == DImode) |
c81fc13e | 1610 | return ((TARGET_POWERPC64 |
a260abc9 DE |
1611 | && GET_CODE (op) == CONST_DOUBLE && CONST_DOUBLE_LOW (op) == 0) |
1612 | || (num_insns_constant (op, DImode) <= 2)); | |
4e74d8ec | 1613 | |
a9098fd0 GK |
1614 | else if (mode == SImode) |
1615 | return 1; | |
4e74d8ec MM |
1616 | else |
1617 | abort (); | |
9878760c | 1618 | } |
8f75773e | 1619 | |
72ac76be | 1620 | /* Return nonzero if all elements of a vector have the same value. */ |
69ef87e2 AH |
1621 | |
1622 | static int | |
a2369ed3 | 1623 | easy_vector_same (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
d744e06e AH |
1624 | { |
1625 | int units, i, cst; | |
1626 | ||
1627 | units = CONST_VECTOR_NUNITS (op); | |
1628 | ||
1629 | cst = INTVAL (CONST_VECTOR_ELT (op, 0)); | |
1630 | for (i = 1; i < units; ++i) | |
1631 | if (INTVAL (CONST_VECTOR_ELT (op, i)) != cst) | |
1632 | break; | |
1633 | if (i == units) | |
1634 | return 1; | |
1635 | return 0; | |
1636 | } | |
1637 | ||
1638 | /* Return 1 if the operand is a CONST_INT and can be put into a | |
1639 | register without using memory. */ | |
1640 | ||
1641 | int | |
a2369ed3 | 1642 | easy_vector_constant (rtx op, enum machine_mode mode) |
69ef87e2 | 1643 | { |
d744e06e | 1644 | int cst, cst2; |
69ef87e2 | 1645 | |
d744e06e AH |
1646 | if (GET_CODE (op) != CONST_VECTOR |
1647 | || (!TARGET_ALTIVEC | |
1648 | && !TARGET_SPE)) | |
69ef87e2 AH |
1649 | return 0; |
1650 | ||
d744e06e AH |
1651 | if (zero_constant (op, mode) |
1652 | && ((TARGET_ALTIVEC && ALTIVEC_VECTOR_MODE (mode)) | |
1653 | || (TARGET_SPE && SPE_VECTOR_MODE (mode)))) | |
1654 | return 1; | |
69ef87e2 | 1655 | |
d744e06e AH |
1656 | if (GET_MODE_CLASS (mode) != MODE_VECTOR_INT) |
1657 | return 0; | |
1658 | ||
f5119d10 AH |
1659 | if (TARGET_SPE && mode == V1DImode) |
1660 | return 0; | |
1661 | ||
d744e06e AH |
1662 | cst = INTVAL (CONST_VECTOR_ELT (op, 0)); |
1663 | cst2 = INTVAL (CONST_VECTOR_ELT (op, 1)); | |
1664 | ||
1665 | /* Limit SPE vectors to 15 bits signed. These we can generate with: | |
1666 | li r0, CONSTANT1 | |
1667 | evmergelo r0, r0, r0 | |
1668 | li r0, CONSTANT2 | |
1669 | ||
1670 | I don't know how efficient it would be to allow bigger constants, | |
1671 | considering we'll have an extra 'ori' for every 'li'. I doubt 5 | |
1672 | instructions is better than a 64-bit memory load, but I don't | |
1673 | have the e500 timing specs. */ | |
1674 | if (TARGET_SPE && mode == V2SImode | |
1675 | && cst >= -0x7fff && cst <= 0x7fff | |
f5119d10 | 1676 | && cst2 >= -0x7fff && cst2 <= 0x7fff) |
d744e06e AH |
1677 | return 1; |
1678 | ||
ce1f50b2 HP |
1679 | if (TARGET_ALTIVEC) |
1680 | switch (mode) | |
1681 | { | |
1682 | case V4SImode: | |
1683 | if (EASY_VECTOR_15 (cst, op, mode)) | |
1684 | return 1; | |
1685 | if ((cst & 0xffff) != ((cst >> 16) & 0xffff)) | |
1686 | break; | |
1687 | cst = cst >> 16; | |
1688 | case V8HImode: | |
1689 | if (EASY_VECTOR_15 (cst, op, mode)) | |
1690 | return 1; | |
1691 | if ((cst & 0xff) != ((cst >> 8) & 0xff)) | |
1692 | break; | |
1693 | cst = cst >> 8; | |
1694 | case V16QImode: | |
1695 | if (EASY_VECTOR_15 (cst, op, mode)) | |
1696 | return 1; | |
1697 | default: | |
1698 | break; | |
1699 | } | |
d744e06e AH |
1700 | |
1701 | if (TARGET_ALTIVEC && EASY_VECTOR_15_ADD_SELF (cst, op, mode)) | |
1702 | return 1; | |
1703 | ||
1704 | return 0; | |
1705 | } | |
1706 | ||
1707 | /* Same as easy_vector_constant but only for EASY_VECTOR_15_ADD_SELF. */ | |
1708 | ||
1709 | int | |
a2369ed3 | 1710 | easy_vector_constant_add_self (rtx op, enum machine_mode mode) |
d744e06e AH |
1711 | { |
1712 | int cst; | |
1713 | ||
1714 | if (!easy_vector_constant (op, mode)) | |
1715 | return 0; | |
1716 | ||
1717 | cst = INTVAL (CONST_VECTOR_ELT (op, 0)); | |
1718 | ||
1719 | return TARGET_ALTIVEC && EASY_VECTOR_15_ADD_SELF (cst, op, mode); | |
1720 | } | |
1721 | ||
1722 | const char * | |
a2369ed3 | 1723 | output_vec_const_move (rtx *operands) |
d744e06e AH |
1724 | { |
1725 | int cst, cst2; | |
1726 | enum machine_mode mode; | |
1727 | rtx dest, vec; | |
1728 | ||
1729 | dest = operands[0]; | |
1730 | vec = operands[1]; | |
69ef87e2 | 1731 | |
d744e06e AH |
1732 | cst = INTVAL (CONST_VECTOR_ELT (vec, 0)); |
1733 | cst2 = INTVAL (CONST_VECTOR_ELT (vec, 1)); | |
1734 | mode = GET_MODE (dest); | |
69ef87e2 | 1735 | |
d744e06e AH |
1736 | if (TARGET_ALTIVEC) |
1737 | { | |
1738 | if (zero_constant (vec, mode)) | |
1739 | return "vxor %0,%0,%0"; | |
ce1f50b2 HP |
1740 | else if (EASY_VECTOR_15_ADD_SELF (cst, vec, mode)) |
1741 | return "#"; | |
1742 | else if (easy_vector_constant (vec, mode)) | |
98ef3137 | 1743 | { |
d744e06e AH |
1744 | operands[1] = GEN_INT (cst); |
1745 | switch (mode) | |
1746 | { | |
1747 | case V4SImode: | |
ce1f50b2 HP |
1748 | if (EASY_VECTOR_15 (cst, vec, mode)) |
1749 | { | |
1750 | operands[1] = GEN_INT (cst); | |
1751 | return "vspltisw %0,%1"; | |
1752 | } | |
1753 | cst = cst >> 16; | |
d744e06e | 1754 | case V8HImode: |
ce1f50b2 HP |
1755 | if (EASY_VECTOR_15 (cst, vec, mode)) |
1756 | { | |
1757 | operands[1] = GEN_INT (cst); | |
1758 | return "vspltish %0,%1"; | |
1759 | } | |
1760 | cst = cst >> 8; | |
d744e06e | 1761 | case V16QImode: |
ce1f50b2 HP |
1762 | if (EASY_VECTOR_15 (cst, vec, mode)) |
1763 | { | |
1764 | operands[1] = GEN_INT (cst); | |
1765 | return "vspltisb %0,%1"; | |
1766 | } | |
d744e06e AH |
1767 | default: |
1768 | abort (); | |
1769 | } | |
98ef3137 | 1770 | } |
d744e06e AH |
1771 | else |
1772 | abort (); | |
69ef87e2 AH |
1773 | } |
1774 | ||
d744e06e AH |
1775 | if (TARGET_SPE) |
1776 | { | |
1777 | /* Vector constant 0 is handled as a splitter of V2SI, and in the | |
1778 | pattern of V1DI, V4HI, and V2SF. | |
1779 | ||
c1207243 | 1780 | FIXME: We should probably return # and add post reload |
d744e06e AH |
1781 | splitters for these, but this way is so easy ;-). |
1782 | */ | |
1783 | operands[1] = GEN_INT (cst); | |
1784 | operands[2] = GEN_INT (cst2); | |
1785 | if (cst == cst2) | |
1786 | return "li %0,%1\n\tevmergelo %0,%0,%0"; | |
1787 | else | |
1788 | return "li %0,%1\n\tevmergelo %0,%0,%0\n\tli %0,%2"; | |
1789 | } | |
1790 | ||
1791 | abort (); | |
69ef87e2 AH |
1792 | } |
1793 | ||
1794 | /* Return 1 if the operand is the constant 0. This works for scalars | |
1795 | as well as vectors. */ | |
1796 | int | |
a2369ed3 | 1797 | zero_constant (rtx op, enum machine_mode mode) |
69ef87e2 AH |
1798 | { |
1799 | return op == CONST0_RTX (mode); | |
1800 | } | |
1801 | ||
50a0b056 GK |
1802 | /* Return 1 if the operand is 0.0. */ |
1803 | int | |
a2369ed3 | 1804 | zero_fp_constant (rtx op, enum machine_mode mode) |
50a0b056 GK |
1805 | { |
1806 | return GET_MODE_CLASS (mode) == MODE_FLOAT && op == CONST0_RTX (mode); | |
1807 | } | |
1808 | ||
a4f6c312 SS |
1809 | /* Return 1 if the operand is in volatile memory. Note that during |
1810 | the RTL generation phase, memory_operand does not return TRUE for | |
b6c9286a MM |
1811 | volatile memory references. So this function allows us to |
1812 | recognize volatile references where its safe. */ | |
1813 | ||
1814 | int | |
a2369ed3 | 1815 | volatile_mem_operand (rtx op, enum machine_mode mode) |
b6c9286a MM |
1816 | { |
1817 | if (GET_CODE (op) != MEM) | |
1818 | return 0; | |
1819 | ||
1820 | if (!MEM_VOLATILE_P (op)) | |
1821 | return 0; | |
1822 | ||
1823 | if (mode != GET_MODE (op)) | |
1824 | return 0; | |
1825 | ||
1826 | if (reload_completed) | |
1827 | return memory_operand (op, mode); | |
1828 | ||
1829 | if (reload_in_progress) | |
1830 | return strict_memory_address_p (mode, XEXP (op, 0)); | |
1831 | ||
1832 | return memory_address_p (mode, XEXP (op, 0)); | |
1833 | } | |
1834 | ||
97f6e72f | 1835 | /* Return 1 if the operand is an offsettable memory operand. */ |
914c2e77 RK |
1836 | |
1837 | int | |
a2369ed3 | 1838 | offsettable_mem_operand (rtx op, enum machine_mode mode) |
914c2e77 | 1839 | { |
97f6e72f | 1840 | return ((GET_CODE (op) == MEM) |
677a9668 | 1841 | && offsettable_address_p (reload_completed || reload_in_progress, |
97f6e72f | 1842 | mode, XEXP (op, 0))); |
914c2e77 RK |
1843 | } |
1844 | ||
9878760c RK |
1845 | /* Return 1 if the operand is either an easy FP constant (see above) or |
1846 | memory. */ | |
1847 | ||
1848 | int | |
a2369ed3 | 1849 | mem_or_easy_const_operand (rtx op, enum machine_mode mode) |
9878760c RK |
1850 | { |
1851 | return memory_operand (op, mode) || easy_fp_constant (op, mode); | |
1852 | } | |
1853 | ||
1854 | /* Return 1 if the operand is either a non-special register or an item | |
5f59ecb7 | 1855 | that can be used as the operand of a `mode' add insn. */ |
9878760c RK |
1856 | |
1857 | int | |
a2369ed3 | 1858 | add_operand (rtx op, enum machine_mode mode) |
9878760c | 1859 | { |
2bfcf297 | 1860 | if (GET_CODE (op) == CONST_INT) |
e72247f4 DE |
1861 | return (CONST_OK_FOR_LETTER_P (INTVAL (op), 'I') |
1862 | || CONST_OK_FOR_LETTER_P (INTVAL (op), 'L')); | |
2bfcf297 DB |
1863 | |
1864 | return gpc_reg_operand (op, mode); | |
9878760c RK |
1865 | } |
1866 | ||
dcfedcd0 RK |
1867 | /* Return 1 if OP is a constant but not a valid add_operand. */ |
1868 | ||
1869 | int | |
a2369ed3 | 1870 | non_add_cint_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
dcfedcd0 RK |
1871 | { |
1872 | return (GET_CODE (op) == CONST_INT | |
e72247f4 DE |
1873 | && !CONST_OK_FOR_LETTER_P (INTVAL (op), 'I') |
1874 | && !CONST_OK_FOR_LETTER_P (INTVAL (op), 'L')); | |
dcfedcd0 RK |
1875 | } |
1876 | ||
9878760c RK |
1877 | /* Return 1 if the operand is a non-special register or a constant that |
1878 | can be used as the operand of an OR or XOR insn on the RS/6000. */ | |
1879 | ||
1880 | int | |
a2369ed3 | 1881 | logical_operand (rtx op, enum machine_mode mode) |
9878760c | 1882 | { |
40501e5f | 1883 | HOST_WIDE_INT opl, oph; |
1d328b19 | 1884 | |
dfbdccdb GK |
1885 | if (gpc_reg_operand (op, mode)) |
1886 | return 1; | |
1d328b19 | 1887 | |
dfbdccdb | 1888 | if (GET_CODE (op) == CONST_INT) |
40501e5f AM |
1889 | { |
1890 | opl = INTVAL (op) & GET_MODE_MASK (mode); | |
1891 | ||
1892 | #if HOST_BITS_PER_WIDE_INT <= 32 | |
1893 | if (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT && opl < 0) | |
1894 | return 0; | |
1895 | #endif | |
1896 | } | |
dfbdccdb GK |
1897 | else if (GET_CODE (op) == CONST_DOUBLE) |
1898 | { | |
1d328b19 | 1899 | if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT) |
40501e5f | 1900 | abort (); |
1d328b19 GK |
1901 | |
1902 | opl = CONST_DOUBLE_LOW (op); | |
1903 | oph = CONST_DOUBLE_HIGH (op); | |
40501e5f | 1904 | if (oph != 0) |
38886f37 | 1905 | return 0; |
dfbdccdb GK |
1906 | } |
1907 | else | |
1908 | return 0; | |
1d328b19 | 1909 | |
40501e5f AM |
1910 | return ((opl & ~ (unsigned HOST_WIDE_INT) 0xffff) == 0 |
1911 | || (opl & ~ (unsigned HOST_WIDE_INT) 0xffff0000) == 0); | |
9878760c RK |
1912 | } |
1913 | ||
dcfedcd0 | 1914 | /* Return 1 if C is a constant that is not a logical operand (as |
1d328b19 | 1915 | above), but could be split into one. */ |
dcfedcd0 RK |
1916 | |
1917 | int | |
a2369ed3 | 1918 | non_logical_cint_operand (rtx op, enum machine_mode mode) |
dcfedcd0 | 1919 | { |
dfbdccdb | 1920 | return ((GET_CODE (op) == CONST_INT || GET_CODE (op) == CONST_DOUBLE) |
1d328b19 GK |
1921 | && ! logical_operand (op, mode) |
1922 | && reg_or_logical_cint_operand (op, mode)); | |
dcfedcd0 RK |
1923 | } |
1924 | ||
19ba8161 | 1925 | /* Return 1 if C is a constant that can be encoded in a 32-bit mask on the |
9878760c RK |
1926 | RS/6000. It is if there are no more than two 1->0 or 0->1 transitions. |
1927 | Reject all ones and all zeros, since these should have been optimized | |
1928 | away and confuse the making of MB and ME. */ | |
1929 | ||
1930 | int | |
a2369ed3 | 1931 | mask_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
9878760c | 1932 | { |
02071907 | 1933 | HOST_WIDE_INT c, lsb; |
9878760c | 1934 | |
19ba8161 DE |
1935 | if (GET_CODE (op) != CONST_INT) |
1936 | return 0; | |
1937 | ||
1938 | c = INTVAL (op); | |
1939 | ||
57deb3a1 AM |
1940 | /* Fail in 64-bit mode if the mask wraps around because the upper |
1941 | 32-bits of the mask will all be 1s, contrary to GCC's internal view. */ | |
1942 | if (TARGET_POWERPC64 && (c & 0x80000001) == 0x80000001) | |
1943 | return 0; | |
1944 | ||
c5059423 AM |
1945 | /* We don't change the number of transitions by inverting, |
1946 | so make sure we start with the LS bit zero. */ | |
1947 | if (c & 1) | |
1948 | c = ~c; | |
1949 | ||
1950 | /* Reject all zeros or all ones. */ | |
1951 | if (c == 0) | |
9878760c RK |
1952 | return 0; |
1953 | ||
c5059423 AM |
1954 | /* Find the first transition. */ |
1955 | lsb = c & -c; | |
1956 | ||
1957 | /* Invert to look for a second transition. */ | |
1958 | c = ~c; | |
9878760c | 1959 | |
c5059423 AM |
1960 | /* Erase first transition. */ |
1961 | c &= -lsb; | |
9878760c | 1962 | |
c5059423 AM |
1963 | /* Find the second transition (if any). */ |
1964 | lsb = c & -c; | |
1965 | ||
1966 | /* Match if all the bits above are 1's (or c is zero). */ | |
1967 | return c == -lsb; | |
9878760c RK |
1968 | } |
1969 | ||
0ba1b2ff AM |
1970 | /* Return 1 for the PowerPC64 rlwinm corner case. */ |
1971 | ||
1972 | int | |
a2369ed3 | 1973 | mask_operand_wrap (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
0ba1b2ff AM |
1974 | { |
1975 | HOST_WIDE_INT c, lsb; | |
1976 | ||
1977 | if (GET_CODE (op) != CONST_INT) | |
1978 | return 0; | |
1979 | ||
1980 | c = INTVAL (op); | |
1981 | ||
1982 | if ((c & 0x80000001) != 0x80000001) | |
1983 | return 0; | |
1984 | ||
1985 | c = ~c; | |
1986 | if (c == 0) | |
1987 | return 0; | |
1988 | ||
1989 | lsb = c & -c; | |
1990 | c = ~c; | |
1991 | c &= -lsb; | |
1992 | lsb = c & -c; | |
1993 | return c == -lsb; | |
1994 | } | |
1995 | ||
a260abc9 DE |
1996 | /* Return 1 if the operand is a constant that is a PowerPC64 mask. |
1997 | It is if there are no more than one 1->0 or 0->1 transitions. | |
0ba1b2ff AM |
1998 | Reject all zeros, since zero should have been optimized away and |
1999 | confuses the making of MB and ME. */ | |
9878760c RK |
2000 | |
2001 | int | |
a2369ed3 | 2002 | mask64_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
a260abc9 DE |
2003 | { |
2004 | if (GET_CODE (op) == CONST_INT) | |
2005 | { | |
02071907 | 2006 | HOST_WIDE_INT c, lsb; |
a260abc9 | 2007 | |
c5059423 | 2008 | c = INTVAL (op); |
a260abc9 | 2009 | |
0ba1b2ff | 2010 | /* Reject all zeros. */ |
c5059423 | 2011 | if (c == 0) |
e2c953b6 DE |
2012 | return 0; |
2013 | ||
0ba1b2ff AM |
2014 | /* We don't change the number of transitions by inverting, |
2015 | so make sure we start with the LS bit zero. */ | |
2016 | if (c & 1) | |
2017 | c = ~c; | |
2018 | ||
c5059423 AM |
2019 | /* Find the transition, and check that all bits above are 1's. */ |
2020 | lsb = c & -c; | |
e3981aab DE |
2021 | |
2022 | /* Match if all the bits above are 1's (or c is zero). */ | |
c5059423 | 2023 | return c == -lsb; |
e2c953b6 | 2024 | } |
0ba1b2ff AM |
2025 | return 0; |
2026 | } | |
2027 | ||
2028 | /* Like mask64_operand, but allow up to three transitions. This | |
2029 | predicate is used by insn patterns that generate two rldicl or | |
2030 | rldicr machine insns. */ | |
2031 | ||
2032 | int | |
a2369ed3 | 2033 | mask64_2_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
0ba1b2ff AM |
2034 | { |
2035 | if (GET_CODE (op) == CONST_INT) | |
a260abc9 | 2036 | { |
0ba1b2ff | 2037 | HOST_WIDE_INT c, lsb; |
a260abc9 | 2038 | |
0ba1b2ff | 2039 | c = INTVAL (op); |
a260abc9 | 2040 | |
0ba1b2ff AM |
2041 | /* Disallow all zeros. */ |
2042 | if (c == 0) | |
2043 | return 0; | |
a260abc9 | 2044 | |
0ba1b2ff AM |
2045 | /* We don't change the number of transitions by inverting, |
2046 | so make sure we start with the LS bit zero. */ | |
2047 | if (c & 1) | |
2048 | c = ~c; | |
a260abc9 | 2049 | |
0ba1b2ff AM |
2050 | /* Find the first transition. */ |
2051 | lsb = c & -c; | |
a260abc9 | 2052 | |
0ba1b2ff AM |
2053 | /* Invert to look for a second transition. */ |
2054 | c = ~c; | |
2055 | ||
2056 | /* Erase first transition. */ | |
2057 | c &= -lsb; | |
2058 | ||
2059 | /* Find the second transition. */ | |
2060 | lsb = c & -c; | |
2061 | ||
2062 | /* Invert to look for a third transition. */ | |
2063 | c = ~c; | |
2064 | ||
2065 | /* Erase second transition. */ | |
2066 | c &= -lsb; | |
2067 | ||
2068 | /* Find the third transition (if any). */ | |
2069 | lsb = c & -c; | |
2070 | ||
2071 | /* Match if all the bits above are 1's (or c is zero). */ | |
2072 | return c == -lsb; | |
2073 | } | |
2074 | return 0; | |
2075 | } | |
2076 | ||
2077 | /* Generates shifts and masks for a pair of rldicl or rldicr insns to | |
2078 | implement ANDing by the mask IN. */ | |
2079 | void | |
a2369ed3 | 2080 | build_mask64_2_operands (rtx in, rtx *out) |
0ba1b2ff AM |
2081 | { |
2082 | #if HOST_BITS_PER_WIDE_INT >= 64 | |
2083 | unsigned HOST_WIDE_INT c, lsb, m1, m2; | |
2084 | int shift; | |
2085 | ||
2086 | if (GET_CODE (in) != CONST_INT) | |
2087 | abort (); | |
2088 | ||
2089 | c = INTVAL (in); | |
2090 | if (c & 1) | |
2091 | { | |
2092 | /* Assume c initially something like 0x00fff000000fffff. The idea | |
2093 | is to rotate the word so that the middle ^^^^^^ group of zeros | |
2094 | is at the MS end and can be cleared with an rldicl mask. We then | |
2095 | rotate back and clear off the MS ^^ group of zeros with a | |
2096 | second rldicl. */ | |
2097 | c = ~c; /* c == 0xff000ffffff00000 */ | |
2098 | lsb = c & -c; /* lsb == 0x0000000000100000 */ | |
2099 | m1 = -lsb; /* m1 == 0xfffffffffff00000 */ | |
2100 | c = ~c; /* c == 0x00fff000000fffff */ | |
2101 | c &= -lsb; /* c == 0x00fff00000000000 */ | |
2102 | lsb = c & -c; /* lsb == 0x0000100000000000 */ | |
2103 | c = ~c; /* c == 0xff000fffffffffff */ | |
2104 | c &= -lsb; /* c == 0xff00000000000000 */ | |
2105 | shift = 0; | |
2106 | while ((lsb >>= 1) != 0) | |
2107 | shift++; /* shift == 44 on exit from loop */ | |
2108 | m1 <<= 64 - shift; /* m1 == 0xffffff0000000000 */ | |
2109 | m1 = ~m1; /* m1 == 0x000000ffffffffff */ | |
2110 | m2 = ~c; /* m2 == 0x00ffffffffffffff */ | |
a260abc9 DE |
2111 | } |
2112 | else | |
0ba1b2ff AM |
2113 | { |
2114 | /* Assume c initially something like 0xff000f0000000000. The idea | |
2115 | is to rotate the word so that the ^^^ middle group of zeros | |
2116 | is at the LS end and can be cleared with an rldicr mask. We then | |
2117 | rotate back and clear off the LS group of ^^^^^^^^^^ zeros with | |
2118 | a second rldicr. */ | |
2119 | lsb = c & -c; /* lsb == 0x0000010000000000 */ | |
2120 | m2 = -lsb; /* m2 == 0xffffff0000000000 */ | |
2121 | c = ~c; /* c == 0x00fff0ffffffffff */ | |
2122 | c &= -lsb; /* c == 0x00fff00000000000 */ | |
2123 | lsb = c & -c; /* lsb == 0x0000100000000000 */ | |
2124 | c = ~c; /* c == 0xff000fffffffffff */ | |
2125 | c &= -lsb; /* c == 0xff00000000000000 */ | |
2126 | shift = 0; | |
2127 | while ((lsb >>= 1) != 0) | |
2128 | shift++; /* shift == 44 on exit from loop */ | |
2129 | m1 = ~c; /* m1 == 0x00ffffffffffffff */ | |
2130 | m1 >>= shift; /* m1 == 0x0000000000000fff */ | |
2131 | m1 = ~m1; /* m1 == 0xfffffffffffff000 */ | |
2132 | } | |
2133 | ||
2134 | /* Note that when we only have two 0->1 and 1->0 transitions, one of the | |
2135 | masks will be all 1's. We are guaranteed more than one transition. */ | |
2136 | out[0] = GEN_INT (64 - shift); | |
2137 | out[1] = GEN_INT (m1); | |
2138 | out[2] = GEN_INT (shift); | |
2139 | out[3] = GEN_INT (m2); | |
2140 | #else | |
045572c7 GK |
2141 | (void)in; |
2142 | (void)out; | |
0ba1b2ff AM |
2143 | abort (); |
2144 | #endif | |
a260abc9 DE |
2145 | } |
2146 | ||
2147 | /* Return 1 if the operand is either a non-special register or a constant | |
2148 | that can be used as the operand of a PowerPC64 logical AND insn. */ | |
2149 | ||
2150 | int | |
a2369ed3 | 2151 | and64_operand (rtx op, enum machine_mode mode) |
9878760c | 2152 | { |
a4f6c312 | 2153 | if (fixed_regs[CR0_REGNO]) /* CR0 not available, don't do andi./andis. */ |
52d3af72 DE |
2154 | return (gpc_reg_operand (op, mode) || mask64_operand (op, mode)); |
2155 | ||
2156 | return (logical_operand (op, mode) || mask64_operand (op, mode)); | |
9878760c RK |
2157 | } |
2158 | ||
0ba1b2ff AM |
2159 | /* Like the above, but also match constants that can be implemented |
2160 | with two rldicl or rldicr insns. */ | |
2161 | ||
2162 | int | |
a2369ed3 | 2163 | and64_2_operand (rtx op, enum machine_mode mode) |
0ba1b2ff | 2164 | { |
a3c9585f | 2165 | if (fixed_regs[CR0_REGNO]) /* CR0 not available, don't do andi./andis. */ |
0ba1b2ff AM |
2166 | return gpc_reg_operand (op, mode) || mask64_2_operand (op, mode); |
2167 | ||
2168 | return logical_operand (op, mode) || mask64_2_operand (op, mode); | |
2169 | } | |
2170 | ||
a260abc9 DE |
2171 | /* Return 1 if the operand is either a non-special register or a |
2172 | constant that can be used as the operand of an RS/6000 logical AND insn. */ | |
dcfedcd0 RK |
2173 | |
2174 | int | |
a2369ed3 | 2175 | and_operand (rtx op, enum machine_mode mode) |
dcfedcd0 | 2176 | { |
a4f6c312 | 2177 | if (fixed_regs[CR0_REGNO]) /* CR0 not available, don't do andi./andis. */ |
52d3af72 DE |
2178 | return (gpc_reg_operand (op, mode) || mask_operand (op, mode)); |
2179 | ||
2180 | return (logical_operand (op, mode) || mask_operand (op, mode)); | |
dcfedcd0 RK |
2181 | } |
2182 | ||
9878760c RK |
2183 | /* Return 1 if the operand is a general register or memory operand. */ |
2184 | ||
2185 | int | |
a2369ed3 | 2186 | reg_or_mem_operand (rtx op, enum machine_mode mode) |
9878760c | 2187 | { |
b6c9286a MM |
2188 | return (gpc_reg_operand (op, mode) |
2189 | || memory_operand (op, mode) | |
4c81e946 | 2190 | || macho_lo_sum_memory_operand (op, mode) |
b6c9286a | 2191 | || volatile_mem_operand (op, mode)); |
9878760c RK |
2192 | } |
2193 | ||
a7a813f7 | 2194 | /* Return 1 if the operand is a general register or memory operand without |
3cb999d8 | 2195 | pre_inc or pre_dec which produces invalid form of PowerPC lwa |
a7a813f7 RK |
2196 | instruction. */ |
2197 | ||
2198 | int | |
a2369ed3 | 2199 | lwa_operand (rtx op, enum machine_mode mode) |
a7a813f7 RK |
2200 | { |
2201 | rtx inner = op; | |
2202 | ||
2203 | if (reload_completed && GET_CODE (inner) == SUBREG) | |
2204 | inner = SUBREG_REG (inner); | |
2205 | ||
2206 | return gpc_reg_operand (inner, mode) | |
2207 | || (memory_operand (inner, mode) | |
2208 | && GET_CODE (XEXP (inner, 0)) != PRE_INC | |
6a40a9d6 DE |
2209 | && GET_CODE (XEXP (inner, 0)) != PRE_DEC |
2210 | && (GET_CODE (XEXP (inner, 0)) != PLUS | |
e903c96a DE |
2211 | || GET_CODE (XEXP (XEXP (inner, 0), 1)) != CONST_INT |
2212 | || INTVAL (XEXP (XEXP (inner, 0), 1)) % 4 == 0)); | |
a7a813f7 RK |
2213 | } |
2214 | ||
cc4d5fec JH |
2215 | /* Return 1 if the operand, used inside a MEM, is a SYMBOL_REF. */ |
2216 | ||
2217 | int | |
a2369ed3 | 2218 | symbol_ref_operand (rtx op, enum machine_mode mode) |
cc4d5fec JH |
2219 | { |
2220 | if (mode != VOIDmode && GET_MODE (op) != mode) | |
2221 | return 0; | |
2222 | ||
473f51b6 DE |
2223 | return (GET_CODE (op) == SYMBOL_REF |
2224 | && (DEFAULT_ABI != ABI_AIX || SYMBOL_REF_FUNCTION_P (op))); | |
cc4d5fec JH |
2225 | } |
2226 | ||
9878760c | 2227 | /* Return 1 if the operand, used inside a MEM, is a valid first argument |
cc4d5fec | 2228 | to CALL. This is a SYMBOL_REF, a pseudo-register, LR or CTR. */ |
9878760c RK |
2229 | |
2230 | int | |
a2369ed3 | 2231 | call_operand (rtx op, enum machine_mode mode) |
9878760c RK |
2232 | { |
2233 | if (mode != VOIDmode && GET_MODE (op) != mode) | |
2234 | return 0; | |
2235 | ||
2236 | return (GET_CODE (op) == SYMBOL_REF | |
cc4d5fec JH |
2237 | || (GET_CODE (op) == REG |
2238 | && (REGNO (op) == LINK_REGISTER_REGNUM | |
2239 | || REGNO (op) == COUNT_REGISTER_REGNUM | |
2240 | || REGNO (op) >= FIRST_PSEUDO_REGISTER))); | |
9878760c RK |
2241 | } |
2242 | ||
2af3d377 | 2243 | /* Return 1 if the operand is a SYMBOL_REF for a function known to be in |
d1908feb | 2244 | this file. */ |
2af3d377 RK |
2245 | |
2246 | int | |
a2369ed3 DJ |
2247 | current_file_function_operand (rtx op, |
2248 | enum machine_mode mode ATTRIBUTE_UNUSED) | |
2af3d377 | 2249 | { |
473f51b6 DE |
2250 | return (GET_CODE (op) == SYMBOL_REF |
2251 | && (DEFAULT_ABI != ABI_AIX || SYMBOL_REF_FUNCTION_P (op)) | |
2252 | && (SYMBOL_REF_LOCAL_P (op) | |
2253 | || (op == XEXP (DECL_RTL (current_function_decl), 0)))); | |
2af3d377 RK |
2254 | } |
2255 | ||
9878760c RK |
2256 | /* Return 1 if this operand is a valid input for a move insn. */ |
2257 | ||
2258 | int | |
a2369ed3 | 2259 | input_operand (rtx op, enum machine_mode mode) |
9878760c | 2260 | { |
eb4e8003 | 2261 | /* Memory is always valid. */ |
9878760c RK |
2262 | if (memory_operand (op, mode)) |
2263 | return 1; | |
2264 | ||
34792e82 | 2265 | /* Only a tiny bit of handling for CONSTANT_P_RTX is necessary. */ |
01b4cf2b | 2266 | if (GET_CODE (op) == CONSTANT_P_RTX) |
34792e82 JL |
2267 | return 1; |
2268 | ||
eb4e8003 RK |
2269 | /* For floating-point, easy constants are valid. */ |
2270 | if (GET_MODE_CLASS (mode) == MODE_FLOAT | |
2271 | && CONSTANT_P (op) | |
2272 | && easy_fp_constant (op, mode)) | |
2273 | return 1; | |
2274 | ||
4e74d8ec MM |
2275 | /* Allow any integer constant. */ |
2276 | if (GET_MODE_CLASS (mode) == MODE_INT | |
e675f625 | 2277 | && (GET_CODE (op) == CONST_INT |
e675f625 | 2278 | || GET_CODE (op) == CONST_DOUBLE)) |
4e74d8ec MM |
2279 | return 1; |
2280 | ||
d744e06e AH |
2281 | /* Allow easy vector constants. */ |
2282 | if (GET_CODE (op) == CONST_VECTOR | |
2283 | && easy_vector_constant (op, mode)) | |
2284 | return 1; | |
2285 | ||
eb4e8003 RK |
2286 | /* For floating-point or multi-word mode, the only remaining valid type |
2287 | is a register. */ | |
9878760c RK |
2288 | if (GET_MODE_CLASS (mode) == MODE_FLOAT |
2289 | || GET_MODE_SIZE (mode) > UNITS_PER_WORD) | |
eb4e8003 | 2290 | return register_operand (op, mode); |
9878760c | 2291 | |
88fe15a1 RK |
2292 | /* The only cases left are integral modes one word or smaller (we |
2293 | do not get called for MODE_CC values). These can be in any | |
2294 | register. */ | |
2295 | if (register_operand (op, mode)) | |
a8b3aeda | 2296 | return 1; |
88fe15a1 | 2297 | |
84cf9dda | 2298 | /* A SYMBOL_REF referring to the TOC is valid. */ |
4d588c14 | 2299 | if (legitimate_constant_pool_address_p (op)) |
84cf9dda RK |
2300 | return 1; |
2301 | ||
9ebbca7d | 2302 | /* A constant pool expression (relative to the TOC) is valid */ |
4d588c14 | 2303 | if (toc_relative_expr_p (op)) |
b6c9286a MM |
2304 | return 1; |
2305 | ||
88228c4b MM |
2306 | /* V.4 allows SYMBOL_REFs and CONSTs that are in the small data region |
2307 | to be valid. */ | |
f607bc57 | 2308 | if (DEFAULT_ABI == ABI_V4 |
88228c4b MM |
2309 | && (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST) |
2310 | && small_data_operand (op, Pmode)) | |
2311 | return 1; | |
2312 | ||
042259f2 | 2313 | return 0; |
9878760c | 2314 | } |
7509c759 | 2315 | |
95727fb8 AP |
2316 | |
2317 | /* Darwin, AIX increases natural record alignment to doubleword if the first | |
2318 | field is an FP double while the FP fields remain word aligned. */ | |
2319 | ||
19d66194 | 2320 | unsigned int |
95727fb8 AP |
2321 | rs6000_special_round_type_align (tree type, int computed, int specified) |
2322 | { | |
2323 | tree field = TYPE_FIELDS (type); | |
95727fb8 AP |
2324 | |
2325 | /* Skip all the static variables only if ABI is greater than | |
2326 | 1 or equal to 0. */ | |
3ce5437a | 2327 | while (field != NULL && TREE_CODE (field) == VAR_DECL) |
95727fb8 AP |
2328 | field = TREE_CHAIN (field); |
2329 | ||
3ce5437a | 2330 | if (field == NULL || field == type || DECL_MODE (field) != DFmode) |
95727fb8 AP |
2331 | return MAX (computed, specified); |
2332 | ||
2333 | return MAX (MAX (computed, specified), 64); | |
2334 | } | |
2335 | ||
a4f6c312 | 2336 | /* Return 1 for an operand in small memory on V.4/eabi. */ |
7509c759 MM |
2337 | |
2338 | int | |
a2369ed3 DJ |
2339 | small_data_operand (rtx op ATTRIBUTE_UNUSED, |
2340 | enum machine_mode mode ATTRIBUTE_UNUSED) | |
7509c759 | 2341 | { |
38c1f2d7 | 2342 | #if TARGET_ELF |
5f59ecb7 | 2343 | rtx sym_ref; |
7509c759 | 2344 | |
d9407988 | 2345 | if (rs6000_sdata == SDATA_NONE || rs6000_sdata == SDATA_DATA) |
a54d04b7 | 2346 | return 0; |
a54d04b7 | 2347 | |
f607bc57 | 2348 | if (DEFAULT_ABI != ABI_V4) |
7509c759 MM |
2349 | return 0; |
2350 | ||
88228c4b MM |
2351 | if (GET_CODE (op) == SYMBOL_REF) |
2352 | sym_ref = op; | |
2353 | ||
2354 | else if (GET_CODE (op) != CONST | |
2355 | || GET_CODE (XEXP (op, 0)) != PLUS | |
2356 | || GET_CODE (XEXP (XEXP (op, 0), 0)) != SYMBOL_REF | |
2357 | || GET_CODE (XEXP (XEXP (op, 0), 1)) != CONST_INT) | |
7509c759 MM |
2358 | return 0; |
2359 | ||
88228c4b | 2360 | else |
dbf55e53 MM |
2361 | { |
2362 | rtx sum = XEXP (op, 0); | |
2363 | HOST_WIDE_INT summand; | |
2364 | ||
2365 | /* We have to be careful here, because it is the referenced address | |
2366 | that must be 32k from _SDA_BASE_, not just the symbol. */ | |
2367 | summand = INTVAL (XEXP (sum, 1)); | |
307b599c | 2368 | if (summand < 0 || (unsigned HOST_WIDE_INT) summand > g_switch_value) |
dbf55e53 MM |
2369 | return 0; |
2370 | ||
2371 | sym_ref = XEXP (sum, 0); | |
2372 | } | |
88228c4b | 2373 | |
20bfcd69 | 2374 | return SYMBOL_REF_SMALL_P (sym_ref); |
d9407988 MM |
2375 | #else |
2376 | return 0; | |
2377 | #endif | |
7509c759 | 2378 | } |
46c07df8 | 2379 | |
d2288d5d HP |
2380 | /* Return true, if operand is a memory operand and has a |
2381 | displacement divisible by 4. */ | |
2382 | ||
2383 | int | |
2384 | word_offset_memref_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) | |
2385 | { | |
2386 | rtx addr; | |
2387 | int off = 0; | |
2388 | ||
2389 | if (!memory_operand (op, mode)) | |
2390 | return 0; | |
2391 | ||
2392 | addr = XEXP (op, 0); | |
2393 | if (GET_CODE (addr) == PLUS | |
2394 | && GET_CODE (XEXP (addr, 0)) == REG | |
2395 | && GET_CODE (XEXP (addr, 1)) == CONST_INT) | |
2396 | off = INTVAL (XEXP (addr, 1)); | |
2397 | ||
2398 | return (off % 4) == 0; | |
2399 | } | |
2400 | ||
3a1f863f | 2401 | /* Return true if either operand is a general purpose register. */ |
46c07df8 | 2402 | |
3a1f863f DE |
2403 | bool |
2404 | gpr_or_gpr_p (rtx op0, rtx op1) | |
46c07df8 | 2405 | { |
3a1f863f DE |
2406 | return ((REG_P (op0) && INT_REGNO_P (REGNO (op0))) |
2407 | || (REG_P (op1) && INT_REGNO_P (REGNO (op1)))); | |
46c07df8 HP |
2408 | } |
2409 | ||
9ebbca7d | 2410 | \f |
4d588c14 RH |
2411 | /* Subroutines of rs6000_legitimize_address and rs6000_legitimate_address. */ |
2412 | ||
9ebbca7d | 2413 | static int |
a2369ed3 | 2414 | constant_pool_expr_1 (rtx op, int *have_sym, int *have_toc) |
9ebbca7d GK |
2415 | { |
2416 | switch (GET_CODE(op)) | |
2417 | { | |
2418 | case SYMBOL_REF: | |
c4501e62 JJ |
2419 | if (RS6000_SYMBOL_REF_TLS_P (op)) |
2420 | return 0; | |
2421 | else if (CONSTANT_POOL_ADDRESS_P (op)) | |
a4f6c312 SS |
2422 | { |
2423 | if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (op), Pmode)) | |
2424 | { | |
2425 | *have_sym = 1; | |
2426 | return 1; | |
2427 | } | |
2428 | else | |
2429 | return 0; | |
2430 | } | |
2431 | else if (! strcmp (XSTR (op, 0), toc_label_name)) | |
2432 | { | |
2433 | *have_toc = 1; | |
2434 | return 1; | |
2435 | } | |
2436 | else | |
2437 | return 0; | |
9ebbca7d GK |
2438 | case PLUS: |
2439 | case MINUS: | |
c1f11548 DE |
2440 | return (constant_pool_expr_1 (XEXP (op, 0), have_sym, have_toc) |
2441 | && constant_pool_expr_1 (XEXP (op, 1), have_sym, have_toc)); | |
9ebbca7d | 2442 | case CONST: |
a4f6c312 | 2443 | return constant_pool_expr_1 (XEXP (op, 0), have_sym, have_toc); |
9ebbca7d | 2444 | case CONST_INT: |
a4f6c312 | 2445 | return 1; |
9ebbca7d | 2446 | default: |
a4f6c312 | 2447 | return 0; |
9ebbca7d GK |
2448 | } |
2449 | } | |
2450 | ||
4d588c14 | 2451 | static bool |
a2369ed3 | 2452 | constant_pool_expr_p (rtx op) |
9ebbca7d GK |
2453 | { |
2454 | int have_sym = 0; | |
2455 | int have_toc = 0; | |
2456 | return constant_pool_expr_1 (op, &have_sym, &have_toc) && have_sym; | |
2457 | } | |
2458 | ||
4d588c14 | 2459 | static bool |
a2369ed3 | 2460 | toc_relative_expr_p (rtx op) |
9ebbca7d | 2461 | { |
4d588c14 RH |
2462 | int have_sym = 0; |
2463 | int have_toc = 0; | |
2464 | return constant_pool_expr_1 (op, &have_sym, &have_toc) && have_toc; | |
2465 | } | |
2466 | ||
2467 | /* SPE offset addressing is limited to 5-bits worth of double words. */ | |
2468 | #define SPE_CONST_OFFSET_OK(x) (((x) & ~0xf8) == 0) | |
2469 | ||
2470 | bool | |
a2369ed3 | 2471 | legitimate_constant_pool_address_p (rtx x) |
4d588c14 RH |
2472 | { |
2473 | return (TARGET_TOC | |
2474 | && GET_CODE (x) == PLUS | |
2475 | && GET_CODE (XEXP (x, 0)) == REG | |
2476 | && (TARGET_MINIMAL_TOC || REGNO (XEXP (x, 0)) == TOC_REGISTER) | |
2477 | && constant_pool_expr_p (XEXP (x, 1))); | |
2478 | } | |
2479 | ||
2480 | static bool | |
a2369ed3 | 2481 | legitimate_small_data_p (enum machine_mode mode, rtx x) |
4d588c14 RH |
2482 | { |
2483 | return (DEFAULT_ABI == ABI_V4 | |
2484 | && !flag_pic && !TARGET_TOC | |
2485 | && (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST) | |
2486 | && small_data_operand (x, mode)); | |
2487 | } | |
2488 | ||
2489 | static bool | |
a2369ed3 | 2490 | legitimate_offset_address_p (enum machine_mode mode, rtx x, int strict) |
4d588c14 RH |
2491 | { |
2492 | unsigned HOST_WIDE_INT offset, extra; | |
2493 | ||
2494 | if (GET_CODE (x) != PLUS) | |
2495 | return false; | |
2496 | if (GET_CODE (XEXP (x, 0)) != REG) | |
2497 | return false; | |
2498 | if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict)) | |
2499 | return false; | |
2500 | if (GET_CODE (XEXP (x, 1)) != CONST_INT) | |
2501 | return false; | |
2502 | ||
2503 | offset = INTVAL (XEXP (x, 1)); | |
2504 | extra = 0; | |
2505 | switch (mode) | |
2506 | { | |
2507 | case V16QImode: | |
2508 | case V8HImode: | |
2509 | case V4SFmode: | |
2510 | case V4SImode: | |
2511 | /* AltiVec vector modes. Only reg+reg addressing is valid here, | |
2512 | which leaves the only valid constant offset of zero, which by | |
2513 | canonicalization rules is also invalid. */ | |
2514 | return false; | |
2515 | ||
2516 | case V4HImode: | |
2517 | case V2SImode: | |
2518 | case V1DImode: | |
2519 | case V2SFmode: | |
2520 | /* SPE vector modes. */ | |
2521 | return SPE_CONST_OFFSET_OK (offset); | |
2522 | ||
2523 | case DFmode: | |
2524 | case DImode: | |
3364872d | 2525 | if (mode == DFmode || !TARGET_POWERPC64) |
4d588c14 RH |
2526 | extra = 4; |
2527 | else if (offset & 3) | |
2528 | return false; | |
2529 | break; | |
2530 | ||
2531 | case TFmode: | |
2532 | case TImode: | |
3364872d | 2533 | if (mode == TFmode || !TARGET_POWERPC64) |
4d588c14 RH |
2534 | extra = 12; |
2535 | else if (offset & 3) | |
2536 | return false; | |
2537 | else | |
2538 | extra = 8; | |
2539 | break; | |
2540 | ||
2541 | default: | |
2542 | break; | |
2543 | } | |
2544 | ||
2545 | return (offset + extra >= offset) && (offset + extra + 0x8000 < 0x10000); | |
2546 | } | |
2547 | ||
2548 | static bool | |
a2369ed3 | 2549 | legitimate_indexed_address_p (rtx x, int strict) |
4d588c14 RH |
2550 | { |
2551 | rtx op0, op1; | |
2552 | ||
2553 | if (GET_CODE (x) != PLUS) | |
2554 | return false; | |
2555 | op0 = XEXP (x, 0); | |
2556 | op1 = XEXP (x, 1); | |
2557 | ||
2558 | if (!REG_P (op0) || !REG_P (op1)) | |
2559 | return false; | |
2560 | ||
2561 | return ((INT_REG_OK_FOR_BASE_P (op0, strict) | |
2562 | && INT_REG_OK_FOR_INDEX_P (op1, strict)) | |
2563 | || (INT_REG_OK_FOR_BASE_P (op1, strict) | |
2564 | && INT_REG_OK_FOR_INDEX_P (op0, strict))); | |
9ebbca7d GK |
2565 | } |
2566 | ||
4d588c14 | 2567 | static inline bool |
a2369ed3 | 2568 | legitimate_indirect_address_p (rtx x, int strict) |
4d588c14 RH |
2569 | { |
2570 | return GET_CODE (x) == REG && INT_REG_OK_FOR_BASE_P (x, strict); | |
2571 | } | |
2572 | ||
4c81e946 FJ |
2573 | static bool |
2574 | macho_lo_sum_memory_operand (rtx x, enum machine_mode mode) | |
2575 | { | |
2576 | if (!TARGET_MACHO || !flag_pic | |
2577 | || mode != SImode || GET_CODE(x) != MEM) | |
2578 | return false; | |
2579 | x = XEXP (x, 0); | |
2580 | ||
2581 | if (GET_CODE (x) != LO_SUM) | |
2582 | return false; | |
2583 | if (GET_CODE (XEXP (x, 0)) != REG) | |
2584 | return false; | |
2585 | if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), 0)) | |
2586 | return false; | |
2587 | x = XEXP (x, 1); | |
2588 | ||
2589 | return CONSTANT_P (x); | |
2590 | } | |
2591 | ||
4d588c14 | 2592 | static bool |
a2369ed3 | 2593 | legitimate_lo_sum_address_p (enum machine_mode mode, rtx x, int strict) |
4d588c14 RH |
2594 | { |
2595 | if (GET_CODE (x) != LO_SUM) | |
2596 | return false; | |
2597 | if (GET_CODE (XEXP (x, 0)) != REG) | |
2598 | return false; | |
2599 | if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict)) | |
2600 | return false; | |
2601 | x = XEXP (x, 1); | |
2602 | ||
8622e235 | 2603 | if (TARGET_ELF || TARGET_MACHO) |
4d588c14 | 2604 | { |
a29077da | 2605 | if (DEFAULT_ABI != ABI_AIX && DEFAULT_ABI != ABI_DARWIN && flag_pic) |
4d588c14 RH |
2606 | return false; |
2607 | if (TARGET_TOC) | |
2608 | return false; | |
2609 | if (GET_MODE_NUNITS (mode) != 1) | |
2610 | return false; | |
2611 | if (GET_MODE_BITSIZE (mode) > 32 | |
2612 | && !(TARGET_HARD_FLOAT && TARGET_FPRS && mode == DFmode)) | |
2613 | return false; | |
2614 | ||
2615 | return CONSTANT_P (x); | |
2616 | } | |
2617 | ||
2618 | return false; | |
2619 | } | |
2620 | ||
2621 | ||
9ebbca7d GK |
2622 | /* Try machine-dependent ways of modifying an illegitimate address |
2623 | to be legitimate. If we find one, return the new, valid address. | |
2624 | This is used from only one place: `memory_address' in explow.c. | |
2625 | ||
a4f6c312 SS |
2626 | OLDX is the address as it was before break_out_memory_refs was |
2627 | called. In some cases it is useful to look at this to decide what | |
2628 | needs to be done. | |
9ebbca7d | 2629 | |
a4f6c312 | 2630 | MODE is passed so that this function can use GO_IF_LEGITIMATE_ADDRESS. |
9ebbca7d | 2631 | |
a4f6c312 SS |
2632 | It is always safe for this function to do nothing. It exists to |
2633 | recognize opportunities to optimize the output. | |
9ebbca7d GK |
2634 | |
2635 | On RS/6000, first check for the sum of a register with a constant | |
2636 | integer that is out of range. If so, generate code to add the | |
2637 | constant with the low-order 16 bits masked to the register and force | |
2638 | this result into another register (this can be done with `cau'). | |
2639 | Then generate an address of REG+(CONST&0xffff), allowing for the | |
2640 | possibility of bit 16 being a one. | |
2641 | ||
2642 | Then check for the sum of a register and something not constant, try to | |
2643 | load the other things into a register and return the sum. */ | |
4d588c14 | 2644 | |
9ebbca7d | 2645 | rtx |
a2369ed3 DJ |
2646 | rs6000_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED, |
2647 | enum machine_mode mode) | |
0ac081f6 | 2648 | { |
c4501e62 JJ |
2649 | if (GET_CODE (x) == SYMBOL_REF) |
2650 | { | |
2651 | enum tls_model model = SYMBOL_REF_TLS_MODEL (x); | |
2652 | if (model != 0) | |
2653 | return rs6000_legitimize_tls_address (x, model); | |
2654 | } | |
2655 | ||
9ebbca7d GK |
2656 | if (GET_CODE (x) == PLUS |
2657 | && GET_CODE (XEXP (x, 0)) == REG | |
2658 | && GET_CODE (XEXP (x, 1)) == CONST_INT | |
2659 | && (unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 1)) + 0x8000) >= 0x10000) | |
2660 | { | |
2661 | HOST_WIDE_INT high_int, low_int; | |
2662 | rtx sum; | |
a65c591c DE |
2663 | low_int = ((INTVAL (XEXP (x, 1)) & 0xffff) ^ 0x8000) - 0x8000; |
2664 | high_int = INTVAL (XEXP (x, 1)) - low_int; | |
9ebbca7d GK |
2665 | sum = force_operand (gen_rtx_PLUS (Pmode, XEXP (x, 0), |
2666 | GEN_INT (high_int)), 0); | |
2667 | return gen_rtx_PLUS (Pmode, sum, GEN_INT (low_int)); | |
2668 | } | |
2669 | else if (GET_CODE (x) == PLUS | |
2670 | && GET_CODE (XEXP (x, 0)) == REG | |
2671 | && GET_CODE (XEXP (x, 1)) != CONST_INT | |
6ac7bf2c | 2672 | && GET_MODE_NUNITS (mode) == 1 |
a3170dc6 AH |
2673 | && ((TARGET_HARD_FLOAT && TARGET_FPRS) |
2674 | || TARGET_POWERPC64 | |
fcce224d | 2675 | || (mode != DFmode && mode != TFmode)) |
9ebbca7d GK |
2676 | && (TARGET_POWERPC64 || mode != DImode) |
2677 | && mode != TImode) | |
2678 | { | |
2679 | return gen_rtx_PLUS (Pmode, XEXP (x, 0), | |
2680 | force_reg (Pmode, force_operand (XEXP (x, 1), 0))); | |
2681 | } | |
0ac081f6 AH |
2682 | else if (ALTIVEC_VECTOR_MODE (mode)) |
2683 | { | |
2684 | rtx reg; | |
2685 | ||
2686 | /* Make sure both operands are registers. */ | |
2687 | if (GET_CODE (x) == PLUS) | |
9f85ed45 | 2688 | return gen_rtx_PLUS (Pmode, force_reg (Pmode, XEXP (x, 0)), |
0ac081f6 AH |
2689 | force_reg (Pmode, XEXP (x, 1))); |
2690 | ||
2691 | reg = force_reg (Pmode, x); | |
2692 | return reg; | |
2693 | } | |
a3170dc6 AH |
2694 | else if (SPE_VECTOR_MODE (mode)) |
2695 | { | |
2696 | /* We accept [reg + reg] and [reg + OFFSET]. */ | |
2697 | ||
2698 | if (GET_CODE (x) == PLUS) | |
2699 | { | |
2700 | rtx op1 = XEXP (x, 0); | |
2701 | rtx op2 = XEXP (x, 1); | |
2702 | ||
2703 | op1 = force_reg (Pmode, op1); | |
2704 | ||
2705 | if (GET_CODE (op2) != REG | |
2706 | && (GET_CODE (op2) != CONST_INT | |
2707 | || !SPE_CONST_OFFSET_OK (INTVAL (op2)))) | |
2708 | op2 = force_reg (Pmode, op2); | |
2709 | ||
2710 | return gen_rtx_PLUS (Pmode, op1, op2); | |
2711 | } | |
2712 | ||
2713 | return force_reg (Pmode, x); | |
2714 | } | |
f1384257 AM |
2715 | else if (TARGET_ELF |
2716 | && TARGET_32BIT | |
2717 | && TARGET_NO_TOC | |
2718 | && ! flag_pic | |
9ebbca7d GK |
2719 | && GET_CODE (x) != CONST_INT |
2720 | && GET_CODE (x) != CONST_DOUBLE | |
2721 | && CONSTANT_P (x) | |
6ac7bf2c GK |
2722 | && GET_MODE_NUNITS (mode) == 1 |
2723 | && (GET_MODE_BITSIZE (mode) <= 32 | |
a3170dc6 | 2724 | || ((TARGET_HARD_FLOAT && TARGET_FPRS) && mode == DFmode))) |
9ebbca7d GK |
2725 | { |
2726 | rtx reg = gen_reg_rtx (Pmode); | |
8a1977f3 GK |
2727 | emit_insn (gen_elf_high (reg, x)); |
2728 | return gen_rtx_LO_SUM (Pmode, reg, x); | |
9ebbca7d | 2729 | } |
ee890fe2 SS |
2730 | else if (TARGET_MACHO && TARGET_32BIT && TARGET_NO_TOC |
2731 | && ! flag_pic | |
ab82a49f AP |
2732 | #if TARGET_MACHO |
2733 | && ! MACHO_DYNAMIC_NO_PIC_P | |
2734 | #endif | |
ee890fe2 SS |
2735 | && GET_CODE (x) != CONST_INT |
2736 | && GET_CODE (x) != CONST_DOUBLE | |
2737 | && CONSTANT_P (x) | |
a3170dc6 | 2738 | && ((TARGET_HARD_FLOAT && TARGET_FPRS) || mode != DFmode) |
ee890fe2 SS |
2739 | && mode != DImode |
2740 | && mode != TImode) | |
2741 | { | |
2742 | rtx reg = gen_reg_rtx (Pmode); | |
8a1977f3 GK |
2743 | emit_insn (gen_macho_high (reg, x)); |
2744 | return gen_rtx_LO_SUM (Pmode, reg, x); | |
ee890fe2 | 2745 | } |
9ebbca7d | 2746 | else if (TARGET_TOC |
4d588c14 | 2747 | && constant_pool_expr_p (x) |
a9098fd0 | 2748 | && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x), Pmode)) |
9ebbca7d GK |
2749 | { |
2750 | return create_TOC_reference (x); | |
2751 | } | |
2752 | else | |
2753 | return NULL_RTX; | |
2754 | } | |
258bfae2 | 2755 | |
c4501e62 JJ |
2756 | /* Construct the SYMBOL_REF for the tls_get_addr function. */ |
2757 | ||
2758 | static GTY(()) rtx rs6000_tls_symbol; | |
2759 | static rtx | |
863d938c | 2760 | rs6000_tls_get_addr (void) |
c4501e62 JJ |
2761 | { |
2762 | if (!rs6000_tls_symbol) | |
2763 | rs6000_tls_symbol = init_one_libfunc ("__tls_get_addr"); | |
2764 | ||
2765 | return rs6000_tls_symbol; | |
2766 | } | |
2767 | ||
2768 | /* Construct the SYMBOL_REF for TLS GOT references. */ | |
2769 | ||
2770 | static GTY(()) rtx rs6000_got_symbol; | |
2771 | static rtx | |
863d938c | 2772 | rs6000_got_sym (void) |
c4501e62 JJ |
2773 | { |
2774 | if (!rs6000_got_symbol) | |
2775 | { | |
2776 | rs6000_got_symbol = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_"); | |
2777 | SYMBOL_REF_FLAGS (rs6000_got_symbol) |= SYMBOL_FLAG_LOCAL; | |
2778 | SYMBOL_REF_FLAGS (rs6000_got_symbol) |= SYMBOL_FLAG_EXTERNAL; | |
2779 | } | |
2780 | ||
2781 | return rs6000_got_symbol; | |
2782 | } | |
2783 | ||
2784 | /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute | |
2785 | this (thread-local) address. */ | |
2786 | ||
2787 | static rtx | |
a2369ed3 | 2788 | rs6000_legitimize_tls_address (rtx addr, enum tls_model model) |
c4501e62 JJ |
2789 | { |
2790 | rtx dest, insn; | |
2791 | ||
2792 | dest = gen_reg_rtx (Pmode); | |
2793 | if (model == TLS_MODEL_LOCAL_EXEC && rs6000_tls_size == 16) | |
2794 | { | |
2795 | rtx tlsreg; | |
2796 | ||
2797 | if (TARGET_64BIT) | |
2798 | { | |
2799 | tlsreg = gen_rtx_REG (Pmode, 13); | |
2800 | insn = gen_tls_tprel_64 (dest, tlsreg, addr); | |
2801 | } | |
2802 | else | |
2803 | { | |
2804 | tlsreg = gen_rtx_REG (Pmode, 2); | |
2805 | insn = gen_tls_tprel_32 (dest, tlsreg, addr); | |
2806 | } | |
2807 | emit_insn (insn); | |
2808 | } | |
2809 | else if (model == TLS_MODEL_LOCAL_EXEC && rs6000_tls_size == 32) | |
2810 | { | |
2811 | rtx tlsreg, tmp; | |
2812 | ||
2813 | tmp = gen_reg_rtx (Pmode); | |
2814 | if (TARGET_64BIT) | |
2815 | { | |
2816 | tlsreg = gen_rtx_REG (Pmode, 13); | |
2817 | insn = gen_tls_tprel_ha_64 (tmp, tlsreg, addr); | |
2818 | } | |
2819 | else | |
2820 | { | |
2821 | tlsreg = gen_rtx_REG (Pmode, 2); | |
2822 | insn = gen_tls_tprel_ha_32 (tmp, tlsreg, addr); | |
2823 | } | |
2824 | emit_insn (insn); | |
2825 | if (TARGET_64BIT) | |
2826 | insn = gen_tls_tprel_lo_64 (dest, tmp, addr); | |
2827 | else | |
2828 | insn = gen_tls_tprel_lo_32 (dest, tmp, addr); | |
2829 | emit_insn (insn); | |
2830 | } | |
2831 | else | |
2832 | { | |
2833 | rtx r3, got, tga, tmp1, tmp2, eqv; | |
2834 | ||
2835 | if (TARGET_64BIT) | |
2836 | got = gen_rtx_REG (Pmode, TOC_REGISTER); | |
2837 | else | |
2838 | { | |
2839 | if (flag_pic == 1) | |
2840 | got = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM); | |
2841 | else | |
2842 | { | |
2843 | rtx gsym = rs6000_got_sym (); | |
2844 | got = gen_reg_rtx (Pmode); | |
2845 | if (flag_pic == 0) | |
2846 | rs6000_emit_move (got, gsym, Pmode); | |
2847 | else | |
2848 | { | |
2849 | char buf[30]; | |
2850 | static int tls_got_labelno = 0; | |
2851 | rtx tempLR, lab, tmp3, mem; | |
2852 | rtx first, last; | |
2853 | ||
2854 | ASM_GENERATE_INTERNAL_LABEL (buf, "LTLS", tls_got_labelno++); | |
2855 | lab = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); | |
2856 | tempLR = gen_reg_rtx (Pmode); | |
2857 | tmp1 = gen_reg_rtx (Pmode); | |
2858 | tmp2 = gen_reg_rtx (Pmode); | |
2859 | tmp3 = gen_reg_rtx (Pmode); | |
2860 | mem = gen_rtx_MEM (Pmode, tmp1); | |
2861 | RTX_UNCHANGING_P (mem) = 1; | |
2862 | ||
2863 | first = emit_insn (gen_load_toc_v4_PIC_1b (tempLR, lab, | |
2864 | gsym)); | |
2865 | emit_move_insn (tmp1, tempLR); | |
2866 | emit_move_insn (tmp2, mem); | |
2867 | emit_insn (gen_addsi3 (tmp3, tmp1, tmp2)); | |
2868 | last = emit_move_insn (got, tmp3); | |
2869 | REG_NOTES (last) = gen_rtx_EXPR_LIST (REG_EQUAL, gsym, | |
2870 | REG_NOTES (last)); | |
2871 | REG_NOTES (first) = gen_rtx_INSN_LIST (REG_LIBCALL, last, | |
2872 | REG_NOTES (first)); | |
2873 | REG_NOTES (last) = gen_rtx_INSN_LIST (REG_RETVAL, first, | |
2874 | REG_NOTES (last)); | |
2875 | } | |
2876 | } | |
2877 | } | |
2878 | ||
2879 | if (model == TLS_MODEL_GLOBAL_DYNAMIC) | |
2880 | { | |
2881 | r3 = gen_rtx_REG (Pmode, 3); | |
2882 | if (TARGET_64BIT) | |
2883 | insn = gen_tls_gd_64 (r3, got, addr); | |
2884 | else | |
2885 | insn = gen_tls_gd_32 (r3, got, addr); | |
2886 | start_sequence (); | |
2887 | emit_insn (insn); | |
2888 | tga = gen_rtx_MEM (Pmode, rs6000_tls_get_addr ()); | |
2889 | insn = gen_call_value (r3, tga, const0_rtx, const0_rtx); | |
2890 | insn = emit_call_insn (insn); | |
2891 | CONST_OR_PURE_CALL_P (insn) = 1; | |
2892 | use_reg (&CALL_INSN_FUNCTION_USAGE (insn), r3); | |
2893 | insn = get_insns (); | |
2894 | end_sequence (); | |
2895 | emit_libcall_block (insn, dest, r3, addr); | |
2896 | } | |
2897 | else if (model == TLS_MODEL_LOCAL_DYNAMIC) | |
2898 | { | |
2899 | r3 = gen_rtx_REG (Pmode, 3); | |
2900 | if (TARGET_64BIT) | |
2901 | insn = gen_tls_ld_64 (r3, got); | |
2902 | else | |
2903 | insn = gen_tls_ld_32 (r3, got); | |
2904 | start_sequence (); | |
2905 | emit_insn (insn); | |
2906 | tga = gen_rtx_MEM (Pmode, rs6000_tls_get_addr ()); | |
2907 | insn = gen_call_value (r3, tga, const0_rtx, const0_rtx); | |
2908 | insn = emit_call_insn (insn); | |
2909 | CONST_OR_PURE_CALL_P (insn) = 1; | |
2910 | use_reg (&CALL_INSN_FUNCTION_USAGE (insn), r3); | |
2911 | insn = get_insns (); | |
2912 | end_sequence (); | |
2913 | tmp1 = gen_reg_rtx (Pmode); | |
2914 | eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), | |
2915 | UNSPEC_TLSLD); | |
2916 | emit_libcall_block (insn, tmp1, r3, eqv); | |
2917 | if (rs6000_tls_size == 16) | |
2918 | { | |
2919 | if (TARGET_64BIT) | |
2920 | insn = gen_tls_dtprel_64 (dest, tmp1, addr); | |
2921 | else | |
2922 | insn = gen_tls_dtprel_32 (dest, tmp1, addr); | |
2923 | } | |
2924 | else if (rs6000_tls_size == 32) | |
2925 | { | |
2926 | tmp2 = gen_reg_rtx (Pmode); | |
2927 | if (TARGET_64BIT) | |
2928 | insn = gen_tls_dtprel_ha_64 (tmp2, tmp1, addr); | |
2929 | else | |
2930 | insn = gen_tls_dtprel_ha_32 (tmp2, tmp1, addr); | |
2931 | emit_insn (insn); | |
2932 | if (TARGET_64BIT) | |
2933 | insn = gen_tls_dtprel_lo_64 (dest, tmp2, addr); | |
2934 | else | |
2935 | insn = gen_tls_dtprel_lo_32 (dest, tmp2, addr); | |
2936 | } | |
2937 | else | |
2938 | { | |
2939 | tmp2 = gen_reg_rtx (Pmode); | |
2940 | if (TARGET_64BIT) | |
2941 | insn = gen_tls_got_dtprel_64 (tmp2, got, addr); | |
2942 | else | |
2943 | insn = gen_tls_got_dtprel_32 (tmp2, got, addr); | |
2944 | emit_insn (insn); | |
2945 | insn = gen_rtx_SET (Pmode, dest, | |
2946 | gen_rtx_PLUS (Pmode, tmp2, tmp1)); | |
2947 | } | |
2948 | emit_insn (insn); | |
2949 | } | |
2950 | else | |
2951 | { | |
2952 | /* IE, or 64 bit offset LE. */ | |
2953 | tmp2 = gen_reg_rtx (Pmode); | |
2954 | if (TARGET_64BIT) | |
2955 | insn = gen_tls_got_tprel_64 (tmp2, got, addr); | |
2956 | else | |
2957 | insn = gen_tls_got_tprel_32 (tmp2, got, addr); | |
2958 | emit_insn (insn); | |
2959 | if (TARGET_64BIT) | |
2960 | insn = gen_tls_tls_64 (dest, tmp2, addr); | |
2961 | else | |
2962 | insn = gen_tls_tls_32 (dest, tmp2, addr); | |
2963 | emit_insn (insn); | |
2964 | } | |
2965 | } | |
2966 | ||
2967 | return dest; | |
2968 | } | |
2969 | ||
2970 | /* Return 1 if X is a SYMBOL_REF for a TLS symbol. This is used in | |
2971 | instruction definitions. */ | |
2972 | ||
2973 | int | |
a2369ed3 | 2974 | rs6000_tls_symbol_ref (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED) |
c4501e62 JJ |
2975 | { |
2976 | return RS6000_SYMBOL_REF_TLS_P (x); | |
2977 | } | |
2978 | ||
2979 | /* Return 1 if X contains a thread-local symbol. */ | |
2980 | ||
2981 | bool | |
a2369ed3 | 2982 | rs6000_tls_referenced_p (rtx x) |
c4501e62 | 2983 | { |
cd413cab AP |
2984 | if (! TARGET_HAVE_TLS) |
2985 | return false; | |
2986 | ||
c4501e62 JJ |
2987 | return for_each_rtx (&x, &rs6000_tls_symbol_ref_1, 0); |
2988 | } | |
2989 | ||
2990 | /* Return 1 if *X is a thread-local symbol. This is the same as | |
2991 | rs6000_tls_symbol_ref except for the type of the unused argument. */ | |
2992 | ||
2993 | static inline int | |
a2369ed3 | 2994 | rs6000_tls_symbol_ref_1 (rtx *x, void *data ATTRIBUTE_UNUSED) |
c4501e62 JJ |
2995 | { |
2996 | return RS6000_SYMBOL_REF_TLS_P (*x); | |
2997 | } | |
2998 | ||
24ea750e DJ |
2999 | /* The convention appears to be to define this wherever it is used. |
3000 | With legitimize_reload_address now defined here, REG_MODE_OK_FOR_BASE_P | |
3001 | is now used here. */ | |
3002 | #ifndef REG_MODE_OK_FOR_BASE_P | |
3003 | #define REG_MODE_OK_FOR_BASE_P(REGNO, MODE) REG_OK_FOR_BASE_P (REGNO) | |
3004 | #endif | |
3005 | ||
3006 | /* Our implementation of LEGITIMIZE_RELOAD_ADDRESS. Returns a value to | |
3007 | replace the input X, or the original X if no replacement is called for. | |
3008 | The output parameter *WIN is 1 if the calling macro should goto WIN, | |
3009 | 0 if it should not. | |
3010 | ||
3011 | For RS/6000, we wish to handle large displacements off a base | |
3012 | register by splitting the addend across an addiu/addis and the mem insn. | |
3013 | This cuts number of extra insns needed from 3 to 1. | |
3014 | ||
3015 | On Darwin, we use this to generate code for floating point constants. | |
3016 | A movsf_low is generated so we wind up with 2 instructions rather than 3. | |
3017 | The Darwin code is inside #if TARGET_MACHO because only then is | |
3018 | machopic_function_base_name() defined. */ | |
3019 | rtx | |
a2369ed3 DJ |
3020 | rs6000_legitimize_reload_address (rtx x, enum machine_mode mode, |
3021 | int opnum, int type, int ind_levels ATTRIBUTE_UNUSED, int *win) | |
24ea750e DJ |
3022 | { |
3023 | /* We must recognize output that we have already generated ourselves. */ | |
3024 | if (GET_CODE (x) == PLUS | |
3025 | && GET_CODE (XEXP (x, 0)) == PLUS | |
3026 | && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG | |
3027 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT | |
3028 | && GET_CODE (XEXP (x, 1)) == CONST_INT) | |
3029 | { | |
3030 | push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL, | |
3031 | BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0, | |
3032 | opnum, (enum reload_type)type); | |
3033 | *win = 1; | |
3034 | return x; | |
3035 | } | |
3deb2758 | 3036 | |
24ea750e DJ |
3037 | #if TARGET_MACHO |
3038 | if (DEFAULT_ABI == ABI_DARWIN && flag_pic | |
3039 | && GET_CODE (x) == LO_SUM | |
3040 | && GET_CODE (XEXP (x, 0)) == PLUS | |
3041 | && XEXP (XEXP (x, 0), 0) == pic_offset_table_rtx | |
3042 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == HIGH | |
3043 | && GET_CODE (XEXP (XEXP (XEXP (x, 0), 1), 0)) == CONST | |
3044 | && XEXP (XEXP (XEXP (x, 0), 1), 0) == XEXP (x, 1) | |
3045 | && GET_CODE (XEXP (XEXP (x, 1), 0)) == MINUS | |
3046 | && GET_CODE (XEXP (XEXP (XEXP (x, 1), 0), 0)) == SYMBOL_REF | |
3047 | && GET_CODE (XEXP (XEXP (XEXP (x, 1), 0), 1)) == SYMBOL_REF) | |
3048 | { | |
3049 | /* Result of previous invocation of this function on Darwin | |
6f317ef3 | 3050 | floating point constant. */ |
24ea750e DJ |
3051 | push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL, |
3052 | BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, | |
3053 | opnum, (enum reload_type)type); | |
3054 | *win = 1; | |
3055 | return x; | |
3056 | } | |
3057 | #endif | |
3058 | if (GET_CODE (x) == PLUS | |
3059 | && GET_CODE (XEXP (x, 0)) == REG | |
3060 | && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER | |
3061 | && REG_MODE_OK_FOR_BASE_P (XEXP (x, 0), mode) | |
78c875e8 | 3062 | && GET_CODE (XEXP (x, 1)) == CONST_INT |
93638d7a | 3063 | && !SPE_VECTOR_MODE (mode) |
78c875e8 | 3064 | && !ALTIVEC_VECTOR_MODE (mode)) |
24ea750e DJ |
3065 | { |
3066 | HOST_WIDE_INT val = INTVAL (XEXP (x, 1)); | |
3067 | HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000; | |
3068 | HOST_WIDE_INT high | |
3069 | = (((val - low) & 0xffffffff) ^ 0x80000000) - 0x80000000; | |
3070 | ||
3071 | /* Check for 32-bit overflow. */ | |
3072 | if (high + low != val) | |
3073 | { | |
3074 | *win = 0; | |
3075 | return x; | |
3076 | } | |
3077 | ||
3078 | /* Reload the high part into a base reg; leave the low part | |
3079 | in the mem directly. */ | |
3080 | ||
3081 | x = gen_rtx_PLUS (GET_MODE (x), | |
3082 | gen_rtx_PLUS (GET_MODE (x), XEXP (x, 0), | |
3083 | GEN_INT (high)), | |
3084 | GEN_INT (low)); | |
3085 | ||
3086 | push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL, | |
3087 | BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0, | |
3088 | opnum, (enum reload_type)type); | |
3089 | *win = 1; | |
3090 | return x; | |
3091 | } | |
3092 | #if TARGET_MACHO | |
3093 | if (GET_CODE (x) == SYMBOL_REF | |
3094 | && DEFAULT_ABI == ABI_DARWIN | |
69ef87e2 | 3095 | && !ALTIVEC_VECTOR_MODE (mode) |
a29077da GK |
3096 | && (flag_pic || MACHO_DYNAMIC_NO_PIC_P) |
3097 | /* Don't do this for TFmode, since the result isn't offsettable. */ | |
3098 | && mode != TFmode) | |
24ea750e | 3099 | { |
a29077da GK |
3100 | if (flag_pic) |
3101 | { | |
3102 | rtx offset = gen_rtx_CONST (Pmode, | |
3103 | gen_rtx_MINUS (Pmode, x, | |
3104 | gen_rtx_SYMBOL_REF (Pmode, | |
3105 | machopic_function_base_name ()))); | |
3106 | x = gen_rtx_LO_SUM (GET_MODE (x), | |
3107 | gen_rtx_PLUS (Pmode, pic_offset_table_rtx, | |
3108 | gen_rtx_HIGH (Pmode, offset)), offset); | |
3109 | } | |
3110 | else | |
3111 | x = gen_rtx_LO_SUM (GET_MODE (x), | |
3112 | gen_rtx_HIGH (Pmode, x), x); | |
3113 | ||
24ea750e | 3114 | push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL, |
a29077da GK |
3115 | BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, |
3116 | opnum, (enum reload_type)type); | |
24ea750e DJ |
3117 | *win = 1; |
3118 | return x; | |
3119 | } | |
3120 | #endif | |
3121 | if (TARGET_TOC | |
4d588c14 | 3122 | && constant_pool_expr_p (x) |
c1f11548 | 3123 | && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x), mode)) |
24ea750e DJ |
3124 | { |
3125 | (x) = create_TOC_reference (x); | |
3126 | *win = 1; | |
3127 | return x; | |
3128 | } | |
3129 | *win = 0; | |
3130 | return x; | |
3131 | } | |
3132 | ||
258bfae2 FS |
3133 | /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression |
3134 | that is a valid memory address for an instruction. | |
3135 | The MODE argument is the machine mode for the MEM expression | |
3136 | that wants to use this address. | |
3137 | ||
3138 | On the RS/6000, there are four valid address: a SYMBOL_REF that | |
3139 | refers to a constant pool entry of an address (or the sum of it | |
3140 | plus a constant), a short (16-bit signed) constant plus a register, | |
3141 | the sum of two registers, or a register indirect, possibly with an | |
5bdc5878 | 3142 | auto-increment. For DFmode and DImode with a constant plus register, |
258bfae2 FS |
3143 | we must ensure that both words are addressable or PowerPC64 with offset |
3144 | word aligned. | |
3145 | ||
3146 | For modes spanning multiple registers (DFmode in 32-bit GPRs, | |
3147 | 32-bit DImode, TImode), indexed addressing cannot be used because | |
3148 | adjacent memory cells are accessed by adding word-sized offsets | |
3149 | during assembly output. */ | |
3150 | int | |
a2369ed3 | 3151 | rs6000_legitimate_address (enum machine_mode mode, rtx x, int reg_ok_strict) |
258bfae2 | 3152 | { |
c4501e62 JJ |
3153 | if (RS6000_SYMBOL_REF_TLS_P (x)) |
3154 | return 0; | |
4d588c14 | 3155 | if (legitimate_indirect_address_p (x, reg_ok_strict)) |
258bfae2 FS |
3156 | return 1; |
3157 | if ((GET_CODE (x) == PRE_INC || GET_CODE (x) == PRE_DEC) | |
0d6d6892 | 3158 | && !ALTIVEC_VECTOR_MODE (mode) |
a3170dc6 | 3159 | && !SPE_VECTOR_MODE (mode) |
258bfae2 | 3160 | && TARGET_UPDATE |
4d588c14 | 3161 | && legitimate_indirect_address_p (XEXP (x, 0), reg_ok_strict)) |
258bfae2 | 3162 | return 1; |
4d588c14 | 3163 | if (legitimate_small_data_p (mode, x)) |
258bfae2 | 3164 | return 1; |
4d588c14 | 3165 | if (legitimate_constant_pool_address_p (x)) |
258bfae2 FS |
3166 | return 1; |
3167 | /* If not REG_OK_STRICT (before reload) let pass any stack offset. */ | |
3168 | if (! reg_ok_strict | |
3169 | && GET_CODE (x) == PLUS | |
3170 | && GET_CODE (XEXP (x, 0)) == REG | |
3171 | && XEXP (x, 0) == virtual_stack_vars_rtx | |
3172 | && GET_CODE (XEXP (x, 1)) == CONST_INT) | |
3173 | return 1; | |
4d588c14 | 3174 | if (legitimate_offset_address_p (mode, x, reg_ok_strict)) |
258bfae2 FS |
3175 | return 1; |
3176 | if (mode != TImode | |
a3170dc6 AH |
3177 | && ((TARGET_HARD_FLOAT && TARGET_FPRS) |
3178 | || TARGET_POWERPC64 | |
fcce224d | 3179 | || (mode != DFmode && mode != TFmode)) |
258bfae2 | 3180 | && (TARGET_POWERPC64 || mode != DImode) |
4d588c14 | 3181 | && legitimate_indexed_address_p (x, reg_ok_strict)) |
258bfae2 | 3182 | return 1; |
4d588c14 | 3183 | if (legitimate_lo_sum_address_p (mode, x, reg_ok_strict)) |
258bfae2 FS |
3184 | return 1; |
3185 | return 0; | |
3186 | } | |
4d588c14 RH |
3187 | |
3188 | /* Go to LABEL if ADDR (a legitimate address expression) | |
3189 | has an effect that depends on the machine mode it is used for. | |
3190 | ||
3191 | On the RS/6000 this is true of all integral offsets (since AltiVec | |
3192 | modes don't allow them) or is a pre-increment or decrement. | |
3193 | ||
3194 | ??? Except that due to conceptual problems in offsettable_address_p | |
3195 | we can't really report the problems of integral offsets. So leave | |
3196 | this assuming that the adjustable offset must be valid for the | |
3197 | sub-words of a TFmode operand, which is what we had before. */ | |
3198 | ||
3199 | bool | |
a2369ed3 | 3200 | rs6000_mode_dependent_address (rtx addr) |
4d588c14 RH |
3201 | { |
3202 | switch (GET_CODE (addr)) | |
3203 | { | |
3204 | case PLUS: | |
3205 | if (GET_CODE (XEXP (addr, 1)) == CONST_INT) | |
3206 | { | |
3207 | unsigned HOST_WIDE_INT val = INTVAL (XEXP (addr, 1)); | |
3208 | return val + 12 + 0x8000 >= 0x10000; | |
3209 | } | |
3210 | break; | |
3211 | ||
3212 | case LO_SUM: | |
3213 | return true; | |
3214 | ||
3215 | case PRE_INC: | |
3216 | case PRE_DEC: | |
3217 | return TARGET_UPDATE; | |
3218 | ||
3219 | default: | |
3220 | break; | |
3221 | } | |
3222 | ||
3223 | return false; | |
3224 | } | |
fb4d4348 | 3225 | \f |
a4f6c312 SS |
3226 | /* Try to output insns to set TARGET equal to the constant C if it can |
3227 | be done in less than N insns. Do all computations in MODE. | |
3228 | Returns the place where the output has been placed if it can be | |
3229 | done and the insns have been emitted. If it would take more than N | |
3230 | insns, zero is returned and no insns and emitted. */ | |
2bfcf297 DB |
3231 | |
3232 | rtx | |
a2369ed3 DJ |
3233 | rs6000_emit_set_const (rtx dest, enum machine_mode mode, |
3234 | rtx source, int n ATTRIBUTE_UNUSED) | |
2bfcf297 | 3235 | { |
af8cb5c5 | 3236 | rtx result, insn, set; |
2bfcf297 DB |
3237 | HOST_WIDE_INT c0, c1; |
3238 | ||
af8cb5c5 | 3239 | if (mode == QImode || mode == HImode) |
2bfcf297 DB |
3240 | { |
3241 | if (dest == NULL) | |
3242 | dest = gen_reg_rtx (mode); | |
3243 | emit_insn (gen_rtx_SET (VOIDmode, dest, source)); | |
3244 | return dest; | |
3245 | } | |
af8cb5c5 | 3246 | else if (mode == SImode) |
2bfcf297 | 3247 | { |
af8cb5c5 DE |
3248 | result = no_new_pseudos ? dest : gen_reg_rtx (SImode); |
3249 | ||
3250 | emit_insn (gen_rtx_SET (VOIDmode, result, | |
3251 | GEN_INT (INTVAL (source) | |
3252 | & (~ (HOST_WIDE_INT) 0xffff)))); | |
3253 | emit_insn (gen_rtx_SET (VOIDmode, dest, | |
3254 | gen_rtx_IOR (SImode, result, | |
3255 | GEN_INT (INTVAL (source) & 0xffff)))); | |
3256 | result = dest; | |
2bfcf297 | 3257 | } |
af8cb5c5 | 3258 | else if (mode == DImode) |
2bfcf297 | 3259 | { |
af8cb5c5 DE |
3260 | if (GET_CODE (source) == CONST_INT) |
3261 | { | |
3262 | c0 = INTVAL (source); | |
3263 | c1 = -(c0 < 0); | |
3264 | } | |
3265 | else if (GET_CODE (source) == CONST_DOUBLE) | |
3266 | { | |
2bfcf297 | 3267 | #if HOST_BITS_PER_WIDE_INT >= 64 |
af8cb5c5 DE |
3268 | c0 = CONST_DOUBLE_LOW (source); |
3269 | c1 = -(c0 < 0); | |
2bfcf297 | 3270 | #else |
af8cb5c5 DE |
3271 | c0 = CONST_DOUBLE_LOW (source); |
3272 | c1 = CONST_DOUBLE_HIGH (source); | |
2bfcf297 | 3273 | #endif |
af8cb5c5 DE |
3274 | } |
3275 | else | |
3276 | abort (); | |
3277 | ||
3278 | result = rs6000_emit_set_long_const (dest, c0, c1); | |
2bfcf297 DB |
3279 | } |
3280 | else | |
a4f6c312 | 3281 | abort (); |
2bfcf297 | 3282 | |
af8cb5c5 DE |
3283 | insn = get_last_insn (); |
3284 | set = single_set (insn); | |
3285 | if (! CONSTANT_P (SET_SRC (set))) | |
3286 | set_unique_reg_note (insn, REG_EQUAL, source); | |
3287 | ||
3288 | return result; | |
2bfcf297 DB |
3289 | } |
3290 | ||
3291 | /* Having failed to find a 3 insn sequence in rs6000_emit_set_const, | |
3292 | fall back to a straight forward decomposition. We do this to avoid | |
3293 | exponential run times encountered when looking for longer sequences | |
3294 | with rs6000_emit_set_const. */ | |
3295 | static rtx | |
a2369ed3 | 3296 | rs6000_emit_set_long_const (rtx dest, HOST_WIDE_INT c1, HOST_WIDE_INT c2) |
2bfcf297 DB |
3297 | { |
3298 | if (!TARGET_POWERPC64) | |
3299 | { | |
3300 | rtx operand1, operand2; | |
3301 | ||
3302 | operand1 = operand_subword_force (dest, WORDS_BIG_ENDIAN == 0, | |
3303 | DImode); | |
3304 | operand2 = operand_subword_force (dest, WORDS_BIG_ENDIAN != 0, | |
3305 | DImode); | |
3306 | emit_move_insn (operand1, GEN_INT (c1)); | |
3307 | emit_move_insn (operand2, GEN_INT (c2)); | |
3308 | } | |
3309 | else | |
3310 | { | |
bc06712d | 3311 | HOST_WIDE_INT ud1, ud2, ud3, ud4; |
252b88f7 | 3312 | |
bc06712d | 3313 | ud1 = c1 & 0xffff; |
f921c9c9 | 3314 | ud2 = (c1 & 0xffff0000) >> 16; |
2bfcf297 | 3315 | #if HOST_BITS_PER_WIDE_INT >= 64 |
bc06712d | 3316 | c2 = c1 >> 32; |
2bfcf297 | 3317 | #endif |
bc06712d | 3318 | ud3 = c2 & 0xffff; |
f921c9c9 | 3319 | ud4 = (c2 & 0xffff0000) >> 16; |
2bfcf297 | 3320 | |
bc06712d TR |
3321 | if ((ud4 == 0xffff && ud3 == 0xffff && ud2 == 0xffff && (ud1 & 0x8000)) |
3322 | || (ud4 == 0 && ud3 == 0 && ud2 == 0 && ! (ud1 & 0x8000))) | |
2bfcf297 | 3323 | { |
bc06712d | 3324 | if (ud1 & 0x8000) |
b78d48dd | 3325 | emit_move_insn (dest, GEN_INT (((ud1 ^ 0x8000) - 0x8000))); |
bc06712d TR |
3326 | else |
3327 | emit_move_insn (dest, GEN_INT (ud1)); | |
2bfcf297 | 3328 | } |
2bfcf297 | 3329 | |
bc06712d TR |
3330 | else if ((ud4 == 0xffff && ud3 == 0xffff && (ud2 & 0x8000)) |
3331 | || (ud4 == 0 && ud3 == 0 && ! (ud2 & 0x8000))) | |
252b88f7 | 3332 | { |
bc06712d TR |
3333 | if (ud2 & 0x8000) |
3334 | emit_move_insn (dest, GEN_INT (((ud2 << 16) ^ 0x80000000) | |
3335 | - 0x80000000)); | |
252b88f7 | 3336 | else |
bc06712d TR |
3337 | emit_move_insn (dest, GEN_INT (ud2 << 16)); |
3338 | if (ud1 != 0) | |
3339 | emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud1))); | |
252b88f7 | 3340 | } |
bc06712d TR |
3341 | else if ((ud4 == 0xffff && (ud3 & 0x8000)) |
3342 | || (ud4 == 0 && ! (ud3 & 0x8000))) | |
3343 | { | |
3344 | if (ud3 & 0x8000) | |
3345 | emit_move_insn (dest, GEN_INT (((ud3 << 16) ^ 0x80000000) | |
3346 | - 0x80000000)); | |
3347 | else | |
3348 | emit_move_insn (dest, GEN_INT (ud3 << 16)); | |
3349 | ||
3350 | if (ud2 != 0) | |
3351 | emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud2))); | |
3352 | emit_move_insn (dest, gen_rtx_ASHIFT (DImode, dest, GEN_INT (16))); | |
3353 | if (ud1 != 0) | |
3354 | emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud1))); | |
3355 | } | |
3356 | else | |
3357 | { | |
3358 | if (ud4 & 0x8000) | |
3359 | emit_move_insn (dest, GEN_INT (((ud4 << 16) ^ 0x80000000) | |
3360 | - 0x80000000)); | |
3361 | else | |
3362 | emit_move_insn (dest, GEN_INT (ud4 << 16)); | |
3363 | ||
3364 | if (ud3 != 0) | |
3365 | emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud3))); | |
2bfcf297 | 3366 | |
bc06712d TR |
3367 | emit_move_insn (dest, gen_rtx_ASHIFT (DImode, dest, GEN_INT (32))); |
3368 | if (ud2 != 0) | |
3369 | emit_move_insn (dest, gen_rtx_IOR (DImode, dest, | |
3370 | GEN_INT (ud2 << 16))); | |
3371 | if (ud1 != 0) | |
3372 | emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud1))); | |
3373 | } | |
3374 | } | |
2bfcf297 DB |
3375 | return dest; |
3376 | } | |
3377 | ||
fb4d4348 GK |
3378 | /* Emit a move from SOURCE to DEST in mode MODE. */ |
3379 | void | |
a2369ed3 | 3380 | rs6000_emit_move (rtx dest, rtx source, enum machine_mode mode) |
fb4d4348 GK |
3381 | { |
3382 | rtx operands[2]; | |
3383 | operands[0] = dest; | |
3384 | operands[1] = source; | |
3385 | ||
3386 | /* Sanity checks. Check that we get CONST_DOUBLE only when we should. */ | |
3387 | if (GET_CODE (operands[1]) == CONST_DOUBLE | |
3388 | && ! FLOAT_MODE_P (mode) | |
3389 | && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT) | |
3390 | { | |
3391 | /* FIXME. This should never happen. */ | |
3392 | /* Since it seems that it does, do the safe thing and convert | |
3393 | to a CONST_INT. */ | |
2496c7bd | 3394 | operands[1] = gen_int_mode (CONST_DOUBLE_LOW (operands[1]), mode); |
fb4d4348 GK |
3395 | } |
3396 | if (GET_CODE (operands[1]) == CONST_DOUBLE | |
3397 | && ! FLOAT_MODE_P (mode) | |
3398 | && ((CONST_DOUBLE_HIGH (operands[1]) == 0 | |
3399 | && CONST_DOUBLE_LOW (operands[1]) >= 0) | |
3400 | || (CONST_DOUBLE_HIGH (operands[1]) == -1 | |
3401 | && CONST_DOUBLE_LOW (operands[1]) < 0))) | |
3402 | abort (); | |
c9e8cb32 DD |
3403 | |
3404 | /* Check if GCC is setting up a block move that will end up using FP | |
3405 | registers as temporaries. We must make sure this is acceptable. */ | |
3406 | if (GET_CODE (operands[0]) == MEM | |
3407 | && GET_CODE (operands[1]) == MEM | |
3408 | && mode == DImode | |
41543739 GK |
3409 | && (SLOW_UNALIGNED_ACCESS (DImode, MEM_ALIGN (operands[0])) |
3410 | || SLOW_UNALIGNED_ACCESS (DImode, MEM_ALIGN (operands[1]))) | |
3411 | && ! (SLOW_UNALIGNED_ACCESS (SImode, (MEM_ALIGN (operands[0]) > 32 | |
3412 | ? 32 : MEM_ALIGN (operands[0]))) | |
3413 | || SLOW_UNALIGNED_ACCESS (SImode, (MEM_ALIGN (operands[1]) > 32 | |
3414 | ? 32 | |
3415 | : MEM_ALIGN (operands[1])))) | |
3416 | && ! MEM_VOLATILE_P (operands [0]) | |
3417 | && ! MEM_VOLATILE_P (operands [1])) | |
c9e8cb32 | 3418 | { |
41543739 GK |
3419 | emit_move_insn (adjust_address (operands[0], SImode, 0), |
3420 | adjust_address (operands[1], SImode, 0)); | |
3421 | emit_move_insn (adjust_address (operands[0], SImode, 4), | |
3422 | adjust_address (operands[1], SImode, 4)); | |
c9e8cb32 DD |
3423 | return; |
3424 | } | |
630d42a0 | 3425 | |
67cef334 DE |
3426 | if (!no_new_pseudos) |
3427 | { | |
3428 | if (GET_CODE (operands[1]) == MEM && optimize > 0 | |
3429 | && (mode == QImode || mode == HImode || mode == SImode) | |
3430 | && GET_MODE_SIZE (mode) < GET_MODE_SIZE (word_mode)) | |
3431 | { | |
3432 | rtx reg = gen_reg_rtx (word_mode); | |
3433 | ||
3434 | emit_insn (gen_rtx_SET (word_mode, reg, | |
3435 | gen_rtx_ZERO_EXTEND (word_mode, | |
3436 | operands[1]))); | |
3437 | operands[1] = gen_lowpart (mode, reg); | |
3438 | } | |
3439 | if (GET_CODE (operands[0]) != REG) | |
3440 | operands[1] = force_reg (mode, operands[1]); | |
3441 | } | |
a9098fd0 | 3442 | |
a3170dc6 AH |
3443 | if (mode == SFmode && ! TARGET_POWERPC |
3444 | && TARGET_HARD_FLOAT && TARGET_FPRS | |
ffc14f31 | 3445 | && GET_CODE (operands[0]) == MEM) |
fb4d4348 | 3446 | { |
ffc14f31 GK |
3447 | int regnum; |
3448 | ||
3449 | if (reload_in_progress || reload_completed) | |
3450 | regnum = true_regnum (operands[1]); | |
3451 | else if (GET_CODE (operands[1]) == REG) | |
3452 | regnum = REGNO (operands[1]); | |
3453 | else | |
3454 | regnum = -1; | |
fb4d4348 GK |
3455 | |
3456 | /* If operands[1] is a register, on POWER it may have | |
3457 | double-precision data in it, so truncate it to single | |
3458 | precision. */ | |
3459 | if (FP_REGNO_P (regnum) || regnum >= FIRST_PSEUDO_REGISTER) | |
3460 | { | |
3461 | rtx newreg; | |
3462 | newreg = (no_new_pseudos ? operands[1] : gen_reg_rtx (mode)); | |
3463 | emit_insn (gen_aux_truncdfsf2 (newreg, operands[1])); | |
3464 | operands[1] = newreg; | |
3465 | } | |
3466 | } | |
3467 | ||
c4501e62 JJ |
3468 | /* Recognize the case where operand[1] is a reference to thread-local |
3469 | data and load its address to a register. */ | |
3470 | if (GET_CODE (operands[1]) == SYMBOL_REF) | |
3471 | { | |
3472 | enum tls_model model = SYMBOL_REF_TLS_MODEL (operands[1]); | |
3473 | if (model != 0) | |
3474 | operands[1] = rs6000_legitimize_tls_address (operands[1], model); | |
3475 | } | |
3476 | ||
8f4e6caf RH |
3477 | /* Handle the case where reload calls us with an invalid address. */ |
3478 | if (reload_in_progress && mode == Pmode | |
69ef87e2 | 3479 | && (! general_operand (operands[1], mode) |
8f4e6caf RH |
3480 | || ! nonimmediate_operand (operands[0], mode))) |
3481 | goto emit_set; | |
3482 | ||
3483 | /* Handle the case of CONSTANT_P_RTX. */ | |
3484 | if (GET_CODE (operands[1]) == CONSTANT_P_RTX) | |
3485 | goto emit_set; | |
a9baceb1 GK |
3486 | |
3487 | /* 128-bit constant floating-point values on Darwin should really be | |
3488 | loaded as two parts. */ | |
3489 | if ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) | |
3490 | && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128 | |
3491 | && mode == TFmode && GET_CODE (operands[1]) == CONST_DOUBLE) | |
3492 | { | |
3493 | /* DImode is used, not DFmode, because simplify_gen_subreg doesn't | |
3494 | know how to get a DFmode SUBREG of a TFmode. */ | |
3495 | rs6000_emit_move (simplify_gen_subreg (DImode, operands[0], mode, 0), | |
3496 | simplify_gen_subreg (DImode, operands[1], mode, 0), | |
3497 | DImode); | |
3498 | rs6000_emit_move (simplify_gen_subreg (DImode, operands[0], mode, | |
3499 | GET_MODE_SIZE (DImode)), | |
3500 | simplify_gen_subreg (DImode, operands[1], mode, | |
3501 | GET_MODE_SIZE (DImode)), | |
3502 | DImode); | |
3503 | return; | |
3504 | } | |
3505 | ||
fb4d4348 GK |
3506 | /* FIXME: In the long term, this switch statement should go away |
3507 | and be replaced by a sequence of tests based on things like | |
3508 | mode == Pmode. */ | |
3509 | switch (mode) | |
3510 | { | |
3511 | case HImode: | |
3512 | case QImode: | |
3513 | if (CONSTANT_P (operands[1]) | |
3514 | && GET_CODE (operands[1]) != CONST_INT) | |
a9098fd0 | 3515 | operands[1] = force_const_mem (mode, operands[1]); |
fb4d4348 GK |
3516 | break; |
3517 | ||
06f4e019 | 3518 | case TFmode: |
fb4d4348 GK |
3519 | case DFmode: |
3520 | case SFmode: | |
3521 | if (CONSTANT_P (operands[1]) | |
3522 | && ! easy_fp_constant (operands[1], mode)) | |
a9098fd0 | 3523 | operands[1] = force_const_mem (mode, operands[1]); |
fb4d4348 GK |
3524 | break; |
3525 | ||
0ac081f6 AH |
3526 | case V16QImode: |
3527 | case V8HImode: | |
3528 | case V4SFmode: | |
3529 | case V4SImode: | |
a3170dc6 AH |
3530 | case V4HImode: |
3531 | case V2SFmode: | |
3532 | case V2SImode: | |
00a892b8 | 3533 | case V1DImode: |
69ef87e2 | 3534 | if (CONSTANT_P (operands[1]) |
d744e06e | 3535 | && !easy_vector_constant (operands[1], mode)) |
0ac081f6 AH |
3536 | operands[1] = force_const_mem (mode, operands[1]); |
3537 | break; | |
3538 | ||
fb4d4348 | 3539 | case SImode: |
a9098fd0 | 3540 | case DImode: |
fb4d4348 GK |
3541 | /* Use default pattern for address of ELF small data */ |
3542 | if (TARGET_ELF | |
a9098fd0 | 3543 | && mode == Pmode |
f607bc57 | 3544 | && DEFAULT_ABI == ABI_V4 |
a9098fd0 GK |
3545 | && (GET_CODE (operands[1]) == SYMBOL_REF |
3546 | || GET_CODE (operands[1]) == CONST) | |
3547 | && small_data_operand (operands[1], mode)) | |
fb4d4348 GK |
3548 | { |
3549 | emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1])); | |
3550 | return; | |
3551 | } | |
3552 | ||
f607bc57 | 3553 | if (DEFAULT_ABI == ABI_V4 |
a9098fd0 GK |
3554 | && mode == Pmode && mode == SImode |
3555 | && flag_pic == 1 && got_operand (operands[1], mode)) | |
fb4d4348 GK |
3556 | { |
3557 | emit_insn (gen_movsi_got (operands[0], operands[1])); | |
3558 | return; | |
3559 | } | |
3560 | ||
ee890fe2 | 3561 | if ((TARGET_ELF || DEFAULT_ABI == ABI_DARWIN) |
f1384257 AM |
3562 | && TARGET_NO_TOC |
3563 | && ! flag_pic | |
a9098fd0 | 3564 | && mode == Pmode |
fb4d4348 GK |
3565 | && CONSTANT_P (operands[1]) |
3566 | && GET_CODE (operands[1]) != HIGH | |
3567 | && GET_CODE (operands[1]) != CONST_INT) | |
3568 | { | |
a9098fd0 | 3569 | rtx target = (no_new_pseudos ? operands[0] : gen_reg_rtx (mode)); |
fb4d4348 GK |
3570 | |
3571 | /* If this is a function address on -mcall-aixdesc, | |
3572 | convert it to the address of the descriptor. */ | |
3573 | if (DEFAULT_ABI == ABI_AIX | |
3574 | && GET_CODE (operands[1]) == SYMBOL_REF | |
3575 | && XSTR (operands[1], 0)[0] == '.') | |
3576 | { | |
3577 | const char *name = XSTR (operands[1], 0); | |
3578 | rtx new_ref; | |
3579 | while (*name == '.') | |
3580 | name++; | |
3581 | new_ref = gen_rtx_SYMBOL_REF (Pmode, name); | |
3582 | CONSTANT_POOL_ADDRESS_P (new_ref) | |
3583 | = CONSTANT_POOL_ADDRESS_P (operands[1]); | |
d1908feb | 3584 | SYMBOL_REF_FLAGS (new_ref) = SYMBOL_REF_FLAGS (operands[1]); |
fb4d4348 | 3585 | SYMBOL_REF_USED (new_ref) = SYMBOL_REF_USED (operands[1]); |
d1908feb | 3586 | SYMBOL_REF_DECL (new_ref) = SYMBOL_REF_DECL (operands[1]); |
fb4d4348 GK |
3587 | operands[1] = new_ref; |
3588 | } | |
7509c759 | 3589 | |
ee890fe2 SS |
3590 | if (DEFAULT_ABI == ABI_DARWIN) |
3591 | { | |
ab82a49f AP |
3592 | #if TARGET_MACHO |
3593 | if (MACHO_DYNAMIC_NO_PIC_P) | |
3594 | { | |
3595 | /* Take care of any required data indirection. */ | |
3596 | operands[1] = rs6000_machopic_legitimize_pic_address ( | |
3597 | operands[1], mode, operands[0]); | |
3598 | if (operands[0] != operands[1]) | |
3599 | emit_insn (gen_rtx_SET (VOIDmode, | |
3600 | operands[0], operands[1])); | |
3601 | return; | |
3602 | } | |
3603 | #endif | |
ee890fe2 SS |
3604 | emit_insn (gen_macho_high (target, operands[1])); |
3605 | emit_insn (gen_macho_low (operands[0], target, operands[1])); | |
3606 | return; | |
3607 | } | |
3608 | ||
fb4d4348 GK |
3609 | emit_insn (gen_elf_high (target, operands[1])); |
3610 | emit_insn (gen_elf_low (operands[0], target, operands[1])); | |
3611 | return; | |
3612 | } | |
3613 | ||
a9098fd0 GK |
3614 | /* If this is a SYMBOL_REF that refers to a constant pool entry, |
3615 | and we have put it in the TOC, we just need to make a TOC-relative | |
3616 | reference to it. */ | |
3617 | if (TARGET_TOC | |
3618 | && GET_CODE (operands[1]) == SYMBOL_REF | |
4d588c14 | 3619 | && constant_pool_expr_p (operands[1]) |
a9098fd0 GK |
3620 | && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (operands[1]), |
3621 | get_pool_mode (operands[1]))) | |
fb4d4348 | 3622 | { |
a9098fd0 | 3623 | operands[1] = create_TOC_reference (operands[1]); |
fb4d4348 | 3624 | } |
a9098fd0 GK |
3625 | else if (mode == Pmode |
3626 | && CONSTANT_P (operands[1]) | |
38886f37 AO |
3627 | && ((GET_CODE (operands[1]) != CONST_INT |
3628 | && ! easy_fp_constant (operands[1], mode)) | |
3629 | || (GET_CODE (operands[1]) == CONST_INT | |
3630 | && num_insns_constant (operands[1], mode) > 2) | |
3631 | || (GET_CODE (operands[0]) == REG | |
3632 | && FP_REGNO_P (REGNO (operands[0])))) | |
a9098fd0 | 3633 | && GET_CODE (operands[1]) != HIGH |
4d588c14 RH |
3634 | && ! legitimate_constant_pool_address_p (operands[1]) |
3635 | && ! toc_relative_expr_p (operands[1])) | |
fb4d4348 GK |
3636 | { |
3637 | /* Emit a USE operation so that the constant isn't deleted if | |
3638 | expensive optimizations are turned on because nobody | |
3639 | references it. This should only be done for operands that | |
3640 | contain SYMBOL_REFs with CONSTANT_POOL_ADDRESS_P set. | |
3641 | This should not be done for operands that contain LABEL_REFs. | |
3642 | For now, we just handle the obvious case. */ | |
3643 | if (GET_CODE (operands[1]) != LABEL_REF) | |
3644 | emit_insn (gen_rtx_USE (VOIDmode, operands[1])); | |
3645 | ||
c859cda6 | 3646 | #if TARGET_MACHO |
ee890fe2 | 3647 | /* Darwin uses a special PIC legitimizer. */ |
ab82a49f | 3648 | if (DEFAULT_ABI == ABI_DARWIN && MACHOPIC_INDIRECT) |
ee890fe2 | 3649 | { |
ee890fe2 SS |
3650 | operands[1] = |
3651 | rs6000_machopic_legitimize_pic_address (operands[1], mode, | |
c859cda6 DJ |
3652 | operands[0]); |
3653 | if (operands[0] != operands[1]) | |
3654 | emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1])); | |
ee890fe2 SS |
3655 | return; |
3656 | } | |
c859cda6 | 3657 | #endif |
ee890fe2 | 3658 | |
fb4d4348 GK |
3659 | /* If we are to limit the number of things we put in the TOC and |
3660 | this is a symbol plus a constant we can add in one insn, | |
3661 | just put the symbol in the TOC and add the constant. Don't do | |
3662 | this if reload is in progress. */ | |
3663 | if (GET_CODE (operands[1]) == CONST | |
3664 | && TARGET_NO_SUM_IN_TOC && ! reload_in_progress | |
3665 | && GET_CODE (XEXP (operands[1], 0)) == PLUS | |
a9098fd0 | 3666 | && add_operand (XEXP (XEXP (operands[1], 0), 1), mode) |
fb4d4348 GK |
3667 | && (GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == LABEL_REF |
3668 | || GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == SYMBOL_REF) | |
3669 | && ! side_effects_p (operands[0])) | |
3670 | { | |
a4f6c312 SS |
3671 | rtx sym = |
3672 | force_const_mem (mode, XEXP (XEXP (operands[1], 0), 0)); | |
fb4d4348 GK |
3673 | rtx other = XEXP (XEXP (operands[1], 0), 1); |
3674 | ||
a9098fd0 GK |
3675 | sym = force_reg (mode, sym); |
3676 | if (mode == SImode) | |
3677 | emit_insn (gen_addsi3 (operands[0], sym, other)); | |
3678 | else | |
3679 | emit_insn (gen_adddi3 (operands[0], sym, other)); | |
fb4d4348 GK |
3680 | return; |
3681 | } | |
3682 | ||
a9098fd0 | 3683 | operands[1] = force_const_mem (mode, operands[1]); |
fb4d4348 GK |
3684 | |
3685 | if (TARGET_TOC | |
4d588c14 | 3686 | && constant_pool_expr_p (XEXP (operands[1], 0)) |
d34c5b80 DE |
3687 | && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P ( |
3688 | get_pool_constant (XEXP (operands[1], 0)), | |
3689 | get_pool_mode (XEXP (operands[1], 0)))) | |
a9098fd0 | 3690 | { |
ba4828e0 RK |
3691 | operands[1] |
3692 | = gen_rtx_MEM (mode, | |
3693 | create_TOC_reference (XEXP (operands[1], 0))); | |
3694 | set_mem_alias_set (operands[1], get_TOC_alias_set ()); | |
fb4d4348 | 3695 | RTX_UNCHANGING_P (operands[1]) = 1; |
a9098fd0 | 3696 | } |
fb4d4348 GK |
3697 | } |
3698 | break; | |
a9098fd0 | 3699 | |
fb4d4348 GK |
3700 | case TImode: |
3701 | if (GET_CODE (operands[0]) == MEM | |
3702 | && GET_CODE (XEXP (operands[0], 0)) != REG | |
3703 | && ! reload_in_progress) | |
792760b9 RK |
3704 | operands[0] |
3705 | = replace_equiv_address (operands[0], | |
3706 | copy_addr_to_reg (XEXP (operands[0], 0))); | |
fb4d4348 GK |
3707 | |
3708 | if (GET_CODE (operands[1]) == MEM | |
3709 | && GET_CODE (XEXP (operands[1], 0)) != REG | |
3710 | && ! reload_in_progress) | |
792760b9 RK |
3711 | operands[1] |
3712 | = replace_equiv_address (operands[1], | |
3713 | copy_addr_to_reg (XEXP (operands[1], 0))); | |
27dc0551 DE |
3714 | if (TARGET_POWER) |
3715 | { | |
3716 | emit_insn (gen_rtx_PARALLEL (VOIDmode, | |
3717 | gen_rtvec (2, | |
3718 | gen_rtx_SET (VOIDmode, | |
3719 | operands[0], operands[1]), | |
3720 | gen_rtx_CLOBBER (VOIDmode, | |
3721 | gen_rtx_SCRATCH (SImode))))); | |
3722 | return; | |
3723 | } | |
fb4d4348 GK |
3724 | break; |
3725 | ||
3726 | default: | |
3727 | abort (); | |
3728 | } | |
3729 | ||
a9098fd0 GK |
3730 | /* Above, we may have called force_const_mem which may have returned |
3731 | an invalid address. If we can, fix this up; otherwise, reload will | |
3732 | have to deal with it. */ | |
8f4e6caf RH |
3733 | if (GET_CODE (operands[1]) == MEM && ! reload_in_progress) |
3734 | operands[1] = validize_mem (operands[1]); | |
a9098fd0 | 3735 | |
8f4e6caf | 3736 | emit_set: |
fb4d4348 GK |
3737 | emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1])); |
3738 | } | |
4697a36c | 3739 | \f |
2858f73a GK |
3740 | /* Nonzero if we can use a floating-point register to pass this arg. */ |
3741 | #define USE_FP_FOR_ARG_P(CUM,MODE,TYPE) \ | |
3742 | (GET_MODE_CLASS (MODE) == MODE_FLOAT \ | |
3743 | && (CUM)->fregno <= FP_ARG_MAX_REG \ | |
3744 | && TARGET_HARD_FLOAT && TARGET_FPRS) | |
3745 | ||
3746 | /* Nonzero if we can use an AltiVec register to pass this arg. */ | |
3747 | #define USE_ALTIVEC_FOR_ARG_P(CUM,MODE,TYPE,NAMED) \ | |
3748 | (ALTIVEC_VECTOR_MODE (MODE) \ | |
3749 | && (CUM)->vregno <= ALTIVEC_ARG_MAX_REG \ | |
3750 | && TARGET_ALTIVEC_ABI \ | |
83953138 | 3751 | && (NAMED)) |
2858f73a | 3752 | |
c6e8c921 GK |
3753 | /* Return a nonzero value to say to return the function value in |
3754 | memory, just as large structures are always returned. TYPE will be | |
3755 | the data type of the value, and FNTYPE will be the type of the | |
3756 | function doing the returning, or @code{NULL} for libcalls. | |
3757 | ||
3758 | The AIX ABI for the RS/6000 specifies that all structures are | |
3759 | returned in memory. The Darwin ABI does the same. The SVR4 ABI | |
3760 | specifies that structures <= 8 bytes are returned in r3/r4, but a | |
3761 | draft put them in memory, and GCC used to implement the draft | |
3762 | instead of the final standard. Therefore, TARGET_AIX_STRUCT_RET | |
3763 | controls this instead of DEFAULT_ABI; V.4 targets needing backward | |
3764 | compatibility can change DRAFT_V4_STRUCT_RET to override the | |
3765 | default, and -m switches get the final word. See | |
3766 | rs6000_override_options for more details. | |
3767 | ||
3768 | The PPC32 SVR4 ABI uses IEEE double extended for long double, if 128-bit | |
3769 | long double support is enabled. These values are returned in memory. | |
3770 | ||
3771 | int_size_in_bytes returns -1 for variable size objects, which go in | |
3772 | memory always. The cast to unsigned makes -1 > 8. */ | |
3773 | ||
3774 | static bool | |
3775 | rs6000_return_in_memory (tree type, tree fntype ATTRIBUTE_UNUSED) | |
3776 | { | |
3777 | if (AGGREGATE_TYPE_P (type) | |
3778 | && (TARGET_AIX_STRUCT_RET | |
3779 | || (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 8)) | |
3780 | return true; | |
3781 | if (DEFAULT_ABI == ABI_V4 && TYPE_MODE (type) == TFmode) | |
3782 | return true; | |
3783 | return false; | |
3784 | } | |
3785 | ||
4697a36c MM |
3786 | /* Initialize a variable CUM of type CUMULATIVE_ARGS |
3787 | for a call to a function whose data type is FNTYPE. | |
3788 | For a library call, FNTYPE is 0. | |
3789 | ||
3790 | For incoming args we set the number of arguments in the prototype large | |
1c20ae99 | 3791 | so we never return a PARALLEL. */ |
4697a36c MM |
3792 | |
3793 | void | |
a2369ed3 | 3794 | init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype, |
0f6937fe AM |
3795 | rtx libname ATTRIBUTE_UNUSED, int incoming, |
3796 | int libcall, int n_named_args) | |
4697a36c MM |
3797 | { |
3798 | static CUMULATIVE_ARGS zero_cumulative; | |
3799 | ||
3800 | *cum = zero_cumulative; | |
3801 | cum->words = 0; | |
3802 | cum->fregno = FP_ARG_MIN_REG; | |
0ac081f6 | 3803 | cum->vregno = ALTIVEC_ARG_MIN_REG; |
4697a36c | 3804 | cum->prototype = (fntype && TYPE_ARG_TYPES (fntype)); |
ddcc8263 DE |
3805 | cum->call_cookie = ((DEFAULT_ABI == ABI_V4 && libcall) |
3806 | ? CALL_LIBCALL : CALL_NORMAL); | |
4cc833b7 | 3807 | cum->sysv_gregno = GP_ARG_MIN_REG; |
a6c9bed4 AH |
3808 | cum->stdarg = fntype |
3809 | && (TYPE_ARG_TYPES (fntype) != 0 | |
3810 | && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype))) | |
3811 | != void_type_node)); | |
4697a36c | 3812 | |
0f6937fe AM |
3813 | cum->nargs_prototype = 0; |
3814 | if (incoming || cum->prototype) | |
3815 | cum->nargs_prototype = n_named_args; | |
4697a36c | 3816 | |
a5c76ee6 ZW |
3817 | /* Check for a longcall attribute. */ |
3818 | if (fntype | |
3819 | && lookup_attribute ("longcall", TYPE_ATTRIBUTES (fntype)) | |
3820 | && !lookup_attribute ("shortcall", TYPE_ATTRIBUTES (fntype))) | |
6a4cee5f MM |
3821 | cum->call_cookie = CALL_LONG; |
3822 | ||
4697a36c MM |
3823 | if (TARGET_DEBUG_ARG) |
3824 | { | |
3825 | fprintf (stderr, "\ninit_cumulative_args:"); | |
3826 | if (fntype) | |
3827 | { | |
3828 | tree ret_type = TREE_TYPE (fntype); | |
3829 | fprintf (stderr, " ret code = %s,", | |
3830 | tree_code_name[ (int)TREE_CODE (ret_type) ]); | |
3831 | } | |
3832 | ||
6a4cee5f MM |
3833 | if (cum->call_cookie & CALL_LONG) |
3834 | fprintf (stderr, " longcall,"); | |
3835 | ||
4697a36c MM |
3836 | fprintf (stderr, " proto = %d, nargs = %d\n", |
3837 | cum->prototype, cum->nargs_prototype); | |
3838 | } | |
3839 | } | |
3840 | \f | |
c229cba9 DE |
3841 | /* If defined, a C expression which determines whether, and in which |
3842 | direction, to pad out an argument with extra space. The value | |
3843 | should be of type `enum direction': either `upward' to pad above | |
3844 | the argument, `downward' to pad below, or `none' to inhibit | |
3845 | padding. | |
3846 | ||
3847 | For the AIX ABI structs are always stored left shifted in their | |
3848 | argument slot. */ | |
3849 | ||
9ebbca7d | 3850 | enum direction |
a2369ed3 | 3851 | function_arg_padding (enum machine_mode mode, tree type) |
c229cba9 | 3852 | { |
6e985040 AM |
3853 | #ifndef AGGREGATE_PADDING_FIXED |
3854 | #define AGGREGATE_PADDING_FIXED 0 | |
3855 | #endif | |
3856 | #ifndef AGGREGATES_PAD_UPWARD_ALWAYS | |
3857 | #define AGGREGATES_PAD_UPWARD_ALWAYS 0 | |
3858 | #endif | |
3859 | ||
3860 | if (!AGGREGATE_PADDING_FIXED) | |
3861 | { | |
3862 | /* GCC used to pass structures of the same size as integer types as | |
3863 | if they were in fact integers, ignoring FUNCTION_ARG_PADDING. | |
3864 | ie. Structures of size 1 or 2 (or 4 when TARGET_64BIT) were | |
3865 | passed padded downward, except that -mstrict-align further | |
3866 | muddied the water in that multi-component structures of 2 and 4 | |
3867 | bytes in size were passed padded upward. | |
3868 | ||
3869 | The following arranges for best compatibility with previous | |
3870 | versions of gcc, but removes the -mstrict-align dependency. */ | |
3871 | if (BYTES_BIG_ENDIAN) | |
3872 | { | |
3873 | HOST_WIDE_INT size = 0; | |
3874 | ||
3875 | if (mode == BLKmode) | |
3876 | { | |
3877 | if (type && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST) | |
3878 | size = int_size_in_bytes (type); | |
3879 | } | |
3880 | else | |
3881 | size = GET_MODE_SIZE (mode); | |
3882 | ||
3883 | if (size == 1 || size == 2 || size == 4) | |
3884 | return downward; | |
3885 | } | |
3886 | return upward; | |
3887 | } | |
3888 | ||
3889 | if (AGGREGATES_PAD_UPWARD_ALWAYS) | |
3890 | { | |
3891 | if (type != 0 && AGGREGATE_TYPE_P (type)) | |
3892 | return upward; | |
3893 | } | |
c229cba9 | 3894 | |
d3704c46 KH |
3895 | /* Fall back to the default. */ |
3896 | return DEFAULT_FUNCTION_ARG_PADDING (mode, type); | |
c229cba9 DE |
3897 | } |
3898 | ||
b6c9286a MM |
3899 | /* If defined, a C expression that gives the alignment boundary, in bits, |
3900 | of an argument with the specified mode and type. If it is not defined, | |
3901 | PARM_BOUNDARY is used for all arguments. | |
3902 | ||
2310f99a | 3903 | V.4 wants long longs to be double word aligned. */ |
b6c9286a MM |
3904 | |
3905 | int | |
a2369ed3 | 3906 | function_arg_boundary (enum machine_mode mode, tree type ATTRIBUTE_UNUSED) |
b6c9286a | 3907 | { |
f607bc57 | 3908 | if (DEFAULT_ABI == ABI_V4 && (mode == DImode || mode == DFmode)) |
e1f83b4d | 3909 | return 64; |
a3170dc6 AH |
3910 | else if (SPE_VECTOR_MODE (mode)) |
3911 | return 64; | |
0ac081f6 AH |
3912 | else if (TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode)) |
3913 | return 128; | |
9ebbca7d | 3914 | else |
b6c9286a | 3915 | return PARM_BOUNDARY; |
b6c9286a MM |
3916 | } |
3917 | \f | |
4697a36c MM |
3918 | /* Update the data in CUM to advance over an argument |
3919 | of mode MODE and data type TYPE. | |
3920 | (TYPE is null for libcalls where that information may not be available.) */ | |
3921 | ||
3922 | void | |
a2369ed3 DJ |
3923 | function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode, |
3924 | tree type, int named) | |
4697a36c MM |
3925 | { |
3926 | cum->nargs_prototype--; | |
3927 | ||
0ac081f6 AH |
3928 | if (TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode)) |
3929 | { | |
2858f73a | 3930 | if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named)) |
0ac081f6 | 3931 | cum->vregno++; |
2858f73a | 3932 | |
c72d6c26 HP |
3933 | /* PowerPC64 Linux and AIX allocates GPRs for a vector argument |
3934 | even if it is going to be passed in a vector register. | |
3935 | Darwin does the same for variable-argument functions. */ | |
3936 | if ((DEFAULT_ABI == ABI_AIX && TARGET_64BIT) | |
3937 | || (cum->stdarg && DEFAULT_ABI != ABI_V4)) | |
3938 | { | |
a594a19c GK |
3939 | int align; |
3940 | ||
2858f73a GK |
3941 | /* Vector parameters must be 16-byte aligned. This places |
3942 | them at 2 mod 4 in terms of words in 32-bit mode, since | |
3943 | the parameter save area starts at offset 24 from the | |
3944 | stack. In 64-bit mode, they just have to start on an | |
3945 | even word, since the parameter save area is 16-byte | |
3946 | aligned. Space for GPRs is reserved even if the argument | |
3947 | will be passed in memory. */ | |
3948 | if (TARGET_32BIT) | |
3949 | align = ((6 - (cum->words & 3)) & 3); | |
3950 | else | |
3951 | align = cum->words & 1; | |
a594a19c | 3952 | cum->words += align + RS6000_ARG_SIZE (mode, type); |
2858f73a | 3953 | |
a594a19c GK |
3954 | if (TARGET_DEBUG_ARG) |
3955 | { | |
3956 | fprintf (stderr, "function_adv: words = %2d, align=%d, ", | |
3957 | cum->words, align); | |
3958 | fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s\n", | |
2858f73a GK |
3959 | cum->nargs_prototype, cum->prototype, |
3960 | GET_MODE_NAME (mode)); | |
a594a19c GK |
3961 | } |
3962 | } | |
0ac081f6 | 3963 | } |
a4b0320c | 3964 | else if (TARGET_SPE_ABI && TARGET_SPE && SPE_VECTOR_MODE (mode) |
a6c9bed4 AH |
3965 | && !cum->stdarg |
3966 | && cum->sysv_gregno <= GP_ARG_MAX_REG) | |
a4b0320c | 3967 | cum->sysv_gregno++; |
f607bc57 | 3968 | else if (DEFAULT_ABI == ABI_V4) |
4697a36c | 3969 | { |
a3170dc6 | 3970 | if (TARGET_HARD_FLOAT && TARGET_FPRS |
4cc833b7 | 3971 | && (mode == SFmode || mode == DFmode)) |
4697a36c | 3972 | { |
4cc833b7 RH |
3973 | if (cum->fregno <= FP_ARG_V4_MAX_REG) |
3974 | cum->fregno++; | |
3975 | else | |
3976 | { | |
3977 | if (mode == DFmode) | |
3978 | cum->words += cum->words & 1; | |
d34c5b80 | 3979 | cum->words += RS6000_ARG_SIZE (mode, type); |
4cc833b7 | 3980 | } |
4697a36c | 3981 | } |
4cc833b7 RH |
3982 | else |
3983 | { | |
3984 | int n_words; | |
3985 | int gregno = cum->sysv_gregno; | |
3986 | ||
3987 | /* Aggregates and IEEE quad get passed by reference. */ | |
3988 | if ((type && AGGREGATE_TYPE_P (type)) | |
3989 | || mode == TFmode) | |
3990 | n_words = 1; | |
3991 | else | |
d34c5b80 | 3992 | n_words = RS6000_ARG_SIZE (mode, type); |
4cc833b7 | 3993 | |
a4b0320c | 3994 | /* Long long and SPE vectors are put in odd registers. */ |
4cc833b7 RH |
3995 | if (n_words == 2 && (gregno & 1) == 0) |
3996 | gregno += 1; | |
3997 | ||
a4b0320c AH |
3998 | /* Long long and SPE vectors are not split between registers |
3999 | and stack. */ | |
4cc833b7 RH |
4000 | if (gregno + n_words - 1 > GP_ARG_MAX_REG) |
4001 | { | |
4002 | /* Long long is aligned on the stack. */ | |
4003 | if (n_words == 2) | |
4004 | cum->words += cum->words & 1; | |
4005 | cum->words += n_words; | |
4006 | } | |
4697a36c | 4007 | |
4cc833b7 RH |
4008 | /* Note: continuing to accumulate gregno past when we've started |
4009 | spilling to the stack indicates the fact that we've started | |
4010 | spilling to the stack to expand_builtin_saveregs. */ | |
4011 | cum->sysv_gregno = gregno + n_words; | |
4012 | } | |
4697a36c | 4013 | |
4cc833b7 RH |
4014 | if (TARGET_DEBUG_ARG) |
4015 | { | |
4016 | fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ", | |
4017 | cum->words, cum->fregno); | |
4018 | fprintf (stderr, "gregno = %2d, nargs = %4d, proto = %d, ", | |
4019 | cum->sysv_gregno, cum->nargs_prototype, cum->prototype); | |
4020 | fprintf (stderr, "mode = %4s, named = %d\n", | |
4021 | GET_MODE_NAME (mode), named); | |
4022 | } | |
4697a36c MM |
4023 | } |
4024 | else | |
4cc833b7 RH |
4025 | { |
4026 | int align = (TARGET_32BIT && (cum->words & 1) != 0 | |
4027 | && function_arg_boundary (mode, type) == 64) ? 1 : 0; | |
a4f6c312 | 4028 | |
d34c5b80 | 4029 | cum->words += align + RS6000_ARG_SIZE (mode, type); |
4697a36c | 4030 | |
a3170dc6 AH |
4031 | if (GET_MODE_CLASS (mode) == MODE_FLOAT |
4032 | && TARGET_HARD_FLOAT && TARGET_FPRS) | |
fcce224d | 4033 | cum->fregno += (mode == TFmode ? 2 : 1); |
4cc833b7 RH |
4034 | |
4035 | if (TARGET_DEBUG_ARG) | |
4036 | { | |
4037 | fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ", | |
4038 | cum->words, cum->fregno); | |
4039 | fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s, ", | |
4040 | cum->nargs_prototype, cum->prototype, GET_MODE_NAME (mode)); | |
4041 | fprintf (stderr, "named = %d, align = %d\n", named, align); | |
4042 | } | |
4043 | } | |
4697a36c | 4044 | } |
a6c9bed4 AH |
4045 | |
4046 | /* Determine where to put a SIMD argument on the SPE. */ | |
b78d48dd | 4047 | |
a6c9bed4 | 4048 | static rtx |
a2369ed3 DJ |
4049 | rs6000_spe_function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode, |
4050 | tree type) | |
a6c9bed4 AH |
4051 | { |
4052 | if (cum->stdarg) | |
4053 | { | |
4054 | int gregno = cum->sysv_gregno; | |
4055 | int n_words = RS6000_ARG_SIZE (mode, type); | |
4056 | ||
4057 | /* SPE vectors are put in odd registers. */ | |
4058 | if (n_words == 2 && (gregno & 1) == 0) | |
4059 | gregno += 1; | |
4060 | ||
4061 | if (gregno + n_words - 1 <= GP_ARG_MAX_REG) | |
4062 | { | |
4063 | rtx r1, r2; | |
4064 | enum machine_mode m = SImode; | |
4065 | ||
4066 | r1 = gen_rtx_REG (m, gregno); | |
4067 | r1 = gen_rtx_EXPR_LIST (m, r1, const0_rtx); | |
4068 | r2 = gen_rtx_REG (m, gregno + 1); | |
4069 | r2 = gen_rtx_EXPR_LIST (m, r2, GEN_INT (4)); | |
4070 | return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r2)); | |
4071 | } | |
4072 | else | |
b78d48dd | 4073 | return NULL_RTX; |
a6c9bed4 AH |
4074 | } |
4075 | else | |
4076 | { | |
4077 | if (cum->sysv_gregno <= GP_ARG_MAX_REG) | |
4078 | return gen_rtx_REG (mode, cum->sysv_gregno); | |
4079 | else | |
b78d48dd | 4080 | return NULL_RTX; |
a6c9bed4 AH |
4081 | } |
4082 | } | |
4083 | ||
b78d48dd FJ |
4084 | /* Determine where to place an argument in 64-bit mode with 32-bit ABI. */ |
4085 | ||
4086 | static rtx | |
4087 | rs6000_mixed_function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode, | |
4088 | tree type, int align_words) | |
4089 | { | |
4090 | if (mode == DFmode) | |
4091 | { | |
4092 | /* -mpowerpc64 with 32bit ABI splits up a DFmode argument | |
4093 | in vararg list into zero, one or two GPRs */ | |
4094 | if (align_words >= GP_ARG_NUM_REG) | |
4095 | return gen_rtx_PARALLEL (DFmode, | |
4096 | gen_rtvec (2, | |
4097 | gen_rtx_EXPR_LIST (VOIDmode, | |
4098 | NULL_RTX, const0_rtx), | |
4099 | gen_rtx_EXPR_LIST (VOIDmode, | |
4100 | gen_rtx_REG (mode, | |
4101 | cum->fregno), | |
4102 | const0_rtx))); | |
4103 | else if (align_words + RS6000_ARG_SIZE (mode, type) | |
4104 | > GP_ARG_NUM_REG) | |
4105 | /* If this is partially on the stack, then we only | |
a3c9585f | 4106 | include the portion actually in registers here. */ |
b78d48dd FJ |
4107 | return gen_rtx_PARALLEL (DFmode, |
4108 | gen_rtvec (2, | |
4109 | gen_rtx_EXPR_LIST (VOIDmode, | |
4110 | gen_rtx_REG (SImode, | |
4111 | GP_ARG_MIN_REG | |
4112 | + align_words), | |
4113 | const0_rtx), | |
4114 | gen_rtx_EXPR_LIST (VOIDmode, | |
4115 | gen_rtx_REG (mode, | |
4116 | cum->fregno), | |
4117 | const0_rtx))); | |
4118 | ||
4119 | /* split a DFmode arg into two GPRs */ | |
4120 | return gen_rtx_PARALLEL (DFmode, | |
4121 | gen_rtvec (3, | |
4122 | gen_rtx_EXPR_LIST (VOIDmode, | |
4123 | gen_rtx_REG (SImode, | |
4124 | GP_ARG_MIN_REG | |
4125 | + align_words), | |
4126 | const0_rtx), | |
4127 | gen_rtx_EXPR_LIST (VOIDmode, | |
4128 | gen_rtx_REG (SImode, | |
4129 | GP_ARG_MIN_REG | |
4130 | + align_words + 1), | |
4131 | GEN_INT (4)), | |
4132 | gen_rtx_EXPR_LIST (VOIDmode, | |
4133 | gen_rtx_REG (mode, cum->fregno), | |
4134 | const0_rtx))); | |
4135 | } | |
4136 | /* -mpowerpc64 with 32bit ABI splits up a DImode argument into one | |
4137 | or two GPRs */ | |
4138 | else if (mode == DImode) | |
4139 | { | |
4140 | if (align_words < GP_ARG_NUM_REG - 1) | |
4141 | return gen_rtx_PARALLEL (DImode, | |
4142 | gen_rtvec (2, | |
4143 | gen_rtx_EXPR_LIST (VOIDmode, | |
4144 | gen_rtx_REG (SImode, | |
4145 | GP_ARG_MIN_REG | |
4146 | + align_words), | |
4147 | const0_rtx), | |
4148 | gen_rtx_EXPR_LIST (VOIDmode, | |
4149 | gen_rtx_REG (SImode, | |
4150 | GP_ARG_MIN_REG | |
4151 | + align_words + 1), | |
4152 | GEN_INT (4)))); | |
4153 | else if (align_words == GP_ARG_NUM_REG - 1) | |
4154 | return gen_rtx_PARALLEL (DImode, | |
4155 | gen_rtvec (2, | |
4156 | gen_rtx_EXPR_LIST (VOIDmode, | |
4157 | NULL_RTX, const0_rtx), | |
4158 | gen_rtx_EXPR_LIST (VOIDmode, | |
4159 | gen_rtx_REG (SImode, | |
4160 | GP_ARG_MIN_REG | |
4161 | + align_words), | |
4162 | const0_rtx))); | |
4163 | } | |
4164 | else if (mode == BLKmode && align_words <= (GP_ARG_NUM_REG - 1)) | |
4165 | { | |
4166 | int k; | |
4167 | int size = int_size_in_bytes (type); | |
2f7b62ef | 4168 | int no_units = ((size - 1) / 4) + 1; |
b78d48dd FJ |
4169 | int max_no_words = GP_ARG_NUM_REG - align_words; |
4170 | int rtlvec_len = no_units < max_no_words ? no_units : max_no_words; | |
4171 | rtx *rtlvec = (rtx *) alloca (rtlvec_len * sizeof (rtx)); | |
4172 | ||
4173 | memset ((char *) rtlvec, 0, rtlvec_len * sizeof (rtx)); | |
4174 | ||
4175 | for (k=0; k < rtlvec_len; k++) | |
4176 | rtlvec[k] = gen_rtx_EXPR_LIST (VOIDmode, | |
4177 | gen_rtx_REG (SImode, | |
4178 | GP_ARG_MIN_REG | |
4179 | + align_words + k), | |
4180 | k == 0 ? const0_rtx : GEN_INT (k*4)); | |
4181 | ||
4182 | return gen_rtx_PARALLEL (BLKmode, gen_rtvec_v (k, rtlvec)); | |
4183 | } | |
4184 | ||
4185 | return NULL_RTX; | |
4186 | } | |
4187 | ||
4697a36c MM |
4188 | /* Determine where to put an argument to a function. |
4189 | Value is zero to push the argument on the stack, | |
4190 | or a hard register in which to store the argument. | |
4191 | ||
4192 | MODE is the argument's machine mode. | |
4193 | TYPE is the data type of the argument (as a tree). | |
4194 | This is null for libcalls where that information may | |
4195 | not be available. | |
4196 | CUM is a variable of type CUMULATIVE_ARGS which gives info about | |
4197 | the preceding args and about the function being called. | |
4198 | NAMED is nonzero if this argument is a named parameter | |
4199 | (otherwise it is an extra parameter matching an ellipsis). | |
4200 | ||
4201 | On RS/6000 the first eight words of non-FP are normally in registers | |
4202 | and the rest are pushed. Under AIX, the first 13 FP args are in registers. | |
4203 | Under V.4, the first 8 FP args are in registers. | |
4204 | ||
4205 | If this is floating-point and no prototype is specified, we use | |
4206 | both an FP and integer register (or possibly FP reg and stack). Library | |
b9599e46 | 4207 | functions (when CALL_LIBCALL is set) always have the proper types for args, |
4697a36c | 4208 | so we can pass the FP value just in one register. emit_library_function |
1c20ae99 | 4209 | doesn't support PARALLEL anyway. */ |
4697a36c MM |
4210 | |
4211 | struct rtx_def * | |
a2369ed3 DJ |
4212 | function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode, |
4213 | tree type, int named) | |
4697a36c | 4214 | { |
4cc833b7 | 4215 | enum rs6000_abi abi = DEFAULT_ABI; |
4697a36c | 4216 | |
a4f6c312 SS |
4217 | /* Return a marker to indicate whether CR1 needs to set or clear the |
4218 | bit that V.4 uses to say fp args were passed in registers. | |
4219 | Assume that we don't need the marker for software floating point, | |
4220 | or compiler generated library calls. */ | |
4697a36c MM |
4221 | if (mode == VOIDmode) |
4222 | { | |
f607bc57 | 4223 | if (abi == ABI_V4 |
7509c759 | 4224 | && cum->nargs_prototype < 0 |
b9599e46 FS |
4225 | && (cum->call_cookie & CALL_LIBCALL) == 0 |
4226 | && (cum->prototype || TARGET_NO_PROTOTYPE)) | |
7509c759 | 4227 | { |
a3170dc6 AH |
4228 | /* For the SPE, we need to crxor CR6 always. */ |
4229 | if (TARGET_SPE_ABI) | |
4230 | return GEN_INT (cum->call_cookie | CALL_V4_SET_FP_ARGS); | |
4231 | else if (TARGET_HARD_FLOAT && TARGET_FPRS) | |
4232 | return GEN_INT (cum->call_cookie | |
4233 | | ((cum->fregno == FP_ARG_MIN_REG) | |
4234 | ? CALL_V4_SET_FP_ARGS | |
4235 | : CALL_V4_CLEAR_FP_ARGS)); | |
7509c759 | 4236 | } |
4697a36c | 4237 | |
7509c759 | 4238 | return GEN_INT (cum->call_cookie); |
4697a36c MM |
4239 | } |
4240 | ||
2858f73a | 4241 | if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named)) |
c72d6c26 HP |
4242 | if (TARGET_64BIT && ! cum->prototype) |
4243 | { | |
4244 | /* Vector parameters get passed in vector register | |
4245 | and also in GPRs or memory, in absence of prototype. */ | |
4246 | int align_words; | |
4247 | rtx slot; | |
4248 | align_words = (cum->words + 1) & ~1; | |
4249 | ||
4250 | if (align_words >= GP_ARG_NUM_REG) | |
4251 | { | |
4252 | slot = NULL_RTX; | |
4253 | } | |
4254 | else | |
4255 | { | |
4256 | slot = gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words); | |
4257 | } | |
4258 | return gen_rtx_PARALLEL (mode, | |
4259 | gen_rtvec (2, | |
4260 | gen_rtx_EXPR_LIST (VOIDmode, | |
4261 | slot, const0_rtx), | |
4262 | gen_rtx_EXPR_LIST (VOIDmode, | |
4263 | gen_rtx_REG (mode, cum->vregno), | |
4264 | const0_rtx))); | |
4265 | } | |
4266 | else | |
4267 | return gen_rtx_REG (mode, cum->vregno); | |
2858f73a | 4268 | else if (TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode)) |
0ac081f6 | 4269 | { |
2858f73a | 4270 | if (named || abi == ABI_V4) |
a594a19c | 4271 | return NULL_RTX; |
0ac081f6 | 4272 | else |
a594a19c GK |
4273 | { |
4274 | /* Vector parameters to varargs functions under AIX or Darwin | |
4275 | get passed in memory and possibly also in GPRs. */ | |
4276 | int align, align_words; | |
2858f73a | 4277 | enum machine_mode part_mode = mode; |
a594a19c GK |
4278 | |
4279 | /* Vector parameters must be 16-byte aligned. This places them at | |
2858f73a GK |
4280 | 2 mod 4 in terms of words in 32-bit mode, since the parameter |
4281 | save area starts at offset 24 from the stack. In 64-bit mode, | |
4282 | they just have to start on an even word, since the parameter | |
4283 | save area is 16-byte aligned. */ | |
4284 | if (TARGET_32BIT) | |
4285 | align = ((6 - (cum->words & 3)) & 3); | |
4286 | else | |
4287 | align = cum->words & 1; | |
a594a19c GK |
4288 | align_words = cum->words + align; |
4289 | ||
4290 | /* Out of registers? Memory, then. */ | |
4291 | if (align_words >= GP_ARG_NUM_REG) | |
4292 | return NULL_RTX; | |
4293 | ||
2858f73a GK |
4294 | /* The vector value goes in GPRs. Only the part of the |
4295 | value in GPRs is reported here. */ | |
4296 | if (align_words + CLASS_MAX_NREGS (mode, GENERAL_REGS) | |
4297 | > GP_ARG_NUM_REG) | |
839a4992 | 4298 | /* Fortunately, there are only two possibilities, the value |
2858f73a GK |
4299 | is either wholly in GPRs or half in GPRs and half not. */ |
4300 | part_mode = DImode; | |
4301 | ||
4302 | return gen_rtx_REG (part_mode, GP_ARG_MIN_REG + align_words); | |
a594a19c | 4303 | } |
0ac081f6 | 4304 | } |
a6c9bed4 AH |
4305 | else if (TARGET_SPE_ABI && TARGET_SPE && SPE_VECTOR_MODE (mode)) |
4306 | return rs6000_spe_function_arg (cum, mode, type); | |
f607bc57 | 4307 | else if (abi == ABI_V4) |
4697a36c | 4308 | { |
a3170dc6 | 4309 | if (TARGET_HARD_FLOAT && TARGET_FPRS |
4cc833b7 RH |
4310 | && (mode == SFmode || mode == DFmode)) |
4311 | { | |
4312 | if (cum->fregno <= FP_ARG_V4_MAX_REG) | |
4313 | return gen_rtx_REG (mode, cum->fregno); | |
4314 | else | |
b78d48dd | 4315 | return NULL_RTX; |
4cc833b7 RH |
4316 | } |
4317 | else | |
4318 | { | |
4319 | int n_words; | |
4320 | int gregno = cum->sysv_gregno; | |
4321 | ||
4322 | /* Aggregates and IEEE quad get passed by reference. */ | |
4323 | if ((type && AGGREGATE_TYPE_P (type)) | |
4324 | || mode == TFmode) | |
4325 | n_words = 1; | |
4326 | else | |
d34c5b80 | 4327 | n_words = RS6000_ARG_SIZE (mode, type); |
4cc833b7 | 4328 | |
a4b0320c | 4329 | /* Long long and SPE vectors are put in odd registers. */ |
4cc833b7 RH |
4330 | if (n_words == 2 && (gregno & 1) == 0) |
4331 | gregno += 1; | |
4332 | ||
a6c9bed4 | 4333 | /* Long long do not split between registers and stack. */ |
4cc833b7 | 4334 | if (gregno + n_words - 1 <= GP_ARG_MAX_REG) |
a6c9bed4 | 4335 | return gen_rtx_REG (mode, gregno); |
4cc833b7 | 4336 | else |
b78d48dd | 4337 | return NULL_RTX; |
4cc833b7 | 4338 | } |
4697a36c | 4339 | } |
4cc833b7 RH |
4340 | else |
4341 | { | |
4342 | int align = (TARGET_32BIT && (cum->words & 1) != 0 | |
4343 | && function_arg_boundary (mode, type) == 64) ? 1 : 0; | |
4344 | int align_words = cum->words + align; | |
4697a36c | 4345 | |
4cc833b7 RH |
4346 | if (type && TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST) |
4347 | return NULL_RTX; | |
4348 | ||
b78d48dd FJ |
4349 | if (TARGET_32BIT && TARGET_POWERPC64 |
4350 | && (mode == DFmode || mode == DImode || mode == BLKmode)) | |
4351 | return rs6000_mixed_function_arg (cum, mode, type, align_words); | |
4352 | ||
2858f73a | 4353 | if (USE_FP_FOR_ARG_P (cum, mode, type)) |
4cc833b7 RH |
4354 | { |
4355 | if (! type | |
4356 | || ((cum->nargs_prototype > 0) | |
4357 | /* IBM AIX extended its linkage convention definition always | |
4358 | to require FP args after register save area hole on the | |
4359 | stack. */ | |
4360 | && (DEFAULT_ABI != ABI_AIX | |
4361 | || ! TARGET_XL_CALL | |
4362 | || (align_words < GP_ARG_NUM_REG)))) | |
4363 | return gen_rtx_REG (mode, cum->fregno); | |
4364 | ||
4365 | return gen_rtx_PARALLEL (mode, | |
4366 | gen_rtvec (2, | |
39403d82 | 4367 | gen_rtx_EXPR_LIST (VOIDmode, |
1c20ae99 JW |
4368 | ((align_words >= GP_ARG_NUM_REG) |
4369 | ? NULL_RTX | |
4370 | : (align_words | |
d34c5b80 | 4371 | + RS6000_ARG_SIZE (mode, type) |
1c20ae99 JW |
4372 | > GP_ARG_NUM_REG |
4373 | /* If this is partially on the stack, then | |
4374 | we only include the portion actually | |
4375 | in registers here. */ | |
fb7e4164 | 4376 | ? gen_rtx_REG (Pmode, |
1c20ae99 | 4377 | GP_ARG_MIN_REG + align_words) |
39403d82 | 4378 | : gen_rtx_REG (mode, |
1c20ae99 JW |
4379 | GP_ARG_MIN_REG + align_words))), |
4380 | const0_rtx), | |
39403d82 DE |
4381 | gen_rtx_EXPR_LIST (VOIDmode, |
4382 | gen_rtx_REG (mode, cum->fregno), | |
1c20ae99 | 4383 | const0_rtx))); |
4cc833b7 RH |
4384 | } |
4385 | else if (align_words < GP_ARG_NUM_REG) | |
4386 | return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words); | |
4387 | else | |
4388 | return NULL_RTX; | |
4697a36c | 4389 | } |
4697a36c MM |
4390 | } |
4391 | \f | |
4392 | /* For an arg passed partly in registers and partly in memory, | |
4393 | this is the number of registers used. | |
4394 | For args passed entirely in registers or entirely in memory, zero. */ | |
4395 | ||
4396 | int | |
a2369ed3 | 4397 | function_arg_partial_nregs (CUMULATIVE_ARGS *cum, enum machine_mode mode, |
2858f73a | 4398 | tree type, int named) |
4697a36c | 4399 | { |
f607bc57 | 4400 | if (DEFAULT_ABI == ABI_V4) |
4697a36c | 4401 | return 0; |
4697a36c | 4402 | |
2858f73a GK |
4403 | if (USE_FP_FOR_ARG_P (cum, mode, type) |
4404 | || USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named)) | |
4697a36c MM |
4405 | { |
4406 | if (cum->nargs_prototype >= 0) | |
4407 | return 0; | |
4408 | } | |
4409 | ||
4410 | if (cum->words < GP_ARG_NUM_REG | |
d34c5b80 | 4411 | && GP_ARG_NUM_REG < (cum->words + RS6000_ARG_SIZE (mode, type))) |
4697a36c MM |
4412 | { |
4413 | int ret = GP_ARG_NUM_REG - cum->words; | |
4414 | if (ret && TARGET_DEBUG_ARG) | |
4415 | fprintf (stderr, "function_arg_partial_nregs: %d\n", ret); | |
4416 | ||
4417 | return ret; | |
4418 | } | |
4419 | ||
4420 | return 0; | |
4421 | } | |
4422 | \f | |
4423 | /* A C expression that indicates when an argument must be passed by | |
4424 | reference. If nonzero for an argument, a copy of that argument is | |
4425 | made in memory and a pointer to the argument is passed instead of | |
4426 | the argument itself. The pointer is passed in whatever way is | |
4427 | appropriate for passing a pointer to that type. | |
4428 | ||
c8c99a68 DE |
4429 | Under V.4, structures and unions are passed by reference. |
4430 | ||
4431 | As an extension to all ABIs, variable sized types are passed by | |
4432 | reference. */ | |
4697a36c MM |
4433 | |
4434 | int | |
a2369ed3 DJ |
4435 | function_arg_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED, |
4436 | enum machine_mode mode ATTRIBUTE_UNUSED, | |
d779d0dc | 4437 | tree type, int named ATTRIBUTE_UNUSED) |
4697a36c | 4438 | { |
f607bc57 | 4439 | if (DEFAULT_ABI == ABI_V4 |
4cc833b7 RH |
4440 | && ((type && AGGREGATE_TYPE_P (type)) |
4441 | || mode == TFmode)) | |
4697a36c MM |
4442 | { |
4443 | if (TARGET_DEBUG_ARG) | |
4444 | fprintf (stderr, "function_arg_pass_by_reference: aggregate\n"); | |
4445 | ||
4446 | return 1; | |
4447 | } | |
fff2cb99 | 4448 | return type && int_size_in_bytes (type) < 0; |
4697a36c | 4449 | } |
5985c7a6 FJ |
4450 | |
4451 | static void | |
2d9db8eb | 4452 | rs6000_move_block_from_reg (int regno, rtx x, int nregs) |
5985c7a6 FJ |
4453 | { |
4454 | int i; | |
4455 | enum machine_mode reg_mode = TARGET_32BIT ? SImode : DImode; | |
4456 | ||
4457 | if (nregs == 0) | |
4458 | return; | |
4459 | ||
4460 | for (i = 0; i < nregs; i++) | |
4461 | { | |
4462 | rtx tem = adjust_address_nv (x, reg_mode, i*GET_MODE_SIZE(reg_mode)); | |
4463 | if (reload_completed) | |
4464 | { | |
4465 | if (! strict_memory_address_p (reg_mode, XEXP (tem, 0))) | |
4466 | tem = NULL_RTX; | |
4467 | else | |
4468 | tem = simplify_gen_subreg (reg_mode, x, BLKmode, | |
4469 | i * GET_MODE_SIZE(reg_mode)); | |
4470 | } | |
4471 | else | |
4472 | tem = replace_equiv_address (tem, XEXP (tem, 0)); | |
4473 | ||
4474 | if (tem == NULL_RTX) | |
4475 | abort (); | |
4476 | ||
4477 | emit_move_insn (tem, gen_rtx_REG (reg_mode, regno + i)); | |
4478 | } | |
4479 | } | |
4480 | ||
4697a36c MM |
4481 | \f |
4482 | /* Perform any needed actions needed for a function that is receiving a | |
4483 | variable number of arguments. | |
4484 | ||
4485 | CUM is as above. | |
4486 | ||
4487 | MODE and TYPE are the mode and type of the current parameter. | |
4488 | ||
4489 | PRETEND_SIZE is a variable that should be set to the amount of stack | |
4490 | that must be pushed by the prolog to pretend that our caller pushed | |
4491 | it. | |
4492 | ||
4493 | Normally, this macro will push all remaining incoming registers on the | |
4494 | stack and set PRETEND_SIZE to the length of the registers pushed. */ | |
4495 | ||
c6e8c921 | 4496 | static void |
a2369ed3 DJ |
4497 | setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode, |
4498 | tree type, int *pretend_size ATTRIBUTE_UNUSED, int no_rtl) | |
4697a36c | 4499 | { |
4cc833b7 RH |
4500 | CUMULATIVE_ARGS next_cum; |
4501 | int reg_size = TARGET_32BIT ? 4 : 8; | |
ca5adc63 | 4502 | rtx save_area = NULL_RTX, mem; |
dfafc897 | 4503 | int first_reg_offset, set; |
4697a36c | 4504 | |
f31bf321 | 4505 | /* Skip the last named argument. */ |
d34c5b80 | 4506 | next_cum = *cum; |
f31bf321 | 4507 | function_arg_advance (&next_cum, mode, type, 1); |
4cc833b7 | 4508 | |
f607bc57 | 4509 | if (DEFAULT_ABI == ABI_V4) |
d34c5b80 | 4510 | { |
4cc833b7 | 4511 | /* Indicate to allocate space on the stack for varargs save area. */ |
00dba523 | 4512 | cfun->machine->sysv_varargs_p = 1; |
60e2d0ca | 4513 | if (! no_rtl) |
2c4974b7 | 4514 | save_area = plus_constant (virtual_stack_vars_rtx, |
bd227acc | 4515 | - RS6000_VARARGS_SIZE); |
4cc833b7 RH |
4516 | |
4517 | first_reg_offset = next_cum.sysv_gregno - GP_ARG_MIN_REG; | |
4697a36c | 4518 | } |
60e2d0ca | 4519 | else |
4697a36c | 4520 | { |
d34c5b80 | 4521 | first_reg_offset = next_cum.words; |
4cc833b7 | 4522 | save_area = virtual_incoming_args_rtx; |
00dba523 | 4523 | cfun->machine->sysv_varargs_p = 0; |
4697a36c MM |
4524 | |
4525 | if (MUST_PASS_IN_STACK (mode, type)) | |
d34c5b80 | 4526 | first_reg_offset += RS6000_ARG_SIZE (TYPE_MODE (type), type); |
4cc833b7 | 4527 | } |
4697a36c | 4528 | |
dfafc897 | 4529 | set = get_varargs_alias_set (); |
c81fc13e | 4530 | if (! no_rtl && first_reg_offset < GP_ARG_NUM_REG) |
4cc833b7 | 4531 | { |
dfafc897 FS |
4532 | mem = gen_rtx_MEM (BLKmode, |
4533 | plus_constant (save_area, | |
4534 | first_reg_offset * reg_size)), | |
ba4828e0 | 4535 | set_mem_alias_set (mem, set); |
8ac61af7 | 4536 | set_mem_align (mem, BITS_PER_WORD); |
dfafc897 | 4537 | |
5985c7a6 FJ |
4538 | rs6000_move_block_from_reg (GP_ARG_MIN_REG + first_reg_offset, mem, |
4539 | GP_ARG_NUM_REG - first_reg_offset); | |
4697a36c MM |
4540 | } |
4541 | ||
4697a36c | 4542 | /* Save FP registers if needed. */ |
f607bc57 | 4543 | if (DEFAULT_ABI == ABI_V4 |
a3170dc6 AH |
4544 | && TARGET_HARD_FLOAT && TARGET_FPRS |
4545 | && ! no_rtl | |
4cc833b7 | 4546 | && next_cum.fregno <= FP_ARG_V4_MAX_REG) |
4697a36c | 4547 | { |
4cc833b7 | 4548 | int fregno = next_cum.fregno; |
9ebbca7d | 4549 | rtx cr1 = gen_rtx_REG (CCmode, CR1_REGNO); |
4cc833b7 RH |
4550 | rtx lab = gen_label_rtx (); |
4551 | int off = (GP_ARG_NUM_REG * reg_size) + ((fregno - FP_ARG_MIN_REG) * 8); | |
4697a36c | 4552 | |
4cc833b7 | 4553 | emit_jump_insn (gen_rtx_SET (VOIDmode, |
4697a36c | 4554 | pc_rtx, |
39403d82 | 4555 | gen_rtx_IF_THEN_ELSE (VOIDmode, |
4cc833b7 RH |
4556 | gen_rtx_NE (VOIDmode, cr1, |
4557 | const0_rtx), | |
39403d82 | 4558 | gen_rtx_LABEL_REF (VOIDmode, lab), |
4697a36c MM |
4559 | pc_rtx))); |
4560 | ||
4cc833b7 RH |
4561 | while (fregno <= FP_ARG_V4_MAX_REG) |
4562 | { | |
dfafc897 | 4563 | mem = gen_rtx_MEM (DFmode, plus_constant (save_area, off)); |
ba4828e0 | 4564 | set_mem_alias_set (mem, set); |
dfafc897 | 4565 | emit_move_insn (mem, gen_rtx_REG (DFmode, fregno)); |
4cc833b7 RH |
4566 | fregno++; |
4567 | off += 8; | |
4697a36c | 4568 | } |
4cc833b7 RH |
4569 | |
4570 | emit_label (lab); | |
4697a36c | 4571 | } |
4697a36c | 4572 | } |
4697a36c | 4573 | |
dfafc897 | 4574 | /* Create the va_list data type. */ |
2c4974b7 | 4575 | |
c35d187f RH |
4576 | static tree |
4577 | rs6000_build_builtin_va_list (void) | |
dfafc897 | 4578 | { |
64c2816f | 4579 | tree f_gpr, f_fpr, f_res, f_ovf, f_sav, record, type_decl; |
4697a36c | 4580 | |
9ebbca7d GK |
4581 | /* For AIX, prefer 'char *' because that's what the system |
4582 | header files like. */ | |
f607bc57 | 4583 | if (DEFAULT_ABI != ABI_V4) |
9ebbca7d | 4584 | return build_pointer_type (char_type_node); |
dfafc897 | 4585 | |
f1e639b1 | 4586 | record = (*lang_hooks.types.make_type) (RECORD_TYPE); |
bab45a51 | 4587 | type_decl = build_decl (TYPE_DECL, get_identifier ("__va_list_tag"), record); |
0f4fd75d | 4588 | |
9ebbca7d GK |
4589 | f_gpr = build_decl (FIELD_DECL, get_identifier ("gpr"), |
4590 | unsigned_char_type_node); | |
4591 | f_fpr = build_decl (FIELD_DECL, get_identifier ("fpr"), | |
4592 | unsigned_char_type_node); | |
64c2816f DT |
4593 | /* Give the two bytes of padding a name, so that -Wpadded won't warn on |
4594 | every user file. */ | |
4595 | f_res = build_decl (FIELD_DECL, get_identifier ("reserved"), | |
4596 | short_unsigned_type_node); | |
dfafc897 FS |
4597 | f_ovf = build_decl (FIELD_DECL, get_identifier ("overflow_arg_area"), |
4598 | ptr_type_node); | |
4599 | f_sav = build_decl (FIELD_DECL, get_identifier ("reg_save_area"), | |
4600 | ptr_type_node); | |
4601 | ||
4602 | DECL_FIELD_CONTEXT (f_gpr) = record; | |
4603 | DECL_FIELD_CONTEXT (f_fpr) = record; | |
64c2816f | 4604 | DECL_FIELD_CONTEXT (f_res) = record; |
dfafc897 FS |
4605 | DECL_FIELD_CONTEXT (f_ovf) = record; |
4606 | DECL_FIELD_CONTEXT (f_sav) = record; | |
4607 | ||
bab45a51 FS |
4608 | TREE_CHAIN (record) = type_decl; |
4609 | TYPE_NAME (record) = type_decl; | |
dfafc897 FS |
4610 | TYPE_FIELDS (record) = f_gpr; |
4611 | TREE_CHAIN (f_gpr) = f_fpr; | |
64c2816f DT |
4612 | TREE_CHAIN (f_fpr) = f_res; |
4613 | TREE_CHAIN (f_res) = f_ovf; | |
dfafc897 FS |
4614 | TREE_CHAIN (f_ovf) = f_sav; |
4615 | ||
4616 | layout_type (record); | |
4617 | ||
4618 | /* The correct type is an array type of one element. */ | |
4619 | return build_array_type (record, build_index_type (size_zero_node)); | |
4620 | } | |
4621 | ||
4622 | /* Implement va_start. */ | |
4623 | ||
4624 | void | |
a2369ed3 | 4625 | rs6000_va_start (tree valist, rtx nextarg) |
4697a36c | 4626 | { |
dfafc897 | 4627 | HOST_WIDE_INT words, n_gpr, n_fpr; |
c566f9bd | 4628 | tree f_gpr, f_fpr, f_res, f_ovf, f_sav; |
dfafc897 | 4629 | tree gpr, fpr, ovf, sav, t; |
2c4974b7 | 4630 | |
dfafc897 | 4631 | /* Only SVR4 needs something special. */ |
f607bc57 | 4632 | if (DEFAULT_ABI != ABI_V4) |
dfafc897 | 4633 | { |
e5faf155 | 4634 | std_expand_builtin_va_start (valist, nextarg); |
dfafc897 FS |
4635 | return; |
4636 | } | |
4637 | ||
973a648b | 4638 | f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node)); |
dfafc897 | 4639 | f_fpr = TREE_CHAIN (f_gpr); |
c566f9bd DT |
4640 | f_res = TREE_CHAIN (f_fpr); |
4641 | f_ovf = TREE_CHAIN (f_res); | |
dfafc897 FS |
4642 | f_sav = TREE_CHAIN (f_ovf); |
4643 | ||
8ebecc3b | 4644 | valist = build1 (INDIRECT_REF, TREE_TYPE (TREE_TYPE (valist)), valist); |
dfafc897 FS |
4645 | gpr = build (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr); |
4646 | fpr = build (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr); | |
4647 | ovf = build (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf); | |
4648 | sav = build (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav); | |
4649 | ||
4650 | /* Count number of gp and fp argument registers used. */ | |
4cc833b7 | 4651 | words = current_function_args_info.words; |
dfafc897 FS |
4652 | n_gpr = current_function_args_info.sysv_gregno - GP_ARG_MIN_REG; |
4653 | n_fpr = current_function_args_info.fregno - FP_ARG_MIN_REG; | |
4654 | ||
4655 | if (TARGET_DEBUG_ARG) | |
4a0a75dd KG |
4656 | fprintf (stderr, "va_start: words = "HOST_WIDE_INT_PRINT_DEC", n_gpr = " |
4657 | HOST_WIDE_INT_PRINT_DEC", n_fpr = "HOST_WIDE_INT_PRINT_DEC"\n", | |
4658 | words, n_gpr, n_fpr); | |
dfafc897 FS |
4659 | |
4660 | t = build (MODIFY_EXPR, TREE_TYPE (gpr), gpr, build_int_2 (n_gpr, 0)); | |
4661 | TREE_SIDE_EFFECTS (t) = 1; | |
4662 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
4663 | ||
4664 | t = build (MODIFY_EXPR, TREE_TYPE (fpr), fpr, build_int_2 (n_fpr, 0)); | |
4665 | TREE_SIDE_EFFECTS (t) = 1; | |
4666 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
4667 | ||
4668 | /* Find the overflow area. */ | |
4669 | t = make_tree (TREE_TYPE (ovf), virtual_incoming_args_rtx); | |
4670 | if (words != 0) | |
4671 | t = build (PLUS_EXPR, TREE_TYPE (ovf), t, | |
4672 | build_int_2 (words * UNITS_PER_WORD, 0)); | |
4673 | t = build (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t); | |
4674 | TREE_SIDE_EFFECTS (t) = 1; | |
4675 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
4676 | ||
4677 | /* Find the register save area. */ | |
4678 | t = make_tree (TREE_TYPE (sav), virtual_stack_vars_rtx); | |
4679 | t = build (PLUS_EXPR, TREE_TYPE (sav), t, | |
4680 | build_int_2 (-RS6000_VARARGS_SIZE, -1)); | |
4681 | t = build (MODIFY_EXPR, TREE_TYPE (sav), sav, t); | |
4682 | TREE_SIDE_EFFECTS (t) = 1; | |
4683 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
4684 | } | |
4685 | ||
4686 | /* Implement va_arg. */ | |
4687 | ||
4688 | rtx | |
a2369ed3 | 4689 | rs6000_va_arg (tree valist, tree type) |
dfafc897 | 4690 | { |
c566f9bd | 4691 | tree f_gpr, f_fpr, f_res, f_ovf, f_sav; |
dfafc897 FS |
4692 | tree gpr, fpr, ovf, sav, reg, t, u; |
4693 | int indirect_p, size, rsize, n_reg, sav_ofs, sav_scale; | |
4694 | rtx lab_false, lab_over, addr_rtx, r; | |
4695 | ||
f607bc57 | 4696 | if (DEFAULT_ABI != ABI_V4) |
c8c99a68 DE |
4697 | { |
4698 | /* Variable sized types are passed by reference. */ | |
fff2cb99 | 4699 | if (int_size_in_bytes (type) < 0) |
c8c99a68 DE |
4700 | { |
4701 | u = build_pointer_type (type); | |
4702 | ||
4703 | /* Args grow upward. */ | |
4704 | t = build (POSTINCREMENT_EXPR, TREE_TYPE (valist), valist, | |
4705 | build_int_2 (POINTER_SIZE / BITS_PER_UNIT, 0)); | |
4706 | TREE_SIDE_EFFECTS (t) = 1; | |
4707 | ||
4708 | t = build1 (NOP_EXPR, build_pointer_type (u), t); | |
4709 | TREE_SIDE_EFFECTS (t) = 1; | |
4710 | ||
4711 | t = build1 (INDIRECT_REF, u, t); | |
4712 | TREE_SIDE_EFFECTS (t) = 1; | |
4713 | ||
4714 | return expand_expr (t, NULL_RTX, VOIDmode, EXPAND_NORMAL); | |
4715 | } | |
4716 | else | |
b0fadda7 | 4717 | return std_expand_builtin_va_arg (valist, type); |
c8c99a68 | 4718 | } |
dfafc897 | 4719 | |
973a648b | 4720 | f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node)); |
dfafc897 | 4721 | f_fpr = TREE_CHAIN (f_gpr); |
c566f9bd DT |
4722 | f_res = TREE_CHAIN (f_fpr); |
4723 | f_ovf = TREE_CHAIN (f_res); | |
dfafc897 FS |
4724 | f_sav = TREE_CHAIN (f_ovf); |
4725 | ||
8ebecc3b | 4726 | valist = build1 (INDIRECT_REF, TREE_TYPE (TREE_TYPE (valist)), valist); |
dfafc897 FS |
4727 | gpr = build (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr); |
4728 | fpr = build (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr); | |
4729 | ovf = build (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf); | |
4730 | sav = build (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav); | |
4731 | ||
4732 | size = int_size_in_bytes (type); | |
4733 | rsize = (size + UNITS_PER_WORD - 1) / UNITS_PER_WORD; | |
4cc833b7 | 4734 | |
dfafc897 | 4735 | if (AGGREGATE_TYPE_P (type) || TYPE_MODE (type) == TFmode) |
4cc833b7 | 4736 | { |
dfafc897 FS |
4737 | /* Aggregates and long doubles are passed by reference. */ |
4738 | indirect_p = 1; | |
4739 | reg = gpr; | |
4740 | n_reg = 1; | |
4741 | sav_ofs = 0; | |
4742 | sav_scale = 4; | |
d3294cd9 FS |
4743 | size = UNITS_PER_WORD; |
4744 | rsize = 1; | |
dfafc897 | 4745 | } |
a3170dc6 | 4746 | else if (FLOAT_TYPE_P (type) && TARGET_HARD_FLOAT && TARGET_FPRS) |
dfafc897 FS |
4747 | { |
4748 | /* FP args go in FP registers, if present. */ | |
4749 | indirect_p = 0; | |
4750 | reg = fpr; | |
4751 | n_reg = 1; | |
4752 | sav_ofs = 8*4; | |
4753 | sav_scale = 8; | |
4cc833b7 | 4754 | } |
dfafc897 FS |
4755 | else |
4756 | { | |
4757 | /* Otherwise into GP registers. */ | |
4758 | indirect_p = 0; | |
4759 | reg = gpr; | |
4760 | n_reg = rsize; | |
4761 | sav_ofs = 0; | |
4762 | sav_scale = 4; | |
4763 | } | |
4764 | ||
a3c9585f | 4765 | /* Pull the value out of the saved registers.... */ |
dfafc897 FS |
4766 | |
4767 | lab_false = gen_label_rtx (); | |
4768 | lab_over = gen_label_rtx (); | |
4769 | addr_rtx = gen_reg_rtx (Pmode); | |
4770 | ||
16861f33 AH |
4771 | /* AltiVec vectors never go in registers. */ |
4772 | if (!TARGET_ALTIVEC || TREE_CODE (type) != VECTOR_TYPE) | |
2c4974b7 | 4773 | { |
41daaf0e AH |
4774 | TREE_THIS_VOLATILE (reg) = 1; |
4775 | emit_cmp_and_jump_insns | |
4776 | (expand_expr (reg, NULL_RTX, QImode, EXPAND_NORMAL), | |
4777 | GEN_INT (8 - n_reg + 1), GE, const1_rtx, QImode, 1, | |
4778 | lab_false); | |
dfafc897 | 4779 | |
41daaf0e AH |
4780 | /* Long long is aligned in the registers. */ |
4781 | if (n_reg > 1) | |
4782 | { | |
4783 | u = build (BIT_AND_EXPR, TREE_TYPE (reg), reg, | |
4784 | build_int_2 (n_reg - 1, 0)); | |
4785 | u = build (PLUS_EXPR, TREE_TYPE (reg), reg, u); | |
4786 | u = build (MODIFY_EXPR, TREE_TYPE (reg), reg, u); | |
4787 | TREE_SIDE_EFFECTS (u) = 1; | |
4788 | expand_expr (u, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
4789 | } | |
2c4974b7 | 4790 | |
41daaf0e AH |
4791 | if (sav_ofs) |
4792 | t = build (PLUS_EXPR, ptr_type_node, sav, build_int_2 (sav_ofs, 0)); | |
4793 | else | |
4794 | t = sav; | |
2c4974b7 | 4795 | |
41daaf0e AH |
4796 | u = build (POSTINCREMENT_EXPR, TREE_TYPE (reg), reg, |
4797 | build_int_2 (n_reg, 0)); | |
4798 | TREE_SIDE_EFFECTS (u) = 1; | |
2c4974b7 | 4799 | |
41daaf0e AH |
4800 | u = build1 (CONVERT_EXPR, integer_type_node, u); |
4801 | TREE_SIDE_EFFECTS (u) = 1; | |
dfafc897 | 4802 | |
41daaf0e AH |
4803 | u = build (MULT_EXPR, integer_type_node, u, build_int_2 (sav_scale, 0)); |
4804 | TREE_SIDE_EFFECTS (u) = 1; | |
dfafc897 | 4805 | |
41daaf0e AH |
4806 | t = build (PLUS_EXPR, ptr_type_node, t, u); |
4807 | TREE_SIDE_EFFECTS (t) = 1; | |
4808 | ||
4809 | r = expand_expr (t, addr_rtx, Pmode, EXPAND_NORMAL); | |
4810 | if (r != addr_rtx) | |
4811 | emit_move_insn (addr_rtx, r); | |
4812 | ||
4813 | emit_jump_insn (gen_jump (lab_over)); | |
4814 | emit_barrier (); | |
4815 | } | |
dfafc897 | 4816 | |
dfafc897 FS |
4817 | emit_label (lab_false); |
4818 | ||
a4f6c312 | 4819 | /* ... otherwise out of the overflow area. */ |
dfafc897 | 4820 | |
41daaf0e AH |
4821 | /* Make sure we don't find reg 7 for the next int arg. |
4822 | ||
4823 | All AltiVec vectors go in the overflow area. So in the AltiVec | |
4824 | case we need to get the vectors from the overflow area, but | |
4825 | remember where the GPRs and FPRs are. */ | |
16861f33 AH |
4826 | if (n_reg > 1 && (TREE_CODE (type) != VECTOR_TYPE |
4827 | || !TARGET_ALTIVEC)) | |
dfafc897 FS |
4828 | { |
4829 | t = build (MODIFY_EXPR, TREE_TYPE (reg), reg, build_int_2 (8, 0)); | |
4830 | TREE_SIDE_EFFECTS (t) = 1; | |
4831 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
4832 | } | |
4833 | ||
4834 | /* Care for on-stack alignment if needed. */ | |
4835 | if (rsize <= 1) | |
4836 | t = ovf; | |
4837 | else | |
4838 | { | |
41daaf0e AH |
4839 | int align; |
4840 | ||
16861f33 AH |
4841 | /* AltiVec vectors are 16 byte aligned. */ |
4842 | if (TARGET_ALTIVEC && TREE_CODE (type) == VECTOR_TYPE) | |
41daaf0e AH |
4843 | align = 15; |
4844 | else | |
4845 | align = 7; | |
4846 | ||
4847 | t = build (PLUS_EXPR, TREE_TYPE (ovf), ovf, build_int_2 (align, 0)); | |
4848 | t = build (BIT_AND_EXPR, TREE_TYPE (t), t, build_int_2 (-align-1, -1)); | |
dfafc897 FS |
4849 | } |
4850 | t = save_expr (t); | |
4851 | ||
4852 | r = expand_expr (t, addr_rtx, Pmode, EXPAND_NORMAL); | |
4853 | if (r != addr_rtx) | |
4854 | emit_move_insn (addr_rtx, r); | |
4855 | ||
4856 | t = build (PLUS_EXPR, TREE_TYPE (t), t, build_int_2 (size, 0)); | |
4857 | t = build (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t); | |
4858 | TREE_SIDE_EFFECTS (t) = 1; | |
4859 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
4860 | ||
4861 | emit_label (lab_over); | |
4862 | ||
4863 | if (indirect_p) | |
4864 | { | |
4865 | r = gen_rtx_MEM (Pmode, addr_rtx); | |
ba4828e0 | 4866 | set_mem_alias_set (r, get_varargs_alias_set ()); |
dfafc897 FS |
4867 | emit_move_insn (addr_rtx, r); |
4868 | } | |
4869 | ||
4870 | return addr_rtx; | |
4697a36c | 4871 | } |
0ac081f6 AH |
4872 | |
4873 | /* Builtins. */ | |
4874 | ||
6a2dd09a RS |
4875 | #define def_builtin(MASK, NAME, TYPE, CODE) \ |
4876 | do { \ | |
4877 | if ((MASK) & target_flags) \ | |
4878 | builtin_function ((NAME), (TYPE), (CODE), BUILT_IN_MD, \ | |
4879 | NULL, NULL_TREE); \ | |
0ac081f6 AH |
4880 | } while (0) |
4881 | ||
24408032 AH |
4882 | /* Simple ternary operations: VECd = foo (VECa, VECb, VECc). */ |
4883 | ||
2212663f | 4884 | static const struct builtin_description bdesc_3arg[] = |
24408032 AH |
4885 | { |
4886 | { MASK_ALTIVEC, CODE_FOR_altivec_vmaddfp, "__builtin_altivec_vmaddfp", ALTIVEC_BUILTIN_VMADDFP }, | |
4887 | { MASK_ALTIVEC, CODE_FOR_altivec_vmhaddshs, "__builtin_altivec_vmhaddshs", ALTIVEC_BUILTIN_VMHADDSHS }, | |
4888 | { MASK_ALTIVEC, CODE_FOR_altivec_vmhraddshs, "__builtin_altivec_vmhraddshs", ALTIVEC_BUILTIN_VMHRADDSHS }, | |
4889 | { MASK_ALTIVEC, CODE_FOR_altivec_vmladduhm, "__builtin_altivec_vmladduhm", ALTIVEC_BUILTIN_VMLADDUHM}, | |
4890 | { MASK_ALTIVEC, CODE_FOR_altivec_vmsumubm, "__builtin_altivec_vmsumubm", ALTIVEC_BUILTIN_VMSUMUBM }, | |
4891 | { MASK_ALTIVEC, CODE_FOR_altivec_vmsummbm, "__builtin_altivec_vmsummbm", ALTIVEC_BUILTIN_VMSUMMBM }, | |
4892 | { MASK_ALTIVEC, CODE_FOR_altivec_vmsumuhm, "__builtin_altivec_vmsumuhm", ALTIVEC_BUILTIN_VMSUMUHM }, | |
4893 | { MASK_ALTIVEC, CODE_FOR_altivec_vmsumshm, "__builtin_altivec_vmsumshm", ALTIVEC_BUILTIN_VMSUMSHM }, | |
4894 | { MASK_ALTIVEC, CODE_FOR_altivec_vmsumuhs, "__builtin_altivec_vmsumuhs", ALTIVEC_BUILTIN_VMSUMUHS }, | |
4895 | { MASK_ALTIVEC, CODE_FOR_altivec_vmsumshs, "__builtin_altivec_vmsumshs", ALTIVEC_BUILTIN_VMSUMSHS }, | |
4896 | { MASK_ALTIVEC, CODE_FOR_altivec_vnmsubfp, "__builtin_altivec_vnmsubfp", ALTIVEC_BUILTIN_VNMSUBFP }, | |
4897 | { MASK_ALTIVEC, CODE_FOR_altivec_vperm_4sf, "__builtin_altivec_vperm_4sf", ALTIVEC_BUILTIN_VPERM_4SF }, | |
4898 | { MASK_ALTIVEC, CODE_FOR_altivec_vperm_4si, "__builtin_altivec_vperm_4si", ALTIVEC_BUILTIN_VPERM_4SI }, | |
4899 | { MASK_ALTIVEC, CODE_FOR_altivec_vperm_8hi, "__builtin_altivec_vperm_8hi", ALTIVEC_BUILTIN_VPERM_8HI }, | |
4900 | { MASK_ALTIVEC, CODE_FOR_altivec_vperm_16qi, "__builtin_altivec_vperm_16qi", ALTIVEC_BUILTIN_VPERM_16QI }, | |
4901 | { MASK_ALTIVEC, CODE_FOR_altivec_vsel_4sf, "__builtin_altivec_vsel_4sf", ALTIVEC_BUILTIN_VSEL_4SF }, | |
4902 | { MASK_ALTIVEC, CODE_FOR_altivec_vsel_4si, "__builtin_altivec_vsel_4si", ALTIVEC_BUILTIN_VSEL_4SI }, | |
4903 | { MASK_ALTIVEC, CODE_FOR_altivec_vsel_8hi, "__builtin_altivec_vsel_8hi", ALTIVEC_BUILTIN_VSEL_8HI }, | |
4904 | { MASK_ALTIVEC, CODE_FOR_altivec_vsel_16qi, "__builtin_altivec_vsel_16qi", ALTIVEC_BUILTIN_VSEL_16QI }, | |
4905 | { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_16qi, "__builtin_altivec_vsldoi_16qi", ALTIVEC_BUILTIN_VSLDOI_16QI }, | |
4906 | { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_8hi, "__builtin_altivec_vsldoi_8hi", ALTIVEC_BUILTIN_VSLDOI_8HI }, | |
4907 | { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_4si, "__builtin_altivec_vsldoi_4si", ALTIVEC_BUILTIN_VSLDOI_4SI }, | |
4908 | { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_4sf, "__builtin_altivec_vsldoi_4sf", ALTIVEC_BUILTIN_VSLDOI_4SF }, | |
4909 | }; | |
2212663f | 4910 | |
95385cbb AH |
4911 | /* DST operations: void foo (void *, const int, const char). */ |
4912 | ||
4913 | static const struct builtin_description bdesc_dst[] = | |
4914 | { | |
4915 | { MASK_ALTIVEC, CODE_FOR_altivec_dst, "__builtin_altivec_dst", ALTIVEC_BUILTIN_DST }, | |
4916 | { MASK_ALTIVEC, CODE_FOR_altivec_dstt, "__builtin_altivec_dstt", ALTIVEC_BUILTIN_DSTT }, | |
4917 | { MASK_ALTIVEC, CODE_FOR_altivec_dstst, "__builtin_altivec_dstst", ALTIVEC_BUILTIN_DSTST }, | |
4918 | { MASK_ALTIVEC, CODE_FOR_altivec_dststt, "__builtin_altivec_dststt", ALTIVEC_BUILTIN_DSTSTT } | |
4919 | }; | |
4920 | ||
2212663f | 4921 | /* Simple binary operations: VECc = foo (VECa, VECb). */ |
24408032 | 4922 | |
a3170dc6 | 4923 | static struct builtin_description bdesc_2arg[] = |
0ac081f6 | 4924 | { |
f18c054f DB |
4925 | { MASK_ALTIVEC, CODE_FOR_addv16qi3, "__builtin_altivec_vaddubm", ALTIVEC_BUILTIN_VADDUBM }, |
4926 | { MASK_ALTIVEC, CODE_FOR_addv8hi3, "__builtin_altivec_vadduhm", ALTIVEC_BUILTIN_VADDUHM }, | |
4927 | { MASK_ALTIVEC, CODE_FOR_addv4si3, "__builtin_altivec_vadduwm", ALTIVEC_BUILTIN_VADDUWM }, | |
4928 | { MASK_ALTIVEC, CODE_FOR_addv4sf3, "__builtin_altivec_vaddfp", ALTIVEC_BUILTIN_VADDFP }, | |
0ac081f6 AH |
4929 | { MASK_ALTIVEC, CODE_FOR_altivec_vaddcuw, "__builtin_altivec_vaddcuw", ALTIVEC_BUILTIN_VADDCUW }, |
4930 | { MASK_ALTIVEC, CODE_FOR_altivec_vaddubs, "__builtin_altivec_vaddubs", ALTIVEC_BUILTIN_VADDUBS }, | |
4931 | { MASK_ALTIVEC, CODE_FOR_altivec_vaddsbs, "__builtin_altivec_vaddsbs", ALTIVEC_BUILTIN_VADDSBS }, | |
4932 | { MASK_ALTIVEC, CODE_FOR_altivec_vadduhs, "__builtin_altivec_vadduhs", ALTIVEC_BUILTIN_VADDUHS }, | |
4933 | { MASK_ALTIVEC, CODE_FOR_altivec_vaddshs, "__builtin_altivec_vaddshs", ALTIVEC_BUILTIN_VADDSHS }, | |
4934 | { MASK_ALTIVEC, CODE_FOR_altivec_vadduws, "__builtin_altivec_vadduws", ALTIVEC_BUILTIN_VADDUWS }, | |
4935 | { MASK_ALTIVEC, CODE_FOR_altivec_vaddsws, "__builtin_altivec_vaddsws", ALTIVEC_BUILTIN_VADDSWS }, | |
f18c054f | 4936 | { MASK_ALTIVEC, CODE_FOR_andv4si3, "__builtin_altivec_vand", ALTIVEC_BUILTIN_VAND }, |
0ac081f6 AH |
4937 | { MASK_ALTIVEC, CODE_FOR_altivec_vandc, "__builtin_altivec_vandc", ALTIVEC_BUILTIN_VANDC }, |
4938 | { MASK_ALTIVEC, CODE_FOR_altivec_vavgub, "__builtin_altivec_vavgub", ALTIVEC_BUILTIN_VAVGUB }, | |
4939 | { MASK_ALTIVEC, CODE_FOR_altivec_vavgsb, "__builtin_altivec_vavgsb", ALTIVEC_BUILTIN_VAVGSB }, | |
4940 | { MASK_ALTIVEC, CODE_FOR_altivec_vavguh, "__builtin_altivec_vavguh", ALTIVEC_BUILTIN_VAVGUH }, | |
4941 | { MASK_ALTIVEC, CODE_FOR_altivec_vavgsh, "__builtin_altivec_vavgsh", ALTIVEC_BUILTIN_VAVGSH }, | |
4942 | { MASK_ALTIVEC, CODE_FOR_altivec_vavguw, "__builtin_altivec_vavguw", ALTIVEC_BUILTIN_VAVGUW }, | |
4943 | { MASK_ALTIVEC, CODE_FOR_altivec_vavgsw, "__builtin_altivec_vavgsw", ALTIVEC_BUILTIN_VAVGSW }, | |
617e0e1d DB |
4944 | { MASK_ALTIVEC, CODE_FOR_altivec_vcfux, "__builtin_altivec_vcfux", ALTIVEC_BUILTIN_VCFUX }, |
4945 | { MASK_ALTIVEC, CODE_FOR_altivec_vcfsx, "__builtin_altivec_vcfsx", ALTIVEC_BUILTIN_VCFSX }, | |
0ac081f6 AH |
4946 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpbfp, "__builtin_altivec_vcmpbfp", ALTIVEC_BUILTIN_VCMPBFP }, |
4947 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequb, "__builtin_altivec_vcmpequb", ALTIVEC_BUILTIN_VCMPEQUB }, | |
4948 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequh, "__builtin_altivec_vcmpequh", ALTIVEC_BUILTIN_VCMPEQUH }, | |
4949 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequw, "__builtin_altivec_vcmpequw", ALTIVEC_BUILTIN_VCMPEQUW }, | |
4950 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpeqfp, "__builtin_altivec_vcmpeqfp", ALTIVEC_BUILTIN_VCMPEQFP }, | |
4951 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgefp, "__builtin_altivec_vcmpgefp", ALTIVEC_BUILTIN_VCMPGEFP }, | |
4952 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtub, "__builtin_altivec_vcmpgtub", ALTIVEC_BUILTIN_VCMPGTUB }, | |
4953 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsb, "__builtin_altivec_vcmpgtsb", ALTIVEC_BUILTIN_VCMPGTSB }, | |
4954 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtuh, "__builtin_altivec_vcmpgtuh", ALTIVEC_BUILTIN_VCMPGTUH }, | |
4955 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsh, "__builtin_altivec_vcmpgtsh", ALTIVEC_BUILTIN_VCMPGTSH }, | |
4956 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtuw, "__builtin_altivec_vcmpgtuw", ALTIVEC_BUILTIN_VCMPGTUW }, | |
4957 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsw, "__builtin_altivec_vcmpgtsw", ALTIVEC_BUILTIN_VCMPGTSW }, | |
4958 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtfp, "__builtin_altivec_vcmpgtfp", ALTIVEC_BUILTIN_VCMPGTFP }, | |
617e0e1d DB |
4959 | { MASK_ALTIVEC, CODE_FOR_altivec_vctsxs, "__builtin_altivec_vctsxs", ALTIVEC_BUILTIN_VCTSXS }, |
4960 | { MASK_ALTIVEC, CODE_FOR_altivec_vctuxs, "__builtin_altivec_vctuxs", ALTIVEC_BUILTIN_VCTUXS }, | |
f18c054f DB |
4961 | { MASK_ALTIVEC, CODE_FOR_umaxv16qi3, "__builtin_altivec_vmaxub", ALTIVEC_BUILTIN_VMAXUB }, |
4962 | { MASK_ALTIVEC, CODE_FOR_smaxv16qi3, "__builtin_altivec_vmaxsb", ALTIVEC_BUILTIN_VMAXSB }, | |
df966bff AH |
4963 | { MASK_ALTIVEC, CODE_FOR_umaxv8hi3, "__builtin_altivec_vmaxuh", ALTIVEC_BUILTIN_VMAXUH }, |
4964 | { MASK_ALTIVEC, CODE_FOR_smaxv8hi3, "__builtin_altivec_vmaxsh", ALTIVEC_BUILTIN_VMAXSH }, | |
4965 | { MASK_ALTIVEC, CODE_FOR_umaxv4si3, "__builtin_altivec_vmaxuw", ALTIVEC_BUILTIN_VMAXUW }, | |
4966 | { MASK_ALTIVEC, CODE_FOR_smaxv4si3, "__builtin_altivec_vmaxsw", ALTIVEC_BUILTIN_VMAXSW }, | |
4967 | { MASK_ALTIVEC, CODE_FOR_smaxv4sf3, "__builtin_altivec_vmaxfp", ALTIVEC_BUILTIN_VMAXFP }, | |
0ac081f6 AH |
4968 | { MASK_ALTIVEC, CODE_FOR_altivec_vmrghb, "__builtin_altivec_vmrghb", ALTIVEC_BUILTIN_VMRGHB }, |
4969 | { MASK_ALTIVEC, CODE_FOR_altivec_vmrghh, "__builtin_altivec_vmrghh", ALTIVEC_BUILTIN_VMRGHH }, | |
4970 | { MASK_ALTIVEC, CODE_FOR_altivec_vmrghw, "__builtin_altivec_vmrghw", ALTIVEC_BUILTIN_VMRGHW }, | |
4971 | { MASK_ALTIVEC, CODE_FOR_altivec_vmrglb, "__builtin_altivec_vmrglb", ALTIVEC_BUILTIN_VMRGLB }, | |
4972 | { MASK_ALTIVEC, CODE_FOR_altivec_vmrglh, "__builtin_altivec_vmrglh", ALTIVEC_BUILTIN_VMRGLH }, | |
4973 | { MASK_ALTIVEC, CODE_FOR_altivec_vmrglw, "__builtin_altivec_vmrglw", ALTIVEC_BUILTIN_VMRGLW }, | |
f18c054f DB |
4974 | { MASK_ALTIVEC, CODE_FOR_uminv16qi3, "__builtin_altivec_vminub", ALTIVEC_BUILTIN_VMINUB }, |
4975 | { MASK_ALTIVEC, CODE_FOR_sminv16qi3, "__builtin_altivec_vminsb", ALTIVEC_BUILTIN_VMINSB }, | |
4976 | { MASK_ALTIVEC, CODE_FOR_uminv8hi3, "__builtin_altivec_vminuh", ALTIVEC_BUILTIN_VMINUH }, | |
4977 | { MASK_ALTIVEC, CODE_FOR_sminv8hi3, "__builtin_altivec_vminsh", ALTIVEC_BUILTIN_VMINSH }, | |
4978 | { MASK_ALTIVEC, CODE_FOR_uminv4si3, "__builtin_altivec_vminuw", ALTIVEC_BUILTIN_VMINUW }, | |
4979 | { MASK_ALTIVEC, CODE_FOR_sminv4si3, "__builtin_altivec_vminsw", ALTIVEC_BUILTIN_VMINSW }, | |
4980 | { MASK_ALTIVEC, CODE_FOR_sminv4sf3, "__builtin_altivec_vminfp", ALTIVEC_BUILTIN_VMINFP }, | |
0ac081f6 AH |
4981 | { MASK_ALTIVEC, CODE_FOR_altivec_vmuleub, "__builtin_altivec_vmuleub", ALTIVEC_BUILTIN_VMULEUB }, |
4982 | { MASK_ALTIVEC, CODE_FOR_altivec_vmulesb, "__builtin_altivec_vmulesb", ALTIVEC_BUILTIN_VMULESB }, | |
4983 | { MASK_ALTIVEC, CODE_FOR_altivec_vmuleuh, "__builtin_altivec_vmuleuh", ALTIVEC_BUILTIN_VMULEUH }, | |
4984 | { MASK_ALTIVEC, CODE_FOR_altivec_vmulesh, "__builtin_altivec_vmulesh", ALTIVEC_BUILTIN_VMULESH }, | |
4985 | { MASK_ALTIVEC, CODE_FOR_altivec_vmuloub, "__builtin_altivec_vmuloub", ALTIVEC_BUILTIN_VMULOUB }, | |
4986 | { MASK_ALTIVEC, CODE_FOR_altivec_vmulosb, "__builtin_altivec_vmulosb", ALTIVEC_BUILTIN_VMULOSB }, | |
4987 | { MASK_ALTIVEC, CODE_FOR_altivec_vmulouh, "__builtin_altivec_vmulouh", ALTIVEC_BUILTIN_VMULOUH }, | |
4988 | { MASK_ALTIVEC, CODE_FOR_altivec_vmulosh, "__builtin_altivec_vmulosh", ALTIVEC_BUILTIN_VMULOSH }, | |
4989 | { MASK_ALTIVEC, CODE_FOR_altivec_vnor, "__builtin_altivec_vnor", ALTIVEC_BUILTIN_VNOR }, | |
f18c054f | 4990 | { MASK_ALTIVEC, CODE_FOR_iorv4si3, "__builtin_altivec_vor", ALTIVEC_BUILTIN_VOR }, |
0ac081f6 AH |
4991 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhum, "__builtin_altivec_vpkuhum", ALTIVEC_BUILTIN_VPKUHUM }, |
4992 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwum, "__builtin_altivec_vpkuwum", ALTIVEC_BUILTIN_VPKUWUM }, | |
4993 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkpx, "__builtin_altivec_vpkpx", ALTIVEC_BUILTIN_VPKPX }, | |
4994 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhss, "__builtin_altivec_vpkuhss", ALTIVEC_BUILTIN_VPKUHSS }, | |
4995 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkshss, "__builtin_altivec_vpkshss", ALTIVEC_BUILTIN_VPKSHSS }, | |
4996 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwss, "__builtin_altivec_vpkuwss", ALTIVEC_BUILTIN_VPKUWSS }, | |
4997 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkswss, "__builtin_altivec_vpkswss", ALTIVEC_BUILTIN_VPKSWSS }, | |
4998 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhus, "__builtin_altivec_vpkuhus", ALTIVEC_BUILTIN_VPKUHUS }, | |
4999 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkshus, "__builtin_altivec_vpkshus", ALTIVEC_BUILTIN_VPKSHUS }, | |
5000 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwus, "__builtin_altivec_vpkuwus", ALTIVEC_BUILTIN_VPKUWUS }, | |
5001 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkswus, "__builtin_altivec_vpkswus", ALTIVEC_BUILTIN_VPKSWUS }, | |
5002 | { MASK_ALTIVEC, CODE_FOR_altivec_vrlb, "__builtin_altivec_vrlb", ALTIVEC_BUILTIN_VRLB }, | |
5003 | { MASK_ALTIVEC, CODE_FOR_altivec_vrlh, "__builtin_altivec_vrlh", ALTIVEC_BUILTIN_VRLH }, | |
5004 | { MASK_ALTIVEC, CODE_FOR_altivec_vrlw, "__builtin_altivec_vrlw", ALTIVEC_BUILTIN_VRLW }, | |
5005 | { MASK_ALTIVEC, CODE_FOR_altivec_vslb, "__builtin_altivec_vslb", ALTIVEC_BUILTIN_VSLB }, | |
5006 | { MASK_ALTIVEC, CODE_FOR_altivec_vslh, "__builtin_altivec_vslh", ALTIVEC_BUILTIN_VSLH }, | |
5007 | { MASK_ALTIVEC, CODE_FOR_altivec_vslw, "__builtin_altivec_vslw", ALTIVEC_BUILTIN_VSLW }, | |
5008 | { MASK_ALTIVEC, CODE_FOR_altivec_vsl, "__builtin_altivec_vsl", ALTIVEC_BUILTIN_VSL }, | |
5009 | { MASK_ALTIVEC, CODE_FOR_altivec_vslo, "__builtin_altivec_vslo", ALTIVEC_BUILTIN_VSLO }, | |
2212663f DB |
5010 | { MASK_ALTIVEC, CODE_FOR_altivec_vspltb, "__builtin_altivec_vspltb", ALTIVEC_BUILTIN_VSPLTB }, |
5011 | { MASK_ALTIVEC, CODE_FOR_altivec_vsplth, "__builtin_altivec_vsplth", ALTIVEC_BUILTIN_VSPLTH }, | |
5012 | { MASK_ALTIVEC, CODE_FOR_altivec_vspltw, "__builtin_altivec_vspltw", ALTIVEC_BUILTIN_VSPLTW }, | |
0ac081f6 | 5013 | { MASK_ALTIVEC, CODE_FOR_altivec_vsrb, "__builtin_altivec_vsrb", ALTIVEC_BUILTIN_VSRB }, |
f18c054f DB |
5014 | { MASK_ALTIVEC, CODE_FOR_altivec_vsrh, "__builtin_altivec_vsrh", ALTIVEC_BUILTIN_VSRH }, |
5015 | { MASK_ALTIVEC, CODE_FOR_altivec_vsrw, "__builtin_altivec_vsrw", ALTIVEC_BUILTIN_VSRW }, | |
0ac081f6 AH |
5016 | { MASK_ALTIVEC, CODE_FOR_altivec_vsrab, "__builtin_altivec_vsrab", ALTIVEC_BUILTIN_VSRAB }, |
5017 | { MASK_ALTIVEC, CODE_FOR_altivec_vsrah, "__builtin_altivec_vsrah", ALTIVEC_BUILTIN_VSRAH }, | |
5018 | { MASK_ALTIVEC, CODE_FOR_altivec_vsraw, "__builtin_altivec_vsraw", ALTIVEC_BUILTIN_VSRAW }, | |
5019 | { MASK_ALTIVEC, CODE_FOR_altivec_vsr, "__builtin_altivec_vsr", ALTIVEC_BUILTIN_VSR }, | |
5020 | { MASK_ALTIVEC, CODE_FOR_altivec_vsro, "__builtin_altivec_vsro", ALTIVEC_BUILTIN_VSRO }, | |
f18c054f DB |
5021 | { MASK_ALTIVEC, CODE_FOR_subv16qi3, "__builtin_altivec_vsububm", ALTIVEC_BUILTIN_VSUBUBM }, |
5022 | { MASK_ALTIVEC, CODE_FOR_subv8hi3, "__builtin_altivec_vsubuhm", ALTIVEC_BUILTIN_VSUBUHM }, | |
5023 | { MASK_ALTIVEC, CODE_FOR_subv4si3, "__builtin_altivec_vsubuwm", ALTIVEC_BUILTIN_VSUBUWM }, | |
5024 | { MASK_ALTIVEC, CODE_FOR_subv4sf3, "__builtin_altivec_vsubfp", ALTIVEC_BUILTIN_VSUBFP }, | |
0ac081f6 AH |
5025 | { MASK_ALTIVEC, CODE_FOR_altivec_vsubcuw, "__builtin_altivec_vsubcuw", ALTIVEC_BUILTIN_VSUBCUW }, |
5026 | { MASK_ALTIVEC, CODE_FOR_altivec_vsububs, "__builtin_altivec_vsububs", ALTIVEC_BUILTIN_VSUBUBS }, | |
5027 | { MASK_ALTIVEC, CODE_FOR_altivec_vsubsbs, "__builtin_altivec_vsubsbs", ALTIVEC_BUILTIN_VSUBSBS }, | |
5028 | { MASK_ALTIVEC, CODE_FOR_altivec_vsubuhs, "__builtin_altivec_vsubuhs", ALTIVEC_BUILTIN_VSUBUHS }, | |
5029 | { MASK_ALTIVEC, CODE_FOR_altivec_vsubshs, "__builtin_altivec_vsubshs", ALTIVEC_BUILTIN_VSUBSHS }, | |
5030 | { MASK_ALTIVEC, CODE_FOR_altivec_vsubuws, "__builtin_altivec_vsubuws", ALTIVEC_BUILTIN_VSUBUWS }, | |
5031 | { MASK_ALTIVEC, CODE_FOR_altivec_vsubsws, "__builtin_altivec_vsubsws", ALTIVEC_BUILTIN_VSUBSWS }, | |
5032 | { MASK_ALTIVEC, CODE_FOR_altivec_vsum4ubs, "__builtin_altivec_vsum4ubs", ALTIVEC_BUILTIN_VSUM4UBS }, | |
5033 | { MASK_ALTIVEC, CODE_FOR_altivec_vsum4sbs, "__builtin_altivec_vsum4sbs", ALTIVEC_BUILTIN_VSUM4SBS }, | |
5034 | { MASK_ALTIVEC, CODE_FOR_altivec_vsum4shs, "__builtin_altivec_vsum4shs", ALTIVEC_BUILTIN_VSUM4SHS }, | |
5035 | { MASK_ALTIVEC, CODE_FOR_altivec_vsum2sws, "__builtin_altivec_vsum2sws", ALTIVEC_BUILTIN_VSUM2SWS }, | |
5036 | { MASK_ALTIVEC, CODE_FOR_altivec_vsumsws, "__builtin_altivec_vsumsws", ALTIVEC_BUILTIN_VSUMSWS }, | |
f18c054f | 5037 | { MASK_ALTIVEC, CODE_FOR_xorv4si3, "__builtin_altivec_vxor", ALTIVEC_BUILTIN_VXOR }, |
a3170dc6 AH |
5038 | |
5039 | /* Place holder, leave as first spe builtin. */ | |
5040 | { 0, CODE_FOR_spe_evaddw, "__builtin_spe_evaddw", SPE_BUILTIN_EVADDW }, | |
5041 | { 0, CODE_FOR_spe_evand, "__builtin_spe_evand", SPE_BUILTIN_EVAND }, | |
5042 | { 0, CODE_FOR_spe_evandc, "__builtin_spe_evandc", SPE_BUILTIN_EVANDC }, | |
5043 | { 0, CODE_FOR_spe_evdivws, "__builtin_spe_evdivws", SPE_BUILTIN_EVDIVWS }, | |
5044 | { 0, CODE_FOR_spe_evdivwu, "__builtin_spe_evdivwu", SPE_BUILTIN_EVDIVWU }, | |
5045 | { 0, CODE_FOR_spe_eveqv, "__builtin_spe_eveqv", SPE_BUILTIN_EVEQV }, | |
5046 | { 0, CODE_FOR_spe_evfsadd, "__builtin_spe_evfsadd", SPE_BUILTIN_EVFSADD }, | |
5047 | { 0, CODE_FOR_spe_evfsdiv, "__builtin_spe_evfsdiv", SPE_BUILTIN_EVFSDIV }, | |
5048 | { 0, CODE_FOR_spe_evfsmul, "__builtin_spe_evfsmul", SPE_BUILTIN_EVFSMUL }, | |
5049 | { 0, CODE_FOR_spe_evfssub, "__builtin_spe_evfssub", SPE_BUILTIN_EVFSSUB }, | |
5050 | { 0, CODE_FOR_spe_evmergehi, "__builtin_spe_evmergehi", SPE_BUILTIN_EVMERGEHI }, | |
5051 | { 0, CODE_FOR_spe_evmergehilo, "__builtin_spe_evmergehilo", SPE_BUILTIN_EVMERGEHILO }, | |
5052 | { 0, CODE_FOR_spe_evmergelo, "__builtin_spe_evmergelo", SPE_BUILTIN_EVMERGELO }, | |
5053 | { 0, CODE_FOR_spe_evmergelohi, "__builtin_spe_evmergelohi", SPE_BUILTIN_EVMERGELOHI }, | |
5054 | { 0, CODE_FOR_spe_evmhegsmfaa, "__builtin_spe_evmhegsmfaa", SPE_BUILTIN_EVMHEGSMFAA }, | |
5055 | { 0, CODE_FOR_spe_evmhegsmfan, "__builtin_spe_evmhegsmfan", SPE_BUILTIN_EVMHEGSMFAN }, | |
5056 | { 0, CODE_FOR_spe_evmhegsmiaa, "__builtin_spe_evmhegsmiaa", SPE_BUILTIN_EVMHEGSMIAA }, | |
5057 | { 0, CODE_FOR_spe_evmhegsmian, "__builtin_spe_evmhegsmian", SPE_BUILTIN_EVMHEGSMIAN }, | |
5058 | { 0, CODE_FOR_spe_evmhegumiaa, "__builtin_spe_evmhegumiaa", SPE_BUILTIN_EVMHEGUMIAA }, | |
5059 | { 0, CODE_FOR_spe_evmhegumian, "__builtin_spe_evmhegumian", SPE_BUILTIN_EVMHEGUMIAN }, | |
5060 | { 0, CODE_FOR_spe_evmhesmf, "__builtin_spe_evmhesmf", SPE_BUILTIN_EVMHESMF }, | |
5061 | { 0, CODE_FOR_spe_evmhesmfa, "__builtin_spe_evmhesmfa", SPE_BUILTIN_EVMHESMFA }, | |
5062 | { 0, CODE_FOR_spe_evmhesmfaaw, "__builtin_spe_evmhesmfaaw", SPE_BUILTIN_EVMHESMFAAW }, | |
5063 | { 0, CODE_FOR_spe_evmhesmfanw, "__builtin_spe_evmhesmfanw", SPE_BUILTIN_EVMHESMFANW }, | |
5064 | { 0, CODE_FOR_spe_evmhesmi, "__builtin_spe_evmhesmi", SPE_BUILTIN_EVMHESMI }, | |
5065 | { 0, CODE_FOR_spe_evmhesmia, "__builtin_spe_evmhesmia", SPE_BUILTIN_EVMHESMIA }, | |
5066 | { 0, CODE_FOR_spe_evmhesmiaaw, "__builtin_spe_evmhesmiaaw", SPE_BUILTIN_EVMHESMIAAW }, | |
5067 | { 0, CODE_FOR_spe_evmhesmianw, "__builtin_spe_evmhesmianw", SPE_BUILTIN_EVMHESMIANW }, | |
5068 | { 0, CODE_FOR_spe_evmhessf, "__builtin_spe_evmhessf", SPE_BUILTIN_EVMHESSF }, | |
5069 | { 0, CODE_FOR_spe_evmhessfa, "__builtin_spe_evmhessfa", SPE_BUILTIN_EVMHESSFA }, | |
5070 | { 0, CODE_FOR_spe_evmhessfaaw, "__builtin_spe_evmhessfaaw", SPE_BUILTIN_EVMHESSFAAW }, | |
5071 | { 0, CODE_FOR_spe_evmhessfanw, "__builtin_spe_evmhessfanw", SPE_BUILTIN_EVMHESSFANW }, | |
5072 | { 0, CODE_FOR_spe_evmhessiaaw, "__builtin_spe_evmhessiaaw", SPE_BUILTIN_EVMHESSIAAW }, | |
5073 | { 0, CODE_FOR_spe_evmhessianw, "__builtin_spe_evmhessianw", SPE_BUILTIN_EVMHESSIANW }, | |
5074 | { 0, CODE_FOR_spe_evmheumi, "__builtin_spe_evmheumi", SPE_BUILTIN_EVMHEUMI }, | |
5075 | { 0, CODE_FOR_spe_evmheumia, "__builtin_spe_evmheumia", SPE_BUILTIN_EVMHEUMIA }, | |
5076 | { 0, CODE_FOR_spe_evmheumiaaw, "__builtin_spe_evmheumiaaw", SPE_BUILTIN_EVMHEUMIAAW }, | |
5077 | { 0, CODE_FOR_spe_evmheumianw, "__builtin_spe_evmheumianw", SPE_BUILTIN_EVMHEUMIANW }, | |
5078 | { 0, CODE_FOR_spe_evmheusiaaw, "__builtin_spe_evmheusiaaw", SPE_BUILTIN_EVMHEUSIAAW }, | |
5079 | { 0, CODE_FOR_spe_evmheusianw, "__builtin_spe_evmheusianw", SPE_BUILTIN_EVMHEUSIANW }, | |
5080 | { 0, CODE_FOR_spe_evmhogsmfaa, "__builtin_spe_evmhogsmfaa", SPE_BUILTIN_EVMHOGSMFAA }, | |
5081 | { 0, CODE_FOR_spe_evmhogsmfan, "__builtin_spe_evmhogsmfan", SPE_BUILTIN_EVMHOGSMFAN }, | |
5082 | { 0, CODE_FOR_spe_evmhogsmiaa, "__builtin_spe_evmhogsmiaa", SPE_BUILTIN_EVMHOGSMIAA }, | |
5083 | { 0, CODE_FOR_spe_evmhogsmian, "__builtin_spe_evmhogsmian", SPE_BUILTIN_EVMHOGSMIAN }, | |
5084 | { 0, CODE_FOR_spe_evmhogumiaa, "__builtin_spe_evmhogumiaa", SPE_BUILTIN_EVMHOGUMIAA }, | |
5085 | { 0, CODE_FOR_spe_evmhogumian, "__builtin_spe_evmhogumian", SPE_BUILTIN_EVMHOGUMIAN }, | |
5086 | { 0, CODE_FOR_spe_evmhosmf, "__builtin_spe_evmhosmf", SPE_BUILTIN_EVMHOSMF }, | |
5087 | { 0, CODE_FOR_spe_evmhosmfa, "__builtin_spe_evmhosmfa", SPE_BUILTIN_EVMHOSMFA }, | |
5088 | { 0, CODE_FOR_spe_evmhosmfaaw, "__builtin_spe_evmhosmfaaw", SPE_BUILTIN_EVMHOSMFAAW }, | |
5089 | { 0, CODE_FOR_spe_evmhosmfanw, "__builtin_spe_evmhosmfanw", SPE_BUILTIN_EVMHOSMFANW }, | |
5090 | { 0, CODE_FOR_spe_evmhosmi, "__builtin_spe_evmhosmi", SPE_BUILTIN_EVMHOSMI }, | |
5091 | { 0, CODE_FOR_spe_evmhosmia, "__builtin_spe_evmhosmia", SPE_BUILTIN_EVMHOSMIA }, | |
5092 | { 0, CODE_FOR_spe_evmhosmiaaw, "__builtin_spe_evmhosmiaaw", SPE_BUILTIN_EVMHOSMIAAW }, | |
5093 | { 0, CODE_FOR_spe_evmhosmianw, "__builtin_spe_evmhosmianw", SPE_BUILTIN_EVMHOSMIANW }, | |
5094 | { 0, CODE_FOR_spe_evmhossf, "__builtin_spe_evmhossf", SPE_BUILTIN_EVMHOSSF }, | |
5095 | { 0, CODE_FOR_spe_evmhossfa, "__builtin_spe_evmhossfa", SPE_BUILTIN_EVMHOSSFA }, | |
5096 | { 0, CODE_FOR_spe_evmhossfaaw, "__builtin_spe_evmhossfaaw", SPE_BUILTIN_EVMHOSSFAAW }, | |
5097 | { 0, CODE_FOR_spe_evmhossfanw, "__builtin_spe_evmhossfanw", SPE_BUILTIN_EVMHOSSFANW }, | |
5098 | { 0, CODE_FOR_spe_evmhossiaaw, "__builtin_spe_evmhossiaaw", SPE_BUILTIN_EVMHOSSIAAW }, | |
5099 | { 0, CODE_FOR_spe_evmhossianw, "__builtin_spe_evmhossianw", SPE_BUILTIN_EVMHOSSIANW }, | |
5100 | { 0, CODE_FOR_spe_evmhoumi, "__builtin_spe_evmhoumi", SPE_BUILTIN_EVMHOUMI }, | |
5101 | { 0, CODE_FOR_spe_evmhoumia, "__builtin_spe_evmhoumia", SPE_BUILTIN_EVMHOUMIA }, | |
5102 | { 0, CODE_FOR_spe_evmhoumiaaw, "__builtin_spe_evmhoumiaaw", SPE_BUILTIN_EVMHOUMIAAW }, | |
5103 | { 0, CODE_FOR_spe_evmhoumianw, "__builtin_spe_evmhoumianw", SPE_BUILTIN_EVMHOUMIANW }, | |
5104 | { 0, CODE_FOR_spe_evmhousiaaw, "__builtin_spe_evmhousiaaw", SPE_BUILTIN_EVMHOUSIAAW }, | |
5105 | { 0, CODE_FOR_spe_evmhousianw, "__builtin_spe_evmhousianw", SPE_BUILTIN_EVMHOUSIANW }, | |
5106 | { 0, CODE_FOR_spe_evmwhsmf, "__builtin_spe_evmwhsmf", SPE_BUILTIN_EVMWHSMF }, | |
5107 | { 0, CODE_FOR_spe_evmwhsmfa, "__builtin_spe_evmwhsmfa", SPE_BUILTIN_EVMWHSMFA }, | |
5108 | { 0, CODE_FOR_spe_evmwhsmi, "__builtin_spe_evmwhsmi", SPE_BUILTIN_EVMWHSMI }, | |
5109 | { 0, CODE_FOR_spe_evmwhsmia, "__builtin_spe_evmwhsmia", SPE_BUILTIN_EVMWHSMIA }, | |
5110 | { 0, CODE_FOR_spe_evmwhssf, "__builtin_spe_evmwhssf", SPE_BUILTIN_EVMWHSSF }, | |
5111 | { 0, CODE_FOR_spe_evmwhssfa, "__builtin_spe_evmwhssfa", SPE_BUILTIN_EVMWHSSFA }, | |
5112 | { 0, CODE_FOR_spe_evmwhumi, "__builtin_spe_evmwhumi", SPE_BUILTIN_EVMWHUMI }, | |
5113 | { 0, CODE_FOR_spe_evmwhumia, "__builtin_spe_evmwhumia", SPE_BUILTIN_EVMWHUMIA }, | |
a3170dc6 AH |
5114 | { 0, CODE_FOR_spe_evmwlsmiaaw, "__builtin_spe_evmwlsmiaaw", SPE_BUILTIN_EVMWLSMIAAW }, |
5115 | { 0, CODE_FOR_spe_evmwlsmianw, "__builtin_spe_evmwlsmianw", SPE_BUILTIN_EVMWLSMIANW }, | |
a3170dc6 AH |
5116 | { 0, CODE_FOR_spe_evmwlssiaaw, "__builtin_spe_evmwlssiaaw", SPE_BUILTIN_EVMWLSSIAAW }, |
5117 | { 0, CODE_FOR_spe_evmwlssianw, "__builtin_spe_evmwlssianw", SPE_BUILTIN_EVMWLSSIANW }, | |
5118 | { 0, CODE_FOR_spe_evmwlumi, "__builtin_spe_evmwlumi", SPE_BUILTIN_EVMWLUMI }, | |
5119 | { 0, CODE_FOR_spe_evmwlumia, "__builtin_spe_evmwlumia", SPE_BUILTIN_EVMWLUMIA }, | |
5120 | { 0, CODE_FOR_spe_evmwlumiaaw, "__builtin_spe_evmwlumiaaw", SPE_BUILTIN_EVMWLUMIAAW }, | |
5121 | { 0, CODE_FOR_spe_evmwlumianw, "__builtin_spe_evmwlumianw", SPE_BUILTIN_EVMWLUMIANW }, | |
5122 | { 0, CODE_FOR_spe_evmwlusiaaw, "__builtin_spe_evmwlusiaaw", SPE_BUILTIN_EVMWLUSIAAW }, | |
5123 | { 0, CODE_FOR_spe_evmwlusianw, "__builtin_spe_evmwlusianw", SPE_BUILTIN_EVMWLUSIANW }, | |
5124 | { 0, CODE_FOR_spe_evmwsmf, "__builtin_spe_evmwsmf", SPE_BUILTIN_EVMWSMF }, | |
5125 | { 0, CODE_FOR_spe_evmwsmfa, "__builtin_spe_evmwsmfa", SPE_BUILTIN_EVMWSMFA }, | |
5126 | { 0, CODE_FOR_spe_evmwsmfaa, "__builtin_spe_evmwsmfaa", SPE_BUILTIN_EVMWSMFAA }, | |
5127 | { 0, CODE_FOR_spe_evmwsmfan, "__builtin_spe_evmwsmfan", SPE_BUILTIN_EVMWSMFAN }, | |
5128 | { 0, CODE_FOR_spe_evmwsmi, "__builtin_spe_evmwsmi", SPE_BUILTIN_EVMWSMI }, | |
5129 | { 0, CODE_FOR_spe_evmwsmia, "__builtin_spe_evmwsmia", SPE_BUILTIN_EVMWSMIA }, | |
5130 | { 0, CODE_FOR_spe_evmwsmiaa, "__builtin_spe_evmwsmiaa", SPE_BUILTIN_EVMWSMIAA }, | |
5131 | { 0, CODE_FOR_spe_evmwsmian, "__builtin_spe_evmwsmian", SPE_BUILTIN_EVMWSMIAN }, | |
5132 | { 0, CODE_FOR_spe_evmwssf, "__builtin_spe_evmwssf", SPE_BUILTIN_EVMWSSF }, | |
5133 | { 0, CODE_FOR_spe_evmwssfa, "__builtin_spe_evmwssfa", SPE_BUILTIN_EVMWSSFA }, | |
5134 | { 0, CODE_FOR_spe_evmwssfaa, "__builtin_spe_evmwssfaa", SPE_BUILTIN_EVMWSSFAA }, | |
5135 | { 0, CODE_FOR_spe_evmwssfan, "__builtin_spe_evmwssfan", SPE_BUILTIN_EVMWSSFAN }, | |
5136 | { 0, CODE_FOR_spe_evmwumi, "__builtin_spe_evmwumi", SPE_BUILTIN_EVMWUMI }, | |
5137 | { 0, CODE_FOR_spe_evmwumia, "__builtin_spe_evmwumia", SPE_BUILTIN_EVMWUMIA }, | |
5138 | { 0, CODE_FOR_spe_evmwumiaa, "__builtin_spe_evmwumiaa", SPE_BUILTIN_EVMWUMIAA }, | |
5139 | { 0, CODE_FOR_spe_evmwumian, "__builtin_spe_evmwumian", SPE_BUILTIN_EVMWUMIAN }, | |
5140 | { 0, CODE_FOR_spe_evnand, "__builtin_spe_evnand", SPE_BUILTIN_EVNAND }, | |
5141 | { 0, CODE_FOR_spe_evnor, "__builtin_spe_evnor", SPE_BUILTIN_EVNOR }, | |
5142 | { 0, CODE_FOR_spe_evor, "__builtin_spe_evor", SPE_BUILTIN_EVOR }, | |
5143 | { 0, CODE_FOR_spe_evorc, "__builtin_spe_evorc", SPE_BUILTIN_EVORC }, | |
5144 | { 0, CODE_FOR_spe_evrlw, "__builtin_spe_evrlw", SPE_BUILTIN_EVRLW }, | |
5145 | { 0, CODE_FOR_spe_evslw, "__builtin_spe_evslw", SPE_BUILTIN_EVSLW }, | |
5146 | { 0, CODE_FOR_spe_evsrws, "__builtin_spe_evsrws", SPE_BUILTIN_EVSRWS }, | |
5147 | { 0, CODE_FOR_spe_evsrwu, "__builtin_spe_evsrwu", SPE_BUILTIN_EVSRWU }, | |
5148 | { 0, CODE_FOR_spe_evsubfw, "__builtin_spe_evsubfw", SPE_BUILTIN_EVSUBFW }, | |
5149 | ||
5150 | /* SPE binary operations expecting a 5-bit unsigned literal. */ | |
5151 | { 0, CODE_FOR_spe_evaddiw, "__builtin_spe_evaddiw", SPE_BUILTIN_EVADDIW }, | |
5152 | ||
5153 | { 0, CODE_FOR_spe_evrlwi, "__builtin_spe_evrlwi", SPE_BUILTIN_EVRLWI }, | |
5154 | { 0, CODE_FOR_spe_evslwi, "__builtin_spe_evslwi", SPE_BUILTIN_EVSLWI }, | |
5155 | { 0, CODE_FOR_spe_evsrwis, "__builtin_spe_evsrwis", SPE_BUILTIN_EVSRWIS }, | |
5156 | { 0, CODE_FOR_spe_evsrwiu, "__builtin_spe_evsrwiu", SPE_BUILTIN_EVSRWIU }, | |
5157 | { 0, CODE_FOR_spe_evsubifw, "__builtin_spe_evsubifw", SPE_BUILTIN_EVSUBIFW }, | |
5158 | { 0, CODE_FOR_spe_evmwhssfaa, "__builtin_spe_evmwhssfaa", SPE_BUILTIN_EVMWHSSFAA }, | |
5159 | { 0, CODE_FOR_spe_evmwhssmaa, "__builtin_spe_evmwhssmaa", SPE_BUILTIN_EVMWHSSMAA }, | |
5160 | { 0, CODE_FOR_spe_evmwhsmfaa, "__builtin_spe_evmwhsmfaa", SPE_BUILTIN_EVMWHSMFAA }, | |
5161 | { 0, CODE_FOR_spe_evmwhsmiaa, "__builtin_spe_evmwhsmiaa", SPE_BUILTIN_EVMWHSMIAA }, | |
5162 | { 0, CODE_FOR_spe_evmwhusiaa, "__builtin_spe_evmwhusiaa", SPE_BUILTIN_EVMWHUSIAA }, | |
5163 | { 0, CODE_FOR_spe_evmwhumiaa, "__builtin_spe_evmwhumiaa", SPE_BUILTIN_EVMWHUMIAA }, | |
5164 | { 0, CODE_FOR_spe_evmwhssfan, "__builtin_spe_evmwhssfan", SPE_BUILTIN_EVMWHSSFAN }, | |
5165 | { 0, CODE_FOR_spe_evmwhssian, "__builtin_spe_evmwhssian", SPE_BUILTIN_EVMWHSSIAN }, | |
5166 | { 0, CODE_FOR_spe_evmwhsmfan, "__builtin_spe_evmwhsmfan", SPE_BUILTIN_EVMWHSMFAN }, | |
5167 | { 0, CODE_FOR_spe_evmwhsmian, "__builtin_spe_evmwhsmian", SPE_BUILTIN_EVMWHSMIAN }, | |
5168 | { 0, CODE_FOR_spe_evmwhusian, "__builtin_spe_evmwhusian", SPE_BUILTIN_EVMWHUSIAN }, | |
5169 | { 0, CODE_FOR_spe_evmwhumian, "__builtin_spe_evmwhumian", SPE_BUILTIN_EVMWHUMIAN }, | |
5170 | { 0, CODE_FOR_spe_evmwhgssfaa, "__builtin_spe_evmwhgssfaa", SPE_BUILTIN_EVMWHGSSFAA }, | |
5171 | { 0, CODE_FOR_spe_evmwhgsmfaa, "__builtin_spe_evmwhgsmfaa", SPE_BUILTIN_EVMWHGSMFAA }, | |
5172 | { 0, CODE_FOR_spe_evmwhgsmiaa, "__builtin_spe_evmwhgsmiaa", SPE_BUILTIN_EVMWHGSMIAA }, | |
5173 | { 0, CODE_FOR_spe_evmwhgumiaa, "__builtin_spe_evmwhgumiaa", SPE_BUILTIN_EVMWHGUMIAA }, | |
5174 | { 0, CODE_FOR_spe_evmwhgssfan, "__builtin_spe_evmwhgssfan", SPE_BUILTIN_EVMWHGSSFAN }, | |
5175 | { 0, CODE_FOR_spe_evmwhgsmfan, "__builtin_spe_evmwhgsmfan", SPE_BUILTIN_EVMWHGSMFAN }, | |
5176 | { 0, CODE_FOR_spe_evmwhgsmian, "__builtin_spe_evmwhgsmian", SPE_BUILTIN_EVMWHGSMIAN }, | |
5177 | { 0, CODE_FOR_spe_evmwhgumian, "__builtin_spe_evmwhgumian", SPE_BUILTIN_EVMWHGUMIAN }, | |
5178 | { 0, CODE_FOR_spe_brinc, "__builtin_spe_brinc", SPE_BUILTIN_BRINC }, | |
5179 | ||
5180 | /* Place-holder. Leave as last binary SPE builtin. */ | |
17edbda5 | 5181 | { 0, CODE_FOR_xorv2si3, "__builtin_spe_evxor", SPE_BUILTIN_EVXOR }, |
ae4b4a02 AH |
5182 | }; |
5183 | ||
5184 | /* AltiVec predicates. */ | |
5185 | ||
5186 | struct builtin_description_predicates | |
5187 | { | |
5188 | const unsigned int mask; | |
5189 | const enum insn_code icode; | |
5190 | const char *opcode; | |
5191 | const char *const name; | |
5192 | const enum rs6000_builtins code; | |
5193 | }; | |
5194 | ||
5195 | static const struct builtin_description_predicates bdesc_altivec_preds[] = | |
5196 | { | |
5197 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpbfp.", "__builtin_altivec_vcmpbfp_p", ALTIVEC_BUILTIN_VCMPBFP_P }, | |
5198 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpeqfp.", "__builtin_altivec_vcmpeqfp_p", ALTIVEC_BUILTIN_VCMPEQFP_P }, | |
5199 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpgefp.", "__builtin_altivec_vcmpgefp_p", ALTIVEC_BUILTIN_VCMPGEFP_P }, | |
5200 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpgtfp.", "__builtin_altivec_vcmpgtfp_p", ALTIVEC_BUILTIN_VCMPGTFP_P }, | |
5201 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpequw.", "__builtin_altivec_vcmpequw_p", ALTIVEC_BUILTIN_VCMPEQUW_P }, | |
5202 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpgtsw.", "__builtin_altivec_vcmpgtsw_p", ALTIVEC_BUILTIN_VCMPGTSW_P }, | |
5203 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpgtuw.", "__builtin_altivec_vcmpgtuw_p", ALTIVEC_BUILTIN_VCMPGTUW_P }, | |
5204 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpgtuh.", "__builtin_altivec_vcmpgtuh_p", ALTIVEC_BUILTIN_VCMPGTUH_P }, | |
5205 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpgtsh.", "__builtin_altivec_vcmpgtsh_p", ALTIVEC_BUILTIN_VCMPGTSH_P }, | |
5206 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpequh.", "__builtin_altivec_vcmpequh_p", ALTIVEC_BUILTIN_VCMPEQUH_P }, | |
5207 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpequb.", "__builtin_altivec_vcmpequb_p", ALTIVEC_BUILTIN_VCMPEQUB_P }, | |
5208 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpgtsb.", "__builtin_altivec_vcmpgtsb_p", ALTIVEC_BUILTIN_VCMPGTSB_P }, | |
5209 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpgtub.", "__builtin_altivec_vcmpgtub_p", ALTIVEC_BUILTIN_VCMPGTUB_P } | |
0ac081f6 | 5210 | }; |
24408032 | 5211 | |
a3170dc6 AH |
5212 | /* SPE predicates. */ |
5213 | static struct builtin_description bdesc_spe_predicates[] = | |
5214 | { | |
5215 | /* Place-holder. Leave as first. */ | |
5216 | { 0, CODE_FOR_spe_evcmpeq, "__builtin_spe_evcmpeq", SPE_BUILTIN_EVCMPEQ }, | |
5217 | { 0, CODE_FOR_spe_evcmpgts, "__builtin_spe_evcmpgts", SPE_BUILTIN_EVCMPGTS }, | |
5218 | { 0, CODE_FOR_spe_evcmpgtu, "__builtin_spe_evcmpgtu", SPE_BUILTIN_EVCMPGTU }, | |
5219 | { 0, CODE_FOR_spe_evcmplts, "__builtin_spe_evcmplts", SPE_BUILTIN_EVCMPLTS }, | |
5220 | { 0, CODE_FOR_spe_evcmpltu, "__builtin_spe_evcmpltu", SPE_BUILTIN_EVCMPLTU }, | |
5221 | { 0, CODE_FOR_spe_evfscmpeq, "__builtin_spe_evfscmpeq", SPE_BUILTIN_EVFSCMPEQ }, | |
5222 | { 0, CODE_FOR_spe_evfscmpgt, "__builtin_spe_evfscmpgt", SPE_BUILTIN_EVFSCMPGT }, | |
5223 | { 0, CODE_FOR_spe_evfscmplt, "__builtin_spe_evfscmplt", SPE_BUILTIN_EVFSCMPLT }, | |
5224 | { 0, CODE_FOR_spe_evfststeq, "__builtin_spe_evfststeq", SPE_BUILTIN_EVFSTSTEQ }, | |
5225 | { 0, CODE_FOR_spe_evfststgt, "__builtin_spe_evfststgt", SPE_BUILTIN_EVFSTSTGT }, | |
5226 | /* Place-holder. Leave as last. */ | |
5227 | { 0, CODE_FOR_spe_evfststlt, "__builtin_spe_evfststlt", SPE_BUILTIN_EVFSTSTLT }, | |
5228 | }; | |
5229 | ||
5230 | /* SPE evsel predicates. */ | |
5231 | static struct builtin_description bdesc_spe_evsel[] = | |
5232 | { | |
5233 | /* Place-holder. Leave as first. */ | |
5234 | { 0, CODE_FOR_spe_evcmpgts, "__builtin_spe_evsel_gts", SPE_BUILTIN_EVSEL_CMPGTS }, | |
5235 | { 0, CODE_FOR_spe_evcmpgtu, "__builtin_spe_evsel_gtu", SPE_BUILTIN_EVSEL_CMPGTU }, | |
5236 | { 0, CODE_FOR_spe_evcmplts, "__builtin_spe_evsel_lts", SPE_BUILTIN_EVSEL_CMPLTS }, | |
5237 | { 0, CODE_FOR_spe_evcmpltu, "__builtin_spe_evsel_ltu", SPE_BUILTIN_EVSEL_CMPLTU }, | |
5238 | { 0, CODE_FOR_spe_evcmpeq, "__builtin_spe_evsel_eq", SPE_BUILTIN_EVSEL_CMPEQ }, | |
5239 | { 0, CODE_FOR_spe_evfscmpgt, "__builtin_spe_evsel_fsgt", SPE_BUILTIN_EVSEL_FSCMPGT }, | |
5240 | { 0, CODE_FOR_spe_evfscmplt, "__builtin_spe_evsel_fslt", SPE_BUILTIN_EVSEL_FSCMPLT }, | |
5241 | { 0, CODE_FOR_spe_evfscmpeq, "__builtin_spe_evsel_fseq", SPE_BUILTIN_EVSEL_FSCMPEQ }, | |
5242 | { 0, CODE_FOR_spe_evfststgt, "__builtin_spe_evsel_fststgt", SPE_BUILTIN_EVSEL_FSTSTGT }, | |
5243 | { 0, CODE_FOR_spe_evfststlt, "__builtin_spe_evsel_fststlt", SPE_BUILTIN_EVSEL_FSTSTLT }, | |
5244 | /* Place-holder. Leave as last. */ | |
5245 | { 0, CODE_FOR_spe_evfststeq, "__builtin_spe_evsel_fststeq", SPE_BUILTIN_EVSEL_FSTSTEQ }, | |
5246 | }; | |
5247 | ||
b6d08ca1 | 5248 | /* ABS* operations. */ |
100c4561 AH |
5249 | |
5250 | static const struct builtin_description bdesc_abs[] = | |
5251 | { | |
5252 | { MASK_ALTIVEC, CODE_FOR_absv4si2, "__builtin_altivec_abs_v4si", ALTIVEC_BUILTIN_ABS_V4SI }, | |
5253 | { MASK_ALTIVEC, CODE_FOR_absv8hi2, "__builtin_altivec_abs_v8hi", ALTIVEC_BUILTIN_ABS_V8HI }, | |
5254 | { MASK_ALTIVEC, CODE_FOR_absv4sf2, "__builtin_altivec_abs_v4sf", ALTIVEC_BUILTIN_ABS_V4SF }, | |
5255 | { MASK_ALTIVEC, CODE_FOR_absv16qi2, "__builtin_altivec_abs_v16qi", ALTIVEC_BUILTIN_ABS_V16QI }, | |
5256 | { MASK_ALTIVEC, CODE_FOR_altivec_abss_v4si, "__builtin_altivec_abss_v4si", ALTIVEC_BUILTIN_ABSS_V4SI }, | |
5257 | { MASK_ALTIVEC, CODE_FOR_altivec_abss_v8hi, "__builtin_altivec_abss_v8hi", ALTIVEC_BUILTIN_ABSS_V8HI }, | |
5258 | { MASK_ALTIVEC, CODE_FOR_altivec_abss_v16qi, "__builtin_altivec_abss_v16qi", ALTIVEC_BUILTIN_ABSS_V16QI } | |
5259 | }; | |
5260 | ||
617e0e1d DB |
5261 | /* Simple unary operations: VECb = foo (unsigned literal) or VECb = |
5262 | foo (VECa). */ | |
24408032 | 5263 | |
a3170dc6 | 5264 | static struct builtin_description bdesc_1arg[] = |
2212663f | 5265 | { |
617e0e1d DB |
5266 | { MASK_ALTIVEC, CODE_FOR_altivec_vexptefp, "__builtin_altivec_vexptefp", ALTIVEC_BUILTIN_VEXPTEFP }, |
5267 | { MASK_ALTIVEC, CODE_FOR_altivec_vlogefp, "__builtin_altivec_vlogefp", ALTIVEC_BUILTIN_VLOGEFP }, | |
5268 | { MASK_ALTIVEC, CODE_FOR_altivec_vrefp, "__builtin_altivec_vrefp", ALTIVEC_BUILTIN_VREFP }, | |
5269 | { MASK_ALTIVEC, CODE_FOR_altivec_vrfim, "__builtin_altivec_vrfim", ALTIVEC_BUILTIN_VRFIM }, | |
5270 | { MASK_ALTIVEC, CODE_FOR_altivec_vrfin, "__builtin_altivec_vrfin", ALTIVEC_BUILTIN_VRFIN }, | |
5271 | { MASK_ALTIVEC, CODE_FOR_altivec_vrfip, "__builtin_altivec_vrfip", ALTIVEC_BUILTIN_VRFIP }, | |
5272 | { MASK_ALTIVEC, CODE_FOR_ftruncv4sf2, "__builtin_altivec_vrfiz", ALTIVEC_BUILTIN_VRFIZ }, | |
5273 | { MASK_ALTIVEC, CODE_FOR_altivec_vrsqrtefp, "__builtin_altivec_vrsqrtefp", ALTIVEC_BUILTIN_VRSQRTEFP }, | |
2212663f DB |
5274 | { MASK_ALTIVEC, CODE_FOR_altivec_vspltisb, "__builtin_altivec_vspltisb", ALTIVEC_BUILTIN_VSPLTISB }, |
5275 | { MASK_ALTIVEC, CODE_FOR_altivec_vspltish, "__builtin_altivec_vspltish", ALTIVEC_BUILTIN_VSPLTISH }, | |
5276 | { MASK_ALTIVEC, CODE_FOR_altivec_vspltisw, "__builtin_altivec_vspltisw", ALTIVEC_BUILTIN_VSPLTISW }, | |
20e26713 AH |
5277 | { MASK_ALTIVEC, CODE_FOR_altivec_vupkhsb, "__builtin_altivec_vupkhsb", ALTIVEC_BUILTIN_VUPKHSB }, |
5278 | { MASK_ALTIVEC, CODE_FOR_altivec_vupkhpx, "__builtin_altivec_vupkhpx", ALTIVEC_BUILTIN_VUPKHPX }, | |
5279 | { MASK_ALTIVEC, CODE_FOR_altivec_vupkhsh, "__builtin_altivec_vupkhsh", ALTIVEC_BUILTIN_VUPKHSH }, | |
5280 | { MASK_ALTIVEC, CODE_FOR_altivec_vupklsb, "__builtin_altivec_vupklsb", ALTIVEC_BUILTIN_VUPKLSB }, | |
5281 | { MASK_ALTIVEC, CODE_FOR_altivec_vupklpx, "__builtin_altivec_vupklpx", ALTIVEC_BUILTIN_VUPKLPX }, | |
5282 | { MASK_ALTIVEC, CODE_FOR_altivec_vupklsh, "__builtin_altivec_vupklsh", ALTIVEC_BUILTIN_VUPKLSH }, | |
a3170dc6 AH |
5283 | |
5284 | /* The SPE unary builtins must start with SPE_BUILTIN_EVABS and | |
5285 | end with SPE_BUILTIN_EVSUBFUSIAAW. */ | |
5286 | { 0, CODE_FOR_spe_evabs, "__builtin_spe_evabs", SPE_BUILTIN_EVABS }, | |
5287 | { 0, CODE_FOR_spe_evaddsmiaaw, "__builtin_spe_evaddsmiaaw", SPE_BUILTIN_EVADDSMIAAW }, | |
5288 | { 0, CODE_FOR_spe_evaddssiaaw, "__builtin_spe_evaddssiaaw", SPE_BUILTIN_EVADDSSIAAW }, | |
5289 | { 0, CODE_FOR_spe_evaddumiaaw, "__builtin_spe_evaddumiaaw", SPE_BUILTIN_EVADDUMIAAW }, | |
5290 | { 0, CODE_FOR_spe_evaddusiaaw, "__builtin_spe_evaddusiaaw", SPE_BUILTIN_EVADDUSIAAW }, | |
5291 | { 0, CODE_FOR_spe_evcntlsw, "__builtin_spe_evcntlsw", SPE_BUILTIN_EVCNTLSW }, | |
5292 | { 0, CODE_FOR_spe_evcntlzw, "__builtin_spe_evcntlzw", SPE_BUILTIN_EVCNTLZW }, | |
5293 | { 0, CODE_FOR_spe_evextsb, "__builtin_spe_evextsb", SPE_BUILTIN_EVEXTSB }, | |
5294 | { 0, CODE_FOR_spe_evextsh, "__builtin_spe_evextsh", SPE_BUILTIN_EVEXTSH }, | |
5295 | { 0, CODE_FOR_spe_evfsabs, "__builtin_spe_evfsabs", SPE_BUILTIN_EVFSABS }, | |
5296 | { 0, CODE_FOR_spe_evfscfsf, "__builtin_spe_evfscfsf", SPE_BUILTIN_EVFSCFSF }, | |
5297 | { 0, CODE_FOR_spe_evfscfsi, "__builtin_spe_evfscfsi", SPE_BUILTIN_EVFSCFSI }, | |
5298 | { 0, CODE_FOR_spe_evfscfuf, "__builtin_spe_evfscfuf", SPE_BUILTIN_EVFSCFUF }, | |
5299 | { 0, CODE_FOR_spe_evfscfui, "__builtin_spe_evfscfui", SPE_BUILTIN_EVFSCFUI }, | |
5300 | { 0, CODE_FOR_spe_evfsctsf, "__builtin_spe_evfsctsf", SPE_BUILTIN_EVFSCTSF }, | |
5301 | { 0, CODE_FOR_spe_evfsctsi, "__builtin_spe_evfsctsi", SPE_BUILTIN_EVFSCTSI }, | |
5302 | { 0, CODE_FOR_spe_evfsctsiz, "__builtin_spe_evfsctsiz", SPE_BUILTIN_EVFSCTSIZ }, | |
5303 | { 0, CODE_FOR_spe_evfsctuf, "__builtin_spe_evfsctuf", SPE_BUILTIN_EVFSCTUF }, | |
5304 | { 0, CODE_FOR_spe_evfsctui, "__builtin_spe_evfsctui", SPE_BUILTIN_EVFSCTUI }, | |
5305 | { 0, CODE_FOR_spe_evfsctuiz, "__builtin_spe_evfsctuiz", SPE_BUILTIN_EVFSCTUIZ }, | |
5306 | { 0, CODE_FOR_spe_evfsnabs, "__builtin_spe_evfsnabs", SPE_BUILTIN_EVFSNABS }, | |
5307 | { 0, CODE_FOR_spe_evfsneg, "__builtin_spe_evfsneg", SPE_BUILTIN_EVFSNEG }, | |
5308 | { 0, CODE_FOR_spe_evmra, "__builtin_spe_evmra", SPE_BUILTIN_EVMRA }, | |
5309 | { 0, CODE_FOR_spe_evneg, "__builtin_spe_evneg", SPE_BUILTIN_EVNEG }, | |
5310 | { 0, CODE_FOR_spe_evrndw, "__builtin_spe_evrndw", SPE_BUILTIN_EVRNDW }, | |
5311 | { 0, CODE_FOR_spe_evsubfsmiaaw, "__builtin_spe_evsubfsmiaaw", SPE_BUILTIN_EVSUBFSMIAAW }, | |
5312 | { 0, CODE_FOR_spe_evsubfssiaaw, "__builtin_spe_evsubfssiaaw", SPE_BUILTIN_EVSUBFSSIAAW }, | |
5313 | { 0, CODE_FOR_spe_evsubfumiaaw, "__builtin_spe_evsubfumiaaw", SPE_BUILTIN_EVSUBFUMIAAW }, | |
a3170dc6 AH |
5314 | |
5315 | /* Place-holder. Leave as last unary SPE builtin. */ | |
5316 | { 0, CODE_FOR_spe_evsubfusiaaw, "__builtin_spe_evsubfusiaaw", SPE_BUILTIN_EVSUBFUSIAAW }, | |
2212663f DB |
5317 | }; |
5318 | ||
5319 | static rtx | |
a2369ed3 | 5320 | rs6000_expand_unop_builtin (enum insn_code icode, tree arglist, rtx target) |
2212663f DB |
5321 | { |
5322 | rtx pat; | |
5323 | tree arg0 = TREE_VALUE (arglist); | |
5324 | rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
5325 | enum machine_mode tmode = insn_data[icode].operand[0].mode; | |
5326 | enum machine_mode mode0 = insn_data[icode].operand[1].mode; | |
5327 | ||
0559cc77 DE |
5328 | if (icode == CODE_FOR_nothing) |
5329 | /* Builtin not supported on this processor. */ | |
5330 | return 0; | |
5331 | ||
20e26713 AH |
5332 | /* If we got invalid arguments bail out before generating bad rtl. */ |
5333 | if (arg0 == error_mark_node) | |
9a171fcd | 5334 | return const0_rtx; |
20e26713 | 5335 | |
0559cc77 DE |
5336 | if (icode == CODE_FOR_altivec_vspltisb |
5337 | || icode == CODE_FOR_altivec_vspltish | |
5338 | || icode == CODE_FOR_altivec_vspltisw | |
5339 | || icode == CODE_FOR_spe_evsplatfi | |
5340 | || icode == CODE_FOR_spe_evsplati) | |
b44140e7 AH |
5341 | { |
5342 | /* Only allow 5-bit *signed* literals. */ | |
b44140e7 AH |
5343 | if (GET_CODE (op0) != CONST_INT |
5344 | || INTVAL (op0) > 0x1f | |
5345 | || INTVAL (op0) < -0x1f) | |
5346 | { | |
5347 | error ("argument 1 must be a 5-bit signed literal"); | |
9a171fcd | 5348 | return const0_rtx; |
b44140e7 | 5349 | } |
b44140e7 AH |
5350 | } |
5351 | ||
c62f2db5 | 5352 | if (target == 0 |
2212663f DB |
5353 | || GET_MODE (target) != tmode |
5354 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
5355 | target = gen_reg_rtx (tmode); | |
5356 | ||
5357 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) | |
5358 | op0 = copy_to_mode_reg (mode0, op0); | |
5359 | ||
5360 | pat = GEN_FCN (icode) (target, op0); | |
5361 | if (! pat) | |
5362 | return 0; | |
5363 | emit_insn (pat); | |
0ac081f6 | 5364 | |
2212663f DB |
5365 | return target; |
5366 | } | |
ae4b4a02 | 5367 | |
100c4561 | 5368 | static rtx |
a2369ed3 | 5369 | altivec_expand_abs_builtin (enum insn_code icode, tree arglist, rtx target) |
100c4561 AH |
5370 | { |
5371 | rtx pat, scratch1, scratch2; | |
5372 | tree arg0 = TREE_VALUE (arglist); | |
5373 | rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
5374 | enum machine_mode tmode = insn_data[icode].operand[0].mode; | |
5375 | enum machine_mode mode0 = insn_data[icode].operand[1].mode; | |
5376 | ||
5377 | /* If we have invalid arguments, bail out before generating bad rtl. */ | |
5378 | if (arg0 == error_mark_node) | |
9a171fcd | 5379 | return const0_rtx; |
100c4561 AH |
5380 | |
5381 | if (target == 0 | |
5382 | || GET_MODE (target) != tmode | |
5383 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
5384 | target = gen_reg_rtx (tmode); | |
5385 | ||
5386 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) | |
5387 | op0 = copy_to_mode_reg (mode0, op0); | |
5388 | ||
5389 | scratch1 = gen_reg_rtx (mode0); | |
5390 | scratch2 = gen_reg_rtx (mode0); | |
5391 | ||
5392 | pat = GEN_FCN (icode) (target, op0, scratch1, scratch2); | |
5393 | if (! pat) | |
5394 | return 0; | |
5395 | emit_insn (pat); | |
5396 | ||
5397 | return target; | |
5398 | } | |
5399 | ||
0ac081f6 | 5400 | static rtx |
a2369ed3 | 5401 | rs6000_expand_binop_builtin (enum insn_code icode, tree arglist, rtx target) |
0ac081f6 AH |
5402 | { |
5403 | rtx pat; | |
5404 | tree arg0 = TREE_VALUE (arglist); | |
5405 | tree arg1 = TREE_VALUE (TREE_CHAIN (arglist)); | |
5406 | rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
5407 | rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); | |
5408 | enum machine_mode tmode = insn_data[icode].operand[0].mode; | |
5409 | enum machine_mode mode0 = insn_data[icode].operand[1].mode; | |
5410 | enum machine_mode mode1 = insn_data[icode].operand[2].mode; | |
5411 | ||
0559cc77 DE |
5412 | if (icode == CODE_FOR_nothing) |
5413 | /* Builtin not supported on this processor. */ | |
5414 | return 0; | |
5415 | ||
20e26713 AH |
5416 | /* If we got invalid arguments bail out before generating bad rtl. */ |
5417 | if (arg0 == error_mark_node || arg1 == error_mark_node) | |
9a171fcd | 5418 | return const0_rtx; |
20e26713 | 5419 | |
0559cc77 DE |
5420 | if (icode == CODE_FOR_altivec_vcfux |
5421 | || icode == CODE_FOR_altivec_vcfsx | |
5422 | || icode == CODE_FOR_altivec_vctsxs | |
5423 | || icode == CODE_FOR_altivec_vctuxs | |
5424 | || icode == CODE_FOR_altivec_vspltb | |
5425 | || icode == CODE_FOR_altivec_vsplth | |
5426 | || icode == CODE_FOR_altivec_vspltw | |
5427 | || icode == CODE_FOR_spe_evaddiw | |
5428 | || icode == CODE_FOR_spe_evldd | |
5429 | || icode == CODE_FOR_spe_evldh | |
5430 | || icode == CODE_FOR_spe_evldw | |
5431 | || icode == CODE_FOR_spe_evlhhesplat | |
5432 | || icode == CODE_FOR_spe_evlhhossplat | |
5433 | || icode == CODE_FOR_spe_evlhhousplat | |
5434 | || icode == CODE_FOR_spe_evlwhe | |
5435 | || icode == CODE_FOR_spe_evlwhos | |
5436 | || icode == CODE_FOR_spe_evlwhou | |
5437 | || icode == CODE_FOR_spe_evlwhsplat | |
5438 | || icode == CODE_FOR_spe_evlwwsplat | |
5439 | || icode == CODE_FOR_spe_evrlwi | |
5440 | || icode == CODE_FOR_spe_evslwi | |
5441 | || icode == CODE_FOR_spe_evsrwis | |
f5119d10 | 5442 | || icode == CODE_FOR_spe_evsubifw |
0559cc77 | 5443 | || icode == CODE_FOR_spe_evsrwiu) |
b44140e7 AH |
5444 | { |
5445 | /* Only allow 5-bit unsigned literals. */ | |
b44140e7 AH |
5446 | if (TREE_CODE (arg1) != INTEGER_CST |
5447 | || TREE_INT_CST_LOW (arg1) & ~0x1f) | |
5448 | { | |
5449 | error ("argument 2 must be a 5-bit unsigned literal"); | |
9a171fcd | 5450 | return const0_rtx; |
b44140e7 | 5451 | } |
b44140e7 AH |
5452 | } |
5453 | ||
c62f2db5 | 5454 | if (target == 0 |
0ac081f6 AH |
5455 | || GET_MODE (target) != tmode |
5456 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
5457 | target = gen_reg_rtx (tmode); | |
5458 | ||
5459 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) | |
5460 | op0 = copy_to_mode_reg (mode0, op0); | |
5461 | if (! (*insn_data[icode].operand[2].predicate) (op1, mode1)) | |
5462 | op1 = copy_to_mode_reg (mode1, op1); | |
5463 | ||
5464 | pat = GEN_FCN (icode) (target, op0, op1); | |
5465 | if (! pat) | |
5466 | return 0; | |
5467 | emit_insn (pat); | |
5468 | ||
5469 | return target; | |
5470 | } | |
6525c0e7 | 5471 | |
ae4b4a02 | 5472 | static rtx |
a2369ed3 DJ |
5473 | altivec_expand_predicate_builtin (enum insn_code icode, const char *opcode, |
5474 | tree arglist, rtx target) | |
ae4b4a02 AH |
5475 | { |
5476 | rtx pat, scratch; | |
5477 | tree cr6_form = TREE_VALUE (arglist); | |
5478 | tree arg0 = TREE_VALUE (TREE_CHAIN (arglist)); | |
5479 | tree arg1 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist))); | |
5480 | rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
5481 | rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); | |
5482 | enum machine_mode tmode = SImode; | |
5483 | enum machine_mode mode0 = insn_data[icode].operand[1].mode; | |
5484 | enum machine_mode mode1 = insn_data[icode].operand[2].mode; | |
5485 | int cr6_form_int; | |
5486 | ||
5487 | if (TREE_CODE (cr6_form) != INTEGER_CST) | |
5488 | { | |
5489 | error ("argument 1 of __builtin_altivec_predicate must be a constant"); | |
9a171fcd | 5490 | return const0_rtx; |
ae4b4a02 AH |
5491 | } |
5492 | else | |
5493 | cr6_form_int = TREE_INT_CST_LOW (cr6_form); | |
5494 | ||
5495 | if (mode0 != mode1) | |
5496 | abort (); | |
5497 | ||
5498 | /* If we have invalid arguments, bail out before generating bad rtl. */ | |
5499 | if (arg0 == error_mark_node || arg1 == error_mark_node) | |
9a171fcd | 5500 | return const0_rtx; |
ae4b4a02 AH |
5501 | |
5502 | if (target == 0 | |
5503 | || GET_MODE (target) != tmode | |
5504 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
5505 | target = gen_reg_rtx (tmode); | |
5506 | ||
5507 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) | |
5508 | op0 = copy_to_mode_reg (mode0, op0); | |
5509 | if (! (*insn_data[icode].operand[2].predicate) (op1, mode1)) | |
5510 | op1 = copy_to_mode_reg (mode1, op1); | |
5511 | ||
5512 | scratch = gen_reg_rtx (mode0); | |
5513 | ||
5514 | pat = GEN_FCN (icode) (scratch, op0, op1, | |
f1c25d3b | 5515 | gen_rtx_SYMBOL_REF (Pmode, opcode)); |
ae4b4a02 AH |
5516 | if (! pat) |
5517 | return 0; | |
5518 | emit_insn (pat); | |
5519 | ||
5520 | /* The vec_any* and vec_all* predicates use the same opcodes for two | |
5521 | different operations, but the bits in CR6 will be different | |
5522 | depending on what information we want. So we have to play tricks | |
5523 | with CR6 to get the right bits out. | |
5524 | ||
5525 | If you think this is disgusting, look at the specs for the | |
5526 | AltiVec predicates. */ | |
5527 | ||
5528 | switch (cr6_form_int) | |
5529 | { | |
5530 | case 0: | |
5531 | emit_insn (gen_cr6_test_for_zero (target)); | |
5532 | break; | |
5533 | case 1: | |
5534 | emit_insn (gen_cr6_test_for_zero_reverse (target)); | |
5535 | break; | |
5536 | case 2: | |
5537 | emit_insn (gen_cr6_test_for_lt (target)); | |
5538 | break; | |
5539 | case 3: | |
5540 | emit_insn (gen_cr6_test_for_lt_reverse (target)); | |
5541 | break; | |
5542 | default: | |
5543 | error ("argument 1 of __builtin_altivec_predicate is out of range"); | |
5544 | break; | |
5545 | } | |
5546 | ||
5547 | return target; | |
5548 | } | |
5549 | ||
b4a62fa0 | 5550 | static rtx |
38f391a5 | 5551 | altivec_expand_lv_builtin (enum insn_code icode, tree arglist, rtx target) |
b4a62fa0 SB |
5552 | { |
5553 | rtx pat, addr; | |
5554 | tree arg0 = TREE_VALUE (arglist); | |
5555 | tree arg1 = TREE_VALUE (TREE_CHAIN (arglist)); | |
5556 | enum machine_mode tmode = insn_data[icode].operand[0].mode; | |
5557 | enum machine_mode mode0 = Pmode; | |
5558 | enum machine_mode mode1 = Pmode; | |
5559 | rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
5560 | rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); | |
5561 | ||
5562 | if (icode == CODE_FOR_nothing) | |
5563 | /* Builtin not supported on this processor. */ | |
5564 | return 0; | |
5565 | ||
5566 | /* If we got invalid arguments bail out before generating bad rtl. */ | |
5567 | if (arg0 == error_mark_node || arg1 == error_mark_node) | |
5568 | return const0_rtx; | |
5569 | ||
5570 | if (target == 0 | |
5571 | || GET_MODE (target) != tmode | |
5572 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
5573 | target = gen_reg_rtx (tmode); | |
5574 | ||
5575 | op1 = copy_to_mode_reg (mode1, op1); | |
5576 | ||
5577 | if (op0 == const0_rtx) | |
5578 | { | |
5579 | addr = gen_rtx_MEM (tmode, op1); | |
5580 | } | |
5581 | else | |
5582 | { | |
5583 | op0 = copy_to_mode_reg (mode0, op0); | |
5584 | addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op0, op1)); | |
5585 | } | |
5586 | ||
5587 | pat = GEN_FCN (icode) (target, addr); | |
5588 | ||
5589 | if (! pat) | |
5590 | return 0; | |
5591 | emit_insn (pat); | |
5592 | ||
5593 | return target; | |
5594 | } | |
5595 | ||
6525c0e7 | 5596 | static rtx |
a2369ed3 | 5597 | altivec_expand_stv_builtin (enum insn_code icode, tree arglist) |
6525c0e7 AH |
5598 | { |
5599 | tree arg0 = TREE_VALUE (arglist); | |
5600 | tree arg1 = TREE_VALUE (TREE_CHAIN (arglist)); | |
5601 | tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist))); | |
5602 | rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
5603 | rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); | |
5604 | rtx op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0); | |
b4a62fa0 SB |
5605 | rtx pat, addr; |
5606 | enum machine_mode tmode = insn_data[icode].operand[0].mode; | |
5607 | enum machine_mode mode1 = Pmode; | |
5608 | enum machine_mode mode2 = Pmode; | |
6525c0e7 AH |
5609 | |
5610 | /* Invalid arguments. Bail before doing anything stoopid! */ | |
5611 | if (arg0 == error_mark_node | |
5612 | || arg1 == error_mark_node | |
5613 | || arg2 == error_mark_node) | |
9a171fcd | 5614 | return const0_rtx; |
6525c0e7 | 5615 | |
b4a62fa0 SB |
5616 | if (! (*insn_data[icode].operand[1].predicate) (op0, tmode)) |
5617 | op0 = copy_to_mode_reg (tmode, op0); | |
5618 | ||
5619 | op2 = copy_to_mode_reg (mode2, op2); | |
5620 | ||
5621 | if (op1 == const0_rtx) | |
5622 | { | |
5623 | addr = gen_rtx_MEM (tmode, op2); | |
5624 | } | |
5625 | else | |
5626 | { | |
5627 | op1 = copy_to_mode_reg (mode1, op1); | |
5628 | addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op1, op2)); | |
5629 | } | |
6525c0e7 | 5630 | |
b4a62fa0 | 5631 | pat = GEN_FCN (icode) (addr, op0); |
6525c0e7 AH |
5632 | if (pat) |
5633 | emit_insn (pat); | |
5634 | return NULL_RTX; | |
5635 | } | |
5636 | ||
2212663f | 5637 | static rtx |
a2369ed3 | 5638 | rs6000_expand_ternop_builtin (enum insn_code icode, tree arglist, rtx target) |
2212663f DB |
5639 | { |
5640 | rtx pat; | |
5641 | tree arg0 = TREE_VALUE (arglist); | |
5642 | tree arg1 = TREE_VALUE (TREE_CHAIN (arglist)); | |
5643 | tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist))); | |
5644 | rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
5645 | rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); | |
5646 | rtx op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0); | |
5647 | enum machine_mode tmode = insn_data[icode].operand[0].mode; | |
5648 | enum machine_mode mode0 = insn_data[icode].operand[1].mode; | |
5649 | enum machine_mode mode1 = insn_data[icode].operand[2].mode; | |
5650 | enum machine_mode mode2 = insn_data[icode].operand[3].mode; | |
0ac081f6 | 5651 | |
774b5662 DE |
5652 | if (icode == CODE_FOR_nothing) |
5653 | /* Builtin not supported on this processor. */ | |
5654 | return 0; | |
5655 | ||
20e26713 AH |
5656 | /* If we got invalid arguments bail out before generating bad rtl. */ |
5657 | if (arg0 == error_mark_node | |
5658 | || arg1 == error_mark_node | |
5659 | || arg2 == error_mark_node) | |
9a171fcd | 5660 | return const0_rtx; |
20e26713 | 5661 | |
774b5662 DE |
5662 | if (icode == CODE_FOR_altivec_vsldoi_4sf |
5663 | || icode == CODE_FOR_altivec_vsldoi_4si | |
5664 | || icode == CODE_FOR_altivec_vsldoi_8hi | |
5665 | || icode == CODE_FOR_altivec_vsldoi_16qi) | |
b44140e7 AH |
5666 | { |
5667 | /* Only allow 4-bit unsigned literals. */ | |
b44140e7 AH |
5668 | if (TREE_CODE (arg2) != INTEGER_CST |
5669 | || TREE_INT_CST_LOW (arg2) & ~0xf) | |
5670 | { | |
5671 | error ("argument 3 must be a 4-bit unsigned literal"); | |
e3277ffb | 5672 | return const0_rtx; |
b44140e7 | 5673 | } |
b44140e7 AH |
5674 | } |
5675 | ||
c62f2db5 | 5676 | if (target == 0 |
2212663f DB |
5677 | || GET_MODE (target) != tmode |
5678 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
5679 | target = gen_reg_rtx (tmode); | |
5680 | ||
5681 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) | |
5682 | op0 = copy_to_mode_reg (mode0, op0); | |
5683 | if (! (*insn_data[icode].operand[2].predicate) (op1, mode1)) | |
5684 | op1 = copy_to_mode_reg (mode1, op1); | |
5685 | if (! (*insn_data[icode].operand[3].predicate) (op2, mode2)) | |
5686 | op2 = copy_to_mode_reg (mode2, op2); | |
5687 | ||
5688 | pat = GEN_FCN (icode) (target, op0, op1, op2); | |
5689 | if (! pat) | |
5690 | return 0; | |
5691 | emit_insn (pat); | |
5692 | ||
5693 | return target; | |
5694 | } | |
92898235 | 5695 | |
3a9b8c7e | 5696 | /* Expand the lvx builtins. */ |
0ac081f6 | 5697 | static rtx |
a2369ed3 | 5698 | altivec_expand_ld_builtin (tree exp, rtx target, bool *expandedp) |
0ac081f6 | 5699 | { |
0ac081f6 AH |
5700 | tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0); |
5701 | tree arglist = TREE_OPERAND (exp, 1); | |
0ac081f6 | 5702 | unsigned int fcode = DECL_FUNCTION_CODE (fndecl); |
3a9b8c7e AH |
5703 | tree arg0; |
5704 | enum machine_mode tmode, mode0; | |
7c3abc73 | 5705 | rtx pat, op0; |
3a9b8c7e | 5706 | enum insn_code icode; |
92898235 | 5707 | |
0ac081f6 AH |
5708 | switch (fcode) |
5709 | { | |
f18c054f DB |
5710 | case ALTIVEC_BUILTIN_LD_INTERNAL_16qi: |
5711 | icode = CODE_FOR_altivec_lvx_16qi; | |
3a9b8c7e | 5712 | break; |
f18c054f DB |
5713 | case ALTIVEC_BUILTIN_LD_INTERNAL_8hi: |
5714 | icode = CODE_FOR_altivec_lvx_8hi; | |
3a9b8c7e AH |
5715 | break; |
5716 | case ALTIVEC_BUILTIN_LD_INTERNAL_4si: | |
5717 | icode = CODE_FOR_altivec_lvx_4si; | |
5718 | break; | |
5719 | case ALTIVEC_BUILTIN_LD_INTERNAL_4sf: | |
5720 | icode = CODE_FOR_altivec_lvx_4sf; | |
5721 | break; | |
5722 | default: | |
5723 | *expandedp = false; | |
5724 | return NULL_RTX; | |
5725 | } | |
0ac081f6 | 5726 | |
3a9b8c7e | 5727 | *expandedp = true; |
f18c054f | 5728 | |
3a9b8c7e AH |
5729 | arg0 = TREE_VALUE (arglist); |
5730 | op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
5731 | tmode = insn_data[icode].operand[0].mode; | |
5732 | mode0 = insn_data[icode].operand[1].mode; | |
f18c054f | 5733 | |
3a9b8c7e AH |
5734 | if (target == 0 |
5735 | || GET_MODE (target) != tmode | |
5736 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
5737 | target = gen_reg_rtx (tmode); | |
24408032 | 5738 | |
3a9b8c7e AH |
5739 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) |
5740 | op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0)); | |
f18c054f | 5741 | |
3a9b8c7e AH |
5742 | pat = GEN_FCN (icode) (target, op0); |
5743 | if (! pat) | |
5744 | return 0; | |
5745 | emit_insn (pat); | |
5746 | return target; | |
5747 | } | |
f18c054f | 5748 | |
3a9b8c7e AH |
5749 | /* Expand the stvx builtins. */ |
5750 | static rtx | |
a2369ed3 DJ |
5751 | altivec_expand_st_builtin (tree exp, rtx target ATTRIBUTE_UNUSED, |
5752 | bool *expandedp) | |
3a9b8c7e AH |
5753 | { |
5754 | tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0); | |
5755 | tree arglist = TREE_OPERAND (exp, 1); | |
5756 | unsigned int fcode = DECL_FUNCTION_CODE (fndecl); | |
5757 | tree arg0, arg1; | |
5758 | enum machine_mode mode0, mode1; | |
7c3abc73 | 5759 | rtx pat, op0, op1; |
3a9b8c7e | 5760 | enum insn_code icode; |
f18c054f | 5761 | |
3a9b8c7e AH |
5762 | switch (fcode) |
5763 | { | |
5764 | case ALTIVEC_BUILTIN_ST_INTERNAL_16qi: | |
5765 | icode = CODE_FOR_altivec_stvx_16qi; | |
5766 | break; | |
5767 | case ALTIVEC_BUILTIN_ST_INTERNAL_8hi: | |
5768 | icode = CODE_FOR_altivec_stvx_8hi; | |
5769 | break; | |
5770 | case ALTIVEC_BUILTIN_ST_INTERNAL_4si: | |
5771 | icode = CODE_FOR_altivec_stvx_4si; | |
5772 | break; | |
5773 | case ALTIVEC_BUILTIN_ST_INTERNAL_4sf: | |
5774 | icode = CODE_FOR_altivec_stvx_4sf; | |
5775 | break; | |
5776 | default: | |
5777 | *expandedp = false; | |
5778 | return NULL_RTX; | |
5779 | } | |
24408032 | 5780 | |
3a9b8c7e AH |
5781 | arg0 = TREE_VALUE (arglist); |
5782 | arg1 = TREE_VALUE (TREE_CHAIN (arglist)); | |
5783 | op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
5784 | op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); | |
5785 | mode0 = insn_data[icode].operand[0].mode; | |
5786 | mode1 = insn_data[icode].operand[1].mode; | |
f18c054f | 5787 | |
3a9b8c7e AH |
5788 | if (! (*insn_data[icode].operand[0].predicate) (op0, mode0)) |
5789 | op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0)); | |
5790 | if (! (*insn_data[icode].operand[1].predicate) (op1, mode1)) | |
5791 | op1 = copy_to_mode_reg (mode1, op1); | |
f18c054f | 5792 | |
3a9b8c7e AH |
5793 | pat = GEN_FCN (icode) (op0, op1); |
5794 | if (pat) | |
5795 | emit_insn (pat); | |
f18c054f | 5796 | |
3a9b8c7e AH |
5797 | *expandedp = true; |
5798 | return NULL_RTX; | |
5799 | } | |
f18c054f | 5800 | |
3a9b8c7e AH |
5801 | /* Expand the dst builtins. */ |
5802 | static rtx | |
a2369ed3 DJ |
5803 | altivec_expand_dst_builtin (tree exp, rtx target ATTRIBUTE_UNUSED, |
5804 | bool *expandedp) | |
3a9b8c7e AH |
5805 | { |
5806 | tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0); | |
5807 | tree arglist = TREE_OPERAND (exp, 1); | |
5808 | unsigned int fcode = DECL_FUNCTION_CODE (fndecl); | |
5809 | tree arg0, arg1, arg2; | |
5810 | enum machine_mode mode0, mode1, mode2; | |
7c3abc73 | 5811 | rtx pat, op0, op1, op2; |
3a9b8c7e | 5812 | struct builtin_description *d; |
a3170dc6 | 5813 | size_t i; |
f18c054f | 5814 | |
3a9b8c7e | 5815 | *expandedp = false; |
f18c054f | 5816 | |
3a9b8c7e AH |
5817 | /* Handle DST variants. */ |
5818 | d = (struct builtin_description *) bdesc_dst; | |
5819 | for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++) | |
5820 | if (d->code == fcode) | |
5821 | { | |
5822 | arg0 = TREE_VALUE (arglist); | |
5823 | arg1 = TREE_VALUE (TREE_CHAIN (arglist)); | |
5824 | arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist))); | |
5825 | op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
5826 | op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); | |
5827 | op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0); | |
5828 | mode0 = insn_data[d->icode].operand[0].mode; | |
5829 | mode1 = insn_data[d->icode].operand[1].mode; | |
5830 | mode2 = insn_data[d->icode].operand[2].mode; | |
24408032 | 5831 | |
3a9b8c7e AH |
5832 | /* Invalid arguments, bail out before generating bad rtl. */ |
5833 | if (arg0 == error_mark_node | |
5834 | || arg1 == error_mark_node | |
5835 | || arg2 == error_mark_node) | |
5836 | return const0_rtx; | |
f18c054f | 5837 | |
3a9b8c7e AH |
5838 | if (TREE_CODE (arg2) != INTEGER_CST |
5839 | || TREE_INT_CST_LOW (arg2) & ~0x3) | |
5840 | { | |
5841 | error ("argument to `%s' must be a 2-bit unsigned literal", d->name); | |
5842 | return const0_rtx; | |
5843 | } | |
f18c054f | 5844 | |
3a9b8c7e | 5845 | if (! (*insn_data[d->icode].operand[0].predicate) (op0, mode0)) |
b4a62fa0 | 5846 | op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0)); |
3a9b8c7e AH |
5847 | if (! (*insn_data[d->icode].operand[1].predicate) (op1, mode1)) |
5848 | op1 = copy_to_mode_reg (mode1, op1); | |
24408032 | 5849 | |
3a9b8c7e AH |
5850 | pat = GEN_FCN (d->icode) (op0, op1, op2); |
5851 | if (pat != 0) | |
5852 | emit_insn (pat); | |
f18c054f | 5853 | |
3a9b8c7e AH |
5854 | *expandedp = true; |
5855 | return NULL_RTX; | |
5856 | } | |
f18c054f | 5857 | |
3a9b8c7e AH |
5858 | return NULL_RTX; |
5859 | } | |
24408032 | 5860 | |
3a9b8c7e AH |
5861 | /* Expand the builtin in EXP and store the result in TARGET. Store |
5862 | true in *EXPANDEDP if we found a builtin to expand. */ | |
5863 | static rtx | |
a2369ed3 | 5864 | altivec_expand_builtin (tree exp, rtx target, bool *expandedp) |
3a9b8c7e AH |
5865 | { |
5866 | struct builtin_description *d; | |
5867 | struct builtin_description_predicates *dp; | |
5868 | size_t i; | |
5869 | enum insn_code icode; | |
5870 | tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0); | |
5871 | tree arglist = TREE_OPERAND (exp, 1); | |
7c3abc73 AH |
5872 | tree arg0; |
5873 | rtx op0, pat; | |
5874 | enum machine_mode tmode, mode0; | |
3a9b8c7e | 5875 | unsigned int fcode = DECL_FUNCTION_CODE (fndecl); |
0ac081f6 | 5876 | |
3a9b8c7e AH |
5877 | target = altivec_expand_ld_builtin (exp, target, expandedp); |
5878 | if (*expandedp) | |
5879 | return target; | |
0ac081f6 | 5880 | |
3a9b8c7e AH |
5881 | target = altivec_expand_st_builtin (exp, target, expandedp); |
5882 | if (*expandedp) | |
5883 | return target; | |
5884 | ||
5885 | target = altivec_expand_dst_builtin (exp, target, expandedp); | |
5886 | if (*expandedp) | |
5887 | return target; | |
5888 | ||
5889 | *expandedp = true; | |
95385cbb | 5890 | |
3a9b8c7e AH |
5891 | switch (fcode) |
5892 | { | |
6525c0e7 AH |
5893 | case ALTIVEC_BUILTIN_STVX: |
5894 | return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx, arglist); | |
5895 | case ALTIVEC_BUILTIN_STVEBX: | |
5896 | return altivec_expand_stv_builtin (CODE_FOR_altivec_stvebx, arglist); | |
5897 | case ALTIVEC_BUILTIN_STVEHX: | |
5898 | return altivec_expand_stv_builtin (CODE_FOR_altivec_stvehx, arglist); | |
5899 | case ALTIVEC_BUILTIN_STVEWX: | |
5900 | return altivec_expand_stv_builtin (CODE_FOR_altivec_stvewx, arglist); | |
5901 | case ALTIVEC_BUILTIN_STVXL: | |
5902 | return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl, arglist); | |
3a9b8c7e | 5903 | |
95385cbb AH |
5904 | case ALTIVEC_BUILTIN_MFVSCR: |
5905 | icode = CODE_FOR_altivec_mfvscr; | |
5906 | tmode = insn_data[icode].operand[0].mode; | |
5907 | ||
5908 | if (target == 0 | |
5909 | || GET_MODE (target) != tmode | |
5910 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
5911 | target = gen_reg_rtx (tmode); | |
5912 | ||
5913 | pat = GEN_FCN (icode) (target); | |
0ac081f6 AH |
5914 | if (! pat) |
5915 | return 0; | |
5916 | emit_insn (pat); | |
95385cbb AH |
5917 | return target; |
5918 | ||
5919 | case ALTIVEC_BUILTIN_MTVSCR: | |
5920 | icode = CODE_FOR_altivec_mtvscr; | |
5921 | arg0 = TREE_VALUE (arglist); | |
5922 | op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
5923 | mode0 = insn_data[icode].operand[0].mode; | |
5924 | ||
5925 | /* If we got invalid arguments bail out before generating bad rtl. */ | |
5926 | if (arg0 == error_mark_node) | |
9a171fcd | 5927 | return const0_rtx; |
95385cbb AH |
5928 | |
5929 | if (! (*insn_data[icode].operand[0].predicate) (op0, mode0)) | |
5930 | op0 = copy_to_mode_reg (mode0, op0); | |
5931 | ||
5932 | pat = GEN_FCN (icode) (op0); | |
5933 | if (pat) | |
5934 | emit_insn (pat); | |
5935 | return NULL_RTX; | |
3a9b8c7e | 5936 | |
95385cbb AH |
5937 | case ALTIVEC_BUILTIN_DSSALL: |
5938 | emit_insn (gen_altivec_dssall ()); | |
5939 | return NULL_RTX; | |
5940 | ||
5941 | case ALTIVEC_BUILTIN_DSS: | |
5942 | icode = CODE_FOR_altivec_dss; | |
5943 | arg0 = TREE_VALUE (arglist); | |
5944 | op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
5945 | mode0 = insn_data[icode].operand[0].mode; | |
5946 | ||
5947 | /* If we got invalid arguments bail out before generating bad rtl. */ | |
5948 | if (arg0 == error_mark_node) | |
9a171fcd | 5949 | return const0_rtx; |
95385cbb | 5950 | |
b44140e7 AH |
5951 | if (TREE_CODE (arg0) != INTEGER_CST |
5952 | || TREE_INT_CST_LOW (arg0) & ~0x3) | |
5953 | { | |
5954 | error ("argument to dss must be a 2-bit unsigned literal"); | |
9a171fcd | 5955 | return const0_rtx; |
b44140e7 AH |
5956 | } |
5957 | ||
95385cbb AH |
5958 | if (! (*insn_data[icode].operand[0].predicate) (op0, mode0)) |
5959 | op0 = copy_to_mode_reg (mode0, op0); | |
5960 | ||
5961 | emit_insn (gen_altivec_dss (op0)); | |
0ac081f6 AH |
5962 | return NULL_RTX; |
5963 | } | |
24408032 | 5964 | |
100c4561 AH |
5965 | /* Expand abs* operations. */ |
5966 | d = (struct builtin_description *) bdesc_abs; | |
ca7558fc | 5967 | for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++) |
100c4561 AH |
5968 | if (d->code == fcode) |
5969 | return altivec_expand_abs_builtin (d->icode, arglist, target); | |
5970 | ||
ae4b4a02 AH |
5971 | /* Expand the AltiVec predicates. */ |
5972 | dp = (struct builtin_description_predicates *) bdesc_altivec_preds; | |
ca7558fc | 5973 | for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, dp++) |
ae4b4a02 AH |
5974 | if (dp->code == fcode) |
5975 | return altivec_expand_predicate_builtin (dp->icode, dp->opcode, arglist, target); | |
5976 | ||
6525c0e7 AH |
5977 | /* LV* are funky. We initialized them differently. */ |
5978 | switch (fcode) | |
5979 | { | |
5980 | case ALTIVEC_BUILTIN_LVSL: | |
b4a62fa0 | 5981 | return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsl, |
6525c0e7 AH |
5982 | arglist, target); |
5983 | case ALTIVEC_BUILTIN_LVSR: | |
b4a62fa0 | 5984 | return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsr, |
92898235 | 5985 | arglist, target); |
6525c0e7 | 5986 | case ALTIVEC_BUILTIN_LVEBX: |
b4a62fa0 | 5987 | return altivec_expand_lv_builtin (CODE_FOR_altivec_lvebx, |
92898235 | 5988 | arglist, target); |
6525c0e7 | 5989 | case ALTIVEC_BUILTIN_LVEHX: |
b4a62fa0 | 5990 | return altivec_expand_lv_builtin (CODE_FOR_altivec_lvehx, |
92898235 | 5991 | arglist, target); |
6525c0e7 | 5992 | case ALTIVEC_BUILTIN_LVEWX: |
b4a62fa0 | 5993 | return altivec_expand_lv_builtin (CODE_FOR_altivec_lvewx, |
92898235 | 5994 | arglist, target); |
6525c0e7 | 5995 | case ALTIVEC_BUILTIN_LVXL: |
b4a62fa0 | 5996 | return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl, |
92898235 | 5997 | arglist, target); |
6525c0e7 | 5998 | case ALTIVEC_BUILTIN_LVX: |
b4a62fa0 | 5999 | return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx, |
92898235 | 6000 | arglist, target); |
6525c0e7 AH |
6001 | default: |
6002 | break; | |
6003 | /* Fall through. */ | |
6004 | } | |
95385cbb | 6005 | |
92898235 | 6006 | *expandedp = false; |
0ac081f6 AH |
6007 | return NULL_RTX; |
6008 | } | |
6009 | ||
a3170dc6 AH |
6010 | /* Binops that need to be initialized manually, but can be expanded |
6011 | automagically by rs6000_expand_binop_builtin. */ | |
6012 | static struct builtin_description bdesc_2arg_spe[] = | |
6013 | { | |
6014 | { 0, CODE_FOR_spe_evlddx, "__builtin_spe_evlddx", SPE_BUILTIN_EVLDDX }, | |
6015 | { 0, CODE_FOR_spe_evldwx, "__builtin_spe_evldwx", SPE_BUILTIN_EVLDWX }, | |
6016 | { 0, CODE_FOR_spe_evldhx, "__builtin_spe_evldhx", SPE_BUILTIN_EVLDHX }, | |
6017 | { 0, CODE_FOR_spe_evlwhex, "__builtin_spe_evlwhex", SPE_BUILTIN_EVLWHEX }, | |
6018 | { 0, CODE_FOR_spe_evlwhoux, "__builtin_spe_evlwhoux", SPE_BUILTIN_EVLWHOUX }, | |
6019 | { 0, CODE_FOR_spe_evlwhosx, "__builtin_spe_evlwhosx", SPE_BUILTIN_EVLWHOSX }, | |
6020 | { 0, CODE_FOR_spe_evlwwsplatx, "__builtin_spe_evlwwsplatx", SPE_BUILTIN_EVLWWSPLATX }, | |
6021 | { 0, CODE_FOR_spe_evlwhsplatx, "__builtin_spe_evlwhsplatx", SPE_BUILTIN_EVLWHSPLATX }, | |
6022 | { 0, CODE_FOR_spe_evlhhesplatx, "__builtin_spe_evlhhesplatx", SPE_BUILTIN_EVLHHESPLATX }, | |
6023 | { 0, CODE_FOR_spe_evlhhousplatx, "__builtin_spe_evlhhousplatx", SPE_BUILTIN_EVLHHOUSPLATX }, | |
6024 | { 0, CODE_FOR_spe_evlhhossplatx, "__builtin_spe_evlhhossplatx", SPE_BUILTIN_EVLHHOSSPLATX }, | |
6025 | { 0, CODE_FOR_spe_evldd, "__builtin_spe_evldd", SPE_BUILTIN_EVLDD }, | |
6026 | { 0, CODE_FOR_spe_evldw, "__builtin_spe_evldw", SPE_BUILTIN_EVLDW }, | |
6027 | { 0, CODE_FOR_spe_evldh, "__builtin_spe_evldh", SPE_BUILTIN_EVLDH }, | |
6028 | { 0, CODE_FOR_spe_evlwhe, "__builtin_spe_evlwhe", SPE_BUILTIN_EVLWHE }, | |
6029 | { 0, CODE_FOR_spe_evlwhou, "__builtin_spe_evlwhou", SPE_BUILTIN_EVLWHOU }, | |
6030 | { 0, CODE_FOR_spe_evlwhos, "__builtin_spe_evlwhos", SPE_BUILTIN_EVLWHOS }, | |
6031 | { 0, CODE_FOR_spe_evlwwsplat, "__builtin_spe_evlwwsplat", SPE_BUILTIN_EVLWWSPLAT }, | |
6032 | { 0, CODE_FOR_spe_evlwhsplat, "__builtin_spe_evlwhsplat", SPE_BUILTIN_EVLWHSPLAT }, | |
6033 | { 0, CODE_FOR_spe_evlhhesplat, "__builtin_spe_evlhhesplat", SPE_BUILTIN_EVLHHESPLAT }, | |
6034 | { 0, CODE_FOR_spe_evlhhousplat, "__builtin_spe_evlhhousplat", SPE_BUILTIN_EVLHHOUSPLAT }, | |
6035 | { 0, CODE_FOR_spe_evlhhossplat, "__builtin_spe_evlhhossplat", SPE_BUILTIN_EVLHHOSSPLAT } | |
6036 | }; | |
6037 | ||
6038 | /* Expand the builtin in EXP and store the result in TARGET. Store | |
6039 | true in *EXPANDEDP if we found a builtin to expand. | |
6040 | ||
6041 | This expands the SPE builtins that are not simple unary and binary | |
6042 | operations. */ | |
6043 | static rtx | |
a2369ed3 | 6044 | spe_expand_builtin (tree exp, rtx target, bool *expandedp) |
a3170dc6 AH |
6045 | { |
6046 | tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0); | |
6047 | tree arglist = TREE_OPERAND (exp, 1); | |
6048 | tree arg1, arg0; | |
6049 | unsigned int fcode = DECL_FUNCTION_CODE (fndecl); | |
6050 | enum insn_code icode; | |
6051 | enum machine_mode tmode, mode0; | |
6052 | rtx pat, op0; | |
6053 | struct builtin_description *d; | |
6054 | size_t i; | |
6055 | ||
6056 | *expandedp = true; | |
6057 | ||
6058 | /* Syntax check for a 5-bit unsigned immediate. */ | |
6059 | switch (fcode) | |
6060 | { | |
6061 | case SPE_BUILTIN_EVSTDD: | |
6062 | case SPE_BUILTIN_EVSTDH: | |
6063 | case SPE_BUILTIN_EVSTDW: | |
6064 | case SPE_BUILTIN_EVSTWHE: | |
6065 | case SPE_BUILTIN_EVSTWHO: | |
6066 | case SPE_BUILTIN_EVSTWWE: | |
6067 | case SPE_BUILTIN_EVSTWWO: | |
6068 | arg1 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist))); | |
6069 | if (TREE_CODE (arg1) != INTEGER_CST | |
6070 | || TREE_INT_CST_LOW (arg1) & ~0x1f) | |
6071 | { | |
6072 | error ("argument 2 must be a 5-bit unsigned literal"); | |
6073 | return const0_rtx; | |
6074 | } | |
6075 | break; | |
6076 | default: | |
6077 | break; | |
6078 | } | |
6079 | ||
00332c9f AH |
6080 | /* The evsplat*i instructions are not quite generic. */ |
6081 | switch (fcode) | |
6082 | { | |
6083 | case SPE_BUILTIN_EVSPLATFI: | |
6084 | return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplatfi, | |
6085 | arglist, target); | |
6086 | case SPE_BUILTIN_EVSPLATI: | |
6087 | return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplati, | |
6088 | arglist, target); | |
6089 | default: | |
6090 | break; | |
6091 | } | |
6092 | ||
a3170dc6 AH |
6093 | d = (struct builtin_description *) bdesc_2arg_spe; |
6094 | for (i = 0; i < ARRAY_SIZE (bdesc_2arg_spe); ++i, ++d) | |
6095 | if (d->code == fcode) | |
6096 | return rs6000_expand_binop_builtin (d->icode, arglist, target); | |
6097 | ||
6098 | d = (struct builtin_description *) bdesc_spe_predicates; | |
6099 | for (i = 0; i < ARRAY_SIZE (bdesc_spe_predicates); ++i, ++d) | |
6100 | if (d->code == fcode) | |
6101 | return spe_expand_predicate_builtin (d->icode, arglist, target); | |
6102 | ||
6103 | d = (struct builtin_description *) bdesc_spe_evsel; | |
6104 | for (i = 0; i < ARRAY_SIZE (bdesc_spe_evsel); ++i, ++d) | |
6105 | if (d->code == fcode) | |
6106 | return spe_expand_evsel_builtin (d->icode, arglist, target); | |
6107 | ||
6108 | switch (fcode) | |
6109 | { | |
6110 | case SPE_BUILTIN_EVSTDDX: | |
6111 | return altivec_expand_stv_builtin (CODE_FOR_spe_evstddx, arglist); | |
6112 | case SPE_BUILTIN_EVSTDHX: | |
6113 | return altivec_expand_stv_builtin (CODE_FOR_spe_evstdhx, arglist); | |
6114 | case SPE_BUILTIN_EVSTDWX: | |
6115 | return altivec_expand_stv_builtin (CODE_FOR_spe_evstdwx, arglist); | |
6116 | case SPE_BUILTIN_EVSTWHEX: | |
6117 | return altivec_expand_stv_builtin (CODE_FOR_spe_evstwhex, arglist); | |
6118 | case SPE_BUILTIN_EVSTWHOX: | |
6119 | return altivec_expand_stv_builtin (CODE_FOR_spe_evstwhox, arglist); | |
6120 | case SPE_BUILTIN_EVSTWWEX: | |
6121 | return altivec_expand_stv_builtin (CODE_FOR_spe_evstwwex, arglist); | |
6122 | case SPE_BUILTIN_EVSTWWOX: | |
6123 | return altivec_expand_stv_builtin (CODE_FOR_spe_evstwwox, arglist); | |
6124 | case SPE_BUILTIN_EVSTDD: | |
6125 | return altivec_expand_stv_builtin (CODE_FOR_spe_evstdd, arglist); | |
6126 | case SPE_BUILTIN_EVSTDH: | |
6127 | return altivec_expand_stv_builtin (CODE_FOR_spe_evstdh, arglist); | |
6128 | case SPE_BUILTIN_EVSTDW: | |
6129 | return altivec_expand_stv_builtin (CODE_FOR_spe_evstdw, arglist); | |
6130 | case SPE_BUILTIN_EVSTWHE: | |
6131 | return altivec_expand_stv_builtin (CODE_FOR_spe_evstwhe, arglist); | |
6132 | case SPE_BUILTIN_EVSTWHO: | |
6133 | return altivec_expand_stv_builtin (CODE_FOR_spe_evstwho, arglist); | |
6134 | case SPE_BUILTIN_EVSTWWE: | |
6135 | return altivec_expand_stv_builtin (CODE_FOR_spe_evstwwe, arglist); | |
6136 | case SPE_BUILTIN_EVSTWWO: | |
6137 | return altivec_expand_stv_builtin (CODE_FOR_spe_evstwwo, arglist); | |
6138 | case SPE_BUILTIN_MFSPEFSCR: | |
6139 | icode = CODE_FOR_spe_mfspefscr; | |
6140 | tmode = insn_data[icode].operand[0].mode; | |
6141 | ||
6142 | if (target == 0 | |
6143 | || GET_MODE (target) != tmode | |
6144 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
6145 | target = gen_reg_rtx (tmode); | |
6146 | ||
6147 | pat = GEN_FCN (icode) (target); | |
6148 | if (! pat) | |
6149 | return 0; | |
6150 | emit_insn (pat); | |
6151 | return target; | |
6152 | case SPE_BUILTIN_MTSPEFSCR: | |
6153 | icode = CODE_FOR_spe_mtspefscr; | |
6154 | arg0 = TREE_VALUE (arglist); | |
6155 | op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
6156 | mode0 = insn_data[icode].operand[0].mode; | |
6157 | ||
6158 | if (arg0 == error_mark_node) | |
6159 | return const0_rtx; | |
6160 | ||
6161 | if (! (*insn_data[icode].operand[0].predicate) (op0, mode0)) | |
6162 | op0 = copy_to_mode_reg (mode0, op0); | |
6163 | ||
6164 | pat = GEN_FCN (icode) (op0); | |
6165 | if (pat) | |
6166 | emit_insn (pat); | |
6167 | return NULL_RTX; | |
6168 | default: | |
6169 | break; | |
6170 | } | |
6171 | ||
6172 | *expandedp = false; | |
6173 | return NULL_RTX; | |
6174 | } | |
6175 | ||
6176 | static rtx | |
a2369ed3 | 6177 | spe_expand_predicate_builtin (enum insn_code icode, tree arglist, rtx target) |
a3170dc6 AH |
6178 | { |
6179 | rtx pat, scratch, tmp; | |
6180 | tree form = TREE_VALUE (arglist); | |
6181 | tree arg0 = TREE_VALUE (TREE_CHAIN (arglist)); | |
6182 | tree arg1 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist))); | |
6183 | rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
6184 | rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); | |
6185 | enum machine_mode mode0 = insn_data[icode].operand[1].mode; | |
6186 | enum machine_mode mode1 = insn_data[icode].operand[2].mode; | |
6187 | int form_int; | |
6188 | enum rtx_code code; | |
6189 | ||
6190 | if (TREE_CODE (form) != INTEGER_CST) | |
6191 | { | |
6192 | error ("argument 1 of __builtin_spe_predicate must be a constant"); | |
6193 | return const0_rtx; | |
6194 | } | |
6195 | else | |
6196 | form_int = TREE_INT_CST_LOW (form); | |
6197 | ||
6198 | if (mode0 != mode1) | |
6199 | abort (); | |
6200 | ||
6201 | if (arg0 == error_mark_node || arg1 == error_mark_node) | |
6202 | return const0_rtx; | |
6203 | ||
6204 | if (target == 0 | |
6205 | || GET_MODE (target) != SImode | |
6206 | || ! (*insn_data[icode].operand[0].predicate) (target, SImode)) | |
6207 | target = gen_reg_rtx (SImode); | |
6208 | ||
6209 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) | |
6210 | op0 = copy_to_mode_reg (mode0, op0); | |
6211 | if (! (*insn_data[icode].operand[2].predicate) (op1, mode1)) | |
6212 | op1 = copy_to_mode_reg (mode1, op1); | |
6213 | ||
6214 | scratch = gen_reg_rtx (CCmode); | |
6215 | ||
6216 | pat = GEN_FCN (icode) (scratch, op0, op1); | |
6217 | if (! pat) | |
6218 | return const0_rtx; | |
6219 | emit_insn (pat); | |
6220 | ||
6221 | /* There are 4 variants for each predicate: _any_, _all_, _upper_, | |
6222 | _lower_. We use one compare, but look in different bits of the | |
6223 | CR for each variant. | |
6224 | ||
6225 | There are 2 elements in each SPE simd type (upper/lower). The CR | |
6226 | bits are set as follows: | |
6227 | ||
6228 | BIT0 | BIT 1 | BIT 2 | BIT 3 | |
6229 | U | L | (U | L) | (U & L) | |
6230 | ||
6231 | So, for an "all" relationship, BIT 3 would be set. | |
6232 | For an "any" relationship, BIT 2 would be set. Etc. | |
6233 | ||
6234 | Following traditional nomenclature, these bits map to: | |
6235 | ||
6236 | BIT0 | BIT 1 | BIT 2 | BIT 3 | |
6237 | LT | GT | EQ | OV | |
6238 | ||
6239 | Later, we will generate rtl to look in the LT/EQ/EQ/OV bits. | |
6240 | */ | |
6241 | ||
6242 | switch (form_int) | |
6243 | { | |
6244 | /* All variant. OV bit. */ | |
6245 | case 0: | |
6246 | /* We need to get to the OV bit, which is the ORDERED bit. We | |
6247 | could generate (ordered:SI (reg:CC xx) (const_int 0)), but | |
6248 | that's ugly and will trigger a validate_condition_mode abort. | |
6249 | So let's just use another pattern. */ | |
6250 | emit_insn (gen_move_from_CR_ov_bit (target, scratch)); | |
6251 | return target; | |
6252 | /* Any variant. EQ bit. */ | |
6253 | case 1: | |
6254 | code = EQ; | |
6255 | break; | |
6256 | /* Upper variant. LT bit. */ | |
6257 | case 2: | |
6258 | code = LT; | |
6259 | break; | |
6260 | /* Lower variant. GT bit. */ | |
6261 | case 3: | |
6262 | code = GT; | |
6263 | break; | |
6264 | default: | |
6265 | error ("argument 1 of __builtin_spe_predicate is out of range"); | |
6266 | return const0_rtx; | |
6267 | } | |
6268 | ||
6269 | tmp = gen_rtx_fmt_ee (code, SImode, scratch, const0_rtx); | |
6270 | emit_move_insn (target, tmp); | |
6271 | ||
6272 | return target; | |
6273 | } | |
6274 | ||
6275 | /* The evsel builtins look like this: | |
6276 | ||
6277 | e = __builtin_spe_evsel_OP (a, b, c, d); | |
6278 | ||
6279 | and work like this: | |
6280 | ||
6281 | e[upper] = a[upper] *OP* b[upper] ? c[upper] : d[upper]; | |
6282 | e[lower] = a[lower] *OP* b[lower] ? c[lower] : d[lower]; | |
6283 | */ | |
6284 | ||
6285 | static rtx | |
a2369ed3 | 6286 | spe_expand_evsel_builtin (enum insn_code icode, tree arglist, rtx target) |
a3170dc6 AH |
6287 | { |
6288 | rtx pat, scratch; | |
6289 | tree arg0 = TREE_VALUE (arglist); | |
6290 | tree arg1 = TREE_VALUE (TREE_CHAIN (arglist)); | |
6291 | tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist))); | |
6292 | tree arg3 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (TREE_CHAIN (arglist)))); | |
6293 | rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
6294 | rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); | |
6295 | rtx op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0); | |
6296 | rtx op3 = expand_expr (arg3, NULL_RTX, VOIDmode, 0); | |
6297 | enum machine_mode mode0 = insn_data[icode].operand[1].mode; | |
6298 | enum machine_mode mode1 = insn_data[icode].operand[2].mode; | |
6299 | ||
6300 | if (mode0 != mode1) | |
6301 | abort (); | |
6302 | ||
6303 | if (arg0 == error_mark_node || arg1 == error_mark_node | |
6304 | || arg2 == error_mark_node || arg3 == error_mark_node) | |
6305 | return const0_rtx; | |
6306 | ||
6307 | if (target == 0 | |
6308 | || GET_MODE (target) != mode0 | |
6309 | || ! (*insn_data[icode].operand[0].predicate) (target, mode0)) | |
6310 | target = gen_reg_rtx (mode0); | |
6311 | ||
6312 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) | |
6313 | op0 = copy_to_mode_reg (mode0, op0); | |
6314 | if (! (*insn_data[icode].operand[1].predicate) (op1, mode1)) | |
6315 | op1 = copy_to_mode_reg (mode0, op1); | |
6316 | if (! (*insn_data[icode].operand[1].predicate) (op2, mode1)) | |
6317 | op2 = copy_to_mode_reg (mode0, op2); | |
6318 | if (! (*insn_data[icode].operand[1].predicate) (op3, mode1)) | |
6319 | op3 = copy_to_mode_reg (mode0, op3); | |
6320 | ||
6321 | /* Generate the compare. */ | |
6322 | scratch = gen_reg_rtx (CCmode); | |
6323 | pat = GEN_FCN (icode) (scratch, op0, op1); | |
6324 | if (! pat) | |
6325 | return const0_rtx; | |
6326 | emit_insn (pat); | |
6327 | ||
6328 | if (mode0 == V2SImode) | |
6329 | emit_insn (gen_spe_evsel (target, op2, op3, scratch)); | |
6330 | else | |
6331 | emit_insn (gen_spe_evsel_fs (target, op2, op3, scratch)); | |
6332 | ||
6333 | return target; | |
6334 | } | |
6335 | ||
0ac081f6 AH |
6336 | /* Expand an expression EXP that calls a built-in function, |
6337 | with result going to TARGET if that's convenient | |
6338 | (and in mode MODE if that's convenient). | |
6339 | SUBTARGET may be used as the target for computing one of EXP's operands. | |
6340 | IGNORE is nonzero if the value is to be ignored. */ | |
6341 | ||
6342 | static rtx | |
a2369ed3 DJ |
6343 | rs6000_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED, |
6344 | enum machine_mode mode ATTRIBUTE_UNUSED, | |
6345 | int ignore ATTRIBUTE_UNUSED) | |
0ac081f6 | 6346 | { |
92898235 AH |
6347 | tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0); |
6348 | tree arglist = TREE_OPERAND (exp, 1); | |
6349 | unsigned int fcode = DECL_FUNCTION_CODE (fndecl); | |
6350 | struct builtin_description *d; | |
6351 | size_t i; | |
6352 | rtx ret; | |
6353 | bool success; | |
6354 | ||
0ac081f6 | 6355 | if (TARGET_ALTIVEC) |
92898235 AH |
6356 | { |
6357 | ret = altivec_expand_builtin (exp, target, &success); | |
6358 | ||
a3170dc6 AH |
6359 | if (success) |
6360 | return ret; | |
6361 | } | |
6362 | if (TARGET_SPE) | |
6363 | { | |
6364 | ret = spe_expand_builtin (exp, target, &success); | |
6365 | ||
92898235 AH |
6366 | if (success) |
6367 | return ret; | |
6368 | } | |
6369 | ||
0559cc77 DE |
6370 | if (TARGET_ALTIVEC || TARGET_SPE) |
6371 | { | |
6372 | /* Handle simple unary operations. */ | |
6373 | d = (struct builtin_description *) bdesc_1arg; | |
6374 | for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++) | |
6375 | if (d->code == fcode) | |
6376 | return rs6000_expand_unop_builtin (d->icode, arglist, target); | |
6377 | ||
6378 | /* Handle simple binary operations. */ | |
6379 | d = (struct builtin_description *) bdesc_2arg; | |
6380 | for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++) | |
6381 | if (d->code == fcode) | |
6382 | return rs6000_expand_binop_builtin (d->icode, arglist, target); | |
6383 | ||
6384 | /* Handle simple ternary operations. */ | |
6385 | d = (struct builtin_description *) bdesc_3arg; | |
6386 | for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++) | |
6387 | if (d->code == fcode) | |
6388 | return rs6000_expand_ternop_builtin (d->icode, arglist, target); | |
6389 | } | |
0ac081f6 AH |
6390 | |
6391 | abort (); | |
92898235 | 6392 | return NULL_RTX; |
0ac081f6 AH |
6393 | } |
6394 | ||
6395 | static void | |
863d938c | 6396 | rs6000_init_builtins (void) |
0ac081f6 | 6397 | { |
3fdaa45a AH |
6398 | opaque_V2SI_type_node = copy_node (V2SI_type_node); |
6399 | opaque_V2SF_type_node = copy_node (V2SF_type_node); | |
6035d635 | 6400 | opaque_p_V2SI_type_node = build_pointer_type (opaque_V2SI_type_node); |
3fdaa45a | 6401 | |
a3170dc6 | 6402 | if (TARGET_SPE) |
3fdaa45a | 6403 | spe_init_builtins (); |
0ac081f6 AH |
6404 | if (TARGET_ALTIVEC) |
6405 | altivec_init_builtins (); | |
0559cc77 DE |
6406 | if (TARGET_ALTIVEC || TARGET_SPE) |
6407 | rs6000_common_init_builtins (); | |
0ac081f6 AH |
6408 | } |
6409 | ||
a3170dc6 AH |
6410 | /* Search through a set of builtins and enable the mask bits. |
6411 | DESC is an array of builtins. | |
b6d08ca1 | 6412 | SIZE is the total number of builtins. |
a3170dc6 AH |
6413 | START is the builtin enum at which to start. |
6414 | END is the builtin enum at which to end. */ | |
0ac081f6 | 6415 | static void |
a2369ed3 DJ |
6416 | enable_mask_for_builtins (struct builtin_description *desc, int size, |
6417 | enum rs6000_builtins start, | |
6418 | enum rs6000_builtins end) | |
a3170dc6 AH |
6419 | { |
6420 | int i; | |
6421 | ||
6422 | for (i = 0; i < size; ++i) | |
6423 | if (desc[i].code == start) | |
6424 | break; | |
6425 | ||
6426 | if (i == size) | |
6427 | return; | |
6428 | ||
6429 | for (; i < size; ++i) | |
6430 | { | |
6431 | /* Flip all the bits on. */ | |
6432 | desc[i].mask = target_flags; | |
6433 | if (desc[i].code == end) | |
6434 | break; | |
6435 | } | |
6436 | } | |
6437 | ||
6438 | static void | |
863d938c | 6439 | spe_init_builtins (void) |
0ac081f6 | 6440 | { |
a3170dc6 AH |
6441 | tree endlink = void_list_node; |
6442 | tree puint_type_node = build_pointer_type (unsigned_type_node); | |
6443 | tree pushort_type_node = build_pointer_type (short_unsigned_type_node); | |
ae4b4a02 | 6444 | struct builtin_description *d; |
0ac081f6 AH |
6445 | size_t i; |
6446 | ||
a3170dc6 AH |
6447 | tree v2si_ftype_4_v2si |
6448 | = build_function_type | |
3fdaa45a AH |
6449 | (opaque_V2SI_type_node, |
6450 | tree_cons (NULL_TREE, opaque_V2SI_type_node, | |
6451 | tree_cons (NULL_TREE, opaque_V2SI_type_node, | |
6452 | tree_cons (NULL_TREE, opaque_V2SI_type_node, | |
6453 | tree_cons (NULL_TREE, opaque_V2SI_type_node, | |
a3170dc6 AH |
6454 | endlink))))); |
6455 | ||
6456 | tree v2sf_ftype_4_v2sf | |
6457 | = build_function_type | |
3fdaa45a AH |
6458 | (opaque_V2SF_type_node, |
6459 | tree_cons (NULL_TREE, opaque_V2SF_type_node, | |
6460 | tree_cons (NULL_TREE, opaque_V2SF_type_node, | |
6461 | tree_cons (NULL_TREE, opaque_V2SF_type_node, | |
6462 | tree_cons (NULL_TREE, opaque_V2SF_type_node, | |
a3170dc6 AH |
6463 | endlink))))); |
6464 | ||
6465 | tree int_ftype_int_v2si_v2si | |
6466 | = build_function_type | |
6467 | (integer_type_node, | |
6468 | tree_cons (NULL_TREE, integer_type_node, | |
3fdaa45a AH |
6469 | tree_cons (NULL_TREE, opaque_V2SI_type_node, |
6470 | tree_cons (NULL_TREE, opaque_V2SI_type_node, | |
a3170dc6 AH |
6471 | endlink)))); |
6472 | ||
6473 | tree int_ftype_int_v2sf_v2sf | |
6474 | = build_function_type | |
6475 | (integer_type_node, | |
6476 | tree_cons (NULL_TREE, integer_type_node, | |
3fdaa45a AH |
6477 | tree_cons (NULL_TREE, opaque_V2SF_type_node, |
6478 | tree_cons (NULL_TREE, opaque_V2SF_type_node, | |
a3170dc6 AH |
6479 | endlink)))); |
6480 | ||
6481 | tree void_ftype_v2si_puint_int | |
6482 | = build_function_type (void_type_node, | |
3fdaa45a | 6483 | tree_cons (NULL_TREE, opaque_V2SI_type_node, |
a3170dc6 AH |
6484 | tree_cons (NULL_TREE, puint_type_node, |
6485 | tree_cons (NULL_TREE, | |
6486 | integer_type_node, | |
6487 | endlink)))); | |
6488 | ||
6489 | tree void_ftype_v2si_puint_char | |
6490 | = build_function_type (void_type_node, | |
3fdaa45a | 6491 | tree_cons (NULL_TREE, opaque_V2SI_type_node, |
a3170dc6 AH |
6492 | tree_cons (NULL_TREE, puint_type_node, |
6493 | tree_cons (NULL_TREE, | |
6494 | char_type_node, | |
6495 | endlink)))); | |
6496 | ||
6497 | tree void_ftype_v2si_pv2si_int | |
6498 | = build_function_type (void_type_node, | |
3fdaa45a | 6499 | tree_cons (NULL_TREE, opaque_V2SI_type_node, |
6035d635 | 6500 | tree_cons (NULL_TREE, opaque_p_V2SI_type_node, |
a3170dc6 AH |
6501 | tree_cons (NULL_TREE, |
6502 | integer_type_node, | |
6503 | endlink)))); | |
6504 | ||
6505 | tree void_ftype_v2si_pv2si_char | |
6506 | = build_function_type (void_type_node, | |
3fdaa45a | 6507 | tree_cons (NULL_TREE, opaque_V2SI_type_node, |
6035d635 | 6508 | tree_cons (NULL_TREE, opaque_p_V2SI_type_node, |
a3170dc6 AH |
6509 | tree_cons (NULL_TREE, |
6510 | char_type_node, | |
6511 | endlink)))); | |
6512 | ||
6513 | tree void_ftype_int | |
6514 | = build_function_type (void_type_node, | |
6515 | tree_cons (NULL_TREE, integer_type_node, endlink)); | |
6516 | ||
6517 | tree int_ftype_void | |
36e8d515 | 6518 | = build_function_type (integer_type_node, endlink); |
a3170dc6 AH |
6519 | |
6520 | tree v2si_ftype_pv2si_int | |
3fdaa45a | 6521 | = build_function_type (opaque_V2SI_type_node, |
6035d635 | 6522 | tree_cons (NULL_TREE, opaque_p_V2SI_type_node, |
a3170dc6 AH |
6523 | tree_cons (NULL_TREE, integer_type_node, |
6524 | endlink))); | |
6525 | ||
6526 | tree v2si_ftype_puint_int | |
3fdaa45a | 6527 | = build_function_type (opaque_V2SI_type_node, |
a3170dc6 AH |
6528 | tree_cons (NULL_TREE, puint_type_node, |
6529 | tree_cons (NULL_TREE, integer_type_node, | |
6530 | endlink))); | |
6531 | ||
6532 | tree v2si_ftype_pushort_int | |
3fdaa45a | 6533 | = build_function_type (opaque_V2SI_type_node, |
a3170dc6 AH |
6534 | tree_cons (NULL_TREE, pushort_type_node, |
6535 | tree_cons (NULL_TREE, integer_type_node, | |
6536 | endlink))); | |
6537 | ||
00332c9f AH |
6538 | tree v2si_ftype_signed_char |
6539 | = build_function_type (opaque_V2SI_type_node, | |
6540 | tree_cons (NULL_TREE, signed_char_type_node, | |
6541 | endlink)); | |
6542 | ||
a3170dc6 AH |
6543 | /* The initialization of the simple binary and unary builtins is |
6544 | done in rs6000_common_init_builtins, but we have to enable the | |
6545 | mask bits here manually because we have run out of `target_flags' | |
6546 | bits. We really need to redesign this mask business. */ | |
6547 | ||
6548 | enable_mask_for_builtins ((struct builtin_description *) bdesc_2arg, | |
6549 | ARRAY_SIZE (bdesc_2arg), | |
6550 | SPE_BUILTIN_EVADDW, | |
6551 | SPE_BUILTIN_EVXOR); | |
6552 | enable_mask_for_builtins ((struct builtin_description *) bdesc_1arg, | |
6553 | ARRAY_SIZE (bdesc_1arg), | |
6554 | SPE_BUILTIN_EVABS, | |
6555 | SPE_BUILTIN_EVSUBFUSIAAW); | |
6556 | enable_mask_for_builtins ((struct builtin_description *) bdesc_spe_predicates, | |
6557 | ARRAY_SIZE (bdesc_spe_predicates), | |
6558 | SPE_BUILTIN_EVCMPEQ, | |
6559 | SPE_BUILTIN_EVFSTSTLT); | |
6560 | enable_mask_for_builtins ((struct builtin_description *) bdesc_spe_evsel, | |
6561 | ARRAY_SIZE (bdesc_spe_evsel), | |
6562 | SPE_BUILTIN_EVSEL_CMPGTS, | |
6563 | SPE_BUILTIN_EVSEL_FSTSTEQ); | |
6564 | ||
36252949 AH |
6565 | (*lang_hooks.decls.pushdecl) |
6566 | (build_decl (TYPE_DECL, get_identifier ("__ev64_opaque__"), | |
6567 | opaque_V2SI_type_node)); | |
6568 | ||
a3170dc6 AH |
6569 | /* Initialize irregular SPE builtins. */ |
6570 | ||
6571 | def_builtin (target_flags, "__builtin_spe_mtspefscr", void_ftype_int, SPE_BUILTIN_MTSPEFSCR); | |
6572 | def_builtin (target_flags, "__builtin_spe_mfspefscr", int_ftype_void, SPE_BUILTIN_MFSPEFSCR); | |
6573 | def_builtin (target_flags, "__builtin_spe_evstddx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDDX); | |
6574 | def_builtin (target_flags, "__builtin_spe_evstdhx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDHX); | |
6575 | def_builtin (target_flags, "__builtin_spe_evstdwx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDWX); | |
6576 | def_builtin (target_flags, "__builtin_spe_evstwhex", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWHEX); | |
6577 | def_builtin (target_flags, "__builtin_spe_evstwhox", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWHOX); | |
6578 | def_builtin (target_flags, "__builtin_spe_evstwwex", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWWEX); | |
6579 | def_builtin (target_flags, "__builtin_spe_evstwwox", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWWOX); | |
6580 | def_builtin (target_flags, "__builtin_spe_evstdd", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDD); | |
6581 | def_builtin (target_flags, "__builtin_spe_evstdh", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDH); | |
6582 | def_builtin (target_flags, "__builtin_spe_evstdw", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDW); | |
6583 | def_builtin (target_flags, "__builtin_spe_evstwhe", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWHE); | |
6584 | def_builtin (target_flags, "__builtin_spe_evstwho", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWHO); | |
6585 | def_builtin (target_flags, "__builtin_spe_evstwwe", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWWE); | |
6586 | def_builtin (target_flags, "__builtin_spe_evstwwo", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWWO); | |
00332c9f AH |
6587 | def_builtin (target_flags, "__builtin_spe_evsplatfi", v2si_ftype_signed_char, SPE_BUILTIN_EVSPLATFI); |
6588 | def_builtin (target_flags, "__builtin_spe_evsplati", v2si_ftype_signed_char, SPE_BUILTIN_EVSPLATI); | |
a3170dc6 AH |
6589 | |
6590 | /* Loads. */ | |
6591 | def_builtin (target_flags, "__builtin_spe_evlddx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDDX); | |
6592 | def_builtin (target_flags, "__builtin_spe_evldwx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDWX); | |
6593 | def_builtin (target_flags, "__builtin_spe_evldhx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDHX); | |
6594 | def_builtin (target_flags, "__builtin_spe_evlwhex", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHEX); | |
6595 | def_builtin (target_flags, "__builtin_spe_evlwhoux", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOUX); | |
6596 | def_builtin (target_flags, "__builtin_spe_evlwhosx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOSX); | |
6597 | def_builtin (target_flags, "__builtin_spe_evlwwsplatx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWWSPLATX); | |
6598 | def_builtin (target_flags, "__builtin_spe_evlwhsplatx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHSPLATX); | |
6599 | def_builtin (target_flags, "__builtin_spe_evlhhesplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHESPLATX); | |
6600 | def_builtin (target_flags, "__builtin_spe_evlhhousplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOUSPLATX); | |
6601 | def_builtin (target_flags, "__builtin_spe_evlhhossplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOSSPLATX); | |
6602 | def_builtin (target_flags, "__builtin_spe_evldd", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDD); | |
6603 | def_builtin (target_flags, "__builtin_spe_evldw", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDW); | |
6604 | def_builtin (target_flags, "__builtin_spe_evldh", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDH); | |
6605 | def_builtin (target_flags, "__builtin_spe_evlhhesplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHESPLAT); | |
6606 | def_builtin (target_flags, "__builtin_spe_evlhhossplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOSSPLAT); | |
6607 | def_builtin (target_flags, "__builtin_spe_evlhhousplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOUSPLAT); | |
6608 | def_builtin (target_flags, "__builtin_spe_evlwhe", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHE); | |
6609 | def_builtin (target_flags, "__builtin_spe_evlwhos", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOS); | |
6610 | def_builtin (target_flags, "__builtin_spe_evlwhou", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOU); | |
6611 | def_builtin (target_flags, "__builtin_spe_evlwhsplat", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHSPLAT); | |
6612 | def_builtin (target_flags, "__builtin_spe_evlwwsplat", v2si_ftype_puint_int, SPE_BUILTIN_EVLWWSPLAT); | |
6613 | ||
6614 | /* Predicates. */ | |
6615 | d = (struct builtin_description *) bdesc_spe_predicates; | |
6616 | for (i = 0; i < ARRAY_SIZE (bdesc_spe_predicates); ++i, d++) | |
6617 | { | |
6618 | tree type; | |
6619 | ||
6620 | switch (insn_data[d->icode].operand[1].mode) | |
6621 | { | |
6622 | case V2SImode: | |
6623 | type = int_ftype_int_v2si_v2si; | |
6624 | break; | |
6625 | case V2SFmode: | |
6626 | type = int_ftype_int_v2sf_v2sf; | |
6627 | break; | |
6628 | default: | |
6629 | abort (); | |
6630 | } | |
6631 | ||
6632 | def_builtin (d->mask, d->name, type, d->code); | |
6633 | } | |
6634 | ||
6635 | /* Evsel predicates. */ | |
6636 | d = (struct builtin_description *) bdesc_spe_evsel; | |
6637 | for (i = 0; i < ARRAY_SIZE (bdesc_spe_evsel); ++i, d++) | |
6638 | { | |
6639 | tree type; | |
6640 | ||
6641 | switch (insn_data[d->icode].operand[1].mode) | |
6642 | { | |
6643 | case V2SImode: | |
6644 | type = v2si_ftype_4_v2si; | |
6645 | break; | |
6646 | case V2SFmode: | |
6647 | type = v2sf_ftype_4_v2sf; | |
6648 | break; | |
6649 | default: | |
6650 | abort (); | |
6651 | } | |
6652 | ||
6653 | def_builtin (d->mask, d->name, type, d->code); | |
6654 | } | |
6655 | } | |
6656 | ||
6657 | static void | |
863d938c | 6658 | altivec_init_builtins (void) |
a3170dc6 AH |
6659 | { |
6660 | struct builtin_description *d; | |
6661 | struct builtin_description_predicates *dp; | |
6662 | size_t i; | |
6663 | tree pfloat_type_node = build_pointer_type (float_type_node); | |
6664 | tree pint_type_node = build_pointer_type (integer_type_node); | |
6665 | tree pshort_type_node = build_pointer_type (short_integer_type_node); | |
6666 | tree pchar_type_node = build_pointer_type (char_type_node); | |
6667 | ||
6668 | tree pvoid_type_node = build_pointer_type (void_type_node); | |
6669 | ||
0dbc3651 ZW |
6670 | tree pcfloat_type_node = build_pointer_type (build_qualified_type (float_type_node, TYPE_QUAL_CONST)); |
6671 | tree pcint_type_node = build_pointer_type (build_qualified_type (integer_type_node, TYPE_QUAL_CONST)); | |
6672 | tree pcshort_type_node = build_pointer_type (build_qualified_type (short_integer_type_node, TYPE_QUAL_CONST)); | |
6673 | tree pcchar_type_node = build_pointer_type (build_qualified_type (char_type_node, TYPE_QUAL_CONST)); | |
6674 | ||
6675 | tree pcvoid_type_node = build_pointer_type (build_qualified_type (void_type_node, TYPE_QUAL_CONST)); | |
6676 | ||
a3170dc6 AH |
6677 | tree int_ftype_int_v4si_v4si |
6678 | = build_function_type_list (integer_type_node, | |
6679 | integer_type_node, V4SI_type_node, | |
6680 | V4SI_type_node, NULL_TREE); | |
0dbc3651 ZW |
6681 | tree v4sf_ftype_pcfloat |
6682 | = build_function_type_list (V4SF_type_node, pcfloat_type_node, NULL_TREE); | |
a3170dc6 | 6683 | tree void_ftype_pfloat_v4sf |
b4de2f7d | 6684 | = build_function_type_list (void_type_node, |
a3170dc6 | 6685 | pfloat_type_node, V4SF_type_node, NULL_TREE); |
0dbc3651 ZW |
6686 | tree v4si_ftype_pcint |
6687 | = build_function_type_list (V4SI_type_node, pcint_type_node, NULL_TREE); | |
6688 | tree void_ftype_pint_v4si | |
b4de2f7d AH |
6689 | = build_function_type_list (void_type_node, |
6690 | pint_type_node, V4SI_type_node, NULL_TREE); | |
0dbc3651 ZW |
6691 | tree v8hi_ftype_pcshort |
6692 | = build_function_type_list (V8HI_type_node, pcshort_type_node, NULL_TREE); | |
f18c054f | 6693 | tree void_ftype_pshort_v8hi |
b4de2f7d AH |
6694 | = build_function_type_list (void_type_node, |
6695 | pshort_type_node, V8HI_type_node, NULL_TREE); | |
0dbc3651 ZW |
6696 | tree v16qi_ftype_pcchar |
6697 | = build_function_type_list (V16QI_type_node, pcchar_type_node, NULL_TREE); | |
f18c054f | 6698 | tree void_ftype_pchar_v16qi |
b4de2f7d AH |
6699 | = build_function_type_list (void_type_node, |
6700 | pchar_type_node, V16QI_type_node, NULL_TREE); | |
95385cbb | 6701 | tree void_ftype_v4si |
b4de2f7d | 6702 | = build_function_type_list (void_type_node, V4SI_type_node, NULL_TREE); |
a3170dc6 AH |
6703 | tree v8hi_ftype_void |
6704 | = build_function_type (V8HI_type_node, void_list_node); | |
6705 | tree void_ftype_void | |
6706 | = build_function_type (void_type_node, void_list_node); | |
6707 | tree void_ftype_qi | |
6708 | = build_function_type_list (void_type_node, char_type_node, NULL_TREE); | |
0dbc3651 | 6709 | |
b4a62fa0 | 6710 | tree v16qi_ftype_long_pcvoid |
a3170dc6 | 6711 | = build_function_type_list (V16QI_type_node, |
b4a62fa0 SB |
6712 | long_integer_type_node, pcvoid_type_node, NULL_TREE); |
6713 | tree v8hi_ftype_long_pcvoid | |
a3170dc6 | 6714 | = build_function_type_list (V8HI_type_node, |
b4a62fa0 SB |
6715 | long_integer_type_node, pcvoid_type_node, NULL_TREE); |
6716 | tree v4si_ftype_long_pcvoid | |
a3170dc6 | 6717 | = build_function_type_list (V4SI_type_node, |
b4a62fa0 | 6718 | long_integer_type_node, pcvoid_type_node, NULL_TREE); |
0dbc3651 | 6719 | |
b4a62fa0 | 6720 | tree void_ftype_v4si_long_pvoid |
b4de2f7d | 6721 | = build_function_type_list (void_type_node, |
b4a62fa0 | 6722 | V4SI_type_node, long_integer_type_node, |
b4de2f7d | 6723 | pvoid_type_node, NULL_TREE); |
b4a62fa0 | 6724 | tree void_ftype_v16qi_long_pvoid |
b4de2f7d | 6725 | = build_function_type_list (void_type_node, |
b4a62fa0 | 6726 | V16QI_type_node, long_integer_type_node, |
b4de2f7d | 6727 | pvoid_type_node, NULL_TREE); |
b4a62fa0 | 6728 | tree void_ftype_v8hi_long_pvoid |
b4de2f7d | 6729 | = build_function_type_list (void_type_node, |
b4a62fa0 | 6730 | V8HI_type_node, long_integer_type_node, |
b4de2f7d | 6731 | pvoid_type_node, NULL_TREE); |
a3170dc6 AH |
6732 | tree int_ftype_int_v8hi_v8hi |
6733 | = build_function_type_list (integer_type_node, | |
6734 | integer_type_node, V8HI_type_node, | |
6735 | V8HI_type_node, NULL_TREE); | |
6736 | tree int_ftype_int_v16qi_v16qi | |
6737 | = build_function_type_list (integer_type_node, | |
6738 | integer_type_node, V16QI_type_node, | |
6739 | V16QI_type_node, NULL_TREE); | |
6740 | tree int_ftype_int_v4sf_v4sf | |
6741 | = build_function_type_list (integer_type_node, | |
6742 | integer_type_node, V4SF_type_node, | |
6743 | V4SF_type_node, NULL_TREE); | |
6744 | tree v4si_ftype_v4si | |
6745 | = build_function_type_list (V4SI_type_node, V4SI_type_node, NULL_TREE); | |
6746 | tree v8hi_ftype_v8hi | |
6747 | = build_function_type_list (V8HI_type_node, V8HI_type_node, NULL_TREE); | |
6748 | tree v16qi_ftype_v16qi | |
6749 | = build_function_type_list (V16QI_type_node, V16QI_type_node, NULL_TREE); | |
6750 | tree v4sf_ftype_v4sf | |
6751 | = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE); | |
0dbc3651 | 6752 | tree void_ftype_pcvoid_int_char |
a3170dc6 | 6753 | = build_function_type_list (void_type_node, |
0dbc3651 | 6754 | pcvoid_type_node, integer_type_node, |
a3170dc6 | 6755 | char_type_node, NULL_TREE); |
0dbc3651 ZW |
6756 | |
6757 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_4sf", v4sf_ftype_pcfloat, | |
6758 | ALTIVEC_BUILTIN_LD_INTERNAL_4sf); | |
6759 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_4sf", void_ftype_pfloat_v4sf, | |
6760 | ALTIVEC_BUILTIN_ST_INTERNAL_4sf); | |
6761 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_4si", v4si_ftype_pcint, | |
6762 | ALTIVEC_BUILTIN_LD_INTERNAL_4si); | |
6763 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_4si", void_ftype_pint_v4si, | |
6764 | ALTIVEC_BUILTIN_ST_INTERNAL_4si); | |
6765 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_8hi", v8hi_ftype_pcshort, | |
6766 | ALTIVEC_BUILTIN_LD_INTERNAL_8hi); | |
6767 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_8hi", void_ftype_pshort_v8hi, | |
6768 | ALTIVEC_BUILTIN_ST_INTERNAL_8hi); | |
6769 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_16qi", v16qi_ftype_pcchar, | |
6770 | ALTIVEC_BUILTIN_LD_INTERNAL_16qi); | |
6771 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_16qi", void_ftype_pchar_v16qi, | |
6772 | ALTIVEC_BUILTIN_ST_INTERNAL_16qi); | |
a3170dc6 AH |
6773 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_mtvscr", void_ftype_v4si, ALTIVEC_BUILTIN_MTVSCR); |
6774 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_mfvscr", v8hi_ftype_void, ALTIVEC_BUILTIN_MFVSCR); | |
6775 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_dssall", void_ftype_void, ALTIVEC_BUILTIN_DSSALL); | |
6776 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_dss", void_ftype_qi, ALTIVEC_BUILTIN_DSS); | |
b4a62fa0 SB |
6777 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvsl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSL); |
6778 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvsr", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSR); | |
6779 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvebx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEBX); | |
6780 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvehx", v8hi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEHX); | |
6781 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvewx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEWX); | |
6782 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvxl", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVXL); | |
6783 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVX); | |
6784 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVX); | |
6785 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvewx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVEWX); | |
6786 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvxl", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVXL); | |
6787 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvebx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVEBX); | |
6788 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvehx", void_ftype_v8hi_long_pvoid, ALTIVEC_BUILTIN_STVEHX); | |
a3170dc6 AH |
6789 | |
6790 | /* Add the DST variants. */ | |
6791 | d = (struct builtin_description *) bdesc_dst; | |
6792 | for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++) | |
0dbc3651 | 6793 | def_builtin (d->mask, d->name, void_ftype_pcvoid_int_char, d->code); |
a3170dc6 AH |
6794 | |
6795 | /* Initialize the predicates. */ | |
6796 | dp = (struct builtin_description_predicates *) bdesc_altivec_preds; | |
6797 | for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, dp++) | |
6798 | { | |
6799 | enum machine_mode mode1; | |
6800 | tree type; | |
6801 | ||
6802 | mode1 = insn_data[dp->icode].operand[1].mode; | |
6803 | ||
6804 | switch (mode1) | |
6805 | { | |
6806 | case V4SImode: | |
6807 | type = int_ftype_int_v4si_v4si; | |
6808 | break; | |
6809 | case V8HImode: | |
6810 | type = int_ftype_int_v8hi_v8hi; | |
6811 | break; | |
6812 | case V16QImode: | |
6813 | type = int_ftype_int_v16qi_v16qi; | |
6814 | break; | |
6815 | case V4SFmode: | |
6816 | type = int_ftype_int_v4sf_v4sf; | |
6817 | break; | |
6818 | default: | |
6819 | abort (); | |
6820 | } | |
6821 | ||
6822 | def_builtin (dp->mask, dp->name, type, dp->code); | |
6823 | } | |
6824 | ||
6825 | /* Initialize the abs* operators. */ | |
6826 | d = (struct builtin_description *) bdesc_abs; | |
6827 | for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++) | |
6828 | { | |
6829 | enum machine_mode mode0; | |
6830 | tree type; | |
6831 | ||
6832 | mode0 = insn_data[d->icode].operand[0].mode; | |
6833 | ||
6834 | switch (mode0) | |
6835 | { | |
6836 | case V4SImode: | |
6837 | type = v4si_ftype_v4si; | |
6838 | break; | |
6839 | case V8HImode: | |
6840 | type = v8hi_ftype_v8hi; | |
6841 | break; | |
6842 | case V16QImode: | |
6843 | type = v16qi_ftype_v16qi; | |
6844 | break; | |
6845 | case V4SFmode: | |
6846 | type = v4sf_ftype_v4sf; | |
6847 | break; | |
6848 | default: | |
6849 | abort (); | |
6850 | } | |
6851 | ||
6852 | def_builtin (d->mask, d->name, type, d->code); | |
6853 | } | |
6854 | } | |
6855 | ||
6856 | static void | |
863d938c | 6857 | rs6000_common_init_builtins (void) |
a3170dc6 AH |
6858 | { |
6859 | struct builtin_description *d; | |
6860 | size_t i; | |
6861 | ||
6862 | tree v4sf_ftype_v4sf_v4sf_v16qi | |
6863 | = build_function_type_list (V4SF_type_node, | |
6864 | V4SF_type_node, V4SF_type_node, | |
6865 | V16QI_type_node, NULL_TREE); | |
6866 | tree v4si_ftype_v4si_v4si_v16qi | |
6867 | = build_function_type_list (V4SI_type_node, | |
6868 | V4SI_type_node, V4SI_type_node, | |
6869 | V16QI_type_node, NULL_TREE); | |
6870 | tree v8hi_ftype_v8hi_v8hi_v16qi | |
6871 | = build_function_type_list (V8HI_type_node, | |
6872 | V8HI_type_node, V8HI_type_node, | |
6873 | V16QI_type_node, NULL_TREE); | |
6874 | tree v16qi_ftype_v16qi_v16qi_v16qi | |
6875 | = build_function_type_list (V16QI_type_node, | |
6876 | V16QI_type_node, V16QI_type_node, | |
6877 | V16QI_type_node, NULL_TREE); | |
6878 | tree v4si_ftype_char | |
6879 | = build_function_type_list (V4SI_type_node, char_type_node, NULL_TREE); | |
6880 | tree v8hi_ftype_char | |
6881 | = build_function_type_list (V8HI_type_node, char_type_node, NULL_TREE); | |
6882 | tree v16qi_ftype_char | |
6883 | = build_function_type_list (V16QI_type_node, char_type_node, NULL_TREE); | |
6884 | tree v8hi_ftype_v16qi | |
6885 | = build_function_type_list (V8HI_type_node, V16QI_type_node, NULL_TREE); | |
6886 | tree v4sf_ftype_v4sf | |
6887 | = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE); | |
6888 | ||
6889 | tree v2si_ftype_v2si_v2si | |
2abe3e28 AH |
6890 | = build_function_type_list (opaque_V2SI_type_node, |
6891 | opaque_V2SI_type_node, | |
6892 | opaque_V2SI_type_node, NULL_TREE); | |
a3170dc6 AH |
6893 | |
6894 | tree v2sf_ftype_v2sf_v2sf | |
2abe3e28 AH |
6895 | = build_function_type_list (opaque_V2SF_type_node, |
6896 | opaque_V2SF_type_node, | |
6897 | opaque_V2SF_type_node, NULL_TREE); | |
a3170dc6 AH |
6898 | |
6899 | tree v2si_ftype_int_int | |
2abe3e28 | 6900 | = build_function_type_list (opaque_V2SI_type_node, |
a3170dc6 AH |
6901 | integer_type_node, integer_type_node, |
6902 | NULL_TREE); | |
6903 | ||
6904 | tree v2si_ftype_v2si | |
2abe3e28 AH |
6905 | = build_function_type_list (opaque_V2SI_type_node, |
6906 | opaque_V2SI_type_node, NULL_TREE); | |
a3170dc6 AH |
6907 | |
6908 | tree v2sf_ftype_v2sf | |
2abe3e28 AH |
6909 | = build_function_type_list (opaque_V2SF_type_node, |
6910 | opaque_V2SF_type_node, NULL_TREE); | |
a3170dc6 AH |
6911 | |
6912 | tree v2sf_ftype_v2si | |
2abe3e28 AH |
6913 | = build_function_type_list (opaque_V2SF_type_node, |
6914 | opaque_V2SI_type_node, NULL_TREE); | |
a3170dc6 AH |
6915 | |
6916 | tree v2si_ftype_v2sf | |
2abe3e28 AH |
6917 | = build_function_type_list (opaque_V2SI_type_node, |
6918 | opaque_V2SF_type_node, NULL_TREE); | |
a3170dc6 AH |
6919 | |
6920 | tree v2si_ftype_v2si_char | |
2abe3e28 AH |
6921 | = build_function_type_list (opaque_V2SI_type_node, |
6922 | opaque_V2SI_type_node, | |
6923 | char_type_node, NULL_TREE); | |
a3170dc6 AH |
6924 | |
6925 | tree v2si_ftype_int_char | |
2abe3e28 | 6926 | = build_function_type_list (opaque_V2SI_type_node, |
a3170dc6 AH |
6927 | integer_type_node, char_type_node, NULL_TREE); |
6928 | ||
6929 | tree v2si_ftype_char | |
2abe3e28 AH |
6930 | = build_function_type_list (opaque_V2SI_type_node, |
6931 | char_type_node, NULL_TREE); | |
a3170dc6 AH |
6932 | |
6933 | tree int_ftype_int_int | |
6934 | = build_function_type_list (integer_type_node, | |
6935 | integer_type_node, integer_type_node, | |
6936 | NULL_TREE); | |
95385cbb | 6937 | |
0ac081f6 | 6938 | tree v4si_ftype_v4si_v4si |
b4de2f7d AH |
6939 | = build_function_type_list (V4SI_type_node, |
6940 | V4SI_type_node, V4SI_type_node, NULL_TREE); | |
617e0e1d | 6941 | tree v4sf_ftype_v4si_char |
b4de2f7d AH |
6942 | = build_function_type_list (V4SF_type_node, |
6943 | V4SI_type_node, char_type_node, NULL_TREE); | |
617e0e1d | 6944 | tree v4si_ftype_v4sf_char |
b4de2f7d AH |
6945 | = build_function_type_list (V4SI_type_node, |
6946 | V4SF_type_node, char_type_node, NULL_TREE); | |
2212663f | 6947 | tree v4si_ftype_v4si_char |
b4de2f7d AH |
6948 | = build_function_type_list (V4SI_type_node, |
6949 | V4SI_type_node, char_type_node, NULL_TREE); | |
2212663f | 6950 | tree v8hi_ftype_v8hi_char |
b4de2f7d AH |
6951 | = build_function_type_list (V8HI_type_node, |
6952 | V8HI_type_node, char_type_node, NULL_TREE); | |
2212663f | 6953 | tree v16qi_ftype_v16qi_char |
b4de2f7d AH |
6954 | = build_function_type_list (V16QI_type_node, |
6955 | V16QI_type_node, char_type_node, NULL_TREE); | |
24408032 | 6956 | tree v16qi_ftype_v16qi_v16qi_char |
b4de2f7d AH |
6957 | = build_function_type_list (V16QI_type_node, |
6958 | V16QI_type_node, V16QI_type_node, | |
6959 | char_type_node, NULL_TREE); | |
24408032 | 6960 | tree v8hi_ftype_v8hi_v8hi_char |
b4de2f7d AH |
6961 | = build_function_type_list (V8HI_type_node, |
6962 | V8HI_type_node, V8HI_type_node, | |
6963 | char_type_node, NULL_TREE); | |
24408032 | 6964 | tree v4si_ftype_v4si_v4si_char |
b4de2f7d AH |
6965 | = build_function_type_list (V4SI_type_node, |
6966 | V4SI_type_node, V4SI_type_node, | |
6967 | char_type_node, NULL_TREE); | |
24408032 | 6968 | tree v4sf_ftype_v4sf_v4sf_char |
b4de2f7d AH |
6969 | = build_function_type_list (V4SF_type_node, |
6970 | V4SF_type_node, V4SF_type_node, | |
6971 | char_type_node, NULL_TREE); | |
0ac081f6 | 6972 | tree v4sf_ftype_v4sf_v4sf |
b4de2f7d AH |
6973 | = build_function_type_list (V4SF_type_node, |
6974 | V4SF_type_node, V4SF_type_node, NULL_TREE); | |
617e0e1d | 6975 | tree v4sf_ftype_v4sf_v4sf_v4si |
b4de2f7d AH |
6976 | = build_function_type_list (V4SF_type_node, |
6977 | V4SF_type_node, V4SF_type_node, | |
6978 | V4SI_type_node, NULL_TREE); | |
2212663f | 6979 | tree v4sf_ftype_v4sf_v4sf_v4sf |
b4de2f7d AH |
6980 | = build_function_type_list (V4SF_type_node, |
6981 | V4SF_type_node, V4SF_type_node, | |
6982 | V4SF_type_node, NULL_TREE); | |
617e0e1d | 6983 | tree v4si_ftype_v4si_v4si_v4si |
b4de2f7d AH |
6984 | = build_function_type_list (V4SI_type_node, |
6985 | V4SI_type_node, V4SI_type_node, | |
6986 | V4SI_type_node, NULL_TREE); | |
0ac081f6 | 6987 | tree v8hi_ftype_v8hi_v8hi |
b4de2f7d AH |
6988 | = build_function_type_list (V8HI_type_node, |
6989 | V8HI_type_node, V8HI_type_node, NULL_TREE); | |
2212663f | 6990 | tree v8hi_ftype_v8hi_v8hi_v8hi |
b4de2f7d AH |
6991 | = build_function_type_list (V8HI_type_node, |
6992 | V8HI_type_node, V8HI_type_node, | |
6993 | V8HI_type_node, NULL_TREE); | |
2212663f | 6994 | tree v4si_ftype_v8hi_v8hi_v4si |
b4de2f7d AH |
6995 | = build_function_type_list (V4SI_type_node, |
6996 | V8HI_type_node, V8HI_type_node, | |
6997 | V4SI_type_node, NULL_TREE); | |
2212663f | 6998 | tree v4si_ftype_v16qi_v16qi_v4si |
b4de2f7d AH |
6999 | = build_function_type_list (V4SI_type_node, |
7000 | V16QI_type_node, V16QI_type_node, | |
7001 | V4SI_type_node, NULL_TREE); | |
0ac081f6 | 7002 | tree v16qi_ftype_v16qi_v16qi |
b4de2f7d AH |
7003 | = build_function_type_list (V16QI_type_node, |
7004 | V16QI_type_node, V16QI_type_node, NULL_TREE); | |
0ac081f6 | 7005 | tree v4si_ftype_v4sf_v4sf |
b4de2f7d AH |
7006 | = build_function_type_list (V4SI_type_node, |
7007 | V4SF_type_node, V4SF_type_node, NULL_TREE); | |
0ac081f6 | 7008 | tree v8hi_ftype_v16qi_v16qi |
b4de2f7d AH |
7009 | = build_function_type_list (V8HI_type_node, |
7010 | V16QI_type_node, V16QI_type_node, NULL_TREE); | |
0ac081f6 | 7011 | tree v4si_ftype_v8hi_v8hi |
b4de2f7d AH |
7012 | = build_function_type_list (V4SI_type_node, |
7013 | V8HI_type_node, V8HI_type_node, NULL_TREE); | |
0ac081f6 | 7014 | tree v8hi_ftype_v4si_v4si |
b4de2f7d AH |
7015 | = build_function_type_list (V8HI_type_node, |
7016 | V4SI_type_node, V4SI_type_node, NULL_TREE); | |
0ac081f6 | 7017 | tree v16qi_ftype_v8hi_v8hi |
b4de2f7d AH |
7018 | = build_function_type_list (V16QI_type_node, |
7019 | V8HI_type_node, V8HI_type_node, NULL_TREE); | |
0ac081f6 | 7020 | tree v4si_ftype_v16qi_v4si |
b4de2f7d AH |
7021 | = build_function_type_list (V4SI_type_node, |
7022 | V16QI_type_node, V4SI_type_node, NULL_TREE); | |
fa066a23 | 7023 | tree v4si_ftype_v16qi_v16qi |
b4de2f7d AH |
7024 | = build_function_type_list (V4SI_type_node, |
7025 | V16QI_type_node, V16QI_type_node, NULL_TREE); | |
0ac081f6 | 7026 | tree v4si_ftype_v8hi_v4si |
b4de2f7d AH |
7027 | = build_function_type_list (V4SI_type_node, |
7028 | V8HI_type_node, V4SI_type_node, NULL_TREE); | |
a3170dc6 AH |
7029 | tree v4si_ftype_v8hi |
7030 | = build_function_type_list (V4SI_type_node, V8HI_type_node, NULL_TREE); | |
7031 | tree int_ftype_v4si_v4si | |
7032 | = build_function_type_list (integer_type_node, | |
7033 | V4SI_type_node, V4SI_type_node, NULL_TREE); | |
7034 | tree int_ftype_v4sf_v4sf | |
7035 | = build_function_type_list (integer_type_node, | |
7036 | V4SF_type_node, V4SF_type_node, NULL_TREE); | |
7037 | tree int_ftype_v16qi_v16qi | |
7038 | = build_function_type_list (integer_type_node, | |
7039 | V16QI_type_node, V16QI_type_node, NULL_TREE); | |
0ac081f6 | 7040 | tree int_ftype_v8hi_v8hi |
b4de2f7d AH |
7041 | = build_function_type_list (integer_type_node, |
7042 | V8HI_type_node, V8HI_type_node, NULL_TREE); | |
0ac081f6 | 7043 | |
6f317ef3 | 7044 | /* Add the simple ternary operators. */ |
2212663f | 7045 | d = (struct builtin_description *) bdesc_3arg; |
ca7558fc | 7046 | for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++) |
2212663f DB |
7047 | { |
7048 | ||
7049 | enum machine_mode mode0, mode1, mode2, mode3; | |
7050 | tree type; | |
7051 | ||
0559cc77 | 7052 | if (d->name == 0 || d->icode == CODE_FOR_nothing) |
2212663f DB |
7053 | continue; |
7054 | ||
7055 | mode0 = insn_data[d->icode].operand[0].mode; | |
7056 | mode1 = insn_data[d->icode].operand[1].mode; | |
7057 | mode2 = insn_data[d->icode].operand[2].mode; | |
7058 | mode3 = insn_data[d->icode].operand[3].mode; | |
7059 | ||
7060 | /* When all four are of the same mode. */ | |
7061 | if (mode0 == mode1 && mode1 == mode2 && mode2 == mode3) | |
7062 | { | |
7063 | switch (mode0) | |
7064 | { | |
617e0e1d DB |
7065 | case V4SImode: |
7066 | type = v4si_ftype_v4si_v4si_v4si; | |
7067 | break; | |
2212663f DB |
7068 | case V4SFmode: |
7069 | type = v4sf_ftype_v4sf_v4sf_v4sf; | |
7070 | break; | |
7071 | case V8HImode: | |
7072 | type = v8hi_ftype_v8hi_v8hi_v8hi; | |
7073 | break; | |
7074 | case V16QImode: | |
7075 | type = v16qi_ftype_v16qi_v16qi_v16qi; | |
7076 | break; | |
7077 | default: | |
7078 | abort(); | |
7079 | } | |
7080 | } | |
7081 | else if (mode0 == mode1 && mode1 == mode2 && mode3 == V16QImode) | |
7082 | { | |
7083 | switch (mode0) | |
7084 | { | |
7085 | case V4SImode: | |
7086 | type = v4si_ftype_v4si_v4si_v16qi; | |
7087 | break; | |
7088 | case V4SFmode: | |
7089 | type = v4sf_ftype_v4sf_v4sf_v16qi; | |
7090 | break; | |
7091 | case V8HImode: | |
7092 | type = v8hi_ftype_v8hi_v8hi_v16qi; | |
7093 | break; | |
7094 | case V16QImode: | |
7095 | type = v16qi_ftype_v16qi_v16qi_v16qi; | |
7096 | break; | |
7097 | default: | |
7098 | abort(); | |
7099 | } | |
7100 | } | |
7101 | else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V16QImode | |
7102 | && mode3 == V4SImode) | |
24408032 | 7103 | type = v4si_ftype_v16qi_v16qi_v4si; |
2212663f DB |
7104 | else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V8HImode |
7105 | && mode3 == V4SImode) | |
24408032 | 7106 | type = v4si_ftype_v8hi_v8hi_v4si; |
617e0e1d DB |
7107 | else if (mode0 == V4SFmode && mode1 == V4SFmode && mode2 == V4SFmode |
7108 | && mode3 == V4SImode) | |
24408032 AH |
7109 | type = v4sf_ftype_v4sf_v4sf_v4si; |
7110 | ||
7111 | /* vchar, vchar, vchar, 4 bit literal. */ | |
7112 | else if (mode0 == V16QImode && mode1 == mode0 && mode2 == mode0 | |
7113 | && mode3 == QImode) | |
7114 | type = v16qi_ftype_v16qi_v16qi_char; | |
7115 | ||
7116 | /* vshort, vshort, vshort, 4 bit literal. */ | |
7117 | else if (mode0 == V8HImode && mode1 == mode0 && mode2 == mode0 | |
7118 | && mode3 == QImode) | |
7119 | type = v8hi_ftype_v8hi_v8hi_char; | |
7120 | ||
7121 | /* vint, vint, vint, 4 bit literal. */ | |
7122 | else if (mode0 == V4SImode && mode1 == mode0 && mode2 == mode0 | |
7123 | && mode3 == QImode) | |
7124 | type = v4si_ftype_v4si_v4si_char; | |
7125 | ||
7126 | /* vfloat, vfloat, vfloat, 4 bit literal. */ | |
7127 | else if (mode0 == V4SFmode && mode1 == mode0 && mode2 == mode0 | |
7128 | && mode3 == QImode) | |
7129 | type = v4sf_ftype_v4sf_v4sf_char; | |
7130 | ||
2212663f DB |
7131 | else |
7132 | abort (); | |
7133 | ||
7134 | def_builtin (d->mask, d->name, type, d->code); | |
7135 | } | |
7136 | ||
0ac081f6 | 7137 | /* Add the simple binary operators. */ |
00b960c7 | 7138 | d = (struct builtin_description *) bdesc_2arg; |
ca7558fc | 7139 | for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++) |
0ac081f6 AH |
7140 | { |
7141 | enum machine_mode mode0, mode1, mode2; | |
7142 | tree type; | |
7143 | ||
0559cc77 | 7144 | if (d->name == 0 || d->icode == CODE_FOR_nothing) |
0ac081f6 AH |
7145 | continue; |
7146 | ||
7147 | mode0 = insn_data[d->icode].operand[0].mode; | |
7148 | mode1 = insn_data[d->icode].operand[1].mode; | |
7149 | mode2 = insn_data[d->icode].operand[2].mode; | |
7150 | ||
7151 | /* When all three operands are of the same mode. */ | |
7152 | if (mode0 == mode1 && mode1 == mode2) | |
7153 | { | |
7154 | switch (mode0) | |
7155 | { | |
7156 | case V4SFmode: | |
7157 | type = v4sf_ftype_v4sf_v4sf; | |
7158 | break; | |
7159 | case V4SImode: | |
7160 | type = v4si_ftype_v4si_v4si; | |
7161 | break; | |
7162 | case V16QImode: | |
7163 | type = v16qi_ftype_v16qi_v16qi; | |
7164 | break; | |
7165 | case V8HImode: | |
7166 | type = v8hi_ftype_v8hi_v8hi; | |
7167 | break; | |
a3170dc6 AH |
7168 | case V2SImode: |
7169 | type = v2si_ftype_v2si_v2si; | |
7170 | break; | |
7171 | case V2SFmode: | |
7172 | type = v2sf_ftype_v2sf_v2sf; | |
7173 | break; | |
7174 | case SImode: | |
7175 | type = int_ftype_int_int; | |
7176 | break; | |
0ac081f6 AH |
7177 | default: |
7178 | abort (); | |
7179 | } | |
7180 | } | |
7181 | ||
7182 | /* A few other combos we really don't want to do manually. */ | |
7183 | ||
7184 | /* vint, vfloat, vfloat. */ | |
7185 | else if (mode0 == V4SImode && mode1 == V4SFmode && mode2 == V4SFmode) | |
7186 | type = v4si_ftype_v4sf_v4sf; | |
7187 | ||
7188 | /* vshort, vchar, vchar. */ | |
7189 | else if (mode0 == V8HImode && mode1 == V16QImode && mode2 == V16QImode) | |
7190 | type = v8hi_ftype_v16qi_v16qi; | |
7191 | ||
7192 | /* vint, vshort, vshort. */ | |
7193 | else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V8HImode) | |
7194 | type = v4si_ftype_v8hi_v8hi; | |
7195 | ||
7196 | /* vshort, vint, vint. */ | |
7197 | else if (mode0 == V8HImode && mode1 == V4SImode && mode2 == V4SImode) | |
7198 | type = v8hi_ftype_v4si_v4si; | |
7199 | ||
7200 | /* vchar, vshort, vshort. */ | |
7201 | else if (mode0 == V16QImode && mode1 == V8HImode && mode2 == V8HImode) | |
7202 | type = v16qi_ftype_v8hi_v8hi; | |
7203 | ||
7204 | /* vint, vchar, vint. */ | |
7205 | else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V4SImode) | |
7206 | type = v4si_ftype_v16qi_v4si; | |
7207 | ||
fa066a23 AH |
7208 | /* vint, vchar, vchar. */ |
7209 | else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V16QImode) | |
7210 | type = v4si_ftype_v16qi_v16qi; | |
7211 | ||
0ac081f6 AH |
7212 | /* vint, vshort, vint. */ |
7213 | else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V4SImode) | |
7214 | type = v4si_ftype_v8hi_v4si; | |
2212663f DB |
7215 | |
7216 | /* vint, vint, 5 bit literal. */ | |
7217 | else if (mode0 == V4SImode && mode1 == V4SImode && mode2 == QImode) | |
7218 | type = v4si_ftype_v4si_char; | |
7219 | ||
7220 | /* vshort, vshort, 5 bit literal. */ | |
7221 | else if (mode0 == V8HImode && mode1 == V8HImode && mode2 == QImode) | |
7222 | type = v8hi_ftype_v8hi_char; | |
7223 | ||
7224 | /* vchar, vchar, 5 bit literal. */ | |
7225 | else if (mode0 == V16QImode && mode1 == V16QImode && mode2 == QImode) | |
7226 | type = v16qi_ftype_v16qi_char; | |
0ac081f6 | 7227 | |
617e0e1d DB |
7228 | /* vfloat, vint, 5 bit literal. */ |
7229 | else if (mode0 == V4SFmode && mode1 == V4SImode && mode2 == QImode) | |
7230 | type = v4sf_ftype_v4si_char; | |
7231 | ||
7232 | /* vint, vfloat, 5 bit literal. */ | |
7233 | else if (mode0 == V4SImode && mode1 == V4SFmode && mode2 == QImode) | |
7234 | type = v4si_ftype_v4sf_char; | |
7235 | ||
a3170dc6 AH |
7236 | else if (mode0 == V2SImode && mode1 == SImode && mode2 == SImode) |
7237 | type = v2si_ftype_int_int; | |
7238 | ||
7239 | else if (mode0 == V2SImode && mode1 == V2SImode && mode2 == QImode) | |
7240 | type = v2si_ftype_v2si_char; | |
7241 | ||
7242 | else if (mode0 == V2SImode && mode1 == SImode && mode2 == QImode) | |
7243 | type = v2si_ftype_int_char; | |
7244 | ||
0ac081f6 AH |
7245 | /* int, x, x. */ |
7246 | else if (mode0 == SImode) | |
7247 | { | |
7248 | switch (mode1) | |
7249 | { | |
7250 | case V4SImode: | |
7251 | type = int_ftype_v4si_v4si; | |
7252 | break; | |
7253 | case V4SFmode: | |
7254 | type = int_ftype_v4sf_v4sf; | |
7255 | break; | |
7256 | case V16QImode: | |
7257 | type = int_ftype_v16qi_v16qi; | |
7258 | break; | |
7259 | case V8HImode: | |
7260 | type = int_ftype_v8hi_v8hi; | |
7261 | break; | |
7262 | default: | |
7263 | abort (); | |
7264 | } | |
7265 | } | |
7266 | ||
7267 | else | |
7268 | abort (); | |
7269 | ||
2212663f DB |
7270 | def_builtin (d->mask, d->name, type, d->code); |
7271 | } | |
24408032 | 7272 | |
2212663f DB |
7273 | /* Add the simple unary operators. */ |
7274 | d = (struct builtin_description *) bdesc_1arg; | |
ca7558fc | 7275 | for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++) |
2212663f DB |
7276 | { |
7277 | enum machine_mode mode0, mode1; | |
7278 | tree type; | |
7279 | ||
0559cc77 | 7280 | if (d->name == 0 || d->icode == CODE_FOR_nothing) |
2212663f DB |
7281 | continue; |
7282 | ||
7283 | mode0 = insn_data[d->icode].operand[0].mode; | |
7284 | mode1 = insn_data[d->icode].operand[1].mode; | |
7285 | ||
7286 | if (mode0 == V4SImode && mode1 == QImode) | |
7287 | type = v4si_ftype_char; | |
7288 | else if (mode0 == V8HImode && mode1 == QImode) | |
7289 | type = v8hi_ftype_char; | |
7290 | else if (mode0 == V16QImode && mode1 == QImode) | |
7291 | type = v16qi_ftype_char; | |
617e0e1d DB |
7292 | else if (mode0 == V4SFmode && mode1 == V4SFmode) |
7293 | type = v4sf_ftype_v4sf; | |
20e26713 AH |
7294 | else if (mode0 == V8HImode && mode1 == V16QImode) |
7295 | type = v8hi_ftype_v16qi; | |
7296 | else if (mode0 == V4SImode && mode1 == V8HImode) | |
7297 | type = v4si_ftype_v8hi; | |
a3170dc6 AH |
7298 | else if (mode0 == V2SImode && mode1 == V2SImode) |
7299 | type = v2si_ftype_v2si; | |
7300 | else if (mode0 == V2SFmode && mode1 == V2SFmode) | |
7301 | type = v2sf_ftype_v2sf; | |
7302 | else if (mode0 == V2SFmode && mode1 == V2SImode) | |
7303 | type = v2sf_ftype_v2si; | |
7304 | else if (mode0 == V2SImode && mode1 == V2SFmode) | |
7305 | type = v2si_ftype_v2sf; | |
7306 | else if (mode0 == V2SImode && mode1 == QImode) | |
7307 | type = v2si_ftype_char; | |
2212663f DB |
7308 | else |
7309 | abort (); | |
7310 | ||
0ac081f6 AH |
7311 | def_builtin (d->mask, d->name, type, d->code); |
7312 | } | |
7313 | } | |
7314 | ||
c15c90bb ZW |
7315 | static void |
7316 | rs6000_init_libfuncs (void) | |
7317 | { | |
7318 | if (!TARGET_HARD_FLOAT) | |
7319 | return; | |
7320 | ||
c9034561 | 7321 | if (DEFAULT_ABI != ABI_V4) |
c15c90bb | 7322 | { |
c9034561 | 7323 | if (TARGET_XCOFF && ! TARGET_POWER2 && ! TARGET_POWERPC) |
c15c90bb | 7324 | { |
c9034561 | 7325 | /* AIX library routines for float->int conversion. */ |
85363ca0 ZW |
7326 | set_conv_libfunc (sfix_optab, SImode, DFmode, "__itrunc"); |
7327 | set_conv_libfunc (ufix_optab, SImode, DFmode, "__uitrunc"); | |
4274207b DE |
7328 | set_conv_libfunc (sfix_optab, SImode, TFmode, "_qitrunc"); |
7329 | set_conv_libfunc (ufix_optab, SImode, TFmode, "_quitrunc"); | |
c15c90bb ZW |
7330 | } |
7331 | ||
c9034561 | 7332 | /* Standard AIX/Darwin/64-bit SVR4 quad floating point routines. */ |
c15c90bb ZW |
7333 | set_optab_libfunc (add_optab, TFmode, "_xlqadd"); |
7334 | set_optab_libfunc (sub_optab, TFmode, "_xlqsub"); | |
7335 | set_optab_libfunc (smul_optab, TFmode, "_xlqmul"); | |
7336 | set_optab_libfunc (sdiv_optab, TFmode, "_xlqdiv"); | |
7337 | } | |
c9034561 | 7338 | else |
c15c90bb | 7339 | { |
c9034561 | 7340 | /* 32-bit SVR4 quad floating point routines. */ |
c15c90bb ZW |
7341 | |
7342 | set_optab_libfunc (add_optab, TFmode, "_q_add"); | |
7343 | set_optab_libfunc (sub_optab, TFmode, "_q_sub"); | |
7344 | set_optab_libfunc (neg_optab, TFmode, "_q_neg"); | |
7345 | set_optab_libfunc (smul_optab, TFmode, "_q_mul"); | |
7346 | set_optab_libfunc (sdiv_optab, TFmode, "_q_div"); | |
7347 | if (TARGET_PPC_GPOPT || TARGET_POWER2) | |
7348 | set_optab_libfunc (sqrt_optab, TFmode, "_q_sqrt"); | |
7349 | ||
c9034561 ZW |
7350 | set_optab_libfunc (eq_optab, TFmode, "_q_feq"); |
7351 | set_optab_libfunc (ne_optab, TFmode, "_q_fne"); | |
7352 | set_optab_libfunc (gt_optab, TFmode, "_q_fgt"); | |
7353 | set_optab_libfunc (ge_optab, TFmode, "_q_fge"); | |
7354 | set_optab_libfunc (lt_optab, TFmode, "_q_flt"); | |
7355 | set_optab_libfunc (le_optab, TFmode, "_q_fle"); | |
7356 | ||
85363ca0 ZW |
7357 | set_conv_libfunc (sext_optab, TFmode, SFmode, "_q_stoq"); |
7358 | set_conv_libfunc (sext_optab, TFmode, DFmode, "_q_dtoq"); | |
7359 | set_conv_libfunc (trunc_optab, SFmode, TFmode, "_q_qtos"); | |
7360 | set_conv_libfunc (trunc_optab, DFmode, TFmode, "_q_qtod"); | |
7361 | set_conv_libfunc (sfix_optab, SImode, TFmode, "_q_qtoi"); | |
7362 | set_conv_libfunc (ufix_optab, SImode, TFmode, "_q_qtou"); | |
7363 | set_conv_libfunc (sfloat_optab, TFmode, SImode, "_q_itoq"); | |
c15c90bb ZW |
7364 | } |
7365 | } | |
35aff10b | 7366 | \f |
7e69e155 MM |
7367 | /* Expand a block move operation, and return 1 if successful. Return 0 |
7368 | if we should let the compiler generate normal code. | |
7369 | ||
7370 | operands[0] is the destination | |
7371 | operands[1] is the source | |
7372 | operands[2] is the length | |
7373 | operands[3] is the alignment */ | |
7374 | ||
3933e0e1 MM |
7375 | #define MAX_MOVE_REG 4 |
7376 | ||
7e69e155 | 7377 | int |
a2369ed3 | 7378 | expand_block_move (rtx operands[]) |
7e69e155 | 7379 | { |
b6c9286a MM |
7380 | rtx orig_dest = operands[0]; |
7381 | rtx orig_src = operands[1]; | |
7e69e155 | 7382 | rtx bytes_rtx = operands[2]; |
7e69e155 | 7383 | rtx align_rtx = operands[3]; |
3933e0e1 | 7384 | int constp = (GET_CODE (bytes_rtx) == CONST_INT); |
5ee95df6 | 7385 | int align; |
3933e0e1 MM |
7386 | int bytes; |
7387 | int offset; | |
7e69e155 | 7388 | int move_bytes; |
cabfd258 GK |
7389 | rtx stores[MAX_MOVE_REG]; |
7390 | int num_reg = 0; | |
7e69e155 | 7391 | |
3933e0e1 | 7392 | /* If this is not a fixed size move, just call memcpy */ |
cc0d9ba8 | 7393 | if (! constp) |
3933e0e1 MM |
7394 | return 0; |
7395 | ||
5ee95df6 FS |
7396 | /* If this is not a fixed size alignment, abort */ |
7397 | if (GET_CODE (align_rtx) != CONST_INT) | |
7398 | abort (); | |
7399 | align = INTVAL (align_rtx); | |
7400 | ||
7e69e155 | 7401 | /* Anything to move? */ |
3933e0e1 MM |
7402 | bytes = INTVAL (bytes_rtx); |
7403 | if (bytes <= 0) | |
7e69e155 MM |
7404 | return 1; |
7405 | ||
ea9982a8 | 7406 | /* store_one_arg depends on expand_block_move to handle at least the size of |
6f317ef3 | 7407 | reg_parm_stack_space. */ |
ea9982a8 | 7408 | if (bytes > (TARGET_POWERPC64 ? 64 : 32)) |
7e69e155 MM |
7409 | return 0; |
7410 | ||
cabfd258 | 7411 | for (offset = 0; bytes > 0; offset += move_bytes, bytes -= move_bytes) |
7e69e155 | 7412 | { |
cabfd258 | 7413 | union { |
a2369ed3 DJ |
7414 | rtx (*movstrsi) (rtx, rtx, rtx, rtx); |
7415 | rtx (*mov) (rtx, rtx); | |
cabfd258 GK |
7416 | } gen_func; |
7417 | enum machine_mode mode = BLKmode; | |
7418 | rtx src, dest; | |
7419 | ||
7420 | if (TARGET_STRING | |
7421 | && bytes > 24 /* move up to 32 bytes at a time */ | |
7422 | && ! fixed_regs[5] | |
7423 | && ! fixed_regs[6] | |
7424 | && ! fixed_regs[7] | |
7425 | && ! fixed_regs[8] | |
7426 | && ! fixed_regs[9] | |
7427 | && ! fixed_regs[10] | |
7428 | && ! fixed_regs[11] | |
7429 | && ! fixed_regs[12]) | |
7e69e155 | 7430 | { |
cabfd258 GK |
7431 | move_bytes = (bytes > 32) ? 32 : bytes; |
7432 | gen_func.movstrsi = gen_movstrsi_8reg; | |
7433 | } | |
7434 | else if (TARGET_STRING | |
7435 | && bytes > 16 /* move up to 24 bytes at a time */ | |
7436 | && ! fixed_regs[5] | |
7437 | && ! fixed_regs[6] | |
7438 | && ! fixed_regs[7] | |
7439 | && ! fixed_regs[8] | |
7440 | && ! fixed_regs[9] | |
7441 | && ! fixed_regs[10]) | |
7442 | { | |
7443 | move_bytes = (bytes > 24) ? 24 : bytes; | |
7444 | gen_func.movstrsi = gen_movstrsi_6reg; | |
7445 | } | |
7446 | else if (TARGET_STRING | |
7447 | && bytes > 8 /* move up to 16 bytes at a time */ | |
7448 | && ! fixed_regs[5] | |
7449 | && ! fixed_regs[6] | |
7450 | && ! fixed_regs[7] | |
7451 | && ! fixed_regs[8]) | |
7452 | { | |
7453 | move_bytes = (bytes > 16) ? 16 : bytes; | |
7454 | gen_func.movstrsi = gen_movstrsi_4reg; | |
7455 | } | |
7456 | else if (bytes >= 8 && TARGET_POWERPC64 | |
7457 | /* 64-bit loads and stores require word-aligned | |
7458 | displacements. */ | |
7459 | && (align >= 8 || (! STRICT_ALIGNMENT && align >= 4))) | |
7460 | { | |
7461 | move_bytes = 8; | |
7462 | mode = DImode; | |
7463 | gen_func.mov = gen_movdi; | |
7464 | } | |
7465 | else if (TARGET_STRING && bytes > 4 && !TARGET_POWERPC64) | |
7466 | { /* move up to 8 bytes at a time */ | |
7467 | move_bytes = (bytes > 8) ? 8 : bytes; | |
7468 | gen_func.movstrsi = gen_movstrsi_2reg; | |
7469 | } | |
7470 | else if (bytes >= 4 && (align >= 4 || ! STRICT_ALIGNMENT)) | |
7471 | { /* move 4 bytes */ | |
7472 | move_bytes = 4; | |
7473 | mode = SImode; | |
7474 | gen_func.mov = gen_movsi; | |
7475 | } | |
7476 | else if (bytes == 2 && (align >= 2 || ! STRICT_ALIGNMENT)) | |
7477 | { /* move 2 bytes */ | |
7478 | move_bytes = 2; | |
7479 | mode = HImode; | |
7480 | gen_func.mov = gen_movhi; | |
7481 | } | |
7482 | else if (TARGET_STRING && bytes > 1) | |
7483 | { /* move up to 4 bytes at a time */ | |
7484 | move_bytes = (bytes > 4) ? 4 : bytes; | |
7485 | gen_func.movstrsi = gen_movstrsi_1reg; | |
7486 | } | |
7487 | else /* move 1 byte at a time */ | |
7488 | { | |
7489 | move_bytes = 1; | |
7490 | mode = QImode; | |
7491 | gen_func.mov = gen_movqi; | |
7492 | } | |
7493 | ||
7494 | src = adjust_address (orig_src, mode, offset); | |
7495 | dest = adjust_address (orig_dest, mode, offset); | |
7496 | ||
7497 | if (mode != BLKmode) | |
7498 | { | |
7499 | rtx tmp_reg = gen_reg_rtx (mode); | |
7500 | ||
7501 | emit_insn ((*gen_func.mov) (tmp_reg, src)); | |
7502 | stores[num_reg++] = (*gen_func.mov) (dest, tmp_reg); | |
4c64a852 | 7503 | } |
3933e0e1 | 7504 | |
cabfd258 GK |
7505 | if (mode == BLKmode || num_reg >= MAX_MOVE_REG || bytes == move_bytes) |
7506 | { | |
7507 | int i; | |
7508 | for (i = 0; i < num_reg; i++) | |
7509 | emit_insn (stores[i]); | |
7510 | num_reg = 0; | |
7511 | } | |
35aff10b | 7512 | |
cabfd258 | 7513 | if (mode == BLKmode) |
7e69e155 | 7514 | { |
cabfd258 GK |
7515 | /* Move the address into scratch registers. The movstrsi |
7516 | patterns require zero offset. */ | |
7517 | if (!REG_P (XEXP (src, 0))) | |
b6c9286a | 7518 | { |
cabfd258 GK |
7519 | rtx src_reg = copy_addr_to_reg (XEXP (src, 0)); |
7520 | src = replace_equiv_address (src, src_reg); | |
b6c9286a | 7521 | } |
cabfd258 GK |
7522 | set_mem_size (src, GEN_INT (move_bytes)); |
7523 | ||
7524 | if (!REG_P (XEXP (dest, 0))) | |
3933e0e1 | 7525 | { |
cabfd258 GK |
7526 | rtx dest_reg = copy_addr_to_reg (XEXP (dest, 0)); |
7527 | dest = replace_equiv_address (dest, dest_reg); | |
7e69e155 | 7528 | } |
cabfd258 GK |
7529 | set_mem_size (dest, GEN_INT (move_bytes)); |
7530 | ||
7531 | emit_insn ((*gen_func.movstrsi) (dest, src, | |
7532 | GEN_INT (move_bytes & 31), | |
7533 | align_rtx)); | |
7e69e155 | 7534 | } |
7e69e155 MM |
7535 | } |
7536 | ||
7537 | return 1; | |
7538 | } | |
7539 | ||
9878760c RK |
7540 | \f |
7541 | /* Return 1 if OP is a load multiple operation. It is known to be a | |
7542 | PARALLEL and the first section will be tested. */ | |
7543 | ||
7544 | int | |
a2369ed3 | 7545 | load_multiple_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
9878760c RK |
7546 | { |
7547 | int count = XVECLEN (op, 0); | |
e2c953b6 | 7548 | unsigned int dest_regno; |
9878760c RK |
7549 | rtx src_addr; |
7550 | int i; | |
7551 | ||
7552 | /* Perform a quick check so we don't blow up below. */ | |
7553 | if (count <= 1 | |
7554 | || GET_CODE (XVECEXP (op, 0, 0)) != SET | |
7555 | || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG | |
7556 | || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM) | |
7557 | return 0; | |
7558 | ||
7559 | dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0))); | |
7560 | src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0); | |
7561 | ||
7562 | for (i = 1; i < count; i++) | |
7563 | { | |
7564 | rtx elt = XVECEXP (op, 0, i); | |
7565 | ||
7566 | if (GET_CODE (elt) != SET | |
7567 | || GET_CODE (SET_DEST (elt)) != REG | |
7568 | || GET_MODE (SET_DEST (elt)) != SImode | |
7569 | || REGNO (SET_DEST (elt)) != dest_regno + i | |
7570 | || GET_CODE (SET_SRC (elt)) != MEM | |
7571 | || GET_MODE (SET_SRC (elt)) != SImode | |
7572 | || GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS | |
7573 | || ! rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr) | |
7574 | || GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT | |
7575 | || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != i * 4) | |
7576 | return 0; | |
7577 | } | |
7578 | ||
7579 | return 1; | |
7580 | } | |
7581 | ||
7582 | /* Similar, but tests for store multiple. Here, the second vector element | |
7583 | is a CLOBBER. It will be tested later. */ | |
7584 | ||
7585 | int | |
a2369ed3 | 7586 | store_multiple_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
9878760c RK |
7587 | { |
7588 | int count = XVECLEN (op, 0) - 1; | |
e2c953b6 | 7589 | unsigned int src_regno; |
9878760c RK |
7590 | rtx dest_addr; |
7591 | int i; | |
7592 | ||
7593 | /* Perform a quick check so we don't blow up below. */ | |
7594 | if (count <= 1 | |
7595 | || GET_CODE (XVECEXP (op, 0, 0)) != SET | |
7596 | || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM | |
7597 | || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG) | |
7598 | return 0; | |
7599 | ||
7600 | src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0))); | |
7601 | dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0); | |
7602 | ||
7603 | for (i = 1; i < count; i++) | |
7604 | { | |
7605 | rtx elt = XVECEXP (op, 0, i + 1); | |
7606 | ||
7607 | if (GET_CODE (elt) != SET | |
7608 | || GET_CODE (SET_SRC (elt)) != REG | |
7609 | || GET_MODE (SET_SRC (elt)) != SImode | |
7610 | || REGNO (SET_SRC (elt)) != src_regno + i | |
7611 | || GET_CODE (SET_DEST (elt)) != MEM | |
7612 | || GET_MODE (SET_DEST (elt)) != SImode | |
7613 | || GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS | |
7614 | || ! rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr) | |
7615 | || GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT | |
7616 | || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != i * 4) | |
7617 | return 0; | |
7618 | } | |
7619 | ||
7620 | return 1; | |
7621 | } | |
9ebbca7d | 7622 | |
9caa3eb2 DE |
7623 | /* Return a string to perform a load_multiple operation. |
7624 | operands[0] is the vector. | |
7625 | operands[1] is the source address. | |
7626 | operands[2] is the first destination register. */ | |
7627 | ||
7628 | const char * | |
a2369ed3 | 7629 | rs6000_output_load_multiple (rtx operands[3]) |
9caa3eb2 DE |
7630 | { |
7631 | /* We have to handle the case where the pseudo used to contain the address | |
7632 | is assigned to one of the output registers. */ | |
7633 | int i, j; | |
7634 | int words = XVECLEN (operands[0], 0); | |
7635 | rtx xop[10]; | |
7636 | ||
7637 | if (XVECLEN (operands[0], 0) == 1) | |
7638 | return "{l|lwz} %2,0(%1)"; | |
7639 | ||
7640 | for (i = 0; i < words; i++) | |
7641 | if (refers_to_regno_p (REGNO (operands[2]) + i, | |
7642 | REGNO (operands[2]) + i + 1, operands[1], 0)) | |
7643 | { | |
7644 | if (i == words-1) | |
7645 | { | |
7646 | xop[0] = GEN_INT (4 * (words-1)); | |
7647 | xop[1] = operands[1]; | |
7648 | xop[2] = operands[2]; | |
7649 | output_asm_insn ("{lsi|lswi} %2,%1,%0\n\t{l|lwz} %1,%0(%1)", xop); | |
7650 | return ""; | |
7651 | } | |
7652 | else if (i == 0) | |
7653 | { | |
7654 | xop[0] = GEN_INT (4 * (words-1)); | |
7655 | xop[1] = operands[1]; | |
7656 | xop[2] = gen_rtx_REG (SImode, REGNO (operands[2]) + 1); | |
7657 | output_asm_insn ("{cal %1,4(%1)|addi %1,%1,4}\n\t{lsi|lswi} %2,%1,%0\n\t{l|lwz} %1,-4(%1)", xop); | |
7658 | return ""; | |
7659 | } | |
7660 | else | |
7661 | { | |
7662 | for (j = 0; j < words; j++) | |
7663 | if (j != i) | |
7664 | { | |
7665 | xop[0] = GEN_INT (j * 4); | |
7666 | xop[1] = operands[1]; | |
7667 | xop[2] = gen_rtx_REG (SImode, REGNO (operands[2]) + j); | |
7668 | output_asm_insn ("{l|lwz} %2,%0(%1)", xop); | |
7669 | } | |
7670 | xop[0] = GEN_INT (i * 4); | |
7671 | xop[1] = operands[1]; | |
7672 | output_asm_insn ("{l|lwz} %1,%0(%1)", xop); | |
7673 | return ""; | |
7674 | } | |
7675 | } | |
7676 | ||
7677 | return "{lsi|lswi} %2,%1,%N0"; | |
7678 | } | |
7679 | ||
00b960c7 AH |
7680 | /* Return 1 for a parallel vrsave operation. */ |
7681 | ||
7682 | int | |
a2369ed3 | 7683 | vrsave_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
00b960c7 AH |
7684 | { |
7685 | int count = XVECLEN (op, 0); | |
7686 | unsigned int dest_regno, src_regno; | |
7687 | int i; | |
7688 | ||
7689 | if (count <= 1 | |
7690 | || GET_CODE (XVECEXP (op, 0, 0)) != SET | |
7691 | || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG | |
a004eb82 | 7692 | || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC_VOLATILE) |
00b960c7 AH |
7693 | return 0; |
7694 | ||
7695 | dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0))); | |
7696 | src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0))); | |
7697 | ||
7698 | if (dest_regno != VRSAVE_REGNO | |
7699 | && src_regno != VRSAVE_REGNO) | |
7700 | return 0; | |
7701 | ||
7702 | for (i = 1; i < count; i++) | |
7703 | { | |
7704 | rtx elt = XVECEXP (op, 0, i); | |
7705 | ||
9aa86737 AH |
7706 | if (GET_CODE (elt) != CLOBBER |
7707 | && GET_CODE (elt) != SET) | |
00b960c7 AH |
7708 | return 0; |
7709 | } | |
7710 | ||
7711 | return 1; | |
7712 | } | |
7713 | ||
2c4a9cff DE |
7714 | /* Return 1 for an PARALLEL suitable for mfcr. */ |
7715 | ||
7716 | int | |
a2369ed3 | 7717 | mfcr_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
2c4a9cff DE |
7718 | { |
7719 | int count = XVECLEN (op, 0); | |
7720 | int i; | |
7721 | ||
7722 | /* Perform a quick check so we don't blow up below. */ | |
7723 | if (count < 1 | |
7724 | || GET_CODE (XVECEXP (op, 0, 0)) != SET | |
7725 | || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC | |
7726 | || XVECLEN (SET_SRC (XVECEXP (op, 0, 0)), 0) != 2) | |
7727 | return 0; | |
7728 | ||
7729 | for (i = 0; i < count; i++) | |
7730 | { | |
7731 | rtx exp = XVECEXP (op, 0, i); | |
7732 | rtx unspec; | |
7733 | int maskval; | |
7734 | rtx src_reg; | |
7735 | ||
7736 | src_reg = XVECEXP (SET_SRC (exp), 0, 0); | |
7737 | ||
7738 | if (GET_CODE (src_reg) != REG | |
7739 | || GET_MODE (src_reg) != CCmode | |
7740 | || ! CR_REGNO_P (REGNO (src_reg))) | |
7741 | return 0; | |
7742 | ||
7743 | if (GET_CODE (exp) != SET | |
7744 | || GET_CODE (SET_DEST (exp)) != REG | |
7745 | || GET_MODE (SET_DEST (exp)) != SImode | |
7746 | || ! INT_REGNO_P (REGNO (SET_DEST (exp)))) | |
7747 | return 0; | |
7748 | unspec = SET_SRC (exp); | |
7749 | maskval = 1 << (MAX_CR_REGNO - REGNO (src_reg)); | |
7750 | ||
7751 | if (GET_CODE (unspec) != UNSPEC | |
7752 | || XINT (unspec, 1) != UNSPEC_MOVESI_FROM_CR | |
7753 | || XVECLEN (unspec, 0) != 2 | |
7754 | || XVECEXP (unspec, 0, 0) != src_reg | |
7755 | || GET_CODE (XVECEXP (unspec, 0, 1)) != CONST_INT | |
7756 | || INTVAL (XVECEXP (unspec, 0, 1)) != maskval) | |
7757 | return 0; | |
7758 | } | |
7759 | return 1; | |
7760 | } | |
7761 | ||
a4f6c312 | 7762 | /* Return 1 for an PARALLEL suitable for mtcrf. */ |
9ebbca7d GK |
7763 | |
7764 | int | |
a2369ed3 | 7765 | mtcrf_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
9ebbca7d GK |
7766 | { |
7767 | int count = XVECLEN (op, 0); | |
7768 | int i; | |
9ebbca7d GK |
7769 | rtx src_reg; |
7770 | ||
7771 | /* Perform a quick check so we don't blow up below. */ | |
e35b9579 GK |
7772 | if (count < 1 |
7773 | || GET_CODE (XVECEXP (op, 0, 0)) != SET | |
7774 | || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC | |
7775 | || XVECLEN (SET_SRC (XVECEXP (op, 0, 0)), 0) != 2) | |
9ebbca7d | 7776 | return 0; |
e35b9579 | 7777 | src_reg = XVECEXP (SET_SRC (XVECEXP (op, 0, 0)), 0, 0); |
9ebbca7d GK |
7778 | |
7779 | if (GET_CODE (src_reg) != REG | |
7780 | || GET_MODE (src_reg) != SImode | |
7781 | || ! INT_REGNO_P (REGNO (src_reg))) | |
7782 | return 0; | |
7783 | ||
e35b9579 | 7784 | for (i = 0; i < count; i++) |
9ebbca7d GK |
7785 | { |
7786 | rtx exp = XVECEXP (op, 0, i); | |
7787 | rtx unspec; | |
7788 | int maskval; | |
7789 | ||
7790 | if (GET_CODE (exp) != SET | |
7791 | || GET_CODE (SET_DEST (exp)) != REG | |
7792 | || GET_MODE (SET_DEST (exp)) != CCmode | |
7793 | || ! CR_REGNO_P (REGNO (SET_DEST (exp)))) | |
7794 | return 0; | |
7795 | unspec = SET_SRC (exp); | |
7796 | maskval = 1 << (MAX_CR_REGNO - REGNO (SET_DEST (exp))); | |
9ebbca7d GK |
7797 | |
7798 | if (GET_CODE (unspec) != UNSPEC | |
615158e2 | 7799 | || XINT (unspec, 1) != UNSPEC_MOVESI_TO_CR |
9ebbca7d GK |
7800 | || XVECLEN (unspec, 0) != 2 |
7801 | || XVECEXP (unspec, 0, 0) != src_reg | |
7802 | || GET_CODE (XVECEXP (unspec, 0, 1)) != CONST_INT | |
7803 | || INTVAL (XVECEXP (unspec, 0, 1)) != maskval) | |
7804 | return 0; | |
7805 | } | |
e35b9579 | 7806 | return 1; |
9ebbca7d GK |
7807 | } |
7808 | ||
a4f6c312 | 7809 | /* Return 1 for an PARALLEL suitable for lmw. */ |
9ebbca7d GK |
7810 | |
7811 | int | |
a2369ed3 | 7812 | lmw_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
9ebbca7d GK |
7813 | { |
7814 | int count = XVECLEN (op, 0); | |
e2c953b6 | 7815 | unsigned int dest_regno; |
9ebbca7d | 7816 | rtx src_addr; |
e2c953b6 | 7817 | unsigned int base_regno; |
9ebbca7d GK |
7818 | HOST_WIDE_INT offset; |
7819 | int i; | |
7820 | ||
7821 | /* Perform a quick check so we don't blow up below. */ | |
7822 | if (count <= 1 | |
7823 | || GET_CODE (XVECEXP (op, 0, 0)) != SET | |
7824 | || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG | |
7825 | || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM) | |
7826 | return 0; | |
7827 | ||
7828 | dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0))); | |
7829 | src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0); | |
7830 | ||
7831 | if (dest_regno > 31 | |
e2c953b6 | 7832 | || count != 32 - (int) dest_regno) |
9ebbca7d GK |
7833 | return 0; |
7834 | ||
4d588c14 | 7835 | if (legitimate_indirect_address_p (src_addr, 0)) |
9ebbca7d GK |
7836 | { |
7837 | offset = 0; | |
7838 | base_regno = REGNO (src_addr); | |
7839 | if (base_regno == 0) | |
7840 | return 0; | |
7841 | } | |
4d588c14 | 7842 | else if (legitimate_offset_address_p (SImode, src_addr, 0)) |
9ebbca7d GK |
7843 | { |
7844 | offset = INTVAL (XEXP (src_addr, 1)); | |
7845 | base_regno = REGNO (XEXP (src_addr, 0)); | |
7846 | } | |
7847 | else | |
7848 | return 0; | |
7849 | ||
7850 | for (i = 0; i < count; i++) | |
7851 | { | |
7852 | rtx elt = XVECEXP (op, 0, i); | |
7853 | rtx newaddr; | |
7854 | rtx addr_reg; | |
7855 | HOST_WIDE_INT newoffset; | |
7856 | ||
7857 | if (GET_CODE (elt) != SET | |
7858 | || GET_CODE (SET_DEST (elt)) != REG | |
7859 | || GET_MODE (SET_DEST (elt)) != SImode | |
7860 | || REGNO (SET_DEST (elt)) != dest_regno + i | |
7861 | || GET_CODE (SET_SRC (elt)) != MEM | |
7862 | || GET_MODE (SET_SRC (elt)) != SImode) | |
7863 | return 0; | |
7864 | newaddr = XEXP (SET_SRC (elt), 0); | |
4d588c14 | 7865 | if (legitimate_indirect_address_p (newaddr, 0)) |
9ebbca7d GK |
7866 | { |
7867 | newoffset = 0; | |
7868 | addr_reg = newaddr; | |
7869 | } | |
4d588c14 | 7870 | else if (legitimate_offset_address_p (SImode, newaddr, 0)) |
9ebbca7d GK |
7871 | { |
7872 | addr_reg = XEXP (newaddr, 0); | |
7873 | newoffset = INTVAL (XEXP (newaddr, 1)); | |
7874 | } | |
7875 | else | |
7876 | return 0; | |
7877 | if (REGNO (addr_reg) != base_regno | |
7878 | || newoffset != offset + 4 * i) | |
7879 | return 0; | |
7880 | } | |
7881 | ||
7882 | return 1; | |
7883 | } | |
7884 | ||
a4f6c312 | 7885 | /* Return 1 for an PARALLEL suitable for stmw. */ |
9ebbca7d GK |
7886 | |
7887 | int | |
a2369ed3 | 7888 | stmw_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
9ebbca7d GK |
7889 | { |
7890 | int count = XVECLEN (op, 0); | |
e2c953b6 | 7891 | unsigned int src_regno; |
9ebbca7d | 7892 | rtx dest_addr; |
e2c953b6 | 7893 | unsigned int base_regno; |
9ebbca7d GK |
7894 | HOST_WIDE_INT offset; |
7895 | int i; | |
7896 | ||
7897 | /* Perform a quick check so we don't blow up below. */ | |
7898 | if (count <= 1 | |
7899 | || GET_CODE (XVECEXP (op, 0, 0)) != SET | |
7900 | || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM | |
7901 | || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG) | |
7902 | return 0; | |
7903 | ||
7904 | src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0))); | |
7905 | dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0); | |
7906 | ||
7907 | if (src_regno > 31 | |
e2c953b6 | 7908 | || count != 32 - (int) src_regno) |
9ebbca7d GK |
7909 | return 0; |
7910 | ||
4d588c14 | 7911 | if (legitimate_indirect_address_p (dest_addr, 0)) |
9ebbca7d GK |
7912 | { |
7913 | offset = 0; | |
7914 | base_regno = REGNO (dest_addr); | |
7915 | if (base_regno == 0) | |
7916 | return 0; | |
7917 | } | |
4d588c14 | 7918 | else if (legitimate_offset_address_p (SImode, dest_addr, 0)) |
9ebbca7d GK |
7919 | { |
7920 | offset = INTVAL (XEXP (dest_addr, 1)); | |
7921 | base_regno = REGNO (XEXP (dest_addr, 0)); | |
7922 | } | |
7923 | else | |
7924 | return 0; | |
7925 | ||
7926 | for (i = 0; i < count; i++) | |
7927 | { | |
7928 | rtx elt = XVECEXP (op, 0, i); | |
7929 | rtx newaddr; | |
7930 | rtx addr_reg; | |
7931 | HOST_WIDE_INT newoffset; | |
7932 | ||
7933 | if (GET_CODE (elt) != SET | |
7934 | || GET_CODE (SET_SRC (elt)) != REG | |
7935 | || GET_MODE (SET_SRC (elt)) != SImode | |
7936 | || REGNO (SET_SRC (elt)) != src_regno + i | |
7937 | || GET_CODE (SET_DEST (elt)) != MEM | |
7938 | || GET_MODE (SET_DEST (elt)) != SImode) | |
7939 | return 0; | |
7940 | newaddr = XEXP (SET_DEST (elt), 0); | |
4d588c14 | 7941 | if (legitimate_indirect_address_p (newaddr, 0)) |
9ebbca7d GK |
7942 | { |
7943 | newoffset = 0; | |
7944 | addr_reg = newaddr; | |
7945 | } | |
4d588c14 | 7946 | else if (legitimate_offset_address_p (SImode, newaddr, 0)) |
9ebbca7d GK |
7947 | { |
7948 | addr_reg = XEXP (newaddr, 0); | |
7949 | newoffset = INTVAL (XEXP (newaddr, 1)); | |
7950 | } | |
7951 | else | |
7952 | return 0; | |
7953 | if (REGNO (addr_reg) != base_regno | |
7954 | || newoffset != offset + 4 * i) | |
7955 | return 0; | |
7956 | } | |
7957 | ||
7958 | return 1; | |
7959 | } | |
9878760c | 7960 | \f |
a4f6c312 SS |
7961 | /* A validation routine: say whether CODE, a condition code, and MODE |
7962 | match. The other alternatives either don't make sense or should | |
7963 | never be generated. */ | |
39a10a29 | 7964 | |
39a10a29 | 7965 | static void |
a2369ed3 | 7966 | validate_condition_mode (enum rtx_code code, enum machine_mode mode) |
39a10a29 GK |
7967 | { |
7968 | if (GET_RTX_CLASS (code) != '<' | |
7969 | || GET_MODE_CLASS (mode) != MODE_CC) | |
7970 | abort (); | |
7971 | ||
7972 | /* These don't make sense. */ | |
7973 | if ((code == GT || code == LT || code == GE || code == LE) | |
7974 | && mode == CCUNSmode) | |
7975 | abort (); | |
7976 | ||
7977 | if ((code == GTU || code == LTU || code == GEU || code == LEU) | |
7978 | && mode != CCUNSmode) | |
7979 | abort (); | |
7980 | ||
7981 | if (mode != CCFPmode | |
7982 | && (code == ORDERED || code == UNORDERED | |
7983 | || code == UNEQ || code == LTGT | |
7984 | || code == UNGT || code == UNLT | |
7985 | || code == UNGE || code == UNLE)) | |
a4f6c312 | 7986 | abort (); |
39a10a29 | 7987 | |
de6c5979 | 7988 | /* These should never be generated except for |
bc9ec0e0 | 7989 | flag_finite_math_only. */ |
39a10a29 | 7990 | if (mode == CCFPmode |
ad72b533 | 7991 | && ! flag_finite_math_only |
39a10a29 GK |
7992 | && (code == LE || code == GE |
7993 | || code == UNEQ || code == LTGT | |
7994 | || code == UNGT || code == UNLT)) | |
7995 | abort (); | |
7996 | ||
7997 | /* These are invalid; the information is not there. */ | |
7998 | if (mode == CCEQmode | |
7999 | && code != EQ && code != NE) | |
8000 | abort (); | |
8001 | } | |
8002 | ||
9878760c RK |
8003 | /* Return 1 if OP is a comparison operation that is valid for a branch insn. |
8004 | We only check the opcode against the mode of the CC value here. */ | |
8005 | ||
8006 | int | |
a2369ed3 | 8007 | branch_comparison_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
9878760c RK |
8008 | { |
8009 | enum rtx_code code = GET_CODE (op); | |
8010 | enum machine_mode cc_mode; | |
8011 | ||
8012 | if (GET_RTX_CLASS (code) != '<') | |
8013 | return 0; | |
8014 | ||
8015 | cc_mode = GET_MODE (XEXP (op, 0)); | |
8016 | if (GET_MODE_CLASS (cc_mode) != MODE_CC) | |
8017 | return 0; | |
8018 | ||
39a10a29 | 8019 | validate_condition_mode (code, cc_mode); |
9878760c | 8020 | |
39a10a29 GK |
8021 | return 1; |
8022 | } | |
8023 | ||
8024 | /* Return 1 if OP is a comparison operation that is valid for a branch | |
8025 | insn and which is true if the corresponding bit in the CC register | |
8026 | is set. */ | |
8027 | ||
8028 | int | |
a2369ed3 | 8029 | branch_positive_comparison_operator (rtx op, enum machine_mode mode) |
39a10a29 GK |
8030 | { |
8031 | enum rtx_code code; | |
8032 | ||
8daf2e65 | 8033 | if (! branch_comparison_operator (op, mode)) |
9878760c RK |
8034 | return 0; |
8035 | ||
39a10a29 GK |
8036 | code = GET_CODE (op); |
8037 | return (code == EQ || code == LT || code == GT | |
993f19a8 | 8038 | || (TARGET_E500 && TARGET_HARD_FLOAT && !TARGET_FPRS && code == NE) |
39a10a29 GK |
8039 | || code == LTU || code == GTU |
8040 | || code == UNORDERED); | |
9878760c RK |
8041 | } |
8042 | ||
b7053a3f GK |
8043 | /* Return 1 if OP is a comparison operation that is valid for an scc |
8044 | insn: it must be a positive comparison. */ | |
9878760c RK |
8045 | |
8046 | int | |
a2369ed3 | 8047 | scc_comparison_operator (rtx op, enum machine_mode mode) |
9878760c | 8048 | { |
b7053a3f | 8049 | return branch_positive_comparison_operator (op, mode); |
9878760c | 8050 | } |
e0cd0770 JC |
8051 | |
8052 | int | |
a2369ed3 | 8053 | trap_comparison_operator (rtx op, enum machine_mode mode) |
e0cd0770 JC |
8054 | { |
8055 | if (mode != VOIDmode && mode != GET_MODE (op)) | |
8056 | return 0; | |
39a10a29 | 8057 | return GET_RTX_CLASS (GET_CODE (op)) == '<'; |
e0cd0770 | 8058 | } |
dfbdccdb GK |
8059 | |
8060 | int | |
a2369ed3 | 8061 | boolean_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
dfbdccdb GK |
8062 | { |
8063 | enum rtx_code code = GET_CODE (op); | |
8064 | return (code == AND || code == IOR || code == XOR); | |
8065 | } | |
1d328b19 GK |
8066 | |
8067 | int | |
a2369ed3 | 8068 | boolean_or_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
1d328b19 GK |
8069 | { |
8070 | enum rtx_code code = GET_CODE (op); | |
8071 | return (code == IOR || code == XOR); | |
8072 | } | |
50a0b056 GK |
8073 | |
8074 | int | |
a2369ed3 | 8075 | min_max_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
50a0b056 GK |
8076 | { |
8077 | enum rtx_code code = GET_CODE (op); | |
8078 | return (code == SMIN || code == SMAX || code == UMIN || code == UMAX); | |
8079 | } | |
9878760c RK |
8080 | \f |
8081 | /* Return 1 if ANDOP is a mask that has no bits on that are not in the | |
8082 | mask required to convert the result of a rotate insn into a shift | |
b1765bde | 8083 | left insn of SHIFTOP bits. Both are known to be SImode CONST_INT. */ |
9878760c RK |
8084 | |
8085 | int | |
a2369ed3 | 8086 | includes_lshift_p (rtx shiftop, rtx andop) |
9878760c | 8087 | { |
e2c953b6 DE |
8088 | unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0; |
8089 | ||
8090 | shift_mask <<= INTVAL (shiftop); | |
9878760c | 8091 | |
b1765bde | 8092 | return (INTVAL (andop) & 0xffffffff & ~shift_mask) == 0; |
9878760c RK |
8093 | } |
8094 | ||
8095 | /* Similar, but for right shift. */ | |
8096 | ||
8097 | int | |
a2369ed3 | 8098 | includes_rshift_p (rtx shiftop, rtx andop) |
9878760c | 8099 | { |
a7653a2c | 8100 | unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0; |
9878760c RK |
8101 | |
8102 | shift_mask >>= INTVAL (shiftop); | |
8103 | ||
b1765bde | 8104 | return (INTVAL (andop) & 0xffffffff & ~shift_mask) == 0; |
e2c953b6 DE |
8105 | } |
8106 | ||
c5059423 AM |
8107 | /* Return 1 if ANDOP is a mask suitable for use with an rldic insn |
8108 | to perform a left shift. It must have exactly SHIFTOP least | |
b6d08ca1 | 8109 | significant 0's, then one or more 1's, then zero or more 0's. */ |
e2c953b6 DE |
8110 | |
8111 | int | |
a2369ed3 | 8112 | includes_rldic_lshift_p (rtx shiftop, rtx andop) |
e2c953b6 | 8113 | { |
c5059423 AM |
8114 | if (GET_CODE (andop) == CONST_INT) |
8115 | { | |
02071907 | 8116 | HOST_WIDE_INT c, lsb, shift_mask; |
e2c953b6 | 8117 | |
c5059423 | 8118 | c = INTVAL (andop); |
02071907 | 8119 | if (c == 0 || c == ~0) |
c5059423 | 8120 | return 0; |
e2c953b6 | 8121 | |
02071907 | 8122 | shift_mask = ~0; |
c5059423 AM |
8123 | shift_mask <<= INTVAL (shiftop); |
8124 | ||
b6d08ca1 | 8125 | /* Find the least significant one bit. */ |
c5059423 AM |
8126 | lsb = c & -c; |
8127 | ||
8128 | /* It must coincide with the LSB of the shift mask. */ | |
8129 | if (-lsb != shift_mask) | |
8130 | return 0; | |
e2c953b6 | 8131 | |
c5059423 AM |
8132 | /* Invert to look for the next transition (if any). */ |
8133 | c = ~c; | |
8134 | ||
8135 | /* Remove the low group of ones (originally low group of zeros). */ | |
8136 | c &= -lsb; | |
8137 | ||
8138 | /* Again find the lsb, and check we have all 1's above. */ | |
8139 | lsb = c & -c; | |
8140 | return c == -lsb; | |
8141 | } | |
8142 | else if (GET_CODE (andop) == CONST_DOUBLE | |
8143 | && (GET_MODE (andop) == VOIDmode || GET_MODE (andop) == DImode)) | |
8144 | { | |
02071907 AM |
8145 | HOST_WIDE_INT low, high, lsb; |
8146 | HOST_WIDE_INT shift_mask_low, shift_mask_high; | |
c5059423 AM |
8147 | |
8148 | low = CONST_DOUBLE_LOW (andop); | |
8149 | if (HOST_BITS_PER_WIDE_INT < 64) | |
8150 | high = CONST_DOUBLE_HIGH (andop); | |
8151 | ||
8152 | if ((low == 0 && (HOST_BITS_PER_WIDE_INT >= 64 || high == 0)) | |
02071907 | 8153 | || (low == ~0 && (HOST_BITS_PER_WIDE_INT >= 64 || high == ~0))) |
c5059423 AM |
8154 | return 0; |
8155 | ||
8156 | if (HOST_BITS_PER_WIDE_INT < 64 && low == 0) | |
8157 | { | |
02071907 | 8158 | shift_mask_high = ~0; |
c5059423 AM |
8159 | if (INTVAL (shiftop) > 32) |
8160 | shift_mask_high <<= INTVAL (shiftop) - 32; | |
8161 | ||
8162 | lsb = high & -high; | |
8163 | ||
8164 | if (-lsb != shift_mask_high || INTVAL (shiftop) < 32) | |
8165 | return 0; | |
8166 | ||
8167 | high = ~high; | |
8168 | high &= -lsb; | |
8169 | ||
8170 | lsb = high & -high; | |
8171 | return high == -lsb; | |
8172 | } | |
8173 | ||
02071907 | 8174 | shift_mask_low = ~0; |
c5059423 AM |
8175 | shift_mask_low <<= INTVAL (shiftop); |
8176 | ||
8177 | lsb = low & -low; | |
8178 | ||
8179 | if (-lsb != shift_mask_low) | |
8180 | return 0; | |
8181 | ||
8182 | if (HOST_BITS_PER_WIDE_INT < 64) | |
8183 | high = ~high; | |
8184 | low = ~low; | |
8185 | low &= -lsb; | |
8186 | ||
8187 | if (HOST_BITS_PER_WIDE_INT < 64 && low == 0) | |
8188 | { | |
8189 | lsb = high & -high; | |
8190 | return high == -lsb; | |
8191 | } | |
8192 | ||
8193 | lsb = low & -low; | |
8194 | return low == -lsb && (HOST_BITS_PER_WIDE_INT >= 64 || high == ~0); | |
8195 | } | |
8196 | else | |
8197 | return 0; | |
8198 | } | |
e2c953b6 | 8199 | |
c5059423 AM |
8200 | /* Return 1 if ANDOP is a mask suitable for use with an rldicr insn |
8201 | to perform a left shift. It must have SHIFTOP or more least | |
c1207243 | 8202 | significant 0's, with the remainder of the word 1's. */ |
e2c953b6 | 8203 | |
c5059423 | 8204 | int |
a2369ed3 | 8205 | includes_rldicr_lshift_p (rtx shiftop, rtx andop) |
c5059423 | 8206 | { |
e2c953b6 | 8207 | if (GET_CODE (andop) == CONST_INT) |
c5059423 | 8208 | { |
02071907 | 8209 | HOST_WIDE_INT c, lsb, shift_mask; |
c5059423 | 8210 | |
02071907 | 8211 | shift_mask = ~0; |
c5059423 AM |
8212 | shift_mask <<= INTVAL (shiftop); |
8213 | c = INTVAL (andop); | |
8214 | ||
c1207243 | 8215 | /* Find the least significant one bit. */ |
c5059423 AM |
8216 | lsb = c & -c; |
8217 | ||
8218 | /* It must be covered by the shift mask. | |
a4f6c312 | 8219 | This test also rejects c == 0. */ |
c5059423 AM |
8220 | if ((lsb & shift_mask) == 0) |
8221 | return 0; | |
8222 | ||
8223 | /* Check we have all 1's above the transition, and reject all 1's. */ | |
8224 | return c == -lsb && lsb != 1; | |
8225 | } | |
8226 | else if (GET_CODE (andop) == CONST_DOUBLE | |
8227 | && (GET_MODE (andop) == VOIDmode || GET_MODE (andop) == DImode)) | |
8228 | { | |
02071907 | 8229 | HOST_WIDE_INT low, lsb, shift_mask_low; |
c5059423 AM |
8230 | |
8231 | low = CONST_DOUBLE_LOW (andop); | |
8232 | ||
8233 | if (HOST_BITS_PER_WIDE_INT < 64) | |
8234 | { | |
02071907 | 8235 | HOST_WIDE_INT high, shift_mask_high; |
c5059423 AM |
8236 | |
8237 | high = CONST_DOUBLE_HIGH (andop); | |
8238 | ||
8239 | if (low == 0) | |
8240 | { | |
02071907 | 8241 | shift_mask_high = ~0; |
c5059423 AM |
8242 | if (INTVAL (shiftop) > 32) |
8243 | shift_mask_high <<= INTVAL (shiftop) - 32; | |
8244 | ||
8245 | lsb = high & -high; | |
8246 | ||
8247 | if ((lsb & shift_mask_high) == 0) | |
8248 | return 0; | |
8249 | ||
8250 | return high == -lsb; | |
8251 | } | |
8252 | if (high != ~0) | |
8253 | return 0; | |
8254 | } | |
8255 | ||
02071907 | 8256 | shift_mask_low = ~0; |
c5059423 AM |
8257 | shift_mask_low <<= INTVAL (shiftop); |
8258 | ||
8259 | lsb = low & -low; | |
8260 | ||
8261 | if ((lsb & shift_mask_low) == 0) | |
8262 | return 0; | |
8263 | ||
8264 | return low == -lsb && lsb != 1; | |
8265 | } | |
e2c953b6 | 8266 | else |
c5059423 | 8267 | return 0; |
9878760c | 8268 | } |
35068b43 RK |
8269 | |
8270 | /* Return 1 if REGNO (reg1) == REGNO (reg2) - 1 making them candidates | |
8271 | for lfq and stfq insns. | |
8272 | ||
8273 | Note reg1 and reg2 *must* be hard registers. To be sure we will | |
8274 | abort if we are passed pseudo registers. */ | |
8275 | ||
8276 | int | |
a2369ed3 | 8277 | registers_ok_for_quad_peep (rtx reg1, rtx reg2) |
35068b43 RK |
8278 | { |
8279 | /* We might have been passed a SUBREG. */ | |
8280 | if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG) | |
8281 | return 0; | |
8282 | ||
8283 | return (REGNO (reg1) == REGNO (reg2) - 1); | |
8284 | } | |
8285 | ||
a4f6c312 SS |
8286 | /* Return 1 if addr1 and addr2 are suitable for lfq or stfq insn. |
8287 | addr1 and addr2 must be in consecutive memory locations | |
8288 | (addr2 == addr1 + 8). */ | |
35068b43 RK |
8289 | |
8290 | int | |
a2369ed3 | 8291 | addrs_ok_for_quad_peep (rtx addr1, rtx addr2) |
35068b43 | 8292 | { |
e2c953b6 | 8293 | unsigned int reg1; |
35068b43 RK |
8294 | int offset1; |
8295 | ||
8296 | /* Extract an offset (if used) from the first addr. */ | |
8297 | if (GET_CODE (addr1) == PLUS) | |
8298 | { | |
8299 | /* If not a REG, return zero. */ | |
8300 | if (GET_CODE (XEXP (addr1, 0)) != REG) | |
8301 | return 0; | |
8302 | else | |
8303 | { | |
8304 | reg1 = REGNO (XEXP (addr1, 0)); | |
8305 | /* The offset must be constant! */ | |
8306 | if (GET_CODE (XEXP (addr1, 1)) != CONST_INT) | |
8307 | return 0; | |
8308 | offset1 = INTVAL (XEXP (addr1, 1)); | |
8309 | } | |
8310 | } | |
8311 | else if (GET_CODE (addr1) != REG) | |
8312 | return 0; | |
8313 | else | |
8314 | { | |
8315 | reg1 = REGNO (addr1); | |
8316 | /* This was a simple (mem (reg)) expression. Offset is 0. */ | |
8317 | offset1 = 0; | |
8318 | } | |
8319 | ||
a2369ed3 | 8320 | /* Make sure the second address is a (mem (plus (reg) (const_int))) |
0f6937fe AM |
8321 | or if it is (mem (reg)) then make sure that offset1 is -8 and the same |
8322 | register as addr1. */ | |
984e25ac | 8323 | if (offset1 == -8 && GET_CODE (addr2) == REG && reg1 == REGNO (addr2)) |
0f6937fe | 8324 | return 1; |
35068b43 RK |
8325 | if (GET_CODE (addr2) != PLUS) |
8326 | return 0; | |
8327 | ||
8328 | if (GET_CODE (XEXP (addr2, 0)) != REG | |
8329 | || GET_CODE (XEXP (addr2, 1)) != CONST_INT) | |
8330 | return 0; | |
8331 | ||
8332 | if (reg1 != REGNO (XEXP (addr2, 0))) | |
8333 | return 0; | |
8334 | ||
8335 | /* The offset for the second addr must be 8 more than the first addr. */ | |
8336 | if (INTVAL (XEXP (addr2, 1)) != offset1 + 8) | |
8337 | return 0; | |
8338 | ||
8339 | /* All the tests passed. addr1 and addr2 are valid for lfq or stfq | |
8340 | instructions. */ | |
8341 | return 1; | |
8342 | } | |
9878760c RK |
8343 | \f |
8344 | /* Return the register class of a scratch register needed to copy IN into | |
8345 | or out of a register in CLASS in MODE. If it can be done directly, | |
8346 | NO_REGS is returned. */ | |
8347 | ||
8348 | enum reg_class | |
a2369ed3 | 8349 | secondary_reload_class (enum reg_class class, |
a9baceb1 GK |
8350 | enum machine_mode mode ATTRIBUTE_UNUSED, |
8351 | rtx in) | |
9878760c | 8352 | { |
5accd822 | 8353 | int regno; |
9878760c | 8354 | |
ab82a49f AP |
8355 | if (TARGET_ELF || (DEFAULT_ABI == ABI_DARWIN |
8356 | #if TARGET_MACHO | |
8357 | && MACHOPIC_INDIRECT | |
8358 | #endif | |
8359 | )) | |
46fad5b7 DJ |
8360 | { |
8361 | /* We cannot copy a symbolic operand directly into anything | |
8362 | other than BASE_REGS for TARGET_ELF. So indicate that a | |
8363 | register from BASE_REGS is needed as an intermediate | |
8364 | register. | |
8365 | ||
8366 | On Darwin, pic addresses require a load from memory, which | |
8367 | needs a base register. */ | |
8368 | if (class != BASE_REGS | |
8369 | && (GET_CODE (in) == SYMBOL_REF | |
8370 | || GET_CODE (in) == HIGH | |
8371 | || GET_CODE (in) == LABEL_REF | |
8372 | || GET_CODE (in) == CONST)) | |
8373 | return BASE_REGS; | |
8374 | } | |
e7b7998a | 8375 | |
5accd822 DE |
8376 | if (GET_CODE (in) == REG) |
8377 | { | |
8378 | regno = REGNO (in); | |
8379 | if (regno >= FIRST_PSEUDO_REGISTER) | |
8380 | { | |
8381 | regno = true_regnum (in); | |
8382 | if (regno >= FIRST_PSEUDO_REGISTER) | |
8383 | regno = -1; | |
8384 | } | |
8385 | } | |
8386 | else if (GET_CODE (in) == SUBREG) | |
8387 | { | |
8388 | regno = true_regnum (in); | |
8389 | if (regno >= FIRST_PSEUDO_REGISTER) | |
8390 | regno = -1; | |
8391 | } | |
8392 | else | |
8393 | regno = -1; | |
8394 | ||
9878760c RK |
8395 | /* We can place anything into GENERAL_REGS and can put GENERAL_REGS |
8396 | into anything. */ | |
8397 | if (class == GENERAL_REGS || class == BASE_REGS | |
8398 | || (regno >= 0 && INT_REGNO_P (regno))) | |
8399 | return NO_REGS; | |
8400 | ||
8401 | /* Constants, memory, and FP registers can go into FP registers. */ | |
8402 | if ((regno == -1 || FP_REGNO_P (regno)) | |
8403 | && (class == FLOAT_REGS || class == NON_SPECIAL_REGS)) | |
8404 | return NO_REGS; | |
8405 | ||
0ac081f6 AH |
8406 | /* Memory, and AltiVec registers can go into AltiVec registers. */ |
8407 | if ((regno == -1 || ALTIVEC_REGNO_P (regno)) | |
8408 | && class == ALTIVEC_REGS) | |
8409 | return NO_REGS; | |
8410 | ||
9878760c RK |
8411 | /* We can copy among the CR registers. */ |
8412 | if ((class == CR_REGS || class == CR0_REGS) | |
8413 | && regno >= 0 && CR_REGNO_P (regno)) | |
8414 | return NO_REGS; | |
8415 | ||
8416 | /* Otherwise, we need GENERAL_REGS. */ | |
8417 | return GENERAL_REGS; | |
8418 | } | |
8419 | \f | |
8420 | /* Given a comparison operation, return the bit number in CCR to test. We | |
8421 | know this is a valid comparison. | |
8422 | ||
8423 | SCC_P is 1 if this is for an scc. That means that %D will have been | |
8424 | used instead of %C, so the bits will be in different places. | |
8425 | ||
b4ac57ab | 8426 | Return -1 if OP isn't a valid comparison for some reason. */ |
9878760c RK |
8427 | |
8428 | int | |
a2369ed3 | 8429 | ccr_bit (rtx op, int scc_p) |
9878760c RK |
8430 | { |
8431 | enum rtx_code code = GET_CODE (op); | |
8432 | enum machine_mode cc_mode; | |
8433 | int cc_regnum; | |
8434 | int base_bit; | |
9ebbca7d | 8435 | rtx reg; |
9878760c RK |
8436 | |
8437 | if (GET_RTX_CLASS (code) != '<') | |
8438 | return -1; | |
8439 | ||
9ebbca7d GK |
8440 | reg = XEXP (op, 0); |
8441 | ||
8442 | if (GET_CODE (reg) != REG | |
8443 | || ! CR_REGNO_P (REGNO (reg))) | |
8444 | abort (); | |
8445 | ||
8446 | cc_mode = GET_MODE (reg); | |
8447 | cc_regnum = REGNO (reg); | |
8448 | base_bit = 4 * (cc_regnum - CR0_REGNO); | |
9878760c | 8449 | |
39a10a29 | 8450 | validate_condition_mode (code, cc_mode); |
c5defebb | 8451 | |
b7053a3f GK |
8452 | /* When generating a sCOND operation, only positive conditions are |
8453 | allowed. */ | |
8454 | if (scc_p && code != EQ && code != GT && code != LT && code != UNORDERED | |
8455 | && code != GTU && code != LTU) | |
8456 | abort (); | |
8457 | ||
9878760c RK |
8458 | switch (code) |
8459 | { | |
8460 | case NE: | |
993f19a8 AH |
8461 | if (TARGET_E500 && !TARGET_FPRS |
8462 | && TARGET_HARD_FLOAT && cc_mode == CCFPmode) | |
a3170dc6 | 8463 | return base_bit + 1; |
9878760c RK |
8464 | return scc_p ? base_bit + 3 : base_bit + 2; |
8465 | case EQ: | |
993f19a8 AH |
8466 | if (TARGET_E500 && !TARGET_FPRS |
8467 | && TARGET_HARD_FLOAT && cc_mode == CCFPmode) | |
a3170dc6 | 8468 | return base_bit + 1; |
9878760c | 8469 | return base_bit + 2; |
1c882ea4 | 8470 | case GT: case GTU: case UNLE: |
9878760c | 8471 | return base_bit + 1; |
1c882ea4 | 8472 | case LT: case LTU: case UNGE: |
9878760c | 8473 | return base_bit; |
1c882ea4 GK |
8474 | case ORDERED: case UNORDERED: |
8475 | return base_bit + 3; | |
9878760c RK |
8476 | |
8477 | case GE: case GEU: | |
39a10a29 | 8478 | /* If scc, we will have done a cror to put the bit in the |
9878760c RK |
8479 | unordered position. So test that bit. For integer, this is ! LT |
8480 | unless this is an scc insn. */ | |
39a10a29 | 8481 | return scc_p ? base_bit + 3 : base_bit; |
9878760c RK |
8482 | |
8483 | case LE: case LEU: | |
39a10a29 | 8484 | return scc_p ? base_bit + 3 : base_bit + 1; |
1c882ea4 | 8485 | |
9878760c RK |
8486 | default: |
8487 | abort (); | |
8488 | } | |
8489 | } | |
1ff7789b | 8490 | \f |
8d30c4ee | 8491 | /* Return the GOT register. */ |
1ff7789b MM |
8492 | |
8493 | struct rtx_def * | |
a2369ed3 | 8494 | rs6000_got_register (rtx value ATTRIBUTE_UNUSED) |
1ff7789b | 8495 | { |
a4f6c312 SS |
8496 | /* The second flow pass currently (June 1999) can't update |
8497 | regs_ever_live without disturbing other parts of the compiler, so | |
8498 | update it here to make the prolog/epilogue code happy. */ | |
1db02437 FS |
8499 | if (no_new_pseudos && ! regs_ever_live[RS6000_PIC_OFFSET_TABLE_REGNUM]) |
8500 | regs_ever_live[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1; | |
1ff7789b | 8501 | |
8d30c4ee | 8502 | current_function_uses_pic_offset_table = 1; |
3cb999d8 | 8503 | |
1ff7789b MM |
8504 | return pic_offset_table_rtx; |
8505 | } | |
a7df97e6 | 8506 | \f |
e2500fed GK |
8507 | /* Function to init struct machine_function. |
8508 | This will be called, via a pointer variable, | |
8509 | from push_function_context. */ | |
a7df97e6 | 8510 | |
e2500fed | 8511 | static struct machine_function * |
863d938c | 8512 | rs6000_init_machine_status (void) |
a7df97e6 | 8513 | { |
e2500fed | 8514 | return ggc_alloc_cleared (sizeof (machine_function)); |
a7df97e6 | 8515 | } |
9878760c | 8516 | \f |
0ba1b2ff AM |
8517 | /* These macros test for integers and extract the low-order bits. */ |
8518 | #define INT_P(X) \ | |
8519 | ((GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST_DOUBLE) \ | |
8520 | && GET_MODE (X) == VOIDmode) | |
8521 | ||
8522 | #define INT_LOWPART(X) \ | |
8523 | (GET_CODE (X) == CONST_INT ? INTVAL (X) : CONST_DOUBLE_LOW (X)) | |
8524 | ||
8525 | int | |
a2369ed3 | 8526 | extract_MB (rtx op) |
0ba1b2ff AM |
8527 | { |
8528 | int i; | |
8529 | unsigned long val = INT_LOWPART (op); | |
8530 | ||
8531 | /* If the high bit is zero, the value is the first 1 bit we find | |
8532 | from the left. */ | |
8533 | if ((val & 0x80000000) == 0) | |
8534 | { | |
8535 | if ((val & 0xffffffff) == 0) | |
8536 | abort (); | |
8537 | ||
8538 | i = 1; | |
8539 | while (((val <<= 1) & 0x80000000) == 0) | |
8540 | ++i; | |
8541 | return i; | |
8542 | } | |
8543 | ||
8544 | /* If the high bit is set and the low bit is not, or the mask is all | |
8545 | 1's, the value is zero. */ | |
8546 | if ((val & 1) == 0 || (val & 0xffffffff) == 0xffffffff) | |
8547 | return 0; | |
8548 | ||
8549 | /* Otherwise we have a wrap-around mask. Look for the first 0 bit | |
8550 | from the right. */ | |
8551 | i = 31; | |
8552 | while (((val >>= 1) & 1) != 0) | |
8553 | --i; | |
8554 | ||
8555 | return i; | |
8556 | } | |
8557 | ||
8558 | int | |
a2369ed3 | 8559 | extract_ME (rtx op) |
0ba1b2ff AM |
8560 | { |
8561 | int i; | |
8562 | unsigned long val = INT_LOWPART (op); | |
8563 | ||
8564 | /* If the low bit is zero, the value is the first 1 bit we find from | |
8565 | the right. */ | |
8566 | if ((val & 1) == 0) | |
8567 | { | |
8568 | if ((val & 0xffffffff) == 0) | |
8569 | abort (); | |
8570 | ||
8571 | i = 30; | |
8572 | while (((val >>= 1) & 1) == 0) | |
8573 | --i; | |
8574 | ||
8575 | return i; | |
8576 | } | |
8577 | ||
8578 | /* If the low bit is set and the high bit is not, or the mask is all | |
8579 | 1's, the value is 31. */ | |
8580 | if ((val & 0x80000000) == 0 || (val & 0xffffffff) == 0xffffffff) | |
8581 | return 31; | |
8582 | ||
8583 | /* Otherwise we have a wrap-around mask. Look for the first 0 bit | |
8584 | from the left. */ | |
8585 | i = 0; | |
8586 | while (((val <<= 1) & 0x80000000) != 0) | |
8587 | ++i; | |
8588 | ||
8589 | return i; | |
8590 | } | |
8591 | ||
c4501e62 JJ |
8592 | /* Locate some local-dynamic symbol still in use by this function |
8593 | so that we can print its name in some tls_ld pattern. */ | |
8594 | ||
8595 | static const char * | |
863d938c | 8596 | rs6000_get_some_local_dynamic_name (void) |
c4501e62 JJ |
8597 | { |
8598 | rtx insn; | |
8599 | ||
8600 | if (cfun->machine->some_ld_name) | |
8601 | return cfun->machine->some_ld_name; | |
8602 | ||
8603 | for (insn = get_insns (); insn ; insn = NEXT_INSN (insn)) | |
8604 | if (INSN_P (insn) | |
8605 | && for_each_rtx (&PATTERN (insn), | |
8606 | rs6000_get_some_local_dynamic_name_1, 0)) | |
8607 | return cfun->machine->some_ld_name; | |
8608 | ||
8609 | abort (); | |
8610 | } | |
8611 | ||
8612 | /* Helper function for rs6000_get_some_local_dynamic_name. */ | |
8613 | ||
8614 | static int | |
a2369ed3 | 8615 | rs6000_get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED) |
c4501e62 JJ |
8616 | { |
8617 | rtx x = *px; | |
8618 | ||
8619 | if (GET_CODE (x) == SYMBOL_REF) | |
8620 | { | |
8621 | const char *str = XSTR (x, 0); | |
8622 | if (SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC) | |
8623 | { | |
8624 | cfun->machine->some_ld_name = str; | |
8625 | return 1; | |
8626 | } | |
8627 | } | |
8628 | ||
8629 | return 0; | |
8630 | } | |
8631 | ||
9878760c RK |
8632 | /* Print an operand. Recognize special options, documented below. */ |
8633 | ||
38c1f2d7 | 8634 | #if TARGET_ELF |
d9407988 | 8635 | #define SMALL_DATA_RELOC ((rs6000_sdata == SDATA_EABI) ? "sda21" : "sdarel") |
8fbd2dc7 | 8636 | #define SMALL_DATA_REG ((rs6000_sdata == SDATA_EABI) ? 0 : 13) |
ba5e43aa MM |
8637 | #else |
8638 | #define SMALL_DATA_RELOC "sda21" | |
8fbd2dc7 | 8639 | #define SMALL_DATA_REG 0 |
ba5e43aa MM |
8640 | #endif |
8641 | ||
9878760c | 8642 | void |
a2369ed3 | 8643 | print_operand (FILE *file, rtx x, int code) |
9878760c RK |
8644 | { |
8645 | int i; | |
a260abc9 | 8646 | HOST_WIDE_INT val; |
0ba1b2ff | 8647 | unsigned HOST_WIDE_INT uval; |
9878760c RK |
8648 | |
8649 | switch (code) | |
8650 | { | |
a8b3aeda | 8651 | case '.': |
a85d226b RK |
8652 | /* Write out an instruction after the call which may be replaced |
8653 | with glue code by the loader. This depends on the AIX version. */ | |
8654 | asm_fprintf (file, RS6000_CALL_GLUE); | |
a8b3aeda RK |
8655 | return; |
8656 | ||
81eace42 GK |
8657 | /* %a is output_address. */ |
8658 | ||
9854d9ed RK |
8659 | case 'A': |
8660 | /* If X is a constant integer whose low-order 5 bits are zero, | |
8661 | write 'l'. Otherwise, write 'r'. This is a kludge to fix a bug | |
76229ac8 | 8662 | in the AIX assembler where "sri" with a zero shift count |
20e26713 | 8663 | writes a trash instruction. */ |
9854d9ed | 8664 | if (GET_CODE (x) == CONST_INT && (INTVAL (x) & 31) == 0) |
76229ac8 | 8665 | putc ('l', file); |
9854d9ed | 8666 | else |
76229ac8 | 8667 | putc ('r', file); |
9854d9ed RK |
8668 | return; |
8669 | ||
8670 | case 'b': | |
e2c953b6 DE |
8671 | /* If constant, low-order 16 bits of constant, unsigned. |
8672 | Otherwise, write normally. */ | |
8673 | if (INT_P (x)) | |
8674 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 0xffff); | |
8675 | else | |
8676 | print_operand (file, x, 0); | |
cad12a8d RK |
8677 | return; |
8678 | ||
a260abc9 DE |
8679 | case 'B': |
8680 | /* If the low-order bit is zero, write 'r'; otherwise, write 'l' | |
8681 | for 64-bit mask direction. */ | |
296b8152 | 8682 | putc (((INT_LOWPART(x) & 1) == 0 ? 'r' : 'l'), file); |
a238cd8b | 8683 | return; |
a260abc9 | 8684 | |
81eace42 GK |
8685 | /* %c is output_addr_const if a CONSTANT_ADDRESS_P, otherwise |
8686 | output_operand. */ | |
8687 | ||
9854d9ed | 8688 | case 'E': |
39a10a29 | 8689 | /* X is a CR register. Print the number of the EQ bit of the CR */ |
9854d9ed RK |
8690 | if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x))) |
8691 | output_operand_lossage ("invalid %%E value"); | |
78fbdbf7 | 8692 | else |
39a10a29 | 8693 | fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO) + 2); |
a85d226b | 8694 | return; |
9854d9ed RK |
8695 | |
8696 | case 'f': | |
8697 | /* X is a CR register. Print the shift count needed to move it | |
8698 | to the high-order four bits. */ | |
8699 | if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x))) | |
8700 | output_operand_lossage ("invalid %%f value"); | |
8701 | else | |
9ebbca7d | 8702 | fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO)); |
9854d9ed RK |
8703 | return; |
8704 | ||
8705 | case 'F': | |
8706 | /* Similar, but print the count for the rotate in the opposite | |
8707 | direction. */ | |
8708 | if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x))) | |
8709 | output_operand_lossage ("invalid %%F value"); | |
8710 | else | |
9ebbca7d | 8711 | fprintf (file, "%d", 32 - 4 * (REGNO (x) - CR0_REGNO)); |
9854d9ed RK |
8712 | return; |
8713 | ||
8714 | case 'G': | |
8715 | /* X is a constant integer. If it is negative, print "m", | |
43aa4e05 | 8716 | otherwise print "z". This is to make an aze or ame insn. */ |
9854d9ed RK |
8717 | if (GET_CODE (x) != CONST_INT) |
8718 | output_operand_lossage ("invalid %%G value"); | |
8719 | else if (INTVAL (x) >= 0) | |
76229ac8 | 8720 | putc ('z', file); |
9854d9ed | 8721 | else |
76229ac8 | 8722 | putc ('m', file); |
9854d9ed | 8723 | return; |
e2c953b6 | 8724 | |
9878760c | 8725 | case 'h': |
a4f6c312 SS |
8726 | /* If constant, output low-order five bits. Otherwise, write |
8727 | normally. */ | |
9878760c | 8728 | if (INT_P (x)) |
5f59ecb7 | 8729 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 31); |
9878760c RK |
8730 | else |
8731 | print_operand (file, x, 0); | |
8732 | return; | |
8733 | ||
64305719 | 8734 | case 'H': |
a4f6c312 SS |
8735 | /* If constant, output low-order six bits. Otherwise, write |
8736 | normally. */ | |
64305719 | 8737 | if (INT_P (x)) |
5f59ecb7 | 8738 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 63); |
64305719 DE |
8739 | else |
8740 | print_operand (file, x, 0); | |
8741 | return; | |
8742 | ||
9854d9ed RK |
8743 | case 'I': |
8744 | /* Print `i' if this is a constant, else nothing. */ | |
9878760c | 8745 | if (INT_P (x)) |
76229ac8 | 8746 | putc ('i', file); |
9878760c RK |
8747 | return; |
8748 | ||
9854d9ed RK |
8749 | case 'j': |
8750 | /* Write the bit number in CCR for jump. */ | |
8751 | i = ccr_bit (x, 0); | |
8752 | if (i == -1) | |
8753 | output_operand_lossage ("invalid %%j code"); | |
9878760c | 8754 | else |
9854d9ed | 8755 | fprintf (file, "%d", i); |
9878760c RK |
8756 | return; |
8757 | ||
9854d9ed RK |
8758 | case 'J': |
8759 | /* Similar, but add one for shift count in rlinm for scc and pass | |
8760 | scc flag to `ccr_bit'. */ | |
8761 | i = ccr_bit (x, 1); | |
8762 | if (i == -1) | |
8763 | output_operand_lossage ("invalid %%J code"); | |
8764 | else | |
a0466a68 RK |
8765 | /* If we want bit 31, write a shift count of zero, not 32. */ |
8766 | fprintf (file, "%d", i == 31 ? 0 : i + 1); | |
9878760c RK |
8767 | return; |
8768 | ||
9854d9ed RK |
8769 | case 'k': |
8770 | /* X must be a constant. Write the 1's complement of the | |
8771 | constant. */ | |
9878760c | 8772 | if (! INT_P (x)) |
9854d9ed | 8773 | output_operand_lossage ("invalid %%k value"); |
e2c953b6 DE |
8774 | else |
8775 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, ~ INT_LOWPART (x)); | |
9878760c RK |
8776 | return; |
8777 | ||
81eace42 | 8778 | case 'K': |
9ebbca7d GK |
8779 | /* X must be a symbolic constant on ELF. Write an |
8780 | expression suitable for an 'addi' that adds in the low 16 | |
8781 | bits of the MEM. */ | |
8782 | if (GET_CODE (x) != CONST) | |
8783 | { | |
8784 | print_operand_address (file, x); | |
8785 | fputs ("@l", file); | |
8786 | } | |
8787 | else | |
8788 | { | |
8789 | if (GET_CODE (XEXP (x, 0)) != PLUS | |
8790 | || (GET_CODE (XEXP (XEXP (x, 0), 0)) != SYMBOL_REF | |
8791 | && GET_CODE (XEXP (XEXP (x, 0), 0)) != LABEL_REF) | |
8792 | || GET_CODE (XEXP (XEXP (x, 0), 1)) != CONST_INT) | |
53cd5d6c | 8793 | output_operand_lossage ("invalid %%K value"); |
9ebbca7d GK |
8794 | print_operand_address (file, XEXP (XEXP (x, 0), 0)); |
8795 | fputs ("@l", file); | |
ed8d2920 MM |
8796 | /* For GNU as, there must be a non-alphanumeric character |
8797 | between 'l' and the number. The '-' is added by | |
8798 | print_operand() already. */ | |
8799 | if (INTVAL (XEXP (XEXP (x, 0), 1)) >= 0) | |
8800 | fputs ("+", file); | |
9ebbca7d GK |
8801 | print_operand (file, XEXP (XEXP (x, 0), 1), 0); |
8802 | } | |
81eace42 GK |
8803 | return; |
8804 | ||
8805 | /* %l is output_asm_label. */ | |
9ebbca7d | 8806 | |
9854d9ed RK |
8807 | case 'L': |
8808 | /* Write second word of DImode or DFmode reference. Works on register | |
8809 | or non-indexed memory only. */ | |
8810 | if (GET_CODE (x) == REG) | |
5ebfb2ba | 8811 | fprintf (file, "%s", reg_names[REGNO (x) + 1]); |
9854d9ed RK |
8812 | else if (GET_CODE (x) == MEM) |
8813 | { | |
8814 | /* Handle possible auto-increment. Since it is pre-increment and | |
1427100a | 8815 | we have already done it, we can just use an offset of word. */ |
9854d9ed RK |
8816 | if (GET_CODE (XEXP (x, 0)) == PRE_INC |
8817 | || GET_CODE (XEXP (x, 0)) == PRE_DEC) | |
ed8908e7 RK |
8818 | output_address (plus_constant (XEXP (XEXP (x, 0), 0), |
8819 | UNITS_PER_WORD)); | |
9854d9ed | 8820 | else |
d7624dc0 RK |
8821 | output_address (XEXP (adjust_address_nv (x, SImode, |
8822 | UNITS_PER_WORD), | |
8823 | 0)); | |
ed8908e7 | 8824 | |
ba5e43aa | 8825 | if (small_data_operand (x, GET_MODE (x))) |
8fbd2dc7 MM |
8826 | fprintf (file, "@%s(%s)", SMALL_DATA_RELOC, |
8827 | reg_names[SMALL_DATA_REG]); | |
9854d9ed | 8828 | } |
9878760c | 8829 | return; |
9854d9ed | 8830 | |
9878760c RK |
8831 | case 'm': |
8832 | /* MB value for a mask operand. */ | |
b1765bde | 8833 | if (! mask_operand (x, SImode)) |
9878760c RK |
8834 | output_operand_lossage ("invalid %%m value"); |
8835 | ||
0ba1b2ff | 8836 | fprintf (file, "%d", extract_MB (x)); |
9878760c RK |
8837 | return; |
8838 | ||
8839 | case 'M': | |
8840 | /* ME value for a mask operand. */ | |
b1765bde | 8841 | if (! mask_operand (x, SImode)) |
a260abc9 | 8842 | output_operand_lossage ("invalid %%M value"); |
9878760c | 8843 | |
0ba1b2ff | 8844 | fprintf (file, "%d", extract_ME (x)); |
9878760c RK |
8845 | return; |
8846 | ||
81eace42 GK |
8847 | /* %n outputs the negative of its operand. */ |
8848 | ||
9878760c RK |
8849 | case 'N': |
8850 | /* Write the number of elements in the vector times 4. */ | |
8851 | if (GET_CODE (x) != PARALLEL) | |
8852 | output_operand_lossage ("invalid %%N value"); | |
e2c953b6 DE |
8853 | else |
8854 | fprintf (file, "%d", XVECLEN (x, 0) * 4); | |
9878760c RK |
8855 | return; |
8856 | ||
8857 | case 'O': | |
8858 | /* Similar, but subtract 1 first. */ | |
8859 | if (GET_CODE (x) != PARALLEL) | |
1427100a | 8860 | output_operand_lossage ("invalid %%O value"); |
e2c953b6 DE |
8861 | else |
8862 | fprintf (file, "%d", (XVECLEN (x, 0) - 1) * 4); | |
9878760c RK |
8863 | return; |
8864 | ||
9854d9ed RK |
8865 | case 'p': |
8866 | /* X is a CONST_INT that is a power of two. Output the logarithm. */ | |
8867 | if (! INT_P (x) | |
2bfcf297 | 8868 | || INT_LOWPART (x) < 0 |
9854d9ed RK |
8869 | || (i = exact_log2 (INT_LOWPART (x))) < 0) |
8870 | output_operand_lossage ("invalid %%p value"); | |
e2c953b6 DE |
8871 | else |
8872 | fprintf (file, "%d", i); | |
9854d9ed RK |
8873 | return; |
8874 | ||
9878760c RK |
8875 | case 'P': |
8876 | /* The operand must be an indirect memory reference. The result | |
a4f6c312 | 8877 | is the register number. */ |
9878760c RK |
8878 | if (GET_CODE (x) != MEM || GET_CODE (XEXP (x, 0)) != REG |
8879 | || REGNO (XEXP (x, 0)) >= 32) | |
8880 | output_operand_lossage ("invalid %%P value"); | |
e2c953b6 DE |
8881 | else |
8882 | fprintf (file, "%d", REGNO (XEXP (x, 0))); | |
9878760c RK |
8883 | return; |
8884 | ||
dfbdccdb GK |
8885 | case 'q': |
8886 | /* This outputs the logical code corresponding to a boolean | |
8887 | expression. The expression may have one or both operands | |
39a10a29 GK |
8888 | negated (if one, only the first one). For condition register |
8889 | logical operations, it will also treat the negated | |
8890 | CR codes as NOTs, but not handle NOTs of them. */ | |
dfbdccdb | 8891 | { |
63bc1d05 | 8892 | const char *const *t = 0; |
dfbdccdb GK |
8893 | const char *s; |
8894 | enum rtx_code code = GET_CODE (x); | |
8895 | static const char * const tbl[3][3] = { | |
8896 | { "and", "andc", "nor" }, | |
8897 | { "or", "orc", "nand" }, | |
8898 | { "xor", "eqv", "xor" } }; | |
8899 | ||
8900 | if (code == AND) | |
8901 | t = tbl[0]; | |
8902 | else if (code == IOR) | |
8903 | t = tbl[1]; | |
8904 | else if (code == XOR) | |
8905 | t = tbl[2]; | |
8906 | else | |
8907 | output_operand_lossage ("invalid %%q value"); | |
8908 | ||
8909 | if (GET_CODE (XEXP (x, 0)) != NOT) | |
8910 | s = t[0]; | |
8911 | else | |
8912 | { | |
8913 | if (GET_CODE (XEXP (x, 1)) == NOT) | |
8914 | s = t[2]; | |
8915 | else | |
8916 | s = t[1]; | |
8917 | } | |
8918 | ||
8919 | fputs (s, file); | |
8920 | } | |
8921 | return; | |
8922 | ||
2c4a9cff DE |
8923 | case 'Q': |
8924 | if (TARGET_MFCRF) | |
8925 | fputc (',',file); | |
5efb1046 | 8926 | /* FALLTHRU */ |
2c4a9cff DE |
8927 | else |
8928 | return; | |
8929 | ||
9854d9ed RK |
8930 | case 'R': |
8931 | /* X is a CR register. Print the mask for `mtcrf'. */ | |
8932 | if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x))) | |
8933 | output_operand_lossage ("invalid %%R value"); | |
8934 | else | |
9ebbca7d | 8935 | fprintf (file, "%d", 128 >> (REGNO (x) - CR0_REGNO)); |
9878760c | 8936 | return; |
9854d9ed RK |
8937 | |
8938 | case 's': | |
8939 | /* Low 5 bits of 32 - value */ | |
8940 | if (! INT_P (x)) | |
8941 | output_operand_lossage ("invalid %%s value"); | |
e2c953b6 DE |
8942 | else |
8943 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, (32 - INT_LOWPART (x)) & 31); | |
9878760c | 8944 | return; |
9854d9ed | 8945 | |
a260abc9 | 8946 | case 'S': |
0ba1b2ff | 8947 | /* PowerPC64 mask position. All 0's is excluded. |
a260abc9 DE |
8948 | CONST_INT 32-bit mask is considered sign-extended so any |
8949 | transition must occur within the CONST_INT, not on the boundary. */ | |
b1765bde | 8950 | if (! mask64_operand (x, DImode)) |
a260abc9 DE |
8951 | output_operand_lossage ("invalid %%S value"); |
8952 | ||
0ba1b2ff | 8953 | uval = INT_LOWPART (x); |
a260abc9 | 8954 | |
0ba1b2ff | 8955 | if (uval & 1) /* Clear Left */ |
a260abc9 | 8956 | { |
f099d360 GK |
8957 | #if HOST_BITS_PER_WIDE_INT > 64 |
8958 | uval &= ((unsigned HOST_WIDE_INT) 1 << 64) - 1; | |
8959 | #endif | |
0ba1b2ff | 8960 | i = 64; |
a260abc9 | 8961 | } |
0ba1b2ff | 8962 | else /* Clear Right */ |
a260abc9 | 8963 | { |
0ba1b2ff | 8964 | uval = ~uval; |
f099d360 GK |
8965 | #if HOST_BITS_PER_WIDE_INT > 64 |
8966 | uval &= ((unsigned HOST_WIDE_INT) 1 << 64) - 1; | |
8967 | #endif | |
0ba1b2ff | 8968 | i = 63; |
a260abc9 | 8969 | } |
0ba1b2ff AM |
8970 | while (uval != 0) |
8971 | --i, uval >>= 1; | |
8972 | if (i < 0) | |
8973 | abort (); | |
8974 | fprintf (file, "%d", i); | |
8975 | return; | |
a260abc9 | 8976 | |
a3170dc6 AH |
8977 | case 't': |
8978 | /* Like 'J' but get to the OVERFLOW/UNORDERED bit. */ | |
8979 | if (GET_CODE (x) != REG || GET_MODE (x) != CCmode) | |
8980 | abort (); | |
8981 | ||
8982 | /* Bit 3 is OV bit. */ | |
8983 | i = 4 * (REGNO (x) - CR0_REGNO) + 3; | |
8984 | ||
8985 | /* If we want bit 31, write a shift count of zero, not 32. */ | |
8986 | fprintf (file, "%d", i == 31 ? 0 : i + 1); | |
8987 | return; | |
8988 | ||
cccf3bdc DE |
8989 | case 'T': |
8990 | /* Print the symbolic name of a branch target register. */ | |
8991 | if (GET_CODE (x) != REG || (REGNO (x) != LINK_REGISTER_REGNUM | |
8992 | && REGNO (x) != COUNT_REGISTER_REGNUM)) | |
8993 | output_operand_lossage ("invalid %%T value"); | |
e2c953b6 | 8994 | else if (REGNO (x) == LINK_REGISTER_REGNUM) |
cccf3bdc DE |
8995 | fputs (TARGET_NEW_MNEMONICS ? "lr" : "r", file); |
8996 | else | |
8997 | fputs ("ctr", file); | |
8998 | return; | |
8999 | ||
9854d9ed | 9000 | case 'u': |
802a0058 | 9001 | /* High-order 16 bits of constant for use in unsigned operand. */ |
9854d9ed RK |
9002 | if (! INT_P (x)) |
9003 | output_operand_lossage ("invalid %%u value"); | |
e2c953b6 DE |
9004 | else |
9005 | fprintf (file, HOST_WIDE_INT_PRINT_HEX, | |
9006 | (INT_LOWPART (x) >> 16) & 0xffff); | |
9878760c RK |
9007 | return; |
9008 | ||
802a0058 MM |
9009 | case 'v': |
9010 | /* High-order 16 bits of constant for use in signed operand. */ | |
9011 | if (! INT_P (x)) | |
9012 | output_operand_lossage ("invalid %%v value"); | |
e2c953b6 | 9013 | else |
134c32f6 DE |
9014 | fprintf (file, HOST_WIDE_INT_PRINT_HEX, |
9015 | (INT_LOWPART (x) >> 16) & 0xffff); | |
9016 | return; | |
802a0058 | 9017 | |
9854d9ed RK |
9018 | case 'U': |
9019 | /* Print `u' if this has an auto-increment or auto-decrement. */ | |
9020 | if (GET_CODE (x) == MEM | |
9021 | && (GET_CODE (XEXP (x, 0)) == PRE_INC | |
9022 | || GET_CODE (XEXP (x, 0)) == PRE_DEC)) | |
76229ac8 | 9023 | putc ('u', file); |
9854d9ed | 9024 | return; |
9878760c | 9025 | |
e0cd0770 JC |
9026 | case 'V': |
9027 | /* Print the trap code for this operand. */ | |
9028 | switch (GET_CODE (x)) | |
9029 | { | |
9030 | case EQ: | |
9031 | fputs ("eq", file); /* 4 */ | |
9032 | break; | |
9033 | case NE: | |
9034 | fputs ("ne", file); /* 24 */ | |
9035 | break; | |
9036 | case LT: | |
9037 | fputs ("lt", file); /* 16 */ | |
9038 | break; | |
9039 | case LE: | |
9040 | fputs ("le", file); /* 20 */ | |
9041 | break; | |
9042 | case GT: | |
9043 | fputs ("gt", file); /* 8 */ | |
9044 | break; | |
9045 | case GE: | |
9046 | fputs ("ge", file); /* 12 */ | |
9047 | break; | |
9048 | case LTU: | |
9049 | fputs ("llt", file); /* 2 */ | |
9050 | break; | |
9051 | case LEU: | |
9052 | fputs ("lle", file); /* 6 */ | |
9053 | break; | |
9054 | case GTU: | |
9055 | fputs ("lgt", file); /* 1 */ | |
9056 | break; | |
9057 | case GEU: | |
9058 | fputs ("lge", file); /* 5 */ | |
9059 | break; | |
9060 | default: | |
9061 | abort (); | |
9062 | } | |
9063 | break; | |
9064 | ||
9854d9ed RK |
9065 | case 'w': |
9066 | /* If constant, low-order 16 bits of constant, signed. Otherwise, write | |
9067 | normally. */ | |
9068 | if (INT_P (x)) | |
5f59ecb7 DE |
9069 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, |
9070 | ((INT_LOWPART (x) & 0xffff) ^ 0x8000) - 0x8000); | |
9854d9ed RK |
9071 | else |
9072 | print_operand (file, x, 0); | |
9878760c RK |
9073 | return; |
9074 | ||
9854d9ed | 9075 | case 'W': |
e2c953b6 | 9076 | /* MB value for a PowerPC64 rldic operand. */ |
e2c953b6 DE |
9077 | val = (GET_CODE (x) == CONST_INT |
9078 | ? INTVAL (x) : CONST_DOUBLE_HIGH (x)); | |
9079 | ||
9080 | if (val < 0) | |
9081 | i = -1; | |
9854d9ed | 9082 | else |
e2c953b6 DE |
9083 | for (i = 0; i < HOST_BITS_PER_WIDE_INT; i++) |
9084 | if ((val <<= 1) < 0) | |
9085 | break; | |
9086 | ||
9087 | #if HOST_BITS_PER_WIDE_INT == 32 | |
9088 | if (GET_CODE (x) == CONST_INT && i >= 0) | |
9089 | i += 32; /* zero-extend high-part was all 0's */ | |
9090 | else if (GET_CODE (x) == CONST_DOUBLE && i == 32) | |
9091 | { | |
9092 | val = CONST_DOUBLE_LOW (x); | |
9093 | ||
9094 | if (val == 0) | |
a4f6c312 | 9095 | abort (); |
e2c953b6 DE |
9096 | else if (val < 0) |
9097 | --i; | |
9098 | else | |
9099 | for ( ; i < 64; i++) | |
9100 | if ((val <<= 1) < 0) | |
9101 | break; | |
9102 | } | |
9103 | #endif | |
9104 | ||
9105 | fprintf (file, "%d", i + 1); | |
9854d9ed | 9106 | return; |
9878760c | 9107 | |
9854d9ed RK |
9108 | case 'X': |
9109 | if (GET_CODE (x) == MEM | |
4d588c14 | 9110 | && legitimate_indexed_address_p (XEXP (x, 0), 0)) |
76229ac8 | 9111 | putc ('x', file); |
9854d9ed | 9112 | return; |
9878760c | 9113 | |
9854d9ed RK |
9114 | case 'Y': |
9115 | /* Like 'L', for third word of TImode */ | |
9116 | if (GET_CODE (x) == REG) | |
5ebfb2ba | 9117 | fprintf (file, "%s", reg_names[REGNO (x) + 2]); |
9854d9ed | 9118 | else if (GET_CODE (x) == MEM) |
9878760c | 9119 | { |
9854d9ed RK |
9120 | if (GET_CODE (XEXP (x, 0)) == PRE_INC |
9121 | || GET_CODE (XEXP (x, 0)) == PRE_DEC) | |
a54d04b7 | 9122 | output_address (plus_constant (XEXP (XEXP (x, 0), 0), 8)); |
9854d9ed | 9123 | else |
d7624dc0 | 9124 | output_address (XEXP (adjust_address_nv (x, SImode, 8), 0)); |
ba5e43aa | 9125 | if (small_data_operand (x, GET_MODE (x))) |
8fbd2dc7 MM |
9126 | fprintf (file, "@%s(%s)", SMALL_DATA_RELOC, |
9127 | reg_names[SMALL_DATA_REG]); | |
9878760c RK |
9128 | } |
9129 | return; | |
9854d9ed | 9130 | |
9878760c | 9131 | case 'z': |
b4ac57ab RS |
9132 | /* X is a SYMBOL_REF. Write out the name preceded by a |
9133 | period and without any trailing data in brackets. Used for function | |
4d30c363 MM |
9134 | names. If we are configured for System V (or the embedded ABI) on |
9135 | the PowerPC, do not emit the period, since those systems do not use | |
9136 | TOCs and the like. */ | |
9878760c RK |
9137 | if (GET_CODE (x) != SYMBOL_REF) |
9138 | abort (); | |
9139 | ||
b6c9286a MM |
9140 | if (XSTR (x, 0)[0] != '.') |
9141 | { | |
9142 | switch (DEFAULT_ABI) | |
9143 | { | |
9144 | default: | |
9145 | abort (); | |
9146 | ||
9147 | case ABI_AIX: | |
9148 | putc ('.', file); | |
9149 | break; | |
9150 | ||
9151 | case ABI_V4: | |
ee890fe2 | 9152 | case ABI_DARWIN: |
b6c9286a | 9153 | break; |
b6c9286a MM |
9154 | } |
9155 | } | |
9739c90c JJ |
9156 | if (TARGET_AIX) |
9157 | RS6000_OUTPUT_BASENAME (file, XSTR (x, 0)); | |
9158 | else | |
9159 | assemble_name (file, XSTR (x, 0)); | |
9878760c RK |
9160 | return; |
9161 | ||
9854d9ed RK |
9162 | case 'Z': |
9163 | /* Like 'L', for last word of TImode. */ | |
9164 | if (GET_CODE (x) == REG) | |
5ebfb2ba | 9165 | fprintf (file, "%s", reg_names[REGNO (x) + 3]); |
9854d9ed RK |
9166 | else if (GET_CODE (x) == MEM) |
9167 | { | |
9168 | if (GET_CODE (XEXP (x, 0)) == PRE_INC | |
9169 | || GET_CODE (XEXP (x, 0)) == PRE_DEC) | |
a54d04b7 | 9170 | output_address (plus_constant (XEXP (XEXP (x, 0), 0), 12)); |
9854d9ed | 9171 | else |
d7624dc0 | 9172 | output_address (XEXP (adjust_address_nv (x, SImode, 12), 0)); |
ba5e43aa | 9173 | if (small_data_operand (x, GET_MODE (x))) |
8fbd2dc7 MM |
9174 | fprintf (file, "@%s(%s)", SMALL_DATA_RELOC, |
9175 | reg_names[SMALL_DATA_REG]); | |
9854d9ed | 9176 | } |
5c23c401 | 9177 | return; |
0ac081f6 | 9178 | |
a3170dc6 | 9179 | /* Print AltiVec or SPE memory operand. */ |
0ac081f6 AH |
9180 | case 'y': |
9181 | { | |
9182 | rtx tmp; | |
9183 | ||
9184 | if (GET_CODE (x) != MEM) | |
9185 | abort (); | |
9186 | ||
9187 | tmp = XEXP (x, 0); | |
9188 | ||
993f19a8 | 9189 | if (TARGET_E500) |
a3170dc6 AH |
9190 | { |
9191 | /* Handle [reg]. */ | |
9192 | if (GET_CODE (tmp) == REG) | |
9193 | { | |
9194 | fprintf (file, "0(%s)", reg_names[REGNO (tmp)]); | |
9195 | break; | |
9196 | } | |
9197 | /* Handle [reg+UIMM]. */ | |
9198 | else if (GET_CODE (tmp) == PLUS && | |
9199 | GET_CODE (XEXP (tmp, 1)) == CONST_INT) | |
9200 | { | |
9201 | int x; | |
9202 | ||
9203 | if (GET_CODE (XEXP (tmp, 0)) != REG) | |
9204 | abort (); | |
9205 | ||
9206 | x = INTVAL (XEXP (tmp, 1)); | |
9207 | fprintf (file, "%d(%s)", x, reg_names[REGNO (XEXP (tmp, 0))]); | |
9208 | break; | |
9209 | } | |
9210 | ||
9211 | /* Fall through. Must be [reg+reg]. */ | |
9212 | } | |
0ac081f6 | 9213 | if (GET_CODE (tmp) == REG) |
c62f2db5 | 9214 | fprintf (file, "0,%s", reg_names[REGNO (tmp)]); |
0ac081f6 AH |
9215 | else if (GET_CODE (tmp) == PLUS && GET_CODE (XEXP (tmp, 1)) == REG) |
9216 | { | |
9217 | if (REGNO (XEXP (tmp, 0)) == 0) | |
9218 | fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 1)) ], | |
9219 | reg_names[ REGNO (XEXP (tmp, 0)) ]); | |
9220 | else | |
9221 | fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 0)) ], | |
9222 | reg_names[ REGNO (XEXP (tmp, 1)) ]); | |
9223 | } | |
9224 | else | |
9225 | abort (); | |
9226 | break; | |
9227 | } | |
9854d9ed | 9228 | |
9878760c RK |
9229 | case 0: |
9230 | if (GET_CODE (x) == REG) | |
9231 | fprintf (file, "%s", reg_names[REGNO (x)]); | |
9232 | else if (GET_CODE (x) == MEM) | |
9233 | { | |
9234 | /* We need to handle PRE_INC and PRE_DEC here, since we need to | |
9235 | know the width from the mode. */ | |
9236 | if (GET_CODE (XEXP (x, 0)) == PRE_INC) | |
79ba6d34 MM |
9237 | fprintf (file, "%d(%s)", GET_MODE_SIZE (GET_MODE (x)), |
9238 | reg_names[REGNO (XEXP (XEXP (x, 0), 0))]); | |
9878760c | 9239 | else if (GET_CODE (XEXP (x, 0)) == PRE_DEC) |
79ba6d34 MM |
9240 | fprintf (file, "%d(%s)", - GET_MODE_SIZE (GET_MODE (x)), |
9241 | reg_names[REGNO (XEXP (XEXP (x, 0), 0))]); | |
9878760c | 9242 | else |
a54d04b7 | 9243 | output_address (XEXP (x, 0)); |
9878760c RK |
9244 | } |
9245 | else | |
a54d04b7 | 9246 | output_addr_const (file, x); |
a85d226b | 9247 | return; |
9878760c | 9248 | |
c4501e62 JJ |
9249 | case '&': |
9250 | assemble_name (file, rs6000_get_some_local_dynamic_name ()); | |
9251 | return; | |
9252 | ||
9878760c RK |
9253 | default: |
9254 | output_operand_lossage ("invalid %%xn code"); | |
9255 | } | |
9256 | } | |
9257 | \f | |
9258 | /* Print the address of an operand. */ | |
9259 | ||
9260 | void | |
a2369ed3 | 9261 | print_operand_address (FILE *file, rtx x) |
9878760c RK |
9262 | { |
9263 | if (GET_CODE (x) == REG) | |
4697a36c | 9264 | fprintf (file, "0(%s)", reg_names[ REGNO (x) ]); |
9ebbca7d GK |
9265 | else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST |
9266 | || GET_CODE (x) == LABEL_REF) | |
9878760c RK |
9267 | { |
9268 | output_addr_const (file, x); | |
ba5e43aa | 9269 | if (small_data_operand (x, GET_MODE (x))) |
8fbd2dc7 MM |
9270 | fprintf (file, "@%s(%s)", SMALL_DATA_RELOC, |
9271 | reg_names[SMALL_DATA_REG]); | |
9ebbca7d | 9272 | else if (TARGET_TOC) |
a4f6c312 | 9273 | abort (); |
9878760c RK |
9274 | } |
9275 | else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == REG) | |
9276 | { | |
9277 | if (REGNO (XEXP (x, 0)) == 0) | |
4697a36c MM |
9278 | fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 1)) ], |
9279 | reg_names[ REGNO (XEXP (x, 0)) ]); | |
9878760c | 9280 | else |
4697a36c MM |
9281 | fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 0)) ], |
9282 | reg_names[ REGNO (XEXP (x, 1)) ]); | |
9878760c RK |
9283 | } |
9284 | else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT) | |
4a0a75dd KG |
9285 | fprintf (file, HOST_WIDE_INT_PRINT_DEC "(%s)", |
9286 | INTVAL (XEXP (x, 1)), reg_names[ REGNO (XEXP (x, 0)) ]); | |
3cb999d8 DE |
9287 | #if TARGET_ELF |
9288 | else if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 0)) == REG | |
9289 | && CONSTANT_P (XEXP (x, 1))) | |
4697a36c MM |
9290 | { |
9291 | output_addr_const (file, XEXP (x, 1)); | |
9292 | fprintf (file, "@l(%s)", reg_names[ REGNO (XEXP (x, 0)) ]); | |
9293 | } | |
c859cda6 DJ |
9294 | #endif |
9295 | #if TARGET_MACHO | |
9296 | else if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 0)) == REG | |
9297 | && CONSTANT_P (XEXP (x, 1))) | |
9298 | { | |
9299 | fprintf (file, "lo16("); | |
9300 | output_addr_const (file, XEXP (x, 1)); | |
9301 | fprintf (file, ")(%s)", reg_names[ REGNO (XEXP (x, 0)) ]); | |
9302 | } | |
3cb999d8 | 9303 | #endif |
4d588c14 | 9304 | else if (legitimate_constant_pool_address_p (x)) |
9ebbca7d | 9305 | { |
2bfcf297 | 9306 | if (TARGET_AIX && (!TARGET_ELF || !TARGET_MINIMAL_TOC)) |
9ebbca7d | 9307 | { |
2bfcf297 DB |
9308 | rtx contains_minus = XEXP (x, 1); |
9309 | rtx minus, symref; | |
9310 | const char *name; | |
9ebbca7d GK |
9311 | |
9312 | /* Find the (minus (sym) (toc)) buried in X, and temporarily | |
a4f6c312 | 9313 | turn it into (sym) for output_addr_const. */ |
9ebbca7d GK |
9314 | while (GET_CODE (XEXP (contains_minus, 0)) != MINUS) |
9315 | contains_minus = XEXP (contains_minus, 0); | |
9316 | ||
2bfcf297 DB |
9317 | minus = XEXP (contains_minus, 0); |
9318 | symref = XEXP (minus, 0); | |
9319 | XEXP (contains_minus, 0) = symref; | |
9320 | if (TARGET_ELF) | |
9321 | { | |
9322 | char *newname; | |
9323 | ||
9324 | name = XSTR (symref, 0); | |
9325 | newname = alloca (strlen (name) + sizeof ("@toc")); | |
9326 | strcpy (newname, name); | |
9327 | strcat (newname, "@toc"); | |
9328 | XSTR (symref, 0) = newname; | |
9329 | } | |
9330 | output_addr_const (file, XEXP (x, 1)); | |
9331 | if (TARGET_ELF) | |
9332 | XSTR (symref, 0) = name; | |
9ebbca7d GK |
9333 | XEXP (contains_minus, 0) = minus; |
9334 | } | |
9335 | else | |
9336 | output_addr_const (file, XEXP (x, 1)); | |
9337 | ||
9338 | fprintf (file, "(%s)", reg_names[REGNO (XEXP (x, 0))]); | |
9339 | } | |
9878760c RK |
9340 | else |
9341 | abort (); | |
9342 | } | |
9343 | \f | |
88cad84b | 9344 | /* Target hook for assembling integer objects. The PowerPC version has |
301d03af RS |
9345 | to handle fixup entries for relocatable code if RELOCATABLE_NEEDS_FIXUP |
9346 | is defined. It also needs to handle DI-mode objects on 64-bit | |
9347 | targets. */ | |
9348 | ||
9349 | static bool | |
a2369ed3 | 9350 | rs6000_assemble_integer (rtx x, unsigned int size, int aligned_p) |
301d03af RS |
9351 | { |
9352 | #ifdef RELOCATABLE_NEEDS_FIXUP | |
9353 | /* Special handling for SI values. */ | |
9354 | if (size == 4 && aligned_p) | |
9355 | { | |
a2369ed3 | 9356 | extern int in_toc_section (void); |
301d03af RS |
9357 | static int recurse = 0; |
9358 | ||
9359 | /* For -mrelocatable, we mark all addresses that need to be fixed up | |
9360 | in the .fixup section. */ | |
9361 | if (TARGET_RELOCATABLE | |
9362 | && !in_toc_section () | |
9363 | && !in_text_section () | |
9364 | && !recurse | |
9365 | && GET_CODE (x) != CONST_INT | |
9366 | && GET_CODE (x) != CONST_DOUBLE | |
9367 | && CONSTANT_P (x)) | |
9368 | { | |
9369 | char buf[256]; | |
9370 | ||
9371 | recurse = 1; | |
9372 | ASM_GENERATE_INTERNAL_LABEL (buf, "LCP", fixuplabelno); | |
9373 | fixuplabelno++; | |
9374 | ASM_OUTPUT_LABEL (asm_out_file, buf); | |
9375 | fprintf (asm_out_file, "\t.long\t("); | |
9376 | output_addr_const (asm_out_file, x); | |
9377 | fprintf (asm_out_file, ")@fixup\n"); | |
9378 | fprintf (asm_out_file, "\t.section\t\".fixup\",\"aw\"\n"); | |
9379 | ASM_OUTPUT_ALIGN (asm_out_file, 2); | |
9380 | fprintf (asm_out_file, "\t.long\t"); | |
9381 | assemble_name (asm_out_file, buf); | |
9382 | fprintf (asm_out_file, "\n\t.previous\n"); | |
9383 | recurse = 0; | |
9384 | return true; | |
9385 | } | |
9386 | /* Remove initial .'s to turn a -mcall-aixdesc function | |
9387 | address into the address of the descriptor, not the function | |
9388 | itself. */ | |
9389 | else if (GET_CODE (x) == SYMBOL_REF | |
9390 | && XSTR (x, 0)[0] == '.' | |
9391 | && DEFAULT_ABI == ABI_AIX) | |
9392 | { | |
9393 | const char *name = XSTR (x, 0); | |
9394 | while (*name == '.') | |
9395 | name++; | |
9396 | ||
9397 | fprintf (asm_out_file, "\t.long\t%s\n", name); | |
9398 | return true; | |
9399 | } | |
9400 | } | |
9401 | #endif /* RELOCATABLE_NEEDS_FIXUP */ | |
9402 | return default_assemble_integer (x, size, aligned_p); | |
9403 | } | |
93638d7a AM |
9404 | |
9405 | #ifdef HAVE_GAS_HIDDEN | |
9406 | /* Emit an assembler directive to set symbol visibility for DECL to | |
9407 | VISIBILITY_TYPE. */ | |
9408 | ||
5add3202 | 9409 | static void |
a2369ed3 | 9410 | rs6000_assemble_visibility (tree decl, int vis) |
93638d7a | 9411 | { |
93638d7a AM |
9412 | /* Functions need to have their entry point symbol visibility set as |
9413 | well as their descriptor symbol visibility. */ | |
9414 | if (DEFAULT_ABI == ABI_AIX && TREE_CODE (decl) == FUNCTION_DECL) | |
9415 | { | |
25fdb4dc RH |
9416 | static const char * const visibility_types[] = { |
9417 | NULL, "internal", "hidden", "protected" | |
9418 | }; | |
9419 | ||
9420 | const char *name, *type; | |
93638d7a AM |
9421 | |
9422 | name = ((* targetm.strip_name_encoding) | |
9423 | (IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl)))); | |
25fdb4dc | 9424 | type = visibility_types[vis]; |
93638d7a | 9425 | |
25fdb4dc RH |
9426 | fprintf (asm_out_file, "\t.%s\t%s\n", type, name); |
9427 | fprintf (asm_out_file, "\t.%s\t.%s\n", type, name); | |
93638d7a | 9428 | } |
25fdb4dc RH |
9429 | else |
9430 | default_assemble_visibility (decl, vis); | |
93638d7a AM |
9431 | } |
9432 | #endif | |
301d03af | 9433 | \f |
39a10a29 | 9434 | enum rtx_code |
a2369ed3 | 9435 | rs6000_reverse_condition (enum machine_mode mode, enum rtx_code code) |
39a10a29 GK |
9436 | { |
9437 | /* Reversal of FP compares takes care -- an ordered compare | |
9438 | becomes an unordered compare and vice versa. */ | |
bc9ec0e0 GK |
9439 | if (mode == CCFPmode |
9440 | && (!flag_finite_math_only | |
9441 | || code == UNLT || code == UNLE || code == UNGT || code == UNGE | |
9442 | || code == UNEQ || code == LTGT)) | |
bab6226b | 9443 | return reverse_condition_maybe_unordered (code); |
39a10a29 | 9444 | else |
bab6226b | 9445 | return reverse_condition (code); |
39a10a29 GK |
9446 | } |
9447 | ||
39a10a29 GK |
9448 | /* Generate a compare for CODE. Return a brand-new rtx that |
9449 | represents the result of the compare. */ | |
a4f6c312 | 9450 | |
39a10a29 | 9451 | static rtx |
a2369ed3 | 9452 | rs6000_generate_compare (enum rtx_code code) |
39a10a29 GK |
9453 | { |
9454 | enum machine_mode comp_mode; | |
9455 | rtx compare_result; | |
9456 | ||
9457 | if (rs6000_compare_fp_p) | |
9458 | comp_mode = CCFPmode; | |
9459 | else if (code == GTU || code == LTU | |
9460 | || code == GEU || code == LEU) | |
9461 | comp_mode = CCUNSmode; | |
9462 | else | |
9463 | comp_mode = CCmode; | |
9464 | ||
9465 | /* First, the compare. */ | |
9466 | compare_result = gen_reg_rtx (comp_mode); | |
a3170dc6 AH |
9467 | |
9468 | /* SPE FP compare instructions on the GPRs. Yuck! */ | |
993f19a8 AH |
9469 | if ((TARGET_E500 && !TARGET_FPRS && TARGET_HARD_FLOAT) |
9470 | && rs6000_compare_fp_p) | |
a3170dc6 AH |
9471 | { |
9472 | rtx cmp, or1, or2, or_result, compare_result2; | |
9473 | ||
9474 | switch (code) | |
9475 | { | |
9476 | case EQ: | |
9477 | case UNEQ: | |
9478 | case NE: | |
9479 | case LTGT: | |
bc9ec0e0 | 9480 | cmp = flag_finite_math_only |
a3170dc6 AH |
9481 | ? gen_tstsfeq_gpr (compare_result, rs6000_compare_op0, |
9482 | rs6000_compare_op1) | |
9483 | : gen_cmpsfeq_gpr (compare_result, rs6000_compare_op0, | |
9484 | rs6000_compare_op1); | |
9485 | break; | |
9486 | case GT: | |
9487 | case GTU: | |
9488 | case UNGT: | |
9489 | case UNGE: | |
9490 | case GE: | |
9491 | case GEU: | |
bc9ec0e0 | 9492 | cmp = flag_finite_math_only |
a3170dc6 AH |
9493 | ? gen_tstsfgt_gpr (compare_result, rs6000_compare_op0, |
9494 | rs6000_compare_op1) | |
9495 | : gen_cmpsfgt_gpr (compare_result, rs6000_compare_op0, | |
9496 | rs6000_compare_op1); | |
9497 | break; | |
9498 | case LT: | |
9499 | case LTU: | |
9500 | case UNLT: | |
9501 | case UNLE: | |
9502 | case LE: | |
9503 | case LEU: | |
bc9ec0e0 | 9504 | cmp = flag_finite_math_only |
a3170dc6 AH |
9505 | ? gen_tstsflt_gpr (compare_result, rs6000_compare_op0, |
9506 | rs6000_compare_op1) | |
9507 | : gen_cmpsflt_gpr (compare_result, rs6000_compare_op0, | |
9508 | rs6000_compare_op1); | |
9509 | break; | |
9510 | default: | |
9511 | abort (); | |
9512 | } | |
9513 | ||
9514 | /* Synthesize LE and GE from LT/GT || EQ. */ | |
9515 | if (code == LE || code == GE || code == LEU || code == GEU) | |
9516 | { | |
9517 | /* Synthesize GE/LE frome GT/LT || EQ. */ | |
9518 | ||
9519 | emit_insn (cmp); | |
9520 | ||
9521 | switch (code) | |
9522 | { | |
9523 | case LE: code = LT; break; | |
9524 | case GE: code = GT; break; | |
9525 | case LEU: code = LT; break; | |
9526 | case GEU: code = GT; break; | |
9527 | default: abort (); | |
9528 | } | |
9529 | ||
9530 | or1 = gen_reg_rtx (SImode); | |
9531 | or2 = gen_reg_rtx (SImode); | |
9532 | or_result = gen_reg_rtx (CCEQmode); | |
9533 | compare_result2 = gen_reg_rtx (CCFPmode); | |
9534 | ||
9535 | /* Do the EQ. */ | |
bc9ec0e0 | 9536 | cmp = flag_finite_math_only |
a3170dc6 AH |
9537 | ? gen_tstsfeq_gpr (compare_result2, rs6000_compare_op0, |
9538 | rs6000_compare_op1) | |
9539 | : gen_cmpsfeq_gpr (compare_result2, rs6000_compare_op0, | |
9540 | rs6000_compare_op1); | |
9541 | emit_insn (cmp); | |
9542 | ||
9543 | /* The MC8540 FP compare instructions set the CR bits | |
9544 | differently than other PPC compare instructions. For | |
9545 | that matter, there is no generic test instruction, but a | |
9546 | testgt, testlt, and testeq. For a true condition, bit 2 | |
9547 | is set (x1xx) in the CR. Following the traditional CR | |
9548 | values: | |
9549 | ||
9550 | LT GT EQ OV | |
9551 | bit3 bit2 bit1 bit0 | |
9552 | ||
9553 | ... bit 2 would be a GT CR alias, so later on we | |
b6d08ca1 | 9554 | look in the GT bits for the branch instructions. |
a3170dc6 AH |
9555 | However, we must be careful to emit correct RTL in |
9556 | the meantime, so optimizations don't get confused. */ | |
9557 | ||
f1c25d3b KH |
9558 | or1 = gen_rtx_NE (SImode, compare_result, const0_rtx); |
9559 | or2 = gen_rtx_NE (SImode, compare_result2, const0_rtx); | |
a3170dc6 AH |
9560 | |
9561 | /* OR them together. */ | |
9562 | cmp = gen_rtx_SET (VOIDmode, or_result, | |
9563 | gen_rtx_COMPARE (CCEQmode, | |
9564 | gen_rtx_IOR (SImode, or1, or2), | |
9565 | const_true_rtx)); | |
9566 | compare_result = or_result; | |
9567 | code = EQ; | |
9568 | } | |
9569 | else | |
9570 | { | |
9571 | /* We only care about 1 bit (x1xx), so map everything to NE to | |
9572 | maintain rtl sanity. We'll get to the right bit (x1xx) at | |
9573 | code output time. */ | |
9574 | if (code == NE || code == LTGT) | |
9575 | /* Do the inverse here because we have no cmpne | |
9576 | instruction. We use the cmpeq instruction and expect | |
9577 | to get a 0 instead. */ | |
9578 | code = EQ; | |
9579 | else | |
9580 | code = NE; | |
9581 | } | |
9582 | ||
9583 | emit_insn (cmp); | |
9584 | } | |
9585 | else | |
9586 | emit_insn (gen_rtx_SET (VOIDmode, compare_result, | |
9587 | gen_rtx_COMPARE (comp_mode, | |
9588 | rs6000_compare_op0, | |
9589 | rs6000_compare_op1))); | |
39a10a29 | 9590 | |
ca5adc63 | 9591 | /* Some kinds of FP comparisons need an OR operation; |
bc9ec0e0 | 9592 | under flag_finite_math_only we don't bother. */ |
39a10a29 | 9593 | if (rs6000_compare_fp_p |
bc9ec0e0 | 9594 | && ! flag_finite_math_only |
993f19a8 | 9595 | && ! (TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS) |
39a10a29 GK |
9596 | && (code == LE || code == GE |
9597 | || code == UNEQ || code == LTGT | |
9598 | || code == UNGT || code == UNLT)) | |
9599 | { | |
9600 | enum rtx_code or1, or2; | |
9601 | rtx or1_rtx, or2_rtx, compare2_rtx; | |
9602 | rtx or_result = gen_reg_rtx (CCEQmode); | |
9603 | ||
9604 | switch (code) | |
9605 | { | |
9606 | case LE: or1 = LT; or2 = EQ; break; | |
9607 | case GE: or1 = GT; or2 = EQ; break; | |
9608 | case UNEQ: or1 = UNORDERED; or2 = EQ; break; | |
9609 | case LTGT: or1 = LT; or2 = GT; break; | |
9610 | case UNGT: or1 = UNORDERED; or2 = GT; break; | |
9611 | case UNLT: or1 = UNORDERED; or2 = LT; break; | |
9612 | default: abort (); | |
9613 | } | |
9614 | validate_condition_mode (or1, comp_mode); | |
9615 | validate_condition_mode (or2, comp_mode); | |
1c563bed KH |
9616 | or1_rtx = gen_rtx_fmt_ee (or1, SImode, compare_result, const0_rtx); |
9617 | or2_rtx = gen_rtx_fmt_ee (or2, SImode, compare_result, const0_rtx); | |
39a10a29 GK |
9618 | compare2_rtx = gen_rtx_COMPARE (CCEQmode, |
9619 | gen_rtx_IOR (SImode, or1_rtx, or2_rtx), | |
9620 | const_true_rtx); | |
9621 | emit_insn (gen_rtx_SET (VOIDmode, or_result, compare2_rtx)); | |
9622 | ||
9623 | compare_result = or_result; | |
9624 | code = EQ; | |
9625 | } | |
9626 | ||
9627 | validate_condition_mode (code, GET_MODE (compare_result)); | |
9628 | ||
1c563bed | 9629 | return gen_rtx_fmt_ee (code, VOIDmode, compare_result, const0_rtx); |
39a10a29 GK |
9630 | } |
9631 | ||
9632 | ||
9633 | /* Emit the RTL for an sCOND pattern. */ | |
9634 | ||
9635 | void | |
a2369ed3 | 9636 | rs6000_emit_sCOND (enum rtx_code code, rtx result) |
39a10a29 GK |
9637 | { |
9638 | rtx condition_rtx; | |
9639 | enum machine_mode op_mode; | |
b7053a3f | 9640 | enum rtx_code cond_code; |
39a10a29 GK |
9641 | |
9642 | condition_rtx = rs6000_generate_compare (code); | |
b7053a3f GK |
9643 | cond_code = GET_CODE (condition_rtx); |
9644 | ||
9645 | if (cond_code == NE | |
9646 | || cond_code == GE || cond_code == LE | |
9647 | || cond_code == GEU || cond_code == LEU | |
9648 | || cond_code == ORDERED || cond_code == UNGE || cond_code == UNLE) | |
9649 | { | |
9650 | rtx not_result = gen_reg_rtx (CCEQmode); | |
9651 | rtx not_op, rev_cond_rtx; | |
9652 | enum machine_mode cc_mode; | |
9653 | ||
9654 | cc_mode = GET_MODE (XEXP (condition_rtx, 0)); | |
9655 | ||
1c563bed | 9656 | rev_cond_rtx = gen_rtx_fmt_ee (rs6000_reverse_condition (cc_mode, cond_code), |
0f4c242b | 9657 | SImode, XEXP (condition_rtx, 0), const0_rtx); |
b7053a3f GK |
9658 | not_op = gen_rtx_COMPARE (CCEQmode, rev_cond_rtx, const0_rtx); |
9659 | emit_insn (gen_rtx_SET (VOIDmode, not_result, not_op)); | |
9660 | condition_rtx = gen_rtx_EQ (VOIDmode, not_result, const0_rtx); | |
9661 | } | |
39a10a29 GK |
9662 | |
9663 | op_mode = GET_MODE (rs6000_compare_op0); | |
9664 | if (op_mode == VOIDmode) | |
9665 | op_mode = GET_MODE (rs6000_compare_op1); | |
9666 | ||
9667 | if (TARGET_POWERPC64 && (op_mode == DImode || rs6000_compare_fp_p)) | |
9668 | { | |
9669 | PUT_MODE (condition_rtx, DImode); | |
9670 | convert_move (result, condition_rtx, 0); | |
9671 | } | |
9672 | else | |
9673 | { | |
9674 | PUT_MODE (condition_rtx, SImode); | |
9675 | emit_insn (gen_rtx_SET (VOIDmode, result, condition_rtx)); | |
9676 | } | |
9677 | } | |
9678 | ||
39a10a29 GK |
9679 | /* Emit a branch of kind CODE to location LOC. */ |
9680 | ||
9681 | void | |
a2369ed3 | 9682 | rs6000_emit_cbranch (enum rtx_code code, rtx loc) |
39a10a29 GK |
9683 | { |
9684 | rtx condition_rtx, loc_ref; | |
9685 | ||
9686 | condition_rtx = rs6000_generate_compare (code); | |
9687 | loc_ref = gen_rtx_LABEL_REF (VOIDmode, loc); | |
9688 | emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, | |
9689 | gen_rtx_IF_THEN_ELSE (VOIDmode, condition_rtx, | |
9690 | loc_ref, pc_rtx))); | |
9691 | } | |
9692 | ||
12a4e8c5 GK |
9693 | /* Return the string to output a conditional branch to LABEL, which is |
9694 | the operand number of the label, or -1 if the branch is really a | |
9695 | conditional return. | |
9696 | ||
9697 | OP is the conditional expression. XEXP (OP, 0) is assumed to be a | |
9698 | condition code register and its mode specifies what kind of | |
9699 | comparison we made. | |
9700 | ||
a0ab749a | 9701 | REVERSED is nonzero if we should reverse the sense of the comparison. |
12a4e8c5 GK |
9702 | |
9703 | INSN is the insn. */ | |
9704 | ||
9705 | char * | |
a2369ed3 | 9706 | output_cbranch (rtx op, const char *label, int reversed, rtx insn) |
12a4e8c5 GK |
9707 | { |
9708 | static char string[64]; | |
9709 | enum rtx_code code = GET_CODE (op); | |
9710 | rtx cc_reg = XEXP (op, 0); | |
9711 | enum machine_mode mode = GET_MODE (cc_reg); | |
9712 | int cc_regno = REGNO (cc_reg) - CR0_REGNO; | |
39a10a29 | 9713 | int need_longbranch = label != NULL && get_attr_length (insn) == 8; |
12a4e8c5 GK |
9714 | int really_reversed = reversed ^ need_longbranch; |
9715 | char *s = string; | |
9716 | const char *ccode; | |
9717 | const char *pred; | |
9718 | rtx note; | |
9719 | ||
39a10a29 GK |
9720 | validate_condition_mode (code, mode); |
9721 | ||
9722 | /* Work out which way this really branches. We could use | |
9723 | reverse_condition_maybe_unordered here always but this | |
9724 | makes the resulting assembler clearer. */ | |
12a4e8c5 | 9725 | if (really_reversed) |
de40e1df DJ |
9726 | { |
9727 | /* Reversal of FP compares takes care -- an ordered compare | |
9728 | becomes an unordered compare and vice versa. */ | |
9729 | if (mode == CCFPmode) | |
9730 | code = reverse_condition_maybe_unordered (code); | |
9731 | else | |
9732 | code = reverse_condition (code); | |
9733 | } | |
12a4e8c5 | 9734 | |
993f19a8 | 9735 | if ((TARGET_E500 && !TARGET_FPRS && TARGET_HARD_FLOAT) && mode == CCFPmode) |
a3170dc6 AH |
9736 | { |
9737 | /* The efscmp/tst* instructions twiddle bit 2, which maps nicely | |
9738 | to the GT bit. */ | |
9739 | if (code == EQ) | |
9740 | /* Opposite of GT. */ | |
9741 | code = UNLE; | |
9742 | else if (code == NE) | |
9743 | code = GT; | |
9744 | else | |
9745 | abort (); | |
9746 | } | |
9747 | ||
39a10a29 | 9748 | switch (code) |
12a4e8c5 GK |
9749 | { |
9750 | /* Not all of these are actually distinct opcodes, but | |
9751 | we distinguish them for clarity of the resulting assembler. */ | |
50a0b056 GK |
9752 | case NE: case LTGT: |
9753 | ccode = "ne"; break; | |
9754 | case EQ: case UNEQ: | |
9755 | ccode = "eq"; break; | |
9756 | case GE: case GEU: | |
9757 | ccode = "ge"; break; | |
9758 | case GT: case GTU: case UNGT: | |
9759 | ccode = "gt"; break; | |
9760 | case LE: case LEU: | |
9761 | ccode = "le"; break; | |
9762 | case LT: case LTU: case UNLT: | |
9763 | ccode = "lt"; break; | |
12a4e8c5 GK |
9764 | case UNORDERED: ccode = "un"; break; |
9765 | case ORDERED: ccode = "nu"; break; | |
9766 | case UNGE: ccode = "nl"; break; | |
9767 | case UNLE: ccode = "ng"; break; | |
9768 | default: | |
a4f6c312 | 9769 | abort (); |
12a4e8c5 GK |
9770 | } |
9771 | ||
94a54f47 GK |
9772 | /* Maybe we have a guess as to how likely the branch is. |
9773 | The old mnemonics don't have a way to specify this information. */ | |
f4857b9b | 9774 | pred = ""; |
12a4e8c5 GK |
9775 | note = find_reg_note (insn, REG_BR_PROB, NULL_RTX); |
9776 | if (note != NULL_RTX) | |
9777 | { | |
9778 | /* PROB is the difference from 50%. */ | |
9779 | int prob = INTVAL (XEXP (note, 0)) - REG_BR_PROB_BASE / 2; | |
f4857b9b AM |
9780 | bool always_hint = rs6000_cpu != PROCESSOR_POWER4; |
9781 | ||
9782 | /* Only hint for highly probable/improbable branches on newer | |
9783 | cpus as static prediction overrides processor dynamic | |
9784 | prediction. For older cpus we may as well always hint, but | |
9785 | assume not taken for branches that are very close to 50% as a | |
9786 | mispredicted taken branch is more expensive than a | |
9787 | mispredicted not-taken branch. */ | |
9788 | if (always_hint | |
9789 | || abs (prob) > REG_BR_PROB_BASE / 100 * 48) | |
9790 | { | |
9791 | if (abs (prob) > REG_BR_PROB_BASE / 20 | |
9792 | && ((prob > 0) ^ need_longbranch)) | |
7f3d8013 | 9793 | pred = "+"; |
f4857b9b AM |
9794 | else |
9795 | pred = "-"; | |
9796 | } | |
12a4e8c5 | 9797 | } |
12a4e8c5 GK |
9798 | |
9799 | if (label == NULL) | |
94a54f47 | 9800 | s += sprintf (s, "{b%sr|b%slr%s} ", ccode, ccode, pred); |
12a4e8c5 | 9801 | else |
94a54f47 | 9802 | s += sprintf (s, "{b%s|b%s%s} ", ccode, ccode, pred); |
12a4e8c5 | 9803 | |
37c67319 | 9804 | /* We need to escape any '%' characters in the reg_names string. |
a3c9585f | 9805 | Assume they'd only be the first character.... */ |
37c67319 GK |
9806 | if (reg_names[cc_regno + CR0_REGNO][0] == '%') |
9807 | *s++ = '%'; | |
94a54f47 | 9808 | s += sprintf (s, "%s", reg_names[cc_regno + CR0_REGNO]); |
12a4e8c5 GK |
9809 | |
9810 | if (label != NULL) | |
9811 | { | |
9812 | /* If the branch distance was too far, we may have to use an | |
9813 | unconditional branch to go the distance. */ | |
9814 | if (need_longbranch) | |
44518ddd | 9815 | s += sprintf (s, ",$+8\n\tb %s", label); |
12a4e8c5 GK |
9816 | else |
9817 | s += sprintf (s, ",%s", label); | |
9818 | } | |
9819 | ||
9820 | return string; | |
9821 | } | |
50a0b056 GK |
9822 | |
9823 | /* Emit a conditional move: move TRUE_COND to DEST if OP of the | |
9824 | operands of the last comparison is nonzero/true, FALSE_COND if it | |
9825 | is zero/false. Return 0 if the hardware has no such operation. */ | |
a4f6c312 | 9826 | |
50a0b056 | 9827 | int |
a2369ed3 | 9828 | rs6000_emit_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond) |
50a0b056 GK |
9829 | { |
9830 | enum rtx_code code = GET_CODE (op); | |
9831 | rtx op0 = rs6000_compare_op0; | |
9832 | rtx op1 = rs6000_compare_op1; | |
9833 | REAL_VALUE_TYPE c1; | |
3148ad6d DJ |
9834 | enum machine_mode compare_mode = GET_MODE (op0); |
9835 | enum machine_mode result_mode = GET_MODE (dest); | |
50a0b056 GK |
9836 | rtx temp; |
9837 | ||
a3c9585f | 9838 | /* These modes should always match. */ |
a3170dc6 AH |
9839 | if (GET_MODE (op1) != compare_mode |
9840 | /* In the isel case however, we can use a compare immediate, so | |
9841 | op1 may be a small constant. */ | |
9842 | && (!TARGET_ISEL || !short_cint_operand (op1, VOIDmode))) | |
3148ad6d | 9843 | return 0; |
178c3eff | 9844 | if (GET_MODE (true_cond) != result_mode) |
3148ad6d | 9845 | return 0; |
178c3eff | 9846 | if (GET_MODE (false_cond) != result_mode) |
3148ad6d DJ |
9847 | return 0; |
9848 | ||
50a0b056 | 9849 | /* First, work out if the hardware can do this at all, or |
a3c9585f | 9850 | if it's too slow.... */ |
50a0b056 | 9851 | if (! rs6000_compare_fp_p) |
a3170dc6 AH |
9852 | { |
9853 | if (TARGET_ISEL) | |
9854 | return rs6000_emit_int_cmove (dest, op, true_cond, false_cond); | |
9855 | return 0; | |
9856 | } | |
50a0b056 GK |
9857 | |
9858 | /* Eliminate half of the comparisons by switching operands, this | |
9859 | makes the remaining code simpler. */ | |
9860 | if (code == UNLT || code == UNGT || code == UNORDERED || code == NE | |
bc9ec0e0 | 9861 | || code == LTGT || code == LT || code == UNLE) |
50a0b056 GK |
9862 | { |
9863 | code = reverse_condition_maybe_unordered (code); | |
9864 | temp = true_cond; | |
9865 | true_cond = false_cond; | |
9866 | false_cond = temp; | |
9867 | } | |
9868 | ||
9869 | /* UNEQ and LTGT take four instructions for a comparison with zero, | |
9870 | it'll probably be faster to use a branch here too. */ | |
bc9ec0e0 | 9871 | if (code == UNEQ && HONOR_NANS (compare_mode)) |
50a0b056 GK |
9872 | return 0; |
9873 | ||
9874 | if (GET_CODE (op1) == CONST_DOUBLE) | |
9875 | REAL_VALUE_FROM_CONST_DOUBLE (c1, op1); | |
9876 | ||
b6d08ca1 | 9877 | /* We're going to try to implement comparisons by performing |
50a0b056 GK |
9878 | a subtract, then comparing against zero. Unfortunately, |
9879 | Inf - Inf is NaN which is not zero, and so if we don't | |
27d30956 | 9880 | know that the operand is finite and the comparison |
50a0b056 | 9881 | would treat EQ different to UNORDERED, we can't do it. */ |
bc9ec0e0 | 9882 | if (HONOR_INFINITIES (compare_mode) |
50a0b056 | 9883 | && code != GT && code != UNGE |
045572c7 | 9884 | && (GET_CODE (op1) != CONST_DOUBLE || real_isinf (&c1)) |
50a0b056 GK |
9885 | /* Constructs of the form (a OP b ? a : b) are safe. */ |
9886 | && ((! rtx_equal_p (op0, false_cond) && ! rtx_equal_p (op1, false_cond)) | |
9887 | || (! rtx_equal_p (op0, true_cond) | |
9888 | && ! rtx_equal_p (op1, true_cond)))) | |
9889 | return 0; | |
9890 | /* At this point we know we can use fsel. */ | |
9891 | ||
9892 | /* Reduce the comparison to a comparison against zero. */ | |
3148ad6d | 9893 | temp = gen_reg_rtx (compare_mode); |
50a0b056 | 9894 | emit_insn (gen_rtx_SET (VOIDmode, temp, |
3148ad6d | 9895 | gen_rtx_MINUS (compare_mode, op0, op1))); |
50a0b056 | 9896 | op0 = temp; |
3148ad6d | 9897 | op1 = CONST0_RTX (compare_mode); |
50a0b056 GK |
9898 | |
9899 | /* If we don't care about NaNs we can reduce some of the comparisons | |
9900 | down to faster ones. */ | |
bc9ec0e0 | 9901 | if (! HONOR_NANS (compare_mode)) |
50a0b056 GK |
9902 | switch (code) |
9903 | { | |
9904 | case GT: | |
9905 | code = LE; | |
9906 | temp = true_cond; | |
9907 | true_cond = false_cond; | |
9908 | false_cond = temp; | |
9909 | break; | |
9910 | case UNGE: | |
9911 | code = GE; | |
9912 | break; | |
9913 | case UNEQ: | |
9914 | code = EQ; | |
9915 | break; | |
9916 | default: | |
9917 | break; | |
9918 | } | |
9919 | ||
9920 | /* Now, reduce everything down to a GE. */ | |
9921 | switch (code) | |
9922 | { | |
9923 | case GE: | |
9924 | break; | |
9925 | ||
9926 | case LE: | |
3148ad6d DJ |
9927 | temp = gen_reg_rtx (compare_mode); |
9928 | emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0))); | |
50a0b056 GK |
9929 | op0 = temp; |
9930 | break; | |
9931 | ||
9932 | case ORDERED: | |
3148ad6d DJ |
9933 | temp = gen_reg_rtx (compare_mode); |
9934 | emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_ABS (compare_mode, op0))); | |
50a0b056 GK |
9935 | op0 = temp; |
9936 | break; | |
9937 | ||
9938 | case EQ: | |
3148ad6d | 9939 | temp = gen_reg_rtx (compare_mode); |
50a0b056 | 9940 | emit_insn (gen_rtx_SET (VOIDmode, temp, |
3148ad6d DJ |
9941 | gen_rtx_NEG (compare_mode, |
9942 | gen_rtx_ABS (compare_mode, op0)))); | |
50a0b056 GK |
9943 | op0 = temp; |
9944 | break; | |
9945 | ||
9946 | case UNGE: | |
bc9ec0e0 | 9947 | /* a UNGE 0 <-> (a GE 0 || -a UNLT 0) */ |
3148ad6d | 9948 | temp = gen_reg_rtx (result_mode); |
50a0b056 | 9949 | emit_insn (gen_rtx_SET (VOIDmode, temp, |
3148ad6d | 9950 | gen_rtx_IF_THEN_ELSE (result_mode, |
50a0b056 GK |
9951 | gen_rtx_GE (VOIDmode, |
9952 | op0, op1), | |
9953 | true_cond, false_cond))); | |
bc9ec0e0 GK |
9954 | false_cond = true_cond; |
9955 | true_cond = temp; | |
50a0b056 | 9956 | |
3148ad6d DJ |
9957 | temp = gen_reg_rtx (compare_mode); |
9958 | emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0))); | |
50a0b056 GK |
9959 | op0 = temp; |
9960 | break; | |
9961 | ||
9962 | case GT: | |
bc9ec0e0 | 9963 | /* a GT 0 <-> (a GE 0 && -a UNLT 0) */ |
3148ad6d | 9964 | temp = gen_reg_rtx (result_mode); |
50a0b056 | 9965 | emit_insn (gen_rtx_SET (VOIDmode, temp, |
3148ad6d | 9966 | gen_rtx_IF_THEN_ELSE (result_mode, |
50a0b056 GK |
9967 | gen_rtx_GE (VOIDmode, |
9968 | op0, op1), | |
9969 | true_cond, false_cond))); | |
bc9ec0e0 GK |
9970 | true_cond = false_cond; |
9971 | false_cond = temp; | |
50a0b056 | 9972 | |
3148ad6d DJ |
9973 | temp = gen_reg_rtx (compare_mode); |
9974 | emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0))); | |
50a0b056 GK |
9975 | op0 = temp; |
9976 | break; | |
9977 | ||
9978 | default: | |
9979 | abort (); | |
9980 | } | |
9981 | ||
9982 | emit_insn (gen_rtx_SET (VOIDmode, dest, | |
3148ad6d | 9983 | gen_rtx_IF_THEN_ELSE (result_mode, |
50a0b056 GK |
9984 | gen_rtx_GE (VOIDmode, |
9985 | op0, op1), | |
9986 | true_cond, false_cond))); | |
9987 | return 1; | |
9988 | } | |
9989 | ||
a3170dc6 AH |
9990 | /* Same as above, but for ints (isel). */ |
9991 | ||
9992 | static int | |
a2369ed3 | 9993 | rs6000_emit_int_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond) |
a3170dc6 AH |
9994 | { |
9995 | rtx condition_rtx, cr; | |
9996 | ||
9997 | /* All isel implementations thus far are 32-bits. */ | |
9998 | if (GET_MODE (rs6000_compare_op0) != SImode) | |
9999 | return 0; | |
10000 | ||
10001 | /* We still have to do the compare, because isel doesn't do a | |
10002 | compare, it just looks at the CRx bits set by a previous compare | |
10003 | instruction. */ | |
10004 | condition_rtx = rs6000_generate_compare (GET_CODE (op)); | |
10005 | cr = XEXP (condition_rtx, 0); | |
10006 | ||
10007 | if (GET_MODE (cr) == CCmode) | |
10008 | emit_insn (gen_isel_signed (dest, condition_rtx, | |
10009 | true_cond, false_cond, cr)); | |
10010 | else | |
10011 | emit_insn (gen_isel_unsigned (dest, condition_rtx, | |
10012 | true_cond, false_cond, cr)); | |
10013 | ||
10014 | return 1; | |
10015 | } | |
10016 | ||
10017 | const char * | |
a2369ed3 | 10018 | output_isel (rtx *operands) |
a3170dc6 AH |
10019 | { |
10020 | enum rtx_code code; | |
10021 | ||
10022 | code = GET_CODE (operands[1]); | |
10023 | if (code == GE || code == GEU || code == LE || code == LEU || code == NE) | |
10024 | { | |
10025 | PUT_CODE (operands[1], reverse_condition (code)); | |
10026 | return "isel %0,%3,%2,%j1"; | |
10027 | } | |
10028 | else | |
10029 | return "isel %0,%2,%3,%j1"; | |
10030 | } | |
10031 | ||
50a0b056 | 10032 | void |
a2369ed3 | 10033 | rs6000_emit_minmax (rtx dest, enum rtx_code code, rtx op0, rtx op1) |
50a0b056 GK |
10034 | { |
10035 | enum machine_mode mode = GET_MODE (op0); | |
5dc8d536 | 10036 | enum rtx_code c; |
50a0b056 | 10037 | rtx target; |
5dc8d536 AH |
10038 | |
10039 | if (code == SMAX || code == SMIN) | |
10040 | c = GE; | |
10041 | else | |
10042 | c = GEU; | |
10043 | ||
50a0b056 | 10044 | if (code == SMAX || code == UMAX) |
5dc8d536 | 10045 | target = emit_conditional_move (dest, c, op0, op1, mode, |
50a0b056 GK |
10046 | op0, op1, mode, 0); |
10047 | else | |
5dc8d536 | 10048 | target = emit_conditional_move (dest, c, op0, op1, mode, |
50a0b056 GK |
10049 | op1, op0, mode, 0); |
10050 | if (target == NULL_RTX) | |
10051 | abort (); | |
10052 | if (target != dest) | |
10053 | emit_move_insn (dest, target); | |
10054 | } | |
46c07df8 | 10055 | |
a9baceb1 GK |
10056 | /* Emit instructions to move SRC to DST. Called by splitters for |
10057 | multi-register moves. It will emit at most one instruction for | |
10058 | each register that is accessed; that is, it won't emit li/lis pairs | |
10059 | (or equivalent for 64-bit code). One of SRC or DST must be a hard | |
10060 | register. */ | |
46c07df8 | 10061 | |
46c07df8 | 10062 | void |
a9baceb1 | 10063 | rs6000_split_multireg_move (rtx dst, rtx src) |
46c07df8 | 10064 | { |
a9baceb1 GK |
10065 | /* The register number of the first register being moved. */ |
10066 | int reg; | |
10067 | /* The mode that is to be moved. */ | |
10068 | enum machine_mode mode; | |
10069 | /* The mode that the move is being done in, and its size. */ | |
10070 | enum machine_mode reg_mode; | |
10071 | int reg_mode_size; | |
10072 | /* The number of registers that will be moved. */ | |
10073 | int nregs; | |
10074 | ||
10075 | reg = REG_P (dst) ? REGNO (dst) : REGNO (src); | |
10076 | mode = GET_MODE (dst); | |
10077 | nregs = HARD_REGNO_NREGS (reg, mode); | |
10078 | if (FP_REGNO_P (reg)) | |
10079 | reg_mode = DFmode; | |
10080 | else if (ALTIVEC_REGNO_P (reg)) | |
10081 | reg_mode = V16QImode; | |
10082 | else | |
10083 | reg_mode = word_mode; | |
10084 | reg_mode_size = GET_MODE_SIZE (reg_mode); | |
46c07df8 | 10085 | |
a9baceb1 GK |
10086 | if (reg_mode_size * nregs != GET_MODE_SIZE (mode)) |
10087 | abort (); | |
10088 | ||
10089 | if (REG_P (src) && REG_P (dst) && (REGNO (src) < REGNO (dst))) | |
10090 | { | |
10091 | /* Move register range backwards, if we might have destructive | |
10092 | overlap. */ | |
10093 | int i; | |
10094 | for (i = nregs - 1; i >= 0; i--) | |
10095 | emit_insn (gen_rtx_SET (VOIDmode, | |
10096 | simplify_gen_subreg (reg_mode, dst, mode, | |
10097 | i * reg_mode_size), | |
10098 | simplify_gen_subreg (reg_mode, src, mode, | |
10099 | i * reg_mode_size))); | |
10100 | } | |
46c07df8 HP |
10101 | else |
10102 | { | |
a9baceb1 GK |
10103 | int i; |
10104 | int j = -1; | |
10105 | bool used_update = false; | |
46c07df8 | 10106 | |
a9baceb1 | 10107 | if (GET_CODE (src) == MEM && INT_REGNO_P (reg)) |
46c07df8 HP |
10108 | { |
10109 | rtx breg; | |
3a1f863f | 10110 | |
a9baceb1 GK |
10111 | if (GET_CODE (XEXP (src, 0)) == PRE_INC |
10112 | || GET_CODE (XEXP (src, 0)) == PRE_DEC) | |
3a1f863f DE |
10113 | { |
10114 | rtx delta_rtx; | |
a9baceb1 GK |
10115 | breg = XEXP (XEXP (src, 0), 0); |
10116 | delta_rtx = GET_CODE (XEXP (src, 0)) == PRE_INC | |
10117 | ? GEN_INT (GET_MODE_SIZE (GET_MODE (src))) | |
10118 | : GEN_INT (-GET_MODE_SIZE (GET_MODE (src))); | |
10119 | emit_insn (TARGET_32BIT | |
10120 | ? gen_addsi3 (breg, breg, delta_rtx) | |
10121 | : gen_adddi3 (breg, breg, delta_rtx)); | |
3a1f863f DE |
10122 | src = gen_rtx_MEM (mode, breg); |
10123 | } | |
10124 | ||
10125 | /* We have now address involving an base register only. | |
10126 | If we use one of the registers to address memory, | |
10127 | we have change that register last. */ | |
10128 | ||
10129 | breg = (GET_CODE (XEXP (src, 0)) == PLUS | |
10130 | ? XEXP (XEXP (src, 0), 0) | |
10131 | : XEXP (src, 0)); | |
10132 | ||
10133 | if (!REG_P (breg)) | |
10134 | abort(); | |
10135 | ||
10136 | if (REGNO (breg) >= REGNO (dst) | |
10137 | && REGNO (breg) < REGNO (dst) + nregs) | |
10138 | j = REGNO (breg) - REGNO (dst); | |
46c07df8 HP |
10139 | } |
10140 | ||
a9baceb1 | 10141 | if (GET_CODE (dst) == MEM && INT_REGNO_P (reg)) |
3a1f863f DE |
10142 | { |
10143 | rtx breg; | |
10144 | ||
a9baceb1 GK |
10145 | if (GET_CODE (XEXP (dst, 0)) == PRE_INC |
10146 | || GET_CODE (XEXP (dst, 0)) == PRE_DEC) | |
3a1f863f DE |
10147 | { |
10148 | rtx delta_rtx; | |
a9baceb1 GK |
10149 | breg = XEXP (XEXP (dst, 0), 0); |
10150 | delta_rtx = GET_CODE (XEXP (dst, 0)) == PRE_INC | |
10151 | ? GEN_INT (GET_MODE_SIZE (GET_MODE (dst))) | |
10152 | : GEN_INT (-GET_MODE_SIZE (GET_MODE (dst))); | |
3a1f863f DE |
10153 | |
10154 | /* We have to update the breg before doing the store. | |
10155 | Use store with update, if available. */ | |
10156 | ||
10157 | if (TARGET_UPDATE) | |
10158 | { | |
a9baceb1 GK |
10159 | rtx nsrc = simplify_gen_subreg (reg_mode, src, mode, 0); |
10160 | emit_insn (TARGET_32BIT | |
10161 | ? gen_movsi_update (breg, breg, delta_rtx, nsrc) | |
10162 | : gen_movdi_update (breg, breg, delta_rtx, nsrc)); | |
10163 | used_update = true; | |
3a1f863f DE |
10164 | } |
10165 | else | |
a9baceb1 GK |
10166 | emit_insn (TARGET_32BIT |
10167 | ? gen_addsi3 (breg, breg, delta_rtx) | |
10168 | : gen_adddi3 (breg, breg, delta_rtx)); | |
3a1f863f DE |
10169 | dst = gen_rtx_MEM (mode, breg); |
10170 | } | |
10171 | } | |
10172 | ||
46c07df8 | 10173 | for (i = 0; i < nregs; i++) |
3a1f863f DE |
10174 | { |
10175 | /* Calculate index to next subword. */ | |
10176 | ++j; | |
10177 | if (j == nregs) | |
10178 | j = 0; | |
46c07df8 | 10179 | |
a9baceb1 GK |
10180 | /* If compiler already emited move of first word by |
10181 | store with update, no need to do anything. */ | |
3a1f863f | 10182 | if (j == 0 && used_update) |
a9baceb1 GK |
10183 | continue; |
10184 | ||
10185 | emit_insn (gen_rtx_SET (VOIDmode, | |
10186 | simplify_gen_subreg (reg_mode, dst, mode, | |
10187 | j * reg_mode_size), | |
10188 | simplify_gen_subreg (reg_mode, src, mode, | |
10189 | j * reg_mode_size))); | |
3a1f863f | 10190 | } |
46c07df8 HP |
10191 | } |
10192 | } | |
10193 | ||
12a4e8c5 | 10194 | \f |
a4f6c312 SS |
10195 | /* This page contains routines that are used to determine what the |
10196 | function prologue and epilogue code will do and write them out. */ | |
9878760c | 10197 | |
a4f6c312 SS |
10198 | /* Return the first fixed-point register that is required to be |
10199 | saved. 32 if none. */ | |
9878760c RK |
10200 | |
10201 | int | |
863d938c | 10202 | first_reg_to_save (void) |
9878760c RK |
10203 | { |
10204 | int first_reg; | |
10205 | ||
10206 | /* Find lowest numbered live register. */ | |
10207 | for (first_reg = 13; first_reg <= 31; first_reg++) | |
a38d360d GK |
10208 | if (regs_ever_live[first_reg] |
10209 | && (! call_used_regs[first_reg] | |
1db02437 | 10210 | || (first_reg == RS6000_PIC_OFFSET_TABLE_REGNUM |
14f00213 | 10211 | && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0) |
f607bc57 | 10212 | || (DEFAULT_ABI == ABI_DARWIN && flag_pic))))) |
9878760c RK |
10213 | break; |
10214 | ||
ee890fe2 | 10215 | #if TARGET_MACHO |
93638d7a AM |
10216 | if (flag_pic |
10217 | && current_function_uses_pic_offset_table | |
10218 | && first_reg > RS6000_PIC_OFFSET_TABLE_REGNUM) | |
1db02437 | 10219 | return RS6000_PIC_OFFSET_TABLE_REGNUM; |
ee890fe2 SS |
10220 | #endif |
10221 | ||
9878760c RK |
10222 | return first_reg; |
10223 | } | |
10224 | ||
10225 | /* Similar, for FP regs. */ | |
10226 | ||
10227 | int | |
863d938c | 10228 | first_fp_reg_to_save (void) |
9878760c RK |
10229 | { |
10230 | int first_reg; | |
10231 | ||
10232 | /* Find lowest numbered live register. */ | |
10233 | for (first_reg = 14 + 32; first_reg <= 63; first_reg++) | |
10234 | if (regs_ever_live[first_reg]) | |
10235 | break; | |
10236 | ||
10237 | return first_reg; | |
10238 | } | |
00b960c7 AH |
10239 | |
10240 | /* Similar, for AltiVec regs. */ | |
10241 | ||
10242 | static int | |
863d938c | 10243 | first_altivec_reg_to_save (void) |
00b960c7 AH |
10244 | { |
10245 | int i; | |
10246 | ||
10247 | /* Stack frame remains as is unless we are in AltiVec ABI. */ | |
10248 | if (! TARGET_ALTIVEC_ABI) | |
10249 | return LAST_ALTIVEC_REGNO + 1; | |
10250 | ||
10251 | /* Find lowest numbered live register. */ | |
10252 | for (i = FIRST_ALTIVEC_REGNO + 20; i <= LAST_ALTIVEC_REGNO; ++i) | |
10253 | if (regs_ever_live[i]) | |
10254 | break; | |
10255 | ||
10256 | return i; | |
10257 | } | |
10258 | ||
10259 | /* Return a 32-bit mask of the AltiVec registers we need to set in | |
10260 | VRSAVE. Bit n of the return value is 1 if Vn is live. The MSB in | |
10261 | the 32-bit word is 0. */ | |
10262 | ||
10263 | static unsigned int | |
863d938c | 10264 | compute_vrsave_mask (void) |
00b960c7 AH |
10265 | { |
10266 | unsigned int i, mask = 0; | |
10267 | ||
10268 | /* First, find out if we use _any_ altivec registers. */ | |
10269 | for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i) | |
10270 | if (regs_ever_live[i]) | |
10271 | mask |= ALTIVEC_REG_BIT (i); | |
10272 | ||
10273 | if (mask == 0) | |
10274 | return mask; | |
10275 | ||
00b960c7 AH |
10276 | /* Next, remove the argument registers from the set. These must |
10277 | be in the VRSAVE mask set by the caller, so we don't need to add | |
10278 | them in again. More importantly, the mask we compute here is | |
10279 | used to generate CLOBBERs in the set_vrsave insn, and we do not | |
10280 | wish the argument registers to die. */ | |
a6cf80f2 | 10281 | for (i = cfun->args_info.vregno - 1; i >= ALTIVEC_ARG_MIN_REG; --i) |
00b960c7 AH |
10282 | mask &= ~ALTIVEC_REG_BIT (i); |
10283 | ||
10284 | /* Similarly, remove the return value from the set. */ | |
10285 | { | |
10286 | bool yes = false; | |
10287 | diddle_return_value (is_altivec_return_reg, &yes); | |
10288 | if (yes) | |
10289 | mask &= ~ALTIVEC_REG_BIT (ALTIVEC_ARG_RETURN); | |
10290 | } | |
10291 | ||
10292 | return mask; | |
10293 | } | |
10294 | ||
10295 | static void | |
a2369ed3 | 10296 | is_altivec_return_reg (rtx reg, void *xyes) |
00b960c7 AH |
10297 | { |
10298 | bool *yes = (bool *) xyes; | |
10299 | if (REGNO (reg) == ALTIVEC_ARG_RETURN) | |
10300 | *yes = true; | |
10301 | } | |
10302 | ||
4697a36c MM |
10303 | \f |
10304 | /* Calculate the stack information for the current function. This is | |
10305 | complicated by having two separate calling sequences, the AIX calling | |
10306 | sequence and the V.4 calling sequence. | |
10307 | ||
592696dd | 10308 | AIX (and Darwin/Mac OS X) stack frames look like: |
a260abc9 | 10309 | 32-bit 64-bit |
4697a36c | 10310 | SP----> +---------------------------------------+ |
a260abc9 | 10311 | | back chain to caller | 0 0 |
4697a36c | 10312 | +---------------------------------------+ |
a260abc9 | 10313 | | saved CR | 4 8 (8-11) |
4697a36c | 10314 | +---------------------------------------+ |
a260abc9 | 10315 | | saved LR | 8 16 |
4697a36c | 10316 | +---------------------------------------+ |
a260abc9 | 10317 | | reserved for compilers | 12 24 |
4697a36c | 10318 | +---------------------------------------+ |
a260abc9 | 10319 | | reserved for binders | 16 32 |
4697a36c | 10320 | +---------------------------------------+ |
a260abc9 | 10321 | | saved TOC pointer | 20 40 |
4697a36c | 10322 | +---------------------------------------+ |
a260abc9 | 10323 | | Parameter save area (P) | 24 48 |
4697a36c | 10324 | +---------------------------------------+ |
a260abc9 | 10325 | | Alloca space (A) | 24+P etc. |
802a0058 | 10326 | +---------------------------------------+ |
a7df97e6 | 10327 | | Local variable space (L) | 24+P+A |
4697a36c | 10328 | +---------------------------------------+ |
a7df97e6 | 10329 | | Float/int conversion temporary (X) | 24+P+A+L |
4697a36c | 10330 | +---------------------------------------+ |
00b960c7 AH |
10331 | | Save area for AltiVec registers (W) | 24+P+A+L+X |
10332 | +---------------------------------------+ | |
10333 | | AltiVec alignment padding (Y) | 24+P+A+L+X+W | |
10334 | +---------------------------------------+ | |
10335 | | Save area for VRSAVE register (Z) | 24+P+A+L+X+W+Y | |
4697a36c | 10336 | +---------------------------------------+ |
00b960c7 AH |
10337 | | Save area for GP registers (G) | 24+P+A+X+L+X+W+Y+Z |
10338 | +---------------------------------------+ | |
10339 | | Save area for FP registers (F) | 24+P+A+X+L+X+W+Y+Z+G | |
4697a36c MM |
10340 | +---------------------------------------+ |
10341 | old SP->| back chain to caller's caller | | |
10342 | +---------------------------------------+ | |
10343 | ||
5376a30c KR |
10344 | The required alignment for AIX configurations is two words (i.e., 8 |
10345 | or 16 bytes). | |
10346 | ||
10347 | ||
4697a36c MM |
10348 | V.4 stack frames look like: |
10349 | ||
10350 | SP----> +---------------------------------------+ | |
10351 | | back chain to caller | 0 | |
10352 | +---------------------------------------+ | |
5eb387b8 | 10353 | | caller's saved LR | 4 |
4697a36c MM |
10354 | +---------------------------------------+ |
10355 | | Parameter save area (P) | 8 | |
10356 | +---------------------------------------+ | |
a7df97e6 MM |
10357 | | Alloca space (A) | 8+P |
10358 | +---------------------------------------+ | |
10359 | | Varargs save area (V) | 8+P+A | |
10360 | +---------------------------------------+ | |
10361 | | Local variable space (L) | 8+P+A+V | |
10362 | +---------------------------------------+ | |
10363 | | Float/int conversion temporary (X) | 8+P+A+V+L | |
4697a36c | 10364 | +---------------------------------------+ |
00b960c7 AH |
10365 | | Save area for AltiVec registers (W) | 8+P+A+V+L+X |
10366 | +---------------------------------------+ | |
10367 | | AltiVec alignment padding (Y) | 8+P+A+V+L+X+W | |
10368 | +---------------------------------------+ | |
10369 | | Save area for VRSAVE register (Z) | 8+P+A+V+L+X+W+Y | |
10370 | +---------------------------------------+ | |
a3170dc6 AH |
10371 | | SPE: area for 64-bit GP registers | |
10372 | +---------------------------------------+ | |
10373 | | SPE alignment padding | | |
10374 | +---------------------------------------+ | |
00b960c7 | 10375 | | saved CR (C) | 8+P+A+V+L+X+W+Y+Z |
a7df97e6 | 10376 | +---------------------------------------+ |
00b960c7 | 10377 | | Save area for GP registers (G) | 8+P+A+V+L+X+W+Y+Z+C |
a7df97e6 | 10378 | +---------------------------------------+ |
00b960c7 | 10379 | | Save area for FP registers (F) | 8+P+A+V+L+X+W+Y+Z+C+G |
4697a36c MM |
10380 | +---------------------------------------+ |
10381 | old SP->| back chain to caller's caller | | |
10382 | +---------------------------------------+ | |
b6c9286a | 10383 | |
5376a30c KR |
10384 | The required alignment for V.4 is 16 bytes, or 8 bytes if -meabi is |
10385 | given. (But note below and in sysv4.h that we require only 8 and | |
10386 | may round up the size of our stack frame anyways. The historical | |
10387 | reason is early versions of powerpc-linux which didn't properly | |
10388 | align the stack at program startup. A happy side-effect is that | |
10389 | -mno-eabi libraries can be used with -meabi programs.) | |
10390 | ||
50d440bc | 10391 | The EABI configuration defaults to the V.4 layout. However, |
5376a30c KR |
10392 | the stack alignment requirements may differ. If -mno-eabi is not |
10393 | given, the required stack alignment is 8 bytes; if -mno-eabi is | |
10394 | given, the required alignment is 16 bytes. (But see V.4 comment | |
10395 | above.) */ | |
4697a36c | 10396 | |
61b2fbe7 MM |
10397 | #ifndef ABI_STACK_BOUNDARY |
10398 | #define ABI_STACK_BOUNDARY STACK_BOUNDARY | |
10399 | #endif | |
10400 | ||
d1d0c603 | 10401 | static rs6000_stack_t * |
863d938c | 10402 | rs6000_stack_info (void) |
4697a36c MM |
10403 | { |
10404 | static rs6000_stack_t info, zero_info; | |
10405 | rs6000_stack_t *info_ptr = &info; | |
9ebbca7d | 10406 | int reg_size = TARGET_POWERPC64 ? 8 : 4; |
83720594 | 10407 | int ehrd_size; |
d1d0c603 | 10408 | HOST_WIDE_INT total_raw_size; |
4697a36c | 10409 | |
a4f6c312 | 10410 | /* Zero all fields portably. */ |
4697a36c MM |
10411 | info = zero_info; |
10412 | ||
c19de7aa AH |
10413 | if (TARGET_SPE) |
10414 | { | |
10415 | /* Cache value so we don't rescan instruction chain over and over. */ | |
9b7b447f AH |
10416 | if (cfun->machine->insn_chain_scanned_p == 0) |
10417 | { | |
10418 | cfun->machine->insn_chain_scanned_p = 1; | |
10419 | info_ptr->spe_64bit_regs_used = (int) spe_func_has_64bit_regs_p (); | |
10420 | } | |
c19de7aa AH |
10421 | } |
10422 | ||
a4f6c312 | 10423 | /* Select which calling sequence. */ |
178274da | 10424 | info_ptr->abi = DEFAULT_ABI; |
9878760c | 10425 | |
a4f6c312 | 10426 | /* Calculate which registers need to be saved & save area size. */ |
4697a36c | 10427 | info_ptr->first_gp_reg_save = first_reg_to_save (); |
1db02437 | 10428 | /* Assume that we will have to save RS6000_PIC_OFFSET_TABLE_REGNUM, |
906fb125 | 10429 | even if it currently looks like we won't. */ |
2bfcf297 | 10430 | if (((TARGET_TOC && TARGET_MINIMAL_TOC) |
178274da AM |
10431 | || (flag_pic == 1 && DEFAULT_ABI == ABI_V4) |
10432 | || (flag_pic && DEFAULT_ABI == ABI_DARWIN)) | |
1db02437 FS |
10433 | && info_ptr->first_gp_reg_save > RS6000_PIC_OFFSET_TABLE_REGNUM) |
10434 | info_ptr->gp_size = reg_size * (32 - RS6000_PIC_OFFSET_TABLE_REGNUM); | |
906fb125 GK |
10435 | else |
10436 | info_ptr->gp_size = reg_size * (32 - info_ptr->first_gp_reg_save); | |
4697a36c | 10437 | |
a3170dc6 AH |
10438 | /* For the SPE, we have an additional upper 32-bits on each GPR. |
10439 | Ideally we should save the entire 64-bits only when the upper | |
10440 | half is used in SIMD instructions. Since we only record | |
10441 | registers live (not the size they are used in), this proves | |
10442 | difficult because we'd have to traverse the instruction chain at | |
10443 | the right time, taking reload into account. This is a real pain, | |
c19de7aa AH |
10444 | so we opt to save the GPRs in 64-bits always if but one register |
10445 | gets used in 64-bits. Otherwise, all the registers in the frame | |
10446 | get saved in 32-bits. | |
a3170dc6 | 10447 | |
c19de7aa | 10448 | So... since when we save all GPRs (except the SP) in 64-bits, the |
a3170dc6 | 10449 | traditional GP save area will be empty. */ |
c19de7aa | 10450 | if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0) |
a3170dc6 AH |
10451 | info_ptr->gp_size = 0; |
10452 | ||
4697a36c MM |
10453 | info_ptr->first_fp_reg_save = first_fp_reg_to_save (); |
10454 | info_ptr->fp_size = 8 * (64 - info_ptr->first_fp_reg_save); | |
10455 | ||
00b960c7 AH |
10456 | info_ptr->first_altivec_reg_save = first_altivec_reg_to_save (); |
10457 | info_ptr->altivec_size = 16 * (LAST_ALTIVEC_REGNO + 1 | |
10458 | - info_ptr->first_altivec_reg_save); | |
10459 | ||
592696dd | 10460 | /* Does this function call anything? */ |
71f123ca FS |
10461 | info_ptr->calls_p = (! current_function_is_leaf |
10462 | || cfun->machine->ra_needs_full_frame); | |
b6c9286a | 10463 | |
a4f6c312 | 10464 | /* Determine if we need to save the link register. */ |
71f123ca | 10465 | if (rs6000_ra_ever_killed () |
ffcfcb5f AM |
10466 | || (DEFAULT_ABI == ABI_AIX |
10467 | && current_function_profile | |
10468 | && !TARGET_PROFILE_KERNEL) | |
4697a36c MM |
10469 | #ifdef TARGET_RELOCATABLE |
10470 | || (TARGET_RELOCATABLE && (get_pool_size () != 0)) | |
10471 | #endif | |
10472 | || (info_ptr->first_fp_reg_save != 64 | |
10473 | && !FP_SAVE_INLINE (info_ptr->first_fp_reg_save)) | |
00b960c7 | 10474 | || info_ptr->first_altivec_reg_save <= LAST_ALTIVEC_REGNO |
178274da | 10475 | || (DEFAULT_ABI == ABI_V4 && current_function_calls_alloca) |
a4f6c312 SS |
10476 | || (DEFAULT_ABI == ABI_DARWIN |
10477 | && flag_pic | |
10478 | && current_function_uses_pic_offset_table) | |
4697a36c MM |
10479 | || info_ptr->calls_p) |
10480 | { | |
10481 | info_ptr->lr_save_p = 1; | |
9ebbca7d | 10482 | regs_ever_live[LINK_REGISTER_REGNUM] = 1; |
4697a36c MM |
10483 | } |
10484 | ||
9ebbca7d GK |
10485 | /* Determine if we need to save the condition code registers. */ |
10486 | if (regs_ever_live[CR2_REGNO] | |
10487 | || regs_ever_live[CR3_REGNO] | |
10488 | || regs_ever_live[CR4_REGNO]) | |
4697a36c MM |
10489 | { |
10490 | info_ptr->cr_save_p = 1; | |
178274da | 10491 | if (DEFAULT_ABI == ABI_V4) |
4697a36c MM |
10492 | info_ptr->cr_size = reg_size; |
10493 | } | |
10494 | ||
83720594 RH |
10495 | /* If the current function calls __builtin_eh_return, then we need |
10496 | to allocate stack space for registers that will hold data for | |
10497 | the exception handler. */ | |
10498 | if (current_function_calls_eh_return) | |
10499 | { | |
10500 | unsigned int i; | |
10501 | for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; ++i) | |
10502 | continue; | |
a3170dc6 AH |
10503 | |
10504 | /* SPE saves EH registers in 64-bits. */ | |
c19de7aa AH |
10505 | ehrd_size = i * (TARGET_SPE_ABI |
10506 | && info_ptr->spe_64bit_regs_used != 0 | |
10507 | ? UNITS_PER_SPE_WORD : UNITS_PER_WORD); | |
83720594 RH |
10508 | } |
10509 | else | |
10510 | ehrd_size = 0; | |
10511 | ||
592696dd | 10512 | /* Determine various sizes. */ |
4697a36c MM |
10513 | info_ptr->reg_size = reg_size; |
10514 | info_ptr->fixed_size = RS6000_SAVE_AREA; | |
10515 | info_ptr->varargs_size = RS6000_VARARGS_AREA; | |
189e03e3 | 10516 | info_ptr->vars_size = RS6000_ALIGN (get_frame_size (), 8); |
a4f6c312 SS |
10517 | info_ptr->parm_size = RS6000_ALIGN (current_function_outgoing_args_size, |
10518 | 8); | |
00b960c7 | 10519 | |
c19de7aa | 10520 | if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0) |
a3170dc6 AH |
10521 | info_ptr->spe_gp_size = 8 * (32 - info_ptr->first_gp_reg_save); |
10522 | else | |
10523 | info_ptr->spe_gp_size = 0; | |
10524 | ||
4d774ff8 HP |
10525 | if (TARGET_ALTIVEC_ABI) |
10526 | info_ptr->vrsave_mask = compute_vrsave_mask (); | |
00b960c7 | 10527 | else |
4d774ff8 HP |
10528 | info_ptr->vrsave_mask = 0; |
10529 | ||
10530 | if (TARGET_ALTIVEC_VRSAVE && info_ptr->vrsave_mask) | |
10531 | info_ptr->vrsave_size = 4; | |
10532 | else | |
10533 | info_ptr->vrsave_size = 0; | |
b6c9286a | 10534 | |
592696dd | 10535 | /* Calculate the offsets. */ |
178274da | 10536 | switch (DEFAULT_ABI) |
4697a36c | 10537 | { |
b6c9286a | 10538 | case ABI_NONE: |
24d304eb | 10539 | default: |
b6c9286a MM |
10540 | abort (); |
10541 | ||
10542 | case ABI_AIX: | |
ee890fe2 | 10543 | case ABI_DARWIN: |
b6c9286a MM |
10544 | info_ptr->fp_save_offset = - info_ptr->fp_size; |
10545 | info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size; | |
00b960c7 AH |
10546 | |
10547 | if (TARGET_ALTIVEC_ABI) | |
10548 | { | |
10549 | info_ptr->vrsave_save_offset | |
10550 | = info_ptr->gp_save_offset - info_ptr->vrsave_size; | |
10551 | ||
10552 | /* Align stack so vector save area is on a quadword boundary. */ | |
10553 | if (info_ptr->altivec_size != 0) | |
10554 | info_ptr->altivec_padding_size | |
10555 | = 16 - (-info_ptr->vrsave_save_offset % 16); | |
10556 | else | |
10557 | info_ptr->altivec_padding_size = 0; | |
10558 | ||
10559 | info_ptr->altivec_save_offset | |
10560 | = info_ptr->vrsave_save_offset | |
10561 | - info_ptr->altivec_padding_size | |
10562 | - info_ptr->altivec_size; | |
10563 | ||
10564 | /* Adjust for AltiVec case. */ | |
10565 | info_ptr->ehrd_offset = info_ptr->altivec_save_offset - ehrd_size; | |
10566 | } | |
10567 | else | |
10568 | info_ptr->ehrd_offset = info_ptr->gp_save_offset - ehrd_size; | |
a260abc9 DE |
10569 | info_ptr->cr_save_offset = reg_size; /* first word when 64-bit. */ |
10570 | info_ptr->lr_save_offset = 2*reg_size; | |
24d304eb RK |
10571 | break; |
10572 | ||
10573 | case ABI_V4: | |
b6c9286a MM |
10574 | info_ptr->fp_save_offset = - info_ptr->fp_size; |
10575 | info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size; | |
a7df97e6 | 10576 | info_ptr->cr_save_offset = info_ptr->gp_save_offset - info_ptr->cr_size; |
00b960c7 | 10577 | |
c19de7aa | 10578 | if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0) |
a3170dc6 AH |
10579 | { |
10580 | /* Align stack so SPE GPR save area is aligned on a | |
10581 | double-word boundary. */ | |
10582 | if (info_ptr->spe_gp_size != 0) | |
10583 | info_ptr->spe_padding_size | |
10584 | = 8 - (-info_ptr->cr_save_offset % 8); | |
10585 | else | |
10586 | info_ptr->spe_padding_size = 0; | |
10587 | ||
10588 | info_ptr->spe_gp_save_offset | |
10589 | = info_ptr->cr_save_offset | |
10590 | - info_ptr->spe_padding_size | |
10591 | - info_ptr->spe_gp_size; | |
10592 | ||
10593 | /* Adjust for SPE case. */ | |
10594 | info_ptr->toc_save_offset | |
10595 | = info_ptr->spe_gp_save_offset - info_ptr->toc_size; | |
10596 | } | |
10597 | else if (TARGET_ALTIVEC_ABI) | |
00b960c7 AH |
10598 | { |
10599 | info_ptr->vrsave_save_offset | |
10600 | = info_ptr->cr_save_offset - info_ptr->vrsave_size; | |
10601 | ||
10602 | /* Align stack so vector save area is on a quadword boundary. */ | |
10603 | if (info_ptr->altivec_size != 0) | |
10604 | info_ptr->altivec_padding_size | |
10605 | = 16 - (-info_ptr->vrsave_save_offset % 16); | |
10606 | else | |
10607 | info_ptr->altivec_padding_size = 0; | |
10608 | ||
10609 | info_ptr->altivec_save_offset | |
10610 | = info_ptr->vrsave_save_offset | |
10611 | - info_ptr->altivec_padding_size | |
10612 | - info_ptr->altivec_size; | |
10613 | ||
10614 | /* Adjust for AltiVec case. */ | |
10615 | info_ptr->toc_save_offset | |
10616 | = info_ptr->altivec_save_offset - info_ptr->toc_size; | |
10617 | } | |
10618 | else | |
10619 | info_ptr->toc_save_offset = info_ptr->cr_save_offset - info_ptr->toc_size; | |
83720594 | 10620 | info_ptr->ehrd_offset = info_ptr->toc_save_offset - ehrd_size; |
b6c9286a MM |
10621 | info_ptr->lr_save_offset = reg_size; |
10622 | break; | |
4697a36c MM |
10623 | } |
10624 | ||
00b960c7 AH |
10625 | info_ptr->save_size = RS6000_ALIGN (info_ptr->fp_size |
10626 | + info_ptr->gp_size | |
10627 | + info_ptr->altivec_size | |
10628 | + info_ptr->altivec_padding_size | |
a3170dc6 AH |
10629 | + info_ptr->spe_gp_size |
10630 | + info_ptr->spe_padding_size | |
00b960c7 AH |
10631 | + ehrd_size |
10632 | + info_ptr->cr_size | |
10633 | + info_ptr->lr_size | |
10634 | + info_ptr->vrsave_size | |
10635 | + info_ptr->toc_size, | |
10636 | (TARGET_ALTIVEC_ABI || ABI_DARWIN) | |
10637 | ? 16 : 8); | |
10638 | ||
ff381587 MM |
10639 | total_raw_size = (info_ptr->vars_size |
10640 | + info_ptr->parm_size | |
ff381587 MM |
10641 | + info_ptr->save_size |
10642 | + info_ptr->varargs_size | |
10643 | + info_ptr->fixed_size); | |
10644 | ||
a4f6c312 SS |
10645 | info_ptr->total_size = |
10646 | RS6000_ALIGN (total_raw_size, ABI_STACK_BOUNDARY / BITS_PER_UNIT); | |
ff381587 MM |
10647 | |
10648 | /* Determine if we need to allocate any stack frame: | |
10649 | ||
a4f6c312 SS |
10650 | For AIX we need to push the stack if a frame pointer is needed |
10651 | (because the stack might be dynamically adjusted), if we are | |
10652 | debugging, if we make calls, or if the sum of fp_save, gp_save, | |
10653 | and local variables are more than the space needed to save all | |
10654 | non-volatile registers: 32-bit: 18*8 + 19*4 = 220 or 64-bit: 18*8 | |
10655 | + 18*8 = 288 (GPR13 reserved). | |
ff381587 | 10656 | |
a4f6c312 SS |
10657 | For V.4 we don't have the stack cushion that AIX uses, but assume |
10658 | that the debugger can handle stackless frames. */ | |
ff381587 MM |
10659 | |
10660 | if (info_ptr->calls_p) | |
10661 | info_ptr->push_p = 1; | |
10662 | ||
178274da | 10663 | else if (DEFAULT_ABI == ABI_V4) |
e72247f4 | 10664 | info_ptr->push_p = total_raw_size > info_ptr->fixed_size; |
ff381587 | 10665 | |
178274da AM |
10666 | else if (frame_pointer_needed) |
10667 | info_ptr->push_p = 1; | |
10668 | ||
10669 | else if (TARGET_XCOFF && write_symbols != NO_DEBUG) | |
10670 | info_ptr->push_p = 1; | |
10671 | ||
ff381587 | 10672 | else |
178274da AM |
10673 | info_ptr->push_p |
10674 | = total_raw_size - info_ptr->fixed_size > (TARGET_32BIT ? 220 : 288); | |
ff381587 | 10675 | |
a4f6c312 | 10676 | /* Zero offsets if we're not saving those registers. */ |
8dda1a21 | 10677 | if (info_ptr->fp_size == 0) |
4697a36c MM |
10678 | info_ptr->fp_save_offset = 0; |
10679 | ||
8dda1a21 | 10680 | if (info_ptr->gp_size == 0) |
4697a36c MM |
10681 | info_ptr->gp_save_offset = 0; |
10682 | ||
00b960c7 AH |
10683 | if (! TARGET_ALTIVEC_ABI || info_ptr->altivec_size == 0) |
10684 | info_ptr->altivec_save_offset = 0; | |
10685 | ||
10686 | if (! TARGET_ALTIVEC_ABI || info_ptr->vrsave_mask == 0) | |
10687 | info_ptr->vrsave_save_offset = 0; | |
10688 | ||
c19de7aa AH |
10689 | if (! TARGET_SPE_ABI |
10690 | || info_ptr->spe_64bit_regs_used == 0 | |
10691 | || info_ptr->spe_gp_size == 0) | |
a3170dc6 AH |
10692 | info_ptr->spe_gp_save_offset = 0; |
10693 | ||
c81fc13e | 10694 | if (! info_ptr->lr_save_p) |
4697a36c MM |
10695 | info_ptr->lr_save_offset = 0; |
10696 | ||
c81fc13e | 10697 | if (! info_ptr->cr_save_p) |
4697a36c MM |
10698 | info_ptr->cr_save_offset = 0; |
10699 | ||
c81fc13e | 10700 | if (! info_ptr->toc_save_p) |
b6c9286a MM |
10701 | info_ptr->toc_save_offset = 0; |
10702 | ||
4697a36c MM |
10703 | return info_ptr; |
10704 | } | |
10705 | ||
c19de7aa AH |
10706 | /* Return true if the current function uses any GPRs in 64-bit SIMD |
10707 | mode. */ | |
10708 | ||
10709 | static bool | |
863d938c | 10710 | spe_func_has_64bit_regs_p (void) |
c19de7aa AH |
10711 | { |
10712 | rtx insns, insn; | |
10713 | ||
10714 | /* Functions that save and restore all the call-saved registers will | |
10715 | need to save/restore the registers in 64-bits. */ | |
10716 | if (current_function_calls_eh_return | |
10717 | || current_function_calls_setjmp | |
10718 | || current_function_has_nonlocal_goto) | |
10719 | return true; | |
10720 | ||
10721 | insns = get_insns (); | |
10722 | ||
10723 | for (insn = NEXT_INSN (insns); insn != NULL_RTX; insn = NEXT_INSN (insn)) | |
10724 | { | |
10725 | if (INSN_P (insn)) | |
10726 | { | |
10727 | rtx i; | |
10728 | ||
10729 | i = PATTERN (insn); | |
10730 | if (GET_CODE (i) == SET | |
10731 | && SPE_VECTOR_MODE (GET_MODE (SET_SRC (i)))) | |
10732 | return true; | |
10733 | } | |
10734 | } | |
10735 | ||
10736 | return false; | |
10737 | } | |
10738 | ||
d1d0c603 | 10739 | static void |
a2369ed3 | 10740 | debug_stack_info (rs6000_stack_t *info) |
9878760c | 10741 | { |
d330fd93 | 10742 | const char *abi_string; |
24d304eb | 10743 | |
c81fc13e | 10744 | if (! info) |
4697a36c MM |
10745 | info = rs6000_stack_info (); |
10746 | ||
10747 | fprintf (stderr, "\nStack information for function %s:\n", | |
10748 | ((current_function_decl && DECL_NAME (current_function_decl)) | |
10749 | ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl)) | |
10750 | : "<unknown>")); | |
10751 | ||
24d304eb RK |
10752 | switch (info->abi) |
10753 | { | |
b6c9286a MM |
10754 | default: abi_string = "Unknown"; break; |
10755 | case ABI_NONE: abi_string = "NONE"; break; | |
50d440bc | 10756 | case ABI_AIX: abi_string = "AIX"; break; |
ee890fe2 | 10757 | case ABI_DARWIN: abi_string = "Darwin"; break; |
b6c9286a | 10758 | case ABI_V4: abi_string = "V.4"; break; |
24d304eb RK |
10759 | } |
10760 | ||
10761 | fprintf (stderr, "\tABI = %5s\n", abi_string); | |
10762 | ||
00b960c7 AH |
10763 | if (TARGET_ALTIVEC_ABI) |
10764 | fprintf (stderr, "\tALTIVEC ABI extensions enabled.\n"); | |
10765 | ||
a3170dc6 AH |
10766 | if (TARGET_SPE_ABI) |
10767 | fprintf (stderr, "\tSPE ABI extensions enabled.\n"); | |
10768 | ||
4697a36c MM |
10769 | if (info->first_gp_reg_save != 32) |
10770 | fprintf (stderr, "\tfirst_gp_reg_save = %5d\n", info->first_gp_reg_save); | |
10771 | ||
10772 | if (info->first_fp_reg_save != 64) | |
10773 | fprintf (stderr, "\tfirst_fp_reg_save = %5d\n", info->first_fp_reg_save); | |
9878760c | 10774 | |
00b960c7 AH |
10775 | if (info->first_altivec_reg_save <= LAST_ALTIVEC_REGNO) |
10776 | fprintf (stderr, "\tfirst_altivec_reg_save = %5d\n", | |
10777 | info->first_altivec_reg_save); | |
10778 | ||
4697a36c MM |
10779 | if (info->lr_save_p) |
10780 | fprintf (stderr, "\tlr_save_p = %5d\n", info->lr_save_p); | |
9878760c | 10781 | |
4697a36c MM |
10782 | if (info->cr_save_p) |
10783 | fprintf (stderr, "\tcr_save_p = %5d\n", info->cr_save_p); | |
10784 | ||
b6c9286a MM |
10785 | if (info->toc_save_p) |
10786 | fprintf (stderr, "\ttoc_save_p = %5d\n", info->toc_save_p); | |
10787 | ||
00b960c7 AH |
10788 | if (info->vrsave_mask) |
10789 | fprintf (stderr, "\tvrsave_mask = 0x%x\n", info->vrsave_mask); | |
10790 | ||
4697a36c MM |
10791 | if (info->push_p) |
10792 | fprintf (stderr, "\tpush_p = %5d\n", info->push_p); | |
10793 | ||
10794 | if (info->calls_p) | |
10795 | fprintf (stderr, "\tcalls_p = %5d\n", info->calls_p); | |
10796 | ||
4697a36c MM |
10797 | if (info->gp_save_offset) |
10798 | fprintf (stderr, "\tgp_save_offset = %5d\n", info->gp_save_offset); | |
10799 | ||
10800 | if (info->fp_save_offset) | |
10801 | fprintf (stderr, "\tfp_save_offset = %5d\n", info->fp_save_offset); | |
10802 | ||
00b960c7 AH |
10803 | if (info->altivec_save_offset) |
10804 | fprintf (stderr, "\taltivec_save_offset = %5d\n", | |
10805 | info->altivec_save_offset); | |
10806 | ||
a3170dc6 AH |
10807 | if (info->spe_gp_save_offset) |
10808 | fprintf (stderr, "\tspe_gp_save_offset = %5d\n", | |
10809 | info->spe_gp_save_offset); | |
10810 | ||
00b960c7 AH |
10811 | if (info->vrsave_save_offset) |
10812 | fprintf (stderr, "\tvrsave_save_offset = %5d\n", | |
10813 | info->vrsave_save_offset); | |
10814 | ||
4697a36c MM |
10815 | if (info->lr_save_offset) |
10816 | fprintf (stderr, "\tlr_save_offset = %5d\n", info->lr_save_offset); | |
10817 | ||
10818 | if (info->cr_save_offset) | |
10819 | fprintf (stderr, "\tcr_save_offset = %5d\n", info->cr_save_offset); | |
10820 | ||
b6c9286a MM |
10821 | if (info->toc_save_offset) |
10822 | fprintf (stderr, "\ttoc_save_offset = %5d\n", info->toc_save_offset); | |
10823 | ||
4697a36c MM |
10824 | if (info->varargs_save_offset) |
10825 | fprintf (stderr, "\tvarargs_save_offset = %5d\n", info->varargs_save_offset); | |
10826 | ||
10827 | if (info->total_size) | |
d1d0c603 JJ |
10828 | fprintf (stderr, "\ttotal_size = "HOST_WIDE_INT_PRINT_DEC"\n", |
10829 | info->total_size); | |
4697a36c MM |
10830 | |
10831 | if (info->varargs_size) | |
10832 | fprintf (stderr, "\tvarargs_size = %5d\n", info->varargs_size); | |
10833 | ||
10834 | if (info->vars_size) | |
d1d0c603 JJ |
10835 | fprintf (stderr, "\tvars_size = "HOST_WIDE_INT_PRINT_DEC"\n", |
10836 | info->vars_size); | |
4697a36c MM |
10837 | |
10838 | if (info->parm_size) | |
10839 | fprintf (stderr, "\tparm_size = %5d\n", info->parm_size); | |
10840 | ||
10841 | if (info->fixed_size) | |
10842 | fprintf (stderr, "\tfixed_size = %5d\n", info->fixed_size); | |
10843 | ||
10844 | if (info->gp_size) | |
10845 | fprintf (stderr, "\tgp_size = %5d\n", info->gp_size); | |
10846 | ||
a3170dc6 AH |
10847 | if (info->spe_gp_size) |
10848 | fprintf (stderr, "\tspe_gp_size = %5d\n", info->spe_gp_size); | |
10849 | ||
4697a36c MM |
10850 | if (info->fp_size) |
10851 | fprintf (stderr, "\tfp_size = %5d\n", info->fp_size); | |
10852 | ||
00b960c7 AH |
10853 | if (info->altivec_size) |
10854 | fprintf (stderr, "\taltivec_size = %5d\n", info->altivec_size); | |
10855 | ||
10856 | if (info->vrsave_size) | |
10857 | fprintf (stderr, "\tvrsave_size = %5d\n", info->vrsave_size); | |
10858 | ||
10859 | if (info->altivec_padding_size) | |
10860 | fprintf (stderr, "\taltivec_padding_size= %5d\n", | |
10861 | info->altivec_padding_size); | |
10862 | ||
a3170dc6 AH |
10863 | if (info->spe_padding_size) |
10864 | fprintf (stderr, "\tspe_padding_size = %5d\n", | |
10865 | info->spe_padding_size); | |
10866 | ||
a4f6c312 | 10867 | if (info->lr_size) |
ed947a96 | 10868 | fprintf (stderr, "\tlr_size = %5d\n", info->lr_size); |
b6c9286a | 10869 | |
4697a36c MM |
10870 | if (info->cr_size) |
10871 | fprintf (stderr, "\tcr_size = %5d\n", info->cr_size); | |
10872 | ||
a4f6c312 | 10873 | if (info->toc_size) |
b6c9286a MM |
10874 | fprintf (stderr, "\ttoc_size = %5d\n", info->toc_size); |
10875 | ||
4697a36c MM |
10876 | if (info->save_size) |
10877 | fprintf (stderr, "\tsave_size = %5d\n", info->save_size); | |
10878 | ||
10879 | if (info->reg_size != 4) | |
10880 | fprintf (stderr, "\treg_size = %5d\n", info->reg_size); | |
10881 | ||
10882 | fprintf (stderr, "\n"); | |
9878760c | 10883 | } |
71f123ca FS |
10884 | |
10885 | rtx | |
a2369ed3 | 10886 | rs6000_return_addr (int count, rtx frame) |
71f123ca | 10887 | { |
a4f6c312 SS |
10888 | /* Currently we don't optimize very well between prolog and body |
10889 | code and for PIC code the code can be actually quite bad, so | |
10890 | don't try to be too clever here. */ | |
f1384257 | 10891 | if (count != 0 || (DEFAULT_ABI != ABI_AIX && flag_pic)) |
71f123ca FS |
10892 | { |
10893 | cfun->machine->ra_needs_full_frame = 1; | |
8ac61af7 RK |
10894 | |
10895 | return | |
10896 | gen_rtx_MEM | |
10897 | (Pmode, | |
10898 | memory_address | |
10899 | (Pmode, | |
10900 | plus_constant (copy_to_reg | |
10901 | (gen_rtx_MEM (Pmode, | |
10902 | memory_address (Pmode, frame))), | |
10903 | RETURN_ADDRESS_OFFSET))); | |
71f123ca FS |
10904 | } |
10905 | ||
8c29550d | 10906 | cfun->machine->ra_need_lr = 1; |
9e2f7ec7 | 10907 | return get_hard_reg_initial_val (Pmode, LINK_REGISTER_REGNUM); |
71f123ca FS |
10908 | } |
10909 | ||
5e1bf043 DJ |
10910 | /* Say whether a function is a candidate for sibcall handling or not. |
10911 | We do not allow indirect calls to be optimized into sibling calls. | |
10912 | Also, we can't do it if there are any vector parameters; there's | |
10913 | nowhere to put the VRsave code so it works; note that functions with | |
10914 | vector parameters are required to have a prototype, so the argument | |
10915 | type info must be available here. (The tail recursion case can work | |
10916 | with vector parameters, but there's no way to distinguish here.) */ | |
4977bab6 | 10917 | static bool |
a2369ed3 | 10918 | rs6000_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED) |
5e1bf043 DJ |
10919 | { |
10920 | tree type; | |
4977bab6 | 10921 | if (decl) |
5e1bf043 DJ |
10922 | { |
10923 | if (TARGET_ALTIVEC_VRSAVE) | |
10924 | { | |
4977bab6 | 10925 | for (type = TYPE_ARG_TYPES (TREE_TYPE (decl)); |
5e1bf043 DJ |
10926 | type; type = TREE_CHAIN (type)) |
10927 | { | |
c15b529f | 10928 | if (TREE_CODE (TREE_VALUE (type)) == VECTOR_TYPE) |
4977bab6 | 10929 | return false; |
5e1bf043 DJ |
10930 | } |
10931 | } | |
10932 | if (DEFAULT_ABI == ABI_DARWIN | |
4977bab6 | 10933 | || (*targetm.binds_local_p) (decl)) |
2bcc50d0 | 10934 | { |
4977bab6 | 10935 | tree attr_list = TYPE_ATTRIBUTES (TREE_TYPE (decl)); |
2bcc50d0 AM |
10936 | |
10937 | if (!lookup_attribute ("longcall", attr_list) | |
10938 | || lookup_attribute ("shortcall", attr_list)) | |
4977bab6 | 10939 | return true; |
2bcc50d0 | 10940 | } |
5e1bf043 | 10941 | } |
4977bab6 | 10942 | return false; |
5e1bf043 DJ |
10943 | } |
10944 | ||
71f123ca | 10945 | static int |
863d938c | 10946 | rs6000_ra_ever_killed (void) |
71f123ca FS |
10947 | { |
10948 | rtx top; | |
5e1bf043 DJ |
10949 | rtx reg; |
10950 | rtx insn; | |
71f123ca | 10951 | |
dd292d0a | 10952 | if (current_function_is_thunk) |
71f123ca | 10953 | return 0; |
eb0424da | 10954 | |
36f7e964 AH |
10955 | /* regs_ever_live has LR marked as used if any sibcalls are present, |
10956 | but this should not force saving and restoring in the | |
10957 | pro/epilogue. Likewise, reg_set_between_p thinks a sibcall | |
a3c9585f | 10958 | clobbers LR, so that is inappropriate. */ |
36f7e964 | 10959 | |
5e1bf043 DJ |
10960 | /* Also, the prologue can generate a store into LR that |
10961 | doesn't really count, like this: | |
36f7e964 | 10962 | |
5e1bf043 DJ |
10963 | move LR->R0 |
10964 | bcl to set PIC register | |
10965 | move LR->R31 | |
10966 | move R0->LR | |
36f7e964 AH |
10967 | |
10968 | When we're called from the epilogue, we need to avoid counting | |
10969 | this as a store. */ | |
5e1bf043 | 10970 | |
71f123ca FS |
10971 | push_topmost_sequence (); |
10972 | top = get_insns (); | |
10973 | pop_topmost_sequence (); | |
5e1bf043 | 10974 | reg = gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM); |
71f123ca | 10975 | |
5e1bf043 DJ |
10976 | for (insn = NEXT_INSN (top); insn != NULL_RTX; insn = NEXT_INSN (insn)) |
10977 | { | |
10978 | if (INSN_P (insn)) | |
10979 | { | |
10980 | if (FIND_REG_INC_NOTE (insn, reg)) | |
10981 | return 1; | |
10982 | else if (GET_CODE (insn) == CALL_INSN | |
c15b529f | 10983 | && !SIBLING_CALL_P (insn)) |
5e1bf043 | 10984 | return 1; |
36f7e964 AH |
10985 | else if (set_of (reg, insn) != NULL_RTX |
10986 | && !prologue_epilogue_contains (insn)) | |
5e1bf043 DJ |
10987 | return 1; |
10988 | } | |
10989 | } | |
10990 | return 0; | |
71f123ca | 10991 | } |
4697a36c | 10992 | \f |
8cd8f856 GK |
10993 | /* Add a REG_MAYBE_DEAD note to the insn. */ |
10994 | static void | |
a2369ed3 | 10995 | rs6000_maybe_dead (rtx insn) |
8cd8f856 GK |
10996 | { |
10997 | REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD, | |
10998 | const0_rtx, | |
10999 | REG_NOTES (insn)); | |
11000 | } | |
11001 | ||
9ebbca7d | 11002 | /* Emit instructions needed to load the TOC register. |
c7ca610e | 11003 | This is only needed when TARGET_TOC, TARGET_MINIMAL_TOC, and there is |
9ebbca7d | 11004 | a constant pool; or for SVR4 -fpic. */ |
c7ca610e RK |
11005 | |
11006 | void | |
a2369ed3 | 11007 | rs6000_emit_load_toc_table (int fromprolog) |
c7ca610e | 11008 | { |
027fbf43 | 11009 | rtx dest, insn; |
1db02437 | 11010 | dest = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM); |
c7ca610e | 11011 | |
20b71b17 AM |
11012 | if (TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 1) |
11013 | { | |
11014 | rtx temp = (fromprolog | |
11015 | ? gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM) | |
11016 | : gen_reg_rtx (Pmode)); | |
027fbf43 JJ |
11017 | insn = emit_insn (gen_load_toc_v4_pic_si (temp)); |
11018 | if (fromprolog) | |
11019 | rs6000_maybe_dead (insn); | |
11020 | insn = emit_move_insn (dest, temp); | |
11021 | if (fromprolog) | |
11022 | rs6000_maybe_dead (insn); | |
20b71b17 AM |
11023 | } |
11024 | else if (TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2) | |
11025 | { | |
11026 | char buf[30]; | |
11027 | rtx tempLR = (fromprolog | |
11028 | ? gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM) | |
11029 | : gen_reg_rtx (Pmode)); | |
11030 | rtx temp0 = (fromprolog | |
11031 | ? gen_rtx_REG (Pmode, 0) | |
11032 | : gen_reg_rtx (Pmode)); | |
11033 | rtx symF; | |
11034 | ||
11035 | /* possibly create the toc section */ | |
11036 | if (! toc_initialized) | |
38c1f2d7 | 11037 | { |
20b71b17 AM |
11038 | toc_section (); |
11039 | function_section (current_function_decl); | |
38c1f2d7 | 11040 | } |
9ebbca7d | 11041 | |
20b71b17 AM |
11042 | if (fromprolog) |
11043 | { | |
11044 | rtx symL; | |
38c1f2d7 | 11045 | |
20b71b17 AM |
11046 | ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno); |
11047 | symF = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); | |
9ebbca7d | 11048 | |
20b71b17 AM |
11049 | ASM_GENERATE_INTERNAL_LABEL (buf, "LCL", rs6000_pic_labelno); |
11050 | symL = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); | |
11051 | ||
11052 | rs6000_maybe_dead (emit_insn (gen_load_toc_v4_PIC_1 (tempLR, | |
11053 | symF))); | |
11054 | rs6000_maybe_dead (emit_move_insn (dest, tempLR)); | |
11055 | rs6000_maybe_dead (emit_insn (gen_load_toc_v4_PIC_2 (temp0, dest, | |
11056 | symL, | |
11057 | symF))); | |
9ebbca7d GK |
11058 | } |
11059 | else | |
20b71b17 AM |
11060 | { |
11061 | rtx tocsym; | |
11062 | static int reload_toc_labelno = 0; | |
11063 | ||
11064 | tocsym = gen_rtx_SYMBOL_REF (Pmode, toc_label_name); | |
11065 | ||
11066 | ASM_GENERATE_INTERNAL_LABEL (buf, "LCG", reload_toc_labelno++); | |
11067 | symF = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); | |
11068 | ||
027fbf43 JJ |
11069 | emit_insn (gen_load_toc_v4_PIC_1b (tempLR, symF, tocsym)); |
11070 | emit_move_insn (dest, tempLR); | |
11071 | emit_move_insn (temp0, gen_rtx_MEM (Pmode, dest)); | |
20b71b17 | 11072 | } |
027fbf43 JJ |
11073 | insn = emit_insn (gen_addsi3 (dest, temp0, dest)); |
11074 | if (fromprolog) | |
11075 | rs6000_maybe_dead (insn); | |
9ebbca7d | 11076 | } |
20b71b17 AM |
11077 | else if (TARGET_ELF && !TARGET_AIX && flag_pic == 0 && TARGET_MINIMAL_TOC) |
11078 | { | |
11079 | /* This is for AIX code running in non-PIC ELF32. */ | |
11080 | char buf[30]; | |
11081 | rtx realsym; | |
11082 | ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1); | |
11083 | realsym = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); | |
11084 | ||
027fbf43 JJ |
11085 | insn = emit_insn (gen_elf_high (dest, realsym)); |
11086 | if (fromprolog) | |
11087 | rs6000_maybe_dead (insn); | |
11088 | insn = emit_insn (gen_elf_low (dest, dest, realsym)); | |
11089 | if (fromprolog) | |
11090 | rs6000_maybe_dead (insn); | |
20b71b17 AM |
11091 | } |
11092 | else if (DEFAULT_ABI == ABI_AIX) | |
9ebbca7d GK |
11093 | { |
11094 | if (TARGET_32BIT) | |
027fbf43 | 11095 | insn = emit_insn (gen_load_toc_aix_si (dest)); |
9ebbca7d | 11096 | else |
027fbf43 JJ |
11097 | insn = emit_insn (gen_load_toc_aix_di (dest)); |
11098 | if (fromprolog) | |
11099 | rs6000_maybe_dead (insn); | |
9ebbca7d | 11100 | } |
20b71b17 AM |
11101 | else |
11102 | abort (); | |
9ebbca7d GK |
11103 | } |
11104 | ||
d1d0c603 JJ |
11105 | /* Emit instructions to restore the link register after determining where |
11106 | its value has been stored. */ | |
11107 | ||
11108 | void | |
11109 | rs6000_emit_eh_reg_restore (rtx source, rtx scratch) | |
11110 | { | |
11111 | rs6000_stack_t *info = rs6000_stack_info (); | |
11112 | rtx operands[2]; | |
11113 | ||
11114 | operands[0] = source; | |
11115 | operands[1] = scratch; | |
11116 | ||
11117 | if (info->lr_save_p) | |
11118 | { | |
11119 | rtx frame_rtx = stack_pointer_rtx; | |
11120 | HOST_WIDE_INT sp_offset = 0; | |
11121 | rtx tmp; | |
11122 | ||
11123 | if (frame_pointer_needed | |
11124 | || current_function_calls_alloca | |
11125 | || info->total_size > 32767) | |
11126 | { | |
11127 | emit_move_insn (operands[1], gen_rtx_MEM (Pmode, frame_rtx)); | |
11128 | frame_rtx = operands[1]; | |
11129 | } | |
11130 | else if (info->push_p) | |
11131 | sp_offset = info->total_size; | |
11132 | ||
11133 | tmp = plus_constant (frame_rtx, info->lr_save_offset + sp_offset); | |
11134 | tmp = gen_rtx_MEM (Pmode, tmp); | |
11135 | emit_move_insn (tmp, operands[0]); | |
11136 | } | |
11137 | else | |
11138 | emit_move_insn (gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM), operands[0]); | |
11139 | } | |
11140 | ||
f103e34d GK |
11141 | static GTY(()) int set = -1; |
11142 | ||
9ebbca7d | 11143 | int |
863d938c | 11144 | get_TOC_alias_set (void) |
9ebbca7d | 11145 | { |
f103e34d GK |
11146 | if (set == -1) |
11147 | set = new_alias_set (); | |
11148 | return set; | |
9ebbca7d GK |
11149 | } |
11150 | ||
c1207243 | 11151 | /* This returns nonzero if the current function uses the TOC. This is |
3c9eb5f4 AM |
11152 | determined by the presence of (use (unspec ... UNSPEC_TOC)), which |
11153 | is generated by the ABI_V4 load_toc_* patterns. */ | |
c954844a | 11154 | #if TARGET_ELF |
3c9eb5f4 | 11155 | static int |
38f391a5 | 11156 | uses_TOC (void) |
9ebbca7d | 11157 | { |
c4501e62 | 11158 | rtx insn; |
38c1f2d7 | 11159 | |
c4501e62 JJ |
11160 | for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) |
11161 | if (INSN_P (insn)) | |
11162 | { | |
11163 | rtx pat = PATTERN (insn); | |
11164 | int i; | |
9ebbca7d | 11165 | |
c4501e62 JJ |
11166 | if (GET_CODE (pat) == PARALLEL) |
11167 | for (i = 0; i < XVECLEN (pat, 0); i++) | |
11168 | { | |
11169 | rtx sub = XVECEXP (pat, 0, i); | |
11170 | if (GET_CODE (sub) == USE) | |
11171 | { | |
11172 | sub = XEXP (sub, 0); | |
11173 | if (GET_CODE (sub) == UNSPEC | |
11174 | && XINT (sub, 1) == UNSPEC_TOC) | |
11175 | return 1; | |
11176 | } | |
11177 | } | |
11178 | } | |
11179 | return 0; | |
9ebbca7d | 11180 | } |
c954844a | 11181 | #endif |
38c1f2d7 | 11182 | |
9ebbca7d | 11183 | rtx |
a2369ed3 | 11184 | create_TOC_reference (rtx symbol) |
9ebbca7d | 11185 | { |
a8a05998 ZW |
11186 | return gen_rtx_PLUS (Pmode, |
11187 | gen_rtx_REG (Pmode, TOC_REGISTER), | |
11188 | gen_rtx_CONST (Pmode, | |
11189 | gen_rtx_MINUS (Pmode, symbol, | |
b999aaeb | 11190 | gen_rtx_SYMBOL_REF (Pmode, toc_label_name)))); |
9ebbca7d | 11191 | } |
38c1f2d7 | 11192 | |
fc4767bb JJ |
11193 | /* If _Unwind_* has been called from within the same module, |
11194 | toc register is not guaranteed to be saved to 40(1) on function | |
11195 | entry. Save it there in that case. */ | |
c7ca610e | 11196 | |
9ebbca7d | 11197 | void |
863d938c | 11198 | rs6000_aix_emit_builtin_unwind_init (void) |
9ebbca7d GK |
11199 | { |
11200 | rtx mem; | |
11201 | rtx stack_top = gen_reg_rtx (Pmode); | |
11202 | rtx opcode_addr = gen_reg_rtx (Pmode); | |
fc4767bb JJ |
11203 | rtx opcode = gen_reg_rtx (SImode); |
11204 | rtx tocompare = gen_reg_rtx (SImode); | |
11205 | rtx no_toc_save_needed = gen_label_rtx (); | |
9ebbca7d GK |
11206 | |
11207 | mem = gen_rtx_MEM (Pmode, hard_frame_pointer_rtx); | |
11208 | emit_move_insn (stack_top, mem); | |
11209 | ||
fc4767bb JJ |
11210 | mem = gen_rtx_MEM (Pmode, |
11211 | gen_rtx_PLUS (Pmode, stack_top, | |
9ebbca7d GK |
11212 | GEN_INT (2 * GET_MODE_SIZE (Pmode)))); |
11213 | emit_move_insn (opcode_addr, mem); | |
fc4767bb JJ |
11214 | emit_move_insn (opcode, gen_rtx_MEM (SImode, opcode_addr)); |
11215 | emit_move_insn (tocompare, gen_int_mode (TARGET_32BIT ? 0x80410014 | |
2496c7bd | 11216 | : 0xE8410028, SImode)); |
9ebbca7d | 11217 | |
fc4767bb | 11218 | do_compare_rtx_and_jump (opcode, tocompare, EQ, 1, |
06f4e019 | 11219 | SImode, NULL_RTX, NULL_RTX, |
fc4767bb | 11220 | no_toc_save_needed); |
9ebbca7d | 11221 | |
fc4767bb JJ |
11222 | mem = gen_rtx_MEM (Pmode, |
11223 | gen_rtx_PLUS (Pmode, stack_top, | |
11224 | GEN_INT (5 * GET_MODE_SIZE (Pmode)))); | |
11225 | emit_move_insn (mem, gen_rtx_REG (Pmode, 2)); | |
11226 | emit_label (no_toc_save_needed); | |
9ebbca7d | 11227 | } |
38c1f2d7 | 11228 | \f |
ba4828e0 RK |
11229 | /* This ties together stack memory (MEM with an alias set of |
11230 | rs6000_sr_alias_set) and the change to the stack pointer. */ | |
11231 | ||
9ebbca7d | 11232 | static void |
863d938c | 11233 | rs6000_emit_stack_tie (void) |
9ebbca7d | 11234 | { |
ba4828e0 RK |
11235 | rtx mem = gen_rtx_MEM (BLKmode, gen_rtx_REG (Pmode, STACK_POINTER_REGNUM)); |
11236 | ||
11237 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
9ebbca7d GK |
11238 | emit_insn (gen_stack_tie (mem)); |
11239 | } | |
38c1f2d7 | 11240 | |
9ebbca7d GK |
11241 | /* Emit the correct code for allocating stack space, as insns. |
11242 | If COPY_R12, make sure a copy of the old frame is left in r12. | |
11243 | The generated code may use hard register 0 as a temporary. */ | |
11244 | ||
11245 | static void | |
a2369ed3 | 11246 | rs6000_emit_allocate_stack (HOST_WIDE_INT size, int copy_r12) |
38c1f2d7 | 11247 | { |
9ebbca7d GK |
11248 | rtx insn; |
11249 | rtx stack_reg = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM); | |
11250 | rtx tmp_reg = gen_rtx_REG (Pmode, 0); | |
11251 | rtx todec = GEN_INT (-size); | |
a157febd GK |
11252 | |
11253 | if (current_function_limit_stack) | |
11254 | { | |
11255 | if (REG_P (stack_limit_rtx) | |
11256 | && REGNO (stack_limit_rtx) > 1 | |
11257 | && REGNO (stack_limit_rtx) <= 31) | |
11258 | { | |
5b71a4e7 | 11259 | emit_insn (TARGET_32BIT |
9ebbca7d GK |
11260 | ? gen_addsi3 (tmp_reg, |
11261 | stack_limit_rtx, | |
11262 | GEN_INT (size)) | |
11263 | : gen_adddi3 (tmp_reg, | |
11264 | stack_limit_rtx, | |
11265 | GEN_INT (size))); | |
5b71a4e7 | 11266 | |
9ebbca7d GK |
11267 | emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg, |
11268 | const0_rtx)); | |
a157febd GK |
11269 | } |
11270 | else if (GET_CODE (stack_limit_rtx) == SYMBOL_REF | |
9ebbca7d | 11271 | && TARGET_32BIT |
f607bc57 | 11272 | && DEFAULT_ABI == ABI_V4) |
a157febd | 11273 | { |
9ebbca7d GK |
11274 | rtx toload = gen_rtx_CONST (VOIDmode, |
11275 | gen_rtx_PLUS (Pmode, | |
11276 | stack_limit_rtx, | |
11277 | GEN_INT (size))); | |
5b71a4e7 | 11278 | |
9ebbca7d GK |
11279 | emit_insn (gen_elf_high (tmp_reg, toload)); |
11280 | emit_insn (gen_elf_low (tmp_reg, tmp_reg, toload)); | |
11281 | emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg, | |
11282 | const0_rtx)); | |
a157febd GK |
11283 | } |
11284 | else | |
11285 | warning ("stack limit expression is not supported"); | |
11286 | } | |
11287 | ||
9ebbca7d GK |
11288 | if (copy_r12 || ! TARGET_UPDATE) |
11289 | emit_move_insn (gen_rtx_REG (Pmode, 12), stack_reg); | |
11290 | ||
38c1f2d7 MM |
11291 | if (TARGET_UPDATE) |
11292 | { | |
9ebbca7d | 11293 | if (size > 32767) |
38c1f2d7 | 11294 | { |
9ebbca7d GK |
11295 | /* Need a note here so that try_split doesn't get confused. */ |
11296 | if (get_last_insn() == NULL_RTX) | |
2e040219 | 11297 | emit_note (NOTE_INSN_DELETED); |
9ebbca7d GK |
11298 | insn = emit_move_insn (tmp_reg, todec); |
11299 | try_split (PATTERN (insn), insn, 0); | |
11300 | todec = tmp_reg; | |
38c1f2d7 | 11301 | } |
5b71a4e7 DE |
11302 | |
11303 | insn = emit_insn (TARGET_32BIT | |
11304 | ? gen_movsi_update (stack_reg, stack_reg, | |
11305 | todec, stack_reg) | |
11306 | : gen_movdi_update (stack_reg, stack_reg, | |
9ebbca7d | 11307 | todec, stack_reg)); |
38c1f2d7 MM |
11308 | } |
11309 | else | |
11310 | { | |
5b71a4e7 DE |
11311 | insn = emit_insn (TARGET_32BIT |
11312 | ? gen_addsi3 (stack_reg, stack_reg, todec) | |
11313 | : gen_adddi3 (stack_reg, stack_reg, todec)); | |
9ebbca7d GK |
11314 | emit_move_insn (gen_rtx_MEM (Pmode, stack_reg), |
11315 | gen_rtx_REG (Pmode, 12)); | |
11316 | } | |
5b71a4e7 | 11317 | |
9ebbca7d GK |
11318 | RTX_FRAME_RELATED_P (insn) = 1; |
11319 | REG_NOTES (insn) = | |
11320 | gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, | |
11321 | gen_rtx_SET (VOIDmode, stack_reg, | |
11322 | gen_rtx_PLUS (Pmode, stack_reg, | |
11323 | GEN_INT (-size))), | |
11324 | REG_NOTES (insn)); | |
11325 | } | |
11326 | ||
a4f6c312 SS |
11327 | /* Add to 'insn' a note which is PATTERN (INSN) but with REG replaced |
11328 | with (plus:P (reg 1) VAL), and with REG2 replaced with RREG if REG2 | |
11329 | is not NULL. It would be nice if dwarf2out_frame_debug_expr could | |
11330 | deduce these equivalences by itself so it wasn't necessary to hold | |
11331 | its hand so much. */ | |
9ebbca7d GK |
11332 | |
11333 | static void | |
a2369ed3 DJ |
11334 | rs6000_frame_related (rtx insn, rtx reg, HOST_WIDE_INT val, |
11335 | rtx reg2, rtx rreg) | |
9ebbca7d GK |
11336 | { |
11337 | rtx real, temp; | |
11338 | ||
e56c4463 JL |
11339 | /* copy_rtx will not make unique copies of registers, so we need to |
11340 | ensure we don't have unwanted sharing here. */ | |
11341 | if (reg == reg2) | |
11342 | reg = gen_raw_REG (GET_MODE (reg), REGNO (reg)); | |
11343 | ||
11344 | if (reg == rreg) | |
11345 | reg = gen_raw_REG (GET_MODE (reg), REGNO (reg)); | |
11346 | ||
9ebbca7d GK |
11347 | real = copy_rtx (PATTERN (insn)); |
11348 | ||
89e7058f AH |
11349 | if (reg2 != NULL_RTX) |
11350 | real = replace_rtx (real, reg2, rreg); | |
11351 | ||
9ebbca7d GK |
11352 | real = replace_rtx (real, reg, |
11353 | gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode, | |
11354 | STACK_POINTER_REGNUM), | |
11355 | GEN_INT (val))); | |
11356 | ||
11357 | /* We expect that 'real' is either a SET or a PARALLEL containing | |
11358 | SETs (and possibly other stuff). In a PARALLEL, all the SETs | |
11359 | are important so they all have to be marked RTX_FRAME_RELATED_P. */ | |
11360 | ||
11361 | if (GET_CODE (real) == SET) | |
11362 | { | |
11363 | rtx set = real; | |
11364 | ||
11365 | temp = simplify_rtx (SET_SRC (set)); | |
11366 | if (temp) | |
11367 | SET_SRC (set) = temp; | |
11368 | temp = simplify_rtx (SET_DEST (set)); | |
11369 | if (temp) | |
11370 | SET_DEST (set) = temp; | |
11371 | if (GET_CODE (SET_DEST (set)) == MEM) | |
38c1f2d7 | 11372 | { |
9ebbca7d GK |
11373 | temp = simplify_rtx (XEXP (SET_DEST (set), 0)); |
11374 | if (temp) | |
11375 | XEXP (SET_DEST (set), 0) = temp; | |
38c1f2d7 | 11376 | } |
38c1f2d7 | 11377 | } |
9ebbca7d GK |
11378 | else if (GET_CODE (real) == PARALLEL) |
11379 | { | |
11380 | int i; | |
11381 | for (i = 0; i < XVECLEN (real, 0); i++) | |
11382 | if (GET_CODE (XVECEXP (real, 0, i)) == SET) | |
11383 | { | |
11384 | rtx set = XVECEXP (real, 0, i); | |
11385 | ||
11386 | temp = simplify_rtx (SET_SRC (set)); | |
11387 | if (temp) | |
11388 | SET_SRC (set) = temp; | |
11389 | temp = simplify_rtx (SET_DEST (set)); | |
11390 | if (temp) | |
11391 | SET_DEST (set) = temp; | |
11392 | if (GET_CODE (SET_DEST (set)) == MEM) | |
11393 | { | |
11394 | temp = simplify_rtx (XEXP (SET_DEST (set), 0)); | |
11395 | if (temp) | |
11396 | XEXP (SET_DEST (set), 0) = temp; | |
11397 | } | |
11398 | RTX_FRAME_RELATED_P (set) = 1; | |
11399 | } | |
11400 | } | |
11401 | else | |
a4f6c312 | 11402 | abort (); |
c19de7aa AH |
11403 | |
11404 | if (TARGET_SPE) | |
11405 | real = spe_synthesize_frame_save (real); | |
11406 | ||
9ebbca7d GK |
11407 | RTX_FRAME_RELATED_P (insn) = 1; |
11408 | REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, | |
11409 | real, | |
11410 | REG_NOTES (insn)); | |
38c1f2d7 MM |
11411 | } |
11412 | ||
c19de7aa AH |
11413 | /* Given an SPE frame note, return a PARALLEL of SETs with the |
11414 | original note, plus a synthetic register save. */ | |
11415 | ||
11416 | static rtx | |
a2369ed3 | 11417 | spe_synthesize_frame_save (rtx real) |
c19de7aa AH |
11418 | { |
11419 | rtx synth, offset, reg, real2; | |
11420 | ||
11421 | if (GET_CODE (real) != SET | |
11422 | || GET_MODE (SET_SRC (real)) != V2SImode) | |
11423 | return real; | |
11424 | ||
11425 | /* For the SPE, registers saved in 64-bits, get a PARALLEL for their | |
11426 | frame related note. The parallel contains a set of the register | |
41f3a930 | 11427 | being saved, and another set to a synthetic register (n+1200). |
c19de7aa AH |
11428 | This is so we can differentiate between 64-bit and 32-bit saves. |
11429 | Words cannot describe this nastiness. */ | |
11430 | ||
11431 | if (GET_CODE (SET_DEST (real)) != MEM | |
11432 | || GET_CODE (XEXP (SET_DEST (real), 0)) != PLUS | |
11433 | || GET_CODE (SET_SRC (real)) != REG) | |
11434 | abort (); | |
11435 | ||
11436 | /* Transform: | |
11437 | (set (mem (plus (reg x) (const y))) | |
11438 | (reg z)) | |
11439 | into: | |
11440 | (set (mem (plus (reg x) (const y+4))) | |
41f3a930 | 11441 | (reg z+1200)) |
c19de7aa AH |
11442 | */ |
11443 | ||
11444 | real2 = copy_rtx (real); | |
11445 | PUT_MODE (SET_DEST (real2), SImode); | |
11446 | reg = SET_SRC (real2); | |
11447 | real2 = replace_rtx (real2, reg, gen_rtx_REG (SImode, REGNO (reg))); | |
11448 | synth = copy_rtx (real2); | |
11449 | ||
11450 | if (BYTES_BIG_ENDIAN) | |
11451 | { | |
11452 | offset = XEXP (XEXP (SET_DEST (real2), 0), 1); | |
11453 | real2 = replace_rtx (real2, offset, GEN_INT (INTVAL (offset) + 4)); | |
11454 | } | |
11455 | ||
11456 | reg = SET_SRC (synth); | |
41f3a930 | 11457 | |
c19de7aa | 11458 | synth = replace_rtx (synth, reg, |
41f3a930 | 11459 | gen_rtx_REG (SImode, REGNO (reg) + 1200)); |
c19de7aa AH |
11460 | |
11461 | offset = XEXP (XEXP (SET_DEST (synth), 0), 1); | |
11462 | synth = replace_rtx (synth, offset, | |
11463 | GEN_INT (INTVAL (offset) | |
11464 | + (BYTES_BIG_ENDIAN ? 0 : 4))); | |
11465 | ||
11466 | RTX_FRAME_RELATED_P (synth) = 1; | |
11467 | RTX_FRAME_RELATED_P (real2) = 1; | |
11468 | if (BYTES_BIG_ENDIAN) | |
11469 | real = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, synth, real2)); | |
11470 | else | |
11471 | real = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, real2, synth)); | |
11472 | ||
11473 | return real; | |
11474 | } | |
11475 | ||
00b960c7 AH |
11476 | /* Returns an insn that has a vrsave set operation with the |
11477 | appropriate CLOBBERs. */ | |
11478 | ||
11479 | static rtx | |
a2369ed3 | 11480 | generate_set_vrsave (rtx reg, rs6000_stack_t *info, int epiloguep) |
00b960c7 AH |
11481 | { |
11482 | int nclobs, i; | |
11483 | rtx insn, clobs[TOTAL_ALTIVEC_REGS + 1]; | |
a004eb82 | 11484 | rtx vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO); |
00b960c7 | 11485 | |
a004eb82 AH |
11486 | clobs[0] |
11487 | = gen_rtx_SET (VOIDmode, | |
11488 | vrsave, | |
11489 | gen_rtx_UNSPEC_VOLATILE (SImode, | |
11490 | gen_rtvec (2, reg, vrsave), | |
11491 | 30)); | |
00b960c7 AH |
11492 | |
11493 | nclobs = 1; | |
11494 | ||
9aa86737 AH |
11495 | /* We need to clobber the registers in the mask so the scheduler |
11496 | does not move sets to VRSAVE before sets of AltiVec registers. | |
11497 | ||
11498 | However, if the function receives nonlocal gotos, reload will set | |
11499 | all call saved registers live. We will end up with: | |
11500 | ||
11501 | (set (reg 999) (mem)) | |
11502 | (parallel [ (set (reg vrsave) (unspec blah)) | |
11503 | (clobber (reg 999))]) | |
11504 | ||
11505 | The clobber will cause the store into reg 999 to be dead, and | |
11506 | flow will attempt to delete an epilogue insn. In this case, we | |
11507 | need an unspec use/set of the register. */ | |
00b960c7 AH |
11508 | |
11509 | for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i) | |
11510 | if (info->vrsave_mask != 0 && ALTIVEC_REG_BIT (i) != 0) | |
9aa86737 AH |
11511 | { |
11512 | if (!epiloguep || call_used_regs [i]) | |
11513 | clobs[nclobs++] = gen_rtx_CLOBBER (VOIDmode, | |
11514 | gen_rtx_REG (V4SImode, i)); | |
11515 | else | |
11516 | { | |
11517 | rtx reg = gen_rtx_REG (V4SImode, i); | |
9aa86737 AH |
11518 | |
11519 | clobs[nclobs++] | |
a004eb82 AH |
11520 | = gen_rtx_SET (VOIDmode, |
11521 | reg, | |
11522 | gen_rtx_UNSPEC (V4SImode, | |
11523 | gen_rtvec (1, reg), 27)); | |
9aa86737 AH |
11524 | } |
11525 | } | |
00b960c7 AH |
11526 | |
11527 | insn = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (nclobs)); | |
11528 | ||
11529 | for (i = 0; i < nclobs; ++i) | |
11530 | XVECEXP (insn, 0, i) = clobs[i]; | |
11531 | ||
11532 | return insn; | |
11533 | } | |
11534 | ||
89e7058f AH |
11535 | /* Save a register into the frame, and emit RTX_FRAME_RELATED_P notes. |
11536 | Save REGNO into [FRAME_REG + OFFSET] in mode MODE. */ | |
11537 | ||
11538 | static void | |
a2369ed3 | 11539 | emit_frame_save (rtx frame_reg, rtx frame_ptr, enum machine_mode mode, |
d1d0c603 | 11540 | unsigned int regno, int offset, HOST_WIDE_INT total_size) |
89e7058f AH |
11541 | { |
11542 | rtx reg, offset_rtx, insn, mem, addr, int_rtx; | |
11543 | rtx replacea, replaceb; | |
11544 | ||
11545 | int_rtx = GEN_INT (offset); | |
11546 | ||
11547 | /* Some cases that need register indexed addressing. */ | |
11548 | if ((TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode)) | |
a3170dc6 AH |
11549 | || (TARGET_SPE_ABI |
11550 | && SPE_VECTOR_MODE (mode) | |
11551 | && !SPE_CONST_OFFSET_OK (offset))) | |
89e7058f AH |
11552 | { |
11553 | /* Whomever calls us must make sure r11 is available in the | |
11554 | flow path of instructions in the prologue. */ | |
11555 | offset_rtx = gen_rtx_REG (Pmode, 11); | |
11556 | emit_move_insn (offset_rtx, int_rtx); | |
11557 | ||
11558 | replacea = offset_rtx; | |
11559 | replaceb = int_rtx; | |
11560 | } | |
11561 | else | |
11562 | { | |
11563 | offset_rtx = int_rtx; | |
11564 | replacea = NULL_RTX; | |
11565 | replaceb = NULL_RTX; | |
11566 | } | |
11567 | ||
11568 | reg = gen_rtx_REG (mode, regno); | |
11569 | addr = gen_rtx_PLUS (Pmode, frame_reg, offset_rtx); | |
11570 | mem = gen_rtx_MEM (mode, addr); | |
11571 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
11572 | ||
11573 | insn = emit_move_insn (mem, reg); | |
11574 | ||
11575 | rs6000_frame_related (insn, frame_ptr, total_size, replacea, replaceb); | |
11576 | } | |
11577 | ||
a3170dc6 AH |
11578 | /* Emit an offset memory reference suitable for a frame store, while |
11579 | converting to a valid addressing mode. */ | |
11580 | ||
11581 | static rtx | |
a2369ed3 | 11582 | gen_frame_mem_offset (enum machine_mode mode, rtx reg, int offset) |
a3170dc6 AH |
11583 | { |
11584 | rtx int_rtx, offset_rtx; | |
11585 | ||
11586 | int_rtx = GEN_INT (offset); | |
11587 | ||
11588 | if (TARGET_SPE_ABI && SPE_VECTOR_MODE (mode)) | |
11589 | { | |
11590 | offset_rtx = gen_rtx_REG (Pmode, FIXED_SCRATCH); | |
11591 | emit_move_insn (offset_rtx, int_rtx); | |
11592 | } | |
11593 | else | |
11594 | offset_rtx = int_rtx; | |
11595 | ||
11596 | return gen_rtx_MEM (mode, gen_rtx_PLUS (Pmode, reg, offset_rtx)); | |
11597 | } | |
11598 | ||
9ebbca7d GK |
11599 | /* Emit function prologue as insns. */ |
11600 | ||
9878760c | 11601 | void |
863d938c | 11602 | rs6000_emit_prologue (void) |
9878760c | 11603 | { |
4697a36c | 11604 | rs6000_stack_t *info = rs6000_stack_info (); |
0e67400a FJ |
11605 | enum machine_mode reg_mode = Pmode; |
11606 | int reg_size = UNITS_PER_WORD; | |
9ebbca7d GK |
11607 | rtx sp_reg_rtx = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM); |
11608 | rtx frame_ptr_rtx = gen_rtx_REG (Pmode, 12); | |
11609 | rtx frame_reg_rtx = sp_reg_rtx; | |
b78d48dd | 11610 | rtx cr_save_rtx = NULL_RTX; |
9ebbca7d GK |
11611 | rtx insn; |
11612 | int saving_FPRs_inline; | |
11613 | int using_store_multiple; | |
11614 | HOST_WIDE_INT sp_offset = 0; | |
11615 | ||
c19de7aa | 11616 | if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0) |
a3170dc6 AH |
11617 | { |
11618 | reg_mode = V2SImode; | |
11619 | reg_size = 8; | |
11620 | } | |
11621 | ||
9ebbca7d | 11622 | using_store_multiple = (TARGET_MULTIPLE && ! TARGET_POWERPC64 |
c19de7aa AH |
11623 | && (!TARGET_SPE_ABI |
11624 | || info->spe_64bit_regs_used == 0) | |
9ebbca7d GK |
11625 | && info->first_gp_reg_save < 31); |
11626 | saving_FPRs_inline = (info->first_fp_reg_save == 64 | |
8c29550d | 11627 | || FP_SAVE_INLINE (info->first_fp_reg_save) |
acd0b319 | 11628 | || current_function_calls_eh_return |
8c29550d | 11629 | || cfun->machine->ra_need_lr); |
9ebbca7d GK |
11630 | |
11631 | /* For V.4, update stack before we do any saving and set back pointer. */ | |
fc4767bb | 11632 | if (info->push_p |
acd0b319 AM |
11633 | && (DEFAULT_ABI == ABI_V4 |
11634 | || current_function_calls_eh_return)) | |
9ebbca7d GK |
11635 | { |
11636 | if (info->total_size < 32767) | |
11637 | sp_offset = info->total_size; | |
11638 | else | |
11639 | frame_reg_rtx = frame_ptr_rtx; | |
11640 | rs6000_emit_allocate_stack (info->total_size, | |
11641 | (frame_reg_rtx != sp_reg_rtx | |
11642 | && (info->cr_save_p | |
11643 | || info->lr_save_p | |
11644 | || info->first_fp_reg_save < 64 | |
11645 | || info->first_gp_reg_save < 32 | |
11646 | ))); | |
11647 | if (frame_reg_rtx != sp_reg_rtx) | |
11648 | rs6000_emit_stack_tie (); | |
11649 | } | |
11650 | ||
9aa86737 AH |
11651 | /* Save AltiVec registers if needed. */ |
11652 | if (TARGET_ALTIVEC_ABI && info->altivec_size != 0) | |
11653 | { | |
11654 | int i; | |
11655 | ||
11656 | /* There should be a non inline version of this, for when we | |
11657 | are saving lots of vector registers. */ | |
11658 | for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i) | |
11659 | if (info->vrsave_mask & ALTIVEC_REG_BIT (i)) | |
11660 | { | |
11661 | rtx areg, savereg, mem; | |
11662 | int offset; | |
11663 | ||
11664 | offset = info->altivec_save_offset + sp_offset | |
11665 | + 16 * (i - info->first_altivec_reg_save); | |
11666 | ||
11667 | savereg = gen_rtx_REG (V4SImode, i); | |
11668 | ||
11669 | areg = gen_rtx_REG (Pmode, 0); | |
11670 | emit_move_insn (areg, GEN_INT (offset)); | |
11671 | ||
11672 | /* AltiVec addressing mode is [reg+reg]. */ | |
11673 | mem = gen_rtx_MEM (V4SImode, | |
11674 | gen_rtx_PLUS (Pmode, frame_reg_rtx, areg)); | |
11675 | ||
11676 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
11677 | ||
11678 | insn = emit_move_insn (mem, savereg); | |
11679 | ||
5c242421 SB |
11680 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, |
11681 | areg, GEN_INT (offset)); | |
9aa86737 AH |
11682 | } |
11683 | } | |
11684 | ||
11685 | /* VRSAVE is a bit vector representing which AltiVec registers | |
11686 | are used. The OS uses this to determine which vector | |
11687 | registers to save on a context switch. We need to save | |
11688 | VRSAVE on the stack frame, add whatever AltiVec registers we | |
11689 | used in this function, and do the corresponding magic in the | |
11690 | epilogue. */ | |
11691 | ||
4d774ff8 HP |
11692 | if (TARGET_ALTIVEC && TARGET_ALTIVEC_VRSAVE |
11693 | && info->vrsave_mask != 0) | |
9aa86737 | 11694 | { |
a004eb82 | 11695 | rtx reg, mem, vrsave; |
9aa86737 AH |
11696 | int offset; |
11697 | ||
11698 | /* Get VRSAVE onto a GPR. */ | |
11699 | reg = gen_rtx_REG (SImode, 12); | |
a004eb82 | 11700 | vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO); |
b188f760 AH |
11701 | if (TARGET_MACHO) |
11702 | emit_insn (gen_get_vrsave_internal (reg)); | |
11703 | else | |
11704 | emit_insn (gen_rtx_SET (VOIDmode, reg, vrsave)); | |
9aa86737 AH |
11705 | |
11706 | /* Save VRSAVE. */ | |
11707 | offset = info->vrsave_save_offset + sp_offset; | |
11708 | mem | |
11709 | = gen_rtx_MEM (SImode, | |
11710 | gen_rtx_PLUS (Pmode, frame_reg_rtx, GEN_INT (offset))); | |
11711 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
11712 | insn = emit_move_insn (mem, reg); | |
11713 | ||
11714 | /* Include the registers in the mask. */ | |
11715 | emit_insn (gen_iorsi3 (reg, reg, GEN_INT ((int) info->vrsave_mask))); | |
11716 | ||
11717 | insn = emit_insn (generate_set_vrsave (reg, info, 0)); | |
11718 | } | |
11719 | ||
9ebbca7d GK |
11720 | /* If we use the link register, get it into r0. */ |
11721 | if (info->lr_save_p) | |
71f123ca | 11722 | emit_move_insn (gen_rtx_REG (Pmode, 0), |
9ebbca7d GK |
11723 | gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)); |
11724 | ||
11725 | /* If we need to save CR, put it into r12. */ | |
11726 | if (info->cr_save_p && frame_reg_rtx != frame_ptr_rtx) | |
11727 | { | |
11728 | cr_save_rtx = gen_rtx_REG (SImode, 12); | |
11729 | emit_insn (gen_movesi_from_cr (cr_save_rtx)); | |
11730 | } | |
11731 | ||
a4f6c312 SS |
11732 | /* Do any required saving of fpr's. If only one or two to save, do |
11733 | it ourselves. Otherwise, call function. */ | |
9ebbca7d GK |
11734 | if (saving_FPRs_inline) |
11735 | { | |
11736 | int i; | |
11737 | for (i = 0; i < 64 - info->first_fp_reg_save; i++) | |
11738 | if ((regs_ever_live[info->first_fp_reg_save+i] | |
11739 | && ! call_used_regs[info->first_fp_reg_save+i])) | |
89e7058f AH |
11740 | emit_frame_save (frame_reg_rtx, frame_ptr_rtx, DFmode, |
11741 | info->first_fp_reg_save + i, | |
11742 | info->fp_save_offset + sp_offset + 8 * i, | |
11743 | info->total_size); | |
9ebbca7d GK |
11744 | } |
11745 | else if (info->first_fp_reg_save != 64) | |
11746 | { | |
11747 | int i; | |
11748 | char rname[30]; | |
520a57c8 | 11749 | const char *alloc_rname; |
9ebbca7d GK |
11750 | rtvec p; |
11751 | p = rtvec_alloc (2 + 64 - info->first_fp_reg_save); | |
11752 | ||
11753 | RTVEC_ELT (p, 0) = gen_rtx_CLOBBER (VOIDmode, | |
11754 | gen_rtx_REG (Pmode, | |
11755 | LINK_REGISTER_REGNUM)); | |
11756 | sprintf (rname, "%s%d%s", SAVE_FP_PREFIX, | |
11757 | info->first_fp_reg_save - 32, SAVE_FP_SUFFIX); | |
a8a05998 | 11758 | alloc_rname = ggc_strdup (rname); |
9ebbca7d GK |
11759 | RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode, |
11760 | gen_rtx_SYMBOL_REF (Pmode, | |
11761 | alloc_rname)); | |
11762 | for (i = 0; i < 64 - info->first_fp_reg_save; i++) | |
11763 | { | |
11764 | rtx addr, reg, mem; | |
11765 | reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i); | |
11766 | addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
11767 | GEN_INT (info->fp_save_offset | |
11768 | + sp_offset + 8*i)); | |
11769 | mem = gen_rtx_MEM (DFmode, addr); | |
ba4828e0 | 11770 | set_mem_alias_set (mem, rs6000_sr_alias_set); |
9ebbca7d GK |
11771 | |
11772 | RTVEC_ELT (p, i + 2) = gen_rtx_SET (VOIDmode, mem, reg); | |
11773 | } | |
11774 | insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p)); | |
11775 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, | |
11776 | NULL_RTX, NULL_RTX); | |
11777 | } | |
b6c9286a | 11778 | |
9ebbca7d GK |
11779 | /* Save GPRs. This is done as a PARALLEL if we are using |
11780 | the store-multiple instructions. */ | |
11781 | if (using_store_multiple) | |
b6c9286a | 11782 | { |
308c142a | 11783 | rtvec p; |
9ebbca7d GK |
11784 | int i; |
11785 | p = rtvec_alloc (32 - info->first_gp_reg_save); | |
9ebbca7d GK |
11786 | for (i = 0; i < 32 - info->first_gp_reg_save; i++) |
11787 | { | |
11788 | rtx addr, reg, mem; | |
11789 | reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i); | |
11790 | addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
11791 | GEN_INT (info->gp_save_offset | |
11792 | + sp_offset | |
11793 | + reg_size * i)); | |
11794 | mem = gen_rtx_MEM (reg_mode, addr); | |
ba4828e0 | 11795 | set_mem_alias_set (mem, rs6000_sr_alias_set); |
9ebbca7d GK |
11796 | |
11797 | RTVEC_ELT (p, i) = gen_rtx_SET (VOIDmode, mem, reg); | |
11798 | } | |
11799 | insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p)); | |
11800 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, | |
11801 | NULL_RTX, NULL_RTX); | |
b6c9286a MM |
11802 | } |
11803 | else | |
11804 | { | |
9ebbca7d GK |
11805 | int i; |
11806 | for (i = 0; i < 32 - info->first_gp_reg_save; i++) | |
11807 | if ((regs_ever_live[info->first_gp_reg_save+i] | |
11808 | && ! call_used_regs[info->first_gp_reg_save+i]) | |
1db02437 | 11809 | || (i+info->first_gp_reg_save == RS6000_PIC_OFFSET_TABLE_REGNUM |
14f00213 | 11810 | && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0) |
f607bc57 | 11811 | || (DEFAULT_ABI == ABI_DARWIN && flag_pic)))) |
a3170dc6 AH |
11812 | { |
11813 | rtx addr, reg, mem; | |
11814 | reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i); | |
11815 | ||
c19de7aa | 11816 | if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0) |
a3170dc6 AH |
11817 | { |
11818 | int offset = info->spe_gp_save_offset + sp_offset + 8 * i; | |
11819 | rtx b; | |
11820 | ||
11821 | if (!SPE_CONST_OFFSET_OK (offset)) | |
11822 | { | |
11823 | b = gen_rtx_REG (Pmode, FIXED_SCRATCH); | |
11824 | emit_move_insn (b, GEN_INT (offset)); | |
11825 | } | |
11826 | else | |
11827 | b = GEN_INT (offset); | |
11828 | ||
11829 | addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, b); | |
11830 | mem = gen_rtx_MEM (V2SImode, addr); | |
11831 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
11832 | insn = emit_move_insn (mem, reg); | |
11833 | ||
11834 | if (GET_CODE (b) == CONST_INT) | |
11835 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, | |
11836 | NULL_RTX, NULL_RTX); | |
11837 | else | |
11838 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, | |
11839 | b, GEN_INT (offset)); | |
11840 | } | |
11841 | else | |
11842 | { | |
11843 | addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
11844 | GEN_INT (info->gp_save_offset | |
11845 | + sp_offset | |
11846 | + reg_size * i)); | |
11847 | mem = gen_rtx_MEM (reg_mode, addr); | |
11848 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
11849 | ||
11850 | insn = emit_move_insn (mem, reg); | |
11851 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, | |
11852 | NULL_RTX, NULL_RTX); | |
11853 | } | |
11854 | } | |
9ebbca7d GK |
11855 | } |
11856 | ||
83720594 RH |
11857 | /* ??? There's no need to emit actual instructions here, but it's the |
11858 | easiest way to get the frame unwind information emitted. */ | |
11859 | if (current_function_calls_eh_return) | |
11860 | { | |
78e1b90d DE |
11861 | unsigned int i, regno; |
11862 | ||
fc4767bb JJ |
11863 | /* In AIX ABI we need to pretend we save r2 here. */ |
11864 | if (TARGET_AIX) | |
11865 | { | |
11866 | rtx addr, reg, mem; | |
11867 | ||
11868 | reg = gen_rtx_REG (reg_mode, 2); | |
11869 | addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
11870 | GEN_INT (sp_offset + 5 * reg_size)); | |
11871 | mem = gen_rtx_MEM (reg_mode, addr); | |
11872 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
11873 | ||
11874 | insn = emit_move_insn (mem, reg); | |
11875 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, | |
11876 | NULL_RTX, NULL_RTX); | |
11877 | PATTERN (insn) = gen_blockage (); | |
11878 | } | |
11879 | ||
83720594 RH |
11880 | for (i = 0; ; ++i) |
11881 | { | |
83720594 RH |
11882 | regno = EH_RETURN_DATA_REGNO (i); |
11883 | if (regno == INVALID_REGNUM) | |
11884 | break; | |
11885 | ||
89e7058f AH |
11886 | emit_frame_save (frame_reg_rtx, frame_ptr_rtx, reg_mode, regno, |
11887 | info->ehrd_offset + sp_offset | |
11888 | + reg_size * (int) i, | |
11889 | info->total_size); | |
83720594 RH |
11890 | } |
11891 | } | |
11892 | ||
9ebbca7d GK |
11893 | /* Save lr if we used it. */ |
11894 | if (info->lr_save_p) | |
11895 | { | |
11896 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
11897 | GEN_INT (info->lr_save_offset + sp_offset)); | |
11898 | rtx reg = gen_rtx_REG (Pmode, 0); | |
11899 | rtx mem = gen_rtx_MEM (Pmode, addr); | |
11900 | /* This should not be of rs6000_sr_alias_set, because of | |
11901 | __builtin_return_address. */ | |
11902 | ||
11903 | insn = emit_move_insn (mem, reg); | |
11904 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, | |
11905 | reg, gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)); | |
11906 | } | |
11907 | ||
11908 | /* Save CR if we use any that must be preserved. */ | |
11909 | if (info->cr_save_p) | |
11910 | { | |
11911 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
11912 | GEN_INT (info->cr_save_offset + sp_offset)); | |
11913 | rtx mem = gen_rtx_MEM (SImode, addr); | |
ba4828e0 RK |
11914 | |
11915 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
9ebbca7d GK |
11916 | |
11917 | /* If r12 was used to hold the original sp, copy cr into r0 now | |
11918 | that it's free. */ | |
11919 | if (REGNO (frame_reg_rtx) == 12) | |
11920 | { | |
11921 | cr_save_rtx = gen_rtx_REG (SImode, 0); | |
11922 | emit_insn (gen_movesi_from_cr (cr_save_rtx)); | |
11923 | } | |
11924 | insn = emit_move_insn (mem, cr_save_rtx); | |
11925 | ||
11926 | /* Now, there's no way that dwarf2out_frame_debug_expr is going | |
615158e2 JJ |
11927 | to understand '(unspec:SI [(reg:CC 68) ...] UNSPEC_MOVESI_FROM_CR)'. |
11928 | But that's OK. All we have to do is specify that _one_ condition | |
11929 | code register is saved in this stack slot. The thrower's epilogue | |
a1dc9455 FS |
11930 | will then restore all the call-saved registers. |
11931 | We use CR2_REGNO (70) to be compatible with gcc-2.95 on Linux. */ | |
9ebbca7d | 11932 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, |
a1dc9455 | 11933 | cr_save_rtx, gen_rtx_REG (SImode, CR2_REGNO)); |
9ebbca7d GK |
11934 | } |
11935 | ||
11936 | /* Update stack and set back pointer unless this is V.4, | |
11937 | for which it was done previously. */ | |
fc4767bb JJ |
11938 | if (info->push_p |
11939 | && !(DEFAULT_ABI == ABI_V4 || current_function_calls_eh_return)) | |
9ebbca7d GK |
11940 | rs6000_emit_allocate_stack (info->total_size, FALSE); |
11941 | ||
11942 | /* Set frame pointer, if needed. */ | |
11943 | if (frame_pointer_needed) | |
11944 | { | |
a3170dc6 | 11945 | insn = emit_move_insn (gen_rtx_REG (Pmode, FRAME_POINTER_REGNUM), |
9ebbca7d GK |
11946 | sp_reg_rtx); |
11947 | RTX_FRAME_RELATED_P (insn) = 1; | |
b6c9286a | 11948 | } |
9878760c | 11949 | |
1db02437 | 11950 | /* If we are using RS6000_PIC_OFFSET_TABLE_REGNUM, we need to set it up. */ |
9ebbca7d | 11951 | if ((TARGET_TOC && TARGET_MINIMAL_TOC && get_pool_size () != 0) |
f607bc57 | 11952 | || (DEFAULT_ABI == ABI_V4 && flag_pic == 1 |
1db02437 | 11953 | && regs_ever_live[RS6000_PIC_OFFSET_TABLE_REGNUM])) |
9ebbca7d GK |
11954 | { |
11955 | /* If emit_load_toc_table will use the link register, we need to save | |
c4501e62 | 11956 | it. We use R12 for this purpose because emit_load_toc_table |
9ebbca7d GK |
11957 | can use register 0. This allows us to use a plain 'blr' to return |
11958 | from the procedure more often. */ | |
f1384257 AM |
11959 | int save_LR_around_toc_setup = (TARGET_ELF |
11960 | && DEFAULT_ABI != ABI_AIX | |
11961 | && flag_pic | |
d5fa86ba GK |
11962 | && ! info->lr_save_p |
11963 | && EXIT_BLOCK_PTR->pred != NULL); | |
9ebbca7d | 11964 | if (save_LR_around_toc_setup) |
c4501e62 JJ |
11965 | { |
11966 | rtx lr = gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM); | |
11967 | rs6000_maybe_dead (emit_move_insn (frame_ptr_rtx, lr)); | |
11968 | rs6000_emit_load_toc_table (TRUE); | |
11969 | rs6000_maybe_dead (emit_move_insn (lr, frame_ptr_rtx)); | |
11970 | } | |
11971 | else | |
11972 | rs6000_emit_load_toc_table (TRUE); | |
9ebbca7d | 11973 | } |
ee890fe2 | 11974 | |
fcce224d | 11975 | #if TARGET_MACHO |
ee890fe2 SS |
11976 | if (DEFAULT_ABI == ABI_DARWIN |
11977 | && flag_pic && current_function_uses_pic_offset_table) | |
11978 | { | |
11979 | rtx dest = gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM); | |
f099d360 | 11980 | const char *picbase = machopic_function_base_name (); |
6788f5ca | 11981 | rtx src = gen_rtx_SYMBOL_REF (Pmode, picbase); |
ee890fe2 | 11982 | |
f51eee6a | 11983 | rs6000_maybe_dead (emit_insn (gen_load_macho_picbase (dest, src))); |
ee890fe2 SS |
11984 | |
11985 | rs6000_maybe_dead ( | |
1db02437 | 11986 | emit_move_insn (gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM), |
ee890fe2 SS |
11987 | gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM))); |
11988 | } | |
fcce224d | 11989 | #endif |
9ebbca7d GK |
11990 | } |
11991 | ||
9ebbca7d | 11992 | /* Write function prologue. */ |
a4f6c312 | 11993 | |
08c148a8 | 11994 | static void |
a2369ed3 DJ |
11995 | rs6000_output_function_prologue (FILE *file, |
11996 | HOST_WIDE_INT size ATTRIBUTE_UNUSED) | |
9ebbca7d GK |
11997 | { |
11998 | rs6000_stack_t *info = rs6000_stack_info (); | |
11999 | ||
4697a36c MM |
12000 | if (TARGET_DEBUG_STACK) |
12001 | debug_stack_info (info); | |
9878760c | 12002 | |
a4f6c312 SS |
12003 | /* Write .extern for any function we will call to save and restore |
12004 | fp values. */ | |
12005 | if (info->first_fp_reg_save < 64 | |
12006 | && !FP_SAVE_INLINE (info->first_fp_reg_save)) | |
4d30c363 | 12007 | fprintf (file, "\t.extern %s%d%s\n\t.extern %s%d%s\n", |
4697a36c | 12008 | SAVE_FP_PREFIX, info->first_fp_reg_save - 32, SAVE_FP_SUFFIX, |
a4f6c312 SS |
12009 | RESTORE_FP_PREFIX, info->first_fp_reg_save - 32, |
12010 | RESTORE_FP_SUFFIX); | |
9878760c | 12011 | |
c764f757 RK |
12012 | /* Write .extern for AIX common mode routines, if needed. */ |
12013 | if (! TARGET_POWER && ! TARGET_POWERPC && ! common_mode_defined) | |
12014 | { | |
f6709c70 JW |
12015 | fputs ("\t.extern __mulh\n", file); |
12016 | fputs ("\t.extern __mull\n", file); | |
12017 | fputs ("\t.extern __divss\n", file); | |
12018 | fputs ("\t.extern __divus\n", file); | |
12019 | fputs ("\t.extern __quoss\n", file); | |
12020 | fputs ("\t.extern __quous\n", file); | |
c764f757 RK |
12021 | common_mode_defined = 1; |
12022 | } | |
9878760c | 12023 | |
9ebbca7d | 12024 | if (! HAVE_prologue) |
979721f8 | 12025 | { |
9ebbca7d | 12026 | start_sequence (); |
9dda4cc8 | 12027 | |
a4f6c312 SS |
12028 | /* A NOTE_INSN_DELETED is supposed to be at the start and end of |
12029 | the "toplevel" insn chain. */ | |
2e040219 | 12030 | emit_note (NOTE_INSN_DELETED); |
9ebbca7d | 12031 | rs6000_emit_prologue (); |
2e040219 | 12032 | emit_note (NOTE_INSN_DELETED); |
178c3eff | 12033 | |
a3c9585f | 12034 | /* Expand INSN_ADDRESSES so final() doesn't crash. */ |
178c3eff DJ |
12035 | { |
12036 | rtx insn; | |
12037 | unsigned addr = 0; | |
12038 | for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn)) | |
12039 | { | |
12040 | INSN_ADDRESSES_NEW (insn, addr); | |
12041 | addr += 4; | |
12042 | } | |
12043 | } | |
9dda4cc8 | 12044 | |
9ebbca7d | 12045 | if (TARGET_DEBUG_STACK) |
a4f6c312 SS |
12046 | debug_rtx_list (get_insns (), 100); |
12047 | final (get_insns (), file, FALSE, FALSE); | |
9ebbca7d | 12048 | end_sequence (); |
979721f8 MM |
12049 | } |
12050 | ||
9ebbca7d GK |
12051 | rs6000_pic_labelno++; |
12052 | } | |
12053 | ||
12054 | /* Emit function epilogue as insns. | |
9878760c | 12055 | |
9ebbca7d GK |
12056 | At present, dwarf2out_frame_debug_expr doesn't understand |
12057 | register restores, so we don't bother setting RTX_FRAME_RELATED_P | |
12058 | anywhere in the epilogue. Most of the insns below would in any case | |
12059 | need special notes to explain where r11 is in relation to the stack. */ | |
9878760c | 12060 | |
9ebbca7d | 12061 | void |
a2369ed3 | 12062 | rs6000_emit_epilogue (int sibcall) |
9ebbca7d GK |
12063 | { |
12064 | rs6000_stack_t *info; | |
12065 | int restoring_FPRs_inline; | |
12066 | int using_load_multiple; | |
12067 | int using_mfcr_multiple; | |
12068 | int use_backchain_to_restore_sp; | |
12069 | int sp_offset = 0; | |
12070 | rtx sp_reg_rtx = gen_rtx_REG (Pmode, 1); | |
12071 | rtx frame_reg_rtx = sp_reg_rtx; | |
0e67400a FJ |
12072 | enum machine_mode reg_mode = Pmode; |
12073 | int reg_size = UNITS_PER_WORD; | |
9ebbca7d GK |
12074 | int i; |
12075 | ||
c19de7aa AH |
12076 | info = rs6000_stack_info (); |
12077 | ||
12078 | if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0) | |
a3170dc6 AH |
12079 | { |
12080 | reg_mode = V2SImode; | |
12081 | reg_size = 8; | |
12082 | } | |
12083 | ||
9ebbca7d | 12084 | using_load_multiple = (TARGET_MULTIPLE && ! TARGET_POWERPC64 |
c19de7aa AH |
12085 | && (!TARGET_SPE_ABI |
12086 | || info->spe_64bit_regs_used == 0) | |
9ebbca7d GK |
12087 | && info->first_gp_reg_save < 31); |
12088 | restoring_FPRs_inline = (sibcall | |
83720594 | 12089 | || current_function_calls_eh_return |
9ebbca7d GK |
12090 | || info->first_fp_reg_save == 64 |
12091 | || FP_SAVE_INLINE (info->first_fp_reg_save)); | |
12092 | use_backchain_to_restore_sp = (frame_pointer_needed | |
12093 | || current_function_calls_alloca | |
12094 | || info->total_size > 32767); | |
12095 | using_mfcr_multiple = (rs6000_cpu == PROCESSOR_PPC601 | |
12096 | || rs6000_cpu == PROCESSOR_PPC603 | |
12097 | || rs6000_cpu == PROCESSOR_PPC750 | |
12098 | || optimize_size); | |
12099 | ||
12100 | /* If we have a frame pointer, a call to alloca, or a large stack | |
12101 | frame, restore the old stack pointer using the backchain. Otherwise, | |
12102 | we know what size to update it with. */ | |
12103 | if (use_backchain_to_restore_sp) | |
bacbde18 | 12104 | { |
9ebbca7d GK |
12105 | /* Under V.4, don't reset the stack pointer until after we're done |
12106 | loading the saved registers. */ | |
f607bc57 | 12107 | if (DEFAULT_ABI == ABI_V4) |
9ebbca7d | 12108 | frame_reg_rtx = gen_rtx_REG (Pmode, 11); |
4697a36c | 12109 | |
9ebbca7d GK |
12110 | emit_move_insn (frame_reg_rtx, |
12111 | gen_rtx_MEM (Pmode, sp_reg_rtx)); | |
12112 | ||
bacbde18 | 12113 | } |
9ebbca7d | 12114 | else if (info->push_p) |
85638c0d | 12115 | { |
fc4767bb JJ |
12116 | if (DEFAULT_ABI == ABI_V4 |
12117 | || current_function_calls_eh_return) | |
9ebbca7d GK |
12118 | sp_offset = info->total_size; |
12119 | else | |
12120 | { | |
12121 | emit_insn (TARGET_32BIT | |
12122 | ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx, | |
12123 | GEN_INT (info->total_size)) | |
12124 | : gen_adddi3 (sp_reg_rtx, sp_reg_rtx, | |
12125 | GEN_INT (info->total_size))); | |
12126 | } | |
85638c0d | 12127 | } |
9ebbca7d | 12128 | |
9aa86737 AH |
12129 | /* Restore AltiVec registers if needed. */ |
12130 | if (TARGET_ALTIVEC_ABI && info->altivec_size != 0) | |
12131 | { | |
12132 | int i; | |
12133 | ||
12134 | for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i) | |
12135 | if (info->vrsave_mask & ALTIVEC_REG_BIT (i)) | |
12136 | { | |
12137 | rtx addr, areg, mem; | |
12138 | ||
12139 | areg = gen_rtx_REG (Pmode, 0); | |
12140 | emit_move_insn | |
12141 | (areg, GEN_INT (info->altivec_save_offset | |
12142 | + sp_offset | |
12143 | + 16 * (i - info->first_altivec_reg_save))); | |
12144 | ||
12145 | /* AltiVec addressing mode is [reg+reg]. */ | |
12146 | addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, areg); | |
12147 | mem = gen_rtx_MEM (V4SImode, addr); | |
12148 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
12149 | ||
12150 | emit_move_insn (gen_rtx_REG (V4SImode, i), mem); | |
12151 | } | |
12152 | } | |
12153 | ||
12154 | /* Restore VRSAVE if needed. */ | |
4d774ff8 HP |
12155 | if (TARGET_ALTIVEC_ABI && TARGET_ALTIVEC_VRSAVE |
12156 | && info->vrsave_mask != 0) | |
9aa86737 AH |
12157 | { |
12158 | rtx addr, mem, reg; | |
12159 | ||
12160 | addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
12161 | GEN_INT (info->vrsave_save_offset + sp_offset)); | |
12162 | mem = gen_rtx_MEM (SImode, addr); | |
12163 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
12164 | reg = gen_rtx_REG (SImode, 12); | |
12165 | emit_move_insn (reg, mem); | |
12166 | ||
12167 | emit_insn (generate_set_vrsave (reg, info, 1)); | |
12168 | } | |
12169 | ||
9ebbca7d GK |
12170 | /* Get the old lr if we saved it. */ |
12171 | if (info->lr_save_p) | |
b6c9286a | 12172 | { |
a3170dc6 AH |
12173 | rtx mem = gen_frame_mem_offset (Pmode, frame_reg_rtx, |
12174 | info->lr_save_offset + sp_offset); | |
ba4828e0 RK |
12175 | |
12176 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
b6c9286a | 12177 | |
9ebbca7d | 12178 | emit_move_insn (gen_rtx_REG (Pmode, 0), mem); |
b6c9286a | 12179 | } |
9ebbca7d GK |
12180 | |
12181 | /* Get the old cr if we saved it. */ | |
12182 | if (info->cr_save_p) | |
12183 | { | |
12184 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
12185 | GEN_INT (info->cr_save_offset + sp_offset)); | |
12186 | rtx mem = gen_rtx_MEM (SImode, addr); | |
ba4828e0 RK |
12187 | |
12188 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
b6c9286a | 12189 | |
9ebbca7d GK |
12190 | emit_move_insn (gen_rtx_REG (SImode, 12), mem); |
12191 | } | |
12192 | ||
12193 | /* Set LR here to try to overlap restores below. */ | |
4697a36c | 12194 | if (info->lr_save_p) |
9ebbca7d GK |
12195 | emit_move_insn (gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM), |
12196 | gen_rtx_REG (Pmode, 0)); | |
12197 | ||
83720594 RH |
12198 | /* Load exception handler data registers, if needed. */ |
12199 | if (current_function_calls_eh_return) | |
12200 | { | |
78e1b90d DE |
12201 | unsigned int i, regno; |
12202 | ||
fc4767bb JJ |
12203 | if (TARGET_AIX) |
12204 | { | |
12205 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
12206 | GEN_INT (sp_offset + 5 * reg_size)); | |
12207 | rtx mem = gen_rtx_MEM (reg_mode, addr); | |
12208 | ||
12209 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
12210 | ||
12211 | emit_move_insn (gen_rtx_REG (reg_mode, 2), mem); | |
12212 | } | |
12213 | ||
83720594 RH |
12214 | for (i = 0; ; ++i) |
12215 | { | |
a3170dc6 | 12216 | rtx mem; |
83720594 RH |
12217 | |
12218 | regno = EH_RETURN_DATA_REGNO (i); | |
12219 | if (regno == INVALID_REGNUM) | |
12220 | break; | |
12221 | ||
a3170dc6 AH |
12222 | mem = gen_frame_mem_offset (reg_mode, frame_reg_rtx, |
12223 | info->ehrd_offset + sp_offset | |
12224 | + reg_size * (int) i); | |
ba4828e0 | 12225 | set_mem_alias_set (mem, rs6000_sr_alias_set); |
83720594 RH |
12226 | |
12227 | emit_move_insn (gen_rtx_REG (reg_mode, regno), mem); | |
12228 | } | |
12229 | } | |
9ebbca7d GK |
12230 | |
12231 | /* Restore GPRs. This is done as a PARALLEL if we are using | |
12232 | the load-multiple instructions. */ | |
12233 | if (using_load_multiple) | |
979721f8 | 12234 | { |
9ebbca7d GK |
12235 | rtvec p; |
12236 | p = rtvec_alloc (32 - info->first_gp_reg_save); | |
12237 | for (i = 0; i < 32 - info->first_gp_reg_save; i++) | |
979721f8 | 12238 | { |
9ebbca7d GK |
12239 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, |
12240 | GEN_INT (info->gp_save_offset | |
12241 | + sp_offset | |
12242 | + reg_size * i)); | |
12243 | rtx mem = gen_rtx_MEM (reg_mode, addr); | |
ba4828e0 RK |
12244 | |
12245 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
9ebbca7d GK |
12246 | |
12247 | RTVEC_ELT (p, i) = | |
12248 | gen_rtx_SET (VOIDmode, | |
12249 | gen_rtx_REG (reg_mode, info->first_gp_reg_save + i), | |
12250 | mem); | |
979721f8 | 12251 | } |
9ebbca7d | 12252 | emit_insn (gen_rtx_PARALLEL (VOIDmode, p)); |
979721f8 | 12253 | } |
9ebbca7d GK |
12254 | else |
12255 | for (i = 0; i < 32 - info->first_gp_reg_save; i++) | |
12256 | if ((regs_ever_live[info->first_gp_reg_save+i] | |
12257 | && ! call_used_regs[info->first_gp_reg_save+i]) | |
1db02437 | 12258 | || (i+info->first_gp_reg_save == RS6000_PIC_OFFSET_TABLE_REGNUM |
14f00213 | 12259 | && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0) |
f607bc57 | 12260 | || (DEFAULT_ABI == ABI_DARWIN && flag_pic)))) |
9ebbca7d GK |
12261 | { |
12262 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
12263 | GEN_INT (info->gp_save_offset | |
12264 | + sp_offset | |
12265 | + reg_size * i)); | |
12266 | rtx mem = gen_rtx_MEM (reg_mode, addr); | |
ba4828e0 | 12267 | |
a3170dc6 | 12268 | /* Restore 64-bit quantities for SPE. */ |
c19de7aa | 12269 | if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0) |
a3170dc6 AH |
12270 | { |
12271 | int offset = info->spe_gp_save_offset + sp_offset + 8 * i; | |
12272 | rtx b; | |
12273 | ||
12274 | if (!SPE_CONST_OFFSET_OK (offset)) | |
12275 | { | |
12276 | b = gen_rtx_REG (Pmode, FIXED_SCRATCH); | |
12277 | emit_move_insn (b, GEN_INT (offset)); | |
12278 | } | |
12279 | else | |
12280 | b = GEN_INT (offset); | |
12281 | ||
12282 | addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, b); | |
12283 | mem = gen_rtx_MEM (V2SImode, addr); | |
12284 | } | |
12285 | ||
ba4828e0 | 12286 | set_mem_alias_set (mem, rs6000_sr_alias_set); |
9ebbca7d GK |
12287 | |
12288 | emit_move_insn (gen_rtx_REG (reg_mode, | |
a3170dc6 | 12289 | info->first_gp_reg_save + i), mem); |
9ebbca7d | 12290 | } |
9878760c | 12291 | |
9ebbca7d GK |
12292 | /* Restore fpr's if we need to do it without calling a function. */ |
12293 | if (restoring_FPRs_inline) | |
12294 | for (i = 0; i < 64 - info->first_fp_reg_save; i++) | |
12295 | if ((regs_ever_live[info->first_fp_reg_save+i] | |
12296 | && ! call_used_regs[info->first_fp_reg_save+i])) | |
12297 | { | |
12298 | rtx addr, mem; | |
12299 | addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
12300 | GEN_INT (info->fp_save_offset | |
12301 | + sp_offset | |
a4f6c312 | 12302 | + 8 * i)); |
9ebbca7d | 12303 | mem = gen_rtx_MEM (DFmode, addr); |
ba4828e0 | 12304 | set_mem_alias_set (mem, rs6000_sr_alias_set); |
9ebbca7d GK |
12305 | |
12306 | emit_move_insn (gen_rtx_REG (DFmode, | |
12307 | info->first_fp_reg_save + i), | |
12308 | mem); | |
12309 | } | |
8d30c4ee | 12310 | |
9ebbca7d GK |
12311 | /* If we saved cr, restore it here. Just those that were used. */ |
12312 | if (info->cr_save_p) | |
979721f8 | 12313 | { |
9ebbca7d | 12314 | rtx r12_rtx = gen_rtx_REG (SImode, 12); |
e35b9579 | 12315 | int count = 0; |
9ebbca7d GK |
12316 | |
12317 | if (using_mfcr_multiple) | |
979721f8 | 12318 | { |
9ebbca7d GK |
12319 | for (i = 0; i < 8; i++) |
12320 | if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i]) | |
e35b9579 | 12321 | count++; |
9ebbca7d | 12322 | if (count == 0) |
e35b9579 GK |
12323 | abort (); |
12324 | } | |
12325 | ||
12326 | if (using_mfcr_multiple && count > 1) | |
12327 | { | |
12328 | rtvec p; | |
12329 | int ndx; | |
9ebbca7d | 12330 | |
e35b9579 | 12331 | p = rtvec_alloc (count); |
9ebbca7d | 12332 | |
e35b9579 | 12333 | ndx = 0; |
9ebbca7d GK |
12334 | for (i = 0; i < 8; i++) |
12335 | if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i]) | |
12336 | { | |
12337 | rtvec r = rtvec_alloc (2); | |
12338 | RTVEC_ELT (r, 0) = r12_rtx; | |
12339 | RTVEC_ELT (r, 1) = GEN_INT (1 << (7-i)); | |
e35b9579 | 12340 | RTVEC_ELT (p, ndx) = |
9ebbca7d | 12341 | gen_rtx_SET (VOIDmode, gen_rtx_REG (CCmode, CR0_REGNO+i), |
615158e2 | 12342 | gen_rtx_UNSPEC (CCmode, r, UNSPEC_MOVESI_TO_CR)); |
e35b9579 | 12343 | ndx++; |
9ebbca7d GK |
12344 | } |
12345 | emit_insn (gen_rtx_PARALLEL (VOIDmode, p)); | |
e35b9579 GK |
12346 | if (ndx != count) |
12347 | abort (); | |
979721f8 MM |
12348 | } |
12349 | else | |
9ebbca7d GK |
12350 | for (i = 0; i < 8; i++) |
12351 | if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i]) | |
979721f8 | 12352 | { |
9ebbca7d GK |
12353 | emit_insn (gen_movsi_to_cr_one (gen_rtx_REG (CCmode, |
12354 | CR0_REGNO+i), | |
12355 | r12_rtx)); | |
979721f8 | 12356 | } |
979721f8 MM |
12357 | } |
12358 | ||
9ebbca7d GK |
12359 | /* If this is V.4, unwind the stack pointer after all of the loads |
12360 | have been done. We need to emit a block here so that sched | |
12361 | doesn't decide to move the sp change before the register restores | |
12362 | (which may not have any obvious dependency on the stack). This | |
12363 | doesn't hurt performance, because there is no scheduling that can | |
12364 | be done after this point. */ | |
fc4767bb JJ |
12365 | if (DEFAULT_ABI == ABI_V4 |
12366 | || current_function_calls_eh_return) | |
b6c9286a | 12367 | { |
9ebbca7d GK |
12368 | if (frame_reg_rtx != sp_reg_rtx) |
12369 | rs6000_emit_stack_tie (); | |
b6c9286a | 12370 | |
9ebbca7d | 12371 | if (use_backchain_to_restore_sp) |
b6c9286a | 12372 | { |
9ebbca7d | 12373 | emit_move_insn (sp_reg_rtx, frame_reg_rtx); |
b6c9286a | 12374 | } |
9ebbca7d | 12375 | else if (sp_offset != 0) |
13f1623b | 12376 | { |
5b71a4e7 | 12377 | emit_insn (TARGET_32BIT |
9ebbca7d GK |
12378 | ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx, |
12379 | GEN_INT (sp_offset)) | |
12380 | : gen_adddi3 (sp_reg_rtx, sp_reg_rtx, | |
12381 | GEN_INT (sp_offset))); | |
13f1623b | 12382 | } |
9ebbca7d | 12383 | } |
b6c9286a | 12384 | |
83720594 RH |
12385 | if (current_function_calls_eh_return) |
12386 | { | |
12387 | rtx sa = EH_RETURN_STACKADJ_RTX; | |
5b71a4e7 | 12388 | emit_insn (TARGET_32BIT |
83720594 RH |
12389 | ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx, sa) |
12390 | : gen_adddi3 (sp_reg_rtx, sp_reg_rtx, sa)); | |
12391 | } | |
12392 | ||
9ebbca7d GK |
12393 | if (!sibcall) |
12394 | { | |
12395 | rtvec p; | |
12396 | if (! restoring_FPRs_inline) | |
12397 | p = rtvec_alloc (3 + 64 - info->first_fp_reg_save); | |
12398 | else | |
12399 | p = rtvec_alloc (2); | |
b6c9286a | 12400 | |
e35b9579 GK |
12401 | RTVEC_ELT (p, 0) = gen_rtx_RETURN (VOIDmode); |
12402 | RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode, | |
9ebbca7d GK |
12403 | gen_rtx_REG (Pmode, |
12404 | LINK_REGISTER_REGNUM)); | |
9ebbca7d GK |
12405 | |
12406 | /* If we have to restore more than two FP registers, branch to the | |
12407 | restore function. It will return to our caller. */ | |
12408 | if (! restoring_FPRs_inline) | |
12409 | { | |
12410 | int i; | |
12411 | char rname[30]; | |
520a57c8 | 12412 | const char *alloc_rname; |
979721f8 | 12413 | |
9ebbca7d GK |
12414 | sprintf (rname, "%s%d%s", RESTORE_FP_PREFIX, |
12415 | info->first_fp_reg_save - 32, RESTORE_FP_SUFFIX); | |
a8a05998 | 12416 | alloc_rname = ggc_strdup (rname); |
9ebbca7d GK |
12417 | RTVEC_ELT (p, 2) = gen_rtx_USE (VOIDmode, |
12418 | gen_rtx_SYMBOL_REF (Pmode, | |
12419 | alloc_rname)); | |
b6c9286a | 12420 | |
9ebbca7d GK |
12421 | for (i = 0; i < 64 - info->first_fp_reg_save; i++) |
12422 | { | |
12423 | rtx addr, mem; | |
12424 | addr = gen_rtx_PLUS (Pmode, sp_reg_rtx, | |
12425 | GEN_INT (info->fp_save_offset + 8*i)); | |
12426 | mem = gen_rtx_MEM (DFmode, addr); | |
ba4828e0 | 12427 | set_mem_alias_set (mem, rs6000_sr_alias_set); |
9ebbca7d GK |
12428 | |
12429 | RTVEC_ELT (p, i+3) = | |
12430 | gen_rtx_SET (VOIDmode, | |
12431 | gen_rtx_REG (DFmode, info->first_fp_reg_save + i), | |
12432 | mem); | |
b6c9286a MM |
12433 | } |
12434 | } | |
9ebbca7d GK |
12435 | |
12436 | emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p)); | |
3daf36a4 | 12437 | } |
9878760c RK |
12438 | } |
12439 | ||
12440 | /* Write function epilogue. */ | |
12441 | ||
08c148a8 | 12442 | static void |
a2369ed3 DJ |
12443 | rs6000_output_function_epilogue (FILE *file, |
12444 | HOST_WIDE_INT size ATTRIBUTE_UNUSED) | |
9878760c | 12445 | { |
4697a36c | 12446 | rs6000_stack_t *info = rs6000_stack_info (); |
9878760c | 12447 | |
9ebbca7d | 12448 | if (! HAVE_epilogue) |
9878760c | 12449 | { |
9ebbca7d GK |
12450 | rtx insn = get_last_insn (); |
12451 | /* If the last insn was a BARRIER, we don't have to write anything except | |
12452 | the trace table. */ | |
12453 | if (GET_CODE (insn) == NOTE) | |
12454 | insn = prev_nonnote_insn (insn); | |
12455 | if (insn == 0 || GET_CODE (insn) != BARRIER) | |
4697a36c | 12456 | { |
9ebbca7d GK |
12457 | /* This is slightly ugly, but at least we don't have two |
12458 | copies of the epilogue-emitting code. */ | |
12459 | start_sequence (); | |
12460 | ||
12461 | /* A NOTE_INSN_DELETED is supposed to be at the start | |
12462 | and end of the "toplevel" insn chain. */ | |
2e040219 | 12463 | emit_note (NOTE_INSN_DELETED); |
9ebbca7d | 12464 | rs6000_emit_epilogue (FALSE); |
2e040219 | 12465 | emit_note (NOTE_INSN_DELETED); |
9ebbca7d | 12466 | |
a3c9585f | 12467 | /* Expand INSN_ADDRESSES so final() doesn't crash. */ |
178c3eff DJ |
12468 | { |
12469 | rtx insn; | |
12470 | unsigned addr = 0; | |
12471 | for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn)) | |
12472 | { | |
12473 | INSN_ADDRESSES_NEW (insn, addr); | |
12474 | addr += 4; | |
12475 | } | |
12476 | } | |
12477 | ||
9ebbca7d | 12478 | if (TARGET_DEBUG_STACK) |
a4f6c312 SS |
12479 | debug_rtx_list (get_insns (), 100); |
12480 | final (get_insns (), file, FALSE, FALSE); | |
9ebbca7d | 12481 | end_sequence (); |
4697a36c | 12482 | } |
9878760c | 12483 | } |
b4ac57ab | 12484 | |
efdba735 SH |
12485 | #if TARGET_MACHO |
12486 | macho_branch_islands (); | |
0e5da0be GK |
12487 | /* Mach-O doesn't support labels at the end of objects, so if |
12488 | it looks like we might want one, insert a NOP. */ | |
12489 | { | |
12490 | rtx insn = get_last_insn (); | |
12491 | while (insn | |
12492 | && NOTE_P (insn) | |
12493 | && NOTE_LINE_NUMBER (insn) != NOTE_INSN_DELETED_LABEL) | |
12494 | insn = PREV_INSN (insn); | |
12495 | if (insn | |
12496 | && (LABEL_P (insn) | |
12497 | || (NOTE_P (insn) | |
12498 | && NOTE_LINE_NUMBER (insn) == NOTE_INSN_DELETED_LABEL))) | |
12499 | fputs ("\tnop\n", file); | |
12500 | } | |
12501 | #endif | |
12502 | ||
9b30bae2 | 12503 | /* Output a traceback table here. See /usr/include/sys/debug.h for info |
314fc5a9 ILT |
12504 | on its format. |
12505 | ||
12506 | We don't output a traceback table if -finhibit-size-directive was | |
12507 | used. The documentation for -finhibit-size-directive reads | |
12508 | ``don't output a @code{.size} assembler directive, or anything | |
12509 | else that would cause trouble if the function is split in the | |
12510 | middle, and the two halves are placed at locations far apart in | |
12511 | memory.'' The traceback table has this property, since it | |
12512 | includes the offset from the start of the function to the | |
4d30c363 MM |
12513 | traceback table itself. |
12514 | ||
12515 | System V.4 Powerpc's (and the embedded ABI derived from it) use a | |
b6c9286a | 12516 | different traceback table. */ |
57ac7be9 AM |
12517 | if (DEFAULT_ABI == ABI_AIX && ! flag_inhibit_size_directive |
12518 | && rs6000_traceback != traceback_none) | |
9b30bae2 | 12519 | { |
69c75916 | 12520 | const char *fname = NULL; |
3ac88239 | 12521 | const char *language_string = lang_hooks.name; |
6041bf2f | 12522 | int fixed_parms = 0, float_parms = 0, parm_info = 0; |
314fc5a9 | 12523 | int i; |
57ac7be9 AM |
12524 | int optional_tbtab; |
12525 | ||
12526 | if (rs6000_traceback == traceback_full) | |
12527 | optional_tbtab = 1; | |
12528 | else if (rs6000_traceback == traceback_part) | |
12529 | optional_tbtab = 0; | |
12530 | else | |
12531 | optional_tbtab = !optimize_size && !TARGET_ELF; | |
314fc5a9 | 12532 | |
69c75916 AM |
12533 | if (optional_tbtab) |
12534 | { | |
12535 | fname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0); | |
12536 | while (*fname == '.') /* V.4 encodes . in the name */ | |
12537 | fname++; | |
12538 | ||
12539 | /* Need label immediately before tbtab, so we can compute | |
12540 | its offset from the function start. */ | |
12541 | ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT"); | |
12542 | ASM_OUTPUT_LABEL (file, fname); | |
12543 | } | |
314fc5a9 ILT |
12544 | |
12545 | /* The .tbtab pseudo-op can only be used for the first eight | |
12546 | expressions, since it can't handle the possibly variable | |
12547 | length fields that follow. However, if you omit the optional | |
12548 | fields, the assembler outputs zeros for all optional fields | |
12549 | anyways, giving each variable length field is minimum length | |
12550 | (as defined in sys/debug.h). Thus we can not use the .tbtab | |
12551 | pseudo-op at all. */ | |
12552 | ||
12553 | /* An all-zero word flags the start of the tbtab, for debuggers | |
12554 | that have to find it by searching forward from the entry | |
12555 | point or from the current pc. */ | |
19d2d16f | 12556 | fputs ("\t.long 0\n", file); |
314fc5a9 ILT |
12557 | |
12558 | /* Tbtab format type. Use format type 0. */ | |
19d2d16f | 12559 | fputs ("\t.byte 0,", file); |
314fc5a9 | 12560 | |
5fc921c1 DE |
12561 | /* Language type. Unfortunately, there does not seem to be any |
12562 | official way to discover the language being compiled, so we | |
12563 | use language_string. | |
12564 | C is 0. Fortran is 1. Pascal is 2. Ada is 3. C++ is 9. | |
12565 | Java is 13. Objective-C is 14. */ | |
12566 | if (! strcmp (language_string, "GNU C")) | |
314fc5a9 ILT |
12567 | i = 0; |
12568 | else if (! strcmp (language_string, "GNU F77")) | |
12569 | i = 1; | |
8b83775b | 12570 | else if (! strcmp (language_string, "GNU Pascal")) |
314fc5a9 | 12571 | i = 2; |
5fc921c1 DE |
12572 | else if (! strcmp (language_string, "GNU Ada")) |
12573 | i = 3; | |
314fc5a9 ILT |
12574 | else if (! strcmp (language_string, "GNU C++")) |
12575 | i = 9; | |
9517ead8 AG |
12576 | else if (! strcmp (language_string, "GNU Java")) |
12577 | i = 13; | |
5fc921c1 DE |
12578 | else if (! strcmp (language_string, "GNU Objective-C")) |
12579 | i = 14; | |
314fc5a9 ILT |
12580 | else |
12581 | abort (); | |
12582 | fprintf (file, "%d,", i); | |
12583 | ||
12584 | /* 8 single bit fields: global linkage (not set for C extern linkage, | |
12585 | apparently a PL/I convention?), out-of-line epilogue/prologue, offset | |
12586 | from start of procedure stored in tbtab, internal function, function | |
12587 | has controlled storage, function has no toc, function uses fp, | |
12588 | function logs/aborts fp operations. */ | |
12589 | /* Assume that fp operations are used if any fp reg must be saved. */ | |
6041bf2f DE |
12590 | fprintf (file, "%d,", |
12591 | (optional_tbtab << 5) | ((info->first_fp_reg_save != 64) << 1)); | |
314fc5a9 ILT |
12592 | |
12593 | /* 6 bitfields: function is interrupt handler, name present in | |
12594 | proc table, function calls alloca, on condition directives | |
12595 | (controls stack walks, 3 bits), saves condition reg, saves | |
12596 | link reg. */ | |
12597 | /* The `function calls alloca' bit seems to be set whenever reg 31 is | |
12598 | set up as a frame pointer, even when there is no alloca call. */ | |
12599 | fprintf (file, "%d,", | |
6041bf2f DE |
12600 | ((optional_tbtab << 6) |
12601 | | ((optional_tbtab & frame_pointer_needed) << 5) | |
12602 | | (info->cr_save_p << 1) | |
12603 | | (info->lr_save_p))); | |
314fc5a9 | 12604 | |
6041bf2f | 12605 | /* 3 bitfields: saves backchain, fixup code, number of fpr saved |
314fc5a9 ILT |
12606 | (6 bits). */ |
12607 | fprintf (file, "%d,", | |
4697a36c | 12608 | (info->push_p << 7) | (64 - info->first_fp_reg_save)); |
314fc5a9 ILT |
12609 | |
12610 | /* 2 bitfields: spare bits (2 bits), number of gpr saved (6 bits). */ | |
12611 | fprintf (file, "%d,", (32 - first_reg_to_save ())); | |
12612 | ||
6041bf2f DE |
12613 | if (optional_tbtab) |
12614 | { | |
12615 | /* Compute the parameter info from the function decl argument | |
12616 | list. */ | |
12617 | tree decl; | |
12618 | int next_parm_info_bit = 31; | |
314fc5a9 | 12619 | |
6041bf2f DE |
12620 | for (decl = DECL_ARGUMENTS (current_function_decl); |
12621 | decl; decl = TREE_CHAIN (decl)) | |
12622 | { | |
12623 | rtx parameter = DECL_INCOMING_RTL (decl); | |
12624 | enum machine_mode mode = GET_MODE (parameter); | |
314fc5a9 | 12625 | |
6041bf2f DE |
12626 | if (GET_CODE (parameter) == REG) |
12627 | { | |
12628 | if (GET_MODE_CLASS (mode) == MODE_FLOAT) | |
12629 | { | |
12630 | int bits; | |
12631 | ||
12632 | float_parms++; | |
12633 | ||
12634 | if (mode == SFmode) | |
12635 | bits = 0x2; | |
fcce224d | 12636 | else if (mode == DFmode || mode == TFmode) |
6041bf2f DE |
12637 | bits = 0x3; |
12638 | else | |
12639 | abort (); | |
12640 | ||
12641 | /* If only one bit will fit, don't or in this entry. */ | |
12642 | if (next_parm_info_bit > 0) | |
12643 | parm_info |= (bits << (next_parm_info_bit - 1)); | |
12644 | next_parm_info_bit -= 2; | |
12645 | } | |
12646 | else | |
12647 | { | |
12648 | fixed_parms += ((GET_MODE_SIZE (mode) | |
12649 | + (UNITS_PER_WORD - 1)) | |
12650 | / UNITS_PER_WORD); | |
12651 | next_parm_info_bit -= 1; | |
12652 | } | |
12653 | } | |
12654 | } | |
12655 | } | |
314fc5a9 ILT |
12656 | |
12657 | /* Number of fixed point parameters. */ | |
12658 | /* This is actually the number of words of fixed point parameters; thus | |
12659 | an 8 byte struct counts as 2; and thus the maximum value is 8. */ | |
12660 | fprintf (file, "%d,", fixed_parms); | |
12661 | ||
12662 | /* 2 bitfields: number of floating point parameters (7 bits), parameters | |
12663 | all on stack. */ | |
12664 | /* This is actually the number of fp registers that hold parameters; | |
12665 | and thus the maximum value is 13. */ | |
12666 | /* Set parameters on stack bit if parameters are not in their original | |
12667 | registers, regardless of whether they are on the stack? Xlc | |
12668 | seems to set the bit when not optimizing. */ | |
12669 | fprintf (file, "%d\n", ((float_parms << 1) | (! optimize))); | |
12670 | ||
6041bf2f DE |
12671 | if (! optional_tbtab) |
12672 | return; | |
12673 | ||
314fc5a9 ILT |
12674 | /* Optional fields follow. Some are variable length. */ |
12675 | ||
12676 | /* Parameter types, left adjusted bit fields: 0 fixed, 10 single float, | |
12677 | 11 double float. */ | |
12678 | /* There is an entry for each parameter in a register, in the order that | |
12679 | they occur in the parameter list. Any intervening arguments on the | |
12680 | stack are ignored. If the list overflows a long (max possible length | |
12681 | 34 bits) then completely leave off all elements that don't fit. */ | |
12682 | /* Only emit this long if there was at least one parameter. */ | |
12683 | if (fixed_parms || float_parms) | |
12684 | fprintf (file, "\t.long %d\n", parm_info); | |
12685 | ||
12686 | /* Offset from start of code to tb table. */ | |
19d2d16f | 12687 | fputs ("\t.long ", file); |
314fc5a9 | 12688 | ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT"); |
54ee9799 DE |
12689 | #if TARGET_AIX |
12690 | RS6000_OUTPUT_BASENAME (file, fname); | |
12691 | #else | |
9ebbca7d | 12692 | assemble_name (file, fname); |
54ee9799 | 12693 | #endif |
19d2d16f | 12694 | fputs ("-.", file); |
54ee9799 DE |
12695 | #if TARGET_AIX |
12696 | RS6000_OUTPUT_BASENAME (file, fname); | |
12697 | #else | |
9ebbca7d | 12698 | assemble_name (file, fname); |
54ee9799 | 12699 | #endif |
19d2d16f | 12700 | putc ('\n', file); |
314fc5a9 ILT |
12701 | |
12702 | /* Interrupt handler mask. */ | |
12703 | /* Omit this long, since we never set the interrupt handler bit | |
12704 | above. */ | |
12705 | ||
12706 | /* Number of CTL (controlled storage) anchors. */ | |
12707 | /* Omit this long, since the has_ctl bit is never set above. */ | |
12708 | ||
12709 | /* Displacement into stack of each CTL anchor. */ | |
12710 | /* Omit this list of longs, because there are no CTL anchors. */ | |
12711 | ||
12712 | /* Length of function name. */ | |
69c75916 AM |
12713 | if (*fname == '*') |
12714 | ++fname; | |
296b8152 | 12715 | fprintf (file, "\t.short %d\n", (int) strlen (fname)); |
314fc5a9 ILT |
12716 | |
12717 | /* Function name. */ | |
12718 | assemble_string (fname, strlen (fname)); | |
12719 | ||
12720 | /* Register for alloca automatic storage; this is always reg 31. | |
12721 | Only emit this if the alloca bit was set above. */ | |
12722 | if (frame_pointer_needed) | |
19d2d16f | 12723 | fputs ("\t.byte 31\n", file); |
b1765bde DE |
12724 | |
12725 | fputs ("\t.align 2\n", file); | |
9b30bae2 | 12726 | } |
9878760c | 12727 | } |
17167fd8 | 12728 | \f |
a4f6c312 SS |
12729 | /* A C compound statement that outputs the assembler code for a thunk |
12730 | function, used to implement C++ virtual function calls with | |
12731 | multiple inheritance. The thunk acts as a wrapper around a virtual | |
12732 | function, adjusting the implicit object parameter before handing | |
12733 | control off to the real function. | |
12734 | ||
12735 | First, emit code to add the integer DELTA to the location that | |
12736 | contains the incoming first argument. Assume that this argument | |
12737 | contains a pointer, and is the one used to pass the `this' pointer | |
12738 | in C++. This is the incoming argument *before* the function | |
12739 | prologue, e.g. `%o0' on a sparc. The addition must preserve the | |
12740 | values of all other incoming arguments. | |
17167fd8 MM |
12741 | |
12742 | After the addition, emit code to jump to FUNCTION, which is a | |
a4f6c312 SS |
12743 | `FUNCTION_DECL'. This is a direct pure jump, not a call, and does |
12744 | not touch the return address. Hence returning from FUNCTION will | |
12745 | return to whoever called the current `thunk'. | |
17167fd8 | 12746 | |
a4f6c312 SS |
12747 | The effect must be as if FUNCTION had been called directly with the |
12748 | adjusted first argument. This macro is responsible for emitting | |
12749 | all of the code for a thunk function; output_function_prologue() | |
12750 | and output_function_epilogue() are not invoked. | |
17167fd8 | 12751 | |
a4f6c312 SS |
12752 | The THUNK_FNDECL is redundant. (DELTA and FUNCTION have already |
12753 | been extracted from it.) It might possibly be useful on some | |
12754 | targets, but probably not. | |
17167fd8 | 12755 | |
a4f6c312 SS |
12756 | If you do not define this macro, the target-independent code in the |
12757 | C++ frontend will generate a less efficient heavyweight thunk that | |
12758 | calls FUNCTION instead of jumping to it. The generic approach does | |
12759 | not support varargs. */ | |
17167fd8 | 12760 | |
3961e8fe | 12761 | static void |
a2369ed3 DJ |
12762 | rs6000_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED, |
12763 | HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset, | |
12764 | tree function) | |
17167fd8 | 12765 | { |
5b71a4e7 | 12766 | rtx this, insn, funexp; |
17167fd8 | 12767 | |
5b71a4e7 | 12768 | reload_completed = 1; |
fe3ad572 | 12769 | epilogue_completed = 1; |
5b71a4e7 | 12770 | no_new_pseudos = 1; |
56a7189a | 12771 | |
5b71a4e7 | 12772 | /* Mark the end of the (empty) prologue. */ |
2e040219 | 12773 | emit_note (NOTE_INSN_PROLOGUE_END); |
17167fd8 | 12774 | |
5b71a4e7 DE |
12775 | /* Find the "this" pointer. If the function returns a structure, |
12776 | the structure return pointer is in r3. */ | |
61f71b34 | 12777 | if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function)) |
5b71a4e7 | 12778 | this = gen_rtx_REG (Pmode, 4); |
56a7189a | 12779 | else |
5b71a4e7 | 12780 | this = gen_rtx_REG (Pmode, 3); |
17167fd8 | 12781 | |
5b71a4e7 DE |
12782 | /* Apply the constant offset, if required. */ |
12783 | if (delta) | |
12784 | { | |
12785 | rtx delta_rtx = GEN_INT (delta); | |
12786 | emit_insn (TARGET_32BIT | |
12787 | ? gen_addsi3 (this, this, delta_rtx) | |
12788 | : gen_adddi3 (this, this, delta_rtx)); | |
17167fd8 MM |
12789 | } |
12790 | ||
5b71a4e7 DE |
12791 | /* Apply the offset from the vtable, if required. */ |
12792 | if (vcall_offset) | |
17167fd8 | 12793 | { |
5b71a4e7 DE |
12794 | rtx vcall_offset_rtx = GEN_INT (vcall_offset); |
12795 | rtx tmp = gen_rtx_REG (Pmode, 12); | |
17167fd8 | 12796 | |
5b71a4e7 | 12797 | emit_move_insn (tmp, gen_rtx_MEM (Pmode, this)); |
eeff9307 JJ |
12798 | if (((unsigned HOST_WIDE_INT) vcall_offset) + 0x8000 >= 0x10000) |
12799 | { | |
12800 | emit_insn (TARGET_32BIT | |
12801 | ? gen_addsi3 (tmp, tmp, vcall_offset_rtx) | |
12802 | : gen_adddi3 (tmp, tmp, vcall_offset_rtx)); | |
12803 | emit_move_insn (tmp, gen_rtx_MEM (Pmode, tmp)); | |
12804 | } | |
12805 | else | |
12806 | { | |
12807 | rtx loc = gen_rtx_PLUS (Pmode, tmp, vcall_offset_rtx); | |
12808 | ||
12809 | emit_move_insn (tmp, gen_rtx_MEM (Pmode, loc)); | |
12810 | } | |
5b71a4e7 DE |
12811 | emit_insn (TARGET_32BIT |
12812 | ? gen_addsi3 (this, this, tmp) | |
12813 | : gen_adddi3 (this, this, tmp)); | |
17167fd8 MM |
12814 | } |
12815 | ||
5b71a4e7 DE |
12816 | /* Generate a tail call to the target function. */ |
12817 | if (!TREE_USED (function)) | |
12818 | { | |
12819 | assemble_external (function); | |
12820 | TREE_USED (function) = 1; | |
12821 | } | |
12822 | funexp = XEXP (DECL_RTL (function), 0); | |
5b71a4e7 | 12823 | funexp = gen_rtx_MEM (FUNCTION_MODE, funexp); |
ee890fe2 SS |
12824 | |
12825 | #if TARGET_MACHO | |
ab82a49f | 12826 | if (MACHOPIC_INDIRECT) |
5b71a4e7 | 12827 | funexp = machopic_indirect_call_target (funexp); |
ee890fe2 | 12828 | #endif |
5b71a4e7 DE |
12829 | |
12830 | /* gen_sibcall expects reload to convert scratch pseudo to LR so we must | |
12831 | generate sibcall RTL explicitly to avoid constraint abort. */ | |
12832 | insn = emit_call_insn ( | |
12833 | gen_rtx_PARALLEL (VOIDmode, | |
12834 | gen_rtvec (4, | |
12835 | gen_rtx_CALL (VOIDmode, | |
12836 | funexp, const0_rtx), | |
12837 | gen_rtx_USE (VOIDmode, const0_rtx), | |
12838 | gen_rtx_USE (VOIDmode, | |
12839 | gen_rtx_REG (SImode, | |
12840 | LINK_REGISTER_REGNUM)), | |
12841 | gen_rtx_RETURN (VOIDmode)))); | |
12842 | SIBLING_CALL_P (insn) = 1; | |
12843 | emit_barrier (); | |
12844 | ||
12845 | /* Run just enough of rest_of_compilation to get the insns emitted. | |
12846 | There's not really enough bulk here to make other passes such as | |
12847 | instruction scheduling worth while. Note that use_thunk calls | |
12848 | assemble_start_function and assemble_end_function. */ | |
12849 | insn = get_insns (); | |
a2855205 | 12850 | insn_locators_initialize (); |
5b71a4e7 DE |
12851 | shorten_branches (insn); |
12852 | final_start_function (insn, file, 1); | |
12853 | final (insn, file, 1, 0); | |
12854 | final_end_function (); | |
12855 | ||
12856 | reload_completed = 0; | |
fe3ad572 | 12857 | epilogue_completed = 0; |
5b71a4e7 | 12858 | no_new_pseudos = 0; |
9ebbca7d | 12859 | } |
9ebbca7d GK |
12860 | \f |
12861 | /* A quick summary of the various types of 'constant-pool tables' | |
12862 | under PowerPC: | |
12863 | ||
12864 | Target Flags Name One table per | |
12865 | AIX (none) AIX TOC object file | |
12866 | AIX -mfull-toc AIX TOC object file | |
12867 | AIX -mminimal-toc AIX minimal TOC translation unit | |
12868 | SVR4/EABI (none) SVR4 SDATA object file | |
12869 | SVR4/EABI -fpic SVR4 pic object file | |
12870 | SVR4/EABI -fPIC SVR4 PIC translation unit | |
12871 | SVR4/EABI -mrelocatable EABI TOC function | |
12872 | SVR4/EABI -maix AIX TOC object file | |
12873 | SVR4/EABI -maix -mminimal-toc | |
12874 | AIX minimal TOC translation unit | |
12875 | ||
12876 | Name Reg. Set by entries contains: | |
12877 | made by addrs? fp? sum? | |
12878 | ||
12879 | AIX TOC 2 crt0 as Y option option | |
12880 | AIX minimal TOC 30 prolog gcc Y Y option | |
12881 | SVR4 SDATA 13 crt0 gcc N Y N | |
12882 | SVR4 pic 30 prolog ld Y not yet N | |
12883 | SVR4 PIC 30 prolog gcc Y option option | |
12884 | EABI TOC 30 prolog gcc Y option option | |
12885 | ||
12886 | */ | |
12887 | ||
9ebbca7d GK |
12888 | /* Hash functions for the hash table. */ |
12889 | ||
12890 | static unsigned | |
a2369ed3 | 12891 | rs6000_hash_constant (rtx k) |
9ebbca7d | 12892 | { |
46b33600 RH |
12893 | enum rtx_code code = GET_CODE (k); |
12894 | enum machine_mode mode = GET_MODE (k); | |
12895 | unsigned result = (code << 3) ^ mode; | |
12896 | const char *format; | |
12897 | int flen, fidx; | |
9ebbca7d | 12898 | |
46b33600 RH |
12899 | format = GET_RTX_FORMAT (code); |
12900 | flen = strlen (format); | |
12901 | fidx = 0; | |
9ebbca7d | 12902 | |
46b33600 RH |
12903 | switch (code) |
12904 | { | |
12905 | case LABEL_REF: | |
12906 | return result * 1231 + (unsigned) INSN_UID (XEXP (k, 0)); | |
12907 | ||
12908 | case CONST_DOUBLE: | |
12909 | if (mode != VOIDmode) | |
12910 | return real_hash (CONST_DOUBLE_REAL_VALUE (k)) * result; | |
12911 | flen = 2; | |
12912 | break; | |
12913 | ||
12914 | case CODE_LABEL: | |
12915 | fidx = 3; | |
12916 | break; | |
12917 | ||
12918 | default: | |
12919 | break; | |
12920 | } | |
9ebbca7d GK |
12921 | |
12922 | for (; fidx < flen; fidx++) | |
12923 | switch (format[fidx]) | |
12924 | { | |
12925 | case 's': | |
12926 | { | |
12927 | unsigned i, len; | |
12928 | const char *str = XSTR (k, fidx); | |
12929 | len = strlen (str); | |
12930 | result = result * 613 + len; | |
12931 | for (i = 0; i < len; i++) | |
12932 | result = result * 613 + (unsigned) str[i]; | |
17167fd8 MM |
12933 | break; |
12934 | } | |
9ebbca7d GK |
12935 | case 'u': |
12936 | case 'e': | |
12937 | result = result * 1231 + rs6000_hash_constant (XEXP (k, fidx)); | |
12938 | break; | |
12939 | case 'i': | |
12940 | case 'n': | |
12941 | result = result * 613 + (unsigned) XINT (k, fidx); | |
12942 | break; | |
12943 | case 'w': | |
12944 | if (sizeof (unsigned) >= sizeof (HOST_WIDE_INT)) | |
12945 | result = result * 613 + (unsigned) XWINT (k, fidx); | |
12946 | else | |
12947 | { | |
12948 | size_t i; | |
12949 | for (i = 0; i < sizeof(HOST_WIDE_INT)/sizeof(unsigned); i++) | |
12950 | result = result * 613 + (unsigned) (XWINT (k, fidx) | |
12951 | >> CHAR_BIT * i); | |
12952 | } | |
12953 | break; | |
09501938 DE |
12954 | case '0': |
12955 | break; | |
9ebbca7d | 12956 | default: |
a4f6c312 | 12957 | abort (); |
9ebbca7d | 12958 | } |
46b33600 | 12959 | |
9ebbca7d GK |
12960 | return result; |
12961 | } | |
12962 | ||
12963 | static unsigned | |
a2369ed3 | 12964 | toc_hash_function (const void *hash_entry) |
9ebbca7d | 12965 | { |
a9098fd0 GK |
12966 | const struct toc_hash_struct *thc = |
12967 | (const struct toc_hash_struct *) hash_entry; | |
12968 | return rs6000_hash_constant (thc->key) ^ thc->key_mode; | |
9ebbca7d GK |
12969 | } |
12970 | ||
12971 | /* Compare H1 and H2 for equivalence. */ | |
12972 | ||
12973 | static int | |
a2369ed3 | 12974 | toc_hash_eq (const void *h1, const void *h2) |
9ebbca7d GK |
12975 | { |
12976 | rtx r1 = ((const struct toc_hash_struct *) h1)->key; | |
12977 | rtx r2 = ((const struct toc_hash_struct *) h2)->key; | |
12978 | ||
a9098fd0 GK |
12979 | if (((const struct toc_hash_struct *) h1)->key_mode |
12980 | != ((const struct toc_hash_struct *) h2)->key_mode) | |
12981 | return 0; | |
12982 | ||
5692c7bc | 12983 | return rtx_equal_p (r1, r2); |
9ebbca7d GK |
12984 | } |
12985 | ||
28e510bd MM |
12986 | /* These are the names given by the C++ front-end to vtables, and |
12987 | vtable-like objects. Ideally, this logic should not be here; | |
12988 | instead, there should be some programmatic way of inquiring as | |
12989 | to whether or not an object is a vtable. */ | |
12990 | ||
12991 | #define VTABLE_NAME_P(NAME) \ | |
12992 | (strncmp ("_vt.", name, strlen("_vt.")) == 0 \ | |
12993 | || strncmp ("_ZTV", name, strlen ("_ZTV")) == 0 \ | |
12994 | || strncmp ("_ZTT", name, strlen ("_ZTT")) == 0 \ | |
12995 | || strncmp ("_ZTC", name, strlen ("_ZTC")) == 0) | |
12996 | ||
12997 | void | |
a2369ed3 | 12998 | rs6000_output_symbol_ref (FILE *file, rtx x) |
28e510bd MM |
12999 | { |
13000 | /* Currently C++ toc references to vtables can be emitted before it | |
13001 | is decided whether the vtable is public or private. If this is | |
13002 | the case, then the linker will eventually complain that there is | |
13003 | a reference to an unknown section. Thus, for vtables only, | |
13004 | we emit the TOC reference to reference the symbol and not the | |
13005 | section. */ | |
13006 | const char *name = XSTR (x, 0); | |
54ee9799 DE |
13007 | |
13008 | if (VTABLE_NAME_P (name)) | |
13009 | { | |
13010 | RS6000_OUTPUT_BASENAME (file, name); | |
13011 | } | |
13012 | else | |
13013 | assemble_name (file, name); | |
28e510bd MM |
13014 | } |
13015 | ||
a4f6c312 SS |
13016 | /* Output a TOC entry. We derive the entry name from what is being |
13017 | written. */ | |
9878760c RK |
13018 | |
13019 | void | |
a2369ed3 | 13020 | output_toc (FILE *file, rtx x, int labelno, enum machine_mode mode) |
9878760c RK |
13021 | { |
13022 | char buf[256]; | |
3cce094d | 13023 | const char *name = buf; |
ec940faa | 13024 | const char *real_name; |
9878760c RK |
13025 | rtx base = x; |
13026 | int offset = 0; | |
13027 | ||
4697a36c MM |
13028 | if (TARGET_NO_TOC) |
13029 | abort (); | |
13030 | ||
9ebbca7d GK |
13031 | /* When the linker won't eliminate them, don't output duplicate |
13032 | TOC entries (this happens on AIX if there is any kind of TOC, | |
17211ab5 GK |
13033 | and on SVR4 under -fPIC or -mrelocatable). Don't do this for |
13034 | CODE_LABELs. */ | |
13035 | if (TARGET_TOC && GET_CODE (x) != LABEL_REF) | |
9ebbca7d GK |
13036 | { |
13037 | struct toc_hash_struct *h; | |
13038 | void * * found; | |
13039 | ||
17211ab5 | 13040 | /* Create toc_hash_table. This can't be done at OVERRIDE_OPTIONS |
39e3f58c | 13041 | time because GGC is not initialized at that point. */ |
17211ab5 GK |
13042 | if (toc_hash_table == NULL) |
13043 | toc_hash_table = htab_create_ggc (1021, toc_hash_function, | |
13044 | toc_hash_eq, NULL); | |
13045 | ||
9ebbca7d GK |
13046 | h = ggc_alloc (sizeof (*h)); |
13047 | h->key = x; | |
a9098fd0 | 13048 | h->key_mode = mode; |
9ebbca7d GK |
13049 | h->labelno = labelno; |
13050 | ||
13051 | found = htab_find_slot (toc_hash_table, h, 1); | |
13052 | if (*found == NULL) | |
13053 | *found = h; | |
13054 | else /* This is indeed a duplicate. | |
13055 | Set this label equal to that label. */ | |
13056 | { | |
13057 | fputs ("\t.set ", file); | |
13058 | ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC"); | |
13059 | fprintf (file, "%d,", labelno); | |
13060 | ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC"); | |
13061 | fprintf (file, "%d\n", ((*(const struct toc_hash_struct **) | |
13062 | found)->labelno)); | |
13063 | return; | |
13064 | } | |
13065 | } | |
13066 | ||
13067 | /* If we're going to put a double constant in the TOC, make sure it's | |
13068 | aligned properly when strict alignment is on. */ | |
ff1720ed RK |
13069 | if (GET_CODE (x) == CONST_DOUBLE |
13070 | && STRICT_ALIGNMENT | |
a9098fd0 | 13071 | && GET_MODE_BITSIZE (mode) >= 64 |
ff1720ed RK |
13072 | && ! (TARGET_NO_FP_IN_TOC && ! TARGET_MINIMAL_TOC)) { |
13073 | ASM_OUTPUT_ALIGN (file, 3); | |
13074 | } | |
13075 | ||
4977bab6 | 13076 | (*targetm.asm_out.internal_label) (file, "LC", labelno); |
9878760c | 13077 | |
37c37a57 RK |
13078 | /* Handle FP constants specially. Note that if we have a minimal |
13079 | TOC, things we put here aren't actually in the TOC, so we can allow | |
13080 | FP constants. */ | |
fcce224d DE |
13081 | if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == TFmode) |
13082 | { | |
13083 | REAL_VALUE_TYPE rv; | |
13084 | long k[4]; | |
13085 | ||
13086 | REAL_VALUE_FROM_CONST_DOUBLE (rv, x); | |
13087 | REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv, k); | |
13088 | ||
13089 | if (TARGET_64BIT) | |
13090 | { | |
13091 | if (TARGET_MINIMAL_TOC) | |
13092 | fputs (DOUBLE_INT_ASM_OP, file); | |
13093 | else | |
13094 | fprintf (file, "\t.tc FT_%lx_%lx_%lx_%lx[TC],", | |
13095 | k[0] & 0xffffffff, k[1] & 0xffffffff, | |
13096 | k[2] & 0xffffffff, k[3] & 0xffffffff); | |
13097 | fprintf (file, "0x%lx%08lx,0x%lx%08lx\n", | |
13098 | k[0] & 0xffffffff, k[1] & 0xffffffff, | |
13099 | k[2] & 0xffffffff, k[3] & 0xffffffff); | |
13100 | return; | |
13101 | } | |
13102 | else | |
13103 | { | |
13104 | if (TARGET_MINIMAL_TOC) | |
13105 | fputs ("\t.long ", file); | |
13106 | else | |
13107 | fprintf (file, "\t.tc FT_%lx_%lx_%lx_%lx[TC],", | |
13108 | k[0] & 0xffffffff, k[1] & 0xffffffff, | |
13109 | k[2] & 0xffffffff, k[3] & 0xffffffff); | |
13110 | fprintf (file, "0x%lx,0x%lx,0x%lx,0x%lx\n", | |
13111 | k[0] & 0xffffffff, k[1] & 0xffffffff, | |
13112 | k[2] & 0xffffffff, k[3] & 0xffffffff); | |
13113 | return; | |
13114 | } | |
13115 | } | |
13116 | else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == DFmode) | |
9878760c | 13117 | { |
042259f2 DE |
13118 | REAL_VALUE_TYPE rv; |
13119 | long k[2]; | |
0adc764e | 13120 | |
042259f2 DE |
13121 | REAL_VALUE_FROM_CONST_DOUBLE (rv, x); |
13122 | REAL_VALUE_TO_TARGET_DOUBLE (rv, k); | |
31bfaa0b | 13123 | |
13ded975 DE |
13124 | if (TARGET_64BIT) |
13125 | { | |
13126 | if (TARGET_MINIMAL_TOC) | |
2bfcf297 | 13127 | fputs (DOUBLE_INT_ASM_OP, file); |
13ded975 | 13128 | else |
2f0552b6 AM |
13129 | fprintf (file, "\t.tc FD_%lx_%lx[TC],", |
13130 | k[0] & 0xffffffff, k[1] & 0xffffffff); | |
13131 | fprintf (file, "0x%lx%08lx\n", | |
13132 | k[0] & 0xffffffff, k[1] & 0xffffffff); | |
13ded975 DE |
13133 | return; |
13134 | } | |
1875cc88 | 13135 | else |
13ded975 DE |
13136 | { |
13137 | if (TARGET_MINIMAL_TOC) | |
2bfcf297 | 13138 | fputs ("\t.long ", file); |
13ded975 | 13139 | else |
2f0552b6 AM |
13140 | fprintf (file, "\t.tc FD_%lx_%lx[TC],", |
13141 | k[0] & 0xffffffff, k[1] & 0xffffffff); | |
13142 | fprintf (file, "0x%lx,0x%lx\n", | |
13143 | k[0] & 0xffffffff, k[1] & 0xffffffff); | |
13ded975 DE |
13144 | return; |
13145 | } | |
9878760c | 13146 | } |
a9098fd0 | 13147 | else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == SFmode) |
9878760c | 13148 | { |
042259f2 DE |
13149 | REAL_VALUE_TYPE rv; |
13150 | long l; | |
9878760c | 13151 | |
042259f2 DE |
13152 | REAL_VALUE_FROM_CONST_DOUBLE (rv, x); |
13153 | REAL_VALUE_TO_TARGET_SINGLE (rv, l); | |
13154 | ||
31bfaa0b DE |
13155 | if (TARGET_64BIT) |
13156 | { | |
13157 | if (TARGET_MINIMAL_TOC) | |
2bfcf297 | 13158 | fputs (DOUBLE_INT_ASM_OP, file); |
31bfaa0b | 13159 | else |
2f0552b6 AM |
13160 | fprintf (file, "\t.tc FS_%lx[TC],", l & 0xffffffff); |
13161 | fprintf (file, "0x%lx00000000\n", l & 0xffffffff); | |
31bfaa0b DE |
13162 | return; |
13163 | } | |
042259f2 | 13164 | else |
31bfaa0b DE |
13165 | { |
13166 | if (TARGET_MINIMAL_TOC) | |
2bfcf297 | 13167 | fputs ("\t.long ", file); |
31bfaa0b | 13168 | else |
2f0552b6 AM |
13169 | fprintf (file, "\t.tc FS_%lx[TC],", l & 0xffffffff); |
13170 | fprintf (file, "0x%lx\n", l & 0xffffffff); | |
31bfaa0b DE |
13171 | return; |
13172 | } | |
042259f2 | 13173 | } |
f176e826 | 13174 | else if (GET_MODE (x) == VOIDmode |
a9098fd0 | 13175 | && (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE)) |
042259f2 | 13176 | { |
e2c953b6 | 13177 | unsigned HOST_WIDE_INT low; |
042259f2 DE |
13178 | HOST_WIDE_INT high; |
13179 | ||
13180 | if (GET_CODE (x) == CONST_DOUBLE) | |
13181 | { | |
13182 | low = CONST_DOUBLE_LOW (x); | |
13183 | high = CONST_DOUBLE_HIGH (x); | |
13184 | } | |
13185 | else | |
13186 | #if HOST_BITS_PER_WIDE_INT == 32 | |
13187 | { | |
13188 | low = INTVAL (x); | |
0858c623 | 13189 | high = (low & 0x80000000) ? ~0 : 0; |
042259f2 DE |
13190 | } |
13191 | #else | |
13192 | { | |
0858c623 | 13193 | low = INTVAL (x) & 0xffffffff; |
042259f2 DE |
13194 | high = (HOST_WIDE_INT) INTVAL (x) >> 32; |
13195 | } | |
13196 | #endif | |
9878760c | 13197 | |
a9098fd0 GK |
13198 | /* TOC entries are always Pmode-sized, but since this |
13199 | is a bigendian machine then if we're putting smaller | |
13200 | integer constants in the TOC we have to pad them. | |
13201 | (This is still a win over putting the constants in | |
13202 | a separate constant pool, because then we'd have | |
02a4ec28 FS |
13203 | to have both a TOC entry _and_ the actual constant.) |
13204 | ||
13205 | For a 32-bit target, CONST_INT values are loaded and shifted | |
13206 | entirely within `low' and can be stored in one TOC entry. */ | |
13207 | ||
13208 | if (TARGET_64BIT && POINTER_SIZE < GET_MODE_BITSIZE (mode)) | |
a9098fd0 | 13209 | abort ();/* It would be easy to make this work, but it doesn't now. */ |
02a4ec28 FS |
13210 | |
13211 | if (POINTER_SIZE > GET_MODE_BITSIZE (mode)) | |
fb52d8de AM |
13212 | { |
13213 | #if HOST_BITS_PER_WIDE_INT == 32 | |
13214 | lshift_double (low, high, POINTER_SIZE - GET_MODE_BITSIZE (mode), | |
13215 | POINTER_SIZE, &low, &high, 0); | |
13216 | #else | |
13217 | low |= high << 32; | |
13218 | low <<= POINTER_SIZE - GET_MODE_BITSIZE (mode); | |
13219 | high = (HOST_WIDE_INT) low >> 32; | |
13220 | low &= 0xffffffff; | |
13221 | #endif | |
13222 | } | |
a9098fd0 | 13223 | |
13ded975 DE |
13224 | if (TARGET_64BIT) |
13225 | { | |
13226 | if (TARGET_MINIMAL_TOC) | |
2bfcf297 | 13227 | fputs (DOUBLE_INT_ASM_OP, file); |
13ded975 | 13228 | else |
2f0552b6 AM |
13229 | fprintf (file, "\t.tc ID_%lx_%lx[TC],", |
13230 | (long) high & 0xffffffff, (long) low & 0xffffffff); | |
13231 | fprintf (file, "0x%lx%08lx\n", | |
13232 | (long) high & 0xffffffff, (long) low & 0xffffffff); | |
13ded975 DE |
13233 | return; |
13234 | } | |
1875cc88 | 13235 | else |
13ded975 | 13236 | { |
02a4ec28 FS |
13237 | if (POINTER_SIZE < GET_MODE_BITSIZE (mode)) |
13238 | { | |
13239 | if (TARGET_MINIMAL_TOC) | |
2bfcf297 | 13240 | fputs ("\t.long ", file); |
02a4ec28 | 13241 | else |
2bfcf297 | 13242 | fprintf (file, "\t.tc ID_%lx_%lx[TC],", |
2f0552b6 AM |
13243 | (long) high & 0xffffffff, (long) low & 0xffffffff); |
13244 | fprintf (file, "0x%lx,0x%lx\n", | |
13245 | (long) high & 0xffffffff, (long) low & 0xffffffff); | |
02a4ec28 | 13246 | } |
13ded975 | 13247 | else |
02a4ec28 FS |
13248 | { |
13249 | if (TARGET_MINIMAL_TOC) | |
2bfcf297 | 13250 | fputs ("\t.long ", file); |
02a4ec28 | 13251 | else |
2f0552b6 AM |
13252 | fprintf (file, "\t.tc IS_%lx[TC],", (long) low & 0xffffffff); |
13253 | fprintf (file, "0x%lx\n", (long) low & 0xffffffff); | |
02a4ec28 | 13254 | } |
13ded975 DE |
13255 | return; |
13256 | } | |
9878760c RK |
13257 | } |
13258 | ||
13259 | if (GET_CODE (x) == CONST) | |
13260 | { | |
2bfcf297 DB |
13261 | if (GET_CODE (XEXP (x, 0)) != PLUS) |
13262 | abort (); | |
13263 | ||
9878760c RK |
13264 | base = XEXP (XEXP (x, 0), 0); |
13265 | offset = INTVAL (XEXP (XEXP (x, 0), 1)); | |
13266 | } | |
13267 | ||
13268 | if (GET_CODE (base) == SYMBOL_REF) | |
13269 | name = XSTR (base, 0); | |
13270 | else if (GET_CODE (base) == LABEL_REF) | |
13271 | ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (XEXP (base, 0))); | |
13272 | else if (GET_CODE (base) == CODE_LABEL) | |
13273 | ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (base)); | |
13274 | else | |
13275 | abort (); | |
13276 | ||
772c5265 | 13277 | real_name = (*targetm.strip_name_encoding) (name); |
1875cc88 | 13278 | if (TARGET_MINIMAL_TOC) |
2bfcf297 | 13279 | fputs (TARGET_32BIT ? "\t.long " : DOUBLE_INT_ASM_OP, file); |
1875cc88 JW |
13280 | else |
13281 | { | |
b6c9286a | 13282 | fprintf (file, "\t.tc %s", real_name); |
9878760c | 13283 | |
1875cc88 JW |
13284 | if (offset < 0) |
13285 | fprintf (file, ".N%d", - offset); | |
13286 | else if (offset) | |
13287 | fprintf (file, ".P%d", offset); | |
9878760c | 13288 | |
19d2d16f | 13289 | fputs ("[TC],", file); |
1875cc88 | 13290 | } |
581bc4de MM |
13291 | |
13292 | /* Currently C++ toc references to vtables can be emitted before it | |
13293 | is decided whether the vtable is public or private. If this is | |
13294 | the case, then the linker will eventually complain that there is | |
13295 | a TOC reference to an unknown section. Thus, for vtables only, | |
13296 | we emit the TOC reference to reference the symbol and not the | |
13297 | section. */ | |
28e510bd | 13298 | if (VTABLE_NAME_P (name)) |
581bc4de | 13299 | { |
54ee9799 | 13300 | RS6000_OUTPUT_BASENAME (file, name); |
581bc4de MM |
13301 | if (offset < 0) |
13302 | fprintf (file, "%d", offset); | |
13303 | else if (offset > 0) | |
13304 | fprintf (file, "+%d", offset); | |
13305 | } | |
13306 | else | |
13307 | output_addr_const (file, x); | |
19d2d16f | 13308 | putc ('\n', file); |
9878760c RK |
13309 | } |
13310 | \f | |
13311 | /* Output an assembler pseudo-op to write an ASCII string of N characters | |
13312 | starting at P to FILE. | |
13313 | ||
13314 | On the RS/6000, we have to do this using the .byte operation and | |
13315 | write out special characters outside the quoted string. | |
13316 | Also, the assembler is broken; very long strings are truncated, | |
a4f6c312 | 13317 | so we must artificially break them up early. */ |
9878760c RK |
13318 | |
13319 | void | |
a2369ed3 | 13320 | output_ascii (FILE *file, const char *p, int n) |
9878760c RK |
13321 | { |
13322 | char c; | |
13323 | int i, count_string; | |
d330fd93 KG |
13324 | const char *for_string = "\t.byte \""; |
13325 | const char *for_decimal = "\t.byte "; | |
13326 | const char *to_close = NULL; | |
9878760c RK |
13327 | |
13328 | count_string = 0; | |
13329 | for (i = 0; i < n; i++) | |
13330 | { | |
13331 | c = *p++; | |
13332 | if (c >= ' ' && c < 0177) | |
13333 | { | |
13334 | if (for_string) | |
13335 | fputs (for_string, file); | |
13336 | putc (c, file); | |
13337 | ||
13338 | /* Write two quotes to get one. */ | |
13339 | if (c == '"') | |
13340 | { | |
13341 | putc (c, file); | |
13342 | ++count_string; | |
13343 | } | |
13344 | ||
13345 | for_string = NULL; | |
13346 | for_decimal = "\"\n\t.byte "; | |
13347 | to_close = "\"\n"; | |
13348 | ++count_string; | |
13349 | ||
13350 | if (count_string >= 512) | |
13351 | { | |
13352 | fputs (to_close, file); | |
13353 | ||
13354 | for_string = "\t.byte \""; | |
13355 | for_decimal = "\t.byte "; | |
13356 | to_close = NULL; | |
13357 | count_string = 0; | |
13358 | } | |
13359 | } | |
13360 | else | |
13361 | { | |
13362 | if (for_decimal) | |
13363 | fputs (for_decimal, file); | |
13364 | fprintf (file, "%d", c); | |
13365 | ||
13366 | for_string = "\n\t.byte \""; | |
13367 | for_decimal = ", "; | |
13368 | to_close = "\n"; | |
13369 | count_string = 0; | |
13370 | } | |
13371 | } | |
13372 | ||
13373 | /* Now close the string if we have written one. Then end the line. */ | |
13374 | if (to_close) | |
9ebbca7d | 13375 | fputs (to_close, file); |
9878760c RK |
13376 | } |
13377 | \f | |
13378 | /* Generate a unique section name for FILENAME for a section type | |
13379 | represented by SECTION_DESC. Output goes into BUF. | |
13380 | ||
13381 | SECTION_DESC can be any string, as long as it is different for each | |
13382 | possible section type. | |
13383 | ||
13384 | We name the section in the same manner as xlc. The name begins with an | |
13385 | underscore followed by the filename (after stripping any leading directory | |
11e5fe42 RK |
13386 | names) with the last period replaced by the string SECTION_DESC. If |
13387 | FILENAME does not contain a period, SECTION_DESC is appended to the end of | |
13388 | the name. */ | |
9878760c RK |
13389 | |
13390 | void | |
a2369ed3 DJ |
13391 | rs6000_gen_section_name (char **buf, const char *filename, |
13392 | const char *section_desc) | |
9878760c | 13393 | { |
9ebbca7d | 13394 | const char *q, *after_last_slash, *last_period = 0; |
9878760c RK |
13395 | char *p; |
13396 | int len; | |
9878760c RK |
13397 | |
13398 | after_last_slash = filename; | |
13399 | for (q = filename; *q; q++) | |
11e5fe42 RK |
13400 | { |
13401 | if (*q == '/') | |
13402 | after_last_slash = q + 1; | |
13403 | else if (*q == '.') | |
13404 | last_period = q; | |
13405 | } | |
9878760c | 13406 | |
11e5fe42 | 13407 | len = strlen (after_last_slash) + strlen (section_desc) + 2; |
6d9f628e | 13408 | *buf = (char *) xmalloc (len); |
9878760c RK |
13409 | |
13410 | p = *buf; | |
13411 | *p++ = '_'; | |
13412 | ||
13413 | for (q = after_last_slash; *q; q++) | |
13414 | { | |
11e5fe42 | 13415 | if (q == last_period) |
9878760c RK |
13416 | { |
13417 | strcpy (p, section_desc); | |
13418 | p += strlen (section_desc); | |
e3981aab | 13419 | break; |
9878760c RK |
13420 | } |
13421 | ||
e9a780ec | 13422 | else if (ISALNUM (*q)) |
9878760c RK |
13423 | *p++ = *q; |
13424 | } | |
13425 | ||
11e5fe42 | 13426 | if (last_period == 0) |
9878760c RK |
13427 | strcpy (p, section_desc); |
13428 | else | |
13429 | *p = '\0'; | |
13430 | } | |
e165f3f0 | 13431 | \f |
a4f6c312 | 13432 | /* Emit profile function. */ |
411707f4 | 13433 | |
411707f4 | 13434 | void |
a2369ed3 | 13435 | output_profile_hook (int labelno ATTRIBUTE_UNUSED) |
411707f4 | 13436 | { |
ffcfcb5f AM |
13437 | if (TARGET_PROFILE_KERNEL) |
13438 | return; | |
13439 | ||
8480e480 CC |
13440 | if (DEFAULT_ABI == ABI_AIX) |
13441 | { | |
9739c90c JJ |
13442 | #ifndef NO_PROFILE_COUNTERS |
13443 | # define NO_PROFILE_COUNTERS 0 | |
13444 | #endif | |
13445 | if (NO_PROFILE_COUNTERS) | |
13446 | emit_library_call (init_one_libfunc (RS6000_MCOUNT), 0, VOIDmode, 0); | |
13447 | else | |
13448 | { | |
13449 | char buf[30]; | |
13450 | const char *label_name; | |
13451 | rtx fun; | |
411707f4 | 13452 | |
9739c90c JJ |
13453 | ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno); |
13454 | label_name = (*targetm.strip_name_encoding) (ggc_strdup (buf)); | |
13455 | fun = gen_rtx_SYMBOL_REF (Pmode, label_name); | |
411707f4 | 13456 | |
9739c90c JJ |
13457 | emit_library_call (init_one_libfunc (RS6000_MCOUNT), 0, VOIDmode, 1, |
13458 | fun, Pmode); | |
13459 | } | |
8480e480 | 13460 | } |
ee890fe2 SS |
13461 | else if (DEFAULT_ABI == ABI_DARWIN) |
13462 | { | |
d5fa86ba | 13463 | const char *mcount_name = RS6000_MCOUNT; |
ee890fe2 SS |
13464 | int caller_addr_regno = LINK_REGISTER_REGNUM; |
13465 | ||
13466 | /* Be conservative and always set this, at least for now. */ | |
13467 | current_function_uses_pic_offset_table = 1; | |
13468 | ||
13469 | #if TARGET_MACHO | |
13470 | /* For PIC code, set up a stub and collect the caller's address | |
13471 | from r0, which is where the prologue puts it. */ | |
ab82a49f | 13472 | if (MACHOPIC_INDIRECT) |
ee890fe2 SS |
13473 | { |
13474 | mcount_name = machopic_stub_name (mcount_name); | |
13475 | if (current_function_uses_pic_offset_table) | |
13476 | caller_addr_regno = 0; | |
13477 | } | |
13478 | #endif | |
13479 | emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mcount_name), | |
13480 | 0, VOIDmode, 1, | |
13481 | gen_rtx_REG (Pmode, caller_addr_regno), Pmode); | |
13482 | } | |
411707f4 CC |
13483 | } |
13484 | ||
a4f6c312 | 13485 | /* Write function profiler code. */ |
e165f3f0 RK |
13486 | |
13487 | void | |
a2369ed3 | 13488 | output_function_profiler (FILE *file, int labelno) |
e165f3f0 | 13489 | { |
3daf36a4 | 13490 | char buf[100]; |
09eeeacb | 13491 | int save_lr = 8; |
e165f3f0 | 13492 | |
38c1f2d7 | 13493 | switch (DEFAULT_ABI) |
3daf36a4 | 13494 | { |
38c1f2d7 MM |
13495 | default: |
13496 | abort (); | |
13497 | ||
13498 | case ABI_V4: | |
09eeeacb | 13499 | save_lr = 4; |
09eeeacb AM |
13500 | if (!TARGET_32BIT) |
13501 | { | |
13502 | warning ("no profiling of 64-bit code for this ABI"); | |
13503 | return; | |
13504 | } | |
ffcfcb5f | 13505 | ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno); |
38c1f2d7 MM |
13506 | fprintf (file, "\tmflr %s\n", reg_names[0]); |
13507 | if (flag_pic == 1) | |
13508 | { | |
dfdfa60f | 13509 | fputs ("\tbl _GLOBAL_OFFSET_TABLE_@local-4\n", file); |
09eeeacb AM |
13510 | asm_fprintf (file, "\t{st|stw} %s,%d(%s)\n", |
13511 | reg_names[0], save_lr, reg_names[1]); | |
17167fd8 | 13512 | asm_fprintf (file, "\tmflr %s\n", reg_names[12]); |
dfdfa60f | 13513 | asm_fprintf (file, "\t{l|lwz} %s,", reg_names[0]); |
38c1f2d7 | 13514 | assemble_name (file, buf); |
17167fd8 | 13515 | asm_fprintf (file, "@got(%s)\n", reg_names[12]); |
38c1f2d7 | 13516 | } |
9ebbca7d | 13517 | else if (flag_pic > 1) |
38c1f2d7 | 13518 | { |
09eeeacb AM |
13519 | asm_fprintf (file, "\t{st|stw} %s,%d(%s)\n", |
13520 | reg_names[0], save_lr, reg_names[1]); | |
9ebbca7d GK |
13521 | /* Now, we need to get the address of the label. */ |
13522 | fputs ("\tbl 1f\n\t.long ", file); | |
034e84c4 | 13523 | assemble_name (file, buf); |
9ebbca7d GK |
13524 | fputs ("-.\n1:", file); |
13525 | asm_fprintf (file, "\tmflr %s\n", reg_names[11]); | |
13526 | asm_fprintf (file, "\t{l|lwz} %s,0(%s)\n", | |
13527 | reg_names[0], reg_names[11]); | |
13528 | asm_fprintf (file, "\t{cax|add} %s,%s,%s\n", | |
13529 | reg_names[0], reg_names[0], reg_names[11]); | |
38c1f2d7 | 13530 | } |
38c1f2d7 MM |
13531 | else |
13532 | { | |
17167fd8 | 13533 | asm_fprintf (file, "\t{liu|lis} %s,", reg_names[12]); |
38c1f2d7 | 13534 | assemble_name (file, buf); |
dfdfa60f | 13535 | fputs ("@ha\n", file); |
09eeeacb AM |
13536 | asm_fprintf (file, "\t{st|stw} %s,%d(%s)\n", |
13537 | reg_names[0], save_lr, reg_names[1]); | |
a260abc9 | 13538 | asm_fprintf (file, "\t{cal|la} %s,", reg_names[0]); |
38c1f2d7 | 13539 | assemble_name (file, buf); |
17167fd8 | 13540 | asm_fprintf (file, "@l(%s)\n", reg_names[12]); |
38c1f2d7 MM |
13541 | } |
13542 | ||
50d440bc NC |
13543 | /* ABI_V4 saves the static chain reg with ASM_OUTPUT_REG_PUSH. */ |
13544 | fprintf (file, "\tbl %s\n", RS6000_MCOUNT); | |
38c1f2d7 MM |
13545 | break; |
13546 | ||
13547 | case ABI_AIX: | |
ee890fe2 | 13548 | case ABI_DARWIN: |
ffcfcb5f AM |
13549 | if (!TARGET_PROFILE_KERNEL) |
13550 | { | |
a3c9585f | 13551 | /* Don't do anything, done in output_profile_hook (). */ |
ffcfcb5f AM |
13552 | } |
13553 | else | |
13554 | { | |
13555 | if (TARGET_32BIT) | |
13556 | abort (); | |
13557 | ||
13558 | asm_fprintf (file, "\tmflr %s\n", reg_names[0]); | |
13559 | asm_fprintf (file, "\tstd %s,16(%s)\n", reg_names[0], reg_names[1]); | |
13560 | ||
13561 | if (current_function_needs_context) | |
13562 | { | |
13563 | asm_fprintf (file, "\tstd %s,24(%s)\n", | |
13564 | reg_names[STATIC_CHAIN_REGNUM], reg_names[1]); | |
13565 | fprintf (file, "\tbl %s\n", RS6000_MCOUNT); | |
13566 | asm_fprintf (file, "\tld %s,24(%s)\n", | |
13567 | reg_names[STATIC_CHAIN_REGNUM], reg_names[1]); | |
13568 | } | |
13569 | else | |
13570 | fprintf (file, "\tbl %s\n", RS6000_MCOUNT); | |
13571 | } | |
38c1f2d7 MM |
13572 | break; |
13573 | } | |
e165f3f0 | 13574 | } |
a251ffd0 | 13575 | |
b54cf83a DE |
13576 | \f |
13577 | static int | |
863d938c | 13578 | rs6000_use_dfa_pipeline_interface (void) |
b54cf83a DE |
13579 | { |
13580 | return 1; | |
13581 | } | |
13582 | ||
b54cf83a DE |
13583 | /* Power4 load update and store update instructions are cracked into a |
13584 | load or store and an integer insn which are executed in the same cycle. | |
13585 | Branches have their own dispatch slot which does not count against the | |
13586 | GCC issue rate, but it changes the program flow so there are no other | |
13587 | instructions to issue in this cycle. */ | |
13588 | ||
13589 | static int | |
a2369ed3 DJ |
13590 | rs6000_variable_issue (FILE *stream ATTRIBUTE_UNUSED, |
13591 | int verbose ATTRIBUTE_UNUSED, | |
13592 | rtx insn, int more) | |
b54cf83a DE |
13593 | { |
13594 | if (GET_CODE (PATTERN (insn)) == USE | |
13595 | || GET_CODE (PATTERN (insn)) == CLOBBER) | |
13596 | return more; | |
13597 | ||
13598 | if (rs6000_cpu == PROCESSOR_POWER4) | |
13599 | { | |
cbe26ab8 DN |
13600 | if (is_microcoded_insn (insn)) |
13601 | return 0; | |
13602 | else if (is_cracked_insn (insn)) | |
13603 | return more > 2 ? more - 2 : 0; | |
b54cf83a | 13604 | } |
165b263e DE |
13605 | |
13606 | return more - 1; | |
b54cf83a DE |
13607 | } |
13608 | ||
a251ffd0 TG |
13609 | /* Adjust the cost of a scheduling dependency. Return the new cost of |
13610 | a dependency LINK or INSN on DEP_INSN. COST is the current cost. */ | |
13611 | ||
c237e94a | 13612 | static int |
a2369ed3 DJ |
13613 | rs6000_adjust_cost (rtx insn, rtx link, rtx dep_insn ATTRIBUTE_UNUSED, |
13614 | int cost) | |
a251ffd0 TG |
13615 | { |
13616 | if (! recog_memoized (insn)) | |
13617 | return 0; | |
13618 | ||
13619 | if (REG_NOTE_KIND (link) != 0) | |
13620 | return 0; | |
13621 | ||
13622 | if (REG_NOTE_KIND (link) == 0) | |
13623 | { | |
ed947a96 DJ |
13624 | /* Data dependency; DEP_INSN writes a register that INSN reads |
13625 | some cycles later. */ | |
13626 | switch (get_attr_type (insn)) | |
13627 | { | |
13628 | case TYPE_JMPREG: | |
309323c2 | 13629 | /* Tell the first scheduling pass about the latency between |
ed947a96 DJ |
13630 | a mtctr and bctr (and mtlr and br/blr). The first |
13631 | scheduling pass will not know about this latency since | |
13632 | the mtctr instruction, which has the latency associated | |
13633 | to it, will be generated by reload. */ | |
309323c2 | 13634 | return TARGET_POWER ? 5 : 4; |
ed947a96 DJ |
13635 | case TYPE_BRANCH: |
13636 | /* Leave some extra cycles between a compare and its | |
13637 | dependent branch, to inhibit expensive mispredicts. */ | |
309323c2 DE |
13638 | if ((rs6000_cpu_attr == CPU_PPC603 |
13639 | || rs6000_cpu_attr == CPU_PPC604 | |
13640 | || rs6000_cpu_attr == CPU_PPC604E | |
13641 | || rs6000_cpu_attr == CPU_PPC620 | |
13642 | || rs6000_cpu_attr == CPU_PPC630 | |
13643 | || rs6000_cpu_attr == CPU_PPC750 | |
13644 | || rs6000_cpu_attr == CPU_PPC7400 | |
13645 | || rs6000_cpu_attr == CPU_PPC7450 | |
13646 | || rs6000_cpu_attr == CPU_POWER4) | |
ed947a96 DJ |
13647 | && recog_memoized (dep_insn) |
13648 | && (INSN_CODE (dep_insn) >= 0) | |
b54cf83a DE |
13649 | && (get_attr_type (dep_insn) == TYPE_CMP |
13650 | || get_attr_type (dep_insn) == TYPE_COMPARE | |
ed947a96 | 13651 | || get_attr_type (dep_insn) == TYPE_DELAYED_COMPARE |
9259f3b0 DE |
13652 | || get_attr_type (dep_insn) == TYPE_IMUL_COMPARE |
13653 | || get_attr_type (dep_insn) == TYPE_LMUL_COMPARE | |
ed947a96 | 13654 | || get_attr_type (dep_insn) == TYPE_FPCOMPARE |
b54cf83a DE |
13655 | || get_attr_type (dep_insn) == TYPE_CR_LOGICAL |
13656 | || get_attr_type (dep_insn) == TYPE_DELAYED_CR)) | |
ed947a96 DJ |
13657 | return cost + 2; |
13658 | default: | |
13659 | break; | |
13660 | } | |
a251ffd0 TG |
13661 | /* Fall out to return default cost. */ |
13662 | } | |
13663 | ||
13664 | return cost; | |
13665 | } | |
b6c9286a | 13666 | |
cbe26ab8 | 13667 | /* The function returns a true if INSN is microcoded. |
839a4992 | 13668 | Return false otherwise. */ |
cbe26ab8 DN |
13669 | |
13670 | static bool | |
13671 | is_microcoded_insn (rtx insn) | |
13672 | { | |
13673 | if (!insn || !INSN_P (insn) | |
13674 | || GET_CODE (PATTERN (insn)) == USE | |
13675 | || GET_CODE (PATTERN (insn)) == CLOBBER) | |
13676 | return false; | |
13677 | ||
13678 | if (rs6000_cpu == PROCESSOR_POWER4) | |
13679 | { | |
13680 | enum attr_type type = get_attr_type (insn); | |
13681 | if (type == TYPE_LOAD_EXT_U | |
13682 | || type == TYPE_LOAD_EXT_UX | |
13683 | || type == TYPE_LOAD_UX | |
13684 | || type == TYPE_STORE_UX | |
13685 | || type == TYPE_MFCR) | |
13686 | return true; | |
13687 | } | |
13688 | ||
13689 | return false; | |
13690 | } | |
13691 | ||
5c425df5 | 13692 | /* The function returns a nonzero value if INSN can be scheduled only |
cbe26ab8 DN |
13693 | as the first insn in a dispatch group ("dispatch-slot restricted"). |
13694 | In this case, the returned value indicates how many dispatch slots | |
13695 | the insn occupies (at the beginning of the group). | |
79ae11c4 DN |
13696 | Return 0 otherwise. */ |
13697 | ||
cbe26ab8 | 13698 | static int |
79ae11c4 DN |
13699 | is_dispatch_slot_restricted (rtx insn) |
13700 | { | |
13701 | enum attr_type type; | |
13702 | ||
13703 | if (rs6000_cpu != PROCESSOR_POWER4) | |
13704 | return 0; | |
13705 | ||
13706 | if (!insn | |
13707 | || insn == NULL_RTX | |
13708 | || GET_CODE (insn) == NOTE | |
13709 | || GET_CODE (PATTERN (insn)) == USE | |
13710 | || GET_CODE (PATTERN (insn)) == CLOBBER) | |
13711 | return 0; | |
13712 | ||
13713 | type = get_attr_type (insn); | |
13714 | ||
13715 | switch (type){ | |
13716 | case TYPE_MFCR: | |
13717 | case TYPE_MFCRF: | |
13718 | case TYPE_MTCR: | |
13719 | case TYPE_DELAYED_CR: | |
13720 | case TYPE_CR_LOGICAL: | |
13721 | case TYPE_MTJMPR: | |
13722 | case TYPE_MFJMPR: | |
13723 | return 1; | |
13724 | case TYPE_IDIV: | |
13725 | case TYPE_LDIV: | |
13726 | return 2; | |
13727 | default: | |
13728 | return 0; | |
13729 | } | |
13730 | } | |
13731 | ||
cbe26ab8 DN |
13732 | /* The function returns true if INSN is cracked into 2 instructions |
13733 | by the processor (and therefore occupies 2 issue slots). */ | |
13734 | ||
13735 | static bool | |
13736 | is_cracked_insn (rtx insn) | |
13737 | { | |
13738 | if (!insn || !INSN_P (insn) | |
13739 | || GET_CODE (PATTERN (insn)) == USE | |
13740 | || GET_CODE (PATTERN (insn)) == CLOBBER) | |
13741 | return false; | |
13742 | ||
13743 | if (rs6000_cpu == PROCESSOR_POWER4) | |
13744 | { | |
13745 | enum attr_type type = get_attr_type (insn); | |
13746 | if (type == TYPE_LOAD_U || type == TYPE_STORE_U | |
13747 | || type == TYPE_FPLOAD_U || type == TYPE_FPSTORE_U | |
13748 | || type == TYPE_FPLOAD_UX || type == TYPE_FPSTORE_UX | |
13749 | || type == TYPE_LOAD_EXT || type == TYPE_DELAYED_CR | |
13750 | || type == TYPE_COMPARE || type == TYPE_DELAYED_COMPARE | |
13751 | || type == TYPE_IMUL_COMPARE || type == TYPE_LMUL_COMPARE | |
13752 | || type == TYPE_IDIV || type == TYPE_LDIV | |
13753 | || type == TYPE_INSERT_WORD) | |
13754 | return true; | |
13755 | } | |
13756 | ||
13757 | return false; | |
13758 | } | |
13759 | ||
13760 | /* The function returns true if INSN can be issued only from | |
a3c9585f | 13761 | the branch slot. */ |
cbe26ab8 DN |
13762 | |
13763 | static bool | |
13764 | is_branch_slot_insn (rtx insn) | |
13765 | { | |
13766 | if (!insn || !INSN_P (insn) | |
13767 | || GET_CODE (PATTERN (insn)) == USE | |
13768 | || GET_CODE (PATTERN (insn)) == CLOBBER) | |
13769 | return false; | |
13770 | ||
13771 | if (rs6000_cpu == PROCESSOR_POWER4) | |
13772 | { | |
13773 | enum attr_type type = get_attr_type (insn); | |
13774 | if (type == TYPE_BRANCH || type == TYPE_JMPREG) | |
13775 | return true; | |
13776 | return false; | |
13777 | } | |
13778 | ||
13779 | return false; | |
13780 | } | |
79ae11c4 | 13781 | |
a4f6c312 | 13782 | /* A C statement (sans semicolon) to update the integer scheduling |
79ae11c4 DN |
13783 | priority INSN_PRIORITY (INSN). Increase the priority to execute the |
13784 | INSN earlier, reduce the priority to execute INSN later. Do not | |
a4f6c312 SS |
13785 | define this macro if you do not need to adjust the scheduling |
13786 | priorities of insns. */ | |
bef84347 | 13787 | |
c237e94a | 13788 | static int |
a2369ed3 | 13789 | rs6000_adjust_priority (rtx insn ATTRIBUTE_UNUSED, int priority) |
bef84347 | 13790 | { |
a4f6c312 SS |
13791 | /* On machines (like the 750) which have asymmetric integer units, |
13792 | where one integer unit can do multiply and divides and the other | |
13793 | can't, reduce the priority of multiply/divide so it is scheduled | |
13794 | before other integer operations. */ | |
bef84347 VM |
13795 | |
13796 | #if 0 | |
2c3c49de | 13797 | if (! INSN_P (insn)) |
bef84347 VM |
13798 | return priority; |
13799 | ||
13800 | if (GET_CODE (PATTERN (insn)) == USE) | |
13801 | return priority; | |
13802 | ||
13803 | switch (rs6000_cpu_attr) { | |
13804 | case CPU_PPC750: | |
13805 | switch (get_attr_type (insn)) | |
13806 | { | |
13807 | default: | |
13808 | break; | |
13809 | ||
13810 | case TYPE_IMUL: | |
13811 | case TYPE_IDIV: | |
3cb999d8 DE |
13812 | fprintf (stderr, "priority was %#x (%d) before adjustment\n", |
13813 | priority, priority); | |
bef84347 VM |
13814 | if (priority >= 0 && priority < 0x01000000) |
13815 | priority >>= 3; | |
13816 | break; | |
13817 | } | |
13818 | } | |
13819 | #endif | |
13820 | ||
79ae11c4 DN |
13821 | if (is_dispatch_slot_restricted (insn) |
13822 | && reload_completed | |
13823 | && current_sched_info->sched_max_insns_priority | |
13824 | && rs6000_sched_restricted_insns_priority) | |
13825 | { | |
13826 | ||
13827 | /* Prioritize insns that can be dispatched only in the first dispatch slot. */ | |
13828 | if (rs6000_sched_restricted_insns_priority == 1) | |
13829 | /* Attach highest priority to insn. This means that in | |
13830 | haifa-sched.c:ready_sort(), dispatch-slot restriction considerations | |
13831 | precede 'priority' (critical path) considerations. */ | |
13832 | return current_sched_info->sched_max_insns_priority; | |
13833 | else if (rs6000_sched_restricted_insns_priority == 2) | |
13834 | /* Increase priority of insn by a minimal amount. This means that in | |
13835 | haifa-sched.c:ready_sort(), only 'priority' (critical path) considerations | |
13836 | precede dispatch-slot restriction considerations. */ | |
13837 | return (priority + 1); | |
13838 | } | |
13839 | ||
bef84347 VM |
13840 | return priority; |
13841 | } | |
13842 | ||
a4f6c312 SS |
13843 | /* Return how many instructions the machine can issue per cycle. */ |
13844 | ||
c237e94a | 13845 | static int |
863d938c | 13846 | rs6000_issue_rate (void) |
b6c9286a | 13847 | { |
3317bab1 DE |
13848 | /* Use issue rate of 1 for first scheduling pass to decrease degradation. */ |
13849 | if (!reload_completed) | |
13850 | return 1; | |
13851 | ||
b6c9286a | 13852 | switch (rs6000_cpu_attr) { |
3cb999d8 DE |
13853 | case CPU_RIOS1: /* ? */ |
13854 | case CPU_RS64A: | |
13855 | case CPU_PPC601: /* ? */ | |
ed947a96 | 13856 | case CPU_PPC7450: |
3cb999d8 | 13857 | return 3; |
b54cf83a | 13858 | case CPU_PPC440: |
b6c9286a | 13859 | case CPU_PPC603: |
bef84347 | 13860 | case CPU_PPC750: |
ed947a96 | 13861 | case CPU_PPC7400: |
be12c2b0 | 13862 | case CPU_PPC8540: |
bef84347 | 13863 | return 2; |
3cb999d8 | 13864 | case CPU_RIOS2: |
b6c9286a | 13865 | case CPU_PPC604: |
19684119 | 13866 | case CPU_PPC604E: |
b6c9286a | 13867 | case CPU_PPC620: |
3cb999d8 | 13868 | case CPU_PPC630: |
b6c9286a | 13869 | return 4; |
cbe26ab8 DN |
13870 | case CPU_POWER4: |
13871 | return 5; | |
b6c9286a MM |
13872 | default: |
13873 | return 1; | |
13874 | } | |
13875 | } | |
13876 | ||
be12c2b0 VM |
13877 | /* Return how many instructions to look ahead for better insn |
13878 | scheduling. */ | |
13879 | ||
13880 | static int | |
863d938c | 13881 | rs6000_use_sched_lookahead (void) |
be12c2b0 VM |
13882 | { |
13883 | if (rs6000_cpu_attr == CPU_PPC8540) | |
13884 | return 4; | |
13885 | return 0; | |
13886 | } | |
13887 | ||
569fa502 DN |
13888 | /* Determine is PAT refers to memory. */ |
13889 | ||
13890 | static bool | |
13891 | is_mem_ref (rtx pat) | |
13892 | { | |
13893 | const char * fmt; | |
13894 | int i, j; | |
13895 | bool ret = false; | |
13896 | ||
13897 | if (GET_CODE (pat) == MEM) | |
13898 | return true; | |
13899 | ||
13900 | /* Recursively process the pattern. */ | |
13901 | fmt = GET_RTX_FORMAT (GET_CODE (pat)); | |
13902 | ||
13903 | for (i = GET_RTX_LENGTH (GET_CODE (pat)) - 1; i >= 0 && !ret; i--) | |
13904 | { | |
13905 | if (fmt[i] == 'e') | |
13906 | ret |= is_mem_ref (XEXP (pat, i)); | |
13907 | else if (fmt[i] == 'E') | |
13908 | for (j = XVECLEN (pat, i) - 1; j >= 0; j--) | |
13909 | ret |= is_mem_ref (XVECEXP (pat, i, j)); | |
13910 | } | |
13911 | ||
13912 | return ret; | |
13913 | } | |
13914 | ||
13915 | /* Determine if PAT is a PATTERN of a load insn. */ | |
13916 | ||
13917 | static bool | |
13918 | is_load_insn1 (rtx pat) | |
13919 | { | |
13920 | if (!pat || pat == NULL_RTX) | |
13921 | return false; | |
13922 | ||
13923 | if (GET_CODE (pat) == SET) | |
13924 | return is_mem_ref (SET_SRC (pat)); | |
13925 | ||
13926 | if (GET_CODE (pat) == PARALLEL) | |
13927 | { | |
13928 | int i; | |
13929 | ||
13930 | for (i = 0; i < XVECLEN (pat, 0); i++) | |
13931 | if (is_load_insn1 (XVECEXP (pat, 0, i))) | |
13932 | return true; | |
13933 | } | |
13934 | ||
13935 | return false; | |
13936 | } | |
13937 | ||
13938 | /* Determine if INSN loads from memory. */ | |
13939 | ||
13940 | static bool | |
13941 | is_load_insn (rtx insn) | |
13942 | { | |
13943 | if (!insn || !INSN_P (insn)) | |
13944 | return false; | |
13945 | ||
13946 | if (GET_CODE (insn) == CALL_INSN) | |
13947 | return false; | |
13948 | ||
13949 | return is_load_insn1 (PATTERN (insn)); | |
13950 | } | |
13951 | ||
13952 | /* Determine if PAT is a PATTERN of a store insn. */ | |
13953 | ||
13954 | static bool | |
13955 | is_store_insn1 (rtx pat) | |
13956 | { | |
13957 | if (!pat || pat == NULL_RTX) | |
13958 | return false; | |
13959 | ||
13960 | if (GET_CODE (pat) == SET) | |
13961 | return is_mem_ref (SET_DEST (pat)); | |
13962 | ||
13963 | if (GET_CODE (pat) == PARALLEL) | |
13964 | { | |
13965 | int i; | |
13966 | ||
13967 | for (i = 0; i < XVECLEN (pat, 0); i++) | |
13968 | if (is_store_insn1 (XVECEXP (pat, 0, i))) | |
13969 | return true; | |
13970 | } | |
13971 | ||
13972 | return false; | |
13973 | } | |
13974 | ||
13975 | /* Determine if INSN stores to memory. */ | |
13976 | ||
13977 | static bool | |
13978 | is_store_insn (rtx insn) | |
13979 | { | |
13980 | if (!insn || !INSN_P (insn)) | |
13981 | return false; | |
13982 | ||
13983 | return is_store_insn1 (PATTERN (insn)); | |
13984 | } | |
13985 | ||
13986 | /* Returns whether the dependence between INSN and NEXT is considered | |
13987 | costly by the given target. */ | |
13988 | ||
13989 | static bool | |
13990 | rs6000_is_costly_dependence (rtx insn, rtx next, rtx link, int cost, int distance) | |
13991 | { | |
13992 | /* If the flag is not enbled - no dependence is considered costly; | |
13993 | allow all dependent insns in the same group. | |
13994 | This is the most aggressive option. */ | |
13995 | if (rs6000_sched_costly_dep == no_dep_costly) | |
13996 | return false; | |
13997 | ||
13998 | /* If the flag is set to 1 - a dependence is always considered costly; | |
13999 | do not allow dependent instructions in the same group. | |
14000 | This is the most conservative option. */ | |
14001 | if (rs6000_sched_costly_dep == all_deps_costly) | |
14002 | return true; | |
14003 | ||
14004 | if (rs6000_sched_costly_dep == store_to_load_dep_costly | |
14005 | && is_load_insn (next) | |
14006 | && is_store_insn (insn)) | |
14007 | /* Prevent load after store in the same group. */ | |
14008 | return true; | |
14009 | ||
14010 | if (rs6000_sched_costly_dep == true_store_to_load_dep_costly | |
14011 | && is_load_insn (next) | |
14012 | && is_store_insn (insn) | |
14013 | && (!link || (int) REG_NOTE_KIND (link) == 0)) | |
14014 | /* Prevent load after store in the same group if it is a true dependence. */ | |
14015 | return true; | |
14016 | ||
14017 | /* The flag is set to X; dependences with latency >= X are considered costly, | |
14018 | and will not be scheduled in the same group. */ | |
14019 | if (rs6000_sched_costly_dep <= max_dep_latency | |
14020 | && ((cost - distance) >= (int)rs6000_sched_costly_dep)) | |
14021 | return true; | |
14022 | ||
14023 | return false; | |
14024 | } | |
14025 | ||
cbe26ab8 DN |
14026 | /* Return the next insn after INSN that is found before TAIL is reached, |
14027 | skipping any "non-active" insns - insns that will not actually occupy | |
14028 | an issue slot. Return NULL_RTX if such an insn is not found. */ | |
14029 | ||
14030 | static rtx | |
14031 | get_next_active_insn (rtx insn, rtx tail) | |
14032 | { | |
14033 | rtx next_insn; | |
14034 | ||
14035 | if (!insn || insn == tail) | |
14036 | return NULL_RTX; | |
14037 | ||
14038 | next_insn = NEXT_INSN (insn); | |
14039 | ||
14040 | while (next_insn | |
14041 | && next_insn != tail | |
14042 | && (GET_CODE(next_insn) == NOTE | |
14043 | || GET_CODE (PATTERN (next_insn)) == USE | |
14044 | || GET_CODE (PATTERN (next_insn)) == CLOBBER)) | |
14045 | { | |
14046 | next_insn = NEXT_INSN (next_insn); | |
14047 | } | |
14048 | ||
14049 | if (!next_insn || next_insn == tail) | |
14050 | return NULL_RTX; | |
14051 | ||
14052 | return next_insn; | |
14053 | } | |
14054 | ||
839a4992 | 14055 | /* Return whether the presence of INSN causes a dispatch group termination |
cbe26ab8 DN |
14056 | of group WHICH_GROUP. |
14057 | ||
14058 | If WHICH_GROUP == current_group, this function will return true if INSN | |
14059 | causes the termination of the current group (i.e, the dispatch group to | |
14060 | which INSN belongs). This means that INSN will be the last insn in the | |
14061 | group it belongs to. | |
14062 | ||
14063 | If WHICH_GROUP == previous_group, this function will return true if INSN | |
14064 | causes the termination of the previous group (i.e, the dispatch group that | |
14065 | precedes the group to which INSN belongs). This means that INSN will be | |
14066 | the first insn in the group it belongs to). */ | |
14067 | ||
14068 | static bool | |
14069 | insn_terminates_group_p (rtx insn, enum group_termination which_group) | |
14070 | { | |
14071 | enum attr_type type; | |
14072 | ||
14073 | if (! insn) | |
14074 | return false; | |
569fa502 | 14075 | |
cbe26ab8 DN |
14076 | type = get_attr_type (insn); |
14077 | ||
14078 | if (is_microcoded_insn (insn)) | |
14079 | return true; | |
14080 | ||
14081 | if (which_group == current_group) | |
14082 | { | |
14083 | if (is_branch_slot_insn (insn)) | |
14084 | return true; | |
14085 | return false; | |
14086 | } | |
14087 | else if (which_group == previous_group) | |
14088 | { | |
14089 | if (is_dispatch_slot_restricted (insn)) | |
14090 | return true; | |
14091 | return false; | |
14092 | } | |
14093 | ||
14094 | return false; | |
14095 | } | |
14096 | ||
839a4992 | 14097 | /* Return true if it is recommended to keep NEXT_INSN "far" (in a separate |
cbe26ab8 DN |
14098 | dispatch group) from the insns in GROUP_INSNS. Return false otherwise. */ |
14099 | ||
14100 | static bool | |
14101 | is_costly_group (rtx *group_insns, rtx next_insn) | |
14102 | { | |
14103 | int i; | |
14104 | rtx link; | |
14105 | int cost; | |
14106 | int issue_rate = rs6000_issue_rate (); | |
14107 | ||
14108 | for (i = 0; i < issue_rate; i++) | |
14109 | { | |
14110 | rtx insn = group_insns[i]; | |
14111 | if (!insn) | |
14112 | continue; | |
14113 | for (link = INSN_DEPEND (insn); link != 0; link = XEXP (link, 1)) | |
14114 | { | |
14115 | rtx next = XEXP (link, 0); | |
14116 | if (next == next_insn) | |
14117 | { | |
14118 | cost = insn_cost (insn, link, next_insn); | |
14119 | if (rs6000_is_costly_dependence (insn, next_insn, link, cost, 0)) | |
14120 | return true; | |
14121 | } | |
14122 | } | |
14123 | } | |
14124 | ||
14125 | return false; | |
14126 | } | |
14127 | ||
14128 | /* Utility of the function redefine_groups. | |
14129 | Check if it is too costly to schedule NEXT_INSN together with GROUP_INSNS | |
14130 | in the same dispatch group. If so, insert nops before NEXT_INSN, in order | |
14131 | to keep it "far" (in a separate group) from GROUP_INSNS, following | |
14132 | one of the following schemes, depending on the value of the flag | |
14133 | -minsert_sched_nops = X: | |
14134 | (1) X == sched_finish_regroup_exact: insert exactly as many nops as needed | |
839a4992 | 14135 | in order to force NEXT_INSN into a separate group. |
cbe26ab8 DN |
14136 | (2) X < sched_finish_regroup_exact: insert exactly X nops. |
14137 | GROUP_END, CAN_ISSUE_MORE and GROUP_COUNT record the state after nop | |
14138 | insertion (has a group just ended, how many vacant issue slots remain in the | |
14139 | last group, and how many dispatch groups were encountered so far). */ | |
14140 | ||
14141 | static int | |
14142 | force_new_group (int sched_verbose, FILE *dump, rtx *group_insns, rtx next_insn, | |
14143 | bool *group_end, int can_issue_more, int *group_count) | |
14144 | { | |
14145 | rtx nop; | |
14146 | bool force; | |
14147 | int issue_rate = rs6000_issue_rate (); | |
14148 | bool end = *group_end; | |
14149 | int i; | |
14150 | ||
14151 | if (next_insn == NULL_RTX) | |
14152 | return can_issue_more; | |
14153 | ||
14154 | if (rs6000_sched_insert_nops > sched_finish_regroup_exact) | |
14155 | return can_issue_more; | |
14156 | ||
14157 | force = is_costly_group (group_insns, next_insn); | |
14158 | if (!force) | |
14159 | return can_issue_more; | |
14160 | ||
14161 | if (sched_verbose > 6) | |
14162 | fprintf (dump,"force: group count = %d, can_issue_more = %d\n", | |
14163 | *group_count ,can_issue_more); | |
14164 | ||
14165 | if (rs6000_sched_insert_nops == sched_finish_regroup_exact) | |
14166 | { | |
14167 | if (*group_end) | |
14168 | can_issue_more = 0; | |
14169 | ||
14170 | /* Since only a branch can be issued in the last issue_slot, it is | |
14171 | sufficient to insert 'can_issue_more - 1' nops if next_insn is not | |
14172 | a branch. If next_insn is a branch, we insert 'can_issue_more' nops; | |
14173 | in this case the last nop will start a new group and the branch will be | |
14174 | forced to the new group. */ | |
14175 | if (can_issue_more && !is_branch_slot_insn (next_insn)) | |
14176 | can_issue_more--; | |
14177 | ||
14178 | while (can_issue_more > 0) | |
14179 | { | |
14180 | nop = gen_nop(); | |
14181 | emit_insn_before (nop, next_insn); | |
14182 | can_issue_more--; | |
14183 | } | |
14184 | ||
14185 | *group_end = true; | |
14186 | return 0; | |
14187 | } | |
14188 | ||
14189 | if (rs6000_sched_insert_nops < sched_finish_regroup_exact) | |
14190 | { | |
14191 | int n_nops = rs6000_sched_insert_nops; | |
14192 | ||
14193 | /* Nops can't be issued from the branch slot, so the effective | |
14194 | issue_rate for nops is 'issue_rate - 1'. */ | |
14195 | if (can_issue_more == 0) | |
14196 | can_issue_more = issue_rate; | |
14197 | can_issue_more--; | |
14198 | if (can_issue_more == 0) | |
14199 | { | |
14200 | can_issue_more = issue_rate - 1; | |
14201 | (*group_count)++; | |
14202 | end = true; | |
14203 | for (i = 0; i < issue_rate; i++) | |
14204 | { | |
14205 | group_insns[i] = 0; | |
14206 | } | |
14207 | } | |
14208 | ||
14209 | while (n_nops > 0) | |
14210 | { | |
14211 | nop = gen_nop (); | |
14212 | emit_insn_before (nop, next_insn); | |
14213 | if (can_issue_more == issue_rate - 1) /* new group begins */ | |
14214 | end = false; | |
14215 | can_issue_more--; | |
14216 | if (can_issue_more == 0) | |
14217 | { | |
14218 | can_issue_more = issue_rate - 1; | |
14219 | (*group_count)++; | |
14220 | end = true; | |
14221 | for (i = 0; i < issue_rate; i++) | |
14222 | { | |
14223 | group_insns[i] = 0; | |
14224 | } | |
14225 | } | |
14226 | n_nops--; | |
14227 | } | |
14228 | ||
14229 | /* Scale back relative to 'issue_rate' (instead of 'issue_rate - 1'). */ | |
14230 | can_issue_more++; | |
14231 | ||
14232 | *group_end = /* Is next_insn going to start a new group? */ | |
14233 | (end | |
14234 | || (can_issue_more == 1 && !is_branch_slot_insn (next_insn)) | |
14235 | || (can_issue_more <= 2 && is_cracked_insn (next_insn)) | |
14236 | || (can_issue_more < issue_rate && | |
14237 | insn_terminates_group_p (next_insn, previous_group))); | |
14238 | if (*group_end && end) | |
14239 | (*group_count)--; | |
14240 | ||
14241 | if (sched_verbose > 6) | |
14242 | fprintf (dump, "done force: group count = %d, can_issue_more = %d\n", | |
14243 | *group_count, can_issue_more); | |
14244 | return can_issue_more; | |
14245 | } | |
14246 | ||
14247 | return can_issue_more; | |
14248 | } | |
14249 | ||
14250 | /* This function tries to synch the dispatch groups that the compiler "sees" | |
14251 | with the dispatch groups that the processor dispatcher is expected to | |
14252 | form in practice. It tries to achieve this synchronization by forcing the | |
14253 | estimated processor grouping on the compiler (as opposed to the function | |
14254 | 'pad_goups' which tries to force the scheduler's grouping on the processor). | |
14255 | ||
14256 | The function scans the insn sequence between PREV_HEAD_INSN and TAIL and | |
14257 | examines the (estimated) dispatch groups that will be formed by the processor | |
14258 | dispatcher. It marks these group boundaries to reflect the estimated | |
14259 | processor grouping, overriding the grouping that the scheduler had marked. | |
14260 | Depending on the value of the flag '-minsert-sched-nops' this function can | |
14261 | force certain insns into separate groups or force a certain distance between | |
14262 | them by inserting nops, for example, if there exists a "costly dependence" | |
14263 | between the insns. | |
14264 | ||
14265 | The function estimates the group boundaries that the processor will form as | |
14266 | folllows: It keeps track of how many vacant issue slots are available after | |
14267 | each insn. A subsequent insn will start a new group if one of the following | |
14268 | 4 cases applies: | |
14269 | - no more vacant issue slots remain in the current dispatch group. | |
14270 | - only the last issue slot, which is the branch slot, is vacant, but the next | |
14271 | insn is not a branch. | |
14272 | - only the last 2 or less issue slots, including the branch slot, are vacant, | |
14273 | which means that a cracked insn (which occupies two issue slots) can't be | |
14274 | issued in this group. | |
14275 | - less than 'issue_rate' slots are vacant, and the next insn always needs to | |
14276 | start a new group. */ | |
14277 | ||
14278 | static int | |
14279 | redefine_groups (FILE *dump, int sched_verbose, rtx prev_head_insn, rtx tail) | |
14280 | { | |
14281 | rtx insn, next_insn; | |
14282 | int issue_rate; | |
14283 | int can_issue_more; | |
14284 | int slot, i; | |
14285 | bool group_end; | |
14286 | int group_count = 0; | |
14287 | rtx *group_insns; | |
14288 | ||
14289 | /* Initialize. */ | |
14290 | issue_rate = rs6000_issue_rate (); | |
14291 | group_insns = alloca (issue_rate * sizeof (rtx)); | |
14292 | for (i = 0; i < issue_rate; i++) | |
14293 | { | |
14294 | group_insns[i] = 0; | |
14295 | } | |
14296 | can_issue_more = issue_rate; | |
14297 | slot = 0; | |
14298 | insn = get_next_active_insn (prev_head_insn, tail); | |
14299 | group_end = false; | |
14300 | ||
14301 | while (insn != NULL_RTX) | |
14302 | { | |
14303 | slot = (issue_rate - can_issue_more); | |
14304 | group_insns[slot] = insn; | |
14305 | can_issue_more = | |
14306 | rs6000_variable_issue (dump, sched_verbose, insn, can_issue_more); | |
14307 | if (insn_terminates_group_p (insn, current_group)) | |
14308 | can_issue_more = 0; | |
14309 | ||
14310 | next_insn = get_next_active_insn (insn, tail); | |
14311 | if (next_insn == NULL_RTX) | |
14312 | return group_count + 1; | |
14313 | ||
14314 | group_end = /* Is next_insn going to start a new group? */ | |
14315 | (can_issue_more == 0 | |
14316 | || (can_issue_more == 1 && !is_branch_slot_insn (next_insn)) | |
14317 | || (can_issue_more <= 2 && is_cracked_insn (next_insn)) | |
14318 | || (can_issue_more < issue_rate && | |
14319 | insn_terminates_group_p (next_insn, previous_group))); | |
14320 | ||
14321 | can_issue_more = force_new_group (sched_verbose, dump, group_insns, | |
14322 | next_insn, &group_end, can_issue_more, &group_count); | |
14323 | ||
14324 | if (group_end) | |
14325 | { | |
14326 | group_count++; | |
14327 | can_issue_more = 0; | |
14328 | for (i = 0; i < issue_rate; i++) | |
14329 | { | |
14330 | group_insns[i] = 0; | |
14331 | } | |
14332 | } | |
14333 | ||
14334 | if (GET_MODE (next_insn) == TImode && can_issue_more) | |
14335 | PUT_MODE(next_insn, VOIDmode); | |
14336 | else if (!can_issue_more && GET_MODE (next_insn) != TImode) | |
14337 | PUT_MODE (next_insn, TImode); | |
14338 | ||
14339 | insn = next_insn; | |
14340 | if (can_issue_more == 0) | |
14341 | can_issue_more = issue_rate; | |
14342 | } /* while */ | |
14343 | ||
14344 | return group_count; | |
14345 | } | |
14346 | ||
14347 | /* Scan the insn sequence between PREV_HEAD_INSN and TAIL and examine the | |
14348 | dispatch group boundaries that the scheduler had marked. Pad with nops | |
14349 | any dispatch groups which have vacant issue slots, in order to force the | |
14350 | scheduler's grouping on the processor dispatcher. The function | |
14351 | returns the number of dispatch groups found. */ | |
14352 | ||
14353 | static int | |
14354 | pad_groups (FILE *dump, int sched_verbose, rtx prev_head_insn, rtx tail) | |
14355 | { | |
14356 | rtx insn, next_insn; | |
14357 | rtx nop; | |
14358 | int issue_rate; | |
14359 | int can_issue_more; | |
14360 | int group_end; | |
14361 | int group_count = 0; | |
14362 | ||
14363 | /* Initialize issue_rate. */ | |
14364 | issue_rate = rs6000_issue_rate (); | |
14365 | can_issue_more = issue_rate; | |
14366 | ||
14367 | insn = get_next_active_insn (prev_head_insn, tail); | |
14368 | next_insn = get_next_active_insn (insn, tail); | |
14369 | ||
14370 | while (insn != NULL_RTX) | |
14371 | { | |
14372 | can_issue_more = | |
14373 | rs6000_variable_issue (dump, sched_verbose, insn, can_issue_more); | |
14374 | ||
14375 | group_end = (next_insn == NULL_RTX || GET_MODE (next_insn) == TImode); | |
14376 | ||
14377 | if (next_insn == NULL_RTX) | |
14378 | break; | |
14379 | ||
14380 | if (group_end) | |
14381 | { | |
14382 | /* If the scheduler had marked group termination at this location | |
14383 | (between insn and next_indn), and neither insn nor next_insn will | |
14384 | force group termination, pad the group with nops to force group | |
14385 | termination. */ | |
14386 | if (can_issue_more | |
14387 | && (rs6000_sched_insert_nops == sched_finish_pad_groups) | |
14388 | && !insn_terminates_group_p (insn, current_group) | |
14389 | && !insn_terminates_group_p (next_insn, previous_group)) | |
14390 | { | |
14391 | if (!is_branch_slot_insn(next_insn)) | |
14392 | can_issue_more--; | |
14393 | ||
14394 | while (can_issue_more) | |
14395 | { | |
14396 | nop = gen_nop (); | |
14397 | emit_insn_before (nop, next_insn); | |
14398 | can_issue_more--; | |
14399 | } | |
14400 | } | |
14401 | ||
14402 | can_issue_more = issue_rate; | |
14403 | group_count++; | |
14404 | } | |
14405 | ||
14406 | insn = next_insn; | |
14407 | next_insn = get_next_active_insn (insn, tail); | |
14408 | } | |
14409 | ||
14410 | return group_count; | |
14411 | } | |
14412 | ||
14413 | /* The following function is called at the end of scheduling BB. | |
14414 | After reload, it inserts nops at insn group bundling. */ | |
14415 | ||
14416 | static void | |
38f391a5 | 14417 | rs6000_sched_finish (FILE *dump, int sched_verbose) |
cbe26ab8 DN |
14418 | { |
14419 | int n_groups; | |
14420 | ||
14421 | if (sched_verbose) | |
14422 | fprintf (dump, "=== Finishing schedule.\n"); | |
14423 | ||
14424 | if (reload_completed && rs6000_cpu == PROCESSOR_POWER4) | |
14425 | { | |
14426 | if (rs6000_sched_insert_nops == sched_finish_none) | |
14427 | return; | |
14428 | ||
14429 | if (rs6000_sched_insert_nops == sched_finish_pad_groups) | |
14430 | n_groups = pad_groups (dump, sched_verbose, | |
14431 | current_sched_info->prev_head, | |
14432 | current_sched_info->next_tail); | |
14433 | else | |
14434 | n_groups = redefine_groups (dump, sched_verbose, | |
14435 | current_sched_info->prev_head, | |
14436 | current_sched_info->next_tail); | |
14437 | ||
14438 | if (sched_verbose >= 6) | |
14439 | { | |
14440 | fprintf (dump, "ngroups = %d\n", n_groups); | |
14441 | print_rtl (dump, current_sched_info->prev_head); | |
14442 | fprintf (dump, "Done finish_sched\n"); | |
14443 | } | |
14444 | } | |
14445 | } | |
b6c9286a | 14446 | \f |
b6c9286a MM |
14447 | /* Length in units of the trampoline for entering a nested function. */ |
14448 | ||
14449 | int | |
863d938c | 14450 | rs6000_trampoline_size (void) |
b6c9286a MM |
14451 | { |
14452 | int ret = 0; | |
14453 | ||
14454 | switch (DEFAULT_ABI) | |
14455 | { | |
14456 | default: | |
14457 | abort (); | |
14458 | ||
14459 | case ABI_AIX: | |
8f802bfb | 14460 | ret = (TARGET_32BIT) ? 12 : 24; |
b6c9286a MM |
14461 | break; |
14462 | ||
4dabc42d | 14463 | case ABI_DARWIN: |
b6c9286a | 14464 | case ABI_V4: |
03a7e1a5 | 14465 | ret = (TARGET_32BIT) ? 40 : 48; |
b6c9286a | 14466 | break; |
b6c9286a MM |
14467 | } |
14468 | ||
14469 | return ret; | |
14470 | } | |
14471 | ||
14472 | /* Emit RTL insns to initialize the variable parts of a trampoline. | |
14473 | FNADDR is an RTX for the address of the function's pure code. | |
14474 | CXT is an RTX for the static chain value for the function. */ | |
14475 | ||
14476 | void | |
a2369ed3 | 14477 | rs6000_initialize_trampoline (rtx addr, rtx fnaddr, rtx cxt) |
b6c9286a | 14478 | { |
ac2a93a1 | 14479 | enum machine_mode pmode = Pmode; |
8bd04c56 MM |
14480 | int regsize = (TARGET_32BIT) ? 4 : 8; |
14481 | rtx ctx_reg = force_reg (pmode, cxt); | |
b6c9286a MM |
14482 | |
14483 | switch (DEFAULT_ABI) | |
14484 | { | |
14485 | default: | |
14486 | abort (); | |
14487 | ||
8bd04c56 | 14488 | /* Macros to shorten the code expansions below. */ |
39403d82 | 14489 | #define MEM_DEREF(addr) gen_rtx_MEM (pmode, memory_address (pmode, addr)) |
c5c76735 JL |
14490 | #define MEM_PLUS(addr,offset) \ |
14491 | gen_rtx_MEM (pmode, memory_address (pmode, plus_constant (addr, offset))) | |
7c59dc5d | 14492 | |
b6c9286a MM |
14493 | /* Under AIX, just build the 3 word function descriptor */ |
14494 | case ABI_AIX: | |
8bd04c56 MM |
14495 | { |
14496 | rtx fn_reg = gen_reg_rtx (pmode); | |
14497 | rtx toc_reg = gen_reg_rtx (pmode); | |
14498 | emit_move_insn (fn_reg, MEM_DEREF (fnaddr)); | |
1cb18e3c | 14499 | emit_move_insn (toc_reg, MEM_PLUS (fnaddr, regsize)); |
8bd04c56 MM |
14500 | emit_move_insn (MEM_DEREF (addr), fn_reg); |
14501 | emit_move_insn (MEM_PLUS (addr, regsize), toc_reg); | |
14502 | emit_move_insn (MEM_PLUS (addr, 2*regsize), ctx_reg); | |
14503 | } | |
b6c9286a MM |
14504 | break; |
14505 | ||
4dabc42d TC |
14506 | /* Under V.4/eabi/darwin, __trampoline_setup does the real work. */ |
14507 | case ABI_DARWIN: | |
b6c9286a | 14508 | case ABI_V4: |
39403d82 | 14509 | emit_library_call (gen_rtx_SYMBOL_REF (SImode, "__trampoline_setup"), |
eaf1bcf1 MM |
14510 | FALSE, VOIDmode, 4, |
14511 | addr, pmode, | |
14512 | GEN_INT (rs6000_trampoline_size ()), SImode, | |
14513 | fnaddr, pmode, | |
14514 | ctx_reg, pmode); | |
b6c9286a | 14515 | break; |
b6c9286a MM |
14516 | } |
14517 | ||
14518 | return; | |
14519 | } | |
7509c759 MM |
14520 | |
14521 | \f | |
91d231cb | 14522 | /* Table of valid machine attributes. */ |
a4f6c312 | 14523 | |
91d231cb | 14524 | const struct attribute_spec rs6000_attribute_table[] = |
7509c759 | 14525 | { |
91d231cb | 14526 | /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */ |
a5c76ee6 ZW |
14527 | { "longcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute }, |
14528 | { "shortcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute }, | |
14529 | { NULL, 0, 0, false, false, false, NULL } | |
91d231cb | 14530 | }; |
7509c759 | 14531 | |
a5c76ee6 ZW |
14532 | /* Handle a "longcall" or "shortcall" attribute; arguments as in |
14533 | struct attribute_spec.handler. */ | |
a4f6c312 | 14534 | |
91d231cb | 14535 | static tree |
a2369ed3 DJ |
14536 | rs6000_handle_longcall_attribute (tree *node, tree name, |
14537 | tree args ATTRIBUTE_UNUSED, | |
14538 | int flags ATTRIBUTE_UNUSED, | |
14539 | bool *no_add_attrs) | |
91d231cb JM |
14540 | { |
14541 | if (TREE_CODE (*node) != FUNCTION_TYPE | |
14542 | && TREE_CODE (*node) != FIELD_DECL | |
14543 | && TREE_CODE (*node) != TYPE_DECL) | |
14544 | { | |
14545 | warning ("`%s' attribute only applies to functions", | |
14546 | IDENTIFIER_POINTER (name)); | |
14547 | *no_add_attrs = true; | |
14548 | } | |
6a4cee5f | 14549 | |
91d231cb | 14550 | return NULL_TREE; |
7509c759 MM |
14551 | } |
14552 | ||
a5c76ee6 ZW |
14553 | /* Set longcall attributes on all functions declared when |
14554 | rs6000_default_long_calls is true. */ | |
14555 | static void | |
a2369ed3 | 14556 | rs6000_set_default_type_attributes (tree type) |
a5c76ee6 ZW |
14557 | { |
14558 | if (rs6000_default_long_calls | |
14559 | && (TREE_CODE (type) == FUNCTION_TYPE | |
14560 | || TREE_CODE (type) == METHOD_TYPE)) | |
14561 | TYPE_ATTRIBUTES (type) = tree_cons (get_identifier ("longcall"), | |
14562 | NULL_TREE, | |
14563 | TYPE_ATTRIBUTES (type)); | |
14564 | } | |
14565 | ||
3cb999d8 DE |
14566 | /* Return a reference suitable for calling a function with the |
14567 | longcall attribute. */ | |
a4f6c312 | 14568 | |
6a4cee5f | 14569 | struct rtx_def * |
a2369ed3 | 14570 | rs6000_longcall_ref (rtx call_ref) |
6a4cee5f | 14571 | { |
d330fd93 | 14572 | const char *call_name; |
6a4cee5f MM |
14573 | tree node; |
14574 | ||
14575 | if (GET_CODE (call_ref) != SYMBOL_REF) | |
14576 | return call_ref; | |
14577 | ||
14578 | /* System V adds '.' to the internal name, so skip them. */ | |
14579 | call_name = XSTR (call_ref, 0); | |
14580 | if (*call_name == '.') | |
14581 | { | |
14582 | while (*call_name == '.') | |
14583 | call_name++; | |
14584 | ||
14585 | node = get_identifier (call_name); | |
39403d82 | 14586 | call_ref = gen_rtx_SYMBOL_REF (VOIDmode, IDENTIFIER_POINTER (node)); |
6a4cee5f MM |
14587 | } |
14588 | ||
14589 | return force_reg (Pmode, call_ref); | |
14590 | } | |
7509c759 | 14591 | \f |
b64a1b53 RH |
14592 | #ifdef USING_ELFOS_H |
14593 | ||
7509c759 MM |
14594 | /* A C statement or statements to switch to the appropriate section |
14595 | for output of RTX in mode MODE. You can assume that RTX is some | |
14596 | kind of constant in RTL. The argument MODE is redundant except in | |
14597 | the case of a `const_int' rtx. Select the section by calling | |
14598 | `text_section' or one of the alternatives for other sections. | |
14599 | ||
14600 | Do not define this macro if you put all constants in the read-only | |
14601 | data section. */ | |
14602 | ||
b64a1b53 | 14603 | static void |
a2369ed3 DJ |
14604 | rs6000_elf_select_rtx_section (enum machine_mode mode, rtx x, |
14605 | unsigned HOST_WIDE_INT align) | |
7509c759 | 14606 | { |
a9098fd0 | 14607 | if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode)) |
7509c759 | 14608 | toc_section (); |
7509c759 | 14609 | else |
b64a1b53 | 14610 | default_elf_select_rtx_section (mode, x, align); |
7509c759 MM |
14611 | } |
14612 | ||
14613 | /* A C statement or statements to switch to the appropriate | |
14614 | section for output of DECL. DECL is either a `VAR_DECL' node | |
14615 | or a constant of some sort. RELOC indicates whether forming | |
14616 | the initial value of DECL requires link-time relocations. */ | |
14617 | ||
ae46c4e0 | 14618 | static void |
a2369ed3 DJ |
14619 | rs6000_elf_select_section (tree decl, int reloc, |
14620 | unsigned HOST_WIDE_INT align) | |
7509c759 | 14621 | { |
f1384257 AM |
14622 | /* Pretend that we're always building for a shared library when |
14623 | ABI_AIX, because otherwise we end up with dynamic relocations | |
14624 | in read-only sections. This happens for function pointers, | |
14625 | references to vtables in typeinfo, and probably other cases. */ | |
0e5dbd9b DE |
14626 | default_elf_select_section_1 (decl, reloc, align, |
14627 | flag_pic || DEFAULT_ABI == ABI_AIX); | |
63019373 GK |
14628 | } |
14629 | ||
14630 | /* A C statement to build up a unique section name, expressed as a | |
14631 | STRING_CST node, and assign it to DECL_SECTION_NAME (decl). | |
14632 | RELOC indicates whether the initial value of EXP requires | |
14633 | link-time relocations. If you do not define this macro, GCC will use | |
14634 | the symbol name prefixed by `.' as the section name. Note - this | |
f5143c46 | 14635 | macro can now be called for uninitialized data items as well as |
4912a07c | 14636 | initialized data and functions. */ |
63019373 | 14637 | |
ae46c4e0 | 14638 | static void |
a2369ed3 | 14639 | rs6000_elf_unique_section (tree decl, int reloc) |
63019373 | 14640 | { |
f1384257 AM |
14641 | /* As above, pretend that we're always building for a shared library |
14642 | when ABI_AIX, to avoid dynamic relocations in read-only sections. */ | |
0e5dbd9b DE |
14643 | default_unique_section_1 (decl, reloc, |
14644 | flag_pic || DEFAULT_ABI == ABI_AIX); | |
7509c759 | 14645 | } |
d9407988 | 14646 | \f |
d1908feb JJ |
14647 | /* For a SYMBOL_REF, set generic flags and then perform some |
14648 | target-specific processing. | |
14649 | ||
d1908feb JJ |
14650 | When the AIX ABI is requested on a non-AIX system, replace the |
14651 | function name with the real name (with a leading .) rather than the | |
14652 | function descriptor name. This saves a lot of overriding code to | |
14653 | read the prefixes. */ | |
d9407988 | 14654 | |
fb49053f | 14655 | static void |
a2369ed3 | 14656 | rs6000_elf_encode_section_info (tree decl, rtx rtl, int first) |
d9407988 | 14657 | { |
d1908feb | 14658 | default_encode_section_info (decl, rtl, first); |
b2003250 | 14659 | |
d1908feb JJ |
14660 | if (first |
14661 | && TREE_CODE (decl) == FUNCTION_DECL | |
14662 | && !TARGET_AIX | |
14663 | && DEFAULT_ABI == ABI_AIX) | |
d9407988 | 14664 | { |
c6a2438a | 14665 | rtx sym_ref = XEXP (rtl, 0); |
d1908feb JJ |
14666 | size_t len = strlen (XSTR (sym_ref, 0)); |
14667 | char *str = alloca (len + 2); | |
14668 | str[0] = '.'; | |
14669 | memcpy (str + 1, XSTR (sym_ref, 0), len + 1); | |
14670 | XSTR (sym_ref, 0) = ggc_alloc_string (str, len + 1); | |
d9407988 | 14671 | } |
d9407988 MM |
14672 | } |
14673 | ||
0e5dbd9b | 14674 | static bool |
a2369ed3 | 14675 | rs6000_elf_in_small_data_p (tree decl) |
0e5dbd9b DE |
14676 | { |
14677 | if (rs6000_sdata == SDATA_NONE) | |
14678 | return false; | |
14679 | ||
14680 | if (TREE_CODE (decl) == VAR_DECL && DECL_SECTION_NAME (decl)) | |
14681 | { | |
14682 | const char *section = TREE_STRING_POINTER (DECL_SECTION_NAME (decl)); | |
14683 | if (strcmp (section, ".sdata") == 0 | |
14684 | || strcmp (section, ".sdata2") == 0 | |
20bfcd69 GK |
14685 | || strcmp (section, ".sbss") == 0 |
14686 | || strcmp (section, ".sbss2") == 0 | |
14687 | || strcmp (section, ".PPC.EMB.sdata0") == 0 | |
14688 | || strcmp (section, ".PPC.EMB.sbss0") == 0) | |
0e5dbd9b DE |
14689 | return true; |
14690 | } | |
14691 | else | |
14692 | { | |
14693 | HOST_WIDE_INT size = int_size_in_bytes (TREE_TYPE (decl)); | |
14694 | ||
14695 | if (size > 0 | |
307b599c | 14696 | && (unsigned HOST_WIDE_INT) size <= g_switch_value |
20bfcd69 GK |
14697 | /* If it's not public, and we're not going to reference it there, |
14698 | there's no need to put it in the small data section. */ | |
0e5dbd9b DE |
14699 | && (rs6000_sdata != SDATA_DATA || TREE_PUBLIC (decl))) |
14700 | return true; | |
14701 | } | |
14702 | ||
14703 | return false; | |
14704 | } | |
14705 | ||
b91da81f | 14706 | #endif /* USING_ELFOS_H */ |
000034eb | 14707 | |
a6c2a102 | 14708 | \f |
000034eb | 14709 | /* Return a REG that occurs in ADDR with coefficient 1. |
02441cd6 JL |
14710 | ADDR can be effectively incremented by incrementing REG. |
14711 | ||
14712 | r0 is special and we must not select it as an address | |
14713 | register by this routine since our caller will try to | |
14714 | increment the returned register via an "la" instruction. */ | |
000034eb DE |
14715 | |
14716 | struct rtx_def * | |
a2369ed3 | 14717 | find_addr_reg (rtx addr) |
000034eb DE |
14718 | { |
14719 | while (GET_CODE (addr) == PLUS) | |
14720 | { | |
02441cd6 JL |
14721 | if (GET_CODE (XEXP (addr, 0)) == REG |
14722 | && REGNO (XEXP (addr, 0)) != 0) | |
000034eb | 14723 | addr = XEXP (addr, 0); |
02441cd6 JL |
14724 | else if (GET_CODE (XEXP (addr, 1)) == REG |
14725 | && REGNO (XEXP (addr, 1)) != 0) | |
000034eb DE |
14726 | addr = XEXP (addr, 1); |
14727 | else if (CONSTANT_P (XEXP (addr, 0))) | |
14728 | addr = XEXP (addr, 1); | |
14729 | else if (CONSTANT_P (XEXP (addr, 1))) | |
14730 | addr = XEXP (addr, 0); | |
14731 | else | |
14732 | abort (); | |
14733 | } | |
02441cd6 | 14734 | if (GET_CODE (addr) == REG && REGNO (addr) != 0) |
000034eb DE |
14735 | return addr; |
14736 | abort (); | |
14737 | } | |
14738 | ||
a6c2a102 | 14739 | void |
a2369ed3 | 14740 | rs6000_fatal_bad_address (rtx op) |
a6c2a102 DE |
14741 | { |
14742 | fatal_insn ("bad address", op); | |
14743 | } | |
c8023011 | 14744 | |
ee890fe2 SS |
14745 | #if TARGET_MACHO |
14746 | ||
14747 | #if 0 | |
14748 | /* Returns 1 if OP is either a symbol reference or a sum of a symbol | |
14749 | reference and a constant. */ | |
14750 | ||
14751 | int | |
a2369ed3 | 14752 | symbolic_operand (rtx op) |
ee890fe2 SS |
14753 | { |
14754 | switch (GET_CODE (op)) | |
14755 | { | |
14756 | case SYMBOL_REF: | |
14757 | case LABEL_REF: | |
14758 | return 1; | |
14759 | case CONST: | |
14760 | op = XEXP (op, 0); | |
14761 | return (GET_CODE (op) == SYMBOL_REF || | |
14762 | (GET_CODE (XEXP (op, 0)) == SYMBOL_REF | |
14763 | || GET_CODE (XEXP (op, 0)) == LABEL_REF) | |
14764 | && GET_CODE (XEXP (op, 1)) == CONST_INT); | |
14765 | default: | |
14766 | return 0; | |
14767 | } | |
c8023011 | 14768 | } |
ee890fe2 SS |
14769 | #endif |
14770 | ||
efdba735 | 14771 | #if TARGET_MACHO |
ee890fe2 | 14772 | |
efdba735 | 14773 | static tree branch_island_list = 0; |
ee890fe2 | 14774 | |
efdba735 SH |
14775 | /* Remember to generate a branch island for far calls to the given |
14776 | function. */ | |
ee890fe2 | 14777 | |
efdba735 SH |
14778 | static void |
14779 | add_compiler_branch_island (tree label_name, tree function_name, int line_number) | |
ee890fe2 | 14780 | { |
efdba735 SH |
14781 | tree branch_island = build_tree_list (function_name, label_name); |
14782 | TREE_TYPE (branch_island) = build_int_2 (line_number, 0); | |
14783 | TREE_CHAIN (branch_island) = branch_island_list; | |
14784 | branch_island_list = branch_island; | |
ee890fe2 SS |
14785 | } |
14786 | ||
efdba735 SH |
14787 | #define BRANCH_ISLAND_LABEL_NAME(BRANCH_ISLAND) TREE_VALUE (BRANCH_ISLAND) |
14788 | #define BRANCH_ISLAND_FUNCTION_NAME(BRANCH_ISLAND) TREE_PURPOSE (BRANCH_ISLAND) | |
14789 | #define BRANCH_ISLAND_LINE_NUMBER(BRANCH_ISLAND) \ | |
14790 | TREE_INT_CST_LOW (TREE_TYPE (BRANCH_ISLAND)) | |
ee890fe2 | 14791 | |
efdba735 SH |
14792 | /* Generate far-jump branch islands for everything on the |
14793 | branch_island_list. Invoked immediately after the last instruction | |
14794 | of the epilogue has been emitted; the branch-islands must be | |
14795 | appended to, and contiguous with, the function body. Mach-O stubs | |
14796 | are generated in machopic_output_stub(). */ | |
ee890fe2 | 14797 | |
efdba735 SH |
14798 | static void |
14799 | macho_branch_islands (void) | |
14800 | { | |
14801 | char tmp_buf[512]; | |
14802 | tree branch_island; | |
14803 | ||
14804 | for (branch_island = branch_island_list; | |
14805 | branch_island; | |
14806 | branch_island = TREE_CHAIN (branch_island)) | |
14807 | { | |
14808 | const char *label = | |
14809 | IDENTIFIER_POINTER (BRANCH_ISLAND_LABEL_NAME (branch_island)); | |
14810 | const char *name = | |
14811 | darwin_strip_name_encoding ( | |
14812 | IDENTIFIER_POINTER (BRANCH_ISLAND_FUNCTION_NAME (branch_island))); | |
14813 | char name_buf[512]; | |
14814 | /* Cheap copy of the details from the Darwin ASM_OUTPUT_LABELREF(). */ | |
14815 | if (name[0] == '*' || name[0] == '&') | |
14816 | strcpy (name_buf, name+1); | |
14817 | else | |
14818 | { | |
14819 | name_buf[0] = '_'; | |
14820 | strcpy (name_buf+1, name); | |
14821 | } | |
14822 | strcpy (tmp_buf, "\n"); | |
14823 | strcat (tmp_buf, label); | |
ee890fe2 | 14824 | #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO) |
efdba735 | 14825 | if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG) |
f7efd730 | 14826 | fprintf (asm_out_file, "\t.stabd 68,0," HOST_WIDE_INT_PRINT_UNSIGNED "\n", |
efdba735 | 14827 | BRANCH_ISLAND_LINE_NUMBER(branch_island)); |
ee890fe2 | 14828 | #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */ |
efdba735 SH |
14829 | if (flag_pic) |
14830 | { | |
14831 | strcat (tmp_buf, ":\n\tmflr r0\n\tbcl 20,31,"); | |
14832 | strcat (tmp_buf, label); | |
14833 | strcat (tmp_buf, "_pic\n"); | |
14834 | strcat (tmp_buf, label); | |
14835 | strcat (tmp_buf, "_pic:\n\tmflr r11\n"); | |
14836 | ||
14837 | strcat (tmp_buf, "\taddis r11,r11,ha16("); | |
14838 | strcat (tmp_buf, name_buf); | |
14839 | strcat (tmp_buf, " - "); | |
14840 | strcat (tmp_buf, label); | |
14841 | strcat (tmp_buf, "_pic)\n"); | |
14842 | ||
14843 | strcat (tmp_buf, "\tmtlr r0\n"); | |
14844 | ||
14845 | strcat (tmp_buf, "\taddi r12,r11,lo16("); | |
14846 | strcat (tmp_buf, name_buf); | |
14847 | strcat (tmp_buf, " - "); | |
14848 | strcat (tmp_buf, label); | |
14849 | strcat (tmp_buf, "_pic)\n"); | |
14850 | ||
14851 | strcat (tmp_buf, "\tmtctr r12\n\tbctr\n"); | |
14852 | } | |
14853 | else | |
14854 | { | |
14855 | strcat (tmp_buf, ":\nlis r12,hi16("); | |
14856 | strcat (tmp_buf, name_buf); | |
14857 | strcat (tmp_buf, ")\n\tori r12,r12,lo16("); | |
14858 | strcat (tmp_buf, name_buf); | |
14859 | strcat (tmp_buf, ")\n\tmtctr r12\n\tbctr"); | |
14860 | } | |
14861 | output_asm_insn (tmp_buf, 0); | |
ee890fe2 | 14862 | #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO) |
efdba735 | 14863 | if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG) |
f7efd730 | 14864 | fprintf(asm_out_file, "\t.stabd 68,0," HOST_WIDE_INT_PRINT_UNSIGNED "\n", |
efdba735 | 14865 | BRANCH_ISLAND_LINE_NUMBER (branch_island)); |
ee890fe2 | 14866 | #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */ |
efdba735 | 14867 | } |
ee890fe2 | 14868 | |
efdba735 | 14869 | branch_island_list = 0; |
ee890fe2 SS |
14870 | } |
14871 | ||
14872 | /* NO_PREVIOUS_DEF checks in the link list whether the function name is | |
14873 | already there or not. */ | |
14874 | ||
efdba735 | 14875 | static int |
a2369ed3 | 14876 | no_previous_def (tree function_name) |
ee890fe2 | 14877 | { |
efdba735 SH |
14878 | tree branch_island; |
14879 | for (branch_island = branch_island_list; | |
14880 | branch_island; | |
14881 | branch_island = TREE_CHAIN (branch_island)) | |
14882 | if (function_name == BRANCH_ISLAND_FUNCTION_NAME (branch_island)) | |
ee890fe2 SS |
14883 | return 0; |
14884 | return 1; | |
14885 | } | |
14886 | ||
14887 | /* GET_PREV_LABEL gets the label name from the previous definition of | |
14888 | the function. */ | |
14889 | ||
efdba735 | 14890 | static tree |
a2369ed3 | 14891 | get_prev_label (tree function_name) |
ee890fe2 | 14892 | { |
efdba735 SH |
14893 | tree branch_island; |
14894 | for (branch_island = branch_island_list; | |
14895 | branch_island; | |
14896 | branch_island = TREE_CHAIN (branch_island)) | |
14897 | if (function_name == BRANCH_ISLAND_FUNCTION_NAME (branch_island)) | |
14898 | return BRANCH_ISLAND_LABEL_NAME (branch_island); | |
ee890fe2 SS |
14899 | return 0; |
14900 | } | |
14901 | ||
14902 | /* INSN is either a function call or a millicode call. It may have an | |
14903 | unconditional jump in its delay slot. | |
14904 | ||
14905 | CALL_DEST is the routine we are calling. */ | |
14906 | ||
14907 | char * | |
efdba735 | 14908 | output_call (rtx insn, rtx *operands, int dest_operand_number, int cookie_operand_number) |
ee890fe2 SS |
14909 | { |
14910 | static char buf[256]; | |
efdba735 SH |
14911 | if (GET_CODE (operands[dest_operand_number]) == SYMBOL_REF |
14912 | && (INTVAL (operands[cookie_operand_number]) & CALL_LONG)) | |
ee890fe2 SS |
14913 | { |
14914 | tree labelname; | |
efdba735 | 14915 | tree funname = get_identifier (XSTR (operands[dest_operand_number], 0)); |
ee890fe2 SS |
14916 | |
14917 | if (no_previous_def (funname)) | |
14918 | { | |
308c142a | 14919 | int line_number = 0; |
ee890fe2 SS |
14920 | rtx label_rtx = gen_label_rtx (); |
14921 | char *label_buf, temp_buf[256]; | |
14922 | ASM_GENERATE_INTERNAL_LABEL (temp_buf, "L", | |
14923 | CODE_LABEL_NUMBER (label_rtx)); | |
14924 | label_buf = temp_buf[0] == '*' ? temp_buf + 1 : temp_buf; | |
14925 | labelname = get_identifier (label_buf); | |
14926 | for (; insn && GET_CODE (insn) != NOTE; insn = PREV_INSN (insn)); | |
14927 | if (insn) | |
14928 | line_number = NOTE_LINE_NUMBER (insn); | |
efdba735 | 14929 | add_compiler_branch_island (labelname, funname, line_number); |
ee890fe2 SS |
14930 | } |
14931 | else | |
14932 | labelname = get_prev_label (funname); | |
14933 | ||
efdba735 SH |
14934 | /* "jbsr foo, L42" is Mach-O for "Link as 'bl foo' if a 'bl' |
14935 | instruction will reach 'foo', otherwise link as 'bl L42'". | |
14936 | "L42" should be a 'branch island', that will do a far jump to | |
14937 | 'foo'. Branch islands are generated in | |
14938 | macho_branch_islands(). */ | |
ee890fe2 | 14939 | sprintf (buf, "jbsr %%z%d,%.246s", |
efdba735 | 14940 | dest_operand_number, IDENTIFIER_POINTER (labelname)); |
ee890fe2 SS |
14941 | } |
14942 | else | |
efdba735 SH |
14943 | sprintf (buf, "bl %%z%d", dest_operand_number); |
14944 | return buf; | |
ee890fe2 SS |
14945 | } |
14946 | ||
efdba735 | 14947 | #endif /* TARGET_MACHO */ |
ee890fe2 | 14948 | |
ee890fe2 SS |
14949 | /* Generate PIC and indirect symbol stubs. */ |
14950 | ||
14951 | void | |
a2369ed3 | 14952 | machopic_output_stub (FILE *file, const char *symb, const char *stub) |
ee890fe2 SS |
14953 | { |
14954 | unsigned int length; | |
a4f6c312 SS |
14955 | char *symbol_name, *lazy_ptr_name; |
14956 | char *local_label_0; | |
ee890fe2 SS |
14957 | static int label = 0; |
14958 | ||
df56a27f | 14959 | /* Lose our funky encoding stuff so it doesn't contaminate the stub. */ |
772c5265 | 14960 | symb = (*targetm.strip_name_encoding) (symb); |
df56a27f | 14961 | |
ee890fe2 | 14962 | |
ee890fe2 SS |
14963 | length = strlen (symb); |
14964 | symbol_name = alloca (length + 32); | |
14965 | GEN_SYMBOL_NAME_FOR_SYMBOL (symbol_name, symb, length); | |
14966 | ||
14967 | lazy_ptr_name = alloca (length + 32); | |
14968 | GEN_LAZY_PTR_NAME_FOR_SYMBOL (lazy_ptr_name, symb, length); | |
14969 | ||
ee890fe2 | 14970 | if (flag_pic == 2) |
d3c300d2 | 14971 | machopic_picsymbol_stub1_section (); |
ee890fe2 | 14972 | else |
d3c300d2 DJ |
14973 | machopic_symbol_stub1_section (); |
14974 | fprintf (file, "\t.align 2\n"); | |
ee890fe2 SS |
14975 | |
14976 | fprintf (file, "%s:\n", stub); | |
14977 | fprintf (file, "\t.indirect_symbol %s\n", symbol_name); | |
14978 | ||
14979 | if (flag_pic == 2) | |
14980 | { | |
876455fa AP |
14981 | label++; |
14982 | local_label_0 = alloca (sizeof("\"L0000000000$spb\"")); | |
14983 | sprintf (local_label_0, "\"L%011d$spb\"", label); | |
14984 | ||
ee890fe2 SS |
14985 | fprintf (file, "\tmflr r0\n"); |
14986 | fprintf (file, "\tbcl 20,31,%s\n", local_label_0); | |
14987 | fprintf (file, "%s:\n\tmflr r11\n", local_label_0); | |
14988 | fprintf (file, "\taddis r11,r11,ha16(%s-%s)\n", | |
14989 | lazy_ptr_name, local_label_0); | |
14990 | fprintf (file, "\tmtlr r0\n"); | |
d3c300d2 | 14991 | fprintf (file, "\tlwzu r12,lo16(%s-%s)(r11)\n", |
ee890fe2 SS |
14992 | lazy_ptr_name, local_label_0); |
14993 | fprintf (file, "\tmtctr r12\n"); | |
ee890fe2 SS |
14994 | fprintf (file, "\tbctr\n"); |
14995 | } | |
14996 | else | |
ab82a49f AP |
14997 | { |
14998 | fprintf (file, "\tlis r11,ha16(%s)\n", lazy_ptr_name); | |
14999 | fprintf (file, "\tlwzu r12,lo16(%s)(r11)\n", lazy_ptr_name); | |
15000 | fprintf (file, "\tmtctr r12\n"); | |
15001 | fprintf (file, "\tbctr\n"); | |
15002 | } | |
ee890fe2 SS |
15003 | |
15004 | machopic_lazy_symbol_ptr_section (); | |
15005 | fprintf (file, "%s:\n", lazy_ptr_name); | |
15006 | fprintf (file, "\t.indirect_symbol %s\n", symbol_name); | |
15007 | fprintf (file, "\t.long dyld_stub_binding_helper\n"); | |
15008 | } | |
15009 | ||
15010 | /* Legitimize PIC addresses. If the address is already | |
15011 | position-independent, we return ORIG. Newly generated | |
15012 | position-independent addresses go into a reg. This is REG if non | |
15013 | zero, otherwise we allocate register(s) as necessary. */ | |
15014 | ||
c859cda6 | 15015 | #define SMALL_INT(X) ((unsigned) (INTVAL(X) + 0x8000) < 0x10000) |
ee890fe2 SS |
15016 | |
15017 | rtx | |
a2369ed3 DJ |
15018 | rs6000_machopic_legitimize_pic_address (rtx orig, enum machine_mode mode, |
15019 | rtx reg) | |
ee890fe2 SS |
15020 | { |
15021 | rtx base, offset; | |
15022 | ||
15023 | if (reg == NULL && ! reload_in_progress && ! reload_completed) | |
15024 | reg = gen_reg_rtx (Pmode); | |
15025 | ||
15026 | if (GET_CODE (orig) == CONST) | |
15027 | { | |
15028 | if (GET_CODE (XEXP (orig, 0)) == PLUS | |
15029 | && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx) | |
15030 | return orig; | |
15031 | ||
15032 | if (GET_CODE (XEXP (orig, 0)) == PLUS) | |
15033 | { | |
2cf520bf | 15034 | /* Use a different reg for the intermediate value, as |
a3c9585f | 15035 | it will be marked UNCHANGING. */ |
2cf520bf GK |
15036 | rtx reg_temp = no_new_pseudos ? reg : gen_reg_rtx (Pmode); |
15037 | ||
a4f6c312 SS |
15038 | base = |
15039 | rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 0), | |
2cf520bf | 15040 | Pmode, reg_temp); |
a4f6c312 SS |
15041 | offset = |
15042 | rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 1), | |
15043 | Pmode, reg); | |
ee890fe2 SS |
15044 | } |
15045 | else | |
15046 | abort (); | |
15047 | ||
15048 | if (GET_CODE (offset) == CONST_INT) | |
15049 | { | |
15050 | if (SMALL_INT (offset)) | |
ed8908e7 | 15051 | return plus_constant (base, INTVAL (offset)); |
ee890fe2 SS |
15052 | else if (! reload_in_progress && ! reload_completed) |
15053 | offset = force_reg (Pmode, offset); | |
15054 | else | |
c859cda6 DJ |
15055 | { |
15056 | rtx mem = force_const_mem (Pmode, orig); | |
15057 | return machopic_legitimize_pic_address (mem, Pmode, reg); | |
15058 | } | |
ee890fe2 | 15059 | } |
f1c25d3b | 15060 | return gen_rtx_PLUS (Pmode, base, offset); |
ee890fe2 SS |
15061 | } |
15062 | ||
15063 | /* Fall back on generic machopic code. */ | |
15064 | return machopic_legitimize_pic_address (orig, mode, reg); | |
15065 | } | |
15066 | ||
15067 | /* This is just a placeholder to make linking work without having to | |
15068 | add this to the generic Darwin EXTRA_SECTIONS. If -mcall-aix is | |
15069 | ever needed for Darwin (not too likely!) this would have to get a | |
15070 | real definition. */ | |
15071 | ||
15072 | void | |
863d938c | 15073 | toc_section (void) |
ee890fe2 SS |
15074 | { |
15075 | } | |
15076 | ||
15077 | #endif /* TARGET_MACHO */ | |
7c262518 RH |
15078 | |
15079 | #if TARGET_ELF | |
15080 | static unsigned int | |
a2369ed3 | 15081 | rs6000_elf_section_type_flags (tree decl, const char *name, int reloc) |
7c262518 | 15082 | { |
1ff8f81a AM |
15083 | return default_section_type_flags_1 (decl, name, reloc, |
15084 | flag_pic || DEFAULT_ABI == ABI_AIX); | |
7c262518 | 15085 | } |
d9f6800d RH |
15086 | |
15087 | /* Record an element in the table of global constructors. SYMBOL is | |
15088 | a SYMBOL_REF of the function to be called; PRIORITY is a number | |
15089 | between 0 and MAX_INIT_PRIORITY. | |
15090 | ||
15091 | This differs from default_named_section_asm_out_constructor in | |
15092 | that we have special handling for -mrelocatable. */ | |
15093 | ||
15094 | static void | |
a2369ed3 | 15095 | rs6000_elf_asm_out_constructor (rtx symbol, int priority) |
d9f6800d RH |
15096 | { |
15097 | const char *section = ".ctors"; | |
15098 | char buf[16]; | |
15099 | ||
15100 | if (priority != DEFAULT_INIT_PRIORITY) | |
15101 | { | |
15102 | sprintf (buf, ".ctors.%.5u", | |
15103 | /* Invert the numbering so the linker puts us in the proper | |
15104 | order; constructors are run from right to left, and the | |
15105 | linker sorts in increasing order. */ | |
15106 | MAX_INIT_PRIORITY - priority); | |
15107 | section = buf; | |
15108 | } | |
15109 | ||
715bdd29 RH |
15110 | named_section_flags (section, SECTION_WRITE); |
15111 | assemble_align (POINTER_SIZE); | |
d9f6800d RH |
15112 | |
15113 | if (TARGET_RELOCATABLE) | |
15114 | { | |
15115 | fputs ("\t.long (", asm_out_file); | |
15116 | output_addr_const (asm_out_file, symbol); | |
15117 | fputs (")@fixup\n", asm_out_file); | |
15118 | } | |
15119 | else | |
c8af3574 | 15120 | assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1); |
d9f6800d RH |
15121 | } |
15122 | ||
15123 | static void | |
a2369ed3 | 15124 | rs6000_elf_asm_out_destructor (rtx symbol, int priority) |
d9f6800d RH |
15125 | { |
15126 | const char *section = ".dtors"; | |
15127 | char buf[16]; | |
15128 | ||
15129 | if (priority != DEFAULT_INIT_PRIORITY) | |
15130 | { | |
15131 | sprintf (buf, ".dtors.%.5u", | |
15132 | /* Invert the numbering so the linker puts us in the proper | |
15133 | order; constructors are run from right to left, and the | |
15134 | linker sorts in increasing order. */ | |
15135 | MAX_INIT_PRIORITY - priority); | |
15136 | section = buf; | |
15137 | } | |
15138 | ||
715bdd29 RH |
15139 | named_section_flags (section, SECTION_WRITE); |
15140 | assemble_align (POINTER_SIZE); | |
d9f6800d RH |
15141 | |
15142 | if (TARGET_RELOCATABLE) | |
15143 | { | |
15144 | fputs ("\t.long (", asm_out_file); | |
15145 | output_addr_const (asm_out_file, symbol); | |
15146 | fputs (")@fixup\n", asm_out_file); | |
15147 | } | |
15148 | else | |
c8af3574 | 15149 | assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1); |
d9f6800d | 15150 | } |
9739c90c JJ |
15151 | |
15152 | void | |
a2369ed3 | 15153 | rs6000_elf_declare_function_name (FILE *file, const char *name, tree decl) |
9739c90c JJ |
15154 | { |
15155 | if (TARGET_64BIT) | |
15156 | { | |
15157 | fputs ("\t.section\t\".opd\",\"aw\"\n\t.align 3\n", file); | |
15158 | ASM_OUTPUT_LABEL (file, name); | |
15159 | fputs (DOUBLE_INT_ASM_OP, file); | |
15160 | putc ('.', file); | |
15161 | assemble_name (file, name); | |
15162 | fputs (",.TOC.@tocbase,0\n\t.previous\n\t.size\t", file); | |
15163 | assemble_name (file, name); | |
15164 | fputs (",24\n\t.type\t.", file); | |
15165 | assemble_name (file, name); | |
15166 | fputs (",@function\n", file); | |
15167 | if (TREE_PUBLIC (decl) && ! DECL_WEAK (decl)) | |
15168 | { | |
15169 | fputs ("\t.globl\t.", file); | |
15170 | assemble_name (file, name); | |
15171 | putc ('\n', file); | |
15172 | } | |
15173 | ASM_DECLARE_RESULT (file, DECL_RESULT (decl)); | |
15174 | putc ('.', file); | |
15175 | ASM_OUTPUT_LABEL (file, name); | |
15176 | return; | |
15177 | } | |
15178 | ||
15179 | if (TARGET_RELOCATABLE | |
15180 | && (get_pool_size () != 0 || current_function_profile) | |
3c9eb5f4 | 15181 | && uses_TOC ()) |
9739c90c JJ |
15182 | { |
15183 | char buf[256]; | |
15184 | ||
15185 | (*targetm.asm_out.internal_label) (file, "LCL", rs6000_pic_labelno); | |
15186 | ||
15187 | ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1); | |
15188 | fprintf (file, "\t.long "); | |
15189 | assemble_name (file, buf); | |
15190 | putc ('-', file); | |
15191 | ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno); | |
15192 | assemble_name (file, buf); | |
15193 | putc ('\n', file); | |
15194 | } | |
15195 | ||
15196 | ASM_OUTPUT_TYPE_DIRECTIVE (file, name, "function"); | |
15197 | ASM_DECLARE_RESULT (file, DECL_RESULT (decl)); | |
15198 | ||
15199 | if (DEFAULT_ABI == ABI_AIX) | |
15200 | { | |
15201 | const char *desc_name, *orig_name; | |
15202 | ||
15203 | orig_name = (*targetm.strip_name_encoding) (name); | |
15204 | desc_name = orig_name; | |
15205 | while (*desc_name == '.') | |
15206 | desc_name++; | |
15207 | ||
15208 | if (TREE_PUBLIC (decl)) | |
15209 | fprintf (file, "\t.globl %s\n", desc_name); | |
15210 | ||
15211 | fprintf (file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP); | |
15212 | fprintf (file, "%s:\n", desc_name); | |
15213 | fprintf (file, "\t.long %s\n", orig_name); | |
15214 | fputs ("\t.long _GLOBAL_OFFSET_TABLE_\n", file); | |
15215 | if (DEFAULT_ABI == ABI_AIX) | |
15216 | fputs ("\t.long 0\n", file); | |
15217 | fprintf (file, "\t.previous\n"); | |
15218 | } | |
15219 | ASM_OUTPUT_LABEL (file, name); | |
15220 | } | |
7c262518 RH |
15221 | #endif |
15222 | ||
cbaaba19 | 15223 | #if TARGET_XCOFF |
7c262518 | 15224 | static void |
a2369ed3 | 15225 | rs6000_xcoff_asm_globalize_label (FILE *stream, const char *name) |
b275d088 DE |
15226 | { |
15227 | fputs (GLOBAL_ASM_OP, stream); | |
15228 | RS6000_OUTPUT_BASENAME (stream, name); | |
15229 | putc ('\n', stream); | |
15230 | } | |
15231 | ||
15232 | static void | |
a2369ed3 | 15233 | rs6000_xcoff_asm_named_section (const char *name, unsigned int flags) |
7c262518 | 15234 | { |
0e5dbd9b DE |
15235 | int smclass; |
15236 | static const char * const suffix[3] = { "PR", "RO", "RW" }; | |
15237 | ||
15238 | if (flags & SECTION_CODE) | |
15239 | smclass = 0; | |
15240 | else if (flags & SECTION_WRITE) | |
15241 | smclass = 2; | |
15242 | else | |
15243 | smclass = 1; | |
15244 | ||
5b5198f7 | 15245 | fprintf (asm_out_file, "\t.csect %s%s[%s],%u\n", |
0e5dbd9b | 15246 | (flags & SECTION_CODE) ? "." : "", |
5b5198f7 | 15247 | name, suffix[smclass], flags & SECTION_ENTSIZE); |
7c262518 | 15248 | } |
ae46c4e0 RH |
15249 | |
15250 | static void | |
a2369ed3 DJ |
15251 | rs6000_xcoff_select_section (tree decl, int reloc, |
15252 | unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED) | |
ae46c4e0 | 15253 | { |
5add3202 | 15254 | if (decl_readonly_section_1 (decl, reloc, 1)) |
ae46c4e0 | 15255 | { |
0e5dbd9b | 15256 | if (TREE_PUBLIC (decl)) |
ae46c4e0 RH |
15257 | read_only_data_section (); |
15258 | else | |
15259 | read_only_private_data_section (); | |
15260 | } | |
15261 | else | |
15262 | { | |
0e5dbd9b | 15263 | if (TREE_PUBLIC (decl)) |
ae46c4e0 RH |
15264 | data_section (); |
15265 | else | |
15266 | private_data_section (); | |
15267 | } | |
15268 | } | |
15269 | ||
15270 | static void | |
a2369ed3 | 15271 | rs6000_xcoff_unique_section (tree decl, int reloc ATTRIBUTE_UNUSED) |
ae46c4e0 RH |
15272 | { |
15273 | const char *name; | |
ae46c4e0 | 15274 | |
5b5198f7 DE |
15275 | /* Use select_section for private and uninitialized data. */ |
15276 | if (!TREE_PUBLIC (decl) | |
15277 | || DECL_COMMON (decl) | |
0e5dbd9b DE |
15278 | || DECL_INITIAL (decl) == NULL_TREE |
15279 | || DECL_INITIAL (decl) == error_mark_node | |
15280 | || (flag_zero_initialized_in_bss | |
15281 | && initializer_zerop (DECL_INITIAL (decl)))) | |
15282 | return; | |
15283 | ||
15284 | name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl)); | |
15285 | name = (*targetm.strip_name_encoding) (name); | |
15286 | DECL_SECTION_NAME (decl) = build_string (strlen (name), name); | |
ae46c4e0 | 15287 | } |
b64a1b53 | 15288 | |
fb49053f RH |
15289 | /* Select section for constant in constant pool. |
15290 | ||
15291 | On RS/6000, all constants are in the private read-only data area. | |
15292 | However, if this is being placed in the TOC it must be output as a | |
15293 | toc entry. */ | |
15294 | ||
b64a1b53 | 15295 | static void |
a2369ed3 DJ |
15296 | rs6000_xcoff_select_rtx_section (enum machine_mode mode, rtx x, |
15297 | unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED) | |
b64a1b53 RH |
15298 | { |
15299 | if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode)) | |
15300 | toc_section (); | |
15301 | else | |
15302 | read_only_private_data_section (); | |
15303 | } | |
772c5265 RH |
15304 | |
15305 | /* Remove any trailing [DS] or the like from the symbol name. */ | |
15306 | ||
15307 | static const char * | |
a2369ed3 | 15308 | rs6000_xcoff_strip_name_encoding (const char *name) |
772c5265 RH |
15309 | { |
15310 | size_t len; | |
15311 | if (*name == '*') | |
15312 | name++; | |
15313 | len = strlen (name); | |
15314 | if (name[len - 1] == ']') | |
15315 | return ggc_alloc_string (name, len - 4); | |
15316 | else | |
15317 | return name; | |
15318 | } | |
15319 | ||
5add3202 DE |
15320 | /* Section attributes. AIX is always PIC. */ |
15321 | ||
15322 | static unsigned int | |
a2369ed3 | 15323 | rs6000_xcoff_section_type_flags (tree decl, const char *name, int reloc) |
5add3202 | 15324 | { |
5b5198f7 DE |
15325 | unsigned int align; |
15326 | unsigned int flags = default_section_type_flags_1 (decl, name, reloc, 1); | |
15327 | ||
15328 | /* Align to at least UNIT size. */ | |
15329 | if (flags & SECTION_CODE) | |
15330 | align = MIN_UNITS_PER_WORD; | |
15331 | else | |
15332 | /* Increase alignment of large objects if not already stricter. */ | |
15333 | align = MAX ((DECL_ALIGN (decl) / BITS_PER_UNIT), | |
15334 | int_size_in_bytes (TREE_TYPE (decl)) > MIN_UNITS_PER_WORD | |
15335 | ? UNITS_PER_FP_WORD : MIN_UNITS_PER_WORD); | |
15336 | ||
15337 | return flags | (exact_log2 (align) & SECTION_ENTSIZE); | |
5add3202 | 15338 | } |
a5fe455b | 15339 | |
1bc7c5b6 ZW |
15340 | /* Output at beginning of assembler file. |
15341 | ||
15342 | Initialize the section names for the RS/6000 at this point. | |
15343 | ||
15344 | Specify filename, including full path, to assembler. | |
15345 | ||
15346 | We want to go into the TOC section so at least one .toc will be emitted. | |
15347 | Also, in order to output proper .bs/.es pairs, we need at least one static | |
15348 | [RW] section emitted. | |
15349 | ||
15350 | Finally, declare mcount when profiling to make the assembler happy. */ | |
15351 | ||
15352 | static void | |
863d938c | 15353 | rs6000_xcoff_file_start (void) |
1bc7c5b6 ZW |
15354 | { |
15355 | rs6000_gen_section_name (&xcoff_bss_section_name, | |
15356 | main_input_filename, ".bss_"); | |
15357 | rs6000_gen_section_name (&xcoff_private_data_section_name, | |
15358 | main_input_filename, ".rw_"); | |
15359 | rs6000_gen_section_name (&xcoff_read_only_section_name, | |
15360 | main_input_filename, ".ro_"); | |
15361 | ||
15362 | fputs ("\t.file\t", asm_out_file); | |
15363 | output_quoted_string (asm_out_file, main_input_filename); | |
15364 | fputc ('\n', asm_out_file); | |
15365 | toc_section (); | |
15366 | if (write_symbols != NO_DEBUG) | |
15367 | private_data_section (); | |
15368 | text_section (); | |
15369 | if (profile_flag) | |
15370 | fprintf (asm_out_file, "\t.extern %s\n", RS6000_MCOUNT); | |
15371 | rs6000_file_start (); | |
15372 | } | |
15373 | ||
a5fe455b ZW |
15374 | /* Output at end of assembler file. |
15375 | On the RS/6000, referencing data should automatically pull in text. */ | |
15376 | ||
15377 | static void | |
863d938c | 15378 | rs6000_xcoff_file_end (void) |
a5fe455b ZW |
15379 | { |
15380 | text_section (); | |
15381 | fputs ("_section_.text:\n", asm_out_file); | |
15382 | data_section (); | |
15383 | fputs (TARGET_32BIT | |
15384 | ? "\t.long _section_.text\n" : "\t.llong _section_.text\n", | |
15385 | asm_out_file); | |
15386 | } | |
f1384257 | 15387 | #endif /* TARGET_XCOFF */ |
0e5dbd9b | 15388 | |
f1384257 AM |
15389 | #if TARGET_MACHO |
15390 | /* Cross-module name binding. Darwin does not support overriding | |
7f3d8013 | 15391 | functions at dynamic-link time. */ |
0e5dbd9b | 15392 | |
2bcc50d0 | 15393 | static bool |
a2369ed3 | 15394 | rs6000_binds_local_p (tree decl) |
0e5dbd9b | 15395 | { |
f1384257 | 15396 | return default_binds_local_p_1 (decl, 0); |
0e5dbd9b | 15397 | } |
f1384257 | 15398 | #endif |
34bb030a | 15399 | |
3c50106f RH |
15400 | /* Compute a (partial) cost for rtx X. Return true if the complete |
15401 | cost has been computed, and false if subexpressions should be | |
15402 | scanned. In either case, *TOTAL contains the cost result. */ | |
15403 | ||
15404 | static bool | |
a2369ed3 DJ |
15405 | rs6000_rtx_costs (rtx x, int code, int outer_code ATTRIBUTE_UNUSED, |
15406 | int *total) | |
3c50106f RH |
15407 | { |
15408 | switch (code) | |
15409 | { | |
15410 | /* On the RS/6000, if it is valid in the insn, it is free. | |
15411 | So this always returns 0. */ | |
15412 | case CONST_INT: | |
15413 | case CONST: | |
15414 | case LABEL_REF: | |
15415 | case SYMBOL_REF: | |
15416 | case CONST_DOUBLE: | |
15417 | case HIGH: | |
15418 | *total = 0; | |
15419 | return true; | |
15420 | ||
15421 | case PLUS: | |
15422 | *total = ((GET_CODE (XEXP (x, 1)) == CONST_INT | |
15423 | && ((unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 1)) | |
15424 | + 0x8000) >= 0x10000) | |
15425 | && ((INTVAL (XEXP (x, 1)) & 0xffff) != 0)) | |
15426 | ? COSTS_N_INSNS (2) | |
15427 | : COSTS_N_INSNS (1)); | |
15428 | return true; | |
15429 | ||
15430 | case AND: | |
15431 | case IOR: | |
15432 | case XOR: | |
15433 | *total = ((GET_CODE (XEXP (x, 1)) == CONST_INT | |
15434 | && (INTVAL (XEXP (x, 1)) & (~ (HOST_WIDE_INT) 0xffff)) != 0 | |
15435 | && ((INTVAL (XEXP (x, 1)) & 0xffff) != 0)) | |
15436 | ? COSTS_N_INSNS (2) | |
15437 | : COSTS_N_INSNS (1)); | |
15438 | return true; | |
15439 | ||
15440 | case MULT: | |
15441 | if (optimize_size) | |
15442 | { | |
15443 | *total = COSTS_N_INSNS (2); | |
15444 | return true; | |
15445 | } | |
15446 | switch (rs6000_cpu) | |
15447 | { | |
15448 | case PROCESSOR_RIOS1: | |
15449 | case PROCESSOR_PPC405: | |
15450 | *total = (GET_CODE (XEXP (x, 1)) != CONST_INT | |
15451 | ? COSTS_N_INSNS (5) | |
15452 | : (INTVAL (XEXP (x, 1)) >= -256 | |
15453 | && INTVAL (XEXP (x, 1)) <= 255) | |
15454 | ? COSTS_N_INSNS (3) : COSTS_N_INSNS (4)); | |
15455 | return true; | |
15456 | ||
02ca7595 DE |
15457 | case PROCESSOR_PPC440: |
15458 | *total = (GET_CODE (XEXP (x, 1)) != CONST_INT | |
15459 | ? COSTS_N_INSNS (3) | |
15460 | : COSTS_N_INSNS (2)); | |
15461 | return true; | |
15462 | ||
3c50106f RH |
15463 | case PROCESSOR_RS64A: |
15464 | *total = (GET_CODE (XEXP (x, 1)) != CONST_INT | |
15465 | ? GET_MODE (XEXP (x, 1)) != DImode | |
15466 | ? COSTS_N_INSNS (20) : COSTS_N_INSNS (34) | |
15467 | : (INTVAL (XEXP (x, 1)) >= -256 | |
15468 | && INTVAL (XEXP (x, 1)) <= 255) | |
15469 | ? COSTS_N_INSNS (8) : COSTS_N_INSNS (12)); | |
15470 | return true; | |
15471 | ||
15472 | case PROCESSOR_RIOS2: | |
15473 | case PROCESSOR_MPCCORE: | |
15474 | case PROCESSOR_PPC604e: | |
15475 | *total = COSTS_N_INSNS (2); | |
15476 | return true; | |
15477 | ||
15478 | case PROCESSOR_PPC601: | |
15479 | *total = COSTS_N_INSNS (5); | |
15480 | return true; | |
15481 | ||
15482 | case PROCESSOR_PPC603: | |
15483 | case PROCESSOR_PPC7400: | |
15484 | case PROCESSOR_PPC750: | |
15485 | *total = (GET_CODE (XEXP (x, 1)) != CONST_INT | |
15486 | ? COSTS_N_INSNS (5) | |
15487 | : (INTVAL (XEXP (x, 1)) >= -256 | |
15488 | && INTVAL (XEXP (x, 1)) <= 255) | |
15489 | ? COSTS_N_INSNS (2) : COSTS_N_INSNS (3)); | |
15490 | return true; | |
15491 | ||
15492 | case PROCESSOR_PPC7450: | |
15493 | *total = (GET_CODE (XEXP (x, 1)) != CONST_INT | |
15494 | ? COSTS_N_INSNS (4) | |
15495 | : COSTS_N_INSNS (3)); | |
15496 | return true; | |
15497 | ||
15498 | case PROCESSOR_PPC403: | |
15499 | case PROCESSOR_PPC604: | |
15500 | case PROCESSOR_PPC8540: | |
15501 | *total = COSTS_N_INSNS (4); | |
15502 | return true; | |
15503 | ||
15504 | case PROCESSOR_PPC620: | |
15505 | case PROCESSOR_PPC630: | |
3c50106f RH |
15506 | *total = (GET_CODE (XEXP (x, 1)) != CONST_INT |
15507 | ? GET_MODE (XEXP (x, 1)) != DImode | |
15508 | ? COSTS_N_INSNS (5) : COSTS_N_INSNS (7) | |
15509 | : (INTVAL (XEXP (x, 1)) >= -256 | |
15510 | && INTVAL (XEXP (x, 1)) <= 255) | |
15511 | ? COSTS_N_INSNS (3) : COSTS_N_INSNS (4)); | |
15512 | return true; | |
15513 | ||
9259f3b0 DE |
15514 | case PROCESSOR_POWER4: |
15515 | *total = (GET_CODE (XEXP (x, 1)) != CONST_INT | |
15516 | ? GET_MODE (XEXP (x, 1)) != DImode | |
984e25ac DE |
15517 | ? COSTS_N_INSNS (3) : COSTS_N_INSNS (4) |
15518 | : COSTS_N_INSNS (2)); | |
9259f3b0 DE |
15519 | return true; |
15520 | ||
3c50106f RH |
15521 | default: |
15522 | abort (); | |
15523 | } | |
15524 | ||
15525 | case DIV: | |
15526 | case MOD: | |
15527 | if (GET_CODE (XEXP (x, 1)) == CONST_INT | |
15528 | && exact_log2 (INTVAL (XEXP (x, 1))) >= 0) | |
15529 | { | |
15530 | *total = COSTS_N_INSNS (2); | |
15531 | return true; | |
15532 | } | |
5efb1046 | 15533 | /* FALLTHRU */ |
3c50106f RH |
15534 | |
15535 | case UDIV: | |
15536 | case UMOD: | |
15537 | switch (rs6000_cpu) | |
15538 | { | |
15539 | case PROCESSOR_RIOS1: | |
15540 | *total = COSTS_N_INSNS (19); | |
15541 | return true; | |
15542 | ||
15543 | case PROCESSOR_RIOS2: | |
15544 | *total = COSTS_N_INSNS (13); | |
15545 | return true; | |
15546 | ||
15547 | case PROCESSOR_RS64A: | |
15548 | *total = (GET_MODE (XEXP (x, 1)) != DImode | |
15549 | ? COSTS_N_INSNS (65) | |
15550 | : COSTS_N_INSNS (67)); | |
15551 | return true; | |
15552 | ||
15553 | case PROCESSOR_MPCCORE: | |
15554 | *total = COSTS_N_INSNS (6); | |
15555 | return true; | |
15556 | ||
15557 | case PROCESSOR_PPC403: | |
15558 | *total = COSTS_N_INSNS (33); | |
15559 | return true; | |
15560 | ||
15561 | case PROCESSOR_PPC405: | |
15562 | *total = COSTS_N_INSNS (35); | |
15563 | return true; | |
15564 | ||
02ca7595 DE |
15565 | case PROCESSOR_PPC440: |
15566 | *total = COSTS_N_INSNS (34); | |
15567 | return true; | |
15568 | ||
3c50106f RH |
15569 | case PROCESSOR_PPC601: |
15570 | *total = COSTS_N_INSNS (36); | |
15571 | return true; | |
15572 | ||
15573 | case PROCESSOR_PPC603: | |
15574 | *total = COSTS_N_INSNS (37); | |
15575 | return true; | |
15576 | ||
15577 | case PROCESSOR_PPC604: | |
15578 | case PROCESSOR_PPC604e: | |
15579 | *total = COSTS_N_INSNS (20); | |
15580 | return true; | |
15581 | ||
15582 | case PROCESSOR_PPC620: | |
15583 | case PROCESSOR_PPC630: | |
3c50106f RH |
15584 | *total = (GET_MODE (XEXP (x, 1)) != DImode |
15585 | ? COSTS_N_INSNS (21) | |
15586 | : COSTS_N_INSNS (37)); | |
15587 | return true; | |
15588 | ||
15589 | case PROCESSOR_PPC750: | |
15590 | case PROCESSOR_PPC8540: | |
15591 | case PROCESSOR_PPC7400: | |
15592 | *total = COSTS_N_INSNS (19); | |
15593 | return true; | |
15594 | ||
15595 | case PROCESSOR_PPC7450: | |
15596 | *total = COSTS_N_INSNS (23); | |
15597 | return true; | |
984e25ac DE |
15598 | |
15599 | case PROCESSOR_POWER4: | |
15600 | *total = (GET_MODE (XEXP (x, 1)) != DImode | |
15601 | ? COSTS_N_INSNS (18) | |
15602 | : COSTS_N_INSNS (34)); | |
15603 | return true; | |
3c50106f RH |
15604 | |
15605 | default: | |
15606 | abort (); | |
15607 | } | |
15608 | ||
15609 | case FFS: | |
15610 | *total = COSTS_N_INSNS (4); | |
15611 | return true; | |
15612 | ||
15613 | case MEM: | |
a3c9585f | 15614 | /* MEM should be slightly more expensive than (plus (reg) (const)). */ |
3c50106f RH |
15615 | *total = 5; |
15616 | return true; | |
15617 | ||
15618 | default: | |
15619 | return false; | |
15620 | } | |
15621 | } | |
15622 | ||
34bb030a DE |
15623 | /* A C expression returning the cost of moving data from a register of class |
15624 | CLASS1 to one of CLASS2. */ | |
15625 | ||
15626 | int | |
a2369ed3 DJ |
15627 | rs6000_register_move_cost (enum machine_mode mode, |
15628 | enum reg_class from, enum reg_class to) | |
34bb030a DE |
15629 | { |
15630 | /* Moves from/to GENERAL_REGS. */ | |
15631 | if (reg_classes_intersect_p (to, GENERAL_REGS) | |
15632 | || reg_classes_intersect_p (from, GENERAL_REGS)) | |
15633 | { | |
15634 | if (! reg_classes_intersect_p (to, GENERAL_REGS)) | |
15635 | from = to; | |
15636 | ||
15637 | if (from == FLOAT_REGS || from == ALTIVEC_REGS) | |
15638 | return (rs6000_memory_move_cost (mode, from, 0) | |
15639 | + rs6000_memory_move_cost (mode, GENERAL_REGS, 0)); | |
15640 | ||
a3c9585f | 15641 | /* It's more expensive to move CR_REGS than CR0_REGS because of the shift.... */ |
34bb030a DE |
15642 | else if (from == CR_REGS) |
15643 | return 4; | |
15644 | ||
15645 | else | |
15646 | /* A move will cost one instruction per GPR moved. */ | |
15647 | return 2 * HARD_REGNO_NREGS (0, mode); | |
15648 | } | |
15649 | ||
15650 | /* Moving between two similar registers is just one instruction. */ | |
15651 | else if (reg_classes_intersect_p (to, from)) | |
15652 | return mode == TFmode ? 4 : 2; | |
15653 | ||
15654 | /* Everything else has to go through GENERAL_REGS. */ | |
15655 | else | |
15656 | return (rs6000_register_move_cost (mode, GENERAL_REGS, to) | |
15657 | + rs6000_register_move_cost (mode, from, GENERAL_REGS)); | |
15658 | } | |
15659 | ||
15660 | /* A C expressions returning the cost of moving data of MODE from a register to | |
15661 | or from memory. */ | |
15662 | ||
15663 | int | |
a2369ed3 DJ |
15664 | rs6000_memory_move_cost (enum machine_mode mode, enum reg_class class, |
15665 | int in ATTRIBUTE_UNUSED) | |
34bb030a DE |
15666 | { |
15667 | if (reg_classes_intersect_p (class, GENERAL_REGS)) | |
15668 | return 4 * HARD_REGNO_NREGS (0, mode); | |
15669 | else if (reg_classes_intersect_p (class, FLOAT_REGS)) | |
15670 | return 4 * HARD_REGNO_NREGS (32, mode); | |
15671 | else if (reg_classes_intersect_p (class, ALTIVEC_REGS)) | |
15672 | return 4 * HARD_REGNO_NREGS (FIRST_ALTIVEC_REGNO, mode); | |
15673 | else | |
15674 | return 4 + rs6000_register_move_cost (mode, class, GENERAL_REGS); | |
15675 | } | |
15676 | ||
ded9bf77 AH |
15677 | /* Return an RTX representing where to find the function value of a |
15678 | function returning MODE. */ | |
15679 | static rtx | |
15680 | rs6000_complex_function_value (enum machine_mode mode) | |
15681 | { | |
15682 | unsigned int regno; | |
15683 | rtx r1, r2; | |
15684 | enum machine_mode inner = GET_MODE_INNER (mode); | |
fb7e4164 | 15685 | unsigned int inner_bytes = GET_MODE_SIZE (inner); |
ded9bf77 AH |
15686 | |
15687 | if (FLOAT_MODE_P (mode)) | |
15688 | regno = FP_ARG_RETURN; | |
15689 | else | |
15690 | { | |
15691 | regno = GP_ARG_RETURN; | |
15692 | ||
15693 | /* 32-bit is OK since it'll go in r3/r4. */ | |
fb7e4164 | 15694 | if (TARGET_32BIT && inner_bytes >= 4) |
ded9bf77 AH |
15695 | return gen_rtx_REG (mode, regno); |
15696 | } | |
15697 | ||
fb7e4164 AM |
15698 | if (inner_bytes >= 8) |
15699 | return gen_rtx_REG (mode, regno); | |
15700 | ||
ded9bf77 AH |
15701 | r1 = gen_rtx_EXPR_LIST (inner, gen_rtx_REG (inner, regno), |
15702 | const0_rtx); | |
15703 | r2 = gen_rtx_EXPR_LIST (inner, gen_rtx_REG (inner, regno + 1), | |
fb7e4164 | 15704 | GEN_INT (inner_bytes)); |
ded9bf77 AH |
15705 | return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r2)); |
15706 | } | |
15707 | ||
a6ebc39a AH |
15708 | /* Define how to find the value returned by a function. |
15709 | VALTYPE is the data type of the value (as a tree). | |
15710 | If the precise function being called is known, FUNC is its FUNCTION_DECL; | |
15711 | otherwise, FUNC is 0. | |
15712 | ||
15713 | On the SPE, both FPs and vectors are returned in r3. | |
15714 | ||
15715 | On RS/6000 an integer value is in r3 and a floating-point value is in | |
15716 | fp1, unless -msoft-float. */ | |
15717 | ||
15718 | rtx | |
15719 | rs6000_function_value (tree valtype, tree func ATTRIBUTE_UNUSED) | |
15720 | { | |
15721 | enum machine_mode mode; | |
2a8fa26c | 15722 | unsigned int regno; |
a6ebc39a | 15723 | |
0e67400a FJ |
15724 | if (TARGET_32BIT && TARGET_POWERPC64 && TYPE_MODE (valtype) == DImode) |
15725 | { | |
15726 | /* Long long return value need be split in -mpowerpc64, 32bit ABI. */ | |
15727 | return gen_rtx_PARALLEL (DImode, | |
15728 | gen_rtvec (2, | |
15729 | gen_rtx_EXPR_LIST (VOIDmode, | |
15730 | gen_rtx_REG (SImode, GP_ARG_RETURN), | |
15731 | const0_rtx), | |
15732 | gen_rtx_EXPR_LIST (VOIDmode, | |
15733 | gen_rtx_REG (SImode, | |
15734 | GP_ARG_RETURN + 1), | |
15735 | GEN_INT (4)))); | |
15736 | } | |
15737 | ||
a6ebc39a AH |
15738 | if ((INTEGRAL_TYPE_P (valtype) |
15739 | && TYPE_PRECISION (valtype) < BITS_PER_WORD) | |
15740 | || POINTER_TYPE_P (valtype)) | |
b78d48dd | 15741 | mode = TARGET_32BIT ? SImode : DImode; |
a6ebc39a AH |
15742 | else |
15743 | mode = TYPE_MODE (valtype); | |
15744 | ||
2a8fa26c DE |
15745 | if (TREE_CODE (valtype) == REAL_TYPE && TARGET_HARD_FLOAT && TARGET_FPRS) |
15746 | regno = FP_ARG_RETURN; | |
ded9bf77 AH |
15747 | else if (TREE_CODE (valtype) == COMPLEX_TYPE |
15748 | && TARGET_HARD_FLOAT | |
15749 | && SPLIT_COMPLEX_ARGS) | |
15750 | return rs6000_complex_function_value (mode); | |
2a8fa26c | 15751 | else if (TREE_CODE (valtype) == VECTOR_TYPE && TARGET_ALTIVEC) |
a6ebc39a AH |
15752 | regno = ALTIVEC_ARG_RETURN; |
15753 | else | |
15754 | regno = GP_ARG_RETURN; | |
15755 | ||
15756 | return gen_rtx_REG (mode, regno); | |
15757 | } | |
15758 | ||
ded9bf77 AH |
15759 | /* Define how to find the value returned by a library function |
15760 | assuming the value has mode MODE. */ | |
15761 | rtx | |
15762 | rs6000_libcall_value (enum machine_mode mode) | |
15763 | { | |
15764 | unsigned int regno; | |
15765 | ||
15766 | if (GET_MODE_CLASS (mode) == MODE_FLOAT | |
15767 | && TARGET_HARD_FLOAT && TARGET_FPRS) | |
15768 | regno = FP_ARG_RETURN; | |
15769 | else if (ALTIVEC_VECTOR_MODE (mode)) | |
15770 | regno = ALTIVEC_ARG_RETURN; | |
15771 | else if (COMPLEX_MODE_P (mode) && SPLIT_COMPLEX_ARGS) | |
15772 | return rs6000_complex_function_value (mode); | |
15773 | else | |
15774 | regno = GP_ARG_RETURN; | |
15775 | ||
15776 | return gen_rtx_REG (mode, regno); | |
15777 | } | |
15778 | ||
d1d0c603 JJ |
15779 | /* Define the offset between two registers, FROM to be eliminated and its |
15780 | replacement TO, at the start of a routine. */ | |
15781 | HOST_WIDE_INT | |
15782 | rs6000_initial_elimination_offset (int from, int to) | |
15783 | { | |
15784 | rs6000_stack_t *info = rs6000_stack_info (); | |
15785 | HOST_WIDE_INT offset; | |
15786 | ||
15787 | if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM) | |
15788 | offset = info->push_p ? 0 : -info->total_size; | |
15789 | else if (from == ARG_POINTER_REGNUM && to == FRAME_POINTER_REGNUM) | |
15790 | offset = info->total_size; | |
15791 | else if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM) | |
15792 | offset = info->push_p ? info->total_size : 0; | |
15793 | else if (from == RS6000_PIC_OFFSET_TABLE_REGNUM) | |
15794 | offset = 0; | |
15795 | else | |
15796 | abort (); | |
15797 | ||
15798 | return offset; | |
15799 | } | |
15800 | ||
62e1dfcf NC |
15801 | /* Return true if TYPE is of type __ev64_opaque__. */ |
15802 | ||
c8e4f0e9 | 15803 | static bool |
a2369ed3 | 15804 | is_ev64_opaque_type (tree type) |
62e1dfcf | 15805 | { |
c8e4f0e9 | 15806 | return (TARGET_SPE |
2abe3e28 AH |
15807 | && (type == opaque_V2SI_type_node |
15808 | || type == opaque_V2SF_type_node | |
36252949 | 15809 | || type == opaque_p_V2SI_type_node)); |
62e1dfcf NC |
15810 | } |
15811 | ||
96714395 | 15812 | static rtx |
a2369ed3 | 15813 | rs6000_dwarf_register_span (rtx reg) |
96714395 AH |
15814 | { |
15815 | unsigned regno; | |
15816 | ||
15817 | if (!TARGET_SPE || !SPE_VECTOR_MODE (GET_MODE (reg))) | |
15818 | return NULL_RTX; | |
15819 | ||
15820 | regno = REGNO (reg); | |
15821 | ||
15822 | /* The duality of the SPE register size wreaks all kinds of havoc. | |
15823 | This is a way of distinguishing r0 in 32-bits from r0 in | |
15824 | 64-bits. */ | |
15825 | return | |
15826 | gen_rtx_PARALLEL (VOIDmode, | |
3bd104d1 AH |
15827 | BYTES_BIG_ENDIAN |
15828 | ? gen_rtvec (2, | |
15829 | gen_rtx_REG (SImode, regno + 1200), | |
15830 | gen_rtx_REG (SImode, regno)) | |
15831 | : gen_rtvec (2, | |
15832 | gen_rtx_REG (SImode, regno), | |
15833 | gen_rtx_REG (SImode, regno + 1200))); | |
96714395 AH |
15834 | } |
15835 | ||
93c9d1ba AM |
15836 | /* Map internal gcc register numbers to DWARF2 register numbers. */ |
15837 | ||
15838 | unsigned int | |
15839 | rs6000_dbx_register_number (unsigned int regno) | |
15840 | { | |
15841 | if (regno <= 63 || write_symbols != DWARF2_DEBUG) | |
15842 | return regno; | |
15843 | if (regno == MQ_REGNO) | |
15844 | return 100; | |
15845 | if (regno == LINK_REGISTER_REGNUM) | |
15846 | return 108; | |
15847 | if (regno == COUNT_REGISTER_REGNUM) | |
15848 | return 109; | |
15849 | if (CR_REGNO_P (regno)) | |
15850 | return regno - CR0_REGNO + 86; | |
15851 | if (regno == XER_REGNO) | |
15852 | return 101; | |
15853 | if (ALTIVEC_REGNO_P (regno)) | |
15854 | return regno - FIRST_ALTIVEC_REGNO + 1124; | |
15855 | if (regno == VRSAVE_REGNO) | |
15856 | return 356; | |
15857 | if (regno == VSCR_REGNO) | |
15858 | return 67; | |
15859 | if (regno == SPE_ACC_REGNO) | |
15860 | return 99; | |
15861 | if (regno == SPEFSCR_REGNO) | |
15862 | return 612; | |
15863 | /* SPE high reg number. We get these values of regno from | |
15864 | rs6000_dwarf_register_span. */ | |
15865 | if (regno >= 1200 && regno < 1232) | |
15866 | return regno; | |
15867 | ||
15868 | abort (); | |
15869 | } | |
15870 | ||
17211ab5 | 15871 | #include "gt-rs6000.h" |