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9878760c | 1 | /* Subroutines used for code generation on IBM RS/6000. |
f676971a | 2 | Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, |
93c9d1ba | 3 | 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc. |
fab3bcc3 | 4 | Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu) |
9878760c | 5 | |
5de601cf | 6 | This file is part of GCC. |
9878760c | 7 | |
5de601cf NC |
8 | GCC is free software; you can redistribute it and/or modify it |
9 | under the terms of the GNU General Public License as published | |
10 | by the Free Software Foundation; either version 2, or (at your | |
11 | option) any later version. | |
9878760c | 12 | |
5de601cf NC |
13 | GCC is distributed in the hope that it will be useful, but WITHOUT |
14 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
15 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
16 | License for more details. | |
9878760c | 17 | |
5de601cf NC |
18 | You should have received a copy of the GNU General Public License |
19 | along with GCC; see the file COPYING. If not, write to the | |
20 | Free Software Foundation, 59 Temple Place - Suite 330, Boston, | |
21 | MA 02111-1307, USA. */ | |
9878760c | 22 | |
956d6950 | 23 | #include "config.h" |
c4d38ccb | 24 | #include "system.h" |
4977bab6 ZW |
25 | #include "coretypes.h" |
26 | #include "tm.h" | |
9878760c RK |
27 | #include "rtl.h" |
28 | #include "regs.h" | |
29 | #include "hard-reg-set.h" | |
30 | #include "real.h" | |
31 | #include "insn-config.h" | |
32 | #include "conditions.h" | |
9878760c RK |
33 | #include "insn-attr.h" |
34 | #include "flags.h" | |
35 | #include "recog.h" | |
9878760c | 36 | #include "obstack.h" |
9b30bae2 | 37 | #include "tree.h" |
dfafc897 | 38 | #include "expr.h" |
2fc1c679 | 39 | #include "optabs.h" |
2a430ec1 | 40 | #include "except.h" |
a7df97e6 | 41 | #include "function.h" |
296b8152 | 42 | #include "output.h" |
d5fa86ba | 43 | #include "basic-block.h" |
d0101753 | 44 | #include "integrate.h" |
296b8152 | 45 | #include "toplev.h" |
c8023011 | 46 | #include "ggc.h" |
9ebbca7d GK |
47 | #include "hashtab.h" |
48 | #include "tm_p.h" | |
672a6f42 NB |
49 | #include "target.h" |
50 | #include "target-def.h" | |
3ac88239 | 51 | #include "langhooks.h" |
24ea750e | 52 | #include "reload.h" |
117dca74 | 53 | #include "cfglayout.h" |
79ae11c4 | 54 | #include "sched-int.h" |
cd3ce9b4 | 55 | #include "tree-gimple.h" |
1bc7c5b6 ZW |
56 | #if TARGET_XCOFF |
57 | #include "xcoffout.h" /* get declarations of xcoff_*_section_name */ | |
58 | #endif | |
9b30bae2 | 59 | |
7509c759 MM |
60 | #ifndef TARGET_NO_PROTOTYPE |
61 | #define TARGET_NO_PROTOTYPE 0 | |
62 | #endif | |
63 | ||
452a7d36 | 64 | #define EASY_VECTOR_15(n) ((n) >= -16 && (n) <= 15) |
c4ad648e | 65 | #define EASY_VECTOR_15_ADD_SELF(n) ((n) >= 0x10 && (n) <= 0x1e && !((n) & 1)) |
d744e06e | 66 | |
9878760c RK |
67 | #define min(A,B) ((A) < (B) ? (A) : (B)) |
68 | #define max(A,B) ((A) > (B) ? (A) : (B)) | |
69 | ||
d1d0c603 JJ |
70 | /* Structure used to define the rs6000 stack */ |
71 | typedef struct rs6000_stack { | |
72 | int first_gp_reg_save; /* first callee saved GP register used */ | |
73 | int first_fp_reg_save; /* first callee saved FP register used */ | |
74 | int first_altivec_reg_save; /* first callee saved AltiVec register used */ | |
75 | int lr_save_p; /* true if the link reg needs to be saved */ | |
76 | int cr_save_p; /* true if the CR reg needs to be saved */ | |
77 | unsigned int vrsave_mask; /* mask of vec registers to save */ | |
78 | int toc_save_p; /* true if the TOC needs to be saved */ | |
79 | int push_p; /* true if we need to allocate stack space */ | |
80 | int calls_p; /* true if the function makes any calls */ | |
c4ad648e | 81 | int world_save_p; /* true if we're saving *everything*: |
d62294f5 | 82 | r13-r31, cr, f14-f31, vrsave, v20-v31 */ |
d1d0c603 JJ |
83 | enum rs6000_abi abi; /* which ABI to use */ |
84 | int gp_save_offset; /* offset to save GP regs from initial SP */ | |
85 | int fp_save_offset; /* offset to save FP regs from initial SP */ | |
86 | int altivec_save_offset; /* offset to save AltiVec regs from initial SP */ | |
87 | int lr_save_offset; /* offset to save LR from initial SP */ | |
88 | int cr_save_offset; /* offset to save CR from initial SP */ | |
89 | int vrsave_save_offset; /* offset to save VRSAVE from initial SP */ | |
90 | int spe_gp_save_offset; /* offset to save spe 64-bit gprs */ | |
91 | int toc_save_offset; /* offset to save the TOC pointer */ | |
92 | int varargs_save_offset; /* offset to save the varargs registers */ | |
93 | int ehrd_offset; /* offset to EH return data */ | |
94 | int reg_size; /* register size (4 or 8) */ | |
95 | int varargs_size; /* size to hold V.4 args passed in regs */ | |
96 | HOST_WIDE_INT vars_size; /* variable save area size */ | |
97 | int parm_size; /* outgoing parameter size */ | |
98 | int save_size; /* save area size */ | |
99 | int fixed_size; /* fixed size of stack frame */ | |
100 | int gp_size; /* size of saved GP registers */ | |
101 | int fp_size; /* size of saved FP registers */ | |
102 | int altivec_size; /* size of saved AltiVec registers */ | |
103 | int cr_size; /* size to hold CR if not in save_size */ | |
104 | int lr_size; /* size to hold LR if not in save_size */ | |
105 | int vrsave_size; /* size to hold VRSAVE if not in save_size */ | |
106 | int altivec_padding_size; /* size of altivec alignment padding if | |
107 | not in save_size */ | |
108 | int spe_gp_size; /* size of 64-bit GPR save size for SPE */ | |
109 | int spe_padding_size; | |
110 | int toc_size; /* size to hold TOC if not in save_size */ | |
111 | HOST_WIDE_INT total_size; /* total bytes allocated for stack */ | |
112 | int spe_64bit_regs_used; | |
113 | } rs6000_stack_t; | |
114 | ||
5248c961 RK |
115 | /* Target cpu type */ |
116 | ||
117 | enum processor_type rs6000_cpu; | |
8e3f41e7 MM |
118 | struct rs6000_cpu_select rs6000_select[3] = |
119 | { | |
815cdc52 MM |
120 | /* switch name, tune arch */ |
121 | { (const char *)0, "--with-cpu=", 1, 1 }, | |
122 | { (const char *)0, "-mcpu=", 1, 1 }, | |
123 | { (const char *)0, "-mtune=", 1, 0 }, | |
8e3f41e7 | 124 | }; |
5248c961 | 125 | |
ec507f2d DE |
126 | /* Always emit branch hint bits. */ |
127 | static GTY(()) bool rs6000_always_hint; | |
128 | ||
129 | /* Schedule instructions for group formation. */ | |
130 | static GTY(()) bool rs6000_sched_groups; | |
131 | ||
f676971a | 132 | /* Support adjust_priority scheduler hook |
79ae11c4 DN |
133 | and -mprioritize-restricted-insns= option. */ |
134 | const char *rs6000_sched_restricted_insns_priority_str; | |
135 | int rs6000_sched_restricted_insns_priority; | |
136 | ||
569fa502 DN |
137 | /* Support for -msched-costly-dep option. */ |
138 | const char *rs6000_sched_costly_dep_str; | |
139 | enum rs6000_dependence_cost rs6000_sched_costly_dep; | |
140 | ||
cbe26ab8 DN |
141 | /* Support for -minsert-sched-nops option. */ |
142 | const char *rs6000_sched_insert_nops_str; | |
143 | enum rs6000_nop_insertion rs6000_sched_insert_nops; | |
144 | ||
7ccf35ed | 145 | /* Support targetm.vectorize.builtin_mask_for_load. */ |
13c62176 | 146 | static GTY(()) tree altivec_builtin_mask_for_load; |
7ccf35ed | 147 | /* Support targetm.vectorize.builtin_mask_for_store. */ |
13c62176 | 148 | static GTY(()) tree altivec_builtin_mask_for_store; |
7ccf35ed | 149 | |
6fa3f289 ZW |
150 | /* Size of long double */ |
151 | const char *rs6000_long_double_size_string; | |
152 | int rs6000_long_double_type_size; | |
153 | ||
154 | /* Whether -mabi=altivec has appeared */ | |
155 | int rs6000_altivec_abi; | |
156 | ||
08b57fb3 AH |
157 | /* Whether VRSAVE instructions should be generated. */ |
158 | int rs6000_altivec_vrsave; | |
159 | ||
160 | /* String from -mvrsave= option. */ | |
161 | const char *rs6000_altivec_vrsave_string; | |
162 | ||
a3170dc6 AH |
163 | /* Nonzero if we want SPE ABI extensions. */ |
164 | int rs6000_spe_abi; | |
165 | ||
166 | /* Whether isel instructions should be generated. */ | |
167 | int rs6000_isel; | |
168 | ||
993f19a8 AH |
169 | /* Whether SPE simd instructions should be generated. */ |
170 | int rs6000_spe; | |
171 | ||
5da702b1 AH |
172 | /* Nonzero if floating point operations are done in the GPRs. */ |
173 | int rs6000_float_gprs = 0; | |
174 | ||
175 | /* String from -mfloat-gprs=. */ | |
176 | const char *rs6000_float_gprs_string; | |
a3170dc6 AH |
177 | |
178 | /* String from -misel=. */ | |
179 | const char *rs6000_isel_string; | |
180 | ||
993f19a8 AH |
181 | /* String from -mspe=. */ |
182 | const char *rs6000_spe_string; | |
183 | ||
a0ab749a | 184 | /* Set to nonzero once AIX common-mode calls have been defined. */ |
bbfb86aa | 185 | static GTY(()) int common_mode_defined; |
c81bebd7 | 186 | |
9878760c RK |
187 | /* Save information from a "cmpxx" operation until the branch or scc is |
188 | emitted. */ | |
9878760c RK |
189 | rtx rs6000_compare_op0, rs6000_compare_op1; |
190 | int rs6000_compare_fp_p; | |
874a0744 | 191 | |
874a0744 MM |
192 | /* Label number of label created for -mrelocatable, to call to so we can |
193 | get the address of the GOT section */ | |
194 | int rs6000_pic_labelno; | |
c81bebd7 | 195 | |
b91da81f | 196 | #ifdef USING_ELFOS_H |
c81bebd7 | 197 | /* Which abi to adhere to */ |
9739c90c | 198 | const char *rs6000_abi_name; |
d9407988 MM |
199 | |
200 | /* Semantics of the small data area */ | |
201 | enum rs6000_sdata_type rs6000_sdata = SDATA_DATA; | |
202 | ||
203 | /* Which small data model to use */ | |
815cdc52 | 204 | const char *rs6000_sdata_name = (char *)0; |
9ebbca7d GK |
205 | |
206 | /* Counter for labels which are to be placed in .fixup. */ | |
207 | int fixuplabelno = 0; | |
874a0744 | 208 | #endif |
4697a36c | 209 | |
c4501e62 JJ |
210 | /* Bit size of immediate TLS offsets and string from which it is decoded. */ |
211 | int rs6000_tls_size = 32; | |
212 | const char *rs6000_tls_size_string; | |
213 | ||
b6c9286a MM |
214 | /* ABI enumeration available for subtarget to use. */ |
215 | enum rs6000_abi rs6000_current_abi; | |
216 | ||
0ac081f6 AH |
217 | /* ABI string from -mabi= option. */ |
218 | const char *rs6000_abi_string; | |
219 | ||
85b776df AM |
220 | /* Whether to use variant of AIX ABI for PowerPC64 Linux. */ |
221 | int dot_symbols; | |
222 | ||
38c1f2d7 | 223 | /* Debug flags */ |
815cdc52 | 224 | const char *rs6000_debug_name; |
38c1f2d7 MM |
225 | int rs6000_debug_stack; /* debug stack applications */ |
226 | int rs6000_debug_arg; /* debug argument handling */ | |
227 | ||
0d1fbc8c AH |
228 | /* Value is TRUE if register/mode pair is accepatable. */ |
229 | bool rs6000_hard_regno_mode_ok_p[NUM_MACHINE_MODES][FIRST_PSEUDO_REGISTER]; | |
230 | ||
6035d635 | 231 | /* Opaque types. */ |
2abe3e28 | 232 | static GTY(()) tree opaque_V2SI_type_node; |
2abe3e28 | 233 | static GTY(()) tree opaque_V2SF_type_node; |
6035d635 | 234 | static GTY(()) tree opaque_p_V2SI_type_node; |
4a5eab38 PB |
235 | static GTY(()) tree V16QI_type_node; |
236 | static GTY(()) tree V2SI_type_node; | |
237 | static GTY(()) tree V2SF_type_node; | |
238 | static GTY(()) tree V4HI_type_node; | |
239 | static GTY(()) tree V4SI_type_node; | |
240 | static GTY(()) tree V4SF_type_node; | |
241 | static GTY(()) tree V8HI_type_node; | |
242 | static GTY(()) tree unsigned_V16QI_type_node; | |
243 | static GTY(()) tree unsigned_V8HI_type_node; | |
244 | static GTY(()) tree unsigned_V4SI_type_node; | |
8bb418a3 ZL |
245 | static GTY(()) tree bool_char_type_node; /* __bool char */ |
246 | static GTY(()) tree bool_short_type_node; /* __bool short */ | |
247 | static GTY(()) tree bool_int_type_node; /* __bool int */ | |
248 | static GTY(()) tree pixel_type_node; /* __pixel */ | |
249 | static GTY(()) tree bool_V16QI_type_node; /* __vector __bool char */ | |
250 | static GTY(()) tree bool_V8HI_type_node; /* __vector __bool short */ | |
251 | static GTY(()) tree bool_V4SI_type_node; /* __vector __bool int */ | |
252 | static GTY(()) tree pixel_V8HI_type_node; /* __vector __pixel */ | |
253 | ||
254 | int rs6000_warn_altivec_long = 1; /* On by default. */ | |
255 | const char *rs6000_warn_altivec_long_switch; | |
256 | ||
57ac7be9 AM |
257 | const char *rs6000_traceback_name; |
258 | static enum { | |
259 | traceback_default = 0, | |
260 | traceback_none, | |
261 | traceback_part, | |
262 | traceback_full | |
263 | } rs6000_traceback; | |
264 | ||
38c1f2d7 MM |
265 | /* Flag to say the TOC is initialized */ |
266 | int toc_initialized; | |
9ebbca7d | 267 | char toc_label_name[10]; |
38c1f2d7 | 268 | |
9ebbca7d | 269 | /* Alias set for saves and restores from the rs6000 stack. */ |
f103e34d | 270 | static GTY(()) int rs6000_sr_alias_set; |
c8023011 | 271 | |
a5c76ee6 ZW |
272 | /* Call distance, overridden by -mlongcall and #pragma longcall(1). |
273 | The only place that looks at this is rs6000_set_default_type_attributes; | |
274 | everywhere else should rely on the presence or absence of a longcall | |
275 | attribute on the function declaration. */ | |
276 | int rs6000_default_long_calls; | |
277 | const char *rs6000_longcall_switch; | |
278 | ||
a3c9585f KH |
279 | /* Control alignment for fields within structures. */ |
280 | /* String from -malign-XXXXX. */ | |
025d9908 KH |
281 | const char *rs6000_alignment_string; |
282 | int rs6000_alignment_flags; | |
283 | ||
a3170dc6 AH |
284 | struct builtin_description |
285 | { | |
286 | /* mask is not const because we're going to alter it below. This | |
287 | nonsense will go away when we rewrite the -march infrastructure | |
288 | to give us more target flag bits. */ | |
289 | unsigned int mask; | |
290 | const enum insn_code icode; | |
291 | const char *const name; | |
292 | const enum rs6000_builtins code; | |
293 | }; | |
8b897cfa RS |
294 | \f |
295 | /* Target cpu costs. */ | |
296 | ||
297 | struct processor_costs { | |
c4ad648e | 298 | const int mulsi; /* cost of SImode multiplication. */ |
8b897cfa RS |
299 | const int mulsi_const; /* cost of SImode multiplication by constant. */ |
300 | const int mulsi_const9; /* cost of SImode mult by short constant. */ | |
c4ad648e AM |
301 | const int muldi; /* cost of DImode multiplication. */ |
302 | const int divsi; /* cost of SImode division. */ | |
303 | const int divdi; /* cost of DImode division. */ | |
304 | const int fp; /* cost of simple SFmode and DFmode insns. */ | |
305 | const int dmul; /* cost of DFmode multiplication (and fmadd). */ | |
306 | const int sdiv; /* cost of SFmode division (fdivs). */ | |
307 | const int ddiv; /* cost of DFmode division (fdiv). */ | |
8b897cfa RS |
308 | }; |
309 | ||
310 | const struct processor_costs *rs6000_cost; | |
311 | ||
312 | /* Processor costs (relative to an add) */ | |
313 | ||
314 | /* Instruction size costs on 32bit processors. */ | |
315 | static const | |
316 | struct processor_costs size32_cost = { | |
06a67bdd RS |
317 | COSTS_N_INSNS (1), /* mulsi */ |
318 | COSTS_N_INSNS (1), /* mulsi_const */ | |
319 | COSTS_N_INSNS (1), /* mulsi_const9 */ | |
320 | COSTS_N_INSNS (1), /* muldi */ | |
321 | COSTS_N_INSNS (1), /* divsi */ | |
322 | COSTS_N_INSNS (1), /* divdi */ | |
323 | COSTS_N_INSNS (1), /* fp */ | |
324 | COSTS_N_INSNS (1), /* dmul */ | |
325 | COSTS_N_INSNS (1), /* sdiv */ | |
326 | COSTS_N_INSNS (1), /* ddiv */ | |
8b897cfa RS |
327 | }; |
328 | ||
329 | /* Instruction size costs on 64bit processors. */ | |
330 | static const | |
331 | struct processor_costs size64_cost = { | |
06a67bdd RS |
332 | COSTS_N_INSNS (1), /* mulsi */ |
333 | COSTS_N_INSNS (1), /* mulsi_const */ | |
334 | COSTS_N_INSNS (1), /* mulsi_const9 */ | |
335 | COSTS_N_INSNS (1), /* muldi */ | |
336 | COSTS_N_INSNS (1), /* divsi */ | |
337 | COSTS_N_INSNS (1), /* divdi */ | |
338 | COSTS_N_INSNS (1), /* fp */ | |
339 | COSTS_N_INSNS (1), /* dmul */ | |
340 | COSTS_N_INSNS (1), /* sdiv */ | |
341 | COSTS_N_INSNS (1), /* ddiv */ | |
8b897cfa RS |
342 | }; |
343 | ||
344 | /* Instruction costs on RIOS1 processors. */ | |
345 | static const | |
346 | struct processor_costs rios1_cost = { | |
06a67bdd RS |
347 | COSTS_N_INSNS (5), /* mulsi */ |
348 | COSTS_N_INSNS (4), /* mulsi_const */ | |
349 | COSTS_N_INSNS (3), /* mulsi_const9 */ | |
350 | COSTS_N_INSNS (5), /* muldi */ | |
351 | COSTS_N_INSNS (19), /* divsi */ | |
352 | COSTS_N_INSNS (19), /* divdi */ | |
353 | COSTS_N_INSNS (2), /* fp */ | |
354 | COSTS_N_INSNS (2), /* dmul */ | |
355 | COSTS_N_INSNS (19), /* sdiv */ | |
356 | COSTS_N_INSNS (19), /* ddiv */ | |
8b897cfa RS |
357 | }; |
358 | ||
359 | /* Instruction costs on RIOS2 processors. */ | |
360 | static const | |
361 | struct processor_costs rios2_cost = { | |
06a67bdd RS |
362 | COSTS_N_INSNS (2), /* mulsi */ |
363 | COSTS_N_INSNS (2), /* mulsi_const */ | |
364 | COSTS_N_INSNS (2), /* mulsi_const9 */ | |
365 | COSTS_N_INSNS (2), /* muldi */ | |
366 | COSTS_N_INSNS (13), /* divsi */ | |
367 | COSTS_N_INSNS (13), /* divdi */ | |
368 | COSTS_N_INSNS (2), /* fp */ | |
369 | COSTS_N_INSNS (2), /* dmul */ | |
370 | COSTS_N_INSNS (17), /* sdiv */ | |
371 | COSTS_N_INSNS (17), /* ddiv */ | |
8b897cfa RS |
372 | }; |
373 | ||
374 | /* Instruction costs on RS64A processors. */ | |
375 | static const | |
376 | struct processor_costs rs64a_cost = { | |
06a67bdd RS |
377 | COSTS_N_INSNS (20), /* mulsi */ |
378 | COSTS_N_INSNS (12), /* mulsi_const */ | |
379 | COSTS_N_INSNS (8), /* mulsi_const9 */ | |
380 | COSTS_N_INSNS (34), /* muldi */ | |
381 | COSTS_N_INSNS (65), /* divsi */ | |
382 | COSTS_N_INSNS (67), /* divdi */ | |
383 | COSTS_N_INSNS (4), /* fp */ | |
384 | COSTS_N_INSNS (4), /* dmul */ | |
385 | COSTS_N_INSNS (31), /* sdiv */ | |
386 | COSTS_N_INSNS (31), /* ddiv */ | |
8b897cfa RS |
387 | }; |
388 | ||
389 | /* Instruction costs on MPCCORE processors. */ | |
390 | static const | |
391 | struct processor_costs mpccore_cost = { | |
06a67bdd RS |
392 | COSTS_N_INSNS (2), /* mulsi */ |
393 | COSTS_N_INSNS (2), /* mulsi_const */ | |
394 | COSTS_N_INSNS (2), /* mulsi_const9 */ | |
395 | COSTS_N_INSNS (2), /* muldi */ | |
396 | COSTS_N_INSNS (6), /* divsi */ | |
397 | COSTS_N_INSNS (6), /* divdi */ | |
398 | COSTS_N_INSNS (4), /* fp */ | |
399 | COSTS_N_INSNS (5), /* dmul */ | |
400 | COSTS_N_INSNS (10), /* sdiv */ | |
401 | COSTS_N_INSNS (17), /* ddiv */ | |
8b897cfa RS |
402 | }; |
403 | ||
404 | /* Instruction costs on PPC403 processors. */ | |
405 | static const | |
406 | struct processor_costs ppc403_cost = { | |
06a67bdd RS |
407 | COSTS_N_INSNS (4), /* mulsi */ |
408 | COSTS_N_INSNS (4), /* mulsi_const */ | |
409 | COSTS_N_INSNS (4), /* mulsi_const9 */ | |
410 | COSTS_N_INSNS (4), /* muldi */ | |
411 | COSTS_N_INSNS (33), /* divsi */ | |
412 | COSTS_N_INSNS (33), /* divdi */ | |
413 | COSTS_N_INSNS (11), /* fp */ | |
414 | COSTS_N_INSNS (11), /* dmul */ | |
415 | COSTS_N_INSNS (11), /* sdiv */ | |
416 | COSTS_N_INSNS (11), /* ddiv */ | |
8b897cfa RS |
417 | }; |
418 | ||
419 | /* Instruction costs on PPC405 processors. */ | |
420 | static const | |
421 | struct processor_costs ppc405_cost = { | |
06a67bdd RS |
422 | COSTS_N_INSNS (5), /* mulsi */ |
423 | COSTS_N_INSNS (4), /* mulsi_const */ | |
424 | COSTS_N_INSNS (3), /* mulsi_const9 */ | |
425 | COSTS_N_INSNS (5), /* muldi */ | |
426 | COSTS_N_INSNS (35), /* divsi */ | |
427 | COSTS_N_INSNS (35), /* divdi */ | |
428 | COSTS_N_INSNS (11), /* fp */ | |
429 | COSTS_N_INSNS (11), /* dmul */ | |
430 | COSTS_N_INSNS (11), /* sdiv */ | |
431 | COSTS_N_INSNS (11), /* ddiv */ | |
8b897cfa RS |
432 | }; |
433 | ||
434 | /* Instruction costs on PPC440 processors. */ | |
435 | static const | |
436 | struct processor_costs ppc440_cost = { | |
06a67bdd RS |
437 | COSTS_N_INSNS (3), /* mulsi */ |
438 | COSTS_N_INSNS (2), /* mulsi_const */ | |
439 | COSTS_N_INSNS (2), /* mulsi_const9 */ | |
440 | COSTS_N_INSNS (3), /* muldi */ | |
441 | COSTS_N_INSNS (34), /* divsi */ | |
442 | COSTS_N_INSNS (34), /* divdi */ | |
443 | COSTS_N_INSNS (5), /* fp */ | |
444 | COSTS_N_INSNS (5), /* dmul */ | |
445 | COSTS_N_INSNS (19), /* sdiv */ | |
446 | COSTS_N_INSNS (33), /* ddiv */ | |
8b897cfa RS |
447 | }; |
448 | ||
449 | /* Instruction costs on PPC601 processors. */ | |
450 | static const | |
451 | struct processor_costs ppc601_cost = { | |
06a67bdd RS |
452 | COSTS_N_INSNS (5), /* mulsi */ |
453 | COSTS_N_INSNS (5), /* mulsi_const */ | |
454 | COSTS_N_INSNS (5), /* mulsi_const9 */ | |
455 | COSTS_N_INSNS (5), /* muldi */ | |
456 | COSTS_N_INSNS (36), /* divsi */ | |
457 | COSTS_N_INSNS (36), /* divdi */ | |
458 | COSTS_N_INSNS (4), /* fp */ | |
459 | COSTS_N_INSNS (5), /* dmul */ | |
460 | COSTS_N_INSNS (17), /* sdiv */ | |
461 | COSTS_N_INSNS (31), /* ddiv */ | |
8b897cfa RS |
462 | }; |
463 | ||
464 | /* Instruction costs on PPC603 processors. */ | |
465 | static const | |
466 | struct processor_costs ppc603_cost = { | |
06a67bdd RS |
467 | COSTS_N_INSNS (5), /* mulsi */ |
468 | COSTS_N_INSNS (3), /* mulsi_const */ | |
469 | COSTS_N_INSNS (2), /* mulsi_const9 */ | |
470 | COSTS_N_INSNS (5), /* muldi */ | |
471 | COSTS_N_INSNS (37), /* divsi */ | |
472 | COSTS_N_INSNS (37), /* divdi */ | |
473 | COSTS_N_INSNS (3), /* fp */ | |
474 | COSTS_N_INSNS (4), /* dmul */ | |
475 | COSTS_N_INSNS (18), /* sdiv */ | |
476 | COSTS_N_INSNS (33), /* ddiv */ | |
8b897cfa RS |
477 | }; |
478 | ||
479 | /* Instruction costs on PPC604 processors. */ | |
480 | static const | |
481 | struct processor_costs ppc604_cost = { | |
06a67bdd RS |
482 | COSTS_N_INSNS (4), /* mulsi */ |
483 | COSTS_N_INSNS (4), /* mulsi_const */ | |
484 | COSTS_N_INSNS (4), /* mulsi_const9 */ | |
485 | COSTS_N_INSNS (4), /* muldi */ | |
486 | COSTS_N_INSNS (20), /* divsi */ | |
487 | COSTS_N_INSNS (20), /* divdi */ | |
488 | COSTS_N_INSNS (3), /* fp */ | |
489 | COSTS_N_INSNS (3), /* dmul */ | |
490 | COSTS_N_INSNS (18), /* sdiv */ | |
491 | COSTS_N_INSNS (32), /* ddiv */ | |
8b897cfa RS |
492 | }; |
493 | ||
494 | /* Instruction costs on PPC604e processors. */ | |
495 | static const | |
496 | struct processor_costs ppc604e_cost = { | |
06a67bdd RS |
497 | COSTS_N_INSNS (2), /* mulsi */ |
498 | COSTS_N_INSNS (2), /* mulsi_const */ | |
499 | COSTS_N_INSNS (2), /* mulsi_const9 */ | |
500 | COSTS_N_INSNS (2), /* muldi */ | |
501 | COSTS_N_INSNS (20), /* divsi */ | |
502 | COSTS_N_INSNS (20), /* divdi */ | |
503 | COSTS_N_INSNS (3), /* fp */ | |
504 | COSTS_N_INSNS (3), /* dmul */ | |
505 | COSTS_N_INSNS (18), /* sdiv */ | |
506 | COSTS_N_INSNS (32), /* ddiv */ | |
8b897cfa RS |
507 | }; |
508 | ||
f0517163 | 509 | /* Instruction costs on PPC620 processors. */ |
8b897cfa RS |
510 | static const |
511 | struct processor_costs ppc620_cost = { | |
06a67bdd RS |
512 | COSTS_N_INSNS (5), /* mulsi */ |
513 | COSTS_N_INSNS (4), /* mulsi_const */ | |
514 | COSTS_N_INSNS (3), /* mulsi_const9 */ | |
515 | COSTS_N_INSNS (7), /* muldi */ | |
516 | COSTS_N_INSNS (21), /* divsi */ | |
517 | COSTS_N_INSNS (37), /* divdi */ | |
518 | COSTS_N_INSNS (3), /* fp */ | |
519 | COSTS_N_INSNS (3), /* dmul */ | |
520 | COSTS_N_INSNS (18), /* sdiv */ | |
521 | COSTS_N_INSNS (32), /* ddiv */ | |
f0517163 RS |
522 | }; |
523 | ||
524 | /* Instruction costs on PPC630 processors. */ | |
525 | static const | |
526 | struct processor_costs ppc630_cost = { | |
06a67bdd RS |
527 | COSTS_N_INSNS (5), /* mulsi */ |
528 | COSTS_N_INSNS (4), /* mulsi_const */ | |
529 | COSTS_N_INSNS (3), /* mulsi_const9 */ | |
530 | COSTS_N_INSNS (7), /* muldi */ | |
531 | COSTS_N_INSNS (21), /* divsi */ | |
532 | COSTS_N_INSNS (37), /* divdi */ | |
533 | COSTS_N_INSNS (3), /* fp */ | |
534 | COSTS_N_INSNS (3), /* dmul */ | |
535 | COSTS_N_INSNS (17), /* sdiv */ | |
536 | COSTS_N_INSNS (21), /* ddiv */ | |
8b897cfa RS |
537 | }; |
538 | ||
539 | /* Instruction costs on PPC750 and PPC7400 processors. */ | |
540 | static const | |
541 | struct processor_costs ppc750_cost = { | |
06a67bdd RS |
542 | COSTS_N_INSNS (5), /* mulsi */ |
543 | COSTS_N_INSNS (3), /* mulsi_const */ | |
544 | COSTS_N_INSNS (2), /* mulsi_const9 */ | |
545 | COSTS_N_INSNS (5), /* muldi */ | |
546 | COSTS_N_INSNS (17), /* divsi */ | |
547 | COSTS_N_INSNS (17), /* divdi */ | |
548 | COSTS_N_INSNS (3), /* fp */ | |
549 | COSTS_N_INSNS (3), /* dmul */ | |
550 | COSTS_N_INSNS (17), /* sdiv */ | |
551 | COSTS_N_INSNS (31), /* ddiv */ | |
8b897cfa RS |
552 | }; |
553 | ||
554 | /* Instruction costs on PPC7450 processors. */ | |
555 | static const | |
556 | struct processor_costs ppc7450_cost = { | |
06a67bdd RS |
557 | COSTS_N_INSNS (4), /* mulsi */ |
558 | COSTS_N_INSNS (3), /* mulsi_const */ | |
559 | COSTS_N_INSNS (3), /* mulsi_const9 */ | |
560 | COSTS_N_INSNS (4), /* muldi */ | |
561 | COSTS_N_INSNS (23), /* divsi */ | |
562 | COSTS_N_INSNS (23), /* divdi */ | |
563 | COSTS_N_INSNS (5), /* fp */ | |
564 | COSTS_N_INSNS (5), /* dmul */ | |
565 | COSTS_N_INSNS (21), /* sdiv */ | |
566 | COSTS_N_INSNS (35), /* ddiv */ | |
8b897cfa | 567 | }; |
a3170dc6 | 568 | |
8b897cfa RS |
569 | /* Instruction costs on PPC8540 processors. */ |
570 | static const | |
571 | struct processor_costs ppc8540_cost = { | |
06a67bdd RS |
572 | COSTS_N_INSNS (4), /* mulsi */ |
573 | COSTS_N_INSNS (4), /* mulsi_const */ | |
574 | COSTS_N_INSNS (4), /* mulsi_const9 */ | |
575 | COSTS_N_INSNS (4), /* muldi */ | |
576 | COSTS_N_INSNS (19), /* divsi */ | |
577 | COSTS_N_INSNS (19), /* divdi */ | |
578 | COSTS_N_INSNS (4), /* fp */ | |
579 | COSTS_N_INSNS (4), /* dmul */ | |
580 | COSTS_N_INSNS (29), /* sdiv */ | |
581 | COSTS_N_INSNS (29), /* ddiv */ | |
8b897cfa RS |
582 | }; |
583 | ||
584 | /* Instruction costs on POWER4 and POWER5 processors. */ | |
585 | static const | |
586 | struct processor_costs power4_cost = { | |
06a67bdd RS |
587 | COSTS_N_INSNS (3), /* mulsi */ |
588 | COSTS_N_INSNS (2), /* mulsi_const */ | |
589 | COSTS_N_INSNS (2), /* mulsi_const9 */ | |
590 | COSTS_N_INSNS (4), /* muldi */ | |
591 | COSTS_N_INSNS (18), /* divsi */ | |
592 | COSTS_N_INSNS (34), /* divdi */ | |
593 | COSTS_N_INSNS (3), /* fp */ | |
594 | COSTS_N_INSNS (3), /* dmul */ | |
595 | COSTS_N_INSNS (17), /* sdiv */ | |
596 | COSTS_N_INSNS (17), /* ddiv */ | |
8b897cfa RS |
597 | }; |
598 | ||
599 | \f | |
a2369ed3 DJ |
600 | static bool rs6000_function_ok_for_sibcall (tree, tree); |
601 | static int num_insns_constant_wide (HOST_WIDE_INT); | |
602 | static void validate_condition_mode (enum rtx_code, enum machine_mode); | |
603 | static rtx rs6000_generate_compare (enum rtx_code); | |
604 | static void rs6000_maybe_dead (rtx); | |
605 | static void rs6000_emit_stack_tie (void); | |
606 | static void rs6000_frame_related (rtx, rtx, HOST_WIDE_INT, rtx, rtx); | |
607 | static rtx spe_synthesize_frame_save (rtx); | |
608 | static bool spe_func_has_64bit_regs_p (void); | |
b20a9cca | 609 | static void emit_frame_save (rtx, rtx, enum machine_mode, unsigned int, |
d1d0c603 | 610 | int, HOST_WIDE_INT); |
a2369ed3 DJ |
611 | static rtx gen_frame_mem_offset (enum machine_mode, rtx, int); |
612 | static void rs6000_emit_allocate_stack (HOST_WIDE_INT, int); | |
613 | static unsigned rs6000_hash_constant (rtx); | |
614 | static unsigned toc_hash_function (const void *); | |
615 | static int toc_hash_eq (const void *, const void *); | |
616 | static int constant_pool_expr_1 (rtx, int *, int *); | |
617 | static bool constant_pool_expr_p (rtx); | |
618 | static bool toc_relative_expr_p (rtx); | |
619 | static bool legitimate_small_data_p (enum machine_mode, rtx); | |
a2369ed3 DJ |
620 | static bool legitimate_indexed_address_p (rtx, int); |
621 | static bool legitimate_indirect_address_p (rtx, int); | |
4c81e946 | 622 | static bool macho_lo_sum_memory_operand (rtx x, enum machine_mode mode); |
a2369ed3 DJ |
623 | static bool legitimate_lo_sum_address_p (enum machine_mode, rtx, int); |
624 | static struct machine_function * rs6000_init_machine_status (void); | |
625 | static bool rs6000_assemble_integer (rtx, unsigned int, int); | |
5add3202 | 626 | #ifdef HAVE_GAS_HIDDEN |
a2369ed3 | 627 | static void rs6000_assemble_visibility (tree, int); |
5add3202 | 628 | #endif |
a2369ed3 DJ |
629 | static int rs6000_ra_ever_killed (void); |
630 | static tree rs6000_handle_longcall_attribute (tree *, tree, tree, int, bool *); | |
8bb418a3 | 631 | static tree rs6000_handle_altivec_attribute (tree *, tree, tree, int, bool *); |
76d2b81d | 632 | static void rs6000_eliminate_indexed_memrefs (rtx operands[2]); |
f18eca82 | 633 | static const char *rs6000_mangle_fundamental_type (tree); |
b86fe7b4 | 634 | extern const struct attribute_spec rs6000_attribute_table[]; |
a2369ed3 DJ |
635 | static void rs6000_set_default_type_attributes (tree); |
636 | static void rs6000_output_function_prologue (FILE *, HOST_WIDE_INT); | |
637 | static void rs6000_output_function_epilogue (FILE *, HOST_WIDE_INT); | |
b20a9cca AM |
638 | static void rs6000_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT, |
639 | tree); | |
a2369ed3 | 640 | static rtx rs6000_emit_set_long_const (rtx, HOST_WIDE_INT, HOST_WIDE_INT); |
c6e8c921 | 641 | static bool rs6000_return_in_memory (tree, tree); |
a2369ed3 | 642 | static void rs6000_file_start (void); |
7c262518 | 643 | #if TARGET_ELF |
a2369ed3 DJ |
644 | static unsigned int rs6000_elf_section_type_flags (tree, const char *, int); |
645 | static void rs6000_elf_asm_out_constructor (rtx, int); | |
646 | static void rs6000_elf_asm_out_destructor (rtx, int); | |
647 | static void rs6000_elf_select_section (tree, int, unsigned HOST_WIDE_INT); | |
648 | static void rs6000_elf_unique_section (tree, int); | |
649 | static void rs6000_elf_select_rtx_section (enum machine_mode, rtx, | |
b20a9cca | 650 | unsigned HOST_WIDE_INT); |
a56d7372 | 651 | static void rs6000_elf_encode_section_info (tree, rtx, int) |
0e5dbd9b | 652 | ATTRIBUTE_UNUSED; |
a2369ed3 | 653 | static bool rs6000_elf_in_small_data_p (tree); |
7c262518 | 654 | #endif |
cbaaba19 | 655 | #if TARGET_XCOFF |
a2369ed3 | 656 | static void rs6000_xcoff_asm_globalize_label (FILE *, const char *); |
8210e4c4 | 657 | static void rs6000_xcoff_asm_named_section (const char *, unsigned int, tree); |
a2369ed3 DJ |
658 | static void rs6000_xcoff_select_section (tree, int, unsigned HOST_WIDE_INT); |
659 | static void rs6000_xcoff_unique_section (tree, int); | |
660 | static void rs6000_xcoff_select_rtx_section (enum machine_mode, rtx, | |
b20a9cca | 661 | unsigned HOST_WIDE_INT); |
a2369ed3 DJ |
662 | static const char * rs6000_xcoff_strip_name_encoding (const char *); |
663 | static unsigned int rs6000_xcoff_section_type_flags (tree, const char *, int); | |
664 | static void rs6000_xcoff_file_start (void); | |
665 | static void rs6000_xcoff_file_end (void); | |
f1384257 AM |
666 | #endif |
667 | #if TARGET_MACHO | |
a2369ed3 | 668 | static bool rs6000_binds_local_p (tree); |
f1384257 | 669 | #endif |
a2369ed3 DJ |
670 | static int rs6000_variable_issue (FILE *, int, rtx, int); |
671 | static bool rs6000_rtx_costs (rtx, int, int, int *); | |
672 | static int rs6000_adjust_cost (rtx, rtx, rtx, int); | |
cbe26ab8 | 673 | static bool is_microcoded_insn (rtx); |
79ae11c4 | 674 | static int is_dispatch_slot_restricted (rtx); |
cbe26ab8 DN |
675 | static bool is_cracked_insn (rtx); |
676 | static bool is_branch_slot_insn (rtx); | |
a2369ed3 DJ |
677 | static int rs6000_adjust_priority (rtx, int); |
678 | static int rs6000_issue_rate (void); | |
569fa502 | 679 | static bool rs6000_is_costly_dependence (rtx, rtx, rtx, int, int); |
cbe26ab8 DN |
680 | static rtx get_next_active_insn (rtx, rtx); |
681 | static bool insn_terminates_group_p (rtx , enum group_termination); | |
682 | static bool is_costly_group (rtx *, rtx); | |
683 | static int force_new_group (int, FILE *, rtx *, rtx, bool *, int, int *); | |
684 | static int redefine_groups (FILE *, int, rtx, rtx); | |
685 | static int pad_groups (FILE *, int, rtx, rtx); | |
686 | static void rs6000_sched_finish (FILE *, int); | |
a2369ed3 | 687 | static int rs6000_use_sched_lookahead (void); |
7ccf35ed DN |
688 | static tree rs6000_builtin_mask_for_load (void); |
689 | static tree rs6000_builtin_mask_for_store (void); | |
a2369ed3 DJ |
690 | |
691 | static void rs6000_init_builtins (void); | |
692 | static rtx rs6000_expand_unop_builtin (enum insn_code, tree, rtx); | |
693 | static rtx rs6000_expand_binop_builtin (enum insn_code, tree, rtx); | |
694 | static rtx rs6000_expand_ternop_builtin (enum insn_code, tree, rtx); | |
695 | static rtx rs6000_expand_builtin (tree, rtx, rtx, enum machine_mode, int); | |
696 | static void altivec_init_builtins (void); | |
697 | static void rs6000_common_init_builtins (void); | |
c15c90bb | 698 | static void rs6000_init_libfuncs (void); |
a2369ed3 | 699 | |
b20a9cca AM |
700 | static void enable_mask_for_builtins (struct builtin_description *, int, |
701 | enum rs6000_builtins, | |
702 | enum rs6000_builtins); | |
7c62e993 | 703 | static tree build_opaque_vector_type (tree, int); |
a2369ed3 DJ |
704 | static void spe_init_builtins (void); |
705 | static rtx spe_expand_builtin (tree, rtx, bool *); | |
61bea3b0 | 706 | static rtx spe_expand_stv_builtin (enum insn_code, tree); |
a2369ed3 DJ |
707 | static rtx spe_expand_predicate_builtin (enum insn_code, tree, rtx); |
708 | static rtx spe_expand_evsel_builtin (enum insn_code, tree, rtx); | |
709 | static int rs6000_emit_int_cmove (rtx, rtx, rtx, rtx); | |
d1d0c603 JJ |
710 | static rs6000_stack_t *rs6000_stack_info (void); |
711 | static void debug_stack_info (rs6000_stack_t *); | |
a2369ed3 DJ |
712 | |
713 | static rtx altivec_expand_builtin (tree, rtx, bool *); | |
714 | static rtx altivec_expand_ld_builtin (tree, rtx, bool *); | |
715 | static rtx altivec_expand_st_builtin (tree, rtx, bool *); | |
716 | static rtx altivec_expand_dst_builtin (tree, rtx, bool *); | |
717 | static rtx altivec_expand_abs_builtin (enum insn_code, tree, rtx); | |
f676971a | 718 | static rtx altivec_expand_predicate_builtin (enum insn_code, |
c4ad648e | 719 | const char *, tree, rtx); |
b4a62fa0 | 720 | static rtx altivec_expand_lv_builtin (enum insn_code, tree, rtx); |
a2369ed3 DJ |
721 | static rtx altivec_expand_stv_builtin (enum insn_code, tree); |
722 | static void rs6000_parse_abi_options (void); | |
723 | static void rs6000_parse_alignment_option (void); | |
724 | static void rs6000_parse_tls_size_option (void); | |
5da702b1 | 725 | static void rs6000_parse_yes_no_option (const char *, const char *, int *); |
4d4cbc0e | 726 | static void rs6000_parse_float_gprs_option (void); |
a2369ed3 DJ |
727 | static int first_altivec_reg_to_save (void); |
728 | static unsigned int compute_vrsave_mask (void); | |
d62294f5 | 729 | static void compute_save_world_info(rs6000_stack_t *info_ptr); |
a2369ed3 DJ |
730 | static void is_altivec_return_reg (rtx, void *); |
731 | static rtx generate_set_vrsave (rtx, rs6000_stack_t *, int); | |
732 | int easy_vector_constant (rtx, enum machine_mode); | |
733 | static int easy_vector_same (rtx, enum machine_mode); | |
452a7d36 | 734 | static int easy_vector_splat_const (int, enum machine_mode); |
a2369ed3 DJ |
735 | static bool is_ev64_opaque_type (tree); |
736 | static rtx rs6000_dwarf_register_span (rtx); | |
737 | static rtx rs6000_legitimize_tls_address (rtx, enum tls_model); | |
738 | static rtx rs6000_tls_get_addr (void); | |
739 | static rtx rs6000_got_sym (void); | |
740 | static inline int rs6000_tls_symbol_ref_1 (rtx *, void *); | |
741 | static const char *rs6000_get_some_local_dynamic_name (void); | |
742 | static int rs6000_get_some_local_dynamic_name_1 (rtx *, void *); | |
ded9bf77 | 743 | static rtx rs6000_complex_function_value (enum machine_mode); |
b20a9cca | 744 | static rtx rs6000_spe_function_arg (CUMULATIVE_ARGS *, |
a2369ed3 | 745 | enum machine_mode, tree); |
ec6376ab | 746 | static rtx rs6000_mixed_function_arg (enum machine_mode, tree, int); |
b1917422 | 747 | static void rs6000_move_block_from_reg (int regno, rtx x, int nregs); |
c6e8c921 GK |
748 | static void setup_incoming_varargs (CUMULATIVE_ARGS *, |
749 | enum machine_mode, tree, | |
750 | int *, int); | |
8cd5a4e0 RH |
751 | static bool rs6000_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode, |
752 | tree, bool); | |
efdba735 SH |
753 | #if TARGET_MACHO |
754 | static void macho_branch_islands (void); | |
755 | static void add_compiler_branch_island (tree, tree, int); | |
756 | static int no_previous_def (tree function_name); | |
757 | static tree get_prev_label (tree function_name); | |
c4e18b1c | 758 | static void rs6000_darwin_file_start (void); |
efdba735 SH |
759 | #endif |
760 | ||
c35d187f | 761 | static tree rs6000_build_builtin_va_list (void); |
23a60a04 | 762 | static tree rs6000_gimplify_va_arg (tree, tree, tree *, tree *); |
fe984136 | 763 | static bool rs6000_must_pass_in_stack (enum machine_mode, tree); |
f676971a | 764 | static bool rs6000_vector_mode_supported_p (enum machine_mode); |
21213b4c DP |
765 | static int get_vec_cmp_insn (enum rtx_code, enum machine_mode, |
766 | enum machine_mode); | |
767 | static rtx rs6000_emit_vector_compare (enum rtx_code, rtx, rtx, | |
768 | enum machine_mode); | |
769 | static int get_vsel_insn (enum machine_mode); | |
770 | static void rs6000_emit_vector_select (rtx, rtx, rtx, rtx); | |
17211ab5 | 771 | |
21213b4c DP |
772 | |
773 | const int INSN_NOT_AVAILABLE = -1; | |
93f90be6 FJ |
774 | static enum machine_mode rs6000_eh_return_filter_mode (void); |
775 | ||
17211ab5 GK |
776 | /* Hash table stuff for keeping track of TOC entries. */ |
777 | ||
778 | struct toc_hash_struct GTY(()) | |
779 | { | |
780 | /* `key' will satisfy CONSTANT_P; in fact, it will satisfy | |
781 | ASM_OUTPUT_SPECIAL_POOL_ENTRY_P. */ | |
782 | rtx key; | |
783 | enum machine_mode key_mode; | |
784 | int labelno; | |
785 | }; | |
786 | ||
787 | static GTY ((param_is (struct toc_hash_struct))) htab_t toc_hash_table; | |
c81bebd7 MM |
788 | \f |
789 | /* Default register names. */ | |
790 | char rs6000_reg_names[][8] = | |
791 | { | |
802a0058 MM |
792 | "0", "1", "2", "3", "4", "5", "6", "7", |
793 | "8", "9", "10", "11", "12", "13", "14", "15", | |
794 | "16", "17", "18", "19", "20", "21", "22", "23", | |
795 | "24", "25", "26", "27", "28", "29", "30", "31", | |
796 | "0", "1", "2", "3", "4", "5", "6", "7", | |
797 | "8", "9", "10", "11", "12", "13", "14", "15", | |
798 | "16", "17", "18", "19", "20", "21", "22", "23", | |
799 | "24", "25", "26", "27", "28", "29", "30", "31", | |
800 | "mq", "lr", "ctr","ap", | |
801 | "0", "1", "2", "3", "4", "5", "6", "7", | |
0ac081f6 AH |
802 | "xer", |
803 | /* AltiVec registers. */ | |
0cd5e3a1 AH |
804 | "0", "1", "2", "3", "4", "5", "6", "7", |
805 | "8", "9", "10", "11", "12", "13", "14", "15", | |
806 | "16", "17", "18", "19", "20", "21", "22", "23", | |
807 | "24", "25", "26", "27", "28", "29", "30", "31", | |
59a4c851 AH |
808 | "vrsave", "vscr", |
809 | /* SPE registers. */ | |
810 | "spe_acc", "spefscr" | |
c81bebd7 MM |
811 | }; |
812 | ||
813 | #ifdef TARGET_REGNAMES | |
8b60264b | 814 | static const char alt_reg_names[][8] = |
c81bebd7 | 815 | { |
802a0058 MM |
816 | "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7", |
817 | "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15", | |
818 | "%r16", "%r17", "%r18", "%r19", "%r20", "%r21", "%r22", "%r23", | |
819 | "%r24", "%r25", "%r26", "%r27", "%r28", "%r29", "%r30", "%r31", | |
820 | "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7", | |
821 | "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15", | |
822 | "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23", | |
823 | "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31", | |
824 | "mq", "lr", "ctr", "ap", | |
825 | "%cr0", "%cr1", "%cr2", "%cr3", "%cr4", "%cr5", "%cr6", "%cr7", | |
0ac081f6 | 826 | "xer", |
59a4c851 | 827 | /* AltiVec registers. */ |
0ac081f6 | 828 | "%v0", "%v1", "%v2", "%v3", "%v4", "%v5", "%v6", "%v7", |
59a4c851 AH |
829 | "%v8", "%v9", "%v10", "%v11", "%v12", "%v13", "%v14", "%v15", |
830 | "%v16", "%v17", "%v18", "%v19", "%v20", "%v21", "%v22", "%v23", | |
831 | "%v24", "%v25", "%v26", "%v27", "%v28", "%v29", "%v30", "%v31", | |
832 | "vrsave", "vscr", | |
833 | /* SPE registers. */ | |
834 | "spe_acc", "spefscr" | |
c81bebd7 MM |
835 | }; |
836 | #endif | |
9878760c | 837 | \f |
daf11973 MM |
838 | #ifndef MASK_STRICT_ALIGN |
839 | #define MASK_STRICT_ALIGN 0 | |
840 | #endif | |
ffcfcb5f AM |
841 | #ifndef TARGET_PROFILE_KERNEL |
842 | #define TARGET_PROFILE_KERNEL 0 | |
843 | #endif | |
3961e8fe RH |
844 | |
845 | /* The VRSAVE bitmask puts bit %v0 as the most significant bit. */ | |
846 | #define ALTIVEC_REG_BIT(REGNO) (0x80000000 >> ((REGNO) - FIRST_ALTIVEC_REGNO)) | |
c4501e62 JJ |
847 | |
848 | /* Return 1 for a symbol ref for a thread-local storage symbol. */ | |
849 | #define RS6000_SYMBOL_REF_TLS_P(RTX) \ | |
850 | (GET_CODE (RTX) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (RTX) != 0) | |
672a6f42 NB |
851 | \f |
852 | /* Initialize the GCC target structure. */ | |
91d231cb JM |
853 | #undef TARGET_ATTRIBUTE_TABLE |
854 | #define TARGET_ATTRIBUTE_TABLE rs6000_attribute_table | |
a5c76ee6 ZW |
855 | #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES |
856 | #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES rs6000_set_default_type_attributes | |
daf11973 | 857 | |
301d03af RS |
858 | #undef TARGET_ASM_ALIGNED_DI_OP |
859 | #define TARGET_ASM_ALIGNED_DI_OP DOUBLE_INT_ASM_OP | |
860 | ||
861 | /* Default unaligned ops are only provided for ELF. Find the ops needed | |
862 | for non-ELF systems. */ | |
863 | #ifndef OBJECT_FORMAT_ELF | |
cbaaba19 | 864 | #if TARGET_XCOFF |
ae6c1efd | 865 | /* For XCOFF. rs6000_assemble_integer will handle unaligned DIs on |
301d03af RS |
866 | 64-bit targets. */ |
867 | #undef TARGET_ASM_UNALIGNED_HI_OP | |
868 | #define TARGET_ASM_UNALIGNED_HI_OP "\t.vbyte\t2," | |
869 | #undef TARGET_ASM_UNALIGNED_SI_OP | |
870 | #define TARGET_ASM_UNALIGNED_SI_OP "\t.vbyte\t4," | |
871 | #undef TARGET_ASM_UNALIGNED_DI_OP | |
872 | #define TARGET_ASM_UNALIGNED_DI_OP "\t.vbyte\t8," | |
873 | #else | |
874 | /* For Darwin. */ | |
875 | #undef TARGET_ASM_UNALIGNED_HI_OP | |
876 | #define TARGET_ASM_UNALIGNED_HI_OP "\t.short\t" | |
877 | #undef TARGET_ASM_UNALIGNED_SI_OP | |
878 | #define TARGET_ASM_UNALIGNED_SI_OP "\t.long\t" | |
49bd1d27 SS |
879 | #undef TARGET_ASM_UNALIGNED_DI_OP |
880 | #define TARGET_ASM_UNALIGNED_DI_OP "\t.quad\t" | |
881 | #undef TARGET_ASM_ALIGNED_DI_OP | |
882 | #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t" | |
301d03af RS |
883 | #endif |
884 | #endif | |
885 | ||
886 | /* This hook deals with fixups for relocatable code and DI-mode objects | |
887 | in 64-bit code. */ | |
888 | #undef TARGET_ASM_INTEGER | |
889 | #define TARGET_ASM_INTEGER rs6000_assemble_integer | |
890 | ||
93638d7a AM |
891 | #ifdef HAVE_GAS_HIDDEN |
892 | #undef TARGET_ASM_ASSEMBLE_VISIBILITY | |
893 | #define TARGET_ASM_ASSEMBLE_VISIBILITY rs6000_assemble_visibility | |
894 | #endif | |
895 | ||
c4501e62 JJ |
896 | #undef TARGET_HAVE_TLS |
897 | #define TARGET_HAVE_TLS HAVE_AS_TLS | |
898 | ||
899 | #undef TARGET_CANNOT_FORCE_CONST_MEM | |
900 | #define TARGET_CANNOT_FORCE_CONST_MEM rs6000_tls_referenced_p | |
901 | ||
08c148a8 NB |
902 | #undef TARGET_ASM_FUNCTION_PROLOGUE |
903 | #define TARGET_ASM_FUNCTION_PROLOGUE rs6000_output_function_prologue | |
904 | #undef TARGET_ASM_FUNCTION_EPILOGUE | |
905 | #define TARGET_ASM_FUNCTION_EPILOGUE rs6000_output_function_epilogue | |
906 | ||
b54cf83a DE |
907 | #undef TARGET_SCHED_VARIABLE_ISSUE |
908 | #define TARGET_SCHED_VARIABLE_ISSUE rs6000_variable_issue | |
909 | ||
c237e94a ZW |
910 | #undef TARGET_SCHED_ISSUE_RATE |
911 | #define TARGET_SCHED_ISSUE_RATE rs6000_issue_rate | |
912 | #undef TARGET_SCHED_ADJUST_COST | |
913 | #define TARGET_SCHED_ADJUST_COST rs6000_adjust_cost | |
914 | #undef TARGET_SCHED_ADJUST_PRIORITY | |
915 | #define TARGET_SCHED_ADJUST_PRIORITY rs6000_adjust_priority | |
f676971a | 916 | #undef TARGET_SCHED_IS_COSTLY_DEPENDENCE |
569fa502 | 917 | #define TARGET_SCHED_IS_COSTLY_DEPENDENCE rs6000_is_costly_dependence |
cbe26ab8 DN |
918 | #undef TARGET_SCHED_FINISH |
919 | #define TARGET_SCHED_FINISH rs6000_sched_finish | |
c237e94a | 920 | |
be12c2b0 VM |
921 | #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD |
922 | #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD rs6000_use_sched_lookahead | |
923 | ||
7ccf35ed DN |
924 | #undef TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD |
925 | #define TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD rs6000_builtin_mask_for_load | |
926 | ||
927 | #undef TARGET_VECTORIZE_BUILTIN_MASK_FOR_STORE | |
928 | #define TARGET_VECTORIZE_BUILTIN_MASK_FOR_STORE rs6000_builtin_mask_for_store | |
929 | ||
0ac081f6 AH |
930 | #undef TARGET_INIT_BUILTINS |
931 | #define TARGET_INIT_BUILTINS rs6000_init_builtins | |
932 | ||
933 | #undef TARGET_EXPAND_BUILTIN | |
934 | #define TARGET_EXPAND_BUILTIN rs6000_expand_builtin | |
935 | ||
f18eca82 ZL |
936 | #undef TARGET_MANGLE_FUNDAMENTAL_TYPE |
937 | #define TARGET_MANGLE_FUNDAMENTAL_TYPE rs6000_mangle_fundamental_type | |
938 | ||
c15c90bb ZW |
939 | #undef TARGET_INIT_LIBFUNCS |
940 | #define TARGET_INIT_LIBFUNCS rs6000_init_libfuncs | |
941 | ||
f1384257 | 942 | #if TARGET_MACHO |
0e5dbd9b DE |
943 | #undef TARGET_BINDS_LOCAL_P |
944 | #define TARGET_BINDS_LOCAL_P rs6000_binds_local_p | |
f1384257 | 945 | #endif |
0e5dbd9b | 946 | |
3961e8fe RH |
947 | #undef TARGET_ASM_OUTPUT_MI_THUNK |
948 | #define TARGET_ASM_OUTPUT_MI_THUNK rs6000_output_mi_thunk | |
949 | ||
3961e8fe | 950 | #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK |
5b71a4e7 | 951 | #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_tree_hwi_hwi_tree_true |
00b960c7 | 952 | |
4977bab6 ZW |
953 | #undef TARGET_FUNCTION_OK_FOR_SIBCALL |
954 | #define TARGET_FUNCTION_OK_FOR_SIBCALL rs6000_function_ok_for_sibcall | |
955 | ||
3c50106f RH |
956 | #undef TARGET_RTX_COSTS |
957 | #define TARGET_RTX_COSTS rs6000_rtx_costs | |
dcefdf67 RH |
958 | #undef TARGET_ADDRESS_COST |
959 | #define TARGET_ADDRESS_COST hook_int_rtx_0 | |
3c50106f | 960 | |
c8e4f0e9 AH |
961 | #undef TARGET_VECTOR_OPAQUE_P |
962 | #define TARGET_VECTOR_OPAQUE_P is_ev64_opaque_type | |
62e1dfcf | 963 | |
96714395 AH |
964 | #undef TARGET_DWARF_REGISTER_SPAN |
965 | #define TARGET_DWARF_REGISTER_SPAN rs6000_dwarf_register_span | |
966 | ||
c6e8c921 GK |
967 | /* On rs6000, function arguments are promoted, as are function return |
968 | values. */ | |
969 | #undef TARGET_PROMOTE_FUNCTION_ARGS | |
970 | #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true | |
971 | #undef TARGET_PROMOTE_FUNCTION_RETURN | |
972 | #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true | |
973 | ||
c6e8c921 GK |
974 | #undef TARGET_RETURN_IN_MEMORY |
975 | #define TARGET_RETURN_IN_MEMORY rs6000_return_in_memory | |
976 | ||
977 | #undef TARGET_SETUP_INCOMING_VARARGS | |
978 | #define TARGET_SETUP_INCOMING_VARARGS setup_incoming_varargs | |
979 | ||
980 | /* Always strict argument naming on rs6000. */ | |
981 | #undef TARGET_STRICT_ARGUMENT_NAMING | |
982 | #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true | |
983 | #undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED | |
984 | #define TARGET_PRETEND_OUTGOING_VARARGS_NAMED hook_bool_CUMULATIVE_ARGS_true | |
42ba5130 RH |
985 | #undef TARGET_SPLIT_COMPLEX_ARG |
986 | #define TARGET_SPLIT_COMPLEX_ARG hook_bool_tree_true | |
fe984136 RH |
987 | #undef TARGET_MUST_PASS_IN_STACK |
988 | #define TARGET_MUST_PASS_IN_STACK rs6000_must_pass_in_stack | |
8cd5a4e0 RH |
989 | #undef TARGET_PASS_BY_REFERENCE |
990 | #define TARGET_PASS_BY_REFERENCE rs6000_pass_by_reference | |
c6e8c921 | 991 | |
c35d187f RH |
992 | #undef TARGET_BUILD_BUILTIN_VA_LIST |
993 | #define TARGET_BUILD_BUILTIN_VA_LIST rs6000_build_builtin_va_list | |
994 | ||
cd3ce9b4 JM |
995 | #undef TARGET_GIMPLIFY_VA_ARG_EXPR |
996 | #define TARGET_GIMPLIFY_VA_ARG_EXPR rs6000_gimplify_va_arg | |
997 | ||
93f90be6 FJ |
998 | #undef TARGET_EH_RETURN_FILTER_MODE |
999 | #define TARGET_EH_RETURN_FILTER_MODE rs6000_eh_return_filter_mode | |
1000 | ||
f676971a EC |
1001 | #undef TARGET_VECTOR_MODE_SUPPORTED_P |
1002 | #define TARGET_VECTOR_MODE_SUPPORTED_P rs6000_vector_mode_supported_p | |
1003 | ||
f6897b10 | 1004 | struct gcc_target targetm = TARGET_INITIALIZER; |
672a6f42 | 1005 | \f |
0d1fbc8c AH |
1006 | |
1007 | /* Value is 1 if hard register REGNO can hold a value of machine-mode | |
1008 | MODE. */ | |
1009 | static int | |
1010 | rs6000_hard_regno_mode_ok (int regno, enum machine_mode mode) | |
1011 | { | |
1012 | /* The GPRs can hold any mode, but values bigger than one register | |
1013 | cannot go past R31. */ | |
1014 | if (INT_REGNO_P (regno)) | |
1015 | return INT_REGNO_P (regno + HARD_REGNO_NREGS (regno, mode) - 1); | |
1016 | ||
1017 | /* The float registers can only hold floating modes and DImode. */ | |
1018 | if (FP_REGNO_P (regno)) | |
1019 | return | |
1020 | (GET_MODE_CLASS (mode) == MODE_FLOAT | |
1021 | && FP_REGNO_P (regno + HARD_REGNO_NREGS (regno, mode) - 1)) | |
1022 | || (GET_MODE_CLASS (mode) == MODE_INT | |
1023 | && GET_MODE_SIZE (mode) == UNITS_PER_FP_WORD); | |
1024 | ||
1025 | /* The CR register can only hold CC modes. */ | |
1026 | if (CR_REGNO_P (regno)) | |
1027 | return GET_MODE_CLASS (mode) == MODE_CC; | |
1028 | ||
1029 | if (XER_REGNO_P (regno)) | |
1030 | return mode == PSImode; | |
1031 | ||
1032 | /* AltiVec only in AldyVec registers. */ | |
1033 | if (ALTIVEC_REGNO_P (regno)) | |
1034 | return ALTIVEC_VECTOR_MODE (mode); | |
1035 | ||
1036 | /* ...but GPRs can hold SIMD data on the SPE in one register. */ | |
1037 | if (SPE_SIMD_REGNO_P (regno) && TARGET_SPE && SPE_VECTOR_MODE (mode)) | |
1038 | return 1; | |
1039 | ||
1040 | /* We cannot put TImode anywhere except general register and it must be | |
1041 | able to fit within the register set. */ | |
1042 | ||
1043 | return GET_MODE_SIZE (mode) <= UNITS_PER_WORD; | |
1044 | } | |
1045 | ||
1046 | /* Initialize rs6000_hard_regno_mode_ok_p table. */ | |
1047 | static void | |
1048 | rs6000_init_hard_regno_mode_ok (void) | |
1049 | { | |
1050 | int r, m; | |
1051 | ||
1052 | for (r = 0; r < FIRST_PSEUDO_REGISTER; ++r) | |
1053 | for (m = 0; m < NUM_MACHINE_MODES; ++m) | |
1054 | if (rs6000_hard_regno_mode_ok (r, m)) | |
1055 | rs6000_hard_regno_mode_ok_p[m][r] = true; | |
1056 | } | |
1057 | ||
c1e55850 GK |
1058 | /* If not otherwise specified by a target, make 'long double' equivalent to |
1059 | 'double'. */ | |
1060 | ||
1061 | #ifndef RS6000_DEFAULT_LONG_DOUBLE_SIZE | |
1062 | #define RS6000_DEFAULT_LONG_DOUBLE_SIZE 64 | |
1063 | #endif | |
1064 | ||
5248c961 RK |
1065 | /* Override command line options. Mostly we process the processor |
1066 | type and sometimes adjust other TARGET_ options. */ | |
1067 | ||
1068 | void | |
d779d0dc | 1069 | rs6000_override_options (const char *default_cpu) |
5248c961 | 1070 | { |
c4d38ccb | 1071 | size_t i, j; |
8e3f41e7 | 1072 | struct rs6000_cpu_select *ptr; |
66188a7e | 1073 | int set_masks; |
5248c961 | 1074 | |
66188a7e | 1075 | /* Simplifications for entries below. */ |
85638c0d | 1076 | |
66188a7e GK |
1077 | enum { |
1078 | POWERPC_BASE_MASK = MASK_POWERPC | MASK_NEW_MNEMONICS, | |
1079 | POWERPC_7400_MASK = POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_ALTIVEC | |
1080 | }; | |
85638c0d | 1081 | |
66188a7e GK |
1082 | /* This table occasionally claims that a processor does not support |
1083 | a particular feature even though it does, but the feature is slower | |
1084 | than the alternative. Thus, it shouldn't be relied on as a | |
f676971a | 1085 | complete description of the processor's support. |
66188a7e GK |
1086 | |
1087 | Please keep this list in order, and don't forget to update the | |
1088 | documentation in invoke.texi when adding a new processor or | |
1089 | flag. */ | |
5248c961 RK |
1090 | static struct ptt |
1091 | { | |
8b60264b KG |
1092 | const char *const name; /* Canonical processor name. */ |
1093 | const enum processor_type processor; /* Processor type enum value. */ | |
1094 | const int target_enable; /* Target flags to enable. */ | |
8b60264b | 1095 | } const processor_target_table[] |
66188a7e | 1096 | = {{"401", PROCESSOR_PPC403, POWERPC_BASE_MASK | MASK_SOFT_FLOAT}, |
49a0b204 | 1097 | {"403", PROCESSOR_PPC403, |
66188a7e GK |
1098 | POWERPC_BASE_MASK | MASK_SOFT_FLOAT | MASK_STRICT_ALIGN}, |
1099 | {"405", PROCESSOR_PPC405, POWERPC_BASE_MASK | MASK_SOFT_FLOAT}, | |
1100 | {"405fp", PROCESSOR_PPC405, POWERPC_BASE_MASK}, | |
1101 | {"440", PROCESSOR_PPC440, POWERPC_BASE_MASK | MASK_SOFT_FLOAT}, | |
1102 | {"440fp", PROCESSOR_PPC440, POWERPC_BASE_MASK}, | |
1103 | {"505", PROCESSOR_MPCCORE, POWERPC_BASE_MASK}, | |
5248c961 | 1104 | {"601", PROCESSOR_PPC601, |
66188a7e GK |
1105 | MASK_POWER | POWERPC_BASE_MASK | MASK_MULTIPLE | MASK_STRING}, |
1106 | {"602", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT}, | |
1107 | {"603", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT}, | |
1108 | {"603e", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT}, | |
1109 | {"604", PROCESSOR_PPC604, POWERPC_BASE_MASK | MASK_PPC_GFXOPT}, | |
1110 | {"604e", PROCESSOR_PPC604e, POWERPC_BASE_MASK | MASK_PPC_GFXOPT}, | |
7ddb6568 AM |
1111 | {"620", PROCESSOR_PPC620, |
1112 | POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64}, | |
1113 | {"630", PROCESSOR_PPC630, | |
1114 | POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64}, | |
66188a7e GK |
1115 | {"740", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT}, |
1116 | {"7400", PROCESSOR_PPC7400, POWERPC_7400_MASK}, | |
1117 | {"7450", PROCESSOR_PPC7450, POWERPC_7400_MASK}, | |
1118 | {"750", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT}, | |
1119 | {"801", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT}, | |
1120 | {"821", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT}, | |
1121 | {"823", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT}, | |
1122 | {"8540", PROCESSOR_PPC8540, POWERPC_BASE_MASK | MASK_PPC_GFXOPT}, | |
4d4cbc0e AH |
1123 | /* 8548 has a dummy entry for now. */ |
1124 | {"8548", PROCESSOR_PPC8540, POWERPC_BASE_MASK | MASK_PPC_GFXOPT}, | |
66188a7e | 1125 | {"860", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT}, |
7177e720 | 1126 | {"970", PROCESSOR_POWER4, |
66188a7e GK |
1127 | POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64}, |
1128 | {"common", PROCESSOR_COMMON, MASK_NEW_MNEMONICS}, | |
1129 | {"ec603e", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_SOFT_FLOAT}, | |
1130 | {"G3", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT}, | |
1131 | {"G4", PROCESSOR_PPC7450, POWERPC_7400_MASK}, | |
49ffe578 | 1132 | {"G5", PROCESSOR_POWER4, |
66188a7e GK |
1133 | POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64}, |
1134 | {"power", PROCESSOR_POWER, MASK_POWER | MASK_MULTIPLE | MASK_STRING}, | |
1135 | {"power2", PROCESSOR_POWER, | |
1136 | MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING}, | |
7ddb6568 AM |
1137 | {"power3", PROCESSOR_PPC630, |
1138 | POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64}, | |
1139 | {"power4", PROCESSOR_POWER4, | |
fc091c8e | 1140 | POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POWERPC64}, |
ec507f2d | 1141 | {"power5", PROCESSOR_POWER5, |
fc091c8e | 1142 | POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POWERPC64}, |
66188a7e GK |
1143 | {"powerpc", PROCESSOR_POWERPC, POWERPC_BASE_MASK}, |
1144 | {"powerpc64", PROCESSOR_POWERPC64, | |
1145 | POWERPC_BASE_MASK | MASK_POWERPC64}, | |
1146 | {"rios", PROCESSOR_RIOS1, MASK_POWER | MASK_MULTIPLE | MASK_STRING}, | |
1147 | {"rios1", PROCESSOR_RIOS1, MASK_POWER | MASK_MULTIPLE | MASK_STRING}, | |
1148 | {"rios2", PROCESSOR_RIOS2, | |
1149 | MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING}, | |
1150 | {"rsc", PROCESSOR_PPC601, MASK_POWER | MASK_MULTIPLE | MASK_STRING}, | |
1151 | {"rsc1", PROCESSOR_PPC601, MASK_POWER | MASK_MULTIPLE | MASK_STRING}, | |
7ddb6568 | 1152 | {"rs64a", PROCESSOR_RS64A, POWERPC_BASE_MASK | MASK_POWERPC64}, |
66188a7e | 1153 | }; |
5248c961 | 1154 | |
ca7558fc | 1155 | const size_t ptt_size = ARRAY_SIZE (processor_target_table); |
5248c961 | 1156 | |
66188a7e GK |
1157 | /* Some OSs don't support saving the high part of 64-bit registers on |
1158 | context switch. Other OSs don't support saving Altivec registers. | |
1159 | On those OSs, we don't touch the MASK_POWERPC64 or MASK_ALTIVEC | |
1160 | settings; if the user wants either, the user must explicitly specify | |
1161 | them and we won't interfere with the user's specification. */ | |
1162 | ||
1163 | enum { | |
1164 | POWER_MASKS = MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING, | |
f676971a | 1165 | POWERPC_MASKS = (POWERPC_BASE_MASK | MASK_PPC_GPOPT |
66188a7e GK |
1166 | | MASK_PPC_GFXOPT | MASK_POWERPC64 | MASK_ALTIVEC |
1167 | | MASK_MFCRF) | |
1168 | }; | |
0d1fbc8c AH |
1169 | |
1170 | rs6000_init_hard_regno_mode_ok (); | |
1171 | ||
c4ad648e | 1172 | set_masks = POWER_MASKS | POWERPC_MASKS | MASK_SOFT_FLOAT; |
66188a7e GK |
1173 | #ifdef OS_MISSING_POWERPC64 |
1174 | if (OS_MISSING_POWERPC64) | |
1175 | set_masks &= ~MASK_POWERPC64; | |
1176 | #endif | |
1177 | #ifdef OS_MISSING_ALTIVEC | |
1178 | if (OS_MISSING_ALTIVEC) | |
1179 | set_masks &= ~MASK_ALTIVEC; | |
1180 | #endif | |
1181 | ||
957211c3 AM |
1182 | /* Don't override these by the processor default if given explicitly. */ |
1183 | set_masks &= ~(target_flags_explicit | |
1184 | & (MASK_MULTIPLE | MASK_STRING | MASK_SOFT_FLOAT)); | |
1185 | ||
a4f6c312 | 1186 | /* Identify the processor type. */ |
8e3f41e7 | 1187 | rs6000_select[0].string = default_cpu; |
3cb999d8 | 1188 | rs6000_cpu = TARGET_POWERPC64 ? PROCESSOR_DEFAULT64 : PROCESSOR_DEFAULT; |
8e3f41e7 | 1189 | |
b6a1cbae | 1190 | for (i = 0; i < ARRAY_SIZE (rs6000_select); i++) |
5248c961 | 1191 | { |
8e3f41e7 MM |
1192 | ptr = &rs6000_select[i]; |
1193 | if (ptr->string != (char *)0 && ptr->string[0] != '\0') | |
5248c961 | 1194 | { |
8e3f41e7 MM |
1195 | for (j = 0; j < ptt_size; j++) |
1196 | if (! strcmp (ptr->string, processor_target_table[j].name)) | |
1197 | { | |
1198 | if (ptr->set_tune_p) | |
1199 | rs6000_cpu = processor_target_table[j].processor; | |
1200 | ||
1201 | if (ptr->set_arch_p) | |
1202 | { | |
66188a7e GK |
1203 | target_flags &= ~set_masks; |
1204 | target_flags |= (processor_target_table[j].target_enable | |
1205 | & set_masks); | |
8e3f41e7 MM |
1206 | } |
1207 | break; | |
1208 | } | |
1209 | ||
4406229e | 1210 | if (j == ptt_size) |
8e3f41e7 | 1211 | error ("bad value (%s) for %s switch", ptr->string, ptr->name); |
5248c961 RK |
1212 | } |
1213 | } | |
8a61d227 | 1214 | |
993f19a8 | 1215 | if (TARGET_E500) |
a3170dc6 AH |
1216 | rs6000_isel = 1; |
1217 | ||
dff9f1b6 DE |
1218 | /* If we are optimizing big endian systems for space, use the load/store |
1219 | multiple and string instructions. */ | |
ef792183 | 1220 | if (BYTES_BIG_ENDIAN && optimize_size) |
957211c3 | 1221 | target_flags |= ~target_flags_explicit & (MASK_MULTIPLE | MASK_STRING); |
938937d8 | 1222 | |
a4f6c312 SS |
1223 | /* Don't allow -mmultiple or -mstring on little endian systems |
1224 | unless the cpu is a 750, because the hardware doesn't support the | |
1225 | instructions used in little endian mode, and causes an alignment | |
1226 | trap. The 750 does not cause an alignment trap (except when the | |
1227 | target is unaligned). */ | |
bef84347 | 1228 | |
b21fb038 | 1229 | if (!BYTES_BIG_ENDIAN && rs6000_cpu != PROCESSOR_PPC750) |
7e69e155 MM |
1230 | { |
1231 | if (TARGET_MULTIPLE) | |
1232 | { | |
1233 | target_flags &= ~MASK_MULTIPLE; | |
b21fb038 | 1234 | if ((target_flags_explicit & MASK_MULTIPLE) != 0) |
7e69e155 MM |
1235 | warning ("-mmultiple is not supported on little endian systems"); |
1236 | } | |
1237 | ||
1238 | if (TARGET_STRING) | |
1239 | { | |
1240 | target_flags &= ~MASK_STRING; | |
b21fb038 | 1241 | if ((target_flags_explicit & MASK_STRING) != 0) |
938937d8 | 1242 | warning ("-mstring is not supported on little endian systems"); |
7e69e155 MM |
1243 | } |
1244 | } | |
3933e0e1 | 1245 | |
38c1f2d7 MM |
1246 | /* Set debug flags */ |
1247 | if (rs6000_debug_name) | |
1248 | { | |
bfc79d3b | 1249 | if (! strcmp (rs6000_debug_name, "all")) |
38c1f2d7 | 1250 | rs6000_debug_stack = rs6000_debug_arg = 1; |
bfc79d3b | 1251 | else if (! strcmp (rs6000_debug_name, "stack")) |
38c1f2d7 | 1252 | rs6000_debug_stack = 1; |
bfc79d3b | 1253 | else if (! strcmp (rs6000_debug_name, "arg")) |
38c1f2d7 MM |
1254 | rs6000_debug_arg = 1; |
1255 | else | |
c725bd79 | 1256 | error ("unknown -mdebug-%s switch", rs6000_debug_name); |
38c1f2d7 MM |
1257 | } |
1258 | ||
57ac7be9 AM |
1259 | if (rs6000_traceback_name) |
1260 | { | |
1261 | if (! strncmp (rs6000_traceback_name, "full", 4)) | |
1262 | rs6000_traceback = traceback_full; | |
1263 | else if (! strncmp (rs6000_traceback_name, "part", 4)) | |
1264 | rs6000_traceback = traceback_part; | |
1265 | else if (! strncmp (rs6000_traceback_name, "no", 2)) | |
1266 | rs6000_traceback = traceback_none; | |
1267 | else | |
1268 | error ("unknown -mtraceback arg `%s'; expecting `full', `partial' or `none'", | |
1269 | rs6000_traceback_name); | |
1270 | } | |
1271 | ||
6fa3f289 | 1272 | /* Set size of long double */ |
c1e55850 | 1273 | rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE; |
6fa3f289 ZW |
1274 | if (rs6000_long_double_size_string) |
1275 | { | |
1276 | char *tail; | |
1277 | int size = strtol (rs6000_long_double_size_string, &tail, 10); | |
1278 | if (*tail != '\0' || (size != 64 && size != 128)) | |
1279 | error ("Unknown switch -mlong-double-%s", | |
1280 | rs6000_long_double_size_string); | |
1281 | else | |
1282 | rs6000_long_double_type_size = size; | |
1283 | } | |
1284 | ||
6d0ef01e HP |
1285 | /* Set Altivec ABI as default for powerpc64 linux. */ |
1286 | if (TARGET_ELF && TARGET_64BIT) | |
1287 | { | |
1288 | rs6000_altivec_abi = 1; | |
1289 | rs6000_altivec_vrsave = 1; | |
1290 | } | |
1291 | ||
0ac081f6 AH |
1292 | /* Handle -mabi= options. */ |
1293 | rs6000_parse_abi_options (); | |
1294 | ||
025d9908 KH |
1295 | /* Handle -malign-XXXXX option. */ |
1296 | rs6000_parse_alignment_option (); | |
1297 | ||
4d4cbc0e AH |
1298 | rs6000_parse_float_gprs_option (); |
1299 | ||
5da702b1 AH |
1300 | /* Handle generic -mFOO=YES/NO options. */ |
1301 | rs6000_parse_yes_no_option ("vrsave", rs6000_altivec_vrsave_string, | |
1302 | &rs6000_altivec_vrsave); | |
1303 | rs6000_parse_yes_no_option ("isel", rs6000_isel_string, | |
1304 | &rs6000_isel); | |
1305 | rs6000_parse_yes_no_option ("spe", rs6000_spe_string, &rs6000_spe); | |
993f19a8 | 1306 | |
c4501e62 JJ |
1307 | /* Handle -mtls-size option. */ |
1308 | rs6000_parse_tls_size_option (); | |
1309 | ||
a7ae18e2 AH |
1310 | #ifdef SUBTARGET_OVERRIDE_OPTIONS |
1311 | SUBTARGET_OVERRIDE_OPTIONS; | |
1312 | #endif | |
1313 | #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS | |
1314 | SUBSUBTARGET_OVERRIDE_OPTIONS; | |
1315 | #endif | |
4d4cbc0e AH |
1316 | #ifdef SUB3TARGET_OVERRIDE_OPTIONS |
1317 | SUB3TARGET_OVERRIDE_OPTIONS; | |
1318 | #endif | |
a7ae18e2 | 1319 | |
5da702b1 AH |
1320 | if (TARGET_E500) |
1321 | { | |
e4463bf1 AH |
1322 | if (TARGET_ALTIVEC) |
1323 | error ("AltiVec and E500 instructions cannot coexist"); | |
1324 | ||
5da702b1 AH |
1325 | /* The e500 does not have string instructions, and we set |
1326 | MASK_STRING above when optimizing for size. */ | |
1327 | if ((target_flags & MASK_STRING) != 0) | |
1328 | target_flags = target_flags & ~MASK_STRING; | |
b6e59a3a AH |
1329 | |
1330 | /* No SPE means 64-bit long doubles, even if an E500. */ | |
1331 | if (rs6000_spe_string != 0 | |
c4ad648e | 1332 | && !strcmp (rs6000_spe_string, "no")) |
b6e59a3a | 1333 | rs6000_long_double_type_size = 64; |
5da702b1 AH |
1334 | } |
1335 | else if (rs6000_select[1].string != NULL) | |
1336 | { | |
1337 | /* For the powerpc-eabispe configuration, we set all these by | |
1338 | default, so let's unset them if we manually set another | |
1339 | CPU that is not the E500. */ | |
1340 | if (rs6000_abi_string == 0) | |
1341 | rs6000_spe_abi = 0; | |
1342 | if (rs6000_spe_string == 0) | |
1343 | rs6000_spe = 0; | |
1344 | if (rs6000_float_gprs_string == 0) | |
1345 | rs6000_float_gprs = 0; | |
1346 | if (rs6000_isel_string == 0) | |
1347 | rs6000_isel = 0; | |
b6e59a3a | 1348 | if (rs6000_long_double_size_string == 0) |
c1e55850 | 1349 | rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE; |
5da702b1 | 1350 | } |
b5044283 | 1351 | |
ec507f2d DE |
1352 | rs6000_always_hint = (rs6000_cpu != PROCESSOR_POWER4 |
1353 | && rs6000_cpu != PROCESSOR_POWER5); | |
1354 | rs6000_sched_groups = (rs6000_cpu == PROCESSOR_POWER4 | |
1355 | || rs6000_cpu == PROCESSOR_POWER5); | |
1356 | ||
a5c76ee6 ZW |
1357 | /* Handle -m(no-)longcall option. This is a bit of a cheap hack, |
1358 | using TARGET_OPTIONS to handle a toggle switch, but we're out of | |
1359 | bits in target_flags so TARGET_SWITCHES cannot be used. | |
1360 | Assumption here is that rs6000_longcall_switch points into the | |
1361 | text of the complete option, rather than being a copy, so we can | |
1362 | scan back for the presence or absence of the no- modifier. */ | |
1363 | if (rs6000_longcall_switch) | |
1364 | { | |
1365 | const char *base = rs6000_longcall_switch; | |
1366 | while (base[-1] != 'm') base--; | |
1367 | ||
1368 | if (*rs6000_longcall_switch != '\0') | |
1369 | error ("invalid option `%s'", base); | |
1370 | rs6000_default_long_calls = (base[0] != 'n'); | |
1371 | } | |
1372 | ||
8bb418a3 ZL |
1373 | /* Handle -m(no-)warn-altivec-long similarly. */ |
1374 | if (rs6000_warn_altivec_long_switch) | |
1375 | { | |
1376 | const char *base = rs6000_warn_altivec_long_switch; | |
1377 | while (base[-1] != 'm') base--; | |
1378 | ||
1379 | if (*rs6000_warn_altivec_long_switch != '\0') | |
1380 | error ("invalid option `%s'", base); | |
1381 | rs6000_warn_altivec_long = (base[0] != 'n'); | |
1382 | } | |
1383 | ||
cbe26ab8 | 1384 | /* Handle -mprioritize-restricted-insns option. */ |
ec507f2d DE |
1385 | rs6000_sched_restricted_insns_priority |
1386 | = (rs6000_sched_groups ? 1 : 0); | |
79ae11c4 DN |
1387 | if (rs6000_sched_restricted_insns_priority_str) |
1388 | rs6000_sched_restricted_insns_priority = | |
1389 | atoi (rs6000_sched_restricted_insns_priority_str); | |
1390 | ||
569fa502 | 1391 | /* Handle -msched-costly-dep option. */ |
ec507f2d DE |
1392 | rs6000_sched_costly_dep |
1393 | = (rs6000_sched_groups ? store_to_load_dep_costly : no_dep_costly); | |
569fa502 DN |
1394 | if (rs6000_sched_costly_dep_str) |
1395 | { | |
f676971a | 1396 | if (! strcmp (rs6000_sched_costly_dep_str, "no")) |
c4ad648e | 1397 | rs6000_sched_costly_dep = no_dep_costly; |
569fa502 | 1398 | else if (! strcmp (rs6000_sched_costly_dep_str, "all")) |
c4ad648e | 1399 | rs6000_sched_costly_dep = all_deps_costly; |
569fa502 | 1400 | else if (! strcmp (rs6000_sched_costly_dep_str, "true_store_to_load")) |
c4ad648e | 1401 | rs6000_sched_costly_dep = true_store_to_load_dep_costly; |
569fa502 | 1402 | else if (! strcmp (rs6000_sched_costly_dep_str, "store_to_load")) |
c4ad648e | 1403 | rs6000_sched_costly_dep = store_to_load_dep_costly; |
f676971a | 1404 | else |
c4ad648e | 1405 | rs6000_sched_costly_dep = atoi (rs6000_sched_costly_dep_str); |
cbe26ab8 DN |
1406 | } |
1407 | ||
1408 | /* Handle -minsert-sched-nops option. */ | |
ec507f2d DE |
1409 | rs6000_sched_insert_nops |
1410 | = (rs6000_sched_groups ? sched_finish_regroup_exact : sched_finish_none); | |
cbe26ab8 DN |
1411 | if (rs6000_sched_insert_nops_str) |
1412 | { | |
1413 | if (! strcmp (rs6000_sched_insert_nops_str, "no")) | |
c4ad648e | 1414 | rs6000_sched_insert_nops = sched_finish_none; |
cbe26ab8 | 1415 | else if (! strcmp (rs6000_sched_insert_nops_str, "pad")) |
c4ad648e | 1416 | rs6000_sched_insert_nops = sched_finish_pad_groups; |
cbe26ab8 | 1417 | else if (! strcmp (rs6000_sched_insert_nops_str, "regroup_exact")) |
c4ad648e | 1418 | rs6000_sched_insert_nops = sched_finish_regroup_exact; |
cbe26ab8 | 1419 | else |
c4ad648e | 1420 | rs6000_sched_insert_nops = atoi (rs6000_sched_insert_nops_str); |
569fa502 DN |
1421 | } |
1422 | ||
c81bebd7 | 1423 | #ifdef TARGET_REGNAMES |
a4f6c312 SS |
1424 | /* If the user desires alternate register names, copy in the |
1425 | alternate names now. */ | |
c81bebd7 | 1426 | if (TARGET_REGNAMES) |
4e135bdd | 1427 | memcpy (rs6000_reg_names, alt_reg_names, sizeof (rs6000_reg_names)); |
c81bebd7 MM |
1428 | #endif |
1429 | ||
6fa3f289 ZW |
1430 | /* Set TARGET_AIX_STRUCT_RET last, after the ABI is determined. |
1431 | If -maix-struct-return or -msvr4-struct-return was explicitly | |
1432 | used, don't override with the ABI default. */ | |
b21fb038 | 1433 | if ((target_flags_explicit & MASK_AIX_STRUCT_RET) == 0) |
6fa3f289 ZW |
1434 | { |
1435 | if (DEFAULT_ABI == ABI_V4 && !DRAFT_V4_STRUCT_RET) | |
1436 | target_flags = (target_flags & ~MASK_AIX_STRUCT_RET); | |
1437 | else | |
1438 | target_flags |= MASK_AIX_STRUCT_RET; | |
1439 | } | |
1440 | ||
fcce224d DE |
1441 | if (TARGET_LONG_DOUBLE_128 |
1442 | && (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)) | |
70a01792 | 1443 | REAL_MODE_FORMAT (TFmode) = &ibm_extended_format; |
fcce224d | 1444 | |
9ebbca7d GK |
1445 | /* Allocate an alias set for register saves & restores from stack. */ |
1446 | rs6000_sr_alias_set = new_alias_set (); | |
1447 | ||
f676971a | 1448 | if (TARGET_TOC) |
9ebbca7d | 1449 | ASM_GENERATE_INTERNAL_LABEL (toc_label_name, "LCTOC", 1); |
71f123ca | 1450 | |
301d03af RS |
1451 | /* We can only guarantee the availability of DI pseudo-ops when |
1452 | assembling for 64-bit targets. */ | |
ae6c1efd | 1453 | if (!TARGET_64BIT) |
301d03af RS |
1454 | { |
1455 | targetm.asm_out.aligned_op.di = NULL; | |
1456 | targetm.asm_out.unaligned_op.di = NULL; | |
1457 | } | |
1458 | ||
1494c534 DE |
1459 | /* Set branch target alignment, if not optimizing for size. */ |
1460 | if (!optimize_size) | |
1461 | { | |
1462 | if (rs6000_sched_groups) | |
1463 | { | |
1464 | if (align_functions <= 0) | |
1465 | align_functions = 16; | |
1466 | if (align_jumps <= 0) | |
1467 | align_jumps = 16; | |
1468 | if (align_loops <= 0) | |
1469 | align_loops = 16; | |
1470 | } | |
1471 | if (align_jumps_max_skip <= 0) | |
1472 | align_jumps_max_skip = 15; | |
1473 | if (align_loops_max_skip <= 0) | |
1474 | align_loops_max_skip = 15; | |
1475 | } | |
2792d578 | 1476 | |
71f123ca FS |
1477 | /* Arrange to save and restore machine status around nested functions. */ |
1478 | init_machine_status = rs6000_init_machine_status; | |
42ba5130 RH |
1479 | |
1480 | /* We should always be splitting complex arguments, but we can't break | |
1481 | Linux and Darwin ABIs at the moment. For now, only AIX is fixed. */ | |
1482 | if (DEFAULT_ABI != ABI_AIX) | |
1483 | targetm.calls.split_complex_arg = NULL; | |
8b897cfa RS |
1484 | |
1485 | /* Initialize rs6000_cost with the appropriate target costs. */ | |
1486 | if (optimize_size) | |
1487 | rs6000_cost = TARGET_POWERPC64 ? &size64_cost : &size32_cost; | |
1488 | else | |
1489 | switch (rs6000_cpu) | |
1490 | { | |
1491 | case PROCESSOR_RIOS1: | |
1492 | rs6000_cost = &rios1_cost; | |
1493 | break; | |
1494 | ||
1495 | case PROCESSOR_RIOS2: | |
1496 | rs6000_cost = &rios2_cost; | |
1497 | break; | |
1498 | ||
1499 | case PROCESSOR_RS64A: | |
1500 | rs6000_cost = &rs64a_cost; | |
1501 | break; | |
1502 | ||
1503 | case PROCESSOR_MPCCORE: | |
1504 | rs6000_cost = &mpccore_cost; | |
1505 | break; | |
1506 | ||
1507 | case PROCESSOR_PPC403: | |
1508 | rs6000_cost = &ppc403_cost; | |
1509 | break; | |
1510 | ||
1511 | case PROCESSOR_PPC405: | |
1512 | rs6000_cost = &ppc405_cost; | |
1513 | break; | |
1514 | ||
1515 | case PROCESSOR_PPC440: | |
1516 | rs6000_cost = &ppc440_cost; | |
1517 | break; | |
1518 | ||
1519 | case PROCESSOR_PPC601: | |
1520 | rs6000_cost = &ppc601_cost; | |
1521 | break; | |
1522 | ||
1523 | case PROCESSOR_PPC603: | |
1524 | rs6000_cost = &ppc603_cost; | |
1525 | break; | |
1526 | ||
1527 | case PROCESSOR_PPC604: | |
1528 | rs6000_cost = &ppc604_cost; | |
1529 | break; | |
1530 | ||
1531 | case PROCESSOR_PPC604e: | |
1532 | rs6000_cost = &ppc604e_cost; | |
1533 | break; | |
1534 | ||
1535 | case PROCESSOR_PPC620: | |
8b897cfa RS |
1536 | rs6000_cost = &ppc620_cost; |
1537 | break; | |
1538 | ||
f0517163 RS |
1539 | case PROCESSOR_PPC630: |
1540 | rs6000_cost = &ppc630_cost; | |
1541 | break; | |
1542 | ||
8b897cfa RS |
1543 | case PROCESSOR_PPC750: |
1544 | case PROCESSOR_PPC7400: | |
1545 | rs6000_cost = &ppc750_cost; | |
1546 | break; | |
1547 | ||
1548 | case PROCESSOR_PPC7450: | |
1549 | rs6000_cost = &ppc7450_cost; | |
1550 | break; | |
1551 | ||
1552 | case PROCESSOR_PPC8540: | |
1553 | rs6000_cost = &ppc8540_cost; | |
1554 | break; | |
1555 | ||
1556 | case PROCESSOR_POWER4: | |
1557 | case PROCESSOR_POWER5: | |
1558 | rs6000_cost = &power4_cost; | |
1559 | break; | |
1560 | ||
1561 | default: | |
1562 | abort (); | |
1563 | } | |
5248c961 | 1564 | } |
5accd822 | 1565 | |
7ccf35ed DN |
1566 | /* Implement targetm.vectorize.builtin_mask_for_load. */ |
1567 | static tree | |
1568 | rs6000_builtin_mask_for_load (void) | |
1569 | { | |
1570 | if (TARGET_ALTIVEC) | |
1571 | return altivec_builtin_mask_for_load; | |
1572 | else | |
1573 | return 0; | |
1574 | } | |
1575 | ||
1576 | /* Implement targetm.vectorize.builtin_mask_for_store. */ | |
1577 | static tree | |
1578 | rs6000_builtin_mask_for_store (void) | |
1579 | { | |
1580 | if (TARGET_ALTIVEC) | |
1581 | return altivec_builtin_mask_for_store; | |
1582 | else | |
1583 | return 0; | |
1584 | } | |
1585 | ||
5da702b1 AH |
1586 | /* Handle generic options of the form -mfoo=yes/no. |
1587 | NAME is the option name. | |
1588 | VALUE is the option value. | |
1589 | FLAG is the pointer to the flag where to store a 1 or 0, depending on | |
1590 | whether the option value is 'yes' or 'no' respectively. */ | |
993f19a8 | 1591 | static void |
5da702b1 | 1592 | rs6000_parse_yes_no_option (const char *name, const char *value, int *flag) |
993f19a8 | 1593 | { |
5da702b1 | 1594 | if (value == 0) |
993f19a8 | 1595 | return; |
5da702b1 AH |
1596 | else if (!strcmp (value, "yes")) |
1597 | *flag = 1; | |
1598 | else if (!strcmp (value, "no")) | |
1599 | *flag = 0; | |
08b57fb3 | 1600 | else |
5da702b1 | 1601 | error ("unknown -m%s= option specified: '%s'", name, value); |
08b57fb3 AH |
1602 | } |
1603 | ||
0ac081f6 | 1604 | /* Handle -mabi= options. */ |
00b960c7 | 1605 | static void |
863d938c | 1606 | rs6000_parse_abi_options (void) |
0ac081f6 AH |
1607 | { |
1608 | if (rs6000_abi_string == 0) | |
1609 | return; | |
1610 | else if (! strcmp (rs6000_abi_string, "altivec")) | |
5cc73f91 AH |
1611 | { |
1612 | rs6000_altivec_abi = 1; | |
1613 | rs6000_spe_abi = 0; | |
1614 | } | |
76a773f3 AH |
1615 | else if (! strcmp (rs6000_abi_string, "no-altivec")) |
1616 | rs6000_altivec_abi = 0; | |
a3170dc6 | 1617 | else if (! strcmp (rs6000_abi_string, "spe")) |
01f4962d NS |
1618 | { |
1619 | rs6000_spe_abi = 1; | |
5cc73f91 | 1620 | rs6000_altivec_abi = 0; |
01f4962d NS |
1621 | if (!TARGET_SPE_ABI) |
1622 | error ("not configured for ABI: '%s'", rs6000_abi_string); | |
1623 | } | |
f676971a | 1624 | |
a3170dc6 AH |
1625 | else if (! strcmp (rs6000_abi_string, "no-spe")) |
1626 | rs6000_spe_abi = 0; | |
0ac081f6 | 1627 | else |
c725bd79 | 1628 | error ("unknown ABI specified: '%s'", rs6000_abi_string); |
0ac081f6 AH |
1629 | } |
1630 | ||
4d4cbc0e AH |
1631 | /* Handle -mfloat-gprs= options. */ |
1632 | static void | |
1633 | rs6000_parse_float_gprs_option (void) | |
1634 | { | |
1635 | if (rs6000_float_gprs_string == 0) | |
1636 | return; | |
1637 | else if (! strcmp (rs6000_float_gprs_string, "yes") | |
1638 | || ! strcmp (rs6000_float_gprs_string, "single")) | |
1639 | rs6000_float_gprs = 1; | |
1640 | else if (! strcmp (rs6000_float_gprs_string, "double")) | |
1641 | rs6000_float_gprs = 2; | |
1642 | else if (! strcmp (rs6000_float_gprs_string, "no")) | |
1643 | rs6000_float_gprs = 0; | |
1644 | else | |
1645 | error ("invalid option for -mfloat-gprs"); | |
1646 | } | |
1647 | ||
025d9908 KH |
1648 | /* Handle -malign-XXXXXX options. */ |
1649 | static void | |
863d938c | 1650 | rs6000_parse_alignment_option (void) |
025d9908 | 1651 | { |
b20a9cca AM |
1652 | if (rs6000_alignment_string == 0) |
1653 | return; | |
1654 | else if (! strcmp (rs6000_alignment_string, "power")) | |
025d9908 KH |
1655 | rs6000_alignment_flags = MASK_ALIGN_POWER; |
1656 | else if (! strcmp (rs6000_alignment_string, "natural")) | |
1657 | rs6000_alignment_flags = MASK_ALIGN_NATURAL; | |
1658 | else | |
1659 | error ("unknown -malign-XXXXX option specified: '%s'", | |
1660 | rs6000_alignment_string); | |
1661 | } | |
1662 | ||
c4501e62 JJ |
1663 | /* Validate and record the size specified with the -mtls-size option. */ |
1664 | ||
1665 | static void | |
863d938c | 1666 | rs6000_parse_tls_size_option (void) |
c4501e62 JJ |
1667 | { |
1668 | if (rs6000_tls_size_string == 0) | |
1669 | return; | |
1670 | else if (strcmp (rs6000_tls_size_string, "16") == 0) | |
1671 | rs6000_tls_size = 16; | |
1672 | else if (strcmp (rs6000_tls_size_string, "32") == 0) | |
1673 | rs6000_tls_size = 32; | |
1674 | else if (strcmp (rs6000_tls_size_string, "64") == 0) | |
1675 | rs6000_tls_size = 64; | |
1676 | else | |
1677 | error ("bad value `%s' for -mtls-size switch", rs6000_tls_size_string); | |
1678 | } | |
1679 | ||
5accd822 | 1680 | void |
a2369ed3 | 1681 | optimization_options (int level ATTRIBUTE_UNUSED, int size ATTRIBUTE_UNUSED) |
5accd822 | 1682 | { |
5accd822 | 1683 | } |
3cfa4909 MM |
1684 | \f |
1685 | /* Do anything needed at the start of the asm file. */ | |
1686 | ||
1bc7c5b6 | 1687 | static void |
863d938c | 1688 | rs6000_file_start (void) |
3cfa4909 | 1689 | { |
c4d38ccb | 1690 | size_t i; |
3cfa4909 | 1691 | char buffer[80]; |
d330fd93 | 1692 | const char *start = buffer; |
3cfa4909 | 1693 | struct rs6000_cpu_select *ptr; |
1bc7c5b6 ZW |
1694 | const char *default_cpu = TARGET_CPU_DEFAULT; |
1695 | FILE *file = asm_out_file; | |
1696 | ||
1697 | default_file_start (); | |
1698 | ||
1699 | #ifdef TARGET_BI_ARCH | |
1700 | if ((TARGET_DEFAULT ^ target_flags) & MASK_64BIT) | |
1701 | default_cpu = 0; | |
1702 | #endif | |
3cfa4909 MM |
1703 | |
1704 | if (flag_verbose_asm) | |
1705 | { | |
1706 | sprintf (buffer, "\n%s rs6000/powerpc options:", ASM_COMMENT_START); | |
1707 | rs6000_select[0].string = default_cpu; | |
1708 | ||
b6a1cbae | 1709 | for (i = 0; i < ARRAY_SIZE (rs6000_select); i++) |
3cfa4909 MM |
1710 | { |
1711 | ptr = &rs6000_select[i]; | |
1712 | if (ptr->string != (char *)0 && ptr->string[0] != '\0') | |
1713 | { | |
1714 | fprintf (file, "%s %s%s", start, ptr->name, ptr->string); | |
1715 | start = ""; | |
1716 | } | |
1717 | } | |
1718 | ||
b91da81f | 1719 | #ifdef USING_ELFOS_H |
3cfa4909 MM |
1720 | switch (rs6000_sdata) |
1721 | { | |
1722 | case SDATA_NONE: fprintf (file, "%s -msdata=none", start); start = ""; break; | |
1723 | case SDATA_DATA: fprintf (file, "%s -msdata=data", start); start = ""; break; | |
1724 | case SDATA_SYSV: fprintf (file, "%s -msdata=sysv", start); start = ""; break; | |
1725 | case SDATA_EABI: fprintf (file, "%s -msdata=eabi", start); start = ""; break; | |
1726 | } | |
1727 | ||
1728 | if (rs6000_sdata && g_switch_value) | |
1729 | { | |
307b599c MK |
1730 | fprintf (file, "%s -G " HOST_WIDE_INT_PRINT_UNSIGNED, start, |
1731 | g_switch_value); | |
3cfa4909 MM |
1732 | start = ""; |
1733 | } | |
1734 | #endif | |
1735 | ||
1736 | if (*start == '\0') | |
949ea356 | 1737 | putc ('\n', file); |
3cfa4909 MM |
1738 | } |
1739 | } | |
c4e18b1c | 1740 | |
5248c961 | 1741 | \f |
a0ab749a | 1742 | /* Return nonzero if this function is known to have a null epilogue. */ |
9878760c RK |
1743 | |
1744 | int | |
863d938c | 1745 | direct_return (void) |
9878760c | 1746 | { |
4697a36c MM |
1747 | if (reload_completed) |
1748 | { | |
1749 | rs6000_stack_t *info = rs6000_stack_info (); | |
1750 | ||
1751 | if (info->first_gp_reg_save == 32 | |
1752 | && info->first_fp_reg_save == 64 | |
00b960c7 | 1753 | && info->first_altivec_reg_save == LAST_ALTIVEC_REGNO + 1 |
c81fc13e DE |
1754 | && ! info->lr_save_p |
1755 | && ! info->cr_save_p | |
00b960c7 | 1756 | && info->vrsave_mask == 0 |
c81fc13e | 1757 | && ! info->push_p) |
4697a36c MM |
1758 | return 1; |
1759 | } | |
1760 | ||
1761 | return 0; | |
9878760c RK |
1762 | } |
1763 | ||
1764 | /* Returns 1 always. */ | |
1765 | ||
1766 | int | |
f676971a | 1767 | any_operand (rtx op ATTRIBUTE_UNUSED, |
a2369ed3 | 1768 | enum machine_mode mode ATTRIBUTE_UNUSED) |
9878760c RK |
1769 | { |
1770 | return 1; | |
1771 | } | |
1772 | ||
85d346f1 DE |
1773 | /* Returns 1 always. */ |
1774 | ||
1775 | int | |
f676971a | 1776 | any_parallel_operand (rtx op ATTRIBUTE_UNUSED, |
85d346f1 DE |
1777 | enum machine_mode mode ATTRIBUTE_UNUSED) |
1778 | { | |
1779 | return 1; | |
1780 | } | |
1781 | ||
a4f6c312 | 1782 | /* Returns 1 if op is the count register. */ |
85d346f1 | 1783 | |
38c1f2d7 | 1784 | int |
a2369ed3 | 1785 | count_register_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
b6c9286a MM |
1786 | { |
1787 | if (GET_CODE (op) != REG) | |
1788 | return 0; | |
1789 | ||
1790 | if (REGNO (op) == COUNT_REGISTER_REGNUM) | |
1791 | return 1; | |
1792 | ||
1793 | if (REGNO (op) > FIRST_PSEUDO_REGISTER) | |
1794 | return 1; | |
1795 | ||
1796 | return 0; | |
1797 | } | |
1798 | ||
0ec4e2a8 | 1799 | /* Returns 1 if op is an altivec register. */ |
85d346f1 | 1800 | |
0ec4e2a8 | 1801 | int |
a2369ed3 | 1802 | altivec_register_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
0ec4e2a8 | 1803 | { |
0ec4e2a8 AH |
1804 | return (register_operand (op, mode) |
1805 | && (GET_CODE (op) != REG | |
1806 | || REGNO (op) > FIRST_PSEUDO_REGISTER | |
1807 | || ALTIVEC_REGNO_P (REGNO (op)))); | |
1808 | } | |
1809 | ||
38c1f2d7 | 1810 | int |
a2369ed3 | 1811 | xer_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
802a0058 MM |
1812 | { |
1813 | if (GET_CODE (op) != REG) | |
1814 | return 0; | |
1815 | ||
9ebbca7d | 1816 | if (XER_REGNO_P (REGNO (op))) |
802a0058 MM |
1817 | return 1; |
1818 | ||
802a0058 MM |
1819 | return 0; |
1820 | } | |
1821 | ||
c859cda6 | 1822 | /* Return 1 if OP is a signed 8-bit constant. Int multiplication |
6f317ef3 | 1823 | by such constants completes more quickly. */ |
c859cda6 DJ |
1824 | |
1825 | int | |
a2369ed3 | 1826 | s8bit_cint_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
c859cda6 | 1827 | { |
c4ad648e | 1828 | return (GET_CODE (op) == CONST_INT |
c859cda6 DJ |
1829 | && (INTVAL (op) >= -128 && INTVAL (op) <= 127)); |
1830 | } | |
1831 | ||
9878760c RK |
1832 | /* Return 1 if OP is a constant that can fit in a D field. */ |
1833 | ||
1834 | int | |
a2369ed3 | 1835 | short_cint_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
9878760c | 1836 | { |
5f59ecb7 DE |
1837 | return (GET_CODE (op) == CONST_INT |
1838 | && CONST_OK_FOR_LETTER_P (INTVAL (op), 'I')); | |
9878760c RK |
1839 | } |
1840 | ||
5519a4f9 | 1841 | /* Similar for an unsigned D field. */ |
9878760c RK |
1842 | |
1843 | int | |
a2369ed3 | 1844 | u_short_cint_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
9878760c | 1845 | { |
19684119 | 1846 | return (GET_CODE (op) == CONST_INT |
c1f11548 | 1847 | && CONST_OK_FOR_LETTER_P (INTVAL (op) & GET_MODE_MASK (mode), 'K')); |
9878760c RK |
1848 | } |
1849 | ||
dcfedcd0 RK |
1850 | /* Return 1 if OP is a CONST_INT that cannot fit in a signed D field. */ |
1851 | ||
1852 | int | |
a2369ed3 | 1853 | non_short_cint_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
dcfedcd0 RK |
1854 | { |
1855 | return (GET_CODE (op) == CONST_INT | |
a7653a2c | 1856 | && (unsigned HOST_WIDE_INT) (INTVAL (op) + 0x8000) >= 0x10000); |
dcfedcd0 RK |
1857 | } |
1858 | ||
2bfcf297 DB |
1859 | /* Returns 1 if OP is a CONST_INT that is a positive value |
1860 | and an exact power of 2. */ | |
1861 | ||
1862 | int | |
a2369ed3 | 1863 | exact_log2_cint_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
2bfcf297 DB |
1864 | { |
1865 | return (GET_CODE (op) == CONST_INT | |
1866 | && INTVAL (op) > 0 | |
1867 | && exact_log2 (INTVAL (op)) >= 0); | |
1868 | } | |
1869 | ||
9878760c RK |
1870 | /* Returns 1 if OP is a register that is not special (i.e., not MQ, |
1871 | ctr, or lr). */ | |
1872 | ||
1873 | int | |
a2369ed3 | 1874 | gpc_reg_operand (rtx op, enum machine_mode mode) |
9878760c RK |
1875 | { |
1876 | return (register_operand (op, mode) | |
802a0058 | 1877 | && (GET_CODE (op) != REG |
f676971a | 1878 | || (REGNO (op) >= ARG_POINTER_REGNUM |
9ebbca7d GK |
1879 | && !XER_REGNO_P (REGNO (op))) |
1880 | || REGNO (op) < MQ_REGNO)); | |
9878760c RK |
1881 | } |
1882 | ||
1883 | /* Returns 1 if OP is either a pseudo-register or a register denoting a | |
1884 | CR field. */ | |
1885 | ||
1886 | int | |
a2369ed3 | 1887 | cc_reg_operand (rtx op, enum machine_mode mode) |
9878760c RK |
1888 | { |
1889 | return (register_operand (op, mode) | |
1890 | && (GET_CODE (op) != REG | |
1891 | || REGNO (op) >= FIRST_PSEUDO_REGISTER | |
1892 | || CR_REGNO_P (REGNO (op)))); | |
1893 | } | |
1894 | ||
815cdc52 MM |
1895 | /* Returns 1 if OP is either a pseudo-register or a register denoting a |
1896 | CR field that isn't CR0. */ | |
1897 | ||
1898 | int | |
a2369ed3 | 1899 | cc_reg_not_cr0_operand (rtx op, enum machine_mode mode) |
815cdc52 MM |
1900 | { |
1901 | return (register_operand (op, mode) | |
1902 | && (GET_CODE (op) != REG | |
1903 | || REGNO (op) >= FIRST_PSEUDO_REGISTER | |
1904 | || CR_REGNO_NOT_CR0_P (REGNO (op)))); | |
1905 | } | |
1906 | ||
a4f6c312 SS |
1907 | /* Returns 1 if OP is either a constant integer valid for a D-field or |
1908 | a non-special register. If a register, it must be in the proper | |
1909 | mode unless MODE is VOIDmode. */ | |
9878760c RK |
1910 | |
1911 | int | |
a2369ed3 | 1912 | reg_or_short_operand (rtx op, enum machine_mode mode) |
9878760c | 1913 | { |
f5a28898 | 1914 | return short_cint_operand (op, mode) || gpc_reg_operand (op, mode); |
9878760c RK |
1915 | } |
1916 | ||
a4f6c312 | 1917 | /* Similar, except check if the negation of the constant would be |
42f806e5 AM |
1918 | valid for a D-field. Don't allow a constant zero, since all the |
1919 | patterns that call this predicate use "addic r1,r2,-constant" on | |
1920 | a constant value to set a carry when r2 is greater or equal to | |
1921 | "constant". That doesn't work for zero. */ | |
9878760c RK |
1922 | |
1923 | int | |
a2369ed3 | 1924 | reg_or_neg_short_operand (rtx op, enum machine_mode mode) |
9878760c RK |
1925 | { |
1926 | if (GET_CODE (op) == CONST_INT) | |
42f806e5 | 1927 | return CONST_OK_FOR_LETTER_P (INTVAL (op), 'P') && INTVAL (op) != 0; |
9878760c | 1928 | |
cd2b37d9 | 1929 | return gpc_reg_operand (op, mode); |
9878760c RK |
1930 | } |
1931 | ||
768070a0 TR |
1932 | /* Returns 1 if OP is either a constant integer valid for a DS-field or |
1933 | a non-special register. If a register, it must be in the proper | |
1934 | mode unless MODE is VOIDmode. */ | |
1935 | ||
1936 | int | |
a2369ed3 | 1937 | reg_or_aligned_short_operand (rtx op, enum machine_mode mode) |
768070a0 TR |
1938 | { |
1939 | if (gpc_reg_operand (op, mode)) | |
1940 | return 1; | |
1941 | else if (short_cint_operand (op, mode) && !(INTVAL (op) & 3)) | |
1942 | return 1; | |
1943 | ||
1944 | return 0; | |
1945 | } | |
1946 | ||
1947 | ||
a4f6c312 SS |
1948 | /* Return 1 if the operand is either a register or an integer whose |
1949 | high-order 16 bits are zero. */ | |
9878760c RK |
1950 | |
1951 | int | |
a2369ed3 | 1952 | reg_or_u_short_operand (rtx op, enum machine_mode mode) |
9878760c | 1953 | { |
e675f625 | 1954 | return u_short_cint_operand (op, mode) || gpc_reg_operand (op, mode); |
9878760c RK |
1955 | } |
1956 | ||
1957 | /* Return 1 is the operand is either a non-special register or ANY | |
1958 | constant integer. */ | |
1959 | ||
1960 | int | |
a2369ed3 | 1961 | reg_or_cint_operand (rtx op, enum machine_mode mode) |
9878760c | 1962 | { |
a4f6c312 | 1963 | return (GET_CODE (op) == CONST_INT || gpc_reg_operand (op, mode)); |
f6bf7de2 DE |
1964 | } |
1965 | ||
1966 | /* Return 1 is the operand is either a non-special register or ANY | |
1967 | 32-bit signed constant integer. */ | |
1968 | ||
1969 | int | |
a2369ed3 | 1970 | reg_or_arith_cint_operand (rtx op, enum machine_mode mode) |
f6bf7de2 | 1971 | { |
a4f6c312 SS |
1972 | return (gpc_reg_operand (op, mode) |
1973 | || (GET_CODE (op) == CONST_INT | |
f6bf7de2 | 1974 | #if HOST_BITS_PER_WIDE_INT != 32 |
a4f6c312 SS |
1975 | && ((unsigned HOST_WIDE_INT) (INTVAL (op) + 0x80000000) |
1976 | < (unsigned HOST_WIDE_INT) 0x100000000ll) | |
f6bf7de2 | 1977 | #endif |
a4f6c312 | 1978 | )); |
9878760c RK |
1979 | } |
1980 | ||
2bfcf297 DB |
1981 | /* Return 1 is the operand is either a non-special register or a 32-bit |
1982 | signed constant integer valid for 64-bit addition. */ | |
1983 | ||
1984 | int | |
a2369ed3 | 1985 | reg_or_add_cint64_operand (rtx op, enum machine_mode mode) |
2bfcf297 | 1986 | { |
a4f6c312 SS |
1987 | return (gpc_reg_operand (op, mode) |
1988 | || (GET_CODE (op) == CONST_INT | |
a65c591c | 1989 | #if HOST_BITS_PER_WIDE_INT == 32 |
a4f6c312 | 1990 | && INTVAL (op) < 0x7fff8000 |
a65c591c | 1991 | #else |
a4f6c312 SS |
1992 | && ((unsigned HOST_WIDE_INT) (INTVAL (op) + 0x80008000) |
1993 | < 0x100000000ll) | |
2bfcf297 | 1994 | #endif |
a4f6c312 | 1995 | )); |
2bfcf297 DB |
1996 | } |
1997 | ||
1998 | /* Return 1 is the operand is either a non-special register or a 32-bit | |
1999 | signed constant integer valid for 64-bit subtraction. */ | |
2000 | ||
2001 | int | |
a2369ed3 | 2002 | reg_or_sub_cint64_operand (rtx op, enum machine_mode mode) |
2bfcf297 | 2003 | { |
a4f6c312 SS |
2004 | return (gpc_reg_operand (op, mode) |
2005 | || (GET_CODE (op) == CONST_INT | |
a65c591c | 2006 | #if HOST_BITS_PER_WIDE_INT == 32 |
a4f6c312 | 2007 | && (- INTVAL (op)) < 0x7fff8000 |
a65c591c | 2008 | #else |
a4f6c312 SS |
2009 | && ((unsigned HOST_WIDE_INT) ((- INTVAL (op)) + 0x80008000) |
2010 | < 0x100000000ll) | |
2bfcf297 | 2011 | #endif |
a4f6c312 | 2012 | )); |
2bfcf297 DB |
2013 | } |
2014 | ||
9ebbca7d GK |
2015 | /* Return 1 is the operand is either a non-special register or ANY |
2016 | 32-bit unsigned constant integer. */ | |
2017 | ||
2018 | int | |
a2369ed3 | 2019 | reg_or_logical_cint_operand (rtx op, enum machine_mode mode) |
9ebbca7d | 2020 | { |
1d328b19 GK |
2021 | if (GET_CODE (op) == CONST_INT) |
2022 | { | |
2023 | if (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT) | |
2024 | { | |
2025 | if (GET_MODE_BITSIZE (mode) <= 32) | |
a4f6c312 | 2026 | abort (); |
1d328b19 GK |
2027 | |
2028 | if (INTVAL (op) < 0) | |
2029 | return 0; | |
2030 | } | |
2031 | ||
2032 | return ((INTVAL (op) & GET_MODE_MASK (mode) | |
0858c623 | 2033 | & (~ (unsigned HOST_WIDE_INT) 0xffffffff)) == 0); |
1d328b19 GK |
2034 | } |
2035 | else if (GET_CODE (op) == CONST_DOUBLE) | |
2036 | { | |
2037 | if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT | |
2038 | || mode != DImode) | |
a4f6c312 | 2039 | abort (); |
1d328b19 GK |
2040 | |
2041 | return CONST_DOUBLE_HIGH (op) == 0; | |
2042 | } | |
f676971a | 2043 | else |
1d328b19 | 2044 | return gpc_reg_operand (op, mode); |
9ebbca7d GK |
2045 | } |
2046 | ||
51d3e7d6 | 2047 | /* Return 1 if the operand is an operand that can be loaded via the GOT. */ |
766a866c MM |
2048 | |
2049 | int | |
a2369ed3 | 2050 | got_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
766a866c MM |
2051 | { |
2052 | return (GET_CODE (op) == SYMBOL_REF | |
2053 | || GET_CODE (op) == CONST | |
2054 | || GET_CODE (op) == LABEL_REF); | |
2055 | } | |
2056 | ||
38c1f2d7 MM |
2057 | /* Return 1 if the operand is a simple references that can be loaded via |
2058 | the GOT (labels involving addition aren't allowed). */ | |
2059 | ||
2060 | int | |
a2369ed3 | 2061 | got_no_const_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
38c1f2d7 MM |
2062 | { |
2063 | return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF); | |
2064 | } | |
2065 | ||
4e74d8ec MM |
2066 | /* Return the number of instructions it takes to form a constant in an |
2067 | integer register. */ | |
2068 | ||
2069 | static int | |
a2369ed3 | 2070 | num_insns_constant_wide (HOST_WIDE_INT value) |
4e74d8ec MM |
2071 | { |
2072 | /* signed constant loadable with {cal|addi} */ | |
5f59ecb7 | 2073 | if (CONST_OK_FOR_LETTER_P (value, 'I')) |
0865c631 GK |
2074 | return 1; |
2075 | ||
4e74d8ec | 2076 | /* constant loadable with {cau|addis} */ |
5f59ecb7 | 2077 | else if (CONST_OK_FOR_LETTER_P (value, 'L')) |
4e74d8ec MM |
2078 | return 1; |
2079 | ||
5f59ecb7 | 2080 | #if HOST_BITS_PER_WIDE_INT == 64 |
c81fc13e | 2081 | else if (TARGET_POWERPC64) |
4e74d8ec | 2082 | { |
a65c591c DE |
2083 | HOST_WIDE_INT low = ((value & 0xffffffff) ^ 0x80000000) - 0x80000000; |
2084 | HOST_WIDE_INT high = value >> 31; | |
4e74d8ec | 2085 | |
a65c591c | 2086 | if (high == 0 || high == -1) |
4e74d8ec MM |
2087 | return 2; |
2088 | ||
a65c591c | 2089 | high >>= 1; |
4e74d8ec | 2090 | |
a65c591c | 2091 | if (low == 0) |
4e74d8ec | 2092 | return num_insns_constant_wide (high) + 1; |
4e74d8ec MM |
2093 | else |
2094 | return (num_insns_constant_wide (high) | |
e396202a | 2095 | + num_insns_constant_wide (low) + 1); |
4e74d8ec MM |
2096 | } |
2097 | #endif | |
2098 | ||
2099 | else | |
2100 | return 2; | |
2101 | } | |
2102 | ||
2103 | int | |
a2369ed3 | 2104 | num_insns_constant (rtx op, enum machine_mode mode) |
4e74d8ec | 2105 | { |
4e74d8ec | 2106 | if (GET_CODE (op) == CONST_INT) |
0d30d435 DE |
2107 | { |
2108 | #if HOST_BITS_PER_WIDE_INT == 64 | |
4e2c1c44 DE |
2109 | if ((INTVAL (op) >> 31) != 0 && (INTVAL (op) >> 31) != -1 |
2110 | && mask64_operand (op, mode)) | |
c4ad648e | 2111 | return 2; |
0d30d435 DE |
2112 | else |
2113 | #endif | |
2114 | return num_insns_constant_wide (INTVAL (op)); | |
2115 | } | |
4e74d8ec | 2116 | |
6fc48950 MM |
2117 | else if (GET_CODE (op) == CONST_DOUBLE && mode == SFmode) |
2118 | { | |
2119 | long l; | |
2120 | REAL_VALUE_TYPE rv; | |
2121 | ||
2122 | REAL_VALUE_FROM_CONST_DOUBLE (rv, op); | |
2123 | REAL_VALUE_TO_TARGET_SINGLE (rv, l); | |
e72247f4 | 2124 | return num_insns_constant_wide ((HOST_WIDE_INT) l); |
6fc48950 MM |
2125 | } |
2126 | ||
47ad8c61 | 2127 | else if (GET_CODE (op) == CONST_DOUBLE) |
4e74d8ec | 2128 | { |
47ad8c61 MM |
2129 | HOST_WIDE_INT low; |
2130 | HOST_WIDE_INT high; | |
2131 | long l[2]; | |
2132 | REAL_VALUE_TYPE rv; | |
2133 | int endian = (WORDS_BIG_ENDIAN == 0); | |
4e74d8ec | 2134 | |
47ad8c61 MM |
2135 | if (mode == VOIDmode || mode == DImode) |
2136 | { | |
2137 | high = CONST_DOUBLE_HIGH (op); | |
2138 | low = CONST_DOUBLE_LOW (op); | |
2139 | } | |
2140 | else | |
2141 | { | |
2142 | REAL_VALUE_FROM_CONST_DOUBLE (rv, op); | |
2143 | REAL_VALUE_TO_TARGET_DOUBLE (rv, l); | |
2144 | high = l[endian]; | |
2145 | low = l[1 - endian]; | |
2146 | } | |
4e74d8ec | 2147 | |
47ad8c61 MM |
2148 | if (TARGET_32BIT) |
2149 | return (num_insns_constant_wide (low) | |
2150 | + num_insns_constant_wide (high)); | |
4e74d8ec MM |
2151 | |
2152 | else | |
47ad8c61 | 2153 | { |
e72247f4 | 2154 | if (high == 0 && low >= 0) |
47ad8c61 MM |
2155 | return num_insns_constant_wide (low); |
2156 | ||
e72247f4 | 2157 | else if (high == -1 && low < 0) |
47ad8c61 MM |
2158 | return num_insns_constant_wide (low); |
2159 | ||
a260abc9 DE |
2160 | else if (mask64_operand (op, mode)) |
2161 | return 2; | |
2162 | ||
47ad8c61 MM |
2163 | else if (low == 0) |
2164 | return num_insns_constant_wide (high) + 1; | |
2165 | ||
2166 | else | |
2167 | return (num_insns_constant_wide (high) | |
2168 | + num_insns_constant_wide (low) + 1); | |
2169 | } | |
4e74d8ec MM |
2170 | } |
2171 | ||
2172 | else | |
2173 | abort (); | |
2174 | } | |
2175 | ||
a4f6c312 SS |
2176 | /* Return 1 if the operand is a CONST_DOUBLE and it can be put into a |
2177 | register with one instruction per word. We only do this if we can | |
2178 | safely read CONST_DOUBLE_{LOW,HIGH}. */ | |
9878760c RK |
2179 | |
2180 | int | |
a2369ed3 | 2181 | easy_fp_constant (rtx op, enum machine_mode mode) |
9878760c | 2182 | { |
9878760c RK |
2183 | if (GET_CODE (op) != CONST_DOUBLE |
2184 | || GET_MODE (op) != mode | |
4e74d8ec | 2185 | || (GET_MODE_CLASS (mode) != MODE_FLOAT && mode != DImode)) |
9878760c RK |
2186 | return 0; |
2187 | ||
a4f6c312 | 2188 | /* Consider all constants with -msoft-float to be easy. */ |
4d4cbc0e | 2189 | if ((TARGET_SOFT_FLOAT || TARGET_E500_SINGLE) |
a3170dc6 | 2190 | && mode != DImode) |
b6c9286a MM |
2191 | return 1; |
2192 | ||
a4f6c312 | 2193 | /* If we are using V.4 style PIC, consider all constants to be hard. */ |
f607bc57 | 2194 | if (flag_pic && DEFAULT_ABI == ABI_V4) |
a7273471 MM |
2195 | return 0; |
2196 | ||
5ae4759c | 2197 | #ifdef TARGET_RELOCATABLE |
a4f6c312 SS |
2198 | /* Similarly if we are using -mrelocatable, consider all constants |
2199 | to be hard. */ | |
5ae4759c MM |
2200 | if (TARGET_RELOCATABLE) |
2201 | return 0; | |
2202 | #endif | |
2203 | ||
fcce224d DE |
2204 | if (mode == TFmode) |
2205 | { | |
2206 | long k[4]; | |
2207 | REAL_VALUE_TYPE rv; | |
2208 | ||
2209 | REAL_VALUE_FROM_CONST_DOUBLE (rv, op); | |
2210 | REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv, k); | |
2211 | ||
2212 | return (num_insns_constant_wide ((HOST_WIDE_INT) k[0]) == 1 | |
2213 | && num_insns_constant_wide ((HOST_WIDE_INT) k[1]) == 1 | |
2214 | && num_insns_constant_wide ((HOST_WIDE_INT) k[2]) == 1 | |
2215 | && num_insns_constant_wide ((HOST_WIDE_INT) k[3]) == 1); | |
2216 | } | |
2217 | ||
2218 | else if (mode == DFmode) | |
042259f2 DE |
2219 | { |
2220 | long k[2]; | |
2221 | REAL_VALUE_TYPE rv; | |
2222 | ||
4d4cbc0e AH |
2223 | if (TARGET_E500_DOUBLE) |
2224 | return 0; | |
2225 | ||
042259f2 DE |
2226 | REAL_VALUE_FROM_CONST_DOUBLE (rv, op); |
2227 | REAL_VALUE_TO_TARGET_DOUBLE (rv, k); | |
9878760c | 2228 | |
a65c591c DE |
2229 | return (num_insns_constant_wide ((HOST_WIDE_INT) k[0]) == 1 |
2230 | && num_insns_constant_wide ((HOST_WIDE_INT) k[1]) == 1); | |
042259f2 | 2231 | } |
4e74d8ec MM |
2232 | |
2233 | else if (mode == SFmode) | |
042259f2 DE |
2234 | { |
2235 | long l; | |
2236 | REAL_VALUE_TYPE rv; | |
2237 | ||
2238 | REAL_VALUE_FROM_CONST_DOUBLE (rv, op); | |
2239 | REAL_VALUE_TO_TARGET_SINGLE (rv, l); | |
9878760c | 2240 | |
4e74d8ec | 2241 | return num_insns_constant_wide (l) == 1; |
042259f2 | 2242 | } |
4e74d8ec | 2243 | |
a260abc9 | 2244 | else if (mode == DImode) |
c81fc13e | 2245 | return ((TARGET_POWERPC64 |
a260abc9 DE |
2246 | && GET_CODE (op) == CONST_DOUBLE && CONST_DOUBLE_LOW (op) == 0) |
2247 | || (num_insns_constant (op, DImode) <= 2)); | |
4e74d8ec | 2248 | |
a9098fd0 GK |
2249 | else if (mode == SImode) |
2250 | return 1; | |
4e74d8ec MM |
2251 | else |
2252 | abort (); | |
9878760c | 2253 | } |
8f75773e | 2254 | |
effa5d5d | 2255 | /* Returns the constant for the splat instruction, if exists. */ |
452a7d36 HP |
2256 | |
2257 | static int | |
2258 | easy_vector_splat_const (int cst, enum machine_mode mode) | |
2259 | { | |
f676971a | 2260 | switch (mode) |
452a7d36 HP |
2261 | { |
2262 | case V4SImode: | |
f676971a EC |
2263 | if (EASY_VECTOR_15 (cst) |
2264 | || EASY_VECTOR_15_ADD_SELF (cst)) | |
452a7d36 HP |
2265 | return cst; |
2266 | if ((cst & 0xffff) != ((cst >> 16) & 0xffff)) | |
2267 | break; | |
2268 | cst = cst >> 16; | |
c4ad648e AM |
2269 | /* Fall thru */ |
2270 | ||
452a7d36 | 2271 | case V8HImode: |
f676971a EC |
2272 | if (EASY_VECTOR_15 (cst) |
2273 | || EASY_VECTOR_15_ADD_SELF (cst)) | |
452a7d36 HP |
2274 | return cst; |
2275 | if ((cst & 0xff) != ((cst >> 8) & 0xff)) | |
2276 | break; | |
2277 | cst = cst >> 8; | |
c4ad648e AM |
2278 | /* Fall thru */ |
2279 | ||
452a7d36 | 2280 | case V16QImode: |
c4ad648e AM |
2281 | if (EASY_VECTOR_15 (cst) |
2282 | || EASY_VECTOR_15_ADD_SELF (cst)) | |
2283 | return cst; | |
f676971a | 2284 | default: |
452a7d36 HP |
2285 | break; |
2286 | } | |
2287 | return 0; | |
2288 | } | |
2289 | ||
2290 | ||
72ac76be | 2291 | /* Return nonzero if all elements of a vector have the same value. */ |
69ef87e2 AH |
2292 | |
2293 | static int | |
a2369ed3 | 2294 | easy_vector_same (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
d744e06e AH |
2295 | { |
2296 | int units, i, cst; | |
2297 | ||
2298 | units = CONST_VECTOR_NUNITS (op); | |
2299 | ||
2300 | cst = INTVAL (CONST_VECTOR_ELT (op, 0)); | |
2301 | for (i = 1; i < units; ++i) | |
2302 | if (INTVAL (CONST_VECTOR_ELT (op, i)) != cst) | |
2303 | break; | |
452a7d36 | 2304 | if (i == units && easy_vector_splat_const (cst, mode)) |
d744e06e AH |
2305 | return 1; |
2306 | return 0; | |
2307 | } | |
2308 | ||
2309 | /* Return 1 if the operand is a CONST_INT and can be put into a | |
2310 | register without using memory. */ | |
2311 | ||
2312 | int | |
a2369ed3 | 2313 | easy_vector_constant (rtx op, enum machine_mode mode) |
69ef87e2 | 2314 | { |
d744e06e | 2315 | int cst, cst2; |
69ef87e2 | 2316 | |
d744e06e AH |
2317 | if (GET_CODE (op) != CONST_VECTOR |
2318 | || (!TARGET_ALTIVEC | |
2319 | && !TARGET_SPE)) | |
69ef87e2 AH |
2320 | return 0; |
2321 | ||
d744e06e AH |
2322 | if (zero_constant (op, mode) |
2323 | && ((TARGET_ALTIVEC && ALTIVEC_VECTOR_MODE (mode)) | |
2324 | || (TARGET_SPE && SPE_VECTOR_MODE (mode)))) | |
2325 | return 1; | |
69ef87e2 | 2326 | |
d744e06e AH |
2327 | if (GET_MODE_CLASS (mode) != MODE_VECTOR_INT) |
2328 | return 0; | |
2329 | ||
f5119d10 AH |
2330 | if (TARGET_SPE && mode == V1DImode) |
2331 | return 0; | |
2332 | ||
d744e06e AH |
2333 | cst = INTVAL (CONST_VECTOR_ELT (op, 0)); |
2334 | cst2 = INTVAL (CONST_VECTOR_ELT (op, 1)); | |
2335 | ||
2336 | /* Limit SPE vectors to 15 bits signed. These we can generate with: | |
2337 | li r0, CONSTANT1 | |
2338 | evmergelo r0, r0, r0 | |
2339 | li r0, CONSTANT2 | |
2340 | ||
2341 | I don't know how efficient it would be to allow bigger constants, | |
2342 | considering we'll have an extra 'ori' for every 'li'. I doubt 5 | |
2343 | instructions is better than a 64-bit memory load, but I don't | |
2344 | have the e500 timing specs. */ | |
2345 | if (TARGET_SPE && mode == V2SImode | |
2346 | && cst >= -0x7fff && cst <= 0x7fff | |
f5119d10 | 2347 | && cst2 >= -0x7fff && cst2 <= 0x7fff) |
d744e06e AH |
2348 | return 1; |
2349 | ||
f676971a | 2350 | if (TARGET_ALTIVEC |
452a7d36 HP |
2351 | && easy_vector_same (op, mode)) |
2352 | { | |
2353 | cst = easy_vector_splat_const (cst, mode); | |
f676971a | 2354 | if (EASY_VECTOR_15_ADD_SELF (cst) |
452a7d36 HP |
2355 | || EASY_VECTOR_15 (cst)) |
2356 | return 1; | |
f676971a | 2357 | } |
d744e06e AH |
2358 | return 0; |
2359 | } | |
2360 | ||
2361 | /* Same as easy_vector_constant but only for EASY_VECTOR_15_ADD_SELF. */ | |
2362 | ||
2363 | int | |
a2369ed3 | 2364 | easy_vector_constant_add_self (rtx op, enum machine_mode mode) |
d744e06e AH |
2365 | { |
2366 | int cst; | |
452a7d36 HP |
2367 | if (TARGET_ALTIVEC |
2368 | && GET_CODE (op) == CONST_VECTOR | |
2369 | && easy_vector_same (op, mode)) | |
2370 | { | |
2371 | cst = easy_vector_splat_const (INTVAL (CONST_VECTOR_ELT (op, 0)), mode); | |
2372 | if (EASY_VECTOR_15_ADD_SELF (cst)) | |
f676971a | 2373 | return 1; |
452a7d36 HP |
2374 | } |
2375 | return 0; | |
2376 | } | |
d744e06e | 2377 | |
452a7d36 | 2378 | /* Generate easy_vector_constant out of a easy_vector_constant_add_self. */ |
d744e06e | 2379 | |
f676971a | 2380 | rtx |
452a7d36 HP |
2381 | gen_easy_vector_constant_add_self (rtx op) |
2382 | { | |
2383 | int i, units; | |
2384 | rtvec v; | |
2385 | units = GET_MODE_NUNITS (GET_MODE (op)); | |
2386 | v = rtvec_alloc (units); | |
2387 | ||
2388 | for (i = 0; i < units; i++) | |
f676971a | 2389 | RTVEC_ELT (v, i) = |
452a7d36 HP |
2390 | GEN_INT (INTVAL (CONST_VECTOR_ELT (op, i)) >> 1); |
2391 | return gen_rtx_raw_CONST_VECTOR (GET_MODE (op), v); | |
d744e06e AH |
2392 | } |
2393 | ||
2394 | const char * | |
a2369ed3 | 2395 | output_vec_const_move (rtx *operands) |
d744e06e AH |
2396 | { |
2397 | int cst, cst2; | |
2398 | enum machine_mode mode; | |
2399 | rtx dest, vec; | |
2400 | ||
2401 | dest = operands[0]; | |
2402 | vec = operands[1]; | |
69ef87e2 | 2403 | |
d744e06e AH |
2404 | cst = INTVAL (CONST_VECTOR_ELT (vec, 0)); |
2405 | cst2 = INTVAL (CONST_VECTOR_ELT (vec, 1)); | |
2406 | mode = GET_MODE (dest); | |
69ef87e2 | 2407 | |
d744e06e AH |
2408 | if (TARGET_ALTIVEC) |
2409 | { | |
2410 | if (zero_constant (vec, mode)) | |
2411 | return "vxor %0,%0,%0"; | |
ce1f50b2 | 2412 | else if (easy_vector_constant (vec, mode)) |
98ef3137 | 2413 | { |
d744e06e AH |
2414 | operands[1] = GEN_INT (cst); |
2415 | switch (mode) | |
2416 | { | |
2417 | case V4SImode: | |
452a7d36 | 2418 | if (EASY_VECTOR_15 (cst)) |
ce1f50b2 HP |
2419 | { |
2420 | operands[1] = GEN_INT (cst); | |
2421 | return "vspltisw %0,%1"; | |
2422 | } | |
452a7d36 HP |
2423 | else if (EASY_VECTOR_15_ADD_SELF (cst)) |
2424 | return "#"; | |
ce1f50b2 | 2425 | cst = cst >> 16; |
c4ad648e AM |
2426 | /* Fall thru */ |
2427 | ||
d744e06e | 2428 | case V8HImode: |
452a7d36 | 2429 | if (EASY_VECTOR_15 (cst)) |
ce1f50b2 HP |
2430 | { |
2431 | operands[1] = GEN_INT (cst); | |
2432 | return "vspltish %0,%1"; | |
2433 | } | |
452a7d36 HP |
2434 | else if (EASY_VECTOR_15_ADD_SELF (cst)) |
2435 | return "#"; | |
ce1f50b2 | 2436 | cst = cst >> 8; |
c4ad648e AM |
2437 | /* Fall thru */ |
2438 | ||
d744e06e | 2439 | case V16QImode: |
452a7d36 | 2440 | if (EASY_VECTOR_15 (cst)) |
ce1f50b2 HP |
2441 | { |
2442 | operands[1] = GEN_INT (cst); | |
2443 | return "vspltisb %0,%1"; | |
2444 | } | |
452a7d36 HP |
2445 | else if (EASY_VECTOR_15_ADD_SELF (cst)) |
2446 | return "#"; | |
c4ad648e | 2447 | |
d744e06e AH |
2448 | default: |
2449 | abort (); | |
2450 | } | |
98ef3137 | 2451 | } |
d744e06e AH |
2452 | else |
2453 | abort (); | |
69ef87e2 AH |
2454 | } |
2455 | ||
d744e06e AH |
2456 | if (TARGET_SPE) |
2457 | { | |
2458 | /* Vector constant 0 is handled as a splitter of V2SI, and in the | |
2459 | pattern of V1DI, V4HI, and V2SF. | |
2460 | ||
c1207243 | 2461 | FIXME: We should probably return # and add post reload |
c4ad648e | 2462 | splitters for these, but this way is so easy ;-). */ |
d744e06e AH |
2463 | operands[1] = GEN_INT (cst); |
2464 | operands[2] = GEN_INT (cst2); | |
2465 | if (cst == cst2) | |
2466 | return "li %0,%1\n\tevmergelo %0,%0,%0"; | |
2467 | else | |
2468 | return "li %0,%1\n\tevmergelo %0,%0,%0\n\tli %0,%2"; | |
2469 | } | |
2470 | ||
2471 | abort (); | |
69ef87e2 AH |
2472 | } |
2473 | ||
2474 | /* Return 1 if the operand is the constant 0. This works for scalars | |
2475 | as well as vectors. */ | |
2476 | int | |
a2369ed3 | 2477 | zero_constant (rtx op, enum machine_mode mode) |
69ef87e2 AH |
2478 | { |
2479 | return op == CONST0_RTX (mode); | |
2480 | } | |
2481 | ||
50a0b056 GK |
2482 | /* Return 1 if the operand is 0.0. */ |
2483 | int | |
a2369ed3 | 2484 | zero_fp_constant (rtx op, enum machine_mode mode) |
50a0b056 GK |
2485 | { |
2486 | return GET_MODE_CLASS (mode) == MODE_FLOAT && op == CONST0_RTX (mode); | |
2487 | } | |
2488 | ||
a4f6c312 SS |
2489 | /* Return 1 if the operand is in volatile memory. Note that during |
2490 | the RTL generation phase, memory_operand does not return TRUE for | |
b6c9286a MM |
2491 | volatile memory references. So this function allows us to |
2492 | recognize volatile references where its safe. */ | |
2493 | ||
2494 | int | |
a2369ed3 | 2495 | volatile_mem_operand (rtx op, enum machine_mode mode) |
b6c9286a MM |
2496 | { |
2497 | if (GET_CODE (op) != MEM) | |
2498 | return 0; | |
2499 | ||
2500 | if (!MEM_VOLATILE_P (op)) | |
2501 | return 0; | |
2502 | ||
2503 | if (mode != GET_MODE (op)) | |
2504 | return 0; | |
2505 | ||
2506 | if (reload_completed) | |
2507 | return memory_operand (op, mode); | |
2508 | ||
2509 | if (reload_in_progress) | |
2510 | return strict_memory_address_p (mode, XEXP (op, 0)); | |
2511 | ||
2512 | return memory_address_p (mode, XEXP (op, 0)); | |
2513 | } | |
2514 | ||
97f6e72f | 2515 | /* Return 1 if the operand is an offsettable memory operand. */ |
914c2e77 RK |
2516 | |
2517 | int | |
a2369ed3 | 2518 | offsettable_mem_operand (rtx op, enum machine_mode mode) |
914c2e77 | 2519 | { |
97f6e72f | 2520 | return ((GET_CODE (op) == MEM) |
677a9668 | 2521 | && offsettable_address_p (reload_completed || reload_in_progress, |
97f6e72f | 2522 | mode, XEXP (op, 0))); |
914c2e77 RK |
2523 | } |
2524 | ||
9878760c RK |
2525 | /* Return 1 if the operand is either an easy FP constant (see above) or |
2526 | memory. */ | |
2527 | ||
2528 | int | |
a2369ed3 | 2529 | mem_or_easy_const_operand (rtx op, enum machine_mode mode) |
9878760c RK |
2530 | { |
2531 | return memory_operand (op, mode) || easy_fp_constant (op, mode); | |
2532 | } | |
2533 | ||
2534 | /* Return 1 if the operand is either a non-special register or an item | |
5f59ecb7 | 2535 | that can be used as the operand of a `mode' add insn. */ |
9878760c RK |
2536 | |
2537 | int | |
a2369ed3 | 2538 | add_operand (rtx op, enum machine_mode mode) |
9878760c | 2539 | { |
2bfcf297 | 2540 | if (GET_CODE (op) == CONST_INT) |
e72247f4 DE |
2541 | return (CONST_OK_FOR_LETTER_P (INTVAL (op), 'I') |
2542 | || CONST_OK_FOR_LETTER_P (INTVAL (op), 'L')); | |
2bfcf297 DB |
2543 | |
2544 | return gpc_reg_operand (op, mode); | |
9878760c RK |
2545 | } |
2546 | ||
dcfedcd0 RK |
2547 | /* Return 1 if OP is a constant but not a valid add_operand. */ |
2548 | ||
2549 | int | |
a2369ed3 | 2550 | non_add_cint_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
dcfedcd0 RK |
2551 | { |
2552 | return (GET_CODE (op) == CONST_INT | |
e72247f4 DE |
2553 | && !CONST_OK_FOR_LETTER_P (INTVAL (op), 'I') |
2554 | && !CONST_OK_FOR_LETTER_P (INTVAL (op), 'L')); | |
dcfedcd0 RK |
2555 | } |
2556 | ||
9878760c RK |
2557 | /* Return 1 if the operand is a non-special register or a constant that |
2558 | can be used as the operand of an OR or XOR insn on the RS/6000. */ | |
2559 | ||
2560 | int | |
a2369ed3 | 2561 | logical_operand (rtx op, enum machine_mode mode) |
9878760c | 2562 | { |
40501e5f | 2563 | HOST_WIDE_INT opl, oph; |
1d328b19 | 2564 | |
dfbdccdb GK |
2565 | if (gpc_reg_operand (op, mode)) |
2566 | return 1; | |
1d328b19 | 2567 | |
dfbdccdb | 2568 | if (GET_CODE (op) == CONST_INT) |
40501e5f AM |
2569 | { |
2570 | opl = INTVAL (op) & GET_MODE_MASK (mode); | |
2571 | ||
2572 | #if HOST_BITS_PER_WIDE_INT <= 32 | |
2573 | if (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT && opl < 0) | |
2574 | return 0; | |
2575 | #endif | |
2576 | } | |
dfbdccdb GK |
2577 | else if (GET_CODE (op) == CONST_DOUBLE) |
2578 | { | |
1d328b19 | 2579 | if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT) |
40501e5f | 2580 | abort (); |
1d328b19 GK |
2581 | |
2582 | opl = CONST_DOUBLE_LOW (op); | |
2583 | oph = CONST_DOUBLE_HIGH (op); | |
40501e5f | 2584 | if (oph != 0) |
38886f37 | 2585 | return 0; |
dfbdccdb GK |
2586 | } |
2587 | else | |
2588 | return 0; | |
1d328b19 | 2589 | |
40501e5f AM |
2590 | return ((opl & ~ (unsigned HOST_WIDE_INT) 0xffff) == 0 |
2591 | || (opl & ~ (unsigned HOST_WIDE_INT) 0xffff0000) == 0); | |
9878760c RK |
2592 | } |
2593 | ||
dcfedcd0 | 2594 | /* Return 1 if C is a constant that is not a logical operand (as |
1d328b19 | 2595 | above), but could be split into one. */ |
dcfedcd0 RK |
2596 | |
2597 | int | |
a2369ed3 | 2598 | non_logical_cint_operand (rtx op, enum machine_mode mode) |
dcfedcd0 | 2599 | { |
dfbdccdb | 2600 | return ((GET_CODE (op) == CONST_INT || GET_CODE (op) == CONST_DOUBLE) |
1d328b19 GK |
2601 | && ! logical_operand (op, mode) |
2602 | && reg_or_logical_cint_operand (op, mode)); | |
dcfedcd0 RK |
2603 | } |
2604 | ||
19ba8161 | 2605 | /* Return 1 if C is a constant that can be encoded in a 32-bit mask on the |
9878760c RK |
2606 | RS/6000. It is if there are no more than two 1->0 or 0->1 transitions. |
2607 | Reject all ones and all zeros, since these should have been optimized | |
2608 | away and confuse the making of MB and ME. */ | |
2609 | ||
2610 | int | |
a2369ed3 | 2611 | mask_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
9878760c | 2612 | { |
02071907 | 2613 | HOST_WIDE_INT c, lsb; |
9878760c | 2614 | |
19ba8161 DE |
2615 | if (GET_CODE (op) != CONST_INT) |
2616 | return 0; | |
2617 | ||
2618 | c = INTVAL (op); | |
2619 | ||
57deb3a1 AM |
2620 | /* Fail in 64-bit mode if the mask wraps around because the upper |
2621 | 32-bits of the mask will all be 1s, contrary to GCC's internal view. */ | |
2622 | if (TARGET_POWERPC64 && (c & 0x80000001) == 0x80000001) | |
2623 | return 0; | |
2624 | ||
c5059423 AM |
2625 | /* We don't change the number of transitions by inverting, |
2626 | so make sure we start with the LS bit zero. */ | |
2627 | if (c & 1) | |
2628 | c = ~c; | |
2629 | ||
2630 | /* Reject all zeros or all ones. */ | |
2631 | if (c == 0) | |
9878760c RK |
2632 | return 0; |
2633 | ||
c5059423 AM |
2634 | /* Find the first transition. */ |
2635 | lsb = c & -c; | |
2636 | ||
2637 | /* Invert to look for a second transition. */ | |
2638 | c = ~c; | |
9878760c | 2639 | |
c5059423 AM |
2640 | /* Erase first transition. */ |
2641 | c &= -lsb; | |
9878760c | 2642 | |
c5059423 AM |
2643 | /* Find the second transition (if any). */ |
2644 | lsb = c & -c; | |
2645 | ||
2646 | /* Match if all the bits above are 1's (or c is zero). */ | |
2647 | return c == -lsb; | |
9878760c RK |
2648 | } |
2649 | ||
0ba1b2ff AM |
2650 | /* Return 1 for the PowerPC64 rlwinm corner case. */ |
2651 | ||
2652 | int | |
a2369ed3 | 2653 | mask_operand_wrap (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
0ba1b2ff AM |
2654 | { |
2655 | HOST_WIDE_INT c, lsb; | |
2656 | ||
2657 | if (GET_CODE (op) != CONST_INT) | |
2658 | return 0; | |
2659 | ||
2660 | c = INTVAL (op); | |
2661 | ||
2662 | if ((c & 0x80000001) != 0x80000001) | |
2663 | return 0; | |
2664 | ||
2665 | c = ~c; | |
2666 | if (c == 0) | |
2667 | return 0; | |
2668 | ||
2669 | lsb = c & -c; | |
2670 | c = ~c; | |
2671 | c &= -lsb; | |
2672 | lsb = c & -c; | |
2673 | return c == -lsb; | |
2674 | } | |
2675 | ||
a260abc9 DE |
2676 | /* Return 1 if the operand is a constant that is a PowerPC64 mask. |
2677 | It is if there are no more than one 1->0 or 0->1 transitions. | |
0ba1b2ff AM |
2678 | Reject all zeros, since zero should have been optimized away and |
2679 | confuses the making of MB and ME. */ | |
9878760c RK |
2680 | |
2681 | int | |
a2369ed3 | 2682 | mask64_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
a260abc9 DE |
2683 | { |
2684 | if (GET_CODE (op) == CONST_INT) | |
2685 | { | |
02071907 | 2686 | HOST_WIDE_INT c, lsb; |
a260abc9 | 2687 | |
c5059423 | 2688 | c = INTVAL (op); |
a260abc9 | 2689 | |
0ba1b2ff | 2690 | /* Reject all zeros. */ |
c5059423 | 2691 | if (c == 0) |
e2c953b6 DE |
2692 | return 0; |
2693 | ||
0ba1b2ff AM |
2694 | /* We don't change the number of transitions by inverting, |
2695 | so make sure we start with the LS bit zero. */ | |
2696 | if (c & 1) | |
2697 | c = ~c; | |
2698 | ||
c5059423 AM |
2699 | /* Find the transition, and check that all bits above are 1's. */ |
2700 | lsb = c & -c; | |
e3981aab DE |
2701 | |
2702 | /* Match if all the bits above are 1's (or c is zero). */ | |
c5059423 | 2703 | return c == -lsb; |
e2c953b6 | 2704 | } |
0ba1b2ff AM |
2705 | return 0; |
2706 | } | |
2707 | ||
2708 | /* Like mask64_operand, but allow up to three transitions. This | |
2709 | predicate is used by insn patterns that generate two rldicl or | |
2710 | rldicr machine insns. */ | |
2711 | ||
2712 | int | |
a2369ed3 | 2713 | mask64_2_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
0ba1b2ff AM |
2714 | { |
2715 | if (GET_CODE (op) == CONST_INT) | |
a260abc9 | 2716 | { |
0ba1b2ff | 2717 | HOST_WIDE_INT c, lsb; |
a260abc9 | 2718 | |
0ba1b2ff | 2719 | c = INTVAL (op); |
a260abc9 | 2720 | |
0ba1b2ff AM |
2721 | /* Disallow all zeros. */ |
2722 | if (c == 0) | |
2723 | return 0; | |
a260abc9 | 2724 | |
0ba1b2ff AM |
2725 | /* We don't change the number of transitions by inverting, |
2726 | so make sure we start with the LS bit zero. */ | |
2727 | if (c & 1) | |
2728 | c = ~c; | |
a260abc9 | 2729 | |
0ba1b2ff AM |
2730 | /* Find the first transition. */ |
2731 | lsb = c & -c; | |
a260abc9 | 2732 | |
0ba1b2ff AM |
2733 | /* Invert to look for a second transition. */ |
2734 | c = ~c; | |
2735 | ||
2736 | /* Erase first transition. */ | |
2737 | c &= -lsb; | |
2738 | ||
2739 | /* Find the second transition. */ | |
2740 | lsb = c & -c; | |
2741 | ||
2742 | /* Invert to look for a third transition. */ | |
2743 | c = ~c; | |
2744 | ||
2745 | /* Erase second transition. */ | |
2746 | c &= -lsb; | |
2747 | ||
2748 | /* Find the third transition (if any). */ | |
2749 | lsb = c & -c; | |
2750 | ||
2751 | /* Match if all the bits above are 1's (or c is zero). */ | |
2752 | return c == -lsb; | |
2753 | } | |
2754 | return 0; | |
2755 | } | |
2756 | ||
2757 | /* Generates shifts and masks for a pair of rldicl or rldicr insns to | |
2758 | implement ANDing by the mask IN. */ | |
2759 | void | |
a2369ed3 | 2760 | build_mask64_2_operands (rtx in, rtx *out) |
0ba1b2ff AM |
2761 | { |
2762 | #if HOST_BITS_PER_WIDE_INT >= 64 | |
2763 | unsigned HOST_WIDE_INT c, lsb, m1, m2; | |
2764 | int shift; | |
2765 | ||
2766 | if (GET_CODE (in) != CONST_INT) | |
2767 | abort (); | |
2768 | ||
2769 | c = INTVAL (in); | |
2770 | if (c & 1) | |
2771 | { | |
2772 | /* Assume c initially something like 0x00fff000000fffff. The idea | |
2773 | is to rotate the word so that the middle ^^^^^^ group of zeros | |
2774 | is at the MS end and can be cleared with an rldicl mask. We then | |
2775 | rotate back and clear off the MS ^^ group of zeros with a | |
2776 | second rldicl. */ | |
2777 | c = ~c; /* c == 0xff000ffffff00000 */ | |
2778 | lsb = c & -c; /* lsb == 0x0000000000100000 */ | |
2779 | m1 = -lsb; /* m1 == 0xfffffffffff00000 */ | |
2780 | c = ~c; /* c == 0x00fff000000fffff */ | |
2781 | c &= -lsb; /* c == 0x00fff00000000000 */ | |
2782 | lsb = c & -c; /* lsb == 0x0000100000000000 */ | |
2783 | c = ~c; /* c == 0xff000fffffffffff */ | |
2784 | c &= -lsb; /* c == 0xff00000000000000 */ | |
2785 | shift = 0; | |
2786 | while ((lsb >>= 1) != 0) | |
2787 | shift++; /* shift == 44 on exit from loop */ | |
2788 | m1 <<= 64 - shift; /* m1 == 0xffffff0000000000 */ | |
2789 | m1 = ~m1; /* m1 == 0x000000ffffffffff */ | |
2790 | m2 = ~c; /* m2 == 0x00ffffffffffffff */ | |
a260abc9 DE |
2791 | } |
2792 | else | |
0ba1b2ff AM |
2793 | { |
2794 | /* Assume c initially something like 0xff000f0000000000. The idea | |
2795 | is to rotate the word so that the ^^^ middle group of zeros | |
2796 | is at the LS end and can be cleared with an rldicr mask. We then | |
2797 | rotate back and clear off the LS group of ^^^^^^^^^^ zeros with | |
2798 | a second rldicr. */ | |
2799 | lsb = c & -c; /* lsb == 0x0000010000000000 */ | |
2800 | m2 = -lsb; /* m2 == 0xffffff0000000000 */ | |
2801 | c = ~c; /* c == 0x00fff0ffffffffff */ | |
2802 | c &= -lsb; /* c == 0x00fff00000000000 */ | |
2803 | lsb = c & -c; /* lsb == 0x0000100000000000 */ | |
2804 | c = ~c; /* c == 0xff000fffffffffff */ | |
2805 | c &= -lsb; /* c == 0xff00000000000000 */ | |
2806 | shift = 0; | |
2807 | while ((lsb >>= 1) != 0) | |
2808 | shift++; /* shift == 44 on exit from loop */ | |
2809 | m1 = ~c; /* m1 == 0x00ffffffffffffff */ | |
2810 | m1 >>= shift; /* m1 == 0x0000000000000fff */ | |
2811 | m1 = ~m1; /* m1 == 0xfffffffffffff000 */ | |
2812 | } | |
2813 | ||
2814 | /* Note that when we only have two 0->1 and 1->0 transitions, one of the | |
2815 | masks will be all 1's. We are guaranteed more than one transition. */ | |
2816 | out[0] = GEN_INT (64 - shift); | |
2817 | out[1] = GEN_INT (m1); | |
2818 | out[2] = GEN_INT (shift); | |
2819 | out[3] = GEN_INT (m2); | |
2820 | #else | |
045572c7 GK |
2821 | (void)in; |
2822 | (void)out; | |
0ba1b2ff AM |
2823 | abort (); |
2824 | #endif | |
a260abc9 DE |
2825 | } |
2826 | ||
2827 | /* Return 1 if the operand is either a non-special register or a constant | |
2828 | that can be used as the operand of a PowerPC64 logical AND insn. */ | |
2829 | ||
2830 | int | |
a2369ed3 | 2831 | and64_operand (rtx op, enum machine_mode mode) |
9878760c | 2832 | { |
a4f6c312 | 2833 | if (fixed_regs[CR0_REGNO]) /* CR0 not available, don't do andi./andis. */ |
52d3af72 DE |
2834 | return (gpc_reg_operand (op, mode) || mask64_operand (op, mode)); |
2835 | ||
2836 | return (logical_operand (op, mode) || mask64_operand (op, mode)); | |
9878760c RK |
2837 | } |
2838 | ||
0ba1b2ff AM |
2839 | /* Like the above, but also match constants that can be implemented |
2840 | with two rldicl or rldicr insns. */ | |
2841 | ||
2842 | int | |
a2369ed3 | 2843 | and64_2_operand (rtx op, enum machine_mode mode) |
0ba1b2ff | 2844 | { |
a3c9585f | 2845 | if (fixed_regs[CR0_REGNO]) /* CR0 not available, don't do andi./andis. */ |
0ba1b2ff AM |
2846 | return gpc_reg_operand (op, mode) || mask64_2_operand (op, mode); |
2847 | ||
2848 | return logical_operand (op, mode) || mask64_2_operand (op, mode); | |
2849 | } | |
2850 | ||
a260abc9 DE |
2851 | /* Return 1 if the operand is either a non-special register or a |
2852 | constant that can be used as the operand of an RS/6000 logical AND insn. */ | |
dcfedcd0 RK |
2853 | |
2854 | int | |
a2369ed3 | 2855 | and_operand (rtx op, enum machine_mode mode) |
dcfedcd0 | 2856 | { |
a4f6c312 | 2857 | if (fixed_regs[CR0_REGNO]) /* CR0 not available, don't do andi./andis. */ |
52d3af72 DE |
2858 | return (gpc_reg_operand (op, mode) || mask_operand (op, mode)); |
2859 | ||
2860 | return (logical_operand (op, mode) || mask_operand (op, mode)); | |
dcfedcd0 RK |
2861 | } |
2862 | ||
9878760c RK |
2863 | /* Return 1 if the operand is a general register or memory operand. */ |
2864 | ||
2865 | int | |
a2369ed3 | 2866 | reg_or_mem_operand (rtx op, enum machine_mode mode) |
9878760c | 2867 | { |
b6c9286a MM |
2868 | return (gpc_reg_operand (op, mode) |
2869 | || memory_operand (op, mode) | |
4c81e946 | 2870 | || macho_lo_sum_memory_operand (op, mode) |
b6c9286a | 2871 | || volatile_mem_operand (op, mode)); |
9878760c RK |
2872 | } |
2873 | ||
a7a813f7 | 2874 | /* Return 1 if the operand is a general register or memory operand without |
3cb999d8 | 2875 | pre_inc or pre_dec which produces invalid form of PowerPC lwa |
a7a813f7 RK |
2876 | instruction. */ |
2877 | ||
2878 | int | |
a2369ed3 | 2879 | lwa_operand (rtx op, enum machine_mode mode) |
a7a813f7 RK |
2880 | { |
2881 | rtx inner = op; | |
2882 | ||
2883 | if (reload_completed && GET_CODE (inner) == SUBREG) | |
2884 | inner = SUBREG_REG (inner); | |
f676971a | 2885 | |
a7a813f7 RK |
2886 | return gpc_reg_operand (inner, mode) |
2887 | || (memory_operand (inner, mode) | |
2888 | && GET_CODE (XEXP (inner, 0)) != PRE_INC | |
6a40a9d6 DE |
2889 | && GET_CODE (XEXP (inner, 0)) != PRE_DEC |
2890 | && (GET_CODE (XEXP (inner, 0)) != PLUS | |
e903c96a DE |
2891 | || GET_CODE (XEXP (XEXP (inner, 0), 1)) != CONST_INT |
2892 | || INTVAL (XEXP (XEXP (inner, 0), 1)) % 4 == 0)); | |
a7a813f7 RK |
2893 | } |
2894 | ||
cc4d5fec JH |
2895 | /* Return 1 if the operand, used inside a MEM, is a SYMBOL_REF. */ |
2896 | ||
2897 | int | |
a2369ed3 | 2898 | symbol_ref_operand (rtx op, enum machine_mode mode) |
cc4d5fec JH |
2899 | { |
2900 | if (mode != VOIDmode && GET_MODE (op) != mode) | |
2901 | return 0; | |
2902 | ||
473f51b6 DE |
2903 | return (GET_CODE (op) == SYMBOL_REF |
2904 | && (DEFAULT_ABI != ABI_AIX || SYMBOL_REF_FUNCTION_P (op))); | |
cc4d5fec JH |
2905 | } |
2906 | ||
9878760c | 2907 | /* Return 1 if the operand, used inside a MEM, is a valid first argument |
cc4d5fec | 2908 | to CALL. This is a SYMBOL_REF, a pseudo-register, LR or CTR. */ |
9878760c RK |
2909 | |
2910 | int | |
a2369ed3 | 2911 | call_operand (rtx op, enum machine_mode mode) |
9878760c RK |
2912 | { |
2913 | if (mode != VOIDmode && GET_MODE (op) != mode) | |
2914 | return 0; | |
2915 | ||
2916 | return (GET_CODE (op) == SYMBOL_REF | |
cc4d5fec JH |
2917 | || (GET_CODE (op) == REG |
2918 | && (REGNO (op) == LINK_REGISTER_REGNUM | |
2919 | || REGNO (op) == COUNT_REGISTER_REGNUM | |
2920 | || REGNO (op) >= FIRST_PSEUDO_REGISTER))); | |
9878760c RK |
2921 | } |
2922 | ||
2af3d377 | 2923 | /* Return 1 if the operand is a SYMBOL_REF for a function known to be in |
d1908feb | 2924 | this file. */ |
2af3d377 RK |
2925 | |
2926 | int | |
f676971a | 2927 | current_file_function_operand (rtx op, |
c4ad648e | 2928 | enum machine_mode mode ATTRIBUTE_UNUSED) |
2af3d377 | 2929 | { |
473f51b6 DE |
2930 | return (GET_CODE (op) == SYMBOL_REF |
2931 | && (DEFAULT_ABI != ABI_AIX || SYMBOL_REF_FUNCTION_P (op)) | |
2932 | && (SYMBOL_REF_LOCAL_P (op) | |
2933 | || (op == XEXP (DECL_RTL (current_function_decl), 0)))); | |
2af3d377 RK |
2934 | } |
2935 | ||
9878760c RK |
2936 | /* Return 1 if this operand is a valid input for a move insn. */ |
2937 | ||
2938 | int | |
a2369ed3 | 2939 | input_operand (rtx op, enum machine_mode mode) |
9878760c | 2940 | { |
eb4e8003 | 2941 | /* Memory is always valid. */ |
9878760c RK |
2942 | if (memory_operand (op, mode)) |
2943 | return 1; | |
2944 | ||
eb4e8003 RK |
2945 | /* For floating-point, easy constants are valid. */ |
2946 | if (GET_MODE_CLASS (mode) == MODE_FLOAT | |
2947 | && CONSTANT_P (op) | |
2948 | && easy_fp_constant (op, mode)) | |
2949 | return 1; | |
2950 | ||
4e74d8ec MM |
2951 | /* Allow any integer constant. */ |
2952 | if (GET_MODE_CLASS (mode) == MODE_INT | |
e675f625 | 2953 | && (GET_CODE (op) == CONST_INT |
e675f625 | 2954 | || GET_CODE (op) == CONST_DOUBLE)) |
4e74d8ec MM |
2955 | return 1; |
2956 | ||
d744e06e AH |
2957 | /* Allow easy vector constants. */ |
2958 | if (GET_CODE (op) == CONST_VECTOR | |
2959 | && easy_vector_constant (op, mode)) | |
2960 | return 1; | |
2961 | ||
eb4e8003 RK |
2962 | /* For floating-point or multi-word mode, the only remaining valid type |
2963 | is a register. */ | |
9878760c RK |
2964 | if (GET_MODE_CLASS (mode) == MODE_FLOAT |
2965 | || GET_MODE_SIZE (mode) > UNITS_PER_WORD) | |
eb4e8003 | 2966 | return register_operand (op, mode); |
9878760c | 2967 | |
88fe15a1 RK |
2968 | /* The only cases left are integral modes one word or smaller (we |
2969 | do not get called for MODE_CC values). These can be in any | |
2970 | register. */ | |
2971 | if (register_operand (op, mode)) | |
a8b3aeda | 2972 | return 1; |
88fe15a1 | 2973 | |
84cf9dda | 2974 | /* A SYMBOL_REF referring to the TOC is valid. */ |
4d588c14 | 2975 | if (legitimate_constant_pool_address_p (op)) |
84cf9dda RK |
2976 | return 1; |
2977 | ||
9ebbca7d | 2978 | /* A constant pool expression (relative to the TOC) is valid */ |
4d588c14 | 2979 | if (toc_relative_expr_p (op)) |
b6c9286a MM |
2980 | return 1; |
2981 | ||
88228c4b MM |
2982 | /* V.4 allows SYMBOL_REFs and CONSTs that are in the small data region |
2983 | to be valid. */ | |
f607bc57 | 2984 | if (DEFAULT_ABI == ABI_V4 |
88228c4b MM |
2985 | && (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST) |
2986 | && small_data_operand (op, Pmode)) | |
2987 | return 1; | |
2988 | ||
042259f2 | 2989 | return 0; |
9878760c | 2990 | } |
7509c759 | 2991 | |
95727fb8 AP |
2992 | |
2993 | /* Darwin, AIX increases natural record alignment to doubleword if the first | |
2994 | field is an FP double while the FP fields remain word aligned. */ | |
2995 | ||
19d66194 | 2996 | unsigned int |
95727fb8 AP |
2997 | rs6000_special_round_type_align (tree type, int computed, int specified) |
2998 | { | |
2999 | tree field = TYPE_FIELDS (type); | |
95727fb8 AP |
3000 | |
3001 | /* Skip all the static variables only if ABI is greater than | |
71cc389b | 3002 | 1 or equal to 0. */ |
3ce5437a | 3003 | while (field != NULL && TREE_CODE (field) == VAR_DECL) |
95727fb8 AP |
3004 | field = TREE_CHAIN (field); |
3005 | ||
3ce5437a | 3006 | if (field == NULL || field == type || DECL_MODE (field) != DFmode) |
95727fb8 AP |
3007 | return MAX (computed, specified); |
3008 | ||
3009 | return MAX (MAX (computed, specified), 64); | |
3010 | } | |
3011 | ||
a4f6c312 | 3012 | /* Return 1 for an operand in small memory on V.4/eabi. */ |
7509c759 MM |
3013 | |
3014 | int | |
f676971a | 3015 | small_data_operand (rtx op ATTRIBUTE_UNUSED, |
a2369ed3 | 3016 | enum machine_mode mode ATTRIBUTE_UNUSED) |
7509c759 | 3017 | { |
38c1f2d7 | 3018 | #if TARGET_ELF |
5f59ecb7 | 3019 | rtx sym_ref; |
7509c759 | 3020 | |
d9407988 | 3021 | if (rs6000_sdata == SDATA_NONE || rs6000_sdata == SDATA_DATA) |
a54d04b7 | 3022 | return 0; |
a54d04b7 | 3023 | |
f607bc57 | 3024 | if (DEFAULT_ABI != ABI_V4) |
7509c759 MM |
3025 | return 0; |
3026 | ||
88228c4b MM |
3027 | if (GET_CODE (op) == SYMBOL_REF) |
3028 | sym_ref = op; | |
3029 | ||
3030 | else if (GET_CODE (op) != CONST | |
3031 | || GET_CODE (XEXP (op, 0)) != PLUS | |
3032 | || GET_CODE (XEXP (XEXP (op, 0), 0)) != SYMBOL_REF | |
3033 | || GET_CODE (XEXP (XEXP (op, 0), 1)) != CONST_INT) | |
7509c759 MM |
3034 | return 0; |
3035 | ||
88228c4b | 3036 | else |
dbf55e53 MM |
3037 | { |
3038 | rtx sum = XEXP (op, 0); | |
3039 | HOST_WIDE_INT summand; | |
3040 | ||
3041 | /* We have to be careful here, because it is the referenced address | |
c4ad648e | 3042 | that must be 32k from _SDA_BASE_, not just the symbol. */ |
dbf55e53 | 3043 | summand = INTVAL (XEXP (sum, 1)); |
307b599c | 3044 | if (summand < 0 || (unsigned HOST_WIDE_INT) summand > g_switch_value) |
dbf55e53 MM |
3045 | return 0; |
3046 | ||
3047 | sym_ref = XEXP (sum, 0); | |
3048 | } | |
88228c4b | 3049 | |
20bfcd69 | 3050 | return SYMBOL_REF_SMALL_P (sym_ref); |
d9407988 MM |
3051 | #else |
3052 | return 0; | |
3053 | #endif | |
7509c759 | 3054 | } |
46c07df8 | 3055 | |
d2288d5d HP |
3056 | /* Return true, if operand is a memory operand and has a |
3057 | displacement divisible by 4. */ | |
3058 | ||
3059 | int | |
3060 | word_offset_memref_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) | |
3061 | { | |
3062 | rtx addr; | |
3063 | int off = 0; | |
3064 | ||
3065 | if (!memory_operand (op, mode)) | |
3066 | return 0; | |
3067 | ||
3068 | addr = XEXP (op, 0); | |
3069 | if (GET_CODE (addr) == PLUS | |
3070 | && GET_CODE (XEXP (addr, 0)) == REG | |
3071 | && GET_CODE (XEXP (addr, 1)) == CONST_INT) | |
3072 | off = INTVAL (XEXP (addr, 1)); | |
3073 | ||
3074 | return (off % 4) == 0; | |
3075 | } | |
3076 | ||
3a1f863f | 3077 | /* Return true if either operand is a general purpose register. */ |
46c07df8 | 3078 | |
3a1f863f DE |
3079 | bool |
3080 | gpr_or_gpr_p (rtx op0, rtx op1) | |
46c07df8 | 3081 | { |
3a1f863f DE |
3082 | return ((REG_P (op0) && INT_REGNO_P (REGNO (op0))) |
3083 | || (REG_P (op1) && INT_REGNO_P (REGNO (op1)))); | |
46c07df8 HP |
3084 | } |
3085 | ||
9ebbca7d | 3086 | \f |
4d588c14 RH |
3087 | /* Subroutines of rs6000_legitimize_address and rs6000_legitimate_address. */ |
3088 | ||
f676971a EC |
3089 | static int |
3090 | constant_pool_expr_1 (rtx op, int *have_sym, int *have_toc) | |
9ebbca7d | 3091 | { |
f676971a | 3092 | switch (GET_CODE(op)) |
9ebbca7d GK |
3093 | { |
3094 | case SYMBOL_REF: | |
c4501e62 JJ |
3095 | if (RS6000_SYMBOL_REF_TLS_P (op)) |
3096 | return 0; | |
3097 | else if (CONSTANT_POOL_ADDRESS_P (op)) | |
a4f6c312 SS |
3098 | { |
3099 | if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (op), Pmode)) | |
3100 | { | |
3101 | *have_sym = 1; | |
3102 | return 1; | |
3103 | } | |
3104 | else | |
3105 | return 0; | |
3106 | } | |
3107 | else if (! strcmp (XSTR (op, 0), toc_label_name)) | |
3108 | { | |
3109 | *have_toc = 1; | |
3110 | return 1; | |
3111 | } | |
3112 | else | |
3113 | return 0; | |
9ebbca7d GK |
3114 | case PLUS: |
3115 | case MINUS: | |
c1f11548 DE |
3116 | return (constant_pool_expr_1 (XEXP (op, 0), have_sym, have_toc) |
3117 | && constant_pool_expr_1 (XEXP (op, 1), have_sym, have_toc)); | |
9ebbca7d | 3118 | case CONST: |
a4f6c312 | 3119 | return constant_pool_expr_1 (XEXP (op, 0), have_sym, have_toc); |
9ebbca7d | 3120 | case CONST_INT: |
a4f6c312 | 3121 | return 1; |
9ebbca7d | 3122 | default: |
a4f6c312 | 3123 | return 0; |
9ebbca7d GK |
3124 | } |
3125 | } | |
3126 | ||
4d588c14 | 3127 | static bool |
a2369ed3 | 3128 | constant_pool_expr_p (rtx op) |
9ebbca7d GK |
3129 | { |
3130 | int have_sym = 0; | |
3131 | int have_toc = 0; | |
3132 | return constant_pool_expr_1 (op, &have_sym, &have_toc) && have_sym; | |
3133 | } | |
3134 | ||
4d588c14 | 3135 | static bool |
a2369ed3 | 3136 | toc_relative_expr_p (rtx op) |
9ebbca7d | 3137 | { |
4d588c14 RH |
3138 | int have_sym = 0; |
3139 | int have_toc = 0; | |
3140 | return constant_pool_expr_1 (op, &have_sym, &have_toc) && have_toc; | |
3141 | } | |
3142 | ||
4d588c14 | 3143 | bool |
a2369ed3 | 3144 | legitimate_constant_pool_address_p (rtx x) |
4d588c14 RH |
3145 | { |
3146 | return (TARGET_TOC | |
3147 | && GET_CODE (x) == PLUS | |
3148 | && GET_CODE (XEXP (x, 0)) == REG | |
3149 | && (TARGET_MINIMAL_TOC || REGNO (XEXP (x, 0)) == TOC_REGISTER) | |
3150 | && constant_pool_expr_p (XEXP (x, 1))); | |
3151 | } | |
3152 | ||
3153 | static bool | |
a2369ed3 | 3154 | legitimate_small_data_p (enum machine_mode mode, rtx x) |
4d588c14 RH |
3155 | { |
3156 | return (DEFAULT_ABI == ABI_V4 | |
3157 | && !flag_pic && !TARGET_TOC | |
3158 | && (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST) | |
3159 | && small_data_operand (x, mode)); | |
3160 | } | |
3161 | ||
60cdabab DE |
3162 | /* SPE offset addressing is limited to 5-bits worth of double words. */ |
3163 | #define SPE_CONST_OFFSET_OK(x) (((x) & ~0xf8) == 0) | |
3164 | ||
76d2b81d DJ |
3165 | bool |
3166 | rs6000_legitimate_offset_address_p (enum machine_mode mode, rtx x, int strict) | |
4d588c14 RH |
3167 | { |
3168 | unsigned HOST_WIDE_INT offset, extra; | |
3169 | ||
3170 | if (GET_CODE (x) != PLUS) | |
3171 | return false; | |
3172 | if (GET_CODE (XEXP (x, 0)) != REG) | |
3173 | return false; | |
3174 | if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict)) | |
3175 | return false; | |
60cdabab DE |
3176 | if (legitimate_constant_pool_address_p (x)) |
3177 | return true; | |
4d588c14 RH |
3178 | if (GET_CODE (XEXP (x, 1)) != CONST_INT) |
3179 | return false; | |
3180 | ||
3181 | offset = INTVAL (XEXP (x, 1)); | |
3182 | extra = 0; | |
3183 | switch (mode) | |
3184 | { | |
3185 | case V16QImode: | |
3186 | case V8HImode: | |
3187 | case V4SFmode: | |
3188 | case V4SImode: | |
3189 | /* AltiVec vector modes. Only reg+reg addressing is valid here, | |
3190 | which leaves the only valid constant offset of zero, which by | |
3191 | canonicalization rules is also invalid. */ | |
3192 | return false; | |
3193 | ||
3194 | case V4HImode: | |
3195 | case V2SImode: | |
3196 | case V1DImode: | |
3197 | case V2SFmode: | |
3198 | /* SPE vector modes. */ | |
3199 | return SPE_CONST_OFFSET_OK (offset); | |
3200 | ||
3201 | case DFmode: | |
4d4cbc0e AH |
3202 | if (TARGET_E500_DOUBLE) |
3203 | return SPE_CONST_OFFSET_OK (offset); | |
3204 | ||
4d588c14 | 3205 | case DImode: |
3364872d | 3206 | if (mode == DFmode || !TARGET_POWERPC64) |
4d588c14 RH |
3207 | extra = 4; |
3208 | else if (offset & 3) | |
3209 | return false; | |
3210 | break; | |
3211 | ||
3212 | case TFmode: | |
3213 | case TImode: | |
3364872d | 3214 | if (mode == TFmode || !TARGET_POWERPC64) |
4d588c14 RH |
3215 | extra = 12; |
3216 | else if (offset & 3) | |
3217 | return false; | |
3218 | else | |
3219 | extra = 8; | |
3220 | break; | |
3221 | ||
3222 | default: | |
3223 | break; | |
3224 | } | |
3225 | ||
b1917422 AM |
3226 | offset += 0x8000; |
3227 | return (offset < 0x10000) && (offset + extra < 0x10000); | |
4d588c14 RH |
3228 | } |
3229 | ||
3230 | static bool | |
a2369ed3 | 3231 | legitimate_indexed_address_p (rtx x, int strict) |
4d588c14 RH |
3232 | { |
3233 | rtx op0, op1; | |
3234 | ||
3235 | if (GET_CODE (x) != PLUS) | |
3236 | return false; | |
850e8d3d | 3237 | |
4d588c14 RH |
3238 | op0 = XEXP (x, 0); |
3239 | op1 = XEXP (x, 1); | |
3240 | ||
3241 | if (!REG_P (op0) || !REG_P (op1)) | |
3242 | return false; | |
3243 | ||
3244 | return ((INT_REG_OK_FOR_BASE_P (op0, strict) | |
3245 | && INT_REG_OK_FOR_INDEX_P (op1, strict)) | |
3246 | || (INT_REG_OK_FOR_BASE_P (op1, strict) | |
3247 | && INT_REG_OK_FOR_INDEX_P (op0, strict))); | |
9ebbca7d GK |
3248 | } |
3249 | ||
4d588c14 | 3250 | static inline bool |
a2369ed3 | 3251 | legitimate_indirect_address_p (rtx x, int strict) |
4d588c14 RH |
3252 | { |
3253 | return GET_CODE (x) == REG && INT_REG_OK_FOR_BASE_P (x, strict); | |
3254 | } | |
3255 | ||
4c81e946 FJ |
3256 | static bool |
3257 | macho_lo_sum_memory_operand (rtx x, enum machine_mode mode) | |
3258 | { | |
c4ad648e AM |
3259 | if (!TARGET_MACHO || !flag_pic |
3260 | || mode != SImode || GET_CODE(x) != MEM) | |
3261 | return false; | |
3262 | x = XEXP (x, 0); | |
4c81e946 FJ |
3263 | |
3264 | if (GET_CODE (x) != LO_SUM) | |
3265 | return false; | |
3266 | if (GET_CODE (XEXP (x, 0)) != REG) | |
3267 | return false; | |
3268 | if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), 0)) | |
3269 | return false; | |
3270 | x = XEXP (x, 1); | |
3271 | ||
3272 | return CONSTANT_P (x); | |
3273 | } | |
3274 | ||
4d588c14 | 3275 | static bool |
a2369ed3 | 3276 | legitimate_lo_sum_address_p (enum machine_mode mode, rtx x, int strict) |
4d588c14 RH |
3277 | { |
3278 | if (GET_CODE (x) != LO_SUM) | |
3279 | return false; | |
3280 | if (GET_CODE (XEXP (x, 0)) != REG) | |
3281 | return false; | |
3282 | if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict)) | |
3283 | return false; | |
3284 | x = XEXP (x, 1); | |
3285 | ||
8622e235 | 3286 | if (TARGET_ELF || TARGET_MACHO) |
4d588c14 | 3287 | { |
a29077da | 3288 | if (DEFAULT_ABI != ABI_AIX && DEFAULT_ABI != ABI_DARWIN && flag_pic) |
4d588c14 RH |
3289 | return false; |
3290 | if (TARGET_TOC) | |
3291 | return false; | |
3292 | if (GET_MODE_NUNITS (mode) != 1) | |
3293 | return false; | |
c1e55850 | 3294 | if (GET_MODE_BITSIZE (mode) > 64) |
4d588c14 RH |
3295 | return false; |
3296 | ||
3297 | return CONSTANT_P (x); | |
3298 | } | |
3299 | ||
3300 | return false; | |
3301 | } | |
3302 | ||
3303 | ||
9ebbca7d GK |
3304 | /* Try machine-dependent ways of modifying an illegitimate address |
3305 | to be legitimate. If we find one, return the new, valid address. | |
3306 | This is used from only one place: `memory_address' in explow.c. | |
3307 | ||
a4f6c312 SS |
3308 | OLDX is the address as it was before break_out_memory_refs was |
3309 | called. In some cases it is useful to look at this to decide what | |
3310 | needs to be done. | |
9ebbca7d | 3311 | |
a4f6c312 | 3312 | MODE is passed so that this function can use GO_IF_LEGITIMATE_ADDRESS. |
9ebbca7d | 3313 | |
a4f6c312 SS |
3314 | It is always safe for this function to do nothing. It exists to |
3315 | recognize opportunities to optimize the output. | |
9ebbca7d GK |
3316 | |
3317 | On RS/6000, first check for the sum of a register with a constant | |
3318 | integer that is out of range. If so, generate code to add the | |
3319 | constant with the low-order 16 bits masked to the register and force | |
3320 | this result into another register (this can be done with `cau'). | |
3321 | Then generate an address of REG+(CONST&0xffff), allowing for the | |
3322 | possibility of bit 16 being a one. | |
3323 | ||
3324 | Then check for the sum of a register and something not constant, try to | |
3325 | load the other things into a register and return the sum. */ | |
4d588c14 | 3326 | |
9ebbca7d | 3327 | rtx |
a2369ed3 DJ |
3328 | rs6000_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED, |
3329 | enum machine_mode mode) | |
0ac081f6 | 3330 | { |
c4501e62 JJ |
3331 | if (GET_CODE (x) == SYMBOL_REF) |
3332 | { | |
3333 | enum tls_model model = SYMBOL_REF_TLS_MODEL (x); | |
3334 | if (model != 0) | |
3335 | return rs6000_legitimize_tls_address (x, model); | |
3336 | } | |
3337 | ||
f676971a | 3338 | if (GET_CODE (x) == PLUS |
9ebbca7d GK |
3339 | && GET_CODE (XEXP (x, 0)) == REG |
3340 | && GET_CODE (XEXP (x, 1)) == CONST_INT | |
3341 | && (unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 1)) + 0x8000) >= 0x10000) | |
f676971a | 3342 | { |
9ebbca7d GK |
3343 | HOST_WIDE_INT high_int, low_int; |
3344 | rtx sum; | |
a65c591c DE |
3345 | low_int = ((INTVAL (XEXP (x, 1)) & 0xffff) ^ 0x8000) - 0x8000; |
3346 | high_int = INTVAL (XEXP (x, 1)) - low_int; | |
9ebbca7d GK |
3347 | sum = force_operand (gen_rtx_PLUS (Pmode, XEXP (x, 0), |
3348 | GEN_INT (high_int)), 0); | |
3349 | return gen_rtx_PLUS (Pmode, sum, GEN_INT (low_int)); | |
3350 | } | |
f676971a | 3351 | else if (GET_CODE (x) == PLUS |
9ebbca7d GK |
3352 | && GET_CODE (XEXP (x, 0)) == REG |
3353 | && GET_CODE (XEXP (x, 1)) != CONST_INT | |
6ac7bf2c | 3354 | && GET_MODE_NUNITS (mode) == 1 |
a3170dc6 AH |
3355 | && ((TARGET_HARD_FLOAT && TARGET_FPRS) |
3356 | || TARGET_POWERPC64 | |
4d4cbc0e | 3357 | || ((mode != DFmode || TARGET_E500_DOUBLE) && mode != TFmode)) |
9ebbca7d GK |
3358 | && (TARGET_POWERPC64 || mode != DImode) |
3359 | && mode != TImode) | |
3360 | { | |
3361 | return gen_rtx_PLUS (Pmode, XEXP (x, 0), | |
3362 | force_reg (Pmode, force_operand (XEXP (x, 1), 0))); | |
3363 | } | |
0ac081f6 AH |
3364 | else if (ALTIVEC_VECTOR_MODE (mode)) |
3365 | { | |
3366 | rtx reg; | |
3367 | ||
3368 | /* Make sure both operands are registers. */ | |
3369 | if (GET_CODE (x) == PLUS) | |
9f85ed45 | 3370 | return gen_rtx_PLUS (Pmode, force_reg (Pmode, XEXP (x, 0)), |
0ac081f6 AH |
3371 | force_reg (Pmode, XEXP (x, 1))); |
3372 | ||
3373 | reg = force_reg (Pmode, x); | |
3374 | return reg; | |
3375 | } | |
4d4cbc0e AH |
3376 | else if (SPE_VECTOR_MODE (mode) |
3377 | || (TARGET_E500_DOUBLE && mode == DFmode)) | |
a3170dc6 AH |
3378 | { |
3379 | /* We accept [reg + reg] and [reg + OFFSET]. */ | |
3380 | ||
3381 | if (GET_CODE (x) == PLUS) | |
c4ad648e AM |
3382 | { |
3383 | rtx op1 = XEXP (x, 0); | |
3384 | rtx op2 = XEXP (x, 1); | |
a3170dc6 | 3385 | |
c4ad648e | 3386 | op1 = force_reg (Pmode, op1); |
a3170dc6 | 3387 | |
c4ad648e AM |
3388 | if (GET_CODE (op2) != REG |
3389 | && (GET_CODE (op2) != CONST_INT | |
3390 | || !SPE_CONST_OFFSET_OK (INTVAL (op2)))) | |
3391 | op2 = force_reg (Pmode, op2); | |
a3170dc6 | 3392 | |
c4ad648e AM |
3393 | return gen_rtx_PLUS (Pmode, op1, op2); |
3394 | } | |
a3170dc6 AH |
3395 | |
3396 | return force_reg (Pmode, x); | |
3397 | } | |
f1384257 AM |
3398 | else if (TARGET_ELF |
3399 | && TARGET_32BIT | |
3400 | && TARGET_NO_TOC | |
3401 | && ! flag_pic | |
9ebbca7d | 3402 | && GET_CODE (x) != CONST_INT |
f676971a | 3403 | && GET_CODE (x) != CONST_DOUBLE |
9ebbca7d | 3404 | && CONSTANT_P (x) |
6ac7bf2c GK |
3405 | && GET_MODE_NUNITS (mode) == 1 |
3406 | && (GET_MODE_BITSIZE (mode) <= 32 | |
a3170dc6 | 3407 | || ((TARGET_HARD_FLOAT && TARGET_FPRS) && mode == DFmode))) |
9ebbca7d GK |
3408 | { |
3409 | rtx reg = gen_reg_rtx (Pmode); | |
8a1977f3 GK |
3410 | emit_insn (gen_elf_high (reg, x)); |
3411 | return gen_rtx_LO_SUM (Pmode, reg, x); | |
9ebbca7d | 3412 | } |
ee890fe2 SS |
3413 | else if (TARGET_MACHO && TARGET_32BIT && TARGET_NO_TOC |
3414 | && ! flag_pic | |
ab82a49f AP |
3415 | #if TARGET_MACHO |
3416 | && ! MACHO_DYNAMIC_NO_PIC_P | |
3417 | #endif | |
ee890fe2 | 3418 | && GET_CODE (x) != CONST_INT |
f676971a | 3419 | && GET_CODE (x) != CONST_DOUBLE |
ee890fe2 | 3420 | && CONSTANT_P (x) |
4d4cbc0e AH |
3421 | && ((TARGET_HARD_FLOAT && TARGET_FPRS) |
3422 | || (mode != DFmode || TARGET_E500_DOUBLE)) | |
f676971a | 3423 | && mode != DImode |
ee890fe2 SS |
3424 | && mode != TImode) |
3425 | { | |
3426 | rtx reg = gen_reg_rtx (Pmode); | |
8a1977f3 GK |
3427 | emit_insn (gen_macho_high (reg, x)); |
3428 | return gen_rtx_LO_SUM (Pmode, reg, x); | |
ee890fe2 | 3429 | } |
f676971a | 3430 | else if (TARGET_TOC |
4d588c14 | 3431 | && constant_pool_expr_p (x) |
a9098fd0 | 3432 | && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x), Pmode)) |
9ebbca7d GK |
3433 | { |
3434 | return create_TOC_reference (x); | |
3435 | } | |
3436 | else | |
3437 | return NULL_RTX; | |
3438 | } | |
258bfae2 | 3439 | |
c973d557 JJ |
3440 | /* This is called from dwarf2out.c via ASM_OUTPUT_DWARF_DTPREL. |
3441 | We need to emit DTP-relative relocations. */ | |
3442 | ||
3443 | void | |
3444 | rs6000_output_dwarf_dtprel (FILE *file, int size, rtx x) | |
3445 | { | |
3446 | switch (size) | |
3447 | { | |
3448 | case 4: | |
3449 | fputs ("\t.long\t", file); | |
3450 | break; | |
3451 | case 8: | |
3452 | fputs (DOUBLE_INT_ASM_OP, file); | |
3453 | break; | |
3454 | default: | |
3455 | abort (); | |
3456 | } | |
3457 | output_addr_const (file, x); | |
3458 | fputs ("@dtprel+0x8000", file); | |
3459 | } | |
3460 | ||
c4501e62 JJ |
3461 | /* Construct the SYMBOL_REF for the tls_get_addr function. */ |
3462 | ||
3463 | static GTY(()) rtx rs6000_tls_symbol; | |
3464 | static rtx | |
863d938c | 3465 | rs6000_tls_get_addr (void) |
c4501e62 JJ |
3466 | { |
3467 | if (!rs6000_tls_symbol) | |
3468 | rs6000_tls_symbol = init_one_libfunc ("__tls_get_addr"); | |
3469 | ||
3470 | return rs6000_tls_symbol; | |
3471 | } | |
3472 | ||
3473 | /* Construct the SYMBOL_REF for TLS GOT references. */ | |
3474 | ||
3475 | static GTY(()) rtx rs6000_got_symbol; | |
3476 | static rtx | |
863d938c | 3477 | rs6000_got_sym (void) |
c4501e62 JJ |
3478 | { |
3479 | if (!rs6000_got_symbol) | |
3480 | { | |
3481 | rs6000_got_symbol = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_"); | |
3482 | SYMBOL_REF_FLAGS (rs6000_got_symbol) |= SYMBOL_FLAG_LOCAL; | |
3483 | SYMBOL_REF_FLAGS (rs6000_got_symbol) |= SYMBOL_FLAG_EXTERNAL; | |
f676971a | 3484 | } |
c4501e62 JJ |
3485 | |
3486 | return rs6000_got_symbol; | |
3487 | } | |
3488 | ||
3489 | /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute | |
3490 | this (thread-local) address. */ | |
3491 | ||
3492 | static rtx | |
a2369ed3 | 3493 | rs6000_legitimize_tls_address (rtx addr, enum tls_model model) |
c4501e62 JJ |
3494 | { |
3495 | rtx dest, insn; | |
3496 | ||
3497 | dest = gen_reg_rtx (Pmode); | |
3498 | if (model == TLS_MODEL_LOCAL_EXEC && rs6000_tls_size == 16) | |
3499 | { | |
3500 | rtx tlsreg; | |
3501 | ||
3502 | if (TARGET_64BIT) | |
3503 | { | |
3504 | tlsreg = gen_rtx_REG (Pmode, 13); | |
3505 | insn = gen_tls_tprel_64 (dest, tlsreg, addr); | |
3506 | } | |
3507 | else | |
3508 | { | |
3509 | tlsreg = gen_rtx_REG (Pmode, 2); | |
3510 | insn = gen_tls_tprel_32 (dest, tlsreg, addr); | |
3511 | } | |
3512 | emit_insn (insn); | |
3513 | } | |
3514 | else if (model == TLS_MODEL_LOCAL_EXEC && rs6000_tls_size == 32) | |
3515 | { | |
3516 | rtx tlsreg, tmp; | |
3517 | ||
3518 | tmp = gen_reg_rtx (Pmode); | |
3519 | if (TARGET_64BIT) | |
3520 | { | |
3521 | tlsreg = gen_rtx_REG (Pmode, 13); | |
3522 | insn = gen_tls_tprel_ha_64 (tmp, tlsreg, addr); | |
3523 | } | |
3524 | else | |
3525 | { | |
3526 | tlsreg = gen_rtx_REG (Pmode, 2); | |
3527 | insn = gen_tls_tprel_ha_32 (tmp, tlsreg, addr); | |
3528 | } | |
3529 | emit_insn (insn); | |
3530 | if (TARGET_64BIT) | |
3531 | insn = gen_tls_tprel_lo_64 (dest, tmp, addr); | |
3532 | else | |
3533 | insn = gen_tls_tprel_lo_32 (dest, tmp, addr); | |
3534 | emit_insn (insn); | |
3535 | } | |
3536 | else | |
3537 | { | |
3538 | rtx r3, got, tga, tmp1, tmp2, eqv; | |
3539 | ||
3540 | if (TARGET_64BIT) | |
3541 | got = gen_rtx_REG (Pmode, TOC_REGISTER); | |
3542 | else | |
3543 | { | |
3544 | if (flag_pic == 1) | |
3545 | got = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM); | |
3546 | else | |
3547 | { | |
3548 | rtx gsym = rs6000_got_sym (); | |
3549 | got = gen_reg_rtx (Pmode); | |
3550 | if (flag_pic == 0) | |
3551 | rs6000_emit_move (got, gsym, Pmode); | |
3552 | else | |
3553 | { | |
3554 | char buf[30]; | |
3555 | static int tls_got_labelno = 0; | |
3556 | rtx tempLR, lab, tmp3, mem; | |
3557 | rtx first, last; | |
3558 | ||
3559 | ASM_GENERATE_INTERNAL_LABEL (buf, "LTLS", tls_got_labelno++); | |
3560 | lab = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); | |
3561 | tempLR = gen_reg_rtx (Pmode); | |
3562 | tmp1 = gen_reg_rtx (Pmode); | |
3563 | tmp2 = gen_reg_rtx (Pmode); | |
3564 | tmp3 = gen_reg_rtx (Pmode); | |
542a8afa | 3565 | mem = gen_const_mem (Pmode, tmp1); |
c4501e62 JJ |
3566 | |
3567 | first = emit_insn (gen_load_toc_v4_PIC_1b (tempLR, lab, | |
3568 | gsym)); | |
3569 | emit_move_insn (tmp1, tempLR); | |
3570 | emit_move_insn (tmp2, mem); | |
3571 | emit_insn (gen_addsi3 (tmp3, tmp1, tmp2)); | |
3572 | last = emit_move_insn (got, tmp3); | |
3573 | REG_NOTES (last) = gen_rtx_EXPR_LIST (REG_EQUAL, gsym, | |
3574 | REG_NOTES (last)); | |
3575 | REG_NOTES (first) = gen_rtx_INSN_LIST (REG_LIBCALL, last, | |
3576 | REG_NOTES (first)); | |
3577 | REG_NOTES (last) = gen_rtx_INSN_LIST (REG_RETVAL, first, | |
3578 | REG_NOTES (last)); | |
3579 | } | |
3580 | } | |
3581 | } | |
3582 | ||
3583 | if (model == TLS_MODEL_GLOBAL_DYNAMIC) | |
3584 | { | |
3585 | r3 = gen_rtx_REG (Pmode, 3); | |
3586 | if (TARGET_64BIT) | |
3587 | insn = gen_tls_gd_64 (r3, got, addr); | |
3588 | else | |
3589 | insn = gen_tls_gd_32 (r3, got, addr); | |
3590 | start_sequence (); | |
3591 | emit_insn (insn); | |
3592 | tga = gen_rtx_MEM (Pmode, rs6000_tls_get_addr ()); | |
3593 | insn = gen_call_value (r3, tga, const0_rtx, const0_rtx); | |
3594 | insn = emit_call_insn (insn); | |
3595 | CONST_OR_PURE_CALL_P (insn) = 1; | |
3596 | use_reg (&CALL_INSN_FUNCTION_USAGE (insn), r3); | |
3597 | insn = get_insns (); | |
3598 | end_sequence (); | |
3599 | emit_libcall_block (insn, dest, r3, addr); | |
3600 | } | |
3601 | else if (model == TLS_MODEL_LOCAL_DYNAMIC) | |
3602 | { | |
3603 | r3 = gen_rtx_REG (Pmode, 3); | |
3604 | if (TARGET_64BIT) | |
3605 | insn = gen_tls_ld_64 (r3, got); | |
3606 | else | |
3607 | insn = gen_tls_ld_32 (r3, got); | |
3608 | start_sequence (); | |
3609 | emit_insn (insn); | |
3610 | tga = gen_rtx_MEM (Pmode, rs6000_tls_get_addr ()); | |
3611 | insn = gen_call_value (r3, tga, const0_rtx, const0_rtx); | |
3612 | insn = emit_call_insn (insn); | |
3613 | CONST_OR_PURE_CALL_P (insn) = 1; | |
3614 | use_reg (&CALL_INSN_FUNCTION_USAGE (insn), r3); | |
3615 | insn = get_insns (); | |
3616 | end_sequence (); | |
3617 | tmp1 = gen_reg_rtx (Pmode); | |
3618 | eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), | |
3619 | UNSPEC_TLSLD); | |
3620 | emit_libcall_block (insn, tmp1, r3, eqv); | |
3621 | if (rs6000_tls_size == 16) | |
3622 | { | |
3623 | if (TARGET_64BIT) | |
3624 | insn = gen_tls_dtprel_64 (dest, tmp1, addr); | |
3625 | else | |
3626 | insn = gen_tls_dtprel_32 (dest, tmp1, addr); | |
3627 | } | |
3628 | else if (rs6000_tls_size == 32) | |
3629 | { | |
3630 | tmp2 = gen_reg_rtx (Pmode); | |
3631 | if (TARGET_64BIT) | |
3632 | insn = gen_tls_dtprel_ha_64 (tmp2, tmp1, addr); | |
3633 | else | |
3634 | insn = gen_tls_dtprel_ha_32 (tmp2, tmp1, addr); | |
3635 | emit_insn (insn); | |
3636 | if (TARGET_64BIT) | |
3637 | insn = gen_tls_dtprel_lo_64 (dest, tmp2, addr); | |
3638 | else | |
3639 | insn = gen_tls_dtprel_lo_32 (dest, tmp2, addr); | |
3640 | } | |
3641 | else | |
3642 | { | |
3643 | tmp2 = gen_reg_rtx (Pmode); | |
3644 | if (TARGET_64BIT) | |
3645 | insn = gen_tls_got_dtprel_64 (tmp2, got, addr); | |
3646 | else | |
3647 | insn = gen_tls_got_dtprel_32 (tmp2, got, addr); | |
3648 | emit_insn (insn); | |
3649 | insn = gen_rtx_SET (Pmode, dest, | |
3650 | gen_rtx_PLUS (Pmode, tmp2, tmp1)); | |
3651 | } | |
3652 | emit_insn (insn); | |
3653 | } | |
3654 | else | |
3655 | { | |
3656 | /* IE, or 64 bit offset LE. */ | |
3657 | tmp2 = gen_reg_rtx (Pmode); | |
3658 | if (TARGET_64BIT) | |
3659 | insn = gen_tls_got_tprel_64 (tmp2, got, addr); | |
3660 | else | |
3661 | insn = gen_tls_got_tprel_32 (tmp2, got, addr); | |
3662 | emit_insn (insn); | |
3663 | if (TARGET_64BIT) | |
3664 | insn = gen_tls_tls_64 (dest, tmp2, addr); | |
3665 | else | |
3666 | insn = gen_tls_tls_32 (dest, tmp2, addr); | |
3667 | emit_insn (insn); | |
3668 | } | |
3669 | } | |
3670 | ||
3671 | return dest; | |
3672 | } | |
3673 | ||
3674 | /* Return 1 if X is a SYMBOL_REF for a TLS symbol. This is used in | |
3675 | instruction definitions. */ | |
3676 | ||
3677 | int | |
a2369ed3 | 3678 | rs6000_tls_symbol_ref (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED) |
c4501e62 JJ |
3679 | { |
3680 | return RS6000_SYMBOL_REF_TLS_P (x); | |
3681 | } | |
3682 | ||
3683 | /* Return 1 if X contains a thread-local symbol. */ | |
3684 | ||
3685 | bool | |
a2369ed3 | 3686 | rs6000_tls_referenced_p (rtx x) |
c4501e62 | 3687 | { |
cd413cab AP |
3688 | if (! TARGET_HAVE_TLS) |
3689 | return false; | |
3690 | ||
c4501e62 JJ |
3691 | return for_each_rtx (&x, &rs6000_tls_symbol_ref_1, 0); |
3692 | } | |
3693 | ||
3694 | /* Return 1 if *X is a thread-local symbol. This is the same as | |
3695 | rs6000_tls_symbol_ref except for the type of the unused argument. */ | |
3696 | ||
3697 | static inline int | |
a2369ed3 | 3698 | rs6000_tls_symbol_ref_1 (rtx *x, void *data ATTRIBUTE_UNUSED) |
c4501e62 JJ |
3699 | { |
3700 | return RS6000_SYMBOL_REF_TLS_P (*x); | |
3701 | } | |
3702 | ||
24ea750e DJ |
3703 | /* The convention appears to be to define this wherever it is used. |
3704 | With legitimize_reload_address now defined here, REG_MODE_OK_FOR_BASE_P | |
3705 | is now used here. */ | |
3706 | #ifndef REG_MODE_OK_FOR_BASE_P | |
3707 | #define REG_MODE_OK_FOR_BASE_P(REGNO, MODE) REG_OK_FOR_BASE_P (REGNO) | |
3708 | #endif | |
3709 | ||
3710 | /* Our implementation of LEGITIMIZE_RELOAD_ADDRESS. Returns a value to | |
3711 | replace the input X, or the original X if no replacement is called for. | |
3712 | The output parameter *WIN is 1 if the calling macro should goto WIN, | |
3713 | 0 if it should not. | |
3714 | ||
3715 | For RS/6000, we wish to handle large displacements off a base | |
3716 | register by splitting the addend across an addiu/addis and the mem insn. | |
3717 | This cuts number of extra insns needed from 3 to 1. | |
3718 | ||
3719 | On Darwin, we use this to generate code for floating point constants. | |
3720 | A movsf_low is generated so we wind up with 2 instructions rather than 3. | |
3721 | The Darwin code is inside #if TARGET_MACHO because only then is | |
3722 | machopic_function_base_name() defined. */ | |
3723 | rtx | |
f676971a | 3724 | rs6000_legitimize_reload_address (rtx x, enum machine_mode mode, |
c4ad648e AM |
3725 | int opnum, int type, |
3726 | int ind_levels ATTRIBUTE_UNUSED, int *win) | |
24ea750e | 3727 | { |
f676971a | 3728 | /* We must recognize output that we have already generated ourselves. */ |
24ea750e DJ |
3729 | if (GET_CODE (x) == PLUS |
3730 | && GET_CODE (XEXP (x, 0)) == PLUS | |
3731 | && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG | |
3732 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT | |
3733 | && GET_CODE (XEXP (x, 1)) == CONST_INT) | |
3734 | { | |
3735 | push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL, | |
c4ad648e AM |
3736 | BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0, |
3737 | opnum, (enum reload_type)type); | |
24ea750e DJ |
3738 | *win = 1; |
3739 | return x; | |
3740 | } | |
3deb2758 | 3741 | |
24ea750e DJ |
3742 | #if TARGET_MACHO |
3743 | if (DEFAULT_ABI == ABI_DARWIN && flag_pic | |
3744 | && GET_CODE (x) == LO_SUM | |
3745 | && GET_CODE (XEXP (x, 0)) == PLUS | |
3746 | && XEXP (XEXP (x, 0), 0) == pic_offset_table_rtx | |
3747 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == HIGH | |
3748 | && GET_CODE (XEXP (XEXP (XEXP (x, 0), 1), 0)) == CONST | |
3749 | && XEXP (XEXP (XEXP (x, 0), 1), 0) == XEXP (x, 1) | |
3750 | && GET_CODE (XEXP (XEXP (x, 1), 0)) == MINUS | |
3751 | && GET_CODE (XEXP (XEXP (XEXP (x, 1), 0), 0)) == SYMBOL_REF | |
3752 | && GET_CODE (XEXP (XEXP (XEXP (x, 1), 0), 1)) == SYMBOL_REF) | |
3753 | { | |
3754 | /* Result of previous invocation of this function on Darwin | |
6f317ef3 | 3755 | floating point constant. */ |
24ea750e | 3756 | push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL, |
c4ad648e AM |
3757 | BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, |
3758 | opnum, (enum reload_type)type); | |
24ea750e DJ |
3759 | *win = 1; |
3760 | return x; | |
3761 | } | |
3762 | #endif | |
3763 | if (GET_CODE (x) == PLUS | |
3764 | && GET_CODE (XEXP (x, 0)) == REG | |
3765 | && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER | |
3766 | && REG_MODE_OK_FOR_BASE_P (XEXP (x, 0), mode) | |
78c875e8 | 3767 | && GET_CODE (XEXP (x, 1)) == CONST_INT |
93638d7a | 3768 | && !SPE_VECTOR_MODE (mode) |
4d4cbc0e | 3769 | && !(TARGET_E500_DOUBLE && mode == DFmode) |
78c875e8 | 3770 | && !ALTIVEC_VECTOR_MODE (mode)) |
24ea750e DJ |
3771 | { |
3772 | HOST_WIDE_INT val = INTVAL (XEXP (x, 1)); | |
3773 | HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000; | |
3774 | HOST_WIDE_INT high | |
c4ad648e | 3775 | = (((val - low) & 0xffffffff) ^ 0x80000000) - 0x80000000; |
24ea750e DJ |
3776 | |
3777 | /* Check for 32-bit overflow. */ | |
3778 | if (high + low != val) | |
c4ad648e | 3779 | { |
24ea750e DJ |
3780 | *win = 0; |
3781 | return x; | |
3782 | } | |
3783 | ||
3784 | /* Reload the high part into a base reg; leave the low part | |
c4ad648e | 3785 | in the mem directly. */ |
24ea750e DJ |
3786 | |
3787 | x = gen_rtx_PLUS (GET_MODE (x), | |
c4ad648e AM |
3788 | gen_rtx_PLUS (GET_MODE (x), XEXP (x, 0), |
3789 | GEN_INT (high)), | |
3790 | GEN_INT (low)); | |
24ea750e DJ |
3791 | |
3792 | push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL, | |
c4ad648e AM |
3793 | BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0, |
3794 | opnum, (enum reload_type)type); | |
24ea750e DJ |
3795 | *win = 1; |
3796 | return x; | |
3797 | } | |
3798 | #if TARGET_MACHO | |
3799 | if (GET_CODE (x) == SYMBOL_REF | |
3800 | && DEFAULT_ABI == ABI_DARWIN | |
69ef87e2 | 3801 | && !ALTIVEC_VECTOR_MODE (mode) |
a29077da GK |
3802 | && (flag_pic || MACHO_DYNAMIC_NO_PIC_P) |
3803 | /* Don't do this for TFmode, since the result isn't offsettable. */ | |
3804 | && mode != TFmode) | |
24ea750e | 3805 | { |
a29077da GK |
3806 | if (flag_pic) |
3807 | { | |
3808 | rtx offset = gen_rtx_CONST (Pmode, | |
3809 | gen_rtx_MINUS (Pmode, x, | |
11abc112 | 3810 | machopic_function_base_sym ())); |
a29077da GK |
3811 | x = gen_rtx_LO_SUM (GET_MODE (x), |
3812 | gen_rtx_PLUS (Pmode, pic_offset_table_rtx, | |
3813 | gen_rtx_HIGH (Pmode, offset)), offset); | |
3814 | } | |
3815 | else | |
3816 | x = gen_rtx_LO_SUM (GET_MODE (x), | |
c4ad648e | 3817 | gen_rtx_HIGH (Pmode, x), x); |
a29077da | 3818 | |
24ea750e | 3819 | push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL, |
a29077da GK |
3820 | BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, |
3821 | opnum, (enum reload_type)type); | |
24ea750e DJ |
3822 | *win = 1; |
3823 | return x; | |
3824 | } | |
3825 | #endif | |
3826 | if (TARGET_TOC | |
4d588c14 | 3827 | && constant_pool_expr_p (x) |
c1f11548 | 3828 | && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x), mode)) |
24ea750e DJ |
3829 | { |
3830 | (x) = create_TOC_reference (x); | |
3831 | *win = 1; | |
3832 | return x; | |
3833 | } | |
3834 | *win = 0; | |
3835 | return x; | |
f676971a | 3836 | } |
24ea750e | 3837 | |
258bfae2 FS |
3838 | /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression |
3839 | that is a valid memory address for an instruction. | |
3840 | The MODE argument is the machine mode for the MEM expression | |
3841 | that wants to use this address. | |
3842 | ||
3843 | On the RS/6000, there are four valid address: a SYMBOL_REF that | |
3844 | refers to a constant pool entry of an address (or the sum of it | |
3845 | plus a constant), a short (16-bit signed) constant plus a register, | |
3846 | the sum of two registers, or a register indirect, possibly with an | |
5bdc5878 | 3847 | auto-increment. For DFmode and DImode with a constant plus register, |
258bfae2 FS |
3848 | we must ensure that both words are addressable or PowerPC64 with offset |
3849 | word aligned. | |
3850 | ||
3851 | For modes spanning multiple registers (DFmode in 32-bit GPRs, | |
76d2b81d | 3852 | 32-bit DImode, TImode, TFmode), indexed addressing cannot be used because |
258bfae2 FS |
3853 | adjacent memory cells are accessed by adding word-sized offsets |
3854 | during assembly output. */ | |
3855 | int | |
a2369ed3 | 3856 | rs6000_legitimate_address (enum machine_mode mode, rtx x, int reg_ok_strict) |
258bfae2 | 3857 | { |
850e8d3d DN |
3858 | /* If this is an unaligned stvx/ldvx type address, discard the outer AND. */ |
3859 | if (TARGET_ALTIVEC | |
3860 | && ALTIVEC_VECTOR_MODE (mode) | |
3861 | && GET_CODE (x) == AND | |
3862 | && GET_CODE (XEXP (x, 1)) == CONST_INT | |
3863 | && INTVAL (XEXP (x, 1)) == -16) | |
3864 | x = XEXP (x, 0); | |
3865 | ||
c4501e62 JJ |
3866 | if (RS6000_SYMBOL_REF_TLS_P (x)) |
3867 | return 0; | |
4d588c14 | 3868 | if (legitimate_indirect_address_p (x, reg_ok_strict)) |
258bfae2 FS |
3869 | return 1; |
3870 | if ((GET_CODE (x) == PRE_INC || GET_CODE (x) == PRE_DEC) | |
0d6d6892 | 3871 | && !ALTIVEC_VECTOR_MODE (mode) |
a3170dc6 | 3872 | && !SPE_VECTOR_MODE (mode) |
4d4cbc0e | 3873 | && !(TARGET_E500_DOUBLE && mode == DFmode) |
258bfae2 | 3874 | && TARGET_UPDATE |
4d588c14 | 3875 | && legitimate_indirect_address_p (XEXP (x, 0), reg_ok_strict)) |
258bfae2 | 3876 | return 1; |
4d588c14 | 3877 | if (legitimate_small_data_p (mode, x)) |
258bfae2 | 3878 | return 1; |
4d588c14 | 3879 | if (legitimate_constant_pool_address_p (x)) |
258bfae2 FS |
3880 | return 1; |
3881 | /* If not REG_OK_STRICT (before reload) let pass any stack offset. */ | |
3882 | if (! reg_ok_strict | |
3883 | && GET_CODE (x) == PLUS | |
3884 | && GET_CODE (XEXP (x, 0)) == REG | |
708d2456 | 3885 | && (XEXP (x, 0) == virtual_stack_vars_rtx |
c4ad648e | 3886 | || XEXP (x, 0) == arg_pointer_rtx) |
258bfae2 FS |
3887 | && GET_CODE (XEXP (x, 1)) == CONST_INT) |
3888 | return 1; | |
76d2b81d | 3889 | if (rs6000_legitimate_offset_address_p (mode, x, reg_ok_strict)) |
258bfae2 FS |
3890 | return 1; |
3891 | if (mode != TImode | |
76d2b81d | 3892 | && mode != TFmode |
a3170dc6 AH |
3893 | && ((TARGET_HARD_FLOAT && TARGET_FPRS) |
3894 | || TARGET_POWERPC64 | |
4d4cbc0e | 3895 | || ((mode != DFmode || TARGET_E500_DOUBLE) && mode != TFmode)) |
258bfae2 | 3896 | && (TARGET_POWERPC64 || mode != DImode) |
4d588c14 | 3897 | && legitimate_indexed_address_p (x, reg_ok_strict)) |
258bfae2 | 3898 | return 1; |
4d588c14 | 3899 | if (legitimate_lo_sum_address_p (mode, x, reg_ok_strict)) |
258bfae2 FS |
3900 | return 1; |
3901 | return 0; | |
3902 | } | |
4d588c14 RH |
3903 | |
3904 | /* Go to LABEL if ADDR (a legitimate address expression) | |
3905 | has an effect that depends on the machine mode it is used for. | |
3906 | ||
3907 | On the RS/6000 this is true of all integral offsets (since AltiVec | |
3908 | modes don't allow them) or is a pre-increment or decrement. | |
3909 | ||
3910 | ??? Except that due to conceptual problems in offsettable_address_p | |
3911 | we can't really report the problems of integral offsets. So leave | |
f676971a | 3912 | this assuming that the adjustable offset must be valid for the |
4d588c14 RH |
3913 | sub-words of a TFmode operand, which is what we had before. */ |
3914 | ||
3915 | bool | |
a2369ed3 | 3916 | rs6000_mode_dependent_address (rtx addr) |
4d588c14 RH |
3917 | { |
3918 | switch (GET_CODE (addr)) | |
3919 | { | |
3920 | case PLUS: | |
3921 | if (GET_CODE (XEXP (addr, 1)) == CONST_INT) | |
3922 | { | |
3923 | unsigned HOST_WIDE_INT val = INTVAL (XEXP (addr, 1)); | |
3924 | return val + 12 + 0x8000 >= 0x10000; | |
3925 | } | |
3926 | break; | |
3927 | ||
3928 | case LO_SUM: | |
3929 | return true; | |
3930 | ||
3931 | case PRE_INC: | |
3932 | case PRE_DEC: | |
3933 | return TARGET_UPDATE; | |
3934 | ||
3935 | default: | |
3936 | break; | |
3937 | } | |
3938 | ||
3939 | return false; | |
3940 | } | |
d8ecbcdb AH |
3941 | |
3942 | /* Return number of consecutive hard regs needed starting at reg REGNO | |
3943 | to hold something of mode MODE. | |
3944 | This is ordinarily the length in words of a value of mode MODE | |
3945 | but can be less for certain modes in special long registers. | |
3946 | ||
3947 | For the SPE, GPRs are 64 bits but only 32 bits are visible in | |
3948 | scalar instructions. The upper 32 bits are only available to the | |
3949 | SIMD instructions. | |
3950 | ||
3951 | POWER and PowerPC GPRs hold 32 bits worth; | |
3952 | PowerPC64 GPRs and FPRs point register holds 64 bits worth. */ | |
3953 | ||
3954 | int | |
3955 | rs6000_hard_regno_nregs (int regno, enum machine_mode mode) | |
3956 | { | |
3957 | if (FP_REGNO_P (regno)) | |
3958 | return (GET_MODE_SIZE (mode) + UNITS_PER_FP_WORD - 1) / UNITS_PER_FP_WORD; | |
3959 | ||
4d4cbc0e AH |
3960 | if (TARGET_E500_DOUBLE && mode == DFmode) |
3961 | return 1; | |
3962 | ||
d8ecbcdb AH |
3963 | if (SPE_SIMD_REGNO_P (regno) && TARGET_SPE && SPE_VECTOR_MODE (mode)) |
3964 | return (GET_MODE_SIZE (mode) + UNITS_PER_SPE_WORD - 1) / UNITS_PER_SPE_WORD; | |
3965 | ||
3966 | if (ALTIVEC_REGNO_P (regno)) | |
3967 | return | |
3968 | (GET_MODE_SIZE (mode) + UNITS_PER_ALTIVEC_WORD - 1) / UNITS_PER_ALTIVEC_WORD; | |
3969 | ||
3970 | return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD; | |
3971 | } | |
2aa4498c AH |
3972 | |
3973 | /* Change register usage conditional on target flags. */ | |
3974 | void | |
3975 | rs6000_conditional_register_usage (void) | |
3976 | { | |
3977 | int i; | |
3978 | ||
3979 | /* Set MQ register fixed (already call_used) if not POWER | |
3980 | architecture (RIOS1, RIOS2, RSC, and PPC601) so that it will not | |
3981 | be allocated. */ | |
3982 | if (! TARGET_POWER) | |
3983 | fixed_regs[64] = 1; | |
3984 | ||
3985 | /* 64-bit AIX reserves GPR13 for thread-private data. */ | |
3986 | if (TARGET_64BIT) | |
3987 | fixed_regs[13] = call_used_regs[13] | |
3988 | = call_really_used_regs[13] = 1; | |
3989 | ||
3990 | /* Conditionally disable FPRs. */ | |
3991 | if (TARGET_SOFT_FLOAT || !TARGET_FPRS) | |
3992 | for (i = 32; i < 64; i++) | |
3993 | fixed_regs[i] = call_used_regs[i] | |
c4ad648e | 3994 | = call_really_used_regs[i] = 1; |
2aa4498c AH |
3995 | |
3996 | if (DEFAULT_ABI == ABI_V4 | |
3997 | && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM | |
3998 | && flag_pic == 2) | |
3999 | fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1; | |
4000 | ||
4001 | if (DEFAULT_ABI == ABI_V4 | |
4002 | && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM | |
4003 | && flag_pic == 1) | |
4004 | fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] | |
4005 | = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] | |
4006 | = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1; | |
4007 | ||
4008 | if (DEFAULT_ABI == ABI_DARWIN | |
4009 | && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) | |
4010 | global_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] | |
4011 | = fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] | |
4012 | = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] | |
4013 | = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1; | |
4014 | ||
b4db40bf JJ |
4015 | if (TARGET_TOC && TARGET_MINIMAL_TOC) |
4016 | fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] | |
4017 | = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1; | |
4018 | ||
2aa4498c AH |
4019 | if (TARGET_ALTIVEC) |
4020 | global_regs[VSCR_REGNO] = 1; | |
4021 | ||
4022 | if (TARGET_SPE) | |
4023 | { | |
4024 | global_regs[SPEFSCR_REGNO] = 1; | |
4025 | fixed_regs[FIXED_SCRATCH] | |
c4ad648e | 4026 | = call_used_regs[FIXED_SCRATCH] |
2aa4498c AH |
4027 | = call_really_used_regs[FIXED_SCRATCH] = 1; |
4028 | } | |
4029 | ||
4030 | if (! TARGET_ALTIVEC) | |
4031 | { | |
4032 | for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i) | |
4033 | fixed_regs[i] = call_used_regs[i] = call_really_used_regs[i] = 1; | |
4034 | call_really_used_regs[VRSAVE_REGNO] = 1; | |
4035 | } | |
4036 | ||
4037 | if (TARGET_ALTIVEC_ABI) | |
4038 | for (i = FIRST_ALTIVEC_REGNO; i < FIRST_ALTIVEC_REGNO + 20; ++i) | |
4039 | call_used_regs[i] = call_really_used_regs[i] = 1; | |
4040 | } | |
fb4d4348 | 4041 | \f |
a4f6c312 SS |
4042 | /* Try to output insns to set TARGET equal to the constant C if it can |
4043 | be done in less than N insns. Do all computations in MODE. | |
4044 | Returns the place where the output has been placed if it can be | |
4045 | done and the insns have been emitted. If it would take more than N | |
4046 | insns, zero is returned and no insns and emitted. */ | |
2bfcf297 DB |
4047 | |
4048 | rtx | |
f676971a | 4049 | rs6000_emit_set_const (rtx dest, enum machine_mode mode, |
a2369ed3 | 4050 | rtx source, int n ATTRIBUTE_UNUSED) |
2bfcf297 | 4051 | { |
af8cb5c5 | 4052 | rtx result, insn, set; |
2bfcf297 DB |
4053 | HOST_WIDE_INT c0, c1; |
4054 | ||
af8cb5c5 | 4055 | if (mode == QImode || mode == HImode) |
2bfcf297 DB |
4056 | { |
4057 | if (dest == NULL) | |
c4ad648e | 4058 | dest = gen_reg_rtx (mode); |
2bfcf297 DB |
4059 | emit_insn (gen_rtx_SET (VOIDmode, dest, source)); |
4060 | return dest; | |
4061 | } | |
af8cb5c5 | 4062 | else if (mode == SImode) |
2bfcf297 | 4063 | { |
af8cb5c5 DE |
4064 | result = no_new_pseudos ? dest : gen_reg_rtx (SImode); |
4065 | ||
4066 | emit_insn (gen_rtx_SET (VOIDmode, result, | |
4067 | GEN_INT (INTVAL (source) | |
4068 | & (~ (HOST_WIDE_INT) 0xffff)))); | |
4069 | emit_insn (gen_rtx_SET (VOIDmode, dest, | |
4070 | gen_rtx_IOR (SImode, result, | |
4071 | GEN_INT (INTVAL (source) & 0xffff)))); | |
4072 | result = dest; | |
2bfcf297 | 4073 | } |
af8cb5c5 | 4074 | else if (mode == DImode) |
2bfcf297 | 4075 | { |
af8cb5c5 DE |
4076 | if (GET_CODE (source) == CONST_INT) |
4077 | { | |
4078 | c0 = INTVAL (source); | |
4079 | c1 = -(c0 < 0); | |
4080 | } | |
4081 | else if (GET_CODE (source) == CONST_DOUBLE) | |
4082 | { | |
2bfcf297 | 4083 | #if HOST_BITS_PER_WIDE_INT >= 64 |
af8cb5c5 DE |
4084 | c0 = CONST_DOUBLE_LOW (source); |
4085 | c1 = -(c0 < 0); | |
2bfcf297 | 4086 | #else |
af8cb5c5 DE |
4087 | c0 = CONST_DOUBLE_LOW (source); |
4088 | c1 = CONST_DOUBLE_HIGH (source); | |
2bfcf297 | 4089 | #endif |
af8cb5c5 DE |
4090 | } |
4091 | else | |
4092 | abort (); | |
4093 | ||
4094 | result = rs6000_emit_set_long_const (dest, c0, c1); | |
2bfcf297 DB |
4095 | } |
4096 | else | |
a4f6c312 | 4097 | abort (); |
2bfcf297 | 4098 | |
af8cb5c5 DE |
4099 | insn = get_last_insn (); |
4100 | set = single_set (insn); | |
4101 | if (! CONSTANT_P (SET_SRC (set))) | |
4102 | set_unique_reg_note (insn, REG_EQUAL, source); | |
4103 | ||
4104 | return result; | |
2bfcf297 DB |
4105 | } |
4106 | ||
4107 | /* Having failed to find a 3 insn sequence in rs6000_emit_set_const, | |
4108 | fall back to a straight forward decomposition. We do this to avoid | |
4109 | exponential run times encountered when looking for longer sequences | |
4110 | with rs6000_emit_set_const. */ | |
4111 | static rtx | |
a2369ed3 | 4112 | rs6000_emit_set_long_const (rtx dest, HOST_WIDE_INT c1, HOST_WIDE_INT c2) |
2bfcf297 DB |
4113 | { |
4114 | if (!TARGET_POWERPC64) | |
4115 | { | |
4116 | rtx operand1, operand2; | |
4117 | ||
4118 | operand1 = operand_subword_force (dest, WORDS_BIG_ENDIAN == 0, | |
4119 | DImode); | |
4120 | operand2 = operand_subword_force (dest, WORDS_BIG_ENDIAN != 0, | |
4121 | DImode); | |
4122 | emit_move_insn (operand1, GEN_INT (c1)); | |
4123 | emit_move_insn (operand2, GEN_INT (c2)); | |
4124 | } | |
4125 | else | |
4126 | { | |
bc06712d | 4127 | HOST_WIDE_INT ud1, ud2, ud3, ud4; |
252b88f7 | 4128 | |
bc06712d | 4129 | ud1 = c1 & 0xffff; |
f921c9c9 | 4130 | ud2 = (c1 & 0xffff0000) >> 16; |
2bfcf297 | 4131 | #if HOST_BITS_PER_WIDE_INT >= 64 |
bc06712d | 4132 | c2 = c1 >> 32; |
2bfcf297 | 4133 | #endif |
bc06712d | 4134 | ud3 = c2 & 0xffff; |
f921c9c9 | 4135 | ud4 = (c2 & 0xffff0000) >> 16; |
2bfcf297 | 4136 | |
f676971a | 4137 | if ((ud4 == 0xffff && ud3 == 0xffff && ud2 == 0xffff && (ud1 & 0x8000)) |
bc06712d | 4138 | || (ud4 == 0 && ud3 == 0 && ud2 == 0 && ! (ud1 & 0x8000))) |
2bfcf297 | 4139 | { |
bc06712d | 4140 | if (ud1 & 0x8000) |
b78d48dd | 4141 | emit_move_insn (dest, GEN_INT (((ud1 ^ 0x8000) - 0x8000))); |
bc06712d TR |
4142 | else |
4143 | emit_move_insn (dest, GEN_INT (ud1)); | |
2bfcf297 | 4144 | } |
2bfcf297 | 4145 | |
f676971a | 4146 | else if ((ud4 == 0xffff && ud3 == 0xffff && (ud2 & 0x8000)) |
bc06712d | 4147 | || (ud4 == 0 && ud3 == 0 && ! (ud2 & 0x8000))) |
252b88f7 | 4148 | { |
bc06712d | 4149 | if (ud2 & 0x8000) |
f676971a | 4150 | emit_move_insn (dest, GEN_INT (((ud2 << 16) ^ 0x80000000) |
bc06712d | 4151 | - 0x80000000)); |
252b88f7 | 4152 | else |
bc06712d TR |
4153 | emit_move_insn (dest, GEN_INT (ud2 << 16)); |
4154 | if (ud1 != 0) | |
4155 | emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud1))); | |
252b88f7 | 4156 | } |
f676971a | 4157 | else if ((ud4 == 0xffff && (ud3 & 0x8000)) |
bc06712d TR |
4158 | || (ud4 == 0 && ! (ud3 & 0x8000))) |
4159 | { | |
4160 | if (ud3 & 0x8000) | |
f676971a | 4161 | emit_move_insn (dest, GEN_INT (((ud3 << 16) ^ 0x80000000) |
bc06712d TR |
4162 | - 0x80000000)); |
4163 | else | |
4164 | emit_move_insn (dest, GEN_INT (ud3 << 16)); | |
4165 | ||
4166 | if (ud2 != 0) | |
4167 | emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud2))); | |
4168 | emit_move_insn (dest, gen_rtx_ASHIFT (DImode, dest, GEN_INT (16))); | |
4169 | if (ud1 != 0) | |
4170 | emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud1))); | |
4171 | } | |
f676971a | 4172 | else |
bc06712d TR |
4173 | { |
4174 | if (ud4 & 0x8000) | |
f676971a | 4175 | emit_move_insn (dest, GEN_INT (((ud4 << 16) ^ 0x80000000) |
bc06712d TR |
4176 | - 0x80000000)); |
4177 | else | |
4178 | emit_move_insn (dest, GEN_INT (ud4 << 16)); | |
4179 | ||
4180 | if (ud3 != 0) | |
4181 | emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud3))); | |
2bfcf297 | 4182 | |
bc06712d TR |
4183 | emit_move_insn (dest, gen_rtx_ASHIFT (DImode, dest, GEN_INT (32))); |
4184 | if (ud2 != 0) | |
f676971a EC |
4185 | emit_move_insn (dest, gen_rtx_IOR (DImode, dest, |
4186 | GEN_INT (ud2 << 16))); | |
bc06712d TR |
4187 | if (ud1 != 0) |
4188 | emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud1))); | |
4189 | } | |
4190 | } | |
2bfcf297 DB |
4191 | return dest; |
4192 | } | |
4193 | ||
76d2b81d DJ |
4194 | /* Helper for the following. Get rid of [r+r] memory refs |
4195 | in cases where it won't work (TImode, TFmode). */ | |
4196 | ||
4197 | static void | |
4198 | rs6000_eliminate_indexed_memrefs (rtx operands[2]) | |
4199 | { | |
4200 | if (GET_CODE (operands[0]) == MEM | |
4201 | && GET_CODE (XEXP (operands[0], 0)) != REG | |
4202 | && ! reload_in_progress) | |
4203 | operands[0] | |
4204 | = replace_equiv_address (operands[0], | |
4205 | copy_addr_to_reg (XEXP (operands[0], 0))); | |
4206 | ||
4207 | if (GET_CODE (operands[1]) == MEM | |
4208 | && GET_CODE (XEXP (operands[1], 0)) != REG | |
4209 | && ! reload_in_progress) | |
4210 | operands[1] | |
4211 | = replace_equiv_address (operands[1], | |
4212 | copy_addr_to_reg (XEXP (operands[1], 0))); | |
4213 | } | |
4214 | ||
fb4d4348 GK |
4215 | /* Emit a move from SOURCE to DEST in mode MODE. */ |
4216 | void | |
a2369ed3 | 4217 | rs6000_emit_move (rtx dest, rtx source, enum machine_mode mode) |
fb4d4348 GK |
4218 | { |
4219 | rtx operands[2]; | |
4220 | operands[0] = dest; | |
4221 | operands[1] = source; | |
f676971a | 4222 | |
fb4d4348 GK |
4223 | /* Sanity checks. Check that we get CONST_DOUBLE only when we should. */ |
4224 | if (GET_CODE (operands[1]) == CONST_DOUBLE | |
4225 | && ! FLOAT_MODE_P (mode) | |
4226 | && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT) | |
4227 | { | |
4228 | /* FIXME. This should never happen. */ | |
4229 | /* Since it seems that it does, do the safe thing and convert | |
4230 | to a CONST_INT. */ | |
2496c7bd | 4231 | operands[1] = gen_int_mode (CONST_DOUBLE_LOW (operands[1]), mode); |
fb4d4348 GK |
4232 | } |
4233 | if (GET_CODE (operands[1]) == CONST_DOUBLE | |
4234 | && ! FLOAT_MODE_P (mode) | |
4235 | && ((CONST_DOUBLE_HIGH (operands[1]) == 0 | |
4236 | && CONST_DOUBLE_LOW (operands[1]) >= 0) | |
4237 | || (CONST_DOUBLE_HIGH (operands[1]) == -1 | |
4238 | && CONST_DOUBLE_LOW (operands[1]) < 0))) | |
4239 | abort (); | |
c9e8cb32 DD |
4240 | |
4241 | /* Check if GCC is setting up a block move that will end up using FP | |
4242 | registers as temporaries. We must make sure this is acceptable. */ | |
4243 | if (GET_CODE (operands[0]) == MEM | |
4244 | && GET_CODE (operands[1]) == MEM | |
4245 | && mode == DImode | |
41543739 GK |
4246 | && (SLOW_UNALIGNED_ACCESS (DImode, MEM_ALIGN (operands[0])) |
4247 | || SLOW_UNALIGNED_ACCESS (DImode, MEM_ALIGN (operands[1]))) | |
4248 | && ! (SLOW_UNALIGNED_ACCESS (SImode, (MEM_ALIGN (operands[0]) > 32 | |
4249 | ? 32 : MEM_ALIGN (operands[0]))) | |
4250 | || SLOW_UNALIGNED_ACCESS (SImode, (MEM_ALIGN (operands[1]) > 32 | |
f676971a | 4251 | ? 32 |
41543739 GK |
4252 | : MEM_ALIGN (operands[1])))) |
4253 | && ! MEM_VOLATILE_P (operands [0]) | |
4254 | && ! MEM_VOLATILE_P (operands [1])) | |
c9e8cb32 | 4255 | { |
41543739 GK |
4256 | emit_move_insn (adjust_address (operands[0], SImode, 0), |
4257 | adjust_address (operands[1], SImode, 0)); | |
4258 | emit_move_insn (adjust_address (operands[0], SImode, 4), | |
4259 | adjust_address (operands[1], SImode, 4)); | |
c9e8cb32 DD |
4260 | return; |
4261 | } | |
630d42a0 | 4262 | |
67cef334 DE |
4263 | if (!no_new_pseudos) |
4264 | { | |
4265 | if (GET_CODE (operands[1]) == MEM && optimize > 0 | |
4266 | && (mode == QImode || mode == HImode || mode == SImode) | |
4267 | && GET_MODE_SIZE (mode) < GET_MODE_SIZE (word_mode)) | |
4268 | { | |
4269 | rtx reg = gen_reg_rtx (word_mode); | |
4270 | ||
4271 | emit_insn (gen_rtx_SET (word_mode, reg, | |
4272 | gen_rtx_ZERO_EXTEND (word_mode, | |
4273 | operands[1]))); | |
4274 | operands[1] = gen_lowpart (mode, reg); | |
4275 | } | |
4276 | if (GET_CODE (operands[0]) != REG) | |
4277 | operands[1] = force_reg (mode, operands[1]); | |
4278 | } | |
a9098fd0 | 4279 | |
a3170dc6 AH |
4280 | if (mode == SFmode && ! TARGET_POWERPC |
4281 | && TARGET_HARD_FLOAT && TARGET_FPRS | |
ffc14f31 | 4282 | && GET_CODE (operands[0]) == MEM) |
fb4d4348 | 4283 | { |
ffc14f31 GK |
4284 | int regnum; |
4285 | ||
4286 | if (reload_in_progress || reload_completed) | |
4287 | regnum = true_regnum (operands[1]); | |
4288 | else if (GET_CODE (operands[1]) == REG) | |
4289 | regnum = REGNO (operands[1]); | |
4290 | else | |
4291 | regnum = -1; | |
f676971a | 4292 | |
fb4d4348 GK |
4293 | /* If operands[1] is a register, on POWER it may have |
4294 | double-precision data in it, so truncate it to single | |
4295 | precision. */ | |
4296 | if (FP_REGNO_P (regnum) || regnum >= FIRST_PSEUDO_REGISTER) | |
4297 | { | |
4298 | rtx newreg; | |
4299 | newreg = (no_new_pseudos ? operands[1] : gen_reg_rtx (mode)); | |
4300 | emit_insn (gen_aux_truncdfsf2 (newreg, operands[1])); | |
4301 | operands[1] = newreg; | |
4302 | } | |
4303 | } | |
4304 | ||
c4501e62 JJ |
4305 | /* Recognize the case where operand[1] is a reference to thread-local |
4306 | data and load its address to a register. */ | |
4307 | if (GET_CODE (operands[1]) == SYMBOL_REF) | |
4308 | { | |
4309 | enum tls_model model = SYMBOL_REF_TLS_MODEL (operands[1]); | |
4310 | if (model != 0) | |
4311 | operands[1] = rs6000_legitimize_tls_address (operands[1], model); | |
4312 | } | |
4313 | ||
8f4e6caf RH |
4314 | /* Handle the case where reload calls us with an invalid address. */ |
4315 | if (reload_in_progress && mode == Pmode | |
69ef87e2 | 4316 | && (! general_operand (operands[1], mode) |
8f4e6caf RH |
4317 | || ! nonimmediate_operand (operands[0], mode))) |
4318 | goto emit_set; | |
4319 | ||
a9baceb1 GK |
4320 | /* 128-bit constant floating-point values on Darwin should really be |
4321 | loaded as two parts. */ | |
4322 | if ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) | |
4323 | && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128 | |
4324 | && mode == TFmode && GET_CODE (operands[1]) == CONST_DOUBLE) | |
4325 | { | |
4326 | /* DImode is used, not DFmode, because simplify_gen_subreg doesn't | |
4327 | know how to get a DFmode SUBREG of a TFmode. */ | |
4328 | rs6000_emit_move (simplify_gen_subreg (DImode, operands[0], mode, 0), | |
4329 | simplify_gen_subreg (DImode, operands[1], mode, 0), | |
4330 | DImode); | |
4331 | rs6000_emit_move (simplify_gen_subreg (DImode, operands[0], mode, | |
4332 | GET_MODE_SIZE (DImode)), | |
4333 | simplify_gen_subreg (DImode, operands[1], mode, | |
4334 | GET_MODE_SIZE (DImode)), | |
4335 | DImode); | |
4336 | return; | |
4337 | } | |
4338 | ||
fb4d4348 GK |
4339 | /* FIXME: In the long term, this switch statement should go away |
4340 | and be replaced by a sequence of tests based on things like | |
4341 | mode == Pmode. */ | |
4342 | switch (mode) | |
4343 | { | |
4344 | case HImode: | |
4345 | case QImode: | |
4346 | if (CONSTANT_P (operands[1]) | |
4347 | && GET_CODE (operands[1]) != CONST_INT) | |
a9098fd0 | 4348 | operands[1] = force_const_mem (mode, operands[1]); |
fb4d4348 GK |
4349 | break; |
4350 | ||
06f4e019 | 4351 | case TFmode: |
76d2b81d DJ |
4352 | rs6000_eliminate_indexed_memrefs (operands); |
4353 | /* fall through */ | |
4354 | ||
fb4d4348 GK |
4355 | case DFmode: |
4356 | case SFmode: | |
f676971a | 4357 | if (CONSTANT_P (operands[1]) |
fb4d4348 | 4358 | && ! easy_fp_constant (operands[1], mode)) |
a9098fd0 | 4359 | operands[1] = force_const_mem (mode, operands[1]); |
fb4d4348 | 4360 | break; |
f676971a | 4361 | |
0ac081f6 AH |
4362 | case V16QImode: |
4363 | case V8HImode: | |
4364 | case V4SFmode: | |
4365 | case V4SImode: | |
a3170dc6 AH |
4366 | case V4HImode: |
4367 | case V2SFmode: | |
4368 | case V2SImode: | |
00a892b8 | 4369 | case V1DImode: |
69ef87e2 | 4370 | if (CONSTANT_P (operands[1]) |
d744e06e | 4371 | && !easy_vector_constant (operands[1], mode)) |
0ac081f6 AH |
4372 | operands[1] = force_const_mem (mode, operands[1]); |
4373 | break; | |
f676971a | 4374 | |
fb4d4348 | 4375 | case SImode: |
a9098fd0 | 4376 | case DImode: |
fb4d4348 GK |
4377 | /* Use default pattern for address of ELF small data */ |
4378 | if (TARGET_ELF | |
a9098fd0 | 4379 | && mode == Pmode |
f607bc57 | 4380 | && DEFAULT_ABI == ABI_V4 |
f676971a | 4381 | && (GET_CODE (operands[1]) == SYMBOL_REF |
a9098fd0 GK |
4382 | || GET_CODE (operands[1]) == CONST) |
4383 | && small_data_operand (operands[1], mode)) | |
fb4d4348 GK |
4384 | { |
4385 | emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1])); | |
4386 | return; | |
4387 | } | |
4388 | ||
f607bc57 | 4389 | if (DEFAULT_ABI == ABI_V4 |
a9098fd0 GK |
4390 | && mode == Pmode && mode == SImode |
4391 | && flag_pic == 1 && got_operand (operands[1], mode)) | |
fb4d4348 GK |
4392 | { |
4393 | emit_insn (gen_movsi_got (operands[0], operands[1])); | |
4394 | return; | |
4395 | } | |
4396 | ||
ee890fe2 | 4397 | if ((TARGET_ELF || DEFAULT_ABI == ABI_DARWIN) |
f1384257 AM |
4398 | && TARGET_NO_TOC |
4399 | && ! flag_pic | |
a9098fd0 | 4400 | && mode == Pmode |
fb4d4348 GK |
4401 | && CONSTANT_P (operands[1]) |
4402 | && GET_CODE (operands[1]) != HIGH | |
4403 | && GET_CODE (operands[1]) != CONST_INT) | |
4404 | { | |
a9098fd0 | 4405 | rtx target = (no_new_pseudos ? operands[0] : gen_reg_rtx (mode)); |
fb4d4348 GK |
4406 | |
4407 | /* If this is a function address on -mcall-aixdesc, | |
4408 | convert it to the address of the descriptor. */ | |
4409 | if (DEFAULT_ABI == ABI_AIX | |
4410 | && GET_CODE (operands[1]) == SYMBOL_REF | |
4411 | && XSTR (operands[1], 0)[0] == '.') | |
4412 | { | |
4413 | const char *name = XSTR (operands[1], 0); | |
4414 | rtx new_ref; | |
4415 | while (*name == '.') | |
4416 | name++; | |
4417 | new_ref = gen_rtx_SYMBOL_REF (Pmode, name); | |
4418 | CONSTANT_POOL_ADDRESS_P (new_ref) | |
4419 | = CONSTANT_POOL_ADDRESS_P (operands[1]); | |
d1908feb | 4420 | SYMBOL_REF_FLAGS (new_ref) = SYMBOL_REF_FLAGS (operands[1]); |
fb4d4348 | 4421 | SYMBOL_REF_USED (new_ref) = SYMBOL_REF_USED (operands[1]); |
d1908feb | 4422 | SYMBOL_REF_DECL (new_ref) = SYMBOL_REF_DECL (operands[1]); |
fb4d4348 GK |
4423 | operands[1] = new_ref; |
4424 | } | |
7509c759 | 4425 | |
ee890fe2 SS |
4426 | if (DEFAULT_ABI == ABI_DARWIN) |
4427 | { | |
ab82a49f AP |
4428 | #if TARGET_MACHO |
4429 | if (MACHO_DYNAMIC_NO_PIC_P) | |
4430 | { | |
4431 | /* Take care of any required data indirection. */ | |
4432 | operands[1] = rs6000_machopic_legitimize_pic_address ( | |
4433 | operands[1], mode, operands[0]); | |
4434 | if (operands[0] != operands[1]) | |
4435 | emit_insn (gen_rtx_SET (VOIDmode, | |
c4ad648e | 4436 | operands[0], operands[1])); |
ab82a49f AP |
4437 | return; |
4438 | } | |
4439 | #endif | |
ac9e2cff AP |
4440 | if (mode == DImode) |
4441 | { | |
4442 | emit_insn (gen_macho_high_di (target, operands[1])); | |
4443 | emit_insn (gen_macho_low_di (operands[0], target, operands[1])); | |
4444 | } | |
4445 | else | |
4446 | { | |
4447 | emit_insn (gen_macho_high (target, operands[1])); | |
4448 | emit_insn (gen_macho_low (operands[0], target, operands[1])); | |
4449 | } | |
ee890fe2 SS |
4450 | return; |
4451 | } | |
4452 | ||
fb4d4348 GK |
4453 | emit_insn (gen_elf_high (target, operands[1])); |
4454 | emit_insn (gen_elf_low (operands[0], target, operands[1])); | |
4455 | return; | |
4456 | } | |
4457 | ||
a9098fd0 GK |
4458 | /* If this is a SYMBOL_REF that refers to a constant pool entry, |
4459 | and we have put it in the TOC, we just need to make a TOC-relative | |
4460 | reference to it. */ | |
4461 | if (TARGET_TOC | |
4462 | && GET_CODE (operands[1]) == SYMBOL_REF | |
4d588c14 | 4463 | && constant_pool_expr_p (operands[1]) |
a9098fd0 GK |
4464 | && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (operands[1]), |
4465 | get_pool_mode (operands[1]))) | |
fb4d4348 | 4466 | { |
a9098fd0 | 4467 | operands[1] = create_TOC_reference (operands[1]); |
fb4d4348 | 4468 | } |
a9098fd0 GK |
4469 | else if (mode == Pmode |
4470 | && CONSTANT_P (operands[1]) | |
38886f37 AO |
4471 | && ((GET_CODE (operands[1]) != CONST_INT |
4472 | && ! easy_fp_constant (operands[1], mode)) | |
4473 | || (GET_CODE (operands[1]) == CONST_INT | |
4474 | && num_insns_constant (operands[1], mode) > 2) | |
4475 | || (GET_CODE (operands[0]) == REG | |
4476 | && FP_REGNO_P (REGNO (operands[0])))) | |
a9098fd0 | 4477 | && GET_CODE (operands[1]) != HIGH |
4d588c14 RH |
4478 | && ! legitimate_constant_pool_address_p (operands[1]) |
4479 | && ! toc_relative_expr_p (operands[1])) | |
fb4d4348 GK |
4480 | { |
4481 | /* Emit a USE operation so that the constant isn't deleted if | |
4482 | expensive optimizations are turned on because nobody | |
4483 | references it. This should only be done for operands that | |
4484 | contain SYMBOL_REFs with CONSTANT_POOL_ADDRESS_P set. | |
4485 | This should not be done for operands that contain LABEL_REFs. | |
4486 | For now, we just handle the obvious case. */ | |
4487 | if (GET_CODE (operands[1]) != LABEL_REF) | |
4488 | emit_insn (gen_rtx_USE (VOIDmode, operands[1])); | |
4489 | ||
c859cda6 | 4490 | #if TARGET_MACHO |
ee890fe2 | 4491 | /* Darwin uses a special PIC legitimizer. */ |
ab82a49f | 4492 | if (DEFAULT_ABI == ABI_DARWIN && MACHOPIC_INDIRECT) |
ee890fe2 | 4493 | { |
ee890fe2 SS |
4494 | operands[1] = |
4495 | rs6000_machopic_legitimize_pic_address (operands[1], mode, | |
c859cda6 DJ |
4496 | operands[0]); |
4497 | if (operands[0] != operands[1]) | |
4498 | emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1])); | |
ee890fe2 SS |
4499 | return; |
4500 | } | |
c859cda6 | 4501 | #endif |
ee890fe2 | 4502 | |
fb4d4348 GK |
4503 | /* If we are to limit the number of things we put in the TOC and |
4504 | this is a symbol plus a constant we can add in one insn, | |
4505 | just put the symbol in the TOC and add the constant. Don't do | |
4506 | this if reload is in progress. */ | |
4507 | if (GET_CODE (operands[1]) == CONST | |
4508 | && TARGET_NO_SUM_IN_TOC && ! reload_in_progress | |
4509 | && GET_CODE (XEXP (operands[1], 0)) == PLUS | |
a9098fd0 | 4510 | && add_operand (XEXP (XEXP (operands[1], 0), 1), mode) |
fb4d4348 GK |
4511 | && (GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == LABEL_REF |
4512 | || GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == SYMBOL_REF) | |
4513 | && ! side_effects_p (operands[0])) | |
4514 | { | |
a4f6c312 SS |
4515 | rtx sym = |
4516 | force_const_mem (mode, XEXP (XEXP (operands[1], 0), 0)); | |
fb4d4348 GK |
4517 | rtx other = XEXP (XEXP (operands[1], 0), 1); |
4518 | ||
a9098fd0 GK |
4519 | sym = force_reg (mode, sym); |
4520 | if (mode == SImode) | |
4521 | emit_insn (gen_addsi3 (operands[0], sym, other)); | |
4522 | else | |
4523 | emit_insn (gen_adddi3 (operands[0], sym, other)); | |
fb4d4348 GK |
4524 | return; |
4525 | } | |
4526 | ||
a9098fd0 | 4527 | operands[1] = force_const_mem (mode, operands[1]); |
fb4d4348 | 4528 | |
f676971a | 4529 | if (TARGET_TOC |
4d588c14 | 4530 | && constant_pool_expr_p (XEXP (operands[1], 0)) |
d34c5b80 DE |
4531 | && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P ( |
4532 | get_pool_constant (XEXP (operands[1], 0)), | |
4533 | get_pool_mode (XEXP (operands[1], 0)))) | |
a9098fd0 | 4534 | { |
ba4828e0 | 4535 | operands[1] |
542a8afa | 4536 | = gen_const_mem (mode, |
c4ad648e | 4537 | create_TOC_reference (XEXP (operands[1], 0))); |
ba4828e0 | 4538 | set_mem_alias_set (operands[1], get_TOC_alias_set ()); |
a9098fd0 | 4539 | } |
fb4d4348 GK |
4540 | } |
4541 | break; | |
a9098fd0 | 4542 | |
fb4d4348 | 4543 | case TImode: |
76d2b81d DJ |
4544 | rs6000_eliminate_indexed_memrefs (operands); |
4545 | ||
27dc0551 DE |
4546 | if (TARGET_POWER) |
4547 | { | |
4548 | emit_insn (gen_rtx_PARALLEL (VOIDmode, | |
4549 | gen_rtvec (2, | |
4550 | gen_rtx_SET (VOIDmode, | |
4551 | operands[0], operands[1]), | |
4552 | gen_rtx_CLOBBER (VOIDmode, | |
4553 | gen_rtx_SCRATCH (SImode))))); | |
4554 | return; | |
4555 | } | |
fb4d4348 GK |
4556 | break; |
4557 | ||
4558 | default: | |
4559 | abort (); | |
4560 | } | |
4561 | ||
a9098fd0 GK |
4562 | /* Above, we may have called force_const_mem which may have returned |
4563 | an invalid address. If we can, fix this up; otherwise, reload will | |
4564 | have to deal with it. */ | |
8f4e6caf RH |
4565 | if (GET_CODE (operands[1]) == MEM && ! reload_in_progress) |
4566 | operands[1] = validize_mem (operands[1]); | |
a9098fd0 | 4567 | |
8f4e6caf | 4568 | emit_set: |
fb4d4348 GK |
4569 | emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1])); |
4570 | } | |
4697a36c | 4571 | \f |
2858f73a GK |
4572 | /* Nonzero if we can use a floating-point register to pass this arg. */ |
4573 | #define USE_FP_FOR_ARG_P(CUM,MODE,TYPE) \ | |
4574 | (GET_MODE_CLASS (MODE) == MODE_FLOAT \ | |
4575 | && (CUM)->fregno <= FP_ARG_MAX_REG \ | |
4576 | && TARGET_HARD_FLOAT && TARGET_FPRS) | |
4577 | ||
4578 | /* Nonzero if we can use an AltiVec register to pass this arg. */ | |
4579 | #define USE_ALTIVEC_FOR_ARG_P(CUM,MODE,TYPE,NAMED) \ | |
4580 | (ALTIVEC_VECTOR_MODE (MODE) \ | |
4581 | && (CUM)->vregno <= ALTIVEC_ARG_MAX_REG \ | |
4582 | && TARGET_ALTIVEC_ABI \ | |
83953138 | 4583 | && (NAMED)) |
2858f73a | 4584 | |
c6e8c921 GK |
4585 | /* Return a nonzero value to say to return the function value in |
4586 | memory, just as large structures are always returned. TYPE will be | |
4587 | the data type of the value, and FNTYPE will be the type of the | |
4588 | function doing the returning, or @code{NULL} for libcalls. | |
4589 | ||
4590 | The AIX ABI for the RS/6000 specifies that all structures are | |
4591 | returned in memory. The Darwin ABI does the same. The SVR4 ABI | |
4592 | specifies that structures <= 8 bytes are returned in r3/r4, but a | |
4593 | draft put them in memory, and GCC used to implement the draft | |
4594 | instead of the final standard. Therefore, TARGET_AIX_STRUCT_RET | |
4595 | controls this instead of DEFAULT_ABI; V.4 targets needing backward | |
4596 | compatibility can change DRAFT_V4_STRUCT_RET to override the | |
4597 | default, and -m switches get the final word. See | |
4598 | rs6000_override_options for more details. | |
4599 | ||
4600 | The PPC32 SVR4 ABI uses IEEE double extended for long double, if 128-bit | |
4601 | long double support is enabled. These values are returned in memory. | |
4602 | ||
4603 | int_size_in_bytes returns -1 for variable size objects, which go in | |
4604 | memory always. The cast to unsigned makes -1 > 8. */ | |
4605 | ||
4606 | static bool | |
4607 | rs6000_return_in_memory (tree type, tree fntype ATTRIBUTE_UNUSED) | |
4608 | { | |
4609 | if (AGGREGATE_TYPE_P (type) | |
4610 | && (TARGET_AIX_STRUCT_RET | |
4611 | || (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 8)) | |
4612 | return true; | |
4613 | if (DEFAULT_ABI == ABI_V4 && TYPE_MODE (type) == TFmode) | |
4614 | return true; | |
4615 | return false; | |
4616 | } | |
4617 | ||
4697a36c MM |
4618 | /* Initialize a variable CUM of type CUMULATIVE_ARGS |
4619 | for a call to a function whose data type is FNTYPE. | |
4620 | For a library call, FNTYPE is 0. | |
4621 | ||
4622 | For incoming args we set the number of arguments in the prototype large | |
1c20ae99 | 4623 | so we never return a PARALLEL. */ |
4697a36c MM |
4624 | |
4625 | void | |
f676971a | 4626 | init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype, |
0f6937fe AM |
4627 | rtx libname ATTRIBUTE_UNUSED, int incoming, |
4628 | int libcall, int n_named_args) | |
4697a36c MM |
4629 | { |
4630 | static CUMULATIVE_ARGS zero_cumulative; | |
4631 | ||
4632 | *cum = zero_cumulative; | |
4633 | cum->words = 0; | |
4634 | cum->fregno = FP_ARG_MIN_REG; | |
0ac081f6 | 4635 | cum->vregno = ALTIVEC_ARG_MIN_REG; |
4697a36c | 4636 | cum->prototype = (fntype && TYPE_ARG_TYPES (fntype)); |
ddcc8263 DE |
4637 | cum->call_cookie = ((DEFAULT_ABI == ABI_V4 && libcall) |
4638 | ? CALL_LIBCALL : CALL_NORMAL); | |
4cc833b7 | 4639 | cum->sysv_gregno = GP_ARG_MIN_REG; |
a6c9bed4 AH |
4640 | cum->stdarg = fntype |
4641 | && (TYPE_ARG_TYPES (fntype) != 0 | |
4642 | && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype))) | |
4643 | != void_type_node)); | |
4697a36c | 4644 | |
0f6937fe AM |
4645 | cum->nargs_prototype = 0; |
4646 | if (incoming || cum->prototype) | |
4647 | cum->nargs_prototype = n_named_args; | |
4697a36c | 4648 | |
a5c76ee6 ZW |
4649 | /* Check for a longcall attribute. */ |
4650 | if (fntype | |
4651 | && lookup_attribute ("longcall", TYPE_ATTRIBUTES (fntype)) | |
4652 | && !lookup_attribute ("shortcall", TYPE_ATTRIBUTES (fntype))) | |
6a4cee5f MM |
4653 | cum->call_cookie = CALL_LONG; |
4654 | ||
4697a36c MM |
4655 | if (TARGET_DEBUG_ARG) |
4656 | { | |
4657 | fprintf (stderr, "\ninit_cumulative_args:"); | |
4658 | if (fntype) | |
4659 | { | |
4660 | tree ret_type = TREE_TYPE (fntype); | |
4661 | fprintf (stderr, " ret code = %s,", | |
4662 | tree_code_name[ (int)TREE_CODE (ret_type) ]); | |
4663 | } | |
4664 | ||
6a4cee5f MM |
4665 | if (cum->call_cookie & CALL_LONG) |
4666 | fprintf (stderr, " longcall,"); | |
4667 | ||
4697a36c MM |
4668 | fprintf (stderr, " proto = %d, nargs = %d\n", |
4669 | cum->prototype, cum->nargs_prototype); | |
4670 | } | |
f676971a | 4671 | |
c4ad648e AM |
4672 | if (fntype |
4673 | && !TARGET_ALTIVEC | |
4674 | && TARGET_ALTIVEC_ABI | |
4675 | && ALTIVEC_VECTOR_MODE (TYPE_MODE (TREE_TYPE (fntype)))) | |
4676 | { | |
4677 | error ("Cannot return value in vector register because" | |
4678 | " altivec instructions are disabled, use -maltivec" | |
4679 | " to enable them."); | |
4680 | } | |
4697a36c MM |
4681 | } |
4682 | \f | |
fe984136 RH |
4683 | /* Return true if TYPE must be passed on the stack and not in registers. */ |
4684 | ||
4685 | static bool | |
4686 | rs6000_must_pass_in_stack (enum machine_mode mode, tree type) | |
4687 | { | |
4688 | if (DEFAULT_ABI == ABI_AIX || TARGET_64BIT) | |
4689 | return must_pass_in_stack_var_size (mode, type); | |
4690 | else | |
4691 | return must_pass_in_stack_var_size_or_pad (mode, type); | |
4692 | } | |
4693 | ||
c229cba9 DE |
4694 | /* If defined, a C expression which determines whether, and in which |
4695 | direction, to pad out an argument with extra space. The value | |
4696 | should be of type `enum direction': either `upward' to pad above | |
4697 | the argument, `downward' to pad below, or `none' to inhibit | |
4698 | padding. | |
4699 | ||
4700 | For the AIX ABI structs are always stored left shifted in their | |
4701 | argument slot. */ | |
4702 | ||
9ebbca7d | 4703 | enum direction |
a2369ed3 | 4704 | function_arg_padding (enum machine_mode mode, tree type) |
c229cba9 | 4705 | { |
6e985040 AM |
4706 | #ifndef AGGREGATE_PADDING_FIXED |
4707 | #define AGGREGATE_PADDING_FIXED 0 | |
4708 | #endif | |
4709 | #ifndef AGGREGATES_PAD_UPWARD_ALWAYS | |
4710 | #define AGGREGATES_PAD_UPWARD_ALWAYS 0 | |
4711 | #endif | |
4712 | ||
4713 | if (!AGGREGATE_PADDING_FIXED) | |
4714 | { | |
4715 | /* GCC used to pass structures of the same size as integer types as | |
4716 | if they were in fact integers, ignoring FUNCTION_ARG_PADDING. | |
19525b57 | 4717 | i.e. Structures of size 1 or 2 (or 4 when TARGET_64BIT) were |
6e985040 AM |
4718 | passed padded downward, except that -mstrict-align further |
4719 | muddied the water in that multi-component structures of 2 and 4 | |
4720 | bytes in size were passed padded upward. | |
4721 | ||
4722 | The following arranges for best compatibility with previous | |
4723 | versions of gcc, but removes the -mstrict-align dependency. */ | |
4724 | if (BYTES_BIG_ENDIAN) | |
4725 | { | |
4726 | HOST_WIDE_INT size = 0; | |
4727 | ||
4728 | if (mode == BLKmode) | |
4729 | { | |
4730 | if (type && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST) | |
4731 | size = int_size_in_bytes (type); | |
4732 | } | |
4733 | else | |
4734 | size = GET_MODE_SIZE (mode); | |
4735 | ||
4736 | if (size == 1 || size == 2 || size == 4) | |
4737 | return downward; | |
4738 | } | |
4739 | return upward; | |
4740 | } | |
4741 | ||
4742 | if (AGGREGATES_PAD_UPWARD_ALWAYS) | |
4743 | { | |
4744 | if (type != 0 && AGGREGATE_TYPE_P (type)) | |
4745 | return upward; | |
4746 | } | |
c229cba9 | 4747 | |
d3704c46 KH |
4748 | /* Fall back to the default. */ |
4749 | return DEFAULT_FUNCTION_ARG_PADDING (mode, type); | |
c229cba9 DE |
4750 | } |
4751 | ||
b6c9286a | 4752 | /* If defined, a C expression that gives the alignment boundary, in bits, |
f676971a | 4753 | of an argument with the specified mode and type. If it is not defined, |
b6c9286a | 4754 | PARM_BOUNDARY is used for all arguments. |
f676971a | 4755 | |
2310f99a | 4756 | V.4 wants long longs to be double word aligned. */ |
b6c9286a MM |
4757 | |
4758 | int | |
a2369ed3 | 4759 | function_arg_boundary (enum machine_mode mode, tree type ATTRIBUTE_UNUSED) |
b6c9286a | 4760 | { |
4ed78545 AM |
4761 | if (DEFAULT_ABI == ABI_V4 && GET_MODE_SIZE (mode) == 8) |
4762 | return 64; | |
4763 | else if (SPE_VECTOR_MODE (mode)) | |
e1f83b4d | 4764 | return 64; |
b2d04ecf | 4765 | else if (ALTIVEC_VECTOR_MODE (mode)) |
0ac081f6 | 4766 | return 128; |
9ebbca7d | 4767 | else |
b6c9286a | 4768 | return PARM_BOUNDARY; |
b6c9286a | 4769 | } |
c53bdcf5 AM |
4770 | |
4771 | /* Compute the size (in words) of a function argument. */ | |
4772 | ||
4773 | static unsigned long | |
4774 | rs6000_arg_size (enum machine_mode mode, tree type) | |
4775 | { | |
4776 | unsigned long size; | |
4777 | ||
4778 | if (mode != BLKmode) | |
4779 | size = GET_MODE_SIZE (mode); | |
4780 | else | |
4781 | size = int_size_in_bytes (type); | |
4782 | ||
4783 | if (TARGET_32BIT) | |
4784 | return (size + 3) >> 2; | |
4785 | else | |
4786 | return (size + 7) >> 3; | |
4787 | } | |
b6c9286a | 4788 | \f |
4697a36c MM |
4789 | /* Update the data in CUM to advance over an argument |
4790 | of mode MODE and data type TYPE. | |
b2d04ecf AM |
4791 | (TYPE is null for libcalls where that information may not be available.) |
4792 | ||
4793 | Note that for args passed by reference, function_arg will be called | |
4794 | with MODE and TYPE set to that of the pointer to the arg, not the arg | |
4795 | itself. */ | |
4697a36c MM |
4796 | |
4797 | void | |
f676971a | 4798 | function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode, |
a2369ed3 | 4799 | tree type, int named) |
4697a36c MM |
4800 | { |
4801 | cum->nargs_prototype--; | |
4802 | ||
0ac081f6 AH |
4803 | if (TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode)) |
4804 | { | |
4ed78545 AM |
4805 | bool stack = false; |
4806 | ||
2858f73a | 4807 | if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named)) |
c4ad648e | 4808 | { |
6d0ef01e HP |
4809 | cum->vregno++; |
4810 | if (!TARGET_ALTIVEC) | |
4811 | error ("Cannot pass argument in vector register because" | |
4812 | " altivec instructions are disabled, use -maltivec" | |
4813 | " to enable them."); | |
4ed78545 AM |
4814 | |
4815 | /* PowerPC64 Linux and AIX allocate GPRs for a vector argument | |
f676971a | 4816 | even if it is going to be passed in a vector register. |
4ed78545 AM |
4817 | Darwin does the same for variable-argument functions. */ |
4818 | if ((DEFAULT_ABI == ABI_AIX && TARGET_64BIT) | |
4819 | || (cum->stdarg && DEFAULT_ABI != ABI_V4)) | |
4820 | stack = true; | |
6d0ef01e | 4821 | } |
4ed78545 AM |
4822 | else |
4823 | stack = true; | |
4824 | ||
4825 | if (stack) | |
c4ad648e | 4826 | { |
a594a19c | 4827 | int align; |
f676971a | 4828 | |
2858f73a GK |
4829 | /* Vector parameters must be 16-byte aligned. This places |
4830 | them at 2 mod 4 in terms of words in 32-bit mode, since | |
4831 | the parameter save area starts at offset 24 from the | |
4832 | stack. In 64-bit mode, they just have to start on an | |
4833 | even word, since the parameter save area is 16-byte | |
4834 | aligned. Space for GPRs is reserved even if the argument | |
4835 | will be passed in memory. */ | |
4836 | if (TARGET_32BIT) | |
4ed78545 | 4837 | align = (2 - cum->words) & 3; |
2858f73a GK |
4838 | else |
4839 | align = cum->words & 1; | |
c53bdcf5 | 4840 | cum->words += align + rs6000_arg_size (mode, type); |
f676971a | 4841 | |
a594a19c GK |
4842 | if (TARGET_DEBUG_ARG) |
4843 | { | |
f676971a | 4844 | fprintf (stderr, "function_adv: words = %2d, align=%d, ", |
a594a19c GK |
4845 | cum->words, align); |
4846 | fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s\n", | |
f676971a | 4847 | cum->nargs_prototype, cum->prototype, |
2858f73a | 4848 | GET_MODE_NAME (mode)); |
a594a19c GK |
4849 | } |
4850 | } | |
0ac081f6 | 4851 | } |
a4b0320c | 4852 | else if (TARGET_SPE_ABI && TARGET_SPE && SPE_VECTOR_MODE (mode) |
a6c9bed4 AH |
4853 | && !cum->stdarg |
4854 | && cum->sysv_gregno <= GP_ARG_MAX_REG) | |
a4b0320c | 4855 | cum->sysv_gregno++; |
f607bc57 | 4856 | else if (DEFAULT_ABI == ABI_V4) |
4697a36c | 4857 | { |
a3170dc6 | 4858 | if (TARGET_HARD_FLOAT && TARGET_FPRS |
4cc833b7 | 4859 | && (mode == SFmode || mode == DFmode)) |
4697a36c | 4860 | { |
4cc833b7 RH |
4861 | if (cum->fregno <= FP_ARG_V4_MAX_REG) |
4862 | cum->fregno++; | |
4863 | else | |
4864 | { | |
4865 | if (mode == DFmode) | |
c4ad648e | 4866 | cum->words += cum->words & 1; |
c53bdcf5 | 4867 | cum->words += rs6000_arg_size (mode, type); |
4cc833b7 | 4868 | } |
4697a36c | 4869 | } |
4cc833b7 RH |
4870 | else |
4871 | { | |
b2d04ecf | 4872 | int n_words = rs6000_arg_size (mode, type); |
4cc833b7 RH |
4873 | int gregno = cum->sysv_gregno; |
4874 | ||
4ed78545 AM |
4875 | /* Long long and SPE vectors are put in (r3,r4), (r5,r6), |
4876 | (r7,r8) or (r9,r10). As does any other 2 word item such | |
4877 | as complex int due to a historical mistake. */ | |
4878 | if (n_words == 2) | |
4879 | gregno += (1 - gregno) & 1; | |
4cc833b7 | 4880 | |
4ed78545 | 4881 | /* Multi-reg args are not split between registers and stack. */ |
4cc833b7 RH |
4882 | if (gregno + n_words - 1 > GP_ARG_MAX_REG) |
4883 | { | |
4ed78545 AM |
4884 | /* Long long and SPE vectors are aligned on the stack. |
4885 | So are other 2 word items such as complex int due to | |
4886 | a historical mistake. */ | |
4cc833b7 RH |
4887 | if (n_words == 2) |
4888 | cum->words += cum->words & 1; | |
4889 | cum->words += n_words; | |
4890 | } | |
4697a36c | 4891 | |
4cc833b7 RH |
4892 | /* Note: continuing to accumulate gregno past when we've started |
4893 | spilling to the stack indicates the fact that we've started | |
4894 | spilling to the stack to expand_builtin_saveregs. */ | |
4895 | cum->sysv_gregno = gregno + n_words; | |
4896 | } | |
4697a36c | 4897 | |
4cc833b7 RH |
4898 | if (TARGET_DEBUG_ARG) |
4899 | { | |
4900 | fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ", | |
4901 | cum->words, cum->fregno); | |
4902 | fprintf (stderr, "gregno = %2d, nargs = %4d, proto = %d, ", | |
4903 | cum->sysv_gregno, cum->nargs_prototype, cum->prototype); | |
4904 | fprintf (stderr, "mode = %4s, named = %d\n", | |
4905 | GET_MODE_NAME (mode), named); | |
4906 | } | |
4697a36c MM |
4907 | } |
4908 | else | |
4cc833b7 | 4909 | { |
b2d04ecf AM |
4910 | int n_words = rs6000_arg_size (mode, type); |
4911 | int align = function_arg_boundary (mode, type) / PARM_BOUNDARY - 1; | |
a4f6c312 | 4912 | |
b2d04ecf AM |
4913 | /* The simple alignment calculation here works because |
4914 | function_arg_boundary / PARM_BOUNDARY will only be 1 or 2. | |
4915 | If we ever want to handle alignments larger than 8 bytes for | |
4916 | 32-bit or 16 bytes for 64-bit, then we'll need to take into | |
4917 | account the offset to the start of the parm save area. */ | |
4918 | align &= cum->words; | |
4919 | cum->words += align + n_words; | |
4697a36c | 4920 | |
a3170dc6 AH |
4921 | if (GET_MODE_CLASS (mode) == MODE_FLOAT |
4922 | && TARGET_HARD_FLOAT && TARGET_FPRS) | |
c53bdcf5 | 4923 | cum->fregno += (GET_MODE_SIZE (mode) + 7) >> 3; |
4cc833b7 RH |
4924 | |
4925 | if (TARGET_DEBUG_ARG) | |
4926 | { | |
4927 | fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ", | |
4928 | cum->words, cum->fregno); | |
4929 | fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s, ", | |
4930 | cum->nargs_prototype, cum->prototype, GET_MODE_NAME (mode)); | |
4931 | fprintf (stderr, "named = %d, align = %d\n", named, align); | |
4932 | } | |
4933 | } | |
4697a36c | 4934 | } |
a6c9bed4 AH |
4935 | |
4936 | /* Determine where to put a SIMD argument on the SPE. */ | |
b78d48dd | 4937 | |
a6c9bed4 | 4938 | static rtx |
f676971a | 4939 | rs6000_spe_function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode, |
a2369ed3 | 4940 | tree type) |
a6c9bed4 AH |
4941 | { |
4942 | if (cum->stdarg) | |
4943 | { | |
4944 | int gregno = cum->sysv_gregno; | |
c53bdcf5 | 4945 | int n_words = rs6000_arg_size (mode, type); |
a6c9bed4 AH |
4946 | |
4947 | /* SPE vectors are put in odd registers. */ | |
4948 | if (n_words == 2 && (gregno & 1) == 0) | |
4949 | gregno += 1; | |
4950 | ||
4951 | if (gregno + n_words - 1 <= GP_ARG_MAX_REG) | |
4952 | { | |
4953 | rtx r1, r2; | |
4954 | enum machine_mode m = SImode; | |
4955 | ||
4956 | r1 = gen_rtx_REG (m, gregno); | |
4957 | r1 = gen_rtx_EXPR_LIST (m, r1, const0_rtx); | |
4958 | r2 = gen_rtx_REG (m, gregno + 1); | |
4959 | r2 = gen_rtx_EXPR_LIST (m, r2, GEN_INT (4)); | |
4960 | return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r2)); | |
4961 | } | |
4962 | else | |
b78d48dd | 4963 | return NULL_RTX; |
a6c9bed4 AH |
4964 | } |
4965 | else | |
4966 | { | |
4967 | if (cum->sysv_gregno <= GP_ARG_MAX_REG) | |
4968 | return gen_rtx_REG (mode, cum->sysv_gregno); | |
4969 | else | |
b78d48dd | 4970 | return NULL_RTX; |
a6c9bed4 AH |
4971 | } |
4972 | } | |
4973 | ||
b78d48dd FJ |
4974 | /* Determine where to place an argument in 64-bit mode with 32-bit ABI. */ |
4975 | ||
4976 | static rtx | |
ec6376ab | 4977 | rs6000_mixed_function_arg (enum machine_mode mode, tree type, int align_words) |
b78d48dd | 4978 | { |
ec6376ab AM |
4979 | int n_units; |
4980 | int i, k; | |
4981 | rtx rvec[GP_ARG_NUM_REG + 1]; | |
4982 | ||
4983 | if (align_words >= GP_ARG_NUM_REG) | |
4984 | return NULL_RTX; | |
4985 | ||
4986 | n_units = rs6000_arg_size (mode, type); | |
4987 | ||
4988 | /* Optimize the simple case where the arg fits in one gpr, except in | |
4989 | the case of BLKmode due to assign_parms assuming that registers are | |
4990 | BITS_PER_WORD wide. */ | |
4991 | if (n_units == 0 | |
4992 | || (n_units == 1 && mode != BLKmode)) | |
4993 | return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words); | |
4994 | ||
4995 | k = 0; | |
4996 | if (align_words + n_units > GP_ARG_NUM_REG) | |
4997 | /* Not all of the arg fits in gprs. Say that it goes in memory too, | |
4998 | using a magic NULL_RTX component. | |
4999 | FIXME: This is not strictly correct. Only some of the arg | |
5000 | belongs in memory, not all of it. However, there isn't any way | |
5001 | to do this currently, apart from building rtx descriptions for | |
5002 | the pieces of memory we want stored. Due to bugs in the generic | |
5003 | code we can't use the normal function_arg_partial_nregs scheme | |
5004 | with the PARALLEL arg description we emit here. | |
5005 | In any case, the code to store the whole arg to memory is often | |
5006 | more efficient than code to store pieces, and we know that space | |
5007 | is available in the right place for the whole arg. */ | |
5008 | rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx); | |
5009 | ||
5010 | i = 0; | |
5011 | do | |
36a454e1 | 5012 | { |
ec6376ab AM |
5013 | rtx r = gen_rtx_REG (SImode, GP_ARG_MIN_REG + align_words); |
5014 | rtx off = GEN_INT (i++ * 4); | |
5015 | rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off); | |
36a454e1 | 5016 | } |
ec6376ab AM |
5017 | while (++align_words < GP_ARG_NUM_REG && --n_units != 0); |
5018 | ||
5019 | return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec)); | |
b78d48dd FJ |
5020 | } |
5021 | ||
4697a36c MM |
5022 | /* Determine where to put an argument to a function. |
5023 | Value is zero to push the argument on the stack, | |
5024 | or a hard register in which to store the argument. | |
5025 | ||
5026 | MODE is the argument's machine mode. | |
5027 | TYPE is the data type of the argument (as a tree). | |
5028 | This is null for libcalls where that information may | |
5029 | not be available. | |
5030 | CUM is a variable of type CUMULATIVE_ARGS which gives info about | |
5031 | the preceding args and about the function being called. | |
5032 | NAMED is nonzero if this argument is a named parameter | |
5033 | (otherwise it is an extra parameter matching an ellipsis). | |
5034 | ||
5035 | On RS/6000 the first eight words of non-FP are normally in registers | |
5036 | and the rest are pushed. Under AIX, the first 13 FP args are in registers. | |
5037 | Under V.4, the first 8 FP args are in registers. | |
5038 | ||
5039 | If this is floating-point and no prototype is specified, we use | |
5040 | both an FP and integer register (or possibly FP reg and stack). Library | |
b9599e46 | 5041 | functions (when CALL_LIBCALL is set) always have the proper types for args, |
4697a36c | 5042 | so we can pass the FP value just in one register. emit_library_function |
b2d04ecf AM |
5043 | doesn't support PARALLEL anyway. |
5044 | ||
5045 | Note that for args passed by reference, function_arg will be called | |
5046 | with MODE and TYPE set to that of the pointer to the arg, not the arg | |
5047 | itself. */ | |
4697a36c MM |
5048 | |
5049 | struct rtx_def * | |
f676971a | 5050 | function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode, |
a2369ed3 | 5051 | tree type, int named) |
4697a36c | 5052 | { |
4cc833b7 | 5053 | enum rs6000_abi abi = DEFAULT_ABI; |
4697a36c | 5054 | |
a4f6c312 SS |
5055 | /* Return a marker to indicate whether CR1 needs to set or clear the |
5056 | bit that V.4 uses to say fp args were passed in registers. | |
5057 | Assume that we don't need the marker for software floating point, | |
5058 | or compiler generated library calls. */ | |
4697a36c MM |
5059 | if (mode == VOIDmode) |
5060 | { | |
f607bc57 | 5061 | if (abi == ABI_V4 |
7509c759 | 5062 | && cum->nargs_prototype < 0 |
b9599e46 FS |
5063 | && (cum->call_cookie & CALL_LIBCALL) == 0 |
5064 | && (cum->prototype || TARGET_NO_PROTOTYPE)) | |
7509c759 | 5065 | { |
a3170dc6 AH |
5066 | /* For the SPE, we need to crxor CR6 always. */ |
5067 | if (TARGET_SPE_ABI) | |
5068 | return GEN_INT (cum->call_cookie | CALL_V4_SET_FP_ARGS); | |
5069 | else if (TARGET_HARD_FLOAT && TARGET_FPRS) | |
5070 | return GEN_INT (cum->call_cookie | |
5071 | | ((cum->fregno == FP_ARG_MIN_REG) | |
5072 | ? CALL_V4_SET_FP_ARGS | |
5073 | : CALL_V4_CLEAR_FP_ARGS)); | |
7509c759 | 5074 | } |
4697a36c | 5075 | |
7509c759 | 5076 | return GEN_INT (cum->call_cookie); |
4697a36c MM |
5077 | } |
5078 | ||
2858f73a | 5079 | if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named)) |
c72d6c26 HP |
5080 | if (TARGET_64BIT && ! cum->prototype) |
5081 | { | |
c4ad648e AM |
5082 | /* Vector parameters get passed in vector register |
5083 | and also in GPRs or memory, in absence of prototype. */ | |
5084 | int align_words; | |
5085 | rtx slot; | |
5086 | align_words = (cum->words + 1) & ~1; | |
5087 | ||
5088 | if (align_words >= GP_ARG_NUM_REG) | |
5089 | { | |
5090 | slot = NULL_RTX; | |
5091 | } | |
5092 | else | |
5093 | { | |
5094 | slot = gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words); | |
5095 | } | |
5096 | return gen_rtx_PARALLEL (mode, | |
5097 | gen_rtvec (2, | |
5098 | gen_rtx_EXPR_LIST (VOIDmode, | |
5099 | slot, const0_rtx), | |
5100 | gen_rtx_EXPR_LIST (VOIDmode, | |
5101 | gen_rtx_REG (mode, cum->vregno), | |
5102 | const0_rtx))); | |
c72d6c26 HP |
5103 | } |
5104 | else | |
5105 | return gen_rtx_REG (mode, cum->vregno); | |
2858f73a | 5106 | else if (TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode)) |
0ac081f6 | 5107 | { |
2858f73a | 5108 | if (named || abi == ABI_V4) |
a594a19c | 5109 | return NULL_RTX; |
0ac081f6 | 5110 | else |
a594a19c GK |
5111 | { |
5112 | /* Vector parameters to varargs functions under AIX or Darwin | |
5113 | get passed in memory and possibly also in GPRs. */ | |
ec6376ab AM |
5114 | int align, align_words, n_words; |
5115 | enum machine_mode part_mode; | |
a594a19c GK |
5116 | |
5117 | /* Vector parameters must be 16-byte aligned. This places them at | |
2858f73a GK |
5118 | 2 mod 4 in terms of words in 32-bit mode, since the parameter |
5119 | save area starts at offset 24 from the stack. In 64-bit mode, | |
5120 | they just have to start on an even word, since the parameter | |
5121 | save area is 16-byte aligned. */ | |
5122 | if (TARGET_32BIT) | |
4ed78545 | 5123 | align = (2 - cum->words) & 3; |
2858f73a GK |
5124 | else |
5125 | align = cum->words & 1; | |
a594a19c GK |
5126 | align_words = cum->words + align; |
5127 | ||
5128 | /* Out of registers? Memory, then. */ | |
5129 | if (align_words >= GP_ARG_NUM_REG) | |
5130 | return NULL_RTX; | |
ec6376ab AM |
5131 | |
5132 | if (TARGET_32BIT && TARGET_POWERPC64) | |
5133 | return rs6000_mixed_function_arg (mode, type, align_words); | |
5134 | ||
2858f73a GK |
5135 | /* The vector value goes in GPRs. Only the part of the |
5136 | value in GPRs is reported here. */ | |
ec6376ab AM |
5137 | part_mode = mode; |
5138 | n_words = rs6000_arg_size (mode, type); | |
5139 | if (align_words + n_words > GP_ARG_NUM_REG) | |
839a4992 | 5140 | /* Fortunately, there are only two possibilities, the value |
2858f73a GK |
5141 | is either wholly in GPRs or half in GPRs and half not. */ |
5142 | part_mode = DImode; | |
ec6376ab AM |
5143 | |
5144 | return gen_rtx_REG (part_mode, GP_ARG_MIN_REG + align_words); | |
a594a19c | 5145 | } |
0ac081f6 | 5146 | } |
a6c9bed4 AH |
5147 | else if (TARGET_SPE_ABI && TARGET_SPE && SPE_VECTOR_MODE (mode)) |
5148 | return rs6000_spe_function_arg (cum, mode, type); | |
f607bc57 | 5149 | else if (abi == ABI_V4) |
4697a36c | 5150 | { |
a3170dc6 | 5151 | if (TARGET_HARD_FLOAT && TARGET_FPRS |
4cc833b7 RH |
5152 | && (mode == SFmode || mode == DFmode)) |
5153 | { | |
5154 | if (cum->fregno <= FP_ARG_V4_MAX_REG) | |
5155 | return gen_rtx_REG (mode, cum->fregno); | |
5156 | else | |
b78d48dd | 5157 | return NULL_RTX; |
4cc833b7 RH |
5158 | } |
5159 | else | |
5160 | { | |
b2d04ecf | 5161 | int n_words = rs6000_arg_size (mode, type); |
4cc833b7 RH |
5162 | int gregno = cum->sysv_gregno; |
5163 | ||
4ed78545 AM |
5164 | /* Long long and SPE vectors are put in (r3,r4), (r5,r6), |
5165 | (r7,r8) or (r9,r10). As does any other 2 word item such | |
5166 | as complex int due to a historical mistake. */ | |
5167 | if (n_words == 2) | |
5168 | gregno += (1 - gregno) & 1; | |
4cc833b7 | 5169 | |
4ed78545 | 5170 | /* Multi-reg args are not split between registers and stack. */ |
ec6376ab | 5171 | if (gregno + n_words - 1 > GP_ARG_MAX_REG) |
b78d48dd | 5172 | return NULL_RTX; |
ec6376ab AM |
5173 | |
5174 | if (TARGET_32BIT && TARGET_POWERPC64) | |
5175 | return rs6000_mixed_function_arg (mode, type, | |
5176 | gregno - GP_ARG_MIN_REG); | |
5177 | return gen_rtx_REG (mode, gregno); | |
4cc833b7 | 5178 | } |
4697a36c | 5179 | } |
4cc833b7 RH |
5180 | else |
5181 | { | |
b2d04ecf AM |
5182 | int align = function_arg_boundary (mode, type) / PARM_BOUNDARY - 1; |
5183 | int align_words = cum->words + (cum->words & align); | |
b78d48dd | 5184 | |
2858f73a | 5185 | if (USE_FP_FOR_ARG_P (cum, mode, type)) |
4cc833b7 | 5186 | { |
ec6376ab AM |
5187 | rtx rvec[GP_ARG_NUM_REG + 1]; |
5188 | rtx r; | |
5189 | int k; | |
c53bdcf5 AM |
5190 | bool needs_psave; |
5191 | enum machine_mode fmode = mode; | |
c53bdcf5 AM |
5192 | unsigned long n_fpreg = (GET_MODE_SIZE (mode) + 7) >> 3; |
5193 | ||
5194 | if (cum->fregno + n_fpreg > FP_ARG_MAX_REG + 1) | |
5195 | { | |
c53bdcf5 AM |
5196 | /* Currently, we only ever need one reg here because complex |
5197 | doubles are split. */ | |
ec6376ab | 5198 | if (cum->fregno != FP_ARG_MAX_REG || fmode != TFmode) |
c53bdcf5 | 5199 | abort (); |
ec6376ab AM |
5200 | |
5201 | /* Long double split over regs and memory. */ | |
5202 | fmode = DFmode; | |
c53bdcf5 | 5203 | } |
c53bdcf5 AM |
5204 | |
5205 | /* Do we also need to pass this arg in the parameter save | |
5206 | area? */ | |
5207 | needs_psave = (type | |
5208 | && (cum->nargs_prototype <= 0 | |
5209 | || (DEFAULT_ABI == ABI_AIX | |
5210 | && TARGET_XL_CALL | |
5211 | && align_words >= GP_ARG_NUM_REG))); | |
5212 | ||
5213 | if (!needs_psave && mode == fmode) | |
ec6376ab | 5214 | return gen_rtx_REG (fmode, cum->fregno); |
c53bdcf5 | 5215 | |
ec6376ab | 5216 | k = 0; |
c53bdcf5 AM |
5217 | if (needs_psave) |
5218 | { | |
ec6376ab | 5219 | /* Describe the part that goes in gprs or the stack. |
c53bdcf5 | 5220 | This piece must come first, before the fprs. */ |
c53bdcf5 AM |
5221 | if (align_words < GP_ARG_NUM_REG) |
5222 | { | |
5223 | unsigned long n_words = rs6000_arg_size (mode, type); | |
ec6376ab AM |
5224 | |
5225 | if (align_words + n_words > GP_ARG_NUM_REG | |
5226 | || (TARGET_32BIT && TARGET_POWERPC64)) | |
5227 | { | |
5228 | /* If this is partially on the stack, then we only | |
5229 | include the portion actually in registers here. */ | |
5230 | enum machine_mode rmode = TARGET_32BIT ? SImode : DImode; | |
5231 | rtx off; | |
2e6c9641 | 5232 | int i=0; |
c4ad648e AM |
5233 | if (align_words + n_words > GP_ARG_NUM_REG |
5234 | && (TARGET_32BIT && TARGET_POWERPC64)) | |
5235 | /* Not all of the arg fits in gprs. Say that it | |
5236 | goes in memory too, using a magic NULL_RTX | |
5237 | component. Also see comment in | |
5238 | rs6000_mixed_function_arg for why the normal | |
5239 | function_arg_partial_nregs scheme doesn't work | |
5240 | in this case. */ | |
5241 | rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, | |
5242 | const0_rtx); | |
ec6376ab AM |
5243 | do |
5244 | { | |
5245 | r = gen_rtx_REG (rmode, | |
5246 | GP_ARG_MIN_REG + align_words); | |
2e6c9641 | 5247 | off = GEN_INT (i++ * GET_MODE_SIZE (rmode)); |
ec6376ab AM |
5248 | rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off); |
5249 | } | |
5250 | while (++align_words < GP_ARG_NUM_REG && --n_words != 0); | |
5251 | } | |
5252 | else | |
5253 | { | |
5254 | /* The whole arg fits in gprs. */ | |
5255 | r = gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words); | |
5256 | rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, const0_rtx); | |
5257 | } | |
c53bdcf5 | 5258 | } |
ec6376ab AM |
5259 | else |
5260 | /* It's entirely in memory. */ | |
5261 | rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx); | |
c53bdcf5 AM |
5262 | } |
5263 | ||
ec6376ab AM |
5264 | /* Describe where this piece goes in the fprs. */ |
5265 | r = gen_rtx_REG (fmode, cum->fregno); | |
5266 | rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, const0_rtx); | |
5267 | ||
5268 | return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec)); | |
4cc833b7 RH |
5269 | } |
5270 | else if (align_words < GP_ARG_NUM_REG) | |
b2d04ecf | 5271 | { |
ec6376ab AM |
5272 | if (TARGET_32BIT && TARGET_POWERPC64) |
5273 | return rs6000_mixed_function_arg (mode, type, align_words); | |
b2d04ecf AM |
5274 | |
5275 | return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words); | |
5276 | } | |
4cc833b7 RH |
5277 | else |
5278 | return NULL_RTX; | |
4697a36c | 5279 | } |
4697a36c MM |
5280 | } |
5281 | \f | |
ec6376ab AM |
5282 | /* For an arg passed partly in registers and partly in memory, this is |
5283 | the number of registers used. For args passed entirely in registers | |
5284 | or entirely in memory, zero. When an arg is described by a PARALLEL, | |
5285 | perhaps using more than one register type, this function returns the | |
5286 | number of registers used by the first element of the PARALLEL. */ | |
4697a36c MM |
5287 | |
5288 | int | |
f676971a | 5289 | function_arg_partial_nregs (CUMULATIVE_ARGS *cum, enum machine_mode mode, |
2858f73a | 5290 | tree type, int named) |
4697a36c | 5291 | { |
c53bdcf5 | 5292 | int ret = 0; |
ec6376ab AM |
5293 | int align; |
5294 | int parm_offset; | |
5295 | int align_words; | |
c53bdcf5 | 5296 | |
f607bc57 | 5297 | if (DEFAULT_ABI == ABI_V4) |
4697a36c | 5298 | return 0; |
4697a36c | 5299 | |
c53bdcf5 AM |
5300 | if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named) |
5301 | && cum->nargs_prototype >= 0) | |
5302 | return 0; | |
5303 | ||
ec6376ab AM |
5304 | align = function_arg_boundary (mode, type) / PARM_BOUNDARY - 1; |
5305 | parm_offset = TARGET_32BIT ? 2 : 0; | |
5306 | align_words = cum->words + ((parm_offset - cum->words) & align); | |
5307 | ||
5308 | if (USE_FP_FOR_ARG_P (cum, mode, type) | |
5309 | /* If we are passing this arg in gprs as well, then this function | |
5310 | should return the number of gprs (or memory) partially passed, | |
5311 | *not* the number of fprs. */ | |
5312 | && !(type | |
5313 | && (cum->nargs_prototype <= 0 | |
5314 | || (DEFAULT_ABI == ABI_AIX | |
5315 | && TARGET_XL_CALL | |
5316 | && align_words >= GP_ARG_NUM_REG)))) | |
4697a36c | 5317 | { |
c53bdcf5 | 5318 | if (cum->fregno + ((GET_MODE_SIZE (mode) + 7) >> 3) > FP_ARG_MAX_REG + 1) |
ec6376ab | 5319 | ret = FP_ARG_MAX_REG + 1 - cum->fregno; |
c53bdcf5 | 5320 | else if (cum->nargs_prototype >= 0) |
4697a36c MM |
5321 | return 0; |
5322 | } | |
5323 | ||
ec6376ab AM |
5324 | if (align_words < GP_ARG_NUM_REG |
5325 | && GP_ARG_NUM_REG < align_words + rs6000_arg_size (mode, type)) | |
5326 | ret = GP_ARG_NUM_REG - align_words; | |
4697a36c | 5327 | |
c53bdcf5 AM |
5328 | if (ret != 0 && TARGET_DEBUG_ARG) |
5329 | fprintf (stderr, "function_arg_partial_nregs: %d\n", ret); | |
4697a36c | 5330 | |
c53bdcf5 | 5331 | return ret; |
4697a36c MM |
5332 | } |
5333 | \f | |
5334 | /* A C expression that indicates when an argument must be passed by | |
5335 | reference. If nonzero for an argument, a copy of that argument is | |
5336 | made in memory and a pointer to the argument is passed instead of | |
5337 | the argument itself. The pointer is passed in whatever way is | |
5338 | appropriate for passing a pointer to that type. | |
5339 | ||
b2d04ecf AM |
5340 | Under V.4, aggregates and long double are passed by reference. |
5341 | ||
5342 | As an extension to all 32-bit ABIs, AltiVec vectors are passed by | |
5343 | reference unless the AltiVec vector extension ABI is in force. | |
c8c99a68 DE |
5344 | |
5345 | As an extension to all ABIs, variable sized types are passed by | |
5346 | reference. */ | |
4697a36c | 5347 | |
8cd5a4e0 | 5348 | static bool |
f676971a EC |
5349 | rs6000_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED, |
5350 | enum machine_mode mode ATTRIBUTE_UNUSED, | |
8cd5a4e0 | 5351 | tree type, bool named ATTRIBUTE_UNUSED) |
4697a36c | 5352 | { |
b2d04ecf AM |
5353 | if ((DEFAULT_ABI == ABI_V4 |
5354 | && ((type && AGGREGATE_TYPE_P (type)) | |
5355 | || mode == TFmode)) | |
5356 | || (TARGET_32BIT && !TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode)) | |
5357 | || (type && int_size_in_bytes (type) < 0)) | |
4697a36c MM |
5358 | { |
5359 | if (TARGET_DEBUG_ARG) | |
b2d04ecf | 5360 | fprintf (stderr, "function_arg_pass_by_reference\n"); |
4697a36c MM |
5361 | |
5362 | return 1; | |
5363 | } | |
b2d04ecf | 5364 | return 0; |
4697a36c | 5365 | } |
5985c7a6 FJ |
5366 | |
5367 | static void | |
2d9db8eb | 5368 | rs6000_move_block_from_reg (int regno, rtx x, int nregs) |
5985c7a6 FJ |
5369 | { |
5370 | int i; | |
5371 | enum machine_mode reg_mode = TARGET_32BIT ? SImode : DImode; | |
5372 | ||
5373 | if (nregs == 0) | |
5374 | return; | |
5375 | ||
c4ad648e | 5376 | for (i = 0; i < nregs; i++) |
5985c7a6 FJ |
5377 | { |
5378 | rtx tem = adjust_address_nv (x, reg_mode, i*GET_MODE_SIZE(reg_mode)); | |
5379 | if (reload_completed) | |
c4ad648e AM |
5380 | { |
5381 | if (! strict_memory_address_p (reg_mode, XEXP (tem, 0))) | |
5382 | tem = NULL_RTX; | |
5383 | else | |
5384 | tem = simplify_gen_subreg (reg_mode, x, BLKmode, | |
5385 | i * GET_MODE_SIZE(reg_mode)); | |
5386 | } | |
5985c7a6 FJ |
5387 | else |
5388 | tem = replace_equiv_address (tem, XEXP (tem, 0)); | |
5389 | ||
5390 | if (tem == NULL_RTX) | |
c4ad648e | 5391 | abort (); |
5985c7a6 FJ |
5392 | |
5393 | emit_move_insn (tem, gen_rtx_REG (reg_mode, regno + i)); | |
5394 | } | |
5395 | } | |
4697a36c MM |
5396 | \f |
5397 | /* Perform any needed actions needed for a function that is receiving a | |
f676971a | 5398 | variable number of arguments. |
4697a36c MM |
5399 | |
5400 | CUM is as above. | |
5401 | ||
5402 | MODE and TYPE are the mode and type of the current parameter. | |
5403 | ||
5404 | PRETEND_SIZE is a variable that should be set to the amount of stack | |
5405 | that must be pushed by the prolog to pretend that our caller pushed | |
5406 | it. | |
5407 | ||
5408 | Normally, this macro will push all remaining incoming registers on the | |
5409 | stack and set PRETEND_SIZE to the length of the registers pushed. */ | |
5410 | ||
c6e8c921 | 5411 | static void |
f676971a | 5412 | setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode, |
c4ad648e AM |
5413 | tree type, int *pretend_size ATTRIBUTE_UNUSED, |
5414 | int no_rtl) | |
4697a36c | 5415 | { |
4cc833b7 RH |
5416 | CUMULATIVE_ARGS next_cum; |
5417 | int reg_size = TARGET_32BIT ? 4 : 8; | |
ca5adc63 | 5418 | rtx save_area = NULL_RTX, mem; |
dfafc897 | 5419 | int first_reg_offset, set; |
4697a36c | 5420 | |
f31bf321 | 5421 | /* Skip the last named argument. */ |
d34c5b80 | 5422 | next_cum = *cum; |
f31bf321 | 5423 | function_arg_advance (&next_cum, mode, type, 1); |
4cc833b7 | 5424 | |
f607bc57 | 5425 | if (DEFAULT_ABI == ABI_V4) |
d34c5b80 | 5426 | { |
60e2d0ca | 5427 | if (! no_rtl) |
2c4974b7 | 5428 | save_area = plus_constant (virtual_stack_vars_rtx, |
bd227acc | 5429 | - RS6000_VARARGS_SIZE); |
4cc833b7 RH |
5430 | |
5431 | first_reg_offset = next_cum.sysv_gregno - GP_ARG_MIN_REG; | |
4697a36c | 5432 | } |
60e2d0ca | 5433 | else |
4697a36c | 5434 | { |
d34c5b80 | 5435 | first_reg_offset = next_cum.words; |
4cc833b7 | 5436 | save_area = virtual_incoming_args_rtx; |
4697a36c | 5437 | |
fe984136 | 5438 | if (targetm.calls.must_pass_in_stack (mode, type)) |
c53bdcf5 | 5439 | first_reg_offset += rs6000_arg_size (TYPE_MODE (type), type); |
4cc833b7 | 5440 | } |
4697a36c | 5441 | |
dfafc897 | 5442 | set = get_varargs_alias_set (); |
5496b36f | 5443 | if (! no_rtl && first_reg_offset < GP_ARG_NUM_REG) |
4cc833b7 | 5444 | { |
dfafc897 | 5445 | mem = gen_rtx_MEM (BLKmode, |
c4ad648e | 5446 | plus_constant (save_area, |
dfafc897 | 5447 | first_reg_offset * reg_size)), |
ba4828e0 | 5448 | set_mem_alias_set (mem, set); |
8ac61af7 | 5449 | set_mem_align (mem, BITS_PER_WORD); |
dfafc897 | 5450 | |
f676971a | 5451 | rs6000_move_block_from_reg (GP_ARG_MIN_REG + first_reg_offset, mem, |
c4ad648e | 5452 | GP_ARG_NUM_REG - first_reg_offset); |
4697a36c MM |
5453 | } |
5454 | ||
4697a36c | 5455 | /* Save FP registers if needed. */ |
f607bc57 | 5456 | if (DEFAULT_ABI == ABI_V4 |
a3170dc6 AH |
5457 | && TARGET_HARD_FLOAT && TARGET_FPRS |
5458 | && ! no_rtl | |
5496b36f | 5459 | && next_cum.fregno <= FP_ARG_V4_MAX_REG) |
4697a36c | 5460 | { |
5496b36f | 5461 | int fregno = next_cum.fregno; |
9ebbca7d | 5462 | rtx cr1 = gen_rtx_REG (CCmode, CR1_REGNO); |
4cc833b7 RH |
5463 | rtx lab = gen_label_rtx (); |
5464 | int off = (GP_ARG_NUM_REG * reg_size) + ((fregno - FP_ARG_MIN_REG) * 8); | |
4697a36c | 5465 | |
c4ad648e AM |
5466 | emit_jump_insn |
5467 | (gen_rtx_SET (VOIDmode, | |
5468 | pc_rtx, | |
5469 | gen_rtx_IF_THEN_ELSE (VOIDmode, | |
4cc833b7 | 5470 | gen_rtx_NE (VOIDmode, cr1, |
c4ad648e | 5471 | const0_rtx), |
39403d82 | 5472 | gen_rtx_LABEL_REF (VOIDmode, lab), |
4697a36c MM |
5473 | pc_rtx))); |
5474 | ||
5496b36f | 5475 | while (fregno <= FP_ARG_V4_MAX_REG) |
4cc833b7 | 5476 | { |
5496b36f | 5477 | mem = gen_rtx_MEM (DFmode, plus_constant (save_area, off)); |
c4ad648e | 5478 | set_mem_alias_set (mem, set); |
dfafc897 | 5479 | emit_move_insn (mem, gen_rtx_REG (DFmode, fregno)); |
5496b36f JJ |
5480 | fregno++; |
5481 | off += 8; | |
4697a36c | 5482 | } |
4cc833b7 RH |
5483 | |
5484 | emit_label (lab); | |
4697a36c | 5485 | } |
4697a36c | 5486 | } |
4697a36c | 5487 | |
dfafc897 | 5488 | /* Create the va_list data type. */ |
2c4974b7 | 5489 | |
c35d187f RH |
5490 | static tree |
5491 | rs6000_build_builtin_va_list (void) | |
dfafc897 | 5492 | { |
64c2816f | 5493 | tree f_gpr, f_fpr, f_res, f_ovf, f_sav, record, type_decl; |
4697a36c | 5494 | |
9ebbca7d GK |
5495 | /* For AIX, prefer 'char *' because that's what the system |
5496 | header files like. */ | |
f607bc57 | 5497 | if (DEFAULT_ABI != ABI_V4) |
9ebbca7d | 5498 | return build_pointer_type (char_type_node); |
dfafc897 | 5499 | |
f1e639b1 | 5500 | record = (*lang_hooks.types.make_type) (RECORD_TYPE); |
bab45a51 | 5501 | type_decl = build_decl (TYPE_DECL, get_identifier ("__va_list_tag"), record); |
0f4fd75d | 5502 | |
f676971a | 5503 | f_gpr = build_decl (FIELD_DECL, get_identifier ("gpr"), |
9ebbca7d | 5504 | unsigned_char_type_node); |
f676971a | 5505 | f_fpr = build_decl (FIELD_DECL, get_identifier ("fpr"), |
9ebbca7d | 5506 | unsigned_char_type_node); |
64c2816f DT |
5507 | /* Give the two bytes of padding a name, so that -Wpadded won't warn on |
5508 | every user file. */ | |
5509 | f_res = build_decl (FIELD_DECL, get_identifier ("reserved"), | |
5510 | short_unsigned_type_node); | |
dfafc897 FS |
5511 | f_ovf = build_decl (FIELD_DECL, get_identifier ("overflow_arg_area"), |
5512 | ptr_type_node); | |
5513 | f_sav = build_decl (FIELD_DECL, get_identifier ("reg_save_area"), | |
5514 | ptr_type_node); | |
5515 | ||
5516 | DECL_FIELD_CONTEXT (f_gpr) = record; | |
5517 | DECL_FIELD_CONTEXT (f_fpr) = record; | |
64c2816f | 5518 | DECL_FIELD_CONTEXT (f_res) = record; |
dfafc897 FS |
5519 | DECL_FIELD_CONTEXT (f_ovf) = record; |
5520 | DECL_FIELD_CONTEXT (f_sav) = record; | |
5521 | ||
bab45a51 FS |
5522 | TREE_CHAIN (record) = type_decl; |
5523 | TYPE_NAME (record) = type_decl; | |
dfafc897 FS |
5524 | TYPE_FIELDS (record) = f_gpr; |
5525 | TREE_CHAIN (f_gpr) = f_fpr; | |
64c2816f DT |
5526 | TREE_CHAIN (f_fpr) = f_res; |
5527 | TREE_CHAIN (f_res) = f_ovf; | |
dfafc897 FS |
5528 | TREE_CHAIN (f_ovf) = f_sav; |
5529 | ||
5530 | layout_type (record); | |
5531 | ||
5532 | /* The correct type is an array type of one element. */ | |
5533 | return build_array_type (record, build_index_type (size_zero_node)); | |
5534 | } | |
5535 | ||
5536 | /* Implement va_start. */ | |
5537 | ||
5538 | void | |
a2369ed3 | 5539 | rs6000_va_start (tree valist, rtx nextarg) |
4697a36c | 5540 | { |
dfafc897 | 5541 | HOST_WIDE_INT words, n_gpr, n_fpr; |
c566f9bd | 5542 | tree f_gpr, f_fpr, f_res, f_ovf, f_sav; |
dfafc897 | 5543 | tree gpr, fpr, ovf, sav, t; |
2c4974b7 | 5544 | |
dfafc897 | 5545 | /* Only SVR4 needs something special. */ |
f607bc57 | 5546 | if (DEFAULT_ABI != ABI_V4) |
dfafc897 | 5547 | { |
e5faf155 | 5548 | std_expand_builtin_va_start (valist, nextarg); |
dfafc897 FS |
5549 | return; |
5550 | } | |
5551 | ||
973a648b | 5552 | f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node)); |
dfafc897 | 5553 | f_fpr = TREE_CHAIN (f_gpr); |
c566f9bd DT |
5554 | f_res = TREE_CHAIN (f_fpr); |
5555 | f_ovf = TREE_CHAIN (f_res); | |
dfafc897 FS |
5556 | f_sav = TREE_CHAIN (f_ovf); |
5557 | ||
872a65b5 | 5558 | valist = build_va_arg_indirect_ref (valist); |
44de5aeb RK |
5559 | gpr = build (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE); |
5560 | fpr = build (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE); | |
5561 | ovf = build (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE); | |
5562 | sav = build (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE); | |
dfafc897 FS |
5563 | |
5564 | /* Count number of gp and fp argument registers used. */ | |
4cc833b7 | 5565 | words = current_function_args_info.words; |
dfafc897 FS |
5566 | n_gpr = current_function_args_info.sysv_gregno - GP_ARG_MIN_REG; |
5567 | n_fpr = current_function_args_info.fregno - FP_ARG_MIN_REG; | |
5568 | ||
5569 | if (TARGET_DEBUG_ARG) | |
4a0a75dd KG |
5570 | fprintf (stderr, "va_start: words = "HOST_WIDE_INT_PRINT_DEC", n_gpr = " |
5571 | HOST_WIDE_INT_PRINT_DEC", n_fpr = "HOST_WIDE_INT_PRINT_DEC"\n", | |
5572 | words, n_gpr, n_fpr); | |
dfafc897 | 5573 | |
5496b36f JJ |
5574 | t = build (MODIFY_EXPR, TREE_TYPE (gpr), gpr, |
5575 | build_int_cst (NULL_TREE, n_gpr)); | |
5576 | TREE_SIDE_EFFECTS (t) = 1; | |
5577 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
58c8adc1 | 5578 | |
5496b36f JJ |
5579 | t = build (MODIFY_EXPR, TREE_TYPE (fpr), fpr, |
5580 | build_int_cst (NULL_TREE, n_fpr)); | |
5581 | TREE_SIDE_EFFECTS (t) = 1; | |
5582 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
dfafc897 FS |
5583 | |
5584 | /* Find the overflow area. */ | |
5585 | t = make_tree (TREE_TYPE (ovf), virtual_incoming_args_rtx); | |
5586 | if (words != 0) | |
5587 | t = build (PLUS_EXPR, TREE_TYPE (ovf), t, | |
7d60be94 | 5588 | build_int_cst (NULL_TREE, words * UNITS_PER_WORD)); |
dfafc897 FS |
5589 | t = build (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t); |
5590 | TREE_SIDE_EFFECTS (t) = 1; | |
5591 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
5592 | ||
5593 | /* Find the register save area. */ | |
5594 | t = make_tree (TREE_TYPE (sav), virtual_stack_vars_rtx); | |
5595 | t = build (PLUS_EXPR, TREE_TYPE (sav), t, | |
7d60be94 | 5596 | build_int_cst (NULL_TREE, -RS6000_VARARGS_SIZE)); |
dfafc897 FS |
5597 | t = build (MODIFY_EXPR, TREE_TYPE (sav), sav, t); |
5598 | TREE_SIDE_EFFECTS (t) = 1; | |
5599 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
5600 | } | |
5601 | ||
5602 | /* Implement va_arg. */ | |
5603 | ||
23a60a04 JM |
5604 | tree |
5605 | rs6000_gimplify_va_arg (tree valist, tree type, tree *pre_p, tree *post_p) | |
cd3ce9b4 | 5606 | { |
cd3ce9b4 JM |
5607 | tree f_gpr, f_fpr, f_res, f_ovf, f_sav; |
5608 | tree gpr, fpr, ovf, sav, reg, t, u; | |
08b0dc1b | 5609 | int size, rsize, n_reg, sav_ofs, sav_scale; |
cd3ce9b4 JM |
5610 | tree lab_false, lab_over, addr; |
5611 | int align; | |
5612 | tree ptrtype = build_pointer_type (type); | |
5613 | ||
08b0dc1b RH |
5614 | if (pass_by_reference (NULL, TYPE_MODE (type), type, false)) |
5615 | { | |
5616 | t = rs6000_gimplify_va_arg (valist, ptrtype, pre_p, post_p); | |
872a65b5 | 5617 | return build_va_arg_indirect_ref (t); |
08b0dc1b RH |
5618 | } |
5619 | ||
cd3ce9b4 JM |
5620 | if (DEFAULT_ABI != ABI_V4) |
5621 | { | |
08b0dc1b | 5622 | if (targetm.calls.split_complex_arg && TREE_CODE (type) == COMPLEX_TYPE) |
cd3ce9b4 JM |
5623 | { |
5624 | tree elem_type = TREE_TYPE (type); | |
5625 | enum machine_mode elem_mode = TYPE_MODE (elem_type); | |
5626 | int elem_size = GET_MODE_SIZE (elem_mode); | |
5627 | ||
5628 | if (elem_size < UNITS_PER_WORD) | |
5629 | { | |
23a60a04 | 5630 | tree real_part, imag_part; |
cd3ce9b4 JM |
5631 | tree post = NULL_TREE; |
5632 | ||
23a60a04 JM |
5633 | real_part = rs6000_gimplify_va_arg (valist, elem_type, pre_p, |
5634 | &post); | |
5635 | /* Copy the value into a temporary, lest the formal temporary | |
5636 | be reused out from under us. */ | |
5637 | real_part = get_initialized_tmp_var (real_part, pre_p, &post); | |
cd3ce9b4 JM |
5638 | append_to_statement_list (post, pre_p); |
5639 | ||
23a60a04 JM |
5640 | imag_part = rs6000_gimplify_va_arg (valist, elem_type, pre_p, |
5641 | post_p); | |
cd3ce9b4 | 5642 | |
23a60a04 | 5643 | return build (COMPLEX_EXPR, type, real_part, imag_part); |
cd3ce9b4 JM |
5644 | } |
5645 | } | |
5646 | ||
23a60a04 | 5647 | return std_gimplify_va_arg_expr (valist, type, pre_p, post_p); |
cd3ce9b4 JM |
5648 | } |
5649 | ||
5650 | f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node)); | |
5651 | f_fpr = TREE_CHAIN (f_gpr); | |
5652 | f_res = TREE_CHAIN (f_fpr); | |
5653 | f_ovf = TREE_CHAIN (f_res); | |
5654 | f_sav = TREE_CHAIN (f_ovf); | |
5655 | ||
872a65b5 | 5656 | valist = build_va_arg_indirect_ref (valist); |
44de5aeb RK |
5657 | gpr = build (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE); |
5658 | fpr = build (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE); | |
5659 | ovf = build (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE); | |
5660 | sav = build (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE); | |
cd3ce9b4 JM |
5661 | |
5662 | size = int_size_in_bytes (type); | |
5663 | rsize = (size + 3) / 4; | |
5664 | align = 1; | |
5665 | ||
08b0dc1b RH |
5666 | if (TARGET_HARD_FLOAT && TARGET_FPRS |
5667 | && (TYPE_MODE (type) == SFmode || TYPE_MODE (type) == DFmode)) | |
cd3ce9b4 JM |
5668 | { |
5669 | /* FP args go in FP registers, if present. */ | |
cd3ce9b4 JM |
5670 | reg = fpr; |
5671 | n_reg = 1; | |
5672 | sav_ofs = 8*4; | |
5673 | sav_scale = 8; | |
5674 | if (TYPE_MODE (type) == DFmode) | |
5675 | align = 8; | |
5676 | } | |
5677 | else | |
5678 | { | |
5679 | /* Otherwise into GP registers. */ | |
cd3ce9b4 JM |
5680 | reg = gpr; |
5681 | n_reg = rsize; | |
5682 | sav_ofs = 0; | |
5683 | sav_scale = 4; | |
5684 | if (n_reg == 2) | |
5685 | align = 8; | |
5686 | } | |
5687 | ||
5688 | /* Pull the value out of the saved registers.... */ | |
5689 | ||
5690 | lab_over = NULL; | |
5691 | addr = create_tmp_var (ptr_type_node, "addr"); | |
5692 | DECL_POINTER_ALIAS_SET (addr) = get_varargs_alias_set (); | |
5693 | ||
5694 | /* AltiVec vectors never go in registers when -mabi=altivec. */ | |
5695 | if (TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (TYPE_MODE (type))) | |
5696 | align = 16; | |
5697 | else | |
5698 | { | |
5699 | lab_false = create_artificial_label (); | |
5700 | lab_over = create_artificial_label (); | |
5701 | ||
5702 | /* Long long and SPE vectors are aligned in the registers. | |
5703 | As are any other 2 gpr item such as complex int due to a | |
5704 | historical mistake. */ | |
5705 | u = reg; | |
5706 | if (n_reg == 2) | |
5707 | { | |
5708 | u = build2 (BIT_AND_EXPR, TREE_TYPE (reg), reg, | |
95674810 | 5709 | size_int (n_reg - 1)); |
cd3ce9b4 JM |
5710 | u = build2 (POSTINCREMENT_EXPR, TREE_TYPE (reg), reg, u); |
5711 | } | |
5712 | ||
95674810 | 5713 | t = fold_convert (TREE_TYPE (reg), size_int (8 - n_reg + 1)); |
cd3ce9b4 JM |
5714 | t = build2 (GE_EXPR, boolean_type_node, u, t); |
5715 | u = build1 (GOTO_EXPR, void_type_node, lab_false); | |
5716 | t = build3 (COND_EXPR, void_type_node, t, u, NULL_TREE); | |
5717 | gimplify_and_add (t, pre_p); | |
5718 | ||
5719 | t = sav; | |
5720 | if (sav_ofs) | |
95674810 | 5721 | t = build2 (PLUS_EXPR, ptr_type_node, sav, size_int (sav_ofs)); |
cd3ce9b4 | 5722 | |
95674810 | 5723 | u = build2 (POSTINCREMENT_EXPR, TREE_TYPE (reg), reg, size_int (n_reg)); |
cd3ce9b4 | 5724 | u = build1 (CONVERT_EXPR, integer_type_node, u); |
95674810 | 5725 | u = build2 (MULT_EXPR, integer_type_node, u, size_int (sav_scale)); |
cd3ce9b4 JM |
5726 | t = build2 (PLUS_EXPR, ptr_type_node, t, u); |
5727 | ||
5728 | t = build2 (MODIFY_EXPR, void_type_node, addr, t); | |
5729 | gimplify_and_add (t, pre_p); | |
5730 | ||
5731 | t = build1 (GOTO_EXPR, void_type_node, lab_over); | |
5732 | gimplify_and_add (t, pre_p); | |
5733 | ||
5734 | t = build1 (LABEL_EXPR, void_type_node, lab_false); | |
5735 | append_to_statement_list (t, pre_p); | |
5736 | ||
5737 | if (n_reg > 2) | |
5738 | { | |
5739 | /* Ensure that we don't find any more args in regs. | |
5740 | Alignment has taken care of the n_reg == 2 case. */ | |
95674810 | 5741 | t = build (MODIFY_EXPR, TREE_TYPE (reg), reg, size_int (8)); |
cd3ce9b4 JM |
5742 | gimplify_and_add (t, pre_p); |
5743 | } | |
5744 | } | |
5745 | ||
5746 | /* ... otherwise out of the overflow area. */ | |
5747 | ||
5748 | /* Care for on-stack alignment if needed. */ | |
5749 | t = ovf; | |
5750 | if (align != 1) | |
5751 | { | |
95674810 | 5752 | t = build2 (PLUS_EXPR, TREE_TYPE (t), t, size_int (align - 1)); |
4a90aeeb | 5753 | t = build2 (BIT_AND_EXPR, TREE_TYPE (t), t, |
7d60be94 | 5754 | build_int_cst (NULL_TREE, -align)); |
cd3ce9b4 JM |
5755 | } |
5756 | gimplify_expr (&t, pre_p, NULL, is_gimple_val, fb_rvalue); | |
5757 | ||
5758 | u = build2 (MODIFY_EXPR, void_type_node, addr, t); | |
5759 | gimplify_and_add (u, pre_p); | |
5760 | ||
95674810 | 5761 | t = build2 (PLUS_EXPR, TREE_TYPE (t), t, size_int (size)); |
cd3ce9b4 JM |
5762 | t = build2 (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t); |
5763 | gimplify_and_add (t, pre_p); | |
5764 | ||
5765 | if (lab_over) | |
5766 | { | |
5767 | t = build1 (LABEL_EXPR, void_type_node, lab_over); | |
5768 | append_to_statement_list (t, pre_p); | |
5769 | } | |
5770 | ||
08b0dc1b | 5771 | addr = fold_convert (ptrtype, addr); |
872a65b5 | 5772 | return build_va_arg_indirect_ref (addr); |
cd3ce9b4 JM |
5773 | } |
5774 | ||
0ac081f6 AH |
5775 | /* Builtins. */ |
5776 | ||
6e34d3a3 JM |
5777 | #define def_builtin(MASK, NAME, TYPE, CODE) \ |
5778 | do { \ | |
5779 | if ((MASK) & target_flags) \ | |
5780 | lang_hooks.builtin_function ((NAME), (TYPE), (CODE), BUILT_IN_MD, \ | |
5781 | NULL, NULL_TREE); \ | |
0ac081f6 AH |
5782 | } while (0) |
5783 | ||
24408032 AH |
5784 | /* Simple ternary operations: VECd = foo (VECa, VECb, VECc). */ |
5785 | ||
2212663f | 5786 | static const struct builtin_description bdesc_3arg[] = |
24408032 AH |
5787 | { |
5788 | { MASK_ALTIVEC, CODE_FOR_altivec_vmaddfp, "__builtin_altivec_vmaddfp", ALTIVEC_BUILTIN_VMADDFP }, | |
5789 | { MASK_ALTIVEC, CODE_FOR_altivec_vmhaddshs, "__builtin_altivec_vmhaddshs", ALTIVEC_BUILTIN_VMHADDSHS }, | |
5790 | { MASK_ALTIVEC, CODE_FOR_altivec_vmhraddshs, "__builtin_altivec_vmhraddshs", ALTIVEC_BUILTIN_VMHRADDSHS }, | |
5791 | { MASK_ALTIVEC, CODE_FOR_altivec_vmladduhm, "__builtin_altivec_vmladduhm", ALTIVEC_BUILTIN_VMLADDUHM}, | |
5792 | { MASK_ALTIVEC, CODE_FOR_altivec_vmsumubm, "__builtin_altivec_vmsumubm", ALTIVEC_BUILTIN_VMSUMUBM }, | |
5793 | { MASK_ALTIVEC, CODE_FOR_altivec_vmsummbm, "__builtin_altivec_vmsummbm", ALTIVEC_BUILTIN_VMSUMMBM }, | |
5794 | { MASK_ALTIVEC, CODE_FOR_altivec_vmsumuhm, "__builtin_altivec_vmsumuhm", ALTIVEC_BUILTIN_VMSUMUHM }, | |
5795 | { MASK_ALTIVEC, CODE_FOR_altivec_vmsumshm, "__builtin_altivec_vmsumshm", ALTIVEC_BUILTIN_VMSUMSHM }, | |
5796 | { MASK_ALTIVEC, CODE_FOR_altivec_vmsumuhs, "__builtin_altivec_vmsumuhs", ALTIVEC_BUILTIN_VMSUMUHS }, | |
5797 | { MASK_ALTIVEC, CODE_FOR_altivec_vmsumshs, "__builtin_altivec_vmsumshs", ALTIVEC_BUILTIN_VMSUMSHS }, | |
f676971a | 5798 | { MASK_ALTIVEC, CODE_FOR_altivec_vnmsubfp, "__builtin_altivec_vnmsubfp", ALTIVEC_BUILTIN_VNMSUBFP }, |
24408032 AH |
5799 | { MASK_ALTIVEC, CODE_FOR_altivec_vperm_4sf, "__builtin_altivec_vperm_4sf", ALTIVEC_BUILTIN_VPERM_4SF }, |
5800 | { MASK_ALTIVEC, CODE_FOR_altivec_vperm_4si, "__builtin_altivec_vperm_4si", ALTIVEC_BUILTIN_VPERM_4SI }, | |
5801 | { MASK_ALTIVEC, CODE_FOR_altivec_vperm_8hi, "__builtin_altivec_vperm_8hi", ALTIVEC_BUILTIN_VPERM_8HI }, | |
5802 | { MASK_ALTIVEC, CODE_FOR_altivec_vperm_16qi, "__builtin_altivec_vperm_16qi", ALTIVEC_BUILTIN_VPERM_16QI }, | |
5803 | { MASK_ALTIVEC, CODE_FOR_altivec_vsel_4sf, "__builtin_altivec_vsel_4sf", ALTIVEC_BUILTIN_VSEL_4SF }, | |
5804 | { MASK_ALTIVEC, CODE_FOR_altivec_vsel_4si, "__builtin_altivec_vsel_4si", ALTIVEC_BUILTIN_VSEL_4SI }, | |
5805 | { MASK_ALTIVEC, CODE_FOR_altivec_vsel_8hi, "__builtin_altivec_vsel_8hi", ALTIVEC_BUILTIN_VSEL_8HI }, | |
5806 | { MASK_ALTIVEC, CODE_FOR_altivec_vsel_16qi, "__builtin_altivec_vsel_16qi", ALTIVEC_BUILTIN_VSEL_16QI }, | |
5807 | { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_16qi, "__builtin_altivec_vsldoi_16qi", ALTIVEC_BUILTIN_VSLDOI_16QI }, | |
5808 | { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_8hi, "__builtin_altivec_vsldoi_8hi", ALTIVEC_BUILTIN_VSLDOI_8HI }, | |
5809 | { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_4si, "__builtin_altivec_vsldoi_4si", ALTIVEC_BUILTIN_VSLDOI_4SI }, | |
5810 | { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_4sf, "__builtin_altivec_vsldoi_4sf", ALTIVEC_BUILTIN_VSLDOI_4SF }, | |
5811 | }; | |
2212663f | 5812 | |
95385cbb AH |
5813 | /* DST operations: void foo (void *, const int, const char). */ |
5814 | ||
5815 | static const struct builtin_description bdesc_dst[] = | |
5816 | { | |
5817 | { MASK_ALTIVEC, CODE_FOR_altivec_dst, "__builtin_altivec_dst", ALTIVEC_BUILTIN_DST }, | |
5818 | { MASK_ALTIVEC, CODE_FOR_altivec_dstt, "__builtin_altivec_dstt", ALTIVEC_BUILTIN_DSTT }, | |
5819 | { MASK_ALTIVEC, CODE_FOR_altivec_dstst, "__builtin_altivec_dstst", ALTIVEC_BUILTIN_DSTST }, | |
5820 | { MASK_ALTIVEC, CODE_FOR_altivec_dststt, "__builtin_altivec_dststt", ALTIVEC_BUILTIN_DSTSTT } | |
5821 | }; | |
5822 | ||
2212663f | 5823 | /* Simple binary operations: VECc = foo (VECa, VECb). */ |
24408032 | 5824 | |
a3170dc6 | 5825 | static struct builtin_description bdesc_2arg[] = |
0ac081f6 | 5826 | { |
f18c054f DB |
5827 | { MASK_ALTIVEC, CODE_FOR_addv16qi3, "__builtin_altivec_vaddubm", ALTIVEC_BUILTIN_VADDUBM }, |
5828 | { MASK_ALTIVEC, CODE_FOR_addv8hi3, "__builtin_altivec_vadduhm", ALTIVEC_BUILTIN_VADDUHM }, | |
5829 | { MASK_ALTIVEC, CODE_FOR_addv4si3, "__builtin_altivec_vadduwm", ALTIVEC_BUILTIN_VADDUWM }, | |
5830 | { MASK_ALTIVEC, CODE_FOR_addv4sf3, "__builtin_altivec_vaddfp", ALTIVEC_BUILTIN_VADDFP }, | |
0ac081f6 AH |
5831 | { MASK_ALTIVEC, CODE_FOR_altivec_vaddcuw, "__builtin_altivec_vaddcuw", ALTIVEC_BUILTIN_VADDCUW }, |
5832 | { MASK_ALTIVEC, CODE_FOR_altivec_vaddubs, "__builtin_altivec_vaddubs", ALTIVEC_BUILTIN_VADDUBS }, | |
5833 | { MASK_ALTIVEC, CODE_FOR_altivec_vaddsbs, "__builtin_altivec_vaddsbs", ALTIVEC_BUILTIN_VADDSBS }, | |
5834 | { MASK_ALTIVEC, CODE_FOR_altivec_vadduhs, "__builtin_altivec_vadduhs", ALTIVEC_BUILTIN_VADDUHS }, | |
5835 | { MASK_ALTIVEC, CODE_FOR_altivec_vaddshs, "__builtin_altivec_vaddshs", ALTIVEC_BUILTIN_VADDSHS }, | |
5836 | { MASK_ALTIVEC, CODE_FOR_altivec_vadduws, "__builtin_altivec_vadduws", ALTIVEC_BUILTIN_VADDUWS }, | |
5837 | { MASK_ALTIVEC, CODE_FOR_altivec_vaddsws, "__builtin_altivec_vaddsws", ALTIVEC_BUILTIN_VADDSWS }, | |
f18c054f | 5838 | { MASK_ALTIVEC, CODE_FOR_andv4si3, "__builtin_altivec_vand", ALTIVEC_BUILTIN_VAND }, |
0ac081f6 AH |
5839 | { MASK_ALTIVEC, CODE_FOR_altivec_vandc, "__builtin_altivec_vandc", ALTIVEC_BUILTIN_VANDC }, |
5840 | { MASK_ALTIVEC, CODE_FOR_altivec_vavgub, "__builtin_altivec_vavgub", ALTIVEC_BUILTIN_VAVGUB }, | |
5841 | { MASK_ALTIVEC, CODE_FOR_altivec_vavgsb, "__builtin_altivec_vavgsb", ALTIVEC_BUILTIN_VAVGSB }, | |
5842 | { MASK_ALTIVEC, CODE_FOR_altivec_vavguh, "__builtin_altivec_vavguh", ALTIVEC_BUILTIN_VAVGUH }, | |
5843 | { MASK_ALTIVEC, CODE_FOR_altivec_vavgsh, "__builtin_altivec_vavgsh", ALTIVEC_BUILTIN_VAVGSH }, | |
5844 | { MASK_ALTIVEC, CODE_FOR_altivec_vavguw, "__builtin_altivec_vavguw", ALTIVEC_BUILTIN_VAVGUW }, | |
5845 | { MASK_ALTIVEC, CODE_FOR_altivec_vavgsw, "__builtin_altivec_vavgsw", ALTIVEC_BUILTIN_VAVGSW }, | |
617e0e1d DB |
5846 | { MASK_ALTIVEC, CODE_FOR_altivec_vcfux, "__builtin_altivec_vcfux", ALTIVEC_BUILTIN_VCFUX }, |
5847 | { MASK_ALTIVEC, CODE_FOR_altivec_vcfsx, "__builtin_altivec_vcfsx", ALTIVEC_BUILTIN_VCFSX }, | |
0ac081f6 AH |
5848 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpbfp, "__builtin_altivec_vcmpbfp", ALTIVEC_BUILTIN_VCMPBFP }, |
5849 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequb, "__builtin_altivec_vcmpequb", ALTIVEC_BUILTIN_VCMPEQUB }, | |
5850 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequh, "__builtin_altivec_vcmpequh", ALTIVEC_BUILTIN_VCMPEQUH }, | |
5851 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequw, "__builtin_altivec_vcmpequw", ALTIVEC_BUILTIN_VCMPEQUW }, | |
5852 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpeqfp, "__builtin_altivec_vcmpeqfp", ALTIVEC_BUILTIN_VCMPEQFP }, | |
5853 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgefp, "__builtin_altivec_vcmpgefp", ALTIVEC_BUILTIN_VCMPGEFP }, | |
5854 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtub, "__builtin_altivec_vcmpgtub", ALTIVEC_BUILTIN_VCMPGTUB }, | |
5855 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsb, "__builtin_altivec_vcmpgtsb", ALTIVEC_BUILTIN_VCMPGTSB }, | |
5856 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtuh, "__builtin_altivec_vcmpgtuh", ALTIVEC_BUILTIN_VCMPGTUH }, | |
5857 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsh, "__builtin_altivec_vcmpgtsh", ALTIVEC_BUILTIN_VCMPGTSH }, | |
5858 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtuw, "__builtin_altivec_vcmpgtuw", ALTIVEC_BUILTIN_VCMPGTUW }, | |
5859 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsw, "__builtin_altivec_vcmpgtsw", ALTIVEC_BUILTIN_VCMPGTSW }, | |
5860 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtfp, "__builtin_altivec_vcmpgtfp", ALTIVEC_BUILTIN_VCMPGTFP }, | |
617e0e1d DB |
5861 | { MASK_ALTIVEC, CODE_FOR_altivec_vctsxs, "__builtin_altivec_vctsxs", ALTIVEC_BUILTIN_VCTSXS }, |
5862 | { MASK_ALTIVEC, CODE_FOR_altivec_vctuxs, "__builtin_altivec_vctuxs", ALTIVEC_BUILTIN_VCTUXS }, | |
f18c054f DB |
5863 | { MASK_ALTIVEC, CODE_FOR_umaxv16qi3, "__builtin_altivec_vmaxub", ALTIVEC_BUILTIN_VMAXUB }, |
5864 | { MASK_ALTIVEC, CODE_FOR_smaxv16qi3, "__builtin_altivec_vmaxsb", ALTIVEC_BUILTIN_VMAXSB }, | |
df966bff AH |
5865 | { MASK_ALTIVEC, CODE_FOR_umaxv8hi3, "__builtin_altivec_vmaxuh", ALTIVEC_BUILTIN_VMAXUH }, |
5866 | { MASK_ALTIVEC, CODE_FOR_smaxv8hi3, "__builtin_altivec_vmaxsh", ALTIVEC_BUILTIN_VMAXSH }, | |
5867 | { MASK_ALTIVEC, CODE_FOR_umaxv4si3, "__builtin_altivec_vmaxuw", ALTIVEC_BUILTIN_VMAXUW }, | |
5868 | { MASK_ALTIVEC, CODE_FOR_smaxv4si3, "__builtin_altivec_vmaxsw", ALTIVEC_BUILTIN_VMAXSW }, | |
5869 | { MASK_ALTIVEC, CODE_FOR_smaxv4sf3, "__builtin_altivec_vmaxfp", ALTIVEC_BUILTIN_VMAXFP }, | |
0ac081f6 AH |
5870 | { MASK_ALTIVEC, CODE_FOR_altivec_vmrghb, "__builtin_altivec_vmrghb", ALTIVEC_BUILTIN_VMRGHB }, |
5871 | { MASK_ALTIVEC, CODE_FOR_altivec_vmrghh, "__builtin_altivec_vmrghh", ALTIVEC_BUILTIN_VMRGHH }, | |
5872 | { MASK_ALTIVEC, CODE_FOR_altivec_vmrghw, "__builtin_altivec_vmrghw", ALTIVEC_BUILTIN_VMRGHW }, | |
5873 | { MASK_ALTIVEC, CODE_FOR_altivec_vmrglb, "__builtin_altivec_vmrglb", ALTIVEC_BUILTIN_VMRGLB }, | |
5874 | { MASK_ALTIVEC, CODE_FOR_altivec_vmrglh, "__builtin_altivec_vmrglh", ALTIVEC_BUILTIN_VMRGLH }, | |
5875 | { MASK_ALTIVEC, CODE_FOR_altivec_vmrglw, "__builtin_altivec_vmrglw", ALTIVEC_BUILTIN_VMRGLW }, | |
f18c054f DB |
5876 | { MASK_ALTIVEC, CODE_FOR_uminv16qi3, "__builtin_altivec_vminub", ALTIVEC_BUILTIN_VMINUB }, |
5877 | { MASK_ALTIVEC, CODE_FOR_sminv16qi3, "__builtin_altivec_vminsb", ALTIVEC_BUILTIN_VMINSB }, | |
5878 | { MASK_ALTIVEC, CODE_FOR_uminv8hi3, "__builtin_altivec_vminuh", ALTIVEC_BUILTIN_VMINUH }, | |
5879 | { MASK_ALTIVEC, CODE_FOR_sminv8hi3, "__builtin_altivec_vminsh", ALTIVEC_BUILTIN_VMINSH }, | |
5880 | { MASK_ALTIVEC, CODE_FOR_uminv4si3, "__builtin_altivec_vminuw", ALTIVEC_BUILTIN_VMINUW }, | |
5881 | { MASK_ALTIVEC, CODE_FOR_sminv4si3, "__builtin_altivec_vminsw", ALTIVEC_BUILTIN_VMINSW }, | |
5882 | { MASK_ALTIVEC, CODE_FOR_sminv4sf3, "__builtin_altivec_vminfp", ALTIVEC_BUILTIN_VMINFP }, | |
0ac081f6 AH |
5883 | { MASK_ALTIVEC, CODE_FOR_altivec_vmuleub, "__builtin_altivec_vmuleub", ALTIVEC_BUILTIN_VMULEUB }, |
5884 | { MASK_ALTIVEC, CODE_FOR_altivec_vmulesb, "__builtin_altivec_vmulesb", ALTIVEC_BUILTIN_VMULESB }, | |
5885 | { MASK_ALTIVEC, CODE_FOR_altivec_vmuleuh, "__builtin_altivec_vmuleuh", ALTIVEC_BUILTIN_VMULEUH }, | |
5886 | { MASK_ALTIVEC, CODE_FOR_altivec_vmulesh, "__builtin_altivec_vmulesh", ALTIVEC_BUILTIN_VMULESH }, | |
5887 | { MASK_ALTIVEC, CODE_FOR_altivec_vmuloub, "__builtin_altivec_vmuloub", ALTIVEC_BUILTIN_VMULOUB }, | |
5888 | { MASK_ALTIVEC, CODE_FOR_altivec_vmulosb, "__builtin_altivec_vmulosb", ALTIVEC_BUILTIN_VMULOSB }, | |
5889 | { MASK_ALTIVEC, CODE_FOR_altivec_vmulouh, "__builtin_altivec_vmulouh", ALTIVEC_BUILTIN_VMULOUH }, | |
5890 | { MASK_ALTIVEC, CODE_FOR_altivec_vmulosh, "__builtin_altivec_vmulosh", ALTIVEC_BUILTIN_VMULOSH }, | |
5891 | { MASK_ALTIVEC, CODE_FOR_altivec_vnor, "__builtin_altivec_vnor", ALTIVEC_BUILTIN_VNOR }, | |
f18c054f | 5892 | { MASK_ALTIVEC, CODE_FOR_iorv4si3, "__builtin_altivec_vor", ALTIVEC_BUILTIN_VOR }, |
0ac081f6 AH |
5893 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhum, "__builtin_altivec_vpkuhum", ALTIVEC_BUILTIN_VPKUHUM }, |
5894 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwum, "__builtin_altivec_vpkuwum", ALTIVEC_BUILTIN_VPKUWUM }, | |
5895 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkpx, "__builtin_altivec_vpkpx", ALTIVEC_BUILTIN_VPKPX }, | |
5896 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhss, "__builtin_altivec_vpkuhss", ALTIVEC_BUILTIN_VPKUHSS }, | |
5897 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkshss, "__builtin_altivec_vpkshss", ALTIVEC_BUILTIN_VPKSHSS }, | |
5898 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwss, "__builtin_altivec_vpkuwss", ALTIVEC_BUILTIN_VPKUWSS }, | |
5899 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkswss, "__builtin_altivec_vpkswss", ALTIVEC_BUILTIN_VPKSWSS }, | |
5900 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhus, "__builtin_altivec_vpkuhus", ALTIVEC_BUILTIN_VPKUHUS }, | |
5901 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkshus, "__builtin_altivec_vpkshus", ALTIVEC_BUILTIN_VPKSHUS }, | |
5902 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwus, "__builtin_altivec_vpkuwus", ALTIVEC_BUILTIN_VPKUWUS }, | |
5903 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkswus, "__builtin_altivec_vpkswus", ALTIVEC_BUILTIN_VPKSWUS }, | |
5904 | { MASK_ALTIVEC, CODE_FOR_altivec_vrlb, "__builtin_altivec_vrlb", ALTIVEC_BUILTIN_VRLB }, | |
5905 | { MASK_ALTIVEC, CODE_FOR_altivec_vrlh, "__builtin_altivec_vrlh", ALTIVEC_BUILTIN_VRLH }, | |
5906 | { MASK_ALTIVEC, CODE_FOR_altivec_vrlw, "__builtin_altivec_vrlw", ALTIVEC_BUILTIN_VRLW }, | |
5907 | { MASK_ALTIVEC, CODE_FOR_altivec_vslb, "__builtin_altivec_vslb", ALTIVEC_BUILTIN_VSLB }, | |
5908 | { MASK_ALTIVEC, CODE_FOR_altivec_vslh, "__builtin_altivec_vslh", ALTIVEC_BUILTIN_VSLH }, | |
5909 | { MASK_ALTIVEC, CODE_FOR_altivec_vslw, "__builtin_altivec_vslw", ALTIVEC_BUILTIN_VSLW }, | |
5910 | { MASK_ALTIVEC, CODE_FOR_altivec_vsl, "__builtin_altivec_vsl", ALTIVEC_BUILTIN_VSL }, | |
5911 | { MASK_ALTIVEC, CODE_FOR_altivec_vslo, "__builtin_altivec_vslo", ALTIVEC_BUILTIN_VSLO }, | |
2212663f DB |
5912 | { MASK_ALTIVEC, CODE_FOR_altivec_vspltb, "__builtin_altivec_vspltb", ALTIVEC_BUILTIN_VSPLTB }, |
5913 | { MASK_ALTIVEC, CODE_FOR_altivec_vsplth, "__builtin_altivec_vsplth", ALTIVEC_BUILTIN_VSPLTH }, | |
5914 | { MASK_ALTIVEC, CODE_FOR_altivec_vspltw, "__builtin_altivec_vspltw", ALTIVEC_BUILTIN_VSPLTW }, | |
0ac081f6 | 5915 | { MASK_ALTIVEC, CODE_FOR_altivec_vsrb, "__builtin_altivec_vsrb", ALTIVEC_BUILTIN_VSRB }, |
f18c054f DB |
5916 | { MASK_ALTIVEC, CODE_FOR_altivec_vsrh, "__builtin_altivec_vsrh", ALTIVEC_BUILTIN_VSRH }, |
5917 | { MASK_ALTIVEC, CODE_FOR_altivec_vsrw, "__builtin_altivec_vsrw", ALTIVEC_BUILTIN_VSRW }, | |
0ac081f6 AH |
5918 | { MASK_ALTIVEC, CODE_FOR_altivec_vsrab, "__builtin_altivec_vsrab", ALTIVEC_BUILTIN_VSRAB }, |
5919 | { MASK_ALTIVEC, CODE_FOR_altivec_vsrah, "__builtin_altivec_vsrah", ALTIVEC_BUILTIN_VSRAH }, | |
5920 | { MASK_ALTIVEC, CODE_FOR_altivec_vsraw, "__builtin_altivec_vsraw", ALTIVEC_BUILTIN_VSRAW }, | |
5921 | { MASK_ALTIVEC, CODE_FOR_altivec_vsr, "__builtin_altivec_vsr", ALTIVEC_BUILTIN_VSR }, | |
5922 | { MASK_ALTIVEC, CODE_FOR_altivec_vsro, "__builtin_altivec_vsro", ALTIVEC_BUILTIN_VSRO }, | |
f18c054f DB |
5923 | { MASK_ALTIVEC, CODE_FOR_subv16qi3, "__builtin_altivec_vsububm", ALTIVEC_BUILTIN_VSUBUBM }, |
5924 | { MASK_ALTIVEC, CODE_FOR_subv8hi3, "__builtin_altivec_vsubuhm", ALTIVEC_BUILTIN_VSUBUHM }, | |
5925 | { MASK_ALTIVEC, CODE_FOR_subv4si3, "__builtin_altivec_vsubuwm", ALTIVEC_BUILTIN_VSUBUWM }, | |
5926 | { MASK_ALTIVEC, CODE_FOR_subv4sf3, "__builtin_altivec_vsubfp", ALTIVEC_BUILTIN_VSUBFP }, | |
0ac081f6 AH |
5927 | { MASK_ALTIVEC, CODE_FOR_altivec_vsubcuw, "__builtin_altivec_vsubcuw", ALTIVEC_BUILTIN_VSUBCUW }, |
5928 | { MASK_ALTIVEC, CODE_FOR_altivec_vsububs, "__builtin_altivec_vsububs", ALTIVEC_BUILTIN_VSUBUBS }, | |
5929 | { MASK_ALTIVEC, CODE_FOR_altivec_vsubsbs, "__builtin_altivec_vsubsbs", ALTIVEC_BUILTIN_VSUBSBS }, | |
5930 | { MASK_ALTIVEC, CODE_FOR_altivec_vsubuhs, "__builtin_altivec_vsubuhs", ALTIVEC_BUILTIN_VSUBUHS }, | |
5931 | { MASK_ALTIVEC, CODE_FOR_altivec_vsubshs, "__builtin_altivec_vsubshs", ALTIVEC_BUILTIN_VSUBSHS }, | |
5932 | { MASK_ALTIVEC, CODE_FOR_altivec_vsubuws, "__builtin_altivec_vsubuws", ALTIVEC_BUILTIN_VSUBUWS }, | |
5933 | { MASK_ALTIVEC, CODE_FOR_altivec_vsubsws, "__builtin_altivec_vsubsws", ALTIVEC_BUILTIN_VSUBSWS }, | |
5934 | { MASK_ALTIVEC, CODE_FOR_altivec_vsum4ubs, "__builtin_altivec_vsum4ubs", ALTIVEC_BUILTIN_VSUM4UBS }, | |
5935 | { MASK_ALTIVEC, CODE_FOR_altivec_vsum4sbs, "__builtin_altivec_vsum4sbs", ALTIVEC_BUILTIN_VSUM4SBS }, | |
5936 | { MASK_ALTIVEC, CODE_FOR_altivec_vsum4shs, "__builtin_altivec_vsum4shs", ALTIVEC_BUILTIN_VSUM4SHS }, | |
5937 | { MASK_ALTIVEC, CODE_FOR_altivec_vsum2sws, "__builtin_altivec_vsum2sws", ALTIVEC_BUILTIN_VSUM2SWS }, | |
5938 | { MASK_ALTIVEC, CODE_FOR_altivec_vsumsws, "__builtin_altivec_vsumsws", ALTIVEC_BUILTIN_VSUMSWS }, | |
f18c054f | 5939 | { MASK_ALTIVEC, CODE_FOR_xorv4si3, "__builtin_altivec_vxor", ALTIVEC_BUILTIN_VXOR }, |
a3170dc6 AH |
5940 | |
5941 | /* Place holder, leave as first spe builtin. */ | |
5942 | { 0, CODE_FOR_spe_evaddw, "__builtin_spe_evaddw", SPE_BUILTIN_EVADDW }, | |
5943 | { 0, CODE_FOR_spe_evand, "__builtin_spe_evand", SPE_BUILTIN_EVAND }, | |
5944 | { 0, CODE_FOR_spe_evandc, "__builtin_spe_evandc", SPE_BUILTIN_EVANDC }, | |
5945 | { 0, CODE_FOR_spe_evdivws, "__builtin_spe_evdivws", SPE_BUILTIN_EVDIVWS }, | |
5946 | { 0, CODE_FOR_spe_evdivwu, "__builtin_spe_evdivwu", SPE_BUILTIN_EVDIVWU }, | |
5947 | { 0, CODE_FOR_spe_eveqv, "__builtin_spe_eveqv", SPE_BUILTIN_EVEQV }, | |
5948 | { 0, CODE_FOR_spe_evfsadd, "__builtin_spe_evfsadd", SPE_BUILTIN_EVFSADD }, | |
5949 | { 0, CODE_FOR_spe_evfsdiv, "__builtin_spe_evfsdiv", SPE_BUILTIN_EVFSDIV }, | |
5950 | { 0, CODE_FOR_spe_evfsmul, "__builtin_spe_evfsmul", SPE_BUILTIN_EVFSMUL }, | |
5951 | { 0, CODE_FOR_spe_evfssub, "__builtin_spe_evfssub", SPE_BUILTIN_EVFSSUB }, | |
5952 | { 0, CODE_FOR_spe_evmergehi, "__builtin_spe_evmergehi", SPE_BUILTIN_EVMERGEHI }, | |
5953 | { 0, CODE_FOR_spe_evmergehilo, "__builtin_spe_evmergehilo", SPE_BUILTIN_EVMERGEHILO }, | |
5954 | { 0, CODE_FOR_spe_evmergelo, "__builtin_spe_evmergelo", SPE_BUILTIN_EVMERGELO }, | |
5955 | { 0, CODE_FOR_spe_evmergelohi, "__builtin_spe_evmergelohi", SPE_BUILTIN_EVMERGELOHI }, | |
5956 | { 0, CODE_FOR_spe_evmhegsmfaa, "__builtin_spe_evmhegsmfaa", SPE_BUILTIN_EVMHEGSMFAA }, | |
5957 | { 0, CODE_FOR_spe_evmhegsmfan, "__builtin_spe_evmhegsmfan", SPE_BUILTIN_EVMHEGSMFAN }, | |
5958 | { 0, CODE_FOR_spe_evmhegsmiaa, "__builtin_spe_evmhegsmiaa", SPE_BUILTIN_EVMHEGSMIAA }, | |
5959 | { 0, CODE_FOR_spe_evmhegsmian, "__builtin_spe_evmhegsmian", SPE_BUILTIN_EVMHEGSMIAN }, | |
5960 | { 0, CODE_FOR_spe_evmhegumiaa, "__builtin_spe_evmhegumiaa", SPE_BUILTIN_EVMHEGUMIAA }, | |
5961 | { 0, CODE_FOR_spe_evmhegumian, "__builtin_spe_evmhegumian", SPE_BUILTIN_EVMHEGUMIAN }, | |
5962 | { 0, CODE_FOR_spe_evmhesmf, "__builtin_spe_evmhesmf", SPE_BUILTIN_EVMHESMF }, | |
5963 | { 0, CODE_FOR_spe_evmhesmfa, "__builtin_spe_evmhesmfa", SPE_BUILTIN_EVMHESMFA }, | |
5964 | { 0, CODE_FOR_spe_evmhesmfaaw, "__builtin_spe_evmhesmfaaw", SPE_BUILTIN_EVMHESMFAAW }, | |
5965 | { 0, CODE_FOR_spe_evmhesmfanw, "__builtin_spe_evmhesmfanw", SPE_BUILTIN_EVMHESMFANW }, | |
5966 | { 0, CODE_FOR_spe_evmhesmi, "__builtin_spe_evmhesmi", SPE_BUILTIN_EVMHESMI }, | |
5967 | { 0, CODE_FOR_spe_evmhesmia, "__builtin_spe_evmhesmia", SPE_BUILTIN_EVMHESMIA }, | |
5968 | { 0, CODE_FOR_spe_evmhesmiaaw, "__builtin_spe_evmhesmiaaw", SPE_BUILTIN_EVMHESMIAAW }, | |
5969 | { 0, CODE_FOR_spe_evmhesmianw, "__builtin_spe_evmhesmianw", SPE_BUILTIN_EVMHESMIANW }, | |
5970 | { 0, CODE_FOR_spe_evmhessf, "__builtin_spe_evmhessf", SPE_BUILTIN_EVMHESSF }, | |
5971 | { 0, CODE_FOR_spe_evmhessfa, "__builtin_spe_evmhessfa", SPE_BUILTIN_EVMHESSFA }, | |
5972 | { 0, CODE_FOR_spe_evmhessfaaw, "__builtin_spe_evmhessfaaw", SPE_BUILTIN_EVMHESSFAAW }, | |
5973 | { 0, CODE_FOR_spe_evmhessfanw, "__builtin_spe_evmhessfanw", SPE_BUILTIN_EVMHESSFANW }, | |
5974 | { 0, CODE_FOR_spe_evmhessiaaw, "__builtin_spe_evmhessiaaw", SPE_BUILTIN_EVMHESSIAAW }, | |
5975 | { 0, CODE_FOR_spe_evmhessianw, "__builtin_spe_evmhessianw", SPE_BUILTIN_EVMHESSIANW }, | |
5976 | { 0, CODE_FOR_spe_evmheumi, "__builtin_spe_evmheumi", SPE_BUILTIN_EVMHEUMI }, | |
5977 | { 0, CODE_FOR_spe_evmheumia, "__builtin_spe_evmheumia", SPE_BUILTIN_EVMHEUMIA }, | |
5978 | { 0, CODE_FOR_spe_evmheumiaaw, "__builtin_spe_evmheumiaaw", SPE_BUILTIN_EVMHEUMIAAW }, | |
5979 | { 0, CODE_FOR_spe_evmheumianw, "__builtin_spe_evmheumianw", SPE_BUILTIN_EVMHEUMIANW }, | |
5980 | { 0, CODE_FOR_spe_evmheusiaaw, "__builtin_spe_evmheusiaaw", SPE_BUILTIN_EVMHEUSIAAW }, | |
5981 | { 0, CODE_FOR_spe_evmheusianw, "__builtin_spe_evmheusianw", SPE_BUILTIN_EVMHEUSIANW }, | |
5982 | { 0, CODE_FOR_spe_evmhogsmfaa, "__builtin_spe_evmhogsmfaa", SPE_BUILTIN_EVMHOGSMFAA }, | |
5983 | { 0, CODE_FOR_spe_evmhogsmfan, "__builtin_spe_evmhogsmfan", SPE_BUILTIN_EVMHOGSMFAN }, | |
5984 | { 0, CODE_FOR_spe_evmhogsmiaa, "__builtin_spe_evmhogsmiaa", SPE_BUILTIN_EVMHOGSMIAA }, | |
5985 | { 0, CODE_FOR_spe_evmhogsmian, "__builtin_spe_evmhogsmian", SPE_BUILTIN_EVMHOGSMIAN }, | |
5986 | { 0, CODE_FOR_spe_evmhogumiaa, "__builtin_spe_evmhogumiaa", SPE_BUILTIN_EVMHOGUMIAA }, | |
5987 | { 0, CODE_FOR_spe_evmhogumian, "__builtin_spe_evmhogumian", SPE_BUILTIN_EVMHOGUMIAN }, | |
5988 | { 0, CODE_FOR_spe_evmhosmf, "__builtin_spe_evmhosmf", SPE_BUILTIN_EVMHOSMF }, | |
5989 | { 0, CODE_FOR_spe_evmhosmfa, "__builtin_spe_evmhosmfa", SPE_BUILTIN_EVMHOSMFA }, | |
5990 | { 0, CODE_FOR_spe_evmhosmfaaw, "__builtin_spe_evmhosmfaaw", SPE_BUILTIN_EVMHOSMFAAW }, | |
5991 | { 0, CODE_FOR_spe_evmhosmfanw, "__builtin_spe_evmhosmfanw", SPE_BUILTIN_EVMHOSMFANW }, | |
5992 | { 0, CODE_FOR_spe_evmhosmi, "__builtin_spe_evmhosmi", SPE_BUILTIN_EVMHOSMI }, | |
5993 | { 0, CODE_FOR_spe_evmhosmia, "__builtin_spe_evmhosmia", SPE_BUILTIN_EVMHOSMIA }, | |
5994 | { 0, CODE_FOR_spe_evmhosmiaaw, "__builtin_spe_evmhosmiaaw", SPE_BUILTIN_EVMHOSMIAAW }, | |
5995 | { 0, CODE_FOR_spe_evmhosmianw, "__builtin_spe_evmhosmianw", SPE_BUILTIN_EVMHOSMIANW }, | |
5996 | { 0, CODE_FOR_spe_evmhossf, "__builtin_spe_evmhossf", SPE_BUILTIN_EVMHOSSF }, | |
5997 | { 0, CODE_FOR_spe_evmhossfa, "__builtin_spe_evmhossfa", SPE_BUILTIN_EVMHOSSFA }, | |
5998 | { 0, CODE_FOR_spe_evmhossfaaw, "__builtin_spe_evmhossfaaw", SPE_BUILTIN_EVMHOSSFAAW }, | |
5999 | { 0, CODE_FOR_spe_evmhossfanw, "__builtin_spe_evmhossfanw", SPE_BUILTIN_EVMHOSSFANW }, | |
6000 | { 0, CODE_FOR_spe_evmhossiaaw, "__builtin_spe_evmhossiaaw", SPE_BUILTIN_EVMHOSSIAAW }, | |
6001 | { 0, CODE_FOR_spe_evmhossianw, "__builtin_spe_evmhossianw", SPE_BUILTIN_EVMHOSSIANW }, | |
6002 | { 0, CODE_FOR_spe_evmhoumi, "__builtin_spe_evmhoumi", SPE_BUILTIN_EVMHOUMI }, | |
6003 | { 0, CODE_FOR_spe_evmhoumia, "__builtin_spe_evmhoumia", SPE_BUILTIN_EVMHOUMIA }, | |
6004 | { 0, CODE_FOR_spe_evmhoumiaaw, "__builtin_spe_evmhoumiaaw", SPE_BUILTIN_EVMHOUMIAAW }, | |
6005 | { 0, CODE_FOR_spe_evmhoumianw, "__builtin_spe_evmhoumianw", SPE_BUILTIN_EVMHOUMIANW }, | |
6006 | { 0, CODE_FOR_spe_evmhousiaaw, "__builtin_spe_evmhousiaaw", SPE_BUILTIN_EVMHOUSIAAW }, | |
6007 | { 0, CODE_FOR_spe_evmhousianw, "__builtin_spe_evmhousianw", SPE_BUILTIN_EVMHOUSIANW }, | |
6008 | { 0, CODE_FOR_spe_evmwhsmf, "__builtin_spe_evmwhsmf", SPE_BUILTIN_EVMWHSMF }, | |
6009 | { 0, CODE_FOR_spe_evmwhsmfa, "__builtin_spe_evmwhsmfa", SPE_BUILTIN_EVMWHSMFA }, | |
6010 | { 0, CODE_FOR_spe_evmwhsmi, "__builtin_spe_evmwhsmi", SPE_BUILTIN_EVMWHSMI }, | |
6011 | { 0, CODE_FOR_spe_evmwhsmia, "__builtin_spe_evmwhsmia", SPE_BUILTIN_EVMWHSMIA }, | |
6012 | { 0, CODE_FOR_spe_evmwhssf, "__builtin_spe_evmwhssf", SPE_BUILTIN_EVMWHSSF }, | |
6013 | { 0, CODE_FOR_spe_evmwhssfa, "__builtin_spe_evmwhssfa", SPE_BUILTIN_EVMWHSSFA }, | |
6014 | { 0, CODE_FOR_spe_evmwhumi, "__builtin_spe_evmwhumi", SPE_BUILTIN_EVMWHUMI }, | |
6015 | { 0, CODE_FOR_spe_evmwhumia, "__builtin_spe_evmwhumia", SPE_BUILTIN_EVMWHUMIA }, | |
a3170dc6 AH |
6016 | { 0, CODE_FOR_spe_evmwlsmiaaw, "__builtin_spe_evmwlsmiaaw", SPE_BUILTIN_EVMWLSMIAAW }, |
6017 | { 0, CODE_FOR_spe_evmwlsmianw, "__builtin_spe_evmwlsmianw", SPE_BUILTIN_EVMWLSMIANW }, | |
a3170dc6 AH |
6018 | { 0, CODE_FOR_spe_evmwlssiaaw, "__builtin_spe_evmwlssiaaw", SPE_BUILTIN_EVMWLSSIAAW }, |
6019 | { 0, CODE_FOR_spe_evmwlssianw, "__builtin_spe_evmwlssianw", SPE_BUILTIN_EVMWLSSIANW }, | |
6020 | { 0, CODE_FOR_spe_evmwlumi, "__builtin_spe_evmwlumi", SPE_BUILTIN_EVMWLUMI }, | |
6021 | { 0, CODE_FOR_spe_evmwlumia, "__builtin_spe_evmwlumia", SPE_BUILTIN_EVMWLUMIA }, | |
6022 | { 0, CODE_FOR_spe_evmwlumiaaw, "__builtin_spe_evmwlumiaaw", SPE_BUILTIN_EVMWLUMIAAW }, | |
6023 | { 0, CODE_FOR_spe_evmwlumianw, "__builtin_spe_evmwlumianw", SPE_BUILTIN_EVMWLUMIANW }, | |
6024 | { 0, CODE_FOR_spe_evmwlusiaaw, "__builtin_spe_evmwlusiaaw", SPE_BUILTIN_EVMWLUSIAAW }, | |
6025 | { 0, CODE_FOR_spe_evmwlusianw, "__builtin_spe_evmwlusianw", SPE_BUILTIN_EVMWLUSIANW }, | |
6026 | { 0, CODE_FOR_spe_evmwsmf, "__builtin_spe_evmwsmf", SPE_BUILTIN_EVMWSMF }, | |
6027 | { 0, CODE_FOR_spe_evmwsmfa, "__builtin_spe_evmwsmfa", SPE_BUILTIN_EVMWSMFA }, | |
6028 | { 0, CODE_FOR_spe_evmwsmfaa, "__builtin_spe_evmwsmfaa", SPE_BUILTIN_EVMWSMFAA }, | |
6029 | { 0, CODE_FOR_spe_evmwsmfan, "__builtin_spe_evmwsmfan", SPE_BUILTIN_EVMWSMFAN }, | |
6030 | { 0, CODE_FOR_spe_evmwsmi, "__builtin_spe_evmwsmi", SPE_BUILTIN_EVMWSMI }, | |
6031 | { 0, CODE_FOR_spe_evmwsmia, "__builtin_spe_evmwsmia", SPE_BUILTIN_EVMWSMIA }, | |
6032 | { 0, CODE_FOR_spe_evmwsmiaa, "__builtin_spe_evmwsmiaa", SPE_BUILTIN_EVMWSMIAA }, | |
6033 | { 0, CODE_FOR_spe_evmwsmian, "__builtin_spe_evmwsmian", SPE_BUILTIN_EVMWSMIAN }, | |
6034 | { 0, CODE_FOR_spe_evmwssf, "__builtin_spe_evmwssf", SPE_BUILTIN_EVMWSSF }, | |
6035 | { 0, CODE_FOR_spe_evmwssfa, "__builtin_spe_evmwssfa", SPE_BUILTIN_EVMWSSFA }, | |
6036 | { 0, CODE_FOR_spe_evmwssfaa, "__builtin_spe_evmwssfaa", SPE_BUILTIN_EVMWSSFAA }, | |
6037 | { 0, CODE_FOR_spe_evmwssfan, "__builtin_spe_evmwssfan", SPE_BUILTIN_EVMWSSFAN }, | |
6038 | { 0, CODE_FOR_spe_evmwumi, "__builtin_spe_evmwumi", SPE_BUILTIN_EVMWUMI }, | |
6039 | { 0, CODE_FOR_spe_evmwumia, "__builtin_spe_evmwumia", SPE_BUILTIN_EVMWUMIA }, | |
6040 | { 0, CODE_FOR_spe_evmwumiaa, "__builtin_spe_evmwumiaa", SPE_BUILTIN_EVMWUMIAA }, | |
6041 | { 0, CODE_FOR_spe_evmwumian, "__builtin_spe_evmwumian", SPE_BUILTIN_EVMWUMIAN }, | |
6042 | { 0, CODE_FOR_spe_evnand, "__builtin_spe_evnand", SPE_BUILTIN_EVNAND }, | |
6043 | { 0, CODE_FOR_spe_evnor, "__builtin_spe_evnor", SPE_BUILTIN_EVNOR }, | |
6044 | { 0, CODE_FOR_spe_evor, "__builtin_spe_evor", SPE_BUILTIN_EVOR }, | |
6045 | { 0, CODE_FOR_spe_evorc, "__builtin_spe_evorc", SPE_BUILTIN_EVORC }, | |
6046 | { 0, CODE_FOR_spe_evrlw, "__builtin_spe_evrlw", SPE_BUILTIN_EVRLW }, | |
6047 | { 0, CODE_FOR_spe_evslw, "__builtin_spe_evslw", SPE_BUILTIN_EVSLW }, | |
6048 | { 0, CODE_FOR_spe_evsrws, "__builtin_spe_evsrws", SPE_BUILTIN_EVSRWS }, | |
6049 | { 0, CODE_FOR_spe_evsrwu, "__builtin_spe_evsrwu", SPE_BUILTIN_EVSRWU }, | |
6050 | { 0, CODE_FOR_spe_evsubfw, "__builtin_spe_evsubfw", SPE_BUILTIN_EVSUBFW }, | |
6051 | ||
6052 | /* SPE binary operations expecting a 5-bit unsigned literal. */ | |
6053 | { 0, CODE_FOR_spe_evaddiw, "__builtin_spe_evaddiw", SPE_BUILTIN_EVADDIW }, | |
6054 | ||
6055 | { 0, CODE_FOR_spe_evrlwi, "__builtin_spe_evrlwi", SPE_BUILTIN_EVRLWI }, | |
6056 | { 0, CODE_FOR_spe_evslwi, "__builtin_spe_evslwi", SPE_BUILTIN_EVSLWI }, | |
6057 | { 0, CODE_FOR_spe_evsrwis, "__builtin_spe_evsrwis", SPE_BUILTIN_EVSRWIS }, | |
6058 | { 0, CODE_FOR_spe_evsrwiu, "__builtin_spe_evsrwiu", SPE_BUILTIN_EVSRWIU }, | |
6059 | { 0, CODE_FOR_spe_evsubifw, "__builtin_spe_evsubifw", SPE_BUILTIN_EVSUBIFW }, | |
6060 | { 0, CODE_FOR_spe_evmwhssfaa, "__builtin_spe_evmwhssfaa", SPE_BUILTIN_EVMWHSSFAA }, | |
6061 | { 0, CODE_FOR_spe_evmwhssmaa, "__builtin_spe_evmwhssmaa", SPE_BUILTIN_EVMWHSSMAA }, | |
6062 | { 0, CODE_FOR_spe_evmwhsmfaa, "__builtin_spe_evmwhsmfaa", SPE_BUILTIN_EVMWHSMFAA }, | |
6063 | { 0, CODE_FOR_spe_evmwhsmiaa, "__builtin_spe_evmwhsmiaa", SPE_BUILTIN_EVMWHSMIAA }, | |
6064 | { 0, CODE_FOR_spe_evmwhusiaa, "__builtin_spe_evmwhusiaa", SPE_BUILTIN_EVMWHUSIAA }, | |
6065 | { 0, CODE_FOR_spe_evmwhumiaa, "__builtin_spe_evmwhumiaa", SPE_BUILTIN_EVMWHUMIAA }, | |
6066 | { 0, CODE_FOR_spe_evmwhssfan, "__builtin_spe_evmwhssfan", SPE_BUILTIN_EVMWHSSFAN }, | |
6067 | { 0, CODE_FOR_spe_evmwhssian, "__builtin_spe_evmwhssian", SPE_BUILTIN_EVMWHSSIAN }, | |
6068 | { 0, CODE_FOR_spe_evmwhsmfan, "__builtin_spe_evmwhsmfan", SPE_BUILTIN_EVMWHSMFAN }, | |
6069 | { 0, CODE_FOR_spe_evmwhsmian, "__builtin_spe_evmwhsmian", SPE_BUILTIN_EVMWHSMIAN }, | |
6070 | { 0, CODE_FOR_spe_evmwhusian, "__builtin_spe_evmwhusian", SPE_BUILTIN_EVMWHUSIAN }, | |
6071 | { 0, CODE_FOR_spe_evmwhumian, "__builtin_spe_evmwhumian", SPE_BUILTIN_EVMWHUMIAN }, | |
6072 | { 0, CODE_FOR_spe_evmwhgssfaa, "__builtin_spe_evmwhgssfaa", SPE_BUILTIN_EVMWHGSSFAA }, | |
6073 | { 0, CODE_FOR_spe_evmwhgsmfaa, "__builtin_spe_evmwhgsmfaa", SPE_BUILTIN_EVMWHGSMFAA }, | |
6074 | { 0, CODE_FOR_spe_evmwhgsmiaa, "__builtin_spe_evmwhgsmiaa", SPE_BUILTIN_EVMWHGSMIAA }, | |
6075 | { 0, CODE_FOR_spe_evmwhgumiaa, "__builtin_spe_evmwhgumiaa", SPE_BUILTIN_EVMWHGUMIAA }, | |
6076 | { 0, CODE_FOR_spe_evmwhgssfan, "__builtin_spe_evmwhgssfan", SPE_BUILTIN_EVMWHGSSFAN }, | |
6077 | { 0, CODE_FOR_spe_evmwhgsmfan, "__builtin_spe_evmwhgsmfan", SPE_BUILTIN_EVMWHGSMFAN }, | |
6078 | { 0, CODE_FOR_spe_evmwhgsmian, "__builtin_spe_evmwhgsmian", SPE_BUILTIN_EVMWHGSMIAN }, | |
6079 | { 0, CODE_FOR_spe_evmwhgumian, "__builtin_spe_evmwhgumian", SPE_BUILTIN_EVMWHGUMIAN }, | |
6080 | { 0, CODE_FOR_spe_brinc, "__builtin_spe_brinc", SPE_BUILTIN_BRINC }, | |
6081 | ||
6082 | /* Place-holder. Leave as last binary SPE builtin. */ | |
17edbda5 | 6083 | { 0, CODE_FOR_xorv2si3, "__builtin_spe_evxor", SPE_BUILTIN_EVXOR }, |
ae4b4a02 AH |
6084 | }; |
6085 | ||
6086 | /* AltiVec predicates. */ | |
6087 | ||
6088 | struct builtin_description_predicates | |
6089 | { | |
6090 | const unsigned int mask; | |
6091 | const enum insn_code icode; | |
6092 | const char *opcode; | |
6093 | const char *const name; | |
6094 | const enum rs6000_builtins code; | |
6095 | }; | |
6096 | ||
6097 | static const struct builtin_description_predicates bdesc_altivec_preds[] = | |
6098 | { | |
6099 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpbfp.", "__builtin_altivec_vcmpbfp_p", ALTIVEC_BUILTIN_VCMPBFP_P }, | |
6100 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpeqfp.", "__builtin_altivec_vcmpeqfp_p", ALTIVEC_BUILTIN_VCMPEQFP_P }, | |
6101 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpgefp.", "__builtin_altivec_vcmpgefp_p", ALTIVEC_BUILTIN_VCMPGEFP_P }, | |
6102 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpgtfp.", "__builtin_altivec_vcmpgtfp_p", ALTIVEC_BUILTIN_VCMPGTFP_P }, | |
6103 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpequw.", "__builtin_altivec_vcmpequw_p", ALTIVEC_BUILTIN_VCMPEQUW_P }, | |
6104 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpgtsw.", "__builtin_altivec_vcmpgtsw_p", ALTIVEC_BUILTIN_VCMPGTSW_P }, | |
6105 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpgtuw.", "__builtin_altivec_vcmpgtuw_p", ALTIVEC_BUILTIN_VCMPGTUW_P }, | |
6106 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpgtuh.", "__builtin_altivec_vcmpgtuh_p", ALTIVEC_BUILTIN_VCMPGTUH_P }, | |
6107 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpgtsh.", "__builtin_altivec_vcmpgtsh_p", ALTIVEC_BUILTIN_VCMPGTSH_P }, | |
6108 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpequh.", "__builtin_altivec_vcmpequh_p", ALTIVEC_BUILTIN_VCMPEQUH_P }, | |
6109 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpequb.", "__builtin_altivec_vcmpequb_p", ALTIVEC_BUILTIN_VCMPEQUB_P }, | |
6110 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpgtsb.", "__builtin_altivec_vcmpgtsb_p", ALTIVEC_BUILTIN_VCMPGTSB_P }, | |
6111 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpgtub.", "__builtin_altivec_vcmpgtub_p", ALTIVEC_BUILTIN_VCMPGTUB_P } | |
0ac081f6 | 6112 | }; |
24408032 | 6113 | |
a3170dc6 AH |
6114 | /* SPE predicates. */ |
6115 | static struct builtin_description bdesc_spe_predicates[] = | |
6116 | { | |
6117 | /* Place-holder. Leave as first. */ | |
6118 | { 0, CODE_FOR_spe_evcmpeq, "__builtin_spe_evcmpeq", SPE_BUILTIN_EVCMPEQ }, | |
6119 | { 0, CODE_FOR_spe_evcmpgts, "__builtin_spe_evcmpgts", SPE_BUILTIN_EVCMPGTS }, | |
6120 | { 0, CODE_FOR_spe_evcmpgtu, "__builtin_spe_evcmpgtu", SPE_BUILTIN_EVCMPGTU }, | |
6121 | { 0, CODE_FOR_spe_evcmplts, "__builtin_spe_evcmplts", SPE_BUILTIN_EVCMPLTS }, | |
6122 | { 0, CODE_FOR_spe_evcmpltu, "__builtin_spe_evcmpltu", SPE_BUILTIN_EVCMPLTU }, | |
6123 | { 0, CODE_FOR_spe_evfscmpeq, "__builtin_spe_evfscmpeq", SPE_BUILTIN_EVFSCMPEQ }, | |
6124 | { 0, CODE_FOR_spe_evfscmpgt, "__builtin_spe_evfscmpgt", SPE_BUILTIN_EVFSCMPGT }, | |
6125 | { 0, CODE_FOR_spe_evfscmplt, "__builtin_spe_evfscmplt", SPE_BUILTIN_EVFSCMPLT }, | |
6126 | { 0, CODE_FOR_spe_evfststeq, "__builtin_spe_evfststeq", SPE_BUILTIN_EVFSTSTEQ }, | |
6127 | { 0, CODE_FOR_spe_evfststgt, "__builtin_spe_evfststgt", SPE_BUILTIN_EVFSTSTGT }, | |
6128 | /* Place-holder. Leave as last. */ | |
6129 | { 0, CODE_FOR_spe_evfststlt, "__builtin_spe_evfststlt", SPE_BUILTIN_EVFSTSTLT }, | |
6130 | }; | |
6131 | ||
6132 | /* SPE evsel predicates. */ | |
6133 | static struct builtin_description bdesc_spe_evsel[] = | |
6134 | { | |
6135 | /* Place-holder. Leave as first. */ | |
6136 | { 0, CODE_FOR_spe_evcmpgts, "__builtin_spe_evsel_gts", SPE_BUILTIN_EVSEL_CMPGTS }, | |
6137 | { 0, CODE_FOR_spe_evcmpgtu, "__builtin_spe_evsel_gtu", SPE_BUILTIN_EVSEL_CMPGTU }, | |
6138 | { 0, CODE_FOR_spe_evcmplts, "__builtin_spe_evsel_lts", SPE_BUILTIN_EVSEL_CMPLTS }, | |
6139 | { 0, CODE_FOR_spe_evcmpltu, "__builtin_spe_evsel_ltu", SPE_BUILTIN_EVSEL_CMPLTU }, | |
6140 | { 0, CODE_FOR_spe_evcmpeq, "__builtin_spe_evsel_eq", SPE_BUILTIN_EVSEL_CMPEQ }, | |
6141 | { 0, CODE_FOR_spe_evfscmpgt, "__builtin_spe_evsel_fsgt", SPE_BUILTIN_EVSEL_FSCMPGT }, | |
6142 | { 0, CODE_FOR_spe_evfscmplt, "__builtin_spe_evsel_fslt", SPE_BUILTIN_EVSEL_FSCMPLT }, | |
6143 | { 0, CODE_FOR_spe_evfscmpeq, "__builtin_spe_evsel_fseq", SPE_BUILTIN_EVSEL_FSCMPEQ }, | |
6144 | { 0, CODE_FOR_spe_evfststgt, "__builtin_spe_evsel_fststgt", SPE_BUILTIN_EVSEL_FSTSTGT }, | |
6145 | { 0, CODE_FOR_spe_evfststlt, "__builtin_spe_evsel_fststlt", SPE_BUILTIN_EVSEL_FSTSTLT }, | |
6146 | /* Place-holder. Leave as last. */ | |
6147 | { 0, CODE_FOR_spe_evfststeq, "__builtin_spe_evsel_fststeq", SPE_BUILTIN_EVSEL_FSTSTEQ }, | |
6148 | }; | |
6149 | ||
b6d08ca1 | 6150 | /* ABS* operations. */ |
100c4561 AH |
6151 | |
6152 | static const struct builtin_description bdesc_abs[] = | |
6153 | { | |
6154 | { MASK_ALTIVEC, CODE_FOR_absv4si2, "__builtin_altivec_abs_v4si", ALTIVEC_BUILTIN_ABS_V4SI }, | |
6155 | { MASK_ALTIVEC, CODE_FOR_absv8hi2, "__builtin_altivec_abs_v8hi", ALTIVEC_BUILTIN_ABS_V8HI }, | |
6156 | { MASK_ALTIVEC, CODE_FOR_absv4sf2, "__builtin_altivec_abs_v4sf", ALTIVEC_BUILTIN_ABS_V4SF }, | |
6157 | { MASK_ALTIVEC, CODE_FOR_absv16qi2, "__builtin_altivec_abs_v16qi", ALTIVEC_BUILTIN_ABS_V16QI }, | |
6158 | { MASK_ALTIVEC, CODE_FOR_altivec_abss_v4si, "__builtin_altivec_abss_v4si", ALTIVEC_BUILTIN_ABSS_V4SI }, | |
6159 | { MASK_ALTIVEC, CODE_FOR_altivec_abss_v8hi, "__builtin_altivec_abss_v8hi", ALTIVEC_BUILTIN_ABSS_V8HI }, | |
6160 | { MASK_ALTIVEC, CODE_FOR_altivec_abss_v16qi, "__builtin_altivec_abss_v16qi", ALTIVEC_BUILTIN_ABSS_V16QI } | |
6161 | }; | |
6162 | ||
617e0e1d DB |
6163 | /* Simple unary operations: VECb = foo (unsigned literal) or VECb = |
6164 | foo (VECa). */ | |
24408032 | 6165 | |
a3170dc6 | 6166 | static struct builtin_description bdesc_1arg[] = |
2212663f | 6167 | { |
617e0e1d DB |
6168 | { MASK_ALTIVEC, CODE_FOR_altivec_vexptefp, "__builtin_altivec_vexptefp", ALTIVEC_BUILTIN_VEXPTEFP }, |
6169 | { MASK_ALTIVEC, CODE_FOR_altivec_vlogefp, "__builtin_altivec_vlogefp", ALTIVEC_BUILTIN_VLOGEFP }, | |
6170 | { MASK_ALTIVEC, CODE_FOR_altivec_vrefp, "__builtin_altivec_vrefp", ALTIVEC_BUILTIN_VREFP }, | |
6171 | { MASK_ALTIVEC, CODE_FOR_altivec_vrfim, "__builtin_altivec_vrfim", ALTIVEC_BUILTIN_VRFIM }, | |
6172 | { MASK_ALTIVEC, CODE_FOR_altivec_vrfin, "__builtin_altivec_vrfin", ALTIVEC_BUILTIN_VRFIN }, | |
6173 | { MASK_ALTIVEC, CODE_FOR_altivec_vrfip, "__builtin_altivec_vrfip", ALTIVEC_BUILTIN_VRFIP }, | |
6174 | { MASK_ALTIVEC, CODE_FOR_ftruncv4sf2, "__builtin_altivec_vrfiz", ALTIVEC_BUILTIN_VRFIZ }, | |
6175 | { MASK_ALTIVEC, CODE_FOR_altivec_vrsqrtefp, "__builtin_altivec_vrsqrtefp", ALTIVEC_BUILTIN_VRSQRTEFP }, | |
2212663f DB |
6176 | { MASK_ALTIVEC, CODE_FOR_altivec_vspltisb, "__builtin_altivec_vspltisb", ALTIVEC_BUILTIN_VSPLTISB }, |
6177 | { MASK_ALTIVEC, CODE_FOR_altivec_vspltish, "__builtin_altivec_vspltish", ALTIVEC_BUILTIN_VSPLTISH }, | |
6178 | { MASK_ALTIVEC, CODE_FOR_altivec_vspltisw, "__builtin_altivec_vspltisw", ALTIVEC_BUILTIN_VSPLTISW }, | |
20e26713 AH |
6179 | { MASK_ALTIVEC, CODE_FOR_altivec_vupkhsb, "__builtin_altivec_vupkhsb", ALTIVEC_BUILTIN_VUPKHSB }, |
6180 | { MASK_ALTIVEC, CODE_FOR_altivec_vupkhpx, "__builtin_altivec_vupkhpx", ALTIVEC_BUILTIN_VUPKHPX }, | |
6181 | { MASK_ALTIVEC, CODE_FOR_altivec_vupkhsh, "__builtin_altivec_vupkhsh", ALTIVEC_BUILTIN_VUPKHSH }, | |
6182 | { MASK_ALTIVEC, CODE_FOR_altivec_vupklsb, "__builtin_altivec_vupklsb", ALTIVEC_BUILTIN_VUPKLSB }, | |
6183 | { MASK_ALTIVEC, CODE_FOR_altivec_vupklpx, "__builtin_altivec_vupklpx", ALTIVEC_BUILTIN_VUPKLPX }, | |
6184 | { MASK_ALTIVEC, CODE_FOR_altivec_vupklsh, "__builtin_altivec_vupklsh", ALTIVEC_BUILTIN_VUPKLSH }, | |
a3170dc6 AH |
6185 | |
6186 | /* The SPE unary builtins must start with SPE_BUILTIN_EVABS and | |
6187 | end with SPE_BUILTIN_EVSUBFUSIAAW. */ | |
6188 | { 0, CODE_FOR_spe_evabs, "__builtin_spe_evabs", SPE_BUILTIN_EVABS }, | |
6189 | { 0, CODE_FOR_spe_evaddsmiaaw, "__builtin_spe_evaddsmiaaw", SPE_BUILTIN_EVADDSMIAAW }, | |
6190 | { 0, CODE_FOR_spe_evaddssiaaw, "__builtin_spe_evaddssiaaw", SPE_BUILTIN_EVADDSSIAAW }, | |
6191 | { 0, CODE_FOR_spe_evaddumiaaw, "__builtin_spe_evaddumiaaw", SPE_BUILTIN_EVADDUMIAAW }, | |
6192 | { 0, CODE_FOR_spe_evaddusiaaw, "__builtin_spe_evaddusiaaw", SPE_BUILTIN_EVADDUSIAAW }, | |
6193 | { 0, CODE_FOR_spe_evcntlsw, "__builtin_spe_evcntlsw", SPE_BUILTIN_EVCNTLSW }, | |
6194 | { 0, CODE_FOR_spe_evcntlzw, "__builtin_spe_evcntlzw", SPE_BUILTIN_EVCNTLZW }, | |
6195 | { 0, CODE_FOR_spe_evextsb, "__builtin_spe_evextsb", SPE_BUILTIN_EVEXTSB }, | |
6196 | { 0, CODE_FOR_spe_evextsh, "__builtin_spe_evextsh", SPE_BUILTIN_EVEXTSH }, | |
6197 | { 0, CODE_FOR_spe_evfsabs, "__builtin_spe_evfsabs", SPE_BUILTIN_EVFSABS }, | |
6198 | { 0, CODE_FOR_spe_evfscfsf, "__builtin_spe_evfscfsf", SPE_BUILTIN_EVFSCFSF }, | |
6199 | { 0, CODE_FOR_spe_evfscfsi, "__builtin_spe_evfscfsi", SPE_BUILTIN_EVFSCFSI }, | |
6200 | { 0, CODE_FOR_spe_evfscfuf, "__builtin_spe_evfscfuf", SPE_BUILTIN_EVFSCFUF }, | |
6201 | { 0, CODE_FOR_spe_evfscfui, "__builtin_spe_evfscfui", SPE_BUILTIN_EVFSCFUI }, | |
6202 | { 0, CODE_FOR_spe_evfsctsf, "__builtin_spe_evfsctsf", SPE_BUILTIN_EVFSCTSF }, | |
6203 | { 0, CODE_FOR_spe_evfsctsi, "__builtin_spe_evfsctsi", SPE_BUILTIN_EVFSCTSI }, | |
6204 | { 0, CODE_FOR_spe_evfsctsiz, "__builtin_spe_evfsctsiz", SPE_BUILTIN_EVFSCTSIZ }, | |
6205 | { 0, CODE_FOR_spe_evfsctuf, "__builtin_spe_evfsctuf", SPE_BUILTIN_EVFSCTUF }, | |
6206 | { 0, CODE_FOR_spe_evfsctui, "__builtin_spe_evfsctui", SPE_BUILTIN_EVFSCTUI }, | |
6207 | { 0, CODE_FOR_spe_evfsctuiz, "__builtin_spe_evfsctuiz", SPE_BUILTIN_EVFSCTUIZ }, | |
6208 | { 0, CODE_FOR_spe_evfsnabs, "__builtin_spe_evfsnabs", SPE_BUILTIN_EVFSNABS }, | |
6209 | { 0, CODE_FOR_spe_evfsneg, "__builtin_spe_evfsneg", SPE_BUILTIN_EVFSNEG }, | |
6210 | { 0, CODE_FOR_spe_evmra, "__builtin_spe_evmra", SPE_BUILTIN_EVMRA }, | |
6a599451 | 6211 | { 0, CODE_FOR_negv2si2, "__builtin_spe_evneg", SPE_BUILTIN_EVNEG }, |
a3170dc6 AH |
6212 | { 0, CODE_FOR_spe_evrndw, "__builtin_spe_evrndw", SPE_BUILTIN_EVRNDW }, |
6213 | { 0, CODE_FOR_spe_evsubfsmiaaw, "__builtin_spe_evsubfsmiaaw", SPE_BUILTIN_EVSUBFSMIAAW }, | |
6214 | { 0, CODE_FOR_spe_evsubfssiaaw, "__builtin_spe_evsubfssiaaw", SPE_BUILTIN_EVSUBFSSIAAW }, | |
6215 | { 0, CODE_FOR_spe_evsubfumiaaw, "__builtin_spe_evsubfumiaaw", SPE_BUILTIN_EVSUBFUMIAAW }, | |
a3170dc6 AH |
6216 | |
6217 | /* Place-holder. Leave as last unary SPE builtin. */ | |
6218 | { 0, CODE_FOR_spe_evsubfusiaaw, "__builtin_spe_evsubfusiaaw", SPE_BUILTIN_EVSUBFUSIAAW }, | |
2212663f DB |
6219 | }; |
6220 | ||
6221 | static rtx | |
a2369ed3 | 6222 | rs6000_expand_unop_builtin (enum insn_code icode, tree arglist, rtx target) |
2212663f DB |
6223 | { |
6224 | rtx pat; | |
6225 | tree arg0 = TREE_VALUE (arglist); | |
6226 | rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
6227 | enum machine_mode tmode = insn_data[icode].operand[0].mode; | |
6228 | enum machine_mode mode0 = insn_data[icode].operand[1].mode; | |
6229 | ||
0559cc77 DE |
6230 | if (icode == CODE_FOR_nothing) |
6231 | /* Builtin not supported on this processor. */ | |
6232 | return 0; | |
6233 | ||
20e26713 AH |
6234 | /* If we got invalid arguments bail out before generating bad rtl. */ |
6235 | if (arg0 == error_mark_node) | |
9a171fcd | 6236 | return const0_rtx; |
20e26713 | 6237 | |
0559cc77 DE |
6238 | if (icode == CODE_FOR_altivec_vspltisb |
6239 | || icode == CODE_FOR_altivec_vspltish | |
6240 | || icode == CODE_FOR_altivec_vspltisw | |
6241 | || icode == CODE_FOR_spe_evsplatfi | |
6242 | || icode == CODE_FOR_spe_evsplati) | |
b44140e7 AH |
6243 | { |
6244 | /* Only allow 5-bit *signed* literals. */ | |
b44140e7 AH |
6245 | if (GET_CODE (op0) != CONST_INT |
6246 | || INTVAL (op0) > 0x1f | |
6247 | || INTVAL (op0) < -0x1f) | |
6248 | { | |
6249 | error ("argument 1 must be a 5-bit signed literal"); | |
9a171fcd | 6250 | return const0_rtx; |
b44140e7 | 6251 | } |
b44140e7 AH |
6252 | } |
6253 | ||
c62f2db5 | 6254 | if (target == 0 |
2212663f DB |
6255 | || GET_MODE (target) != tmode |
6256 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
6257 | target = gen_reg_rtx (tmode); | |
6258 | ||
6259 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) | |
6260 | op0 = copy_to_mode_reg (mode0, op0); | |
6261 | ||
6262 | pat = GEN_FCN (icode) (target, op0); | |
6263 | if (! pat) | |
6264 | return 0; | |
6265 | emit_insn (pat); | |
0ac081f6 | 6266 | |
2212663f DB |
6267 | return target; |
6268 | } | |
ae4b4a02 | 6269 | |
100c4561 | 6270 | static rtx |
a2369ed3 | 6271 | altivec_expand_abs_builtin (enum insn_code icode, tree arglist, rtx target) |
100c4561 AH |
6272 | { |
6273 | rtx pat, scratch1, scratch2; | |
6274 | tree arg0 = TREE_VALUE (arglist); | |
6275 | rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
6276 | enum machine_mode tmode = insn_data[icode].operand[0].mode; | |
6277 | enum machine_mode mode0 = insn_data[icode].operand[1].mode; | |
6278 | ||
6279 | /* If we have invalid arguments, bail out before generating bad rtl. */ | |
6280 | if (arg0 == error_mark_node) | |
9a171fcd | 6281 | return const0_rtx; |
100c4561 AH |
6282 | |
6283 | if (target == 0 | |
6284 | || GET_MODE (target) != tmode | |
6285 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
6286 | target = gen_reg_rtx (tmode); | |
6287 | ||
6288 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) | |
6289 | op0 = copy_to_mode_reg (mode0, op0); | |
6290 | ||
6291 | scratch1 = gen_reg_rtx (mode0); | |
6292 | scratch2 = gen_reg_rtx (mode0); | |
6293 | ||
6294 | pat = GEN_FCN (icode) (target, op0, scratch1, scratch2); | |
6295 | if (! pat) | |
6296 | return 0; | |
6297 | emit_insn (pat); | |
6298 | ||
6299 | return target; | |
6300 | } | |
6301 | ||
0ac081f6 | 6302 | static rtx |
a2369ed3 | 6303 | rs6000_expand_binop_builtin (enum insn_code icode, tree arglist, rtx target) |
0ac081f6 AH |
6304 | { |
6305 | rtx pat; | |
6306 | tree arg0 = TREE_VALUE (arglist); | |
6307 | tree arg1 = TREE_VALUE (TREE_CHAIN (arglist)); | |
6308 | rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
6309 | rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); | |
6310 | enum machine_mode tmode = insn_data[icode].operand[0].mode; | |
6311 | enum machine_mode mode0 = insn_data[icode].operand[1].mode; | |
6312 | enum machine_mode mode1 = insn_data[icode].operand[2].mode; | |
6313 | ||
0559cc77 DE |
6314 | if (icode == CODE_FOR_nothing) |
6315 | /* Builtin not supported on this processor. */ | |
6316 | return 0; | |
6317 | ||
20e26713 AH |
6318 | /* If we got invalid arguments bail out before generating bad rtl. */ |
6319 | if (arg0 == error_mark_node || arg1 == error_mark_node) | |
9a171fcd | 6320 | return const0_rtx; |
20e26713 | 6321 | |
0559cc77 DE |
6322 | if (icode == CODE_FOR_altivec_vcfux |
6323 | || icode == CODE_FOR_altivec_vcfsx | |
6324 | || icode == CODE_FOR_altivec_vctsxs | |
6325 | || icode == CODE_FOR_altivec_vctuxs | |
6326 | || icode == CODE_FOR_altivec_vspltb | |
6327 | || icode == CODE_FOR_altivec_vsplth | |
6328 | || icode == CODE_FOR_altivec_vspltw | |
6329 | || icode == CODE_FOR_spe_evaddiw | |
6330 | || icode == CODE_FOR_spe_evldd | |
6331 | || icode == CODE_FOR_spe_evldh | |
6332 | || icode == CODE_FOR_spe_evldw | |
6333 | || icode == CODE_FOR_spe_evlhhesplat | |
6334 | || icode == CODE_FOR_spe_evlhhossplat | |
6335 | || icode == CODE_FOR_spe_evlhhousplat | |
6336 | || icode == CODE_FOR_spe_evlwhe | |
6337 | || icode == CODE_FOR_spe_evlwhos | |
6338 | || icode == CODE_FOR_spe_evlwhou | |
6339 | || icode == CODE_FOR_spe_evlwhsplat | |
6340 | || icode == CODE_FOR_spe_evlwwsplat | |
6341 | || icode == CODE_FOR_spe_evrlwi | |
6342 | || icode == CODE_FOR_spe_evslwi | |
6343 | || icode == CODE_FOR_spe_evsrwis | |
f5119d10 | 6344 | || icode == CODE_FOR_spe_evsubifw |
0559cc77 | 6345 | || icode == CODE_FOR_spe_evsrwiu) |
b44140e7 AH |
6346 | { |
6347 | /* Only allow 5-bit unsigned literals. */ | |
8bb418a3 | 6348 | STRIP_NOPS (arg1); |
b44140e7 AH |
6349 | if (TREE_CODE (arg1) != INTEGER_CST |
6350 | || TREE_INT_CST_LOW (arg1) & ~0x1f) | |
6351 | { | |
6352 | error ("argument 2 must be a 5-bit unsigned literal"); | |
9a171fcd | 6353 | return const0_rtx; |
b44140e7 | 6354 | } |
b44140e7 AH |
6355 | } |
6356 | ||
c62f2db5 | 6357 | if (target == 0 |
0ac081f6 AH |
6358 | || GET_MODE (target) != tmode |
6359 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
6360 | target = gen_reg_rtx (tmode); | |
6361 | ||
6362 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) | |
6363 | op0 = copy_to_mode_reg (mode0, op0); | |
6364 | if (! (*insn_data[icode].operand[2].predicate) (op1, mode1)) | |
6365 | op1 = copy_to_mode_reg (mode1, op1); | |
6366 | ||
6367 | pat = GEN_FCN (icode) (target, op0, op1); | |
6368 | if (! pat) | |
6369 | return 0; | |
6370 | emit_insn (pat); | |
6371 | ||
6372 | return target; | |
6373 | } | |
6525c0e7 | 6374 | |
ae4b4a02 | 6375 | static rtx |
f676971a | 6376 | altivec_expand_predicate_builtin (enum insn_code icode, const char *opcode, |
a2369ed3 | 6377 | tree arglist, rtx target) |
ae4b4a02 AH |
6378 | { |
6379 | rtx pat, scratch; | |
6380 | tree cr6_form = TREE_VALUE (arglist); | |
6381 | tree arg0 = TREE_VALUE (TREE_CHAIN (arglist)); | |
6382 | tree arg1 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist))); | |
6383 | rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
6384 | rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); | |
6385 | enum machine_mode tmode = SImode; | |
6386 | enum machine_mode mode0 = insn_data[icode].operand[1].mode; | |
6387 | enum machine_mode mode1 = insn_data[icode].operand[2].mode; | |
6388 | int cr6_form_int; | |
6389 | ||
6390 | if (TREE_CODE (cr6_form) != INTEGER_CST) | |
6391 | { | |
6392 | error ("argument 1 of __builtin_altivec_predicate must be a constant"); | |
9a171fcd | 6393 | return const0_rtx; |
ae4b4a02 AH |
6394 | } |
6395 | else | |
6396 | cr6_form_int = TREE_INT_CST_LOW (cr6_form); | |
6397 | ||
6398 | if (mode0 != mode1) | |
6399 | abort (); | |
6400 | ||
6401 | /* If we have invalid arguments, bail out before generating bad rtl. */ | |
6402 | if (arg0 == error_mark_node || arg1 == error_mark_node) | |
9a171fcd | 6403 | return const0_rtx; |
ae4b4a02 AH |
6404 | |
6405 | if (target == 0 | |
6406 | || GET_MODE (target) != tmode | |
6407 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
6408 | target = gen_reg_rtx (tmode); | |
6409 | ||
6410 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) | |
6411 | op0 = copy_to_mode_reg (mode0, op0); | |
6412 | if (! (*insn_data[icode].operand[2].predicate) (op1, mode1)) | |
6413 | op1 = copy_to_mode_reg (mode1, op1); | |
6414 | ||
6415 | scratch = gen_reg_rtx (mode0); | |
6416 | ||
6417 | pat = GEN_FCN (icode) (scratch, op0, op1, | |
f1c25d3b | 6418 | gen_rtx_SYMBOL_REF (Pmode, opcode)); |
ae4b4a02 AH |
6419 | if (! pat) |
6420 | return 0; | |
6421 | emit_insn (pat); | |
6422 | ||
6423 | /* The vec_any* and vec_all* predicates use the same opcodes for two | |
6424 | different operations, but the bits in CR6 will be different | |
6425 | depending on what information we want. So we have to play tricks | |
6426 | with CR6 to get the right bits out. | |
6427 | ||
6428 | If you think this is disgusting, look at the specs for the | |
6429 | AltiVec predicates. */ | |
6430 | ||
c4ad648e AM |
6431 | switch (cr6_form_int) |
6432 | { | |
6433 | case 0: | |
6434 | emit_insn (gen_cr6_test_for_zero (target)); | |
6435 | break; | |
6436 | case 1: | |
6437 | emit_insn (gen_cr6_test_for_zero_reverse (target)); | |
6438 | break; | |
6439 | case 2: | |
6440 | emit_insn (gen_cr6_test_for_lt (target)); | |
6441 | break; | |
6442 | case 3: | |
6443 | emit_insn (gen_cr6_test_for_lt_reverse (target)); | |
6444 | break; | |
6445 | default: | |
6446 | error ("argument 1 of __builtin_altivec_predicate is out of range"); | |
6447 | break; | |
6448 | } | |
ae4b4a02 AH |
6449 | |
6450 | return target; | |
6451 | } | |
6452 | ||
b4a62fa0 | 6453 | static rtx |
38f391a5 | 6454 | altivec_expand_lv_builtin (enum insn_code icode, tree arglist, rtx target) |
b4a62fa0 SB |
6455 | { |
6456 | rtx pat, addr; | |
6457 | tree arg0 = TREE_VALUE (arglist); | |
6458 | tree arg1 = TREE_VALUE (TREE_CHAIN (arglist)); | |
6459 | enum machine_mode tmode = insn_data[icode].operand[0].mode; | |
6460 | enum machine_mode mode0 = Pmode; | |
6461 | enum machine_mode mode1 = Pmode; | |
6462 | rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
6463 | rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); | |
6464 | ||
6465 | if (icode == CODE_FOR_nothing) | |
6466 | /* Builtin not supported on this processor. */ | |
6467 | return 0; | |
6468 | ||
6469 | /* If we got invalid arguments bail out before generating bad rtl. */ | |
6470 | if (arg0 == error_mark_node || arg1 == error_mark_node) | |
6471 | return const0_rtx; | |
6472 | ||
6473 | if (target == 0 | |
6474 | || GET_MODE (target) != tmode | |
6475 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
6476 | target = gen_reg_rtx (tmode); | |
6477 | ||
f676971a | 6478 | op1 = copy_to_mode_reg (mode1, op1); |
b4a62fa0 SB |
6479 | |
6480 | if (op0 == const0_rtx) | |
6481 | { | |
6482 | addr = gen_rtx_MEM (tmode, op1); | |
6483 | } | |
6484 | else | |
6485 | { | |
6486 | op0 = copy_to_mode_reg (mode0, op0); | |
6487 | addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op0, op1)); | |
6488 | } | |
6489 | ||
6490 | pat = GEN_FCN (icode) (target, addr); | |
6491 | ||
6492 | if (! pat) | |
6493 | return 0; | |
6494 | emit_insn (pat); | |
6495 | ||
6496 | return target; | |
6497 | } | |
6498 | ||
61bea3b0 AH |
6499 | static rtx |
6500 | spe_expand_stv_builtin (enum insn_code icode, tree arglist) | |
6501 | { | |
6502 | tree arg0 = TREE_VALUE (arglist); | |
6503 | tree arg1 = TREE_VALUE (TREE_CHAIN (arglist)); | |
6504 | tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist))); | |
6505 | rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
6506 | rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); | |
6507 | rtx op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0); | |
6508 | rtx pat; | |
6509 | enum machine_mode mode0 = insn_data[icode].operand[0].mode; | |
6510 | enum machine_mode mode1 = insn_data[icode].operand[1].mode; | |
6511 | enum machine_mode mode2 = insn_data[icode].operand[2].mode; | |
6512 | ||
6513 | /* Invalid arguments. Bail before doing anything stoopid! */ | |
6514 | if (arg0 == error_mark_node | |
6515 | || arg1 == error_mark_node | |
6516 | || arg2 == error_mark_node) | |
6517 | return const0_rtx; | |
6518 | ||
6519 | if (! (*insn_data[icode].operand[2].predicate) (op0, mode2)) | |
6520 | op0 = copy_to_mode_reg (mode2, op0); | |
6521 | if (! (*insn_data[icode].operand[0].predicate) (op1, mode0)) | |
6522 | op1 = copy_to_mode_reg (mode0, op1); | |
6523 | if (! (*insn_data[icode].operand[1].predicate) (op2, mode1)) | |
6524 | op2 = copy_to_mode_reg (mode1, op2); | |
6525 | ||
6526 | pat = GEN_FCN (icode) (op1, op2, op0); | |
6527 | if (pat) | |
6528 | emit_insn (pat); | |
6529 | return NULL_RTX; | |
6530 | } | |
6531 | ||
6525c0e7 | 6532 | static rtx |
a2369ed3 | 6533 | altivec_expand_stv_builtin (enum insn_code icode, tree arglist) |
6525c0e7 AH |
6534 | { |
6535 | tree arg0 = TREE_VALUE (arglist); | |
6536 | tree arg1 = TREE_VALUE (TREE_CHAIN (arglist)); | |
6537 | tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist))); | |
6538 | rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
6539 | rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); | |
6540 | rtx op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0); | |
b4a62fa0 SB |
6541 | rtx pat, addr; |
6542 | enum machine_mode tmode = insn_data[icode].operand[0].mode; | |
6543 | enum machine_mode mode1 = Pmode; | |
6544 | enum machine_mode mode2 = Pmode; | |
6525c0e7 AH |
6545 | |
6546 | /* Invalid arguments. Bail before doing anything stoopid! */ | |
6547 | if (arg0 == error_mark_node | |
6548 | || arg1 == error_mark_node | |
6549 | || arg2 == error_mark_node) | |
9a171fcd | 6550 | return const0_rtx; |
6525c0e7 | 6551 | |
b4a62fa0 SB |
6552 | if (! (*insn_data[icode].operand[1].predicate) (op0, tmode)) |
6553 | op0 = copy_to_mode_reg (tmode, op0); | |
6554 | ||
f676971a | 6555 | op2 = copy_to_mode_reg (mode2, op2); |
b4a62fa0 SB |
6556 | |
6557 | if (op1 == const0_rtx) | |
6558 | { | |
6559 | addr = gen_rtx_MEM (tmode, op2); | |
6560 | } | |
6561 | else | |
6562 | { | |
6563 | op1 = copy_to_mode_reg (mode1, op1); | |
6564 | addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op1, op2)); | |
6565 | } | |
6525c0e7 | 6566 | |
b4a62fa0 | 6567 | pat = GEN_FCN (icode) (addr, op0); |
6525c0e7 AH |
6568 | if (pat) |
6569 | emit_insn (pat); | |
6570 | return NULL_RTX; | |
6571 | } | |
6572 | ||
2212663f | 6573 | static rtx |
a2369ed3 | 6574 | rs6000_expand_ternop_builtin (enum insn_code icode, tree arglist, rtx target) |
2212663f DB |
6575 | { |
6576 | rtx pat; | |
6577 | tree arg0 = TREE_VALUE (arglist); | |
6578 | tree arg1 = TREE_VALUE (TREE_CHAIN (arglist)); | |
6579 | tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist))); | |
6580 | rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
6581 | rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); | |
6582 | rtx op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0); | |
6583 | enum machine_mode tmode = insn_data[icode].operand[0].mode; | |
6584 | enum machine_mode mode0 = insn_data[icode].operand[1].mode; | |
6585 | enum machine_mode mode1 = insn_data[icode].operand[2].mode; | |
6586 | enum machine_mode mode2 = insn_data[icode].operand[3].mode; | |
0ac081f6 | 6587 | |
774b5662 DE |
6588 | if (icode == CODE_FOR_nothing) |
6589 | /* Builtin not supported on this processor. */ | |
6590 | return 0; | |
6591 | ||
20e26713 AH |
6592 | /* If we got invalid arguments bail out before generating bad rtl. */ |
6593 | if (arg0 == error_mark_node | |
6594 | || arg1 == error_mark_node | |
6595 | || arg2 == error_mark_node) | |
9a171fcd | 6596 | return const0_rtx; |
20e26713 | 6597 | |
774b5662 DE |
6598 | if (icode == CODE_FOR_altivec_vsldoi_4sf |
6599 | || icode == CODE_FOR_altivec_vsldoi_4si | |
6600 | || icode == CODE_FOR_altivec_vsldoi_8hi | |
6601 | || icode == CODE_FOR_altivec_vsldoi_16qi) | |
b44140e7 AH |
6602 | { |
6603 | /* Only allow 4-bit unsigned literals. */ | |
8bb418a3 | 6604 | STRIP_NOPS (arg2); |
b44140e7 AH |
6605 | if (TREE_CODE (arg2) != INTEGER_CST |
6606 | || TREE_INT_CST_LOW (arg2) & ~0xf) | |
6607 | { | |
6608 | error ("argument 3 must be a 4-bit unsigned literal"); | |
e3277ffb | 6609 | return const0_rtx; |
b44140e7 | 6610 | } |
b44140e7 AH |
6611 | } |
6612 | ||
c62f2db5 | 6613 | if (target == 0 |
2212663f DB |
6614 | || GET_MODE (target) != tmode |
6615 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
6616 | target = gen_reg_rtx (tmode); | |
6617 | ||
6618 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) | |
6619 | op0 = copy_to_mode_reg (mode0, op0); | |
6620 | if (! (*insn_data[icode].operand[2].predicate) (op1, mode1)) | |
6621 | op1 = copy_to_mode_reg (mode1, op1); | |
6622 | if (! (*insn_data[icode].operand[3].predicate) (op2, mode2)) | |
6623 | op2 = copy_to_mode_reg (mode2, op2); | |
6624 | ||
6625 | pat = GEN_FCN (icode) (target, op0, op1, op2); | |
6626 | if (! pat) | |
6627 | return 0; | |
6628 | emit_insn (pat); | |
6629 | ||
6630 | return target; | |
6631 | } | |
92898235 | 6632 | |
3a9b8c7e | 6633 | /* Expand the lvx builtins. */ |
0ac081f6 | 6634 | static rtx |
a2369ed3 | 6635 | altivec_expand_ld_builtin (tree exp, rtx target, bool *expandedp) |
0ac081f6 | 6636 | { |
0ac081f6 AH |
6637 | tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0); |
6638 | tree arglist = TREE_OPERAND (exp, 1); | |
0ac081f6 | 6639 | unsigned int fcode = DECL_FUNCTION_CODE (fndecl); |
3a9b8c7e AH |
6640 | tree arg0; |
6641 | enum machine_mode tmode, mode0; | |
7c3abc73 | 6642 | rtx pat, op0; |
3a9b8c7e | 6643 | enum insn_code icode; |
92898235 | 6644 | |
0ac081f6 AH |
6645 | switch (fcode) |
6646 | { | |
f18c054f DB |
6647 | case ALTIVEC_BUILTIN_LD_INTERNAL_16qi: |
6648 | icode = CODE_FOR_altivec_lvx_16qi; | |
3a9b8c7e | 6649 | break; |
f18c054f DB |
6650 | case ALTIVEC_BUILTIN_LD_INTERNAL_8hi: |
6651 | icode = CODE_FOR_altivec_lvx_8hi; | |
3a9b8c7e AH |
6652 | break; |
6653 | case ALTIVEC_BUILTIN_LD_INTERNAL_4si: | |
6654 | icode = CODE_FOR_altivec_lvx_4si; | |
6655 | break; | |
6656 | case ALTIVEC_BUILTIN_LD_INTERNAL_4sf: | |
6657 | icode = CODE_FOR_altivec_lvx_4sf; | |
6658 | break; | |
6659 | default: | |
6660 | *expandedp = false; | |
6661 | return NULL_RTX; | |
6662 | } | |
0ac081f6 | 6663 | |
3a9b8c7e | 6664 | *expandedp = true; |
f18c054f | 6665 | |
3a9b8c7e AH |
6666 | arg0 = TREE_VALUE (arglist); |
6667 | op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
6668 | tmode = insn_data[icode].operand[0].mode; | |
6669 | mode0 = insn_data[icode].operand[1].mode; | |
f18c054f | 6670 | |
3a9b8c7e AH |
6671 | if (target == 0 |
6672 | || GET_MODE (target) != tmode | |
6673 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
6674 | target = gen_reg_rtx (tmode); | |
24408032 | 6675 | |
3a9b8c7e AH |
6676 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) |
6677 | op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0)); | |
f18c054f | 6678 | |
3a9b8c7e AH |
6679 | pat = GEN_FCN (icode) (target, op0); |
6680 | if (! pat) | |
6681 | return 0; | |
6682 | emit_insn (pat); | |
6683 | return target; | |
6684 | } | |
f18c054f | 6685 | |
3a9b8c7e AH |
6686 | /* Expand the stvx builtins. */ |
6687 | static rtx | |
f676971a | 6688 | altivec_expand_st_builtin (tree exp, rtx target ATTRIBUTE_UNUSED, |
a2369ed3 | 6689 | bool *expandedp) |
3a9b8c7e AH |
6690 | { |
6691 | tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0); | |
6692 | tree arglist = TREE_OPERAND (exp, 1); | |
6693 | unsigned int fcode = DECL_FUNCTION_CODE (fndecl); | |
6694 | tree arg0, arg1; | |
6695 | enum machine_mode mode0, mode1; | |
7c3abc73 | 6696 | rtx pat, op0, op1; |
3a9b8c7e | 6697 | enum insn_code icode; |
f18c054f | 6698 | |
3a9b8c7e AH |
6699 | switch (fcode) |
6700 | { | |
6701 | case ALTIVEC_BUILTIN_ST_INTERNAL_16qi: | |
6702 | icode = CODE_FOR_altivec_stvx_16qi; | |
6703 | break; | |
6704 | case ALTIVEC_BUILTIN_ST_INTERNAL_8hi: | |
6705 | icode = CODE_FOR_altivec_stvx_8hi; | |
6706 | break; | |
6707 | case ALTIVEC_BUILTIN_ST_INTERNAL_4si: | |
6708 | icode = CODE_FOR_altivec_stvx_4si; | |
6709 | break; | |
6710 | case ALTIVEC_BUILTIN_ST_INTERNAL_4sf: | |
6711 | icode = CODE_FOR_altivec_stvx_4sf; | |
6712 | break; | |
6713 | default: | |
6714 | *expandedp = false; | |
6715 | return NULL_RTX; | |
6716 | } | |
24408032 | 6717 | |
3a9b8c7e AH |
6718 | arg0 = TREE_VALUE (arglist); |
6719 | arg1 = TREE_VALUE (TREE_CHAIN (arglist)); | |
6720 | op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
6721 | op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); | |
6722 | mode0 = insn_data[icode].operand[0].mode; | |
6723 | mode1 = insn_data[icode].operand[1].mode; | |
f18c054f | 6724 | |
3a9b8c7e AH |
6725 | if (! (*insn_data[icode].operand[0].predicate) (op0, mode0)) |
6726 | op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0)); | |
6727 | if (! (*insn_data[icode].operand[1].predicate) (op1, mode1)) | |
6728 | op1 = copy_to_mode_reg (mode1, op1); | |
f18c054f | 6729 | |
3a9b8c7e AH |
6730 | pat = GEN_FCN (icode) (op0, op1); |
6731 | if (pat) | |
6732 | emit_insn (pat); | |
f18c054f | 6733 | |
3a9b8c7e AH |
6734 | *expandedp = true; |
6735 | return NULL_RTX; | |
6736 | } | |
f18c054f | 6737 | |
3a9b8c7e AH |
6738 | /* Expand the dst builtins. */ |
6739 | static rtx | |
f676971a | 6740 | altivec_expand_dst_builtin (tree exp, rtx target ATTRIBUTE_UNUSED, |
a2369ed3 | 6741 | bool *expandedp) |
3a9b8c7e AH |
6742 | { |
6743 | tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0); | |
6744 | tree arglist = TREE_OPERAND (exp, 1); | |
6745 | unsigned int fcode = DECL_FUNCTION_CODE (fndecl); | |
6746 | tree arg0, arg1, arg2; | |
6747 | enum machine_mode mode0, mode1, mode2; | |
7c3abc73 | 6748 | rtx pat, op0, op1, op2; |
3a9b8c7e | 6749 | struct builtin_description *d; |
a3170dc6 | 6750 | size_t i; |
f18c054f | 6751 | |
3a9b8c7e | 6752 | *expandedp = false; |
f18c054f | 6753 | |
3a9b8c7e AH |
6754 | /* Handle DST variants. */ |
6755 | d = (struct builtin_description *) bdesc_dst; | |
6756 | for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++) | |
6757 | if (d->code == fcode) | |
6758 | { | |
6759 | arg0 = TREE_VALUE (arglist); | |
6760 | arg1 = TREE_VALUE (TREE_CHAIN (arglist)); | |
6761 | arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist))); | |
6762 | op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
6763 | op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); | |
6764 | op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0); | |
6765 | mode0 = insn_data[d->icode].operand[0].mode; | |
6766 | mode1 = insn_data[d->icode].operand[1].mode; | |
6767 | mode2 = insn_data[d->icode].operand[2].mode; | |
24408032 | 6768 | |
3a9b8c7e AH |
6769 | /* Invalid arguments, bail out before generating bad rtl. */ |
6770 | if (arg0 == error_mark_node | |
6771 | || arg1 == error_mark_node | |
6772 | || arg2 == error_mark_node) | |
6773 | return const0_rtx; | |
f18c054f | 6774 | |
86e7df90 | 6775 | *expandedp = true; |
8bb418a3 | 6776 | STRIP_NOPS (arg2); |
3a9b8c7e AH |
6777 | if (TREE_CODE (arg2) != INTEGER_CST |
6778 | || TREE_INT_CST_LOW (arg2) & ~0x3) | |
6779 | { | |
6780 | error ("argument to `%s' must be a 2-bit unsigned literal", d->name); | |
6781 | return const0_rtx; | |
6782 | } | |
f18c054f | 6783 | |
3a9b8c7e | 6784 | if (! (*insn_data[d->icode].operand[0].predicate) (op0, mode0)) |
b4a62fa0 | 6785 | op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0)); |
3a9b8c7e AH |
6786 | if (! (*insn_data[d->icode].operand[1].predicate) (op1, mode1)) |
6787 | op1 = copy_to_mode_reg (mode1, op1); | |
24408032 | 6788 | |
3a9b8c7e AH |
6789 | pat = GEN_FCN (d->icode) (op0, op1, op2); |
6790 | if (pat != 0) | |
6791 | emit_insn (pat); | |
f18c054f | 6792 | |
3a9b8c7e AH |
6793 | return NULL_RTX; |
6794 | } | |
f18c054f | 6795 | |
3a9b8c7e AH |
6796 | return NULL_RTX; |
6797 | } | |
24408032 | 6798 | |
3a9b8c7e AH |
6799 | /* Expand the builtin in EXP and store the result in TARGET. Store |
6800 | true in *EXPANDEDP if we found a builtin to expand. */ | |
6801 | static rtx | |
a2369ed3 | 6802 | altivec_expand_builtin (tree exp, rtx target, bool *expandedp) |
3a9b8c7e AH |
6803 | { |
6804 | struct builtin_description *d; | |
6805 | struct builtin_description_predicates *dp; | |
6806 | size_t i; | |
6807 | enum insn_code icode; | |
6808 | tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0); | |
6809 | tree arglist = TREE_OPERAND (exp, 1); | |
7c3abc73 AH |
6810 | tree arg0; |
6811 | rtx op0, pat; | |
6812 | enum machine_mode tmode, mode0; | |
3a9b8c7e | 6813 | unsigned int fcode = DECL_FUNCTION_CODE (fndecl); |
0ac081f6 | 6814 | |
3a9b8c7e AH |
6815 | target = altivec_expand_ld_builtin (exp, target, expandedp); |
6816 | if (*expandedp) | |
6817 | return target; | |
0ac081f6 | 6818 | |
3a9b8c7e AH |
6819 | target = altivec_expand_st_builtin (exp, target, expandedp); |
6820 | if (*expandedp) | |
6821 | return target; | |
6822 | ||
6823 | target = altivec_expand_dst_builtin (exp, target, expandedp); | |
6824 | if (*expandedp) | |
6825 | return target; | |
6826 | ||
6827 | *expandedp = true; | |
95385cbb | 6828 | |
3a9b8c7e AH |
6829 | switch (fcode) |
6830 | { | |
6525c0e7 AH |
6831 | case ALTIVEC_BUILTIN_STVX: |
6832 | return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx, arglist); | |
6833 | case ALTIVEC_BUILTIN_STVEBX: | |
6834 | return altivec_expand_stv_builtin (CODE_FOR_altivec_stvebx, arglist); | |
6835 | case ALTIVEC_BUILTIN_STVEHX: | |
6836 | return altivec_expand_stv_builtin (CODE_FOR_altivec_stvehx, arglist); | |
6837 | case ALTIVEC_BUILTIN_STVEWX: | |
6838 | return altivec_expand_stv_builtin (CODE_FOR_altivec_stvewx, arglist); | |
6839 | case ALTIVEC_BUILTIN_STVXL: | |
6840 | return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl, arglist); | |
3a9b8c7e | 6841 | |
95385cbb AH |
6842 | case ALTIVEC_BUILTIN_MFVSCR: |
6843 | icode = CODE_FOR_altivec_mfvscr; | |
6844 | tmode = insn_data[icode].operand[0].mode; | |
6845 | ||
6846 | if (target == 0 | |
6847 | || GET_MODE (target) != tmode | |
6848 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
6849 | target = gen_reg_rtx (tmode); | |
f676971a | 6850 | |
95385cbb | 6851 | pat = GEN_FCN (icode) (target); |
0ac081f6 AH |
6852 | if (! pat) |
6853 | return 0; | |
6854 | emit_insn (pat); | |
95385cbb AH |
6855 | return target; |
6856 | ||
6857 | case ALTIVEC_BUILTIN_MTVSCR: | |
6858 | icode = CODE_FOR_altivec_mtvscr; | |
6859 | arg0 = TREE_VALUE (arglist); | |
6860 | op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
6861 | mode0 = insn_data[icode].operand[0].mode; | |
6862 | ||
6863 | /* If we got invalid arguments bail out before generating bad rtl. */ | |
6864 | if (arg0 == error_mark_node) | |
9a171fcd | 6865 | return const0_rtx; |
95385cbb AH |
6866 | |
6867 | if (! (*insn_data[icode].operand[0].predicate) (op0, mode0)) | |
6868 | op0 = copy_to_mode_reg (mode0, op0); | |
6869 | ||
6870 | pat = GEN_FCN (icode) (op0); | |
6871 | if (pat) | |
6872 | emit_insn (pat); | |
6873 | return NULL_RTX; | |
3a9b8c7e | 6874 | |
95385cbb AH |
6875 | case ALTIVEC_BUILTIN_DSSALL: |
6876 | emit_insn (gen_altivec_dssall ()); | |
6877 | return NULL_RTX; | |
6878 | ||
6879 | case ALTIVEC_BUILTIN_DSS: | |
6880 | icode = CODE_FOR_altivec_dss; | |
6881 | arg0 = TREE_VALUE (arglist); | |
8bb418a3 | 6882 | STRIP_NOPS (arg0); |
95385cbb AH |
6883 | op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); |
6884 | mode0 = insn_data[icode].operand[0].mode; | |
6885 | ||
6886 | /* If we got invalid arguments bail out before generating bad rtl. */ | |
6887 | if (arg0 == error_mark_node) | |
9a171fcd | 6888 | return const0_rtx; |
95385cbb | 6889 | |
b44140e7 AH |
6890 | if (TREE_CODE (arg0) != INTEGER_CST |
6891 | || TREE_INT_CST_LOW (arg0) & ~0x3) | |
6892 | { | |
6893 | error ("argument to dss must be a 2-bit unsigned literal"); | |
9a171fcd | 6894 | return const0_rtx; |
b44140e7 AH |
6895 | } |
6896 | ||
95385cbb AH |
6897 | if (! (*insn_data[icode].operand[0].predicate) (op0, mode0)) |
6898 | op0 = copy_to_mode_reg (mode0, op0); | |
6899 | ||
6900 | emit_insn (gen_altivec_dss (op0)); | |
0ac081f6 | 6901 | return NULL_RTX; |
f676971a | 6902 | |
8bb418a3 ZL |
6903 | case ALTIVEC_BUILTIN_COMPILETIME_ERROR: |
6904 | arg0 = TREE_VALUE (arglist); | |
97dc04b3 | 6905 | while (TREE_CODE (arg0) == NOP_EXPR || TREE_CODE (arg0) == ADDR_EXPR |
c4ad648e | 6906 | || TREE_CODE (arg0) == ARRAY_REF) |
8bb418a3 ZL |
6907 | arg0 = TREE_OPERAND (arg0, 0); |
6908 | error ("invalid parameter combination for `%s' AltiVec intrinsic", | |
6909 | TREE_STRING_POINTER (arg0)); | |
6910 | ||
6911 | return const0_rtx; | |
0ac081f6 | 6912 | } |
24408032 | 6913 | |
100c4561 AH |
6914 | /* Expand abs* operations. */ |
6915 | d = (struct builtin_description *) bdesc_abs; | |
ca7558fc | 6916 | for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++) |
100c4561 AH |
6917 | if (d->code == fcode) |
6918 | return altivec_expand_abs_builtin (d->icode, arglist, target); | |
6919 | ||
ae4b4a02 AH |
6920 | /* Expand the AltiVec predicates. */ |
6921 | dp = (struct builtin_description_predicates *) bdesc_altivec_preds; | |
ca7558fc | 6922 | for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, dp++) |
ae4b4a02 | 6923 | if (dp->code == fcode) |
c4ad648e AM |
6924 | return altivec_expand_predicate_builtin (dp->icode, dp->opcode, |
6925 | arglist, target); | |
ae4b4a02 | 6926 | |
6525c0e7 AH |
6927 | /* LV* are funky. We initialized them differently. */ |
6928 | switch (fcode) | |
6929 | { | |
6930 | case ALTIVEC_BUILTIN_LVSL: | |
b4a62fa0 | 6931 | return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsl, |
c4ad648e | 6932 | arglist, target); |
6525c0e7 | 6933 | case ALTIVEC_BUILTIN_LVSR: |
b4a62fa0 | 6934 | return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsr, |
c4ad648e | 6935 | arglist, target); |
6525c0e7 | 6936 | case ALTIVEC_BUILTIN_LVEBX: |
b4a62fa0 | 6937 | return altivec_expand_lv_builtin (CODE_FOR_altivec_lvebx, |
c4ad648e | 6938 | arglist, target); |
6525c0e7 | 6939 | case ALTIVEC_BUILTIN_LVEHX: |
b4a62fa0 | 6940 | return altivec_expand_lv_builtin (CODE_FOR_altivec_lvehx, |
c4ad648e | 6941 | arglist, target); |
6525c0e7 | 6942 | case ALTIVEC_BUILTIN_LVEWX: |
b4a62fa0 | 6943 | return altivec_expand_lv_builtin (CODE_FOR_altivec_lvewx, |
c4ad648e | 6944 | arglist, target); |
6525c0e7 | 6945 | case ALTIVEC_BUILTIN_LVXL: |
b4a62fa0 | 6946 | return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl, |
c4ad648e | 6947 | arglist, target); |
6525c0e7 | 6948 | case ALTIVEC_BUILTIN_LVX: |
b4a62fa0 | 6949 | return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx, |
c4ad648e | 6950 | arglist, target); |
6525c0e7 AH |
6951 | default: |
6952 | break; | |
6953 | /* Fall through. */ | |
6954 | } | |
95385cbb | 6955 | |
92898235 | 6956 | *expandedp = false; |
0ac081f6 AH |
6957 | return NULL_RTX; |
6958 | } | |
6959 | ||
a3170dc6 AH |
6960 | /* Binops that need to be initialized manually, but can be expanded |
6961 | automagically by rs6000_expand_binop_builtin. */ | |
6962 | static struct builtin_description bdesc_2arg_spe[] = | |
6963 | { | |
6964 | { 0, CODE_FOR_spe_evlddx, "__builtin_spe_evlddx", SPE_BUILTIN_EVLDDX }, | |
6965 | { 0, CODE_FOR_spe_evldwx, "__builtin_spe_evldwx", SPE_BUILTIN_EVLDWX }, | |
6966 | { 0, CODE_FOR_spe_evldhx, "__builtin_spe_evldhx", SPE_BUILTIN_EVLDHX }, | |
6967 | { 0, CODE_FOR_spe_evlwhex, "__builtin_spe_evlwhex", SPE_BUILTIN_EVLWHEX }, | |
6968 | { 0, CODE_FOR_spe_evlwhoux, "__builtin_spe_evlwhoux", SPE_BUILTIN_EVLWHOUX }, | |
6969 | { 0, CODE_FOR_spe_evlwhosx, "__builtin_spe_evlwhosx", SPE_BUILTIN_EVLWHOSX }, | |
6970 | { 0, CODE_FOR_spe_evlwwsplatx, "__builtin_spe_evlwwsplatx", SPE_BUILTIN_EVLWWSPLATX }, | |
6971 | { 0, CODE_FOR_spe_evlwhsplatx, "__builtin_spe_evlwhsplatx", SPE_BUILTIN_EVLWHSPLATX }, | |
6972 | { 0, CODE_FOR_spe_evlhhesplatx, "__builtin_spe_evlhhesplatx", SPE_BUILTIN_EVLHHESPLATX }, | |
6973 | { 0, CODE_FOR_spe_evlhhousplatx, "__builtin_spe_evlhhousplatx", SPE_BUILTIN_EVLHHOUSPLATX }, | |
6974 | { 0, CODE_FOR_spe_evlhhossplatx, "__builtin_spe_evlhhossplatx", SPE_BUILTIN_EVLHHOSSPLATX }, | |
6975 | { 0, CODE_FOR_spe_evldd, "__builtin_spe_evldd", SPE_BUILTIN_EVLDD }, | |
6976 | { 0, CODE_FOR_spe_evldw, "__builtin_spe_evldw", SPE_BUILTIN_EVLDW }, | |
6977 | { 0, CODE_FOR_spe_evldh, "__builtin_spe_evldh", SPE_BUILTIN_EVLDH }, | |
6978 | { 0, CODE_FOR_spe_evlwhe, "__builtin_spe_evlwhe", SPE_BUILTIN_EVLWHE }, | |
6979 | { 0, CODE_FOR_spe_evlwhou, "__builtin_spe_evlwhou", SPE_BUILTIN_EVLWHOU }, | |
6980 | { 0, CODE_FOR_spe_evlwhos, "__builtin_spe_evlwhos", SPE_BUILTIN_EVLWHOS }, | |
6981 | { 0, CODE_FOR_spe_evlwwsplat, "__builtin_spe_evlwwsplat", SPE_BUILTIN_EVLWWSPLAT }, | |
6982 | { 0, CODE_FOR_spe_evlwhsplat, "__builtin_spe_evlwhsplat", SPE_BUILTIN_EVLWHSPLAT }, | |
6983 | { 0, CODE_FOR_spe_evlhhesplat, "__builtin_spe_evlhhesplat", SPE_BUILTIN_EVLHHESPLAT }, | |
6984 | { 0, CODE_FOR_spe_evlhhousplat, "__builtin_spe_evlhhousplat", SPE_BUILTIN_EVLHHOUSPLAT }, | |
6985 | { 0, CODE_FOR_spe_evlhhossplat, "__builtin_spe_evlhhossplat", SPE_BUILTIN_EVLHHOSSPLAT } | |
6986 | }; | |
6987 | ||
6988 | /* Expand the builtin in EXP and store the result in TARGET. Store | |
6989 | true in *EXPANDEDP if we found a builtin to expand. | |
6990 | ||
6991 | This expands the SPE builtins that are not simple unary and binary | |
6992 | operations. */ | |
6993 | static rtx | |
a2369ed3 | 6994 | spe_expand_builtin (tree exp, rtx target, bool *expandedp) |
a3170dc6 AH |
6995 | { |
6996 | tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0); | |
6997 | tree arglist = TREE_OPERAND (exp, 1); | |
6998 | tree arg1, arg0; | |
6999 | unsigned int fcode = DECL_FUNCTION_CODE (fndecl); | |
7000 | enum insn_code icode; | |
7001 | enum machine_mode tmode, mode0; | |
7002 | rtx pat, op0; | |
7003 | struct builtin_description *d; | |
7004 | size_t i; | |
7005 | ||
7006 | *expandedp = true; | |
7007 | ||
7008 | /* Syntax check for a 5-bit unsigned immediate. */ | |
7009 | switch (fcode) | |
7010 | { | |
7011 | case SPE_BUILTIN_EVSTDD: | |
7012 | case SPE_BUILTIN_EVSTDH: | |
7013 | case SPE_BUILTIN_EVSTDW: | |
7014 | case SPE_BUILTIN_EVSTWHE: | |
7015 | case SPE_BUILTIN_EVSTWHO: | |
7016 | case SPE_BUILTIN_EVSTWWE: | |
7017 | case SPE_BUILTIN_EVSTWWO: | |
7018 | arg1 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist))); | |
7019 | if (TREE_CODE (arg1) != INTEGER_CST | |
7020 | || TREE_INT_CST_LOW (arg1) & ~0x1f) | |
7021 | { | |
7022 | error ("argument 2 must be a 5-bit unsigned literal"); | |
7023 | return const0_rtx; | |
7024 | } | |
7025 | break; | |
7026 | default: | |
7027 | break; | |
7028 | } | |
7029 | ||
00332c9f AH |
7030 | /* The evsplat*i instructions are not quite generic. */ |
7031 | switch (fcode) | |
7032 | { | |
7033 | case SPE_BUILTIN_EVSPLATFI: | |
7034 | return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplatfi, | |
7035 | arglist, target); | |
7036 | case SPE_BUILTIN_EVSPLATI: | |
7037 | return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplati, | |
7038 | arglist, target); | |
7039 | default: | |
7040 | break; | |
7041 | } | |
7042 | ||
a3170dc6 AH |
7043 | d = (struct builtin_description *) bdesc_2arg_spe; |
7044 | for (i = 0; i < ARRAY_SIZE (bdesc_2arg_spe); ++i, ++d) | |
7045 | if (d->code == fcode) | |
7046 | return rs6000_expand_binop_builtin (d->icode, arglist, target); | |
7047 | ||
7048 | d = (struct builtin_description *) bdesc_spe_predicates; | |
7049 | for (i = 0; i < ARRAY_SIZE (bdesc_spe_predicates); ++i, ++d) | |
7050 | if (d->code == fcode) | |
7051 | return spe_expand_predicate_builtin (d->icode, arglist, target); | |
7052 | ||
7053 | d = (struct builtin_description *) bdesc_spe_evsel; | |
7054 | for (i = 0; i < ARRAY_SIZE (bdesc_spe_evsel); ++i, ++d) | |
7055 | if (d->code == fcode) | |
7056 | return spe_expand_evsel_builtin (d->icode, arglist, target); | |
7057 | ||
7058 | switch (fcode) | |
7059 | { | |
7060 | case SPE_BUILTIN_EVSTDDX: | |
61bea3b0 | 7061 | return spe_expand_stv_builtin (CODE_FOR_spe_evstddx, arglist); |
a3170dc6 | 7062 | case SPE_BUILTIN_EVSTDHX: |
61bea3b0 | 7063 | return spe_expand_stv_builtin (CODE_FOR_spe_evstdhx, arglist); |
a3170dc6 | 7064 | case SPE_BUILTIN_EVSTDWX: |
61bea3b0 | 7065 | return spe_expand_stv_builtin (CODE_FOR_spe_evstdwx, arglist); |
a3170dc6 | 7066 | case SPE_BUILTIN_EVSTWHEX: |
61bea3b0 | 7067 | return spe_expand_stv_builtin (CODE_FOR_spe_evstwhex, arglist); |
a3170dc6 | 7068 | case SPE_BUILTIN_EVSTWHOX: |
61bea3b0 | 7069 | return spe_expand_stv_builtin (CODE_FOR_spe_evstwhox, arglist); |
a3170dc6 | 7070 | case SPE_BUILTIN_EVSTWWEX: |
61bea3b0 | 7071 | return spe_expand_stv_builtin (CODE_FOR_spe_evstwwex, arglist); |
a3170dc6 | 7072 | case SPE_BUILTIN_EVSTWWOX: |
61bea3b0 | 7073 | return spe_expand_stv_builtin (CODE_FOR_spe_evstwwox, arglist); |
a3170dc6 | 7074 | case SPE_BUILTIN_EVSTDD: |
61bea3b0 | 7075 | return spe_expand_stv_builtin (CODE_FOR_spe_evstdd, arglist); |
a3170dc6 | 7076 | case SPE_BUILTIN_EVSTDH: |
61bea3b0 | 7077 | return spe_expand_stv_builtin (CODE_FOR_spe_evstdh, arglist); |
a3170dc6 | 7078 | case SPE_BUILTIN_EVSTDW: |
61bea3b0 | 7079 | return spe_expand_stv_builtin (CODE_FOR_spe_evstdw, arglist); |
a3170dc6 | 7080 | case SPE_BUILTIN_EVSTWHE: |
61bea3b0 | 7081 | return spe_expand_stv_builtin (CODE_FOR_spe_evstwhe, arglist); |
a3170dc6 | 7082 | case SPE_BUILTIN_EVSTWHO: |
61bea3b0 | 7083 | return spe_expand_stv_builtin (CODE_FOR_spe_evstwho, arglist); |
a3170dc6 | 7084 | case SPE_BUILTIN_EVSTWWE: |
61bea3b0 | 7085 | return spe_expand_stv_builtin (CODE_FOR_spe_evstwwe, arglist); |
a3170dc6 | 7086 | case SPE_BUILTIN_EVSTWWO: |
61bea3b0 | 7087 | return spe_expand_stv_builtin (CODE_FOR_spe_evstwwo, arglist); |
a3170dc6 AH |
7088 | case SPE_BUILTIN_MFSPEFSCR: |
7089 | icode = CODE_FOR_spe_mfspefscr; | |
7090 | tmode = insn_data[icode].operand[0].mode; | |
7091 | ||
7092 | if (target == 0 | |
7093 | || GET_MODE (target) != tmode | |
7094 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
7095 | target = gen_reg_rtx (tmode); | |
f676971a | 7096 | |
a3170dc6 AH |
7097 | pat = GEN_FCN (icode) (target); |
7098 | if (! pat) | |
7099 | return 0; | |
7100 | emit_insn (pat); | |
7101 | return target; | |
7102 | case SPE_BUILTIN_MTSPEFSCR: | |
7103 | icode = CODE_FOR_spe_mtspefscr; | |
7104 | arg0 = TREE_VALUE (arglist); | |
7105 | op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
7106 | mode0 = insn_data[icode].operand[0].mode; | |
7107 | ||
7108 | if (arg0 == error_mark_node) | |
7109 | return const0_rtx; | |
7110 | ||
7111 | if (! (*insn_data[icode].operand[0].predicate) (op0, mode0)) | |
7112 | op0 = copy_to_mode_reg (mode0, op0); | |
7113 | ||
7114 | pat = GEN_FCN (icode) (op0); | |
7115 | if (pat) | |
7116 | emit_insn (pat); | |
7117 | return NULL_RTX; | |
7118 | default: | |
7119 | break; | |
7120 | } | |
7121 | ||
7122 | *expandedp = false; | |
7123 | return NULL_RTX; | |
7124 | } | |
7125 | ||
7126 | static rtx | |
a2369ed3 | 7127 | spe_expand_predicate_builtin (enum insn_code icode, tree arglist, rtx target) |
a3170dc6 AH |
7128 | { |
7129 | rtx pat, scratch, tmp; | |
7130 | tree form = TREE_VALUE (arglist); | |
7131 | tree arg0 = TREE_VALUE (TREE_CHAIN (arglist)); | |
7132 | tree arg1 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist))); | |
7133 | rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
7134 | rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); | |
7135 | enum machine_mode mode0 = insn_data[icode].operand[1].mode; | |
7136 | enum machine_mode mode1 = insn_data[icode].operand[2].mode; | |
7137 | int form_int; | |
7138 | enum rtx_code code; | |
7139 | ||
7140 | if (TREE_CODE (form) != INTEGER_CST) | |
7141 | { | |
7142 | error ("argument 1 of __builtin_spe_predicate must be a constant"); | |
7143 | return const0_rtx; | |
7144 | } | |
7145 | else | |
7146 | form_int = TREE_INT_CST_LOW (form); | |
7147 | ||
7148 | if (mode0 != mode1) | |
7149 | abort (); | |
7150 | ||
7151 | if (arg0 == error_mark_node || arg1 == error_mark_node) | |
7152 | return const0_rtx; | |
7153 | ||
7154 | if (target == 0 | |
7155 | || GET_MODE (target) != SImode | |
7156 | || ! (*insn_data[icode].operand[0].predicate) (target, SImode)) | |
7157 | target = gen_reg_rtx (SImode); | |
7158 | ||
7159 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) | |
7160 | op0 = copy_to_mode_reg (mode0, op0); | |
7161 | if (! (*insn_data[icode].operand[2].predicate) (op1, mode1)) | |
7162 | op1 = copy_to_mode_reg (mode1, op1); | |
7163 | ||
7164 | scratch = gen_reg_rtx (CCmode); | |
7165 | ||
7166 | pat = GEN_FCN (icode) (scratch, op0, op1); | |
7167 | if (! pat) | |
7168 | return const0_rtx; | |
7169 | emit_insn (pat); | |
7170 | ||
7171 | /* There are 4 variants for each predicate: _any_, _all_, _upper_, | |
7172 | _lower_. We use one compare, but look in different bits of the | |
7173 | CR for each variant. | |
7174 | ||
7175 | There are 2 elements in each SPE simd type (upper/lower). The CR | |
7176 | bits are set as follows: | |
7177 | ||
7178 | BIT0 | BIT 1 | BIT 2 | BIT 3 | |
7179 | U | L | (U | L) | (U & L) | |
7180 | ||
7181 | So, for an "all" relationship, BIT 3 would be set. | |
7182 | For an "any" relationship, BIT 2 would be set. Etc. | |
7183 | ||
7184 | Following traditional nomenclature, these bits map to: | |
7185 | ||
7186 | BIT0 | BIT 1 | BIT 2 | BIT 3 | |
7187 | LT | GT | EQ | OV | |
7188 | ||
7189 | Later, we will generate rtl to look in the LT/EQ/EQ/OV bits. | |
7190 | */ | |
7191 | ||
7192 | switch (form_int) | |
7193 | { | |
7194 | /* All variant. OV bit. */ | |
7195 | case 0: | |
7196 | /* We need to get to the OV bit, which is the ORDERED bit. We | |
7197 | could generate (ordered:SI (reg:CC xx) (const_int 0)), but | |
7198 | that's ugly and will trigger a validate_condition_mode abort. | |
7199 | So let's just use another pattern. */ | |
7200 | emit_insn (gen_move_from_CR_ov_bit (target, scratch)); | |
7201 | return target; | |
7202 | /* Any variant. EQ bit. */ | |
7203 | case 1: | |
7204 | code = EQ; | |
7205 | break; | |
7206 | /* Upper variant. LT bit. */ | |
7207 | case 2: | |
7208 | code = LT; | |
7209 | break; | |
7210 | /* Lower variant. GT bit. */ | |
7211 | case 3: | |
7212 | code = GT; | |
7213 | break; | |
7214 | default: | |
7215 | error ("argument 1 of __builtin_spe_predicate is out of range"); | |
7216 | return const0_rtx; | |
7217 | } | |
7218 | ||
7219 | tmp = gen_rtx_fmt_ee (code, SImode, scratch, const0_rtx); | |
7220 | emit_move_insn (target, tmp); | |
7221 | ||
7222 | return target; | |
7223 | } | |
7224 | ||
7225 | /* The evsel builtins look like this: | |
7226 | ||
7227 | e = __builtin_spe_evsel_OP (a, b, c, d); | |
7228 | ||
7229 | and work like this: | |
7230 | ||
7231 | e[upper] = a[upper] *OP* b[upper] ? c[upper] : d[upper]; | |
7232 | e[lower] = a[lower] *OP* b[lower] ? c[lower] : d[lower]; | |
7233 | */ | |
7234 | ||
7235 | static rtx | |
a2369ed3 | 7236 | spe_expand_evsel_builtin (enum insn_code icode, tree arglist, rtx target) |
a3170dc6 AH |
7237 | { |
7238 | rtx pat, scratch; | |
7239 | tree arg0 = TREE_VALUE (arglist); | |
7240 | tree arg1 = TREE_VALUE (TREE_CHAIN (arglist)); | |
7241 | tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist))); | |
7242 | tree arg3 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (TREE_CHAIN (arglist)))); | |
7243 | rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
7244 | rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); | |
7245 | rtx op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0); | |
7246 | rtx op3 = expand_expr (arg3, NULL_RTX, VOIDmode, 0); | |
7247 | enum machine_mode mode0 = insn_data[icode].operand[1].mode; | |
7248 | enum machine_mode mode1 = insn_data[icode].operand[2].mode; | |
7249 | ||
7250 | if (mode0 != mode1) | |
7251 | abort (); | |
7252 | ||
7253 | if (arg0 == error_mark_node || arg1 == error_mark_node | |
7254 | || arg2 == error_mark_node || arg3 == error_mark_node) | |
7255 | return const0_rtx; | |
7256 | ||
7257 | if (target == 0 | |
7258 | || GET_MODE (target) != mode0 | |
7259 | || ! (*insn_data[icode].operand[0].predicate) (target, mode0)) | |
7260 | target = gen_reg_rtx (mode0); | |
7261 | ||
7262 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) | |
7263 | op0 = copy_to_mode_reg (mode0, op0); | |
7264 | if (! (*insn_data[icode].operand[1].predicate) (op1, mode1)) | |
7265 | op1 = copy_to_mode_reg (mode0, op1); | |
7266 | if (! (*insn_data[icode].operand[1].predicate) (op2, mode1)) | |
7267 | op2 = copy_to_mode_reg (mode0, op2); | |
7268 | if (! (*insn_data[icode].operand[1].predicate) (op3, mode1)) | |
7269 | op3 = copy_to_mode_reg (mode0, op3); | |
7270 | ||
7271 | /* Generate the compare. */ | |
7272 | scratch = gen_reg_rtx (CCmode); | |
7273 | pat = GEN_FCN (icode) (scratch, op0, op1); | |
7274 | if (! pat) | |
7275 | return const0_rtx; | |
7276 | emit_insn (pat); | |
7277 | ||
7278 | if (mode0 == V2SImode) | |
7279 | emit_insn (gen_spe_evsel (target, op2, op3, scratch)); | |
7280 | else | |
7281 | emit_insn (gen_spe_evsel_fs (target, op2, op3, scratch)); | |
7282 | ||
7283 | return target; | |
7284 | } | |
7285 | ||
0ac081f6 AH |
7286 | /* Expand an expression EXP that calls a built-in function, |
7287 | with result going to TARGET if that's convenient | |
7288 | (and in mode MODE if that's convenient). | |
7289 | SUBTARGET may be used as the target for computing one of EXP's operands. | |
7290 | IGNORE is nonzero if the value is to be ignored. */ | |
7291 | ||
7292 | static rtx | |
a2369ed3 | 7293 | rs6000_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED, |
c4ad648e AM |
7294 | enum machine_mode mode ATTRIBUTE_UNUSED, |
7295 | int ignore ATTRIBUTE_UNUSED) | |
0ac081f6 | 7296 | { |
92898235 AH |
7297 | tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0); |
7298 | tree arglist = TREE_OPERAND (exp, 1); | |
7299 | unsigned int fcode = DECL_FUNCTION_CODE (fndecl); | |
7300 | struct builtin_description *d; | |
7301 | size_t i; | |
7302 | rtx ret; | |
7303 | bool success; | |
f676971a | 7304 | |
7ccf35ed DN |
7305 | if (fcode == ALTIVEC_BUILTIN_MASK_FOR_LOAD |
7306 | || fcode == ALTIVEC_BUILTIN_MASK_FOR_STORE) | |
7307 | { | |
7308 | int icode = (int) CODE_FOR_altivec_lvsr; | |
7309 | enum machine_mode tmode = insn_data[icode].operand[0].mode; | |
7310 | enum machine_mode mode = insn_data[icode].operand[1].mode; | |
7311 | tree arg; | |
7312 | rtx op, addr, pat; | |
7313 | ||
7314 | if (!TARGET_ALTIVEC) | |
7315 | abort (); | |
7316 | ||
7317 | arg = TREE_VALUE (arglist); | |
7318 | if (TREE_CODE (TREE_TYPE (arg)) != POINTER_TYPE) | |
7319 | abort (); | |
7320 | op = expand_expr (arg, NULL_RTX, Pmode, EXPAND_NORMAL); | |
7321 | addr = memory_address (mode, op); | |
7322 | if (fcode == ALTIVEC_BUILTIN_MASK_FOR_STORE) | |
7323 | op = addr; | |
7324 | else | |
7325 | { | |
7326 | /* For the load case need to negate the address. */ | |
7327 | op = gen_reg_rtx (GET_MODE (addr)); | |
7328 | emit_insn (gen_rtx_SET (VOIDmode, op, | |
7329 | gen_rtx_NEG (GET_MODE (addr), addr))); | |
c4ad648e | 7330 | } |
7ccf35ed DN |
7331 | op = gen_rtx_MEM (mode, op); |
7332 | ||
7333 | if (target == 0 | |
7334 | || GET_MODE (target) != tmode | |
7335 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
7336 | target = gen_reg_rtx (tmode); | |
7337 | ||
7338 | /*pat = gen_altivec_lvsr (target, op);*/ | |
7339 | pat = GEN_FCN (icode) (target, op); | |
7340 | if (!pat) | |
7341 | return 0; | |
7342 | emit_insn (pat); | |
7343 | ||
7344 | return target; | |
7345 | } | |
7346 | ||
0ac081f6 | 7347 | if (TARGET_ALTIVEC) |
92898235 AH |
7348 | { |
7349 | ret = altivec_expand_builtin (exp, target, &success); | |
7350 | ||
a3170dc6 AH |
7351 | if (success) |
7352 | return ret; | |
7353 | } | |
7354 | if (TARGET_SPE) | |
7355 | { | |
7356 | ret = spe_expand_builtin (exp, target, &success); | |
7357 | ||
92898235 AH |
7358 | if (success) |
7359 | return ret; | |
7360 | } | |
7361 | ||
0559cc77 DE |
7362 | if (TARGET_ALTIVEC || TARGET_SPE) |
7363 | { | |
7364 | /* Handle simple unary operations. */ | |
7365 | d = (struct builtin_description *) bdesc_1arg; | |
7366 | for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++) | |
7367 | if (d->code == fcode) | |
7368 | return rs6000_expand_unop_builtin (d->icode, arglist, target); | |
7369 | ||
7370 | /* Handle simple binary operations. */ | |
7371 | d = (struct builtin_description *) bdesc_2arg; | |
7372 | for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++) | |
7373 | if (d->code == fcode) | |
7374 | return rs6000_expand_binop_builtin (d->icode, arglist, target); | |
7375 | ||
7376 | /* Handle simple ternary operations. */ | |
7377 | d = (struct builtin_description *) bdesc_3arg; | |
7378 | for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++) | |
7379 | if (d->code == fcode) | |
7380 | return rs6000_expand_ternop_builtin (d->icode, arglist, target); | |
7381 | } | |
0ac081f6 AH |
7382 | |
7383 | abort (); | |
92898235 | 7384 | return NULL_RTX; |
0ac081f6 AH |
7385 | } |
7386 | ||
7c62e993 PB |
7387 | static tree |
7388 | build_opaque_vector_type (tree node, int nunits) | |
7389 | { | |
7390 | node = copy_node (node); | |
7391 | TYPE_MAIN_VARIANT (node) = node; | |
7392 | return build_vector_type (node, nunits); | |
7393 | } | |
7394 | ||
0ac081f6 | 7395 | static void |
863d938c | 7396 | rs6000_init_builtins (void) |
0ac081f6 | 7397 | { |
4a5eab38 PB |
7398 | V2SI_type_node = build_vector_type (intSI_type_node, 2); |
7399 | V2SF_type_node = build_vector_type (float_type_node, 2); | |
7400 | V4HI_type_node = build_vector_type (intHI_type_node, 4); | |
7401 | V4SI_type_node = build_vector_type (intSI_type_node, 4); | |
7402 | V4SF_type_node = build_vector_type (float_type_node, 4); | |
7e463bda | 7403 | V8HI_type_node = build_vector_type (intHI_type_node, 8); |
4a5eab38 PB |
7404 | V16QI_type_node = build_vector_type (intQI_type_node, 16); |
7405 | ||
7406 | unsigned_V16QI_type_node = build_vector_type (unsigned_intQI_type_node, 16); | |
7407 | unsigned_V8HI_type_node = build_vector_type (unsigned_intHI_type_node, 8); | |
7408 | unsigned_V4SI_type_node = build_vector_type (unsigned_intSI_type_node, 4); | |
7409 | ||
7c62e993 PB |
7410 | opaque_V2SF_type_node = build_opaque_vector_type (float_type_node, 2); |
7411 | opaque_V2SI_type_node = build_opaque_vector_type (intSI_type_node, 2); | |
6035d635 | 7412 | opaque_p_V2SI_type_node = build_pointer_type (opaque_V2SI_type_node); |
3fdaa45a | 7413 | |
8bb418a3 ZL |
7414 | /* The 'vector bool ...' types must be kept distinct from 'vector unsigned ...' |
7415 | types, especially in C++ land. Similarly, 'vector pixel' is distinct from | |
7416 | 'vector unsigned short'. */ | |
7417 | ||
8dd16ecc NS |
7418 | bool_char_type_node = build_distinct_type_copy (unsigned_intQI_type_node); |
7419 | bool_short_type_node = build_distinct_type_copy (unsigned_intHI_type_node); | |
7420 | bool_int_type_node = build_distinct_type_copy (unsigned_intSI_type_node); | |
7421 | pixel_type_node = build_distinct_type_copy (unsigned_intHI_type_node); | |
8bb418a3 ZL |
7422 | |
7423 | (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL, | |
7424 | get_identifier ("__bool char"), | |
7425 | bool_char_type_node)); | |
7426 | (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL, | |
7427 | get_identifier ("__bool short"), | |
7428 | bool_short_type_node)); | |
7429 | (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL, | |
7430 | get_identifier ("__bool int"), | |
7431 | bool_int_type_node)); | |
7432 | (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL, | |
7433 | get_identifier ("__pixel"), | |
7434 | pixel_type_node)); | |
7435 | ||
4a5eab38 PB |
7436 | bool_V16QI_type_node = build_vector_type (bool_char_type_node, 16); |
7437 | bool_V8HI_type_node = build_vector_type (bool_short_type_node, 8); | |
7438 | bool_V4SI_type_node = build_vector_type (bool_int_type_node, 4); | |
7439 | pixel_V8HI_type_node = build_vector_type (pixel_type_node, 8); | |
8bb418a3 ZL |
7440 | |
7441 | (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL, | |
7442 | get_identifier ("__vector unsigned char"), | |
7443 | unsigned_V16QI_type_node)); | |
7444 | (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL, | |
7445 | get_identifier ("__vector signed char"), | |
7446 | V16QI_type_node)); | |
7447 | (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL, | |
7448 | get_identifier ("__vector __bool char"), | |
7449 | bool_V16QI_type_node)); | |
7450 | ||
7451 | (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL, | |
7452 | get_identifier ("__vector unsigned short"), | |
7453 | unsigned_V8HI_type_node)); | |
7454 | (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL, | |
7455 | get_identifier ("__vector signed short"), | |
7456 | V8HI_type_node)); | |
7457 | (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL, | |
7458 | get_identifier ("__vector __bool short"), | |
7459 | bool_V8HI_type_node)); | |
7460 | ||
7461 | (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL, | |
7462 | get_identifier ("__vector unsigned int"), | |
7463 | unsigned_V4SI_type_node)); | |
7464 | (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL, | |
7465 | get_identifier ("__vector signed int"), | |
7466 | V4SI_type_node)); | |
7467 | (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL, | |
7468 | get_identifier ("__vector __bool int"), | |
7469 | bool_V4SI_type_node)); | |
7470 | ||
7471 | (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL, | |
7472 | get_identifier ("__vector float"), | |
7473 | V4SF_type_node)); | |
7474 | (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL, | |
7475 | get_identifier ("__vector __pixel"), | |
7476 | pixel_V8HI_type_node)); | |
7477 | ||
a3170dc6 | 7478 | if (TARGET_SPE) |
3fdaa45a | 7479 | spe_init_builtins (); |
0ac081f6 AH |
7480 | if (TARGET_ALTIVEC) |
7481 | altivec_init_builtins (); | |
0559cc77 DE |
7482 | if (TARGET_ALTIVEC || TARGET_SPE) |
7483 | rs6000_common_init_builtins (); | |
0ac081f6 AH |
7484 | } |
7485 | ||
a3170dc6 AH |
7486 | /* Search through a set of builtins and enable the mask bits. |
7487 | DESC is an array of builtins. | |
b6d08ca1 | 7488 | SIZE is the total number of builtins. |
a3170dc6 AH |
7489 | START is the builtin enum at which to start. |
7490 | END is the builtin enum at which to end. */ | |
0ac081f6 | 7491 | static void |
a2369ed3 | 7492 | enable_mask_for_builtins (struct builtin_description *desc, int size, |
f676971a | 7493 | enum rs6000_builtins start, |
a2369ed3 | 7494 | enum rs6000_builtins end) |
a3170dc6 AH |
7495 | { |
7496 | int i; | |
7497 | ||
7498 | for (i = 0; i < size; ++i) | |
7499 | if (desc[i].code == start) | |
7500 | break; | |
7501 | ||
7502 | if (i == size) | |
7503 | return; | |
7504 | ||
7505 | for (; i < size; ++i) | |
7506 | { | |
7507 | /* Flip all the bits on. */ | |
7508 | desc[i].mask = target_flags; | |
7509 | if (desc[i].code == end) | |
7510 | break; | |
7511 | } | |
7512 | } | |
7513 | ||
7514 | static void | |
863d938c | 7515 | spe_init_builtins (void) |
0ac081f6 | 7516 | { |
a3170dc6 AH |
7517 | tree endlink = void_list_node; |
7518 | tree puint_type_node = build_pointer_type (unsigned_type_node); | |
7519 | tree pushort_type_node = build_pointer_type (short_unsigned_type_node); | |
ae4b4a02 | 7520 | struct builtin_description *d; |
0ac081f6 AH |
7521 | size_t i; |
7522 | ||
a3170dc6 AH |
7523 | tree v2si_ftype_4_v2si |
7524 | = build_function_type | |
3fdaa45a AH |
7525 | (opaque_V2SI_type_node, |
7526 | tree_cons (NULL_TREE, opaque_V2SI_type_node, | |
7527 | tree_cons (NULL_TREE, opaque_V2SI_type_node, | |
7528 | tree_cons (NULL_TREE, opaque_V2SI_type_node, | |
7529 | tree_cons (NULL_TREE, opaque_V2SI_type_node, | |
a3170dc6 AH |
7530 | endlink))))); |
7531 | ||
7532 | tree v2sf_ftype_4_v2sf | |
7533 | = build_function_type | |
3fdaa45a AH |
7534 | (opaque_V2SF_type_node, |
7535 | tree_cons (NULL_TREE, opaque_V2SF_type_node, | |
7536 | tree_cons (NULL_TREE, opaque_V2SF_type_node, | |
7537 | tree_cons (NULL_TREE, opaque_V2SF_type_node, | |
7538 | tree_cons (NULL_TREE, opaque_V2SF_type_node, | |
a3170dc6 AH |
7539 | endlink))))); |
7540 | ||
7541 | tree int_ftype_int_v2si_v2si | |
7542 | = build_function_type | |
7543 | (integer_type_node, | |
7544 | tree_cons (NULL_TREE, integer_type_node, | |
3fdaa45a AH |
7545 | tree_cons (NULL_TREE, opaque_V2SI_type_node, |
7546 | tree_cons (NULL_TREE, opaque_V2SI_type_node, | |
a3170dc6 AH |
7547 | endlink)))); |
7548 | ||
7549 | tree int_ftype_int_v2sf_v2sf | |
7550 | = build_function_type | |
7551 | (integer_type_node, | |
7552 | tree_cons (NULL_TREE, integer_type_node, | |
3fdaa45a AH |
7553 | tree_cons (NULL_TREE, opaque_V2SF_type_node, |
7554 | tree_cons (NULL_TREE, opaque_V2SF_type_node, | |
a3170dc6 AH |
7555 | endlink)))); |
7556 | ||
7557 | tree void_ftype_v2si_puint_int | |
7558 | = build_function_type (void_type_node, | |
3fdaa45a | 7559 | tree_cons (NULL_TREE, opaque_V2SI_type_node, |
a3170dc6 AH |
7560 | tree_cons (NULL_TREE, puint_type_node, |
7561 | tree_cons (NULL_TREE, | |
7562 | integer_type_node, | |
7563 | endlink)))); | |
7564 | ||
7565 | tree void_ftype_v2si_puint_char | |
7566 | = build_function_type (void_type_node, | |
3fdaa45a | 7567 | tree_cons (NULL_TREE, opaque_V2SI_type_node, |
a3170dc6 AH |
7568 | tree_cons (NULL_TREE, puint_type_node, |
7569 | tree_cons (NULL_TREE, | |
7570 | char_type_node, | |
7571 | endlink)))); | |
7572 | ||
7573 | tree void_ftype_v2si_pv2si_int | |
7574 | = build_function_type (void_type_node, | |
3fdaa45a | 7575 | tree_cons (NULL_TREE, opaque_V2SI_type_node, |
6035d635 | 7576 | tree_cons (NULL_TREE, opaque_p_V2SI_type_node, |
a3170dc6 AH |
7577 | tree_cons (NULL_TREE, |
7578 | integer_type_node, | |
7579 | endlink)))); | |
7580 | ||
7581 | tree void_ftype_v2si_pv2si_char | |
7582 | = build_function_type (void_type_node, | |
3fdaa45a | 7583 | tree_cons (NULL_TREE, opaque_V2SI_type_node, |
6035d635 | 7584 | tree_cons (NULL_TREE, opaque_p_V2SI_type_node, |
a3170dc6 AH |
7585 | tree_cons (NULL_TREE, |
7586 | char_type_node, | |
7587 | endlink)))); | |
7588 | ||
7589 | tree void_ftype_int | |
7590 | = build_function_type (void_type_node, | |
7591 | tree_cons (NULL_TREE, integer_type_node, endlink)); | |
7592 | ||
7593 | tree int_ftype_void | |
36e8d515 | 7594 | = build_function_type (integer_type_node, endlink); |
a3170dc6 AH |
7595 | |
7596 | tree v2si_ftype_pv2si_int | |
3fdaa45a | 7597 | = build_function_type (opaque_V2SI_type_node, |
6035d635 | 7598 | tree_cons (NULL_TREE, opaque_p_V2SI_type_node, |
a3170dc6 AH |
7599 | tree_cons (NULL_TREE, integer_type_node, |
7600 | endlink))); | |
7601 | ||
7602 | tree v2si_ftype_puint_int | |
3fdaa45a | 7603 | = build_function_type (opaque_V2SI_type_node, |
a3170dc6 AH |
7604 | tree_cons (NULL_TREE, puint_type_node, |
7605 | tree_cons (NULL_TREE, integer_type_node, | |
7606 | endlink))); | |
7607 | ||
7608 | tree v2si_ftype_pushort_int | |
3fdaa45a | 7609 | = build_function_type (opaque_V2SI_type_node, |
a3170dc6 AH |
7610 | tree_cons (NULL_TREE, pushort_type_node, |
7611 | tree_cons (NULL_TREE, integer_type_node, | |
7612 | endlink))); | |
7613 | ||
00332c9f AH |
7614 | tree v2si_ftype_signed_char |
7615 | = build_function_type (opaque_V2SI_type_node, | |
7616 | tree_cons (NULL_TREE, signed_char_type_node, | |
7617 | endlink)); | |
7618 | ||
a3170dc6 AH |
7619 | /* The initialization of the simple binary and unary builtins is |
7620 | done in rs6000_common_init_builtins, but we have to enable the | |
7621 | mask bits here manually because we have run out of `target_flags' | |
7622 | bits. We really need to redesign this mask business. */ | |
7623 | ||
7624 | enable_mask_for_builtins ((struct builtin_description *) bdesc_2arg, | |
7625 | ARRAY_SIZE (bdesc_2arg), | |
7626 | SPE_BUILTIN_EVADDW, | |
7627 | SPE_BUILTIN_EVXOR); | |
7628 | enable_mask_for_builtins ((struct builtin_description *) bdesc_1arg, | |
7629 | ARRAY_SIZE (bdesc_1arg), | |
7630 | SPE_BUILTIN_EVABS, | |
7631 | SPE_BUILTIN_EVSUBFUSIAAW); | |
7632 | enable_mask_for_builtins ((struct builtin_description *) bdesc_spe_predicates, | |
7633 | ARRAY_SIZE (bdesc_spe_predicates), | |
7634 | SPE_BUILTIN_EVCMPEQ, | |
7635 | SPE_BUILTIN_EVFSTSTLT); | |
7636 | enable_mask_for_builtins ((struct builtin_description *) bdesc_spe_evsel, | |
7637 | ARRAY_SIZE (bdesc_spe_evsel), | |
7638 | SPE_BUILTIN_EVSEL_CMPGTS, | |
7639 | SPE_BUILTIN_EVSEL_FSTSTEQ); | |
7640 | ||
36252949 AH |
7641 | (*lang_hooks.decls.pushdecl) |
7642 | (build_decl (TYPE_DECL, get_identifier ("__ev64_opaque__"), | |
7643 | opaque_V2SI_type_node)); | |
7644 | ||
a3170dc6 | 7645 | /* Initialize irregular SPE builtins. */ |
f676971a | 7646 | |
a3170dc6 AH |
7647 | def_builtin (target_flags, "__builtin_spe_mtspefscr", void_ftype_int, SPE_BUILTIN_MTSPEFSCR); |
7648 | def_builtin (target_flags, "__builtin_spe_mfspefscr", int_ftype_void, SPE_BUILTIN_MFSPEFSCR); | |
7649 | def_builtin (target_flags, "__builtin_spe_evstddx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDDX); | |
7650 | def_builtin (target_flags, "__builtin_spe_evstdhx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDHX); | |
7651 | def_builtin (target_flags, "__builtin_spe_evstdwx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDWX); | |
7652 | def_builtin (target_flags, "__builtin_spe_evstwhex", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWHEX); | |
7653 | def_builtin (target_flags, "__builtin_spe_evstwhox", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWHOX); | |
7654 | def_builtin (target_flags, "__builtin_spe_evstwwex", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWWEX); | |
7655 | def_builtin (target_flags, "__builtin_spe_evstwwox", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWWOX); | |
7656 | def_builtin (target_flags, "__builtin_spe_evstdd", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDD); | |
7657 | def_builtin (target_flags, "__builtin_spe_evstdh", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDH); | |
7658 | def_builtin (target_flags, "__builtin_spe_evstdw", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDW); | |
7659 | def_builtin (target_flags, "__builtin_spe_evstwhe", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWHE); | |
7660 | def_builtin (target_flags, "__builtin_spe_evstwho", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWHO); | |
7661 | def_builtin (target_flags, "__builtin_spe_evstwwe", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWWE); | |
7662 | def_builtin (target_flags, "__builtin_spe_evstwwo", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWWO); | |
00332c9f AH |
7663 | def_builtin (target_flags, "__builtin_spe_evsplatfi", v2si_ftype_signed_char, SPE_BUILTIN_EVSPLATFI); |
7664 | def_builtin (target_flags, "__builtin_spe_evsplati", v2si_ftype_signed_char, SPE_BUILTIN_EVSPLATI); | |
a3170dc6 AH |
7665 | |
7666 | /* Loads. */ | |
7667 | def_builtin (target_flags, "__builtin_spe_evlddx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDDX); | |
7668 | def_builtin (target_flags, "__builtin_spe_evldwx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDWX); | |
7669 | def_builtin (target_flags, "__builtin_spe_evldhx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDHX); | |
7670 | def_builtin (target_flags, "__builtin_spe_evlwhex", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHEX); | |
7671 | def_builtin (target_flags, "__builtin_spe_evlwhoux", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOUX); | |
7672 | def_builtin (target_flags, "__builtin_spe_evlwhosx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOSX); | |
7673 | def_builtin (target_flags, "__builtin_spe_evlwwsplatx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWWSPLATX); | |
7674 | def_builtin (target_flags, "__builtin_spe_evlwhsplatx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHSPLATX); | |
7675 | def_builtin (target_flags, "__builtin_spe_evlhhesplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHESPLATX); | |
7676 | def_builtin (target_flags, "__builtin_spe_evlhhousplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOUSPLATX); | |
7677 | def_builtin (target_flags, "__builtin_spe_evlhhossplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOSSPLATX); | |
7678 | def_builtin (target_flags, "__builtin_spe_evldd", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDD); | |
7679 | def_builtin (target_flags, "__builtin_spe_evldw", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDW); | |
7680 | def_builtin (target_flags, "__builtin_spe_evldh", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDH); | |
7681 | def_builtin (target_flags, "__builtin_spe_evlhhesplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHESPLAT); | |
7682 | def_builtin (target_flags, "__builtin_spe_evlhhossplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOSSPLAT); | |
7683 | def_builtin (target_flags, "__builtin_spe_evlhhousplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOUSPLAT); | |
7684 | def_builtin (target_flags, "__builtin_spe_evlwhe", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHE); | |
7685 | def_builtin (target_flags, "__builtin_spe_evlwhos", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOS); | |
7686 | def_builtin (target_flags, "__builtin_spe_evlwhou", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOU); | |
7687 | def_builtin (target_flags, "__builtin_spe_evlwhsplat", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHSPLAT); | |
7688 | def_builtin (target_flags, "__builtin_spe_evlwwsplat", v2si_ftype_puint_int, SPE_BUILTIN_EVLWWSPLAT); | |
7689 | ||
7690 | /* Predicates. */ | |
7691 | d = (struct builtin_description *) bdesc_spe_predicates; | |
7692 | for (i = 0; i < ARRAY_SIZE (bdesc_spe_predicates); ++i, d++) | |
7693 | { | |
7694 | tree type; | |
7695 | ||
7696 | switch (insn_data[d->icode].operand[1].mode) | |
7697 | { | |
7698 | case V2SImode: | |
7699 | type = int_ftype_int_v2si_v2si; | |
7700 | break; | |
7701 | case V2SFmode: | |
7702 | type = int_ftype_int_v2sf_v2sf; | |
7703 | break; | |
7704 | default: | |
7705 | abort (); | |
7706 | } | |
7707 | ||
7708 | def_builtin (d->mask, d->name, type, d->code); | |
7709 | } | |
7710 | ||
7711 | /* Evsel predicates. */ | |
7712 | d = (struct builtin_description *) bdesc_spe_evsel; | |
7713 | for (i = 0; i < ARRAY_SIZE (bdesc_spe_evsel); ++i, d++) | |
7714 | { | |
7715 | tree type; | |
7716 | ||
7717 | switch (insn_data[d->icode].operand[1].mode) | |
7718 | { | |
7719 | case V2SImode: | |
7720 | type = v2si_ftype_4_v2si; | |
7721 | break; | |
7722 | case V2SFmode: | |
7723 | type = v2sf_ftype_4_v2sf; | |
7724 | break; | |
7725 | default: | |
7726 | abort (); | |
7727 | } | |
7728 | ||
7729 | def_builtin (d->mask, d->name, type, d->code); | |
7730 | } | |
7731 | } | |
7732 | ||
7733 | static void | |
863d938c | 7734 | altivec_init_builtins (void) |
a3170dc6 AH |
7735 | { |
7736 | struct builtin_description *d; | |
7737 | struct builtin_description_predicates *dp; | |
7738 | size_t i; | |
7739 | tree pfloat_type_node = build_pointer_type (float_type_node); | |
7740 | tree pint_type_node = build_pointer_type (integer_type_node); | |
7741 | tree pshort_type_node = build_pointer_type (short_integer_type_node); | |
7742 | tree pchar_type_node = build_pointer_type (char_type_node); | |
7743 | ||
7744 | tree pvoid_type_node = build_pointer_type (void_type_node); | |
7745 | ||
0dbc3651 ZW |
7746 | tree pcfloat_type_node = build_pointer_type (build_qualified_type (float_type_node, TYPE_QUAL_CONST)); |
7747 | tree pcint_type_node = build_pointer_type (build_qualified_type (integer_type_node, TYPE_QUAL_CONST)); | |
7748 | tree pcshort_type_node = build_pointer_type (build_qualified_type (short_integer_type_node, TYPE_QUAL_CONST)); | |
7749 | tree pcchar_type_node = build_pointer_type (build_qualified_type (char_type_node, TYPE_QUAL_CONST)); | |
7750 | ||
7751 | tree pcvoid_type_node = build_pointer_type (build_qualified_type (void_type_node, TYPE_QUAL_CONST)); | |
7752 | ||
a3170dc6 AH |
7753 | tree int_ftype_int_v4si_v4si |
7754 | = build_function_type_list (integer_type_node, | |
7755 | integer_type_node, V4SI_type_node, | |
7756 | V4SI_type_node, NULL_TREE); | |
0dbc3651 ZW |
7757 | tree v4sf_ftype_pcfloat |
7758 | = build_function_type_list (V4SF_type_node, pcfloat_type_node, NULL_TREE); | |
a3170dc6 | 7759 | tree void_ftype_pfloat_v4sf |
b4de2f7d | 7760 | = build_function_type_list (void_type_node, |
a3170dc6 | 7761 | pfloat_type_node, V4SF_type_node, NULL_TREE); |
0dbc3651 ZW |
7762 | tree v4si_ftype_pcint |
7763 | = build_function_type_list (V4SI_type_node, pcint_type_node, NULL_TREE); | |
7764 | tree void_ftype_pint_v4si | |
b4de2f7d AH |
7765 | = build_function_type_list (void_type_node, |
7766 | pint_type_node, V4SI_type_node, NULL_TREE); | |
0dbc3651 ZW |
7767 | tree v8hi_ftype_pcshort |
7768 | = build_function_type_list (V8HI_type_node, pcshort_type_node, NULL_TREE); | |
f18c054f | 7769 | tree void_ftype_pshort_v8hi |
b4de2f7d AH |
7770 | = build_function_type_list (void_type_node, |
7771 | pshort_type_node, V8HI_type_node, NULL_TREE); | |
0dbc3651 ZW |
7772 | tree v16qi_ftype_pcchar |
7773 | = build_function_type_list (V16QI_type_node, pcchar_type_node, NULL_TREE); | |
f18c054f | 7774 | tree void_ftype_pchar_v16qi |
b4de2f7d AH |
7775 | = build_function_type_list (void_type_node, |
7776 | pchar_type_node, V16QI_type_node, NULL_TREE); | |
95385cbb | 7777 | tree void_ftype_v4si |
b4de2f7d | 7778 | = build_function_type_list (void_type_node, V4SI_type_node, NULL_TREE); |
a3170dc6 AH |
7779 | tree v8hi_ftype_void |
7780 | = build_function_type (V8HI_type_node, void_list_node); | |
7781 | tree void_ftype_void | |
7782 | = build_function_type (void_type_node, void_list_node); | |
e34b6648 JJ |
7783 | tree void_ftype_int |
7784 | = build_function_type_list (void_type_node, integer_type_node, NULL_TREE); | |
0dbc3651 | 7785 | |
b4a62fa0 | 7786 | tree v16qi_ftype_long_pcvoid |
a3170dc6 | 7787 | = build_function_type_list (V16QI_type_node, |
b4a62fa0 SB |
7788 | long_integer_type_node, pcvoid_type_node, NULL_TREE); |
7789 | tree v8hi_ftype_long_pcvoid | |
a3170dc6 | 7790 | = build_function_type_list (V8HI_type_node, |
b4a62fa0 SB |
7791 | long_integer_type_node, pcvoid_type_node, NULL_TREE); |
7792 | tree v4si_ftype_long_pcvoid | |
a3170dc6 | 7793 | = build_function_type_list (V4SI_type_node, |
b4a62fa0 | 7794 | long_integer_type_node, pcvoid_type_node, NULL_TREE); |
0dbc3651 | 7795 | |
b4a62fa0 | 7796 | tree void_ftype_v4si_long_pvoid |
b4de2f7d | 7797 | = build_function_type_list (void_type_node, |
b4a62fa0 | 7798 | V4SI_type_node, long_integer_type_node, |
b4de2f7d | 7799 | pvoid_type_node, NULL_TREE); |
b4a62fa0 | 7800 | tree void_ftype_v16qi_long_pvoid |
b4de2f7d | 7801 | = build_function_type_list (void_type_node, |
b4a62fa0 | 7802 | V16QI_type_node, long_integer_type_node, |
b4de2f7d | 7803 | pvoid_type_node, NULL_TREE); |
b4a62fa0 | 7804 | tree void_ftype_v8hi_long_pvoid |
b4de2f7d | 7805 | = build_function_type_list (void_type_node, |
b4a62fa0 | 7806 | V8HI_type_node, long_integer_type_node, |
b4de2f7d | 7807 | pvoid_type_node, NULL_TREE); |
a3170dc6 AH |
7808 | tree int_ftype_int_v8hi_v8hi |
7809 | = build_function_type_list (integer_type_node, | |
7810 | integer_type_node, V8HI_type_node, | |
7811 | V8HI_type_node, NULL_TREE); | |
7812 | tree int_ftype_int_v16qi_v16qi | |
7813 | = build_function_type_list (integer_type_node, | |
7814 | integer_type_node, V16QI_type_node, | |
7815 | V16QI_type_node, NULL_TREE); | |
7816 | tree int_ftype_int_v4sf_v4sf | |
7817 | = build_function_type_list (integer_type_node, | |
7818 | integer_type_node, V4SF_type_node, | |
7819 | V4SF_type_node, NULL_TREE); | |
7820 | tree v4si_ftype_v4si | |
7821 | = build_function_type_list (V4SI_type_node, V4SI_type_node, NULL_TREE); | |
7822 | tree v8hi_ftype_v8hi | |
7823 | = build_function_type_list (V8HI_type_node, V8HI_type_node, NULL_TREE); | |
7824 | tree v16qi_ftype_v16qi | |
7825 | = build_function_type_list (V16QI_type_node, V16QI_type_node, NULL_TREE); | |
7826 | tree v4sf_ftype_v4sf | |
7827 | = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE); | |
8bb418a3 | 7828 | tree void_ftype_pcvoid_int_int |
a3170dc6 | 7829 | = build_function_type_list (void_type_node, |
0dbc3651 | 7830 | pcvoid_type_node, integer_type_node, |
8bb418a3 ZL |
7831 | integer_type_node, NULL_TREE); |
7832 | tree int_ftype_pcchar | |
7833 | = build_function_type_list (integer_type_node, | |
7834 | pcchar_type_node, NULL_TREE); | |
7835 | ||
0dbc3651 ZW |
7836 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_4sf", v4sf_ftype_pcfloat, |
7837 | ALTIVEC_BUILTIN_LD_INTERNAL_4sf); | |
7838 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_4sf", void_ftype_pfloat_v4sf, | |
7839 | ALTIVEC_BUILTIN_ST_INTERNAL_4sf); | |
7840 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_4si", v4si_ftype_pcint, | |
7841 | ALTIVEC_BUILTIN_LD_INTERNAL_4si); | |
7842 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_4si", void_ftype_pint_v4si, | |
7843 | ALTIVEC_BUILTIN_ST_INTERNAL_4si); | |
7844 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_8hi", v8hi_ftype_pcshort, | |
7845 | ALTIVEC_BUILTIN_LD_INTERNAL_8hi); | |
7846 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_8hi", void_ftype_pshort_v8hi, | |
7847 | ALTIVEC_BUILTIN_ST_INTERNAL_8hi); | |
7848 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_16qi", v16qi_ftype_pcchar, | |
7849 | ALTIVEC_BUILTIN_LD_INTERNAL_16qi); | |
7850 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_16qi", void_ftype_pchar_v16qi, | |
7851 | ALTIVEC_BUILTIN_ST_INTERNAL_16qi); | |
a3170dc6 AH |
7852 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_mtvscr", void_ftype_v4si, ALTIVEC_BUILTIN_MTVSCR); |
7853 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_mfvscr", v8hi_ftype_void, ALTIVEC_BUILTIN_MFVSCR); | |
7854 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_dssall", void_ftype_void, ALTIVEC_BUILTIN_DSSALL); | |
e34b6648 | 7855 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_dss", void_ftype_int, ALTIVEC_BUILTIN_DSS); |
b4a62fa0 SB |
7856 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvsl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSL); |
7857 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvsr", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSR); | |
7858 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvebx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEBX); | |
7859 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvehx", v8hi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEHX); | |
7860 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvewx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEWX); | |
7861 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvxl", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVXL); | |
7862 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVX); | |
7863 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVX); | |
7864 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvewx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVEWX); | |
7865 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvxl", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVXL); | |
7866 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvebx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVEBX); | |
7867 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvehx", void_ftype_v8hi_long_pvoid, ALTIVEC_BUILTIN_STVEHX); | |
a3170dc6 | 7868 | |
8bb418a3 ZL |
7869 | /* See altivec.h for usage of "__builtin_altivec_compiletime_error". */ |
7870 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_compiletime_error", int_ftype_pcchar, | |
7871 | ALTIVEC_BUILTIN_COMPILETIME_ERROR); | |
7872 | ||
a3170dc6 AH |
7873 | /* Add the DST variants. */ |
7874 | d = (struct builtin_description *) bdesc_dst; | |
7875 | for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++) | |
8bb418a3 | 7876 | def_builtin (d->mask, d->name, void_ftype_pcvoid_int_int, d->code); |
a3170dc6 AH |
7877 | |
7878 | /* Initialize the predicates. */ | |
7879 | dp = (struct builtin_description_predicates *) bdesc_altivec_preds; | |
7880 | for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, dp++) | |
7881 | { | |
7882 | enum machine_mode mode1; | |
7883 | tree type; | |
7884 | ||
7885 | mode1 = insn_data[dp->icode].operand[1].mode; | |
7886 | ||
7887 | switch (mode1) | |
7888 | { | |
7889 | case V4SImode: | |
7890 | type = int_ftype_int_v4si_v4si; | |
7891 | break; | |
7892 | case V8HImode: | |
7893 | type = int_ftype_int_v8hi_v8hi; | |
7894 | break; | |
7895 | case V16QImode: | |
7896 | type = int_ftype_int_v16qi_v16qi; | |
7897 | break; | |
7898 | case V4SFmode: | |
7899 | type = int_ftype_int_v4sf_v4sf; | |
7900 | break; | |
7901 | default: | |
7902 | abort (); | |
7903 | } | |
f676971a | 7904 | |
a3170dc6 AH |
7905 | def_builtin (dp->mask, dp->name, type, dp->code); |
7906 | } | |
7907 | ||
7908 | /* Initialize the abs* operators. */ | |
7909 | d = (struct builtin_description *) bdesc_abs; | |
7910 | for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++) | |
7911 | { | |
7912 | enum machine_mode mode0; | |
7913 | tree type; | |
7914 | ||
7915 | mode0 = insn_data[d->icode].operand[0].mode; | |
7916 | ||
7917 | switch (mode0) | |
7918 | { | |
7919 | case V4SImode: | |
7920 | type = v4si_ftype_v4si; | |
7921 | break; | |
7922 | case V8HImode: | |
7923 | type = v8hi_ftype_v8hi; | |
7924 | break; | |
7925 | case V16QImode: | |
7926 | type = v16qi_ftype_v16qi; | |
7927 | break; | |
7928 | case V4SFmode: | |
7929 | type = v4sf_ftype_v4sf; | |
7930 | break; | |
7931 | default: | |
7932 | abort (); | |
7933 | } | |
f676971a | 7934 | |
a3170dc6 AH |
7935 | def_builtin (d->mask, d->name, type, d->code); |
7936 | } | |
7ccf35ed | 7937 | |
13c62176 DN |
7938 | if (TARGET_ALTIVEC) |
7939 | { | |
7940 | tree decl; | |
7941 | ||
7942 | /* Initialize target builtin that implements | |
7943 | targetm.vectorize.builtin_mask_for_load. */ | |
7944 | ||
7945 | decl = lang_hooks.builtin_function ("__builtin_altivec_mask_for_load", | |
7946 | v16qi_ftype_long_pcvoid, | |
7947 | ALTIVEC_BUILTIN_MASK_FOR_LOAD, | |
7948 | BUILT_IN_MD, NULL, NULL_TREE); | |
7949 | /* Record the decl. Will be used by rs6000_builtin_mask_for_load. */ | |
7950 | altivec_builtin_mask_for_load = decl; | |
7951 | ||
7952 | ||
7953 | /* Initialize target builtin that implements | |
7954 | targetm.vectorize.builtin_mask_for_store. */ | |
7955 | ||
7956 | decl = lang_hooks.builtin_function ("__builtin_altivec_mask_for_store", | |
7957 | v16qi_ftype_long_pcvoid, | |
7958 | ALTIVEC_BUILTIN_MASK_FOR_STORE, | |
7959 | BUILT_IN_MD, NULL, NULL_TREE); | |
7960 | /* Record the decl. Will be used by rs6000_builtin_mask_for_store. */ | |
7961 | altivec_builtin_mask_for_store = decl; | |
7962 | } | |
a3170dc6 AH |
7963 | } |
7964 | ||
7965 | static void | |
863d938c | 7966 | rs6000_common_init_builtins (void) |
a3170dc6 AH |
7967 | { |
7968 | struct builtin_description *d; | |
7969 | size_t i; | |
7970 | ||
7971 | tree v4sf_ftype_v4sf_v4sf_v16qi | |
7972 | = build_function_type_list (V4SF_type_node, | |
7973 | V4SF_type_node, V4SF_type_node, | |
7974 | V16QI_type_node, NULL_TREE); | |
7975 | tree v4si_ftype_v4si_v4si_v16qi | |
7976 | = build_function_type_list (V4SI_type_node, | |
7977 | V4SI_type_node, V4SI_type_node, | |
7978 | V16QI_type_node, NULL_TREE); | |
7979 | tree v8hi_ftype_v8hi_v8hi_v16qi | |
7980 | = build_function_type_list (V8HI_type_node, | |
7981 | V8HI_type_node, V8HI_type_node, | |
7982 | V16QI_type_node, NULL_TREE); | |
7983 | tree v16qi_ftype_v16qi_v16qi_v16qi | |
7984 | = build_function_type_list (V16QI_type_node, | |
7985 | V16QI_type_node, V16QI_type_node, | |
7986 | V16QI_type_node, NULL_TREE); | |
b9e4e5d1 ZL |
7987 | tree v4si_ftype_int |
7988 | = build_function_type_list (V4SI_type_node, integer_type_node, NULL_TREE); | |
7989 | tree v8hi_ftype_int | |
7990 | = build_function_type_list (V8HI_type_node, integer_type_node, NULL_TREE); | |
7991 | tree v16qi_ftype_int | |
7992 | = build_function_type_list (V16QI_type_node, integer_type_node, NULL_TREE); | |
a3170dc6 AH |
7993 | tree v8hi_ftype_v16qi |
7994 | = build_function_type_list (V8HI_type_node, V16QI_type_node, NULL_TREE); | |
7995 | tree v4sf_ftype_v4sf | |
7996 | = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE); | |
7997 | ||
7998 | tree v2si_ftype_v2si_v2si | |
2abe3e28 AH |
7999 | = build_function_type_list (opaque_V2SI_type_node, |
8000 | opaque_V2SI_type_node, | |
8001 | opaque_V2SI_type_node, NULL_TREE); | |
a3170dc6 AH |
8002 | |
8003 | tree v2sf_ftype_v2sf_v2sf | |
2abe3e28 AH |
8004 | = build_function_type_list (opaque_V2SF_type_node, |
8005 | opaque_V2SF_type_node, | |
8006 | opaque_V2SF_type_node, NULL_TREE); | |
a3170dc6 AH |
8007 | |
8008 | tree v2si_ftype_int_int | |
2abe3e28 | 8009 | = build_function_type_list (opaque_V2SI_type_node, |
a3170dc6 AH |
8010 | integer_type_node, integer_type_node, |
8011 | NULL_TREE); | |
8012 | ||
8013 | tree v2si_ftype_v2si | |
2abe3e28 AH |
8014 | = build_function_type_list (opaque_V2SI_type_node, |
8015 | opaque_V2SI_type_node, NULL_TREE); | |
a3170dc6 AH |
8016 | |
8017 | tree v2sf_ftype_v2sf | |
2abe3e28 AH |
8018 | = build_function_type_list (opaque_V2SF_type_node, |
8019 | opaque_V2SF_type_node, NULL_TREE); | |
f676971a | 8020 | |
a3170dc6 | 8021 | tree v2sf_ftype_v2si |
2abe3e28 AH |
8022 | = build_function_type_list (opaque_V2SF_type_node, |
8023 | opaque_V2SI_type_node, NULL_TREE); | |
a3170dc6 AH |
8024 | |
8025 | tree v2si_ftype_v2sf | |
2abe3e28 AH |
8026 | = build_function_type_list (opaque_V2SI_type_node, |
8027 | opaque_V2SF_type_node, NULL_TREE); | |
a3170dc6 AH |
8028 | |
8029 | tree v2si_ftype_v2si_char | |
2abe3e28 AH |
8030 | = build_function_type_list (opaque_V2SI_type_node, |
8031 | opaque_V2SI_type_node, | |
8032 | char_type_node, NULL_TREE); | |
a3170dc6 AH |
8033 | |
8034 | tree v2si_ftype_int_char | |
2abe3e28 | 8035 | = build_function_type_list (opaque_V2SI_type_node, |
a3170dc6 AH |
8036 | integer_type_node, char_type_node, NULL_TREE); |
8037 | ||
8038 | tree v2si_ftype_char | |
2abe3e28 AH |
8039 | = build_function_type_list (opaque_V2SI_type_node, |
8040 | char_type_node, NULL_TREE); | |
a3170dc6 AH |
8041 | |
8042 | tree int_ftype_int_int | |
8043 | = build_function_type_list (integer_type_node, | |
8044 | integer_type_node, integer_type_node, | |
8045 | NULL_TREE); | |
95385cbb | 8046 | |
0ac081f6 | 8047 | tree v4si_ftype_v4si_v4si |
b4de2f7d AH |
8048 | = build_function_type_list (V4SI_type_node, |
8049 | V4SI_type_node, V4SI_type_node, NULL_TREE); | |
b9e4e5d1 | 8050 | tree v4sf_ftype_v4si_int |
b4de2f7d | 8051 | = build_function_type_list (V4SF_type_node, |
b9e4e5d1 ZL |
8052 | V4SI_type_node, integer_type_node, NULL_TREE); |
8053 | tree v4si_ftype_v4sf_int | |
b4de2f7d | 8054 | = build_function_type_list (V4SI_type_node, |
b9e4e5d1 ZL |
8055 | V4SF_type_node, integer_type_node, NULL_TREE); |
8056 | tree v4si_ftype_v4si_int | |
b4de2f7d | 8057 | = build_function_type_list (V4SI_type_node, |
b9e4e5d1 ZL |
8058 | V4SI_type_node, integer_type_node, NULL_TREE); |
8059 | tree v8hi_ftype_v8hi_int | |
b4de2f7d | 8060 | = build_function_type_list (V8HI_type_node, |
b9e4e5d1 ZL |
8061 | V8HI_type_node, integer_type_node, NULL_TREE); |
8062 | tree v16qi_ftype_v16qi_int | |
b4de2f7d | 8063 | = build_function_type_list (V16QI_type_node, |
b9e4e5d1 ZL |
8064 | V16QI_type_node, integer_type_node, NULL_TREE); |
8065 | tree v16qi_ftype_v16qi_v16qi_int | |
b4de2f7d AH |
8066 | = build_function_type_list (V16QI_type_node, |
8067 | V16QI_type_node, V16QI_type_node, | |
b9e4e5d1 ZL |
8068 | integer_type_node, NULL_TREE); |
8069 | tree v8hi_ftype_v8hi_v8hi_int | |
b4de2f7d AH |
8070 | = build_function_type_list (V8HI_type_node, |
8071 | V8HI_type_node, V8HI_type_node, | |
b9e4e5d1 ZL |
8072 | integer_type_node, NULL_TREE); |
8073 | tree v4si_ftype_v4si_v4si_int | |
b4de2f7d AH |
8074 | = build_function_type_list (V4SI_type_node, |
8075 | V4SI_type_node, V4SI_type_node, | |
b9e4e5d1 ZL |
8076 | integer_type_node, NULL_TREE); |
8077 | tree v4sf_ftype_v4sf_v4sf_int | |
b4de2f7d AH |
8078 | = build_function_type_list (V4SF_type_node, |
8079 | V4SF_type_node, V4SF_type_node, | |
b9e4e5d1 | 8080 | integer_type_node, NULL_TREE); |
0ac081f6 | 8081 | tree v4sf_ftype_v4sf_v4sf |
b4de2f7d AH |
8082 | = build_function_type_list (V4SF_type_node, |
8083 | V4SF_type_node, V4SF_type_node, NULL_TREE); | |
617e0e1d | 8084 | tree v4sf_ftype_v4sf_v4sf_v4si |
b4de2f7d AH |
8085 | = build_function_type_list (V4SF_type_node, |
8086 | V4SF_type_node, V4SF_type_node, | |
8087 | V4SI_type_node, NULL_TREE); | |
2212663f | 8088 | tree v4sf_ftype_v4sf_v4sf_v4sf |
b4de2f7d AH |
8089 | = build_function_type_list (V4SF_type_node, |
8090 | V4SF_type_node, V4SF_type_node, | |
8091 | V4SF_type_node, NULL_TREE); | |
f676971a | 8092 | tree v4si_ftype_v4si_v4si_v4si |
b4de2f7d AH |
8093 | = build_function_type_list (V4SI_type_node, |
8094 | V4SI_type_node, V4SI_type_node, | |
8095 | V4SI_type_node, NULL_TREE); | |
0ac081f6 | 8096 | tree v8hi_ftype_v8hi_v8hi |
b4de2f7d AH |
8097 | = build_function_type_list (V8HI_type_node, |
8098 | V8HI_type_node, V8HI_type_node, NULL_TREE); | |
2212663f | 8099 | tree v8hi_ftype_v8hi_v8hi_v8hi |
b4de2f7d AH |
8100 | = build_function_type_list (V8HI_type_node, |
8101 | V8HI_type_node, V8HI_type_node, | |
8102 | V8HI_type_node, NULL_TREE); | |
c4ad648e | 8103 | tree v4si_ftype_v8hi_v8hi_v4si |
b4de2f7d AH |
8104 | = build_function_type_list (V4SI_type_node, |
8105 | V8HI_type_node, V8HI_type_node, | |
8106 | V4SI_type_node, NULL_TREE); | |
c4ad648e | 8107 | tree v4si_ftype_v16qi_v16qi_v4si |
b4de2f7d AH |
8108 | = build_function_type_list (V4SI_type_node, |
8109 | V16QI_type_node, V16QI_type_node, | |
8110 | V4SI_type_node, NULL_TREE); | |
0ac081f6 | 8111 | tree v16qi_ftype_v16qi_v16qi |
b4de2f7d AH |
8112 | = build_function_type_list (V16QI_type_node, |
8113 | V16QI_type_node, V16QI_type_node, NULL_TREE); | |
0ac081f6 | 8114 | tree v4si_ftype_v4sf_v4sf |
b4de2f7d AH |
8115 | = build_function_type_list (V4SI_type_node, |
8116 | V4SF_type_node, V4SF_type_node, NULL_TREE); | |
0ac081f6 | 8117 | tree v8hi_ftype_v16qi_v16qi |
b4de2f7d AH |
8118 | = build_function_type_list (V8HI_type_node, |
8119 | V16QI_type_node, V16QI_type_node, NULL_TREE); | |
0ac081f6 | 8120 | tree v4si_ftype_v8hi_v8hi |
b4de2f7d AH |
8121 | = build_function_type_list (V4SI_type_node, |
8122 | V8HI_type_node, V8HI_type_node, NULL_TREE); | |
0ac081f6 | 8123 | tree v8hi_ftype_v4si_v4si |
b4de2f7d AH |
8124 | = build_function_type_list (V8HI_type_node, |
8125 | V4SI_type_node, V4SI_type_node, NULL_TREE); | |
0ac081f6 | 8126 | tree v16qi_ftype_v8hi_v8hi |
b4de2f7d AH |
8127 | = build_function_type_list (V16QI_type_node, |
8128 | V8HI_type_node, V8HI_type_node, NULL_TREE); | |
0ac081f6 | 8129 | tree v4si_ftype_v16qi_v4si |
b4de2f7d AH |
8130 | = build_function_type_list (V4SI_type_node, |
8131 | V16QI_type_node, V4SI_type_node, NULL_TREE); | |
fa066a23 | 8132 | tree v4si_ftype_v16qi_v16qi |
b4de2f7d AH |
8133 | = build_function_type_list (V4SI_type_node, |
8134 | V16QI_type_node, V16QI_type_node, NULL_TREE); | |
0ac081f6 | 8135 | tree v4si_ftype_v8hi_v4si |
b4de2f7d AH |
8136 | = build_function_type_list (V4SI_type_node, |
8137 | V8HI_type_node, V4SI_type_node, NULL_TREE); | |
a3170dc6 AH |
8138 | tree v4si_ftype_v8hi |
8139 | = build_function_type_list (V4SI_type_node, V8HI_type_node, NULL_TREE); | |
8140 | tree int_ftype_v4si_v4si | |
8141 | = build_function_type_list (integer_type_node, | |
8142 | V4SI_type_node, V4SI_type_node, NULL_TREE); | |
8143 | tree int_ftype_v4sf_v4sf | |
8144 | = build_function_type_list (integer_type_node, | |
8145 | V4SF_type_node, V4SF_type_node, NULL_TREE); | |
8146 | tree int_ftype_v16qi_v16qi | |
8147 | = build_function_type_list (integer_type_node, | |
8148 | V16QI_type_node, V16QI_type_node, NULL_TREE); | |
0ac081f6 | 8149 | tree int_ftype_v8hi_v8hi |
b4de2f7d AH |
8150 | = build_function_type_list (integer_type_node, |
8151 | V8HI_type_node, V8HI_type_node, NULL_TREE); | |
0ac081f6 | 8152 | |
6f317ef3 | 8153 | /* Add the simple ternary operators. */ |
2212663f | 8154 | d = (struct builtin_description *) bdesc_3arg; |
ca7558fc | 8155 | for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++) |
2212663f | 8156 | { |
f676971a | 8157 | |
2212663f DB |
8158 | enum machine_mode mode0, mode1, mode2, mode3; |
8159 | tree type; | |
8160 | ||
0559cc77 | 8161 | if (d->name == 0 || d->icode == CODE_FOR_nothing) |
2212663f | 8162 | continue; |
f676971a | 8163 | |
2212663f DB |
8164 | mode0 = insn_data[d->icode].operand[0].mode; |
8165 | mode1 = insn_data[d->icode].operand[1].mode; | |
8166 | mode2 = insn_data[d->icode].operand[2].mode; | |
8167 | mode3 = insn_data[d->icode].operand[3].mode; | |
f676971a | 8168 | |
2212663f DB |
8169 | /* When all four are of the same mode. */ |
8170 | if (mode0 == mode1 && mode1 == mode2 && mode2 == mode3) | |
8171 | { | |
8172 | switch (mode0) | |
8173 | { | |
617e0e1d DB |
8174 | case V4SImode: |
8175 | type = v4si_ftype_v4si_v4si_v4si; | |
8176 | break; | |
2212663f DB |
8177 | case V4SFmode: |
8178 | type = v4sf_ftype_v4sf_v4sf_v4sf; | |
8179 | break; | |
8180 | case V8HImode: | |
8181 | type = v8hi_ftype_v8hi_v8hi_v8hi; | |
f676971a | 8182 | break; |
2212663f DB |
8183 | case V16QImode: |
8184 | type = v16qi_ftype_v16qi_v16qi_v16qi; | |
f676971a | 8185 | break; |
2212663f | 8186 | default: |
f676971a | 8187 | abort(); |
2212663f DB |
8188 | } |
8189 | } | |
8190 | else if (mode0 == mode1 && mode1 == mode2 && mode3 == V16QImode) | |
c4ad648e | 8191 | { |
2212663f DB |
8192 | switch (mode0) |
8193 | { | |
8194 | case V4SImode: | |
8195 | type = v4si_ftype_v4si_v4si_v16qi; | |
8196 | break; | |
8197 | case V4SFmode: | |
8198 | type = v4sf_ftype_v4sf_v4sf_v16qi; | |
8199 | break; | |
8200 | case V8HImode: | |
8201 | type = v8hi_ftype_v8hi_v8hi_v16qi; | |
f676971a | 8202 | break; |
2212663f DB |
8203 | case V16QImode: |
8204 | type = v16qi_ftype_v16qi_v16qi_v16qi; | |
f676971a | 8205 | break; |
2212663f | 8206 | default: |
f676971a | 8207 | abort(); |
2212663f DB |
8208 | } |
8209 | } | |
f676971a | 8210 | else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V16QImode |
2212663f | 8211 | && mode3 == V4SImode) |
24408032 | 8212 | type = v4si_ftype_v16qi_v16qi_v4si; |
f676971a | 8213 | else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V8HImode |
2212663f | 8214 | && mode3 == V4SImode) |
24408032 | 8215 | type = v4si_ftype_v8hi_v8hi_v4si; |
f676971a | 8216 | else if (mode0 == V4SFmode && mode1 == V4SFmode && mode2 == V4SFmode |
617e0e1d | 8217 | && mode3 == V4SImode) |
24408032 AH |
8218 | type = v4sf_ftype_v4sf_v4sf_v4si; |
8219 | ||
8220 | /* vchar, vchar, vchar, 4 bit literal. */ | |
8221 | else if (mode0 == V16QImode && mode1 == mode0 && mode2 == mode0 | |
8222 | && mode3 == QImode) | |
b9e4e5d1 | 8223 | type = v16qi_ftype_v16qi_v16qi_int; |
24408032 AH |
8224 | |
8225 | /* vshort, vshort, vshort, 4 bit literal. */ | |
8226 | else if (mode0 == V8HImode && mode1 == mode0 && mode2 == mode0 | |
8227 | && mode3 == QImode) | |
b9e4e5d1 | 8228 | type = v8hi_ftype_v8hi_v8hi_int; |
24408032 AH |
8229 | |
8230 | /* vint, vint, vint, 4 bit literal. */ | |
8231 | else if (mode0 == V4SImode && mode1 == mode0 && mode2 == mode0 | |
8232 | && mode3 == QImode) | |
b9e4e5d1 | 8233 | type = v4si_ftype_v4si_v4si_int; |
24408032 AH |
8234 | |
8235 | /* vfloat, vfloat, vfloat, 4 bit literal. */ | |
8236 | else if (mode0 == V4SFmode && mode1 == mode0 && mode2 == mode0 | |
8237 | && mode3 == QImode) | |
b9e4e5d1 | 8238 | type = v4sf_ftype_v4sf_v4sf_int; |
24408032 | 8239 | |
2212663f DB |
8240 | else |
8241 | abort (); | |
8242 | ||
8243 | def_builtin (d->mask, d->name, type, d->code); | |
8244 | } | |
8245 | ||
0ac081f6 | 8246 | /* Add the simple binary operators. */ |
00b960c7 | 8247 | d = (struct builtin_description *) bdesc_2arg; |
ca7558fc | 8248 | for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++) |
0ac081f6 AH |
8249 | { |
8250 | enum machine_mode mode0, mode1, mode2; | |
8251 | tree type; | |
8252 | ||
0559cc77 | 8253 | if (d->name == 0 || d->icode == CODE_FOR_nothing) |
0ac081f6 | 8254 | continue; |
f676971a | 8255 | |
0ac081f6 AH |
8256 | mode0 = insn_data[d->icode].operand[0].mode; |
8257 | mode1 = insn_data[d->icode].operand[1].mode; | |
8258 | mode2 = insn_data[d->icode].operand[2].mode; | |
8259 | ||
8260 | /* When all three operands are of the same mode. */ | |
8261 | if (mode0 == mode1 && mode1 == mode2) | |
8262 | { | |
8263 | switch (mode0) | |
8264 | { | |
8265 | case V4SFmode: | |
8266 | type = v4sf_ftype_v4sf_v4sf; | |
8267 | break; | |
8268 | case V4SImode: | |
8269 | type = v4si_ftype_v4si_v4si; | |
8270 | break; | |
8271 | case V16QImode: | |
8272 | type = v16qi_ftype_v16qi_v16qi; | |
8273 | break; | |
8274 | case V8HImode: | |
8275 | type = v8hi_ftype_v8hi_v8hi; | |
8276 | break; | |
a3170dc6 AH |
8277 | case V2SImode: |
8278 | type = v2si_ftype_v2si_v2si; | |
8279 | break; | |
8280 | case V2SFmode: | |
8281 | type = v2sf_ftype_v2sf_v2sf; | |
8282 | break; | |
8283 | case SImode: | |
8284 | type = int_ftype_int_int; | |
8285 | break; | |
0ac081f6 AH |
8286 | default: |
8287 | abort (); | |
8288 | } | |
8289 | } | |
8290 | ||
8291 | /* A few other combos we really don't want to do manually. */ | |
8292 | ||
8293 | /* vint, vfloat, vfloat. */ | |
8294 | else if (mode0 == V4SImode && mode1 == V4SFmode && mode2 == V4SFmode) | |
8295 | type = v4si_ftype_v4sf_v4sf; | |
8296 | ||
8297 | /* vshort, vchar, vchar. */ | |
8298 | else if (mode0 == V8HImode && mode1 == V16QImode && mode2 == V16QImode) | |
8299 | type = v8hi_ftype_v16qi_v16qi; | |
8300 | ||
8301 | /* vint, vshort, vshort. */ | |
8302 | else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V8HImode) | |
8303 | type = v4si_ftype_v8hi_v8hi; | |
8304 | ||
8305 | /* vshort, vint, vint. */ | |
8306 | else if (mode0 == V8HImode && mode1 == V4SImode && mode2 == V4SImode) | |
8307 | type = v8hi_ftype_v4si_v4si; | |
8308 | ||
8309 | /* vchar, vshort, vshort. */ | |
8310 | else if (mode0 == V16QImode && mode1 == V8HImode && mode2 == V8HImode) | |
8311 | type = v16qi_ftype_v8hi_v8hi; | |
8312 | ||
8313 | /* vint, vchar, vint. */ | |
8314 | else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V4SImode) | |
8315 | type = v4si_ftype_v16qi_v4si; | |
8316 | ||
fa066a23 AH |
8317 | /* vint, vchar, vchar. */ |
8318 | else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V16QImode) | |
8319 | type = v4si_ftype_v16qi_v16qi; | |
8320 | ||
0ac081f6 AH |
8321 | /* vint, vshort, vint. */ |
8322 | else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V4SImode) | |
8323 | type = v4si_ftype_v8hi_v4si; | |
f676971a | 8324 | |
2212663f DB |
8325 | /* vint, vint, 5 bit literal. */ |
8326 | else if (mode0 == V4SImode && mode1 == V4SImode && mode2 == QImode) | |
b9e4e5d1 | 8327 | type = v4si_ftype_v4si_int; |
f676971a | 8328 | |
2212663f DB |
8329 | /* vshort, vshort, 5 bit literal. */ |
8330 | else if (mode0 == V8HImode && mode1 == V8HImode && mode2 == QImode) | |
b9e4e5d1 | 8331 | type = v8hi_ftype_v8hi_int; |
f676971a | 8332 | |
2212663f DB |
8333 | /* vchar, vchar, 5 bit literal. */ |
8334 | else if (mode0 == V16QImode && mode1 == V16QImode && mode2 == QImode) | |
b9e4e5d1 | 8335 | type = v16qi_ftype_v16qi_int; |
0ac081f6 | 8336 | |
617e0e1d DB |
8337 | /* vfloat, vint, 5 bit literal. */ |
8338 | else if (mode0 == V4SFmode && mode1 == V4SImode && mode2 == QImode) | |
b9e4e5d1 | 8339 | type = v4sf_ftype_v4si_int; |
f676971a | 8340 | |
617e0e1d DB |
8341 | /* vint, vfloat, 5 bit literal. */ |
8342 | else if (mode0 == V4SImode && mode1 == V4SFmode && mode2 == QImode) | |
b9e4e5d1 | 8343 | type = v4si_ftype_v4sf_int; |
617e0e1d | 8344 | |
a3170dc6 AH |
8345 | else if (mode0 == V2SImode && mode1 == SImode && mode2 == SImode) |
8346 | type = v2si_ftype_int_int; | |
8347 | ||
8348 | else if (mode0 == V2SImode && mode1 == V2SImode && mode2 == QImode) | |
8349 | type = v2si_ftype_v2si_char; | |
8350 | ||
8351 | else if (mode0 == V2SImode && mode1 == SImode && mode2 == QImode) | |
8352 | type = v2si_ftype_int_char; | |
8353 | ||
0ac081f6 AH |
8354 | /* int, x, x. */ |
8355 | else if (mode0 == SImode) | |
8356 | { | |
8357 | switch (mode1) | |
8358 | { | |
8359 | case V4SImode: | |
8360 | type = int_ftype_v4si_v4si; | |
8361 | break; | |
8362 | case V4SFmode: | |
8363 | type = int_ftype_v4sf_v4sf; | |
8364 | break; | |
8365 | case V16QImode: | |
8366 | type = int_ftype_v16qi_v16qi; | |
8367 | break; | |
8368 | case V8HImode: | |
8369 | type = int_ftype_v8hi_v8hi; | |
8370 | break; | |
8371 | default: | |
8372 | abort (); | |
8373 | } | |
8374 | } | |
8375 | ||
8376 | else | |
8377 | abort (); | |
8378 | ||
2212663f DB |
8379 | def_builtin (d->mask, d->name, type, d->code); |
8380 | } | |
24408032 | 8381 | |
2212663f DB |
8382 | /* Add the simple unary operators. */ |
8383 | d = (struct builtin_description *) bdesc_1arg; | |
ca7558fc | 8384 | for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++) |
2212663f DB |
8385 | { |
8386 | enum machine_mode mode0, mode1; | |
8387 | tree type; | |
8388 | ||
0559cc77 | 8389 | if (d->name == 0 || d->icode == CODE_FOR_nothing) |
2212663f | 8390 | continue; |
f676971a | 8391 | |
2212663f DB |
8392 | mode0 = insn_data[d->icode].operand[0].mode; |
8393 | mode1 = insn_data[d->icode].operand[1].mode; | |
8394 | ||
8395 | if (mode0 == V4SImode && mode1 == QImode) | |
c4ad648e | 8396 | type = v4si_ftype_int; |
2212663f | 8397 | else if (mode0 == V8HImode && mode1 == QImode) |
c4ad648e | 8398 | type = v8hi_ftype_int; |
2212663f | 8399 | else if (mode0 == V16QImode && mode1 == QImode) |
c4ad648e | 8400 | type = v16qi_ftype_int; |
617e0e1d DB |
8401 | else if (mode0 == V4SFmode && mode1 == V4SFmode) |
8402 | type = v4sf_ftype_v4sf; | |
20e26713 AH |
8403 | else if (mode0 == V8HImode && mode1 == V16QImode) |
8404 | type = v8hi_ftype_v16qi; | |
8405 | else if (mode0 == V4SImode && mode1 == V8HImode) | |
8406 | type = v4si_ftype_v8hi; | |
a3170dc6 AH |
8407 | else if (mode0 == V2SImode && mode1 == V2SImode) |
8408 | type = v2si_ftype_v2si; | |
8409 | else if (mode0 == V2SFmode && mode1 == V2SFmode) | |
8410 | type = v2sf_ftype_v2sf; | |
8411 | else if (mode0 == V2SFmode && mode1 == V2SImode) | |
8412 | type = v2sf_ftype_v2si; | |
8413 | else if (mode0 == V2SImode && mode1 == V2SFmode) | |
8414 | type = v2si_ftype_v2sf; | |
8415 | else if (mode0 == V2SImode && mode1 == QImode) | |
8416 | type = v2si_ftype_char; | |
2212663f DB |
8417 | else |
8418 | abort (); | |
8419 | ||
0ac081f6 AH |
8420 | def_builtin (d->mask, d->name, type, d->code); |
8421 | } | |
8422 | } | |
8423 | ||
c15c90bb ZW |
8424 | static void |
8425 | rs6000_init_libfuncs (void) | |
8426 | { | |
8427 | if (!TARGET_HARD_FLOAT) | |
8428 | return; | |
8429 | ||
c9034561 | 8430 | if (DEFAULT_ABI != ABI_V4) |
c15c90bb | 8431 | { |
c9034561 | 8432 | if (TARGET_XCOFF && ! TARGET_POWER2 && ! TARGET_POWERPC) |
c15c90bb | 8433 | { |
c9034561 | 8434 | /* AIX library routines for float->int conversion. */ |
85363ca0 ZW |
8435 | set_conv_libfunc (sfix_optab, SImode, DFmode, "__itrunc"); |
8436 | set_conv_libfunc (ufix_optab, SImode, DFmode, "__uitrunc"); | |
4274207b DE |
8437 | set_conv_libfunc (sfix_optab, SImode, TFmode, "_qitrunc"); |
8438 | set_conv_libfunc (ufix_optab, SImode, TFmode, "_quitrunc"); | |
c15c90bb ZW |
8439 | } |
8440 | ||
c9034561 | 8441 | /* Standard AIX/Darwin/64-bit SVR4 quad floating point routines. */ |
c15c90bb ZW |
8442 | set_optab_libfunc (add_optab, TFmode, "_xlqadd"); |
8443 | set_optab_libfunc (sub_optab, TFmode, "_xlqsub"); | |
8444 | set_optab_libfunc (smul_optab, TFmode, "_xlqmul"); | |
8445 | set_optab_libfunc (sdiv_optab, TFmode, "_xlqdiv"); | |
8446 | } | |
c9034561 | 8447 | else |
c15c90bb | 8448 | { |
c9034561 | 8449 | /* 32-bit SVR4 quad floating point routines. */ |
c15c90bb ZW |
8450 | |
8451 | set_optab_libfunc (add_optab, TFmode, "_q_add"); | |
8452 | set_optab_libfunc (sub_optab, TFmode, "_q_sub"); | |
8453 | set_optab_libfunc (neg_optab, TFmode, "_q_neg"); | |
8454 | set_optab_libfunc (smul_optab, TFmode, "_q_mul"); | |
8455 | set_optab_libfunc (sdiv_optab, TFmode, "_q_div"); | |
8456 | if (TARGET_PPC_GPOPT || TARGET_POWER2) | |
8457 | set_optab_libfunc (sqrt_optab, TFmode, "_q_sqrt"); | |
8458 | ||
c9034561 ZW |
8459 | set_optab_libfunc (eq_optab, TFmode, "_q_feq"); |
8460 | set_optab_libfunc (ne_optab, TFmode, "_q_fne"); | |
8461 | set_optab_libfunc (gt_optab, TFmode, "_q_fgt"); | |
8462 | set_optab_libfunc (ge_optab, TFmode, "_q_fge"); | |
8463 | set_optab_libfunc (lt_optab, TFmode, "_q_flt"); | |
8464 | set_optab_libfunc (le_optab, TFmode, "_q_fle"); | |
8465 | ||
85363ca0 ZW |
8466 | set_conv_libfunc (sext_optab, TFmode, SFmode, "_q_stoq"); |
8467 | set_conv_libfunc (sext_optab, TFmode, DFmode, "_q_dtoq"); | |
8468 | set_conv_libfunc (trunc_optab, SFmode, TFmode, "_q_qtos"); | |
8469 | set_conv_libfunc (trunc_optab, DFmode, TFmode, "_q_qtod"); | |
8470 | set_conv_libfunc (sfix_optab, SImode, TFmode, "_q_qtoi"); | |
8471 | set_conv_libfunc (ufix_optab, SImode, TFmode, "_q_qtou"); | |
8472 | set_conv_libfunc (sfloat_optab, TFmode, SImode, "_q_itoq"); | |
c15c90bb ZW |
8473 | } |
8474 | } | |
fba73eb1 DE |
8475 | |
8476 | \f | |
8477 | /* Expand a block clear operation, and return 1 if successful. Return 0 | |
8478 | if we should let the compiler generate normal code. | |
8479 | ||
8480 | operands[0] is the destination | |
8481 | operands[1] is the length | |
8482 | operands[2] is the alignment */ | |
8483 | ||
8484 | int | |
8485 | expand_block_clear (rtx operands[]) | |
8486 | { | |
8487 | rtx orig_dest = operands[0]; | |
8488 | rtx bytes_rtx = operands[1]; | |
8489 | rtx align_rtx = operands[2]; | |
5514620a GK |
8490 | bool constp = (GET_CODE (bytes_rtx) == CONST_INT); |
8491 | HOST_WIDE_INT align; | |
8492 | HOST_WIDE_INT bytes; | |
fba73eb1 DE |
8493 | int offset; |
8494 | int clear_bytes; | |
5514620a | 8495 | int clear_step; |
fba73eb1 DE |
8496 | |
8497 | /* If this is not a fixed size move, just call memcpy */ | |
8498 | if (! constp) | |
8499 | return 0; | |
8500 | ||
8501 | /* If this is not a fixed size alignment, abort */ | |
8502 | if (GET_CODE (align_rtx) != CONST_INT) | |
8503 | abort (); | |
8504 | align = INTVAL (align_rtx) * BITS_PER_UNIT; | |
8505 | ||
8506 | /* Anything to clear? */ | |
8507 | bytes = INTVAL (bytes_rtx); | |
8508 | if (bytes <= 0) | |
8509 | return 1; | |
8510 | ||
5514620a GK |
8511 | /* Use the builtin memset after a point, to avoid huge code bloat. |
8512 | When optimize_size, avoid any significant code bloat; calling | |
8513 | memset is about 4 instructions, so allow for one instruction to | |
8514 | load zero and three to do clearing. */ | |
8515 | if (TARGET_ALTIVEC && align >= 128) | |
8516 | clear_step = 16; | |
8517 | else if (TARGET_POWERPC64 && align >= 32) | |
8518 | clear_step = 8; | |
8519 | else | |
8520 | clear_step = 4; | |
fba73eb1 | 8521 | |
5514620a GK |
8522 | if (optimize_size && bytes > 3 * clear_step) |
8523 | return 0; | |
8524 | if (! optimize_size && bytes > 8 * clear_step) | |
fba73eb1 DE |
8525 | return 0; |
8526 | ||
8527 | for (offset = 0; bytes > 0; offset += clear_bytes, bytes -= clear_bytes) | |
8528 | { | |
fba73eb1 DE |
8529 | enum machine_mode mode = BLKmode; |
8530 | rtx dest; | |
f676971a | 8531 | |
5514620a GK |
8532 | if (bytes >= 16 && TARGET_ALTIVEC && align >= 128) |
8533 | { | |
8534 | clear_bytes = 16; | |
8535 | mode = V4SImode; | |
8536 | } | |
8537 | else if (bytes >= 8 && TARGET_POWERPC64 | |
8538 | /* 64-bit loads and stores require word-aligned | |
8539 | displacements. */ | |
8540 | && (align >= 64 || (!STRICT_ALIGNMENT && align >= 32))) | |
fba73eb1 DE |
8541 | { |
8542 | clear_bytes = 8; | |
8543 | mode = DImode; | |
fba73eb1 | 8544 | } |
5514620a | 8545 | else if (bytes >= 4 && (align >= 32 || !STRICT_ALIGNMENT)) |
fba73eb1 DE |
8546 | { /* move 4 bytes */ |
8547 | clear_bytes = 4; | |
8548 | mode = SImode; | |
fba73eb1 | 8549 | } |
5514620a | 8550 | else if (bytes == 2 && (align >= 16 || !STRICT_ALIGNMENT)) |
fba73eb1 DE |
8551 | { /* move 2 bytes */ |
8552 | clear_bytes = 2; | |
8553 | mode = HImode; | |
fba73eb1 DE |
8554 | } |
8555 | else /* move 1 byte at a time */ | |
8556 | { | |
8557 | clear_bytes = 1; | |
8558 | mode = QImode; | |
fba73eb1 | 8559 | } |
f676971a | 8560 | |
fba73eb1 | 8561 | dest = adjust_address (orig_dest, mode, offset); |
f676971a | 8562 | |
5514620a | 8563 | emit_move_insn (dest, CONST0_RTX (mode)); |
fba73eb1 DE |
8564 | } |
8565 | ||
8566 | return 1; | |
8567 | } | |
8568 | ||
35aff10b | 8569 | \f |
7e69e155 MM |
8570 | /* Expand a block move operation, and return 1 if successful. Return 0 |
8571 | if we should let the compiler generate normal code. | |
8572 | ||
8573 | operands[0] is the destination | |
8574 | operands[1] is the source | |
8575 | operands[2] is the length | |
8576 | operands[3] is the alignment */ | |
8577 | ||
3933e0e1 MM |
8578 | #define MAX_MOVE_REG 4 |
8579 | ||
7e69e155 | 8580 | int |
a2369ed3 | 8581 | expand_block_move (rtx operands[]) |
7e69e155 | 8582 | { |
b6c9286a MM |
8583 | rtx orig_dest = operands[0]; |
8584 | rtx orig_src = operands[1]; | |
7e69e155 | 8585 | rtx bytes_rtx = operands[2]; |
7e69e155 | 8586 | rtx align_rtx = operands[3]; |
3933e0e1 | 8587 | int constp = (GET_CODE (bytes_rtx) == CONST_INT); |
5ee95df6 | 8588 | int align; |
3933e0e1 MM |
8589 | int bytes; |
8590 | int offset; | |
7e69e155 | 8591 | int move_bytes; |
cabfd258 GK |
8592 | rtx stores[MAX_MOVE_REG]; |
8593 | int num_reg = 0; | |
7e69e155 | 8594 | |
3933e0e1 | 8595 | /* If this is not a fixed size move, just call memcpy */ |
cc0d9ba8 | 8596 | if (! constp) |
3933e0e1 MM |
8597 | return 0; |
8598 | ||
5ee95df6 FS |
8599 | /* If this is not a fixed size alignment, abort */ |
8600 | if (GET_CODE (align_rtx) != CONST_INT) | |
8601 | abort (); | |
fba73eb1 | 8602 | align = INTVAL (align_rtx) * BITS_PER_UNIT; |
5ee95df6 | 8603 | |
7e69e155 | 8604 | /* Anything to move? */ |
3933e0e1 MM |
8605 | bytes = INTVAL (bytes_rtx); |
8606 | if (bytes <= 0) | |
7e69e155 MM |
8607 | return 1; |
8608 | ||
ea9982a8 | 8609 | /* store_one_arg depends on expand_block_move to handle at least the size of |
f676971a | 8610 | reg_parm_stack_space. */ |
ea9982a8 | 8611 | if (bytes > (TARGET_POWERPC64 ? 64 : 32)) |
7e69e155 MM |
8612 | return 0; |
8613 | ||
cabfd258 | 8614 | for (offset = 0; bytes > 0; offset += move_bytes, bytes -= move_bytes) |
7e69e155 | 8615 | { |
cabfd258 | 8616 | union { |
70128ad9 | 8617 | rtx (*movmemsi) (rtx, rtx, rtx, rtx); |
a2369ed3 | 8618 | rtx (*mov) (rtx, rtx); |
cabfd258 GK |
8619 | } gen_func; |
8620 | enum machine_mode mode = BLKmode; | |
8621 | rtx src, dest; | |
f676971a | 8622 | |
5514620a GK |
8623 | /* Altivec first, since it will be faster than a string move |
8624 | when it applies, and usually not significantly larger. */ | |
8625 | if (TARGET_ALTIVEC && bytes >= 16 && align >= 128) | |
8626 | { | |
8627 | move_bytes = 16; | |
8628 | mode = V4SImode; | |
8629 | gen_func.mov = gen_movv4si; | |
8630 | } | |
8631 | else if (TARGET_STRING | |
cabfd258 GK |
8632 | && bytes > 24 /* move up to 32 bytes at a time */ |
8633 | && ! fixed_regs[5] | |
8634 | && ! fixed_regs[6] | |
8635 | && ! fixed_regs[7] | |
8636 | && ! fixed_regs[8] | |
8637 | && ! fixed_regs[9] | |
8638 | && ! fixed_regs[10] | |
8639 | && ! fixed_regs[11] | |
8640 | && ! fixed_regs[12]) | |
7e69e155 | 8641 | { |
cabfd258 | 8642 | move_bytes = (bytes > 32) ? 32 : bytes; |
70128ad9 | 8643 | gen_func.movmemsi = gen_movmemsi_8reg; |
cabfd258 GK |
8644 | } |
8645 | else if (TARGET_STRING | |
8646 | && bytes > 16 /* move up to 24 bytes at a time */ | |
8647 | && ! fixed_regs[5] | |
8648 | && ! fixed_regs[6] | |
8649 | && ! fixed_regs[7] | |
8650 | && ! fixed_regs[8] | |
8651 | && ! fixed_regs[9] | |
8652 | && ! fixed_regs[10]) | |
8653 | { | |
8654 | move_bytes = (bytes > 24) ? 24 : bytes; | |
70128ad9 | 8655 | gen_func.movmemsi = gen_movmemsi_6reg; |
cabfd258 GK |
8656 | } |
8657 | else if (TARGET_STRING | |
8658 | && bytes > 8 /* move up to 16 bytes at a time */ | |
8659 | && ! fixed_regs[5] | |
8660 | && ! fixed_regs[6] | |
8661 | && ! fixed_regs[7] | |
8662 | && ! fixed_regs[8]) | |
8663 | { | |
8664 | move_bytes = (bytes > 16) ? 16 : bytes; | |
70128ad9 | 8665 | gen_func.movmemsi = gen_movmemsi_4reg; |
cabfd258 GK |
8666 | } |
8667 | else if (bytes >= 8 && TARGET_POWERPC64 | |
8668 | /* 64-bit loads and stores require word-aligned | |
8669 | displacements. */ | |
fba73eb1 | 8670 | && (align >= 64 || (!STRICT_ALIGNMENT && align >= 32))) |
cabfd258 GK |
8671 | { |
8672 | move_bytes = 8; | |
8673 | mode = DImode; | |
8674 | gen_func.mov = gen_movdi; | |
8675 | } | |
8676 | else if (TARGET_STRING && bytes > 4 && !TARGET_POWERPC64) | |
8677 | { /* move up to 8 bytes at a time */ | |
8678 | move_bytes = (bytes > 8) ? 8 : bytes; | |
70128ad9 | 8679 | gen_func.movmemsi = gen_movmemsi_2reg; |
cabfd258 | 8680 | } |
cd7d9ca4 | 8681 | else if (bytes >= 4 && (align >= 32 || !STRICT_ALIGNMENT)) |
cabfd258 GK |
8682 | { /* move 4 bytes */ |
8683 | move_bytes = 4; | |
8684 | mode = SImode; | |
8685 | gen_func.mov = gen_movsi; | |
8686 | } | |
cd7d9ca4 | 8687 | else if (bytes == 2 && (align >= 16 || !STRICT_ALIGNMENT)) |
cabfd258 GK |
8688 | { /* move 2 bytes */ |
8689 | move_bytes = 2; | |
8690 | mode = HImode; | |
8691 | gen_func.mov = gen_movhi; | |
8692 | } | |
8693 | else if (TARGET_STRING && bytes > 1) | |
8694 | { /* move up to 4 bytes at a time */ | |
8695 | move_bytes = (bytes > 4) ? 4 : bytes; | |
70128ad9 | 8696 | gen_func.movmemsi = gen_movmemsi_1reg; |
cabfd258 GK |
8697 | } |
8698 | else /* move 1 byte at a time */ | |
8699 | { | |
8700 | move_bytes = 1; | |
8701 | mode = QImode; | |
8702 | gen_func.mov = gen_movqi; | |
8703 | } | |
f676971a | 8704 | |
cabfd258 GK |
8705 | src = adjust_address (orig_src, mode, offset); |
8706 | dest = adjust_address (orig_dest, mode, offset); | |
f676971a EC |
8707 | |
8708 | if (mode != BLKmode) | |
cabfd258 GK |
8709 | { |
8710 | rtx tmp_reg = gen_reg_rtx (mode); | |
f676971a | 8711 | |
cabfd258 GK |
8712 | emit_insn ((*gen_func.mov) (tmp_reg, src)); |
8713 | stores[num_reg++] = (*gen_func.mov) (dest, tmp_reg); | |
4c64a852 | 8714 | } |
3933e0e1 | 8715 | |
cabfd258 GK |
8716 | if (mode == BLKmode || num_reg >= MAX_MOVE_REG || bytes == move_bytes) |
8717 | { | |
8718 | int i; | |
8719 | for (i = 0; i < num_reg; i++) | |
8720 | emit_insn (stores[i]); | |
8721 | num_reg = 0; | |
8722 | } | |
35aff10b | 8723 | |
cabfd258 | 8724 | if (mode == BLKmode) |
7e69e155 | 8725 | { |
70128ad9 | 8726 | /* Move the address into scratch registers. The movmemsi |
cabfd258 GK |
8727 | patterns require zero offset. */ |
8728 | if (!REG_P (XEXP (src, 0))) | |
b6c9286a | 8729 | { |
cabfd258 GK |
8730 | rtx src_reg = copy_addr_to_reg (XEXP (src, 0)); |
8731 | src = replace_equiv_address (src, src_reg); | |
b6c9286a | 8732 | } |
cabfd258 | 8733 | set_mem_size (src, GEN_INT (move_bytes)); |
f676971a | 8734 | |
cabfd258 | 8735 | if (!REG_P (XEXP (dest, 0))) |
3933e0e1 | 8736 | { |
cabfd258 GK |
8737 | rtx dest_reg = copy_addr_to_reg (XEXP (dest, 0)); |
8738 | dest = replace_equiv_address (dest, dest_reg); | |
7e69e155 | 8739 | } |
cabfd258 | 8740 | set_mem_size (dest, GEN_INT (move_bytes)); |
f676971a | 8741 | |
70128ad9 | 8742 | emit_insn ((*gen_func.movmemsi) (dest, src, |
cabfd258 GK |
8743 | GEN_INT (move_bytes & 31), |
8744 | align_rtx)); | |
7e69e155 | 8745 | } |
7e69e155 MM |
8746 | } |
8747 | ||
8748 | return 1; | |
8749 | } | |
8750 | ||
d62294f5 FJ |
8751 | \f |
8752 | /* Return 1 if OP is suitable for a save_world call in prologue. It is | |
8753 | known to be a PARALLEL. */ | |
8754 | int | |
8755 | save_world_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) | |
8756 | { | |
8757 | int index; | |
8758 | int i; | |
8759 | rtx elt; | |
8760 | int count = XVECLEN (op, 0); | |
8761 | ||
8762 | if (count != 55) | |
8763 | return 0; | |
8764 | ||
8765 | index = 0; | |
8766 | if (GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER | |
8767 | || GET_CODE (XVECEXP (op, 0, index++)) != USE) | |
8768 | return 0; | |
8769 | ||
8770 | for (i=1; i <= 18; i++) | |
8771 | { | |
8772 | elt = XVECEXP (op, 0, index++); | |
8773 | if (GET_CODE (elt) != SET | |
8774 | || GET_CODE (SET_DEST (elt)) != MEM | |
8775 | || ! memory_operand (SET_DEST (elt), DFmode) | |
8776 | || GET_CODE (SET_SRC (elt)) != REG | |
8777 | || GET_MODE (SET_SRC (elt)) != DFmode) | |
8778 | return 0; | |
8779 | } | |
8780 | ||
8781 | for (i=1; i <= 12; i++) | |
8782 | { | |
8783 | elt = XVECEXP (op, 0, index++); | |
8784 | if (GET_CODE (elt) != SET | |
8785 | || GET_CODE (SET_DEST (elt)) != MEM | |
8786 | || GET_CODE (SET_SRC (elt)) != REG | |
8787 | || GET_MODE (SET_SRC (elt)) != V4SImode) | |
8788 | return 0; | |
8789 | } | |
8790 | ||
8791 | for (i=1; i <= 19; i++) | |
8792 | { | |
8793 | elt = XVECEXP (op, 0, index++); | |
8794 | if (GET_CODE (elt) != SET | |
8795 | || GET_CODE (SET_DEST (elt)) != MEM | |
8796 | || ! memory_operand (SET_DEST (elt), Pmode) | |
8797 | || GET_CODE (SET_SRC (elt)) != REG | |
8798 | || GET_MODE (SET_SRC (elt)) != Pmode) | |
8799 | return 0; | |
8800 | } | |
8801 | ||
8802 | elt = XVECEXP (op, 0, index++); | |
8803 | if (GET_CODE (elt) != SET | |
8804 | || GET_CODE (SET_DEST (elt)) != MEM | |
8805 | || ! memory_operand (SET_DEST (elt), Pmode) | |
8806 | || GET_CODE (SET_SRC (elt)) != REG | |
8807 | || REGNO (SET_SRC (elt)) != CR2_REGNO | |
8808 | || GET_MODE (SET_SRC (elt)) != Pmode) | |
8809 | return 0; | |
8810 | ||
8811 | if (GET_CODE (XVECEXP (op, 0, index++)) != USE | |
8812 | || GET_CODE (XVECEXP (op, 0, index++)) != USE | |
8813 | || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER) | |
8814 | return 0; | |
8815 | return 1; | |
8816 | } | |
8817 | ||
8818 | /* Return 1 if OP is suitable for a save_world call in prologue. It is | |
8819 | known to be a PARALLEL. */ | |
8820 | int | |
8821 | restore_world_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) | |
8822 | { | |
8823 | int index; | |
8824 | int i; | |
8825 | rtx elt; | |
8826 | int count = XVECLEN (op, 0); | |
8827 | ||
8828 | if (count != 59) | |
8829 | return 0; | |
8830 | ||
8831 | index = 0; | |
8832 | if (GET_CODE (XVECEXP (op, 0, index++)) != RETURN | |
8833 | || GET_CODE (XVECEXP (op, 0, index++)) != USE | |
8834 | || GET_CODE (XVECEXP (op, 0, index++)) != USE | |
8835 | || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER) | |
8836 | return 0; | |
8837 | ||
8838 | elt = XVECEXP (op, 0, index++); | |
8839 | if (GET_CODE (elt) != SET | |
8840 | || GET_CODE (SET_SRC (elt)) != MEM | |
8841 | || ! memory_operand (SET_SRC (elt), Pmode) | |
8842 | || GET_CODE (SET_DEST (elt)) != REG | |
8843 | || REGNO (SET_DEST (elt)) != CR2_REGNO | |
8844 | || GET_MODE (SET_DEST (elt)) != Pmode) | |
8845 | return 0; | |
8846 | ||
8847 | for (i=1; i <= 19; i++) | |
8848 | { | |
8849 | elt = XVECEXP (op, 0, index++); | |
8850 | if (GET_CODE (elt) != SET | |
8851 | || GET_CODE (SET_SRC (elt)) != MEM | |
8852 | || ! memory_operand (SET_SRC (elt), Pmode) | |
8853 | || GET_CODE (SET_DEST (elt)) != REG | |
8854 | || GET_MODE (SET_DEST (elt)) != Pmode) | |
8855 | return 0; | |
8856 | } | |
8857 | ||
8858 | for (i=1; i <= 12; i++) | |
8859 | { | |
8860 | elt = XVECEXP (op, 0, index++); | |
8861 | if (GET_CODE (elt) != SET | |
8862 | || GET_CODE (SET_SRC (elt)) != MEM | |
8863 | || GET_CODE (SET_DEST (elt)) != REG | |
8864 | || GET_MODE (SET_DEST (elt)) != V4SImode) | |
8865 | return 0; | |
8866 | } | |
8867 | ||
8868 | for (i=1; i <= 18; i++) | |
8869 | { | |
8870 | elt = XVECEXP (op, 0, index++); | |
8871 | if (GET_CODE (elt) != SET | |
8872 | || GET_CODE (SET_SRC (elt)) != MEM | |
8873 | || ! memory_operand (SET_SRC (elt), DFmode) | |
8874 | || GET_CODE (SET_DEST (elt)) != REG | |
8875 | || GET_MODE (SET_DEST (elt)) != DFmode) | |
8876 | return 0; | |
8877 | } | |
8878 | ||
8879 | if (GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER | |
8880 | || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER | |
8881 | || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER | |
8882 | || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER | |
8883 | || GET_CODE (XVECEXP (op, 0, index++)) != USE) | |
8884 | return 0; | |
8885 | return 1; | |
8886 | } | |
8887 | ||
9878760c RK |
8888 | \f |
8889 | /* Return 1 if OP is a load multiple operation. It is known to be a | |
8890 | PARALLEL and the first section will be tested. */ | |
8891 | ||
8892 | int | |
a2369ed3 | 8893 | load_multiple_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
9878760c RK |
8894 | { |
8895 | int count = XVECLEN (op, 0); | |
e2c953b6 | 8896 | unsigned int dest_regno; |
9878760c RK |
8897 | rtx src_addr; |
8898 | int i; | |
8899 | ||
8900 | /* Perform a quick check so we don't blow up below. */ | |
8901 | if (count <= 1 | |
8902 | || GET_CODE (XVECEXP (op, 0, 0)) != SET | |
8903 | || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG | |
8904 | || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM) | |
8905 | return 0; | |
8906 | ||
8907 | dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0))); | |
8908 | src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0); | |
8909 | ||
8910 | for (i = 1; i < count; i++) | |
8911 | { | |
8912 | rtx elt = XVECEXP (op, 0, i); | |
8913 | ||
8914 | if (GET_CODE (elt) != SET | |
8915 | || GET_CODE (SET_DEST (elt)) != REG | |
8916 | || GET_MODE (SET_DEST (elt)) != SImode | |
8917 | || REGNO (SET_DEST (elt)) != dest_regno + i | |
8918 | || GET_CODE (SET_SRC (elt)) != MEM | |
8919 | || GET_MODE (SET_SRC (elt)) != SImode | |
8920 | || GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS | |
8921 | || ! rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr) | |
8922 | || GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT | |
8923 | || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != i * 4) | |
8924 | return 0; | |
8925 | } | |
8926 | ||
8927 | return 1; | |
8928 | } | |
8929 | ||
8930 | /* Similar, but tests for store multiple. Here, the second vector element | |
8931 | is a CLOBBER. It will be tested later. */ | |
8932 | ||
8933 | int | |
a2369ed3 | 8934 | store_multiple_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
9878760c RK |
8935 | { |
8936 | int count = XVECLEN (op, 0) - 1; | |
e2c953b6 | 8937 | unsigned int src_regno; |
9878760c RK |
8938 | rtx dest_addr; |
8939 | int i; | |
8940 | ||
8941 | /* Perform a quick check so we don't blow up below. */ | |
8942 | if (count <= 1 | |
8943 | || GET_CODE (XVECEXP (op, 0, 0)) != SET | |
8944 | || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM | |
8945 | || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG) | |
8946 | return 0; | |
8947 | ||
8948 | src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0))); | |
8949 | dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0); | |
8950 | ||
8951 | for (i = 1; i < count; i++) | |
8952 | { | |
8953 | rtx elt = XVECEXP (op, 0, i + 1); | |
8954 | ||
8955 | if (GET_CODE (elt) != SET | |
8956 | || GET_CODE (SET_SRC (elt)) != REG | |
8957 | || GET_MODE (SET_SRC (elt)) != SImode | |
8958 | || REGNO (SET_SRC (elt)) != src_regno + i | |
8959 | || GET_CODE (SET_DEST (elt)) != MEM | |
8960 | || GET_MODE (SET_DEST (elt)) != SImode | |
8961 | || GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS | |
8962 | || ! rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr) | |
8963 | || GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT | |
8964 | || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != i * 4) | |
8965 | return 0; | |
8966 | } | |
8967 | ||
8968 | return 1; | |
8969 | } | |
9ebbca7d | 8970 | |
9caa3eb2 DE |
8971 | /* Return a string to perform a load_multiple operation. |
8972 | operands[0] is the vector. | |
8973 | operands[1] is the source address. | |
8974 | operands[2] is the first destination register. */ | |
8975 | ||
8976 | const char * | |
a2369ed3 | 8977 | rs6000_output_load_multiple (rtx operands[3]) |
9caa3eb2 DE |
8978 | { |
8979 | /* We have to handle the case where the pseudo used to contain the address | |
8980 | is assigned to one of the output registers. */ | |
8981 | int i, j; | |
8982 | int words = XVECLEN (operands[0], 0); | |
8983 | rtx xop[10]; | |
8984 | ||
8985 | if (XVECLEN (operands[0], 0) == 1) | |
8986 | return "{l|lwz} %2,0(%1)"; | |
8987 | ||
8988 | for (i = 0; i < words; i++) | |
8989 | if (refers_to_regno_p (REGNO (operands[2]) + i, | |
8990 | REGNO (operands[2]) + i + 1, operands[1], 0)) | |
8991 | { | |
8992 | if (i == words-1) | |
8993 | { | |
8994 | xop[0] = GEN_INT (4 * (words-1)); | |
8995 | xop[1] = operands[1]; | |
8996 | xop[2] = operands[2]; | |
8997 | output_asm_insn ("{lsi|lswi} %2,%1,%0\n\t{l|lwz} %1,%0(%1)", xop); | |
8998 | return ""; | |
8999 | } | |
9000 | else if (i == 0) | |
9001 | { | |
9002 | xop[0] = GEN_INT (4 * (words-1)); | |
9003 | xop[1] = operands[1]; | |
9004 | xop[2] = gen_rtx_REG (SImode, REGNO (operands[2]) + 1); | |
9005 | output_asm_insn ("{cal %1,4(%1)|addi %1,%1,4}\n\t{lsi|lswi} %2,%1,%0\n\t{l|lwz} %1,-4(%1)", xop); | |
9006 | return ""; | |
9007 | } | |
9008 | else | |
9009 | { | |
9010 | for (j = 0; j < words; j++) | |
9011 | if (j != i) | |
9012 | { | |
9013 | xop[0] = GEN_INT (j * 4); | |
9014 | xop[1] = operands[1]; | |
9015 | xop[2] = gen_rtx_REG (SImode, REGNO (operands[2]) + j); | |
9016 | output_asm_insn ("{l|lwz} %2,%0(%1)", xop); | |
9017 | } | |
9018 | xop[0] = GEN_INT (i * 4); | |
9019 | xop[1] = operands[1]; | |
9020 | output_asm_insn ("{l|lwz} %1,%0(%1)", xop); | |
9021 | return ""; | |
9022 | } | |
9023 | } | |
9024 | ||
9025 | return "{lsi|lswi} %2,%1,%N0"; | |
9026 | } | |
9027 | ||
00b960c7 AH |
9028 | /* Return 1 for a parallel vrsave operation. */ |
9029 | ||
9030 | int | |
a2369ed3 | 9031 | vrsave_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
00b960c7 AH |
9032 | { |
9033 | int count = XVECLEN (op, 0); | |
9034 | unsigned int dest_regno, src_regno; | |
9035 | int i; | |
9036 | ||
9037 | if (count <= 1 | |
9038 | || GET_CODE (XVECEXP (op, 0, 0)) != SET | |
9039 | || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG | |
a004eb82 | 9040 | || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC_VOLATILE) |
00b960c7 AH |
9041 | return 0; |
9042 | ||
9043 | dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0))); | |
9044 | src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0))); | |
9045 | ||
9046 | if (dest_regno != VRSAVE_REGNO | |
9047 | && src_regno != VRSAVE_REGNO) | |
9048 | return 0; | |
9049 | ||
9050 | for (i = 1; i < count; i++) | |
9051 | { | |
9052 | rtx elt = XVECEXP (op, 0, i); | |
9053 | ||
9aa86737 AH |
9054 | if (GET_CODE (elt) != CLOBBER |
9055 | && GET_CODE (elt) != SET) | |
00b960c7 AH |
9056 | return 0; |
9057 | } | |
9058 | ||
9059 | return 1; | |
9060 | } | |
9061 | ||
2c4a9cff DE |
9062 | /* Return 1 for an PARALLEL suitable for mfcr. */ |
9063 | ||
9064 | int | |
a2369ed3 | 9065 | mfcr_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
2c4a9cff DE |
9066 | { |
9067 | int count = XVECLEN (op, 0); | |
9068 | int i; | |
9069 | ||
9070 | /* Perform a quick check so we don't blow up below. */ | |
9071 | if (count < 1 | |
9072 | || GET_CODE (XVECEXP (op, 0, 0)) != SET | |
9073 | || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC | |
9074 | || XVECLEN (SET_SRC (XVECEXP (op, 0, 0)), 0) != 2) | |
9075 | return 0; | |
9076 | ||
9077 | for (i = 0; i < count; i++) | |
9078 | { | |
9079 | rtx exp = XVECEXP (op, 0, i); | |
9080 | rtx unspec; | |
9081 | int maskval; | |
9082 | rtx src_reg; | |
9083 | ||
9084 | src_reg = XVECEXP (SET_SRC (exp), 0, 0); | |
9085 | ||
9086 | if (GET_CODE (src_reg) != REG | |
9087 | || GET_MODE (src_reg) != CCmode | |
9088 | || ! CR_REGNO_P (REGNO (src_reg))) | |
9089 | return 0; | |
9090 | ||
9091 | if (GET_CODE (exp) != SET | |
9092 | || GET_CODE (SET_DEST (exp)) != REG | |
9093 | || GET_MODE (SET_DEST (exp)) != SImode | |
9094 | || ! INT_REGNO_P (REGNO (SET_DEST (exp)))) | |
9095 | return 0; | |
9096 | unspec = SET_SRC (exp); | |
9097 | maskval = 1 << (MAX_CR_REGNO - REGNO (src_reg)); | |
9098 | ||
9099 | if (GET_CODE (unspec) != UNSPEC | |
9100 | || XINT (unspec, 1) != UNSPEC_MOVESI_FROM_CR | |
9101 | || XVECLEN (unspec, 0) != 2 | |
9102 | || XVECEXP (unspec, 0, 0) != src_reg | |
9103 | || GET_CODE (XVECEXP (unspec, 0, 1)) != CONST_INT | |
9104 | || INTVAL (XVECEXP (unspec, 0, 1)) != maskval) | |
9105 | return 0; | |
9106 | } | |
9107 | return 1; | |
9108 | } | |
9109 | ||
a4f6c312 | 9110 | /* Return 1 for an PARALLEL suitable for mtcrf. */ |
9ebbca7d GK |
9111 | |
9112 | int | |
a2369ed3 | 9113 | mtcrf_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
9ebbca7d GK |
9114 | { |
9115 | int count = XVECLEN (op, 0); | |
9116 | int i; | |
9ebbca7d GK |
9117 | rtx src_reg; |
9118 | ||
9119 | /* Perform a quick check so we don't blow up below. */ | |
e35b9579 GK |
9120 | if (count < 1 |
9121 | || GET_CODE (XVECEXP (op, 0, 0)) != SET | |
9122 | || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC | |
9123 | || XVECLEN (SET_SRC (XVECEXP (op, 0, 0)), 0) != 2) | |
9ebbca7d | 9124 | return 0; |
e35b9579 | 9125 | src_reg = XVECEXP (SET_SRC (XVECEXP (op, 0, 0)), 0, 0); |
f676971a | 9126 | |
9ebbca7d GK |
9127 | if (GET_CODE (src_reg) != REG |
9128 | || GET_MODE (src_reg) != SImode | |
9129 | || ! INT_REGNO_P (REGNO (src_reg))) | |
9130 | return 0; | |
9131 | ||
e35b9579 | 9132 | for (i = 0; i < count; i++) |
9ebbca7d GK |
9133 | { |
9134 | rtx exp = XVECEXP (op, 0, i); | |
9135 | rtx unspec; | |
9136 | int maskval; | |
f676971a | 9137 | |
9ebbca7d GK |
9138 | if (GET_CODE (exp) != SET |
9139 | || GET_CODE (SET_DEST (exp)) != REG | |
9140 | || GET_MODE (SET_DEST (exp)) != CCmode | |
9141 | || ! CR_REGNO_P (REGNO (SET_DEST (exp)))) | |
9142 | return 0; | |
9143 | unspec = SET_SRC (exp); | |
9144 | maskval = 1 << (MAX_CR_REGNO - REGNO (SET_DEST (exp))); | |
f676971a | 9145 | |
9ebbca7d | 9146 | if (GET_CODE (unspec) != UNSPEC |
615158e2 | 9147 | || XINT (unspec, 1) != UNSPEC_MOVESI_TO_CR |
9ebbca7d GK |
9148 | || XVECLEN (unspec, 0) != 2 |
9149 | || XVECEXP (unspec, 0, 0) != src_reg | |
9150 | || GET_CODE (XVECEXP (unspec, 0, 1)) != CONST_INT | |
9151 | || INTVAL (XVECEXP (unspec, 0, 1)) != maskval) | |
9152 | return 0; | |
9153 | } | |
e35b9579 | 9154 | return 1; |
9ebbca7d GK |
9155 | } |
9156 | ||
a4f6c312 | 9157 | /* Return 1 for an PARALLEL suitable for lmw. */ |
9ebbca7d GK |
9158 | |
9159 | int | |
a2369ed3 | 9160 | lmw_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
9ebbca7d GK |
9161 | { |
9162 | int count = XVECLEN (op, 0); | |
e2c953b6 | 9163 | unsigned int dest_regno; |
9ebbca7d | 9164 | rtx src_addr; |
e2c953b6 | 9165 | unsigned int base_regno; |
9ebbca7d GK |
9166 | HOST_WIDE_INT offset; |
9167 | int i; | |
9168 | ||
9169 | /* Perform a quick check so we don't blow up below. */ | |
9170 | if (count <= 1 | |
9171 | || GET_CODE (XVECEXP (op, 0, 0)) != SET | |
9172 | || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG | |
9173 | || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM) | |
9174 | return 0; | |
9175 | ||
9176 | dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0))); | |
9177 | src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0); | |
9178 | ||
9179 | if (dest_regno > 31 | |
e2c953b6 | 9180 | || count != 32 - (int) dest_regno) |
9ebbca7d GK |
9181 | return 0; |
9182 | ||
4d588c14 | 9183 | if (legitimate_indirect_address_p (src_addr, 0)) |
9ebbca7d GK |
9184 | { |
9185 | offset = 0; | |
9186 | base_regno = REGNO (src_addr); | |
9187 | if (base_regno == 0) | |
9188 | return 0; | |
9189 | } | |
76d2b81d | 9190 | else if (rs6000_legitimate_offset_address_p (SImode, src_addr, 0)) |
9ebbca7d GK |
9191 | { |
9192 | offset = INTVAL (XEXP (src_addr, 1)); | |
9193 | base_regno = REGNO (XEXP (src_addr, 0)); | |
9194 | } | |
9195 | else | |
9196 | return 0; | |
9197 | ||
9198 | for (i = 0; i < count; i++) | |
9199 | { | |
9200 | rtx elt = XVECEXP (op, 0, i); | |
9201 | rtx newaddr; | |
9202 | rtx addr_reg; | |
9203 | HOST_WIDE_INT newoffset; | |
9204 | ||
9205 | if (GET_CODE (elt) != SET | |
9206 | || GET_CODE (SET_DEST (elt)) != REG | |
9207 | || GET_MODE (SET_DEST (elt)) != SImode | |
9208 | || REGNO (SET_DEST (elt)) != dest_regno + i | |
9209 | || GET_CODE (SET_SRC (elt)) != MEM | |
9210 | || GET_MODE (SET_SRC (elt)) != SImode) | |
9211 | return 0; | |
9212 | newaddr = XEXP (SET_SRC (elt), 0); | |
4d588c14 | 9213 | if (legitimate_indirect_address_p (newaddr, 0)) |
9ebbca7d GK |
9214 | { |
9215 | newoffset = 0; | |
9216 | addr_reg = newaddr; | |
9217 | } | |
76d2b81d | 9218 | else if (rs6000_legitimate_offset_address_p (SImode, newaddr, 0)) |
9ebbca7d GK |
9219 | { |
9220 | addr_reg = XEXP (newaddr, 0); | |
9221 | newoffset = INTVAL (XEXP (newaddr, 1)); | |
9222 | } | |
9223 | else | |
9224 | return 0; | |
9225 | if (REGNO (addr_reg) != base_regno | |
9226 | || newoffset != offset + 4 * i) | |
9227 | return 0; | |
9228 | } | |
9229 | ||
9230 | return 1; | |
9231 | } | |
9232 | ||
a4f6c312 | 9233 | /* Return 1 for an PARALLEL suitable for stmw. */ |
9ebbca7d GK |
9234 | |
9235 | int | |
a2369ed3 | 9236 | stmw_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
9ebbca7d GK |
9237 | { |
9238 | int count = XVECLEN (op, 0); | |
e2c953b6 | 9239 | unsigned int src_regno; |
9ebbca7d | 9240 | rtx dest_addr; |
e2c953b6 | 9241 | unsigned int base_regno; |
9ebbca7d GK |
9242 | HOST_WIDE_INT offset; |
9243 | int i; | |
9244 | ||
9245 | /* Perform a quick check so we don't blow up below. */ | |
9246 | if (count <= 1 | |
9247 | || GET_CODE (XVECEXP (op, 0, 0)) != SET | |
9248 | || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM | |
9249 | || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG) | |
9250 | return 0; | |
9251 | ||
9252 | src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0))); | |
9253 | dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0); | |
9254 | ||
9255 | if (src_regno > 31 | |
e2c953b6 | 9256 | || count != 32 - (int) src_regno) |
9ebbca7d GK |
9257 | return 0; |
9258 | ||
4d588c14 | 9259 | if (legitimate_indirect_address_p (dest_addr, 0)) |
9ebbca7d GK |
9260 | { |
9261 | offset = 0; | |
9262 | base_regno = REGNO (dest_addr); | |
9263 | if (base_regno == 0) | |
9264 | return 0; | |
9265 | } | |
76d2b81d | 9266 | else if (rs6000_legitimate_offset_address_p (SImode, dest_addr, 0)) |
9ebbca7d GK |
9267 | { |
9268 | offset = INTVAL (XEXP (dest_addr, 1)); | |
9269 | base_regno = REGNO (XEXP (dest_addr, 0)); | |
9270 | } | |
9271 | else | |
9272 | return 0; | |
9273 | ||
9274 | for (i = 0; i < count; i++) | |
9275 | { | |
9276 | rtx elt = XVECEXP (op, 0, i); | |
9277 | rtx newaddr; | |
9278 | rtx addr_reg; | |
9279 | HOST_WIDE_INT newoffset; | |
9280 | ||
9281 | if (GET_CODE (elt) != SET | |
9282 | || GET_CODE (SET_SRC (elt)) != REG | |
9283 | || GET_MODE (SET_SRC (elt)) != SImode | |
9284 | || REGNO (SET_SRC (elt)) != src_regno + i | |
9285 | || GET_CODE (SET_DEST (elt)) != MEM | |
9286 | || GET_MODE (SET_DEST (elt)) != SImode) | |
9287 | return 0; | |
9288 | newaddr = XEXP (SET_DEST (elt), 0); | |
4d588c14 | 9289 | if (legitimate_indirect_address_p (newaddr, 0)) |
9ebbca7d GK |
9290 | { |
9291 | newoffset = 0; | |
9292 | addr_reg = newaddr; | |
9293 | } | |
76d2b81d | 9294 | else if (rs6000_legitimate_offset_address_p (SImode, newaddr, 0)) |
9ebbca7d GK |
9295 | { |
9296 | addr_reg = XEXP (newaddr, 0); | |
9297 | newoffset = INTVAL (XEXP (newaddr, 1)); | |
9298 | } | |
9299 | else | |
9300 | return 0; | |
9301 | if (REGNO (addr_reg) != base_regno | |
9302 | || newoffset != offset + 4 * i) | |
9303 | return 0; | |
9304 | } | |
9305 | ||
9306 | return 1; | |
9307 | } | |
9878760c | 9308 | \f |
a4f6c312 SS |
9309 | /* A validation routine: say whether CODE, a condition code, and MODE |
9310 | match. The other alternatives either don't make sense or should | |
9311 | never be generated. */ | |
39a10a29 | 9312 | |
39a10a29 | 9313 | static void |
a2369ed3 | 9314 | validate_condition_mode (enum rtx_code code, enum machine_mode mode) |
39a10a29 | 9315 | { |
ec8e098d PB |
9316 | if ((GET_RTX_CLASS (code) != RTX_COMPARE |
9317 | && GET_RTX_CLASS (code) != RTX_COMM_COMPARE) | |
39a10a29 GK |
9318 | || GET_MODE_CLASS (mode) != MODE_CC) |
9319 | abort (); | |
9320 | ||
9321 | /* These don't make sense. */ | |
9322 | if ((code == GT || code == LT || code == GE || code == LE) | |
9323 | && mode == CCUNSmode) | |
9324 | abort (); | |
9325 | ||
9326 | if ((code == GTU || code == LTU || code == GEU || code == LEU) | |
9327 | && mode != CCUNSmode) | |
9328 | abort (); | |
9329 | ||
9330 | if (mode != CCFPmode | |
9331 | && (code == ORDERED || code == UNORDERED | |
9332 | || code == UNEQ || code == LTGT | |
9333 | || code == UNGT || code == UNLT | |
9334 | || code == UNGE || code == UNLE)) | |
a4f6c312 | 9335 | abort (); |
f676971a EC |
9336 | |
9337 | /* These should never be generated except for | |
bc9ec0e0 | 9338 | flag_finite_math_only. */ |
39a10a29 | 9339 | if (mode == CCFPmode |
ad72b533 | 9340 | && ! flag_finite_math_only |
39a10a29 GK |
9341 | && (code == LE || code == GE |
9342 | || code == UNEQ || code == LTGT | |
9343 | || code == UNGT || code == UNLT)) | |
9344 | abort (); | |
9345 | ||
9346 | /* These are invalid; the information is not there. */ | |
f676971a | 9347 | if (mode == CCEQmode |
39a10a29 GK |
9348 | && code != EQ && code != NE) |
9349 | abort (); | |
9350 | } | |
9351 | ||
9878760c RK |
9352 | /* Return 1 if OP is a comparison operation that is valid for a branch insn. |
9353 | We only check the opcode against the mode of the CC value here. */ | |
9354 | ||
9355 | int | |
a2369ed3 | 9356 | branch_comparison_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
9878760c RK |
9357 | { |
9358 | enum rtx_code code = GET_CODE (op); | |
9359 | enum machine_mode cc_mode; | |
9360 | ||
ec8e098d | 9361 | if (!COMPARISON_P (op)) |
9878760c RK |
9362 | return 0; |
9363 | ||
9364 | cc_mode = GET_MODE (XEXP (op, 0)); | |
9365 | if (GET_MODE_CLASS (cc_mode) != MODE_CC) | |
9366 | return 0; | |
9367 | ||
39a10a29 | 9368 | validate_condition_mode (code, cc_mode); |
9878760c | 9369 | |
39a10a29 GK |
9370 | return 1; |
9371 | } | |
9372 | ||
9373 | /* Return 1 if OP is a comparison operation that is valid for a branch | |
9374 | insn and which is true if the corresponding bit in the CC register | |
9375 | is set. */ | |
9376 | ||
9377 | int | |
a2369ed3 | 9378 | branch_positive_comparison_operator (rtx op, enum machine_mode mode) |
39a10a29 GK |
9379 | { |
9380 | enum rtx_code code; | |
9381 | ||
8daf2e65 | 9382 | if (! branch_comparison_operator (op, mode)) |
9878760c RK |
9383 | return 0; |
9384 | ||
39a10a29 GK |
9385 | code = GET_CODE (op); |
9386 | return (code == EQ || code == LT || code == GT | |
9387 | || code == LTU || code == GTU | |
9388 | || code == UNORDERED); | |
9878760c RK |
9389 | } |
9390 | ||
b7053a3f GK |
9391 | /* Return 1 if OP is a comparison operation that is valid for an scc |
9392 | insn: it must be a positive comparison. */ | |
9878760c RK |
9393 | |
9394 | int | |
a2369ed3 | 9395 | scc_comparison_operator (rtx op, enum machine_mode mode) |
9878760c | 9396 | { |
b7053a3f | 9397 | return branch_positive_comparison_operator (op, mode); |
9878760c | 9398 | } |
e0cd0770 JC |
9399 | |
9400 | int | |
a2369ed3 | 9401 | trap_comparison_operator (rtx op, enum machine_mode mode) |
e0cd0770 JC |
9402 | { |
9403 | if (mode != VOIDmode && mode != GET_MODE (op)) | |
9404 | return 0; | |
ec8e098d | 9405 | return COMPARISON_P (op); |
e0cd0770 | 9406 | } |
dfbdccdb GK |
9407 | |
9408 | int | |
a2369ed3 | 9409 | boolean_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
dfbdccdb GK |
9410 | { |
9411 | enum rtx_code code = GET_CODE (op); | |
9412 | return (code == AND || code == IOR || code == XOR); | |
9413 | } | |
1d328b19 GK |
9414 | |
9415 | int | |
a2369ed3 | 9416 | boolean_or_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
1d328b19 GK |
9417 | { |
9418 | enum rtx_code code = GET_CODE (op); | |
9419 | return (code == IOR || code == XOR); | |
9420 | } | |
50a0b056 GK |
9421 | |
9422 | int | |
a2369ed3 | 9423 | min_max_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
50a0b056 GK |
9424 | { |
9425 | enum rtx_code code = GET_CODE (op); | |
9426 | return (code == SMIN || code == SMAX || code == UMIN || code == UMAX); | |
9427 | } | |
9878760c RK |
9428 | \f |
9429 | /* Return 1 if ANDOP is a mask that has no bits on that are not in the | |
9430 | mask required to convert the result of a rotate insn into a shift | |
b1765bde | 9431 | left insn of SHIFTOP bits. Both are known to be SImode CONST_INT. */ |
9878760c RK |
9432 | |
9433 | int | |
a2369ed3 | 9434 | includes_lshift_p (rtx shiftop, rtx andop) |
9878760c | 9435 | { |
e2c953b6 DE |
9436 | unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0; |
9437 | ||
9438 | shift_mask <<= INTVAL (shiftop); | |
9878760c | 9439 | |
b1765bde | 9440 | return (INTVAL (andop) & 0xffffffff & ~shift_mask) == 0; |
9878760c RK |
9441 | } |
9442 | ||
9443 | /* Similar, but for right shift. */ | |
9444 | ||
9445 | int | |
a2369ed3 | 9446 | includes_rshift_p (rtx shiftop, rtx andop) |
9878760c | 9447 | { |
a7653a2c | 9448 | unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0; |
9878760c RK |
9449 | |
9450 | shift_mask >>= INTVAL (shiftop); | |
9451 | ||
b1765bde | 9452 | return (INTVAL (andop) & 0xffffffff & ~shift_mask) == 0; |
e2c953b6 DE |
9453 | } |
9454 | ||
c5059423 AM |
9455 | /* Return 1 if ANDOP is a mask suitable for use with an rldic insn |
9456 | to perform a left shift. It must have exactly SHIFTOP least | |
b6d08ca1 | 9457 | significant 0's, then one or more 1's, then zero or more 0's. */ |
e2c953b6 DE |
9458 | |
9459 | int | |
a2369ed3 | 9460 | includes_rldic_lshift_p (rtx shiftop, rtx andop) |
e2c953b6 | 9461 | { |
c5059423 AM |
9462 | if (GET_CODE (andop) == CONST_INT) |
9463 | { | |
02071907 | 9464 | HOST_WIDE_INT c, lsb, shift_mask; |
e2c953b6 | 9465 | |
c5059423 | 9466 | c = INTVAL (andop); |
02071907 | 9467 | if (c == 0 || c == ~0) |
c5059423 | 9468 | return 0; |
e2c953b6 | 9469 | |
02071907 | 9470 | shift_mask = ~0; |
c5059423 AM |
9471 | shift_mask <<= INTVAL (shiftop); |
9472 | ||
b6d08ca1 | 9473 | /* Find the least significant one bit. */ |
c5059423 AM |
9474 | lsb = c & -c; |
9475 | ||
9476 | /* It must coincide with the LSB of the shift mask. */ | |
9477 | if (-lsb != shift_mask) | |
9478 | return 0; | |
e2c953b6 | 9479 | |
c5059423 AM |
9480 | /* Invert to look for the next transition (if any). */ |
9481 | c = ~c; | |
9482 | ||
9483 | /* Remove the low group of ones (originally low group of zeros). */ | |
9484 | c &= -lsb; | |
9485 | ||
9486 | /* Again find the lsb, and check we have all 1's above. */ | |
9487 | lsb = c & -c; | |
9488 | return c == -lsb; | |
9489 | } | |
9490 | else if (GET_CODE (andop) == CONST_DOUBLE | |
9491 | && (GET_MODE (andop) == VOIDmode || GET_MODE (andop) == DImode)) | |
9492 | { | |
02071907 AM |
9493 | HOST_WIDE_INT low, high, lsb; |
9494 | HOST_WIDE_INT shift_mask_low, shift_mask_high; | |
c5059423 AM |
9495 | |
9496 | low = CONST_DOUBLE_LOW (andop); | |
9497 | if (HOST_BITS_PER_WIDE_INT < 64) | |
9498 | high = CONST_DOUBLE_HIGH (andop); | |
9499 | ||
9500 | if ((low == 0 && (HOST_BITS_PER_WIDE_INT >= 64 || high == 0)) | |
02071907 | 9501 | || (low == ~0 && (HOST_BITS_PER_WIDE_INT >= 64 || high == ~0))) |
c5059423 AM |
9502 | return 0; |
9503 | ||
9504 | if (HOST_BITS_PER_WIDE_INT < 64 && low == 0) | |
9505 | { | |
02071907 | 9506 | shift_mask_high = ~0; |
c5059423 AM |
9507 | if (INTVAL (shiftop) > 32) |
9508 | shift_mask_high <<= INTVAL (shiftop) - 32; | |
9509 | ||
9510 | lsb = high & -high; | |
9511 | ||
9512 | if (-lsb != shift_mask_high || INTVAL (shiftop) < 32) | |
9513 | return 0; | |
9514 | ||
9515 | high = ~high; | |
9516 | high &= -lsb; | |
9517 | ||
9518 | lsb = high & -high; | |
9519 | return high == -lsb; | |
9520 | } | |
9521 | ||
02071907 | 9522 | shift_mask_low = ~0; |
c5059423 AM |
9523 | shift_mask_low <<= INTVAL (shiftop); |
9524 | ||
9525 | lsb = low & -low; | |
9526 | ||
9527 | if (-lsb != shift_mask_low) | |
9528 | return 0; | |
9529 | ||
9530 | if (HOST_BITS_PER_WIDE_INT < 64) | |
9531 | high = ~high; | |
9532 | low = ~low; | |
9533 | low &= -lsb; | |
9534 | ||
9535 | if (HOST_BITS_PER_WIDE_INT < 64 && low == 0) | |
9536 | { | |
9537 | lsb = high & -high; | |
9538 | return high == -lsb; | |
9539 | } | |
9540 | ||
9541 | lsb = low & -low; | |
9542 | return low == -lsb && (HOST_BITS_PER_WIDE_INT >= 64 || high == ~0); | |
9543 | } | |
9544 | else | |
9545 | return 0; | |
9546 | } | |
e2c953b6 | 9547 | |
c5059423 AM |
9548 | /* Return 1 if ANDOP is a mask suitable for use with an rldicr insn |
9549 | to perform a left shift. It must have SHIFTOP or more least | |
c1207243 | 9550 | significant 0's, with the remainder of the word 1's. */ |
e2c953b6 | 9551 | |
c5059423 | 9552 | int |
a2369ed3 | 9553 | includes_rldicr_lshift_p (rtx shiftop, rtx andop) |
c5059423 | 9554 | { |
e2c953b6 | 9555 | if (GET_CODE (andop) == CONST_INT) |
c5059423 | 9556 | { |
02071907 | 9557 | HOST_WIDE_INT c, lsb, shift_mask; |
c5059423 | 9558 | |
02071907 | 9559 | shift_mask = ~0; |
c5059423 AM |
9560 | shift_mask <<= INTVAL (shiftop); |
9561 | c = INTVAL (andop); | |
9562 | ||
c1207243 | 9563 | /* Find the least significant one bit. */ |
c5059423 AM |
9564 | lsb = c & -c; |
9565 | ||
9566 | /* It must be covered by the shift mask. | |
a4f6c312 | 9567 | This test also rejects c == 0. */ |
c5059423 AM |
9568 | if ((lsb & shift_mask) == 0) |
9569 | return 0; | |
9570 | ||
9571 | /* Check we have all 1's above the transition, and reject all 1's. */ | |
9572 | return c == -lsb && lsb != 1; | |
9573 | } | |
9574 | else if (GET_CODE (andop) == CONST_DOUBLE | |
9575 | && (GET_MODE (andop) == VOIDmode || GET_MODE (andop) == DImode)) | |
9576 | { | |
02071907 | 9577 | HOST_WIDE_INT low, lsb, shift_mask_low; |
c5059423 AM |
9578 | |
9579 | low = CONST_DOUBLE_LOW (andop); | |
9580 | ||
9581 | if (HOST_BITS_PER_WIDE_INT < 64) | |
9582 | { | |
02071907 | 9583 | HOST_WIDE_INT high, shift_mask_high; |
c5059423 AM |
9584 | |
9585 | high = CONST_DOUBLE_HIGH (andop); | |
9586 | ||
9587 | if (low == 0) | |
9588 | { | |
02071907 | 9589 | shift_mask_high = ~0; |
c5059423 AM |
9590 | if (INTVAL (shiftop) > 32) |
9591 | shift_mask_high <<= INTVAL (shiftop) - 32; | |
9592 | ||
9593 | lsb = high & -high; | |
9594 | ||
9595 | if ((lsb & shift_mask_high) == 0) | |
9596 | return 0; | |
9597 | ||
9598 | return high == -lsb; | |
9599 | } | |
9600 | if (high != ~0) | |
9601 | return 0; | |
9602 | } | |
9603 | ||
02071907 | 9604 | shift_mask_low = ~0; |
c5059423 AM |
9605 | shift_mask_low <<= INTVAL (shiftop); |
9606 | ||
9607 | lsb = low & -low; | |
9608 | ||
9609 | if ((lsb & shift_mask_low) == 0) | |
9610 | return 0; | |
9611 | ||
9612 | return low == -lsb && lsb != 1; | |
9613 | } | |
e2c953b6 | 9614 | else |
c5059423 | 9615 | return 0; |
9878760c | 9616 | } |
35068b43 | 9617 | |
11ac38b2 DE |
9618 | /* Return 1 if operands will generate a valid arguments to rlwimi |
9619 | instruction for insert with right shift in 64-bit mode. The mask may | |
9620 | not start on the first bit or stop on the last bit because wrap-around | |
9621 | effects of instruction do not correspond to semantics of RTL insn. */ | |
9622 | ||
9623 | int | |
9624 | insvdi_rshift_rlwimi_p (rtx sizeop, rtx startop, rtx shiftop) | |
9625 | { | |
9626 | if (INTVAL (startop) < 64 | |
9627 | && INTVAL (startop) > 32 | |
9628 | && (INTVAL (sizeop) + INTVAL (startop) < 64) | |
9629 | && (INTVAL (sizeop) + INTVAL (startop) > 33) | |
9630 | && (INTVAL (sizeop) + INTVAL (startop) + INTVAL (shiftop) < 96) | |
9631 | && (INTVAL (sizeop) + INTVAL (startop) + INTVAL (shiftop) >= 64) | |
9632 | && (64 - (INTVAL (shiftop) & 63)) >= INTVAL (sizeop)) | |
9633 | return 1; | |
9634 | ||
9635 | return 0; | |
9636 | } | |
9637 | ||
35068b43 | 9638 | /* Return 1 if REGNO (reg1) == REGNO (reg2) - 1 making them candidates |
90f81f99 | 9639 | for lfq and stfq insns iff the registers are hard registers. */ |
35068b43 RK |
9640 | |
9641 | int | |
a2369ed3 | 9642 | registers_ok_for_quad_peep (rtx reg1, rtx reg2) |
35068b43 RK |
9643 | { |
9644 | /* We might have been passed a SUBREG. */ | |
f676971a | 9645 | if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG) |
35068b43 | 9646 | return 0; |
f676971a | 9647 | |
90f81f99 AP |
9648 | /* We might have been passed non floating point registers. */ |
9649 | if (!FP_REGNO_P (REGNO (reg1)) | |
9650 | || !FP_REGNO_P (REGNO (reg2))) | |
9651 | return 0; | |
35068b43 RK |
9652 | |
9653 | return (REGNO (reg1) == REGNO (reg2) - 1); | |
9654 | } | |
9655 | ||
a4f6c312 SS |
9656 | /* Return 1 if addr1 and addr2 are suitable for lfq or stfq insn. |
9657 | addr1 and addr2 must be in consecutive memory locations | |
9658 | (addr2 == addr1 + 8). */ | |
35068b43 RK |
9659 | |
9660 | int | |
90f81f99 | 9661 | mems_ok_for_quad_peep (rtx mem1, rtx mem2) |
35068b43 | 9662 | { |
90f81f99 | 9663 | rtx addr1, addr2; |
e2c953b6 | 9664 | unsigned int reg1; |
35068b43 RK |
9665 | int offset1; |
9666 | ||
90f81f99 AP |
9667 | /* The mems cannot be volatile. */ |
9668 | if (MEM_VOLATILE_P (mem1) || MEM_VOLATILE_P (mem2)) | |
9669 | return 0; | |
f676971a | 9670 | |
90f81f99 AP |
9671 | addr1 = XEXP (mem1, 0); |
9672 | addr2 = XEXP (mem2, 0); | |
9673 | ||
35068b43 RK |
9674 | /* Extract an offset (if used) from the first addr. */ |
9675 | if (GET_CODE (addr1) == PLUS) | |
9676 | { | |
9677 | /* If not a REG, return zero. */ | |
9678 | if (GET_CODE (XEXP (addr1, 0)) != REG) | |
9679 | return 0; | |
9680 | else | |
9681 | { | |
c4ad648e | 9682 | reg1 = REGNO (XEXP (addr1, 0)); |
35068b43 RK |
9683 | /* The offset must be constant! */ |
9684 | if (GET_CODE (XEXP (addr1, 1)) != CONST_INT) | |
c4ad648e AM |
9685 | return 0; |
9686 | offset1 = INTVAL (XEXP (addr1, 1)); | |
35068b43 RK |
9687 | } |
9688 | } | |
9689 | else if (GET_CODE (addr1) != REG) | |
9690 | return 0; | |
9691 | else | |
9692 | { | |
9693 | reg1 = REGNO (addr1); | |
9694 | /* This was a simple (mem (reg)) expression. Offset is 0. */ | |
9695 | offset1 = 0; | |
9696 | } | |
9697 | ||
a2369ed3 | 9698 | /* Make sure the second address is a (mem (plus (reg) (const_int))) |
f676971a | 9699 | or if it is (mem (reg)) then make sure that offset1 is -8 and the same |
0f6937fe | 9700 | register as addr1. */ |
984e25ac | 9701 | if (offset1 == -8 && GET_CODE (addr2) == REG && reg1 == REGNO (addr2)) |
0f6937fe | 9702 | return 1; |
35068b43 RK |
9703 | if (GET_CODE (addr2) != PLUS) |
9704 | return 0; | |
9705 | ||
9706 | if (GET_CODE (XEXP (addr2, 0)) != REG | |
9707 | || GET_CODE (XEXP (addr2, 1)) != CONST_INT) | |
9708 | return 0; | |
9709 | ||
9710 | if (reg1 != REGNO (XEXP (addr2, 0))) | |
9711 | return 0; | |
9712 | ||
9713 | /* The offset for the second addr must be 8 more than the first addr. */ | |
9714 | if (INTVAL (XEXP (addr2, 1)) != offset1 + 8) | |
9715 | return 0; | |
9716 | ||
9717 | /* All the tests passed. addr1 and addr2 are valid for lfq or stfq | |
9718 | instructions. */ | |
9719 | return 1; | |
9720 | } | |
9878760c RK |
9721 | \f |
9722 | /* Return the register class of a scratch register needed to copy IN into | |
9723 | or out of a register in CLASS in MODE. If it can be done directly, | |
9724 | NO_REGS is returned. */ | |
9725 | ||
9726 | enum reg_class | |
f676971a | 9727 | secondary_reload_class (enum reg_class class, |
a9baceb1 GK |
9728 | enum machine_mode mode ATTRIBUTE_UNUSED, |
9729 | rtx in) | |
9878760c | 9730 | { |
5accd822 | 9731 | int regno; |
9878760c | 9732 | |
ab82a49f AP |
9733 | if (TARGET_ELF || (DEFAULT_ABI == ABI_DARWIN |
9734 | #if TARGET_MACHO | |
c4ad648e | 9735 | && MACHOPIC_INDIRECT |
ab82a49f | 9736 | #endif |
c4ad648e | 9737 | )) |
46fad5b7 DJ |
9738 | { |
9739 | /* We cannot copy a symbolic operand directly into anything | |
c4ad648e AM |
9740 | other than BASE_REGS for TARGET_ELF. So indicate that a |
9741 | register from BASE_REGS is needed as an intermediate | |
9742 | register. | |
f676971a | 9743 | |
46fad5b7 DJ |
9744 | On Darwin, pic addresses require a load from memory, which |
9745 | needs a base register. */ | |
9746 | if (class != BASE_REGS | |
c4ad648e AM |
9747 | && (GET_CODE (in) == SYMBOL_REF |
9748 | || GET_CODE (in) == HIGH | |
9749 | || GET_CODE (in) == LABEL_REF | |
9750 | || GET_CODE (in) == CONST)) | |
9751 | return BASE_REGS; | |
46fad5b7 | 9752 | } |
e7b7998a | 9753 | |
5accd822 DE |
9754 | if (GET_CODE (in) == REG) |
9755 | { | |
9756 | regno = REGNO (in); | |
9757 | if (regno >= FIRST_PSEUDO_REGISTER) | |
9758 | { | |
9759 | regno = true_regnum (in); | |
9760 | if (regno >= FIRST_PSEUDO_REGISTER) | |
9761 | regno = -1; | |
9762 | } | |
9763 | } | |
9764 | else if (GET_CODE (in) == SUBREG) | |
9765 | { | |
9766 | regno = true_regnum (in); | |
9767 | if (regno >= FIRST_PSEUDO_REGISTER) | |
9768 | regno = -1; | |
9769 | } | |
9770 | else | |
9771 | regno = -1; | |
9772 | ||
9878760c RK |
9773 | /* We can place anything into GENERAL_REGS and can put GENERAL_REGS |
9774 | into anything. */ | |
9775 | if (class == GENERAL_REGS || class == BASE_REGS | |
9776 | || (regno >= 0 && INT_REGNO_P (regno))) | |
9777 | return NO_REGS; | |
9778 | ||
9779 | /* Constants, memory, and FP registers can go into FP registers. */ | |
9780 | if ((regno == -1 || FP_REGNO_P (regno)) | |
9781 | && (class == FLOAT_REGS || class == NON_SPECIAL_REGS)) | |
9782 | return NO_REGS; | |
9783 | ||
0ac081f6 AH |
9784 | /* Memory, and AltiVec registers can go into AltiVec registers. */ |
9785 | if ((regno == -1 || ALTIVEC_REGNO_P (regno)) | |
9786 | && class == ALTIVEC_REGS) | |
9787 | return NO_REGS; | |
9788 | ||
9878760c RK |
9789 | /* We can copy among the CR registers. */ |
9790 | if ((class == CR_REGS || class == CR0_REGS) | |
9791 | && regno >= 0 && CR_REGNO_P (regno)) | |
9792 | return NO_REGS; | |
9793 | ||
9794 | /* Otherwise, we need GENERAL_REGS. */ | |
9795 | return GENERAL_REGS; | |
9796 | } | |
9797 | \f | |
9798 | /* Given a comparison operation, return the bit number in CCR to test. We | |
f676971a | 9799 | know this is a valid comparison. |
9878760c RK |
9800 | |
9801 | SCC_P is 1 if this is for an scc. That means that %D will have been | |
9802 | used instead of %C, so the bits will be in different places. | |
9803 | ||
b4ac57ab | 9804 | Return -1 if OP isn't a valid comparison for some reason. */ |
9878760c RK |
9805 | |
9806 | int | |
a2369ed3 | 9807 | ccr_bit (rtx op, int scc_p) |
9878760c RK |
9808 | { |
9809 | enum rtx_code code = GET_CODE (op); | |
9810 | enum machine_mode cc_mode; | |
9811 | int cc_regnum; | |
9812 | int base_bit; | |
9ebbca7d | 9813 | rtx reg; |
9878760c | 9814 | |
ec8e098d | 9815 | if (!COMPARISON_P (op)) |
9878760c RK |
9816 | return -1; |
9817 | ||
9ebbca7d GK |
9818 | reg = XEXP (op, 0); |
9819 | ||
9820 | if (GET_CODE (reg) != REG | |
9821 | || ! CR_REGNO_P (REGNO (reg))) | |
9822 | abort (); | |
9823 | ||
9824 | cc_mode = GET_MODE (reg); | |
9825 | cc_regnum = REGNO (reg); | |
9826 | base_bit = 4 * (cc_regnum - CR0_REGNO); | |
9878760c | 9827 | |
39a10a29 | 9828 | validate_condition_mode (code, cc_mode); |
c5defebb | 9829 | |
b7053a3f GK |
9830 | /* When generating a sCOND operation, only positive conditions are |
9831 | allowed. */ | |
9832 | if (scc_p && code != EQ && code != GT && code != LT && code != UNORDERED | |
9833 | && code != GTU && code != LTU) | |
9834 | abort (); | |
f676971a | 9835 | |
9878760c RK |
9836 | switch (code) |
9837 | { | |
9838 | case NE: | |
9839 | return scc_p ? base_bit + 3 : base_bit + 2; | |
9840 | case EQ: | |
9841 | return base_bit + 2; | |
1c882ea4 | 9842 | case GT: case GTU: case UNLE: |
9878760c | 9843 | return base_bit + 1; |
1c882ea4 | 9844 | case LT: case LTU: case UNGE: |
9878760c | 9845 | return base_bit; |
1c882ea4 GK |
9846 | case ORDERED: case UNORDERED: |
9847 | return base_bit + 3; | |
9878760c RK |
9848 | |
9849 | case GE: case GEU: | |
39a10a29 | 9850 | /* If scc, we will have done a cror to put the bit in the |
9878760c RK |
9851 | unordered position. So test that bit. For integer, this is ! LT |
9852 | unless this is an scc insn. */ | |
39a10a29 | 9853 | return scc_p ? base_bit + 3 : base_bit; |
9878760c RK |
9854 | |
9855 | case LE: case LEU: | |
39a10a29 | 9856 | return scc_p ? base_bit + 3 : base_bit + 1; |
1c882ea4 | 9857 | |
9878760c RK |
9858 | default: |
9859 | abort (); | |
9860 | } | |
9861 | } | |
1ff7789b | 9862 | \f |
8d30c4ee | 9863 | /* Return the GOT register. */ |
1ff7789b MM |
9864 | |
9865 | struct rtx_def * | |
a2369ed3 | 9866 | rs6000_got_register (rtx value ATTRIBUTE_UNUSED) |
1ff7789b | 9867 | { |
a4f6c312 SS |
9868 | /* The second flow pass currently (June 1999) can't update |
9869 | regs_ever_live without disturbing other parts of the compiler, so | |
9870 | update it here to make the prolog/epilogue code happy. */ | |
1db02437 FS |
9871 | if (no_new_pseudos && ! regs_ever_live[RS6000_PIC_OFFSET_TABLE_REGNUM]) |
9872 | regs_ever_live[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1; | |
1ff7789b | 9873 | |
8d30c4ee | 9874 | current_function_uses_pic_offset_table = 1; |
3cb999d8 | 9875 | |
1ff7789b MM |
9876 | return pic_offset_table_rtx; |
9877 | } | |
a7df97e6 | 9878 | \f |
e2500fed GK |
9879 | /* Function to init struct machine_function. |
9880 | This will be called, via a pointer variable, | |
9881 | from push_function_context. */ | |
a7df97e6 | 9882 | |
e2500fed | 9883 | static struct machine_function * |
863d938c | 9884 | rs6000_init_machine_status (void) |
a7df97e6 | 9885 | { |
e2500fed | 9886 | return ggc_alloc_cleared (sizeof (machine_function)); |
a7df97e6 | 9887 | } |
9878760c | 9888 | \f |
0ba1b2ff AM |
9889 | /* These macros test for integers and extract the low-order bits. */ |
9890 | #define INT_P(X) \ | |
9891 | ((GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST_DOUBLE) \ | |
9892 | && GET_MODE (X) == VOIDmode) | |
9893 | ||
9894 | #define INT_LOWPART(X) \ | |
9895 | (GET_CODE (X) == CONST_INT ? INTVAL (X) : CONST_DOUBLE_LOW (X)) | |
9896 | ||
9897 | int | |
a2369ed3 | 9898 | extract_MB (rtx op) |
0ba1b2ff AM |
9899 | { |
9900 | int i; | |
9901 | unsigned long val = INT_LOWPART (op); | |
9902 | ||
9903 | /* If the high bit is zero, the value is the first 1 bit we find | |
9904 | from the left. */ | |
9905 | if ((val & 0x80000000) == 0) | |
9906 | { | |
9907 | if ((val & 0xffffffff) == 0) | |
9908 | abort (); | |
9909 | ||
9910 | i = 1; | |
9911 | while (((val <<= 1) & 0x80000000) == 0) | |
9912 | ++i; | |
9913 | return i; | |
9914 | } | |
9915 | ||
9916 | /* If the high bit is set and the low bit is not, or the mask is all | |
9917 | 1's, the value is zero. */ | |
9918 | if ((val & 1) == 0 || (val & 0xffffffff) == 0xffffffff) | |
9919 | return 0; | |
9920 | ||
9921 | /* Otherwise we have a wrap-around mask. Look for the first 0 bit | |
9922 | from the right. */ | |
9923 | i = 31; | |
9924 | while (((val >>= 1) & 1) != 0) | |
9925 | --i; | |
9926 | ||
9927 | return i; | |
9928 | } | |
9929 | ||
9930 | int | |
a2369ed3 | 9931 | extract_ME (rtx op) |
0ba1b2ff AM |
9932 | { |
9933 | int i; | |
9934 | unsigned long val = INT_LOWPART (op); | |
9935 | ||
9936 | /* If the low bit is zero, the value is the first 1 bit we find from | |
9937 | the right. */ | |
9938 | if ((val & 1) == 0) | |
9939 | { | |
9940 | if ((val & 0xffffffff) == 0) | |
9941 | abort (); | |
9942 | ||
9943 | i = 30; | |
9944 | while (((val >>= 1) & 1) == 0) | |
9945 | --i; | |
9946 | ||
9947 | return i; | |
9948 | } | |
9949 | ||
9950 | /* If the low bit is set and the high bit is not, or the mask is all | |
9951 | 1's, the value is 31. */ | |
9952 | if ((val & 0x80000000) == 0 || (val & 0xffffffff) == 0xffffffff) | |
9953 | return 31; | |
9954 | ||
9955 | /* Otherwise we have a wrap-around mask. Look for the first 0 bit | |
9956 | from the left. */ | |
9957 | i = 0; | |
9958 | while (((val <<= 1) & 0x80000000) != 0) | |
9959 | ++i; | |
9960 | ||
9961 | return i; | |
9962 | } | |
9963 | ||
c4501e62 JJ |
9964 | /* Locate some local-dynamic symbol still in use by this function |
9965 | so that we can print its name in some tls_ld pattern. */ | |
9966 | ||
9967 | static const char * | |
863d938c | 9968 | rs6000_get_some_local_dynamic_name (void) |
c4501e62 JJ |
9969 | { |
9970 | rtx insn; | |
9971 | ||
9972 | if (cfun->machine->some_ld_name) | |
9973 | return cfun->machine->some_ld_name; | |
9974 | ||
9975 | for (insn = get_insns (); insn ; insn = NEXT_INSN (insn)) | |
9976 | if (INSN_P (insn) | |
9977 | && for_each_rtx (&PATTERN (insn), | |
9978 | rs6000_get_some_local_dynamic_name_1, 0)) | |
9979 | return cfun->machine->some_ld_name; | |
9980 | ||
9981 | abort (); | |
9982 | } | |
9983 | ||
9984 | /* Helper function for rs6000_get_some_local_dynamic_name. */ | |
9985 | ||
9986 | static int | |
a2369ed3 | 9987 | rs6000_get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED) |
c4501e62 JJ |
9988 | { |
9989 | rtx x = *px; | |
9990 | ||
9991 | if (GET_CODE (x) == SYMBOL_REF) | |
9992 | { | |
9993 | const char *str = XSTR (x, 0); | |
9994 | if (SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC) | |
9995 | { | |
9996 | cfun->machine->some_ld_name = str; | |
9997 | return 1; | |
9998 | } | |
9999 | } | |
10000 | ||
10001 | return 0; | |
10002 | } | |
10003 | ||
85b776df AM |
10004 | /* Write out a function code label. */ |
10005 | ||
10006 | void | |
10007 | rs6000_output_function_entry (FILE *file, const char *fname) | |
10008 | { | |
10009 | if (fname[0] != '.') | |
10010 | { | |
10011 | switch (DEFAULT_ABI) | |
10012 | { | |
10013 | default: | |
10014 | abort (); | |
10015 | ||
10016 | case ABI_AIX: | |
10017 | if (DOT_SYMBOLS) | |
10018 | putc ('.', file); | |
10019 | else | |
10020 | ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "L."); | |
10021 | break; | |
10022 | ||
10023 | case ABI_V4: | |
10024 | case ABI_DARWIN: | |
10025 | break; | |
10026 | } | |
10027 | } | |
10028 | if (TARGET_AIX) | |
10029 | RS6000_OUTPUT_BASENAME (file, fname); | |
10030 | else | |
10031 | assemble_name (file, fname); | |
10032 | } | |
10033 | ||
9878760c RK |
10034 | /* Print an operand. Recognize special options, documented below. */ |
10035 | ||
38c1f2d7 | 10036 | #if TARGET_ELF |
d9407988 | 10037 | #define SMALL_DATA_RELOC ((rs6000_sdata == SDATA_EABI) ? "sda21" : "sdarel") |
8fbd2dc7 | 10038 | #define SMALL_DATA_REG ((rs6000_sdata == SDATA_EABI) ? 0 : 13) |
ba5e43aa MM |
10039 | #else |
10040 | #define SMALL_DATA_RELOC "sda21" | |
8fbd2dc7 | 10041 | #define SMALL_DATA_REG 0 |
ba5e43aa MM |
10042 | #endif |
10043 | ||
9878760c | 10044 | void |
a2369ed3 | 10045 | print_operand (FILE *file, rtx x, int code) |
9878760c RK |
10046 | { |
10047 | int i; | |
a260abc9 | 10048 | HOST_WIDE_INT val; |
0ba1b2ff | 10049 | unsigned HOST_WIDE_INT uval; |
9878760c RK |
10050 | |
10051 | switch (code) | |
10052 | { | |
a8b3aeda | 10053 | case '.': |
a85d226b RK |
10054 | /* Write out an instruction after the call which may be replaced |
10055 | with glue code by the loader. This depends on the AIX version. */ | |
10056 | asm_fprintf (file, RS6000_CALL_GLUE); | |
a8b3aeda RK |
10057 | return; |
10058 | ||
81eace42 GK |
10059 | /* %a is output_address. */ |
10060 | ||
9854d9ed RK |
10061 | case 'A': |
10062 | /* If X is a constant integer whose low-order 5 bits are zero, | |
10063 | write 'l'. Otherwise, write 'r'. This is a kludge to fix a bug | |
76229ac8 | 10064 | in the AIX assembler where "sri" with a zero shift count |
20e26713 | 10065 | writes a trash instruction. */ |
9854d9ed | 10066 | if (GET_CODE (x) == CONST_INT && (INTVAL (x) & 31) == 0) |
76229ac8 | 10067 | putc ('l', file); |
9854d9ed | 10068 | else |
76229ac8 | 10069 | putc ('r', file); |
9854d9ed RK |
10070 | return; |
10071 | ||
10072 | case 'b': | |
e2c953b6 DE |
10073 | /* If constant, low-order 16 bits of constant, unsigned. |
10074 | Otherwise, write normally. */ | |
10075 | if (INT_P (x)) | |
10076 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 0xffff); | |
10077 | else | |
10078 | print_operand (file, x, 0); | |
cad12a8d RK |
10079 | return; |
10080 | ||
a260abc9 DE |
10081 | case 'B': |
10082 | /* If the low-order bit is zero, write 'r'; otherwise, write 'l' | |
10083 | for 64-bit mask direction. */ | |
296b8152 | 10084 | putc (((INT_LOWPART(x) & 1) == 0 ? 'r' : 'l'), file); |
a238cd8b | 10085 | return; |
a260abc9 | 10086 | |
81eace42 GK |
10087 | /* %c is output_addr_const if a CONSTANT_ADDRESS_P, otherwise |
10088 | output_operand. */ | |
10089 | ||
423c1189 AH |
10090 | case 'c': |
10091 | /* X is a CR register. Print the number of the GT bit of the CR. */ | |
10092 | if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x))) | |
10093 | output_operand_lossage ("invalid %%E value"); | |
10094 | else | |
10095 | fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO) + 1); | |
10096 | return; | |
10097 | ||
10098 | case 'D': | |
6b1fedc3 | 10099 | /* Like 'J' but get to the EQ bit. */ |
423c1189 AH |
10100 | if (GET_CODE (x) != REG) |
10101 | abort (); | |
10102 | ||
6b1fedc3 AH |
10103 | /* Bit 1 is EQ bit. */ |
10104 | i = 4 * (REGNO (x) - CR0_REGNO) + 2; | |
423c1189 AH |
10105 | |
10106 | /* If we want bit 31, write a shift count of zero, not 32. */ | |
10107 | fprintf (file, "%d", i == 31 ? 0 : i + 1); | |
10108 | return; | |
10109 | ||
9854d9ed | 10110 | case 'E': |
39a10a29 | 10111 | /* X is a CR register. Print the number of the EQ bit of the CR */ |
9854d9ed RK |
10112 | if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x))) |
10113 | output_operand_lossage ("invalid %%E value"); | |
78fbdbf7 | 10114 | else |
39a10a29 | 10115 | fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO) + 2); |
a85d226b | 10116 | return; |
9854d9ed RK |
10117 | |
10118 | case 'f': | |
10119 | /* X is a CR register. Print the shift count needed to move it | |
10120 | to the high-order four bits. */ | |
10121 | if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x))) | |
10122 | output_operand_lossage ("invalid %%f value"); | |
10123 | else | |
9ebbca7d | 10124 | fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO)); |
9854d9ed RK |
10125 | return; |
10126 | ||
10127 | case 'F': | |
10128 | /* Similar, but print the count for the rotate in the opposite | |
10129 | direction. */ | |
10130 | if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x))) | |
10131 | output_operand_lossage ("invalid %%F value"); | |
10132 | else | |
9ebbca7d | 10133 | fprintf (file, "%d", 32 - 4 * (REGNO (x) - CR0_REGNO)); |
9854d9ed RK |
10134 | return; |
10135 | ||
10136 | case 'G': | |
10137 | /* X is a constant integer. If it is negative, print "m", | |
43aa4e05 | 10138 | otherwise print "z". This is to make an aze or ame insn. */ |
9854d9ed RK |
10139 | if (GET_CODE (x) != CONST_INT) |
10140 | output_operand_lossage ("invalid %%G value"); | |
10141 | else if (INTVAL (x) >= 0) | |
76229ac8 | 10142 | putc ('z', file); |
9854d9ed | 10143 | else |
76229ac8 | 10144 | putc ('m', file); |
9854d9ed | 10145 | return; |
e2c953b6 | 10146 | |
9878760c | 10147 | case 'h': |
a4f6c312 SS |
10148 | /* If constant, output low-order five bits. Otherwise, write |
10149 | normally. */ | |
9878760c | 10150 | if (INT_P (x)) |
5f59ecb7 | 10151 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 31); |
9878760c RK |
10152 | else |
10153 | print_operand (file, x, 0); | |
10154 | return; | |
10155 | ||
64305719 | 10156 | case 'H': |
a4f6c312 SS |
10157 | /* If constant, output low-order six bits. Otherwise, write |
10158 | normally. */ | |
64305719 | 10159 | if (INT_P (x)) |
5f59ecb7 | 10160 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 63); |
64305719 DE |
10161 | else |
10162 | print_operand (file, x, 0); | |
10163 | return; | |
10164 | ||
9854d9ed RK |
10165 | case 'I': |
10166 | /* Print `i' if this is a constant, else nothing. */ | |
9878760c | 10167 | if (INT_P (x)) |
76229ac8 | 10168 | putc ('i', file); |
9878760c RK |
10169 | return; |
10170 | ||
9854d9ed RK |
10171 | case 'j': |
10172 | /* Write the bit number in CCR for jump. */ | |
10173 | i = ccr_bit (x, 0); | |
10174 | if (i == -1) | |
10175 | output_operand_lossage ("invalid %%j code"); | |
9878760c | 10176 | else |
9854d9ed | 10177 | fprintf (file, "%d", i); |
9878760c RK |
10178 | return; |
10179 | ||
9854d9ed RK |
10180 | case 'J': |
10181 | /* Similar, but add one for shift count in rlinm for scc and pass | |
10182 | scc flag to `ccr_bit'. */ | |
10183 | i = ccr_bit (x, 1); | |
10184 | if (i == -1) | |
10185 | output_operand_lossage ("invalid %%J code"); | |
10186 | else | |
a0466a68 RK |
10187 | /* If we want bit 31, write a shift count of zero, not 32. */ |
10188 | fprintf (file, "%d", i == 31 ? 0 : i + 1); | |
9878760c RK |
10189 | return; |
10190 | ||
9854d9ed RK |
10191 | case 'k': |
10192 | /* X must be a constant. Write the 1's complement of the | |
10193 | constant. */ | |
9878760c | 10194 | if (! INT_P (x)) |
9854d9ed | 10195 | output_operand_lossage ("invalid %%k value"); |
e2c953b6 DE |
10196 | else |
10197 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, ~ INT_LOWPART (x)); | |
9878760c RK |
10198 | return; |
10199 | ||
81eace42 | 10200 | case 'K': |
9ebbca7d GK |
10201 | /* X must be a symbolic constant on ELF. Write an |
10202 | expression suitable for an 'addi' that adds in the low 16 | |
10203 | bits of the MEM. */ | |
10204 | if (GET_CODE (x) != CONST) | |
10205 | { | |
10206 | print_operand_address (file, x); | |
10207 | fputs ("@l", file); | |
10208 | } | |
10209 | else | |
10210 | { | |
10211 | if (GET_CODE (XEXP (x, 0)) != PLUS | |
10212 | || (GET_CODE (XEXP (XEXP (x, 0), 0)) != SYMBOL_REF | |
10213 | && GET_CODE (XEXP (XEXP (x, 0), 0)) != LABEL_REF) | |
10214 | || GET_CODE (XEXP (XEXP (x, 0), 1)) != CONST_INT) | |
53cd5d6c | 10215 | output_operand_lossage ("invalid %%K value"); |
9ebbca7d GK |
10216 | print_operand_address (file, XEXP (XEXP (x, 0), 0)); |
10217 | fputs ("@l", file); | |
ed8d2920 MM |
10218 | /* For GNU as, there must be a non-alphanumeric character |
10219 | between 'l' and the number. The '-' is added by | |
10220 | print_operand() already. */ | |
10221 | if (INTVAL (XEXP (XEXP (x, 0), 1)) >= 0) | |
10222 | fputs ("+", file); | |
9ebbca7d GK |
10223 | print_operand (file, XEXP (XEXP (x, 0), 1), 0); |
10224 | } | |
81eace42 GK |
10225 | return; |
10226 | ||
10227 | /* %l is output_asm_label. */ | |
9ebbca7d | 10228 | |
9854d9ed RK |
10229 | case 'L': |
10230 | /* Write second word of DImode or DFmode reference. Works on register | |
10231 | or non-indexed memory only. */ | |
10232 | if (GET_CODE (x) == REG) | |
fb5c67a7 | 10233 | fputs (reg_names[REGNO (x) + 1], file); |
9854d9ed RK |
10234 | else if (GET_CODE (x) == MEM) |
10235 | { | |
10236 | /* Handle possible auto-increment. Since it is pre-increment and | |
1427100a | 10237 | we have already done it, we can just use an offset of word. */ |
9854d9ed RK |
10238 | if (GET_CODE (XEXP (x, 0)) == PRE_INC |
10239 | || GET_CODE (XEXP (x, 0)) == PRE_DEC) | |
ed8908e7 RK |
10240 | output_address (plus_constant (XEXP (XEXP (x, 0), 0), |
10241 | UNITS_PER_WORD)); | |
9854d9ed | 10242 | else |
d7624dc0 RK |
10243 | output_address (XEXP (adjust_address_nv (x, SImode, |
10244 | UNITS_PER_WORD), | |
10245 | 0)); | |
ed8908e7 | 10246 | |
ba5e43aa | 10247 | if (small_data_operand (x, GET_MODE (x))) |
8fbd2dc7 MM |
10248 | fprintf (file, "@%s(%s)", SMALL_DATA_RELOC, |
10249 | reg_names[SMALL_DATA_REG]); | |
9854d9ed | 10250 | } |
9878760c | 10251 | return; |
f676971a | 10252 | |
9878760c RK |
10253 | case 'm': |
10254 | /* MB value for a mask operand. */ | |
b1765bde | 10255 | if (! mask_operand (x, SImode)) |
9878760c RK |
10256 | output_operand_lossage ("invalid %%m value"); |
10257 | ||
0ba1b2ff | 10258 | fprintf (file, "%d", extract_MB (x)); |
9878760c RK |
10259 | return; |
10260 | ||
10261 | case 'M': | |
10262 | /* ME value for a mask operand. */ | |
b1765bde | 10263 | if (! mask_operand (x, SImode)) |
a260abc9 | 10264 | output_operand_lossage ("invalid %%M value"); |
9878760c | 10265 | |
0ba1b2ff | 10266 | fprintf (file, "%d", extract_ME (x)); |
9878760c RK |
10267 | return; |
10268 | ||
81eace42 GK |
10269 | /* %n outputs the negative of its operand. */ |
10270 | ||
9878760c RK |
10271 | case 'N': |
10272 | /* Write the number of elements in the vector times 4. */ | |
10273 | if (GET_CODE (x) != PARALLEL) | |
10274 | output_operand_lossage ("invalid %%N value"); | |
e2c953b6 DE |
10275 | else |
10276 | fprintf (file, "%d", XVECLEN (x, 0) * 4); | |
9878760c RK |
10277 | return; |
10278 | ||
10279 | case 'O': | |
10280 | /* Similar, but subtract 1 first. */ | |
10281 | if (GET_CODE (x) != PARALLEL) | |
1427100a | 10282 | output_operand_lossage ("invalid %%O value"); |
e2c953b6 DE |
10283 | else |
10284 | fprintf (file, "%d", (XVECLEN (x, 0) - 1) * 4); | |
9878760c RK |
10285 | return; |
10286 | ||
9854d9ed RK |
10287 | case 'p': |
10288 | /* X is a CONST_INT that is a power of two. Output the logarithm. */ | |
10289 | if (! INT_P (x) | |
2bfcf297 | 10290 | || INT_LOWPART (x) < 0 |
9854d9ed RK |
10291 | || (i = exact_log2 (INT_LOWPART (x))) < 0) |
10292 | output_operand_lossage ("invalid %%p value"); | |
e2c953b6 DE |
10293 | else |
10294 | fprintf (file, "%d", i); | |
9854d9ed RK |
10295 | return; |
10296 | ||
9878760c RK |
10297 | case 'P': |
10298 | /* The operand must be an indirect memory reference. The result | |
8bb418a3 | 10299 | is the register name. */ |
9878760c RK |
10300 | if (GET_CODE (x) != MEM || GET_CODE (XEXP (x, 0)) != REG |
10301 | || REGNO (XEXP (x, 0)) >= 32) | |
10302 | output_operand_lossage ("invalid %%P value"); | |
e2c953b6 | 10303 | else |
fb5c67a7 | 10304 | fputs (reg_names[REGNO (XEXP (x, 0))], file); |
9878760c RK |
10305 | return; |
10306 | ||
dfbdccdb GK |
10307 | case 'q': |
10308 | /* This outputs the logical code corresponding to a boolean | |
10309 | expression. The expression may have one or both operands | |
39a10a29 | 10310 | negated (if one, only the first one). For condition register |
c4ad648e AM |
10311 | logical operations, it will also treat the negated |
10312 | CR codes as NOTs, but not handle NOTs of them. */ | |
dfbdccdb | 10313 | { |
63bc1d05 | 10314 | const char *const *t = 0; |
dfbdccdb GK |
10315 | const char *s; |
10316 | enum rtx_code code = GET_CODE (x); | |
10317 | static const char * const tbl[3][3] = { | |
10318 | { "and", "andc", "nor" }, | |
10319 | { "or", "orc", "nand" }, | |
10320 | { "xor", "eqv", "xor" } }; | |
10321 | ||
10322 | if (code == AND) | |
10323 | t = tbl[0]; | |
10324 | else if (code == IOR) | |
10325 | t = tbl[1]; | |
10326 | else if (code == XOR) | |
10327 | t = tbl[2]; | |
10328 | else | |
10329 | output_operand_lossage ("invalid %%q value"); | |
10330 | ||
10331 | if (GET_CODE (XEXP (x, 0)) != NOT) | |
10332 | s = t[0]; | |
10333 | else | |
10334 | { | |
10335 | if (GET_CODE (XEXP (x, 1)) == NOT) | |
10336 | s = t[2]; | |
10337 | else | |
10338 | s = t[1]; | |
10339 | } | |
f676971a | 10340 | |
dfbdccdb GK |
10341 | fputs (s, file); |
10342 | } | |
10343 | return; | |
10344 | ||
2c4a9cff DE |
10345 | case 'Q': |
10346 | if (TARGET_MFCRF) | |
3b6ce0af | 10347 | fputc (',', file); |
5efb1046 | 10348 | /* FALLTHRU */ |
2c4a9cff DE |
10349 | else |
10350 | return; | |
10351 | ||
9854d9ed RK |
10352 | case 'R': |
10353 | /* X is a CR register. Print the mask for `mtcrf'. */ | |
10354 | if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x))) | |
10355 | output_operand_lossage ("invalid %%R value"); | |
10356 | else | |
9ebbca7d | 10357 | fprintf (file, "%d", 128 >> (REGNO (x) - CR0_REGNO)); |
9878760c | 10358 | return; |
9854d9ed RK |
10359 | |
10360 | case 's': | |
10361 | /* Low 5 bits of 32 - value */ | |
10362 | if (! INT_P (x)) | |
10363 | output_operand_lossage ("invalid %%s value"); | |
e2c953b6 DE |
10364 | else |
10365 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, (32 - INT_LOWPART (x)) & 31); | |
9878760c | 10366 | return; |
9854d9ed | 10367 | |
a260abc9 | 10368 | case 'S': |
0ba1b2ff | 10369 | /* PowerPC64 mask position. All 0's is excluded. |
a260abc9 DE |
10370 | CONST_INT 32-bit mask is considered sign-extended so any |
10371 | transition must occur within the CONST_INT, not on the boundary. */ | |
b1765bde | 10372 | if (! mask64_operand (x, DImode)) |
a260abc9 DE |
10373 | output_operand_lossage ("invalid %%S value"); |
10374 | ||
0ba1b2ff | 10375 | uval = INT_LOWPART (x); |
a260abc9 | 10376 | |
0ba1b2ff | 10377 | if (uval & 1) /* Clear Left */ |
a260abc9 | 10378 | { |
f099d360 GK |
10379 | #if HOST_BITS_PER_WIDE_INT > 64 |
10380 | uval &= ((unsigned HOST_WIDE_INT) 1 << 64) - 1; | |
10381 | #endif | |
0ba1b2ff | 10382 | i = 64; |
a260abc9 | 10383 | } |
0ba1b2ff | 10384 | else /* Clear Right */ |
a260abc9 | 10385 | { |
0ba1b2ff | 10386 | uval = ~uval; |
f099d360 GK |
10387 | #if HOST_BITS_PER_WIDE_INT > 64 |
10388 | uval &= ((unsigned HOST_WIDE_INT) 1 << 64) - 1; | |
10389 | #endif | |
0ba1b2ff | 10390 | i = 63; |
a260abc9 | 10391 | } |
0ba1b2ff AM |
10392 | while (uval != 0) |
10393 | --i, uval >>= 1; | |
10394 | if (i < 0) | |
10395 | abort (); | |
10396 | fprintf (file, "%d", i); | |
10397 | return; | |
a260abc9 | 10398 | |
a3170dc6 AH |
10399 | case 't': |
10400 | /* Like 'J' but get to the OVERFLOW/UNORDERED bit. */ | |
10401 | if (GET_CODE (x) != REG || GET_MODE (x) != CCmode) | |
10402 | abort (); | |
10403 | ||
10404 | /* Bit 3 is OV bit. */ | |
10405 | i = 4 * (REGNO (x) - CR0_REGNO) + 3; | |
10406 | ||
10407 | /* If we want bit 31, write a shift count of zero, not 32. */ | |
10408 | fprintf (file, "%d", i == 31 ? 0 : i + 1); | |
10409 | return; | |
10410 | ||
cccf3bdc DE |
10411 | case 'T': |
10412 | /* Print the symbolic name of a branch target register. */ | |
10413 | if (GET_CODE (x) != REG || (REGNO (x) != LINK_REGISTER_REGNUM | |
10414 | && REGNO (x) != COUNT_REGISTER_REGNUM)) | |
10415 | output_operand_lossage ("invalid %%T value"); | |
e2c953b6 | 10416 | else if (REGNO (x) == LINK_REGISTER_REGNUM) |
cccf3bdc DE |
10417 | fputs (TARGET_NEW_MNEMONICS ? "lr" : "r", file); |
10418 | else | |
10419 | fputs ("ctr", file); | |
10420 | return; | |
10421 | ||
9854d9ed | 10422 | case 'u': |
802a0058 | 10423 | /* High-order 16 bits of constant for use in unsigned operand. */ |
9854d9ed RK |
10424 | if (! INT_P (x)) |
10425 | output_operand_lossage ("invalid %%u value"); | |
e2c953b6 | 10426 | else |
f676971a | 10427 | fprintf (file, HOST_WIDE_INT_PRINT_HEX, |
e2c953b6 | 10428 | (INT_LOWPART (x) >> 16) & 0xffff); |
9878760c RK |
10429 | return; |
10430 | ||
802a0058 MM |
10431 | case 'v': |
10432 | /* High-order 16 bits of constant for use in signed operand. */ | |
10433 | if (! INT_P (x)) | |
10434 | output_operand_lossage ("invalid %%v value"); | |
e2c953b6 | 10435 | else |
134c32f6 DE |
10436 | fprintf (file, HOST_WIDE_INT_PRINT_HEX, |
10437 | (INT_LOWPART (x) >> 16) & 0xffff); | |
10438 | return; | |
802a0058 | 10439 | |
9854d9ed RK |
10440 | case 'U': |
10441 | /* Print `u' if this has an auto-increment or auto-decrement. */ | |
10442 | if (GET_CODE (x) == MEM | |
10443 | && (GET_CODE (XEXP (x, 0)) == PRE_INC | |
10444 | || GET_CODE (XEXP (x, 0)) == PRE_DEC)) | |
76229ac8 | 10445 | putc ('u', file); |
9854d9ed | 10446 | return; |
9878760c | 10447 | |
e0cd0770 JC |
10448 | case 'V': |
10449 | /* Print the trap code for this operand. */ | |
10450 | switch (GET_CODE (x)) | |
10451 | { | |
10452 | case EQ: | |
10453 | fputs ("eq", file); /* 4 */ | |
10454 | break; | |
10455 | case NE: | |
10456 | fputs ("ne", file); /* 24 */ | |
10457 | break; | |
10458 | case LT: | |
10459 | fputs ("lt", file); /* 16 */ | |
10460 | break; | |
10461 | case LE: | |
10462 | fputs ("le", file); /* 20 */ | |
10463 | break; | |
10464 | case GT: | |
10465 | fputs ("gt", file); /* 8 */ | |
10466 | break; | |
10467 | case GE: | |
10468 | fputs ("ge", file); /* 12 */ | |
10469 | break; | |
10470 | case LTU: | |
10471 | fputs ("llt", file); /* 2 */ | |
10472 | break; | |
10473 | case LEU: | |
10474 | fputs ("lle", file); /* 6 */ | |
10475 | break; | |
10476 | case GTU: | |
10477 | fputs ("lgt", file); /* 1 */ | |
10478 | break; | |
10479 | case GEU: | |
10480 | fputs ("lge", file); /* 5 */ | |
10481 | break; | |
10482 | default: | |
10483 | abort (); | |
10484 | } | |
10485 | break; | |
10486 | ||
9854d9ed RK |
10487 | case 'w': |
10488 | /* If constant, low-order 16 bits of constant, signed. Otherwise, write | |
10489 | normally. */ | |
10490 | if (INT_P (x)) | |
f676971a | 10491 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, |
5f59ecb7 | 10492 | ((INT_LOWPART (x) & 0xffff) ^ 0x8000) - 0x8000); |
9854d9ed RK |
10493 | else |
10494 | print_operand (file, x, 0); | |
9878760c RK |
10495 | return; |
10496 | ||
9854d9ed | 10497 | case 'W': |
e2c953b6 | 10498 | /* MB value for a PowerPC64 rldic operand. */ |
e2c953b6 DE |
10499 | val = (GET_CODE (x) == CONST_INT |
10500 | ? INTVAL (x) : CONST_DOUBLE_HIGH (x)); | |
10501 | ||
10502 | if (val < 0) | |
10503 | i = -1; | |
9854d9ed | 10504 | else |
e2c953b6 DE |
10505 | for (i = 0; i < HOST_BITS_PER_WIDE_INT; i++) |
10506 | if ((val <<= 1) < 0) | |
10507 | break; | |
10508 | ||
10509 | #if HOST_BITS_PER_WIDE_INT == 32 | |
10510 | if (GET_CODE (x) == CONST_INT && i >= 0) | |
10511 | i += 32; /* zero-extend high-part was all 0's */ | |
10512 | else if (GET_CODE (x) == CONST_DOUBLE && i == 32) | |
10513 | { | |
10514 | val = CONST_DOUBLE_LOW (x); | |
10515 | ||
10516 | if (val == 0) | |
a4f6c312 | 10517 | abort (); |
e2c953b6 DE |
10518 | else if (val < 0) |
10519 | --i; | |
10520 | else | |
10521 | for ( ; i < 64; i++) | |
10522 | if ((val <<= 1) < 0) | |
10523 | break; | |
10524 | } | |
10525 | #endif | |
10526 | ||
10527 | fprintf (file, "%d", i + 1); | |
9854d9ed | 10528 | return; |
9878760c | 10529 | |
9854d9ed RK |
10530 | case 'X': |
10531 | if (GET_CODE (x) == MEM | |
4d588c14 | 10532 | && legitimate_indexed_address_p (XEXP (x, 0), 0)) |
76229ac8 | 10533 | putc ('x', file); |
9854d9ed | 10534 | return; |
9878760c | 10535 | |
9854d9ed RK |
10536 | case 'Y': |
10537 | /* Like 'L', for third word of TImode */ | |
10538 | if (GET_CODE (x) == REG) | |
fb5c67a7 | 10539 | fputs (reg_names[REGNO (x) + 2], file); |
9854d9ed | 10540 | else if (GET_CODE (x) == MEM) |
9878760c | 10541 | { |
9854d9ed RK |
10542 | if (GET_CODE (XEXP (x, 0)) == PRE_INC |
10543 | || GET_CODE (XEXP (x, 0)) == PRE_DEC) | |
a54d04b7 | 10544 | output_address (plus_constant (XEXP (XEXP (x, 0), 0), 8)); |
9854d9ed | 10545 | else |
d7624dc0 | 10546 | output_address (XEXP (adjust_address_nv (x, SImode, 8), 0)); |
ba5e43aa | 10547 | if (small_data_operand (x, GET_MODE (x))) |
8fbd2dc7 MM |
10548 | fprintf (file, "@%s(%s)", SMALL_DATA_RELOC, |
10549 | reg_names[SMALL_DATA_REG]); | |
9878760c RK |
10550 | } |
10551 | return; | |
f676971a | 10552 | |
9878760c | 10553 | case 'z': |
b4ac57ab RS |
10554 | /* X is a SYMBOL_REF. Write out the name preceded by a |
10555 | period and without any trailing data in brackets. Used for function | |
4d30c363 MM |
10556 | names. If we are configured for System V (or the embedded ABI) on |
10557 | the PowerPC, do not emit the period, since those systems do not use | |
10558 | TOCs and the like. */ | |
9878760c RK |
10559 | if (GET_CODE (x) != SYMBOL_REF) |
10560 | abort (); | |
10561 | ||
c4ad648e AM |
10562 | /* Mark the decl as referenced so that cgraph will output the |
10563 | function. */ | |
9bf6462a | 10564 | if (SYMBOL_REF_DECL (x)) |
c4ad648e | 10565 | mark_decl_referenced (SYMBOL_REF_DECL (x)); |
9bf6462a | 10566 | |
85b776df | 10567 | /* For macho, check to see if we need a stub. */ |
f9da97f0 AP |
10568 | if (TARGET_MACHO) |
10569 | { | |
10570 | const char *name = XSTR (x, 0); | |
a031e781 | 10571 | #if TARGET_MACHO |
3b48085e | 10572 | if (MACHOPIC_INDIRECT |
11abc112 MM |
10573 | && machopic_classify_symbol (x) == MACHOPIC_UNDEFINED_FUNCTION) |
10574 | name = machopic_indirection_name (x, /*stub_p=*/true); | |
f9da97f0 AP |
10575 | #endif |
10576 | assemble_name (file, name); | |
10577 | } | |
85b776df | 10578 | else if (!DOT_SYMBOLS) |
9739c90c | 10579 | assemble_name (file, XSTR (x, 0)); |
85b776df AM |
10580 | else |
10581 | rs6000_output_function_entry (file, XSTR (x, 0)); | |
9878760c RK |
10582 | return; |
10583 | ||
9854d9ed RK |
10584 | case 'Z': |
10585 | /* Like 'L', for last word of TImode. */ | |
10586 | if (GET_CODE (x) == REG) | |
fb5c67a7 | 10587 | fputs (reg_names[REGNO (x) + 3], file); |
9854d9ed RK |
10588 | else if (GET_CODE (x) == MEM) |
10589 | { | |
10590 | if (GET_CODE (XEXP (x, 0)) == PRE_INC | |
10591 | || GET_CODE (XEXP (x, 0)) == PRE_DEC) | |
a54d04b7 | 10592 | output_address (plus_constant (XEXP (XEXP (x, 0), 0), 12)); |
9854d9ed | 10593 | else |
d7624dc0 | 10594 | output_address (XEXP (adjust_address_nv (x, SImode, 12), 0)); |
ba5e43aa | 10595 | if (small_data_operand (x, GET_MODE (x))) |
8fbd2dc7 MM |
10596 | fprintf (file, "@%s(%s)", SMALL_DATA_RELOC, |
10597 | reg_names[SMALL_DATA_REG]); | |
9854d9ed | 10598 | } |
5c23c401 | 10599 | return; |
0ac081f6 | 10600 | |
a3170dc6 | 10601 | /* Print AltiVec or SPE memory operand. */ |
0ac081f6 AH |
10602 | case 'y': |
10603 | { | |
10604 | rtx tmp; | |
10605 | ||
10606 | if (GET_CODE (x) != MEM) | |
10607 | abort (); | |
10608 | ||
10609 | tmp = XEXP (x, 0); | |
10610 | ||
993f19a8 | 10611 | if (TARGET_E500) |
a3170dc6 AH |
10612 | { |
10613 | /* Handle [reg]. */ | |
10614 | if (GET_CODE (tmp) == REG) | |
10615 | { | |
10616 | fprintf (file, "0(%s)", reg_names[REGNO (tmp)]); | |
10617 | break; | |
10618 | } | |
10619 | /* Handle [reg+UIMM]. */ | |
10620 | else if (GET_CODE (tmp) == PLUS && | |
10621 | GET_CODE (XEXP (tmp, 1)) == CONST_INT) | |
10622 | { | |
10623 | int x; | |
10624 | ||
10625 | if (GET_CODE (XEXP (tmp, 0)) != REG) | |
10626 | abort (); | |
10627 | ||
10628 | x = INTVAL (XEXP (tmp, 1)); | |
10629 | fprintf (file, "%d(%s)", x, reg_names[REGNO (XEXP (tmp, 0))]); | |
10630 | break; | |
10631 | } | |
10632 | ||
10633 | /* Fall through. Must be [reg+reg]. */ | |
10634 | } | |
850e8d3d DN |
10635 | if (TARGET_ALTIVEC |
10636 | && GET_CODE (tmp) == AND | |
10637 | && GET_CODE (XEXP (tmp, 1)) == CONST_INT | |
10638 | && INTVAL (XEXP (tmp, 1)) == -16) | |
10639 | tmp = XEXP (tmp, 0); | |
0ac081f6 | 10640 | if (GET_CODE (tmp) == REG) |
c62f2db5 | 10641 | fprintf (file, "0,%s", reg_names[REGNO (tmp)]); |
0ac081f6 AH |
10642 | else if (GET_CODE (tmp) == PLUS && GET_CODE (XEXP (tmp, 1)) == REG) |
10643 | { | |
10644 | if (REGNO (XEXP (tmp, 0)) == 0) | |
10645 | fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 1)) ], | |
10646 | reg_names[ REGNO (XEXP (tmp, 0)) ]); | |
10647 | else | |
10648 | fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 0)) ], | |
10649 | reg_names[ REGNO (XEXP (tmp, 1)) ]); | |
10650 | } | |
10651 | else | |
10652 | abort (); | |
10653 | break; | |
10654 | } | |
f676971a | 10655 | |
9878760c RK |
10656 | case 0: |
10657 | if (GET_CODE (x) == REG) | |
10658 | fprintf (file, "%s", reg_names[REGNO (x)]); | |
10659 | else if (GET_CODE (x) == MEM) | |
10660 | { | |
10661 | /* We need to handle PRE_INC and PRE_DEC here, since we need to | |
10662 | know the width from the mode. */ | |
10663 | if (GET_CODE (XEXP (x, 0)) == PRE_INC) | |
79ba6d34 MM |
10664 | fprintf (file, "%d(%s)", GET_MODE_SIZE (GET_MODE (x)), |
10665 | reg_names[REGNO (XEXP (XEXP (x, 0), 0))]); | |
9878760c | 10666 | else if (GET_CODE (XEXP (x, 0)) == PRE_DEC) |
79ba6d34 MM |
10667 | fprintf (file, "%d(%s)", - GET_MODE_SIZE (GET_MODE (x)), |
10668 | reg_names[REGNO (XEXP (XEXP (x, 0), 0))]); | |
9878760c | 10669 | else |
a54d04b7 | 10670 | output_address (XEXP (x, 0)); |
9878760c RK |
10671 | } |
10672 | else | |
a54d04b7 | 10673 | output_addr_const (file, x); |
a85d226b | 10674 | return; |
9878760c | 10675 | |
c4501e62 JJ |
10676 | case '&': |
10677 | assemble_name (file, rs6000_get_some_local_dynamic_name ()); | |
10678 | return; | |
10679 | ||
9878760c RK |
10680 | default: |
10681 | output_operand_lossage ("invalid %%xn code"); | |
10682 | } | |
10683 | } | |
10684 | \f | |
10685 | /* Print the address of an operand. */ | |
10686 | ||
10687 | void | |
a2369ed3 | 10688 | print_operand_address (FILE *file, rtx x) |
9878760c RK |
10689 | { |
10690 | if (GET_CODE (x) == REG) | |
4697a36c | 10691 | fprintf (file, "0(%s)", reg_names[ REGNO (x) ]); |
9ebbca7d GK |
10692 | else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST |
10693 | || GET_CODE (x) == LABEL_REF) | |
9878760c RK |
10694 | { |
10695 | output_addr_const (file, x); | |
ba5e43aa | 10696 | if (small_data_operand (x, GET_MODE (x))) |
8fbd2dc7 MM |
10697 | fprintf (file, "@%s(%s)", SMALL_DATA_RELOC, |
10698 | reg_names[SMALL_DATA_REG]); | |
9ebbca7d | 10699 | else if (TARGET_TOC) |
a4f6c312 | 10700 | abort (); |
9878760c RK |
10701 | } |
10702 | else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == REG) | |
10703 | { | |
10704 | if (REGNO (XEXP (x, 0)) == 0) | |
4697a36c MM |
10705 | fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 1)) ], |
10706 | reg_names[ REGNO (XEXP (x, 0)) ]); | |
9878760c | 10707 | else |
4697a36c MM |
10708 | fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 0)) ], |
10709 | reg_names[ REGNO (XEXP (x, 1)) ]); | |
9878760c RK |
10710 | } |
10711 | else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT) | |
4a0a75dd KG |
10712 | fprintf (file, HOST_WIDE_INT_PRINT_DEC "(%s)", |
10713 | INTVAL (XEXP (x, 1)), reg_names[ REGNO (XEXP (x, 0)) ]); | |
3cb999d8 DE |
10714 | #if TARGET_ELF |
10715 | else if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 0)) == REG | |
c4ad648e | 10716 | && CONSTANT_P (XEXP (x, 1))) |
4697a36c MM |
10717 | { |
10718 | output_addr_const (file, XEXP (x, 1)); | |
10719 | fprintf (file, "@l(%s)", reg_names[ REGNO (XEXP (x, 0)) ]); | |
10720 | } | |
c859cda6 DJ |
10721 | #endif |
10722 | #if TARGET_MACHO | |
10723 | else if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 0)) == REG | |
c4ad648e | 10724 | && CONSTANT_P (XEXP (x, 1))) |
c859cda6 DJ |
10725 | { |
10726 | fprintf (file, "lo16("); | |
10727 | output_addr_const (file, XEXP (x, 1)); | |
10728 | fprintf (file, ")(%s)", reg_names[ REGNO (XEXP (x, 0)) ]); | |
10729 | } | |
3cb999d8 | 10730 | #endif |
4d588c14 | 10731 | else if (legitimate_constant_pool_address_p (x)) |
9ebbca7d | 10732 | { |
2bfcf297 | 10733 | if (TARGET_AIX && (!TARGET_ELF || !TARGET_MINIMAL_TOC)) |
9ebbca7d | 10734 | { |
2bfcf297 DB |
10735 | rtx contains_minus = XEXP (x, 1); |
10736 | rtx minus, symref; | |
10737 | const char *name; | |
f676971a | 10738 | |
9ebbca7d | 10739 | /* Find the (minus (sym) (toc)) buried in X, and temporarily |
a4f6c312 | 10740 | turn it into (sym) for output_addr_const. */ |
9ebbca7d GK |
10741 | while (GET_CODE (XEXP (contains_minus, 0)) != MINUS) |
10742 | contains_minus = XEXP (contains_minus, 0); | |
10743 | ||
2bfcf297 DB |
10744 | minus = XEXP (contains_minus, 0); |
10745 | symref = XEXP (minus, 0); | |
10746 | XEXP (contains_minus, 0) = symref; | |
10747 | if (TARGET_ELF) | |
10748 | { | |
10749 | char *newname; | |
10750 | ||
10751 | name = XSTR (symref, 0); | |
10752 | newname = alloca (strlen (name) + sizeof ("@toc")); | |
10753 | strcpy (newname, name); | |
10754 | strcat (newname, "@toc"); | |
10755 | XSTR (symref, 0) = newname; | |
10756 | } | |
10757 | output_addr_const (file, XEXP (x, 1)); | |
10758 | if (TARGET_ELF) | |
10759 | XSTR (symref, 0) = name; | |
9ebbca7d GK |
10760 | XEXP (contains_minus, 0) = minus; |
10761 | } | |
10762 | else | |
10763 | output_addr_const (file, XEXP (x, 1)); | |
10764 | ||
10765 | fprintf (file, "(%s)", reg_names[REGNO (XEXP (x, 0))]); | |
10766 | } | |
9878760c RK |
10767 | else |
10768 | abort (); | |
10769 | } | |
10770 | \f | |
88cad84b | 10771 | /* Target hook for assembling integer objects. The PowerPC version has |
301d03af RS |
10772 | to handle fixup entries for relocatable code if RELOCATABLE_NEEDS_FIXUP |
10773 | is defined. It also needs to handle DI-mode objects on 64-bit | |
10774 | targets. */ | |
10775 | ||
10776 | static bool | |
a2369ed3 | 10777 | rs6000_assemble_integer (rtx x, unsigned int size, int aligned_p) |
301d03af RS |
10778 | { |
10779 | #ifdef RELOCATABLE_NEEDS_FIXUP | |
10780 | /* Special handling for SI values. */ | |
10781 | if (size == 4 && aligned_p) | |
10782 | { | |
a2369ed3 | 10783 | extern int in_toc_section (void); |
301d03af | 10784 | static int recurse = 0; |
f676971a | 10785 | |
301d03af RS |
10786 | /* For -mrelocatable, we mark all addresses that need to be fixed up |
10787 | in the .fixup section. */ | |
10788 | if (TARGET_RELOCATABLE | |
10789 | && !in_toc_section () | |
10790 | && !in_text_section () | |
642af3be | 10791 | && !in_unlikely_text_section () |
301d03af RS |
10792 | && !recurse |
10793 | && GET_CODE (x) != CONST_INT | |
10794 | && GET_CODE (x) != CONST_DOUBLE | |
10795 | && CONSTANT_P (x)) | |
10796 | { | |
10797 | char buf[256]; | |
10798 | ||
10799 | recurse = 1; | |
10800 | ASM_GENERATE_INTERNAL_LABEL (buf, "LCP", fixuplabelno); | |
10801 | fixuplabelno++; | |
10802 | ASM_OUTPUT_LABEL (asm_out_file, buf); | |
10803 | fprintf (asm_out_file, "\t.long\t("); | |
10804 | output_addr_const (asm_out_file, x); | |
10805 | fprintf (asm_out_file, ")@fixup\n"); | |
10806 | fprintf (asm_out_file, "\t.section\t\".fixup\",\"aw\"\n"); | |
10807 | ASM_OUTPUT_ALIGN (asm_out_file, 2); | |
10808 | fprintf (asm_out_file, "\t.long\t"); | |
10809 | assemble_name (asm_out_file, buf); | |
10810 | fprintf (asm_out_file, "\n\t.previous\n"); | |
10811 | recurse = 0; | |
10812 | return true; | |
10813 | } | |
10814 | /* Remove initial .'s to turn a -mcall-aixdesc function | |
10815 | address into the address of the descriptor, not the function | |
10816 | itself. */ | |
10817 | else if (GET_CODE (x) == SYMBOL_REF | |
10818 | && XSTR (x, 0)[0] == '.' | |
10819 | && DEFAULT_ABI == ABI_AIX) | |
10820 | { | |
10821 | const char *name = XSTR (x, 0); | |
10822 | while (*name == '.') | |
10823 | name++; | |
10824 | ||
10825 | fprintf (asm_out_file, "\t.long\t%s\n", name); | |
10826 | return true; | |
10827 | } | |
10828 | } | |
10829 | #endif /* RELOCATABLE_NEEDS_FIXUP */ | |
10830 | return default_assemble_integer (x, size, aligned_p); | |
10831 | } | |
93638d7a AM |
10832 | |
10833 | #ifdef HAVE_GAS_HIDDEN | |
10834 | /* Emit an assembler directive to set symbol visibility for DECL to | |
10835 | VISIBILITY_TYPE. */ | |
10836 | ||
5add3202 | 10837 | static void |
a2369ed3 | 10838 | rs6000_assemble_visibility (tree decl, int vis) |
93638d7a | 10839 | { |
93638d7a AM |
10840 | /* Functions need to have their entry point symbol visibility set as |
10841 | well as their descriptor symbol visibility. */ | |
85b776df AM |
10842 | if (DEFAULT_ABI == ABI_AIX |
10843 | && DOT_SYMBOLS | |
10844 | && TREE_CODE (decl) == FUNCTION_DECL) | |
93638d7a | 10845 | { |
25fdb4dc | 10846 | static const char * const visibility_types[] = { |
c4ad648e | 10847 | NULL, "internal", "hidden", "protected" |
25fdb4dc RH |
10848 | }; |
10849 | ||
10850 | const char *name, *type; | |
93638d7a AM |
10851 | |
10852 | name = ((* targetm.strip_name_encoding) | |
10853 | (IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl)))); | |
25fdb4dc | 10854 | type = visibility_types[vis]; |
93638d7a | 10855 | |
25fdb4dc RH |
10856 | fprintf (asm_out_file, "\t.%s\t%s\n", type, name); |
10857 | fprintf (asm_out_file, "\t.%s\t.%s\n", type, name); | |
93638d7a | 10858 | } |
25fdb4dc RH |
10859 | else |
10860 | default_assemble_visibility (decl, vis); | |
93638d7a AM |
10861 | } |
10862 | #endif | |
301d03af | 10863 | \f |
39a10a29 | 10864 | enum rtx_code |
a2369ed3 | 10865 | rs6000_reverse_condition (enum machine_mode mode, enum rtx_code code) |
39a10a29 GK |
10866 | { |
10867 | /* Reversal of FP compares takes care -- an ordered compare | |
10868 | becomes an unordered compare and vice versa. */ | |
f676971a | 10869 | if (mode == CCFPmode |
bc9ec0e0 GK |
10870 | && (!flag_finite_math_only |
10871 | || code == UNLT || code == UNLE || code == UNGT || code == UNGE | |
10872 | || code == UNEQ || code == LTGT)) | |
bab6226b | 10873 | return reverse_condition_maybe_unordered (code); |
39a10a29 | 10874 | else |
bab6226b | 10875 | return reverse_condition (code); |
39a10a29 GK |
10876 | } |
10877 | ||
39a10a29 GK |
10878 | /* Generate a compare for CODE. Return a brand-new rtx that |
10879 | represents the result of the compare. */ | |
a4f6c312 | 10880 | |
39a10a29 | 10881 | static rtx |
a2369ed3 | 10882 | rs6000_generate_compare (enum rtx_code code) |
39a10a29 GK |
10883 | { |
10884 | enum machine_mode comp_mode; | |
10885 | rtx compare_result; | |
10886 | ||
10887 | if (rs6000_compare_fp_p) | |
10888 | comp_mode = CCFPmode; | |
10889 | else if (code == GTU || code == LTU | |
c4ad648e | 10890 | || code == GEU || code == LEU) |
39a10a29 GK |
10891 | comp_mode = CCUNSmode; |
10892 | else | |
10893 | comp_mode = CCmode; | |
10894 | ||
10895 | /* First, the compare. */ | |
10896 | compare_result = gen_reg_rtx (comp_mode); | |
a3170dc6 AH |
10897 | |
10898 | /* SPE FP compare instructions on the GPRs. Yuck! */ | |
993f19a8 AH |
10899 | if ((TARGET_E500 && !TARGET_FPRS && TARGET_HARD_FLOAT) |
10900 | && rs6000_compare_fp_p) | |
a3170dc6 AH |
10901 | { |
10902 | rtx cmp, or1, or2, or_result, compare_result2; | |
4d4cbc0e AH |
10903 | enum machine_mode op_mode = GET_MODE (rs6000_compare_op0); |
10904 | ||
10905 | if (op_mode == VOIDmode) | |
10906 | op_mode = GET_MODE (rs6000_compare_op1); | |
a3170dc6 | 10907 | |
423c1189 AH |
10908 | /* Note: The E500 comparison instructions set the GT bit (x + |
10909 | 1), on success. This explains the mess. */ | |
10910 | ||
a3170dc6 AH |
10911 | switch (code) |
10912 | { | |
423c1189 | 10913 | case EQ: case UNEQ: case NE: case LTGT: |
4d4cbc0e AH |
10914 | if (op_mode == SFmode) |
10915 | cmp = flag_finite_math_only | |
10916 | ? gen_tstsfeq_gpr (compare_result, rs6000_compare_op0, | |
10917 | rs6000_compare_op1) | |
10918 | : gen_cmpsfeq_gpr (compare_result, rs6000_compare_op0, | |
10919 | rs6000_compare_op1); | |
10920 | else if (op_mode == DFmode) | |
10921 | cmp = flag_finite_math_only | |
10922 | ? gen_tstdfeq_gpr (compare_result, rs6000_compare_op0, | |
10923 | rs6000_compare_op1) | |
10924 | : gen_cmpdfeq_gpr (compare_result, rs6000_compare_op0, | |
10925 | rs6000_compare_op1); | |
10926 | else abort (); | |
a3170dc6 | 10927 | break; |
423c1189 | 10928 | case GT: case GTU: case UNGT: case UNGE: case GE: case GEU: |
4d4cbc0e AH |
10929 | if (op_mode == SFmode) |
10930 | cmp = flag_finite_math_only | |
10931 | ? gen_tstsfgt_gpr (compare_result, rs6000_compare_op0, | |
10932 | rs6000_compare_op1) | |
10933 | : gen_cmpsfgt_gpr (compare_result, rs6000_compare_op0, | |
10934 | rs6000_compare_op1); | |
10935 | else if (op_mode == DFmode) | |
10936 | cmp = flag_finite_math_only | |
10937 | ? gen_tstdfgt_gpr (compare_result, rs6000_compare_op0, | |
10938 | rs6000_compare_op1) | |
10939 | : gen_cmpdfgt_gpr (compare_result, rs6000_compare_op0, | |
10940 | rs6000_compare_op1); | |
10941 | else abort (); | |
a3170dc6 | 10942 | break; |
423c1189 | 10943 | case LT: case LTU: case UNLT: case UNLE: case LE: case LEU: |
4d4cbc0e AH |
10944 | if (op_mode == SFmode) |
10945 | cmp = flag_finite_math_only | |
10946 | ? gen_tstsflt_gpr (compare_result, rs6000_compare_op0, | |
10947 | rs6000_compare_op1) | |
10948 | : gen_cmpsflt_gpr (compare_result, rs6000_compare_op0, | |
10949 | rs6000_compare_op1); | |
10950 | else if (op_mode == DFmode) | |
10951 | cmp = flag_finite_math_only | |
10952 | ? gen_tstdflt_gpr (compare_result, rs6000_compare_op0, | |
10953 | rs6000_compare_op1) | |
10954 | : gen_cmpdflt_gpr (compare_result, rs6000_compare_op0, | |
10955 | rs6000_compare_op1); | |
10956 | else abort (); | |
a3170dc6 | 10957 | break; |
4d4cbc0e AH |
10958 | default: |
10959 | abort (); | |
a3170dc6 AH |
10960 | } |
10961 | ||
10962 | /* Synthesize LE and GE from LT/GT || EQ. */ | |
10963 | if (code == LE || code == GE || code == LEU || code == GEU) | |
10964 | { | |
a3170dc6 AH |
10965 | emit_insn (cmp); |
10966 | ||
10967 | switch (code) | |
10968 | { | |
10969 | case LE: code = LT; break; | |
10970 | case GE: code = GT; break; | |
10971 | case LEU: code = LT; break; | |
10972 | case GEU: code = GT; break; | |
10973 | default: abort (); | |
10974 | } | |
10975 | ||
10976 | or1 = gen_reg_rtx (SImode); | |
10977 | or2 = gen_reg_rtx (SImode); | |
10978 | or_result = gen_reg_rtx (CCEQmode); | |
10979 | compare_result2 = gen_reg_rtx (CCFPmode); | |
10980 | ||
10981 | /* Do the EQ. */ | |
4d4cbc0e AH |
10982 | if (op_mode == SFmode) |
10983 | cmp = flag_finite_math_only | |
10984 | ? gen_tstsfeq_gpr (compare_result2, rs6000_compare_op0, | |
10985 | rs6000_compare_op1) | |
10986 | : gen_cmpsfeq_gpr (compare_result2, rs6000_compare_op0, | |
10987 | rs6000_compare_op1); | |
10988 | else if (op_mode == DFmode) | |
10989 | cmp = flag_finite_math_only | |
10990 | ? gen_tstdfeq_gpr (compare_result2, rs6000_compare_op0, | |
10991 | rs6000_compare_op1) | |
10992 | : gen_cmpdfeq_gpr (compare_result2, rs6000_compare_op0, | |
10993 | rs6000_compare_op1); | |
10994 | else abort (); | |
a3170dc6 AH |
10995 | emit_insn (cmp); |
10996 | ||
423c1189 AH |
10997 | or1 = gen_rtx_GT (SImode, compare_result, const0_rtx); |
10998 | or2 = gen_rtx_GT (SImode, compare_result2, const0_rtx); | |
a3170dc6 AH |
10999 | |
11000 | /* OR them together. */ | |
11001 | cmp = gen_rtx_SET (VOIDmode, or_result, | |
11002 | gen_rtx_COMPARE (CCEQmode, | |
11003 | gen_rtx_IOR (SImode, or1, or2), | |
11004 | const_true_rtx)); | |
11005 | compare_result = or_result; | |
11006 | code = EQ; | |
11007 | } | |
11008 | else | |
11009 | { | |
a3170dc6 | 11010 | if (code == NE || code == LTGT) |
a3170dc6 | 11011 | code = NE; |
423c1189 AH |
11012 | else |
11013 | code = EQ; | |
a3170dc6 AH |
11014 | } |
11015 | ||
11016 | emit_insn (cmp); | |
11017 | } | |
11018 | else | |
11019 | emit_insn (gen_rtx_SET (VOIDmode, compare_result, | |
11020 | gen_rtx_COMPARE (comp_mode, | |
f676971a | 11021 | rs6000_compare_op0, |
a3170dc6 | 11022 | rs6000_compare_op1))); |
f676971a | 11023 | |
ca5adc63 | 11024 | /* Some kinds of FP comparisons need an OR operation; |
bc9ec0e0 | 11025 | under flag_finite_math_only we don't bother. */ |
39a10a29 | 11026 | if (rs6000_compare_fp_p |
bc9ec0e0 | 11027 | && ! flag_finite_math_only |
993f19a8 | 11028 | && ! (TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS) |
39a10a29 GK |
11029 | && (code == LE || code == GE |
11030 | || code == UNEQ || code == LTGT | |
11031 | || code == UNGT || code == UNLT)) | |
11032 | { | |
11033 | enum rtx_code or1, or2; | |
11034 | rtx or1_rtx, or2_rtx, compare2_rtx; | |
11035 | rtx or_result = gen_reg_rtx (CCEQmode); | |
f676971a | 11036 | |
39a10a29 GK |
11037 | switch (code) |
11038 | { | |
11039 | case LE: or1 = LT; or2 = EQ; break; | |
11040 | case GE: or1 = GT; or2 = EQ; break; | |
11041 | case UNEQ: or1 = UNORDERED; or2 = EQ; break; | |
11042 | case LTGT: or1 = LT; or2 = GT; break; | |
11043 | case UNGT: or1 = UNORDERED; or2 = GT; break; | |
11044 | case UNLT: or1 = UNORDERED; or2 = LT; break; | |
11045 | default: abort (); | |
11046 | } | |
11047 | validate_condition_mode (or1, comp_mode); | |
11048 | validate_condition_mode (or2, comp_mode); | |
1c563bed KH |
11049 | or1_rtx = gen_rtx_fmt_ee (or1, SImode, compare_result, const0_rtx); |
11050 | or2_rtx = gen_rtx_fmt_ee (or2, SImode, compare_result, const0_rtx); | |
39a10a29 GK |
11051 | compare2_rtx = gen_rtx_COMPARE (CCEQmode, |
11052 | gen_rtx_IOR (SImode, or1_rtx, or2_rtx), | |
11053 | const_true_rtx); | |
11054 | emit_insn (gen_rtx_SET (VOIDmode, or_result, compare2_rtx)); | |
11055 | ||
11056 | compare_result = or_result; | |
11057 | code = EQ; | |
11058 | } | |
11059 | ||
11060 | validate_condition_mode (code, GET_MODE (compare_result)); | |
f676971a | 11061 | |
1c563bed | 11062 | return gen_rtx_fmt_ee (code, VOIDmode, compare_result, const0_rtx); |
39a10a29 GK |
11063 | } |
11064 | ||
11065 | ||
11066 | /* Emit the RTL for an sCOND pattern. */ | |
11067 | ||
11068 | void | |
a2369ed3 | 11069 | rs6000_emit_sCOND (enum rtx_code code, rtx result) |
39a10a29 GK |
11070 | { |
11071 | rtx condition_rtx; | |
11072 | enum machine_mode op_mode; | |
b7053a3f | 11073 | enum rtx_code cond_code; |
39a10a29 GK |
11074 | |
11075 | condition_rtx = rs6000_generate_compare (code); | |
b7053a3f GK |
11076 | cond_code = GET_CODE (condition_rtx); |
11077 | ||
423c1189 AH |
11078 | if (TARGET_E500 && rs6000_compare_fp_p |
11079 | && !TARGET_FPRS && TARGET_HARD_FLOAT) | |
11080 | { | |
11081 | rtx t; | |
11082 | ||
11083 | PUT_MODE (condition_rtx, SImode); | |
11084 | t = XEXP (condition_rtx, 0); | |
11085 | ||
11086 | if (cond_code != NE && cond_code != EQ) | |
11087 | abort (); | |
11088 | ||
11089 | if (cond_code == NE) | |
6b1fedc3 | 11090 | emit_insn (gen_e500_flip_eq_bit (t, t)); |
423c1189 | 11091 | |
6b1fedc3 | 11092 | emit_insn (gen_move_from_CR_eq_bit (result, t)); |
423c1189 AH |
11093 | return; |
11094 | } | |
11095 | ||
b7053a3f GK |
11096 | if (cond_code == NE |
11097 | || cond_code == GE || cond_code == LE | |
11098 | || cond_code == GEU || cond_code == LEU | |
11099 | || cond_code == ORDERED || cond_code == UNGE || cond_code == UNLE) | |
11100 | { | |
11101 | rtx not_result = gen_reg_rtx (CCEQmode); | |
11102 | rtx not_op, rev_cond_rtx; | |
11103 | enum machine_mode cc_mode; | |
f676971a | 11104 | |
b7053a3f GK |
11105 | cc_mode = GET_MODE (XEXP (condition_rtx, 0)); |
11106 | ||
1c563bed | 11107 | rev_cond_rtx = gen_rtx_fmt_ee (rs6000_reverse_condition (cc_mode, cond_code), |
0f4c242b | 11108 | SImode, XEXP (condition_rtx, 0), const0_rtx); |
b7053a3f GK |
11109 | not_op = gen_rtx_COMPARE (CCEQmode, rev_cond_rtx, const0_rtx); |
11110 | emit_insn (gen_rtx_SET (VOIDmode, not_result, not_op)); | |
11111 | condition_rtx = gen_rtx_EQ (VOIDmode, not_result, const0_rtx); | |
11112 | } | |
39a10a29 GK |
11113 | |
11114 | op_mode = GET_MODE (rs6000_compare_op0); | |
11115 | if (op_mode == VOIDmode) | |
11116 | op_mode = GET_MODE (rs6000_compare_op1); | |
11117 | ||
11118 | if (TARGET_POWERPC64 && (op_mode == DImode || rs6000_compare_fp_p)) | |
11119 | { | |
11120 | PUT_MODE (condition_rtx, DImode); | |
11121 | convert_move (result, condition_rtx, 0); | |
11122 | } | |
11123 | else | |
11124 | { | |
11125 | PUT_MODE (condition_rtx, SImode); | |
11126 | emit_insn (gen_rtx_SET (VOIDmode, result, condition_rtx)); | |
11127 | } | |
11128 | } | |
11129 | ||
39a10a29 GK |
11130 | /* Emit a branch of kind CODE to location LOC. */ |
11131 | ||
11132 | void | |
a2369ed3 | 11133 | rs6000_emit_cbranch (enum rtx_code code, rtx loc) |
39a10a29 GK |
11134 | { |
11135 | rtx condition_rtx, loc_ref; | |
11136 | ||
11137 | condition_rtx = rs6000_generate_compare (code); | |
11138 | loc_ref = gen_rtx_LABEL_REF (VOIDmode, loc); | |
11139 | emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, | |
11140 | gen_rtx_IF_THEN_ELSE (VOIDmode, condition_rtx, | |
11141 | loc_ref, pc_rtx))); | |
11142 | } | |
11143 | ||
12a4e8c5 GK |
11144 | /* Return the string to output a conditional branch to LABEL, which is |
11145 | the operand number of the label, or -1 if the branch is really a | |
f676971a | 11146 | conditional return. |
12a4e8c5 GK |
11147 | |
11148 | OP is the conditional expression. XEXP (OP, 0) is assumed to be a | |
11149 | condition code register and its mode specifies what kind of | |
11150 | comparison we made. | |
11151 | ||
a0ab749a | 11152 | REVERSED is nonzero if we should reverse the sense of the comparison. |
12a4e8c5 GK |
11153 | |
11154 | INSN is the insn. */ | |
11155 | ||
11156 | char * | |
a2369ed3 | 11157 | output_cbranch (rtx op, const char *label, int reversed, rtx insn) |
12a4e8c5 GK |
11158 | { |
11159 | static char string[64]; | |
11160 | enum rtx_code code = GET_CODE (op); | |
11161 | rtx cc_reg = XEXP (op, 0); | |
11162 | enum machine_mode mode = GET_MODE (cc_reg); | |
11163 | int cc_regno = REGNO (cc_reg) - CR0_REGNO; | |
39a10a29 | 11164 | int need_longbranch = label != NULL && get_attr_length (insn) == 8; |
12a4e8c5 GK |
11165 | int really_reversed = reversed ^ need_longbranch; |
11166 | char *s = string; | |
11167 | const char *ccode; | |
11168 | const char *pred; | |
11169 | rtx note; | |
11170 | ||
39a10a29 GK |
11171 | validate_condition_mode (code, mode); |
11172 | ||
11173 | /* Work out which way this really branches. We could use | |
11174 | reverse_condition_maybe_unordered here always but this | |
11175 | makes the resulting assembler clearer. */ | |
12a4e8c5 | 11176 | if (really_reversed) |
de40e1df DJ |
11177 | { |
11178 | /* Reversal of FP compares takes care -- an ordered compare | |
11179 | becomes an unordered compare and vice versa. */ | |
11180 | if (mode == CCFPmode) | |
11181 | code = reverse_condition_maybe_unordered (code); | |
11182 | else | |
11183 | code = reverse_condition (code); | |
11184 | } | |
12a4e8c5 | 11185 | |
993f19a8 | 11186 | if ((TARGET_E500 && !TARGET_FPRS && TARGET_HARD_FLOAT) && mode == CCFPmode) |
a3170dc6 AH |
11187 | { |
11188 | /* The efscmp/tst* instructions twiddle bit 2, which maps nicely | |
11189 | to the GT bit. */ | |
11190 | if (code == EQ) | |
11191 | /* Opposite of GT. */ | |
a3170dc6 | 11192 | code = GT; |
423c1189 AH |
11193 | else if (code == NE) |
11194 | code = UNLE; | |
a3170dc6 AH |
11195 | else |
11196 | abort (); | |
11197 | } | |
11198 | ||
39a10a29 | 11199 | switch (code) |
12a4e8c5 GK |
11200 | { |
11201 | /* Not all of these are actually distinct opcodes, but | |
11202 | we distinguish them for clarity of the resulting assembler. */ | |
50a0b056 GK |
11203 | case NE: case LTGT: |
11204 | ccode = "ne"; break; | |
11205 | case EQ: case UNEQ: | |
11206 | ccode = "eq"; break; | |
f676971a | 11207 | case GE: case GEU: |
50a0b056 | 11208 | ccode = "ge"; break; |
f676971a | 11209 | case GT: case GTU: case UNGT: |
50a0b056 | 11210 | ccode = "gt"; break; |
f676971a | 11211 | case LE: case LEU: |
50a0b056 | 11212 | ccode = "le"; break; |
f676971a | 11213 | case LT: case LTU: case UNLT: |
50a0b056 | 11214 | ccode = "lt"; break; |
12a4e8c5 GK |
11215 | case UNORDERED: ccode = "un"; break; |
11216 | case ORDERED: ccode = "nu"; break; | |
11217 | case UNGE: ccode = "nl"; break; | |
11218 | case UNLE: ccode = "ng"; break; | |
11219 | default: | |
a4f6c312 | 11220 | abort (); |
12a4e8c5 | 11221 | } |
f676971a EC |
11222 | |
11223 | /* Maybe we have a guess as to how likely the branch is. | |
94a54f47 | 11224 | The old mnemonics don't have a way to specify this information. */ |
f4857b9b | 11225 | pred = ""; |
12a4e8c5 GK |
11226 | note = find_reg_note (insn, REG_BR_PROB, NULL_RTX); |
11227 | if (note != NULL_RTX) | |
11228 | { | |
11229 | /* PROB is the difference from 50%. */ | |
11230 | int prob = INTVAL (XEXP (note, 0)) - REG_BR_PROB_BASE / 2; | |
f4857b9b AM |
11231 | |
11232 | /* Only hint for highly probable/improbable branches on newer | |
11233 | cpus as static prediction overrides processor dynamic | |
11234 | prediction. For older cpus we may as well always hint, but | |
11235 | assume not taken for branches that are very close to 50% as a | |
11236 | mispredicted taken branch is more expensive than a | |
f676971a | 11237 | mispredicted not-taken branch. */ |
ec507f2d | 11238 | if (rs6000_always_hint |
f4857b9b AM |
11239 | || abs (prob) > REG_BR_PROB_BASE / 100 * 48) |
11240 | { | |
11241 | if (abs (prob) > REG_BR_PROB_BASE / 20 | |
11242 | && ((prob > 0) ^ need_longbranch)) | |
c4ad648e | 11243 | pred = "+"; |
f4857b9b AM |
11244 | else |
11245 | pred = "-"; | |
11246 | } | |
12a4e8c5 | 11247 | } |
12a4e8c5 GK |
11248 | |
11249 | if (label == NULL) | |
94a54f47 | 11250 | s += sprintf (s, "{b%sr|b%slr%s} ", ccode, ccode, pred); |
12a4e8c5 | 11251 | else |
94a54f47 | 11252 | s += sprintf (s, "{b%s|b%s%s} ", ccode, ccode, pred); |
12a4e8c5 | 11253 | |
37c67319 | 11254 | /* We need to escape any '%' characters in the reg_names string. |
a3c9585f | 11255 | Assume they'd only be the first character.... */ |
37c67319 GK |
11256 | if (reg_names[cc_regno + CR0_REGNO][0] == '%') |
11257 | *s++ = '%'; | |
94a54f47 | 11258 | s += sprintf (s, "%s", reg_names[cc_regno + CR0_REGNO]); |
12a4e8c5 GK |
11259 | |
11260 | if (label != NULL) | |
11261 | { | |
11262 | /* If the branch distance was too far, we may have to use an | |
11263 | unconditional branch to go the distance. */ | |
11264 | if (need_longbranch) | |
44518ddd | 11265 | s += sprintf (s, ",$+8\n\tb %s", label); |
12a4e8c5 GK |
11266 | else |
11267 | s += sprintf (s, ",%s", label); | |
11268 | } | |
11269 | ||
11270 | return string; | |
11271 | } | |
50a0b056 | 11272 | |
6b1fedc3 | 11273 | /* Return the string to flip the EQ bit on a CR. */ |
423c1189 | 11274 | char * |
6b1fedc3 | 11275 | output_e500_flip_eq_bit (rtx dst, rtx src) |
423c1189 AH |
11276 | { |
11277 | static char string[64]; | |
11278 | int a, b; | |
11279 | ||
11280 | if (GET_CODE (dst) != REG || ! CR_REGNO_P (REGNO (dst)) | |
11281 | || GET_CODE (src) != REG || ! CR_REGNO_P (REGNO (src))) | |
11282 | abort (); | |
11283 | ||
6b1fedc3 AH |
11284 | /* EQ bit. */ |
11285 | a = 4 * (REGNO (dst) - CR0_REGNO) + 2; | |
11286 | b = 4 * (REGNO (src) - CR0_REGNO) + 2; | |
423c1189 AH |
11287 | |
11288 | sprintf (string, "crnot %d,%d", a, b); | |
11289 | return string; | |
11290 | } | |
11291 | ||
21213b4c DP |
11292 | /* Return insn index for the vector compare instruction for given CODE, |
11293 | and DEST_MODE, OP_MODE. Return INSN_NOT_AVAILABLE if valid insn is | |
11294 | not available. */ | |
11295 | ||
11296 | static int | |
11297 | get_vec_cmp_insn (enum rtx_code code, | |
11298 | enum machine_mode dest_mode, | |
11299 | enum machine_mode op_mode) | |
11300 | { | |
11301 | if (!TARGET_ALTIVEC) | |
11302 | return INSN_NOT_AVAILABLE; | |
11303 | ||
11304 | switch (code) | |
11305 | { | |
11306 | case EQ: | |
11307 | if (dest_mode == V16QImode && op_mode == V16QImode) | |
11308 | return UNSPEC_VCMPEQUB; | |
11309 | if (dest_mode == V8HImode && op_mode == V8HImode) | |
11310 | return UNSPEC_VCMPEQUH; | |
11311 | if (dest_mode == V4SImode && op_mode == V4SImode) | |
11312 | return UNSPEC_VCMPEQUW; | |
11313 | if (dest_mode == V4SImode && op_mode == V4SFmode) | |
11314 | return UNSPEC_VCMPEQFP; | |
11315 | break; | |
11316 | case GE: | |
11317 | if (dest_mode == V4SImode && op_mode == V4SFmode) | |
11318 | return UNSPEC_VCMPGEFP; | |
11319 | case GT: | |
11320 | if (dest_mode == V16QImode && op_mode == V16QImode) | |
11321 | return UNSPEC_VCMPGTSB; | |
11322 | if (dest_mode == V8HImode && op_mode == V8HImode) | |
11323 | return UNSPEC_VCMPGTSH; | |
11324 | if (dest_mode == V4SImode && op_mode == V4SImode) | |
11325 | return UNSPEC_VCMPGTSW; | |
11326 | if (dest_mode == V4SImode && op_mode == V4SFmode) | |
11327 | return UNSPEC_VCMPGTFP; | |
11328 | break; | |
11329 | case GTU: | |
11330 | if (dest_mode == V16QImode && op_mode == V16QImode) | |
11331 | return UNSPEC_VCMPGTUB; | |
11332 | if (dest_mode == V8HImode && op_mode == V8HImode) | |
11333 | return UNSPEC_VCMPGTUH; | |
11334 | if (dest_mode == V4SImode && op_mode == V4SImode) | |
11335 | return UNSPEC_VCMPGTUW; | |
11336 | break; | |
11337 | default: | |
11338 | break; | |
11339 | } | |
11340 | return INSN_NOT_AVAILABLE; | |
11341 | } | |
11342 | ||
11343 | /* Emit vector compare for operands OP0 and OP1 using code RCODE. | |
11344 | DMODE is expected destination mode. This is a recursive function. */ | |
11345 | ||
11346 | static rtx | |
11347 | rs6000_emit_vector_compare (enum rtx_code rcode, | |
11348 | rtx op0, rtx op1, | |
11349 | enum machine_mode dmode) | |
11350 | { | |
11351 | int vec_cmp_insn; | |
11352 | rtx mask; | |
11353 | enum machine_mode dest_mode; | |
11354 | enum machine_mode op_mode = GET_MODE (op1); | |
11355 | ||
11356 | #ifdef ENABLE_CHECKING | |
11357 | if (!TARGET_ALTIVEC) | |
11358 | abort (); | |
11359 | ||
11360 | if (GET_MODE (op0) != GET_MODE (op1)) | |
11361 | abort (); | |
11362 | #endif | |
11363 | ||
11364 | /* Floating point vector compare instructions uses destination V4SImode. | |
11365 | Move destination to appropriate mode later. */ | |
11366 | if (dmode == V4SFmode) | |
11367 | dest_mode = V4SImode; | |
11368 | else | |
11369 | dest_mode = dmode; | |
11370 | ||
11371 | mask = gen_reg_rtx (dest_mode); | |
11372 | vec_cmp_insn = get_vec_cmp_insn (rcode, dest_mode, op_mode); | |
11373 | ||
11374 | if (vec_cmp_insn == INSN_NOT_AVAILABLE) | |
11375 | { | |
11376 | bool swap_operands = false; | |
11377 | bool try_again = false; | |
11378 | switch (rcode) | |
11379 | { | |
11380 | case LT: | |
11381 | rcode = GT; | |
11382 | swap_operands = true; | |
11383 | try_again = true; | |
11384 | break; | |
11385 | case LTU: | |
11386 | rcode = GTU; | |
11387 | swap_operands = true; | |
11388 | try_again = true; | |
11389 | break; | |
11390 | case NE: | |
11391 | /* Treat A != B as ~(A==B). */ | |
11392 | { | |
11393 | enum insn_code nor_code; | |
11394 | rtx eq_rtx = rs6000_emit_vector_compare (EQ, op0, op1, | |
11395 | dest_mode); | |
11396 | ||
11397 | nor_code = one_cmpl_optab->handlers[(int)dest_mode].insn_code; | |
11398 | if (nor_code == CODE_FOR_nothing) | |
11399 | abort (); | |
11400 | emit_insn (GEN_FCN (nor_code) (mask, eq_rtx)); | |
11401 | ||
11402 | if (dmode != dest_mode) | |
11403 | { | |
11404 | rtx temp = gen_reg_rtx (dest_mode); | |
11405 | convert_move (temp, mask, 0); | |
11406 | return temp; | |
11407 | } | |
11408 | return mask; | |
11409 | } | |
11410 | break; | |
11411 | case GE: | |
11412 | case GEU: | |
11413 | case LE: | |
11414 | case LEU: | |
11415 | /* Try GT/GTU/LT/LTU OR EQ */ | |
11416 | { | |
11417 | rtx c_rtx, eq_rtx; | |
11418 | enum insn_code ior_code; | |
11419 | enum rtx_code new_code; | |
11420 | ||
11421 | if (rcode == GE) | |
11422 | new_code = GT; | |
11423 | else if (rcode == GEU) | |
11424 | new_code = GTU; | |
11425 | else if (rcode == LE) | |
11426 | new_code = LT; | |
11427 | else if (rcode == LEU) | |
11428 | new_code = LTU; | |
11429 | else | |
11430 | abort (); | |
11431 | ||
11432 | c_rtx = rs6000_emit_vector_compare (new_code, | |
11433 | op0, op1, dest_mode); | |
11434 | eq_rtx = rs6000_emit_vector_compare (EQ, op0, op1, | |
11435 | dest_mode); | |
11436 | ||
11437 | ior_code = ior_optab->handlers[(int)dest_mode].insn_code; | |
11438 | if (ior_code == CODE_FOR_nothing) | |
11439 | abort (); | |
11440 | emit_insn (GEN_FCN (ior_code) (mask, c_rtx, eq_rtx)); | |
11441 | if (dmode != dest_mode) | |
11442 | { | |
11443 | rtx temp = gen_reg_rtx (dest_mode); | |
11444 | convert_move (temp, mask, 0); | |
11445 | return temp; | |
11446 | } | |
11447 | return mask; | |
11448 | } | |
11449 | break; | |
11450 | default: | |
11451 | abort (); | |
11452 | } | |
11453 | ||
11454 | if (try_again) | |
11455 | { | |
11456 | vec_cmp_insn = get_vec_cmp_insn (rcode, dest_mode, op_mode); | |
11457 | if (vec_cmp_insn == INSN_NOT_AVAILABLE) | |
11458 | /* You only get two chances. */ | |
11459 | abort (); | |
11460 | } | |
11461 | ||
11462 | if (swap_operands) | |
11463 | { | |
11464 | rtx tmp; | |
11465 | tmp = op0; | |
11466 | op0 = op1; | |
11467 | op1 = tmp; | |
11468 | } | |
11469 | } | |
11470 | ||
11471 | emit_insn (gen_rtx_fmt_ee (SET, | |
11472 | VOIDmode, | |
11473 | mask, | |
11474 | gen_rtx_fmt_Ei (UNSPEC, dest_mode, | |
11475 | gen_rtvec (2, op0, op1), | |
11476 | vec_cmp_insn))); | |
11477 | if (dmode != dest_mode) | |
11478 | { | |
11479 | rtx temp = gen_reg_rtx (dest_mode); | |
11480 | convert_move (temp, mask, 0); | |
11481 | return temp; | |
11482 | } | |
11483 | return mask; | |
11484 | } | |
11485 | ||
11486 | /* Return vector select instruction for MODE. Return INSN_NOT_AVAILABLE, if | |
11487 | valid insn doesn exist for given mode. */ | |
11488 | ||
11489 | static int | |
11490 | get_vsel_insn (enum machine_mode mode) | |
11491 | { | |
11492 | switch (mode) | |
11493 | { | |
11494 | case V4SImode: | |
11495 | return UNSPEC_VSEL4SI; | |
11496 | break; | |
11497 | case V4SFmode: | |
11498 | return UNSPEC_VSEL4SF; | |
11499 | break; | |
11500 | case V8HImode: | |
11501 | return UNSPEC_VSEL8HI; | |
11502 | break; | |
11503 | case V16QImode: | |
11504 | return UNSPEC_VSEL16QI; | |
11505 | break; | |
11506 | default: | |
11507 | return INSN_NOT_AVAILABLE; | |
11508 | break; | |
11509 | } | |
11510 | return INSN_NOT_AVAILABLE; | |
11511 | } | |
11512 | ||
11513 | /* Emit vector select insn where DEST is destination using | |
11514 | operands OP1, OP2 and MASK. */ | |
11515 | ||
11516 | static void | |
11517 | rs6000_emit_vector_select (rtx dest, rtx op1, rtx op2, rtx mask) | |
11518 | { | |
11519 | rtx t, temp; | |
11520 | enum machine_mode dest_mode = GET_MODE (dest); | |
11521 | int vsel_insn_index = get_vsel_insn (GET_MODE (dest)); | |
11522 | ||
11523 | temp = gen_reg_rtx (dest_mode); | |
11524 | ||
11525 | t = gen_rtx_fmt_ee (SET, VOIDmode, temp, | |
11526 | gen_rtx_fmt_Ei (UNSPEC, dest_mode, | |
11527 | gen_rtvec (3, op1, op2, mask), | |
11528 | vsel_insn_index)); | |
11529 | emit_insn (t); | |
11530 | emit_move_insn (dest, temp); | |
11531 | return; | |
11532 | } | |
11533 | ||
11534 | /* Emit vector conditional expression. | |
11535 | DEST is destination. OP1 and OP2 are two VEC_COND_EXPR operands. | |
11536 | CC_OP0 and CC_OP1 are the two operands for the relation operation COND. */ | |
11537 | ||
11538 | int | |
11539 | rs6000_emit_vector_cond_expr (rtx dest, rtx op1, rtx op2, | |
11540 | rtx cond, rtx cc_op0, rtx cc_op1) | |
11541 | { | |
11542 | enum machine_mode dest_mode = GET_MODE (dest); | |
11543 | enum rtx_code rcode = GET_CODE (cond); | |
11544 | rtx mask; | |
11545 | ||
11546 | if (!TARGET_ALTIVEC) | |
11547 | return 0; | |
11548 | ||
11549 | /* Get the vector mask for the given relational operations. */ | |
11550 | mask = rs6000_emit_vector_compare (rcode, cc_op0, cc_op1, dest_mode); | |
11551 | ||
11552 | rs6000_emit_vector_select (dest, op1, op2, mask); | |
11553 | ||
11554 | return 1; | |
11555 | } | |
11556 | ||
50a0b056 GK |
11557 | /* Emit a conditional move: move TRUE_COND to DEST if OP of the |
11558 | operands of the last comparison is nonzero/true, FALSE_COND if it | |
11559 | is zero/false. Return 0 if the hardware has no such operation. */ | |
a4f6c312 | 11560 | |
50a0b056 | 11561 | int |
a2369ed3 | 11562 | rs6000_emit_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond) |
50a0b056 GK |
11563 | { |
11564 | enum rtx_code code = GET_CODE (op); | |
11565 | rtx op0 = rs6000_compare_op0; | |
11566 | rtx op1 = rs6000_compare_op1; | |
11567 | REAL_VALUE_TYPE c1; | |
3148ad6d DJ |
11568 | enum machine_mode compare_mode = GET_MODE (op0); |
11569 | enum machine_mode result_mode = GET_MODE (dest); | |
50a0b056 | 11570 | rtx temp; |
add2402e | 11571 | bool is_against_zero; |
50a0b056 | 11572 | |
a3c9585f | 11573 | /* These modes should always match. */ |
a3170dc6 AH |
11574 | if (GET_MODE (op1) != compare_mode |
11575 | /* In the isel case however, we can use a compare immediate, so | |
11576 | op1 may be a small constant. */ | |
11577 | && (!TARGET_ISEL || !short_cint_operand (op1, VOIDmode))) | |
3148ad6d | 11578 | return 0; |
178c3eff | 11579 | if (GET_MODE (true_cond) != result_mode) |
3148ad6d | 11580 | return 0; |
178c3eff | 11581 | if (GET_MODE (false_cond) != result_mode) |
3148ad6d DJ |
11582 | return 0; |
11583 | ||
50a0b056 | 11584 | /* First, work out if the hardware can do this at all, or |
a3c9585f | 11585 | if it's too slow.... */ |
50a0b056 | 11586 | if (! rs6000_compare_fp_p) |
a3170dc6 AH |
11587 | { |
11588 | if (TARGET_ISEL) | |
11589 | return rs6000_emit_int_cmove (dest, op, true_cond, false_cond); | |
11590 | return 0; | |
11591 | } | |
fef98bf2 AH |
11592 | else if (TARGET_E500 && TARGET_HARD_FLOAT && !TARGET_FPRS |
11593 | && GET_MODE_CLASS (compare_mode) == MODE_FLOAT) | |
11594 | return 0; | |
50a0b056 | 11595 | |
add2402e GK |
11596 | is_against_zero = op1 == CONST0_RTX (compare_mode); |
11597 | ||
11598 | /* A floating-point subtract might overflow, underflow, or produce | |
11599 | an inexact result, thus changing the floating-point flags, so it | |
11600 | can't be generated if we care about that. It's safe if one side | |
11601 | of the construct is zero, since then no subtract will be | |
11602 | generated. */ | |
11603 | if (GET_MODE_CLASS (compare_mode) == MODE_FLOAT | |
11604 | && flag_trapping_math && ! is_against_zero) | |
11605 | return 0; | |
11606 | ||
50a0b056 GK |
11607 | /* Eliminate half of the comparisons by switching operands, this |
11608 | makes the remaining code simpler. */ | |
11609 | if (code == UNLT || code == UNGT || code == UNORDERED || code == NE | |
bc9ec0e0 | 11610 | || code == LTGT || code == LT || code == UNLE) |
50a0b056 GK |
11611 | { |
11612 | code = reverse_condition_maybe_unordered (code); | |
11613 | temp = true_cond; | |
11614 | true_cond = false_cond; | |
11615 | false_cond = temp; | |
11616 | } | |
11617 | ||
11618 | /* UNEQ and LTGT take four instructions for a comparison with zero, | |
11619 | it'll probably be faster to use a branch here too. */ | |
bc9ec0e0 | 11620 | if (code == UNEQ && HONOR_NANS (compare_mode)) |
50a0b056 | 11621 | return 0; |
f676971a | 11622 | |
50a0b056 GK |
11623 | if (GET_CODE (op1) == CONST_DOUBLE) |
11624 | REAL_VALUE_FROM_CONST_DOUBLE (c1, op1); | |
f676971a | 11625 | |
b6d08ca1 | 11626 | /* We're going to try to implement comparisons by performing |
50a0b056 GK |
11627 | a subtract, then comparing against zero. Unfortunately, |
11628 | Inf - Inf is NaN which is not zero, and so if we don't | |
27d30956 | 11629 | know that the operand is finite and the comparison |
50a0b056 | 11630 | would treat EQ different to UNORDERED, we can't do it. */ |
bc9ec0e0 | 11631 | if (HONOR_INFINITIES (compare_mode) |
50a0b056 | 11632 | && code != GT && code != UNGE |
045572c7 | 11633 | && (GET_CODE (op1) != CONST_DOUBLE || real_isinf (&c1)) |
50a0b056 GK |
11634 | /* Constructs of the form (a OP b ? a : b) are safe. */ |
11635 | && ((! rtx_equal_p (op0, false_cond) && ! rtx_equal_p (op1, false_cond)) | |
f676971a | 11636 | || (! rtx_equal_p (op0, true_cond) |
50a0b056 GK |
11637 | && ! rtx_equal_p (op1, true_cond)))) |
11638 | return 0; | |
add2402e | 11639 | |
50a0b056 GK |
11640 | /* At this point we know we can use fsel. */ |
11641 | ||
11642 | /* Reduce the comparison to a comparison against zero. */ | |
add2402e GK |
11643 | if (! is_against_zero) |
11644 | { | |
11645 | temp = gen_reg_rtx (compare_mode); | |
11646 | emit_insn (gen_rtx_SET (VOIDmode, temp, | |
11647 | gen_rtx_MINUS (compare_mode, op0, op1))); | |
11648 | op0 = temp; | |
11649 | op1 = CONST0_RTX (compare_mode); | |
11650 | } | |
50a0b056 GK |
11651 | |
11652 | /* If we don't care about NaNs we can reduce some of the comparisons | |
11653 | down to faster ones. */ | |
bc9ec0e0 | 11654 | if (! HONOR_NANS (compare_mode)) |
50a0b056 GK |
11655 | switch (code) |
11656 | { | |
11657 | case GT: | |
11658 | code = LE; | |
11659 | temp = true_cond; | |
11660 | true_cond = false_cond; | |
11661 | false_cond = temp; | |
11662 | break; | |
11663 | case UNGE: | |
11664 | code = GE; | |
11665 | break; | |
11666 | case UNEQ: | |
11667 | code = EQ; | |
11668 | break; | |
11669 | default: | |
11670 | break; | |
11671 | } | |
11672 | ||
11673 | /* Now, reduce everything down to a GE. */ | |
11674 | switch (code) | |
11675 | { | |
11676 | case GE: | |
11677 | break; | |
11678 | ||
11679 | case LE: | |
3148ad6d DJ |
11680 | temp = gen_reg_rtx (compare_mode); |
11681 | emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0))); | |
50a0b056 GK |
11682 | op0 = temp; |
11683 | break; | |
11684 | ||
11685 | case ORDERED: | |
3148ad6d DJ |
11686 | temp = gen_reg_rtx (compare_mode); |
11687 | emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_ABS (compare_mode, op0))); | |
50a0b056 GK |
11688 | op0 = temp; |
11689 | break; | |
11690 | ||
11691 | case EQ: | |
3148ad6d | 11692 | temp = gen_reg_rtx (compare_mode); |
f676971a | 11693 | emit_insn (gen_rtx_SET (VOIDmode, temp, |
3148ad6d DJ |
11694 | gen_rtx_NEG (compare_mode, |
11695 | gen_rtx_ABS (compare_mode, op0)))); | |
50a0b056 GK |
11696 | op0 = temp; |
11697 | break; | |
11698 | ||
11699 | case UNGE: | |
bc9ec0e0 | 11700 | /* a UNGE 0 <-> (a GE 0 || -a UNLT 0) */ |
3148ad6d | 11701 | temp = gen_reg_rtx (result_mode); |
50a0b056 | 11702 | emit_insn (gen_rtx_SET (VOIDmode, temp, |
3148ad6d | 11703 | gen_rtx_IF_THEN_ELSE (result_mode, |
50a0b056 GK |
11704 | gen_rtx_GE (VOIDmode, |
11705 | op0, op1), | |
11706 | true_cond, false_cond))); | |
bc9ec0e0 GK |
11707 | false_cond = true_cond; |
11708 | true_cond = temp; | |
50a0b056 | 11709 | |
3148ad6d DJ |
11710 | temp = gen_reg_rtx (compare_mode); |
11711 | emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0))); | |
50a0b056 GK |
11712 | op0 = temp; |
11713 | break; | |
11714 | ||
11715 | case GT: | |
bc9ec0e0 | 11716 | /* a GT 0 <-> (a GE 0 && -a UNLT 0) */ |
3148ad6d | 11717 | temp = gen_reg_rtx (result_mode); |
50a0b056 | 11718 | emit_insn (gen_rtx_SET (VOIDmode, temp, |
f676971a | 11719 | gen_rtx_IF_THEN_ELSE (result_mode, |
50a0b056 GK |
11720 | gen_rtx_GE (VOIDmode, |
11721 | op0, op1), | |
11722 | true_cond, false_cond))); | |
bc9ec0e0 GK |
11723 | true_cond = false_cond; |
11724 | false_cond = temp; | |
50a0b056 | 11725 | |
3148ad6d DJ |
11726 | temp = gen_reg_rtx (compare_mode); |
11727 | emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0))); | |
50a0b056 GK |
11728 | op0 = temp; |
11729 | break; | |
11730 | ||
11731 | default: | |
11732 | abort (); | |
11733 | } | |
11734 | ||
11735 | emit_insn (gen_rtx_SET (VOIDmode, dest, | |
3148ad6d | 11736 | gen_rtx_IF_THEN_ELSE (result_mode, |
50a0b056 GK |
11737 | gen_rtx_GE (VOIDmode, |
11738 | op0, op1), | |
11739 | true_cond, false_cond))); | |
11740 | return 1; | |
11741 | } | |
11742 | ||
a3170dc6 AH |
11743 | /* Same as above, but for ints (isel). */ |
11744 | ||
11745 | static int | |
a2369ed3 | 11746 | rs6000_emit_int_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond) |
a3170dc6 AH |
11747 | { |
11748 | rtx condition_rtx, cr; | |
11749 | ||
11750 | /* All isel implementations thus far are 32-bits. */ | |
11751 | if (GET_MODE (rs6000_compare_op0) != SImode) | |
11752 | return 0; | |
11753 | ||
11754 | /* We still have to do the compare, because isel doesn't do a | |
11755 | compare, it just looks at the CRx bits set by a previous compare | |
11756 | instruction. */ | |
11757 | condition_rtx = rs6000_generate_compare (GET_CODE (op)); | |
11758 | cr = XEXP (condition_rtx, 0); | |
11759 | ||
11760 | if (GET_MODE (cr) == CCmode) | |
11761 | emit_insn (gen_isel_signed (dest, condition_rtx, | |
11762 | true_cond, false_cond, cr)); | |
11763 | else | |
11764 | emit_insn (gen_isel_unsigned (dest, condition_rtx, | |
11765 | true_cond, false_cond, cr)); | |
11766 | ||
11767 | return 1; | |
11768 | } | |
11769 | ||
11770 | const char * | |
a2369ed3 | 11771 | output_isel (rtx *operands) |
a3170dc6 AH |
11772 | { |
11773 | enum rtx_code code; | |
11774 | ||
11775 | code = GET_CODE (operands[1]); | |
11776 | if (code == GE || code == GEU || code == LE || code == LEU || code == NE) | |
11777 | { | |
11778 | PUT_CODE (operands[1], reverse_condition (code)); | |
11779 | return "isel %0,%3,%2,%j1"; | |
11780 | } | |
11781 | else | |
11782 | return "isel %0,%2,%3,%j1"; | |
11783 | } | |
11784 | ||
50a0b056 | 11785 | void |
a2369ed3 | 11786 | rs6000_emit_minmax (rtx dest, enum rtx_code code, rtx op0, rtx op1) |
50a0b056 GK |
11787 | { |
11788 | enum machine_mode mode = GET_MODE (op0); | |
5dc8d536 | 11789 | enum rtx_code c; |
50a0b056 | 11790 | rtx target; |
5dc8d536 AH |
11791 | |
11792 | if (code == SMAX || code == SMIN) | |
11793 | c = GE; | |
11794 | else | |
11795 | c = GEU; | |
11796 | ||
50a0b056 | 11797 | if (code == SMAX || code == UMAX) |
f676971a | 11798 | target = emit_conditional_move (dest, c, op0, op1, mode, |
50a0b056 GK |
11799 | op0, op1, mode, 0); |
11800 | else | |
f676971a | 11801 | target = emit_conditional_move (dest, c, op0, op1, mode, |
50a0b056 GK |
11802 | op1, op0, mode, 0); |
11803 | if (target == NULL_RTX) | |
11804 | abort (); | |
11805 | if (target != dest) | |
11806 | emit_move_insn (dest, target); | |
11807 | } | |
46c07df8 | 11808 | |
a9baceb1 GK |
11809 | /* Emit instructions to move SRC to DST. Called by splitters for |
11810 | multi-register moves. It will emit at most one instruction for | |
11811 | each register that is accessed; that is, it won't emit li/lis pairs | |
11812 | (or equivalent for 64-bit code). One of SRC or DST must be a hard | |
11813 | register. */ | |
46c07df8 | 11814 | |
46c07df8 | 11815 | void |
a9baceb1 | 11816 | rs6000_split_multireg_move (rtx dst, rtx src) |
46c07df8 | 11817 | { |
a9baceb1 GK |
11818 | /* The register number of the first register being moved. */ |
11819 | int reg; | |
11820 | /* The mode that is to be moved. */ | |
11821 | enum machine_mode mode; | |
11822 | /* The mode that the move is being done in, and its size. */ | |
11823 | enum machine_mode reg_mode; | |
11824 | int reg_mode_size; | |
11825 | /* The number of registers that will be moved. */ | |
11826 | int nregs; | |
11827 | ||
11828 | reg = REG_P (dst) ? REGNO (dst) : REGNO (src); | |
11829 | mode = GET_MODE (dst); | |
11830 | nregs = HARD_REGNO_NREGS (reg, mode); | |
11831 | if (FP_REGNO_P (reg)) | |
11832 | reg_mode = DFmode; | |
11833 | else if (ALTIVEC_REGNO_P (reg)) | |
11834 | reg_mode = V16QImode; | |
11835 | else | |
11836 | reg_mode = word_mode; | |
11837 | reg_mode_size = GET_MODE_SIZE (reg_mode); | |
f676971a | 11838 | |
a9baceb1 GK |
11839 | if (reg_mode_size * nregs != GET_MODE_SIZE (mode)) |
11840 | abort (); | |
f676971a | 11841 | |
a9baceb1 GK |
11842 | if (REG_P (src) && REG_P (dst) && (REGNO (src) < REGNO (dst))) |
11843 | { | |
11844 | /* Move register range backwards, if we might have destructive | |
11845 | overlap. */ | |
11846 | int i; | |
11847 | for (i = nregs - 1; i >= 0; i--) | |
f676971a | 11848 | emit_insn (gen_rtx_SET (VOIDmode, |
a9baceb1 GK |
11849 | simplify_gen_subreg (reg_mode, dst, mode, |
11850 | i * reg_mode_size), | |
11851 | simplify_gen_subreg (reg_mode, src, mode, | |
11852 | i * reg_mode_size))); | |
11853 | } | |
46c07df8 HP |
11854 | else |
11855 | { | |
a9baceb1 GK |
11856 | int i; |
11857 | int j = -1; | |
11858 | bool used_update = false; | |
46c07df8 | 11859 | |
c1e55850 | 11860 | if (MEM_P (src) && INT_REGNO_P (reg)) |
c4ad648e AM |
11861 | { |
11862 | rtx breg; | |
3a1f863f | 11863 | |
a9baceb1 GK |
11864 | if (GET_CODE (XEXP (src, 0)) == PRE_INC |
11865 | || GET_CODE (XEXP (src, 0)) == PRE_DEC) | |
3a1f863f DE |
11866 | { |
11867 | rtx delta_rtx; | |
a9baceb1 | 11868 | breg = XEXP (XEXP (src, 0), 0); |
c4ad648e AM |
11869 | delta_rtx = (GET_CODE (XEXP (src, 0)) == PRE_INC |
11870 | ? GEN_INT (GET_MODE_SIZE (GET_MODE (src))) | |
11871 | : GEN_INT (-GET_MODE_SIZE (GET_MODE (src)))); | |
a9baceb1 GK |
11872 | emit_insn (TARGET_32BIT |
11873 | ? gen_addsi3 (breg, breg, delta_rtx) | |
11874 | : gen_adddi3 (breg, breg, delta_rtx)); | |
3a1f863f DE |
11875 | src = gen_rtx_MEM (mode, breg); |
11876 | } | |
c1e55850 GK |
11877 | else if (! offsettable_memref_p (src)) |
11878 | { | |
11879 | rtx newsrc, basereg; | |
11880 | basereg = gen_rtx_REG (Pmode, reg); | |
11881 | emit_insn (gen_rtx_SET (VOIDmode, basereg, XEXP (src, 0))); | |
11882 | newsrc = gen_rtx_MEM (GET_MODE (src), basereg); | |
11883 | MEM_COPY_ATTRIBUTES (newsrc, src); | |
11884 | src = newsrc; | |
11885 | } | |
3a1f863f | 11886 | |
0423421f AM |
11887 | breg = XEXP (src, 0); |
11888 | if (GET_CODE (breg) == PLUS || GET_CODE (breg) == LO_SUM) | |
11889 | breg = XEXP (breg, 0); | |
11890 | ||
11891 | /* If the base register we are using to address memory is | |
11892 | also a destination reg, then change that register last. */ | |
11893 | if (REG_P (breg) | |
11894 | && REGNO (breg) >= REGNO (dst) | |
3a1f863f DE |
11895 | && REGNO (breg) < REGNO (dst) + nregs) |
11896 | j = REGNO (breg) - REGNO (dst); | |
c4ad648e | 11897 | } |
46c07df8 | 11898 | |
a9baceb1 | 11899 | if (GET_CODE (dst) == MEM && INT_REGNO_P (reg)) |
3a1f863f DE |
11900 | { |
11901 | rtx breg; | |
11902 | ||
a9baceb1 GK |
11903 | if (GET_CODE (XEXP (dst, 0)) == PRE_INC |
11904 | || GET_CODE (XEXP (dst, 0)) == PRE_DEC) | |
3a1f863f DE |
11905 | { |
11906 | rtx delta_rtx; | |
a9baceb1 | 11907 | breg = XEXP (XEXP (dst, 0), 0); |
c4ad648e AM |
11908 | delta_rtx = (GET_CODE (XEXP (dst, 0)) == PRE_INC |
11909 | ? GEN_INT (GET_MODE_SIZE (GET_MODE (dst))) | |
11910 | : GEN_INT (-GET_MODE_SIZE (GET_MODE (dst)))); | |
3a1f863f DE |
11911 | |
11912 | /* We have to update the breg before doing the store. | |
11913 | Use store with update, if available. */ | |
11914 | ||
11915 | if (TARGET_UPDATE) | |
11916 | { | |
a9baceb1 | 11917 | rtx nsrc = simplify_gen_subreg (reg_mode, src, mode, 0); |
c4ad648e AM |
11918 | emit_insn (TARGET_32BIT |
11919 | ? (TARGET_POWERPC64 | |
11920 | ? gen_movdi_si_update (breg, breg, delta_rtx, nsrc) | |
11921 | : gen_movsi_update (breg, breg, delta_rtx, nsrc)) | |
11922 | : gen_movdi_di_update (breg, breg, delta_rtx, nsrc)); | |
a9baceb1 | 11923 | used_update = true; |
3a1f863f DE |
11924 | } |
11925 | else | |
a9baceb1 GK |
11926 | emit_insn (TARGET_32BIT |
11927 | ? gen_addsi3 (breg, breg, delta_rtx) | |
11928 | : gen_adddi3 (breg, breg, delta_rtx)); | |
3a1f863f DE |
11929 | dst = gen_rtx_MEM (mode, breg); |
11930 | } | |
c1e55850 | 11931 | else if (! offsettable_memref_p (dst)) |
112ccb83 | 11932 | abort (); |
3a1f863f DE |
11933 | } |
11934 | ||
46c07df8 | 11935 | for (i = 0; i < nregs; i++) |
f676971a | 11936 | { |
3a1f863f DE |
11937 | /* Calculate index to next subword. */ |
11938 | ++j; | |
f676971a | 11939 | if (j == nregs) |
3a1f863f | 11940 | j = 0; |
46c07df8 | 11941 | |
112cdef5 | 11942 | /* If compiler already emitted move of first word by |
a9baceb1 | 11943 | store with update, no need to do anything. */ |
3a1f863f | 11944 | if (j == 0 && used_update) |
a9baceb1 | 11945 | continue; |
f676971a | 11946 | |
a9baceb1 GK |
11947 | emit_insn (gen_rtx_SET (VOIDmode, |
11948 | simplify_gen_subreg (reg_mode, dst, mode, | |
11949 | j * reg_mode_size), | |
11950 | simplify_gen_subreg (reg_mode, src, mode, | |
11951 | j * reg_mode_size))); | |
3a1f863f | 11952 | } |
46c07df8 HP |
11953 | } |
11954 | } | |
11955 | ||
12a4e8c5 | 11956 | \f |
a4f6c312 SS |
11957 | /* This page contains routines that are used to determine what the |
11958 | function prologue and epilogue code will do and write them out. */ | |
9878760c | 11959 | |
a4f6c312 SS |
11960 | /* Return the first fixed-point register that is required to be |
11961 | saved. 32 if none. */ | |
9878760c RK |
11962 | |
11963 | int | |
863d938c | 11964 | first_reg_to_save (void) |
9878760c RK |
11965 | { |
11966 | int first_reg; | |
11967 | ||
11968 | /* Find lowest numbered live register. */ | |
11969 | for (first_reg = 13; first_reg <= 31; first_reg++) | |
f676971a | 11970 | if (regs_ever_live[first_reg] |
a38d360d | 11971 | && (! call_used_regs[first_reg] |
1db02437 | 11972 | || (first_reg == RS6000_PIC_OFFSET_TABLE_REGNUM |
14f00213 | 11973 | && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0) |
b4db40bf JJ |
11974 | || (DEFAULT_ABI == ABI_DARWIN && flag_pic) |
11975 | || (TARGET_TOC && TARGET_MINIMAL_TOC))))) | |
9878760c RK |
11976 | break; |
11977 | ||
ee890fe2 | 11978 | #if TARGET_MACHO |
93638d7a AM |
11979 | if (flag_pic |
11980 | && current_function_uses_pic_offset_table | |
11981 | && first_reg > RS6000_PIC_OFFSET_TABLE_REGNUM) | |
1db02437 | 11982 | return RS6000_PIC_OFFSET_TABLE_REGNUM; |
ee890fe2 SS |
11983 | #endif |
11984 | ||
9878760c RK |
11985 | return first_reg; |
11986 | } | |
11987 | ||
11988 | /* Similar, for FP regs. */ | |
11989 | ||
11990 | int | |
863d938c | 11991 | first_fp_reg_to_save (void) |
9878760c RK |
11992 | { |
11993 | int first_reg; | |
11994 | ||
11995 | /* Find lowest numbered live register. */ | |
11996 | for (first_reg = 14 + 32; first_reg <= 63; first_reg++) | |
11997 | if (regs_ever_live[first_reg]) | |
11998 | break; | |
11999 | ||
12000 | return first_reg; | |
12001 | } | |
00b960c7 AH |
12002 | |
12003 | /* Similar, for AltiVec regs. */ | |
12004 | ||
12005 | static int | |
863d938c | 12006 | first_altivec_reg_to_save (void) |
00b960c7 AH |
12007 | { |
12008 | int i; | |
12009 | ||
12010 | /* Stack frame remains as is unless we are in AltiVec ABI. */ | |
12011 | if (! TARGET_ALTIVEC_ABI) | |
12012 | return LAST_ALTIVEC_REGNO + 1; | |
12013 | ||
12014 | /* Find lowest numbered live register. */ | |
12015 | for (i = FIRST_ALTIVEC_REGNO + 20; i <= LAST_ALTIVEC_REGNO; ++i) | |
12016 | if (regs_ever_live[i]) | |
12017 | break; | |
12018 | ||
12019 | return i; | |
12020 | } | |
12021 | ||
12022 | /* Return a 32-bit mask of the AltiVec registers we need to set in | |
12023 | VRSAVE. Bit n of the return value is 1 if Vn is live. The MSB in | |
12024 | the 32-bit word is 0. */ | |
12025 | ||
12026 | static unsigned int | |
863d938c | 12027 | compute_vrsave_mask (void) |
00b960c7 AH |
12028 | { |
12029 | unsigned int i, mask = 0; | |
12030 | ||
12031 | /* First, find out if we use _any_ altivec registers. */ | |
12032 | for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i) | |
12033 | if (regs_ever_live[i]) | |
12034 | mask |= ALTIVEC_REG_BIT (i); | |
12035 | ||
12036 | if (mask == 0) | |
12037 | return mask; | |
12038 | ||
00b960c7 AH |
12039 | /* Next, remove the argument registers from the set. These must |
12040 | be in the VRSAVE mask set by the caller, so we don't need to add | |
12041 | them in again. More importantly, the mask we compute here is | |
12042 | used to generate CLOBBERs in the set_vrsave insn, and we do not | |
12043 | wish the argument registers to die. */ | |
a6cf80f2 | 12044 | for (i = cfun->args_info.vregno - 1; i >= ALTIVEC_ARG_MIN_REG; --i) |
00b960c7 AH |
12045 | mask &= ~ALTIVEC_REG_BIT (i); |
12046 | ||
12047 | /* Similarly, remove the return value from the set. */ | |
12048 | { | |
12049 | bool yes = false; | |
12050 | diddle_return_value (is_altivec_return_reg, &yes); | |
12051 | if (yes) | |
12052 | mask &= ~ALTIVEC_REG_BIT (ALTIVEC_ARG_RETURN); | |
12053 | } | |
12054 | ||
12055 | return mask; | |
12056 | } | |
12057 | ||
d62294f5 FJ |
12058 | /* For a very restricted set of circumstances, we can cut down the |
12059 | size of prologs/epilogs by calling our own save/restore-the-world | |
12060 | routines. */ | |
12061 | ||
12062 | static void | |
12063 | compute_save_world_info(rs6000_stack_t *info_ptr) | |
12064 | { | |
12065 | info_ptr->world_save_p = | |
12066 | (DEFAULT_ABI == ABI_DARWIN) | |
12067 | && ! (current_function_calls_setjmp && flag_exceptions) | |
12068 | && info_ptr->first_fp_reg_save == FIRST_SAVED_FP_REGNO | |
12069 | && info_ptr->first_gp_reg_save == FIRST_SAVED_GP_REGNO | |
12070 | && info_ptr->first_altivec_reg_save == FIRST_SAVED_ALTIVEC_REGNO | |
12071 | && info_ptr->cr_save_p; | |
f676971a | 12072 | |
d62294f5 FJ |
12073 | /* This will not work in conjunction with sibcalls. Make sure there |
12074 | are none. (This check is expensive, but seldom executed.) */ | |
12075 | if ( info_ptr->world_save_p ) | |
f676971a | 12076 | { |
d62294f5 FJ |
12077 | rtx insn; |
12078 | for ( insn = get_last_insn_anywhere (); insn; insn = PREV_INSN (insn)) | |
c4ad648e AM |
12079 | if ( GET_CODE (insn) == CALL_INSN |
12080 | && SIBLING_CALL_P (insn)) | |
12081 | { | |
12082 | info_ptr->world_save_p = 0; | |
12083 | break; | |
12084 | } | |
d62294f5 | 12085 | } |
f676971a | 12086 | |
d62294f5 FJ |
12087 | if (info_ptr->world_save_p) |
12088 | { | |
12089 | /* Even if we're not touching VRsave, make sure there's room on the | |
12090 | stack for it, if it looks like we're calling SAVE_WORLD, which | |
c4ad648e | 12091 | will attempt to save it. */ |
d62294f5 FJ |
12092 | info_ptr->vrsave_size = 4; |
12093 | ||
12094 | /* "Save" the VRsave register too if we're saving the world. */ | |
12095 | if (info_ptr->vrsave_mask == 0) | |
c4ad648e | 12096 | info_ptr->vrsave_mask = compute_vrsave_mask (); |
d62294f5 FJ |
12097 | |
12098 | /* Because the Darwin register save/restore routines only handle | |
c4ad648e AM |
12099 | F14 .. F31 and V20 .. V31 as per the ABI, perform a consistency |
12100 | check and abort if there's something worng. */ | |
f676971a | 12101 | if (info_ptr->first_fp_reg_save < FIRST_SAVED_FP_REGNO |
c4ad648e AM |
12102 | || info_ptr->first_altivec_reg_save < FIRST_SAVED_ALTIVEC_REGNO) |
12103 | abort (); | |
d62294f5 | 12104 | } |
f676971a | 12105 | return; |
d62294f5 FJ |
12106 | } |
12107 | ||
12108 | ||
00b960c7 | 12109 | static void |
a2369ed3 | 12110 | is_altivec_return_reg (rtx reg, void *xyes) |
00b960c7 AH |
12111 | { |
12112 | bool *yes = (bool *) xyes; | |
12113 | if (REGNO (reg) == ALTIVEC_ARG_RETURN) | |
12114 | *yes = true; | |
12115 | } | |
12116 | ||
4697a36c MM |
12117 | \f |
12118 | /* Calculate the stack information for the current function. This is | |
12119 | complicated by having two separate calling sequences, the AIX calling | |
12120 | sequence and the V.4 calling sequence. | |
12121 | ||
592696dd | 12122 | AIX (and Darwin/Mac OS X) stack frames look like: |
a260abc9 | 12123 | 32-bit 64-bit |
4697a36c | 12124 | SP----> +---------------------------------------+ |
a260abc9 | 12125 | | back chain to caller | 0 0 |
4697a36c | 12126 | +---------------------------------------+ |
a260abc9 | 12127 | | saved CR | 4 8 (8-11) |
4697a36c | 12128 | +---------------------------------------+ |
a260abc9 | 12129 | | saved LR | 8 16 |
4697a36c | 12130 | +---------------------------------------+ |
a260abc9 | 12131 | | reserved for compilers | 12 24 |
4697a36c | 12132 | +---------------------------------------+ |
a260abc9 | 12133 | | reserved for binders | 16 32 |
4697a36c | 12134 | +---------------------------------------+ |
a260abc9 | 12135 | | saved TOC pointer | 20 40 |
4697a36c | 12136 | +---------------------------------------+ |
a260abc9 | 12137 | | Parameter save area (P) | 24 48 |
4697a36c | 12138 | +---------------------------------------+ |
a260abc9 | 12139 | | Alloca space (A) | 24+P etc. |
802a0058 | 12140 | +---------------------------------------+ |
a7df97e6 | 12141 | | Local variable space (L) | 24+P+A |
4697a36c | 12142 | +---------------------------------------+ |
a7df97e6 | 12143 | | Float/int conversion temporary (X) | 24+P+A+L |
4697a36c | 12144 | +---------------------------------------+ |
00b960c7 AH |
12145 | | Save area for AltiVec registers (W) | 24+P+A+L+X |
12146 | +---------------------------------------+ | |
12147 | | AltiVec alignment padding (Y) | 24+P+A+L+X+W | |
12148 | +---------------------------------------+ | |
12149 | | Save area for VRSAVE register (Z) | 24+P+A+L+X+W+Y | |
4697a36c | 12150 | +---------------------------------------+ |
00b960c7 AH |
12151 | | Save area for GP registers (G) | 24+P+A+X+L+X+W+Y+Z |
12152 | +---------------------------------------+ | |
12153 | | Save area for FP registers (F) | 24+P+A+X+L+X+W+Y+Z+G | |
4697a36c MM |
12154 | +---------------------------------------+ |
12155 | old SP->| back chain to caller's caller | | |
12156 | +---------------------------------------+ | |
12157 | ||
5376a30c KR |
12158 | The required alignment for AIX configurations is two words (i.e., 8 |
12159 | or 16 bytes). | |
12160 | ||
12161 | ||
4697a36c MM |
12162 | V.4 stack frames look like: |
12163 | ||
12164 | SP----> +---------------------------------------+ | |
12165 | | back chain to caller | 0 | |
12166 | +---------------------------------------+ | |
5eb387b8 | 12167 | | caller's saved LR | 4 |
4697a36c MM |
12168 | +---------------------------------------+ |
12169 | | Parameter save area (P) | 8 | |
12170 | +---------------------------------------+ | |
a7df97e6 | 12171 | | Alloca space (A) | 8+P |
f676971a | 12172 | +---------------------------------------+ |
a7df97e6 | 12173 | | Varargs save area (V) | 8+P+A |
f676971a | 12174 | +---------------------------------------+ |
a7df97e6 | 12175 | | Local variable space (L) | 8+P+A+V |
f676971a | 12176 | +---------------------------------------+ |
a7df97e6 | 12177 | | Float/int conversion temporary (X) | 8+P+A+V+L |
4697a36c | 12178 | +---------------------------------------+ |
00b960c7 AH |
12179 | | Save area for AltiVec registers (W) | 8+P+A+V+L+X |
12180 | +---------------------------------------+ | |
12181 | | AltiVec alignment padding (Y) | 8+P+A+V+L+X+W | |
12182 | +---------------------------------------+ | |
12183 | | Save area for VRSAVE register (Z) | 8+P+A+V+L+X+W+Y | |
12184 | +---------------------------------------+ | |
c4ad648e AM |
12185 | | SPE: area for 64-bit GP registers | |
12186 | +---------------------------------------+ | |
12187 | | SPE alignment padding | | |
12188 | +---------------------------------------+ | |
00b960c7 | 12189 | | saved CR (C) | 8+P+A+V+L+X+W+Y+Z |
f676971a | 12190 | +---------------------------------------+ |
00b960c7 | 12191 | | Save area for GP registers (G) | 8+P+A+V+L+X+W+Y+Z+C |
f676971a | 12192 | +---------------------------------------+ |
00b960c7 | 12193 | | Save area for FP registers (F) | 8+P+A+V+L+X+W+Y+Z+C+G |
4697a36c MM |
12194 | +---------------------------------------+ |
12195 | old SP->| back chain to caller's caller | | |
12196 | +---------------------------------------+ | |
b6c9286a | 12197 | |
5376a30c KR |
12198 | The required alignment for V.4 is 16 bytes, or 8 bytes if -meabi is |
12199 | given. (But note below and in sysv4.h that we require only 8 and | |
12200 | may round up the size of our stack frame anyways. The historical | |
12201 | reason is early versions of powerpc-linux which didn't properly | |
12202 | align the stack at program startup. A happy side-effect is that | |
12203 | -mno-eabi libraries can be used with -meabi programs.) | |
12204 | ||
50d440bc | 12205 | The EABI configuration defaults to the V.4 layout. However, |
5376a30c KR |
12206 | the stack alignment requirements may differ. If -mno-eabi is not |
12207 | given, the required stack alignment is 8 bytes; if -mno-eabi is | |
12208 | given, the required alignment is 16 bytes. (But see V.4 comment | |
12209 | above.) */ | |
4697a36c | 12210 | |
61b2fbe7 MM |
12211 | #ifndef ABI_STACK_BOUNDARY |
12212 | #define ABI_STACK_BOUNDARY STACK_BOUNDARY | |
12213 | #endif | |
12214 | ||
d1d0c603 | 12215 | static rs6000_stack_t * |
863d938c | 12216 | rs6000_stack_info (void) |
4697a36c MM |
12217 | { |
12218 | static rs6000_stack_t info, zero_info; | |
12219 | rs6000_stack_t *info_ptr = &info; | |
327e5343 | 12220 | int reg_size = TARGET_32BIT ? 4 : 8; |
83720594 | 12221 | int ehrd_size; |
64045029 | 12222 | int save_align; |
44688022 | 12223 | HOST_WIDE_INT non_fixed_size; |
4697a36c | 12224 | |
a4f6c312 | 12225 | /* Zero all fields portably. */ |
4697a36c MM |
12226 | info = zero_info; |
12227 | ||
c19de7aa AH |
12228 | if (TARGET_SPE) |
12229 | { | |
12230 | /* Cache value so we don't rescan instruction chain over and over. */ | |
9b7b447f AH |
12231 | if (cfun->machine->insn_chain_scanned_p == 0) |
12232 | { | |
12233 | cfun->machine->insn_chain_scanned_p = 1; | |
12234 | info_ptr->spe_64bit_regs_used = (int) spe_func_has_64bit_regs_p (); | |
12235 | } | |
c19de7aa AH |
12236 | } |
12237 | ||
a4f6c312 | 12238 | /* Select which calling sequence. */ |
178274da | 12239 | info_ptr->abi = DEFAULT_ABI; |
9878760c | 12240 | |
a4f6c312 | 12241 | /* Calculate which registers need to be saved & save area size. */ |
4697a36c | 12242 | info_ptr->first_gp_reg_save = first_reg_to_save (); |
f676971a | 12243 | /* Assume that we will have to save RS6000_PIC_OFFSET_TABLE_REGNUM, |
906fb125 | 12244 | even if it currently looks like we won't. */ |
2bfcf297 | 12245 | if (((TARGET_TOC && TARGET_MINIMAL_TOC) |
178274da AM |
12246 | || (flag_pic == 1 && DEFAULT_ABI == ABI_V4) |
12247 | || (flag_pic && DEFAULT_ABI == ABI_DARWIN)) | |
1db02437 FS |
12248 | && info_ptr->first_gp_reg_save > RS6000_PIC_OFFSET_TABLE_REGNUM) |
12249 | info_ptr->gp_size = reg_size * (32 - RS6000_PIC_OFFSET_TABLE_REGNUM); | |
906fb125 GK |
12250 | else |
12251 | info_ptr->gp_size = reg_size * (32 - info_ptr->first_gp_reg_save); | |
4697a36c | 12252 | |
a3170dc6 AH |
12253 | /* For the SPE, we have an additional upper 32-bits on each GPR. |
12254 | Ideally we should save the entire 64-bits only when the upper | |
12255 | half is used in SIMD instructions. Since we only record | |
12256 | registers live (not the size they are used in), this proves | |
12257 | difficult because we'd have to traverse the instruction chain at | |
12258 | the right time, taking reload into account. This is a real pain, | |
c19de7aa AH |
12259 | so we opt to save the GPRs in 64-bits always if but one register |
12260 | gets used in 64-bits. Otherwise, all the registers in the frame | |
12261 | get saved in 32-bits. | |
a3170dc6 | 12262 | |
c19de7aa | 12263 | So... since when we save all GPRs (except the SP) in 64-bits, the |
a3170dc6 | 12264 | traditional GP save area will be empty. */ |
c19de7aa | 12265 | if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0) |
a3170dc6 AH |
12266 | info_ptr->gp_size = 0; |
12267 | ||
4697a36c MM |
12268 | info_ptr->first_fp_reg_save = first_fp_reg_to_save (); |
12269 | info_ptr->fp_size = 8 * (64 - info_ptr->first_fp_reg_save); | |
12270 | ||
00b960c7 AH |
12271 | info_ptr->first_altivec_reg_save = first_altivec_reg_to_save (); |
12272 | info_ptr->altivec_size = 16 * (LAST_ALTIVEC_REGNO + 1 | |
12273 | - info_ptr->first_altivec_reg_save); | |
12274 | ||
592696dd | 12275 | /* Does this function call anything? */ |
71f123ca FS |
12276 | info_ptr->calls_p = (! current_function_is_leaf |
12277 | || cfun->machine->ra_needs_full_frame); | |
b6c9286a | 12278 | |
a4f6c312 | 12279 | /* Determine if we need to save the link register. */ |
71f123ca | 12280 | if (rs6000_ra_ever_killed () |
ffcfcb5f AM |
12281 | || (DEFAULT_ABI == ABI_AIX |
12282 | && current_function_profile | |
12283 | && !TARGET_PROFILE_KERNEL) | |
4697a36c MM |
12284 | #ifdef TARGET_RELOCATABLE |
12285 | || (TARGET_RELOCATABLE && (get_pool_size () != 0)) | |
12286 | #endif | |
12287 | || (info_ptr->first_fp_reg_save != 64 | |
12288 | && !FP_SAVE_INLINE (info_ptr->first_fp_reg_save)) | |
00b960c7 | 12289 | || info_ptr->first_altivec_reg_save <= LAST_ALTIVEC_REGNO |
178274da | 12290 | || (DEFAULT_ABI == ABI_V4 && current_function_calls_alloca) |
a4f6c312 SS |
12291 | || (DEFAULT_ABI == ABI_DARWIN |
12292 | && flag_pic | |
12293 | && current_function_uses_pic_offset_table) | |
4697a36c MM |
12294 | || info_ptr->calls_p) |
12295 | { | |
12296 | info_ptr->lr_save_p = 1; | |
9ebbca7d | 12297 | regs_ever_live[LINK_REGISTER_REGNUM] = 1; |
4697a36c MM |
12298 | } |
12299 | ||
9ebbca7d | 12300 | /* Determine if we need to save the condition code registers. */ |
f676971a | 12301 | if (regs_ever_live[CR2_REGNO] |
9ebbca7d GK |
12302 | || regs_ever_live[CR3_REGNO] |
12303 | || regs_ever_live[CR4_REGNO]) | |
4697a36c MM |
12304 | { |
12305 | info_ptr->cr_save_p = 1; | |
178274da | 12306 | if (DEFAULT_ABI == ABI_V4) |
4697a36c MM |
12307 | info_ptr->cr_size = reg_size; |
12308 | } | |
12309 | ||
83720594 RH |
12310 | /* If the current function calls __builtin_eh_return, then we need |
12311 | to allocate stack space for registers that will hold data for | |
12312 | the exception handler. */ | |
12313 | if (current_function_calls_eh_return) | |
12314 | { | |
12315 | unsigned int i; | |
12316 | for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; ++i) | |
12317 | continue; | |
a3170dc6 AH |
12318 | |
12319 | /* SPE saves EH registers in 64-bits. */ | |
c19de7aa AH |
12320 | ehrd_size = i * (TARGET_SPE_ABI |
12321 | && info_ptr->spe_64bit_regs_used != 0 | |
12322 | ? UNITS_PER_SPE_WORD : UNITS_PER_WORD); | |
83720594 RH |
12323 | } |
12324 | else | |
12325 | ehrd_size = 0; | |
12326 | ||
592696dd | 12327 | /* Determine various sizes. */ |
4697a36c MM |
12328 | info_ptr->reg_size = reg_size; |
12329 | info_ptr->fixed_size = RS6000_SAVE_AREA; | |
12330 | info_ptr->varargs_size = RS6000_VARARGS_AREA; | |
189e03e3 | 12331 | info_ptr->vars_size = RS6000_ALIGN (get_frame_size (), 8); |
a4f6c312 | 12332 | info_ptr->parm_size = RS6000_ALIGN (current_function_outgoing_args_size, |
03e007d7 | 12333 | TARGET_ALTIVEC ? 16 : 8); |
00b960c7 | 12334 | |
c19de7aa | 12335 | if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0) |
a3170dc6 AH |
12336 | info_ptr->spe_gp_size = 8 * (32 - info_ptr->first_gp_reg_save); |
12337 | else | |
12338 | info_ptr->spe_gp_size = 0; | |
12339 | ||
4d774ff8 HP |
12340 | if (TARGET_ALTIVEC_ABI) |
12341 | info_ptr->vrsave_mask = compute_vrsave_mask (); | |
00b960c7 | 12342 | else |
4d774ff8 HP |
12343 | info_ptr->vrsave_mask = 0; |
12344 | ||
12345 | if (TARGET_ALTIVEC_VRSAVE && info_ptr->vrsave_mask) | |
12346 | info_ptr->vrsave_size = 4; | |
12347 | else | |
12348 | info_ptr->vrsave_size = 0; | |
b6c9286a | 12349 | |
d62294f5 FJ |
12350 | compute_save_world_info (info_ptr); |
12351 | ||
592696dd | 12352 | /* Calculate the offsets. */ |
178274da | 12353 | switch (DEFAULT_ABI) |
4697a36c | 12354 | { |
b6c9286a | 12355 | case ABI_NONE: |
24d304eb | 12356 | default: |
b6c9286a MM |
12357 | abort (); |
12358 | ||
12359 | case ABI_AIX: | |
ee890fe2 | 12360 | case ABI_DARWIN: |
b6c9286a MM |
12361 | info_ptr->fp_save_offset = - info_ptr->fp_size; |
12362 | info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size; | |
00b960c7 AH |
12363 | |
12364 | if (TARGET_ALTIVEC_ABI) | |
12365 | { | |
12366 | info_ptr->vrsave_save_offset | |
12367 | = info_ptr->gp_save_offset - info_ptr->vrsave_size; | |
12368 | ||
12369 | /* Align stack so vector save area is on a quadword boundary. */ | |
12370 | if (info_ptr->altivec_size != 0) | |
12371 | info_ptr->altivec_padding_size | |
12372 | = 16 - (-info_ptr->vrsave_save_offset % 16); | |
12373 | else | |
12374 | info_ptr->altivec_padding_size = 0; | |
12375 | ||
12376 | info_ptr->altivec_save_offset | |
12377 | = info_ptr->vrsave_save_offset | |
12378 | - info_ptr->altivec_padding_size | |
12379 | - info_ptr->altivec_size; | |
12380 | ||
12381 | /* Adjust for AltiVec case. */ | |
12382 | info_ptr->ehrd_offset = info_ptr->altivec_save_offset - ehrd_size; | |
12383 | } | |
12384 | else | |
12385 | info_ptr->ehrd_offset = info_ptr->gp_save_offset - ehrd_size; | |
a260abc9 DE |
12386 | info_ptr->cr_save_offset = reg_size; /* first word when 64-bit. */ |
12387 | info_ptr->lr_save_offset = 2*reg_size; | |
24d304eb RK |
12388 | break; |
12389 | ||
12390 | case ABI_V4: | |
b6c9286a MM |
12391 | info_ptr->fp_save_offset = - info_ptr->fp_size; |
12392 | info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size; | |
a7df97e6 | 12393 | info_ptr->cr_save_offset = info_ptr->gp_save_offset - info_ptr->cr_size; |
00b960c7 | 12394 | |
c19de7aa | 12395 | if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0) |
c4ad648e AM |
12396 | { |
12397 | /* Align stack so SPE GPR save area is aligned on a | |
12398 | double-word boundary. */ | |
12399 | if (info_ptr->spe_gp_size != 0) | |
12400 | info_ptr->spe_padding_size | |
12401 | = 8 - (-info_ptr->cr_save_offset % 8); | |
12402 | else | |
12403 | info_ptr->spe_padding_size = 0; | |
12404 | ||
12405 | info_ptr->spe_gp_save_offset | |
12406 | = info_ptr->cr_save_offset | |
12407 | - info_ptr->spe_padding_size | |
12408 | - info_ptr->spe_gp_size; | |
12409 | ||
12410 | /* Adjust for SPE case. */ | |
12411 | info_ptr->toc_save_offset | |
12412 | = info_ptr->spe_gp_save_offset - info_ptr->toc_size; | |
12413 | } | |
a3170dc6 | 12414 | else if (TARGET_ALTIVEC_ABI) |
00b960c7 AH |
12415 | { |
12416 | info_ptr->vrsave_save_offset | |
12417 | = info_ptr->cr_save_offset - info_ptr->vrsave_size; | |
12418 | ||
12419 | /* Align stack so vector save area is on a quadword boundary. */ | |
12420 | if (info_ptr->altivec_size != 0) | |
12421 | info_ptr->altivec_padding_size | |
12422 | = 16 - (-info_ptr->vrsave_save_offset % 16); | |
12423 | else | |
12424 | info_ptr->altivec_padding_size = 0; | |
12425 | ||
12426 | info_ptr->altivec_save_offset | |
12427 | = info_ptr->vrsave_save_offset | |
12428 | - info_ptr->altivec_padding_size | |
12429 | - info_ptr->altivec_size; | |
12430 | ||
12431 | /* Adjust for AltiVec case. */ | |
12432 | info_ptr->toc_save_offset | |
12433 | = info_ptr->altivec_save_offset - info_ptr->toc_size; | |
12434 | } | |
12435 | else | |
12436 | info_ptr->toc_save_offset = info_ptr->cr_save_offset - info_ptr->toc_size; | |
83720594 | 12437 | info_ptr->ehrd_offset = info_ptr->toc_save_offset - ehrd_size; |
b6c9286a MM |
12438 | info_ptr->lr_save_offset = reg_size; |
12439 | break; | |
4697a36c MM |
12440 | } |
12441 | ||
64045029 | 12442 | save_align = (TARGET_ALTIVEC_ABI || DEFAULT_ABI == ABI_DARWIN) ? 16 : 8; |
00b960c7 AH |
12443 | info_ptr->save_size = RS6000_ALIGN (info_ptr->fp_size |
12444 | + info_ptr->gp_size | |
12445 | + info_ptr->altivec_size | |
12446 | + info_ptr->altivec_padding_size | |
a3170dc6 AH |
12447 | + info_ptr->spe_gp_size |
12448 | + info_ptr->spe_padding_size | |
00b960c7 AH |
12449 | + ehrd_size |
12450 | + info_ptr->cr_size | |
12451 | + info_ptr->lr_size | |
12452 | + info_ptr->vrsave_size | |
12453 | + info_ptr->toc_size, | |
64045029 | 12454 | save_align); |
00b960c7 | 12455 | |
44688022 | 12456 | non_fixed_size = (info_ptr->vars_size |
ff381587 | 12457 | + info_ptr->parm_size |
ff381587 | 12458 | + info_ptr->save_size |
44688022 | 12459 | + info_ptr->varargs_size); |
ff381587 | 12460 | |
44688022 AM |
12461 | info_ptr->total_size = RS6000_ALIGN (non_fixed_size + info_ptr->fixed_size, |
12462 | ABI_STACK_BOUNDARY / BITS_PER_UNIT); | |
ff381587 MM |
12463 | |
12464 | /* Determine if we need to allocate any stack frame: | |
12465 | ||
a4f6c312 SS |
12466 | For AIX we need to push the stack if a frame pointer is needed |
12467 | (because the stack might be dynamically adjusted), if we are | |
12468 | debugging, if we make calls, or if the sum of fp_save, gp_save, | |
12469 | and local variables are more than the space needed to save all | |
12470 | non-volatile registers: 32-bit: 18*8 + 19*4 = 220 or 64-bit: 18*8 | |
12471 | + 18*8 = 288 (GPR13 reserved). | |
ff381587 | 12472 | |
a4f6c312 SS |
12473 | For V.4 we don't have the stack cushion that AIX uses, but assume |
12474 | that the debugger can handle stackless frames. */ | |
ff381587 MM |
12475 | |
12476 | if (info_ptr->calls_p) | |
12477 | info_ptr->push_p = 1; | |
12478 | ||
178274da | 12479 | else if (DEFAULT_ABI == ABI_V4) |
44688022 | 12480 | info_ptr->push_p = non_fixed_size != 0; |
ff381587 | 12481 | |
178274da AM |
12482 | else if (frame_pointer_needed) |
12483 | info_ptr->push_p = 1; | |
12484 | ||
12485 | else if (TARGET_XCOFF && write_symbols != NO_DEBUG) | |
12486 | info_ptr->push_p = 1; | |
12487 | ||
ff381587 | 12488 | else |
44688022 | 12489 | info_ptr->push_p = non_fixed_size > (TARGET_32BIT ? 220 : 288); |
ff381587 | 12490 | |
a4f6c312 | 12491 | /* Zero offsets if we're not saving those registers. */ |
8dda1a21 | 12492 | if (info_ptr->fp_size == 0) |
4697a36c MM |
12493 | info_ptr->fp_save_offset = 0; |
12494 | ||
8dda1a21 | 12495 | if (info_ptr->gp_size == 0) |
4697a36c MM |
12496 | info_ptr->gp_save_offset = 0; |
12497 | ||
00b960c7 AH |
12498 | if (! TARGET_ALTIVEC_ABI || info_ptr->altivec_size == 0) |
12499 | info_ptr->altivec_save_offset = 0; | |
12500 | ||
12501 | if (! TARGET_ALTIVEC_ABI || info_ptr->vrsave_mask == 0) | |
12502 | info_ptr->vrsave_save_offset = 0; | |
12503 | ||
c19de7aa AH |
12504 | if (! TARGET_SPE_ABI |
12505 | || info_ptr->spe_64bit_regs_used == 0 | |
12506 | || info_ptr->spe_gp_size == 0) | |
a3170dc6 AH |
12507 | info_ptr->spe_gp_save_offset = 0; |
12508 | ||
c81fc13e | 12509 | if (! info_ptr->lr_save_p) |
4697a36c MM |
12510 | info_ptr->lr_save_offset = 0; |
12511 | ||
c81fc13e | 12512 | if (! info_ptr->cr_save_p) |
4697a36c MM |
12513 | info_ptr->cr_save_offset = 0; |
12514 | ||
c81fc13e | 12515 | if (! info_ptr->toc_save_p) |
b6c9286a MM |
12516 | info_ptr->toc_save_offset = 0; |
12517 | ||
4697a36c MM |
12518 | return info_ptr; |
12519 | } | |
12520 | ||
c19de7aa AH |
12521 | /* Return true if the current function uses any GPRs in 64-bit SIMD |
12522 | mode. */ | |
12523 | ||
12524 | static bool | |
863d938c | 12525 | spe_func_has_64bit_regs_p (void) |
c19de7aa AH |
12526 | { |
12527 | rtx insns, insn; | |
12528 | ||
12529 | /* Functions that save and restore all the call-saved registers will | |
12530 | need to save/restore the registers in 64-bits. */ | |
12531 | if (current_function_calls_eh_return | |
12532 | || current_function_calls_setjmp | |
12533 | || current_function_has_nonlocal_goto) | |
12534 | return true; | |
12535 | ||
12536 | insns = get_insns (); | |
12537 | ||
12538 | for (insn = NEXT_INSN (insns); insn != NULL_RTX; insn = NEXT_INSN (insn)) | |
12539 | { | |
12540 | if (INSN_P (insn)) | |
12541 | { | |
12542 | rtx i; | |
12543 | ||
12544 | i = PATTERN (insn); | |
12545 | if (GET_CODE (i) == SET | |
12546 | && SPE_VECTOR_MODE (GET_MODE (SET_SRC (i)))) | |
12547 | return true; | |
12548 | } | |
12549 | } | |
12550 | ||
12551 | return false; | |
12552 | } | |
12553 | ||
d1d0c603 | 12554 | static void |
a2369ed3 | 12555 | debug_stack_info (rs6000_stack_t *info) |
9878760c | 12556 | { |
d330fd93 | 12557 | const char *abi_string; |
24d304eb | 12558 | |
c81fc13e | 12559 | if (! info) |
4697a36c MM |
12560 | info = rs6000_stack_info (); |
12561 | ||
12562 | fprintf (stderr, "\nStack information for function %s:\n", | |
12563 | ((current_function_decl && DECL_NAME (current_function_decl)) | |
12564 | ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl)) | |
12565 | : "<unknown>")); | |
12566 | ||
24d304eb RK |
12567 | switch (info->abi) |
12568 | { | |
b6c9286a MM |
12569 | default: abi_string = "Unknown"; break; |
12570 | case ABI_NONE: abi_string = "NONE"; break; | |
50d440bc | 12571 | case ABI_AIX: abi_string = "AIX"; break; |
ee890fe2 | 12572 | case ABI_DARWIN: abi_string = "Darwin"; break; |
b6c9286a | 12573 | case ABI_V4: abi_string = "V.4"; break; |
24d304eb RK |
12574 | } |
12575 | ||
12576 | fprintf (stderr, "\tABI = %5s\n", abi_string); | |
12577 | ||
00b960c7 AH |
12578 | if (TARGET_ALTIVEC_ABI) |
12579 | fprintf (stderr, "\tALTIVEC ABI extensions enabled.\n"); | |
12580 | ||
a3170dc6 AH |
12581 | if (TARGET_SPE_ABI) |
12582 | fprintf (stderr, "\tSPE ABI extensions enabled.\n"); | |
12583 | ||
4697a36c MM |
12584 | if (info->first_gp_reg_save != 32) |
12585 | fprintf (stderr, "\tfirst_gp_reg_save = %5d\n", info->first_gp_reg_save); | |
12586 | ||
12587 | if (info->first_fp_reg_save != 64) | |
12588 | fprintf (stderr, "\tfirst_fp_reg_save = %5d\n", info->first_fp_reg_save); | |
9878760c | 12589 | |
00b960c7 AH |
12590 | if (info->first_altivec_reg_save <= LAST_ALTIVEC_REGNO) |
12591 | fprintf (stderr, "\tfirst_altivec_reg_save = %5d\n", | |
12592 | info->first_altivec_reg_save); | |
12593 | ||
4697a36c MM |
12594 | if (info->lr_save_p) |
12595 | fprintf (stderr, "\tlr_save_p = %5d\n", info->lr_save_p); | |
9878760c | 12596 | |
4697a36c MM |
12597 | if (info->cr_save_p) |
12598 | fprintf (stderr, "\tcr_save_p = %5d\n", info->cr_save_p); | |
12599 | ||
b6c9286a MM |
12600 | if (info->toc_save_p) |
12601 | fprintf (stderr, "\ttoc_save_p = %5d\n", info->toc_save_p); | |
12602 | ||
00b960c7 AH |
12603 | if (info->vrsave_mask) |
12604 | fprintf (stderr, "\tvrsave_mask = 0x%x\n", info->vrsave_mask); | |
12605 | ||
4697a36c MM |
12606 | if (info->push_p) |
12607 | fprintf (stderr, "\tpush_p = %5d\n", info->push_p); | |
12608 | ||
12609 | if (info->calls_p) | |
12610 | fprintf (stderr, "\tcalls_p = %5d\n", info->calls_p); | |
12611 | ||
4697a36c MM |
12612 | if (info->gp_save_offset) |
12613 | fprintf (stderr, "\tgp_save_offset = %5d\n", info->gp_save_offset); | |
12614 | ||
12615 | if (info->fp_save_offset) | |
12616 | fprintf (stderr, "\tfp_save_offset = %5d\n", info->fp_save_offset); | |
12617 | ||
00b960c7 AH |
12618 | if (info->altivec_save_offset) |
12619 | fprintf (stderr, "\taltivec_save_offset = %5d\n", | |
12620 | info->altivec_save_offset); | |
12621 | ||
a3170dc6 AH |
12622 | if (info->spe_gp_save_offset) |
12623 | fprintf (stderr, "\tspe_gp_save_offset = %5d\n", | |
12624 | info->spe_gp_save_offset); | |
12625 | ||
00b960c7 AH |
12626 | if (info->vrsave_save_offset) |
12627 | fprintf (stderr, "\tvrsave_save_offset = %5d\n", | |
12628 | info->vrsave_save_offset); | |
12629 | ||
4697a36c MM |
12630 | if (info->lr_save_offset) |
12631 | fprintf (stderr, "\tlr_save_offset = %5d\n", info->lr_save_offset); | |
12632 | ||
12633 | if (info->cr_save_offset) | |
12634 | fprintf (stderr, "\tcr_save_offset = %5d\n", info->cr_save_offset); | |
12635 | ||
b6c9286a MM |
12636 | if (info->toc_save_offset) |
12637 | fprintf (stderr, "\ttoc_save_offset = %5d\n", info->toc_save_offset); | |
12638 | ||
4697a36c MM |
12639 | if (info->varargs_save_offset) |
12640 | fprintf (stderr, "\tvarargs_save_offset = %5d\n", info->varargs_save_offset); | |
12641 | ||
12642 | if (info->total_size) | |
d1d0c603 JJ |
12643 | fprintf (stderr, "\ttotal_size = "HOST_WIDE_INT_PRINT_DEC"\n", |
12644 | info->total_size); | |
4697a36c MM |
12645 | |
12646 | if (info->varargs_size) | |
12647 | fprintf (stderr, "\tvarargs_size = %5d\n", info->varargs_size); | |
12648 | ||
12649 | if (info->vars_size) | |
d1d0c603 JJ |
12650 | fprintf (stderr, "\tvars_size = "HOST_WIDE_INT_PRINT_DEC"\n", |
12651 | info->vars_size); | |
4697a36c MM |
12652 | |
12653 | if (info->parm_size) | |
12654 | fprintf (stderr, "\tparm_size = %5d\n", info->parm_size); | |
12655 | ||
12656 | if (info->fixed_size) | |
12657 | fprintf (stderr, "\tfixed_size = %5d\n", info->fixed_size); | |
12658 | ||
12659 | if (info->gp_size) | |
12660 | fprintf (stderr, "\tgp_size = %5d\n", info->gp_size); | |
12661 | ||
a3170dc6 AH |
12662 | if (info->spe_gp_size) |
12663 | fprintf (stderr, "\tspe_gp_size = %5d\n", info->spe_gp_size); | |
12664 | ||
4697a36c MM |
12665 | if (info->fp_size) |
12666 | fprintf (stderr, "\tfp_size = %5d\n", info->fp_size); | |
12667 | ||
00b960c7 AH |
12668 | if (info->altivec_size) |
12669 | fprintf (stderr, "\taltivec_size = %5d\n", info->altivec_size); | |
12670 | ||
12671 | if (info->vrsave_size) | |
12672 | fprintf (stderr, "\tvrsave_size = %5d\n", info->vrsave_size); | |
12673 | ||
12674 | if (info->altivec_padding_size) | |
12675 | fprintf (stderr, "\taltivec_padding_size= %5d\n", | |
12676 | info->altivec_padding_size); | |
12677 | ||
a3170dc6 AH |
12678 | if (info->spe_padding_size) |
12679 | fprintf (stderr, "\tspe_padding_size = %5d\n", | |
12680 | info->spe_padding_size); | |
12681 | ||
a4f6c312 | 12682 | if (info->lr_size) |
ed947a96 | 12683 | fprintf (stderr, "\tlr_size = %5d\n", info->lr_size); |
b6c9286a | 12684 | |
4697a36c MM |
12685 | if (info->cr_size) |
12686 | fprintf (stderr, "\tcr_size = %5d\n", info->cr_size); | |
12687 | ||
a4f6c312 | 12688 | if (info->toc_size) |
b6c9286a MM |
12689 | fprintf (stderr, "\ttoc_size = %5d\n", info->toc_size); |
12690 | ||
4697a36c MM |
12691 | if (info->save_size) |
12692 | fprintf (stderr, "\tsave_size = %5d\n", info->save_size); | |
12693 | ||
12694 | if (info->reg_size != 4) | |
12695 | fprintf (stderr, "\treg_size = %5d\n", info->reg_size); | |
12696 | ||
12697 | fprintf (stderr, "\n"); | |
9878760c | 12698 | } |
71f123ca FS |
12699 | |
12700 | rtx | |
a2369ed3 | 12701 | rs6000_return_addr (int count, rtx frame) |
71f123ca | 12702 | { |
a4f6c312 SS |
12703 | /* Currently we don't optimize very well between prolog and body |
12704 | code and for PIC code the code can be actually quite bad, so | |
12705 | don't try to be too clever here. */ | |
f1384257 | 12706 | if (count != 0 || (DEFAULT_ABI != ABI_AIX && flag_pic)) |
71f123ca FS |
12707 | { |
12708 | cfun->machine->ra_needs_full_frame = 1; | |
8ac61af7 RK |
12709 | |
12710 | return | |
12711 | gen_rtx_MEM | |
12712 | (Pmode, | |
12713 | memory_address | |
12714 | (Pmode, | |
12715 | plus_constant (copy_to_reg | |
12716 | (gen_rtx_MEM (Pmode, | |
12717 | memory_address (Pmode, frame))), | |
12718 | RETURN_ADDRESS_OFFSET))); | |
71f123ca FS |
12719 | } |
12720 | ||
8c29550d | 12721 | cfun->machine->ra_need_lr = 1; |
9e2f7ec7 | 12722 | return get_hard_reg_initial_val (Pmode, LINK_REGISTER_REGNUM); |
71f123ca FS |
12723 | } |
12724 | ||
5e1bf043 DJ |
12725 | /* Say whether a function is a candidate for sibcall handling or not. |
12726 | We do not allow indirect calls to be optimized into sibling calls. | |
12727 | Also, we can't do it if there are any vector parameters; there's | |
12728 | nowhere to put the VRsave code so it works; note that functions with | |
12729 | vector parameters are required to have a prototype, so the argument | |
12730 | type info must be available here. (The tail recursion case can work | |
12731 | with vector parameters, but there's no way to distinguish here.) */ | |
4977bab6 | 12732 | static bool |
a2369ed3 | 12733 | rs6000_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED) |
5e1bf043 DJ |
12734 | { |
12735 | tree type; | |
4977bab6 | 12736 | if (decl) |
5e1bf043 DJ |
12737 | { |
12738 | if (TARGET_ALTIVEC_VRSAVE) | |
c4ad648e | 12739 | { |
4977bab6 | 12740 | for (type = TYPE_ARG_TYPES (TREE_TYPE (decl)); |
5e1bf043 DJ |
12741 | type; type = TREE_CHAIN (type)) |
12742 | { | |
c15b529f | 12743 | if (TREE_CODE (TREE_VALUE (type)) == VECTOR_TYPE) |
4977bab6 | 12744 | return false; |
5e1bf043 | 12745 | } |
c4ad648e | 12746 | } |
5e1bf043 | 12747 | if (DEFAULT_ABI == ABI_DARWIN |
4977bab6 | 12748 | || (*targetm.binds_local_p) (decl)) |
2bcc50d0 | 12749 | { |
4977bab6 | 12750 | tree attr_list = TYPE_ATTRIBUTES (TREE_TYPE (decl)); |
2bcc50d0 AM |
12751 | |
12752 | if (!lookup_attribute ("longcall", attr_list) | |
12753 | || lookup_attribute ("shortcall", attr_list)) | |
4977bab6 | 12754 | return true; |
2bcc50d0 | 12755 | } |
5e1bf043 | 12756 | } |
4977bab6 | 12757 | return false; |
5e1bf043 DJ |
12758 | } |
12759 | ||
71f123ca | 12760 | static int |
863d938c | 12761 | rs6000_ra_ever_killed (void) |
71f123ca FS |
12762 | { |
12763 | rtx top; | |
5e1bf043 DJ |
12764 | rtx reg; |
12765 | rtx insn; | |
71f123ca | 12766 | |
dd292d0a | 12767 | if (current_function_is_thunk) |
71f123ca | 12768 | return 0; |
eb0424da | 12769 | |
36f7e964 AH |
12770 | /* regs_ever_live has LR marked as used if any sibcalls are present, |
12771 | but this should not force saving and restoring in the | |
12772 | pro/epilogue. Likewise, reg_set_between_p thinks a sibcall | |
a3c9585f | 12773 | clobbers LR, so that is inappropriate. */ |
36f7e964 | 12774 | |
5e1bf043 DJ |
12775 | /* Also, the prologue can generate a store into LR that |
12776 | doesn't really count, like this: | |
36f7e964 | 12777 | |
5e1bf043 DJ |
12778 | move LR->R0 |
12779 | bcl to set PIC register | |
12780 | move LR->R31 | |
12781 | move R0->LR | |
36f7e964 AH |
12782 | |
12783 | When we're called from the epilogue, we need to avoid counting | |
12784 | this as a store. */ | |
f676971a | 12785 | |
71f123ca FS |
12786 | push_topmost_sequence (); |
12787 | top = get_insns (); | |
12788 | pop_topmost_sequence (); | |
5e1bf043 | 12789 | reg = gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM); |
71f123ca | 12790 | |
5e1bf043 DJ |
12791 | for (insn = NEXT_INSN (top); insn != NULL_RTX; insn = NEXT_INSN (insn)) |
12792 | { | |
12793 | if (INSN_P (insn)) | |
12794 | { | |
12795 | if (FIND_REG_INC_NOTE (insn, reg)) | |
12796 | return 1; | |
f676971a | 12797 | else if (GET_CODE (insn) == CALL_INSN |
c15b529f | 12798 | && !SIBLING_CALL_P (insn)) |
5e1bf043 | 12799 | return 1; |
36f7e964 AH |
12800 | else if (set_of (reg, insn) != NULL_RTX |
12801 | && !prologue_epilogue_contains (insn)) | |
5e1bf043 DJ |
12802 | return 1; |
12803 | } | |
12804 | } | |
12805 | return 0; | |
71f123ca | 12806 | } |
4697a36c | 12807 | \f |
8cd8f856 GK |
12808 | /* Add a REG_MAYBE_DEAD note to the insn. */ |
12809 | static void | |
a2369ed3 | 12810 | rs6000_maybe_dead (rtx insn) |
8cd8f856 GK |
12811 | { |
12812 | REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD, | |
12813 | const0_rtx, | |
12814 | REG_NOTES (insn)); | |
12815 | } | |
12816 | ||
9ebbca7d | 12817 | /* Emit instructions needed to load the TOC register. |
c7ca610e | 12818 | This is only needed when TARGET_TOC, TARGET_MINIMAL_TOC, and there is |
9ebbca7d | 12819 | a constant pool; or for SVR4 -fpic. */ |
c7ca610e RK |
12820 | |
12821 | void | |
a2369ed3 | 12822 | rs6000_emit_load_toc_table (int fromprolog) |
c7ca610e | 12823 | { |
027fbf43 | 12824 | rtx dest, insn; |
1db02437 | 12825 | dest = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM); |
c7ca610e | 12826 | |
20b71b17 AM |
12827 | if (TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 1) |
12828 | { | |
12829 | rtx temp = (fromprolog | |
12830 | ? gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM) | |
12831 | : gen_reg_rtx (Pmode)); | |
027fbf43 JJ |
12832 | insn = emit_insn (gen_load_toc_v4_pic_si (temp)); |
12833 | if (fromprolog) | |
12834 | rs6000_maybe_dead (insn); | |
12835 | insn = emit_move_insn (dest, temp); | |
12836 | if (fromprolog) | |
12837 | rs6000_maybe_dead (insn); | |
20b71b17 AM |
12838 | } |
12839 | else if (TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2) | |
12840 | { | |
12841 | char buf[30]; | |
12842 | rtx tempLR = (fromprolog | |
12843 | ? gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM) | |
12844 | : gen_reg_rtx (Pmode)); | |
12845 | rtx temp0 = (fromprolog | |
12846 | ? gen_rtx_REG (Pmode, 0) | |
12847 | : gen_reg_rtx (Pmode)); | |
12848 | rtx symF; | |
12849 | ||
12850 | /* possibly create the toc section */ | |
12851 | if (! toc_initialized) | |
38c1f2d7 | 12852 | { |
20b71b17 AM |
12853 | toc_section (); |
12854 | function_section (current_function_decl); | |
38c1f2d7 | 12855 | } |
9ebbca7d | 12856 | |
20b71b17 AM |
12857 | if (fromprolog) |
12858 | { | |
12859 | rtx symL; | |
38c1f2d7 | 12860 | |
20b71b17 AM |
12861 | ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno); |
12862 | symF = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); | |
9ebbca7d | 12863 | |
20b71b17 AM |
12864 | ASM_GENERATE_INTERNAL_LABEL (buf, "LCL", rs6000_pic_labelno); |
12865 | symL = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); | |
12866 | ||
12867 | rs6000_maybe_dead (emit_insn (gen_load_toc_v4_PIC_1 (tempLR, | |
12868 | symF))); | |
12869 | rs6000_maybe_dead (emit_move_insn (dest, tempLR)); | |
12870 | rs6000_maybe_dead (emit_insn (gen_load_toc_v4_PIC_2 (temp0, dest, | |
12871 | symL, | |
12872 | symF))); | |
9ebbca7d GK |
12873 | } |
12874 | else | |
20b71b17 AM |
12875 | { |
12876 | rtx tocsym; | |
12877 | static int reload_toc_labelno = 0; | |
12878 | ||
12879 | tocsym = gen_rtx_SYMBOL_REF (Pmode, toc_label_name); | |
12880 | ||
12881 | ASM_GENERATE_INTERNAL_LABEL (buf, "LCG", reload_toc_labelno++); | |
12882 | symF = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); | |
12883 | ||
027fbf43 JJ |
12884 | emit_insn (gen_load_toc_v4_PIC_1b (tempLR, symF, tocsym)); |
12885 | emit_move_insn (dest, tempLR); | |
12886 | emit_move_insn (temp0, gen_rtx_MEM (Pmode, dest)); | |
20b71b17 | 12887 | } |
027fbf43 JJ |
12888 | insn = emit_insn (gen_addsi3 (dest, temp0, dest)); |
12889 | if (fromprolog) | |
12890 | rs6000_maybe_dead (insn); | |
9ebbca7d | 12891 | } |
20b71b17 AM |
12892 | else if (TARGET_ELF && !TARGET_AIX && flag_pic == 0 && TARGET_MINIMAL_TOC) |
12893 | { | |
12894 | /* This is for AIX code running in non-PIC ELF32. */ | |
12895 | char buf[30]; | |
12896 | rtx realsym; | |
12897 | ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1); | |
12898 | realsym = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); | |
12899 | ||
027fbf43 JJ |
12900 | insn = emit_insn (gen_elf_high (dest, realsym)); |
12901 | if (fromprolog) | |
12902 | rs6000_maybe_dead (insn); | |
12903 | insn = emit_insn (gen_elf_low (dest, dest, realsym)); | |
12904 | if (fromprolog) | |
12905 | rs6000_maybe_dead (insn); | |
20b71b17 AM |
12906 | } |
12907 | else if (DEFAULT_ABI == ABI_AIX) | |
9ebbca7d GK |
12908 | { |
12909 | if (TARGET_32BIT) | |
027fbf43 | 12910 | insn = emit_insn (gen_load_toc_aix_si (dest)); |
9ebbca7d | 12911 | else |
027fbf43 JJ |
12912 | insn = emit_insn (gen_load_toc_aix_di (dest)); |
12913 | if (fromprolog) | |
12914 | rs6000_maybe_dead (insn); | |
9ebbca7d | 12915 | } |
20b71b17 AM |
12916 | else |
12917 | abort (); | |
9ebbca7d GK |
12918 | } |
12919 | ||
d1d0c603 JJ |
12920 | /* Emit instructions to restore the link register after determining where |
12921 | its value has been stored. */ | |
12922 | ||
12923 | void | |
12924 | rs6000_emit_eh_reg_restore (rtx source, rtx scratch) | |
12925 | { | |
12926 | rs6000_stack_t *info = rs6000_stack_info (); | |
12927 | rtx operands[2]; | |
12928 | ||
12929 | operands[0] = source; | |
12930 | operands[1] = scratch; | |
12931 | ||
12932 | if (info->lr_save_p) | |
12933 | { | |
12934 | rtx frame_rtx = stack_pointer_rtx; | |
12935 | HOST_WIDE_INT sp_offset = 0; | |
12936 | rtx tmp; | |
12937 | ||
12938 | if (frame_pointer_needed | |
12939 | || current_function_calls_alloca | |
12940 | || info->total_size > 32767) | |
12941 | { | |
12942 | emit_move_insn (operands[1], gen_rtx_MEM (Pmode, frame_rtx)); | |
12943 | frame_rtx = operands[1]; | |
12944 | } | |
12945 | else if (info->push_p) | |
12946 | sp_offset = info->total_size; | |
12947 | ||
12948 | tmp = plus_constant (frame_rtx, info->lr_save_offset + sp_offset); | |
12949 | tmp = gen_rtx_MEM (Pmode, tmp); | |
12950 | emit_move_insn (tmp, operands[0]); | |
12951 | } | |
12952 | else | |
12953 | emit_move_insn (gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM), operands[0]); | |
12954 | } | |
12955 | ||
f103e34d GK |
12956 | static GTY(()) int set = -1; |
12957 | ||
f676971a | 12958 | int |
863d938c | 12959 | get_TOC_alias_set (void) |
9ebbca7d | 12960 | { |
f103e34d GK |
12961 | if (set == -1) |
12962 | set = new_alias_set (); | |
12963 | return set; | |
f676971a | 12964 | } |
9ebbca7d | 12965 | |
c1207243 | 12966 | /* This returns nonzero if the current function uses the TOC. This is |
3c9eb5f4 AM |
12967 | determined by the presence of (use (unspec ... UNSPEC_TOC)), which |
12968 | is generated by the ABI_V4 load_toc_* patterns. */ | |
c954844a | 12969 | #if TARGET_ELF |
3c9eb5f4 | 12970 | static int |
f676971a | 12971 | uses_TOC (void) |
9ebbca7d | 12972 | { |
c4501e62 | 12973 | rtx insn; |
38c1f2d7 | 12974 | |
c4501e62 JJ |
12975 | for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) |
12976 | if (INSN_P (insn)) | |
12977 | { | |
12978 | rtx pat = PATTERN (insn); | |
12979 | int i; | |
9ebbca7d | 12980 | |
f676971a | 12981 | if (GET_CODE (pat) == PARALLEL) |
c4501e62 JJ |
12982 | for (i = 0; i < XVECLEN (pat, 0); i++) |
12983 | { | |
12984 | rtx sub = XVECEXP (pat, 0, i); | |
12985 | if (GET_CODE (sub) == USE) | |
12986 | { | |
12987 | sub = XEXP (sub, 0); | |
12988 | if (GET_CODE (sub) == UNSPEC | |
12989 | && XINT (sub, 1) == UNSPEC_TOC) | |
12990 | return 1; | |
12991 | } | |
12992 | } | |
12993 | } | |
12994 | return 0; | |
9ebbca7d | 12995 | } |
c954844a | 12996 | #endif |
38c1f2d7 | 12997 | |
9ebbca7d | 12998 | rtx |
f676971a | 12999 | create_TOC_reference (rtx symbol) |
9ebbca7d | 13000 | { |
f676971a | 13001 | return gen_rtx_PLUS (Pmode, |
a8a05998 | 13002 | gen_rtx_REG (Pmode, TOC_REGISTER), |
f676971a EC |
13003 | gen_rtx_CONST (Pmode, |
13004 | gen_rtx_MINUS (Pmode, symbol, | |
b999aaeb | 13005 | gen_rtx_SYMBOL_REF (Pmode, toc_label_name)))); |
9ebbca7d | 13006 | } |
38c1f2d7 | 13007 | |
fc4767bb JJ |
13008 | /* If _Unwind_* has been called from within the same module, |
13009 | toc register is not guaranteed to be saved to 40(1) on function | |
13010 | entry. Save it there in that case. */ | |
c7ca610e | 13011 | |
9ebbca7d | 13012 | void |
863d938c | 13013 | rs6000_aix_emit_builtin_unwind_init (void) |
9ebbca7d GK |
13014 | { |
13015 | rtx mem; | |
13016 | rtx stack_top = gen_reg_rtx (Pmode); | |
13017 | rtx opcode_addr = gen_reg_rtx (Pmode); | |
fc4767bb JJ |
13018 | rtx opcode = gen_reg_rtx (SImode); |
13019 | rtx tocompare = gen_reg_rtx (SImode); | |
13020 | rtx no_toc_save_needed = gen_label_rtx (); | |
9ebbca7d GK |
13021 | |
13022 | mem = gen_rtx_MEM (Pmode, hard_frame_pointer_rtx); | |
13023 | emit_move_insn (stack_top, mem); | |
13024 | ||
fc4767bb JJ |
13025 | mem = gen_rtx_MEM (Pmode, |
13026 | gen_rtx_PLUS (Pmode, stack_top, | |
9ebbca7d GK |
13027 | GEN_INT (2 * GET_MODE_SIZE (Pmode)))); |
13028 | emit_move_insn (opcode_addr, mem); | |
fc4767bb JJ |
13029 | emit_move_insn (opcode, gen_rtx_MEM (SImode, opcode_addr)); |
13030 | emit_move_insn (tocompare, gen_int_mode (TARGET_32BIT ? 0x80410014 | |
2496c7bd | 13031 | : 0xE8410028, SImode)); |
9ebbca7d | 13032 | |
fc4767bb | 13033 | do_compare_rtx_and_jump (opcode, tocompare, EQ, 1, |
06f4e019 | 13034 | SImode, NULL_RTX, NULL_RTX, |
fc4767bb | 13035 | no_toc_save_needed); |
9ebbca7d | 13036 | |
fc4767bb JJ |
13037 | mem = gen_rtx_MEM (Pmode, |
13038 | gen_rtx_PLUS (Pmode, stack_top, | |
13039 | GEN_INT (5 * GET_MODE_SIZE (Pmode)))); | |
13040 | emit_move_insn (mem, gen_rtx_REG (Pmode, 2)); | |
13041 | emit_label (no_toc_save_needed); | |
9ebbca7d | 13042 | } |
38c1f2d7 | 13043 | \f |
ba4828e0 RK |
13044 | /* This ties together stack memory (MEM with an alias set of |
13045 | rs6000_sr_alias_set) and the change to the stack pointer. */ | |
13046 | ||
9ebbca7d | 13047 | static void |
863d938c | 13048 | rs6000_emit_stack_tie (void) |
9ebbca7d | 13049 | { |
ba4828e0 RK |
13050 | rtx mem = gen_rtx_MEM (BLKmode, gen_rtx_REG (Pmode, STACK_POINTER_REGNUM)); |
13051 | ||
13052 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
9ebbca7d GK |
13053 | emit_insn (gen_stack_tie (mem)); |
13054 | } | |
38c1f2d7 | 13055 | |
9ebbca7d GK |
13056 | /* Emit the correct code for allocating stack space, as insns. |
13057 | If COPY_R12, make sure a copy of the old frame is left in r12. | |
13058 | The generated code may use hard register 0 as a temporary. */ | |
13059 | ||
13060 | static void | |
a2369ed3 | 13061 | rs6000_emit_allocate_stack (HOST_WIDE_INT size, int copy_r12) |
38c1f2d7 | 13062 | { |
9ebbca7d GK |
13063 | rtx insn; |
13064 | rtx stack_reg = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM); | |
13065 | rtx tmp_reg = gen_rtx_REG (Pmode, 0); | |
13066 | rtx todec = GEN_INT (-size); | |
a157febd GK |
13067 | |
13068 | if (current_function_limit_stack) | |
13069 | { | |
13070 | if (REG_P (stack_limit_rtx) | |
f676971a | 13071 | && REGNO (stack_limit_rtx) > 1 |
a157febd GK |
13072 | && REGNO (stack_limit_rtx) <= 31) |
13073 | { | |
5b71a4e7 | 13074 | emit_insn (TARGET_32BIT |
9ebbca7d GK |
13075 | ? gen_addsi3 (tmp_reg, |
13076 | stack_limit_rtx, | |
13077 | GEN_INT (size)) | |
13078 | : gen_adddi3 (tmp_reg, | |
13079 | stack_limit_rtx, | |
13080 | GEN_INT (size))); | |
5b71a4e7 | 13081 | |
9ebbca7d GK |
13082 | emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg, |
13083 | const0_rtx)); | |
a157febd GK |
13084 | } |
13085 | else if (GET_CODE (stack_limit_rtx) == SYMBOL_REF | |
9ebbca7d | 13086 | && TARGET_32BIT |
f607bc57 | 13087 | && DEFAULT_ABI == ABI_V4) |
a157febd | 13088 | { |
9ebbca7d | 13089 | rtx toload = gen_rtx_CONST (VOIDmode, |
f676971a EC |
13090 | gen_rtx_PLUS (Pmode, |
13091 | stack_limit_rtx, | |
9ebbca7d | 13092 | GEN_INT (size))); |
5b71a4e7 | 13093 | |
9ebbca7d GK |
13094 | emit_insn (gen_elf_high (tmp_reg, toload)); |
13095 | emit_insn (gen_elf_low (tmp_reg, tmp_reg, toload)); | |
13096 | emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg, | |
13097 | const0_rtx)); | |
a157febd GK |
13098 | } |
13099 | else | |
13100 | warning ("stack limit expression is not supported"); | |
13101 | } | |
13102 | ||
9ebbca7d GK |
13103 | if (copy_r12 || ! TARGET_UPDATE) |
13104 | emit_move_insn (gen_rtx_REG (Pmode, 12), stack_reg); | |
13105 | ||
38c1f2d7 MM |
13106 | if (TARGET_UPDATE) |
13107 | { | |
9ebbca7d | 13108 | if (size > 32767) |
38c1f2d7 | 13109 | { |
9ebbca7d GK |
13110 | /* Need a note here so that try_split doesn't get confused. */ |
13111 | if (get_last_insn() == NULL_RTX) | |
2e040219 | 13112 | emit_note (NOTE_INSN_DELETED); |
9ebbca7d GK |
13113 | insn = emit_move_insn (tmp_reg, todec); |
13114 | try_split (PATTERN (insn), insn, 0); | |
13115 | todec = tmp_reg; | |
38c1f2d7 | 13116 | } |
5b71a4e7 DE |
13117 | |
13118 | insn = emit_insn (TARGET_32BIT | |
13119 | ? gen_movsi_update (stack_reg, stack_reg, | |
13120 | todec, stack_reg) | |
c4ad648e | 13121 | : gen_movdi_di_update (stack_reg, stack_reg, |
9ebbca7d | 13122 | todec, stack_reg)); |
38c1f2d7 MM |
13123 | } |
13124 | else | |
13125 | { | |
5b71a4e7 DE |
13126 | insn = emit_insn (TARGET_32BIT |
13127 | ? gen_addsi3 (stack_reg, stack_reg, todec) | |
13128 | : gen_adddi3 (stack_reg, stack_reg, todec)); | |
9ebbca7d GK |
13129 | emit_move_insn (gen_rtx_MEM (Pmode, stack_reg), |
13130 | gen_rtx_REG (Pmode, 12)); | |
13131 | } | |
f676971a | 13132 | |
9ebbca7d | 13133 | RTX_FRAME_RELATED_P (insn) = 1; |
f676971a | 13134 | REG_NOTES (insn) = |
9ebbca7d | 13135 | gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, |
f676971a | 13136 | gen_rtx_SET (VOIDmode, stack_reg, |
9ebbca7d GK |
13137 | gen_rtx_PLUS (Pmode, stack_reg, |
13138 | GEN_INT (-size))), | |
13139 | REG_NOTES (insn)); | |
13140 | } | |
13141 | ||
a4f6c312 SS |
13142 | /* Add to 'insn' a note which is PATTERN (INSN) but with REG replaced |
13143 | with (plus:P (reg 1) VAL), and with REG2 replaced with RREG if REG2 | |
13144 | is not NULL. It would be nice if dwarf2out_frame_debug_expr could | |
13145 | deduce these equivalences by itself so it wasn't necessary to hold | |
13146 | its hand so much. */ | |
9ebbca7d GK |
13147 | |
13148 | static void | |
f676971a | 13149 | rs6000_frame_related (rtx insn, rtx reg, HOST_WIDE_INT val, |
a2369ed3 | 13150 | rtx reg2, rtx rreg) |
9ebbca7d GK |
13151 | { |
13152 | rtx real, temp; | |
13153 | ||
e56c4463 JL |
13154 | /* copy_rtx will not make unique copies of registers, so we need to |
13155 | ensure we don't have unwanted sharing here. */ | |
13156 | if (reg == reg2) | |
13157 | reg = gen_raw_REG (GET_MODE (reg), REGNO (reg)); | |
13158 | ||
13159 | if (reg == rreg) | |
13160 | reg = gen_raw_REG (GET_MODE (reg), REGNO (reg)); | |
13161 | ||
9ebbca7d GK |
13162 | real = copy_rtx (PATTERN (insn)); |
13163 | ||
89e7058f AH |
13164 | if (reg2 != NULL_RTX) |
13165 | real = replace_rtx (real, reg2, rreg); | |
f676971a EC |
13166 | |
13167 | real = replace_rtx (real, reg, | |
9ebbca7d GK |
13168 | gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode, |
13169 | STACK_POINTER_REGNUM), | |
13170 | GEN_INT (val))); | |
f676971a | 13171 | |
9ebbca7d GK |
13172 | /* We expect that 'real' is either a SET or a PARALLEL containing |
13173 | SETs (and possibly other stuff). In a PARALLEL, all the SETs | |
13174 | are important so they all have to be marked RTX_FRAME_RELATED_P. */ | |
13175 | ||
13176 | if (GET_CODE (real) == SET) | |
13177 | { | |
13178 | rtx set = real; | |
f676971a | 13179 | |
9ebbca7d GK |
13180 | temp = simplify_rtx (SET_SRC (set)); |
13181 | if (temp) | |
13182 | SET_SRC (set) = temp; | |
13183 | temp = simplify_rtx (SET_DEST (set)); | |
13184 | if (temp) | |
13185 | SET_DEST (set) = temp; | |
13186 | if (GET_CODE (SET_DEST (set)) == MEM) | |
38c1f2d7 | 13187 | { |
9ebbca7d GK |
13188 | temp = simplify_rtx (XEXP (SET_DEST (set), 0)); |
13189 | if (temp) | |
13190 | XEXP (SET_DEST (set), 0) = temp; | |
38c1f2d7 | 13191 | } |
38c1f2d7 | 13192 | } |
9ebbca7d GK |
13193 | else if (GET_CODE (real) == PARALLEL) |
13194 | { | |
13195 | int i; | |
13196 | for (i = 0; i < XVECLEN (real, 0); i++) | |
13197 | if (GET_CODE (XVECEXP (real, 0, i)) == SET) | |
13198 | { | |
13199 | rtx set = XVECEXP (real, 0, i); | |
f676971a | 13200 | |
9ebbca7d GK |
13201 | temp = simplify_rtx (SET_SRC (set)); |
13202 | if (temp) | |
13203 | SET_SRC (set) = temp; | |
13204 | temp = simplify_rtx (SET_DEST (set)); | |
13205 | if (temp) | |
13206 | SET_DEST (set) = temp; | |
13207 | if (GET_CODE (SET_DEST (set)) == MEM) | |
13208 | { | |
13209 | temp = simplify_rtx (XEXP (SET_DEST (set), 0)); | |
13210 | if (temp) | |
13211 | XEXP (SET_DEST (set), 0) = temp; | |
13212 | } | |
13213 | RTX_FRAME_RELATED_P (set) = 1; | |
13214 | } | |
13215 | } | |
13216 | else | |
a4f6c312 | 13217 | abort (); |
c19de7aa AH |
13218 | |
13219 | if (TARGET_SPE) | |
13220 | real = spe_synthesize_frame_save (real); | |
13221 | ||
9ebbca7d GK |
13222 | RTX_FRAME_RELATED_P (insn) = 1; |
13223 | REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, | |
13224 | real, | |
13225 | REG_NOTES (insn)); | |
38c1f2d7 MM |
13226 | } |
13227 | ||
c19de7aa AH |
13228 | /* Given an SPE frame note, return a PARALLEL of SETs with the |
13229 | original note, plus a synthetic register save. */ | |
13230 | ||
13231 | static rtx | |
a2369ed3 | 13232 | spe_synthesize_frame_save (rtx real) |
c19de7aa AH |
13233 | { |
13234 | rtx synth, offset, reg, real2; | |
13235 | ||
13236 | if (GET_CODE (real) != SET | |
13237 | || GET_MODE (SET_SRC (real)) != V2SImode) | |
13238 | return real; | |
13239 | ||
13240 | /* For the SPE, registers saved in 64-bits, get a PARALLEL for their | |
13241 | frame related note. The parallel contains a set of the register | |
41f3a930 | 13242 | being saved, and another set to a synthetic register (n+1200). |
c19de7aa AH |
13243 | This is so we can differentiate between 64-bit and 32-bit saves. |
13244 | Words cannot describe this nastiness. */ | |
13245 | ||
13246 | if (GET_CODE (SET_DEST (real)) != MEM | |
13247 | || GET_CODE (XEXP (SET_DEST (real), 0)) != PLUS | |
13248 | || GET_CODE (SET_SRC (real)) != REG) | |
13249 | abort (); | |
13250 | ||
13251 | /* Transform: | |
13252 | (set (mem (plus (reg x) (const y))) | |
13253 | (reg z)) | |
13254 | into: | |
13255 | (set (mem (plus (reg x) (const y+4))) | |
41f3a930 | 13256 | (reg z+1200)) |
c19de7aa AH |
13257 | */ |
13258 | ||
13259 | real2 = copy_rtx (real); | |
13260 | PUT_MODE (SET_DEST (real2), SImode); | |
13261 | reg = SET_SRC (real2); | |
13262 | real2 = replace_rtx (real2, reg, gen_rtx_REG (SImode, REGNO (reg))); | |
13263 | synth = copy_rtx (real2); | |
13264 | ||
13265 | if (BYTES_BIG_ENDIAN) | |
13266 | { | |
13267 | offset = XEXP (XEXP (SET_DEST (real2), 0), 1); | |
13268 | real2 = replace_rtx (real2, offset, GEN_INT (INTVAL (offset) + 4)); | |
13269 | } | |
13270 | ||
13271 | reg = SET_SRC (synth); | |
41f3a930 | 13272 | |
c19de7aa | 13273 | synth = replace_rtx (synth, reg, |
41f3a930 | 13274 | gen_rtx_REG (SImode, REGNO (reg) + 1200)); |
c19de7aa AH |
13275 | |
13276 | offset = XEXP (XEXP (SET_DEST (synth), 0), 1); | |
13277 | synth = replace_rtx (synth, offset, | |
13278 | GEN_INT (INTVAL (offset) | |
13279 | + (BYTES_BIG_ENDIAN ? 0 : 4))); | |
13280 | ||
13281 | RTX_FRAME_RELATED_P (synth) = 1; | |
13282 | RTX_FRAME_RELATED_P (real2) = 1; | |
13283 | if (BYTES_BIG_ENDIAN) | |
13284 | real = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, synth, real2)); | |
13285 | else | |
13286 | real = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, real2, synth)); | |
13287 | ||
13288 | return real; | |
13289 | } | |
13290 | ||
00b960c7 AH |
13291 | /* Returns an insn that has a vrsave set operation with the |
13292 | appropriate CLOBBERs. */ | |
13293 | ||
13294 | static rtx | |
a2369ed3 | 13295 | generate_set_vrsave (rtx reg, rs6000_stack_t *info, int epiloguep) |
00b960c7 AH |
13296 | { |
13297 | int nclobs, i; | |
13298 | rtx insn, clobs[TOTAL_ALTIVEC_REGS + 1]; | |
a004eb82 | 13299 | rtx vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO); |
00b960c7 | 13300 | |
a004eb82 AH |
13301 | clobs[0] |
13302 | = gen_rtx_SET (VOIDmode, | |
13303 | vrsave, | |
13304 | gen_rtx_UNSPEC_VOLATILE (SImode, | |
13305 | gen_rtvec (2, reg, vrsave), | |
13306 | 30)); | |
00b960c7 AH |
13307 | |
13308 | nclobs = 1; | |
13309 | ||
9aa86737 AH |
13310 | /* We need to clobber the registers in the mask so the scheduler |
13311 | does not move sets to VRSAVE before sets of AltiVec registers. | |
13312 | ||
13313 | However, if the function receives nonlocal gotos, reload will set | |
13314 | all call saved registers live. We will end up with: | |
13315 | ||
13316 | (set (reg 999) (mem)) | |
13317 | (parallel [ (set (reg vrsave) (unspec blah)) | |
13318 | (clobber (reg 999))]) | |
13319 | ||
13320 | The clobber will cause the store into reg 999 to be dead, and | |
13321 | flow will attempt to delete an epilogue insn. In this case, we | |
13322 | need an unspec use/set of the register. */ | |
00b960c7 AH |
13323 | |
13324 | for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i) | |
44688022 | 13325 | if (info->vrsave_mask & ALTIVEC_REG_BIT (i)) |
9aa86737 AH |
13326 | { |
13327 | if (!epiloguep || call_used_regs [i]) | |
13328 | clobs[nclobs++] = gen_rtx_CLOBBER (VOIDmode, | |
13329 | gen_rtx_REG (V4SImode, i)); | |
13330 | else | |
13331 | { | |
13332 | rtx reg = gen_rtx_REG (V4SImode, i); | |
9aa86737 AH |
13333 | |
13334 | clobs[nclobs++] | |
a004eb82 AH |
13335 | = gen_rtx_SET (VOIDmode, |
13336 | reg, | |
13337 | gen_rtx_UNSPEC (V4SImode, | |
13338 | gen_rtvec (1, reg), 27)); | |
9aa86737 AH |
13339 | } |
13340 | } | |
00b960c7 AH |
13341 | |
13342 | insn = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (nclobs)); | |
13343 | ||
13344 | for (i = 0; i < nclobs; ++i) | |
13345 | XVECEXP (insn, 0, i) = clobs[i]; | |
13346 | ||
13347 | return insn; | |
13348 | } | |
13349 | ||
89e7058f AH |
13350 | /* Save a register into the frame, and emit RTX_FRAME_RELATED_P notes. |
13351 | Save REGNO into [FRAME_REG + OFFSET] in mode MODE. */ | |
13352 | ||
13353 | static void | |
f676971a | 13354 | emit_frame_save (rtx frame_reg, rtx frame_ptr, enum machine_mode mode, |
d1d0c603 | 13355 | unsigned int regno, int offset, HOST_WIDE_INT total_size) |
89e7058f AH |
13356 | { |
13357 | rtx reg, offset_rtx, insn, mem, addr, int_rtx; | |
13358 | rtx replacea, replaceb; | |
13359 | ||
13360 | int_rtx = GEN_INT (offset); | |
13361 | ||
13362 | /* Some cases that need register indexed addressing. */ | |
13363 | if ((TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode)) | |
4d4cbc0e | 13364 | || (TARGET_E500_DOUBLE && mode == DFmode) |
a3170dc6 AH |
13365 | || (TARGET_SPE_ABI |
13366 | && SPE_VECTOR_MODE (mode) | |
13367 | && !SPE_CONST_OFFSET_OK (offset))) | |
89e7058f AH |
13368 | { |
13369 | /* Whomever calls us must make sure r11 is available in the | |
c4ad648e | 13370 | flow path of instructions in the prologue. */ |
89e7058f AH |
13371 | offset_rtx = gen_rtx_REG (Pmode, 11); |
13372 | emit_move_insn (offset_rtx, int_rtx); | |
13373 | ||
13374 | replacea = offset_rtx; | |
13375 | replaceb = int_rtx; | |
13376 | } | |
13377 | else | |
13378 | { | |
13379 | offset_rtx = int_rtx; | |
13380 | replacea = NULL_RTX; | |
13381 | replaceb = NULL_RTX; | |
13382 | } | |
13383 | ||
13384 | reg = gen_rtx_REG (mode, regno); | |
13385 | addr = gen_rtx_PLUS (Pmode, frame_reg, offset_rtx); | |
13386 | mem = gen_rtx_MEM (mode, addr); | |
13387 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
13388 | ||
13389 | insn = emit_move_insn (mem, reg); | |
13390 | ||
13391 | rs6000_frame_related (insn, frame_ptr, total_size, replacea, replaceb); | |
13392 | } | |
13393 | ||
a3170dc6 AH |
13394 | /* Emit an offset memory reference suitable for a frame store, while |
13395 | converting to a valid addressing mode. */ | |
13396 | ||
13397 | static rtx | |
a2369ed3 | 13398 | gen_frame_mem_offset (enum machine_mode mode, rtx reg, int offset) |
a3170dc6 AH |
13399 | { |
13400 | rtx int_rtx, offset_rtx; | |
13401 | ||
13402 | int_rtx = GEN_INT (offset); | |
13403 | ||
4d4cbc0e AH |
13404 | if ((TARGET_SPE_ABI && SPE_VECTOR_MODE (mode)) |
13405 | || (TARGET_E500_DOUBLE && mode == DFmode)) | |
a3170dc6 AH |
13406 | { |
13407 | offset_rtx = gen_rtx_REG (Pmode, FIXED_SCRATCH); | |
13408 | emit_move_insn (offset_rtx, int_rtx); | |
13409 | } | |
13410 | else | |
13411 | offset_rtx = int_rtx; | |
13412 | ||
13413 | return gen_rtx_MEM (mode, gen_rtx_PLUS (Pmode, reg, offset_rtx)); | |
13414 | } | |
13415 | ||
699c914a MS |
13416 | #ifndef TARGET_FIX_AND_CONTINUE |
13417 | #define TARGET_FIX_AND_CONTINUE 0 | |
13418 | #endif | |
13419 | ||
9ebbca7d GK |
13420 | /* Emit function prologue as insns. */ |
13421 | ||
9878760c | 13422 | void |
863d938c | 13423 | rs6000_emit_prologue (void) |
9878760c | 13424 | { |
4697a36c | 13425 | rs6000_stack_t *info = rs6000_stack_info (); |
0e67400a | 13426 | enum machine_mode reg_mode = Pmode; |
327e5343 | 13427 | int reg_size = TARGET_32BIT ? 4 : 8; |
9ebbca7d GK |
13428 | rtx sp_reg_rtx = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM); |
13429 | rtx frame_ptr_rtx = gen_rtx_REG (Pmode, 12); | |
13430 | rtx frame_reg_rtx = sp_reg_rtx; | |
b78d48dd | 13431 | rtx cr_save_rtx = NULL_RTX; |
9ebbca7d GK |
13432 | rtx insn; |
13433 | int saving_FPRs_inline; | |
13434 | int using_store_multiple; | |
13435 | HOST_WIDE_INT sp_offset = 0; | |
f676971a | 13436 | |
699c914a MS |
13437 | if (TARGET_FIX_AND_CONTINUE) |
13438 | { | |
13439 | /* gdb on darwin arranges to forward a function from the old | |
13440 | address by modifying the first 4 instructions of the function | |
13441 | to branch to the overriding function. This is necessary to | |
13442 | permit function pointers that point to the old function to | |
13443 | actually forward to the new function. */ | |
13444 | emit_insn (gen_nop ()); | |
13445 | emit_insn (gen_nop ()); | |
13446 | emit_insn (gen_nop ()); | |
13447 | emit_insn (gen_nop ()); | |
13448 | } | |
13449 | ||
13450 | if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0) | |
13451 | { | |
13452 | reg_mode = V2SImode; | |
13453 | reg_size = 8; | |
13454 | } | |
a3170dc6 | 13455 | |
9ebbca7d | 13456 | using_store_multiple = (TARGET_MULTIPLE && ! TARGET_POWERPC64 |
c19de7aa AH |
13457 | && (!TARGET_SPE_ABI |
13458 | || info->spe_64bit_regs_used == 0) | |
9ebbca7d GK |
13459 | && info->first_gp_reg_save < 31); |
13460 | saving_FPRs_inline = (info->first_fp_reg_save == 64 | |
8c29550d | 13461 | || FP_SAVE_INLINE (info->first_fp_reg_save) |
acd0b319 | 13462 | || current_function_calls_eh_return |
8c29550d | 13463 | || cfun->machine->ra_need_lr); |
9ebbca7d GK |
13464 | |
13465 | /* For V.4, update stack before we do any saving and set back pointer. */ | |
fc4767bb | 13466 | if (info->push_p |
acd0b319 AM |
13467 | && (DEFAULT_ABI == ABI_V4 |
13468 | || current_function_calls_eh_return)) | |
9ebbca7d GK |
13469 | { |
13470 | if (info->total_size < 32767) | |
13471 | sp_offset = info->total_size; | |
13472 | else | |
13473 | frame_reg_rtx = frame_ptr_rtx; | |
f676971a | 13474 | rs6000_emit_allocate_stack (info->total_size, |
9ebbca7d GK |
13475 | (frame_reg_rtx != sp_reg_rtx |
13476 | && (info->cr_save_p | |
13477 | || info->lr_save_p | |
13478 | || info->first_fp_reg_save < 64 | |
13479 | || info->first_gp_reg_save < 32 | |
13480 | ))); | |
13481 | if (frame_reg_rtx != sp_reg_rtx) | |
13482 | rs6000_emit_stack_tie (); | |
13483 | } | |
13484 | ||
d62294f5 FJ |
13485 | /* Handle world saves specially here. */ |
13486 | if (info->world_save_p) | |
13487 | { | |
13488 | int i, j, sz; | |
13489 | rtx treg; | |
13490 | rtvec p; | |
13491 | ||
13492 | /* save_world expects lr in r0. */ | |
13493 | if (info->lr_save_p) | |
c4ad648e AM |
13494 | { |
13495 | insn = emit_move_insn (gen_rtx_REG (Pmode, 0), | |
13496 | gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)); | |
13497 | RTX_FRAME_RELATED_P (insn) = 1; | |
13498 | } | |
d62294f5 FJ |
13499 | |
13500 | /* The SAVE_WORLD and RESTORE_WORLD routines make a number of | |
c4ad648e AM |
13501 | assumptions about the offsets of various bits of the stack |
13502 | frame. Abort if things aren't what they should be. */ | |
d62294f5 | 13503 | if (info->gp_save_offset != -220 |
c4ad648e AM |
13504 | || info->fp_save_offset != -144 |
13505 | || info->lr_save_offset != 8 | |
13506 | || info->cr_save_offset != 4 | |
13507 | || !info->push_p | |
13508 | || !info->lr_save_p | |
13509 | || (current_function_calls_eh_return && info->ehrd_offset != -432) | |
13510 | || (info->vrsave_save_offset != -224 | |
13511 | || info->altivec_save_offset != (-224 -16 -192))) | |
13512 | abort (); | |
d62294f5 FJ |
13513 | |
13514 | treg = gen_rtx_REG (SImode, 11); | |
13515 | emit_move_insn (treg, GEN_INT (-info->total_size)); | |
13516 | ||
13517 | /* SAVE_WORLD takes the caller's LR in R0 and the frame size | |
c4ad648e | 13518 | in R11. It also clobbers R12, so beware! */ |
d62294f5 FJ |
13519 | |
13520 | /* Preserve CR2 for save_world prologues */ | |
13521 | sz = 6; | |
13522 | sz += 32 - info->first_gp_reg_save; | |
13523 | sz += 64 - info->first_fp_reg_save; | |
13524 | sz += LAST_ALTIVEC_REGNO - info->first_altivec_reg_save + 1; | |
13525 | p = rtvec_alloc (sz); | |
13526 | j = 0; | |
13527 | RTVEC_ELT (p, j++) = gen_rtx_CLOBBER (VOIDmode, | |
c4ad648e AM |
13528 | gen_rtx_REG (Pmode, |
13529 | LINK_REGISTER_REGNUM)); | |
d62294f5 | 13530 | RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode, |
c4ad648e AM |
13531 | gen_rtx_SYMBOL_REF (Pmode, |
13532 | "*save_world")); | |
d62294f5 | 13533 | /* We do floats first so that the instruction pattern matches |
c4ad648e AM |
13534 | properly. */ |
13535 | for (i = 0; i < 64 - info->first_fp_reg_save; i++) | |
13536 | { | |
13537 | rtx reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i); | |
13538 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
13539 | GEN_INT (info->fp_save_offset | |
13540 | + sp_offset + 8 * i)); | |
13541 | rtx mem = gen_rtx_MEM (DFmode, addr); | |
13542 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
13543 | ||
13544 | RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg); | |
13545 | } | |
d62294f5 | 13546 | for (i = 0; info->first_altivec_reg_save + i <= LAST_ALTIVEC_REGNO; i++) |
c4ad648e AM |
13547 | { |
13548 | rtx reg = gen_rtx_REG (V4SImode, info->first_altivec_reg_save + i); | |
13549 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
13550 | GEN_INT (info->altivec_save_offset | |
13551 | + sp_offset + 16 * i)); | |
13552 | rtx mem = gen_rtx_MEM (V4SImode, addr); | |
13553 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
13554 | ||
13555 | RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg); | |
13556 | } | |
d62294f5 | 13557 | for (i = 0; i < 32 - info->first_gp_reg_save; i++) |
c4ad648e AM |
13558 | { |
13559 | rtx reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i); | |
13560 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
13561 | GEN_INT (info->gp_save_offset | |
13562 | + sp_offset + reg_size * i)); | |
13563 | rtx mem = gen_rtx_MEM (reg_mode, addr); | |
13564 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
13565 | ||
13566 | RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg); | |
13567 | } | |
13568 | ||
13569 | { | |
13570 | /* CR register traditionally saved as CR2. */ | |
13571 | rtx reg = gen_rtx_REG (reg_mode, CR2_REGNO); | |
13572 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
13573 | GEN_INT (info->cr_save_offset | |
13574 | + sp_offset)); | |
13575 | rtx mem = gen_rtx_MEM (reg_mode, addr); | |
13576 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
13577 | ||
13578 | RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg); | |
13579 | } | |
d62294f5 FJ |
13580 | /* Prevent any attempt to delete the setting of r0 and treg! */ |
13581 | RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode, gen_rtx_REG (Pmode, 0)); | |
13582 | RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode, treg); | |
13583 | RTVEC_ELT (p, j++) = gen_rtx_CLOBBER (VOIDmode, sp_reg_rtx); | |
13584 | ||
13585 | insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p)); | |
13586 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, | |
c4ad648e | 13587 | NULL_RTX, NULL_RTX); |
d62294f5 FJ |
13588 | |
13589 | if (current_function_calls_eh_return) | |
c4ad648e AM |
13590 | { |
13591 | unsigned int i; | |
13592 | for (i = 0; ; ++i) | |
13593 | { | |
13594 | unsigned int regno = EH_RETURN_DATA_REGNO (i); | |
13595 | if (regno == INVALID_REGNUM) | |
13596 | break; | |
13597 | emit_frame_save (frame_reg_rtx, frame_ptr_rtx, reg_mode, regno, | |
13598 | info->ehrd_offset + sp_offset | |
13599 | + reg_size * (int) i, | |
13600 | info->total_size); | |
13601 | } | |
13602 | } | |
d62294f5 FJ |
13603 | } |
13604 | ||
9aa86737 | 13605 | /* Save AltiVec registers if needed. */ |
d62294f5 | 13606 | if (! info->world_save_p && TARGET_ALTIVEC_ABI && info->altivec_size != 0) |
9aa86737 AH |
13607 | { |
13608 | int i; | |
13609 | ||
13610 | /* There should be a non inline version of this, for when we | |
13611 | are saving lots of vector registers. */ | |
13612 | for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i) | |
13613 | if (info->vrsave_mask & ALTIVEC_REG_BIT (i)) | |
13614 | { | |
13615 | rtx areg, savereg, mem; | |
13616 | int offset; | |
13617 | ||
13618 | offset = info->altivec_save_offset + sp_offset | |
13619 | + 16 * (i - info->first_altivec_reg_save); | |
13620 | ||
13621 | savereg = gen_rtx_REG (V4SImode, i); | |
13622 | ||
13623 | areg = gen_rtx_REG (Pmode, 0); | |
13624 | emit_move_insn (areg, GEN_INT (offset)); | |
13625 | ||
13626 | /* AltiVec addressing mode is [reg+reg]. */ | |
13627 | mem = gen_rtx_MEM (V4SImode, | |
13628 | gen_rtx_PLUS (Pmode, frame_reg_rtx, areg)); | |
f676971a | 13629 | |
9aa86737 AH |
13630 | set_mem_alias_set (mem, rs6000_sr_alias_set); |
13631 | ||
13632 | insn = emit_move_insn (mem, savereg); | |
13633 | ||
5c242421 SB |
13634 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, |
13635 | areg, GEN_INT (offset)); | |
9aa86737 AH |
13636 | } |
13637 | } | |
13638 | ||
13639 | /* VRSAVE is a bit vector representing which AltiVec registers | |
13640 | are used. The OS uses this to determine which vector | |
13641 | registers to save on a context switch. We need to save | |
13642 | VRSAVE on the stack frame, add whatever AltiVec registers we | |
13643 | used in this function, and do the corresponding magic in the | |
13644 | epilogue. */ | |
13645 | ||
4d774ff8 | 13646 | if (TARGET_ALTIVEC && TARGET_ALTIVEC_VRSAVE |
d62294f5 | 13647 | && ! info->world_save_p && info->vrsave_mask != 0) |
9aa86737 | 13648 | { |
a004eb82 | 13649 | rtx reg, mem, vrsave; |
9aa86737 AH |
13650 | int offset; |
13651 | ||
13652 | /* Get VRSAVE onto a GPR. */ | |
13653 | reg = gen_rtx_REG (SImode, 12); | |
a004eb82 | 13654 | vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO); |
b188f760 AH |
13655 | if (TARGET_MACHO) |
13656 | emit_insn (gen_get_vrsave_internal (reg)); | |
13657 | else | |
13658 | emit_insn (gen_rtx_SET (VOIDmode, reg, vrsave)); | |
9aa86737 AH |
13659 | |
13660 | /* Save VRSAVE. */ | |
13661 | offset = info->vrsave_save_offset + sp_offset; | |
13662 | mem | |
13663 | = gen_rtx_MEM (SImode, | |
13664 | gen_rtx_PLUS (Pmode, frame_reg_rtx, GEN_INT (offset))); | |
13665 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
13666 | insn = emit_move_insn (mem, reg); | |
13667 | ||
13668 | /* Include the registers in the mask. */ | |
13669 | emit_insn (gen_iorsi3 (reg, reg, GEN_INT ((int) info->vrsave_mask))); | |
13670 | ||
13671 | insn = emit_insn (generate_set_vrsave (reg, info, 0)); | |
13672 | } | |
13673 | ||
9ebbca7d | 13674 | /* If we use the link register, get it into r0. */ |
d62294f5 | 13675 | if (! info->world_save_p && info->lr_save_p) |
f8a57be8 GK |
13676 | { |
13677 | insn = emit_move_insn (gen_rtx_REG (Pmode, 0), | |
13678 | gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)); | |
13679 | RTX_FRAME_RELATED_P (insn) = 1; | |
13680 | } | |
9ebbca7d GK |
13681 | |
13682 | /* If we need to save CR, put it into r12. */ | |
d62294f5 | 13683 | if (! info->world_save_p && info->cr_save_p && frame_reg_rtx != frame_ptr_rtx) |
9ebbca7d | 13684 | { |
f8a57be8 | 13685 | rtx set; |
f676971a | 13686 | |
9ebbca7d | 13687 | cr_save_rtx = gen_rtx_REG (SImode, 12); |
f8a57be8 GK |
13688 | insn = emit_insn (gen_movesi_from_cr (cr_save_rtx)); |
13689 | RTX_FRAME_RELATED_P (insn) = 1; | |
13690 | /* Now, there's no way that dwarf2out_frame_debug_expr is going | |
13691 | to understand '(unspec:SI [(reg:CC 68) ...] UNSPEC_MOVESI_FROM_CR)'. | |
13692 | But that's OK. All we have to do is specify that _one_ condition | |
13693 | code register is saved in this stack slot. The thrower's epilogue | |
13694 | will then restore all the call-saved registers. | |
13695 | We use CR2_REGNO (70) to be compatible with gcc-2.95 on Linux. */ | |
13696 | set = gen_rtx_SET (VOIDmode, cr_save_rtx, | |
13697 | gen_rtx_REG (SImode, CR2_REGNO)); | |
13698 | REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, | |
13699 | set, | |
13700 | REG_NOTES (insn)); | |
9ebbca7d GK |
13701 | } |
13702 | ||
a4f6c312 SS |
13703 | /* Do any required saving of fpr's. If only one or two to save, do |
13704 | it ourselves. Otherwise, call function. */ | |
d62294f5 | 13705 | if (! info->world_save_p && saving_FPRs_inline) |
9ebbca7d GK |
13706 | { |
13707 | int i; | |
13708 | for (i = 0; i < 64 - info->first_fp_reg_save; i++) | |
f676971a | 13709 | if ((regs_ever_live[info->first_fp_reg_save+i] |
9ebbca7d | 13710 | && ! call_used_regs[info->first_fp_reg_save+i])) |
89e7058f AH |
13711 | emit_frame_save (frame_reg_rtx, frame_ptr_rtx, DFmode, |
13712 | info->first_fp_reg_save + i, | |
13713 | info->fp_save_offset + sp_offset + 8 * i, | |
13714 | info->total_size); | |
9ebbca7d | 13715 | } |
d62294f5 | 13716 | else if (! info->world_save_p && info->first_fp_reg_save != 64) |
9ebbca7d GK |
13717 | { |
13718 | int i; | |
13719 | char rname[30]; | |
520a57c8 | 13720 | const char *alloc_rname; |
9ebbca7d GK |
13721 | rtvec p; |
13722 | p = rtvec_alloc (2 + 64 - info->first_fp_reg_save); | |
f676971a EC |
13723 | |
13724 | RTVEC_ELT (p, 0) = gen_rtx_CLOBBER (VOIDmode, | |
13725 | gen_rtx_REG (Pmode, | |
9ebbca7d GK |
13726 | LINK_REGISTER_REGNUM)); |
13727 | sprintf (rname, "%s%d%s", SAVE_FP_PREFIX, | |
13728 | info->first_fp_reg_save - 32, SAVE_FP_SUFFIX); | |
a8a05998 | 13729 | alloc_rname = ggc_strdup (rname); |
9ebbca7d GK |
13730 | RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode, |
13731 | gen_rtx_SYMBOL_REF (Pmode, | |
13732 | alloc_rname)); | |
13733 | for (i = 0; i < 64 - info->first_fp_reg_save; i++) | |
13734 | { | |
13735 | rtx addr, reg, mem; | |
13736 | reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i); | |
13737 | addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
f676971a | 13738 | GEN_INT (info->fp_save_offset |
9ebbca7d GK |
13739 | + sp_offset + 8*i)); |
13740 | mem = gen_rtx_MEM (DFmode, addr); | |
ba4828e0 | 13741 | set_mem_alias_set (mem, rs6000_sr_alias_set); |
9ebbca7d GK |
13742 | |
13743 | RTVEC_ELT (p, i + 2) = gen_rtx_SET (VOIDmode, mem, reg); | |
13744 | } | |
13745 | insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p)); | |
f676971a | 13746 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, |
9ebbca7d GK |
13747 | NULL_RTX, NULL_RTX); |
13748 | } | |
b6c9286a | 13749 | |
9ebbca7d GK |
13750 | /* Save GPRs. This is done as a PARALLEL if we are using |
13751 | the store-multiple instructions. */ | |
d62294f5 | 13752 | if (! info->world_save_p && using_store_multiple) |
b6c9286a | 13753 | { |
308c142a | 13754 | rtvec p; |
9ebbca7d GK |
13755 | int i; |
13756 | p = rtvec_alloc (32 - info->first_gp_reg_save); | |
9ebbca7d GK |
13757 | for (i = 0; i < 32 - info->first_gp_reg_save; i++) |
13758 | { | |
13759 | rtx addr, reg, mem; | |
13760 | reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i); | |
f676971a EC |
13761 | addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, |
13762 | GEN_INT (info->gp_save_offset | |
13763 | + sp_offset | |
9ebbca7d GK |
13764 | + reg_size * i)); |
13765 | mem = gen_rtx_MEM (reg_mode, addr); | |
ba4828e0 | 13766 | set_mem_alias_set (mem, rs6000_sr_alias_set); |
9ebbca7d GK |
13767 | |
13768 | RTVEC_ELT (p, i) = gen_rtx_SET (VOIDmode, mem, reg); | |
13769 | } | |
13770 | insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p)); | |
f676971a | 13771 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, |
9ebbca7d | 13772 | NULL_RTX, NULL_RTX); |
b6c9286a | 13773 | } |
d62294f5 | 13774 | else if (! info->world_save_p) |
b6c9286a | 13775 | { |
9ebbca7d GK |
13776 | int i; |
13777 | for (i = 0; i < 32 - info->first_gp_reg_save; i++) | |
f676971a | 13778 | if ((regs_ever_live[info->first_gp_reg_save+i] |
b4db40bf JJ |
13779 | && (! call_used_regs[info->first_gp_reg_save+i] |
13780 | || (i+info->first_gp_reg_save | |
13781 | == RS6000_PIC_OFFSET_TABLE_REGNUM | |
13782 | && TARGET_TOC && TARGET_MINIMAL_TOC))) | |
1db02437 | 13783 | || (i+info->first_gp_reg_save == RS6000_PIC_OFFSET_TABLE_REGNUM |
14f00213 | 13784 | && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0) |
f607bc57 | 13785 | || (DEFAULT_ABI == ABI_DARWIN && flag_pic)))) |
a3170dc6 AH |
13786 | { |
13787 | rtx addr, reg, mem; | |
13788 | reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i); | |
13789 | ||
c19de7aa | 13790 | if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0) |
a3170dc6 AH |
13791 | { |
13792 | int offset = info->spe_gp_save_offset + sp_offset + 8 * i; | |
13793 | rtx b; | |
13794 | ||
13795 | if (!SPE_CONST_OFFSET_OK (offset)) | |
13796 | { | |
13797 | b = gen_rtx_REG (Pmode, FIXED_SCRATCH); | |
13798 | emit_move_insn (b, GEN_INT (offset)); | |
13799 | } | |
13800 | else | |
13801 | b = GEN_INT (offset); | |
13802 | ||
13803 | addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, b); | |
13804 | mem = gen_rtx_MEM (V2SImode, addr); | |
13805 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
13806 | insn = emit_move_insn (mem, reg); | |
13807 | ||
13808 | if (GET_CODE (b) == CONST_INT) | |
13809 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, | |
13810 | NULL_RTX, NULL_RTX); | |
13811 | else | |
13812 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, | |
13813 | b, GEN_INT (offset)); | |
13814 | } | |
13815 | else | |
13816 | { | |
f676971a EC |
13817 | addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, |
13818 | GEN_INT (info->gp_save_offset | |
13819 | + sp_offset | |
a3170dc6 AH |
13820 | + reg_size * i)); |
13821 | mem = gen_rtx_MEM (reg_mode, addr); | |
13822 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
13823 | ||
13824 | insn = emit_move_insn (mem, reg); | |
f676971a | 13825 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, |
a3170dc6 AH |
13826 | NULL_RTX, NULL_RTX); |
13827 | } | |
13828 | } | |
9ebbca7d GK |
13829 | } |
13830 | ||
83720594 RH |
13831 | /* ??? There's no need to emit actual instructions here, but it's the |
13832 | easiest way to get the frame unwind information emitted. */ | |
d62294f5 | 13833 | if (! info->world_save_p && current_function_calls_eh_return) |
83720594 | 13834 | { |
78e1b90d DE |
13835 | unsigned int i, regno; |
13836 | ||
fc4767bb JJ |
13837 | /* In AIX ABI we need to pretend we save r2 here. */ |
13838 | if (TARGET_AIX) | |
13839 | { | |
13840 | rtx addr, reg, mem; | |
13841 | ||
13842 | reg = gen_rtx_REG (reg_mode, 2); | |
13843 | addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
13844 | GEN_INT (sp_offset + 5 * reg_size)); | |
13845 | mem = gen_rtx_MEM (reg_mode, addr); | |
13846 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
13847 | ||
13848 | insn = emit_move_insn (mem, reg); | |
f676971a | 13849 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, |
fc4767bb JJ |
13850 | NULL_RTX, NULL_RTX); |
13851 | PATTERN (insn) = gen_blockage (); | |
13852 | } | |
13853 | ||
83720594 RH |
13854 | for (i = 0; ; ++i) |
13855 | { | |
83720594 RH |
13856 | regno = EH_RETURN_DATA_REGNO (i); |
13857 | if (regno == INVALID_REGNUM) | |
13858 | break; | |
13859 | ||
89e7058f AH |
13860 | emit_frame_save (frame_reg_rtx, frame_ptr_rtx, reg_mode, regno, |
13861 | info->ehrd_offset + sp_offset | |
13862 | + reg_size * (int) i, | |
13863 | info->total_size); | |
83720594 RH |
13864 | } |
13865 | } | |
13866 | ||
9ebbca7d | 13867 | /* Save lr if we used it. */ |
d62294f5 | 13868 | if (! info->world_save_p && info->lr_save_p) |
9ebbca7d GK |
13869 | { |
13870 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
13871 | GEN_INT (info->lr_save_offset + sp_offset)); | |
13872 | rtx reg = gen_rtx_REG (Pmode, 0); | |
13873 | rtx mem = gen_rtx_MEM (Pmode, addr); | |
13874 | /* This should not be of rs6000_sr_alias_set, because of | |
13875 | __builtin_return_address. */ | |
f676971a | 13876 | |
9ebbca7d | 13877 | insn = emit_move_insn (mem, reg); |
f676971a | 13878 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, |
f8a57be8 | 13879 | NULL_RTX, NULL_RTX); |
9ebbca7d GK |
13880 | } |
13881 | ||
13882 | /* Save CR if we use any that must be preserved. */ | |
d62294f5 | 13883 | if (! info->world_save_p && info->cr_save_p) |
9ebbca7d GK |
13884 | { |
13885 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
13886 | GEN_INT (info->cr_save_offset + sp_offset)); | |
13887 | rtx mem = gen_rtx_MEM (SImode, addr); | |
f8a57be8 GK |
13888 | /* See the large comment above about why CR2_REGNO is used. */ |
13889 | rtx magic_eh_cr_reg = gen_rtx_REG (SImode, CR2_REGNO); | |
ba4828e0 RK |
13890 | |
13891 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
9ebbca7d GK |
13892 | |
13893 | /* If r12 was used to hold the original sp, copy cr into r0 now | |
13894 | that it's free. */ | |
13895 | if (REGNO (frame_reg_rtx) == 12) | |
13896 | { | |
f8a57be8 GK |
13897 | rtx set; |
13898 | ||
9ebbca7d | 13899 | cr_save_rtx = gen_rtx_REG (SImode, 0); |
f8a57be8 GK |
13900 | insn = emit_insn (gen_movesi_from_cr (cr_save_rtx)); |
13901 | RTX_FRAME_RELATED_P (insn) = 1; | |
13902 | set = gen_rtx_SET (VOIDmode, cr_save_rtx, magic_eh_cr_reg); | |
13903 | REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, | |
13904 | set, | |
13905 | REG_NOTES (insn)); | |
f676971a | 13906 | |
9ebbca7d GK |
13907 | } |
13908 | insn = emit_move_insn (mem, cr_save_rtx); | |
13909 | ||
f676971a | 13910 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, |
f8a57be8 | 13911 | NULL_RTX, NULL_RTX); |
9ebbca7d GK |
13912 | } |
13913 | ||
f676971a | 13914 | /* Update stack and set back pointer unless this is V.4, |
9ebbca7d | 13915 | for which it was done previously. */ |
d62294f5 | 13916 | if (! info->world_save_p && info->push_p |
fc4767bb | 13917 | && !(DEFAULT_ABI == ABI_V4 || current_function_calls_eh_return)) |
9ebbca7d GK |
13918 | rs6000_emit_allocate_stack (info->total_size, FALSE); |
13919 | ||
13920 | /* Set frame pointer, if needed. */ | |
13921 | if (frame_pointer_needed) | |
13922 | { | |
f676971a | 13923 | insn = emit_move_insn (gen_rtx_REG (Pmode, FRAME_POINTER_REGNUM), |
9ebbca7d GK |
13924 | sp_reg_rtx); |
13925 | RTX_FRAME_RELATED_P (insn) = 1; | |
b6c9286a | 13926 | } |
9878760c | 13927 | |
1db02437 | 13928 | /* If we are using RS6000_PIC_OFFSET_TABLE_REGNUM, we need to set it up. */ |
9ebbca7d | 13929 | if ((TARGET_TOC && TARGET_MINIMAL_TOC && get_pool_size () != 0) |
f607bc57 | 13930 | || (DEFAULT_ABI == ABI_V4 && flag_pic == 1 |
1db02437 | 13931 | && regs_ever_live[RS6000_PIC_OFFSET_TABLE_REGNUM])) |
c4ad648e AM |
13932 | { |
13933 | /* If emit_load_toc_table will use the link register, we need to save | |
13934 | it. We use R12 for this purpose because emit_load_toc_table | |
13935 | can use register 0. This allows us to use a plain 'blr' to return | |
13936 | from the procedure more often. */ | |
13937 | int save_LR_around_toc_setup = (TARGET_ELF | |
13938 | && DEFAULT_ABI != ABI_AIX | |
13939 | && flag_pic | |
13940 | && ! info->lr_save_p | |
13941 | && EDGE_COUNT (EXIT_BLOCK_PTR->preds) > 0); | |
13942 | if (save_LR_around_toc_setup) | |
13943 | { | |
13944 | rtx lr = gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM); | |
f8a57be8 | 13945 | |
c4ad648e AM |
13946 | insn = emit_move_insn (frame_ptr_rtx, lr); |
13947 | rs6000_maybe_dead (insn); | |
13948 | RTX_FRAME_RELATED_P (insn) = 1; | |
f8a57be8 | 13949 | |
c4ad648e | 13950 | rs6000_emit_load_toc_table (TRUE); |
f8a57be8 | 13951 | |
c4ad648e AM |
13952 | insn = emit_move_insn (lr, frame_ptr_rtx); |
13953 | rs6000_maybe_dead (insn); | |
13954 | RTX_FRAME_RELATED_P (insn) = 1; | |
13955 | } | |
13956 | else | |
13957 | rs6000_emit_load_toc_table (TRUE); | |
13958 | } | |
ee890fe2 | 13959 | |
fcce224d | 13960 | #if TARGET_MACHO |
ee890fe2 SS |
13961 | if (DEFAULT_ABI == ABI_DARWIN |
13962 | && flag_pic && current_function_uses_pic_offset_table) | |
13963 | { | |
f8a57be8 | 13964 | rtx lr = gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM); |
11abc112 | 13965 | rtx src = machopic_function_base_sym (); |
ee890fe2 | 13966 | |
f8a57be8 | 13967 | rs6000_maybe_dead (emit_insn (gen_load_macho_picbase (lr, src))); |
ee890fe2 | 13968 | |
f676971a | 13969 | insn = emit_move_insn (gen_rtx_REG (Pmode, |
f8a57be8 GK |
13970 | RS6000_PIC_OFFSET_TABLE_REGNUM), |
13971 | lr); | |
13972 | rs6000_maybe_dead (insn); | |
ee890fe2 | 13973 | } |
fcce224d | 13974 | #endif |
9ebbca7d GK |
13975 | } |
13976 | ||
9ebbca7d | 13977 | /* Write function prologue. */ |
a4f6c312 | 13978 | |
08c148a8 | 13979 | static void |
f676971a | 13980 | rs6000_output_function_prologue (FILE *file, |
a2369ed3 | 13981 | HOST_WIDE_INT size ATTRIBUTE_UNUSED) |
9ebbca7d GK |
13982 | { |
13983 | rs6000_stack_t *info = rs6000_stack_info (); | |
13984 | ||
4697a36c MM |
13985 | if (TARGET_DEBUG_STACK) |
13986 | debug_stack_info (info); | |
9878760c | 13987 | |
a4f6c312 SS |
13988 | /* Write .extern for any function we will call to save and restore |
13989 | fp values. */ | |
13990 | if (info->first_fp_reg_save < 64 | |
13991 | && !FP_SAVE_INLINE (info->first_fp_reg_save)) | |
4d30c363 | 13992 | fprintf (file, "\t.extern %s%d%s\n\t.extern %s%d%s\n", |
4697a36c | 13993 | SAVE_FP_PREFIX, info->first_fp_reg_save - 32, SAVE_FP_SUFFIX, |
a4f6c312 SS |
13994 | RESTORE_FP_PREFIX, info->first_fp_reg_save - 32, |
13995 | RESTORE_FP_SUFFIX); | |
9878760c | 13996 | |
c764f757 RK |
13997 | /* Write .extern for AIX common mode routines, if needed. */ |
13998 | if (! TARGET_POWER && ! TARGET_POWERPC && ! common_mode_defined) | |
13999 | { | |
f6709c70 JW |
14000 | fputs ("\t.extern __mulh\n", file); |
14001 | fputs ("\t.extern __mull\n", file); | |
14002 | fputs ("\t.extern __divss\n", file); | |
14003 | fputs ("\t.extern __divus\n", file); | |
14004 | fputs ("\t.extern __quoss\n", file); | |
14005 | fputs ("\t.extern __quous\n", file); | |
c764f757 RK |
14006 | common_mode_defined = 1; |
14007 | } | |
9878760c | 14008 | |
9ebbca7d | 14009 | if (! HAVE_prologue) |
979721f8 | 14010 | { |
9ebbca7d | 14011 | start_sequence (); |
9dda4cc8 | 14012 | |
a4f6c312 SS |
14013 | /* A NOTE_INSN_DELETED is supposed to be at the start and end of |
14014 | the "toplevel" insn chain. */ | |
2e040219 | 14015 | emit_note (NOTE_INSN_DELETED); |
9ebbca7d | 14016 | rs6000_emit_prologue (); |
2e040219 | 14017 | emit_note (NOTE_INSN_DELETED); |
178c3eff | 14018 | |
a3c9585f | 14019 | /* Expand INSN_ADDRESSES so final() doesn't crash. */ |
178c3eff DJ |
14020 | { |
14021 | rtx insn; | |
14022 | unsigned addr = 0; | |
14023 | for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn)) | |
14024 | { | |
14025 | INSN_ADDRESSES_NEW (insn, addr); | |
14026 | addr += 4; | |
14027 | } | |
14028 | } | |
9dda4cc8 | 14029 | |
9ebbca7d | 14030 | if (TARGET_DEBUG_STACK) |
a4f6c312 SS |
14031 | debug_rtx_list (get_insns (), 100); |
14032 | final (get_insns (), file, FALSE, FALSE); | |
9ebbca7d | 14033 | end_sequence (); |
979721f8 MM |
14034 | } |
14035 | ||
9ebbca7d GK |
14036 | rs6000_pic_labelno++; |
14037 | } | |
f676971a | 14038 | |
9ebbca7d | 14039 | /* Emit function epilogue as insns. |
9878760c | 14040 | |
9ebbca7d GK |
14041 | At present, dwarf2out_frame_debug_expr doesn't understand |
14042 | register restores, so we don't bother setting RTX_FRAME_RELATED_P | |
14043 | anywhere in the epilogue. Most of the insns below would in any case | |
14044 | need special notes to explain where r11 is in relation to the stack. */ | |
9878760c | 14045 | |
9ebbca7d | 14046 | void |
a2369ed3 | 14047 | rs6000_emit_epilogue (int sibcall) |
9ebbca7d GK |
14048 | { |
14049 | rs6000_stack_t *info; | |
14050 | int restoring_FPRs_inline; | |
14051 | int using_load_multiple; | |
14052 | int using_mfcr_multiple; | |
14053 | int use_backchain_to_restore_sp; | |
14054 | int sp_offset = 0; | |
14055 | rtx sp_reg_rtx = gen_rtx_REG (Pmode, 1); | |
14056 | rtx frame_reg_rtx = sp_reg_rtx; | |
0e67400a | 14057 | enum machine_mode reg_mode = Pmode; |
327e5343 | 14058 | int reg_size = TARGET_32BIT ? 4 : 8; |
9ebbca7d GK |
14059 | int i; |
14060 | ||
c19de7aa AH |
14061 | info = rs6000_stack_info (); |
14062 | ||
14063 | if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0) | |
a3170dc6 AH |
14064 | { |
14065 | reg_mode = V2SImode; | |
14066 | reg_size = 8; | |
14067 | } | |
14068 | ||
9ebbca7d | 14069 | using_load_multiple = (TARGET_MULTIPLE && ! TARGET_POWERPC64 |
c19de7aa AH |
14070 | && (!TARGET_SPE_ABI |
14071 | || info->spe_64bit_regs_used == 0) | |
9ebbca7d GK |
14072 | && info->first_gp_reg_save < 31); |
14073 | restoring_FPRs_inline = (sibcall | |
83720594 | 14074 | || current_function_calls_eh_return |
9ebbca7d GK |
14075 | || info->first_fp_reg_save == 64 |
14076 | || FP_SAVE_INLINE (info->first_fp_reg_save)); | |
f676971a | 14077 | use_backchain_to_restore_sp = (frame_pointer_needed |
9ebbca7d GK |
14078 | || current_function_calls_alloca |
14079 | || info->total_size > 32767); | |
14080 | using_mfcr_multiple = (rs6000_cpu == PROCESSOR_PPC601 | |
14081 | || rs6000_cpu == PROCESSOR_PPC603 | |
14082 | || rs6000_cpu == PROCESSOR_PPC750 | |
14083 | || optimize_size); | |
14084 | ||
d62294f5 FJ |
14085 | if (info->world_save_p) |
14086 | { | |
14087 | int i, j; | |
14088 | char rname[30]; | |
14089 | const char *alloc_rname; | |
14090 | rtvec p; | |
14091 | ||
14092 | /* eh_rest_world_r10 will return to the location saved in the LR | |
c4ad648e AM |
14093 | stack slot (which is not likely to be our caller.) |
14094 | Input: R10 -- stack adjustment. Clobbers R0, R11, R12, R7, R8. | |
14095 | rest_world is similar, except any R10 parameter is ignored. | |
14096 | The exception-handling stuff that was here in 2.95 is no | |
14097 | longer necessary. */ | |
d62294f5 FJ |
14098 | |
14099 | p = rtvec_alloc (9 | |
14100 | + 1 | |
f676971a | 14101 | + 32 - info->first_gp_reg_save |
c4ad648e AM |
14102 | + LAST_ALTIVEC_REGNO + 1 - info->first_altivec_reg_save |
14103 | + 63 + 1 - info->first_fp_reg_save); | |
d62294f5 | 14104 | |
c4ad648e AM |
14105 | strcpy (rname, ((current_function_calls_eh_return) ? |
14106 | "*eh_rest_world_r10" : "*rest_world")); | |
d62294f5 FJ |
14107 | alloc_rname = ggc_strdup (rname); |
14108 | ||
14109 | j = 0; | |
14110 | RTVEC_ELT (p, j++) = gen_rtx_RETURN (VOIDmode); | |
14111 | RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode, | |
c4ad648e AM |
14112 | gen_rtx_REG (Pmode, |
14113 | LINK_REGISTER_REGNUM)); | |
d62294f5 | 14114 | RTVEC_ELT (p, j++) |
c4ad648e | 14115 | = gen_rtx_USE (VOIDmode, gen_rtx_SYMBOL_REF (Pmode, alloc_rname)); |
d62294f5 | 14116 | /* The instruction pattern requires a clobber here; |
c4ad648e | 14117 | it is shared with the restVEC helper. */ |
d62294f5 | 14118 | RTVEC_ELT (p, j++) |
c4ad648e | 14119 | = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 11)); |
d62294f5 FJ |
14120 | |
14121 | { | |
c4ad648e AM |
14122 | /* CR register traditionally saved as CR2. */ |
14123 | rtx reg = gen_rtx_REG (reg_mode, CR2_REGNO); | |
14124 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
14125 | GEN_INT (info->cr_save_offset)); | |
14126 | rtx mem = gen_rtx_MEM (reg_mode, addr); | |
14127 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
14128 | ||
14129 | RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem); | |
d62294f5 FJ |
14130 | } |
14131 | ||
14132 | for (i = 0; i < 32 - info->first_gp_reg_save; i++) | |
c4ad648e AM |
14133 | { |
14134 | rtx reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i); | |
14135 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
14136 | GEN_INT (info->gp_save_offset | |
14137 | + reg_size * i)); | |
14138 | rtx mem = gen_rtx_MEM (reg_mode, addr); | |
14139 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
14140 | ||
14141 | RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem); | |
14142 | } | |
d62294f5 | 14143 | for (i = 0; info->first_altivec_reg_save + i <= LAST_ALTIVEC_REGNO; i++) |
c4ad648e AM |
14144 | { |
14145 | rtx reg = gen_rtx_REG (V4SImode, info->first_altivec_reg_save + i); | |
14146 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
14147 | GEN_INT (info->altivec_save_offset | |
14148 | + 16 * i)); | |
14149 | rtx mem = gen_rtx_MEM (V4SImode, addr); | |
14150 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
14151 | ||
14152 | RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem); | |
14153 | } | |
d62294f5 | 14154 | for (i = 0; info->first_fp_reg_save + i <= 63; i++) |
c4ad648e AM |
14155 | { |
14156 | rtx reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i); | |
14157 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
14158 | GEN_INT (info->fp_save_offset | |
14159 | + 8 * i)); | |
14160 | rtx mem = gen_rtx_MEM (DFmode, addr); | |
14161 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
14162 | ||
14163 | RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem); | |
14164 | } | |
d62294f5 | 14165 | RTVEC_ELT (p, j++) |
c4ad648e | 14166 | = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 0)); |
d62294f5 | 14167 | RTVEC_ELT (p, j++) |
c4ad648e | 14168 | = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 12)); |
d62294f5 | 14169 | RTVEC_ELT (p, j++) |
c4ad648e | 14170 | = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 7)); |
d62294f5 | 14171 | RTVEC_ELT (p, j++) |
c4ad648e | 14172 | = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 8)); |
d62294f5 | 14173 | RTVEC_ELT (p, j++) |
c4ad648e | 14174 | = gen_rtx_USE (VOIDmode, gen_rtx_REG (SImode, 10)); |
d62294f5 FJ |
14175 | emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p)); |
14176 | ||
14177 | return; | |
14178 | } | |
14179 | ||
9ebbca7d GK |
14180 | /* If we have a frame pointer, a call to alloca, or a large stack |
14181 | frame, restore the old stack pointer using the backchain. Otherwise, | |
14182 | we know what size to update it with. */ | |
14183 | if (use_backchain_to_restore_sp) | |
bacbde18 | 14184 | { |
9ebbca7d GK |
14185 | /* Under V.4, don't reset the stack pointer until after we're done |
14186 | loading the saved registers. */ | |
f607bc57 | 14187 | if (DEFAULT_ABI == ABI_V4) |
9ebbca7d | 14188 | frame_reg_rtx = gen_rtx_REG (Pmode, 11); |
4697a36c | 14189 | |
9ebbca7d GK |
14190 | emit_move_insn (frame_reg_rtx, |
14191 | gen_rtx_MEM (Pmode, sp_reg_rtx)); | |
f676971a | 14192 | |
bacbde18 | 14193 | } |
9ebbca7d | 14194 | else if (info->push_p) |
85638c0d | 14195 | { |
fc4767bb JJ |
14196 | if (DEFAULT_ABI == ABI_V4 |
14197 | || current_function_calls_eh_return) | |
9ebbca7d GK |
14198 | sp_offset = info->total_size; |
14199 | else | |
14200 | { | |
14201 | emit_insn (TARGET_32BIT | |
14202 | ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx, | |
14203 | GEN_INT (info->total_size)) | |
14204 | : gen_adddi3 (sp_reg_rtx, sp_reg_rtx, | |
14205 | GEN_INT (info->total_size))); | |
14206 | } | |
85638c0d | 14207 | } |
f676971a | 14208 | |
9aa86737 AH |
14209 | /* Restore AltiVec registers if needed. */ |
14210 | if (TARGET_ALTIVEC_ABI && info->altivec_size != 0) | |
14211 | { | |
14212 | int i; | |
14213 | ||
14214 | for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i) | |
14215 | if (info->vrsave_mask & ALTIVEC_REG_BIT (i)) | |
14216 | { | |
14217 | rtx addr, areg, mem; | |
14218 | ||
14219 | areg = gen_rtx_REG (Pmode, 0); | |
14220 | emit_move_insn | |
14221 | (areg, GEN_INT (info->altivec_save_offset | |
14222 | + sp_offset | |
14223 | + 16 * (i - info->first_altivec_reg_save))); | |
14224 | ||
14225 | /* AltiVec addressing mode is [reg+reg]. */ | |
14226 | addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, areg); | |
14227 | mem = gen_rtx_MEM (V4SImode, addr); | |
14228 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
14229 | ||
14230 | emit_move_insn (gen_rtx_REG (V4SImode, i), mem); | |
14231 | } | |
14232 | } | |
14233 | ||
14234 | /* Restore VRSAVE if needed. */ | |
44688022 | 14235 | if (TARGET_ALTIVEC && TARGET_ALTIVEC_VRSAVE |
4d774ff8 | 14236 | && info->vrsave_mask != 0) |
9aa86737 AH |
14237 | { |
14238 | rtx addr, mem, reg; | |
14239 | ||
14240 | addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
14241 | GEN_INT (info->vrsave_save_offset + sp_offset)); | |
14242 | mem = gen_rtx_MEM (SImode, addr); | |
14243 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
14244 | reg = gen_rtx_REG (SImode, 12); | |
14245 | emit_move_insn (reg, mem); | |
14246 | ||
14247 | emit_insn (generate_set_vrsave (reg, info, 1)); | |
14248 | } | |
14249 | ||
9ebbca7d GK |
14250 | /* Get the old lr if we saved it. */ |
14251 | if (info->lr_save_p) | |
b6c9286a | 14252 | { |
a3170dc6 AH |
14253 | rtx mem = gen_frame_mem_offset (Pmode, frame_reg_rtx, |
14254 | info->lr_save_offset + sp_offset); | |
ba4828e0 RK |
14255 | |
14256 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
b6c9286a | 14257 | |
9ebbca7d | 14258 | emit_move_insn (gen_rtx_REG (Pmode, 0), mem); |
b6c9286a | 14259 | } |
f676971a | 14260 | |
9ebbca7d GK |
14261 | /* Get the old cr if we saved it. */ |
14262 | if (info->cr_save_p) | |
14263 | { | |
14264 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
14265 | GEN_INT (info->cr_save_offset + sp_offset)); | |
14266 | rtx mem = gen_rtx_MEM (SImode, addr); | |
ba4828e0 RK |
14267 | |
14268 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
b6c9286a | 14269 | |
9ebbca7d GK |
14270 | emit_move_insn (gen_rtx_REG (SImode, 12), mem); |
14271 | } | |
f676971a | 14272 | |
9ebbca7d | 14273 | /* Set LR here to try to overlap restores below. */ |
4697a36c | 14274 | if (info->lr_save_p) |
9ebbca7d GK |
14275 | emit_move_insn (gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM), |
14276 | gen_rtx_REG (Pmode, 0)); | |
f676971a | 14277 | |
83720594 RH |
14278 | /* Load exception handler data registers, if needed. */ |
14279 | if (current_function_calls_eh_return) | |
14280 | { | |
78e1b90d DE |
14281 | unsigned int i, regno; |
14282 | ||
fc4767bb JJ |
14283 | if (TARGET_AIX) |
14284 | { | |
14285 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
14286 | GEN_INT (sp_offset + 5 * reg_size)); | |
14287 | rtx mem = gen_rtx_MEM (reg_mode, addr); | |
14288 | ||
14289 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
14290 | ||
14291 | emit_move_insn (gen_rtx_REG (reg_mode, 2), mem); | |
14292 | } | |
14293 | ||
83720594 RH |
14294 | for (i = 0; ; ++i) |
14295 | { | |
a3170dc6 | 14296 | rtx mem; |
83720594 RH |
14297 | |
14298 | regno = EH_RETURN_DATA_REGNO (i); | |
14299 | if (regno == INVALID_REGNUM) | |
14300 | break; | |
14301 | ||
a3170dc6 AH |
14302 | mem = gen_frame_mem_offset (reg_mode, frame_reg_rtx, |
14303 | info->ehrd_offset + sp_offset | |
14304 | + reg_size * (int) i); | |
ba4828e0 | 14305 | set_mem_alias_set (mem, rs6000_sr_alias_set); |
83720594 RH |
14306 | |
14307 | emit_move_insn (gen_rtx_REG (reg_mode, regno), mem); | |
14308 | } | |
14309 | } | |
f676971a | 14310 | |
9ebbca7d GK |
14311 | /* Restore GPRs. This is done as a PARALLEL if we are using |
14312 | the load-multiple instructions. */ | |
14313 | if (using_load_multiple) | |
979721f8 | 14314 | { |
9ebbca7d GK |
14315 | rtvec p; |
14316 | p = rtvec_alloc (32 - info->first_gp_reg_save); | |
14317 | for (i = 0; i < 32 - info->first_gp_reg_save; i++) | |
979721f8 | 14318 | { |
f676971a EC |
14319 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, |
14320 | GEN_INT (info->gp_save_offset | |
14321 | + sp_offset | |
9ebbca7d GK |
14322 | + reg_size * i)); |
14323 | rtx mem = gen_rtx_MEM (reg_mode, addr); | |
ba4828e0 RK |
14324 | |
14325 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
9ebbca7d | 14326 | |
f676971a | 14327 | RTVEC_ELT (p, i) = |
9ebbca7d GK |
14328 | gen_rtx_SET (VOIDmode, |
14329 | gen_rtx_REG (reg_mode, info->first_gp_reg_save + i), | |
14330 | mem); | |
979721f8 | 14331 | } |
9ebbca7d | 14332 | emit_insn (gen_rtx_PARALLEL (VOIDmode, p)); |
979721f8 | 14333 | } |
9ebbca7d GK |
14334 | else |
14335 | for (i = 0; i < 32 - info->first_gp_reg_save; i++) | |
f676971a | 14336 | if ((regs_ever_live[info->first_gp_reg_save+i] |
b4db40bf JJ |
14337 | && (! call_used_regs[info->first_gp_reg_save+i] |
14338 | || (i+info->first_gp_reg_save == RS6000_PIC_OFFSET_TABLE_REGNUM | |
14339 | && TARGET_TOC && TARGET_MINIMAL_TOC))) | |
1db02437 | 14340 | || (i+info->first_gp_reg_save == RS6000_PIC_OFFSET_TABLE_REGNUM |
14f00213 | 14341 | && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0) |
f607bc57 | 14342 | || (DEFAULT_ABI == ABI_DARWIN && flag_pic)))) |
9ebbca7d | 14343 | { |
f676971a EC |
14344 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, |
14345 | GEN_INT (info->gp_save_offset | |
14346 | + sp_offset | |
9ebbca7d GK |
14347 | + reg_size * i)); |
14348 | rtx mem = gen_rtx_MEM (reg_mode, addr); | |
ba4828e0 | 14349 | |
a3170dc6 | 14350 | /* Restore 64-bit quantities for SPE. */ |
c19de7aa | 14351 | if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0) |
a3170dc6 AH |
14352 | { |
14353 | int offset = info->spe_gp_save_offset + sp_offset + 8 * i; | |
14354 | rtx b; | |
14355 | ||
14356 | if (!SPE_CONST_OFFSET_OK (offset)) | |
14357 | { | |
14358 | b = gen_rtx_REG (Pmode, FIXED_SCRATCH); | |
14359 | emit_move_insn (b, GEN_INT (offset)); | |
14360 | } | |
14361 | else | |
14362 | b = GEN_INT (offset); | |
14363 | ||
14364 | addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, b); | |
14365 | mem = gen_rtx_MEM (V2SImode, addr); | |
14366 | } | |
14367 | ||
ba4828e0 | 14368 | set_mem_alias_set (mem, rs6000_sr_alias_set); |
9ebbca7d | 14369 | |
f676971a | 14370 | emit_move_insn (gen_rtx_REG (reg_mode, |
a3170dc6 | 14371 | info->first_gp_reg_save + i), mem); |
9ebbca7d | 14372 | } |
9878760c | 14373 | |
9ebbca7d GK |
14374 | /* Restore fpr's if we need to do it without calling a function. */ |
14375 | if (restoring_FPRs_inline) | |
14376 | for (i = 0; i < 64 - info->first_fp_reg_save; i++) | |
f676971a | 14377 | if ((regs_ever_live[info->first_fp_reg_save+i] |
9ebbca7d GK |
14378 | && ! call_used_regs[info->first_fp_reg_save+i])) |
14379 | { | |
14380 | rtx addr, mem; | |
14381 | addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
f676971a EC |
14382 | GEN_INT (info->fp_save_offset |
14383 | + sp_offset | |
a4f6c312 | 14384 | + 8 * i)); |
9ebbca7d | 14385 | mem = gen_rtx_MEM (DFmode, addr); |
ba4828e0 | 14386 | set_mem_alias_set (mem, rs6000_sr_alias_set); |
9ebbca7d | 14387 | |
f676971a | 14388 | emit_move_insn (gen_rtx_REG (DFmode, |
9ebbca7d GK |
14389 | info->first_fp_reg_save + i), |
14390 | mem); | |
14391 | } | |
8d30c4ee | 14392 | |
9ebbca7d GK |
14393 | /* If we saved cr, restore it here. Just those that were used. */ |
14394 | if (info->cr_save_p) | |
979721f8 | 14395 | { |
9ebbca7d | 14396 | rtx r12_rtx = gen_rtx_REG (SImode, 12); |
e35b9579 | 14397 | int count = 0; |
f676971a | 14398 | |
9ebbca7d | 14399 | if (using_mfcr_multiple) |
979721f8 | 14400 | { |
9ebbca7d GK |
14401 | for (i = 0; i < 8; i++) |
14402 | if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i]) | |
e35b9579 | 14403 | count++; |
9ebbca7d | 14404 | if (count == 0) |
e35b9579 GK |
14405 | abort (); |
14406 | } | |
14407 | ||
14408 | if (using_mfcr_multiple && count > 1) | |
14409 | { | |
14410 | rtvec p; | |
14411 | int ndx; | |
f676971a | 14412 | |
e35b9579 | 14413 | p = rtvec_alloc (count); |
9ebbca7d | 14414 | |
e35b9579 | 14415 | ndx = 0; |
9ebbca7d GK |
14416 | for (i = 0; i < 8; i++) |
14417 | if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i]) | |
14418 | { | |
14419 | rtvec r = rtvec_alloc (2); | |
14420 | RTVEC_ELT (r, 0) = r12_rtx; | |
14421 | RTVEC_ELT (r, 1) = GEN_INT (1 << (7-i)); | |
e35b9579 | 14422 | RTVEC_ELT (p, ndx) = |
f676971a | 14423 | gen_rtx_SET (VOIDmode, gen_rtx_REG (CCmode, CR0_REGNO+i), |
615158e2 | 14424 | gen_rtx_UNSPEC (CCmode, r, UNSPEC_MOVESI_TO_CR)); |
e35b9579 | 14425 | ndx++; |
9ebbca7d GK |
14426 | } |
14427 | emit_insn (gen_rtx_PARALLEL (VOIDmode, p)); | |
e35b9579 GK |
14428 | if (ndx != count) |
14429 | abort (); | |
979721f8 MM |
14430 | } |
14431 | else | |
9ebbca7d GK |
14432 | for (i = 0; i < 8; i++) |
14433 | if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i]) | |
979721f8 | 14434 | { |
f676971a | 14435 | emit_insn (gen_movsi_to_cr_one (gen_rtx_REG (CCmode, |
9ebbca7d GK |
14436 | CR0_REGNO+i), |
14437 | r12_rtx)); | |
979721f8 | 14438 | } |
979721f8 MM |
14439 | } |
14440 | ||
9ebbca7d GK |
14441 | /* If this is V.4, unwind the stack pointer after all of the loads |
14442 | have been done. We need to emit a block here so that sched | |
14443 | doesn't decide to move the sp change before the register restores | |
14444 | (which may not have any obvious dependency on the stack). This | |
14445 | doesn't hurt performance, because there is no scheduling that can | |
14446 | be done after this point. */ | |
fc4767bb JJ |
14447 | if (DEFAULT_ABI == ABI_V4 |
14448 | || current_function_calls_eh_return) | |
b6c9286a | 14449 | { |
9ebbca7d | 14450 | if (frame_reg_rtx != sp_reg_rtx) |
c4ad648e | 14451 | rs6000_emit_stack_tie (); |
b6c9286a | 14452 | |
9ebbca7d | 14453 | if (use_backchain_to_restore_sp) |
b6c9286a | 14454 | { |
9ebbca7d | 14455 | emit_move_insn (sp_reg_rtx, frame_reg_rtx); |
b6c9286a | 14456 | } |
9ebbca7d | 14457 | else if (sp_offset != 0) |
13f1623b | 14458 | { |
5b71a4e7 | 14459 | emit_insn (TARGET_32BIT |
9ebbca7d GK |
14460 | ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx, |
14461 | GEN_INT (sp_offset)) | |
14462 | : gen_adddi3 (sp_reg_rtx, sp_reg_rtx, | |
14463 | GEN_INT (sp_offset))); | |
13f1623b | 14464 | } |
9ebbca7d | 14465 | } |
b6c9286a | 14466 | |
83720594 RH |
14467 | if (current_function_calls_eh_return) |
14468 | { | |
14469 | rtx sa = EH_RETURN_STACKADJ_RTX; | |
5b71a4e7 | 14470 | emit_insn (TARGET_32BIT |
83720594 RH |
14471 | ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx, sa) |
14472 | : gen_adddi3 (sp_reg_rtx, sp_reg_rtx, sa)); | |
14473 | } | |
14474 | ||
9ebbca7d GK |
14475 | if (!sibcall) |
14476 | { | |
14477 | rtvec p; | |
14478 | if (! restoring_FPRs_inline) | |
14479 | p = rtvec_alloc (3 + 64 - info->first_fp_reg_save); | |
14480 | else | |
14481 | p = rtvec_alloc (2); | |
b6c9286a | 14482 | |
e35b9579 | 14483 | RTVEC_ELT (p, 0) = gen_rtx_RETURN (VOIDmode); |
f676971a EC |
14484 | RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode, |
14485 | gen_rtx_REG (Pmode, | |
9ebbca7d | 14486 | LINK_REGISTER_REGNUM)); |
9ebbca7d GK |
14487 | |
14488 | /* If we have to restore more than two FP registers, branch to the | |
14489 | restore function. It will return to our caller. */ | |
14490 | if (! restoring_FPRs_inline) | |
14491 | { | |
14492 | int i; | |
14493 | char rname[30]; | |
520a57c8 | 14494 | const char *alloc_rname; |
979721f8 | 14495 | |
f676971a | 14496 | sprintf (rname, "%s%d%s", RESTORE_FP_PREFIX, |
9ebbca7d | 14497 | info->first_fp_reg_save - 32, RESTORE_FP_SUFFIX); |
a8a05998 | 14498 | alloc_rname = ggc_strdup (rname); |
9ebbca7d GK |
14499 | RTVEC_ELT (p, 2) = gen_rtx_USE (VOIDmode, |
14500 | gen_rtx_SYMBOL_REF (Pmode, | |
14501 | alloc_rname)); | |
b6c9286a | 14502 | |
9ebbca7d GK |
14503 | for (i = 0; i < 64 - info->first_fp_reg_save; i++) |
14504 | { | |
14505 | rtx addr, mem; | |
14506 | addr = gen_rtx_PLUS (Pmode, sp_reg_rtx, | |
14507 | GEN_INT (info->fp_save_offset + 8*i)); | |
14508 | mem = gen_rtx_MEM (DFmode, addr); | |
ba4828e0 | 14509 | set_mem_alias_set (mem, rs6000_sr_alias_set); |
9ebbca7d | 14510 | |
f676971a | 14511 | RTVEC_ELT (p, i+3) = |
9ebbca7d GK |
14512 | gen_rtx_SET (VOIDmode, |
14513 | gen_rtx_REG (DFmode, info->first_fp_reg_save + i), | |
14514 | mem); | |
b6c9286a MM |
14515 | } |
14516 | } | |
f676971a | 14517 | |
9ebbca7d | 14518 | emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p)); |
3daf36a4 | 14519 | } |
9878760c RK |
14520 | } |
14521 | ||
14522 | /* Write function epilogue. */ | |
14523 | ||
08c148a8 | 14524 | static void |
f676971a | 14525 | rs6000_output_function_epilogue (FILE *file, |
a2369ed3 | 14526 | HOST_WIDE_INT size ATTRIBUTE_UNUSED) |
9878760c | 14527 | { |
4697a36c | 14528 | rs6000_stack_t *info = rs6000_stack_info (); |
9878760c | 14529 | |
9ebbca7d | 14530 | if (! HAVE_epilogue) |
9878760c | 14531 | { |
9ebbca7d GK |
14532 | rtx insn = get_last_insn (); |
14533 | /* If the last insn was a BARRIER, we don't have to write anything except | |
14534 | the trace table. */ | |
14535 | if (GET_CODE (insn) == NOTE) | |
14536 | insn = prev_nonnote_insn (insn); | |
14537 | if (insn == 0 || GET_CODE (insn) != BARRIER) | |
4697a36c | 14538 | { |
9ebbca7d GK |
14539 | /* This is slightly ugly, but at least we don't have two |
14540 | copies of the epilogue-emitting code. */ | |
14541 | start_sequence (); | |
14542 | ||
14543 | /* A NOTE_INSN_DELETED is supposed to be at the start | |
14544 | and end of the "toplevel" insn chain. */ | |
2e040219 | 14545 | emit_note (NOTE_INSN_DELETED); |
9ebbca7d | 14546 | rs6000_emit_epilogue (FALSE); |
2e040219 | 14547 | emit_note (NOTE_INSN_DELETED); |
9ebbca7d | 14548 | |
a3c9585f | 14549 | /* Expand INSN_ADDRESSES so final() doesn't crash. */ |
178c3eff DJ |
14550 | { |
14551 | rtx insn; | |
14552 | unsigned addr = 0; | |
14553 | for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn)) | |
14554 | { | |
14555 | INSN_ADDRESSES_NEW (insn, addr); | |
14556 | addr += 4; | |
14557 | } | |
14558 | } | |
14559 | ||
9ebbca7d | 14560 | if (TARGET_DEBUG_STACK) |
a4f6c312 SS |
14561 | debug_rtx_list (get_insns (), 100); |
14562 | final (get_insns (), file, FALSE, FALSE); | |
9ebbca7d | 14563 | end_sequence (); |
4697a36c | 14564 | } |
9878760c | 14565 | } |
b4ac57ab | 14566 | |
efdba735 SH |
14567 | #if TARGET_MACHO |
14568 | macho_branch_islands (); | |
0e5da0be GK |
14569 | /* Mach-O doesn't support labels at the end of objects, so if |
14570 | it looks like we might want one, insert a NOP. */ | |
14571 | { | |
14572 | rtx insn = get_last_insn (); | |
14573 | while (insn | |
14574 | && NOTE_P (insn) | |
14575 | && NOTE_LINE_NUMBER (insn) != NOTE_INSN_DELETED_LABEL) | |
14576 | insn = PREV_INSN (insn); | |
f676971a EC |
14577 | if (insn |
14578 | && (LABEL_P (insn) | |
0e5da0be GK |
14579 | || (NOTE_P (insn) |
14580 | && NOTE_LINE_NUMBER (insn) == NOTE_INSN_DELETED_LABEL))) | |
14581 | fputs ("\tnop\n", file); | |
14582 | } | |
14583 | #endif | |
14584 | ||
9b30bae2 | 14585 | /* Output a traceback table here. See /usr/include/sys/debug.h for info |
314fc5a9 ILT |
14586 | on its format. |
14587 | ||
14588 | We don't output a traceback table if -finhibit-size-directive was | |
14589 | used. The documentation for -finhibit-size-directive reads | |
14590 | ``don't output a @code{.size} assembler directive, or anything | |
14591 | else that would cause trouble if the function is split in the | |
14592 | middle, and the two halves are placed at locations far apart in | |
14593 | memory.'' The traceback table has this property, since it | |
14594 | includes the offset from the start of the function to the | |
4d30c363 MM |
14595 | traceback table itself. |
14596 | ||
14597 | System V.4 Powerpc's (and the embedded ABI derived from it) use a | |
b6c9286a | 14598 | different traceback table. */ |
57ac7be9 AM |
14599 | if (DEFAULT_ABI == ABI_AIX && ! flag_inhibit_size_directive |
14600 | && rs6000_traceback != traceback_none) | |
9b30bae2 | 14601 | { |
69c75916 | 14602 | const char *fname = NULL; |
3ac88239 | 14603 | const char *language_string = lang_hooks.name; |
6041bf2f | 14604 | int fixed_parms = 0, float_parms = 0, parm_info = 0; |
314fc5a9 | 14605 | int i; |
57ac7be9 AM |
14606 | int optional_tbtab; |
14607 | ||
14608 | if (rs6000_traceback == traceback_full) | |
14609 | optional_tbtab = 1; | |
14610 | else if (rs6000_traceback == traceback_part) | |
14611 | optional_tbtab = 0; | |
14612 | else | |
14613 | optional_tbtab = !optimize_size && !TARGET_ELF; | |
314fc5a9 | 14614 | |
69c75916 AM |
14615 | if (optional_tbtab) |
14616 | { | |
14617 | fname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0); | |
14618 | while (*fname == '.') /* V.4 encodes . in the name */ | |
14619 | fname++; | |
14620 | ||
14621 | /* Need label immediately before tbtab, so we can compute | |
14622 | its offset from the function start. */ | |
14623 | ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT"); | |
14624 | ASM_OUTPUT_LABEL (file, fname); | |
14625 | } | |
314fc5a9 ILT |
14626 | |
14627 | /* The .tbtab pseudo-op can only be used for the first eight | |
14628 | expressions, since it can't handle the possibly variable | |
14629 | length fields that follow. However, if you omit the optional | |
14630 | fields, the assembler outputs zeros for all optional fields | |
14631 | anyways, giving each variable length field is minimum length | |
14632 | (as defined in sys/debug.h). Thus we can not use the .tbtab | |
14633 | pseudo-op at all. */ | |
14634 | ||
14635 | /* An all-zero word flags the start of the tbtab, for debuggers | |
14636 | that have to find it by searching forward from the entry | |
14637 | point or from the current pc. */ | |
19d2d16f | 14638 | fputs ("\t.long 0\n", file); |
314fc5a9 ILT |
14639 | |
14640 | /* Tbtab format type. Use format type 0. */ | |
19d2d16f | 14641 | fputs ("\t.byte 0,", file); |
314fc5a9 | 14642 | |
5fc921c1 DE |
14643 | /* Language type. Unfortunately, there does not seem to be any |
14644 | official way to discover the language being compiled, so we | |
14645 | use language_string. | |
14646 | C is 0. Fortran is 1. Pascal is 2. Ada is 3. C++ is 9. | |
14647 | Java is 13. Objective-C is 14. */ | |
14648 | if (! strcmp (language_string, "GNU C")) | |
314fc5a9 | 14649 | i = 0; |
6de9cd9a DN |
14650 | else if (! strcmp (language_string, "GNU F77") |
14651 | || ! strcmp (language_string, "GNU F95")) | |
314fc5a9 | 14652 | i = 1; |
8b83775b | 14653 | else if (! strcmp (language_string, "GNU Pascal")) |
314fc5a9 | 14654 | i = 2; |
5fc921c1 DE |
14655 | else if (! strcmp (language_string, "GNU Ada")) |
14656 | i = 3; | |
314fc5a9 ILT |
14657 | else if (! strcmp (language_string, "GNU C++")) |
14658 | i = 9; | |
9517ead8 AG |
14659 | else if (! strcmp (language_string, "GNU Java")) |
14660 | i = 13; | |
5fc921c1 DE |
14661 | else if (! strcmp (language_string, "GNU Objective-C")) |
14662 | i = 14; | |
314fc5a9 ILT |
14663 | else |
14664 | abort (); | |
14665 | fprintf (file, "%d,", i); | |
14666 | ||
14667 | /* 8 single bit fields: global linkage (not set for C extern linkage, | |
14668 | apparently a PL/I convention?), out-of-line epilogue/prologue, offset | |
14669 | from start of procedure stored in tbtab, internal function, function | |
14670 | has controlled storage, function has no toc, function uses fp, | |
14671 | function logs/aborts fp operations. */ | |
14672 | /* Assume that fp operations are used if any fp reg must be saved. */ | |
6041bf2f DE |
14673 | fprintf (file, "%d,", |
14674 | (optional_tbtab << 5) | ((info->first_fp_reg_save != 64) << 1)); | |
314fc5a9 ILT |
14675 | |
14676 | /* 6 bitfields: function is interrupt handler, name present in | |
14677 | proc table, function calls alloca, on condition directives | |
14678 | (controls stack walks, 3 bits), saves condition reg, saves | |
14679 | link reg. */ | |
14680 | /* The `function calls alloca' bit seems to be set whenever reg 31 is | |
14681 | set up as a frame pointer, even when there is no alloca call. */ | |
14682 | fprintf (file, "%d,", | |
6041bf2f DE |
14683 | ((optional_tbtab << 6) |
14684 | | ((optional_tbtab & frame_pointer_needed) << 5) | |
14685 | | (info->cr_save_p << 1) | |
14686 | | (info->lr_save_p))); | |
314fc5a9 | 14687 | |
6041bf2f | 14688 | /* 3 bitfields: saves backchain, fixup code, number of fpr saved |
314fc5a9 ILT |
14689 | (6 bits). */ |
14690 | fprintf (file, "%d,", | |
4697a36c | 14691 | (info->push_p << 7) | (64 - info->first_fp_reg_save)); |
314fc5a9 ILT |
14692 | |
14693 | /* 2 bitfields: spare bits (2 bits), number of gpr saved (6 bits). */ | |
14694 | fprintf (file, "%d,", (32 - first_reg_to_save ())); | |
14695 | ||
6041bf2f DE |
14696 | if (optional_tbtab) |
14697 | { | |
14698 | /* Compute the parameter info from the function decl argument | |
14699 | list. */ | |
14700 | tree decl; | |
14701 | int next_parm_info_bit = 31; | |
314fc5a9 | 14702 | |
6041bf2f DE |
14703 | for (decl = DECL_ARGUMENTS (current_function_decl); |
14704 | decl; decl = TREE_CHAIN (decl)) | |
14705 | { | |
14706 | rtx parameter = DECL_INCOMING_RTL (decl); | |
14707 | enum machine_mode mode = GET_MODE (parameter); | |
314fc5a9 | 14708 | |
6041bf2f DE |
14709 | if (GET_CODE (parameter) == REG) |
14710 | { | |
14711 | if (GET_MODE_CLASS (mode) == MODE_FLOAT) | |
14712 | { | |
14713 | int bits; | |
14714 | ||
14715 | float_parms++; | |
14716 | ||
14717 | if (mode == SFmode) | |
14718 | bits = 0x2; | |
fcce224d | 14719 | else if (mode == DFmode || mode == TFmode) |
6041bf2f DE |
14720 | bits = 0x3; |
14721 | else | |
14722 | abort (); | |
14723 | ||
14724 | /* If only one bit will fit, don't or in this entry. */ | |
14725 | if (next_parm_info_bit > 0) | |
14726 | parm_info |= (bits << (next_parm_info_bit - 1)); | |
14727 | next_parm_info_bit -= 2; | |
14728 | } | |
14729 | else | |
14730 | { | |
14731 | fixed_parms += ((GET_MODE_SIZE (mode) | |
14732 | + (UNITS_PER_WORD - 1)) | |
14733 | / UNITS_PER_WORD); | |
14734 | next_parm_info_bit -= 1; | |
14735 | } | |
14736 | } | |
14737 | } | |
14738 | } | |
314fc5a9 ILT |
14739 | |
14740 | /* Number of fixed point parameters. */ | |
14741 | /* This is actually the number of words of fixed point parameters; thus | |
14742 | an 8 byte struct counts as 2; and thus the maximum value is 8. */ | |
14743 | fprintf (file, "%d,", fixed_parms); | |
14744 | ||
14745 | /* 2 bitfields: number of floating point parameters (7 bits), parameters | |
14746 | all on stack. */ | |
14747 | /* This is actually the number of fp registers that hold parameters; | |
14748 | and thus the maximum value is 13. */ | |
14749 | /* Set parameters on stack bit if parameters are not in their original | |
14750 | registers, regardless of whether they are on the stack? Xlc | |
14751 | seems to set the bit when not optimizing. */ | |
14752 | fprintf (file, "%d\n", ((float_parms << 1) | (! optimize))); | |
14753 | ||
6041bf2f DE |
14754 | if (! optional_tbtab) |
14755 | return; | |
14756 | ||
314fc5a9 ILT |
14757 | /* Optional fields follow. Some are variable length. */ |
14758 | ||
14759 | /* Parameter types, left adjusted bit fields: 0 fixed, 10 single float, | |
14760 | 11 double float. */ | |
14761 | /* There is an entry for each parameter in a register, in the order that | |
14762 | they occur in the parameter list. Any intervening arguments on the | |
14763 | stack are ignored. If the list overflows a long (max possible length | |
14764 | 34 bits) then completely leave off all elements that don't fit. */ | |
14765 | /* Only emit this long if there was at least one parameter. */ | |
14766 | if (fixed_parms || float_parms) | |
14767 | fprintf (file, "\t.long %d\n", parm_info); | |
14768 | ||
14769 | /* Offset from start of code to tb table. */ | |
19d2d16f | 14770 | fputs ("\t.long ", file); |
314fc5a9 | 14771 | ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT"); |
85b776df AM |
14772 | if (TARGET_AIX) |
14773 | RS6000_OUTPUT_BASENAME (file, fname); | |
14774 | else | |
14775 | assemble_name (file, fname); | |
14776 | putc ('-', file); | |
14777 | rs6000_output_function_entry (file, fname); | |
19d2d16f | 14778 | putc ('\n', file); |
314fc5a9 ILT |
14779 | |
14780 | /* Interrupt handler mask. */ | |
14781 | /* Omit this long, since we never set the interrupt handler bit | |
14782 | above. */ | |
14783 | ||
14784 | /* Number of CTL (controlled storage) anchors. */ | |
14785 | /* Omit this long, since the has_ctl bit is never set above. */ | |
14786 | ||
14787 | /* Displacement into stack of each CTL anchor. */ | |
14788 | /* Omit this list of longs, because there are no CTL anchors. */ | |
14789 | ||
14790 | /* Length of function name. */ | |
69c75916 AM |
14791 | if (*fname == '*') |
14792 | ++fname; | |
296b8152 | 14793 | fprintf (file, "\t.short %d\n", (int) strlen (fname)); |
314fc5a9 ILT |
14794 | |
14795 | /* Function name. */ | |
14796 | assemble_string (fname, strlen (fname)); | |
14797 | ||
14798 | /* Register for alloca automatic storage; this is always reg 31. | |
14799 | Only emit this if the alloca bit was set above. */ | |
14800 | if (frame_pointer_needed) | |
19d2d16f | 14801 | fputs ("\t.byte 31\n", file); |
b1765bde DE |
14802 | |
14803 | fputs ("\t.align 2\n", file); | |
9b30bae2 | 14804 | } |
9878760c | 14805 | } |
17167fd8 | 14806 | \f |
a4f6c312 SS |
14807 | /* A C compound statement that outputs the assembler code for a thunk |
14808 | function, used to implement C++ virtual function calls with | |
14809 | multiple inheritance. The thunk acts as a wrapper around a virtual | |
14810 | function, adjusting the implicit object parameter before handing | |
14811 | control off to the real function. | |
14812 | ||
14813 | First, emit code to add the integer DELTA to the location that | |
14814 | contains the incoming first argument. Assume that this argument | |
14815 | contains a pointer, and is the one used to pass the `this' pointer | |
14816 | in C++. This is the incoming argument *before* the function | |
14817 | prologue, e.g. `%o0' on a sparc. The addition must preserve the | |
14818 | values of all other incoming arguments. | |
17167fd8 MM |
14819 | |
14820 | After the addition, emit code to jump to FUNCTION, which is a | |
a4f6c312 SS |
14821 | `FUNCTION_DECL'. This is a direct pure jump, not a call, and does |
14822 | not touch the return address. Hence returning from FUNCTION will | |
14823 | return to whoever called the current `thunk'. | |
17167fd8 | 14824 | |
a4f6c312 SS |
14825 | The effect must be as if FUNCTION had been called directly with the |
14826 | adjusted first argument. This macro is responsible for emitting | |
14827 | all of the code for a thunk function; output_function_prologue() | |
14828 | and output_function_epilogue() are not invoked. | |
17167fd8 | 14829 | |
a4f6c312 SS |
14830 | The THUNK_FNDECL is redundant. (DELTA and FUNCTION have already |
14831 | been extracted from it.) It might possibly be useful on some | |
14832 | targets, but probably not. | |
17167fd8 | 14833 | |
a4f6c312 SS |
14834 | If you do not define this macro, the target-independent code in the |
14835 | C++ frontend will generate a less efficient heavyweight thunk that | |
14836 | calls FUNCTION instead of jumping to it. The generic approach does | |
14837 | not support varargs. */ | |
17167fd8 | 14838 | |
3961e8fe | 14839 | static void |
f676971a EC |
14840 | rs6000_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED, |
14841 | HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset, | |
a2369ed3 | 14842 | tree function) |
17167fd8 | 14843 | { |
5b71a4e7 | 14844 | rtx this, insn, funexp; |
17167fd8 | 14845 | |
5b71a4e7 | 14846 | reload_completed = 1; |
fe3ad572 | 14847 | epilogue_completed = 1; |
5b71a4e7 | 14848 | no_new_pseudos = 1; |
6429e3be | 14849 | reset_block_changes (); |
56a7189a | 14850 | |
5b71a4e7 | 14851 | /* Mark the end of the (empty) prologue. */ |
2e040219 | 14852 | emit_note (NOTE_INSN_PROLOGUE_END); |
17167fd8 | 14853 | |
5b71a4e7 DE |
14854 | /* Find the "this" pointer. If the function returns a structure, |
14855 | the structure return pointer is in r3. */ | |
61f71b34 | 14856 | if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function)) |
5b71a4e7 | 14857 | this = gen_rtx_REG (Pmode, 4); |
56a7189a | 14858 | else |
5b71a4e7 | 14859 | this = gen_rtx_REG (Pmode, 3); |
17167fd8 | 14860 | |
5b71a4e7 DE |
14861 | /* Apply the constant offset, if required. */ |
14862 | if (delta) | |
14863 | { | |
14864 | rtx delta_rtx = GEN_INT (delta); | |
14865 | emit_insn (TARGET_32BIT | |
14866 | ? gen_addsi3 (this, this, delta_rtx) | |
14867 | : gen_adddi3 (this, this, delta_rtx)); | |
17167fd8 MM |
14868 | } |
14869 | ||
5b71a4e7 DE |
14870 | /* Apply the offset from the vtable, if required. */ |
14871 | if (vcall_offset) | |
17167fd8 | 14872 | { |
5b71a4e7 DE |
14873 | rtx vcall_offset_rtx = GEN_INT (vcall_offset); |
14874 | rtx tmp = gen_rtx_REG (Pmode, 12); | |
17167fd8 | 14875 | |
5b71a4e7 | 14876 | emit_move_insn (tmp, gen_rtx_MEM (Pmode, this)); |
eeff9307 JJ |
14877 | if (((unsigned HOST_WIDE_INT) vcall_offset) + 0x8000 >= 0x10000) |
14878 | { | |
14879 | emit_insn (TARGET_32BIT | |
14880 | ? gen_addsi3 (tmp, tmp, vcall_offset_rtx) | |
14881 | : gen_adddi3 (tmp, tmp, vcall_offset_rtx)); | |
14882 | emit_move_insn (tmp, gen_rtx_MEM (Pmode, tmp)); | |
14883 | } | |
14884 | else | |
14885 | { | |
14886 | rtx loc = gen_rtx_PLUS (Pmode, tmp, vcall_offset_rtx); | |
14887 | ||
14888 | emit_move_insn (tmp, gen_rtx_MEM (Pmode, loc)); | |
14889 | } | |
5b71a4e7 DE |
14890 | emit_insn (TARGET_32BIT |
14891 | ? gen_addsi3 (this, this, tmp) | |
14892 | : gen_adddi3 (this, this, tmp)); | |
17167fd8 MM |
14893 | } |
14894 | ||
5b71a4e7 DE |
14895 | /* Generate a tail call to the target function. */ |
14896 | if (!TREE_USED (function)) | |
14897 | { | |
14898 | assemble_external (function); | |
14899 | TREE_USED (function) = 1; | |
14900 | } | |
14901 | funexp = XEXP (DECL_RTL (function), 0); | |
5b71a4e7 | 14902 | funexp = gen_rtx_MEM (FUNCTION_MODE, funexp); |
ee890fe2 SS |
14903 | |
14904 | #if TARGET_MACHO | |
ab82a49f | 14905 | if (MACHOPIC_INDIRECT) |
5b71a4e7 | 14906 | funexp = machopic_indirect_call_target (funexp); |
ee890fe2 | 14907 | #endif |
5b71a4e7 DE |
14908 | |
14909 | /* gen_sibcall expects reload to convert scratch pseudo to LR so we must | |
14910 | generate sibcall RTL explicitly to avoid constraint abort. */ | |
14911 | insn = emit_call_insn ( | |
14912 | gen_rtx_PARALLEL (VOIDmode, | |
14913 | gen_rtvec (4, | |
14914 | gen_rtx_CALL (VOIDmode, | |
14915 | funexp, const0_rtx), | |
14916 | gen_rtx_USE (VOIDmode, const0_rtx), | |
14917 | gen_rtx_USE (VOIDmode, | |
14918 | gen_rtx_REG (SImode, | |
14919 | LINK_REGISTER_REGNUM)), | |
14920 | gen_rtx_RETURN (VOIDmode)))); | |
14921 | SIBLING_CALL_P (insn) = 1; | |
14922 | emit_barrier (); | |
14923 | ||
14924 | /* Run just enough of rest_of_compilation to get the insns emitted. | |
14925 | There's not really enough bulk here to make other passes such as | |
14926 | instruction scheduling worth while. Note that use_thunk calls | |
14927 | assemble_start_function and assemble_end_function. */ | |
14928 | insn = get_insns (); | |
a2855205 | 14929 | insn_locators_initialize (); |
5b71a4e7 DE |
14930 | shorten_branches (insn); |
14931 | final_start_function (insn, file, 1); | |
14932 | final (insn, file, 1, 0); | |
14933 | final_end_function (); | |
14934 | ||
14935 | reload_completed = 0; | |
fe3ad572 | 14936 | epilogue_completed = 0; |
5b71a4e7 | 14937 | no_new_pseudos = 0; |
9ebbca7d | 14938 | } |
9ebbca7d GK |
14939 | \f |
14940 | /* A quick summary of the various types of 'constant-pool tables' | |
14941 | under PowerPC: | |
14942 | ||
f676971a | 14943 | Target Flags Name One table per |
9ebbca7d GK |
14944 | AIX (none) AIX TOC object file |
14945 | AIX -mfull-toc AIX TOC object file | |
14946 | AIX -mminimal-toc AIX minimal TOC translation unit | |
14947 | SVR4/EABI (none) SVR4 SDATA object file | |
14948 | SVR4/EABI -fpic SVR4 pic object file | |
14949 | SVR4/EABI -fPIC SVR4 PIC translation unit | |
14950 | SVR4/EABI -mrelocatable EABI TOC function | |
14951 | SVR4/EABI -maix AIX TOC object file | |
f676971a | 14952 | SVR4/EABI -maix -mminimal-toc |
9ebbca7d GK |
14953 | AIX minimal TOC translation unit |
14954 | ||
14955 | Name Reg. Set by entries contains: | |
14956 | made by addrs? fp? sum? | |
14957 | ||
14958 | AIX TOC 2 crt0 as Y option option | |
14959 | AIX minimal TOC 30 prolog gcc Y Y option | |
14960 | SVR4 SDATA 13 crt0 gcc N Y N | |
14961 | SVR4 pic 30 prolog ld Y not yet N | |
14962 | SVR4 PIC 30 prolog gcc Y option option | |
14963 | EABI TOC 30 prolog gcc Y option option | |
14964 | ||
14965 | */ | |
14966 | ||
9ebbca7d GK |
14967 | /* Hash functions for the hash table. */ |
14968 | ||
14969 | static unsigned | |
a2369ed3 | 14970 | rs6000_hash_constant (rtx k) |
9ebbca7d | 14971 | { |
46b33600 RH |
14972 | enum rtx_code code = GET_CODE (k); |
14973 | enum machine_mode mode = GET_MODE (k); | |
14974 | unsigned result = (code << 3) ^ mode; | |
14975 | const char *format; | |
14976 | int flen, fidx; | |
f676971a | 14977 | |
46b33600 RH |
14978 | format = GET_RTX_FORMAT (code); |
14979 | flen = strlen (format); | |
14980 | fidx = 0; | |
9ebbca7d | 14981 | |
46b33600 RH |
14982 | switch (code) |
14983 | { | |
14984 | case LABEL_REF: | |
14985 | return result * 1231 + (unsigned) INSN_UID (XEXP (k, 0)); | |
14986 | ||
14987 | case CONST_DOUBLE: | |
14988 | if (mode != VOIDmode) | |
14989 | return real_hash (CONST_DOUBLE_REAL_VALUE (k)) * result; | |
14990 | flen = 2; | |
14991 | break; | |
14992 | ||
14993 | case CODE_LABEL: | |
14994 | fidx = 3; | |
14995 | break; | |
14996 | ||
14997 | default: | |
14998 | break; | |
14999 | } | |
9ebbca7d GK |
15000 | |
15001 | for (; fidx < flen; fidx++) | |
15002 | switch (format[fidx]) | |
15003 | { | |
15004 | case 's': | |
15005 | { | |
15006 | unsigned i, len; | |
15007 | const char *str = XSTR (k, fidx); | |
15008 | len = strlen (str); | |
15009 | result = result * 613 + len; | |
15010 | for (i = 0; i < len; i++) | |
15011 | result = result * 613 + (unsigned) str[i]; | |
17167fd8 MM |
15012 | break; |
15013 | } | |
9ebbca7d GK |
15014 | case 'u': |
15015 | case 'e': | |
15016 | result = result * 1231 + rs6000_hash_constant (XEXP (k, fidx)); | |
15017 | break; | |
15018 | case 'i': | |
15019 | case 'n': | |
15020 | result = result * 613 + (unsigned) XINT (k, fidx); | |
15021 | break; | |
15022 | case 'w': | |
15023 | if (sizeof (unsigned) >= sizeof (HOST_WIDE_INT)) | |
15024 | result = result * 613 + (unsigned) XWINT (k, fidx); | |
15025 | else | |
15026 | { | |
15027 | size_t i; | |
15028 | for (i = 0; i < sizeof(HOST_WIDE_INT)/sizeof(unsigned); i++) | |
15029 | result = result * 613 + (unsigned) (XWINT (k, fidx) | |
15030 | >> CHAR_BIT * i); | |
15031 | } | |
15032 | break; | |
09501938 DE |
15033 | case '0': |
15034 | break; | |
9ebbca7d | 15035 | default: |
a4f6c312 | 15036 | abort (); |
9ebbca7d | 15037 | } |
46b33600 | 15038 | |
9ebbca7d GK |
15039 | return result; |
15040 | } | |
15041 | ||
15042 | static unsigned | |
a2369ed3 | 15043 | toc_hash_function (const void *hash_entry) |
9ebbca7d | 15044 | { |
f676971a | 15045 | const struct toc_hash_struct *thc = |
a9098fd0 GK |
15046 | (const struct toc_hash_struct *) hash_entry; |
15047 | return rs6000_hash_constant (thc->key) ^ thc->key_mode; | |
9ebbca7d GK |
15048 | } |
15049 | ||
15050 | /* Compare H1 and H2 for equivalence. */ | |
15051 | ||
15052 | static int | |
a2369ed3 | 15053 | toc_hash_eq (const void *h1, const void *h2) |
9ebbca7d GK |
15054 | { |
15055 | rtx r1 = ((const struct toc_hash_struct *) h1)->key; | |
15056 | rtx r2 = ((const struct toc_hash_struct *) h2)->key; | |
15057 | ||
a9098fd0 GK |
15058 | if (((const struct toc_hash_struct *) h1)->key_mode |
15059 | != ((const struct toc_hash_struct *) h2)->key_mode) | |
15060 | return 0; | |
15061 | ||
5692c7bc | 15062 | return rtx_equal_p (r1, r2); |
9ebbca7d GK |
15063 | } |
15064 | ||
28e510bd MM |
15065 | /* These are the names given by the C++ front-end to vtables, and |
15066 | vtable-like objects. Ideally, this logic should not be here; | |
15067 | instead, there should be some programmatic way of inquiring as | |
15068 | to whether or not an object is a vtable. */ | |
15069 | ||
15070 | #define VTABLE_NAME_P(NAME) \ | |
15071 | (strncmp ("_vt.", name, strlen("_vt.")) == 0 \ | |
15072 | || strncmp ("_ZTV", name, strlen ("_ZTV")) == 0 \ | |
15073 | || strncmp ("_ZTT", name, strlen ("_ZTT")) == 0 \ | |
26be75db | 15074 | || strncmp ("_ZTI", name, strlen ("_ZTI")) == 0 \ |
f676971a | 15075 | || strncmp ("_ZTC", name, strlen ("_ZTC")) == 0) |
28e510bd MM |
15076 | |
15077 | void | |
a2369ed3 | 15078 | rs6000_output_symbol_ref (FILE *file, rtx x) |
28e510bd MM |
15079 | { |
15080 | /* Currently C++ toc references to vtables can be emitted before it | |
15081 | is decided whether the vtable is public or private. If this is | |
15082 | the case, then the linker will eventually complain that there is | |
f676971a | 15083 | a reference to an unknown section. Thus, for vtables only, |
28e510bd MM |
15084 | we emit the TOC reference to reference the symbol and not the |
15085 | section. */ | |
15086 | const char *name = XSTR (x, 0); | |
54ee9799 | 15087 | |
f676971a | 15088 | if (VTABLE_NAME_P (name)) |
54ee9799 DE |
15089 | { |
15090 | RS6000_OUTPUT_BASENAME (file, name); | |
15091 | } | |
15092 | else | |
15093 | assemble_name (file, name); | |
28e510bd MM |
15094 | } |
15095 | ||
a4f6c312 SS |
15096 | /* Output a TOC entry. We derive the entry name from what is being |
15097 | written. */ | |
9878760c RK |
15098 | |
15099 | void | |
a2369ed3 | 15100 | output_toc (FILE *file, rtx x, int labelno, enum machine_mode mode) |
9878760c RK |
15101 | { |
15102 | char buf[256]; | |
3cce094d | 15103 | const char *name = buf; |
ec940faa | 15104 | const char *real_name; |
9878760c RK |
15105 | rtx base = x; |
15106 | int offset = 0; | |
15107 | ||
4697a36c MM |
15108 | if (TARGET_NO_TOC) |
15109 | abort (); | |
15110 | ||
9ebbca7d GK |
15111 | /* When the linker won't eliminate them, don't output duplicate |
15112 | TOC entries (this happens on AIX if there is any kind of TOC, | |
17211ab5 GK |
15113 | and on SVR4 under -fPIC or -mrelocatable). Don't do this for |
15114 | CODE_LABELs. */ | |
15115 | if (TARGET_TOC && GET_CODE (x) != LABEL_REF) | |
9ebbca7d GK |
15116 | { |
15117 | struct toc_hash_struct *h; | |
15118 | void * * found; | |
f676971a | 15119 | |
17211ab5 | 15120 | /* Create toc_hash_table. This can't be done at OVERRIDE_OPTIONS |
c4ad648e | 15121 | time because GGC is not initialized at that point. */ |
17211ab5 | 15122 | if (toc_hash_table == NULL) |
f676971a | 15123 | toc_hash_table = htab_create_ggc (1021, toc_hash_function, |
17211ab5 GK |
15124 | toc_hash_eq, NULL); |
15125 | ||
9ebbca7d GK |
15126 | h = ggc_alloc (sizeof (*h)); |
15127 | h->key = x; | |
a9098fd0 | 15128 | h->key_mode = mode; |
9ebbca7d | 15129 | h->labelno = labelno; |
f676971a | 15130 | |
9ebbca7d GK |
15131 | found = htab_find_slot (toc_hash_table, h, 1); |
15132 | if (*found == NULL) | |
15133 | *found = h; | |
f676971a | 15134 | else /* This is indeed a duplicate. |
9ebbca7d GK |
15135 | Set this label equal to that label. */ |
15136 | { | |
15137 | fputs ("\t.set ", file); | |
15138 | ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC"); | |
15139 | fprintf (file, "%d,", labelno); | |
15140 | ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC"); | |
f676971a | 15141 | fprintf (file, "%d\n", ((*(const struct toc_hash_struct **) |
9ebbca7d GK |
15142 | found)->labelno)); |
15143 | return; | |
15144 | } | |
15145 | } | |
15146 | ||
15147 | /* If we're going to put a double constant in the TOC, make sure it's | |
15148 | aligned properly when strict alignment is on. */ | |
ff1720ed RK |
15149 | if (GET_CODE (x) == CONST_DOUBLE |
15150 | && STRICT_ALIGNMENT | |
a9098fd0 | 15151 | && GET_MODE_BITSIZE (mode) >= 64 |
ff1720ed RK |
15152 | && ! (TARGET_NO_FP_IN_TOC && ! TARGET_MINIMAL_TOC)) { |
15153 | ASM_OUTPUT_ALIGN (file, 3); | |
15154 | } | |
15155 | ||
4977bab6 | 15156 | (*targetm.asm_out.internal_label) (file, "LC", labelno); |
9878760c | 15157 | |
37c37a57 RK |
15158 | /* Handle FP constants specially. Note that if we have a minimal |
15159 | TOC, things we put here aren't actually in the TOC, so we can allow | |
15160 | FP constants. */ | |
fcce224d DE |
15161 | if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == TFmode) |
15162 | { | |
15163 | REAL_VALUE_TYPE rv; | |
15164 | long k[4]; | |
15165 | ||
15166 | REAL_VALUE_FROM_CONST_DOUBLE (rv, x); | |
15167 | REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv, k); | |
15168 | ||
15169 | if (TARGET_64BIT) | |
15170 | { | |
15171 | if (TARGET_MINIMAL_TOC) | |
15172 | fputs (DOUBLE_INT_ASM_OP, file); | |
15173 | else | |
15174 | fprintf (file, "\t.tc FT_%lx_%lx_%lx_%lx[TC],", | |
15175 | k[0] & 0xffffffff, k[1] & 0xffffffff, | |
15176 | k[2] & 0xffffffff, k[3] & 0xffffffff); | |
15177 | fprintf (file, "0x%lx%08lx,0x%lx%08lx\n", | |
15178 | k[0] & 0xffffffff, k[1] & 0xffffffff, | |
15179 | k[2] & 0xffffffff, k[3] & 0xffffffff); | |
15180 | return; | |
15181 | } | |
15182 | else | |
15183 | { | |
15184 | if (TARGET_MINIMAL_TOC) | |
15185 | fputs ("\t.long ", file); | |
15186 | else | |
15187 | fprintf (file, "\t.tc FT_%lx_%lx_%lx_%lx[TC],", | |
15188 | k[0] & 0xffffffff, k[1] & 0xffffffff, | |
15189 | k[2] & 0xffffffff, k[3] & 0xffffffff); | |
15190 | fprintf (file, "0x%lx,0x%lx,0x%lx,0x%lx\n", | |
15191 | k[0] & 0xffffffff, k[1] & 0xffffffff, | |
15192 | k[2] & 0xffffffff, k[3] & 0xffffffff); | |
15193 | return; | |
15194 | } | |
15195 | } | |
15196 | else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == DFmode) | |
9878760c | 15197 | { |
042259f2 DE |
15198 | REAL_VALUE_TYPE rv; |
15199 | long k[2]; | |
0adc764e | 15200 | |
042259f2 DE |
15201 | REAL_VALUE_FROM_CONST_DOUBLE (rv, x); |
15202 | REAL_VALUE_TO_TARGET_DOUBLE (rv, k); | |
31bfaa0b | 15203 | |
13ded975 DE |
15204 | if (TARGET_64BIT) |
15205 | { | |
15206 | if (TARGET_MINIMAL_TOC) | |
2bfcf297 | 15207 | fputs (DOUBLE_INT_ASM_OP, file); |
13ded975 | 15208 | else |
2f0552b6 AM |
15209 | fprintf (file, "\t.tc FD_%lx_%lx[TC],", |
15210 | k[0] & 0xffffffff, k[1] & 0xffffffff); | |
15211 | fprintf (file, "0x%lx%08lx\n", | |
15212 | k[0] & 0xffffffff, k[1] & 0xffffffff); | |
13ded975 DE |
15213 | return; |
15214 | } | |
1875cc88 | 15215 | else |
13ded975 DE |
15216 | { |
15217 | if (TARGET_MINIMAL_TOC) | |
2bfcf297 | 15218 | fputs ("\t.long ", file); |
13ded975 | 15219 | else |
2f0552b6 AM |
15220 | fprintf (file, "\t.tc FD_%lx_%lx[TC],", |
15221 | k[0] & 0xffffffff, k[1] & 0xffffffff); | |
15222 | fprintf (file, "0x%lx,0x%lx\n", | |
15223 | k[0] & 0xffffffff, k[1] & 0xffffffff); | |
13ded975 DE |
15224 | return; |
15225 | } | |
9878760c | 15226 | } |
a9098fd0 | 15227 | else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == SFmode) |
9878760c | 15228 | { |
042259f2 DE |
15229 | REAL_VALUE_TYPE rv; |
15230 | long l; | |
9878760c | 15231 | |
042259f2 DE |
15232 | REAL_VALUE_FROM_CONST_DOUBLE (rv, x); |
15233 | REAL_VALUE_TO_TARGET_SINGLE (rv, l); | |
15234 | ||
31bfaa0b DE |
15235 | if (TARGET_64BIT) |
15236 | { | |
15237 | if (TARGET_MINIMAL_TOC) | |
2bfcf297 | 15238 | fputs (DOUBLE_INT_ASM_OP, file); |
31bfaa0b | 15239 | else |
2f0552b6 AM |
15240 | fprintf (file, "\t.tc FS_%lx[TC],", l & 0xffffffff); |
15241 | fprintf (file, "0x%lx00000000\n", l & 0xffffffff); | |
31bfaa0b DE |
15242 | return; |
15243 | } | |
042259f2 | 15244 | else |
31bfaa0b DE |
15245 | { |
15246 | if (TARGET_MINIMAL_TOC) | |
2bfcf297 | 15247 | fputs ("\t.long ", file); |
31bfaa0b | 15248 | else |
2f0552b6 AM |
15249 | fprintf (file, "\t.tc FS_%lx[TC],", l & 0xffffffff); |
15250 | fprintf (file, "0x%lx\n", l & 0xffffffff); | |
31bfaa0b DE |
15251 | return; |
15252 | } | |
042259f2 | 15253 | } |
f176e826 | 15254 | else if (GET_MODE (x) == VOIDmode |
a9098fd0 | 15255 | && (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE)) |
042259f2 | 15256 | { |
e2c953b6 | 15257 | unsigned HOST_WIDE_INT low; |
042259f2 DE |
15258 | HOST_WIDE_INT high; |
15259 | ||
15260 | if (GET_CODE (x) == CONST_DOUBLE) | |
15261 | { | |
15262 | low = CONST_DOUBLE_LOW (x); | |
15263 | high = CONST_DOUBLE_HIGH (x); | |
15264 | } | |
15265 | else | |
15266 | #if HOST_BITS_PER_WIDE_INT == 32 | |
15267 | { | |
15268 | low = INTVAL (x); | |
0858c623 | 15269 | high = (low & 0x80000000) ? ~0 : 0; |
042259f2 DE |
15270 | } |
15271 | #else | |
15272 | { | |
c4ad648e AM |
15273 | low = INTVAL (x) & 0xffffffff; |
15274 | high = (HOST_WIDE_INT) INTVAL (x) >> 32; | |
042259f2 DE |
15275 | } |
15276 | #endif | |
9878760c | 15277 | |
a9098fd0 GK |
15278 | /* TOC entries are always Pmode-sized, but since this |
15279 | is a bigendian machine then if we're putting smaller | |
15280 | integer constants in the TOC we have to pad them. | |
15281 | (This is still a win over putting the constants in | |
15282 | a separate constant pool, because then we'd have | |
02a4ec28 FS |
15283 | to have both a TOC entry _and_ the actual constant.) |
15284 | ||
15285 | For a 32-bit target, CONST_INT values are loaded and shifted | |
15286 | entirely within `low' and can be stored in one TOC entry. */ | |
15287 | ||
15288 | if (TARGET_64BIT && POINTER_SIZE < GET_MODE_BITSIZE (mode)) | |
a9098fd0 | 15289 | abort ();/* It would be easy to make this work, but it doesn't now. */ |
02a4ec28 FS |
15290 | |
15291 | if (POINTER_SIZE > GET_MODE_BITSIZE (mode)) | |
fb52d8de AM |
15292 | { |
15293 | #if HOST_BITS_PER_WIDE_INT == 32 | |
15294 | lshift_double (low, high, POINTER_SIZE - GET_MODE_BITSIZE (mode), | |
15295 | POINTER_SIZE, &low, &high, 0); | |
15296 | #else | |
15297 | low |= high << 32; | |
15298 | low <<= POINTER_SIZE - GET_MODE_BITSIZE (mode); | |
15299 | high = (HOST_WIDE_INT) low >> 32; | |
15300 | low &= 0xffffffff; | |
15301 | #endif | |
15302 | } | |
a9098fd0 | 15303 | |
13ded975 DE |
15304 | if (TARGET_64BIT) |
15305 | { | |
15306 | if (TARGET_MINIMAL_TOC) | |
2bfcf297 | 15307 | fputs (DOUBLE_INT_ASM_OP, file); |
13ded975 | 15308 | else |
2f0552b6 AM |
15309 | fprintf (file, "\t.tc ID_%lx_%lx[TC],", |
15310 | (long) high & 0xffffffff, (long) low & 0xffffffff); | |
15311 | fprintf (file, "0x%lx%08lx\n", | |
15312 | (long) high & 0xffffffff, (long) low & 0xffffffff); | |
13ded975 DE |
15313 | return; |
15314 | } | |
1875cc88 | 15315 | else |
13ded975 | 15316 | { |
02a4ec28 FS |
15317 | if (POINTER_SIZE < GET_MODE_BITSIZE (mode)) |
15318 | { | |
15319 | if (TARGET_MINIMAL_TOC) | |
2bfcf297 | 15320 | fputs ("\t.long ", file); |
02a4ec28 | 15321 | else |
2bfcf297 | 15322 | fprintf (file, "\t.tc ID_%lx_%lx[TC],", |
2f0552b6 AM |
15323 | (long) high & 0xffffffff, (long) low & 0xffffffff); |
15324 | fprintf (file, "0x%lx,0x%lx\n", | |
15325 | (long) high & 0xffffffff, (long) low & 0xffffffff); | |
02a4ec28 | 15326 | } |
13ded975 | 15327 | else |
02a4ec28 FS |
15328 | { |
15329 | if (TARGET_MINIMAL_TOC) | |
2bfcf297 | 15330 | fputs ("\t.long ", file); |
02a4ec28 | 15331 | else |
2f0552b6 AM |
15332 | fprintf (file, "\t.tc IS_%lx[TC],", (long) low & 0xffffffff); |
15333 | fprintf (file, "0x%lx\n", (long) low & 0xffffffff); | |
02a4ec28 | 15334 | } |
13ded975 DE |
15335 | return; |
15336 | } | |
9878760c RK |
15337 | } |
15338 | ||
15339 | if (GET_CODE (x) == CONST) | |
15340 | { | |
2bfcf297 DB |
15341 | if (GET_CODE (XEXP (x, 0)) != PLUS) |
15342 | abort (); | |
15343 | ||
9878760c RK |
15344 | base = XEXP (XEXP (x, 0), 0); |
15345 | offset = INTVAL (XEXP (XEXP (x, 0), 1)); | |
15346 | } | |
f676971a | 15347 | |
9878760c RK |
15348 | if (GET_CODE (base) == SYMBOL_REF) |
15349 | name = XSTR (base, 0); | |
15350 | else if (GET_CODE (base) == LABEL_REF) | |
15351 | ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (XEXP (base, 0))); | |
15352 | else if (GET_CODE (base) == CODE_LABEL) | |
15353 | ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (base)); | |
15354 | else | |
15355 | abort (); | |
15356 | ||
772c5265 | 15357 | real_name = (*targetm.strip_name_encoding) (name); |
1875cc88 | 15358 | if (TARGET_MINIMAL_TOC) |
2bfcf297 | 15359 | fputs (TARGET_32BIT ? "\t.long " : DOUBLE_INT_ASM_OP, file); |
1875cc88 JW |
15360 | else |
15361 | { | |
b6c9286a | 15362 | fprintf (file, "\t.tc %s", real_name); |
9878760c | 15363 | |
1875cc88 JW |
15364 | if (offset < 0) |
15365 | fprintf (file, ".N%d", - offset); | |
15366 | else if (offset) | |
15367 | fprintf (file, ".P%d", offset); | |
9878760c | 15368 | |
19d2d16f | 15369 | fputs ("[TC],", file); |
1875cc88 | 15370 | } |
581bc4de MM |
15371 | |
15372 | /* Currently C++ toc references to vtables can be emitted before it | |
15373 | is decided whether the vtable is public or private. If this is | |
15374 | the case, then the linker will eventually complain that there is | |
15375 | a TOC reference to an unknown section. Thus, for vtables only, | |
15376 | we emit the TOC reference to reference the symbol and not the | |
15377 | section. */ | |
28e510bd | 15378 | if (VTABLE_NAME_P (name)) |
581bc4de | 15379 | { |
54ee9799 | 15380 | RS6000_OUTPUT_BASENAME (file, name); |
581bc4de MM |
15381 | if (offset < 0) |
15382 | fprintf (file, "%d", offset); | |
15383 | else if (offset > 0) | |
15384 | fprintf (file, "+%d", offset); | |
15385 | } | |
15386 | else | |
15387 | output_addr_const (file, x); | |
19d2d16f | 15388 | putc ('\n', file); |
9878760c RK |
15389 | } |
15390 | \f | |
15391 | /* Output an assembler pseudo-op to write an ASCII string of N characters | |
15392 | starting at P to FILE. | |
15393 | ||
15394 | On the RS/6000, we have to do this using the .byte operation and | |
15395 | write out special characters outside the quoted string. | |
15396 | Also, the assembler is broken; very long strings are truncated, | |
a4f6c312 | 15397 | so we must artificially break them up early. */ |
9878760c RK |
15398 | |
15399 | void | |
a2369ed3 | 15400 | output_ascii (FILE *file, const char *p, int n) |
9878760c RK |
15401 | { |
15402 | char c; | |
15403 | int i, count_string; | |
d330fd93 KG |
15404 | const char *for_string = "\t.byte \""; |
15405 | const char *for_decimal = "\t.byte "; | |
15406 | const char *to_close = NULL; | |
9878760c RK |
15407 | |
15408 | count_string = 0; | |
15409 | for (i = 0; i < n; i++) | |
15410 | { | |
15411 | c = *p++; | |
15412 | if (c >= ' ' && c < 0177) | |
15413 | { | |
15414 | if (for_string) | |
15415 | fputs (for_string, file); | |
15416 | putc (c, file); | |
15417 | ||
15418 | /* Write two quotes to get one. */ | |
15419 | if (c == '"') | |
15420 | { | |
15421 | putc (c, file); | |
15422 | ++count_string; | |
15423 | } | |
15424 | ||
15425 | for_string = NULL; | |
15426 | for_decimal = "\"\n\t.byte "; | |
15427 | to_close = "\"\n"; | |
15428 | ++count_string; | |
15429 | ||
15430 | if (count_string >= 512) | |
15431 | { | |
15432 | fputs (to_close, file); | |
15433 | ||
15434 | for_string = "\t.byte \""; | |
15435 | for_decimal = "\t.byte "; | |
15436 | to_close = NULL; | |
15437 | count_string = 0; | |
15438 | } | |
15439 | } | |
15440 | else | |
15441 | { | |
15442 | if (for_decimal) | |
15443 | fputs (for_decimal, file); | |
15444 | fprintf (file, "%d", c); | |
15445 | ||
15446 | for_string = "\n\t.byte \""; | |
15447 | for_decimal = ", "; | |
15448 | to_close = "\n"; | |
15449 | count_string = 0; | |
15450 | } | |
15451 | } | |
15452 | ||
15453 | /* Now close the string if we have written one. Then end the line. */ | |
15454 | if (to_close) | |
9ebbca7d | 15455 | fputs (to_close, file); |
9878760c RK |
15456 | } |
15457 | \f | |
15458 | /* Generate a unique section name for FILENAME for a section type | |
15459 | represented by SECTION_DESC. Output goes into BUF. | |
15460 | ||
15461 | SECTION_DESC can be any string, as long as it is different for each | |
15462 | possible section type. | |
15463 | ||
15464 | We name the section in the same manner as xlc. The name begins with an | |
15465 | underscore followed by the filename (after stripping any leading directory | |
11e5fe42 RK |
15466 | names) with the last period replaced by the string SECTION_DESC. If |
15467 | FILENAME does not contain a period, SECTION_DESC is appended to the end of | |
15468 | the name. */ | |
9878760c RK |
15469 | |
15470 | void | |
f676971a | 15471 | rs6000_gen_section_name (char **buf, const char *filename, |
c4ad648e | 15472 | const char *section_desc) |
9878760c | 15473 | { |
9ebbca7d | 15474 | const char *q, *after_last_slash, *last_period = 0; |
9878760c RK |
15475 | char *p; |
15476 | int len; | |
9878760c RK |
15477 | |
15478 | after_last_slash = filename; | |
15479 | for (q = filename; *q; q++) | |
11e5fe42 RK |
15480 | { |
15481 | if (*q == '/') | |
15482 | after_last_slash = q + 1; | |
15483 | else if (*q == '.') | |
15484 | last_period = q; | |
15485 | } | |
9878760c | 15486 | |
11e5fe42 | 15487 | len = strlen (after_last_slash) + strlen (section_desc) + 2; |
6d9f628e | 15488 | *buf = (char *) xmalloc (len); |
9878760c RK |
15489 | |
15490 | p = *buf; | |
15491 | *p++ = '_'; | |
15492 | ||
15493 | for (q = after_last_slash; *q; q++) | |
15494 | { | |
11e5fe42 | 15495 | if (q == last_period) |
c4ad648e | 15496 | { |
9878760c RK |
15497 | strcpy (p, section_desc); |
15498 | p += strlen (section_desc); | |
e3981aab | 15499 | break; |
c4ad648e | 15500 | } |
9878760c | 15501 | |
e9a780ec | 15502 | else if (ISALNUM (*q)) |
c4ad648e | 15503 | *p++ = *q; |
9878760c RK |
15504 | } |
15505 | ||
11e5fe42 | 15506 | if (last_period == 0) |
9878760c RK |
15507 | strcpy (p, section_desc); |
15508 | else | |
15509 | *p = '\0'; | |
15510 | } | |
e165f3f0 | 15511 | \f |
a4f6c312 | 15512 | /* Emit profile function. */ |
411707f4 | 15513 | |
411707f4 | 15514 | void |
a2369ed3 | 15515 | output_profile_hook (int labelno ATTRIBUTE_UNUSED) |
411707f4 | 15516 | { |
ffcfcb5f AM |
15517 | if (TARGET_PROFILE_KERNEL) |
15518 | return; | |
15519 | ||
8480e480 CC |
15520 | if (DEFAULT_ABI == ABI_AIX) |
15521 | { | |
9739c90c JJ |
15522 | #ifndef NO_PROFILE_COUNTERS |
15523 | # define NO_PROFILE_COUNTERS 0 | |
15524 | #endif | |
f676971a | 15525 | if (NO_PROFILE_COUNTERS) |
9739c90c JJ |
15526 | emit_library_call (init_one_libfunc (RS6000_MCOUNT), 0, VOIDmode, 0); |
15527 | else | |
15528 | { | |
15529 | char buf[30]; | |
15530 | const char *label_name; | |
15531 | rtx fun; | |
411707f4 | 15532 | |
9739c90c JJ |
15533 | ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno); |
15534 | label_name = (*targetm.strip_name_encoding) (ggc_strdup (buf)); | |
15535 | fun = gen_rtx_SYMBOL_REF (Pmode, label_name); | |
411707f4 | 15536 | |
9739c90c JJ |
15537 | emit_library_call (init_one_libfunc (RS6000_MCOUNT), 0, VOIDmode, 1, |
15538 | fun, Pmode); | |
15539 | } | |
8480e480 | 15540 | } |
ee890fe2 SS |
15541 | else if (DEFAULT_ABI == ABI_DARWIN) |
15542 | { | |
d5fa86ba | 15543 | const char *mcount_name = RS6000_MCOUNT; |
ee890fe2 SS |
15544 | int caller_addr_regno = LINK_REGISTER_REGNUM; |
15545 | ||
15546 | /* Be conservative and always set this, at least for now. */ | |
15547 | current_function_uses_pic_offset_table = 1; | |
15548 | ||
15549 | #if TARGET_MACHO | |
15550 | /* For PIC code, set up a stub and collect the caller's address | |
15551 | from r0, which is where the prologue puts it. */ | |
11abc112 MM |
15552 | if (MACHOPIC_INDIRECT |
15553 | && current_function_uses_pic_offset_table) | |
15554 | caller_addr_regno = 0; | |
ee890fe2 SS |
15555 | #endif |
15556 | emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mcount_name), | |
15557 | 0, VOIDmode, 1, | |
15558 | gen_rtx_REG (Pmode, caller_addr_regno), Pmode); | |
15559 | } | |
411707f4 CC |
15560 | } |
15561 | ||
a4f6c312 | 15562 | /* Write function profiler code. */ |
e165f3f0 RK |
15563 | |
15564 | void | |
a2369ed3 | 15565 | output_function_profiler (FILE *file, int labelno) |
e165f3f0 | 15566 | { |
3daf36a4 | 15567 | char buf[100]; |
09eeeacb | 15568 | int save_lr = 8; |
e165f3f0 | 15569 | |
38c1f2d7 | 15570 | switch (DEFAULT_ABI) |
3daf36a4 | 15571 | { |
38c1f2d7 MM |
15572 | default: |
15573 | abort (); | |
15574 | ||
15575 | case ABI_V4: | |
09eeeacb | 15576 | save_lr = 4; |
09eeeacb AM |
15577 | if (!TARGET_32BIT) |
15578 | { | |
15579 | warning ("no profiling of 64-bit code for this ABI"); | |
15580 | return; | |
15581 | } | |
ffcfcb5f | 15582 | ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno); |
38c1f2d7 MM |
15583 | fprintf (file, "\tmflr %s\n", reg_names[0]); |
15584 | if (flag_pic == 1) | |
15585 | { | |
dfdfa60f | 15586 | fputs ("\tbl _GLOBAL_OFFSET_TABLE_@local-4\n", file); |
09eeeacb AM |
15587 | asm_fprintf (file, "\t{st|stw} %s,%d(%s)\n", |
15588 | reg_names[0], save_lr, reg_names[1]); | |
17167fd8 | 15589 | asm_fprintf (file, "\tmflr %s\n", reg_names[12]); |
dfdfa60f | 15590 | asm_fprintf (file, "\t{l|lwz} %s,", reg_names[0]); |
38c1f2d7 | 15591 | assemble_name (file, buf); |
17167fd8 | 15592 | asm_fprintf (file, "@got(%s)\n", reg_names[12]); |
38c1f2d7 | 15593 | } |
9ebbca7d | 15594 | else if (flag_pic > 1) |
38c1f2d7 | 15595 | { |
09eeeacb AM |
15596 | asm_fprintf (file, "\t{st|stw} %s,%d(%s)\n", |
15597 | reg_names[0], save_lr, reg_names[1]); | |
9ebbca7d GK |
15598 | /* Now, we need to get the address of the label. */ |
15599 | fputs ("\tbl 1f\n\t.long ", file); | |
034e84c4 | 15600 | assemble_name (file, buf); |
9ebbca7d GK |
15601 | fputs ("-.\n1:", file); |
15602 | asm_fprintf (file, "\tmflr %s\n", reg_names[11]); | |
f676971a | 15603 | asm_fprintf (file, "\t{l|lwz} %s,0(%s)\n", |
9ebbca7d GK |
15604 | reg_names[0], reg_names[11]); |
15605 | asm_fprintf (file, "\t{cax|add} %s,%s,%s\n", | |
15606 | reg_names[0], reg_names[0], reg_names[11]); | |
38c1f2d7 | 15607 | } |
38c1f2d7 MM |
15608 | else |
15609 | { | |
17167fd8 | 15610 | asm_fprintf (file, "\t{liu|lis} %s,", reg_names[12]); |
38c1f2d7 | 15611 | assemble_name (file, buf); |
dfdfa60f | 15612 | fputs ("@ha\n", file); |
09eeeacb AM |
15613 | asm_fprintf (file, "\t{st|stw} %s,%d(%s)\n", |
15614 | reg_names[0], save_lr, reg_names[1]); | |
a260abc9 | 15615 | asm_fprintf (file, "\t{cal|la} %s,", reg_names[0]); |
38c1f2d7 | 15616 | assemble_name (file, buf); |
17167fd8 | 15617 | asm_fprintf (file, "@l(%s)\n", reg_names[12]); |
38c1f2d7 MM |
15618 | } |
15619 | ||
50d440bc | 15620 | /* ABI_V4 saves the static chain reg with ASM_OUTPUT_REG_PUSH. */ |
3b6ce0af DE |
15621 | fprintf (file, "\tbl %s%s\n", |
15622 | RS6000_MCOUNT, flag_pic ? "@plt" : ""); | |
38c1f2d7 MM |
15623 | break; |
15624 | ||
15625 | case ABI_AIX: | |
ee890fe2 | 15626 | case ABI_DARWIN: |
ffcfcb5f AM |
15627 | if (!TARGET_PROFILE_KERNEL) |
15628 | { | |
a3c9585f | 15629 | /* Don't do anything, done in output_profile_hook (). */ |
ffcfcb5f AM |
15630 | } |
15631 | else | |
15632 | { | |
15633 | if (TARGET_32BIT) | |
15634 | abort (); | |
15635 | ||
15636 | asm_fprintf (file, "\tmflr %s\n", reg_names[0]); | |
15637 | asm_fprintf (file, "\tstd %s,16(%s)\n", reg_names[0], reg_names[1]); | |
15638 | ||
6de9cd9a | 15639 | if (cfun->static_chain_decl != NULL) |
ffcfcb5f AM |
15640 | { |
15641 | asm_fprintf (file, "\tstd %s,24(%s)\n", | |
15642 | reg_names[STATIC_CHAIN_REGNUM], reg_names[1]); | |
15643 | fprintf (file, "\tbl %s\n", RS6000_MCOUNT); | |
15644 | asm_fprintf (file, "\tld %s,24(%s)\n", | |
15645 | reg_names[STATIC_CHAIN_REGNUM], reg_names[1]); | |
15646 | } | |
15647 | else | |
15648 | fprintf (file, "\tbl %s\n", RS6000_MCOUNT); | |
15649 | } | |
38c1f2d7 MM |
15650 | break; |
15651 | } | |
e165f3f0 | 15652 | } |
a251ffd0 | 15653 | |
b54cf83a | 15654 | \f |
b54cf83a DE |
15655 | /* Power4 load update and store update instructions are cracked into a |
15656 | load or store and an integer insn which are executed in the same cycle. | |
15657 | Branches have their own dispatch slot which does not count against the | |
15658 | GCC issue rate, but it changes the program flow so there are no other | |
15659 | instructions to issue in this cycle. */ | |
15660 | ||
15661 | static int | |
f676971a EC |
15662 | rs6000_variable_issue (FILE *stream ATTRIBUTE_UNUSED, |
15663 | int verbose ATTRIBUTE_UNUSED, | |
a2369ed3 | 15664 | rtx insn, int more) |
b54cf83a DE |
15665 | { |
15666 | if (GET_CODE (PATTERN (insn)) == USE | |
15667 | || GET_CODE (PATTERN (insn)) == CLOBBER) | |
15668 | return more; | |
15669 | ||
ec507f2d | 15670 | if (rs6000_sched_groups) |
b54cf83a | 15671 | { |
cbe26ab8 | 15672 | if (is_microcoded_insn (insn)) |
c4ad648e | 15673 | return 0; |
cbe26ab8 | 15674 | else if (is_cracked_insn (insn)) |
c4ad648e | 15675 | return more > 2 ? more - 2 : 0; |
b54cf83a | 15676 | } |
165b263e DE |
15677 | |
15678 | return more - 1; | |
b54cf83a DE |
15679 | } |
15680 | ||
a251ffd0 TG |
15681 | /* Adjust the cost of a scheduling dependency. Return the new cost of |
15682 | a dependency LINK or INSN on DEP_INSN. COST is the current cost. */ | |
15683 | ||
c237e94a | 15684 | static int |
0a4f0294 | 15685 | rs6000_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost) |
a251ffd0 TG |
15686 | { |
15687 | if (! recog_memoized (insn)) | |
15688 | return 0; | |
15689 | ||
15690 | if (REG_NOTE_KIND (link) != 0) | |
15691 | return 0; | |
15692 | ||
15693 | if (REG_NOTE_KIND (link) == 0) | |
15694 | { | |
ed947a96 DJ |
15695 | /* Data dependency; DEP_INSN writes a register that INSN reads |
15696 | some cycles later. */ | |
15697 | switch (get_attr_type (insn)) | |
15698 | { | |
15699 | case TYPE_JMPREG: | |
309323c2 | 15700 | /* Tell the first scheduling pass about the latency between |
ed947a96 DJ |
15701 | a mtctr and bctr (and mtlr and br/blr). The first |
15702 | scheduling pass will not know about this latency since | |
15703 | the mtctr instruction, which has the latency associated | |
15704 | to it, will be generated by reload. */ | |
309323c2 | 15705 | return TARGET_POWER ? 5 : 4; |
ed947a96 DJ |
15706 | case TYPE_BRANCH: |
15707 | /* Leave some extra cycles between a compare and its | |
15708 | dependent branch, to inhibit expensive mispredicts. */ | |
309323c2 DE |
15709 | if ((rs6000_cpu_attr == CPU_PPC603 |
15710 | || rs6000_cpu_attr == CPU_PPC604 | |
15711 | || rs6000_cpu_attr == CPU_PPC604E | |
15712 | || rs6000_cpu_attr == CPU_PPC620 | |
15713 | || rs6000_cpu_attr == CPU_PPC630 | |
15714 | || rs6000_cpu_attr == CPU_PPC750 | |
15715 | || rs6000_cpu_attr == CPU_PPC7400 | |
15716 | || rs6000_cpu_attr == CPU_PPC7450 | |
ec507f2d DE |
15717 | || rs6000_cpu_attr == CPU_POWER4 |
15718 | || rs6000_cpu_attr == CPU_POWER5) | |
ed947a96 DJ |
15719 | && recog_memoized (dep_insn) |
15720 | && (INSN_CODE (dep_insn) >= 0) | |
b54cf83a DE |
15721 | && (get_attr_type (dep_insn) == TYPE_CMP |
15722 | || get_attr_type (dep_insn) == TYPE_COMPARE | |
ed947a96 | 15723 | || get_attr_type (dep_insn) == TYPE_DELAYED_COMPARE |
9259f3b0 DE |
15724 | || get_attr_type (dep_insn) == TYPE_IMUL_COMPARE |
15725 | || get_attr_type (dep_insn) == TYPE_LMUL_COMPARE | |
ed947a96 | 15726 | || get_attr_type (dep_insn) == TYPE_FPCOMPARE |
b54cf83a DE |
15727 | || get_attr_type (dep_insn) == TYPE_CR_LOGICAL |
15728 | || get_attr_type (dep_insn) == TYPE_DELAYED_CR)) | |
ed947a96 DJ |
15729 | return cost + 2; |
15730 | default: | |
15731 | break; | |
15732 | } | |
a251ffd0 TG |
15733 | /* Fall out to return default cost. */ |
15734 | } | |
15735 | ||
15736 | return cost; | |
15737 | } | |
b6c9286a | 15738 | |
cbe26ab8 | 15739 | /* The function returns a true if INSN is microcoded. |
839a4992 | 15740 | Return false otherwise. */ |
cbe26ab8 DN |
15741 | |
15742 | static bool | |
15743 | is_microcoded_insn (rtx insn) | |
15744 | { | |
15745 | if (!insn || !INSN_P (insn) | |
15746 | || GET_CODE (PATTERN (insn)) == USE | |
15747 | || GET_CODE (PATTERN (insn)) == CLOBBER) | |
15748 | return false; | |
15749 | ||
ec507f2d | 15750 | if (rs6000_sched_groups) |
cbe26ab8 DN |
15751 | { |
15752 | enum attr_type type = get_attr_type (insn); | |
15753 | if (type == TYPE_LOAD_EXT_U | |
15754 | || type == TYPE_LOAD_EXT_UX | |
15755 | || type == TYPE_LOAD_UX | |
15756 | || type == TYPE_STORE_UX | |
15757 | || type == TYPE_MFCR) | |
c4ad648e | 15758 | return true; |
cbe26ab8 DN |
15759 | } |
15760 | ||
15761 | return false; | |
15762 | } | |
15763 | ||
5c425df5 | 15764 | /* The function returns a nonzero value if INSN can be scheduled only |
cbe26ab8 DN |
15765 | as the first insn in a dispatch group ("dispatch-slot restricted"). |
15766 | In this case, the returned value indicates how many dispatch slots | |
15767 | the insn occupies (at the beginning of the group). | |
79ae11c4 DN |
15768 | Return 0 otherwise. */ |
15769 | ||
cbe26ab8 | 15770 | static int |
79ae11c4 DN |
15771 | is_dispatch_slot_restricted (rtx insn) |
15772 | { | |
15773 | enum attr_type type; | |
15774 | ||
ec507f2d | 15775 | if (!rs6000_sched_groups) |
79ae11c4 DN |
15776 | return 0; |
15777 | ||
15778 | if (!insn | |
15779 | || insn == NULL_RTX | |
15780 | || GET_CODE (insn) == NOTE | |
15781 | || GET_CODE (PATTERN (insn)) == USE | |
15782 | || GET_CODE (PATTERN (insn)) == CLOBBER) | |
15783 | return 0; | |
15784 | ||
15785 | type = get_attr_type (insn); | |
15786 | ||
ec507f2d DE |
15787 | switch (type) |
15788 | { | |
15789 | case TYPE_MFCR: | |
15790 | case TYPE_MFCRF: | |
15791 | case TYPE_MTCR: | |
15792 | case TYPE_DELAYED_CR: | |
15793 | case TYPE_CR_LOGICAL: | |
15794 | case TYPE_MTJMPR: | |
15795 | case TYPE_MFJMPR: | |
15796 | return 1; | |
15797 | case TYPE_IDIV: | |
15798 | case TYPE_LDIV: | |
15799 | return 2; | |
15800 | default: | |
15801 | if (rs6000_cpu == PROCESSOR_POWER5 | |
15802 | && is_cracked_insn (insn)) | |
15803 | return 2; | |
15804 | return 0; | |
15805 | } | |
79ae11c4 DN |
15806 | } |
15807 | ||
cbe26ab8 DN |
15808 | /* The function returns true if INSN is cracked into 2 instructions |
15809 | by the processor (and therefore occupies 2 issue slots). */ | |
15810 | ||
15811 | static bool | |
15812 | is_cracked_insn (rtx insn) | |
15813 | { | |
15814 | if (!insn || !INSN_P (insn) | |
15815 | || GET_CODE (PATTERN (insn)) == USE | |
15816 | || GET_CODE (PATTERN (insn)) == CLOBBER) | |
15817 | return false; | |
15818 | ||
ec507f2d | 15819 | if (rs6000_sched_groups) |
cbe26ab8 DN |
15820 | { |
15821 | enum attr_type type = get_attr_type (insn); | |
15822 | if (type == TYPE_LOAD_U || type == TYPE_STORE_U | |
c4ad648e AM |
15823 | || type == TYPE_FPLOAD_U || type == TYPE_FPSTORE_U |
15824 | || type == TYPE_FPLOAD_UX || type == TYPE_FPSTORE_UX | |
15825 | || type == TYPE_LOAD_EXT || type == TYPE_DELAYED_CR | |
15826 | || type == TYPE_COMPARE || type == TYPE_DELAYED_COMPARE | |
15827 | || type == TYPE_IMUL_COMPARE || type == TYPE_LMUL_COMPARE | |
15828 | || type == TYPE_IDIV || type == TYPE_LDIV | |
15829 | || type == TYPE_INSERT_WORD) | |
15830 | return true; | |
cbe26ab8 DN |
15831 | } |
15832 | ||
15833 | return false; | |
15834 | } | |
15835 | ||
15836 | /* The function returns true if INSN can be issued only from | |
a3c9585f | 15837 | the branch slot. */ |
cbe26ab8 DN |
15838 | |
15839 | static bool | |
15840 | is_branch_slot_insn (rtx insn) | |
15841 | { | |
15842 | if (!insn || !INSN_P (insn) | |
15843 | || GET_CODE (PATTERN (insn)) == USE | |
15844 | || GET_CODE (PATTERN (insn)) == CLOBBER) | |
15845 | return false; | |
15846 | ||
ec507f2d | 15847 | if (rs6000_sched_groups) |
cbe26ab8 DN |
15848 | { |
15849 | enum attr_type type = get_attr_type (insn); | |
15850 | if (type == TYPE_BRANCH || type == TYPE_JMPREG) | |
f676971a | 15851 | return true; |
cbe26ab8 DN |
15852 | return false; |
15853 | } | |
15854 | ||
15855 | return false; | |
15856 | } | |
79ae11c4 | 15857 | |
a4f6c312 | 15858 | /* A C statement (sans semicolon) to update the integer scheduling |
79ae11c4 DN |
15859 | priority INSN_PRIORITY (INSN). Increase the priority to execute the |
15860 | INSN earlier, reduce the priority to execute INSN later. Do not | |
a4f6c312 SS |
15861 | define this macro if you do not need to adjust the scheduling |
15862 | priorities of insns. */ | |
bef84347 | 15863 | |
c237e94a | 15864 | static int |
a2369ed3 | 15865 | rs6000_adjust_priority (rtx insn ATTRIBUTE_UNUSED, int priority) |
bef84347 | 15866 | { |
a4f6c312 SS |
15867 | /* On machines (like the 750) which have asymmetric integer units, |
15868 | where one integer unit can do multiply and divides and the other | |
15869 | can't, reduce the priority of multiply/divide so it is scheduled | |
15870 | before other integer operations. */ | |
bef84347 VM |
15871 | |
15872 | #if 0 | |
2c3c49de | 15873 | if (! INSN_P (insn)) |
bef84347 VM |
15874 | return priority; |
15875 | ||
15876 | if (GET_CODE (PATTERN (insn)) == USE) | |
15877 | return priority; | |
15878 | ||
15879 | switch (rs6000_cpu_attr) { | |
15880 | case CPU_PPC750: | |
15881 | switch (get_attr_type (insn)) | |
15882 | { | |
15883 | default: | |
15884 | break; | |
15885 | ||
15886 | case TYPE_IMUL: | |
15887 | case TYPE_IDIV: | |
3cb999d8 DE |
15888 | fprintf (stderr, "priority was %#x (%d) before adjustment\n", |
15889 | priority, priority); | |
bef84347 VM |
15890 | if (priority >= 0 && priority < 0x01000000) |
15891 | priority >>= 3; | |
15892 | break; | |
15893 | } | |
15894 | } | |
15895 | #endif | |
15896 | ||
79ae11c4 DN |
15897 | if (is_dispatch_slot_restricted (insn) |
15898 | && reload_completed | |
f676971a | 15899 | && current_sched_info->sched_max_insns_priority |
79ae11c4 DN |
15900 | && rs6000_sched_restricted_insns_priority) |
15901 | { | |
15902 | ||
c4ad648e AM |
15903 | /* Prioritize insns that can be dispatched only in the first |
15904 | dispatch slot. */ | |
79ae11c4 | 15905 | if (rs6000_sched_restricted_insns_priority == 1) |
f676971a EC |
15906 | /* Attach highest priority to insn. This means that in |
15907 | haifa-sched.c:ready_sort(), dispatch-slot restriction considerations | |
79ae11c4 | 15908 | precede 'priority' (critical path) considerations. */ |
f676971a | 15909 | return current_sched_info->sched_max_insns_priority; |
79ae11c4 | 15910 | else if (rs6000_sched_restricted_insns_priority == 2) |
f676971a | 15911 | /* Increase priority of insn by a minimal amount. This means that in |
c4ad648e AM |
15912 | haifa-sched.c:ready_sort(), only 'priority' (critical path) |
15913 | considerations precede dispatch-slot restriction considerations. */ | |
f676971a EC |
15914 | return (priority + 1); |
15915 | } | |
79ae11c4 | 15916 | |
bef84347 VM |
15917 | return priority; |
15918 | } | |
15919 | ||
a4f6c312 SS |
15920 | /* Return how many instructions the machine can issue per cycle. */ |
15921 | ||
c237e94a | 15922 | static int |
863d938c | 15923 | rs6000_issue_rate (void) |
b6c9286a | 15924 | { |
3317bab1 DE |
15925 | /* Use issue rate of 1 for first scheduling pass to decrease degradation. */ |
15926 | if (!reload_completed) | |
15927 | return 1; | |
15928 | ||
b6c9286a | 15929 | switch (rs6000_cpu_attr) { |
3cb999d8 DE |
15930 | case CPU_RIOS1: /* ? */ |
15931 | case CPU_RS64A: | |
15932 | case CPU_PPC601: /* ? */ | |
ed947a96 | 15933 | case CPU_PPC7450: |
3cb999d8 | 15934 | return 3; |
b54cf83a | 15935 | case CPU_PPC440: |
b6c9286a | 15936 | case CPU_PPC603: |
bef84347 | 15937 | case CPU_PPC750: |
ed947a96 | 15938 | case CPU_PPC7400: |
be12c2b0 | 15939 | case CPU_PPC8540: |
f676971a | 15940 | return 2; |
3cb999d8 | 15941 | case CPU_RIOS2: |
b6c9286a | 15942 | case CPU_PPC604: |
19684119 | 15943 | case CPU_PPC604E: |
b6c9286a | 15944 | case CPU_PPC620: |
3cb999d8 | 15945 | case CPU_PPC630: |
b6c9286a | 15946 | return 4; |
cbe26ab8 | 15947 | case CPU_POWER4: |
ec507f2d | 15948 | case CPU_POWER5: |
cbe26ab8 | 15949 | return 5; |
b6c9286a MM |
15950 | default: |
15951 | return 1; | |
15952 | } | |
15953 | } | |
15954 | ||
be12c2b0 VM |
15955 | /* Return how many instructions to look ahead for better insn |
15956 | scheduling. */ | |
15957 | ||
15958 | static int | |
863d938c | 15959 | rs6000_use_sched_lookahead (void) |
be12c2b0 VM |
15960 | { |
15961 | if (rs6000_cpu_attr == CPU_PPC8540) | |
15962 | return 4; | |
15963 | return 0; | |
15964 | } | |
15965 | ||
569fa502 DN |
15966 | /* Determine is PAT refers to memory. */ |
15967 | ||
15968 | static bool | |
15969 | is_mem_ref (rtx pat) | |
15970 | { | |
15971 | const char * fmt; | |
15972 | int i, j; | |
15973 | bool ret = false; | |
15974 | ||
15975 | if (GET_CODE (pat) == MEM) | |
15976 | return true; | |
15977 | ||
15978 | /* Recursively process the pattern. */ | |
15979 | fmt = GET_RTX_FORMAT (GET_CODE (pat)); | |
15980 | ||
15981 | for (i = GET_RTX_LENGTH (GET_CODE (pat)) - 1; i >= 0 && !ret; i--) | |
15982 | { | |
15983 | if (fmt[i] == 'e') | |
15984 | ret |= is_mem_ref (XEXP (pat, i)); | |
15985 | else if (fmt[i] == 'E') | |
15986 | for (j = XVECLEN (pat, i) - 1; j >= 0; j--) | |
15987 | ret |= is_mem_ref (XVECEXP (pat, i, j)); | |
15988 | } | |
15989 | ||
15990 | return ret; | |
15991 | } | |
15992 | ||
15993 | /* Determine if PAT is a PATTERN of a load insn. */ | |
f676971a | 15994 | |
569fa502 DN |
15995 | static bool |
15996 | is_load_insn1 (rtx pat) | |
15997 | { | |
15998 | if (!pat || pat == NULL_RTX) | |
15999 | return false; | |
16000 | ||
16001 | if (GET_CODE (pat) == SET) | |
16002 | return is_mem_ref (SET_SRC (pat)); | |
16003 | ||
16004 | if (GET_CODE (pat) == PARALLEL) | |
16005 | { | |
16006 | int i; | |
16007 | ||
16008 | for (i = 0; i < XVECLEN (pat, 0); i++) | |
16009 | if (is_load_insn1 (XVECEXP (pat, 0, i))) | |
16010 | return true; | |
16011 | } | |
16012 | ||
16013 | return false; | |
16014 | } | |
16015 | ||
16016 | /* Determine if INSN loads from memory. */ | |
16017 | ||
16018 | static bool | |
16019 | is_load_insn (rtx insn) | |
16020 | { | |
16021 | if (!insn || !INSN_P (insn)) | |
16022 | return false; | |
16023 | ||
16024 | if (GET_CODE (insn) == CALL_INSN) | |
16025 | return false; | |
16026 | ||
16027 | return is_load_insn1 (PATTERN (insn)); | |
16028 | } | |
16029 | ||
16030 | /* Determine if PAT is a PATTERN of a store insn. */ | |
16031 | ||
16032 | static bool | |
16033 | is_store_insn1 (rtx pat) | |
16034 | { | |
16035 | if (!pat || pat == NULL_RTX) | |
16036 | return false; | |
16037 | ||
16038 | if (GET_CODE (pat) == SET) | |
16039 | return is_mem_ref (SET_DEST (pat)); | |
16040 | ||
16041 | if (GET_CODE (pat) == PARALLEL) | |
16042 | { | |
16043 | int i; | |
16044 | ||
16045 | for (i = 0; i < XVECLEN (pat, 0); i++) | |
16046 | if (is_store_insn1 (XVECEXP (pat, 0, i))) | |
16047 | return true; | |
16048 | } | |
16049 | ||
16050 | return false; | |
16051 | } | |
16052 | ||
16053 | /* Determine if INSN stores to memory. */ | |
16054 | ||
16055 | static bool | |
16056 | is_store_insn (rtx insn) | |
16057 | { | |
16058 | if (!insn || !INSN_P (insn)) | |
16059 | return false; | |
16060 | ||
16061 | return is_store_insn1 (PATTERN (insn)); | |
16062 | } | |
16063 | ||
16064 | /* Returns whether the dependence between INSN and NEXT is considered | |
16065 | costly by the given target. */ | |
16066 | ||
16067 | static bool | |
c4ad648e AM |
16068 | rs6000_is_costly_dependence (rtx insn, rtx next, rtx link, int cost, |
16069 | int distance) | |
f676971a | 16070 | { |
569fa502 | 16071 | /* If the flag is not enbled - no dependence is considered costly; |
f676971a | 16072 | allow all dependent insns in the same group. |
569fa502 DN |
16073 | This is the most aggressive option. */ |
16074 | if (rs6000_sched_costly_dep == no_dep_costly) | |
16075 | return false; | |
16076 | ||
f676971a | 16077 | /* If the flag is set to 1 - a dependence is always considered costly; |
569fa502 DN |
16078 | do not allow dependent instructions in the same group. |
16079 | This is the most conservative option. */ | |
16080 | if (rs6000_sched_costly_dep == all_deps_costly) | |
f676971a | 16081 | return true; |
569fa502 | 16082 | |
f676971a EC |
16083 | if (rs6000_sched_costly_dep == store_to_load_dep_costly |
16084 | && is_load_insn (next) | |
569fa502 DN |
16085 | && is_store_insn (insn)) |
16086 | /* Prevent load after store in the same group. */ | |
16087 | return true; | |
16088 | ||
16089 | if (rs6000_sched_costly_dep == true_store_to_load_dep_costly | |
f676971a | 16090 | && is_load_insn (next) |
569fa502 DN |
16091 | && is_store_insn (insn) |
16092 | && (!link || (int) REG_NOTE_KIND (link) == 0)) | |
c4ad648e AM |
16093 | /* Prevent load after store in the same group if it is a true |
16094 | dependence. */ | |
569fa502 | 16095 | return true; |
f676971a EC |
16096 | |
16097 | /* The flag is set to X; dependences with latency >= X are considered costly, | |
569fa502 DN |
16098 | and will not be scheduled in the same group. */ |
16099 | if (rs6000_sched_costly_dep <= max_dep_latency | |
16100 | && ((cost - distance) >= (int)rs6000_sched_costly_dep)) | |
16101 | return true; | |
16102 | ||
16103 | return false; | |
16104 | } | |
16105 | ||
f676971a | 16106 | /* Return the next insn after INSN that is found before TAIL is reached, |
cbe26ab8 DN |
16107 | skipping any "non-active" insns - insns that will not actually occupy |
16108 | an issue slot. Return NULL_RTX if such an insn is not found. */ | |
16109 | ||
16110 | static rtx | |
16111 | get_next_active_insn (rtx insn, rtx tail) | |
16112 | { | |
16113 | rtx next_insn; | |
16114 | ||
16115 | if (!insn || insn == tail) | |
16116 | return NULL_RTX; | |
16117 | ||
16118 | next_insn = NEXT_INSN (insn); | |
16119 | ||
16120 | while (next_insn | |
16121 | && next_insn != tail | |
16122 | && (GET_CODE(next_insn) == NOTE | |
16123 | || GET_CODE (PATTERN (next_insn)) == USE | |
16124 | || GET_CODE (PATTERN (next_insn)) == CLOBBER)) | |
16125 | { | |
16126 | next_insn = NEXT_INSN (next_insn); | |
16127 | } | |
16128 | ||
16129 | if (!next_insn || next_insn == tail) | |
16130 | return NULL_RTX; | |
16131 | ||
16132 | return next_insn; | |
16133 | } | |
16134 | ||
839a4992 | 16135 | /* Return whether the presence of INSN causes a dispatch group termination |
cbe26ab8 DN |
16136 | of group WHICH_GROUP. |
16137 | ||
16138 | If WHICH_GROUP == current_group, this function will return true if INSN | |
16139 | causes the termination of the current group (i.e, the dispatch group to | |
16140 | which INSN belongs). This means that INSN will be the last insn in the | |
16141 | group it belongs to. | |
16142 | ||
16143 | If WHICH_GROUP == previous_group, this function will return true if INSN | |
16144 | causes the termination of the previous group (i.e, the dispatch group that | |
16145 | precedes the group to which INSN belongs). This means that INSN will be | |
16146 | the first insn in the group it belongs to). */ | |
16147 | ||
16148 | static bool | |
16149 | insn_terminates_group_p (rtx insn, enum group_termination which_group) | |
16150 | { | |
16151 | enum attr_type type; | |
16152 | ||
16153 | if (! insn) | |
16154 | return false; | |
569fa502 | 16155 | |
cbe26ab8 DN |
16156 | type = get_attr_type (insn); |
16157 | ||
16158 | if (is_microcoded_insn (insn)) | |
16159 | return true; | |
16160 | ||
16161 | if (which_group == current_group) | |
16162 | { | |
16163 | if (is_branch_slot_insn (insn)) | |
c4ad648e | 16164 | return true; |
cbe26ab8 DN |
16165 | return false; |
16166 | } | |
16167 | else if (which_group == previous_group) | |
16168 | { | |
16169 | if (is_dispatch_slot_restricted (insn)) | |
c4ad648e | 16170 | return true; |
cbe26ab8 DN |
16171 | return false; |
16172 | } | |
16173 | ||
16174 | return false; | |
16175 | } | |
16176 | ||
839a4992 | 16177 | /* Return true if it is recommended to keep NEXT_INSN "far" (in a separate |
cbe26ab8 DN |
16178 | dispatch group) from the insns in GROUP_INSNS. Return false otherwise. */ |
16179 | ||
16180 | static bool | |
16181 | is_costly_group (rtx *group_insns, rtx next_insn) | |
16182 | { | |
16183 | int i; | |
16184 | rtx link; | |
16185 | int cost; | |
16186 | int issue_rate = rs6000_issue_rate (); | |
16187 | ||
16188 | for (i = 0; i < issue_rate; i++) | |
16189 | { | |
16190 | rtx insn = group_insns[i]; | |
16191 | if (!insn) | |
c4ad648e | 16192 | continue; |
cbe26ab8 | 16193 | for (link = INSN_DEPEND (insn); link != 0; link = XEXP (link, 1)) |
c4ad648e AM |
16194 | { |
16195 | rtx next = XEXP (link, 0); | |
16196 | if (next == next_insn) | |
16197 | { | |
16198 | cost = insn_cost (insn, link, next_insn); | |
16199 | if (rs6000_is_costly_dependence (insn, next_insn, link, cost, 0)) | |
16200 | return true; | |
16201 | } | |
16202 | } | |
cbe26ab8 DN |
16203 | } |
16204 | ||
16205 | return false; | |
16206 | } | |
16207 | ||
f676971a | 16208 | /* Utility of the function redefine_groups. |
cbe26ab8 DN |
16209 | Check if it is too costly to schedule NEXT_INSN together with GROUP_INSNS |
16210 | in the same dispatch group. If so, insert nops before NEXT_INSN, in order | |
16211 | to keep it "far" (in a separate group) from GROUP_INSNS, following | |
16212 | one of the following schemes, depending on the value of the flag | |
16213 | -minsert_sched_nops = X: | |
16214 | (1) X == sched_finish_regroup_exact: insert exactly as many nops as needed | |
839a4992 | 16215 | in order to force NEXT_INSN into a separate group. |
f676971a EC |
16216 | (2) X < sched_finish_regroup_exact: insert exactly X nops. |
16217 | GROUP_END, CAN_ISSUE_MORE and GROUP_COUNT record the state after nop | |
cbe26ab8 DN |
16218 | insertion (has a group just ended, how many vacant issue slots remain in the |
16219 | last group, and how many dispatch groups were encountered so far). */ | |
16220 | ||
f676971a | 16221 | static int |
c4ad648e AM |
16222 | force_new_group (int sched_verbose, FILE *dump, rtx *group_insns, |
16223 | rtx next_insn, bool *group_end, int can_issue_more, | |
16224 | int *group_count) | |
cbe26ab8 DN |
16225 | { |
16226 | rtx nop; | |
16227 | bool force; | |
16228 | int issue_rate = rs6000_issue_rate (); | |
16229 | bool end = *group_end; | |
16230 | int i; | |
16231 | ||
16232 | if (next_insn == NULL_RTX) | |
16233 | return can_issue_more; | |
16234 | ||
16235 | if (rs6000_sched_insert_nops > sched_finish_regroup_exact) | |
16236 | return can_issue_more; | |
16237 | ||
16238 | force = is_costly_group (group_insns, next_insn); | |
16239 | if (!force) | |
16240 | return can_issue_more; | |
16241 | ||
16242 | if (sched_verbose > 6) | |
16243 | fprintf (dump,"force: group count = %d, can_issue_more = %d\n", | |
c4ad648e | 16244 | *group_count ,can_issue_more); |
cbe26ab8 DN |
16245 | |
16246 | if (rs6000_sched_insert_nops == sched_finish_regroup_exact) | |
16247 | { | |
16248 | if (*group_end) | |
c4ad648e | 16249 | can_issue_more = 0; |
cbe26ab8 DN |
16250 | |
16251 | /* Since only a branch can be issued in the last issue_slot, it is | |
16252 | sufficient to insert 'can_issue_more - 1' nops if next_insn is not | |
16253 | a branch. If next_insn is a branch, we insert 'can_issue_more' nops; | |
c4ad648e AM |
16254 | in this case the last nop will start a new group and the branch |
16255 | will be forced to the new group. */ | |
cbe26ab8 | 16256 | if (can_issue_more && !is_branch_slot_insn (next_insn)) |
c4ad648e | 16257 | can_issue_more--; |
cbe26ab8 DN |
16258 | |
16259 | while (can_issue_more > 0) | |
c4ad648e AM |
16260 | { |
16261 | nop = gen_nop(); | |
16262 | emit_insn_before (nop, next_insn); | |
16263 | can_issue_more--; | |
16264 | } | |
cbe26ab8 DN |
16265 | |
16266 | *group_end = true; | |
16267 | return 0; | |
f676971a | 16268 | } |
cbe26ab8 DN |
16269 | |
16270 | if (rs6000_sched_insert_nops < sched_finish_regroup_exact) | |
16271 | { | |
16272 | int n_nops = rs6000_sched_insert_nops; | |
16273 | ||
f676971a | 16274 | /* Nops can't be issued from the branch slot, so the effective |
c4ad648e | 16275 | issue_rate for nops is 'issue_rate - 1'. */ |
cbe26ab8 | 16276 | if (can_issue_more == 0) |
c4ad648e | 16277 | can_issue_more = issue_rate; |
cbe26ab8 DN |
16278 | can_issue_more--; |
16279 | if (can_issue_more == 0) | |
c4ad648e AM |
16280 | { |
16281 | can_issue_more = issue_rate - 1; | |
16282 | (*group_count)++; | |
16283 | end = true; | |
16284 | for (i = 0; i < issue_rate; i++) | |
16285 | { | |
16286 | group_insns[i] = 0; | |
16287 | } | |
16288 | } | |
cbe26ab8 DN |
16289 | |
16290 | while (n_nops > 0) | |
c4ad648e AM |
16291 | { |
16292 | nop = gen_nop (); | |
16293 | emit_insn_before (nop, next_insn); | |
16294 | if (can_issue_more == issue_rate - 1) /* new group begins */ | |
16295 | end = false; | |
16296 | can_issue_more--; | |
16297 | if (can_issue_more == 0) | |
16298 | { | |
16299 | can_issue_more = issue_rate - 1; | |
16300 | (*group_count)++; | |
16301 | end = true; | |
16302 | for (i = 0; i < issue_rate; i++) | |
16303 | { | |
16304 | group_insns[i] = 0; | |
16305 | } | |
16306 | } | |
16307 | n_nops--; | |
16308 | } | |
cbe26ab8 DN |
16309 | |
16310 | /* Scale back relative to 'issue_rate' (instead of 'issue_rate - 1'). */ | |
f676971a | 16311 | can_issue_more++; |
cbe26ab8 | 16312 | |
c4ad648e AM |
16313 | /* Is next_insn going to start a new group? */ |
16314 | *group_end | |
16315 | = (end | |
cbe26ab8 DN |
16316 | || (can_issue_more == 1 && !is_branch_slot_insn (next_insn)) |
16317 | || (can_issue_more <= 2 && is_cracked_insn (next_insn)) | |
16318 | || (can_issue_more < issue_rate && | |
c4ad648e | 16319 | insn_terminates_group_p (next_insn, previous_group))); |
cbe26ab8 | 16320 | if (*group_end && end) |
c4ad648e | 16321 | (*group_count)--; |
cbe26ab8 DN |
16322 | |
16323 | if (sched_verbose > 6) | |
c4ad648e AM |
16324 | fprintf (dump, "done force: group count = %d, can_issue_more = %d\n", |
16325 | *group_count, can_issue_more); | |
f676971a EC |
16326 | return can_issue_more; |
16327 | } | |
cbe26ab8 DN |
16328 | |
16329 | return can_issue_more; | |
16330 | } | |
16331 | ||
16332 | /* This function tries to synch the dispatch groups that the compiler "sees" | |
f676971a | 16333 | with the dispatch groups that the processor dispatcher is expected to |
cbe26ab8 DN |
16334 | form in practice. It tries to achieve this synchronization by forcing the |
16335 | estimated processor grouping on the compiler (as opposed to the function | |
16336 | 'pad_goups' which tries to force the scheduler's grouping on the processor). | |
16337 | ||
16338 | The function scans the insn sequence between PREV_HEAD_INSN and TAIL and | |
16339 | examines the (estimated) dispatch groups that will be formed by the processor | |
16340 | dispatcher. It marks these group boundaries to reflect the estimated | |
16341 | processor grouping, overriding the grouping that the scheduler had marked. | |
16342 | Depending on the value of the flag '-minsert-sched-nops' this function can | |
16343 | force certain insns into separate groups or force a certain distance between | |
16344 | them by inserting nops, for example, if there exists a "costly dependence" | |
16345 | between the insns. | |
16346 | ||
16347 | The function estimates the group boundaries that the processor will form as | |
16348 | folllows: It keeps track of how many vacant issue slots are available after | |
16349 | each insn. A subsequent insn will start a new group if one of the following | |
16350 | 4 cases applies: | |
16351 | - no more vacant issue slots remain in the current dispatch group. | |
16352 | - only the last issue slot, which is the branch slot, is vacant, but the next | |
16353 | insn is not a branch. | |
16354 | - only the last 2 or less issue slots, including the branch slot, are vacant, | |
16355 | which means that a cracked insn (which occupies two issue slots) can't be | |
16356 | issued in this group. | |
f676971a | 16357 | - less than 'issue_rate' slots are vacant, and the next insn always needs to |
cbe26ab8 DN |
16358 | start a new group. */ |
16359 | ||
16360 | static int | |
16361 | redefine_groups (FILE *dump, int sched_verbose, rtx prev_head_insn, rtx tail) | |
16362 | { | |
16363 | rtx insn, next_insn; | |
16364 | int issue_rate; | |
16365 | int can_issue_more; | |
16366 | int slot, i; | |
16367 | bool group_end; | |
16368 | int group_count = 0; | |
16369 | rtx *group_insns; | |
16370 | ||
16371 | /* Initialize. */ | |
16372 | issue_rate = rs6000_issue_rate (); | |
16373 | group_insns = alloca (issue_rate * sizeof (rtx)); | |
f676971a | 16374 | for (i = 0; i < issue_rate; i++) |
cbe26ab8 DN |
16375 | { |
16376 | group_insns[i] = 0; | |
16377 | } | |
16378 | can_issue_more = issue_rate; | |
16379 | slot = 0; | |
16380 | insn = get_next_active_insn (prev_head_insn, tail); | |
16381 | group_end = false; | |
16382 | ||
16383 | while (insn != NULL_RTX) | |
16384 | { | |
16385 | slot = (issue_rate - can_issue_more); | |
16386 | group_insns[slot] = insn; | |
16387 | can_issue_more = | |
c4ad648e | 16388 | rs6000_variable_issue (dump, sched_verbose, insn, can_issue_more); |
cbe26ab8 | 16389 | if (insn_terminates_group_p (insn, current_group)) |
c4ad648e | 16390 | can_issue_more = 0; |
cbe26ab8 DN |
16391 | |
16392 | next_insn = get_next_active_insn (insn, tail); | |
16393 | if (next_insn == NULL_RTX) | |
c4ad648e | 16394 | return group_count + 1; |
cbe26ab8 | 16395 | |
c4ad648e AM |
16396 | /* Is next_insn going to start a new group? */ |
16397 | group_end | |
16398 | = (can_issue_more == 0 | |
16399 | || (can_issue_more == 1 && !is_branch_slot_insn (next_insn)) | |
16400 | || (can_issue_more <= 2 && is_cracked_insn (next_insn)) | |
16401 | || (can_issue_more < issue_rate && | |
16402 | insn_terminates_group_p (next_insn, previous_group))); | |
cbe26ab8 | 16403 | |
f676971a | 16404 | can_issue_more = force_new_group (sched_verbose, dump, group_insns, |
c4ad648e AM |
16405 | next_insn, &group_end, can_issue_more, |
16406 | &group_count); | |
cbe26ab8 DN |
16407 | |
16408 | if (group_end) | |
c4ad648e AM |
16409 | { |
16410 | group_count++; | |
16411 | can_issue_more = 0; | |
16412 | for (i = 0; i < issue_rate; i++) | |
16413 | { | |
16414 | group_insns[i] = 0; | |
16415 | } | |
16416 | } | |
cbe26ab8 DN |
16417 | |
16418 | if (GET_MODE (next_insn) == TImode && can_issue_more) | |
c4ad648e | 16419 | PUT_MODE(next_insn, VOIDmode); |
cbe26ab8 | 16420 | else if (!can_issue_more && GET_MODE (next_insn) != TImode) |
c4ad648e | 16421 | PUT_MODE (next_insn, TImode); |
cbe26ab8 DN |
16422 | |
16423 | insn = next_insn; | |
16424 | if (can_issue_more == 0) | |
c4ad648e AM |
16425 | can_issue_more = issue_rate; |
16426 | } /* while */ | |
cbe26ab8 DN |
16427 | |
16428 | return group_count; | |
16429 | } | |
16430 | ||
16431 | /* Scan the insn sequence between PREV_HEAD_INSN and TAIL and examine the | |
16432 | dispatch group boundaries that the scheduler had marked. Pad with nops | |
16433 | any dispatch groups which have vacant issue slots, in order to force the | |
16434 | scheduler's grouping on the processor dispatcher. The function | |
16435 | returns the number of dispatch groups found. */ | |
16436 | ||
16437 | static int | |
16438 | pad_groups (FILE *dump, int sched_verbose, rtx prev_head_insn, rtx tail) | |
16439 | { | |
16440 | rtx insn, next_insn; | |
16441 | rtx nop; | |
16442 | int issue_rate; | |
16443 | int can_issue_more; | |
16444 | int group_end; | |
16445 | int group_count = 0; | |
16446 | ||
16447 | /* Initialize issue_rate. */ | |
16448 | issue_rate = rs6000_issue_rate (); | |
16449 | can_issue_more = issue_rate; | |
16450 | ||
16451 | insn = get_next_active_insn (prev_head_insn, tail); | |
16452 | next_insn = get_next_active_insn (insn, tail); | |
16453 | ||
16454 | while (insn != NULL_RTX) | |
16455 | { | |
16456 | can_issue_more = | |
16457 | rs6000_variable_issue (dump, sched_verbose, insn, can_issue_more); | |
16458 | ||
16459 | group_end = (next_insn == NULL_RTX || GET_MODE (next_insn) == TImode); | |
16460 | ||
16461 | if (next_insn == NULL_RTX) | |
c4ad648e | 16462 | break; |
cbe26ab8 DN |
16463 | |
16464 | if (group_end) | |
c4ad648e AM |
16465 | { |
16466 | /* If the scheduler had marked group termination at this location | |
16467 | (between insn and next_indn), and neither insn nor next_insn will | |
16468 | force group termination, pad the group with nops to force group | |
16469 | termination. */ | |
16470 | if (can_issue_more | |
16471 | && (rs6000_sched_insert_nops == sched_finish_pad_groups) | |
16472 | && !insn_terminates_group_p (insn, current_group) | |
16473 | && !insn_terminates_group_p (next_insn, previous_group)) | |
16474 | { | |
16475 | if (!is_branch_slot_insn(next_insn)) | |
16476 | can_issue_more--; | |
16477 | ||
16478 | while (can_issue_more) | |
16479 | { | |
16480 | nop = gen_nop (); | |
16481 | emit_insn_before (nop, next_insn); | |
16482 | can_issue_more--; | |
16483 | } | |
16484 | } | |
16485 | ||
16486 | can_issue_more = issue_rate; | |
16487 | group_count++; | |
16488 | } | |
cbe26ab8 DN |
16489 | |
16490 | insn = next_insn; | |
16491 | next_insn = get_next_active_insn (insn, tail); | |
16492 | } | |
16493 | ||
16494 | return group_count; | |
16495 | } | |
16496 | ||
16497 | /* The following function is called at the end of scheduling BB. | |
16498 | After reload, it inserts nops at insn group bundling. */ | |
16499 | ||
16500 | static void | |
38f391a5 | 16501 | rs6000_sched_finish (FILE *dump, int sched_verbose) |
cbe26ab8 DN |
16502 | { |
16503 | int n_groups; | |
16504 | ||
16505 | if (sched_verbose) | |
16506 | fprintf (dump, "=== Finishing schedule.\n"); | |
16507 | ||
ec507f2d | 16508 | if (reload_completed && rs6000_sched_groups) |
cbe26ab8 DN |
16509 | { |
16510 | if (rs6000_sched_insert_nops == sched_finish_none) | |
c4ad648e | 16511 | return; |
cbe26ab8 DN |
16512 | |
16513 | if (rs6000_sched_insert_nops == sched_finish_pad_groups) | |
c4ad648e AM |
16514 | n_groups = pad_groups (dump, sched_verbose, |
16515 | current_sched_info->prev_head, | |
16516 | current_sched_info->next_tail); | |
cbe26ab8 | 16517 | else |
c4ad648e AM |
16518 | n_groups = redefine_groups (dump, sched_verbose, |
16519 | current_sched_info->prev_head, | |
16520 | current_sched_info->next_tail); | |
cbe26ab8 DN |
16521 | |
16522 | if (sched_verbose >= 6) | |
16523 | { | |
16524 | fprintf (dump, "ngroups = %d\n", n_groups); | |
16525 | print_rtl (dump, current_sched_info->prev_head); | |
16526 | fprintf (dump, "Done finish_sched\n"); | |
16527 | } | |
16528 | } | |
16529 | } | |
b6c9286a | 16530 | \f |
b6c9286a MM |
16531 | /* Length in units of the trampoline for entering a nested function. */ |
16532 | ||
16533 | int | |
863d938c | 16534 | rs6000_trampoline_size (void) |
b6c9286a MM |
16535 | { |
16536 | int ret = 0; | |
16537 | ||
16538 | switch (DEFAULT_ABI) | |
16539 | { | |
16540 | default: | |
16541 | abort (); | |
16542 | ||
16543 | case ABI_AIX: | |
8f802bfb | 16544 | ret = (TARGET_32BIT) ? 12 : 24; |
b6c9286a MM |
16545 | break; |
16546 | ||
4dabc42d | 16547 | case ABI_DARWIN: |
b6c9286a | 16548 | case ABI_V4: |
03a7e1a5 | 16549 | ret = (TARGET_32BIT) ? 40 : 48; |
b6c9286a | 16550 | break; |
b6c9286a MM |
16551 | } |
16552 | ||
16553 | return ret; | |
16554 | } | |
16555 | ||
16556 | /* Emit RTL insns to initialize the variable parts of a trampoline. | |
16557 | FNADDR is an RTX for the address of the function's pure code. | |
16558 | CXT is an RTX for the static chain value for the function. */ | |
16559 | ||
16560 | void | |
a2369ed3 | 16561 | rs6000_initialize_trampoline (rtx addr, rtx fnaddr, rtx cxt) |
b6c9286a | 16562 | { |
ac2a93a1 | 16563 | enum machine_mode pmode = Pmode; |
8bd04c56 MM |
16564 | int regsize = (TARGET_32BIT) ? 4 : 8; |
16565 | rtx ctx_reg = force_reg (pmode, cxt); | |
b6c9286a MM |
16566 | |
16567 | switch (DEFAULT_ABI) | |
16568 | { | |
16569 | default: | |
16570 | abort (); | |
16571 | ||
8bd04c56 | 16572 | /* Macros to shorten the code expansions below. */ |
39403d82 | 16573 | #define MEM_DEREF(addr) gen_rtx_MEM (pmode, memory_address (pmode, addr)) |
c5c76735 JL |
16574 | #define MEM_PLUS(addr,offset) \ |
16575 | gen_rtx_MEM (pmode, memory_address (pmode, plus_constant (addr, offset))) | |
7c59dc5d | 16576 | |
b6c9286a MM |
16577 | /* Under AIX, just build the 3 word function descriptor */ |
16578 | case ABI_AIX: | |
8bd04c56 MM |
16579 | { |
16580 | rtx fn_reg = gen_reg_rtx (pmode); | |
16581 | rtx toc_reg = gen_reg_rtx (pmode); | |
16582 | emit_move_insn (fn_reg, MEM_DEREF (fnaddr)); | |
1cb18e3c | 16583 | emit_move_insn (toc_reg, MEM_PLUS (fnaddr, regsize)); |
8bd04c56 MM |
16584 | emit_move_insn (MEM_DEREF (addr), fn_reg); |
16585 | emit_move_insn (MEM_PLUS (addr, regsize), toc_reg); | |
16586 | emit_move_insn (MEM_PLUS (addr, 2*regsize), ctx_reg); | |
16587 | } | |
b6c9286a MM |
16588 | break; |
16589 | ||
4dabc42d TC |
16590 | /* Under V.4/eabi/darwin, __trampoline_setup does the real work. */ |
16591 | case ABI_DARWIN: | |
b6c9286a | 16592 | case ABI_V4: |
39403d82 | 16593 | emit_library_call (gen_rtx_SYMBOL_REF (SImode, "__trampoline_setup"), |
eaf1bcf1 MM |
16594 | FALSE, VOIDmode, 4, |
16595 | addr, pmode, | |
16596 | GEN_INT (rs6000_trampoline_size ()), SImode, | |
16597 | fnaddr, pmode, | |
16598 | ctx_reg, pmode); | |
b6c9286a | 16599 | break; |
b6c9286a MM |
16600 | } |
16601 | ||
16602 | return; | |
16603 | } | |
7509c759 MM |
16604 | |
16605 | \f | |
91d231cb | 16606 | /* Table of valid machine attributes. */ |
a4f6c312 | 16607 | |
91d231cb | 16608 | const struct attribute_spec rs6000_attribute_table[] = |
7509c759 | 16609 | { |
91d231cb | 16610 | /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */ |
8bb418a3 | 16611 | { "altivec", 1, 1, false, true, false, rs6000_handle_altivec_attribute }, |
a5c76ee6 ZW |
16612 | { "longcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute }, |
16613 | { "shortcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute }, | |
16614 | { NULL, 0, 0, false, false, false, NULL } | |
91d231cb | 16615 | }; |
7509c759 | 16616 | |
8bb418a3 ZL |
16617 | /* Handle the "altivec" attribute. The attribute may have |
16618 | arguments as follows: | |
f676971a | 16619 | |
8bb418a3 ZL |
16620 | __attribute__((altivec(vector__))) |
16621 | __attribute__((altivec(pixel__))) (always followed by 'unsigned short') | |
16622 | __attribute__((altivec(bool__))) (always followed by 'unsigned') | |
16623 | ||
16624 | and may appear more than once (e.g., 'vector bool char') in a | |
16625 | given declaration. */ | |
16626 | ||
16627 | static tree | |
16628 | rs6000_handle_altivec_attribute (tree *node, tree name, tree args, | |
16629 | int flags ATTRIBUTE_UNUSED, | |
16630 | bool *no_add_attrs) | |
16631 | { | |
16632 | tree type = *node, result = NULL_TREE; | |
16633 | enum machine_mode mode; | |
16634 | int unsigned_p; | |
16635 | char altivec_type | |
16636 | = ((args && TREE_CODE (args) == TREE_LIST && TREE_VALUE (args) | |
16637 | && TREE_CODE (TREE_VALUE (args)) == IDENTIFIER_NODE) | |
16638 | ? *IDENTIFIER_POINTER (TREE_VALUE (args)) | |
f676971a | 16639 | : '?'); |
8bb418a3 ZL |
16640 | |
16641 | while (POINTER_TYPE_P (type) | |
16642 | || TREE_CODE (type) == FUNCTION_TYPE | |
16643 | || TREE_CODE (type) == METHOD_TYPE | |
16644 | || TREE_CODE (type) == ARRAY_TYPE) | |
16645 | type = TREE_TYPE (type); | |
16646 | ||
16647 | mode = TYPE_MODE (type); | |
16648 | ||
16649 | if (rs6000_warn_altivec_long | |
16650 | && (type == long_unsigned_type_node || type == long_integer_type_node)) | |
16651 | warning ("use of 'long' in AltiVec types is deprecated; use 'int'"); | |
16652 | ||
16653 | switch (altivec_type) | |
16654 | { | |
16655 | case 'v': | |
8df83eae | 16656 | unsigned_p = TYPE_UNSIGNED (type); |
8bb418a3 ZL |
16657 | switch (mode) |
16658 | { | |
c4ad648e AM |
16659 | case SImode: |
16660 | result = (unsigned_p ? unsigned_V4SI_type_node : V4SI_type_node); | |
16661 | break; | |
16662 | case HImode: | |
16663 | result = (unsigned_p ? unsigned_V8HI_type_node : V8HI_type_node); | |
16664 | break; | |
16665 | case QImode: | |
16666 | result = (unsigned_p ? unsigned_V16QI_type_node : V16QI_type_node); | |
16667 | break; | |
16668 | case SFmode: result = V4SF_type_node; break; | |
16669 | /* If the user says 'vector int bool', we may be handed the 'bool' | |
16670 | attribute _before_ the 'vector' attribute, and so select the | |
16671 | proper type in the 'b' case below. */ | |
16672 | case V4SImode: case V8HImode: case V16QImode: case V4SFmode: | |
16673 | result = type; | |
16674 | default: break; | |
8bb418a3 ZL |
16675 | } |
16676 | break; | |
16677 | case 'b': | |
16678 | switch (mode) | |
16679 | { | |
c4ad648e AM |
16680 | case SImode: case V4SImode: result = bool_V4SI_type_node; break; |
16681 | case HImode: case V8HImode: result = bool_V8HI_type_node; break; | |
16682 | case QImode: case V16QImode: result = bool_V16QI_type_node; | |
16683 | default: break; | |
8bb418a3 ZL |
16684 | } |
16685 | break; | |
16686 | case 'p': | |
16687 | switch (mode) | |
16688 | { | |
c4ad648e AM |
16689 | case V8HImode: result = pixel_V8HI_type_node; |
16690 | default: break; | |
8bb418a3 ZL |
16691 | } |
16692 | default: break; | |
16693 | } | |
16694 | ||
7958a2a6 FJ |
16695 | if (result && result != type && TYPE_READONLY (type)) |
16696 | result = build_qualified_type (result, TYPE_QUAL_CONST); | |
16697 | ||
8bb418a3 ZL |
16698 | *no_add_attrs = true; /* No need to hang on to the attribute. */ |
16699 | ||
16700 | if (!result) | |
16701 | warning ("`%s' attribute ignored", IDENTIFIER_POINTER (name)); | |
16702 | else | |
16703 | *node = reconstruct_complex_type (*node, result); | |
16704 | ||
16705 | return NULL_TREE; | |
16706 | } | |
16707 | ||
f18eca82 ZL |
16708 | /* AltiVec defines four built-in scalar types that serve as vector |
16709 | elements; we must teach the compiler how to mangle them. */ | |
16710 | ||
16711 | static const char * | |
16712 | rs6000_mangle_fundamental_type (tree type) | |
16713 | { | |
16714 | if (type == bool_char_type_node) return "U6__boolc"; | |
16715 | if (type == bool_short_type_node) return "U6__bools"; | |
16716 | if (type == pixel_type_node) return "u7__pixel"; | |
16717 | if (type == bool_int_type_node) return "U6__booli"; | |
16718 | ||
16719 | /* For all other types, use normal C++ mangling. */ | |
16720 | return NULL; | |
16721 | } | |
16722 | ||
a5c76ee6 ZW |
16723 | /* Handle a "longcall" or "shortcall" attribute; arguments as in |
16724 | struct attribute_spec.handler. */ | |
a4f6c312 | 16725 | |
91d231cb | 16726 | static tree |
f676971a EC |
16727 | rs6000_handle_longcall_attribute (tree *node, tree name, |
16728 | tree args ATTRIBUTE_UNUSED, | |
16729 | int flags ATTRIBUTE_UNUSED, | |
a2369ed3 | 16730 | bool *no_add_attrs) |
91d231cb JM |
16731 | { |
16732 | if (TREE_CODE (*node) != FUNCTION_TYPE | |
16733 | && TREE_CODE (*node) != FIELD_DECL | |
16734 | && TREE_CODE (*node) != TYPE_DECL) | |
16735 | { | |
16736 | warning ("`%s' attribute only applies to functions", | |
16737 | IDENTIFIER_POINTER (name)); | |
16738 | *no_add_attrs = true; | |
16739 | } | |
6a4cee5f | 16740 | |
91d231cb | 16741 | return NULL_TREE; |
7509c759 MM |
16742 | } |
16743 | ||
a5c76ee6 ZW |
16744 | /* Set longcall attributes on all functions declared when |
16745 | rs6000_default_long_calls is true. */ | |
16746 | static void | |
a2369ed3 | 16747 | rs6000_set_default_type_attributes (tree type) |
a5c76ee6 ZW |
16748 | { |
16749 | if (rs6000_default_long_calls | |
16750 | && (TREE_CODE (type) == FUNCTION_TYPE | |
16751 | || TREE_CODE (type) == METHOD_TYPE)) | |
16752 | TYPE_ATTRIBUTES (type) = tree_cons (get_identifier ("longcall"), | |
16753 | NULL_TREE, | |
16754 | TYPE_ATTRIBUTES (type)); | |
16755 | } | |
16756 | ||
3cb999d8 DE |
16757 | /* Return a reference suitable for calling a function with the |
16758 | longcall attribute. */ | |
a4f6c312 | 16759 | |
6a4cee5f | 16760 | struct rtx_def * |
a2369ed3 | 16761 | rs6000_longcall_ref (rtx call_ref) |
6a4cee5f | 16762 | { |
d330fd93 | 16763 | const char *call_name; |
6a4cee5f MM |
16764 | tree node; |
16765 | ||
16766 | if (GET_CODE (call_ref) != SYMBOL_REF) | |
16767 | return call_ref; | |
16768 | ||
16769 | /* System V adds '.' to the internal name, so skip them. */ | |
16770 | call_name = XSTR (call_ref, 0); | |
16771 | if (*call_name == '.') | |
16772 | { | |
16773 | while (*call_name == '.') | |
16774 | call_name++; | |
16775 | ||
16776 | node = get_identifier (call_name); | |
39403d82 | 16777 | call_ref = gen_rtx_SYMBOL_REF (VOIDmode, IDENTIFIER_POINTER (node)); |
6a4cee5f MM |
16778 | } |
16779 | ||
16780 | return force_reg (Pmode, call_ref); | |
16781 | } | |
7509c759 | 16782 | \f |
b64a1b53 RH |
16783 | #ifdef USING_ELFOS_H |
16784 | ||
7509c759 MM |
16785 | /* A C statement or statements to switch to the appropriate section |
16786 | for output of RTX in mode MODE. You can assume that RTX is some | |
16787 | kind of constant in RTL. The argument MODE is redundant except in | |
16788 | the case of a `const_int' rtx. Select the section by calling | |
16789 | `text_section' or one of the alternatives for other sections. | |
16790 | ||
16791 | Do not define this macro if you put all constants in the read-only | |
16792 | data section. */ | |
16793 | ||
b64a1b53 | 16794 | static void |
f676971a | 16795 | rs6000_elf_select_rtx_section (enum machine_mode mode, rtx x, |
a2369ed3 | 16796 | unsigned HOST_WIDE_INT align) |
7509c759 | 16797 | { |
a9098fd0 | 16798 | if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode)) |
7509c759 | 16799 | toc_section (); |
7509c759 | 16800 | else |
b64a1b53 | 16801 | default_elf_select_rtx_section (mode, x, align); |
7509c759 MM |
16802 | } |
16803 | ||
16804 | /* A C statement or statements to switch to the appropriate | |
16805 | section for output of DECL. DECL is either a `VAR_DECL' node | |
16806 | or a constant of some sort. RELOC indicates whether forming | |
16807 | the initial value of DECL requires link-time relocations. */ | |
16808 | ||
ae46c4e0 | 16809 | static void |
f676971a | 16810 | rs6000_elf_select_section (tree decl, int reloc, |
a2369ed3 | 16811 | unsigned HOST_WIDE_INT align) |
7509c759 | 16812 | { |
f1384257 AM |
16813 | /* Pretend that we're always building for a shared library when |
16814 | ABI_AIX, because otherwise we end up with dynamic relocations | |
16815 | in read-only sections. This happens for function pointers, | |
16816 | references to vtables in typeinfo, and probably other cases. */ | |
0e5dbd9b DE |
16817 | default_elf_select_section_1 (decl, reloc, align, |
16818 | flag_pic || DEFAULT_ABI == ABI_AIX); | |
63019373 GK |
16819 | } |
16820 | ||
16821 | /* A C statement to build up a unique section name, expressed as a | |
16822 | STRING_CST node, and assign it to DECL_SECTION_NAME (decl). | |
16823 | RELOC indicates whether the initial value of EXP requires | |
16824 | link-time relocations. If you do not define this macro, GCC will use | |
16825 | the symbol name prefixed by `.' as the section name. Note - this | |
f5143c46 | 16826 | macro can now be called for uninitialized data items as well as |
4912a07c | 16827 | initialized data and functions. */ |
63019373 | 16828 | |
ae46c4e0 | 16829 | static void |
a2369ed3 | 16830 | rs6000_elf_unique_section (tree decl, int reloc) |
63019373 | 16831 | { |
f1384257 AM |
16832 | /* As above, pretend that we're always building for a shared library |
16833 | when ABI_AIX, to avoid dynamic relocations in read-only sections. */ | |
0e5dbd9b DE |
16834 | default_unique_section_1 (decl, reloc, |
16835 | flag_pic || DEFAULT_ABI == ABI_AIX); | |
7509c759 | 16836 | } |
d9407988 | 16837 | \f |
d1908feb JJ |
16838 | /* For a SYMBOL_REF, set generic flags and then perform some |
16839 | target-specific processing. | |
16840 | ||
d1908feb JJ |
16841 | When the AIX ABI is requested on a non-AIX system, replace the |
16842 | function name with the real name (with a leading .) rather than the | |
16843 | function descriptor name. This saves a lot of overriding code to | |
16844 | read the prefixes. */ | |
d9407988 | 16845 | |
fb49053f | 16846 | static void |
a2369ed3 | 16847 | rs6000_elf_encode_section_info (tree decl, rtx rtl, int first) |
d9407988 | 16848 | { |
d1908feb | 16849 | default_encode_section_info (decl, rtl, first); |
b2003250 | 16850 | |
d1908feb JJ |
16851 | if (first |
16852 | && TREE_CODE (decl) == FUNCTION_DECL | |
16853 | && !TARGET_AIX | |
16854 | && DEFAULT_ABI == ABI_AIX) | |
d9407988 | 16855 | { |
c6a2438a | 16856 | rtx sym_ref = XEXP (rtl, 0); |
d1908feb JJ |
16857 | size_t len = strlen (XSTR (sym_ref, 0)); |
16858 | char *str = alloca (len + 2); | |
16859 | str[0] = '.'; | |
16860 | memcpy (str + 1, XSTR (sym_ref, 0), len + 1); | |
16861 | XSTR (sym_ref, 0) = ggc_alloc_string (str, len + 1); | |
d9407988 | 16862 | } |
d9407988 MM |
16863 | } |
16864 | ||
0e5dbd9b | 16865 | static bool |
a2369ed3 | 16866 | rs6000_elf_in_small_data_p (tree decl) |
0e5dbd9b DE |
16867 | { |
16868 | if (rs6000_sdata == SDATA_NONE) | |
16869 | return false; | |
16870 | ||
16871 | if (TREE_CODE (decl) == VAR_DECL && DECL_SECTION_NAME (decl)) | |
16872 | { | |
16873 | const char *section = TREE_STRING_POINTER (DECL_SECTION_NAME (decl)); | |
16874 | if (strcmp (section, ".sdata") == 0 | |
16875 | || strcmp (section, ".sdata2") == 0 | |
20bfcd69 GK |
16876 | || strcmp (section, ".sbss") == 0 |
16877 | || strcmp (section, ".sbss2") == 0 | |
16878 | || strcmp (section, ".PPC.EMB.sdata0") == 0 | |
16879 | || strcmp (section, ".PPC.EMB.sbss0") == 0) | |
0e5dbd9b DE |
16880 | return true; |
16881 | } | |
16882 | else | |
16883 | { | |
16884 | HOST_WIDE_INT size = int_size_in_bytes (TREE_TYPE (decl)); | |
16885 | ||
16886 | if (size > 0 | |
307b599c | 16887 | && (unsigned HOST_WIDE_INT) size <= g_switch_value |
20bfcd69 GK |
16888 | /* If it's not public, and we're not going to reference it there, |
16889 | there's no need to put it in the small data section. */ | |
0e5dbd9b DE |
16890 | && (rs6000_sdata != SDATA_DATA || TREE_PUBLIC (decl))) |
16891 | return true; | |
16892 | } | |
16893 | ||
16894 | return false; | |
16895 | } | |
16896 | ||
b91da81f | 16897 | #endif /* USING_ELFOS_H */ |
000034eb | 16898 | |
a6c2a102 | 16899 | \f |
000034eb | 16900 | /* Return a REG that occurs in ADDR with coefficient 1. |
02441cd6 JL |
16901 | ADDR can be effectively incremented by incrementing REG. |
16902 | ||
16903 | r0 is special and we must not select it as an address | |
16904 | register by this routine since our caller will try to | |
16905 | increment the returned register via an "la" instruction. */ | |
000034eb DE |
16906 | |
16907 | struct rtx_def * | |
a2369ed3 | 16908 | find_addr_reg (rtx addr) |
000034eb DE |
16909 | { |
16910 | while (GET_CODE (addr) == PLUS) | |
16911 | { | |
02441cd6 JL |
16912 | if (GET_CODE (XEXP (addr, 0)) == REG |
16913 | && REGNO (XEXP (addr, 0)) != 0) | |
000034eb | 16914 | addr = XEXP (addr, 0); |
02441cd6 JL |
16915 | else if (GET_CODE (XEXP (addr, 1)) == REG |
16916 | && REGNO (XEXP (addr, 1)) != 0) | |
000034eb DE |
16917 | addr = XEXP (addr, 1); |
16918 | else if (CONSTANT_P (XEXP (addr, 0))) | |
16919 | addr = XEXP (addr, 1); | |
16920 | else if (CONSTANT_P (XEXP (addr, 1))) | |
16921 | addr = XEXP (addr, 0); | |
16922 | else | |
16923 | abort (); | |
16924 | } | |
02441cd6 | 16925 | if (GET_CODE (addr) == REG && REGNO (addr) != 0) |
000034eb DE |
16926 | return addr; |
16927 | abort (); | |
16928 | } | |
16929 | ||
a6c2a102 | 16930 | void |
a2369ed3 | 16931 | rs6000_fatal_bad_address (rtx op) |
a6c2a102 DE |
16932 | { |
16933 | fatal_insn ("bad address", op); | |
16934 | } | |
c8023011 | 16935 | |
ee890fe2 SS |
16936 | #if TARGET_MACHO |
16937 | ||
efdba735 | 16938 | static tree branch_island_list = 0; |
ee890fe2 | 16939 | |
efdba735 SH |
16940 | /* Remember to generate a branch island for far calls to the given |
16941 | function. */ | |
ee890fe2 | 16942 | |
f676971a | 16943 | static void |
c4ad648e AM |
16944 | add_compiler_branch_island (tree label_name, tree function_name, |
16945 | int line_number) | |
ee890fe2 | 16946 | { |
efdba735 | 16947 | tree branch_island = build_tree_list (function_name, label_name); |
7d60be94 | 16948 | TREE_TYPE (branch_island) = build_int_cst (NULL_TREE, line_number); |
efdba735 SH |
16949 | TREE_CHAIN (branch_island) = branch_island_list; |
16950 | branch_island_list = branch_island; | |
ee890fe2 SS |
16951 | } |
16952 | ||
efdba735 SH |
16953 | #define BRANCH_ISLAND_LABEL_NAME(BRANCH_ISLAND) TREE_VALUE (BRANCH_ISLAND) |
16954 | #define BRANCH_ISLAND_FUNCTION_NAME(BRANCH_ISLAND) TREE_PURPOSE (BRANCH_ISLAND) | |
16955 | #define BRANCH_ISLAND_LINE_NUMBER(BRANCH_ISLAND) \ | |
16956 | TREE_INT_CST_LOW (TREE_TYPE (BRANCH_ISLAND)) | |
ee890fe2 | 16957 | |
efdba735 SH |
16958 | /* Generate far-jump branch islands for everything on the |
16959 | branch_island_list. Invoked immediately after the last instruction | |
16960 | of the epilogue has been emitted; the branch-islands must be | |
16961 | appended to, and contiguous with, the function body. Mach-O stubs | |
16962 | are generated in machopic_output_stub(). */ | |
ee890fe2 | 16963 | |
efdba735 SH |
16964 | static void |
16965 | macho_branch_islands (void) | |
16966 | { | |
16967 | char tmp_buf[512]; | |
16968 | tree branch_island; | |
16969 | ||
16970 | for (branch_island = branch_island_list; | |
16971 | branch_island; | |
16972 | branch_island = TREE_CHAIN (branch_island)) | |
16973 | { | |
16974 | const char *label = | |
16975 | IDENTIFIER_POINTER (BRANCH_ISLAND_LABEL_NAME (branch_island)); | |
16976 | const char *name = | |
11abc112 | 16977 | IDENTIFIER_POINTER (BRANCH_ISLAND_FUNCTION_NAME (branch_island)); |
efdba735 SH |
16978 | char name_buf[512]; |
16979 | /* Cheap copy of the details from the Darwin ASM_OUTPUT_LABELREF(). */ | |
16980 | if (name[0] == '*' || name[0] == '&') | |
16981 | strcpy (name_buf, name+1); | |
16982 | else | |
16983 | { | |
16984 | name_buf[0] = '_'; | |
16985 | strcpy (name_buf+1, name); | |
16986 | } | |
16987 | strcpy (tmp_buf, "\n"); | |
16988 | strcat (tmp_buf, label); | |
ee890fe2 | 16989 | #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO) |
efdba735 | 16990 | if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG) |
f7efd730 | 16991 | fprintf (asm_out_file, "\t.stabd 68,0," HOST_WIDE_INT_PRINT_UNSIGNED "\n", |
efdba735 | 16992 | BRANCH_ISLAND_LINE_NUMBER(branch_island)); |
ee890fe2 | 16993 | #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */ |
efdba735 SH |
16994 | if (flag_pic) |
16995 | { | |
16996 | strcat (tmp_buf, ":\n\tmflr r0\n\tbcl 20,31,"); | |
16997 | strcat (tmp_buf, label); | |
16998 | strcat (tmp_buf, "_pic\n"); | |
16999 | strcat (tmp_buf, label); | |
17000 | strcat (tmp_buf, "_pic:\n\tmflr r11\n"); | |
f676971a | 17001 | |
efdba735 SH |
17002 | strcat (tmp_buf, "\taddis r11,r11,ha16("); |
17003 | strcat (tmp_buf, name_buf); | |
17004 | strcat (tmp_buf, " - "); | |
17005 | strcat (tmp_buf, label); | |
17006 | strcat (tmp_buf, "_pic)\n"); | |
f676971a | 17007 | |
efdba735 | 17008 | strcat (tmp_buf, "\tmtlr r0\n"); |
f676971a | 17009 | |
efdba735 SH |
17010 | strcat (tmp_buf, "\taddi r12,r11,lo16("); |
17011 | strcat (tmp_buf, name_buf); | |
17012 | strcat (tmp_buf, " - "); | |
17013 | strcat (tmp_buf, label); | |
17014 | strcat (tmp_buf, "_pic)\n"); | |
f676971a | 17015 | |
efdba735 SH |
17016 | strcat (tmp_buf, "\tmtctr r12\n\tbctr\n"); |
17017 | } | |
17018 | else | |
17019 | { | |
17020 | strcat (tmp_buf, ":\nlis r12,hi16("); | |
17021 | strcat (tmp_buf, name_buf); | |
17022 | strcat (tmp_buf, ")\n\tori r12,r12,lo16("); | |
17023 | strcat (tmp_buf, name_buf); | |
17024 | strcat (tmp_buf, ")\n\tmtctr r12\n\tbctr"); | |
17025 | } | |
17026 | output_asm_insn (tmp_buf, 0); | |
ee890fe2 | 17027 | #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO) |
efdba735 | 17028 | if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG) |
f7efd730 | 17029 | fprintf(asm_out_file, "\t.stabd 68,0," HOST_WIDE_INT_PRINT_UNSIGNED "\n", |
efdba735 | 17030 | BRANCH_ISLAND_LINE_NUMBER (branch_island)); |
ee890fe2 | 17031 | #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */ |
efdba735 | 17032 | } |
ee890fe2 | 17033 | |
efdba735 | 17034 | branch_island_list = 0; |
ee890fe2 SS |
17035 | } |
17036 | ||
17037 | /* NO_PREVIOUS_DEF checks in the link list whether the function name is | |
17038 | already there or not. */ | |
17039 | ||
efdba735 | 17040 | static int |
a2369ed3 | 17041 | no_previous_def (tree function_name) |
ee890fe2 | 17042 | { |
efdba735 SH |
17043 | tree branch_island; |
17044 | for (branch_island = branch_island_list; | |
17045 | branch_island; | |
17046 | branch_island = TREE_CHAIN (branch_island)) | |
17047 | if (function_name == BRANCH_ISLAND_FUNCTION_NAME (branch_island)) | |
ee890fe2 SS |
17048 | return 0; |
17049 | return 1; | |
17050 | } | |
17051 | ||
17052 | /* GET_PREV_LABEL gets the label name from the previous definition of | |
17053 | the function. */ | |
17054 | ||
efdba735 | 17055 | static tree |
a2369ed3 | 17056 | get_prev_label (tree function_name) |
ee890fe2 | 17057 | { |
efdba735 SH |
17058 | tree branch_island; |
17059 | for (branch_island = branch_island_list; | |
17060 | branch_island; | |
17061 | branch_island = TREE_CHAIN (branch_island)) | |
17062 | if (function_name == BRANCH_ISLAND_FUNCTION_NAME (branch_island)) | |
17063 | return BRANCH_ISLAND_LABEL_NAME (branch_island); | |
ee890fe2 SS |
17064 | return 0; |
17065 | } | |
17066 | ||
17067 | /* INSN is either a function call or a millicode call. It may have an | |
f676971a | 17068 | unconditional jump in its delay slot. |
ee890fe2 SS |
17069 | |
17070 | CALL_DEST is the routine we are calling. */ | |
17071 | ||
17072 | char * | |
c4ad648e AM |
17073 | output_call (rtx insn, rtx *operands, int dest_operand_number, |
17074 | int cookie_operand_number) | |
ee890fe2 SS |
17075 | { |
17076 | static char buf[256]; | |
efdba735 SH |
17077 | if (GET_CODE (operands[dest_operand_number]) == SYMBOL_REF |
17078 | && (INTVAL (operands[cookie_operand_number]) & CALL_LONG)) | |
ee890fe2 SS |
17079 | { |
17080 | tree labelname; | |
efdba735 | 17081 | tree funname = get_identifier (XSTR (operands[dest_operand_number], 0)); |
f676971a | 17082 | |
ee890fe2 SS |
17083 | if (no_previous_def (funname)) |
17084 | { | |
308c142a | 17085 | int line_number = 0; |
ee890fe2 SS |
17086 | rtx label_rtx = gen_label_rtx (); |
17087 | char *label_buf, temp_buf[256]; | |
17088 | ASM_GENERATE_INTERNAL_LABEL (temp_buf, "L", | |
17089 | CODE_LABEL_NUMBER (label_rtx)); | |
17090 | label_buf = temp_buf[0] == '*' ? temp_buf + 1 : temp_buf; | |
17091 | labelname = get_identifier (label_buf); | |
17092 | for (; insn && GET_CODE (insn) != NOTE; insn = PREV_INSN (insn)); | |
17093 | if (insn) | |
17094 | line_number = NOTE_LINE_NUMBER (insn); | |
efdba735 | 17095 | add_compiler_branch_island (labelname, funname, line_number); |
ee890fe2 SS |
17096 | } |
17097 | else | |
17098 | labelname = get_prev_label (funname); | |
17099 | ||
efdba735 SH |
17100 | /* "jbsr foo, L42" is Mach-O for "Link as 'bl foo' if a 'bl' |
17101 | instruction will reach 'foo', otherwise link as 'bl L42'". | |
17102 | "L42" should be a 'branch island', that will do a far jump to | |
17103 | 'foo'. Branch islands are generated in | |
17104 | macho_branch_islands(). */ | |
ee890fe2 | 17105 | sprintf (buf, "jbsr %%z%d,%.246s", |
efdba735 | 17106 | dest_operand_number, IDENTIFIER_POINTER (labelname)); |
ee890fe2 SS |
17107 | } |
17108 | else | |
efdba735 SH |
17109 | sprintf (buf, "bl %%z%d", dest_operand_number); |
17110 | return buf; | |
ee890fe2 SS |
17111 | } |
17112 | ||
ee890fe2 SS |
17113 | /* Generate PIC and indirect symbol stubs. */ |
17114 | ||
17115 | void | |
a2369ed3 | 17116 | machopic_output_stub (FILE *file, const char *symb, const char *stub) |
ee890fe2 SS |
17117 | { |
17118 | unsigned int length; | |
a4f6c312 SS |
17119 | char *symbol_name, *lazy_ptr_name; |
17120 | char *local_label_0; | |
ee890fe2 SS |
17121 | static int label = 0; |
17122 | ||
df56a27f | 17123 | /* Lose our funky encoding stuff so it doesn't contaminate the stub. */ |
772c5265 | 17124 | symb = (*targetm.strip_name_encoding) (symb); |
df56a27f | 17125 | |
ee890fe2 | 17126 | |
ee890fe2 SS |
17127 | length = strlen (symb); |
17128 | symbol_name = alloca (length + 32); | |
17129 | GEN_SYMBOL_NAME_FOR_SYMBOL (symbol_name, symb, length); | |
17130 | ||
17131 | lazy_ptr_name = alloca (length + 32); | |
17132 | GEN_LAZY_PTR_NAME_FOR_SYMBOL (lazy_ptr_name, symb, length); | |
17133 | ||
ee890fe2 | 17134 | if (flag_pic == 2) |
d3c300d2 | 17135 | machopic_picsymbol_stub1_section (); |
ee890fe2 | 17136 | else |
d3c300d2 | 17137 | machopic_symbol_stub1_section (); |
ee890fe2 SS |
17138 | |
17139 | if (flag_pic == 2) | |
17140 | { | |
d974312d DJ |
17141 | fprintf (file, "\t.align 5\n"); |
17142 | ||
17143 | fprintf (file, "%s:\n", stub); | |
17144 | fprintf (file, "\t.indirect_symbol %s\n", symbol_name); | |
17145 | ||
876455fa AP |
17146 | label++; |
17147 | local_label_0 = alloca (sizeof("\"L0000000000$spb\"")); | |
17148 | sprintf (local_label_0, "\"L%011d$spb\"", label); | |
f676971a | 17149 | |
ee890fe2 SS |
17150 | fprintf (file, "\tmflr r0\n"); |
17151 | fprintf (file, "\tbcl 20,31,%s\n", local_label_0); | |
17152 | fprintf (file, "%s:\n\tmflr r11\n", local_label_0); | |
17153 | fprintf (file, "\taddis r11,r11,ha16(%s-%s)\n", | |
17154 | lazy_ptr_name, local_label_0); | |
17155 | fprintf (file, "\tmtlr r0\n"); | |
d3c300d2 | 17156 | fprintf (file, "\tlwzu r12,lo16(%s-%s)(r11)\n", |
ee890fe2 SS |
17157 | lazy_ptr_name, local_label_0); |
17158 | fprintf (file, "\tmtctr r12\n"); | |
ee890fe2 SS |
17159 | fprintf (file, "\tbctr\n"); |
17160 | } | |
17161 | else | |
d974312d DJ |
17162 | { |
17163 | fprintf (file, "\t.align 4\n"); | |
17164 | ||
17165 | fprintf (file, "%s:\n", stub); | |
17166 | fprintf (file, "\t.indirect_symbol %s\n", symbol_name); | |
17167 | ||
17168 | fprintf (file, "\tlis r11,ha16(%s)\n", lazy_ptr_name); | |
17169 | fprintf (file, "\tlwzu r12,lo16(%s)(r11)\n", lazy_ptr_name); | |
17170 | fprintf (file, "\tmtctr r12\n"); | |
17171 | fprintf (file, "\tbctr\n"); | |
17172 | } | |
f676971a | 17173 | |
ee890fe2 SS |
17174 | machopic_lazy_symbol_ptr_section (); |
17175 | fprintf (file, "%s:\n", lazy_ptr_name); | |
17176 | fprintf (file, "\t.indirect_symbol %s\n", symbol_name); | |
49bd1d27 SS |
17177 | fprintf (file, "%sdyld_stub_binding_helper\n", |
17178 | (TARGET_64BIT ? DOUBLE_INT_ASM_OP : "\t.long\t")); | |
ee890fe2 SS |
17179 | } |
17180 | ||
17181 | /* Legitimize PIC addresses. If the address is already | |
17182 | position-independent, we return ORIG. Newly generated | |
17183 | position-independent addresses go into a reg. This is REG if non | |
17184 | zero, otherwise we allocate register(s) as necessary. */ | |
17185 | ||
c859cda6 | 17186 | #define SMALL_INT(X) ((unsigned) (INTVAL(X) + 0x8000) < 0x10000) |
ee890fe2 SS |
17187 | |
17188 | rtx | |
f676971a | 17189 | rs6000_machopic_legitimize_pic_address (rtx orig, enum machine_mode mode, |
a2369ed3 | 17190 | rtx reg) |
ee890fe2 SS |
17191 | { |
17192 | rtx base, offset; | |
17193 | ||
17194 | if (reg == NULL && ! reload_in_progress && ! reload_completed) | |
17195 | reg = gen_reg_rtx (Pmode); | |
17196 | ||
17197 | if (GET_CODE (orig) == CONST) | |
17198 | { | |
17199 | if (GET_CODE (XEXP (orig, 0)) == PLUS | |
17200 | && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx) | |
17201 | return orig; | |
17202 | ||
17203 | if (GET_CODE (XEXP (orig, 0)) == PLUS) | |
17204 | { | |
2cf520bf | 17205 | /* Use a different reg for the intermediate value, as |
a3c9585f | 17206 | it will be marked UNCHANGING. */ |
2cf520bf GK |
17207 | rtx reg_temp = no_new_pseudos ? reg : gen_reg_rtx (Pmode); |
17208 | ||
a4f6c312 SS |
17209 | base = |
17210 | rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 0), | |
2cf520bf | 17211 | Pmode, reg_temp); |
a4f6c312 SS |
17212 | offset = |
17213 | rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 1), | |
17214 | Pmode, reg); | |
ee890fe2 SS |
17215 | } |
17216 | else | |
17217 | abort (); | |
17218 | ||
17219 | if (GET_CODE (offset) == CONST_INT) | |
17220 | { | |
17221 | if (SMALL_INT (offset)) | |
ed8908e7 | 17222 | return plus_constant (base, INTVAL (offset)); |
ee890fe2 SS |
17223 | else if (! reload_in_progress && ! reload_completed) |
17224 | offset = force_reg (Pmode, offset); | |
17225 | else | |
c859cda6 DJ |
17226 | { |
17227 | rtx mem = force_const_mem (Pmode, orig); | |
17228 | return machopic_legitimize_pic_address (mem, Pmode, reg); | |
17229 | } | |
ee890fe2 | 17230 | } |
f1c25d3b | 17231 | return gen_rtx_PLUS (Pmode, base, offset); |
ee890fe2 SS |
17232 | } |
17233 | ||
17234 | /* Fall back on generic machopic code. */ | |
17235 | return machopic_legitimize_pic_address (orig, mode, reg); | |
17236 | } | |
17237 | ||
17238 | /* This is just a placeholder to make linking work without having to | |
17239 | add this to the generic Darwin EXTRA_SECTIONS. If -mcall-aix is | |
17240 | ever needed for Darwin (not too likely!) this would have to get a | |
17241 | real definition. */ | |
17242 | ||
17243 | void | |
863d938c | 17244 | toc_section (void) |
ee890fe2 SS |
17245 | { |
17246 | } | |
17247 | ||
c4e18b1c GK |
17248 | /* Output a .machine directive for the Darwin assembler, and call |
17249 | the generic start_file routine. */ | |
17250 | ||
17251 | static void | |
17252 | rs6000_darwin_file_start (void) | |
17253 | { | |
17254 | static const struct | |
17255 | { | |
17256 | const char *arg; | |
17257 | const char *name; | |
17258 | int if_set; | |
17259 | } mapping[] = { | |
17260 | { "970", "ppc970", MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64 }, | |
17261 | { "power4", "ppc970", 0 }, | |
17262 | { "G5", "ppc970", 0 }, | |
17263 | { "7450", "ppc7450", 0 }, | |
17264 | { "7400", "ppc7400", MASK_ALTIVEC }, | |
17265 | { "G4", "ppc7400", 0 }, | |
17266 | { "750", "ppc750", 0 }, | |
17267 | { "740", "ppc750", 0 }, | |
17268 | { "G3", "ppc750", 0 }, | |
17269 | { "604e", "ppc604e", 0 }, | |
17270 | { "604", "ppc604", 0 }, | |
17271 | { "603e", "ppc603", 0 }, | |
17272 | { "603", "ppc603", 0 }, | |
17273 | { "601", "ppc601", 0 }, | |
17274 | { NULL, "ppc", 0 } }; | |
17275 | const char *cpu_id = ""; | |
17276 | size_t i; | |
17277 | ||
17278 | rs6000_file_start(); | |
17279 | ||
17280 | /* Determine the argument to -mcpu=. Default to G3 if not specified. */ | |
17281 | for (i = 0; i < ARRAY_SIZE (rs6000_select); i++) | |
17282 | if (rs6000_select[i].set_arch_p && rs6000_select[i].string | |
17283 | && rs6000_select[i].string[0] != '\0') | |
17284 | cpu_id = rs6000_select[i].string; | |
17285 | ||
17286 | /* Look through the mapping array. Pick the first name that either | |
17287 | matches the argument, has a bit set in IF_SET that is also set | |
17288 | in the target flags, or has a NULL name. */ | |
17289 | ||
17290 | i = 0; | |
17291 | while (mapping[i].arg != NULL | |
17292 | && strcmp (mapping[i].arg, cpu_id) != 0 | |
17293 | && (mapping[i].if_set & target_flags) == 0) | |
17294 | i++; | |
17295 | ||
17296 | fprintf (asm_out_file, "\t.machine %s\n", mapping[i].name); | |
17297 | } | |
17298 | ||
ee890fe2 | 17299 | #endif /* TARGET_MACHO */ |
7c262518 RH |
17300 | |
17301 | #if TARGET_ELF | |
17302 | static unsigned int | |
a2369ed3 | 17303 | rs6000_elf_section_type_flags (tree decl, const char *name, int reloc) |
7c262518 | 17304 | { |
1ff8f81a AM |
17305 | return default_section_type_flags_1 (decl, name, reloc, |
17306 | flag_pic || DEFAULT_ABI == ABI_AIX); | |
7c262518 | 17307 | } |
d9f6800d RH |
17308 | |
17309 | /* Record an element in the table of global constructors. SYMBOL is | |
17310 | a SYMBOL_REF of the function to be called; PRIORITY is a number | |
17311 | between 0 and MAX_INIT_PRIORITY. | |
17312 | ||
17313 | This differs from default_named_section_asm_out_constructor in | |
17314 | that we have special handling for -mrelocatable. */ | |
17315 | ||
17316 | static void | |
a2369ed3 | 17317 | rs6000_elf_asm_out_constructor (rtx symbol, int priority) |
d9f6800d RH |
17318 | { |
17319 | const char *section = ".ctors"; | |
17320 | char buf[16]; | |
17321 | ||
17322 | if (priority != DEFAULT_INIT_PRIORITY) | |
17323 | { | |
17324 | sprintf (buf, ".ctors.%.5u", | |
c4ad648e AM |
17325 | /* Invert the numbering so the linker puts us in the proper |
17326 | order; constructors are run from right to left, and the | |
17327 | linker sorts in increasing order. */ | |
17328 | MAX_INIT_PRIORITY - priority); | |
d9f6800d RH |
17329 | section = buf; |
17330 | } | |
17331 | ||
715bdd29 RH |
17332 | named_section_flags (section, SECTION_WRITE); |
17333 | assemble_align (POINTER_SIZE); | |
d9f6800d RH |
17334 | |
17335 | if (TARGET_RELOCATABLE) | |
17336 | { | |
17337 | fputs ("\t.long (", asm_out_file); | |
17338 | output_addr_const (asm_out_file, symbol); | |
17339 | fputs (")@fixup\n", asm_out_file); | |
17340 | } | |
17341 | else | |
c8af3574 | 17342 | assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1); |
d9f6800d RH |
17343 | } |
17344 | ||
17345 | static void | |
a2369ed3 | 17346 | rs6000_elf_asm_out_destructor (rtx symbol, int priority) |
d9f6800d RH |
17347 | { |
17348 | const char *section = ".dtors"; | |
17349 | char buf[16]; | |
17350 | ||
17351 | if (priority != DEFAULT_INIT_PRIORITY) | |
17352 | { | |
17353 | sprintf (buf, ".dtors.%.5u", | |
c4ad648e AM |
17354 | /* Invert the numbering so the linker puts us in the proper |
17355 | order; constructors are run from right to left, and the | |
17356 | linker sorts in increasing order. */ | |
17357 | MAX_INIT_PRIORITY - priority); | |
d9f6800d RH |
17358 | section = buf; |
17359 | } | |
17360 | ||
715bdd29 RH |
17361 | named_section_flags (section, SECTION_WRITE); |
17362 | assemble_align (POINTER_SIZE); | |
d9f6800d RH |
17363 | |
17364 | if (TARGET_RELOCATABLE) | |
17365 | { | |
17366 | fputs ("\t.long (", asm_out_file); | |
17367 | output_addr_const (asm_out_file, symbol); | |
17368 | fputs (")@fixup\n", asm_out_file); | |
17369 | } | |
17370 | else | |
c8af3574 | 17371 | assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1); |
d9f6800d | 17372 | } |
9739c90c JJ |
17373 | |
17374 | void | |
a2369ed3 | 17375 | rs6000_elf_declare_function_name (FILE *file, const char *name, tree decl) |
9739c90c JJ |
17376 | { |
17377 | if (TARGET_64BIT) | |
17378 | { | |
17379 | fputs ("\t.section\t\".opd\",\"aw\"\n\t.align 3\n", file); | |
17380 | ASM_OUTPUT_LABEL (file, name); | |
17381 | fputs (DOUBLE_INT_ASM_OP, file); | |
85b776df AM |
17382 | rs6000_output_function_entry (file, name); |
17383 | fputs (",.TOC.@tocbase,0\n\t.previous\n", file); | |
17384 | if (DOT_SYMBOLS) | |
9739c90c | 17385 | { |
85b776df | 17386 | fputs ("\t.size\t", file); |
9739c90c | 17387 | assemble_name (file, name); |
85b776df AM |
17388 | fputs (",24\n\t.type\t.", file); |
17389 | assemble_name (file, name); | |
17390 | fputs (",@function\n", file); | |
17391 | if (TREE_PUBLIC (decl) && ! DECL_WEAK (decl)) | |
17392 | { | |
17393 | fputs ("\t.globl\t.", file); | |
17394 | assemble_name (file, name); | |
17395 | putc ('\n', file); | |
17396 | } | |
9739c90c | 17397 | } |
85b776df AM |
17398 | else |
17399 | ASM_OUTPUT_TYPE_DIRECTIVE (file, name, "function"); | |
9739c90c | 17400 | ASM_DECLARE_RESULT (file, DECL_RESULT (decl)); |
85b776df AM |
17401 | rs6000_output_function_entry (file, name); |
17402 | fputs (":\n", file); | |
9739c90c JJ |
17403 | return; |
17404 | } | |
17405 | ||
17406 | if (TARGET_RELOCATABLE | |
17407 | && (get_pool_size () != 0 || current_function_profile) | |
3c9eb5f4 | 17408 | && uses_TOC ()) |
9739c90c JJ |
17409 | { |
17410 | char buf[256]; | |
17411 | ||
17412 | (*targetm.asm_out.internal_label) (file, "LCL", rs6000_pic_labelno); | |
17413 | ||
17414 | ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1); | |
17415 | fprintf (file, "\t.long "); | |
17416 | assemble_name (file, buf); | |
17417 | putc ('-', file); | |
17418 | ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno); | |
17419 | assemble_name (file, buf); | |
17420 | putc ('\n', file); | |
17421 | } | |
17422 | ||
17423 | ASM_OUTPUT_TYPE_DIRECTIVE (file, name, "function"); | |
17424 | ASM_DECLARE_RESULT (file, DECL_RESULT (decl)); | |
17425 | ||
17426 | if (DEFAULT_ABI == ABI_AIX) | |
17427 | { | |
17428 | const char *desc_name, *orig_name; | |
17429 | ||
17430 | orig_name = (*targetm.strip_name_encoding) (name); | |
17431 | desc_name = orig_name; | |
17432 | while (*desc_name == '.') | |
17433 | desc_name++; | |
17434 | ||
17435 | if (TREE_PUBLIC (decl)) | |
17436 | fprintf (file, "\t.globl %s\n", desc_name); | |
17437 | ||
17438 | fprintf (file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP); | |
17439 | fprintf (file, "%s:\n", desc_name); | |
17440 | fprintf (file, "\t.long %s\n", orig_name); | |
17441 | fputs ("\t.long _GLOBAL_OFFSET_TABLE_\n", file); | |
17442 | if (DEFAULT_ABI == ABI_AIX) | |
17443 | fputs ("\t.long 0\n", file); | |
17444 | fprintf (file, "\t.previous\n"); | |
17445 | } | |
17446 | ASM_OUTPUT_LABEL (file, name); | |
17447 | } | |
7c262518 RH |
17448 | #endif |
17449 | ||
cbaaba19 | 17450 | #if TARGET_XCOFF |
7c262518 | 17451 | static void |
a2369ed3 | 17452 | rs6000_xcoff_asm_globalize_label (FILE *stream, const char *name) |
b275d088 DE |
17453 | { |
17454 | fputs (GLOBAL_ASM_OP, stream); | |
17455 | RS6000_OUTPUT_BASENAME (stream, name); | |
17456 | putc ('\n', stream); | |
17457 | } | |
17458 | ||
17459 | static void | |
c18a5b6c MM |
17460 | rs6000_xcoff_asm_named_section (const char *name, unsigned int flags, |
17461 | tree decl ATTRIBUTE_UNUSED) | |
7c262518 | 17462 | { |
0e5dbd9b DE |
17463 | int smclass; |
17464 | static const char * const suffix[3] = { "PR", "RO", "RW" }; | |
17465 | ||
17466 | if (flags & SECTION_CODE) | |
17467 | smclass = 0; | |
17468 | else if (flags & SECTION_WRITE) | |
17469 | smclass = 2; | |
17470 | else | |
17471 | smclass = 1; | |
17472 | ||
5b5198f7 | 17473 | fprintf (asm_out_file, "\t.csect %s%s[%s],%u\n", |
0e5dbd9b | 17474 | (flags & SECTION_CODE) ? "." : "", |
5b5198f7 | 17475 | name, suffix[smclass], flags & SECTION_ENTSIZE); |
7c262518 | 17476 | } |
ae46c4e0 RH |
17477 | |
17478 | static void | |
f676971a | 17479 | rs6000_xcoff_select_section (tree decl, int reloc, |
c4ad648e | 17480 | unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED) |
ae46c4e0 | 17481 | { |
5add3202 | 17482 | if (decl_readonly_section_1 (decl, reloc, 1)) |
ae46c4e0 | 17483 | { |
0e5dbd9b | 17484 | if (TREE_PUBLIC (decl)) |
c4ad648e | 17485 | read_only_data_section (); |
ae46c4e0 | 17486 | else |
c4ad648e | 17487 | read_only_private_data_section (); |
ae46c4e0 RH |
17488 | } |
17489 | else | |
17490 | { | |
0e5dbd9b | 17491 | if (TREE_PUBLIC (decl)) |
c4ad648e | 17492 | data_section (); |
ae46c4e0 | 17493 | else |
c4ad648e | 17494 | private_data_section (); |
ae46c4e0 RH |
17495 | } |
17496 | } | |
17497 | ||
17498 | static void | |
a2369ed3 | 17499 | rs6000_xcoff_unique_section (tree decl, int reloc ATTRIBUTE_UNUSED) |
ae46c4e0 RH |
17500 | { |
17501 | const char *name; | |
ae46c4e0 | 17502 | |
5b5198f7 DE |
17503 | /* Use select_section for private and uninitialized data. */ |
17504 | if (!TREE_PUBLIC (decl) | |
17505 | || DECL_COMMON (decl) | |
0e5dbd9b DE |
17506 | || DECL_INITIAL (decl) == NULL_TREE |
17507 | || DECL_INITIAL (decl) == error_mark_node | |
17508 | || (flag_zero_initialized_in_bss | |
17509 | && initializer_zerop (DECL_INITIAL (decl)))) | |
17510 | return; | |
17511 | ||
17512 | name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl)); | |
17513 | name = (*targetm.strip_name_encoding) (name); | |
17514 | DECL_SECTION_NAME (decl) = build_string (strlen (name), name); | |
ae46c4e0 | 17515 | } |
b64a1b53 | 17516 | |
fb49053f RH |
17517 | /* Select section for constant in constant pool. |
17518 | ||
17519 | On RS/6000, all constants are in the private read-only data area. | |
17520 | However, if this is being placed in the TOC it must be output as a | |
17521 | toc entry. */ | |
17522 | ||
b64a1b53 | 17523 | static void |
f676971a | 17524 | rs6000_xcoff_select_rtx_section (enum machine_mode mode, rtx x, |
c4ad648e | 17525 | unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED) |
b64a1b53 RH |
17526 | { |
17527 | if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode)) | |
17528 | toc_section (); | |
17529 | else | |
17530 | read_only_private_data_section (); | |
17531 | } | |
772c5265 RH |
17532 | |
17533 | /* Remove any trailing [DS] or the like from the symbol name. */ | |
17534 | ||
17535 | static const char * | |
a2369ed3 | 17536 | rs6000_xcoff_strip_name_encoding (const char *name) |
772c5265 RH |
17537 | { |
17538 | size_t len; | |
17539 | if (*name == '*') | |
17540 | name++; | |
17541 | len = strlen (name); | |
17542 | if (name[len - 1] == ']') | |
17543 | return ggc_alloc_string (name, len - 4); | |
17544 | else | |
17545 | return name; | |
17546 | } | |
17547 | ||
5add3202 DE |
17548 | /* Section attributes. AIX is always PIC. */ |
17549 | ||
17550 | static unsigned int | |
a2369ed3 | 17551 | rs6000_xcoff_section_type_flags (tree decl, const char *name, int reloc) |
5add3202 | 17552 | { |
5b5198f7 DE |
17553 | unsigned int align; |
17554 | unsigned int flags = default_section_type_flags_1 (decl, name, reloc, 1); | |
17555 | ||
17556 | /* Align to at least UNIT size. */ | |
17557 | if (flags & SECTION_CODE) | |
17558 | align = MIN_UNITS_PER_WORD; | |
17559 | else | |
17560 | /* Increase alignment of large objects if not already stricter. */ | |
17561 | align = MAX ((DECL_ALIGN (decl) / BITS_PER_UNIT), | |
17562 | int_size_in_bytes (TREE_TYPE (decl)) > MIN_UNITS_PER_WORD | |
17563 | ? UNITS_PER_FP_WORD : MIN_UNITS_PER_WORD); | |
17564 | ||
17565 | return flags | (exact_log2 (align) & SECTION_ENTSIZE); | |
5add3202 | 17566 | } |
a5fe455b | 17567 | |
1bc7c5b6 ZW |
17568 | /* Output at beginning of assembler file. |
17569 | ||
17570 | Initialize the section names for the RS/6000 at this point. | |
17571 | ||
17572 | Specify filename, including full path, to assembler. | |
17573 | ||
17574 | We want to go into the TOC section so at least one .toc will be emitted. | |
17575 | Also, in order to output proper .bs/.es pairs, we need at least one static | |
17576 | [RW] section emitted. | |
17577 | ||
17578 | Finally, declare mcount when profiling to make the assembler happy. */ | |
17579 | ||
17580 | static void | |
863d938c | 17581 | rs6000_xcoff_file_start (void) |
1bc7c5b6 ZW |
17582 | { |
17583 | rs6000_gen_section_name (&xcoff_bss_section_name, | |
17584 | main_input_filename, ".bss_"); | |
17585 | rs6000_gen_section_name (&xcoff_private_data_section_name, | |
17586 | main_input_filename, ".rw_"); | |
17587 | rs6000_gen_section_name (&xcoff_read_only_section_name, | |
17588 | main_input_filename, ".ro_"); | |
17589 | ||
17590 | fputs ("\t.file\t", asm_out_file); | |
17591 | output_quoted_string (asm_out_file, main_input_filename); | |
17592 | fputc ('\n', asm_out_file); | |
17593 | toc_section (); | |
17594 | if (write_symbols != NO_DEBUG) | |
17595 | private_data_section (); | |
17596 | text_section (); | |
17597 | if (profile_flag) | |
17598 | fprintf (asm_out_file, "\t.extern %s\n", RS6000_MCOUNT); | |
17599 | rs6000_file_start (); | |
17600 | } | |
17601 | ||
a5fe455b ZW |
17602 | /* Output at end of assembler file. |
17603 | On the RS/6000, referencing data should automatically pull in text. */ | |
17604 | ||
17605 | static void | |
863d938c | 17606 | rs6000_xcoff_file_end (void) |
a5fe455b ZW |
17607 | { |
17608 | text_section (); | |
17609 | fputs ("_section_.text:\n", asm_out_file); | |
17610 | data_section (); | |
17611 | fputs (TARGET_32BIT | |
17612 | ? "\t.long _section_.text\n" : "\t.llong _section_.text\n", | |
17613 | asm_out_file); | |
17614 | } | |
f1384257 | 17615 | #endif /* TARGET_XCOFF */ |
0e5dbd9b | 17616 | |
f1384257 AM |
17617 | #if TARGET_MACHO |
17618 | /* Cross-module name binding. Darwin does not support overriding | |
7f3d8013 | 17619 | functions at dynamic-link time. */ |
0e5dbd9b | 17620 | |
2bcc50d0 | 17621 | static bool |
a2369ed3 | 17622 | rs6000_binds_local_p (tree decl) |
0e5dbd9b | 17623 | { |
f1384257 | 17624 | return default_binds_local_p_1 (decl, 0); |
0e5dbd9b | 17625 | } |
f1384257 | 17626 | #endif |
34bb030a | 17627 | |
3c50106f RH |
17628 | /* Compute a (partial) cost for rtx X. Return true if the complete |
17629 | cost has been computed, and false if subexpressions should be | |
17630 | scanned. In either case, *TOTAL contains the cost result. */ | |
17631 | ||
17632 | static bool | |
1494c534 | 17633 | rs6000_rtx_costs (rtx x, int code, int outer_code, int *total) |
3c50106f | 17634 | { |
f0517163 RS |
17635 | enum machine_mode mode = GET_MODE (x); |
17636 | ||
3c50106f RH |
17637 | switch (code) |
17638 | { | |
30a555d9 | 17639 | /* On the RS/6000, if it is valid in the insn, it is free. */ |
3c50106f | 17640 | case CONST_INT: |
066cd967 DE |
17641 | if (((outer_code == SET |
17642 | || outer_code == PLUS | |
17643 | || outer_code == MINUS) | |
17644 | && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'I') | |
17645 | || CONST_OK_FOR_LETTER_P (INTVAL (x), 'L'))) | |
17646 | || ((outer_code == IOR || outer_code == XOR) | |
17647 | && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'K') | |
17648 | || CONST_OK_FOR_LETTER_P (INTVAL (x), 'L'))) | |
627b6fe2 DJ |
17649 | || ((outer_code == DIV || outer_code == UDIV |
17650 | || outer_code == MOD || outer_code == UMOD) | |
17651 | && exact_log2 (INTVAL (x)) >= 0) | |
066cd967 DE |
17652 | || (outer_code == AND |
17653 | && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'K') | |
17654 | || CONST_OK_FOR_LETTER_P (INTVAL (x), 'L') | |
d5861a7a | 17655 | || mask_operand (x, VOIDmode))) |
066cd967 DE |
17656 | || outer_code == ASHIFT |
17657 | || outer_code == ASHIFTRT | |
17658 | || outer_code == LSHIFTRT | |
17659 | || outer_code == ROTATE | |
17660 | || outer_code == ROTATERT | |
d5861a7a | 17661 | || outer_code == ZERO_EXTRACT |
066cd967 DE |
17662 | || (outer_code == MULT |
17663 | && CONST_OK_FOR_LETTER_P (INTVAL (x), 'I')) | |
17664 | || (outer_code == COMPARE | |
17665 | && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'I') | |
17666 | || CONST_OK_FOR_LETTER_P (INTVAL (x), 'K')))) | |
17667 | { | |
17668 | *total = 0; | |
17669 | return true; | |
17670 | } | |
17671 | else if ((outer_code == PLUS | |
17672 | && reg_or_add_cint64_operand (x, VOIDmode)) | |
17673 | || (outer_code == MINUS | |
17674 | && reg_or_sub_cint64_operand (x, VOIDmode)) | |
17675 | || ((outer_code == SET | |
17676 | || outer_code == IOR | |
17677 | || outer_code == XOR) | |
17678 | && (INTVAL (x) | |
17679 | & ~ (unsigned HOST_WIDE_INT) 0xffffffff) == 0)) | |
17680 | { | |
17681 | *total = COSTS_N_INSNS (1); | |
17682 | return true; | |
17683 | } | |
17684 | /* FALLTHRU */ | |
17685 | ||
17686 | case CONST_DOUBLE: | |
17687 | if (mode == DImode | |
17688 | && ((outer_code == AND | |
17689 | && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'K') | |
17690 | || CONST_OK_FOR_LETTER_P (INTVAL (x), 'L') | |
d5861a7a | 17691 | || mask64_operand (x, DImode))) |
066cd967 DE |
17692 | || ((outer_code == IOR || outer_code == XOR) |
17693 | && CONST_DOUBLE_HIGH (x) == 0 | |
17694 | && (CONST_DOUBLE_LOW (x) | |
17695 | & ~ (unsigned HOST_WIDE_INT) 0xffff) == 0))) | |
17696 | { | |
17697 | *total = 0; | |
17698 | return true; | |
17699 | } | |
17700 | else if (mode == DImode | |
17701 | && (outer_code == SET | |
17702 | || outer_code == IOR | |
17703 | || outer_code == XOR) | |
17704 | && CONST_DOUBLE_HIGH (x) == 0) | |
17705 | { | |
17706 | *total = COSTS_N_INSNS (1); | |
17707 | return true; | |
17708 | } | |
17709 | /* FALLTHRU */ | |
17710 | ||
3c50106f | 17711 | case CONST: |
066cd967 | 17712 | case HIGH: |
3c50106f | 17713 | case SYMBOL_REF: |
066cd967 DE |
17714 | case MEM: |
17715 | /* When optimizing for size, MEM should be slightly more expensive | |
17716 | than generating address, e.g., (plus (reg) (const)). | |
c112cf2b | 17717 | L1 cache latency is about two instructions. */ |
066cd967 | 17718 | *total = optimize_size ? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (2); |
3c50106f RH |
17719 | return true; |
17720 | ||
30a555d9 DE |
17721 | case LABEL_REF: |
17722 | *total = 0; | |
17723 | return true; | |
17724 | ||
3c50106f | 17725 | case PLUS: |
f0517163 | 17726 | if (mode == DFmode) |
066cd967 DE |
17727 | { |
17728 | if (GET_CODE (XEXP (x, 0)) == MULT) | |
17729 | { | |
17730 | /* FNMA accounted in outer NEG. */ | |
17731 | if (outer_code == NEG) | |
17732 | *total = rs6000_cost->dmul - rs6000_cost->fp; | |
17733 | else | |
17734 | *total = rs6000_cost->dmul; | |
17735 | } | |
17736 | else | |
17737 | *total = rs6000_cost->fp; | |
17738 | } | |
f0517163 | 17739 | else if (mode == SFmode) |
066cd967 DE |
17740 | { |
17741 | /* FNMA accounted in outer NEG. */ | |
17742 | if (outer_code == NEG && GET_CODE (XEXP (x, 0)) == MULT) | |
17743 | *total = 0; | |
17744 | else | |
17745 | *total = rs6000_cost->fp; | |
17746 | } | |
938bf747 RS |
17747 | else if (GET_CODE (XEXP (x, 0)) == MULT) |
17748 | { | |
17749 | /* The rs6000 doesn't have shift-and-add instructions. */ | |
17750 | rs6000_rtx_costs (XEXP (x, 0), MULT, PLUS, total); | |
17751 | *total += COSTS_N_INSNS (1); | |
17752 | } | |
f0517163 | 17753 | else |
066cd967 DE |
17754 | *total = COSTS_N_INSNS (1); |
17755 | return false; | |
3c50106f | 17756 | |
52190329 | 17757 | case MINUS: |
f0517163 | 17758 | if (mode == DFmode) |
066cd967 DE |
17759 | { |
17760 | if (GET_CODE (XEXP (x, 0)) == MULT) | |
17761 | { | |
17762 | /* FNMA accounted in outer NEG. */ | |
17763 | if (outer_code == NEG) | |
17764 | *total = 0; | |
17765 | else | |
17766 | *total = rs6000_cost->dmul; | |
17767 | } | |
17768 | else | |
17769 | *total = rs6000_cost->fp; | |
17770 | } | |
f0517163 | 17771 | else if (mode == SFmode) |
066cd967 DE |
17772 | { |
17773 | /* FNMA accounted in outer NEG. */ | |
17774 | if (outer_code == NEG && GET_CODE (XEXP (x, 0)) == MULT) | |
17775 | *total = 0; | |
17776 | else | |
17777 | *total = rs6000_cost->fp; | |
17778 | } | |
938bf747 RS |
17779 | else if (GET_CODE (XEXP (x, 0)) == MULT) |
17780 | { | |
17781 | /* The rs6000 doesn't have shift-and-sub instructions. */ | |
17782 | rs6000_rtx_costs (XEXP (x, 0), MULT, MINUS, total); | |
17783 | *total += COSTS_N_INSNS (1); | |
17784 | } | |
f0517163 | 17785 | else |
c4ad648e | 17786 | *total = COSTS_N_INSNS (1); |
066cd967 | 17787 | return false; |
3c50106f RH |
17788 | |
17789 | case MULT: | |
8b897cfa | 17790 | if (GET_CODE (XEXP (x, 1)) == CONST_INT) |
3c50106f | 17791 | { |
8b897cfa RS |
17792 | if (INTVAL (XEXP (x, 1)) >= -256 |
17793 | && INTVAL (XEXP (x, 1)) <= 255) | |
06a67bdd | 17794 | *total = rs6000_cost->mulsi_const9; |
8b897cfa | 17795 | else |
06a67bdd | 17796 | *total = rs6000_cost->mulsi_const; |
3c50106f | 17797 | } |
066cd967 DE |
17798 | /* FMA accounted in outer PLUS/MINUS. */ |
17799 | else if ((mode == DFmode || mode == SFmode) | |
17800 | && (outer_code == PLUS || outer_code == MINUS)) | |
17801 | *total = 0; | |
f0517163 | 17802 | else if (mode == DFmode) |
06a67bdd | 17803 | *total = rs6000_cost->dmul; |
f0517163 | 17804 | else if (mode == SFmode) |
06a67bdd | 17805 | *total = rs6000_cost->fp; |
f0517163 | 17806 | else if (mode == DImode) |
06a67bdd | 17807 | *total = rs6000_cost->muldi; |
8b897cfa | 17808 | else |
06a67bdd | 17809 | *total = rs6000_cost->mulsi; |
066cd967 | 17810 | return false; |
3c50106f RH |
17811 | |
17812 | case DIV: | |
17813 | case MOD: | |
f0517163 RS |
17814 | if (FLOAT_MODE_P (mode)) |
17815 | { | |
06a67bdd RS |
17816 | *total = mode == DFmode ? rs6000_cost->ddiv |
17817 | : rs6000_cost->sdiv; | |
066cd967 | 17818 | return false; |
f0517163 | 17819 | } |
5efb1046 | 17820 | /* FALLTHRU */ |
3c50106f RH |
17821 | |
17822 | case UDIV: | |
17823 | case UMOD: | |
627b6fe2 DJ |
17824 | if (GET_CODE (XEXP (x, 1)) == CONST_INT |
17825 | && exact_log2 (INTVAL (XEXP (x, 1))) >= 0) | |
17826 | { | |
17827 | if (code == DIV || code == MOD) | |
17828 | /* Shift, addze */ | |
17829 | *total = COSTS_N_INSNS (2); | |
17830 | else | |
17831 | /* Shift */ | |
17832 | *total = COSTS_N_INSNS (1); | |
17833 | } | |
c4ad648e | 17834 | else |
627b6fe2 DJ |
17835 | { |
17836 | if (GET_MODE (XEXP (x, 1)) == DImode) | |
17837 | *total = rs6000_cost->divdi; | |
17838 | else | |
17839 | *total = rs6000_cost->divsi; | |
17840 | } | |
17841 | /* Add in shift and subtract for MOD. */ | |
17842 | if (code == MOD || code == UMOD) | |
17843 | *total += COSTS_N_INSNS (2); | |
066cd967 | 17844 | return false; |
3c50106f RH |
17845 | |
17846 | case FFS: | |
17847 | *total = COSTS_N_INSNS (4); | |
066cd967 | 17848 | return false; |
3c50106f | 17849 | |
06a67bdd | 17850 | case NOT: |
066cd967 DE |
17851 | if (outer_code == AND || outer_code == IOR || outer_code == XOR) |
17852 | { | |
17853 | *total = 0; | |
17854 | return false; | |
17855 | } | |
17856 | /* FALLTHRU */ | |
17857 | ||
17858 | case AND: | |
17859 | case IOR: | |
17860 | case XOR: | |
d5861a7a DE |
17861 | case ZERO_EXTRACT: |
17862 | *total = COSTS_N_INSNS (1); | |
17863 | return false; | |
17864 | ||
066cd967 DE |
17865 | case ASHIFT: |
17866 | case ASHIFTRT: | |
17867 | case LSHIFTRT: | |
17868 | case ROTATE: | |
17869 | case ROTATERT: | |
d5861a7a | 17870 | /* Handle mul_highpart. */ |
066cd967 DE |
17871 | if (outer_code == TRUNCATE |
17872 | && GET_CODE (XEXP (x, 0)) == MULT) | |
17873 | { | |
17874 | if (mode == DImode) | |
17875 | *total = rs6000_cost->muldi; | |
17876 | else | |
17877 | *total = rs6000_cost->mulsi; | |
17878 | return true; | |
17879 | } | |
d5861a7a DE |
17880 | else if (outer_code == AND) |
17881 | *total = 0; | |
17882 | else | |
17883 | *total = COSTS_N_INSNS (1); | |
17884 | return false; | |
17885 | ||
17886 | case SIGN_EXTEND: | |
17887 | case ZERO_EXTEND: | |
17888 | if (GET_CODE (XEXP (x, 0)) == MEM) | |
17889 | *total = 0; | |
17890 | else | |
17891 | *total = COSTS_N_INSNS (1); | |
066cd967 | 17892 | return false; |
06a67bdd | 17893 | |
066cd967 DE |
17894 | case COMPARE: |
17895 | case NEG: | |
17896 | case ABS: | |
17897 | if (!FLOAT_MODE_P (mode)) | |
17898 | { | |
17899 | *total = COSTS_N_INSNS (1); | |
17900 | return false; | |
17901 | } | |
17902 | /* FALLTHRU */ | |
17903 | ||
17904 | case FLOAT: | |
17905 | case UNSIGNED_FLOAT: | |
17906 | case FIX: | |
17907 | case UNSIGNED_FIX: | |
17908 | case FLOAT_EXTEND: | |
06a67bdd RS |
17909 | case FLOAT_TRUNCATE: |
17910 | *total = rs6000_cost->fp; | |
066cd967 | 17911 | return false; |
06a67bdd RS |
17912 | |
17913 | case UNSPEC: | |
17914 | switch (XINT (x, 1)) | |
17915 | { | |
17916 | case UNSPEC_FRSP: | |
17917 | *total = rs6000_cost->fp; | |
17918 | return true; | |
17919 | ||
17920 | default: | |
17921 | break; | |
17922 | } | |
17923 | break; | |
17924 | ||
17925 | case CALL: | |
17926 | case IF_THEN_ELSE: | |
17927 | if (optimize_size) | |
17928 | { | |
17929 | *total = COSTS_N_INSNS (1); | |
17930 | return true; | |
17931 | } | |
066cd967 DE |
17932 | else if (FLOAT_MODE_P (mode) |
17933 | && TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS) | |
17934 | { | |
17935 | *total = rs6000_cost->fp; | |
17936 | return false; | |
17937 | } | |
17938 | ||
06a67bdd RS |
17939 | break; |
17940 | ||
3c50106f | 17941 | default: |
06a67bdd | 17942 | break; |
3c50106f | 17943 | } |
06a67bdd RS |
17944 | |
17945 | return false; | |
3c50106f RH |
17946 | } |
17947 | ||
34bb030a DE |
17948 | /* A C expression returning the cost of moving data from a register of class |
17949 | CLASS1 to one of CLASS2. */ | |
17950 | ||
17951 | int | |
f676971a | 17952 | rs6000_register_move_cost (enum machine_mode mode, |
a2369ed3 | 17953 | enum reg_class from, enum reg_class to) |
34bb030a DE |
17954 | { |
17955 | /* Moves from/to GENERAL_REGS. */ | |
17956 | if (reg_classes_intersect_p (to, GENERAL_REGS) | |
17957 | || reg_classes_intersect_p (from, GENERAL_REGS)) | |
17958 | { | |
17959 | if (! reg_classes_intersect_p (to, GENERAL_REGS)) | |
17960 | from = to; | |
17961 | ||
17962 | if (from == FLOAT_REGS || from == ALTIVEC_REGS) | |
17963 | return (rs6000_memory_move_cost (mode, from, 0) | |
17964 | + rs6000_memory_move_cost (mode, GENERAL_REGS, 0)); | |
17965 | ||
c4ad648e AM |
17966 | /* It's more expensive to move CR_REGS than CR0_REGS because of the |
17967 | shift. */ | |
34bb030a DE |
17968 | else if (from == CR_REGS) |
17969 | return 4; | |
17970 | ||
17971 | else | |
c4ad648e | 17972 | /* A move will cost one instruction per GPR moved. */ |
34bb030a DE |
17973 | return 2 * HARD_REGNO_NREGS (0, mode); |
17974 | } | |
17975 | ||
c4ad648e | 17976 | /* Moving between two similar registers is just one instruction. */ |
34bb030a DE |
17977 | else if (reg_classes_intersect_p (to, from)) |
17978 | return mode == TFmode ? 4 : 2; | |
17979 | ||
c4ad648e | 17980 | /* Everything else has to go through GENERAL_REGS. */ |
34bb030a | 17981 | else |
f676971a | 17982 | return (rs6000_register_move_cost (mode, GENERAL_REGS, to) |
34bb030a DE |
17983 | + rs6000_register_move_cost (mode, from, GENERAL_REGS)); |
17984 | } | |
17985 | ||
17986 | /* A C expressions returning the cost of moving data of MODE from a register to | |
17987 | or from memory. */ | |
17988 | ||
17989 | int | |
f676971a | 17990 | rs6000_memory_move_cost (enum machine_mode mode, enum reg_class class, |
a2369ed3 | 17991 | int in ATTRIBUTE_UNUSED) |
34bb030a DE |
17992 | { |
17993 | if (reg_classes_intersect_p (class, GENERAL_REGS)) | |
17994 | return 4 * HARD_REGNO_NREGS (0, mode); | |
17995 | else if (reg_classes_intersect_p (class, FLOAT_REGS)) | |
17996 | return 4 * HARD_REGNO_NREGS (32, mode); | |
17997 | else if (reg_classes_intersect_p (class, ALTIVEC_REGS)) | |
17998 | return 4 * HARD_REGNO_NREGS (FIRST_ALTIVEC_REGNO, mode); | |
17999 | else | |
18000 | return 4 + rs6000_register_move_cost (mode, class, GENERAL_REGS); | |
18001 | } | |
18002 | ||
ded9bf77 AH |
18003 | /* Return an RTX representing where to find the function value of a |
18004 | function returning MODE. */ | |
18005 | static rtx | |
18006 | rs6000_complex_function_value (enum machine_mode mode) | |
18007 | { | |
18008 | unsigned int regno; | |
18009 | rtx r1, r2; | |
18010 | enum machine_mode inner = GET_MODE_INNER (mode); | |
fb7e4164 | 18011 | unsigned int inner_bytes = GET_MODE_SIZE (inner); |
ded9bf77 | 18012 | |
4ed78545 | 18013 | if (FLOAT_MODE_P (mode) && TARGET_HARD_FLOAT && TARGET_FPRS) |
ded9bf77 AH |
18014 | regno = FP_ARG_RETURN; |
18015 | else | |
18016 | { | |
18017 | regno = GP_ARG_RETURN; | |
18018 | ||
18019 | /* 32-bit is OK since it'll go in r3/r4. */ | |
fb7e4164 | 18020 | if (TARGET_32BIT && inner_bytes >= 4) |
ded9bf77 AH |
18021 | return gen_rtx_REG (mode, regno); |
18022 | } | |
18023 | ||
fb7e4164 AM |
18024 | if (inner_bytes >= 8) |
18025 | return gen_rtx_REG (mode, regno); | |
18026 | ||
ded9bf77 AH |
18027 | r1 = gen_rtx_EXPR_LIST (inner, gen_rtx_REG (inner, regno), |
18028 | const0_rtx); | |
18029 | r2 = gen_rtx_EXPR_LIST (inner, gen_rtx_REG (inner, regno + 1), | |
fb7e4164 | 18030 | GEN_INT (inner_bytes)); |
ded9bf77 AH |
18031 | return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r2)); |
18032 | } | |
18033 | ||
a6ebc39a AH |
18034 | /* Define how to find the value returned by a function. |
18035 | VALTYPE is the data type of the value (as a tree). | |
18036 | If the precise function being called is known, FUNC is its FUNCTION_DECL; | |
18037 | otherwise, FUNC is 0. | |
18038 | ||
18039 | On the SPE, both FPs and vectors are returned in r3. | |
18040 | ||
18041 | On RS/6000 an integer value is in r3 and a floating-point value is in | |
18042 | fp1, unless -msoft-float. */ | |
18043 | ||
18044 | rtx | |
18045 | rs6000_function_value (tree valtype, tree func ATTRIBUTE_UNUSED) | |
18046 | { | |
18047 | enum machine_mode mode; | |
2a8fa26c | 18048 | unsigned int regno; |
a6ebc39a | 18049 | |
0e67400a FJ |
18050 | if (TARGET_32BIT && TARGET_POWERPC64 && TYPE_MODE (valtype) == DImode) |
18051 | { | |
18052 | /* Long long return value need be split in -mpowerpc64, 32bit ABI. */ | |
18053 | return gen_rtx_PARALLEL (DImode, | |
18054 | gen_rtvec (2, | |
18055 | gen_rtx_EXPR_LIST (VOIDmode, | |
18056 | gen_rtx_REG (SImode, GP_ARG_RETURN), | |
18057 | const0_rtx), | |
18058 | gen_rtx_EXPR_LIST (VOIDmode, | |
18059 | gen_rtx_REG (SImode, | |
18060 | GP_ARG_RETURN + 1), | |
18061 | GEN_INT (4)))); | |
18062 | } | |
18063 | ||
a6ebc39a AH |
18064 | if ((INTEGRAL_TYPE_P (valtype) |
18065 | && TYPE_PRECISION (valtype) < BITS_PER_WORD) | |
18066 | || POINTER_TYPE_P (valtype)) | |
b78d48dd | 18067 | mode = TARGET_32BIT ? SImode : DImode; |
a6ebc39a AH |
18068 | else |
18069 | mode = TYPE_MODE (valtype); | |
18070 | ||
4ed78545 | 18071 | if (SCALAR_FLOAT_TYPE_P (valtype) && TARGET_HARD_FLOAT && TARGET_FPRS) |
2a8fa26c | 18072 | regno = FP_ARG_RETURN; |
ded9bf77 | 18073 | else if (TREE_CODE (valtype) == COMPLEX_TYPE |
42ba5130 | 18074 | && targetm.calls.split_complex_arg) |
ded9bf77 | 18075 | return rs6000_complex_function_value (mode); |
44688022 | 18076 | else if (TREE_CODE (valtype) == VECTOR_TYPE |
d0b2079e FJ |
18077 | && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI |
18078 | && ALTIVEC_VECTOR_MODE(mode)) | |
a6ebc39a AH |
18079 | regno = ALTIVEC_ARG_RETURN; |
18080 | else | |
18081 | regno = GP_ARG_RETURN; | |
18082 | ||
18083 | return gen_rtx_REG (mode, regno); | |
18084 | } | |
18085 | ||
ded9bf77 AH |
18086 | /* Define how to find the value returned by a library function |
18087 | assuming the value has mode MODE. */ | |
18088 | rtx | |
18089 | rs6000_libcall_value (enum machine_mode mode) | |
18090 | { | |
18091 | unsigned int regno; | |
18092 | ||
2e6c9641 FJ |
18093 | if (TARGET_32BIT && TARGET_POWERPC64 && mode == DImode) |
18094 | { | |
18095 | /* Long long return value need be split in -mpowerpc64, 32bit ABI. */ | |
18096 | return gen_rtx_PARALLEL (DImode, | |
18097 | gen_rtvec (2, | |
18098 | gen_rtx_EXPR_LIST (VOIDmode, | |
18099 | gen_rtx_REG (SImode, GP_ARG_RETURN), | |
18100 | const0_rtx), | |
18101 | gen_rtx_EXPR_LIST (VOIDmode, | |
18102 | gen_rtx_REG (SImode, | |
18103 | GP_ARG_RETURN + 1), | |
18104 | GEN_INT (4)))); | |
18105 | } | |
18106 | ||
ded9bf77 AH |
18107 | if (GET_MODE_CLASS (mode) == MODE_FLOAT |
18108 | && TARGET_HARD_FLOAT && TARGET_FPRS) | |
18109 | regno = FP_ARG_RETURN; | |
44688022 AM |
18110 | else if (ALTIVEC_VECTOR_MODE (mode) |
18111 | && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI) | |
ded9bf77 | 18112 | regno = ALTIVEC_ARG_RETURN; |
42ba5130 | 18113 | else if (COMPLEX_MODE_P (mode) && targetm.calls.split_complex_arg) |
ded9bf77 AH |
18114 | return rs6000_complex_function_value (mode); |
18115 | else | |
18116 | regno = GP_ARG_RETURN; | |
18117 | ||
18118 | return gen_rtx_REG (mode, regno); | |
18119 | } | |
18120 | ||
d1d0c603 JJ |
18121 | /* Define the offset between two registers, FROM to be eliminated and its |
18122 | replacement TO, at the start of a routine. */ | |
18123 | HOST_WIDE_INT | |
18124 | rs6000_initial_elimination_offset (int from, int to) | |
18125 | { | |
18126 | rs6000_stack_t *info = rs6000_stack_info (); | |
18127 | HOST_WIDE_INT offset; | |
18128 | ||
18129 | if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM) | |
18130 | offset = info->push_p ? 0 : -info->total_size; | |
18131 | else if (from == ARG_POINTER_REGNUM && to == FRAME_POINTER_REGNUM) | |
18132 | offset = info->total_size; | |
18133 | else if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM) | |
18134 | offset = info->push_p ? info->total_size : 0; | |
18135 | else if (from == RS6000_PIC_OFFSET_TABLE_REGNUM) | |
18136 | offset = 0; | |
18137 | else | |
18138 | abort (); | |
18139 | ||
18140 | return offset; | |
18141 | } | |
18142 | ||
62e1dfcf NC |
18143 | /* Return true if TYPE is of type __ev64_opaque__. */ |
18144 | ||
c8e4f0e9 | 18145 | static bool |
a2369ed3 | 18146 | is_ev64_opaque_type (tree type) |
62e1dfcf | 18147 | { |
c8e4f0e9 | 18148 | return (TARGET_SPE |
2abe3e28 AH |
18149 | && (type == opaque_V2SI_type_node |
18150 | || type == opaque_V2SF_type_node | |
36252949 | 18151 | || type == opaque_p_V2SI_type_node)); |
62e1dfcf NC |
18152 | } |
18153 | ||
96714395 | 18154 | static rtx |
a2369ed3 | 18155 | rs6000_dwarf_register_span (rtx reg) |
96714395 AH |
18156 | { |
18157 | unsigned regno; | |
18158 | ||
4d4cbc0e AH |
18159 | if (TARGET_SPE |
18160 | && (SPE_VECTOR_MODE (GET_MODE (reg)) | |
18161 | || (TARGET_E500_DOUBLE && GET_MODE (reg) == DFmode))) | |
18162 | ; | |
18163 | else | |
96714395 AH |
18164 | return NULL_RTX; |
18165 | ||
18166 | regno = REGNO (reg); | |
18167 | ||
18168 | /* The duality of the SPE register size wreaks all kinds of havoc. | |
18169 | This is a way of distinguishing r0 in 32-bits from r0 in | |
18170 | 64-bits. */ | |
18171 | return | |
18172 | gen_rtx_PARALLEL (VOIDmode, | |
3bd104d1 AH |
18173 | BYTES_BIG_ENDIAN |
18174 | ? gen_rtvec (2, | |
18175 | gen_rtx_REG (SImode, regno + 1200), | |
18176 | gen_rtx_REG (SImode, regno)) | |
18177 | : gen_rtvec (2, | |
18178 | gen_rtx_REG (SImode, regno), | |
18179 | gen_rtx_REG (SImode, regno + 1200))); | |
96714395 AH |
18180 | } |
18181 | ||
93c9d1ba AM |
18182 | /* Map internal gcc register numbers to DWARF2 register numbers. */ |
18183 | ||
18184 | unsigned int | |
18185 | rs6000_dbx_register_number (unsigned int regno) | |
18186 | { | |
18187 | if (regno <= 63 || write_symbols != DWARF2_DEBUG) | |
18188 | return regno; | |
18189 | if (regno == MQ_REGNO) | |
18190 | return 100; | |
18191 | if (regno == LINK_REGISTER_REGNUM) | |
18192 | return 108; | |
18193 | if (regno == COUNT_REGISTER_REGNUM) | |
18194 | return 109; | |
18195 | if (CR_REGNO_P (regno)) | |
18196 | return regno - CR0_REGNO + 86; | |
18197 | if (regno == XER_REGNO) | |
18198 | return 101; | |
18199 | if (ALTIVEC_REGNO_P (regno)) | |
18200 | return regno - FIRST_ALTIVEC_REGNO + 1124; | |
18201 | if (regno == VRSAVE_REGNO) | |
18202 | return 356; | |
18203 | if (regno == VSCR_REGNO) | |
18204 | return 67; | |
18205 | if (regno == SPE_ACC_REGNO) | |
18206 | return 99; | |
18207 | if (regno == SPEFSCR_REGNO) | |
18208 | return 612; | |
18209 | /* SPE high reg number. We get these values of regno from | |
18210 | rs6000_dwarf_register_span. */ | |
18211 | if (regno >= 1200 && regno < 1232) | |
18212 | return regno; | |
18213 | ||
18214 | abort (); | |
18215 | } | |
18216 | ||
93f90be6 | 18217 | /* target hook eh_return_filter_mode */ |
f676971a | 18218 | static enum machine_mode |
93f90be6 FJ |
18219 | rs6000_eh_return_filter_mode (void) |
18220 | { | |
18221 | return TARGET_32BIT ? SImode : word_mode; | |
18222 | } | |
18223 | ||
f676971a EC |
18224 | /* Target hook for vector_mode_supported_p. */ |
18225 | static bool | |
18226 | rs6000_vector_mode_supported_p (enum machine_mode mode) | |
18227 | { | |
18228 | ||
18229 | if (TARGET_SPE && SPE_VECTOR_MODE (mode)) | |
18230 | return true; | |
18231 | ||
18232 | else if (TARGET_ALTIVEC && ALTIVEC_VECTOR_MODE (mode)) | |
18233 | return true; | |
18234 | ||
18235 | else | |
18236 | return false; | |
18237 | } | |
18238 | ||
17211ab5 | 18239 | #include "gt-rs6000.h" |