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Commit | Line | Data |
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9878760c | 1 | /* Subroutines used for code generation on IBM RS/6000. |
9ebbca7d | 2 | Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, |
d3c300d2 | 3 | 2000, 2001, 2002, 2003 Free Software Foundation, Inc. |
fab3bcc3 | 4 | Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu) |
9878760c | 5 | |
5de601cf | 6 | This file is part of GCC. |
9878760c | 7 | |
5de601cf NC |
8 | GCC is free software; you can redistribute it and/or modify it |
9 | under the terms of the GNU General Public License as published | |
10 | by the Free Software Foundation; either version 2, or (at your | |
11 | option) any later version. | |
9878760c | 12 | |
5de601cf NC |
13 | GCC is distributed in the hope that it will be useful, but WITHOUT |
14 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
15 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
16 | License for more details. | |
9878760c | 17 | |
5de601cf NC |
18 | You should have received a copy of the GNU General Public License |
19 | along with GCC; see the file COPYING. If not, write to the | |
20 | Free Software Foundation, 59 Temple Place - Suite 330, Boston, | |
21 | MA 02111-1307, USA. */ | |
9878760c | 22 | |
956d6950 | 23 | #include "config.h" |
c4d38ccb | 24 | #include "system.h" |
4977bab6 ZW |
25 | #include "coretypes.h" |
26 | #include "tm.h" | |
9878760c RK |
27 | #include "rtl.h" |
28 | #include "regs.h" | |
29 | #include "hard-reg-set.h" | |
30 | #include "real.h" | |
31 | #include "insn-config.h" | |
32 | #include "conditions.h" | |
9878760c RK |
33 | #include "insn-attr.h" |
34 | #include "flags.h" | |
35 | #include "recog.h" | |
9878760c | 36 | #include "obstack.h" |
9b30bae2 | 37 | #include "tree.h" |
dfafc897 | 38 | #include "expr.h" |
2fc1c679 | 39 | #include "optabs.h" |
2a430ec1 | 40 | #include "except.h" |
a7df97e6 | 41 | #include "function.h" |
296b8152 | 42 | #include "output.h" |
d5fa86ba | 43 | #include "basic-block.h" |
d0101753 | 44 | #include "integrate.h" |
296b8152 | 45 | #include "toplev.h" |
c8023011 | 46 | #include "ggc.h" |
9ebbca7d GK |
47 | #include "hashtab.h" |
48 | #include "tm_p.h" | |
672a6f42 NB |
49 | #include "target.h" |
50 | #include "target-def.h" | |
3ac88239 | 51 | #include "langhooks.h" |
24ea750e | 52 | #include "reload.h" |
9b30bae2 | 53 | |
7509c759 MM |
54 | #ifndef TARGET_NO_PROTOTYPE |
55 | #define TARGET_NO_PROTOTYPE 0 | |
56 | #endif | |
57 | ||
d744e06e AH |
58 | #define EASY_VECTOR_15(n, x, y) ((n) >= -16 && (n) <= 15 \ |
59 | && easy_vector_same (x, y)) | |
60 | ||
61 | #define EASY_VECTOR_15_ADD_SELF(n, x, y) ((n) >= 0x10 && (n) <= 0x1e \ | |
62 | && !((n) & 1) \ | |
63 | && easy_vector_same (x, y)) | |
64 | ||
9878760c RK |
65 | #define min(A,B) ((A) < (B) ? (A) : (B)) |
66 | #define max(A,B) ((A) > (B) ? (A) : (B)) | |
67 | ||
5248c961 RK |
68 | /* Target cpu type */ |
69 | ||
70 | enum processor_type rs6000_cpu; | |
8e3f41e7 MM |
71 | struct rs6000_cpu_select rs6000_select[3] = |
72 | { | |
815cdc52 MM |
73 | /* switch name, tune arch */ |
74 | { (const char *)0, "--with-cpu=", 1, 1 }, | |
75 | { (const char *)0, "-mcpu=", 1, 1 }, | |
76 | { (const char *)0, "-mtune=", 1, 0 }, | |
8e3f41e7 | 77 | }; |
5248c961 | 78 | |
6fa3f289 ZW |
79 | /* Size of long double */ |
80 | const char *rs6000_long_double_size_string; | |
81 | int rs6000_long_double_type_size; | |
82 | ||
83 | /* Whether -mabi=altivec has appeared */ | |
84 | int rs6000_altivec_abi; | |
85 | ||
08b57fb3 AH |
86 | /* Whether VRSAVE instructions should be generated. */ |
87 | int rs6000_altivec_vrsave; | |
88 | ||
89 | /* String from -mvrsave= option. */ | |
90 | const char *rs6000_altivec_vrsave_string; | |
91 | ||
a3170dc6 AH |
92 | /* Nonzero if we want SPE ABI extensions. */ |
93 | int rs6000_spe_abi; | |
94 | ||
95 | /* Whether isel instructions should be generated. */ | |
96 | int rs6000_isel; | |
97 | ||
993f19a8 AH |
98 | /* Whether SPE simd instructions should be generated. */ |
99 | int rs6000_spe; | |
100 | ||
5da702b1 AH |
101 | /* Nonzero if floating point operations are done in the GPRs. */ |
102 | int rs6000_float_gprs = 0; | |
103 | ||
104 | /* String from -mfloat-gprs=. */ | |
105 | const char *rs6000_float_gprs_string; | |
a3170dc6 AH |
106 | |
107 | /* String from -misel=. */ | |
108 | const char *rs6000_isel_string; | |
109 | ||
993f19a8 AH |
110 | /* String from -mspe=. */ |
111 | const char *rs6000_spe_string; | |
112 | ||
a0ab749a | 113 | /* Set to nonzero once AIX common-mode calls have been defined. */ |
bbfb86aa | 114 | static GTY(()) int common_mode_defined; |
c81bebd7 | 115 | |
9878760c RK |
116 | /* Save information from a "cmpxx" operation until the branch or scc is |
117 | emitted. */ | |
9878760c RK |
118 | rtx rs6000_compare_op0, rs6000_compare_op1; |
119 | int rs6000_compare_fp_p; | |
874a0744 | 120 | |
874a0744 MM |
121 | /* Label number of label created for -mrelocatable, to call to so we can |
122 | get the address of the GOT section */ | |
123 | int rs6000_pic_labelno; | |
c81bebd7 | 124 | |
b91da81f | 125 | #ifdef USING_ELFOS_H |
c81bebd7 | 126 | /* Which abi to adhere to */ |
815cdc52 | 127 | const char *rs6000_abi_name = RS6000_ABI_NAME; |
d9407988 MM |
128 | |
129 | /* Semantics of the small data area */ | |
130 | enum rs6000_sdata_type rs6000_sdata = SDATA_DATA; | |
131 | ||
132 | /* Which small data model to use */ | |
815cdc52 | 133 | const char *rs6000_sdata_name = (char *)0; |
9ebbca7d GK |
134 | |
135 | /* Counter for labels which are to be placed in .fixup. */ | |
136 | int fixuplabelno = 0; | |
874a0744 | 137 | #endif |
4697a36c | 138 | |
b6c9286a MM |
139 | /* ABI enumeration available for subtarget to use. */ |
140 | enum rs6000_abi rs6000_current_abi; | |
141 | ||
0ac081f6 AH |
142 | /* ABI string from -mabi= option. */ |
143 | const char *rs6000_abi_string; | |
144 | ||
38c1f2d7 | 145 | /* Debug flags */ |
815cdc52 | 146 | const char *rs6000_debug_name; |
38c1f2d7 MM |
147 | int rs6000_debug_stack; /* debug stack applications */ |
148 | int rs6000_debug_arg; /* debug argument handling */ | |
149 | ||
2abe3e28 AH |
150 | /* A copy of V2SI_type_node to be used as an opaque type. */ |
151 | static GTY(()) tree opaque_V2SI_type_node; | |
152 | ||
153 | /* Same, but for V2SF. */ | |
154 | static GTY(()) tree opaque_V2SF_type_node; | |
155 | ||
57ac7be9 AM |
156 | const char *rs6000_traceback_name; |
157 | static enum { | |
158 | traceback_default = 0, | |
159 | traceback_none, | |
160 | traceback_part, | |
161 | traceback_full | |
162 | } rs6000_traceback; | |
163 | ||
38c1f2d7 MM |
164 | /* Flag to say the TOC is initialized */ |
165 | int toc_initialized; | |
9ebbca7d | 166 | char toc_label_name[10]; |
38c1f2d7 | 167 | |
9ebbca7d GK |
168 | /* Alias set for saves and restores from the rs6000 stack. */ |
169 | static int rs6000_sr_alias_set; | |
c8023011 | 170 | |
a5c76ee6 ZW |
171 | /* Call distance, overridden by -mlongcall and #pragma longcall(1). |
172 | The only place that looks at this is rs6000_set_default_type_attributes; | |
173 | everywhere else should rely on the presence or absence of a longcall | |
174 | attribute on the function declaration. */ | |
175 | int rs6000_default_long_calls; | |
176 | const char *rs6000_longcall_switch; | |
177 | ||
a3170dc6 AH |
178 | struct builtin_description |
179 | { | |
180 | /* mask is not const because we're going to alter it below. This | |
181 | nonsense will go away when we rewrite the -march infrastructure | |
182 | to give us more target flag bits. */ | |
183 | unsigned int mask; | |
184 | const enum insn_code icode; | |
185 | const char *const name; | |
186 | const enum rs6000_builtins code; | |
187 | }; | |
188 | ||
4977bab6 | 189 | static bool rs6000_function_ok_for_sibcall PARAMS ((tree, tree)); |
9ebbca7d | 190 | static int num_insns_constant_wide PARAMS ((HOST_WIDE_INT)); |
39a10a29 GK |
191 | static void validate_condition_mode |
192 | PARAMS ((enum rtx_code, enum machine_mode)); | |
193 | static rtx rs6000_generate_compare PARAMS ((enum rtx_code)); | |
e50f5f3d | 194 | static void rs6000_maybe_dead PARAMS ((rtx)); |
9ebbca7d GK |
195 | static void rs6000_emit_stack_tie PARAMS ((void)); |
196 | static void rs6000_frame_related PARAMS ((rtx, rtx, HOST_WIDE_INT, rtx, rtx)); | |
c19de7aa AH |
197 | static rtx spe_synthesize_frame_save PARAMS ((rtx)); |
198 | static bool spe_func_has_64bit_regs_p PARAMS ((void)); | |
89e7058f AH |
199 | static void emit_frame_save PARAMS ((rtx, rtx, enum machine_mode, |
200 | unsigned int, int, int)); | |
a3170dc6 | 201 | static rtx gen_frame_mem_offset PARAMS ((enum machine_mode, rtx, int)); |
9ebbca7d GK |
202 | static void rs6000_emit_allocate_stack PARAMS ((HOST_WIDE_INT, int)); |
203 | static unsigned rs6000_hash_constant PARAMS ((rtx)); | |
204 | static unsigned toc_hash_function PARAMS ((const void *)); | |
205 | static int toc_hash_eq PARAMS ((const void *, const void *)); | |
9ebbca7d | 206 | static int constant_pool_expr_1 PARAMS ((rtx, int *, int *)); |
e2500fed | 207 | static struct machine_function * rs6000_init_machine_status PARAMS ((void)); |
301d03af | 208 | static bool rs6000_assemble_integer PARAMS ((rtx, unsigned int, int)); |
5add3202 | 209 | #ifdef HAVE_GAS_HIDDEN |
25fdb4dc | 210 | static void rs6000_assemble_visibility PARAMS ((tree, int)); |
5add3202 | 211 | #endif |
71f123ca | 212 | static int rs6000_ra_ever_killed PARAMS ((void)); |
91d231cb JM |
213 | static tree rs6000_handle_longcall_attribute PARAMS ((tree *, tree, tree, int, bool *)); |
214 | const struct attribute_spec rs6000_attribute_table[]; | |
a5c76ee6 | 215 | static void rs6000_set_default_type_attributes PARAMS ((tree)); |
08c148a8 NB |
216 | static void rs6000_output_function_prologue PARAMS ((FILE *, HOST_WIDE_INT)); |
217 | static void rs6000_output_function_epilogue PARAMS ((FILE *, HOST_WIDE_INT)); | |
3961e8fe RH |
218 | static void rs6000_output_mi_thunk PARAMS ((FILE *, tree, HOST_WIDE_INT, |
219 | HOST_WIDE_INT, tree)); | |
2bfcf297 DB |
220 | static rtx rs6000_emit_set_long_const PARAMS ((rtx, |
221 | HOST_WIDE_INT, HOST_WIDE_INT)); | |
7c262518 RH |
222 | #if TARGET_ELF |
223 | static unsigned int rs6000_elf_section_type_flags PARAMS ((tree, const char *, | |
224 | int)); | |
d9f6800d RH |
225 | static void rs6000_elf_asm_out_constructor PARAMS ((rtx, int)); |
226 | static void rs6000_elf_asm_out_destructor PARAMS ((rtx, int)); | |
ae46c4e0 | 227 | static void rs6000_elf_select_section PARAMS ((tree, int, |
5b71a4e7 | 228 | unsigned HOST_WIDE_INT)); |
ae46c4e0 | 229 | static void rs6000_elf_unique_section PARAMS ((tree, int)); |
b64a1b53 RH |
230 | static void rs6000_elf_select_rtx_section PARAMS ((enum machine_mode, rtx, |
231 | unsigned HOST_WIDE_INT)); | |
0e5dbd9b DE |
232 | static void rs6000_elf_encode_section_info PARAMS ((tree, int)) |
233 | ATTRIBUTE_UNUSED; | |
772c5265 | 234 | static const char *rs6000_elf_strip_name_encoding PARAMS ((const char *)); |
0e5dbd9b | 235 | static bool rs6000_elf_in_small_data_p PARAMS ((tree)); |
7c262518 | 236 | #endif |
cbaaba19 | 237 | #if TARGET_XCOFF |
b275d088 DE |
238 | static void rs6000_xcoff_asm_globalize_label PARAMS ((FILE *, const char *)); |
239 | static void rs6000_xcoff_asm_named_section PARAMS ((const char *, unsigned int)); | |
ae46c4e0 RH |
240 | static void rs6000_xcoff_select_section PARAMS ((tree, int, |
241 | unsigned HOST_WIDE_INT)); | |
242 | static void rs6000_xcoff_unique_section PARAMS ((tree, int)); | |
b64a1b53 RH |
243 | static void rs6000_xcoff_select_rtx_section PARAMS ((enum machine_mode, rtx, |
244 | unsigned HOST_WIDE_INT)); | |
772c5265 | 245 | static const char * rs6000_xcoff_strip_name_encoding PARAMS ((const char *)); |
5add3202 | 246 | static unsigned int rs6000_xcoff_section_type_flags PARAMS ((tree, const char *, int)); |
fb49053f RH |
247 | static void rs6000_xcoff_encode_section_info PARAMS ((tree, int)) |
248 | ATTRIBUTE_UNUSED; | |
f1384257 AM |
249 | #endif |
250 | #if TARGET_MACHO | |
2bcc50d0 | 251 | static bool rs6000_binds_local_p PARAMS ((tree)); |
f1384257 | 252 | #endif |
b54cf83a | 253 | static int rs6000_use_dfa_pipeline_interface PARAMS ((void)); |
b54cf83a | 254 | static int rs6000_variable_issue PARAMS ((FILE *, int, rtx, int)); |
3c50106f | 255 | static bool rs6000_rtx_costs PARAMS ((rtx, int, int, int *)); |
c237e94a ZW |
256 | static int rs6000_adjust_cost PARAMS ((rtx, rtx, rtx, int)); |
257 | static int rs6000_adjust_priority PARAMS ((rtx, int)); | |
258 | static int rs6000_issue_rate PARAMS ((void)); | |
be12c2b0 | 259 | static int rs6000_use_sched_lookahead PARAMS ((void)); |
c237e94a | 260 | |
6fa3f289 | 261 | static void rs6000_init_builtins PARAMS ((void)); |
92898235 AH |
262 | static rtx rs6000_expand_unop_builtin PARAMS ((enum insn_code, tree, rtx)); |
263 | static rtx rs6000_expand_binop_builtin PARAMS ((enum insn_code, tree, rtx)); | |
264 | static rtx rs6000_expand_ternop_builtin PARAMS ((enum insn_code, tree, rtx)); | |
0ac081f6 | 265 | static rtx rs6000_expand_builtin PARAMS ((tree, rtx, rtx, enum machine_mode, int)); |
92898235 | 266 | static void altivec_init_builtins PARAMS ((void)); |
a3170dc6 AH |
267 | static void rs6000_common_init_builtins PARAMS ((void)); |
268 | ||
269 | static void enable_mask_for_builtins PARAMS ((struct builtin_description *, | |
270 | int, enum rs6000_builtins, | |
271 | enum rs6000_builtins)); | |
272 | static void spe_init_builtins PARAMS ((void)); | |
273 | static rtx spe_expand_builtin PARAMS ((tree, rtx, bool *)); | |
274 | static rtx spe_expand_predicate_builtin PARAMS ((enum insn_code, tree, rtx)); | |
275 | static rtx spe_expand_evsel_builtin PARAMS ((enum insn_code, tree, rtx)); | |
276 | static int rs6000_emit_int_cmove PARAMS ((rtx, rtx, rtx, rtx)); | |
277 | ||
92898235 | 278 | static rtx altivec_expand_builtin PARAMS ((tree, rtx, bool *)); |
3a9b8c7e AH |
279 | static rtx altivec_expand_ld_builtin PARAMS ((tree, rtx, bool *)); |
280 | static rtx altivec_expand_st_builtin PARAMS ((tree, rtx, bool *)); | |
281 | static rtx altivec_expand_dst_builtin PARAMS ((tree, rtx, bool *)); | |
100c4561 | 282 | static rtx altivec_expand_abs_builtin PARAMS ((enum insn_code, tree, rtx)); |
ae4b4a02 | 283 | static rtx altivec_expand_predicate_builtin PARAMS ((enum insn_code, const char *, tree, rtx)); |
6525c0e7 | 284 | static rtx altivec_expand_stv_builtin PARAMS ((enum insn_code, tree)); |
0ac081f6 | 285 | static void rs6000_parse_abi_options PARAMS ((void)); |
5da702b1 | 286 | static void rs6000_parse_yes_no_option (const char *, const char *, int *); |
00b960c7 AH |
287 | static int first_altivec_reg_to_save PARAMS ((void)); |
288 | static unsigned int compute_vrsave_mask PARAMS ((void)); | |
289 | static void is_altivec_return_reg PARAMS ((rtx, void *)); | |
9aa86737 | 290 | static rtx generate_set_vrsave PARAMS ((rtx, rs6000_stack_t *, int)); |
d744e06e AH |
291 | int easy_vector_constant PARAMS ((rtx, enum machine_mode)); |
292 | static int easy_vector_same PARAMS ((rtx, enum machine_mode)); | |
c8e4f0e9 | 293 | static bool is_ev64_opaque_type PARAMS ((tree)); |
96714395 | 294 | static rtx rs6000_dwarf_register_span PARAMS ((rtx)); |
17211ab5 GK |
295 | |
296 | /* Hash table stuff for keeping track of TOC entries. */ | |
297 | ||
298 | struct toc_hash_struct GTY(()) | |
299 | { | |
300 | /* `key' will satisfy CONSTANT_P; in fact, it will satisfy | |
301 | ASM_OUTPUT_SPECIAL_POOL_ENTRY_P. */ | |
302 | rtx key; | |
303 | enum machine_mode key_mode; | |
304 | int labelno; | |
305 | }; | |
306 | ||
307 | static GTY ((param_is (struct toc_hash_struct))) htab_t toc_hash_table; | |
c81bebd7 MM |
308 | \f |
309 | /* Default register names. */ | |
310 | char rs6000_reg_names[][8] = | |
311 | { | |
802a0058 MM |
312 | "0", "1", "2", "3", "4", "5", "6", "7", |
313 | "8", "9", "10", "11", "12", "13", "14", "15", | |
314 | "16", "17", "18", "19", "20", "21", "22", "23", | |
315 | "24", "25", "26", "27", "28", "29", "30", "31", | |
316 | "0", "1", "2", "3", "4", "5", "6", "7", | |
317 | "8", "9", "10", "11", "12", "13", "14", "15", | |
318 | "16", "17", "18", "19", "20", "21", "22", "23", | |
319 | "24", "25", "26", "27", "28", "29", "30", "31", | |
320 | "mq", "lr", "ctr","ap", | |
321 | "0", "1", "2", "3", "4", "5", "6", "7", | |
0ac081f6 AH |
322 | "xer", |
323 | /* AltiVec registers. */ | |
0cd5e3a1 AH |
324 | "0", "1", "2", "3", "4", "5", "6", "7", |
325 | "8", "9", "10", "11", "12", "13", "14", "15", | |
326 | "16", "17", "18", "19", "20", "21", "22", "23", | |
327 | "24", "25", "26", "27", "28", "29", "30", "31", | |
59a4c851 AH |
328 | "vrsave", "vscr", |
329 | /* SPE registers. */ | |
330 | "spe_acc", "spefscr" | |
c81bebd7 MM |
331 | }; |
332 | ||
333 | #ifdef TARGET_REGNAMES | |
8b60264b | 334 | static const char alt_reg_names[][8] = |
c81bebd7 | 335 | { |
802a0058 MM |
336 | "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7", |
337 | "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15", | |
338 | "%r16", "%r17", "%r18", "%r19", "%r20", "%r21", "%r22", "%r23", | |
339 | "%r24", "%r25", "%r26", "%r27", "%r28", "%r29", "%r30", "%r31", | |
340 | "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7", | |
341 | "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15", | |
342 | "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23", | |
343 | "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31", | |
344 | "mq", "lr", "ctr", "ap", | |
345 | "%cr0", "%cr1", "%cr2", "%cr3", "%cr4", "%cr5", "%cr6", "%cr7", | |
0ac081f6 | 346 | "xer", |
59a4c851 | 347 | /* AltiVec registers. */ |
0ac081f6 | 348 | "%v0", "%v1", "%v2", "%v3", "%v4", "%v5", "%v6", "%v7", |
59a4c851 AH |
349 | "%v8", "%v9", "%v10", "%v11", "%v12", "%v13", "%v14", "%v15", |
350 | "%v16", "%v17", "%v18", "%v19", "%v20", "%v21", "%v22", "%v23", | |
351 | "%v24", "%v25", "%v26", "%v27", "%v28", "%v29", "%v30", "%v31", | |
352 | "vrsave", "vscr", | |
353 | /* SPE registers. */ | |
354 | "spe_acc", "spefscr" | |
c81bebd7 MM |
355 | }; |
356 | #endif | |
9878760c | 357 | \f |
daf11973 MM |
358 | #ifndef MASK_STRICT_ALIGN |
359 | #define MASK_STRICT_ALIGN 0 | |
360 | #endif | |
ffcfcb5f AM |
361 | #ifndef TARGET_PROFILE_KERNEL |
362 | #define TARGET_PROFILE_KERNEL 0 | |
363 | #endif | |
3961e8fe RH |
364 | |
365 | /* The VRSAVE bitmask puts bit %v0 as the most significant bit. */ | |
366 | #define ALTIVEC_REG_BIT(REGNO) (0x80000000 >> ((REGNO) - FIRST_ALTIVEC_REGNO)) | |
672a6f42 NB |
367 | \f |
368 | /* Initialize the GCC target structure. */ | |
91d231cb JM |
369 | #undef TARGET_ATTRIBUTE_TABLE |
370 | #define TARGET_ATTRIBUTE_TABLE rs6000_attribute_table | |
a5c76ee6 ZW |
371 | #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES |
372 | #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES rs6000_set_default_type_attributes | |
daf11973 | 373 | |
301d03af RS |
374 | #undef TARGET_ASM_ALIGNED_DI_OP |
375 | #define TARGET_ASM_ALIGNED_DI_OP DOUBLE_INT_ASM_OP | |
376 | ||
377 | /* Default unaligned ops are only provided for ELF. Find the ops needed | |
378 | for non-ELF systems. */ | |
379 | #ifndef OBJECT_FORMAT_ELF | |
cbaaba19 | 380 | #if TARGET_XCOFF |
ae6c1efd | 381 | /* For XCOFF. rs6000_assemble_integer will handle unaligned DIs on |
301d03af RS |
382 | 64-bit targets. */ |
383 | #undef TARGET_ASM_UNALIGNED_HI_OP | |
384 | #define TARGET_ASM_UNALIGNED_HI_OP "\t.vbyte\t2," | |
385 | #undef TARGET_ASM_UNALIGNED_SI_OP | |
386 | #define TARGET_ASM_UNALIGNED_SI_OP "\t.vbyte\t4," | |
387 | #undef TARGET_ASM_UNALIGNED_DI_OP | |
388 | #define TARGET_ASM_UNALIGNED_DI_OP "\t.vbyte\t8," | |
389 | #else | |
390 | /* For Darwin. */ | |
391 | #undef TARGET_ASM_UNALIGNED_HI_OP | |
392 | #define TARGET_ASM_UNALIGNED_HI_OP "\t.short\t" | |
393 | #undef TARGET_ASM_UNALIGNED_SI_OP | |
394 | #define TARGET_ASM_UNALIGNED_SI_OP "\t.long\t" | |
395 | #endif | |
396 | #endif | |
397 | ||
398 | /* This hook deals with fixups for relocatable code and DI-mode objects | |
399 | in 64-bit code. */ | |
400 | #undef TARGET_ASM_INTEGER | |
401 | #define TARGET_ASM_INTEGER rs6000_assemble_integer | |
402 | ||
93638d7a AM |
403 | #ifdef HAVE_GAS_HIDDEN |
404 | #undef TARGET_ASM_ASSEMBLE_VISIBILITY | |
405 | #define TARGET_ASM_ASSEMBLE_VISIBILITY rs6000_assemble_visibility | |
406 | #endif | |
407 | ||
08c148a8 NB |
408 | #undef TARGET_ASM_FUNCTION_PROLOGUE |
409 | #define TARGET_ASM_FUNCTION_PROLOGUE rs6000_output_function_prologue | |
410 | #undef TARGET_ASM_FUNCTION_EPILOGUE | |
411 | #define TARGET_ASM_FUNCTION_EPILOGUE rs6000_output_function_epilogue | |
412 | ||
b54cf83a DE |
413 | #undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE |
414 | #define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE rs6000_use_dfa_pipeline_interface | |
b54cf83a DE |
415 | #undef TARGET_SCHED_VARIABLE_ISSUE |
416 | #define TARGET_SCHED_VARIABLE_ISSUE rs6000_variable_issue | |
417 | ||
c237e94a ZW |
418 | #undef TARGET_SCHED_ISSUE_RATE |
419 | #define TARGET_SCHED_ISSUE_RATE rs6000_issue_rate | |
420 | #undef TARGET_SCHED_ADJUST_COST | |
421 | #define TARGET_SCHED_ADJUST_COST rs6000_adjust_cost | |
422 | #undef TARGET_SCHED_ADJUST_PRIORITY | |
423 | #define TARGET_SCHED_ADJUST_PRIORITY rs6000_adjust_priority | |
424 | ||
be12c2b0 VM |
425 | #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD |
426 | #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD rs6000_use_sched_lookahead | |
427 | ||
0ac081f6 AH |
428 | #undef TARGET_INIT_BUILTINS |
429 | #define TARGET_INIT_BUILTINS rs6000_init_builtins | |
430 | ||
431 | #undef TARGET_EXPAND_BUILTIN | |
432 | #define TARGET_EXPAND_BUILTIN rs6000_expand_builtin | |
433 | ||
f1384257 | 434 | #if TARGET_MACHO |
0e5dbd9b DE |
435 | #undef TARGET_BINDS_LOCAL_P |
436 | #define TARGET_BINDS_LOCAL_P rs6000_binds_local_p | |
f1384257 | 437 | #endif |
0e5dbd9b | 438 | |
3961e8fe RH |
439 | #undef TARGET_ASM_OUTPUT_MI_THUNK |
440 | #define TARGET_ASM_OUTPUT_MI_THUNK rs6000_output_mi_thunk | |
441 | ||
3961e8fe | 442 | #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK |
5b71a4e7 | 443 | #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_tree_hwi_hwi_tree_true |
00b960c7 | 444 | |
4977bab6 ZW |
445 | #undef TARGET_FUNCTION_OK_FOR_SIBCALL |
446 | #define TARGET_FUNCTION_OK_FOR_SIBCALL rs6000_function_ok_for_sibcall | |
447 | ||
3c50106f RH |
448 | #undef TARGET_RTX_COSTS |
449 | #define TARGET_RTX_COSTS rs6000_rtx_costs | |
dcefdf67 RH |
450 | #undef TARGET_ADDRESS_COST |
451 | #define TARGET_ADDRESS_COST hook_int_rtx_0 | |
3c50106f | 452 | |
c8e4f0e9 AH |
453 | #undef TARGET_VECTOR_OPAQUE_P |
454 | #define TARGET_VECTOR_OPAQUE_P is_ev64_opaque_type | |
62e1dfcf | 455 | |
96714395 AH |
456 | #undef TARGET_DWARF_REGISTER_SPAN |
457 | #define TARGET_DWARF_REGISTER_SPAN rs6000_dwarf_register_span | |
458 | ||
f6897b10 | 459 | struct gcc_target targetm = TARGET_INITIALIZER; |
672a6f42 | 460 | \f |
5248c961 RK |
461 | /* Override command line options. Mostly we process the processor |
462 | type and sometimes adjust other TARGET_ options. */ | |
463 | ||
464 | void | |
8e3f41e7 | 465 | rs6000_override_options (default_cpu) |
d330fd93 | 466 | const char *default_cpu; |
5248c961 | 467 | { |
c4d38ccb | 468 | size_t i, j; |
8e3f41e7 | 469 | struct rs6000_cpu_select *ptr; |
5248c961 | 470 | |
85638c0d RK |
471 | /* Simplify the entries below by making a mask for any POWER |
472 | variant and any PowerPC variant. */ | |
473 | ||
938937d8 | 474 | #define POWER_MASKS (MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING) |
68c49ffa RK |
475 | #define POWERPC_MASKS (MASK_POWERPC | MASK_PPC_GPOPT \ |
476 | | MASK_PPC_GFXOPT | MASK_POWERPC64) | |
477 | #define POWERPC_OPT_MASKS (MASK_PPC_GPOPT | MASK_PPC_GFXOPT) | |
85638c0d | 478 | |
5248c961 RK |
479 | static struct ptt |
480 | { | |
8b60264b KG |
481 | const char *const name; /* Canonical processor name. */ |
482 | const enum processor_type processor; /* Processor type enum value. */ | |
483 | const int target_enable; /* Target flags to enable. */ | |
484 | const int target_disable; /* Target flags to disable. */ | |
485 | } const processor_target_table[] | |
cf27b467 MM |
486 | = {{"common", PROCESSOR_COMMON, MASK_NEW_MNEMONICS, |
487 | POWER_MASKS | POWERPC_MASKS}, | |
db7f1e43 | 488 | {"power", PROCESSOR_POWER, |
938937d8 | 489 | MASK_POWER | MASK_MULTIPLE | MASK_STRING, |
db7f1e43 | 490 | MASK_POWER2 | POWERPC_MASKS | MASK_NEW_MNEMONICS}, |
8e3f41e7 MM |
491 | {"power2", PROCESSOR_POWER, |
492 | MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING, | |
493 | POWERPC_MASKS | MASK_NEW_MNEMONICS}, | |
c71791e0 DE |
494 | {"power3", PROCESSOR_PPC630, |
495 | MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS, | |
d7b53ca4 | 496 | POWER_MASKS}, |
309323c2 | 497 | {"power4", PROCESSOR_POWER4, |
7f3d8013 | 498 | MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS, |
a12f8290 | 499 | POWER_MASKS}, |
db7f1e43 RK |
500 | {"powerpc", PROCESSOR_POWERPC, |
501 | MASK_POWERPC | MASK_NEW_MNEMONICS, | |
68c49ffa | 502 | POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64}, |
3cb999d8 DE |
503 | {"powerpc64", PROCESSOR_POWERPC64, |
504 | MASK_POWERPC | MASK_POWERPC64 | MASK_NEW_MNEMONICS, | |
505 | POWER_MASKS | POWERPC_OPT_MASKS}, | |
db7f1e43 | 506 | {"rios", PROCESSOR_RIOS1, |
938937d8 | 507 | MASK_POWER | MASK_MULTIPLE | MASK_STRING, |
db7f1e43 RK |
508 | MASK_POWER2 | POWERPC_MASKS | MASK_NEW_MNEMONICS}, |
509 | {"rios1", PROCESSOR_RIOS1, | |
938937d8 | 510 | MASK_POWER | MASK_MULTIPLE | MASK_STRING, |
db7f1e43 RK |
511 | MASK_POWER2 | POWERPC_MASKS | MASK_NEW_MNEMONICS}, |
512 | {"rsc", PROCESSOR_PPC601, | |
938937d8 | 513 | MASK_POWER | MASK_MULTIPLE | MASK_STRING, |
db7f1e43 RK |
514 | MASK_POWER2 | POWERPC_MASKS | MASK_NEW_MNEMONICS}, |
515 | {"rsc1", PROCESSOR_PPC601, | |
938937d8 | 516 | MASK_POWER | MASK_MULTIPLE | MASK_STRING, |
db7f1e43 RK |
517 | MASK_POWER2 | POWERPC_MASKS | MASK_NEW_MNEMONICS}, |
518 | {"rios2", PROCESSOR_RIOS2, | |
938937d8 | 519 | MASK_POWER | MASK_MULTIPLE | MASK_STRING | MASK_POWER2, |
db7f1e43 | 520 | POWERPC_MASKS | MASK_NEW_MNEMONICS}, |
3cb999d8 DE |
521 | {"rs64a", PROCESSOR_RS64A, |
522 | MASK_POWERPC | MASK_NEW_MNEMONICS, | |
523 | POWER_MASKS | POWERPC_OPT_MASKS}, | |
a3a1dbf6 MM |
524 | {"401", PROCESSOR_PPC403, |
525 | MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS, | |
526 | POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64}, | |
49a0b204 | 527 | {"403", PROCESSOR_PPC403, |
daf11973 | 528 | MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS | MASK_STRICT_ALIGN, |
49a0b204 | 529 | POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64}, |
d7a5e253 DE |
530 | {"405", PROCESSOR_PPC405, |
531 | MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS, | |
532 | POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64}, | |
4977bab6 ZW |
533 | {"405f", PROCESSOR_PPC405, |
534 | MASK_POWERPC | MASK_NEW_MNEMONICS, | |
535 | POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64}, | |
cf27b467 MM |
536 | {"505", PROCESSOR_MPCCORE, |
537 | MASK_POWERPC | MASK_NEW_MNEMONICS, | |
538 | POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64}, | |
5248c961 | 539 | {"601", PROCESSOR_PPC601, |
938937d8 | 540 | MASK_POWER | MASK_POWERPC | MASK_NEW_MNEMONICS | MASK_MULTIPLE | MASK_STRING, |
68c49ffa | 541 | MASK_POWER2 | POWERPC_OPT_MASKS | MASK_POWERPC64}, |
1ec26da6 | 542 | {"602", PROCESSOR_PPC603, |
cf27b467 MM |
543 | MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS, |
544 | POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64}, | |
5248c961 | 545 | {"603", PROCESSOR_PPC603, |
68c49ffa RK |
546 | MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS, |
547 | POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64}, | |
b6c9286a MM |
548 | {"603e", PROCESSOR_PPC603, |
549 | MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS, | |
550 | POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64}, | |
b5370a88 | 551 | {"ec603e", PROCESSOR_PPC603, |
a3a1dbf6 MM |
552 | MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS, |
553 | POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64}, | |
5248c961 | 554 | {"604", PROCESSOR_PPC604, |
b6c9286a MM |
555 | MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS, |
556 | POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64}, | |
cac8ce95 | 557 | {"604e", PROCESSOR_PPC604e, |
07e6159a MM |
558 | MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS, |
559 | POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64}, | |
b6c9286a | 560 | {"620", PROCESSOR_PPC620, |
68c49ffa | 561 | MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS, |
d7b53ca4 | 562 | POWER_MASKS}, |
3cb999d8 DE |
563 | {"630", PROCESSOR_PPC630, |
564 | MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS, | |
d7b53ca4 | 565 | POWER_MASKS}, |
bef84347 VM |
566 | {"740", PROCESSOR_PPC750, |
567 | MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS, | |
568 | POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64}, | |
569 | {"750", PROCESSOR_PPC750, | |
570 | MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS, | |
571 | POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64}, | |
a4f6c312 SS |
572 | {"7400", PROCESSOR_PPC7400, |
573 | MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS, | |
574 | POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64}, | |
575 | {"7450", PROCESSOR_PPC7450, | |
576 | MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS, | |
577 | POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64}, | |
a3170dc6 AH |
578 | {"8540", PROCESSOR_PPC8540, |
579 | MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS, | |
580 | POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64}, | |
07e6159a MM |
581 | {"801", PROCESSOR_MPCCORE, |
582 | MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS, | |
583 | POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64}, | |
cf27b467 MM |
584 | {"821", PROCESSOR_MPCCORE, |
585 | MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS, | |
586 | POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64}, | |
07e6159a MM |
587 | {"823", PROCESSOR_MPCCORE, |
588 | MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS, | |
589 | POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64}, | |
cf27b467 MM |
590 | {"860", PROCESSOR_MPCCORE, |
591 | MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS, | |
592 | POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64}}; | |
5248c961 | 593 | |
ca7558fc | 594 | const size_t ptt_size = ARRAY_SIZE (processor_target_table); |
5248c961 | 595 | |
a4f6c312 SS |
596 | /* Save current -mmultiple/-mno-multiple status. */ |
597 | int multiple = TARGET_MULTIPLE; | |
598 | /* Save current -mstring/-mno-string status. */ | |
599 | int string = TARGET_STRING; | |
8a61d227 | 600 | |
a4f6c312 | 601 | /* Identify the processor type. */ |
8e3f41e7 | 602 | rs6000_select[0].string = default_cpu; |
3cb999d8 | 603 | rs6000_cpu = TARGET_POWERPC64 ? PROCESSOR_DEFAULT64 : PROCESSOR_DEFAULT; |
8e3f41e7 | 604 | |
b6a1cbae | 605 | for (i = 0; i < ARRAY_SIZE (rs6000_select); i++) |
5248c961 | 606 | { |
8e3f41e7 MM |
607 | ptr = &rs6000_select[i]; |
608 | if (ptr->string != (char *)0 && ptr->string[0] != '\0') | |
5248c961 | 609 | { |
8e3f41e7 MM |
610 | for (j = 0; j < ptt_size; j++) |
611 | if (! strcmp (ptr->string, processor_target_table[j].name)) | |
612 | { | |
613 | if (ptr->set_tune_p) | |
614 | rs6000_cpu = processor_target_table[j].processor; | |
615 | ||
616 | if (ptr->set_arch_p) | |
617 | { | |
618 | target_flags |= processor_target_table[j].target_enable; | |
619 | target_flags &= ~processor_target_table[j].target_disable; | |
620 | } | |
621 | break; | |
622 | } | |
623 | ||
4406229e | 624 | if (j == ptt_size) |
8e3f41e7 | 625 | error ("bad value (%s) for %s switch", ptr->string, ptr->name); |
5248c961 RK |
626 | } |
627 | } | |
8a61d227 | 628 | |
993f19a8 | 629 | if (TARGET_E500) |
a3170dc6 AH |
630 | rs6000_isel = 1; |
631 | ||
dff9f1b6 DE |
632 | /* If we are optimizing big endian systems for space, use the load/store |
633 | multiple and string instructions. */ | |
ef792183 | 634 | if (BYTES_BIG_ENDIAN && optimize_size) |
dff9f1b6 | 635 | target_flags |= MASK_MULTIPLE | MASK_STRING; |
ef792183 | 636 | |
8a61d227 MM |
637 | /* If -mmultiple or -mno-multiple was explicitly used, don't |
638 | override with the processor default */ | |
b21fb038 | 639 | if ((target_flags_explicit & MASK_MULTIPLE) != 0) |
8a61d227 | 640 | target_flags = (target_flags & ~MASK_MULTIPLE) | multiple; |
7e69e155 | 641 | |
a4f6c312 SS |
642 | /* If -mstring or -mno-string was explicitly used, don't override |
643 | with the processor default. */ | |
b21fb038 | 644 | if ((target_flags_explicit & MASK_STRING) != 0) |
1f5515bf | 645 | target_flags = (target_flags & ~MASK_STRING) | string; |
938937d8 | 646 | |
a4f6c312 SS |
647 | /* Don't allow -mmultiple or -mstring on little endian systems |
648 | unless the cpu is a 750, because the hardware doesn't support the | |
649 | instructions used in little endian mode, and causes an alignment | |
650 | trap. The 750 does not cause an alignment trap (except when the | |
651 | target is unaligned). */ | |
bef84347 | 652 | |
b21fb038 | 653 | if (!BYTES_BIG_ENDIAN && rs6000_cpu != PROCESSOR_PPC750) |
7e69e155 MM |
654 | { |
655 | if (TARGET_MULTIPLE) | |
656 | { | |
657 | target_flags &= ~MASK_MULTIPLE; | |
b21fb038 | 658 | if ((target_flags_explicit & MASK_MULTIPLE) != 0) |
7e69e155 MM |
659 | warning ("-mmultiple is not supported on little endian systems"); |
660 | } | |
661 | ||
662 | if (TARGET_STRING) | |
663 | { | |
664 | target_flags &= ~MASK_STRING; | |
b21fb038 | 665 | if ((target_flags_explicit & MASK_STRING) != 0) |
938937d8 | 666 | warning ("-mstring is not supported on little endian systems"); |
7e69e155 MM |
667 | } |
668 | } | |
3933e0e1 | 669 | |
38c1f2d7 MM |
670 | /* Set debug flags */ |
671 | if (rs6000_debug_name) | |
672 | { | |
bfc79d3b | 673 | if (! strcmp (rs6000_debug_name, "all")) |
38c1f2d7 | 674 | rs6000_debug_stack = rs6000_debug_arg = 1; |
bfc79d3b | 675 | else if (! strcmp (rs6000_debug_name, "stack")) |
38c1f2d7 | 676 | rs6000_debug_stack = 1; |
bfc79d3b | 677 | else if (! strcmp (rs6000_debug_name, "arg")) |
38c1f2d7 MM |
678 | rs6000_debug_arg = 1; |
679 | else | |
c725bd79 | 680 | error ("unknown -mdebug-%s switch", rs6000_debug_name); |
38c1f2d7 MM |
681 | } |
682 | ||
57ac7be9 AM |
683 | if (rs6000_traceback_name) |
684 | { | |
685 | if (! strncmp (rs6000_traceback_name, "full", 4)) | |
686 | rs6000_traceback = traceback_full; | |
687 | else if (! strncmp (rs6000_traceback_name, "part", 4)) | |
688 | rs6000_traceback = traceback_part; | |
689 | else if (! strncmp (rs6000_traceback_name, "no", 2)) | |
690 | rs6000_traceback = traceback_none; | |
691 | else | |
692 | error ("unknown -mtraceback arg `%s'; expecting `full', `partial' or `none'", | |
693 | rs6000_traceback_name); | |
694 | } | |
695 | ||
6fa3f289 ZW |
696 | /* Set size of long double */ |
697 | rs6000_long_double_type_size = 64; | |
698 | if (rs6000_long_double_size_string) | |
699 | { | |
700 | char *tail; | |
701 | int size = strtol (rs6000_long_double_size_string, &tail, 10); | |
702 | if (*tail != '\0' || (size != 64 && size != 128)) | |
703 | error ("Unknown switch -mlong-double-%s", | |
704 | rs6000_long_double_size_string); | |
705 | else | |
706 | rs6000_long_double_type_size = size; | |
707 | } | |
708 | ||
0ac081f6 AH |
709 | /* Handle -mabi= options. */ |
710 | rs6000_parse_abi_options (); | |
711 | ||
5da702b1 AH |
712 | /* Handle generic -mFOO=YES/NO options. */ |
713 | rs6000_parse_yes_no_option ("vrsave", rs6000_altivec_vrsave_string, | |
714 | &rs6000_altivec_vrsave); | |
715 | rs6000_parse_yes_no_option ("isel", rs6000_isel_string, | |
716 | &rs6000_isel); | |
717 | rs6000_parse_yes_no_option ("spe", rs6000_spe_string, &rs6000_spe); | |
718 | rs6000_parse_yes_no_option ("float-gprs", rs6000_float_gprs_string, | |
719 | &rs6000_float_gprs); | |
993f19a8 | 720 | |
a7ae18e2 AH |
721 | #ifdef SUBTARGET_OVERRIDE_OPTIONS |
722 | SUBTARGET_OVERRIDE_OPTIONS; | |
723 | #endif | |
724 | #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS | |
725 | SUBSUBTARGET_OVERRIDE_OPTIONS; | |
726 | #endif | |
727 | ||
5da702b1 AH |
728 | if (TARGET_E500) |
729 | { | |
730 | /* The e500 does not have string instructions, and we set | |
731 | MASK_STRING above when optimizing for size. */ | |
732 | if ((target_flags & MASK_STRING) != 0) | |
733 | target_flags = target_flags & ~MASK_STRING; | |
734 | } | |
735 | else if (rs6000_select[1].string != NULL) | |
736 | { | |
737 | /* For the powerpc-eabispe configuration, we set all these by | |
738 | default, so let's unset them if we manually set another | |
739 | CPU that is not the E500. */ | |
740 | if (rs6000_abi_string == 0) | |
741 | rs6000_spe_abi = 0; | |
742 | if (rs6000_spe_string == 0) | |
743 | rs6000_spe = 0; | |
744 | if (rs6000_float_gprs_string == 0) | |
745 | rs6000_float_gprs = 0; | |
746 | if (rs6000_isel_string == 0) | |
747 | rs6000_isel = 0; | |
748 | } | |
b5044283 | 749 | |
a5c76ee6 ZW |
750 | /* Handle -m(no-)longcall option. This is a bit of a cheap hack, |
751 | using TARGET_OPTIONS to handle a toggle switch, but we're out of | |
752 | bits in target_flags so TARGET_SWITCHES cannot be used. | |
753 | Assumption here is that rs6000_longcall_switch points into the | |
754 | text of the complete option, rather than being a copy, so we can | |
755 | scan back for the presence or absence of the no- modifier. */ | |
756 | if (rs6000_longcall_switch) | |
757 | { | |
758 | const char *base = rs6000_longcall_switch; | |
759 | while (base[-1] != 'm') base--; | |
760 | ||
761 | if (*rs6000_longcall_switch != '\0') | |
762 | error ("invalid option `%s'", base); | |
763 | rs6000_default_long_calls = (base[0] != 'n'); | |
764 | } | |
765 | ||
c81bebd7 | 766 | #ifdef TARGET_REGNAMES |
a4f6c312 SS |
767 | /* If the user desires alternate register names, copy in the |
768 | alternate names now. */ | |
c81bebd7 | 769 | if (TARGET_REGNAMES) |
4e135bdd | 770 | memcpy (rs6000_reg_names, alt_reg_names, sizeof (rs6000_reg_names)); |
c81bebd7 MM |
771 | #endif |
772 | ||
6fa3f289 ZW |
773 | /* Set TARGET_AIX_STRUCT_RET last, after the ABI is determined. |
774 | If -maix-struct-return or -msvr4-struct-return was explicitly | |
775 | used, don't override with the ABI default. */ | |
b21fb038 | 776 | if ((target_flags_explicit & MASK_AIX_STRUCT_RET) == 0) |
6fa3f289 ZW |
777 | { |
778 | if (DEFAULT_ABI == ABI_V4 && !DRAFT_V4_STRUCT_RET) | |
779 | target_flags = (target_flags & ~MASK_AIX_STRUCT_RET); | |
780 | else | |
781 | target_flags |= MASK_AIX_STRUCT_RET; | |
782 | } | |
783 | ||
fcce224d DE |
784 | if (TARGET_LONG_DOUBLE_128 |
785 | && (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)) | |
786 | real_format_for_mode[TFmode - QFmode] = &ibm_extended_format; | |
787 | ||
9ebbca7d GK |
788 | /* Allocate an alias set for register saves & restores from stack. */ |
789 | rs6000_sr_alias_set = new_alias_set (); | |
790 | ||
791 | if (TARGET_TOC) | |
792 | ASM_GENERATE_INTERNAL_LABEL (toc_label_name, "LCTOC", 1); | |
71f123ca | 793 | |
301d03af RS |
794 | /* We can only guarantee the availability of DI pseudo-ops when |
795 | assembling for 64-bit targets. */ | |
ae6c1efd | 796 | if (!TARGET_64BIT) |
301d03af RS |
797 | { |
798 | targetm.asm_out.aligned_op.di = NULL; | |
799 | targetm.asm_out.unaligned_op.di = NULL; | |
800 | } | |
801 | ||
2792d578 DE |
802 | /* Set maximum branch target alignment at two instructions, eight bytes. */ |
803 | align_jumps_max_skip = 8; | |
804 | align_loops_max_skip = 8; | |
805 | ||
71f123ca FS |
806 | /* Arrange to save and restore machine status around nested functions. */ |
807 | init_machine_status = rs6000_init_machine_status; | |
5248c961 | 808 | } |
5accd822 | 809 | |
5da702b1 AH |
810 | /* Handle generic options of the form -mfoo=yes/no. |
811 | NAME is the option name. | |
812 | VALUE is the option value. | |
813 | FLAG is the pointer to the flag where to store a 1 or 0, depending on | |
814 | whether the option value is 'yes' or 'no' respectively. */ | |
993f19a8 | 815 | static void |
5da702b1 | 816 | rs6000_parse_yes_no_option (const char *name, const char *value, int *flag) |
993f19a8 | 817 | { |
5da702b1 | 818 | if (value == 0) |
993f19a8 | 819 | return; |
5da702b1 AH |
820 | else if (!strcmp (value, "yes")) |
821 | *flag = 1; | |
822 | else if (!strcmp (value, "no")) | |
823 | *flag = 0; | |
08b57fb3 | 824 | else |
5da702b1 | 825 | error ("unknown -m%s= option specified: '%s'", name, value); |
08b57fb3 AH |
826 | } |
827 | ||
0ac081f6 | 828 | /* Handle -mabi= options. */ |
00b960c7 AH |
829 | static void |
830 | rs6000_parse_abi_options () | |
0ac081f6 AH |
831 | { |
832 | if (rs6000_abi_string == 0) | |
833 | return; | |
834 | else if (! strcmp (rs6000_abi_string, "altivec")) | |
6fa3f289 | 835 | rs6000_altivec_abi = 1; |
76a773f3 AH |
836 | else if (! strcmp (rs6000_abi_string, "no-altivec")) |
837 | rs6000_altivec_abi = 0; | |
a3170dc6 | 838 | else if (! strcmp (rs6000_abi_string, "spe")) |
01f4962d NS |
839 | { |
840 | rs6000_spe_abi = 1; | |
841 | if (!TARGET_SPE_ABI) | |
842 | error ("not configured for ABI: '%s'", rs6000_abi_string); | |
843 | } | |
844 | ||
a3170dc6 AH |
845 | else if (! strcmp (rs6000_abi_string, "no-spe")) |
846 | rs6000_spe_abi = 0; | |
0ac081f6 | 847 | else |
c725bd79 | 848 | error ("unknown ABI specified: '%s'", rs6000_abi_string); |
0ac081f6 AH |
849 | } |
850 | ||
5accd822 DE |
851 | void |
852 | optimization_options (level, size) | |
e2c953b6 | 853 | int level ATTRIBUTE_UNUSED; |
5accd822 DE |
854 | int size ATTRIBUTE_UNUSED; |
855 | { | |
5accd822 | 856 | } |
3cfa4909 MM |
857 | \f |
858 | /* Do anything needed at the start of the asm file. */ | |
859 | ||
860 | void | |
861 | rs6000_file_start (file, default_cpu) | |
862 | FILE *file; | |
d330fd93 | 863 | const char *default_cpu; |
3cfa4909 | 864 | { |
c4d38ccb | 865 | size_t i; |
3cfa4909 | 866 | char buffer[80]; |
d330fd93 | 867 | const char *start = buffer; |
3cfa4909 MM |
868 | struct rs6000_cpu_select *ptr; |
869 | ||
870 | if (flag_verbose_asm) | |
871 | { | |
872 | sprintf (buffer, "\n%s rs6000/powerpc options:", ASM_COMMENT_START); | |
873 | rs6000_select[0].string = default_cpu; | |
874 | ||
b6a1cbae | 875 | for (i = 0; i < ARRAY_SIZE (rs6000_select); i++) |
3cfa4909 MM |
876 | { |
877 | ptr = &rs6000_select[i]; | |
878 | if (ptr->string != (char *)0 && ptr->string[0] != '\0') | |
879 | { | |
880 | fprintf (file, "%s %s%s", start, ptr->name, ptr->string); | |
881 | start = ""; | |
882 | } | |
883 | } | |
884 | ||
b91da81f | 885 | #ifdef USING_ELFOS_H |
3cfa4909 MM |
886 | switch (rs6000_sdata) |
887 | { | |
888 | case SDATA_NONE: fprintf (file, "%s -msdata=none", start); start = ""; break; | |
889 | case SDATA_DATA: fprintf (file, "%s -msdata=data", start); start = ""; break; | |
890 | case SDATA_SYSV: fprintf (file, "%s -msdata=sysv", start); start = ""; break; | |
891 | case SDATA_EABI: fprintf (file, "%s -msdata=eabi", start); start = ""; break; | |
892 | } | |
893 | ||
894 | if (rs6000_sdata && g_switch_value) | |
895 | { | |
896 | fprintf (file, "%s -G %d", start, g_switch_value); | |
897 | start = ""; | |
898 | } | |
899 | #endif | |
900 | ||
901 | if (*start == '\0') | |
949ea356 | 902 | putc ('\n', file); |
3cfa4909 MM |
903 | } |
904 | } | |
5248c961 | 905 | \f |
a0ab749a | 906 | /* Return nonzero if this function is known to have a null epilogue. */ |
9878760c RK |
907 | |
908 | int | |
909 | direct_return () | |
910 | { | |
4697a36c MM |
911 | if (reload_completed) |
912 | { | |
913 | rs6000_stack_t *info = rs6000_stack_info (); | |
914 | ||
915 | if (info->first_gp_reg_save == 32 | |
916 | && info->first_fp_reg_save == 64 | |
00b960c7 | 917 | && info->first_altivec_reg_save == LAST_ALTIVEC_REGNO + 1 |
c81fc13e DE |
918 | && ! info->lr_save_p |
919 | && ! info->cr_save_p | |
00b960c7 | 920 | && info->vrsave_mask == 0 |
c81fc13e | 921 | && ! info->push_p) |
4697a36c MM |
922 | return 1; |
923 | } | |
924 | ||
925 | return 0; | |
9878760c RK |
926 | } |
927 | ||
928 | /* Returns 1 always. */ | |
929 | ||
930 | int | |
931 | any_operand (op, mode) | |
592696dd | 932 | rtx op ATTRIBUTE_UNUSED; |
296b8152 | 933 | enum machine_mode mode ATTRIBUTE_UNUSED; |
9878760c RK |
934 | { |
935 | return 1; | |
936 | } | |
937 | ||
a4f6c312 | 938 | /* Returns 1 if op is the count register. */ |
38c1f2d7 | 939 | int |
a4f6c312 | 940 | count_register_operand (op, mode) |
592696dd | 941 | rtx op; |
296b8152 | 942 | enum machine_mode mode ATTRIBUTE_UNUSED; |
b6c9286a MM |
943 | { |
944 | if (GET_CODE (op) != REG) | |
945 | return 0; | |
946 | ||
947 | if (REGNO (op) == COUNT_REGISTER_REGNUM) | |
948 | return 1; | |
949 | ||
950 | if (REGNO (op) > FIRST_PSEUDO_REGISTER) | |
951 | return 1; | |
952 | ||
953 | return 0; | |
954 | } | |
955 | ||
0ec4e2a8 AH |
956 | /* Returns 1 if op is an altivec register. */ |
957 | int | |
958 | altivec_register_operand (op, mode) | |
959 | rtx op; | |
960 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
961 | { | |
962 | ||
963 | return (register_operand (op, mode) | |
964 | && (GET_CODE (op) != REG | |
965 | || REGNO (op) > FIRST_PSEUDO_REGISTER | |
966 | || ALTIVEC_REGNO_P (REGNO (op)))); | |
967 | } | |
968 | ||
38c1f2d7 | 969 | int |
a4f6c312 | 970 | xer_operand (op, mode) |
592696dd | 971 | rtx op; |
296b8152 | 972 | enum machine_mode mode ATTRIBUTE_UNUSED; |
802a0058 MM |
973 | { |
974 | if (GET_CODE (op) != REG) | |
975 | return 0; | |
976 | ||
9ebbca7d | 977 | if (XER_REGNO_P (REGNO (op))) |
802a0058 MM |
978 | return 1; |
979 | ||
802a0058 MM |
980 | return 0; |
981 | } | |
982 | ||
c859cda6 | 983 | /* Return 1 if OP is a signed 8-bit constant. Int multiplication |
6f317ef3 | 984 | by such constants completes more quickly. */ |
c859cda6 DJ |
985 | |
986 | int | |
987 | s8bit_cint_operand (op, mode) | |
988 | rtx op; | |
989 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
990 | { | |
991 | return ( GET_CODE (op) == CONST_INT | |
992 | && (INTVAL (op) >= -128 && INTVAL (op) <= 127)); | |
993 | } | |
994 | ||
9878760c RK |
995 | /* Return 1 if OP is a constant that can fit in a D field. */ |
996 | ||
997 | int | |
998 | short_cint_operand (op, mode) | |
592696dd | 999 | rtx op; |
296b8152 | 1000 | enum machine_mode mode ATTRIBUTE_UNUSED; |
9878760c | 1001 | { |
5f59ecb7 DE |
1002 | return (GET_CODE (op) == CONST_INT |
1003 | && CONST_OK_FOR_LETTER_P (INTVAL (op), 'I')); | |
9878760c RK |
1004 | } |
1005 | ||
5519a4f9 | 1006 | /* Similar for an unsigned D field. */ |
9878760c RK |
1007 | |
1008 | int | |
1009 | u_short_cint_operand (op, mode) | |
592696dd | 1010 | rtx op; |
296b8152 | 1011 | enum machine_mode mode ATTRIBUTE_UNUSED; |
9878760c | 1012 | { |
19684119 | 1013 | return (GET_CODE (op) == CONST_INT |
c1f11548 | 1014 | && CONST_OK_FOR_LETTER_P (INTVAL (op) & GET_MODE_MASK (mode), 'K')); |
9878760c RK |
1015 | } |
1016 | ||
dcfedcd0 RK |
1017 | /* Return 1 if OP is a CONST_INT that cannot fit in a signed D field. */ |
1018 | ||
1019 | int | |
1020 | non_short_cint_operand (op, mode) | |
592696dd | 1021 | rtx op; |
296b8152 | 1022 | enum machine_mode mode ATTRIBUTE_UNUSED; |
dcfedcd0 RK |
1023 | { |
1024 | return (GET_CODE (op) == CONST_INT | |
a7653a2c | 1025 | && (unsigned HOST_WIDE_INT) (INTVAL (op) + 0x8000) >= 0x10000); |
dcfedcd0 RK |
1026 | } |
1027 | ||
2bfcf297 DB |
1028 | /* Returns 1 if OP is a CONST_INT that is a positive value |
1029 | and an exact power of 2. */ | |
1030 | ||
1031 | int | |
1032 | exact_log2_cint_operand (op, mode) | |
592696dd | 1033 | rtx op; |
2bfcf297 DB |
1034 | enum machine_mode mode ATTRIBUTE_UNUSED; |
1035 | { | |
1036 | return (GET_CODE (op) == CONST_INT | |
1037 | && INTVAL (op) > 0 | |
1038 | && exact_log2 (INTVAL (op)) >= 0); | |
1039 | } | |
1040 | ||
9878760c RK |
1041 | /* Returns 1 if OP is a register that is not special (i.e., not MQ, |
1042 | ctr, or lr). */ | |
1043 | ||
1044 | int | |
cd2b37d9 | 1045 | gpc_reg_operand (op, mode) |
592696dd | 1046 | rtx op; |
9878760c RK |
1047 | enum machine_mode mode; |
1048 | { | |
1049 | return (register_operand (op, mode) | |
802a0058 | 1050 | && (GET_CODE (op) != REG |
9ebbca7d GK |
1051 | || (REGNO (op) >= ARG_POINTER_REGNUM |
1052 | && !XER_REGNO_P (REGNO (op))) | |
1053 | || REGNO (op) < MQ_REGNO)); | |
9878760c RK |
1054 | } |
1055 | ||
1056 | /* Returns 1 if OP is either a pseudo-register or a register denoting a | |
1057 | CR field. */ | |
1058 | ||
1059 | int | |
1060 | cc_reg_operand (op, mode) | |
592696dd | 1061 | rtx op; |
9878760c RK |
1062 | enum machine_mode mode; |
1063 | { | |
1064 | return (register_operand (op, mode) | |
1065 | && (GET_CODE (op) != REG | |
1066 | || REGNO (op) >= FIRST_PSEUDO_REGISTER | |
1067 | || CR_REGNO_P (REGNO (op)))); | |
1068 | } | |
1069 | ||
815cdc52 MM |
1070 | /* Returns 1 if OP is either a pseudo-register or a register denoting a |
1071 | CR field that isn't CR0. */ | |
1072 | ||
1073 | int | |
1074 | cc_reg_not_cr0_operand (op, mode) | |
592696dd | 1075 | rtx op; |
815cdc52 MM |
1076 | enum machine_mode mode; |
1077 | { | |
1078 | return (register_operand (op, mode) | |
1079 | && (GET_CODE (op) != REG | |
1080 | || REGNO (op) >= FIRST_PSEUDO_REGISTER | |
1081 | || CR_REGNO_NOT_CR0_P (REGNO (op)))); | |
1082 | } | |
1083 | ||
a4f6c312 SS |
1084 | /* Returns 1 if OP is either a constant integer valid for a D-field or |
1085 | a non-special register. If a register, it must be in the proper | |
1086 | mode unless MODE is VOIDmode. */ | |
9878760c RK |
1087 | |
1088 | int | |
1089 | reg_or_short_operand (op, mode) | |
592696dd | 1090 | rtx op; |
9878760c RK |
1091 | enum machine_mode mode; |
1092 | { | |
f5a28898 | 1093 | return short_cint_operand (op, mode) || gpc_reg_operand (op, mode); |
9878760c RK |
1094 | } |
1095 | ||
a4f6c312 SS |
1096 | /* Similar, except check if the negation of the constant would be |
1097 | valid for a D-field. */ | |
9878760c RK |
1098 | |
1099 | int | |
1100 | reg_or_neg_short_operand (op, mode) | |
592696dd | 1101 | rtx op; |
9878760c RK |
1102 | enum machine_mode mode; |
1103 | { | |
1104 | if (GET_CODE (op) == CONST_INT) | |
1105 | return CONST_OK_FOR_LETTER_P (INTVAL (op), 'P'); | |
1106 | ||
cd2b37d9 | 1107 | return gpc_reg_operand (op, mode); |
9878760c RK |
1108 | } |
1109 | ||
768070a0 TR |
1110 | /* Returns 1 if OP is either a constant integer valid for a DS-field or |
1111 | a non-special register. If a register, it must be in the proper | |
1112 | mode unless MODE is VOIDmode. */ | |
1113 | ||
1114 | int | |
1115 | reg_or_aligned_short_operand (op, mode) | |
1116 | rtx op; | |
1117 | enum machine_mode mode; | |
1118 | { | |
1119 | if (gpc_reg_operand (op, mode)) | |
1120 | return 1; | |
1121 | else if (short_cint_operand (op, mode) && !(INTVAL (op) & 3)) | |
1122 | return 1; | |
1123 | ||
1124 | return 0; | |
1125 | } | |
1126 | ||
1127 | ||
a4f6c312 SS |
1128 | /* Return 1 if the operand is either a register or an integer whose |
1129 | high-order 16 bits are zero. */ | |
9878760c RK |
1130 | |
1131 | int | |
1132 | reg_or_u_short_operand (op, mode) | |
592696dd | 1133 | rtx op; |
9878760c RK |
1134 | enum machine_mode mode; |
1135 | { | |
e675f625 | 1136 | return u_short_cint_operand (op, mode) || gpc_reg_operand (op, mode); |
9878760c RK |
1137 | } |
1138 | ||
1139 | /* Return 1 is the operand is either a non-special register or ANY | |
1140 | constant integer. */ | |
1141 | ||
1142 | int | |
1143 | reg_or_cint_operand (op, mode) | |
592696dd | 1144 | rtx op; |
9878760c RK |
1145 | enum machine_mode mode; |
1146 | { | |
a4f6c312 | 1147 | return (GET_CODE (op) == CONST_INT || gpc_reg_operand (op, mode)); |
f6bf7de2 DE |
1148 | } |
1149 | ||
1150 | /* Return 1 is the operand is either a non-special register or ANY | |
1151 | 32-bit signed constant integer. */ | |
1152 | ||
1153 | int | |
1154 | reg_or_arith_cint_operand (op, mode) | |
592696dd | 1155 | rtx op; |
f6bf7de2 DE |
1156 | enum machine_mode mode; |
1157 | { | |
a4f6c312 SS |
1158 | return (gpc_reg_operand (op, mode) |
1159 | || (GET_CODE (op) == CONST_INT | |
f6bf7de2 | 1160 | #if HOST_BITS_PER_WIDE_INT != 32 |
a4f6c312 SS |
1161 | && ((unsigned HOST_WIDE_INT) (INTVAL (op) + 0x80000000) |
1162 | < (unsigned HOST_WIDE_INT) 0x100000000ll) | |
f6bf7de2 | 1163 | #endif |
a4f6c312 | 1164 | )); |
9878760c RK |
1165 | } |
1166 | ||
2bfcf297 DB |
1167 | /* Return 1 is the operand is either a non-special register or a 32-bit |
1168 | signed constant integer valid for 64-bit addition. */ | |
1169 | ||
1170 | int | |
1171 | reg_or_add_cint64_operand (op, mode) | |
592696dd | 1172 | rtx op; |
2bfcf297 DB |
1173 | enum machine_mode mode; |
1174 | { | |
a4f6c312 SS |
1175 | return (gpc_reg_operand (op, mode) |
1176 | || (GET_CODE (op) == CONST_INT | |
a65c591c | 1177 | #if HOST_BITS_PER_WIDE_INT == 32 |
a4f6c312 | 1178 | && INTVAL (op) < 0x7fff8000 |
a65c591c | 1179 | #else |
a4f6c312 SS |
1180 | && ((unsigned HOST_WIDE_INT) (INTVAL (op) + 0x80008000) |
1181 | < 0x100000000ll) | |
2bfcf297 | 1182 | #endif |
a4f6c312 | 1183 | )); |
2bfcf297 DB |
1184 | } |
1185 | ||
1186 | /* Return 1 is the operand is either a non-special register or a 32-bit | |
1187 | signed constant integer valid for 64-bit subtraction. */ | |
1188 | ||
1189 | int | |
1190 | reg_or_sub_cint64_operand (op, mode) | |
592696dd | 1191 | rtx op; |
2bfcf297 DB |
1192 | enum machine_mode mode; |
1193 | { | |
a4f6c312 SS |
1194 | return (gpc_reg_operand (op, mode) |
1195 | || (GET_CODE (op) == CONST_INT | |
a65c591c | 1196 | #if HOST_BITS_PER_WIDE_INT == 32 |
a4f6c312 | 1197 | && (- INTVAL (op)) < 0x7fff8000 |
a65c591c | 1198 | #else |
a4f6c312 SS |
1199 | && ((unsigned HOST_WIDE_INT) ((- INTVAL (op)) + 0x80008000) |
1200 | < 0x100000000ll) | |
2bfcf297 | 1201 | #endif |
a4f6c312 | 1202 | )); |
2bfcf297 DB |
1203 | } |
1204 | ||
9ebbca7d GK |
1205 | /* Return 1 is the operand is either a non-special register or ANY |
1206 | 32-bit unsigned constant integer. */ | |
1207 | ||
1208 | int | |
1d328b19 | 1209 | reg_or_logical_cint_operand (op, mode) |
592696dd | 1210 | rtx op; |
9ebbca7d GK |
1211 | enum machine_mode mode; |
1212 | { | |
1d328b19 GK |
1213 | if (GET_CODE (op) == CONST_INT) |
1214 | { | |
1215 | if (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT) | |
1216 | { | |
1217 | if (GET_MODE_BITSIZE (mode) <= 32) | |
a4f6c312 | 1218 | abort (); |
1d328b19 GK |
1219 | |
1220 | if (INTVAL (op) < 0) | |
1221 | return 0; | |
1222 | } | |
1223 | ||
1224 | return ((INTVAL (op) & GET_MODE_MASK (mode) | |
0858c623 | 1225 | & (~ (unsigned HOST_WIDE_INT) 0xffffffff)) == 0); |
1d328b19 GK |
1226 | } |
1227 | else if (GET_CODE (op) == CONST_DOUBLE) | |
1228 | { | |
1229 | if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT | |
1230 | || mode != DImode) | |
a4f6c312 | 1231 | abort (); |
1d328b19 GK |
1232 | |
1233 | return CONST_DOUBLE_HIGH (op) == 0; | |
1234 | } | |
1235 | else | |
1236 | return gpc_reg_operand (op, mode); | |
9ebbca7d GK |
1237 | } |
1238 | ||
51d3e7d6 | 1239 | /* Return 1 if the operand is an operand that can be loaded via the GOT. */ |
766a866c MM |
1240 | |
1241 | int | |
1242 | got_operand (op, mode) | |
592696dd | 1243 | rtx op; |
296b8152 | 1244 | enum machine_mode mode ATTRIBUTE_UNUSED; |
766a866c MM |
1245 | { |
1246 | return (GET_CODE (op) == SYMBOL_REF | |
1247 | || GET_CODE (op) == CONST | |
1248 | || GET_CODE (op) == LABEL_REF); | |
1249 | } | |
1250 | ||
38c1f2d7 MM |
1251 | /* Return 1 if the operand is a simple references that can be loaded via |
1252 | the GOT (labels involving addition aren't allowed). */ | |
1253 | ||
1254 | int | |
1255 | got_no_const_operand (op, mode) | |
592696dd | 1256 | rtx op; |
296b8152 | 1257 | enum machine_mode mode ATTRIBUTE_UNUSED; |
38c1f2d7 MM |
1258 | { |
1259 | return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF); | |
1260 | } | |
1261 | ||
4e74d8ec MM |
1262 | /* Return the number of instructions it takes to form a constant in an |
1263 | integer register. */ | |
1264 | ||
1265 | static int | |
1266 | num_insns_constant_wide (value) | |
1267 | HOST_WIDE_INT value; | |
1268 | { | |
1269 | /* signed constant loadable with {cal|addi} */ | |
5f59ecb7 | 1270 | if (CONST_OK_FOR_LETTER_P (value, 'I')) |
0865c631 GK |
1271 | return 1; |
1272 | ||
4e74d8ec | 1273 | /* constant loadable with {cau|addis} */ |
5f59ecb7 | 1274 | else if (CONST_OK_FOR_LETTER_P (value, 'L')) |
4e74d8ec MM |
1275 | return 1; |
1276 | ||
5f59ecb7 | 1277 | #if HOST_BITS_PER_WIDE_INT == 64 |
c81fc13e | 1278 | else if (TARGET_POWERPC64) |
4e74d8ec | 1279 | { |
a65c591c DE |
1280 | HOST_WIDE_INT low = ((value & 0xffffffff) ^ 0x80000000) - 0x80000000; |
1281 | HOST_WIDE_INT high = value >> 31; | |
4e74d8ec | 1282 | |
a65c591c | 1283 | if (high == 0 || high == -1) |
4e74d8ec MM |
1284 | return 2; |
1285 | ||
a65c591c | 1286 | high >>= 1; |
4e74d8ec | 1287 | |
a65c591c | 1288 | if (low == 0) |
4e74d8ec | 1289 | return num_insns_constant_wide (high) + 1; |
4e74d8ec MM |
1290 | else |
1291 | return (num_insns_constant_wide (high) | |
e396202a | 1292 | + num_insns_constant_wide (low) + 1); |
4e74d8ec MM |
1293 | } |
1294 | #endif | |
1295 | ||
1296 | else | |
1297 | return 2; | |
1298 | } | |
1299 | ||
1300 | int | |
1301 | num_insns_constant (op, mode) | |
1302 | rtx op; | |
1303 | enum machine_mode mode; | |
1304 | { | |
4e74d8ec | 1305 | if (GET_CODE (op) == CONST_INT) |
0d30d435 DE |
1306 | { |
1307 | #if HOST_BITS_PER_WIDE_INT == 64 | |
4e2c1c44 DE |
1308 | if ((INTVAL (op) >> 31) != 0 && (INTVAL (op) >> 31) != -1 |
1309 | && mask64_operand (op, mode)) | |
0d30d435 DE |
1310 | return 2; |
1311 | else | |
1312 | #endif | |
1313 | return num_insns_constant_wide (INTVAL (op)); | |
1314 | } | |
4e74d8ec | 1315 | |
6fc48950 MM |
1316 | else if (GET_CODE (op) == CONST_DOUBLE && mode == SFmode) |
1317 | { | |
1318 | long l; | |
1319 | REAL_VALUE_TYPE rv; | |
1320 | ||
1321 | REAL_VALUE_FROM_CONST_DOUBLE (rv, op); | |
1322 | REAL_VALUE_TO_TARGET_SINGLE (rv, l); | |
e72247f4 | 1323 | return num_insns_constant_wide ((HOST_WIDE_INT) l); |
6fc48950 MM |
1324 | } |
1325 | ||
47ad8c61 | 1326 | else if (GET_CODE (op) == CONST_DOUBLE) |
4e74d8ec | 1327 | { |
47ad8c61 MM |
1328 | HOST_WIDE_INT low; |
1329 | HOST_WIDE_INT high; | |
1330 | long l[2]; | |
1331 | REAL_VALUE_TYPE rv; | |
1332 | int endian = (WORDS_BIG_ENDIAN == 0); | |
4e74d8ec | 1333 | |
47ad8c61 MM |
1334 | if (mode == VOIDmode || mode == DImode) |
1335 | { | |
1336 | high = CONST_DOUBLE_HIGH (op); | |
1337 | low = CONST_DOUBLE_LOW (op); | |
1338 | } | |
1339 | else | |
1340 | { | |
1341 | REAL_VALUE_FROM_CONST_DOUBLE (rv, op); | |
1342 | REAL_VALUE_TO_TARGET_DOUBLE (rv, l); | |
1343 | high = l[endian]; | |
1344 | low = l[1 - endian]; | |
1345 | } | |
4e74d8ec | 1346 | |
47ad8c61 MM |
1347 | if (TARGET_32BIT) |
1348 | return (num_insns_constant_wide (low) | |
1349 | + num_insns_constant_wide (high)); | |
4e74d8ec MM |
1350 | |
1351 | else | |
47ad8c61 | 1352 | { |
e72247f4 | 1353 | if (high == 0 && low >= 0) |
47ad8c61 MM |
1354 | return num_insns_constant_wide (low); |
1355 | ||
e72247f4 | 1356 | else if (high == -1 && low < 0) |
47ad8c61 MM |
1357 | return num_insns_constant_wide (low); |
1358 | ||
a260abc9 DE |
1359 | else if (mask64_operand (op, mode)) |
1360 | return 2; | |
1361 | ||
47ad8c61 MM |
1362 | else if (low == 0) |
1363 | return num_insns_constant_wide (high) + 1; | |
1364 | ||
1365 | else | |
1366 | return (num_insns_constant_wide (high) | |
1367 | + num_insns_constant_wide (low) + 1); | |
1368 | } | |
4e74d8ec MM |
1369 | } |
1370 | ||
1371 | else | |
1372 | abort (); | |
1373 | } | |
1374 | ||
a4f6c312 SS |
1375 | /* Return 1 if the operand is a CONST_DOUBLE and it can be put into a |
1376 | register with one instruction per word. We only do this if we can | |
1377 | safely read CONST_DOUBLE_{LOW,HIGH}. */ | |
9878760c RK |
1378 | |
1379 | int | |
1380 | easy_fp_constant (op, mode) | |
592696dd SS |
1381 | rtx op; |
1382 | enum machine_mode mode; | |
9878760c | 1383 | { |
9878760c RK |
1384 | if (GET_CODE (op) != CONST_DOUBLE |
1385 | || GET_MODE (op) != mode | |
4e74d8ec | 1386 | || (GET_MODE_CLASS (mode) != MODE_FLOAT && mode != DImode)) |
9878760c RK |
1387 | return 0; |
1388 | ||
a4f6c312 | 1389 | /* Consider all constants with -msoft-float to be easy. */ |
a3170dc6 AH |
1390 | if ((TARGET_SOFT_FLOAT || !TARGET_FPRS) |
1391 | && mode != DImode) | |
b6c9286a MM |
1392 | return 1; |
1393 | ||
a4f6c312 | 1394 | /* If we are using V.4 style PIC, consider all constants to be hard. */ |
f607bc57 | 1395 | if (flag_pic && DEFAULT_ABI == ABI_V4) |
a7273471 MM |
1396 | return 0; |
1397 | ||
5ae4759c | 1398 | #ifdef TARGET_RELOCATABLE |
a4f6c312 SS |
1399 | /* Similarly if we are using -mrelocatable, consider all constants |
1400 | to be hard. */ | |
5ae4759c MM |
1401 | if (TARGET_RELOCATABLE) |
1402 | return 0; | |
1403 | #endif | |
1404 | ||
fcce224d DE |
1405 | if (mode == TFmode) |
1406 | { | |
1407 | long k[4]; | |
1408 | REAL_VALUE_TYPE rv; | |
1409 | ||
1410 | REAL_VALUE_FROM_CONST_DOUBLE (rv, op); | |
1411 | REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv, k); | |
1412 | ||
1413 | return (num_insns_constant_wide ((HOST_WIDE_INT) k[0]) == 1 | |
1414 | && num_insns_constant_wide ((HOST_WIDE_INT) k[1]) == 1 | |
1415 | && num_insns_constant_wide ((HOST_WIDE_INT) k[2]) == 1 | |
1416 | && num_insns_constant_wide ((HOST_WIDE_INT) k[3]) == 1); | |
1417 | } | |
1418 | ||
1419 | else if (mode == DFmode) | |
042259f2 DE |
1420 | { |
1421 | long k[2]; | |
1422 | REAL_VALUE_TYPE rv; | |
1423 | ||
1424 | REAL_VALUE_FROM_CONST_DOUBLE (rv, op); | |
1425 | REAL_VALUE_TO_TARGET_DOUBLE (rv, k); | |
9878760c | 1426 | |
a65c591c DE |
1427 | return (num_insns_constant_wide ((HOST_WIDE_INT) k[0]) == 1 |
1428 | && num_insns_constant_wide ((HOST_WIDE_INT) k[1]) == 1); | |
042259f2 | 1429 | } |
4e74d8ec MM |
1430 | |
1431 | else if (mode == SFmode) | |
042259f2 DE |
1432 | { |
1433 | long l; | |
1434 | REAL_VALUE_TYPE rv; | |
1435 | ||
1436 | REAL_VALUE_FROM_CONST_DOUBLE (rv, op); | |
1437 | REAL_VALUE_TO_TARGET_SINGLE (rv, l); | |
9878760c | 1438 | |
4e74d8ec | 1439 | return num_insns_constant_wide (l) == 1; |
042259f2 | 1440 | } |
4e74d8ec | 1441 | |
a260abc9 | 1442 | else if (mode == DImode) |
c81fc13e | 1443 | return ((TARGET_POWERPC64 |
a260abc9 DE |
1444 | && GET_CODE (op) == CONST_DOUBLE && CONST_DOUBLE_LOW (op) == 0) |
1445 | || (num_insns_constant (op, DImode) <= 2)); | |
4e74d8ec | 1446 | |
a9098fd0 GK |
1447 | else if (mode == SImode) |
1448 | return 1; | |
4e74d8ec MM |
1449 | else |
1450 | abort (); | |
9878760c | 1451 | } |
8f75773e | 1452 | |
d744e06e | 1453 | /* Return non zero if all elements of a vector have the same value. */ |
69ef87e2 AH |
1454 | |
1455 | static int | |
d744e06e AH |
1456 | easy_vector_same (op, mode) |
1457 | rtx op; | |
1458 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
1459 | { | |
1460 | int units, i, cst; | |
1461 | ||
1462 | units = CONST_VECTOR_NUNITS (op); | |
1463 | ||
1464 | cst = INTVAL (CONST_VECTOR_ELT (op, 0)); | |
1465 | for (i = 1; i < units; ++i) | |
1466 | if (INTVAL (CONST_VECTOR_ELT (op, i)) != cst) | |
1467 | break; | |
1468 | if (i == units) | |
1469 | return 1; | |
1470 | return 0; | |
1471 | } | |
1472 | ||
1473 | /* Return 1 if the operand is a CONST_INT and can be put into a | |
1474 | register without using memory. */ | |
1475 | ||
1476 | int | |
1477 | easy_vector_constant (op, mode) | |
69ef87e2 | 1478 | rtx op; |
d744e06e | 1479 | enum machine_mode mode; |
69ef87e2 | 1480 | { |
d744e06e | 1481 | int cst, cst2; |
69ef87e2 | 1482 | |
d744e06e AH |
1483 | if (GET_CODE (op) != CONST_VECTOR |
1484 | || (!TARGET_ALTIVEC | |
1485 | && !TARGET_SPE)) | |
69ef87e2 AH |
1486 | return 0; |
1487 | ||
d744e06e AH |
1488 | if (zero_constant (op, mode) |
1489 | && ((TARGET_ALTIVEC && ALTIVEC_VECTOR_MODE (mode)) | |
1490 | || (TARGET_SPE && SPE_VECTOR_MODE (mode)))) | |
1491 | return 1; | |
69ef87e2 | 1492 | |
d744e06e AH |
1493 | if (GET_MODE_CLASS (mode) != MODE_VECTOR_INT) |
1494 | return 0; | |
1495 | ||
1496 | cst = INTVAL (CONST_VECTOR_ELT (op, 0)); | |
1497 | cst2 = INTVAL (CONST_VECTOR_ELT (op, 1)); | |
1498 | ||
1499 | /* Limit SPE vectors to 15 bits signed. These we can generate with: | |
1500 | li r0, CONSTANT1 | |
1501 | evmergelo r0, r0, r0 | |
1502 | li r0, CONSTANT2 | |
1503 | ||
1504 | I don't know how efficient it would be to allow bigger constants, | |
1505 | considering we'll have an extra 'ori' for every 'li'. I doubt 5 | |
1506 | instructions is better than a 64-bit memory load, but I don't | |
1507 | have the e500 timing specs. */ | |
1508 | if (TARGET_SPE && mode == V2SImode | |
1509 | && cst >= -0x7fff && cst <= 0x7fff | |
1510 | && cst2 >= -0x7fff && cst <= 0x7fff) | |
1511 | return 1; | |
1512 | ||
1513 | if (TARGET_ALTIVEC && EASY_VECTOR_15 (cst, op, mode)) | |
1514 | return 1; | |
1515 | ||
1516 | if (TARGET_ALTIVEC && EASY_VECTOR_15_ADD_SELF (cst, op, mode)) | |
1517 | return 1; | |
1518 | ||
1519 | return 0; | |
1520 | } | |
1521 | ||
1522 | /* Same as easy_vector_constant but only for EASY_VECTOR_15_ADD_SELF. */ | |
1523 | ||
1524 | int | |
1525 | easy_vector_constant_add_self (op, mode) | |
1526 | rtx op; | |
1527 | enum machine_mode mode; | |
1528 | { | |
1529 | int cst; | |
1530 | ||
1531 | if (!easy_vector_constant (op, mode)) | |
1532 | return 0; | |
1533 | ||
1534 | cst = INTVAL (CONST_VECTOR_ELT (op, 0)); | |
1535 | ||
1536 | return TARGET_ALTIVEC && EASY_VECTOR_15_ADD_SELF (cst, op, mode); | |
1537 | } | |
1538 | ||
1539 | const char * | |
1540 | output_vec_const_move (operands) | |
1541 | rtx *operands; | |
1542 | { | |
1543 | int cst, cst2; | |
1544 | enum machine_mode mode; | |
1545 | rtx dest, vec; | |
1546 | ||
1547 | dest = operands[0]; | |
1548 | vec = operands[1]; | |
69ef87e2 | 1549 | |
d744e06e AH |
1550 | cst = INTVAL (CONST_VECTOR_ELT (vec, 0)); |
1551 | cst2 = INTVAL (CONST_VECTOR_ELT (vec, 1)); | |
1552 | mode = GET_MODE (dest); | |
69ef87e2 | 1553 | |
d744e06e AH |
1554 | if (TARGET_ALTIVEC) |
1555 | { | |
1556 | if (zero_constant (vec, mode)) | |
1557 | return "vxor %0,%0,%0"; | |
1558 | else if (EASY_VECTOR_15 (cst, vec, mode)) | |
98ef3137 | 1559 | { |
d744e06e AH |
1560 | operands[1] = GEN_INT (cst); |
1561 | switch (mode) | |
1562 | { | |
1563 | case V4SImode: | |
1564 | return "vspltisw %0,%1"; | |
1565 | case V8HImode: | |
1566 | return "vspltish %0,%1"; | |
1567 | case V16QImode: | |
1568 | return "vspltisb %0,%1"; | |
1569 | default: | |
1570 | abort (); | |
1571 | } | |
98ef3137 | 1572 | } |
d744e06e AH |
1573 | else if (EASY_VECTOR_15_ADD_SELF (cst, vec, mode)) |
1574 | return "#"; | |
1575 | else | |
1576 | abort (); | |
69ef87e2 AH |
1577 | } |
1578 | ||
d744e06e AH |
1579 | if (TARGET_SPE) |
1580 | { | |
1581 | /* Vector constant 0 is handled as a splitter of V2SI, and in the | |
1582 | pattern of V1DI, V4HI, and V2SF. | |
1583 | ||
1584 | FIXME: We should probabl return # and add post reload | |
1585 | splitters for these, but this way is so easy ;-). | |
1586 | */ | |
1587 | operands[1] = GEN_INT (cst); | |
1588 | operands[2] = GEN_INT (cst2); | |
1589 | if (cst == cst2) | |
1590 | return "li %0,%1\n\tevmergelo %0,%0,%0"; | |
1591 | else | |
1592 | return "li %0,%1\n\tevmergelo %0,%0,%0\n\tli %0,%2"; | |
1593 | } | |
1594 | ||
1595 | abort (); | |
69ef87e2 AH |
1596 | } |
1597 | ||
1598 | /* Return 1 if the operand is the constant 0. This works for scalars | |
1599 | as well as vectors. */ | |
1600 | int | |
1601 | zero_constant (op, mode) | |
1602 | rtx op; | |
1603 | enum machine_mode mode; | |
1604 | { | |
1605 | return op == CONST0_RTX (mode); | |
1606 | } | |
1607 | ||
50a0b056 GK |
1608 | /* Return 1 if the operand is 0.0. */ |
1609 | int | |
1610 | zero_fp_constant (op, mode) | |
592696dd SS |
1611 | rtx op; |
1612 | enum machine_mode mode; | |
50a0b056 GK |
1613 | { |
1614 | return GET_MODE_CLASS (mode) == MODE_FLOAT && op == CONST0_RTX (mode); | |
1615 | } | |
1616 | ||
a4f6c312 SS |
1617 | /* Return 1 if the operand is in volatile memory. Note that during |
1618 | the RTL generation phase, memory_operand does not return TRUE for | |
b6c9286a MM |
1619 | volatile memory references. So this function allows us to |
1620 | recognize volatile references where its safe. */ | |
1621 | ||
1622 | int | |
1623 | volatile_mem_operand (op, mode) | |
592696dd | 1624 | rtx op; |
b6c9286a MM |
1625 | enum machine_mode mode; |
1626 | { | |
1627 | if (GET_CODE (op) != MEM) | |
1628 | return 0; | |
1629 | ||
1630 | if (!MEM_VOLATILE_P (op)) | |
1631 | return 0; | |
1632 | ||
1633 | if (mode != GET_MODE (op)) | |
1634 | return 0; | |
1635 | ||
1636 | if (reload_completed) | |
1637 | return memory_operand (op, mode); | |
1638 | ||
1639 | if (reload_in_progress) | |
1640 | return strict_memory_address_p (mode, XEXP (op, 0)); | |
1641 | ||
1642 | return memory_address_p (mode, XEXP (op, 0)); | |
1643 | } | |
1644 | ||
97f6e72f | 1645 | /* Return 1 if the operand is an offsettable memory operand. */ |
914c2e77 RK |
1646 | |
1647 | int | |
97f6e72f | 1648 | offsettable_mem_operand (op, mode) |
592696dd | 1649 | rtx op; |
914c2e77 RK |
1650 | enum machine_mode mode; |
1651 | { | |
97f6e72f | 1652 | return ((GET_CODE (op) == MEM) |
677a9668 | 1653 | && offsettable_address_p (reload_completed || reload_in_progress, |
97f6e72f | 1654 | mode, XEXP (op, 0))); |
914c2e77 RK |
1655 | } |
1656 | ||
9878760c RK |
1657 | /* Return 1 if the operand is either an easy FP constant (see above) or |
1658 | memory. */ | |
1659 | ||
1660 | int | |
1661 | mem_or_easy_const_operand (op, mode) | |
592696dd | 1662 | rtx op; |
9878760c RK |
1663 | enum machine_mode mode; |
1664 | { | |
1665 | return memory_operand (op, mode) || easy_fp_constant (op, mode); | |
1666 | } | |
1667 | ||
1668 | /* Return 1 if the operand is either a non-special register or an item | |
5f59ecb7 | 1669 | that can be used as the operand of a `mode' add insn. */ |
9878760c RK |
1670 | |
1671 | int | |
1672 | add_operand (op, mode) | |
592696dd | 1673 | rtx op; |
9878760c RK |
1674 | enum machine_mode mode; |
1675 | { | |
2bfcf297 | 1676 | if (GET_CODE (op) == CONST_INT) |
e72247f4 DE |
1677 | return (CONST_OK_FOR_LETTER_P (INTVAL (op), 'I') |
1678 | || CONST_OK_FOR_LETTER_P (INTVAL (op), 'L')); | |
2bfcf297 DB |
1679 | |
1680 | return gpc_reg_operand (op, mode); | |
9878760c RK |
1681 | } |
1682 | ||
dcfedcd0 RK |
1683 | /* Return 1 if OP is a constant but not a valid add_operand. */ |
1684 | ||
1685 | int | |
1686 | non_add_cint_operand (op, mode) | |
592696dd | 1687 | rtx op; |
296b8152 | 1688 | enum machine_mode mode ATTRIBUTE_UNUSED; |
dcfedcd0 RK |
1689 | { |
1690 | return (GET_CODE (op) == CONST_INT | |
e72247f4 DE |
1691 | && !CONST_OK_FOR_LETTER_P (INTVAL (op), 'I') |
1692 | && !CONST_OK_FOR_LETTER_P (INTVAL (op), 'L')); | |
dcfedcd0 RK |
1693 | } |
1694 | ||
9878760c RK |
1695 | /* Return 1 if the operand is a non-special register or a constant that |
1696 | can be used as the operand of an OR or XOR insn on the RS/6000. */ | |
1697 | ||
1698 | int | |
1699 | logical_operand (op, mode) | |
592696dd | 1700 | rtx op; |
9878760c RK |
1701 | enum machine_mode mode; |
1702 | { | |
40501e5f | 1703 | HOST_WIDE_INT opl, oph; |
1d328b19 | 1704 | |
dfbdccdb GK |
1705 | if (gpc_reg_operand (op, mode)) |
1706 | return 1; | |
1d328b19 | 1707 | |
dfbdccdb | 1708 | if (GET_CODE (op) == CONST_INT) |
40501e5f AM |
1709 | { |
1710 | opl = INTVAL (op) & GET_MODE_MASK (mode); | |
1711 | ||
1712 | #if HOST_BITS_PER_WIDE_INT <= 32 | |
1713 | if (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT && opl < 0) | |
1714 | return 0; | |
1715 | #endif | |
1716 | } | |
dfbdccdb GK |
1717 | else if (GET_CODE (op) == CONST_DOUBLE) |
1718 | { | |
1d328b19 | 1719 | if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT) |
40501e5f | 1720 | abort (); |
1d328b19 GK |
1721 | |
1722 | opl = CONST_DOUBLE_LOW (op); | |
1723 | oph = CONST_DOUBLE_HIGH (op); | |
40501e5f | 1724 | if (oph != 0) |
38886f37 | 1725 | return 0; |
dfbdccdb GK |
1726 | } |
1727 | else | |
1728 | return 0; | |
1d328b19 | 1729 | |
40501e5f AM |
1730 | return ((opl & ~ (unsigned HOST_WIDE_INT) 0xffff) == 0 |
1731 | || (opl & ~ (unsigned HOST_WIDE_INT) 0xffff0000) == 0); | |
9878760c RK |
1732 | } |
1733 | ||
dcfedcd0 | 1734 | /* Return 1 if C is a constant that is not a logical operand (as |
1d328b19 | 1735 | above), but could be split into one. */ |
dcfedcd0 RK |
1736 | |
1737 | int | |
1738 | non_logical_cint_operand (op, mode) | |
592696dd | 1739 | rtx op; |
5f59ecb7 | 1740 | enum machine_mode mode; |
dcfedcd0 | 1741 | { |
dfbdccdb | 1742 | return ((GET_CODE (op) == CONST_INT || GET_CODE (op) == CONST_DOUBLE) |
1d328b19 GK |
1743 | && ! logical_operand (op, mode) |
1744 | && reg_or_logical_cint_operand (op, mode)); | |
dcfedcd0 RK |
1745 | } |
1746 | ||
19ba8161 | 1747 | /* Return 1 if C is a constant that can be encoded in a 32-bit mask on the |
9878760c RK |
1748 | RS/6000. It is if there are no more than two 1->0 or 0->1 transitions. |
1749 | Reject all ones and all zeros, since these should have been optimized | |
1750 | away and confuse the making of MB and ME. */ | |
1751 | ||
1752 | int | |
19ba8161 | 1753 | mask_operand (op, mode) |
592696dd | 1754 | rtx op; |
19ba8161 | 1755 | enum machine_mode mode ATTRIBUTE_UNUSED; |
9878760c | 1756 | { |
02071907 | 1757 | HOST_WIDE_INT c, lsb; |
9878760c | 1758 | |
19ba8161 DE |
1759 | if (GET_CODE (op) != CONST_INT) |
1760 | return 0; | |
1761 | ||
1762 | c = INTVAL (op); | |
1763 | ||
57deb3a1 AM |
1764 | /* Fail in 64-bit mode if the mask wraps around because the upper |
1765 | 32-bits of the mask will all be 1s, contrary to GCC's internal view. */ | |
1766 | if (TARGET_POWERPC64 && (c & 0x80000001) == 0x80000001) | |
1767 | return 0; | |
1768 | ||
c5059423 AM |
1769 | /* We don't change the number of transitions by inverting, |
1770 | so make sure we start with the LS bit zero. */ | |
1771 | if (c & 1) | |
1772 | c = ~c; | |
1773 | ||
1774 | /* Reject all zeros or all ones. */ | |
1775 | if (c == 0) | |
9878760c RK |
1776 | return 0; |
1777 | ||
c5059423 AM |
1778 | /* Find the first transition. */ |
1779 | lsb = c & -c; | |
1780 | ||
1781 | /* Invert to look for a second transition. */ | |
1782 | c = ~c; | |
9878760c | 1783 | |
c5059423 AM |
1784 | /* Erase first transition. */ |
1785 | c &= -lsb; | |
9878760c | 1786 | |
c5059423 AM |
1787 | /* Find the second transition (if any). */ |
1788 | lsb = c & -c; | |
1789 | ||
1790 | /* Match if all the bits above are 1's (or c is zero). */ | |
1791 | return c == -lsb; | |
9878760c RK |
1792 | } |
1793 | ||
0ba1b2ff AM |
1794 | /* Return 1 for the PowerPC64 rlwinm corner case. */ |
1795 | ||
1796 | int | |
1797 | mask_operand_wrap (op, mode) | |
1798 | rtx op; | |
1799 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
1800 | { | |
1801 | HOST_WIDE_INT c, lsb; | |
1802 | ||
1803 | if (GET_CODE (op) != CONST_INT) | |
1804 | return 0; | |
1805 | ||
1806 | c = INTVAL (op); | |
1807 | ||
1808 | if ((c & 0x80000001) != 0x80000001) | |
1809 | return 0; | |
1810 | ||
1811 | c = ~c; | |
1812 | if (c == 0) | |
1813 | return 0; | |
1814 | ||
1815 | lsb = c & -c; | |
1816 | c = ~c; | |
1817 | c &= -lsb; | |
1818 | lsb = c & -c; | |
1819 | return c == -lsb; | |
1820 | } | |
1821 | ||
a260abc9 DE |
1822 | /* Return 1 if the operand is a constant that is a PowerPC64 mask. |
1823 | It is if there are no more than one 1->0 or 0->1 transitions. | |
0ba1b2ff AM |
1824 | Reject all zeros, since zero should have been optimized away and |
1825 | confuses the making of MB and ME. */ | |
9878760c RK |
1826 | |
1827 | int | |
a260abc9 | 1828 | mask64_operand (op, mode) |
592696dd | 1829 | rtx op; |
0ba1b2ff | 1830 | enum machine_mode mode ATTRIBUTE_UNUSED; |
a260abc9 DE |
1831 | { |
1832 | if (GET_CODE (op) == CONST_INT) | |
1833 | { | |
02071907 | 1834 | HOST_WIDE_INT c, lsb; |
a260abc9 | 1835 | |
c5059423 | 1836 | c = INTVAL (op); |
a260abc9 | 1837 | |
0ba1b2ff | 1838 | /* Reject all zeros. */ |
c5059423 | 1839 | if (c == 0) |
e2c953b6 DE |
1840 | return 0; |
1841 | ||
0ba1b2ff AM |
1842 | /* We don't change the number of transitions by inverting, |
1843 | so make sure we start with the LS bit zero. */ | |
1844 | if (c & 1) | |
1845 | c = ~c; | |
1846 | ||
c5059423 AM |
1847 | /* Find the transition, and check that all bits above are 1's. */ |
1848 | lsb = c & -c; | |
e3981aab DE |
1849 | |
1850 | /* Match if all the bits above are 1's (or c is zero). */ | |
c5059423 | 1851 | return c == -lsb; |
e2c953b6 | 1852 | } |
0ba1b2ff AM |
1853 | return 0; |
1854 | } | |
1855 | ||
1856 | /* Like mask64_operand, but allow up to three transitions. This | |
1857 | predicate is used by insn patterns that generate two rldicl or | |
1858 | rldicr machine insns. */ | |
1859 | ||
1860 | int | |
1861 | mask64_2_operand (op, mode) | |
1862 | rtx op; | |
1863 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
1864 | { | |
1865 | if (GET_CODE (op) == CONST_INT) | |
a260abc9 | 1866 | { |
0ba1b2ff | 1867 | HOST_WIDE_INT c, lsb; |
a260abc9 | 1868 | |
0ba1b2ff | 1869 | c = INTVAL (op); |
a260abc9 | 1870 | |
0ba1b2ff AM |
1871 | /* Disallow all zeros. */ |
1872 | if (c == 0) | |
1873 | return 0; | |
a260abc9 | 1874 | |
0ba1b2ff AM |
1875 | /* We don't change the number of transitions by inverting, |
1876 | so make sure we start with the LS bit zero. */ | |
1877 | if (c & 1) | |
1878 | c = ~c; | |
a260abc9 | 1879 | |
0ba1b2ff AM |
1880 | /* Find the first transition. */ |
1881 | lsb = c & -c; | |
a260abc9 | 1882 | |
0ba1b2ff AM |
1883 | /* Invert to look for a second transition. */ |
1884 | c = ~c; | |
1885 | ||
1886 | /* Erase first transition. */ | |
1887 | c &= -lsb; | |
1888 | ||
1889 | /* Find the second transition. */ | |
1890 | lsb = c & -c; | |
1891 | ||
1892 | /* Invert to look for a third transition. */ | |
1893 | c = ~c; | |
1894 | ||
1895 | /* Erase second transition. */ | |
1896 | c &= -lsb; | |
1897 | ||
1898 | /* Find the third transition (if any). */ | |
1899 | lsb = c & -c; | |
1900 | ||
1901 | /* Match if all the bits above are 1's (or c is zero). */ | |
1902 | return c == -lsb; | |
1903 | } | |
1904 | return 0; | |
1905 | } | |
1906 | ||
1907 | /* Generates shifts and masks for a pair of rldicl or rldicr insns to | |
1908 | implement ANDing by the mask IN. */ | |
1909 | void | |
1910 | build_mask64_2_operands (in, out) | |
1911 | rtx in; | |
1912 | rtx *out; | |
1913 | { | |
1914 | #if HOST_BITS_PER_WIDE_INT >= 64 | |
1915 | unsigned HOST_WIDE_INT c, lsb, m1, m2; | |
1916 | int shift; | |
1917 | ||
1918 | if (GET_CODE (in) != CONST_INT) | |
1919 | abort (); | |
1920 | ||
1921 | c = INTVAL (in); | |
1922 | if (c & 1) | |
1923 | { | |
1924 | /* Assume c initially something like 0x00fff000000fffff. The idea | |
1925 | is to rotate the word so that the middle ^^^^^^ group of zeros | |
1926 | is at the MS end and can be cleared with an rldicl mask. We then | |
1927 | rotate back and clear off the MS ^^ group of zeros with a | |
1928 | second rldicl. */ | |
1929 | c = ~c; /* c == 0xff000ffffff00000 */ | |
1930 | lsb = c & -c; /* lsb == 0x0000000000100000 */ | |
1931 | m1 = -lsb; /* m1 == 0xfffffffffff00000 */ | |
1932 | c = ~c; /* c == 0x00fff000000fffff */ | |
1933 | c &= -lsb; /* c == 0x00fff00000000000 */ | |
1934 | lsb = c & -c; /* lsb == 0x0000100000000000 */ | |
1935 | c = ~c; /* c == 0xff000fffffffffff */ | |
1936 | c &= -lsb; /* c == 0xff00000000000000 */ | |
1937 | shift = 0; | |
1938 | while ((lsb >>= 1) != 0) | |
1939 | shift++; /* shift == 44 on exit from loop */ | |
1940 | m1 <<= 64 - shift; /* m1 == 0xffffff0000000000 */ | |
1941 | m1 = ~m1; /* m1 == 0x000000ffffffffff */ | |
1942 | m2 = ~c; /* m2 == 0x00ffffffffffffff */ | |
a260abc9 DE |
1943 | } |
1944 | else | |
0ba1b2ff AM |
1945 | { |
1946 | /* Assume c initially something like 0xff000f0000000000. The idea | |
1947 | is to rotate the word so that the ^^^ middle group of zeros | |
1948 | is at the LS end and can be cleared with an rldicr mask. We then | |
1949 | rotate back and clear off the LS group of ^^^^^^^^^^ zeros with | |
1950 | a second rldicr. */ | |
1951 | lsb = c & -c; /* lsb == 0x0000010000000000 */ | |
1952 | m2 = -lsb; /* m2 == 0xffffff0000000000 */ | |
1953 | c = ~c; /* c == 0x00fff0ffffffffff */ | |
1954 | c &= -lsb; /* c == 0x00fff00000000000 */ | |
1955 | lsb = c & -c; /* lsb == 0x0000100000000000 */ | |
1956 | c = ~c; /* c == 0xff000fffffffffff */ | |
1957 | c &= -lsb; /* c == 0xff00000000000000 */ | |
1958 | shift = 0; | |
1959 | while ((lsb >>= 1) != 0) | |
1960 | shift++; /* shift == 44 on exit from loop */ | |
1961 | m1 = ~c; /* m1 == 0x00ffffffffffffff */ | |
1962 | m1 >>= shift; /* m1 == 0x0000000000000fff */ | |
1963 | m1 = ~m1; /* m1 == 0xfffffffffffff000 */ | |
1964 | } | |
1965 | ||
1966 | /* Note that when we only have two 0->1 and 1->0 transitions, one of the | |
1967 | masks will be all 1's. We are guaranteed more than one transition. */ | |
1968 | out[0] = GEN_INT (64 - shift); | |
1969 | out[1] = GEN_INT (m1); | |
1970 | out[2] = GEN_INT (shift); | |
1971 | out[3] = GEN_INT (m2); | |
1972 | #else | |
045572c7 GK |
1973 | (void)in; |
1974 | (void)out; | |
0ba1b2ff AM |
1975 | abort (); |
1976 | #endif | |
a260abc9 DE |
1977 | } |
1978 | ||
1979 | /* Return 1 if the operand is either a non-special register or a constant | |
1980 | that can be used as the operand of a PowerPC64 logical AND insn. */ | |
1981 | ||
1982 | int | |
1983 | and64_operand (op, mode) | |
592696dd | 1984 | rtx op; |
9878760c RK |
1985 | enum machine_mode mode; |
1986 | { | |
a4f6c312 | 1987 | if (fixed_regs[CR0_REGNO]) /* CR0 not available, don't do andi./andis. */ |
52d3af72 DE |
1988 | return (gpc_reg_operand (op, mode) || mask64_operand (op, mode)); |
1989 | ||
1990 | return (logical_operand (op, mode) || mask64_operand (op, mode)); | |
9878760c RK |
1991 | } |
1992 | ||
0ba1b2ff AM |
1993 | /* Like the above, but also match constants that can be implemented |
1994 | with two rldicl or rldicr insns. */ | |
1995 | ||
1996 | int | |
1997 | and64_2_operand (op, mode) | |
1998 | rtx op; | |
1999 | enum machine_mode mode; | |
2000 | { | |
2001 | if (fixed_regs[CR0_REGNO]) /* CR0 not available, don't do andi./andis. */ | |
2002 | return gpc_reg_operand (op, mode) || mask64_2_operand (op, mode); | |
2003 | ||
2004 | return logical_operand (op, mode) || mask64_2_operand (op, mode); | |
2005 | } | |
2006 | ||
a260abc9 DE |
2007 | /* Return 1 if the operand is either a non-special register or a |
2008 | constant that can be used as the operand of an RS/6000 logical AND insn. */ | |
dcfedcd0 RK |
2009 | |
2010 | int | |
a260abc9 | 2011 | and_operand (op, mode) |
592696dd | 2012 | rtx op; |
a260abc9 | 2013 | enum machine_mode mode; |
dcfedcd0 | 2014 | { |
a4f6c312 | 2015 | if (fixed_regs[CR0_REGNO]) /* CR0 not available, don't do andi./andis. */ |
52d3af72 DE |
2016 | return (gpc_reg_operand (op, mode) || mask_operand (op, mode)); |
2017 | ||
2018 | return (logical_operand (op, mode) || mask_operand (op, mode)); | |
dcfedcd0 RK |
2019 | } |
2020 | ||
9878760c RK |
2021 | /* Return 1 if the operand is a general register or memory operand. */ |
2022 | ||
2023 | int | |
2024 | reg_or_mem_operand (op, mode) | |
592696dd SS |
2025 | rtx op; |
2026 | enum machine_mode mode; | |
9878760c | 2027 | { |
b6c9286a MM |
2028 | return (gpc_reg_operand (op, mode) |
2029 | || memory_operand (op, mode) | |
2030 | || volatile_mem_operand (op, mode)); | |
9878760c RK |
2031 | } |
2032 | ||
a7a813f7 | 2033 | /* Return 1 if the operand is a general register or memory operand without |
3cb999d8 | 2034 | pre_inc or pre_dec which produces invalid form of PowerPC lwa |
a7a813f7 RK |
2035 | instruction. */ |
2036 | ||
2037 | int | |
2038 | lwa_operand (op, mode) | |
592696dd SS |
2039 | rtx op; |
2040 | enum machine_mode mode; | |
a7a813f7 RK |
2041 | { |
2042 | rtx inner = op; | |
2043 | ||
2044 | if (reload_completed && GET_CODE (inner) == SUBREG) | |
2045 | inner = SUBREG_REG (inner); | |
2046 | ||
2047 | return gpc_reg_operand (inner, mode) | |
2048 | || (memory_operand (inner, mode) | |
2049 | && GET_CODE (XEXP (inner, 0)) != PRE_INC | |
6a40a9d6 DE |
2050 | && GET_CODE (XEXP (inner, 0)) != PRE_DEC |
2051 | && (GET_CODE (XEXP (inner, 0)) != PLUS | |
e903c96a DE |
2052 | || GET_CODE (XEXP (XEXP (inner, 0), 1)) != CONST_INT |
2053 | || INTVAL (XEXP (XEXP (inner, 0), 1)) % 4 == 0)); | |
a7a813f7 RK |
2054 | } |
2055 | ||
cc4d5fec JH |
2056 | /* Return 1 if the operand, used inside a MEM, is a SYMBOL_REF. */ |
2057 | ||
2058 | int | |
2059 | symbol_ref_operand (op, mode) | |
2060 | rtx op; | |
2061 | enum machine_mode mode; | |
2062 | { | |
2063 | if (mode != VOIDmode && GET_MODE (op) != mode) | |
2064 | return 0; | |
2065 | ||
2066 | return (GET_CODE (op) == SYMBOL_REF); | |
2067 | } | |
2068 | ||
9878760c | 2069 | /* Return 1 if the operand, used inside a MEM, is a valid first argument |
cc4d5fec | 2070 | to CALL. This is a SYMBOL_REF, a pseudo-register, LR or CTR. */ |
9878760c RK |
2071 | |
2072 | int | |
2073 | call_operand (op, mode) | |
592696dd | 2074 | rtx op; |
9878760c RK |
2075 | enum machine_mode mode; |
2076 | { | |
2077 | if (mode != VOIDmode && GET_MODE (op) != mode) | |
2078 | return 0; | |
2079 | ||
2080 | return (GET_CODE (op) == SYMBOL_REF | |
cc4d5fec JH |
2081 | || (GET_CODE (op) == REG |
2082 | && (REGNO (op) == LINK_REGISTER_REGNUM | |
2083 | || REGNO (op) == COUNT_REGISTER_REGNUM | |
2084 | || REGNO (op) >= FIRST_PSEUDO_REGISTER))); | |
9878760c RK |
2085 | } |
2086 | ||
2af3d377 | 2087 | /* Return 1 if the operand is a SYMBOL_REF for a function known to be in |
a4f6c312 | 2088 | this file and the function is not weakly defined. */ |
2af3d377 RK |
2089 | |
2090 | int | |
2091 | current_file_function_operand (op, mode) | |
592696dd | 2092 | rtx op; |
296b8152 | 2093 | enum machine_mode mode ATTRIBUTE_UNUSED; |
2af3d377 RK |
2094 | { |
2095 | return (GET_CODE (op) == SYMBOL_REF | |
2096 | && (SYMBOL_REF_FLAG (op) | |
8f1b829e | 2097 | || (op == XEXP (DECL_RTL (current_function_decl), 0) |
c81fc13e | 2098 | && ! DECL_WEAK (current_function_decl)))); |
2af3d377 RK |
2099 | } |
2100 | ||
9878760c RK |
2101 | /* Return 1 if this operand is a valid input for a move insn. */ |
2102 | ||
2103 | int | |
2104 | input_operand (op, mode) | |
592696dd | 2105 | rtx op; |
9878760c RK |
2106 | enum machine_mode mode; |
2107 | { | |
eb4e8003 | 2108 | /* Memory is always valid. */ |
9878760c RK |
2109 | if (memory_operand (op, mode)) |
2110 | return 1; | |
2111 | ||
34792e82 | 2112 | /* Only a tiny bit of handling for CONSTANT_P_RTX is necessary. */ |
01b4cf2b | 2113 | if (GET_CODE (op) == CONSTANT_P_RTX) |
34792e82 JL |
2114 | return 1; |
2115 | ||
eb4e8003 RK |
2116 | /* For floating-point, easy constants are valid. */ |
2117 | if (GET_MODE_CLASS (mode) == MODE_FLOAT | |
2118 | && CONSTANT_P (op) | |
2119 | && easy_fp_constant (op, mode)) | |
2120 | return 1; | |
2121 | ||
4e74d8ec MM |
2122 | /* Allow any integer constant. */ |
2123 | if (GET_MODE_CLASS (mode) == MODE_INT | |
e675f625 | 2124 | && (GET_CODE (op) == CONST_INT |
e675f625 | 2125 | || GET_CODE (op) == CONST_DOUBLE)) |
4e74d8ec MM |
2126 | return 1; |
2127 | ||
d744e06e AH |
2128 | /* Allow easy vector constants. */ |
2129 | if (GET_CODE (op) == CONST_VECTOR | |
2130 | && easy_vector_constant (op, mode)) | |
2131 | return 1; | |
2132 | ||
eb4e8003 RK |
2133 | /* For floating-point or multi-word mode, the only remaining valid type |
2134 | is a register. */ | |
9878760c RK |
2135 | if (GET_MODE_CLASS (mode) == MODE_FLOAT |
2136 | || GET_MODE_SIZE (mode) > UNITS_PER_WORD) | |
eb4e8003 | 2137 | return register_operand (op, mode); |
9878760c | 2138 | |
88fe15a1 RK |
2139 | /* The only cases left are integral modes one word or smaller (we |
2140 | do not get called for MODE_CC values). These can be in any | |
2141 | register. */ | |
2142 | if (register_operand (op, mode)) | |
a8b3aeda | 2143 | return 1; |
88fe15a1 | 2144 | |
84cf9dda | 2145 | /* A SYMBOL_REF referring to the TOC is valid. */ |
7fec4abd | 2146 | if (LEGITIMATE_CONSTANT_POOL_ADDRESS_P (op)) |
84cf9dda RK |
2147 | return 1; |
2148 | ||
9ebbca7d GK |
2149 | /* A constant pool expression (relative to the TOC) is valid */ |
2150 | if (TOC_RELATIVE_EXPR_P (op)) | |
b6c9286a MM |
2151 | return 1; |
2152 | ||
88228c4b MM |
2153 | /* V.4 allows SYMBOL_REFs and CONSTs that are in the small data region |
2154 | to be valid. */ | |
f607bc57 | 2155 | if (DEFAULT_ABI == ABI_V4 |
88228c4b MM |
2156 | && (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST) |
2157 | && small_data_operand (op, Pmode)) | |
2158 | return 1; | |
2159 | ||
042259f2 | 2160 | return 0; |
9878760c | 2161 | } |
7509c759 | 2162 | |
a4f6c312 | 2163 | /* Return 1 for an operand in small memory on V.4/eabi. */ |
7509c759 MM |
2164 | |
2165 | int | |
2166 | small_data_operand (op, mode) | |
296b8152 KG |
2167 | rtx op ATTRIBUTE_UNUSED; |
2168 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
7509c759 | 2169 | { |
38c1f2d7 | 2170 | #if TARGET_ELF |
5f59ecb7 | 2171 | rtx sym_ref; |
7509c759 | 2172 | |
d9407988 | 2173 | if (rs6000_sdata == SDATA_NONE || rs6000_sdata == SDATA_DATA) |
a54d04b7 | 2174 | return 0; |
a54d04b7 | 2175 | |
f607bc57 | 2176 | if (DEFAULT_ABI != ABI_V4) |
7509c759 MM |
2177 | return 0; |
2178 | ||
88228c4b MM |
2179 | if (GET_CODE (op) == SYMBOL_REF) |
2180 | sym_ref = op; | |
2181 | ||
2182 | else if (GET_CODE (op) != CONST | |
2183 | || GET_CODE (XEXP (op, 0)) != PLUS | |
2184 | || GET_CODE (XEXP (XEXP (op, 0), 0)) != SYMBOL_REF | |
2185 | || GET_CODE (XEXP (XEXP (op, 0), 1)) != CONST_INT) | |
7509c759 MM |
2186 | return 0; |
2187 | ||
88228c4b | 2188 | else |
dbf55e53 MM |
2189 | { |
2190 | rtx sum = XEXP (op, 0); | |
2191 | HOST_WIDE_INT summand; | |
2192 | ||
2193 | /* We have to be careful here, because it is the referenced address | |
2194 | that must be 32k from _SDA_BASE_, not just the symbol. */ | |
2195 | summand = INTVAL (XEXP (sum, 1)); | |
2196 | if (summand < 0 || summand > g_switch_value) | |
2197 | return 0; | |
2198 | ||
2199 | sym_ref = XEXP (sum, 0); | |
2200 | } | |
88228c4b MM |
2201 | |
2202 | if (*XSTR (sym_ref, 0) != '@') | |
7509c759 MM |
2203 | return 0; |
2204 | ||
2205 | return 1; | |
d9407988 MM |
2206 | |
2207 | #else | |
2208 | return 0; | |
2209 | #endif | |
7509c759 | 2210 | } |
9ebbca7d GK |
2211 | \f |
2212 | static int | |
2213 | constant_pool_expr_1 (op, have_sym, have_toc) | |
2214 | rtx op; | |
2215 | int *have_sym; | |
2216 | int *have_toc; | |
2217 | { | |
2218 | switch (GET_CODE(op)) | |
2219 | { | |
2220 | case SYMBOL_REF: | |
a4f6c312 SS |
2221 | if (CONSTANT_POOL_ADDRESS_P (op)) |
2222 | { | |
2223 | if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (op), Pmode)) | |
2224 | { | |
2225 | *have_sym = 1; | |
2226 | return 1; | |
2227 | } | |
2228 | else | |
2229 | return 0; | |
2230 | } | |
2231 | else if (! strcmp (XSTR (op, 0), toc_label_name)) | |
2232 | { | |
2233 | *have_toc = 1; | |
2234 | return 1; | |
2235 | } | |
2236 | else | |
2237 | return 0; | |
9ebbca7d GK |
2238 | case PLUS: |
2239 | case MINUS: | |
c1f11548 DE |
2240 | return (constant_pool_expr_1 (XEXP (op, 0), have_sym, have_toc) |
2241 | && constant_pool_expr_1 (XEXP (op, 1), have_sym, have_toc)); | |
9ebbca7d | 2242 | case CONST: |
a4f6c312 | 2243 | return constant_pool_expr_1 (XEXP (op, 0), have_sym, have_toc); |
9ebbca7d | 2244 | case CONST_INT: |
a4f6c312 | 2245 | return 1; |
9ebbca7d | 2246 | default: |
a4f6c312 | 2247 | return 0; |
9ebbca7d GK |
2248 | } |
2249 | } | |
2250 | ||
2251 | int | |
2252 | constant_pool_expr_p (op) | |
2253 | rtx op; | |
2254 | { | |
2255 | int have_sym = 0; | |
2256 | int have_toc = 0; | |
2257 | return constant_pool_expr_1 (op, &have_sym, &have_toc) && have_sym; | |
2258 | } | |
2259 | ||
2260 | int | |
2261 | toc_relative_expr_p (op) | |
2262 | rtx op; | |
2263 | { | |
2264 | int have_sym = 0; | |
2265 | int have_toc = 0; | |
2266 | return constant_pool_expr_1 (op, &have_sym, &have_toc) && have_toc; | |
2267 | } | |
2268 | ||
2269 | /* Try machine-dependent ways of modifying an illegitimate address | |
2270 | to be legitimate. If we find one, return the new, valid address. | |
2271 | This is used from only one place: `memory_address' in explow.c. | |
2272 | ||
a4f6c312 SS |
2273 | OLDX is the address as it was before break_out_memory_refs was |
2274 | called. In some cases it is useful to look at this to decide what | |
2275 | needs to be done. | |
9ebbca7d | 2276 | |
a4f6c312 | 2277 | MODE is passed so that this function can use GO_IF_LEGITIMATE_ADDRESS. |
9ebbca7d | 2278 | |
a4f6c312 SS |
2279 | It is always safe for this function to do nothing. It exists to |
2280 | recognize opportunities to optimize the output. | |
9ebbca7d GK |
2281 | |
2282 | On RS/6000, first check for the sum of a register with a constant | |
2283 | integer that is out of range. If so, generate code to add the | |
2284 | constant with the low-order 16 bits masked to the register and force | |
2285 | this result into another register (this can be done with `cau'). | |
2286 | Then generate an address of REG+(CONST&0xffff), allowing for the | |
2287 | possibility of bit 16 being a one. | |
2288 | ||
2289 | Then check for the sum of a register and something not constant, try to | |
2290 | load the other things into a register and return the sum. */ | |
2291 | rtx | |
2292 | rs6000_legitimize_address (x, oldx, mode) | |
2293 | rtx x; | |
2294 | rtx oldx ATTRIBUTE_UNUSED; | |
2295 | enum machine_mode mode; | |
0ac081f6 | 2296 | { |
9ebbca7d GK |
2297 | if (GET_CODE (x) == PLUS |
2298 | && GET_CODE (XEXP (x, 0)) == REG | |
2299 | && GET_CODE (XEXP (x, 1)) == CONST_INT | |
2300 | && (unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 1)) + 0x8000) >= 0x10000) | |
2301 | { | |
2302 | HOST_WIDE_INT high_int, low_int; | |
2303 | rtx sum; | |
a65c591c DE |
2304 | low_int = ((INTVAL (XEXP (x, 1)) & 0xffff) ^ 0x8000) - 0x8000; |
2305 | high_int = INTVAL (XEXP (x, 1)) - low_int; | |
9ebbca7d GK |
2306 | sum = force_operand (gen_rtx_PLUS (Pmode, XEXP (x, 0), |
2307 | GEN_INT (high_int)), 0); | |
2308 | return gen_rtx_PLUS (Pmode, sum, GEN_INT (low_int)); | |
2309 | } | |
2310 | else if (GET_CODE (x) == PLUS | |
2311 | && GET_CODE (XEXP (x, 0)) == REG | |
2312 | && GET_CODE (XEXP (x, 1)) != CONST_INT | |
6ac7bf2c | 2313 | && GET_MODE_NUNITS (mode) == 1 |
a3170dc6 AH |
2314 | && ((TARGET_HARD_FLOAT && TARGET_FPRS) |
2315 | || TARGET_POWERPC64 | |
fcce224d | 2316 | || (mode != DFmode && mode != TFmode)) |
9ebbca7d GK |
2317 | && (TARGET_POWERPC64 || mode != DImode) |
2318 | && mode != TImode) | |
2319 | { | |
2320 | return gen_rtx_PLUS (Pmode, XEXP (x, 0), | |
2321 | force_reg (Pmode, force_operand (XEXP (x, 1), 0))); | |
2322 | } | |
0ac081f6 AH |
2323 | else if (ALTIVEC_VECTOR_MODE (mode)) |
2324 | { | |
2325 | rtx reg; | |
2326 | ||
2327 | /* Make sure both operands are registers. */ | |
2328 | if (GET_CODE (x) == PLUS) | |
9f85ed45 | 2329 | return gen_rtx_PLUS (Pmode, force_reg (Pmode, XEXP (x, 0)), |
0ac081f6 AH |
2330 | force_reg (Pmode, XEXP (x, 1))); |
2331 | ||
2332 | reg = force_reg (Pmode, x); | |
2333 | return reg; | |
2334 | } | |
a3170dc6 AH |
2335 | else if (SPE_VECTOR_MODE (mode)) |
2336 | { | |
2337 | /* We accept [reg + reg] and [reg + OFFSET]. */ | |
2338 | ||
2339 | if (GET_CODE (x) == PLUS) | |
2340 | { | |
2341 | rtx op1 = XEXP (x, 0); | |
2342 | rtx op2 = XEXP (x, 1); | |
2343 | ||
2344 | op1 = force_reg (Pmode, op1); | |
2345 | ||
2346 | if (GET_CODE (op2) != REG | |
2347 | && (GET_CODE (op2) != CONST_INT | |
2348 | || !SPE_CONST_OFFSET_OK (INTVAL (op2)))) | |
2349 | op2 = force_reg (Pmode, op2); | |
2350 | ||
2351 | return gen_rtx_PLUS (Pmode, op1, op2); | |
2352 | } | |
2353 | ||
2354 | return force_reg (Pmode, x); | |
2355 | } | |
f1384257 AM |
2356 | else if (TARGET_ELF |
2357 | && TARGET_32BIT | |
2358 | && TARGET_NO_TOC | |
2359 | && ! flag_pic | |
9ebbca7d GK |
2360 | && GET_CODE (x) != CONST_INT |
2361 | && GET_CODE (x) != CONST_DOUBLE | |
2362 | && CONSTANT_P (x) | |
6ac7bf2c GK |
2363 | && GET_MODE_NUNITS (mode) == 1 |
2364 | && (GET_MODE_BITSIZE (mode) <= 32 | |
a3170dc6 | 2365 | || ((TARGET_HARD_FLOAT && TARGET_FPRS) && mode == DFmode))) |
9ebbca7d GK |
2366 | { |
2367 | rtx reg = gen_reg_rtx (Pmode); | |
2368 | emit_insn (gen_elf_high (reg, (x))); | |
2369 | return gen_rtx_LO_SUM (Pmode, reg, (x)); | |
2370 | } | |
ee890fe2 SS |
2371 | else if (TARGET_MACHO && TARGET_32BIT && TARGET_NO_TOC |
2372 | && ! flag_pic | |
ab82a49f AP |
2373 | #if TARGET_MACHO |
2374 | && ! MACHO_DYNAMIC_NO_PIC_P | |
2375 | #endif | |
ee890fe2 SS |
2376 | && GET_CODE (x) != CONST_INT |
2377 | && GET_CODE (x) != CONST_DOUBLE | |
2378 | && CONSTANT_P (x) | |
a3170dc6 | 2379 | && ((TARGET_HARD_FLOAT && TARGET_FPRS) || mode != DFmode) |
ee890fe2 SS |
2380 | && mode != DImode |
2381 | && mode != TImode) | |
2382 | { | |
2383 | rtx reg = gen_reg_rtx (Pmode); | |
2384 | emit_insn (gen_macho_high (reg, (x))); | |
2385 | return gen_rtx_LO_SUM (Pmode, reg, (x)); | |
2386 | } | |
9ebbca7d GK |
2387 | else if (TARGET_TOC |
2388 | && CONSTANT_POOL_EXPR_P (x) | |
a9098fd0 | 2389 | && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x), Pmode)) |
9ebbca7d GK |
2390 | { |
2391 | return create_TOC_reference (x); | |
2392 | } | |
2393 | else | |
2394 | return NULL_RTX; | |
2395 | } | |
258bfae2 | 2396 | |
24ea750e DJ |
2397 | /* The convention appears to be to define this wherever it is used. |
2398 | With legitimize_reload_address now defined here, REG_MODE_OK_FOR_BASE_P | |
2399 | is now used here. */ | |
2400 | #ifndef REG_MODE_OK_FOR_BASE_P | |
2401 | #define REG_MODE_OK_FOR_BASE_P(REGNO, MODE) REG_OK_FOR_BASE_P (REGNO) | |
2402 | #endif | |
2403 | ||
2404 | /* Our implementation of LEGITIMIZE_RELOAD_ADDRESS. Returns a value to | |
2405 | replace the input X, or the original X if no replacement is called for. | |
2406 | The output parameter *WIN is 1 if the calling macro should goto WIN, | |
2407 | 0 if it should not. | |
2408 | ||
2409 | For RS/6000, we wish to handle large displacements off a base | |
2410 | register by splitting the addend across an addiu/addis and the mem insn. | |
2411 | This cuts number of extra insns needed from 3 to 1. | |
2412 | ||
2413 | On Darwin, we use this to generate code for floating point constants. | |
2414 | A movsf_low is generated so we wind up with 2 instructions rather than 3. | |
2415 | The Darwin code is inside #if TARGET_MACHO because only then is | |
2416 | machopic_function_base_name() defined. */ | |
2417 | rtx | |
2418 | rs6000_legitimize_reload_address (x, mode, opnum, type, ind_levels, win) | |
2419 | rtx x; | |
2420 | enum machine_mode mode; | |
2421 | int opnum; | |
2422 | int type; | |
2423 | int ind_levels ATTRIBUTE_UNUSED; | |
2424 | int *win; | |
2425 | { | |
2426 | /* We must recognize output that we have already generated ourselves. */ | |
2427 | if (GET_CODE (x) == PLUS | |
2428 | && GET_CODE (XEXP (x, 0)) == PLUS | |
2429 | && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG | |
2430 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT | |
2431 | && GET_CODE (XEXP (x, 1)) == CONST_INT) | |
2432 | { | |
2433 | push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL, | |
2434 | BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0, | |
2435 | opnum, (enum reload_type)type); | |
2436 | *win = 1; | |
2437 | return x; | |
2438 | } | |
3deb2758 | 2439 | |
24ea750e DJ |
2440 | #if TARGET_MACHO |
2441 | if (DEFAULT_ABI == ABI_DARWIN && flag_pic | |
2442 | && GET_CODE (x) == LO_SUM | |
2443 | && GET_CODE (XEXP (x, 0)) == PLUS | |
2444 | && XEXP (XEXP (x, 0), 0) == pic_offset_table_rtx | |
2445 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == HIGH | |
2446 | && GET_CODE (XEXP (XEXP (XEXP (x, 0), 1), 0)) == CONST | |
2447 | && XEXP (XEXP (XEXP (x, 0), 1), 0) == XEXP (x, 1) | |
2448 | && GET_CODE (XEXP (XEXP (x, 1), 0)) == MINUS | |
2449 | && GET_CODE (XEXP (XEXP (XEXP (x, 1), 0), 0)) == SYMBOL_REF | |
2450 | && GET_CODE (XEXP (XEXP (XEXP (x, 1), 0), 1)) == SYMBOL_REF) | |
2451 | { | |
2452 | /* Result of previous invocation of this function on Darwin | |
6f317ef3 | 2453 | floating point constant. */ |
24ea750e DJ |
2454 | push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL, |
2455 | BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, | |
2456 | opnum, (enum reload_type)type); | |
2457 | *win = 1; | |
2458 | return x; | |
2459 | } | |
2460 | #endif | |
2461 | if (GET_CODE (x) == PLUS | |
2462 | && GET_CODE (XEXP (x, 0)) == REG | |
2463 | && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER | |
2464 | && REG_MODE_OK_FOR_BASE_P (XEXP (x, 0), mode) | |
78c875e8 | 2465 | && GET_CODE (XEXP (x, 1)) == CONST_INT |
93638d7a | 2466 | && !SPE_VECTOR_MODE (mode) |
78c875e8 | 2467 | && !ALTIVEC_VECTOR_MODE (mode)) |
24ea750e DJ |
2468 | { |
2469 | HOST_WIDE_INT val = INTVAL (XEXP (x, 1)); | |
2470 | HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000; | |
2471 | HOST_WIDE_INT high | |
2472 | = (((val - low) & 0xffffffff) ^ 0x80000000) - 0x80000000; | |
2473 | ||
2474 | /* Check for 32-bit overflow. */ | |
2475 | if (high + low != val) | |
2476 | { | |
2477 | *win = 0; | |
2478 | return x; | |
2479 | } | |
2480 | ||
2481 | /* Reload the high part into a base reg; leave the low part | |
2482 | in the mem directly. */ | |
2483 | ||
2484 | x = gen_rtx_PLUS (GET_MODE (x), | |
2485 | gen_rtx_PLUS (GET_MODE (x), XEXP (x, 0), | |
2486 | GEN_INT (high)), | |
2487 | GEN_INT (low)); | |
2488 | ||
2489 | push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL, | |
2490 | BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0, | |
2491 | opnum, (enum reload_type)type); | |
2492 | *win = 1; | |
2493 | return x; | |
2494 | } | |
2495 | #if TARGET_MACHO | |
2496 | if (GET_CODE (x) == SYMBOL_REF | |
2497 | && DEFAULT_ABI == ABI_DARWIN | |
69ef87e2 | 2498 | && !ALTIVEC_VECTOR_MODE (mode) |
24ea750e DJ |
2499 | && flag_pic) |
2500 | { | |
2501 | /* Darwin load of floating point constant. */ | |
2502 | rtx offset = gen_rtx (CONST, Pmode, | |
2503 | gen_rtx (MINUS, Pmode, x, | |
2504 | gen_rtx (SYMBOL_REF, Pmode, | |
2505 | machopic_function_base_name ()))); | |
2506 | x = gen_rtx (LO_SUM, GET_MODE (x), | |
2507 | gen_rtx (PLUS, Pmode, pic_offset_table_rtx, | |
2508 | gen_rtx (HIGH, Pmode, offset)), offset); | |
2509 | push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL, | |
2510 | BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, | |
2511 | opnum, (enum reload_type)type); | |
2512 | *win = 1; | |
2513 | return x; | |
2514 | } | |
ab82a49f AP |
2515 | if (GET_CODE (x) == SYMBOL_REF |
2516 | && DEFAULT_ABI == ABI_DARWIN | |
2517 | && !ALTIVEC_VECTOR_MODE (mode) | |
2518 | && MACHO_DYNAMIC_NO_PIC_P) | |
2519 | { | |
2520 | /* Darwin load of floating point constant. */ | |
2521 | x = gen_rtx (LO_SUM, GET_MODE (x), | |
2522 | gen_rtx (HIGH, Pmode, x), x); | |
2523 | push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL, | |
2524 | BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, | |
2525 | opnum, (enum reload_type)type); | |
2526 | *win = 1; | |
2527 | return x; | |
2528 | } | |
24ea750e DJ |
2529 | #endif |
2530 | if (TARGET_TOC | |
c1f11548 DE |
2531 | && CONSTANT_POOL_EXPR_P (x) |
2532 | && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x), mode)) | |
24ea750e DJ |
2533 | { |
2534 | (x) = create_TOC_reference (x); | |
2535 | *win = 1; | |
2536 | return x; | |
2537 | } | |
2538 | *win = 0; | |
2539 | return x; | |
2540 | } | |
2541 | ||
258bfae2 FS |
2542 | /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression |
2543 | that is a valid memory address for an instruction. | |
2544 | The MODE argument is the machine mode for the MEM expression | |
2545 | that wants to use this address. | |
2546 | ||
2547 | On the RS/6000, there are four valid address: a SYMBOL_REF that | |
2548 | refers to a constant pool entry of an address (or the sum of it | |
2549 | plus a constant), a short (16-bit signed) constant plus a register, | |
2550 | the sum of two registers, or a register indirect, possibly with an | |
5bdc5878 | 2551 | auto-increment. For DFmode and DImode with a constant plus register, |
258bfae2 FS |
2552 | we must ensure that both words are addressable or PowerPC64 with offset |
2553 | word aligned. | |
2554 | ||
2555 | For modes spanning multiple registers (DFmode in 32-bit GPRs, | |
2556 | 32-bit DImode, TImode), indexed addressing cannot be used because | |
2557 | adjacent memory cells are accessed by adding word-sized offsets | |
2558 | during assembly output. */ | |
2559 | int | |
2560 | rs6000_legitimate_address (mode, x, reg_ok_strict) | |
2561 | enum machine_mode mode; | |
2562 | rtx x; | |
2563 | int reg_ok_strict; | |
2564 | { | |
2565 | if (LEGITIMATE_INDIRECT_ADDRESS_P (x, reg_ok_strict)) | |
2566 | return 1; | |
2567 | if ((GET_CODE (x) == PRE_INC || GET_CODE (x) == PRE_DEC) | |
0d6d6892 | 2568 | && !ALTIVEC_VECTOR_MODE (mode) |
a3170dc6 | 2569 | && !SPE_VECTOR_MODE (mode) |
258bfae2 FS |
2570 | && TARGET_UPDATE |
2571 | && LEGITIMATE_INDIRECT_ADDRESS_P (XEXP (x, 0), reg_ok_strict)) | |
2572 | return 1; | |
2573 | if (LEGITIMATE_SMALL_DATA_P (mode, x)) | |
2574 | return 1; | |
2575 | if (LEGITIMATE_CONSTANT_POOL_ADDRESS_P (x)) | |
2576 | return 1; | |
2577 | /* If not REG_OK_STRICT (before reload) let pass any stack offset. */ | |
2578 | if (! reg_ok_strict | |
2579 | && GET_CODE (x) == PLUS | |
2580 | && GET_CODE (XEXP (x, 0)) == REG | |
2581 | && XEXP (x, 0) == virtual_stack_vars_rtx | |
2582 | && GET_CODE (XEXP (x, 1)) == CONST_INT) | |
2583 | return 1; | |
2584 | if (LEGITIMATE_OFFSET_ADDRESS_P (mode, x, reg_ok_strict)) | |
2585 | return 1; | |
2586 | if (mode != TImode | |
a3170dc6 AH |
2587 | && ((TARGET_HARD_FLOAT && TARGET_FPRS) |
2588 | || TARGET_POWERPC64 | |
fcce224d | 2589 | || (mode != DFmode && mode != TFmode)) |
258bfae2 FS |
2590 | && (TARGET_POWERPC64 || mode != DImode) |
2591 | && LEGITIMATE_INDEXED_ADDRESS_P (x, reg_ok_strict)) | |
2592 | return 1; | |
2593 | if (LEGITIMATE_LO_SUM_ADDRESS_P (mode, x, reg_ok_strict)) | |
2594 | return 1; | |
2595 | return 0; | |
2596 | } | |
fb4d4348 | 2597 | \f |
a4f6c312 SS |
2598 | /* Try to output insns to set TARGET equal to the constant C if it can |
2599 | be done in less than N insns. Do all computations in MODE. | |
2600 | Returns the place where the output has been placed if it can be | |
2601 | done and the insns have been emitted. If it would take more than N | |
2602 | insns, zero is returned and no insns and emitted. */ | |
2bfcf297 DB |
2603 | |
2604 | rtx | |
2605 | rs6000_emit_set_const (dest, mode, source, n) | |
2606 | rtx dest, source; | |
2607 | enum machine_mode mode; | |
2608 | int n ATTRIBUTE_UNUSED; | |
2609 | { | |
af8cb5c5 | 2610 | rtx result, insn, set; |
2bfcf297 DB |
2611 | HOST_WIDE_INT c0, c1; |
2612 | ||
af8cb5c5 | 2613 | if (mode == QImode || mode == HImode) |
2bfcf297 DB |
2614 | { |
2615 | if (dest == NULL) | |
2616 | dest = gen_reg_rtx (mode); | |
2617 | emit_insn (gen_rtx_SET (VOIDmode, dest, source)); | |
2618 | return dest; | |
2619 | } | |
af8cb5c5 | 2620 | else if (mode == SImode) |
2bfcf297 | 2621 | { |
af8cb5c5 DE |
2622 | result = no_new_pseudos ? dest : gen_reg_rtx (SImode); |
2623 | ||
2624 | emit_insn (gen_rtx_SET (VOIDmode, result, | |
2625 | GEN_INT (INTVAL (source) | |
2626 | & (~ (HOST_WIDE_INT) 0xffff)))); | |
2627 | emit_insn (gen_rtx_SET (VOIDmode, dest, | |
2628 | gen_rtx_IOR (SImode, result, | |
2629 | GEN_INT (INTVAL (source) & 0xffff)))); | |
2630 | result = dest; | |
2bfcf297 | 2631 | } |
af8cb5c5 | 2632 | else if (mode == DImode) |
2bfcf297 | 2633 | { |
af8cb5c5 DE |
2634 | if (GET_CODE (source) == CONST_INT) |
2635 | { | |
2636 | c0 = INTVAL (source); | |
2637 | c1 = -(c0 < 0); | |
2638 | } | |
2639 | else if (GET_CODE (source) == CONST_DOUBLE) | |
2640 | { | |
2bfcf297 | 2641 | #if HOST_BITS_PER_WIDE_INT >= 64 |
af8cb5c5 DE |
2642 | c0 = CONST_DOUBLE_LOW (source); |
2643 | c1 = -(c0 < 0); | |
2bfcf297 | 2644 | #else |
af8cb5c5 DE |
2645 | c0 = CONST_DOUBLE_LOW (source); |
2646 | c1 = CONST_DOUBLE_HIGH (source); | |
2bfcf297 | 2647 | #endif |
af8cb5c5 DE |
2648 | } |
2649 | else | |
2650 | abort (); | |
2651 | ||
2652 | result = rs6000_emit_set_long_const (dest, c0, c1); | |
2bfcf297 DB |
2653 | } |
2654 | else | |
a4f6c312 | 2655 | abort (); |
2bfcf297 | 2656 | |
af8cb5c5 DE |
2657 | insn = get_last_insn (); |
2658 | set = single_set (insn); | |
2659 | if (! CONSTANT_P (SET_SRC (set))) | |
2660 | set_unique_reg_note (insn, REG_EQUAL, source); | |
2661 | ||
2662 | return result; | |
2bfcf297 DB |
2663 | } |
2664 | ||
2665 | /* Having failed to find a 3 insn sequence in rs6000_emit_set_const, | |
2666 | fall back to a straight forward decomposition. We do this to avoid | |
2667 | exponential run times encountered when looking for longer sequences | |
2668 | with rs6000_emit_set_const. */ | |
2669 | static rtx | |
2670 | rs6000_emit_set_long_const (dest, c1, c2) | |
2671 | rtx dest; | |
2672 | HOST_WIDE_INT c1, c2; | |
2673 | { | |
2674 | if (!TARGET_POWERPC64) | |
2675 | { | |
2676 | rtx operand1, operand2; | |
2677 | ||
2678 | operand1 = operand_subword_force (dest, WORDS_BIG_ENDIAN == 0, | |
2679 | DImode); | |
2680 | operand2 = operand_subword_force (dest, WORDS_BIG_ENDIAN != 0, | |
2681 | DImode); | |
2682 | emit_move_insn (operand1, GEN_INT (c1)); | |
2683 | emit_move_insn (operand2, GEN_INT (c2)); | |
2684 | } | |
2685 | else | |
2686 | { | |
bc06712d | 2687 | HOST_WIDE_INT ud1, ud2, ud3, ud4; |
252b88f7 | 2688 | |
bc06712d TR |
2689 | ud1 = c1 & 0xffff; |
2690 | ud2 = (c1 & 0xffff0000) >> 16; | |
2bfcf297 | 2691 | #if HOST_BITS_PER_WIDE_INT >= 64 |
bc06712d | 2692 | c2 = c1 >> 32; |
2bfcf297 | 2693 | #endif |
bc06712d TR |
2694 | ud3 = c2 & 0xffff; |
2695 | ud4 = (c2 & 0xffff0000) >> 16; | |
2bfcf297 | 2696 | |
bc06712d TR |
2697 | if ((ud4 == 0xffff && ud3 == 0xffff && ud2 == 0xffff && (ud1 & 0x8000)) |
2698 | || (ud4 == 0 && ud3 == 0 && ud2 == 0 && ! (ud1 & 0x8000))) | |
2bfcf297 | 2699 | { |
bc06712d TR |
2700 | if (ud1 & 0x8000) |
2701 | emit_move_insn (dest, GEN_INT (((ud1 ^ 0x8000) - 0x8000))); | |
2702 | else | |
2703 | emit_move_insn (dest, GEN_INT (ud1)); | |
2bfcf297 | 2704 | } |
2bfcf297 | 2705 | |
bc06712d TR |
2706 | else if ((ud4 == 0xffff && ud3 == 0xffff && (ud2 & 0x8000)) |
2707 | || (ud4 == 0 && ud3 == 0 && ! (ud2 & 0x8000))) | |
252b88f7 | 2708 | { |
bc06712d TR |
2709 | if (ud2 & 0x8000) |
2710 | emit_move_insn (dest, GEN_INT (((ud2 << 16) ^ 0x80000000) | |
2711 | - 0x80000000)); | |
252b88f7 | 2712 | else |
bc06712d TR |
2713 | emit_move_insn (dest, GEN_INT (ud2 << 16)); |
2714 | if (ud1 != 0) | |
2715 | emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud1))); | |
252b88f7 | 2716 | } |
bc06712d TR |
2717 | else if ((ud4 == 0xffff && (ud3 & 0x8000)) |
2718 | || (ud4 == 0 && ! (ud3 & 0x8000))) | |
2719 | { | |
2720 | if (ud3 & 0x8000) | |
2721 | emit_move_insn (dest, GEN_INT (((ud3 << 16) ^ 0x80000000) | |
2722 | - 0x80000000)); | |
2723 | else | |
2724 | emit_move_insn (dest, GEN_INT (ud3 << 16)); | |
2725 | ||
2726 | if (ud2 != 0) | |
2727 | emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud2))); | |
2728 | emit_move_insn (dest, gen_rtx_ASHIFT (DImode, dest, GEN_INT (16))); | |
2729 | if (ud1 != 0) | |
2730 | emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud1))); | |
2731 | } | |
2732 | else | |
2733 | { | |
2734 | if (ud4 & 0x8000) | |
2735 | emit_move_insn (dest, GEN_INT (((ud4 << 16) ^ 0x80000000) | |
2736 | - 0x80000000)); | |
2737 | else | |
2738 | emit_move_insn (dest, GEN_INT (ud4 << 16)); | |
2739 | ||
2740 | if (ud3 != 0) | |
2741 | emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud3))); | |
2bfcf297 | 2742 | |
bc06712d TR |
2743 | emit_move_insn (dest, gen_rtx_ASHIFT (DImode, dest, GEN_INT (32))); |
2744 | if (ud2 != 0) | |
2745 | emit_move_insn (dest, gen_rtx_IOR (DImode, dest, | |
2746 | GEN_INT (ud2 << 16))); | |
2747 | if (ud1 != 0) | |
2748 | emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud1))); | |
2749 | } | |
2750 | } | |
2bfcf297 DB |
2751 | return dest; |
2752 | } | |
2753 | ||
fb4d4348 GK |
2754 | /* Emit a move from SOURCE to DEST in mode MODE. */ |
2755 | void | |
2756 | rs6000_emit_move (dest, source, mode) | |
2757 | rtx dest; | |
2758 | rtx source; | |
2759 | enum machine_mode mode; | |
2760 | { | |
2761 | rtx operands[2]; | |
2762 | operands[0] = dest; | |
2763 | operands[1] = source; | |
2764 | ||
2765 | /* Sanity checks. Check that we get CONST_DOUBLE only when we should. */ | |
2766 | if (GET_CODE (operands[1]) == CONST_DOUBLE | |
2767 | && ! FLOAT_MODE_P (mode) | |
2768 | && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT) | |
2769 | { | |
2770 | /* FIXME. This should never happen. */ | |
2771 | /* Since it seems that it does, do the safe thing and convert | |
2772 | to a CONST_INT. */ | |
2496c7bd | 2773 | operands[1] = gen_int_mode (CONST_DOUBLE_LOW (operands[1]), mode); |
fb4d4348 GK |
2774 | } |
2775 | if (GET_CODE (operands[1]) == CONST_DOUBLE | |
2776 | && ! FLOAT_MODE_P (mode) | |
2777 | && ((CONST_DOUBLE_HIGH (operands[1]) == 0 | |
2778 | && CONST_DOUBLE_LOW (operands[1]) >= 0) | |
2779 | || (CONST_DOUBLE_HIGH (operands[1]) == -1 | |
2780 | && CONST_DOUBLE_LOW (operands[1]) < 0))) | |
2781 | abort (); | |
c9e8cb32 DD |
2782 | |
2783 | /* Check if GCC is setting up a block move that will end up using FP | |
2784 | registers as temporaries. We must make sure this is acceptable. */ | |
2785 | if (GET_CODE (operands[0]) == MEM | |
2786 | && GET_CODE (operands[1]) == MEM | |
2787 | && mode == DImode | |
41543739 GK |
2788 | && (SLOW_UNALIGNED_ACCESS (DImode, MEM_ALIGN (operands[0])) |
2789 | || SLOW_UNALIGNED_ACCESS (DImode, MEM_ALIGN (operands[1]))) | |
2790 | && ! (SLOW_UNALIGNED_ACCESS (SImode, (MEM_ALIGN (operands[0]) > 32 | |
2791 | ? 32 : MEM_ALIGN (operands[0]))) | |
2792 | || SLOW_UNALIGNED_ACCESS (SImode, (MEM_ALIGN (operands[1]) > 32 | |
2793 | ? 32 | |
2794 | : MEM_ALIGN (operands[1])))) | |
2795 | && ! MEM_VOLATILE_P (operands [0]) | |
2796 | && ! MEM_VOLATILE_P (operands [1])) | |
c9e8cb32 | 2797 | { |
41543739 GK |
2798 | emit_move_insn (adjust_address (operands[0], SImode, 0), |
2799 | adjust_address (operands[1], SImode, 0)); | |
2800 | emit_move_insn (adjust_address (operands[0], SImode, 4), | |
2801 | adjust_address (operands[1], SImode, 4)); | |
c9e8cb32 DD |
2802 | return; |
2803 | } | |
fb4d4348 | 2804 | |
67cef334 DE |
2805 | if (!no_new_pseudos) |
2806 | { | |
2807 | if (GET_CODE (operands[1]) == MEM && optimize > 0 | |
2808 | && (mode == QImode || mode == HImode || mode == SImode) | |
2809 | && GET_MODE_SIZE (mode) < GET_MODE_SIZE (word_mode)) | |
2810 | { | |
2811 | rtx reg = gen_reg_rtx (word_mode); | |
2812 | ||
2813 | emit_insn (gen_rtx_SET (word_mode, reg, | |
2814 | gen_rtx_ZERO_EXTEND (word_mode, | |
2815 | operands[1]))); | |
2816 | operands[1] = gen_lowpart (mode, reg); | |
2817 | } | |
2818 | if (GET_CODE (operands[0]) != REG) | |
2819 | operands[1] = force_reg (mode, operands[1]); | |
2820 | } | |
a9098fd0 | 2821 | |
a3170dc6 AH |
2822 | if (mode == SFmode && ! TARGET_POWERPC |
2823 | && TARGET_HARD_FLOAT && TARGET_FPRS | |
ffc14f31 | 2824 | && GET_CODE (operands[0]) == MEM) |
fb4d4348 | 2825 | { |
ffc14f31 GK |
2826 | int regnum; |
2827 | ||
2828 | if (reload_in_progress || reload_completed) | |
2829 | regnum = true_regnum (operands[1]); | |
2830 | else if (GET_CODE (operands[1]) == REG) | |
2831 | regnum = REGNO (operands[1]); | |
2832 | else | |
2833 | regnum = -1; | |
fb4d4348 GK |
2834 | |
2835 | /* If operands[1] is a register, on POWER it may have | |
2836 | double-precision data in it, so truncate it to single | |
2837 | precision. */ | |
2838 | if (FP_REGNO_P (regnum) || regnum >= FIRST_PSEUDO_REGISTER) | |
2839 | { | |
2840 | rtx newreg; | |
2841 | newreg = (no_new_pseudos ? operands[1] : gen_reg_rtx (mode)); | |
2842 | emit_insn (gen_aux_truncdfsf2 (newreg, operands[1])); | |
2843 | operands[1] = newreg; | |
2844 | } | |
2845 | } | |
2846 | ||
a9098fd0 GK |
2847 | /* Handle the case where reload calls us with an invalid address; |
2848 | and the case of CONSTANT_P_RTX. */ | |
16861f33 | 2849 | if (!ALTIVEC_VECTOR_MODE (mode) |
69ef87e2 AH |
2850 | && (! general_operand (operands[1], mode) |
2851 | || ! nonimmediate_operand (operands[0], mode) | |
2852 | || GET_CODE (operands[1]) == CONSTANT_P_RTX)) | |
fb4d4348 GK |
2853 | { |
2854 | emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1])); | |
2855 | return; | |
2856 | } | |
a9098fd0 | 2857 | |
fb4d4348 GK |
2858 | /* FIXME: In the long term, this switch statement should go away |
2859 | and be replaced by a sequence of tests based on things like | |
2860 | mode == Pmode. */ | |
2861 | switch (mode) | |
2862 | { | |
2863 | case HImode: | |
2864 | case QImode: | |
2865 | if (CONSTANT_P (operands[1]) | |
2866 | && GET_CODE (operands[1]) != CONST_INT) | |
a9098fd0 | 2867 | operands[1] = force_const_mem (mode, operands[1]); |
fb4d4348 GK |
2868 | break; |
2869 | ||
06f4e019 | 2870 | case TFmode: |
fb4d4348 GK |
2871 | case DFmode: |
2872 | case SFmode: | |
2873 | if (CONSTANT_P (operands[1]) | |
2874 | && ! easy_fp_constant (operands[1], mode)) | |
a9098fd0 | 2875 | operands[1] = force_const_mem (mode, operands[1]); |
fb4d4348 GK |
2876 | break; |
2877 | ||
0ac081f6 AH |
2878 | case V16QImode: |
2879 | case V8HImode: | |
2880 | case V4SFmode: | |
2881 | case V4SImode: | |
a3170dc6 AH |
2882 | case V4HImode: |
2883 | case V2SFmode: | |
2884 | case V2SImode: | |
00a892b8 | 2885 | case V1DImode: |
69ef87e2 | 2886 | if (CONSTANT_P (operands[1]) |
d744e06e | 2887 | && !easy_vector_constant (operands[1], mode)) |
0ac081f6 AH |
2888 | operands[1] = force_const_mem (mode, operands[1]); |
2889 | break; | |
2890 | ||
fb4d4348 | 2891 | case SImode: |
a9098fd0 | 2892 | case DImode: |
fb4d4348 GK |
2893 | /* Use default pattern for address of ELF small data */ |
2894 | if (TARGET_ELF | |
a9098fd0 | 2895 | && mode == Pmode |
f607bc57 | 2896 | && DEFAULT_ABI == ABI_V4 |
a9098fd0 GK |
2897 | && (GET_CODE (operands[1]) == SYMBOL_REF |
2898 | || GET_CODE (operands[1]) == CONST) | |
2899 | && small_data_operand (operands[1], mode)) | |
fb4d4348 GK |
2900 | { |
2901 | emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1])); | |
2902 | return; | |
2903 | } | |
2904 | ||
f607bc57 | 2905 | if (DEFAULT_ABI == ABI_V4 |
a9098fd0 GK |
2906 | && mode == Pmode && mode == SImode |
2907 | && flag_pic == 1 && got_operand (operands[1], mode)) | |
fb4d4348 GK |
2908 | { |
2909 | emit_insn (gen_movsi_got (operands[0], operands[1])); | |
2910 | return; | |
2911 | } | |
2912 | ||
ee890fe2 | 2913 | if ((TARGET_ELF || DEFAULT_ABI == ABI_DARWIN) |
f1384257 AM |
2914 | && TARGET_NO_TOC |
2915 | && ! flag_pic | |
a9098fd0 | 2916 | && mode == Pmode |
fb4d4348 GK |
2917 | && CONSTANT_P (operands[1]) |
2918 | && GET_CODE (operands[1]) != HIGH | |
2919 | && GET_CODE (operands[1]) != CONST_INT) | |
2920 | { | |
a9098fd0 | 2921 | rtx target = (no_new_pseudos ? operands[0] : gen_reg_rtx (mode)); |
fb4d4348 GK |
2922 | |
2923 | /* If this is a function address on -mcall-aixdesc, | |
2924 | convert it to the address of the descriptor. */ | |
2925 | if (DEFAULT_ABI == ABI_AIX | |
2926 | && GET_CODE (operands[1]) == SYMBOL_REF | |
2927 | && XSTR (operands[1], 0)[0] == '.') | |
2928 | { | |
2929 | const char *name = XSTR (operands[1], 0); | |
2930 | rtx new_ref; | |
2931 | while (*name == '.') | |
2932 | name++; | |
2933 | new_ref = gen_rtx_SYMBOL_REF (Pmode, name); | |
2934 | CONSTANT_POOL_ADDRESS_P (new_ref) | |
2935 | = CONSTANT_POOL_ADDRESS_P (operands[1]); | |
2936 | SYMBOL_REF_FLAG (new_ref) = SYMBOL_REF_FLAG (operands[1]); | |
2937 | SYMBOL_REF_USED (new_ref) = SYMBOL_REF_USED (operands[1]); | |
2938 | operands[1] = new_ref; | |
2939 | } | |
7509c759 | 2940 | |
ee890fe2 SS |
2941 | if (DEFAULT_ABI == ABI_DARWIN) |
2942 | { | |
ab82a49f AP |
2943 | #if TARGET_MACHO |
2944 | if (MACHO_DYNAMIC_NO_PIC_P) | |
2945 | { | |
2946 | /* Take care of any required data indirection. */ | |
2947 | operands[1] = rs6000_machopic_legitimize_pic_address ( | |
2948 | operands[1], mode, operands[0]); | |
2949 | if (operands[0] != operands[1]) | |
2950 | emit_insn (gen_rtx_SET (VOIDmode, | |
2951 | operands[0], operands[1])); | |
2952 | return; | |
2953 | } | |
2954 | #endif | |
ee890fe2 SS |
2955 | emit_insn (gen_macho_high (target, operands[1])); |
2956 | emit_insn (gen_macho_low (operands[0], target, operands[1])); | |
2957 | return; | |
2958 | } | |
2959 | ||
fb4d4348 GK |
2960 | emit_insn (gen_elf_high (target, operands[1])); |
2961 | emit_insn (gen_elf_low (operands[0], target, operands[1])); | |
2962 | return; | |
2963 | } | |
2964 | ||
a9098fd0 GK |
2965 | /* If this is a SYMBOL_REF that refers to a constant pool entry, |
2966 | and we have put it in the TOC, we just need to make a TOC-relative | |
2967 | reference to it. */ | |
2968 | if (TARGET_TOC | |
2969 | && GET_CODE (operands[1]) == SYMBOL_REF | |
2970 | && CONSTANT_POOL_EXPR_P (operands[1]) | |
2971 | && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (operands[1]), | |
2972 | get_pool_mode (operands[1]))) | |
fb4d4348 | 2973 | { |
a9098fd0 | 2974 | operands[1] = create_TOC_reference (operands[1]); |
fb4d4348 | 2975 | } |
a9098fd0 GK |
2976 | else if (mode == Pmode |
2977 | && CONSTANT_P (operands[1]) | |
38886f37 AO |
2978 | && ((GET_CODE (operands[1]) != CONST_INT |
2979 | && ! easy_fp_constant (operands[1], mode)) | |
2980 | || (GET_CODE (operands[1]) == CONST_INT | |
2981 | && num_insns_constant (operands[1], mode) > 2) | |
2982 | || (GET_CODE (operands[0]) == REG | |
2983 | && FP_REGNO_P (REGNO (operands[0])))) | |
a9098fd0 GK |
2984 | && GET_CODE (operands[1]) != HIGH |
2985 | && ! LEGITIMATE_CONSTANT_POOL_ADDRESS_P (operands[1]) | |
2986 | && ! TOC_RELATIVE_EXPR_P (operands[1])) | |
fb4d4348 GK |
2987 | { |
2988 | /* Emit a USE operation so that the constant isn't deleted if | |
2989 | expensive optimizations are turned on because nobody | |
2990 | references it. This should only be done for operands that | |
2991 | contain SYMBOL_REFs with CONSTANT_POOL_ADDRESS_P set. | |
2992 | This should not be done for operands that contain LABEL_REFs. | |
2993 | For now, we just handle the obvious case. */ | |
2994 | if (GET_CODE (operands[1]) != LABEL_REF) | |
2995 | emit_insn (gen_rtx_USE (VOIDmode, operands[1])); | |
2996 | ||
c859cda6 | 2997 | #if TARGET_MACHO |
ee890fe2 | 2998 | /* Darwin uses a special PIC legitimizer. */ |
ab82a49f | 2999 | if (DEFAULT_ABI == ABI_DARWIN && MACHOPIC_INDIRECT) |
ee890fe2 | 3000 | { |
ee890fe2 SS |
3001 | operands[1] = |
3002 | rs6000_machopic_legitimize_pic_address (operands[1], mode, | |
c859cda6 DJ |
3003 | operands[0]); |
3004 | if (operands[0] != operands[1]) | |
3005 | emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1])); | |
ee890fe2 SS |
3006 | return; |
3007 | } | |
c859cda6 | 3008 | #endif |
ee890fe2 | 3009 | |
fb4d4348 GK |
3010 | /* If we are to limit the number of things we put in the TOC and |
3011 | this is a symbol plus a constant we can add in one insn, | |
3012 | just put the symbol in the TOC and add the constant. Don't do | |
3013 | this if reload is in progress. */ | |
3014 | if (GET_CODE (operands[1]) == CONST | |
3015 | && TARGET_NO_SUM_IN_TOC && ! reload_in_progress | |
3016 | && GET_CODE (XEXP (operands[1], 0)) == PLUS | |
a9098fd0 | 3017 | && add_operand (XEXP (XEXP (operands[1], 0), 1), mode) |
fb4d4348 GK |
3018 | && (GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == LABEL_REF |
3019 | || GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == SYMBOL_REF) | |
3020 | && ! side_effects_p (operands[0])) | |
3021 | { | |
a4f6c312 SS |
3022 | rtx sym = |
3023 | force_const_mem (mode, XEXP (XEXP (operands[1], 0), 0)); | |
fb4d4348 GK |
3024 | rtx other = XEXP (XEXP (operands[1], 0), 1); |
3025 | ||
a9098fd0 GK |
3026 | sym = force_reg (mode, sym); |
3027 | if (mode == SImode) | |
3028 | emit_insn (gen_addsi3 (operands[0], sym, other)); | |
3029 | else | |
3030 | emit_insn (gen_adddi3 (operands[0], sym, other)); | |
fb4d4348 GK |
3031 | return; |
3032 | } | |
3033 | ||
a9098fd0 | 3034 | operands[1] = force_const_mem (mode, operands[1]); |
fb4d4348 GK |
3035 | |
3036 | if (TARGET_TOC | |
d34c5b80 DE |
3037 | && CONSTANT_POOL_EXPR_P (XEXP (operands[1], 0)) |
3038 | && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P ( | |
3039 | get_pool_constant (XEXP (operands[1], 0)), | |
3040 | get_pool_mode (XEXP (operands[1], 0)))) | |
a9098fd0 | 3041 | { |
ba4828e0 RK |
3042 | operands[1] |
3043 | = gen_rtx_MEM (mode, | |
3044 | create_TOC_reference (XEXP (operands[1], 0))); | |
3045 | set_mem_alias_set (operands[1], get_TOC_alias_set ()); | |
fb4d4348 | 3046 | RTX_UNCHANGING_P (operands[1]) = 1; |
a9098fd0 | 3047 | } |
fb4d4348 GK |
3048 | } |
3049 | break; | |
a9098fd0 | 3050 | |
fb4d4348 GK |
3051 | case TImode: |
3052 | if (GET_CODE (operands[0]) == MEM | |
3053 | && GET_CODE (XEXP (operands[0], 0)) != REG | |
3054 | && ! reload_in_progress) | |
792760b9 RK |
3055 | operands[0] |
3056 | = replace_equiv_address (operands[0], | |
3057 | copy_addr_to_reg (XEXP (operands[0], 0))); | |
fb4d4348 GK |
3058 | |
3059 | if (GET_CODE (operands[1]) == MEM | |
3060 | && GET_CODE (XEXP (operands[1], 0)) != REG | |
3061 | && ! reload_in_progress) | |
792760b9 RK |
3062 | operands[1] |
3063 | = replace_equiv_address (operands[1], | |
3064 | copy_addr_to_reg (XEXP (operands[1], 0))); | |
27dc0551 DE |
3065 | if (TARGET_POWER) |
3066 | { | |
3067 | emit_insn (gen_rtx_PARALLEL (VOIDmode, | |
3068 | gen_rtvec (2, | |
3069 | gen_rtx_SET (VOIDmode, | |
3070 | operands[0], operands[1]), | |
3071 | gen_rtx_CLOBBER (VOIDmode, | |
3072 | gen_rtx_SCRATCH (SImode))))); | |
3073 | return; | |
3074 | } | |
fb4d4348 GK |
3075 | break; |
3076 | ||
3077 | default: | |
3078 | abort (); | |
3079 | } | |
3080 | ||
a9098fd0 GK |
3081 | /* Above, we may have called force_const_mem which may have returned |
3082 | an invalid address. If we can, fix this up; otherwise, reload will | |
3083 | have to deal with it. */ | |
3084 | if (GET_CODE (operands[1]) == MEM | |
3085 | && ! memory_address_p (mode, XEXP (operands[1], 0)) | |
3086 | && ! reload_in_progress) | |
f4ef873c | 3087 | operands[1] = adjust_address (operands[1], mode, 0); |
a9098fd0 | 3088 | |
fb4d4348 | 3089 | emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1])); |
02a4ec28 | 3090 | return; |
fb4d4348 | 3091 | } |
4697a36c MM |
3092 | \f |
3093 | /* Initialize a variable CUM of type CUMULATIVE_ARGS | |
3094 | for a call to a function whose data type is FNTYPE. | |
3095 | For a library call, FNTYPE is 0. | |
3096 | ||
3097 | For incoming args we set the number of arguments in the prototype large | |
1c20ae99 | 3098 | so we never return a PARALLEL. */ |
4697a36c MM |
3099 | |
3100 | void | |
3101 | init_cumulative_args (cum, fntype, libname, incoming) | |
3102 | CUMULATIVE_ARGS *cum; | |
3103 | tree fntype; | |
296b8152 | 3104 | rtx libname ATTRIBUTE_UNUSED; |
4697a36c MM |
3105 | int incoming; |
3106 | { | |
3107 | static CUMULATIVE_ARGS zero_cumulative; | |
3108 | ||
3109 | *cum = zero_cumulative; | |
3110 | cum->words = 0; | |
3111 | cum->fregno = FP_ARG_MIN_REG; | |
0ac081f6 | 3112 | cum->vregno = ALTIVEC_ARG_MIN_REG; |
4697a36c | 3113 | cum->prototype = (fntype && TYPE_ARG_TYPES (fntype)); |
7509c759 | 3114 | cum->call_cookie = CALL_NORMAL; |
4cc833b7 | 3115 | cum->sysv_gregno = GP_ARG_MIN_REG; |
4697a36c MM |
3116 | |
3117 | if (incoming) | |
bd227acc | 3118 | cum->nargs_prototype = 1000; /* don't return a PARALLEL */ |
4697a36c MM |
3119 | |
3120 | else if (cum->prototype) | |
3121 | cum->nargs_prototype = (list_length (TYPE_ARG_TYPES (fntype)) - 1 | |
3122 | + (TYPE_MODE (TREE_TYPE (fntype)) == BLKmode | |
3123 | || RETURN_IN_MEMORY (TREE_TYPE (fntype)))); | |
3124 | ||
3125 | else | |
3126 | cum->nargs_prototype = 0; | |
3127 | ||
3128 | cum->orig_nargs = cum->nargs_prototype; | |
7509c759 | 3129 | |
a5c76ee6 ZW |
3130 | /* Check for a longcall attribute. */ |
3131 | if (fntype | |
3132 | && lookup_attribute ("longcall", TYPE_ATTRIBUTES (fntype)) | |
3133 | && !lookup_attribute ("shortcall", TYPE_ATTRIBUTES (fntype))) | |
6a4cee5f MM |
3134 | cum->call_cookie = CALL_LONG; |
3135 | ||
4697a36c MM |
3136 | if (TARGET_DEBUG_ARG) |
3137 | { | |
3138 | fprintf (stderr, "\ninit_cumulative_args:"); | |
3139 | if (fntype) | |
3140 | { | |
3141 | tree ret_type = TREE_TYPE (fntype); | |
3142 | fprintf (stderr, " ret code = %s,", | |
3143 | tree_code_name[ (int)TREE_CODE (ret_type) ]); | |
3144 | } | |
3145 | ||
6a4cee5f MM |
3146 | if (cum->call_cookie & CALL_LONG) |
3147 | fprintf (stderr, " longcall,"); | |
3148 | ||
4697a36c MM |
3149 | fprintf (stderr, " proto = %d, nargs = %d\n", |
3150 | cum->prototype, cum->nargs_prototype); | |
3151 | } | |
3152 | } | |
3153 | \f | |
c229cba9 DE |
3154 | /* If defined, a C expression which determines whether, and in which |
3155 | direction, to pad out an argument with extra space. The value | |
3156 | should be of type `enum direction': either `upward' to pad above | |
3157 | the argument, `downward' to pad below, or `none' to inhibit | |
3158 | padding. | |
3159 | ||
3160 | For the AIX ABI structs are always stored left shifted in their | |
3161 | argument slot. */ | |
3162 | ||
9ebbca7d | 3163 | enum direction |
c229cba9 DE |
3164 | function_arg_padding (mode, type) |
3165 | enum machine_mode mode; | |
3166 | tree type; | |
3167 | { | |
c85f7c16 | 3168 | if (type != 0 && AGGREGATE_TYPE_P (type)) |
9ebbca7d | 3169 | return upward; |
c229cba9 DE |
3170 | |
3171 | /* This is the default definition. */ | |
3172 | return (! BYTES_BIG_ENDIAN | |
9ebbca7d | 3173 | ? upward |
c229cba9 DE |
3174 | : ((mode == BLKmode |
3175 | ? (type && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST | |
3176 | && int_size_in_bytes (type) < (PARM_BOUNDARY / BITS_PER_UNIT)) | |
3177 | : GET_MODE_BITSIZE (mode) < PARM_BOUNDARY) | |
9ebbca7d | 3178 | ? downward : upward)); |
c229cba9 DE |
3179 | } |
3180 | ||
b6c9286a MM |
3181 | /* If defined, a C expression that gives the alignment boundary, in bits, |
3182 | of an argument with the specified mode and type. If it is not defined, | |
3183 | PARM_BOUNDARY is used for all arguments. | |
3184 | ||
2310f99a | 3185 | V.4 wants long longs to be double word aligned. */ |
b6c9286a MM |
3186 | |
3187 | int | |
3188 | function_arg_boundary (mode, type) | |
3189 | enum machine_mode mode; | |
9ebbca7d | 3190 | tree type ATTRIBUTE_UNUSED; |
b6c9286a | 3191 | { |
f607bc57 | 3192 | if (DEFAULT_ABI == ABI_V4 && (mode == DImode || mode == DFmode)) |
e1f83b4d | 3193 | return 64; |
a3170dc6 AH |
3194 | else if (SPE_VECTOR_MODE (mode)) |
3195 | return 64; | |
0ac081f6 AH |
3196 | else if (TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode)) |
3197 | return 128; | |
9ebbca7d | 3198 | else |
b6c9286a | 3199 | return PARM_BOUNDARY; |
b6c9286a MM |
3200 | } |
3201 | \f | |
4697a36c MM |
3202 | /* Update the data in CUM to advance over an argument |
3203 | of mode MODE and data type TYPE. | |
3204 | (TYPE is null for libcalls where that information may not be available.) */ | |
3205 | ||
3206 | void | |
3207 | function_arg_advance (cum, mode, type, named) | |
3208 | CUMULATIVE_ARGS *cum; | |
3209 | enum machine_mode mode; | |
3210 | tree type; | |
3211 | int named; | |
3212 | { | |
3213 | cum->nargs_prototype--; | |
3214 | ||
0ac081f6 AH |
3215 | if (TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode)) |
3216 | { | |
3217 | if (cum->vregno <= ALTIVEC_ARG_MAX_REG && cum->nargs_prototype >= 0) | |
3218 | cum->vregno++; | |
3219 | else | |
3220 | cum->words += RS6000_ARG_SIZE (mode, type); | |
3221 | } | |
a4b0320c AH |
3222 | else if (TARGET_SPE_ABI && TARGET_SPE && SPE_VECTOR_MODE (mode) |
3223 | && named && cum->sysv_gregno <= GP_ARG_MAX_REG) | |
3224 | cum->sysv_gregno++; | |
f607bc57 | 3225 | else if (DEFAULT_ABI == ABI_V4) |
4697a36c | 3226 | { |
a3170dc6 | 3227 | if (TARGET_HARD_FLOAT && TARGET_FPRS |
4cc833b7 | 3228 | && (mode == SFmode || mode == DFmode)) |
4697a36c | 3229 | { |
4cc833b7 RH |
3230 | if (cum->fregno <= FP_ARG_V4_MAX_REG) |
3231 | cum->fregno++; | |
3232 | else | |
3233 | { | |
3234 | if (mode == DFmode) | |
3235 | cum->words += cum->words & 1; | |
d34c5b80 | 3236 | cum->words += RS6000_ARG_SIZE (mode, type); |
4cc833b7 | 3237 | } |
4697a36c | 3238 | } |
4cc833b7 RH |
3239 | else |
3240 | { | |
3241 | int n_words; | |
3242 | int gregno = cum->sysv_gregno; | |
3243 | ||
3244 | /* Aggregates and IEEE quad get passed by reference. */ | |
3245 | if ((type && AGGREGATE_TYPE_P (type)) | |
3246 | || mode == TFmode) | |
3247 | n_words = 1; | |
3248 | else | |
d34c5b80 | 3249 | n_words = RS6000_ARG_SIZE (mode, type); |
4cc833b7 | 3250 | |
a4b0320c | 3251 | /* Long long and SPE vectors are put in odd registers. */ |
4cc833b7 RH |
3252 | if (n_words == 2 && (gregno & 1) == 0) |
3253 | gregno += 1; | |
3254 | ||
a4b0320c AH |
3255 | /* Long long and SPE vectors are not split between registers |
3256 | and stack. */ | |
4cc833b7 RH |
3257 | if (gregno + n_words - 1 > GP_ARG_MAX_REG) |
3258 | { | |
3259 | /* Long long is aligned on the stack. */ | |
3260 | if (n_words == 2) | |
3261 | cum->words += cum->words & 1; | |
3262 | cum->words += n_words; | |
3263 | } | |
4697a36c | 3264 | |
4cc833b7 RH |
3265 | /* Note: continuing to accumulate gregno past when we've started |
3266 | spilling to the stack indicates the fact that we've started | |
3267 | spilling to the stack to expand_builtin_saveregs. */ | |
3268 | cum->sysv_gregno = gregno + n_words; | |
3269 | } | |
4697a36c | 3270 | |
4cc833b7 RH |
3271 | if (TARGET_DEBUG_ARG) |
3272 | { | |
3273 | fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ", | |
3274 | cum->words, cum->fregno); | |
3275 | fprintf (stderr, "gregno = %2d, nargs = %4d, proto = %d, ", | |
3276 | cum->sysv_gregno, cum->nargs_prototype, cum->prototype); | |
3277 | fprintf (stderr, "mode = %4s, named = %d\n", | |
3278 | GET_MODE_NAME (mode), named); | |
3279 | } | |
4697a36c MM |
3280 | } |
3281 | else | |
4cc833b7 RH |
3282 | { |
3283 | int align = (TARGET_32BIT && (cum->words & 1) != 0 | |
3284 | && function_arg_boundary (mode, type) == 64) ? 1 : 0; | |
a4f6c312 | 3285 | |
d34c5b80 | 3286 | cum->words += align + RS6000_ARG_SIZE (mode, type); |
4697a36c | 3287 | |
a3170dc6 AH |
3288 | if (GET_MODE_CLASS (mode) == MODE_FLOAT |
3289 | && TARGET_HARD_FLOAT && TARGET_FPRS) | |
fcce224d | 3290 | cum->fregno += (mode == TFmode ? 2 : 1); |
4cc833b7 RH |
3291 | |
3292 | if (TARGET_DEBUG_ARG) | |
3293 | { | |
3294 | fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ", | |
3295 | cum->words, cum->fregno); | |
3296 | fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s, ", | |
3297 | cum->nargs_prototype, cum->prototype, GET_MODE_NAME (mode)); | |
3298 | fprintf (stderr, "named = %d, align = %d\n", named, align); | |
3299 | } | |
3300 | } | |
4697a36c MM |
3301 | } |
3302 | \f | |
3303 | /* Determine where to put an argument to a function. | |
3304 | Value is zero to push the argument on the stack, | |
3305 | or a hard register in which to store the argument. | |
3306 | ||
3307 | MODE is the argument's machine mode. | |
3308 | TYPE is the data type of the argument (as a tree). | |
3309 | This is null for libcalls where that information may | |
3310 | not be available. | |
3311 | CUM is a variable of type CUMULATIVE_ARGS which gives info about | |
3312 | the preceding args and about the function being called. | |
3313 | NAMED is nonzero if this argument is a named parameter | |
3314 | (otherwise it is an extra parameter matching an ellipsis). | |
3315 | ||
3316 | On RS/6000 the first eight words of non-FP are normally in registers | |
3317 | and the rest are pushed. Under AIX, the first 13 FP args are in registers. | |
3318 | Under V.4, the first 8 FP args are in registers. | |
3319 | ||
3320 | If this is floating-point and no prototype is specified, we use | |
3321 | both an FP and integer register (or possibly FP reg and stack). Library | |
3322 | functions (when TYPE is zero) always have the proper types for args, | |
3323 | so we can pass the FP value just in one register. emit_library_function | |
1c20ae99 | 3324 | doesn't support PARALLEL anyway. */ |
4697a36c MM |
3325 | |
3326 | struct rtx_def * | |
3327 | function_arg (cum, mode, type, named) | |
3328 | CUMULATIVE_ARGS *cum; | |
3329 | enum machine_mode mode; | |
3330 | tree type; | |
20c29ebe | 3331 | int named; |
4697a36c | 3332 | { |
4cc833b7 | 3333 | enum rs6000_abi abi = DEFAULT_ABI; |
4697a36c | 3334 | |
a4f6c312 SS |
3335 | /* Return a marker to indicate whether CR1 needs to set or clear the |
3336 | bit that V.4 uses to say fp args were passed in registers. | |
3337 | Assume that we don't need the marker for software floating point, | |
3338 | or compiler generated library calls. */ | |
4697a36c MM |
3339 | if (mode == VOIDmode) |
3340 | { | |
f607bc57 | 3341 | if (abi == ABI_V4 |
7509c759 | 3342 | && cum->nargs_prototype < 0 |
4697a36c | 3343 | && type && (cum->prototype || TARGET_NO_PROTOTYPE)) |
7509c759 | 3344 | { |
a3170dc6 AH |
3345 | /* For the SPE, we need to crxor CR6 always. */ |
3346 | if (TARGET_SPE_ABI) | |
3347 | return GEN_INT (cum->call_cookie | CALL_V4_SET_FP_ARGS); | |
3348 | else if (TARGET_HARD_FLOAT && TARGET_FPRS) | |
3349 | return GEN_INT (cum->call_cookie | |
3350 | | ((cum->fregno == FP_ARG_MIN_REG) | |
3351 | ? CALL_V4_SET_FP_ARGS | |
3352 | : CALL_V4_CLEAR_FP_ARGS)); | |
7509c759 | 3353 | } |
4697a36c | 3354 | |
7509c759 | 3355 | return GEN_INT (cum->call_cookie); |
4697a36c MM |
3356 | } |
3357 | ||
0ac081f6 AH |
3358 | if (TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode)) |
3359 | { | |
20c29ebe | 3360 | if (named && cum->vregno <= ALTIVEC_ARG_MAX_REG) |
0ac081f6 AH |
3361 | return gen_rtx_REG (mode, cum->vregno); |
3362 | else | |
3363 | return NULL; | |
3364 | } | |
a4b0320c | 3365 | else if (TARGET_SPE_ABI && TARGET_SPE && SPE_VECTOR_MODE (mode) && named) |
a3170dc6 | 3366 | { |
a4b0320c | 3367 | if (cum->sysv_gregno <= GP_ARG_MAX_REG) |
a3170dc6 AH |
3368 | return gen_rtx_REG (mode, cum->sysv_gregno); |
3369 | else | |
3370 | return NULL; | |
3371 | } | |
f607bc57 | 3372 | else if (abi == ABI_V4) |
4697a36c | 3373 | { |
a3170dc6 | 3374 | if (TARGET_HARD_FLOAT && TARGET_FPRS |
4cc833b7 RH |
3375 | && (mode == SFmode || mode == DFmode)) |
3376 | { | |
3377 | if (cum->fregno <= FP_ARG_V4_MAX_REG) | |
3378 | return gen_rtx_REG (mode, cum->fregno); | |
3379 | else | |
3380 | return NULL; | |
3381 | } | |
3382 | else | |
3383 | { | |
3384 | int n_words; | |
3385 | int gregno = cum->sysv_gregno; | |
3386 | ||
3387 | /* Aggregates and IEEE quad get passed by reference. */ | |
3388 | if ((type && AGGREGATE_TYPE_P (type)) | |
3389 | || mode == TFmode) | |
3390 | n_words = 1; | |
3391 | else | |
d34c5b80 | 3392 | n_words = RS6000_ARG_SIZE (mode, type); |
4cc833b7 | 3393 | |
a4b0320c | 3394 | /* Long long and SPE vectors are put in odd registers. */ |
4cc833b7 RH |
3395 | if (n_words == 2 && (gregno & 1) == 0) |
3396 | gregno += 1; | |
3397 | ||
a4b0320c AH |
3398 | /* Long long and SPE vectors are not split between registers |
3399 | and stack. */ | |
4cc833b7 | 3400 | if (gregno + n_words - 1 <= GP_ARG_MAX_REG) |
a4b0320c AH |
3401 | { |
3402 | /* SPE vectors in ... get split into 2 registers. */ | |
3403 | if (TARGET_SPE && TARGET_SPE_ABI | |
3404 | && SPE_VECTOR_MODE (mode) && !named) | |
3405 | { | |
3406 | rtx r1, r2; | |
57de2c8f | 3407 | enum machine_mode m = SImode; |
f9dd72da | 3408 | |
a4b0320c AH |
3409 | r1 = gen_rtx_REG (m, gregno); |
3410 | r1 = gen_rtx_EXPR_LIST (m, r1, const0_rtx); | |
3411 | r2 = gen_rtx_REG (m, gregno + 1); | |
3412 | r2 = gen_rtx_EXPR_LIST (m, r2, GEN_INT (4)); | |
3413 | return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r2)); | |
3414 | } | |
3415 | return gen_rtx_REG (mode, gregno); | |
3416 | } | |
4cc833b7 RH |
3417 | else |
3418 | return NULL; | |
3419 | } | |
4697a36c | 3420 | } |
4cc833b7 RH |
3421 | else |
3422 | { | |
3423 | int align = (TARGET_32BIT && (cum->words & 1) != 0 | |
3424 | && function_arg_boundary (mode, type) == 64) ? 1 : 0; | |
3425 | int align_words = cum->words + align; | |
4697a36c | 3426 | |
4cc833b7 RH |
3427 | if (type && TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST) |
3428 | return NULL_RTX; | |
3429 | ||
3430 | if (USE_FP_FOR_ARG_P (*cum, mode, type)) | |
3431 | { | |
3432 | if (! type | |
3433 | || ((cum->nargs_prototype > 0) | |
3434 | /* IBM AIX extended its linkage convention definition always | |
3435 | to require FP args after register save area hole on the | |
3436 | stack. */ | |
3437 | && (DEFAULT_ABI != ABI_AIX | |
3438 | || ! TARGET_XL_CALL | |
3439 | || (align_words < GP_ARG_NUM_REG)))) | |
3440 | return gen_rtx_REG (mode, cum->fregno); | |
3441 | ||
3442 | return gen_rtx_PARALLEL (mode, | |
3443 | gen_rtvec (2, | |
39403d82 | 3444 | gen_rtx_EXPR_LIST (VOIDmode, |
1c20ae99 JW |
3445 | ((align_words >= GP_ARG_NUM_REG) |
3446 | ? NULL_RTX | |
3447 | : (align_words | |
d34c5b80 | 3448 | + RS6000_ARG_SIZE (mode, type) |
1c20ae99 JW |
3449 | > GP_ARG_NUM_REG |
3450 | /* If this is partially on the stack, then | |
3451 | we only include the portion actually | |
3452 | in registers here. */ | |
39403d82 | 3453 | ? gen_rtx_REG (SImode, |
1c20ae99 | 3454 | GP_ARG_MIN_REG + align_words) |
39403d82 | 3455 | : gen_rtx_REG (mode, |
1c20ae99 JW |
3456 | GP_ARG_MIN_REG + align_words))), |
3457 | const0_rtx), | |
39403d82 DE |
3458 | gen_rtx_EXPR_LIST (VOIDmode, |
3459 | gen_rtx_REG (mode, cum->fregno), | |
1c20ae99 | 3460 | const0_rtx))); |
4cc833b7 RH |
3461 | } |
3462 | else if (align_words < GP_ARG_NUM_REG) | |
3463 | return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words); | |
3464 | else | |
3465 | return NULL_RTX; | |
4697a36c | 3466 | } |
4697a36c MM |
3467 | } |
3468 | \f | |
3469 | /* For an arg passed partly in registers and partly in memory, | |
3470 | this is the number of registers used. | |
3471 | For args passed entirely in registers or entirely in memory, zero. */ | |
3472 | ||
3473 | int | |
3474 | function_arg_partial_nregs (cum, mode, type, named) | |
3475 | CUMULATIVE_ARGS *cum; | |
3476 | enum machine_mode mode; | |
3477 | tree type; | |
d34c5b80 | 3478 | int named ATTRIBUTE_UNUSED; |
4697a36c | 3479 | { |
f607bc57 | 3480 | if (DEFAULT_ABI == ABI_V4) |
4697a36c | 3481 | return 0; |
4697a36c | 3482 | |
0ac081f6 AH |
3483 | if (USE_FP_FOR_ARG_P (*cum, mode, type) |
3484 | || USE_ALTIVEC_FOR_ARG_P (*cum, mode, type)) | |
4697a36c MM |
3485 | { |
3486 | if (cum->nargs_prototype >= 0) | |
3487 | return 0; | |
3488 | } | |
3489 | ||
3490 | if (cum->words < GP_ARG_NUM_REG | |
d34c5b80 | 3491 | && GP_ARG_NUM_REG < (cum->words + RS6000_ARG_SIZE (mode, type))) |
4697a36c MM |
3492 | { |
3493 | int ret = GP_ARG_NUM_REG - cum->words; | |
3494 | if (ret && TARGET_DEBUG_ARG) | |
3495 | fprintf (stderr, "function_arg_partial_nregs: %d\n", ret); | |
3496 | ||
3497 | return ret; | |
3498 | } | |
3499 | ||
3500 | return 0; | |
3501 | } | |
3502 | \f | |
3503 | /* A C expression that indicates when an argument must be passed by | |
3504 | reference. If nonzero for an argument, a copy of that argument is | |
3505 | made in memory and a pointer to the argument is passed instead of | |
3506 | the argument itself. The pointer is passed in whatever way is | |
3507 | appropriate for passing a pointer to that type. | |
3508 | ||
c8c99a68 DE |
3509 | Under V.4, structures and unions are passed by reference. |
3510 | ||
3511 | As an extension to all ABIs, variable sized types are passed by | |
3512 | reference. */ | |
4697a36c MM |
3513 | |
3514 | int | |
3515 | function_arg_pass_by_reference (cum, mode, type, named) | |
296b8152 KG |
3516 | CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED; |
3517 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
4697a36c | 3518 | tree type; |
296b8152 | 3519 | int named ATTRIBUTE_UNUSED; |
4697a36c | 3520 | { |
f607bc57 | 3521 | if (DEFAULT_ABI == ABI_V4 |
4cc833b7 RH |
3522 | && ((type && AGGREGATE_TYPE_P (type)) |
3523 | || mode == TFmode)) | |
4697a36c MM |
3524 | { |
3525 | if (TARGET_DEBUG_ARG) | |
3526 | fprintf (stderr, "function_arg_pass_by_reference: aggregate\n"); | |
3527 | ||
3528 | return 1; | |
3529 | } | |
c8c99a68 | 3530 | return type && int_size_in_bytes (type) <= 0; |
4697a36c | 3531 | } |
4697a36c MM |
3532 | \f |
3533 | /* Perform any needed actions needed for a function that is receiving a | |
3534 | variable number of arguments. | |
3535 | ||
3536 | CUM is as above. | |
3537 | ||
3538 | MODE and TYPE are the mode and type of the current parameter. | |
3539 | ||
3540 | PRETEND_SIZE is a variable that should be set to the amount of stack | |
3541 | that must be pushed by the prolog to pretend that our caller pushed | |
3542 | it. | |
3543 | ||
3544 | Normally, this macro will push all remaining incoming registers on the | |
3545 | stack and set PRETEND_SIZE to the length of the registers pushed. */ | |
3546 | ||
3547 | void | |
3548 | setup_incoming_varargs (cum, mode, type, pretend_size, no_rtl) | |
3549 | CUMULATIVE_ARGS *cum; | |
3550 | enum machine_mode mode; | |
3551 | tree type; | |
de62b72c | 3552 | int *pretend_size ATTRIBUTE_UNUSED; |
4697a36c MM |
3553 | int no_rtl; |
3554 | ||
3555 | { | |
4cc833b7 RH |
3556 | CUMULATIVE_ARGS next_cum; |
3557 | int reg_size = TARGET_32BIT ? 4 : 8; | |
ca5adc63 | 3558 | rtx save_area = NULL_RTX, mem; |
dfafc897 | 3559 | int first_reg_offset, set; |
d34c5b80 DE |
3560 | tree fntype; |
3561 | int stdarg_p; | |
4697a36c | 3562 | |
d34c5b80 DE |
3563 | fntype = TREE_TYPE (current_function_decl); |
3564 | stdarg_p = (TYPE_ARG_TYPES (fntype) != 0 | |
3565 | && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype))) | |
3566 | != void_type_node)); | |
4cc833b7 | 3567 | |
d34c5b80 DE |
3568 | /* For varargs, we do not want to skip the dummy va_dcl argument. |
3569 | For stdargs, we do want to skip the last named argument. */ | |
3570 | next_cum = *cum; | |
3571 | if (stdarg_p) | |
3572 | function_arg_advance (&next_cum, mode, type, 1); | |
4cc833b7 | 3573 | |
f607bc57 | 3574 | if (DEFAULT_ABI == ABI_V4) |
d34c5b80 | 3575 | { |
4cc833b7 | 3576 | /* Indicate to allocate space on the stack for varargs save area. */ |
00dba523 | 3577 | cfun->machine->sysv_varargs_p = 1; |
60e2d0ca | 3578 | if (! no_rtl) |
2c4974b7 | 3579 | save_area = plus_constant (virtual_stack_vars_rtx, |
bd227acc | 3580 | - RS6000_VARARGS_SIZE); |
4cc833b7 RH |
3581 | |
3582 | first_reg_offset = next_cum.sysv_gregno - GP_ARG_MIN_REG; | |
4697a36c | 3583 | } |
60e2d0ca | 3584 | else |
4697a36c | 3585 | { |
d34c5b80 | 3586 | first_reg_offset = next_cum.words; |
4cc833b7 | 3587 | save_area = virtual_incoming_args_rtx; |
00dba523 | 3588 | cfun->machine->sysv_varargs_p = 0; |
4697a36c MM |
3589 | |
3590 | if (MUST_PASS_IN_STACK (mode, type)) | |
d34c5b80 | 3591 | first_reg_offset += RS6000_ARG_SIZE (TYPE_MODE (type), type); |
4cc833b7 | 3592 | } |
4697a36c | 3593 | |
dfafc897 | 3594 | set = get_varargs_alias_set (); |
c81fc13e | 3595 | if (! no_rtl && first_reg_offset < GP_ARG_NUM_REG) |
4cc833b7 | 3596 | { |
dfafc897 FS |
3597 | mem = gen_rtx_MEM (BLKmode, |
3598 | plus_constant (save_area, | |
3599 | first_reg_offset * reg_size)), | |
ba4828e0 | 3600 | set_mem_alias_set (mem, set); |
8ac61af7 | 3601 | set_mem_align (mem, BITS_PER_WORD); |
dfafc897 | 3602 | |
4cc833b7 | 3603 | move_block_from_reg |
dfafc897 | 3604 | (GP_ARG_MIN_REG + first_reg_offset, mem, |
4cc833b7 RH |
3605 | GP_ARG_NUM_REG - first_reg_offset, |
3606 | (GP_ARG_NUM_REG - first_reg_offset) * UNITS_PER_WORD); | |
4697a36c MM |
3607 | } |
3608 | ||
4697a36c | 3609 | /* Save FP registers if needed. */ |
f607bc57 | 3610 | if (DEFAULT_ABI == ABI_V4 |
a3170dc6 AH |
3611 | && TARGET_HARD_FLOAT && TARGET_FPRS |
3612 | && ! no_rtl | |
4cc833b7 | 3613 | && next_cum.fregno <= FP_ARG_V4_MAX_REG) |
4697a36c | 3614 | { |
4cc833b7 | 3615 | int fregno = next_cum.fregno; |
9ebbca7d | 3616 | rtx cr1 = gen_rtx_REG (CCmode, CR1_REGNO); |
4cc833b7 RH |
3617 | rtx lab = gen_label_rtx (); |
3618 | int off = (GP_ARG_NUM_REG * reg_size) + ((fregno - FP_ARG_MIN_REG) * 8); | |
4697a36c | 3619 | |
4cc833b7 | 3620 | emit_jump_insn (gen_rtx_SET (VOIDmode, |
4697a36c | 3621 | pc_rtx, |
39403d82 | 3622 | gen_rtx_IF_THEN_ELSE (VOIDmode, |
4cc833b7 RH |
3623 | gen_rtx_NE (VOIDmode, cr1, |
3624 | const0_rtx), | |
39403d82 | 3625 | gen_rtx_LABEL_REF (VOIDmode, lab), |
4697a36c MM |
3626 | pc_rtx))); |
3627 | ||
4cc833b7 RH |
3628 | while (fregno <= FP_ARG_V4_MAX_REG) |
3629 | { | |
dfafc897 | 3630 | mem = gen_rtx_MEM (DFmode, plus_constant (save_area, off)); |
ba4828e0 | 3631 | set_mem_alias_set (mem, set); |
dfafc897 | 3632 | emit_move_insn (mem, gen_rtx_REG (DFmode, fregno)); |
4cc833b7 RH |
3633 | fregno++; |
3634 | off += 8; | |
4697a36c | 3635 | } |
4cc833b7 RH |
3636 | |
3637 | emit_label (lab); | |
4697a36c | 3638 | } |
4697a36c | 3639 | } |
4697a36c | 3640 | |
dfafc897 | 3641 | /* Create the va_list data type. */ |
2c4974b7 | 3642 | |
dfafc897 FS |
3643 | tree |
3644 | rs6000_build_va_list () | |
3645 | { | |
bab45a51 | 3646 | tree f_gpr, f_fpr, f_ovf, f_sav, record, type_decl; |
4697a36c | 3647 | |
9ebbca7d GK |
3648 | /* For AIX, prefer 'char *' because that's what the system |
3649 | header files like. */ | |
f607bc57 | 3650 | if (DEFAULT_ABI != ABI_V4) |
9ebbca7d | 3651 | return build_pointer_type (char_type_node); |
dfafc897 | 3652 | |
f1e639b1 | 3653 | record = (*lang_hooks.types.make_type) (RECORD_TYPE); |
bab45a51 | 3654 | type_decl = build_decl (TYPE_DECL, get_identifier ("__va_list_tag"), record); |
0f4fd75d | 3655 | |
9ebbca7d GK |
3656 | f_gpr = build_decl (FIELD_DECL, get_identifier ("gpr"), |
3657 | unsigned_char_type_node); | |
3658 | f_fpr = build_decl (FIELD_DECL, get_identifier ("fpr"), | |
3659 | unsigned_char_type_node); | |
dfafc897 FS |
3660 | f_ovf = build_decl (FIELD_DECL, get_identifier ("overflow_arg_area"), |
3661 | ptr_type_node); | |
3662 | f_sav = build_decl (FIELD_DECL, get_identifier ("reg_save_area"), | |
3663 | ptr_type_node); | |
3664 | ||
3665 | DECL_FIELD_CONTEXT (f_gpr) = record; | |
3666 | DECL_FIELD_CONTEXT (f_fpr) = record; | |
3667 | DECL_FIELD_CONTEXT (f_ovf) = record; | |
3668 | DECL_FIELD_CONTEXT (f_sav) = record; | |
3669 | ||
bab45a51 FS |
3670 | TREE_CHAIN (record) = type_decl; |
3671 | TYPE_NAME (record) = type_decl; | |
dfafc897 FS |
3672 | TYPE_FIELDS (record) = f_gpr; |
3673 | TREE_CHAIN (f_gpr) = f_fpr; | |
3674 | TREE_CHAIN (f_fpr) = f_ovf; | |
3675 | TREE_CHAIN (f_ovf) = f_sav; | |
3676 | ||
3677 | layout_type (record); | |
3678 | ||
3679 | /* The correct type is an array type of one element. */ | |
3680 | return build_array_type (record, build_index_type (size_zero_node)); | |
3681 | } | |
3682 | ||
3683 | /* Implement va_start. */ | |
3684 | ||
3685 | void | |
e5faf155 | 3686 | rs6000_va_start (valist, nextarg) |
dfafc897 FS |
3687 | tree valist; |
3688 | rtx nextarg; | |
4697a36c | 3689 | { |
dfafc897 FS |
3690 | HOST_WIDE_INT words, n_gpr, n_fpr; |
3691 | tree f_gpr, f_fpr, f_ovf, f_sav; | |
3692 | tree gpr, fpr, ovf, sav, t; | |
2c4974b7 | 3693 | |
dfafc897 | 3694 | /* Only SVR4 needs something special. */ |
f607bc57 | 3695 | if (DEFAULT_ABI != ABI_V4) |
dfafc897 | 3696 | { |
e5faf155 | 3697 | std_expand_builtin_va_start (valist, nextarg); |
dfafc897 FS |
3698 | return; |
3699 | } | |
3700 | ||
973a648b | 3701 | f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node)); |
dfafc897 FS |
3702 | f_fpr = TREE_CHAIN (f_gpr); |
3703 | f_ovf = TREE_CHAIN (f_fpr); | |
3704 | f_sav = TREE_CHAIN (f_ovf); | |
3705 | ||
8ebecc3b | 3706 | valist = build1 (INDIRECT_REF, TREE_TYPE (TREE_TYPE (valist)), valist); |
dfafc897 FS |
3707 | gpr = build (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr); |
3708 | fpr = build (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr); | |
3709 | ovf = build (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf); | |
3710 | sav = build (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav); | |
3711 | ||
3712 | /* Count number of gp and fp argument registers used. */ | |
4cc833b7 | 3713 | words = current_function_args_info.words; |
dfafc897 FS |
3714 | n_gpr = current_function_args_info.sysv_gregno - GP_ARG_MIN_REG; |
3715 | n_fpr = current_function_args_info.fregno - FP_ARG_MIN_REG; | |
3716 | ||
3717 | if (TARGET_DEBUG_ARG) | |
78e1b90d DE |
3718 | { |
3719 | fputs ("va_start: words = ", stderr); | |
3720 | fprintf (stderr, HOST_WIDE_INT_PRINT_DEC, words); | |
3721 | fputs (", n_gpr = ", stderr); | |
3722 | fprintf (stderr, HOST_WIDE_INT_PRINT_DEC, n_gpr); | |
3723 | fputs (", n_fpr = ", stderr); | |
3724 | fprintf (stderr, HOST_WIDE_INT_PRINT_DEC, n_fpr); | |
3725 | putc ('\n', stderr); | |
3726 | } | |
dfafc897 FS |
3727 | |
3728 | t = build (MODIFY_EXPR, TREE_TYPE (gpr), gpr, build_int_2 (n_gpr, 0)); | |
3729 | TREE_SIDE_EFFECTS (t) = 1; | |
3730 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
3731 | ||
3732 | t = build (MODIFY_EXPR, TREE_TYPE (fpr), fpr, build_int_2 (n_fpr, 0)); | |
3733 | TREE_SIDE_EFFECTS (t) = 1; | |
3734 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
3735 | ||
3736 | /* Find the overflow area. */ | |
3737 | t = make_tree (TREE_TYPE (ovf), virtual_incoming_args_rtx); | |
3738 | if (words != 0) | |
3739 | t = build (PLUS_EXPR, TREE_TYPE (ovf), t, | |
3740 | build_int_2 (words * UNITS_PER_WORD, 0)); | |
3741 | t = build (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t); | |
3742 | TREE_SIDE_EFFECTS (t) = 1; | |
3743 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
3744 | ||
3745 | /* Find the register save area. */ | |
3746 | t = make_tree (TREE_TYPE (sav), virtual_stack_vars_rtx); | |
3747 | t = build (PLUS_EXPR, TREE_TYPE (sav), t, | |
3748 | build_int_2 (-RS6000_VARARGS_SIZE, -1)); | |
3749 | t = build (MODIFY_EXPR, TREE_TYPE (sav), sav, t); | |
3750 | TREE_SIDE_EFFECTS (t) = 1; | |
3751 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
3752 | } | |
3753 | ||
3754 | /* Implement va_arg. */ | |
3755 | ||
3756 | rtx | |
3757 | rs6000_va_arg (valist, type) | |
3758 | tree valist, type; | |
3759 | { | |
3760 | tree f_gpr, f_fpr, f_ovf, f_sav; | |
3761 | tree gpr, fpr, ovf, sav, reg, t, u; | |
3762 | int indirect_p, size, rsize, n_reg, sav_ofs, sav_scale; | |
3763 | rtx lab_false, lab_over, addr_rtx, r; | |
3764 | ||
f607bc57 | 3765 | if (DEFAULT_ABI != ABI_V4) |
c8c99a68 DE |
3766 | { |
3767 | /* Variable sized types are passed by reference. */ | |
3768 | if (int_size_in_bytes (type) <= 0) | |
3769 | { | |
3770 | u = build_pointer_type (type); | |
3771 | ||
3772 | /* Args grow upward. */ | |
3773 | t = build (POSTINCREMENT_EXPR, TREE_TYPE (valist), valist, | |
3774 | build_int_2 (POINTER_SIZE / BITS_PER_UNIT, 0)); | |
3775 | TREE_SIDE_EFFECTS (t) = 1; | |
3776 | ||
3777 | t = build1 (NOP_EXPR, build_pointer_type (u), t); | |
3778 | TREE_SIDE_EFFECTS (t) = 1; | |
3779 | ||
3780 | t = build1 (INDIRECT_REF, u, t); | |
3781 | TREE_SIDE_EFFECTS (t) = 1; | |
3782 | ||
3783 | return expand_expr (t, NULL_RTX, VOIDmode, EXPAND_NORMAL); | |
3784 | } | |
3785 | else | |
3786 | return std_expand_builtin_va_arg (valist, type); | |
3787 | } | |
dfafc897 | 3788 | |
973a648b | 3789 | f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node)); |
dfafc897 FS |
3790 | f_fpr = TREE_CHAIN (f_gpr); |
3791 | f_ovf = TREE_CHAIN (f_fpr); | |
3792 | f_sav = TREE_CHAIN (f_ovf); | |
3793 | ||
8ebecc3b | 3794 | valist = build1 (INDIRECT_REF, TREE_TYPE (TREE_TYPE (valist)), valist); |
dfafc897 FS |
3795 | gpr = build (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr); |
3796 | fpr = build (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr); | |
3797 | ovf = build (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf); | |
3798 | sav = build (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav); | |
3799 | ||
3800 | size = int_size_in_bytes (type); | |
3801 | rsize = (size + UNITS_PER_WORD - 1) / UNITS_PER_WORD; | |
4cc833b7 | 3802 | |
dfafc897 | 3803 | if (AGGREGATE_TYPE_P (type) || TYPE_MODE (type) == TFmode) |
4cc833b7 | 3804 | { |
dfafc897 FS |
3805 | /* Aggregates and long doubles are passed by reference. */ |
3806 | indirect_p = 1; | |
3807 | reg = gpr; | |
3808 | n_reg = 1; | |
3809 | sav_ofs = 0; | |
3810 | sav_scale = 4; | |
d3294cd9 FS |
3811 | size = UNITS_PER_WORD; |
3812 | rsize = 1; | |
dfafc897 | 3813 | } |
a3170dc6 | 3814 | else if (FLOAT_TYPE_P (type) && TARGET_HARD_FLOAT && TARGET_FPRS) |
dfafc897 FS |
3815 | { |
3816 | /* FP args go in FP registers, if present. */ | |
3817 | indirect_p = 0; | |
3818 | reg = fpr; | |
3819 | n_reg = 1; | |
3820 | sav_ofs = 8*4; | |
3821 | sav_scale = 8; | |
4cc833b7 | 3822 | } |
dfafc897 FS |
3823 | else |
3824 | { | |
3825 | /* Otherwise into GP registers. */ | |
3826 | indirect_p = 0; | |
3827 | reg = gpr; | |
3828 | n_reg = rsize; | |
3829 | sav_ofs = 0; | |
3830 | sav_scale = 4; | |
3831 | } | |
3832 | ||
a4f6c312 | 3833 | /* Pull the value out of the saved registers ... */ |
dfafc897 FS |
3834 | |
3835 | lab_false = gen_label_rtx (); | |
3836 | lab_over = gen_label_rtx (); | |
3837 | addr_rtx = gen_reg_rtx (Pmode); | |
3838 | ||
16861f33 AH |
3839 | /* AltiVec vectors never go in registers. */ |
3840 | if (!TARGET_ALTIVEC || TREE_CODE (type) != VECTOR_TYPE) | |
2c4974b7 | 3841 | { |
41daaf0e AH |
3842 | TREE_THIS_VOLATILE (reg) = 1; |
3843 | emit_cmp_and_jump_insns | |
3844 | (expand_expr (reg, NULL_RTX, QImode, EXPAND_NORMAL), | |
3845 | GEN_INT (8 - n_reg + 1), GE, const1_rtx, QImode, 1, | |
3846 | lab_false); | |
dfafc897 | 3847 | |
41daaf0e AH |
3848 | /* Long long is aligned in the registers. */ |
3849 | if (n_reg > 1) | |
3850 | { | |
3851 | u = build (BIT_AND_EXPR, TREE_TYPE (reg), reg, | |
3852 | build_int_2 (n_reg - 1, 0)); | |
3853 | u = build (PLUS_EXPR, TREE_TYPE (reg), reg, u); | |
3854 | u = build (MODIFY_EXPR, TREE_TYPE (reg), reg, u); | |
3855 | TREE_SIDE_EFFECTS (u) = 1; | |
3856 | expand_expr (u, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
3857 | } | |
2c4974b7 | 3858 | |
41daaf0e AH |
3859 | if (sav_ofs) |
3860 | t = build (PLUS_EXPR, ptr_type_node, sav, build_int_2 (sav_ofs, 0)); | |
3861 | else | |
3862 | t = sav; | |
2c4974b7 | 3863 | |
41daaf0e AH |
3864 | u = build (POSTINCREMENT_EXPR, TREE_TYPE (reg), reg, |
3865 | build_int_2 (n_reg, 0)); | |
3866 | TREE_SIDE_EFFECTS (u) = 1; | |
2c4974b7 | 3867 | |
41daaf0e AH |
3868 | u = build1 (CONVERT_EXPR, integer_type_node, u); |
3869 | TREE_SIDE_EFFECTS (u) = 1; | |
dfafc897 | 3870 | |
41daaf0e AH |
3871 | u = build (MULT_EXPR, integer_type_node, u, build_int_2 (sav_scale, 0)); |
3872 | TREE_SIDE_EFFECTS (u) = 1; | |
dfafc897 | 3873 | |
41daaf0e AH |
3874 | t = build (PLUS_EXPR, ptr_type_node, t, u); |
3875 | TREE_SIDE_EFFECTS (t) = 1; | |
3876 | ||
3877 | r = expand_expr (t, addr_rtx, Pmode, EXPAND_NORMAL); | |
3878 | if (r != addr_rtx) | |
3879 | emit_move_insn (addr_rtx, r); | |
3880 | ||
3881 | emit_jump_insn (gen_jump (lab_over)); | |
3882 | emit_barrier (); | |
3883 | } | |
dfafc897 | 3884 | |
dfafc897 FS |
3885 | emit_label (lab_false); |
3886 | ||
a4f6c312 | 3887 | /* ... otherwise out of the overflow area. */ |
dfafc897 | 3888 | |
41daaf0e AH |
3889 | /* Make sure we don't find reg 7 for the next int arg. |
3890 | ||
3891 | All AltiVec vectors go in the overflow area. So in the AltiVec | |
3892 | case we need to get the vectors from the overflow area, but | |
3893 | remember where the GPRs and FPRs are. */ | |
16861f33 AH |
3894 | if (n_reg > 1 && (TREE_CODE (type) != VECTOR_TYPE |
3895 | || !TARGET_ALTIVEC)) | |
dfafc897 FS |
3896 | { |
3897 | t = build (MODIFY_EXPR, TREE_TYPE (reg), reg, build_int_2 (8, 0)); | |
3898 | TREE_SIDE_EFFECTS (t) = 1; | |
3899 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
3900 | } | |
3901 | ||
3902 | /* Care for on-stack alignment if needed. */ | |
3903 | if (rsize <= 1) | |
3904 | t = ovf; | |
3905 | else | |
3906 | { | |
41daaf0e AH |
3907 | int align; |
3908 | ||
16861f33 AH |
3909 | /* AltiVec vectors are 16 byte aligned. */ |
3910 | if (TARGET_ALTIVEC && TREE_CODE (type) == VECTOR_TYPE) | |
41daaf0e AH |
3911 | align = 15; |
3912 | else | |
3913 | align = 7; | |
3914 | ||
3915 | t = build (PLUS_EXPR, TREE_TYPE (ovf), ovf, build_int_2 (align, 0)); | |
3916 | t = build (BIT_AND_EXPR, TREE_TYPE (t), t, build_int_2 (-align-1, -1)); | |
dfafc897 FS |
3917 | } |
3918 | t = save_expr (t); | |
3919 | ||
3920 | r = expand_expr (t, addr_rtx, Pmode, EXPAND_NORMAL); | |
3921 | if (r != addr_rtx) | |
3922 | emit_move_insn (addr_rtx, r); | |
3923 | ||
3924 | t = build (PLUS_EXPR, TREE_TYPE (t), t, build_int_2 (size, 0)); | |
3925 | t = build (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t); | |
3926 | TREE_SIDE_EFFECTS (t) = 1; | |
3927 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
3928 | ||
3929 | emit_label (lab_over); | |
3930 | ||
3931 | if (indirect_p) | |
3932 | { | |
3933 | r = gen_rtx_MEM (Pmode, addr_rtx); | |
ba4828e0 | 3934 | set_mem_alias_set (r, get_varargs_alias_set ()); |
dfafc897 FS |
3935 | emit_move_insn (addr_rtx, r); |
3936 | } | |
3937 | ||
3938 | return addr_rtx; | |
4697a36c | 3939 | } |
0ac081f6 AH |
3940 | |
3941 | /* Builtins. */ | |
3942 | ||
6a2dd09a RS |
3943 | #define def_builtin(MASK, NAME, TYPE, CODE) \ |
3944 | do { \ | |
3945 | if ((MASK) & target_flags) \ | |
3946 | builtin_function ((NAME), (TYPE), (CODE), BUILT_IN_MD, \ | |
3947 | NULL, NULL_TREE); \ | |
0ac081f6 AH |
3948 | } while (0) |
3949 | ||
24408032 AH |
3950 | /* Simple ternary operations: VECd = foo (VECa, VECb, VECc). */ |
3951 | ||
2212663f | 3952 | static const struct builtin_description bdesc_3arg[] = |
24408032 AH |
3953 | { |
3954 | { MASK_ALTIVEC, CODE_FOR_altivec_vmaddfp, "__builtin_altivec_vmaddfp", ALTIVEC_BUILTIN_VMADDFP }, | |
3955 | { MASK_ALTIVEC, CODE_FOR_altivec_vmhaddshs, "__builtin_altivec_vmhaddshs", ALTIVEC_BUILTIN_VMHADDSHS }, | |
3956 | { MASK_ALTIVEC, CODE_FOR_altivec_vmhraddshs, "__builtin_altivec_vmhraddshs", ALTIVEC_BUILTIN_VMHRADDSHS }, | |
3957 | { MASK_ALTIVEC, CODE_FOR_altivec_vmladduhm, "__builtin_altivec_vmladduhm", ALTIVEC_BUILTIN_VMLADDUHM}, | |
3958 | { MASK_ALTIVEC, CODE_FOR_altivec_vmsumubm, "__builtin_altivec_vmsumubm", ALTIVEC_BUILTIN_VMSUMUBM }, | |
3959 | { MASK_ALTIVEC, CODE_FOR_altivec_vmsummbm, "__builtin_altivec_vmsummbm", ALTIVEC_BUILTIN_VMSUMMBM }, | |
3960 | { MASK_ALTIVEC, CODE_FOR_altivec_vmsumuhm, "__builtin_altivec_vmsumuhm", ALTIVEC_BUILTIN_VMSUMUHM }, | |
3961 | { MASK_ALTIVEC, CODE_FOR_altivec_vmsumshm, "__builtin_altivec_vmsumshm", ALTIVEC_BUILTIN_VMSUMSHM }, | |
3962 | { MASK_ALTIVEC, CODE_FOR_altivec_vmsumuhs, "__builtin_altivec_vmsumuhs", ALTIVEC_BUILTIN_VMSUMUHS }, | |
3963 | { MASK_ALTIVEC, CODE_FOR_altivec_vmsumshs, "__builtin_altivec_vmsumshs", ALTIVEC_BUILTIN_VMSUMSHS }, | |
3964 | { MASK_ALTIVEC, CODE_FOR_altivec_vnmsubfp, "__builtin_altivec_vnmsubfp", ALTIVEC_BUILTIN_VNMSUBFP }, | |
3965 | { MASK_ALTIVEC, CODE_FOR_altivec_vperm_4sf, "__builtin_altivec_vperm_4sf", ALTIVEC_BUILTIN_VPERM_4SF }, | |
3966 | { MASK_ALTIVEC, CODE_FOR_altivec_vperm_4si, "__builtin_altivec_vperm_4si", ALTIVEC_BUILTIN_VPERM_4SI }, | |
3967 | { MASK_ALTIVEC, CODE_FOR_altivec_vperm_8hi, "__builtin_altivec_vperm_8hi", ALTIVEC_BUILTIN_VPERM_8HI }, | |
3968 | { MASK_ALTIVEC, CODE_FOR_altivec_vperm_16qi, "__builtin_altivec_vperm_16qi", ALTIVEC_BUILTIN_VPERM_16QI }, | |
3969 | { MASK_ALTIVEC, CODE_FOR_altivec_vsel_4sf, "__builtin_altivec_vsel_4sf", ALTIVEC_BUILTIN_VSEL_4SF }, | |
3970 | { MASK_ALTIVEC, CODE_FOR_altivec_vsel_4si, "__builtin_altivec_vsel_4si", ALTIVEC_BUILTIN_VSEL_4SI }, | |
3971 | { MASK_ALTIVEC, CODE_FOR_altivec_vsel_8hi, "__builtin_altivec_vsel_8hi", ALTIVEC_BUILTIN_VSEL_8HI }, | |
3972 | { MASK_ALTIVEC, CODE_FOR_altivec_vsel_16qi, "__builtin_altivec_vsel_16qi", ALTIVEC_BUILTIN_VSEL_16QI }, | |
3973 | { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_16qi, "__builtin_altivec_vsldoi_16qi", ALTIVEC_BUILTIN_VSLDOI_16QI }, | |
3974 | { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_8hi, "__builtin_altivec_vsldoi_8hi", ALTIVEC_BUILTIN_VSLDOI_8HI }, | |
3975 | { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_4si, "__builtin_altivec_vsldoi_4si", ALTIVEC_BUILTIN_VSLDOI_4SI }, | |
3976 | { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_4sf, "__builtin_altivec_vsldoi_4sf", ALTIVEC_BUILTIN_VSLDOI_4SF }, | |
3977 | }; | |
2212663f | 3978 | |
95385cbb AH |
3979 | /* DST operations: void foo (void *, const int, const char). */ |
3980 | ||
3981 | static const struct builtin_description bdesc_dst[] = | |
3982 | { | |
3983 | { MASK_ALTIVEC, CODE_FOR_altivec_dst, "__builtin_altivec_dst", ALTIVEC_BUILTIN_DST }, | |
3984 | { MASK_ALTIVEC, CODE_FOR_altivec_dstt, "__builtin_altivec_dstt", ALTIVEC_BUILTIN_DSTT }, | |
3985 | { MASK_ALTIVEC, CODE_FOR_altivec_dstst, "__builtin_altivec_dstst", ALTIVEC_BUILTIN_DSTST }, | |
3986 | { MASK_ALTIVEC, CODE_FOR_altivec_dststt, "__builtin_altivec_dststt", ALTIVEC_BUILTIN_DSTSTT } | |
3987 | }; | |
3988 | ||
2212663f | 3989 | /* Simple binary operations: VECc = foo (VECa, VECb). */ |
24408032 | 3990 | |
a3170dc6 | 3991 | static struct builtin_description bdesc_2arg[] = |
0ac081f6 | 3992 | { |
f18c054f DB |
3993 | { MASK_ALTIVEC, CODE_FOR_addv16qi3, "__builtin_altivec_vaddubm", ALTIVEC_BUILTIN_VADDUBM }, |
3994 | { MASK_ALTIVEC, CODE_FOR_addv8hi3, "__builtin_altivec_vadduhm", ALTIVEC_BUILTIN_VADDUHM }, | |
3995 | { MASK_ALTIVEC, CODE_FOR_addv4si3, "__builtin_altivec_vadduwm", ALTIVEC_BUILTIN_VADDUWM }, | |
3996 | { MASK_ALTIVEC, CODE_FOR_addv4sf3, "__builtin_altivec_vaddfp", ALTIVEC_BUILTIN_VADDFP }, | |
0ac081f6 AH |
3997 | { MASK_ALTIVEC, CODE_FOR_altivec_vaddcuw, "__builtin_altivec_vaddcuw", ALTIVEC_BUILTIN_VADDCUW }, |
3998 | { MASK_ALTIVEC, CODE_FOR_altivec_vaddubs, "__builtin_altivec_vaddubs", ALTIVEC_BUILTIN_VADDUBS }, | |
3999 | { MASK_ALTIVEC, CODE_FOR_altivec_vaddsbs, "__builtin_altivec_vaddsbs", ALTIVEC_BUILTIN_VADDSBS }, | |
4000 | { MASK_ALTIVEC, CODE_FOR_altivec_vadduhs, "__builtin_altivec_vadduhs", ALTIVEC_BUILTIN_VADDUHS }, | |
4001 | { MASK_ALTIVEC, CODE_FOR_altivec_vaddshs, "__builtin_altivec_vaddshs", ALTIVEC_BUILTIN_VADDSHS }, | |
4002 | { MASK_ALTIVEC, CODE_FOR_altivec_vadduws, "__builtin_altivec_vadduws", ALTIVEC_BUILTIN_VADDUWS }, | |
4003 | { MASK_ALTIVEC, CODE_FOR_altivec_vaddsws, "__builtin_altivec_vaddsws", ALTIVEC_BUILTIN_VADDSWS }, | |
f18c054f | 4004 | { MASK_ALTIVEC, CODE_FOR_andv4si3, "__builtin_altivec_vand", ALTIVEC_BUILTIN_VAND }, |
0ac081f6 AH |
4005 | { MASK_ALTIVEC, CODE_FOR_altivec_vandc, "__builtin_altivec_vandc", ALTIVEC_BUILTIN_VANDC }, |
4006 | { MASK_ALTIVEC, CODE_FOR_altivec_vavgub, "__builtin_altivec_vavgub", ALTIVEC_BUILTIN_VAVGUB }, | |
4007 | { MASK_ALTIVEC, CODE_FOR_altivec_vavgsb, "__builtin_altivec_vavgsb", ALTIVEC_BUILTIN_VAVGSB }, | |
4008 | { MASK_ALTIVEC, CODE_FOR_altivec_vavguh, "__builtin_altivec_vavguh", ALTIVEC_BUILTIN_VAVGUH }, | |
4009 | { MASK_ALTIVEC, CODE_FOR_altivec_vavgsh, "__builtin_altivec_vavgsh", ALTIVEC_BUILTIN_VAVGSH }, | |
4010 | { MASK_ALTIVEC, CODE_FOR_altivec_vavguw, "__builtin_altivec_vavguw", ALTIVEC_BUILTIN_VAVGUW }, | |
4011 | { MASK_ALTIVEC, CODE_FOR_altivec_vavgsw, "__builtin_altivec_vavgsw", ALTIVEC_BUILTIN_VAVGSW }, | |
617e0e1d DB |
4012 | { MASK_ALTIVEC, CODE_FOR_altivec_vcfux, "__builtin_altivec_vcfux", ALTIVEC_BUILTIN_VCFUX }, |
4013 | { MASK_ALTIVEC, CODE_FOR_altivec_vcfsx, "__builtin_altivec_vcfsx", ALTIVEC_BUILTIN_VCFSX }, | |
0ac081f6 AH |
4014 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpbfp, "__builtin_altivec_vcmpbfp", ALTIVEC_BUILTIN_VCMPBFP }, |
4015 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequb, "__builtin_altivec_vcmpequb", ALTIVEC_BUILTIN_VCMPEQUB }, | |
4016 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequh, "__builtin_altivec_vcmpequh", ALTIVEC_BUILTIN_VCMPEQUH }, | |
4017 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequw, "__builtin_altivec_vcmpequw", ALTIVEC_BUILTIN_VCMPEQUW }, | |
4018 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpeqfp, "__builtin_altivec_vcmpeqfp", ALTIVEC_BUILTIN_VCMPEQFP }, | |
4019 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgefp, "__builtin_altivec_vcmpgefp", ALTIVEC_BUILTIN_VCMPGEFP }, | |
4020 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtub, "__builtin_altivec_vcmpgtub", ALTIVEC_BUILTIN_VCMPGTUB }, | |
4021 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsb, "__builtin_altivec_vcmpgtsb", ALTIVEC_BUILTIN_VCMPGTSB }, | |
4022 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtuh, "__builtin_altivec_vcmpgtuh", ALTIVEC_BUILTIN_VCMPGTUH }, | |
4023 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsh, "__builtin_altivec_vcmpgtsh", ALTIVEC_BUILTIN_VCMPGTSH }, | |
4024 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtuw, "__builtin_altivec_vcmpgtuw", ALTIVEC_BUILTIN_VCMPGTUW }, | |
4025 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsw, "__builtin_altivec_vcmpgtsw", ALTIVEC_BUILTIN_VCMPGTSW }, | |
4026 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtfp, "__builtin_altivec_vcmpgtfp", ALTIVEC_BUILTIN_VCMPGTFP }, | |
617e0e1d DB |
4027 | { MASK_ALTIVEC, CODE_FOR_altivec_vctsxs, "__builtin_altivec_vctsxs", ALTIVEC_BUILTIN_VCTSXS }, |
4028 | { MASK_ALTIVEC, CODE_FOR_altivec_vctuxs, "__builtin_altivec_vctuxs", ALTIVEC_BUILTIN_VCTUXS }, | |
f18c054f DB |
4029 | { MASK_ALTIVEC, CODE_FOR_umaxv16qi3, "__builtin_altivec_vmaxub", ALTIVEC_BUILTIN_VMAXUB }, |
4030 | { MASK_ALTIVEC, CODE_FOR_smaxv16qi3, "__builtin_altivec_vmaxsb", ALTIVEC_BUILTIN_VMAXSB }, | |
df966bff AH |
4031 | { MASK_ALTIVEC, CODE_FOR_umaxv8hi3, "__builtin_altivec_vmaxuh", ALTIVEC_BUILTIN_VMAXUH }, |
4032 | { MASK_ALTIVEC, CODE_FOR_smaxv8hi3, "__builtin_altivec_vmaxsh", ALTIVEC_BUILTIN_VMAXSH }, | |
4033 | { MASK_ALTIVEC, CODE_FOR_umaxv4si3, "__builtin_altivec_vmaxuw", ALTIVEC_BUILTIN_VMAXUW }, | |
4034 | { MASK_ALTIVEC, CODE_FOR_smaxv4si3, "__builtin_altivec_vmaxsw", ALTIVEC_BUILTIN_VMAXSW }, | |
4035 | { MASK_ALTIVEC, CODE_FOR_smaxv4sf3, "__builtin_altivec_vmaxfp", ALTIVEC_BUILTIN_VMAXFP }, | |
0ac081f6 AH |
4036 | { MASK_ALTIVEC, CODE_FOR_altivec_vmrghb, "__builtin_altivec_vmrghb", ALTIVEC_BUILTIN_VMRGHB }, |
4037 | { MASK_ALTIVEC, CODE_FOR_altivec_vmrghh, "__builtin_altivec_vmrghh", ALTIVEC_BUILTIN_VMRGHH }, | |
4038 | { MASK_ALTIVEC, CODE_FOR_altivec_vmrghw, "__builtin_altivec_vmrghw", ALTIVEC_BUILTIN_VMRGHW }, | |
4039 | { MASK_ALTIVEC, CODE_FOR_altivec_vmrglb, "__builtin_altivec_vmrglb", ALTIVEC_BUILTIN_VMRGLB }, | |
4040 | { MASK_ALTIVEC, CODE_FOR_altivec_vmrglh, "__builtin_altivec_vmrglh", ALTIVEC_BUILTIN_VMRGLH }, | |
4041 | { MASK_ALTIVEC, CODE_FOR_altivec_vmrglw, "__builtin_altivec_vmrglw", ALTIVEC_BUILTIN_VMRGLW }, | |
f18c054f DB |
4042 | { MASK_ALTIVEC, CODE_FOR_uminv16qi3, "__builtin_altivec_vminub", ALTIVEC_BUILTIN_VMINUB }, |
4043 | { MASK_ALTIVEC, CODE_FOR_sminv16qi3, "__builtin_altivec_vminsb", ALTIVEC_BUILTIN_VMINSB }, | |
4044 | { MASK_ALTIVEC, CODE_FOR_uminv8hi3, "__builtin_altivec_vminuh", ALTIVEC_BUILTIN_VMINUH }, | |
4045 | { MASK_ALTIVEC, CODE_FOR_sminv8hi3, "__builtin_altivec_vminsh", ALTIVEC_BUILTIN_VMINSH }, | |
4046 | { MASK_ALTIVEC, CODE_FOR_uminv4si3, "__builtin_altivec_vminuw", ALTIVEC_BUILTIN_VMINUW }, | |
4047 | { MASK_ALTIVEC, CODE_FOR_sminv4si3, "__builtin_altivec_vminsw", ALTIVEC_BUILTIN_VMINSW }, | |
4048 | { MASK_ALTIVEC, CODE_FOR_sminv4sf3, "__builtin_altivec_vminfp", ALTIVEC_BUILTIN_VMINFP }, | |
0ac081f6 AH |
4049 | { MASK_ALTIVEC, CODE_FOR_altivec_vmuleub, "__builtin_altivec_vmuleub", ALTIVEC_BUILTIN_VMULEUB }, |
4050 | { MASK_ALTIVEC, CODE_FOR_altivec_vmulesb, "__builtin_altivec_vmulesb", ALTIVEC_BUILTIN_VMULESB }, | |
4051 | { MASK_ALTIVEC, CODE_FOR_altivec_vmuleuh, "__builtin_altivec_vmuleuh", ALTIVEC_BUILTIN_VMULEUH }, | |
4052 | { MASK_ALTIVEC, CODE_FOR_altivec_vmulesh, "__builtin_altivec_vmulesh", ALTIVEC_BUILTIN_VMULESH }, | |
4053 | { MASK_ALTIVEC, CODE_FOR_altivec_vmuloub, "__builtin_altivec_vmuloub", ALTIVEC_BUILTIN_VMULOUB }, | |
4054 | { MASK_ALTIVEC, CODE_FOR_altivec_vmulosb, "__builtin_altivec_vmulosb", ALTIVEC_BUILTIN_VMULOSB }, | |
4055 | { MASK_ALTIVEC, CODE_FOR_altivec_vmulouh, "__builtin_altivec_vmulouh", ALTIVEC_BUILTIN_VMULOUH }, | |
4056 | { MASK_ALTIVEC, CODE_FOR_altivec_vmulosh, "__builtin_altivec_vmulosh", ALTIVEC_BUILTIN_VMULOSH }, | |
4057 | { MASK_ALTIVEC, CODE_FOR_altivec_vnor, "__builtin_altivec_vnor", ALTIVEC_BUILTIN_VNOR }, | |
f18c054f | 4058 | { MASK_ALTIVEC, CODE_FOR_iorv4si3, "__builtin_altivec_vor", ALTIVEC_BUILTIN_VOR }, |
0ac081f6 AH |
4059 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhum, "__builtin_altivec_vpkuhum", ALTIVEC_BUILTIN_VPKUHUM }, |
4060 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwum, "__builtin_altivec_vpkuwum", ALTIVEC_BUILTIN_VPKUWUM }, | |
4061 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkpx, "__builtin_altivec_vpkpx", ALTIVEC_BUILTIN_VPKPX }, | |
4062 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhss, "__builtin_altivec_vpkuhss", ALTIVEC_BUILTIN_VPKUHSS }, | |
4063 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkshss, "__builtin_altivec_vpkshss", ALTIVEC_BUILTIN_VPKSHSS }, | |
4064 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwss, "__builtin_altivec_vpkuwss", ALTIVEC_BUILTIN_VPKUWSS }, | |
4065 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkswss, "__builtin_altivec_vpkswss", ALTIVEC_BUILTIN_VPKSWSS }, | |
4066 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhus, "__builtin_altivec_vpkuhus", ALTIVEC_BUILTIN_VPKUHUS }, | |
4067 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkshus, "__builtin_altivec_vpkshus", ALTIVEC_BUILTIN_VPKSHUS }, | |
4068 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwus, "__builtin_altivec_vpkuwus", ALTIVEC_BUILTIN_VPKUWUS }, | |
4069 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkswus, "__builtin_altivec_vpkswus", ALTIVEC_BUILTIN_VPKSWUS }, | |
4070 | { MASK_ALTIVEC, CODE_FOR_altivec_vrlb, "__builtin_altivec_vrlb", ALTIVEC_BUILTIN_VRLB }, | |
4071 | { MASK_ALTIVEC, CODE_FOR_altivec_vrlh, "__builtin_altivec_vrlh", ALTIVEC_BUILTIN_VRLH }, | |
4072 | { MASK_ALTIVEC, CODE_FOR_altivec_vrlw, "__builtin_altivec_vrlw", ALTIVEC_BUILTIN_VRLW }, | |
4073 | { MASK_ALTIVEC, CODE_FOR_altivec_vslb, "__builtin_altivec_vslb", ALTIVEC_BUILTIN_VSLB }, | |
4074 | { MASK_ALTIVEC, CODE_FOR_altivec_vslh, "__builtin_altivec_vslh", ALTIVEC_BUILTIN_VSLH }, | |
4075 | { MASK_ALTIVEC, CODE_FOR_altivec_vslw, "__builtin_altivec_vslw", ALTIVEC_BUILTIN_VSLW }, | |
4076 | { MASK_ALTIVEC, CODE_FOR_altivec_vsl, "__builtin_altivec_vsl", ALTIVEC_BUILTIN_VSL }, | |
4077 | { MASK_ALTIVEC, CODE_FOR_altivec_vslo, "__builtin_altivec_vslo", ALTIVEC_BUILTIN_VSLO }, | |
2212663f DB |
4078 | { MASK_ALTIVEC, CODE_FOR_altivec_vspltb, "__builtin_altivec_vspltb", ALTIVEC_BUILTIN_VSPLTB }, |
4079 | { MASK_ALTIVEC, CODE_FOR_altivec_vsplth, "__builtin_altivec_vsplth", ALTIVEC_BUILTIN_VSPLTH }, | |
4080 | { MASK_ALTIVEC, CODE_FOR_altivec_vspltw, "__builtin_altivec_vspltw", ALTIVEC_BUILTIN_VSPLTW }, | |
0ac081f6 | 4081 | { MASK_ALTIVEC, CODE_FOR_altivec_vsrb, "__builtin_altivec_vsrb", ALTIVEC_BUILTIN_VSRB }, |
f18c054f DB |
4082 | { MASK_ALTIVEC, CODE_FOR_altivec_vsrh, "__builtin_altivec_vsrh", ALTIVEC_BUILTIN_VSRH }, |
4083 | { MASK_ALTIVEC, CODE_FOR_altivec_vsrw, "__builtin_altivec_vsrw", ALTIVEC_BUILTIN_VSRW }, | |
0ac081f6 AH |
4084 | { MASK_ALTIVEC, CODE_FOR_altivec_vsrab, "__builtin_altivec_vsrab", ALTIVEC_BUILTIN_VSRAB }, |
4085 | { MASK_ALTIVEC, CODE_FOR_altivec_vsrah, "__builtin_altivec_vsrah", ALTIVEC_BUILTIN_VSRAH }, | |
4086 | { MASK_ALTIVEC, CODE_FOR_altivec_vsraw, "__builtin_altivec_vsraw", ALTIVEC_BUILTIN_VSRAW }, | |
4087 | { MASK_ALTIVEC, CODE_FOR_altivec_vsr, "__builtin_altivec_vsr", ALTIVEC_BUILTIN_VSR }, | |
4088 | { MASK_ALTIVEC, CODE_FOR_altivec_vsro, "__builtin_altivec_vsro", ALTIVEC_BUILTIN_VSRO }, | |
f18c054f DB |
4089 | { MASK_ALTIVEC, CODE_FOR_subv16qi3, "__builtin_altivec_vsububm", ALTIVEC_BUILTIN_VSUBUBM }, |
4090 | { MASK_ALTIVEC, CODE_FOR_subv8hi3, "__builtin_altivec_vsubuhm", ALTIVEC_BUILTIN_VSUBUHM }, | |
4091 | { MASK_ALTIVEC, CODE_FOR_subv4si3, "__builtin_altivec_vsubuwm", ALTIVEC_BUILTIN_VSUBUWM }, | |
4092 | { MASK_ALTIVEC, CODE_FOR_subv4sf3, "__builtin_altivec_vsubfp", ALTIVEC_BUILTIN_VSUBFP }, | |
0ac081f6 AH |
4093 | { MASK_ALTIVEC, CODE_FOR_altivec_vsubcuw, "__builtin_altivec_vsubcuw", ALTIVEC_BUILTIN_VSUBCUW }, |
4094 | { MASK_ALTIVEC, CODE_FOR_altivec_vsububs, "__builtin_altivec_vsububs", ALTIVEC_BUILTIN_VSUBUBS }, | |
4095 | { MASK_ALTIVEC, CODE_FOR_altivec_vsubsbs, "__builtin_altivec_vsubsbs", ALTIVEC_BUILTIN_VSUBSBS }, | |
4096 | { MASK_ALTIVEC, CODE_FOR_altivec_vsubuhs, "__builtin_altivec_vsubuhs", ALTIVEC_BUILTIN_VSUBUHS }, | |
4097 | { MASK_ALTIVEC, CODE_FOR_altivec_vsubshs, "__builtin_altivec_vsubshs", ALTIVEC_BUILTIN_VSUBSHS }, | |
4098 | { MASK_ALTIVEC, CODE_FOR_altivec_vsubuws, "__builtin_altivec_vsubuws", ALTIVEC_BUILTIN_VSUBUWS }, | |
4099 | { MASK_ALTIVEC, CODE_FOR_altivec_vsubsws, "__builtin_altivec_vsubsws", ALTIVEC_BUILTIN_VSUBSWS }, | |
4100 | { MASK_ALTIVEC, CODE_FOR_altivec_vsum4ubs, "__builtin_altivec_vsum4ubs", ALTIVEC_BUILTIN_VSUM4UBS }, | |
4101 | { MASK_ALTIVEC, CODE_FOR_altivec_vsum4sbs, "__builtin_altivec_vsum4sbs", ALTIVEC_BUILTIN_VSUM4SBS }, | |
4102 | { MASK_ALTIVEC, CODE_FOR_altivec_vsum4shs, "__builtin_altivec_vsum4shs", ALTIVEC_BUILTIN_VSUM4SHS }, | |
4103 | { MASK_ALTIVEC, CODE_FOR_altivec_vsum2sws, "__builtin_altivec_vsum2sws", ALTIVEC_BUILTIN_VSUM2SWS }, | |
4104 | { MASK_ALTIVEC, CODE_FOR_altivec_vsumsws, "__builtin_altivec_vsumsws", ALTIVEC_BUILTIN_VSUMSWS }, | |
f18c054f | 4105 | { MASK_ALTIVEC, CODE_FOR_xorv4si3, "__builtin_altivec_vxor", ALTIVEC_BUILTIN_VXOR }, |
a3170dc6 AH |
4106 | |
4107 | /* Place holder, leave as first spe builtin. */ | |
4108 | { 0, CODE_FOR_spe_evaddw, "__builtin_spe_evaddw", SPE_BUILTIN_EVADDW }, | |
4109 | { 0, CODE_FOR_spe_evand, "__builtin_spe_evand", SPE_BUILTIN_EVAND }, | |
4110 | { 0, CODE_FOR_spe_evandc, "__builtin_spe_evandc", SPE_BUILTIN_EVANDC }, | |
4111 | { 0, CODE_FOR_spe_evdivws, "__builtin_spe_evdivws", SPE_BUILTIN_EVDIVWS }, | |
4112 | { 0, CODE_FOR_spe_evdivwu, "__builtin_spe_evdivwu", SPE_BUILTIN_EVDIVWU }, | |
4113 | { 0, CODE_FOR_spe_eveqv, "__builtin_spe_eveqv", SPE_BUILTIN_EVEQV }, | |
4114 | { 0, CODE_FOR_spe_evfsadd, "__builtin_spe_evfsadd", SPE_BUILTIN_EVFSADD }, | |
4115 | { 0, CODE_FOR_spe_evfsdiv, "__builtin_spe_evfsdiv", SPE_BUILTIN_EVFSDIV }, | |
4116 | { 0, CODE_FOR_spe_evfsmul, "__builtin_spe_evfsmul", SPE_BUILTIN_EVFSMUL }, | |
4117 | { 0, CODE_FOR_spe_evfssub, "__builtin_spe_evfssub", SPE_BUILTIN_EVFSSUB }, | |
4118 | { 0, CODE_FOR_spe_evmergehi, "__builtin_spe_evmergehi", SPE_BUILTIN_EVMERGEHI }, | |
4119 | { 0, CODE_FOR_spe_evmergehilo, "__builtin_spe_evmergehilo", SPE_BUILTIN_EVMERGEHILO }, | |
4120 | { 0, CODE_FOR_spe_evmergelo, "__builtin_spe_evmergelo", SPE_BUILTIN_EVMERGELO }, | |
4121 | { 0, CODE_FOR_spe_evmergelohi, "__builtin_spe_evmergelohi", SPE_BUILTIN_EVMERGELOHI }, | |
4122 | { 0, CODE_FOR_spe_evmhegsmfaa, "__builtin_spe_evmhegsmfaa", SPE_BUILTIN_EVMHEGSMFAA }, | |
4123 | { 0, CODE_FOR_spe_evmhegsmfan, "__builtin_spe_evmhegsmfan", SPE_BUILTIN_EVMHEGSMFAN }, | |
4124 | { 0, CODE_FOR_spe_evmhegsmiaa, "__builtin_spe_evmhegsmiaa", SPE_BUILTIN_EVMHEGSMIAA }, | |
4125 | { 0, CODE_FOR_spe_evmhegsmian, "__builtin_spe_evmhegsmian", SPE_BUILTIN_EVMHEGSMIAN }, | |
4126 | { 0, CODE_FOR_spe_evmhegumiaa, "__builtin_spe_evmhegumiaa", SPE_BUILTIN_EVMHEGUMIAA }, | |
4127 | { 0, CODE_FOR_spe_evmhegumian, "__builtin_spe_evmhegumian", SPE_BUILTIN_EVMHEGUMIAN }, | |
4128 | { 0, CODE_FOR_spe_evmhesmf, "__builtin_spe_evmhesmf", SPE_BUILTIN_EVMHESMF }, | |
4129 | { 0, CODE_FOR_spe_evmhesmfa, "__builtin_spe_evmhesmfa", SPE_BUILTIN_EVMHESMFA }, | |
4130 | { 0, CODE_FOR_spe_evmhesmfaaw, "__builtin_spe_evmhesmfaaw", SPE_BUILTIN_EVMHESMFAAW }, | |
4131 | { 0, CODE_FOR_spe_evmhesmfanw, "__builtin_spe_evmhesmfanw", SPE_BUILTIN_EVMHESMFANW }, | |
4132 | { 0, CODE_FOR_spe_evmhesmi, "__builtin_spe_evmhesmi", SPE_BUILTIN_EVMHESMI }, | |
4133 | { 0, CODE_FOR_spe_evmhesmia, "__builtin_spe_evmhesmia", SPE_BUILTIN_EVMHESMIA }, | |
4134 | { 0, CODE_FOR_spe_evmhesmiaaw, "__builtin_spe_evmhesmiaaw", SPE_BUILTIN_EVMHESMIAAW }, | |
4135 | { 0, CODE_FOR_spe_evmhesmianw, "__builtin_spe_evmhesmianw", SPE_BUILTIN_EVMHESMIANW }, | |
4136 | { 0, CODE_FOR_spe_evmhessf, "__builtin_spe_evmhessf", SPE_BUILTIN_EVMHESSF }, | |
4137 | { 0, CODE_FOR_spe_evmhessfa, "__builtin_spe_evmhessfa", SPE_BUILTIN_EVMHESSFA }, | |
4138 | { 0, CODE_FOR_spe_evmhessfaaw, "__builtin_spe_evmhessfaaw", SPE_BUILTIN_EVMHESSFAAW }, | |
4139 | { 0, CODE_FOR_spe_evmhessfanw, "__builtin_spe_evmhessfanw", SPE_BUILTIN_EVMHESSFANW }, | |
4140 | { 0, CODE_FOR_spe_evmhessiaaw, "__builtin_spe_evmhessiaaw", SPE_BUILTIN_EVMHESSIAAW }, | |
4141 | { 0, CODE_FOR_spe_evmhessianw, "__builtin_spe_evmhessianw", SPE_BUILTIN_EVMHESSIANW }, | |
4142 | { 0, CODE_FOR_spe_evmheumi, "__builtin_spe_evmheumi", SPE_BUILTIN_EVMHEUMI }, | |
4143 | { 0, CODE_FOR_spe_evmheumia, "__builtin_spe_evmheumia", SPE_BUILTIN_EVMHEUMIA }, | |
4144 | { 0, CODE_FOR_spe_evmheumiaaw, "__builtin_spe_evmheumiaaw", SPE_BUILTIN_EVMHEUMIAAW }, | |
4145 | { 0, CODE_FOR_spe_evmheumianw, "__builtin_spe_evmheumianw", SPE_BUILTIN_EVMHEUMIANW }, | |
4146 | { 0, CODE_FOR_spe_evmheusiaaw, "__builtin_spe_evmheusiaaw", SPE_BUILTIN_EVMHEUSIAAW }, | |
4147 | { 0, CODE_FOR_spe_evmheusianw, "__builtin_spe_evmheusianw", SPE_BUILTIN_EVMHEUSIANW }, | |
4148 | { 0, CODE_FOR_spe_evmhogsmfaa, "__builtin_spe_evmhogsmfaa", SPE_BUILTIN_EVMHOGSMFAA }, | |
4149 | { 0, CODE_FOR_spe_evmhogsmfan, "__builtin_spe_evmhogsmfan", SPE_BUILTIN_EVMHOGSMFAN }, | |
4150 | { 0, CODE_FOR_spe_evmhogsmiaa, "__builtin_spe_evmhogsmiaa", SPE_BUILTIN_EVMHOGSMIAA }, | |
4151 | { 0, CODE_FOR_spe_evmhogsmian, "__builtin_spe_evmhogsmian", SPE_BUILTIN_EVMHOGSMIAN }, | |
4152 | { 0, CODE_FOR_spe_evmhogumiaa, "__builtin_spe_evmhogumiaa", SPE_BUILTIN_EVMHOGUMIAA }, | |
4153 | { 0, CODE_FOR_spe_evmhogumian, "__builtin_spe_evmhogumian", SPE_BUILTIN_EVMHOGUMIAN }, | |
4154 | { 0, CODE_FOR_spe_evmhosmf, "__builtin_spe_evmhosmf", SPE_BUILTIN_EVMHOSMF }, | |
4155 | { 0, CODE_FOR_spe_evmhosmfa, "__builtin_spe_evmhosmfa", SPE_BUILTIN_EVMHOSMFA }, | |
4156 | { 0, CODE_FOR_spe_evmhosmfaaw, "__builtin_spe_evmhosmfaaw", SPE_BUILTIN_EVMHOSMFAAW }, | |
4157 | { 0, CODE_FOR_spe_evmhosmfanw, "__builtin_spe_evmhosmfanw", SPE_BUILTIN_EVMHOSMFANW }, | |
4158 | { 0, CODE_FOR_spe_evmhosmi, "__builtin_spe_evmhosmi", SPE_BUILTIN_EVMHOSMI }, | |
4159 | { 0, CODE_FOR_spe_evmhosmia, "__builtin_spe_evmhosmia", SPE_BUILTIN_EVMHOSMIA }, | |
4160 | { 0, CODE_FOR_spe_evmhosmiaaw, "__builtin_spe_evmhosmiaaw", SPE_BUILTIN_EVMHOSMIAAW }, | |
4161 | { 0, CODE_FOR_spe_evmhosmianw, "__builtin_spe_evmhosmianw", SPE_BUILTIN_EVMHOSMIANW }, | |
4162 | { 0, CODE_FOR_spe_evmhossf, "__builtin_spe_evmhossf", SPE_BUILTIN_EVMHOSSF }, | |
4163 | { 0, CODE_FOR_spe_evmhossfa, "__builtin_spe_evmhossfa", SPE_BUILTIN_EVMHOSSFA }, | |
4164 | { 0, CODE_FOR_spe_evmhossfaaw, "__builtin_spe_evmhossfaaw", SPE_BUILTIN_EVMHOSSFAAW }, | |
4165 | { 0, CODE_FOR_spe_evmhossfanw, "__builtin_spe_evmhossfanw", SPE_BUILTIN_EVMHOSSFANW }, | |
4166 | { 0, CODE_FOR_spe_evmhossiaaw, "__builtin_spe_evmhossiaaw", SPE_BUILTIN_EVMHOSSIAAW }, | |
4167 | { 0, CODE_FOR_spe_evmhossianw, "__builtin_spe_evmhossianw", SPE_BUILTIN_EVMHOSSIANW }, | |
4168 | { 0, CODE_FOR_spe_evmhoumi, "__builtin_spe_evmhoumi", SPE_BUILTIN_EVMHOUMI }, | |
4169 | { 0, CODE_FOR_spe_evmhoumia, "__builtin_spe_evmhoumia", SPE_BUILTIN_EVMHOUMIA }, | |
4170 | { 0, CODE_FOR_spe_evmhoumiaaw, "__builtin_spe_evmhoumiaaw", SPE_BUILTIN_EVMHOUMIAAW }, | |
4171 | { 0, CODE_FOR_spe_evmhoumianw, "__builtin_spe_evmhoumianw", SPE_BUILTIN_EVMHOUMIANW }, | |
4172 | { 0, CODE_FOR_spe_evmhousiaaw, "__builtin_spe_evmhousiaaw", SPE_BUILTIN_EVMHOUSIAAW }, | |
4173 | { 0, CODE_FOR_spe_evmhousianw, "__builtin_spe_evmhousianw", SPE_BUILTIN_EVMHOUSIANW }, | |
4174 | { 0, CODE_FOR_spe_evmwhsmf, "__builtin_spe_evmwhsmf", SPE_BUILTIN_EVMWHSMF }, | |
4175 | { 0, CODE_FOR_spe_evmwhsmfa, "__builtin_spe_evmwhsmfa", SPE_BUILTIN_EVMWHSMFA }, | |
4176 | { 0, CODE_FOR_spe_evmwhsmi, "__builtin_spe_evmwhsmi", SPE_BUILTIN_EVMWHSMI }, | |
4177 | { 0, CODE_FOR_spe_evmwhsmia, "__builtin_spe_evmwhsmia", SPE_BUILTIN_EVMWHSMIA }, | |
4178 | { 0, CODE_FOR_spe_evmwhssf, "__builtin_spe_evmwhssf", SPE_BUILTIN_EVMWHSSF }, | |
4179 | { 0, CODE_FOR_spe_evmwhssfa, "__builtin_spe_evmwhssfa", SPE_BUILTIN_EVMWHSSFA }, | |
4180 | { 0, CODE_FOR_spe_evmwhumi, "__builtin_spe_evmwhumi", SPE_BUILTIN_EVMWHUMI }, | |
4181 | { 0, CODE_FOR_spe_evmwhumia, "__builtin_spe_evmwhumia", SPE_BUILTIN_EVMWHUMIA }, | |
a3170dc6 AH |
4182 | { 0, CODE_FOR_spe_evmwlsmiaaw, "__builtin_spe_evmwlsmiaaw", SPE_BUILTIN_EVMWLSMIAAW }, |
4183 | { 0, CODE_FOR_spe_evmwlsmianw, "__builtin_spe_evmwlsmianw", SPE_BUILTIN_EVMWLSMIANW }, | |
a3170dc6 AH |
4184 | { 0, CODE_FOR_spe_evmwlssiaaw, "__builtin_spe_evmwlssiaaw", SPE_BUILTIN_EVMWLSSIAAW }, |
4185 | { 0, CODE_FOR_spe_evmwlssianw, "__builtin_spe_evmwlssianw", SPE_BUILTIN_EVMWLSSIANW }, | |
4186 | { 0, CODE_FOR_spe_evmwlumi, "__builtin_spe_evmwlumi", SPE_BUILTIN_EVMWLUMI }, | |
4187 | { 0, CODE_FOR_spe_evmwlumia, "__builtin_spe_evmwlumia", SPE_BUILTIN_EVMWLUMIA }, | |
4188 | { 0, CODE_FOR_spe_evmwlumiaaw, "__builtin_spe_evmwlumiaaw", SPE_BUILTIN_EVMWLUMIAAW }, | |
4189 | { 0, CODE_FOR_spe_evmwlumianw, "__builtin_spe_evmwlumianw", SPE_BUILTIN_EVMWLUMIANW }, | |
4190 | { 0, CODE_FOR_spe_evmwlusiaaw, "__builtin_spe_evmwlusiaaw", SPE_BUILTIN_EVMWLUSIAAW }, | |
4191 | { 0, CODE_FOR_spe_evmwlusianw, "__builtin_spe_evmwlusianw", SPE_BUILTIN_EVMWLUSIANW }, | |
4192 | { 0, CODE_FOR_spe_evmwsmf, "__builtin_spe_evmwsmf", SPE_BUILTIN_EVMWSMF }, | |
4193 | { 0, CODE_FOR_spe_evmwsmfa, "__builtin_spe_evmwsmfa", SPE_BUILTIN_EVMWSMFA }, | |
4194 | { 0, CODE_FOR_spe_evmwsmfaa, "__builtin_spe_evmwsmfaa", SPE_BUILTIN_EVMWSMFAA }, | |
4195 | { 0, CODE_FOR_spe_evmwsmfan, "__builtin_spe_evmwsmfan", SPE_BUILTIN_EVMWSMFAN }, | |
4196 | { 0, CODE_FOR_spe_evmwsmi, "__builtin_spe_evmwsmi", SPE_BUILTIN_EVMWSMI }, | |
4197 | { 0, CODE_FOR_spe_evmwsmia, "__builtin_spe_evmwsmia", SPE_BUILTIN_EVMWSMIA }, | |
4198 | { 0, CODE_FOR_spe_evmwsmiaa, "__builtin_spe_evmwsmiaa", SPE_BUILTIN_EVMWSMIAA }, | |
4199 | { 0, CODE_FOR_spe_evmwsmian, "__builtin_spe_evmwsmian", SPE_BUILTIN_EVMWSMIAN }, | |
4200 | { 0, CODE_FOR_spe_evmwssf, "__builtin_spe_evmwssf", SPE_BUILTIN_EVMWSSF }, | |
4201 | { 0, CODE_FOR_spe_evmwssfa, "__builtin_spe_evmwssfa", SPE_BUILTIN_EVMWSSFA }, | |
4202 | { 0, CODE_FOR_spe_evmwssfaa, "__builtin_spe_evmwssfaa", SPE_BUILTIN_EVMWSSFAA }, | |
4203 | { 0, CODE_FOR_spe_evmwssfan, "__builtin_spe_evmwssfan", SPE_BUILTIN_EVMWSSFAN }, | |
4204 | { 0, CODE_FOR_spe_evmwumi, "__builtin_spe_evmwumi", SPE_BUILTIN_EVMWUMI }, | |
4205 | { 0, CODE_FOR_spe_evmwumia, "__builtin_spe_evmwumia", SPE_BUILTIN_EVMWUMIA }, | |
4206 | { 0, CODE_FOR_spe_evmwumiaa, "__builtin_spe_evmwumiaa", SPE_BUILTIN_EVMWUMIAA }, | |
4207 | { 0, CODE_FOR_spe_evmwumian, "__builtin_spe_evmwumian", SPE_BUILTIN_EVMWUMIAN }, | |
4208 | { 0, CODE_FOR_spe_evnand, "__builtin_spe_evnand", SPE_BUILTIN_EVNAND }, | |
4209 | { 0, CODE_FOR_spe_evnor, "__builtin_spe_evnor", SPE_BUILTIN_EVNOR }, | |
4210 | { 0, CODE_FOR_spe_evor, "__builtin_spe_evor", SPE_BUILTIN_EVOR }, | |
4211 | { 0, CODE_FOR_spe_evorc, "__builtin_spe_evorc", SPE_BUILTIN_EVORC }, | |
4212 | { 0, CODE_FOR_spe_evrlw, "__builtin_spe_evrlw", SPE_BUILTIN_EVRLW }, | |
4213 | { 0, CODE_FOR_spe_evslw, "__builtin_spe_evslw", SPE_BUILTIN_EVSLW }, | |
4214 | { 0, CODE_FOR_spe_evsrws, "__builtin_spe_evsrws", SPE_BUILTIN_EVSRWS }, | |
4215 | { 0, CODE_FOR_spe_evsrwu, "__builtin_spe_evsrwu", SPE_BUILTIN_EVSRWU }, | |
4216 | { 0, CODE_FOR_spe_evsubfw, "__builtin_spe_evsubfw", SPE_BUILTIN_EVSUBFW }, | |
4217 | ||
4218 | /* SPE binary operations expecting a 5-bit unsigned literal. */ | |
4219 | { 0, CODE_FOR_spe_evaddiw, "__builtin_spe_evaddiw", SPE_BUILTIN_EVADDIW }, | |
4220 | ||
4221 | { 0, CODE_FOR_spe_evrlwi, "__builtin_spe_evrlwi", SPE_BUILTIN_EVRLWI }, | |
4222 | { 0, CODE_FOR_spe_evslwi, "__builtin_spe_evslwi", SPE_BUILTIN_EVSLWI }, | |
4223 | { 0, CODE_FOR_spe_evsrwis, "__builtin_spe_evsrwis", SPE_BUILTIN_EVSRWIS }, | |
4224 | { 0, CODE_FOR_spe_evsrwiu, "__builtin_spe_evsrwiu", SPE_BUILTIN_EVSRWIU }, | |
4225 | { 0, CODE_FOR_spe_evsubifw, "__builtin_spe_evsubifw", SPE_BUILTIN_EVSUBIFW }, | |
4226 | { 0, CODE_FOR_spe_evmwhssfaa, "__builtin_spe_evmwhssfaa", SPE_BUILTIN_EVMWHSSFAA }, | |
4227 | { 0, CODE_FOR_spe_evmwhssmaa, "__builtin_spe_evmwhssmaa", SPE_BUILTIN_EVMWHSSMAA }, | |
4228 | { 0, CODE_FOR_spe_evmwhsmfaa, "__builtin_spe_evmwhsmfaa", SPE_BUILTIN_EVMWHSMFAA }, | |
4229 | { 0, CODE_FOR_spe_evmwhsmiaa, "__builtin_spe_evmwhsmiaa", SPE_BUILTIN_EVMWHSMIAA }, | |
4230 | { 0, CODE_FOR_spe_evmwhusiaa, "__builtin_spe_evmwhusiaa", SPE_BUILTIN_EVMWHUSIAA }, | |
4231 | { 0, CODE_FOR_spe_evmwhumiaa, "__builtin_spe_evmwhumiaa", SPE_BUILTIN_EVMWHUMIAA }, | |
4232 | { 0, CODE_FOR_spe_evmwhssfan, "__builtin_spe_evmwhssfan", SPE_BUILTIN_EVMWHSSFAN }, | |
4233 | { 0, CODE_FOR_spe_evmwhssian, "__builtin_spe_evmwhssian", SPE_BUILTIN_EVMWHSSIAN }, | |
4234 | { 0, CODE_FOR_spe_evmwhsmfan, "__builtin_spe_evmwhsmfan", SPE_BUILTIN_EVMWHSMFAN }, | |
4235 | { 0, CODE_FOR_spe_evmwhsmian, "__builtin_spe_evmwhsmian", SPE_BUILTIN_EVMWHSMIAN }, | |
4236 | { 0, CODE_FOR_spe_evmwhusian, "__builtin_spe_evmwhusian", SPE_BUILTIN_EVMWHUSIAN }, | |
4237 | { 0, CODE_FOR_spe_evmwhumian, "__builtin_spe_evmwhumian", SPE_BUILTIN_EVMWHUMIAN }, | |
4238 | { 0, CODE_FOR_spe_evmwhgssfaa, "__builtin_spe_evmwhgssfaa", SPE_BUILTIN_EVMWHGSSFAA }, | |
4239 | { 0, CODE_FOR_spe_evmwhgsmfaa, "__builtin_spe_evmwhgsmfaa", SPE_BUILTIN_EVMWHGSMFAA }, | |
4240 | { 0, CODE_FOR_spe_evmwhgsmiaa, "__builtin_spe_evmwhgsmiaa", SPE_BUILTIN_EVMWHGSMIAA }, | |
4241 | { 0, CODE_FOR_spe_evmwhgumiaa, "__builtin_spe_evmwhgumiaa", SPE_BUILTIN_EVMWHGUMIAA }, | |
4242 | { 0, CODE_FOR_spe_evmwhgssfan, "__builtin_spe_evmwhgssfan", SPE_BUILTIN_EVMWHGSSFAN }, | |
4243 | { 0, CODE_FOR_spe_evmwhgsmfan, "__builtin_spe_evmwhgsmfan", SPE_BUILTIN_EVMWHGSMFAN }, | |
4244 | { 0, CODE_FOR_spe_evmwhgsmian, "__builtin_spe_evmwhgsmian", SPE_BUILTIN_EVMWHGSMIAN }, | |
4245 | { 0, CODE_FOR_spe_evmwhgumian, "__builtin_spe_evmwhgumian", SPE_BUILTIN_EVMWHGUMIAN }, | |
4246 | { 0, CODE_FOR_spe_brinc, "__builtin_spe_brinc", SPE_BUILTIN_BRINC }, | |
4247 | ||
4248 | /* Place-holder. Leave as last binary SPE builtin. */ | |
17edbda5 | 4249 | { 0, CODE_FOR_xorv2si3, "__builtin_spe_evxor", SPE_BUILTIN_EVXOR }, |
ae4b4a02 AH |
4250 | }; |
4251 | ||
4252 | /* AltiVec predicates. */ | |
4253 | ||
4254 | struct builtin_description_predicates | |
4255 | { | |
4256 | const unsigned int mask; | |
4257 | const enum insn_code icode; | |
4258 | const char *opcode; | |
4259 | const char *const name; | |
4260 | const enum rs6000_builtins code; | |
4261 | }; | |
4262 | ||
4263 | static const struct builtin_description_predicates bdesc_altivec_preds[] = | |
4264 | { | |
4265 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpbfp.", "__builtin_altivec_vcmpbfp_p", ALTIVEC_BUILTIN_VCMPBFP_P }, | |
4266 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpeqfp.", "__builtin_altivec_vcmpeqfp_p", ALTIVEC_BUILTIN_VCMPEQFP_P }, | |
4267 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpgefp.", "__builtin_altivec_vcmpgefp_p", ALTIVEC_BUILTIN_VCMPGEFP_P }, | |
4268 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpgtfp.", "__builtin_altivec_vcmpgtfp_p", ALTIVEC_BUILTIN_VCMPGTFP_P }, | |
4269 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpequw.", "__builtin_altivec_vcmpequw_p", ALTIVEC_BUILTIN_VCMPEQUW_P }, | |
4270 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpgtsw.", "__builtin_altivec_vcmpgtsw_p", ALTIVEC_BUILTIN_VCMPGTSW_P }, | |
4271 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpgtuw.", "__builtin_altivec_vcmpgtuw_p", ALTIVEC_BUILTIN_VCMPGTUW_P }, | |
4272 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpgtuh.", "__builtin_altivec_vcmpgtuh_p", ALTIVEC_BUILTIN_VCMPGTUH_P }, | |
4273 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpgtsh.", "__builtin_altivec_vcmpgtsh_p", ALTIVEC_BUILTIN_VCMPGTSH_P }, | |
4274 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpequh.", "__builtin_altivec_vcmpequh_p", ALTIVEC_BUILTIN_VCMPEQUH_P }, | |
4275 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpequb.", "__builtin_altivec_vcmpequb_p", ALTIVEC_BUILTIN_VCMPEQUB_P }, | |
4276 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpgtsb.", "__builtin_altivec_vcmpgtsb_p", ALTIVEC_BUILTIN_VCMPGTSB_P }, | |
4277 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpgtub.", "__builtin_altivec_vcmpgtub_p", ALTIVEC_BUILTIN_VCMPGTUB_P } | |
0ac081f6 | 4278 | }; |
24408032 | 4279 | |
a3170dc6 AH |
4280 | /* SPE predicates. */ |
4281 | static struct builtin_description bdesc_spe_predicates[] = | |
4282 | { | |
4283 | /* Place-holder. Leave as first. */ | |
4284 | { 0, CODE_FOR_spe_evcmpeq, "__builtin_spe_evcmpeq", SPE_BUILTIN_EVCMPEQ }, | |
4285 | { 0, CODE_FOR_spe_evcmpgts, "__builtin_spe_evcmpgts", SPE_BUILTIN_EVCMPGTS }, | |
4286 | { 0, CODE_FOR_spe_evcmpgtu, "__builtin_spe_evcmpgtu", SPE_BUILTIN_EVCMPGTU }, | |
4287 | { 0, CODE_FOR_spe_evcmplts, "__builtin_spe_evcmplts", SPE_BUILTIN_EVCMPLTS }, | |
4288 | { 0, CODE_FOR_spe_evcmpltu, "__builtin_spe_evcmpltu", SPE_BUILTIN_EVCMPLTU }, | |
4289 | { 0, CODE_FOR_spe_evfscmpeq, "__builtin_spe_evfscmpeq", SPE_BUILTIN_EVFSCMPEQ }, | |
4290 | { 0, CODE_FOR_spe_evfscmpgt, "__builtin_spe_evfscmpgt", SPE_BUILTIN_EVFSCMPGT }, | |
4291 | { 0, CODE_FOR_spe_evfscmplt, "__builtin_spe_evfscmplt", SPE_BUILTIN_EVFSCMPLT }, | |
4292 | { 0, CODE_FOR_spe_evfststeq, "__builtin_spe_evfststeq", SPE_BUILTIN_EVFSTSTEQ }, | |
4293 | { 0, CODE_FOR_spe_evfststgt, "__builtin_spe_evfststgt", SPE_BUILTIN_EVFSTSTGT }, | |
4294 | /* Place-holder. Leave as last. */ | |
4295 | { 0, CODE_FOR_spe_evfststlt, "__builtin_spe_evfststlt", SPE_BUILTIN_EVFSTSTLT }, | |
4296 | }; | |
4297 | ||
4298 | /* SPE evsel predicates. */ | |
4299 | static struct builtin_description bdesc_spe_evsel[] = | |
4300 | { | |
4301 | /* Place-holder. Leave as first. */ | |
4302 | { 0, CODE_FOR_spe_evcmpgts, "__builtin_spe_evsel_gts", SPE_BUILTIN_EVSEL_CMPGTS }, | |
4303 | { 0, CODE_FOR_spe_evcmpgtu, "__builtin_spe_evsel_gtu", SPE_BUILTIN_EVSEL_CMPGTU }, | |
4304 | { 0, CODE_FOR_spe_evcmplts, "__builtin_spe_evsel_lts", SPE_BUILTIN_EVSEL_CMPLTS }, | |
4305 | { 0, CODE_FOR_spe_evcmpltu, "__builtin_spe_evsel_ltu", SPE_BUILTIN_EVSEL_CMPLTU }, | |
4306 | { 0, CODE_FOR_spe_evcmpeq, "__builtin_spe_evsel_eq", SPE_BUILTIN_EVSEL_CMPEQ }, | |
4307 | { 0, CODE_FOR_spe_evfscmpgt, "__builtin_spe_evsel_fsgt", SPE_BUILTIN_EVSEL_FSCMPGT }, | |
4308 | { 0, CODE_FOR_spe_evfscmplt, "__builtin_spe_evsel_fslt", SPE_BUILTIN_EVSEL_FSCMPLT }, | |
4309 | { 0, CODE_FOR_spe_evfscmpeq, "__builtin_spe_evsel_fseq", SPE_BUILTIN_EVSEL_FSCMPEQ }, | |
4310 | { 0, CODE_FOR_spe_evfststgt, "__builtin_spe_evsel_fststgt", SPE_BUILTIN_EVSEL_FSTSTGT }, | |
4311 | { 0, CODE_FOR_spe_evfststlt, "__builtin_spe_evsel_fststlt", SPE_BUILTIN_EVSEL_FSTSTLT }, | |
4312 | /* Place-holder. Leave as last. */ | |
4313 | { 0, CODE_FOR_spe_evfststeq, "__builtin_spe_evsel_fststeq", SPE_BUILTIN_EVSEL_FSTSTEQ }, | |
4314 | }; | |
4315 | ||
b6d08ca1 | 4316 | /* ABS* operations. */ |
100c4561 AH |
4317 | |
4318 | static const struct builtin_description bdesc_abs[] = | |
4319 | { | |
4320 | { MASK_ALTIVEC, CODE_FOR_absv4si2, "__builtin_altivec_abs_v4si", ALTIVEC_BUILTIN_ABS_V4SI }, | |
4321 | { MASK_ALTIVEC, CODE_FOR_absv8hi2, "__builtin_altivec_abs_v8hi", ALTIVEC_BUILTIN_ABS_V8HI }, | |
4322 | { MASK_ALTIVEC, CODE_FOR_absv4sf2, "__builtin_altivec_abs_v4sf", ALTIVEC_BUILTIN_ABS_V4SF }, | |
4323 | { MASK_ALTIVEC, CODE_FOR_absv16qi2, "__builtin_altivec_abs_v16qi", ALTIVEC_BUILTIN_ABS_V16QI }, | |
4324 | { MASK_ALTIVEC, CODE_FOR_altivec_abss_v4si, "__builtin_altivec_abss_v4si", ALTIVEC_BUILTIN_ABSS_V4SI }, | |
4325 | { MASK_ALTIVEC, CODE_FOR_altivec_abss_v8hi, "__builtin_altivec_abss_v8hi", ALTIVEC_BUILTIN_ABSS_V8HI }, | |
4326 | { MASK_ALTIVEC, CODE_FOR_altivec_abss_v16qi, "__builtin_altivec_abss_v16qi", ALTIVEC_BUILTIN_ABSS_V16QI } | |
4327 | }; | |
4328 | ||
617e0e1d DB |
4329 | /* Simple unary operations: VECb = foo (unsigned literal) or VECb = |
4330 | foo (VECa). */ | |
24408032 | 4331 | |
a3170dc6 | 4332 | static struct builtin_description bdesc_1arg[] = |
2212663f | 4333 | { |
617e0e1d DB |
4334 | { MASK_ALTIVEC, CODE_FOR_altivec_vexptefp, "__builtin_altivec_vexptefp", ALTIVEC_BUILTIN_VEXPTEFP }, |
4335 | { MASK_ALTIVEC, CODE_FOR_altivec_vlogefp, "__builtin_altivec_vlogefp", ALTIVEC_BUILTIN_VLOGEFP }, | |
4336 | { MASK_ALTIVEC, CODE_FOR_altivec_vrefp, "__builtin_altivec_vrefp", ALTIVEC_BUILTIN_VREFP }, | |
4337 | { MASK_ALTIVEC, CODE_FOR_altivec_vrfim, "__builtin_altivec_vrfim", ALTIVEC_BUILTIN_VRFIM }, | |
4338 | { MASK_ALTIVEC, CODE_FOR_altivec_vrfin, "__builtin_altivec_vrfin", ALTIVEC_BUILTIN_VRFIN }, | |
4339 | { MASK_ALTIVEC, CODE_FOR_altivec_vrfip, "__builtin_altivec_vrfip", ALTIVEC_BUILTIN_VRFIP }, | |
4340 | { MASK_ALTIVEC, CODE_FOR_ftruncv4sf2, "__builtin_altivec_vrfiz", ALTIVEC_BUILTIN_VRFIZ }, | |
4341 | { MASK_ALTIVEC, CODE_FOR_altivec_vrsqrtefp, "__builtin_altivec_vrsqrtefp", ALTIVEC_BUILTIN_VRSQRTEFP }, | |
2212663f DB |
4342 | { MASK_ALTIVEC, CODE_FOR_altivec_vspltisb, "__builtin_altivec_vspltisb", ALTIVEC_BUILTIN_VSPLTISB }, |
4343 | { MASK_ALTIVEC, CODE_FOR_altivec_vspltish, "__builtin_altivec_vspltish", ALTIVEC_BUILTIN_VSPLTISH }, | |
4344 | { MASK_ALTIVEC, CODE_FOR_altivec_vspltisw, "__builtin_altivec_vspltisw", ALTIVEC_BUILTIN_VSPLTISW }, | |
20e26713 AH |
4345 | { MASK_ALTIVEC, CODE_FOR_altivec_vupkhsb, "__builtin_altivec_vupkhsb", ALTIVEC_BUILTIN_VUPKHSB }, |
4346 | { MASK_ALTIVEC, CODE_FOR_altivec_vupkhpx, "__builtin_altivec_vupkhpx", ALTIVEC_BUILTIN_VUPKHPX }, | |
4347 | { MASK_ALTIVEC, CODE_FOR_altivec_vupkhsh, "__builtin_altivec_vupkhsh", ALTIVEC_BUILTIN_VUPKHSH }, | |
4348 | { MASK_ALTIVEC, CODE_FOR_altivec_vupklsb, "__builtin_altivec_vupklsb", ALTIVEC_BUILTIN_VUPKLSB }, | |
4349 | { MASK_ALTIVEC, CODE_FOR_altivec_vupklpx, "__builtin_altivec_vupklpx", ALTIVEC_BUILTIN_VUPKLPX }, | |
4350 | { MASK_ALTIVEC, CODE_FOR_altivec_vupklsh, "__builtin_altivec_vupklsh", ALTIVEC_BUILTIN_VUPKLSH }, | |
a3170dc6 AH |
4351 | |
4352 | /* The SPE unary builtins must start with SPE_BUILTIN_EVABS and | |
4353 | end with SPE_BUILTIN_EVSUBFUSIAAW. */ | |
4354 | { 0, CODE_FOR_spe_evabs, "__builtin_spe_evabs", SPE_BUILTIN_EVABS }, | |
4355 | { 0, CODE_FOR_spe_evaddsmiaaw, "__builtin_spe_evaddsmiaaw", SPE_BUILTIN_EVADDSMIAAW }, | |
4356 | { 0, CODE_FOR_spe_evaddssiaaw, "__builtin_spe_evaddssiaaw", SPE_BUILTIN_EVADDSSIAAW }, | |
4357 | { 0, CODE_FOR_spe_evaddumiaaw, "__builtin_spe_evaddumiaaw", SPE_BUILTIN_EVADDUMIAAW }, | |
4358 | { 0, CODE_FOR_spe_evaddusiaaw, "__builtin_spe_evaddusiaaw", SPE_BUILTIN_EVADDUSIAAW }, | |
4359 | { 0, CODE_FOR_spe_evcntlsw, "__builtin_spe_evcntlsw", SPE_BUILTIN_EVCNTLSW }, | |
4360 | { 0, CODE_FOR_spe_evcntlzw, "__builtin_spe_evcntlzw", SPE_BUILTIN_EVCNTLZW }, | |
4361 | { 0, CODE_FOR_spe_evextsb, "__builtin_spe_evextsb", SPE_BUILTIN_EVEXTSB }, | |
4362 | { 0, CODE_FOR_spe_evextsh, "__builtin_spe_evextsh", SPE_BUILTIN_EVEXTSH }, | |
4363 | { 0, CODE_FOR_spe_evfsabs, "__builtin_spe_evfsabs", SPE_BUILTIN_EVFSABS }, | |
4364 | { 0, CODE_FOR_spe_evfscfsf, "__builtin_spe_evfscfsf", SPE_BUILTIN_EVFSCFSF }, | |
4365 | { 0, CODE_FOR_spe_evfscfsi, "__builtin_spe_evfscfsi", SPE_BUILTIN_EVFSCFSI }, | |
4366 | { 0, CODE_FOR_spe_evfscfuf, "__builtin_spe_evfscfuf", SPE_BUILTIN_EVFSCFUF }, | |
4367 | { 0, CODE_FOR_spe_evfscfui, "__builtin_spe_evfscfui", SPE_BUILTIN_EVFSCFUI }, | |
4368 | { 0, CODE_FOR_spe_evfsctsf, "__builtin_spe_evfsctsf", SPE_BUILTIN_EVFSCTSF }, | |
4369 | { 0, CODE_FOR_spe_evfsctsi, "__builtin_spe_evfsctsi", SPE_BUILTIN_EVFSCTSI }, | |
4370 | { 0, CODE_FOR_spe_evfsctsiz, "__builtin_spe_evfsctsiz", SPE_BUILTIN_EVFSCTSIZ }, | |
4371 | { 0, CODE_FOR_spe_evfsctuf, "__builtin_spe_evfsctuf", SPE_BUILTIN_EVFSCTUF }, | |
4372 | { 0, CODE_FOR_spe_evfsctui, "__builtin_spe_evfsctui", SPE_BUILTIN_EVFSCTUI }, | |
4373 | { 0, CODE_FOR_spe_evfsctuiz, "__builtin_spe_evfsctuiz", SPE_BUILTIN_EVFSCTUIZ }, | |
4374 | { 0, CODE_FOR_spe_evfsnabs, "__builtin_spe_evfsnabs", SPE_BUILTIN_EVFSNABS }, | |
4375 | { 0, CODE_FOR_spe_evfsneg, "__builtin_spe_evfsneg", SPE_BUILTIN_EVFSNEG }, | |
4376 | { 0, CODE_FOR_spe_evmra, "__builtin_spe_evmra", SPE_BUILTIN_EVMRA }, | |
4377 | { 0, CODE_FOR_spe_evneg, "__builtin_spe_evneg", SPE_BUILTIN_EVNEG }, | |
4378 | { 0, CODE_FOR_spe_evrndw, "__builtin_spe_evrndw", SPE_BUILTIN_EVRNDW }, | |
4379 | { 0, CODE_FOR_spe_evsubfsmiaaw, "__builtin_spe_evsubfsmiaaw", SPE_BUILTIN_EVSUBFSMIAAW }, | |
4380 | { 0, CODE_FOR_spe_evsubfssiaaw, "__builtin_spe_evsubfssiaaw", SPE_BUILTIN_EVSUBFSSIAAW }, | |
4381 | { 0, CODE_FOR_spe_evsubfumiaaw, "__builtin_spe_evsubfumiaaw", SPE_BUILTIN_EVSUBFUMIAAW }, | |
4382 | { 0, CODE_FOR_spe_evsplatfi, "__builtin_spe_evsplatfi", SPE_BUILTIN_EVSPLATFI }, | |
4383 | { 0, CODE_FOR_spe_evsplati, "__builtin_spe_evsplati", SPE_BUILTIN_EVSPLATI }, | |
4384 | ||
4385 | /* Place-holder. Leave as last unary SPE builtin. */ | |
4386 | { 0, CODE_FOR_spe_evsubfusiaaw, "__builtin_spe_evsubfusiaaw", SPE_BUILTIN_EVSUBFUSIAAW }, | |
2212663f DB |
4387 | }; |
4388 | ||
4389 | static rtx | |
92898235 | 4390 | rs6000_expand_unop_builtin (icode, arglist, target) |
2212663f DB |
4391 | enum insn_code icode; |
4392 | tree arglist; | |
4393 | rtx target; | |
4394 | { | |
4395 | rtx pat; | |
4396 | tree arg0 = TREE_VALUE (arglist); | |
4397 | rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
4398 | enum machine_mode tmode = insn_data[icode].operand[0].mode; | |
4399 | enum machine_mode mode0 = insn_data[icode].operand[1].mode; | |
4400 | ||
0559cc77 DE |
4401 | if (icode == CODE_FOR_nothing) |
4402 | /* Builtin not supported on this processor. */ | |
4403 | return 0; | |
4404 | ||
20e26713 AH |
4405 | /* If we got invalid arguments bail out before generating bad rtl. */ |
4406 | if (arg0 == error_mark_node) | |
9a171fcd | 4407 | return const0_rtx; |
20e26713 | 4408 | |
0559cc77 DE |
4409 | if (icode == CODE_FOR_altivec_vspltisb |
4410 | || icode == CODE_FOR_altivec_vspltish | |
4411 | || icode == CODE_FOR_altivec_vspltisw | |
4412 | || icode == CODE_FOR_spe_evsplatfi | |
4413 | || icode == CODE_FOR_spe_evsplati) | |
b44140e7 AH |
4414 | { |
4415 | /* Only allow 5-bit *signed* literals. */ | |
b44140e7 AH |
4416 | if (GET_CODE (op0) != CONST_INT |
4417 | || INTVAL (op0) > 0x1f | |
4418 | || INTVAL (op0) < -0x1f) | |
4419 | { | |
4420 | error ("argument 1 must be a 5-bit signed literal"); | |
9a171fcd | 4421 | return const0_rtx; |
b44140e7 | 4422 | } |
b44140e7 AH |
4423 | } |
4424 | ||
c62f2db5 | 4425 | if (target == 0 |
2212663f DB |
4426 | || GET_MODE (target) != tmode |
4427 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
4428 | target = gen_reg_rtx (tmode); | |
4429 | ||
4430 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) | |
4431 | op0 = copy_to_mode_reg (mode0, op0); | |
4432 | ||
4433 | pat = GEN_FCN (icode) (target, op0); | |
4434 | if (! pat) | |
4435 | return 0; | |
4436 | emit_insn (pat); | |
0ac081f6 | 4437 | |
2212663f DB |
4438 | return target; |
4439 | } | |
ae4b4a02 | 4440 | |
100c4561 AH |
4441 | static rtx |
4442 | altivec_expand_abs_builtin (icode, arglist, target) | |
4443 | enum insn_code icode; | |
4444 | tree arglist; | |
4445 | rtx target; | |
4446 | { | |
4447 | rtx pat, scratch1, scratch2; | |
4448 | tree arg0 = TREE_VALUE (arglist); | |
4449 | rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
4450 | enum machine_mode tmode = insn_data[icode].operand[0].mode; | |
4451 | enum machine_mode mode0 = insn_data[icode].operand[1].mode; | |
4452 | ||
4453 | /* If we have invalid arguments, bail out before generating bad rtl. */ | |
4454 | if (arg0 == error_mark_node) | |
9a171fcd | 4455 | return const0_rtx; |
100c4561 AH |
4456 | |
4457 | if (target == 0 | |
4458 | || GET_MODE (target) != tmode | |
4459 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
4460 | target = gen_reg_rtx (tmode); | |
4461 | ||
4462 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) | |
4463 | op0 = copy_to_mode_reg (mode0, op0); | |
4464 | ||
4465 | scratch1 = gen_reg_rtx (mode0); | |
4466 | scratch2 = gen_reg_rtx (mode0); | |
4467 | ||
4468 | pat = GEN_FCN (icode) (target, op0, scratch1, scratch2); | |
4469 | if (! pat) | |
4470 | return 0; | |
4471 | emit_insn (pat); | |
4472 | ||
4473 | return target; | |
4474 | } | |
4475 | ||
0ac081f6 | 4476 | static rtx |
92898235 | 4477 | rs6000_expand_binop_builtin (icode, arglist, target) |
0ac081f6 AH |
4478 | enum insn_code icode; |
4479 | tree arglist; | |
4480 | rtx target; | |
4481 | { | |
4482 | rtx pat; | |
4483 | tree arg0 = TREE_VALUE (arglist); | |
4484 | tree arg1 = TREE_VALUE (TREE_CHAIN (arglist)); | |
4485 | rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
4486 | rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); | |
4487 | enum machine_mode tmode = insn_data[icode].operand[0].mode; | |
4488 | enum machine_mode mode0 = insn_data[icode].operand[1].mode; | |
4489 | enum machine_mode mode1 = insn_data[icode].operand[2].mode; | |
4490 | ||
0559cc77 DE |
4491 | if (icode == CODE_FOR_nothing) |
4492 | /* Builtin not supported on this processor. */ | |
4493 | return 0; | |
4494 | ||
20e26713 AH |
4495 | /* If we got invalid arguments bail out before generating bad rtl. */ |
4496 | if (arg0 == error_mark_node || arg1 == error_mark_node) | |
9a171fcd | 4497 | return const0_rtx; |
20e26713 | 4498 | |
0559cc77 DE |
4499 | if (icode == CODE_FOR_altivec_vcfux |
4500 | || icode == CODE_FOR_altivec_vcfsx | |
4501 | || icode == CODE_FOR_altivec_vctsxs | |
4502 | || icode == CODE_FOR_altivec_vctuxs | |
4503 | || icode == CODE_FOR_altivec_vspltb | |
4504 | || icode == CODE_FOR_altivec_vsplth | |
4505 | || icode == CODE_FOR_altivec_vspltw | |
4506 | || icode == CODE_FOR_spe_evaddiw | |
4507 | || icode == CODE_FOR_spe_evldd | |
4508 | || icode == CODE_FOR_spe_evldh | |
4509 | || icode == CODE_FOR_spe_evldw | |
4510 | || icode == CODE_FOR_spe_evlhhesplat | |
4511 | || icode == CODE_FOR_spe_evlhhossplat | |
4512 | || icode == CODE_FOR_spe_evlhhousplat | |
4513 | || icode == CODE_FOR_spe_evlwhe | |
4514 | || icode == CODE_FOR_spe_evlwhos | |
4515 | || icode == CODE_FOR_spe_evlwhou | |
4516 | || icode == CODE_FOR_spe_evlwhsplat | |
4517 | || icode == CODE_FOR_spe_evlwwsplat | |
4518 | || icode == CODE_FOR_spe_evrlwi | |
4519 | || icode == CODE_FOR_spe_evslwi | |
4520 | || icode == CODE_FOR_spe_evsrwis | |
4521 | || icode == CODE_FOR_spe_evsrwiu) | |
b44140e7 AH |
4522 | { |
4523 | /* Only allow 5-bit unsigned literals. */ | |
b44140e7 AH |
4524 | if (TREE_CODE (arg1) != INTEGER_CST |
4525 | || TREE_INT_CST_LOW (arg1) & ~0x1f) | |
4526 | { | |
4527 | error ("argument 2 must be a 5-bit unsigned literal"); | |
9a171fcd | 4528 | return const0_rtx; |
b44140e7 | 4529 | } |
b44140e7 AH |
4530 | } |
4531 | ||
c62f2db5 | 4532 | if (target == 0 |
0ac081f6 AH |
4533 | || GET_MODE (target) != tmode |
4534 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
4535 | target = gen_reg_rtx (tmode); | |
4536 | ||
4537 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) | |
4538 | op0 = copy_to_mode_reg (mode0, op0); | |
4539 | if (! (*insn_data[icode].operand[2].predicate) (op1, mode1)) | |
4540 | op1 = copy_to_mode_reg (mode1, op1); | |
4541 | ||
4542 | pat = GEN_FCN (icode) (target, op0, op1); | |
4543 | if (! pat) | |
4544 | return 0; | |
4545 | emit_insn (pat); | |
4546 | ||
4547 | return target; | |
4548 | } | |
6525c0e7 | 4549 | |
ae4b4a02 AH |
4550 | static rtx |
4551 | altivec_expand_predicate_builtin (icode, opcode, arglist, target) | |
4552 | enum insn_code icode; | |
4553 | const char *opcode; | |
4554 | tree arglist; | |
4555 | rtx target; | |
4556 | { | |
4557 | rtx pat, scratch; | |
4558 | tree cr6_form = TREE_VALUE (arglist); | |
4559 | tree arg0 = TREE_VALUE (TREE_CHAIN (arglist)); | |
4560 | tree arg1 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist))); | |
4561 | rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
4562 | rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); | |
4563 | enum machine_mode tmode = SImode; | |
4564 | enum machine_mode mode0 = insn_data[icode].operand[1].mode; | |
4565 | enum machine_mode mode1 = insn_data[icode].operand[2].mode; | |
4566 | int cr6_form_int; | |
4567 | ||
4568 | if (TREE_CODE (cr6_form) != INTEGER_CST) | |
4569 | { | |
4570 | error ("argument 1 of __builtin_altivec_predicate must be a constant"); | |
9a171fcd | 4571 | return const0_rtx; |
ae4b4a02 AH |
4572 | } |
4573 | else | |
4574 | cr6_form_int = TREE_INT_CST_LOW (cr6_form); | |
4575 | ||
4576 | if (mode0 != mode1) | |
4577 | abort (); | |
4578 | ||
4579 | /* If we have invalid arguments, bail out before generating bad rtl. */ | |
4580 | if (arg0 == error_mark_node || arg1 == error_mark_node) | |
9a171fcd | 4581 | return const0_rtx; |
ae4b4a02 AH |
4582 | |
4583 | if (target == 0 | |
4584 | || GET_MODE (target) != tmode | |
4585 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
4586 | target = gen_reg_rtx (tmode); | |
4587 | ||
4588 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) | |
4589 | op0 = copy_to_mode_reg (mode0, op0); | |
4590 | if (! (*insn_data[icode].operand[2].predicate) (op1, mode1)) | |
4591 | op1 = copy_to_mode_reg (mode1, op1); | |
4592 | ||
4593 | scratch = gen_reg_rtx (mode0); | |
4594 | ||
4595 | pat = GEN_FCN (icode) (scratch, op0, op1, | |
4596 | gen_rtx (SYMBOL_REF, Pmode, opcode)); | |
4597 | if (! pat) | |
4598 | return 0; | |
4599 | emit_insn (pat); | |
4600 | ||
4601 | /* The vec_any* and vec_all* predicates use the same opcodes for two | |
4602 | different operations, but the bits in CR6 will be different | |
4603 | depending on what information we want. So we have to play tricks | |
4604 | with CR6 to get the right bits out. | |
4605 | ||
4606 | If you think this is disgusting, look at the specs for the | |
4607 | AltiVec predicates. */ | |
4608 | ||
4609 | switch (cr6_form_int) | |
4610 | { | |
4611 | case 0: | |
4612 | emit_insn (gen_cr6_test_for_zero (target)); | |
4613 | break; | |
4614 | case 1: | |
4615 | emit_insn (gen_cr6_test_for_zero_reverse (target)); | |
4616 | break; | |
4617 | case 2: | |
4618 | emit_insn (gen_cr6_test_for_lt (target)); | |
4619 | break; | |
4620 | case 3: | |
4621 | emit_insn (gen_cr6_test_for_lt_reverse (target)); | |
4622 | break; | |
4623 | default: | |
4624 | error ("argument 1 of __builtin_altivec_predicate is out of range"); | |
4625 | break; | |
4626 | } | |
4627 | ||
4628 | return target; | |
4629 | } | |
4630 | ||
6525c0e7 AH |
4631 | static rtx |
4632 | altivec_expand_stv_builtin (icode, arglist) | |
4633 | enum insn_code icode; | |
4634 | tree arglist; | |
4635 | { | |
4636 | tree arg0 = TREE_VALUE (arglist); | |
4637 | tree arg1 = TREE_VALUE (TREE_CHAIN (arglist)); | |
4638 | tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist))); | |
4639 | rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
4640 | rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); | |
4641 | rtx op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0); | |
4642 | rtx pat; | |
4643 | enum machine_mode mode0 = insn_data[icode].operand[0].mode; | |
4644 | enum machine_mode mode1 = insn_data[icode].operand[1].mode; | |
4645 | enum machine_mode mode2 = insn_data[icode].operand[2].mode; | |
4646 | ||
4647 | /* Invalid arguments. Bail before doing anything stoopid! */ | |
4648 | if (arg0 == error_mark_node | |
4649 | || arg1 == error_mark_node | |
4650 | || arg2 == error_mark_node) | |
9a171fcd | 4651 | return const0_rtx; |
6525c0e7 AH |
4652 | |
4653 | if (! (*insn_data[icode].operand[2].predicate) (op0, mode2)) | |
4654 | op0 = copy_to_mode_reg (mode2, op0); | |
4655 | if (! (*insn_data[icode].operand[0].predicate) (op1, mode0)) | |
4656 | op1 = copy_to_mode_reg (mode0, op1); | |
4657 | if (! (*insn_data[icode].operand[1].predicate) (op2, mode1)) | |
4658 | op2 = copy_to_mode_reg (mode1, op2); | |
4659 | ||
4660 | pat = GEN_FCN (icode) (op1, op2, op0); | |
4661 | if (pat) | |
4662 | emit_insn (pat); | |
4663 | return NULL_RTX; | |
4664 | } | |
4665 | ||
2212663f | 4666 | static rtx |
92898235 | 4667 | rs6000_expand_ternop_builtin (icode, arglist, target) |
2212663f DB |
4668 | enum insn_code icode; |
4669 | tree arglist; | |
4670 | rtx target; | |
4671 | { | |
4672 | rtx pat; | |
4673 | tree arg0 = TREE_VALUE (arglist); | |
4674 | tree arg1 = TREE_VALUE (TREE_CHAIN (arglist)); | |
4675 | tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist))); | |
4676 | rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
4677 | rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); | |
4678 | rtx op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0); | |
4679 | enum machine_mode tmode = insn_data[icode].operand[0].mode; | |
4680 | enum machine_mode mode0 = insn_data[icode].operand[1].mode; | |
4681 | enum machine_mode mode1 = insn_data[icode].operand[2].mode; | |
4682 | enum machine_mode mode2 = insn_data[icode].operand[3].mode; | |
0ac081f6 | 4683 | |
774b5662 DE |
4684 | if (icode == CODE_FOR_nothing) |
4685 | /* Builtin not supported on this processor. */ | |
4686 | return 0; | |
4687 | ||
20e26713 AH |
4688 | /* If we got invalid arguments bail out before generating bad rtl. */ |
4689 | if (arg0 == error_mark_node | |
4690 | || arg1 == error_mark_node | |
4691 | || arg2 == error_mark_node) | |
9a171fcd | 4692 | return const0_rtx; |
20e26713 | 4693 | |
774b5662 DE |
4694 | if (icode == CODE_FOR_altivec_vsldoi_4sf |
4695 | || icode == CODE_FOR_altivec_vsldoi_4si | |
4696 | || icode == CODE_FOR_altivec_vsldoi_8hi | |
4697 | || icode == CODE_FOR_altivec_vsldoi_16qi) | |
b44140e7 AH |
4698 | { |
4699 | /* Only allow 4-bit unsigned literals. */ | |
b44140e7 AH |
4700 | if (TREE_CODE (arg2) != INTEGER_CST |
4701 | || TREE_INT_CST_LOW (arg2) & ~0xf) | |
4702 | { | |
4703 | error ("argument 3 must be a 4-bit unsigned literal"); | |
e3277ffb | 4704 | return const0_rtx; |
b44140e7 | 4705 | } |
b44140e7 AH |
4706 | } |
4707 | ||
c62f2db5 | 4708 | if (target == 0 |
2212663f DB |
4709 | || GET_MODE (target) != tmode |
4710 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
4711 | target = gen_reg_rtx (tmode); | |
4712 | ||
4713 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) | |
4714 | op0 = copy_to_mode_reg (mode0, op0); | |
4715 | if (! (*insn_data[icode].operand[2].predicate) (op1, mode1)) | |
4716 | op1 = copy_to_mode_reg (mode1, op1); | |
4717 | if (! (*insn_data[icode].operand[3].predicate) (op2, mode2)) | |
4718 | op2 = copy_to_mode_reg (mode2, op2); | |
4719 | ||
4720 | pat = GEN_FCN (icode) (target, op0, op1, op2); | |
4721 | if (! pat) | |
4722 | return 0; | |
4723 | emit_insn (pat); | |
4724 | ||
4725 | return target; | |
4726 | } | |
92898235 | 4727 | |
3a9b8c7e | 4728 | /* Expand the lvx builtins. */ |
0ac081f6 | 4729 | static rtx |
3a9b8c7e | 4730 | altivec_expand_ld_builtin (exp, target, expandedp) |
0ac081f6 AH |
4731 | tree exp; |
4732 | rtx target; | |
92898235 | 4733 | bool *expandedp; |
0ac081f6 | 4734 | { |
0ac081f6 AH |
4735 | tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0); |
4736 | tree arglist = TREE_OPERAND (exp, 1); | |
0ac081f6 | 4737 | unsigned int fcode = DECL_FUNCTION_CODE (fndecl); |
3a9b8c7e AH |
4738 | tree arg0; |
4739 | enum machine_mode tmode, mode0; | |
7c3abc73 | 4740 | rtx pat, op0; |
3a9b8c7e | 4741 | enum insn_code icode; |
92898235 | 4742 | |
0ac081f6 AH |
4743 | switch (fcode) |
4744 | { | |
f18c054f DB |
4745 | case ALTIVEC_BUILTIN_LD_INTERNAL_16qi: |
4746 | icode = CODE_FOR_altivec_lvx_16qi; | |
3a9b8c7e | 4747 | break; |
f18c054f DB |
4748 | case ALTIVEC_BUILTIN_LD_INTERNAL_8hi: |
4749 | icode = CODE_FOR_altivec_lvx_8hi; | |
3a9b8c7e AH |
4750 | break; |
4751 | case ALTIVEC_BUILTIN_LD_INTERNAL_4si: | |
4752 | icode = CODE_FOR_altivec_lvx_4si; | |
4753 | break; | |
4754 | case ALTIVEC_BUILTIN_LD_INTERNAL_4sf: | |
4755 | icode = CODE_FOR_altivec_lvx_4sf; | |
4756 | break; | |
4757 | default: | |
4758 | *expandedp = false; | |
4759 | return NULL_RTX; | |
4760 | } | |
0ac081f6 | 4761 | |
3a9b8c7e | 4762 | *expandedp = true; |
f18c054f | 4763 | |
3a9b8c7e AH |
4764 | arg0 = TREE_VALUE (arglist); |
4765 | op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
4766 | tmode = insn_data[icode].operand[0].mode; | |
4767 | mode0 = insn_data[icode].operand[1].mode; | |
f18c054f | 4768 | |
3a9b8c7e AH |
4769 | if (target == 0 |
4770 | || GET_MODE (target) != tmode | |
4771 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
4772 | target = gen_reg_rtx (tmode); | |
24408032 | 4773 | |
3a9b8c7e AH |
4774 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) |
4775 | op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0)); | |
f18c054f | 4776 | |
3a9b8c7e AH |
4777 | pat = GEN_FCN (icode) (target, op0); |
4778 | if (! pat) | |
4779 | return 0; | |
4780 | emit_insn (pat); | |
4781 | return target; | |
4782 | } | |
f18c054f | 4783 | |
3a9b8c7e AH |
4784 | /* Expand the stvx builtins. */ |
4785 | static rtx | |
4786 | altivec_expand_st_builtin (exp, target, expandedp) | |
4787 | tree exp; | |
7c3abc73 | 4788 | rtx target ATTRIBUTE_UNUSED; |
3a9b8c7e AH |
4789 | bool *expandedp; |
4790 | { | |
4791 | tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0); | |
4792 | tree arglist = TREE_OPERAND (exp, 1); | |
4793 | unsigned int fcode = DECL_FUNCTION_CODE (fndecl); | |
4794 | tree arg0, arg1; | |
4795 | enum machine_mode mode0, mode1; | |
7c3abc73 | 4796 | rtx pat, op0, op1; |
3a9b8c7e | 4797 | enum insn_code icode; |
f18c054f | 4798 | |
3a9b8c7e AH |
4799 | switch (fcode) |
4800 | { | |
4801 | case ALTIVEC_BUILTIN_ST_INTERNAL_16qi: | |
4802 | icode = CODE_FOR_altivec_stvx_16qi; | |
4803 | break; | |
4804 | case ALTIVEC_BUILTIN_ST_INTERNAL_8hi: | |
4805 | icode = CODE_FOR_altivec_stvx_8hi; | |
4806 | break; | |
4807 | case ALTIVEC_BUILTIN_ST_INTERNAL_4si: | |
4808 | icode = CODE_FOR_altivec_stvx_4si; | |
4809 | break; | |
4810 | case ALTIVEC_BUILTIN_ST_INTERNAL_4sf: | |
4811 | icode = CODE_FOR_altivec_stvx_4sf; | |
4812 | break; | |
4813 | default: | |
4814 | *expandedp = false; | |
4815 | return NULL_RTX; | |
4816 | } | |
24408032 | 4817 | |
3a9b8c7e AH |
4818 | arg0 = TREE_VALUE (arglist); |
4819 | arg1 = TREE_VALUE (TREE_CHAIN (arglist)); | |
4820 | op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
4821 | op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); | |
4822 | mode0 = insn_data[icode].operand[0].mode; | |
4823 | mode1 = insn_data[icode].operand[1].mode; | |
f18c054f | 4824 | |
3a9b8c7e AH |
4825 | if (! (*insn_data[icode].operand[0].predicate) (op0, mode0)) |
4826 | op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0)); | |
4827 | if (! (*insn_data[icode].operand[1].predicate) (op1, mode1)) | |
4828 | op1 = copy_to_mode_reg (mode1, op1); | |
f18c054f | 4829 | |
3a9b8c7e AH |
4830 | pat = GEN_FCN (icode) (op0, op1); |
4831 | if (pat) | |
4832 | emit_insn (pat); | |
f18c054f | 4833 | |
3a9b8c7e AH |
4834 | *expandedp = true; |
4835 | return NULL_RTX; | |
4836 | } | |
f18c054f | 4837 | |
3a9b8c7e AH |
4838 | /* Expand the dst builtins. */ |
4839 | static rtx | |
4840 | altivec_expand_dst_builtin (exp, target, expandedp) | |
4841 | tree exp; | |
7c3abc73 | 4842 | rtx target ATTRIBUTE_UNUSED; |
3a9b8c7e AH |
4843 | bool *expandedp; |
4844 | { | |
4845 | tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0); | |
4846 | tree arglist = TREE_OPERAND (exp, 1); | |
4847 | unsigned int fcode = DECL_FUNCTION_CODE (fndecl); | |
4848 | tree arg0, arg1, arg2; | |
4849 | enum machine_mode mode0, mode1, mode2; | |
7c3abc73 | 4850 | rtx pat, op0, op1, op2; |
3a9b8c7e | 4851 | struct builtin_description *d; |
a3170dc6 | 4852 | size_t i; |
f18c054f | 4853 | |
3a9b8c7e | 4854 | *expandedp = false; |
f18c054f | 4855 | |
3a9b8c7e AH |
4856 | /* Handle DST variants. */ |
4857 | d = (struct builtin_description *) bdesc_dst; | |
4858 | for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++) | |
4859 | if (d->code == fcode) | |
4860 | { | |
4861 | arg0 = TREE_VALUE (arglist); | |
4862 | arg1 = TREE_VALUE (TREE_CHAIN (arglist)); | |
4863 | arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist))); | |
4864 | op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
4865 | op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); | |
4866 | op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0); | |
4867 | mode0 = insn_data[d->icode].operand[0].mode; | |
4868 | mode1 = insn_data[d->icode].operand[1].mode; | |
4869 | mode2 = insn_data[d->icode].operand[2].mode; | |
24408032 | 4870 | |
3a9b8c7e AH |
4871 | /* Invalid arguments, bail out before generating bad rtl. */ |
4872 | if (arg0 == error_mark_node | |
4873 | || arg1 == error_mark_node | |
4874 | || arg2 == error_mark_node) | |
4875 | return const0_rtx; | |
f18c054f | 4876 | |
3a9b8c7e AH |
4877 | if (TREE_CODE (arg2) != INTEGER_CST |
4878 | || TREE_INT_CST_LOW (arg2) & ~0x3) | |
4879 | { | |
4880 | error ("argument to `%s' must be a 2-bit unsigned literal", d->name); | |
4881 | return const0_rtx; | |
4882 | } | |
f18c054f | 4883 | |
3a9b8c7e AH |
4884 | if (! (*insn_data[d->icode].operand[0].predicate) (op0, mode0)) |
4885 | op0 = copy_to_mode_reg (mode0, op0); | |
4886 | if (! (*insn_data[d->icode].operand[1].predicate) (op1, mode1)) | |
4887 | op1 = copy_to_mode_reg (mode1, op1); | |
24408032 | 4888 | |
3a9b8c7e AH |
4889 | pat = GEN_FCN (d->icode) (op0, op1, op2); |
4890 | if (pat != 0) | |
4891 | emit_insn (pat); | |
f18c054f | 4892 | |
3a9b8c7e AH |
4893 | *expandedp = true; |
4894 | return NULL_RTX; | |
4895 | } | |
f18c054f | 4896 | |
3a9b8c7e AH |
4897 | return NULL_RTX; |
4898 | } | |
24408032 | 4899 | |
3a9b8c7e AH |
4900 | /* Expand the builtin in EXP and store the result in TARGET. Store |
4901 | true in *EXPANDEDP if we found a builtin to expand. */ | |
4902 | static rtx | |
4903 | altivec_expand_builtin (exp, target, expandedp) | |
4904 | tree exp; | |
4905 | rtx target; | |
4906 | bool *expandedp; | |
4907 | { | |
4908 | struct builtin_description *d; | |
4909 | struct builtin_description_predicates *dp; | |
4910 | size_t i; | |
4911 | enum insn_code icode; | |
4912 | tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0); | |
4913 | tree arglist = TREE_OPERAND (exp, 1); | |
7c3abc73 AH |
4914 | tree arg0; |
4915 | rtx op0, pat; | |
4916 | enum machine_mode tmode, mode0; | |
3a9b8c7e | 4917 | unsigned int fcode = DECL_FUNCTION_CODE (fndecl); |
0ac081f6 | 4918 | |
3a9b8c7e AH |
4919 | target = altivec_expand_ld_builtin (exp, target, expandedp); |
4920 | if (*expandedp) | |
4921 | return target; | |
0ac081f6 | 4922 | |
3a9b8c7e AH |
4923 | target = altivec_expand_st_builtin (exp, target, expandedp); |
4924 | if (*expandedp) | |
4925 | return target; | |
4926 | ||
4927 | target = altivec_expand_dst_builtin (exp, target, expandedp); | |
4928 | if (*expandedp) | |
4929 | return target; | |
4930 | ||
4931 | *expandedp = true; | |
95385cbb | 4932 | |
3a9b8c7e AH |
4933 | switch (fcode) |
4934 | { | |
6525c0e7 AH |
4935 | case ALTIVEC_BUILTIN_STVX: |
4936 | return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx, arglist); | |
4937 | case ALTIVEC_BUILTIN_STVEBX: | |
4938 | return altivec_expand_stv_builtin (CODE_FOR_altivec_stvebx, arglist); | |
4939 | case ALTIVEC_BUILTIN_STVEHX: | |
4940 | return altivec_expand_stv_builtin (CODE_FOR_altivec_stvehx, arglist); | |
4941 | case ALTIVEC_BUILTIN_STVEWX: | |
4942 | return altivec_expand_stv_builtin (CODE_FOR_altivec_stvewx, arglist); | |
4943 | case ALTIVEC_BUILTIN_STVXL: | |
4944 | return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl, arglist); | |
3a9b8c7e | 4945 | |
95385cbb AH |
4946 | case ALTIVEC_BUILTIN_MFVSCR: |
4947 | icode = CODE_FOR_altivec_mfvscr; | |
4948 | tmode = insn_data[icode].operand[0].mode; | |
4949 | ||
4950 | if (target == 0 | |
4951 | || GET_MODE (target) != tmode | |
4952 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
4953 | target = gen_reg_rtx (tmode); | |
4954 | ||
4955 | pat = GEN_FCN (icode) (target); | |
0ac081f6 AH |
4956 | if (! pat) |
4957 | return 0; | |
4958 | emit_insn (pat); | |
95385cbb AH |
4959 | return target; |
4960 | ||
4961 | case ALTIVEC_BUILTIN_MTVSCR: | |
4962 | icode = CODE_FOR_altivec_mtvscr; | |
4963 | arg0 = TREE_VALUE (arglist); | |
4964 | op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
4965 | mode0 = insn_data[icode].operand[0].mode; | |
4966 | ||
4967 | /* If we got invalid arguments bail out before generating bad rtl. */ | |
4968 | if (arg0 == error_mark_node) | |
9a171fcd | 4969 | return const0_rtx; |
95385cbb AH |
4970 | |
4971 | if (! (*insn_data[icode].operand[0].predicate) (op0, mode0)) | |
4972 | op0 = copy_to_mode_reg (mode0, op0); | |
4973 | ||
4974 | pat = GEN_FCN (icode) (op0); | |
4975 | if (pat) | |
4976 | emit_insn (pat); | |
4977 | return NULL_RTX; | |
3a9b8c7e | 4978 | |
95385cbb AH |
4979 | case ALTIVEC_BUILTIN_DSSALL: |
4980 | emit_insn (gen_altivec_dssall ()); | |
4981 | return NULL_RTX; | |
4982 | ||
4983 | case ALTIVEC_BUILTIN_DSS: | |
4984 | icode = CODE_FOR_altivec_dss; | |
4985 | arg0 = TREE_VALUE (arglist); | |
4986 | op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
4987 | mode0 = insn_data[icode].operand[0].mode; | |
4988 | ||
4989 | /* If we got invalid arguments bail out before generating bad rtl. */ | |
4990 | if (arg0 == error_mark_node) | |
9a171fcd | 4991 | return const0_rtx; |
95385cbb | 4992 | |
b44140e7 AH |
4993 | if (TREE_CODE (arg0) != INTEGER_CST |
4994 | || TREE_INT_CST_LOW (arg0) & ~0x3) | |
4995 | { | |
4996 | error ("argument to dss must be a 2-bit unsigned literal"); | |
9a171fcd | 4997 | return const0_rtx; |
b44140e7 AH |
4998 | } |
4999 | ||
95385cbb AH |
5000 | if (! (*insn_data[icode].operand[0].predicate) (op0, mode0)) |
5001 | op0 = copy_to_mode_reg (mode0, op0); | |
5002 | ||
5003 | emit_insn (gen_altivec_dss (op0)); | |
0ac081f6 AH |
5004 | return NULL_RTX; |
5005 | } | |
24408032 | 5006 | |
100c4561 AH |
5007 | /* Expand abs* operations. */ |
5008 | d = (struct builtin_description *) bdesc_abs; | |
ca7558fc | 5009 | for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++) |
100c4561 AH |
5010 | if (d->code == fcode) |
5011 | return altivec_expand_abs_builtin (d->icode, arglist, target); | |
5012 | ||
ae4b4a02 AH |
5013 | /* Expand the AltiVec predicates. */ |
5014 | dp = (struct builtin_description_predicates *) bdesc_altivec_preds; | |
ca7558fc | 5015 | for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, dp++) |
ae4b4a02 AH |
5016 | if (dp->code == fcode) |
5017 | return altivec_expand_predicate_builtin (dp->icode, dp->opcode, arglist, target); | |
5018 | ||
6525c0e7 AH |
5019 | /* LV* are funky. We initialized them differently. */ |
5020 | switch (fcode) | |
5021 | { | |
5022 | case ALTIVEC_BUILTIN_LVSL: | |
92898235 | 5023 | return rs6000_expand_binop_builtin (CODE_FOR_altivec_lvsl, |
6525c0e7 AH |
5024 | arglist, target); |
5025 | case ALTIVEC_BUILTIN_LVSR: | |
92898235 AH |
5026 | return rs6000_expand_binop_builtin (CODE_FOR_altivec_lvsr, |
5027 | arglist, target); | |
6525c0e7 | 5028 | case ALTIVEC_BUILTIN_LVEBX: |
92898235 AH |
5029 | return rs6000_expand_binop_builtin (CODE_FOR_altivec_lvebx, |
5030 | arglist, target); | |
6525c0e7 | 5031 | case ALTIVEC_BUILTIN_LVEHX: |
92898235 AH |
5032 | return rs6000_expand_binop_builtin (CODE_FOR_altivec_lvehx, |
5033 | arglist, target); | |
6525c0e7 | 5034 | case ALTIVEC_BUILTIN_LVEWX: |
92898235 AH |
5035 | return rs6000_expand_binop_builtin (CODE_FOR_altivec_lvewx, |
5036 | arglist, target); | |
6525c0e7 | 5037 | case ALTIVEC_BUILTIN_LVXL: |
92898235 AH |
5038 | return rs6000_expand_binop_builtin (CODE_FOR_altivec_lvxl, |
5039 | arglist, target); | |
6525c0e7 | 5040 | case ALTIVEC_BUILTIN_LVX: |
92898235 AH |
5041 | return rs6000_expand_binop_builtin (CODE_FOR_altivec_lvx, |
5042 | arglist, target); | |
6525c0e7 AH |
5043 | default: |
5044 | break; | |
5045 | /* Fall through. */ | |
5046 | } | |
95385cbb | 5047 | |
92898235 | 5048 | *expandedp = false; |
0ac081f6 AH |
5049 | return NULL_RTX; |
5050 | } | |
5051 | ||
a3170dc6 AH |
5052 | /* Binops that need to be initialized manually, but can be expanded |
5053 | automagically by rs6000_expand_binop_builtin. */ | |
5054 | static struct builtin_description bdesc_2arg_spe[] = | |
5055 | { | |
5056 | { 0, CODE_FOR_spe_evlddx, "__builtin_spe_evlddx", SPE_BUILTIN_EVLDDX }, | |
5057 | { 0, CODE_FOR_spe_evldwx, "__builtin_spe_evldwx", SPE_BUILTIN_EVLDWX }, | |
5058 | { 0, CODE_FOR_spe_evldhx, "__builtin_spe_evldhx", SPE_BUILTIN_EVLDHX }, | |
5059 | { 0, CODE_FOR_spe_evlwhex, "__builtin_spe_evlwhex", SPE_BUILTIN_EVLWHEX }, | |
5060 | { 0, CODE_FOR_spe_evlwhoux, "__builtin_spe_evlwhoux", SPE_BUILTIN_EVLWHOUX }, | |
5061 | { 0, CODE_FOR_spe_evlwhosx, "__builtin_spe_evlwhosx", SPE_BUILTIN_EVLWHOSX }, | |
5062 | { 0, CODE_FOR_spe_evlwwsplatx, "__builtin_spe_evlwwsplatx", SPE_BUILTIN_EVLWWSPLATX }, | |
5063 | { 0, CODE_FOR_spe_evlwhsplatx, "__builtin_spe_evlwhsplatx", SPE_BUILTIN_EVLWHSPLATX }, | |
5064 | { 0, CODE_FOR_spe_evlhhesplatx, "__builtin_spe_evlhhesplatx", SPE_BUILTIN_EVLHHESPLATX }, | |
5065 | { 0, CODE_FOR_spe_evlhhousplatx, "__builtin_spe_evlhhousplatx", SPE_BUILTIN_EVLHHOUSPLATX }, | |
5066 | { 0, CODE_FOR_spe_evlhhossplatx, "__builtin_spe_evlhhossplatx", SPE_BUILTIN_EVLHHOSSPLATX }, | |
5067 | { 0, CODE_FOR_spe_evldd, "__builtin_spe_evldd", SPE_BUILTIN_EVLDD }, | |
5068 | { 0, CODE_FOR_spe_evldw, "__builtin_spe_evldw", SPE_BUILTIN_EVLDW }, | |
5069 | { 0, CODE_FOR_spe_evldh, "__builtin_spe_evldh", SPE_BUILTIN_EVLDH }, | |
5070 | { 0, CODE_FOR_spe_evlwhe, "__builtin_spe_evlwhe", SPE_BUILTIN_EVLWHE }, | |
5071 | { 0, CODE_FOR_spe_evlwhou, "__builtin_spe_evlwhou", SPE_BUILTIN_EVLWHOU }, | |
5072 | { 0, CODE_FOR_spe_evlwhos, "__builtin_spe_evlwhos", SPE_BUILTIN_EVLWHOS }, | |
5073 | { 0, CODE_FOR_spe_evlwwsplat, "__builtin_spe_evlwwsplat", SPE_BUILTIN_EVLWWSPLAT }, | |
5074 | { 0, CODE_FOR_spe_evlwhsplat, "__builtin_spe_evlwhsplat", SPE_BUILTIN_EVLWHSPLAT }, | |
5075 | { 0, CODE_FOR_spe_evlhhesplat, "__builtin_spe_evlhhesplat", SPE_BUILTIN_EVLHHESPLAT }, | |
5076 | { 0, CODE_FOR_spe_evlhhousplat, "__builtin_spe_evlhhousplat", SPE_BUILTIN_EVLHHOUSPLAT }, | |
5077 | { 0, CODE_FOR_spe_evlhhossplat, "__builtin_spe_evlhhossplat", SPE_BUILTIN_EVLHHOSSPLAT } | |
5078 | }; | |
5079 | ||
5080 | /* Expand the builtin in EXP and store the result in TARGET. Store | |
5081 | true in *EXPANDEDP if we found a builtin to expand. | |
5082 | ||
5083 | This expands the SPE builtins that are not simple unary and binary | |
5084 | operations. */ | |
5085 | static rtx | |
5086 | spe_expand_builtin (exp, target, expandedp) | |
5087 | tree exp; | |
5088 | rtx target; | |
5089 | bool *expandedp; | |
5090 | { | |
5091 | tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0); | |
5092 | tree arglist = TREE_OPERAND (exp, 1); | |
5093 | tree arg1, arg0; | |
5094 | unsigned int fcode = DECL_FUNCTION_CODE (fndecl); | |
5095 | enum insn_code icode; | |
5096 | enum machine_mode tmode, mode0; | |
5097 | rtx pat, op0; | |
5098 | struct builtin_description *d; | |
5099 | size_t i; | |
5100 | ||
5101 | *expandedp = true; | |
5102 | ||
5103 | /* Syntax check for a 5-bit unsigned immediate. */ | |
5104 | switch (fcode) | |
5105 | { | |
5106 | case SPE_BUILTIN_EVSTDD: | |
5107 | case SPE_BUILTIN_EVSTDH: | |
5108 | case SPE_BUILTIN_EVSTDW: | |
5109 | case SPE_BUILTIN_EVSTWHE: | |
5110 | case SPE_BUILTIN_EVSTWHO: | |
5111 | case SPE_BUILTIN_EVSTWWE: | |
5112 | case SPE_BUILTIN_EVSTWWO: | |
5113 | arg1 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist))); | |
5114 | if (TREE_CODE (arg1) != INTEGER_CST | |
5115 | || TREE_INT_CST_LOW (arg1) & ~0x1f) | |
5116 | { | |
5117 | error ("argument 2 must be a 5-bit unsigned literal"); | |
5118 | return const0_rtx; | |
5119 | } | |
5120 | break; | |
5121 | default: | |
5122 | break; | |
5123 | } | |
5124 | ||
5125 | d = (struct builtin_description *) bdesc_2arg_spe; | |
5126 | for (i = 0; i < ARRAY_SIZE (bdesc_2arg_spe); ++i, ++d) | |
5127 | if (d->code == fcode) | |
5128 | return rs6000_expand_binop_builtin (d->icode, arglist, target); | |
5129 | ||
5130 | d = (struct builtin_description *) bdesc_spe_predicates; | |
5131 | for (i = 0; i < ARRAY_SIZE (bdesc_spe_predicates); ++i, ++d) | |
5132 | if (d->code == fcode) | |
5133 | return spe_expand_predicate_builtin (d->icode, arglist, target); | |
5134 | ||
5135 | d = (struct builtin_description *) bdesc_spe_evsel; | |
5136 | for (i = 0; i < ARRAY_SIZE (bdesc_spe_evsel); ++i, ++d) | |
5137 | if (d->code == fcode) | |
5138 | return spe_expand_evsel_builtin (d->icode, arglist, target); | |
5139 | ||
5140 | switch (fcode) | |
5141 | { | |
5142 | case SPE_BUILTIN_EVSTDDX: | |
5143 | return altivec_expand_stv_builtin (CODE_FOR_spe_evstddx, arglist); | |
5144 | case SPE_BUILTIN_EVSTDHX: | |
5145 | return altivec_expand_stv_builtin (CODE_FOR_spe_evstdhx, arglist); | |
5146 | case SPE_BUILTIN_EVSTDWX: | |
5147 | return altivec_expand_stv_builtin (CODE_FOR_spe_evstdwx, arglist); | |
5148 | case SPE_BUILTIN_EVSTWHEX: | |
5149 | return altivec_expand_stv_builtin (CODE_FOR_spe_evstwhex, arglist); | |
5150 | case SPE_BUILTIN_EVSTWHOX: | |
5151 | return altivec_expand_stv_builtin (CODE_FOR_spe_evstwhox, arglist); | |
5152 | case SPE_BUILTIN_EVSTWWEX: | |
5153 | return altivec_expand_stv_builtin (CODE_FOR_spe_evstwwex, arglist); | |
5154 | case SPE_BUILTIN_EVSTWWOX: | |
5155 | return altivec_expand_stv_builtin (CODE_FOR_spe_evstwwox, arglist); | |
5156 | case SPE_BUILTIN_EVSTDD: | |
5157 | return altivec_expand_stv_builtin (CODE_FOR_spe_evstdd, arglist); | |
5158 | case SPE_BUILTIN_EVSTDH: | |
5159 | return altivec_expand_stv_builtin (CODE_FOR_spe_evstdh, arglist); | |
5160 | case SPE_BUILTIN_EVSTDW: | |
5161 | return altivec_expand_stv_builtin (CODE_FOR_spe_evstdw, arglist); | |
5162 | case SPE_BUILTIN_EVSTWHE: | |
5163 | return altivec_expand_stv_builtin (CODE_FOR_spe_evstwhe, arglist); | |
5164 | case SPE_BUILTIN_EVSTWHO: | |
5165 | return altivec_expand_stv_builtin (CODE_FOR_spe_evstwho, arglist); | |
5166 | case SPE_BUILTIN_EVSTWWE: | |
5167 | return altivec_expand_stv_builtin (CODE_FOR_spe_evstwwe, arglist); | |
5168 | case SPE_BUILTIN_EVSTWWO: | |
5169 | return altivec_expand_stv_builtin (CODE_FOR_spe_evstwwo, arglist); | |
5170 | case SPE_BUILTIN_MFSPEFSCR: | |
5171 | icode = CODE_FOR_spe_mfspefscr; | |
5172 | tmode = insn_data[icode].operand[0].mode; | |
5173 | ||
5174 | if (target == 0 | |
5175 | || GET_MODE (target) != tmode | |
5176 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
5177 | target = gen_reg_rtx (tmode); | |
5178 | ||
5179 | pat = GEN_FCN (icode) (target); | |
5180 | if (! pat) | |
5181 | return 0; | |
5182 | emit_insn (pat); | |
5183 | return target; | |
5184 | case SPE_BUILTIN_MTSPEFSCR: | |
5185 | icode = CODE_FOR_spe_mtspefscr; | |
5186 | arg0 = TREE_VALUE (arglist); | |
5187 | op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
5188 | mode0 = insn_data[icode].operand[0].mode; | |
5189 | ||
5190 | if (arg0 == error_mark_node) | |
5191 | return const0_rtx; | |
5192 | ||
5193 | if (! (*insn_data[icode].operand[0].predicate) (op0, mode0)) | |
5194 | op0 = copy_to_mode_reg (mode0, op0); | |
5195 | ||
5196 | pat = GEN_FCN (icode) (op0); | |
5197 | if (pat) | |
5198 | emit_insn (pat); | |
5199 | return NULL_RTX; | |
5200 | default: | |
5201 | break; | |
5202 | } | |
5203 | ||
5204 | *expandedp = false; | |
5205 | return NULL_RTX; | |
5206 | } | |
5207 | ||
5208 | static rtx | |
5209 | spe_expand_predicate_builtin (icode, arglist, target) | |
5210 | enum insn_code icode; | |
5211 | tree arglist; | |
5212 | rtx target; | |
5213 | { | |
5214 | rtx pat, scratch, tmp; | |
5215 | tree form = TREE_VALUE (arglist); | |
5216 | tree arg0 = TREE_VALUE (TREE_CHAIN (arglist)); | |
5217 | tree arg1 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist))); | |
5218 | rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
5219 | rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); | |
5220 | enum machine_mode mode0 = insn_data[icode].operand[1].mode; | |
5221 | enum machine_mode mode1 = insn_data[icode].operand[2].mode; | |
5222 | int form_int; | |
5223 | enum rtx_code code; | |
5224 | ||
5225 | if (TREE_CODE (form) != INTEGER_CST) | |
5226 | { | |
5227 | error ("argument 1 of __builtin_spe_predicate must be a constant"); | |
5228 | return const0_rtx; | |
5229 | } | |
5230 | else | |
5231 | form_int = TREE_INT_CST_LOW (form); | |
5232 | ||
5233 | if (mode0 != mode1) | |
5234 | abort (); | |
5235 | ||
5236 | if (arg0 == error_mark_node || arg1 == error_mark_node) | |
5237 | return const0_rtx; | |
5238 | ||
5239 | if (target == 0 | |
5240 | || GET_MODE (target) != SImode | |
5241 | || ! (*insn_data[icode].operand[0].predicate) (target, SImode)) | |
5242 | target = gen_reg_rtx (SImode); | |
5243 | ||
5244 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) | |
5245 | op0 = copy_to_mode_reg (mode0, op0); | |
5246 | if (! (*insn_data[icode].operand[2].predicate) (op1, mode1)) | |
5247 | op1 = copy_to_mode_reg (mode1, op1); | |
5248 | ||
5249 | scratch = gen_reg_rtx (CCmode); | |
5250 | ||
5251 | pat = GEN_FCN (icode) (scratch, op0, op1); | |
5252 | if (! pat) | |
5253 | return const0_rtx; | |
5254 | emit_insn (pat); | |
5255 | ||
5256 | /* There are 4 variants for each predicate: _any_, _all_, _upper_, | |
5257 | _lower_. We use one compare, but look in different bits of the | |
5258 | CR for each variant. | |
5259 | ||
5260 | There are 2 elements in each SPE simd type (upper/lower). The CR | |
5261 | bits are set as follows: | |
5262 | ||
5263 | BIT0 | BIT 1 | BIT 2 | BIT 3 | |
5264 | U | L | (U | L) | (U & L) | |
5265 | ||
5266 | So, for an "all" relationship, BIT 3 would be set. | |
5267 | For an "any" relationship, BIT 2 would be set. Etc. | |
5268 | ||
5269 | Following traditional nomenclature, these bits map to: | |
5270 | ||
5271 | BIT0 | BIT 1 | BIT 2 | BIT 3 | |
5272 | LT | GT | EQ | OV | |
5273 | ||
5274 | Later, we will generate rtl to look in the LT/EQ/EQ/OV bits. | |
5275 | */ | |
5276 | ||
5277 | switch (form_int) | |
5278 | { | |
5279 | /* All variant. OV bit. */ | |
5280 | case 0: | |
5281 | /* We need to get to the OV bit, which is the ORDERED bit. We | |
5282 | could generate (ordered:SI (reg:CC xx) (const_int 0)), but | |
5283 | that's ugly and will trigger a validate_condition_mode abort. | |
5284 | So let's just use another pattern. */ | |
5285 | emit_insn (gen_move_from_CR_ov_bit (target, scratch)); | |
5286 | return target; | |
5287 | /* Any variant. EQ bit. */ | |
5288 | case 1: | |
5289 | code = EQ; | |
5290 | break; | |
5291 | /* Upper variant. LT bit. */ | |
5292 | case 2: | |
5293 | code = LT; | |
5294 | break; | |
5295 | /* Lower variant. GT bit. */ | |
5296 | case 3: | |
5297 | code = GT; | |
5298 | break; | |
5299 | default: | |
5300 | error ("argument 1 of __builtin_spe_predicate is out of range"); | |
5301 | return const0_rtx; | |
5302 | } | |
5303 | ||
5304 | tmp = gen_rtx_fmt_ee (code, SImode, scratch, const0_rtx); | |
5305 | emit_move_insn (target, tmp); | |
5306 | ||
5307 | return target; | |
5308 | } | |
5309 | ||
5310 | /* The evsel builtins look like this: | |
5311 | ||
5312 | e = __builtin_spe_evsel_OP (a, b, c, d); | |
5313 | ||
5314 | and work like this: | |
5315 | ||
5316 | e[upper] = a[upper] *OP* b[upper] ? c[upper] : d[upper]; | |
5317 | e[lower] = a[lower] *OP* b[lower] ? c[lower] : d[lower]; | |
5318 | */ | |
5319 | ||
5320 | static rtx | |
5321 | spe_expand_evsel_builtin (icode, arglist, target) | |
5322 | enum insn_code icode; | |
5323 | tree arglist; | |
5324 | rtx target; | |
5325 | { | |
5326 | rtx pat, scratch; | |
5327 | tree arg0 = TREE_VALUE (arglist); | |
5328 | tree arg1 = TREE_VALUE (TREE_CHAIN (arglist)); | |
5329 | tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist))); | |
5330 | tree arg3 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (TREE_CHAIN (arglist)))); | |
5331 | rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
5332 | rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); | |
5333 | rtx op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0); | |
5334 | rtx op3 = expand_expr (arg3, NULL_RTX, VOIDmode, 0); | |
5335 | enum machine_mode mode0 = insn_data[icode].operand[1].mode; | |
5336 | enum machine_mode mode1 = insn_data[icode].operand[2].mode; | |
5337 | ||
5338 | if (mode0 != mode1) | |
5339 | abort (); | |
5340 | ||
5341 | if (arg0 == error_mark_node || arg1 == error_mark_node | |
5342 | || arg2 == error_mark_node || arg3 == error_mark_node) | |
5343 | return const0_rtx; | |
5344 | ||
5345 | if (target == 0 | |
5346 | || GET_MODE (target) != mode0 | |
5347 | || ! (*insn_data[icode].operand[0].predicate) (target, mode0)) | |
5348 | target = gen_reg_rtx (mode0); | |
5349 | ||
5350 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) | |
5351 | op0 = copy_to_mode_reg (mode0, op0); | |
5352 | if (! (*insn_data[icode].operand[1].predicate) (op1, mode1)) | |
5353 | op1 = copy_to_mode_reg (mode0, op1); | |
5354 | if (! (*insn_data[icode].operand[1].predicate) (op2, mode1)) | |
5355 | op2 = copy_to_mode_reg (mode0, op2); | |
5356 | if (! (*insn_data[icode].operand[1].predicate) (op3, mode1)) | |
5357 | op3 = copy_to_mode_reg (mode0, op3); | |
5358 | ||
5359 | /* Generate the compare. */ | |
5360 | scratch = gen_reg_rtx (CCmode); | |
5361 | pat = GEN_FCN (icode) (scratch, op0, op1); | |
5362 | if (! pat) | |
5363 | return const0_rtx; | |
5364 | emit_insn (pat); | |
5365 | ||
5366 | if (mode0 == V2SImode) | |
5367 | emit_insn (gen_spe_evsel (target, op2, op3, scratch)); | |
5368 | else | |
5369 | emit_insn (gen_spe_evsel_fs (target, op2, op3, scratch)); | |
5370 | ||
5371 | return target; | |
5372 | } | |
5373 | ||
0ac081f6 AH |
5374 | /* Expand an expression EXP that calls a built-in function, |
5375 | with result going to TARGET if that's convenient | |
5376 | (and in mode MODE if that's convenient). | |
5377 | SUBTARGET may be used as the target for computing one of EXP's operands. | |
5378 | IGNORE is nonzero if the value is to be ignored. */ | |
5379 | ||
5380 | static rtx | |
5381 | rs6000_expand_builtin (exp, target, subtarget, mode, ignore) | |
5382 | tree exp; | |
5383 | rtx target; | |
00b960c7 AH |
5384 | rtx subtarget ATTRIBUTE_UNUSED; |
5385 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
5386 | int ignore ATTRIBUTE_UNUSED; | |
0ac081f6 | 5387 | { |
92898235 AH |
5388 | tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0); |
5389 | tree arglist = TREE_OPERAND (exp, 1); | |
5390 | unsigned int fcode = DECL_FUNCTION_CODE (fndecl); | |
5391 | struct builtin_description *d; | |
5392 | size_t i; | |
5393 | rtx ret; | |
5394 | bool success; | |
5395 | ||
0ac081f6 | 5396 | if (TARGET_ALTIVEC) |
92898235 AH |
5397 | { |
5398 | ret = altivec_expand_builtin (exp, target, &success); | |
5399 | ||
a3170dc6 AH |
5400 | if (success) |
5401 | return ret; | |
5402 | } | |
5403 | if (TARGET_SPE) | |
5404 | { | |
5405 | ret = spe_expand_builtin (exp, target, &success); | |
5406 | ||
92898235 AH |
5407 | if (success) |
5408 | return ret; | |
5409 | } | |
5410 | ||
0559cc77 DE |
5411 | if (TARGET_ALTIVEC || TARGET_SPE) |
5412 | { | |
5413 | /* Handle simple unary operations. */ | |
5414 | d = (struct builtin_description *) bdesc_1arg; | |
5415 | for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++) | |
5416 | if (d->code == fcode) | |
5417 | return rs6000_expand_unop_builtin (d->icode, arglist, target); | |
5418 | ||
5419 | /* Handle simple binary operations. */ | |
5420 | d = (struct builtin_description *) bdesc_2arg; | |
5421 | for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++) | |
5422 | if (d->code == fcode) | |
5423 | return rs6000_expand_binop_builtin (d->icode, arglist, target); | |
5424 | ||
5425 | /* Handle simple ternary operations. */ | |
5426 | d = (struct builtin_description *) bdesc_3arg; | |
5427 | for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++) | |
5428 | if (d->code == fcode) | |
5429 | return rs6000_expand_ternop_builtin (d->icode, arglist, target); | |
5430 | } | |
0ac081f6 AH |
5431 | |
5432 | abort (); | |
92898235 | 5433 | return NULL_RTX; |
0ac081f6 AH |
5434 | } |
5435 | ||
5436 | static void | |
6fa3f289 | 5437 | rs6000_init_builtins () |
0ac081f6 | 5438 | { |
3fdaa45a AH |
5439 | opaque_V2SI_type_node = copy_node (V2SI_type_node); |
5440 | opaque_V2SF_type_node = copy_node (V2SF_type_node); | |
5441 | ||
a3170dc6 | 5442 | if (TARGET_SPE) |
3fdaa45a | 5443 | spe_init_builtins (); |
0ac081f6 AH |
5444 | if (TARGET_ALTIVEC) |
5445 | altivec_init_builtins (); | |
0559cc77 DE |
5446 | if (TARGET_ALTIVEC || TARGET_SPE) |
5447 | rs6000_common_init_builtins (); | |
0ac081f6 AH |
5448 | } |
5449 | ||
a3170dc6 AH |
5450 | /* Search through a set of builtins and enable the mask bits. |
5451 | DESC is an array of builtins. | |
b6d08ca1 | 5452 | SIZE is the total number of builtins. |
a3170dc6 AH |
5453 | START is the builtin enum at which to start. |
5454 | END is the builtin enum at which to end. */ | |
0ac081f6 | 5455 | static void |
a3170dc6 AH |
5456 | enable_mask_for_builtins (desc, size, start, end) |
5457 | struct builtin_description *desc; | |
5458 | int size; | |
5459 | enum rs6000_builtins start, end; | |
5460 | { | |
5461 | int i; | |
5462 | ||
5463 | for (i = 0; i < size; ++i) | |
5464 | if (desc[i].code == start) | |
5465 | break; | |
5466 | ||
5467 | if (i == size) | |
5468 | return; | |
5469 | ||
5470 | for (; i < size; ++i) | |
5471 | { | |
5472 | /* Flip all the bits on. */ | |
5473 | desc[i].mask = target_flags; | |
5474 | if (desc[i].code == end) | |
5475 | break; | |
5476 | } | |
5477 | } | |
5478 | ||
5479 | static void | |
b24c9d35 | 5480 | spe_init_builtins () |
0ac081f6 | 5481 | { |
a3170dc6 AH |
5482 | tree endlink = void_list_node; |
5483 | tree puint_type_node = build_pointer_type (unsigned_type_node); | |
5484 | tree pushort_type_node = build_pointer_type (short_unsigned_type_node); | |
3fdaa45a | 5485 | tree pv2si_type_node = build_pointer_type (opaque_V2SI_type_node); |
ae4b4a02 | 5486 | struct builtin_description *d; |
0ac081f6 AH |
5487 | size_t i; |
5488 | ||
a3170dc6 AH |
5489 | tree v2si_ftype_4_v2si |
5490 | = build_function_type | |
3fdaa45a AH |
5491 | (opaque_V2SI_type_node, |
5492 | tree_cons (NULL_TREE, opaque_V2SI_type_node, | |
5493 | tree_cons (NULL_TREE, opaque_V2SI_type_node, | |
5494 | tree_cons (NULL_TREE, opaque_V2SI_type_node, | |
5495 | tree_cons (NULL_TREE, opaque_V2SI_type_node, | |
a3170dc6 AH |
5496 | endlink))))); |
5497 | ||
5498 | tree v2sf_ftype_4_v2sf | |
5499 | = build_function_type | |
3fdaa45a AH |
5500 | (opaque_V2SF_type_node, |
5501 | tree_cons (NULL_TREE, opaque_V2SF_type_node, | |
5502 | tree_cons (NULL_TREE, opaque_V2SF_type_node, | |
5503 | tree_cons (NULL_TREE, opaque_V2SF_type_node, | |
5504 | tree_cons (NULL_TREE, opaque_V2SF_type_node, | |
a3170dc6 AH |
5505 | endlink))))); |
5506 | ||
5507 | tree int_ftype_int_v2si_v2si | |
5508 | = build_function_type | |
5509 | (integer_type_node, | |
5510 | tree_cons (NULL_TREE, integer_type_node, | |
3fdaa45a AH |
5511 | tree_cons (NULL_TREE, opaque_V2SI_type_node, |
5512 | tree_cons (NULL_TREE, opaque_V2SI_type_node, | |
a3170dc6 AH |
5513 | endlink)))); |
5514 | ||
5515 | tree int_ftype_int_v2sf_v2sf | |
5516 | = build_function_type | |
5517 | (integer_type_node, | |
5518 | tree_cons (NULL_TREE, integer_type_node, | |
3fdaa45a AH |
5519 | tree_cons (NULL_TREE, opaque_V2SF_type_node, |
5520 | tree_cons (NULL_TREE, opaque_V2SF_type_node, | |
a3170dc6 AH |
5521 | endlink)))); |
5522 | ||
5523 | tree void_ftype_v2si_puint_int | |
5524 | = build_function_type (void_type_node, | |
3fdaa45a | 5525 | tree_cons (NULL_TREE, opaque_V2SI_type_node, |
a3170dc6 AH |
5526 | tree_cons (NULL_TREE, puint_type_node, |
5527 | tree_cons (NULL_TREE, | |
5528 | integer_type_node, | |
5529 | endlink)))); | |
5530 | ||
5531 | tree void_ftype_v2si_puint_char | |
5532 | = build_function_type (void_type_node, | |
3fdaa45a | 5533 | tree_cons (NULL_TREE, opaque_V2SI_type_node, |
a3170dc6 AH |
5534 | tree_cons (NULL_TREE, puint_type_node, |
5535 | tree_cons (NULL_TREE, | |
5536 | char_type_node, | |
5537 | endlink)))); | |
5538 | ||
5539 | tree void_ftype_v2si_pv2si_int | |
5540 | = build_function_type (void_type_node, | |
3fdaa45a | 5541 | tree_cons (NULL_TREE, opaque_V2SI_type_node, |
a3170dc6 AH |
5542 | tree_cons (NULL_TREE, pv2si_type_node, |
5543 | tree_cons (NULL_TREE, | |
5544 | integer_type_node, | |
5545 | endlink)))); | |
5546 | ||
5547 | tree void_ftype_v2si_pv2si_char | |
5548 | = build_function_type (void_type_node, | |
3fdaa45a | 5549 | tree_cons (NULL_TREE, opaque_V2SI_type_node, |
a3170dc6 AH |
5550 | tree_cons (NULL_TREE, pv2si_type_node, |
5551 | tree_cons (NULL_TREE, | |
5552 | char_type_node, | |
5553 | endlink)))); | |
5554 | ||
5555 | tree void_ftype_int | |
5556 | = build_function_type (void_type_node, | |
5557 | tree_cons (NULL_TREE, integer_type_node, endlink)); | |
5558 | ||
5559 | tree int_ftype_void | |
5560 | = build_function_type (integer_type_node, | |
5561 | tree_cons (NULL_TREE, void_type_node, endlink)); | |
5562 | ||
5563 | tree v2si_ftype_pv2si_int | |
3fdaa45a | 5564 | = build_function_type (opaque_V2SI_type_node, |
a3170dc6 AH |
5565 | tree_cons (NULL_TREE, pv2si_type_node, |
5566 | tree_cons (NULL_TREE, integer_type_node, | |
5567 | endlink))); | |
5568 | ||
5569 | tree v2si_ftype_puint_int | |
3fdaa45a | 5570 | = build_function_type (opaque_V2SI_type_node, |
a3170dc6 AH |
5571 | tree_cons (NULL_TREE, puint_type_node, |
5572 | tree_cons (NULL_TREE, integer_type_node, | |
5573 | endlink))); | |
5574 | ||
5575 | tree v2si_ftype_pushort_int | |
3fdaa45a | 5576 | = build_function_type (opaque_V2SI_type_node, |
a3170dc6 AH |
5577 | tree_cons (NULL_TREE, pushort_type_node, |
5578 | tree_cons (NULL_TREE, integer_type_node, | |
5579 | endlink))); | |
5580 | ||
5581 | /* The initialization of the simple binary and unary builtins is | |
5582 | done in rs6000_common_init_builtins, but we have to enable the | |
5583 | mask bits here manually because we have run out of `target_flags' | |
5584 | bits. We really need to redesign this mask business. */ | |
5585 | ||
5586 | enable_mask_for_builtins ((struct builtin_description *) bdesc_2arg, | |
5587 | ARRAY_SIZE (bdesc_2arg), | |
5588 | SPE_BUILTIN_EVADDW, | |
5589 | SPE_BUILTIN_EVXOR); | |
5590 | enable_mask_for_builtins ((struct builtin_description *) bdesc_1arg, | |
5591 | ARRAY_SIZE (bdesc_1arg), | |
5592 | SPE_BUILTIN_EVABS, | |
5593 | SPE_BUILTIN_EVSUBFUSIAAW); | |
5594 | enable_mask_for_builtins ((struct builtin_description *) bdesc_spe_predicates, | |
5595 | ARRAY_SIZE (bdesc_spe_predicates), | |
5596 | SPE_BUILTIN_EVCMPEQ, | |
5597 | SPE_BUILTIN_EVFSTSTLT); | |
5598 | enable_mask_for_builtins ((struct builtin_description *) bdesc_spe_evsel, | |
5599 | ARRAY_SIZE (bdesc_spe_evsel), | |
5600 | SPE_BUILTIN_EVSEL_CMPGTS, | |
5601 | SPE_BUILTIN_EVSEL_FSTSTEQ); | |
5602 | ||
5603 | /* Initialize irregular SPE builtins. */ | |
5604 | ||
5605 | def_builtin (target_flags, "__builtin_spe_mtspefscr", void_ftype_int, SPE_BUILTIN_MTSPEFSCR); | |
5606 | def_builtin (target_flags, "__builtin_spe_mfspefscr", int_ftype_void, SPE_BUILTIN_MFSPEFSCR); | |
5607 | def_builtin (target_flags, "__builtin_spe_evstddx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDDX); | |
5608 | def_builtin (target_flags, "__builtin_spe_evstdhx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDHX); | |
5609 | def_builtin (target_flags, "__builtin_spe_evstdwx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDWX); | |
5610 | def_builtin (target_flags, "__builtin_spe_evstwhex", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWHEX); | |
5611 | def_builtin (target_flags, "__builtin_spe_evstwhox", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWHOX); | |
5612 | def_builtin (target_flags, "__builtin_spe_evstwwex", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWWEX); | |
5613 | def_builtin (target_flags, "__builtin_spe_evstwwox", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWWOX); | |
5614 | def_builtin (target_flags, "__builtin_spe_evstdd", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDD); | |
5615 | def_builtin (target_flags, "__builtin_spe_evstdh", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDH); | |
5616 | def_builtin (target_flags, "__builtin_spe_evstdw", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDW); | |
5617 | def_builtin (target_flags, "__builtin_spe_evstwhe", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWHE); | |
5618 | def_builtin (target_flags, "__builtin_spe_evstwho", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWHO); | |
5619 | def_builtin (target_flags, "__builtin_spe_evstwwe", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWWE); | |
5620 | def_builtin (target_flags, "__builtin_spe_evstwwo", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWWO); | |
5621 | ||
5622 | /* Loads. */ | |
5623 | def_builtin (target_flags, "__builtin_spe_evlddx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDDX); | |
5624 | def_builtin (target_flags, "__builtin_spe_evldwx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDWX); | |
5625 | def_builtin (target_flags, "__builtin_spe_evldhx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDHX); | |
5626 | def_builtin (target_flags, "__builtin_spe_evlwhex", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHEX); | |
5627 | def_builtin (target_flags, "__builtin_spe_evlwhoux", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOUX); | |
5628 | def_builtin (target_flags, "__builtin_spe_evlwhosx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOSX); | |
5629 | def_builtin (target_flags, "__builtin_spe_evlwwsplatx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWWSPLATX); | |
5630 | def_builtin (target_flags, "__builtin_spe_evlwhsplatx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHSPLATX); | |
5631 | def_builtin (target_flags, "__builtin_spe_evlhhesplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHESPLATX); | |
5632 | def_builtin (target_flags, "__builtin_spe_evlhhousplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOUSPLATX); | |
5633 | def_builtin (target_flags, "__builtin_spe_evlhhossplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOSSPLATX); | |
5634 | def_builtin (target_flags, "__builtin_spe_evldd", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDD); | |
5635 | def_builtin (target_flags, "__builtin_spe_evldw", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDW); | |
5636 | def_builtin (target_flags, "__builtin_spe_evldh", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDH); | |
5637 | def_builtin (target_flags, "__builtin_spe_evlhhesplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHESPLAT); | |
5638 | def_builtin (target_flags, "__builtin_spe_evlhhossplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOSSPLAT); | |
5639 | def_builtin (target_flags, "__builtin_spe_evlhhousplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOUSPLAT); | |
5640 | def_builtin (target_flags, "__builtin_spe_evlwhe", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHE); | |
5641 | def_builtin (target_flags, "__builtin_spe_evlwhos", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOS); | |
5642 | def_builtin (target_flags, "__builtin_spe_evlwhou", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOU); | |
5643 | def_builtin (target_flags, "__builtin_spe_evlwhsplat", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHSPLAT); | |
5644 | def_builtin (target_flags, "__builtin_spe_evlwwsplat", v2si_ftype_puint_int, SPE_BUILTIN_EVLWWSPLAT); | |
5645 | ||
5646 | /* Predicates. */ | |
5647 | d = (struct builtin_description *) bdesc_spe_predicates; | |
5648 | for (i = 0; i < ARRAY_SIZE (bdesc_spe_predicates); ++i, d++) | |
5649 | { | |
5650 | tree type; | |
5651 | ||
5652 | switch (insn_data[d->icode].operand[1].mode) | |
5653 | { | |
5654 | case V2SImode: | |
5655 | type = int_ftype_int_v2si_v2si; | |
5656 | break; | |
5657 | case V2SFmode: | |
5658 | type = int_ftype_int_v2sf_v2sf; | |
5659 | break; | |
5660 | default: | |
5661 | abort (); | |
5662 | } | |
5663 | ||
5664 | def_builtin (d->mask, d->name, type, d->code); | |
5665 | } | |
5666 | ||
5667 | /* Evsel predicates. */ | |
5668 | d = (struct builtin_description *) bdesc_spe_evsel; | |
5669 | for (i = 0; i < ARRAY_SIZE (bdesc_spe_evsel); ++i, d++) | |
5670 | { | |
5671 | tree type; | |
5672 | ||
5673 | switch (insn_data[d->icode].operand[1].mode) | |
5674 | { | |
5675 | case V2SImode: | |
5676 | type = v2si_ftype_4_v2si; | |
5677 | break; | |
5678 | case V2SFmode: | |
5679 | type = v2sf_ftype_4_v2sf; | |
5680 | break; | |
5681 | default: | |
5682 | abort (); | |
5683 | } | |
5684 | ||
5685 | def_builtin (d->mask, d->name, type, d->code); | |
5686 | } | |
5687 | } | |
5688 | ||
5689 | static void | |
b24c9d35 | 5690 | altivec_init_builtins () |
a3170dc6 AH |
5691 | { |
5692 | struct builtin_description *d; | |
5693 | struct builtin_description_predicates *dp; | |
5694 | size_t i; | |
5695 | tree pfloat_type_node = build_pointer_type (float_type_node); | |
5696 | tree pint_type_node = build_pointer_type (integer_type_node); | |
5697 | tree pshort_type_node = build_pointer_type (short_integer_type_node); | |
5698 | tree pchar_type_node = build_pointer_type (char_type_node); | |
5699 | ||
5700 | tree pvoid_type_node = build_pointer_type (void_type_node); | |
5701 | ||
0dbc3651 ZW |
5702 | tree pcfloat_type_node = build_pointer_type (build_qualified_type (float_type_node, TYPE_QUAL_CONST)); |
5703 | tree pcint_type_node = build_pointer_type (build_qualified_type (integer_type_node, TYPE_QUAL_CONST)); | |
5704 | tree pcshort_type_node = build_pointer_type (build_qualified_type (short_integer_type_node, TYPE_QUAL_CONST)); | |
5705 | tree pcchar_type_node = build_pointer_type (build_qualified_type (char_type_node, TYPE_QUAL_CONST)); | |
5706 | ||
5707 | tree pcvoid_type_node = build_pointer_type (build_qualified_type (void_type_node, TYPE_QUAL_CONST)); | |
5708 | ||
a3170dc6 AH |
5709 | tree int_ftype_int_v4si_v4si |
5710 | = build_function_type_list (integer_type_node, | |
5711 | integer_type_node, V4SI_type_node, | |
5712 | V4SI_type_node, NULL_TREE); | |
0dbc3651 ZW |
5713 | tree v4sf_ftype_pcfloat |
5714 | = build_function_type_list (V4SF_type_node, pcfloat_type_node, NULL_TREE); | |
a3170dc6 | 5715 | tree void_ftype_pfloat_v4sf |
b4de2f7d | 5716 | = build_function_type_list (void_type_node, |
a3170dc6 | 5717 | pfloat_type_node, V4SF_type_node, NULL_TREE); |
0dbc3651 ZW |
5718 | tree v4si_ftype_pcint |
5719 | = build_function_type_list (V4SI_type_node, pcint_type_node, NULL_TREE); | |
5720 | tree void_ftype_pint_v4si | |
b4de2f7d AH |
5721 | = build_function_type_list (void_type_node, |
5722 | pint_type_node, V4SI_type_node, NULL_TREE); | |
0dbc3651 ZW |
5723 | tree v8hi_ftype_pcshort |
5724 | = build_function_type_list (V8HI_type_node, pcshort_type_node, NULL_TREE); | |
f18c054f | 5725 | tree void_ftype_pshort_v8hi |
b4de2f7d AH |
5726 | = build_function_type_list (void_type_node, |
5727 | pshort_type_node, V8HI_type_node, NULL_TREE); | |
0dbc3651 ZW |
5728 | tree v16qi_ftype_pcchar |
5729 | = build_function_type_list (V16QI_type_node, pcchar_type_node, NULL_TREE); | |
f18c054f | 5730 | tree void_ftype_pchar_v16qi |
b4de2f7d AH |
5731 | = build_function_type_list (void_type_node, |
5732 | pchar_type_node, V16QI_type_node, NULL_TREE); | |
95385cbb | 5733 | tree void_ftype_v4si |
b4de2f7d | 5734 | = build_function_type_list (void_type_node, V4SI_type_node, NULL_TREE); |
a3170dc6 AH |
5735 | tree v8hi_ftype_void |
5736 | = build_function_type (V8HI_type_node, void_list_node); | |
5737 | tree void_ftype_void | |
5738 | = build_function_type (void_type_node, void_list_node); | |
5739 | tree void_ftype_qi | |
5740 | = build_function_type_list (void_type_node, char_type_node, NULL_TREE); | |
0dbc3651 ZW |
5741 | |
5742 | tree v16qi_ftype_int_pcvoid | |
a3170dc6 | 5743 | = build_function_type_list (V16QI_type_node, |
0dbc3651 ZW |
5744 | integer_type_node, pcvoid_type_node, NULL_TREE); |
5745 | tree v8hi_ftype_int_pcvoid | |
a3170dc6 | 5746 | = build_function_type_list (V8HI_type_node, |
0dbc3651 ZW |
5747 | integer_type_node, pcvoid_type_node, NULL_TREE); |
5748 | tree v4si_ftype_int_pcvoid | |
a3170dc6 | 5749 | = build_function_type_list (V4SI_type_node, |
0dbc3651 ZW |
5750 | integer_type_node, pcvoid_type_node, NULL_TREE); |
5751 | ||
14b32f4e | 5752 | tree void_ftype_v4si_int_pvoid |
b4de2f7d AH |
5753 | = build_function_type_list (void_type_node, |
5754 | V4SI_type_node, integer_type_node, | |
5755 | pvoid_type_node, NULL_TREE); | |
6525c0e7 | 5756 | tree void_ftype_v16qi_int_pvoid |
b4de2f7d AH |
5757 | = build_function_type_list (void_type_node, |
5758 | V16QI_type_node, integer_type_node, | |
5759 | pvoid_type_node, NULL_TREE); | |
6525c0e7 | 5760 | tree void_ftype_v8hi_int_pvoid |
b4de2f7d AH |
5761 | = build_function_type_list (void_type_node, |
5762 | V8HI_type_node, integer_type_node, | |
5763 | pvoid_type_node, NULL_TREE); | |
a3170dc6 AH |
5764 | tree int_ftype_int_v8hi_v8hi |
5765 | = build_function_type_list (integer_type_node, | |
5766 | integer_type_node, V8HI_type_node, | |
5767 | V8HI_type_node, NULL_TREE); | |
5768 | tree int_ftype_int_v16qi_v16qi | |
5769 | = build_function_type_list (integer_type_node, | |
5770 | integer_type_node, V16QI_type_node, | |
5771 | V16QI_type_node, NULL_TREE); | |
5772 | tree int_ftype_int_v4sf_v4sf | |
5773 | = build_function_type_list (integer_type_node, | |
5774 | integer_type_node, V4SF_type_node, | |
5775 | V4SF_type_node, NULL_TREE); | |
5776 | tree v4si_ftype_v4si | |
5777 | = build_function_type_list (V4SI_type_node, V4SI_type_node, NULL_TREE); | |
5778 | tree v8hi_ftype_v8hi | |
5779 | = build_function_type_list (V8HI_type_node, V8HI_type_node, NULL_TREE); | |
5780 | tree v16qi_ftype_v16qi | |
5781 | = build_function_type_list (V16QI_type_node, V16QI_type_node, NULL_TREE); | |
5782 | tree v4sf_ftype_v4sf | |
5783 | = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE); | |
0dbc3651 | 5784 | tree void_ftype_pcvoid_int_char |
a3170dc6 | 5785 | = build_function_type_list (void_type_node, |
0dbc3651 | 5786 | pcvoid_type_node, integer_type_node, |
a3170dc6 | 5787 | char_type_node, NULL_TREE); |
0dbc3651 ZW |
5788 | |
5789 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_4sf", v4sf_ftype_pcfloat, | |
5790 | ALTIVEC_BUILTIN_LD_INTERNAL_4sf); | |
5791 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_4sf", void_ftype_pfloat_v4sf, | |
5792 | ALTIVEC_BUILTIN_ST_INTERNAL_4sf); | |
5793 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_4si", v4si_ftype_pcint, | |
5794 | ALTIVEC_BUILTIN_LD_INTERNAL_4si); | |
5795 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_4si", void_ftype_pint_v4si, | |
5796 | ALTIVEC_BUILTIN_ST_INTERNAL_4si); | |
5797 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_8hi", v8hi_ftype_pcshort, | |
5798 | ALTIVEC_BUILTIN_LD_INTERNAL_8hi); | |
5799 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_8hi", void_ftype_pshort_v8hi, | |
5800 | ALTIVEC_BUILTIN_ST_INTERNAL_8hi); | |
5801 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_16qi", v16qi_ftype_pcchar, | |
5802 | ALTIVEC_BUILTIN_LD_INTERNAL_16qi); | |
5803 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_16qi", void_ftype_pchar_v16qi, | |
5804 | ALTIVEC_BUILTIN_ST_INTERNAL_16qi); | |
a3170dc6 AH |
5805 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_mtvscr", void_ftype_v4si, ALTIVEC_BUILTIN_MTVSCR); |
5806 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_mfvscr", v8hi_ftype_void, ALTIVEC_BUILTIN_MFVSCR); | |
5807 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_dssall", void_ftype_void, ALTIVEC_BUILTIN_DSSALL); | |
5808 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_dss", void_ftype_qi, ALTIVEC_BUILTIN_DSS); | |
0dbc3651 ZW |
5809 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvsl", v16qi_ftype_int_pcvoid, ALTIVEC_BUILTIN_LVSL); |
5810 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvsr", v16qi_ftype_int_pcvoid, ALTIVEC_BUILTIN_LVSR); | |
5811 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvebx", v16qi_ftype_int_pcvoid, ALTIVEC_BUILTIN_LVEBX); | |
5812 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvehx", v8hi_ftype_int_pcvoid, ALTIVEC_BUILTIN_LVEHX); | |
5813 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvewx", v4si_ftype_int_pcvoid, ALTIVEC_BUILTIN_LVEWX); | |
5814 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvxl", v4si_ftype_int_pcvoid, ALTIVEC_BUILTIN_LVXL); | |
5815 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvx", v4si_ftype_int_pcvoid, ALTIVEC_BUILTIN_LVX); | |
a3170dc6 AH |
5816 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvx", void_ftype_v4si_int_pvoid, ALTIVEC_BUILTIN_STVX); |
5817 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvewx", void_ftype_v4si_int_pvoid, ALTIVEC_BUILTIN_STVEWX); | |
5818 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvxl", void_ftype_v4si_int_pvoid, ALTIVEC_BUILTIN_STVXL); | |
5819 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvebx", void_ftype_v16qi_int_pvoid, ALTIVEC_BUILTIN_STVEBX); | |
5820 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvehx", void_ftype_v8hi_int_pvoid, ALTIVEC_BUILTIN_STVEHX); | |
5821 | ||
5822 | /* Add the DST variants. */ | |
5823 | d = (struct builtin_description *) bdesc_dst; | |
5824 | for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++) | |
0dbc3651 | 5825 | def_builtin (d->mask, d->name, void_ftype_pcvoid_int_char, d->code); |
a3170dc6 AH |
5826 | |
5827 | /* Initialize the predicates. */ | |
5828 | dp = (struct builtin_description_predicates *) bdesc_altivec_preds; | |
5829 | for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, dp++) | |
5830 | { | |
5831 | enum machine_mode mode1; | |
5832 | tree type; | |
5833 | ||
5834 | mode1 = insn_data[dp->icode].operand[1].mode; | |
5835 | ||
5836 | switch (mode1) | |
5837 | { | |
5838 | case V4SImode: | |
5839 | type = int_ftype_int_v4si_v4si; | |
5840 | break; | |
5841 | case V8HImode: | |
5842 | type = int_ftype_int_v8hi_v8hi; | |
5843 | break; | |
5844 | case V16QImode: | |
5845 | type = int_ftype_int_v16qi_v16qi; | |
5846 | break; | |
5847 | case V4SFmode: | |
5848 | type = int_ftype_int_v4sf_v4sf; | |
5849 | break; | |
5850 | default: | |
5851 | abort (); | |
5852 | } | |
5853 | ||
5854 | def_builtin (dp->mask, dp->name, type, dp->code); | |
5855 | } | |
5856 | ||
5857 | /* Initialize the abs* operators. */ | |
5858 | d = (struct builtin_description *) bdesc_abs; | |
5859 | for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++) | |
5860 | { | |
5861 | enum machine_mode mode0; | |
5862 | tree type; | |
5863 | ||
5864 | mode0 = insn_data[d->icode].operand[0].mode; | |
5865 | ||
5866 | switch (mode0) | |
5867 | { | |
5868 | case V4SImode: | |
5869 | type = v4si_ftype_v4si; | |
5870 | break; | |
5871 | case V8HImode: | |
5872 | type = v8hi_ftype_v8hi; | |
5873 | break; | |
5874 | case V16QImode: | |
5875 | type = v16qi_ftype_v16qi; | |
5876 | break; | |
5877 | case V4SFmode: | |
5878 | type = v4sf_ftype_v4sf; | |
5879 | break; | |
5880 | default: | |
5881 | abort (); | |
5882 | } | |
5883 | ||
5884 | def_builtin (d->mask, d->name, type, d->code); | |
5885 | } | |
5886 | } | |
5887 | ||
5888 | static void | |
b24c9d35 | 5889 | rs6000_common_init_builtins () |
a3170dc6 AH |
5890 | { |
5891 | struct builtin_description *d; | |
5892 | size_t i; | |
5893 | ||
5894 | tree v4sf_ftype_v4sf_v4sf_v16qi | |
5895 | = build_function_type_list (V4SF_type_node, | |
5896 | V4SF_type_node, V4SF_type_node, | |
5897 | V16QI_type_node, NULL_TREE); | |
5898 | tree v4si_ftype_v4si_v4si_v16qi | |
5899 | = build_function_type_list (V4SI_type_node, | |
5900 | V4SI_type_node, V4SI_type_node, | |
5901 | V16QI_type_node, NULL_TREE); | |
5902 | tree v8hi_ftype_v8hi_v8hi_v16qi | |
5903 | = build_function_type_list (V8HI_type_node, | |
5904 | V8HI_type_node, V8HI_type_node, | |
5905 | V16QI_type_node, NULL_TREE); | |
5906 | tree v16qi_ftype_v16qi_v16qi_v16qi | |
5907 | = build_function_type_list (V16QI_type_node, | |
5908 | V16QI_type_node, V16QI_type_node, | |
5909 | V16QI_type_node, NULL_TREE); | |
5910 | tree v4si_ftype_char | |
5911 | = build_function_type_list (V4SI_type_node, char_type_node, NULL_TREE); | |
5912 | tree v8hi_ftype_char | |
5913 | = build_function_type_list (V8HI_type_node, char_type_node, NULL_TREE); | |
5914 | tree v16qi_ftype_char | |
5915 | = build_function_type_list (V16QI_type_node, char_type_node, NULL_TREE); | |
5916 | tree v8hi_ftype_v16qi | |
5917 | = build_function_type_list (V8HI_type_node, V16QI_type_node, NULL_TREE); | |
5918 | tree v4sf_ftype_v4sf | |
5919 | = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE); | |
5920 | ||
5921 | tree v2si_ftype_v2si_v2si | |
2abe3e28 AH |
5922 | = build_function_type_list (opaque_V2SI_type_node, |
5923 | opaque_V2SI_type_node, | |
5924 | opaque_V2SI_type_node, NULL_TREE); | |
a3170dc6 AH |
5925 | |
5926 | tree v2sf_ftype_v2sf_v2sf | |
2abe3e28 AH |
5927 | = build_function_type_list (opaque_V2SF_type_node, |
5928 | opaque_V2SF_type_node, | |
5929 | opaque_V2SF_type_node, NULL_TREE); | |
a3170dc6 AH |
5930 | |
5931 | tree v2si_ftype_int_int | |
2abe3e28 | 5932 | = build_function_type_list (opaque_V2SI_type_node, |
a3170dc6 AH |
5933 | integer_type_node, integer_type_node, |
5934 | NULL_TREE); | |
5935 | ||
5936 | tree v2si_ftype_v2si | |
2abe3e28 AH |
5937 | = build_function_type_list (opaque_V2SI_type_node, |
5938 | opaque_V2SI_type_node, NULL_TREE); | |
a3170dc6 AH |
5939 | |
5940 | tree v2sf_ftype_v2sf | |
2abe3e28 AH |
5941 | = build_function_type_list (opaque_V2SF_type_node, |
5942 | opaque_V2SF_type_node, NULL_TREE); | |
a3170dc6 AH |
5943 | |
5944 | tree v2sf_ftype_v2si | |
2abe3e28 AH |
5945 | = build_function_type_list (opaque_V2SF_type_node, |
5946 | opaque_V2SI_type_node, NULL_TREE); | |
a3170dc6 AH |
5947 | |
5948 | tree v2si_ftype_v2sf | |
2abe3e28 AH |
5949 | = build_function_type_list (opaque_V2SI_type_node, |
5950 | opaque_V2SF_type_node, NULL_TREE); | |
a3170dc6 AH |
5951 | |
5952 | tree v2si_ftype_v2si_char | |
2abe3e28 AH |
5953 | = build_function_type_list (opaque_V2SI_type_node, |
5954 | opaque_V2SI_type_node, | |
5955 | char_type_node, NULL_TREE); | |
a3170dc6 AH |
5956 | |
5957 | tree v2si_ftype_int_char | |
2abe3e28 | 5958 | = build_function_type_list (opaque_V2SI_type_node, |
a3170dc6 AH |
5959 | integer_type_node, char_type_node, NULL_TREE); |
5960 | ||
5961 | tree v2si_ftype_char | |
2abe3e28 AH |
5962 | = build_function_type_list (opaque_V2SI_type_node, |
5963 | char_type_node, NULL_TREE); | |
a3170dc6 AH |
5964 | |
5965 | tree int_ftype_int_int | |
5966 | = build_function_type_list (integer_type_node, | |
5967 | integer_type_node, integer_type_node, | |
5968 | NULL_TREE); | |
95385cbb | 5969 | |
0ac081f6 | 5970 | tree v4si_ftype_v4si_v4si |
b4de2f7d AH |
5971 | = build_function_type_list (V4SI_type_node, |
5972 | V4SI_type_node, V4SI_type_node, NULL_TREE); | |
617e0e1d | 5973 | tree v4sf_ftype_v4si_char |
b4de2f7d AH |
5974 | = build_function_type_list (V4SF_type_node, |
5975 | V4SI_type_node, char_type_node, NULL_TREE); | |
617e0e1d | 5976 | tree v4si_ftype_v4sf_char |
b4de2f7d AH |
5977 | = build_function_type_list (V4SI_type_node, |
5978 | V4SF_type_node, char_type_node, NULL_TREE); | |
2212663f | 5979 | tree v4si_ftype_v4si_char |
b4de2f7d AH |
5980 | = build_function_type_list (V4SI_type_node, |
5981 | V4SI_type_node, char_type_node, NULL_TREE); | |
2212663f | 5982 | tree v8hi_ftype_v8hi_char |
b4de2f7d AH |
5983 | = build_function_type_list (V8HI_type_node, |
5984 | V8HI_type_node, char_type_node, NULL_TREE); | |
2212663f | 5985 | tree v16qi_ftype_v16qi_char |
b4de2f7d AH |
5986 | = build_function_type_list (V16QI_type_node, |
5987 | V16QI_type_node, char_type_node, NULL_TREE); | |
24408032 | 5988 | tree v16qi_ftype_v16qi_v16qi_char |
b4de2f7d AH |
5989 | = build_function_type_list (V16QI_type_node, |
5990 | V16QI_type_node, V16QI_type_node, | |
5991 | char_type_node, NULL_TREE); | |
24408032 | 5992 | tree v8hi_ftype_v8hi_v8hi_char |
b4de2f7d AH |
5993 | = build_function_type_list (V8HI_type_node, |
5994 | V8HI_type_node, V8HI_type_node, | |
5995 | char_type_node, NULL_TREE); | |
24408032 | 5996 | tree v4si_ftype_v4si_v4si_char |
b4de2f7d AH |
5997 | = build_function_type_list (V4SI_type_node, |
5998 | V4SI_type_node, V4SI_type_node, | |
5999 | char_type_node, NULL_TREE); | |
24408032 | 6000 | tree v4sf_ftype_v4sf_v4sf_char |
b4de2f7d AH |
6001 | = build_function_type_list (V4SF_type_node, |
6002 | V4SF_type_node, V4SF_type_node, | |
6003 | char_type_node, NULL_TREE); | |
0ac081f6 | 6004 | tree v4sf_ftype_v4sf_v4sf |
b4de2f7d AH |
6005 | = build_function_type_list (V4SF_type_node, |
6006 | V4SF_type_node, V4SF_type_node, NULL_TREE); | |
617e0e1d | 6007 | tree v4sf_ftype_v4sf_v4sf_v4si |
b4de2f7d AH |
6008 | = build_function_type_list (V4SF_type_node, |
6009 | V4SF_type_node, V4SF_type_node, | |
6010 | V4SI_type_node, NULL_TREE); | |
2212663f | 6011 | tree v4sf_ftype_v4sf_v4sf_v4sf |
b4de2f7d AH |
6012 | = build_function_type_list (V4SF_type_node, |
6013 | V4SF_type_node, V4SF_type_node, | |
6014 | V4SF_type_node, NULL_TREE); | |
617e0e1d | 6015 | tree v4si_ftype_v4si_v4si_v4si |
b4de2f7d AH |
6016 | = build_function_type_list (V4SI_type_node, |
6017 | V4SI_type_node, V4SI_type_node, | |
6018 | V4SI_type_node, NULL_TREE); | |
0ac081f6 | 6019 | tree v8hi_ftype_v8hi_v8hi |
b4de2f7d AH |
6020 | = build_function_type_list (V8HI_type_node, |
6021 | V8HI_type_node, V8HI_type_node, NULL_TREE); | |
2212663f | 6022 | tree v8hi_ftype_v8hi_v8hi_v8hi |
b4de2f7d AH |
6023 | = build_function_type_list (V8HI_type_node, |
6024 | V8HI_type_node, V8HI_type_node, | |
6025 | V8HI_type_node, NULL_TREE); | |
2212663f | 6026 | tree v4si_ftype_v8hi_v8hi_v4si |
b4de2f7d AH |
6027 | = build_function_type_list (V4SI_type_node, |
6028 | V8HI_type_node, V8HI_type_node, | |
6029 | V4SI_type_node, NULL_TREE); | |
2212663f | 6030 | tree v4si_ftype_v16qi_v16qi_v4si |
b4de2f7d AH |
6031 | = build_function_type_list (V4SI_type_node, |
6032 | V16QI_type_node, V16QI_type_node, | |
6033 | V4SI_type_node, NULL_TREE); | |
0ac081f6 | 6034 | tree v16qi_ftype_v16qi_v16qi |
b4de2f7d AH |
6035 | = build_function_type_list (V16QI_type_node, |
6036 | V16QI_type_node, V16QI_type_node, NULL_TREE); | |
0ac081f6 | 6037 | tree v4si_ftype_v4sf_v4sf |
b4de2f7d AH |
6038 | = build_function_type_list (V4SI_type_node, |
6039 | V4SF_type_node, V4SF_type_node, NULL_TREE); | |
0ac081f6 | 6040 | tree v8hi_ftype_v16qi_v16qi |
b4de2f7d AH |
6041 | = build_function_type_list (V8HI_type_node, |
6042 | V16QI_type_node, V16QI_type_node, NULL_TREE); | |
0ac081f6 | 6043 | tree v4si_ftype_v8hi_v8hi |
b4de2f7d AH |
6044 | = build_function_type_list (V4SI_type_node, |
6045 | V8HI_type_node, V8HI_type_node, NULL_TREE); | |
0ac081f6 | 6046 | tree v8hi_ftype_v4si_v4si |
b4de2f7d AH |
6047 | = build_function_type_list (V8HI_type_node, |
6048 | V4SI_type_node, V4SI_type_node, NULL_TREE); | |
0ac081f6 | 6049 | tree v16qi_ftype_v8hi_v8hi |
b4de2f7d AH |
6050 | = build_function_type_list (V16QI_type_node, |
6051 | V8HI_type_node, V8HI_type_node, NULL_TREE); | |
0ac081f6 | 6052 | tree v4si_ftype_v16qi_v4si |
b4de2f7d AH |
6053 | = build_function_type_list (V4SI_type_node, |
6054 | V16QI_type_node, V4SI_type_node, NULL_TREE); | |
fa066a23 | 6055 | tree v4si_ftype_v16qi_v16qi |
b4de2f7d AH |
6056 | = build_function_type_list (V4SI_type_node, |
6057 | V16QI_type_node, V16QI_type_node, NULL_TREE); | |
0ac081f6 | 6058 | tree v4si_ftype_v8hi_v4si |
b4de2f7d AH |
6059 | = build_function_type_list (V4SI_type_node, |
6060 | V8HI_type_node, V4SI_type_node, NULL_TREE); | |
a3170dc6 AH |
6061 | tree v4si_ftype_v8hi |
6062 | = build_function_type_list (V4SI_type_node, V8HI_type_node, NULL_TREE); | |
6063 | tree int_ftype_v4si_v4si | |
6064 | = build_function_type_list (integer_type_node, | |
6065 | V4SI_type_node, V4SI_type_node, NULL_TREE); | |
6066 | tree int_ftype_v4sf_v4sf | |
6067 | = build_function_type_list (integer_type_node, | |
6068 | V4SF_type_node, V4SF_type_node, NULL_TREE); | |
6069 | tree int_ftype_v16qi_v16qi | |
6070 | = build_function_type_list (integer_type_node, | |
6071 | V16QI_type_node, V16QI_type_node, NULL_TREE); | |
0ac081f6 | 6072 | tree int_ftype_v8hi_v8hi |
b4de2f7d AH |
6073 | = build_function_type_list (integer_type_node, |
6074 | V8HI_type_node, V8HI_type_node, NULL_TREE); | |
0ac081f6 | 6075 | |
6f317ef3 | 6076 | /* Add the simple ternary operators. */ |
2212663f | 6077 | d = (struct builtin_description *) bdesc_3arg; |
ca7558fc | 6078 | for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++) |
2212663f DB |
6079 | { |
6080 | ||
6081 | enum machine_mode mode0, mode1, mode2, mode3; | |
6082 | tree type; | |
6083 | ||
0559cc77 | 6084 | if (d->name == 0 || d->icode == CODE_FOR_nothing) |
2212663f DB |
6085 | continue; |
6086 | ||
6087 | mode0 = insn_data[d->icode].operand[0].mode; | |
6088 | mode1 = insn_data[d->icode].operand[1].mode; | |
6089 | mode2 = insn_data[d->icode].operand[2].mode; | |
6090 | mode3 = insn_data[d->icode].operand[3].mode; | |
6091 | ||
6092 | /* When all four are of the same mode. */ | |
6093 | if (mode0 == mode1 && mode1 == mode2 && mode2 == mode3) | |
6094 | { | |
6095 | switch (mode0) | |
6096 | { | |
617e0e1d DB |
6097 | case V4SImode: |
6098 | type = v4si_ftype_v4si_v4si_v4si; | |
6099 | break; | |
2212663f DB |
6100 | case V4SFmode: |
6101 | type = v4sf_ftype_v4sf_v4sf_v4sf; | |
6102 | break; | |
6103 | case V8HImode: | |
6104 | type = v8hi_ftype_v8hi_v8hi_v8hi; | |
6105 | break; | |
6106 | case V16QImode: | |
6107 | type = v16qi_ftype_v16qi_v16qi_v16qi; | |
6108 | break; | |
6109 | default: | |
6110 | abort(); | |
6111 | } | |
6112 | } | |
6113 | else if (mode0 == mode1 && mode1 == mode2 && mode3 == V16QImode) | |
6114 | { | |
6115 | switch (mode0) | |
6116 | { | |
6117 | case V4SImode: | |
6118 | type = v4si_ftype_v4si_v4si_v16qi; | |
6119 | break; | |
6120 | case V4SFmode: | |
6121 | type = v4sf_ftype_v4sf_v4sf_v16qi; | |
6122 | break; | |
6123 | case V8HImode: | |
6124 | type = v8hi_ftype_v8hi_v8hi_v16qi; | |
6125 | break; | |
6126 | case V16QImode: | |
6127 | type = v16qi_ftype_v16qi_v16qi_v16qi; | |
6128 | break; | |
6129 | default: | |
6130 | abort(); | |
6131 | } | |
6132 | } | |
6133 | else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V16QImode | |
6134 | && mode3 == V4SImode) | |
24408032 | 6135 | type = v4si_ftype_v16qi_v16qi_v4si; |
2212663f DB |
6136 | else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V8HImode |
6137 | && mode3 == V4SImode) | |
24408032 | 6138 | type = v4si_ftype_v8hi_v8hi_v4si; |
617e0e1d DB |
6139 | else if (mode0 == V4SFmode && mode1 == V4SFmode && mode2 == V4SFmode |
6140 | && mode3 == V4SImode) | |
24408032 AH |
6141 | type = v4sf_ftype_v4sf_v4sf_v4si; |
6142 | ||
6143 | /* vchar, vchar, vchar, 4 bit literal. */ | |
6144 | else if (mode0 == V16QImode && mode1 == mode0 && mode2 == mode0 | |
6145 | && mode3 == QImode) | |
6146 | type = v16qi_ftype_v16qi_v16qi_char; | |
6147 | ||
6148 | /* vshort, vshort, vshort, 4 bit literal. */ | |
6149 | else if (mode0 == V8HImode && mode1 == mode0 && mode2 == mode0 | |
6150 | && mode3 == QImode) | |
6151 | type = v8hi_ftype_v8hi_v8hi_char; | |
6152 | ||
6153 | /* vint, vint, vint, 4 bit literal. */ | |
6154 | else if (mode0 == V4SImode && mode1 == mode0 && mode2 == mode0 | |
6155 | && mode3 == QImode) | |
6156 | type = v4si_ftype_v4si_v4si_char; | |
6157 | ||
6158 | /* vfloat, vfloat, vfloat, 4 bit literal. */ | |
6159 | else if (mode0 == V4SFmode && mode1 == mode0 && mode2 == mode0 | |
6160 | && mode3 == QImode) | |
6161 | type = v4sf_ftype_v4sf_v4sf_char; | |
6162 | ||
2212663f DB |
6163 | else |
6164 | abort (); | |
6165 | ||
6166 | def_builtin (d->mask, d->name, type, d->code); | |
6167 | } | |
6168 | ||
0ac081f6 | 6169 | /* Add the simple binary operators. */ |
00b960c7 | 6170 | d = (struct builtin_description *) bdesc_2arg; |
ca7558fc | 6171 | for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++) |
0ac081f6 AH |
6172 | { |
6173 | enum machine_mode mode0, mode1, mode2; | |
6174 | tree type; | |
6175 | ||
0559cc77 | 6176 | if (d->name == 0 || d->icode == CODE_FOR_nothing) |
0ac081f6 AH |
6177 | continue; |
6178 | ||
6179 | mode0 = insn_data[d->icode].operand[0].mode; | |
6180 | mode1 = insn_data[d->icode].operand[1].mode; | |
6181 | mode2 = insn_data[d->icode].operand[2].mode; | |
6182 | ||
6183 | /* When all three operands are of the same mode. */ | |
6184 | if (mode0 == mode1 && mode1 == mode2) | |
6185 | { | |
6186 | switch (mode0) | |
6187 | { | |
6188 | case V4SFmode: | |
6189 | type = v4sf_ftype_v4sf_v4sf; | |
6190 | break; | |
6191 | case V4SImode: | |
6192 | type = v4si_ftype_v4si_v4si; | |
6193 | break; | |
6194 | case V16QImode: | |
6195 | type = v16qi_ftype_v16qi_v16qi; | |
6196 | break; | |
6197 | case V8HImode: | |
6198 | type = v8hi_ftype_v8hi_v8hi; | |
6199 | break; | |
a3170dc6 AH |
6200 | case V2SImode: |
6201 | type = v2si_ftype_v2si_v2si; | |
6202 | break; | |
6203 | case V2SFmode: | |
6204 | type = v2sf_ftype_v2sf_v2sf; | |
6205 | break; | |
6206 | case SImode: | |
6207 | type = int_ftype_int_int; | |
6208 | break; | |
0ac081f6 AH |
6209 | default: |
6210 | abort (); | |
6211 | } | |
6212 | } | |
6213 | ||
6214 | /* A few other combos we really don't want to do manually. */ | |
6215 | ||
6216 | /* vint, vfloat, vfloat. */ | |
6217 | else if (mode0 == V4SImode && mode1 == V4SFmode && mode2 == V4SFmode) | |
6218 | type = v4si_ftype_v4sf_v4sf; | |
6219 | ||
6220 | /* vshort, vchar, vchar. */ | |
6221 | else if (mode0 == V8HImode && mode1 == V16QImode && mode2 == V16QImode) | |
6222 | type = v8hi_ftype_v16qi_v16qi; | |
6223 | ||
6224 | /* vint, vshort, vshort. */ | |
6225 | else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V8HImode) | |
6226 | type = v4si_ftype_v8hi_v8hi; | |
6227 | ||
6228 | /* vshort, vint, vint. */ | |
6229 | else if (mode0 == V8HImode && mode1 == V4SImode && mode2 == V4SImode) | |
6230 | type = v8hi_ftype_v4si_v4si; | |
6231 | ||
6232 | /* vchar, vshort, vshort. */ | |
6233 | else if (mode0 == V16QImode && mode1 == V8HImode && mode2 == V8HImode) | |
6234 | type = v16qi_ftype_v8hi_v8hi; | |
6235 | ||
6236 | /* vint, vchar, vint. */ | |
6237 | else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V4SImode) | |
6238 | type = v4si_ftype_v16qi_v4si; | |
6239 | ||
fa066a23 AH |
6240 | /* vint, vchar, vchar. */ |
6241 | else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V16QImode) | |
6242 | type = v4si_ftype_v16qi_v16qi; | |
6243 | ||
0ac081f6 AH |
6244 | /* vint, vshort, vint. */ |
6245 | else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V4SImode) | |
6246 | type = v4si_ftype_v8hi_v4si; | |
2212663f DB |
6247 | |
6248 | /* vint, vint, 5 bit literal. */ | |
6249 | else if (mode0 == V4SImode && mode1 == V4SImode && mode2 == QImode) | |
6250 | type = v4si_ftype_v4si_char; | |
6251 | ||
6252 | /* vshort, vshort, 5 bit literal. */ | |
6253 | else if (mode0 == V8HImode && mode1 == V8HImode && mode2 == QImode) | |
6254 | type = v8hi_ftype_v8hi_char; | |
6255 | ||
6256 | /* vchar, vchar, 5 bit literal. */ | |
6257 | else if (mode0 == V16QImode && mode1 == V16QImode && mode2 == QImode) | |
6258 | type = v16qi_ftype_v16qi_char; | |
0ac081f6 | 6259 | |
617e0e1d DB |
6260 | /* vfloat, vint, 5 bit literal. */ |
6261 | else if (mode0 == V4SFmode && mode1 == V4SImode && mode2 == QImode) | |
6262 | type = v4sf_ftype_v4si_char; | |
6263 | ||
6264 | /* vint, vfloat, 5 bit literal. */ | |
6265 | else if (mode0 == V4SImode && mode1 == V4SFmode && mode2 == QImode) | |
6266 | type = v4si_ftype_v4sf_char; | |
6267 | ||
a3170dc6 AH |
6268 | else if (mode0 == V2SImode && mode1 == SImode && mode2 == SImode) |
6269 | type = v2si_ftype_int_int; | |
6270 | ||
6271 | else if (mode0 == V2SImode && mode1 == V2SImode && mode2 == QImode) | |
6272 | type = v2si_ftype_v2si_char; | |
6273 | ||
6274 | else if (mode0 == V2SImode && mode1 == SImode && mode2 == QImode) | |
6275 | type = v2si_ftype_int_char; | |
6276 | ||
0ac081f6 AH |
6277 | /* int, x, x. */ |
6278 | else if (mode0 == SImode) | |
6279 | { | |
6280 | switch (mode1) | |
6281 | { | |
6282 | case V4SImode: | |
6283 | type = int_ftype_v4si_v4si; | |
6284 | break; | |
6285 | case V4SFmode: | |
6286 | type = int_ftype_v4sf_v4sf; | |
6287 | break; | |
6288 | case V16QImode: | |
6289 | type = int_ftype_v16qi_v16qi; | |
6290 | break; | |
6291 | case V8HImode: | |
6292 | type = int_ftype_v8hi_v8hi; | |
6293 | break; | |
6294 | default: | |
6295 | abort (); | |
6296 | } | |
6297 | } | |
6298 | ||
6299 | else | |
6300 | abort (); | |
6301 | ||
2212663f DB |
6302 | def_builtin (d->mask, d->name, type, d->code); |
6303 | } | |
24408032 | 6304 | |
2212663f DB |
6305 | /* Add the simple unary operators. */ |
6306 | d = (struct builtin_description *) bdesc_1arg; | |
ca7558fc | 6307 | for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++) |
2212663f DB |
6308 | { |
6309 | enum machine_mode mode0, mode1; | |
6310 | tree type; | |
6311 | ||
0559cc77 | 6312 | if (d->name == 0 || d->icode == CODE_FOR_nothing) |
2212663f DB |
6313 | continue; |
6314 | ||
6315 | mode0 = insn_data[d->icode].operand[0].mode; | |
6316 | mode1 = insn_data[d->icode].operand[1].mode; | |
6317 | ||
6318 | if (mode0 == V4SImode && mode1 == QImode) | |
6319 | type = v4si_ftype_char; | |
6320 | else if (mode0 == V8HImode && mode1 == QImode) | |
6321 | type = v8hi_ftype_char; | |
6322 | else if (mode0 == V16QImode && mode1 == QImode) | |
6323 | type = v16qi_ftype_char; | |
617e0e1d DB |
6324 | else if (mode0 == V4SFmode && mode1 == V4SFmode) |
6325 | type = v4sf_ftype_v4sf; | |
20e26713 AH |
6326 | else if (mode0 == V8HImode && mode1 == V16QImode) |
6327 | type = v8hi_ftype_v16qi; | |
6328 | else if (mode0 == V4SImode && mode1 == V8HImode) | |
6329 | type = v4si_ftype_v8hi; | |
a3170dc6 AH |
6330 | else if (mode0 == V2SImode && mode1 == V2SImode) |
6331 | type = v2si_ftype_v2si; | |
6332 | else if (mode0 == V2SFmode && mode1 == V2SFmode) | |
6333 | type = v2sf_ftype_v2sf; | |
6334 | else if (mode0 == V2SFmode && mode1 == V2SImode) | |
6335 | type = v2sf_ftype_v2si; | |
6336 | else if (mode0 == V2SImode && mode1 == V2SFmode) | |
6337 | type = v2si_ftype_v2sf; | |
6338 | else if (mode0 == V2SImode && mode1 == QImode) | |
6339 | type = v2si_ftype_char; | |
2212663f DB |
6340 | else |
6341 | abort (); | |
6342 | ||
0ac081f6 AH |
6343 | def_builtin (d->mask, d->name, type, d->code); |
6344 | } | |
6345 | } | |
6346 | ||
35aff10b | 6347 | \f |
7e69e155 MM |
6348 | /* Expand a block move operation, and return 1 if successful. Return 0 |
6349 | if we should let the compiler generate normal code. | |
6350 | ||
6351 | operands[0] is the destination | |
6352 | operands[1] is the source | |
6353 | operands[2] is the length | |
6354 | operands[3] is the alignment */ | |
6355 | ||
3933e0e1 MM |
6356 | #define MAX_MOVE_REG 4 |
6357 | ||
7e69e155 MM |
6358 | int |
6359 | expand_block_move (operands) | |
6360 | rtx operands[]; | |
6361 | { | |
b6c9286a MM |
6362 | rtx orig_dest = operands[0]; |
6363 | rtx orig_src = operands[1]; | |
7e69e155 | 6364 | rtx bytes_rtx = operands[2]; |
7e69e155 | 6365 | rtx align_rtx = operands[3]; |
3933e0e1 | 6366 | int constp = (GET_CODE (bytes_rtx) == CONST_INT); |
5ee95df6 | 6367 | int align; |
3933e0e1 MM |
6368 | int bytes; |
6369 | int offset; | |
7e69e155 MM |
6370 | int move_bytes; |
6371 | ||
3933e0e1 | 6372 | /* If this is not a fixed size move, just call memcpy */ |
cc0d9ba8 | 6373 | if (! constp) |
3933e0e1 MM |
6374 | return 0; |
6375 | ||
5ee95df6 FS |
6376 | /* If this is not a fixed size alignment, abort */ |
6377 | if (GET_CODE (align_rtx) != CONST_INT) | |
6378 | abort (); | |
6379 | align = INTVAL (align_rtx); | |
6380 | ||
7e69e155 | 6381 | /* Anything to move? */ |
3933e0e1 MM |
6382 | bytes = INTVAL (bytes_rtx); |
6383 | if (bytes <= 0) | |
7e69e155 MM |
6384 | return 1; |
6385 | ||
ea9982a8 | 6386 | /* store_one_arg depends on expand_block_move to handle at least the size of |
6f317ef3 | 6387 | reg_parm_stack_space. */ |
ea9982a8 | 6388 | if (bytes > (TARGET_POWERPC64 ? 64 : 32)) |
7e69e155 MM |
6389 | return 0; |
6390 | ||
3933e0e1 | 6391 | if (TARGET_STRING) /* string instructions are available */ |
7e69e155 | 6392 | { |
35aff10b | 6393 | for (offset = 0; bytes > 0; offset += move_bytes, bytes -= move_bytes) |
7e69e155 | 6394 | { |
35aff10b AM |
6395 | union { |
6396 | rtx (*movstrsi) PARAMS ((rtx, rtx, rtx, rtx)); | |
6397 | rtx (*mov) PARAMS ((rtx, rtx)); | |
6398 | } gen_func; | |
6399 | enum machine_mode mode = BLKmode; | |
6400 | rtx src, dest; | |
6401 | ||
3933e0e1 | 6402 | if (bytes > 24 /* move up to 32 bytes at a time */ |
cc0d9ba8 DE |
6403 | && ! fixed_regs[5] |
6404 | && ! fixed_regs[6] | |
6405 | && ! fixed_regs[7] | |
6406 | && ! fixed_regs[8] | |
6407 | && ! fixed_regs[9] | |
6408 | && ! fixed_regs[10] | |
6409 | && ! fixed_regs[11] | |
6410 | && ! fixed_regs[12]) | |
3933e0e1 MM |
6411 | { |
6412 | move_bytes = (bytes > 32) ? 32 : bytes; | |
35aff10b | 6413 | gen_func.movstrsi = gen_movstrsi_8reg; |
3933e0e1 MM |
6414 | } |
6415 | else if (bytes > 16 /* move up to 24 bytes at a time */ | |
f9562f27 DE |
6416 | && ! fixed_regs[5] |
6417 | && ! fixed_regs[6] | |
cc0d9ba8 DE |
6418 | && ! fixed_regs[7] |
6419 | && ! fixed_regs[8] | |
6420 | && ! fixed_regs[9] | |
f9562f27 | 6421 | && ! fixed_regs[10]) |
3933e0e1 MM |
6422 | { |
6423 | move_bytes = (bytes > 24) ? 24 : bytes; | |
35aff10b | 6424 | gen_func.movstrsi = gen_movstrsi_6reg; |
3933e0e1 MM |
6425 | } |
6426 | else if (bytes > 8 /* move up to 16 bytes at a time */ | |
f9562f27 DE |
6427 | && ! fixed_regs[5] |
6428 | && ! fixed_regs[6] | |
6429 | && ! fixed_regs[7] | |
6430 | && ! fixed_regs[8]) | |
3933e0e1 MM |
6431 | { |
6432 | move_bytes = (bytes > 16) ? 16 : bytes; | |
35aff10b | 6433 | gen_func.movstrsi = gen_movstrsi_4reg; |
3933e0e1 | 6434 | } |
acad7ed3 | 6435 | else if (bytes >= 8 && TARGET_POWERPC64 |
a4f6c312 | 6436 | /* 64-bit loads and stores require word-aligned |
82e41834 | 6437 | displacements. */ |
a4f6c312 | 6438 | && (align >= 8 || (! STRICT_ALIGNMENT && align >= 4))) |
acad7ed3 DE |
6439 | { |
6440 | move_bytes = 8; | |
35aff10b AM |
6441 | mode = DImode; |
6442 | gen_func.mov = gen_movdi; | |
acad7ed3 | 6443 | } |
09a625f7 | 6444 | else if (bytes > 4 && !TARGET_POWERPC64) |
3933e0e1 MM |
6445 | { /* move up to 8 bytes at a time */ |
6446 | move_bytes = (bytes > 8) ? 8 : bytes; | |
35aff10b | 6447 | gen_func.movstrsi = gen_movstrsi_2reg; |
3933e0e1 | 6448 | } |
cc0d9ba8 | 6449 | else if (bytes >= 4 && (align >= 4 || ! STRICT_ALIGNMENT)) |
3933e0e1 MM |
6450 | { /* move 4 bytes */ |
6451 | move_bytes = 4; | |
35aff10b AM |
6452 | mode = SImode; |
6453 | gen_func.mov = gen_movsi; | |
3933e0e1 | 6454 | } |
cc0d9ba8 | 6455 | else if (bytes == 2 && (align >= 2 || ! STRICT_ALIGNMENT)) |
3933e0e1 MM |
6456 | { /* move 2 bytes */ |
6457 | move_bytes = 2; | |
35aff10b AM |
6458 | mode = HImode; |
6459 | gen_func.mov = gen_movhi; | |
3933e0e1 MM |
6460 | } |
6461 | else if (bytes == 1) /* move 1 byte */ | |
6462 | { | |
6463 | move_bytes = 1; | |
35aff10b AM |
6464 | mode = QImode; |
6465 | gen_func.mov = gen_movqi; | |
3933e0e1 MM |
6466 | } |
6467 | else | |
6468 | { /* move up to 4 bytes at a time */ | |
6469 | move_bytes = (bytes > 4) ? 4 : bytes; | |
35aff10b | 6470 | gen_func.movstrsi = gen_movstrsi_1reg; |
3933e0e1 | 6471 | } |
4c64a852 | 6472 | |
35aff10b AM |
6473 | src = adjust_address (orig_src, mode, offset); |
6474 | dest = adjust_address (orig_dest, mode, offset); | |
6475 | ||
6476 | if (mode == BLKmode) | |
015892ee | 6477 | { |
35aff10b AM |
6478 | /* Move the address into scratch registers. The movstrsi |
6479 | patterns require zero offset. */ | |
6480 | if (!REG_P (XEXP (src, 0))) | |
cc0d9ba8 | 6481 | { |
35aff10b AM |
6482 | rtx src_reg = copy_addr_to_reg (XEXP (src, 0)); |
6483 | src = replace_equiv_address (src, src_reg); | |
cc0d9ba8 | 6484 | } |
35aff10b AM |
6485 | set_mem_size (src, GEN_INT (move_bytes)); |
6486 | ||
6487 | if (!REG_P (XEXP (dest, 0))) | |
cc0d9ba8 | 6488 | { |
35aff10b AM |
6489 | rtx dest_reg = copy_addr_to_reg (XEXP (dest, 0)); |
6490 | dest = replace_equiv_address (dest, dest_reg); | |
cc0d9ba8 | 6491 | } |
35aff10b AM |
6492 | set_mem_size (dest, GEN_INT (move_bytes)); |
6493 | ||
6494 | emit_insn ((*gen_func.movstrsi) (dest, src, | |
6495 | GEN_INT (move_bytes & 31), | |
6496 | align_rtx)); | |
6497 | } | |
6498 | else | |
6499 | { | |
6500 | rtx tmp_reg = gen_reg_rtx (mode); | |
6501 | ||
6502 | emit_insn ((*gen_func.mov) (tmp_reg, src)); | |
6503 | emit_insn ((*gen_func.mov) (dest, tmp_reg)); | |
015892ee | 6504 | } |
4c64a852 | 6505 | } |
3933e0e1 MM |
6506 | } |
6507 | ||
6508 | else /* string instructions not available */ | |
6509 | { | |
35aff10b AM |
6510 | rtx stores[MAX_MOVE_REG]; |
6511 | int num_reg = 0; | |
6512 | int i; | |
6513 | ||
6514 | for (offset = 0; bytes > 0; offset += move_bytes, bytes -= move_bytes) | |
7e69e155 | 6515 | { |
35aff10b AM |
6516 | rtx (*gen_mov_func) PARAMS ((rtx, rtx)); |
6517 | enum machine_mode mode; | |
6518 | rtx src, dest, tmp_reg; | |
3933e0e1 | 6519 | |
cc0d9ba8 DE |
6520 | /* Generate the appropriate load and store, saving the stores |
6521 | for later. */ | |
6522 | if (bytes >= 8 && TARGET_POWERPC64 | |
a4f6c312 SS |
6523 | /* 64-bit loads and stores require word-aligned |
6524 | displacements. */ | |
cc0d9ba8 | 6525 | && (align >= 8 || (! STRICT_ALIGNMENT && align >= 4))) |
b6c9286a MM |
6526 | { |
6527 | move_bytes = 8; | |
35aff10b AM |
6528 | mode = DImode; |
6529 | gen_mov_func = gen_movdi; | |
b6c9286a | 6530 | } |
cc0d9ba8 | 6531 | else if (bytes >= 4 && (align >= 4 || ! STRICT_ALIGNMENT)) |
3933e0e1 MM |
6532 | { |
6533 | move_bytes = 4; | |
35aff10b AM |
6534 | mode = SImode; |
6535 | gen_mov_func = gen_movsi; | |
3933e0e1 | 6536 | } |
cc0d9ba8 | 6537 | else if (bytes >= 2 && (align >= 2 || ! STRICT_ALIGNMENT)) |
3933e0e1 MM |
6538 | { |
6539 | move_bytes = 2; | |
35aff10b AM |
6540 | mode = HImode; |
6541 | gen_mov_func = gen_movhi; | |
3933e0e1 MM |
6542 | } |
6543 | else | |
6544 | { | |
6545 | move_bytes = 1; | |
35aff10b AM |
6546 | mode = QImode; |
6547 | gen_mov_func = gen_movqi; | |
3933e0e1 MM |
6548 | } |
6549 | ||
35aff10b AM |
6550 | src = adjust_address (orig_src, mode, offset); |
6551 | dest = adjust_address (orig_dest, mode, offset); | |
6552 | tmp_reg = gen_reg_rtx (mode); | |
6553 | ||
6554 | emit_insn ((*gen_mov_func) (tmp_reg, src)); | |
6555 | stores[num_reg++] = (*gen_mov_func) (dest, tmp_reg); | |
6556 | ||
3933e0e1 MM |
6557 | if (num_reg >= MAX_MOVE_REG) |
6558 | { | |
6559 | for (i = 0; i < num_reg; i++) | |
6560 | emit_insn (stores[i]); | |
6561 | num_reg = 0; | |
7e69e155 MM |
6562 | } |
6563 | } | |
3933e0e1 | 6564 | |
b6c9286a MM |
6565 | for (i = 0; i < num_reg; i++) |
6566 | emit_insn (stores[i]); | |
7e69e155 MM |
6567 | } |
6568 | ||
6569 | return 1; | |
6570 | } | |
6571 | ||
9878760c RK |
6572 | \f |
6573 | /* Return 1 if OP is a load multiple operation. It is known to be a | |
6574 | PARALLEL and the first section will be tested. */ | |
6575 | ||
6576 | int | |
6577 | load_multiple_operation (op, mode) | |
6578 | rtx op; | |
296b8152 | 6579 | enum machine_mode mode ATTRIBUTE_UNUSED; |
9878760c RK |
6580 | { |
6581 | int count = XVECLEN (op, 0); | |
e2c953b6 | 6582 | unsigned int dest_regno; |
9878760c RK |
6583 | rtx src_addr; |
6584 | int i; | |
6585 | ||
6586 | /* Perform a quick check so we don't blow up below. */ | |
6587 | if (count <= 1 | |
6588 | || GET_CODE (XVECEXP (op, 0, 0)) != SET | |
6589 | || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG | |
6590 | || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM) | |
6591 | return 0; | |
6592 | ||
6593 | dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0))); | |
6594 | src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0); | |
6595 | ||
6596 | for (i = 1; i < count; i++) | |
6597 | { | |
6598 | rtx elt = XVECEXP (op, 0, i); | |
6599 | ||
6600 | if (GET_CODE (elt) != SET | |
6601 | || GET_CODE (SET_DEST (elt)) != REG | |
6602 | || GET_MODE (SET_DEST (elt)) != SImode | |
6603 | || REGNO (SET_DEST (elt)) != dest_regno + i | |
6604 | || GET_CODE (SET_SRC (elt)) != MEM | |
6605 | || GET_MODE (SET_SRC (elt)) != SImode | |
6606 | || GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS | |
6607 | || ! rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr) | |
6608 | || GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT | |
6609 | || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != i * 4) | |
6610 | return 0; | |
6611 | } | |
6612 | ||
6613 | return 1; | |
6614 | } | |
6615 | ||
6616 | /* Similar, but tests for store multiple. Here, the second vector element | |
6617 | is a CLOBBER. It will be tested later. */ | |
6618 | ||
6619 | int | |
6620 | store_multiple_operation (op, mode) | |
6621 | rtx op; | |
296b8152 | 6622 | enum machine_mode mode ATTRIBUTE_UNUSED; |
9878760c RK |
6623 | { |
6624 | int count = XVECLEN (op, 0) - 1; | |
e2c953b6 | 6625 | unsigned int src_regno; |
9878760c RK |
6626 | rtx dest_addr; |
6627 | int i; | |
6628 | ||
6629 | /* Perform a quick check so we don't blow up below. */ | |
6630 | if (count <= 1 | |
6631 | || GET_CODE (XVECEXP (op, 0, 0)) != SET | |
6632 | || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM | |
6633 | || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG) | |
6634 | return 0; | |
6635 | ||
6636 | src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0))); | |
6637 | dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0); | |
6638 | ||
6639 | for (i = 1; i < count; i++) | |
6640 | { | |
6641 | rtx elt = XVECEXP (op, 0, i + 1); | |
6642 | ||
6643 | if (GET_CODE (elt) != SET | |
6644 | || GET_CODE (SET_SRC (elt)) != REG | |
6645 | || GET_MODE (SET_SRC (elt)) != SImode | |
6646 | || REGNO (SET_SRC (elt)) != src_regno + i | |
6647 | || GET_CODE (SET_DEST (elt)) != MEM | |
6648 | || GET_MODE (SET_DEST (elt)) != SImode | |
6649 | || GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS | |
6650 | || ! rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr) | |
6651 | || GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT | |
6652 | || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != i * 4) | |
6653 | return 0; | |
6654 | } | |
6655 | ||
6656 | return 1; | |
6657 | } | |
9ebbca7d | 6658 | |
9caa3eb2 DE |
6659 | /* Return a string to perform a load_multiple operation. |
6660 | operands[0] is the vector. | |
6661 | operands[1] is the source address. | |
6662 | operands[2] is the first destination register. */ | |
6663 | ||
6664 | const char * | |
6665 | rs6000_output_load_multiple (operands) | |
ebe637e3 | 6666 | rtx operands[3]; |
9caa3eb2 DE |
6667 | { |
6668 | /* We have to handle the case where the pseudo used to contain the address | |
6669 | is assigned to one of the output registers. */ | |
6670 | int i, j; | |
6671 | int words = XVECLEN (operands[0], 0); | |
6672 | rtx xop[10]; | |
6673 | ||
6674 | if (XVECLEN (operands[0], 0) == 1) | |
6675 | return "{l|lwz} %2,0(%1)"; | |
6676 | ||
6677 | for (i = 0; i < words; i++) | |
6678 | if (refers_to_regno_p (REGNO (operands[2]) + i, | |
6679 | REGNO (operands[2]) + i + 1, operands[1], 0)) | |
6680 | { | |
6681 | if (i == words-1) | |
6682 | { | |
6683 | xop[0] = GEN_INT (4 * (words-1)); | |
6684 | xop[1] = operands[1]; | |
6685 | xop[2] = operands[2]; | |
6686 | output_asm_insn ("{lsi|lswi} %2,%1,%0\n\t{l|lwz} %1,%0(%1)", xop); | |
6687 | return ""; | |
6688 | } | |
6689 | else if (i == 0) | |
6690 | { | |
6691 | xop[0] = GEN_INT (4 * (words-1)); | |
6692 | xop[1] = operands[1]; | |
6693 | xop[2] = gen_rtx_REG (SImode, REGNO (operands[2]) + 1); | |
6694 | output_asm_insn ("{cal %1,4(%1)|addi %1,%1,4}\n\t{lsi|lswi} %2,%1,%0\n\t{l|lwz} %1,-4(%1)", xop); | |
6695 | return ""; | |
6696 | } | |
6697 | else | |
6698 | { | |
6699 | for (j = 0; j < words; j++) | |
6700 | if (j != i) | |
6701 | { | |
6702 | xop[0] = GEN_INT (j * 4); | |
6703 | xop[1] = operands[1]; | |
6704 | xop[2] = gen_rtx_REG (SImode, REGNO (operands[2]) + j); | |
6705 | output_asm_insn ("{l|lwz} %2,%0(%1)", xop); | |
6706 | } | |
6707 | xop[0] = GEN_INT (i * 4); | |
6708 | xop[1] = operands[1]; | |
6709 | output_asm_insn ("{l|lwz} %1,%0(%1)", xop); | |
6710 | return ""; | |
6711 | } | |
6712 | } | |
6713 | ||
6714 | return "{lsi|lswi} %2,%1,%N0"; | |
6715 | } | |
6716 | ||
00b960c7 AH |
6717 | /* Return 1 for a parallel vrsave operation. */ |
6718 | ||
6719 | int | |
6720 | vrsave_operation (op, mode) | |
6721 | rtx op; | |
6722 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
6723 | { | |
6724 | int count = XVECLEN (op, 0); | |
6725 | unsigned int dest_regno, src_regno; | |
6726 | int i; | |
6727 | ||
6728 | if (count <= 1 | |
6729 | || GET_CODE (XVECEXP (op, 0, 0)) != SET | |
6730 | || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG | |
a004eb82 | 6731 | || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC_VOLATILE) |
00b960c7 AH |
6732 | return 0; |
6733 | ||
6734 | dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0))); | |
6735 | src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0))); | |
6736 | ||
6737 | if (dest_regno != VRSAVE_REGNO | |
6738 | && src_regno != VRSAVE_REGNO) | |
6739 | return 0; | |
6740 | ||
6741 | for (i = 1; i < count; i++) | |
6742 | { | |
6743 | rtx elt = XVECEXP (op, 0, i); | |
6744 | ||
9aa86737 AH |
6745 | if (GET_CODE (elt) != CLOBBER |
6746 | && GET_CODE (elt) != SET) | |
00b960c7 AH |
6747 | return 0; |
6748 | } | |
6749 | ||
6750 | return 1; | |
6751 | } | |
6752 | ||
a4f6c312 | 6753 | /* Return 1 for an PARALLEL suitable for mtcrf. */ |
9ebbca7d GK |
6754 | |
6755 | int | |
6756 | mtcrf_operation (op, mode) | |
6757 | rtx op; | |
6758 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
6759 | { | |
6760 | int count = XVECLEN (op, 0); | |
6761 | int i; | |
9ebbca7d GK |
6762 | rtx src_reg; |
6763 | ||
6764 | /* Perform a quick check so we don't blow up below. */ | |
e35b9579 GK |
6765 | if (count < 1 |
6766 | || GET_CODE (XVECEXP (op, 0, 0)) != SET | |
6767 | || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC | |
6768 | || XVECLEN (SET_SRC (XVECEXP (op, 0, 0)), 0) != 2) | |
9ebbca7d | 6769 | return 0; |
e35b9579 | 6770 | src_reg = XVECEXP (SET_SRC (XVECEXP (op, 0, 0)), 0, 0); |
9ebbca7d GK |
6771 | |
6772 | if (GET_CODE (src_reg) != REG | |
6773 | || GET_MODE (src_reg) != SImode | |
6774 | || ! INT_REGNO_P (REGNO (src_reg))) | |
6775 | return 0; | |
6776 | ||
e35b9579 | 6777 | for (i = 0; i < count; i++) |
9ebbca7d GK |
6778 | { |
6779 | rtx exp = XVECEXP (op, 0, i); | |
6780 | rtx unspec; | |
6781 | int maskval; | |
6782 | ||
6783 | if (GET_CODE (exp) != SET | |
6784 | || GET_CODE (SET_DEST (exp)) != REG | |
6785 | || GET_MODE (SET_DEST (exp)) != CCmode | |
6786 | || ! CR_REGNO_P (REGNO (SET_DEST (exp)))) | |
6787 | return 0; | |
6788 | unspec = SET_SRC (exp); | |
6789 | maskval = 1 << (MAX_CR_REGNO - REGNO (SET_DEST (exp))); | |
9ebbca7d GK |
6790 | |
6791 | if (GET_CODE (unspec) != UNSPEC | |
615158e2 | 6792 | || XINT (unspec, 1) != UNSPEC_MOVESI_TO_CR |
9ebbca7d GK |
6793 | || XVECLEN (unspec, 0) != 2 |
6794 | || XVECEXP (unspec, 0, 0) != src_reg | |
6795 | || GET_CODE (XVECEXP (unspec, 0, 1)) != CONST_INT | |
6796 | || INTVAL (XVECEXP (unspec, 0, 1)) != maskval) | |
6797 | return 0; | |
6798 | } | |
e35b9579 | 6799 | return 1; |
9ebbca7d GK |
6800 | } |
6801 | ||
a4f6c312 | 6802 | /* Return 1 for an PARALLEL suitable for lmw. */ |
9ebbca7d GK |
6803 | |
6804 | int | |
6805 | lmw_operation (op, mode) | |
6806 | rtx op; | |
6807 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
6808 | { | |
6809 | int count = XVECLEN (op, 0); | |
e2c953b6 | 6810 | unsigned int dest_regno; |
9ebbca7d | 6811 | rtx src_addr; |
e2c953b6 | 6812 | unsigned int base_regno; |
9ebbca7d GK |
6813 | HOST_WIDE_INT offset; |
6814 | int i; | |
6815 | ||
6816 | /* Perform a quick check so we don't blow up below. */ | |
6817 | if (count <= 1 | |
6818 | || GET_CODE (XVECEXP (op, 0, 0)) != SET | |
6819 | || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG | |
6820 | || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM) | |
6821 | return 0; | |
6822 | ||
6823 | dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0))); | |
6824 | src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0); | |
6825 | ||
6826 | if (dest_regno > 31 | |
e2c953b6 | 6827 | || count != 32 - (int) dest_regno) |
9ebbca7d GK |
6828 | return 0; |
6829 | ||
258bfae2 | 6830 | if (LEGITIMATE_INDIRECT_ADDRESS_P (src_addr, 0)) |
9ebbca7d GK |
6831 | { |
6832 | offset = 0; | |
6833 | base_regno = REGNO (src_addr); | |
6834 | if (base_regno == 0) | |
6835 | return 0; | |
6836 | } | |
258bfae2 | 6837 | else if (LEGITIMATE_OFFSET_ADDRESS_P (SImode, src_addr, 0)) |
9ebbca7d GK |
6838 | { |
6839 | offset = INTVAL (XEXP (src_addr, 1)); | |
6840 | base_regno = REGNO (XEXP (src_addr, 0)); | |
6841 | } | |
6842 | else | |
6843 | return 0; | |
6844 | ||
6845 | for (i = 0; i < count; i++) | |
6846 | { | |
6847 | rtx elt = XVECEXP (op, 0, i); | |
6848 | rtx newaddr; | |
6849 | rtx addr_reg; | |
6850 | HOST_WIDE_INT newoffset; | |
6851 | ||
6852 | if (GET_CODE (elt) != SET | |
6853 | || GET_CODE (SET_DEST (elt)) != REG | |
6854 | || GET_MODE (SET_DEST (elt)) != SImode | |
6855 | || REGNO (SET_DEST (elt)) != dest_regno + i | |
6856 | || GET_CODE (SET_SRC (elt)) != MEM | |
6857 | || GET_MODE (SET_SRC (elt)) != SImode) | |
6858 | return 0; | |
6859 | newaddr = XEXP (SET_SRC (elt), 0); | |
258bfae2 | 6860 | if (LEGITIMATE_INDIRECT_ADDRESS_P (newaddr, 0)) |
9ebbca7d GK |
6861 | { |
6862 | newoffset = 0; | |
6863 | addr_reg = newaddr; | |
6864 | } | |
258bfae2 | 6865 | else if (LEGITIMATE_OFFSET_ADDRESS_P (SImode, newaddr, 0)) |
9ebbca7d GK |
6866 | { |
6867 | addr_reg = XEXP (newaddr, 0); | |
6868 | newoffset = INTVAL (XEXP (newaddr, 1)); | |
6869 | } | |
6870 | else | |
6871 | return 0; | |
6872 | if (REGNO (addr_reg) != base_regno | |
6873 | || newoffset != offset + 4 * i) | |
6874 | return 0; | |
6875 | } | |
6876 | ||
6877 | return 1; | |
6878 | } | |
6879 | ||
a4f6c312 | 6880 | /* Return 1 for an PARALLEL suitable for stmw. */ |
9ebbca7d GK |
6881 | |
6882 | int | |
6883 | stmw_operation (op, mode) | |
6884 | rtx op; | |
6885 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
6886 | { | |
6887 | int count = XVECLEN (op, 0); | |
e2c953b6 | 6888 | unsigned int src_regno; |
9ebbca7d | 6889 | rtx dest_addr; |
e2c953b6 | 6890 | unsigned int base_regno; |
9ebbca7d GK |
6891 | HOST_WIDE_INT offset; |
6892 | int i; | |
6893 | ||
6894 | /* Perform a quick check so we don't blow up below. */ | |
6895 | if (count <= 1 | |
6896 | || GET_CODE (XVECEXP (op, 0, 0)) != SET | |
6897 | || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM | |
6898 | || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG) | |
6899 | return 0; | |
6900 | ||
6901 | src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0))); | |
6902 | dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0); | |
6903 | ||
6904 | if (src_regno > 31 | |
e2c953b6 | 6905 | || count != 32 - (int) src_regno) |
9ebbca7d GK |
6906 | return 0; |
6907 | ||
258bfae2 | 6908 | if (LEGITIMATE_INDIRECT_ADDRESS_P (dest_addr, 0)) |
9ebbca7d GK |
6909 | { |
6910 | offset = 0; | |
6911 | base_regno = REGNO (dest_addr); | |
6912 | if (base_regno == 0) | |
6913 | return 0; | |
6914 | } | |
258bfae2 | 6915 | else if (LEGITIMATE_OFFSET_ADDRESS_P (SImode, dest_addr, 0)) |
9ebbca7d GK |
6916 | { |
6917 | offset = INTVAL (XEXP (dest_addr, 1)); | |
6918 | base_regno = REGNO (XEXP (dest_addr, 0)); | |
6919 | } | |
6920 | else | |
6921 | return 0; | |
6922 | ||
6923 | for (i = 0; i < count; i++) | |
6924 | { | |
6925 | rtx elt = XVECEXP (op, 0, i); | |
6926 | rtx newaddr; | |
6927 | rtx addr_reg; | |
6928 | HOST_WIDE_INT newoffset; | |
6929 | ||
6930 | if (GET_CODE (elt) != SET | |
6931 | || GET_CODE (SET_SRC (elt)) != REG | |
6932 | || GET_MODE (SET_SRC (elt)) != SImode | |
6933 | || REGNO (SET_SRC (elt)) != src_regno + i | |
6934 | || GET_CODE (SET_DEST (elt)) != MEM | |
6935 | || GET_MODE (SET_DEST (elt)) != SImode) | |
6936 | return 0; | |
6937 | newaddr = XEXP (SET_DEST (elt), 0); | |
258bfae2 | 6938 | if (LEGITIMATE_INDIRECT_ADDRESS_P (newaddr, 0)) |
9ebbca7d GK |
6939 | { |
6940 | newoffset = 0; | |
6941 | addr_reg = newaddr; | |
6942 | } | |
258bfae2 | 6943 | else if (LEGITIMATE_OFFSET_ADDRESS_P (SImode, newaddr, 0)) |
9ebbca7d GK |
6944 | { |
6945 | addr_reg = XEXP (newaddr, 0); | |
6946 | newoffset = INTVAL (XEXP (newaddr, 1)); | |
6947 | } | |
6948 | else | |
6949 | return 0; | |
6950 | if (REGNO (addr_reg) != base_regno | |
6951 | || newoffset != offset + 4 * i) | |
6952 | return 0; | |
6953 | } | |
6954 | ||
6955 | return 1; | |
6956 | } | |
9878760c | 6957 | \f |
a4f6c312 SS |
6958 | /* A validation routine: say whether CODE, a condition code, and MODE |
6959 | match. The other alternatives either don't make sense or should | |
6960 | never be generated. */ | |
39a10a29 | 6961 | |
39a10a29 GK |
6962 | static void |
6963 | validate_condition_mode (code, mode) | |
6964 | enum rtx_code code; | |
6965 | enum machine_mode mode; | |
6966 | { | |
6967 | if (GET_RTX_CLASS (code) != '<' | |
6968 | || GET_MODE_CLASS (mode) != MODE_CC) | |
6969 | abort (); | |
6970 | ||
6971 | /* These don't make sense. */ | |
6972 | if ((code == GT || code == LT || code == GE || code == LE) | |
6973 | && mode == CCUNSmode) | |
6974 | abort (); | |
6975 | ||
6976 | if ((code == GTU || code == LTU || code == GEU || code == LEU) | |
6977 | && mode != CCUNSmode) | |
6978 | abort (); | |
6979 | ||
6980 | if (mode != CCFPmode | |
6981 | && (code == ORDERED || code == UNORDERED | |
6982 | || code == UNEQ || code == LTGT | |
6983 | || code == UNGT || code == UNLT | |
6984 | || code == UNGE || code == UNLE)) | |
a4f6c312 | 6985 | abort (); |
39a10a29 | 6986 | |
de6c5979 | 6987 | /* These should never be generated except for |
ad72b533 | 6988 | flag_unsafe_math_optimizations and flag_finite_math_only. */ |
39a10a29 | 6989 | if (mode == CCFPmode |
de6c5979 | 6990 | && ! flag_unsafe_math_optimizations |
ad72b533 | 6991 | && ! flag_finite_math_only |
39a10a29 GK |
6992 | && (code == LE || code == GE |
6993 | || code == UNEQ || code == LTGT | |
6994 | || code == UNGT || code == UNLT)) | |
6995 | abort (); | |
6996 | ||
6997 | /* These are invalid; the information is not there. */ | |
6998 | if (mode == CCEQmode | |
6999 | && code != EQ && code != NE) | |
7000 | abort (); | |
7001 | } | |
7002 | ||
9878760c RK |
7003 | /* Return 1 if OP is a comparison operation that is valid for a branch insn. |
7004 | We only check the opcode against the mode of the CC value here. */ | |
7005 | ||
7006 | int | |
7007 | branch_comparison_operator (op, mode) | |
592696dd | 7008 | rtx op; |
296b8152 | 7009 | enum machine_mode mode ATTRIBUTE_UNUSED; |
9878760c RK |
7010 | { |
7011 | enum rtx_code code = GET_CODE (op); | |
7012 | enum machine_mode cc_mode; | |
7013 | ||
7014 | if (GET_RTX_CLASS (code) != '<') | |
7015 | return 0; | |
7016 | ||
7017 | cc_mode = GET_MODE (XEXP (op, 0)); | |
7018 | if (GET_MODE_CLASS (cc_mode) != MODE_CC) | |
7019 | return 0; | |
7020 | ||
39a10a29 | 7021 | validate_condition_mode (code, cc_mode); |
9878760c | 7022 | |
39a10a29 GK |
7023 | return 1; |
7024 | } | |
7025 | ||
7026 | /* Return 1 if OP is a comparison operation that is valid for a branch | |
7027 | insn and which is true if the corresponding bit in the CC register | |
7028 | is set. */ | |
7029 | ||
7030 | int | |
7031 | branch_positive_comparison_operator (op, mode) | |
592696dd | 7032 | rtx op; |
39a10a29 GK |
7033 | enum machine_mode mode; |
7034 | { | |
7035 | enum rtx_code code; | |
7036 | ||
7037 | if (! branch_comparison_operator (op, mode)) | |
9878760c RK |
7038 | return 0; |
7039 | ||
39a10a29 GK |
7040 | code = GET_CODE (op); |
7041 | return (code == EQ || code == LT || code == GT | |
993f19a8 | 7042 | || (TARGET_E500 && TARGET_HARD_FLOAT && !TARGET_FPRS && code == NE) |
39a10a29 GK |
7043 | || code == LTU || code == GTU |
7044 | || code == UNORDERED); | |
9878760c RK |
7045 | } |
7046 | ||
7047 | /* Return 1 if OP is a comparison operation that is valid for an scc insn. | |
7048 | We check the opcode against the mode of the CC value and disallow EQ or | |
7049 | NE comparisons for integers. */ | |
7050 | ||
7051 | int | |
7052 | scc_comparison_operator (op, mode) | |
592696dd | 7053 | rtx op; |
9878760c RK |
7054 | enum machine_mode mode; |
7055 | { | |
7056 | enum rtx_code code = GET_CODE (op); | |
7057 | enum machine_mode cc_mode; | |
7058 | ||
7059 | if (GET_MODE (op) != mode && mode != VOIDmode) | |
7060 | return 0; | |
7061 | ||
7062 | if (GET_RTX_CLASS (code) != '<') | |
7063 | return 0; | |
7064 | ||
7065 | cc_mode = GET_MODE (XEXP (op, 0)); | |
7066 | if (GET_MODE_CLASS (cc_mode) != MODE_CC) | |
7067 | return 0; | |
7068 | ||
39a10a29 | 7069 | validate_condition_mode (code, cc_mode); |
9878760c | 7070 | |
39a10a29 | 7071 | if (code == NE && cc_mode != CCFPmode) |
c5defebb RK |
7072 | return 0; |
7073 | ||
9878760c RK |
7074 | return 1; |
7075 | } | |
e0cd0770 JC |
7076 | |
7077 | int | |
7078 | trap_comparison_operator (op, mode) | |
7079 | rtx op; | |
7080 | enum machine_mode mode; | |
7081 | { | |
7082 | if (mode != VOIDmode && mode != GET_MODE (op)) | |
7083 | return 0; | |
39a10a29 | 7084 | return GET_RTX_CLASS (GET_CODE (op)) == '<'; |
e0cd0770 | 7085 | } |
dfbdccdb GK |
7086 | |
7087 | int | |
7088 | boolean_operator (op, mode) | |
7089 | rtx op; | |
7090 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
7091 | { | |
7092 | enum rtx_code code = GET_CODE (op); | |
7093 | return (code == AND || code == IOR || code == XOR); | |
7094 | } | |
1d328b19 GK |
7095 | |
7096 | int | |
7097 | boolean_or_operator (op, mode) | |
7098 | rtx op; | |
7099 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
7100 | { | |
7101 | enum rtx_code code = GET_CODE (op); | |
7102 | return (code == IOR || code == XOR); | |
7103 | } | |
50a0b056 GK |
7104 | |
7105 | int | |
7106 | min_max_operator (op, mode) | |
7107 | rtx op; | |
7108 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
7109 | { | |
7110 | enum rtx_code code = GET_CODE (op); | |
7111 | return (code == SMIN || code == SMAX || code == UMIN || code == UMAX); | |
7112 | } | |
9878760c RK |
7113 | \f |
7114 | /* Return 1 if ANDOP is a mask that has no bits on that are not in the | |
7115 | mask required to convert the result of a rotate insn into a shift | |
b1765bde | 7116 | left insn of SHIFTOP bits. Both are known to be SImode CONST_INT. */ |
9878760c RK |
7117 | |
7118 | int | |
7119 | includes_lshift_p (shiftop, andop) | |
592696dd SS |
7120 | rtx shiftop; |
7121 | rtx andop; | |
9878760c | 7122 | { |
e2c953b6 DE |
7123 | unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0; |
7124 | ||
7125 | shift_mask <<= INTVAL (shiftop); | |
9878760c | 7126 | |
b1765bde | 7127 | return (INTVAL (andop) & 0xffffffff & ~shift_mask) == 0; |
9878760c RK |
7128 | } |
7129 | ||
7130 | /* Similar, but for right shift. */ | |
7131 | ||
7132 | int | |
7133 | includes_rshift_p (shiftop, andop) | |
592696dd SS |
7134 | rtx shiftop; |
7135 | rtx andop; | |
9878760c | 7136 | { |
a7653a2c | 7137 | unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0; |
9878760c RK |
7138 | |
7139 | shift_mask >>= INTVAL (shiftop); | |
7140 | ||
b1765bde | 7141 | return (INTVAL (andop) & 0xffffffff & ~shift_mask) == 0; |
e2c953b6 DE |
7142 | } |
7143 | ||
c5059423 AM |
7144 | /* Return 1 if ANDOP is a mask suitable for use with an rldic insn |
7145 | to perform a left shift. It must have exactly SHIFTOP least | |
b6d08ca1 | 7146 | significant 0's, then one or more 1's, then zero or more 0's. */ |
e2c953b6 DE |
7147 | |
7148 | int | |
c5059423 | 7149 | includes_rldic_lshift_p (shiftop, andop) |
592696dd SS |
7150 | rtx shiftop; |
7151 | rtx andop; | |
e2c953b6 | 7152 | { |
c5059423 AM |
7153 | if (GET_CODE (andop) == CONST_INT) |
7154 | { | |
02071907 | 7155 | HOST_WIDE_INT c, lsb, shift_mask; |
e2c953b6 | 7156 | |
c5059423 | 7157 | c = INTVAL (andop); |
02071907 | 7158 | if (c == 0 || c == ~0) |
c5059423 | 7159 | return 0; |
e2c953b6 | 7160 | |
02071907 | 7161 | shift_mask = ~0; |
c5059423 AM |
7162 | shift_mask <<= INTVAL (shiftop); |
7163 | ||
b6d08ca1 | 7164 | /* Find the least significant one bit. */ |
c5059423 AM |
7165 | lsb = c & -c; |
7166 | ||
7167 | /* It must coincide with the LSB of the shift mask. */ | |
7168 | if (-lsb != shift_mask) | |
7169 | return 0; | |
e2c953b6 | 7170 | |
c5059423 AM |
7171 | /* Invert to look for the next transition (if any). */ |
7172 | c = ~c; | |
7173 | ||
7174 | /* Remove the low group of ones (originally low group of zeros). */ | |
7175 | c &= -lsb; | |
7176 | ||
7177 | /* Again find the lsb, and check we have all 1's above. */ | |
7178 | lsb = c & -c; | |
7179 | return c == -lsb; | |
7180 | } | |
7181 | else if (GET_CODE (andop) == CONST_DOUBLE | |
7182 | && (GET_MODE (andop) == VOIDmode || GET_MODE (andop) == DImode)) | |
7183 | { | |
02071907 AM |
7184 | HOST_WIDE_INT low, high, lsb; |
7185 | HOST_WIDE_INT shift_mask_low, shift_mask_high; | |
c5059423 AM |
7186 | |
7187 | low = CONST_DOUBLE_LOW (andop); | |
7188 | if (HOST_BITS_PER_WIDE_INT < 64) | |
7189 | high = CONST_DOUBLE_HIGH (andop); | |
7190 | ||
7191 | if ((low == 0 && (HOST_BITS_PER_WIDE_INT >= 64 || high == 0)) | |
02071907 | 7192 | || (low == ~0 && (HOST_BITS_PER_WIDE_INT >= 64 || high == ~0))) |
c5059423 AM |
7193 | return 0; |
7194 | ||
7195 | if (HOST_BITS_PER_WIDE_INT < 64 && low == 0) | |
7196 | { | |
02071907 | 7197 | shift_mask_high = ~0; |
c5059423 AM |
7198 | if (INTVAL (shiftop) > 32) |
7199 | shift_mask_high <<= INTVAL (shiftop) - 32; | |
7200 | ||
7201 | lsb = high & -high; | |
7202 | ||
7203 | if (-lsb != shift_mask_high || INTVAL (shiftop) < 32) | |
7204 | return 0; | |
7205 | ||
7206 | high = ~high; | |
7207 | high &= -lsb; | |
7208 | ||
7209 | lsb = high & -high; | |
7210 | return high == -lsb; | |
7211 | } | |
7212 | ||
02071907 | 7213 | shift_mask_low = ~0; |
c5059423 AM |
7214 | shift_mask_low <<= INTVAL (shiftop); |
7215 | ||
7216 | lsb = low & -low; | |
7217 | ||
7218 | if (-lsb != shift_mask_low) | |
7219 | return 0; | |
7220 | ||
7221 | if (HOST_BITS_PER_WIDE_INT < 64) | |
7222 | high = ~high; | |
7223 | low = ~low; | |
7224 | low &= -lsb; | |
7225 | ||
7226 | if (HOST_BITS_PER_WIDE_INT < 64 && low == 0) | |
7227 | { | |
7228 | lsb = high & -high; | |
7229 | return high == -lsb; | |
7230 | } | |
7231 | ||
7232 | lsb = low & -low; | |
7233 | return low == -lsb && (HOST_BITS_PER_WIDE_INT >= 64 || high == ~0); | |
7234 | } | |
7235 | else | |
7236 | return 0; | |
7237 | } | |
e2c953b6 | 7238 | |
c5059423 AM |
7239 | /* Return 1 if ANDOP is a mask suitable for use with an rldicr insn |
7240 | to perform a left shift. It must have SHIFTOP or more least | |
7241 | signifigant 0's, with the remainder of the word 1's. */ | |
e2c953b6 | 7242 | |
c5059423 AM |
7243 | int |
7244 | includes_rldicr_lshift_p (shiftop, andop) | |
592696dd SS |
7245 | rtx shiftop; |
7246 | rtx andop; | |
c5059423 | 7247 | { |
e2c953b6 | 7248 | if (GET_CODE (andop) == CONST_INT) |
c5059423 | 7249 | { |
02071907 | 7250 | HOST_WIDE_INT c, lsb, shift_mask; |
c5059423 | 7251 | |
02071907 | 7252 | shift_mask = ~0; |
c5059423 AM |
7253 | shift_mask <<= INTVAL (shiftop); |
7254 | c = INTVAL (andop); | |
7255 | ||
7256 | /* Find the least signifigant one bit. */ | |
7257 | lsb = c & -c; | |
7258 | ||
7259 | /* It must be covered by the shift mask. | |
a4f6c312 | 7260 | This test also rejects c == 0. */ |
c5059423 AM |
7261 | if ((lsb & shift_mask) == 0) |
7262 | return 0; | |
7263 | ||
7264 | /* Check we have all 1's above the transition, and reject all 1's. */ | |
7265 | return c == -lsb && lsb != 1; | |
7266 | } | |
7267 | else if (GET_CODE (andop) == CONST_DOUBLE | |
7268 | && (GET_MODE (andop) == VOIDmode || GET_MODE (andop) == DImode)) | |
7269 | { | |
02071907 | 7270 | HOST_WIDE_INT low, lsb, shift_mask_low; |
c5059423 AM |
7271 | |
7272 | low = CONST_DOUBLE_LOW (andop); | |
7273 | ||
7274 | if (HOST_BITS_PER_WIDE_INT < 64) | |
7275 | { | |
02071907 | 7276 | HOST_WIDE_INT high, shift_mask_high; |
c5059423 AM |
7277 | |
7278 | high = CONST_DOUBLE_HIGH (andop); | |
7279 | ||
7280 | if (low == 0) | |
7281 | { | |
02071907 | 7282 | shift_mask_high = ~0; |
c5059423 AM |
7283 | if (INTVAL (shiftop) > 32) |
7284 | shift_mask_high <<= INTVAL (shiftop) - 32; | |
7285 | ||
7286 | lsb = high & -high; | |
7287 | ||
7288 | if ((lsb & shift_mask_high) == 0) | |
7289 | return 0; | |
7290 | ||
7291 | return high == -lsb; | |
7292 | } | |
7293 | if (high != ~0) | |
7294 | return 0; | |
7295 | } | |
7296 | ||
02071907 | 7297 | shift_mask_low = ~0; |
c5059423 AM |
7298 | shift_mask_low <<= INTVAL (shiftop); |
7299 | ||
7300 | lsb = low & -low; | |
7301 | ||
7302 | if ((lsb & shift_mask_low) == 0) | |
7303 | return 0; | |
7304 | ||
7305 | return low == -lsb && lsb != 1; | |
7306 | } | |
e2c953b6 | 7307 | else |
c5059423 | 7308 | return 0; |
9878760c | 7309 | } |
35068b43 RK |
7310 | |
7311 | /* Return 1 if REGNO (reg1) == REGNO (reg2) - 1 making them candidates | |
7312 | for lfq and stfq insns. | |
7313 | ||
7314 | Note reg1 and reg2 *must* be hard registers. To be sure we will | |
7315 | abort if we are passed pseudo registers. */ | |
7316 | ||
7317 | int | |
7318 | registers_ok_for_quad_peep (reg1, reg2) | |
7319 | rtx reg1, reg2; | |
7320 | { | |
7321 | /* We might have been passed a SUBREG. */ | |
7322 | if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG) | |
7323 | return 0; | |
7324 | ||
7325 | return (REGNO (reg1) == REGNO (reg2) - 1); | |
7326 | } | |
7327 | ||
a4f6c312 SS |
7328 | /* Return 1 if addr1 and addr2 are suitable for lfq or stfq insn. |
7329 | addr1 and addr2 must be in consecutive memory locations | |
7330 | (addr2 == addr1 + 8). */ | |
35068b43 RK |
7331 | |
7332 | int | |
7333 | addrs_ok_for_quad_peep (addr1, addr2) | |
592696dd SS |
7334 | rtx addr1; |
7335 | rtx addr2; | |
35068b43 | 7336 | { |
e2c953b6 | 7337 | unsigned int reg1; |
35068b43 RK |
7338 | int offset1; |
7339 | ||
7340 | /* Extract an offset (if used) from the first addr. */ | |
7341 | if (GET_CODE (addr1) == PLUS) | |
7342 | { | |
7343 | /* If not a REG, return zero. */ | |
7344 | if (GET_CODE (XEXP (addr1, 0)) != REG) | |
7345 | return 0; | |
7346 | else | |
7347 | { | |
7348 | reg1 = REGNO (XEXP (addr1, 0)); | |
7349 | /* The offset must be constant! */ | |
7350 | if (GET_CODE (XEXP (addr1, 1)) != CONST_INT) | |
7351 | return 0; | |
7352 | offset1 = INTVAL (XEXP (addr1, 1)); | |
7353 | } | |
7354 | } | |
7355 | else if (GET_CODE (addr1) != REG) | |
7356 | return 0; | |
7357 | else | |
7358 | { | |
7359 | reg1 = REGNO (addr1); | |
7360 | /* This was a simple (mem (reg)) expression. Offset is 0. */ | |
7361 | offset1 = 0; | |
7362 | } | |
7363 | ||
984e25ac DE |
7364 | /* Make sure the second address is a (mem (plus (reg) (const_int))) |
7365 | or if it is (mem (reg)) then make sure that offset1 is -8 and the same | |
7366 | register as addr1. */ | |
7367 | if (offset1 == -8 && GET_CODE (addr2) == REG && reg1 == REGNO (addr2)) | |
7368 | return 1; | |
35068b43 RK |
7369 | if (GET_CODE (addr2) != PLUS) |
7370 | return 0; | |
7371 | ||
7372 | if (GET_CODE (XEXP (addr2, 0)) != REG | |
7373 | || GET_CODE (XEXP (addr2, 1)) != CONST_INT) | |
7374 | return 0; | |
7375 | ||
7376 | if (reg1 != REGNO (XEXP (addr2, 0))) | |
7377 | return 0; | |
7378 | ||
7379 | /* The offset for the second addr must be 8 more than the first addr. */ | |
7380 | if (INTVAL (XEXP (addr2, 1)) != offset1 + 8) | |
7381 | return 0; | |
7382 | ||
7383 | /* All the tests passed. addr1 and addr2 are valid for lfq or stfq | |
7384 | instructions. */ | |
7385 | return 1; | |
7386 | } | |
9878760c RK |
7387 | \f |
7388 | /* Return the register class of a scratch register needed to copy IN into | |
7389 | or out of a register in CLASS in MODE. If it can be done directly, | |
7390 | NO_REGS is returned. */ | |
7391 | ||
7392 | enum reg_class | |
7393 | secondary_reload_class (class, mode, in) | |
7394 | enum reg_class class; | |
296b8152 | 7395 | enum machine_mode mode ATTRIBUTE_UNUSED; |
9878760c RK |
7396 | rtx in; |
7397 | { | |
5accd822 | 7398 | int regno; |
9878760c | 7399 | |
ab82a49f AP |
7400 | if (TARGET_ELF || (DEFAULT_ABI == ABI_DARWIN |
7401 | #if TARGET_MACHO | |
7402 | && MACHOPIC_INDIRECT | |
7403 | #endif | |
7404 | )) | |
46fad5b7 DJ |
7405 | { |
7406 | /* We cannot copy a symbolic operand directly into anything | |
7407 | other than BASE_REGS for TARGET_ELF. So indicate that a | |
7408 | register from BASE_REGS is needed as an intermediate | |
7409 | register. | |
7410 | ||
7411 | On Darwin, pic addresses require a load from memory, which | |
7412 | needs a base register. */ | |
7413 | if (class != BASE_REGS | |
7414 | && (GET_CODE (in) == SYMBOL_REF | |
7415 | || GET_CODE (in) == HIGH | |
7416 | || GET_CODE (in) == LABEL_REF | |
7417 | || GET_CODE (in) == CONST)) | |
7418 | return BASE_REGS; | |
7419 | } | |
e7b7998a | 7420 | |
5accd822 DE |
7421 | if (GET_CODE (in) == REG) |
7422 | { | |
7423 | regno = REGNO (in); | |
7424 | if (regno >= FIRST_PSEUDO_REGISTER) | |
7425 | { | |
7426 | regno = true_regnum (in); | |
7427 | if (regno >= FIRST_PSEUDO_REGISTER) | |
7428 | regno = -1; | |
7429 | } | |
7430 | } | |
7431 | else if (GET_CODE (in) == SUBREG) | |
7432 | { | |
7433 | regno = true_regnum (in); | |
7434 | if (regno >= FIRST_PSEUDO_REGISTER) | |
7435 | regno = -1; | |
7436 | } | |
7437 | else | |
7438 | regno = -1; | |
7439 | ||
9878760c RK |
7440 | /* We can place anything into GENERAL_REGS and can put GENERAL_REGS |
7441 | into anything. */ | |
7442 | if (class == GENERAL_REGS || class == BASE_REGS | |
7443 | || (regno >= 0 && INT_REGNO_P (regno))) | |
7444 | return NO_REGS; | |
7445 | ||
7446 | /* Constants, memory, and FP registers can go into FP registers. */ | |
7447 | if ((regno == -1 || FP_REGNO_P (regno)) | |
7448 | && (class == FLOAT_REGS || class == NON_SPECIAL_REGS)) | |
7449 | return NO_REGS; | |
7450 | ||
0ac081f6 AH |
7451 | /* Memory, and AltiVec registers can go into AltiVec registers. */ |
7452 | if ((regno == -1 || ALTIVEC_REGNO_P (regno)) | |
7453 | && class == ALTIVEC_REGS) | |
7454 | return NO_REGS; | |
7455 | ||
9878760c RK |
7456 | /* We can copy among the CR registers. */ |
7457 | if ((class == CR_REGS || class == CR0_REGS) | |
7458 | && regno >= 0 && CR_REGNO_P (regno)) | |
7459 | return NO_REGS; | |
7460 | ||
7461 | /* Otherwise, we need GENERAL_REGS. */ | |
7462 | return GENERAL_REGS; | |
7463 | } | |
7464 | \f | |
7465 | /* Given a comparison operation, return the bit number in CCR to test. We | |
7466 | know this is a valid comparison. | |
7467 | ||
7468 | SCC_P is 1 if this is for an scc. That means that %D will have been | |
7469 | used instead of %C, so the bits will be in different places. | |
7470 | ||
b4ac57ab | 7471 | Return -1 if OP isn't a valid comparison for some reason. */ |
9878760c RK |
7472 | |
7473 | int | |
7474 | ccr_bit (op, scc_p) | |
592696dd | 7475 | rtx op; |
9878760c RK |
7476 | int scc_p; |
7477 | { | |
7478 | enum rtx_code code = GET_CODE (op); | |
7479 | enum machine_mode cc_mode; | |
7480 | int cc_regnum; | |
7481 | int base_bit; | |
9ebbca7d | 7482 | rtx reg; |
9878760c RK |
7483 | |
7484 | if (GET_RTX_CLASS (code) != '<') | |
7485 | return -1; | |
7486 | ||
9ebbca7d GK |
7487 | reg = XEXP (op, 0); |
7488 | ||
7489 | if (GET_CODE (reg) != REG | |
7490 | || ! CR_REGNO_P (REGNO (reg))) | |
7491 | abort (); | |
7492 | ||
7493 | cc_mode = GET_MODE (reg); | |
7494 | cc_regnum = REGNO (reg); | |
7495 | base_bit = 4 * (cc_regnum - CR0_REGNO); | |
9878760c | 7496 | |
39a10a29 | 7497 | validate_condition_mode (code, cc_mode); |
c5defebb | 7498 | |
9878760c RK |
7499 | switch (code) |
7500 | { | |
7501 | case NE: | |
993f19a8 AH |
7502 | if (TARGET_E500 && !TARGET_FPRS |
7503 | && TARGET_HARD_FLOAT && cc_mode == CCFPmode) | |
a3170dc6 | 7504 | return base_bit + 1; |
9878760c RK |
7505 | return scc_p ? base_bit + 3 : base_bit + 2; |
7506 | case EQ: | |
993f19a8 AH |
7507 | if (TARGET_E500 && !TARGET_FPRS |
7508 | && TARGET_HARD_FLOAT && cc_mode == CCFPmode) | |
a3170dc6 | 7509 | return base_bit + 1; |
9878760c | 7510 | return base_bit + 2; |
1c882ea4 | 7511 | case GT: case GTU: case UNLE: |
9878760c | 7512 | return base_bit + 1; |
1c882ea4 | 7513 | case LT: case LTU: case UNGE: |
9878760c | 7514 | return base_bit; |
1c882ea4 GK |
7515 | case ORDERED: case UNORDERED: |
7516 | return base_bit + 3; | |
9878760c RK |
7517 | |
7518 | case GE: case GEU: | |
39a10a29 | 7519 | /* If scc, we will have done a cror to put the bit in the |
9878760c RK |
7520 | unordered position. So test that bit. For integer, this is ! LT |
7521 | unless this is an scc insn. */ | |
39a10a29 | 7522 | return scc_p ? base_bit + 3 : base_bit; |
9878760c RK |
7523 | |
7524 | case LE: case LEU: | |
39a10a29 | 7525 | return scc_p ? base_bit + 3 : base_bit + 1; |
1c882ea4 | 7526 | |
9878760c RK |
7527 | default: |
7528 | abort (); | |
7529 | } | |
7530 | } | |
1ff7789b | 7531 | \f |
8d30c4ee | 7532 | /* Return the GOT register. */ |
1ff7789b MM |
7533 | |
7534 | struct rtx_def * | |
7535 | rs6000_got_register (value) | |
5f59ecb7 | 7536 | rtx value ATTRIBUTE_UNUSED; |
1ff7789b | 7537 | { |
a4f6c312 SS |
7538 | /* The second flow pass currently (June 1999) can't update |
7539 | regs_ever_live without disturbing other parts of the compiler, so | |
7540 | update it here to make the prolog/epilogue code happy. */ | |
1db02437 FS |
7541 | if (no_new_pseudos && ! regs_ever_live[RS6000_PIC_OFFSET_TABLE_REGNUM]) |
7542 | regs_ever_live[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1; | |
1ff7789b | 7543 | |
8d30c4ee | 7544 | current_function_uses_pic_offset_table = 1; |
3cb999d8 | 7545 | |
1ff7789b MM |
7546 | return pic_offset_table_rtx; |
7547 | } | |
a7df97e6 | 7548 | \f |
e2500fed GK |
7549 | /* Function to init struct machine_function. |
7550 | This will be called, via a pointer variable, | |
7551 | from push_function_context. */ | |
a7df97e6 | 7552 | |
e2500fed GK |
7553 | static struct machine_function * |
7554 | rs6000_init_machine_status () | |
a7df97e6 | 7555 | { |
e2500fed | 7556 | return ggc_alloc_cleared (sizeof (machine_function)); |
a7df97e6 | 7557 | } |
9878760c | 7558 | \f |
0ba1b2ff AM |
7559 | /* These macros test for integers and extract the low-order bits. */ |
7560 | #define INT_P(X) \ | |
7561 | ((GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST_DOUBLE) \ | |
7562 | && GET_MODE (X) == VOIDmode) | |
7563 | ||
7564 | #define INT_LOWPART(X) \ | |
7565 | (GET_CODE (X) == CONST_INT ? INTVAL (X) : CONST_DOUBLE_LOW (X)) | |
7566 | ||
7567 | int | |
7568 | extract_MB (op) | |
7569 | rtx op; | |
7570 | { | |
7571 | int i; | |
7572 | unsigned long val = INT_LOWPART (op); | |
7573 | ||
7574 | /* If the high bit is zero, the value is the first 1 bit we find | |
7575 | from the left. */ | |
7576 | if ((val & 0x80000000) == 0) | |
7577 | { | |
7578 | if ((val & 0xffffffff) == 0) | |
7579 | abort (); | |
7580 | ||
7581 | i = 1; | |
7582 | while (((val <<= 1) & 0x80000000) == 0) | |
7583 | ++i; | |
7584 | return i; | |
7585 | } | |
7586 | ||
7587 | /* If the high bit is set and the low bit is not, or the mask is all | |
7588 | 1's, the value is zero. */ | |
7589 | if ((val & 1) == 0 || (val & 0xffffffff) == 0xffffffff) | |
7590 | return 0; | |
7591 | ||
7592 | /* Otherwise we have a wrap-around mask. Look for the first 0 bit | |
7593 | from the right. */ | |
7594 | i = 31; | |
7595 | while (((val >>= 1) & 1) != 0) | |
7596 | --i; | |
7597 | ||
7598 | return i; | |
7599 | } | |
7600 | ||
7601 | int | |
7602 | extract_ME (op) | |
7603 | rtx op; | |
7604 | { | |
7605 | int i; | |
7606 | unsigned long val = INT_LOWPART (op); | |
7607 | ||
7608 | /* If the low bit is zero, the value is the first 1 bit we find from | |
7609 | the right. */ | |
7610 | if ((val & 1) == 0) | |
7611 | { | |
7612 | if ((val & 0xffffffff) == 0) | |
7613 | abort (); | |
7614 | ||
7615 | i = 30; | |
7616 | while (((val >>= 1) & 1) == 0) | |
7617 | --i; | |
7618 | ||
7619 | return i; | |
7620 | } | |
7621 | ||
7622 | /* If the low bit is set and the high bit is not, or the mask is all | |
7623 | 1's, the value is 31. */ | |
7624 | if ((val & 0x80000000) == 0 || (val & 0xffffffff) == 0xffffffff) | |
7625 | return 31; | |
7626 | ||
7627 | /* Otherwise we have a wrap-around mask. Look for the first 0 bit | |
7628 | from the left. */ | |
7629 | i = 0; | |
7630 | while (((val <<= 1) & 0x80000000) != 0) | |
7631 | ++i; | |
7632 | ||
7633 | return i; | |
7634 | } | |
7635 | ||
9878760c RK |
7636 | /* Print an operand. Recognize special options, documented below. */ |
7637 | ||
38c1f2d7 | 7638 | #if TARGET_ELF |
d9407988 | 7639 | #define SMALL_DATA_RELOC ((rs6000_sdata == SDATA_EABI) ? "sda21" : "sdarel") |
8fbd2dc7 | 7640 | #define SMALL_DATA_REG ((rs6000_sdata == SDATA_EABI) ? 0 : 13) |
ba5e43aa MM |
7641 | #else |
7642 | #define SMALL_DATA_RELOC "sda21" | |
8fbd2dc7 | 7643 | #define SMALL_DATA_REG 0 |
ba5e43aa MM |
7644 | #endif |
7645 | ||
9878760c RK |
7646 | void |
7647 | print_operand (file, x, code) | |
7648 | FILE *file; | |
7649 | rtx x; | |
9ebbca7d | 7650 | int code; |
9878760c RK |
7651 | { |
7652 | int i; | |
a260abc9 | 7653 | HOST_WIDE_INT val; |
0ba1b2ff | 7654 | unsigned HOST_WIDE_INT uval; |
9878760c RK |
7655 | |
7656 | switch (code) | |
7657 | { | |
a8b3aeda | 7658 | case '.': |
a85d226b RK |
7659 | /* Write out an instruction after the call which may be replaced |
7660 | with glue code by the loader. This depends on the AIX version. */ | |
7661 | asm_fprintf (file, RS6000_CALL_GLUE); | |
a8b3aeda RK |
7662 | return; |
7663 | ||
81eace42 GK |
7664 | /* %a is output_address. */ |
7665 | ||
9854d9ed RK |
7666 | case 'A': |
7667 | /* If X is a constant integer whose low-order 5 bits are zero, | |
7668 | write 'l'. Otherwise, write 'r'. This is a kludge to fix a bug | |
76229ac8 | 7669 | in the AIX assembler where "sri" with a zero shift count |
20e26713 | 7670 | writes a trash instruction. */ |
9854d9ed | 7671 | if (GET_CODE (x) == CONST_INT && (INTVAL (x) & 31) == 0) |
76229ac8 | 7672 | putc ('l', file); |
9854d9ed | 7673 | else |
76229ac8 | 7674 | putc ('r', file); |
9854d9ed RK |
7675 | return; |
7676 | ||
7677 | case 'b': | |
e2c953b6 DE |
7678 | /* If constant, low-order 16 bits of constant, unsigned. |
7679 | Otherwise, write normally. */ | |
7680 | if (INT_P (x)) | |
7681 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 0xffff); | |
7682 | else | |
7683 | print_operand (file, x, 0); | |
cad12a8d RK |
7684 | return; |
7685 | ||
a260abc9 DE |
7686 | case 'B': |
7687 | /* If the low-order bit is zero, write 'r'; otherwise, write 'l' | |
7688 | for 64-bit mask direction. */ | |
296b8152 | 7689 | putc (((INT_LOWPART(x) & 1) == 0 ? 'r' : 'l'), file); |
a238cd8b | 7690 | return; |
a260abc9 | 7691 | |
81eace42 GK |
7692 | /* %c is output_addr_const if a CONSTANT_ADDRESS_P, otherwise |
7693 | output_operand. */ | |
7694 | ||
9854d9ed | 7695 | case 'D': |
39a10a29 GK |
7696 | /* There used to be a comment for 'C' reading "This is an |
7697 | optional cror needed for certain floating-point | |
7698 | comparisons. Otherwise write nothing." */ | |
7699 | ||
9854d9ed RK |
7700 | /* Similar, except that this is for an scc, so we must be able to |
7701 | encode the test in a single bit that is one. We do the above | |
7702 | for any LE, GE, GEU, or LEU and invert the bit for NE. */ | |
7703 | if (GET_CODE (x) == LE || GET_CODE (x) == GE | |
7704 | || GET_CODE (x) == LEU || GET_CODE (x) == GEU) | |
7705 | { | |
9ebbca7d | 7706 | int base_bit = 4 * (REGNO (XEXP (x, 0)) - CR0_REGNO); |
9854d9ed RK |
7707 | |
7708 | fprintf (file, "cror %d,%d,%d\n\t", base_bit + 3, | |
7709 | base_bit + 2, | |
7710 | base_bit + (GET_CODE (x) == GE || GET_CODE (x) == GEU)); | |
7711 | } | |
7712 | ||
7713 | else if (GET_CODE (x) == NE) | |
7714 | { | |
9ebbca7d | 7715 | int base_bit = 4 * (REGNO (XEXP (x, 0)) - CR0_REGNO); |
9854d9ed RK |
7716 | |
7717 | fprintf (file, "crnor %d,%d,%d\n\t", base_bit + 3, | |
7718 | base_bit + 2, base_bit + 2); | |
7719 | } | |
993f19a8 | 7720 | else if (TARGET_E500 && !TARGET_FPRS && TARGET_HARD_FLOAT |
a3170dc6 AH |
7721 | && GET_CODE (x) == EQ |
7722 | && GET_MODE (XEXP (x, 0)) == CCFPmode) | |
7723 | { | |
7724 | int base_bit = 4 * (REGNO (XEXP (x, 0)) - CR0_REGNO); | |
7725 | ||
7726 | fprintf (file, "crnor %d,%d,%d\n\t", base_bit + 1, | |
7727 | base_bit + 1, base_bit + 1); | |
7728 | } | |
9854d9ed RK |
7729 | return; |
7730 | ||
7731 | case 'E': | |
39a10a29 | 7732 | /* X is a CR register. Print the number of the EQ bit of the CR */ |
9854d9ed RK |
7733 | if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x))) |
7734 | output_operand_lossage ("invalid %%E value"); | |
78fbdbf7 | 7735 | else |
39a10a29 | 7736 | fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO) + 2); |
a85d226b | 7737 | return; |
9854d9ed RK |
7738 | |
7739 | case 'f': | |
7740 | /* X is a CR register. Print the shift count needed to move it | |
7741 | to the high-order four bits. */ | |
7742 | if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x))) | |
7743 | output_operand_lossage ("invalid %%f value"); | |
7744 | else | |
9ebbca7d | 7745 | fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO)); |
9854d9ed RK |
7746 | return; |
7747 | ||
7748 | case 'F': | |
7749 | /* Similar, but print the count for the rotate in the opposite | |
7750 | direction. */ | |
7751 | if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x))) | |
7752 | output_operand_lossage ("invalid %%F value"); | |
7753 | else | |
9ebbca7d | 7754 | fprintf (file, "%d", 32 - 4 * (REGNO (x) - CR0_REGNO)); |
9854d9ed RK |
7755 | return; |
7756 | ||
7757 | case 'G': | |
7758 | /* X is a constant integer. If it is negative, print "m", | |
43aa4e05 | 7759 | otherwise print "z". This is to make an aze or ame insn. */ |
9854d9ed RK |
7760 | if (GET_CODE (x) != CONST_INT) |
7761 | output_operand_lossage ("invalid %%G value"); | |
7762 | else if (INTVAL (x) >= 0) | |
76229ac8 | 7763 | putc ('z', file); |
9854d9ed | 7764 | else |
76229ac8 | 7765 | putc ('m', file); |
9854d9ed | 7766 | return; |
e2c953b6 | 7767 | |
9878760c | 7768 | case 'h': |
a4f6c312 SS |
7769 | /* If constant, output low-order five bits. Otherwise, write |
7770 | normally. */ | |
9878760c | 7771 | if (INT_P (x)) |
5f59ecb7 | 7772 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 31); |
9878760c RK |
7773 | else |
7774 | print_operand (file, x, 0); | |
7775 | return; | |
7776 | ||
64305719 | 7777 | case 'H': |
a4f6c312 SS |
7778 | /* If constant, output low-order six bits. Otherwise, write |
7779 | normally. */ | |
64305719 | 7780 | if (INT_P (x)) |
5f59ecb7 | 7781 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 63); |
64305719 DE |
7782 | else |
7783 | print_operand (file, x, 0); | |
7784 | return; | |
7785 | ||
9854d9ed RK |
7786 | case 'I': |
7787 | /* Print `i' if this is a constant, else nothing. */ | |
9878760c | 7788 | if (INT_P (x)) |
76229ac8 | 7789 | putc ('i', file); |
9878760c RK |
7790 | return; |
7791 | ||
9854d9ed RK |
7792 | case 'j': |
7793 | /* Write the bit number in CCR for jump. */ | |
7794 | i = ccr_bit (x, 0); | |
7795 | if (i == -1) | |
7796 | output_operand_lossage ("invalid %%j code"); | |
9878760c | 7797 | else |
9854d9ed | 7798 | fprintf (file, "%d", i); |
9878760c RK |
7799 | return; |
7800 | ||
9854d9ed RK |
7801 | case 'J': |
7802 | /* Similar, but add one for shift count in rlinm for scc and pass | |
7803 | scc flag to `ccr_bit'. */ | |
7804 | i = ccr_bit (x, 1); | |
7805 | if (i == -1) | |
7806 | output_operand_lossage ("invalid %%J code"); | |
7807 | else | |
a0466a68 RK |
7808 | /* If we want bit 31, write a shift count of zero, not 32. */ |
7809 | fprintf (file, "%d", i == 31 ? 0 : i + 1); | |
9878760c RK |
7810 | return; |
7811 | ||
9854d9ed RK |
7812 | case 'k': |
7813 | /* X must be a constant. Write the 1's complement of the | |
7814 | constant. */ | |
9878760c | 7815 | if (! INT_P (x)) |
9854d9ed | 7816 | output_operand_lossage ("invalid %%k value"); |
e2c953b6 DE |
7817 | else |
7818 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, ~ INT_LOWPART (x)); | |
9878760c RK |
7819 | return; |
7820 | ||
81eace42 | 7821 | case 'K': |
9ebbca7d GK |
7822 | /* X must be a symbolic constant on ELF. Write an |
7823 | expression suitable for an 'addi' that adds in the low 16 | |
7824 | bits of the MEM. */ | |
7825 | if (GET_CODE (x) != CONST) | |
7826 | { | |
7827 | print_operand_address (file, x); | |
7828 | fputs ("@l", file); | |
7829 | } | |
7830 | else | |
7831 | { | |
7832 | if (GET_CODE (XEXP (x, 0)) != PLUS | |
7833 | || (GET_CODE (XEXP (XEXP (x, 0), 0)) != SYMBOL_REF | |
7834 | && GET_CODE (XEXP (XEXP (x, 0), 0)) != LABEL_REF) | |
7835 | || GET_CODE (XEXP (XEXP (x, 0), 1)) != CONST_INT) | |
53cd5d6c | 7836 | output_operand_lossage ("invalid %%K value"); |
9ebbca7d GK |
7837 | print_operand_address (file, XEXP (XEXP (x, 0), 0)); |
7838 | fputs ("@l", file); | |
ed8d2920 MM |
7839 | /* For GNU as, there must be a non-alphanumeric character |
7840 | between 'l' and the number. The '-' is added by | |
7841 | print_operand() already. */ | |
7842 | if (INTVAL (XEXP (XEXP (x, 0), 1)) >= 0) | |
7843 | fputs ("+", file); | |
9ebbca7d GK |
7844 | print_operand (file, XEXP (XEXP (x, 0), 1), 0); |
7845 | } | |
81eace42 GK |
7846 | return; |
7847 | ||
7848 | /* %l is output_asm_label. */ | |
9ebbca7d | 7849 | |
9854d9ed RK |
7850 | case 'L': |
7851 | /* Write second word of DImode or DFmode reference. Works on register | |
7852 | or non-indexed memory only. */ | |
7853 | if (GET_CODE (x) == REG) | |
5ebfb2ba | 7854 | fprintf (file, "%s", reg_names[REGNO (x) + 1]); |
9854d9ed RK |
7855 | else if (GET_CODE (x) == MEM) |
7856 | { | |
7857 | /* Handle possible auto-increment. Since it is pre-increment and | |
1427100a | 7858 | we have already done it, we can just use an offset of word. */ |
9854d9ed RK |
7859 | if (GET_CODE (XEXP (x, 0)) == PRE_INC |
7860 | || GET_CODE (XEXP (x, 0)) == PRE_DEC) | |
ed8908e7 RK |
7861 | output_address (plus_constant (XEXP (XEXP (x, 0), 0), |
7862 | UNITS_PER_WORD)); | |
9854d9ed | 7863 | else |
d7624dc0 RK |
7864 | output_address (XEXP (adjust_address_nv (x, SImode, |
7865 | UNITS_PER_WORD), | |
7866 | 0)); | |
ed8908e7 | 7867 | |
ba5e43aa | 7868 | if (small_data_operand (x, GET_MODE (x))) |
8fbd2dc7 MM |
7869 | fprintf (file, "@%s(%s)", SMALL_DATA_RELOC, |
7870 | reg_names[SMALL_DATA_REG]); | |
9854d9ed | 7871 | } |
9878760c | 7872 | return; |
9854d9ed | 7873 | |
9878760c RK |
7874 | case 'm': |
7875 | /* MB value for a mask operand. */ | |
b1765bde | 7876 | if (! mask_operand (x, SImode)) |
9878760c RK |
7877 | output_operand_lossage ("invalid %%m value"); |
7878 | ||
0ba1b2ff | 7879 | fprintf (file, "%d", extract_MB (x)); |
9878760c RK |
7880 | return; |
7881 | ||
7882 | case 'M': | |
7883 | /* ME value for a mask operand. */ | |
b1765bde | 7884 | if (! mask_operand (x, SImode)) |
a260abc9 | 7885 | output_operand_lossage ("invalid %%M value"); |
9878760c | 7886 | |
0ba1b2ff | 7887 | fprintf (file, "%d", extract_ME (x)); |
9878760c RK |
7888 | return; |
7889 | ||
81eace42 GK |
7890 | /* %n outputs the negative of its operand. */ |
7891 | ||
9878760c RK |
7892 | case 'N': |
7893 | /* Write the number of elements in the vector times 4. */ | |
7894 | if (GET_CODE (x) != PARALLEL) | |
7895 | output_operand_lossage ("invalid %%N value"); | |
e2c953b6 DE |
7896 | else |
7897 | fprintf (file, "%d", XVECLEN (x, 0) * 4); | |
9878760c RK |
7898 | return; |
7899 | ||
7900 | case 'O': | |
7901 | /* Similar, but subtract 1 first. */ | |
7902 | if (GET_CODE (x) != PARALLEL) | |
1427100a | 7903 | output_operand_lossage ("invalid %%O value"); |
e2c953b6 DE |
7904 | else |
7905 | fprintf (file, "%d", (XVECLEN (x, 0) - 1) * 4); | |
9878760c RK |
7906 | return; |
7907 | ||
9854d9ed RK |
7908 | case 'p': |
7909 | /* X is a CONST_INT that is a power of two. Output the logarithm. */ | |
7910 | if (! INT_P (x) | |
2bfcf297 | 7911 | || INT_LOWPART (x) < 0 |
9854d9ed RK |
7912 | || (i = exact_log2 (INT_LOWPART (x))) < 0) |
7913 | output_operand_lossage ("invalid %%p value"); | |
e2c953b6 DE |
7914 | else |
7915 | fprintf (file, "%d", i); | |
9854d9ed RK |
7916 | return; |
7917 | ||
9878760c RK |
7918 | case 'P': |
7919 | /* The operand must be an indirect memory reference. The result | |
a4f6c312 | 7920 | is the register number. */ |
9878760c RK |
7921 | if (GET_CODE (x) != MEM || GET_CODE (XEXP (x, 0)) != REG |
7922 | || REGNO (XEXP (x, 0)) >= 32) | |
7923 | output_operand_lossage ("invalid %%P value"); | |
e2c953b6 DE |
7924 | else |
7925 | fprintf (file, "%d", REGNO (XEXP (x, 0))); | |
9878760c RK |
7926 | return; |
7927 | ||
dfbdccdb GK |
7928 | case 'q': |
7929 | /* This outputs the logical code corresponding to a boolean | |
7930 | expression. The expression may have one or both operands | |
39a10a29 GK |
7931 | negated (if one, only the first one). For condition register |
7932 | logical operations, it will also treat the negated | |
7933 | CR codes as NOTs, but not handle NOTs of them. */ | |
dfbdccdb | 7934 | { |
63bc1d05 | 7935 | const char *const *t = 0; |
dfbdccdb GK |
7936 | const char *s; |
7937 | enum rtx_code code = GET_CODE (x); | |
7938 | static const char * const tbl[3][3] = { | |
7939 | { "and", "andc", "nor" }, | |
7940 | { "or", "orc", "nand" }, | |
7941 | { "xor", "eqv", "xor" } }; | |
7942 | ||
7943 | if (code == AND) | |
7944 | t = tbl[0]; | |
7945 | else if (code == IOR) | |
7946 | t = tbl[1]; | |
7947 | else if (code == XOR) | |
7948 | t = tbl[2]; | |
7949 | else | |
7950 | output_operand_lossage ("invalid %%q value"); | |
7951 | ||
7952 | if (GET_CODE (XEXP (x, 0)) != NOT) | |
7953 | s = t[0]; | |
7954 | else | |
7955 | { | |
7956 | if (GET_CODE (XEXP (x, 1)) == NOT) | |
7957 | s = t[2]; | |
7958 | else | |
7959 | s = t[1]; | |
7960 | } | |
7961 | ||
7962 | fputs (s, file); | |
7963 | } | |
7964 | return; | |
7965 | ||
9854d9ed RK |
7966 | case 'R': |
7967 | /* X is a CR register. Print the mask for `mtcrf'. */ | |
7968 | if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x))) | |
7969 | output_operand_lossage ("invalid %%R value"); | |
7970 | else | |
9ebbca7d | 7971 | fprintf (file, "%d", 128 >> (REGNO (x) - CR0_REGNO)); |
9878760c | 7972 | return; |
9854d9ed RK |
7973 | |
7974 | case 's': | |
7975 | /* Low 5 bits of 32 - value */ | |
7976 | if (! INT_P (x)) | |
7977 | output_operand_lossage ("invalid %%s value"); | |
e2c953b6 DE |
7978 | else |
7979 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, (32 - INT_LOWPART (x)) & 31); | |
9878760c | 7980 | return; |
9854d9ed | 7981 | |
a260abc9 | 7982 | case 'S': |
0ba1b2ff | 7983 | /* PowerPC64 mask position. All 0's is excluded. |
a260abc9 DE |
7984 | CONST_INT 32-bit mask is considered sign-extended so any |
7985 | transition must occur within the CONST_INT, not on the boundary. */ | |
b1765bde | 7986 | if (! mask64_operand (x, DImode)) |
a260abc9 DE |
7987 | output_operand_lossage ("invalid %%S value"); |
7988 | ||
0ba1b2ff | 7989 | uval = INT_LOWPART (x); |
a260abc9 | 7990 | |
0ba1b2ff | 7991 | if (uval & 1) /* Clear Left */ |
a260abc9 | 7992 | { |
f099d360 GK |
7993 | #if HOST_BITS_PER_WIDE_INT > 64 |
7994 | uval &= ((unsigned HOST_WIDE_INT) 1 << 64) - 1; | |
7995 | #endif | |
0ba1b2ff | 7996 | i = 64; |
a260abc9 | 7997 | } |
0ba1b2ff | 7998 | else /* Clear Right */ |
a260abc9 | 7999 | { |
0ba1b2ff | 8000 | uval = ~uval; |
f099d360 GK |
8001 | #if HOST_BITS_PER_WIDE_INT > 64 |
8002 | uval &= ((unsigned HOST_WIDE_INT) 1 << 64) - 1; | |
8003 | #endif | |
0ba1b2ff | 8004 | i = 63; |
a260abc9 | 8005 | } |
0ba1b2ff AM |
8006 | while (uval != 0) |
8007 | --i, uval >>= 1; | |
8008 | if (i < 0) | |
8009 | abort (); | |
8010 | fprintf (file, "%d", i); | |
8011 | return; | |
a260abc9 | 8012 | |
a3170dc6 AH |
8013 | case 't': |
8014 | /* Like 'J' but get to the OVERFLOW/UNORDERED bit. */ | |
8015 | if (GET_CODE (x) != REG || GET_MODE (x) != CCmode) | |
8016 | abort (); | |
8017 | ||
8018 | /* Bit 3 is OV bit. */ | |
8019 | i = 4 * (REGNO (x) - CR0_REGNO) + 3; | |
8020 | ||
8021 | /* If we want bit 31, write a shift count of zero, not 32. */ | |
8022 | fprintf (file, "%d", i == 31 ? 0 : i + 1); | |
8023 | return; | |
8024 | ||
cccf3bdc DE |
8025 | case 'T': |
8026 | /* Print the symbolic name of a branch target register. */ | |
8027 | if (GET_CODE (x) != REG || (REGNO (x) != LINK_REGISTER_REGNUM | |
8028 | && REGNO (x) != COUNT_REGISTER_REGNUM)) | |
8029 | output_operand_lossage ("invalid %%T value"); | |
e2c953b6 | 8030 | else if (REGNO (x) == LINK_REGISTER_REGNUM) |
cccf3bdc DE |
8031 | fputs (TARGET_NEW_MNEMONICS ? "lr" : "r", file); |
8032 | else | |
8033 | fputs ("ctr", file); | |
8034 | return; | |
8035 | ||
9854d9ed | 8036 | case 'u': |
802a0058 | 8037 | /* High-order 16 bits of constant for use in unsigned operand. */ |
9854d9ed RK |
8038 | if (! INT_P (x)) |
8039 | output_operand_lossage ("invalid %%u value"); | |
e2c953b6 DE |
8040 | else |
8041 | fprintf (file, HOST_WIDE_INT_PRINT_HEX, | |
8042 | (INT_LOWPART (x) >> 16) & 0xffff); | |
9878760c RK |
8043 | return; |
8044 | ||
802a0058 MM |
8045 | case 'v': |
8046 | /* High-order 16 bits of constant for use in signed operand. */ | |
8047 | if (! INT_P (x)) | |
8048 | output_operand_lossage ("invalid %%v value"); | |
e2c953b6 | 8049 | else |
134c32f6 DE |
8050 | fprintf (file, HOST_WIDE_INT_PRINT_HEX, |
8051 | (INT_LOWPART (x) >> 16) & 0xffff); | |
8052 | return; | |
802a0058 | 8053 | |
9854d9ed RK |
8054 | case 'U': |
8055 | /* Print `u' if this has an auto-increment or auto-decrement. */ | |
8056 | if (GET_CODE (x) == MEM | |
8057 | && (GET_CODE (XEXP (x, 0)) == PRE_INC | |
8058 | || GET_CODE (XEXP (x, 0)) == PRE_DEC)) | |
76229ac8 | 8059 | putc ('u', file); |
9854d9ed | 8060 | return; |
9878760c | 8061 | |
e0cd0770 JC |
8062 | case 'V': |
8063 | /* Print the trap code for this operand. */ | |
8064 | switch (GET_CODE (x)) | |
8065 | { | |
8066 | case EQ: | |
8067 | fputs ("eq", file); /* 4 */ | |
8068 | break; | |
8069 | case NE: | |
8070 | fputs ("ne", file); /* 24 */ | |
8071 | break; | |
8072 | case LT: | |
8073 | fputs ("lt", file); /* 16 */ | |
8074 | break; | |
8075 | case LE: | |
8076 | fputs ("le", file); /* 20 */ | |
8077 | break; | |
8078 | case GT: | |
8079 | fputs ("gt", file); /* 8 */ | |
8080 | break; | |
8081 | case GE: | |
8082 | fputs ("ge", file); /* 12 */ | |
8083 | break; | |
8084 | case LTU: | |
8085 | fputs ("llt", file); /* 2 */ | |
8086 | break; | |
8087 | case LEU: | |
8088 | fputs ("lle", file); /* 6 */ | |
8089 | break; | |
8090 | case GTU: | |
8091 | fputs ("lgt", file); /* 1 */ | |
8092 | break; | |
8093 | case GEU: | |
8094 | fputs ("lge", file); /* 5 */ | |
8095 | break; | |
8096 | default: | |
8097 | abort (); | |
8098 | } | |
8099 | break; | |
8100 | ||
9854d9ed RK |
8101 | case 'w': |
8102 | /* If constant, low-order 16 bits of constant, signed. Otherwise, write | |
8103 | normally. */ | |
8104 | if (INT_P (x)) | |
5f59ecb7 DE |
8105 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, |
8106 | ((INT_LOWPART (x) & 0xffff) ^ 0x8000) - 0x8000); | |
9854d9ed RK |
8107 | else |
8108 | print_operand (file, x, 0); | |
9878760c RK |
8109 | return; |
8110 | ||
9854d9ed | 8111 | case 'W': |
e2c953b6 | 8112 | /* MB value for a PowerPC64 rldic operand. */ |
e2c953b6 DE |
8113 | val = (GET_CODE (x) == CONST_INT |
8114 | ? INTVAL (x) : CONST_DOUBLE_HIGH (x)); | |
8115 | ||
8116 | if (val < 0) | |
8117 | i = -1; | |
9854d9ed | 8118 | else |
e2c953b6 DE |
8119 | for (i = 0; i < HOST_BITS_PER_WIDE_INT; i++) |
8120 | if ((val <<= 1) < 0) | |
8121 | break; | |
8122 | ||
8123 | #if HOST_BITS_PER_WIDE_INT == 32 | |
8124 | if (GET_CODE (x) == CONST_INT && i >= 0) | |
8125 | i += 32; /* zero-extend high-part was all 0's */ | |
8126 | else if (GET_CODE (x) == CONST_DOUBLE && i == 32) | |
8127 | { | |
8128 | val = CONST_DOUBLE_LOW (x); | |
8129 | ||
8130 | if (val == 0) | |
a4f6c312 | 8131 | abort (); |
e2c953b6 DE |
8132 | else if (val < 0) |
8133 | --i; | |
8134 | else | |
8135 | for ( ; i < 64; i++) | |
8136 | if ((val <<= 1) < 0) | |
8137 | break; | |
8138 | } | |
8139 | #endif | |
8140 | ||
8141 | fprintf (file, "%d", i + 1); | |
9854d9ed | 8142 | return; |
9878760c | 8143 | |
9854d9ed RK |
8144 | case 'X': |
8145 | if (GET_CODE (x) == MEM | |
258bfae2 | 8146 | && LEGITIMATE_INDEXED_ADDRESS_P (XEXP (x, 0), 0)) |
76229ac8 | 8147 | putc ('x', file); |
9854d9ed | 8148 | return; |
9878760c | 8149 | |
9854d9ed RK |
8150 | case 'Y': |
8151 | /* Like 'L', for third word of TImode */ | |
8152 | if (GET_CODE (x) == REG) | |
5ebfb2ba | 8153 | fprintf (file, "%s", reg_names[REGNO (x) + 2]); |
9854d9ed | 8154 | else if (GET_CODE (x) == MEM) |
9878760c | 8155 | { |
9854d9ed RK |
8156 | if (GET_CODE (XEXP (x, 0)) == PRE_INC |
8157 | || GET_CODE (XEXP (x, 0)) == PRE_DEC) | |
a54d04b7 | 8158 | output_address (plus_constant (XEXP (XEXP (x, 0), 0), 8)); |
9854d9ed | 8159 | else |
d7624dc0 | 8160 | output_address (XEXP (adjust_address_nv (x, SImode, 8), 0)); |
ba5e43aa | 8161 | if (small_data_operand (x, GET_MODE (x))) |
8fbd2dc7 MM |
8162 | fprintf (file, "@%s(%s)", SMALL_DATA_RELOC, |
8163 | reg_names[SMALL_DATA_REG]); | |
9878760c RK |
8164 | } |
8165 | return; | |
9854d9ed | 8166 | |
9878760c | 8167 | case 'z': |
b4ac57ab RS |
8168 | /* X is a SYMBOL_REF. Write out the name preceded by a |
8169 | period and without any trailing data in brackets. Used for function | |
4d30c363 MM |
8170 | names. If we are configured for System V (or the embedded ABI) on |
8171 | the PowerPC, do not emit the period, since those systems do not use | |
8172 | TOCs and the like. */ | |
9878760c RK |
8173 | if (GET_CODE (x) != SYMBOL_REF) |
8174 | abort (); | |
8175 | ||
b6c9286a MM |
8176 | if (XSTR (x, 0)[0] != '.') |
8177 | { | |
8178 | switch (DEFAULT_ABI) | |
8179 | { | |
8180 | default: | |
8181 | abort (); | |
8182 | ||
8183 | case ABI_AIX: | |
8184 | putc ('.', file); | |
8185 | break; | |
8186 | ||
8187 | case ABI_V4: | |
ee890fe2 | 8188 | case ABI_DARWIN: |
b6c9286a | 8189 | break; |
b6c9286a MM |
8190 | } |
8191 | } | |
54ee9799 DE |
8192 | #if TARGET_AIX |
8193 | RS6000_OUTPUT_BASENAME (file, XSTR (x, 0)); | |
8194 | #else | |
9ebbca7d | 8195 | assemble_name (file, XSTR (x, 0)); |
54ee9799 | 8196 | #endif |
9878760c RK |
8197 | return; |
8198 | ||
9854d9ed RK |
8199 | case 'Z': |
8200 | /* Like 'L', for last word of TImode. */ | |
8201 | if (GET_CODE (x) == REG) | |
5ebfb2ba | 8202 | fprintf (file, "%s", reg_names[REGNO (x) + 3]); |
9854d9ed RK |
8203 | else if (GET_CODE (x) == MEM) |
8204 | { | |
8205 | if (GET_CODE (XEXP (x, 0)) == PRE_INC | |
8206 | || GET_CODE (XEXP (x, 0)) == PRE_DEC) | |
a54d04b7 | 8207 | output_address (plus_constant (XEXP (XEXP (x, 0), 0), 12)); |
9854d9ed | 8208 | else |
d7624dc0 | 8209 | output_address (XEXP (adjust_address_nv (x, SImode, 12), 0)); |
ba5e43aa | 8210 | if (small_data_operand (x, GET_MODE (x))) |
8fbd2dc7 MM |
8211 | fprintf (file, "@%s(%s)", SMALL_DATA_RELOC, |
8212 | reg_names[SMALL_DATA_REG]); | |
9854d9ed | 8213 | } |
5c23c401 | 8214 | return; |
0ac081f6 | 8215 | |
a3170dc6 | 8216 | /* Print AltiVec or SPE memory operand. */ |
0ac081f6 AH |
8217 | case 'y': |
8218 | { | |
8219 | rtx tmp; | |
8220 | ||
8221 | if (GET_CODE (x) != MEM) | |
8222 | abort (); | |
8223 | ||
8224 | tmp = XEXP (x, 0); | |
8225 | ||
993f19a8 | 8226 | if (TARGET_E500) |
a3170dc6 AH |
8227 | { |
8228 | /* Handle [reg]. */ | |
8229 | if (GET_CODE (tmp) == REG) | |
8230 | { | |
8231 | fprintf (file, "0(%s)", reg_names[REGNO (tmp)]); | |
8232 | break; | |
8233 | } | |
8234 | /* Handle [reg+UIMM]. */ | |
8235 | else if (GET_CODE (tmp) == PLUS && | |
8236 | GET_CODE (XEXP (tmp, 1)) == CONST_INT) | |
8237 | { | |
8238 | int x; | |
8239 | ||
8240 | if (GET_CODE (XEXP (tmp, 0)) != REG) | |
8241 | abort (); | |
8242 | ||
8243 | x = INTVAL (XEXP (tmp, 1)); | |
8244 | fprintf (file, "%d(%s)", x, reg_names[REGNO (XEXP (tmp, 0))]); | |
8245 | break; | |
8246 | } | |
8247 | ||
8248 | /* Fall through. Must be [reg+reg]. */ | |
8249 | } | |
0ac081f6 | 8250 | if (GET_CODE (tmp) == REG) |
c62f2db5 | 8251 | fprintf (file, "0,%s", reg_names[REGNO (tmp)]); |
0ac081f6 AH |
8252 | else if (GET_CODE (tmp) == PLUS && GET_CODE (XEXP (tmp, 1)) == REG) |
8253 | { | |
8254 | if (REGNO (XEXP (tmp, 0)) == 0) | |
8255 | fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 1)) ], | |
8256 | reg_names[ REGNO (XEXP (tmp, 0)) ]); | |
8257 | else | |
8258 | fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 0)) ], | |
8259 | reg_names[ REGNO (XEXP (tmp, 1)) ]); | |
8260 | } | |
8261 | else | |
8262 | abort (); | |
8263 | break; | |
8264 | } | |
9854d9ed | 8265 | |
9878760c RK |
8266 | case 0: |
8267 | if (GET_CODE (x) == REG) | |
8268 | fprintf (file, "%s", reg_names[REGNO (x)]); | |
8269 | else if (GET_CODE (x) == MEM) | |
8270 | { | |
8271 | /* We need to handle PRE_INC and PRE_DEC here, since we need to | |
8272 | know the width from the mode. */ | |
8273 | if (GET_CODE (XEXP (x, 0)) == PRE_INC) | |
79ba6d34 MM |
8274 | fprintf (file, "%d(%s)", GET_MODE_SIZE (GET_MODE (x)), |
8275 | reg_names[REGNO (XEXP (XEXP (x, 0), 0))]); | |
9878760c | 8276 | else if (GET_CODE (XEXP (x, 0)) == PRE_DEC) |
79ba6d34 MM |
8277 | fprintf (file, "%d(%s)", - GET_MODE_SIZE (GET_MODE (x)), |
8278 | reg_names[REGNO (XEXP (XEXP (x, 0), 0))]); | |
9878760c | 8279 | else |
a54d04b7 | 8280 | output_address (XEXP (x, 0)); |
9878760c RK |
8281 | } |
8282 | else | |
a54d04b7 | 8283 | output_addr_const (file, x); |
a85d226b | 8284 | return; |
9878760c RK |
8285 | |
8286 | default: | |
8287 | output_operand_lossage ("invalid %%xn code"); | |
8288 | } | |
8289 | } | |
8290 | \f | |
8291 | /* Print the address of an operand. */ | |
8292 | ||
8293 | void | |
8294 | print_operand_address (file, x) | |
8295 | FILE *file; | |
592696dd | 8296 | rtx x; |
9878760c RK |
8297 | { |
8298 | if (GET_CODE (x) == REG) | |
4697a36c | 8299 | fprintf (file, "0(%s)", reg_names[ REGNO (x) ]); |
9ebbca7d GK |
8300 | else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST |
8301 | || GET_CODE (x) == LABEL_REF) | |
9878760c RK |
8302 | { |
8303 | output_addr_const (file, x); | |
ba5e43aa | 8304 | if (small_data_operand (x, GET_MODE (x))) |
8fbd2dc7 MM |
8305 | fprintf (file, "@%s(%s)", SMALL_DATA_RELOC, |
8306 | reg_names[SMALL_DATA_REG]); | |
9ebbca7d | 8307 | else if (TARGET_TOC) |
a4f6c312 | 8308 | abort (); |
9878760c RK |
8309 | } |
8310 | else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == REG) | |
8311 | { | |
8312 | if (REGNO (XEXP (x, 0)) == 0) | |
4697a36c MM |
8313 | fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 1)) ], |
8314 | reg_names[ REGNO (XEXP (x, 0)) ]); | |
9878760c | 8315 | else |
4697a36c MM |
8316 | fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 0)) ], |
8317 | reg_names[ REGNO (XEXP (x, 1)) ]); | |
9878760c RK |
8318 | } |
8319 | else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT) | |
5f59ecb7 DE |
8320 | { |
8321 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (XEXP (x, 1))); | |
8322 | fprintf (file, "(%s)", reg_names[ REGNO (XEXP (x, 0)) ]); | |
8323 | } | |
3cb999d8 DE |
8324 | #if TARGET_ELF |
8325 | else if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 0)) == REG | |
8326 | && CONSTANT_P (XEXP (x, 1))) | |
4697a36c MM |
8327 | { |
8328 | output_addr_const (file, XEXP (x, 1)); | |
8329 | fprintf (file, "@l(%s)", reg_names[ REGNO (XEXP (x, 0)) ]); | |
8330 | } | |
c859cda6 DJ |
8331 | #endif |
8332 | #if TARGET_MACHO | |
8333 | else if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 0)) == REG | |
8334 | && CONSTANT_P (XEXP (x, 1))) | |
8335 | { | |
8336 | fprintf (file, "lo16("); | |
8337 | output_addr_const (file, XEXP (x, 1)); | |
8338 | fprintf (file, ")(%s)", reg_names[ REGNO (XEXP (x, 0)) ]); | |
8339 | } | |
3cb999d8 | 8340 | #endif |
9ebbca7d GK |
8341 | else if (LEGITIMATE_CONSTANT_POOL_ADDRESS_P (x)) |
8342 | { | |
2bfcf297 | 8343 | if (TARGET_AIX && (!TARGET_ELF || !TARGET_MINIMAL_TOC)) |
9ebbca7d | 8344 | { |
2bfcf297 DB |
8345 | rtx contains_minus = XEXP (x, 1); |
8346 | rtx minus, symref; | |
8347 | const char *name; | |
9ebbca7d GK |
8348 | |
8349 | /* Find the (minus (sym) (toc)) buried in X, and temporarily | |
a4f6c312 | 8350 | turn it into (sym) for output_addr_const. */ |
9ebbca7d GK |
8351 | while (GET_CODE (XEXP (contains_minus, 0)) != MINUS) |
8352 | contains_minus = XEXP (contains_minus, 0); | |
8353 | ||
2bfcf297 DB |
8354 | minus = XEXP (contains_minus, 0); |
8355 | symref = XEXP (minus, 0); | |
8356 | XEXP (contains_minus, 0) = symref; | |
8357 | if (TARGET_ELF) | |
8358 | { | |
8359 | char *newname; | |
8360 | ||
8361 | name = XSTR (symref, 0); | |
8362 | newname = alloca (strlen (name) + sizeof ("@toc")); | |
8363 | strcpy (newname, name); | |
8364 | strcat (newname, "@toc"); | |
8365 | XSTR (symref, 0) = newname; | |
8366 | } | |
8367 | output_addr_const (file, XEXP (x, 1)); | |
8368 | if (TARGET_ELF) | |
8369 | XSTR (symref, 0) = name; | |
9ebbca7d GK |
8370 | XEXP (contains_minus, 0) = minus; |
8371 | } | |
8372 | else | |
8373 | output_addr_const (file, XEXP (x, 1)); | |
8374 | ||
8375 | fprintf (file, "(%s)", reg_names[REGNO (XEXP (x, 0))]); | |
8376 | } | |
9878760c RK |
8377 | else |
8378 | abort (); | |
8379 | } | |
8380 | \f | |
88cad84b | 8381 | /* Target hook for assembling integer objects. The PowerPC version has |
301d03af RS |
8382 | to handle fixup entries for relocatable code if RELOCATABLE_NEEDS_FIXUP |
8383 | is defined. It also needs to handle DI-mode objects on 64-bit | |
8384 | targets. */ | |
8385 | ||
8386 | static bool | |
8387 | rs6000_assemble_integer (x, size, aligned_p) | |
8388 | rtx x; | |
8389 | unsigned int size; | |
8390 | int aligned_p; | |
8391 | { | |
8392 | #ifdef RELOCATABLE_NEEDS_FIXUP | |
8393 | /* Special handling for SI values. */ | |
8394 | if (size == 4 && aligned_p) | |
8395 | { | |
8396 | extern int in_toc_section PARAMS ((void)); | |
8397 | static int recurse = 0; | |
8398 | ||
8399 | /* For -mrelocatable, we mark all addresses that need to be fixed up | |
8400 | in the .fixup section. */ | |
8401 | if (TARGET_RELOCATABLE | |
8402 | && !in_toc_section () | |
8403 | && !in_text_section () | |
8404 | && !recurse | |
8405 | && GET_CODE (x) != CONST_INT | |
8406 | && GET_CODE (x) != CONST_DOUBLE | |
8407 | && CONSTANT_P (x)) | |
8408 | { | |
8409 | char buf[256]; | |
8410 | ||
8411 | recurse = 1; | |
8412 | ASM_GENERATE_INTERNAL_LABEL (buf, "LCP", fixuplabelno); | |
8413 | fixuplabelno++; | |
8414 | ASM_OUTPUT_LABEL (asm_out_file, buf); | |
8415 | fprintf (asm_out_file, "\t.long\t("); | |
8416 | output_addr_const (asm_out_file, x); | |
8417 | fprintf (asm_out_file, ")@fixup\n"); | |
8418 | fprintf (asm_out_file, "\t.section\t\".fixup\",\"aw\"\n"); | |
8419 | ASM_OUTPUT_ALIGN (asm_out_file, 2); | |
8420 | fprintf (asm_out_file, "\t.long\t"); | |
8421 | assemble_name (asm_out_file, buf); | |
8422 | fprintf (asm_out_file, "\n\t.previous\n"); | |
8423 | recurse = 0; | |
8424 | return true; | |
8425 | } | |
8426 | /* Remove initial .'s to turn a -mcall-aixdesc function | |
8427 | address into the address of the descriptor, not the function | |
8428 | itself. */ | |
8429 | else if (GET_CODE (x) == SYMBOL_REF | |
8430 | && XSTR (x, 0)[0] == '.' | |
8431 | && DEFAULT_ABI == ABI_AIX) | |
8432 | { | |
8433 | const char *name = XSTR (x, 0); | |
8434 | while (*name == '.') | |
8435 | name++; | |
8436 | ||
8437 | fprintf (asm_out_file, "\t.long\t%s\n", name); | |
8438 | return true; | |
8439 | } | |
8440 | } | |
8441 | #endif /* RELOCATABLE_NEEDS_FIXUP */ | |
8442 | return default_assemble_integer (x, size, aligned_p); | |
8443 | } | |
93638d7a AM |
8444 | |
8445 | #ifdef HAVE_GAS_HIDDEN | |
8446 | /* Emit an assembler directive to set symbol visibility for DECL to | |
8447 | VISIBILITY_TYPE. */ | |
8448 | ||
5add3202 | 8449 | static void |
25fdb4dc | 8450 | rs6000_assemble_visibility (decl, vis) |
93638d7a | 8451 | tree decl; |
25fdb4dc | 8452 | int vis; |
93638d7a | 8453 | { |
93638d7a AM |
8454 | /* Functions need to have their entry point symbol visibility set as |
8455 | well as their descriptor symbol visibility. */ | |
8456 | if (DEFAULT_ABI == ABI_AIX && TREE_CODE (decl) == FUNCTION_DECL) | |
8457 | { | |
25fdb4dc RH |
8458 | static const char * const visibility_types[] = { |
8459 | NULL, "internal", "hidden", "protected" | |
8460 | }; | |
8461 | ||
8462 | const char *name, *type; | |
93638d7a AM |
8463 | |
8464 | name = ((* targetm.strip_name_encoding) | |
8465 | (IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl)))); | |
25fdb4dc | 8466 | type = visibility_types[vis]; |
93638d7a | 8467 | |
25fdb4dc RH |
8468 | fprintf (asm_out_file, "\t.%s\t%s\n", type, name); |
8469 | fprintf (asm_out_file, "\t.%s\t.%s\n", type, name); | |
93638d7a | 8470 | } |
25fdb4dc RH |
8471 | else |
8472 | default_assemble_visibility (decl, vis); | |
93638d7a AM |
8473 | } |
8474 | #endif | |
301d03af | 8475 | \f |
39a10a29 GK |
8476 | enum rtx_code |
8477 | rs6000_reverse_condition (mode, code) | |
8478 | enum machine_mode mode; | |
8479 | enum rtx_code code; | |
8480 | { | |
8481 | /* Reversal of FP compares takes care -- an ordered compare | |
8482 | becomes an unordered compare and vice versa. */ | |
de40e1df | 8483 | if (mode == CCFPmode && !flag_unsafe_math_optimizations) |
bab6226b | 8484 | return reverse_condition_maybe_unordered (code); |
39a10a29 | 8485 | else |
bab6226b | 8486 | return reverse_condition (code); |
39a10a29 GK |
8487 | } |
8488 | ||
39a10a29 GK |
8489 | /* Generate a compare for CODE. Return a brand-new rtx that |
8490 | represents the result of the compare. */ | |
a4f6c312 | 8491 | |
39a10a29 GK |
8492 | static rtx |
8493 | rs6000_generate_compare (code) | |
8494 | enum rtx_code code; | |
8495 | { | |
8496 | enum machine_mode comp_mode; | |
8497 | rtx compare_result; | |
8498 | ||
8499 | if (rs6000_compare_fp_p) | |
8500 | comp_mode = CCFPmode; | |
8501 | else if (code == GTU || code == LTU | |
8502 | || code == GEU || code == LEU) | |
8503 | comp_mode = CCUNSmode; | |
8504 | else | |
8505 | comp_mode = CCmode; | |
8506 | ||
8507 | /* First, the compare. */ | |
8508 | compare_result = gen_reg_rtx (comp_mode); | |
a3170dc6 AH |
8509 | |
8510 | /* SPE FP compare instructions on the GPRs. Yuck! */ | |
993f19a8 AH |
8511 | if ((TARGET_E500 && !TARGET_FPRS && TARGET_HARD_FLOAT) |
8512 | && rs6000_compare_fp_p) | |
a3170dc6 AH |
8513 | { |
8514 | rtx cmp, or1, or2, or_result, compare_result2; | |
8515 | ||
8516 | switch (code) | |
8517 | { | |
8518 | case EQ: | |
8519 | case UNEQ: | |
8520 | case NE: | |
8521 | case LTGT: | |
8522 | cmp = flag_unsafe_math_optimizations | |
8523 | ? gen_tstsfeq_gpr (compare_result, rs6000_compare_op0, | |
8524 | rs6000_compare_op1) | |
8525 | : gen_cmpsfeq_gpr (compare_result, rs6000_compare_op0, | |
8526 | rs6000_compare_op1); | |
8527 | break; | |
8528 | case GT: | |
8529 | case GTU: | |
8530 | case UNGT: | |
8531 | case UNGE: | |
8532 | case GE: | |
8533 | case GEU: | |
8534 | cmp = flag_unsafe_math_optimizations | |
8535 | ? gen_tstsfgt_gpr (compare_result, rs6000_compare_op0, | |
8536 | rs6000_compare_op1) | |
8537 | : gen_cmpsfgt_gpr (compare_result, rs6000_compare_op0, | |
8538 | rs6000_compare_op1); | |
8539 | break; | |
8540 | case LT: | |
8541 | case LTU: | |
8542 | case UNLT: | |
8543 | case UNLE: | |
8544 | case LE: | |
8545 | case LEU: | |
8546 | cmp = flag_unsafe_math_optimizations | |
8547 | ? gen_tstsflt_gpr (compare_result, rs6000_compare_op0, | |
8548 | rs6000_compare_op1) | |
8549 | : gen_cmpsflt_gpr (compare_result, rs6000_compare_op0, | |
8550 | rs6000_compare_op1); | |
8551 | break; | |
8552 | default: | |
8553 | abort (); | |
8554 | } | |
8555 | ||
8556 | /* Synthesize LE and GE from LT/GT || EQ. */ | |
8557 | if (code == LE || code == GE || code == LEU || code == GEU) | |
8558 | { | |
8559 | /* Synthesize GE/LE frome GT/LT || EQ. */ | |
8560 | ||
8561 | emit_insn (cmp); | |
8562 | ||
8563 | switch (code) | |
8564 | { | |
8565 | case LE: code = LT; break; | |
8566 | case GE: code = GT; break; | |
8567 | case LEU: code = LT; break; | |
8568 | case GEU: code = GT; break; | |
8569 | default: abort (); | |
8570 | } | |
8571 | ||
8572 | or1 = gen_reg_rtx (SImode); | |
8573 | or2 = gen_reg_rtx (SImode); | |
8574 | or_result = gen_reg_rtx (CCEQmode); | |
8575 | compare_result2 = gen_reg_rtx (CCFPmode); | |
8576 | ||
8577 | /* Do the EQ. */ | |
8578 | cmp = flag_unsafe_math_optimizations | |
8579 | ? gen_tstsfeq_gpr (compare_result2, rs6000_compare_op0, | |
8580 | rs6000_compare_op1) | |
8581 | : gen_cmpsfeq_gpr (compare_result2, rs6000_compare_op0, | |
8582 | rs6000_compare_op1); | |
8583 | emit_insn (cmp); | |
8584 | ||
8585 | /* The MC8540 FP compare instructions set the CR bits | |
8586 | differently than other PPC compare instructions. For | |
8587 | that matter, there is no generic test instruction, but a | |
8588 | testgt, testlt, and testeq. For a true condition, bit 2 | |
8589 | is set (x1xx) in the CR. Following the traditional CR | |
8590 | values: | |
8591 | ||
8592 | LT GT EQ OV | |
8593 | bit3 bit2 bit1 bit0 | |
8594 | ||
8595 | ... bit 2 would be a GT CR alias, so later on we | |
b6d08ca1 | 8596 | look in the GT bits for the branch instructions. |
a3170dc6 AH |
8597 | However, we must be careful to emit correct RTL in |
8598 | the meantime, so optimizations don't get confused. */ | |
8599 | ||
8600 | or1 = gen_rtx (NE, SImode, compare_result, const0_rtx); | |
8601 | or2 = gen_rtx (NE, SImode, compare_result2, const0_rtx); | |
8602 | ||
8603 | /* OR them together. */ | |
8604 | cmp = gen_rtx_SET (VOIDmode, or_result, | |
8605 | gen_rtx_COMPARE (CCEQmode, | |
8606 | gen_rtx_IOR (SImode, or1, or2), | |
8607 | const_true_rtx)); | |
8608 | compare_result = or_result; | |
8609 | code = EQ; | |
8610 | } | |
8611 | else | |
8612 | { | |
8613 | /* We only care about 1 bit (x1xx), so map everything to NE to | |
8614 | maintain rtl sanity. We'll get to the right bit (x1xx) at | |
8615 | code output time. */ | |
8616 | if (code == NE || code == LTGT) | |
8617 | /* Do the inverse here because we have no cmpne | |
8618 | instruction. We use the cmpeq instruction and expect | |
8619 | to get a 0 instead. */ | |
8620 | code = EQ; | |
8621 | else | |
8622 | code = NE; | |
8623 | } | |
8624 | ||
8625 | emit_insn (cmp); | |
8626 | } | |
8627 | else | |
8628 | emit_insn (gen_rtx_SET (VOIDmode, compare_result, | |
8629 | gen_rtx_COMPARE (comp_mode, | |
8630 | rs6000_compare_op0, | |
8631 | rs6000_compare_op1))); | |
39a10a29 | 8632 | |
ca5adc63 | 8633 | /* Some kinds of FP comparisons need an OR operation; |
de6c5979 | 8634 | except for flag_unsafe_math_optimizations we don't bother. */ |
39a10a29 | 8635 | if (rs6000_compare_fp_p |
de6c5979 | 8636 | && ! flag_unsafe_math_optimizations |
993f19a8 | 8637 | && ! (TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS) |
39a10a29 GK |
8638 | && (code == LE || code == GE |
8639 | || code == UNEQ || code == LTGT | |
8640 | || code == UNGT || code == UNLT)) | |
8641 | { | |
8642 | enum rtx_code or1, or2; | |
8643 | rtx or1_rtx, or2_rtx, compare2_rtx; | |
8644 | rtx or_result = gen_reg_rtx (CCEQmode); | |
8645 | ||
8646 | switch (code) | |
8647 | { | |
8648 | case LE: or1 = LT; or2 = EQ; break; | |
8649 | case GE: or1 = GT; or2 = EQ; break; | |
8650 | case UNEQ: or1 = UNORDERED; or2 = EQ; break; | |
8651 | case LTGT: or1 = LT; or2 = GT; break; | |
8652 | case UNGT: or1 = UNORDERED; or2 = GT; break; | |
8653 | case UNLT: or1 = UNORDERED; or2 = LT; break; | |
8654 | default: abort (); | |
8655 | } | |
8656 | validate_condition_mode (or1, comp_mode); | |
8657 | validate_condition_mode (or2, comp_mode); | |
8658 | or1_rtx = gen_rtx (or1, SImode, compare_result, const0_rtx); | |
8659 | or2_rtx = gen_rtx (or2, SImode, compare_result, const0_rtx); | |
8660 | compare2_rtx = gen_rtx_COMPARE (CCEQmode, | |
8661 | gen_rtx_IOR (SImode, or1_rtx, or2_rtx), | |
8662 | const_true_rtx); | |
8663 | emit_insn (gen_rtx_SET (VOIDmode, or_result, compare2_rtx)); | |
8664 | ||
8665 | compare_result = or_result; | |
8666 | code = EQ; | |
8667 | } | |
8668 | ||
8669 | validate_condition_mode (code, GET_MODE (compare_result)); | |
8670 | ||
8671 | return gen_rtx (code, VOIDmode, compare_result, const0_rtx); | |
8672 | } | |
8673 | ||
8674 | ||
8675 | /* Emit the RTL for an sCOND pattern. */ | |
8676 | ||
8677 | void | |
8678 | rs6000_emit_sCOND (code, result) | |
8679 | enum rtx_code code; | |
8680 | rtx result; | |
8681 | { | |
8682 | rtx condition_rtx; | |
8683 | enum machine_mode op_mode; | |
8684 | ||
8685 | condition_rtx = rs6000_generate_compare (code); | |
8686 | ||
8687 | op_mode = GET_MODE (rs6000_compare_op0); | |
8688 | if (op_mode == VOIDmode) | |
8689 | op_mode = GET_MODE (rs6000_compare_op1); | |
8690 | ||
8691 | if (TARGET_POWERPC64 && (op_mode == DImode || rs6000_compare_fp_p)) | |
8692 | { | |
8693 | PUT_MODE (condition_rtx, DImode); | |
8694 | convert_move (result, condition_rtx, 0); | |
8695 | } | |
8696 | else | |
8697 | { | |
8698 | PUT_MODE (condition_rtx, SImode); | |
8699 | emit_insn (gen_rtx_SET (VOIDmode, result, condition_rtx)); | |
8700 | } | |
8701 | } | |
8702 | ||
39a10a29 GK |
8703 | /* Emit a branch of kind CODE to location LOC. */ |
8704 | ||
8705 | void | |
8706 | rs6000_emit_cbranch (code, loc) | |
8707 | enum rtx_code code; | |
8708 | rtx loc; | |
8709 | { | |
8710 | rtx condition_rtx, loc_ref; | |
8711 | ||
8712 | condition_rtx = rs6000_generate_compare (code); | |
8713 | loc_ref = gen_rtx_LABEL_REF (VOIDmode, loc); | |
8714 | emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, | |
8715 | gen_rtx_IF_THEN_ELSE (VOIDmode, condition_rtx, | |
8716 | loc_ref, pc_rtx))); | |
8717 | } | |
8718 | ||
12a4e8c5 GK |
8719 | /* Return the string to output a conditional branch to LABEL, which is |
8720 | the operand number of the label, or -1 if the branch is really a | |
8721 | conditional return. | |
8722 | ||
8723 | OP is the conditional expression. XEXP (OP, 0) is assumed to be a | |
8724 | condition code register and its mode specifies what kind of | |
8725 | comparison we made. | |
8726 | ||
a0ab749a | 8727 | REVERSED is nonzero if we should reverse the sense of the comparison. |
12a4e8c5 GK |
8728 | |
8729 | INSN is the insn. */ | |
8730 | ||
8731 | char * | |
8732 | output_cbranch (op, label, reversed, insn) | |
8733 | rtx op; | |
8734 | const char * label; | |
8735 | int reversed; | |
8736 | rtx insn; | |
8737 | { | |
8738 | static char string[64]; | |
8739 | enum rtx_code code = GET_CODE (op); | |
8740 | rtx cc_reg = XEXP (op, 0); | |
8741 | enum machine_mode mode = GET_MODE (cc_reg); | |
8742 | int cc_regno = REGNO (cc_reg) - CR0_REGNO; | |
39a10a29 | 8743 | int need_longbranch = label != NULL && get_attr_length (insn) == 8; |
12a4e8c5 GK |
8744 | int really_reversed = reversed ^ need_longbranch; |
8745 | char *s = string; | |
8746 | const char *ccode; | |
8747 | const char *pred; | |
8748 | rtx note; | |
8749 | ||
39a10a29 GK |
8750 | validate_condition_mode (code, mode); |
8751 | ||
8752 | /* Work out which way this really branches. We could use | |
8753 | reverse_condition_maybe_unordered here always but this | |
8754 | makes the resulting assembler clearer. */ | |
12a4e8c5 | 8755 | if (really_reversed) |
de40e1df DJ |
8756 | { |
8757 | /* Reversal of FP compares takes care -- an ordered compare | |
8758 | becomes an unordered compare and vice versa. */ | |
8759 | if (mode == CCFPmode) | |
8760 | code = reverse_condition_maybe_unordered (code); | |
8761 | else | |
8762 | code = reverse_condition (code); | |
8763 | } | |
12a4e8c5 | 8764 | |
993f19a8 | 8765 | if ((TARGET_E500 && !TARGET_FPRS && TARGET_HARD_FLOAT) && mode == CCFPmode) |
a3170dc6 AH |
8766 | { |
8767 | /* The efscmp/tst* instructions twiddle bit 2, which maps nicely | |
8768 | to the GT bit. */ | |
8769 | if (code == EQ) | |
8770 | /* Opposite of GT. */ | |
8771 | code = UNLE; | |
8772 | else if (code == NE) | |
8773 | code = GT; | |
8774 | else | |
8775 | abort (); | |
8776 | } | |
8777 | ||
39a10a29 | 8778 | switch (code) |
12a4e8c5 GK |
8779 | { |
8780 | /* Not all of these are actually distinct opcodes, but | |
8781 | we distinguish them for clarity of the resulting assembler. */ | |
50a0b056 GK |
8782 | case NE: case LTGT: |
8783 | ccode = "ne"; break; | |
8784 | case EQ: case UNEQ: | |
8785 | ccode = "eq"; break; | |
8786 | case GE: case GEU: | |
8787 | ccode = "ge"; break; | |
8788 | case GT: case GTU: case UNGT: | |
8789 | ccode = "gt"; break; | |
8790 | case LE: case LEU: | |
8791 | ccode = "le"; break; | |
8792 | case LT: case LTU: case UNLT: | |
8793 | ccode = "lt"; break; | |
12a4e8c5 GK |
8794 | case UNORDERED: ccode = "un"; break; |
8795 | case ORDERED: ccode = "nu"; break; | |
8796 | case UNGE: ccode = "nl"; break; | |
8797 | case UNLE: ccode = "ng"; break; | |
8798 | default: | |
a4f6c312 | 8799 | abort (); |
12a4e8c5 GK |
8800 | } |
8801 | ||
94a54f47 GK |
8802 | /* Maybe we have a guess as to how likely the branch is. |
8803 | The old mnemonics don't have a way to specify this information. */ | |
f4857b9b | 8804 | pred = ""; |
12a4e8c5 GK |
8805 | note = find_reg_note (insn, REG_BR_PROB, NULL_RTX); |
8806 | if (note != NULL_RTX) | |
8807 | { | |
8808 | /* PROB is the difference from 50%. */ | |
8809 | int prob = INTVAL (XEXP (note, 0)) - REG_BR_PROB_BASE / 2; | |
f4857b9b AM |
8810 | bool always_hint = rs6000_cpu != PROCESSOR_POWER4; |
8811 | ||
8812 | /* Only hint for highly probable/improbable branches on newer | |
8813 | cpus as static prediction overrides processor dynamic | |
8814 | prediction. For older cpus we may as well always hint, but | |
8815 | assume not taken for branches that are very close to 50% as a | |
8816 | mispredicted taken branch is more expensive than a | |
8817 | mispredicted not-taken branch. */ | |
8818 | if (always_hint | |
8819 | || abs (prob) > REG_BR_PROB_BASE / 100 * 48) | |
8820 | { | |
8821 | if (abs (prob) > REG_BR_PROB_BASE / 20 | |
8822 | && ((prob > 0) ^ need_longbranch)) | |
7f3d8013 | 8823 | pred = "+"; |
f4857b9b AM |
8824 | else |
8825 | pred = "-"; | |
8826 | } | |
12a4e8c5 | 8827 | } |
12a4e8c5 GK |
8828 | |
8829 | if (label == NULL) | |
94a54f47 | 8830 | s += sprintf (s, "{b%sr|b%slr%s} ", ccode, ccode, pred); |
12a4e8c5 | 8831 | else |
94a54f47 | 8832 | s += sprintf (s, "{b%s|b%s%s} ", ccode, ccode, pred); |
12a4e8c5 | 8833 | |
37c67319 GK |
8834 | /* We need to escape any '%' characters in the reg_names string. |
8835 | Assume they'd only be the first character... */ | |
8836 | if (reg_names[cc_regno + CR0_REGNO][0] == '%') | |
8837 | *s++ = '%'; | |
94a54f47 | 8838 | s += sprintf (s, "%s", reg_names[cc_regno + CR0_REGNO]); |
12a4e8c5 GK |
8839 | |
8840 | if (label != NULL) | |
8841 | { | |
8842 | /* If the branch distance was too far, we may have to use an | |
8843 | unconditional branch to go the distance. */ | |
8844 | if (need_longbranch) | |
44518ddd | 8845 | s += sprintf (s, ",$+8\n\tb %s", label); |
12a4e8c5 GK |
8846 | else |
8847 | s += sprintf (s, ",%s", label); | |
8848 | } | |
8849 | ||
8850 | return string; | |
8851 | } | |
50a0b056 GK |
8852 | |
8853 | /* Emit a conditional move: move TRUE_COND to DEST if OP of the | |
8854 | operands of the last comparison is nonzero/true, FALSE_COND if it | |
8855 | is zero/false. Return 0 if the hardware has no such operation. */ | |
a4f6c312 | 8856 | |
50a0b056 GK |
8857 | int |
8858 | rs6000_emit_cmove (dest, op, true_cond, false_cond) | |
8859 | rtx dest; | |
8860 | rtx op; | |
8861 | rtx true_cond; | |
8862 | rtx false_cond; | |
8863 | { | |
8864 | enum rtx_code code = GET_CODE (op); | |
8865 | rtx op0 = rs6000_compare_op0; | |
8866 | rtx op1 = rs6000_compare_op1; | |
8867 | REAL_VALUE_TYPE c1; | |
3148ad6d DJ |
8868 | enum machine_mode compare_mode = GET_MODE (op0); |
8869 | enum machine_mode result_mode = GET_MODE (dest); | |
50a0b056 GK |
8870 | rtx temp; |
8871 | ||
3148ad6d | 8872 | /* These modes should always match. */ |
a3170dc6 AH |
8873 | if (GET_MODE (op1) != compare_mode |
8874 | /* In the isel case however, we can use a compare immediate, so | |
8875 | op1 may be a small constant. */ | |
8876 | && (!TARGET_ISEL || !short_cint_operand (op1, VOIDmode))) | |
3148ad6d | 8877 | return 0; |
178c3eff | 8878 | if (GET_MODE (true_cond) != result_mode) |
3148ad6d | 8879 | return 0; |
178c3eff | 8880 | if (GET_MODE (false_cond) != result_mode) |
3148ad6d DJ |
8881 | return 0; |
8882 | ||
50a0b056 GK |
8883 | /* First, work out if the hardware can do this at all, or |
8884 | if it's too slow... */ | |
50a0b056 | 8885 | if (! rs6000_compare_fp_p) |
a3170dc6 AH |
8886 | { |
8887 | if (TARGET_ISEL) | |
8888 | return rs6000_emit_int_cmove (dest, op, true_cond, false_cond); | |
8889 | return 0; | |
8890 | } | |
50a0b056 GK |
8891 | |
8892 | /* Eliminate half of the comparisons by switching operands, this | |
8893 | makes the remaining code simpler. */ | |
8894 | if (code == UNLT || code == UNGT || code == UNORDERED || code == NE | |
8895 | || code == LTGT || code == LT) | |
8896 | { | |
8897 | code = reverse_condition_maybe_unordered (code); | |
8898 | temp = true_cond; | |
8899 | true_cond = false_cond; | |
8900 | false_cond = temp; | |
8901 | } | |
8902 | ||
8903 | /* UNEQ and LTGT take four instructions for a comparison with zero, | |
8904 | it'll probably be faster to use a branch here too. */ | |
8905 | if (code == UNEQ) | |
8906 | return 0; | |
8907 | ||
8908 | if (GET_CODE (op1) == CONST_DOUBLE) | |
8909 | REAL_VALUE_FROM_CONST_DOUBLE (c1, op1); | |
8910 | ||
b6d08ca1 | 8911 | /* We're going to try to implement comparisons by performing |
50a0b056 GK |
8912 | a subtract, then comparing against zero. Unfortunately, |
8913 | Inf - Inf is NaN which is not zero, and so if we don't | |
27d30956 | 8914 | know that the operand is finite and the comparison |
50a0b056 GK |
8915 | would treat EQ different to UNORDERED, we can't do it. */ |
8916 | if (! flag_unsafe_math_optimizations | |
8917 | && code != GT && code != UNGE | |
045572c7 | 8918 | && (GET_CODE (op1) != CONST_DOUBLE || real_isinf (&c1)) |
50a0b056 GK |
8919 | /* Constructs of the form (a OP b ? a : b) are safe. */ |
8920 | && ((! rtx_equal_p (op0, false_cond) && ! rtx_equal_p (op1, false_cond)) | |
8921 | || (! rtx_equal_p (op0, true_cond) | |
8922 | && ! rtx_equal_p (op1, true_cond)))) | |
8923 | return 0; | |
8924 | /* At this point we know we can use fsel. */ | |
8925 | ||
8926 | /* Reduce the comparison to a comparison against zero. */ | |
3148ad6d | 8927 | temp = gen_reg_rtx (compare_mode); |
50a0b056 | 8928 | emit_insn (gen_rtx_SET (VOIDmode, temp, |
3148ad6d | 8929 | gen_rtx_MINUS (compare_mode, op0, op1))); |
50a0b056 | 8930 | op0 = temp; |
3148ad6d | 8931 | op1 = CONST0_RTX (compare_mode); |
50a0b056 GK |
8932 | |
8933 | /* If we don't care about NaNs we can reduce some of the comparisons | |
8934 | down to faster ones. */ | |
8935 | if (flag_unsafe_math_optimizations) | |
8936 | switch (code) | |
8937 | { | |
8938 | case GT: | |
8939 | code = LE; | |
8940 | temp = true_cond; | |
8941 | true_cond = false_cond; | |
8942 | false_cond = temp; | |
8943 | break; | |
8944 | case UNGE: | |
8945 | code = GE; | |
8946 | break; | |
8947 | case UNEQ: | |
8948 | code = EQ; | |
8949 | break; | |
8950 | default: | |
8951 | break; | |
8952 | } | |
8953 | ||
8954 | /* Now, reduce everything down to a GE. */ | |
8955 | switch (code) | |
8956 | { | |
8957 | case GE: | |
8958 | break; | |
8959 | ||
8960 | case LE: | |
3148ad6d DJ |
8961 | temp = gen_reg_rtx (compare_mode); |
8962 | emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0))); | |
50a0b056 GK |
8963 | op0 = temp; |
8964 | break; | |
8965 | ||
8966 | case ORDERED: | |
3148ad6d DJ |
8967 | temp = gen_reg_rtx (compare_mode); |
8968 | emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_ABS (compare_mode, op0))); | |
50a0b056 GK |
8969 | op0 = temp; |
8970 | break; | |
8971 | ||
8972 | case EQ: | |
3148ad6d | 8973 | temp = gen_reg_rtx (compare_mode); |
50a0b056 | 8974 | emit_insn (gen_rtx_SET (VOIDmode, temp, |
3148ad6d DJ |
8975 | gen_rtx_NEG (compare_mode, |
8976 | gen_rtx_ABS (compare_mode, op0)))); | |
50a0b056 GK |
8977 | op0 = temp; |
8978 | break; | |
8979 | ||
8980 | case UNGE: | |
3148ad6d | 8981 | temp = gen_reg_rtx (result_mode); |
50a0b056 | 8982 | emit_insn (gen_rtx_SET (VOIDmode, temp, |
3148ad6d | 8983 | gen_rtx_IF_THEN_ELSE (result_mode, |
50a0b056 GK |
8984 | gen_rtx_GE (VOIDmode, |
8985 | op0, op1), | |
8986 | true_cond, false_cond))); | |
8987 | false_cond = temp; | |
8988 | true_cond = false_cond; | |
8989 | ||
3148ad6d DJ |
8990 | temp = gen_reg_rtx (compare_mode); |
8991 | emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0))); | |
50a0b056 GK |
8992 | op0 = temp; |
8993 | break; | |
8994 | ||
8995 | case GT: | |
3148ad6d | 8996 | temp = gen_reg_rtx (result_mode); |
50a0b056 | 8997 | emit_insn (gen_rtx_SET (VOIDmode, temp, |
3148ad6d | 8998 | gen_rtx_IF_THEN_ELSE (result_mode, |
50a0b056 GK |
8999 | gen_rtx_GE (VOIDmode, |
9000 | op0, op1), | |
9001 | true_cond, false_cond))); | |
9002 | true_cond = temp; | |
9003 | false_cond = true_cond; | |
9004 | ||
3148ad6d DJ |
9005 | temp = gen_reg_rtx (compare_mode); |
9006 | emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0))); | |
50a0b056 GK |
9007 | op0 = temp; |
9008 | break; | |
9009 | ||
9010 | default: | |
9011 | abort (); | |
9012 | } | |
9013 | ||
9014 | emit_insn (gen_rtx_SET (VOIDmode, dest, | |
3148ad6d | 9015 | gen_rtx_IF_THEN_ELSE (result_mode, |
50a0b056 GK |
9016 | gen_rtx_GE (VOIDmode, |
9017 | op0, op1), | |
9018 | true_cond, false_cond))); | |
9019 | return 1; | |
9020 | } | |
9021 | ||
a3170dc6 AH |
9022 | /* Same as above, but for ints (isel). */ |
9023 | ||
9024 | static int | |
9025 | rs6000_emit_int_cmove (dest, op, true_cond, false_cond) | |
9026 | rtx dest; | |
9027 | rtx op; | |
9028 | rtx true_cond; | |
9029 | rtx false_cond; | |
9030 | { | |
9031 | rtx condition_rtx, cr; | |
9032 | ||
9033 | /* All isel implementations thus far are 32-bits. */ | |
9034 | if (GET_MODE (rs6000_compare_op0) != SImode) | |
9035 | return 0; | |
9036 | ||
9037 | /* We still have to do the compare, because isel doesn't do a | |
9038 | compare, it just looks at the CRx bits set by a previous compare | |
9039 | instruction. */ | |
9040 | condition_rtx = rs6000_generate_compare (GET_CODE (op)); | |
9041 | cr = XEXP (condition_rtx, 0); | |
9042 | ||
9043 | if (GET_MODE (cr) == CCmode) | |
9044 | emit_insn (gen_isel_signed (dest, condition_rtx, | |
9045 | true_cond, false_cond, cr)); | |
9046 | else | |
9047 | emit_insn (gen_isel_unsigned (dest, condition_rtx, | |
9048 | true_cond, false_cond, cr)); | |
9049 | ||
9050 | return 1; | |
9051 | } | |
9052 | ||
9053 | const char * | |
9054 | output_isel (operands) | |
9055 | rtx *operands; | |
9056 | { | |
9057 | enum rtx_code code; | |
9058 | ||
9059 | code = GET_CODE (operands[1]); | |
9060 | if (code == GE || code == GEU || code == LE || code == LEU || code == NE) | |
9061 | { | |
9062 | PUT_CODE (operands[1], reverse_condition (code)); | |
9063 | return "isel %0,%3,%2,%j1"; | |
9064 | } | |
9065 | else | |
9066 | return "isel %0,%2,%3,%j1"; | |
9067 | } | |
9068 | ||
50a0b056 GK |
9069 | void |
9070 | rs6000_emit_minmax (dest, code, op0, op1) | |
9071 | rtx dest; | |
9072 | enum rtx_code code; | |
9073 | rtx op0; | |
9074 | rtx op1; | |
9075 | { | |
9076 | enum machine_mode mode = GET_MODE (op0); | |
5dc8d536 | 9077 | enum rtx_code c; |
50a0b056 | 9078 | rtx target; |
5dc8d536 AH |
9079 | |
9080 | if (code == SMAX || code == SMIN) | |
9081 | c = GE; | |
9082 | else | |
9083 | c = GEU; | |
9084 | ||
50a0b056 | 9085 | if (code == SMAX || code == UMAX) |
5dc8d536 | 9086 | target = emit_conditional_move (dest, c, op0, op1, mode, |
50a0b056 GK |
9087 | op0, op1, mode, 0); |
9088 | else | |
5dc8d536 | 9089 | target = emit_conditional_move (dest, c, op0, op1, mode, |
50a0b056 GK |
9090 | op1, op0, mode, 0); |
9091 | if (target == NULL_RTX) | |
9092 | abort (); | |
9093 | if (target != dest) | |
9094 | emit_move_insn (dest, target); | |
9095 | } | |
12a4e8c5 | 9096 | \f |
a4f6c312 SS |
9097 | /* This page contains routines that are used to determine what the |
9098 | function prologue and epilogue code will do and write them out. */ | |
9878760c | 9099 | |
a4f6c312 SS |
9100 | /* Return the first fixed-point register that is required to be |
9101 | saved. 32 if none. */ | |
9878760c RK |
9102 | |
9103 | int | |
9104 | first_reg_to_save () | |
9105 | { | |
9106 | int first_reg; | |
9107 | ||
9108 | /* Find lowest numbered live register. */ | |
9109 | for (first_reg = 13; first_reg <= 31; first_reg++) | |
a38d360d GK |
9110 | if (regs_ever_live[first_reg] |
9111 | && (! call_used_regs[first_reg] | |
1db02437 | 9112 | || (first_reg == RS6000_PIC_OFFSET_TABLE_REGNUM |
14f00213 | 9113 | && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0) |
f607bc57 | 9114 | || (DEFAULT_ABI == ABI_DARWIN && flag_pic))))) |
9878760c RK |
9115 | break; |
9116 | ||
ee890fe2 | 9117 | #if TARGET_MACHO |
93638d7a AM |
9118 | if (flag_pic |
9119 | && current_function_uses_pic_offset_table | |
9120 | && first_reg > RS6000_PIC_OFFSET_TABLE_REGNUM) | |
1db02437 | 9121 | return RS6000_PIC_OFFSET_TABLE_REGNUM; |
ee890fe2 SS |
9122 | #endif |
9123 | ||
9878760c RK |
9124 | return first_reg; |
9125 | } | |
9126 | ||
9127 | /* Similar, for FP regs. */ | |
9128 | ||
9129 | int | |
9130 | first_fp_reg_to_save () | |
9131 | { | |
9132 | int first_reg; | |
9133 | ||
9134 | /* Find lowest numbered live register. */ | |
9135 | for (first_reg = 14 + 32; first_reg <= 63; first_reg++) | |
9136 | if (regs_ever_live[first_reg]) | |
9137 | break; | |
9138 | ||
9139 | return first_reg; | |
9140 | } | |
00b960c7 AH |
9141 | |
9142 | /* Similar, for AltiVec regs. */ | |
9143 | ||
9144 | static int | |
9145 | first_altivec_reg_to_save () | |
9146 | { | |
9147 | int i; | |
9148 | ||
9149 | /* Stack frame remains as is unless we are in AltiVec ABI. */ | |
9150 | if (! TARGET_ALTIVEC_ABI) | |
9151 | return LAST_ALTIVEC_REGNO + 1; | |
9152 | ||
9153 | /* Find lowest numbered live register. */ | |
9154 | for (i = FIRST_ALTIVEC_REGNO + 20; i <= LAST_ALTIVEC_REGNO; ++i) | |
9155 | if (regs_ever_live[i]) | |
9156 | break; | |
9157 | ||
9158 | return i; | |
9159 | } | |
9160 | ||
9161 | /* Return a 32-bit mask of the AltiVec registers we need to set in | |
9162 | VRSAVE. Bit n of the return value is 1 if Vn is live. The MSB in | |
9163 | the 32-bit word is 0. */ | |
9164 | ||
9165 | static unsigned int | |
9166 | compute_vrsave_mask () | |
9167 | { | |
9168 | unsigned int i, mask = 0; | |
9169 | ||
9170 | /* First, find out if we use _any_ altivec registers. */ | |
9171 | for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i) | |
9172 | if (regs_ever_live[i]) | |
9173 | mask |= ALTIVEC_REG_BIT (i); | |
9174 | ||
9175 | if (mask == 0) | |
9176 | return mask; | |
9177 | ||
00b960c7 AH |
9178 | /* Next, remove the argument registers from the set. These must |
9179 | be in the VRSAVE mask set by the caller, so we don't need to add | |
9180 | them in again. More importantly, the mask we compute here is | |
9181 | used to generate CLOBBERs in the set_vrsave insn, and we do not | |
9182 | wish the argument registers to die. */ | |
9183 | for (i = cfun->args_info.vregno; i >= ALTIVEC_ARG_MIN_REG; --i) | |
9184 | mask &= ~ALTIVEC_REG_BIT (i); | |
9185 | ||
9186 | /* Similarly, remove the return value from the set. */ | |
9187 | { | |
9188 | bool yes = false; | |
9189 | diddle_return_value (is_altivec_return_reg, &yes); | |
9190 | if (yes) | |
9191 | mask &= ~ALTIVEC_REG_BIT (ALTIVEC_ARG_RETURN); | |
9192 | } | |
9193 | ||
9194 | return mask; | |
9195 | } | |
9196 | ||
9197 | static void | |
9198 | is_altivec_return_reg (reg, xyes) | |
9199 | rtx reg; | |
9200 | void *xyes; | |
9201 | { | |
9202 | bool *yes = (bool *) xyes; | |
9203 | if (REGNO (reg) == ALTIVEC_ARG_RETURN) | |
9204 | *yes = true; | |
9205 | } | |
9206 | ||
4697a36c MM |
9207 | \f |
9208 | /* Calculate the stack information for the current function. This is | |
9209 | complicated by having two separate calling sequences, the AIX calling | |
9210 | sequence and the V.4 calling sequence. | |
9211 | ||
592696dd | 9212 | AIX (and Darwin/Mac OS X) stack frames look like: |
a260abc9 | 9213 | 32-bit 64-bit |
4697a36c | 9214 | SP----> +---------------------------------------+ |
a260abc9 | 9215 | | back chain to caller | 0 0 |
4697a36c | 9216 | +---------------------------------------+ |
a260abc9 | 9217 | | saved CR | 4 8 (8-11) |
4697a36c | 9218 | +---------------------------------------+ |
a260abc9 | 9219 | | saved LR | 8 16 |
4697a36c | 9220 | +---------------------------------------+ |
a260abc9 | 9221 | | reserved for compilers | 12 24 |
4697a36c | 9222 | +---------------------------------------+ |
a260abc9 | 9223 | | reserved for binders | 16 32 |
4697a36c | 9224 | +---------------------------------------+ |
a260abc9 | 9225 | | saved TOC pointer | 20 40 |
4697a36c | 9226 | +---------------------------------------+ |
a260abc9 | 9227 | | Parameter save area (P) | 24 48 |
4697a36c | 9228 | +---------------------------------------+ |
a260abc9 | 9229 | | Alloca space (A) | 24+P etc. |
802a0058 | 9230 | +---------------------------------------+ |
a7df97e6 | 9231 | | Local variable space (L) | 24+P+A |
4697a36c | 9232 | +---------------------------------------+ |
a7df97e6 | 9233 | | Float/int conversion temporary (X) | 24+P+A+L |
4697a36c | 9234 | +---------------------------------------+ |
00b960c7 AH |
9235 | | Save area for AltiVec registers (W) | 24+P+A+L+X |
9236 | +---------------------------------------+ | |
9237 | | AltiVec alignment padding (Y) | 24+P+A+L+X+W | |
9238 | +---------------------------------------+ | |
9239 | | Save area for VRSAVE register (Z) | 24+P+A+L+X+W+Y | |
4697a36c | 9240 | +---------------------------------------+ |
00b960c7 AH |
9241 | | Save area for GP registers (G) | 24+P+A+X+L+X+W+Y+Z |
9242 | +---------------------------------------+ | |
9243 | | Save area for FP registers (F) | 24+P+A+X+L+X+W+Y+Z+G | |
4697a36c MM |
9244 | +---------------------------------------+ |
9245 | old SP->| back chain to caller's caller | | |
9246 | +---------------------------------------+ | |
9247 | ||
5376a30c KR |
9248 | The required alignment for AIX configurations is two words (i.e., 8 |
9249 | or 16 bytes). | |
9250 | ||
9251 | ||
4697a36c MM |
9252 | V.4 stack frames look like: |
9253 | ||
9254 | SP----> +---------------------------------------+ | |
9255 | | back chain to caller | 0 | |
9256 | +---------------------------------------+ | |
5eb387b8 | 9257 | | caller's saved LR | 4 |
4697a36c MM |
9258 | +---------------------------------------+ |
9259 | | Parameter save area (P) | 8 | |
9260 | +---------------------------------------+ | |
a7df97e6 MM |
9261 | | Alloca space (A) | 8+P |
9262 | +---------------------------------------+ | |
9263 | | Varargs save area (V) | 8+P+A | |
9264 | +---------------------------------------+ | |
9265 | | Local variable space (L) | 8+P+A+V | |
9266 | +---------------------------------------+ | |
9267 | | Float/int conversion temporary (X) | 8+P+A+V+L | |
4697a36c | 9268 | +---------------------------------------+ |
00b960c7 AH |
9269 | | Save area for AltiVec registers (W) | 8+P+A+V+L+X |
9270 | +---------------------------------------+ | |
9271 | | AltiVec alignment padding (Y) | 8+P+A+V+L+X+W | |
9272 | +---------------------------------------+ | |
9273 | | Save area for VRSAVE register (Z) | 8+P+A+V+L+X+W+Y | |
9274 | +---------------------------------------+ | |
a3170dc6 AH |
9275 | | SPE: area for 64-bit GP registers | |
9276 | +---------------------------------------+ | |
9277 | | SPE alignment padding | | |
9278 | +---------------------------------------+ | |
00b960c7 | 9279 | | saved CR (C) | 8+P+A+V+L+X+W+Y+Z |
a7df97e6 | 9280 | +---------------------------------------+ |
00b960c7 | 9281 | | Save area for GP registers (G) | 8+P+A+V+L+X+W+Y+Z+C |
a7df97e6 | 9282 | +---------------------------------------+ |
00b960c7 | 9283 | | Save area for FP registers (F) | 8+P+A+V+L+X+W+Y+Z+C+G |
4697a36c MM |
9284 | +---------------------------------------+ |
9285 | old SP->| back chain to caller's caller | | |
9286 | +---------------------------------------+ | |
b6c9286a | 9287 | |
5376a30c KR |
9288 | The required alignment for V.4 is 16 bytes, or 8 bytes if -meabi is |
9289 | given. (But note below and in sysv4.h that we require only 8 and | |
9290 | may round up the size of our stack frame anyways. The historical | |
9291 | reason is early versions of powerpc-linux which didn't properly | |
9292 | align the stack at program startup. A happy side-effect is that | |
9293 | -mno-eabi libraries can be used with -meabi programs.) | |
9294 | ||
50d440bc | 9295 | The EABI configuration defaults to the V.4 layout. However, |
5376a30c KR |
9296 | the stack alignment requirements may differ. If -mno-eabi is not |
9297 | given, the required stack alignment is 8 bytes; if -mno-eabi is | |
9298 | given, the required alignment is 16 bytes. (But see V.4 comment | |
9299 | above.) */ | |
4697a36c | 9300 | |
61b2fbe7 MM |
9301 | #ifndef ABI_STACK_BOUNDARY |
9302 | #define ABI_STACK_BOUNDARY STACK_BOUNDARY | |
9303 | #endif | |
9304 | ||
4697a36c MM |
9305 | rs6000_stack_t * |
9306 | rs6000_stack_info () | |
9307 | { | |
9308 | static rs6000_stack_t info, zero_info; | |
9309 | rs6000_stack_t *info_ptr = &info; | |
9ebbca7d | 9310 | int reg_size = TARGET_POWERPC64 ? 8 : 4; |
83720594 | 9311 | int ehrd_size; |
b6c9286a | 9312 | int total_raw_size; |
4697a36c | 9313 | |
a4f6c312 | 9314 | /* Zero all fields portably. */ |
4697a36c MM |
9315 | info = zero_info; |
9316 | ||
c19de7aa AH |
9317 | if (TARGET_SPE) |
9318 | { | |
9319 | /* Cache value so we don't rescan instruction chain over and over. */ | |
9b7b447f AH |
9320 | if (cfun->machine->insn_chain_scanned_p == 0) |
9321 | { | |
9322 | cfun->machine->insn_chain_scanned_p = 1; | |
9323 | info_ptr->spe_64bit_regs_used = (int) spe_func_has_64bit_regs_p (); | |
9324 | } | |
c19de7aa AH |
9325 | } |
9326 | ||
a4f6c312 | 9327 | /* Select which calling sequence. */ |
178274da | 9328 | info_ptr->abi = DEFAULT_ABI; |
9878760c | 9329 | |
a4f6c312 | 9330 | /* Calculate which registers need to be saved & save area size. */ |
4697a36c | 9331 | info_ptr->first_gp_reg_save = first_reg_to_save (); |
1db02437 | 9332 | /* Assume that we will have to save RS6000_PIC_OFFSET_TABLE_REGNUM, |
906fb125 | 9333 | even if it currently looks like we won't. */ |
2bfcf297 | 9334 | if (((TARGET_TOC && TARGET_MINIMAL_TOC) |
178274da AM |
9335 | || (flag_pic == 1 && DEFAULT_ABI == ABI_V4) |
9336 | || (flag_pic && DEFAULT_ABI == ABI_DARWIN)) | |
1db02437 FS |
9337 | && info_ptr->first_gp_reg_save > RS6000_PIC_OFFSET_TABLE_REGNUM) |
9338 | info_ptr->gp_size = reg_size * (32 - RS6000_PIC_OFFSET_TABLE_REGNUM); | |
906fb125 GK |
9339 | else |
9340 | info_ptr->gp_size = reg_size * (32 - info_ptr->first_gp_reg_save); | |
4697a36c | 9341 | |
a3170dc6 AH |
9342 | /* For the SPE, we have an additional upper 32-bits on each GPR. |
9343 | Ideally we should save the entire 64-bits only when the upper | |
9344 | half is used in SIMD instructions. Since we only record | |
9345 | registers live (not the size they are used in), this proves | |
9346 | difficult because we'd have to traverse the instruction chain at | |
9347 | the right time, taking reload into account. This is a real pain, | |
c19de7aa AH |
9348 | so we opt to save the GPRs in 64-bits always if but one register |
9349 | gets used in 64-bits. Otherwise, all the registers in the frame | |
9350 | get saved in 32-bits. | |
a3170dc6 | 9351 | |
c19de7aa | 9352 | So... since when we save all GPRs (except the SP) in 64-bits, the |
a3170dc6 | 9353 | traditional GP save area will be empty. */ |
c19de7aa | 9354 | if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0) |
a3170dc6 AH |
9355 | info_ptr->gp_size = 0; |
9356 | ||
4697a36c MM |
9357 | info_ptr->first_fp_reg_save = first_fp_reg_to_save (); |
9358 | info_ptr->fp_size = 8 * (64 - info_ptr->first_fp_reg_save); | |
9359 | ||
00b960c7 AH |
9360 | info_ptr->first_altivec_reg_save = first_altivec_reg_to_save (); |
9361 | info_ptr->altivec_size = 16 * (LAST_ALTIVEC_REGNO + 1 | |
9362 | - info_ptr->first_altivec_reg_save); | |
9363 | ||
592696dd | 9364 | /* Does this function call anything? */ |
71f123ca FS |
9365 | info_ptr->calls_p = (! current_function_is_leaf |
9366 | || cfun->machine->ra_needs_full_frame); | |
b6c9286a | 9367 | |
a4f6c312 | 9368 | /* Determine if we need to save the link register. */ |
71f123ca | 9369 | if (rs6000_ra_ever_killed () |
ffcfcb5f AM |
9370 | || (DEFAULT_ABI == ABI_AIX |
9371 | && current_function_profile | |
9372 | && !TARGET_PROFILE_KERNEL) | |
4697a36c MM |
9373 | #ifdef TARGET_RELOCATABLE |
9374 | || (TARGET_RELOCATABLE && (get_pool_size () != 0)) | |
9375 | #endif | |
9376 | || (info_ptr->first_fp_reg_save != 64 | |
9377 | && !FP_SAVE_INLINE (info_ptr->first_fp_reg_save)) | |
00b960c7 | 9378 | || info_ptr->first_altivec_reg_save <= LAST_ALTIVEC_REGNO |
178274da | 9379 | || (DEFAULT_ABI == ABI_V4 && current_function_calls_alloca) |
a4f6c312 SS |
9380 | || (DEFAULT_ABI == ABI_DARWIN |
9381 | && flag_pic | |
9382 | && current_function_uses_pic_offset_table) | |
4697a36c MM |
9383 | || info_ptr->calls_p) |
9384 | { | |
9385 | info_ptr->lr_save_p = 1; | |
9ebbca7d | 9386 | regs_ever_live[LINK_REGISTER_REGNUM] = 1; |
4697a36c MM |
9387 | } |
9388 | ||
9ebbca7d GK |
9389 | /* Determine if we need to save the condition code registers. */ |
9390 | if (regs_ever_live[CR2_REGNO] | |
9391 | || regs_ever_live[CR3_REGNO] | |
9392 | || regs_ever_live[CR4_REGNO]) | |
4697a36c MM |
9393 | { |
9394 | info_ptr->cr_save_p = 1; | |
178274da | 9395 | if (DEFAULT_ABI == ABI_V4) |
4697a36c MM |
9396 | info_ptr->cr_size = reg_size; |
9397 | } | |
9398 | ||
83720594 RH |
9399 | /* If the current function calls __builtin_eh_return, then we need |
9400 | to allocate stack space for registers that will hold data for | |
9401 | the exception handler. */ | |
9402 | if (current_function_calls_eh_return) | |
9403 | { | |
9404 | unsigned int i; | |
9405 | for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; ++i) | |
9406 | continue; | |
a3170dc6 AH |
9407 | |
9408 | /* SPE saves EH registers in 64-bits. */ | |
c19de7aa AH |
9409 | ehrd_size = i * (TARGET_SPE_ABI |
9410 | && info_ptr->spe_64bit_regs_used != 0 | |
9411 | ? UNITS_PER_SPE_WORD : UNITS_PER_WORD); | |
83720594 RH |
9412 | } |
9413 | else | |
9414 | ehrd_size = 0; | |
9415 | ||
592696dd | 9416 | /* Determine various sizes. */ |
4697a36c MM |
9417 | info_ptr->reg_size = reg_size; |
9418 | info_ptr->fixed_size = RS6000_SAVE_AREA; | |
9419 | info_ptr->varargs_size = RS6000_VARARGS_AREA; | |
189e03e3 | 9420 | info_ptr->vars_size = RS6000_ALIGN (get_frame_size (), 8); |
a4f6c312 SS |
9421 | info_ptr->parm_size = RS6000_ALIGN (current_function_outgoing_args_size, |
9422 | 8); | |
00b960c7 | 9423 | |
c19de7aa | 9424 | if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0) |
a3170dc6 AH |
9425 | info_ptr->spe_gp_size = 8 * (32 - info_ptr->first_gp_reg_save); |
9426 | else | |
9427 | info_ptr->spe_gp_size = 0; | |
9428 | ||
08b57fb3 | 9429 | if (TARGET_ALTIVEC_ABI && TARGET_ALTIVEC_VRSAVE) |
00b960c7 AH |
9430 | { |
9431 | info_ptr->vrsave_mask = compute_vrsave_mask (); | |
9432 | info_ptr->vrsave_size = info_ptr->vrsave_mask ? 4 : 0; | |
9433 | } | |
9434 | else | |
9435 | { | |
9436 | info_ptr->vrsave_mask = 0; | |
9437 | info_ptr->vrsave_size = 0; | |
9438 | } | |
b6c9286a | 9439 | |
592696dd | 9440 | /* Calculate the offsets. */ |
178274da | 9441 | switch (DEFAULT_ABI) |
4697a36c | 9442 | { |
b6c9286a | 9443 | case ABI_NONE: |
24d304eb | 9444 | default: |
b6c9286a MM |
9445 | abort (); |
9446 | ||
9447 | case ABI_AIX: | |
ee890fe2 | 9448 | case ABI_DARWIN: |
b6c9286a MM |
9449 | info_ptr->fp_save_offset = - info_ptr->fp_size; |
9450 | info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size; | |
00b960c7 AH |
9451 | |
9452 | if (TARGET_ALTIVEC_ABI) | |
9453 | { | |
9454 | info_ptr->vrsave_save_offset | |
9455 | = info_ptr->gp_save_offset - info_ptr->vrsave_size; | |
9456 | ||
9457 | /* Align stack so vector save area is on a quadword boundary. */ | |
9458 | if (info_ptr->altivec_size != 0) | |
9459 | info_ptr->altivec_padding_size | |
9460 | = 16 - (-info_ptr->vrsave_save_offset % 16); | |
9461 | else | |
9462 | info_ptr->altivec_padding_size = 0; | |
9463 | ||
9464 | info_ptr->altivec_save_offset | |
9465 | = info_ptr->vrsave_save_offset | |
9466 | - info_ptr->altivec_padding_size | |
9467 | - info_ptr->altivec_size; | |
9468 | ||
9469 | /* Adjust for AltiVec case. */ | |
9470 | info_ptr->ehrd_offset = info_ptr->altivec_save_offset - ehrd_size; | |
9471 | } | |
9472 | else | |
9473 | info_ptr->ehrd_offset = info_ptr->gp_save_offset - ehrd_size; | |
a260abc9 DE |
9474 | info_ptr->cr_save_offset = reg_size; /* first word when 64-bit. */ |
9475 | info_ptr->lr_save_offset = 2*reg_size; | |
24d304eb RK |
9476 | break; |
9477 | ||
9478 | case ABI_V4: | |
b6c9286a MM |
9479 | info_ptr->fp_save_offset = - info_ptr->fp_size; |
9480 | info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size; | |
a7df97e6 | 9481 | info_ptr->cr_save_offset = info_ptr->gp_save_offset - info_ptr->cr_size; |
00b960c7 | 9482 | |
c19de7aa | 9483 | if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0) |
a3170dc6 AH |
9484 | { |
9485 | /* Align stack so SPE GPR save area is aligned on a | |
9486 | double-word boundary. */ | |
9487 | if (info_ptr->spe_gp_size != 0) | |
9488 | info_ptr->spe_padding_size | |
9489 | = 8 - (-info_ptr->cr_save_offset % 8); | |
9490 | else | |
9491 | info_ptr->spe_padding_size = 0; | |
9492 | ||
9493 | info_ptr->spe_gp_save_offset | |
9494 | = info_ptr->cr_save_offset | |
9495 | - info_ptr->spe_padding_size | |
9496 | - info_ptr->spe_gp_size; | |
9497 | ||
9498 | /* Adjust for SPE case. */ | |
9499 | info_ptr->toc_save_offset | |
9500 | = info_ptr->spe_gp_save_offset - info_ptr->toc_size; | |
9501 | } | |
9502 | else if (TARGET_ALTIVEC_ABI) | |
00b960c7 AH |
9503 | { |
9504 | info_ptr->vrsave_save_offset | |
9505 | = info_ptr->cr_save_offset - info_ptr->vrsave_size; | |
9506 | ||
9507 | /* Align stack so vector save area is on a quadword boundary. */ | |
9508 | if (info_ptr->altivec_size != 0) | |
9509 | info_ptr->altivec_padding_size | |
9510 | = 16 - (-info_ptr->vrsave_save_offset % 16); | |
9511 | else | |
9512 | info_ptr->altivec_padding_size = 0; | |
9513 | ||
9514 | info_ptr->altivec_save_offset | |
9515 | = info_ptr->vrsave_save_offset | |
9516 | - info_ptr->altivec_padding_size | |
9517 | - info_ptr->altivec_size; | |
9518 | ||
9519 | /* Adjust for AltiVec case. */ | |
9520 | info_ptr->toc_save_offset | |
9521 | = info_ptr->altivec_save_offset - info_ptr->toc_size; | |
9522 | } | |
9523 | else | |
9524 | info_ptr->toc_save_offset = info_ptr->cr_save_offset - info_ptr->toc_size; | |
83720594 | 9525 | info_ptr->ehrd_offset = info_ptr->toc_save_offset - ehrd_size; |
b6c9286a MM |
9526 | info_ptr->lr_save_offset = reg_size; |
9527 | break; | |
4697a36c MM |
9528 | } |
9529 | ||
00b960c7 AH |
9530 | info_ptr->save_size = RS6000_ALIGN (info_ptr->fp_size |
9531 | + info_ptr->gp_size | |
9532 | + info_ptr->altivec_size | |
9533 | + info_ptr->altivec_padding_size | |
9534 | + info_ptr->vrsave_size | |
a3170dc6 AH |
9535 | + info_ptr->spe_gp_size |
9536 | + info_ptr->spe_padding_size | |
00b960c7 AH |
9537 | + ehrd_size |
9538 | + info_ptr->cr_size | |
9539 | + info_ptr->lr_size | |
9540 | + info_ptr->vrsave_size | |
9541 | + info_ptr->toc_size, | |
9542 | (TARGET_ALTIVEC_ABI || ABI_DARWIN) | |
9543 | ? 16 : 8); | |
9544 | ||
ff381587 MM |
9545 | total_raw_size = (info_ptr->vars_size |
9546 | + info_ptr->parm_size | |
ff381587 MM |
9547 | + info_ptr->save_size |
9548 | + info_ptr->varargs_size | |
9549 | + info_ptr->fixed_size); | |
9550 | ||
a4f6c312 SS |
9551 | info_ptr->total_size = |
9552 | RS6000_ALIGN (total_raw_size, ABI_STACK_BOUNDARY / BITS_PER_UNIT); | |
ff381587 MM |
9553 | |
9554 | /* Determine if we need to allocate any stack frame: | |
9555 | ||
a4f6c312 SS |
9556 | For AIX we need to push the stack if a frame pointer is needed |
9557 | (because the stack might be dynamically adjusted), if we are | |
9558 | debugging, if we make calls, or if the sum of fp_save, gp_save, | |
9559 | and local variables are more than the space needed to save all | |
9560 | non-volatile registers: 32-bit: 18*8 + 19*4 = 220 or 64-bit: 18*8 | |
9561 | + 18*8 = 288 (GPR13 reserved). | |
ff381587 | 9562 | |
a4f6c312 SS |
9563 | For V.4 we don't have the stack cushion that AIX uses, but assume |
9564 | that the debugger can handle stackless frames. */ | |
ff381587 MM |
9565 | |
9566 | if (info_ptr->calls_p) | |
9567 | info_ptr->push_p = 1; | |
9568 | ||
178274da | 9569 | else if (DEFAULT_ABI == ABI_V4) |
e72247f4 | 9570 | info_ptr->push_p = total_raw_size > info_ptr->fixed_size; |
ff381587 | 9571 | |
178274da AM |
9572 | else if (frame_pointer_needed) |
9573 | info_ptr->push_p = 1; | |
9574 | ||
9575 | else if (TARGET_XCOFF && write_symbols != NO_DEBUG) | |
9576 | info_ptr->push_p = 1; | |
9577 | ||
ff381587 | 9578 | else |
178274da AM |
9579 | info_ptr->push_p |
9580 | = total_raw_size - info_ptr->fixed_size > (TARGET_32BIT ? 220 : 288); | |
ff381587 | 9581 | |
a4f6c312 | 9582 | /* Zero offsets if we're not saving those registers. */ |
8dda1a21 | 9583 | if (info_ptr->fp_size == 0) |
4697a36c MM |
9584 | info_ptr->fp_save_offset = 0; |
9585 | ||
8dda1a21 | 9586 | if (info_ptr->gp_size == 0) |
4697a36c MM |
9587 | info_ptr->gp_save_offset = 0; |
9588 | ||
00b960c7 AH |
9589 | if (! TARGET_ALTIVEC_ABI || info_ptr->altivec_size == 0) |
9590 | info_ptr->altivec_save_offset = 0; | |
9591 | ||
9592 | if (! TARGET_ALTIVEC_ABI || info_ptr->vrsave_mask == 0) | |
9593 | info_ptr->vrsave_save_offset = 0; | |
9594 | ||
c19de7aa AH |
9595 | if (! TARGET_SPE_ABI |
9596 | || info_ptr->spe_64bit_regs_used == 0 | |
9597 | || info_ptr->spe_gp_size == 0) | |
a3170dc6 AH |
9598 | info_ptr->spe_gp_save_offset = 0; |
9599 | ||
c81fc13e | 9600 | if (! info_ptr->lr_save_p) |
4697a36c MM |
9601 | info_ptr->lr_save_offset = 0; |
9602 | ||
c81fc13e | 9603 | if (! info_ptr->cr_save_p) |
4697a36c MM |
9604 | info_ptr->cr_save_offset = 0; |
9605 | ||
c81fc13e | 9606 | if (! info_ptr->toc_save_p) |
b6c9286a MM |
9607 | info_ptr->toc_save_offset = 0; |
9608 | ||
4697a36c MM |
9609 | return info_ptr; |
9610 | } | |
9611 | ||
c19de7aa AH |
9612 | /* Return true if the current function uses any GPRs in 64-bit SIMD |
9613 | mode. */ | |
9614 | ||
9615 | static bool | |
9616 | spe_func_has_64bit_regs_p () | |
9617 | { | |
9618 | rtx insns, insn; | |
9619 | ||
9620 | /* Functions that save and restore all the call-saved registers will | |
9621 | need to save/restore the registers in 64-bits. */ | |
9622 | if (current_function_calls_eh_return | |
9623 | || current_function_calls_setjmp | |
9624 | || current_function_has_nonlocal_goto) | |
9625 | return true; | |
9626 | ||
9627 | insns = get_insns (); | |
9628 | ||
9629 | for (insn = NEXT_INSN (insns); insn != NULL_RTX; insn = NEXT_INSN (insn)) | |
9630 | { | |
9631 | if (INSN_P (insn)) | |
9632 | { | |
9633 | rtx i; | |
9634 | ||
9635 | i = PATTERN (insn); | |
9636 | if (GET_CODE (i) == SET | |
9637 | && SPE_VECTOR_MODE (GET_MODE (SET_SRC (i)))) | |
9638 | return true; | |
9639 | } | |
9640 | } | |
9641 | ||
9642 | return false; | |
9643 | } | |
9644 | ||
4697a36c MM |
9645 | void |
9646 | debug_stack_info (info) | |
9647 | rs6000_stack_t *info; | |
9878760c | 9648 | { |
d330fd93 | 9649 | const char *abi_string; |
24d304eb | 9650 | |
c81fc13e | 9651 | if (! info) |
4697a36c MM |
9652 | info = rs6000_stack_info (); |
9653 | ||
9654 | fprintf (stderr, "\nStack information for function %s:\n", | |
9655 | ((current_function_decl && DECL_NAME (current_function_decl)) | |
9656 | ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl)) | |
9657 | : "<unknown>")); | |
9658 | ||
24d304eb RK |
9659 | switch (info->abi) |
9660 | { | |
b6c9286a MM |
9661 | default: abi_string = "Unknown"; break; |
9662 | case ABI_NONE: abi_string = "NONE"; break; | |
50d440bc | 9663 | case ABI_AIX: abi_string = "AIX"; break; |
ee890fe2 | 9664 | case ABI_DARWIN: abi_string = "Darwin"; break; |
b6c9286a | 9665 | case ABI_V4: abi_string = "V.4"; break; |
24d304eb RK |
9666 | } |
9667 | ||
9668 | fprintf (stderr, "\tABI = %5s\n", abi_string); | |
9669 | ||
00b960c7 AH |
9670 | if (TARGET_ALTIVEC_ABI) |
9671 | fprintf (stderr, "\tALTIVEC ABI extensions enabled.\n"); | |
9672 | ||
a3170dc6 AH |
9673 | if (TARGET_SPE_ABI) |
9674 | fprintf (stderr, "\tSPE ABI extensions enabled.\n"); | |
9675 | ||
4697a36c MM |
9676 | if (info->first_gp_reg_save != 32) |
9677 | fprintf (stderr, "\tfirst_gp_reg_save = %5d\n", info->first_gp_reg_save); | |
9678 | ||
9679 | if (info->first_fp_reg_save != 64) | |
9680 | fprintf (stderr, "\tfirst_fp_reg_save = %5d\n", info->first_fp_reg_save); | |
9878760c | 9681 | |
00b960c7 AH |
9682 | if (info->first_altivec_reg_save <= LAST_ALTIVEC_REGNO) |
9683 | fprintf (stderr, "\tfirst_altivec_reg_save = %5d\n", | |
9684 | info->first_altivec_reg_save); | |
9685 | ||
4697a36c MM |
9686 | if (info->lr_save_p) |
9687 | fprintf (stderr, "\tlr_save_p = %5d\n", info->lr_save_p); | |
9878760c | 9688 | |
4697a36c MM |
9689 | if (info->cr_save_p) |
9690 | fprintf (stderr, "\tcr_save_p = %5d\n", info->cr_save_p); | |
9691 | ||
b6c9286a MM |
9692 | if (info->toc_save_p) |
9693 | fprintf (stderr, "\ttoc_save_p = %5d\n", info->toc_save_p); | |
9694 | ||
00b960c7 AH |
9695 | if (info->vrsave_mask) |
9696 | fprintf (stderr, "\tvrsave_mask = 0x%x\n", info->vrsave_mask); | |
9697 | ||
4697a36c MM |
9698 | if (info->push_p) |
9699 | fprintf (stderr, "\tpush_p = %5d\n", info->push_p); | |
9700 | ||
9701 | if (info->calls_p) | |
9702 | fprintf (stderr, "\tcalls_p = %5d\n", info->calls_p); | |
9703 | ||
4697a36c MM |
9704 | if (info->gp_save_offset) |
9705 | fprintf (stderr, "\tgp_save_offset = %5d\n", info->gp_save_offset); | |
9706 | ||
9707 | if (info->fp_save_offset) | |
9708 | fprintf (stderr, "\tfp_save_offset = %5d\n", info->fp_save_offset); | |
9709 | ||
00b960c7 AH |
9710 | if (info->altivec_save_offset) |
9711 | fprintf (stderr, "\taltivec_save_offset = %5d\n", | |
9712 | info->altivec_save_offset); | |
9713 | ||
a3170dc6 AH |
9714 | if (info->spe_gp_save_offset) |
9715 | fprintf (stderr, "\tspe_gp_save_offset = %5d\n", | |
9716 | info->spe_gp_save_offset); | |
9717 | ||
00b960c7 AH |
9718 | if (info->vrsave_save_offset) |
9719 | fprintf (stderr, "\tvrsave_save_offset = %5d\n", | |
9720 | info->vrsave_save_offset); | |
9721 | ||
4697a36c MM |
9722 | if (info->lr_save_offset) |
9723 | fprintf (stderr, "\tlr_save_offset = %5d\n", info->lr_save_offset); | |
9724 | ||
9725 | if (info->cr_save_offset) | |
9726 | fprintf (stderr, "\tcr_save_offset = %5d\n", info->cr_save_offset); | |
9727 | ||
b6c9286a MM |
9728 | if (info->toc_save_offset) |
9729 | fprintf (stderr, "\ttoc_save_offset = %5d\n", info->toc_save_offset); | |
9730 | ||
4697a36c MM |
9731 | if (info->varargs_save_offset) |
9732 | fprintf (stderr, "\tvarargs_save_offset = %5d\n", info->varargs_save_offset); | |
9733 | ||
9734 | if (info->total_size) | |
9735 | fprintf (stderr, "\ttotal_size = %5d\n", info->total_size); | |
9736 | ||
9737 | if (info->varargs_size) | |
9738 | fprintf (stderr, "\tvarargs_size = %5d\n", info->varargs_size); | |
9739 | ||
9740 | if (info->vars_size) | |
9741 | fprintf (stderr, "\tvars_size = %5d\n", info->vars_size); | |
9742 | ||
9743 | if (info->parm_size) | |
9744 | fprintf (stderr, "\tparm_size = %5d\n", info->parm_size); | |
9745 | ||
9746 | if (info->fixed_size) | |
9747 | fprintf (stderr, "\tfixed_size = %5d\n", info->fixed_size); | |
9748 | ||
9749 | if (info->gp_size) | |
9750 | fprintf (stderr, "\tgp_size = %5d\n", info->gp_size); | |
9751 | ||
a3170dc6 AH |
9752 | if (info->spe_gp_size) |
9753 | fprintf (stderr, "\tspe_gp_size = %5d\n", info->spe_gp_size); | |
9754 | ||
4697a36c MM |
9755 | if (info->fp_size) |
9756 | fprintf (stderr, "\tfp_size = %5d\n", info->fp_size); | |
9757 | ||
00b960c7 AH |
9758 | if (info->altivec_size) |
9759 | fprintf (stderr, "\taltivec_size = %5d\n", info->altivec_size); | |
9760 | ||
9761 | if (info->vrsave_size) | |
9762 | fprintf (stderr, "\tvrsave_size = %5d\n", info->vrsave_size); | |
9763 | ||
9764 | if (info->altivec_padding_size) | |
9765 | fprintf (stderr, "\taltivec_padding_size= %5d\n", | |
9766 | info->altivec_padding_size); | |
9767 | ||
a3170dc6 AH |
9768 | if (info->spe_padding_size) |
9769 | fprintf (stderr, "\tspe_padding_size = %5d\n", | |
9770 | info->spe_padding_size); | |
9771 | ||
a4f6c312 | 9772 | if (info->lr_size) |
ed947a96 | 9773 | fprintf (stderr, "\tlr_size = %5d\n", info->lr_size); |
b6c9286a | 9774 | |
4697a36c MM |
9775 | if (info->cr_size) |
9776 | fprintf (stderr, "\tcr_size = %5d\n", info->cr_size); | |
9777 | ||
a4f6c312 | 9778 | if (info->toc_size) |
b6c9286a MM |
9779 | fprintf (stderr, "\ttoc_size = %5d\n", info->toc_size); |
9780 | ||
4697a36c MM |
9781 | if (info->save_size) |
9782 | fprintf (stderr, "\tsave_size = %5d\n", info->save_size); | |
9783 | ||
9784 | if (info->reg_size != 4) | |
9785 | fprintf (stderr, "\treg_size = %5d\n", info->reg_size); | |
9786 | ||
9787 | fprintf (stderr, "\n"); | |
9878760c | 9788 | } |
71f123ca FS |
9789 | |
9790 | rtx | |
9791 | rs6000_return_addr (count, frame) | |
9792 | int count; | |
9793 | rtx frame; | |
9794 | { | |
a4f6c312 SS |
9795 | /* Currently we don't optimize very well between prolog and body |
9796 | code and for PIC code the code can be actually quite bad, so | |
9797 | don't try to be too clever here. */ | |
f1384257 | 9798 | if (count != 0 || (DEFAULT_ABI != ABI_AIX && flag_pic)) |
71f123ca FS |
9799 | { |
9800 | cfun->machine->ra_needs_full_frame = 1; | |
8ac61af7 RK |
9801 | |
9802 | return | |
9803 | gen_rtx_MEM | |
9804 | (Pmode, | |
9805 | memory_address | |
9806 | (Pmode, | |
9807 | plus_constant (copy_to_reg | |
9808 | (gen_rtx_MEM (Pmode, | |
9809 | memory_address (Pmode, frame))), | |
9810 | RETURN_ADDRESS_OFFSET))); | |
71f123ca FS |
9811 | } |
9812 | ||
9e2f7ec7 | 9813 | return get_hard_reg_initial_val (Pmode, LINK_REGISTER_REGNUM); |
71f123ca FS |
9814 | } |
9815 | ||
5e1bf043 DJ |
9816 | /* Say whether a function is a candidate for sibcall handling or not. |
9817 | We do not allow indirect calls to be optimized into sibling calls. | |
9818 | Also, we can't do it if there are any vector parameters; there's | |
9819 | nowhere to put the VRsave code so it works; note that functions with | |
9820 | vector parameters are required to have a prototype, so the argument | |
9821 | type info must be available here. (The tail recursion case can work | |
9822 | with vector parameters, but there's no way to distinguish here.) */ | |
4977bab6 ZW |
9823 | static bool |
9824 | rs6000_function_ok_for_sibcall (decl, exp) | |
9825 | tree decl; | |
9826 | tree exp ATTRIBUTE_UNUSED; | |
5e1bf043 DJ |
9827 | { |
9828 | tree type; | |
4977bab6 | 9829 | if (decl) |
5e1bf043 DJ |
9830 | { |
9831 | if (TARGET_ALTIVEC_VRSAVE) | |
9832 | { | |
4977bab6 | 9833 | for (type = TYPE_ARG_TYPES (TREE_TYPE (decl)); |
5e1bf043 DJ |
9834 | type; type = TREE_CHAIN (type)) |
9835 | { | |
c15b529f | 9836 | if (TREE_CODE (TREE_VALUE (type)) == VECTOR_TYPE) |
4977bab6 | 9837 | return false; |
5e1bf043 DJ |
9838 | } |
9839 | } | |
9840 | if (DEFAULT_ABI == ABI_DARWIN | |
4977bab6 | 9841 | || (*targetm.binds_local_p) (decl)) |
2bcc50d0 | 9842 | { |
4977bab6 | 9843 | tree attr_list = TYPE_ATTRIBUTES (TREE_TYPE (decl)); |
2bcc50d0 AM |
9844 | |
9845 | if (!lookup_attribute ("longcall", attr_list) | |
9846 | || lookup_attribute ("shortcall", attr_list)) | |
4977bab6 | 9847 | return true; |
2bcc50d0 | 9848 | } |
5e1bf043 | 9849 | } |
4977bab6 | 9850 | return false; |
5e1bf043 DJ |
9851 | } |
9852 | ||
71f123ca FS |
9853 | static int |
9854 | rs6000_ra_ever_killed () | |
9855 | { | |
9856 | rtx top; | |
5e1bf043 DJ |
9857 | rtx reg; |
9858 | rtx insn; | |
71f123ca | 9859 | |
3961e8fe RH |
9860 | /* Irritatingly, there are two kinds of thunks -- those created with |
9861 | TARGET_ASM_OUTPUT_MI_THUNK and those with DECL_THUNK_P that go | |
9862 | through the regular part of the compiler. This is a very hacky | |
9863 | way to tell them apart. */ | |
9864 | if (current_function_is_thunk && !no_new_pseudos) | |
71f123ca | 9865 | return 0; |
eb0424da | 9866 | |
36f7e964 AH |
9867 | /* regs_ever_live has LR marked as used if any sibcalls are present, |
9868 | but this should not force saving and restoring in the | |
9869 | pro/epilogue. Likewise, reg_set_between_p thinks a sibcall | |
9870 | clobbers LR, so that is inappropriate. */ | |
9871 | ||
5e1bf043 DJ |
9872 | /* Also, the prologue can generate a store into LR that |
9873 | doesn't really count, like this: | |
36f7e964 | 9874 | |
5e1bf043 DJ |
9875 | move LR->R0 |
9876 | bcl to set PIC register | |
9877 | move LR->R31 | |
9878 | move R0->LR | |
36f7e964 AH |
9879 | |
9880 | When we're called from the epilogue, we need to avoid counting | |
9881 | this as a store. */ | |
5e1bf043 | 9882 | |
71f123ca FS |
9883 | push_topmost_sequence (); |
9884 | top = get_insns (); | |
9885 | pop_topmost_sequence (); | |
5e1bf043 | 9886 | reg = gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM); |
71f123ca | 9887 | |
5e1bf043 DJ |
9888 | for (insn = NEXT_INSN (top); insn != NULL_RTX; insn = NEXT_INSN (insn)) |
9889 | { | |
9890 | if (INSN_P (insn)) | |
9891 | { | |
9892 | if (FIND_REG_INC_NOTE (insn, reg)) | |
9893 | return 1; | |
9894 | else if (GET_CODE (insn) == CALL_INSN | |
c15b529f | 9895 | && !SIBLING_CALL_P (insn)) |
5e1bf043 | 9896 | return 1; |
36f7e964 AH |
9897 | else if (set_of (reg, insn) != NULL_RTX |
9898 | && !prologue_epilogue_contains (insn)) | |
5e1bf043 DJ |
9899 | return 1; |
9900 | } | |
9901 | } | |
9902 | return 0; | |
71f123ca | 9903 | } |
4697a36c | 9904 | \f |
8cd8f856 GK |
9905 | /* Add a REG_MAYBE_DEAD note to the insn. */ |
9906 | static void | |
9907 | rs6000_maybe_dead (insn) | |
9908 | rtx insn; | |
9909 | { | |
9910 | REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD, | |
9911 | const0_rtx, | |
9912 | REG_NOTES (insn)); | |
9913 | } | |
9914 | ||
9ebbca7d | 9915 | /* Emit instructions needed to load the TOC register. |
c7ca610e | 9916 | This is only needed when TARGET_TOC, TARGET_MINIMAL_TOC, and there is |
9ebbca7d | 9917 | a constant pool; or for SVR4 -fpic. */ |
c7ca610e RK |
9918 | |
9919 | void | |
9ebbca7d GK |
9920 | rs6000_emit_load_toc_table (fromprolog) |
9921 | int fromprolog; | |
c7ca610e | 9922 | { |
027fbf43 | 9923 | rtx dest, insn; |
1db02437 | 9924 | dest = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM); |
c7ca610e | 9925 | |
20b71b17 AM |
9926 | if (TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 1) |
9927 | { | |
9928 | rtx temp = (fromprolog | |
9929 | ? gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM) | |
9930 | : gen_reg_rtx (Pmode)); | |
027fbf43 JJ |
9931 | insn = emit_insn (gen_load_toc_v4_pic_si (temp)); |
9932 | if (fromprolog) | |
9933 | rs6000_maybe_dead (insn); | |
9934 | insn = emit_move_insn (dest, temp); | |
9935 | if (fromprolog) | |
9936 | rs6000_maybe_dead (insn); | |
20b71b17 AM |
9937 | } |
9938 | else if (TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2) | |
9939 | { | |
9940 | char buf[30]; | |
9941 | rtx tempLR = (fromprolog | |
9942 | ? gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM) | |
9943 | : gen_reg_rtx (Pmode)); | |
9944 | rtx temp0 = (fromprolog | |
9945 | ? gen_rtx_REG (Pmode, 0) | |
9946 | : gen_reg_rtx (Pmode)); | |
9947 | rtx symF; | |
9948 | ||
9949 | /* possibly create the toc section */ | |
9950 | if (! toc_initialized) | |
38c1f2d7 | 9951 | { |
20b71b17 AM |
9952 | toc_section (); |
9953 | function_section (current_function_decl); | |
38c1f2d7 | 9954 | } |
9ebbca7d | 9955 | |
20b71b17 AM |
9956 | if (fromprolog) |
9957 | { | |
9958 | rtx symL; | |
38c1f2d7 | 9959 | |
20b71b17 AM |
9960 | ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno); |
9961 | symF = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); | |
9ebbca7d | 9962 | |
20b71b17 AM |
9963 | ASM_GENERATE_INTERNAL_LABEL (buf, "LCL", rs6000_pic_labelno); |
9964 | symL = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); | |
9965 | ||
9966 | rs6000_maybe_dead (emit_insn (gen_load_toc_v4_PIC_1 (tempLR, | |
9967 | symF))); | |
9968 | rs6000_maybe_dead (emit_move_insn (dest, tempLR)); | |
9969 | rs6000_maybe_dead (emit_insn (gen_load_toc_v4_PIC_2 (temp0, dest, | |
9970 | symL, | |
9971 | symF))); | |
9ebbca7d GK |
9972 | } |
9973 | else | |
20b71b17 AM |
9974 | { |
9975 | rtx tocsym; | |
9976 | static int reload_toc_labelno = 0; | |
9977 | ||
9978 | tocsym = gen_rtx_SYMBOL_REF (Pmode, toc_label_name); | |
9979 | ||
9980 | ASM_GENERATE_INTERNAL_LABEL (buf, "LCG", reload_toc_labelno++); | |
9981 | symF = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); | |
9982 | ||
027fbf43 JJ |
9983 | emit_insn (gen_load_toc_v4_PIC_1b (tempLR, symF, tocsym)); |
9984 | emit_move_insn (dest, tempLR); | |
9985 | emit_move_insn (temp0, gen_rtx_MEM (Pmode, dest)); | |
20b71b17 | 9986 | } |
027fbf43 JJ |
9987 | insn = emit_insn (gen_addsi3 (dest, temp0, dest)); |
9988 | if (fromprolog) | |
9989 | rs6000_maybe_dead (insn); | |
9ebbca7d | 9990 | } |
20b71b17 AM |
9991 | else if (TARGET_ELF && !TARGET_AIX && flag_pic == 0 && TARGET_MINIMAL_TOC) |
9992 | { | |
9993 | /* This is for AIX code running in non-PIC ELF32. */ | |
9994 | char buf[30]; | |
9995 | rtx realsym; | |
9996 | ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1); | |
9997 | realsym = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); | |
9998 | ||
027fbf43 JJ |
9999 | insn = emit_insn (gen_elf_high (dest, realsym)); |
10000 | if (fromprolog) | |
10001 | rs6000_maybe_dead (insn); | |
10002 | insn = emit_insn (gen_elf_low (dest, dest, realsym)); | |
10003 | if (fromprolog) | |
10004 | rs6000_maybe_dead (insn); | |
20b71b17 AM |
10005 | } |
10006 | else if (DEFAULT_ABI == ABI_AIX) | |
9ebbca7d GK |
10007 | { |
10008 | if (TARGET_32BIT) | |
027fbf43 | 10009 | insn = emit_insn (gen_load_toc_aix_si (dest)); |
9ebbca7d | 10010 | else |
027fbf43 JJ |
10011 | insn = emit_insn (gen_load_toc_aix_di (dest)); |
10012 | if (fromprolog) | |
10013 | rs6000_maybe_dead (insn); | |
9ebbca7d | 10014 | } |
20b71b17 AM |
10015 | else |
10016 | abort (); | |
9ebbca7d GK |
10017 | } |
10018 | ||
10019 | int | |
10020 | get_TOC_alias_set () | |
10021 | { | |
10022 | static int set = -1; | |
10023 | if (set == -1) | |
10024 | set = new_alias_set (); | |
10025 | return set; | |
10026 | } | |
10027 | ||
10028 | /* This retuns nonzero if the current function uses the TOC. This is | |
615158e2 JJ |
10029 | determined by the presence of (unspec ... UNSPEC_TOC), which is |
10030 | generated by the various load_toc_* patterns. */ | |
a4f6c312 | 10031 | |
9ebbca7d GK |
10032 | int |
10033 | uses_TOC () | |
10034 | { | |
10035 | rtx insn; | |
38c1f2d7 | 10036 | |
9ebbca7d | 10037 | for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) |
2c3c49de | 10038 | if (INSN_P (insn)) |
9ebbca7d GK |
10039 | { |
10040 | rtx pat = PATTERN (insn); | |
10041 | int i; | |
10042 | ||
8cd8f856 | 10043 | if (GET_CODE (pat) == PARALLEL) |
9ebbca7d GK |
10044 | for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++) |
10045 | if (GET_CODE (XVECEXP (PATTERN (insn), 0, i)) == UNSPEC | |
615158e2 | 10046 | && XINT (XVECEXP (PATTERN (insn), 0, i), 1) == UNSPEC_TOC) |
9ebbca7d | 10047 | return 1; |
38c1f2d7 | 10048 | } |
9ebbca7d GK |
10049 | return 0; |
10050 | } | |
38c1f2d7 | 10051 | |
9ebbca7d | 10052 | rtx |
a4f6c312 | 10053 | create_TOC_reference (symbol) |
9ebbca7d GK |
10054 | rtx symbol; |
10055 | { | |
a8a05998 ZW |
10056 | return gen_rtx_PLUS (Pmode, |
10057 | gen_rtx_REG (Pmode, TOC_REGISTER), | |
10058 | gen_rtx_CONST (Pmode, | |
10059 | gen_rtx_MINUS (Pmode, symbol, | |
b999aaeb | 10060 | gen_rtx_SYMBOL_REF (Pmode, toc_label_name)))); |
9ebbca7d | 10061 | } |
38c1f2d7 | 10062 | |
9ebbca7d GK |
10063 | #if TARGET_AIX |
10064 | /* __throw will restore its own return address to be the same as the | |
10065 | return address of the function that the throw is being made to. | |
10066 | This is unfortunate, because we want to check the original | |
10067 | return address to see if we need to restore the TOC. | |
10068 | So we have to squirrel it away here. | |
10069 | This is used only in compiling __throw and __rethrow. | |
c7ca610e | 10070 | |
9ebbca7d GK |
10071 | Most of this code should be removed by CSE. */ |
10072 | static rtx insn_after_throw; | |
c7ca610e | 10073 | |
a4f6c312 | 10074 | /* This does the saving... */ |
9ebbca7d GK |
10075 | void |
10076 | rs6000_aix_emit_builtin_unwind_init () | |
10077 | { | |
10078 | rtx mem; | |
10079 | rtx stack_top = gen_reg_rtx (Pmode); | |
10080 | rtx opcode_addr = gen_reg_rtx (Pmode); | |
10081 | ||
10082 | insn_after_throw = gen_reg_rtx (SImode); | |
10083 | ||
10084 | mem = gen_rtx_MEM (Pmode, hard_frame_pointer_rtx); | |
10085 | emit_move_insn (stack_top, mem); | |
10086 | ||
10087 | mem = gen_rtx_MEM (Pmode, | |
10088 | gen_rtx_PLUS (Pmode, stack_top, | |
10089 | GEN_INT (2 * GET_MODE_SIZE (Pmode)))); | |
10090 | emit_move_insn (opcode_addr, mem); | |
10091 | emit_move_insn (insn_after_throw, gen_rtx_MEM (SImode, opcode_addr)); | |
c7ca610e RK |
10092 | } |
10093 | ||
a4f6c312 SS |
10094 | /* Emit insns to _restore_ the TOC register, at runtime (specifically |
10095 | in _eh.o). Only used on AIX. | |
9ebbca7d GK |
10096 | |
10097 | The idea is that on AIX, function calls look like this: | |
10098 | bl somefunction-trampoline | |
10099 | lwz r2,20(sp) | |
10100 | ||
a4f6c312 | 10101 | and later, |
9ebbca7d GK |
10102 | somefunction-trampoline: |
10103 | stw r2,20(sp) | |
10104 | ... load function address in the count register ... | |
10105 | bctr | |
10106 | or like this, if the linker determines that this is not a cross-module call | |
10107 | and so the TOC need not be restored: | |
10108 | bl somefunction | |
10109 | nop | |
10110 | or like this, if the compiler could determine that this is not a | |
10111 | cross-module call: | |
10112 | bl somefunction | |
10113 | now, the tricky bit here is that register 2 is saved and restored | |
10114 | by the _linker_, so we can't readily generate debugging information | |
10115 | for it. So we need to go back up the call chain looking at the | |
10116 | insns at return addresses to see which calls saved the TOC register | |
10117 | and so see where it gets restored from. | |
10118 | ||
10119 | Oh, and all this gets done in RTL inside the eh_epilogue pattern, | |
10120 | just before the actual epilogue. | |
10121 | ||
10122 | On the bright side, this incurs no space or time overhead unless an | |
10123 | exception is thrown, except for the extra code in libgcc.a. | |
10124 | ||
10125 | The parameter STACKSIZE is a register containing (at runtime) | |
10126 | the amount to be popped off the stack in addition to the stack frame | |
10127 | of this routine (which will be __throw or __rethrow, and so is | |
10128 | guaranteed to have a stack frame). */ | |
a4f6c312 | 10129 | |
9ebbca7d GK |
10130 | void |
10131 | rs6000_emit_eh_toc_restore (stacksize) | |
10132 | rtx stacksize; | |
10133 | { | |
10134 | rtx top_of_stack; | |
10135 | rtx bottom_of_stack = gen_reg_rtx (Pmode); | |
10136 | rtx tocompare = gen_reg_rtx (SImode); | |
10137 | rtx opcode = gen_reg_rtx (SImode); | |
10138 | rtx opcode_addr = gen_reg_rtx (Pmode); | |
10139 | rtx mem; | |
10140 | rtx loop_start = gen_label_rtx (); | |
10141 | rtx no_toc_restore_needed = gen_label_rtx (); | |
10142 | rtx loop_exit = gen_label_rtx (); | |
10143 | ||
10144 | mem = gen_rtx_MEM (Pmode, hard_frame_pointer_rtx); | |
ba4828e0 | 10145 | set_mem_alias_set (mem, rs6000_sr_alias_set); |
9ebbca7d GK |
10146 | emit_move_insn (bottom_of_stack, mem); |
10147 | ||
10148 | top_of_stack = expand_binop (Pmode, add_optab, | |
10149 | bottom_of_stack, stacksize, | |
10150 | NULL_RTX, 1, OPTAB_WIDEN); | |
10151 | ||
2496c7bd LB |
10152 | emit_move_insn (tocompare, gen_int_mode (TARGET_32BIT ? 0x80410014 |
10153 | : 0xE8410028, SImode)); | |
9ebbca7d GK |
10154 | |
10155 | if (insn_after_throw == NULL_RTX) | |
a4f6c312 | 10156 | abort (); |
9ebbca7d GK |
10157 | emit_move_insn (opcode, insn_after_throw); |
10158 | ||
6496a589 | 10159 | emit_note (NULL, NOTE_INSN_LOOP_BEG); |
9ebbca7d GK |
10160 | emit_label (loop_start); |
10161 | ||
10162 | do_compare_rtx_and_jump (opcode, tocompare, NE, 1, | |
06f4e019 | 10163 | SImode, NULL_RTX, NULL_RTX, |
9ebbca7d GK |
10164 | no_toc_restore_needed); |
10165 | ||
10166 | mem = gen_rtx_MEM (Pmode, | |
10167 | gen_rtx_PLUS (Pmode, bottom_of_stack, | |
10168 | GEN_INT (5 * GET_MODE_SIZE (Pmode)))); | |
10169 | emit_move_insn (gen_rtx_REG (Pmode, 2), mem); | |
10170 | ||
10171 | emit_label (no_toc_restore_needed); | |
10172 | do_compare_rtx_and_jump (top_of_stack, bottom_of_stack, EQ, 1, | |
06f4e019 | 10173 | Pmode, NULL_RTX, NULL_RTX, |
9ebbca7d GK |
10174 | loop_exit); |
10175 | ||
10176 | mem = gen_rtx_MEM (Pmode, bottom_of_stack); | |
ba4828e0 | 10177 | set_mem_alias_set (mem, rs6000_sr_alias_set); |
9ebbca7d GK |
10178 | emit_move_insn (bottom_of_stack, mem); |
10179 | ||
10180 | mem = gen_rtx_MEM (Pmode, | |
10181 | gen_rtx_PLUS (Pmode, bottom_of_stack, | |
10182 | GEN_INT (2 * GET_MODE_SIZE (Pmode)))); | |
10183 | emit_move_insn (opcode_addr, mem); | |
10184 | emit_move_insn (opcode, gen_rtx_MEM (SImode, opcode_addr)); | |
10185 | ||
6496a589 | 10186 | emit_note (NULL, NOTE_INSN_LOOP_CONT); |
9ebbca7d | 10187 | emit_jump (loop_start); |
6496a589 | 10188 | emit_note (NULL, NOTE_INSN_LOOP_END); |
9ebbca7d GK |
10189 | emit_label (loop_exit); |
10190 | } | |
10191 | #endif /* TARGET_AIX */ | |
38c1f2d7 | 10192 | \f |
ba4828e0 RK |
10193 | /* This ties together stack memory (MEM with an alias set of |
10194 | rs6000_sr_alias_set) and the change to the stack pointer. */ | |
10195 | ||
9ebbca7d GK |
10196 | static void |
10197 | rs6000_emit_stack_tie () | |
10198 | { | |
ba4828e0 RK |
10199 | rtx mem = gen_rtx_MEM (BLKmode, gen_rtx_REG (Pmode, STACK_POINTER_REGNUM)); |
10200 | ||
10201 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
9ebbca7d GK |
10202 | emit_insn (gen_stack_tie (mem)); |
10203 | } | |
38c1f2d7 | 10204 | |
9ebbca7d GK |
10205 | /* Emit the correct code for allocating stack space, as insns. |
10206 | If COPY_R12, make sure a copy of the old frame is left in r12. | |
10207 | The generated code may use hard register 0 as a temporary. */ | |
10208 | ||
10209 | static void | |
10210 | rs6000_emit_allocate_stack (size, copy_r12) | |
10211 | HOST_WIDE_INT size; | |
38c1f2d7 MM |
10212 | int copy_r12; |
10213 | { | |
9ebbca7d GK |
10214 | rtx insn; |
10215 | rtx stack_reg = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM); | |
10216 | rtx tmp_reg = gen_rtx_REG (Pmode, 0); | |
10217 | rtx todec = GEN_INT (-size); | |
a157febd GK |
10218 | |
10219 | if (current_function_limit_stack) | |
10220 | { | |
10221 | if (REG_P (stack_limit_rtx) | |
10222 | && REGNO (stack_limit_rtx) > 1 | |
10223 | && REGNO (stack_limit_rtx) <= 31) | |
10224 | { | |
5b71a4e7 | 10225 | emit_insn (TARGET_32BIT |
9ebbca7d GK |
10226 | ? gen_addsi3 (tmp_reg, |
10227 | stack_limit_rtx, | |
10228 | GEN_INT (size)) | |
10229 | : gen_adddi3 (tmp_reg, | |
10230 | stack_limit_rtx, | |
10231 | GEN_INT (size))); | |
5b71a4e7 | 10232 | |
9ebbca7d GK |
10233 | emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg, |
10234 | const0_rtx)); | |
a157febd GK |
10235 | } |
10236 | else if (GET_CODE (stack_limit_rtx) == SYMBOL_REF | |
9ebbca7d | 10237 | && TARGET_32BIT |
f607bc57 | 10238 | && DEFAULT_ABI == ABI_V4) |
a157febd | 10239 | { |
9ebbca7d GK |
10240 | rtx toload = gen_rtx_CONST (VOIDmode, |
10241 | gen_rtx_PLUS (Pmode, | |
10242 | stack_limit_rtx, | |
10243 | GEN_INT (size))); | |
5b71a4e7 | 10244 | |
9ebbca7d GK |
10245 | emit_insn (gen_elf_high (tmp_reg, toload)); |
10246 | emit_insn (gen_elf_low (tmp_reg, tmp_reg, toload)); | |
10247 | emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg, | |
10248 | const0_rtx)); | |
a157febd GK |
10249 | } |
10250 | else | |
10251 | warning ("stack limit expression is not supported"); | |
10252 | } | |
10253 | ||
9ebbca7d GK |
10254 | if (copy_r12 || ! TARGET_UPDATE) |
10255 | emit_move_insn (gen_rtx_REG (Pmode, 12), stack_reg); | |
10256 | ||
38c1f2d7 MM |
10257 | if (TARGET_UPDATE) |
10258 | { | |
9ebbca7d | 10259 | if (size > 32767) |
38c1f2d7 | 10260 | { |
9ebbca7d GK |
10261 | /* Need a note here so that try_split doesn't get confused. */ |
10262 | if (get_last_insn() == NULL_RTX) | |
10263 | emit_note (0, NOTE_INSN_DELETED); | |
10264 | insn = emit_move_insn (tmp_reg, todec); | |
10265 | try_split (PATTERN (insn), insn, 0); | |
10266 | todec = tmp_reg; | |
38c1f2d7 | 10267 | } |
5b71a4e7 DE |
10268 | |
10269 | insn = emit_insn (TARGET_32BIT | |
10270 | ? gen_movsi_update (stack_reg, stack_reg, | |
10271 | todec, stack_reg) | |
10272 | : gen_movdi_update (stack_reg, stack_reg, | |
9ebbca7d | 10273 | todec, stack_reg)); |
38c1f2d7 MM |
10274 | } |
10275 | else | |
10276 | { | |
5b71a4e7 DE |
10277 | insn = emit_insn (TARGET_32BIT |
10278 | ? gen_addsi3 (stack_reg, stack_reg, todec) | |
10279 | : gen_adddi3 (stack_reg, stack_reg, todec)); | |
9ebbca7d GK |
10280 | emit_move_insn (gen_rtx_MEM (Pmode, stack_reg), |
10281 | gen_rtx_REG (Pmode, 12)); | |
10282 | } | |
5b71a4e7 | 10283 | |
9ebbca7d GK |
10284 | RTX_FRAME_RELATED_P (insn) = 1; |
10285 | REG_NOTES (insn) = | |
10286 | gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, | |
10287 | gen_rtx_SET (VOIDmode, stack_reg, | |
10288 | gen_rtx_PLUS (Pmode, stack_reg, | |
10289 | GEN_INT (-size))), | |
10290 | REG_NOTES (insn)); | |
10291 | } | |
10292 | ||
a4f6c312 SS |
10293 | /* Add to 'insn' a note which is PATTERN (INSN) but with REG replaced |
10294 | with (plus:P (reg 1) VAL), and with REG2 replaced with RREG if REG2 | |
10295 | is not NULL. It would be nice if dwarf2out_frame_debug_expr could | |
10296 | deduce these equivalences by itself so it wasn't necessary to hold | |
10297 | its hand so much. */ | |
9ebbca7d GK |
10298 | |
10299 | static void | |
10300 | rs6000_frame_related (insn, reg, val, reg2, rreg) | |
10301 | rtx insn; | |
10302 | rtx reg; | |
10303 | HOST_WIDE_INT val; | |
10304 | rtx reg2; | |
10305 | rtx rreg; | |
10306 | { | |
10307 | rtx real, temp; | |
10308 | ||
e56c4463 JL |
10309 | /* copy_rtx will not make unique copies of registers, so we need to |
10310 | ensure we don't have unwanted sharing here. */ | |
10311 | if (reg == reg2) | |
10312 | reg = gen_raw_REG (GET_MODE (reg), REGNO (reg)); | |
10313 | ||
10314 | if (reg == rreg) | |
10315 | reg = gen_raw_REG (GET_MODE (reg), REGNO (reg)); | |
10316 | ||
9ebbca7d GK |
10317 | real = copy_rtx (PATTERN (insn)); |
10318 | ||
89e7058f AH |
10319 | if (reg2 != NULL_RTX) |
10320 | real = replace_rtx (real, reg2, rreg); | |
10321 | ||
9ebbca7d GK |
10322 | real = replace_rtx (real, reg, |
10323 | gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode, | |
10324 | STACK_POINTER_REGNUM), | |
10325 | GEN_INT (val))); | |
10326 | ||
10327 | /* We expect that 'real' is either a SET or a PARALLEL containing | |
10328 | SETs (and possibly other stuff). In a PARALLEL, all the SETs | |
10329 | are important so they all have to be marked RTX_FRAME_RELATED_P. */ | |
10330 | ||
10331 | if (GET_CODE (real) == SET) | |
10332 | { | |
10333 | rtx set = real; | |
10334 | ||
10335 | temp = simplify_rtx (SET_SRC (set)); | |
10336 | if (temp) | |
10337 | SET_SRC (set) = temp; | |
10338 | temp = simplify_rtx (SET_DEST (set)); | |
10339 | if (temp) | |
10340 | SET_DEST (set) = temp; | |
10341 | if (GET_CODE (SET_DEST (set)) == MEM) | |
38c1f2d7 | 10342 | { |
9ebbca7d GK |
10343 | temp = simplify_rtx (XEXP (SET_DEST (set), 0)); |
10344 | if (temp) | |
10345 | XEXP (SET_DEST (set), 0) = temp; | |
38c1f2d7 | 10346 | } |
38c1f2d7 | 10347 | } |
9ebbca7d GK |
10348 | else if (GET_CODE (real) == PARALLEL) |
10349 | { | |
10350 | int i; | |
10351 | for (i = 0; i < XVECLEN (real, 0); i++) | |
10352 | if (GET_CODE (XVECEXP (real, 0, i)) == SET) | |
10353 | { | |
10354 | rtx set = XVECEXP (real, 0, i); | |
10355 | ||
10356 | temp = simplify_rtx (SET_SRC (set)); | |
10357 | if (temp) | |
10358 | SET_SRC (set) = temp; | |
10359 | temp = simplify_rtx (SET_DEST (set)); | |
10360 | if (temp) | |
10361 | SET_DEST (set) = temp; | |
10362 | if (GET_CODE (SET_DEST (set)) == MEM) | |
10363 | { | |
10364 | temp = simplify_rtx (XEXP (SET_DEST (set), 0)); | |
10365 | if (temp) | |
10366 | XEXP (SET_DEST (set), 0) = temp; | |
10367 | } | |
10368 | RTX_FRAME_RELATED_P (set) = 1; | |
10369 | } | |
10370 | } | |
10371 | else | |
a4f6c312 | 10372 | abort (); |
c19de7aa AH |
10373 | |
10374 | if (TARGET_SPE) | |
10375 | real = spe_synthesize_frame_save (real); | |
10376 | ||
9ebbca7d GK |
10377 | RTX_FRAME_RELATED_P (insn) = 1; |
10378 | REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, | |
10379 | real, | |
10380 | REG_NOTES (insn)); | |
38c1f2d7 MM |
10381 | } |
10382 | ||
c19de7aa AH |
10383 | /* Given an SPE frame note, return a PARALLEL of SETs with the |
10384 | original note, plus a synthetic register save. */ | |
10385 | ||
10386 | static rtx | |
10387 | spe_synthesize_frame_save (real) | |
10388 | rtx real; | |
10389 | { | |
10390 | rtx synth, offset, reg, real2; | |
10391 | ||
10392 | if (GET_CODE (real) != SET | |
10393 | || GET_MODE (SET_SRC (real)) != V2SImode) | |
10394 | return real; | |
10395 | ||
10396 | /* For the SPE, registers saved in 64-bits, get a PARALLEL for their | |
10397 | frame related note. The parallel contains a set of the register | |
41f3a930 | 10398 | being saved, and another set to a synthetic register (n+1200). |
c19de7aa AH |
10399 | This is so we can differentiate between 64-bit and 32-bit saves. |
10400 | Words cannot describe this nastiness. */ | |
10401 | ||
10402 | if (GET_CODE (SET_DEST (real)) != MEM | |
10403 | || GET_CODE (XEXP (SET_DEST (real), 0)) != PLUS | |
10404 | || GET_CODE (SET_SRC (real)) != REG) | |
10405 | abort (); | |
10406 | ||
10407 | /* Transform: | |
10408 | (set (mem (plus (reg x) (const y))) | |
10409 | (reg z)) | |
10410 | into: | |
10411 | (set (mem (plus (reg x) (const y+4))) | |
41f3a930 | 10412 | (reg z+1200)) |
c19de7aa AH |
10413 | */ |
10414 | ||
10415 | real2 = copy_rtx (real); | |
10416 | PUT_MODE (SET_DEST (real2), SImode); | |
10417 | reg = SET_SRC (real2); | |
10418 | real2 = replace_rtx (real2, reg, gen_rtx_REG (SImode, REGNO (reg))); | |
10419 | synth = copy_rtx (real2); | |
10420 | ||
10421 | if (BYTES_BIG_ENDIAN) | |
10422 | { | |
10423 | offset = XEXP (XEXP (SET_DEST (real2), 0), 1); | |
10424 | real2 = replace_rtx (real2, offset, GEN_INT (INTVAL (offset) + 4)); | |
10425 | } | |
10426 | ||
10427 | reg = SET_SRC (synth); | |
41f3a930 | 10428 | |
c19de7aa | 10429 | synth = replace_rtx (synth, reg, |
41f3a930 | 10430 | gen_rtx_REG (SImode, REGNO (reg) + 1200)); |
c19de7aa AH |
10431 | |
10432 | offset = XEXP (XEXP (SET_DEST (synth), 0), 1); | |
10433 | synth = replace_rtx (synth, offset, | |
10434 | GEN_INT (INTVAL (offset) | |
10435 | + (BYTES_BIG_ENDIAN ? 0 : 4))); | |
10436 | ||
10437 | RTX_FRAME_RELATED_P (synth) = 1; | |
10438 | RTX_FRAME_RELATED_P (real2) = 1; | |
10439 | if (BYTES_BIG_ENDIAN) | |
10440 | real = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, synth, real2)); | |
10441 | else | |
10442 | real = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, real2, synth)); | |
10443 | ||
10444 | return real; | |
10445 | } | |
10446 | ||
00b960c7 AH |
10447 | /* Returns an insn that has a vrsave set operation with the |
10448 | appropriate CLOBBERs. */ | |
10449 | ||
10450 | static rtx | |
9aa86737 | 10451 | generate_set_vrsave (reg, info, epiloguep) |
00b960c7 AH |
10452 | rtx reg; |
10453 | rs6000_stack_t *info; | |
9aa86737 | 10454 | int epiloguep; |
00b960c7 AH |
10455 | { |
10456 | int nclobs, i; | |
10457 | rtx insn, clobs[TOTAL_ALTIVEC_REGS + 1]; | |
a004eb82 | 10458 | rtx vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO); |
00b960c7 | 10459 | |
a004eb82 AH |
10460 | clobs[0] |
10461 | = gen_rtx_SET (VOIDmode, | |
10462 | vrsave, | |
10463 | gen_rtx_UNSPEC_VOLATILE (SImode, | |
10464 | gen_rtvec (2, reg, vrsave), | |
10465 | 30)); | |
00b960c7 AH |
10466 | |
10467 | nclobs = 1; | |
10468 | ||
9aa86737 AH |
10469 | /* We need to clobber the registers in the mask so the scheduler |
10470 | does not move sets to VRSAVE before sets of AltiVec registers. | |
10471 | ||
10472 | However, if the function receives nonlocal gotos, reload will set | |
10473 | all call saved registers live. We will end up with: | |
10474 | ||
10475 | (set (reg 999) (mem)) | |
10476 | (parallel [ (set (reg vrsave) (unspec blah)) | |
10477 | (clobber (reg 999))]) | |
10478 | ||
10479 | The clobber will cause the store into reg 999 to be dead, and | |
10480 | flow will attempt to delete an epilogue insn. In this case, we | |
10481 | need an unspec use/set of the register. */ | |
00b960c7 AH |
10482 | |
10483 | for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i) | |
10484 | if (info->vrsave_mask != 0 && ALTIVEC_REG_BIT (i) != 0) | |
9aa86737 AH |
10485 | { |
10486 | if (!epiloguep || call_used_regs [i]) | |
10487 | clobs[nclobs++] = gen_rtx_CLOBBER (VOIDmode, | |
10488 | gen_rtx_REG (V4SImode, i)); | |
10489 | else | |
10490 | { | |
10491 | rtx reg = gen_rtx_REG (V4SImode, i); | |
9aa86737 AH |
10492 | |
10493 | clobs[nclobs++] | |
a004eb82 AH |
10494 | = gen_rtx_SET (VOIDmode, |
10495 | reg, | |
10496 | gen_rtx_UNSPEC (V4SImode, | |
10497 | gen_rtvec (1, reg), 27)); | |
9aa86737 AH |
10498 | } |
10499 | } | |
00b960c7 AH |
10500 | |
10501 | insn = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (nclobs)); | |
10502 | ||
10503 | for (i = 0; i < nclobs; ++i) | |
10504 | XVECEXP (insn, 0, i) = clobs[i]; | |
10505 | ||
10506 | return insn; | |
10507 | } | |
10508 | ||
89e7058f AH |
10509 | /* Save a register into the frame, and emit RTX_FRAME_RELATED_P notes. |
10510 | Save REGNO into [FRAME_REG + OFFSET] in mode MODE. */ | |
10511 | ||
10512 | static void | |
10513 | emit_frame_save (frame_reg, frame_ptr, mode, regno, offset, total_size) | |
10514 | rtx frame_reg; | |
10515 | rtx frame_ptr; | |
10516 | enum machine_mode mode; | |
10517 | unsigned int regno; | |
10518 | int offset; | |
10519 | int total_size; | |
10520 | { | |
10521 | rtx reg, offset_rtx, insn, mem, addr, int_rtx; | |
10522 | rtx replacea, replaceb; | |
10523 | ||
10524 | int_rtx = GEN_INT (offset); | |
10525 | ||
10526 | /* Some cases that need register indexed addressing. */ | |
10527 | if ((TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode)) | |
a3170dc6 AH |
10528 | || (TARGET_SPE_ABI |
10529 | && SPE_VECTOR_MODE (mode) | |
10530 | && !SPE_CONST_OFFSET_OK (offset))) | |
89e7058f AH |
10531 | { |
10532 | /* Whomever calls us must make sure r11 is available in the | |
10533 | flow path of instructions in the prologue. */ | |
10534 | offset_rtx = gen_rtx_REG (Pmode, 11); | |
10535 | emit_move_insn (offset_rtx, int_rtx); | |
10536 | ||
10537 | replacea = offset_rtx; | |
10538 | replaceb = int_rtx; | |
10539 | } | |
10540 | else | |
10541 | { | |
10542 | offset_rtx = int_rtx; | |
10543 | replacea = NULL_RTX; | |
10544 | replaceb = NULL_RTX; | |
10545 | } | |
10546 | ||
10547 | reg = gen_rtx_REG (mode, regno); | |
10548 | addr = gen_rtx_PLUS (Pmode, frame_reg, offset_rtx); | |
10549 | mem = gen_rtx_MEM (mode, addr); | |
10550 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
10551 | ||
10552 | insn = emit_move_insn (mem, reg); | |
10553 | ||
10554 | rs6000_frame_related (insn, frame_ptr, total_size, replacea, replaceb); | |
10555 | } | |
10556 | ||
a3170dc6 AH |
10557 | /* Emit an offset memory reference suitable for a frame store, while |
10558 | converting to a valid addressing mode. */ | |
10559 | ||
10560 | static rtx | |
10561 | gen_frame_mem_offset (mode, reg, offset) | |
10562 | enum machine_mode mode; | |
10563 | rtx reg; | |
10564 | int offset; | |
10565 | { | |
10566 | rtx int_rtx, offset_rtx; | |
10567 | ||
10568 | int_rtx = GEN_INT (offset); | |
10569 | ||
10570 | if (TARGET_SPE_ABI && SPE_VECTOR_MODE (mode)) | |
10571 | { | |
10572 | offset_rtx = gen_rtx_REG (Pmode, FIXED_SCRATCH); | |
10573 | emit_move_insn (offset_rtx, int_rtx); | |
10574 | } | |
10575 | else | |
10576 | offset_rtx = int_rtx; | |
10577 | ||
10578 | return gen_rtx_MEM (mode, gen_rtx_PLUS (Pmode, reg, offset_rtx)); | |
10579 | } | |
10580 | ||
9ebbca7d GK |
10581 | /* Emit function prologue as insns. */ |
10582 | ||
9878760c | 10583 | void |
83720594 | 10584 | rs6000_emit_prologue () |
9878760c | 10585 | { |
4697a36c | 10586 | rs6000_stack_t *info = rs6000_stack_info (); |
9ebbca7d GK |
10587 | enum machine_mode reg_mode = TARGET_POWERPC64 ? DImode : SImode; |
10588 | int reg_size = TARGET_POWERPC64 ? 8 : 4; | |
10589 | rtx sp_reg_rtx = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM); | |
10590 | rtx frame_ptr_rtx = gen_rtx_REG (Pmode, 12); | |
10591 | rtx frame_reg_rtx = sp_reg_rtx; | |
10592 | rtx cr_save_rtx = NULL; | |
10593 | rtx insn; | |
10594 | int saving_FPRs_inline; | |
10595 | int using_store_multiple; | |
10596 | HOST_WIDE_INT sp_offset = 0; | |
10597 | ||
c19de7aa | 10598 | if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0) |
a3170dc6 AH |
10599 | { |
10600 | reg_mode = V2SImode; | |
10601 | reg_size = 8; | |
10602 | } | |
10603 | ||
9ebbca7d | 10604 | using_store_multiple = (TARGET_MULTIPLE && ! TARGET_POWERPC64 |
c19de7aa AH |
10605 | && (!TARGET_SPE_ABI |
10606 | || info->spe_64bit_regs_used == 0) | |
9ebbca7d GK |
10607 | && info->first_gp_reg_save < 31); |
10608 | saving_FPRs_inline = (info->first_fp_reg_save == 64 | |
10609 | || FP_SAVE_INLINE (info->first_fp_reg_save)); | |
10610 | ||
10611 | /* For V.4, update stack before we do any saving and set back pointer. */ | |
f607bc57 | 10612 | if (info->push_p && DEFAULT_ABI == ABI_V4) |
9ebbca7d GK |
10613 | { |
10614 | if (info->total_size < 32767) | |
10615 | sp_offset = info->total_size; | |
10616 | else | |
10617 | frame_reg_rtx = frame_ptr_rtx; | |
10618 | rs6000_emit_allocate_stack (info->total_size, | |
10619 | (frame_reg_rtx != sp_reg_rtx | |
10620 | && (info->cr_save_p | |
10621 | || info->lr_save_p | |
10622 | || info->first_fp_reg_save < 64 | |
10623 | || info->first_gp_reg_save < 32 | |
10624 | ))); | |
10625 | if (frame_reg_rtx != sp_reg_rtx) | |
10626 | rs6000_emit_stack_tie (); | |
10627 | } | |
10628 | ||
9aa86737 AH |
10629 | /* Save AltiVec registers if needed. */ |
10630 | if (TARGET_ALTIVEC_ABI && info->altivec_size != 0) | |
10631 | { | |
10632 | int i; | |
10633 | ||
10634 | /* There should be a non inline version of this, for when we | |
10635 | are saving lots of vector registers. */ | |
10636 | for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i) | |
10637 | if (info->vrsave_mask & ALTIVEC_REG_BIT (i)) | |
10638 | { | |
10639 | rtx areg, savereg, mem; | |
10640 | int offset; | |
10641 | ||
10642 | offset = info->altivec_save_offset + sp_offset | |
10643 | + 16 * (i - info->first_altivec_reg_save); | |
10644 | ||
10645 | savereg = gen_rtx_REG (V4SImode, i); | |
10646 | ||
10647 | areg = gen_rtx_REG (Pmode, 0); | |
10648 | emit_move_insn (areg, GEN_INT (offset)); | |
10649 | ||
10650 | /* AltiVec addressing mode is [reg+reg]. */ | |
10651 | mem = gen_rtx_MEM (V4SImode, | |
10652 | gen_rtx_PLUS (Pmode, frame_reg_rtx, areg)); | |
10653 | ||
10654 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
10655 | ||
10656 | insn = emit_move_insn (mem, savereg); | |
10657 | ||
5c242421 SB |
10658 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, |
10659 | areg, GEN_INT (offset)); | |
9aa86737 AH |
10660 | } |
10661 | } | |
10662 | ||
10663 | /* VRSAVE is a bit vector representing which AltiVec registers | |
10664 | are used. The OS uses this to determine which vector | |
10665 | registers to save on a context switch. We need to save | |
10666 | VRSAVE on the stack frame, add whatever AltiVec registers we | |
10667 | used in this function, and do the corresponding magic in the | |
10668 | epilogue. */ | |
10669 | ||
10670 | if (TARGET_ALTIVEC && info->vrsave_mask != 0) | |
10671 | { | |
a004eb82 | 10672 | rtx reg, mem, vrsave; |
9aa86737 AH |
10673 | int offset; |
10674 | ||
10675 | /* Get VRSAVE onto a GPR. */ | |
10676 | reg = gen_rtx_REG (SImode, 12); | |
a004eb82 | 10677 | vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO); |
b188f760 AH |
10678 | if (TARGET_MACHO) |
10679 | emit_insn (gen_get_vrsave_internal (reg)); | |
10680 | else | |
10681 | emit_insn (gen_rtx_SET (VOIDmode, reg, vrsave)); | |
9aa86737 AH |
10682 | |
10683 | /* Save VRSAVE. */ | |
10684 | offset = info->vrsave_save_offset + sp_offset; | |
10685 | mem | |
10686 | = gen_rtx_MEM (SImode, | |
10687 | gen_rtx_PLUS (Pmode, frame_reg_rtx, GEN_INT (offset))); | |
10688 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
10689 | insn = emit_move_insn (mem, reg); | |
10690 | ||
10691 | /* Include the registers in the mask. */ | |
10692 | emit_insn (gen_iorsi3 (reg, reg, GEN_INT ((int) info->vrsave_mask))); | |
10693 | ||
10694 | insn = emit_insn (generate_set_vrsave (reg, info, 0)); | |
10695 | } | |
10696 | ||
9ebbca7d GK |
10697 | /* If we use the link register, get it into r0. */ |
10698 | if (info->lr_save_p) | |
71f123ca | 10699 | emit_move_insn (gen_rtx_REG (Pmode, 0), |
9ebbca7d GK |
10700 | gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)); |
10701 | ||
10702 | /* If we need to save CR, put it into r12. */ | |
10703 | if (info->cr_save_p && frame_reg_rtx != frame_ptr_rtx) | |
10704 | { | |
10705 | cr_save_rtx = gen_rtx_REG (SImode, 12); | |
10706 | emit_insn (gen_movesi_from_cr (cr_save_rtx)); | |
10707 | } | |
10708 | ||
a4f6c312 SS |
10709 | /* Do any required saving of fpr's. If only one or two to save, do |
10710 | it ourselves. Otherwise, call function. */ | |
9ebbca7d GK |
10711 | if (saving_FPRs_inline) |
10712 | { | |
10713 | int i; | |
10714 | for (i = 0; i < 64 - info->first_fp_reg_save; i++) | |
10715 | if ((regs_ever_live[info->first_fp_reg_save+i] | |
10716 | && ! call_used_regs[info->first_fp_reg_save+i])) | |
89e7058f AH |
10717 | emit_frame_save (frame_reg_rtx, frame_ptr_rtx, DFmode, |
10718 | info->first_fp_reg_save + i, | |
10719 | info->fp_save_offset + sp_offset + 8 * i, | |
10720 | info->total_size); | |
9ebbca7d GK |
10721 | } |
10722 | else if (info->first_fp_reg_save != 64) | |
10723 | { | |
10724 | int i; | |
10725 | char rname[30]; | |
520a57c8 | 10726 | const char *alloc_rname; |
9ebbca7d GK |
10727 | rtvec p; |
10728 | p = rtvec_alloc (2 + 64 - info->first_fp_reg_save); | |
10729 | ||
10730 | RTVEC_ELT (p, 0) = gen_rtx_CLOBBER (VOIDmode, | |
10731 | gen_rtx_REG (Pmode, | |
10732 | LINK_REGISTER_REGNUM)); | |
10733 | sprintf (rname, "%s%d%s", SAVE_FP_PREFIX, | |
10734 | info->first_fp_reg_save - 32, SAVE_FP_SUFFIX); | |
a8a05998 | 10735 | alloc_rname = ggc_strdup (rname); |
9ebbca7d GK |
10736 | RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode, |
10737 | gen_rtx_SYMBOL_REF (Pmode, | |
10738 | alloc_rname)); | |
10739 | for (i = 0; i < 64 - info->first_fp_reg_save; i++) | |
10740 | { | |
10741 | rtx addr, reg, mem; | |
10742 | reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i); | |
10743 | addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
10744 | GEN_INT (info->fp_save_offset | |
10745 | + sp_offset + 8*i)); | |
10746 | mem = gen_rtx_MEM (DFmode, addr); | |
ba4828e0 | 10747 | set_mem_alias_set (mem, rs6000_sr_alias_set); |
9ebbca7d GK |
10748 | |
10749 | RTVEC_ELT (p, i + 2) = gen_rtx_SET (VOIDmode, mem, reg); | |
10750 | } | |
10751 | insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p)); | |
10752 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, | |
10753 | NULL_RTX, NULL_RTX); | |
10754 | } | |
b6c9286a | 10755 | |
9ebbca7d GK |
10756 | /* Save GPRs. This is done as a PARALLEL if we are using |
10757 | the store-multiple instructions. */ | |
10758 | if (using_store_multiple) | |
b6c9286a | 10759 | { |
308c142a | 10760 | rtvec p; |
9ebbca7d GK |
10761 | int i; |
10762 | p = rtvec_alloc (32 - info->first_gp_reg_save); | |
9ebbca7d GK |
10763 | for (i = 0; i < 32 - info->first_gp_reg_save; i++) |
10764 | { | |
10765 | rtx addr, reg, mem; | |
10766 | reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i); | |
10767 | addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
10768 | GEN_INT (info->gp_save_offset | |
10769 | + sp_offset | |
10770 | + reg_size * i)); | |
10771 | mem = gen_rtx_MEM (reg_mode, addr); | |
ba4828e0 | 10772 | set_mem_alias_set (mem, rs6000_sr_alias_set); |
9ebbca7d GK |
10773 | |
10774 | RTVEC_ELT (p, i) = gen_rtx_SET (VOIDmode, mem, reg); | |
10775 | } | |
10776 | insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p)); | |
10777 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, | |
10778 | NULL_RTX, NULL_RTX); | |
b6c9286a MM |
10779 | } |
10780 | else | |
10781 | { | |
9ebbca7d GK |
10782 | int i; |
10783 | for (i = 0; i < 32 - info->first_gp_reg_save; i++) | |
10784 | if ((regs_ever_live[info->first_gp_reg_save+i] | |
10785 | && ! call_used_regs[info->first_gp_reg_save+i]) | |
1db02437 | 10786 | || (i+info->first_gp_reg_save == RS6000_PIC_OFFSET_TABLE_REGNUM |
14f00213 | 10787 | && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0) |
f607bc57 | 10788 | || (DEFAULT_ABI == ABI_DARWIN && flag_pic)))) |
a3170dc6 AH |
10789 | { |
10790 | rtx addr, reg, mem; | |
10791 | reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i); | |
10792 | ||
c19de7aa | 10793 | if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0) |
a3170dc6 AH |
10794 | { |
10795 | int offset = info->spe_gp_save_offset + sp_offset + 8 * i; | |
10796 | rtx b; | |
10797 | ||
10798 | if (!SPE_CONST_OFFSET_OK (offset)) | |
10799 | { | |
10800 | b = gen_rtx_REG (Pmode, FIXED_SCRATCH); | |
10801 | emit_move_insn (b, GEN_INT (offset)); | |
10802 | } | |
10803 | else | |
10804 | b = GEN_INT (offset); | |
10805 | ||
10806 | addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, b); | |
10807 | mem = gen_rtx_MEM (V2SImode, addr); | |
10808 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
10809 | insn = emit_move_insn (mem, reg); | |
10810 | ||
10811 | if (GET_CODE (b) == CONST_INT) | |
10812 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, | |
10813 | NULL_RTX, NULL_RTX); | |
10814 | else | |
10815 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, | |
10816 | b, GEN_INT (offset)); | |
10817 | } | |
10818 | else | |
10819 | { | |
10820 | addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
10821 | GEN_INT (info->gp_save_offset | |
10822 | + sp_offset | |
10823 | + reg_size * i)); | |
10824 | mem = gen_rtx_MEM (reg_mode, addr); | |
10825 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
10826 | ||
10827 | insn = emit_move_insn (mem, reg); | |
10828 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, | |
10829 | NULL_RTX, NULL_RTX); | |
10830 | } | |
10831 | } | |
9ebbca7d GK |
10832 | } |
10833 | ||
83720594 RH |
10834 | /* ??? There's no need to emit actual instructions here, but it's the |
10835 | easiest way to get the frame unwind information emitted. */ | |
10836 | if (current_function_calls_eh_return) | |
10837 | { | |
78e1b90d DE |
10838 | unsigned int i, regno; |
10839 | ||
83720594 RH |
10840 | for (i = 0; ; ++i) |
10841 | { | |
83720594 RH |
10842 | regno = EH_RETURN_DATA_REGNO (i); |
10843 | if (regno == INVALID_REGNUM) | |
10844 | break; | |
10845 | ||
89e7058f AH |
10846 | emit_frame_save (frame_reg_rtx, frame_ptr_rtx, reg_mode, regno, |
10847 | info->ehrd_offset + sp_offset | |
10848 | + reg_size * (int) i, | |
10849 | info->total_size); | |
83720594 RH |
10850 | } |
10851 | } | |
10852 | ||
9ebbca7d GK |
10853 | /* Save lr if we used it. */ |
10854 | if (info->lr_save_p) | |
10855 | { | |
10856 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
10857 | GEN_INT (info->lr_save_offset + sp_offset)); | |
10858 | rtx reg = gen_rtx_REG (Pmode, 0); | |
10859 | rtx mem = gen_rtx_MEM (Pmode, addr); | |
10860 | /* This should not be of rs6000_sr_alias_set, because of | |
10861 | __builtin_return_address. */ | |
10862 | ||
10863 | insn = emit_move_insn (mem, reg); | |
10864 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, | |
10865 | reg, gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)); | |
10866 | } | |
10867 | ||
10868 | /* Save CR if we use any that must be preserved. */ | |
10869 | if (info->cr_save_p) | |
10870 | { | |
10871 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
10872 | GEN_INT (info->cr_save_offset + sp_offset)); | |
10873 | rtx mem = gen_rtx_MEM (SImode, addr); | |
ba4828e0 RK |
10874 | |
10875 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
9ebbca7d GK |
10876 | |
10877 | /* If r12 was used to hold the original sp, copy cr into r0 now | |
10878 | that it's free. */ | |
10879 | if (REGNO (frame_reg_rtx) == 12) | |
10880 | { | |
10881 | cr_save_rtx = gen_rtx_REG (SImode, 0); | |
10882 | emit_insn (gen_movesi_from_cr (cr_save_rtx)); | |
10883 | } | |
10884 | insn = emit_move_insn (mem, cr_save_rtx); | |
10885 | ||
10886 | /* Now, there's no way that dwarf2out_frame_debug_expr is going | |
615158e2 JJ |
10887 | to understand '(unspec:SI [(reg:CC 68) ...] UNSPEC_MOVESI_FROM_CR)'. |
10888 | But that's OK. All we have to do is specify that _one_ condition | |
10889 | code register is saved in this stack slot. The thrower's epilogue | |
a1dc9455 FS |
10890 | will then restore all the call-saved registers. |
10891 | We use CR2_REGNO (70) to be compatible with gcc-2.95 on Linux. */ | |
9ebbca7d | 10892 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, |
a1dc9455 | 10893 | cr_save_rtx, gen_rtx_REG (SImode, CR2_REGNO)); |
9ebbca7d GK |
10894 | } |
10895 | ||
10896 | /* Update stack and set back pointer unless this is V.4, | |
10897 | for which it was done previously. */ | |
f607bc57 | 10898 | if (info->push_p && DEFAULT_ABI != ABI_V4) |
9ebbca7d GK |
10899 | rs6000_emit_allocate_stack (info->total_size, FALSE); |
10900 | ||
10901 | /* Set frame pointer, if needed. */ | |
10902 | if (frame_pointer_needed) | |
10903 | { | |
a3170dc6 | 10904 | insn = emit_move_insn (gen_rtx_REG (Pmode, FRAME_POINTER_REGNUM), |
9ebbca7d GK |
10905 | sp_reg_rtx); |
10906 | RTX_FRAME_RELATED_P (insn) = 1; | |
b6c9286a | 10907 | } |
9878760c | 10908 | |
1db02437 | 10909 | /* If we are using RS6000_PIC_OFFSET_TABLE_REGNUM, we need to set it up. */ |
9ebbca7d | 10910 | if ((TARGET_TOC && TARGET_MINIMAL_TOC && get_pool_size () != 0) |
f607bc57 | 10911 | || (DEFAULT_ABI == ABI_V4 && flag_pic == 1 |
1db02437 | 10912 | && regs_ever_live[RS6000_PIC_OFFSET_TABLE_REGNUM])) |
9ebbca7d GK |
10913 | { |
10914 | /* If emit_load_toc_table will use the link register, we need to save | |
10915 | it. We use R11 for this purpose because emit_load_toc_table | |
10916 | can use register 0. This allows us to use a plain 'blr' to return | |
10917 | from the procedure more often. */ | |
f1384257 AM |
10918 | int save_LR_around_toc_setup = (TARGET_ELF |
10919 | && DEFAULT_ABI != ABI_AIX | |
10920 | && flag_pic | |
d5fa86ba GK |
10921 | && ! info->lr_save_p |
10922 | && EXIT_BLOCK_PTR->pred != NULL); | |
9ebbca7d GK |
10923 | if (save_LR_around_toc_setup) |
10924 | emit_move_insn (gen_rtx_REG (Pmode, 11), | |
10925 | gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)); | |
10926 | ||
10927 | rs6000_emit_load_toc_table (TRUE); | |
10928 | ||
10929 | if (save_LR_around_toc_setup) | |
10930 | emit_move_insn (gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM), | |
10931 | gen_rtx_REG (Pmode, 11)); | |
10932 | } | |
ee890fe2 | 10933 | |
fcce224d | 10934 | #if TARGET_MACHO |
ee890fe2 SS |
10935 | if (DEFAULT_ABI == ABI_DARWIN |
10936 | && flag_pic && current_function_uses_pic_offset_table) | |
10937 | { | |
10938 | rtx dest = gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM); | |
f099d360 | 10939 | const char *picbase = machopic_function_base_name (); |
6788f5ca | 10940 | rtx src = gen_rtx_SYMBOL_REF (Pmode, picbase); |
ee890fe2 | 10941 | |
f51eee6a | 10942 | rs6000_maybe_dead (emit_insn (gen_load_macho_picbase (dest, src))); |
ee890fe2 SS |
10943 | |
10944 | rs6000_maybe_dead ( | |
1db02437 | 10945 | emit_move_insn (gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM), |
ee890fe2 SS |
10946 | gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM))); |
10947 | } | |
fcce224d | 10948 | #endif |
9ebbca7d GK |
10949 | } |
10950 | ||
9ebbca7d | 10951 | /* Write function prologue. */ |
a4f6c312 | 10952 | |
08c148a8 NB |
10953 | static void |
10954 | rs6000_output_function_prologue (file, size) | |
9ebbca7d | 10955 | FILE *file; |
08c148a8 | 10956 | HOST_WIDE_INT size ATTRIBUTE_UNUSED; |
9ebbca7d GK |
10957 | { |
10958 | rs6000_stack_t *info = rs6000_stack_info (); | |
10959 | ||
4697a36c MM |
10960 | if (TARGET_DEBUG_STACK) |
10961 | debug_stack_info (info); | |
9878760c | 10962 | |
a4f6c312 SS |
10963 | /* Write .extern for any function we will call to save and restore |
10964 | fp values. */ | |
10965 | if (info->first_fp_reg_save < 64 | |
10966 | && !FP_SAVE_INLINE (info->first_fp_reg_save)) | |
4d30c363 | 10967 | fprintf (file, "\t.extern %s%d%s\n\t.extern %s%d%s\n", |
4697a36c | 10968 | SAVE_FP_PREFIX, info->first_fp_reg_save - 32, SAVE_FP_SUFFIX, |
a4f6c312 SS |
10969 | RESTORE_FP_PREFIX, info->first_fp_reg_save - 32, |
10970 | RESTORE_FP_SUFFIX); | |
9878760c | 10971 | |
c764f757 RK |
10972 | /* Write .extern for AIX common mode routines, if needed. */ |
10973 | if (! TARGET_POWER && ! TARGET_POWERPC && ! common_mode_defined) | |
10974 | { | |
f6709c70 JW |
10975 | fputs ("\t.extern __mulh\n", file); |
10976 | fputs ("\t.extern __mull\n", file); | |
10977 | fputs ("\t.extern __divss\n", file); | |
10978 | fputs ("\t.extern __divus\n", file); | |
10979 | fputs ("\t.extern __quoss\n", file); | |
10980 | fputs ("\t.extern __quous\n", file); | |
c764f757 RK |
10981 | common_mode_defined = 1; |
10982 | } | |
9878760c | 10983 | |
9ebbca7d | 10984 | if (! HAVE_prologue) |
979721f8 | 10985 | { |
9ebbca7d | 10986 | start_sequence (); |
9dda4cc8 | 10987 | |
a4f6c312 SS |
10988 | /* A NOTE_INSN_DELETED is supposed to be at the start and end of |
10989 | the "toplevel" insn chain. */ | |
9ebbca7d GK |
10990 | emit_note (0, NOTE_INSN_DELETED); |
10991 | rs6000_emit_prologue (); | |
10992 | emit_note (0, NOTE_INSN_DELETED); | |
178c3eff DJ |
10993 | |
10994 | /* Expand INSN_ADDRESSES so final() doesn't crash. */ | |
10995 | { | |
10996 | rtx insn; | |
10997 | unsigned addr = 0; | |
10998 | for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn)) | |
10999 | { | |
11000 | INSN_ADDRESSES_NEW (insn, addr); | |
11001 | addr += 4; | |
11002 | } | |
11003 | } | |
9dda4cc8 | 11004 | |
9ebbca7d | 11005 | if (TARGET_DEBUG_STACK) |
a4f6c312 SS |
11006 | debug_rtx_list (get_insns (), 100); |
11007 | final (get_insns (), file, FALSE, FALSE); | |
9ebbca7d | 11008 | end_sequence (); |
979721f8 MM |
11009 | } |
11010 | ||
9ebbca7d GK |
11011 | rs6000_pic_labelno++; |
11012 | } | |
11013 | ||
11014 | /* Emit function epilogue as insns. | |
9878760c | 11015 | |
9ebbca7d GK |
11016 | At present, dwarf2out_frame_debug_expr doesn't understand |
11017 | register restores, so we don't bother setting RTX_FRAME_RELATED_P | |
11018 | anywhere in the epilogue. Most of the insns below would in any case | |
11019 | need special notes to explain where r11 is in relation to the stack. */ | |
9878760c | 11020 | |
9ebbca7d | 11021 | void |
83720594 | 11022 | rs6000_emit_epilogue (sibcall) |
9ebbca7d GK |
11023 | int sibcall; |
11024 | { | |
11025 | rs6000_stack_t *info; | |
11026 | int restoring_FPRs_inline; | |
11027 | int using_load_multiple; | |
11028 | int using_mfcr_multiple; | |
11029 | int use_backchain_to_restore_sp; | |
11030 | int sp_offset = 0; | |
11031 | rtx sp_reg_rtx = gen_rtx_REG (Pmode, 1); | |
11032 | rtx frame_reg_rtx = sp_reg_rtx; | |
11033 | enum machine_mode reg_mode = TARGET_POWERPC64 ? DImode : SImode; | |
11034 | int reg_size = TARGET_POWERPC64 ? 8 : 4; | |
11035 | int i; | |
11036 | ||
c19de7aa AH |
11037 | info = rs6000_stack_info (); |
11038 | ||
11039 | if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0) | |
a3170dc6 AH |
11040 | { |
11041 | reg_mode = V2SImode; | |
11042 | reg_size = 8; | |
11043 | } | |
11044 | ||
9ebbca7d | 11045 | using_load_multiple = (TARGET_MULTIPLE && ! TARGET_POWERPC64 |
c19de7aa AH |
11046 | && (!TARGET_SPE_ABI |
11047 | || info->spe_64bit_regs_used == 0) | |
9ebbca7d GK |
11048 | && info->first_gp_reg_save < 31); |
11049 | restoring_FPRs_inline = (sibcall | |
83720594 | 11050 | || current_function_calls_eh_return |
9ebbca7d GK |
11051 | || info->first_fp_reg_save == 64 |
11052 | || FP_SAVE_INLINE (info->first_fp_reg_save)); | |
11053 | use_backchain_to_restore_sp = (frame_pointer_needed | |
11054 | || current_function_calls_alloca | |
11055 | || info->total_size > 32767); | |
11056 | using_mfcr_multiple = (rs6000_cpu == PROCESSOR_PPC601 | |
11057 | || rs6000_cpu == PROCESSOR_PPC603 | |
11058 | || rs6000_cpu == PROCESSOR_PPC750 | |
11059 | || optimize_size); | |
11060 | ||
11061 | /* If we have a frame pointer, a call to alloca, or a large stack | |
11062 | frame, restore the old stack pointer using the backchain. Otherwise, | |
11063 | we know what size to update it with. */ | |
11064 | if (use_backchain_to_restore_sp) | |
bacbde18 | 11065 | { |
9ebbca7d GK |
11066 | /* Under V.4, don't reset the stack pointer until after we're done |
11067 | loading the saved registers. */ | |
f607bc57 | 11068 | if (DEFAULT_ABI == ABI_V4) |
9ebbca7d | 11069 | frame_reg_rtx = gen_rtx_REG (Pmode, 11); |
4697a36c | 11070 | |
9ebbca7d GK |
11071 | emit_move_insn (frame_reg_rtx, |
11072 | gen_rtx_MEM (Pmode, sp_reg_rtx)); | |
11073 | ||
bacbde18 | 11074 | } |
9ebbca7d | 11075 | else if (info->push_p) |
85638c0d | 11076 | { |
f607bc57 | 11077 | if (DEFAULT_ABI == ABI_V4) |
9ebbca7d GK |
11078 | sp_offset = info->total_size; |
11079 | else | |
11080 | { | |
11081 | emit_insn (TARGET_32BIT | |
11082 | ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx, | |
11083 | GEN_INT (info->total_size)) | |
11084 | : gen_adddi3 (sp_reg_rtx, sp_reg_rtx, | |
11085 | GEN_INT (info->total_size))); | |
11086 | } | |
85638c0d | 11087 | } |
9ebbca7d | 11088 | |
9aa86737 AH |
11089 | /* Restore AltiVec registers if needed. */ |
11090 | if (TARGET_ALTIVEC_ABI && info->altivec_size != 0) | |
11091 | { | |
11092 | int i; | |
11093 | ||
11094 | for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i) | |
11095 | if (info->vrsave_mask & ALTIVEC_REG_BIT (i)) | |
11096 | { | |
11097 | rtx addr, areg, mem; | |
11098 | ||
11099 | areg = gen_rtx_REG (Pmode, 0); | |
11100 | emit_move_insn | |
11101 | (areg, GEN_INT (info->altivec_save_offset | |
11102 | + sp_offset | |
11103 | + 16 * (i - info->first_altivec_reg_save))); | |
11104 | ||
11105 | /* AltiVec addressing mode is [reg+reg]. */ | |
11106 | addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, areg); | |
11107 | mem = gen_rtx_MEM (V4SImode, addr); | |
11108 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
11109 | ||
11110 | emit_move_insn (gen_rtx_REG (V4SImode, i), mem); | |
11111 | } | |
11112 | } | |
11113 | ||
11114 | /* Restore VRSAVE if needed. */ | |
11115 | if (TARGET_ALTIVEC_ABI && info->vrsave_mask != 0) | |
11116 | { | |
11117 | rtx addr, mem, reg; | |
11118 | ||
11119 | addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
11120 | GEN_INT (info->vrsave_save_offset + sp_offset)); | |
11121 | mem = gen_rtx_MEM (SImode, addr); | |
11122 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
11123 | reg = gen_rtx_REG (SImode, 12); | |
11124 | emit_move_insn (reg, mem); | |
11125 | ||
11126 | emit_insn (generate_set_vrsave (reg, info, 1)); | |
11127 | } | |
11128 | ||
9ebbca7d GK |
11129 | /* Get the old lr if we saved it. */ |
11130 | if (info->lr_save_p) | |
b6c9286a | 11131 | { |
a3170dc6 AH |
11132 | rtx mem = gen_frame_mem_offset (Pmode, frame_reg_rtx, |
11133 | info->lr_save_offset + sp_offset); | |
ba4828e0 RK |
11134 | |
11135 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
b6c9286a | 11136 | |
9ebbca7d | 11137 | emit_move_insn (gen_rtx_REG (Pmode, 0), mem); |
b6c9286a | 11138 | } |
9ebbca7d GK |
11139 | |
11140 | /* Get the old cr if we saved it. */ | |
11141 | if (info->cr_save_p) | |
11142 | { | |
11143 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
11144 | GEN_INT (info->cr_save_offset + sp_offset)); | |
11145 | rtx mem = gen_rtx_MEM (SImode, addr); | |
ba4828e0 RK |
11146 | |
11147 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
b6c9286a | 11148 | |
9ebbca7d GK |
11149 | emit_move_insn (gen_rtx_REG (SImode, 12), mem); |
11150 | } | |
11151 | ||
11152 | /* Set LR here to try to overlap restores below. */ | |
4697a36c | 11153 | if (info->lr_save_p) |
9ebbca7d GK |
11154 | emit_move_insn (gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM), |
11155 | gen_rtx_REG (Pmode, 0)); | |
11156 | ||
83720594 RH |
11157 | /* Load exception handler data registers, if needed. */ |
11158 | if (current_function_calls_eh_return) | |
11159 | { | |
78e1b90d DE |
11160 | unsigned int i, regno; |
11161 | ||
83720594 RH |
11162 | for (i = 0; ; ++i) |
11163 | { | |
a3170dc6 | 11164 | rtx mem; |
83720594 RH |
11165 | |
11166 | regno = EH_RETURN_DATA_REGNO (i); | |
11167 | if (regno == INVALID_REGNUM) | |
11168 | break; | |
11169 | ||
a3170dc6 AH |
11170 | mem = gen_frame_mem_offset (reg_mode, frame_reg_rtx, |
11171 | info->ehrd_offset + sp_offset | |
11172 | + reg_size * (int) i); | |
ba4828e0 | 11173 | set_mem_alias_set (mem, rs6000_sr_alias_set); |
83720594 RH |
11174 | |
11175 | emit_move_insn (gen_rtx_REG (reg_mode, regno), mem); | |
11176 | } | |
11177 | } | |
9ebbca7d GK |
11178 | |
11179 | /* Restore GPRs. This is done as a PARALLEL if we are using | |
11180 | the load-multiple instructions. */ | |
11181 | if (using_load_multiple) | |
979721f8 | 11182 | { |
9ebbca7d GK |
11183 | rtvec p; |
11184 | p = rtvec_alloc (32 - info->first_gp_reg_save); | |
11185 | for (i = 0; i < 32 - info->first_gp_reg_save; i++) | |
979721f8 | 11186 | { |
9ebbca7d GK |
11187 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, |
11188 | GEN_INT (info->gp_save_offset | |
11189 | + sp_offset | |
11190 | + reg_size * i)); | |
11191 | rtx mem = gen_rtx_MEM (reg_mode, addr); | |
ba4828e0 RK |
11192 | |
11193 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
9ebbca7d GK |
11194 | |
11195 | RTVEC_ELT (p, i) = | |
11196 | gen_rtx_SET (VOIDmode, | |
11197 | gen_rtx_REG (reg_mode, info->first_gp_reg_save + i), | |
11198 | mem); | |
979721f8 | 11199 | } |
9ebbca7d | 11200 | emit_insn (gen_rtx_PARALLEL (VOIDmode, p)); |
979721f8 | 11201 | } |
9ebbca7d GK |
11202 | else |
11203 | for (i = 0; i < 32 - info->first_gp_reg_save; i++) | |
11204 | if ((regs_ever_live[info->first_gp_reg_save+i] | |
11205 | && ! call_used_regs[info->first_gp_reg_save+i]) | |
1db02437 | 11206 | || (i+info->first_gp_reg_save == RS6000_PIC_OFFSET_TABLE_REGNUM |
14f00213 | 11207 | && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0) |
f607bc57 | 11208 | || (DEFAULT_ABI == ABI_DARWIN && flag_pic)))) |
9ebbca7d GK |
11209 | { |
11210 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
11211 | GEN_INT (info->gp_save_offset | |
11212 | + sp_offset | |
11213 | + reg_size * i)); | |
11214 | rtx mem = gen_rtx_MEM (reg_mode, addr); | |
ba4828e0 | 11215 | |
a3170dc6 | 11216 | /* Restore 64-bit quantities for SPE. */ |
c19de7aa | 11217 | if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0) |
a3170dc6 AH |
11218 | { |
11219 | int offset = info->spe_gp_save_offset + sp_offset + 8 * i; | |
11220 | rtx b; | |
11221 | ||
11222 | if (!SPE_CONST_OFFSET_OK (offset)) | |
11223 | { | |
11224 | b = gen_rtx_REG (Pmode, FIXED_SCRATCH); | |
11225 | emit_move_insn (b, GEN_INT (offset)); | |
11226 | } | |
11227 | else | |
11228 | b = GEN_INT (offset); | |
11229 | ||
11230 | addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, b); | |
11231 | mem = gen_rtx_MEM (V2SImode, addr); | |
11232 | } | |
11233 | ||
ba4828e0 | 11234 | set_mem_alias_set (mem, rs6000_sr_alias_set); |
9ebbca7d GK |
11235 | |
11236 | emit_move_insn (gen_rtx_REG (reg_mode, | |
a3170dc6 | 11237 | info->first_gp_reg_save + i), mem); |
9ebbca7d | 11238 | } |
9878760c | 11239 | |
9ebbca7d GK |
11240 | /* Restore fpr's if we need to do it without calling a function. */ |
11241 | if (restoring_FPRs_inline) | |
11242 | for (i = 0; i < 64 - info->first_fp_reg_save; i++) | |
11243 | if ((regs_ever_live[info->first_fp_reg_save+i] | |
11244 | && ! call_used_regs[info->first_fp_reg_save+i])) | |
11245 | { | |
11246 | rtx addr, mem; | |
11247 | addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
11248 | GEN_INT (info->fp_save_offset | |
11249 | + sp_offset | |
a4f6c312 | 11250 | + 8 * i)); |
9ebbca7d | 11251 | mem = gen_rtx_MEM (DFmode, addr); |
ba4828e0 | 11252 | set_mem_alias_set (mem, rs6000_sr_alias_set); |
9ebbca7d GK |
11253 | |
11254 | emit_move_insn (gen_rtx_REG (DFmode, | |
11255 | info->first_fp_reg_save + i), | |
11256 | mem); | |
11257 | } | |
8d30c4ee | 11258 | |
9ebbca7d GK |
11259 | /* If we saved cr, restore it here. Just those that were used. */ |
11260 | if (info->cr_save_p) | |
979721f8 | 11261 | { |
9ebbca7d | 11262 | rtx r12_rtx = gen_rtx_REG (SImode, 12); |
e35b9579 | 11263 | int count = 0; |
9ebbca7d GK |
11264 | |
11265 | if (using_mfcr_multiple) | |
979721f8 | 11266 | { |
9ebbca7d GK |
11267 | for (i = 0; i < 8; i++) |
11268 | if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i]) | |
e35b9579 | 11269 | count++; |
9ebbca7d | 11270 | if (count == 0) |
e35b9579 GK |
11271 | abort (); |
11272 | } | |
11273 | ||
11274 | if (using_mfcr_multiple && count > 1) | |
11275 | { | |
11276 | rtvec p; | |
11277 | int ndx; | |
9ebbca7d | 11278 | |
e35b9579 | 11279 | p = rtvec_alloc (count); |
9ebbca7d | 11280 | |
e35b9579 | 11281 | ndx = 0; |
9ebbca7d GK |
11282 | for (i = 0; i < 8; i++) |
11283 | if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i]) | |
11284 | { | |
11285 | rtvec r = rtvec_alloc (2); | |
11286 | RTVEC_ELT (r, 0) = r12_rtx; | |
11287 | RTVEC_ELT (r, 1) = GEN_INT (1 << (7-i)); | |
e35b9579 | 11288 | RTVEC_ELT (p, ndx) = |
9ebbca7d | 11289 | gen_rtx_SET (VOIDmode, gen_rtx_REG (CCmode, CR0_REGNO+i), |
615158e2 | 11290 | gen_rtx_UNSPEC (CCmode, r, UNSPEC_MOVESI_TO_CR)); |
e35b9579 | 11291 | ndx++; |
9ebbca7d GK |
11292 | } |
11293 | emit_insn (gen_rtx_PARALLEL (VOIDmode, p)); | |
e35b9579 GK |
11294 | if (ndx != count) |
11295 | abort (); | |
979721f8 MM |
11296 | } |
11297 | else | |
9ebbca7d GK |
11298 | for (i = 0; i < 8; i++) |
11299 | if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i]) | |
979721f8 | 11300 | { |
9ebbca7d GK |
11301 | emit_insn (gen_movsi_to_cr_one (gen_rtx_REG (CCmode, |
11302 | CR0_REGNO+i), | |
11303 | r12_rtx)); | |
979721f8 | 11304 | } |
979721f8 MM |
11305 | } |
11306 | ||
9ebbca7d GK |
11307 | /* If this is V.4, unwind the stack pointer after all of the loads |
11308 | have been done. We need to emit a block here so that sched | |
11309 | doesn't decide to move the sp change before the register restores | |
11310 | (which may not have any obvious dependency on the stack). This | |
11311 | doesn't hurt performance, because there is no scheduling that can | |
11312 | be done after this point. */ | |
f607bc57 | 11313 | if (DEFAULT_ABI == ABI_V4) |
b6c9286a | 11314 | { |
9ebbca7d GK |
11315 | if (frame_reg_rtx != sp_reg_rtx) |
11316 | rs6000_emit_stack_tie (); | |
b6c9286a | 11317 | |
9ebbca7d | 11318 | if (use_backchain_to_restore_sp) |
b6c9286a | 11319 | { |
9ebbca7d | 11320 | emit_move_insn (sp_reg_rtx, frame_reg_rtx); |
b6c9286a | 11321 | } |
9ebbca7d | 11322 | else if (sp_offset != 0) |
13f1623b | 11323 | { |
5b71a4e7 | 11324 | emit_insn (TARGET_32BIT |
9ebbca7d GK |
11325 | ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx, |
11326 | GEN_INT (sp_offset)) | |
11327 | : gen_adddi3 (sp_reg_rtx, sp_reg_rtx, | |
11328 | GEN_INT (sp_offset))); | |
13f1623b | 11329 | } |
9ebbca7d | 11330 | } |
b6c9286a | 11331 | |
83720594 RH |
11332 | if (current_function_calls_eh_return) |
11333 | { | |
11334 | rtx sa = EH_RETURN_STACKADJ_RTX; | |
5b71a4e7 | 11335 | emit_insn (TARGET_32BIT |
83720594 RH |
11336 | ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx, sa) |
11337 | : gen_adddi3 (sp_reg_rtx, sp_reg_rtx, sa)); | |
11338 | } | |
11339 | ||
9ebbca7d GK |
11340 | if (!sibcall) |
11341 | { | |
11342 | rtvec p; | |
11343 | if (! restoring_FPRs_inline) | |
11344 | p = rtvec_alloc (3 + 64 - info->first_fp_reg_save); | |
11345 | else | |
11346 | p = rtvec_alloc (2); | |
b6c9286a | 11347 | |
e35b9579 GK |
11348 | RTVEC_ELT (p, 0) = gen_rtx_RETURN (VOIDmode); |
11349 | RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode, | |
9ebbca7d GK |
11350 | gen_rtx_REG (Pmode, |
11351 | LINK_REGISTER_REGNUM)); | |
9ebbca7d GK |
11352 | |
11353 | /* If we have to restore more than two FP registers, branch to the | |
11354 | restore function. It will return to our caller. */ | |
11355 | if (! restoring_FPRs_inline) | |
11356 | { | |
11357 | int i; | |
11358 | char rname[30]; | |
520a57c8 | 11359 | const char *alloc_rname; |
979721f8 | 11360 | |
9ebbca7d GK |
11361 | sprintf (rname, "%s%d%s", RESTORE_FP_PREFIX, |
11362 | info->first_fp_reg_save - 32, RESTORE_FP_SUFFIX); | |
a8a05998 | 11363 | alloc_rname = ggc_strdup (rname); |
9ebbca7d GK |
11364 | RTVEC_ELT (p, 2) = gen_rtx_USE (VOIDmode, |
11365 | gen_rtx_SYMBOL_REF (Pmode, | |
11366 | alloc_rname)); | |
b6c9286a | 11367 | |
9ebbca7d GK |
11368 | for (i = 0; i < 64 - info->first_fp_reg_save; i++) |
11369 | { | |
11370 | rtx addr, mem; | |
11371 | addr = gen_rtx_PLUS (Pmode, sp_reg_rtx, | |
11372 | GEN_INT (info->fp_save_offset + 8*i)); | |
11373 | mem = gen_rtx_MEM (DFmode, addr); | |
ba4828e0 | 11374 | set_mem_alias_set (mem, rs6000_sr_alias_set); |
9ebbca7d GK |
11375 | |
11376 | RTVEC_ELT (p, i+3) = | |
11377 | gen_rtx_SET (VOIDmode, | |
11378 | gen_rtx_REG (DFmode, info->first_fp_reg_save + i), | |
11379 | mem); | |
b6c9286a MM |
11380 | } |
11381 | } | |
9ebbca7d GK |
11382 | |
11383 | emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p)); | |
3daf36a4 | 11384 | } |
9878760c RK |
11385 | } |
11386 | ||
11387 | /* Write function epilogue. */ | |
11388 | ||
08c148a8 NB |
11389 | static void |
11390 | rs6000_output_function_epilogue (file, size) | |
9878760c | 11391 | FILE *file; |
08c148a8 | 11392 | HOST_WIDE_INT size ATTRIBUTE_UNUSED; |
9878760c | 11393 | { |
4697a36c | 11394 | rs6000_stack_t *info = rs6000_stack_info (); |
9878760c | 11395 | |
9ebbca7d | 11396 | if (! HAVE_epilogue) |
9878760c | 11397 | { |
9ebbca7d GK |
11398 | rtx insn = get_last_insn (); |
11399 | /* If the last insn was a BARRIER, we don't have to write anything except | |
11400 | the trace table. */ | |
11401 | if (GET_CODE (insn) == NOTE) | |
11402 | insn = prev_nonnote_insn (insn); | |
11403 | if (insn == 0 || GET_CODE (insn) != BARRIER) | |
4697a36c | 11404 | { |
9ebbca7d GK |
11405 | /* This is slightly ugly, but at least we don't have two |
11406 | copies of the epilogue-emitting code. */ | |
11407 | start_sequence (); | |
11408 | ||
11409 | /* A NOTE_INSN_DELETED is supposed to be at the start | |
11410 | and end of the "toplevel" insn chain. */ | |
11411 | emit_note (0, NOTE_INSN_DELETED); | |
11412 | rs6000_emit_epilogue (FALSE); | |
11413 | emit_note (0, NOTE_INSN_DELETED); | |
11414 | ||
178c3eff DJ |
11415 | /* Expand INSN_ADDRESSES so final() doesn't crash. */ |
11416 | { | |
11417 | rtx insn; | |
11418 | unsigned addr = 0; | |
11419 | for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn)) | |
11420 | { | |
11421 | INSN_ADDRESSES_NEW (insn, addr); | |
11422 | addr += 4; | |
11423 | } | |
11424 | } | |
11425 | ||
9ebbca7d | 11426 | if (TARGET_DEBUG_STACK) |
a4f6c312 SS |
11427 | debug_rtx_list (get_insns (), 100); |
11428 | final (get_insns (), file, FALSE, FALSE); | |
9ebbca7d | 11429 | end_sequence (); |
4697a36c | 11430 | } |
9878760c | 11431 | } |
b4ac57ab | 11432 | |
9b30bae2 | 11433 | /* Output a traceback table here. See /usr/include/sys/debug.h for info |
314fc5a9 ILT |
11434 | on its format. |
11435 | ||
11436 | We don't output a traceback table if -finhibit-size-directive was | |
11437 | used. The documentation for -finhibit-size-directive reads | |
11438 | ``don't output a @code{.size} assembler directive, or anything | |
11439 | else that would cause trouble if the function is split in the | |
11440 | middle, and the two halves are placed at locations far apart in | |
11441 | memory.'' The traceback table has this property, since it | |
11442 | includes the offset from the start of the function to the | |
4d30c363 MM |
11443 | traceback table itself. |
11444 | ||
11445 | System V.4 Powerpc's (and the embedded ABI derived from it) use a | |
b6c9286a | 11446 | different traceback table. */ |
57ac7be9 AM |
11447 | if (DEFAULT_ABI == ABI_AIX && ! flag_inhibit_size_directive |
11448 | && rs6000_traceback != traceback_none) | |
9b30bae2 | 11449 | { |
69c75916 | 11450 | const char *fname = NULL; |
3ac88239 | 11451 | const char *language_string = lang_hooks.name; |
6041bf2f | 11452 | int fixed_parms = 0, float_parms = 0, parm_info = 0; |
314fc5a9 | 11453 | int i; |
57ac7be9 AM |
11454 | int optional_tbtab; |
11455 | ||
11456 | if (rs6000_traceback == traceback_full) | |
11457 | optional_tbtab = 1; | |
11458 | else if (rs6000_traceback == traceback_part) | |
11459 | optional_tbtab = 0; | |
11460 | else | |
11461 | optional_tbtab = !optimize_size && !TARGET_ELF; | |
314fc5a9 | 11462 | |
69c75916 AM |
11463 | if (optional_tbtab) |
11464 | { | |
11465 | fname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0); | |
11466 | while (*fname == '.') /* V.4 encodes . in the name */ | |
11467 | fname++; | |
11468 | ||
11469 | /* Need label immediately before tbtab, so we can compute | |
11470 | its offset from the function start. */ | |
11471 | ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT"); | |
11472 | ASM_OUTPUT_LABEL (file, fname); | |
11473 | } | |
314fc5a9 ILT |
11474 | |
11475 | /* The .tbtab pseudo-op can only be used for the first eight | |
11476 | expressions, since it can't handle the possibly variable | |
11477 | length fields that follow. However, if you omit the optional | |
11478 | fields, the assembler outputs zeros for all optional fields | |
11479 | anyways, giving each variable length field is minimum length | |
11480 | (as defined in sys/debug.h). Thus we can not use the .tbtab | |
11481 | pseudo-op at all. */ | |
11482 | ||
11483 | /* An all-zero word flags the start of the tbtab, for debuggers | |
11484 | that have to find it by searching forward from the entry | |
11485 | point or from the current pc. */ | |
19d2d16f | 11486 | fputs ("\t.long 0\n", file); |
314fc5a9 ILT |
11487 | |
11488 | /* Tbtab format type. Use format type 0. */ | |
19d2d16f | 11489 | fputs ("\t.byte 0,", file); |
314fc5a9 ILT |
11490 | |
11491 | /* Language type. Unfortunately, there doesn't seem to be any | |
11492 | official way to get this info, so we use language_string. C | |
11493 | is 0. C++ is 9. No number defined for Obj-C, so use the | |
9517ead8 | 11494 | value for C for now. There is no official value for Java, |
6f573ff9 | 11495 | although IBM appears to be using 13. There is no official value |
f710504c | 11496 | for Chill, so we've chosen 44 pseudo-randomly. */ |
314fc5a9 | 11497 | if (! strcmp (language_string, "GNU C") |
e2c953b6 | 11498 | || ! strcmp (language_string, "GNU Objective-C")) |
314fc5a9 ILT |
11499 | i = 0; |
11500 | else if (! strcmp (language_string, "GNU F77")) | |
11501 | i = 1; | |
11502 | else if (! strcmp (language_string, "GNU Ada")) | |
11503 | i = 3; | |
8b83775b | 11504 | else if (! strcmp (language_string, "GNU Pascal")) |
314fc5a9 ILT |
11505 | i = 2; |
11506 | else if (! strcmp (language_string, "GNU C++")) | |
11507 | i = 9; | |
9517ead8 AG |
11508 | else if (! strcmp (language_string, "GNU Java")) |
11509 | i = 13; | |
6f573ff9 JL |
11510 | else if (! strcmp (language_string, "GNU CHILL")) |
11511 | i = 44; | |
314fc5a9 ILT |
11512 | else |
11513 | abort (); | |
11514 | fprintf (file, "%d,", i); | |
11515 | ||
11516 | /* 8 single bit fields: global linkage (not set for C extern linkage, | |
11517 | apparently a PL/I convention?), out-of-line epilogue/prologue, offset | |
11518 | from start of procedure stored in tbtab, internal function, function | |
11519 | has controlled storage, function has no toc, function uses fp, | |
11520 | function logs/aborts fp operations. */ | |
11521 | /* Assume that fp operations are used if any fp reg must be saved. */ | |
6041bf2f DE |
11522 | fprintf (file, "%d,", |
11523 | (optional_tbtab << 5) | ((info->first_fp_reg_save != 64) << 1)); | |
314fc5a9 ILT |
11524 | |
11525 | /* 6 bitfields: function is interrupt handler, name present in | |
11526 | proc table, function calls alloca, on condition directives | |
11527 | (controls stack walks, 3 bits), saves condition reg, saves | |
11528 | link reg. */ | |
11529 | /* The `function calls alloca' bit seems to be set whenever reg 31 is | |
11530 | set up as a frame pointer, even when there is no alloca call. */ | |
11531 | fprintf (file, "%d,", | |
6041bf2f DE |
11532 | ((optional_tbtab << 6) |
11533 | | ((optional_tbtab & frame_pointer_needed) << 5) | |
11534 | | (info->cr_save_p << 1) | |
11535 | | (info->lr_save_p))); | |
314fc5a9 | 11536 | |
6041bf2f | 11537 | /* 3 bitfields: saves backchain, fixup code, number of fpr saved |
314fc5a9 ILT |
11538 | (6 bits). */ |
11539 | fprintf (file, "%d,", | |
4697a36c | 11540 | (info->push_p << 7) | (64 - info->first_fp_reg_save)); |
314fc5a9 ILT |
11541 | |
11542 | /* 2 bitfields: spare bits (2 bits), number of gpr saved (6 bits). */ | |
11543 | fprintf (file, "%d,", (32 - first_reg_to_save ())); | |
11544 | ||
6041bf2f DE |
11545 | if (optional_tbtab) |
11546 | { | |
11547 | /* Compute the parameter info from the function decl argument | |
11548 | list. */ | |
11549 | tree decl; | |
11550 | int next_parm_info_bit = 31; | |
314fc5a9 | 11551 | |
6041bf2f DE |
11552 | for (decl = DECL_ARGUMENTS (current_function_decl); |
11553 | decl; decl = TREE_CHAIN (decl)) | |
11554 | { | |
11555 | rtx parameter = DECL_INCOMING_RTL (decl); | |
11556 | enum machine_mode mode = GET_MODE (parameter); | |
314fc5a9 | 11557 | |
6041bf2f DE |
11558 | if (GET_CODE (parameter) == REG) |
11559 | { | |
11560 | if (GET_MODE_CLASS (mode) == MODE_FLOAT) | |
11561 | { | |
11562 | int bits; | |
11563 | ||
11564 | float_parms++; | |
11565 | ||
11566 | if (mode == SFmode) | |
11567 | bits = 0x2; | |
fcce224d | 11568 | else if (mode == DFmode || mode == TFmode) |
6041bf2f DE |
11569 | bits = 0x3; |
11570 | else | |
11571 | abort (); | |
11572 | ||
11573 | /* If only one bit will fit, don't or in this entry. */ | |
11574 | if (next_parm_info_bit > 0) | |
11575 | parm_info |= (bits << (next_parm_info_bit - 1)); | |
11576 | next_parm_info_bit -= 2; | |
11577 | } | |
11578 | else | |
11579 | { | |
11580 | fixed_parms += ((GET_MODE_SIZE (mode) | |
11581 | + (UNITS_PER_WORD - 1)) | |
11582 | / UNITS_PER_WORD); | |
11583 | next_parm_info_bit -= 1; | |
11584 | } | |
11585 | } | |
11586 | } | |
11587 | } | |
314fc5a9 ILT |
11588 | |
11589 | /* Number of fixed point parameters. */ | |
11590 | /* This is actually the number of words of fixed point parameters; thus | |
11591 | an 8 byte struct counts as 2; and thus the maximum value is 8. */ | |
11592 | fprintf (file, "%d,", fixed_parms); | |
11593 | ||
11594 | /* 2 bitfields: number of floating point parameters (7 bits), parameters | |
11595 | all on stack. */ | |
11596 | /* This is actually the number of fp registers that hold parameters; | |
11597 | and thus the maximum value is 13. */ | |
11598 | /* Set parameters on stack bit if parameters are not in their original | |
11599 | registers, regardless of whether they are on the stack? Xlc | |
11600 | seems to set the bit when not optimizing. */ | |
11601 | fprintf (file, "%d\n", ((float_parms << 1) | (! optimize))); | |
11602 | ||
6041bf2f DE |
11603 | if (! optional_tbtab) |
11604 | return; | |
11605 | ||
314fc5a9 ILT |
11606 | /* Optional fields follow. Some are variable length. */ |
11607 | ||
11608 | /* Parameter types, left adjusted bit fields: 0 fixed, 10 single float, | |
11609 | 11 double float. */ | |
11610 | /* There is an entry for each parameter in a register, in the order that | |
11611 | they occur in the parameter list. Any intervening arguments on the | |
11612 | stack are ignored. If the list overflows a long (max possible length | |
11613 | 34 bits) then completely leave off all elements that don't fit. */ | |
11614 | /* Only emit this long if there was at least one parameter. */ | |
11615 | if (fixed_parms || float_parms) | |
11616 | fprintf (file, "\t.long %d\n", parm_info); | |
11617 | ||
11618 | /* Offset from start of code to tb table. */ | |
19d2d16f | 11619 | fputs ("\t.long ", file); |
314fc5a9 | 11620 | ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT"); |
54ee9799 DE |
11621 | #if TARGET_AIX |
11622 | RS6000_OUTPUT_BASENAME (file, fname); | |
11623 | #else | |
9ebbca7d | 11624 | assemble_name (file, fname); |
54ee9799 | 11625 | #endif |
19d2d16f | 11626 | fputs ("-.", file); |
54ee9799 DE |
11627 | #if TARGET_AIX |
11628 | RS6000_OUTPUT_BASENAME (file, fname); | |
11629 | #else | |
9ebbca7d | 11630 | assemble_name (file, fname); |
54ee9799 | 11631 | #endif |
19d2d16f | 11632 | putc ('\n', file); |
314fc5a9 ILT |
11633 | |
11634 | /* Interrupt handler mask. */ | |
11635 | /* Omit this long, since we never set the interrupt handler bit | |
11636 | above. */ | |
11637 | ||
11638 | /* Number of CTL (controlled storage) anchors. */ | |
11639 | /* Omit this long, since the has_ctl bit is never set above. */ | |
11640 | ||
11641 | /* Displacement into stack of each CTL anchor. */ | |
11642 | /* Omit this list of longs, because there are no CTL anchors. */ | |
11643 | ||
11644 | /* Length of function name. */ | |
69c75916 AM |
11645 | if (*fname == '*') |
11646 | ++fname; | |
296b8152 | 11647 | fprintf (file, "\t.short %d\n", (int) strlen (fname)); |
314fc5a9 ILT |
11648 | |
11649 | /* Function name. */ | |
11650 | assemble_string (fname, strlen (fname)); | |
11651 | ||
11652 | /* Register for alloca automatic storage; this is always reg 31. | |
11653 | Only emit this if the alloca bit was set above. */ | |
11654 | if (frame_pointer_needed) | |
19d2d16f | 11655 | fputs ("\t.byte 31\n", file); |
b1765bde DE |
11656 | |
11657 | fputs ("\t.align 2\n", file); | |
9b30bae2 | 11658 | } |
9878760c | 11659 | } |
17167fd8 | 11660 | \f |
a4f6c312 SS |
11661 | /* A C compound statement that outputs the assembler code for a thunk |
11662 | function, used to implement C++ virtual function calls with | |
11663 | multiple inheritance. The thunk acts as a wrapper around a virtual | |
11664 | function, adjusting the implicit object parameter before handing | |
11665 | control off to the real function. | |
11666 | ||
11667 | First, emit code to add the integer DELTA to the location that | |
11668 | contains the incoming first argument. Assume that this argument | |
11669 | contains a pointer, and is the one used to pass the `this' pointer | |
11670 | in C++. This is the incoming argument *before* the function | |
11671 | prologue, e.g. `%o0' on a sparc. The addition must preserve the | |
11672 | values of all other incoming arguments. | |
17167fd8 MM |
11673 | |
11674 | After the addition, emit code to jump to FUNCTION, which is a | |
a4f6c312 SS |
11675 | `FUNCTION_DECL'. This is a direct pure jump, not a call, and does |
11676 | not touch the return address. Hence returning from FUNCTION will | |
11677 | return to whoever called the current `thunk'. | |
17167fd8 | 11678 | |
a4f6c312 SS |
11679 | The effect must be as if FUNCTION had been called directly with the |
11680 | adjusted first argument. This macro is responsible for emitting | |
11681 | all of the code for a thunk function; output_function_prologue() | |
11682 | and output_function_epilogue() are not invoked. | |
17167fd8 | 11683 | |
a4f6c312 SS |
11684 | The THUNK_FNDECL is redundant. (DELTA and FUNCTION have already |
11685 | been extracted from it.) It might possibly be useful on some | |
11686 | targets, but probably not. | |
17167fd8 | 11687 | |
a4f6c312 SS |
11688 | If you do not define this macro, the target-independent code in the |
11689 | C++ frontend will generate a less efficient heavyweight thunk that | |
11690 | calls FUNCTION instead of jumping to it. The generic approach does | |
11691 | not support varargs. */ | |
17167fd8 | 11692 | |
3961e8fe RH |
11693 | static void |
11694 | rs6000_output_mi_thunk (file, thunk_fndecl, delta, vcall_offset, function) | |
17167fd8 | 11695 | FILE *file; |
d330fd93 | 11696 | tree thunk_fndecl ATTRIBUTE_UNUSED; |
eb0424da | 11697 | HOST_WIDE_INT delta; |
5b71a4e7 | 11698 | HOST_WIDE_INT vcall_offset; |
17167fd8 MM |
11699 | tree function; |
11700 | { | |
5b71a4e7 | 11701 | rtx this, insn, funexp; |
17167fd8 | 11702 | |
5b71a4e7 DE |
11703 | reload_completed = 1; |
11704 | no_new_pseudos = 1; | |
56a7189a | 11705 | |
5b71a4e7 DE |
11706 | /* Mark the end of the (empty) prologue. */ |
11707 | emit_note (NULL, NOTE_INSN_PROLOGUE_END); | |
17167fd8 | 11708 | |
5b71a4e7 DE |
11709 | /* Find the "this" pointer. If the function returns a structure, |
11710 | the structure return pointer is in r3. */ | |
11711 | if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)))) | |
11712 | this = gen_rtx_REG (Pmode, 4); | |
56a7189a | 11713 | else |
5b71a4e7 | 11714 | this = gen_rtx_REG (Pmode, 3); |
17167fd8 | 11715 | |
5b71a4e7 DE |
11716 | /* Apply the constant offset, if required. */ |
11717 | if (delta) | |
11718 | { | |
11719 | rtx delta_rtx = GEN_INT (delta); | |
11720 | emit_insn (TARGET_32BIT | |
11721 | ? gen_addsi3 (this, this, delta_rtx) | |
11722 | : gen_adddi3 (this, this, delta_rtx)); | |
17167fd8 MM |
11723 | } |
11724 | ||
5b71a4e7 DE |
11725 | /* Apply the offset from the vtable, if required. */ |
11726 | if (vcall_offset) | |
17167fd8 | 11727 | { |
5b71a4e7 DE |
11728 | rtx vcall_offset_rtx = GEN_INT (vcall_offset); |
11729 | rtx tmp = gen_rtx_REG (Pmode, 12); | |
17167fd8 | 11730 | |
5b71a4e7 DE |
11731 | emit_move_insn (tmp, gen_rtx_MEM (Pmode, this)); |
11732 | emit_insn (TARGET_32BIT | |
11733 | ? gen_addsi3 (tmp, tmp, vcall_offset_rtx) | |
11734 | : gen_adddi3 (tmp, tmp, vcall_offset_rtx)); | |
11735 | emit_move_insn (tmp, gen_rtx_MEM (Pmode, tmp)); | |
11736 | emit_insn (TARGET_32BIT | |
11737 | ? gen_addsi3 (this, this, tmp) | |
11738 | : gen_adddi3 (this, this, tmp)); | |
17167fd8 MM |
11739 | } |
11740 | ||
5b71a4e7 DE |
11741 | /* Generate a tail call to the target function. */ |
11742 | if (!TREE_USED (function)) | |
11743 | { | |
11744 | assemble_external (function); | |
11745 | TREE_USED (function) = 1; | |
11746 | } | |
11747 | funexp = XEXP (DECL_RTL (function), 0); | |
42820a49 | 11748 | |
5b71a4e7 DE |
11749 | SYMBOL_REF_FLAG (funexp) = 0; |
11750 | if (current_file_function_operand (funexp, VOIDmode) | |
a5c76ee6 ZW |
11751 | && (! lookup_attribute ("longcall", |
11752 | TYPE_ATTRIBUTES (TREE_TYPE (function))) | |
11753 | || lookup_attribute ("shortcall", | |
11754 | TYPE_ATTRIBUTES (TREE_TYPE (function))))) | |
5b71a4e7 | 11755 | SYMBOL_REF_FLAG (funexp) = 1; |
17167fd8 | 11756 | |
5b71a4e7 | 11757 | funexp = gen_rtx_MEM (FUNCTION_MODE, funexp); |
ee890fe2 SS |
11758 | |
11759 | #if TARGET_MACHO | |
ab82a49f | 11760 | if (MACHOPIC_INDIRECT) |
5b71a4e7 | 11761 | funexp = machopic_indirect_call_target (funexp); |
ee890fe2 | 11762 | #endif |
5b71a4e7 DE |
11763 | |
11764 | /* gen_sibcall expects reload to convert scratch pseudo to LR so we must | |
11765 | generate sibcall RTL explicitly to avoid constraint abort. */ | |
11766 | insn = emit_call_insn ( | |
11767 | gen_rtx_PARALLEL (VOIDmode, | |
11768 | gen_rtvec (4, | |
11769 | gen_rtx_CALL (VOIDmode, | |
11770 | funexp, const0_rtx), | |
11771 | gen_rtx_USE (VOIDmode, const0_rtx), | |
11772 | gen_rtx_USE (VOIDmode, | |
11773 | gen_rtx_REG (SImode, | |
11774 | LINK_REGISTER_REGNUM)), | |
11775 | gen_rtx_RETURN (VOIDmode)))); | |
11776 | SIBLING_CALL_P (insn) = 1; | |
11777 | emit_barrier (); | |
11778 | ||
11779 | /* Run just enough of rest_of_compilation to get the insns emitted. | |
11780 | There's not really enough bulk here to make other passes such as | |
11781 | instruction scheduling worth while. Note that use_thunk calls | |
11782 | assemble_start_function and assemble_end_function. */ | |
11783 | insn = get_insns (); | |
11784 | shorten_branches (insn); | |
11785 | final_start_function (insn, file, 1); | |
11786 | final (insn, file, 1, 0); | |
11787 | final_end_function (); | |
11788 | ||
11789 | reload_completed = 0; | |
11790 | no_new_pseudos = 0; | |
9ebbca7d | 11791 | } |
9ebbca7d GK |
11792 | \f |
11793 | /* A quick summary of the various types of 'constant-pool tables' | |
11794 | under PowerPC: | |
11795 | ||
11796 | Target Flags Name One table per | |
11797 | AIX (none) AIX TOC object file | |
11798 | AIX -mfull-toc AIX TOC object file | |
11799 | AIX -mminimal-toc AIX minimal TOC translation unit | |
11800 | SVR4/EABI (none) SVR4 SDATA object file | |
11801 | SVR4/EABI -fpic SVR4 pic object file | |
11802 | SVR4/EABI -fPIC SVR4 PIC translation unit | |
11803 | SVR4/EABI -mrelocatable EABI TOC function | |
11804 | SVR4/EABI -maix AIX TOC object file | |
11805 | SVR4/EABI -maix -mminimal-toc | |
11806 | AIX minimal TOC translation unit | |
11807 | ||
11808 | Name Reg. Set by entries contains: | |
11809 | made by addrs? fp? sum? | |
11810 | ||
11811 | AIX TOC 2 crt0 as Y option option | |
11812 | AIX minimal TOC 30 prolog gcc Y Y option | |
11813 | SVR4 SDATA 13 crt0 gcc N Y N | |
11814 | SVR4 pic 30 prolog ld Y not yet N | |
11815 | SVR4 PIC 30 prolog gcc Y option option | |
11816 | EABI TOC 30 prolog gcc Y option option | |
11817 | ||
11818 | */ | |
11819 | ||
9ebbca7d GK |
11820 | /* Hash functions for the hash table. */ |
11821 | ||
11822 | static unsigned | |
11823 | rs6000_hash_constant (k) | |
11824 | rtx k; | |
11825 | { | |
46b33600 RH |
11826 | enum rtx_code code = GET_CODE (k); |
11827 | enum machine_mode mode = GET_MODE (k); | |
11828 | unsigned result = (code << 3) ^ mode; | |
11829 | const char *format; | |
11830 | int flen, fidx; | |
9ebbca7d | 11831 | |
46b33600 RH |
11832 | format = GET_RTX_FORMAT (code); |
11833 | flen = strlen (format); | |
11834 | fidx = 0; | |
9ebbca7d | 11835 | |
46b33600 RH |
11836 | switch (code) |
11837 | { | |
11838 | case LABEL_REF: | |
11839 | return result * 1231 + (unsigned) INSN_UID (XEXP (k, 0)); | |
11840 | ||
11841 | case CONST_DOUBLE: | |
11842 | if (mode != VOIDmode) | |
11843 | return real_hash (CONST_DOUBLE_REAL_VALUE (k)) * result; | |
11844 | flen = 2; | |
11845 | break; | |
11846 | ||
11847 | case CODE_LABEL: | |
11848 | fidx = 3; | |
11849 | break; | |
11850 | ||
11851 | default: | |
11852 | break; | |
11853 | } | |
9ebbca7d GK |
11854 | |
11855 | for (; fidx < flen; fidx++) | |
11856 | switch (format[fidx]) | |
11857 | { | |
11858 | case 's': | |
11859 | { | |
11860 | unsigned i, len; | |
11861 | const char *str = XSTR (k, fidx); | |
11862 | len = strlen (str); | |
11863 | result = result * 613 + len; | |
11864 | for (i = 0; i < len; i++) | |
11865 | result = result * 613 + (unsigned) str[i]; | |
17167fd8 MM |
11866 | break; |
11867 | } | |
9ebbca7d GK |
11868 | case 'u': |
11869 | case 'e': | |
11870 | result = result * 1231 + rs6000_hash_constant (XEXP (k, fidx)); | |
11871 | break; | |
11872 | case 'i': | |
11873 | case 'n': | |
11874 | result = result * 613 + (unsigned) XINT (k, fidx); | |
11875 | break; | |
11876 | case 'w': | |
11877 | if (sizeof (unsigned) >= sizeof (HOST_WIDE_INT)) | |
11878 | result = result * 613 + (unsigned) XWINT (k, fidx); | |
11879 | else | |
11880 | { | |
11881 | size_t i; | |
11882 | for (i = 0; i < sizeof(HOST_WIDE_INT)/sizeof(unsigned); i++) | |
11883 | result = result * 613 + (unsigned) (XWINT (k, fidx) | |
11884 | >> CHAR_BIT * i); | |
11885 | } | |
11886 | break; | |
09501938 DE |
11887 | case '0': |
11888 | break; | |
9ebbca7d | 11889 | default: |
a4f6c312 | 11890 | abort (); |
9ebbca7d | 11891 | } |
46b33600 | 11892 | |
9ebbca7d GK |
11893 | return result; |
11894 | } | |
11895 | ||
11896 | static unsigned | |
11897 | toc_hash_function (hash_entry) | |
11898 | const void * hash_entry; | |
11899 | { | |
a9098fd0 GK |
11900 | const struct toc_hash_struct *thc = |
11901 | (const struct toc_hash_struct *) hash_entry; | |
11902 | return rs6000_hash_constant (thc->key) ^ thc->key_mode; | |
9ebbca7d GK |
11903 | } |
11904 | ||
11905 | /* Compare H1 and H2 for equivalence. */ | |
11906 | ||
11907 | static int | |
11908 | toc_hash_eq (h1, h2) | |
11909 | const void * h1; | |
11910 | const void * h2; | |
11911 | { | |
11912 | rtx r1 = ((const struct toc_hash_struct *) h1)->key; | |
11913 | rtx r2 = ((const struct toc_hash_struct *) h2)->key; | |
11914 | ||
a9098fd0 GK |
11915 | if (((const struct toc_hash_struct *) h1)->key_mode |
11916 | != ((const struct toc_hash_struct *) h2)->key_mode) | |
11917 | return 0; | |
11918 | ||
5692c7bc | 11919 | return rtx_equal_p (r1, r2); |
9ebbca7d GK |
11920 | } |
11921 | ||
28e510bd MM |
11922 | /* These are the names given by the C++ front-end to vtables, and |
11923 | vtable-like objects. Ideally, this logic should not be here; | |
11924 | instead, there should be some programmatic way of inquiring as | |
11925 | to whether or not an object is a vtable. */ | |
11926 | ||
11927 | #define VTABLE_NAME_P(NAME) \ | |
11928 | (strncmp ("_vt.", name, strlen("_vt.")) == 0 \ | |
11929 | || strncmp ("_ZTV", name, strlen ("_ZTV")) == 0 \ | |
11930 | || strncmp ("_ZTT", name, strlen ("_ZTT")) == 0 \ | |
11931 | || strncmp ("_ZTC", name, strlen ("_ZTC")) == 0) | |
11932 | ||
11933 | void | |
11934 | rs6000_output_symbol_ref (file, x) | |
11935 | FILE *file; | |
11936 | rtx x; | |
11937 | { | |
11938 | /* Currently C++ toc references to vtables can be emitted before it | |
11939 | is decided whether the vtable is public or private. If this is | |
11940 | the case, then the linker will eventually complain that there is | |
11941 | a reference to an unknown section. Thus, for vtables only, | |
11942 | we emit the TOC reference to reference the symbol and not the | |
11943 | section. */ | |
11944 | const char *name = XSTR (x, 0); | |
54ee9799 DE |
11945 | |
11946 | if (VTABLE_NAME_P (name)) | |
11947 | { | |
11948 | RS6000_OUTPUT_BASENAME (file, name); | |
11949 | } | |
11950 | else | |
11951 | assemble_name (file, name); | |
28e510bd MM |
11952 | } |
11953 | ||
a4f6c312 SS |
11954 | /* Output a TOC entry. We derive the entry name from what is being |
11955 | written. */ | |
9878760c RK |
11956 | |
11957 | void | |
a9098fd0 | 11958 | output_toc (file, x, labelno, mode) |
9878760c RK |
11959 | FILE *file; |
11960 | rtx x; | |
11961 | int labelno; | |
a9098fd0 | 11962 | enum machine_mode mode; |
9878760c RK |
11963 | { |
11964 | char buf[256]; | |
3cce094d | 11965 | const char *name = buf; |
ec940faa | 11966 | const char *real_name; |
9878760c RK |
11967 | rtx base = x; |
11968 | int offset = 0; | |
11969 | ||
4697a36c MM |
11970 | if (TARGET_NO_TOC) |
11971 | abort (); | |
11972 | ||
9ebbca7d GK |
11973 | /* When the linker won't eliminate them, don't output duplicate |
11974 | TOC entries (this happens on AIX if there is any kind of TOC, | |
17211ab5 GK |
11975 | and on SVR4 under -fPIC or -mrelocatable). Don't do this for |
11976 | CODE_LABELs. */ | |
11977 | if (TARGET_TOC && GET_CODE (x) != LABEL_REF) | |
9ebbca7d GK |
11978 | { |
11979 | struct toc_hash_struct *h; | |
11980 | void * * found; | |
11981 | ||
17211ab5 GK |
11982 | /* Create toc_hash_table. This can't be done at OVERRIDE_OPTIONS |
11983 | time because GGC is not initialised at that point. */ | |
11984 | if (toc_hash_table == NULL) | |
11985 | toc_hash_table = htab_create_ggc (1021, toc_hash_function, | |
11986 | toc_hash_eq, NULL); | |
11987 | ||
9ebbca7d GK |
11988 | h = ggc_alloc (sizeof (*h)); |
11989 | h->key = x; | |
a9098fd0 | 11990 | h->key_mode = mode; |
9ebbca7d GK |
11991 | h->labelno = labelno; |
11992 | ||
11993 | found = htab_find_slot (toc_hash_table, h, 1); | |
11994 | if (*found == NULL) | |
11995 | *found = h; | |
11996 | else /* This is indeed a duplicate. | |
11997 | Set this label equal to that label. */ | |
11998 | { | |
11999 | fputs ("\t.set ", file); | |
12000 | ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC"); | |
12001 | fprintf (file, "%d,", labelno); | |
12002 | ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC"); | |
12003 | fprintf (file, "%d\n", ((*(const struct toc_hash_struct **) | |
12004 | found)->labelno)); | |
12005 | return; | |
12006 | } | |
12007 | } | |
12008 | ||
12009 | /* If we're going to put a double constant in the TOC, make sure it's | |
12010 | aligned properly when strict alignment is on. */ | |
ff1720ed RK |
12011 | if (GET_CODE (x) == CONST_DOUBLE |
12012 | && STRICT_ALIGNMENT | |
a9098fd0 | 12013 | && GET_MODE_BITSIZE (mode) >= 64 |
ff1720ed RK |
12014 | && ! (TARGET_NO_FP_IN_TOC && ! TARGET_MINIMAL_TOC)) { |
12015 | ASM_OUTPUT_ALIGN (file, 3); | |
12016 | } | |
12017 | ||
4977bab6 | 12018 | (*targetm.asm_out.internal_label) (file, "LC", labelno); |
9878760c | 12019 | |
37c37a57 RK |
12020 | /* Handle FP constants specially. Note that if we have a minimal |
12021 | TOC, things we put here aren't actually in the TOC, so we can allow | |
12022 | FP constants. */ | |
fcce224d DE |
12023 | if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == TFmode) |
12024 | { | |
12025 | REAL_VALUE_TYPE rv; | |
12026 | long k[4]; | |
12027 | ||
12028 | REAL_VALUE_FROM_CONST_DOUBLE (rv, x); | |
12029 | REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv, k); | |
12030 | ||
12031 | if (TARGET_64BIT) | |
12032 | { | |
12033 | if (TARGET_MINIMAL_TOC) | |
12034 | fputs (DOUBLE_INT_ASM_OP, file); | |
12035 | else | |
12036 | fprintf (file, "\t.tc FT_%lx_%lx_%lx_%lx[TC],", | |
12037 | k[0] & 0xffffffff, k[1] & 0xffffffff, | |
12038 | k[2] & 0xffffffff, k[3] & 0xffffffff); | |
12039 | fprintf (file, "0x%lx%08lx,0x%lx%08lx\n", | |
12040 | k[0] & 0xffffffff, k[1] & 0xffffffff, | |
12041 | k[2] & 0xffffffff, k[3] & 0xffffffff); | |
12042 | return; | |
12043 | } | |
12044 | else | |
12045 | { | |
12046 | if (TARGET_MINIMAL_TOC) | |
12047 | fputs ("\t.long ", file); | |
12048 | else | |
12049 | fprintf (file, "\t.tc FT_%lx_%lx_%lx_%lx[TC],", | |
12050 | k[0] & 0xffffffff, k[1] & 0xffffffff, | |
12051 | k[2] & 0xffffffff, k[3] & 0xffffffff); | |
12052 | fprintf (file, "0x%lx,0x%lx,0x%lx,0x%lx\n", | |
12053 | k[0] & 0xffffffff, k[1] & 0xffffffff, | |
12054 | k[2] & 0xffffffff, k[3] & 0xffffffff); | |
12055 | return; | |
12056 | } | |
12057 | } | |
12058 | else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == DFmode) | |
9878760c | 12059 | { |
042259f2 DE |
12060 | REAL_VALUE_TYPE rv; |
12061 | long k[2]; | |
0adc764e | 12062 | |
042259f2 DE |
12063 | REAL_VALUE_FROM_CONST_DOUBLE (rv, x); |
12064 | REAL_VALUE_TO_TARGET_DOUBLE (rv, k); | |
31bfaa0b | 12065 | |
13ded975 DE |
12066 | if (TARGET_64BIT) |
12067 | { | |
12068 | if (TARGET_MINIMAL_TOC) | |
2bfcf297 | 12069 | fputs (DOUBLE_INT_ASM_OP, file); |
13ded975 | 12070 | else |
2f0552b6 AM |
12071 | fprintf (file, "\t.tc FD_%lx_%lx[TC],", |
12072 | k[0] & 0xffffffff, k[1] & 0xffffffff); | |
12073 | fprintf (file, "0x%lx%08lx\n", | |
12074 | k[0] & 0xffffffff, k[1] & 0xffffffff); | |
13ded975 DE |
12075 | return; |
12076 | } | |
1875cc88 | 12077 | else |
13ded975 DE |
12078 | { |
12079 | if (TARGET_MINIMAL_TOC) | |
2bfcf297 | 12080 | fputs ("\t.long ", file); |
13ded975 | 12081 | else |
2f0552b6 AM |
12082 | fprintf (file, "\t.tc FD_%lx_%lx[TC],", |
12083 | k[0] & 0xffffffff, k[1] & 0xffffffff); | |
12084 | fprintf (file, "0x%lx,0x%lx\n", | |
12085 | k[0] & 0xffffffff, k[1] & 0xffffffff); | |
13ded975 DE |
12086 | return; |
12087 | } | |
9878760c | 12088 | } |
a9098fd0 | 12089 | else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == SFmode) |
9878760c | 12090 | { |
042259f2 DE |
12091 | REAL_VALUE_TYPE rv; |
12092 | long l; | |
9878760c | 12093 | |
042259f2 DE |
12094 | REAL_VALUE_FROM_CONST_DOUBLE (rv, x); |
12095 | REAL_VALUE_TO_TARGET_SINGLE (rv, l); | |
12096 | ||
31bfaa0b DE |
12097 | if (TARGET_64BIT) |
12098 | { | |
12099 | if (TARGET_MINIMAL_TOC) | |
2bfcf297 | 12100 | fputs (DOUBLE_INT_ASM_OP, file); |
31bfaa0b | 12101 | else |
2f0552b6 AM |
12102 | fprintf (file, "\t.tc FS_%lx[TC],", l & 0xffffffff); |
12103 | fprintf (file, "0x%lx00000000\n", l & 0xffffffff); | |
31bfaa0b DE |
12104 | return; |
12105 | } | |
042259f2 | 12106 | else |
31bfaa0b DE |
12107 | { |
12108 | if (TARGET_MINIMAL_TOC) | |
2bfcf297 | 12109 | fputs ("\t.long ", file); |
31bfaa0b | 12110 | else |
2f0552b6 AM |
12111 | fprintf (file, "\t.tc FS_%lx[TC],", l & 0xffffffff); |
12112 | fprintf (file, "0x%lx\n", l & 0xffffffff); | |
31bfaa0b DE |
12113 | return; |
12114 | } | |
042259f2 | 12115 | } |
f176e826 | 12116 | else if (GET_MODE (x) == VOIDmode |
a9098fd0 | 12117 | && (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE)) |
042259f2 | 12118 | { |
e2c953b6 | 12119 | unsigned HOST_WIDE_INT low; |
042259f2 DE |
12120 | HOST_WIDE_INT high; |
12121 | ||
12122 | if (GET_CODE (x) == CONST_DOUBLE) | |
12123 | { | |
12124 | low = CONST_DOUBLE_LOW (x); | |
12125 | high = CONST_DOUBLE_HIGH (x); | |
12126 | } | |
12127 | else | |
12128 | #if HOST_BITS_PER_WIDE_INT == 32 | |
12129 | { | |
12130 | low = INTVAL (x); | |
0858c623 | 12131 | high = (low & 0x80000000) ? ~0 : 0; |
042259f2 DE |
12132 | } |
12133 | #else | |
12134 | { | |
0858c623 | 12135 | low = INTVAL (x) & 0xffffffff; |
042259f2 DE |
12136 | high = (HOST_WIDE_INT) INTVAL (x) >> 32; |
12137 | } | |
12138 | #endif | |
9878760c | 12139 | |
a9098fd0 GK |
12140 | /* TOC entries are always Pmode-sized, but since this |
12141 | is a bigendian machine then if we're putting smaller | |
12142 | integer constants in the TOC we have to pad them. | |
12143 | (This is still a win over putting the constants in | |
12144 | a separate constant pool, because then we'd have | |
02a4ec28 FS |
12145 | to have both a TOC entry _and_ the actual constant.) |
12146 | ||
12147 | For a 32-bit target, CONST_INT values are loaded and shifted | |
12148 | entirely within `low' and can be stored in one TOC entry. */ | |
12149 | ||
12150 | if (TARGET_64BIT && POINTER_SIZE < GET_MODE_BITSIZE (mode)) | |
a9098fd0 | 12151 | abort ();/* It would be easy to make this work, but it doesn't now. */ |
02a4ec28 FS |
12152 | |
12153 | if (POINTER_SIZE > GET_MODE_BITSIZE (mode)) | |
fb52d8de AM |
12154 | { |
12155 | #if HOST_BITS_PER_WIDE_INT == 32 | |
12156 | lshift_double (low, high, POINTER_SIZE - GET_MODE_BITSIZE (mode), | |
12157 | POINTER_SIZE, &low, &high, 0); | |
12158 | #else | |
12159 | low |= high << 32; | |
12160 | low <<= POINTER_SIZE - GET_MODE_BITSIZE (mode); | |
12161 | high = (HOST_WIDE_INT) low >> 32; | |
12162 | low &= 0xffffffff; | |
12163 | #endif | |
12164 | } | |
a9098fd0 | 12165 | |
13ded975 DE |
12166 | if (TARGET_64BIT) |
12167 | { | |
12168 | if (TARGET_MINIMAL_TOC) | |
2bfcf297 | 12169 | fputs (DOUBLE_INT_ASM_OP, file); |
13ded975 | 12170 | else |
2f0552b6 AM |
12171 | fprintf (file, "\t.tc ID_%lx_%lx[TC],", |
12172 | (long) high & 0xffffffff, (long) low & 0xffffffff); | |
12173 | fprintf (file, "0x%lx%08lx\n", | |
12174 | (long) high & 0xffffffff, (long) low & 0xffffffff); | |
13ded975 DE |
12175 | return; |
12176 | } | |
1875cc88 | 12177 | else |
13ded975 | 12178 | { |
02a4ec28 FS |
12179 | if (POINTER_SIZE < GET_MODE_BITSIZE (mode)) |
12180 | { | |
12181 | if (TARGET_MINIMAL_TOC) | |
2bfcf297 | 12182 | fputs ("\t.long ", file); |
02a4ec28 | 12183 | else |
2bfcf297 | 12184 | fprintf (file, "\t.tc ID_%lx_%lx[TC],", |
2f0552b6 AM |
12185 | (long) high & 0xffffffff, (long) low & 0xffffffff); |
12186 | fprintf (file, "0x%lx,0x%lx\n", | |
12187 | (long) high & 0xffffffff, (long) low & 0xffffffff); | |
02a4ec28 | 12188 | } |
13ded975 | 12189 | else |
02a4ec28 FS |
12190 | { |
12191 | if (TARGET_MINIMAL_TOC) | |
2bfcf297 | 12192 | fputs ("\t.long ", file); |
02a4ec28 | 12193 | else |
2f0552b6 AM |
12194 | fprintf (file, "\t.tc IS_%lx[TC],", (long) low & 0xffffffff); |
12195 | fprintf (file, "0x%lx\n", (long) low & 0xffffffff); | |
02a4ec28 | 12196 | } |
13ded975 DE |
12197 | return; |
12198 | } | |
9878760c RK |
12199 | } |
12200 | ||
12201 | if (GET_CODE (x) == CONST) | |
12202 | { | |
2bfcf297 DB |
12203 | if (GET_CODE (XEXP (x, 0)) != PLUS) |
12204 | abort (); | |
12205 | ||
9878760c RK |
12206 | base = XEXP (XEXP (x, 0), 0); |
12207 | offset = INTVAL (XEXP (XEXP (x, 0), 1)); | |
12208 | } | |
12209 | ||
12210 | if (GET_CODE (base) == SYMBOL_REF) | |
12211 | name = XSTR (base, 0); | |
12212 | else if (GET_CODE (base) == LABEL_REF) | |
12213 | ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (XEXP (base, 0))); | |
12214 | else if (GET_CODE (base) == CODE_LABEL) | |
12215 | ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (base)); | |
12216 | else | |
12217 | abort (); | |
12218 | ||
772c5265 | 12219 | real_name = (*targetm.strip_name_encoding) (name); |
1875cc88 | 12220 | if (TARGET_MINIMAL_TOC) |
2bfcf297 | 12221 | fputs (TARGET_32BIT ? "\t.long " : DOUBLE_INT_ASM_OP, file); |
1875cc88 JW |
12222 | else |
12223 | { | |
b6c9286a | 12224 | fprintf (file, "\t.tc %s", real_name); |
9878760c | 12225 | |
1875cc88 JW |
12226 | if (offset < 0) |
12227 | fprintf (file, ".N%d", - offset); | |
12228 | else if (offset) | |
12229 | fprintf (file, ".P%d", offset); | |
9878760c | 12230 | |
19d2d16f | 12231 | fputs ("[TC],", file); |
1875cc88 | 12232 | } |
581bc4de MM |
12233 | |
12234 | /* Currently C++ toc references to vtables can be emitted before it | |
12235 | is decided whether the vtable is public or private. If this is | |
12236 | the case, then the linker will eventually complain that there is | |
12237 | a TOC reference to an unknown section. Thus, for vtables only, | |
12238 | we emit the TOC reference to reference the symbol and not the | |
12239 | section. */ | |
28e510bd | 12240 | if (VTABLE_NAME_P (name)) |
581bc4de | 12241 | { |
54ee9799 | 12242 | RS6000_OUTPUT_BASENAME (file, name); |
581bc4de MM |
12243 | if (offset < 0) |
12244 | fprintf (file, "%d", offset); | |
12245 | else if (offset > 0) | |
12246 | fprintf (file, "+%d", offset); | |
12247 | } | |
12248 | else | |
12249 | output_addr_const (file, x); | |
19d2d16f | 12250 | putc ('\n', file); |
9878760c RK |
12251 | } |
12252 | \f | |
12253 | /* Output an assembler pseudo-op to write an ASCII string of N characters | |
12254 | starting at P to FILE. | |
12255 | ||
12256 | On the RS/6000, we have to do this using the .byte operation and | |
12257 | write out special characters outside the quoted string. | |
12258 | Also, the assembler is broken; very long strings are truncated, | |
a4f6c312 | 12259 | so we must artificially break them up early. */ |
9878760c RK |
12260 | |
12261 | void | |
12262 | output_ascii (file, p, n) | |
12263 | FILE *file; | |
d330fd93 | 12264 | const char *p; |
9878760c RK |
12265 | int n; |
12266 | { | |
12267 | char c; | |
12268 | int i, count_string; | |
d330fd93 KG |
12269 | const char *for_string = "\t.byte \""; |
12270 | const char *for_decimal = "\t.byte "; | |
12271 | const char *to_close = NULL; | |
9878760c RK |
12272 | |
12273 | count_string = 0; | |
12274 | for (i = 0; i < n; i++) | |
12275 | { | |
12276 | c = *p++; | |
12277 | if (c >= ' ' && c < 0177) | |
12278 | { | |
12279 | if (for_string) | |
12280 | fputs (for_string, file); | |
12281 | putc (c, file); | |
12282 | ||
12283 | /* Write two quotes to get one. */ | |
12284 | if (c == '"') | |
12285 | { | |
12286 | putc (c, file); | |
12287 | ++count_string; | |
12288 | } | |
12289 | ||
12290 | for_string = NULL; | |
12291 | for_decimal = "\"\n\t.byte "; | |
12292 | to_close = "\"\n"; | |
12293 | ++count_string; | |
12294 | ||
12295 | if (count_string >= 512) | |
12296 | { | |
12297 | fputs (to_close, file); | |
12298 | ||
12299 | for_string = "\t.byte \""; | |
12300 | for_decimal = "\t.byte "; | |
12301 | to_close = NULL; | |
12302 | count_string = 0; | |
12303 | } | |
12304 | } | |
12305 | else | |
12306 | { | |
12307 | if (for_decimal) | |
12308 | fputs (for_decimal, file); | |
12309 | fprintf (file, "%d", c); | |
12310 | ||
12311 | for_string = "\n\t.byte \""; | |
12312 | for_decimal = ", "; | |
12313 | to_close = "\n"; | |
12314 | count_string = 0; | |
12315 | } | |
12316 | } | |
12317 | ||
12318 | /* Now close the string if we have written one. Then end the line. */ | |
12319 | if (to_close) | |
9ebbca7d | 12320 | fputs (to_close, file); |
9878760c RK |
12321 | } |
12322 | \f | |
12323 | /* Generate a unique section name for FILENAME for a section type | |
12324 | represented by SECTION_DESC. Output goes into BUF. | |
12325 | ||
12326 | SECTION_DESC can be any string, as long as it is different for each | |
12327 | possible section type. | |
12328 | ||
12329 | We name the section in the same manner as xlc. The name begins with an | |
12330 | underscore followed by the filename (after stripping any leading directory | |
11e5fe42 RK |
12331 | names) with the last period replaced by the string SECTION_DESC. If |
12332 | FILENAME does not contain a period, SECTION_DESC is appended to the end of | |
12333 | the name. */ | |
9878760c RK |
12334 | |
12335 | void | |
12336 | rs6000_gen_section_name (buf, filename, section_desc) | |
12337 | char **buf; | |
9ebbca7d GK |
12338 | const char *filename; |
12339 | const char *section_desc; | |
9878760c | 12340 | { |
9ebbca7d | 12341 | const char *q, *after_last_slash, *last_period = 0; |
9878760c RK |
12342 | char *p; |
12343 | int len; | |
9878760c RK |
12344 | |
12345 | after_last_slash = filename; | |
12346 | for (q = filename; *q; q++) | |
11e5fe42 RK |
12347 | { |
12348 | if (*q == '/') | |
12349 | after_last_slash = q + 1; | |
12350 | else if (*q == '.') | |
12351 | last_period = q; | |
12352 | } | |
9878760c | 12353 | |
11e5fe42 | 12354 | len = strlen (after_last_slash) + strlen (section_desc) + 2; |
6d9f628e | 12355 | *buf = (char *) xmalloc (len); |
9878760c RK |
12356 | |
12357 | p = *buf; | |
12358 | *p++ = '_'; | |
12359 | ||
12360 | for (q = after_last_slash; *q; q++) | |
12361 | { | |
11e5fe42 | 12362 | if (q == last_period) |
9878760c RK |
12363 | { |
12364 | strcpy (p, section_desc); | |
12365 | p += strlen (section_desc); | |
e3981aab | 12366 | break; |
9878760c RK |
12367 | } |
12368 | ||
e9a780ec | 12369 | else if (ISALNUM (*q)) |
9878760c RK |
12370 | *p++ = *q; |
12371 | } | |
12372 | ||
11e5fe42 | 12373 | if (last_period == 0) |
9878760c RK |
12374 | strcpy (p, section_desc); |
12375 | else | |
12376 | *p = '\0'; | |
12377 | } | |
e165f3f0 | 12378 | \f |
a4f6c312 | 12379 | /* Emit profile function. */ |
411707f4 | 12380 | |
411707f4 CC |
12381 | void |
12382 | output_profile_hook (labelno) | |
57ac7be9 | 12383 | int labelno ATTRIBUTE_UNUSED; |
411707f4 | 12384 | { |
ffcfcb5f AM |
12385 | if (TARGET_PROFILE_KERNEL) |
12386 | return; | |
12387 | ||
8480e480 CC |
12388 | if (DEFAULT_ABI == ABI_AIX) |
12389 | { | |
57ac7be9 AM |
12390 | #ifdef NO_PROFILE_COUNTERS |
12391 | emit_library_call (init_one_libfunc (RS6000_MCOUNT), 0, VOIDmode, 0); | |
12392 | #else | |
8480e480 | 12393 | char buf[30]; |
40501e5f | 12394 | const char *label_name; |
8480e480 | 12395 | rtx fun; |
411707f4 | 12396 | |
8480e480 | 12397 | ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno); |
772c5265 | 12398 | label_name = (*targetm.strip_name_encoding) (ggc_strdup (buf)); |
8480e480 | 12399 | fun = gen_rtx_SYMBOL_REF (Pmode, label_name); |
411707f4 | 12400 | |
8480e480 CC |
12401 | emit_library_call (init_one_libfunc (RS6000_MCOUNT), 0, VOIDmode, 1, |
12402 | fun, Pmode); | |
57ac7be9 | 12403 | #endif |
8480e480 | 12404 | } |
ee890fe2 SS |
12405 | else if (DEFAULT_ABI == ABI_DARWIN) |
12406 | { | |
d5fa86ba | 12407 | const char *mcount_name = RS6000_MCOUNT; |
ee890fe2 SS |
12408 | int caller_addr_regno = LINK_REGISTER_REGNUM; |
12409 | ||
12410 | /* Be conservative and always set this, at least for now. */ | |
12411 | current_function_uses_pic_offset_table = 1; | |
12412 | ||
12413 | #if TARGET_MACHO | |
12414 | /* For PIC code, set up a stub and collect the caller's address | |
12415 | from r0, which is where the prologue puts it. */ | |
ab82a49f | 12416 | if (MACHOPIC_INDIRECT) |
ee890fe2 SS |
12417 | { |
12418 | mcount_name = machopic_stub_name (mcount_name); | |
12419 | if (current_function_uses_pic_offset_table) | |
12420 | caller_addr_regno = 0; | |
12421 | } | |
12422 | #endif | |
12423 | emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mcount_name), | |
12424 | 0, VOIDmode, 1, | |
12425 | gen_rtx_REG (Pmode, caller_addr_regno), Pmode); | |
12426 | } | |
411707f4 CC |
12427 | } |
12428 | ||
a4f6c312 | 12429 | /* Write function profiler code. */ |
e165f3f0 RK |
12430 | |
12431 | void | |
12432 | output_function_profiler (file, labelno) | |
12433 | FILE *file; | |
12434 | int labelno; | |
12435 | { | |
3daf36a4 | 12436 | char buf[100]; |
09eeeacb | 12437 | int save_lr = 8; |
e165f3f0 | 12438 | |
38c1f2d7 | 12439 | switch (DEFAULT_ABI) |
3daf36a4 | 12440 | { |
38c1f2d7 MM |
12441 | default: |
12442 | abort (); | |
12443 | ||
12444 | case ABI_V4: | |
09eeeacb | 12445 | save_lr = 4; |
09eeeacb AM |
12446 | if (!TARGET_32BIT) |
12447 | { | |
12448 | warning ("no profiling of 64-bit code for this ABI"); | |
12449 | return; | |
12450 | } | |
ffcfcb5f | 12451 | ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno); |
38c1f2d7 MM |
12452 | fprintf (file, "\tmflr %s\n", reg_names[0]); |
12453 | if (flag_pic == 1) | |
12454 | { | |
dfdfa60f | 12455 | fputs ("\tbl _GLOBAL_OFFSET_TABLE_@local-4\n", file); |
09eeeacb AM |
12456 | asm_fprintf (file, "\t{st|stw} %s,%d(%s)\n", |
12457 | reg_names[0], save_lr, reg_names[1]); | |
17167fd8 | 12458 | asm_fprintf (file, "\tmflr %s\n", reg_names[12]); |
dfdfa60f | 12459 | asm_fprintf (file, "\t{l|lwz} %s,", reg_names[0]); |
38c1f2d7 | 12460 | assemble_name (file, buf); |
17167fd8 | 12461 | asm_fprintf (file, "@got(%s)\n", reg_names[12]); |
38c1f2d7 | 12462 | } |
9ebbca7d | 12463 | else if (flag_pic > 1) |
38c1f2d7 | 12464 | { |
09eeeacb AM |
12465 | asm_fprintf (file, "\t{st|stw} %s,%d(%s)\n", |
12466 | reg_names[0], save_lr, reg_names[1]); | |
9ebbca7d GK |
12467 | /* Now, we need to get the address of the label. */ |
12468 | fputs ("\tbl 1f\n\t.long ", file); | |
034e84c4 | 12469 | assemble_name (file, buf); |
9ebbca7d GK |
12470 | fputs ("-.\n1:", file); |
12471 | asm_fprintf (file, "\tmflr %s\n", reg_names[11]); | |
12472 | asm_fprintf (file, "\t{l|lwz} %s,0(%s)\n", | |
12473 | reg_names[0], reg_names[11]); | |
12474 | asm_fprintf (file, "\t{cax|add} %s,%s,%s\n", | |
12475 | reg_names[0], reg_names[0], reg_names[11]); | |
38c1f2d7 | 12476 | } |
38c1f2d7 MM |
12477 | else |
12478 | { | |
17167fd8 | 12479 | asm_fprintf (file, "\t{liu|lis} %s,", reg_names[12]); |
38c1f2d7 | 12480 | assemble_name (file, buf); |
dfdfa60f | 12481 | fputs ("@ha\n", file); |
09eeeacb AM |
12482 | asm_fprintf (file, "\t{st|stw} %s,%d(%s)\n", |
12483 | reg_names[0], save_lr, reg_names[1]); | |
a260abc9 | 12484 | asm_fprintf (file, "\t{cal|la} %s,", reg_names[0]); |
38c1f2d7 | 12485 | assemble_name (file, buf); |
17167fd8 | 12486 | asm_fprintf (file, "@l(%s)\n", reg_names[12]); |
38c1f2d7 MM |
12487 | } |
12488 | ||
50d440bc NC |
12489 | /* ABI_V4 saves the static chain reg with ASM_OUTPUT_REG_PUSH. */ |
12490 | fprintf (file, "\tbl %s\n", RS6000_MCOUNT); | |
38c1f2d7 MM |
12491 | break; |
12492 | ||
12493 | case ABI_AIX: | |
ee890fe2 | 12494 | case ABI_DARWIN: |
ffcfcb5f AM |
12495 | if (!TARGET_PROFILE_KERNEL) |
12496 | { | |
12497 | /* Don't do anything, done in output_profile_hook (). */ | |
12498 | } | |
12499 | else | |
12500 | { | |
12501 | if (TARGET_32BIT) | |
12502 | abort (); | |
12503 | ||
12504 | asm_fprintf (file, "\tmflr %s\n", reg_names[0]); | |
12505 | asm_fprintf (file, "\tstd %s,16(%s)\n", reg_names[0], reg_names[1]); | |
12506 | ||
12507 | if (current_function_needs_context) | |
12508 | { | |
12509 | asm_fprintf (file, "\tstd %s,24(%s)\n", | |
12510 | reg_names[STATIC_CHAIN_REGNUM], reg_names[1]); | |
12511 | fprintf (file, "\tbl %s\n", RS6000_MCOUNT); | |
12512 | asm_fprintf (file, "\tld %s,24(%s)\n", | |
12513 | reg_names[STATIC_CHAIN_REGNUM], reg_names[1]); | |
12514 | } | |
12515 | else | |
12516 | fprintf (file, "\tbl %s\n", RS6000_MCOUNT); | |
12517 | } | |
38c1f2d7 MM |
12518 | break; |
12519 | } | |
e165f3f0 | 12520 | } |
a251ffd0 | 12521 | |
b54cf83a DE |
12522 | \f |
12523 | static int | |
12524 | rs6000_use_dfa_pipeline_interface () | |
12525 | { | |
12526 | return 1; | |
12527 | } | |
12528 | ||
b54cf83a DE |
12529 | /* Power4 load update and store update instructions are cracked into a |
12530 | load or store and an integer insn which are executed in the same cycle. | |
12531 | Branches have their own dispatch slot which does not count against the | |
12532 | GCC issue rate, but it changes the program flow so there are no other | |
12533 | instructions to issue in this cycle. */ | |
12534 | ||
12535 | static int | |
12536 | rs6000_variable_issue (stream, verbose, insn, more) | |
12537 | FILE *stream ATTRIBUTE_UNUSED; | |
12538 | int verbose ATTRIBUTE_UNUSED; | |
12539 | rtx insn; | |
12540 | int more; | |
12541 | { | |
12542 | if (GET_CODE (PATTERN (insn)) == USE | |
12543 | || GET_CODE (PATTERN (insn)) == CLOBBER) | |
12544 | return more; | |
12545 | ||
12546 | if (rs6000_cpu == PROCESSOR_POWER4) | |
12547 | { | |
12548 | enum attr_type type = get_attr_type (insn); | |
12549 | if (type == TYPE_LOAD_EXT_U || type == TYPE_LOAD_EXT_UX | |
9259f3b0 | 12550 | || type == TYPE_LOAD_UX || type == TYPE_STORE_UX) |
b54cf83a DE |
12551 | return 0; |
12552 | else if (type == TYPE_LOAD_U || type == TYPE_STORE_U | |
12553 | || type == TYPE_FPLOAD_U || type == TYPE_FPSTORE_U | |
9259f3b0 DE |
12554 | || type == TYPE_FPLOAD_UX || type == TYPE_FPSTORE_UX |
12555 | || type == TYPE_LOAD_EXT || type == TYPE_DELAYED_CR | |
12556 | || type == TYPE_COMPARE || type == TYPE_DELAYED_COMPARE | |
12557 | || type == TYPE_IMUL_COMPARE || type == TYPE_LMUL_COMPARE | |
12558 | || type == TYPE_IDIV || type == TYPE_LDIV) | |
3317bab1 | 12559 | return more > 2 ? more - 2 : 0; |
b54cf83a | 12560 | } |
165b263e DE |
12561 | |
12562 | return more - 1; | |
b54cf83a DE |
12563 | } |
12564 | ||
a251ffd0 TG |
12565 | /* Adjust the cost of a scheduling dependency. Return the new cost of |
12566 | a dependency LINK or INSN on DEP_INSN. COST is the current cost. */ | |
12567 | ||
c237e94a | 12568 | static int |
a06faf84 | 12569 | rs6000_adjust_cost (insn, link, dep_insn, cost) |
a251ffd0 TG |
12570 | rtx insn; |
12571 | rtx link; | |
296b8152 | 12572 | rtx dep_insn ATTRIBUTE_UNUSED; |
a251ffd0 TG |
12573 | int cost; |
12574 | { | |
12575 | if (! recog_memoized (insn)) | |
12576 | return 0; | |
12577 | ||
12578 | if (REG_NOTE_KIND (link) != 0) | |
12579 | return 0; | |
12580 | ||
12581 | if (REG_NOTE_KIND (link) == 0) | |
12582 | { | |
ed947a96 DJ |
12583 | /* Data dependency; DEP_INSN writes a register that INSN reads |
12584 | some cycles later. */ | |
12585 | switch (get_attr_type (insn)) | |
12586 | { | |
12587 | case TYPE_JMPREG: | |
309323c2 | 12588 | /* Tell the first scheduling pass about the latency between |
ed947a96 DJ |
12589 | a mtctr and bctr (and mtlr and br/blr). The first |
12590 | scheduling pass will not know about this latency since | |
12591 | the mtctr instruction, which has the latency associated | |
12592 | to it, will be generated by reload. */ | |
309323c2 | 12593 | return TARGET_POWER ? 5 : 4; |
ed947a96 DJ |
12594 | case TYPE_BRANCH: |
12595 | /* Leave some extra cycles between a compare and its | |
12596 | dependent branch, to inhibit expensive mispredicts. */ | |
309323c2 DE |
12597 | if ((rs6000_cpu_attr == CPU_PPC603 |
12598 | || rs6000_cpu_attr == CPU_PPC604 | |
12599 | || rs6000_cpu_attr == CPU_PPC604E | |
12600 | || rs6000_cpu_attr == CPU_PPC620 | |
12601 | || rs6000_cpu_attr == CPU_PPC630 | |
12602 | || rs6000_cpu_attr == CPU_PPC750 | |
12603 | || rs6000_cpu_attr == CPU_PPC7400 | |
12604 | || rs6000_cpu_attr == CPU_PPC7450 | |
12605 | || rs6000_cpu_attr == CPU_POWER4) | |
ed947a96 DJ |
12606 | && recog_memoized (dep_insn) |
12607 | && (INSN_CODE (dep_insn) >= 0) | |
b54cf83a DE |
12608 | && (get_attr_type (dep_insn) == TYPE_CMP |
12609 | || get_attr_type (dep_insn) == TYPE_COMPARE | |
ed947a96 | 12610 | || get_attr_type (dep_insn) == TYPE_DELAYED_COMPARE |
9259f3b0 DE |
12611 | || get_attr_type (dep_insn) == TYPE_IMUL_COMPARE |
12612 | || get_attr_type (dep_insn) == TYPE_LMUL_COMPARE | |
ed947a96 | 12613 | || get_attr_type (dep_insn) == TYPE_FPCOMPARE |
b54cf83a DE |
12614 | || get_attr_type (dep_insn) == TYPE_CR_LOGICAL |
12615 | || get_attr_type (dep_insn) == TYPE_DELAYED_CR)) | |
ed947a96 DJ |
12616 | return cost + 2; |
12617 | default: | |
12618 | break; | |
12619 | } | |
a251ffd0 TG |
12620 | /* Fall out to return default cost. */ |
12621 | } | |
12622 | ||
12623 | return cost; | |
12624 | } | |
b6c9286a | 12625 | |
a4f6c312 SS |
12626 | /* A C statement (sans semicolon) to update the integer scheduling |
12627 | priority INSN_PRIORITY (INSN). Reduce the priority to execute the | |
12628 | INSN earlier, increase the priority to execute INSN later. Do not | |
12629 | define this macro if you do not need to adjust the scheduling | |
12630 | priorities of insns. */ | |
bef84347 | 12631 | |
c237e94a | 12632 | static int |
bef84347 | 12633 | rs6000_adjust_priority (insn, priority) |
d330fd93 | 12634 | rtx insn ATTRIBUTE_UNUSED; |
bef84347 VM |
12635 | int priority; |
12636 | { | |
a4f6c312 SS |
12637 | /* On machines (like the 750) which have asymmetric integer units, |
12638 | where one integer unit can do multiply and divides and the other | |
12639 | can't, reduce the priority of multiply/divide so it is scheduled | |
12640 | before other integer operations. */ | |
bef84347 VM |
12641 | |
12642 | #if 0 | |
2c3c49de | 12643 | if (! INSN_P (insn)) |
bef84347 VM |
12644 | return priority; |
12645 | ||
12646 | if (GET_CODE (PATTERN (insn)) == USE) | |
12647 | return priority; | |
12648 | ||
12649 | switch (rs6000_cpu_attr) { | |
12650 | case CPU_PPC750: | |
12651 | switch (get_attr_type (insn)) | |
12652 | { | |
12653 | default: | |
12654 | break; | |
12655 | ||
12656 | case TYPE_IMUL: | |
12657 | case TYPE_IDIV: | |
3cb999d8 DE |
12658 | fprintf (stderr, "priority was %#x (%d) before adjustment\n", |
12659 | priority, priority); | |
bef84347 VM |
12660 | if (priority >= 0 && priority < 0x01000000) |
12661 | priority >>= 3; | |
12662 | break; | |
12663 | } | |
12664 | } | |
12665 | #endif | |
12666 | ||
12667 | return priority; | |
12668 | } | |
12669 | ||
a4f6c312 SS |
12670 | /* Return how many instructions the machine can issue per cycle. */ |
12671 | ||
c237e94a ZW |
12672 | static int |
12673 | rs6000_issue_rate () | |
b6c9286a | 12674 | { |
3317bab1 DE |
12675 | /* Use issue rate of 1 for first scheduling pass to decrease degradation. */ |
12676 | if (!reload_completed) | |
12677 | return 1; | |
12678 | ||
b6c9286a | 12679 | switch (rs6000_cpu_attr) { |
3cb999d8 DE |
12680 | case CPU_RIOS1: /* ? */ |
12681 | case CPU_RS64A: | |
12682 | case CPU_PPC601: /* ? */ | |
ed947a96 | 12683 | case CPU_PPC7450: |
3cb999d8 | 12684 | return 3; |
b54cf83a | 12685 | case CPU_PPC440: |
b6c9286a | 12686 | case CPU_PPC603: |
bef84347 | 12687 | case CPU_PPC750: |
ed947a96 | 12688 | case CPU_PPC7400: |
be12c2b0 | 12689 | case CPU_PPC8540: |
bef84347 | 12690 | return 2; |
3cb999d8 | 12691 | case CPU_RIOS2: |
b6c9286a | 12692 | case CPU_PPC604: |
19684119 | 12693 | case CPU_PPC604E: |
b6c9286a | 12694 | case CPU_PPC620: |
3cb999d8 | 12695 | case CPU_PPC630: |
309323c2 | 12696 | case CPU_POWER4: |
b6c9286a MM |
12697 | return 4; |
12698 | default: | |
12699 | return 1; | |
12700 | } | |
12701 | } | |
12702 | ||
be12c2b0 VM |
12703 | /* Return how many instructions to look ahead for better insn |
12704 | scheduling. */ | |
12705 | ||
12706 | static int | |
12707 | rs6000_use_sched_lookahead () | |
12708 | { | |
12709 | if (rs6000_cpu_attr == CPU_PPC8540) | |
12710 | return 4; | |
12711 | return 0; | |
12712 | } | |
12713 | ||
b6c9286a | 12714 | \f |
b6c9286a MM |
12715 | /* Length in units of the trampoline for entering a nested function. */ |
12716 | ||
12717 | int | |
12718 | rs6000_trampoline_size () | |
12719 | { | |
12720 | int ret = 0; | |
12721 | ||
12722 | switch (DEFAULT_ABI) | |
12723 | { | |
12724 | default: | |
12725 | abort (); | |
12726 | ||
12727 | case ABI_AIX: | |
8f802bfb | 12728 | ret = (TARGET_32BIT) ? 12 : 24; |
b6c9286a MM |
12729 | break; |
12730 | ||
4dabc42d | 12731 | case ABI_DARWIN: |
b6c9286a | 12732 | case ABI_V4: |
03a7e1a5 | 12733 | ret = (TARGET_32BIT) ? 40 : 48; |
b6c9286a | 12734 | break; |
b6c9286a MM |
12735 | } |
12736 | ||
12737 | return ret; | |
12738 | } | |
12739 | ||
12740 | /* Emit RTL insns to initialize the variable parts of a trampoline. | |
12741 | FNADDR is an RTX for the address of the function's pure code. | |
12742 | CXT is an RTX for the static chain value for the function. */ | |
12743 | ||
12744 | void | |
12745 | rs6000_initialize_trampoline (addr, fnaddr, cxt) | |
12746 | rtx addr; | |
12747 | rtx fnaddr; | |
12748 | rtx cxt; | |
12749 | { | |
ac2a93a1 | 12750 | enum machine_mode pmode = Pmode; |
8bd04c56 MM |
12751 | int regsize = (TARGET_32BIT) ? 4 : 8; |
12752 | rtx ctx_reg = force_reg (pmode, cxt); | |
b6c9286a MM |
12753 | |
12754 | switch (DEFAULT_ABI) | |
12755 | { | |
12756 | default: | |
12757 | abort (); | |
12758 | ||
8bd04c56 | 12759 | /* Macros to shorten the code expansions below. */ |
39403d82 | 12760 | #define MEM_DEREF(addr) gen_rtx_MEM (pmode, memory_address (pmode, addr)) |
c5c76735 JL |
12761 | #define MEM_PLUS(addr,offset) \ |
12762 | gen_rtx_MEM (pmode, memory_address (pmode, plus_constant (addr, offset))) | |
7c59dc5d | 12763 | |
b6c9286a MM |
12764 | /* Under AIX, just build the 3 word function descriptor */ |
12765 | case ABI_AIX: | |
8bd04c56 MM |
12766 | { |
12767 | rtx fn_reg = gen_reg_rtx (pmode); | |
12768 | rtx toc_reg = gen_reg_rtx (pmode); | |
12769 | emit_move_insn (fn_reg, MEM_DEREF (fnaddr)); | |
1cb18e3c | 12770 | emit_move_insn (toc_reg, MEM_PLUS (fnaddr, regsize)); |
8bd04c56 MM |
12771 | emit_move_insn (MEM_DEREF (addr), fn_reg); |
12772 | emit_move_insn (MEM_PLUS (addr, regsize), toc_reg); | |
12773 | emit_move_insn (MEM_PLUS (addr, 2*regsize), ctx_reg); | |
12774 | } | |
b6c9286a MM |
12775 | break; |
12776 | ||
4dabc42d TC |
12777 | /* Under V.4/eabi/darwin, __trampoline_setup does the real work. */ |
12778 | case ABI_DARWIN: | |
b6c9286a | 12779 | case ABI_V4: |
39403d82 | 12780 | emit_library_call (gen_rtx_SYMBOL_REF (SImode, "__trampoline_setup"), |
eaf1bcf1 MM |
12781 | FALSE, VOIDmode, 4, |
12782 | addr, pmode, | |
12783 | GEN_INT (rs6000_trampoline_size ()), SImode, | |
12784 | fnaddr, pmode, | |
12785 | ctx_reg, pmode); | |
b6c9286a | 12786 | break; |
b6c9286a MM |
12787 | } |
12788 | ||
12789 | return; | |
12790 | } | |
7509c759 MM |
12791 | |
12792 | \f | |
91d231cb | 12793 | /* Table of valid machine attributes. */ |
a4f6c312 | 12794 | |
91d231cb | 12795 | const struct attribute_spec rs6000_attribute_table[] = |
7509c759 | 12796 | { |
91d231cb | 12797 | /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */ |
a5c76ee6 ZW |
12798 | { "longcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute }, |
12799 | { "shortcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute }, | |
12800 | { NULL, 0, 0, false, false, false, NULL } | |
91d231cb | 12801 | }; |
7509c759 | 12802 | |
a5c76ee6 ZW |
12803 | /* Handle a "longcall" or "shortcall" attribute; arguments as in |
12804 | struct attribute_spec.handler. */ | |
a4f6c312 | 12805 | |
91d231cb JM |
12806 | static tree |
12807 | rs6000_handle_longcall_attribute (node, name, args, flags, no_add_attrs) | |
12808 | tree *node; | |
12809 | tree name; | |
12810 | tree args ATTRIBUTE_UNUSED; | |
12811 | int flags ATTRIBUTE_UNUSED; | |
12812 | bool *no_add_attrs; | |
12813 | { | |
12814 | if (TREE_CODE (*node) != FUNCTION_TYPE | |
12815 | && TREE_CODE (*node) != FIELD_DECL | |
12816 | && TREE_CODE (*node) != TYPE_DECL) | |
12817 | { | |
12818 | warning ("`%s' attribute only applies to functions", | |
12819 | IDENTIFIER_POINTER (name)); | |
12820 | *no_add_attrs = true; | |
12821 | } | |
6a4cee5f | 12822 | |
91d231cb | 12823 | return NULL_TREE; |
7509c759 MM |
12824 | } |
12825 | ||
a5c76ee6 ZW |
12826 | /* Set longcall attributes on all functions declared when |
12827 | rs6000_default_long_calls is true. */ | |
12828 | static void | |
12829 | rs6000_set_default_type_attributes (type) | |
12830 | tree type; | |
12831 | { | |
12832 | if (rs6000_default_long_calls | |
12833 | && (TREE_CODE (type) == FUNCTION_TYPE | |
12834 | || TREE_CODE (type) == METHOD_TYPE)) | |
12835 | TYPE_ATTRIBUTES (type) = tree_cons (get_identifier ("longcall"), | |
12836 | NULL_TREE, | |
12837 | TYPE_ATTRIBUTES (type)); | |
12838 | } | |
12839 | ||
3cb999d8 DE |
12840 | /* Return a reference suitable for calling a function with the |
12841 | longcall attribute. */ | |
a4f6c312 | 12842 | |
6a4cee5f MM |
12843 | struct rtx_def * |
12844 | rs6000_longcall_ref (call_ref) | |
12845 | rtx call_ref; | |
12846 | { | |
d330fd93 | 12847 | const char *call_name; |
6a4cee5f MM |
12848 | tree node; |
12849 | ||
12850 | if (GET_CODE (call_ref) != SYMBOL_REF) | |
12851 | return call_ref; | |
12852 | ||
12853 | /* System V adds '.' to the internal name, so skip them. */ | |
12854 | call_name = XSTR (call_ref, 0); | |
12855 | if (*call_name == '.') | |
12856 | { | |
12857 | while (*call_name == '.') | |
12858 | call_name++; | |
12859 | ||
12860 | node = get_identifier (call_name); | |
39403d82 | 12861 | call_ref = gen_rtx_SYMBOL_REF (VOIDmode, IDENTIFIER_POINTER (node)); |
6a4cee5f MM |
12862 | } |
12863 | ||
12864 | return force_reg (Pmode, call_ref); | |
12865 | } | |
12866 | ||
7509c759 | 12867 | \f |
b64a1b53 RH |
12868 | #ifdef USING_ELFOS_H |
12869 | ||
7509c759 MM |
12870 | /* A C statement or statements to switch to the appropriate section |
12871 | for output of RTX in mode MODE. You can assume that RTX is some | |
12872 | kind of constant in RTL. The argument MODE is redundant except in | |
12873 | the case of a `const_int' rtx. Select the section by calling | |
12874 | `text_section' or one of the alternatives for other sections. | |
12875 | ||
12876 | Do not define this macro if you put all constants in the read-only | |
12877 | data section. */ | |
12878 | ||
b64a1b53 RH |
12879 | static void |
12880 | rs6000_elf_select_rtx_section (mode, x, align) | |
a9098fd0 | 12881 | enum machine_mode mode; |
7509c759 | 12882 | rtx x; |
b64a1b53 | 12883 | unsigned HOST_WIDE_INT align; |
7509c759 | 12884 | { |
a9098fd0 | 12885 | if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode)) |
7509c759 | 12886 | toc_section (); |
7509c759 | 12887 | else |
b64a1b53 | 12888 | default_elf_select_rtx_section (mode, x, align); |
7509c759 MM |
12889 | } |
12890 | ||
12891 | /* A C statement or statements to switch to the appropriate | |
12892 | section for output of DECL. DECL is either a `VAR_DECL' node | |
12893 | or a constant of some sort. RELOC indicates whether forming | |
12894 | the initial value of DECL requires link-time relocations. */ | |
12895 | ||
ae46c4e0 RH |
12896 | static void |
12897 | rs6000_elf_select_section (decl, reloc, align) | |
7509c759 MM |
12898 | tree decl; |
12899 | int reloc; | |
0e5dbd9b | 12900 | unsigned HOST_WIDE_INT align; |
7509c759 | 12901 | { |
f1384257 AM |
12902 | /* Pretend that we're always building for a shared library when |
12903 | ABI_AIX, because otherwise we end up with dynamic relocations | |
12904 | in read-only sections. This happens for function pointers, | |
12905 | references to vtables in typeinfo, and probably other cases. */ | |
0e5dbd9b DE |
12906 | default_elf_select_section_1 (decl, reloc, align, |
12907 | flag_pic || DEFAULT_ABI == ABI_AIX); | |
63019373 GK |
12908 | } |
12909 | ||
12910 | /* A C statement to build up a unique section name, expressed as a | |
12911 | STRING_CST node, and assign it to DECL_SECTION_NAME (decl). | |
12912 | RELOC indicates whether the initial value of EXP requires | |
12913 | link-time relocations. If you do not define this macro, GCC will use | |
12914 | the symbol name prefixed by `.' as the section name. Note - this | |
f5143c46 | 12915 | macro can now be called for uninitialized data items as well as |
4912a07c | 12916 | initialized data and functions. */ |
63019373 | 12917 | |
ae46c4e0 RH |
12918 | static void |
12919 | rs6000_elf_unique_section (decl, reloc) | |
63019373 GK |
12920 | tree decl; |
12921 | int reloc; | |
12922 | { | |
f1384257 AM |
12923 | /* As above, pretend that we're always building for a shared library |
12924 | when ABI_AIX, to avoid dynamic relocations in read-only sections. */ | |
0e5dbd9b DE |
12925 | default_unique_section_1 (decl, reloc, |
12926 | flag_pic || DEFAULT_ABI == ABI_AIX); | |
7509c759 | 12927 | } |
d9407988 | 12928 | \f |
d9407988 MM |
12929 | /* If we are referencing a function that is static or is known to be |
12930 | in this file, make the SYMBOL_REF special. We can use this to indicate | |
12931 | that we can branch to this function without emitting a no-op after the | |
9ebbca7d | 12932 | call. For real AIX calling sequences, we also replace the |
d9407988 MM |
12933 | function name with the real name (1 or 2 leading .'s), rather than |
12934 | the function descriptor name. This saves a lot of overriding code | |
a260abc9 | 12935 | to read the prefixes. */ |
d9407988 | 12936 | |
fb49053f RH |
12937 | static void |
12938 | rs6000_elf_encode_section_info (decl, first) | |
d9407988 | 12939 | tree decl; |
b2003250 | 12940 | int first; |
d9407988 | 12941 | { |
b2003250 RH |
12942 | if (!first) |
12943 | return; | |
12944 | ||
d9407988 MM |
12945 | if (TREE_CODE (decl) == FUNCTION_DECL) |
12946 | { | |
12947 | rtx sym_ref = XEXP (DECL_RTL (decl), 0); | |
b629ba0c | 12948 | if ((*targetm.binds_local_p) (decl)) |
d9407988 MM |
12949 | SYMBOL_REF_FLAG (sym_ref) = 1; |
12950 | ||
f1384257 | 12951 | if (!TARGET_AIX && DEFAULT_ABI == ABI_AIX) |
d9407988 | 12952 | { |
ff669a6c RH |
12953 | size_t len1 = (DEFAULT_ABI == ABI_AIX) ? 1 : 2; |
12954 | size_t len2 = strlen (XSTR (sym_ref, 0)); | |
520a57c8 | 12955 | char *str = alloca (len1 + len2 + 1); |
ff669a6c RH |
12956 | str[0] = '.'; |
12957 | str[1] = '.'; | |
12958 | memcpy (str + len1, XSTR (sym_ref, 0), len2 + 1); | |
12959 | ||
520a57c8 | 12960 | XSTR (sym_ref, 0) = ggc_alloc_string (str, len1 + len2); |
d9407988 MM |
12961 | } |
12962 | } | |
12963 | else if (rs6000_sdata != SDATA_NONE | |
f607bc57 | 12964 | && DEFAULT_ABI == ABI_V4 |
d9407988 MM |
12965 | && TREE_CODE (decl) == VAR_DECL) |
12966 | { | |
c40e5172 | 12967 | rtx sym_ref = XEXP (DECL_RTL (decl), 0); |
d9407988 MM |
12968 | int size = int_size_in_bytes (TREE_TYPE (decl)); |
12969 | tree section_name = DECL_SECTION_NAME (decl); | |
d330fd93 | 12970 | const char *name = (char *)0; |
d9407988 MM |
12971 | int len = 0; |
12972 | ||
c40e5172 JS |
12973 | if ((*targetm.binds_local_p) (decl)) |
12974 | SYMBOL_REF_FLAG (sym_ref) = 1; | |
12975 | ||
d9407988 MM |
12976 | if (section_name) |
12977 | { | |
12978 | if (TREE_CODE (section_name) == STRING_CST) | |
12979 | { | |
12980 | name = TREE_STRING_POINTER (section_name); | |
12981 | len = TREE_STRING_LENGTH (section_name); | |
12982 | } | |
12983 | else | |
12984 | abort (); | |
12985 | } | |
12986 | ||
2792d578 DE |
12987 | if (name |
12988 | ? ((len == sizeof (".sdata") - 1 | |
12989 | && strcmp (name, ".sdata") == 0) | |
12990 | || (len == sizeof (".sdata2") - 1 | |
12991 | && strcmp (name, ".sdata2") == 0) | |
12992 | || (len == sizeof (".sbss") - 1 | |
12993 | && strcmp (name, ".sbss") == 0) | |
12994 | || (len == sizeof (".sbss2") - 1 | |
12995 | && strcmp (name, ".sbss2") == 0) | |
12996 | || (len == sizeof (".PPC.EMB.sdata0") - 1 | |
12997 | && strcmp (name, ".PPC.EMB.sdata0") == 0) | |
12998 | || (len == sizeof (".PPC.EMB.sbss0") - 1 | |
12999 | && strcmp (name, ".PPC.EMB.sbss0") == 0)) | |
13000 | : (size > 0 && size <= g_switch_value)) | |
d9407988 | 13001 | { |
ff669a6c | 13002 | size_t len = strlen (XSTR (sym_ref, 0)); |
88c1e412 | 13003 | char *str = alloca (len + 2); |
ff669a6c | 13004 | |
ff669a6c RH |
13005 | str[0] = '@'; |
13006 | memcpy (str + 1, XSTR (sym_ref, 0), len + 1); | |
88c1e412 | 13007 | XSTR (sym_ref, 0) = ggc_alloc_string (str, len + 1); |
d9407988 MM |
13008 | } |
13009 | } | |
13010 | } | |
13011 | ||
772c5265 RH |
13012 | static const char * |
13013 | rs6000_elf_strip_name_encoding (str) | |
13014 | const char *str; | |
13015 | { | |
13016 | while (*str == '*' || *str == '@') | |
13017 | str++; | |
13018 | return str; | |
13019 | } | |
13020 | ||
0e5dbd9b DE |
13021 | static bool |
13022 | rs6000_elf_in_small_data_p (decl) | |
13023 | tree decl; | |
13024 | { | |
13025 | if (rs6000_sdata == SDATA_NONE) | |
13026 | return false; | |
13027 | ||
13028 | if (TREE_CODE (decl) == VAR_DECL && DECL_SECTION_NAME (decl)) | |
13029 | { | |
13030 | const char *section = TREE_STRING_POINTER (DECL_SECTION_NAME (decl)); | |
13031 | if (strcmp (section, ".sdata") == 0 | |
13032 | || strcmp (section, ".sdata2") == 0 | |
13033 | || strcmp (section, ".sbss") == 0) | |
13034 | return true; | |
13035 | } | |
13036 | else | |
13037 | { | |
13038 | HOST_WIDE_INT size = int_size_in_bytes (TREE_TYPE (decl)); | |
13039 | ||
13040 | if (size > 0 | |
13041 | && size <= g_switch_value | |
13042 | && (rs6000_sdata != SDATA_DATA || TREE_PUBLIC (decl))) | |
13043 | return true; | |
13044 | } | |
13045 | ||
13046 | return false; | |
13047 | } | |
13048 | ||
b91da81f | 13049 | #endif /* USING_ELFOS_H */ |
000034eb | 13050 | |
a6c2a102 | 13051 | \f |
000034eb | 13052 | /* Return a REG that occurs in ADDR with coefficient 1. |
02441cd6 JL |
13053 | ADDR can be effectively incremented by incrementing REG. |
13054 | ||
13055 | r0 is special and we must not select it as an address | |
13056 | register by this routine since our caller will try to | |
13057 | increment the returned register via an "la" instruction. */ | |
000034eb DE |
13058 | |
13059 | struct rtx_def * | |
13060 | find_addr_reg (addr) | |
13061 | rtx addr; | |
13062 | { | |
13063 | while (GET_CODE (addr) == PLUS) | |
13064 | { | |
02441cd6 JL |
13065 | if (GET_CODE (XEXP (addr, 0)) == REG |
13066 | && REGNO (XEXP (addr, 0)) != 0) | |
000034eb | 13067 | addr = XEXP (addr, 0); |
02441cd6 JL |
13068 | else if (GET_CODE (XEXP (addr, 1)) == REG |
13069 | && REGNO (XEXP (addr, 1)) != 0) | |
000034eb DE |
13070 | addr = XEXP (addr, 1); |
13071 | else if (CONSTANT_P (XEXP (addr, 0))) | |
13072 | addr = XEXP (addr, 1); | |
13073 | else if (CONSTANT_P (XEXP (addr, 1))) | |
13074 | addr = XEXP (addr, 0); | |
13075 | else | |
13076 | abort (); | |
13077 | } | |
02441cd6 | 13078 | if (GET_CODE (addr) == REG && REGNO (addr) != 0) |
000034eb DE |
13079 | return addr; |
13080 | abort (); | |
13081 | } | |
13082 | ||
a6c2a102 DE |
13083 | void |
13084 | rs6000_fatal_bad_address (op) | |
13085 | rtx op; | |
13086 | { | |
13087 | fatal_insn ("bad address", op); | |
13088 | } | |
c8023011 | 13089 | |
ee890fe2 SS |
13090 | #if TARGET_MACHO |
13091 | ||
13092 | #if 0 | |
13093 | /* Returns 1 if OP is either a symbol reference or a sum of a symbol | |
13094 | reference and a constant. */ | |
13095 | ||
13096 | int | |
13097 | symbolic_operand (op) | |
592696dd | 13098 | rtx op; |
ee890fe2 SS |
13099 | { |
13100 | switch (GET_CODE (op)) | |
13101 | { | |
13102 | case SYMBOL_REF: | |
13103 | case LABEL_REF: | |
13104 | return 1; | |
13105 | case CONST: | |
13106 | op = XEXP (op, 0); | |
13107 | return (GET_CODE (op) == SYMBOL_REF || | |
13108 | (GET_CODE (XEXP (op, 0)) == SYMBOL_REF | |
13109 | || GET_CODE (XEXP (op, 0)) == LABEL_REF) | |
13110 | && GET_CODE (XEXP (op, 1)) == CONST_INT); | |
13111 | default: | |
13112 | return 0; | |
13113 | } | |
c8023011 | 13114 | } |
ee890fe2 SS |
13115 | #endif |
13116 | ||
13117 | #ifdef RS6000_LONG_BRANCH | |
13118 | ||
13119 | static tree stub_list = 0; | |
13120 | ||
13121 | /* ADD_COMPILER_STUB adds the compiler generated stub for handling | |
13122 | procedure calls to the linked list. */ | |
13123 | ||
13124 | void | |
13125 | add_compiler_stub (label_name, function_name, line_number) | |
13126 | tree label_name; | |
13127 | tree function_name; | |
13128 | int line_number; | |
13129 | { | |
13130 | tree stub = build_tree_list (function_name, label_name); | |
13131 | TREE_TYPE (stub) = build_int_2 (line_number, 0); | |
13132 | TREE_CHAIN (stub) = stub_list; | |
13133 | stub_list = stub; | |
13134 | } | |
13135 | ||
13136 | #define STUB_LABEL_NAME(STUB) TREE_VALUE (STUB) | |
13137 | #define STUB_FUNCTION_NAME(STUB) TREE_PURPOSE (STUB) | |
13138 | #define STUB_LINE_NUMBER(STUB) TREE_INT_CST_LOW (TREE_TYPE (STUB)) | |
13139 | ||
a4f6c312 SS |
13140 | /* OUTPUT_COMPILER_STUB outputs the compiler generated stub for |
13141 | handling procedure calls from the linked list and initializes the | |
13142 | linked list. */ | |
ee890fe2 | 13143 | |
a4f6c312 SS |
13144 | void |
13145 | output_compiler_stub () | |
ee890fe2 SS |
13146 | { |
13147 | char tmp_buf[256]; | |
13148 | char label_buf[256]; | |
308c142a | 13149 | tree stub; |
ee890fe2 SS |
13150 | |
13151 | if (!flag_pic) | |
13152 | for (stub = stub_list; stub; stub = TREE_CHAIN (stub)) | |
13153 | { | |
13154 | fprintf (asm_out_file, | |
13155 | "%s:\n", IDENTIFIER_POINTER(STUB_LABEL_NAME(stub))); | |
13156 | ||
13157 | #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO) | |
13158 | if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG) | |
13159 | fprintf (asm_out_file, "\t.stabd 68,0,%d\n", STUB_LINE_NUMBER(stub)); | |
13160 | #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */ | |
13161 | ||
13162 | if (IDENTIFIER_POINTER (STUB_FUNCTION_NAME (stub))[0] == '*') | |
13163 | strcpy (label_buf, | |
13164 | IDENTIFIER_POINTER (STUB_FUNCTION_NAME (stub))+1); | |
13165 | else | |
13166 | { | |
13167 | label_buf[0] = '_'; | |
13168 | strcpy (label_buf+1, | |
13169 | IDENTIFIER_POINTER (STUB_FUNCTION_NAME (stub))); | |
13170 | } | |
13171 | ||
13172 | strcpy (tmp_buf, "lis r12,hi16("); | |
13173 | strcat (tmp_buf, label_buf); | |
13174 | strcat (tmp_buf, ")\n\tori r12,r12,lo16("); | |
13175 | strcat (tmp_buf, label_buf); | |
13176 | strcat (tmp_buf, ")\n\tmtctr r12\n\tbctr"); | |
13177 | output_asm_insn (tmp_buf, 0); | |
13178 | ||
13179 | #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO) | |
13180 | if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG) | |
13181 | fprintf(asm_out_file, "\t.stabd 68,0,%d\n", STUB_LINE_NUMBER (stub)); | |
13182 | #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */ | |
13183 | } | |
13184 | ||
13185 | stub_list = 0; | |
13186 | } | |
13187 | ||
13188 | /* NO_PREVIOUS_DEF checks in the link list whether the function name is | |
13189 | already there or not. */ | |
13190 | ||
a4f6c312 SS |
13191 | int |
13192 | no_previous_def (function_name) | |
ee890fe2 SS |
13193 | tree function_name; |
13194 | { | |
13195 | tree stub; | |
13196 | for (stub = stub_list; stub; stub = TREE_CHAIN (stub)) | |
13197 | if (function_name == STUB_FUNCTION_NAME (stub)) | |
13198 | return 0; | |
13199 | return 1; | |
13200 | } | |
13201 | ||
13202 | /* GET_PREV_LABEL gets the label name from the previous definition of | |
13203 | the function. */ | |
13204 | ||
a4f6c312 SS |
13205 | tree |
13206 | get_prev_label (function_name) | |
ee890fe2 SS |
13207 | tree function_name; |
13208 | { | |
13209 | tree stub; | |
13210 | for (stub = stub_list; stub; stub = TREE_CHAIN (stub)) | |
13211 | if (function_name == STUB_FUNCTION_NAME (stub)) | |
13212 | return STUB_LABEL_NAME (stub); | |
13213 | return 0; | |
13214 | } | |
13215 | ||
13216 | /* INSN is either a function call or a millicode call. It may have an | |
13217 | unconditional jump in its delay slot. | |
13218 | ||
13219 | CALL_DEST is the routine we are calling. */ | |
13220 | ||
13221 | char * | |
13222 | output_call (insn, call_dest, operand_number) | |
13223 | rtx insn; | |
13224 | rtx call_dest; | |
13225 | int operand_number; | |
13226 | { | |
13227 | static char buf[256]; | |
13228 | if (GET_CODE (call_dest) == SYMBOL_REF && TARGET_LONG_BRANCH && !flag_pic) | |
13229 | { | |
13230 | tree labelname; | |
13231 | tree funname = get_identifier (XSTR (call_dest, 0)); | |
13232 | ||
13233 | if (no_previous_def (funname)) | |
13234 | { | |
308c142a | 13235 | int line_number = 0; |
ee890fe2 SS |
13236 | rtx label_rtx = gen_label_rtx (); |
13237 | char *label_buf, temp_buf[256]; | |
13238 | ASM_GENERATE_INTERNAL_LABEL (temp_buf, "L", | |
13239 | CODE_LABEL_NUMBER (label_rtx)); | |
13240 | label_buf = temp_buf[0] == '*' ? temp_buf + 1 : temp_buf; | |
13241 | labelname = get_identifier (label_buf); | |
13242 | for (; insn && GET_CODE (insn) != NOTE; insn = PREV_INSN (insn)); | |
13243 | if (insn) | |
13244 | line_number = NOTE_LINE_NUMBER (insn); | |
13245 | add_compiler_stub (labelname, funname, line_number); | |
13246 | } | |
13247 | else | |
13248 | labelname = get_prev_label (funname); | |
13249 | ||
13250 | sprintf (buf, "jbsr %%z%d,%.246s", | |
13251 | operand_number, IDENTIFIER_POINTER (labelname)); | |
13252 | return buf; | |
13253 | } | |
13254 | else | |
13255 | { | |
13256 | sprintf (buf, "bl %%z%d", operand_number); | |
13257 | return buf; | |
13258 | } | |
13259 | } | |
13260 | ||
13261 | #endif /* RS6000_LONG_BRANCH */ | |
13262 | ||
13263 | #define GEN_LOCAL_LABEL_FOR_SYMBOL(BUF,SYMBOL,LENGTH,N) \ | |
13264 | do { \ | |
83182544 | 13265 | const char *const symbol_ = (SYMBOL); \ |
ee890fe2 SS |
13266 | char *buffer_ = (BUF); \ |
13267 | if (symbol_[0] == '"') \ | |
13268 | { \ | |
13269 | sprintf(buffer_, "\"L%d$%s", (N), symbol_+1); \ | |
13270 | } \ | |
13271 | else if (name_needs_quotes(symbol_)) \ | |
13272 | { \ | |
13273 | sprintf(buffer_, "\"L%d$%s\"", (N), symbol_); \ | |
13274 | } \ | |
13275 | else \ | |
13276 | { \ | |
13277 | sprintf(buffer_, "L%d$%s", (N), symbol_); \ | |
13278 | } \ | |
13279 | } while (0) | |
13280 | ||
13281 | ||
13282 | /* Generate PIC and indirect symbol stubs. */ | |
13283 | ||
13284 | void | |
13285 | machopic_output_stub (file, symb, stub) | |
13286 | FILE *file; | |
13287 | const char *symb, *stub; | |
13288 | { | |
13289 | unsigned int length; | |
a4f6c312 SS |
13290 | char *symbol_name, *lazy_ptr_name; |
13291 | char *local_label_0; | |
ee890fe2 SS |
13292 | static int label = 0; |
13293 | ||
df56a27f | 13294 | /* Lose our funky encoding stuff so it doesn't contaminate the stub. */ |
772c5265 | 13295 | symb = (*targetm.strip_name_encoding) (symb); |
df56a27f | 13296 | |
ee890fe2 SS |
13297 | label += 1; |
13298 | ||
ee890fe2 SS |
13299 | length = strlen (symb); |
13300 | symbol_name = alloca (length + 32); | |
13301 | GEN_SYMBOL_NAME_FOR_SYMBOL (symbol_name, symb, length); | |
13302 | ||
13303 | lazy_ptr_name = alloca (length + 32); | |
13304 | GEN_LAZY_PTR_NAME_FOR_SYMBOL (lazy_ptr_name, symb, length); | |
13305 | ||
13306 | local_label_0 = alloca (length + 32); | |
13307 | GEN_LOCAL_LABEL_FOR_SYMBOL (local_label_0, symb, length, 0); | |
13308 | ||
ee890fe2 | 13309 | if (flag_pic == 2) |
d3c300d2 | 13310 | machopic_picsymbol_stub1_section (); |
ee890fe2 | 13311 | else |
d3c300d2 DJ |
13312 | machopic_symbol_stub1_section (); |
13313 | fprintf (file, "\t.align 2\n"); | |
ee890fe2 SS |
13314 | |
13315 | fprintf (file, "%s:\n", stub); | |
13316 | fprintf (file, "\t.indirect_symbol %s\n", symbol_name); | |
13317 | ||
13318 | if (flag_pic == 2) | |
13319 | { | |
13320 | fprintf (file, "\tmflr r0\n"); | |
13321 | fprintf (file, "\tbcl 20,31,%s\n", local_label_0); | |
13322 | fprintf (file, "%s:\n\tmflr r11\n", local_label_0); | |
13323 | fprintf (file, "\taddis r11,r11,ha16(%s-%s)\n", | |
13324 | lazy_ptr_name, local_label_0); | |
13325 | fprintf (file, "\tmtlr r0\n"); | |
d3c300d2 | 13326 | fprintf (file, "\tlwzu r12,lo16(%s-%s)(r11)\n", |
ee890fe2 SS |
13327 | lazy_ptr_name, local_label_0); |
13328 | fprintf (file, "\tmtctr r12\n"); | |
ee890fe2 SS |
13329 | fprintf (file, "\tbctr\n"); |
13330 | } | |
13331 | else | |
ab82a49f AP |
13332 | { |
13333 | fprintf (file, "\tlis r11,ha16(%s)\n", lazy_ptr_name); | |
13334 | fprintf (file, "\tlwzu r12,lo16(%s)(r11)\n", lazy_ptr_name); | |
13335 | fprintf (file, "\tmtctr r12\n"); | |
13336 | fprintf (file, "\tbctr\n"); | |
13337 | } | |
ee890fe2 SS |
13338 | |
13339 | machopic_lazy_symbol_ptr_section (); | |
13340 | fprintf (file, "%s:\n", lazy_ptr_name); | |
13341 | fprintf (file, "\t.indirect_symbol %s\n", symbol_name); | |
13342 | fprintf (file, "\t.long dyld_stub_binding_helper\n"); | |
13343 | } | |
13344 | ||
13345 | /* Legitimize PIC addresses. If the address is already | |
13346 | position-independent, we return ORIG. Newly generated | |
13347 | position-independent addresses go into a reg. This is REG if non | |
13348 | zero, otherwise we allocate register(s) as necessary. */ | |
13349 | ||
c859cda6 | 13350 | #define SMALL_INT(X) ((unsigned) (INTVAL(X) + 0x8000) < 0x10000) |
ee890fe2 SS |
13351 | |
13352 | rtx | |
13353 | rs6000_machopic_legitimize_pic_address (orig, mode, reg) | |
13354 | rtx orig; | |
13355 | enum machine_mode mode; | |
13356 | rtx reg; | |
13357 | { | |
13358 | rtx base, offset; | |
13359 | ||
13360 | if (reg == NULL && ! reload_in_progress && ! reload_completed) | |
13361 | reg = gen_reg_rtx (Pmode); | |
13362 | ||
13363 | if (GET_CODE (orig) == CONST) | |
13364 | { | |
13365 | if (GET_CODE (XEXP (orig, 0)) == PLUS | |
13366 | && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx) | |
13367 | return orig; | |
13368 | ||
13369 | if (GET_CODE (XEXP (orig, 0)) == PLUS) | |
13370 | { | |
a4f6c312 SS |
13371 | base = |
13372 | rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 0), | |
13373 | Pmode, reg); | |
13374 | offset = | |
13375 | rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 1), | |
13376 | Pmode, reg); | |
ee890fe2 SS |
13377 | } |
13378 | else | |
13379 | abort (); | |
13380 | ||
13381 | if (GET_CODE (offset) == CONST_INT) | |
13382 | { | |
13383 | if (SMALL_INT (offset)) | |
ed8908e7 | 13384 | return plus_constant (base, INTVAL (offset)); |
ee890fe2 SS |
13385 | else if (! reload_in_progress && ! reload_completed) |
13386 | offset = force_reg (Pmode, offset); | |
13387 | else | |
c859cda6 DJ |
13388 | { |
13389 | rtx mem = force_const_mem (Pmode, orig); | |
13390 | return machopic_legitimize_pic_address (mem, Pmode, reg); | |
13391 | } | |
ee890fe2 SS |
13392 | } |
13393 | return gen_rtx (PLUS, Pmode, base, offset); | |
13394 | } | |
13395 | ||
13396 | /* Fall back on generic machopic code. */ | |
13397 | return machopic_legitimize_pic_address (orig, mode, reg); | |
13398 | } | |
13399 | ||
13400 | /* This is just a placeholder to make linking work without having to | |
13401 | add this to the generic Darwin EXTRA_SECTIONS. If -mcall-aix is | |
13402 | ever needed for Darwin (not too likely!) this would have to get a | |
13403 | real definition. */ | |
13404 | ||
13405 | void | |
13406 | toc_section () | |
13407 | { | |
13408 | } | |
13409 | ||
13410 | #endif /* TARGET_MACHO */ | |
7c262518 RH |
13411 | |
13412 | #if TARGET_ELF | |
13413 | static unsigned int | |
13414 | rs6000_elf_section_type_flags (decl, name, reloc) | |
13415 | tree decl; | |
13416 | const char *name; | |
13417 | int reloc; | |
13418 | { | |
5add3202 DE |
13419 | unsigned int flags |
13420 | = default_section_type_flags_1 (decl, name, reloc, | |
13421 | flag_pic || DEFAULT_ABI == ABI_AIX); | |
7c262518 | 13422 | |
270fc29b RH |
13423 | if (TARGET_RELOCATABLE) |
13424 | flags |= SECTION_WRITE; | |
7c262518 | 13425 | |
d0101753 | 13426 | return flags; |
7c262518 | 13427 | } |
d9f6800d RH |
13428 | |
13429 | /* Record an element in the table of global constructors. SYMBOL is | |
13430 | a SYMBOL_REF of the function to be called; PRIORITY is a number | |
13431 | between 0 and MAX_INIT_PRIORITY. | |
13432 | ||
13433 | This differs from default_named_section_asm_out_constructor in | |
13434 | that we have special handling for -mrelocatable. */ | |
13435 | ||
13436 | static void | |
13437 | rs6000_elf_asm_out_constructor (symbol, priority) | |
13438 | rtx symbol; | |
13439 | int priority; | |
13440 | { | |
13441 | const char *section = ".ctors"; | |
13442 | char buf[16]; | |
13443 | ||
13444 | if (priority != DEFAULT_INIT_PRIORITY) | |
13445 | { | |
13446 | sprintf (buf, ".ctors.%.5u", | |
13447 | /* Invert the numbering so the linker puts us in the proper | |
13448 | order; constructors are run from right to left, and the | |
13449 | linker sorts in increasing order. */ | |
13450 | MAX_INIT_PRIORITY - priority); | |
13451 | section = buf; | |
13452 | } | |
13453 | ||
715bdd29 RH |
13454 | named_section_flags (section, SECTION_WRITE); |
13455 | assemble_align (POINTER_SIZE); | |
d9f6800d RH |
13456 | |
13457 | if (TARGET_RELOCATABLE) | |
13458 | { | |
13459 | fputs ("\t.long (", asm_out_file); | |
13460 | output_addr_const (asm_out_file, symbol); | |
13461 | fputs (")@fixup\n", asm_out_file); | |
13462 | } | |
13463 | else | |
c8af3574 | 13464 | assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1); |
d9f6800d RH |
13465 | } |
13466 | ||
13467 | static void | |
13468 | rs6000_elf_asm_out_destructor (symbol, priority) | |
13469 | rtx symbol; | |
13470 | int priority; | |
13471 | { | |
13472 | const char *section = ".dtors"; | |
13473 | char buf[16]; | |
13474 | ||
13475 | if (priority != DEFAULT_INIT_PRIORITY) | |
13476 | { | |
13477 | sprintf (buf, ".dtors.%.5u", | |
13478 | /* Invert the numbering so the linker puts us in the proper | |
13479 | order; constructors are run from right to left, and the | |
13480 | linker sorts in increasing order. */ | |
13481 | MAX_INIT_PRIORITY - priority); | |
13482 | section = buf; | |
13483 | } | |
13484 | ||
715bdd29 RH |
13485 | named_section_flags (section, SECTION_WRITE); |
13486 | assemble_align (POINTER_SIZE); | |
d9f6800d RH |
13487 | |
13488 | if (TARGET_RELOCATABLE) | |
13489 | { | |
13490 | fputs ("\t.long (", asm_out_file); | |
13491 | output_addr_const (asm_out_file, symbol); | |
13492 | fputs (")@fixup\n", asm_out_file); | |
13493 | } | |
13494 | else | |
c8af3574 | 13495 | assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1); |
d9f6800d | 13496 | } |
7c262518 RH |
13497 | #endif |
13498 | ||
cbaaba19 | 13499 | #if TARGET_XCOFF |
7c262518 | 13500 | static void |
b275d088 DE |
13501 | rs6000_xcoff_asm_globalize_label (stream, name) |
13502 | FILE *stream; | |
13503 | const char *name; | |
13504 | { | |
13505 | fputs (GLOBAL_ASM_OP, stream); | |
13506 | RS6000_OUTPUT_BASENAME (stream, name); | |
13507 | putc ('\n', stream); | |
13508 | } | |
13509 | ||
13510 | static void | |
13511 | rs6000_xcoff_asm_named_section (name, flags) | |
7c262518 | 13512 | const char *name; |
0e5dbd9b | 13513 | unsigned int flags; |
7c262518 | 13514 | { |
0e5dbd9b DE |
13515 | int smclass; |
13516 | static const char * const suffix[3] = { "PR", "RO", "RW" }; | |
13517 | ||
13518 | if (flags & SECTION_CODE) | |
13519 | smclass = 0; | |
13520 | else if (flags & SECTION_WRITE) | |
13521 | smclass = 2; | |
13522 | else | |
13523 | smclass = 1; | |
13524 | ||
5b5198f7 | 13525 | fprintf (asm_out_file, "\t.csect %s%s[%s],%u\n", |
0e5dbd9b | 13526 | (flags & SECTION_CODE) ? "." : "", |
5b5198f7 | 13527 | name, suffix[smclass], flags & SECTION_ENTSIZE); |
7c262518 | 13528 | } |
ae46c4e0 RH |
13529 | |
13530 | static void | |
0e5dbd9b DE |
13531 | rs6000_xcoff_select_section (decl, reloc, align) |
13532 | tree decl; | |
ae46c4e0 RH |
13533 | int reloc; |
13534 | unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED; | |
13535 | { | |
5add3202 | 13536 | if (decl_readonly_section_1 (decl, reloc, 1)) |
ae46c4e0 | 13537 | { |
0e5dbd9b | 13538 | if (TREE_PUBLIC (decl)) |
ae46c4e0 RH |
13539 | read_only_data_section (); |
13540 | else | |
13541 | read_only_private_data_section (); | |
13542 | } | |
13543 | else | |
13544 | { | |
0e5dbd9b | 13545 | if (TREE_PUBLIC (decl)) |
ae46c4e0 RH |
13546 | data_section (); |
13547 | else | |
13548 | private_data_section (); | |
13549 | } | |
13550 | } | |
13551 | ||
13552 | static void | |
13553 | rs6000_xcoff_unique_section (decl, reloc) | |
13554 | tree decl; | |
772c5265 | 13555 | int reloc ATTRIBUTE_UNUSED; |
ae46c4e0 RH |
13556 | { |
13557 | const char *name; | |
ae46c4e0 | 13558 | |
5b5198f7 DE |
13559 | /* Use select_section for private and uninitialized data. */ |
13560 | if (!TREE_PUBLIC (decl) | |
13561 | || DECL_COMMON (decl) | |
0e5dbd9b DE |
13562 | || DECL_INITIAL (decl) == NULL_TREE |
13563 | || DECL_INITIAL (decl) == error_mark_node | |
13564 | || (flag_zero_initialized_in_bss | |
13565 | && initializer_zerop (DECL_INITIAL (decl)))) | |
13566 | return; | |
13567 | ||
13568 | name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl)); | |
13569 | name = (*targetm.strip_name_encoding) (name); | |
13570 | DECL_SECTION_NAME (decl) = build_string (strlen (name), name); | |
ae46c4e0 | 13571 | } |
b64a1b53 | 13572 | |
fb49053f RH |
13573 | /* Select section for constant in constant pool. |
13574 | ||
13575 | On RS/6000, all constants are in the private read-only data area. | |
13576 | However, if this is being placed in the TOC it must be output as a | |
13577 | toc entry. */ | |
13578 | ||
b64a1b53 RH |
13579 | static void |
13580 | rs6000_xcoff_select_rtx_section (mode, x, align) | |
13581 | enum machine_mode mode; | |
13582 | rtx x; | |
13583 | unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED; | |
13584 | { | |
13585 | if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode)) | |
13586 | toc_section (); | |
13587 | else | |
13588 | read_only_private_data_section (); | |
13589 | } | |
772c5265 RH |
13590 | |
13591 | /* Remove any trailing [DS] or the like from the symbol name. */ | |
13592 | ||
13593 | static const char * | |
13594 | rs6000_xcoff_strip_name_encoding (name) | |
13595 | const char *name; | |
13596 | { | |
13597 | size_t len; | |
13598 | if (*name == '*') | |
13599 | name++; | |
13600 | len = strlen (name); | |
13601 | if (name[len - 1] == ']') | |
13602 | return ggc_alloc_string (name, len - 4); | |
13603 | else | |
13604 | return name; | |
13605 | } | |
13606 | ||
5add3202 DE |
13607 | /* Section attributes. AIX is always PIC. */ |
13608 | ||
13609 | static unsigned int | |
13610 | rs6000_xcoff_section_type_flags (decl, name, reloc) | |
13611 | tree decl; | |
13612 | const char *name; | |
13613 | int reloc; | |
13614 | { | |
5b5198f7 DE |
13615 | unsigned int align; |
13616 | unsigned int flags = default_section_type_flags_1 (decl, name, reloc, 1); | |
13617 | ||
13618 | /* Align to at least UNIT size. */ | |
13619 | if (flags & SECTION_CODE) | |
13620 | align = MIN_UNITS_PER_WORD; | |
13621 | else | |
13622 | /* Increase alignment of large objects if not already stricter. */ | |
13623 | align = MAX ((DECL_ALIGN (decl) / BITS_PER_UNIT), | |
13624 | int_size_in_bytes (TREE_TYPE (decl)) > MIN_UNITS_PER_WORD | |
13625 | ? UNITS_PER_FP_WORD : MIN_UNITS_PER_WORD); | |
13626 | ||
13627 | return flags | (exact_log2 (align) & SECTION_ENTSIZE); | |
5add3202 DE |
13628 | } |
13629 | ||
fb49053f RH |
13630 | static void |
13631 | rs6000_xcoff_encode_section_info (decl, first) | |
13632 | tree decl; | |
13633 | int first ATTRIBUTE_UNUSED; | |
13634 | { | |
13635 | if (TREE_CODE (decl) == FUNCTION_DECL | |
b629ba0c | 13636 | && (*targetm.binds_local_p) (decl)) |
fb49053f RH |
13637 | SYMBOL_REF_FLAG (XEXP (DECL_RTL (decl), 0)) = 1; |
13638 | } | |
f1384257 | 13639 | #endif /* TARGET_XCOFF */ |
0e5dbd9b | 13640 | |
f1384257 AM |
13641 | #if TARGET_MACHO |
13642 | /* Cross-module name binding. Darwin does not support overriding | |
7f3d8013 | 13643 | functions at dynamic-link time. */ |
0e5dbd9b | 13644 | |
2bcc50d0 | 13645 | static bool |
0e5dbd9b DE |
13646 | rs6000_binds_local_p (decl) |
13647 | tree decl; | |
13648 | { | |
f1384257 | 13649 | return default_binds_local_p_1 (decl, 0); |
0e5dbd9b | 13650 | } |
f1384257 | 13651 | #endif |
34bb030a | 13652 | |
3c50106f RH |
13653 | /* Compute a (partial) cost for rtx X. Return true if the complete |
13654 | cost has been computed, and false if subexpressions should be | |
13655 | scanned. In either case, *TOTAL contains the cost result. */ | |
13656 | ||
13657 | static bool | |
13658 | rs6000_rtx_costs (x, code, outer_code, total) | |
13659 | rtx x; | |
13660 | int code, outer_code ATTRIBUTE_UNUSED; | |
13661 | int *total; | |
13662 | { | |
13663 | switch (code) | |
13664 | { | |
13665 | /* On the RS/6000, if it is valid in the insn, it is free. | |
13666 | So this always returns 0. */ | |
13667 | case CONST_INT: | |
13668 | case CONST: | |
13669 | case LABEL_REF: | |
13670 | case SYMBOL_REF: | |
13671 | case CONST_DOUBLE: | |
13672 | case HIGH: | |
13673 | *total = 0; | |
13674 | return true; | |
13675 | ||
13676 | case PLUS: | |
13677 | *total = ((GET_CODE (XEXP (x, 1)) == CONST_INT | |
13678 | && ((unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 1)) | |
13679 | + 0x8000) >= 0x10000) | |
13680 | && ((INTVAL (XEXP (x, 1)) & 0xffff) != 0)) | |
13681 | ? COSTS_N_INSNS (2) | |
13682 | : COSTS_N_INSNS (1)); | |
13683 | return true; | |
13684 | ||
13685 | case AND: | |
13686 | case IOR: | |
13687 | case XOR: | |
13688 | *total = ((GET_CODE (XEXP (x, 1)) == CONST_INT | |
13689 | && (INTVAL (XEXP (x, 1)) & (~ (HOST_WIDE_INT) 0xffff)) != 0 | |
13690 | && ((INTVAL (XEXP (x, 1)) & 0xffff) != 0)) | |
13691 | ? COSTS_N_INSNS (2) | |
13692 | : COSTS_N_INSNS (1)); | |
13693 | return true; | |
13694 | ||
13695 | case MULT: | |
13696 | if (optimize_size) | |
13697 | { | |
13698 | *total = COSTS_N_INSNS (2); | |
13699 | return true; | |
13700 | } | |
13701 | switch (rs6000_cpu) | |
13702 | { | |
13703 | case PROCESSOR_RIOS1: | |
13704 | case PROCESSOR_PPC405: | |
13705 | *total = (GET_CODE (XEXP (x, 1)) != CONST_INT | |
13706 | ? COSTS_N_INSNS (5) | |
13707 | : (INTVAL (XEXP (x, 1)) >= -256 | |
13708 | && INTVAL (XEXP (x, 1)) <= 255) | |
13709 | ? COSTS_N_INSNS (3) : COSTS_N_INSNS (4)); | |
13710 | return true; | |
13711 | ||
13712 | case PROCESSOR_RS64A: | |
13713 | *total = (GET_CODE (XEXP (x, 1)) != CONST_INT | |
13714 | ? GET_MODE (XEXP (x, 1)) != DImode | |
13715 | ? COSTS_N_INSNS (20) : COSTS_N_INSNS (34) | |
13716 | : (INTVAL (XEXP (x, 1)) >= -256 | |
13717 | && INTVAL (XEXP (x, 1)) <= 255) | |
13718 | ? COSTS_N_INSNS (8) : COSTS_N_INSNS (12)); | |
13719 | return true; | |
13720 | ||
13721 | case PROCESSOR_RIOS2: | |
13722 | case PROCESSOR_MPCCORE: | |
13723 | case PROCESSOR_PPC604e: | |
13724 | *total = COSTS_N_INSNS (2); | |
13725 | return true; | |
13726 | ||
13727 | case PROCESSOR_PPC601: | |
13728 | *total = COSTS_N_INSNS (5); | |
13729 | return true; | |
13730 | ||
13731 | case PROCESSOR_PPC603: | |
13732 | case PROCESSOR_PPC7400: | |
13733 | case PROCESSOR_PPC750: | |
13734 | *total = (GET_CODE (XEXP (x, 1)) != CONST_INT | |
13735 | ? COSTS_N_INSNS (5) | |
13736 | : (INTVAL (XEXP (x, 1)) >= -256 | |
13737 | && INTVAL (XEXP (x, 1)) <= 255) | |
13738 | ? COSTS_N_INSNS (2) : COSTS_N_INSNS (3)); | |
13739 | return true; | |
13740 | ||
13741 | case PROCESSOR_PPC7450: | |
13742 | *total = (GET_CODE (XEXP (x, 1)) != CONST_INT | |
13743 | ? COSTS_N_INSNS (4) | |
13744 | : COSTS_N_INSNS (3)); | |
13745 | return true; | |
13746 | ||
13747 | case PROCESSOR_PPC403: | |
13748 | case PROCESSOR_PPC604: | |
13749 | case PROCESSOR_PPC8540: | |
13750 | *total = COSTS_N_INSNS (4); | |
13751 | return true; | |
13752 | ||
13753 | case PROCESSOR_PPC620: | |
13754 | case PROCESSOR_PPC630: | |
3c50106f RH |
13755 | *total = (GET_CODE (XEXP (x, 1)) != CONST_INT |
13756 | ? GET_MODE (XEXP (x, 1)) != DImode | |
13757 | ? COSTS_N_INSNS (5) : COSTS_N_INSNS (7) | |
13758 | : (INTVAL (XEXP (x, 1)) >= -256 | |
13759 | && INTVAL (XEXP (x, 1)) <= 255) | |
13760 | ? COSTS_N_INSNS (3) : COSTS_N_INSNS (4)); | |
13761 | return true; | |
13762 | ||
9259f3b0 DE |
13763 | case PROCESSOR_POWER4: |
13764 | *total = (GET_CODE (XEXP (x, 1)) != CONST_INT | |
13765 | ? GET_MODE (XEXP (x, 1)) != DImode | |
984e25ac DE |
13766 | ? COSTS_N_INSNS (3) : COSTS_N_INSNS (4) |
13767 | : COSTS_N_INSNS (2)); | |
9259f3b0 DE |
13768 | return true; |
13769 | ||
3c50106f RH |
13770 | default: |
13771 | abort (); | |
13772 | } | |
13773 | ||
13774 | case DIV: | |
13775 | case MOD: | |
13776 | if (GET_CODE (XEXP (x, 1)) == CONST_INT | |
13777 | && exact_log2 (INTVAL (XEXP (x, 1))) >= 0) | |
13778 | { | |
13779 | *total = COSTS_N_INSNS (2); | |
13780 | return true; | |
13781 | } | |
13782 | /* FALLTHRU */ | |
13783 | ||
13784 | case UDIV: | |
13785 | case UMOD: | |
13786 | switch (rs6000_cpu) | |
13787 | { | |
13788 | case PROCESSOR_RIOS1: | |
13789 | *total = COSTS_N_INSNS (19); | |
13790 | return true; | |
13791 | ||
13792 | case PROCESSOR_RIOS2: | |
13793 | *total = COSTS_N_INSNS (13); | |
13794 | return true; | |
13795 | ||
13796 | case PROCESSOR_RS64A: | |
13797 | *total = (GET_MODE (XEXP (x, 1)) != DImode | |
13798 | ? COSTS_N_INSNS (65) | |
13799 | : COSTS_N_INSNS (67)); | |
13800 | return true; | |
13801 | ||
13802 | case PROCESSOR_MPCCORE: | |
13803 | *total = COSTS_N_INSNS (6); | |
13804 | return true; | |
13805 | ||
13806 | case PROCESSOR_PPC403: | |
13807 | *total = COSTS_N_INSNS (33); | |
13808 | return true; | |
13809 | ||
13810 | case PROCESSOR_PPC405: | |
13811 | *total = COSTS_N_INSNS (35); | |
13812 | return true; | |
13813 | ||
13814 | case PROCESSOR_PPC601: | |
13815 | *total = COSTS_N_INSNS (36); | |
13816 | return true; | |
13817 | ||
13818 | case PROCESSOR_PPC603: | |
13819 | *total = COSTS_N_INSNS (37); | |
13820 | return true; | |
13821 | ||
13822 | case PROCESSOR_PPC604: | |
13823 | case PROCESSOR_PPC604e: | |
13824 | *total = COSTS_N_INSNS (20); | |
13825 | return true; | |
13826 | ||
13827 | case PROCESSOR_PPC620: | |
13828 | case PROCESSOR_PPC630: | |
3c50106f RH |
13829 | *total = (GET_MODE (XEXP (x, 1)) != DImode |
13830 | ? COSTS_N_INSNS (21) | |
13831 | : COSTS_N_INSNS (37)); | |
13832 | return true; | |
13833 | ||
13834 | case PROCESSOR_PPC750: | |
13835 | case PROCESSOR_PPC8540: | |
13836 | case PROCESSOR_PPC7400: | |
13837 | *total = COSTS_N_INSNS (19); | |
13838 | return true; | |
13839 | ||
13840 | case PROCESSOR_PPC7450: | |
13841 | *total = COSTS_N_INSNS (23); | |
13842 | return true; | |
984e25ac DE |
13843 | |
13844 | case PROCESSOR_POWER4: | |
13845 | *total = (GET_MODE (XEXP (x, 1)) != DImode | |
13846 | ? COSTS_N_INSNS (18) | |
13847 | : COSTS_N_INSNS (34)); | |
13848 | return true; | |
3c50106f RH |
13849 | |
13850 | default: | |
13851 | abort (); | |
13852 | } | |
13853 | ||
13854 | case FFS: | |
13855 | *total = COSTS_N_INSNS (4); | |
13856 | return true; | |
13857 | ||
13858 | case MEM: | |
13859 | /* MEM should be slightly more expensive than (plus (reg) (const)) */ | |
13860 | *total = 5; | |
13861 | return true; | |
13862 | ||
13863 | default: | |
13864 | return false; | |
13865 | } | |
13866 | } | |
13867 | ||
34bb030a DE |
13868 | /* A C expression returning the cost of moving data from a register of class |
13869 | CLASS1 to one of CLASS2. */ | |
13870 | ||
13871 | int | |
13872 | rs6000_register_move_cost (mode, from, to) | |
13873 | enum machine_mode mode; | |
13874 | enum reg_class from, to; | |
13875 | { | |
13876 | /* Moves from/to GENERAL_REGS. */ | |
13877 | if (reg_classes_intersect_p (to, GENERAL_REGS) | |
13878 | || reg_classes_intersect_p (from, GENERAL_REGS)) | |
13879 | { | |
13880 | if (! reg_classes_intersect_p (to, GENERAL_REGS)) | |
13881 | from = to; | |
13882 | ||
13883 | if (from == FLOAT_REGS || from == ALTIVEC_REGS) | |
13884 | return (rs6000_memory_move_cost (mode, from, 0) | |
13885 | + rs6000_memory_move_cost (mode, GENERAL_REGS, 0)); | |
13886 | ||
13887 | /* It's more expensive to move CR_REGS than CR0_REGS because of the shift...*/ | |
13888 | else if (from == CR_REGS) | |
13889 | return 4; | |
13890 | ||
13891 | else | |
13892 | /* A move will cost one instruction per GPR moved. */ | |
13893 | return 2 * HARD_REGNO_NREGS (0, mode); | |
13894 | } | |
13895 | ||
13896 | /* Moving between two similar registers is just one instruction. */ | |
13897 | else if (reg_classes_intersect_p (to, from)) | |
13898 | return mode == TFmode ? 4 : 2; | |
13899 | ||
13900 | /* Everything else has to go through GENERAL_REGS. */ | |
13901 | else | |
13902 | return (rs6000_register_move_cost (mode, GENERAL_REGS, to) | |
13903 | + rs6000_register_move_cost (mode, from, GENERAL_REGS)); | |
13904 | } | |
13905 | ||
13906 | /* A C expressions returning the cost of moving data of MODE from a register to | |
13907 | or from memory. */ | |
13908 | ||
13909 | int | |
13910 | rs6000_memory_move_cost (mode, class, in) | |
13911 | enum machine_mode mode; | |
13912 | enum reg_class class; | |
13913 | int in ATTRIBUTE_UNUSED; | |
13914 | { | |
13915 | if (reg_classes_intersect_p (class, GENERAL_REGS)) | |
13916 | return 4 * HARD_REGNO_NREGS (0, mode); | |
13917 | else if (reg_classes_intersect_p (class, FLOAT_REGS)) | |
13918 | return 4 * HARD_REGNO_NREGS (32, mode); | |
13919 | else if (reg_classes_intersect_p (class, ALTIVEC_REGS)) | |
13920 | return 4 * HARD_REGNO_NREGS (FIRST_ALTIVEC_REGNO, mode); | |
13921 | else | |
13922 | return 4 + rs6000_register_move_cost (mode, class, GENERAL_REGS); | |
13923 | } | |
13924 | ||
62e1dfcf NC |
13925 | /* Return true if TYPE is of type __ev64_opaque__. */ |
13926 | ||
c8e4f0e9 | 13927 | static bool |
62e1dfcf NC |
13928 | is_ev64_opaque_type (type) |
13929 | tree type; | |
13930 | { | |
c8e4f0e9 | 13931 | return (TARGET_SPE |
2abe3e28 AH |
13932 | && (type == opaque_V2SI_type_node |
13933 | || type == opaque_V2SF_type_node | |
13934 | || (TREE_CODE (type) == VECTOR_TYPE | |
13935 | && TYPE_NAME (type) | |
13936 | && TREE_CODE (TYPE_NAME (type)) == TYPE_DECL | |
13937 | && DECL_NAME (TYPE_NAME (type)) | |
13938 | && strcmp (IDENTIFIER_POINTER (DECL_NAME (TYPE_NAME (type))), | |
13939 | "__ev64_opaque__") == 0))); | |
62e1dfcf NC |
13940 | } |
13941 | ||
96714395 AH |
13942 | static rtx |
13943 | rs6000_dwarf_register_span (reg) | |
13944 | rtx reg; | |
13945 | { | |
13946 | unsigned regno; | |
13947 | ||
13948 | if (!TARGET_SPE || !SPE_VECTOR_MODE (GET_MODE (reg))) | |
13949 | return NULL_RTX; | |
13950 | ||
13951 | regno = REGNO (reg); | |
13952 | ||
13953 | /* The duality of the SPE register size wreaks all kinds of havoc. | |
13954 | This is a way of distinguishing r0 in 32-bits from r0 in | |
13955 | 64-bits. */ | |
13956 | return | |
13957 | gen_rtx_PARALLEL (VOIDmode, | |
3bd104d1 AH |
13958 | BYTES_BIG_ENDIAN |
13959 | ? gen_rtvec (2, | |
13960 | gen_rtx_REG (SImode, regno + 1200), | |
13961 | gen_rtx_REG (SImode, regno)) | |
13962 | : gen_rtvec (2, | |
13963 | gen_rtx_REG (SImode, regno), | |
13964 | gen_rtx_REG (SImode, regno + 1200))); | |
96714395 AH |
13965 | } |
13966 | ||
17211ab5 | 13967 | #include "gt-rs6000.h" |