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9878760c 1/* Subroutines used for code generation on IBM RS/6000.
f676971a 2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
5b86a469 3 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
fab3bcc3 4 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
9878760c 5
5de601cf 6 This file is part of GCC.
9878760c 7
5de601cf
NC		 8 GCC is free software; you can redistribute it and/or modify it
9 under the terms of the GNU General Public License as published
10 by the Free Software Foundation; either version 2, or (at your
11 option) any later version.
9878760c 12
5de601cf
NC		 13 GCC is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
9878760c 17
5de601cf
NC		 18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING. If not, write to the
39d14dda
KC		 20 Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
21 MA 02110-1301, USA. */
9878760c 22
956d6950 23#include "config.h"
c4d38ccb 24#include "system.h"
4977bab6
ZW		 25#include "coretypes.h"
26#include "tm.h"
9878760c
RK		 27#include "rtl.h"
28#include "regs.h"
29#include "hard-reg-set.h"
30#include "real.h"
31#include "insn-config.h"
32#include "conditions.h"
9878760c
RK		 33#include "insn-attr.h"
34#include "flags.h"
35#include "recog.h"
9878760c 36#include "obstack.h"
9b30bae2 37#include "tree.h"
dfafc897 38#include "expr.h"
2fc1c679 39#include "optabs.h"
2a430ec1 40#include "except.h"
a7df97e6 41#include "function.h"
296b8152 42#include "output.h"
d5fa86ba 43#include "basic-block.h"
d0101753 44#include "integrate.h"
296b8152 45#include "toplev.h"
c8023011 46#include "ggc.h"
9ebbca7d
GK		 47#include "hashtab.h"
48#include "tm_p.h"
672a6f42
NB		 49#include "target.h"
50#include "target-def.h"
3ac88239 51#include "langhooks.h"
24ea750e 52#include "reload.h"
117dca74 53#include "cfglayout.h"
79ae11c4 54#include "sched-int.h"
cd3ce9b4 55#include "tree-gimple.h"
4d3e6fae 56#include "intl.h"
1bc7c5b6
ZW		 57#if TARGET_XCOFF
58#include "xcoffout.h" /* get declarations of xcoff_*_section_name */
59#endif
93a27b7b
ZW		 60#if TARGET_MACHO
61#include "gstab.h" /* for N_SLINE */
62#endif
9b30bae2 63
7509c759
MM		 64#ifndef TARGET_NO_PROTOTYPE
65#define TARGET_NO_PROTOTYPE 0
66#endif
67
9878760c
RK		 68#define min(A,B) ((A) < (B) ? (A) : (B))
69#define max(A,B) ((A) > (B) ? (A) : (B))
70
d1d0c603
JJ		 71/* Structure used to define the rs6000 stack */
72typedef struct rs6000_stack {
73 int first_gp_reg_save; /* first callee saved GP register used */
74 int first_fp_reg_save; /* first callee saved FP register used */
75 int first_altivec_reg_save; /* first callee saved AltiVec register used */
76 int lr_save_p; /* true if the link reg needs to be saved */
77 int cr_save_p; /* true if the CR reg needs to be saved */
78 unsigned int vrsave_mask; /* mask of vec registers to save */
79 int toc_save_p; /* true if the TOC needs to be saved */
80 int push_p; /* true if we need to allocate stack space */
81 int calls_p; /* true if the function makes any calls */
c4ad648e 82 int world_save_p; /* true if we're saving *everything*:
d62294f5 83 r13-r31, cr, f14-f31, vrsave, v20-v31 */
d1d0c603
JJ		 84 enum rs6000_abi abi; /* which ABI to use */
85 int gp_save_offset; /* offset to save GP regs from initial SP */
86 int fp_save_offset; /* offset to save FP regs from initial SP */
87 int altivec_save_offset; /* offset to save AltiVec regs from initial SP */
88 int lr_save_offset; /* offset to save LR from initial SP */
89 int cr_save_offset; /* offset to save CR from initial SP */
90 int vrsave_save_offset; /* offset to save VRSAVE from initial SP */
91 int spe_gp_save_offset; /* offset to save spe 64-bit gprs */
92 int toc_save_offset; /* offset to save the TOC pointer */
93 int varargs_save_offset; /* offset to save the varargs registers */
94 int ehrd_offset; /* offset to EH return data */
95 int reg_size; /* register size (4 or 8) */
96 int varargs_size; /* size to hold V.4 args passed in regs */
97 HOST_WIDE_INT vars_size; /* variable save area size */
98 int parm_size; /* outgoing parameter size */
99 int save_size; /* save area size */
100 int fixed_size; /* fixed size of stack frame */
101 int gp_size; /* size of saved GP registers */
102 int fp_size; /* size of saved FP registers */
103 int altivec_size; /* size of saved AltiVec registers */
104 int cr_size; /* size to hold CR if not in save_size */
105 int lr_size; /* size to hold LR if not in save_size */
106 int vrsave_size; /* size to hold VRSAVE if not in save_size */
107 int altivec_padding_size; /* size of altivec alignment padding if
108 not in save_size */
109 int spe_gp_size; /* size of 64-bit GPR save size for SPE */
110 int spe_padding_size;
111 int toc_size; /* size to hold TOC if not in save_size */
112 HOST_WIDE_INT total_size; /* total bytes allocated for stack */
113 int spe_64bit_regs_used;
114} rs6000_stack_t;
115
5248c961
RK		 116/* Target cpu type */
117
118enum processor_type rs6000_cpu;
8e3f41e7
MM		 119struct rs6000_cpu_select rs6000_select[3] =
120{
815cdc52
MM		 121 /* switch name, tune arch */
122 { (const char *)0, "--with-cpu=", 1, 1 },
123 { (const char *)0, "-mcpu=", 1, 1 },
124 { (const char *)0, "-mtune=", 1, 0 },
8e3f41e7 125};
5248c961 126
ec507f2d
DE		 127/* Always emit branch hint bits. */
128static GTY(()) bool rs6000_always_hint;
129
130/* Schedule instructions for group formation. */
131static GTY(()) bool rs6000_sched_groups;
132
569fa502
DN		 133/* Support for -msched-costly-dep option. */
134const char *rs6000_sched_costly_dep_str;
135enum rs6000_dependence_cost rs6000_sched_costly_dep;
136
cbe26ab8
DN		 137/* Support for -minsert-sched-nops option. */
138const char *rs6000_sched_insert_nops_str;
139enum rs6000_nop_insertion rs6000_sched_insert_nops;
140
7ccf35ed 141/* Support targetm.vectorize.builtin_mask_for_load. */
13c62176 142static GTY(()) tree altivec_builtin_mask_for_load;
7ccf35ed 143
6fa3f289 144/* Size of long double */
6fa3f289
ZW		 145int rs6000_long_double_type_size;
146
147/* Whether -mabi=altivec has appeared */
148int rs6000_altivec_abi;
149
a3170dc6
AH		 150/* Nonzero if we want SPE ABI extensions. */
151int rs6000_spe_abi;
152
5da702b1
AH		 153/* Nonzero if floating point operations are done in the GPRs. */
154int rs6000_float_gprs = 0;
155
594a51fe
SS		 156/* Nonzero if we want Darwin's struct-by-value-in-regs ABI. */
157int rs6000_darwin64_abi;
158
a0ab749a 159/* Set to nonzero once AIX common-mode calls have been defined. */
bbfb86aa 160static GTY(()) int common_mode_defined;
c81bebd7 161
9878760c
RK		 162/* Save information from a "cmpxx" operation until the branch or scc is
163 emitted. */
9878760c
RK		 164rtx rs6000_compare_op0, rs6000_compare_op1;
165int rs6000_compare_fp_p;
874a0744 166
874a0744
MM		 167/* Label number of label created for -mrelocatable, to call to so we can
168 get the address of the GOT section */
169int rs6000_pic_labelno;
c81bebd7 170
b91da81f 171#ifdef USING_ELFOS_H
c81bebd7 172/* Which abi to adhere to */
9739c90c 173const char *rs6000_abi_name;
d9407988
MM		 174
175/* Semantics of the small data area */
176enum rs6000_sdata_type rs6000_sdata = SDATA_DATA;
177
178/* Which small data model to use */
815cdc52 179const char *rs6000_sdata_name = (char *)0;
9ebbca7d
GK		 180
181/* Counter for labels which are to be placed in .fixup. */
182int fixuplabelno = 0;
874a0744 183#endif
4697a36c 184
c4501e62
JJ		 185/* Bit size of immediate TLS offsets and string from which it is decoded. */
186int rs6000_tls_size = 32;
187const char *rs6000_tls_size_string;
188
b6c9286a
MM		 189/* ABI enumeration available for subtarget to use. */
190enum rs6000_abi rs6000_current_abi;
191
85b776df
AM		 192/* Whether to use variant of AIX ABI for PowerPC64 Linux. */
193int dot_symbols;
194
38c1f2d7 195/* Debug flags */
815cdc52 196const char *rs6000_debug_name;
38c1f2d7
MM		 197int rs6000_debug_stack; /* debug stack applications */
198int rs6000_debug_arg; /* debug argument handling */
199
aabcd309 200/* Value is TRUE if register/mode pair is acceptable. */
0d1fbc8c
AH		 201bool rs6000_hard_regno_mode_ok_p[NUM_MACHINE_MODES][FIRST_PSEUDO_REGISTER];
202
58646b77
PB		 203/* Built in types. */
204
205tree rs6000_builtin_types[RS6000_BTI_MAX];
206tree rs6000_builtin_decls[RS6000_BUILTIN_COUNT];
8bb418a3 207
57ac7be9
AM		 208const char *rs6000_traceback_name;
209static enum {
210 traceback_default = 0,
211 traceback_none,
212 traceback_part,
213 traceback_full
214} rs6000_traceback;
215
38c1f2d7
MM		 216/* Flag to say the TOC is initialized */
217int toc_initialized;
9ebbca7d 218char toc_label_name[10];
38c1f2d7 219
9ebbca7d 220/* Alias set for saves and restores from the rs6000 stack. */
f103e34d 221static GTY(()) int rs6000_sr_alias_set;
c8023011 222
a3c9585f
KH		 223/* Control alignment for fields within structures. */
224/* String from -malign-XXXXX. */
025d9908
KH		 225int rs6000_alignment_flags;
226
78f5898b
AH		 227/* True for any options that were explicitly set. */
228struct {
df01da37 229 bool aix_struct_ret; /* True if -maix-struct-ret was used. */
78f5898b
AH		 230 bool alignment; /* True if -malign- was used. */
231 bool abi; /* True if -mabi= was used. */
232 bool spe; /* True if -mspe= was used. */
233 bool float_gprs; /* True if -mfloat-gprs= was used. */
234 bool isel; /* True if -misel was used. */
235 bool long_double; /* True if -mlong-double- was used. */
236} rs6000_explicit_options;
237
a3170dc6
AH		 238struct builtin_description
239{
240 /* mask is not const because we're going to alter it below. This
241 nonsense will go away when we rewrite the -march infrastructure
242 to give us more target flag bits. */
243 unsigned int mask;
244 const enum insn_code icode;
245 const char *const name;
246 const enum rs6000_builtins code;
247};
8b897cfa
RS		 248\f
249/* Target cpu costs. */
250
251struct processor_costs {
c4ad648e 252 const int mulsi; /* cost of SImode multiplication. */
8b897cfa
RS		 253 const int mulsi_const; /* cost of SImode multiplication by constant. */
254 const int mulsi_const9; /* cost of SImode mult by short constant. */
c4ad648e
AM		 255 const int muldi; /* cost of DImode multiplication. */
256 const int divsi; /* cost of SImode division. */
257 const int divdi; /* cost of DImode division. */
258 const int fp; /* cost of simple SFmode and DFmode insns. */
259 const int dmul; /* cost of DFmode multiplication (and fmadd). */
260 const int sdiv; /* cost of SFmode division (fdivs). */
261 const int ddiv; /* cost of DFmode division (fdiv). */
8b897cfa
RS		 262};
263
264const struct processor_costs *rs6000_cost;
265
266/* Processor costs (relative to an add) */
267
268/* Instruction size costs on 32bit processors. */
269static const
270struct processor_costs size32_cost = {
06a67bdd
RS		 271 COSTS_N_INSNS (1), /* mulsi */
272 COSTS_N_INSNS (1), /* mulsi_const */
273 COSTS_N_INSNS (1), /* mulsi_const9 */
274 COSTS_N_INSNS (1), /* muldi */
275 COSTS_N_INSNS (1), /* divsi */
276 COSTS_N_INSNS (1), /* divdi */
277 COSTS_N_INSNS (1), /* fp */
278 COSTS_N_INSNS (1), /* dmul */
279 COSTS_N_INSNS (1), /* sdiv */
280 COSTS_N_INSNS (1), /* ddiv */
8b897cfa
RS		 281};
282
283/* Instruction size costs on 64bit processors. */
284static const
285struct processor_costs size64_cost = {
06a67bdd
RS		 286 COSTS_N_INSNS (1), /* mulsi */
287 COSTS_N_INSNS (1), /* mulsi_const */
288 COSTS_N_INSNS (1), /* mulsi_const9 */
289 COSTS_N_INSNS (1), /* muldi */
290 COSTS_N_INSNS (1), /* divsi */
291 COSTS_N_INSNS (1), /* divdi */
292 COSTS_N_INSNS (1), /* fp */
293 COSTS_N_INSNS (1), /* dmul */
294 COSTS_N_INSNS (1), /* sdiv */
295 COSTS_N_INSNS (1), /* ddiv */
8b897cfa
RS		 296};
297
298/* Instruction costs on RIOS1 processors. */
299static const
300struct processor_costs rios1_cost = {
06a67bdd
RS		 301 COSTS_N_INSNS (5), /* mulsi */
302 COSTS_N_INSNS (4), /* mulsi_const */
303 COSTS_N_INSNS (3), /* mulsi_const9 */
304 COSTS_N_INSNS (5), /* muldi */
305 COSTS_N_INSNS (19), /* divsi */
306 COSTS_N_INSNS (19), /* divdi */
307 COSTS_N_INSNS (2), /* fp */
308 COSTS_N_INSNS (2), /* dmul */
309 COSTS_N_INSNS (19), /* sdiv */
310 COSTS_N_INSNS (19), /* ddiv */
8b897cfa
RS		 311};
312
313/* Instruction costs on RIOS2 processors. */
314static const
315struct processor_costs rios2_cost = {
06a67bdd
RS		 316 COSTS_N_INSNS (2), /* mulsi */
317 COSTS_N_INSNS (2), /* mulsi_const */
318 COSTS_N_INSNS (2), /* mulsi_const9 */
319 COSTS_N_INSNS (2), /* muldi */
320 COSTS_N_INSNS (13), /* divsi */
321 COSTS_N_INSNS (13), /* divdi */
322 COSTS_N_INSNS (2), /* fp */
323 COSTS_N_INSNS (2), /* dmul */
324 COSTS_N_INSNS (17), /* sdiv */
325 COSTS_N_INSNS (17), /* ddiv */
8b897cfa
RS		 326};
327
328/* Instruction costs on RS64A processors. */
329static const
330struct processor_costs rs64a_cost = {
06a67bdd
RS		 331 COSTS_N_INSNS (20), /* mulsi */
332 COSTS_N_INSNS (12), /* mulsi_const */
333 COSTS_N_INSNS (8), /* mulsi_const9 */
334 COSTS_N_INSNS (34), /* muldi */
335 COSTS_N_INSNS (65), /* divsi */
336 COSTS_N_INSNS (67), /* divdi */
337 COSTS_N_INSNS (4), /* fp */
338 COSTS_N_INSNS (4), /* dmul */
339 COSTS_N_INSNS (31), /* sdiv */
340 COSTS_N_INSNS (31), /* ddiv */
8b897cfa
RS		 341};
342
343/* Instruction costs on MPCCORE processors. */
344static const
345struct processor_costs mpccore_cost = {
06a67bdd
RS		 346 COSTS_N_INSNS (2), /* mulsi */
347 COSTS_N_INSNS (2), /* mulsi_const */
348 COSTS_N_INSNS (2), /* mulsi_const9 */
349 COSTS_N_INSNS (2), /* muldi */
350 COSTS_N_INSNS (6), /* divsi */
351 COSTS_N_INSNS (6), /* divdi */
352 COSTS_N_INSNS (4), /* fp */
353 COSTS_N_INSNS (5), /* dmul */
354 COSTS_N_INSNS (10), /* sdiv */
355 COSTS_N_INSNS (17), /* ddiv */
8b897cfa
RS		 356};
357
358/* Instruction costs on PPC403 processors. */
359static const
360struct processor_costs ppc403_cost = {
06a67bdd
RS		 361 COSTS_N_INSNS (4), /* mulsi */
362 COSTS_N_INSNS (4), /* mulsi_const */
363 COSTS_N_INSNS (4), /* mulsi_const9 */
364 COSTS_N_INSNS (4), /* muldi */
365 COSTS_N_INSNS (33), /* divsi */
366 COSTS_N_INSNS (33), /* divdi */
367 COSTS_N_INSNS (11), /* fp */
368 COSTS_N_INSNS (11), /* dmul */
369 COSTS_N_INSNS (11), /* sdiv */
370 COSTS_N_INSNS (11), /* ddiv */
8b897cfa
RS		 371};
372
373/* Instruction costs on PPC405 processors. */
374static const
375struct processor_costs ppc405_cost = {
06a67bdd
RS		 376 COSTS_N_INSNS (5), /* mulsi */
377 COSTS_N_INSNS (4), /* mulsi_const */
378 COSTS_N_INSNS (3), /* mulsi_const9 */
379 COSTS_N_INSNS (5), /* muldi */
380 COSTS_N_INSNS (35), /* divsi */
381 COSTS_N_INSNS (35), /* divdi */
382 COSTS_N_INSNS (11), /* fp */
383 COSTS_N_INSNS (11), /* dmul */
384 COSTS_N_INSNS (11), /* sdiv */
385 COSTS_N_INSNS (11), /* ddiv */
8b897cfa
RS		 386};
387
388/* Instruction costs on PPC440 processors. */
389static const
390struct processor_costs ppc440_cost = {
06a67bdd
RS		 391 COSTS_N_INSNS (3), /* mulsi */
392 COSTS_N_INSNS (2), /* mulsi_const */
393 COSTS_N_INSNS (2), /* mulsi_const9 */
394 COSTS_N_INSNS (3), /* muldi */
395 COSTS_N_INSNS (34), /* divsi */
396 COSTS_N_INSNS (34), /* divdi */
397 COSTS_N_INSNS (5), /* fp */
398 COSTS_N_INSNS (5), /* dmul */
399 COSTS_N_INSNS (19), /* sdiv */
400 COSTS_N_INSNS (33), /* ddiv */
8b897cfa
RS		 401};
402
403/* Instruction costs on PPC601 processors. */
404static const
405struct processor_costs ppc601_cost = {
06a67bdd
RS		 406 COSTS_N_INSNS (5), /* mulsi */
407 COSTS_N_INSNS (5), /* mulsi_const */
408 COSTS_N_INSNS (5), /* mulsi_const9 */
409 COSTS_N_INSNS (5), /* muldi */
410 COSTS_N_INSNS (36), /* divsi */
411 COSTS_N_INSNS (36), /* divdi */
412 COSTS_N_INSNS (4), /* fp */
413 COSTS_N_INSNS (5), /* dmul */
414 COSTS_N_INSNS (17), /* sdiv */
415 COSTS_N_INSNS (31), /* ddiv */
8b897cfa
RS		 416};
417
418/* Instruction costs on PPC603 processors. */
419static const
420struct processor_costs ppc603_cost = {
06a67bdd
RS		 421 COSTS_N_INSNS (5), /* mulsi */
422 COSTS_N_INSNS (3), /* mulsi_const */
423 COSTS_N_INSNS (2), /* mulsi_const9 */
424 COSTS_N_INSNS (5), /* muldi */
425 COSTS_N_INSNS (37), /* divsi */
426 COSTS_N_INSNS (37), /* divdi */
427 COSTS_N_INSNS (3), /* fp */
428 COSTS_N_INSNS (4), /* dmul */
429 COSTS_N_INSNS (18), /* sdiv */
430 COSTS_N_INSNS (33), /* ddiv */
8b897cfa
RS		 431};
432
433/* Instruction costs on PPC604 processors. */
434static const
435struct processor_costs ppc604_cost = {
06a67bdd
RS		 436 COSTS_N_INSNS (4), /* mulsi */
437 COSTS_N_INSNS (4), /* mulsi_const */
438 COSTS_N_INSNS (4), /* mulsi_const9 */
439 COSTS_N_INSNS (4), /* muldi */
440 COSTS_N_INSNS (20), /* divsi */
441 COSTS_N_INSNS (20), /* divdi */
442 COSTS_N_INSNS (3), /* fp */
443 COSTS_N_INSNS (3), /* dmul */
444 COSTS_N_INSNS (18), /* sdiv */
445 COSTS_N_INSNS (32), /* ddiv */
8b897cfa
RS		 446};
447
448/* Instruction costs on PPC604e processors. */
449static const
450struct processor_costs ppc604e_cost = {
06a67bdd
RS		 451 COSTS_N_INSNS (2), /* mulsi */
452 COSTS_N_INSNS (2), /* mulsi_const */
453 COSTS_N_INSNS (2), /* mulsi_const9 */
454 COSTS_N_INSNS (2), /* muldi */
455 COSTS_N_INSNS (20), /* divsi */
456 COSTS_N_INSNS (20), /* divdi */
457 COSTS_N_INSNS (3), /* fp */
458 COSTS_N_INSNS (3), /* dmul */
459 COSTS_N_INSNS (18), /* sdiv */
460 COSTS_N_INSNS (32), /* ddiv */
8b897cfa
RS		 461};
462
f0517163 463/* Instruction costs on PPC620 processors. */
8b897cfa
RS		 464static const
465struct processor_costs ppc620_cost = {
06a67bdd
RS		 466 COSTS_N_INSNS (5), /* mulsi */
467 COSTS_N_INSNS (4), /* mulsi_const */
468 COSTS_N_INSNS (3), /* mulsi_const9 */
469 COSTS_N_INSNS (7), /* muldi */
470 COSTS_N_INSNS (21), /* divsi */
471 COSTS_N_INSNS (37), /* divdi */
472 COSTS_N_INSNS (3), /* fp */
473 COSTS_N_INSNS (3), /* dmul */
474 COSTS_N_INSNS (18), /* sdiv */
475 COSTS_N_INSNS (32), /* ddiv */
f0517163
RS		 476};
477
478/* Instruction costs on PPC630 processors. */
479static const
480struct processor_costs ppc630_cost = {
06a67bdd
RS		 481 COSTS_N_INSNS (5), /* mulsi */
482 COSTS_N_INSNS (4), /* mulsi_const */
483 COSTS_N_INSNS (3), /* mulsi_const9 */
484 COSTS_N_INSNS (7), /* muldi */
485 COSTS_N_INSNS (21), /* divsi */
486 COSTS_N_INSNS (37), /* divdi */
487 COSTS_N_INSNS (3), /* fp */
488 COSTS_N_INSNS (3), /* dmul */
489 COSTS_N_INSNS (17), /* sdiv */
490 COSTS_N_INSNS (21), /* ddiv */
8b897cfa
RS		 491};
492
493/* Instruction costs on PPC750 and PPC7400 processors. */
494static const
495struct processor_costs ppc750_cost = {
06a67bdd
RS		 496 COSTS_N_INSNS (5), /* mulsi */
497 COSTS_N_INSNS (3), /* mulsi_const */
498 COSTS_N_INSNS (2), /* mulsi_const9 */
499 COSTS_N_INSNS (5), /* muldi */
500 COSTS_N_INSNS (17), /* divsi */
501 COSTS_N_INSNS (17), /* divdi */
502 COSTS_N_INSNS (3), /* fp */
503 COSTS_N_INSNS (3), /* dmul */
504 COSTS_N_INSNS (17), /* sdiv */
505 COSTS_N_INSNS (31), /* ddiv */
8b897cfa
RS		 506};
507
508/* Instruction costs on PPC7450 processors. */
509static const
510struct processor_costs ppc7450_cost = {
06a67bdd
RS		 511 COSTS_N_INSNS (4), /* mulsi */
512 COSTS_N_INSNS (3), /* mulsi_const */
513 COSTS_N_INSNS (3), /* mulsi_const9 */
514 COSTS_N_INSNS (4), /* muldi */
515 COSTS_N_INSNS (23), /* divsi */
516 COSTS_N_INSNS (23), /* divdi */
517 COSTS_N_INSNS (5), /* fp */
518 COSTS_N_INSNS (5), /* dmul */
519 COSTS_N_INSNS (21), /* sdiv */
520 COSTS_N_INSNS (35), /* ddiv */
8b897cfa 521};
a3170dc6 522
8b897cfa
RS		 523/* Instruction costs on PPC8540 processors. */
524static const
525struct processor_costs ppc8540_cost = {
06a67bdd
RS		 526 COSTS_N_INSNS (4), /* mulsi */
527 COSTS_N_INSNS (4), /* mulsi_const */
528 COSTS_N_INSNS (4), /* mulsi_const9 */
529 COSTS_N_INSNS (4), /* muldi */
530 COSTS_N_INSNS (19), /* divsi */
531 COSTS_N_INSNS (19), /* divdi */
532 COSTS_N_INSNS (4), /* fp */
533 COSTS_N_INSNS (4), /* dmul */
534 COSTS_N_INSNS (29), /* sdiv */
535 COSTS_N_INSNS (29), /* ddiv */
8b897cfa
RS		 536};
537
538/* Instruction costs on POWER4 and POWER5 processors. */
539static const
540struct processor_costs power4_cost = {
06a67bdd
RS		 541 COSTS_N_INSNS (3), /* mulsi */
542 COSTS_N_INSNS (2), /* mulsi_const */
543 COSTS_N_INSNS (2), /* mulsi_const9 */
544 COSTS_N_INSNS (4), /* muldi */
545 COSTS_N_INSNS (18), /* divsi */
546 COSTS_N_INSNS (34), /* divdi */
547 COSTS_N_INSNS (3), /* fp */
548 COSTS_N_INSNS (3), /* dmul */
549 COSTS_N_INSNS (17), /* sdiv */
550 COSTS_N_INSNS (17), /* ddiv */
8b897cfa
RS		 551};
552
553\f
a2369ed3 554static bool rs6000_function_ok_for_sibcall (tree, tree);
2ffa9a0c 555static const char *rs6000_invalid_within_doloop (rtx);
a2369ed3
DJ		 556static rtx rs6000_generate_compare (enum rtx_code);
557static void rs6000_maybe_dead (rtx);
558static void rs6000_emit_stack_tie (void);
559static void rs6000_frame_related (rtx, rtx, HOST_WIDE_INT, rtx, rtx);
560static rtx spe_synthesize_frame_save (rtx);
561static bool spe_func_has_64bit_regs_p (void);
b20a9cca 562static void emit_frame_save (rtx, rtx, enum machine_mode, unsigned int,
d1d0c603 563 int, HOST_WIDE_INT);
a2369ed3
DJ		 564static rtx gen_frame_mem_offset (enum machine_mode, rtx, int);
565static void rs6000_emit_allocate_stack (HOST_WIDE_INT, int);
566static unsigned rs6000_hash_constant (rtx);
567static unsigned toc_hash_function (const void *);
568static int toc_hash_eq (const void *, const void *);
569static int constant_pool_expr_1 (rtx, int *, int *);
570static bool constant_pool_expr_p (rtx);
a2369ed3 571static bool legitimate_small_data_p (enum machine_mode, rtx);
a2369ed3 572static bool legitimate_indexed_address_p (rtx, int);
a2369ed3
DJ		 573static bool legitimate_lo_sum_address_p (enum machine_mode, rtx, int);
574static struct machine_function * rs6000_init_machine_status (void);
575static bool rs6000_assemble_integer (rtx, unsigned int, int);
6d0a8091 576static bool no_global_regs_above (int);
5add3202 577#ifdef HAVE_GAS_HIDDEN
a2369ed3 578static void rs6000_assemble_visibility (tree, int);
5add3202 579#endif
a2369ed3
DJ		 580static int rs6000_ra_ever_killed (void);
581static tree rs6000_handle_longcall_attribute (tree *, tree, tree, int, bool *);
8bb418a3 582static tree rs6000_handle_altivec_attribute (tree *, tree, tree, int, bool *);
76d2b81d 583static void rs6000_eliminate_indexed_memrefs (rtx operands[2]);
f18eca82 584static const char *rs6000_mangle_fundamental_type (tree);
b86fe7b4 585extern const struct attribute_spec rs6000_attribute_table[];
a2369ed3
DJ		 586static void rs6000_set_default_type_attributes (tree);
587static void rs6000_output_function_prologue (FILE *, HOST_WIDE_INT);
588static void rs6000_output_function_epilogue (FILE *, HOST_WIDE_INT);
b20a9cca
AM		 589static void rs6000_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT,
590 tree);
a2369ed3 591static rtx rs6000_emit_set_long_const (rtx, HOST_WIDE_INT, HOST_WIDE_INT);
c6e8c921 592static bool rs6000_return_in_memory (tree, tree);
a2369ed3 593static void rs6000_file_start (void);
7c262518 594#if TARGET_ELF
a2369ed3
DJ		 595static unsigned int rs6000_elf_section_type_flags (tree, const char *, int);
596static void rs6000_elf_asm_out_constructor (rtx, int);
597static void rs6000_elf_asm_out_destructor (rtx, int);
1334b570 598static void rs6000_elf_end_indicate_exec_stack (void) ATTRIBUTE_UNUSED;
a2369ed3
DJ		 599static void rs6000_elf_select_section (tree, int, unsigned HOST_WIDE_INT);
600static void rs6000_elf_unique_section (tree, int);
601static void rs6000_elf_select_rtx_section (enum machine_mode, rtx,
b20a9cca 602 unsigned HOST_WIDE_INT);
a56d7372 603static void rs6000_elf_encode_section_info (tree, rtx, int)
0e5dbd9b 604 ATTRIBUTE_UNUSED;
a2369ed3 605static bool rs6000_elf_in_small_data_p (tree);
7c262518 606#endif
cbaaba19 607#if TARGET_XCOFF
a2369ed3 608static void rs6000_xcoff_asm_globalize_label (FILE *, const char *);
8210e4c4 609static void rs6000_xcoff_asm_named_section (const char *, unsigned int, tree);
a2369ed3
DJ		 610static void rs6000_xcoff_select_section (tree, int, unsigned HOST_WIDE_INT);
611static void rs6000_xcoff_unique_section (tree, int);
612static void rs6000_xcoff_select_rtx_section (enum machine_mode, rtx,
b20a9cca 613 unsigned HOST_WIDE_INT);
a2369ed3
DJ		 614static const char * rs6000_xcoff_strip_name_encoding (const char *);
615static unsigned int rs6000_xcoff_section_type_flags (tree, const char *, int);
616static void rs6000_xcoff_file_start (void);
617static void rs6000_xcoff_file_end (void);
f1384257 618#endif
a2369ed3
DJ		 619static int rs6000_variable_issue (FILE *, int, rtx, int);
620static bool rs6000_rtx_costs (rtx, int, int, int *);
621static int rs6000_adjust_cost (rtx, rtx, rtx, int);
cbe26ab8 622static bool is_microcoded_insn (rtx);
79ae11c4 623static int is_dispatch_slot_restricted (rtx);
cbe26ab8
DN		 624static bool is_cracked_insn (rtx);
625static bool is_branch_slot_insn (rtx);
a2369ed3
DJ		 626static int rs6000_adjust_priority (rtx, int);
627static int rs6000_issue_rate (void);
569fa502 628static bool rs6000_is_costly_dependence (rtx, rtx, rtx, int, int);
cbe26ab8
DN		 629static rtx get_next_active_insn (rtx, rtx);
630static bool insn_terminates_group_p (rtx , enum group_termination);
631static bool is_costly_group (rtx *, rtx);
632static int force_new_group (int, FILE *, rtx *, rtx, bool *, int, int *);
633static int redefine_groups (FILE *, int, rtx, rtx);
634static int pad_groups (FILE *, int, rtx, rtx);
635static void rs6000_sched_finish (FILE *, int);
a2369ed3 636static int rs6000_use_sched_lookahead (void);
7ccf35ed 637static tree rs6000_builtin_mask_for_load (void);
a2369ed3 638
58646b77 639static void def_builtin (int, const char *, tree, int);
a2369ed3
DJ		 640static void rs6000_init_builtins (void);
641static rtx rs6000_expand_unop_builtin (enum insn_code, tree, rtx);
642static rtx rs6000_expand_binop_builtin (enum insn_code, tree, rtx);
643static rtx rs6000_expand_ternop_builtin (enum insn_code, tree, rtx);
644static rtx rs6000_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
645static void altivec_init_builtins (void);
646static void rs6000_common_init_builtins (void);
c15c90bb 647static void rs6000_init_libfuncs (void);
a2369ed3 648
b20a9cca
AM		 649static void enable_mask_for_builtins (struct builtin_description *, int,
650 enum rs6000_builtins,
651 enum rs6000_builtins);
7c62e993 652static tree build_opaque_vector_type (tree, int);
a2369ed3
DJ		 653static void spe_init_builtins (void);
654static rtx spe_expand_builtin (tree, rtx, bool *);
61bea3b0 655static rtx spe_expand_stv_builtin (enum insn_code, tree);
a2369ed3
DJ		 656static rtx spe_expand_predicate_builtin (enum insn_code, tree, rtx);
657static rtx spe_expand_evsel_builtin (enum insn_code, tree, rtx);
658static int rs6000_emit_int_cmove (rtx, rtx, rtx, rtx);
d1d0c603
JJ		 659static rs6000_stack_t *rs6000_stack_info (void);
660static void debug_stack_info (rs6000_stack_t *);
a2369ed3
DJ		 661
662static rtx altivec_expand_builtin (tree, rtx, bool *);
663static rtx altivec_expand_ld_builtin (tree, rtx, bool *);
664static rtx altivec_expand_st_builtin (tree, rtx, bool *);
665static rtx altivec_expand_dst_builtin (tree, rtx, bool *);
666static rtx altivec_expand_abs_builtin (enum insn_code, tree, rtx);
f676971a 667static rtx altivec_expand_predicate_builtin (enum insn_code,
c4ad648e 668 const char *, tree, rtx);
b4a62fa0 669static rtx altivec_expand_lv_builtin (enum insn_code, tree, rtx);
a2369ed3 670static rtx altivec_expand_stv_builtin (enum insn_code, tree);
78f5898b 671static bool rs6000_handle_option (size_t, const char *, int);
a2369ed3 672static void rs6000_parse_tls_size_option (void);
5da702b1 673static void rs6000_parse_yes_no_option (const char *, const char *, int *);
a2369ed3
DJ		 674static int first_altivec_reg_to_save (void);
675static unsigned int compute_vrsave_mask (void);
9390387d 676static void compute_save_world_info (rs6000_stack_t *info_ptr);
a2369ed3
DJ		 677static void is_altivec_return_reg (rtx, void *);
678static rtx generate_set_vrsave (rtx, rs6000_stack_t *, int);
679int easy_vector_constant (rtx, enum machine_mode);
58646b77 680static bool rs6000_is_opaque_type (tree);
a2369ed3
DJ		 681static rtx rs6000_dwarf_register_span (rtx);
682static rtx rs6000_legitimize_tls_address (rtx, enum tls_model);
fdbe66f2 683static void rs6000_output_dwarf_dtprel (FILE *, int, rtx) ATTRIBUTE_UNUSED;
a2369ed3
DJ		 684static rtx rs6000_tls_get_addr (void);
685static rtx rs6000_got_sym (void);
9390387d 686static int rs6000_tls_symbol_ref_1 (rtx *, void *);
a2369ed3
DJ		 687static const char *rs6000_get_some_local_dynamic_name (void);
688static int rs6000_get_some_local_dynamic_name_1 (rtx *, void *);
ded9bf77 689static rtx rs6000_complex_function_value (enum machine_mode);
b20a9cca 690static rtx rs6000_spe_function_arg (CUMULATIVE_ARGS *,
a2369ed3 691 enum machine_mode, tree);
0b5383eb
DJ		 692static void rs6000_darwin64_record_arg_advance_flush (CUMULATIVE_ARGS *,
693 HOST_WIDE_INT);
694static void rs6000_darwin64_record_arg_advance_recurse (CUMULATIVE_ARGS *,
695 tree, HOST_WIDE_INT);
696static void rs6000_darwin64_record_arg_flush (CUMULATIVE_ARGS *,
697 HOST_WIDE_INT,
698 rtx[], int *);
699static void rs6000_darwin64_record_arg_recurse (CUMULATIVE_ARGS *,
700 tree, HOST_WIDE_INT,
701 rtx[], int *);
702static rtx rs6000_darwin64_record_arg (CUMULATIVE_ARGS *, tree, int, bool);
ec6376ab 703static rtx rs6000_mixed_function_arg (enum machine_mode, tree, int);
b1917422 704static void rs6000_move_block_from_reg (int regno, rtx x, int nregs);
c6e8c921
GK		 705static void setup_incoming_varargs (CUMULATIVE_ARGS *,
706 enum machine_mode, tree,
707 int *, int);
8cd5a4e0
RH		 708static bool rs6000_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode,
709 tree, bool);
78a52f11
RH		 710static int rs6000_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode,
711 tree, bool);
4d3e6fae 712static const char *invalid_arg_for_unprototyped_fn (tree, tree, tree);
efdba735
SH		 713#if TARGET_MACHO
714static void macho_branch_islands (void);
715static void add_compiler_branch_island (tree, tree, int);
716static int no_previous_def (tree function_name);
717static tree get_prev_label (tree function_name);
c4e18b1c 718static void rs6000_darwin_file_start (void);
efdba735
SH		 719#endif
720
c35d187f 721static tree rs6000_build_builtin_va_list (void);
23a60a04 722static tree rs6000_gimplify_va_arg (tree, tree, tree *, tree *);
fe984136 723static bool rs6000_must_pass_in_stack (enum machine_mode, tree);
f676971a 724static bool rs6000_vector_mode_supported_p (enum machine_mode);
94ff898d 725static int get_vec_cmp_insn (enum rtx_code, enum machine_mode,
21213b4c 726 enum machine_mode);
94ff898d 727static rtx rs6000_emit_vector_compare (enum rtx_code, rtx, rtx,
21213b4c
DP		 728 enum machine_mode);
729static int get_vsel_insn (enum machine_mode);
730static void rs6000_emit_vector_select (rtx, rtx, rtx, rtx);
17211ab5 731
21213b4c
DP		 732
733const int INSN_NOT_AVAILABLE = -1;
93f90be6
FJ		 734static enum machine_mode rs6000_eh_return_filter_mode (void);
735
17211ab5
GK		 736/* Hash table stuff for keeping track of TOC entries. */
737
738struct toc_hash_struct GTY(())
739{
740 /* `key' will satisfy CONSTANT_P; in fact, it will satisfy
741 ASM_OUTPUT_SPECIAL_POOL_ENTRY_P. */
742 rtx key;
743 enum machine_mode key_mode;
744 int labelno;
745};
746
747static GTY ((param_is (struct toc_hash_struct))) htab_t toc_hash_table;
c81bebd7
MM		 748\f
749/* Default register names. */
750char rs6000_reg_names[][8] =
751{
802a0058
MM		 752 "0", "1", "2", "3", "4", "5", "6", "7",
753 "8", "9", "10", "11", "12", "13", "14", "15",
754 "16", "17", "18", "19", "20", "21", "22", "23",
755 "24", "25", "26", "27", "28", "29", "30", "31",
756 "0", "1", "2", "3", "4", "5", "6", "7",
757 "8", "9", "10", "11", "12", "13", "14", "15",
758 "16", "17", "18", "19", "20", "21", "22", "23",
759 "24", "25", "26", "27", "28", "29", "30", "31",
760 "mq", "lr", "ctr","ap",
761 "0", "1", "2", "3", "4", "5", "6", "7",
0ac081f6
AH		 762 "xer",
763 /* AltiVec registers. */
0cd5e3a1
AH		 764 "0", "1", "2", "3", "4", "5", "6", "7",
765 "8", "9", "10", "11", "12", "13", "14", "15",
766 "16", "17", "18", "19", "20", "21", "22", "23",
767 "24", "25", "26", "27", "28", "29", "30", "31",
59a4c851
AH		 768 "vrsave", "vscr",
769 /* SPE registers. */
770 "spe_acc", "spefscr"
c81bebd7
MM		 771};
772
773#ifdef TARGET_REGNAMES
8b60264b 774static const char alt_reg_names[][8] =
c81bebd7 775{
802a0058
MM		 776 "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7",
777 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15",
778 "%r16", "%r17", "%r18", "%r19", "%r20", "%r21", "%r22", "%r23",
779 "%r24", "%r25", "%r26", "%r27", "%r28", "%r29", "%r30", "%r31",
780 "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7",
781 "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15",
782 "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23",
783 "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31",
784 "mq", "lr", "ctr", "ap",
785 "%cr0", "%cr1", "%cr2", "%cr3", "%cr4", "%cr5", "%cr6", "%cr7",
0ac081f6 786 "xer",
59a4c851 787 /* AltiVec registers. */
0ac081f6 788 "%v0", "%v1", "%v2", "%v3", "%v4", "%v5", "%v6", "%v7",
59a4c851
AH		 789 "%v8", "%v9", "%v10", "%v11", "%v12", "%v13", "%v14", "%v15",
790 "%v16", "%v17", "%v18", "%v19", "%v20", "%v21", "%v22", "%v23",
791 "%v24", "%v25", "%v26", "%v27", "%v28", "%v29", "%v30", "%v31",
792 "vrsave", "vscr",
793 /* SPE registers. */
794 "spe_acc", "spefscr"
c81bebd7
MM		 795};
796#endif
9878760c 797\f
daf11973
MM		 798#ifndef MASK_STRICT_ALIGN
799#define MASK_STRICT_ALIGN 0
800#endif
ffcfcb5f
AM		 801#ifndef TARGET_PROFILE_KERNEL
802#define TARGET_PROFILE_KERNEL 0
803#endif
3961e8fe
RH		 804
805/* The VRSAVE bitmask puts bit %v0 as the most significant bit. */
806#define ALTIVEC_REG_BIT(REGNO) (0x80000000 >> ((REGNO) - FIRST_ALTIVEC_REGNO))
672a6f42
NB		 807\f
808/* Initialize the GCC target structure. */
91d231cb
JM		 809#undef TARGET_ATTRIBUTE_TABLE
810#define TARGET_ATTRIBUTE_TABLE rs6000_attribute_table
a5c76ee6
ZW		 811#undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES
812#define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES rs6000_set_default_type_attributes
daf11973 813
301d03af
RS		 814#undef TARGET_ASM_ALIGNED_DI_OP
815#define TARGET_ASM_ALIGNED_DI_OP DOUBLE_INT_ASM_OP
816
817/* Default unaligned ops are only provided for ELF. Find the ops needed
818 for non-ELF systems. */
819#ifndef OBJECT_FORMAT_ELF
cbaaba19 820#if TARGET_XCOFF
ae6c1efd 821/* For XCOFF. rs6000_assemble_integer will handle unaligned DIs on
301d03af
RS		 822 64-bit targets. */
823#undef TARGET_ASM_UNALIGNED_HI_OP
824#define TARGET_ASM_UNALIGNED_HI_OP "\t.vbyte\t2,"
825#undef TARGET_ASM_UNALIGNED_SI_OP
826#define TARGET_ASM_UNALIGNED_SI_OP "\t.vbyte\t4,"
827#undef TARGET_ASM_UNALIGNED_DI_OP
828#define TARGET_ASM_UNALIGNED_DI_OP "\t.vbyte\t8,"
829#else
830/* For Darwin. */
831#undef TARGET_ASM_UNALIGNED_HI_OP
832#define TARGET_ASM_UNALIGNED_HI_OP "\t.short\t"
833#undef TARGET_ASM_UNALIGNED_SI_OP
834#define TARGET_ASM_UNALIGNED_SI_OP "\t.long\t"
49bd1d27
SS		 835#undef TARGET_ASM_UNALIGNED_DI_OP
836#define TARGET_ASM_UNALIGNED_DI_OP "\t.quad\t"
837#undef TARGET_ASM_ALIGNED_DI_OP
838#define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
301d03af
RS		 839#endif
840#endif
841
842/* This hook deals with fixups for relocatable code and DI-mode objects
843 in 64-bit code. */
844#undef TARGET_ASM_INTEGER
845#define TARGET_ASM_INTEGER rs6000_assemble_integer
846
93638d7a
AM		 847#ifdef HAVE_GAS_HIDDEN
848#undef TARGET_ASM_ASSEMBLE_VISIBILITY
849#define TARGET_ASM_ASSEMBLE_VISIBILITY rs6000_assemble_visibility
850#endif
851
c4501e62
JJ		 852#undef TARGET_HAVE_TLS
853#define TARGET_HAVE_TLS HAVE_AS_TLS
854
855#undef TARGET_CANNOT_FORCE_CONST_MEM
856#define TARGET_CANNOT_FORCE_CONST_MEM rs6000_tls_referenced_p
857
08c148a8
NB		 858#undef TARGET_ASM_FUNCTION_PROLOGUE
859#define TARGET_ASM_FUNCTION_PROLOGUE rs6000_output_function_prologue
860#undef TARGET_ASM_FUNCTION_EPILOGUE
861#define TARGET_ASM_FUNCTION_EPILOGUE rs6000_output_function_epilogue
862
b54cf83a
DE		 863#undef TARGET_SCHED_VARIABLE_ISSUE
864#define TARGET_SCHED_VARIABLE_ISSUE rs6000_variable_issue
865
c237e94a
ZW		 866#undef TARGET_SCHED_ISSUE_RATE
867#define TARGET_SCHED_ISSUE_RATE rs6000_issue_rate
868#undef TARGET_SCHED_ADJUST_COST
869#define TARGET_SCHED_ADJUST_COST rs6000_adjust_cost
870#undef TARGET_SCHED_ADJUST_PRIORITY
871#define TARGET_SCHED_ADJUST_PRIORITY rs6000_adjust_priority
f676971a 872#undef TARGET_SCHED_IS_COSTLY_DEPENDENCE
569fa502 873#define TARGET_SCHED_IS_COSTLY_DEPENDENCE rs6000_is_costly_dependence
cbe26ab8
DN		 874#undef TARGET_SCHED_FINISH
875#define TARGET_SCHED_FINISH rs6000_sched_finish
c237e94a 876
be12c2b0
VM		 877#undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
878#define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD rs6000_use_sched_lookahead
879
7ccf35ed
DN		 880#undef TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD
881#define TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD rs6000_builtin_mask_for_load
882
0ac081f6
AH		 883#undef TARGET_INIT_BUILTINS
884#define TARGET_INIT_BUILTINS rs6000_init_builtins
885
886#undef TARGET_EXPAND_BUILTIN
887#define TARGET_EXPAND_BUILTIN rs6000_expand_builtin
888
f18eca82
ZL		 889#undef TARGET_MANGLE_FUNDAMENTAL_TYPE
890#define TARGET_MANGLE_FUNDAMENTAL_TYPE rs6000_mangle_fundamental_type
891
c15c90bb
ZW		 892#undef TARGET_INIT_LIBFUNCS
893#define TARGET_INIT_LIBFUNCS rs6000_init_libfuncs
894
f1384257 895#if TARGET_MACHO
0e5dbd9b 896#undef TARGET_BINDS_LOCAL_P
31920d83 897#define TARGET_BINDS_LOCAL_P darwin_binds_local_p
f1384257 898#endif
0e5dbd9b 899
3961e8fe
RH		 900#undef TARGET_ASM_OUTPUT_MI_THUNK
901#define TARGET_ASM_OUTPUT_MI_THUNK rs6000_output_mi_thunk
902
3961e8fe 903#undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
5b71a4e7 904#define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_tree_hwi_hwi_tree_true
00b960c7 905
4977bab6
ZW		 906#undef TARGET_FUNCTION_OK_FOR_SIBCALL
907#define TARGET_FUNCTION_OK_FOR_SIBCALL rs6000_function_ok_for_sibcall
908
2e3f0db6
DJ		 909#undef TARGET_INVALID_WITHIN_DOLOOP
910#define TARGET_INVALID_WITHIN_DOLOOP rs6000_invalid_within_doloop
9419649c 911
3c50106f
RH		 912#undef TARGET_RTX_COSTS
913#define TARGET_RTX_COSTS rs6000_rtx_costs
dcefdf67
RH		 914#undef TARGET_ADDRESS_COST
915#define TARGET_ADDRESS_COST hook_int_rtx_0
3c50106f 916
c8e4f0e9 917#undef TARGET_VECTOR_OPAQUE_P
58646b77 918#define TARGET_VECTOR_OPAQUE_P rs6000_is_opaque_type
62e1dfcf 919
96714395
AH		 920#undef TARGET_DWARF_REGISTER_SPAN
921#define TARGET_DWARF_REGISTER_SPAN rs6000_dwarf_register_span
922
c6e8c921
GK		 923/* On rs6000, function arguments are promoted, as are function return
924 values. */
925#undef TARGET_PROMOTE_FUNCTION_ARGS
926#define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
927#undef TARGET_PROMOTE_FUNCTION_RETURN
928#define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
929
c6e8c921
GK		 930#undef TARGET_RETURN_IN_MEMORY
931#define TARGET_RETURN_IN_MEMORY rs6000_return_in_memory
932
933#undef TARGET_SETUP_INCOMING_VARARGS
934#define TARGET_SETUP_INCOMING_VARARGS setup_incoming_varargs
935
936/* Always strict argument naming on rs6000. */
937#undef TARGET_STRICT_ARGUMENT_NAMING
938#define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
939#undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED
940#define TARGET_PRETEND_OUTGOING_VARARGS_NAMED hook_bool_CUMULATIVE_ARGS_true
42ba5130
RH		 941#undef TARGET_SPLIT_COMPLEX_ARG
942#define TARGET_SPLIT_COMPLEX_ARG hook_bool_tree_true
fe984136
RH		 943#undef TARGET_MUST_PASS_IN_STACK
944#define TARGET_MUST_PASS_IN_STACK rs6000_must_pass_in_stack
8cd5a4e0
RH		 945#undef TARGET_PASS_BY_REFERENCE
946#define TARGET_PASS_BY_REFERENCE rs6000_pass_by_reference
78a52f11
RH		 947#undef TARGET_ARG_PARTIAL_BYTES
948#define TARGET_ARG_PARTIAL_BYTES rs6000_arg_partial_bytes
c6e8c921 949
c35d187f
RH		 950#undef TARGET_BUILD_BUILTIN_VA_LIST
951#define TARGET_BUILD_BUILTIN_VA_LIST rs6000_build_builtin_va_list
952
cd3ce9b4
JM		 953#undef TARGET_GIMPLIFY_VA_ARG_EXPR
954#define TARGET_GIMPLIFY_VA_ARG_EXPR rs6000_gimplify_va_arg
955
93f90be6
FJ		 956#undef TARGET_EH_RETURN_FILTER_MODE
957#define TARGET_EH_RETURN_FILTER_MODE rs6000_eh_return_filter_mode
958
f676971a
EC		 959#undef TARGET_VECTOR_MODE_SUPPORTED_P
960#define TARGET_VECTOR_MODE_SUPPORTED_P rs6000_vector_mode_supported_p
961
4d3e6fae
FJ		 962#undef TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN
963#define TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN invalid_arg_for_unprototyped_fn
964
78f5898b
AH		 965#undef TARGET_HANDLE_OPTION
966#define TARGET_HANDLE_OPTION rs6000_handle_option
967
968#undef TARGET_DEFAULT_TARGET_FLAGS
969#define TARGET_DEFAULT_TARGET_FLAGS \
970 (TARGET_DEFAULT | MASK_SCHED_PROLOG)
971
445cf5eb
JM		 972/* MPC604EUM 3.5.2 Weak Consistency between Multiple Processors
973 The PowerPC architecture requires only weak consistency among
974 processors--that is, memory accesses between processors need not be
975 sequentially consistent and memory accesses among processors can occur
976 in any order. The ability to order memory accesses weakly provides
977 opportunities for more efficient use of the system bus. Unless a
978 dependency exists, the 604e allows read operations to precede store
979 operations. */
980#undef TARGET_RELAXED_ORDERING
981#define TARGET_RELAXED_ORDERING true
982
fdbe66f2
EB		 983#ifdef HAVE_AS_TLS
984#undef TARGET_ASM_OUTPUT_DWARF_DTPREL
985#define TARGET_ASM_OUTPUT_DWARF_DTPREL rs6000_output_dwarf_dtprel
986#endif
987
f6897b10 988struct gcc_target targetm = TARGET_INITIALIZER;
672a6f42 989\f
0d1fbc8c
AH		 990
991/* Value is 1 if hard register REGNO can hold a value of machine-mode
992 MODE. */
993static int
994rs6000_hard_regno_mode_ok (int regno, enum machine_mode mode)
995{
996 /* The GPRs can hold any mode, but values bigger than one register
997 cannot go past R31. */
998 if (INT_REGNO_P (regno))
999 return INT_REGNO_P (regno + HARD_REGNO_NREGS (regno, mode) - 1);
1000
1001 /* The float registers can only hold floating modes and DImode. */
1002 if (FP_REGNO_P (regno))
1003 return
1004 (GET_MODE_CLASS (mode) == MODE_FLOAT
1005 && FP_REGNO_P (regno + HARD_REGNO_NREGS (regno, mode) - 1))
1006 || (GET_MODE_CLASS (mode) == MODE_INT
1007 && GET_MODE_SIZE (mode) == UNITS_PER_FP_WORD);
1008
1009 /* The CR register can only hold CC modes. */
1010 if (CR_REGNO_P (regno))
1011 return GET_MODE_CLASS (mode) == MODE_CC;
1012
1013 if (XER_REGNO_P (regno))
1014 return mode == PSImode;
1015
1016 /* AltiVec only in AldyVec registers. */
1017 if (ALTIVEC_REGNO_P (regno))
1018 return ALTIVEC_VECTOR_MODE (mode);
1019
1020 /* ...but GPRs can hold SIMD data on the SPE in one register. */
1021 if (SPE_SIMD_REGNO_P (regno) && TARGET_SPE && SPE_VECTOR_MODE (mode))
1022 return 1;
1023
1024 /* We cannot put TImode anywhere except general register and it must be
1025 able to fit within the register set. */
1026
1027 return GET_MODE_SIZE (mode) <= UNITS_PER_WORD;
1028}
1029
1030/* Initialize rs6000_hard_regno_mode_ok_p table. */
1031static void
1032rs6000_init_hard_regno_mode_ok (void)
1033{
1034 int r, m;
1035
1036 for (r = 0; r < FIRST_PSEUDO_REGISTER; ++r)
1037 for (m = 0; m < NUM_MACHINE_MODES; ++m)
1038 if (rs6000_hard_regno_mode_ok (r, m))
1039 rs6000_hard_regno_mode_ok_p[m][r] = true;
1040}
1041
c1e55850
GK		 1042/* If not otherwise specified by a target, make 'long double' equivalent to
1043 'double'. */
1044
1045#ifndef RS6000_DEFAULT_LONG_DOUBLE_SIZE
1046#define RS6000_DEFAULT_LONG_DOUBLE_SIZE 64
1047#endif
1048
5248c961
RK		 1049/* Override command line options. Mostly we process the processor
1050 type and sometimes adjust other TARGET_ options. */
1051
1052void
d779d0dc 1053rs6000_override_options (const char *default_cpu)
5248c961 1054{
c4d38ccb 1055 size_t i, j;
8e3f41e7 1056 struct rs6000_cpu_select *ptr;
66188a7e 1057 int set_masks;
5248c961 1058
66188a7e 1059 /* Simplifications for entries below. */
85638c0d 1060
66188a7e
GK		 1061 enum {
1062 POWERPC_BASE_MASK = MASK_POWERPC | MASK_NEW_MNEMONICS,
1063 POWERPC_7400_MASK = POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_ALTIVEC
1064 };
85638c0d 1065
66188a7e
GK		 1066 /* This table occasionally claims that a processor does not support
1067 a particular feature even though it does, but the feature is slower
1068 than the alternative. Thus, it shouldn't be relied on as a
f676971a 1069 complete description of the processor's support.
66188a7e
GK		 1070
1071 Please keep this list in order, and don't forget to update the
1072 documentation in invoke.texi when adding a new processor or
1073 flag. */
5248c961
RK		 1074 static struct ptt
1075 {
8b60264b
KG		 1076 const char *const name; /* Canonical processor name. */
1077 const enum processor_type processor; /* Processor type enum value. */
1078 const int target_enable; /* Target flags to enable. */
8b60264b 1079 } const processor_target_table[]
66188a7e 1080 = {{"401", PROCESSOR_PPC403, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
49a0b204 1081 {"403", PROCESSOR_PPC403,
66188a7e
GK		 1082 POWERPC_BASE_MASK | MASK_SOFT_FLOAT | MASK_STRICT_ALIGN},
1083 {"405", PROCESSOR_PPC405, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1084 {"405fp", PROCESSOR_PPC405, POWERPC_BASE_MASK},
1085 {"440", PROCESSOR_PPC440, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1086 {"440fp", PROCESSOR_PPC440, POWERPC_BASE_MASK},
1087 {"505", PROCESSOR_MPCCORE, POWERPC_BASE_MASK},
5248c961 1088 {"601", PROCESSOR_PPC601,
66188a7e
GK		 1089 MASK_POWER | POWERPC_BASE_MASK | MASK_MULTIPLE | MASK_STRING},
1090 {"602", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1091 {"603", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1092 {"603e", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1093 {"604", PROCESSOR_PPC604, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1094 {"604e", PROCESSOR_PPC604e, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
7ddb6568
AM		 1095 {"620", PROCESSOR_PPC620,
1096 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
1097 {"630", PROCESSOR_PPC630,
1098 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
66188a7e
GK		 1099 {"740", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1100 {"7400", PROCESSOR_PPC7400, POWERPC_7400_MASK},
1101 {"7450", PROCESSOR_PPC7450, POWERPC_7400_MASK},
1102 {"750", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1103 {"801", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1104 {"821", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1105 {"823", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1106 {"8540", PROCESSOR_PPC8540, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
4d4cbc0e
AH		 1107 /* 8548 has a dummy entry for now. */
1108 {"8548", PROCESSOR_PPC8540, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
66188a7e 1109 {"860", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
7177e720 1110 {"970", PROCESSOR_POWER4,
66188a7e
GK		 1111 POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64},
1112 {"common", PROCESSOR_COMMON, MASK_NEW_MNEMONICS},
1113 {"ec603e", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1114 {"G3", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1115 {"G4", PROCESSOR_PPC7450, POWERPC_7400_MASK},
49ffe578 1116 {"G5", PROCESSOR_POWER4,
66188a7e
GK		 1117 POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64},
1118 {"power", PROCESSOR_POWER, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1119 {"power2", PROCESSOR_POWER,
1120 MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING},
7ddb6568
AM		 1121 {"power3", PROCESSOR_PPC630,
1122 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
1123 {"power4", PROCESSOR_POWER4,
fc091c8e 1124 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POWERPC64},
ec507f2d 1125 {"power5", PROCESSOR_POWER5,
432218ba
DE		 1126 POWERPC_BASE_MASK | MASK_POWERPC64 | MASK_PPC_GFXOPT
1127 | MASK_MFCRF | MASK_POPCNTB},
66188a7e
GK		 1128 {"powerpc", PROCESSOR_POWERPC, POWERPC_BASE_MASK},
1129 {"powerpc64", PROCESSOR_POWERPC64,
98c41d98 1130 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
66188a7e
GK		 1131 {"rios", PROCESSOR_RIOS1, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1132 {"rios1", PROCESSOR_RIOS1, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1133 {"rios2", PROCESSOR_RIOS2,
1134 MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING},
1135 {"rsc", PROCESSOR_PPC601, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1136 {"rsc1", PROCESSOR_PPC601, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
98c41d98
DE		 1137 {"rs64", PROCESSOR_RS64A,
1138 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64}
66188a7e 1139 };
5248c961 1140
ca7558fc 1141 const size_t ptt_size = ARRAY_SIZE (processor_target_table);
5248c961 1142
66188a7e
GK		 1143 /* Some OSs don't support saving the high part of 64-bit registers on
1144 context switch. Other OSs don't support saving Altivec registers.
1145 On those OSs, we don't touch the MASK_POWERPC64 or MASK_ALTIVEC
1146 settings; if the user wants either, the user must explicitly specify
1147 them and we won't interfere with the user's specification. */
1148
1149 enum {
1150 POWER_MASKS = MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING,
f676971a 1151 POWERPC_MASKS = (POWERPC_BASE_MASK | MASK_PPC_GPOPT
66188a7e
GK		 1152 | MASK_PPC_GFXOPT | MASK_POWERPC64 | MASK_ALTIVEC
1153 | MASK_MFCRF)
1154 };
0d1fbc8c
AH		 1155
1156 rs6000_init_hard_regno_mode_ok ();
1157
c4ad648e 1158 set_masks = POWER_MASKS | POWERPC_MASKS | MASK_SOFT_FLOAT;
66188a7e
GK		 1159#ifdef OS_MISSING_POWERPC64
1160 if (OS_MISSING_POWERPC64)
1161 set_masks &= ~MASK_POWERPC64;
1162#endif
1163#ifdef OS_MISSING_ALTIVEC
1164 if (OS_MISSING_ALTIVEC)
1165 set_masks &= ~MASK_ALTIVEC;
1166#endif
1167
768875a8
AM		 1168 /* Don't override by the processor default if given explicitly. */
1169 set_masks &= ~target_flags_explicit;
957211c3 1170
a4f6c312 1171 /* Identify the processor type. */
8e3f41e7 1172 rs6000_select[0].string = default_cpu;
3cb999d8 1173 rs6000_cpu = TARGET_POWERPC64 ? PROCESSOR_DEFAULT64 : PROCESSOR_DEFAULT;
8e3f41e7 1174
b6a1cbae 1175 for (i = 0; i < ARRAY_SIZE (rs6000_select); i++)
5248c961 1176 {
8e3f41e7
MM		 1177 ptr = &rs6000_select[i];
1178 if (ptr->string != (char *)0 && ptr->string[0] != '\0')
5248c961 1179 {
8e3f41e7
MM		 1180 for (j = 0; j < ptt_size; j++)
1181 if (! strcmp (ptr->string, processor_target_table[j].name))
1182 {
1183 if (ptr->set_tune_p)
1184 rs6000_cpu = processor_target_table[j].processor;
1185
1186 if (ptr->set_arch_p)
1187 {
66188a7e
GK		 1188 target_flags &= ~set_masks;
1189 target_flags |= (processor_target_table[j].target_enable
1190 & set_masks);
8e3f41e7
MM		 1191 }
1192 break;
1193 }
1194
4406229e 1195 if (j == ptt_size)
8e3f41e7 1196 error ("bad value (%s) for %s switch", ptr->string, ptr->name);
5248c961
RK		 1197 }
1198 }
8a61d227 1199
993f19a8 1200 if (TARGET_E500)
a3170dc6
AH		 1201 rs6000_isel = 1;
1202
dff9f1b6
DE		 1203 /* If we are optimizing big endian systems for space, use the load/store
1204 multiple and string instructions. */
ef792183 1205 if (BYTES_BIG_ENDIAN && optimize_size)
957211c3 1206 target_flags |= ~target_flags_explicit & (MASK_MULTIPLE | MASK_STRING);
938937d8 1207
a4f6c312
SS		 1208 /* Don't allow -mmultiple or -mstring on little endian systems
1209 unless the cpu is a 750, because the hardware doesn't support the
1210 instructions used in little endian mode, and causes an alignment
1211 trap. The 750 does not cause an alignment trap (except when the
1212 target is unaligned). */
bef84347 1213
b21fb038 1214 if (!BYTES_BIG_ENDIAN && rs6000_cpu != PROCESSOR_PPC750)
7e69e155
MM		 1215 {
1216 if (TARGET_MULTIPLE)
1217 {
1218 target_flags &= ~MASK_MULTIPLE;
b21fb038 1219 if ((target_flags_explicit & MASK_MULTIPLE) != 0)
d4ee4d25 1220 warning (0, "-mmultiple is not supported on little endian systems");
7e69e155
MM		 1221 }
1222
1223 if (TARGET_STRING)
1224 {
1225 target_flags &= ~MASK_STRING;
b21fb038 1226 if ((target_flags_explicit & MASK_STRING) != 0)
d4ee4d25 1227 warning (0, "-mstring is not supported on little endian systems");
7e69e155
MM		 1228 }
1229 }
3933e0e1 1230
38c1f2d7
MM		 1231 /* Set debug flags */
1232 if (rs6000_debug_name)
1233 {
bfc79d3b 1234 if (! strcmp (rs6000_debug_name, "all"))
38c1f2d7 1235 rs6000_debug_stack = rs6000_debug_arg = 1;
bfc79d3b 1236 else if (! strcmp (rs6000_debug_name, "stack"))
38c1f2d7 1237 rs6000_debug_stack = 1;
bfc79d3b 1238 else if (! strcmp (rs6000_debug_name, "arg"))
38c1f2d7
MM		 1239 rs6000_debug_arg = 1;
1240 else
c725bd79 1241 error ("unknown -mdebug-%s switch", rs6000_debug_name);
38c1f2d7
MM		 1242 }
1243
57ac7be9
AM		 1244 if (rs6000_traceback_name)
1245 {
1246 if (! strncmp (rs6000_traceback_name, "full", 4))
1247 rs6000_traceback = traceback_full;
1248 else if (! strncmp (rs6000_traceback_name, "part", 4))
1249 rs6000_traceback = traceback_part;
1250 else if (! strncmp (rs6000_traceback_name, "no", 2))
1251 rs6000_traceback = traceback_none;
1252 else
9e637a26 1253 error ("unknown -mtraceback arg %qs; expecting %<full%>, %<partial%> or %<none%>",
57ac7be9
AM		 1254 rs6000_traceback_name);
1255 }
1256
78f5898b
AH		 1257 if (!rs6000_explicit_options.long_double)
1258 rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE;
6fa3f289 1259
6d0ef01e
HP		 1260 /* Set Altivec ABI as default for powerpc64 linux. */
1261 if (TARGET_ELF && TARGET_64BIT)
1262 {
1263 rs6000_altivec_abi = 1;
78f5898b 1264 TARGET_ALTIVEC_VRSAVE = 1;
6d0ef01e
HP		 1265 }
1266
594a51fe
SS		 1267 /* Set the Darwin64 ABI as default for 64-bit Darwin. */
1268 if (DEFAULT_ABI == ABI_DARWIN && TARGET_64BIT)
1269 {
1270 rs6000_darwin64_abi = 1;
9c7956fd 1271#if TARGET_MACHO
6ac49599 1272 darwin_one_byte_bool = 1;
9c7956fd 1273#endif
d9168963
SS		 1274 /* Default to natural alignment, for better performance. */
1275 rs6000_alignment_flags = MASK_ALIGN_NATURAL;
594a51fe
SS		 1276 }
1277
c4501e62
JJ		 1278 /* Handle -mtls-size option. */
1279 rs6000_parse_tls_size_option ();
1280
a7ae18e2
AH		 1281#ifdef SUBTARGET_OVERRIDE_OPTIONS
1282 SUBTARGET_OVERRIDE_OPTIONS;
1283#endif
1284#ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
1285 SUBSUBTARGET_OVERRIDE_OPTIONS;
1286#endif
4d4cbc0e
AH		 1287#ifdef SUB3TARGET_OVERRIDE_OPTIONS
1288 SUB3TARGET_OVERRIDE_OPTIONS;
1289#endif
a7ae18e2 1290
5da702b1
AH		 1291 if (TARGET_E500)
1292 {
e4463bf1
AH		 1293 if (TARGET_ALTIVEC)
1294 error ("AltiVec and E500 instructions cannot coexist");
1295
5da702b1
AH		 1296 /* The e500 does not have string instructions, and we set
1297 MASK_STRING above when optimizing for size. */
1298 if ((target_flags & MASK_STRING) != 0)
1299 target_flags = target_flags & ~MASK_STRING;
1300 }
1301 else if (rs6000_select[1].string != NULL)
1302 {
1303 /* For the powerpc-eabispe configuration, we set all these by
1304 default, so let's unset them if we manually set another
1305 CPU that is not the E500. */
78f5898b 1306 if (!rs6000_explicit_options.abi)
5da702b1 1307 rs6000_spe_abi = 0;
78f5898b 1308 if (!rs6000_explicit_options.spe)
5da702b1 1309 rs6000_spe = 0;
78f5898b 1310 if (!rs6000_explicit_options.float_gprs)
5da702b1 1311 rs6000_float_gprs = 0;
78f5898b 1312 if (!rs6000_explicit_options.isel)
5da702b1 1313 rs6000_isel = 0;
78f5898b 1314 if (!rs6000_explicit_options.long_double)
c1e55850 1315 rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE;
5da702b1 1316 }
b5044283 1317
ec507f2d
DE		 1318 rs6000_always_hint = (rs6000_cpu != PROCESSOR_POWER4
1319 && rs6000_cpu != PROCESSOR_POWER5);
1320 rs6000_sched_groups = (rs6000_cpu == PROCESSOR_POWER4
1321 || rs6000_cpu == PROCESSOR_POWER5);
1322
ec507f2d
DE		 1323 rs6000_sched_restricted_insns_priority
1324 = (rs6000_sched_groups ? 1 : 0);
79ae11c4 1325
569fa502 1326 /* Handle -msched-costly-dep option. */
ec507f2d
DE		 1327 rs6000_sched_costly_dep
1328 = (rs6000_sched_groups ? store_to_load_dep_costly : no_dep_costly);
432218ba 1329
569fa502
DN		 1330 if (rs6000_sched_costly_dep_str)
1331 {
f676971a 1332 if (! strcmp (rs6000_sched_costly_dep_str, "no"))
c4ad648e 1333 rs6000_sched_costly_dep = no_dep_costly;
569fa502 1334 else if (! strcmp (rs6000_sched_costly_dep_str, "all"))
c4ad648e 1335 rs6000_sched_costly_dep = all_deps_costly;
569fa502 1336 else if (! strcmp (rs6000_sched_costly_dep_str, "true_store_to_load"))
c4ad648e 1337 rs6000_sched_costly_dep = true_store_to_load_dep_costly;
569fa502 1338 else if (! strcmp (rs6000_sched_costly_dep_str, "store_to_load"))
c4ad648e 1339 rs6000_sched_costly_dep = store_to_load_dep_costly;
f676971a 1340 else
c4ad648e 1341 rs6000_sched_costly_dep = atoi (rs6000_sched_costly_dep_str);
cbe26ab8
DN		 1342 }
1343
1344 /* Handle -minsert-sched-nops option. */
ec507f2d
DE		 1345 rs6000_sched_insert_nops
1346 = (rs6000_sched_groups ? sched_finish_regroup_exact : sched_finish_none);
432218ba 1347
cbe26ab8
DN		 1348 if (rs6000_sched_insert_nops_str)
1349 {
1350 if (! strcmp (rs6000_sched_insert_nops_str, "no"))
c4ad648e 1351 rs6000_sched_insert_nops = sched_finish_none;
cbe26ab8 1352 else if (! strcmp (rs6000_sched_insert_nops_str, "pad"))
c4ad648e 1353 rs6000_sched_insert_nops = sched_finish_pad_groups;
cbe26ab8 1354 else if (! strcmp (rs6000_sched_insert_nops_str, "regroup_exact"))
c4ad648e 1355 rs6000_sched_insert_nops = sched_finish_regroup_exact;
cbe26ab8 1356 else
c4ad648e 1357 rs6000_sched_insert_nops = atoi (rs6000_sched_insert_nops_str);
569fa502
DN		 1358 }
1359
c81bebd7 1360#ifdef TARGET_REGNAMES
a4f6c312
SS		 1361 /* If the user desires alternate register names, copy in the
1362 alternate names now. */
c81bebd7 1363 if (TARGET_REGNAMES)
4e135bdd 1364 memcpy (rs6000_reg_names, alt_reg_names, sizeof (rs6000_reg_names));
c81bebd7
MM		 1365#endif
1366
df01da37 1367 /* Set aix_struct_return last, after the ABI is determined.
6fa3f289
ZW		 1368 If -maix-struct-return or -msvr4-struct-return was explicitly
1369 used, don't override with the ABI default. */
df01da37
DE		 1370 if (!rs6000_explicit_options.aix_struct_ret)
1371 aix_struct_return = (DEFAULT_ABI != ABI_V4 || DRAFT_V4_STRUCT_RET);
6fa3f289 1372
fcce224d
DE		 1373 if (TARGET_LONG_DOUBLE_128
1374 && (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN))
70a01792 1375 REAL_MODE_FORMAT (TFmode) = &ibm_extended_format;
fcce224d 1376
9ebbca7d
GK		 1377 /* Allocate an alias set for register saves & restores from stack. */
1378 rs6000_sr_alias_set = new_alias_set ();
1379
f676971a 1380 if (TARGET_TOC)
9ebbca7d 1381 ASM_GENERATE_INTERNAL_LABEL (toc_label_name, "LCTOC", 1);
71f123ca 1382
301d03af
RS		 1383 /* We can only guarantee the availability of DI pseudo-ops when
1384 assembling for 64-bit targets. */
ae6c1efd 1385 if (!TARGET_64BIT)
301d03af
RS		 1386 {
1387 targetm.asm_out.aligned_op.di = NULL;
1388 targetm.asm_out.unaligned_op.di = NULL;
1389 }
1390
1494c534
DE		 1391 /* Set branch target alignment, if not optimizing for size. */
1392 if (!optimize_size)
1393 {
1394 if (rs6000_sched_groups)
1395 {
1396 if (align_functions <= 0)
1397 align_functions = 16;
1398 if (align_jumps <= 0)
1399 align_jumps = 16;
1400 if (align_loops <= 0)
1401 align_loops = 16;
1402 }
1403 if (align_jumps_max_skip <= 0)
1404 align_jumps_max_skip = 15;
1405 if (align_loops_max_skip <= 0)
1406 align_loops_max_skip = 15;
1407 }
2792d578 1408
71f123ca
FS		 1409 /* Arrange to save and restore machine status around nested functions. */
1410 init_machine_status = rs6000_init_machine_status;
42ba5130
RH		 1411
1412 /* We should always be splitting complex arguments, but we can't break
1413 Linux and Darwin ABIs at the moment. For now, only AIX is fixed. */
18f63bfa 1414 if (DEFAULT_ABI != ABI_AIX)
42ba5130 1415 targetm.calls.split_complex_arg = NULL;
8b897cfa
RS		 1416
1417 /* Initialize rs6000_cost with the appropriate target costs. */
1418 if (optimize_size)
1419 rs6000_cost = TARGET_POWERPC64 ? &size64_cost : &size32_cost;
1420 else
1421 switch (rs6000_cpu)
1422 {
1423 case PROCESSOR_RIOS1:
1424 rs6000_cost = &rios1_cost;
1425 break;
1426
1427 case PROCESSOR_RIOS2:
1428 rs6000_cost = &rios2_cost;
1429 break;
1430
1431 case PROCESSOR_RS64A:
1432 rs6000_cost = &rs64a_cost;
1433 break;
1434
1435 case PROCESSOR_MPCCORE:
1436 rs6000_cost = &mpccore_cost;
1437 break;
1438
1439 case PROCESSOR_PPC403:
1440 rs6000_cost = &ppc403_cost;
1441 break;
1442
1443 case PROCESSOR_PPC405:
1444 rs6000_cost = &ppc405_cost;
1445 break;
1446
1447 case PROCESSOR_PPC440:
1448 rs6000_cost = &ppc440_cost;
1449 break;
1450
1451 case PROCESSOR_PPC601:
1452 rs6000_cost = &ppc601_cost;
1453 break;
1454
1455 case PROCESSOR_PPC603:
1456 rs6000_cost = &ppc603_cost;
1457 break;
1458
1459 case PROCESSOR_PPC604:
1460 rs6000_cost = &ppc604_cost;
1461 break;
1462
1463 case PROCESSOR_PPC604e:
1464 rs6000_cost = &ppc604e_cost;
1465 break;
1466
1467 case PROCESSOR_PPC620:
8b897cfa
RS		 1468 rs6000_cost = &ppc620_cost;
1469 break;
1470
f0517163
RS		 1471 case PROCESSOR_PPC630:
1472 rs6000_cost = &ppc630_cost;
1473 break;
1474
8b897cfa
RS		 1475 case PROCESSOR_PPC750:
1476 case PROCESSOR_PPC7400:
1477 rs6000_cost = &ppc750_cost;
1478 break;
1479
1480 case PROCESSOR_PPC7450:
1481 rs6000_cost = &ppc7450_cost;
1482 break;
1483
1484 case PROCESSOR_PPC8540:
1485 rs6000_cost = &ppc8540_cost;
1486 break;
1487
1488 case PROCESSOR_POWER4:
1489 case PROCESSOR_POWER5:
1490 rs6000_cost = &power4_cost;
1491 break;
1492
1493 default:
37409796 1494 gcc_unreachable ();
8b897cfa 1495 }
5248c961 1496}
5accd822 1497
7ccf35ed
DN		 1498/* Implement targetm.vectorize.builtin_mask_for_load. */
1499static tree
1500rs6000_builtin_mask_for_load (void)
1501{
1502 if (TARGET_ALTIVEC)
1503 return altivec_builtin_mask_for_load;
1504 else
1505 return 0;
1506}
1507
5da702b1
AH		 1508/* Handle generic options of the form -mfoo=yes/no.
1509 NAME is the option name.
1510 VALUE is the option value.
1511 FLAG is the pointer to the flag where to store a 1 or 0, depending on
1512 whether the option value is 'yes' or 'no' respectively. */
993f19a8 1513static void
5da702b1 1514rs6000_parse_yes_no_option (const char *name, const char *value, int *flag)
993f19a8 1515{
5da702b1 1516 if (value == 0)
993f19a8 1517 return;
5da702b1
AH		 1518 else if (!strcmp (value, "yes"))
1519 *flag = 1;
1520 else if (!strcmp (value, "no"))
1521 *flag = 0;
08b57fb3 1522 else
5da702b1 1523 error ("unknown -m%s= option specified: '%s'", name, value);
08b57fb3
AH		 1524}
1525
c4501e62
JJ		 1526/* Validate and record the size specified with the -mtls-size option. */
1527
1528static void
863d938c 1529rs6000_parse_tls_size_option (void)
c4501e62
JJ		 1530{
1531 if (rs6000_tls_size_string == 0)
1532 return;
1533 else if (strcmp (rs6000_tls_size_string, "16") == 0)
1534 rs6000_tls_size = 16;
1535 else if (strcmp (rs6000_tls_size_string, "32") == 0)
1536 rs6000_tls_size = 32;
1537 else if (strcmp (rs6000_tls_size_string, "64") == 0)
1538 rs6000_tls_size = 64;
1539 else
9e637a26 1540 error ("bad value %qs for -mtls-size switch", rs6000_tls_size_string);
c4501e62
JJ		 1541}
1542
5accd822 1543void
a2369ed3 1544optimization_options (int level ATTRIBUTE_UNUSED, int size ATTRIBUTE_UNUSED)
5accd822 1545{
2e3f0db6
DJ		 1546 if (DEFAULT_ABI == ABI_DARWIN)
1547 /* The Darwin libraries never set errno, so we might as well
1548 avoid calling them when that's the only reason we would. */
1549 flag_errno_math = 0;
5accd822 1550}
78f5898b
AH		 1551
1552/* Implement TARGET_HANDLE_OPTION. */
1553
1554static bool
1555rs6000_handle_option (size_t code, const char *arg, int value)
1556{
1557 switch (code)
1558 {
1559 case OPT_mno_power:
1560 target_flags &= ~(MASK_POWER | MASK_POWER2
1561 | MASK_MULTIPLE | MASK_STRING);
c2dba4ab
AH		 1562 target_flags_explicit |= (MASK_POWER | MASK_POWER2
1563 | MASK_MULTIPLE | MASK_STRING);
78f5898b
AH		 1564 break;
1565 case OPT_mno_powerpc:
1566 target_flags &= ~(MASK_POWERPC | MASK_PPC_GPOPT
1567 | MASK_PPC_GFXOPT | MASK_POWERPC64);
c2dba4ab
AH		 1568 target_flags_explicit |= (MASK_POWERPC | MASK_PPC_GPOPT
1569 | MASK_PPC_GFXOPT | MASK_POWERPC64);
78f5898b
AH		 1570 break;
1571 case OPT_mfull_toc:
1572 target_flags &= ~(MASK_MINIMAL_TOC | MASK_NO_FP_IN_TOC
1573 | MASK_NO_SUM_IN_TOC);
c2dba4ab
AH		 1574 target_flags_explicit |= (MASK_MINIMAL_TOC | MASK_NO_FP_IN_TOC
1575 | MASK_NO_SUM_IN_TOC);
78f5898b
AH		 1576#ifdef TARGET_USES_SYSV4_OPT
1577 /* Note, V.4 no longer uses a normal TOC, so make -mfull-toc, be
1578 just the same as -mminimal-toc. */
1579 target_flags |= MASK_MINIMAL_TOC;
c2dba4ab 1580 target_flags_explicit |= MASK_MINIMAL_TOC;
78f5898b
AH		 1581#endif
1582 break;
1583
1584#ifdef TARGET_USES_SYSV4_OPT
1585 case OPT_mtoc:
1586 /* Make -mtoc behave like -mminimal-toc. */
1587 target_flags |= MASK_MINIMAL_TOC;
c2dba4ab 1588 target_flags_explicit |= MASK_MINIMAL_TOC;
78f5898b
AH		 1589 break;
1590#endif
1591
1592#ifdef TARGET_USES_AIX64_OPT
1593 case OPT_maix64:
1594#else
1595 case OPT_m64:
1596#endif
1597 target_flags |= MASK_POWERPC64 | MASK_POWERPC | MASK_PPC_GFXOPT;
c2dba4ab
AH		 1598 target_flags_explicit |= MASK_POWERPC64 | MASK_POWERPC
1599 | MASK_PPC_GFXOPT;
78f5898b
AH		 1600 break;
1601
1602#ifdef TARGET_USES_AIX64_OPT
1603 case OPT_maix32:
1604#else
1605 case OPT_m32:
1606#endif
1607 target_flags &= ~MASK_POWERPC64;
c2dba4ab 1608 target_flags_explicit |= MASK_POWERPC64;
78f5898b
AH		 1609 break;
1610
1611 case OPT_minsert_sched_nops_:
1612 rs6000_sched_insert_nops_str = arg;
1613 break;
1614
1615 case OPT_mminimal_toc:
1616 if (value == 1)
1617 {
c2dba4ab
AH		 1618 target_flags &= ~(MASK_NO_FP_IN_TOC | MASK_NO_SUM_IN_TOC);
1619 target_flags_explicit |= (MASK_NO_FP_IN_TOC | MASK_NO_SUM_IN_TOC);
78f5898b
AH		 1620 }
1621 break;
1622
1623 case OPT_mpower:
1624 if (value == 1)
c2dba4ab
AH		 1625 {
1626 target_flags |= (MASK_MULTIPLE | MASK_STRING);
1627 target_flags_explicit |= (MASK_MULTIPLE | MASK_STRING);
1628 }
78f5898b
AH		 1629 break;
1630
1631 case OPT_mpower2:
1632 if (value == 1)
c2dba4ab
AH		 1633 {
1634 target_flags |= (MASK_POWER | MASK_MULTIPLE | MASK_STRING);
1635 target_flags_explicit |= (MASK_POWER | MASK_MULTIPLE | MASK_STRING);
1636 }
78f5898b
AH		 1637 break;
1638
1639 case OPT_mpowerpc_gpopt:
1640 case OPT_mpowerpc_gfxopt:
1641 if (value == 1)
c2dba4ab
AH		 1642 {
1643 target_flags |= MASK_POWERPC;
1644 target_flags_explicit |= MASK_POWERPC;
1645 }
78f5898b
AH		 1646 break;
1647
df01da37
DE		 1648 case OPT_maix_struct_return:
1649 case OPT_msvr4_struct_return:
1650 rs6000_explicit_options.aix_struct_ret = true;
1651 break;
1652
78f5898b
AH		 1653 case OPT_mvrsave_:
1654 rs6000_parse_yes_no_option ("vrsave", arg, &(TARGET_ALTIVEC_VRSAVE));
1655 break;
78f5898b
AH		 1656
1657 case OPT_misel_:
1658 rs6000_explicit_options.isel = true;
1659 rs6000_parse_yes_no_option ("isel", arg, &(rs6000_isel));
1660 break;
1661
1662 case OPT_mspe_:
1663 rs6000_explicit_options.spe = true;
1664 rs6000_parse_yes_no_option ("spe", arg, &(rs6000_spe));
1665 /* No SPE means 64-bit long doubles, even if an E500. */
1666 if (!rs6000_spe)
1667 rs6000_long_double_type_size = 64;
1668 break;
1669
1670 case OPT_mdebug_:
1671 rs6000_debug_name = arg;
1672 break;
1673
1674#ifdef TARGET_USES_SYSV4_OPT
1675 case OPT_mcall_:
1676 rs6000_abi_name = arg;
1677 break;
1678
1679 case OPT_msdata_:
1680 rs6000_sdata_name = arg;
1681 break;
1682
1683 case OPT_mtls_size_:
1684 rs6000_tls_size_string = arg;
1685 break;
1686
1687 case OPT_mrelocatable:
1688 if (value == 1)
c2dba4ab
AH		 1689 {
1690 target_flags |= MASK_MINIMAL_TOC | MASK_NO_FP_IN_TOC;
1691 target_flags_explicit |= MASK_MINIMAL_TOC | MASK_NO_FP_IN_TOC;
1692 }
78f5898b
AH		 1693 break;
1694
1695 case OPT_mrelocatable_lib:
1696 if (value == 1)
c2dba4ab
AH		 1697 {
1698 target_flags |= MASK_RELOCATABLE | MASK_MINIMAL_TOC
1699 | MASK_NO_FP_IN_TOC;
1700 target_flags_explicit |= MASK_RELOCATABLE | MASK_MINIMAL_TOC
1701 | MASK_NO_FP_IN_TOC;
1702 }
78f5898b 1703 else
c2dba4ab
AH		 1704 {
1705 target_flags &= ~MASK_RELOCATABLE;
1706 target_flags_explicit |= MASK_RELOCATABLE;
1707 }
78f5898b
AH		 1708 break;
1709#endif
1710
1711 case OPT_mabi_:
1712 rs6000_explicit_options.abi = true;
1713 if (!strcmp (arg, "altivec"))
1714 {
1715 rs6000_altivec_abi = 1;
1716 rs6000_spe_abi = 0;
1717 }
1718 else if (! strcmp (arg, "no-altivec"))
1719 rs6000_altivec_abi = 0;
1720 else if (! strcmp (arg, "spe"))
1721 {
1722 rs6000_spe_abi = 1;
1723 rs6000_altivec_abi = 0;
1724 if (!TARGET_SPE_ABI)
1725 error ("not configured for ABI: '%s'", arg);
1726 }
1727 else if (! strcmp (arg, "no-spe"))
1728 rs6000_spe_abi = 0;
1729
1730 /* These are here for testing during development only, do not
1731 document in the manual please. */
1732 else if (! strcmp (arg, "d64"))
1733 {
1734 rs6000_darwin64_abi = 1;
1735 warning (0, "Using darwin64 ABI");
1736 }
1737 else if (! strcmp (arg, "d32"))
1738 {
1739 rs6000_darwin64_abi = 0;
1740 warning (0, "Using old darwin ABI");
1741 }
1742
1743 else
1744 {
1745 error ("unknown ABI specified: '%s'", arg);
1746 return false;
1747 }
1748 break;
1749
1750 case OPT_mcpu_:
1751 rs6000_select[1].string = arg;
1752 break;
1753
1754 case OPT_mtune_:
1755 rs6000_select[2].string = arg;
1756 break;
1757
1758 case OPT_mtraceback_:
1759 rs6000_traceback_name = arg;
1760 break;
1761
1762 case OPT_mfloat_gprs_:
1763 rs6000_explicit_options.float_gprs = true;
1764 if (! strcmp (arg, "yes") || ! strcmp (arg, "single"))
1765 rs6000_float_gprs = 1;
1766 else if (! strcmp (arg, "double"))
1767 rs6000_float_gprs = 2;
1768 else if (! strcmp (arg, "no"))
1769 rs6000_float_gprs = 0;
1770 else
1771 {
1772 error ("invalid option for -mfloat-gprs: '%s'", arg);
1773 return false;
1774 }
1775 break;
1776
1777 case OPT_mlong_double_:
1778 rs6000_explicit_options.long_double = true;
1779 rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE;
1780 if (value != 64 && value != 128)
1781 {
1782 error ("Unknown switch -mlong-double-%s", arg);
1783 rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE;
1784 return false;
1785 }
1786 else
1787 rs6000_long_double_type_size = value;
1788 break;
1789
1790 case OPT_msched_costly_dep_:
1791 rs6000_sched_costly_dep_str = arg;
1792 break;
1793
1794 case OPT_malign_:
1795 rs6000_explicit_options.alignment = true;
1796 if (! strcmp (arg, "power"))
1797 {
1798 /* On 64-bit Darwin, power alignment is ABI-incompatible with
1799 some C library functions, so warn about it. The flag may be
1800 useful for performance studies from time to time though, so
1801 don't disable it entirely. */
1802 if (DEFAULT_ABI == ABI_DARWIN && TARGET_64BIT)
1803 warning (0, "-malign-power is not supported for 64-bit Darwin;"
1804 " it is incompatible with the installed C and C++ libraries");
1805 rs6000_alignment_flags = MASK_ALIGN_POWER;
1806 }
1807 else if (! strcmp (arg, "natural"))
1808 rs6000_alignment_flags = MASK_ALIGN_NATURAL;
1809 else
1810 {
1811 error ("unknown -malign-XXXXX option specified: '%s'", arg);
1812 return false;
1813 }
1814 break;
1815 }
1816 return true;
1817}
3cfa4909
MM		 1818\f
1819/* Do anything needed at the start of the asm file. */
1820
1bc7c5b6 1821static void
863d938c 1822rs6000_file_start (void)
3cfa4909 1823{
c4d38ccb 1824 size_t i;
3cfa4909 1825 char buffer[80];
d330fd93 1826 const char *start = buffer;
3cfa4909 1827 struct rs6000_cpu_select *ptr;
1bc7c5b6
ZW		 1828 const char *default_cpu = TARGET_CPU_DEFAULT;
1829 FILE *file = asm_out_file;
1830
1831 default_file_start ();
1832
1833#ifdef TARGET_BI_ARCH
1834 if ((TARGET_DEFAULT ^ target_flags) & MASK_64BIT)
1835 default_cpu = 0;
1836#endif
3cfa4909
MM		 1837
1838 if (flag_verbose_asm)
1839 {
1840 sprintf (buffer, "\n%s rs6000/powerpc options:", ASM_COMMENT_START);
1841 rs6000_select[0].string = default_cpu;
1842
b6a1cbae 1843 for (i = 0; i < ARRAY_SIZE (rs6000_select); i++)
3cfa4909
MM		 1844 {
1845 ptr = &rs6000_select[i];
1846 if (ptr->string != (char *)0 && ptr->string[0] != '\0')
1847 {
1848 fprintf (file, "%s %s%s", start, ptr->name, ptr->string);
1849 start = "";
1850 }
1851 }
1852
b0bfee6e
DE		 1853#ifdef CONFIG_PPC405CR
1854 if (rs6000_cpu == PROCESSOR_PPC405)
1855 {
1856 fprint (file, "%s PPC405CR_ERRATUM77", start);
1857 start = "";
1858 }
1859#endif
1860
b91da81f 1861#ifdef USING_ELFOS_H
3cfa4909
MM		 1862 switch (rs6000_sdata)
1863 {
1864 case SDATA_NONE: fprintf (file, "%s -msdata=none", start); start = ""; break;
1865 case SDATA_DATA: fprintf (file, "%s -msdata=data", start); start = ""; break;
1866 case SDATA_SYSV: fprintf (file, "%s -msdata=sysv", start); start = ""; break;
1867 case SDATA_EABI: fprintf (file, "%s -msdata=eabi", start); start = ""; break;
1868 }
1869
1870 if (rs6000_sdata && g_switch_value)
1871 {
307b599c
MK		 1872 fprintf (file, "%s -G " HOST_WIDE_INT_PRINT_UNSIGNED, start,
1873 g_switch_value);
3cfa4909
MM		 1874 start = "";
1875 }
1876#endif
1877
1878 if (*start == '\0')
949ea356 1879 putc ('\n', file);
3cfa4909 1880 }
b723e82f
JJ		 1881
1882 if (DEFAULT_ABI == ABI_AIX || (TARGET_ELF && flag_pic == 2))
1883 {
1884 toc_section ();
1885 text_section ();
1886 }
3cfa4909 1887}
c4e18b1c 1888
5248c961 1889\f
a0ab749a 1890/* Return nonzero if this function is known to have a null epilogue. */
9878760c
RK		 1891
1892int
863d938c 1893direct_return (void)
9878760c 1894{
4697a36c
MM		 1895 if (reload_completed)
1896 {
1897 rs6000_stack_t *info = rs6000_stack_info ();
1898
1899 if (info->first_gp_reg_save == 32
1900 && info->first_fp_reg_save == 64
00b960c7 1901 && info->first_altivec_reg_save == LAST_ALTIVEC_REGNO + 1
c81fc13e
DE		 1902 && ! info->lr_save_p
1903 && ! info->cr_save_p
00b960c7 1904 && info->vrsave_mask == 0
c81fc13e 1905 && ! info->push_p)
4697a36c
MM		 1906 return 1;
1907 }
1908
1909 return 0;
9878760c
RK		 1910}
1911
4e74d8ec
MM		 1912/* Return the number of instructions it takes to form a constant in an
1913 integer register. */
1914
48d72335 1915int
a2369ed3 1916num_insns_constant_wide (HOST_WIDE_INT value)
4e74d8ec
MM		 1917{
1918 /* signed constant loadable with {cal|addi} */
5f59ecb7 1919 if (CONST_OK_FOR_LETTER_P (value, 'I'))
0865c631
GK		 1920 return 1;
1921
4e74d8ec 1922 /* constant loadable with {cau|addis} */
5f59ecb7 1923 else if (CONST_OK_FOR_LETTER_P (value, 'L'))
4e74d8ec
MM		 1924 return 1;
1925
5f59ecb7 1926#if HOST_BITS_PER_WIDE_INT == 64
c81fc13e 1927 else if (TARGET_POWERPC64)
4e74d8ec 1928 {
a65c591c
DE		 1929 HOST_WIDE_INT low = ((value & 0xffffffff) ^ 0x80000000) - 0x80000000;
1930 HOST_WIDE_INT high = value >> 31;
4e74d8ec 1931
a65c591c 1932 if (high == 0 || high == -1)
4e74d8ec
MM		 1933 return 2;
1934
a65c591c 1935 high >>= 1;
4e74d8ec 1936
a65c591c 1937 if (low == 0)
4e74d8ec 1938 return num_insns_constant_wide (high) + 1;
4e74d8ec
MM		 1939 else
1940 return (num_insns_constant_wide (high)
e396202a 1941 + num_insns_constant_wide (low) + 1);
4e74d8ec
MM		 1942 }
1943#endif
1944
1945 else
1946 return 2;
1947}
1948
1949int
a2369ed3 1950num_insns_constant (rtx op, enum machine_mode mode)
4e74d8ec 1951{
37409796
NS		 1952 HOST_WIDE_INT low, high;
1953
1954 switch (GET_CODE (op))
0d30d435 1955 {
37409796 1956 case CONST_INT:
0d30d435 1957#if HOST_BITS_PER_WIDE_INT == 64
4e2c1c44 1958 if ((INTVAL (op) >> 31) != 0 && (INTVAL (op) >> 31) != -1
4ae234b0 1959 && mask_operand (op, mode))
c4ad648e 1960 return 2;
0d30d435
DE		 1961 else
1962#endif
1963 return num_insns_constant_wide (INTVAL (op));
4e74d8ec 1964
37409796
NS		 1965 case CONST_DOUBLE:
1966 if (mode == SFmode)
1967 {
1968 long l;
1969 REAL_VALUE_TYPE rv;
1970
1971 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
1972 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
1973 return num_insns_constant_wide ((HOST_WIDE_INT) l);
1974 }
a260abc9 1975
37409796
NS		 1976 if (mode == VOIDmode || mode == DImode)
1977 {
1978 high = CONST_DOUBLE_HIGH (op);
1979 low = CONST_DOUBLE_LOW (op);
1980 }
1981 else
1982 {
1983 long l[2];
1984 REAL_VALUE_TYPE rv;
1985
1986 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
1987 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
1988 high = l[WORDS_BIG_ENDIAN == 0];
1989 low = l[WORDS_BIG_ENDIAN != 0];
1990 }
47ad8c61 1991
37409796
NS		 1992 if (TARGET_32BIT)
1993 return (num_insns_constant_wide (low)
1994 + num_insns_constant_wide (high));
1995 else
1996 {
1997 if ((high == 0 && low >= 0)
1998 || (high == -1 && low < 0))
1999 return num_insns_constant_wide (low);
2000
4ae234b0 2001 else if (mask_operand (op, mode))
37409796
NS		 2002 return 2;
2003
2004 else if (low == 0)
2005 return num_insns_constant_wide (high) + 1;
2006
2007 else
2008 return (num_insns_constant_wide (high)
2009 + num_insns_constant_wide (low) + 1);
2010 }
2011
2012 default:
2013 gcc_unreachable ();
4e74d8ec 2014 }
4e74d8ec
MM		 2015}
2016
effa5d5d 2017/* Returns the constant for the splat instruction, if exists. */
452a7d36 2018
48d72335 2019int
452a7d36
HP		 2020easy_vector_splat_const (int cst, enum machine_mode mode)
2021{
f676971a 2022 switch (mode)
452a7d36
HP		 2023 {
2024 case V4SImode:
f676971a
EC		 2025 if (EASY_VECTOR_15 (cst)
2026 || EASY_VECTOR_15_ADD_SELF (cst))
452a7d36
HP		 2027 return cst;
2028 if ((cst & 0xffff) != ((cst >> 16) & 0xffff))
2029 break;
2030 cst = cst >> 16;
c4ad648e
AM		 2031 /* Fall thru */
2032
452a7d36 2033 case V8HImode:
f676971a
EC		 2034 if (EASY_VECTOR_15 (cst)
2035 || EASY_VECTOR_15_ADD_SELF (cst))
452a7d36
HP		 2036 return cst;
2037 if ((cst & 0xff) != ((cst >> 8) & 0xff))
2038 break;
2039 cst = cst >> 8;
c4ad648e
AM		 2040 /* Fall thru */
2041
452a7d36 2042 case V16QImode:
c4ad648e
AM		 2043 if (EASY_VECTOR_15 (cst)
2044 || EASY_VECTOR_15_ADD_SELF (cst))
2045 return cst;
f676971a 2046 default:
452a7d36
HP		 2047 break;
2048 }
2049 return 0;
2050}
2051
72ac76be 2052/* Return nonzero if all elements of a vector have the same value. */
69ef87e2 2053
48d72335 2054int
a2369ed3 2055easy_vector_same (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
d744e06e
AH		 2056{
2057 int units, i, cst;
2058
2059 units = CONST_VECTOR_NUNITS (op);
2060
2061 cst = INTVAL (CONST_VECTOR_ELT (op, 0));
2062 for (i = 1; i < units; ++i)
2063 if (INTVAL (CONST_VECTOR_ELT (op, i)) != cst)
2064 break;
452a7d36 2065 if (i == units && easy_vector_splat_const (cst, mode))
d744e06e
AH		 2066 return 1;
2067 return 0;
2068}
2069
452a7d36 2070/* Generate easy_vector_constant out of a easy_vector_constant_add_self. */
d744e06e 2071
f676971a 2072rtx
452a7d36
HP		 2073gen_easy_vector_constant_add_self (rtx op)
2074{
2075 int i, units;
2076 rtvec v;
2077 units = GET_MODE_NUNITS (GET_MODE (op));
2078 v = rtvec_alloc (units);
2079
2080 for (i = 0; i < units; i++)
f676971a 2081 RTVEC_ELT (v, i) =
452a7d36
HP		 2082 GEN_INT (INTVAL (CONST_VECTOR_ELT (op, i)) >> 1);
2083 return gen_rtx_raw_CONST_VECTOR (GET_MODE (op), v);
d744e06e
AH		 2084}
2085
2086const char *
a2369ed3 2087output_vec_const_move (rtx *operands)
d744e06e
AH		 2088{
2089 int cst, cst2;
2090 enum machine_mode mode;
2091 rtx dest, vec;
2092
2093 dest = operands[0];
2094 vec = operands[1];
69ef87e2 2095
d744e06e
AH		 2096 cst = INTVAL (CONST_VECTOR_ELT (vec, 0));
2097 cst2 = INTVAL (CONST_VECTOR_ELT (vec, 1));
2098 mode = GET_MODE (dest);
69ef87e2 2099
d744e06e
AH		 2100 if (TARGET_ALTIVEC)
2101 {
2102 if (zero_constant (vec, mode))
2103 return "vxor %0,%0,%0";
37409796
NS		 2104
2105 gcc_assert (easy_vector_constant (vec, mode));
2106
2107 operands[1] = GEN_INT (cst);
2108 switch (mode)
98ef3137 2109 {
37409796
NS		 2110 case V4SImode:
2111 if (EASY_VECTOR_15 (cst))
d744e06e 2112 {
37409796
NS		 2113 operands[1] = GEN_INT (cst);
2114 return "vspltisw %0,%1";
2115 }
2116 else if (EASY_VECTOR_15_ADD_SELF (cst))
2117 return "#";
2118 cst = cst >> 16;
2119 /* Fall thru */
c4ad648e 2120
37409796
NS		 2121 case V8HImode:
2122 if (EASY_VECTOR_15 (cst))
2123 {
2124 operands[1] = GEN_INT (cst);
2125 return "vspltish %0,%1";
2126 }
2127 else if (EASY_VECTOR_15_ADD_SELF (cst))
2128 return "#";
2129 cst = cst >> 8;
2130 /* Fall thru */
c4ad648e 2131
37409796
NS		 2132 case V16QImode:
2133 if (EASY_VECTOR_15 (cst))
2134 {
2135 operands[1] = GEN_INT (cst);
2136 return "vspltisb %0,%1";
d744e06e 2137 }
37409796
NS		 2138 else if (EASY_VECTOR_15_ADD_SELF (cst))
2139 return "#";
2140
2141 default:
2142 gcc_unreachable ();
98ef3137 2143 }
69ef87e2
AH		 2144 }
2145
37409796
NS		 2146 gcc_assert (TARGET_SPE);
2147
2148 /* Vector constant 0 is handled as a splitter of V2SI, and in the
2149 pattern of V1DI, V4HI, and V2SF.
2150
2151 FIXME: We should probably return # and add post reload
2152 splitters for these, but this way is so easy ;-). */
2153 operands[1] = GEN_INT (cst);
2154 operands[2] = GEN_INT (cst2);
2155 if (cst == cst2)
2156 return "li %0,%1\n\tevmergelo %0,%0,%0";
2157 else
2158 return "li %0,%1\n\tevmergelo %0,%0,%0\n\tli %0,%2";
69ef87e2
AH		 2159}
2160
914c2e77 2161int
e1e2e653
NS		 2162mask64_1or2_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED,
2163 bool allow_one)
0ba1b2ff
AM		 2164{
2165 if (GET_CODE (op) == CONST_INT)
a260abc9 2166 {
0ba1b2ff 2167 HOST_WIDE_INT c, lsb;
e1e2e653
NS		 2168 bool one_ok;
2169
0ba1b2ff 2170 c = INTVAL (op);
a260abc9 2171
0ba1b2ff
AM		 2172 /* Disallow all zeros. */
2173 if (c == 0)
2174 return 0;
a260abc9 2175
e1e2e653
NS		 2176 /* We can use a single rlwinm insn if no upper bits of C are set
2177 AND there are zero, one or two transitions in the _whole_ of
2178 C. */
2179 one_ok = !(c & ~(HOST_WIDE_INT)0xffffffff);
2180
0ba1b2ff
AM		 2181 /* We don't change the number of transitions by inverting,
2182 so make sure we start with the LS bit zero. */
2183 if (c & 1)
2184 c = ~c;
a260abc9 2185
0ba1b2ff
AM		 2186 /* Find the first transition. */
2187 lsb = c & -c;
a260abc9 2188
0ba1b2ff
AM		 2189 /* Invert to look for a second transition. */
2190 c = ~c;
2191
2192 /* Erase first transition. */
2193 c &= -lsb;
2194
2195 /* Find the second transition. */
2196 lsb = c & -c;
2197
2198 /* Invert to look for a third transition. */
2199 c = ~c;
2200
2201 /* Erase second transition. */
2202 c &= -lsb;
2203
e1e2e653
NS		 2204 if (one_ok && !(allow_one || c))
2205 return 0;
2206
0ba1b2ff
AM		 2207 /* Find the third transition (if any). */
2208 lsb = c & -c;
2209
2210 /* Match if all the bits above are 1's (or c is zero). */
2211 return c == -lsb;
2212 }
2213 return 0;
2214}
2215
2216/* Generates shifts and masks for a pair of rldicl or rldicr insns to
2217 implement ANDing by the mask IN. */
2218void
a2369ed3 2219build_mask64_2_operands (rtx in, rtx *out)
0ba1b2ff
AM		 2220{
2221#if HOST_BITS_PER_WIDE_INT >= 64
2222 unsigned HOST_WIDE_INT c, lsb, m1, m2;
2223 int shift;
2224
37409796 2225 gcc_assert (GET_CODE (in) == CONST_INT);
0ba1b2ff
AM		 2226
2227 c = INTVAL (in);
2228 if (c & 1)
2229 {
2230 /* Assume c initially something like 0x00fff000000fffff. The idea
2231 is to rotate the word so that the middle ^^^^^^ group of zeros
2232 is at the MS end and can be cleared with an rldicl mask. We then
2233 rotate back and clear off the MS ^^ group of zeros with a
2234 second rldicl. */
2235 c = ~c; /* c == 0xff000ffffff00000 */
2236 lsb = c & -c; /* lsb == 0x0000000000100000 */
2237 m1 = -lsb; /* m1 == 0xfffffffffff00000 */
2238 c = ~c; /* c == 0x00fff000000fffff */
2239 c &= -lsb; /* c == 0x00fff00000000000 */
2240 lsb = c & -c; /* lsb == 0x0000100000000000 */
2241 c = ~c; /* c == 0xff000fffffffffff */
2242 c &= -lsb; /* c == 0xff00000000000000 */
2243 shift = 0;
2244 while ((lsb >>= 1) != 0)
2245 shift++; /* shift == 44 on exit from loop */
2246 m1 <<= 64 - shift; /* m1 == 0xffffff0000000000 */
2247 m1 = ~m1; /* m1 == 0x000000ffffffffff */
2248 m2 = ~c; /* m2 == 0x00ffffffffffffff */
a260abc9
DE		 2249 }
2250 else
0ba1b2ff
AM		 2251 {
2252 /* Assume c initially something like 0xff000f0000000000. The idea
2253 is to rotate the word so that the ^^^ middle group of zeros
2254 is at the LS end and can be cleared with an rldicr mask. We then
2255 rotate back and clear off the LS group of ^^^^^^^^^^ zeros with
2256 a second rldicr. */
2257 lsb = c & -c; /* lsb == 0x0000010000000000 */
2258 m2 = -lsb; /* m2 == 0xffffff0000000000 */
2259 c = ~c; /* c == 0x00fff0ffffffffff */
2260 c &= -lsb; /* c == 0x00fff00000000000 */
2261 lsb = c & -c; /* lsb == 0x0000100000000000 */
2262 c = ~c; /* c == 0xff000fffffffffff */
2263 c &= -lsb; /* c == 0xff00000000000000 */
2264 shift = 0;
2265 while ((lsb >>= 1) != 0)
2266 shift++; /* shift == 44 on exit from loop */
2267 m1 = ~c; /* m1 == 0x00ffffffffffffff */
2268 m1 >>= shift; /* m1 == 0x0000000000000fff */
2269 m1 = ~m1; /* m1 == 0xfffffffffffff000 */
2270 }
2271
2272 /* Note that when we only have two 0->1 and 1->0 transitions, one of the
2273 masks will be all 1's. We are guaranteed more than one transition. */
2274 out[0] = GEN_INT (64 - shift);
2275 out[1] = GEN_INT (m1);
2276 out[2] = GEN_INT (shift);
2277 out[3] = GEN_INT (m2);
2278#else
045572c7
GK		 2279 (void)in;
2280 (void)out;
37409796 2281 gcc_unreachable ();
0ba1b2ff 2282#endif
a260abc9
DE		 2283}
2284
54b695e7 2285/* Return TRUE if OP is an invalid SUBREG operation on the e500. */
48d72335
DE		 2286
2287bool
54b695e7
AH		 2288invalid_e500_subreg (rtx op, enum machine_mode mode)
2289{
2290 /* Reject (subreg:SI (reg:DF)). */
2291 if (GET_CODE (op) == SUBREG
2292 && mode == SImode
2293 && REG_P (SUBREG_REG (op))
2294 && GET_MODE (SUBREG_REG (op)) == DFmode)
2295 return true;
2296
2297 /* Reject (subreg:DF (reg:DI)). */
2298 if (GET_CODE (op) == SUBREG
2299 && mode == DFmode
2300 && REG_P (SUBREG_REG (op))
2301 && GET_MODE (SUBREG_REG (op)) == DImode)
2302 return true;
2303
2304 return false;
2305}
2306
95727fb8
AP		 2307/* Darwin, AIX increases natural record alignment to doubleword if the first
2308 field is an FP double while the FP fields remain word aligned. */
2309
19d66194 2310unsigned int
95727fb8
AP		 2311rs6000_special_round_type_align (tree type, int computed, int specified)
2312{
2313 tree field = TYPE_FIELDS (type);
95727fb8 2314
85962ac8
AP		 2315 /* Skip all non field decls */
2316 while (field != NULL && TREE_CODE (field) != FIELD_DECL)
95727fb8
AP		 2317 field = TREE_CHAIN (field);
2318
3ce5437a 2319 if (field == NULL || field == type || DECL_MODE (field) != DFmode)
95727fb8
AP		 2320 return MAX (computed, specified);
2321
2322 return MAX (MAX (computed, specified), 64);
2323}
2324
a4f6c312 2325/* Return 1 for an operand in small memory on V.4/eabi. */
7509c759
MM		 2326
2327int
f676971a 2328small_data_operand (rtx op ATTRIBUTE_UNUSED,
a2369ed3 2329 enum machine_mode mode ATTRIBUTE_UNUSED)
7509c759 2330{
38c1f2d7 2331#if TARGET_ELF
5f59ecb7 2332 rtx sym_ref;
7509c759 2333
d9407988 2334 if (rs6000_sdata == SDATA_NONE || rs6000_sdata == SDATA_DATA)
a54d04b7 2335 return 0;
a54d04b7 2336
f607bc57 2337 if (DEFAULT_ABI != ABI_V4)
7509c759
MM		 2338 return 0;
2339
88228c4b
MM		 2340 if (GET_CODE (op) == SYMBOL_REF)
2341 sym_ref = op;
2342
2343 else if (GET_CODE (op) != CONST
2344 || GET_CODE (XEXP (op, 0)) != PLUS
2345 || GET_CODE (XEXP (XEXP (op, 0), 0)) != SYMBOL_REF
2346 || GET_CODE (XEXP (XEXP (op, 0), 1)) != CONST_INT)
7509c759
MM		 2347 return 0;
2348
88228c4b 2349 else
dbf55e53
MM		 2350 {
2351 rtx sum = XEXP (op, 0);
2352 HOST_WIDE_INT summand;
2353
2354 /* We have to be careful here, because it is the referenced address
c4ad648e 2355 that must be 32k from _SDA_BASE_, not just the symbol. */
dbf55e53 2356 summand = INTVAL (XEXP (sum, 1));
307b599c 2357 if (summand < 0 || (unsigned HOST_WIDE_INT) summand > g_switch_value)
9390387d 2358 return 0;
dbf55e53
MM		 2359
2360 sym_ref = XEXP (sum, 0);
2361 }
88228c4b 2362
20bfcd69 2363 return SYMBOL_REF_SMALL_P (sym_ref);
d9407988
MM		 2364#else
2365 return 0;
2366#endif
7509c759 2367}
46c07df8 2368
3a1f863f 2369/* Return true if either operand is a general purpose register. */
46c07df8 2370
3a1f863f
DE		 2371bool
2372gpr_or_gpr_p (rtx op0, rtx op1)
46c07df8 2373{
3a1f863f
DE		 2374 return ((REG_P (op0) && INT_REGNO_P (REGNO (op0)))
2375 || (REG_P (op1) && INT_REGNO_P (REGNO (op1))));
46c07df8
HP		 2376}
2377
9ebbca7d 2378\f
4d588c14
RH		 2379/* Subroutines of rs6000_legitimize_address and rs6000_legitimate_address. */
2380
f676971a
EC		 2381static int
2382constant_pool_expr_1 (rtx op, int *have_sym, int *have_toc)
9ebbca7d 2383{
9390387d 2384 switch (GET_CODE (op))
9ebbca7d
GK		 2385 {
2386 case SYMBOL_REF:
c4501e62
JJ		 2387 if (RS6000_SYMBOL_REF_TLS_P (op))
2388 return 0;
2389 else if (CONSTANT_POOL_ADDRESS_P (op))
a4f6c312
SS		 2390 {
2391 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (op), Pmode))
2392 {
2393 *have_sym = 1;
2394 return 1;
2395 }
2396 else
2397 return 0;
2398 }
2399 else if (! strcmp (XSTR (op, 0), toc_label_name))
2400 {
2401 *have_toc = 1;
2402 return 1;
2403 }
2404 else
2405 return 0;
9ebbca7d
GK		 2406 case PLUS:
2407 case MINUS:
c1f11548
DE		 2408 return (constant_pool_expr_1 (XEXP (op, 0), have_sym, have_toc)
2409 && constant_pool_expr_1 (XEXP (op, 1), have_sym, have_toc));
9ebbca7d 2410 case CONST:
a4f6c312 2411 return constant_pool_expr_1 (XEXP (op, 0), have_sym, have_toc);
9ebbca7d 2412 case CONST_INT:
a4f6c312 2413 return 1;
9ebbca7d 2414 default:
a4f6c312 2415 return 0;
9ebbca7d
GK		 2416 }
2417}
2418
4d588c14 2419static bool
a2369ed3 2420constant_pool_expr_p (rtx op)
9ebbca7d
GK		 2421{
2422 int have_sym = 0;
2423 int have_toc = 0;
2424 return constant_pool_expr_1 (op, &have_sym, &have_toc) && have_sym;
2425}
2426
48d72335 2427bool
a2369ed3 2428toc_relative_expr_p (rtx op)
9ebbca7d 2429{
4d588c14
RH		 2430 int have_sym = 0;
2431 int have_toc = 0;
2432 return constant_pool_expr_1 (op, &have_sym, &have_toc) && have_toc;
2433}
2434
4d588c14 2435bool
a2369ed3 2436legitimate_constant_pool_address_p (rtx x)
4d588c14
RH		 2437{
2438 return (TARGET_TOC
2439 && GET_CODE (x) == PLUS
2440 && GET_CODE (XEXP (x, 0)) == REG
2441 && (TARGET_MINIMAL_TOC || REGNO (XEXP (x, 0)) == TOC_REGISTER)
2442 && constant_pool_expr_p (XEXP (x, 1)));
2443}
2444
2445static bool
a2369ed3 2446legitimate_small_data_p (enum machine_mode mode, rtx x)
4d588c14
RH		 2447{
2448 return (DEFAULT_ABI == ABI_V4
2449 && !flag_pic && !TARGET_TOC
2450 && (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST)
2451 && small_data_operand (x, mode));
2452}
2453
60cdabab
DE		 2454/* SPE offset addressing is limited to 5-bits worth of double words. */
2455#define SPE_CONST_OFFSET_OK(x) (((x) & ~0xf8) == 0)
2456
76d2b81d
DJ		 2457bool
2458rs6000_legitimate_offset_address_p (enum machine_mode mode, rtx x, int strict)
4d588c14
RH		 2459{
2460 unsigned HOST_WIDE_INT offset, extra;
2461
2462 if (GET_CODE (x) != PLUS)
2463 return false;
2464 if (GET_CODE (XEXP (x, 0)) != REG)
2465 return false;
2466 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict))
2467 return false;
60cdabab
DE		 2468 if (legitimate_constant_pool_address_p (x))
2469 return true;
4d588c14
RH		 2470 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
2471 return false;
2472
2473 offset = INTVAL (XEXP (x, 1));
2474 extra = 0;
2475 switch (mode)
2476 {
2477 case V16QImode:
2478 case V8HImode:
2479 case V4SFmode:
2480 case V4SImode:
2481 /* AltiVec vector modes. Only reg+reg addressing is valid here,
2482 which leaves the only valid constant offset of zero, which by
2483 canonicalization rules is also invalid. */
2484 return false;
2485
2486 case V4HImode:
2487 case V2SImode:
2488 case V1DImode:
2489 case V2SFmode:
2490 /* SPE vector modes. */
2491 return SPE_CONST_OFFSET_OK (offset);
2492
2493 case DFmode:
4d4cbc0e
AH		 2494 if (TARGET_E500_DOUBLE)
2495 return SPE_CONST_OFFSET_OK (offset);
2496
4d588c14 2497 case DImode:
54b695e7
AH		 2498 /* On e500v2, we may have:
2499
2500 (subreg:DF (mem:DI (plus (reg) (const_int))) 0).
2501
2502 Which gets addressed with evldd instructions. */
2503 if (TARGET_E500_DOUBLE)
2504 return SPE_CONST_OFFSET_OK (offset);
2505
3364872d 2506 if (mode == DFmode || !TARGET_POWERPC64)
4d588c14
RH		 2507 extra = 4;
2508 else if (offset & 3)
2509 return false;
2510 break;
2511
2512 case TFmode:
2513 case TImode:
3364872d 2514 if (mode == TFmode || !TARGET_POWERPC64)
4d588c14
RH		 2515 extra = 12;
2516 else if (offset & 3)
2517 return false;
2518 else
2519 extra = 8;
2520 break;
2521
2522 default:
2523 break;
2524 }
2525
b1917422
AM		 2526 offset += 0x8000;
2527 return (offset < 0x10000) && (offset + extra < 0x10000);
4d588c14
RH		 2528}
2529
2530static bool
a2369ed3 2531legitimate_indexed_address_p (rtx x, int strict)
4d588c14
RH		 2532{
2533 rtx op0, op1;
2534
2535 if (GET_CODE (x) != PLUS)
2536 return false;
850e8d3d 2537
4d588c14
RH		 2538 op0 = XEXP (x, 0);
2539 op1 = XEXP (x, 1);
2540
2541 if (!REG_P (op0) || !REG_P (op1))
2542 return false;
2543
2544 return ((INT_REG_OK_FOR_BASE_P (op0, strict)
2545 && INT_REG_OK_FOR_INDEX_P (op1, strict))
2546 || (INT_REG_OK_FOR_BASE_P (op1, strict)
2547 && INT_REG_OK_FOR_INDEX_P (op0, strict)));
9ebbca7d
GK		 2548}
2549
48d72335 2550inline bool
a2369ed3 2551legitimate_indirect_address_p (rtx x, int strict)
4d588c14
RH		 2552{
2553 return GET_CODE (x) == REG && INT_REG_OK_FOR_BASE_P (x, strict);
2554}
2555
48d72335 2556bool
4c81e946
FJ		 2557macho_lo_sum_memory_operand (rtx x, enum machine_mode mode)
2558{
c4ad648e 2559 if (!TARGET_MACHO || !flag_pic
9390387d 2560 || mode != SImode || GET_CODE (x) != MEM)
c4ad648e
AM		 2561 return false;
2562 x = XEXP (x, 0);
4c81e946
FJ		 2563
2564 if (GET_CODE (x) != LO_SUM)
2565 return false;
2566 if (GET_CODE (XEXP (x, 0)) != REG)
2567 return false;
2568 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), 0))
2569 return false;
2570 x = XEXP (x, 1);
2571
2572 return CONSTANT_P (x);
2573}
2574
4d588c14 2575static bool
a2369ed3 2576legitimate_lo_sum_address_p (enum machine_mode mode, rtx x, int strict)
4d588c14
RH		 2577{
2578 if (GET_CODE (x) != LO_SUM)
2579 return false;
2580 if (GET_CODE (XEXP (x, 0)) != REG)
2581 return false;
2582 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict))
2583 return false;
54b695e7
AH		 2584 /* Restrict addressing for DI because of our SUBREG hackery. */
2585 if (TARGET_E500_DOUBLE && (mode == DFmode || mode == DImode))
f82f556d 2586 return false;
4d588c14
RH		 2587 x = XEXP (x, 1);
2588
8622e235 2589 if (TARGET_ELF || TARGET_MACHO)
4d588c14 2590 {
a29077da 2591 if (DEFAULT_ABI != ABI_AIX && DEFAULT_ABI != ABI_DARWIN && flag_pic)
4d588c14
RH		 2592 return false;
2593 if (TARGET_TOC)
2594 return false;
2595 if (GET_MODE_NUNITS (mode) != 1)
2596 return false;
5e5f01b9 2597 if (GET_MODE_BITSIZE (mode) > 64
3c028f65
AM		 2598 || (GET_MODE_BITSIZE (mode) > 32 && !TARGET_POWERPC64
2599 && !(TARGET_HARD_FLOAT && TARGET_FPRS && mode == DFmode)))
4d588c14
RH		 2600 return false;
2601
2602 return CONSTANT_P (x);
2603 }
2604
2605 return false;
2606}
2607
2608
9ebbca7d
GK		 2609/* Try machine-dependent ways of modifying an illegitimate address
2610 to be legitimate. If we find one, return the new, valid address.
2611 This is used from only one place: `memory_address' in explow.c.
2612
a4f6c312
SS		 2613 OLDX is the address as it was before break_out_memory_refs was
2614 called. In some cases it is useful to look at this to decide what
2615 needs to be done.
9ebbca7d 2616
a4f6c312 2617 MODE is passed so that this function can use GO_IF_LEGITIMATE_ADDRESS.
9ebbca7d 2618
a4f6c312
SS		 2619 It is always safe for this function to do nothing. It exists to
2620 recognize opportunities to optimize the output.
9ebbca7d
GK		 2621
2622 On RS/6000, first check for the sum of a register with a constant
2623 integer that is out of range. If so, generate code to add the
2624 constant with the low-order 16 bits masked to the register and force
2625 this result into another register (this can be done with `cau').
2626 Then generate an address of REG+(CONST&0xffff), allowing for the
2627 possibility of bit 16 being a one.
2628
2629 Then check for the sum of a register and something not constant, try to
2630 load the other things into a register and return the sum. */
4d588c14 2631
9ebbca7d 2632rtx
a2369ed3
DJ		 2633rs6000_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
2634 enum machine_mode mode)
0ac081f6 2635{
c4501e62
JJ		 2636 if (GET_CODE (x) == SYMBOL_REF)
2637 {
2638 enum tls_model model = SYMBOL_REF_TLS_MODEL (x);
2639 if (model != 0)
2640 return rs6000_legitimize_tls_address (x, model);
2641 }
2642
f676971a 2643 if (GET_CODE (x) == PLUS
9ebbca7d
GK		 2644 && GET_CODE (XEXP (x, 0)) == REG
2645 && GET_CODE (XEXP (x, 1)) == CONST_INT
2646 && (unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 1)) + 0x8000) >= 0x10000)
f676971a 2647 {
9ebbca7d
GK		 2648 HOST_WIDE_INT high_int, low_int;
2649 rtx sum;
a65c591c
DE		 2650 low_int = ((INTVAL (XEXP (x, 1)) & 0xffff) ^ 0x8000) - 0x8000;
2651 high_int = INTVAL (XEXP (x, 1)) - low_int;
9ebbca7d
GK		 2652 sum = force_operand (gen_rtx_PLUS (Pmode, XEXP (x, 0),
2653 GEN_INT (high_int)), 0);
2654 return gen_rtx_PLUS (Pmode, sum, GEN_INT (low_int));
2655 }
f676971a 2656 else if (GET_CODE (x) == PLUS
9ebbca7d
GK		 2657 && GET_CODE (XEXP (x, 0)) == REG
2658 && GET_CODE (XEXP (x, 1)) != CONST_INT
6ac7bf2c 2659 && GET_MODE_NUNITS (mode) == 1
a3170dc6
AH		 2660 && ((TARGET_HARD_FLOAT && TARGET_FPRS)
2661 || TARGET_POWERPC64
54b695e7
AH		 2662 || (((mode != DImode && mode != DFmode) || TARGET_E500_DOUBLE)
2663 && mode != TFmode))
9ebbca7d
GK		 2664 && (TARGET_POWERPC64 || mode != DImode)
2665 && mode != TImode)
2666 {
2667 return gen_rtx_PLUS (Pmode, XEXP (x, 0),
2668 force_reg (Pmode, force_operand (XEXP (x, 1), 0)));
2669 }
0ac081f6
AH		 2670 else if (ALTIVEC_VECTOR_MODE (mode))
2671 {
2672 rtx reg;
2673
2674 /* Make sure both operands are registers. */
2675 if (GET_CODE (x) == PLUS)
9f85ed45 2676 return gen_rtx_PLUS (Pmode, force_reg (Pmode, XEXP (x, 0)),
0ac081f6
AH		 2677 force_reg (Pmode, XEXP (x, 1)));
2678
2679 reg = force_reg (Pmode, x);
2680 return reg;
2681 }
4d4cbc0e 2682 else if (SPE_VECTOR_MODE (mode)
54b695e7
AH		 2683 || (TARGET_E500_DOUBLE && (mode == DFmode
2684 || mode == DImode)))
a3170dc6 2685 {
54b695e7
AH		 2686 if (mode == DImode)
2687 return NULL_RTX;
a3170dc6
AH		 2688 /* We accept [reg + reg] and [reg + OFFSET]. */
2689
2690 if (GET_CODE (x) == PLUS)
c4ad648e
AM		 2691 {
2692 rtx op1 = XEXP (x, 0);
2693 rtx op2 = XEXP (x, 1);
a3170dc6 2694
c4ad648e 2695 op1 = force_reg (Pmode, op1);
a3170dc6 2696
c4ad648e
AM		 2697 if (GET_CODE (op2) != REG
2698 && (GET_CODE (op2) != CONST_INT
2699 || !SPE_CONST_OFFSET_OK (INTVAL (op2))))
2700 op2 = force_reg (Pmode, op2);
a3170dc6 2701
c4ad648e
AM		 2702 return gen_rtx_PLUS (Pmode, op1, op2);
2703 }
a3170dc6
AH		 2704
2705 return force_reg (Pmode, x);
2706 }
f1384257
AM		 2707 else if (TARGET_ELF
2708 && TARGET_32BIT
2709 && TARGET_NO_TOC
2710 && ! flag_pic
9ebbca7d 2711 && GET_CODE (x) != CONST_INT
f676971a 2712 && GET_CODE (x) != CONST_DOUBLE
9ebbca7d 2713 && CONSTANT_P (x)
6ac7bf2c
GK		 2714 && GET_MODE_NUNITS (mode) == 1
2715 && (GET_MODE_BITSIZE (mode) <= 32
a3170dc6 2716 || ((TARGET_HARD_FLOAT && TARGET_FPRS) && mode == DFmode)))
9ebbca7d
GK		 2717 {
2718 rtx reg = gen_reg_rtx (Pmode);
8a1977f3
GK		 2719 emit_insn (gen_elf_high (reg, x));
2720 return gen_rtx_LO_SUM (Pmode, reg, x);
9ebbca7d 2721 }
ee890fe2
SS		 2722 else if (TARGET_MACHO && TARGET_32BIT && TARGET_NO_TOC
2723 && ! flag_pic
ab82a49f
AP		 2724#if TARGET_MACHO
2725 && ! MACHO_DYNAMIC_NO_PIC_P
2726#endif
ee890fe2 2727 && GET_CODE (x) != CONST_INT
f676971a 2728 && GET_CODE (x) != CONST_DOUBLE
ee890fe2 2729 && CONSTANT_P (x)
f82f556d 2730 && ((TARGET_HARD_FLOAT && TARGET_FPRS) || mode != DFmode)
f676971a 2731 && mode != DImode
ee890fe2
SS		 2732 && mode != TImode)
2733 {
2734 rtx reg = gen_reg_rtx (Pmode);
8a1977f3
GK		 2735 emit_insn (gen_macho_high (reg, x));
2736 return gen_rtx_LO_SUM (Pmode, reg, x);
ee890fe2 2737 }
f676971a 2738 else if (TARGET_TOC
4d588c14 2739 && constant_pool_expr_p (x)
a9098fd0 2740 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x), Pmode))
9ebbca7d
GK		 2741 {
2742 return create_TOC_reference (x);
2743 }
2744 else
2745 return NULL_RTX;
2746}
258bfae2 2747
fdbe66f2 2748/* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
c973d557
JJ		 2749 We need to emit DTP-relative relocations. */
2750
fdbe66f2 2751static void
c973d557
JJ		 2752rs6000_output_dwarf_dtprel (FILE *file, int size, rtx x)
2753{
2754 switch (size)
2755 {
2756 case 4:
2757 fputs ("\t.long\t", file);
2758 break;
2759 case 8:
2760 fputs (DOUBLE_INT_ASM_OP, file);
2761 break;
2762 default:
37409796 2763 gcc_unreachable ();
c973d557
JJ		 2764 }
2765 output_addr_const (file, x);
2766 fputs ("@dtprel+0x8000", file);
2767}
2768
c4501e62
JJ		 2769/* Construct the SYMBOL_REF for the tls_get_addr function. */
2770
2771static GTY(()) rtx rs6000_tls_symbol;
2772static rtx
863d938c 2773rs6000_tls_get_addr (void)
c4501e62
JJ		 2774{
2775 if (!rs6000_tls_symbol)
2776 rs6000_tls_symbol = init_one_libfunc ("__tls_get_addr");
2777
2778 return rs6000_tls_symbol;
2779}
2780
2781/* Construct the SYMBOL_REF for TLS GOT references. */
2782
2783static GTY(()) rtx rs6000_got_symbol;
2784static rtx
863d938c 2785rs6000_got_sym (void)
c4501e62
JJ		 2786{
2787 if (!rs6000_got_symbol)
2788 {
2789 rs6000_got_symbol = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
2790 SYMBOL_REF_FLAGS (rs6000_got_symbol) |= SYMBOL_FLAG_LOCAL;
2791 SYMBOL_REF_FLAGS (rs6000_got_symbol) |= SYMBOL_FLAG_EXTERNAL;
f676971a 2792 }
c4501e62
JJ		 2793
2794 return rs6000_got_symbol;
2795}
2796
2797/* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
2798 this (thread-local) address. */
2799
2800static rtx
a2369ed3 2801rs6000_legitimize_tls_address (rtx addr, enum tls_model model)
c4501e62
JJ		 2802{
2803 rtx dest, insn;
2804
2805 dest = gen_reg_rtx (Pmode);
2806 if (model == TLS_MODEL_LOCAL_EXEC && rs6000_tls_size == 16)
2807 {
2808 rtx tlsreg;
2809
2810 if (TARGET_64BIT)
2811 {
2812 tlsreg = gen_rtx_REG (Pmode, 13);
2813 insn = gen_tls_tprel_64 (dest, tlsreg, addr);
2814 }
2815 else
2816 {
2817 tlsreg = gen_rtx_REG (Pmode, 2);
2818 insn = gen_tls_tprel_32 (dest, tlsreg, addr);
2819 }
2820 emit_insn (insn);
2821 }
2822 else if (model == TLS_MODEL_LOCAL_EXEC && rs6000_tls_size == 32)
2823 {
2824 rtx tlsreg, tmp;
2825
2826 tmp = gen_reg_rtx (Pmode);
2827 if (TARGET_64BIT)
2828 {
2829 tlsreg = gen_rtx_REG (Pmode, 13);
2830 insn = gen_tls_tprel_ha_64 (tmp, tlsreg, addr);
2831 }
2832 else
2833 {
2834 tlsreg = gen_rtx_REG (Pmode, 2);
2835 insn = gen_tls_tprel_ha_32 (tmp, tlsreg, addr);
2836 }
2837 emit_insn (insn);
2838 if (TARGET_64BIT)
2839 insn = gen_tls_tprel_lo_64 (dest, tmp, addr);
2840 else
2841 insn = gen_tls_tprel_lo_32 (dest, tmp, addr);
2842 emit_insn (insn);
2843 }
2844 else
2845 {
2846 rtx r3, got, tga, tmp1, tmp2, eqv;
2847
2848 if (TARGET_64BIT)
2849 got = gen_rtx_REG (Pmode, TOC_REGISTER);
2850 else
2851 {
2852 if (flag_pic == 1)
2853 got = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
2854 else
2855 {
2856 rtx gsym = rs6000_got_sym ();
2857 got = gen_reg_rtx (Pmode);
2858 if (flag_pic == 0)
2859 rs6000_emit_move (got, gsym, Pmode);
2860 else
2861 {
ccbca5e4 2862 rtx tempLR, tmp3, mem;
c4501e62
JJ		 2863 rtx first, last;
2864
c4501e62
JJ		 2865 tempLR = gen_reg_rtx (Pmode);
2866 tmp1 = gen_reg_rtx (Pmode);
2867 tmp2 = gen_reg_rtx (Pmode);
2868 tmp3 = gen_reg_rtx (Pmode);
542a8afa 2869 mem = gen_const_mem (Pmode, tmp1);
c4501e62 2870
ccbca5e4 2871 first = emit_insn (gen_load_toc_v4_PIC_1b (tempLR, gsym));
c4501e62
JJ		 2872 emit_move_insn (tmp1, tempLR);
2873 emit_move_insn (tmp2, mem);
2874 emit_insn (gen_addsi3 (tmp3, tmp1, tmp2));
2875 last = emit_move_insn (got, tmp3);
2876 REG_NOTES (last) = gen_rtx_EXPR_LIST (REG_EQUAL, gsym,
2877 REG_NOTES (last));
2878 REG_NOTES (first) = gen_rtx_INSN_LIST (REG_LIBCALL, last,
2879 REG_NOTES (first));
2880 REG_NOTES (last) = gen_rtx_INSN_LIST (REG_RETVAL, first,
2881 REG_NOTES (last));
2882 }
2883 }
2884 }
2885
2886 if (model == TLS_MODEL_GLOBAL_DYNAMIC)
2887 {
2888 r3 = gen_rtx_REG (Pmode, 3);
2889 if (TARGET_64BIT)
2890 insn = gen_tls_gd_64 (r3, got, addr);
2891 else
2892 insn = gen_tls_gd_32 (r3, got, addr);
2893 start_sequence ();
2894 emit_insn (insn);
2895 tga = gen_rtx_MEM (Pmode, rs6000_tls_get_addr ());
2896 insn = gen_call_value (r3, tga, const0_rtx, const0_rtx);
2897 insn = emit_call_insn (insn);
2898 CONST_OR_PURE_CALL_P (insn) = 1;
2899 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), r3);
2900 insn = get_insns ();
2901 end_sequence ();
2902 emit_libcall_block (insn, dest, r3, addr);
2903 }
2904 else if (model == TLS_MODEL_LOCAL_DYNAMIC)
2905 {
2906 r3 = gen_rtx_REG (Pmode, 3);
2907 if (TARGET_64BIT)
2908 insn = gen_tls_ld_64 (r3, got);
2909 else
2910 insn = gen_tls_ld_32 (r3, got);
2911 start_sequence ();
2912 emit_insn (insn);
2913 tga = gen_rtx_MEM (Pmode, rs6000_tls_get_addr ());
2914 insn = gen_call_value (r3, tga, const0_rtx, const0_rtx);
2915 insn = emit_call_insn (insn);
2916 CONST_OR_PURE_CALL_P (insn) = 1;
2917 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), r3);
2918 insn = get_insns ();
2919 end_sequence ();
2920 tmp1 = gen_reg_rtx (Pmode);
2921 eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
2922 UNSPEC_TLSLD);
2923 emit_libcall_block (insn, tmp1, r3, eqv);
2924 if (rs6000_tls_size == 16)
2925 {
2926 if (TARGET_64BIT)
2927 insn = gen_tls_dtprel_64 (dest, tmp1, addr);
2928 else
2929 insn = gen_tls_dtprel_32 (dest, tmp1, addr);
2930 }
2931 else if (rs6000_tls_size == 32)
2932 {
2933 tmp2 = gen_reg_rtx (Pmode);
2934 if (TARGET_64BIT)
2935 insn = gen_tls_dtprel_ha_64 (tmp2, tmp1, addr);
2936 else
2937 insn = gen_tls_dtprel_ha_32 (tmp2, tmp1, addr);
2938 emit_insn (insn);
2939 if (TARGET_64BIT)
2940 insn = gen_tls_dtprel_lo_64 (dest, tmp2, addr);
2941 else
2942 insn = gen_tls_dtprel_lo_32 (dest, tmp2, addr);
2943 }
2944 else
2945 {
2946 tmp2 = gen_reg_rtx (Pmode);
2947 if (TARGET_64BIT)
2948 insn = gen_tls_got_dtprel_64 (tmp2, got, addr);
2949 else
2950 insn = gen_tls_got_dtprel_32 (tmp2, got, addr);
2951 emit_insn (insn);
2952 insn = gen_rtx_SET (Pmode, dest,
2953 gen_rtx_PLUS (Pmode, tmp2, tmp1));
2954 }
2955 emit_insn (insn);
2956 }
2957 else
2958 {
2959 /* IE, or 64 bit offset LE. */
2960 tmp2 = gen_reg_rtx (Pmode);
2961 if (TARGET_64BIT)
2962 insn = gen_tls_got_tprel_64 (tmp2, got, addr);
2963 else
2964 insn = gen_tls_got_tprel_32 (tmp2, got, addr);
2965 emit_insn (insn);
2966 if (TARGET_64BIT)
2967 insn = gen_tls_tls_64 (dest, tmp2, addr);
2968 else
2969 insn = gen_tls_tls_32 (dest, tmp2, addr);
2970 emit_insn (insn);
2971 }
2972 }
2973
2974 return dest;
2975}
2976
c4501e62
JJ		 2977/* Return 1 if X contains a thread-local symbol. */
2978
2979bool
a2369ed3 2980rs6000_tls_referenced_p (rtx x)
c4501e62 2981{
cd413cab
AP		 2982 if (! TARGET_HAVE_TLS)
2983 return false;
2984
c4501e62
JJ		 2985 return for_each_rtx (&x, &rs6000_tls_symbol_ref_1, 0);
2986}
2987
2988/* Return 1 if *X is a thread-local symbol. This is the same as
2989 rs6000_tls_symbol_ref except for the type of the unused argument. */
2990
9390387d 2991static int
a2369ed3 2992rs6000_tls_symbol_ref_1 (rtx *x, void *data ATTRIBUTE_UNUSED)
c4501e62
JJ		 2993{
2994 return RS6000_SYMBOL_REF_TLS_P (*x);
2995}
2996
24ea750e
DJ		 2997/* The convention appears to be to define this wherever it is used.
2998 With legitimize_reload_address now defined here, REG_MODE_OK_FOR_BASE_P
2999 is now used here. */
3000#ifndef REG_MODE_OK_FOR_BASE_P
3001#define REG_MODE_OK_FOR_BASE_P(REGNO, MODE) REG_OK_FOR_BASE_P (REGNO)
3002#endif
3003
3004/* Our implementation of LEGITIMIZE_RELOAD_ADDRESS. Returns a value to
3005 replace the input X, or the original X if no replacement is called for.
3006 The output parameter *WIN is 1 if the calling macro should goto WIN,
3007 0 if it should not.
3008
3009 For RS/6000, we wish to handle large displacements off a base
3010 register by splitting the addend across an addiu/addis and the mem insn.
3011 This cuts number of extra insns needed from 3 to 1.
3012
3013 On Darwin, we use this to generate code for floating point constants.
3014 A movsf_low is generated so we wind up with 2 instructions rather than 3.
3015 The Darwin code is inside #if TARGET_MACHO because only then is
3016 machopic_function_base_name() defined. */
3017rtx
f676971a 3018rs6000_legitimize_reload_address (rtx x, enum machine_mode mode,
c4ad648e
AM		 3019 int opnum, int type,
3020 int ind_levels ATTRIBUTE_UNUSED, int *win)
24ea750e 3021{
f676971a 3022 /* We must recognize output that we have already generated ourselves. */
24ea750e
DJ		 3023 if (GET_CODE (x) == PLUS
3024 && GET_CODE (XEXP (x, 0)) == PLUS
3025 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
3026 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3027 && GET_CODE (XEXP (x, 1)) == CONST_INT)
3028 {
3029 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
c4ad648e
AM		 3030 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
3031 opnum, (enum reload_type)type);
24ea750e
DJ		 3032 *win = 1;
3033 return x;
3034 }
3deb2758 3035
24ea750e
DJ		 3036#if TARGET_MACHO
3037 if (DEFAULT_ABI == ABI_DARWIN && flag_pic
3038 && GET_CODE (x) == LO_SUM
3039 && GET_CODE (XEXP (x, 0)) == PLUS
3040 && XEXP (XEXP (x, 0), 0) == pic_offset_table_rtx
3041 && GET_CODE (XEXP (XEXP (x, 0), 1)) == HIGH
3042 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 1), 0)) == CONST
3043 && XEXP (XEXP (XEXP (x, 0), 1), 0) == XEXP (x, 1)
3044 && GET_CODE (XEXP (XEXP (x, 1), 0)) == MINUS
3045 && GET_CODE (XEXP (XEXP (XEXP (x, 1), 0), 0)) == SYMBOL_REF
3046 && GET_CODE (XEXP (XEXP (XEXP (x, 1), 0), 1)) == SYMBOL_REF)
3047 {
3048 /* Result of previous invocation of this function on Darwin
6f317ef3 3049 floating point constant. */
24ea750e 3050 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
c4ad648e
AM		 3051 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
3052 opnum, (enum reload_type)type);
24ea750e
DJ		 3053 *win = 1;
3054 return x;
3055 }
3056#endif
4937d02d
DE		 3057
3058 /* Force ld/std non-word aligned offset into base register by wrapping
3059 in offset 0. */
3060 if (GET_CODE (x) == PLUS
3061 && GET_CODE (XEXP (x, 0)) == REG
3062 && REGNO (XEXP (x, 0)) < 32
3063 && REG_MODE_OK_FOR_BASE_P (XEXP (x, 0), mode)
3064 && GET_CODE (XEXP (x, 1)) == CONST_INT
3065 && (INTVAL (XEXP (x, 1)) & 3) != 0
78796ad5 3066 && !ALTIVEC_VECTOR_MODE (mode)
4937d02d
DE		 3067 && GET_MODE_SIZE (mode) >= UNITS_PER_WORD
3068 && TARGET_POWERPC64)
3069 {
3070 x = gen_rtx_PLUS (GET_MODE (x), x, GEN_INT (0));
3071 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3072 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
3073 opnum, (enum reload_type) type);
3074 *win = 1;
3075 return x;
3076 }
3077
24ea750e
DJ		 3078 if (GET_CODE (x) == PLUS
3079 && GET_CODE (XEXP (x, 0)) == REG
3080 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
3081 && REG_MODE_OK_FOR_BASE_P (XEXP (x, 0), mode)
78c875e8 3082 && GET_CODE (XEXP (x, 1)) == CONST_INT
93638d7a 3083 && !SPE_VECTOR_MODE (mode)
54b695e7
AH		 3084 && !(TARGET_E500_DOUBLE && (mode == DFmode
3085 || mode == DImode))
78c875e8 3086 && !ALTIVEC_VECTOR_MODE (mode))
24ea750e
DJ		 3087 {
3088 HOST_WIDE_INT val = INTVAL (XEXP (x, 1));
3089 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
3090 HOST_WIDE_INT high
c4ad648e 3091 = (((val - low) & 0xffffffff) ^ 0x80000000) - 0x80000000;
24ea750e
DJ		 3092
3093 /* Check for 32-bit overflow. */
3094 if (high + low != val)
c4ad648e 3095 {
24ea750e
DJ		 3096 *win = 0;
3097 return x;
3098 }
3099
3100 /* Reload the high part into a base reg; leave the low part
c4ad648e 3101 in the mem directly. */
24ea750e
DJ		 3102
3103 x = gen_rtx_PLUS (GET_MODE (x),
c4ad648e
AM		 3104 gen_rtx_PLUS (GET_MODE (x), XEXP (x, 0),
3105 GEN_INT (high)),
3106 GEN_INT (low));
24ea750e
DJ		 3107
3108 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
c4ad648e
AM		 3109 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
3110 opnum, (enum reload_type)type);
24ea750e
DJ		 3111 *win = 1;
3112 return x;
3113 }
4937d02d 3114
24ea750e
DJ		 3115#if TARGET_MACHO
3116 if (GET_CODE (x) == SYMBOL_REF
3117 && DEFAULT_ABI == ABI_DARWIN
69ef87e2 3118 && !ALTIVEC_VECTOR_MODE (mode)
a29077da 3119 && (flag_pic || MACHO_DYNAMIC_NO_PIC_P)
0d8c1c97
AM		 3120 /* Don't do this for TFmode, since the result isn't offsettable.
3121 The same goes for DImode without 64-bit gprs. */
3122 && mode != TFmode
3123 && (mode != DImode || TARGET_POWERPC64))
24ea750e 3124 {
a29077da
GK		 3125 if (flag_pic)
3126 {
3127 rtx offset = gen_rtx_CONST (Pmode,
3128 gen_rtx_MINUS (Pmode, x,
11abc112 3129 machopic_function_base_sym ()));
a29077da
GK		 3130 x = gen_rtx_LO_SUM (GET_MODE (x),
3131 gen_rtx_PLUS (Pmode, pic_offset_table_rtx,
3132 gen_rtx_HIGH (Pmode, offset)), offset);
3133 }
3134 else
3135 x = gen_rtx_LO_SUM (GET_MODE (x),
c4ad648e 3136 gen_rtx_HIGH (Pmode, x), x);
a29077da 3137
24ea750e 3138 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
a29077da
GK		 3139 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
3140 opnum, (enum reload_type)type);
24ea750e
DJ		 3141 *win = 1;
3142 return x;
3143 }
3144#endif
4937d02d 3145
24ea750e 3146 if (TARGET_TOC
4d588c14 3147 && constant_pool_expr_p (x)
c1f11548 3148 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x), mode))
24ea750e
DJ		 3149 {
3150 (x) = create_TOC_reference (x);
3151 *win = 1;
3152 return x;
3153 }
3154 *win = 0;
3155 return x;
f676971a 3156}
24ea750e 3157
258bfae2
FS		 3158/* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
3159 that is a valid memory address for an instruction.
3160 The MODE argument is the machine mode for the MEM expression
3161 that wants to use this address.
3162
3163 On the RS/6000, there are four valid address: a SYMBOL_REF that
3164 refers to a constant pool entry of an address (or the sum of it
3165 plus a constant), a short (16-bit signed) constant plus a register,
3166 the sum of two registers, or a register indirect, possibly with an
5bdc5878 3167 auto-increment. For DFmode and DImode with a constant plus register,
258bfae2
FS		 3168 we must ensure that both words are addressable or PowerPC64 with offset
3169 word aligned.
3170
3171 For modes spanning multiple registers (DFmode in 32-bit GPRs,
76d2b81d 3172 32-bit DImode, TImode, TFmode), indexed addressing cannot be used because
258bfae2
FS		 3173 adjacent memory cells are accessed by adding word-sized offsets
3174 during assembly output. */
3175int
a2369ed3 3176rs6000_legitimate_address (enum machine_mode mode, rtx x, int reg_ok_strict)
258bfae2 3177{
850e8d3d
DN		 3178 /* If this is an unaligned stvx/ldvx type address, discard the outer AND. */
3179 if (TARGET_ALTIVEC
3180 && ALTIVEC_VECTOR_MODE (mode)
3181 && GET_CODE (x) == AND
3182 && GET_CODE (XEXP (x, 1)) == CONST_INT
3183 && INTVAL (XEXP (x, 1)) == -16)
3184 x = XEXP (x, 0);
3185
c4501e62
JJ		 3186 if (RS6000_SYMBOL_REF_TLS_P (x))
3187 return 0;
4d588c14 3188 if (legitimate_indirect_address_p (x, reg_ok_strict))
258bfae2
FS		 3189 return 1;
3190 if ((GET_CODE (x) == PRE_INC || GET_CODE (x) == PRE_DEC)
0d6d6892 3191 && !ALTIVEC_VECTOR_MODE (mode)
a3170dc6 3192 && !SPE_VECTOR_MODE (mode)
54b695e7
AH		 3193 /* Restrict addressing for DI because of our SUBREG hackery. */
3194 && !(TARGET_E500_DOUBLE && (mode == DFmode || mode == DImode))
258bfae2 3195 && TARGET_UPDATE
4d588c14 3196 && legitimate_indirect_address_p (XEXP (x, 0), reg_ok_strict))
258bfae2 3197 return 1;
4d588c14 3198 if (legitimate_small_data_p (mode, x))
258bfae2 3199 return 1;
4d588c14 3200 if (legitimate_constant_pool_address_p (x))
258bfae2
FS		 3201 return 1;
3202 /* If not REG_OK_STRICT (before reload) let pass any stack offset. */
3203 if (! reg_ok_strict
3204 && GET_CODE (x) == PLUS
3205 && GET_CODE (XEXP (x, 0)) == REG
708d2456 3206 && (XEXP (x, 0) == virtual_stack_vars_rtx
c4ad648e 3207 || XEXP (x, 0) == arg_pointer_rtx)
258bfae2
FS		 3208 && GET_CODE (XEXP (x, 1)) == CONST_INT)
3209 return 1;
76d2b81d 3210 if (rs6000_legitimate_offset_address_p (mode, x, reg_ok_strict))
258bfae2
FS		 3211 return 1;
3212 if (mode != TImode
76d2b81d 3213 && mode != TFmode
a3170dc6
AH		 3214 && ((TARGET_HARD_FLOAT && TARGET_FPRS)
3215 || TARGET_POWERPC64
4d4cbc0e 3216 || ((mode != DFmode || TARGET_E500_DOUBLE) && mode != TFmode))
258bfae2 3217 && (TARGET_POWERPC64 || mode != DImode)
4d588c14 3218 && legitimate_indexed_address_p (x, reg_ok_strict))
258bfae2 3219 return 1;
4d588c14 3220 if (legitimate_lo_sum_address_p (mode, x, reg_ok_strict))
258bfae2
FS		 3221 return 1;
3222 return 0;
3223}
4d588c14
RH		 3224
3225/* Go to LABEL if ADDR (a legitimate address expression)
3226 has an effect that depends on the machine mode it is used for.
3227
3228 On the RS/6000 this is true of all integral offsets (since AltiVec
3229 modes don't allow them) or is a pre-increment or decrement.
3230
3231 ??? Except that due to conceptual problems in offsettable_address_p
3232 we can't really report the problems of integral offsets. So leave
f676971a 3233 this assuming that the adjustable offset must be valid for the
4d588c14
RH		 3234 sub-words of a TFmode operand, which is what we had before. */
3235
3236bool
a2369ed3 3237rs6000_mode_dependent_address (rtx addr)
4d588c14
RH		 3238{
3239 switch (GET_CODE (addr))
3240 {
3241 case PLUS:
3242 if (GET_CODE (XEXP (addr, 1)) == CONST_INT)
3243 {
3244 unsigned HOST_WIDE_INT val = INTVAL (XEXP (addr, 1));
3245 return val + 12 + 0x8000 >= 0x10000;
3246 }
3247 break;
3248
3249 case LO_SUM:
3250 return true;
3251
3252 case PRE_INC:
3253 case PRE_DEC:
3254 return TARGET_UPDATE;
3255
3256 default:
3257 break;
3258 }
3259
3260 return false;
3261}
d8ecbcdb
AH		 3262
3263/* Return number of consecutive hard regs needed starting at reg REGNO
3264 to hold something of mode MODE.
3265 This is ordinarily the length in words of a value of mode MODE
3266 but can be less for certain modes in special long registers.
3267
3268 For the SPE, GPRs are 64 bits but only 32 bits are visible in
3269 scalar instructions. The upper 32 bits are only available to the
3270 SIMD instructions.
3271
3272 POWER and PowerPC GPRs hold 32 bits worth;
3273 PowerPC64 GPRs and FPRs point register holds 64 bits worth. */
3274
3275int
3276rs6000_hard_regno_nregs (int regno, enum machine_mode mode)
3277{
3278 if (FP_REGNO_P (regno))
3279 return (GET_MODE_SIZE (mode) + UNITS_PER_FP_WORD - 1) / UNITS_PER_FP_WORD;
3280
4d4cbc0e
AH		 3281 if (TARGET_E500_DOUBLE && mode == DFmode)
3282 return 1;
3283
d8ecbcdb
AH		 3284 if (SPE_SIMD_REGNO_P (regno) && TARGET_SPE && SPE_VECTOR_MODE (mode))
3285 return (GET_MODE_SIZE (mode) + UNITS_PER_SPE_WORD - 1) / UNITS_PER_SPE_WORD;
3286
3287 if (ALTIVEC_REGNO_P (regno))
3288 return
3289 (GET_MODE_SIZE (mode) + UNITS_PER_ALTIVEC_WORD - 1) / UNITS_PER_ALTIVEC_WORD;
3290
3291 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
3292}
2aa4498c
AH		 3293
3294/* Change register usage conditional on target flags. */
3295void
3296rs6000_conditional_register_usage (void)
3297{
3298 int i;
3299
3300 /* Set MQ register fixed (already call_used) if not POWER
3301 architecture (RIOS1, RIOS2, RSC, and PPC601) so that it will not
3302 be allocated. */
3303 if (! TARGET_POWER)
3304 fixed_regs[64] = 1;
3305
7c9ac5c0 3306 /* 64-bit AIX and Linux reserve GPR13 for thread-private data. */
2aa4498c
AH		 3307 if (TARGET_64BIT)
3308 fixed_regs[13] = call_used_regs[13]
3309 = call_really_used_regs[13] = 1;
3310
3311 /* Conditionally disable FPRs. */
3312 if (TARGET_SOFT_FLOAT || !TARGET_FPRS)
3313 for (i = 32; i < 64; i++)
3314 fixed_regs[i] = call_used_regs[i]
c4ad648e 3315 = call_really_used_regs[i] = 1;
2aa4498c 3316
7c9ac5c0
PH		 3317 /* The TOC register is not killed across calls in a way that is
3318 visible to the compiler. */
3319 if (DEFAULT_ABI == ABI_AIX)
3320 call_really_used_regs[2] = 0;
3321
2aa4498c
AH		 3322 if (DEFAULT_ABI == ABI_V4
3323 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM
3324 && flag_pic == 2)
3325 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
3326
3327 if (DEFAULT_ABI == ABI_V4
3328 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM
3329 && flag_pic == 1)
3330 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
3331 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
3332 = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
3333
3334 if (DEFAULT_ABI == ABI_DARWIN
3335 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM)
6d0a8091 3336 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
2aa4498c
AH		 3337 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
3338 = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
3339
b4db40bf
JJ		 3340 if (TARGET_TOC && TARGET_MINIMAL_TOC)
3341 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
3342 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
3343
2aa4498c
AH		 3344 if (TARGET_ALTIVEC)
3345 global_regs[VSCR_REGNO] = 1;
3346
3347 if (TARGET_SPE)
3348 {
3349 global_regs[SPEFSCR_REGNO] = 1;
3350 fixed_regs[FIXED_SCRATCH]
c4ad648e 3351 = call_used_regs[FIXED_SCRATCH]
2aa4498c
AH		 3352 = call_really_used_regs[FIXED_SCRATCH] = 1;
3353 }
3354
3355 if (! TARGET_ALTIVEC)
3356 {
3357 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
3358 fixed_regs[i] = call_used_regs[i] = call_really_used_regs[i] = 1;
3359 call_really_used_regs[VRSAVE_REGNO] = 1;
3360 }
3361
3362 if (TARGET_ALTIVEC_ABI)
3363 for (i = FIRST_ALTIVEC_REGNO; i < FIRST_ALTIVEC_REGNO + 20; ++i)
3364 call_used_regs[i] = call_really_used_regs[i] = 1;
3365}
fb4d4348 3366\f
a4f6c312
SS		 3367/* Try to output insns to set TARGET equal to the constant C if it can
3368 be done in less than N insns. Do all computations in MODE.
3369 Returns the place where the output has been placed if it can be
3370 done and the insns have been emitted. If it would take more than N
3371 insns, zero is returned and no insns and emitted. */
2bfcf297
DB		 3372
3373rtx
f676971a 3374rs6000_emit_set_const (rtx dest, enum machine_mode mode,
a2369ed3 3375 rtx source, int n ATTRIBUTE_UNUSED)
2bfcf297 3376{
af8cb5c5 3377 rtx result, insn, set;
2bfcf297
DB		 3378 HOST_WIDE_INT c0, c1;
3379
37409796 3380 switch (mode)
2bfcf297 3381 {
37409796
NS		 3382 case QImode:
3383 case HImode:
2bfcf297 3384 if (dest == NULL)
c4ad648e 3385 dest = gen_reg_rtx (mode);
2bfcf297
DB		 3386 emit_insn (gen_rtx_SET (VOIDmode, dest, source));
3387 return dest;
37409796
NS		 3388
3389 case SImode:
af8cb5c5 3390 result = no_new_pseudos ? dest : gen_reg_rtx (SImode);
37409796 3391
af8cb5c5
DE		 3392 emit_insn (gen_rtx_SET (VOIDmode, result,
3393 GEN_INT (INTVAL (source)
3394 & (~ (HOST_WIDE_INT) 0xffff))));
3395 emit_insn (gen_rtx_SET (VOIDmode, dest,
3396 gen_rtx_IOR (SImode, result,
3397 GEN_INT (INTVAL (source) & 0xffff))));
3398 result = dest;
37409796
NS		 3399 break;
3400
3401 case DImode:
3402 switch (GET_CODE (source))
af8cb5c5 3403 {
37409796 3404 case CONST_INT:
af8cb5c5
DE		 3405 c0 = INTVAL (source);
3406 c1 = -(c0 < 0);
37409796
NS		 3407 break;
3408
3409 case CONST_DOUBLE:
2bfcf297 3410#if HOST_BITS_PER_WIDE_INT >= 64
af8cb5c5
DE		 3411 c0 = CONST_DOUBLE_LOW (source);
3412 c1 = -(c0 < 0);
2bfcf297 3413#else
af8cb5c5
DE		 3414 c0 = CONST_DOUBLE_LOW (source);
3415 c1 = CONST_DOUBLE_HIGH (source);
2bfcf297 3416#endif
37409796
NS		 3417 break;
3418
3419 default:
3420 gcc_unreachable ();
af8cb5c5 3421 }
af8cb5c5
DE		 3422
3423 result = rs6000_emit_set_long_const (dest, c0, c1);
37409796
NS		 3424 break;
3425
3426 default:
3427 gcc_unreachable ();
2bfcf297 3428 }
2bfcf297 3429
af8cb5c5
DE		 3430 insn = get_last_insn ();
3431 set = single_set (insn);
3432 if (! CONSTANT_P (SET_SRC (set)))
3433 set_unique_reg_note (insn, REG_EQUAL, source);
3434
3435 return result;
2bfcf297
DB		 3436}
3437
3438/* Having failed to find a 3 insn sequence in rs6000_emit_set_const,
3439 fall back to a straight forward decomposition. We do this to avoid
3440 exponential run times encountered when looking for longer sequences
3441 with rs6000_emit_set_const. */
3442static rtx
a2369ed3 3443rs6000_emit_set_long_const (rtx dest, HOST_WIDE_INT c1, HOST_WIDE_INT c2)
2bfcf297
DB		 3444{
3445 if (!TARGET_POWERPC64)
3446 {
3447 rtx operand1, operand2;
3448
3449 operand1 = operand_subword_force (dest, WORDS_BIG_ENDIAN == 0,
3450 DImode);
3451 operand2 = operand_subword_force (dest, WORDS_BIG_ENDIAN != 0,
3452 DImode);
3453 emit_move_insn (operand1, GEN_INT (c1));
3454 emit_move_insn (operand2, GEN_INT (c2));
3455 }
3456 else
3457 {
bc06712d 3458 HOST_WIDE_INT ud1, ud2, ud3, ud4;
252b88f7 3459
bc06712d 3460 ud1 = c1 & 0xffff;
f921c9c9 3461 ud2 = (c1 & 0xffff0000) >> 16;
2bfcf297 3462#if HOST_BITS_PER_WIDE_INT >= 64
bc06712d 3463 c2 = c1 >> 32;
2bfcf297 3464#endif
bc06712d 3465 ud3 = c2 & 0xffff;
f921c9c9 3466 ud4 = (c2 & 0xffff0000) >> 16;
2bfcf297 3467
f676971a 3468 if ((ud4 == 0xffff && ud3 == 0xffff && ud2 == 0xffff && (ud1 & 0x8000))
bc06712d 3469 || (ud4 == 0 && ud3 == 0 && ud2 == 0 && ! (ud1 & 0x8000)))
2bfcf297 3470 {
bc06712d 3471 if (ud1 & 0x8000)
b78d48dd 3472 emit_move_insn (dest, GEN_INT (((ud1 ^ 0x8000) - 0x8000)));
bc06712d
TR		 3473 else
3474 emit_move_insn (dest, GEN_INT (ud1));
2bfcf297 3475 }
2bfcf297 3476
f676971a 3477 else if ((ud4 == 0xffff && ud3 == 0xffff && (ud2 & 0x8000))
bc06712d 3478 || (ud4 == 0 && ud3 == 0 && ! (ud2 & 0x8000)))
252b88f7 3479 {
bc06712d 3480 if (ud2 & 0x8000)
f676971a 3481 emit_move_insn (dest, GEN_INT (((ud2 << 16) ^ 0x80000000)
bc06712d 3482 - 0x80000000));
252b88f7 3483 else
bc06712d
TR		 3484 emit_move_insn (dest, GEN_INT (ud2 << 16));
3485 if (ud1 != 0)
3486 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud1)));
252b88f7 3487 }
f676971a 3488 else if ((ud4 == 0xffff && (ud3 & 0x8000))
bc06712d
TR		 3489 || (ud4 == 0 && ! (ud3 & 0x8000)))
3490 {
3491 if (ud3 & 0x8000)
f676971a 3492 emit_move_insn (dest, GEN_INT (((ud3 << 16) ^ 0x80000000)
bc06712d
TR		 3493 - 0x80000000));
3494 else
3495 emit_move_insn (dest, GEN_INT (ud3 << 16));
3496
3497 if (ud2 != 0)
3498 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud2)));
3499 emit_move_insn (dest, gen_rtx_ASHIFT (DImode, dest, GEN_INT (16)));
3500 if (ud1 != 0)
3501 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud1)));
3502 }
f676971a 3503 else
bc06712d
TR		 3504 {
3505 if (ud4 & 0x8000)
f676971a 3506 emit_move_insn (dest, GEN_INT (((ud4 << 16) ^ 0x80000000)
bc06712d
TR		 3507 - 0x80000000));
3508 else
3509 emit_move_insn (dest, GEN_INT (ud4 << 16));
3510
3511 if (ud3 != 0)
3512 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud3)));
2bfcf297 3513
bc06712d
TR		 3514 emit_move_insn (dest, gen_rtx_ASHIFT (DImode, dest, GEN_INT (32)));
3515 if (ud2 != 0)
f676971a
EC		 3516 emit_move_insn (dest, gen_rtx_IOR (DImode, dest,
3517 GEN_INT (ud2 << 16)));
bc06712d
TR		 3518 if (ud1 != 0)
3519 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud1)));
3520 }
3521 }
2bfcf297
DB		 3522 return dest;
3523}
3524
76d2b81d
DJ		 3525/* Helper for the following. Get rid of [r+r] memory refs
3526 in cases where it won't work (TImode, TFmode). */
3527
3528static void
3529rs6000_eliminate_indexed_memrefs (rtx operands[2])
3530{
3531 if (GET_CODE (operands[0]) == MEM
3532 && GET_CODE (XEXP (operands[0], 0)) != REG
55aa0757 3533 && ! legitimate_constant_pool_address_p (XEXP (operands[0], 0))
76d2b81d
DJ		 3534 && ! reload_in_progress)
3535 operands[0]
3536 = replace_equiv_address (operands[0],
3537 copy_addr_to_reg (XEXP (operands[0], 0)));
3538
3539 if (GET_CODE (operands[1]) == MEM
3540 && GET_CODE (XEXP (operands[1], 0)) != REG
55aa0757 3541 && ! legitimate_constant_pool_address_p (XEXP (operands[1], 0))
76d2b81d
DJ		 3542 && ! reload_in_progress)
3543 operands[1]
3544 = replace_equiv_address (operands[1],
3545 copy_addr_to_reg (XEXP (operands[1], 0)));
3546}
3547
fb4d4348
GK		 3548/* Emit a move from SOURCE to DEST in mode MODE. */
3549void
a2369ed3 3550rs6000_emit_move (rtx dest, rtx source, enum machine_mode mode)
fb4d4348
GK		 3551{
3552 rtx operands[2];
3553 operands[0] = dest;
3554 operands[1] = source;
f676971a 3555
fb4d4348
GK		 3556 /* Sanity checks. Check that we get CONST_DOUBLE only when we should. */
3557 if (GET_CODE (operands[1]) == CONST_DOUBLE
3558 && ! FLOAT_MODE_P (mode)
3559 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
3560 {
3561 /* FIXME. This should never happen. */
3562 /* Since it seems that it does, do the safe thing and convert
3563 to a CONST_INT. */
2496c7bd 3564 operands[1] = gen_int_mode (CONST_DOUBLE_LOW (operands[1]), mode);
fb4d4348 3565 }
37409796
NS		 3566 gcc_assert (GET_CODE (operands[1]) != CONST_DOUBLE
3567 || FLOAT_MODE_P (mode)
3568 || ((CONST_DOUBLE_HIGH (operands[1]) != 0
3569 || CONST_DOUBLE_LOW (operands[1]) < 0)
3570 && (CONST_DOUBLE_HIGH (operands[1]) != -1
3571 || CONST_DOUBLE_LOW (operands[1]) >= 0)));
3572
c9e8cb32
DD		 3573 /* Check if GCC is setting up a block move that will end up using FP
3574 registers as temporaries. We must make sure this is acceptable. */
3575 if (GET_CODE (operands[0]) == MEM
3576 && GET_CODE (operands[1]) == MEM
3577 && mode == DImode
41543739
GK		 3578 && (SLOW_UNALIGNED_ACCESS (DImode, MEM_ALIGN (operands[0]))
3579 || SLOW_UNALIGNED_ACCESS (DImode, MEM_ALIGN (operands[1])))
3580 && ! (SLOW_UNALIGNED_ACCESS (SImode, (MEM_ALIGN (operands[0]) > 32
3581 ? 32 : MEM_ALIGN (operands[0])))
3582 || SLOW_UNALIGNED_ACCESS (SImode, (MEM_ALIGN (operands[1]) > 32
f676971a 3583 ? 32
41543739
GK		 3584 : MEM_ALIGN (operands[1]))))
3585 && ! MEM_VOLATILE_P (operands [0])
3586 && ! MEM_VOLATILE_P (operands [1]))
c9e8cb32 3587 {
41543739
GK		 3588 emit_move_insn (adjust_address (operands[0], SImode, 0),
3589 adjust_address (operands[1], SImode, 0));
3590 emit_move_insn (adjust_address (operands[0], SImode, 4),
3591 adjust_address (operands[1], SImode, 4));
c9e8cb32
DD		 3592 return;
3593 }
630d42a0 3594
55aa0757 3595 if (!no_new_pseudos && GET_CODE (operands[0]) == MEM
c9dbf840 3596 && !gpc_reg_operand (operands[1], mode))
f6219a5e 3597 operands[1] = force_reg (mode, operands[1]);
a9098fd0 3598
a3170dc6
AH		 3599 if (mode == SFmode && ! TARGET_POWERPC
3600 && TARGET_HARD_FLOAT && TARGET_FPRS
ffc14f31 3601 && GET_CODE (operands[0]) == MEM)
fb4d4348 3602 {
ffc14f31
GK		 3603 int regnum;
3604
3605 if (reload_in_progress || reload_completed)
3606 regnum = true_regnum (operands[1]);
3607 else if (GET_CODE (operands[1]) == REG)
3608 regnum = REGNO (operands[1]);
3609 else
3610 regnum = -1;
f676971a 3611
fb4d4348
GK		 3612 /* If operands[1] is a register, on POWER it may have
3613 double-precision data in it, so truncate it to single
3614 precision. */
3615 if (FP_REGNO_P (regnum) || regnum >= FIRST_PSEUDO_REGISTER)
3616 {
3617 rtx newreg;
3618 newreg = (no_new_pseudos ? operands[1] : gen_reg_rtx (mode));
3619 emit_insn (gen_aux_truncdfsf2 (newreg, operands[1]));
3620 operands[1] = newreg;
3621 }
3622 }
3623
c4501e62
JJ		 3624 /* Recognize the case where operand[1] is a reference to thread-local
3625 data and load its address to a register. */
84f52ebd 3626 if (rs6000_tls_referenced_p (operands[1]))
c4501e62 3627 {
84f52ebd
RH		 3628 enum tls_model model;
3629 rtx tmp = operands[1];
3630 rtx addend = NULL;
3631
3632 if (GET_CODE (tmp) == CONST && GET_CODE (XEXP (tmp, 0)) == PLUS)
3633 {
3634 addend = XEXP (XEXP (tmp, 0), 1);
3635 tmp = XEXP (XEXP (tmp, 0), 0);
3636 }
3637
3638 gcc_assert (GET_CODE (tmp) == SYMBOL_REF);
3639 model = SYMBOL_REF_TLS_MODEL (tmp);
3640 gcc_assert (model != 0);
3641
3642 tmp = rs6000_legitimize_tls_address (tmp, model);
3643 if (addend)
3644 {
3645 tmp = gen_rtx_PLUS (mode, tmp, addend);
3646 tmp = force_operand (tmp, operands[0]);
3647 }
3648 operands[1] = tmp;
c4501e62
JJ		 3649 }
3650
8f4e6caf
RH		 3651 /* Handle the case where reload calls us with an invalid address. */
3652 if (reload_in_progress && mode == Pmode
69ef87e2 3653 && (! general_operand (operands[1], mode)
8f4e6caf
RH		 3654 || ! nonimmediate_operand (operands[0], mode)))
3655 goto emit_set;
3656
a9baceb1
GK		 3657 /* 128-bit constant floating-point values on Darwin should really be
3658 loaded as two parts. */
3659 if ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
3660 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128
3661 && mode == TFmode && GET_CODE (operands[1]) == CONST_DOUBLE)
3662 {
3663 /* DImode is used, not DFmode, because simplify_gen_subreg doesn't
3664 know how to get a DFmode SUBREG of a TFmode. */
3665 rs6000_emit_move (simplify_gen_subreg (DImode, operands[0], mode, 0),
3666 simplify_gen_subreg (DImode, operands[1], mode, 0),
3667 DImode);
3668 rs6000_emit_move (simplify_gen_subreg (DImode, operands[0], mode,
3669 GET_MODE_SIZE (DImode)),
3670 simplify_gen_subreg (DImode, operands[1], mode,
3671 GET_MODE_SIZE (DImode)),
3672 DImode);
3673 return;
3674 }
3675
fb4d4348
GK		 3676 /* FIXME: In the long term, this switch statement should go away
3677 and be replaced by a sequence of tests based on things like
3678 mode == Pmode. */
3679 switch (mode)
3680 {
3681 case HImode:
3682 case QImode:
3683 if (CONSTANT_P (operands[1])
3684 && GET_CODE (operands[1]) != CONST_INT)
a9098fd0 3685 operands[1] = force_const_mem (mode, operands[1]);
fb4d4348
GK		 3686 break;
3687
06f4e019 3688 case TFmode:
76d2b81d
DJ		 3689 rs6000_eliminate_indexed_memrefs (operands);
3690 /* fall through */
3691
fb4d4348
GK		 3692 case DFmode:
3693 case SFmode:
f676971a 3694 if (CONSTANT_P (operands[1])
fb4d4348 3695 && ! easy_fp_constant (operands[1], mode))
a9098fd0 3696 operands[1] = force_const_mem (mode, operands[1]);
fb4d4348 3697 break;
f676971a 3698
0ac081f6
AH		 3699 case V16QImode:
3700 case V8HImode:
3701 case V4SFmode:
3702 case V4SImode:
a3170dc6
AH		 3703 case V4HImode:
3704 case V2SFmode:
3705 case V2SImode:
00a892b8 3706 case V1DImode:
69ef87e2 3707 if (CONSTANT_P (operands[1])
d744e06e 3708 && !easy_vector_constant (operands[1], mode))
0ac081f6
AH		 3709 operands[1] = force_const_mem (mode, operands[1]);
3710 break;
f676971a 3711
fb4d4348 3712 case SImode:
a9098fd0 3713 case DImode:
fb4d4348
GK		 3714 /* Use default pattern for address of ELF small data */
3715 if (TARGET_ELF
a9098fd0 3716 && mode == Pmode
f607bc57 3717 && DEFAULT_ABI == ABI_V4
f676971a 3718 && (GET_CODE (operands[1]) == SYMBOL_REF
a9098fd0
GK		 3719 || GET_CODE (operands[1]) == CONST)
3720 && small_data_operand (operands[1], mode))
fb4d4348
GK		 3721 {
3722 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
3723 return;
3724 }
3725
f607bc57 3726 if (DEFAULT_ABI == ABI_V4
a9098fd0
GK		 3727 && mode == Pmode && mode == SImode
3728 && flag_pic == 1 && got_operand (operands[1], mode))
fb4d4348
GK		 3729 {
3730 emit_insn (gen_movsi_got (operands[0], operands[1]));
3731 return;
3732 }
3733
ee890fe2 3734 if ((TARGET_ELF || DEFAULT_ABI == ABI_DARWIN)
f1384257
AM		 3735 && TARGET_NO_TOC
3736 && ! flag_pic
a9098fd0 3737 && mode == Pmode
fb4d4348
GK		 3738 && CONSTANT_P (operands[1])
3739 && GET_CODE (operands[1]) != HIGH
3740 && GET_CODE (operands[1]) != CONST_INT)
3741 {
a9098fd0 3742 rtx target = (no_new_pseudos ? operands[0] : gen_reg_rtx (mode));
fb4d4348
GK		 3743
3744 /* If this is a function address on -mcall-aixdesc,
3745 convert it to the address of the descriptor. */
3746 if (DEFAULT_ABI == ABI_AIX
3747 && GET_CODE (operands[1]) == SYMBOL_REF
3748 && XSTR (operands[1], 0)[0] == '.')
3749 {
3750 const char *name = XSTR (operands[1], 0);
3751 rtx new_ref;
3752 while (*name == '.')
3753 name++;
3754 new_ref = gen_rtx_SYMBOL_REF (Pmode, name);
3755 CONSTANT_POOL_ADDRESS_P (new_ref)
3756 = CONSTANT_POOL_ADDRESS_P (operands[1]);
d1908feb 3757 SYMBOL_REF_FLAGS (new_ref) = SYMBOL_REF_FLAGS (operands[1]);
fb4d4348 3758 SYMBOL_REF_USED (new_ref) = SYMBOL_REF_USED (operands[1]);
d1908feb 3759 SYMBOL_REF_DECL (new_ref) = SYMBOL_REF_DECL (operands[1]);
fb4d4348
GK		 3760 operands[1] = new_ref;
3761 }
7509c759 3762
ee890fe2
SS		 3763 if (DEFAULT_ABI == ABI_DARWIN)
3764 {
ab82a49f
AP		 3765#if TARGET_MACHO
3766 if (MACHO_DYNAMIC_NO_PIC_P)
3767 {
3768 /* Take care of any required data indirection. */
3769 operands[1] = rs6000_machopic_legitimize_pic_address (
3770 operands[1], mode, operands[0]);
3771 if (operands[0] != operands[1])
3772 emit_insn (gen_rtx_SET (VOIDmode,
c4ad648e 3773 operands[0], operands[1]));
ab82a49f
AP		 3774 return;
3775 }
3776#endif
b8a55285
AP		 3777 emit_insn (gen_macho_high (target, operands[1]));
3778 emit_insn (gen_macho_low (operands[0], target, operands[1]));
ee890fe2
SS		 3779 return;
3780 }
3781
fb4d4348
GK		 3782 emit_insn (gen_elf_high (target, operands[1]));
3783 emit_insn (gen_elf_low (operands[0], target, operands[1]));
3784 return;
3785 }
3786
a9098fd0
GK		 3787 /* If this is a SYMBOL_REF that refers to a constant pool entry,
3788 and we have put it in the TOC, we just need to make a TOC-relative
3789 reference to it. */
3790 if (TARGET_TOC
3791 && GET_CODE (operands[1]) == SYMBOL_REF
4d588c14 3792 && constant_pool_expr_p (operands[1])
a9098fd0
GK		 3793 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (operands[1]),
3794 get_pool_mode (operands[1])))
fb4d4348 3795 {
a9098fd0 3796 operands[1] = create_TOC_reference (operands[1]);
fb4d4348 3797 }
a9098fd0
GK		 3798 else if (mode == Pmode
3799 && CONSTANT_P (operands[1])
38886f37
AO		 3800 && ((GET_CODE (operands[1]) != CONST_INT
3801 && ! easy_fp_constant (operands[1], mode))
3802 || (GET_CODE (operands[1]) == CONST_INT
3803 && num_insns_constant (operands[1], mode) > 2)
3804 || (GET_CODE (operands[0]) == REG
3805 && FP_REGNO_P (REGNO (operands[0]))))
a9098fd0 3806 && GET_CODE (operands[1]) != HIGH
4d588c14
RH		 3807 && ! legitimate_constant_pool_address_p (operands[1])
3808 && ! toc_relative_expr_p (operands[1]))
fb4d4348
GK		 3809 {
3810 /* Emit a USE operation so that the constant isn't deleted if
3811 expensive optimizations are turned on because nobody
3812 references it. This should only be done for operands that
3813 contain SYMBOL_REFs with CONSTANT_POOL_ADDRESS_P set.
3814 This should not be done for operands that contain LABEL_REFs.
3815 For now, we just handle the obvious case. */
3816 if (GET_CODE (operands[1]) != LABEL_REF)
3817 emit_insn (gen_rtx_USE (VOIDmode, operands[1]));
3818
c859cda6 3819#if TARGET_MACHO
ee890fe2 3820 /* Darwin uses a special PIC legitimizer. */
ab82a49f 3821 if (DEFAULT_ABI == ABI_DARWIN && MACHOPIC_INDIRECT)
ee890fe2 3822 {
ee890fe2
SS		 3823 operands[1] =
3824 rs6000_machopic_legitimize_pic_address (operands[1], mode,
c859cda6
DJ		 3825 operands[0]);
3826 if (operands[0] != operands[1])
3827 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
ee890fe2
SS		 3828 return;
3829 }
c859cda6 3830#endif
ee890fe2 3831
fb4d4348
GK		 3832 /* If we are to limit the number of things we put in the TOC and
3833 this is a symbol plus a constant we can add in one insn,
3834 just put the symbol in the TOC and add the constant. Don't do
3835 this if reload is in progress. */
3836 if (GET_CODE (operands[1]) == CONST
3837 && TARGET_NO_SUM_IN_TOC && ! reload_in_progress
3838 && GET_CODE (XEXP (operands[1], 0)) == PLUS
a9098fd0 3839 && add_operand (XEXP (XEXP (operands[1], 0), 1), mode)
fb4d4348
GK		 3840 && (GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == LABEL_REF
3841 || GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == SYMBOL_REF)
3842 && ! side_effects_p (operands[0]))
3843 {
a4f6c312
SS		 3844 rtx sym =
3845 force_const_mem (mode, XEXP (XEXP (operands[1], 0), 0));
fb4d4348
GK		 3846 rtx other = XEXP (XEXP (operands[1], 0), 1);
3847
a9098fd0
GK		 3848 sym = force_reg (mode, sym);
3849 if (mode == SImode)
3850 emit_insn (gen_addsi3 (operands[0], sym, other));
3851 else
3852 emit_insn (gen_adddi3 (operands[0], sym, other));
fb4d4348
GK		 3853 return;
3854 }
3855
a9098fd0 3856 operands[1] = force_const_mem (mode, operands[1]);
fb4d4348 3857
f676971a 3858 if (TARGET_TOC
4d588c14 3859 && constant_pool_expr_p (XEXP (operands[1], 0))
d34c5b80
DE		 3860 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (
3861 get_pool_constant (XEXP (operands[1], 0)),
3862 get_pool_mode (XEXP (operands[1], 0))))
a9098fd0 3863 {
ba4828e0 3864 operands[1]
542a8afa 3865 = gen_const_mem (mode,
c4ad648e 3866 create_TOC_reference (XEXP (operands[1], 0)));
ba4828e0 3867 set_mem_alias_set (operands[1], get_TOC_alias_set ());
a9098fd0 3868 }
fb4d4348
GK		 3869 }
3870 break;
a9098fd0 3871
fb4d4348 3872 case TImode:
76d2b81d
DJ		 3873 rs6000_eliminate_indexed_memrefs (operands);
3874
27dc0551
DE		 3875 if (TARGET_POWER)
3876 {
3877 emit_insn (gen_rtx_PARALLEL (VOIDmode,
3878 gen_rtvec (2,
3879 gen_rtx_SET (VOIDmode,
3880 operands[0], operands[1]),
3881 gen_rtx_CLOBBER (VOIDmode,
3882 gen_rtx_SCRATCH (SImode)))));
3883 return;
3884 }
fb4d4348
GK		 3885 break;
3886
3887 default:
37409796 3888 gcc_unreachable ();
fb4d4348
GK		 3889 }
3890
a9098fd0
GK		 3891 /* Above, we may have called force_const_mem which may have returned
3892 an invalid address. If we can, fix this up; otherwise, reload will
3893 have to deal with it. */
8f4e6caf
RH		 3894 if (GET_CODE (operands[1]) == MEM && ! reload_in_progress)
3895 operands[1] = validize_mem (operands[1]);
a9098fd0 3896
8f4e6caf 3897 emit_set:
fb4d4348
GK		 3898 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
3899}
4697a36c 3900\f
2858f73a
GK		 3901/* Nonzero if we can use a floating-point register to pass this arg. */
3902#define USE_FP_FOR_ARG_P(CUM,MODE,TYPE) \
3903 (GET_MODE_CLASS (MODE) == MODE_FLOAT \
3904 && (CUM)->fregno <= FP_ARG_MAX_REG \
3905 && TARGET_HARD_FLOAT && TARGET_FPRS)
3906
3907/* Nonzero if we can use an AltiVec register to pass this arg. */
3908#define USE_ALTIVEC_FOR_ARG_P(CUM,MODE,TYPE,NAMED) \
3909 (ALTIVEC_VECTOR_MODE (MODE) \
3910 && (CUM)->vregno <= ALTIVEC_ARG_MAX_REG \
3911 && TARGET_ALTIVEC_ABI \
83953138 3912 && (NAMED))
2858f73a 3913
c6e8c921
GK		 3914/* Return a nonzero value to say to return the function value in
3915 memory, just as large structures are always returned. TYPE will be
3916 the data type of the value, and FNTYPE will be the type of the
3917 function doing the returning, or @code{NULL} for libcalls.
3918
3919 The AIX ABI for the RS/6000 specifies that all structures are
3920 returned in memory. The Darwin ABI does the same. The SVR4 ABI
3921 specifies that structures <= 8 bytes are returned in r3/r4, but a
3922 draft put them in memory, and GCC used to implement the draft
df01da37 3923 instead of the final standard. Therefore, aix_struct_return
c6e8c921
GK		 3924 controls this instead of DEFAULT_ABI; V.4 targets needing backward
3925 compatibility can change DRAFT_V4_STRUCT_RET to override the
3926 default, and -m switches get the final word. See
3927 rs6000_override_options for more details.
3928
3929 The PPC32 SVR4 ABI uses IEEE double extended for long double, if 128-bit
3930 long double support is enabled. These values are returned in memory.
3931
3932 int_size_in_bytes returns -1 for variable size objects, which go in
3933 memory always. The cast to unsigned makes -1 > 8. */
3934
3935static bool
3936rs6000_return_in_memory (tree type, tree fntype ATTRIBUTE_UNUSED)
3937{
594a51fe
SS		 3938 /* In the darwin64 abi, try to use registers for larger structs
3939 if possible. */
0b5383eb 3940 if (rs6000_darwin64_abi
594a51fe 3941 && TREE_CODE (type) == RECORD_TYPE
0b5383eb
DJ		 3942 && int_size_in_bytes (type) > 0)
3943 {
3944 CUMULATIVE_ARGS valcum;
3945 rtx valret;
3946
3947 valcum.words = 0;
3948 valcum.fregno = FP_ARG_MIN_REG;
3949 valcum.vregno = ALTIVEC_ARG_MIN_REG;
3950 /* Do a trial code generation as if this were going to be passed
3951 as an argument; if any part goes in memory, we return NULL. */
3952 valret = rs6000_darwin64_record_arg (&valcum, type, 1, true);
3953 if (valret)
3954 return false;
3955 /* Otherwise fall through to more conventional ABI rules. */
3956 }
594a51fe 3957
c6e8c921 3958 if (AGGREGATE_TYPE_P (type)
df01da37 3959 && (aix_struct_return
c6e8c921
GK		 3960 || (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 8))
3961 return true;
b693336b 3962
bada2eb8
DE		 3963 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
3964 modes only exist for GCC vector types if -maltivec. */
3965 if (TARGET_32BIT && !TARGET_ALTIVEC_ABI
3966 && ALTIVEC_VECTOR_MODE (TYPE_MODE (type)))
3967 return false;
3968
b693336b
PB		 3969 /* Return synthetic vectors in memory. */
3970 if (TREE_CODE (type) == VECTOR_TYPE
ad630bef 3971 && int_size_in_bytes (type) > (TARGET_ALTIVEC_ABI ? 16 : 8))
b693336b
PB		 3972 {
3973 static bool warned_for_return_big_vectors = false;
3974 if (!warned_for_return_big_vectors)
3975 {
d4ee4d25 3976 warning (0, "GCC vector returned by reference: "
b693336b
PB		 3977 "non-standard ABI extension with no compatibility guarantee");
3978 warned_for_return_big_vectors = true;
3979 }
3980 return true;
3981 }
3982
c6e8c921
GK		 3983 if (DEFAULT_ABI == ABI_V4 && TYPE_MODE (type) == TFmode)
3984 return true;
ad630bef 3985
c6e8c921
GK		 3986 return false;
3987}
3988
4697a36c
MM		 3989/* Initialize a variable CUM of type CUMULATIVE_ARGS
3990 for a call to a function whose data type is FNTYPE.
3991 For a library call, FNTYPE is 0.
3992
3993 For incoming args we set the number of arguments in the prototype large
1c20ae99 3994 so we never return a PARALLEL. */
4697a36c
MM		 3995
3996void
f676971a 3997init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype,
0f6937fe
AM		 3998 rtx libname ATTRIBUTE_UNUSED, int incoming,
3999 int libcall, int n_named_args)
4697a36c
MM		 4000{
4001 static CUMULATIVE_ARGS zero_cumulative;
4002
4003 *cum = zero_cumulative;
4004 cum->words = 0;
4005 cum->fregno = FP_ARG_MIN_REG;
0ac081f6 4006 cum->vregno = ALTIVEC_ARG_MIN_REG;
4697a36c 4007 cum->prototype = (fntype && TYPE_ARG_TYPES (fntype));
ddcc8263
DE		 4008 cum->call_cookie = ((DEFAULT_ABI == ABI_V4 && libcall)
4009 ? CALL_LIBCALL : CALL_NORMAL);
4cc833b7 4010 cum->sysv_gregno = GP_ARG_MIN_REG;
a6c9bed4
AH		 4011 cum->stdarg = fntype
4012 && (TYPE_ARG_TYPES (fntype) != 0
4013 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype)))
4014 != void_type_node));
4697a36c 4015
0f6937fe
AM		 4016 cum->nargs_prototype = 0;
4017 if (incoming || cum->prototype)
4018 cum->nargs_prototype = n_named_args;
4697a36c 4019
a5c76ee6 4020 /* Check for a longcall attribute. */
3eb4e360
AM		 4021 if ((!fntype && rs6000_default_long_calls)
4022 || (fntype
4023 && lookup_attribute ("longcall", TYPE_ATTRIBUTES (fntype))
4024 && !lookup_attribute ("shortcall", TYPE_ATTRIBUTES (fntype))))
4025 cum->call_cookie |= CALL_LONG;
6a4cee5f 4026
4697a36c
MM		 4027 if (TARGET_DEBUG_ARG)
4028 {
4029 fprintf (stderr, "\ninit_cumulative_args:");
4030 if (fntype)
4031 {
4032 tree ret_type = TREE_TYPE (fntype);
4033 fprintf (stderr, " ret code = %s,",
4034 tree_code_name[ (int)TREE_CODE (ret_type) ]);
4035 }
4036
6a4cee5f
MM		 4037 if (cum->call_cookie & CALL_LONG)
4038 fprintf (stderr, " longcall,");
4039
4697a36c
MM		 4040 fprintf (stderr, " proto = %d, nargs = %d\n",
4041 cum->prototype, cum->nargs_prototype);
4042 }
f676971a 4043
c4ad648e
AM		 4044 if (fntype
4045 && !TARGET_ALTIVEC
4046 && TARGET_ALTIVEC_ABI
4047 && ALTIVEC_VECTOR_MODE (TYPE_MODE (TREE_TYPE (fntype))))
4048 {
4049 error ("Cannot return value in vector register because"
4050 " altivec instructions are disabled, use -maltivec"
4051 " to enable them.");
4052 }
4697a36c
MM		 4053}
4054\f
fe984136
RH		 4055/* Return true if TYPE must be passed on the stack and not in registers. */
4056
4057static bool
4058rs6000_must_pass_in_stack (enum machine_mode mode, tree type)
4059{
4060 if (DEFAULT_ABI == ABI_AIX || TARGET_64BIT)
4061 return must_pass_in_stack_var_size (mode, type);
4062 else
4063 return must_pass_in_stack_var_size_or_pad (mode, type);
4064}
4065
c229cba9
DE		 4066/* If defined, a C expression which determines whether, and in which
4067 direction, to pad out an argument with extra space. The value
4068 should be of type `enum direction': either `upward' to pad above
4069 the argument, `downward' to pad below, or `none' to inhibit
4070 padding.
4071
4072 For the AIX ABI structs are always stored left shifted in their
4073 argument slot. */
4074
9ebbca7d 4075enum direction
a2369ed3 4076function_arg_padding (enum machine_mode mode, tree type)
c229cba9 4077{
6e985040
AM		 4078#ifndef AGGREGATE_PADDING_FIXED
4079#define AGGREGATE_PADDING_FIXED 0
4080#endif
4081#ifndef AGGREGATES_PAD_UPWARD_ALWAYS
4082#define AGGREGATES_PAD_UPWARD_ALWAYS 0
4083#endif
4084
4085 if (!AGGREGATE_PADDING_FIXED)
4086 {
4087 /* GCC used to pass structures of the same size as integer types as
4088 if they were in fact integers, ignoring FUNCTION_ARG_PADDING.
19525b57 4089 i.e. Structures of size 1 or 2 (or 4 when TARGET_64BIT) were
6e985040
AM		 4090 passed padded downward, except that -mstrict-align further
4091 muddied the water in that multi-component structures of 2 and 4
4092 bytes in size were passed padded upward.
4093
4094 The following arranges for best compatibility with previous
4095 versions of gcc, but removes the -mstrict-align dependency. */
4096 if (BYTES_BIG_ENDIAN)
4097 {
4098 HOST_WIDE_INT size = 0;
4099
4100 if (mode == BLKmode)
4101 {
4102 if (type && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST)
4103 size = int_size_in_bytes (type);
4104 }
4105 else
4106 size = GET_MODE_SIZE (mode);
4107
4108 if (size == 1 || size == 2 || size == 4)
4109 return downward;
4110 }
4111 return upward;
4112 }
4113
4114 if (AGGREGATES_PAD_UPWARD_ALWAYS)
4115 {
4116 if (type != 0 && AGGREGATE_TYPE_P (type))
4117 return upward;
4118 }
c229cba9 4119
d3704c46
KH		 4120 /* Fall back to the default. */
4121 return DEFAULT_FUNCTION_ARG_PADDING (mode, type);
c229cba9
DE		 4122}
4123
b6c9286a 4124/* If defined, a C expression that gives the alignment boundary, in bits,
f676971a 4125 of an argument with the specified mode and type. If it is not defined,
b6c9286a 4126 PARM_BOUNDARY is used for all arguments.
f676971a 4127
b693336b
PB		 4128 V.4 wants long longs to be double word aligned.
4129 Doubleword align SPE vectors.
4130 Quadword align Altivec vectors.
4131 Quadword align large synthetic vector types. */
b6c9286a
MM		 4132
4133int
b693336b 4134function_arg_boundary (enum machine_mode mode, tree type)
b6c9286a 4135{
4ed78545
AM		 4136 if (DEFAULT_ABI == ABI_V4 && GET_MODE_SIZE (mode) == 8)
4137 return 64;
ad630bef
DE		 4138 else if (SPE_VECTOR_MODE (mode)
4139 || (type && TREE_CODE (type) == VECTOR_TYPE
4140 && int_size_in_bytes (type) >= 8
4141 && int_size_in_bytes (type) < 16))
e1f83b4d 4142 return 64;
ad630bef
DE		 4143 else if (ALTIVEC_VECTOR_MODE (mode)
4144 || (type && TREE_CODE (type) == VECTOR_TYPE
4145 && int_size_in_bytes (type) >= 16))
0ac081f6 4146 return 128;
0b5383eb
DJ		 4147 else if (rs6000_darwin64_abi && mode == BLKmode
4148 && type && TYPE_ALIGN (type) > 64)
4149 return 128;
9ebbca7d 4150 else
b6c9286a 4151 return PARM_BOUNDARY;
b6c9286a 4152}
c53bdcf5 4153
294bd182
AM		 4154/* For a function parm of MODE and TYPE, return the starting word in
4155 the parameter area. NWORDS of the parameter area are already used. */
4156
4157static unsigned int
4158rs6000_parm_start (enum machine_mode mode, tree type, unsigned int nwords)
4159{
4160 unsigned int align;
4161 unsigned int parm_offset;
4162
4163 align = function_arg_boundary (mode, type) / PARM_BOUNDARY - 1;
4164 parm_offset = DEFAULT_ABI == ABI_V4 ? 2 : 6;
4165 return nwords + (-(parm_offset + nwords) & align);
4166}
4167
c53bdcf5
AM		 4168/* Compute the size (in words) of a function argument. */
4169
4170static unsigned long
4171rs6000_arg_size (enum machine_mode mode, tree type)
4172{
4173 unsigned long size;
4174
4175 if (mode != BLKmode)
4176 size = GET_MODE_SIZE (mode);
4177 else
4178 size = int_size_in_bytes (type);
4179
4180 if (TARGET_32BIT)
4181 return (size + 3) >> 2;
4182 else
4183 return (size + 7) >> 3;
4184}
b6c9286a 4185\f
0b5383eb 4186/* Use this to flush pending int fields. */
594a51fe
SS		 4187
4188static void
0b5383eb
DJ		 4189rs6000_darwin64_record_arg_advance_flush (CUMULATIVE_ARGS *cum,
4190 HOST_WIDE_INT bitpos)
594a51fe 4191{
0b5383eb
DJ		 4192 unsigned int startbit, endbit;
4193 int intregs, intoffset;
4194 enum machine_mode mode;
594a51fe 4195
0b5383eb
DJ		 4196 if (cum->intoffset == -1)
4197 return;
594a51fe 4198
0b5383eb
DJ		 4199 intoffset = cum->intoffset;
4200 cum->intoffset = -1;
4201
4202 if (intoffset % BITS_PER_WORD != 0)
4203 {
4204 mode = mode_for_size (BITS_PER_WORD - intoffset % BITS_PER_WORD,
4205 MODE_INT, 0);
4206 if (mode == BLKmode)
594a51fe 4207 {
0b5383eb
DJ		 4208 /* We couldn't find an appropriate mode, which happens,
4209 e.g., in packed structs when there are 3 bytes to load.
4210 Back intoffset back to the beginning of the word in this
4211 case. */
4212 intoffset = intoffset & -BITS_PER_WORD;
594a51fe 4213 }
594a51fe 4214 }
0b5383eb
DJ		 4215
4216 startbit = intoffset & -BITS_PER_WORD;
4217 endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD;
4218 intregs = (endbit - startbit) / BITS_PER_WORD;
4219 cum->words += intregs;
4220}
4221
4222/* The darwin64 ABI calls for us to recurse down through structs,
4223 looking for elements passed in registers. Unfortunately, we have
4224 to track int register count here also because of misalignments
4225 in powerpc alignment mode. */
4226
4227static void
4228rs6000_darwin64_record_arg_advance_recurse (CUMULATIVE_ARGS *cum,
4229 tree type,
4230 HOST_WIDE_INT startbitpos)
4231{
4232 tree f;
4233
4234 for (f = TYPE_FIELDS (type); f ; f = TREE_CHAIN (f))
4235 if (TREE_CODE (f) == FIELD_DECL)
4236 {
4237 HOST_WIDE_INT bitpos = startbitpos;
4238 tree ftype = TREE_TYPE (f);
4239 enum machine_mode mode = TYPE_MODE (ftype);
4240
4241 if (DECL_SIZE (f) != 0
4242 && host_integerp (bit_position (f), 1))
4243 bitpos += int_bit_position (f);
4244
4245 /* ??? FIXME: else assume zero offset. */
4246
4247 if (TREE_CODE (ftype) == RECORD_TYPE)
4248 rs6000_darwin64_record_arg_advance_recurse (cum, ftype, bitpos);
4249 else if (USE_FP_FOR_ARG_P (cum, mode, ftype))
4250 {
4251 rs6000_darwin64_record_arg_advance_flush (cum, bitpos);
4252 cum->fregno += (GET_MODE_SIZE (mode) + 7) >> 3;
4253 cum->words += (GET_MODE_SIZE (mode) + 7) >> 3;
4254 }
4255 else if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, 1))
4256 {
4257 rs6000_darwin64_record_arg_advance_flush (cum, bitpos);
4258 cum->vregno++;
4259 cum->words += 2;
4260 }
4261 else if (cum->intoffset == -1)
4262 cum->intoffset = bitpos;
4263 }
594a51fe
SS		 4264}
4265
4697a36c
MM		 4266/* Update the data in CUM to advance over an argument
4267 of mode MODE and data type TYPE.
b2d04ecf
AM		 4268 (TYPE is null for libcalls where that information may not be available.)
4269
4270 Note that for args passed by reference, function_arg will be called
4271 with MODE and TYPE set to that of the pointer to the arg, not the arg
4272 itself. */
4697a36c
MM		 4273
4274void
f676971a 4275function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
594a51fe 4276 tree type, int named, int depth)
4697a36c 4277{
0b5383eb
DJ		 4278 int size;
4279
594a51fe
SS		 4280 /* Only tick off an argument if we're not recursing. */
4281 if (depth == 0)
4282 cum->nargs_prototype--;
4697a36c 4283
ad630bef
DE		 4284 if (TARGET_ALTIVEC_ABI
4285 && (ALTIVEC_VECTOR_MODE (mode)
4286 || (type && TREE_CODE (type) == VECTOR_TYPE
4287 && int_size_in_bytes (type) == 16)))
0ac081f6 4288 {
4ed78545
AM		 4289 bool stack = false;
4290
2858f73a 4291 if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named))
c4ad648e 4292 {
6d0ef01e
HP		 4293 cum->vregno++;
4294 if (!TARGET_ALTIVEC)
4295 error ("Cannot pass argument in vector register because"
4296 " altivec instructions are disabled, use -maltivec"
4297 " to enable them.");
4ed78545
AM		 4298
4299 /* PowerPC64 Linux and AIX allocate GPRs for a vector argument
f676971a 4300 even if it is going to be passed in a vector register.
4ed78545
AM		 4301 Darwin does the same for variable-argument functions. */
4302 if ((DEFAULT_ABI == ABI_AIX && TARGET_64BIT)
4303 || (cum->stdarg && DEFAULT_ABI != ABI_V4))
4304 stack = true;
6d0ef01e 4305 }
4ed78545
AM		 4306 else
4307 stack = true;
4308
4309 if (stack)
c4ad648e 4310 {
a594a19c 4311 int align;
f676971a 4312
2858f73a
GK		 4313 /* Vector parameters must be 16-byte aligned. This places
4314 them at 2 mod 4 in terms of words in 32-bit mode, since
4315 the parameter save area starts at offset 24 from the
4316 stack. In 64-bit mode, they just have to start on an
4317 even word, since the parameter save area is 16-byte
4318 aligned. Space for GPRs is reserved even if the argument
4319 will be passed in memory. */
4320 if (TARGET_32BIT)
4ed78545 4321 align = (2 - cum->words) & 3;
2858f73a
GK		 4322 else
4323 align = cum->words & 1;
c53bdcf5 4324 cum->words += align + rs6000_arg_size (mode, type);
f676971a 4325
a594a19c
GK		 4326 if (TARGET_DEBUG_ARG)
4327 {
f676971a 4328 fprintf (stderr, "function_adv: words = %2d, align=%d, ",
a594a19c
GK		 4329 cum->words, align);
4330 fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s\n",
f676971a 4331 cum->nargs_prototype, cum->prototype,
2858f73a 4332 GET_MODE_NAME (mode));
a594a19c
GK		 4333 }
4334 }
0ac081f6 4335 }
a4b0320c 4336 else if (TARGET_SPE_ABI && TARGET_SPE && SPE_VECTOR_MODE (mode)
a6c9bed4
AH		 4337 && !cum->stdarg
4338 && cum->sysv_gregno <= GP_ARG_MAX_REG)
a4b0320c 4339 cum->sysv_gregno++;
594a51fe
SS		 4340
4341 else if (rs6000_darwin64_abi
4342 && mode == BLKmode
0b5383eb
DJ		 4343 && TREE_CODE (type) == RECORD_TYPE
4344 && (size = int_size_in_bytes (type)) > 0)
4345 {
4346 /* Variable sized types have size == -1 and are
4347 treated as if consisting entirely of ints.
4348 Pad to 16 byte boundary if needed. */
4349 if (TYPE_ALIGN (type) >= 2 * BITS_PER_WORD
4350 && (cum->words % 2) != 0)
4351 cum->words++;
4352 /* For varargs, we can just go up by the size of the struct. */
4353 if (!named)
4354 cum->words += (size + 7) / 8;
4355 else
4356 {
4357 /* It is tempting to say int register count just goes up by
4358 sizeof(type)/8, but this is wrong in a case such as
4359 { int; double; int; } [powerpc alignment]. We have to
4360 grovel through the fields for these too. */
4361 cum->intoffset = 0;
4362 rs6000_darwin64_record_arg_advance_recurse (cum, type, 0);
4363 rs6000_darwin64_record_arg_advance_flush (cum,
4364 size * BITS_PER_UNIT);
4365 }
4366 }
f607bc57 4367 else if (DEFAULT_ABI == ABI_V4)
4697a36c 4368 {
a3170dc6 4369 if (TARGET_HARD_FLOAT && TARGET_FPRS
4cc833b7 4370 && (mode == SFmode || mode == DFmode))
4697a36c 4371 {
4cc833b7
RH		 4372 if (cum->fregno <= FP_ARG_V4_MAX_REG)
4373 cum->fregno++;
4374 else
4375 {
4376 if (mode == DFmode)
c4ad648e 4377 cum->words += cum->words & 1;
c53bdcf5 4378 cum->words += rs6000_arg_size (mode, type);
4cc833b7 4379 }
4697a36c 4380 }
4cc833b7
RH		 4381 else
4382 {
b2d04ecf 4383 int n_words = rs6000_arg_size (mode, type);
4cc833b7
RH		 4384 int gregno = cum->sysv_gregno;
4385
4ed78545
AM		 4386 /* Long long and SPE vectors are put in (r3,r4), (r5,r6),
4387 (r7,r8) or (r9,r10). As does any other 2 word item such
4388 as complex int due to a historical mistake. */
4389 if (n_words == 2)
4390 gregno += (1 - gregno) & 1;
4cc833b7 4391
4ed78545 4392 /* Multi-reg args are not split between registers and stack. */
4cc833b7
RH		 4393 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
4394 {
4ed78545
AM		 4395 /* Long long and SPE vectors are aligned on the stack.
4396 So are other 2 word items such as complex int due to
4397 a historical mistake. */
4cc833b7
RH		 4398 if (n_words == 2)
4399 cum->words += cum->words & 1;
4400 cum->words += n_words;
4401 }
4697a36c 4402
4cc833b7
RH		 4403 /* Note: continuing to accumulate gregno past when we've started
4404 spilling to the stack indicates the fact that we've started
4405 spilling to the stack to expand_builtin_saveregs. */
4406 cum->sysv_gregno = gregno + n_words;
4407 }
4697a36c 4408
4cc833b7
RH		 4409 if (TARGET_DEBUG_ARG)
4410 {
4411 fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ",
4412 cum->words, cum->fregno);
4413 fprintf (stderr, "gregno = %2d, nargs = %4d, proto = %d, ",
4414 cum->sysv_gregno, cum->nargs_prototype, cum->prototype);
4415 fprintf (stderr, "mode = %4s, named = %d\n",
4416 GET_MODE_NAME (mode), named);
4417 }
4697a36c
MM		 4418 }
4419 else
4cc833b7 4420 {
b2d04ecf 4421 int n_words = rs6000_arg_size (mode, type);
294bd182
AM		 4422 int start_words = cum->words;
4423 int align_words = rs6000_parm_start (mode, type, start_words);
a4f6c312 4424
294bd182 4425 cum->words = align_words + n_words;
4697a36c 4426
a3170dc6
AH		 4427 if (GET_MODE_CLASS (mode) == MODE_FLOAT
4428 && TARGET_HARD_FLOAT && TARGET_FPRS)
c53bdcf5 4429 cum->fregno += (GET_MODE_SIZE (mode) + 7) >> 3;
4cc833b7
RH		 4430
4431 if (TARGET_DEBUG_ARG)
4432 {
4433 fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ",
4434 cum->words, cum->fregno);
4435 fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s, ",
4436 cum->nargs_prototype, cum->prototype, GET_MODE_NAME (mode));
594a51fe 4437 fprintf (stderr, "named = %d, align = %d, depth = %d\n",
294bd182 4438 named, align_words - start_words, depth);
4cc833b7
RH		 4439 }
4440 }
4697a36c 4441}
a6c9bed4 4442
f82f556d
AH		 4443static rtx
4444spe_build_register_parallel (enum machine_mode mode, int gregno)
4445{
54b695e7 4446 rtx r1, r3;
f82f556d 4447
37409796 4448 switch (mode)
f82f556d 4449 {
37409796 4450 case DFmode:
54b695e7
AH		 4451 r1 = gen_rtx_REG (DImode, gregno);
4452 r1 = gen_rtx_EXPR_LIST (VOIDmode, r1, const0_rtx);
4453 return gen_rtx_PARALLEL (mode, gen_rtvec (1, r1));
37409796
NS		 4454
4455 case DCmode:
54b695e7
AH		 4456 r1 = gen_rtx_REG (DImode, gregno);
4457 r1 = gen_rtx_EXPR_LIST (VOIDmode, r1, const0_rtx);
4458 r3 = gen_rtx_REG (DImode, gregno + 2);
4459 r3 = gen_rtx_EXPR_LIST (VOIDmode, r3, GEN_INT (8));
4460 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r3));
37409796
NS		 4461
4462 default:
4463 gcc_unreachable ();
f82f556d 4464 }
f82f556d 4465}
b78d48dd 4466
f82f556d 4467/* Determine where to put a SIMD argument on the SPE. */
a6c9bed4 4468static rtx
f676971a 4469rs6000_spe_function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
a2369ed3 4470 tree type)
a6c9bed4 4471{
f82f556d
AH		 4472 int gregno = cum->sysv_gregno;
4473
4474 /* On E500 v2, double arithmetic is done on the full 64-bit GPR, but
600e1f95 4475 are passed and returned in a pair of GPRs for ABI compatibility. */
18f63bfa 4476 if (TARGET_E500_DOUBLE && (mode == DFmode || mode == DCmode))
f82f556d 4477 {
b5870bee
AH		 4478 int n_words = rs6000_arg_size (mode, type);
4479
f82f556d 4480 /* Doubles go in an odd/even register pair (r5/r6, etc). */
b5870bee
AH		 4481 if (mode == DFmode)
4482 gregno += (1 - gregno) & 1;
f82f556d 4483
b5870bee
AH		 4484 /* Multi-reg args are not split between registers and stack. */
4485 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
f82f556d
AH		 4486 return NULL_RTX;
4487
4488 return spe_build_register_parallel (mode, gregno);
4489 }
a6c9bed4
AH		 4490 if (cum->stdarg)
4491 {
c53bdcf5 4492 int n_words = rs6000_arg_size (mode, type);
a6c9bed4
AH		 4493
4494 /* SPE vectors are put in odd registers. */
4495 if (n_words == 2 && (gregno & 1) == 0)
4496 gregno += 1;
4497
4498 if (gregno + n_words - 1 <= GP_ARG_MAX_REG)
4499 {
4500 rtx r1, r2;
4501 enum machine_mode m = SImode;
4502
4503 r1 = gen_rtx_REG (m, gregno);
4504 r1 = gen_rtx_EXPR_LIST (m, r1, const0_rtx);
4505 r2 = gen_rtx_REG (m, gregno + 1);
4506 r2 = gen_rtx_EXPR_LIST (m, r2, GEN_INT (4));
4507 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r2));
4508 }
4509 else
b78d48dd 4510 return NULL_RTX;
a6c9bed4
AH		 4511 }
4512 else
4513 {
f82f556d
AH		 4514 if (gregno <= GP_ARG_MAX_REG)
4515 return gen_rtx_REG (mode, gregno);
a6c9bed4 4516 else
b78d48dd 4517 return NULL_RTX;
a6c9bed4
AH		 4518 }
4519}
4520
0b5383eb
DJ		 4521/* A subroutine of rs6000_darwin64_record_arg. Assign the bits of the
4522 structure between cum->intoffset and bitpos to integer registers. */
594a51fe 4523
0b5383eb
DJ		 4524static void
4525rs6000_darwin64_record_arg_flush (CUMULATIVE_ARGS *cum,
4526 HOST_WIDE_INT bitpos, rtx rvec[], int *k)
594a51fe 4527{
0b5383eb
DJ		 4528 enum machine_mode mode;
4529 unsigned int regno;
4530 unsigned int startbit, endbit;
4531 int this_regno, intregs, intoffset;
4532 rtx reg;
594a51fe 4533
0b5383eb
DJ		 4534 if (cum->intoffset == -1)
4535 return;
4536
4537 intoffset = cum->intoffset;
4538 cum->intoffset = -1;
4539
4540 /* If this is the trailing part of a word, try to only load that
4541 much into the register. Otherwise load the whole register. Note
4542 that in the latter case we may pick up unwanted bits. It's not a
4543 problem at the moment but may wish to revisit. */
4544
4545 if (intoffset % BITS_PER_WORD != 0)
594a51fe 4546 {
0b5383eb
DJ		 4547 mode = mode_for_size (BITS_PER_WORD - intoffset % BITS_PER_WORD,
4548 MODE_INT, 0);
4549 if (mode == BLKmode)
4550 {
4551 /* We couldn't find an appropriate mode, which happens,
4552 e.g., in packed structs when there are 3 bytes to load.
4553 Back intoffset back to the beginning of the word in this
4554 case. */
4555 intoffset = intoffset & -BITS_PER_WORD;
4556 mode = word_mode;
4557 }
4558 }
4559 else
4560 mode = word_mode;
4561
4562 startbit = intoffset & -BITS_PER_WORD;
4563 endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD;
4564 intregs = (endbit - startbit) / BITS_PER_WORD;
4565 this_regno = cum->words + intoffset / BITS_PER_WORD;
4566
4567 if (intregs > 0 && intregs > GP_ARG_NUM_REG - this_regno)
4568 cum->use_stack = 1;
4569
4570 intregs = MIN (intregs, GP_ARG_NUM_REG - this_regno);
4571 if (intregs <= 0)
4572 return;
4573
4574 intoffset /= BITS_PER_UNIT;
4575 do
4576 {
4577 regno = GP_ARG_MIN_REG + this_regno;
4578 reg = gen_rtx_REG (mode, regno);
4579 rvec[(*k)++] =
4580 gen_rtx_EXPR_LIST (VOIDmode, reg, GEN_INT (intoffset));
4581
4582 this_regno += 1;
4583 intoffset = (intoffset | (UNITS_PER_WORD-1)) + 1;
4584 mode = word_mode;
4585 intregs -= 1;
4586 }
4587 while (intregs > 0);
4588}
4589
4590/* Recursive workhorse for the following. */
4591
4592static void
4593rs6000_darwin64_record_arg_recurse (CUMULATIVE_ARGS *cum, tree type,
4594 HOST_WIDE_INT startbitpos, rtx rvec[],
4595 int *k)
4596{
4597 tree f;
4598
4599 for (f = TYPE_FIELDS (type); f ; f = TREE_CHAIN (f))
4600 if (TREE_CODE (f) == FIELD_DECL)
4601 {
4602 HOST_WIDE_INT bitpos = startbitpos;
4603 tree ftype = TREE_TYPE (f);
4604 enum machine_mode mode = TYPE_MODE (ftype);
4605
4606 if (DECL_SIZE (f) != 0
4607 && host_integerp (bit_position (f), 1))
4608 bitpos += int_bit_position (f);
4609
4610 /* ??? FIXME: else assume zero offset. */
4611
4612 if (TREE_CODE (ftype) == RECORD_TYPE)
4613 rs6000_darwin64_record_arg_recurse (cum, ftype, bitpos, rvec, k);
4614 else if (cum->named && USE_FP_FOR_ARG_P (cum, mode, ftype))
594a51fe 4615 {
0b5383eb
DJ		 4616#if 0
4617 switch (mode)
594a51fe 4618 {
0b5383eb
DJ		 4619 case SCmode: mode = SFmode; break;
4620 case DCmode: mode = DFmode; break;
4621 case TCmode: mode = TFmode; break;
4622 default: break;
594a51fe 4623 }
0b5383eb
DJ		 4624#endif
4625 rs6000_darwin64_record_arg_flush (cum, bitpos, rvec, k);
4626 rvec[(*k)++]
4627 = gen_rtx_EXPR_LIST (VOIDmode,
4628 gen_rtx_REG (mode, cum->fregno++),
4629 GEN_INT (bitpos / BITS_PER_UNIT));
4630 if (mode == TFmode)
4631 cum->fregno++;
594a51fe 4632 }
0b5383eb
DJ		 4633 else if (cum->named && USE_ALTIVEC_FOR_ARG_P (cum, mode, ftype, 1))
4634 {
4635 rs6000_darwin64_record_arg_flush (cum, bitpos, rvec, k);
4636 rvec[(*k)++]
4637 = gen_rtx_EXPR_LIST (VOIDmode,
4638 gen_rtx_REG (mode, cum->vregno++),
4639 GEN_INT (bitpos / BITS_PER_UNIT));
4640 }
4641 else if (cum->intoffset == -1)
4642 cum->intoffset = bitpos;
4643 }
4644}
594a51fe 4645
0b5383eb
DJ		 4646/* For the darwin64 ABI, we want to construct a PARALLEL consisting of
4647 the register(s) to be used for each field and subfield of a struct
4648 being passed by value, along with the offset of where the
4649 register's value may be found in the block. FP fields go in FP
4650 register, vector fields go in vector registers, and everything
4651 else goes in int registers, packed as in memory.
8ff40a74 4652
0b5383eb
DJ		 4653 This code is also used for function return values. RETVAL indicates
4654 whether this is the case.
8ff40a74 4655
0b5383eb
DJ		 4656 Much of this is taken from the Sparc V9 port, which has a similar
4657 calling convention. */
594a51fe 4658
0b5383eb
DJ		 4659static rtx
4660rs6000_darwin64_record_arg (CUMULATIVE_ARGS *orig_cum, tree type,
4661 int named, bool retval)
4662{
4663 rtx rvec[FIRST_PSEUDO_REGISTER];
4664 int k = 1, kbase = 1;
4665 HOST_WIDE_INT typesize = int_size_in_bytes (type);
4666 /* This is a copy; modifications are not visible to our caller. */
4667 CUMULATIVE_ARGS copy_cum = *orig_cum;
4668 CUMULATIVE_ARGS *cum = &copy_cum;
4669
4670 /* Pad to 16 byte boundary if needed. */
4671 if (!retval && TYPE_ALIGN (type) >= 2 * BITS_PER_WORD
4672 && (cum->words % 2) != 0)
4673 cum->words++;
4674
4675 cum->intoffset = 0;
4676 cum->use_stack = 0;
4677 cum->named = named;
4678
4679 /* Put entries into rvec[] for individual FP and vector fields, and
4680 for the chunks of memory that go in int regs. Note we start at
4681 element 1; 0 is reserved for an indication of using memory, and
4682 may or may not be filled in below. */
4683 rs6000_darwin64_record_arg_recurse (cum, type, 0, rvec, &k);
4684 rs6000_darwin64_record_arg_flush (cum, typesize * BITS_PER_UNIT, rvec, &k);
4685
4686 /* If any part of the struct went on the stack put all of it there.
4687 This hack is because the generic code for
4688 FUNCTION_ARG_PARTIAL_NREGS cannot handle cases where the register
4689 parts of the struct are not at the beginning. */
4690 if (cum->use_stack)
4691 {
4692 if (retval)
4693 return NULL_RTX; /* doesn't go in registers at all */
4694 kbase = 0;
4695 rvec[0] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
4696 }
4697 if (k > 1 || cum->use_stack)
4698 return gen_rtx_PARALLEL (BLKmode, gen_rtvec_v (k - kbase, &rvec[kbase]));
594a51fe
SS		 4699 else
4700 return NULL_RTX;
4701}
4702
b78d48dd
FJ		 4703/* Determine where to place an argument in 64-bit mode with 32-bit ABI. */
4704
4705static rtx
ec6376ab 4706rs6000_mixed_function_arg (enum machine_mode mode, tree type, int align_words)
b78d48dd 4707{
ec6376ab
AM		 4708 int n_units;
4709 int i, k;
4710 rtx rvec[GP_ARG_NUM_REG + 1];
4711
4712 if (align_words >= GP_ARG_NUM_REG)
4713 return NULL_RTX;
4714
4715 n_units = rs6000_arg_size (mode, type);
4716
4717 /* Optimize the simple case where the arg fits in one gpr, except in
4718 the case of BLKmode due to assign_parms assuming that registers are
4719 BITS_PER_WORD wide. */
4720 if (n_units == 0
4721 || (n_units == 1 && mode != BLKmode))
4722 return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
4723
4724 k = 0;
4725 if (align_words + n_units > GP_ARG_NUM_REG)
4726 /* Not all of the arg fits in gprs. Say that it goes in memory too,
4727 using a magic NULL_RTX component.
4728 FIXME: This is not strictly correct. Only some of the arg
4729 belongs in memory, not all of it. However, there isn't any way
4730 to do this currently, apart from building rtx descriptions for
4731 the pieces of memory we want stored. Due to bugs in the generic
4732 code we can't use the normal function_arg_partial_nregs scheme
4733 with the PARALLEL arg description we emit here.
4734 In any case, the code to store the whole arg to memory is often
4735 more efficient than code to store pieces, and we know that space
4736 is available in the right place for the whole arg. */
78a52f11
RH		 4737 /* FIXME: This should be fixed since the conversion to
4738 TARGET_ARG_PARTIAL_BYTES. */
ec6376ab
AM		 4739 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
4740
4741 i = 0;
4742 do
36a454e1 4743 {
ec6376ab
AM		 4744 rtx r = gen_rtx_REG (SImode, GP_ARG_MIN_REG + align_words);
4745 rtx off = GEN_INT (i++ * 4);
4746 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
36a454e1 4747 }
ec6376ab
AM		 4748 while (++align_words < GP_ARG_NUM_REG && --n_units != 0);
4749
4750 return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec));
b78d48dd
FJ		 4751}
4752
4697a36c
MM		 4753/* Determine where to put an argument to a function.
4754 Value is zero to push the argument on the stack,
4755 or a hard register in which to store the argument.
4756
4757 MODE is the argument's machine mode.
4758 TYPE is the data type of the argument (as a tree).
4759 This is null for libcalls where that information may
4760 not be available.
4761 CUM is a variable of type CUMULATIVE_ARGS which gives info about
0b5383eb
DJ		 4762 the preceding args and about the function being called. It is
4763 not modified in this routine.
4697a36c
MM		 4764 NAMED is nonzero if this argument is a named parameter
4765 (otherwise it is an extra parameter matching an ellipsis).
4766
4767 On RS/6000 the first eight words of non-FP are normally in registers
4768 and the rest are pushed. Under AIX, the first 13 FP args are in registers.
4769 Under V.4, the first 8 FP args are in registers.
4770
4771 If this is floating-point and no prototype is specified, we use
4772 both an FP and integer register (or possibly FP reg and stack). Library
b9599e46 4773 functions (when CALL_LIBCALL is set) always have the proper types for args,
4697a36c 4774 so we can pass the FP value just in one register. emit_library_function
b2d04ecf
AM		 4775 doesn't support PARALLEL anyway.
4776
4777 Note that for args passed by reference, function_arg will be called
4778 with MODE and TYPE set to that of the pointer to the arg, not the arg
4779 itself. */
4697a36c 4780
9390387d 4781rtx
f676971a 4782function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
a2369ed3 4783 tree type, int named)
4697a36c 4784{
4cc833b7 4785 enum rs6000_abi abi = DEFAULT_ABI;
4697a36c 4786
a4f6c312
SS		 4787 /* Return a marker to indicate whether CR1 needs to set or clear the
4788 bit that V.4 uses to say fp args were passed in registers.
4789 Assume that we don't need the marker for software floating point,
4790 or compiler generated library calls. */
4697a36c
MM		 4791 if (mode == VOIDmode)
4792 {
f607bc57 4793 if (abi == ABI_V4
7509c759 4794 && cum->nargs_prototype < 0
b9599e46
FS		 4795 && (cum->call_cookie & CALL_LIBCALL) == 0
4796 && (cum->prototype || TARGET_NO_PROTOTYPE))
7509c759 4797 {
a3170dc6
AH		 4798 /* For the SPE, we need to crxor CR6 always. */
4799 if (TARGET_SPE_ABI)
4800 return GEN_INT (cum->call_cookie | CALL_V4_SET_FP_ARGS);
4801 else if (TARGET_HARD_FLOAT && TARGET_FPRS)
4802 return GEN_INT (cum->call_cookie
4803 | ((cum->fregno == FP_ARG_MIN_REG)
4804 ? CALL_V4_SET_FP_ARGS
4805 : CALL_V4_CLEAR_FP_ARGS));
7509c759 4806 }
4697a36c 4807
7509c759 4808 return GEN_INT (cum->call_cookie);
4697a36c
MM		 4809 }
4810
0b5383eb
DJ		 4811 if (rs6000_darwin64_abi && mode == BLKmode
4812 && TREE_CODE (type) == RECORD_TYPE)
8ff40a74 4813 {
0b5383eb 4814 rtx rslt = rs6000_darwin64_record_arg (cum, type, named, false);
8ff40a74
SS		 4815 if (rslt != NULL_RTX)
4816 return rslt;
4817 /* Else fall through to usual handling. */
4818 }
4819
2858f73a 4820 if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named))
c72d6c26
HP		 4821 if (TARGET_64BIT && ! cum->prototype)
4822 {
c4ad648e
AM		 4823 /* Vector parameters get passed in vector register
4824 and also in GPRs or memory, in absence of prototype. */
4825 int align_words;
4826 rtx slot;
4827 align_words = (cum->words + 1) & ~1;
4828
4829 if (align_words >= GP_ARG_NUM_REG)
4830 {
4831 slot = NULL_RTX;
4832 }
4833 else
4834 {
4835 slot = gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
4836 }
4837 return gen_rtx_PARALLEL (mode,
4838 gen_rtvec (2,
4839 gen_rtx_EXPR_LIST (VOIDmode,
4840 slot, const0_rtx),
4841 gen_rtx_EXPR_LIST (VOIDmode,
4842 gen_rtx_REG (mode, cum->vregno),
4843 const0_rtx)));
c72d6c26
HP		 4844 }
4845 else
4846 return gen_rtx_REG (mode, cum->vregno);
ad630bef
DE		 4847 else if (TARGET_ALTIVEC_ABI
4848 && (ALTIVEC_VECTOR_MODE (mode)
4849 || (type && TREE_CODE (type) == VECTOR_TYPE
4850 && int_size_in_bytes (type) == 16)))
0ac081f6 4851 {
2858f73a 4852 if (named || abi == ABI_V4)
a594a19c 4853 return NULL_RTX;
0ac081f6 4854 else
a594a19c
GK		 4855 {
4856 /* Vector parameters to varargs functions under AIX or Darwin
4857 get passed in memory and possibly also in GPRs. */
ec6376ab
AM		 4858 int align, align_words, n_words;
4859 enum machine_mode part_mode;
a594a19c
GK		 4860
4861 /* Vector parameters must be 16-byte aligned. This places them at
2858f73a
GK		 4862 2 mod 4 in terms of words in 32-bit mode, since the parameter
4863 save area starts at offset 24 from the stack. In 64-bit mode,
4864 they just have to start on an even word, since the parameter
4865 save area is 16-byte aligned. */
4866 if (TARGET_32BIT)
4ed78545 4867 align = (2 - cum->words) & 3;
2858f73a
GK		 4868 else
4869 align = cum->words & 1;
a594a19c
GK		 4870 align_words = cum->words + align;
4871
4872 /* Out of registers? Memory, then. */
4873 if (align_words >= GP_ARG_NUM_REG)
4874 return NULL_RTX;
ec6376ab
AM		 4875
4876 if (TARGET_32BIT && TARGET_POWERPC64)
4877 return rs6000_mixed_function_arg (mode, type, align_words);
4878
2858f73a
GK		 4879 /* The vector value goes in GPRs. Only the part of the
4880 value in GPRs is reported here. */
ec6376ab
AM		 4881 part_mode = mode;
4882 n_words = rs6000_arg_size (mode, type);
4883 if (align_words + n_words > GP_ARG_NUM_REG)
839a4992 4884 /* Fortunately, there are only two possibilities, the value
2858f73a
GK		 4885 is either wholly in GPRs or half in GPRs and half not. */
4886 part_mode = DImode;
ec6376ab
AM		 4887
4888 return gen_rtx_REG (part_mode, GP_ARG_MIN_REG + align_words);
a594a19c 4889 }
0ac081f6 4890 }
f82f556d
AH		 4891 else if (TARGET_SPE_ABI && TARGET_SPE
4892 && (SPE_VECTOR_MODE (mode)
18f63bfa
AH		 4893 || (TARGET_E500_DOUBLE && (mode == DFmode
4894 || mode == DCmode))))
a6c9bed4 4895 return rs6000_spe_function_arg (cum, mode, type);
594a51fe 4896
f607bc57 4897 else if (abi == ABI_V4)
4697a36c 4898 {
a3170dc6 4899 if (TARGET_HARD_FLOAT && TARGET_FPRS
4cc833b7
RH		 4900 && (mode == SFmode || mode == DFmode))
4901 {
4902 if (cum->fregno <= FP_ARG_V4_MAX_REG)
4903 return gen_rtx_REG (mode, cum->fregno);
4904 else
b78d48dd 4905 return NULL_RTX;
4cc833b7
RH		 4906 }
4907 else
4908 {
b2d04ecf 4909 int n_words = rs6000_arg_size (mode, type);
4cc833b7
RH		 4910 int gregno = cum->sysv_gregno;
4911
4ed78545
AM		 4912 /* Long long and SPE vectors are put in (r3,r4), (r5,r6),
4913 (r7,r8) or (r9,r10). As does any other 2 word item such
4914 as complex int due to a historical mistake. */
4915 if (n_words == 2)
4916 gregno += (1 - gregno) & 1;
4cc833b7 4917
4ed78545 4918 /* Multi-reg args are not split between registers and stack. */
ec6376ab 4919 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
b78d48dd 4920 return NULL_RTX;
ec6376ab
AM		 4921
4922 if (TARGET_32BIT && TARGET_POWERPC64)
4923 return rs6000_mixed_function_arg (mode, type,
4924 gregno - GP_ARG_MIN_REG);
4925 return gen_rtx_REG (mode, gregno);
4cc833b7 4926 }
4697a36c 4927 }
4cc833b7
RH		 4928 else
4929 {
294bd182 4930 int align_words = rs6000_parm_start (mode, type, cum->words);
b78d48dd 4931
2858f73a 4932 if (USE_FP_FOR_ARG_P (cum, mode, type))
4cc833b7 4933 {
ec6376ab
AM		 4934 rtx rvec[GP_ARG_NUM_REG + 1];
4935 rtx r;
4936 int k;
c53bdcf5
AM		 4937 bool needs_psave;
4938 enum machine_mode fmode = mode;
c53bdcf5
AM		 4939 unsigned long n_fpreg = (GET_MODE_SIZE (mode) + 7) >> 3;
4940
4941 if (cum->fregno + n_fpreg > FP_ARG_MAX_REG + 1)
4942 {
c53bdcf5
AM		 4943 /* Currently, we only ever need one reg here because complex
4944 doubles are split. */
37409796 4945 gcc_assert (cum->fregno == FP_ARG_MAX_REG && fmode == TFmode);
ec6376ab
AM		 4946
4947 /* Long double split over regs and memory. */
4948 fmode = DFmode;
c53bdcf5 4949 }
c53bdcf5
AM		 4950
4951 /* Do we also need to pass this arg in the parameter save
4952 area? */
4953 needs_psave = (type
4954 && (cum->nargs_prototype <= 0
4955 || (DEFAULT_ABI == ABI_AIX
de17c25f 4956 && TARGET_XL_COMPAT
c53bdcf5
AM		 4957 && align_words >= GP_ARG_NUM_REG)));
4958
4959 if (!needs_psave && mode == fmode)
ec6376ab 4960 return gen_rtx_REG (fmode, cum->fregno);
c53bdcf5 4961
ec6376ab 4962 k = 0;
c53bdcf5
AM		 4963 if (needs_psave)
4964 {
ec6376ab 4965 /* Describe the part that goes in gprs or the stack.
c53bdcf5 4966 This piece must come first, before the fprs. */
c53bdcf5
AM		 4967 if (align_words < GP_ARG_NUM_REG)
4968 {
4969 unsigned long n_words = rs6000_arg_size (mode, type);
ec6376ab
AM		 4970
4971 if (align_words + n_words > GP_ARG_NUM_REG
4972 || (TARGET_32BIT && TARGET_POWERPC64))
4973 {
4974 /* If this is partially on the stack, then we only
4975 include the portion actually in registers here. */
4976 enum machine_mode rmode = TARGET_32BIT ? SImode : DImode;
4977 rtx off;
2e6c9641 4978 int i=0;
c4ad648e
AM		 4979 if (align_words + n_words > GP_ARG_NUM_REG
4980 && (TARGET_32BIT && TARGET_POWERPC64))
4981 /* Not all of the arg fits in gprs. Say that it
4982 goes in memory too, using a magic NULL_RTX
4983 component. Also see comment in
4984 rs6000_mixed_function_arg for why the normal
4985 function_arg_partial_nregs scheme doesn't work
4986 in this case. */
4987 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX,
4988 const0_rtx);
ec6376ab
AM		 4989 do
4990 {
4991 r = gen_rtx_REG (rmode,
4992 GP_ARG_MIN_REG + align_words);
2e6c9641 4993 off = GEN_INT (i++ * GET_MODE_SIZE (rmode));
ec6376ab
AM		 4994 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
4995 }
4996 while (++align_words < GP_ARG_NUM_REG && --n_words != 0);
4997 }
4998 else
4999 {
5000 /* The whole arg fits in gprs. */
5001 r = gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
5002 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, const0_rtx);
5003 }
c53bdcf5 5004 }
ec6376ab
AM		 5005 else
5006 /* It's entirely in memory. */
5007 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
c53bdcf5
AM		 5008 }
5009
ec6376ab
AM		 5010 /* Describe where this piece goes in the fprs. */
5011 r = gen_rtx_REG (fmode, cum->fregno);
5012 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, const0_rtx);
5013
5014 return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec));
4cc833b7
RH		 5015 }
5016 else if (align_words < GP_ARG_NUM_REG)
b2d04ecf 5017 {
ec6376ab
AM		 5018 if (TARGET_32BIT && TARGET_POWERPC64)
5019 return rs6000_mixed_function_arg (mode, type, align_words);
b2d04ecf 5020
4eeca74f
AM		 5021 if (mode == BLKmode)
5022 mode = Pmode;
5023
b2d04ecf
AM		 5024 return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
5025 }
4cc833b7
RH		 5026 else
5027 return NULL_RTX;
4697a36c 5028 }
4697a36c
MM		 5029}
5030\f
ec6376ab 5031/* For an arg passed partly in registers and partly in memory, this is
fb63c729
AM		 5032 the number of bytes passed in registers. For args passed entirely in
5033 registers or entirely in memory, zero. When an arg is described by a
5034 PARALLEL, perhaps using more than one register type, this function
5035 returns the number of bytes used by the first element of the PARALLEL. */
4697a36c 5036
78a52f11
RH		 5037static int
5038rs6000_arg_partial_bytes (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5039 tree type, bool named)
4697a36c 5040{
c53bdcf5 5041 int ret = 0;
ec6376ab 5042 int align_words;
c53bdcf5 5043
f607bc57 5044 if (DEFAULT_ABI == ABI_V4)
4697a36c 5045 return 0;
4697a36c 5046
c53bdcf5
AM		 5047 if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named)
5048 && cum->nargs_prototype >= 0)
5049 return 0;
5050
0b5383eb
DJ		 5051 /* In this complicated case we just disable the partial_nregs code. */
5052 if (rs6000_darwin64_abi && mode == BLKmode
5053 && TREE_CODE (type) == RECORD_TYPE
5054 && int_size_in_bytes (type) > 0)
5055 return 0;
5056
294bd182 5057 align_words = rs6000_parm_start (mode, type, cum->words);
ec6376ab
AM		 5058
5059 if (USE_FP_FOR_ARG_P (cum, mode, type)
fb63c729
AM		 5060 /* If we are passing this arg in the fixed parameter save area
5061 (gprs or memory) as well as fprs, then this function should
5062 return the number of bytes passed in the parameter save area
5063 rather than bytes passed in fprs. */
ec6376ab
AM		 5064 && !(type
5065 && (cum->nargs_prototype <= 0
5066 || (DEFAULT_ABI == ABI_AIX
de17c25f 5067 && TARGET_XL_COMPAT
ec6376ab 5068 && align_words >= GP_ARG_NUM_REG))))
4697a36c 5069 {
c53bdcf5 5070 if (cum->fregno + ((GET_MODE_SIZE (mode) + 7) >> 3) > FP_ARG_MAX_REG + 1)
ac7e839c 5071 ret = (FP_ARG_MAX_REG + 1 - cum->fregno) * 8;
c53bdcf5 5072 else if (cum->nargs_prototype >= 0)
4697a36c
MM		 5073 return 0;
5074 }
5075
ec6376ab
AM		 5076 if (align_words < GP_ARG_NUM_REG
5077 && GP_ARG_NUM_REG < align_words + rs6000_arg_size (mode, type))
ac7e839c 5078 ret = (GP_ARG_NUM_REG - align_words) * (TARGET_32BIT ? 4 : 8);
78a52f11 5079
c53bdcf5 5080 if (ret != 0 && TARGET_DEBUG_ARG)
78a52f11 5081 fprintf (stderr, "rs6000_arg_partial_bytes: %d\n", ret);
4697a36c 5082
c53bdcf5 5083 return ret;
4697a36c
MM		 5084}
5085\f
5086/* A C expression that indicates when an argument must be passed by
5087 reference. If nonzero for an argument, a copy of that argument is
5088 made in memory and a pointer to the argument is passed instead of
5089 the argument itself. The pointer is passed in whatever way is
5090 appropriate for passing a pointer to that type.
5091
b2d04ecf
AM		 5092 Under V.4, aggregates and long double are passed by reference.
5093
5094 As an extension to all 32-bit ABIs, AltiVec vectors are passed by
5095 reference unless the AltiVec vector extension ABI is in force.
c8c99a68
DE		 5096
5097 As an extension to all ABIs, variable sized types are passed by
5098 reference. */
4697a36c 5099
8cd5a4e0 5100static bool
f676971a 5101rs6000_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
bada2eb8
DE		 5102 enum machine_mode mode, tree type,
5103 bool named ATTRIBUTE_UNUSED)
4697a36c 5104{
bada2eb8 5105 if (DEFAULT_ABI == ABI_V4 && mode == TFmode)
4697a36c
MM		 5106 {
5107 if (TARGET_DEBUG_ARG)
bada2eb8
DE		 5108 fprintf (stderr, "function_arg_pass_by_reference: V4 long double\n");
5109 return 1;
5110 }
5111
5112 if (!type)
5113 return 0;
4697a36c 5114
bada2eb8
DE		 5115 if (DEFAULT_ABI == ABI_V4 && AGGREGATE_TYPE_P (type))
5116 {
5117 if (TARGET_DEBUG_ARG)
5118 fprintf (stderr, "function_arg_pass_by_reference: V4 aggregate\n");
5119 return 1;
5120 }
5121
5122 if (int_size_in_bytes (type) < 0)
5123 {
5124 if (TARGET_DEBUG_ARG)
5125 fprintf (stderr, "function_arg_pass_by_reference: variable size\n");
5126 return 1;
5127 }
5128
5129 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
5130 modes only exist for GCC vector types if -maltivec. */
5131 if (TARGET_32BIT && !TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
5132 {
5133 if (TARGET_DEBUG_ARG)
5134 fprintf (stderr, "function_arg_pass_by_reference: AltiVec\n");
4697a36c
MM		 5135 return 1;
5136 }
b693336b
PB		 5137
5138 /* Pass synthetic vectors in memory. */
bada2eb8 5139 if (TREE_CODE (type) == VECTOR_TYPE
ad630bef 5140 && int_size_in_bytes (type) > (TARGET_ALTIVEC_ABI ? 16 : 8))
b693336b
PB		 5141 {
5142 static bool warned_for_pass_big_vectors = false;
5143 if (TARGET_DEBUG_ARG)
5144 fprintf (stderr, "function_arg_pass_by_reference: synthetic vector\n");
5145 if (!warned_for_pass_big_vectors)
5146 {
d4ee4d25 5147 warning (0, "GCC vector passed by reference: "
b693336b
PB		 5148 "non-standard ABI extension with no compatibility guarantee");
5149 warned_for_pass_big_vectors = true;
5150 }
5151 return 1;
5152 }
5153
b2d04ecf 5154 return 0;
4697a36c 5155}
5985c7a6
FJ		 5156
5157static void
2d9db8eb 5158rs6000_move_block_from_reg (int regno, rtx x, int nregs)
5985c7a6
FJ		 5159{
5160 int i;
5161 enum machine_mode reg_mode = TARGET_32BIT ? SImode : DImode;
5162
5163 if (nregs == 0)
5164 return;
5165
c4ad648e 5166 for (i = 0; i < nregs; i++)
5985c7a6 5167 {
9390387d 5168 rtx tem = adjust_address_nv (x, reg_mode, i * GET_MODE_SIZE (reg_mode));
5985c7a6 5169 if (reload_completed)
c4ad648e
AM		 5170 {
5171 if (! strict_memory_address_p (reg_mode, XEXP (tem, 0)))
5172 tem = NULL_RTX;
5173 else
5174 tem = simplify_gen_subreg (reg_mode, x, BLKmode,
9390387d 5175 i * GET_MODE_SIZE (reg_mode));
c4ad648e 5176 }
5985c7a6
FJ		 5177 else
5178 tem = replace_equiv_address (tem, XEXP (tem, 0));
5179
37409796 5180 gcc_assert (tem);
5985c7a6
FJ		 5181
5182 emit_move_insn (tem, gen_rtx_REG (reg_mode, regno + i));
5183 }
5184}
4697a36c
MM		 5185\f
5186/* Perform any needed actions needed for a function that is receiving a
f676971a 5187 variable number of arguments.
4697a36c
MM		 5188
5189 CUM is as above.
5190
5191 MODE and TYPE are the mode and type of the current parameter.
5192
5193 PRETEND_SIZE is a variable that should be set to the amount of stack
5194 that must be pushed by the prolog to pretend that our caller pushed
5195 it.
5196
5197 Normally, this macro will push all remaining incoming registers on the
5198 stack and set PRETEND_SIZE to the length of the registers pushed. */
5199
c6e8c921 5200static void
f676971a 5201setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
c4ad648e
AM		 5202 tree type, int *pretend_size ATTRIBUTE_UNUSED,
5203 int no_rtl)
4697a36c 5204{
4cc833b7
RH		 5205 CUMULATIVE_ARGS next_cum;
5206 int reg_size = TARGET_32BIT ? 4 : 8;
ca5adc63 5207 rtx save_area = NULL_RTX, mem;
dfafc897 5208 int first_reg_offset, set;
4697a36c 5209
f31bf321 5210 /* Skip the last named argument. */
d34c5b80 5211 next_cum = *cum;
594a51fe 5212 function_arg_advance (&next_cum, mode, type, 1, 0);
4cc833b7 5213
f607bc57 5214 if (DEFAULT_ABI == ABI_V4)
d34c5b80 5215 {
60e2d0ca 5216 if (! no_rtl)
2c4974b7 5217 save_area = plus_constant (virtual_stack_vars_rtx,
bd227acc 5218 - RS6000_VARARGS_SIZE);
4cc833b7
RH		 5219
5220 first_reg_offset = next_cum.sysv_gregno - GP_ARG_MIN_REG;
4697a36c 5221 }
60e2d0ca 5222 else
4697a36c 5223 {
d34c5b80 5224 first_reg_offset = next_cum.words;
4cc833b7 5225 save_area = virtual_incoming_args_rtx;
4697a36c 5226
fe984136 5227 if (targetm.calls.must_pass_in_stack (mode, type))
c53bdcf5 5228 first_reg_offset += rs6000_arg_size (TYPE_MODE (type), type);
4cc833b7 5229 }
4697a36c 5230
dfafc897 5231 set = get_varargs_alias_set ();
9d30f3c1
JJ		 5232 if (! no_rtl && first_reg_offset < GP_ARG_NUM_REG
5233 && cfun->va_list_gpr_size)
4cc833b7 5234 {
9d30f3c1
JJ		 5235 int nregs = GP_ARG_NUM_REG - first_reg_offset;
5236
5237 if (va_list_gpr_counter_field)
5238 {
5239 /* V4 va_list_gpr_size counts number of registers needed. */
5240 if (nregs > cfun->va_list_gpr_size)
5241 nregs = cfun->va_list_gpr_size;
5242 }
5243 else
5244 {
5245 /* char * va_list instead counts number of bytes needed. */
5246 if (nregs > cfun->va_list_gpr_size / reg_size)
5247 nregs = cfun->va_list_gpr_size / reg_size;
5248 }
5249
dfafc897 5250 mem = gen_rtx_MEM (BLKmode,
c4ad648e 5251 plus_constant (save_area,
dfafc897 5252 first_reg_offset * reg_size)),
ba4828e0 5253 set_mem_alias_set (mem, set);
8ac61af7 5254 set_mem_align (mem, BITS_PER_WORD);
dfafc897 5255
f676971a 5256 rs6000_move_block_from_reg (GP_ARG_MIN_REG + first_reg_offset, mem,
9d30f3c1 5257 nregs);
4697a36c
MM		 5258 }
5259
4697a36c 5260 /* Save FP registers if needed. */
f607bc57 5261 if (DEFAULT_ABI == ABI_V4
a3170dc6
AH		 5262 && TARGET_HARD_FLOAT && TARGET_FPRS
5263 && ! no_rtl
9d30f3c1
JJ		 5264 && next_cum.fregno <= FP_ARG_V4_MAX_REG
5265 && cfun->va_list_fpr_size)
4697a36c 5266 {
9d30f3c1 5267 int fregno = next_cum.fregno, nregs;
9ebbca7d 5268 rtx cr1 = gen_rtx_REG (CCmode, CR1_REGNO);
4cc833b7
RH		 5269 rtx lab = gen_label_rtx ();
5270 int off = (GP_ARG_NUM_REG * reg_size) + ((fregno - FP_ARG_MIN_REG) * 8);
4697a36c 5271
c4ad648e
AM		 5272 emit_jump_insn
5273 (gen_rtx_SET (VOIDmode,
5274 pc_rtx,
5275 gen_rtx_IF_THEN_ELSE (VOIDmode,
4cc833b7 5276 gen_rtx_NE (VOIDmode, cr1,
c4ad648e 5277 const0_rtx),
39403d82 5278 gen_rtx_LABEL_REF (VOIDmode, lab),
4697a36c
MM		 5279 pc_rtx)));
5280
9d30f3c1
JJ		 5281 for (nregs = 0;
5282 fregno <= FP_ARG_V4_MAX_REG && nregs < cfun->va_list_fpr_size;
5283 fregno++, off += 8, nregs++)
4cc833b7 5284 {
5496b36f 5285 mem = gen_rtx_MEM (DFmode, plus_constant (save_area, off));
c4ad648e 5286 set_mem_alias_set (mem, set);
94ff898d 5287 set_mem_align (mem, GET_MODE_ALIGNMENT (DFmode));
dfafc897 5288 emit_move_insn (mem, gen_rtx_REG (DFmode, fregno));
4697a36c 5289 }
4cc833b7
RH		 5290
5291 emit_label (lab);
4697a36c 5292 }
4697a36c 5293}
4697a36c 5294
dfafc897 5295/* Create the va_list data type. */
2c4974b7 5296
c35d187f
RH		 5297static tree
5298rs6000_build_builtin_va_list (void)
dfafc897 5299{
64c2816f 5300 tree f_gpr, f_fpr, f_res, f_ovf, f_sav, record, type_decl;
4697a36c 5301
9ebbca7d
GK		 5302 /* For AIX, prefer 'char *' because that's what the system
5303 header files like. */
f607bc57 5304 if (DEFAULT_ABI != ABI_V4)
9ebbca7d 5305 return build_pointer_type (char_type_node);
dfafc897 5306
f1e639b1 5307 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
bab45a51 5308 type_decl = build_decl (TYPE_DECL, get_identifier ("__va_list_tag"), record);
0f4fd75d 5309
f676971a 5310 f_gpr = build_decl (FIELD_DECL, get_identifier ("gpr"),
9ebbca7d 5311 unsigned_char_type_node);
f676971a 5312 f_fpr = build_decl (FIELD_DECL, get_identifier ("fpr"),
9ebbca7d 5313 unsigned_char_type_node);
64c2816f
DT		 5314 /* Give the two bytes of padding a name, so that -Wpadded won't warn on
5315 every user file. */
5316 f_res = build_decl (FIELD_DECL, get_identifier ("reserved"),
5317 short_unsigned_type_node);
dfafc897
FS		 5318 f_ovf = build_decl (FIELD_DECL, get_identifier ("overflow_arg_area"),
5319 ptr_type_node);
5320 f_sav = build_decl (FIELD_DECL, get_identifier ("reg_save_area"),
5321 ptr_type_node);
5322
9d30f3c1
JJ		 5323 va_list_gpr_counter_field = f_gpr;
5324 va_list_fpr_counter_field = f_fpr;
5325
dfafc897
FS		 5326 DECL_FIELD_CONTEXT (f_gpr) = record;
5327 DECL_FIELD_CONTEXT (f_fpr) = record;
64c2816f 5328 DECL_FIELD_CONTEXT (f_res) = record;
dfafc897
FS		 5329 DECL_FIELD_CONTEXT (f_ovf) = record;
5330 DECL_FIELD_CONTEXT (f_sav) = record;
5331
bab45a51
FS		 5332 TREE_CHAIN (record) = type_decl;
5333 TYPE_NAME (record) = type_decl;
dfafc897
FS		 5334 TYPE_FIELDS (record) = f_gpr;
5335 TREE_CHAIN (f_gpr) = f_fpr;
64c2816f
DT		 5336 TREE_CHAIN (f_fpr) = f_res;
5337 TREE_CHAIN (f_res) = f_ovf;
dfafc897
FS		 5338 TREE_CHAIN (f_ovf) = f_sav;
5339
5340 layout_type (record);
5341
5342 /* The correct type is an array type of one element. */
5343 return build_array_type (record, build_index_type (size_zero_node));
5344}
5345
5346/* Implement va_start. */
5347
5348void
a2369ed3 5349rs6000_va_start (tree valist, rtx nextarg)
4697a36c 5350{
dfafc897 5351 HOST_WIDE_INT words, n_gpr, n_fpr;
c566f9bd 5352 tree f_gpr, f_fpr, f_res, f_ovf, f_sav;
dfafc897 5353 tree gpr, fpr, ovf, sav, t;
2c4974b7 5354
dfafc897 5355 /* Only SVR4 needs something special. */
f607bc57 5356 if (DEFAULT_ABI != ABI_V4)
dfafc897 5357 {
e5faf155 5358 std_expand_builtin_va_start (valist, nextarg);
dfafc897
FS		 5359 return;
5360 }
5361
973a648b 5362 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
dfafc897 5363 f_fpr = TREE_CHAIN (f_gpr);
c566f9bd
DT		 5364 f_res = TREE_CHAIN (f_fpr);
5365 f_ovf = TREE_CHAIN (f_res);
dfafc897
FS		 5366 f_sav = TREE_CHAIN (f_ovf);
5367
872a65b5 5368 valist = build_va_arg_indirect_ref (valist);
44de5aeb
RK		 5369 gpr = build (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
5370 fpr = build (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
5371 ovf = build (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
5372 sav = build (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
dfafc897
FS		 5373
5374 /* Count number of gp and fp argument registers used. */
4cc833b7 5375 words = current_function_args_info.words;
987732e0
DE		 5376 n_gpr = MIN (current_function_args_info.sysv_gregno - GP_ARG_MIN_REG,
5377 GP_ARG_NUM_REG);
5378 n_fpr = MIN (current_function_args_info.fregno - FP_ARG_MIN_REG,
5379 FP_ARG_NUM_REG);
dfafc897
FS		 5380
5381 if (TARGET_DEBUG_ARG)
4a0a75dd
KG		 5382 fprintf (stderr, "va_start: words = "HOST_WIDE_INT_PRINT_DEC", n_gpr = "
5383 HOST_WIDE_INT_PRINT_DEC", n_fpr = "HOST_WIDE_INT_PRINT_DEC"\n",
5384 words, n_gpr, n_fpr);
dfafc897 5385
9d30f3c1
JJ		 5386 if (cfun->va_list_gpr_size)
5387 {
5388 t = build (MODIFY_EXPR, TREE_TYPE (gpr), gpr,
5389 build_int_cst (NULL_TREE, n_gpr));
5390 TREE_SIDE_EFFECTS (t) = 1;
5391 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5392 }
58c8adc1 5393
9d30f3c1
JJ		 5394 if (cfun->va_list_fpr_size)
5395 {
5396 t = build (MODIFY_EXPR, TREE_TYPE (fpr), fpr,
5397 build_int_cst (NULL_TREE, n_fpr));
5398 TREE_SIDE_EFFECTS (t) = 1;
5399 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5400 }
dfafc897
FS		 5401
5402 /* Find the overflow area. */
5403 t = make_tree (TREE_TYPE (ovf), virtual_incoming_args_rtx);
5404 if (words != 0)
5405 t = build (PLUS_EXPR, TREE_TYPE (ovf), t,
7d60be94 5406 build_int_cst (NULL_TREE, words * UNITS_PER_WORD));
dfafc897
FS		 5407 t = build (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t);
5408 TREE_SIDE_EFFECTS (t) = 1;
5409 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5410
9d30f3c1
JJ		 5411 /* If there were no va_arg invocations, don't set up the register
5412 save area. */
5413 if (!cfun->va_list_gpr_size
5414 && !cfun->va_list_fpr_size
5415 && n_gpr < GP_ARG_NUM_REG
5416 && n_fpr < FP_ARG_V4_MAX_REG)
5417 return;
5418
dfafc897
FS		 5419 /* Find the register save area. */
5420 t = make_tree (TREE_TYPE (sav), virtual_stack_vars_rtx);
5421 t = build (PLUS_EXPR, TREE_TYPE (sav), t,
7d60be94 5422 build_int_cst (NULL_TREE, -RS6000_VARARGS_SIZE));
dfafc897
FS		 5423 t = build (MODIFY_EXPR, TREE_TYPE (sav), sav, t);
5424 TREE_SIDE_EFFECTS (t) = 1;
5425 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5426}
5427
5428/* Implement va_arg. */
5429
23a60a04
JM		 5430tree
5431rs6000_gimplify_va_arg (tree valist, tree type, tree *pre_p, tree *post_p)
cd3ce9b4 5432{
cd3ce9b4
JM		 5433 tree f_gpr, f_fpr, f_res, f_ovf, f_sav;
5434 tree gpr, fpr, ovf, sav, reg, t, u;
08b0dc1b 5435 int size, rsize, n_reg, sav_ofs, sav_scale;
cd3ce9b4
JM		 5436 tree lab_false, lab_over, addr;
5437 int align;
5438 tree ptrtype = build_pointer_type (type);
5439
08b0dc1b
RH		 5440 if (pass_by_reference (NULL, TYPE_MODE (type), type, false))
5441 {
5442 t = rs6000_gimplify_va_arg (valist, ptrtype, pre_p, post_p);
872a65b5 5443 return build_va_arg_indirect_ref (t);
08b0dc1b
RH		 5444 }
5445
cd3ce9b4
JM		 5446 if (DEFAULT_ABI != ABI_V4)
5447 {
08b0dc1b 5448 if (targetm.calls.split_complex_arg && TREE_CODE (type) == COMPLEX_TYPE)
cd3ce9b4
JM		 5449 {
5450 tree elem_type = TREE_TYPE (type);
5451 enum machine_mode elem_mode = TYPE_MODE (elem_type);
5452 int elem_size = GET_MODE_SIZE (elem_mode);
5453
5454 if (elem_size < UNITS_PER_WORD)
5455 {
23a60a04 5456 tree real_part, imag_part;
cd3ce9b4
JM		 5457 tree post = NULL_TREE;
5458
23a60a04
JM		 5459 real_part = rs6000_gimplify_va_arg (valist, elem_type, pre_p,
5460 &post);
5461 /* Copy the value into a temporary, lest the formal temporary
5462 be reused out from under us. */
5463 real_part = get_initialized_tmp_var (real_part, pre_p, &post);
cd3ce9b4
JM		 5464 append_to_statement_list (post, pre_p);
5465
23a60a04
JM		 5466 imag_part = rs6000_gimplify_va_arg (valist, elem_type, pre_p,
5467 post_p);
cd3ce9b4 5468
23a60a04 5469 return build (COMPLEX_EXPR, type, real_part, imag_part);
cd3ce9b4
JM		 5470 }
5471 }
5472
23a60a04 5473 return std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
cd3ce9b4
JM		 5474 }
5475
5476 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
5477 f_fpr = TREE_CHAIN (f_gpr);
5478 f_res = TREE_CHAIN (f_fpr);
5479 f_ovf = TREE_CHAIN (f_res);
5480 f_sav = TREE_CHAIN (f_ovf);
5481
872a65b5 5482 valist = build_va_arg_indirect_ref (valist);
44de5aeb
RK		 5483 gpr = build (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
5484 fpr = build (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
5485 ovf = build (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
5486 sav = build (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
cd3ce9b4
JM		 5487
5488 size = int_size_in_bytes (type);
5489 rsize = (size + 3) / 4;
5490 align = 1;
5491
08b0dc1b
RH		 5492 if (TARGET_HARD_FLOAT && TARGET_FPRS
5493 && (TYPE_MODE (type) == SFmode || TYPE_MODE (type) == DFmode))
cd3ce9b4
JM		 5494 {
5495 /* FP args go in FP registers, if present. */
cd3ce9b4
JM		 5496 reg = fpr;
5497 n_reg = 1;
5498 sav_ofs = 8*4;
5499 sav_scale = 8;
5500 if (TYPE_MODE (type) == DFmode)
5501 align = 8;
5502 }
5503 else
5504 {
5505 /* Otherwise into GP registers. */
cd3ce9b4
JM		 5506 reg = gpr;
5507 n_reg = rsize;
5508 sav_ofs = 0;
5509 sav_scale = 4;
5510 if (n_reg == 2)
5511 align = 8;
5512 }
5513
5514 /* Pull the value out of the saved registers.... */
5515
5516 lab_over = NULL;
5517 addr = create_tmp_var (ptr_type_node, "addr");
5518 DECL_POINTER_ALIAS_SET (addr) = get_varargs_alias_set ();
5519
5520 /* AltiVec vectors never go in registers when -mabi=altivec. */
5521 if (TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (TYPE_MODE (type)))
5522 align = 16;
5523 else
5524 {
5525 lab_false = create_artificial_label ();
5526 lab_over = create_artificial_label ();
5527
5528 /* Long long and SPE vectors are aligned in the registers.
5529 As are any other 2 gpr item such as complex int due to a
5530 historical mistake. */
5531 u = reg;
5532 if (n_reg == 2)
5533 {
5534 u = build2 (BIT_AND_EXPR, TREE_TYPE (reg), reg,
95674810 5535 size_int (n_reg - 1));
cd3ce9b4
JM		 5536 u = build2 (POSTINCREMENT_EXPR, TREE_TYPE (reg), reg, u);
5537 }
5538
95674810 5539 t = fold_convert (TREE_TYPE (reg), size_int (8 - n_reg + 1));
cd3ce9b4
JM		 5540 t = build2 (GE_EXPR, boolean_type_node, u, t);
5541 u = build1 (GOTO_EXPR, void_type_node, lab_false);
5542 t = build3 (COND_EXPR, void_type_node, t, u, NULL_TREE);
5543 gimplify_and_add (t, pre_p);
5544
5545 t = sav;
5546 if (sav_ofs)
95674810 5547 t = build2 (PLUS_EXPR, ptr_type_node, sav, size_int (sav_ofs));
cd3ce9b4 5548
95674810 5549 u = build2 (POSTINCREMENT_EXPR, TREE_TYPE (reg), reg, size_int (n_reg));
cd3ce9b4 5550 u = build1 (CONVERT_EXPR, integer_type_node, u);
95674810 5551 u = build2 (MULT_EXPR, integer_type_node, u, size_int (sav_scale));
cd3ce9b4
JM		 5552 t = build2 (PLUS_EXPR, ptr_type_node, t, u);
5553
5554 t = build2 (MODIFY_EXPR, void_type_node, addr, t);
5555 gimplify_and_add (t, pre_p);
5556
5557 t = build1 (GOTO_EXPR, void_type_node, lab_over);
5558 gimplify_and_add (t, pre_p);
5559
5560 t = build1 (LABEL_EXPR, void_type_node, lab_false);
5561 append_to_statement_list (t, pre_p);
5562
5563 if (n_reg > 2)
5564 {
5565 /* Ensure that we don't find any more args in regs.
5566 Alignment has taken care of the n_reg == 2 case. */
95674810 5567 t = build (MODIFY_EXPR, TREE_TYPE (reg), reg, size_int (8));
cd3ce9b4
JM		 5568 gimplify_and_add (t, pre_p);
5569 }
5570 }
5571
5572 /* ... otherwise out of the overflow area. */
5573
5574 /* Care for on-stack alignment if needed. */
5575 t = ovf;
5576 if (align != 1)
5577 {
95674810 5578 t = build2 (PLUS_EXPR, TREE_TYPE (t), t, size_int (align - 1));
4a90aeeb 5579 t = build2 (BIT_AND_EXPR, TREE_TYPE (t), t,
7d60be94 5580 build_int_cst (NULL_TREE, -align));
cd3ce9b4
JM		 5581 }
5582 gimplify_expr (&t, pre_p, NULL, is_gimple_val, fb_rvalue);
5583
5584 u = build2 (MODIFY_EXPR, void_type_node, addr, t);
5585 gimplify_and_add (u, pre_p);
5586
95674810 5587 t = build2 (PLUS_EXPR, TREE_TYPE (t), t, size_int (size));
cd3ce9b4
JM		 5588 t = build2 (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t);
5589 gimplify_and_add (t, pre_p);
5590
5591 if (lab_over)
5592 {
5593 t = build1 (LABEL_EXPR, void_type_node, lab_over);
5594 append_to_statement_list (t, pre_p);
5595 }
5596
08b0dc1b 5597 addr = fold_convert (ptrtype, addr);
872a65b5 5598 return build_va_arg_indirect_ref (addr);
cd3ce9b4
JM		 5599}
5600
0ac081f6
AH		 5601/* Builtins. */
5602
58646b77
PB		 5603static void
5604def_builtin (int mask, const char *name, tree type, int code)
5605{
5606 if (mask & target_flags)
5607 {
5608 if (rs6000_builtin_decls[code])
5609 abort ();
5610
5611 rs6000_builtin_decls[code] =
5612 lang_hooks.builtin_function (name, type, code, BUILT_IN_MD,
5613 NULL, NULL_TREE);
5614 }
5615}
0ac081f6 5616
24408032
AH		 5617/* Simple ternary operations: VECd = foo (VECa, VECb, VECc). */
5618
2212663f 5619static const struct builtin_description bdesc_3arg[] =
24408032
AH		 5620{
5621 { MASK_ALTIVEC, CODE_FOR_altivec_vmaddfp, "__builtin_altivec_vmaddfp", ALTIVEC_BUILTIN_VMADDFP },
5622 { MASK_ALTIVEC, CODE_FOR_altivec_vmhaddshs, "__builtin_altivec_vmhaddshs", ALTIVEC_BUILTIN_VMHADDSHS },
5623 { MASK_ALTIVEC, CODE_FOR_altivec_vmhraddshs, "__builtin_altivec_vmhraddshs", ALTIVEC_BUILTIN_VMHRADDSHS },
5624 { MASK_ALTIVEC, CODE_FOR_altivec_vmladduhm, "__builtin_altivec_vmladduhm", ALTIVEC_BUILTIN_VMLADDUHM},
5625 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumubm, "__builtin_altivec_vmsumubm", ALTIVEC_BUILTIN_VMSUMUBM },
5626 { MASK_ALTIVEC, CODE_FOR_altivec_vmsummbm, "__builtin_altivec_vmsummbm", ALTIVEC_BUILTIN_VMSUMMBM },
5627 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumuhm, "__builtin_altivec_vmsumuhm", ALTIVEC_BUILTIN_VMSUMUHM },
5628 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumshm, "__builtin_altivec_vmsumshm", ALTIVEC_BUILTIN_VMSUMSHM },
5629 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumuhs, "__builtin_altivec_vmsumuhs", ALTIVEC_BUILTIN_VMSUMUHS },
5630 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumshs, "__builtin_altivec_vmsumshs", ALTIVEC_BUILTIN_VMSUMSHS },
f676971a 5631 { MASK_ALTIVEC, CODE_FOR_altivec_vnmsubfp, "__builtin_altivec_vnmsubfp", ALTIVEC_BUILTIN_VNMSUBFP },
aba5fb01
NS		 5632 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v4sf, "__builtin_altivec_vperm_4sf", ALTIVEC_BUILTIN_VPERM_4SF },
5633 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v4si, "__builtin_altivec_vperm_4si", ALTIVEC_BUILTIN_VPERM_4SI },
5634 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v8hi, "__builtin_altivec_vperm_8hi", ALTIVEC_BUILTIN_VPERM_8HI },
5635 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v16qi, "__builtin_altivec_vperm_16qi", ALTIVEC_BUILTIN_VPERM_16QI },
5636 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v4sf, "__builtin_altivec_vsel_4sf", ALTIVEC_BUILTIN_VSEL_4SF },
5637 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v4si, "__builtin_altivec_vsel_4si", ALTIVEC_BUILTIN_VSEL_4SI },
5638 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v8hi, "__builtin_altivec_vsel_8hi", ALTIVEC_BUILTIN_VSEL_8HI },
5639 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v16qi, "__builtin_altivec_vsel_16qi", ALTIVEC_BUILTIN_VSEL_16QI },
5640 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v16qi, "__builtin_altivec_vsldoi_16qi", ALTIVEC_BUILTIN_VSLDOI_16QI },
5641 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v8hi, "__builtin_altivec_vsldoi_8hi", ALTIVEC_BUILTIN_VSLDOI_8HI },
5642 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v4si, "__builtin_altivec_vsldoi_4si", ALTIVEC_BUILTIN_VSLDOI_4SI },
5643 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v4sf, "__builtin_altivec_vsldoi_4sf", ALTIVEC_BUILTIN_VSLDOI_4SF },
58646b77
PB		 5644
5645 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_madd", ALTIVEC_BUILTIN_VEC_MADD },
5646 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_madds", ALTIVEC_BUILTIN_VEC_MADDS },
5647 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mladd", ALTIVEC_BUILTIN_VEC_MLADD },
5648 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mradds", ALTIVEC_BUILTIN_VEC_MRADDS },
5649 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_msum", ALTIVEC_BUILTIN_VEC_MSUM },
5650 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumshm", ALTIVEC_BUILTIN_VEC_VMSUMSHM },
5651 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumuhm", ALTIVEC_BUILTIN_VEC_VMSUMUHM },
5652 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsummbm", ALTIVEC_BUILTIN_VEC_VMSUMMBM },
5653 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumubm", ALTIVEC_BUILTIN_VEC_VMSUMUBM },
5654 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_msums", ALTIVEC_BUILTIN_VEC_MSUMS },
5655 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumshs", ALTIVEC_BUILTIN_VEC_VMSUMSHS },
5656 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumuhs", ALTIVEC_BUILTIN_VEC_VMSUMUHS },
5657 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_nmsub", ALTIVEC_BUILTIN_VEC_NMSUB },
5658 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_perm", ALTIVEC_BUILTIN_VEC_PERM },
5659 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sel", ALTIVEC_BUILTIN_VEC_SEL },
24408032 5660};
2212663f 5661
95385cbb
AH		 5662/* DST operations: void foo (void *, const int, const char). */
5663
5664static const struct builtin_description bdesc_dst[] =
5665{
5666 { MASK_ALTIVEC, CODE_FOR_altivec_dst, "__builtin_altivec_dst", ALTIVEC_BUILTIN_DST },
5667 { MASK_ALTIVEC, CODE_FOR_altivec_dstt, "__builtin_altivec_dstt", ALTIVEC_BUILTIN_DSTT },
5668 { MASK_ALTIVEC, CODE_FOR_altivec_dstst, "__builtin_altivec_dstst", ALTIVEC_BUILTIN_DSTST },
58646b77
PB		 5669 { MASK_ALTIVEC, CODE_FOR_altivec_dststt, "__builtin_altivec_dststt", ALTIVEC_BUILTIN_DSTSTT },
5670
5671 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_dst", ALTIVEC_BUILTIN_VEC_DST },
5672 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_dstt", ALTIVEC_BUILTIN_VEC_DSTT },
5673 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_dstst", ALTIVEC_BUILTIN_VEC_DSTST },
5674 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_dststt", ALTIVEC_BUILTIN_VEC_DSTSTT }
95385cbb
AH		 5675};
5676
2212663f 5677/* Simple binary operations: VECc = foo (VECa, VECb). */
24408032 5678
a3170dc6 5679static struct builtin_description bdesc_2arg[] =
0ac081f6 5680{
f18c054f
DB		 5681 { MASK_ALTIVEC, CODE_FOR_addv16qi3, "__builtin_altivec_vaddubm", ALTIVEC_BUILTIN_VADDUBM },
5682 { MASK_ALTIVEC, CODE_FOR_addv8hi3, "__builtin_altivec_vadduhm", ALTIVEC_BUILTIN_VADDUHM },
5683 { MASK_ALTIVEC, CODE_FOR_addv4si3, "__builtin_altivec_vadduwm", ALTIVEC_BUILTIN_VADDUWM },
5684 { MASK_ALTIVEC, CODE_FOR_addv4sf3, "__builtin_altivec_vaddfp", ALTIVEC_BUILTIN_VADDFP },
0ac081f6
AH		 5685 { MASK_ALTIVEC, CODE_FOR_altivec_vaddcuw, "__builtin_altivec_vaddcuw", ALTIVEC_BUILTIN_VADDCUW },
5686 { MASK_ALTIVEC, CODE_FOR_altivec_vaddubs, "__builtin_altivec_vaddubs", ALTIVEC_BUILTIN_VADDUBS },
5687 { MASK_ALTIVEC, CODE_FOR_altivec_vaddsbs, "__builtin_altivec_vaddsbs", ALTIVEC_BUILTIN_VADDSBS },
5688 { MASK_ALTIVEC, CODE_FOR_altivec_vadduhs, "__builtin_altivec_vadduhs", ALTIVEC_BUILTIN_VADDUHS },
5689 { MASK_ALTIVEC, CODE_FOR_altivec_vaddshs, "__builtin_altivec_vaddshs", ALTIVEC_BUILTIN_VADDSHS },
5690 { MASK_ALTIVEC, CODE_FOR_altivec_vadduws, "__builtin_altivec_vadduws", ALTIVEC_BUILTIN_VADDUWS },
5691 { MASK_ALTIVEC, CODE_FOR_altivec_vaddsws, "__builtin_altivec_vaddsws", ALTIVEC_BUILTIN_VADDSWS },
f18c054f 5692 { MASK_ALTIVEC, CODE_FOR_andv4si3, "__builtin_altivec_vand", ALTIVEC_BUILTIN_VAND },
aba5fb01 5693 { MASK_ALTIVEC, CODE_FOR_andcv4si3, "__builtin_altivec_vandc", ALTIVEC_BUILTIN_VANDC },
0ac081f6
AH		 5694 { MASK_ALTIVEC, CODE_FOR_altivec_vavgub, "__builtin_altivec_vavgub", ALTIVEC_BUILTIN_VAVGUB },
5695 { MASK_ALTIVEC, CODE_FOR_altivec_vavgsb, "__builtin_altivec_vavgsb", ALTIVEC_BUILTIN_VAVGSB },
5696 { MASK_ALTIVEC, CODE_FOR_altivec_vavguh, "__builtin_altivec_vavguh", ALTIVEC_BUILTIN_VAVGUH },
5697 { MASK_ALTIVEC, CODE_FOR_altivec_vavgsh, "__builtin_altivec_vavgsh", ALTIVEC_BUILTIN_VAVGSH },
5698 { MASK_ALTIVEC, CODE_FOR_altivec_vavguw, "__builtin_altivec_vavguw", ALTIVEC_BUILTIN_VAVGUW },
5699 { MASK_ALTIVEC, CODE_FOR_altivec_vavgsw, "__builtin_altivec_vavgsw", ALTIVEC_BUILTIN_VAVGSW },
617e0e1d
DB		 5700 { MASK_ALTIVEC, CODE_FOR_altivec_vcfux, "__builtin_altivec_vcfux", ALTIVEC_BUILTIN_VCFUX },
5701 { MASK_ALTIVEC, CODE_FOR_altivec_vcfsx, "__builtin_altivec_vcfsx", ALTIVEC_BUILTIN_VCFSX },
0ac081f6
AH		 5702 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpbfp, "__builtin_altivec_vcmpbfp", ALTIVEC_BUILTIN_VCMPBFP },
5703 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequb, "__builtin_altivec_vcmpequb", ALTIVEC_BUILTIN_VCMPEQUB },
5704 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequh, "__builtin_altivec_vcmpequh", ALTIVEC_BUILTIN_VCMPEQUH },
5705 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequw, "__builtin_altivec_vcmpequw", ALTIVEC_BUILTIN_VCMPEQUW },
5706 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpeqfp, "__builtin_altivec_vcmpeqfp", ALTIVEC_BUILTIN_VCMPEQFP },
5707 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgefp, "__builtin_altivec_vcmpgefp", ALTIVEC_BUILTIN_VCMPGEFP },
5708 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtub, "__builtin_altivec_vcmpgtub", ALTIVEC_BUILTIN_VCMPGTUB },
5709 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsb, "__builtin_altivec_vcmpgtsb", ALTIVEC_BUILTIN_VCMPGTSB },
5710 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtuh, "__builtin_altivec_vcmpgtuh", ALTIVEC_BUILTIN_VCMPGTUH },
5711 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsh, "__builtin_altivec_vcmpgtsh", ALTIVEC_BUILTIN_VCMPGTSH },
5712 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtuw, "__builtin_altivec_vcmpgtuw", ALTIVEC_BUILTIN_VCMPGTUW },
5713 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsw, "__builtin_altivec_vcmpgtsw", ALTIVEC_BUILTIN_VCMPGTSW },
5714 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtfp, "__builtin_altivec_vcmpgtfp", ALTIVEC_BUILTIN_VCMPGTFP },
617e0e1d
DB		 5715 { MASK_ALTIVEC, CODE_FOR_altivec_vctsxs, "__builtin_altivec_vctsxs", ALTIVEC_BUILTIN_VCTSXS },
5716 { MASK_ALTIVEC, CODE_FOR_altivec_vctuxs, "__builtin_altivec_vctuxs", ALTIVEC_BUILTIN_VCTUXS },
f18c054f
DB		 5717 { MASK_ALTIVEC, CODE_FOR_umaxv16qi3, "__builtin_altivec_vmaxub", ALTIVEC_BUILTIN_VMAXUB },
5718 { MASK_ALTIVEC, CODE_FOR_smaxv16qi3, "__builtin_altivec_vmaxsb", ALTIVEC_BUILTIN_VMAXSB },
df966bff
AH		 5719 { MASK_ALTIVEC, CODE_FOR_umaxv8hi3, "__builtin_altivec_vmaxuh", ALTIVEC_BUILTIN_VMAXUH },
5720 { MASK_ALTIVEC, CODE_FOR_smaxv8hi3, "__builtin_altivec_vmaxsh", ALTIVEC_BUILTIN_VMAXSH },
5721 { MASK_ALTIVEC, CODE_FOR_umaxv4si3, "__builtin_altivec_vmaxuw", ALTIVEC_BUILTIN_VMAXUW },
5722 { MASK_ALTIVEC, CODE_FOR_smaxv4si3, "__builtin_altivec_vmaxsw", ALTIVEC_BUILTIN_VMAXSW },
5723 { MASK_ALTIVEC, CODE_FOR_smaxv4sf3, "__builtin_altivec_vmaxfp", ALTIVEC_BUILTIN_VMAXFP },
0ac081f6
AH		 5724 { MASK_ALTIVEC, CODE_FOR_altivec_vmrghb, "__builtin_altivec_vmrghb", ALTIVEC_BUILTIN_VMRGHB },
5725 { MASK_ALTIVEC, CODE_FOR_altivec_vmrghh, "__builtin_altivec_vmrghh", ALTIVEC_BUILTIN_VMRGHH },
5726 { MASK_ALTIVEC, CODE_FOR_altivec_vmrghw, "__builtin_altivec_vmrghw", ALTIVEC_BUILTIN_VMRGHW },
5727 { MASK_ALTIVEC, CODE_FOR_altivec_vmrglb, "__builtin_altivec_vmrglb", ALTIVEC_BUILTIN_VMRGLB },
5728 { MASK_ALTIVEC, CODE_FOR_altivec_vmrglh, "__builtin_altivec_vmrglh", ALTIVEC_BUILTIN_VMRGLH },
5729 { MASK_ALTIVEC, CODE_FOR_altivec_vmrglw, "__builtin_altivec_vmrglw", ALTIVEC_BUILTIN_VMRGLW },
f18c054f
DB		 5730 { MASK_ALTIVEC, CODE_FOR_uminv16qi3, "__builtin_altivec_vminub", ALTIVEC_BUILTIN_VMINUB },
5731 { MASK_ALTIVEC, CODE_FOR_sminv16qi3, "__builtin_altivec_vminsb", ALTIVEC_BUILTIN_VMINSB },
5732 { MASK_ALTIVEC, CODE_FOR_uminv8hi3, "__builtin_altivec_vminuh", ALTIVEC_BUILTIN_VMINUH },
5733 { MASK_ALTIVEC, CODE_FOR_sminv8hi3, "__builtin_altivec_vminsh", ALTIVEC_BUILTIN_VMINSH },
5734 { MASK_ALTIVEC, CODE_FOR_uminv4si3, "__builtin_altivec_vminuw", ALTIVEC_BUILTIN_VMINUW },
5735 { MASK_ALTIVEC, CODE_FOR_sminv4si3, "__builtin_altivec_vminsw", ALTIVEC_BUILTIN_VMINSW },
5736 { MASK_ALTIVEC, CODE_FOR_sminv4sf3, "__builtin_altivec_vminfp", ALTIVEC_BUILTIN_VMINFP },
0ac081f6
AH		 5737 { MASK_ALTIVEC, CODE_FOR_altivec_vmuleub, "__builtin_altivec_vmuleub", ALTIVEC_BUILTIN_VMULEUB },
5738 { MASK_ALTIVEC, CODE_FOR_altivec_vmulesb, "__builtin_altivec_vmulesb", ALTIVEC_BUILTIN_VMULESB },
5739 { MASK_ALTIVEC, CODE_FOR_altivec_vmuleuh, "__builtin_altivec_vmuleuh", ALTIVEC_BUILTIN_VMULEUH },
5740 { MASK_ALTIVEC, CODE_FOR_altivec_vmulesh, "__builtin_altivec_vmulesh", ALTIVEC_BUILTIN_VMULESH },
5741 { MASK_ALTIVEC, CODE_FOR_altivec_vmuloub, "__builtin_altivec_vmuloub", ALTIVEC_BUILTIN_VMULOUB },
5742 { MASK_ALTIVEC, CODE_FOR_altivec_vmulosb, "__builtin_altivec_vmulosb", ALTIVEC_BUILTIN_VMULOSB },
5743 { MASK_ALTIVEC, CODE_FOR_altivec_vmulouh, "__builtin_altivec_vmulouh", ALTIVEC_BUILTIN_VMULOUH },
5744 { MASK_ALTIVEC, CODE_FOR_altivec_vmulosh, "__builtin_altivec_vmulosh", ALTIVEC_BUILTIN_VMULOSH },
f96bc213 5745 { MASK_ALTIVEC, CODE_FOR_altivec_norv4si3, "__builtin_altivec_vnor", ALTIVEC_BUILTIN_VNOR },
f18c054f 5746 { MASK_ALTIVEC, CODE_FOR_iorv4si3, "__builtin_altivec_vor", ALTIVEC_BUILTIN_VOR },
0ac081f6
AH		 5747 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhum, "__builtin_altivec_vpkuhum", ALTIVEC_BUILTIN_VPKUHUM },
5748 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwum, "__builtin_altivec_vpkuwum", ALTIVEC_BUILTIN_VPKUWUM },
5749 { MASK_ALTIVEC, CODE_FOR_altivec_vpkpx, "__builtin_altivec_vpkpx", ALTIVEC_BUILTIN_VPKPX },
5750 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhss, "__builtin_altivec_vpkuhss", ALTIVEC_BUILTIN_VPKUHSS },
5751 { MASK_ALTIVEC, CODE_FOR_altivec_vpkshss, "__builtin_altivec_vpkshss", ALTIVEC_BUILTIN_VPKSHSS },
5752 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwss, "__builtin_altivec_vpkuwss", ALTIVEC_BUILTIN_VPKUWSS },
5753 { MASK_ALTIVEC, CODE_FOR_altivec_vpkswss, "__builtin_altivec_vpkswss", ALTIVEC_BUILTIN_VPKSWSS },
5754 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhus, "__builtin_altivec_vpkuhus", ALTIVEC_BUILTIN_VPKUHUS },
5755 { MASK_ALTIVEC, CODE_FOR_altivec_vpkshus, "__builtin_altivec_vpkshus", ALTIVEC_BUILTIN_VPKSHUS },
5756 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwus, "__builtin_altivec_vpkuwus", ALTIVEC_BUILTIN_VPKUWUS },
5757 { MASK_ALTIVEC, CODE_FOR_altivec_vpkswus, "__builtin_altivec_vpkswus", ALTIVEC_BUILTIN_VPKSWUS },
5758 { MASK_ALTIVEC, CODE_FOR_altivec_vrlb, "__builtin_altivec_vrlb", ALTIVEC_BUILTIN_VRLB },
5759 { MASK_ALTIVEC, CODE_FOR_altivec_vrlh, "__builtin_altivec_vrlh", ALTIVEC_BUILTIN_VRLH },
5760 { MASK_ALTIVEC, CODE_FOR_altivec_vrlw, "__builtin_altivec_vrlw", ALTIVEC_BUILTIN_VRLW },
5761 { MASK_ALTIVEC, CODE_FOR_altivec_vslb, "__builtin_altivec_vslb", ALTIVEC_BUILTIN_VSLB },
5762 { MASK_ALTIVEC, CODE_FOR_altivec_vslh, "__builtin_altivec_vslh", ALTIVEC_BUILTIN_VSLH },
5763 { MASK_ALTIVEC, CODE_FOR_altivec_vslw, "__builtin_altivec_vslw", ALTIVEC_BUILTIN_VSLW },
5764 { MASK_ALTIVEC, CODE_FOR_altivec_vsl, "__builtin_altivec_vsl", ALTIVEC_BUILTIN_VSL },
5765 { MASK_ALTIVEC, CODE_FOR_altivec_vslo, "__builtin_altivec_vslo", ALTIVEC_BUILTIN_VSLO },
2212663f
DB		 5766 { MASK_ALTIVEC, CODE_FOR_altivec_vspltb, "__builtin_altivec_vspltb", ALTIVEC_BUILTIN_VSPLTB },
5767 { MASK_ALTIVEC, CODE_FOR_altivec_vsplth, "__builtin_altivec_vsplth", ALTIVEC_BUILTIN_VSPLTH },
5768 { MASK_ALTIVEC, CODE_FOR_altivec_vspltw, "__builtin_altivec_vspltw", ALTIVEC_BUILTIN_VSPLTW },
3e0de9d1
DP		 5769 { MASK_ALTIVEC, CODE_FOR_lshrv16qi3, "__builtin_altivec_vsrb", ALTIVEC_BUILTIN_VSRB },
5770 { MASK_ALTIVEC, CODE_FOR_lshrv8hi3, "__builtin_altivec_vsrh", ALTIVEC_BUILTIN_VSRH },
5771 { MASK_ALTIVEC, CODE_FOR_lshrv4si3, "__builtin_altivec_vsrw", ALTIVEC_BUILTIN_VSRW },
5772 { MASK_ALTIVEC, CODE_FOR_ashrv16qi3, "__builtin_altivec_vsrab", ALTIVEC_BUILTIN_VSRAB },
5773 { MASK_ALTIVEC, CODE_FOR_ashrv8hi3, "__builtin_altivec_vsrah", ALTIVEC_BUILTIN_VSRAH },
5774 { MASK_ALTIVEC, CODE_FOR_ashrv4si3, "__builtin_altivec_vsraw", ALTIVEC_BUILTIN_VSRAW },
0ac081f6
AH		 5775 { MASK_ALTIVEC, CODE_FOR_altivec_vsr, "__builtin_altivec_vsr", ALTIVEC_BUILTIN_VSR },
5776 { MASK_ALTIVEC, CODE_FOR_altivec_vsro, "__builtin_altivec_vsro", ALTIVEC_BUILTIN_VSRO },
f18c054f
DB		 5777 { MASK_ALTIVEC, CODE_FOR_subv16qi3, "__builtin_altivec_vsububm", ALTIVEC_BUILTIN_VSUBUBM },
5778 { MASK_ALTIVEC, CODE_FOR_subv8hi3, "__builtin_altivec_vsubuhm", ALTIVEC_BUILTIN_VSUBUHM },
5779 { MASK_ALTIVEC, CODE_FOR_subv4si3, "__builtin_altivec_vsubuwm", ALTIVEC_BUILTIN_VSUBUWM },
5780 { MASK_ALTIVEC, CODE_FOR_subv4sf3, "__builtin_altivec_vsubfp", ALTIVEC_BUILTIN_VSUBFP },
0ac081f6
AH		 5781 { MASK_ALTIVEC, CODE_FOR_altivec_vsubcuw, "__builtin_altivec_vsubcuw", ALTIVEC_BUILTIN_VSUBCUW },
5782 { MASK_ALTIVEC, CODE_FOR_altivec_vsububs, "__builtin_altivec_vsububs", ALTIVEC_BUILTIN_VSUBUBS },
5783 { MASK_ALTIVEC, CODE_FOR_altivec_vsubsbs, "__builtin_altivec_vsubsbs", ALTIVEC_BUILTIN_VSUBSBS },
5784 { MASK_ALTIVEC, CODE_FOR_altivec_vsubuhs, "__builtin_altivec_vsubuhs", ALTIVEC_BUILTIN_VSUBUHS },
5785 { MASK_ALTIVEC, CODE_FOR_altivec_vsubshs, "__builtin_altivec_vsubshs", ALTIVEC_BUILTIN_VSUBSHS },
5786 { MASK_ALTIVEC, CODE_FOR_altivec_vsubuws, "__builtin_altivec_vsubuws", ALTIVEC_BUILTIN_VSUBUWS },
5787 { MASK_ALTIVEC, CODE_FOR_altivec_vsubsws, "__builtin_altivec_vsubsws", ALTIVEC_BUILTIN_VSUBSWS },
5788 { MASK_ALTIVEC, CODE_FOR_altivec_vsum4ubs, "__builtin_altivec_vsum4ubs", ALTIVEC_BUILTIN_VSUM4UBS },
5789 { MASK_ALTIVEC, CODE_FOR_altivec_vsum4sbs, "__builtin_altivec_vsum4sbs", ALTIVEC_BUILTIN_VSUM4SBS },
5790 { MASK_ALTIVEC, CODE_FOR_altivec_vsum4shs, "__builtin_altivec_vsum4shs", ALTIVEC_BUILTIN_VSUM4SHS },
5791 { MASK_ALTIVEC, CODE_FOR_altivec_vsum2sws, "__builtin_altivec_vsum2sws", ALTIVEC_BUILTIN_VSUM2SWS },
5792 { MASK_ALTIVEC, CODE_FOR_altivec_vsumsws, "__builtin_altivec_vsumsws", ALTIVEC_BUILTIN_VSUMSWS },
f18c054f 5793 { MASK_ALTIVEC, CODE_FOR_xorv4si3, "__builtin_altivec_vxor", ALTIVEC_BUILTIN_VXOR },
a3170dc6 5794
58646b77
PB		 5795 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_add", ALTIVEC_BUILTIN_VEC_ADD },
5796 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddfp", ALTIVEC_BUILTIN_VEC_VADDFP },
5797 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vadduwm", ALTIVEC_BUILTIN_VEC_VADDUWM },
5798 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vadduhm", ALTIVEC_BUILTIN_VEC_VADDUHM },
5799 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddubm", ALTIVEC_BUILTIN_VEC_VADDUBM },
5800 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_addc", ALTIVEC_BUILTIN_VEC_ADDC },
5801 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_adds", ALTIVEC_BUILTIN_VEC_ADDS },
5802 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddsws", ALTIVEC_BUILTIN_VEC_VADDSWS },
5803 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vadduws", ALTIVEC_BUILTIN_VEC_VADDUWS },
5804 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddshs", ALTIVEC_BUILTIN_VEC_VADDSHS },
5805 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vadduhs", ALTIVEC_BUILTIN_VEC_VADDUHS },
5806 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddsbs", ALTIVEC_BUILTIN_VEC_VADDSBS },
5807 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddubs", ALTIVEC_BUILTIN_VEC_VADDUBS },
5808 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_and", ALTIVEC_BUILTIN_VEC_AND },
5809 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_andc", ALTIVEC_BUILTIN_VEC_ANDC },
5810 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_avg", ALTIVEC_BUILTIN_VEC_AVG },
5811 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavgsw", ALTIVEC_BUILTIN_VEC_VAVGSW },
5812 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavguw", ALTIVEC_BUILTIN_VEC_VAVGUW },
5813 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavgsh", ALTIVEC_BUILTIN_VEC_VAVGSH },
5814 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavguh", ALTIVEC_BUILTIN_VEC_VAVGUH },
5815 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavgsb", ALTIVEC_BUILTIN_VEC_VAVGSB },
5816 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavgub", ALTIVEC_BUILTIN_VEC_VAVGUB },
5817 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmpb", ALTIVEC_BUILTIN_VEC_CMPB },
5818 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmpeq", ALTIVEC_BUILTIN_VEC_CMPEQ },
5819 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpeqfp", ALTIVEC_BUILTIN_VEC_VCMPEQFP },
5820 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpequw", ALTIVEC_BUILTIN_VEC_VCMPEQUW },
5821 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpequh", ALTIVEC_BUILTIN_VEC_VCMPEQUH },
5822 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpequb", ALTIVEC_BUILTIN_VEC_VCMPEQUB },
5823 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmpge", ALTIVEC_BUILTIN_VEC_CMPGE },
5824 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmpgt", ALTIVEC_BUILTIN_VEC_CMPGT },
5825 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtfp", ALTIVEC_BUILTIN_VEC_VCMPGTFP },
5826 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtsw", ALTIVEC_BUILTIN_VEC_VCMPGTSW },
5827 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtuw", ALTIVEC_BUILTIN_VEC_VCMPGTUW },
5828 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtsh", ALTIVEC_BUILTIN_VEC_VCMPGTSH },
5829 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtuh", ALTIVEC_BUILTIN_VEC_VCMPGTUH },
5830 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtsb", ALTIVEC_BUILTIN_VEC_VCMPGTSB },
5831 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtub", ALTIVEC_BUILTIN_VEC_VCMPGTUB },
5832 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmple", ALTIVEC_BUILTIN_VEC_CMPLE },
5833 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmplt", ALTIVEC_BUILTIN_VEC_CMPLT },
5834 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_max", ALTIVEC_BUILTIN_VEC_MAX },
5835 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxfp", ALTIVEC_BUILTIN_VEC_VMAXFP },
5836 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxsw", ALTIVEC_BUILTIN_VEC_VMAXSW },
5837 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxuw", ALTIVEC_BUILTIN_VEC_VMAXUW },
5838 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxsh", ALTIVEC_BUILTIN_VEC_VMAXSH },
5839 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxuh", ALTIVEC_BUILTIN_VEC_VMAXUH },
5840 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxsb", ALTIVEC_BUILTIN_VEC_VMAXSB },
5841 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxub", ALTIVEC_BUILTIN_VEC_VMAXUB },
5842 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mergeh", ALTIVEC_BUILTIN_VEC_MERGEH },
5843 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrghw", ALTIVEC_BUILTIN_VEC_VMRGHW },
5844 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrghh", ALTIVEC_BUILTIN_VEC_VMRGHH },
5845 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrghb", ALTIVEC_BUILTIN_VEC_VMRGHB },
5846 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mergel", ALTIVEC_BUILTIN_VEC_MERGEL },
5847 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrglw", ALTIVEC_BUILTIN_VEC_VMRGLW },
5848 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrglh", ALTIVEC_BUILTIN_VEC_VMRGLH },
5849 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrglb", ALTIVEC_BUILTIN_VEC_VMRGLB },
5850 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_min", ALTIVEC_BUILTIN_VEC_MIN },
5851 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminfp", ALTIVEC_BUILTIN_VEC_VMINFP },
5852 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminsw", ALTIVEC_BUILTIN_VEC_VMINSW },
5853 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminuw", ALTIVEC_BUILTIN_VEC_VMINUW },
5854 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminsh", ALTIVEC_BUILTIN_VEC_VMINSH },
5855 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminuh", ALTIVEC_BUILTIN_VEC_VMINUH },
5856 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminsb", ALTIVEC_BUILTIN_VEC_VMINSB },
5857 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminub", ALTIVEC_BUILTIN_VEC_VMINUB },
5858 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mule", ALTIVEC_BUILTIN_VEC_MULE },
5859 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmuleub", ALTIVEC_BUILTIN_VEC_VMULEUB },
5860 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulesb", ALTIVEC_BUILTIN_VEC_VMULESB },
5861 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmuleuh", ALTIVEC_BUILTIN_VEC_VMULEUH },
5862 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulesh", ALTIVEC_BUILTIN_VEC_VMULESH },
5863 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mulo", ALTIVEC_BUILTIN_VEC_MULO },
5864 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulosh", ALTIVEC_BUILTIN_VEC_VMULOSH },
5865 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulouh", ALTIVEC_BUILTIN_VEC_VMULOUH },
5866 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulosb", ALTIVEC_BUILTIN_VEC_VMULOSB },
5867 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmuloub", ALTIVEC_BUILTIN_VEC_VMULOUB },
5868 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_nor", ALTIVEC_BUILTIN_VEC_NOR },
5869 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_or", ALTIVEC_BUILTIN_VEC_OR },
5870 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_pack", ALTIVEC_BUILTIN_VEC_PACK },
5871 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkuwum", ALTIVEC_BUILTIN_VEC_VPKUWUM },
5872 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkuhum", ALTIVEC_BUILTIN_VEC_VPKUHUM },
5873 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_packpx", ALTIVEC_BUILTIN_VEC_PACKPX },
5874 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_packs", ALTIVEC_BUILTIN_VEC_PACKS },
5875 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkswss", ALTIVEC_BUILTIN_VEC_VPKSWSS },
5876 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkuwus", ALTIVEC_BUILTIN_VEC_VPKUWUS },
5877 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkshss", ALTIVEC_BUILTIN_VEC_VPKSHSS },
5878 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkuhus", ALTIVEC_BUILTIN_VEC_VPKUHUS },
5879 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_packsu", ALTIVEC_BUILTIN_VEC_PACKSU },
5880 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkswus", ALTIVEC_BUILTIN_VEC_VPKSWUS },
5881 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkshus", ALTIVEC_BUILTIN_VEC_VPKSHUS },
5882 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_rl", ALTIVEC_BUILTIN_VEC_RL },
5883 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vrlw", ALTIVEC_BUILTIN_VEC_VRLW },
5884 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vrlh", ALTIVEC_BUILTIN_VEC_VRLH },
5885 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vrlb", ALTIVEC_BUILTIN_VEC_VRLB },
5886 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sl", ALTIVEC_BUILTIN_VEC_SL },
5887 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vslw", ALTIVEC_BUILTIN_VEC_VSLW },
5888 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vslh", ALTIVEC_BUILTIN_VEC_VSLH },
5889 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vslb", ALTIVEC_BUILTIN_VEC_VSLB },
5890 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sll", ALTIVEC_BUILTIN_VEC_SLL },
5891 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_slo", ALTIVEC_BUILTIN_VEC_SLO },
5892 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sr", ALTIVEC_BUILTIN_VEC_SR },
5893 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrw", ALTIVEC_BUILTIN_VEC_VSRW },
5894 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrh", ALTIVEC_BUILTIN_VEC_VSRH },
5895 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrb", ALTIVEC_BUILTIN_VEC_VSRB },
5896 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sra", ALTIVEC_BUILTIN_VEC_SRA },
5897 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsraw", ALTIVEC_BUILTIN_VEC_VSRAW },
5898 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrah", ALTIVEC_BUILTIN_VEC_VSRAH },
5899 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrab", ALTIVEC_BUILTIN_VEC_VSRAB },
5900 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_srl", ALTIVEC_BUILTIN_VEC_SRL },
5901 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sro", ALTIVEC_BUILTIN_VEC_SRO },
5902 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sub", ALTIVEC_BUILTIN_VEC_SUB },
5903 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubfp", ALTIVEC_BUILTIN_VEC_VSUBFP },
5904 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubuwm", ALTIVEC_BUILTIN_VEC_VSUBUWM },
5905 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubuhm", ALTIVEC_BUILTIN_VEC_VSUBUHM },
5906 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsububm", ALTIVEC_BUILTIN_VEC_VSUBUBM },
5907 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_subc", ALTIVEC_BUILTIN_VEC_SUBC },
5908 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_subs", ALTIVEC_BUILTIN_VEC_SUBS },
5909 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubsws", ALTIVEC_BUILTIN_VEC_VSUBSWS },
5910 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubuws", ALTIVEC_BUILTIN_VEC_VSUBUWS },
5911 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubshs", ALTIVEC_BUILTIN_VEC_VSUBSHS },
5912 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubuhs", ALTIVEC_BUILTIN_VEC_VSUBUHS },
5913 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubsbs", ALTIVEC_BUILTIN_VEC_VSUBSBS },
5914 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsububs", ALTIVEC_BUILTIN_VEC_VSUBUBS },
5915 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sum4s", ALTIVEC_BUILTIN_VEC_SUM4S },
5916 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsum4shs", ALTIVEC_BUILTIN_VEC_VSUM4SHS },
5917 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsum4sbs", ALTIVEC_BUILTIN_VEC_VSUM4SBS },
5918 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsum4ubs", ALTIVEC_BUILTIN_VEC_VSUM4UBS },
5919 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sum2s", ALTIVEC_BUILTIN_VEC_SUM2S },
5920 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sums", ALTIVEC_BUILTIN_VEC_SUMS },
5921 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_xor", ALTIVEC_BUILTIN_VEC_XOR },
5922
a3170dc6
AH		 5923 /* Place holder, leave as first spe builtin. */
5924 { 0, CODE_FOR_spe_evaddw, "__builtin_spe_evaddw", SPE_BUILTIN_EVADDW },
5925 { 0, CODE_FOR_spe_evand, "__builtin_spe_evand", SPE_BUILTIN_EVAND },
5926 { 0, CODE_FOR_spe_evandc, "__builtin_spe_evandc", SPE_BUILTIN_EVANDC },
5927 { 0, CODE_FOR_spe_evdivws, "__builtin_spe_evdivws", SPE_BUILTIN_EVDIVWS },
5928 { 0, CODE_FOR_spe_evdivwu, "__builtin_spe_evdivwu", SPE_BUILTIN_EVDIVWU },
5929 { 0, CODE_FOR_spe_eveqv, "__builtin_spe_eveqv", SPE_BUILTIN_EVEQV },
5930 { 0, CODE_FOR_spe_evfsadd, "__builtin_spe_evfsadd", SPE_BUILTIN_EVFSADD },
5931 { 0, CODE_FOR_spe_evfsdiv, "__builtin_spe_evfsdiv", SPE_BUILTIN_EVFSDIV },
5932 { 0, CODE_FOR_spe_evfsmul, "__builtin_spe_evfsmul", SPE_BUILTIN_EVFSMUL },
5933 { 0, CODE_FOR_spe_evfssub, "__builtin_spe_evfssub", SPE_BUILTIN_EVFSSUB },
5934 { 0, CODE_FOR_spe_evmergehi, "__builtin_spe_evmergehi", SPE_BUILTIN_EVMERGEHI },
5935 { 0, CODE_FOR_spe_evmergehilo, "__builtin_spe_evmergehilo", SPE_BUILTIN_EVMERGEHILO },
5936 { 0, CODE_FOR_spe_evmergelo, "__builtin_spe_evmergelo", SPE_BUILTIN_EVMERGELO },
5937 { 0, CODE_FOR_spe_evmergelohi, "__builtin_spe_evmergelohi", SPE_BUILTIN_EVMERGELOHI },
5938 { 0, CODE_FOR_spe_evmhegsmfaa, "__builtin_spe_evmhegsmfaa", SPE_BUILTIN_EVMHEGSMFAA },
5939 { 0, CODE_FOR_spe_evmhegsmfan, "__builtin_spe_evmhegsmfan", SPE_BUILTIN_EVMHEGSMFAN },
5940 { 0, CODE_FOR_spe_evmhegsmiaa, "__builtin_spe_evmhegsmiaa", SPE_BUILTIN_EVMHEGSMIAA },
5941 { 0, CODE_FOR_spe_evmhegsmian, "__builtin_spe_evmhegsmian", SPE_BUILTIN_EVMHEGSMIAN },
5942 { 0, CODE_FOR_spe_evmhegumiaa, "__builtin_spe_evmhegumiaa", SPE_BUILTIN_EVMHEGUMIAA },
5943 { 0, CODE_FOR_spe_evmhegumian, "__builtin_spe_evmhegumian", SPE_BUILTIN_EVMHEGUMIAN },
5944 { 0, CODE_FOR_spe_evmhesmf, "__builtin_spe_evmhesmf", SPE_BUILTIN_EVMHESMF },
5945 { 0, CODE_FOR_spe_evmhesmfa, "__builtin_spe_evmhesmfa", SPE_BUILTIN_EVMHESMFA },
5946 { 0, CODE_FOR_spe_evmhesmfaaw, "__builtin_spe_evmhesmfaaw", SPE_BUILTIN_EVMHESMFAAW },
5947 { 0, CODE_FOR_spe_evmhesmfanw, "__builtin_spe_evmhesmfanw", SPE_BUILTIN_EVMHESMFANW },
5948 { 0, CODE_FOR_spe_evmhesmi, "__builtin_spe_evmhesmi", SPE_BUILTIN_EVMHESMI },
5949 { 0, CODE_FOR_spe_evmhesmia, "__builtin_spe_evmhesmia", SPE_BUILTIN_EVMHESMIA },
5950 { 0, CODE_FOR_spe_evmhesmiaaw, "__builtin_spe_evmhesmiaaw", SPE_BUILTIN_EVMHESMIAAW },
5951 { 0, CODE_FOR_spe_evmhesmianw, "__builtin_spe_evmhesmianw", SPE_BUILTIN_EVMHESMIANW },
5952 { 0, CODE_FOR_spe_evmhessf, "__builtin_spe_evmhessf", SPE_BUILTIN_EVMHESSF },
5953 { 0, CODE_FOR_spe_evmhessfa, "__builtin_spe_evmhessfa", SPE_BUILTIN_EVMHESSFA },
5954 { 0, CODE_FOR_spe_evmhessfaaw, "__builtin_spe_evmhessfaaw", SPE_BUILTIN_EVMHESSFAAW },
5955 { 0, CODE_FOR_spe_evmhessfanw, "__builtin_spe_evmhessfanw", SPE_BUILTIN_EVMHESSFANW },
5956 { 0, CODE_FOR_spe_evmhessiaaw, "__builtin_spe_evmhessiaaw", SPE_BUILTIN_EVMHESSIAAW },
5957 { 0, CODE_FOR_spe_evmhessianw, "__builtin_spe_evmhessianw", SPE_BUILTIN_EVMHESSIANW },
5958 { 0, CODE_FOR_spe_evmheumi, "__builtin_spe_evmheumi", SPE_BUILTIN_EVMHEUMI },
5959 { 0, CODE_FOR_spe_evmheumia, "__builtin_spe_evmheumia", SPE_BUILTIN_EVMHEUMIA },
5960 { 0, CODE_FOR_spe_evmheumiaaw, "__builtin_spe_evmheumiaaw", SPE_BUILTIN_EVMHEUMIAAW },
5961 { 0, CODE_FOR_spe_evmheumianw, "__builtin_spe_evmheumianw", SPE_BUILTIN_EVMHEUMIANW },
5962 { 0, CODE_FOR_spe_evmheusiaaw, "__builtin_spe_evmheusiaaw", SPE_BUILTIN_EVMHEUSIAAW },
5963 { 0, CODE_FOR_spe_evmheusianw, "__builtin_spe_evmheusianw", SPE_BUILTIN_EVMHEUSIANW },
5964 { 0, CODE_FOR_spe_evmhogsmfaa, "__builtin_spe_evmhogsmfaa", SPE_BUILTIN_EVMHOGSMFAA },
5965 { 0, CODE_FOR_spe_evmhogsmfan, "__builtin_spe_evmhogsmfan", SPE_BUILTIN_EVMHOGSMFAN },
5966 { 0, CODE_FOR_spe_evmhogsmiaa, "__builtin_spe_evmhogsmiaa", SPE_BUILTIN_EVMHOGSMIAA },
5967 { 0, CODE_FOR_spe_evmhogsmian, "__builtin_spe_evmhogsmian", SPE_BUILTIN_EVMHOGSMIAN },
5968 { 0, CODE_FOR_spe_evmhogumiaa, "__builtin_spe_evmhogumiaa", SPE_BUILTIN_EVMHOGUMIAA },
5969 { 0, CODE_FOR_spe_evmhogumian, "__builtin_spe_evmhogumian", SPE_BUILTIN_EVMHOGUMIAN },
5970 { 0, CODE_FOR_spe_evmhosmf, "__builtin_spe_evmhosmf", SPE_BUILTIN_EVMHOSMF },
5971 { 0, CODE_FOR_spe_evmhosmfa, "__builtin_spe_evmhosmfa", SPE_BUILTIN_EVMHOSMFA },
5972 { 0, CODE_FOR_spe_evmhosmfaaw, "__builtin_spe_evmhosmfaaw", SPE_BUILTIN_EVMHOSMFAAW },
5973 { 0, CODE_FOR_spe_evmhosmfanw, "__builtin_spe_evmhosmfanw", SPE_BUILTIN_EVMHOSMFANW },
5974 { 0, CODE_FOR_spe_evmhosmi, "__builtin_spe_evmhosmi", SPE_BUILTIN_EVMHOSMI },
5975 { 0, CODE_FOR_spe_evmhosmia, "__builtin_spe_evmhosmia", SPE_BUILTIN_EVMHOSMIA },
5976 { 0, CODE_FOR_spe_evmhosmiaaw, "__builtin_spe_evmhosmiaaw", SPE_BUILTIN_EVMHOSMIAAW },
5977 { 0, CODE_FOR_spe_evmhosmianw, "__builtin_spe_evmhosmianw", SPE_BUILTIN_EVMHOSMIANW },
5978 { 0, CODE_FOR_spe_evmhossf, "__builtin_spe_evmhossf", SPE_BUILTIN_EVMHOSSF },
5979 { 0, CODE_FOR_spe_evmhossfa, "__builtin_spe_evmhossfa", SPE_BUILTIN_EVMHOSSFA },
5980 { 0, CODE_FOR_spe_evmhossfaaw, "__builtin_spe_evmhossfaaw", SPE_BUILTIN_EVMHOSSFAAW },
5981 { 0, CODE_FOR_spe_evmhossfanw, "__builtin_spe_evmhossfanw", SPE_BUILTIN_EVMHOSSFANW },
5982 { 0, CODE_FOR_spe_evmhossiaaw, "__builtin_spe_evmhossiaaw", SPE_BUILTIN_EVMHOSSIAAW },
5983 { 0, CODE_FOR_spe_evmhossianw, "__builtin_spe_evmhossianw", SPE_BUILTIN_EVMHOSSIANW },
5984 { 0, CODE_FOR_spe_evmhoumi, "__builtin_spe_evmhoumi", SPE_BUILTIN_EVMHOUMI },
5985 { 0, CODE_FOR_spe_evmhoumia, "__builtin_spe_evmhoumia", SPE_BUILTIN_EVMHOUMIA },
5986 { 0, CODE_FOR_spe_evmhoumiaaw, "__builtin_spe_evmhoumiaaw", SPE_BUILTIN_EVMHOUMIAAW },
5987 { 0, CODE_FOR_spe_evmhoumianw, "__builtin_spe_evmhoumianw", SPE_BUILTIN_EVMHOUMIANW },
5988 { 0, CODE_FOR_spe_evmhousiaaw, "__builtin_spe_evmhousiaaw", SPE_BUILTIN_EVMHOUSIAAW },
5989 { 0, CODE_FOR_spe_evmhousianw, "__builtin_spe_evmhousianw", SPE_BUILTIN_EVMHOUSIANW },
5990 { 0, CODE_FOR_spe_evmwhsmf, "__builtin_spe_evmwhsmf", SPE_BUILTIN_EVMWHSMF },
5991 { 0, CODE_FOR_spe_evmwhsmfa, "__builtin_spe_evmwhsmfa", SPE_BUILTIN_EVMWHSMFA },
5992 { 0, CODE_FOR_spe_evmwhsmi, "__builtin_spe_evmwhsmi", SPE_BUILTIN_EVMWHSMI },
5993 { 0, CODE_FOR_spe_evmwhsmia, "__builtin_spe_evmwhsmia", SPE_BUILTIN_EVMWHSMIA },
5994 { 0, CODE_FOR_spe_evmwhssf, "__builtin_spe_evmwhssf", SPE_BUILTIN_EVMWHSSF },
5995 { 0, CODE_FOR_spe_evmwhssfa, "__builtin_spe_evmwhssfa", SPE_BUILTIN_EVMWHSSFA },
5996 { 0, CODE_FOR_spe_evmwhumi, "__builtin_spe_evmwhumi", SPE_BUILTIN_EVMWHUMI },
5997 { 0, CODE_FOR_spe_evmwhumia, "__builtin_spe_evmwhumia", SPE_BUILTIN_EVMWHUMIA },
a3170dc6
AH		 5998 { 0, CODE_FOR_spe_evmwlsmiaaw, "__builtin_spe_evmwlsmiaaw", SPE_BUILTIN_EVMWLSMIAAW },
5999 { 0, CODE_FOR_spe_evmwlsmianw, "__builtin_spe_evmwlsmianw", SPE_BUILTIN_EVMWLSMIANW },
a3170dc6
AH		 6000 { 0, CODE_FOR_spe_evmwlssiaaw, "__builtin_spe_evmwlssiaaw", SPE_BUILTIN_EVMWLSSIAAW },
6001 { 0, CODE_FOR_spe_evmwlssianw, "__builtin_spe_evmwlssianw", SPE_BUILTIN_EVMWLSSIANW },
6002 { 0, CODE_FOR_spe_evmwlumi, "__builtin_spe_evmwlumi", SPE_BUILTIN_EVMWLUMI },
6003 { 0, CODE_FOR_spe_evmwlumia, "__builtin_spe_evmwlumia", SPE_BUILTIN_EVMWLUMIA },
6004 { 0, CODE_FOR_spe_evmwlumiaaw, "__builtin_spe_evmwlumiaaw", SPE_BUILTIN_EVMWLUMIAAW },
6005 { 0, CODE_FOR_spe_evmwlumianw, "__builtin_spe_evmwlumianw", SPE_BUILTIN_EVMWLUMIANW },
6006 { 0, CODE_FOR_spe_evmwlusiaaw, "__builtin_spe_evmwlusiaaw", SPE_BUILTIN_EVMWLUSIAAW },
6007 { 0, CODE_FOR_spe_evmwlusianw, "__builtin_spe_evmwlusianw", SPE_BUILTIN_EVMWLUSIANW },
6008 { 0, CODE_FOR_spe_evmwsmf, "__builtin_spe_evmwsmf", SPE_BUILTIN_EVMWSMF },
6009 { 0, CODE_FOR_spe_evmwsmfa, "__builtin_spe_evmwsmfa", SPE_BUILTIN_EVMWSMFA },
6010 { 0, CODE_FOR_spe_evmwsmfaa, "__builtin_spe_evmwsmfaa", SPE_BUILTIN_EVMWSMFAA },
6011 { 0, CODE_FOR_spe_evmwsmfan, "__builtin_spe_evmwsmfan", SPE_BUILTIN_EVMWSMFAN },
6012 { 0, CODE_FOR_spe_evmwsmi, "__builtin_spe_evmwsmi", SPE_BUILTIN_EVMWSMI },
6013 { 0, CODE_FOR_spe_evmwsmia, "__builtin_spe_evmwsmia", SPE_BUILTIN_EVMWSMIA },
6014 { 0, CODE_FOR_spe_evmwsmiaa, "__builtin_spe_evmwsmiaa", SPE_BUILTIN_EVMWSMIAA },
6015 { 0, CODE_FOR_spe_evmwsmian, "__builtin_spe_evmwsmian", SPE_BUILTIN_EVMWSMIAN },
6016 { 0, CODE_FOR_spe_evmwssf, "__builtin_spe_evmwssf", SPE_BUILTIN_EVMWSSF },
6017 { 0, CODE_FOR_spe_evmwssfa, "__builtin_spe_evmwssfa", SPE_BUILTIN_EVMWSSFA },
6018 { 0, CODE_FOR_spe_evmwssfaa, "__builtin_spe_evmwssfaa", SPE_BUILTIN_EVMWSSFAA },
6019 { 0, CODE_FOR_spe_evmwssfan, "__builtin_spe_evmwssfan", SPE_BUILTIN_EVMWSSFAN },
6020 { 0, CODE_FOR_spe_evmwumi, "__builtin_spe_evmwumi", SPE_BUILTIN_EVMWUMI },
6021 { 0, CODE_FOR_spe_evmwumia, "__builtin_spe_evmwumia", SPE_BUILTIN_EVMWUMIA },
6022 { 0, CODE_FOR_spe_evmwumiaa, "__builtin_spe_evmwumiaa", SPE_BUILTIN_EVMWUMIAA },
6023 { 0, CODE_FOR_spe_evmwumian, "__builtin_spe_evmwumian", SPE_BUILTIN_EVMWUMIAN },
6024 { 0, CODE_FOR_spe_evnand, "__builtin_spe_evnand", SPE_BUILTIN_EVNAND },
6025 { 0, CODE_FOR_spe_evnor, "__builtin_spe_evnor", SPE_BUILTIN_EVNOR },
6026 { 0, CODE_FOR_spe_evor, "__builtin_spe_evor", SPE_BUILTIN_EVOR },
6027 { 0, CODE_FOR_spe_evorc, "__builtin_spe_evorc", SPE_BUILTIN_EVORC },
6028 { 0, CODE_FOR_spe_evrlw, "__builtin_spe_evrlw", SPE_BUILTIN_EVRLW },
6029 { 0, CODE_FOR_spe_evslw, "__builtin_spe_evslw", SPE_BUILTIN_EVSLW },
6030 { 0, CODE_FOR_spe_evsrws, "__builtin_spe_evsrws", SPE_BUILTIN_EVSRWS },
6031 { 0, CODE_FOR_spe_evsrwu, "__builtin_spe_evsrwu", SPE_BUILTIN_EVSRWU },
6032 { 0, CODE_FOR_spe_evsubfw, "__builtin_spe_evsubfw", SPE_BUILTIN_EVSUBFW },
6033
6034 /* SPE binary operations expecting a 5-bit unsigned literal. */
6035 { 0, CODE_FOR_spe_evaddiw, "__builtin_spe_evaddiw", SPE_BUILTIN_EVADDIW },
6036
6037 { 0, CODE_FOR_spe_evrlwi, "__builtin_spe_evrlwi", SPE_BUILTIN_EVRLWI },
6038 { 0, CODE_FOR_spe_evslwi, "__builtin_spe_evslwi", SPE_BUILTIN_EVSLWI },
6039 { 0, CODE_FOR_spe_evsrwis, "__builtin_spe_evsrwis", SPE_BUILTIN_EVSRWIS },
6040 { 0, CODE_FOR_spe_evsrwiu, "__builtin_spe_evsrwiu", SPE_BUILTIN_EVSRWIU },
6041 { 0, CODE_FOR_spe_evsubifw, "__builtin_spe_evsubifw", SPE_BUILTIN_EVSUBIFW },
6042 { 0, CODE_FOR_spe_evmwhssfaa, "__builtin_spe_evmwhssfaa", SPE_BUILTIN_EVMWHSSFAA },
6043 { 0, CODE_FOR_spe_evmwhssmaa, "__builtin_spe_evmwhssmaa", SPE_BUILTIN_EVMWHSSMAA },
6044 { 0, CODE_FOR_spe_evmwhsmfaa, "__builtin_spe_evmwhsmfaa", SPE_BUILTIN_EVMWHSMFAA },
6045 { 0, CODE_FOR_spe_evmwhsmiaa, "__builtin_spe_evmwhsmiaa", SPE_BUILTIN_EVMWHSMIAA },
6046 { 0, CODE_FOR_spe_evmwhusiaa, "__builtin_spe_evmwhusiaa", SPE_BUILTIN_EVMWHUSIAA },
6047 { 0, CODE_FOR_spe_evmwhumiaa, "__builtin_spe_evmwhumiaa", SPE_BUILTIN_EVMWHUMIAA },
6048 { 0, CODE_FOR_spe_evmwhssfan, "__builtin_spe_evmwhssfan", SPE_BUILTIN_EVMWHSSFAN },
6049 { 0, CODE_FOR_spe_evmwhssian, "__builtin_spe_evmwhssian", SPE_BUILTIN_EVMWHSSIAN },
6050 { 0, CODE_FOR_spe_evmwhsmfan, "__builtin_spe_evmwhsmfan", SPE_BUILTIN_EVMWHSMFAN },
6051 { 0, CODE_FOR_spe_evmwhsmian, "__builtin_spe_evmwhsmian", SPE_BUILTIN_EVMWHSMIAN },
6052 { 0, CODE_FOR_spe_evmwhusian, "__builtin_spe_evmwhusian", SPE_BUILTIN_EVMWHUSIAN },
6053 { 0, CODE_FOR_spe_evmwhumian, "__builtin_spe_evmwhumian", SPE_BUILTIN_EVMWHUMIAN },
6054 { 0, CODE_FOR_spe_evmwhgssfaa, "__builtin_spe_evmwhgssfaa", SPE_BUILTIN_EVMWHGSSFAA },
6055 { 0, CODE_FOR_spe_evmwhgsmfaa, "__builtin_spe_evmwhgsmfaa", SPE_BUILTIN_EVMWHGSMFAA },
6056 { 0, CODE_FOR_spe_evmwhgsmiaa, "__builtin_spe_evmwhgsmiaa", SPE_BUILTIN_EVMWHGSMIAA },
6057 { 0, CODE_FOR_spe_evmwhgumiaa, "__builtin_spe_evmwhgumiaa", SPE_BUILTIN_EVMWHGUMIAA },
6058 { 0, CODE_FOR_spe_evmwhgssfan, "__builtin_spe_evmwhgssfan", SPE_BUILTIN_EVMWHGSSFAN },
6059 { 0, CODE_FOR_spe_evmwhgsmfan, "__builtin_spe_evmwhgsmfan", SPE_BUILTIN_EVMWHGSMFAN },
6060 { 0, CODE_FOR_spe_evmwhgsmian, "__builtin_spe_evmwhgsmian", SPE_BUILTIN_EVMWHGSMIAN },
6061 { 0, CODE_FOR_spe_evmwhgumian, "__builtin_spe_evmwhgumian", SPE_BUILTIN_EVMWHGUMIAN },
6062 { 0, CODE_FOR_spe_brinc, "__builtin_spe_brinc", SPE_BUILTIN_BRINC },
6063
6064 /* Place-holder. Leave as last binary SPE builtin. */
58646b77 6065 { 0, CODE_FOR_xorv2si3, "__builtin_spe_evxor", SPE_BUILTIN_EVXOR }
ae4b4a02
AH		 6066};
6067
6068/* AltiVec predicates. */
6069
6070struct builtin_description_predicates
6071{
6072 const unsigned int mask;
6073 const enum insn_code icode;
6074 const char *opcode;
6075 const char *const name;
6076 const enum rs6000_builtins code;
6077};
6078
6079static const struct builtin_description_predicates bdesc_altivec_preds[] =
6080{
6081 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpbfp.", "__builtin_altivec_vcmpbfp_p", ALTIVEC_BUILTIN_VCMPBFP_P },
6082 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpeqfp.", "__builtin_altivec_vcmpeqfp_p", ALTIVEC_BUILTIN_VCMPEQFP_P },
6083 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpgefp.", "__builtin_altivec_vcmpgefp_p", ALTIVEC_BUILTIN_VCMPGEFP_P },
6084 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpgtfp.", "__builtin_altivec_vcmpgtfp_p", ALTIVEC_BUILTIN_VCMPGTFP_P },
6085 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpequw.", "__builtin_altivec_vcmpequw_p", ALTIVEC_BUILTIN_VCMPEQUW_P },
6086 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpgtsw.", "__builtin_altivec_vcmpgtsw_p", ALTIVEC_BUILTIN_VCMPGTSW_P },
6087 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpgtuw.", "__builtin_altivec_vcmpgtuw_p", ALTIVEC_BUILTIN_VCMPGTUW_P },
6088 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpgtuh.", "__builtin_altivec_vcmpgtuh_p", ALTIVEC_BUILTIN_VCMPGTUH_P },
6089 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpgtsh.", "__builtin_altivec_vcmpgtsh_p", ALTIVEC_BUILTIN_VCMPGTSH_P },
6090 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpequh.", "__builtin_altivec_vcmpequh_p", ALTIVEC_BUILTIN_VCMPEQUH_P },
6091 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpequb.", "__builtin_altivec_vcmpequb_p", ALTIVEC_BUILTIN_VCMPEQUB_P },
6092 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpgtsb.", "__builtin_altivec_vcmpgtsb_p", ALTIVEC_BUILTIN_VCMPGTSB_P },
58646b77
PB		 6093 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpgtub.", "__builtin_altivec_vcmpgtub_p", ALTIVEC_BUILTIN_VCMPGTUB_P },
6094
6095 { MASK_ALTIVEC, 0, NULL, "__builtin_vec_vcmpeq_p", ALTIVEC_BUILTIN_VCMPEQ_P },
6096 { MASK_ALTIVEC, 0, NULL, "__builtin_vec_vcmpgt_p", ALTIVEC_BUILTIN_VCMPGT_P },
6097 { MASK_ALTIVEC, 0, NULL, "__builtin_vec_vcmpge_p", ALTIVEC_BUILTIN_VCMPGE_P }
0ac081f6 6098};
24408032 6099
a3170dc6
AH		 6100/* SPE predicates. */
6101static struct builtin_description bdesc_spe_predicates[] =
6102{
6103 /* Place-holder. Leave as first. */
6104 { 0, CODE_FOR_spe_evcmpeq, "__builtin_spe_evcmpeq", SPE_BUILTIN_EVCMPEQ },
6105 { 0, CODE_FOR_spe_evcmpgts, "__builtin_spe_evcmpgts", SPE_BUILTIN_EVCMPGTS },
6106 { 0, CODE_FOR_spe_evcmpgtu, "__builtin_spe_evcmpgtu", SPE_BUILTIN_EVCMPGTU },
6107 { 0, CODE_FOR_spe_evcmplts, "__builtin_spe_evcmplts", SPE_BUILTIN_EVCMPLTS },
6108 { 0, CODE_FOR_spe_evcmpltu, "__builtin_spe_evcmpltu", SPE_BUILTIN_EVCMPLTU },
6109 { 0, CODE_FOR_spe_evfscmpeq, "__builtin_spe_evfscmpeq", SPE_BUILTIN_EVFSCMPEQ },
6110 { 0, CODE_FOR_spe_evfscmpgt, "__builtin_spe_evfscmpgt", SPE_BUILTIN_EVFSCMPGT },
6111 { 0, CODE_FOR_spe_evfscmplt, "__builtin_spe_evfscmplt", SPE_BUILTIN_EVFSCMPLT },
6112 { 0, CODE_FOR_spe_evfststeq, "__builtin_spe_evfststeq", SPE_BUILTIN_EVFSTSTEQ },
6113 { 0, CODE_FOR_spe_evfststgt, "__builtin_spe_evfststgt", SPE_BUILTIN_EVFSTSTGT },
6114 /* Place-holder. Leave as last. */
6115 { 0, CODE_FOR_spe_evfststlt, "__builtin_spe_evfststlt", SPE_BUILTIN_EVFSTSTLT },
6116};
6117
6118/* SPE evsel predicates. */
6119static struct builtin_description bdesc_spe_evsel[] =
6120{
6121 /* Place-holder. Leave as first. */
6122 { 0, CODE_FOR_spe_evcmpgts, "__builtin_spe_evsel_gts", SPE_BUILTIN_EVSEL_CMPGTS },
6123 { 0, CODE_FOR_spe_evcmpgtu, "__builtin_spe_evsel_gtu", SPE_BUILTIN_EVSEL_CMPGTU },
6124 { 0, CODE_FOR_spe_evcmplts, "__builtin_spe_evsel_lts", SPE_BUILTIN_EVSEL_CMPLTS },
6125 { 0, CODE_FOR_spe_evcmpltu, "__builtin_spe_evsel_ltu", SPE_BUILTIN_EVSEL_CMPLTU },
6126 { 0, CODE_FOR_spe_evcmpeq, "__builtin_spe_evsel_eq", SPE_BUILTIN_EVSEL_CMPEQ },
6127 { 0, CODE_FOR_spe_evfscmpgt, "__builtin_spe_evsel_fsgt", SPE_BUILTIN_EVSEL_FSCMPGT },
6128 { 0, CODE_FOR_spe_evfscmplt, "__builtin_spe_evsel_fslt", SPE_BUILTIN_EVSEL_FSCMPLT },
6129 { 0, CODE_FOR_spe_evfscmpeq, "__builtin_spe_evsel_fseq", SPE_BUILTIN_EVSEL_FSCMPEQ },
6130 { 0, CODE_FOR_spe_evfststgt, "__builtin_spe_evsel_fststgt", SPE_BUILTIN_EVSEL_FSTSTGT },
6131 { 0, CODE_FOR_spe_evfststlt, "__builtin_spe_evsel_fststlt", SPE_BUILTIN_EVSEL_FSTSTLT },
6132 /* Place-holder. Leave as last. */
6133 { 0, CODE_FOR_spe_evfststeq, "__builtin_spe_evsel_fststeq", SPE_BUILTIN_EVSEL_FSTSTEQ },
6134};
6135
b6d08ca1 6136/* ABS* operations. */
100c4561
AH		 6137
6138static const struct builtin_description bdesc_abs[] =
6139{
6140 { MASK_ALTIVEC, CODE_FOR_absv4si2, "__builtin_altivec_abs_v4si", ALTIVEC_BUILTIN_ABS_V4SI },
6141 { MASK_ALTIVEC, CODE_FOR_absv8hi2, "__builtin_altivec_abs_v8hi", ALTIVEC_BUILTIN_ABS_V8HI },
6142 { MASK_ALTIVEC, CODE_FOR_absv4sf2, "__builtin_altivec_abs_v4sf", ALTIVEC_BUILTIN_ABS_V4SF },
6143 { MASK_ALTIVEC, CODE_FOR_absv16qi2, "__builtin_altivec_abs_v16qi", ALTIVEC_BUILTIN_ABS_V16QI },
6144 { MASK_ALTIVEC, CODE_FOR_altivec_abss_v4si, "__builtin_altivec_abss_v4si", ALTIVEC_BUILTIN_ABSS_V4SI },
6145 { MASK_ALTIVEC, CODE_FOR_altivec_abss_v8hi, "__builtin_altivec_abss_v8hi", ALTIVEC_BUILTIN_ABSS_V8HI },
6146 { MASK_ALTIVEC, CODE_FOR_altivec_abss_v16qi, "__builtin_altivec_abss_v16qi", ALTIVEC_BUILTIN_ABSS_V16QI }
6147};
6148
617e0e1d
DB		 6149/* Simple unary operations: VECb = foo (unsigned literal) or VECb =
6150 foo (VECa). */
24408032 6151
a3170dc6 6152static struct builtin_description bdesc_1arg[] =
2212663f 6153{
617e0e1d
DB		 6154 { MASK_ALTIVEC, CODE_FOR_altivec_vexptefp, "__builtin_altivec_vexptefp", ALTIVEC_BUILTIN_VEXPTEFP },
6155 { MASK_ALTIVEC, CODE_FOR_altivec_vlogefp, "__builtin_altivec_vlogefp", ALTIVEC_BUILTIN_VLOGEFP },
6156 { MASK_ALTIVEC, CODE_FOR_altivec_vrefp, "__builtin_altivec_vrefp", ALTIVEC_BUILTIN_VREFP },
6157 { MASK_ALTIVEC, CODE_FOR_altivec_vrfim, "__builtin_altivec_vrfim", ALTIVEC_BUILTIN_VRFIM },
6158 { MASK_ALTIVEC, CODE_FOR_altivec_vrfin, "__builtin_altivec_vrfin", ALTIVEC_BUILTIN_VRFIN },
6159 { MASK_ALTIVEC, CODE_FOR_altivec_vrfip, "__builtin_altivec_vrfip", ALTIVEC_BUILTIN_VRFIP },
6160 { MASK_ALTIVEC, CODE_FOR_ftruncv4sf2, "__builtin_altivec_vrfiz", ALTIVEC_BUILTIN_VRFIZ },
6161 { MASK_ALTIVEC, CODE_FOR_altivec_vrsqrtefp, "__builtin_altivec_vrsqrtefp", ALTIVEC_BUILTIN_VRSQRTEFP },
2212663f
DB		 6162 { MASK_ALTIVEC, CODE_FOR_altivec_vspltisb, "__builtin_altivec_vspltisb", ALTIVEC_BUILTIN_VSPLTISB },
6163 { MASK_ALTIVEC, CODE_FOR_altivec_vspltish, "__builtin_altivec_vspltish", ALTIVEC_BUILTIN_VSPLTISH },
6164 { MASK_ALTIVEC, CODE_FOR_altivec_vspltisw, "__builtin_altivec_vspltisw", ALTIVEC_BUILTIN_VSPLTISW },
20e26713
AH		 6165 { MASK_ALTIVEC, CODE_FOR_altivec_vupkhsb, "__builtin_altivec_vupkhsb", ALTIVEC_BUILTIN_VUPKHSB },
6166 { MASK_ALTIVEC, CODE_FOR_altivec_vupkhpx, "__builtin_altivec_vupkhpx", ALTIVEC_BUILTIN_VUPKHPX },
6167 { MASK_ALTIVEC, CODE_FOR_altivec_vupkhsh, "__builtin_altivec_vupkhsh", ALTIVEC_BUILTIN_VUPKHSH },
6168 { MASK_ALTIVEC, CODE_FOR_altivec_vupklsb, "__builtin_altivec_vupklsb", ALTIVEC_BUILTIN_VUPKLSB },
6169 { MASK_ALTIVEC, CODE_FOR_altivec_vupklpx, "__builtin_altivec_vupklpx", ALTIVEC_BUILTIN_VUPKLPX },
6170 { MASK_ALTIVEC, CODE_FOR_altivec_vupklsh, "__builtin_altivec_vupklsh", ALTIVEC_BUILTIN_VUPKLSH },
a3170dc6 6171
58646b77
PB		 6172 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_abs", ALTIVEC_BUILTIN_VEC_ABS },
6173 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_abss", ALTIVEC_BUILTIN_VEC_ABSS },
6174 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_ceil", ALTIVEC_BUILTIN_VEC_CEIL },
6175 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_expte", ALTIVEC_BUILTIN_VEC_EXPTE },
6176 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_floor", ALTIVEC_BUILTIN_VEC_FLOOR },
6177 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_loge", ALTIVEC_BUILTIN_VEC_LOGE },
6178 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mtvscr", ALTIVEC_BUILTIN_VEC_MTVSCR },
6179 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_re", ALTIVEC_BUILTIN_VEC_RE },
6180 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_round", ALTIVEC_BUILTIN_VEC_ROUND },
6181 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_rsqrte", ALTIVEC_BUILTIN_VEC_RSQRTE },
6182 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_trunc", ALTIVEC_BUILTIN_VEC_TRUNC },
6183 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_unpackh", ALTIVEC_BUILTIN_VEC_UNPACKH },
6184 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupkhsh", ALTIVEC_BUILTIN_VEC_VUPKHSH },
6185 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupkhpx", ALTIVEC_BUILTIN_VEC_VUPKHPX },
6186 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupkhsb", ALTIVEC_BUILTIN_VEC_VUPKHSB },
6187 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_unpackl", ALTIVEC_BUILTIN_VEC_UNPACKL },
6188 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupklpx", ALTIVEC_BUILTIN_VEC_VUPKLPX },
6189 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupklsh", ALTIVEC_BUILTIN_VEC_VUPKLSH },
6190 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupklsb", ALTIVEC_BUILTIN_VEC_VUPKLSB },
6191
a3170dc6
AH		 6192 /* The SPE unary builtins must start with SPE_BUILTIN_EVABS and
6193 end with SPE_BUILTIN_EVSUBFUSIAAW. */
6194 { 0, CODE_FOR_spe_evabs, "__builtin_spe_evabs", SPE_BUILTIN_EVABS },
6195 { 0, CODE_FOR_spe_evaddsmiaaw, "__builtin_spe_evaddsmiaaw", SPE_BUILTIN_EVADDSMIAAW },
6196 { 0, CODE_FOR_spe_evaddssiaaw, "__builtin_spe_evaddssiaaw", SPE_BUILTIN_EVADDSSIAAW },
6197 { 0, CODE_FOR_spe_evaddumiaaw, "__builtin_spe_evaddumiaaw", SPE_BUILTIN_EVADDUMIAAW },
6198 { 0, CODE_FOR_spe_evaddusiaaw, "__builtin_spe_evaddusiaaw", SPE_BUILTIN_EVADDUSIAAW },
6199 { 0, CODE_FOR_spe_evcntlsw, "__builtin_spe_evcntlsw", SPE_BUILTIN_EVCNTLSW },
6200 { 0, CODE_FOR_spe_evcntlzw, "__builtin_spe_evcntlzw", SPE_BUILTIN_EVCNTLZW },
6201 { 0, CODE_FOR_spe_evextsb, "__builtin_spe_evextsb", SPE_BUILTIN_EVEXTSB },
6202 { 0, CODE_FOR_spe_evextsh, "__builtin_spe_evextsh", SPE_BUILTIN_EVEXTSH },
6203 { 0, CODE_FOR_spe_evfsabs, "__builtin_spe_evfsabs", SPE_BUILTIN_EVFSABS },
6204 { 0, CODE_FOR_spe_evfscfsf, "__builtin_spe_evfscfsf", SPE_BUILTIN_EVFSCFSF },
6205 { 0, CODE_FOR_spe_evfscfsi, "__builtin_spe_evfscfsi", SPE_BUILTIN_EVFSCFSI },
6206 { 0, CODE_FOR_spe_evfscfuf, "__builtin_spe_evfscfuf", SPE_BUILTIN_EVFSCFUF },
6207 { 0, CODE_FOR_spe_evfscfui, "__builtin_spe_evfscfui", SPE_BUILTIN_EVFSCFUI },
6208 { 0, CODE_FOR_spe_evfsctsf, "__builtin_spe_evfsctsf", SPE_BUILTIN_EVFSCTSF },
6209 { 0, CODE_FOR_spe_evfsctsi, "__builtin_spe_evfsctsi", SPE_BUILTIN_EVFSCTSI },
6210 { 0, CODE_FOR_spe_evfsctsiz, "__builtin_spe_evfsctsiz", SPE_BUILTIN_EVFSCTSIZ },
6211 { 0, CODE_FOR_spe_evfsctuf, "__builtin_spe_evfsctuf", SPE_BUILTIN_EVFSCTUF },
6212 { 0, CODE_FOR_spe_evfsctui, "__builtin_spe_evfsctui", SPE_BUILTIN_EVFSCTUI },
6213 { 0, CODE_FOR_spe_evfsctuiz, "__builtin_spe_evfsctuiz", SPE_BUILTIN_EVFSCTUIZ },
6214 { 0, CODE_FOR_spe_evfsnabs, "__builtin_spe_evfsnabs", SPE_BUILTIN_EVFSNABS },
6215 { 0, CODE_FOR_spe_evfsneg, "__builtin_spe_evfsneg", SPE_BUILTIN_EVFSNEG },
6216 { 0, CODE_FOR_spe_evmra, "__builtin_spe_evmra", SPE_BUILTIN_EVMRA },
6a599451 6217 { 0, CODE_FOR_negv2si2, "__builtin_spe_evneg", SPE_BUILTIN_EVNEG },
a3170dc6
AH		 6218 { 0, CODE_FOR_spe_evrndw, "__builtin_spe_evrndw", SPE_BUILTIN_EVRNDW },
6219 { 0, CODE_FOR_spe_evsubfsmiaaw, "__builtin_spe_evsubfsmiaaw", SPE_BUILTIN_EVSUBFSMIAAW },
6220 { 0, CODE_FOR_spe_evsubfssiaaw, "__builtin_spe_evsubfssiaaw", SPE_BUILTIN_EVSUBFSSIAAW },
6221 { 0, CODE_FOR_spe_evsubfumiaaw, "__builtin_spe_evsubfumiaaw", SPE_BUILTIN_EVSUBFUMIAAW },
a3170dc6
AH		 6222
6223 /* Place-holder. Leave as last unary SPE builtin. */
58646b77 6224 { 0, CODE_FOR_spe_evsubfusiaaw, "__builtin_spe_evsubfusiaaw", SPE_BUILTIN_EVSUBFUSIAAW }
2212663f
DB		 6225};
6226
6227static rtx
a2369ed3 6228rs6000_expand_unop_builtin (enum insn_code icode, tree arglist, rtx target)
2212663f
DB		 6229{
6230 rtx pat;
6231 tree arg0 = TREE_VALUE (arglist);
6232 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6233 enum machine_mode tmode = insn_data[icode].operand[0].mode;
6234 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
6235
0559cc77
DE		 6236 if (icode == CODE_FOR_nothing)
6237 /* Builtin not supported on this processor. */
6238 return 0;
6239
20e26713
AH		 6240 /* If we got invalid arguments bail out before generating bad rtl. */
6241 if (arg0 == error_mark_node)
9a171fcd 6242 return const0_rtx;
20e26713 6243
0559cc77
DE		 6244 if (icode == CODE_FOR_altivec_vspltisb
6245 || icode == CODE_FOR_altivec_vspltish
6246 || icode == CODE_FOR_altivec_vspltisw
6247 || icode == CODE_FOR_spe_evsplatfi
6248 || icode == CODE_FOR_spe_evsplati)
b44140e7
AH		 6249 {
6250 /* Only allow 5-bit *signed* literals. */
b44140e7 6251 if (GET_CODE (op0) != CONST_INT
afca671b
DP		 6252 || INTVAL (op0) > 15
6253 || INTVAL (op0) < -16)
b44140e7
AH		 6254 {
6255 error ("argument 1 must be a 5-bit signed literal");
9a171fcd 6256 return const0_rtx;
b44140e7 6257 }
b44140e7
AH		 6258 }
6259
c62f2db5 6260 if (target == 0
2212663f
DB		 6261 || GET_MODE (target) != tmode
6262 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6263 target = gen_reg_rtx (tmode);
6264
6265 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
6266 op0 = copy_to_mode_reg (mode0, op0);
6267
6268 pat = GEN_FCN (icode) (target, op0);
6269 if (! pat)
6270 return 0;
6271 emit_insn (pat);
0ac081f6 6272
2212663f
DB		 6273 return target;
6274}
ae4b4a02 6275
100c4561 6276static rtx
a2369ed3 6277altivec_expand_abs_builtin (enum insn_code icode, tree arglist, rtx target)
100c4561
AH		 6278{
6279 rtx pat, scratch1, scratch2;
6280 tree arg0 = TREE_VALUE (arglist);
6281 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6282 enum machine_mode tmode = insn_data[icode].operand[0].mode;
6283 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
6284
6285 /* If we have invalid arguments, bail out before generating bad rtl. */
6286 if (arg0 == error_mark_node)
9a171fcd 6287 return const0_rtx;
100c4561
AH		 6288
6289 if (target == 0
6290 || GET_MODE (target) != tmode
6291 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6292 target = gen_reg_rtx (tmode);
6293
6294 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
6295 op0 = copy_to_mode_reg (mode0, op0);
6296
6297 scratch1 = gen_reg_rtx (mode0);
6298 scratch2 = gen_reg_rtx (mode0);
6299
6300 pat = GEN_FCN (icode) (target, op0, scratch1, scratch2);
6301 if (! pat)
6302 return 0;
6303 emit_insn (pat);
6304
6305 return target;
6306}
6307
0ac081f6 6308static rtx
a2369ed3 6309rs6000_expand_binop_builtin (enum insn_code icode, tree arglist, rtx target)
0ac081f6
AH		 6310{
6311 rtx pat;
6312 tree arg0 = TREE_VALUE (arglist);
6313 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6314 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6315 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6316 enum machine_mode tmode = insn_data[icode].operand[0].mode;
6317 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
6318 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
6319
0559cc77
DE		 6320 if (icode == CODE_FOR_nothing)
6321 /* Builtin not supported on this processor. */
6322 return 0;
6323
20e26713
AH		 6324 /* If we got invalid arguments bail out before generating bad rtl. */
6325 if (arg0 == error_mark_node || arg1 == error_mark_node)
9a171fcd 6326 return const0_rtx;
20e26713 6327
0559cc77
DE		 6328 if (icode == CODE_FOR_altivec_vcfux
6329 || icode == CODE_FOR_altivec_vcfsx
6330 || icode == CODE_FOR_altivec_vctsxs
6331 || icode == CODE_FOR_altivec_vctuxs
6332 || icode == CODE_FOR_altivec_vspltb
6333 || icode == CODE_FOR_altivec_vsplth
6334 || icode == CODE_FOR_altivec_vspltw
6335 || icode == CODE_FOR_spe_evaddiw
6336 || icode == CODE_FOR_spe_evldd
6337 || icode == CODE_FOR_spe_evldh
6338 || icode == CODE_FOR_spe_evldw
6339 || icode == CODE_FOR_spe_evlhhesplat
6340 || icode == CODE_FOR_spe_evlhhossplat
6341 || icode == CODE_FOR_spe_evlhhousplat
6342 || icode == CODE_FOR_spe_evlwhe
6343 || icode == CODE_FOR_spe_evlwhos
6344 || icode == CODE_FOR_spe_evlwhou
6345 || icode == CODE_FOR_spe_evlwhsplat
6346 || icode == CODE_FOR_spe_evlwwsplat
6347 || icode == CODE_FOR_spe_evrlwi
6348 || icode == CODE_FOR_spe_evslwi
6349 || icode == CODE_FOR_spe_evsrwis
f5119d10 6350 || icode == CODE_FOR_spe_evsubifw
0559cc77 6351 || icode == CODE_FOR_spe_evsrwiu)
b44140e7
AH		 6352 {
6353 /* Only allow 5-bit unsigned literals. */
8bb418a3 6354 STRIP_NOPS (arg1);
b44140e7
AH		 6355 if (TREE_CODE (arg1) != INTEGER_CST
6356 || TREE_INT_CST_LOW (arg1) & ~0x1f)
6357 {
6358 error ("argument 2 must be a 5-bit unsigned literal");
9a171fcd 6359 return const0_rtx;
b44140e7 6360 }
b44140e7
AH		 6361 }
6362
c62f2db5 6363 if (target == 0
0ac081f6
AH		 6364 || GET_MODE (target) != tmode
6365 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6366 target = gen_reg_rtx (tmode);
6367
6368 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
6369 op0 = copy_to_mode_reg (mode0, op0);
6370 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
6371 op1 = copy_to_mode_reg (mode1, op1);
6372
6373 pat = GEN_FCN (icode) (target, op0, op1);
6374 if (! pat)
6375 return 0;
6376 emit_insn (pat);
6377
6378 return target;
6379}
6525c0e7 6380
ae4b4a02 6381static rtx
f676971a 6382altivec_expand_predicate_builtin (enum insn_code icode, const char *opcode,
a2369ed3 6383 tree arglist, rtx target)
ae4b4a02
AH		 6384{
6385 rtx pat, scratch;
6386 tree cr6_form = TREE_VALUE (arglist);
6387 tree arg0 = TREE_VALUE (TREE_CHAIN (arglist));
6388 tree arg1 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
6389 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6390 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6391 enum machine_mode tmode = SImode;
6392 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
6393 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
6394 int cr6_form_int;
6395
6396 if (TREE_CODE (cr6_form) != INTEGER_CST)
6397 {
6398 error ("argument 1 of __builtin_altivec_predicate must be a constant");
9a171fcd 6399 return const0_rtx;
ae4b4a02
AH		 6400 }
6401 else
6402 cr6_form_int = TREE_INT_CST_LOW (cr6_form);
6403
37409796 6404 gcc_assert (mode0 == mode1);
ae4b4a02
AH		 6405
6406 /* If we have invalid arguments, bail out before generating bad rtl. */
6407 if (arg0 == error_mark_node || arg1 == error_mark_node)
9a171fcd 6408 return const0_rtx;
ae4b4a02
AH		 6409
6410 if (target == 0
6411 || GET_MODE (target) != tmode
6412 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6413 target = gen_reg_rtx (tmode);
6414
6415 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
6416 op0 = copy_to_mode_reg (mode0, op0);
6417 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
6418 op1 = copy_to_mode_reg (mode1, op1);
6419
6420 scratch = gen_reg_rtx (mode0);
6421
6422 pat = GEN_FCN (icode) (scratch, op0, op1,
f1c25d3b 6423 gen_rtx_SYMBOL_REF (Pmode, opcode));
ae4b4a02
AH		 6424 if (! pat)
6425 return 0;
6426 emit_insn (pat);
6427
6428 /* The vec_any* and vec_all* predicates use the same opcodes for two
6429 different operations, but the bits in CR6 will be different
6430 depending on what information we want. So we have to play tricks
6431 with CR6 to get the right bits out.
6432
6433 If you think this is disgusting, look at the specs for the
6434 AltiVec predicates. */
6435
c4ad648e
AM		 6436 switch (cr6_form_int)
6437 {
6438 case 0:
6439 emit_insn (gen_cr6_test_for_zero (target));
6440 break;
6441 case 1:
6442 emit_insn (gen_cr6_test_for_zero_reverse (target));
6443 break;
6444 case 2:
6445 emit_insn (gen_cr6_test_for_lt (target));
6446 break;
6447 case 3:
6448 emit_insn (gen_cr6_test_for_lt_reverse (target));
6449 break;
6450 default:
6451 error ("argument 1 of __builtin_altivec_predicate is out of range");
6452 break;
6453 }
ae4b4a02
AH		 6454
6455 return target;
6456}
6457
b4a62fa0 6458static rtx
38f391a5 6459altivec_expand_lv_builtin (enum insn_code icode, tree arglist, rtx target)
b4a62fa0
SB		 6460{
6461 rtx pat, addr;
6462 tree arg0 = TREE_VALUE (arglist);
6463 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6464 enum machine_mode tmode = insn_data[icode].operand[0].mode;
6465 enum machine_mode mode0 = Pmode;
6466 enum machine_mode mode1 = Pmode;
6467 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6468 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6469
6470 if (icode == CODE_FOR_nothing)
6471 /* Builtin not supported on this processor. */
6472 return 0;
6473
6474 /* If we got invalid arguments bail out before generating bad rtl. */
6475 if (arg0 == error_mark_node || arg1 == error_mark_node)
6476 return const0_rtx;
6477
6478 if (target == 0
6479 || GET_MODE (target) != tmode
6480 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6481 target = gen_reg_rtx (tmode);
6482
f676971a 6483 op1 = copy_to_mode_reg (mode1, op1);
b4a62fa0
SB		 6484
6485 if (op0 == const0_rtx)
6486 {
6487 addr = gen_rtx_MEM (tmode, op1);
6488 }
6489 else
6490 {
6491 op0 = copy_to_mode_reg (mode0, op0);
6492 addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op0, op1));
6493 }
6494
6495 pat = GEN_FCN (icode) (target, addr);
6496
6497 if (! pat)
6498 return 0;
6499 emit_insn (pat);
6500
6501 return target;
6502}
6503
61bea3b0
AH		 6504static rtx
6505spe_expand_stv_builtin (enum insn_code icode, tree arglist)
6506{
6507 tree arg0 = TREE_VALUE (arglist);
6508 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6509 tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
6510 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6511 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6512 rtx op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
6513 rtx pat;
6514 enum machine_mode mode0 = insn_data[icode].operand[0].mode;
6515 enum machine_mode mode1 = insn_data[icode].operand[1].mode;
6516 enum machine_mode mode2 = insn_data[icode].operand[2].mode;
6517
6518 /* Invalid arguments. Bail before doing anything stoopid! */
6519 if (arg0 == error_mark_node
6520 || arg1 == error_mark_node
6521 || arg2 == error_mark_node)
6522 return const0_rtx;
6523
6524 if (! (*insn_data[icode].operand[2].predicate) (op0, mode2))
6525 op0 = copy_to_mode_reg (mode2, op0);
6526 if (! (*insn_data[icode].operand[0].predicate) (op1, mode0))
6527 op1 = copy_to_mode_reg (mode0, op1);
6528 if (! (*insn_data[icode].operand[1].predicate) (op2, mode1))
6529 op2 = copy_to_mode_reg (mode1, op2);
6530
6531 pat = GEN_FCN (icode) (op1, op2, op0);
6532 if (pat)
6533 emit_insn (pat);
6534 return NULL_RTX;
6535}
6536
6525c0e7 6537static rtx
a2369ed3 6538altivec_expand_stv_builtin (enum insn_code icode, tree arglist)
6525c0e7
AH		 6539{
6540 tree arg0 = TREE_VALUE (arglist);
6541 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6542 tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
6543 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6544 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6545 rtx op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
b4a62fa0
SB		 6546 rtx pat, addr;
6547 enum machine_mode tmode = insn_data[icode].operand[0].mode;
6548 enum machine_mode mode1 = Pmode;
6549 enum machine_mode mode2 = Pmode;
6525c0e7
AH		 6550
6551 /* Invalid arguments. Bail before doing anything stoopid! */
6552 if (arg0 == error_mark_node
6553 || arg1 == error_mark_node
6554 || arg2 == error_mark_node)
9a171fcd 6555 return const0_rtx;
6525c0e7 6556
b4a62fa0
SB		 6557 if (! (*insn_data[icode].operand[1].predicate) (op0, tmode))
6558 op0 = copy_to_mode_reg (tmode, op0);
6559
f676971a 6560 op2 = copy_to_mode_reg (mode2, op2);
b4a62fa0
SB		 6561
6562 if (op1 == const0_rtx)
6563 {
6564 addr = gen_rtx_MEM (tmode, op2);
6565 }
6566 else
6567 {
6568 op1 = copy_to_mode_reg (mode1, op1);
6569 addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op1, op2));
6570 }
6525c0e7 6571
b4a62fa0 6572 pat = GEN_FCN (icode) (addr, op0);
6525c0e7
AH		 6573 if (pat)
6574 emit_insn (pat);
6575 return NULL_RTX;
6576}
6577
2212663f 6578static rtx
a2369ed3 6579rs6000_expand_ternop_builtin (enum insn_code icode, tree arglist, rtx target)
2212663f
DB		 6580{
6581 rtx pat;
6582 tree arg0 = TREE_VALUE (arglist);
6583 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6584 tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
6585 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6586 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6587 rtx op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
6588 enum machine_mode tmode = insn_data[icode].operand[0].mode;
6589 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
6590 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
6591 enum machine_mode mode2 = insn_data[icode].operand[3].mode;
0ac081f6 6592
774b5662
DE		 6593 if (icode == CODE_FOR_nothing)
6594 /* Builtin not supported on this processor. */
6595 return 0;
6596
20e26713
AH		 6597 /* If we got invalid arguments bail out before generating bad rtl. */
6598 if (arg0 == error_mark_node
6599 || arg1 == error_mark_node
6600 || arg2 == error_mark_node)
9a171fcd 6601 return const0_rtx;
20e26713 6602
aba5fb01
NS		 6603 if (icode == CODE_FOR_altivec_vsldoi_v4sf
6604 || icode == CODE_FOR_altivec_vsldoi_v4si
6605 || icode == CODE_FOR_altivec_vsldoi_v8hi
6606 || icode == CODE_FOR_altivec_vsldoi_v16qi)
b44140e7
AH		 6607 {
6608 /* Only allow 4-bit unsigned literals. */
8bb418a3 6609 STRIP_NOPS (arg2);
b44140e7
AH		 6610 if (TREE_CODE (arg2) != INTEGER_CST
6611 || TREE_INT_CST_LOW (arg2) & ~0xf)
6612 {
6613 error ("argument 3 must be a 4-bit unsigned literal");
e3277ffb 6614 return const0_rtx;
b44140e7 6615 }
b44140e7
AH		 6616 }
6617
c62f2db5 6618 if (target == 0
2212663f
DB		 6619 || GET_MODE (target) != tmode
6620 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6621 target = gen_reg_rtx (tmode);
6622
6623 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
6624 op0 = copy_to_mode_reg (mode0, op0);
6625 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
6626 op1 = copy_to_mode_reg (mode1, op1);
6627 if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
6628 op2 = copy_to_mode_reg (mode2, op2);
6629
6630 pat = GEN_FCN (icode) (target, op0, op1, op2);
6631 if (! pat)
6632 return 0;
6633 emit_insn (pat);
6634
6635 return target;
6636}
92898235 6637
3a9b8c7e 6638/* Expand the lvx builtins. */
0ac081f6 6639static rtx
a2369ed3 6640altivec_expand_ld_builtin (tree exp, rtx target, bool *expandedp)
0ac081f6 6641{
0ac081f6
AH		 6642 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
6643 tree arglist = TREE_OPERAND (exp, 1);
0ac081f6 6644 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
3a9b8c7e
AH		 6645 tree arg0;
6646 enum machine_mode tmode, mode0;
7c3abc73 6647 rtx pat, op0;
3a9b8c7e 6648 enum insn_code icode;
92898235 6649
0ac081f6
AH		 6650 switch (fcode)
6651 {
f18c054f 6652 case ALTIVEC_BUILTIN_LD_INTERNAL_16qi:
81466555 6653 icode = CODE_FOR_altivec_lvx_v16qi;
3a9b8c7e 6654 break;
f18c054f 6655 case ALTIVEC_BUILTIN_LD_INTERNAL_8hi:
81466555 6656 icode = CODE_FOR_altivec_lvx_v8hi;
3a9b8c7e
AH		 6657 break;
6658 case ALTIVEC_BUILTIN_LD_INTERNAL_4si:
81466555 6659 icode = CODE_FOR_altivec_lvx_v4si;
3a9b8c7e
AH		 6660 break;
6661 case ALTIVEC_BUILTIN_LD_INTERNAL_4sf:
81466555 6662 icode = CODE_FOR_altivec_lvx_v4sf;
3a9b8c7e
AH		 6663 break;
6664 default:
6665 *expandedp = false;
6666 return NULL_RTX;
6667 }
0ac081f6 6668
3a9b8c7e 6669 *expandedp = true;
f18c054f 6670
3a9b8c7e
AH		 6671 arg0 = TREE_VALUE (arglist);
6672 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6673 tmode = insn_data[icode].operand[0].mode;
6674 mode0 = insn_data[icode].operand[1].mode;
f18c054f 6675
3a9b8c7e
AH		 6676 if (target == 0
6677 || GET_MODE (target) != tmode
6678 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6679 target = gen_reg_rtx (tmode);
24408032 6680
3a9b8c7e
AH		 6681 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
6682 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
f18c054f 6683
3a9b8c7e
AH		 6684 pat = GEN_FCN (icode) (target, op0);
6685 if (! pat)
6686 return 0;
6687 emit_insn (pat);
6688 return target;
6689}
f18c054f 6690
3a9b8c7e
AH		 6691/* Expand the stvx builtins. */
6692static rtx
f676971a 6693altivec_expand_st_builtin (tree exp, rtx target ATTRIBUTE_UNUSED,
a2369ed3 6694 bool *expandedp)
3a9b8c7e
AH		 6695{
6696 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
6697 tree arglist = TREE_OPERAND (exp, 1);
6698 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
6699 tree arg0, arg1;
6700 enum machine_mode mode0, mode1;
7c3abc73 6701 rtx pat, op0, op1;
3a9b8c7e 6702 enum insn_code icode;
f18c054f 6703
3a9b8c7e
AH		 6704 switch (fcode)
6705 {
6706 case ALTIVEC_BUILTIN_ST_INTERNAL_16qi:
81466555 6707 icode = CODE_FOR_altivec_stvx_v16qi;
3a9b8c7e
AH		 6708 break;
6709 case ALTIVEC_BUILTIN_ST_INTERNAL_8hi:
81466555 6710 icode = CODE_FOR_altivec_stvx_v8hi;
3a9b8c7e
AH		 6711 break;
6712 case ALTIVEC_BUILTIN_ST_INTERNAL_4si:
81466555 6713 icode = CODE_FOR_altivec_stvx_v4si;
3a9b8c7e
AH		 6714 break;
6715 case ALTIVEC_BUILTIN_ST_INTERNAL_4sf:
81466555 6716 icode = CODE_FOR_altivec_stvx_v4sf;
3a9b8c7e
AH		 6717 break;
6718 default:
6719 *expandedp = false;
6720 return NULL_RTX;
6721 }
24408032 6722
3a9b8c7e
AH		 6723 arg0 = TREE_VALUE (arglist);
6724 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6725 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6726 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6727 mode0 = insn_data[icode].operand[0].mode;
6728 mode1 = insn_data[icode].operand[1].mode;
f18c054f 6729
3a9b8c7e
AH		 6730 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
6731 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
6732 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
6733 op1 = copy_to_mode_reg (mode1, op1);
f18c054f 6734
3a9b8c7e
AH		 6735 pat = GEN_FCN (icode) (op0, op1);
6736 if (pat)
6737 emit_insn (pat);
f18c054f 6738
3a9b8c7e
AH		 6739 *expandedp = true;
6740 return NULL_RTX;
6741}
f18c054f 6742
3a9b8c7e
AH		 6743/* Expand the dst builtins. */
6744static rtx
f676971a 6745altivec_expand_dst_builtin (tree exp, rtx target ATTRIBUTE_UNUSED,
a2369ed3 6746 bool *expandedp)
3a9b8c7e
AH		 6747{
6748 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
6749 tree arglist = TREE_OPERAND (exp, 1);
6750 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
6751 tree arg0, arg1, arg2;
6752 enum machine_mode mode0, mode1, mode2;
7c3abc73 6753 rtx pat, op0, op1, op2;
3a9b8c7e 6754 struct builtin_description *d;
a3170dc6 6755 size_t i;
f18c054f 6756
3a9b8c7e 6757 *expandedp = false;
f18c054f 6758
3a9b8c7e
AH		 6759 /* Handle DST variants. */
6760 d = (struct builtin_description *) bdesc_dst;
6761 for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++)
6762 if (d->code == fcode)
6763 {
6764 arg0 = TREE_VALUE (arglist);
6765 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6766 arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
6767 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6768 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6769 op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
6770 mode0 = insn_data[d->icode].operand[0].mode;
6771 mode1 = insn_data[d->icode].operand[1].mode;
6772 mode2 = insn_data[d->icode].operand[2].mode;
24408032 6773
3a9b8c7e
AH		 6774 /* Invalid arguments, bail out before generating bad rtl. */
6775 if (arg0 == error_mark_node
6776 || arg1 == error_mark_node
6777 || arg2 == error_mark_node)
6778 return const0_rtx;
f18c054f 6779
86e7df90 6780 *expandedp = true;
8bb418a3 6781 STRIP_NOPS (arg2);
3a9b8c7e
AH		 6782 if (TREE_CODE (arg2) != INTEGER_CST
6783 || TREE_INT_CST_LOW (arg2) & ~0x3)
6784 {
9e637a26 6785 error ("argument to %qs must be a 2-bit unsigned literal", d->name);
3a9b8c7e
AH		 6786 return const0_rtx;
6787 }
f18c054f 6788
3a9b8c7e 6789 if (! (*insn_data[d->icode].operand[0].predicate) (op0, mode0))
666158b9 6790 op0 = copy_to_mode_reg (Pmode, op0);
3a9b8c7e
AH		 6791 if (! (*insn_data[d->icode].operand[1].predicate) (op1, mode1))
6792 op1 = copy_to_mode_reg (mode1, op1);
24408032 6793
3a9b8c7e
AH		 6794 pat = GEN_FCN (d->icode) (op0, op1, op2);
6795 if (pat != 0)
6796 emit_insn (pat);
f18c054f 6797
3a9b8c7e
AH		 6798 return NULL_RTX;
6799 }
f18c054f 6800
3a9b8c7e
AH		 6801 return NULL_RTX;
6802}
24408032 6803
3a9b8c7e
AH		 6804/* Expand the builtin in EXP and store the result in TARGET. Store
6805 true in *EXPANDEDP if we found a builtin to expand. */
6806static rtx
a2369ed3 6807altivec_expand_builtin (tree exp, rtx target, bool *expandedp)
3a9b8c7e
AH		 6808{
6809 struct builtin_description *d;
6810 struct builtin_description_predicates *dp;
6811 size_t i;
6812 enum insn_code icode;
6813 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
6814 tree arglist = TREE_OPERAND (exp, 1);
7c3abc73
AH		 6815 tree arg0;
6816 rtx op0, pat;
6817 enum machine_mode tmode, mode0;
3a9b8c7e 6818 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
0ac081f6 6819
58646b77
PB		 6820 if (fcode >= ALTIVEC_BUILTIN_OVERLOADED_FIRST
6821 && fcode <= ALTIVEC_BUILTIN_OVERLOADED_LAST)
6822 {
6823 *expandedp = true;
6824 error ("unresolved overload for Altivec builtin %qE", fndecl);
6825 return const0_rtx;
6826 }
6827
3a9b8c7e
AH		 6828 target = altivec_expand_ld_builtin (exp, target, expandedp);
6829 if (*expandedp)
6830 return target;
0ac081f6 6831
3a9b8c7e
AH		 6832 target = altivec_expand_st_builtin (exp, target, expandedp);
6833 if (*expandedp)
6834 return target;
6835
6836 target = altivec_expand_dst_builtin (exp, target, expandedp);
6837 if (*expandedp)
6838 return target;
6839
6840 *expandedp = true;
95385cbb 6841
3a9b8c7e
AH		 6842 switch (fcode)
6843 {
6525c0e7
AH		 6844 case ALTIVEC_BUILTIN_STVX:
6845 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx, arglist);
6846 case ALTIVEC_BUILTIN_STVEBX:
6847 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvebx, arglist);
6848 case ALTIVEC_BUILTIN_STVEHX:
6849 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvehx, arglist);
6850 case ALTIVEC_BUILTIN_STVEWX:
6851 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvewx, arglist);
6852 case ALTIVEC_BUILTIN_STVXL:
6853 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl, arglist);
3a9b8c7e 6854
95385cbb
AH		 6855 case ALTIVEC_BUILTIN_MFVSCR:
6856 icode = CODE_FOR_altivec_mfvscr;
6857 tmode = insn_data[icode].operand[0].mode;
6858
6859 if (target == 0
6860 || GET_MODE (target) != tmode
6861 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6862 target = gen_reg_rtx (tmode);
f676971a 6863
95385cbb 6864 pat = GEN_FCN (icode) (target);
0ac081f6
AH		 6865 if (! pat)
6866 return 0;
6867 emit_insn (pat);
95385cbb
AH		 6868 return target;
6869
6870 case ALTIVEC_BUILTIN_MTVSCR:
6871 icode = CODE_FOR_altivec_mtvscr;
6872 arg0 = TREE_VALUE (arglist);
6873 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6874 mode0 = insn_data[icode].operand[0].mode;
6875
6876 /* If we got invalid arguments bail out before generating bad rtl. */
6877 if (arg0 == error_mark_node)
9a171fcd 6878 return const0_rtx;
95385cbb
AH		 6879
6880 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
6881 op0 = copy_to_mode_reg (mode0, op0);
6882
6883 pat = GEN_FCN (icode) (op0);
6884 if (pat)
6885 emit_insn (pat);
6886 return NULL_RTX;
3a9b8c7e 6887
95385cbb
AH		 6888 case ALTIVEC_BUILTIN_DSSALL:
6889 emit_insn (gen_altivec_dssall ());
6890 return NULL_RTX;
6891
6892 case ALTIVEC_BUILTIN_DSS:
6893 icode = CODE_FOR_altivec_dss;
6894 arg0 = TREE_VALUE (arglist);
8bb418a3 6895 STRIP_NOPS (arg0);
95385cbb
AH		 6896 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6897 mode0 = insn_data[icode].operand[0].mode;
6898
6899 /* If we got invalid arguments bail out before generating bad rtl. */
6900 if (arg0 == error_mark_node)
9a171fcd 6901 return const0_rtx;
95385cbb 6902
b44140e7
AH		 6903 if (TREE_CODE (arg0) != INTEGER_CST
6904 || TREE_INT_CST_LOW (arg0) & ~0x3)
6905 {
6906 error ("argument to dss must be a 2-bit unsigned literal");
9a171fcd 6907 return const0_rtx;
b44140e7
AH		 6908 }
6909
95385cbb
AH		 6910 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
6911 op0 = copy_to_mode_reg (mode0, op0);
6912
6913 emit_insn (gen_altivec_dss (op0));
0ac081f6
AH		 6914 return NULL_RTX;
6915 }
24408032 6916
100c4561
AH		 6917 /* Expand abs* operations. */
6918 d = (struct builtin_description *) bdesc_abs;
ca7558fc 6919 for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++)
100c4561
AH		 6920 if (d->code == fcode)
6921 return altivec_expand_abs_builtin (d->icode, arglist, target);
6922
ae4b4a02
AH		 6923 /* Expand the AltiVec predicates. */
6924 dp = (struct builtin_description_predicates *) bdesc_altivec_preds;
ca7558fc 6925 for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, dp++)
ae4b4a02 6926 if (dp->code == fcode)
c4ad648e
AM		 6927 return altivec_expand_predicate_builtin (dp->icode, dp->opcode,
6928 arglist, target);
ae4b4a02 6929
6525c0e7
AH		 6930 /* LV* are funky. We initialized them differently. */
6931 switch (fcode)
6932 {
6933 case ALTIVEC_BUILTIN_LVSL:
b4a62fa0 6934 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsl,
c4ad648e 6935 arglist, target);
6525c0e7 6936 case ALTIVEC_BUILTIN_LVSR:
b4a62fa0 6937 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsr,
c4ad648e 6938 arglist, target);
6525c0e7 6939 case ALTIVEC_BUILTIN_LVEBX:
b4a62fa0 6940 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvebx,
c4ad648e 6941 arglist, target);
6525c0e7 6942 case ALTIVEC_BUILTIN_LVEHX:
b4a62fa0 6943 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvehx,
c4ad648e 6944 arglist, target);
6525c0e7 6945 case ALTIVEC_BUILTIN_LVEWX:
b4a62fa0 6946 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvewx,
c4ad648e 6947 arglist, target);
6525c0e7 6948 case ALTIVEC_BUILTIN_LVXL:
b4a62fa0 6949 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl,
c4ad648e 6950 arglist, target);
6525c0e7 6951 case ALTIVEC_BUILTIN_LVX:
b4a62fa0 6952 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx,
c4ad648e 6953 arglist, target);
6525c0e7
AH		 6954 default:
6955 break;
6956 /* Fall through. */
6957 }
95385cbb 6958
92898235 6959 *expandedp = false;
0ac081f6
AH		 6960 return NULL_RTX;
6961}
6962
a3170dc6
AH		 6963/* Binops that need to be initialized manually, but can be expanded
6964 automagically by rs6000_expand_binop_builtin. */
6965static struct builtin_description bdesc_2arg_spe[] =
6966{
6967 { 0, CODE_FOR_spe_evlddx, "__builtin_spe_evlddx", SPE_BUILTIN_EVLDDX },
6968 { 0, CODE_FOR_spe_evldwx, "__builtin_spe_evldwx", SPE_BUILTIN_EVLDWX },
6969 { 0, CODE_FOR_spe_evldhx, "__builtin_spe_evldhx", SPE_BUILTIN_EVLDHX },
6970 { 0, CODE_FOR_spe_evlwhex, "__builtin_spe_evlwhex", SPE_BUILTIN_EVLWHEX },
6971 { 0, CODE_FOR_spe_evlwhoux, "__builtin_spe_evlwhoux", SPE_BUILTIN_EVLWHOUX },
6972 { 0, CODE_FOR_spe_evlwhosx, "__builtin_spe_evlwhosx", SPE_BUILTIN_EVLWHOSX },
6973 { 0, CODE_FOR_spe_evlwwsplatx, "__builtin_spe_evlwwsplatx", SPE_BUILTIN_EVLWWSPLATX },
6974 { 0, CODE_FOR_spe_evlwhsplatx, "__builtin_spe_evlwhsplatx", SPE_BUILTIN_EVLWHSPLATX },
6975 { 0, CODE_FOR_spe_evlhhesplatx, "__builtin_spe_evlhhesplatx", SPE_BUILTIN_EVLHHESPLATX },
6976 { 0, CODE_FOR_spe_evlhhousplatx, "__builtin_spe_evlhhousplatx", SPE_BUILTIN_EVLHHOUSPLATX },
6977 { 0, CODE_FOR_spe_evlhhossplatx, "__builtin_spe_evlhhossplatx", SPE_BUILTIN_EVLHHOSSPLATX },
6978 { 0, CODE_FOR_spe_evldd, "__builtin_spe_evldd", SPE_BUILTIN_EVLDD },
6979 { 0, CODE_FOR_spe_evldw, "__builtin_spe_evldw", SPE_BUILTIN_EVLDW },
6980 { 0, CODE_FOR_spe_evldh, "__builtin_spe_evldh", SPE_BUILTIN_EVLDH },
6981 { 0, CODE_FOR_spe_evlwhe, "__builtin_spe_evlwhe", SPE_BUILTIN_EVLWHE },
6982 { 0, CODE_FOR_spe_evlwhou, "__builtin_spe_evlwhou", SPE_BUILTIN_EVLWHOU },
6983 { 0, CODE_FOR_spe_evlwhos, "__builtin_spe_evlwhos", SPE_BUILTIN_EVLWHOS },
6984 { 0, CODE_FOR_spe_evlwwsplat, "__builtin_spe_evlwwsplat", SPE_BUILTIN_EVLWWSPLAT },
6985 { 0, CODE_FOR_spe_evlwhsplat, "__builtin_spe_evlwhsplat", SPE_BUILTIN_EVLWHSPLAT },
6986 { 0, CODE_FOR_spe_evlhhesplat, "__builtin_spe_evlhhesplat", SPE_BUILTIN_EVLHHESPLAT },
6987 { 0, CODE_FOR_spe_evlhhousplat, "__builtin_spe_evlhhousplat", SPE_BUILTIN_EVLHHOUSPLAT },
6988 { 0, CODE_FOR_spe_evlhhossplat, "__builtin_spe_evlhhossplat", SPE_BUILTIN_EVLHHOSSPLAT }
6989};
6990
6991/* Expand the builtin in EXP and store the result in TARGET. Store
6992 true in *EXPANDEDP if we found a builtin to expand.
6993
6994 This expands the SPE builtins that are not simple unary and binary
6995 operations. */
6996static rtx
a2369ed3 6997spe_expand_builtin (tree exp, rtx target, bool *expandedp)
a3170dc6
AH		 6998{
6999 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
7000 tree arglist = TREE_OPERAND (exp, 1);
7001 tree arg1, arg0;
7002 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
7003 enum insn_code icode;
7004 enum machine_mode tmode, mode0;
7005 rtx pat, op0;
7006 struct builtin_description *d;
7007 size_t i;
7008
7009 *expandedp = true;
7010
7011 /* Syntax check for a 5-bit unsigned immediate. */
7012 switch (fcode)
7013 {
7014 case SPE_BUILTIN_EVSTDD:
7015 case SPE_BUILTIN_EVSTDH:
7016 case SPE_BUILTIN_EVSTDW:
7017 case SPE_BUILTIN_EVSTWHE:
7018 case SPE_BUILTIN_EVSTWHO:
7019 case SPE_BUILTIN_EVSTWWE:
7020 case SPE_BUILTIN_EVSTWWO:
7021 arg1 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
7022 if (TREE_CODE (arg1) != INTEGER_CST
7023 || TREE_INT_CST_LOW (arg1) & ~0x1f)
7024 {
7025 error ("argument 2 must be a 5-bit unsigned literal");
7026 return const0_rtx;
7027 }
7028 break;
7029 default:
7030 break;
7031 }
7032
00332c9f
AH		 7033 /* The evsplat*i instructions are not quite generic. */
7034 switch (fcode)
7035 {
7036 case SPE_BUILTIN_EVSPLATFI:
7037 return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplatfi,
7038 arglist, target);
7039 case SPE_BUILTIN_EVSPLATI:
7040 return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplati,
7041 arglist, target);
7042 default:
7043 break;
7044 }
7045
a3170dc6
AH		 7046 d = (struct builtin_description *) bdesc_2arg_spe;
7047 for (i = 0; i < ARRAY_SIZE (bdesc_2arg_spe); ++i, ++d)
7048 if (d->code == fcode)
7049 return rs6000_expand_binop_builtin (d->icode, arglist, target);
7050
7051 d = (struct builtin_description *) bdesc_spe_predicates;
7052 for (i = 0; i < ARRAY_SIZE (bdesc_spe_predicates); ++i, ++d)
7053 if (d->code == fcode)
7054 return spe_expand_predicate_builtin (d->icode, arglist, target);
7055
7056 d = (struct builtin_description *) bdesc_spe_evsel;
7057 for (i = 0; i < ARRAY_SIZE (bdesc_spe_evsel); ++i, ++d)
7058 if (d->code == fcode)
7059 return spe_expand_evsel_builtin (d->icode, arglist, target);
7060
7061 switch (fcode)
7062 {
7063 case SPE_BUILTIN_EVSTDDX:
61bea3b0 7064 return spe_expand_stv_builtin (CODE_FOR_spe_evstddx, arglist);
a3170dc6 7065 case SPE_BUILTIN_EVSTDHX:
61bea3b0 7066 return spe_expand_stv_builtin (CODE_FOR_spe_evstdhx, arglist);
a3170dc6 7067 case SPE_BUILTIN_EVSTDWX:
61bea3b0 7068 return spe_expand_stv_builtin (CODE_FOR_spe_evstdwx, arglist);
a3170dc6 7069 case SPE_BUILTIN_EVSTWHEX:
61bea3b0 7070 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhex, arglist);
a3170dc6 7071 case SPE_BUILTIN_EVSTWHOX:
61bea3b0 7072 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhox, arglist);
a3170dc6 7073 case SPE_BUILTIN_EVSTWWEX:
61bea3b0 7074 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwex, arglist);
a3170dc6 7075 case SPE_BUILTIN_EVSTWWOX:
61bea3b0 7076 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwox, arglist);
a3170dc6 7077 case SPE_BUILTIN_EVSTDD:
61bea3b0 7078 return spe_expand_stv_builtin (CODE_FOR_spe_evstdd, arglist);
a3170dc6 7079 case SPE_BUILTIN_EVSTDH:
61bea3b0 7080 return spe_expand_stv_builtin (CODE_FOR_spe_evstdh, arglist);
a3170dc6 7081 case SPE_BUILTIN_EVSTDW:
61bea3b0 7082 return spe_expand_stv_builtin (CODE_FOR_spe_evstdw, arglist);
a3170dc6 7083 case SPE_BUILTIN_EVSTWHE:
61bea3b0 7084 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhe, arglist);
a3170dc6 7085 case SPE_BUILTIN_EVSTWHO:
61bea3b0 7086 return spe_expand_stv_builtin (CODE_FOR_spe_evstwho, arglist);
a3170dc6 7087 case SPE_BUILTIN_EVSTWWE:
61bea3b0 7088 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwe, arglist);
a3170dc6 7089 case SPE_BUILTIN_EVSTWWO:
61bea3b0 7090 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwo, arglist);
a3170dc6
AH		 7091 case SPE_BUILTIN_MFSPEFSCR:
7092 icode = CODE_FOR_spe_mfspefscr;
7093 tmode = insn_data[icode].operand[0].mode;
7094
7095 if (target == 0
7096 || GET_MODE (target) != tmode
7097 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7098 target = gen_reg_rtx (tmode);
f676971a 7099
a3170dc6
AH		 7100 pat = GEN_FCN (icode) (target);
7101 if (! pat)
7102 return 0;
7103 emit_insn (pat);
7104 return target;
7105 case SPE_BUILTIN_MTSPEFSCR:
7106 icode = CODE_FOR_spe_mtspefscr;
7107 arg0 = TREE_VALUE (arglist);
7108 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
7109 mode0 = insn_data[icode].operand[0].mode;
7110
7111 if (arg0 == error_mark_node)
7112 return const0_rtx;
7113
7114 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
7115 op0 = copy_to_mode_reg (mode0, op0);
7116
7117 pat = GEN_FCN (icode) (op0);
7118 if (pat)
7119 emit_insn (pat);
7120 return NULL_RTX;
7121 default:
7122 break;
7123 }
7124
7125 *expandedp = false;
7126 return NULL_RTX;
7127}
7128
7129static rtx
a2369ed3 7130spe_expand_predicate_builtin (enum insn_code icode, tree arglist, rtx target)
a3170dc6
AH		 7131{
7132 rtx pat, scratch, tmp;
7133 tree form = TREE_VALUE (arglist);
7134 tree arg0 = TREE_VALUE (TREE_CHAIN (arglist));
7135 tree arg1 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
7136 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
7137 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
7138 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
7139 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
7140 int form_int;
7141 enum rtx_code code;
7142
7143 if (TREE_CODE (form) != INTEGER_CST)
7144 {
7145 error ("argument 1 of __builtin_spe_predicate must be a constant");
7146 return const0_rtx;
7147 }
7148 else
7149 form_int = TREE_INT_CST_LOW (form);
7150
37409796 7151 gcc_assert (mode0 == mode1);
a3170dc6
AH		 7152
7153 if (arg0 == error_mark_node || arg1 == error_mark_node)
7154 return const0_rtx;
7155
7156 if (target == 0
7157 || GET_MODE (target) != SImode
7158 || ! (*insn_data[icode].operand[0].predicate) (target, SImode))
7159 target = gen_reg_rtx (SImode);
7160
7161 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
7162 op0 = copy_to_mode_reg (mode0, op0);
7163 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
7164 op1 = copy_to_mode_reg (mode1, op1);
7165
7166 scratch = gen_reg_rtx (CCmode);
7167
7168 pat = GEN_FCN (icode) (scratch, op0, op1);
7169 if (! pat)
7170 return const0_rtx;
7171 emit_insn (pat);
7172
7173 /* There are 4 variants for each predicate: _any_, _all_, _upper_,
7174 _lower_. We use one compare, but look in different bits of the
7175 CR for each variant.
7176
7177 There are 2 elements in each SPE simd type (upper/lower). The CR
7178 bits are set as follows:
7179
7180 BIT0 | BIT 1 | BIT 2 | BIT 3
7181 U | L | (U | L) | (U & L)
7182
7183 So, for an "all" relationship, BIT 3 would be set.
7184 For an "any" relationship, BIT 2 would be set. Etc.
7185
7186 Following traditional nomenclature, these bits map to:
7187
7188 BIT0 | BIT 1 | BIT 2 | BIT 3
7189 LT | GT | EQ | OV
7190
7191 Later, we will generate rtl to look in the LT/EQ/EQ/OV bits.
7192 */
7193
7194 switch (form_int)
7195 {
7196 /* All variant. OV bit. */
7197 case 0:
7198 /* We need to get to the OV bit, which is the ORDERED bit. We
7199 could generate (ordered:SI (reg:CC xx) (const_int 0)), but
992d08b1 7200 that's ugly and will make validate_condition_mode die.
a3170dc6
AH		 7201 So let's just use another pattern. */
7202 emit_insn (gen_move_from_CR_ov_bit (target, scratch));
7203 return target;
7204 /* Any variant. EQ bit. */
7205 case 1:
7206 code = EQ;
7207 break;
7208 /* Upper variant. LT bit. */
7209 case 2:
7210 code = LT;
7211 break;
7212 /* Lower variant. GT bit. */
7213 case 3:
7214 code = GT;
7215 break;
7216 default:
7217 error ("argument 1 of __builtin_spe_predicate is out of range");
7218 return const0_rtx;
7219 }
7220
7221 tmp = gen_rtx_fmt_ee (code, SImode, scratch, const0_rtx);
7222 emit_move_insn (target, tmp);
7223
7224 return target;
7225}
7226
7227/* The evsel builtins look like this:
7228
7229 e = __builtin_spe_evsel_OP (a, b, c, d);
7230
7231 and work like this:
7232
7233 e[upper] = a[upper] *OP* b[upper] ? c[upper] : d[upper];
7234 e[lower] = a[lower] *OP* b[lower] ? c[lower] : d[lower];
7235*/
7236
7237static rtx
a2369ed3 7238spe_expand_evsel_builtin (enum insn_code icode, tree arglist, rtx target)
a3170dc6
AH		 7239{
7240 rtx pat, scratch;
7241 tree arg0 = TREE_VALUE (arglist);
7242 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
7243 tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
7244 tree arg3 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (TREE_CHAIN (arglist))));
7245 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
7246 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
7247 rtx op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
7248 rtx op3 = expand_expr (arg3, NULL_RTX, VOIDmode, 0);
7249 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
7250 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
7251
37409796 7252 gcc_assert (mode0 == mode1);
a3170dc6
AH		 7253
7254 if (arg0 == error_mark_node || arg1 == error_mark_node
7255 || arg2 == error_mark_node || arg3 == error_mark_node)
7256 return const0_rtx;
7257
7258 if (target == 0
7259 || GET_MODE (target) != mode0
7260 || ! (*insn_data[icode].operand[0].predicate) (target, mode0))
7261 target = gen_reg_rtx (mode0);
7262
7263 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
7264 op0 = copy_to_mode_reg (mode0, op0);
7265 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
7266 op1 = copy_to_mode_reg (mode0, op1);
7267 if (! (*insn_data[icode].operand[1].predicate) (op2, mode1))
7268 op2 = copy_to_mode_reg (mode0, op2);
7269 if (! (*insn_data[icode].operand[1].predicate) (op3, mode1))
7270 op3 = copy_to_mode_reg (mode0, op3);
7271
7272 /* Generate the compare. */
7273 scratch = gen_reg_rtx (CCmode);
7274 pat = GEN_FCN (icode) (scratch, op0, op1);
7275 if (! pat)
7276 return const0_rtx;
7277 emit_insn (pat);
7278
7279 if (mode0 == V2SImode)
7280 emit_insn (gen_spe_evsel (target, op2, op3, scratch));
7281 else
7282 emit_insn (gen_spe_evsel_fs (target, op2, op3, scratch));
7283
7284 return target;
7285}
7286
0ac081f6
AH		 7287/* Expand an expression EXP that calls a built-in function,
7288 with result going to TARGET if that's convenient
7289 (and in mode MODE if that's convenient).
7290 SUBTARGET may be used as the target for computing one of EXP's operands.
7291 IGNORE is nonzero if the value is to be ignored. */
7292
7293static rtx
a2369ed3 7294rs6000_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
c4ad648e
AM		 7295 enum machine_mode mode ATTRIBUTE_UNUSED,
7296 int ignore ATTRIBUTE_UNUSED)
0ac081f6 7297{
92898235
AH		 7298 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
7299 tree arglist = TREE_OPERAND (exp, 1);
7300 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
7301 struct builtin_description *d;
7302 size_t i;
7303 rtx ret;
7304 bool success;
f676971a 7305
7ccf35ed
DN		 7306 if (fcode == ALTIVEC_BUILTIN_MASK_FOR_LOAD
7307 || fcode == ALTIVEC_BUILTIN_MASK_FOR_STORE)
7308 {
7309 int icode = (int) CODE_FOR_altivec_lvsr;
7310 enum machine_mode tmode = insn_data[icode].operand[0].mode;
7311 enum machine_mode mode = insn_data[icode].operand[1].mode;
7312 tree arg;
7313 rtx op, addr, pat;
7314
37409796 7315 gcc_assert (TARGET_ALTIVEC);
7ccf35ed
DN		 7316
7317 arg = TREE_VALUE (arglist);
37409796 7318 gcc_assert (TREE_CODE (TREE_TYPE (arg)) == POINTER_TYPE);
7ccf35ed
DN		 7319 op = expand_expr (arg, NULL_RTX, Pmode, EXPAND_NORMAL);
7320 addr = memory_address (mode, op);
7321 if (fcode == ALTIVEC_BUILTIN_MASK_FOR_STORE)
7322 op = addr;
7323 else
7324 {
7325 /* For the load case need to negate the address. */
7326 op = gen_reg_rtx (GET_MODE (addr));
7327 emit_insn (gen_rtx_SET (VOIDmode, op,
7328 gen_rtx_NEG (GET_MODE (addr), addr)));
c4ad648e 7329 }
7ccf35ed
DN		 7330 op = gen_rtx_MEM (mode, op);
7331
7332 if (target == 0
7333 || GET_MODE (target) != tmode
7334 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7335 target = gen_reg_rtx (tmode);
7336
7337 /*pat = gen_altivec_lvsr (target, op);*/
7338 pat = GEN_FCN (icode) (target, op);
7339 if (!pat)
7340 return 0;
7341 emit_insn (pat);
7342
7343 return target;
7344 }
7345
0ac081f6 7346 if (TARGET_ALTIVEC)
92898235
AH		 7347 {
7348 ret = altivec_expand_builtin (exp, target, &success);
7349
a3170dc6
AH		 7350 if (success)
7351 return ret;
7352 }
7353 if (TARGET_SPE)
7354 {
7355 ret = spe_expand_builtin (exp, target, &success);
7356
92898235
AH		 7357 if (success)
7358 return ret;
7359 }
7360
37409796
NS		 7361 gcc_assert (TARGET_ALTIVEC || TARGET_SPE);
7362
7363 /* Handle simple unary operations. */
7364 d = (struct builtin_description *) bdesc_1arg;
7365 for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
7366 if (d->code == fcode)
7367 return rs6000_expand_unop_builtin (d->icode, arglist, target);
7368
7369 /* Handle simple binary operations. */
7370 d = (struct builtin_description *) bdesc_2arg;
7371 for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
7372 if (d->code == fcode)
7373 return rs6000_expand_binop_builtin (d->icode, arglist, target);
0ac081f6 7374
37409796
NS		 7375 /* Handle simple ternary operations. */
7376 d = (struct builtin_description *) bdesc_3arg;
7377 for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++)
7378 if (d->code == fcode)
7379 return rs6000_expand_ternop_builtin (d->icode, arglist, target);
7380
7381 gcc_unreachable ();
0ac081f6
AH		 7382}
7383
7c62e993
PB		 7384static tree
7385build_opaque_vector_type (tree node, int nunits)
7386{
7387 node = copy_node (node);
7388 TYPE_MAIN_VARIANT (node) = node;
7389 return build_vector_type (node, nunits);
7390}
7391
0ac081f6 7392static void
863d938c 7393rs6000_init_builtins (void)
0ac081f6 7394{
4a5eab38
PB		 7395 V2SI_type_node = build_vector_type (intSI_type_node, 2);
7396 V2SF_type_node = build_vector_type (float_type_node, 2);
7397 V4HI_type_node = build_vector_type (intHI_type_node, 4);
7398 V4SI_type_node = build_vector_type (intSI_type_node, 4);
7399 V4SF_type_node = build_vector_type (float_type_node, 4);
7e463bda 7400 V8HI_type_node = build_vector_type (intHI_type_node, 8);
4a5eab38
PB		 7401 V16QI_type_node = build_vector_type (intQI_type_node, 16);
7402
7403 unsigned_V16QI_type_node = build_vector_type (unsigned_intQI_type_node, 16);
7404 unsigned_V8HI_type_node = build_vector_type (unsigned_intHI_type_node, 8);
7405 unsigned_V4SI_type_node = build_vector_type (unsigned_intSI_type_node, 4);
7406
7c62e993
PB		 7407 opaque_V2SF_type_node = build_opaque_vector_type (float_type_node, 2);
7408 opaque_V2SI_type_node = build_opaque_vector_type (intSI_type_node, 2);
6035d635 7409 opaque_p_V2SI_type_node = build_pointer_type (opaque_V2SI_type_node);
58646b77 7410 opaque_V4SI_type_node = copy_node (V4SI_type_node);
3fdaa45a 7411
8bb418a3
ZL		 7412 /* The 'vector bool ...' types must be kept distinct from 'vector unsigned ...'
7413 types, especially in C++ land. Similarly, 'vector pixel' is distinct from
7414 'vector unsigned short'. */
7415
8dd16ecc
NS		 7416 bool_char_type_node = build_distinct_type_copy (unsigned_intQI_type_node);
7417 bool_short_type_node = build_distinct_type_copy (unsigned_intHI_type_node);
7418 bool_int_type_node = build_distinct_type_copy (unsigned_intSI_type_node);
7419 pixel_type_node = build_distinct_type_copy (unsigned_intHI_type_node);
8bb418a3 7420
58646b77
PB		 7421 long_integer_type_internal_node = long_integer_type_node;
7422 long_unsigned_type_internal_node = long_unsigned_type_node;
7423 intQI_type_internal_node = intQI_type_node;
7424 uintQI_type_internal_node = unsigned_intQI_type_node;
7425 intHI_type_internal_node = intHI_type_node;
7426 uintHI_type_internal_node = unsigned_intHI_type_node;
7427 intSI_type_internal_node = intSI_type_node;
7428 uintSI_type_internal_node = unsigned_intSI_type_node;
7429 float_type_internal_node = float_type_node;
7430 void_type_internal_node = void_type_node;
7431
8bb418a3
ZL		 7432 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7433 get_identifier ("__bool char"),
7434 bool_char_type_node));
7435 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7436 get_identifier ("__bool short"),
7437 bool_short_type_node));
7438 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7439 get_identifier ("__bool int"),
7440 bool_int_type_node));
7441 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7442 get_identifier ("__pixel"),
7443 pixel_type_node));
7444
4a5eab38
PB		 7445 bool_V16QI_type_node = build_vector_type (bool_char_type_node, 16);
7446 bool_V8HI_type_node = build_vector_type (bool_short_type_node, 8);
7447 bool_V4SI_type_node = build_vector_type (bool_int_type_node, 4);
7448 pixel_V8HI_type_node = build_vector_type (pixel_type_node, 8);
8bb418a3
ZL		 7449
7450 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7451 get_identifier ("__vector unsigned char"),
7452 unsigned_V16QI_type_node));
7453 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7454 get_identifier ("__vector signed char"),
7455 V16QI_type_node));
7456 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7457 get_identifier ("__vector __bool char"),
7458 bool_V16QI_type_node));
7459
7460 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7461 get_identifier ("__vector unsigned short"),
7462 unsigned_V8HI_type_node));
7463 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7464 get_identifier ("__vector signed short"),
7465 V8HI_type_node));
7466 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7467 get_identifier ("__vector __bool short"),
7468 bool_V8HI_type_node));
7469
7470 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7471 get_identifier ("__vector unsigned int"),
7472 unsigned_V4SI_type_node));
7473 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7474 get_identifier ("__vector signed int"),
7475 V4SI_type_node));
7476 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7477 get_identifier ("__vector __bool int"),
7478 bool_V4SI_type_node));
7479
7480 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7481 get_identifier ("__vector float"),
7482 V4SF_type_node));
7483 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7484 get_identifier ("__vector __pixel"),
7485 pixel_V8HI_type_node));
7486
a3170dc6 7487 if (TARGET_SPE)
3fdaa45a 7488 spe_init_builtins ();
0ac081f6
AH		 7489 if (TARGET_ALTIVEC)
7490 altivec_init_builtins ();
0559cc77
DE		 7491 if (TARGET_ALTIVEC || TARGET_SPE)
7492 rs6000_common_init_builtins ();
0ac081f6
AH		 7493}
7494
a3170dc6
AH		 7495/* Search through a set of builtins and enable the mask bits.
7496 DESC is an array of builtins.
b6d08ca1 7497 SIZE is the total number of builtins.
a3170dc6
AH		 7498 START is the builtin enum at which to start.
7499 END is the builtin enum at which to end. */
0ac081f6 7500static void
a2369ed3 7501enable_mask_for_builtins (struct builtin_description *desc, int size,
f676971a 7502 enum rs6000_builtins start,
a2369ed3 7503 enum rs6000_builtins end)
a3170dc6
AH		 7504{
7505 int i;
7506
7507 for (i = 0; i < size; ++i)
7508 if (desc[i].code == start)
7509 break;
7510
7511 if (i == size)
7512 return;
7513
7514 for (; i < size; ++i)
7515 {
7516 /* Flip all the bits on. */
7517 desc[i].mask = target_flags;
7518 if (desc[i].code == end)
7519 break;
7520 }
7521}
7522
7523static void
863d938c 7524spe_init_builtins (void)
0ac081f6 7525{
a3170dc6
AH		 7526 tree endlink = void_list_node;
7527 tree puint_type_node = build_pointer_type (unsigned_type_node);
7528 tree pushort_type_node = build_pointer_type (short_unsigned_type_node);
ae4b4a02 7529 struct builtin_description *d;
0ac081f6
AH		 7530 size_t i;
7531
a3170dc6
AH		 7532 tree v2si_ftype_4_v2si
7533 = build_function_type
3fdaa45a
AH		 7534 (opaque_V2SI_type_node,
7535 tree_cons (NULL_TREE, opaque_V2SI_type_node,
7536 tree_cons (NULL_TREE, opaque_V2SI_type_node,
7537 tree_cons (NULL_TREE, opaque_V2SI_type_node,
7538 tree_cons (NULL_TREE, opaque_V2SI_type_node,
a3170dc6
AH		 7539 endlink)))));
7540
7541 tree v2sf_ftype_4_v2sf
7542 = build_function_type
3fdaa45a
AH		 7543 (opaque_V2SF_type_node,
7544 tree_cons (NULL_TREE, opaque_V2SF_type_node,
7545 tree_cons (NULL_TREE, opaque_V2SF_type_node,
7546 tree_cons (NULL_TREE, opaque_V2SF_type_node,
7547 tree_cons (NULL_TREE, opaque_V2SF_type_node,
a3170dc6
AH		 7548 endlink)))));
7549
7550 tree int_ftype_int_v2si_v2si
7551 = build_function_type
7552 (integer_type_node,
7553 tree_cons (NULL_TREE, integer_type_node,
3fdaa45a
AH		 7554 tree_cons (NULL_TREE, opaque_V2SI_type_node,
7555 tree_cons (NULL_TREE, opaque_V2SI_type_node,
a3170dc6
AH		 7556 endlink))));
7557
7558 tree int_ftype_int_v2sf_v2sf
7559 = build_function_type
7560 (integer_type_node,
7561 tree_cons (NULL_TREE, integer_type_node,
3fdaa45a
AH		 7562 tree_cons (NULL_TREE, opaque_V2SF_type_node,
7563 tree_cons (NULL_TREE, opaque_V2SF_type_node,
a3170dc6
AH		 7564 endlink))));
7565
7566 tree void_ftype_v2si_puint_int
7567 = build_function_type (void_type_node,
3fdaa45a 7568 tree_cons (NULL_TREE, opaque_V2SI_type_node,
a3170dc6
AH		 7569 tree_cons (NULL_TREE, puint_type_node,
7570 tree_cons (NULL_TREE,
7571 integer_type_node,
7572 endlink))));
7573
7574 tree void_ftype_v2si_puint_char
7575 = build_function_type (void_type_node,
3fdaa45a 7576 tree_cons (NULL_TREE, opaque_V2SI_type_node,
a3170dc6
AH		 7577 tree_cons (NULL_TREE, puint_type_node,
7578 tree_cons (NULL_TREE,
7579 char_type_node,
7580 endlink))));
7581
7582 tree void_ftype_v2si_pv2si_int
7583 = build_function_type (void_type_node,
3fdaa45a 7584 tree_cons (NULL_TREE, opaque_V2SI_type_node,
6035d635 7585 tree_cons (NULL_TREE, opaque_p_V2SI_type_node,
a3170dc6
AH		 7586 tree_cons (NULL_TREE,
7587 integer_type_node,
7588 endlink))));
7589
7590 tree void_ftype_v2si_pv2si_char
7591 = build_function_type (void_type_node,
3fdaa45a 7592 tree_cons (NULL_TREE, opaque_V2SI_type_node,
6035d635 7593 tree_cons (NULL_TREE, opaque_p_V2SI_type_node,
a3170dc6
AH		 7594 tree_cons (NULL_TREE,
7595 char_type_node,
7596 endlink))));
7597
7598 tree void_ftype_int
7599 = build_function_type (void_type_node,
7600 tree_cons (NULL_TREE, integer_type_node, endlink));
7601
7602 tree int_ftype_void
36e8d515 7603 = build_function_type (integer_type_node, endlink);
a3170dc6
AH		 7604
7605 tree v2si_ftype_pv2si_int
3fdaa45a 7606 = build_function_type (opaque_V2SI_type_node,
6035d635 7607 tree_cons (NULL_TREE, opaque_p_V2SI_type_node,
a3170dc6
AH		 7608 tree_cons (NULL_TREE, integer_type_node,
7609 endlink)));
7610
7611 tree v2si_ftype_puint_int
3fdaa45a 7612 = build_function_type (opaque_V2SI_type_node,
a3170dc6
AH		 7613 tree_cons (NULL_TREE, puint_type_node,
7614 tree_cons (NULL_TREE, integer_type_node,
7615 endlink)));
7616
7617 tree v2si_ftype_pushort_int
3fdaa45a 7618 = build_function_type (opaque_V2SI_type_node,
a3170dc6
AH		 7619 tree_cons (NULL_TREE, pushort_type_node,
7620 tree_cons (NULL_TREE, integer_type_node,
7621 endlink)));
7622
00332c9f
AH		 7623 tree v2si_ftype_signed_char
7624 = build_function_type (opaque_V2SI_type_node,
7625 tree_cons (NULL_TREE, signed_char_type_node,
7626 endlink));
7627
a3170dc6
AH		 7628 /* The initialization of the simple binary and unary builtins is
7629 done in rs6000_common_init_builtins, but we have to enable the
7630 mask bits here manually because we have run out of `target_flags'
7631 bits. We really need to redesign this mask business. */
7632
7633 enable_mask_for_builtins ((struct builtin_description *) bdesc_2arg,
7634 ARRAY_SIZE (bdesc_2arg),
7635 SPE_BUILTIN_EVADDW,
7636 SPE_BUILTIN_EVXOR);
7637 enable_mask_for_builtins ((struct builtin_description *) bdesc_1arg,
7638 ARRAY_SIZE (bdesc_1arg),
7639 SPE_BUILTIN_EVABS,
7640 SPE_BUILTIN_EVSUBFUSIAAW);
7641 enable_mask_for_builtins ((struct builtin_description *) bdesc_spe_predicates,
7642 ARRAY_SIZE (bdesc_spe_predicates),
7643 SPE_BUILTIN_EVCMPEQ,
7644 SPE_BUILTIN_EVFSTSTLT);
7645 enable_mask_for_builtins ((struct builtin_description *) bdesc_spe_evsel,
7646 ARRAY_SIZE (bdesc_spe_evsel),
7647 SPE_BUILTIN_EVSEL_CMPGTS,
7648 SPE_BUILTIN_EVSEL_FSTSTEQ);
7649
36252949
AH		 7650 (*lang_hooks.decls.pushdecl)
7651 (build_decl (TYPE_DECL, get_identifier ("__ev64_opaque__"),
7652 opaque_V2SI_type_node));
7653
a3170dc6 7654 /* Initialize irregular SPE builtins. */
f676971a 7655
a3170dc6
AH		 7656 def_builtin (target_flags, "__builtin_spe_mtspefscr", void_ftype_int, SPE_BUILTIN_MTSPEFSCR);
7657 def_builtin (target_flags, "__builtin_spe_mfspefscr", int_ftype_void, SPE_BUILTIN_MFSPEFSCR);
7658 def_builtin (target_flags, "__builtin_spe_evstddx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDDX);
7659 def_builtin (target_flags, "__builtin_spe_evstdhx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDHX);
7660 def_builtin (target_flags, "__builtin_spe_evstdwx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDWX);
7661 def_builtin (target_flags, "__builtin_spe_evstwhex", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWHEX);
7662 def_builtin (target_flags, "__builtin_spe_evstwhox", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWHOX);
7663 def_builtin (target_flags, "__builtin_spe_evstwwex", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWWEX);
7664 def_builtin (target_flags, "__builtin_spe_evstwwox", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWWOX);
7665 def_builtin (target_flags, "__builtin_spe_evstdd", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDD);
7666 def_builtin (target_flags, "__builtin_spe_evstdh", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDH);
7667 def_builtin (target_flags, "__builtin_spe_evstdw", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDW);
7668 def_builtin (target_flags, "__builtin_spe_evstwhe", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWHE);
7669 def_builtin (target_flags, "__builtin_spe_evstwho", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWHO);
7670 def_builtin (target_flags, "__builtin_spe_evstwwe", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWWE);
7671 def_builtin (target_flags, "__builtin_spe_evstwwo", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWWO);
00332c9f
AH		 7672 def_builtin (target_flags, "__builtin_spe_evsplatfi", v2si_ftype_signed_char, SPE_BUILTIN_EVSPLATFI);
7673 def_builtin (target_flags, "__builtin_spe_evsplati", v2si_ftype_signed_char, SPE_BUILTIN_EVSPLATI);
a3170dc6
AH		 7674
7675 /* Loads. */
7676 def_builtin (target_flags, "__builtin_spe_evlddx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDDX);
7677 def_builtin (target_flags, "__builtin_spe_evldwx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDWX);
7678 def_builtin (target_flags, "__builtin_spe_evldhx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDHX);
7679 def_builtin (target_flags, "__builtin_spe_evlwhex", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHEX);
7680 def_builtin (target_flags, "__builtin_spe_evlwhoux", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOUX);
7681 def_builtin (target_flags, "__builtin_spe_evlwhosx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOSX);
7682 def_builtin (target_flags, "__builtin_spe_evlwwsplatx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWWSPLATX);
7683 def_builtin (target_flags, "__builtin_spe_evlwhsplatx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHSPLATX);
7684 def_builtin (target_flags, "__builtin_spe_evlhhesplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHESPLATX);
7685 def_builtin (target_flags, "__builtin_spe_evlhhousplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOUSPLATX);
7686 def_builtin (target_flags, "__builtin_spe_evlhhossplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOSSPLATX);
7687 def_builtin (target_flags, "__builtin_spe_evldd", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDD);
7688 def_builtin (target_flags, "__builtin_spe_evldw", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDW);
7689 def_builtin (target_flags, "__builtin_spe_evldh", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDH);
7690 def_builtin (target_flags, "__builtin_spe_evlhhesplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHESPLAT);
7691 def_builtin (target_flags, "__builtin_spe_evlhhossplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOSSPLAT);
7692 def_builtin (target_flags, "__builtin_spe_evlhhousplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOUSPLAT);
7693 def_builtin (target_flags, "__builtin_spe_evlwhe", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHE);
7694 def_builtin (target_flags, "__builtin_spe_evlwhos", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOS);
7695 def_builtin (target_flags, "__builtin_spe_evlwhou", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOU);
7696 def_builtin (target_flags, "__builtin_spe_evlwhsplat", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHSPLAT);
7697 def_builtin (target_flags, "__builtin_spe_evlwwsplat", v2si_ftype_puint_int, SPE_BUILTIN_EVLWWSPLAT);
7698
7699 /* Predicates. */
7700 d = (struct builtin_description *) bdesc_spe_predicates;
7701 for (i = 0; i < ARRAY_SIZE (bdesc_spe_predicates); ++i, d++)
7702 {
7703 tree type;
7704
7705 switch (insn_data[d->icode].operand[1].mode)
7706 {
7707 case V2SImode:
7708 type = int_ftype_int_v2si_v2si;
7709 break;
7710 case V2SFmode:
7711 type = int_ftype_int_v2sf_v2sf;
7712 break;
7713 default:
37409796 7714 gcc_unreachable ();
a3170dc6
AH		 7715 }
7716
7717 def_builtin (d->mask, d->name, type, d->code);
7718 }
7719
7720 /* Evsel predicates. */
7721 d = (struct builtin_description *) bdesc_spe_evsel;
7722 for (i = 0; i < ARRAY_SIZE (bdesc_spe_evsel); ++i, d++)
7723 {
7724 tree type;
7725
7726 switch (insn_data[d->icode].operand[1].mode)
7727 {
7728 case V2SImode:
7729 type = v2si_ftype_4_v2si;
7730 break;
7731 case V2SFmode:
7732 type = v2sf_ftype_4_v2sf;
7733 break;
7734 default:
37409796 7735 gcc_unreachable ();
a3170dc6
AH		 7736 }
7737
7738 def_builtin (d->mask, d->name, type, d->code);
7739 }
7740}
7741
7742static void
863d938c 7743altivec_init_builtins (void)
a3170dc6
AH		 7744{
7745 struct builtin_description *d;
7746 struct builtin_description_predicates *dp;
7747 size_t i;
7748 tree pfloat_type_node = build_pointer_type (float_type_node);
7749 tree pint_type_node = build_pointer_type (integer_type_node);
7750 tree pshort_type_node = build_pointer_type (short_integer_type_node);
7751 tree pchar_type_node = build_pointer_type (char_type_node);
7752
7753 tree pvoid_type_node = build_pointer_type (void_type_node);
7754
0dbc3651
ZW		 7755 tree pcfloat_type_node = build_pointer_type (build_qualified_type (float_type_node, TYPE_QUAL_CONST));
7756 tree pcint_type_node = build_pointer_type (build_qualified_type (integer_type_node, TYPE_QUAL_CONST));
7757 tree pcshort_type_node = build_pointer_type (build_qualified_type (short_integer_type_node, TYPE_QUAL_CONST));
7758 tree pcchar_type_node = build_pointer_type (build_qualified_type (char_type_node, TYPE_QUAL_CONST));
7759
7760 tree pcvoid_type_node = build_pointer_type (build_qualified_type (void_type_node, TYPE_QUAL_CONST));
7761
58646b77
PB		 7762 tree int_ftype_opaque
7763 = build_function_type_list (integer_type_node,
7764 opaque_V4SI_type_node, NULL_TREE);
7765
7766 tree opaque_ftype_opaque_int
7767 = build_function_type_list (opaque_V4SI_type_node,
7768 opaque_V4SI_type_node, integer_type_node, NULL_TREE);
7769 tree opaque_ftype_opaque_opaque_int
7770 = build_function_type_list (opaque_V4SI_type_node,
7771 opaque_V4SI_type_node, opaque_V4SI_type_node,
7772 integer_type_node, NULL_TREE);
7773 tree int_ftype_int_opaque_opaque
7774 = build_function_type_list (integer_type_node,
7775 integer_type_node, opaque_V4SI_type_node,
7776 opaque_V4SI_type_node, NULL_TREE);
a3170dc6
AH		 7777 tree int_ftype_int_v4si_v4si
7778 = build_function_type_list (integer_type_node,
7779 integer_type_node, V4SI_type_node,
7780 V4SI_type_node, NULL_TREE);
0dbc3651
ZW		 7781 tree v4sf_ftype_pcfloat
7782 = build_function_type_list (V4SF_type_node, pcfloat_type_node, NULL_TREE);
a3170dc6 7783 tree void_ftype_pfloat_v4sf
b4de2f7d 7784 = build_function_type_list (void_type_node,
a3170dc6 7785 pfloat_type_node, V4SF_type_node, NULL_TREE);
0dbc3651
ZW		 7786 tree v4si_ftype_pcint
7787 = build_function_type_list (V4SI_type_node, pcint_type_node, NULL_TREE);
7788 tree void_ftype_pint_v4si
b4de2f7d
AH		 7789 = build_function_type_list (void_type_node,
7790 pint_type_node, V4SI_type_node, NULL_TREE);
0dbc3651
ZW		 7791 tree v8hi_ftype_pcshort
7792 = build_function_type_list (V8HI_type_node, pcshort_type_node, NULL_TREE);
f18c054f 7793 tree void_ftype_pshort_v8hi
b4de2f7d
AH		 7794 = build_function_type_list (void_type_node,
7795 pshort_type_node, V8HI_type_node, NULL_TREE);
0dbc3651
ZW		 7796 tree v16qi_ftype_pcchar
7797 = build_function_type_list (V16QI_type_node, pcchar_type_node, NULL_TREE);
f18c054f 7798 tree void_ftype_pchar_v16qi
b4de2f7d
AH		 7799 = build_function_type_list (void_type_node,
7800 pchar_type_node, V16QI_type_node, NULL_TREE);
95385cbb 7801 tree void_ftype_v4si
b4de2f7d 7802 = build_function_type_list (void_type_node, V4SI_type_node, NULL_TREE);
a3170dc6
AH		 7803 tree v8hi_ftype_void
7804 = build_function_type (V8HI_type_node, void_list_node);
7805 tree void_ftype_void
7806 = build_function_type (void_type_node, void_list_node);
e34b6648
JJ		 7807 tree void_ftype_int
7808 = build_function_type_list (void_type_node, integer_type_node, NULL_TREE);
0dbc3651 7809
58646b77
PB		 7810 tree opaque_ftype_long_pcvoid
7811 = build_function_type_list (opaque_V4SI_type_node,
7812 long_integer_type_node, pcvoid_type_node, NULL_TREE);
b4a62fa0 7813 tree v16qi_ftype_long_pcvoid
a3170dc6 7814 = build_function_type_list (V16QI_type_node,
b4a62fa0
SB		 7815 long_integer_type_node, pcvoid_type_node, NULL_TREE);
7816 tree v8hi_ftype_long_pcvoid
a3170dc6 7817 = build_function_type_list (V8HI_type_node,
b4a62fa0
SB		 7818 long_integer_type_node, pcvoid_type_node, NULL_TREE);
7819 tree v4si_ftype_long_pcvoid
a3170dc6 7820 = build_function_type_list (V4SI_type_node,
b4a62fa0 7821 long_integer_type_node, pcvoid_type_node, NULL_TREE);
0dbc3651 7822
58646b77
PB		 7823 tree void_ftype_opaque_long_pvoid
7824 = build_function_type_list (void_type_node,
7825 opaque_V4SI_type_node, long_integer_type_node,
7826 pvoid_type_node, NULL_TREE);
b4a62fa0 7827 tree void_ftype_v4si_long_pvoid
b4de2f7d 7828 = build_function_type_list (void_type_node,
b4a62fa0 7829 V4SI_type_node, long_integer_type_node,
b4de2f7d 7830 pvoid_type_node, NULL_TREE);
b4a62fa0 7831 tree void_ftype_v16qi_long_pvoid
b4de2f7d 7832 = build_function_type_list (void_type_node,
b4a62fa0 7833 V16QI_type_node, long_integer_type_node,
b4de2f7d 7834 pvoid_type_node, NULL_TREE);
b4a62fa0 7835 tree void_ftype_v8hi_long_pvoid
b4de2f7d 7836 = build_function_type_list (void_type_node,
b4a62fa0 7837 V8HI_type_node, long_integer_type_node,
b4de2f7d 7838 pvoid_type_node, NULL_TREE);
a3170dc6
AH		 7839 tree int_ftype_int_v8hi_v8hi
7840 = build_function_type_list (integer_type_node,
7841 integer_type_node, V8HI_type_node,
7842 V8HI_type_node, NULL_TREE);
7843 tree int_ftype_int_v16qi_v16qi
7844 = build_function_type_list (integer_type_node,
7845 integer_type_node, V16QI_type_node,
7846 V16QI_type_node, NULL_TREE);
7847 tree int_ftype_int_v4sf_v4sf
7848 = build_function_type_list (integer_type_node,
7849 integer_type_node, V4SF_type_node,
7850 V4SF_type_node, NULL_TREE);
7851 tree v4si_ftype_v4si
7852 = build_function_type_list (V4SI_type_node, V4SI_type_node, NULL_TREE);
7853 tree v8hi_ftype_v8hi
7854 = build_function_type_list (V8HI_type_node, V8HI_type_node, NULL_TREE);
7855 tree v16qi_ftype_v16qi
7856 = build_function_type_list (V16QI_type_node, V16QI_type_node, NULL_TREE);
7857 tree v4sf_ftype_v4sf
7858 = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE);
8bb418a3 7859 tree void_ftype_pcvoid_int_int
a3170dc6 7860 = build_function_type_list (void_type_node,
0dbc3651 7861 pcvoid_type_node, integer_type_node,
8bb418a3 7862 integer_type_node, NULL_TREE);
8bb418a3 7863
0dbc3651
ZW		 7864 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_4sf", v4sf_ftype_pcfloat,
7865 ALTIVEC_BUILTIN_LD_INTERNAL_4sf);
7866 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_4sf", void_ftype_pfloat_v4sf,
7867 ALTIVEC_BUILTIN_ST_INTERNAL_4sf);
7868 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_4si", v4si_ftype_pcint,
7869 ALTIVEC_BUILTIN_LD_INTERNAL_4si);
7870 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_4si", void_ftype_pint_v4si,
7871 ALTIVEC_BUILTIN_ST_INTERNAL_4si);
7872 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_8hi", v8hi_ftype_pcshort,
7873 ALTIVEC_BUILTIN_LD_INTERNAL_8hi);
7874 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_8hi", void_ftype_pshort_v8hi,
7875 ALTIVEC_BUILTIN_ST_INTERNAL_8hi);
7876 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_16qi", v16qi_ftype_pcchar,
7877 ALTIVEC_BUILTIN_LD_INTERNAL_16qi);
7878 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_16qi", void_ftype_pchar_v16qi,
7879 ALTIVEC_BUILTIN_ST_INTERNAL_16qi);
a3170dc6
AH		 7880 def_builtin (MASK_ALTIVEC, "__builtin_altivec_mtvscr", void_ftype_v4si, ALTIVEC_BUILTIN_MTVSCR);
7881 def_builtin (MASK_ALTIVEC, "__builtin_altivec_mfvscr", v8hi_ftype_void, ALTIVEC_BUILTIN_MFVSCR);
7882 def_builtin (MASK_ALTIVEC, "__builtin_altivec_dssall", void_ftype_void, ALTIVEC_BUILTIN_DSSALL);
e34b6648 7883 def_builtin (MASK_ALTIVEC, "__builtin_altivec_dss", void_ftype_int, ALTIVEC_BUILTIN_DSS);
b4a62fa0
SB		 7884 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvsl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSL);
7885 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvsr", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSR);
7886 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvebx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEBX);
7887 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvehx", v8hi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEHX);
7888 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvewx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEWX);
7889 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvxl", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVXL);
7890 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVX);
7891 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVX);
7892 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvewx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVEWX);
7893 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvxl", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVXL);
7894 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvebx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVEBX);
7895 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvehx", void_ftype_v8hi_long_pvoid, ALTIVEC_BUILTIN_STVEHX);
58646b77
PB		 7896 def_builtin (MASK_ALTIVEC, "__builtin_vec_ld", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LD);
7897 def_builtin (MASK_ALTIVEC, "__builtin_vec_lde", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LDE);
7898 def_builtin (MASK_ALTIVEC, "__builtin_vec_ldl", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LDL);
7899 def_builtin (MASK_ALTIVEC, "__builtin_vec_lvsl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVSL);
7900 def_builtin (MASK_ALTIVEC, "__builtin_vec_lvsr", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVSR);
7901 def_builtin (MASK_ALTIVEC, "__builtin_vec_lvebx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEBX);
7902 def_builtin (MASK_ALTIVEC, "__builtin_vec_lvehx", v8hi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEHX);
7903 def_builtin (MASK_ALTIVEC, "__builtin_vec_lvewx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEWX);
7904 def_builtin (MASK_ALTIVEC, "__builtin_vec_st", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_ST);
7905 def_builtin (MASK_ALTIVEC, "__builtin_vec_ste", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STE);
7906 def_builtin (MASK_ALTIVEC, "__builtin_vec_stl", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STL);
7907 def_builtin (MASK_ALTIVEC, "__builtin_vec_stvewx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEWX);
7908 def_builtin (MASK_ALTIVEC, "__builtin_vec_stvebx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEBX);
7909 def_builtin (MASK_ALTIVEC, "__builtin_vec_stvehx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEHX);
7910
7911 def_builtin (MASK_ALTIVEC, "__builtin_vec_step", int_ftype_opaque, ALTIVEC_BUILTIN_VEC_STEP);
7912
7913 def_builtin (MASK_ALTIVEC, "__builtin_vec_sld", opaque_ftype_opaque_opaque_int, ALTIVEC_BUILTIN_VEC_SLD);
7914 def_builtin (MASK_ALTIVEC, "__builtin_vec_splat", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_SPLAT);
7915 def_builtin (MASK_ALTIVEC, "__builtin_vec_vspltw", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTW);
7916 def_builtin (MASK_ALTIVEC, "__builtin_vec_vsplth", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTH);
7917 def_builtin (MASK_ALTIVEC, "__builtin_vec_vspltb", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTB);
7918 def_builtin (MASK_ALTIVEC, "__builtin_vec_ctf", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTF);
7919 def_builtin (MASK_ALTIVEC, "__builtin_vec_vcfsx", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VCFSX);
7920 def_builtin (MASK_ALTIVEC, "__builtin_vec_vcfux", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VCFUX);
7921 def_builtin (MASK_ALTIVEC, "__builtin_vec_cts", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTS);
7922 def_builtin (MASK_ALTIVEC, "__builtin_vec_ctu", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTU);
8bb418a3 7923
a3170dc6
AH		 7924 /* Add the DST variants. */
7925 d = (struct builtin_description *) bdesc_dst;
7926 for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++)
8bb418a3 7927 def_builtin (d->mask, d->name, void_ftype_pcvoid_int_int, d->code);
a3170dc6
AH		 7928
7929 /* Initialize the predicates. */
7930 dp = (struct builtin_description_predicates *) bdesc_altivec_preds;
7931 for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, dp++)
7932 {
7933 enum machine_mode mode1;
7934 tree type;
58646b77
PB		 7935 bool is_overloaded = dp->code >= ALTIVEC_BUILTIN_OVERLOADED_FIRST
7936 && dp->code <= ALTIVEC_BUILTIN_OVERLOADED_LAST;
a3170dc6 7937
58646b77
PB		 7938 if (is_overloaded)
7939 mode1 = VOIDmode;
7940 else
7941 mode1 = insn_data[dp->icode].operand[1].mode;
a3170dc6
AH		 7942
7943 switch (mode1)
7944 {
58646b77
PB		 7945 case VOIDmode:
7946 type = int_ftype_int_opaque_opaque;
7947 break;
a3170dc6
AH		 7948 case V4SImode:
7949 type = int_ftype_int_v4si_v4si;
7950 break;
7951 case V8HImode:
7952 type = int_ftype_int_v8hi_v8hi;
7953 break;
7954 case V16QImode:
7955 type = int_ftype_int_v16qi_v16qi;
7956 break;
7957 case V4SFmode:
7958 type = int_ftype_int_v4sf_v4sf;
7959 break;
7960 default:
37409796 7961 gcc_unreachable ();
a3170dc6 7962 }
f676971a 7963
a3170dc6
AH		 7964 def_builtin (dp->mask, dp->name, type, dp->code);
7965 }
7966
7967 /* Initialize the abs* operators. */
7968 d = (struct builtin_description *) bdesc_abs;
7969 for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++)
7970 {
7971 enum machine_mode mode0;
7972 tree type;
7973
7974 mode0 = insn_data[d->icode].operand[0].mode;
7975
7976 switch (mode0)
7977 {
7978 case V4SImode:
7979 type = v4si_ftype_v4si;
7980 break;
7981 case V8HImode:
7982 type = v8hi_ftype_v8hi;
7983 break;
7984 case V16QImode:
7985 type = v16qi_ftype_v16qi;
7986 break;
7987 case V4SFmode:
7988 type = v4sf_ftype_v4sf;
7989 break;
7990 default:
37409796 7991 gcc_unreachable ();
a3170dc6 7992 }
f676971a 7993
a3170dc6
AH		 7994 def_builtin (d->mask, d->name, type, d->code);
7995 }
7ccf35ed 7996
13c62176
DN		 7997 if (TARGET_ALTIVEC)
7998 {
7999 tree decl;
8000
8001 /* Initialize target builtin that implements
8002 targetm.vectorize.builtin_mask_for_load. */
8003
8004 decl = lang_hooks.builtin_function ("__builtin_altivec_mask_for_load",
8bb46326
DN		 8005 v16qi_ftype_long_pcvoid,
8006 ALTIVEC_BUILTIN_MASK_FOR_LOAD,
8007 BUILT_IN_MD, NULL,
8008 tree_cons (get_identifier ("const"),
8009 NULL_TREE, NULL_TREE));
13c62176
DN		 8010 /* Record the decl. Will be used by rs6000_builtin_mask_for_load. */
8011 altivec_builtin_mask_for_load = decl;
13c62176 8012 }
a3170dc6
AH		 8013}
8014
8015static void
863d938c 8016rs6000_common_init_builtins (void)
a3170dc6
AH		 8017{
8018 struct builtin_description *d;
8019 size_t i;
8020
8021 tree v4sf_ftype_v4sf_v4sf_v16qi
8022 = build_function_type_list (V4SF_type_node,
8023 V4SF_type_node, V4SF_type_node,
8024 V16QI_type_node, NULL_TREE);
8025 tree v4si_ftype_v4si_v4si_v16qi
8026 = build_function_type_list (V4SI_type_node,
8027 V4SI_type_node, V4SI_type_node,
8028 V16QI_type_node, NULL_TREE);
8029 tree v8hi_ftype_v8hi_v8hi_v16qi
8030 = build_function_type_list (V8HI_type_node,
8031 V8HI_type_node, V8HI_type_node,
8032 V16QI_type_node, NULL_TREE);
8033 tree v16qi_ftype_v16qi_v16qi_v16qi
8034 = build_function_type_list (V16QI_type_node,
8035 V16QI_type_node, V16QI_type_node,
8036 V16QI_type_node, NULL_TREE);
b9e4e5d1
ZL		 8037 tree v4si_ftype_int
8038 = build_function_type_list (V4SI_type_node, integer_type_node, NULL_TREE);
8039 tree v8hi_ftype_int
8040 = build_function_type_list (V8HI_type_node, integer_type_node, NULL_TREE);
8041 tree v16qi_ftype_int
8042 = build_function_type_list (V16QI_type_node, integer_type_node, NULL_TREE);
a3170dc6
AH		 8043 tree v8hi_ftype_v16qi
8044 = build_function_type_list (V8HI_type_node, V16QI_type_node, NULL_TREE);
8045 tree v4sf_ftype_v4sf
8046 = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE);
8047
8048 tree v2si_ftype_v2si_v2si
2abe3e28
AH		 8049 = build_function_type_list (opaque_V2SI_type_node,
8050 opaque_V2SI_type_node,
8051 opaque_V2SI_type_node, NULL_TREE);
a3170dc6
AH		 8052
8053 tree v2sf_ftype_v2sf_v2sf
2abe3e28
AH		 8054 = build_function_type_list (opaque_V2SF_type_node,
8055 opaque_V2SF_type_node,
8056 opaque_V2SF_type_node, NULL_TREE);
a3170dc6
AH		 8057
8058 tree v2si_ftype_int_int
2abe3e28 8059 = build_function_type_list (opaque_V2SI_type_node,
a3170dc6
AH		 8060 integer_type_node, integer_type_node,
8061 NULL_TREE);
8062
58646b77
PB		 8063 tree opaque_ftype_opaque
8064 = build_function_type_list (opaque_V4SI_type_node,
8065 opaque_V4SI_type_node, NULL_TREE);
8066
a3170dc6 8067 tree v2si_ftype_v2si
2abe3e28
AH		 8068 = build_function_type_list (opaque_V2SI_type_node,
8069 opaque_V2SI_type_node, NULL_TREE);
a3170dc6
AH		 8070
8071 tree v2sf_ftype_v2sf
2abe3e28
AH		 8072 = build_function_type_list (opaque_V2SF_type_node,
8073 opaque_V2SF_type_node, NULL_TREE);
f676971a 8074
a3170dc6 8075 tree v2sf_ftype_v2si
2abe3e28
AH		 8076 = build_function_type_list (opaque_V2SF_type_node,
8077 opaque_V2SI_type_node, NULL_TREE);
a3170dc6
AH		 8078
8079 tree v2si_ftype_v2sf
2abe3e28
AH		 8080 = build_function_type_list (opaque_V2SI_type_node,
8081 opaque_V2SF_type_node, NULL_TREE);
a3170dc6
AH		 8082
8083 tree v2si_ftype_v2si_char
2abe3e28
AH		 8084 = build_function_type_list (opaque_V2SI_type_node,
8085 opaque_V2SI_type_node,
8086 char_type_node, NULL_TREE);
a3170dc6
AH		 8087
8088 tree v2si_ftype_int_char
2abe3e28 8089 = build_function_type_list (opaque_V2SI_type_node,
a3170dc6
AH		 8090 integer_type_node, char_type_node, NULL_TREE);
8091
8092 tree v2si_ftype_char
2abe3e28
AH		 8093 = build_function_type_list (opaque_V2SI_type_node,
8094 char_type_node, NULL_TREE);
a3170dc6
AH		 8095
8096 tree int_ftype_int_int
8097 = build_function_type_list (integer_type_node,
8098 integer_type_node, integer_type_node,
8099 NULL_TREE);
95385cbb 8100
58646b77
PB		 8101 tree opaque_ftype_opaque_opaque
8102 = build_function_type_list (opaque_V4SI_type_node,
8103 opaque_V4SI_type_node, opaque_V4SI_type_node, NULL_TREE);
0ac081f6 8104 tree v4si_ftype_v4si_v4si
b4de2f7d
AH		 8105 = build_function_type_list (V4SI_type_node,
8106 V4SI_type_node, V4SI_type_node, NULL_TREE);
b9e4e5d1 8107 tree v4sf_ftype_v4si_int
b4de2f7d 8108 = build_function_type_list (V4SF_type_node,
b9e4e5d1
ZL		 8109 V4SI_type_node, integer_type_node, NULL_TREE);
8110 tree v4si_ftype_v4sf_int
b4de2f7d 8111 = build_function_type_list (V4SI_type_node,
b9e4e5d1
ZL		 8112 V4SF_type_node, integer_type_node, NULL_TREE);
8113 tree v4si_ftype_v4si_int
b4de2f7d 8114 = build_function_type_list (V4SI_type_node,
b9e4e5d1
ZL		 8115 V4SI_type_node, integer_type_node, NULL_TREE);
8116 tree v8hi_ftype_v8hi_int
b4de2f7d 8117 = build_function_type_list (V8HI_type_node,
b9e4e5d1
ZL		 8118 V8HI_type_node, integer_type_node, NULL_TREE);
8119 tree v16qi_ftype_v16qi_int
b4de2f7d 8120 = build_function_type_list (V16QI_type_node,
b9e4e5d1
ZL		 8121 V16QI_type_node, integer_type_node, NULL_TREE);
8122 tree v16qi_ftype_v16qi_v16qi_int
b4de2f7d
AH		 8123 = build_function_type_list (V16QI_type_node,
8124 V16QI_type_node, V16QI_type_node,
b9e4e5d1
ZL		 8125 integer_type_node, NULL_TREE);
8126 tree v8hi_ftype_v8hi_v8hi_int
b4de2f7d
AH		 8127 = build_function_type_list (V8HI_type_node,
8128 V8HI_type_node, V8HI_type_node,
b9e4e5d1
ZL		 8129 integer_type_node, NULL_TREE);
8130 tree v4si_ftype_v4si_v4si_int
b4de2f7d
AH		 8131 = build_function_type_list (V4SI_type_node,
8132 V4SI_type_node, V4SI_type_node,
b9e4e5d1
ZL		 8133 integer_type_node, NULL_TREE);
8134 tree v4sf_ftype_v4sf_v4sf_int
b4de2f7d
AH		 8135 = build_function_type_list (V4SF_type_node,
8136 V4SF_type_node, V4SF_type_node,
b9e4e5d1 8137 integer_type_node, NULL_TREE);
0ac081f6 8138 tree v4sf_ftype_v4sf_v4sf
b4de2f7d
AH		 8139 = build_function_type_list (V4SF_type_node,
8140 V4SF_type_node, V4SF_type_node, NULL_TREE);
58646b77
PB		 8141 tree opaque_ftype_opaque_opaque_opaque
8142 = build_function_type_list (opaque_V4SI_type_node,
8143 opaque_V4SI_type_node, opaque_V4SI_type_node,
8144 opaque_V4SI_type_node, NULL_TREE);
617e0e1d 8145 tree v4sf_ftype_v4sf_v4sf_v4si
b4de2f7d
AH		 8146 = build_function_type_list (V4SF_type_node,
8147 V4SF_type_node, V4SF_type_node,
8148 V4SI_type_node, NULL_TREE);
2212663f 8149 tree v4sf_ftype_v4sf_v4sf_v4sf
b4de2f7d
AH		 8150 = build_function_type_list (V4SF_type_node,
8151 V4SF_type_node, V4SF_type_node,
8152 V4SF_type_node, NULL_TREE);
f676971a 8153 tree v4si_ftype_v4si_v4si_v4si
b4de2f7d
AH		 8154 = build_function_type_list (V4SI_type_node,
8155 V4SI_type_node, V4SI_type_node,
8156 V4SI_type_node, NULL_TREE);
0ac081f6 8157 tree v8hi_ftype_v8hi_v8hi
b4de2f7d
AH		 8158 = build_function_type_list (V8HI_type_node,
8159 V8HI_type_node, V8HI_type_node, NULL_TREE);
2212663f 8160 tree v8hi_ftype_v8hi_v8hi_v8hi
b4de2f7d
AH		 8161 = build_function_type_list (V8HI_type_node,
8162 V8HI_type_node, V8HI_type_node,
8163 V8HI_type_node, NULL_TREE);
c4ad648e 8164 tree v4si_ftype_v8hi_v8hi_v4si
b4de2f7d
AH		 8165 = build_function_type_list (V4SI_type_node,
8166 V8HI_type_node, V8HI_type_node,
8167 V4SI_type_node, NULL_TREE);
c4ad648e 8168 tree v4si_ftype_v16qi_v16qi_v4si
b4de2f7d
AH		 8169 = build_function_type_list (V4SI_type_node,
8170 V16QI_type_node, V16QI_type_node,
8171 V4SI_type_node, NULL_TREE);
0ac081f6 8172 tree v16qi_ftype_v16qi_v16qi
b4de2f7d
AH		 8173 = build_function_type_list (V16QI_type_node,
8174 V16QI_type_node, V16QI_type_node, NULL_TREE);
0ac081f6 8175 tree v4si_ftype_v4sf_v4sf
b4de2f7d
AH		 8176 = build_function_type_list (V4SI_type_node,
8177 V4SF_type_node, V4SF_type_node, NULL_TREE);
0ac081f6 8178 tree v8hi_ftype_v16qi_v16qi
b4de2f7d
AH		 8179 = build_function_type_list (V8HI_type_node,
8180 V16QI_type_node, V16QI_type_node, NULL_TREE);
0ac081f6 8181 tree v4si_ftype_v8hi_v8hi
b4de2f7d
AH		 8182 = build_function_type_list (V4SI_type_node,
8183 V8HI_type_node, V8HI_type_node, NULL_TREE);
0ac081f6 8184 tree v8hi_ftype_v4si_v4si
b4de2f7d
AH		 8185 = build_function_type_list (V8HI_type_node,
8186 V4SI_type_node, V4SI_type_node, NULL_TREE);
0ac081f6 8187 tree v16qi_ftype_v8hi_v8hi
b4de2f7d
AH		 8188 = build_function_type_list (V16QI_type_node,
8189 V8HI_type_node, V8HI_type_node, NULL_TREE);
0ac081f6 8190 tree v4si_ftype_v16qi_v4si
b4de2f7d
AH		 8191 = build_function_type_list (V4SI_type_node,
8192 V16QI_type_node, V4SI_type_node, NULL_TREE);
fa066a23 8193 tree v4si_ftype_v16qi_v16qi
b4de2f7d
AH		 8194 = build_function_type_list (V4SI_type_node,
8195 V16QI_type_node, V16QI_type_node, NULL_TREE);
0ac081f6 8196 tree v4si_ftype_v8hi_v4si
b4de2f7d
AH		 8197 = build_function_type_list (V4SI_type_node,
8198 V8HI_type_node, V4SI_type_node, NULL_TREE);
a3170dc6
AH		 8199 tree v4si_ftype_v8hi
8200 = build_function_type_list (V4SI_type_node, V8HI_type_node, NULL_TREE);
8201 tree int_ftype_v4si_v4si
8202 = build_function_type_list (integer_type_node,
8203 V4SI_type_node, V4SI_type_node, NULL_TREE);
8204 tree int_ftype_v4sf_v4sf
8205 = build_function_type_list (integer_type_node,
8206 V4SF_type_node, V4SF_type_node, NULL_TREE);
8207 tree int_ftype_v16qi_v16qi
8208 = build_function_type_list (integer_type_node,
8209 V16QI_type_node, V16QI_type_node, NULL_TREE);
0ac081f6 8210 tree int_ftype_v8hi_v8hi
b4de2f7d
AH		 8211 = build_function_type_list (integer_type_node,
8212 V8HI_type_node, V8HI_type_node, NULL_TREE);
0ac081f6 8213
6f317ef3 8214 /* Add the simple ternary operators. */
2212663f 8215 d = (struct builtin_description *) bdesc_3arg;
ca7558fc 8216 for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++)
2212663f 8217 {
2212663f
DB		 8218 enum machine_mode mode0, mode1, mode2, mode3;
8219 tree type;
58646b77
PB		 8220 bool is_overloaded = d->code >= ALTIVEC_BUILTIN_OVERLOADED_FIRST
8221 && d->code <= ALTIVEC_BUILTIN_OVERLOADED_LAST;
2212663f 8222
58646b77
PB		 8223 if (is_overloaded)
8224 {
8225 mode0 = VOIDmode;
8226 mode1 = VOIDmode;
8227 mode2 = VOIDmode;
8228 mode3 = VOIDmode;
8229 }
8230 else
8231 {
8232 if (d->name == 0 || d->icode == CODE_FOR_nothing)
8233 continue;
f676971a 8234
58646b77
PB		 8235 mode0 = insn_data[d->icode].operand[0].mode;
8236 mode1 = insn_data[d->icode].operand[1].mode;
8237 mode2 = insn_data[d->icode].operand[2].mode;
8238 mode3 = insn_data[d->icode].operand[3].mode;
8239 }
8240
2212663f
DB		 8241 /* When all four are of the same mode. */
8242 if (mode0 == mode1 && mode1 == mode2 && mode2 == mode3)
8243 {
8244 switch (mode0)
8245 {
58646b77
PB		 8246 case VOIDmode:
8247 type = opaque_ftype_opaque_opaque_opaque;
8248 break;
617e0e1d
DB		 8249 case V4SImode:
8250 type = v4si_ftype_v4si_v4si_v4si;
8251 break;
2212663f
DB		 8252 case V4SFmode:
8253 type = v4sf_ftype_v4sf_v4sf_v4sf;
8254 break;
8255 case V8HImode:
8256 type = v8hi_ftype_v8hi_v8hi_v8hi;
f676971a 8257 break;
2212663f
DB		 8258 case V16QImode:
8259 type = v16qi_ftype_v16qi_v16qi_v16qi;
f676971a 8260 break;
2212663f 8261 default:
37409796 8262 gcc_unreachable ();
2212663f
DB		 8263 }
8264 }
8265 else if (mode0 == mode1 && mode1 == mode2 && mode3 == V16QImode)
c4ad648e 8266 {
2212663f
DB		 8267 switch (mode0)
8268 {
8269 case V4SImode:
8270 type = v4si_ftype_v4si_v4si_v16qi;
8271 break;
8272 case V4SFmode:
8273 type = v4sf_ftype_v4sf_v4sf_v16qi;
8274 break;
8275 case V8HImode:
8276 type = v8hi_ftype_v8hi_v8hi_v16qi;
f676971a 8277 break;
2212663f
DB		 8278 case V16QImode:
8279 type = v16qi_ftype_v16qi_v16qi_v16qi;
f676971a 8280 break;
2212663f 8281 default:
37409796 8282 gcc_unreachable ();
2212663f
DB		 8283 }
8284 }
f676971a 8285 else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V16QImode
2212663f 8286 && mode3 == V4SImode)
24408032 8287 type = v4si_ftype_v16qi_v16qi_v4si;
f676971a 8288 else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V8HImode
2212663f 8289 && mode3 == V4SImode)
24408032 8290 type = v4si_ftype_v8hi_v8hi_v4si;
f676971a 8291 else if (mode0 == V4SFmode && mode1 == V4SFmode && mode2 == V4SFmode
617e0e1d 8292 && mode3 == V4SImode)
24408032
AH		 8293 type = v4sf_ftype_v4sf_v4sf_v4si;
8294
8295 /* vchar, vchar, vchar, 4 bit literal. */
8296 else if (mode0 == V16QImode && mode1 == mode0 && mode2 == mode0
8297 && mode3 == QImode)
b9e4e5d1 8298 type = v16qi_ftype_v16qi_v16qi_int;
24408032
AH		 8299
8300 /* vshort, vshort, vshort, 4 bit literal. */
8301 else if (mode0 == V8HImode && mode1 == mode0 && mode2 == mode0
8302 && mode3 == QImode)
b9e4e5d1 8303 type = v8hi_ftype_v8hi_v8hi_int;
24408032
AH		 8304
8305 /* vint, vint, vint, 4 bit literal. */
8306 else if (mode0 == V4SImode && mode1 == mode0 && mode2 == mode0
8307 && mode3 == QImode)
b9e4e5d1 8308 type = v4si_ftype_v4si_v4si_int;
24408032
AH		 8309
8310 /* vfloat, vfloat, vfloat, 4 bit literal. */
8311 else if (mode0 == V4SFmode && mode1 == mode0 && mode2 == mode0
8312 && mode3 == QImode)
b9e4e5d1 8313 type = v4sf_ftype_v4sf_v4sf_int;
24408032 8314
2212663f 8315 else
37409796 8316 gcc_unreachable ();
2212663f
DB		 8317
8318 def_builtin (d->mask, d->name, type, d->code);
8319 }
8320
0ac081f6 8321 /* Add the simple binary operators. */
00b960c7 8322 d = (struct builtin_description *) bdesc_2arg;
ca7558fc 8323 for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
0ac081f6
AH		 8324 {
8325 enum machine_mode mode0, mode1, mode2;
8326 tree type;
58646b77
PB		 8327 bool is_overloaded = d->code >= ALTIVEC_BUILTIN_OVERLOADED_FIRST
8328 && d->code <= ALTIVEC_BUILTIN_OVERLOADED_LAST;
0ac081f6 8329
58646b77
PB		 8330 if (is_overloaded)
8331 {
8332 mode0 = VOIDmode;
8333 mode1 = VOIDmode;
8334 mode2 = VOIDmode;
8335 }
8336 else
8337 {
8338 if (d->name == 0 || d->icode == CODE_FOR_nothing)
8339 continue;
f676971a 8340
58646b77
PB		 8341 mode0 = insn_data[d->icode].operand[0].mode;
8342 mode1 = insn_data[d->icode].operand[1].mode;
8343 mode2 = insn_data[d->icode].operand[2].mode;
8344 }
0ac081f6
AH		 8345
8346 /* When all three operands are of the same mode. */
8347 if (mode0 == mode1 && mode1 == mode2)
8348 {
8349 switch (mode0)
8350 {
58646b77
PB		 8351 case VOIDmode:
8352 type = opaque_ftype_opaque_opaque;
8353 break;
0ac081f6
AH		 8354 case V4SFmode:
8355 type = v4sf_ftype_v4sf_v4sf;
8356 break;
8357 case V4SImode:
8358 type = v4si_ftype_v4si_v4si;
8359 break;
8360 case V16QImode:
8361 type = v16qi_ftype_v16qi_v16qi;
8362 break;
8363 case V8HImode:
8364 type = v8hi_ftype_v8hi_v8hi;
8365 break;
a3170dc6
AH		 8366 case V2SImode:
8367 type = v2si_ftype_v2si_v2si;
8368 break;
8369 case V2SFmode:
8370 type = v2sf_ftype_v2sf_v2sf;
8371 break;
8372 case SImode:
8373 type = int_ftype_int_int;
8374 break;
0ac081f6 8375 default:
37409796 8376 gcc_unreachable ();
0ac081f6
AH		 8377 }
8378 }
8379
8380 /* A few other combos we really don't want to do manually. */
8381
8382 /* vint, vfloat, vfloat. */
8383 else if (mode0 == V4SImode && mode1 == V4SFmode && mode2 == V4SFmode)
8384 type = v4si_ftype_v4sf_v4sf;
8385
8386 /* vshort, vchar, vchar. */
8387 else if (mode0 == V8HImode && mode1 == V16QImode && mode2 == V16QImode)
8388 type = v8hi_ftype_v16qi_v16qi;
8389
8390 /* vint, vshort, vshort. */
8391 else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V8HImode)
8392 type = v4si_ftype_v8hi_v8hi;
8393
8394 /* vshort, vint, vint. */
8395 else if (mode0 == V8HImode && mode1 == V4SImode && mode2 == V4SImode)
8396 type = v8hi_ftype_v4si_v4si;
8397
8398 /* vchar, vshort, vshort. */
8399 else if (mode0 == V16QImode && mode1 == V8HImode && mode2 == V8HImode)
8400 type = v16qi_ftype_v8hi_v8hi;
8401
8402 /* vint, vchar, vint. */
8403 else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V4SImode)
8404 type = v4si_ftype_v16qi_v4si;
8405
fa066a23
AH		 8406 /* vint, vchar, vchar. */
8407 else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V16QImode)
8408 type = v4si_ftype_v16qi_v16qi;
8409
0ac081f6
AH		 8410 /* vint, vshort, vint. */
8411 else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V4SImode)
8412 type = v4si_ftype_v8hi_v4si;
f676971a 8413
2212663f
DB		 8414 /* vint, vint, 5 bit literal. */
8415 else if (mode0 == V4SImode && mode1 == V4SImode && mode2 == QImode)
b9e4e5d1 8416 type = v4si_ftype_v4si_int;
f676971a 8417
2212663f
DB		 8418 /* vshort, vshort, 5 bit literal. */
8419 else if (mode0 == V8HImode && mode1 == V8HImode && mode2 == QImode)
b9e4e5d1 8420 type = v8hi_ftype_v8hi_int;
f676971a 8421
2212663f
DB		 8422 /* vchar, vchar, 5 bit literal. */
8423 else if (mode0 == V16QImode && mode1 == V16QImode && mode2 == QImode)
b9e4e5d1 8424 type = v16qi_ftype_v16qi_int;
0ac081f6 8425
617e0e1d
DB		 8426 /* vfloat, vint, 5 bit literal. */
8427 else if (mode0 == V4SFmode && mode1 == V4SImode && mode2 == QImode)
b9e4e5d1 8428 type = v4sf_ftype_v4si_int;
f676971a 8429
617e0e1d
DB		 8430 /* vint, vfloat, 5 bit literal. */
8431 else if (mode0 == V4SImode && mode1 == V4SFmode && mode2 == QImode)
b9e4e5d1 8432 type = v4si_ftype_v4sf_int;
617e0e1d 8433
a3170dc6
AH		 8434 else if (mode0 == V2SImode && mode1 == SImode && mode2 == SImode)
8435 type = v2si_ftype_int_int;
8436
8437 else if (mode0 == V2SImode && mode1 == V2SImode && mode2 == QImode)
8438 type = v2si_ftype_v2si_char;
8439
8440 else if (mode0 == V2SImode && mode1 == SImode && mode2 == QImode)
8441 type = v2si_ftype_int_char;
8442
37409796 8443 else
0ac081f6 8444 {
37409796
NS		 8445 /* int, x, x. */
8446 gcc_assert (mode0 == SImode);
0ac081f6
AH		 8447 switch (mode1)
8448 {
8449 case V4SImode:
8450 type = int_ftype_v4si_v4si;
8451 break;
8452 case V4SFmode:
8453 type = int_ftype_v4sf_v4sf;
8454 break;
8455 case V16QImode:
8456 type = int_ftype_v16qi_v16qi;
8457 break;
8458 case V8HImode:
8459 type = int_ftype_v8hi_v8hi;
8460 break;
8461 default:
37409796 8462 gcc_unreachable ();
0ac081f6
AH		 8463 }
8464 }
8465
2212663f
DB		 8466 def_builtin (d->mask, d->name, type, d->code);
8467 }
24408032 8468
2212663f
DB		 8469 /* Add the simple unary operators. */
8470 d = (struct builtin_description *) bdesc_1arg;
ca7558fc 8471 for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
2212663f
DB		 8472 {
8473 enum machine_mode mode0, mode1;
8474 tree type;
58646b77
PB		 8475 bool is_overloaded = d->code >= ALTIVEC_BUILTIN_OVERLOADED_FIRST
8476 && d->code <= ALTIVEC_BUILTIN_OVERLOADED_LAST;
8477
8478 if (is_overloaded)
8479 {
8480 mode0 = VOIDmode;
8481 mode1 = VOIDmode;
8482 }
8483 else
8484 {
8485 if (d->name == 0 || d->icode == CODE_FOR_nothing)
8486 continue;
8487
8488 mode0 = insn_data[d->icode].operand[0].mode;
8489 mode1 = insn_data[d->icode].operand[1].mode;
8490 }
2212663f
DB		 8491
8492 if (mode0 == V4SImode && mode1 == QImode)
c4ad648e 8493 type = v4si_ftype_int;
2212663f 8494 else if (mode0 == V8HImode && mode1 == QImode)
c4ad648e 8495 type = v8hi_ftype_int;
2212663f 8496 else if (mode0 == V16QImode && mode1 == QImode)
c4ad648e 8497 type = v16qi_ftype_int;
58646b77
PB		 8498 else if (mode0 == VOIDmode && mode1 == VOIDmode)
8499 type = opaque_ftype_opaque;
617e0e1d
DB		 8500 else if (mode0 == V4SFmode && mode1 == V4SFmode)
8501 type = v4sf_ftype_v4sf;
20e26713
AH		 8502 else if (mode0 == V8HImode && mode1 == V16QImode)
8503 type = v8hi_ftype_v16qi;
8504 else if (mode0 == V4SImode && mode1 == V8HImode)
8505 type = v4si_ftype_v8hi;
a3170dc6
AH		 8506 else if (mode0 == V2SImode && mode1 == V2SImode)
8507 type = v2si_ftype_v2si;
8508 else if (mode0 == V2SFmode && mode1 == V2SFmode)
8509 type = v2sf_ftype_v2sf;
8510 else if (mode0 == V2SFmode && mode1 == V2SImode)
8511 type = v2sf_ftype_v2si;
8512 else if (mode0 == V2SImode && mode1 == V2SFmode)
8513 type = v2si_ftype_v2sf;
8514 else if (mode0 == V2SImode && mode1 == QImode)
8515 type = v2si_ftype_char;
2212663f 8516 else
37409796 8517 gcc_unreachable ();
2212663f 8518
0ac081f6
AH		 8519 def_builtin (d->mask, d->name, type, d->code);
8520 }
8521}
8522
c15c90bb
ZW		 8523static void
8524rs6000_init_libfuncs (void)
8525{
8526 if (!TARGET_HARD_FLOAT)
8527 return;
8528
c9034561 8529 if (DEFAULT_ABI != ABI_V4)
c15c90bb 8530 {
c9034561 8531 if (TARGET_XCOFF && ! TARGET_POWER2 && ! TARGET_POWERPC)
c15c90bb 8532 {
c9034561 8533 /* AIX library routines for float->int conversion. */
85363ca0
ZW		 8534 set_conv_libfunc (sfix_optab, SImode, DFmode, "__itrunc");
8535 set_conv_libfunc (ufix_optab, SImode, DFmode, "__uitrunc");
4274207b
DE		 8536 set_conv_libfunc (sfix_optab, SImode, TFmode, "_qitrunc");
8537 set_conv_libfunc (ufix_optab, SImode, TFmode, "_quitrunc");
c15c90bb
ZW		 8538 }
8539
98c41d98
DE		 8540 /* AIX/Darwin/64-bit Linux quad floating point routines. */
8541 if (!TARGET_XL_COMPAT)
8542 {
8543 set_optab_libfunc (add_optab, TFmode, "__gcc_qadd");
8544 set_optab_libfunc (sub_optab, TFmode, "__gcc_qsub");
8545 set_optab_libfunc (smul_optab, TFmode, "__gcc_qmul");
8546 set_optab_libfunc (sdiv_optab, TFmode, "__gcc_qdiv");
8547 }
8548 else
8549 {
8550 set_optab_libfunc (add_optab, TFmode, "_xlqadd");
8551 set_optab_libfunc (sub_optab, TFmode, "_xlqsub");
8552 set_optab_libfunc (smul_optab, TFmode, "_xlqmul");
8553 set_optab_libfunc (sdiv_optab, TFmode, "_xlqdiv");
8554 }
c15c90bb 8555 }
c9034561 8556 else
c15c90bb 8557 {
c9034561 8558 /* 32-bit SVR4 quad floating point routines. */
c15c90bb
ZW		 8559
8560 set_optab_libfunc (add_optab, TFmode, "_q_add");
8561 set_optab_libfunc (sub_optab, TFmode, "_q_sub");
8562 set_optab_libfunc (neg_optab, TFmode, "_q_neg");
8563 set_optab_libfunc (smul_optab, TFmode, "_q_mul");
8564 set_optab_libfunc (sdiv_optab, TFmode, "_q_div");
8565 if (TARGET_PPC_GPOPT || TARGET_POWER2)
8566 set_optab_libfunc (sqrt_optab, TFmode, "_q_sqrt");
8567
c9034561
ZW		 8568 set_optab_libfunc (eq_optab, TFmode, "_q_feq");
8569 set_optab_libfunc (ne_optab, TFmode, "_q_fne");
8570 set_optab_libfunc (gt_optab, TFmode, "_q_fgt");
8571 set_optab_libfunc (ge_optab, TFmode, "_q_fge");
8572 set_optab_libfunc (lt_optab, TFmode, "_q_flt");
8573 set_optab_libfunc (le_optab, TFmode, "_q_fle");
8574
85363ca0
ZW		 8575 set_conv_libfunc (sext_optab, TFmode, SFmode, "_q_stoq");
8576 set_conv_libfunc (sext_optab, TFmode, DFmode, "_q_dtoq");
8577 set_conv_libfunc (trunc_optab, SFmode, TFmode, "_q_qtos");
8578 set_conv_libfunc (trunc_optab, DFmode, TFmode, "_q_qtod");
8579 set_conv_libfunc (sfix_optab, SImode, TFmode, "_q_qtoi");
8580 set_conv_libfunc (ufix_optab, SImode, TFmode, "_q_qtou");
8581 set_conv_libfunc (sfloat_optab, TFmode, SImode, "_q_itoq");
c15c90bb
ZW		 8582 }
8583}
fba73eb1
DE		 8584
8585\f
8586/* Expand a block clear operation, and return 1 if successful. Return 0
8587 if we should let the compiler generate normal code.
8588
8589 operands[0] is the destination
8590 operands[1] is the length
57e84f18 8591 operands[3] is the alignment */
fba73eb1
DE		 8592
8593int
8594expand_block_clear (rtx operands[])
8595{
8596 rtx orig_dest = operands[0];
8597 rtx bytes_rtx = operands[1];
57e84f18 8598 rtx align_rtx = operands[3];
5514620a
GK		 8599 bool constp = (GET_CODE (bytes_rtx) == CONST_INT);
8600 HOST_WIDE_INT align;
8601 HOST_WIDE_INT bytes;
fba73eb1
DE		 8602 int offset;
8603 int clear_bytes;
5514620a 8604 int clear_step;
fba73eb1
DE		 8605
8606 /* If this is not a fixed size move, just call memcpy */
8607 if (! constp)
8608 return 0;
8609
37409796
NS		 8610 /* This must be a fixed size alignment */
8611 gcc_assert (GET_CODE (align_rtx) == CONST_INT);
fba73eb1
DE		 8612 align = INTVAL (align_rtx) * BITS_PER_UNIT;
8613
8614 /* Anything to clear? */
8615 bytes = INTVAL (bytes_rtx);
8616 if (bytes <= 0)
8617 return 1;
8618
5514620a
GK		 8619 /* Use the builtin memset after a point, to avoid huge code bloat.
8620 When optimize_size, avoid any significant code bloat; calling
8621 memset is about 4 instructions, so allow for one instruction to
8622 load zero and three to do clearing. */
8623 if (TARGET_ALTIVEC && align >= 128)
8624 clear_step = 16;
8625 else if (TARGET_POWERPC64 && align >= 32)
8626 clear_step = 8;
8627 else
8628 clear_step = 4;
fba73eb1 8629
5514620a
GK		 8630 if (optimize_size && bytes > 3 * clear_step)
8631 return 0;
8632 if (! optimize_size && bytes > 8 * clear_step)
fba73eb1
DE		 8633 return 0;
8634
8635 for (offset = 0; bytes > 0; offset += clear_bytes, bytes -= clear_bytes)
8636 {
fba73eb1
DE		 8637 enum machine_mode mode = BLKmode;
8638 rtx dest;
f676971a 8639
5514620a
GK		 8640 if (bytes >= 16 && TARGET_ALTIVEC && align >= 128)
8641 {
8642 clear_bytes = 16;
8643 mode = V4SImode;
8644 }
8645 else if (bytes >= 8 && TARGET_POWERPC64
8646 /* 64-bit loads and stores require word-aligned
8647 displacements. */
8648 && (align >= 64 || (!STRICT_ALIGNMENT && align >= 32)))
fba73eb1
DE		 8649 {
8650 clear_bytes = 8;
8651 mode = DImode;
fba73eb1 8652 }
5514620a 8653 else if (bytes >= 4 && (align >= 32 || !STRICT_ALIGNMENT))
fba73eb1
DE		 8654 { /* move 4 bytes */
8655 clear_bytes = 4;
8656 mode = SImode;
fba73eb1 8657 }
5514620a 8658 else if (bytes == 2 && (align >= 16 || !STRICT_ALIGNMENT))
fba73eb1
DE		 8659 { /* move 2 bytes */
8660 clear_bytes = 2;
8661 mode = HImode;
fba73eb1
DE		 8662 }
8663 else /* move 1 byte at a time */
8664 {
8665 clear_bytes = 1;
8666 mode = QImode;
fba73eb1 8667 }
f676971a 8668
fba73eb1 8669 dest = adjust_address (orig_dest, mode, offset);
f676971a 8670
5514620a 8671 emit_move_insn (dest, CONST0_RTX (mode));
fba73eb1
DE		 8672 }
8673
8674 return 1;
8675}
8676
35aff10b 8677\f
7e69e155
MM		 8678/* Expand a block move operation, and return 1 if successful. Return 0
8679 if we should let the compiler generate normal code.
8680
8681 operands[0] is the destination
8682 operands[1] is the source
8683 operands[2] is the length
8684 operands[3] is the alignment */
8685
3933e0e1
MM		 8686#define MAX_MOVE_REG 4
8687
7e69e155 8688int
a2369ed3 8689expand_block_move (rtx operands[])
7e69e155 8690{
b6c9286a
MM		 8691 rtx orig_dest = operands[0];
8692 rtx orig_src = operands[1];
7e69e155 8693 rtx bytes_rtx = operands[2];
7e69e155 8694 rtx align_rtx = operands[3];
3933e0e1 8695 int constp = (GET_CODE (bytes_rtx) == CONST_INT);
5ee95df6 8696 int align;
3933e0e1
MM		 8697 int bytes;
8698 int offset;
7e69e155 8699 int move_bytes;
cabfd258
GK		 8700 rtx stores[MAX_MOVE_REG];
8701 int num_reg = 0;
7e69e155 8702
3933e0e1 8703 /* If this is not a fixed size move, just call memcpy */
cc0d9ba8 8704 if (! constp)
3933e0e1
MM		 8705 return 0;
8706
37409796
NS		 8707 /* This must be a fixed size alignment */
8708 gcc_assert (GET_CODE (align_rtx) == CONST_INT);
fba73eb1 8709 align = INTVAL (align_rtx) * BITS_PER_UNIT;
5ee95df6 8710
7e69e155 8711 /* Anything to move? */
3933e0e1
MM		 8712 bytes = INTVAL (bytes_rtx);
8713 if (bytes <= 0)
7e69e155
MM		 8714 return 1;
8715
ea9982a8 8716 /* store_one_arg depends on expand_block_move to handle at least the size of
f676971a 8717 reg_parm_stack_space. */
ea9982a8 8718 if (bytes > (TARGET_POWERPC64 ? 64 : 32))
7e69e155
MM		 8719 return 0;
8720
cabfd258 8721 for (offset = 0; bytes > 0; offset += move_bytes, bytes -= move_bytes)
7e69e155 8722 {
cabfd258 8723 union {
70128ad9 8724 rtx (*movmemsi) (rtx, rtx, rtx, rtx);
a2369ed3 8725 rtx (*mov) (rtx, rtx);
cabfd258
GK		 8726 } gen_func;
8727 enum machine_mode mode = BLKmode;
8728 rtx src, dest;
f676971a 8729
5514620a
GK		 8730 /* Altivec first, since it will be faster than a string move
8731 when it applies, and usually not significantly larger. */
8732 if (TARGET_ALTIVEC && bytes >= 16 && align >= 128)
8733 {
8734 move_bytes = 16;
8735 mode = V4SImode;
8736 gen_func.mov = gen_movv4si;
8737 }
8738 else if (TARGET_STRING
cabfd258
GK		 8739 && bytes > 24 /* move up to 32 bytes at a time */
8740 && ! fixed_regs[5]
8741 && ! fixed_regs[6]
8742 && ! fixed_regs[7]
8743 && ! fixed_regs[8]
8744 && ! fixed_regs[9]
8745 && ! fixed_regs[10]
8746 && ! fixed_regs[11]
8747 && ! fixed_regs[12])
7e69e155 8748 {
cabfd258 8749 move_bytes = (bytes > 32) ? 32 : bytes;
70128ad9 8750 gen_func.movmemsi = gen_movmemsi_8reg;
cabfd258
GK		 8751 }
8752 else if (TARGET_STRING
8753 && bytes > 16 /* move up to 24 bytes at a time */
8754 && ! fixed_regs[5]
8755 && ! fixed_regs[6]
8756 && ! fixed_regs[7]
8757 && ! fixed_regs[8]
8758 && ! fixed_regs[9]
8759 && ! fixed_regs[10])
8760 {
8761 move_bytes = (bytes > 24) ? 24 : bytes;
70128ad9 8762 gen_func.movmemsi = gen_movmemsi_6reg;
cabfd258
GK		 8763 }
8764 else if (TARGET_STRING
8765 && bytes > 8 /* move up to 16 bytes at a time */
8766 && ! fixed_regs[5]
8767 && ! fixed_regs[6]
8768 && ! fixed_regs[7]
8769 && ! fixed_regs[8])
8770 {
8771 move_bytes = (bytes > 16) ? 16 : bytes;
70128ad9 8772 gen_func.movmemsi = gen_movmemsi_4reg;
cabfd258
GK		 8773 }
8774 else if (bytes >= 8 && TARGET_POWERPC64
8775 /* 64-bit loads and stores require word-aligned
8776 displacements. */
fba73eb1 8777 && (align >= 64 || (!STRICT_ALIGNMENT && align >= 32)))
cabfd258
GK		 8778 {
8779 move_bytes = 8;
8780 mode = DImode;
8781 gen_func.mov = gen_movdi;
8782 }
8783 else if (TARGET_STRING && bytes > 4 && !TARGET_POWERPC64)
8784 { /* move up to 8 bytes at a time */
8785 move_bytes = (bytes > 8) ? 8 : bytes;
70128ad9 8786 gen_func.movmemsi = gen_movmemsi_2reg;
cabfd258 8787 }
cd7d9ca4 8788 else if (bytes >= 4 && (align >= 32 || !STRICT_ALIGNMENT))
cabfd258
GK		 8789 { /* move 4 bytes */
8790 move_bytes = 4;
8791 mode = SImode;
8792 gen_func.mov = gen_movsi;
8793 }
cd7d9ca4 8794 else if (bytes == 2 && (align >= 16 || !STRICT_ALIGNMENT))
cabfd258
GK		 8795 { /* move 2 bytes */
8796 move_bytes = 2;
8797 mode = HImode;
8798 gen_func.mov = gen_movhi;
8799 }
8800 else if (TARGET_STRING && bytes > 1)
8801 { /* move up to 4 bytes at a time */
8802 move_bytes = (bytes > 4) ? 4 : bytes;
70128ad9 8803 gen_func.movmemsi = gen_movmemsi_1reg;
cabfd258
GK		 8804 }
8805 else /* move 1 byte at a time */
8806 {
8807 move_bytes = 1;
8808 mode = QImode;
8809 gen_func.mov = gen_movqi;
8810 }
f676971a 8811
cabfd258
GK		 8812 src = adjust_address (orig_src, mode, offset);
8813 dest = adjust_address (orig_dest, mode, offset);
f676971a
EC		 8814
8815 if (mode != BLKmode)
cabfd258
GK		 8816 {
8817 rtx tmp_reg = gen_reg_rtx (mode);
f676971a 8818
cabfd258
GK		 8819 emit_insn ((*gen_func.mov) (tmp_reg, src));
8820 stores[num_reg++] = (*gen_func.mov) (dest, tmp_reg);
4c64a852 8821 }
3933e0e1 8822
cabfd258
GK		 8823 if (mode == BLKmode || num_reg >= MAX_MOVE_REG || bytes == move_bytes)
8824 {
8825 int i;
8826 for (i = 0; i < num_reg; i++)
8827 emit_insn (stores[i]);
8828 num_reg = 0;
8829 }
35aff10b 8830
cabfd258 8831 if (mode == BLKmode)
7e69e155 8832 {
70128ad9 8833 /* Move the address into scratch registers. The movmemsi
cabfd258
GK		 8834 patterns require zero offset. */
8835 if (!REG_P (XEXP (src, 0)))
b6c9286a 8836 {
cabfd258
GK		 8837 rtx src_reg = copy_addr_to_reg (XEXP (src, 0));
8838 src = replace_equiv_address (src, src_reg);
b6c9286a 8839 }
cabfd258 8840 set_mem_size (src, GEN_INT (move_bytes));
f676971a 8841
cabfd258 8842 if (!REG_P (XEXP (dest, 0)))
3933e0e1 8843 {
cabfd258
GK		 8844 rtx dest_reg = copy_addr_to_reg (XEXP (dest, 0));
8845 dest = replace_equiv_address (dest, dest_reg);
7e69e155 8846 }
cabfd258 8847 set_mem_size (dest, GEN_INT (move_bytes));
f676971a 8848
70128ad9 8849 emit_insn ((*gen_func.movmemsi) (dest, src,
cabfd258
GK		 8850 GEN_INT (move_bytes & 31),
8851 align_rtx));
7e69e155 8852 }
7e69e155
MM		 8853 }
8854
8855 return 1;
8856}
8857
d62294f5 8858\f
9caa3eb2
DE		 8859/* Return a string to perform a load_multiple operation.
8860 operands[0] is the vector.
8861 operands[1] is the source address.
8862 operands[2] is the first destination register. */
8863
8864const char *
a2369ed3 8865rs6000_output_load_multiple (rtx operands[3])
9caa3eb2
DE		 8866{
8867 /* We have to handle the case where the pseudo used to contain the address
8868 is assigned to one of the output registers. */
8869 int i, j;
8870 int words = XVECLEN (operands[0], 0);
8871 rtx xop[10];
8872
8873 if (XVECLEN (operands[0], 0) == 1)
8874 return "{l|lwz} %2,0(%1)";
8875
8876 for (i = 0; i < words; i++)
8877 if (refers_to_regno_p (REGNO (operands[2]) + i,
8878 REGNO (operands[2]) + i + 1, operands[1], 0))
8879 {
8880 if (i == words-1)
8881 {
8882 xop[0] = GEN_INT (4 * (words-1));
8883 xop[1] = operands[1];
8884 xop[2] = operands[2];
8885 output_asm_insn ("{lsi|lswi} %2,%1,%0\n\t{l|lwz} %1,%0(%1)", xop);
8886 return "";
8887 }
8888 else if (i == 0)
8889 {
8890 xop[0] = GEN_INT (4 * (words-1));
8891 xop[1] = operands[1];
8892 xop[2] = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
8893 output_asm_insn ("{cal %1,4(%1)|addi %1,%1,4}\n\t{lsi|lswi} %2,%1,%0\n\t{l|lwz} %1,-4(%1)", xop);
8894 return "";
8895 }
8896 else
8897 {
8898 for (j = 0; j < words; j++)
8899 if (j != i)
8900 {
8901 xop[0] = GEN_INT (j * 4);
8902 xop[1] = operands[1];
8903 xop[2] = gen_rtx_REG (SImode, REGNO (operands[2]) + j);
8904 output_asm_insn ("{l|lwz} %2,%0(%1)", xop);
8905 }
8906 xop[0] = GEN_INT (i * 4);
8907 xop[1] = operands[1];
8908 output_asm_insn ("{l|lwz} %1,%0(%1)", xop);
8909 return "";
8910 }
8911 }
8912
8913 return "{lsi|lswi} %2,%1,%N0";
8914}
8915
9878760c 8916\f
a4f6c312
SS		 8917/* A validation routine: say whether CODE, a condition code, and MODE
8918 match. The other alternatives either don't make sense or should
8919 never be generated. */
39a10a29 8920
48d72335 8921void
a2369ed3 8922validate_condition_mode (enum rtx_code code, enum machine_mode mode)
39a10a29 8923{
37409796
NS		 8924 gcc_assert ((GET_RTX_CLASS (code) == RTX_COMPARE
8925 || GET_RTX_CLASS (code) == RTX_COMM_COMPARE)
8926 && GET_MODE_CLASS (mode) == MODE_CC);
39a10a29
GK		 8927
8928 /* These don't make sense. */
37409796
NS		 8929 gcc_assert ((code != GT && code != LT && code != GE && code != LE)
8930 || mode != CCUNSmode);
39a10a29 8931
37409796
NS		 8932 gcc_assert ((code != GTU && code != LTU && code != GEU && code != LEU)
8933 || mode == CCUNSmode);
39a10a29 8934
37409796
NS		 8935 gcc_assert (mode == CCFPmode
8936 || (code != ORDERED && code != UNORDERED
8937 && code != UNEQ && code != LTGT
8938 && code != UNGT && code != UNLT
8939 && code != UNGE && code != UNLE));
f676971a
EC		 8940
8941 /* These should never be generated except for
bc9ec0e0 8942 flag_finite_math_only. */
37409796
NS		 8943 gcc_assert (mode != CCFPmode
8944 || flag_finite_math_only
8945 || (code != LE && code != GE
8946 && code != UNEQ && code != LTGT
8947 && code != UNGT && code != UNLT));
39a10a29
GK		 8948
8949 /* These are invalid; the information is not there. */
37409796 8950 gcc_assert (mode != CCEQmode || code == EQ || code == NE);
39a10a29
GK		 8951}
8952
9878760c
RK		 8953\f
8954/* Return 1 if ANDOP is a mask that has no bits on that are not in the
8955 mask required to convert the result of a rotate insn into a shift
b1765bde 8956 left insn of SHIFTOP bits. Both are known to be SImode CONST_INT. */
9878760c
RK		 8957
8958int
a2369ed3 8959includes_lshift_p (rtx shiftop, rtx andop)
9878760c 8960{
e2c953b6
DE		 8961 unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0;
8962
8963 shift_mask <<= INTVAL (shiftop);
9878760c 8964
b1765bde 8965 return (INTVAL (andop) & 0xffffffff & ~shift_mask) == 0;
9878760c
RK		 8966}
8967
8968/* Similar, but for right shift. */
8969
8970int
a2369ed3 8971includes_rshift_p (rtx shiftop, rtx andop)
9878760c 8972{
a7653a2c 8973 unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0;
9878760c
RK		 8974
8975 shift_mask >>= INTVAL (shiftop);
8976
b1765bde 8977 return (INTVAL (andop) & 0xffffffff & ~shift_mask) == 0;
e2c953b6
DE		 8978}
8979
c5059423
AM		 8980/* Return 1 if ANDOP is a mask suitable for use with an rldic insn
8981 to perform a left shift. It must have exactly SHIFTOP least
b6d08ca1 8982 significant 0's, then one or more 1's, then zero or more 0's. */
e2c953b6
DE		 8983
8984int
a2369ed3 8985includes_rldic_lshift_p (rtx shiftop, rtx andop)
e2c953b6 8986{
c5059423
AM		 8987 if (GET_CODE (andop) == CONST_INT)
8988 {
02071907 8989 HOST_WIDE_INT c, lsb, shift_mask;
e2c953b6 8990
c5059423 8991 c = INTVAL (andop);
02071907 8992 if (c == 0 || c == ~0)
c5059423 8993 return 0;
e2c953b6 8994
02071907 8995 shift_mask = ~0;
c5059423
AM		 8996 shift_mask <<= INTVAL (shiftop);
8997
b6d08ca1 8998 /* Find the least significant one bit. */
c5059423
AM		 8999 lsb = c & -c;
9000
9001 /* It must coincide with the LSB of the shift mask. */
9002 if (-lsb != shift_mask)
9003 return 0;
e2c953b6 9004
c5059423
AM		 9005 /* Invert to look for the next transition (if any). */
9006 c = ~c;
9007
9008 /* Remove the low group of ones (originally low group of zeros). */
9009 c &= -lsb;
9010
9011 /* Again find the lsb, and check we have all 1's above. */
9012 lsb = c & -c;
9013 return c == -lsb;
9014 }
9015 else if (GET_CODE (andop) == CONST_DOUBLE
9016 && (GET_MODE (andop) == VOIDmode || GET_MODE (andop) == DImode))
9017 {
02071907
AM		 9018 HOST_WIDE_INT low, high, lsb;
9019 HOST_WIDE_INT shift_mask_low, shift_mask_high;
c5059423
AM		 9020
9021 low = CONST_DOUBLE_LOW (andop);
9022 if (HOST_BITS_PER_WIDE_INT < 64)
9023 high = CONST_DOUBLE_HIGH (andop);
9024
9025 if ((low == 0 && (HOST_BITS_PER_WIDE_INT >= 64 || high == 0))
02071907 9026 || (low == ~0 && (HOST_BITS_PER_WIDE_INT >= 64 || high == ~0)))
c5059423
AM		 9027 return 0;
9028
9029 if (HOST_BITS_PER_WIDE_INT < 64 && low == 0)
9030 {
02071907 9031 shift_mask_high = ~0;
c5059423
AM		 9032 if (INTVAL (shiftop) > 32)
9033 shift_mask_high <<= INTVAL (shiftop) - 32;
9034
9035 lsb = high & -high;
9036
9037 if (-lsb != shift_mask_high || INTVAL (shiftop) < 32)
9038 return 0;
9039
9040 high = ~high;
9041 high &= -lsb;
9042
9043 lsb = high & -high;
9044 return high == -lsb;
9045 }
9046
02071907 9047 shift_mask_low = ~0;
c5059423
AM		 9048 shift_mask_low <<= INTVAL (shiftop);
9049
9050 lsb = low & -low;
9051
9052 if (-lsb != shift_mask_low)
9053 return 0;
9054
9055 if (HOST_BITS_PER_WIDE_INT < 64)
9056 high = ~high;
9057 low = ~low;
9058 low &= -lsb;
9059
9060 if (HOST_BITS_PER_WIDE_INT < 64 && low == 0)
9061 {
9062 lsb = high & -high;
9063 return high == -lsb;
9064 }
9065
9066 lsb = low & -low;
9067 return low == -lsb && (HOST_BITS_PER_WIDE_INT >= 64 || high == ~0);
9068 }
9069 else
9070 return 0;
9071}
e2c953b6 9072
c5059423
AM		 9073/* Return 1 if ANDOP is a mask suitable for use with an rldicr insn
9074 to perform a left shift. It must have SHIFTOP or more least
c1207243 9075 significant 0's, with the remainder of the word 1's. */
e2c953b6 9076
c5059423 9077int
a2369ed3 9078includes_rldicr_lshift_p (rtx shiftop, rtx andop)
c5059423 9079{
e2c953b6 9080 if (GET_CODE (andop) == CONST_INT)
c5059423 9081 {
02071907 9082 HOST_WIDE_INT c, lsb, shift_mask;
c5059423 9083
02071907 9084 shift_mask = ~0;
c5059423
AM		 9085 shift_mask <<= INTVAL (shiftop);
9086 c = INTVAL (andop);
9087
c1207243 9088 /* Find the least significant one bit. */
c5059423
AM		 9089 lsb = c & -c;
9090
9091 /* It must be covered by the shift mask.
a4f6c312 9092 This test also rejects c == 0. */
c5059423
AM		 9093 if ((lsb & shift_mask) == 0)
9094 return 0;
9095
9096 /* Check we have all 1's above the transition, and reject all 1's. */
9097 return c == -lsb && lsb != 1;
9098 }
9099 else if (GET_CODE (andop) == CONST_DOUBLE
9100 && (GET_MODE (andop) == VOIDmode || GET_MODE (andop) == DImode))
9101 {
02071907 9102 HOST_WIDE_INT low, lsb, shift_mask_low;
c5059423
AM		 9103
9104 low = CONST_DOUBLE_LOW (andop);
9105
9106 if (HOST_BITS_PER_WIDE_INT < 64)
9107 {
02071907 9108 HOST_WIDE_INT high, shift_mask_high;
c5059423
AM		 9109
9110 high = CONST_DOUBLE_HIGH (andop);
9111
9112 if (low == 0)
9113 {
02071907 9114 shift_mask_high = ~0;
c5059423
AM		 9115 if (INTVAL (shiftop) > 32)
9116 shift_mask_high <<= INTVAL (shiftop) - 32;
9117
9118 lsb = high & -high;
9119
9120 if ((lsb & shift_mask_high) == 0)
9121 return 0;
9122
9123 return high == -lsb;
9124 }
9125 if (high != ~0)
9126 return 0;
9127 }
9128
02071907 9129 shift_mask_low = ~0;
c5059423
AM		 9130 shift_mask_low <<= INTVAL (shiftop);
9131
9132 lsb = low & -low;
9133
9134 if ((lsb & shift_mask_low) == 0)
9135 return 0;
9136
9137 return low == -lsb && lsb != 1;
9138 }
e2c953b6 9139 else
c5059423 9140 return 0;
9878760c 9141}
35068b43 9142
11ac38b2
DE		 9143/* Return 1 if operands will generate a valid arguments to rlwimi
9144instruction for insert with right shift in 64-bit mode. The mask may
9145not start on the first bit or stop on the last bit because wrap-around
9146effects of instruction do not correspond to semantics of RTL insn. */
9147
9148int
9149insvdi_rshift_rlwimi_p (rtx sizeop, rtx startop, rtx shiftop)
9150{
9151 if (INTVAL (startop) < 64
9152 && INTVAL (startop) > 32
9153 && (INTVAL (sizeop) + INTVAL (startop) < 64)
9154 && (INTVAL (sizeop) + INTVAL (startop) > 33)
9155 && (INTVAL (sizeop) + INTVAL (startop) + INTVAL (shiftop) < 96)
9156 && (INTVAL (sizeop) + INTVAL (startop) + INTVAL (shiftop) >= 64)
9157 && (64 - (INTVAL (shiftop) & 63)) >= INTVAL (sizeop))
9158 return 1;
9159
9160 return 0;
9161}
9162
35068b43 9163/* Return 1 if REGNO (reg1) == REGNO (reg2) - 1 making them candidates
90f81f99 9164 for lfq and stfq insns iff the registers are hard registers. */
35068b43
RK		 9165
9166int
a2369ed3 9167registers_ok_for_quad_peep (rtx reg1, rtx reg2)
35068b43
RK		 9168{
9169 /* We might have been passed a SUBREG. */
f676971a 9170 if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG)
35068b43 9171 return 0;
f676971a 9172
90f81f99
AP		 9173 /* We might have been passed non floating point registers. */
9174 if (!FP_REGNO_P (REGNO (reg1))
9175 || !FP_REGNO_P (REGNO (reg2)))
9176 return 0;
35068b43
RK		 9177
9178 return (REGNO (reg1) == REGNO (reg2) - 1);
9179}
9180
a4f6c312
SS		 9181/* Return 1 if addr1 and addr2 are suitable for lfq or stfq insn.
9182 addr1 and addr2 must be in consecutive memory locations
9183 (addr2 == addr1 + 8). */
35068b43
RK		 9184
9185int
90f81f99 9186mems_ok_for_quad_peep (rtx mem1, rtx mem2)
35068b43 9187{
90f81f99 9188 rtx addr1, addr2;
e2c953b6 9189 unsigned int reg1;
35068b43
RK		 9190 int offset1;
9191
90f81f99
AP		 9192 /* The mems cannot be volatile. */
9193 if (MEM_VOLATILE_P (mem1) || MEM_VOLATILE_P (mem2))
9194 return 0;
f676971a 9195
90f81f99
AP		 9196 addr1 = XEXP (mem1, 0);
9197 addr2 = XEXP (mem2, 0);
9198
35068b43
RK		 9199 /* Extract an offset (if used) from the first addr. */
9200 if (GET_CODE (addr1) == PLUS)
9201 {
9202 /* If not a REG, return zero. */
9203 if (GET_CODE (XEXP (addr1, 0)) != REG)
9204 return 0;
9205 else
9206 {
c4ad648e 9207 reg1 = REGNO (XEXP (addr1, 0));
35068b43
RK		 9208 /* The offset must be constant! */
9209 if (GET_CODE (XEXP (addr1, 1)) != CONST_INT)
c4ad648e
AM		 9210 return 0;
9211 offset1 = INTVAL (XEXP (addr1, 1));
35068b43
RK		 9212 }
9213 }
9214 else if (GET_CODE (addr1) != REG)
9215 return 0;
9216 else
9217 {
9218 reg1 = REGNO (addr1);
9219 /* This was a simple (mem (reg)) expression. Offset is 0. */
9220 offset1 = 0;
9221 }
9222
a2369ed3 9223 /* Make sure the second address is a (mem (plus (reg) (const_int)))
f676971a 9224 or if it is (mem (reg)) then make sure that offset1 is -8 and the same
0f6937fe 9225 register as addr1. */
984e25ac 9226 if (offset1 == -8 && GET_CODE (addr2) == REG && reg1 == REGNO (addr2))
0f6937fe 9227 return 1;
35068b43
RK		 9228 if (GET_CODE (addr2) != PLUS)
9229 return 0;
9230
9231 if (GET_CODE (XEXP (addr2, 0)) != REG
9232 || GET_CODE (XEXP (addr2, 1)) != CONST_INT)
9233 return 0;
9234
9235 if (reg1 != REGNO (XEXP (addr2, 0)))
9236 return 0;
9237
9238 /* The offset for the second addr must be 8 more than the first addr. */
9239 if (INTVAL (XEXP (addr2, 1)) != offset1 + 8)
9240 return 0;
9241
9242 /* All the tests passed. addr1 and addr2 are valid for lfq or stfq
9243 instructions. */
9244 return 1;
9245}
9878760c
RK		 9246\f
9247/* Return the register class of a scratch register needed to copy IN into
9248 or out of a register in CLASS in MODE. If it can be done directly,
9249 NO_REGS is returned. */
9250
9251enum reg_class
f676971a 9252secondary_reload_class (enum reg_class class,
a9baceb1
GK		 9253 enum machine_mode mode ATTRIBUTE_UNUSED,
9254 rtx in)
9878760c 9255{
5accd822 9256 int regno;
9878760c 9257
ab82a49f
AP		 9258 if (TARGET_ELF || (DEFAULT_ABI == ABI_DARWIN
9259#if TARGET_MACHO
c4ad648e 9260 && MACHOPIC_INDIRECT
ab82a49f 9261#endif
c4ad648e 9262 ))
46fad5b7
DJ		 9263 {
9264 /* We cannot copy a symbolic operand directly into anything
c4ad648e
AM		 9265 other than BASE_REGS for TARGET_ELF. So indicate that a
9266 register from BASE_REGS is needed as an intermediate
9267 register.
f676971a 9268
46fad5b7
DJ		 9269 On Darwin, pic addresses require a load from memory, which
9270 needs a base register. */
9271 if (class != BASE_REGS
c4ad648e
AM		 9272 && (GET_CODE (in) == SYMBOL_REF
9273 || GET_CODE (in) == HIGH
9274 || GET_CODE (in) == LABEL_REF
9275 || GET_CODE (in) == CONST))
9276 return BASE_REGS;
46fad5b7 9277 }
e7b7998a 9278
5accd822
DE		 9279 if (GET_CODE (in) == REG)
9280 {
9281 regno = REGNO (in);
9282 if (regno >= FIRST_PSEUDO_REGISTER)
9283 {
9284 regno = true_regnum (in);
9285 if (regno >= FIRST_PSEUDO_REGISTER)
9286 regno = -1;
9287 }
9288 }
9289 else if (GET_CODE (in) == SUBREG)
9290 {
9291 regno = true_regnum (in);
9292 if (regno >= FIRST_PSEUDO_REGISTER)
9293 regno = -1;
9294 }
9295 else
9296 regno = -1;
9297
9878760c
RK		 9298 /* We can place anything into GENERAL_REGS and can put GENERAL_REGS
9299 into anything. */
9300 if (class == GENERAL_REGS || class == BASE_REGS
9301 || (regno >= 0 && INT_REGNO_P (regno)))
9302 return NO_REGS;
9303
9304 /* Constants, memory, and FP registers can go into FP registers. */
9305 if ((regno == -1 || FP_REGNO_P (regno))
9306 && (class == FLOAT_REGS || class == NON_SPECIAL_REGS))
9307 return NO_REGS;
9308
0ac081f6
AH		 9309 /* Memory, and AltiVec registers can go into AltiVec registers. */
9310 if ((regno == -1 || ALTIVEC_REGNO_P (regno))
9311 && class == ALTIVEC_REGS)
9312 return NO_REGS;
9313
9878760c
RK		 9314 /* We can copy among the CR registers. */
9315 if ((class == CR_REGS || class == CR0_REGS)
9316 && regno >= 0 && CR_REGNO_P (regno))
9317 return NO_REGS;
9318
9319 /* Otherwise, we need GENERAL_REGS. */
9320 return GENERAL_REGS;
9321}
9322\f
9323/* Given a comparison operation, return the bit number in CCR to test. We
f676971a 9324 know this is a valid comparison.
9878760c
RK		 9325
9326 SCC_P is 1 if this is for an scc. That means that %D will have been
9327 used instead of %C, so the bits will be in different places.
9328
b4ac57ab 9329 Return -1 if OP isn't a valid comparison for some reason. */
9878760c
RK		 9330
9331int
a2369ed3 9332ccr_bit (rtx op, int scc_p)
9878760c
RK		 9333{
9334 enum rtx_code code = GET_CODE (op);
9335 enum machine_mode cc_mode;
9336 int cc_regnum;
9337 int base_bit;
9ebbca7d 9338 rtx reg;
9878760c 9339
ec8e098d 9340 if (!COMPARISON_P (op))
9878760c
RK		 9341 return -1;
9342
9ebbca7d
GK		 9343 reg = XEXP (op, 0);
9344
37409796 9345 gcc_assert (GET_CODE (reg) == REG && CR_REGNO_P (REGNO (reg)));
9ebbca7d
GK		 9346
9347 cc_mode = GET_MODE (reg);
9348 cc_regnum = REGNO (reg);
9349 base_bit = 4 * (cc_regnum - CR0_REGNO);
9878760c 9350
39a10a29 9351 validate_condition_mode (code, cc_mode);
c5defebb 9352
b7053a3f
GK		 9353 /* When generating a sCOND operation, only positive conditions are
9354 allowed. */
37409796
NS		 9355 gcc_assert (!scc_p
9356 || code == EQ || code == GT || code == LT || code == UNORDERED
9357 || code == GTU || code == LTU);
f676971a 9358
9878760c
RK		 9359 switch (code)
9360 {
9361 case NE:
9362 return scc_p ? base_bit + 3 : base_bit + 2;
9363 case EQ:
9364 return base_bit + 2;
1c882ea4 9365 case GT: case GTU: case UNLE:
9878760c 9366 return base_bit + 1;
1c882ea4 9367 case LT: case LTU: case UNGE:
9878760c 9368 return base_bit;
1c882ea4
GK		 9369 case ORDERED: case UNORDERED:
9370 return base_bit + 3;
9878760c
RK		 9371
9372 case GE: case GEU:
39a10a29 9373 /* If scc, we will have done a cror to put the bit in the
9878760c
RK		 9374 unordered position. So test that bit. For integer, this is ! LT
9375 unless this is an scc insn. */
39a10a29 9376 return scc_p ? base_bit + 3 : base_bit;
9878760c
RK		 9377
9378 case LE: case LEU:
39a10a29 9379 return scc_p ? base_bit + 3 : base_bit + 1;
1c882ea4 9380
9878760c 9381 default:
37409796 9382 gcc_unreachable ();
9878760c
RK		 9383 }
9384}
1ff7789b 9385\f
8d30c4ee 9386/* Return the GOT register. */
1ff7789b 9387
9390387d 9388rtx
a2369ed3 9389rs6000_got_register (rtx value ATTRIBUTE_UNUSED)
1ff7789b 9390{
a4f6c312
SS		 9391 /* The second flow pass currently (June 1999) can't update
9392 regs_ever_live without disturbing other parts of the compiler, so
9393 update it here to make the prolog/epilogue code happy. */
1db02437
FS		 9394 if (no_new_pseudos && ! regs_ever_live[RS6000_PIC_OFFSET_TABLE_REGNUM])
9395 regs_ever_live[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
1ff7789b 9396
8d30c4ee 9397 current_function_uses_pic_offset_table = 1;
3cb999d8 9398
1ff7789b
MM		 9399 return pic_offset_table_rtx;
9400}
a7df97e6 9401\f
e2500fed
GK		 9402/* Function to init struct machine_function.
9403 This will be called, via a pointer variable,
9404 from push_function_context. */
a7df97e6 9405
e2500fed 9406static struct machine_function *
863d938c 9407rs6000_init_machine_status (void)
a7df97e6 9408{
e2500fed 9409 return ggc_alloc_cleared (sizeof (machine_function));
a7df97e6 9410}
9878760c 9411\f
0ba1b2ff
AM		 9412/* These macros test for integers and extract the low-order bits. */
9413#define INT_P(X) \
9414((GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST_DOUBLE) \
9415 && GET_MODE (X) == VOIDmode)
9416
9417#define INT_LOWPART(X) \
9418 (GET_CODE (X) == CONST_INT ? INTVAL (X) : CONST_DOUBLE_LOW (X))
9419
9420int
a2369ed3 9421extract_MB (rtx op)
0ba1b2ff
AM		 9422{
9423 int i;
9424 unsigned long val = INT_LOWPART (op);
9425
9426 /* If the high bit is zero, the value is the first 1 bit we find
9427 from the left. */
9428 if ((val & 0x80000000) == 0)
9429 {
37409796 9430 gcc_assert (val & 0xffffffff);
0ba1b2ff
AM		 9431
9432 i = 1;
9433 while (((val <<= 1) & 0x80000000) == 0)
9434 ++i;
9435 return i;
9436 }
9437
9438 /* If the high bit is set and the low bit is not, or the mask is all
9439 1's, the value is zero. */
9440 if ((val & 1) == 0 || (val & 0xffffffff) == 0xffffffff)
9441 return 0;
9442
9443 /* Otherwise we have a wrap-around mask. Look for the first 0 bit
9444 from the right. */
9445 i = 31;
9446 while (((val >>= 1) & 1) != 0)
9447 --i;
9448
9449 return i;
9450}
9451
9452int
a2369ed3 9453extract_ME (rtx op)
0ba1b2ff
AM		 9454{
9455 int i;
9456 unsigned long val = INT_LOWPART (op);
9457
9458 /* If the low bit is zero, the value is the first 1 bit we find from
9459 the right. */
9460 if ((val & 1) == 0)
9461 {
37409796 9462 gcc_assert (val & 0xffffffff);
0ba1b2ff
AM		 9463
9464 i = 30;
9465 while (((val >>= 1) & 1) == 0)
9466 --i;
9467
9468 return i;
9469 }
9470
9471 /* If the low bit is set and the high bit is not, or the mask is all
9472 1's, the value is 31. */
9473 if ((val & 0x80000000) == 0 || (val & 0xffffffff) == 0xffffffff)
9474 return 31;
9475
9476 /* Otherwise we have a wrap-around mask. Look for the first 0 bit
9477 from the left. */
9478 i = 0;
9479 while (((val <<= 1) & 0x80000000) != 0)
9480 ++i;
9481
9482 return i;
9483}
9484
c4501e62
JJ		 9485/* Locate some local-dynamic symbol still in use by this function
9486 so that we can print its name in some tls_ld pattern. */
9487
9488static const char *
863d938c 9489rs6000_get_some_local_dynamic_name (void)
c4501e62
JJ		 9490{
9491 rtx insn;
9492
9493 if (cfun->machine->some_ld_name)
9494 return cfun->machine->some_ld_name;
9495
9496 for (insn = get_insns (); insn ; insn = NEXT_INSN (insn))
9497 if (INSN_P (insn)
9498 && for_each_rtx (&PATTERN (insn),
9499 rs6000_get_some_local_dynamic_name_1, 0))
9500 return cfun->machine->some_ld_name;
9501
37409796 9502 gcc_unreachable ();
c4501e62
JJ		 9503}
9504
9505/* Helper function for rs6000_get_some_local_dynamic_name. */
9506
9507static int
a2369ed3 9508rs6000_get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
c4501e62
JJ		 9509{
9510 rtx x = *px;
9511
9512 if (GET_CODE (x) == SYMBOL_REF)
9513 {
9514 const char *str = XSTR (x, 0);
9515 if (SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC)
9516 {
9517 cfun->machine->some_ld_name = str;
9518 return 1;
9519 }
9520 }
9521
9522 return 0;
9523}
9524
85b776df
AM		 9525/* Write out a function code label. */
9526
9527void
9528rs6000_output_function_entry (FILE *file, const char *fname)
9529{
9530 if (fname[0] != '.')
9531 {
9532 switch (DEFAULT_ABI)
9533 {
9534 default:
37409796 9535 gcc_unreachable ();
85b776df
AM		 9536
9537 case ABI_AIX:
9538 if (DOT_SYMBOLS)
9539 putc ('.', file);
9540 else
9541 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "L.");
9542 break;
9543
9544 case ABI_V4:
9545 case ABI_DARWIN:
9546 break;
9547 }
9548 }
9549 if (TARGET_AIX)
9550 RS6000_OUTPUT_BASENAME (file, fname);
9551 else
9552 assemble_name (file, fname);
9553}
9554
9878760c
RK		 9555/* Print an operand. Recognize special options, documented below. */
9556
38c1f2d7 9557#if TARGET_ELF
d9407988 9558#define SMALL_DATA_RELOC ((rs6000_sdata == SDATA_EABI) ? "sda21" : "sdarel")
8fbd2dc7 9559#define SMALL_DATA_REG ((rs6000_sdata == SDATA_EABI) ? 0 : 13)
ba5e43aa
MM		 9560#else
9561#define SMALL_DATA_RELOC "sda21"
8fbd2dc7 9562#define SMALL_DATA_REG 0
ba5e43aa
MM		 9563#endif
9564
9878760c 9565void
a2369ed3 9566print_operand (FILE *file, rtx x, int code)
9878760c
RK		 9567{
9568 int i;
a260abc9 9569 HOST_WIDE_INT val;
0ba1b2ff 9570 unsigned HOST_WIDE_INT uval;
9878760c
RK		 9571
9572 switch (code)
9573 {
a8b3aeda 9574 case '.':
a85d226b
RK		 9575 /* Write out an instruction after the call which may be replaced
9576 with glue code by the loader. This depends on the AIX version. */
9577 asm_fprintf (file, RS6000_CALL_GLUE);
a8b3aeda
RK		 9578 return;
9579
81eace42
GK		 9580 /* %a is output_address. */
9581
9854d9ed
RK		 9582 case 'A':
9583 /* If X is a constant integer whose low-order 5 bits are zero,
9584 write 'l'. Otherwise, write 'r'. This is a kludge to fix a bug
76229ac8 9585 in the AIX assembler where "sri" with a zero shift count
20e26713 9586 writes a trash instruction. */
9854d9ed 9587 if (GET_CODE (x) == CONST_INT && (INTVAL (x) & 31) == 0)
76229ac8 9588 putc ('l', file);
9854d9ed 9589 else
76229ac8 9590 putc ('r', file);
9854d9ed
RK		 9591 return;
9592
9593 case 'b':
e2c953b6
DE		 9594 /* If constant, low-order 16 bits of constant, unsigned.
9595 Otherwise, write normally. */
9596 if (INT_P (x))
9597 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 0xffff);
9598 else
9599 print_operand (file, x, 0);
cad12a8d
RK		 9600 return;
9601
a260abc9
DE		 9602 case 'B':
9603 /* If the low-order bit is zero, write 'r'; otherwise, write 'l'
9604 for 64-bit mask direction. */
9390387d 9605 putc (((INT_LOWPART (x) & 1) == 0 ? 'r' : 'l'), file);
a238cd8b 9606 return;
a260abc9 9607
81eace42
GK		 9608 /* %c is output_addr_const if a CONSTANT_ADDRESS_P, otherwise
9609 output_operand. */
9610
423c1189
AH		 9611 case 'c':
9612 /* X is a CR register. Print the number of the GT bit of the CR. */
9613 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
9614 output_operand_lossage ("invalid %%E value");
9615 else
9616 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO) + 1);
9617 return;
9618
9619 case 'D':
6b1fedc3 9620 /* Like 'J' but get to the EQ bit. */
37409796 9621 gcc_assert (GET_CODE (x) == REG);
423c1189 9622
6b1fedc3
AH		 9623 /* Bit 1 is EQ bit. */
9624 i = 4 * (REGNO (x) - CR0_REGNO) + 2;
423c1189 9625
64022b5d 9626 fprintf (file, "%d", i);
423c1189
AH		 9627 return;
9628
9854d9ed 9629 case 'E':
39a10a29 9630 /* X is a CR register. Print the number of the EQ bit of the CR */
9854d9ed
RK		 9631 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
9632 output_operand_lossage ("invalid %%E value");
78fbdbf7 9633 else
39a10a29 9634 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO) + 2);
a85d226b 9635 return;
9854d9ed
RK		 9636
9637 case 'f':
9638 /* X is a CR register. Print the shift count needed to move it
9639 to the high-order four bits. */
9640 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
9641 output_operand_lossage ("invalid %%f value");
9642 else
9ebbca7d 9643 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO));
9854d9ed
RK		 9644 return;
9645
9646 case 'F':
9647 /* Similar, but print the count for the rotate in the opposite
9648 direction. */
9649 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
9650 output_operand_lossage ("invalid %%F value");
9651 else
9ebbca7d 9652 fprintf (file, "%d", 32 - 4 * (REGNO (x) - CR0_REGNO));
9854d9ed
RK		 9653 return;
9654
9655 case 'G':
9656 /* X is a constant integer. If it is negative, print "m",
43aa4e05 9657 otherwise print "z". This is to make an aze or ame insn. */
9854d9ed
RK		 9658 if (GET_CODE (x) != CONST_INT)
9659 output_operand_lossage ("invalid %%G value");
9660 else if (INTVAL (x) >= 0)
76229ac8 9661 putc ('z', file);
9854d9ed 9662 else
76229ac8 9663 putc ('m', file);
9854d9ed 9664 return;
e2c953b6 9665
9878760c 9666 case 'h':
a4f6c312
SS		 9667 /* If constant, output low-order five bits. Otherwise, write
9668 normally. */
9878760c 9669 if (INT_P (x))
5f59ecb7 9670 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 31);
9878760c
RK		 9671 else
9672 print_operand (file, x, 0);
9673 return;
9674
64305719 9675 case 'H':
a4f6c312
SS		 9676 /* If constant, output low-order six bits. Otherwise, write
9677 normally. */
64305719 9678 if (INT_P (x))
5f59ecb7 9679 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 63);
64305719
DE		 9680 else
9681 print_operand (file, x, 0);
9682 return;
9683
9854d9ed
RK		 9684 case 'I':
9685 /* Print `i' if this is a constant, else nothing. */
9878760c 9686 if (INT_P (x))
76229ac8 9687 putc ('i', file);
9878760c
RK		 9688 return;
9689
9854d9ed
RK		 9690 case 'j':
9691 /* Write the bit number in CCR for jump. */
9692 i = ccr_bit (x, 0);
9693 if (i == -1)
9694 output_operand_lossage ("invalid %%j code");
9878760c 9695 else
9854d9ed 9696 fprintf (file, "%d", i);
9878760c
RK		 9697 return;
9698
9854d9ed
RK		 9699 case 'J':
9700 /* Similar, but add one for shift count in rlinm for scc and pass
9701 scc flag to `ccr_bit'. */
9702 i = ccr_bit (x, 1);
9703 if (i == -1)
9704 output_operand_lossage ("invalid %%J code");
9705 else
a0466a68
RK		 9706 /* If we want bit 31, write a shift count of zero, not 32. */
9707 fprintf (file, "%d", i == 31 ? 0 : i + 1);
9878760c
RK		 9708 return;
9709
9854d9ed
RK		 9710 case 'k':
9711 /* X must be a constant. Write the 1's complement of the
9712 constant. */
9878760c 9713 if (! INT_P (x))
9854d9ed 9714 output_operand_lossage ("invalid %%k value");
e2c953b6
DE		 9715 else
9716 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ~ INT_LOWPART (x));
9878760c
RK		 9717 return;
9718
81eace42 9719 case 'K':
9ebbca7d
GK		 9720 /* X must be a symbolic constant on ELF. Write an
9721 expression suitable for an 'addi' that adds in the low 16
9722 bits of the MEM. */
9723 if (GET_CODE (x) != CONST)
9724 {
9725 print_operand_address (file, x);
9726 fputs ("@l", file);
9727 }
9728 else
9729 {
9730 if (GET_CODE (XEXP (x, 0)) != PLUS
9731 || (GET_CODE (XEXP (XEXP (x, 0), 0)) != SYMBOL_REF
9732 && GET_CODE (XEXP (XEXP (x, 0), 0)) != LABEL_REF)
9733 || GET_CODE (XEXP (XEXP (x, 0), 1)) != CONST_INT)
53cd5d6c 9734 output_operand_lossage ("invalid %%K value");
9ebbca7d
GK		 9735 print_operand_address (file, XEXP (XEXP (x, 0), 0));
9736 fputs ("@l", file);
ed8d2920
MM		 9737 /* For GNU as, there must be a non-alphanumeric character
9738 between 'l' and the number. The '-' is added by
9739 print_operand() already. */
9740 if (INTVAL (XEXP (XEXP (x, 0), 1)) >= 0)
9741 fputs ("+", file);
9ebbca7d
GK		 9742 print_operand (file, XEXP (XEXP (x, 0), 1), 0);
9743 }
81eace42
GK		 9744 return;
9745
9746 /* %l is output_asm_label. */
9ebbca7d 9747
9854d9ed
RK		 9748 case 'L':
9749 /* Write second word of DImode or DFmode reference. Works on register
9750 or non-indexed memory only. */
9751 if (GET_CODE (x) == REG)
fb5c67a7 9752 fputs (reg_names[REGNO (x) + 1], file);
9854d9ed
RK		 9753 else if (GET_CODE (x) == MEM)
9754 {
9755 /* Handle possible auto-increment. Since it is pre-increment and
1427100a 9756 we have already done it, we can just use an offset of word. */
9854d9ed
RK		 9757 if (GET_CODE (XEXP (x, 0)) == PRE_INC
9758 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
ed8908e7
RK		 9759 output_address (plus_constant (XEXP (XEXP (x, 0), 0),
9760 UNITS_PER_WORD));
9854d9ed 9761 else
d7624dc0
RK		 9762 output_address (XEXP (adjust_address_nv (x, SImode,
9763 UNITS_PER_WORD),
9764 0));
ed8908e7 9765
ba5e43aa 9766 if (small_data_operand (x, GET_MODE (x)))
8fbd2dc7
MM		 9767 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
9768 reg_names[SMALL_DATA_REG]);
9854d9ed 9769 }
9878760c 9770 return;
f676971a 9771
9878760c
RK		 9772 case 'm':
9773 /* MB value for a mask operand. */
b1765bde 9774 if (! mask_operand (x, SImode))
9878760c
RK		 9775 output_operand_lossage ("invalid %%m value");
9776
0ba1b2ff 9777 fprintf (file, "%d", extract_MB (x));
9878760c
RK		 9778 return;
9779
9780 case 'M':
9781 /* ME value for a mask operand. */
b1765bde 9782 if (! mask_operand (x, SImode))
a260abc9 9783 output_operand_lossage ("invalid %%M value");
9878760c 9784
0ba1b2ff 9785 fprintf (file, "%d", extract_ME (x));
9878760c
RK		 9786 return;
9787
81eace42
GK		 9788 /* %n outputs the negative of its operand. */
9789
9878760c
RK		 9790 case 'N':
9791 /* Write the number of elements in the vector times 4. */
9792 if (GET_CODE (x) != PARALLEL)
9793 output_operand_lossage ("invalid %%N value");
e2c953b6
DE		 9794 else
9795 fprintf (file, "%d", XVECLEN (x, 0) * 4);
9878760c
RK		 9796 return;
9797
9798 case 'O':
9799 /* Similar, but subtract 1 first. */
9800 if (GET_CODE (x) != PARALLEL)
1427100a 9801 output_operand_lossage ("invalid %%O value");
e2c953b6
DE		 9802 else
9803 fprintf (file, "%d", (XVECLEN (x, 0) - 1) * 4);
9878760c
RK		 9804 return;
9805
9854d9ed
RK		 9806 case 'p':
9807 /* X is a CONST_INT that is a power of two. Output the logarithm. */
9808 if (! INT_P (x)
2bfcf297 9809 || INT_LOWPART (x) < 0
9854d9ed
RK		 9810 || (i = exact_log2 (INT_LOWPART (x))) < 0)
9811 output_operand_lossage ("invalid %%p value");
e2c953b6
DE		 9812 else
9813 fprintf (file, "%d", i);
9854d9ed
RK		 9814 return;
9815
9878760c
RK		 9816 case 'P':
9817 /* The operand must be an indirect memory reference. The result
8bb418a3 9818 is the register name. */
9878760c
RK		 9819 if (GET_CODE (x) != MEM || GET_CODE (XEXP (x, 0)) != REG
9820 || REGNO (XEXP (x, 0)) >= 32)
9821 output_operand_lossage ("invalid %%P value");
e2c953b6 9822 else
fb5c67a7 9823 fputs (reg_names[REGNO (XEXP (x, 0))], file);
9878760c
RK		 9824 return;
9825
dfbdccdb
GK		 9826 case 'q':
9827 /* This outputs the logical code corresponding to a boolean
9828 expression. The expression may have one or both operands
39a10a29 9829 negated (if one, only the first one). For condition register
c4ad648e
AM		 9830 logical operations, it will also treat the negated
9831 CR codes as NOTs, but not handle NOTs of them. */
dfbdccdb 9832 {
63bc1d05 9833 const char *const *t = 0;
dfbdccdb
GK		 9834 const char *s;
9835 enum rtx_code code = GET_CODE (x);
9836 static const char * const tbl[3][3] = {
9837 { "and", "andc", "nor" },
9838 { "or", "orc", "nand" },
9839 { "xor", "eqv", "xor" } };
9840
9841 if (code == AND)
9842 t = tbl[0];
9843 else if (code == IOR)
9844 t = tbl[1];
9845 else if (code == XOR)
9846 t = tbl[2];
9847 else
9848 output_operand_lossage ("invalid %%q value");
9849
9850 if (GET_CODE (XEXP (x, 0)) != NOT)
9851 s = t[0];
9852 else
9853 {
9854 if (GET_CODE (XEXP (x, 1)) == NOT)
9855 s = t[2];
9856 else
9857 s = t[1];
9858 }
f676971a 9859
dfbdccdb
GK		 9860 fputs (s, file);
9861 }
9862 return;
9863
2c4a9cff
DE		 9864 case 'Q':
9865 if (TARGET_MFCRF)
3b6ce0af 9866 fputc (',', file);
5efb1046 9867 /* FALLTHRU */
2c4a9cff
DE		 9868 else
9869 return;
9870
9854d9ed
RK		 9871 case 'R':
9872 /* X is a CR register. Print the mask for `mtcrf'. */
9873 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
9874 output_operand_lossage ("invalid %%R value");
9875 else
9ebbca7d 9876 fprintf (file, "%d", 128 >> (REGNO (x) - CR0_REGNO));
9878760c 9877 return;
9854d9ed
RK		 9878
9879 case 's':
9880 /* Low 5 bits of 32 - value */
9881 if (! INT_P (x))
9882 output_operand_lossage ("invalid %%s value");
e2c953b6
DE		 9883 else
9884 fprintf (file, HOST_WIDE_INT_PRINT_DEC, (32 - INT_LOWPART (x)) & 31);
9878760c 9885 return;
9854d9ed 9886
a260abc9 9887 case 'S':
0ba1b2ff 9888 /* PowerPC64 mask position. All 0's is excluded.
a260abc9
DE		 9889 CONST_INT 32-bit mask is considered sign-extended so any
9890 transition must occur within the CONST_INT, not on the boundary. */
4ae234b0 9891 if (! mask_operand (x, DImode))
a260abc9
DE		 9892 output_operand_lossage ("invalid %%S value");
9893
0ba1b2ff 9894 uval = INT_LOWPART (x);
a260abc9 9895
0ba1b2ff 9896 if (uval & 1) /* Clear Left */
a260abc9 9897 {
f099d360
GK		 9898#if HOST_BITS_PER_WIDE_INT > 64
9899 uval &= ((unsigned HOST_WIDE_INT) 1 << 64) - 1;
9900#endif
0ba1b2ff 9901 i = 64;
a260abc9 9902 }
0ba1b2ff 9903 else /* Clear Right */
a260abc9 9904 {
0ba1b2ff 9905 uval = ~uval;
f099d360
GK		 9906#if HOST_BITS_PER_WIDE_INT > 64
9907 uval &= ((unsigned HOST_WIDE_INT) 1 << 64) - 1;
9908#endif
0ba1b2ff 9909 i = 63;
a260abc9 9910 }
0ba1b2ff
AM		 9911 while (uval != 0)
9912 --i, uval >>= 1;
37409796 9913 gcc_assert (i >= 0);
0ba1b2ff
AM		 9914 fprintf (file, "%d", i);
9915 return;
a260abc9 9916
a3170dc6
AH		 9917 case 't':
9918 /* Like 'J' but get to the OVERFLOW/UNORDERED bit. */
37409796 9919 gcc_assert (GET_CODE (x) == REG && GET_MODE (x) == CCmode);
a3170dc6
AH		 9920
9921 /* Bit 3 is OV bit. */
9922 i = 4 * (REGNO (x) - CR0_REGNO) + 3;
9923
9924 /* If we want bit 31, write a shift count of zero, not 32. */
9925 fprintf (file, "%d", i == 31 ? 0 : i + 1);
9926 return;
9927
cccf3bdc
DE		 9928 case 'T':
9929 /* Print the symbolic name of a branch target register. */
9930 if (GET_CODE (x) != REG || (REGNO (x) != LINK_REGISTER_REGNUM
9931 && REGNO (x) != COUNT_REGISTER_REGNUM))
9932 output_operand_lossage ("invalid %%T value");
e2c953b6 9933 else if (REGNO (x) == LINK_REGISTER_REGNUM)
cccf3bdc
DE		 9934 fputs (TARGET_NEW_MNEMONICS ? "lr" : "r", file);
9935 else
9936 fputs ("ctr", file);
9937 return;
9938
9854d9ed 9939 case 'u':
802a0058 9940 /* High-order 16 bits of constant for use in unsigned operand. */
9854d9ed
RK		 9941 if (! INT_P (x))
9942 output_operand_lossage ("invalid %%u value");
e2c953b6 9943 else
f676971a 9944 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
e2c953b6 9945 (INT_LOWPART (x) >> 16) & 0xffff);
9878760c
RK		 9946 return;
9947
802a0058
MM		 9948 case 'v':
9949 /* High-order 16 bits of constant for use in signed operand. */
9950 if (! INT_P (x))
9951 output_operand_lossage ("invalid %%v value");
e2c953b6 9952 else
134c32f6
DE		 9953 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
9954 (INT_LOWPART (x) >> 16) & 0xffff);
9955 return;
802a0058 9956
9854d9ed
RK		 9957 case 'U':
9958 /* Print `u' if this has an auto-increment or auto-decrement. */
9959 if (GET_CODE (x) == MEM
9960 && (GET_CODE (XEXP (x, 0)) == PRE_INC
9961 || GET_CODE (XEXP (x, 0)) == PRE_DEC))
76229ac8 9962 putc ('u', file);
9854d9ed 9963 return;
9878760c 9964
e0cd0770
JC		 9965 case 'V':
9966 /* Print the trap code for this operand. */
9967 switch (GET_CODE (x))
9968 {
9969 case EQ:
9970 fputs ("eq", file); /* 4 */
9971 break;
9972 case NE:
9973 fputs ("ne", file); /* 24 */
9974 break;
9975 case LT:
9976 fputs ("lt", file); /* 16 */
9977 break;
9978 case LE:
9979 fputs ("le", file); /* 20 */
9980 break;
9981 case GT:
9982 fputs ("gt", file); /* 8 */
9983 break;
9984 case GE:
9985 fputs ("ge", file); /* 12 */
9986 break;
9987 case LTU:
9988 fputs ("llt", file); /* 2 */
9989 break;
9990 case LEU:
9991 fputs ("lle", file); /* 6 */
9992 break;
9993 case GTU:
9994 fputs ("lgt", file); /* 1 */
9995 break;
9996 case GEU:
9997 fputs ("lge", file); /* 5 */
9998 break;
9999 default:
37409796 10000 gcc_unreachable ();
e0cd0770
JC		 10001 }
10002 break;
10003
9854d9ed
RK		 10004 case 'w':
10005 /* If constant, low-order 16 bits of constant, signed. Otherwise, write
10006 normally. */
10007 if (INT_P (x))
f676971a 10008 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
5f59ecb7 10009 ((INT_LOWPART (x) & 0xffff) ^ 0x8000) - 0x8000);
9854d9ed
RK		 10010 else
10011 print_operand (file, x, 0);
9878760c
RK		 10012 return;
10013
9854d9ed 10014 case 'W':
e2c953b6 10015 /* MB value for a PowerPC64 rldic operand. */
e2c953b6
DE		 10016 val = (GET_CODE (x) == CONST_INT
10017 ? INTVAL (x) : CONST_DOUBLE_HIGH (x));
10018
10019 if (val < 0)
10020 i = -1;
9854d9ed 10021 else
e2c953b6
DE		 10022 for (i = 0; i < HOST_BITS_PER_WIDE_INT; i++)
10023 if ((val <<= 1) < 0)
10024 break;
10025
10026#if HOST_BITS_PER_WIDE_INT == 32
10027 if (GET_CODE (x) == CONST_INT && i >= 0)
10028 i += 32; /* zero-extend high-part was all 0's */
10029 else if (GET_CODE (x) == CONST_DOUBLE && i == 32)
10030 {
10031 val = CONST_DOUBLE_LOW (x);
10032
37409796
NS		 10033 gcc_assert (val);
10034 if (val < 0)
e2c953b6
DE		 10035 --i;
10036 else
10037 for ( ; i < 64; i++)
10038 if ((val <<= 1) < 0)
10039 break;
10040 }
10041#endif
10042
10043 fprintf (file, "%d", i + 1);
9854d9ed 10044 return;
9878760c 10045
9854d9ed
RK		 10046 case 'X':
10047 if (GET_CODE (x) == MEM
4d588c14 10048 && legitimate_indexed_address_p (XEXP (x, 0), 0))
76229ac8 10049 putc ('x', file);
9854d9ed 10050 return;
9878760c 10051
9854d9ed
RK		 10052 case 'Y':
10053 /* Like 'L', for third word of TImode */
10054 if (GET_CODE (x) == REG)
fb5c67a7 10055 fputs (reg_names[REGNO (x) + 2], file);
9854d9ed 10056 else if (GET_CODE (x) == MEM)
9878760c 10057 {
9854d9ed
RK		 10058 if (GET_CODE (XEXP (x, 0)) == PRE_INC
10059 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
a54d04b7 10060 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 8));
9854d9ed 10061 else
d7624dc0 10062 output_address (XEXP (adjust_address_nv (x, SImode, 8), 0));
ba5e43aa 10063 if (small_data_operand (x, GET_MODE (x)))
8fbd2dc7
MM		 10064 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
10065 reg_names[SMALL_DATA_REG]);
9878760c
RK		 10066 }
10067 return;
f676971a 10068
9878760c 10069 case 'z':
b4ac57ab
RS		 10070 /* X is a SYMBOL_REF. Write out the name preceded by a
10071 period and without any trailing data in brackets. Used for function
4d30c363
MM		 10072 names. If we are configured for System V (or the embedded ABI) on
10073 the PowerPC, do not emit the period, since those systems do not use
10074 TOCs and the like. */
37409796 10075 gcc_assert (GET_CODE (x) == SYMBOL_REF);
9878760c 10076
c4ad648e
AM		 10077 /* Mark the decl as referenced so that cgraph will output the
10078 function. */
9bf6462a 10079 if (SYMBOL_REF_DECL (x))
c4ad648e 10080 mark_decl_referenced (SYMBOL_REF_DECL (x));
9bf6462a 10081
85b776df 10082 /* For macho, check to see if we need a stub. */
f9da97f0
AP		 10083 if (TARGET_MACHO)
10084 {
10085 const char *name = XSTR (x, 0);
a031e781 10086#if TARGET_MACHO
3b48085e 10087 if (MACHOPIC_INDIRECT
11abc112
MM		 10088 && machopic_classify_symbol (x) == MACHOPIC_UNDEFINED_FUNCTION)
10089 name = machopic_indirection_name (x, /*stub_p=*/true);
f9da97f0
AP		 10090#endif
10091 assemble_name (file, name);
10092 }
85b776df 10093 else if (!DOT_SYMBOLS)
9739c90c 10094 assemble_name (file, XSTR (x, 0));
85b776df
AM		 10095 else
10096 rs6000_output_function_entry (file, XSTR (x, 0));
9878760c
RK		 10097 return;
10098
9854d9ed
RK		 10099 case 'Z':
10100 /* Like 'L', for last word of TImode. */
10101 if (GET_CODE (x) == REG)
fb5c67a7 10102 fputs (reg_names[REGNO (x) + 3], file);
9854d9ed
RK		 10103 else if (GET_CODE (x) == MEM)
10104 {
10105 if (GET_CODE (XEXP (x, 0)) == PRE_INC
10106 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
a54d04b7 10107 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 12));
9854d9ed 10108 else
d7624dc0 10109 output_address (XEXP (adjust_address_nv (x, SImode, 12), 0));
ba5e43aa 10110 if (small_data_operand (x, GET_MODE (x)))
8fbd2dc7
MM		 10111 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
10112 reg_names[SMALL_DATA_REG]);
9854d9ed 10113 }
5c23c401 10114 return;
0ac081f6 10115
a3170dc6 10116 /* Print AltiVec or SPE memory operand. */
0ac081f6
AH		 10117 case 'y':
10118 {
10119 rtx tmp;
10120
37409796 10121 gcc_assert (GET_CODE (x) == MEM);
0ac081f6
AH		 10122
10123 tmp = XEXP (x, 0);
10124
993f19a8 10125 if (TARGET_E500)
a3170dc6
AH		 10126 {
10127 /* Handle [reg]. */
10128 if (GET_CODE (tmp) == REG)
10129 {
10130 fprintf (file, "0(%s)", reg_names[REGNO (tmp)]);
10131 break;
10132 }
10133 /* Handle [reg+UIMM]. */
10134 else if (GET_CODE (tmp) == PLUS &&
10135 GET_CODE (XEXP (tmp, 1)) == CONST_INT)
10136 {
10137 int x;
10138
37409796 10139 gcc_assert (GET_CODE (XEXP (tmp, 0)) == REG);
a3170dc6
AH		 10140
10141 x = INTVAL (XEXP (tmp, 1));
10142 fprintf (file, "%d(%s)", x, reg_names[REGNO (XEXP (tmp, 0))]);
10143 break;
10144 }
10145
10146 /* Fall through. Must be [reg+reg]. */
10147 }
850e8d3d
DN		 10148 if (TARGET_ALTIVEC
10149 && GET_CODE (tmp) == AND
10150 && GET_CODE (XEXP (tmp, 1)) == CONST_INT
10151 && INTVAL (XEXP (tmp, 1)) == -16)
10152 tmp = XEXP (tmp, 0);
0ac081f6 10153 if (GET_CODE (tmp) == REG)
c62f2db5 10154 fprintf (file, "0,%s", reg_names[REGNO (tmp)]);
37409796 10155 else
0ac081f6 10156 {
37409796
NS		 10157 gcc_assert (GET_CODE (tmp) == PLUS
10158 && GET_CODE (XEXP (tmp, 1)) == REG);
10159
0ac081f6
AH		 10160 if (REGNO (XEXP (tmp, 0)) == 0)
10161 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 1)) ],
10162 reg_names[ REGNO (XEXP (tmp, 0)) ]);
10163 else
10164 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 0)) ],
10165 reg_names[ REGNO (XEXP (tmp, 1)) ]);
10166 }
0ac081f6
AH		 10167 break;
10168 }
f676971a 10169
9878760c
RK		 10170 case 0:
10171 if (GET_CODE (x) == REG)
10172 fprintf (file, "%s", reg_names[REGNO (x)]);
10173 else if (GET_CODE (x) == MEM)
10174 {
10175 /* We need to handle PRE_INC and PRE_DEC here, since we need to
10176 know the width from the mode. */
10177 if (GET_CODE (XEXP (x, 0)) == PRE_INC)
79ba6d34
MM		 10178 fprintf (file, "%d(%s)", GET_MODE_SIZE (GET_MODE (x)),
10179 reg_names[REGNO (XEXP (XEXP (x, 0), 0))]);
9878760c 10180 else if (GET_CODE (XEXP (x, 0)) == PRE_DEC)
79ba6d34
MM		 10181 fprintf (file, "%d(%s)", - GET_MODE_SIZE (GET_MODE (x)),
10182 reg_names[REGNO (XEXP (XEXP (x, 0), 0))]);
9878760c 10183 else
a54d04b7 10184 output_address (XEXP (x, 0));
9878760c
RK		 10185 }
10186 else
a54d04b7 10187 output_addr_const (file, x);
a85d226b 10188 return;
9878760c 10189
c4501e62
JJ		 10190 case '&':
10191 assemble_name (file, rs6000_get_some_local_dynamic_name ());
10192 return;
10193
9878760c
RK		 10194 default:
10195 output_operand_lossage ("invalid %%xn code");
10196 }
10197}
10198\f
10199/* Print the address of an operand. */
10200
10201void
a2369ed3 10202print_operand_address (FILE *file, rtx x)
9878760c
RK		 10203{
10204 if (GET_CODE (x) == REG)
4697a36c 10205 fprintf (file, "0(%s)", reg_names[ REGNO (x) ]);
9ebbca7d
GK		 10206 else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST
10207 || GET_CODE (x) == LABEL_REF)
9878760c
RK		 10208 {
10209 output_addr_const (file, x);
ba5e43aa 10210 if (small_data_operand (x, GET_MODE (x)))
8fbd2dc7
MM		 10211 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
10212 reg_names[SMALL_DATA_REG]);
37409796
NS		 10213 else
10214 gcc_assert (!TARGET_TOC);
9878760c
RK		 10215 }
10216 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == REG)
10217 {
10218 if (REGNO (XEXP (x, 0)) == 0)
4697a36c
MM		 10219 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 1)) ],
10220 reg_names[ REGNO (XEXP (x, 0)) ]);
9878760c 10221 else
4697a36c
MM		 10222 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 0)) ],
10223 reg_names[ REGNO (XEXP (x, 1)) ]);
9878760c
RK		 10224 }
10225 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT)
4a0a75dd
KG		 10226 fprintf (file, HOST_WIDE_INT_PRINT_DEC "(%s)",
10227 INTVAL (XEXP (x, 1)), reg_names[ REGNO (XEXP (x, 0)) ]);
3cb999d8
DE		 10228#if TARGET_ELF
10229 else if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 0)) == REG
c4ad648e 10230 && CONSTANT_P (XEXP (x, 1)))
4697a36c
MM		 10231 {
10232 output_addr_const (file, XEXP (x, 1));
10233 fprintf (file, "@l(%s)", reg_names[ REGNO (XEXP (x, 0)) ]);
10234 }
c859cda6
DJ		 10235#endif
10236#if TARGET_MACHO
10237 else if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 0)) == REG
c4ad648e 10238 && CONSTANT_P (XEXP (x, 1)))
c859cda6
DJ		 10239 {
10240 fprintf (file, "lo16(");
10241 output_addr_const (file, XEXP (x, 1));
10242 fprintf (file, ")(%s)", reg_names[ REGNO (XEXP (x, 0)) ]);
10243 }
3cb999d8 10244#endif
4d588c14 10245 else if (legitimate_constant_pool_address_p (x))
9ebbca7d 10246 {
2bfcf297 10247 if (TARGET_AIX && (!TARGET_ELF || !TARGET_MINIMAL_TOC))
9ebbca7d 10248 {
2bfcf297
DB		 10249 rtx contains_minus = XEXP (x, 1);
10250 rtx minus, symref;
10251 const char *name;
f676971a 10252
9ebbca7d 10253 /* Find the (minus (sym) (toc)) buried in X, and temporarily
a4f6c312 10254 turn it into (sym) for output_addr_const. */
9ebbca7d
GK		 10255 while (GET_CODE (XEXP (contains_minus, 0)) != MINUS)
10256 contains_minus = XEXP (contains_minus, 0);
10257
2bfcf297
DB		 10258 minus = XEXP (contains_minus, 0);
10259 symref = XEXP (minus, 0);
10260 XEXP (contains_minus, 0) = symref;
10261 if (TARGET_ELF)
10262 {
10263 char *newname;
10264
10265 name = XSTR (symref, 0);
10266 newname = alloca (strlen (name) + sizeof ("@toc"));
10267 strcpy (newname, name);
10268 strcat (newname, "@toc");
10269 XSTR (symref, 0) = newname;
10270 }
10271 output_addr_const (file, XEXP (x, 1));
10272 if (TARGET_ELF)
10273 XSTR (symref, 0) = name;
9ebbca7d
GK		 10274 XEXP (contains_minus, 0) = minus;
10275 }
10276 else
10277 output_addr_const (file, XEXP (x, 1));
10278
10279 fprintf (file, "(%s)", reg_names[REGNO (XEXP (x, 0))]);
10280 }
9878760c 10281 else
37409796 10282 gcc_unreachable ();
9878760c
RK		 10283}
10284\f
88cad84b 10285/* Target hook for assembling integer objects. The PowerPC version has
301d03af
RS		 10286 to handle fixup entries for relocatable code if RELOCATABLE_NEEDS_FIXUP
10287 is defined. It also needs to handle DI-mode objects on 64-bit
10288 targets. */
10289
10290static bool
a2369ed3 10291rs6000_assemble_integer (rtx x, unsigned int size, int aligned_p)
301d03af 10292{
f4f4921e 10293#ifdef RELOCATABLE_NEEDS_FIXUP
301d03af 10294 /* Special handling for SI values. */
84dcde01 10295 if (RELOCATABLE_NEEDS_FIXUP && size == 4 && aligned_p)
301d03af 10296 {
a2369ed3 10297 extern int in_toc_section (void);
301d03af 10298 static int recurse = 0;
f676971a 10299
301d03af
RS		 10300 /* For -mrelocatable, we mark all addresses that need to be fixed up
10301 in the .fixup section. */
10302 if (TARGET_RELOCATABLE
10303 && !in_toc_section ()
10304 && !in_text_section ()
642af3be 10305 && !in_unlikely_text_section ()
301d03af
RS		 10306 && !recurse
10307 && GET_CODE (x) != CONST_INT
10308 && GET_CODE (x) != CONST_DOUBLE
10309 && CONSTANT_P (x))
10310 {
10311 char buf[256];
10312
10313 recurse = 1;
10314 ASM_GENERATE_INTERNAL_LABEL (buf, "LCP", fixuplabelno);
10315 fixuplabelno++;
10316 ASM_OUTPUT_LABEL (asm_out_file, buf);
10317 fprintf (asm_out_file, "\t.long\t(");
10318 output_addr_const (asm_out_file, x);
10319 fprintf (asm_out_file, ")@fixup\n");
10320 fprintf (asm_out_file, "\t.section\t\".fixup\",\"aw\"\n");
10321 ASM_OUTPUT_ALIGN (asm_out_file, 2);
10322 fprintf (asm_out_file, "\t.long\t");
10323 assemble_name (asm_out_file, buf);
10324 fprintf (asm_out_file, "\n\t.previous\n");
10325 recurse = 0;
10326 return true;
10327 }
10328 /* Remove initial .'s to turn a -mcall-aixdesc function
10329 address into the address of the descriptor, not the function
10330 itself. */
10331 else if (GET_CODE (x) == SYMBOL_REF
10332 && XSTR (x, 0)[0] == '.'
10333 && DEFAULT_ABI == ABI_AIX)
10334 {
10335 const char *name = XSTR (x, 0);
10336 while (*name == '.')
10337 name++;
10338
10339 fprintf (asm_out_file, "\t.long\t%s\n", name);
10340 return true;
10341 }
10342 }
f4f4921e 10343#endif /* RELOCATABLE_NEEDS_FIXUP */
301d03af
RS		 10344 return default_assemble_integer (x, size, aligned_p);
10345}
93638d7a
AM		 10346
10347#ifdef HAVE_GAS_HIDDEN
10348/* Emit an assembler directive to set symbol visibility for DECL to
10349 VISIBILITY_TYPE. */
10350
5add3202 10351static void
a2369ed3 10352rs6000_assemble_visibility (tree decl, int vis)
93638d7a 10353{
93638d7a
AM		 10354 /* Functions need to have their entry point symbol visibility set as
10355 well as their descriptor symbol visibility. */
85b776df
AM		 10356 if (DEFAULT_ABI == ABI_AIX
10357 && DOT_SYMBOLS
10358 && TREE_CODE (decl) == FUNCTION_DECL)
93638d7a 10359 {
25fdb4dc 10360 static const char * const visibility_types[] = {
c4ad648e 10361 NULL, "internal", "hidden", "protected"
25fdb4dc
RH		 10362 };
10363
10364 const char *name, *type;
93638d7a
AM		 10365
10366 name = ((* targetm.strip_name_encoding)
10367 (IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl))));
25fdb4dc 10368 type = visibility_types[vis];
93638d7a 10369
25fdb4dc
RH		 10370 fprintf (asm_out_file, "\t.%s\t%s\n", type, name);
10371 fprintf (asm_out_file, "\t.%s\t.%s\n", type, name);
93638d7a 10372 }
25fdb4dc
RH		 10373 else
10374 default_assemble_visibility (decl, vis);
93638d7a
AM		 10375}
10376#endif
301d03af 10377\f
39a10a29 10378enum rtx_code
a2369ed3 10379rs6000_reverse_condition (enum machine_mode mode, enum rtx_code code)
39a10a29
GK		 10380{
10381 /* Reversal of FP compares takes care -- an ordered compare
10382 becomes an unordered compare and vice versa. */
f676971a 10383 if (mode == CCFPmode
bc9ec0e0
GK		 10384 && (!flag_finite_math_only
10385 || code == UNLT || code == UNLE || code == UNGT || code == UNGE
10386 || code == UNEQ || code == LTGT))
bab6226b 10387 return reverse_condition_maybe_unordered (code);
39a10a29 10388 else
bab6226b 10389 return reverse_condition (code);
39a10a29
GK		 10390}
10391
39a10a29
GK		 10392/* Generate a compare for CODE. Return a brand-new rtx that
10393 represents the result of the compare. */
a4f6c312 10394
39a10a29 10395static rtx
a2369ed3 10396rs6000_generate_compare (enum rtx_code code)
39a10a29
GK		 10397{
10398 enum machine_mode comp_mode;
10399 rtx compare_result;
10400
10401 if (rs6000_compare_fp_p)
10402 comp_mode = CCFPmode;
10403 else if (code == GTU || code == LTU
c4ad648e 10404 || code == GEU || code == LEU)
39a10a29 10405 comp_mode = CCUNSmode;
60934f9c
NS		 10406 else if ((code == EQ || code == NE)
10407 && GET_CODE (rs6000_compare_op0) == SUBREG
10408 && GET_CODE (rs6000_compare_op1) == SUBREG
10409 && SUBREG_PROMOTED_UNSIGNED_P (rs6000_compare_op0)
10410 && SUBREG_PROMOTED_UNSIGNED_P (rs6000_compare_op1))
10411 /* These are unsigned values, perhaps there will be a later
10412 ordering compare that can be shared with this one.
10413 Unfortunately we cannot detect the signedness of the operands
10414 for non-subregs. */
10415 comp_mode = CCUNSmode;
39a10a29
GK		 10416 else
10417 comp_mode = CCmode;
10418
10419 /* First, the compare. */
10420 compare_result = gen_reg_rtx (comp_mode);
a3170dc6
AH		 10421
10422 /* SPE FP compare instructions on the GPRs. Yuck! */
993f19a8
AH		 10423 if ((TARGET_E500 && !TARGET_FPRS && TARGET_HARD_FLOAT)
10424 && rs6000_compare_fp_p)
a3170dc6 10425 {
64022b5d 10426 rtx cmp, or_result, compare_result2;
4d4cbc0e
AH		 10427 enum machine_mode op_mode = GET_MODE (rs6000_compare_op0);
10428
10429 if (op_mode == VOIDmode)
10430 op_mode = GET_MODE (rs6000_compare_op1);
a3170dc6 10431
423c1189
AH		 10432 /* Note: The E500 comparison instructions set the GT bit (x +
10433 1), on success. This explains the mess. */
10434
a3170dc6
AH		 10435 switch (code)
10436 {
423c1189 10437 case EQ: case UNEQ: case NE: case LTGT:
37409796
NS		 10438 switch (op_mode)
10439 {
10440 case SFmode:
10441 cmp = flag_unsafe_math_optimizations
10442 ? gen_tstsfeq_gpr (compare_result, rs6000_compare_op0,
10443 rs6000_compare_op1)
10444 : gen_cmpsfeq_gpr (compare_result, rs6000_compare_op0,
10445 rs6000_compare_op1);
10446 break;
10447
10448 case DFmode:
10449 cmp = flag_unsafe_math_optimizations
10450 ? gen_tstdfeq_gpr (compare_result, rs6000_compare_op0,
10451 rs6000_compare_op1)
10452 : gen_cmpdfeq_gpr (compare_result, rs6000_compare_op0,
10453 rs6000_compare_op1);
10454 break;
10455
10456 default:
10457 gcc_unreachable ();
10458 }
a3170dc6 10459 break;
37409796 10460
423c1189 10461 case GT: case GTU: case UNGT: case UNGE: case GE: case GEU:
37409796
NS		 10462 switch (op_mode)
10463 {
10464 case SFmode:
10465 cmp = flag_unsafe_math_optimizations
10466 ? gen_tstsfgt_gpr (compare_result, rs6000_compare_op0,
10467 rs6000_compare_op1)
10468 : gen_cmpsfgt_gpr (compare_result, rs6000_compare_op0,
10469 rs6000_compare_op1);
10470 break;
10471
10472 case DFmode:
10473 cmp = flag_unsafe_math_optimizations
10474 ? gen_tstdfgt_gpr (compare_result, rs6000_compare_op0,
10475 rs6000_compare_op1)
10476 : gen_cmpdfgt_gpr (compare_result, rs6000_compare_op0,
10477 rs6000_compare_op1);
10478 break;
10479
10480 default:
10481 gcc_unreachable ();
10482 }
a3170dc6 10483 break;
37409796 10484
423c1189 10485 case LT: case LTU: case UNLT: case UNLE: case LE: case LEU:
37409796
NS		 10486 switch (op_mode)
10487 {
10488 case SFmode:
10489 cmp = flag_unsafe_math_optimizations
10490 ? gen_tstsflt_gpr (compare_result, rs6000_compare_op0,
10491 rs6000_compare_op1)
10492 : gen_cmpsflt_gpr (compare_result, rs6000_compare_op0,
10493 rs6000_compare_op1);
10494 break;
10495
10496 case DFmode:
10497 cmp = flag_unsafe_math_optimizations
10498 ? gen_tstdflt_gpr (compare_result, rs6000_compare_op0,
10499 rs6000_compare_op1)
10500 : gen_cmpdflt_gpr (compare_result, rs6000_compare_op0,
10501 rs6000_compare_op1);
10502 break;
10503
10504 default:
10505 gcc_unreachable ();
10506 }
a3170dc6 10507 break;
4d4cbc0e 10508 default:
37409796 10509 gcc_unreachable ();
a3170dc6
AH		 10510 }
10511
10512 /* Synthesize LE and GE from LT/GT || EQ. */
10513 if (code == LE || code == GE || code == LEU || code == GEU)
10514 {
a3170dc6
AH		 10515 emit_insn (cmp);
10516
10517 switch (code)
10518 {
10519 case LE: code = LT; break;
10520 case GE: code = GT; break;
10521 case LEU: code = LT; break;
10522 case GEU: code = GT; break;
37409796 10523 default: gcc_unreachable ();
a3170dc6
AH		 10524 }
10525
a3170dc6
AH		 10526 compare_result2 = gen_reg_rtx (CCFPmode);
10527
10528 /* Do the EQ. */
37409796
NS		 10529 switch (op_mode)
10530 {
10531 case SFmode:
10532 cmp = flag_unsafe_math_optimizations
10533 ? gen_tstsfeq_gpr (compare_result2, rs6000_compare_op0,
10534 rs6000_compare_op1)
10535 : gen_cmpsfeq_gpr (compare_result2, rs6000_compare_op0,
10536 rs6000_compare_op1);
10537 break;
10538
10539 case DFmode:
10540 cmp = flag_unsafe_math_optimizations
10541 ? gen_tstdfeq_gpr (compare_result2, rs6000_compare_op0,
10542 rs6000_compare_op1)
10543 : gen_cmpdfeq_gpr (compare_result2, rs6000_compare_op0,
10544 rs6000_compare_op1);
10545 break;
10546
10547 default:
10548 gcc_unreachable ();
10549 }
a3170dc6
AH		 10550 emit_insn (cmp);
10551
a3170dc6 10552 /* OR them together. */
64022b5d
AH		 10553 or_result = gen_reg_rtx (CCFPmode);
10554 cmp = gen_e500_cr_ior_compare (or_result, compare_result,
10555 compare_result2);
a3170dc6
AH		 10556 compare_result = or_result;
10557 code = EQ;
10558 }
10559 else
10560 {
a3170dc6 10561 if (code == NE || code == LTGT)
a3170dc6 10562 code = NE;
423c1189
AH		 10563 else
10564 code = EQ;
a3170dc6
AH		 10565 }
10566
10567 emit_insn (cmp);
10568 }
10569 else
de17c25f
DE		 10570 {
10571 /* Generate XLC-compatible TFmode compare as PARALLEL with extra
10572 CLOBBERs to match cmptf_internal2 pattern. */
10573 if (comp_mode == CCFPmode && TARGET_XL_COMPAT
10574 && GET_MODE (rs6000_compare_op0) == TFmode
10575 && (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
10576 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128)
10577 emit_insn (gen_rtx_PARALLEL (VOIDmode,
10578 gen_rtvec (9,
10579 gen_rtx_SET (VOIDmode,
10580 compare_result,
10581 gen_rtx_COMPARE (comp_mode,
10582 rs6000_compare_op0,
10583 rs6000_compare_op1)),
10584 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
10585 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
10586 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
10587 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
10588 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
10589 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
10590 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
10591 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)))));
10592 else
10593 emit_insn (gen_rtx_SET (VOIDmode, compare_result,
10594 gen_rtx_COMPARE (comp_mode,
10595 rs6000_compare_op0,
10596 rs6000_compare_op1)));
10597 }
f676971a 10598
ca5adc63 10599 /* Some kinds of FP comparisons need an OR operation;
e7108df9 10600 under flag_finite_math_only we don't bother. */
39a10a29 10601 if (rs6000_compare_fp_p
e7108df9
DE		 10602 && !flag_finite_math_only
10603 && !(TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS)
39a10a29
GK		 10604 && (code == LE || code == GE
10605 || code == UNEQ || code == LTGT
10606 || code == UNGT || code == UNLT))
10607 {
10608 enum rtx_code or1, or2;
10609 rtx or1_rtx, or2_rtx, compare2_rtx;
10610 rtx or_result = gen_reg_rtx (CCEQmode);
f676971a 10611
39a10a29
GK		 10612 switch (code)
10613 {
10614 case LE: or1 = LT; or2 = EQ; break;
10615 case GE: or1 = GT; or2 = EQ; break;
10616 case UNEQ: or1 = UNORDERED; or2 = EQ; break;
10617 case LTGT: or1 = LT; or2 = GT; break;
10618 case UNGT: or1 = UNORDERED; or2 = GT; break;
10619 case UNLT: or1 = UNORDERED; or2 = LT; break;
37409796 10620 default: gcc_unreachable ();
39a10a29
GK		 10621 }
10622 validate_condition_mode (or1, comp_mode);
10623 validate_condition_mode (or2, comp_mode);
1c563bed
KH		 10624 or1_rtx = gen_rtx_fmt_ee (or1, SImode, compare_result, const0_rtx);
10625 or2_rtx = gen_rtx_fmt_ee (or2, SImode, compare_result, const0_rtx);
39a10a29
GK		 10626 compare2_rtx = gen_rtx_COMPARE (CCEQmode,
10627 gen_rtx_IOR (SImode, or1_rtx, or2_rtx),
10628 const_true_rtx);
10629 emit_insn (gen_rtx_SET (VOIDmode, or_result, compare2_rtx));
10630
10631 compare_result = or_result;
10632 code = EQ;
10633 }
10634
10635 validate_condition_mode (code, GET_MODE (compare_result));
f676971a 10636
1c563bed 10637 return gen_rtx_fmt_ee (code, VOIDmode, compare_result, const0_rtx);
39a10a29
GK		 10638}
10639
10640
10641/* Emit the RTL for an sCOND pattern. */
10642
10643void
a2369ed3 10644rs6000_emit_sCOND (enum rtx_code code, rtx result)
39a10a29
GK		 10645{
10646 rtx condition_rtx;
10647 enum machine_mode op_mode;
b7053a3f 10648 enum rtx_code cond_code;
39a10a29
GK		 10649
10650 condition_rtx = rs6000_generate_compare (code);
b7053a3f
GK		 10651 cond_code = GET_CODE (condition_rtx);
10652
423c1189
AH		 10653 if (TARGET_E500 && rs6000_compare_fp_p
10654 && !TARGET_FPRS && TARGET_HARD_FLOAT)
10655 {
10656 rtx t;
10657
10658 PUT_MODE (condition_rtx, SImode);
10659 t = XEXP (condition_rtx, 0);
10660
37409796 10661 gcc_assert (cond_code == NE || cond_code == EQ);
423c1189
AH		 10662
10663 if (cond_code == NE)
64022b5d 10664 emit_insn (gen_e500_flip_gt_bit (t, t));
423c1189 10665
64022b5d 10666 emit_insn (gen_move_from_CR_gt_bit (result, t));
423c1189
AH		 10667 return;
10668 }
10669
b7053a3f
GK		 10670 if (cond_code == NE
10671 || cond_code == GE || cond_code == LE
10672 || cond_code == GEU || cond_code == LEU
10673 || cond_code == ORDERED || cond_code == UNGE || cond_code == UNLE)
10674 {
10675 rtx not_result = gen_reg_rtx (CCEQmode);
10676 rtx not_op, rev_cond_rtx;
10677 enum machine_mode cc_mode;
f676971a 10678
b7053a3f
GK		 10679 cc_mode = GET_MODE (XEXP (condition_rtx, 0));
10680
1c563bed 10681 rev_cond_rtx = gen_rtx_fmt_ee (rs6000_reverse_condition (cc_mode, cond_code),
0f4c242b 10682 SImode, XEXP (condition_rtx, 0), const0_rtx);
b7053a3f
GK		 10683 not_op = gen_rtx_COMPARE (CCEQmode, rev_cond_rtx, const0_rtx);
10684 emit_insn (gen_rtx_SET (VOIDmode, not_result, not_op));
10685 condition_rtx = gen_rtx_EQ (VOIDmode, not_result, const0_rtx);
10686 }
39a10a29
GK		 10687
10688 op_mode = GET_MODE (rs6000_compare_op0);
10689 if (op_mode == VOIDmode)
10690 op_mode = GET_MODE (rs6000_compare_op1);
10691
10692 if (TARGET_POWERPC64 && (op_mode == DImode || rs6000_compare_fp_p))
10693 {
10694 PUT_MODE (condition_rtx, DImode);
10695 convert_move (result, condition_rtx, 0);
10696 }
10697 else
10698 {
10699 PUT_MODE (condition_rtx, SImode);
10700 emit_insn (gen_rtx_SET (VOIDmode, result, condition_rtx));
10701 }
10702}
10703
39a10a29
GK		 10704/* Emit a branch of kind CODE to location LOC. */
10705
10706void
a2369ed3 10707rs6000_emit_cbranch (enum rtx_code code, rtx loc)
39a10a29
GK		 10708{
10709 rtx condition_rtx, loc_ref;
10710
10711 condition_rtx = rs6000_generate_compare (code);
10712 loc_ref = gen_rtx_LABEL_REF (VOIDmode, loc);
10713 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
10714 gen_rtx_IF_THEN_ELSE (VOIDmode, condition_rtx,
10715 loc_ref, pc_rtx)));
10716}
10717
12a4e8c5
GK		 10718/* Return the string to output a conditional branch to LABEL, which is
10719 the operand number of the label, or -1 if the branch is really a
f676971a 10720 conditional return.
12a4e8c5
GK		 10721
10722 OP is the conditional expression. XEXP (OP, 0) is assumed to be a
10723 condition code register and its mode specifies what kind of
10724 comparison we made.
10725
a0ab749a 10726 REVERSED is nonzero if we should reverse the sense of the comparison.
12a4e8c5
GK		 10727
10728 INSN is the insn. */
10729
10730char *
a2369ed3 10731output_cbranch (rtx op, const char *label, int reversed, rtx insn)
12a4e8c5
GK		 10732{
10733 static char string[64];
10734 enum rtx_code code = GET_CODE (op);
10735 rtx cc_reg = XEXP (op, 0);
10736 enum machine_mode mode = GET_MODE (cc_reg);
10737 int cc_regno = REGNO (cc_reg) - CR0_REGNO;
39a10a29 10738 int need_longbranch = label != NULL && get_attr_length (insn) == 8;
12a4e8c5
GK		 10739 int really_reversed = reversed ^ need_longbranch;
10740 char *s = string;
10741 const char *ccode;
10742 const char *pred;
10743 rtx note;
10744
39a10a29
GK		 10745 validate_condition_mode (code, mode);
10746
10747 /* Work out which way this really branches. We could use
10748 reverse_condition_maybe_unordered here always but this
10749 makes the resulting assembler clearer. */
12a4e8c5 10750 if (really_reversed)
de40e1df
DJ		 10751 {
10752 /* Reversal of FP compares takes care -- an ordered compare
10753 becomes an unordered compare and vice versa. */
10754 if (mode == CCFPmode)
10755 code = reverse_condition_maybe_unordered (code);
10756 else
10757 code = reverse_condition (code);
10758 }
12a4e8c5 10759
993f19a8 10760 if ((TARGET_E500 && !TARGET_FPRS && TARGET_HARD_FLOAT) && mode == CCFPmode)
a3170dc6
AH		 10761 {
10762 /* The efscmp/tst* instructions twiddle bit 2, which maps nicely
10763 to the GT bit. */
37409796
NS		 10764 switch (code)
10765 {
10766 case EQ:
10767 /* Opposite of GT. */
10768 code = GT;
10769 break;
10770
10771 case NE:
10772 code = UNLE;
10773 break;
10774
10775 default:
10776 gcc_unreachable ();
10777 }
a3170dc6
AH		 10778 }
10779
39a10a29 10780 switch (code)
12a4e8c5
GK		 10781 {
10782 /* Not all of these are actually distinct opcodes, but
10783 we distinguish them for clarity of the resulting assembler. */
50a0b056
GK		 10784 case NE: case LTGT:
10785 ccode = "ne"; break;
10786 case EQ: case UNEQ:
10787 ccode = "eq"; break;
f676971a 10788 case GE: case GEU:
50a0b056 10789 ccode = "ge"; break;
f676971a 10790 case GT: case GTU: case UNGT:
50a0b056 10791 ccode = "gt"; break;
f676971a 10792 case LE: case LEU:
50a0b056 10793 ccode = "le"; break;
f676971a 10794 case LT: case LTU: case UNLT:
50a0b056 10795 ccode = "lt"; break;
12a4e8c5
GK		 10796 case UNORDERED: ccode = "un"; break;
10797 case ORDERED: ccode = "nu"; break;
10798 case UNGE: ccode = "nl"; break;
10799 case UNLE: ccode = "ng"; break;
10800 default:
37409796 10801 gcc_unreachable ();
12a4e8c5 10802 }
f676971a
EC		 10803
10804 /* Maybe we have a guess as to how likely the branch is.
94a54f47 10805 The old mnemonics don't have a way to specify this information. */
f4857b9b 10806 pred = "";
12a4e8c5
GK		 10807 note = find_reg_note (insn, REG_BR_PROB, NULL_RTX);
10808 if (note != NULL_RTX)
10809 {
10810 /* PROB is the difference from 50%. */
10811 int prob = INTVAL (XEXP (note, 0)) - REG_BR_PROB_BASE / 2;
f4857b9b
AM		 10812
10813 /* Only hint for highly probable/improbable branches on newer
10814 cpus as static prediction overrides processor dynamic
10815 prediction. For older cpus we may as well always hint, but
10816 assume not taken for branches that are very close to 50% as a
10817 mispredicted taken branch is more expensive than a
f676971a 10818 mispredicted not-taken branch. */
ec507f2d 10819 if (rs6000_always_hint
f4857b9b
AM		 10820 || abs (prob) > REG_BR_PROB_BASE / 100 * 48)
10821 {
10822 if (abs (prob) > REG_BR_PROB_BASE / 20
10823 && ((prob > 0) ^ need_longbranch))
c4ad648e 10824 pred = "+";
f4857b9b
AM		 10825 else
10826 pred = "-";
10827 }
12a4e8c5 10828 }
12a4e8c5
GK		 10829
10830 if (label == NULL)
94a54f47 10831 s += sprintf (s, "{b%sr|b%slr%s} ", ccode, ccode, pred);
12a4e8c5 10832 else
94a54f47 10833 s += sprintf (s, "{b%s|b%s%s} ", ccode, ccode, pred);
12a4e8c5 10834
37c67319 10835 /* We need to escape any '%' characters in the reg_names string.
a3c9585f 10836 Assume they'd only be the first character.... */
37c67319
GK		 10837 if (reg_names[cc_regno + CR0_REGNO][0] == '%')
10838 *s++ = '%';
94a54f47 10839 s += sprintf (s, "%s", reg_names[cc_regno + CR0_REGNO]);
12a4e8c5
GK		 10840
10841 if (label != NULL)
10842 {
10843 /* If the branch distance was too far, we may have to use an
10844 unconditional branch to go the distance. */
10845 if (need_longbranch)
44518ddd 10846 s += sprintf (s, ",$+8\n\tb %s", label);
12a4e8c5
GK		 10847 else
10848 s += sprintf (s, ",%s", label);
10849 }
10850
10851 return string;
10852}
50a0b056 10853
64022b5d 10854/* Return the string to flip the GT bit on a CR. */
423c1189 10855char *
64022b5d 10856output_e500_flip_gt_bit (rtx dst, rtx src)
423c1189
AH		 10857{
10858 static char string[64];
10859 int a, b;
10860
37409796
NS		 10861 gcc_assert (GET_CODE (dst) == REG && CR_REGNO_P (REGNO (dst))
10862 && GET_CODE (src) == REG && CR_REGNO_P (REGNO (src)));
423c1189 10863
64022b5d
AH		 10864 /* GT bit. */
10865 a = 4 * (REGNO (dst) - CR0_REGNO) + 1;
10866 b = 4 * (REGNO (src) - CR0_REGNO) + 1;
423c1189
AH		 10867
10868 sprintf (string, "crnot %d,%d", a, b);
10869 return string;
10870}
10871
21213b4c
DP		 10872/* Return insn index for the vector compare instruction for given CODE,
10873 and DEST_MODE, OP_MODE. Return INSN_NOT_AVAILABLE if valid insn is
10874 not available. */
10875
10876static int
94ff898d 10877get_vec_cmp_insn (enum rtx_code code,
21213b4c
DP		 10878 enum machine_mode dest_mode,
10879 enum machine_mode op_mode)
10880{
10881 if (!TARGET_ALTIVEC)
10882 return INSN_NOT_AVAILABLE;
10883
10884 switch (code)
10885 {
10886 case EQ:
10887 if (dest_mode == V16QImode && op_mode == V16QImode)
10888 return UNSPEC_VCMPEQUB;
10889 if (dest_mode == V8HImode && op_mode == V8HImode)
10890 return UNSPEC_VCMPEQUH;
10891 if (dest_mode == V4SImode && op_mode == V4SImode)
10892 return UNSPEC_VCMPEQUW;
10893 if (dest_mode == V4SImode && op_mode == V4SFmode)
10894 return UNSPEC_VCMPEQFP;
10895 break;
10896 case GE:
10897 if (dest_mode == V4SImode && op_mode == V4SFmode)
10898 return UNSPEC_VCMPGEFP;
10899 case GT:
10900 if (dest_mode == V16QImode && op_mode == V16QImode)
10901 return UNSPEC_VCMPGTSB;
10902 if (dest_mode == V8HImode && op_mode == V8HImode)
10903 return UNSPEC_VCMPGTSH;
10904 if (dest_mode == V4SImode && op_mode == V4SImode)
10905 return UNSPEC_VCMPGTSW;
10906 if (dest_mode == V4SImode && op_mode == V4SFmode)
10907 return UNSPEC_VCMPGTFP;
10908 break;
10909 case GTU:
10910 if (dest_mode == V16QImode && op_mode == V16QImode)
10911 return UNSPEC_VCMPGTUB;
10912 if (dest_mode == V8HImode && op_mode == V8HImode)
10913 return UNSPEC_VCMPGTUH;
10914 if (dest_mode == V4SImode && op_mode == V4SImode)
10915 return UNSPEC_VCMPGTUW;
10916 break;
10917 default:
10918 break;
10919 }
10920 return INSN_NOT_AVAILABLE;
10921}
10922
10923/* Emit vector compare for operands OP0 and OP1 using code RCODE.
10924 DMODE is expected destination mode. This is a recursive function. */
10925
10926static rtx
10927rs6000_emit_vector_compare (enum rtx_code rcode,
10928 rtx op0, rtx op1,
10929 enum machine_mode dmode)
10930{
10931 int vec_cmp_insn;
10932 rtx mask;
10933 enum machine_mode dest_mode;
10934 enum machine_mode op_mode = GET_MODE (op1);
10935
37409796
NS		 10936 gcc_assert (TARGET_ALTIVEC);
10937 gcc_assert (GET_MODE (op0) == GET_MODE (op1));
21213b4c
DP		 10938
10939 /* Floating point vector compare instructions uses destination V4SImode.
10940 Move destination to appropriate mode later. */
10941 if (dmode == V4SFmode)
10942 dest_mode = V4SImode;
10943 else
10944 dest_mode = dmode;
10945
10946 mask = gen_reg_rtx (dest_mode);
10947 vec_cmp_insn = get_vec_cmp_insn (rcode, dest_mode, op_mode);
10948
10949 if (vec_cmp_insn == INSN_NOT_AVAILABLE)
10950 {
10951 bool swap_operands = false;
10952 bool try_again = false;
10953 switch (rcode)
10954 {
10955 case LT:
10956 rcode = GT;
10957 swap_operands = true;
10958 try_again = true;
10959 break;
10960 case LTU:
10961 rcode = GTU;
10962 swap_operands = true;
10963 try_again = true;
10964 break;
10965 case NE:
10966 /* Treat A != B as ~(A==B). */
10967 {
10968 enum insn_code nor_code;
10969 rtx eq_rtx = rs6000_emit_vector_compare (EQ, op0, op1,
10970 dest_mode);
94ff898d 10971
21213b4c 10972 nor_code = one_cmpl_optab->handlers[(int)dest_mode].insn_code;
37409796 10973 gcc_assert (nor_code != CODE_FOR_nothing);
21213b4c
DP		 10974 emit_insn (GEN_FCN (nor_code) (mask, eq_rtx));
10975
10976 if (dmode != dest_mode)
10977 {
10978 rtx temp = gen_reg_rtx (dest_mode);
10979 convert_move (temp, mask, 0);
10980 return temp;
10981 }
10982 return mask;
10983 }
10984 break;
10985 case GE:
10986 case GEU:
10987 case LE:
10988 case LEU:
10989 /* Try GT/GTU/LT/LTU OR EQ */
10990 {
10991 rtx c_rtx, eq_rtx;
10992 enum insn_code ior_code;
10993 enum rtx_code new_code;
10994
37409796
NS		 10995 switch (rcode)
10996 {
10997 case GE:
10998 new_code = GT;
10999 break;
11000
11001 case GEU:
11002 new_code = GTU;
11003 break;
11004
11005 case LE:
11006 new_code = LT;
11007 break;
11008
11009 case LEU:
11010 new_code = LTU;
11011 break;
11012
11013 default:
11014 gcc_unreachable ();
11015 }
21213b4c
DP		 11016
11017 c_rtx = rs6000_emit_vector_compare (new_code,
11018 op0, op1, dest_mode);
11019 eq_rtx = rs6000_emit_vector_compare (EQ, op0, op1,
11020 dest_mode);
11021
11022 ior_code = ior_optab->handlers[(int)dest_mode].insn_code;
37409796 11023 gcc_assert (ior_code != CODE_FOR_nothing);
21213b4c
DP		 11024 emit_insn (GEN_FCN (ior_code) (mask, c_rtx, eq_rtx));
11025 if (dmode != dest_mode)
11026 {
11027 rtx temp = gen_reg_rtx (dest_mode);
11028 convert_move (temp, mask, 0);
11029 return temp;
11030 }
11031 return mask;
11032 }
11033 break;
11034 default:
37409796 11035 gcc_unreachable ();
21213b4c
DP		 11036 }
11037
11038 if (try_again)
11039 {
11040 vec_cmp_insn = get_vec_cmp_insn (rcode, dest_mode, op_mode);
37409796
NS		 11041 /* You only get two chances. */
11042 gcc_assert (vec_cmp_insn != INSN_NOT_AVAILABLE);
21213b4c
DP		 11043 }
11044
11045 if (swap_operands)
11046 {
11047 rtx tmp;
11048 tmp = op0;
11049 op0 = op1;
11050 op1 = tmp;
11051 }
11052 }
11053
915167f5
GK		 11054 emit_insn (gen_rtx_SET (VOIDmode, mask,
11055 gen_rtx_UNSPEC (dest_mode,
11056 gen_rtvec (2, op0, op1),
11057 vec_cmp_insn)));
21213b4c
DP		 11058 if (dmode != dest_mode)
11059 {
11060 rtx temp = gen_reg_rtx (dest_mode);
11061 convert_move (temp, mask, 0);
11062 return temp;
11063 }
11064 return mask;
11065}
11066
11067/* Return vector select instruction for MODE. Return INSN_NOT_AVAILABLE, if
11068 valid insn doesn exist for given mode. */
11069
11070static int
11071get_vsel_insn (enum machine_mode mode)
11072{
11073 switch (mode)
11074 {
11075 case V4SImode:
11076 return UNSPEC_VSEL4SI;
11077 break;
11078 case V4SFmode:
11079 return UNSPEC_VSEL4SF;
11080 break;
11081 case V8HImode:
11082 return UNSPEC_VSEL8HI;
11083 break;
11084 case V16QImode:
11085 return UNSPEC_VSEL16QI;
11086 break;
11087 default:
11088 return INSN_NOT_AVAILABLE;
11089 break;
11090 }
11091 return INSN_NOT_AVAILABLE;
11092}
11093
11094/* Emit vector select insn where DEST is destination using
11095 operands OP1, OP2 and MASK. */
11096
11097static void
11098rs6000_emit_vector_select (rtx dest, rtx op1, rtx op2, rtx mask)
11099{
11100 rtx t, temp;
11101 enum machine_mode dest_mode = GET_MODE (dest);
11102 int vsel_insn_index = get_vsel_insn (GET_MODE (dest));
11103
11104 temp = gen_reg_rtx (dest_mode);
94ff898d 11105
19f1ebc7
DP		 11106 /* For each vector element, select op1 when mask is 1 otherwise
11107 select op2. */
915167f5
GK		 11108 t = gen_rtx_SET (VOIDmode, temp,
11109 gen_rtx_UNSPEC (dest_mode,
11110 gen_rtvec (3, op2, op1, mask),
11111 vsel_insn_index));
21213b4c
DP		 11112 emit_insn (t);
11113 emit_move_insn (dest, temp);
11114 return;
11115}
11116
94ff898d 11117/* Emit vector conditional expression.
21213b4c
DP		 11118 DEST is destination. OP1 and OP2 are two VEC_COND_EXPR operands.
11119 CC_OP0 and CC_OP1 are the two operands for the relation operation COND. */
11120
11121int
11122rs6000_emit_vector_cond_expr (rtx dest, rtx op1, rtx op2,
11123 rtx cond, rtx cc_op0, rtx cc_op1)
11124{
11125 enum machine_mode dest_mode = GET_MODE (dest);
11126 enum rtx_code rcode = GET_CODE (cond);
11127 rtx mask;
11128
11129 if (!TARGET_ALTIVEC)
11130 return 0;
11131
11132 /* Get the vector mask for the given relational operations. */
11133 mask = rs6000_emit_vector_compare (rcode, cc_op0, cc_op1, dest_mode);
11134
11135 rs6000_emit_vector_select (dest, op1, op2, mask);
11136
11137 return 1;
11138}
11139
50a0b056
GK		 11140/* Emit a conditional move: move TRUE_COND to DEST if OP of the
11141 operands of the last comparison is nonzero/true, FALSE_COND if it
11142 is zero/false. Return 0 if the hardware has no such operation. */
a4f6c312 11143
50a0b056 11144int
a2369ed3 11145rs6000_emit_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond)
50a0b056
GK		 11146{
11147 enum rtx_code code = GET_CODE (op);
11148 rtx op0 = rs6000_compare_op0;
11149 rtx op1 = rs6000_compare_op1;
11150 REAL_VALUE_TYPE c1;
3148ad6d
DJ		 11151 enum machine_mode compare_mode = GET_MODE (op0);
11152 enum machine_mode result_mode = GET_MODE (dest);
50a0b056 11153 rtx temp;
add2402e 11154 bool is_against_zero;
50a0b056 11155
a3c9585f 11156 /* These modes should always match. */
a3170dc6
AH		 11157 if (GET_MODE (op1) != compare_mode
11158 /* In the isel case however, we can use a compare immediate, so
11159 op1 may be a small constant. */
11160 && (!TARGET_ISEL || !short_cint_operand (op1, VOIDmode)))
3148ad6d 11161 return 0;
178c3eff 11162 if (GET_MODE (true_cond) != result_mode)
3148ad6d 11163 return 0;
178c3eff 11164 if (GET_MODE (false_cond) != result_mode)
3148ad6d
DJ		 11165 return 0;
11166
50a0b056 11167 /* First, work out if the hardware can do this at all, or
a3c9585f 11168 if it's too slow.... */
50a0b056 11169 if (! rs6000_compare_fp_p)
a3170dc6
AH		 11170 {
11171 if (TARGET_ISEL)
11172 return rs6000_emit_int_cmove (dest, op, true_cond, false_cond);
11173 return 0;
11174 }
fef98bf2
AH		 11175 else if (TARGET_E500 && TARGET_HARD_FLOAT && !TARGET_FPRS
11176 && GET_MODE_CLASS (compare_mode) == MODE_FLOAT)
11177 return 0;
50a0b056 11178
add2402e 11179 is_against_zero = op1 == CONST0_RTX (compare_mode);
94ff898d 11180
add2402e
GK		 11181 /* A floating-point subtract might overflow, underflow, or produce
11182 an inexact result, thus changing the floating-point flags, so it
11183 can't be generated if we care about that. It's safe if one side
11184 of the construct is zero, since then no subtract will be
11185 generated. */
11186 if (GET_MODE_CLASS (compare_mode) == MODE_FLOAT
11187 && flag_trapping_math && ! is_against_zero)
11188 return 0;
11189
50a0b056
GK		 11190 /* Eliminate half of the comparisons by switching operands, this
11191 makes the remaining code simpler. */
11192 if (code == UNLT || code == UNGT || code == UNORDERED || code == NE
bc9ec0e0 11193 || code == LTGT || code == LT || code == UNLE)
50a0b056
GK		 11194 {
11195 code = reverse_condition_maybe_unordered (code);
11196 temp = true_cond;
11197 true_cond = false_cond;
11198 false_cond = temp;
11199 }
11200
11201 /* UNEQ and LTGT take four instructions for a comparison with zero,
11202 it'll probably be faster to use a branch here too. */
bc9ec0e0 11203 if (code == UNEQ && HONOR_NANS (compare_mode))
50a0b056 11204 return 0;
f676971a 11205
50a0b056
GK		 11206 if (GET_CODE (op1) == CONST_DOUBLE)
11207 REAL_VALUE_FROM_CONST_DOUBLE (c1, op1);
f676971a 11208
b6d08ca1 11209 /* We're going to try to implement comparisons by performing
50a0b056
GK		 11210 a subtract, then comparing against zero. Unfortunately,
11211 Inf - Inf is NaN which is not zero, and so if we don't
27d30956 11212 know that the operand is finite and the comparison
50a0b056 11213 would treat EQ different to UNORDERED, we can't do it. */
bc9ec0e0 11214 if (HONOR_INFINITIES (compare_mode)
50a0b056 11215 && code != GT && code != UNGE
045572c7 11216 && (GET_CODE (op1) != CONST_DOUBLE || real_isinf (&c1))
50a0b056
GK		 11217 /* Constructs of the form (a OP b ? a : b) are safe. */
11218 && ((! rtx_equal_p (op0, false_cond) && ! rtx_equal_p (op1, false_cond))
f676971a 11219 || (! rtx_equal_p (op0, true_cond)
50a0b056
GK		 11220 && ! rtx_equal_p (op1, true_cond))))
11221 return 0;
add2402e 11222
50a0b056
GK		 11223 /* At this point we know we can use fsel. */
11224
11225 /* Reduce the comparison to a comparison against zero. */
add2402e
GK		 11226 if (! is_against_zero)
11227 {
11228 temp = gen_reg_rtx (compare_mode);
11229 emit_insn (gen_rtx_SET (VOIDmode, temp,
11230 gen_rtx_MINUS (compare_mode, op0, op1)));
11231 op0 = temp;
11232 op1 = CONST0_RTX (compare_mode);
11233 }
50a0b056
GK		 11234
11235 /* If we don't care about NaNs we can reduce some of the comparisons
11236 down to faster ones. */
bc9ec0e0 11237 if (! HONOR_NANS (compare_mode))
50a0b056
GK		 11238 switch (code)
11239 {
11240 case GT:
11241 code = LE;
11242 temp = true_cond;
11243 true_cond = false_cond;
11244 false_cond = temp;
11245 break;
11246 case UNGE:
11247 code = GE;
11248 break;
11249 case UNEQ:
11250 code = EQ;
11251 break;
11252 default:
11253 break;
11254 }
11255
11256 /* Now, reduce everything down to a GE. */
11257 switch (code)
11258 {
11259 case GE:
11260 break;
11261
11262 case LE:
3148ad6d
DJ		 11263 temp = gen_reg_rtx (compare_mode);
11264 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
50a0b056
GK		 11265 op0 = temp;
11266 break;
11267
11268 case ORDERED:
3148ad6d
DJ		 11269 temp = gen_reg_rtx (compare_mode);
11270 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_ABS (compare_mode, op0)));
50a0b056
GK		 11271 op0 = temp;
11272 break;
11273
11274 case EQ:
3148ad6d 11275 temp = gen_reg_rtx (compare_mode);
f676971a 11276 emit_insn (gen_rtx_SET (VOIDmode, temp,
3148ad6d
DJ		 11277 gen_rtx_NEG (compare_mode,
11278 gen_rtx_ABS (compare_mode, op0))));
50a0b056
GK		 11279 op0 = temp;
11280 break;
11281
11282 case UNGE:
bc9ec0e0 11283 /* a UNGE 0 <-> (a GE 0 || -a UNLT 0) */
3148ad6d 11284 temp = gen_reg_rtx (result_mode);
50a0b056 11285 emit_insn (gen_rtx_SET (VOIDmode, temp,
3148ad6d 11286 gen_rtx_IF_THEN_ELSE (result_mode,
50a0b056
GK		 11287 gen_rtx_GE (VOIDmode,
11288 op0, op1),
11289 true_cond, false_cond)));
bc9ec0e0
GK		 11290 false_cond = true_cond;
11291 true_cond = temp;
50a0b056 11292
3148ad6d
DJ		 11293 temp = gen_reg_rtx (compare_mode);
11294 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
50a0b056
GK		 11295 op0 = temp;
11296 break;
11297
11298 case GT:
bc9ec0e0 11299 /* a GT 0 <-> (a GE 0 && -a UNLT 0) */
3148ad6d 11300 temp = gen_reg_rtx (result_mode);
50a0b056 11301 emit_insn (gen_rtx_SET (VOIDmode, temp,
f676971a 11302 gen_rtx_IF_THEN_ELSE (result_mode,
50a0b056
GK		 11303 gen_rtx_GE (VOIDmode,
11304 op0, op1),
11305 true_cond, false_cond)));
bc9ec0e0
GK		 11306 true_cond = false_cond;
11307 false_cond = temp;
50a0b056 11308
3148ad6d
DJ		 11309 temp = gen_reg_rtx (compare_mode);
11310 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
50a0b056
GK		 11311 op0 = temp;
11312 break;
11313
11314 default:
37409796 11315 gcc_unreachable ();
50a0b056
GK		 11316 }
11317
11318 emit_insn (gen_rtx_SET (VOIDmode, dest,
3148ad6d 11319 gen_rtx_IF_THEN_ELSE (result_mode,
50a0b056
GK		 11320 gen_rtx_GE (VOIDmode,
11321 op0, op1),
11322 true_cond, false_cond)));
11323 return 1;
11324}
11325
a3170dc6
AH		 11326/* Same as above, but for ints (isel). */
11327
11328static int
a2369ed3 11329rs6000_emit_int_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond)
a3170dc6
AH		 11330{
11331 rtx condition_rtx, cr;
11332
11333 /* All isel implementations thus far are 32-bits. */
11334 if (GET_MODE (rs6000_compare_op0) != SImode)
11335 return 0;
11336
11337 /* We still have to do the compare, because isel doesn't do a
11338 compare, it just looks at the CRx bits set by a previous compare
11339 instruction. */
11340 condition_rtx = rs6000_generate_compare (GET_CODE (op));
11341 cr = XEXP (condition_rtx, 0);
11342
11343 if (GET_MODE (cr) == CCmode)
11344 emit_insn (gen_isel_signed (dest, condition_rtx,
11345 true_cond, false_cond, cr));
11346 else
11347 emit_insn (gen_isel_unsigned (dest, condition_rtx,
11348 true_cond, false_cond, cr));
11349
11350 return 1;
11351}
11352
11353const char *
a2369ed3 11354output_isel (rtx *operands)
a3170dc6
AH		 11355{
11356 enum rtx_code code;
11357
11358 code = GET_CODE (operands[1]);
11359 if (code == GE || code == GEU || code == LE || code == LEU || code == NE)
11360 {
11361 PUT_CODE (operands[1], reverse_condition (code));
11362 return "isel %0,%3,%2,%j1";
11363 }
11364 else
11365 return "isel %0,%2,%3,%j1";
11366}
11367
50a0b056 11368void
a2369ed3 11369rs6000_emit_minmax (rtx dest, enum rtx_code code, rtx op0, rtx op1)
50a0b056
GK		 11370{
11371 enum machine_mode mode = GET_MODE (op0);
5dc8d536 11372 enum rtx_code c;
50a0b056 11373 rtx target;
5dc8d536
AH		 11374
11375 if (code == SMAX || code == SMIN)
11376 c = GE;
11377 else
11378 c = GEU;
11379
50a0b056 11380 if (code == SMAX || code == UMAX)
f676971a 11381 target = emit_conditional_move (dest, c, op0, op1, mode,
50a0b056
GK		 11382 op0, op1, mode, 0);
11383 else
f676971a 11384 target = emit_conditional_move (dest, c, op0, op1, mode,
50a0b056 11385 op1, op0, mode, 0);
37409796 11386 gcc_assert (target);
50a0b056
GK		 11387 if (target != dest)
11388 emit_move_insn (dest, target);
11389}
46c07df8 11390
915167f5
GK		 11391/* Emit instructions to perform a load-reserved/store-conditional operation.
11392 The operation performed is an atomic
11393 (set M (CODE:MODE M OP))
11394 If not NULL, BEFORE is atomically set to M before the operation, and
11395 AFTER is set to M after the operation (that is, (CODE:MODE M OP)).
11396 If SYNC_P then a memory barrier is emitted before the operation.
11397 Either OP or M may be wrapped in a NOT operation. */
11398
11399void
11400rs6000_emit_sync (enum rtx_code code, enum machine_mode mode,
11401 rtx m, rtx op, rtx before_param, rtx after_param,
11402 bool sync_p)
11403{
11404 enum machine_mode used_mode;
11405 rtx the_op, set_before, set_after, set_atomic, cc_scratch, before, after;
11406 rtx used_m;
11407 rtvec vec;
11408 HOST_WIDE_INT imask = GET_MODE_MASK (mode);
11409 rtx shift = NULL_RTX;
11410
11411 if (sync_p)
11412 emit_insn (gen_memory_barrier ());
11413
11414 if (GET_CODE (m) == NOT)
11415 used_m = XEXP (m, 0);
11416 else
11417 used_m = m;
11418
11419 /* If this is smaller than SImode, we'll have to use SImode with
11420 adjustments. */
11421 if (mode == QImode || mode == HImode)
11422 {
11423 rtx newop, oldop;
11424
11425 if (MEM_ALIGN (used_m) >= 32)
11426 {
11427 int ishift = 0;
11428 if (BYTES_BIG_ENDIAN)
11429 ishift = GET_MODE_BITSIZE (SImode) - GET_MODE_BITSIZE (mode);
11430
11431 shift = GEN_INT (ishift);
11432 }
11433 else
11434 {
11435 rtx addrSI, aligned_addr;
a9c9d3fa 11436 int shift_mask = mode == QImode ? 0x18 : 0x10;
915167f5
GK		 11437
11438 addrSI = force_reg (SImode, gen_lowpart_common (SImode,
11439 XEXP (used_m, 0)));
11440 shift = gen_reg_rtx (SImode);
11441
11442 emit_insn (gen_rlwinm (shift, addrSI, GEN_INT (3),
a9c9d3fa
GK		 11443 GEN_INT (shift_mask)));
11444 emit_insn (gen_xorsi3 (shift, shift, GEN_INT (shift_mask)));
915167f5
GK		 11445
11446 aligned_addr = expand_binop (Pmode, and_optab,
11447 XEXP (used_m, 0),
11448 GEN_INT (-4), NULL_RTX,
11449 1, OPTAB_LIB_WIDEN);
11450 used_m = change_address (used_m, SImode, aligned_addr);
11451 set_mem_align (used_m, 32);
11452 /* It's safe to keep the old alias set of USED_M, because
11453 the operation is atomic and only affects the original
11454 USED_M. */
11455 if (GET_CODE (m) == NOT)
11456 m = gen_rtx_NOT (SImode, used_m);
11457 else
11458 m = used_m;
11459 }
11460
11461 if (GET_CODE (op) == NOT)
11462 {
11463 oldop = lowpart_subreg (SImode, XEXP (op, 0), mode);
11464 oldop = gen_rtx_NOT (SImode, oldop);
11465 }
11466 else
11467 oldop = lowpart_subreg (SImode, op, mode);
11468 switch (code)
11469 {
11470 case IOR:
11471 case XOR:
11472 newop = expand_binop (SImode, and_optab,
11473 oldop, GEN_INT (imask), NULL_RTX,
11474 1, OPTAB_LIB_WIDEN);
11475 emit_insn (gen_ashlsi3 (newop, newop, shift));
11476 break;
11477
11478 case AND:
11479 newop = expand_binop (SImode, ior_optab,
11480 oldop, GEN_INT (~imask), NULL_RTX,
11481 1, OPTAB_LIB_WIDEN);
a9c9d3fa 11482 emit_insn (gen_rotlsi3 (newop, newop, shift));
915167f5
GK		 11483 break;
11484
11485 case PLUS:
11486 {
11487 rtx mask;
11488
11489 newop = expand_binop (SImode, and_optab,
11490 oldop, GEN_INT (imask), NULL_RTX,
11491 1, OPTAB_LIB_WIDEN);
11492 emit_insn (gen_ashlsi3 (newop, newop, shift));
11493
11494 mask = gen_reg_rtx (SImode);
11495 emit_move_insn (mask, GEN_INT (imask));
11496 emit_insn (gen_ashlsi3 (mask, mask, shift));
11497
11498 newop = gen_rtx_AND (SImode, gen_rtx_PLUS (SImode, m, newop),
11499 mask);
11500 newop = gen_rtx_IOR (SImode, newop,
11501 gen_rtx_AND (SImode,
11502 gen_rtx_NOT (SImode, mask),
11503 m));
11504 break;
11505 }
11506
11507 default:
11508 gcc_unreachable ();
11509 }
11510
a9c9d3fa
GK		 11511 if (GET_CODE (m) == NOT)
11512 {
11513 rtx mask, xorm;
11514
11515 mask = gen_reg_rtx (SImode);
11516 emit_move_insn (mask, GEN_INT (imask));
11517 emit_insn (gen_ashlsi3 (mask, mask, shift));
11518
11519 xorm = gen_rtx_XOR (SImode, used_m, mask);
11520 /* Depending on the value of 'op', the XOR or the operation might
11521 be able to be simplified away. */
11522 newop = simplify_gen_binary (code, SImode, xorm, newop);
11523 }
915167f5
GK		 11524 op = newop;
11525 used_mode = SImode;
11526 before = gen_reg_rtx (used_mode);
11527 after = gen_reg_rtx (used_mode);
11528 }
11529 else
11530 {
11531 used_mode = mode;
11532 before = before_param;
11533 after = after_param;
11534
11535 if (before == NULL_RTX)
11536 before = gen_reg_rtx (used_mode);
11537 if (after == NULL_RTX)
11538 after = gen_reg_rtx (used_mode);
11539 }
11540
a9c9d3fa 11541 if ((code == PLUS || GET_CODE (m) == NOT) && used_mode != mode)
915167f5
GK		 11542 the_op = op; /* Computed above. */
11543 else if (GET_CODE (op) == NOT && GET_CODE (m) != NOT)
11544 the_op = gen_rtx_fmt_ee (code, used_mode, op, m);
11545 else
11546 the_op = gen_rtx_fmt_ee (code, used_mode, m, op);
11547
11548 set_after = gen_rtx_SET (VOIDmode, after, the_op);
11549 set_before = gen_rtx_SET (VOIDmode, before, used_m);
11550 set_atomic = gen_rtx_SET (VOIDmode, used_m,
11551 gen_rtx_UNSPEC (used_mode, gen_rtvec (1, the_op),
11552 UNSPEC_SYNC_OP));
11553 cc_scratch = gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (CCmode));
11554
11555 if (code == PLUS && used_mode != mode)
11556 vec = gen_rtvec (5, set_after, set_before, set_atomic, cc_scratch,
11557 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (SImode)));
11558 else
11559 vec = gen_rtvec (4, set_after, set_before, set_atomic, cc_scratch);
11560 emit_insn (gen_rtx_PARALLEL (VOIDmode, vec));
11561
11562 /* Shift and mask the return values properly. */
11563 if (used_mode != mode && before_param)
11564 {
11565 emit_insn (gen_lshrsi3 (before, before, shift));
11566 convert_move (before_param, before, 1);
11567 }
11568
11569 if (used_mode != mode && after_param)
11570 {
11571 emit_insn (gen_lshrsi3 (after, after, shift));
11572 convert_move (after_param, after, 1);
11573 }
11574
11575 /* The previous sequence will end with a branch that's dependent on
11576 the conditional store, so placing an isync will ensure that no
11577 other instructions (especially, no load or store instructions)
11578 can start before the atomic operation completes. */
11579 if (sync_p)
11580 emit_insn (gen_isync ());
11581}
11582
a9baceb1
GK		 11583/* Emit instructions to move SRC to DST. Called by splitters for
11584 multi-register moves. It will emit at most one instruction for
11585 each register that is accessed; that is, it won't emit li/lis pairs
11586 (or equivalent for 64-bit code). One of SRC or DST must be a hard
11587 register. */
46c07df8 11588
46c07df8 11589void
a9baceb1 11590rs6000_split_multireg_move (rtx dst, rtx src)
46c07df8 11591{
a9baceb1
GK		 11592 /* The register number of the first register being moved. */
11593 int reg;
11594 /* The mode that is to be moved. */
11595 enum machine_mode mode;
11596 /* The mode that the move is being done in, and its size. */
11597 enum machine_mode reg_mode;
11598 int reg_mode_size;
11599 /* The number of registers that will be moved. */
11600 int nregs;
11601
11602 reg = REG_P (dst) ? REGNO (dst) : REGNO (src);
11603 mode = GET_MODE (dst);
c8b622ff 11604 nregs = hard_regno_nregs[reg][mode];
a9baceb1
GK		 11605 if (FP_REGNO_P (reg))
11606 reg_mode = DFmode;
11607 else if (ALTIVEC_REGNO_P (reg))
11608 reg_mode = V16QImode;
11609 else
11610 reg_mode = word_mode;
11611 reg_mode_size = GET_MODE_SIZE (reg_mode);
f676971a 11612
37409796 11613 gcc_assert (reg_mode_size * nregs == GET_MODE_SIZE (mode));
f676971a 11614
a9baceb1
GK		 11615 if (REG_P (src) && REG_P (dst) && (REGNO (src) < REGNO (dst)))
11616 {
11617 /* Move register range backwards, if we might have destructive
11618 overlap. */
11619 int i;
11620 for (i = nregs - 1; i >= 0; i--)
f676971a 11621 emit_insn (gen_rtx_SET (VOIDmode,
a9baceb1
GK		 11622 simplify_gen_subreg (reg_mode, dst, mode,
11623 i * reg_mode_size),
11624 simplify_gen_subreg (reg_mode, src, mode,
11625 i * reg_mode_size)));
11626 }
46c07df8
HP		 11627 else
11628 {
a9baceb1
GK		 11629 int i;
11630 int j = -1;
11631 bool used_update = false;
46c07df8 11632
c1e55850 11633 if (MEM_P (src) && INT_REGNO_P (reg))
c4ad648e
AM		 11634 {
11635 rtx breg;
3a1f863f 11636
a9baceb1
GK		 11637 if (GET_CODE (XEXP (src, 0)) == PRE_INC
11638 || GET_CODE (XEXP (src, 0)) == PRE_DEC)
3a1f863f
DE		 11639 {
11640 rtx delta_rtx;
a9baceb1 11641 breg = XEXP (XEXP (src, 0), 0);
c4ad648e
AM		 11642 delta_rtx = (GET_CODE (XEXP (src, 0)) == PRE_INC
11643 ? GEN_INT (GET_MODE_SIZE (GET_MODE (src)))
11644 : GEN_INT (-GET_MODE_SIZE (GET_MODE (src))));
a9baceb1
GK		 11645 emit_insn (TARGET_32BIT
11646 ? gen_addsi3 (breg, breg, delta_rtx)
11647 : gen_adddi3 (breg, breg, delta_rtx));
3a1f863f
DE		 11648 src = gen_rtx_MEM (mode, breg);
11649 }
c1e55850
GK		 11650 else if (! offsettable_memref_p (src))
11651 {
11652 rtx newsrc, basereg;
11653 basereg = gen_rtx_REG (Pmode, reg);
11654 emit_insn (gen_rtx_SET (VOIDmode, basereg, XEXP (src, 0)));
11655 newsrc = gen_rtx_MEM (GET_MODE (src), basereg);
11656 MEM_COPY_ATTRIBUTES (newsrc, src);
11657 src = newsrc;
11658 }
3a1f863f 11659
0423421f
AM		 11660 breg = XEXP (src, 0);
11661 if (GET_CODE (breg) == PLUS || GET_CODE (breg) == LO_SUM)
11662 breg = XEXP (breg, 0);
11663
11664 /* If the base register we are using to address memory is
11665 also a destination reg, then change that register last. */
11666 if (REG_P (breg)
11667 && REGNO (breg) >= REGNO (dst)
3a1f863f
DE		 11668 && REGNO (breg) < REGNO (dst) + nregs)
11669 j = REGNO (breg) - REGNO (dst);
c4ad648e 11670 }
46c07df8 11671
a9baceb1 11672 if (GET_CODE (dst) == MEM && INT_REGNO_P (reg))
3a1f863f
DE		 11673 {
11674 rtx breg;
11675
a9baceb1
GK		 11676 if (GET_CODE (XEXP (dst, 0)) == PRE_INC
11677 || GET_CODE (XEXP (dst, 0)) == PRE_DEC)
3a1f863f
DE		 11678 {
11679 rtx delta_rtx;
a9baceb1 11680 breg = XEXP (XEXP (dst, 0), 0);
c4ad648e
AM		 11681 delta_rtx = (GET_CODE (XEXP (dst, 0)) == PRE_INC
11682 ? GEN_INT (GET_MODE_SIZE (GET_MODE (dst)))
11683 : GEN_INT (-GET_MODE_SIZE (GET_MODE (dst))));
3a1f863f
DE		 11684
11685 /* We have to update the breg before doing the store.
11686 Use store with update, if available. */
11687
11688 if (TARGET_UPDATE)
11689 {
a9baceb1 11690 rtx nsrc = simplify_gen_subreg (reg_mode, src, mode, 0);
c4ad648e
AM		 11691 emit_insn (TARGET_32BIT
11692 ? (TARGET_POWERPC64
11693 ? gen_movdi_si_update (breg, breg, delta_rtx, nsrc)
11694 : gen_movsi_update (breg, breg, delta_rtx, nsrc))
11695 : gen_movdi_di_update (breg, breg, delta_rtx, nsrc));
a9baceb1 11696 used_update = true;
3a1f863f
DE		 11697 }
11698 else
a9baceb1
GK		 11699 emit_insn (TARGET_32BIT
11700 ? gen_addsi3 (breg, breg, delta_rtx)
11701 : gen_adddi3 (breg, breg, delta_rtx));
3a1f863f
DE		 11702 dst = gen_rtx_MEM (mode, breg);
11703 }
37409796
NS		 11704 else
11705 gcc_assert (offsettable_memref_p (dst));
3a1f863f
DE		 11706 }
11707
46c07df8 11708 for (i = 0; i < nregs; i++)
f676971a 11709 {
3a1f863f
DE		 11710 /* Calculate index to next subword. */
11711 ++j;
f676971a 11712 if (j == nregs)
3a1f863f 11713 j = 0;
46c07df8 11714
112cdef5 11715 /* If compiler already emitted move of first word by
a9baceb1 11716 store with update, no need to do anything. */
3a1f863f 11717 if (j == 0 && used_update)
a9baceb1 11718 continue;
f676971a 11719
a9baceb1
GK		 11720 emit_insn (gen_rtx_SET (VOIDmode,
11721 simplify_gen_subreg (reg_mode, dst, mode,
11722 j * reg_mode_size),
11723 simplify_gen_subreg (reg_mode, src, mode,
11724 j * reg_mode_size)));
3a1f863f 11725 }
46c07df8
HP		 11726 }
11727}
11728
12a4e8c5 11729\f
a4f6c312
SS		 11730/* This page contains routines that are used to determine what the
11731 function prologue and epilogue code will do and write them out. */
9878760c 11732
a4f6c312
SS		 11733/* Return the first fixed-point register that is required to be
11734 saved. 32 if none. */
9878760c
RK		 11735
11736int
863d938c 11737first_reg_to_save (void)
9878760c
RK		 11738{
11739 int first_reg;
11740
11741 /* Find lowest numbered live register. */
11742 for (first_reg = 13; first_reg <= 31; first_reg++)
f676971a 11743 if (regs_ever_live[first_reg]
a38d360d 11744 && (! call_used_regs[first_reg]
1db02437 11745 || (first_reg == RS6000_PIC_OFFSET_TABLE_REGNUM
14f00213 11746 && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0)
b4db40bf
JJ		 11747 || (DEFAULT_ABI == ABI_DARWIN && flag_pic)
11748 || (TARGET_TOC && TARGET_MINIMAL_TOC)))))
9878760c
RK		 11749 break;
11750
ee890fe2 11751#if TARGET_MACHO
93638d7a
AM		 11752 if (flag_pic
11753 && current_function_uses_pic_offset_table
11754 && first_reg > RS6000_PIC_OFFSET_TABLE_REGNUM)
1db02437 11755 return RS6000_PIC_OFFSET_TABLE_REGNUM;
ee890fe2
SS		 11756#endif
11757
9878760c
RK		 11758 return first_reg;
11759}
11760
11761/* Similar, for FP regs. */
11762
11763int
863d938c 11764first_fp_reg_to_save (void)
9878760c
RK		 11765{
11766 int first_reg;
11767
11768 /* Find lowest numbered live register. */
11769 for (first_reg = 14 + 32; first_reg <= 63; first_reg++)
11770 if (regs_ever_live[first_reg])
11771 break;
11772
11773 return first_reg;
11774}
00b960c7
AH		 11775
11776/* Similar, for AltiVec regs. */
11777
11778static int
863d938c 11779first_altivec_reg_to_save (void)
00b960c7
AH		 11780{
11781 int i;
11782
11783 /* Stack frame remains as is unless we are in AltiVec ABI. */
11784 if (! TARGET_ALTIVEC_ABI)
11785 return LAST_ALTIVEC_REGNO + 1;
11786
11787 /* Find lowest numbered live register. */
11788 for (i = FIRST_ALTIVEC_REGNO + 20; i <= LAST_ALTIVEC_REGNO; ++i)
11789 if (regs_ever_live[i])
11790 break;
11791
11792 return i;
11793}
11794
11795/* Return a 32-bit mask of the AltiVec registers we need to set in
11796 VRSAVE. Bit n of the return value is 1 if Vn is live. The MSB in
11797 the 32-bit word is 0. */
11798
11799static unsigned int
863d938c 11800compute_vrsave_mask (void)
00b960c7
AH		 11801{
11802 unsigned int i, mask = 0;
11803
11804 /* First, find out if we use _any_ altivec registers. */
11805 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
11806 if (regs_ever_live[i])
11807 mask |= ALTIVEC_REG_BIT (i);
11808
11809 if (mask == 0)
11810 return mask;
11811
00b960c7
AH		 11812 /* Next, remove the argument registers from the set. These must
11813 be in the VRSAVE mask set by the caller, so we don't need to add
11814 them in again. More importantly, the mask we compute here is
11815 used to generate CLOBBERs in the set_vrsave insn, and we do not
11816 wish the argument registers to die. */
a6cf80f2 11817 for (i = cfun->args_info.vregno - 1; i >= ALTIVEC_ARG_MIN_REG; --i)
00b960c7
AH		 11818 mask &= ~ALTIVEC_REG_BIT (i);
11819
11820 /* Similarly, remove the return value from the set. */
11821 {
11822 bool yes = false;
11823 diddle_return_value (is_altivec_return_reg, &yes);
11824 if (yes)
11825 mask &= ~ALTIVEC_REG_BIT (ALTIVEC_ARG_RETURN);
11826 }
11827
11828 return mask;
11829}
11830
d62294f5 11831/* For a very restricted set of circumstances, we can cut down the
f57fe068
AM		 11832 size of prologues/epilogues by calling our own save/restore-the-world
11833 routines. */
d62294f5
FJ		 11834
11835static void
f57fe068
AM		 11836compute_save_world_info (rs6000_stack_t *info_ptr)
11837{
11838 info_ptr->world_save_p = 1;
11839 info_ptr->world_save_p
11840 = (WORLD_SAVE_P (info_ptr)
11841 && DEFAULT_ABI == ABI_DARWIN
11842 && ! (current_function_calls_setjmp && flag_exceptions)
11843 && info_ptr->first_fp_reg_save == FIRST_SAVED_FP_REGNO
11844 && info_ptr->first_gp_reg_save == FIRST_SAVED_GP_REGNO
11845 && info_ptr->first_altivec_reg_save == FIRST_SAVED_ALTIVEC_REGNO
11846 && info_ptr->cr_save_p);
f676971a 11847
d62294f5
FJ		 11848 /* This will not work in conjunction with sibcalls. Make sure there
11849 are none. (This check is expensive, but seldom executed.) */
f57fe068 11850 if (WORLD_SAVE_P (info_ptr))
f676971a 11851 {
d62294f5
FJ		 11852 rtx insn;
11853 for ( insn = get_last_insn_anywhere (); insn; insn = PREV_INSN (insn))
c4ad648e
AM		 11854 if ( GET_CODE (insn) == CALL_INSN
11855 && SIBLING_CALL_P (insn))
11856 {
11857 info_ptr->world_save_p = 0;
11858 break;
11859 }
d62294f5 11860 }
f676971a 11861
f57fe068 11862 if (WORLD_SAVE_P (info_ptr))
d62294f5
FJ		 11863 {
11864 /* Even if we're not touching VRsave, make sure there's room on the
11865 stack for it, if it looks like we're calling SAVE_WORLD, which
c4ad648e 11866 will attempt to save it. */
d62294f5
FJ		 11867 info_ptr->vrsave_size = 4;
11868
11869 /* "Save" the VRsave register too if we're saving the world. */
11870 if (info_ptr->vrsave_mask == 0)
c4ad648e 11871 info_ptr->vrsave_mask = compute_vrsave_mask ();
d62294f5
FJ		 11872
11873 /* Because the Darwin register save/restore routines only handle
c4ad648e 11874 F14 .. F31 and V20 .. V31 as per the ABI, perform a consistency
992d08b1 11875 check. */
37409796
NS		 11876 gcc_assert (info_ptr->first_fp_reg_save >= FIRST_SAVED_FP_REGNO
11877 && (info_ptr->first_altivec_reg_save
11878 >= FIRST_SAVED_ALTIVEC_REGNO));
d62294f5 11879 }
f676971a 11880 return;
d62294f5
FJ		 11881}
11882
11883
00b960c7 11884static void
a2369ed3 11885is_altivec_return_reg (rtx reg, void *xyes)
00b960c7
AH		 11886{
11887 bool *yes = (bool *) xyes;
11888 if (REGNO (reg) == ALTIVEC_ARG_RETURN)
11889 *yes = true;
11890}
11891
4697a36c
MM		 11892\f
11893/* Calculate the stack information for the current function. This is
11894 complicated by having two separate calling sequences, the AIX calling
11895 sequence and the V.4 calling sequence.
11896
592696dd 11897 AIX (and Darwin/Mac OS X) stack frames look like:
a260abc9 11898 32-bit 64-bit
4697a36c 11899 SP----> +---------------------------------------+
a260abc9 11900 | back chain to caller | 0 0
4697a36c 11901 +---------------------------------------+
a260abc9 11902 | saved CR | 4 8 (8-11)
4697a36c 11903 +---------------------------------------+
a260abc9 11904 | saved LR | 8 16
4697a36c 11905 +---------------------------------------+
a260abc9 11906 | reserved for compilers | 12 24
4697a36c 11907 +---------------------------------------+
a260abc9 11908 | reserved for binders | 16 32
4697a36c 11909 +---------------------------------------+
a260abc9 11910 | saved TOC pointer | 20 40
4697a36c 11911 +---------------------------------------+
a260abc9 11912 | Parameter save area (P) | 24 48
4697a36c 11913 +---------------------------------------+
a260abc9 11914 | Alloca space (A) | 24+P etc.
802a0058 11915 +---------------------------------------+
a7df97e6 11916 | Local variable space (L) | 24+P+A
4697a36c 11917 +---------------------------------------+
a7df97e6 11918 | Float/int conversion temporary (X) | 24+P+A+L
4697a36c 11919 +---------------------------------------+
00b960c7
AH		 11920 | Save area for AltiVec registers (W) | 24+P+A+L+X
11921 +---------------------------------------+
11922 | AltiVec alignment padding (Y) | 24+P+A+L+X+W
11923 +---------------------------------------+
11924 | Save area for VRSAVE register (Z) | 24+P+A+L+X+W+Y
4697a36c 11925 +---------------------------------------+
00b960c7
AH		 11926 | Save area for GP registers (G) | 24+P+A+X+L+X+W+Y+Z
11927 +---------------------------------------+
11928 | Save area for FP registers (F) | 24+P+A+X+L+X+W+Y+Z+G
4697a36c
MM		 11929 +---------------------------------------+
11930 old SP->| back chain to caller's caller |
11931 +---------------------------------------+
11932
5376a30c
KR		 11933 The required alignment for AIX configurations is two words (i.e., 8
11934 or 16 bytes).
11935
11936
4697a36c
MM		 11937 V.4 stack frames look like:
11938
11939 SP----> +---------------------------------------+
11940 | back chain to caller | 0
11941 +---------------------------------------+
5eb387b8 11942 | caller's saved LR | 4
4697a36c
MM		 11943 +---------------------------------------+
11944 | Parameter save area (P) | 8
11945 +---------------------------------------+
a7df97e6 11946 | Alloca space (A) | 8+P
f676971a 11947 +---------------------------------------+
a7df97e6 11948 | Varargs save area (V) | 8+P+A
f676971a 11949 +---------------------------------------+
a7df97e6 11950 | Local variable space (L) | 8+P+A+V
f676971a 11951 +---------------------------------------+
a7df97e6 11952 | Float/int conversion temporary (X) | 8+P+A+V+L
4697a36c 11953 +---------------------------------------+
00b960c7
AH		 11954 | Save area for AltiVec registers (W) | 8+P+A+V+L+X
11955 +---------------------------------------+
11956 | AltiVec alignment padding (Y) | 8+P+A+V+L+X+W
11957 +---------------------------------------+
11958 | Save area for VRSAVE register (Z) | 8+P+A+V+L+X+W+Y
11959 +---------------------------------------+
c4ad648e
AM		 11960 | SPE: area for 64-bit GP registers |
11961 +---------------------------------------+
11962 | SPE alignment padding |
11963 +---------------------------------------+
00b960c7 11964 | saved CR (C) | 8+P+A+V+L+X+W+Y+Z
f676971a 11965 +---------------------------------------+
00b960c7 11966 | Save area for GP registers (G) | 8+P+A+V+L+X+W+Y+Z+C
f676971a 11967 +---------------------------------------+
00b960c7 11968 | Save area for FP registers (F) | 8+P+A+V+L+X+W+Y+Z+C+G
4697a36c
MM		 11969 +---------------------------------------+
11970 old SP->| back chain to caller's caller |
11971 +---------------------------------------+
b6c9286a 11972
5376a30c
KR		 11973 The required alignment for V.4 is 16 bytes, or 8 bytes if -meabi is
11974 given. (But note below and in sysv4.h that we require only 8 and
11975 may round up the size of our stack frame anyways. The historical
11976 reason is early versions of powerpc-linux which didn't properly
11977 align the stack at program startup. A happy side-effect is that
11978 -mno-eabi libraries can be used with -meabi programs.)
11979
50d440bc 11980 The EABI configuration defaults to the V.4 layout. However,
5376a30c
KR		 11981 the stack alignment requirements may differ. If -mno-eabi is not
11982 given, the required stack alignment is 8 bytes; if -mno-eabi is
11983 given, the required alignment is 16 bytes. (But see V.4 comment
11984 above.) */
4697a36c 11985
61b2fbe7
MM		 11986#ifndef ABI_STACK_BOUNDARY
11987#define ABI_STACK_BOUNDARY STACK_BOUNDARY
11988#endif
11989
d1d0c603 11990static rs6000_stack_t *
863d938c 11991rs6000_stack_info (void)
4697a36c
MM		 11992{
11993 static rs6000_stack_t info, zero_info;
11994 rs6000_stack_t *info_ptr = &info;
327e5343 11995 int reg_size = TARGET_32BIT ? 4 : 8;
83720594 11996 int ehrd_size;
64045029 11997 int save_align;
44688022 11998 HOST_WIDE_INT non_fixed_size;
4697a36c 11999
a4f6c312 12000 /* Zero all fields portably. */
4697a36c
MM		 12001 info = zero_info;
12002
c19de7aa
AH		 12003 if (TARGET_SPE)
12004 {
12005 /* Cache value so we don't rescan instruction chain over and over. */
9b7b447f 12006 if (cfun->machine->insn_chain_scanned_p == 0)
b5a5beb9
AH		 12007 cfun->machine->insn_chain_scanned_p
12008 = spe_func_has_64bit_regs_p () + 1;
12009 info_ptr->spe_64bit_regs_used = cfun->machine->insn_chain_scanned_p - 1;
c19de7aa
AH		 12010 }
12011
a4f6c312 12012 /* Select which calling sequence. */
178274da 12013 info_ptr->abi = DEFAULT_ABI;
9878760c 12014
a4f6c312 12015 /* Calculate which registers need to be saved & save area size. */
4697a36c 12016 info_ptr->first_gp_reg_save = first_reg_to_save ();
f676971a 12017 /* Assume that we will have to save RS6000_PIC_OFFSET_TABLE_REGNUM,
906fb125 12018 even if it currently looks like we won't. */
2bfcf297 12019 if (((TARGET_TOC && TARGET_MINIMAL_TOC)
178274da
AM		 12020 || (flag_pic == 1 && DEFAULT_ABI == ABI_V4)
12021 || (flag_pic && DEFAULT_ABI == ABI_DARWIN))
1db02437
FS		 12022 && info_ptr->first_gp_reg_save > RS6000_PIC_OFFSET_TABLE_REGNUM)
12023 info_ptr->gp_size = reg_size * (32 - RS6000_PIC_OFFSET_TABLE_REGNUM);
906fb125
GK		 12024 else
12025 info_ptr->gp_size = reg_size * (32 - info_ptr->first_gp_reg_save);
4697a36c 12026
a3170dc6
AH		 12027 /* For the SPE, we have an additional upper 32-bits on each GPR.
12028 Ideally we should save the entire 64-bits only when the upper
12029 half is used in SIMD instructions. Since we only record
12030 registers live (not the size they are used in), this proves
12031 difficult because we'd have to traverse the instruction chain at
12032 the right time, taking reload into account. This is a real pain,
c19de7aa
AH		 12033 so we opt to save the GPRs in 64-bits always if but one register
12034 gets used in 64-bits. Otherwise, all the registers in the frame
12035 get saved in 32-bits.
a3170dc6 12036
c19de7aa 12037 So... since when we save all GPRs (except the SP) in 64-bits, the
a3170dc6 12038 traditional GP save area will be empty. */
c19de7aa 12039 if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
a3170dc6
AH		 12040 info_ptr->gp_size = 0;
12041
4697a36c
MM		 12042 info_ptr->first_fp_reg_save = first_fp_reg_to_save ();
12043 info_ptr->fp_size = 8 * (64 - info_ptr->first_fp_reg_save);
12044
00b960c7
AH		 12045 info_ptr->first_altivec_reg_save = first_altivec_reg_to_save ();
12046 info_ptr->altivec_size = 16 * (LAST_ALTIVEC_REGNO + 1
12047 - info_ptr->first_altivec_reg_save);
12048
592696dd 12049 /* Does this function call anything? */
71f123ca
FS		 12050 info_ptr->calls_p = (! current_function_is_leaf
12051 || cfun->machine->ra_needs_full_frame);
b6c9286a 12052
a4f6c312 12053 /* Determine if we need to save the link register. */
71f123ca 12054 if (rs6000_ra_ever_killed ()
ffcfcb5f
AM		 12055 || (DEFAULT_ABI == ABI_AIX
12056 && current_function_profile
12057 && !TARGET_PROFILE_KERNEL)
4697a36c
MM		 12058#ifdef TARGET_RELOCATABLE
12059 || (TARGET_RELOCATABLE && (get_pool_size () != 0))
12060#endif
12061 || (info_ptr->first_fp_reg_save != 64
12062 && !FP_SAVE_INLINE (info_ptr->first_fp_reg_save))
00b960c7 12063 || info_ptr->first_altivec_reg_save <= LAST_ALTIVEC_REGNO
178274da 12064 || (DEFAULT_ABI == ABI_V4 && current_function_calls_alloca)
4697a36c
MM		 12065 || info_ptr->calls_p)
12066 {
12067 info_ptr->lr_save_p = 1;
9ebbca7d 12068 regs_ever_live[LINK_REGISTER_REGNUM] = 1;
4697a36c
MM		 12069 }
12070
9ebbca7d 12071 /* Determine if we need to save the condition code registers. */
f676971a 12072 if (regs_ever_live[CR2_REGNO]
9ebbca7d
GK		 12073 || regs_ever_live[CR3_REGNO]
12074 || regs_ever_live[CR4_REGNO])
4697a36c
MM		 12075 {
12076 info_ptr->cr_save_p = 1;
178274da 12077 if (DEFAULT_ABI == ABI_V4)
4697a36c
MM		 12078 info_ptr->cr_size = reg_size;
12079 }
12080
83720594
RH		 12081 /* If the current function calls __builtin_eh_return, then we need
12082 to allocate stack space for registers that will hold data for
12083 the exception handler. */
12084 if (current_function_calls_eh_return)
12085 {
12086 unsigned int i;
12087 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; ++i)
12088 continue;
a3170dc6
AH		 12089
12090 /* SPE saves EH registers in 64-bits. */
c19de7aa
AH		 12091 ehrd_size = i * (TARGET_SPE_ABI
12092 && info_ptr->spe_64bit_regs_used != 0
12093 ? UNITS_PER_SPE_WORD : UNITS_PER_WORD);
83720594
RH		 12094 }
12095 else
12096 ehrd_size = 0;
12097
592696dd 12098 /* Determine various sizes. */
4697a36c
MM		 12099 info_ptr->reg_size = reg_size;
12100 info_ptr->fixed_size = RS6000_SAVE_AREA;
12101 info_ptr->varargs_size = RS6000_VARARGS_AREA;
189e03e3 12102 info_ptr->vars_size = RS6000_ALIGN (get_frame_size (), 8);
a4f6c312 12103 info_ptr->parm_size = RS6000_ALIGN (current_function_outgoing_args_size,
03e007d7 12104 TARGET_ALTIVEC ? 16 : 8);
00b960c7 12105
c19de7aa 12106 if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
a3170dc6
AH		 12107 info_ptr->spe_gp_size = 8 * (32 - info_ptr->first_gp_reg_save);
12108 else
12109 info_ptr->spe_gp_size = 0;
12110
4d774ff8
HP		 12111 if (TARGET_ALTIVEC_ABI)
12112 info_ptr->vrsave_mask = compute_vrsave_mask ();
00b960c7 12113 else
4d774ff8
HP		 12114 info_ptr->vrsave_mask = 0;
12115
12116 if (TARGET_ALTIVEC_VRSAVE && info_ptr->vrsave_mask)
12117 info_ptr->vrsave_size = 4;
12118 else
12119 info_ptr->vrsave_size = 0;
b6c9286a 12120
d62294f5
FJ		 12121 compute_save_world_info (info_ptr);
12122
592696dd 12123 /* Calculate the offsets. */
178274da 12124 switch (DEFAULT_ABI)
4697a36c 12125 {
b6c9286a 12126 case ABI_NONE:
24d304eb 12127 default:
37409796 12128 gcc_unreachable ();
b6c9286a
MM		 12129
12130 case ABI_AIX:
ee890fe2 12131 case ABI_DARWIN:
b6c9286a
MM		 12132 info_ptr->fp_save_offset = - info_ptr->fp_size;
12133 info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size;
00b960c7
AH		 12134
12135 if (TARGET_ALTIVEC_ABI)
12136 {
12137 info_ptr->vrsave_save_offset
12138 = info_ptr->gp_save_offset - info_ptr->vrsave_size;
12139
12140 /* Align stack so vector save area is on a quadword boundary. */
12141 if (info_ptr->altivec_size != 0)
12142 info_ptr->altivec_padding_size
12143 = 16 - (-info_ptr->vrsave_save_offset % 16);
12144 else
12145 info_ptr->altivec_padding_size = 0;
12146
12147 info_ptr->altivec_save_offset
12148 = info_ptr->vrsave_save_offset
12149 - info_ptr->altivec_padding_size
12150 - info_ptr->altivec_size;
12151
12152 /* Adjust for AltiVec case. */
12153 info_ptr->ehrd_offset = info_ptr->altivec_save_offset - ehrd_size;
12154 }
12155 else
12156 info_ptr->ehrd_offset = info_ptr->gp_save_offset - ehrd_size;
a260abc9
DE		 12157 info_ptr->cr_save_offset = reg_size; /* first word when 64-bit. */
12158 info_ptr->lr_save_offset = 2*reg_size;
24d304eb
RK		 12159 break;
12160
12161 case ABI_V4:
b6c9286a
MM		 12162 info_ptr->fp_save_offset = - info_ptr->fp_size;
12163 info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size;
a7df97e6 12164 info_ptr->cr_save_offset = info_ptr->gp_save_offset - info_ptr->cr_size;
00b960c7 12165
c19de7aa 12166 if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
c4ad648e
AM		 12167 {
12168 /* Align stack so SPE GPR save area is aligned on a
12169 double-word boundary. */
12170 if (info_ptr->spe_gp_size != 0)
12171 info_ptr->spe_padding_size
12172 = 8 - (-info_ptr->cr_save_offset % 8);
12173 else
12174 info_ptr->spe_padding_size = 0;
12175
12176 info_ptr->spe_gp_save_offset
12177 = info_ptr->cr_save_offset
12178 - info_ptr->spe_padding_size
12179 - info_ptr->spe_gp_size;
12180
12181 /* Adjust for SPE case. */
12182 info_ptr->toc_save_offset
12183 = info_ptr->spe_gp_save_offset - info_ptr->toc_size;
12184 }
a3170dc6 12185 else if (TARGET_ALTIVEC_ABI)
00b960c7
AH		 12186 {
12187 info_ptr->vrsave_save_offset
12188 = info_ptr->cr_save_offset - info_ptr->vrsave_size;
12189
12190 /* Align stack so vector save area is on a quadword boundary. */
12191 if (info_ptr->altivec_size != 0)
12192 info_ptr->altivec_padding_size
12193 = 16 - (-info_ptr->vrsave_save_offset % 16);
12194 else
12195 info_ptr->altivec_padding_size = 0;
12196
12197 info_ptr->altivec_save_offset
12198 = info_ptr->vrsave_save_offset
12199 - info_ptr->altivec_padding_size
12200 - info_ptr->altivec_size;
12201
12202 /* Adjust for AltiVec case. */
12203 info_ptr->toc_save_offset
12204 = info_ptr->altivec_save_offset - info_ptr->toc_size;
12205 }
12206 else
12207 info_ptr->toc_save_offset = info_ptr->cr_save_offset - info_ptr->toc_size;
83720594 12208 info_ptr->ehrd_offset = info_ptr->toc_save_offset - ehrd_size;
b6c9286a
MM		 12209 info_ptr->lr_save_offset = reg_size;
12210 break;
4697a36c
MM		 12211 }
12212
64045029 12213 save_align = (TARGET_ALTIVEC_ABI || DEFAULT_ABI == ABI_DARWIN) ? 16 : 8;
00b960c7
AH		 12214 info_ptr->save_size = RS6000_ALIGN (info_ptr->fp_size
12215 + info_ptr->gp_size
12216 + info_ptr->altivec_size
12217 + info_ptr->altivec_padding_size
a3170dc6
AH		 12218 + info_ptr->spe_gp_size
12219 + info_ptr->spe_padding_size
00b960c7
AH		 12220 + ehrd_size
12221 + info_ptr->cr_size
12222 + info_ptr->lr_size
12223 + info_ptr->vrsave_size
12224 + info_ptr->toc_size,
64045029 12225 save_align);
00b960c7 12226
44688022 12227 non_fixed_size = (info_ptr->vars_size
ff381587 12228 + info_ptr->parm_size
ff381587 12229 + info_ptr->save_size
44688022 12230 + info_ptr->varargs_size);
ff381587 12231
44688022
AM		 12232 info_ptr->total_size = RS6000_ALIGN (non_fixed_size + info_ptr->fixed_size,
12233 ABI_STACK_BOUNDARY / BITS_PER_UNIT);
ff381587
MM		 12234
12235 /* Determine if we need to allocate any stack frame:
12236
a4f6c312
SS		 12237 For AIX we need to push the stack if a frame pointer is needed
12238 (because the stack might be dynamically adjusted), if we are
12239 debugging, if we make calls, or if the sum of fp_save, gp_save,
12240 and local variables are more than the space needed to save all
12241 non-volatile registers: 32-bit: 18*8 + 19*4 = 220 or 64-bit: 18*8
12242 + 18*8 = 288 (GPR13 reserved).
ff381587 12243
a4f6c312
SS		 12244 For V.4 we don't have the stack cushion that AIX uses, but assume
12245 that the debugger can handle stackless frames. */
ff381587
MM		 12246
12247 if (info_ptr->calls_p)
12248 info_ptr->push_p = 1;
12249
178274da 12250 else if (DEFAULT_ABI == ABI_V4)
44688022 12251 info_ptr->push_p = non_fixed_size != 0;
ff381587 12252
178274da
AM		 12253 else if (frame_pointer_needed)
12254 info_ptr->push_p = 1;
12255
12256 else if (TARGET_XCOFF && write_symbols != NO_DEBUG)
12257 info_ptr->push_p = 1;
12258
ff381587 12259 else
44688022 12260 info_ptr->push_p = non_fixed_size > (TARGET_32BIT ? 220 : 288);
ff381587 12261
a4f6c312 12262 /* Zero offsets if we're not saving those registers. */
8dda1a21 12263 if (info_ptr->fp_size == 0)
4697a36c
MM		 12264 info_ptr->fp_save_offset = 0;
12265
8dda1a21 12266 if (info_ptr->gp_size == 0)
4697a36c
MM		 12267 info_ptr->gp_save_offset = 0;
12268
00b960c7
AH		 12269 if (! TARGET_ALTIVEC_ABI || info_ptr->altivec_size == 0)
12270 info_ptr->altivec_save_offset = 0;
12271
12272 if (! TARGET_ALTIVEC_ABI || info_ptr->vrsave_mask == 0)
12273 info_ptr->vrsave_save_offset = 0;
12274
c19de7aa
AH		 12275 if (! TARGET_SPE_ABI
12276 || info_ptr->spe_64bit_regs_used == 0
12277 || info_ptr->spe_gp_size == 0)
a3170dc6
AH		 12278 info_ptr->spe_gp_save_offset = 0;
12279
c81fc13e 12280 if (! info_ptr->lr_save_p)
4697a36c
MM		 12281 info_ptr->lr_save_offset = 0;
12282
c81fc13e 12283 if (! info_ptr->cr_save_p)
4697a36c
MM		 12284 info_ptr->cr_save_offset = 0;
12285
c81fc13e 12286 if (! info_ptr->toc_save_p)
b6c9286a
MM		 12287 info_ptr->toc_save_offset = 0;
12288
4697a36c
MM		 12289 return info_ptr;
12290}
12291
c19de7aa
AH		 12292/* Return true if the current function uses any GPRs in 64-bit SIMD
12293 mode. */
12294
12295static bool
863d938c 12296spe_func_has_64bit_regs_p (void)
c19de7aa
AH		 12297{
12298 rtx insns, insn;
12299
12300 /* Functions that save and restore all the call-saved registers will
12301 need to save/restore the registers in 64-bits. */
12302 if (current_function_calls_eh_return
12303 || current_function_calls_setjmp
12304 || current_function_has_nonlocal_goto)
12305 return true;
12306
12307 insns = get_insns ();
12308
12309 for (insn = NEXT_INSN (insns); insn != NULL_RTX; insn = NEXT_INSN (insn))
12310 {
12311 if (INSN_P (insn))
12312 {
12313 rtx i;
12314
b5a5beb9
AH		 12315 /* FIXME: This should be implemented with attributes...
12316
12317 (set_attr "spe64" "true")....then,
12318 if (get_spe64(insn)) return true;
12319
12320 It's the only reliable way to do the stuff below. */
12321
c19de7aa 12322 i = PATTERN (insn);
f82f556d
AH		 12323 if (GET_CODE (i) == SET)
12324 {
12325 enum machine_mode mode = GET_MODE (SET_SRC (i));
12326
12327 if (SPE_VECTOR_MODE (mode))
12328 return true;
12329 if (TARGET_E500_DOUBLE && mode == DFmode)
12330 return true;
12331 }
c19de7aa
AH		 12332 }
12333 }
12334
12335 return false;
12336}
12337
d1d0c603 12338static void
a2369ed3 12339debug_stack_info (rs6000_stack_t *info)
9878760c 12340{
d330fd93 12341 const char *abi_string;
24d304eb 12342
c81fc13e 12343 if (! info)
4697a36c
MM		 12344 info = rs6000_stack_info ();
12345
12346 fprintf (stderr, "\nStack information for function %s:\n",
12347 ((current_function_decl && DECL_NAME (current_function_decl))
12348 ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl))
12349 : "<unknown>"));
12350
24d304eb
RK		 12351 switch (info->abi)
12352 {
b6c9286a
MM		 12353 default: abi_string = "Unknown"; break;
12354 case ABI_NONE: abi_string = "NONE"; break;
50d440bc 12355 case ABI_AIX: abi_string = "AIX"; break;
ee890fe2 12356 case ABI_DARWIN: abi_string = "Darwin"; break;
b6c9286a 12357 case ABI_V4: abi_string = "V.4"; break;
24d304eb
RK		 12358 }
12359
12360 fprintf (stderr, "\tABI = %5s\n", abi_string);
12361
00b960c7
AH		 12362 if (TARGET_ALTIVEC_ABI)
12363 fprintf (stderr, "\tALTIVEC ABI extensions enabled.\n");
12364
a3170dc6
AH		 12365 if (TARGET_SPE_ABI)
12366 fprintf (stderr, "\tSPE ABI extensions enabled.\n");
12367
4697a36c
MM		 12368 if (info->first_gp_reg_save != 32)
12369 fprintf (stderr, "\tfirst_gp_reg_save = %5d\n", info->first_gp_reg_save);
12370
12371 if (info->first_fp_reg_save != 64)
12372 fprintf (stderr, "\tfirst_fp_reg_save = %5d\n", info->first_fp_reg_save);
9878760c 12373
00b960c7
AH		 12374 if (info->first_altivec_reg_save <= LAST_ALTIVEC_REGNO)
12375 fprintf (stderr, "\tfirst_altivec_reg_save = %5d\n",
12376 info->first_altivec_reg_save);
12377
4697a36c
MM		 12378 if (info->lr_save_p)
12379 fprintf (stderr, "\tlr_save_p = %5d\n", info->lr_save_p);
9878760c 12380
4697a36c
MM		 12381 if (info->cr_save_p)
12382 fprintf (stderr, "\tcr_save_p = %5d\n", info->cr_save_p);
12383
b6c9286a
MM		 12384 if (info->toc_save_p)
12385 fprintf (stderr, "\ttoc_save_p = %5d\n", info->toc_save_p);
12386
00b960c7
AH		 12387 if (info->vrsave_mask)
12388 fprintf (stderr, "\tvrsave_mask = 0x%x\n", info->vrsave_mask);
12389
4697a36c
MM		 12390 if (info->push_p)
12391 fprintf (stderr, "\tpush_p = %5d\n", info->push_p);
12392
12393 if (info->calls_p)
12394 fprintf (stderr, "\tcalls_p = %5d\n", info->calls_p);
12395
4697a36c
MM		 12396 if (info->gp_save_offset)
12397 fprintf (stderr, "\tgp_save_offset = %5d\n", info->gp_save_offset);
12398
12399 if (info->fp_save_offset)
12400 fprintf (stderr, "\tfp_save_offset = %5d\n", info->fp_save_offset);
12401
00b960c7
AH		 12402 if (info->altivec_save_offset)
12403 fprintf (stderr, "\taltivec_save_offset = %5d\n",
12404 info->altivec_save_offset);
12405
a3170dc6
AH		 12406 if (info->spe_gp_save_offset)
12407 fprintf (stderr, "\tspe_gp_save_offset = %5d\n",
12408 info->spe_gp_save_offset);
12409
00b960c7
AH		 12410 if (info->vrsave_save_offset)
12411 fprintf (stderr, "\tvrsave_save_offset = %5d\n",
12412 info->vrsave_save_offset);
12413
4697a36c
MM		 12414 if (info->lr_save_offset)
12415 fprintf (stderr, "\tlr_save_offset = %5d\n", info->lr_save_offset);
12416
12417 if (info->cr_save_offset)
12418 fprintf (stderr, "\tcr_save_offset = %5d\n", info->cr_save_offset);
12419
b6c9286a
MM		 12420 if (info->toc_save_offset)
12421 fprintf (stderr, "\ttoc_save_offset = %5d\n", info->toc_save_offset);
12422
4697a36c
MM		 12423 if (info->varargs_save_offset)
12424 fprintf (stderr, "\tvarargs_save_offset = %5d\n", info->varargs_save_offset);
12425
12426 if (info->total_size)
d1d0c603
JJ		 12427 fprintf (stderr, "\ttotal_size = "HOST_WIDE_INT_PRINT_DEC"\n",
12428 info->total_size);
4697a36c
MM		 12429
12430 if (info->varargs_size)
12431 fprintf (stderr, "\tvarargs_size = %5d\n", info->varargs_size);
12432
12433 if (info->vars_size)
d1d0c603
JJ		 12434 fprintf (stderr, "\tvars_size = "HOST_WIDE_INT_PRINT_DEC"\n",
12435 info->vars_size);
4697a36c
MM		 12436
12437 if (info->parm_size)
12438 fprintf (stderr, "\tparm_size = %5d\n", info->parm_size);
12439
12440 if (info->fixed_size)
12441 fprintf (stderr, "\tfixed_size = %5d\n", info->fixed_size);
12442
12443 if (info->gp_size)
12444 fprintf (stderr, "\tgp_size = %5d\n", info->gp_size);
12445
a3170dc6
AH		 12446 if (info->spe_gp_size)
12447 fprintf (stderr, "\tspe_gp_size = %5d\n", info->spe_gp_size);
12448
4697a36c
MM		 12449 if (info->fp_size)
12450 fprintf (stderr, "\tfp_size = %5d\n", info->fp_size);
12451
00b960c7
AH		 12452 if (info->altivec_size)
12453 fprintf (stderr, "\taltivec_size = %5d\n", info->altivec_size);
12454
12455 if (info->vrsave_size)
12456 fprintf (stderr, "\tvrsave_size = %5d\n", info->vrsave_size);
12457
12458 if (info->altivec_padding_size)
12459 fprintf (stderr, "\taltivec_padding_size= %5d\n",
12460 info->altivec_padding_size);
12461
a3170dc6
AH		 12462 if (info->spe_padding_size)
12463 fprintf (stderr, "\tspe_padding_size = %5d\n",
12464 info->spe_padding_size);
12465
a4f6c312 12466 if (info->lr_size)
ed947a96 12467 fprintf (stderr, "\tlr_size = %5d\n", info->lr_size);
b6c9286a 12468
4697a36c
MM		 12469 if (info->cr_size)
12470 fprintf (stderr, "\tcr_size = %5d\n", info->cr_size);
12471
a4f6c312 12472 if (info->toc_size)
b6c9286a
MM		 12473 fprintf (stderr, "\ttoc_size = %5d\n", info->toc_size);
12474
4697a36c
MM		 12475 if (info->save_size)
12476 fprintf (stderr, "\tsave_size = %5d\n", info->save_size);
12477
12478 if (info->reg_size != 4)
12479 fprintf (stderr, "\treg_size = %5d\n", info->reg_size);
12480
12481 fprintf (stderr, "\n");
9878760c 12482}
71f123ca
FS		 12483
12484rtx
a2369ed3 12485rs6000_return_addr (int count, rtx frame)
71f123ca 12486{
a4f6c312
SS		 12487 /* Currently we don't optimize very well between prolog and body
12488 code and for PIC code the code can be actually quite bad, so
12489 don't try to be too clever here. */
f1384257 12490 if (count != 0 || (DEFAULT_ABI != ABI_AIX && flag_pic))
71f123ca
FS		 12491 {
12492 cfun->machine->ra_needs_full_frame = 1;
8ac61af7
RK		 12493
12494 return
12495 gen_rtx_MEM
12496 (Pmode,
12497 memory_address
12498 (Pmode,
12499 plus_constant (copy_to_reg
12500 (gen_rtx_MEM (Pmode,
12501 memory_address (Pmode, frame))),
12502 RETURN_ADDRESS_OFFSET)));
71f123ca
FS		 12503 }
12504
8c29550d 12505 cfun->machine->ra_need_lr = 1;
9e2f7ec7 12506 return get_hard_reg_initial_val (Pmode, LINK_REGISTER_REGNUM);
71f123ca
FS		 12507}
12508
5e1bf043
DJ		 12509/* Say whether a function is a candidate for sibcall handling or not.
12510 We do not allow indirect calls to be optimized into sibling calls.
12511 Also, we can't do it if there are any vector parameters; there's
12512 nowhere to put the VRsave code so it works; note that functions with
12513 vector parameters are required to have a prototype, so the argument
12514 type info must be available here. (The tail recursion case can work
12515 with vector parameters, but there's no way to distinguish here.) */
4977bab6 12516static bool
a2369ed3 12517rs6000_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
5e1bf043
DJ		 12518{
12519 tree type;
4977bab6 12520 if (decl)
5e1bf043
DJ		 12521 {
12522 if (TARGET_ALTIVEC_VRSAVE)
c4ad648e 12523 {
4977bab6 12524 for (type = TYPE_ARG_TYPES (TREE_TYPE (decl));
5e1bf043
DJ		 12525 type; type = TREE_CHAIN (type))
12526 {
c15b529f 12527 if (TREE_CODE (TREE_VALUE (type)) == VECTOR_TYPE)
4977bab6 12528 return false;
5e1bf043 12529 }
c4ad648e 12530 }
5e1bf043 12531 if (DEFAULT_ABI == ABI_DARWIN
4977bab6 12532 || (*targetm.binds_local_p) (decl))
2bcc50d0 12533 {
4977bab6 12534 tree attr_list = TYPE_ATTRIBUTES (TREE_TYPE (decl));
2bcc50d0
AM		 12535
12536 if (!lookup_attribute ("longcall", attr_list)
12537 || lookup_attribute ("shortcall", attr_list))
4977bab6 12538 return true;
2bcc50d0 12539 }
5e1bf043 12540 }
4977bab6 12541 return false;
5e1bf043
DJ		 12542}
12543
e7e64a25
AS		 12544/* NULL if INSN insn is valid within a low-overhead loop.
12545 Otherwise return why doloop cannot be applied.
9419649c
DE		 12546 PowerPC uses the COUNT register for branch on table instructions. */
12547
e7e64a25
AS		 12548static const char *
12549rs6000_invalid_within_doloop (rtx insn)
9419649c
DE		 12550{
12551 if (CALL_P (insn))
e7e64a25 12552 return "Function call in the loop.";
9419649c
DE		 12553
12554 if (JUMP_P (insn)
12555 && (GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
12556 || GET_CODE (PATTERN (insn)) == ADDR_VEC))
e7e64a25 12557 return "Computed branch in the loop.";
9419649c 12558
e7e64a25 12559 return NULL;
9419649c
DE		 12560}
12561
71f123ca 12562static int
863d938c 12563rs6000_ra_ever_killed (void)
71f123ca
FS		 12564{
12565 rtx top;
5e1bf043
DJ		 12566 rtx reg;
12567 rtx insn;
71f123ca 12568
dd292d0a 12569 if (current_function_is_thunk)
71f123ca 12570 return 0;
eb0424da 12571
36f7e964
AH		 12572 /* regs_ever_live has LR marked as used if any sibcalls are present,
12573 but this should not force saving and restoring in the
12574 pro/epilogue. Likewise, reg_set_between_p thinks a sibcall
a3c9585f 12575 clobbers LR, so that is inappropriate. */
36f7e964 12576
5e1bf043
DJ		 12577 /* Also, the prologue can generate a store into LR that
12578 doesn't really count, like this:
36f7e964 12579
5e1bf043
DJ		 12580 move LR->R0
12581 bcl to set PIC register
12582 move LR->R31
12583 move R0->LR
36f7e964
AH		 12584
12585 When we're called from the epilogue, we need to avoid counting
12586 this as a store. */
f676971a 12587
71f123ca
FS		 12588 push_topmost_sequence ();
12589 top = get_insns ();
12590 pop_topmost_sequence ();
5e1bf043 12591 reg = gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM);
71f123ca 12592
5e1bf043
DJ		 12593 for (insn = NEXT_INSN (top); insn != NULL_RTX; insn = NEXT_INSN (insn))
12594 {
12595 if (INSN_P (insn))
12596 {
12597 if (FIND_REG_INC_NOTE (insn, reg))
12598 return 1;
f676971a 12599 else if (GET_CODE (insn) == CALL_INSN
c15b529f 12600 && !SIBLING_CALL_P (insn))
5e1bf043 12601 return 1;
36f7e964
AH		 12602 else if (set_of (reg, insn) != NULL_RTX
12603 && !prologue_epilogue_contains (insn))
5e1bf043
DJ		 12604 return 1;
12605 }
12606 }
12607 return 0;
71f123ca 12608}
4697a36c 12609\f
8cd8f856
GK		 12610/* Add a REG_MAYBE_DEAD note to the insn. */
12611static void
a2369ed3 12612rs6000_maybe_dead (rtx insn)
8cd8f856
GK		 12613{
12614 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD,
12615 const0_rtx,
12616 REG_NOTES (insn));
12617}
12618
9ebbca7d 12619/* Emit instructions needed to load the TOC register.
c7ca610e 12620 This is only needed when TARGET_TOC, TARGET_MINIMAL_TOC, and there is
9ebbca7d 12621 a constant pool; or for SVR4 -fpic. */
c7ca610e
RK		 12622
12623void
a2369ed3 12624rs6000_emit_load_toc_table (int fromprolog)
c7ca610e 12625{
027fbf43 12626 rtx dest, insn;
1db02437 12627 dest = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
c7ca610e 12628
7f970b70 12629 if (TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic)
20b71b17 12630 {
7f970b70
AM		 12631 char buf[30];
12632 rtx lab, tmp1, tmp2, got, tempLR;
12633
12634 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
12635 lab = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
12636 if (flag_pic == 2)
12637 got = gen_rtx_SYMBOL_REF (Pmode, toc_label_name);
12638 else
12639 got = rs6000_got_sym ();
12640 tmp1 = tmp2 = dest;
12641 if (!fromprolog)
12642 {
12643 tmp1 = gen_reg_rtx (Pmode);
12644 tmp2 = gen_reg_rtx (Pmode);
12645 }
12646 tempLR = (fromprolog
12647 ? gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)
12648 : gen_reg_rtx (Pmode));
12649 insn = emit_insn (gen_load_toc_v4_PIC_1 (tempLR, lab));
12650 if (fromprolog)
12651 rs6000_maybe_dead (insn);
12652 insn = emit_move_insn (tmp1, tempLR);
12653 if (fromprolog)
12654 rs6000_maybe_dead (insn);
12655 insn = emit_insn (gen_load_toc_v4_PIC_3b (tmp2, tmp1, got, lab));
12656 if (fromprolog)
12657 rs6000_maybe_dead (insn);
12658 insn = emit_insn (gen_load_toc_v4_PIC_3c (dest, tmp2, got, lab));
12659 if (fromprolog)
12660 rs6000_maybe_dead (insn);
12661 }
12662 else if (TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 1)
12663 {
12664 rtx tempLR = (fromprolog
12665 ? gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)
12666 : gen_reg_rtx (Pmode));
12667
12668 insn = emit_insn (gen_load_toc_v4_pic_si (tempLR));
027fbf43
JJ		 12669 if (fromprolog)
12670 rs6000_maybe_dead (insn);
7f970b70 12671 insn = emit_move_insn (dest, tempLR);
027fbf43
JJ		 12672 if (fromprolog)
12673 rs6000_maybe_dead (insn);
20b71b17
AM		 12674 }
12675 else if (TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2)
12676 {
12677 char buf[30];
12678 rtx tempLR = (fromprolog
12679 ? gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)
12680 : gen_reg_rtx (Pmode));
12681 rtx temp0 = (fromprolog
12682 ? gen_rtx_REG (Pmode, 0)
12683 : gen_reg_rtx (Pmode));
20b71b17 12684
20b71b17
AM		 12685 if (fromprolog)
12686 {
ccbca5e4 12687 rtx symF, symL;
38c1f2d7 12688
20b71b17
AM		 12689 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
12690 symF = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
9ebbca7d 12691
20b71b17
AM		 12692 ASM_GENERATE_INTERNAL_LABEL (buf, "LCL", rs6000_pic_labelno);
12693 symL = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
12694
12695 rs6000_maybe_dead (emit_insn (gen_load_toc_v4_PIC_1 (tempLR,
12696 symF)));
12697 rs6000_maybe_dead (emit_move_insn (dest, tempLR));
12698 rs6000_maybe_dead (emit_insn (gen_load_toc_v4_PIC_2 (temp0, dest,
12699 symL,
12700 symF)));
9ebbca7d
GK		 12701 }
12702 else
20b71b17
AM		 12703 {
12704 rtx tocsym;
20b71b17
AM		 12705
12706 tocsym = gen_rtx_SYMBOL_REF (Pmode, toc_label_name);
ccbca5e4 12707 emit_insn (gen_load_toc_v4_PIC_1b (tempLR, tocsym));
027fbf43
JJ		 12708 emit_move_insn (dest, tempLR);
12709 emit_move_insn (temp0, gen_rtx_MEM (Pmode, dest));
20b71b17 12710 }
027fbf43
JJ		 12711 insn = emit_insn (gen_addsi3 (dest, temp0, dest));
12712 if (fromprolog)
12713 rs6000_maybe_dead (insn);
9ebbca7d 12714 }
20b71b17
AM		 12715 else if (TARGET_ELF && !TARGET_AIX && flag_pic == 0 && TARGET_MINIMAL_TOC)
12716 {
12717 /* This is for AIX code running in non-PIC ELF32. */
12718 char buf[30];
12719 rtx realsym;
12720 ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1);
12721 realsym = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
12722
027fbf43
JJ		 12723 insn = emit_insn (gen_elf_high (dest, realsym));
12724 if (fromprolog)
12725 rs6000_maybe_dead (insn);
12726 insn = emit_insn (gen_elf_low (dest, dest, realsym));
12727 if (fromprolog)
12728 rs6000_maybe_dead (insn);
20b71b17 12729 }
37409796 12730 else
9ebbca7d 12731 {
37409796
NS		 12732 gcc_assert (DEFAULT_ABI == ABI_AIX);
12733
9ebbca7d 12734 if (TARGET_32BIT)
027fbf43 12735 insn = emit_insn (gen_load_toc_aix_si (dest));
9ebbca7d 12736 else
027fbf43
JJ		 12737 insn = emit_insn (gen_load_toc_aix_di (dest));
12738 if (fromprolog)
12739 rs6000_maybe_dead (insn);
9ebbca7d
GK		 12740 }
12741}
12742
d1d0c603
JJ		 12743/* Emit instructions to restore the link register after determining where
12744 its value has been stored. */
12745
12746void
12747rs6000_emit_eh_reg_restore (rtx source, rtx scratch)
12748{
12749 rs6000_stack_t *info = rs6000_stack_info ();
12750 rtx operands[2];
12751
12752 operands[0] = source;
12753 operands[1] = scratch;
12754
12755 if (info->lr_save_p)
12756 {
12757 rtx frame_rtx = stack_pointer_rtx;
12758 HOST_WIDE_INT sp_offset = 0;
12759 rtx tmp;
12760
12761 if (frame_pointer_needed
12762 || current_function_calls_alloca
12763 || info->total_size > 32767)
12764 {
12765 emit_move_insn (operands[1], gen_rtx_MEM (Pmode, frame_rtx));
12766 frame_rtx = operands[1];
12767 }
12768 else if (info->push_p)
12769 sp_offset = info->total_size;
12770
12771 tmp = plus_constant (frame_rtx, info->lr_save_offset + sp_offset);
12772 tmp = gen_rtx_MEM (Pmode, tmp);
12773 emit_move_insn (tmp, operands[0]);
12774 }
12775 else
12776 emit_move_insn (gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM), operands[0]);
12777}
12778
f103e34d
GK		 12779static GTY(()) int set = -1;
12780
f676971a 12781int
863d938c 12782get_TOC_alias_set (void)
9ebbca7d 12783{
f103e34d
GK		 12784 if (set == -1)
12785 set = new_alias_set ();
12786 return set;
f676971a 12787}
9ebbca7d 12788
c1207243 12789/* This returns nonzero if the current function uses the TOC. This is
3c9eb5f4
AM		 12790 determined by the presence of (use (unspec ... UNSPEC_TOC)), which
12791 is generated by the ABI_V4 load_toc_* patterns. */
c954844a 12792#if TARGET_ELF
3c9eb5f4 12793static int
f676971a 12794uses_TOC (void)
9ebbca7d 12795{
c4501e62 12796 rtx insn;
38c1f2d7 12797
c4501e62
JJ		 12798 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
12799 if (INSN_P (insn))
12800 {
12801 rtx pat = PATTERN (insn);
12802 int i;
9ebbca7d 12803
f676971a 12804 if (GET_CODE (pat) == PARALLEL)
c4501e62
JJ		 12805 for (i = 0; i < XVECLEN (pat, 0); i++)
12806 {
12807 rtx sub = XVECEXP (pat, 0, i);
12808 if (GET_CODE (sub) == USE)
12809 {
12810 sub = XEXP (sub, 0);
12811 if (GET_CODE (sub) == UNSPEC
12812 && XINT (sub, 1) == UNSPEC_TOC)
12813 return 1;
12814 }
12815 }
12816 }
12817 return 0;
9ebbca7d 12818}
c954844a 12819#endif
38c1f2d7 12820
9ebbca7d 12821rtx
f676971a 12822create_TOC_reference (rtx symbol)
9ebbca7d 12823{
f676971a 12824 return gen_rtx_PLUS (Pmode,
a8a05998 12825 gen_rtx_REG (Pmode, TOC_REGISTER),
f676971a
EC		 12826 gen_rtx_CONST (Pmode,
12827 gen_rtx_MINUS (Pmode, symbol,
b999aaeb 12828 gen_rtx_SYMBOL_REF (Pmode, toc_label_name))));
9ebbca7d 12829}
38c1f2d7 12830
fc4767bb
JJ		 12831/* If _Unwind_* has been called from within the same module,
12832 toc register is not guaranteed to be saved to 40(1) on function
12833 entry. Save it there in that case. */
c7ca610e 12834
9ebbca7d 12835void
863d938c 12836rs6000_aix_emit_builtin_unwind_init (void)
9ebbca7d
GK		 12837{
12838 rtx mem;
12839 rtx stack_top = gen_reg_rtx (Pmode);
12840 rtx opcode_addr = gen_reg_rtx (Pmode);
fc4767bb
JJ		 12841 rtx opcode = gen_reg_rtx (SImode);
12842 rtx tocompare = gen_reg_rtx (SImode);
12843 rtx no_toc_save_needed = gen_label_rtx ();
9ebbca7d
GK		 12844
12845 mem = gen_rtx_MEM (Pmode, hard_frame_pointer_rtx);
12846 emit_move_insn (stack_top, mem);
12847
fc4767bb
JJ		 12848 mem = gen_rtx_MEM (Pmode,
12849 gen_rtx_PLUS (Pmode, stack_top,
9ebbca7d
GK		 12850 GEN_INT (2 * GET_MODE_SIZE (Pmode))));
12851 emit_move_insn (opcode_addr, mem);
fc4767bb
JJ		 12852 emit_move_insn (opcode, gen_rtx_MEM (SImode, opcode_addr));
12853 emit_move_insn (tocompare, gen_int_mode (TARGET_32BIT ? 0x80410014
2496c7bd 12854 : 0xE8410028, SImode));
9ebbca7d 12855
fc4767bb 12856 do_compare_rtx_and_jump (opcode, tocompare, EQ, 1,
06f4e019 12857 SImode, NULL_RTX, NULL_RTX,
fc4767bb 12858 no_toc_save_needed);
9ebbca7d 12859
fc4767bb
JJ		 12860 mem = gen_rtx_MEM (Pmode,
12861 gen_rtx_PLUS (Pmode, stack_top,
12862 GEN_INT (5 * GET_MODE_SIZE (Pmode))));
12863 emit_move_insn (mem, gen_rtx_REG (Pmode, 2));
12864 emit_label (no_toc_save_needed);
9ebbca7d 12865}
38c1f2d7 12866\f
ba4828e0
RK		 12867/* This ties together stack memory (MEM with an alias set of
12868 rs6000_sr_alias_set) and the change to the stack pointer. */
12869
9ebbca7d 12870static void
863d938c 12871rs6000_emit_stack_tie (void)
9ebbca7d 12872{
ba4828e0
RK		 12873 rtx mem = gen_rtx_MEM (BLKmode, gen_rtx_REG (Pmode, STACK_POINTER_REGNUM));
12874
12875 set_mem_alias_set (mem, rs6000_sr_alias_set);
9ebbca7d
GK		 12876 emit_insn (gen_stack_tie (mem));
12877}
38c1f2d7 12878
9ebbca7d
GK		 12879/* Emit the correct code for allocating stack space, as insns.
12880 If COPY_R12, make sure a copy of the old frame is left in r12.
12881 The generated code may use hard register 0 as a temporary. */
12882
12883static void
a2369ed3 12884rs6000_emit_allocate_stack (HOST_WIDE_INT size, int copy_r12)
38c1f2d7 12885{
9ebbca7d
GK		 12886 rtx insn;
12887 rtx stack_reg = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
12888 rtx tmp_reg = gen_rtx_REG (Pmode, 0);
61168ff1
RS		 12889 rtx todec = gen_int_mode (-size, Pmode);
12890
12891 if (INTVAL (todec) != -size)
12892 {
d4ee4d25 12893 warning (0, "stack frame too large");
61168ff1
RS		 12894 emit_insn (gen_trap ());
12895 return;
12896 }
a157febd
GK		 12897
12898 if (current_function_limit_stack)
12899 {
12900 if (REG_P (stack_limit_rtx)
f676971a 12901 && REGNO (stack_limit_rtx) > 1
a157febd
GK		 12902 && REGNO (stack_limit_rtx) <= 31)
12903 {
5b71a4e7 12904 emit_insn (TARGET_32BIT
9ebbca7d
GK		 12905 ? gen_addsi3 (tmp_reg,
12906 stack_limit_rtx,
12907 GEN_INT (size))
12908 : gen_adddi3 (tmp_reg,
12909 stack_limit_rtx,
12910 GEN_INT (size)));
5b71a4e7 12911
9ebbca7d
GK		 12912 emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg,
12913 const0_rtx));
a157febd
GK		 12914 }
12915 else if (GET_CODE (stack_limit_rtx) == SYMBOL_REF
9ebbca7d 12916 && TARGET_32BIT
f607bc57 12917 && DEFAULT_ABI == ABI_V4)
a157febd 12918 {
9ebbca7d 12919 rtx toload = gen_rtx_CONST (VOIDmode,
f676971a
EC		 12920 gen_rtx_PLUS (Pmode,
12921 stack_limit_rtx,
9ebbca7d 12922 GEN_INT (size)));
5b71a4e7 12923
9ebbca7d
GK		 12924 emit_insn (gen_elf_high (tmp_reg, toload));
12925 emit_insn (gen_elf_low (tmp_reg, tmp_reg, toload));
12926 emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg,
12927 const0_rtx));
a157febd
GK		 12928 }
12929 else
d4ee4d25 12930 warning (0, "stack limit expression is not supported");
a157febd
GK		 12931 }
12932
9ebbca7d
GK		 12933 if (copy_r12 || ! TARGET_UPDATE)
12934 emit_move_insn (gen_rtx_REG (Pmode, 12), stack_reg);
12935
38c1f2d7
MM		 12936 if (TARGET_UPDATE)
12937 {
9ebbca7d 12938 if (size > 32767)
38c1f2d7 12939 {
9ebbca7d 12940 /* Need a note here so that try_split doesn't get confused. */
9390387d 12941 if (get_last_insn () == NULL_RTX)
2e040219 12942 emit_note (NOTE_INSN_DELETED);
9ebbca7d
GK		 12943 insn = emit_move_insn (tmp_reg, todec);
12944 try_split (PATTERN (insn), insn, 0);
12945 todec = tmp_reg;
38c1f2d7 12946 }
5b71a4e7
DE		 12947
12948 insn = emit_insn (TARGET_32BIT
12949 ? gen_movsi_update (stack_reg, stack_reg,
12950 todec, stack_reg)
c4ad648e 12951 : gen_movdi_di_update (stack_reg, stack_reg,
9ebbca7d 12952 todec, stack_reg));
38c1f2d7
MM		 12953 }
12954 else
12955 {
5b71a4e7
DE		 12956 insn = emit_insn (TARGET_32BIT
12957 ? gen_addsi3 (stack_reg, stack_reg, todec)
12958 : gen_adddi3 (stack_reg, stack_reg, todec));
9ebbca7d
GK		 12959 emit_move_insn (gen_rtx_MEM (Pmode, stack_reg),
12960 gen_rtx_REG (Pmode, 12));
12961 }
f676971a 12962
9ebbca7d 12963 RTX_FRAME_RELATED_P (insn) = 1;
f676971a 12964 REG_NOTES (insn) =
9ebbca7d 12965 gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
f676971a 12966 gen_rtx_SET (VOIDmode, stack_reg,
9ebbca7d
GK		 12967 gen_rtx_PLUS (Pmode, stack_reg,
12968 GEN_INT (-size))),
12969 REG_NOTES (insn));
12970}
12971
a4f6c312
SS		 12972/* Add to 'insn' a note which is PATTERN (INSN) but with REG replaced
12973 with (plus:P (reg 1) VAL), and with REG2 replaced with RREG if REG2
12974 is not NULL. It would be nice if dwarf2out_frame_debug_expr could
12975 deduce these equivalences by itself so it wasn't necessary to hold
12976 its hand so much. */
9ebbca7d
GK		 12977
12978static void
f676971a 12979rs6000_frame_related (rtx insn, rtx reg, HOST_WIDE_INT val,
a2369ed3 12980 rtx reg2, rtx rreg)
9ebbca7d
GK		 12981{
12982 rtx real, temp;
12983
e56c4463
JL		 12984 /* copy_rtx will not make unique copies of registers, so we need to
12985 ensure we don't have unwanted sharing here. */
12986 if (reg == reg2)
12987 reg = gen_raw_REG (GET_MODE (reg), REGNO (reg));
12988
12989 if (reg == rreg)
12990 reg = gen_raw_REG (GET_MODE (reg), REGNO (reg));
12991
9ebbca7d
GK		 12992 real = copy_rtx (PATTERN (insn));
12993
89e7058f
AH		 12994 if (reg2 != NULL_RTX)
12995 real = replace_rtx (real, reg2, rreg);
f676971a
EC		 12996
12997 real = replace_rtx (real, reg,
9ebbca7d
GK		 12998 gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode,
12999 STACK_POINTER_REGNUM),
13000 GEN_INT (val)));
f676971a 13001
9ebbca7d
GK		 13002 /* We expect that 'real' is either a SET or a PARALLEL containing
13003 SETs (and possibly other stuff). In a PARALLEL, all the SETs
13004 are important so they all have to be marked RTX_FRAME_RELATED_P. */
13005
13006 if (GET_CODE (real) == SET)
13007 {
13008 rtx set = real;
f676971a 13009
9ebbca7d
GK		 13010 temp = simplify_rtx (SET_SRC (set));
13011 if (temp)
13012 SET_SRC (set) = temp;
13013 temp = simplify_rtx (SET_DEST (set));
13014 if (temp)
13015 SET_DEST (set) = temp;
13016 if (GET_CODE (SET_DEST (set)) == MEM)
38c1f2d7 13017 {
9ebbca7d
GK		 13018 temp = simplify_rtx (XEXP (SET_DEST (set), 0));
13019 if (temp)
13020 XEXP (SET_DEST (set), 0) = temp;
38c1f2d7 13021 }
38c1f2d7 13022 }
37409796 13023 else
9ebbca7d
GK		 13024 {
13025 int i;
37409796
NS		 13026
13027 gcc_assert (GET_CODE (real) == PARALLEL);
9ebbca7d
GK		 13028 for (i = 0; i < XVECLEN (real, 0); i++)
13029 if (GET_CODE (XVECEXP (real, 0, i)) == SET)
13030 {
13031 rtx set = XVECEXP (real, 0, i);
f676971a 13032
9ebbca7d
GK		 13033 temp = simplify_rtx (SET_SRC (set));
13034 if (temp)
13035 SET_SRC (set) = temp;
13036 temp = simplify_rtx (SET_DEST (set));
13037 if (temp)
13038 SET_DEST (set) = temp;
13039 if (GET_CODE (SET_DEST (set)) == MEM)
13040 {
13041 temp = simplify_rtx (XEXP (SET_DEST (set), 0));
13042 if (temp)
13043 XEXP (SET_DEST (set), 0) = temp;
13044 }
13045 RTX_FRAME_RELATED_P (set) = 1;
13046 }
13047 }
c19de7aa
AH		 13048
13049 if (TARGET_SPE)
13050 real = spe_synthesize_frame_save (real);
13051
9ebbca7d
GK		 13052 RTX_FRAME_RELATED_P (insn) = 1;
13053 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
13054 real,
13055 REG_NOTES (insn));
38c1f2d7
MM		 13056}
13057
c19de7aa
AH		 13058/* Given an SPE frame note, return a PARALLEL of SETs with the
13059 original note, plus a synthetic register save. */
13060
13061static rtx
a2369ed3 13062spe_synthesize_frame_save (rtx real)
c19de7aa
AH		 13063{
13064 rtx synth, offset, reg, real2;
13065
13066 if (GET_CODE (real) != SET
13067 || GET_MODE (SET_SRC (real)) != V2SImode)
13068 return real;
13069
13070 /* For the SPE, registers saved in 64-bits, get a PARALLEL for their
13071 frame related note. The parallel contains a set of the register
41f3a930 13072 being saved, and another set to a synthetic register (n+1200).
c19de7aa
AH		 13073 This is so we can differentiate between 64-bit and 32-bit saves.
13074 Words cannot describe this nastiness. */
13075
37409796
NS		 13076 gcc_assert (GET_CODE (SET_DEST (real)) == MEM
13077 && GET_CODE (XEXP (SET_DEST (real), 0)) == PLUS
13078 && GET_CODE (SET_SRC (real)) == REG);
c19de7aa
AH		 13079
13080 /* Transform:
13081 (set (mem (plus (reg x) (const y)))
13082 (reg z))
13083 into:
13084 (set (mem (plus (reg x) (const y+4)))
41f3a930 13085 (reg z+1200))
c19de7aa
AH		 13086 */
13087
13088 real2 = copy_rtx (real);
13089 PUT_MODE (SET_DEST (real2), SImode);
13090 reg = SET_SRC (real2);
13091 real2 = replace_rtx (real2, reg, gen_rtx_REG (SImode, REGNO (reg)));
13092 synth = copy_rtx (real2);
13093
13094 if (BYTES_BIG_ENDIAN)
13095 {
13096 offset = XEXP (XEXP (SET_DEST (real2), 0), 1);
13097 real2 = replace_rtx (real2, offset, GEN_INT (INTVAL (offset) + 4));
13098 }
13099
13100 reg = SET_SRC (synth);
41f3a930 13101
c19de7aa 13102 synth = replace_rtx (synth, reg,
41f3a930 13103 gen_rtx_REG (SImode, REGNO (reg) + 1200));
c19de7aa
AH		 13104
13105 offset = XEXP (XEXP (SET_DEST (synth), 0), 1);
13106 synth = replace_rtx (synth, offset,
13107 GEN_INT (INTVAL (offset)
13108 + (BYTES_BIG_ENDIAN ? 0 : 4)));
13109
13110 RTX_FRAME_RELATED_P (synth) = 1;
13111 RTX_FRAME_RELATED_P (real2) = 1;
13112 if (BYTES_BIG_ENDIAN)
13113 real = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, synth, real2));
13114 else
13115 real = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, real2, synth));
13116
13117 return real;
13118}
13119
00b960c7
AH		 13120/* Returns an insn that has a vrsave set operation with the
13121 appropriate CLOBBERs. */
13122
13123static rtx
a2369ed3 13124generate_set_vrsave (rtx reg, rs6000_stack_t *info, int epiloguep)
00b960c7
AH		 13125{
13126 int nclobs, i;
13127 rtx insn, clobs[TOTAL_ALTIVEC_REGS + 1];
a004eb82 13128 rtx vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO);
00b960c7 13129
a004eb82
AH		 13130 clobs[0]
13131 = gen_rtx_SET (VOIDmode,
13132 vrsave,
13133 gen_rtx_UNSPEC_VOLATILE (SImode,
13134 gen_rtvec (2, reg, vrsave),
13135 30));
00b960c7
AH		 13136
13137 nclobs = 1;
13138
9aa86737
AH		 13139 /* We need to clobber the registers in the mask so the scheduler
13140 does not move sets to VRSAVE before sets of AltiVec registers.
13141
13142 However, if the function receives nonlocal gotos, reload will set
13143 all call saved registers live. We will end up with:
13144
13145 (set (reg 999) (mem))
13146 (parallel [ (set (reg vrsave) (unspec blah))
13147 (clobber (reg 999))])
13148
13149 The clobber will cause the store into reg 999 to be dead, and
13150 flow will attempt to delete an epilogue insn. In this case, we
13151 need an unspec use/set of the register. */
00b960c7
AH		 13152
13153 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
44688022 13154 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
9aa86737
AH		 13155 {
13156 if (!epiloguep || call_used_regs [i])
13157 clobs[nclobs++] = gen_rtx_CLOBBER (VOIDmode,
13158 gen_rtx_REG (V4SImode, i));
13159 else
13160 {
13161 rtx reg = gen_rtx_REG (V4SImode, i);
9aa86737
AH		 13162
13163 clobs[nclobs++]
a004eb82
AH		 13164 = gen_rtx_SET (VOIDmode,
13165 reg,
13166 gen_rtx_UNSPEC (V4SImode,
13167 gen_rtvec (1, reg), 27));
9aa86737
AH		 13168 }
13169 }
00b960c7
AH		 13170
13171 insn = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (nclobs));
13172
13173 for (i = 0; i < nclobs; ++i)
13174 XVECEXP (insn, 0, i) = clobs[i];
13175
13176 return insn;
13177}
13178
89e7058f
AH		 13179/* Save a register into the frame, and emit RTX_FRAME_RELATED_P notes.
13180 Save REGNO into [FRAME_REG + OFFSET] in mode MODE. */
13181
13182static void
f676971a 13183emit_frame_save (rtx frame_reg, rtx frame_ptr, enum machine_mode mode,
d1d0c603 13184 unsigned int regno, int offset, HOST_WIDE_INT total_size)
89e7058f
AH		 13185{
13186 rtx reg, offset_rtx, insn, mem, addr, int_rtx;
13187 rtx replacea, replaceb;
13188
13189 int_rtx = GEN_INT (offset);
13190
13191 /* Some cases that need register indexed addressing. */
13192 if ((TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
4d4cbc0e 13193 || (TARGET_E500_DOUBLE && mode == DFmode)
a3170dc6
AH		 13194 || (TARGET_SPE_ABI
13195 && SPE_VECTOR_MODE (mode)
13196 && !SPE_CONST_OFFSET_OK (offset)))
89e7058f
AH		 13197 {
13198 /* Whomever calls us must make sure r11 is available in the
c4ad648e 13199 flow path of instructions in the prologue. */
89e7058f
AH		 13200 offset_rtx = gen_rtx_REG (Pmode, 11);
13201 emit_move_insn (offset_rtx, int_rtx);
13202
13203 replacea = offset_rtx;
13204 replaceb = int_rtx;
13205 }
13206 else
13207 {
13208 offset_rtx = int_rtx;
13209 replacea = NULL_RTX;
13210 replaceb = NULL_RTX;
13211 }
13212
13213 reg = gen_rtx_REG (mode, regno);
13214 addr = gen_rtx_PLUS (Pmode, frame_reg, offset_rtx);
13215 mem = gen_rtx_MEM (mode, addr);
13216 set_mem_alias_set (mem, rs6000_sr_alias_set);
13217
13218 insn = emit_move_insn (mem, reg);
13219
13220 rs6000_frame_related (insn, frame_ptr, total_size, replacea, replaceb);
13221}
13222
a3170dc6
AH		 13223/* Emit an offset memory reference suitable for a frame store, while
13224 converting to a valid addressing mode. */
13225
13226static rtx
a2369ed3 13227gen_frame_mem_offset (enum machine_mode mode, rtx reg, int offset)
a3170dc6
AH		 13228{
13229 rtx int_rtx, offset_rtx;
13230
13231 int_rtx = GEN_INT (offset);
13232
4d4cbc0e
AH		 13233 if ((TARGET_SPE_ABI && SPE_VECTOR_MODE (mode))
13234 || (TARGET_E500_DOUBLE && mode == DFmode))
a3170dc6
AH		 13235 {
13236 offset_rtx = gen_rtx_REG (Pmode, FIXED_SCRATCH);
13237 emit_move_insn (offset_rtx, int_rtx);
13238 }
13239 else
13240 offset_rtx = int_rtx;
13241
13242 return gen_rtx_MEM (mode, gen_rtx_PLUS (Pmode, reg, offset_rtx));
13243}
13244
6d0a8091
DJ		 13245/* Look for user-defined global regs. We should not save and restore these,
13246 and cannot use stmw/lmw if there are any in its range. */
13247
13248static bool
13249no_global_regs_above (int first_greg)
13250{
13251 int i;
13252 for (i = 0; i < 32 - first_greg; i++)
13253 if (global_regs[first_greg + i])
13254 return false;
13255 return true;
13256}
13257
699c914a
MS		 13258#ifndef TARGET_FIX_AND_CONTINUE
13259#define TARGET_FIX_AND_CONTINUE 0
13260#endif
13261
9ebbca7d
GK		 13262/* Emit function prologue as insns. */
13263
9878760c 13264void
863d938c 13265rs6000_emit_prologue (void)
9878760c 13266{
4697a36c 13267 rs6000_stack_t *info = rs6000_stack_info ();
0e67400a 13268 enum machine_mode reg_mode = Pmode;
327e5343 13269 int reg_size = TARGET_32BIT ? 4 : 8;
9ebbca7d
GK		 13270 rtx sp_reg_rtx = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
13271 rtx frame_ptr_rtx = gen_rtx_REG (Pmode, 12);
13272 rtx frame_reg_rtx = sp_reg_rtx;
b78d48dd 13273 rtx cr_save_rtx = NULL_RTX;
9ebbca7d
GK		 13274 rtx insn;
13275 int saving_FPRs_inline;
13276 int using_store_multiple;
13277 HOST_WIDE_INT sp_offset = 0;
f676971a 13278
699c914a
MS		 13279 if (TARGET_FIX_AND_CONTINUE)
13280 {
13281 /* gdb on darwin arranges to forward a function from the old
de2ab0ca 13282 address by modifying the first 5 instructions of the function
699c914a
MS		 13283 to branch to the overriding function. This is necessary to
13284 permit function pointers that point to the old function to
13285 actually forward to the new function. */
13286 emit_insn (gen_nop ());
13287 emit_insn (gen_nop ());
de2ab0ca 13288 emit_insn (gen_nop ());
699c914a
MS		 13289 emit_insn (gen_nop ());
13290 emit_insn (gen_nop ());
13291 }
13292
13293 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
13294 {
13295 reg_mode = V2SImode;
13296 reg_size = 8;
13297 }
a3170dc6 13298
9ebbca7d 13299 using_store_multiple = (TARGET_MULTIPLE && ! TARGET_POWERPC64
c19de7aa
AH		 13300 && (!TARGET_SPE_ABI
13301 || info->spe_64bit_regs_used == 0)
6d0a8091
DJ		 13302 && info->first_gp_reg_save < 31
13303 && no_global_regs_above (info->first_gp_reg_save));
9ebbca7d 13304 saving_FPRs_inline = (info->first_fp_reg_save == 64
8c29550d 13305 || FP_SAVE_INLINE (info->first_fp_reg_save)
acd0b319 13306 || current_function_calls_eh_return
8c29550d 13307 || cfun->machine->ra_need_lr);
9ebbca7d
GK		 13308
13309 /* For V.4, update stack before we do any saving and set back pointer. */
fc4767bb 13310 if (info->push_p
acd0b319
AM		 13311 && (DEFAULT_ABI == ABI_V4
13312 || current_function_calls_eh_return))
9ebbca7d
GK		 13313 {
13314 if (info->total_size < 32767)
13315 sp_offset = info->total_size;
13316 else
13317 frame_reg_rtx = frame_ptr_rtx;
f676971a 13318 rs6000_emit_allocate_stack (info->total_size,
9ebbca7d
GK		 13319 (frame_reg_rtx != sp_reg_rtx
13320 && (info->cr_save_p
13321 || info->lr_save_p
13322 || info->first_fp_reg_save < 64
13323 || info->first_gp_reg_save < 32
13324 )));
13325 if (frame_reg_rtx != sp_reg_rtx)
13326 rs6000_emit_stack_tie ();
13327 }
13328
d62294f5 13329 /* Handle world saves specially here. */
f57fe068 13330 if (WORLD_SAVE_P (info))
d62294f5
FJ		 13331 {
13332 int i, j, sz;
13333 rtx treg;
13334 rtvec p;
13335
13336 /* save_world expects lr in r0. */
13337 if (info->lr_save_p)
c4ad648e
AM		 13338 {
13339 insn = emit_move_insn (gen_rtx_REG (Pmode, 0),
13340 gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM));
13341 RTX_FRAME_RELATED_P (insn) = 1;
13342 }
d62294f5
FJ		 13343
13344 /* The SAVE_WORLD and RESTORE_WORLD routines make a number of
c4ad648e 13345 assumptions about the offsets of various bits of the stack
992d08b1 13346 frame. */
37409796
NS		 13347 gcc_assert (info->gp_save_offset == -220
13348 && info->fp_save_offset == -144
13349 && info->lr_save_offset == 8
13350 && info->cr_save_offset == 4
13351 && info->push_p
13352 && info->lr_save_p
13353 && (!current_function_calls_eh_return
13354 || info->ehrd_offset == -432)
13355 && info->vrsave_save_offset == -224
13356 && info->altivec_save_offset == (-224 -16 -192));
d62294f5
FJ		 13357
13358 treg = gen_rtx_REG (SImode, 11);
13359 emit_move_insn (treg, GEN_INT (-info->total_size));
13360
13361 /* SAVE_WORLD takes the caller's LR in R0 and the frame size
c4ad648e 13362 in R11. It also clobbers R12, so beware! */
d62294f5
FJ		 13363
13364 /* Preserve CR2 for save_world prologues */
13365 sz = 6;
13366 sz += 32 - info->first_gp_reg_save;
13367 sz += 64 - info->first_fp_reg_save;
13368 sz += LAST_ALTIVEC_REGNO - info->first_altivec_reg_save + 1;
13369 p = rtvec_alloc (sz);
13370 j = 0;
13371 RTVEC_ELT (p, j++) = gen_rtx_CLOBBER (VOIDmode,
c4ad648e
AM		 13372 gen_rtx_REG (Pmode,
13373 LINK_REGISTER_REGNUM));
d62294f5 13374 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode,
c4ad648e
AM		 13375 gen_rtx_SYMBOL_REF (Pmode,
13376 "*save_world"));
d62294f5 13377 /* We do floats first so that the instruction pattern matches
c4ad648e
AM		 13378 properly. */
13379 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
13380 {
13381 rtx reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i);
13382 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13383 GEN_INT (info->fp_save_offset
13384 + sp_offset + 8 * i));
13385 rtx mem = gen_rtx_MEM (DFmode, addr);
13386 set_mem_alias_set (mem, rs6000_sr_alias_set);
13387
13388 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
13389 }
d62294f5 13390 for (i = 0; info->first_altivec_reg_save + i <= LAST_ALTIVEC_REGNO; i++)
c4ad648e
AM		 13391 {
13392 rtx reg = gen_rtx_REG (V4SImode, info->first_altivec_reg_save + i);
13393 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13394 GEN_INT (info->altivec_save_offset
13395 + sp_offset + 16 * i));
13396 rtx mem = gen_rtx_MEM (V4SImode, addr);
13397 set_mem_alias_set (mem, rs6000_sr_alias_set);
13398
13399 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
13400 }
d62294f5 13401 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
c4ad648e
AM		 13402 {
13403 rtx reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
13404 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13405 GEN_INT (info->gp_save_offset
13406 + sp_offset + reg_size * i));
13407 rtx mem = gen_rtx_MEM (reg_mode, addr);
13408 set_mem_alias_set (mem, rs6000_sr_alias_set);
13409
13410 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
13411 }
13412
13413 {
13414 /* CR register traditionally saved as CR2. */
13415 rtx reg = gen_rtx_REG (reg_mode, CR2_REGNO);
13416 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13417 GEN_INT (info->cr_save_offset
13418 + sp_offset));
13419 rtx mem = gen_rtx_MEM (reg_mode, addr);
13420 set_mem_alias_set (mem, rs6000_sr_alias_set);
13421
13422 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
13423 }
d62294f5
FJ		 13424 /* Prevent any attempt to delete the setting of r0 and treg! */
13425 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode, gen_rtx_REG (Pmode, 0));
13426 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode, treg);
13427 RTVEC_ELT (p, j++) = gen_rtx_CLOBBER (VOIDmode, sp_reg_rtx);
13428
13429 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
13430 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
c4ad648e 13431 NULL_RTX, NULL_RTX);
d62294f5
FJ		 13432
13433 if (current_function_calls_eh_return)
c4ad648e
AM		 13434 {
13435 unsigned int i;
13436 for (i = 0; ; ++i)
13437 {
13438 unsigned int regno = EH_RETURN_DATA_REGNO (i);
13439 if (regno == INVALID_REGNUM)
13440 break;
13441 emit_frame_save (frame_reg_rtx, frame_ptr_rtx, reg_mode, regno,
13442 info->ehrd_offset + sp_offset
13443 + reg_size * (int) i,
13444 info->total_size);
13445 }
13446 }
d62294f5
FJ		 13447 }
13448
9aa86737 13449 /* Save AltiVec registers if needed. */
f57fe068 13450 if (!WORLD_SAVE_P (info) && TARGET_ALTIVEC_ABI && info->altivec_size != 0)
9aa86737
AH		 13451 {
13452 int i;
13453
13454 /* There should be a non inline version of this, for when we
13455 are saving lots of vector registers. */
13456 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
13457 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
13458 {
13459 rtx areg, savereg, mem;
13460 int offset;
13461
13462 offset = info->altivec_save_offset + sp_offset
13463 + 16 * (i - info->first_altivec_reg_save);
13464
13465 savereg = gen_rtx_REG (V4SImode, i);
13466
13467 areg = gen_rtx_REG (Pmode, 0);
13468 emit_move_insn (areg, GEN_INT (offset));
13469
13470 /* AltiVec addressing mode is [reg+reg]. */
13471 mem = gen_rtx_MEM (V4SImode,
13472 gen_rtx_PLUS (Pmode, frame_reg_rtx, areg));
f676971a 13473
9aa86737
AH		 13474 set_mem_alias_set (mem, rs6000_sr_alias_set);
13475
13476 insn = emit_move_insn (mem, savereg);
13477
5c242421
SB		 13478 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
13479 areg, GEN_INT (offset));
9aa86737
AH		 13480 }
13481 }
13482
13483 /* VRSAVE is a bit vector representing which AltiVec registers
13484 are used. The OS uses this to determine which vector
13485 registers to save on a context switch. We need to save
13486 VRSAVE on the stack frame, add whatever AltiVec registers we
13487 used in this function, and do the corresponding magic in the
13488 epilogue. */
13489
4d774ff8 13490 if (TARGET_ALTIVEC && TARGET_ALTIVEC_VRSAVE
bcb604b6 13491 && info->vrsave_mask != 0)
9aa86737 13492 {
a004eb82 13493 rtx reg, mem, vrsave;
9aa86737
AH		 13494 int offset;
13495
eab97e44
AM		 13496 /* Get VRSAVE onto a GPR. Note that ABI_V4 might be using r12
13497 as frame_reg_rtx and r11 as the static chain pointer for
13498 nested functions. */
13499 reg = gen_rtx_REG (SImode, 0);
a004eb82 13500 vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO);
b188f760
AH		 13501 if (TARGET_MACHO)
13502 emit_insn (gen_get_vrsave_internal (reg));
13503 else
13504 emit_insn (gen_rtx_SET (VOIDmode, reg, vrsave));
9aa86737 13505
bcb604b6
FJ		 13506 if (!WORLD_SAVE_P (info))
13507 {
13508 /* Save VRSAVE. */
13509 offset = info->vrsave_save_offset + sp_offset;
13510 mem
13511 = gen_rtx_MEM (SImode,
13512 gen_rtx_PLUS (Pmode, frame_reg_rtx, GEN_INT (offset)));
13513 set_mem_alias_set (mem, rs6000_sr_alias_set);
13514 insn = emit_move_insn (mem, reg);
13515 }
9aa86737
AH		 13516
13517 /* Include the registers in the mask. */
13518 emit_insn (gen_iorsi3 (reg, reg, GEN_INT ((int) info->vrsave_mask)));
13519
13520 insn = emit_insn (generate_set_vrsave (reg, info, 0));
13521 }
13522
9ebbca7d 13523 /* If we use the link register, get it into r0. */
f57fe068 13524 if (!WORLD_SAVE_P (info) && info->lr_save_p)
f8a57be8
GK		 13525 {
13526 insn = emit_move_insn (gen_rtx_REG (Pmode, 0),
13527 gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM));
13528 RTX_FRAME_RELATED_P (insn) = 1;
13529 }
9ebbca7d
GK		 13530
13531 /* If we need to save CR, put it into r12. */
f57fe068 13532 if (!WORLD_SAVE_P (info) && info->cr_save_p && frame_reg_rtx != frame_ptr_rtx)
9ebbca7d 13533 {
f8a57be8 13534 rtx set;
f676971a 13535
9ebbca7d 13536 cr_save_rtx = gen_rtx_REG (SImode, 12);
f8a57be8
GK		 13537 insn = emit_insn (gen_movesi_from_cr (cr_save_rtx));
13538 RTX_FRAME_RELATED_P (insn) = 1;
13539 /* Now, there's no way that dwarf2out_frame_debug_expr is going
13540 to understand '(unspec:SI [(reg:CC 68) ...] UNSPEC_MOVESI_FROM_CR)'.
13541 But that's OK. All we have to do is specify that _one_ condition
13542 code register is saved in this stack slot. The thrower's epilogue
13543 will then restore all the call-saved registers.
13544 We use CR2_REGNO (70) to be compatible with gcc-2.95 on Linux. */
13545 set = gen_rtx_SET (VOIDmode, cr_save_rtx,
13546 gen_rtx_REG (SImode, CR2_REGNO));
13547 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
13548 set,
13549 REG_NOTES (insn));
9ebbca7d
GK		 13550 }
13551
a4f6c312
SS		 13552 /* Do any required saving of fpr's. If only one or two to save, do
13553 it ourselves. Otherwise, call function. */
f57fe068 13554 if (!WORLD_SAVE_P (info) && saving_FPRs_inline)
9ebbca7d
GK		 13555 {
13556 int i;
13557 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
f676971a 13558 if ((regs_ever_live[info->first_fp_reg_save+i]
9ebbca7d 13559 && ! call_used_regs[info->first_fp_reg_save+i]))
89e7058f
AH		 13560 emit_frame_save (frame_reg_rtx, frame_ptr_rtx, DFmode,
13561 info->first_fp_reg_save + i,
13562 info->fp_save_offset + sp_offset + 8 * i,
13563 info->total_size);
9ebbca7d 13564 }
f57fe068 13565 else if (!WORLD_SAVE_P (info) && info->first_fp_reg_save != 64)
9ebbca7d
GK		 13566 {
13567 int i;
13568 char rname[30];
520a57c8 13569 const char *alloc_rname;
9ebbca7d
GK		 13570 rtvec p;
13571 p = rtvec_alloc (2 + 64 - info->first_fp_reg_save);
f676971a
EC		 13572
13573 RTVEC_ELT (p, 0) = gen_rtx_CLOBBER (VOIDmode,
13574 gen_rtx_REG (Pmode,
9ebbca7d
GK		 13575 LINK_REGISTER_REGNUM));
13576 sprintf (rname, "%s%d%s", SAVE_FP_PREFIX,
13577 info->first_fp_reg_save - 32, SAVE_FP_SUFFIX);
a8a05998 13578 alloc_rname = ggc_strdup (rname);
9ebbca7d
GK		 13579 RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode,
13580 gen_rtx_SYMBOL_REF (Pmode,
13581 alloc_rname));
13582 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
13583 {
13584 rtx addr, reg, mem;
13585 reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i);
13586 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
f676971a 13587 GEN_INT (info->fp_save_offset
9ebbca7d
GK		 13588 + sp_offset + 8*i));
13589 mem = gen_rtx_MEM (DFmode, addr);
ba4828e0 13590 set_mem_alias_set (mem, rs6000_sr_alias_set);
9ebbca7d
GK		 13591
13592 RTVEC_ELT (p, i + 2) = gen_rtx_SET (VOIDmode, mem, reg);
13593 }
13594 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
f676971a 13595 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
9ebbca7d
GK		 13596 NULL_RTX, NULL_RTX);
13597 }
b6c9286a 13598
9ebbca7d
GK		 13599 /* Save GPRs. This is done as a PARALLEL if we are using
13600 the store-multiple instructions. */
f57fe068 13601 if (!WORLD_SAVE_P (info) && using_store_multiple)
b6c9286a 13602 {
308c142a 13603 rtvec p;
9ebbca7d
GK		 13604 int i;
13605 p = rtvec_alloc (32 - info->first_gp_reg_save);
9ebbca7d
GK		 13606 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
13607 {
13608 rtx addr, reg, mem;
13609 reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
f676971a
EC		 13610 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13611 GEN_INT (info->gp_save_offset
13612 + sp_offset
9ebbca7d
GK		 13613 + reg_size * i));
13614 mem = gen_rtx_MEM (reg_mode, addr);
ba4828e0 13615 set_mem_alias_set (mem, rs6000_sr_alias_set);
9ebbca7d
GK		 13616
13617 RTVEC_ELT (p, i) = gen_rtx_SET (VOIDmode, mem, reg);
13618 }
13619 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
f676971a 13620 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
9ebbca7d 13621 NULL_RTX, NULL_RTX);
b6c9286a 13622 }
f57fe068 13623 else if (!WORLD_SAVE_P (info))
b6c9286a 13624 {
9ebbca7d
GK		 13625 int i;
13626 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
6d0a8091
DJ		 13627 if ((regs_ever_live[info->first_gp_reg_save + i]
13628 && (!call_used_regs[info->first_gp_reg_save + i]
13629 || (i + info->first_gp_reg_save
b4db40bf
JJ		 13630 == RS6000_PIC_OFFSET_TABLE_REGNUM
13631 && TARGET_TOC && TARGET_MINIMAL_TOC)))
6d0a8091 13632 || (i + info->first_gp_reg_save == RS6000_PIC_OFFSET_TABLE_REGNUM
14f00213 13633 && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0)
f607bc57 13634 || (DEFAULT_ABI == ABI_DARWIN && flag_pic))))
a3170dc6
AH		 13635 {
13636 rtx addr, reg, mem;
13637 reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
13638
c19de7aa 13639 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
a3170dc6
AH		 13640 {
13641 int offset = info->spe_gp_save_offset + sp_offset + 8 * i;
13642 rtx b;
13643
13644 if (!SPE_CONST_OFFSET_OK (offset))
13645 {
13646 b = gen_rtx_REG (Pmode, FIXED_SCRATCH);
13647 emit_move_insn (b, GEN_INT (offset));
13648 }
13649 else
13650 b = GEN_INT (offset);
13651
13652 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, b);
13653 mem = gen_rtx_MEM (V2SImode, addr);
13654 set_mem_alias_set (mem, rs6000_sr_alias_set);
13655 insn = emit_move_insn (mem, reg);
13656
13657 if (GET_CODE (b) == CONST_INT)
13658 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
13659 NULL_RTX, NULL_RTX);
13660 else
13661 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
13662 b, GEN_INT (offset));
13663 }
13664 else
13665 {
f676971a
EC		 13666 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13667 GEN_INT (info->gp_save_offset
13668 + sp_offset
a3170dc6
AH		 13669 + reg_size * i));
13670 mem = gen_rtx_MEM (reg_mode, addr);
13671 set_mem_alias_set (mem, rs6000_sr_alias_set);
13672
13673 insn = emit_move_insn (mem, reg);
f676971a 13674 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
a3170dc6
AH		 13675 NULL_RTX, NULL_RTX);
13676 }
13677 }
9ebbca7d
GK		 13678 }
13679
83720594
RH		 13680 /* ??? There's no need to emit actual instructions here, but it's the
13681 easiest way to get the frame unwind information emitted. */
f57fe068 13682 if (!WORLD_SAVE_P (info) && current_function_calls_eh_return)
83720594 13683 {
78e1b90d
DE		 13684 unsigned int i, regno;
13685
fc4767bb
JJ		 13686 /* In AIX ABI we need to pretend we save r2 here. */
13687 if (TARGET_AIX)
13688 {
13689 rtx addr, reg, mem;
13690
13691 reg = gen_rtx_REG (reg_mode, 2);
13692 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13693 GEN_INT (sp_offset + 5 * reg_size));
13694 mem = gen_rtx_MEM (reg_mode, addr);
13695 set_mem_alias_set (mem, rs6000_sr_alias_set);
13696
13697 insn = emit_move_insn (mem, reg);
f676971a 13698 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
fc4767bb
JJ		 13699 NULL_RTX, NULL_RTX);
13700 PATTERN (insn) = gen_blockage ();
13701 }
13702
83720594
RH		 13703 for (i = 0; ; ++i)
13704 {
83720594
RH		 13705 regno = EH_RETURN_DATA_REGNO (i);
13706 if (regno == INVALID_REGNUM)
13707 break;
13708
89e7058f
AH		 13709 emit_frame_save (frame_reg_rtx, frame_ptr_rtx, reg_mode, regno,
13710 info->ehrd_offset + sp_offset
13711 + reg_size * (int) i,
13712 info->total_size);
83720594
RH		 13713 }
13714 }
13715
9ebbca7d 13716 /* Save lr if we used it. */
f57fe068 13717 if (!WORLD_SAVE_P (info) && info->lr_save_p)
9ebbca7d
GK		 13718 {
13719 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13720 GEN_INT (info->lr_save_offset + sp_offset));
13721 rtx reg = gen_rtx_REG (Pmode, 0);
13722 rtx mem = gen_rtx_MEM (Pmode, addr);
13723 /* This should not be of rs6000_sr_alias_set, because of
13724 __builtin_return_address. */
f676971a 13725
9ebbca7d 13726 insn = emit_move_insn (mem, reg);
f676971a 13727 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
f8a57be8 13728 NULL_RTX, NULL_RTX);
9ebbca7d
GK		 13729 }
13730
13731 /* Save CR if we use any that must be preserved. */
f57fe068 13732 if (!WORLD_SAVE_P (info) && info->cr_save_p)
9ebbca7d
GK		 13733 {
13734 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13735 GEN_INT (info->cr_save_offset + sp_offset));
13736 rtx mem = gen_rtx_MEM (SImode, addr);
f8a57be8
GK		 13737 /* See the large comment above about why CR2_REGNO is used. */
13738 rtx magic_eh_cr_reg = gen_rtx_REG (SImode, CR2_REGNO);
ba4828e0
RK		 13739
13740 set_mem_alias_set (mem, rs6000_sr_alias_set);
9ebbca7d
GK		 13741
13742 /* If r12 was used to hold the original sp, copy cr into r0 now
13743 that it's free. */
13744 if (REGNO (frame_reg_rtx) == 12)
13745 {
f8a57be8
GK		 13746 rtx set;
13747
9ebbca7d 13748 cr_save_rtx = gen_rtx_REG (SImode, 0);
f8a57be8
GK		 13749 insn = emit_insn (gen_movesi_from_cr (cr_save_rtx));
13750 RTX_FRAME_RELATED_P (insn) = 1;
13751 set = gen_rtx_SET (VOIDmode, cr_save_rtx, magic_eh_cr_reg);
13752 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
13753 set,
13754 REG_NOTES (insn));
f676971a 13755
9ebbca7d
GK		 13756 }
13757 insn = emit_move_insn (mem, cr_save_rtx);
13758
f676971a 13759 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
f8a57be8 13760 NULL_RTX, NULL_RTX);
9ebbca7d
GK		 13761 }
13762
f676971a 13763 /* Update stack and set back pointer unless this is V.4,
9ebbca7d 13764 for which it was done previously. */
f57fe068 13765 if (!WORLD_SAVE_P (info) && info->push_p
fc4767bb 13766 && !(DEFAULT_ABI == ABI_V4 || current_function_calls_eh_return))
9ebbca7d
GK		 13767 rs6000_emit_allocate_stack (info->total_size, FALSE);
13768
13769 /* Set frame pointer, if needed. */
13770 if (frame_pointer_needed)
13771 {
f676971a 13772 insn = emit_move_insn (gen_rtx_REG (Pmode, FRAME_POINTER_REGNUM),
9ebbca7d
GK		 13773 sp_reg_rtx);
13774 RTX_FRAME_RELATED_P (insn) = 1;
b6c9286a 13775 }
9878760c 13776
1db02437 13777 /* If we are using RS6000_PIC_OFFSET_TABLE_REGNUM, we need to set it up. */
9ebbca7d 13778 if ((TARGET_TOC && TARGET_MINIMAL_TOC && get_pool_size () != 0)
7f970b70
AM		 13779 || (DEFAULT_ABI == ABI_V4
13780 && (flag_pic == 1 || (flag_pic && TARGET_SECURE_PLT))
1db02437 13781 && regs_ever_live[RS6000_PIC_OFFSET_TABLE_REGNUM]))
c4ad648e
AM		 13782 {
13783 /* If emit_load_toc_table will use the link register, we need to save
13784 it. We use R12 for this purpose because emit_load_toc_table
13785 can use register 0. This allows us to use a plain 'blr' to return
13786 from the procedure more often. */
13787 int save_LR_around_toc_setup = (TARGET_ELF
13788 && DEFAULT_ABI != ABI_AIX
13789 && flag_pic
13790 && ! info->lr_save_p
13791 && EDGE_COUNT (EXIT_BLOCK_PTR->preds) > 0);
13792 if (save_LR_around_toc_setup)
13793 {
13794 rtx lr = gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM);
f8a57be8 13795
c4ad648e
AM		 13796 insn = emit_move_insn (frame_ptr_rtx, lr);
13797 rs6000_maybe_dead (insn);
13798 RTX_FRAME_RELATED_P (insn) = 1;
f8a57be8 13799
c4ad648e 13800 rs6000_emit_load_toc_table (TRUE);
f8a57be8 13801
c4ad648e
AM		 13802 insn = emit_move_insn (lr, frame_ptr_rtx);
13803 rs6000_maybe_dead (insn);
13804 RTX_FRAME_RELATED_P (insn) = 1;
13805 }
13806 else
13807 rs6000_emit_load_toc_table (TRUE);
13808 }
ee890fe2 13809
fcce224d 13810#if TARGET_MACHO
ee890fe2
SS		 13811 if (DEFAULT_ABI == ABI_DARWIN
13812 && flag_pic && current_function_uses_pic_offset_table)
13813 {
f8a57be8 13814 rtx lr = gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM);
11abc112 13815 rtx src = machopic_function_base_sym ();
ee890fe2 13816
6d0a8091
DJ		 13817 /* Save and restore LR locally around this call (in R0). */
13818 if (!info->lr_save_p)
13819 rs6000_maybe_dead (emit_move_insn (gen_rtx_REG (Pmode, 0), lr));
13820
f8a57be8 13821 rs6000_maybe_dead (emit_insn (gen_load_macho_picbase (lr, src)));
ee890fe2 13822
f676971a 13823 insn = emit_move_insn (gen_rtx_REG (Pmode,
f8a57be8
GK		 13824 RS6000_PIC_OFFSET_TABLE_REGNUM),
13825 lr);
13826 rs6000_maybe_dead (insn);
6d0a8091
DJ		 13827
13828 if (!info->lr_save_p)
13829 rs6000_maybe_dead (emit_move_insn (lr, gen_rtx_REG (Pmode, 0)));
ee890fe2 13830 }
fcce224d 13831#endif
9ebbca7d
GK		 13832}
13833
9ebbca7d 13834/* Write function prologue. */
a4f6c312 13835
08c148a8 13836static void
f676971a 13837rs6000_output_function_prologue (FILE *file,
a2369ed3 13838 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
9ebbca7d
GK		 13839{
13840 rs6000_stack_t *info = rs6000_stack_info ();
13841
4697a36c
MM		 13842 if (TARGET_DEBUG_STACK)
13843 debug_stack_info (info);
9878760c 13844
a4f6c312
SS		 13845 /* Write .extern for any function we will call to save and restore
13846 fp values. */
13847 if (info->first_fp_reg_save < 64
13848 && !FP_SAVE_INLINE (info->first_fp_reg_save))
4d30c363 13849 fprintf (file, "\t.extern %s%d%s\n\t.extern %s%d%s\n",
4697a36c 13850 SAVE_FP_PREFIX, info->first_fp_reg_save - 32, SAVE_FP_SUFFIX,
a4f6c312
SS		 13851 RESTORE_FP_PREFIX, info->first_fp_reg_save - 32,
13852 RESTORE_FP_SUFFIX);
9878760c 13853
c764f757
RK		 13854 /* Write .extern for AIX common mode routines, if needed. */
13855 if (! TARGET_POWER && ! TARGET_POWERPC && ! common_mode_defined)
13856 {
f6709c70
JW		 13857 fputs ("\t.extern __mulh\n", file);
13858 fputs ("\t.extern __mull\n", file);
13859 fputs ("\t.extern __divss\n", file);
13860 fputs ("\t.extern __divus\n", file);
13861 fputs ("\t.extern __quoss\n", file);
13862 fputs ("\t.extern __quous\n", file);
c764f757
RK		 13863 common_mode_defined = 1;
13864 }
9878760c 13865
9ebbca7d 13866 if (! HAVE_prologue)
979721f8 13867 {
9ebbca7d 13868 start_sequence ();
9dda4cc8 13869
a4f6c312
SS		 13870 /* A NOTE_INSN_DELETED is supposed to be at the start and end of
13871 the "toplevel" insn chain. */
2e040219 13872 emit_note (NOTE_INSN_DELETED);
9ebbca7d 13873 rs6000_emit_prologue ();
2e040219 13874 emit_note (NOTE_INSN_DELETED);
178c3eff 13875
a3c9585f 13876 /* Expand INSN_ADDRESSES so final() doesn't crash. */
178c3eff
DJ		 13877 {
13878 rtx insn;
13879 unsigned addr = 0;
13880 for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
13881 {
13882 INSN_ADDRESSES_NEW (insn, addr);
13883 addr += 4;
13884 }
13885 }
9dda4cc8 13886
9ebbca7d 13887 if (TARGET_DEBUG_STACK)
a4f6c312 13888 debug_rtx_list (get_insns (), 100);
c9d691e9 13889 final (get_insns (), file, FALSE);
9ebbca7d 13890 end_sequence ();
979721f8
MM		 13891 }
13892
9ebbca7d
GK		 13893 rs6000_pic_labelno++;
13894}
f676971a 13895
9ebbca7d 13896/* Emit function epilogue as insns.
9878760c 13897
9ebbca7d
GK		 13898 At present, dwarf2out_frame_debug_expr doesn't understand
13899 register restores, so we don't bother setting RTX_FRAME_RELATED_P
13900 anywhere in the epilogue. Most of the insns below would in any case
13901 need special notes to explain where r11 is in relation to the stack. */
9878760c 13902
9ebbca7d 13903void
a2369ed3 13904rs6000_emit_epilogue (int sibcall)
9ebbca7d
GK		 13905{
13906 rs6000_stack_t *info;
13907 int restoring_FPRs_inline;
13908 int using_load_multiple;
13909 int using_mfcr_multiple;
13910 int use_backchain_to_restore_sp;
13911 int sp_offset = 0;
13912 rtx sp_reg_rtx = gen_rtx_REG (Pmode, 1);
13913 rtx frame_reg_rtx = sp_reg_rtx;
0e67400a 13914 enum machine_mode reg_mode = Pmode;
327e5343 13915 int reg_size = TARGET_32BIT ? 4 : 8;
9ebbca7d
GK		 13916 int i;
13917
c19de7aa
AH		 13918 info = rs6000_stack_info ();
13919
13920 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
a3170dc6
AH		 13921 {
13922 reg_mode = V2SImode;
13923 reg_size = 8;
13924 }
13925
9ebbca7d 13926 using_load_multiple = (TARGET_MULTIPLE && ! TARGET_POWERPC64
c19de7aa
AH		 13927 && (!TARGET_SPE_ABI
13928 || info->spe_64bit_regs_used == 0)
6d0a8091
DJ		 13929 && info->first_gp_reg_save < 31
13930 && no_global_regs_above (info->first_gp_reg_save));
9ebbca7d 13931 restoring_FPRs_inline = (sibcall
83720594 13932 || current_function_calls_eh_return
9ebbca7d
GK		 13933 || info->first_fp_reg_save == 64
13934 || FP_SAVE_INLINE (info->first_fp_reg_save));
f676971a 13935 use_backchain_to_restore_sp = (frame_pointer_needed
9ebbca7d
GK		 13936 || current_function_calls_alloca
13937 || info->total_size > 32767);
13938 using_mfcr_multiple = (rs6000_cpu == PROCESSOR_PPC601
13939 || rs6000_cpu == PROCESSOR_PPC603
13940 || rs6000_cpu == PROCESSOR_PPC750
13941 || optimize_size);
13942
f57fe068 13943 if (WORLD_SAVE_P (info))
d62294f5
FJ		 13944 {
13945 int i, j;
13946 char rname[30];
13947 const char *alloc_rname;
13948 rtvec p;
13949
13950 /* eh_rest_world_r10 will return to the location saved in the LR
c4ad648e
AM		 13951 stack slot (which is not likely to be our caller.)
13952 Input: R10 -- stack adjustment. Clobbers R0, R11, R12, R7, R8.
13953 rest_world is similar, except any R10 parameter is ignored.
13954 The exception-handling stuff that was here in 2.95 is no
13955 longer necessary. */
d62294f5
FJ		 13956
13957 p = rtvec_alloc (9
13958 + 1
f676971a 13959 + 32 - info->first_gp_reg_save
c4ad648e
AM		 13960 + LAST_ALTIVEC_REGNO + 1 - info->first_altivec_reg_save
13961 + 63 + 1 - info->first_fp_reg_save);
d62294f5 13962
c4ad648e
AM		 13963 strcpy (rname, ((current_function_calls_eh_return) ?
13964 "*eh_rest_world_r10" : "*rest_world"));
d62294f5
FJ		 13965 alloc_rname = ggc_strdup (rname);
13966
13967 j = 0;
13968 RTVEC_ELT (p, j++) = gen_rtx_RETURN (VOIDmode);
13969 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode,
c4ad648e
AM		 13970 gen_rtx_REG (Pmode,
13971 LINK_REGISTER_REGNUM));
d62294f5 13972 RTVEC_ELT (p, j++)
c4ad648e 13973 = gen_rtx_USE (VOIDmode, gen_rtx_SYMBOL_REF (Pmode, alloc_rname));
d62294f5 13974 /* The instruction pattern requires a clobber here;
c4ad648e 13975 it is shared with the restVEC helper. */
d62294f5 13976 RTVEC_ELT (p, j++)
c4ad648e 13977 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 11));
d62294f5
FJ		 13978
13979 {
c4ad648e
AM		 13980 /* CR register traditionally saved as CR2. */
13981 rtx reg = gen_rtx_REG (reg_mode, CR2_REGNO);
13982 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13983 GEN_INT (info->cr_save_offset));
13984 rtx mem = gen_rtx_MEM (reg_mode, addr);
13985 set_mem_alias_set (mem, rs6000_sr_alias_set);
13986
13987 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
d62294f5
FJ		 13988 }
13989
13990 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
c4ad648e
AM		 13991 {
13992 rtx reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
13993 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13994 GEN_INT (info->gp_save_offset
13995 + reg_size * i));
13996 rtx mem = gen_rtx_MEM (reg_mode, addr);
13997 set_mem_alias_set (mem, rs6000_sr_alias_set);
13998
13999 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
14000 }
d62294f5 14001 for (i = 0; info->first_altivec_reg_save + i <= LAST_ALTIVEC_REGNO; i++)
c4ad648e
AM		 14002 {
14003 rtx reg = gen_rtx_REG (V4SImode, info->first_altivec_reg_save + i);
14004 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14005 GEN_INT (info->altivec_save_offset
14006 + 16 * i));
14007 rtx mem = gen_rtx_MEM (V4SImode, addr);
14008 set_mem_alias_set (mem, rs6000_sr_alias_set);
14009
14010 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
14011 }
d62294f5 14012 for (i = 0; info->first_fp_reg_save + i <= 63; i++)
c4ad648e
AM		 14013 {
14014 rtx reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i);
14015 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14016 GEN_INT (info->fp_save_offset
14017 + 8 * i));
14018 rtx mem = gen_rtx_MEM (DFmode, addr);
14019 set_mem_alias_set (mem, rs6000_sr_alias_set);
14020
14021 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
14022 }
d62294f5 14023 RTVEC_ELT (p, j++)
c4ad648e 14024 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 0));
d62294f5 14025 RTVEC_ELT (p, j++)
c4ad648e 14026 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 12));
d62294f5 14027 RTVEC_ELT (p, j++)
c4ad648e 14028 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 7));
d62294f5 14029 RTVEC_ELT (p, j++)
c4ad648e 14030 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 8));
d62294f5 14031 RTVEC_ELT (p, j++)
c4ad648e 14032 = gen_rtx_USE (VOIDmode, gen_rtx_REG (SImode, 10));
d62294f5
FJ		 14033 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
14034
14035 return;
14036 }
14037
9ebbca7d
GK		 14038 /* If we have a frame pointer, a call to alloca, or a large stack
14039 frame, restore the old stack pointer using the backchain. Otherwise,
14040 we know what size to update it with. */
14041 if (use_backchain_to_restore_sp)
bacbde18 14042 {
9ebbca7d
GK		 14043 /* Under V.4, don't reset the stack pointer until after we're done
14044 loading the saved registers. */
f607bc57 14045 if (DEFAULT_ABI == ABI_V4)
9ebbca7d 14046 frame_reg_rtx = gen_rtx_REG (Pmode, 11);
4697a36c 14047
9ebbca7d
GK		 14048 emit_move_insn (frame_reg_rtx,
14049 gen_rtx_MEM (Pmode, sp_reg_rtx));
f676971a 14050
bacbde18 14051 }
9ebbca7d 14052 else if (info->push_p)
85638c0d 14053 {
fc4767bb
JJ		 14054 if (DEFAULT_ABI == ABI_V4
14055 || current_function_calls_eh_return)
9ebbca7d
GK		 14056 sp_offset = info->total_size;
14057 else
14058 {
14059 emit_insn (TARGET_32BIT
14060 ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx,
14061 GEN_INT (info->total_size))
14062 : gen_adddi3 (sp_reg_rtx, sp_reg_rtx,
14063 GEN_INT (info->total_size)));
14064 }
85638c0d 14065 }
f676971a 14066
9aa86737
AH		 14067 /* Restore AltiVec registers if needed. */
14068 if (TARGET_ALTIVEC_ABI && info->altivec_size != 0)
14069 {
14070 int i;
14071
14072 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
14073 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
14074 {
14075 rtx addr, areg, mem;
14076
14077 areg = gen_rtx_REG (Pmode, 0);
14078 emit_move_insn
14079 (areg, GEN_INT (info->altivec_save_offset
14080 + sp_offset
14081 + 16 * (i - info->first_altivec_reg_save)));
14082
14083 /* AltiVec addressing mode is [reg+reg]. */
14084 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, areg);
14085 mem = gen_rtx_MEM (V4SImode, addr);
14086 set_mem_alias_set (mem, rs6000_sr_alias_set);
14087
14088 emit_move_insn (gen_rtx_REG (V4SImode, i), mem);
14089 }
14090 }
14091
14092 /* Restore VRSAVE if needed. */
44688022 14093 if (TARGET_ALTIVEC && TARGET_ALTIVEC_VRSAVE
4d774ff8 14094 && info->vrsave_mask != 0)
9aa86737
AH		 14095 {
14096 rtx addr, mem, reg;
14097
14098 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14099 GEN_INT (info->vrsave_save_offset + sp_offset));
14100 mem = gen_rtx_MEM (SImode, addr);
14101 set_mem_alias_set (mem, rs6000_sr_alias_set);
14102 reg = gen_rtx_REG (SImode, 12);
14103 emit_move_insn (reg, mem);
14104
14105 emit_insn (generate_set_vrsave (reg, info, 1));
14106 }
14107
9ebbca7d
GK		 14108 /* Get the old lr if we saved it. */
14109 if (info->lr_save_p)
b6c9286a 14110 {
a3170dc6
AH		 14111 rtx mem = gen_frame_mem_offset (Pmode, frame_reg_rtx,
14112 info->lr_save_offset + sp_offset);
ba4828e0
RK		 14113
14114 set_mem_alias_set (mem, rs6000_sr_alias_set);
b6c9286a 14115
9ebbca7d 14116 emit_move_insn (gen_rtx_REG (Pmode, 0), mem);
b6c9286a 14117 }
f676971a 14118
9ebbca7d
GK		 14119 /* Get the old cr if we saved it. */
14120 if (info->cr_save_p)
14121 {
14122 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14123 GEN_INT (info->cr_save_offset + sp_offset));
14124 rtx mem = gen_rtx_MEM (SImode, addr);
ba4828e0
RK		 14125
14126 set_mem_alias_set (mem, rs6000_sr_alias_set);
b6c9286a 14127
9ebbca7d
GK		 14128 emit_move_insn (gen_rtx_REG (SImode, 12), mem);
14129 }
f676971a 14130
9ebbca7d 14131 /* Set LR here to try to overlap restores below. */
4697a36c 14132 if (info->lr_save_p)
9ebbca7d
GK		 14133 emit_move_insn (gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM),
14134 gen_rtx_REG (Pmode, 0));
f676971a 14135
83720594
RH		 14136 /* Load exception handler data registers, if needed. */
14137 if (current_function_calls_eh_return)
14138 {
78e1b90d
DE		 14139 unsigned int i, regno;
14140
fc4767bb
JJ		 14141 if (TARGET_AIX)
14142 {
14143 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14144 GEN_INT (sp_offset + 5 * reg_size));
14145 rtx mem = gen_rtx_MEM (reg_mode, addr);
14146
14147 set_mem_alias_set (mem, rs6000_sr_alias_set);
14148
14149 emit_move_insn (gen_rtx_REG (reg_mode, 2), mem);
14150 }
14151
83720594
RH		 14152 for (i = 0; ; ++i)
14153 {
a3170dc6 14154 rtx mem;
83720594
RH		 14155
14156 regno = EH_RETURN_DATA_REGNO (i);
14157 if (regno == INVALID_REGNUM)
14158 break;
14159
a3170dc6
AH		 14160 mem = gen_frame_mem_offset (reg_mode, frame_reg_rtx,
14161 info->ehrd_offset + sp_offset
14162 + reg_size * (int) i);
ba4828e0 14163 set_mem_alias_set (mem, rs6000_sr_alias_set);
83720594
RH		 14164
14165 emit_move_insn (gen_rtx_REG (reg_mode, regno), mem);
14166 }
14167 }
f676971a 14168
9ebbca7d
GK		 14169 /* Restore GPRs. This is done as a PARALLEL if we are using
14170 the load-multiple instructions. */
14171 if (using_load_multiple)
979721f8 14172 {
9ebbca7d
GK		 14173 rtvec p;
14174 p = rtvec_alloc (32 - info->first_gp_reg_save);
14175 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
979721f8 14176 {
f676971a
EC		 14177 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14178 GEN_INT (info->gp_save_offset
14179 + sp_offset
9ebbca7d
GK		 14180 + reg_size * i));
14181 rtx mem = gen_rtx_MEM (reg_mode, addr);
ba4828e0
RK		 14182
14183 set_mem_alias_set (mem, rs6000_sr_alias_set);
9ebbca7d 14184
f676971a 14185 RTVEC_ELT (p, i) =
9ebbca7d
GK		 14186 gen_rtx_SET (VOIDmode,
14187 gen_rtx_REG (reg_mode, info->first_gp_reg_save + i),
14188 mem);
979721f8 14189 }
9ebbca7d 14190 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
979721f8 14191 }
9ebbca7d
GK		 14192 else
14193 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
6d0a8091
DJ		 14194 if ((regs_ever_live[info->first_gp_reg_save + i]
14195 && (!call_used_regs[info->first_gp_reg_save + i]
14196 || (i + info->first_gp_reg_save == RS6000_PIC_OFFSET_TABLE_REGNUM
b4db40bf 14197 && TARGET_TOC && TARGET_MINIMAL_TOC)))
6d0a8091 14198 || (i + info->first_gp_reg_save == RS6000_PIC_OFFSET_TABLE_REGNUM
14f00213 14199 && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0)
f607bc57 14200 || (DEFAULT_ABI == ABI_DARWIN && flag_pic))))
9ebbca7d 14201 {
f676971a
EC		 14202 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14203 GEN_INT (info->gp_save_offset
14204 + sp_offset
9ebbca7d
GK		 14205 + reg_size * i));
14206 rtx mem = gen_rtx_MEM (reg_mode, addr);
ba4828e0 14207
a3170dc6 14208 /* Restore 64-bit quantities for SPE. */
c19de7aa 14209 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
a3170dc6
AH		 14210 {
14211 int offset = info->spe_gp_save_offset + sp_offset + 8 * i;
14212 rtx b;
14213
14214 if (!SPE_CONST_OFFSET_OK (offset))
14215 {
14216 b = gen_rtx_REG (Pmode, FIXED_SCRATCH);
14217 emit_move_insn (b, GEN_INT (offset));
14218 }
14219 else
14220 b = GEN_INT (offset);
14221
14222 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, b);
14223 mem = gen_rtx_MEM (V2SImode, addr);
14224 }
14225
ba4828e0 14226 set_mem_alias_set (mem, rs6000_sr_alias_set);
9ebbca7d 14227
f676971a 14228 emit_move_insn (gen_rtx_REG (reg_mode,
a3170dc6 14229 info->first_gp_reg_save + i), mem);
9ebbca7d 14230 }
9878760c 14231
9ebbca7d
GK		 14232 /* Restore fpr's if we need to do it without calling a function. */
14233 if (restoring_FPRs_inline)
14234 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
f676971a 14235 if ((regs_ever_live[info->first_fp_reg_save+i]
9ebbca7d
GK		 14236 && ! call_used_regs[info->first_fp_reg_save+i]))
14237 {
14238 rtx addr, mem;
14239 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
f676971a
EC		 14240 GEN_INT (info->fp_save_offset
14241 + sp_offset
a4f6c312 14242 + 8 * i));
9ebbca7d 14243 mem = gen_rtx_MEM (DFmode, addr);
ba4828e0 14244 set_mem_alias_set (mem, rs6000_sr_alias_set);
9ebbca7d 14245
f676971a 14246 emit_move_insn (gen_rtx_REG (DFmode,
9ebbca7d
GK		 14247 info->first_fp_reg_save + i),
14248 mem);
14249 }
8d30c4ee 14250
9ebbca7d
GK		 14251 /* If we saved cr, restore it here. Just those that were used. */
14252 if (info->cr_save_p)
979721f8 14253 {
9ebbca7d 14254 rtx r12_rtx = gen_rtx_REG (SImode, 12);
e35b9579 14255 int count = 0;
f676971a 14256
9ebbca7d 14257 if (using_mfcr_multiple)
979721f8 14258 {
9ebbca7d
GK		 14259 for (i = 0; i < 8; i++)
14260 if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i])
e35b9579 14261 count++;
37409796 14262 gcc_assert (count);
e35b9579
GK		 14263 }
14264
14265 if (using_mfcr_multiple && count > 1)
14266 {
14267 rtvec p;
14268 int ndx;
f676971a 14269
e35b9579 14270 p = rtvec_alloc (count);
9ebbca7d 14271
e35b9579 14272 ndx = 0;
9ebbca7d
GK		 14273 for (i = 0; i < 8; i++)
14274 if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i])
14275 {
14276 rtvec r = rtvec_alloc (2);
14277 RTVEC_ELT (r, 0) = r12_rtx;
14278 RTVEC_ELT (r, 1) = GEN_INT (1 << (7-i));
e35b9579 14279 RTVEC_ELT (p, ndx) =
f676971a 14280 gen_rtx_SET (VOIDmode, gen_rtx_REG (CCmode, CR0_REGNO+i),
615158e2 14281 gen_rtx_UNSPEC (CCmode, r, UNSPEC_MOVESI_TO_CR));
e35b9579 14282 ndx++;
9ebbca7d
GK		 14283 }
14284 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
37409796 14285 gcc_assert (ndx == count);
979721f8
MM		 14286 }
14287 else
9ebbca7d
GK		 14288 for (i = 0; i < 8; i++)
14289 if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i])
979721f8 14290 {
f676971a 14291 emit_insn (gen_movsi_to_cr_one (gen_rtx_REG (CCmode,
9ebbca7d
GK		 14292 CR0_REGNO+i),
14293 r12_rtx));
979721f8 14294 }
979721f8
MM		 14295 }
14296
9ebbca7d
GK		 14297 /* If this is V.4, unwind the stack pointer after all of the loads
14298 have been done. We need to emit a block here so that sched
14299 doesn't decide to move the sp change before the register restores
14300 (which may not have any obvious dependency on the stack). This
14301 doesn't hurt performance, because there is no scheduling that can
14302 be done after this point. */
fc4767bb
JJ		 14303 if (DEFAULT_ABI == ABI_V4
14304 || current_function_calls_eh_return)
b6c9286a 14305 {
9ebbca7d 14306 if (frame_reg_rtx != sp_reg_rtx)
c4ad648e 14307 rs6000_emit_stack_tie ();
b6c9286a 14308
9ebbca7d 14309 if (use_backchain_to_restore_sp)
b6c9286a 14310 {
9ebbca7d 14311 emit_move_insn (sp_reg_rtx, frame_reg_rtx);
b6c9286a 14312 }
9ebbca7d 14313 else if (sp_offset != 0)
13f1623b 14314 {
5b71a4e7 14315 emit_insn (TARGET_32BIT
9ebbca7d
GK		 14316 ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx,
14317 GEN_INT (sp_offset))
14318 : gen_adddi3 (sp_reg_rtx, sp_reg_rtx,
14319 GEN_INT (sp_offset)));
13f1623b 14320 }
9ebbca7d 14321 }
b6c9286a 14322
83720594
RH		 14323 if (current_function_calls_eh_return)
14324 {
14325 rtx sa = EH_RETURN_STACKADJ_RTX;
5b71a4e7 14326 emit_insn (TARGET_32BIT
83720594
RH		 14327 ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx, sa)
14328 : gen_adddi3 (sp_reg_rtx, sp_reg_rtx, sa));
14329 }
14330
9ebbca7d
GK		 14331 if (!sibcall)
14332 {
14333 rtvec p;
14334 if (! restoring_FPRs_inline)
14335 p = rtvec_alloc (3 + 64 - info->first_fp_reg_save);
14336 else
14337 p = rtvec_alloc (2);
b6c9286a 14338
e35b9579 14339 RTVEC_ELT (p, 0) = gen_rtx_RETURN (VOIDmode);
f676971a
EC		 14340 RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode,
14341 gen_rtx_REG (Pmode,
9ebbca7d 14342 LINK_REGISTER_REGNUM));
9ebbca7d
GK		 14343
14344 /* If we have to restore more than two FP registers, branch to the
14345 restore function. It will return to our caller. */
14346 if (! restoring_FPRs_inline)
14347 {
14348 int i;
14349 char rname[30];
520a57c8 14350 const char *alloc_rname;
979721f8 14351
f676971a 14352 sprintf (rname, "%s%d%s", RESTORE_FP_PREFIX,
9ebbca7d 14353 info->first_fp_reg_save - 32, RESTORE_FP_SUFFIX);
a8a05998 14354 alloc_rname = ggc_strdup (rname);
9ebbca7d
GK		 14355 RTVEC_ELT (p, 2) = gen_rtx_USE (VOIDmode,
14356 gen_rtx_SYMBOL_REF (Pmode,
14357 alloc_rname));
b6c9286a 14358
9ebbca7d
GK		 14359 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
14360 {
14361 rtx addr, mem;
14362 addr = gen_rtx_PLUS (Pmode, sp_reg_rtx,
14363 GEN_INT (info->fp_save_offset + 8*i));
14364 mem = gen_rtx_MEM (DFmode, addr);
ba4828e0 14365 set_mem_alias_set (mem, rs6000_sr_alias_set);
9ebbca7d 14366
f676971a 14367 RTVEC_ELT (p, i+3) =
9ebbca7d
GK		 14368 gen_rtx_SET (VOIDmode,
14369 gen_rtx_REG (DFmode, info->first_fp_reg_save + i),
14370 mem);
b6c9286a
MM		 14371 }
14372 }
f676971a 14373
9ebbca7d 14374 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
3daf36a4 14375 }
9878760c
RK		 14376}
14377
14378/* Write function epilogue. */
14379
08c148a8 14380static void
f676971a 14381rs6000_output_function_epilogue (FILE *file,
a2369ed3 14382 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
9878760c 14383{
4697a36c 14384 rs6000_stack_t *info = rs6000_stack_info ();
9878760c 14385
9ebbca7d 14386 if (! HAVE_epilogue)
9878760c 14387 {
9ebbca7d
GK		 14388 rtx insn = get_last_insn ();
14389 /* If the last insn was a BARRIER, we don't have to write anything except
14390 the trace table. */
14391 if (GET_CODE (insn) == NOTE)
14392 insn = prev_nonnote_insn (insn);
14393 if (insn == 0 || GET_CODE (insn) != BARRIER)
4697a36c 14394 {
9ebbca7d
GK		 14395 /* This is slightly ugly, but at least we don't have two
14396 copies of the epilogue-emitting code. */
14397 start_sequence ();
14398
14399 /* A NOTE_INSN_DELETED is supposed to be at the start
14400 and end of the "toplevel" insn chain. */
2e040219 14401 emit_note (NOTE_INSN_DELETED);
9ebbca7d 14402 rs6000_emit_epilogue (FALSE);
2e040219 14403 emit_note (NOTE_INSN_DELETED);
9ebbca7d 14404
a3c9585f 14405 /* Expand INSN_ADDRESSES so final() doesn't crash. */
178c3eff
DJ		 14406 {
14407 rtx insn;
14408 unsigned addr = 0;
14409 for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
14410 {
14411 INSN_ADDRESSES_NEW (insn, addr);
14412 addr += 4;
14413 }
14414 }
14415
9ebbca7d 14416 if (TARGET_DEBUG_STACK)
a4f6c312 14417 debug_rtx_list (get_insns (), 100);
c9d691e9 14418 final (get_insns (), file, FALSE);
9ebbca7d 14419 end_sequence ();
4697a36c 14420 }
9878760c 14421 }
b4ac57ab 14422
efdba735
SH		 14423#if TARGET_MACHO
14424 macho_branch_islands ();
0e5da0be
GK		 14425 /* Mach-O doesn't support labels at the end of objects, so if
14426 it looks like we might want one, insert a NOP. */
14427 {
14428 rtx insn = get_last_insn ();
14429 while (insn
14430 && NOTE_P (insn)
14431 && NOTE_LINE_NUMBER (insn) != NOTE_INSN_DELETED_LABEL)
14432 insn = PREV_INSN (insn);
f676971a
EC		 14433 if (insn
14434 && (LABEL_P (insn)
0e5da0be
GK		 14435 || (NOTE_P (insn)
14436 && NOTE_LINE_NUMBER (insn) == NOTE_INSN_DELETED_LABEL)))
14437 fputs ("\tnop\n", file);
14438 }
14439#endif
14440
9b30bae2 14441 /* Output a traceback table here. See /usr/include/sys/debug.h for info
314fc5a9
ILT		 14442 on its format.
14443
14444 We don't output a traceback table if -finhibit-size-directive was
14445 used. The documentation for -finhibit-size-directive reads
14446 ``don't output a @code{.size} assembler directive, or anything
14447 else that would cause trouble if the function is split in the
14448 middle, and the two halves are placed at locations far apart in
14449 memory.'' The traceback table has this property, since it
14450 includes the offset from the start of the function to the
4d30c363
MM		 14451 traceback table itself.
14452
14453 System V.4 Powerpc's (and the embedded ABI derived from it) use a
b6c9286a 14454 different traceback table. */
57ac7be9
AM		 14455 if (DEFAULT_ABI == ABI_AIX && ! flag_inhibit_size_directive
14456 && rs6000_traceback != traceback_none)
9b30bae2 14457 {
69c75916 14458 const char *fname = NULL;
3ac88239 14459 const char *language_string = lang_hooks.name;
6041bf2f 14460 int fixed_parms = 0, float_parms = 0, parm_info = 0;
314fc5a9 14461 int i;
57ac7be9
AM		 14462 int optional_tbtab;
14463
14464 if (rs6000_traceback == traceback_full)
14465 optional_tbtab = 1;
14466 else if (rs6000_traceback == traceback_part)
14467 optional_tbtab = 0;
14468 else
14469 optional_tbtab = !optimize_size && !TARGET_ELF;
314fc5a9 14470
69c75916
AM		 14471 if (optional_tbtab)
14472 {
14473 fname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
14474 while (*fname == '.') /* V.4 encodes . in the name */
14475 fname++;
14476
14477 /* Need label immediately before tbtab, so we can compute
14478 its offset from the function start. */
14479 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT");
14480 ASM_OUTPUT_LABEL (file, fname);
14481 }
314fc5a9
ILT		 14482
14483 /* The .tbtab pseudo-op can only be used for the first eight
14484 expressions, since it can't handle the possibly variable
14485 length fields that follow. However, if you omit the optional
14486 fields, the assembler outputs zeros for all optional fields
14487 anyways, giving each variable length field is minimum length
14488 (as defined in sys/debug.h). Thus we can not use the .tbtab
14489 pseudo-op at all. */
14490
14491 /* An all-zero word flags the start of the tbtab, for debuggers
14492 that have to find it by searching forward from the entry
14493 point or from the current pc. */
19d2d16f 14494 fputs ("\t.long 0\n", file);
314fc5a9
ILT		 14495
14496 /* Tbtab format type. Use format type 0. */
19d2d16f 14497 fputs ("\t.byte 0,", file);
314fc5a9 14498
5fc921c1
DE		 14499 /* Language type. Unfortunately, there does not seem to be any
14500 official way to discover the language being compiled, so we
14501 use language_string.
14502 C is 0. Fortran is 1. Pascal is 2. Ada is 3. C++ is 9.
14503 Java is 13. Objective-C is 14. */
14504 if (! strcmp (language_string, "GNU C"))
314fc5a9 14505 i = 0;
6de9cd9a
DN		 14506 else if (! strcmp (language_string, "GNU F77")
14507 || ! strcmp (language_string, "GNU F95"))
314fc5a9 14508 i = 1;
8b83775b 14509 else if (! strcmp (language_string, "GNU Pascal"))
314fc5a9 14510 i = 2;
5fc921c1
DE		 14511 else if (! strcmp (language_string, "GNU Ada"))
14512 i = 3;
314fc5a9
ILT		 14513 else if (! strcmp (language_string, "GNU C++"))
14514 i = 9;
9517ead8
AG		 14515 else if (! strcmp (language_string, "GNU Java"))
14516 i = 13;
5fc921c1
DE		 14517 else if (! strcmp (language_string, "GNU Objective-C"))
14518 i = 14;
314fc5a9 14519 else
37409796 14520 gcc_unreachable ();
314fc5a9
ILT		 14521 fprintf (file, "%d,", i);
14522
14523 /* 8 single bit fields: global linkage (not set for C extern linkage,
14524 apparently a PL/I convention?), out-of-line epilogue/prologue, offset
14525 from start of procedure stored in tbtab, internal function, function
14526 has controlled storage, function has no toc, function uses fp,
14527 function logs/aborts fp operations. */
14528 /* Assume that fp operations are used if any fp reg must be saved. */
6041bf2f
DE		 14529 fprintf (file, "%d,",
14530 (optional_tbtab << 5) | ((info->first_fp_reg_save != 64) << 1));
314fc5a9
ILT		 14531
14532 /* 6 bitfields: function is interrupt handler, name present in
14533 proc table, function calls alloca, on condition directives
14534 (controls stack walks, 3 bits), saves condition reg, saves
14535 link reg. */
14536 /* The `function calls alloca' bit seems to be set whenever reg 31 is
14537 set up as a frame pointer, even when there is no alloca call. */
14538 fprintf (file, "%d,",
6041bf2f
DE		 14539 ((optional_tbtab << 6)
14540 | ((optional_tbtab & frame_pointer_needed) << 5)
14541 | (info->cr_save_p << 1)
14542 | (info->lr_save_p)));
314fc5a9 14543
6041bf2f 14544 /* 3 bitfields: saves backchain, fixup code, number of fpr saved
314fc5a9
ILT		 14545 (6 bits). */
14546 fprintf (file, "%d,",
4697a36c 14547 (info->push_p << 7) | (64 - info->first_fp_reg_save));
314fc5a9
ILT		 14548
14549 /* 2 bitfields: spare bits (2 bits), number of gpr saved (6 bits). */
14550 fprintf (file, "%d,", (32 - first_reg_to_save ()));
14551
6041bf2f
DE		 14552 if (optional_tbtab)
14553 {
14554 /* Compute the parameter info from the function decl argument
14555 list. */
14556 tree decl;
14557 int next_parm_info_bit = 31;
314fc5a9 14558
6041bf2f
DE		 14559 for (decl = DECL_ARGUMENTS (current_function_decl);
14560 decl; decl = TREE_CHAIN (decl))
14561 {
14562 rtx parameter = DECL_INCOMING_RTL (decl);
14563 enum machine_mode mode = GET_MODE (parameter);
314fc5a9 14564
6041bf2f
DE		 14565 if (GET_CODE (parameter) == REG)
14566 {
14567 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
14568 {
14569 int bits;
14570
14571 float_parms++;
14572
37409796
NS		 14573 switch (mode)
14574 {
14575 case SFmode:
14576 bits = 0x2;
14577 break;
14578
14579 case DFmode:
14580 case TFmode:
14581 bits = 0x3;
14582 break;
14583
14584 default:
14585 gcc_unreachable ();
14586 }
6041bf2f
DE		 14587
14588 /* If only one bit will fit, don't or in this entry. */
14589 if (next_parm_info_bit > 0)
14590 parm_info |= (bits << (next_parm_info_bit - 1));
14591 next_parm_info_bit -= 2;
14592 }
14593 else
14594 {
14595 fixed_parms += ((GET_MODE_SIZE (mode)
14596 + (UNITS_PER_WORD - 1))
14597 / UNITS_PER_WORD);
14598 next_parm_info_bit -= 1;
14599 }
14600 }
14601 }
14602 }
314fc5a9
ILT		 14603
14604 /* Number of fixed point parameters. */
14605 /* This is actually the number of words of fixed point parameters; thus
14606 an 8 byte struct counts as 2; and thus the maximum value is 8. */
14607 fprintf (file, "%d,", fixed_parms);
14608
14609 /* 2 bitfields: number of floating point parameters (7 bits), parameters
14610 all on stack. */
14611 /* This is actually the number of fp registers that hold parameters;
14612 and thus the maximum value is 13. */
14613 /* Set parameters on stack bit if parameters are not in their original
14614 registers, regardless of whether they are on the stack? Xlc
14615 seems to set the bit when not optimizing. */
14616 fprintf (file, "%d\n", ((float_parms << 1) | (! optimize)));
14617
6041bf2f
DE		 14618 if (! optional_tbtab)
14619 return;
14620
314fc5a9
ILT		 14621 /* Optional fields follow. Some are variable length. */
14622
14623 /* Parameter types, left adjusted bit fields: 0 fixed, 10 single float,
14624 11 double float. */
14625 /* There is an entry for each parameter in a register, in the order that
14626 they occur in the parameter list. Any intervening arguments on the
14627 stack are ignored. If the list overflows a long (max possible length
14628 34 bits) then completely leave off all elements that don't fit. */
14629 /* Only emit this long if there was at least one parameter. */
14630 if (fixed_parms || float_parms)
14631 fprintf (file, "\t.long %d\n", parm_info);
14632
14633 /* Offset from start of code to tb table. */
19d2d16f 14634 fputs ("\t.long ", file);
314fc5a9 14635 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT");
85b776df
AM		 14636 if (TARGET_AIX)
14637 RS6000_OUTPUT_BASENAME (file, fname);
14638 else
14639 assemble_name (file, fname);
14640 putc ('-', file);
14641 rs6000_output_function_entry (file, fname);
19d2d16f 14642 putc ('\n', file);
314fc5a9
ILT		 14643
14644 /* Interrupt handler mask. */
14645 /* Omit this long, since we never set the interrupt handler bit
14646 above. */
14647
14648 /* Number of CTL (controlled storage) anchors. */
14649 /* Omit this long, since the has_ctl bit is never set above. */
14650
14651 /* Displacement into stack of each CTL anchor. */
14652 /* Omit this list of longs, because there are no CTL anchors. */
14653
14654 /* Length of function name. */
69c75916
AM		 14655 if (*fname == '*')
14656 ++fname;
296b8152 14657 fprintf (file, "\t.short %d\n", (int) strlen (fname));
314fc5a9
ILT		 14658
14659 /* Function name. */
14660 assemble_string (fname, strlen (fname));
14661
14662 /* Register for alloca automatic storage; this is always reg 31.
14663 Only emit this if the alloca bit was set above. */
14664 if (frame_pointer_needed)
19d2d16f 14665 fputs ("\t.byte 31\n", file);
b1765bde
DE		 14666
14667 fputs ("\t.align 2\n", file);
9b30bae2 14668 }
9878760c 14669}
17167fd8 14670\f
a4f6c312
SS		 14671/* A C compound statement that outputs the assembler code for a thunk
14672 function, used to implement C++ virtual function calls with
14673 multiple inheritance. The thunk acts as a wrapper around a virtual
14674 function, adjusting the implicit object parameter before handing
14675 control off to the real function.
14676
14677 First, emit code to add the integer DELTA to the location that
14678 contains the incoming first argument. Assume that this argument
14679 contains a pointer, and is the one used to pass the `this' pointer
14680 in C++. This is the incoming argument *before* the function
14681 prologue, e.g. `%o0' on a sparc. The addition must preserve the
14682 values of all other incoming arguments.
17167fd8
MM		 14683
14684 After the addition, emit code to jump to FUNCTION, which is a
a4f6c312
SS		 14685 `FUNCTION_DECL'. This is a direct pure jump, not a call, and does
14686 not touch the return address. Hence returning from FUNCTION will
14687 return to whoever called the current `thunk'.
17167fd8 14688
a4f6c312
SS		 14689 The effect must be as if FUNCTION had been called directly with the
14690 adjusted first argument. This macro is responsible for emitting
14691 all of the code for a thunk function; output_function_prologue()
14692 and output_function_epilogue() are not invoked.
17167fd8 14693
a4f6c312
SS		 14694 The THUNK_FNDECL is redundant. (DELTA and FUNCTION have already
14695 been extracted from it.) It might possibly be useful on some
14696 targets, but probably not.
17167fd8 14697
a4f6c312
SS		 14698 If you do not define this macro, the target-independent code in the
14699 C++ frontend will generate a less efficient heavyweight thunk that
14700 calls FUNCTION instead of jumping to it. The generic approach does
14701 not support varargs. */
17167fd8 14702
3961e8fe 14703static void
f676971a
EC		 14704rs6000_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
14705 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
a2369ed3 14706 tree function)
17167fd8 14707{
5b71a4e7 14708 rtx this, insn, funexp;
17167fd8 14709
5b71a4e7 14710 reload_completed = 1;
fe3ad572 14711 epilogue_completed = 1;
5b71a4e7 14712 no_new_pseudos = 1;
6429e3be 14713 reset_block_changes ();
56a7189a 14714
5b71a4e7 14715 /* Mark the end of the (empty) prologue. */
2e040219 14716 emit_note (NOTE_INSN_PROLOGUE_END);
17167fd8 14717
5b71a4e7
DE		 14718 /* Find the "this" pointer. If the function returns a structure,
14719 the structure return pointer is in r3. */
61f71b34 14720 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
5b71a4e7 14721 this = gen_rtx_REG (Pmode, 4);
56a7189a 14722 else
5b71a4e7 14723 this = gen_rtx_REG (Pmode, 3);
17167fd8 14724
5b71a4e7
DE		 14725 /* Apply the constant offset, if required. */
14726 if (delta)
14727 {
14728 rtx delta_rtx = GEN_INT (delta);
14729 emit_insn (TARGET_32BIT
14730 ? gen_addsi3 (this, this, delta_rtx)
14731 : gen_adddi3 (this, this, delta_rtx));
17167fd8
MM		 14732 }
14733
5b71a4e7
DE		 14734 /* Apply the offset from the vtable, if required. */
14735 if (vcall_offset)
17167fd8 14736 {
5b71a4e7
DE		 14737 rtx vcall_offset_rtx = GEN_INT (vcall_offset);
14738 rtx tmp = gen_rtx_REG (Pmode, 12);
17167fd8 14739
5b71a4e7 14740 emit_move_insn (tmp, gen_rtx_MEM (Pmode, this));
eeff9307
JJ		 14741 if (((unsigned HOST_WIDE_INT) vcall_offset) + 0x8000 >= 0x10000)
14742 {
14743 emit_insn (TARGET_32BIT
14744 ? gen_addsi3 (tmp, tmp, vcall_offset_rtx)
14745 : gen_adddi3 (tmp, tmp, vcall_offset_rtx));
14746 emit_move_insn (tmp, gen_rtx_MEM (Pmode, tmp));
14747 }
14748 else
14749 {
14750 rtx loc = gen_rtx_PLUS (Pmode, tmp, vcall_offset_rtx);
14751
14752 emit_move_insn (tmp, gen_rtx_MEM (Pmode, loc));
14753 }
5b71a4e7
DE		 14754 emit_insn (TARGET_32BIT
14755 ? gen_addsi3 (this, this, tmp)
14756 : gen_adddi3 (this, this, tmp));
17167fd8
MM		 14757 }
14758
5b71a4e7
DE		 14759 /* Generate a tail call to the target function. */
14760 if (!TREE_USED (function))
14761 {
14762 assemble_external (function);
14763 TREE_USED (function) = 1;
14764 }
14765 funexp = XEXP (DECL_RTL (function), 0);
5b71a4e7 14766 funexp = gen_rtx_MEM (FUNCTION_MODE, funexp);
ee890fe2
SS		 14767
14768#if TARGET_MACHO
ab82a49f 14769 if (MACHOPIC_INDIRECT)
5b71a4e7 14770 funexp = machopic_indirect_call_target (funexp);
ee890fe2 14771#endif
5b71a4e7
DE		 14772
14773 /* gen_sibcall expects reload to convert scratch pseudo to LR so we must
992d08b1 14774 generate sibcall RTL explicitly. */
5b71a4e7
DE		 14775 insn = emit_call_insn (
14776 gen_rtx_PARALLEL (VOIDmode,
14777 gen_rtvec (4,
14778 gen_rtx_CALL (VOIDmode,
14779 funexp, const0_rtx),
14780 gen_rtx_USE (VOIDmode, const0_rtx),
14781 gen_rtx_USE (VOIDmode,
14782 gen_rtx_REG (SImode,
14783 LINK_REGISTER_REGNUM)),
14784 gen_rtx_RETURN (VOIDmode))));
14785 SIBLING_CALL_P (insn) = 1;
14786 emit_barrier ();
14787
14788 /* Run just enough of rest_of_compilation to get the insns emitted.
14789 There's not really enough bulk here to make other passes such as
14790 instruction scheduling worth while. Note that use_thunk calls
14791 assemble_start_function and assemble_end_function. */
14792 insn = get_insns ();
a2855205 14793 insn_locators_initialize ();
5b71a4e7
DE		 14794 shorten_branches (insn);
14795 final_start_function (insn, file, 1);
c9d691e9 14796 final (insn, file, 1);
5b71a4e7
DE		 14797 final_end_function ();
14798
14799 reload_completed = 0;
fe3ad572 14800 epilogue_completed = 0;
5b71a4e7 14801 no_new_pseudos = 0;
9ebbca7d 14802}
9ebbca7d
GK		 14803\f
14804/* A quick summary of the various types of 'constant-pool tables'
14805 under PowerPC:
14806
f676971a 14807 Target Flags Name One table per
9ebbca7d
GK		 14808 AIX (none) AIX TOC object file
14809 AIX -mfull-toc AIX TOC object file
14810 AIX -mminimal-toc AIX minimal TOC translation unit
14811 SVR4/EABI (none) SVR4 SDATA object file
14812 SVR4/EABI -fpic SVR4 pic object file
14813 SVR4/EABI -fPIC SVR4 PIC translation unit
14814 SVR4/EABI -mrelocatable EABI TOC function
14815 SVR4/EABI -maix AIX TOC object file
f676971a 14816 SVR4/EABI -maix -mminimal-toc
9ebbca7d
GK		 14817 AIX minimal TOC translation unit
14818
14819 Name Reg. Set by entries contains:
14820 made by addrs? fp? sum?
14821
14822 AIX TOC 2 crt0 as Y option option
14823 AIX minimal TOC 30 prolog gcc Y Y option
14824 SVR4 SDATA 13 crt0 gcc N Y N
14825 SVR4 pic 30 prolog ld Y not yet N
14826 SVR4 PIC 30 prolog gcc Y option option
14827 EABI TOC 30 prolog gcc Y option option
14828
14829*/
14830
9ebbca7d
GK		 14831/* Hash functions for the hash table. */
14832
14833static unsigned
a2369ed3 14834rs6000_hash_constant (rtx k)
9ebbca7d 14835{
46b33600
RH		 14836 enum rtx_code code = GET_CODE (k);
14837 enum machine_mode mode = GET_MODE (k);
14838 unsigned result = (code << 3) ^ mode;
14839 const char *format;
14840 int flen, fidx;
f676971a 14841
46b33600
RH		 14842 format = GET_RTX_FORMAT (code);
14843 flen = strlen (format);
14844 fidx = 0;
9ebbca7d 14845
46b33600
RH		 14846 switch (code)
14847 {
14848 case LABEL_REF:
14849 return result * 1231 + (unsigned) INSN_UID (XEXP (k, 0));
14850
14851 case CONST_DOUBLE:
14852 if (mode != VOIDmode)
14853 return real_hash (CONST_DOUBLE_REAL_VALUE (k)) * result;
14854 flen = 2;
14855 break;
14856
14857 case CODE_LABEL:
14858 fidx = 3;
14859 break;
14860
14861 default:
14862 break;
14863 }
9ebbca7d
GK		 14864
14865 for (; fidx < flen; fidx++)
14866 switch (format[fidx])
14867 {
14868 case 's':
14869 {
14870 unsigned i, len;
14871 const char *str = XSTR (k, fidx);
14872 len = strlen (str);
14873 result = result * 613 + len;
14874 for (i = 0; i < len; i++)
14875 result = result * 613 + (unsigned) str[i];
17167fd8
MM		 14876 break;
14877 }
9ebbca7d
GK		 14878 case 'u':
14879 case 'e':
14880 result = result * 1231 + rs6000_hash_constant (XEXP (k, fidx));
14881 break;
14882 case 'i':
14883 case 'n':
14884 result = result * 613 + (unsigned) XINT (k, fidx);
14885 break;
14886 case 'w':
14887 if (sizeof (unsigned) >= sizeof (HOST_WIDE_INT))
14888 result = result * 613 + (unsigned) XWINT (k, fidx);
14889 else
14890 {
14891 size_t i;
9390387d 14892 for (i = 0; i < sizeof (HOST_WIDE_INT) / sizeof (unsigned); i++)
9ebbca7d
GK		 14893 result = result * 613 + (unsigned) (XWINT (k, fidx)
14894 >> CHAR_BIT * i);
14895 }
14896 break;
09501938
DE		 14897 case '0':
14898 break;
9ebbca7d 14899 default:
37409796 14900 gcc_unreachable ();
9ebbca7d 14901 }
46b33600 14902
9ebbca7d
GK		 14903 return result;
14904}
14905
14906static unsigned
a2369ed3 14907toc_hash_function (const void *hash_entry)
9ebbca7d 14908{
f676971a 14909 const struct toc_hash_struct *thc =
a9098fd0
GK		 14910 (const struct toc_hash_struct *) hash_entry;
14911 return rs6000_hash_constant (thc->key) ^ thc->key_mode;
9ebbca7d
GK		 14912}
14913
14914/* Compare H1 and H2 for equivalence. */
14915
14916static int
a2369ed3 14917toc_hash_eq (const void *h1, const void *h2)
9ebbca7d
GK		 14918{
14919 rtx r1 = ((const struct toc_hash_struct *) h1)->key;
14920 rtx r2 = ((const struct toc_hash_struct *) h2)->key;
14921
a9098fd0
GK		 14922 if (((const struct toc_hash_struct *) h1)->key_mode
14923 != ((const struct toc_hash_struct *) h2)->key_mode)
14924 return 0;
14925
5692c7bc 14926 return rtx_equal_p (r1, r2);
9ebbca7d
GK		 14927}
14928
28e510bd
MM		 14929/* These are the names given by the C++ front-end to vtables, and
14930 vtable-like objects. Ideally, this logic should not be here;
14931 instead, there should be some programmatic way of inquiring as
14932 to whether or not an object is a vtable. */
14933
14934#define VTABLE_NAME_P(NAME) \
9390387d 14935 (strncmp ("_vt.", name, strlen ("_vt.")) == 0 \
28e510bd
MM		 14936 || strncmp ("_ZTV", name, strlen ("_ZTV")) == 0 \
14937 || strncmp ("_ZTT", name, strlen ("_ZTT")) == 0 \
26be75db 14938 || strncmp ("_ZTI", name, strlen ("_ZTI")) == 0 \
f676971a 14939 || strncmp ("_ZTC", name, strlen ("_ZTC")) == 0)
28e510bd
MM		 14940
14941void
a2369ed3 14942rs6000_output_symbol_ref (FILE *file, rtx x)
28e510bd
MM		 14943{
14944 /* Currently C++ toc references to vtables can be emitted before it
14945 is decided whether the vtable is public or private. If this is
14946 the case, then the linker will eventually complain that there is
f676971a 14947 a reference to an unknown section. Thus, for vtables only,
28e510bd
MM		 14948 we emit the TOC reference to reference the symbol and not the
14949 section. */
14950 const char *name = XSTR (x, 0);
54ee9799 14951
f676971a 14952 if (VTABLE_NAME_P (name))
54ee9799
DE		 14953 {
14954 RS6000_OUTPUT_BASENAME (file, name);
14955 }
14956 else
14957 assemble_name (file, name);
28e510bd
MM		 14958}
14959
a4f6c312
SS		 14960/* Output a TOC entry. We derive the entry name from what is being
14961 written. */
9878760c
RK		 14962
14963void
a2369ed3 14964output_toc (FILE *file, rtx x, int labelno, enum machine_mode mode)
9878760c
RK		 14965{
14966 char buf[256];
3cce094d 14967 const char *name = buf;
ec940faa 14968 const char *real_name;
9878760c
RK		 14969 rtx base = x;
14970 int offset = 0;
14971
37409796 14972 gcc_assert (!TARGET_NO_TOC);
4697a36c 14973
9ebbca7d
GK		 14974 /* When the linker won't eliminate them, don't output duplicate
14975 TOC entries (this happens on AIX if there is any kind of TOC,
17211ab5
GK		 14976 and on SVR4 under -fPIC or -mrelocatable). Don't do this for
14977 CODE_LABELs. */
14978 if (TARGET_TOC && GET_CODE (x) != LABEL_REF)
9ebbca7d
GK		 14979 {
14980 struct toc_hash_struct *h;
14981 void * * found;
f676971a 14982
17211ab5 14983 /* Create toc_hash_table. This can't be done at OVERRIDE_OPTIONS
c4ad648e 14984 time because GGC is not initialized at that point. */
17211ab5 14985 if (toc_hash_table == NULL)
f676971a 14986 toc_hash_table = htab_create_ggc (1021, toc_hash_function,
17211ab5
GK		 14987 toc_hash_eq, NULL);
14988
9ebbca7d
GK		 14989 h = ggc_alloc (sizeof (*h));
14990 h->key = x;
a9098fd0 14991 h->key_mode = mode;
9ebbca7d 14992 h->labelno = labelno;
f676971a 14993
9ebbca7d
GK		 14994 found = htab_find_slot (toc_hash_table, h, 1);
14995 if (*found == NULL)
14996 *found = h;
f676971a 14997 else /* This is indeed a duplicate.
9ebbca7d
GK		 14998 Set this label equal to that label. */
14999 {
15000 fputs ("\t.set ", file);
15001 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC");
15002 fprintf (file, "%d,", labelno);
15003 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC");
f676971a 15004 fprintf (file, "%d\n", ((*(const struct toc_hash_struct **)
9ebbca7d
GK		 15005 found)->labelno));
15006 return;
15007 }
15008 }
15009
15010 /* If we're going to put a double constant in the TOC, make sure it's
15011 aligned properly when strict alignment is on. */
ff1720ed
RK		 15012 if (GET_CODE (x) == CONST_DOUBLE
15013 && STRICT_ALIGNMENT
a9098fd0 15014 && GET_MODE_BITSIZE (mode) >= 64
ff1720ed
RK		 15015 && ! (TARGET_NO_FP_IN_TOC && ! TARGET_MINIMAL_TOC)) {
15016 ASM_OUTPUT_ALIGN (file, 3);
15017 }
15018
4977bab6 15019 (*targetm.asm_out.internal_label) (file, "LC", labelno);
9878760c 15020
37c37a57
RK		 15021 /* Handle FP constants specially. Note that if we have a minimal
15022 TOC, things we put here aren't actually in the TOC, so we can allow
15023 FP constants. */
fcce224d
DE		 15024 if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == TFmode)
15025 {
15026 REAL_VALUE_TYPE rv;
15027 long k[4];
15028
15029 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
15030 REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv, k);
15031
15032 if (TARGET_64BIT)
15033 {
15034 if (TARGET_MINIMAL_TOC)
15035 fputs (DOUBLE_INT_ASM_OP, file);
15036 else
15037 fprintf (file, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
15038 k[0] & 0xffffffff, k[1] & 0xffffffff,
15039 k[2] & 0xffffffff, k[3] & 0xffffffff);
15040 fprintf (file, "0x%lx%08lx,0x%lx%08lx\n",
15041 k[0] & 0xffffffff, k[1] & 0xffffffff,
15042 k[2] & 0xffffffff, k[3] & 0xffffffff);
15043 return;
15044 }
15045 else
15046 {
15047 if (TARGET_MINIMAL_TOC)
15048 fputs ("\t.long ", file);
15049 else
15050 fprintf (file, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
15051 k[0] & 0xffffffff, k[1] & 0xffffffff,
15052 k[2] & 0xffffffff, k[3] & 0xffffffff);
15053 fprintf (file, "0x%lx,0x%lx,0x%lx,0x%lx\n",
15054 k[0] & 0xffffffff, k[1] & 0xffffffff,
15055 k[2] & 0xffffffff, k[3] & 0xffffffff);
15056 return;
15057 }
15058 }
15059 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == DFmode)
9878760c 15060 {
042259f2
DE		 15061 REAL_VALUE_TYPE rv;
15062 long k[2];
0adc764e 15063
042259f2
DE		 15064 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
15065 REAL_VALUE_TO_TARGET_DOUBLE (rv, k);
31bfaa0b 15066
13ded975
DE		 15067 if (TARGET_64BIT)
15068 {
15069 if (TARGET_MINIMAL_TOC)
2bfcf297 15070 fputs (DOUBLE_INT_ASM_OP, file);
13ded975 15071 else
2f0552b6
AM		 15072 fprintf (file, "\t.tc FD_%lx_%lx[TC],",
15073 k[0] & 0xffffffff, k[1] & 0xffffffff);
15074 fprintf (file, "0x%lx%08lx\n",
15075 k[0] & 0xffffffff, k[1] & 0xffffffff);
13ded975
DE		 15076 return;
15077 }
1875cc88 15078 else
13ded975
DE		 15079 {
15080 if (TARGET_MINIMAL_TOC)
2bfcf297 15081 fputs ("\t.long ", file);
13ded975 15082 else
2f0552b6
AM		 15083 fprintf (file, "\t.tc FD_%lx_%lx[TC],",
15084 k[0] & 0xffffffff, k[1] & 0xffffffff);
15085 fprintf (file, "0x%lx,0x%lx\n",
15086 k[0] & 0xffffffff, k[1] & 0xffffffff);
13ded975
DE		 15087 return;
15088 }
9878760c 15089 }
a9098fd0 15090 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == SFmode)
9878760c 15091 {
042259f2
DE		 15092 REAL_VALUE_TYPE rv;
15093 long l;
9878760c 15094
042259f2
DE		 15095 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
15096 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
15097
31bfaa0b
DE		 15098 if (TARGET_64BIT)
15099 {
15100 if (TARGET_MINIMAL_TOC)
2bfcf297 15101 fputs (DOUBLE_INT_ASM_OP, file);
31bfaa0b 15102 else
2f0552b6
AM		 15103 fprintf (file, "\t.tc FS_%lx[TC],", l & 0xffffffff);
15104 fprintf (file, "0x%lx00000000\n", l & 0xffffffff);
31bfaa0b
DE		 15105 return;
15106 }
042259f2 15107 else
31bfaa0b
DE		 15108 {
15109 if (TARGET_MINIMAL_TOC)
2bfcf297 15110 fputs ("\t.long ", file);
31bfaa0b 15111 else
2f0552b6
AM		 15112 fprintf (file, "\t.tc FS_%lx[TC],", l & 0xffffffff);
15113 fprintf (file, "0x%lx\n", l & 0xffffffff);
31bfaa0b
DE		 15114 return;
15115 }
042259f2 15116 }
f176e826 15117 else if (GET_MODE (x) == VOIDmode
a9098fd0 15118 && (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE))
042259f2 15119 {
e2c953b6 15120 unsigned HOST_WIDE_INT low;
042259f2
DE		 15121 HOST_WIDE_INT high;
15122
15123 if (GET_CODE (x) == CONST_DOUBLE)
15124 {
15125 low = CONST_DOUBLE_LOW (x);
15126 high = CONST_DOUBLE_HIGH (x);
15127 }
15128 else
15129#if HOST_BITS_PER_WIDE_INT == 32
15130 {
15131 low = INTVAL (x);
0858c623 15132 high = (low & 0x80000000) ? ~0 : 0;
042259f2
DE		 15133 }
15134#else
15135 {
c4ad648e
AM		 15136 low = INTVAL (x) & 0xffffffff;
15137 high = (HOST_WIDE_INT) INTVAL (x) >> 32;
042259f2
DE		 15138 }
15139#endif
9878760c 15140
a9098fd0
GK		 15141 /* TOC entries are always Pmode-sized, but since this
15142 is a bigendian machine then if we're putting smaller
15143 integer constants in the TOC we have to pad them.
15144 (This is still a win over putting the constants in
15145 a separate constant pool, because then we'd have
02a4ec28
FS		 15146 to have both a TOC entry _and_ the actual constant.)
15147
15148 For a 32-bit target, CONST_INT values are loaded and shifted
15149 entirely within `low' and can be stored in one TOC entry. */
15150
37409796
NS		 15151 /* It would be easy to make this work, but it doesn't now. */
15152 gcc_assert (!TARGET_64BIT || POINTER_SIZE >= GET_MODE_BITSIZE (mode));
02a4ec28
FS		 15153
15154 if (POINTER_SIZE > GET_MODE_BITSIZE (mode))
fb52d8de
AM		 15155 {
15156#if HOST_BITS_PER_WIDE_INT == 32
15157 lshift_double (low, high, POINTER_SIZE - GET_MODE_BITSIZE (mode),
15158 POINTER_SIZE, &low, &high, 0);
15159#else
15160 low |= high << 32;
15161 low <<= POINTER_SIZE - GET_MODE_BITSIZE (mode);
15162 high = (HOST_WIDE_INT) low >> 32;
15163 low &= 0xffffffff;
15164#endif
15165 }
a9098fd0 15166
13ded975
DE		 15167 if (TARGET_64BIT)
15168 {
15169 if (TARGET_MINIMAL_TOC)
2bfcf297 15170 fputs (DOUBLE_INT_ASM_OP, file);
13ded975 15171 else
2f0552b6
AM		 15172 fprintf (file, "\t.tc ID_%lx_%lx[TC],",
15173 (long) high & 0xffffffff, (long) low & 0xffffffff);
15174 fprintf (file, "0x%lx%08lx\n",
15175 (long) high & 0xffffffff, (long) low & 0xffffffff);
13ded975
DE		 15176 return;
15177 }
1875cc88 15178 else
13ded975 15179 {
02a4ec28
FS		 15180 if (POINTER_SIZE < GET_MODE_BITSIZE (mode))
15181 {
15182 if (TARGET_MINIMAL_TOC)
2bfcf297 15183 fputs ("\t.long ", file);
02a4ec28 15184 else
2bfcf297 15185 fprintf (file, "\t.tc ID_%lx_%lx[TC],",
2f0552b6
AM		 15186 (long) high & 0xffffffff, (long) low & 0xffffffff);
15187 fprintf (file, "0x%lx,0x%lx\n",
15188 (long) high & 0xffffffff, (long) low & 0xffffffff);
02a4ec28 15189 }
13ded975 15190 else
02a4ec28
FS		 15191 {
15192 if (TARGET_MINIMAL_TOC)
2bfcf297 15193 fputs ("\t.long ", file);
02a4ec28 15194 else
2f0552b6
AM		 15195 fprintf (file, "\t.tc IS_%lx[TC],", (long) low & 0xffffffff);
15196 fprintf (file, "0x%lx\n", (long) low & 0xffffffff);
02a4ec28 15197 }
13ded975
DE		 15198 return;
15199 }
9878760c
RK		 15200 }
15201
15202 if (GET_CODE (x) == CONST)
15203 {
37409796 15204 gcc_assert (GET_CODE (XEXP (x, 0)) == PLUS);
2bfcf297 15205
9878760c
RK		 15206 base = XEXP (XEXP (x, 0), 0);
15207 offset = INTVAL (XEXP (XEXP (x, 0), 1));
15208 }
f676971a 15209
37409796
NS		 15210 switch (GET_CODE (base))
15211 {
15212 case SYMBOL_REF:
15213 name = XSTR (base, 0);
15214 break;
15215
15216 case LABEL_REF:
15217 ASM_GENERATE_INTERNAL_LABEL (buf, "L",
15218 CODE_LABEL_NUMBER (XEXP (base, 0)));
15219 break;
15220
15221 case CODE_LABEL:
15222 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (base));
15223 break;
15224
15225 default:
15226 gcc_unreachable ();
15227 }
9878760c 15228
772c5265 15229 real_name = (*targetm.strip_name_encoding) (name);
1875cc88 15230 if (TARGET_MINIMAL_TOC)
2bfcf297 15231 fputs (TARGET_32BIT ? "\t.long " : DOUBLE_INT_ASM_OP, file);
1875cc88
JW		 15232 else
15233 {
b6c9286a 15234 fprintf (file, "\t.tc %s", real_name);
9878760c 15235
1875cc88
JW		 15236 if (offset < 0)
15237 fprintf (file, ".N%d", - offset);
15238 else if (offset)
15239 fprintf (file, ".P%d", offset);
9878760c 15240
19d2d16f 15241 fputs ("[TC],", file);
1875cc88 15242 }
581bc4de
MM		 15243
15244 /* Currently C++ toc references to vtables can be emitted before it
15245 is decided whether the vtable is public or private. If this is
15246 the case, then the linker will eventually complain that there is
15247 a TOC reference to an unknown section. Thus, for vtables only,
15248 we emit the TOC reference to reference the symbol and not the
15249 section. */
28e510bd 15250 if (VTABLE_NAME_P (name))
581bc4de 15251 {
54ee9799 15252 RS6000_OUTPUT_BASENAME (file, name);
581bc4de
MM		 15253 if (offset < 0)
15254 fprintf (file, "%d", offset);
15255 else if (offset > 0)
15256 fprintf (file, "+%d", offset);
15257 }
15258 else
15259 output_addr_const (file, x);
19d2d16f 15260 putc ('\n', file);
9878760c
RK		 15261}
15262\f
15263/* Output an assembler pseudo-op to write an ASCII string of N characters
15264 starting at P to FILE.
15265
15266 On the RS/6000, we have to do this using the .byte operation and
15267 write out special characters outside the quoted string.
15268 Also, the assembler is broken; very long strings are truncated,
a4f6c312 15269 so we must artificially break them up early. */
9878760c
RK		 15270
15271void
a2369ed3 15272output_ascii (FILE *file, const char *p, int n)
9878760c
RK		 15273{
15274 char c;
15275 int i, count_string;
d330fd93
KG		 15276 const char *for_string = "\t.byte \"";
15277 const char *for_decimal = "\t.byte ";
15278 const char *to_close = NULL;
9878760c
RK		 15279
15280 count_string = 0;
15281 for (i = 0; i < n; i++)
15282 {
15283 c = *p++;
15284 if (c >= ' ' && c < 0177)
15285 {
15286 if (for_string)
15287 fputs (for_string, file);
15288 putc (c, file);
15289
15290 /* Write two quotes to get one. */
15291 if (c == '"')
15292 {
15293 putc (c, file);
15294 ++count_string;
15295 }
15296
15297 for_string = NULL;
15298 for_decimal = "\"\n\t.byte ";
15299 to_close = "\"\n";
15300 ++count_string;
15301
15302 if (count_string >= 512)
15303 {
15304 fputs (to_close, file);
15305
15306 for_string = "\t.byte \"";
15307 for_decimal = "\t.byte ";
15308 to_close = NULL;
15309 count_string = 0;
15310 }
15311 }
15312 else
15313 {
15314 if (for_decimal)
15315 fputs (for_decimal, file);
15316 fprintf (file, "%d", c);
15317
15318 for_string = "\n\t.byte \"";
15319 for_decimal = ", ";
15320 to_close = "\n";
15321 count_string = 0;
15322 }
15323 }
15324
15325 /* Now close the string if we have written one. Then end the line. */
15326 if (to_close)
9ebbca7d 15327 fputs (to_close, file);
9878760c
RK		 15328}
15329\f
15330/* Generate a unique section name for FILENAME for a section type
15331 represented by SECTION_DESC. Output goes into BUF.
15332
15333 SECTION_DESC can be any string, as long as it is different for each
15334 possible section type.
15335
15336 We name the section in the same manner as xlc. The name begins with an
15337 underscore followed by the filename (after stripping any leading directory
11e5fe42
RK		 15338 names) with the last period replaced by the string SECTION_DESC. If
15339 FILENAME does not contain a period, SECTION_DESC is appended to the end of
15340 the name. */
9878760c
RK		 15341
15342void
f676971a 15343rs6000_gen_section_name (char **buf, const char *filename,
c4ad648e 15344 const char *section_desc)
9878760c 15345{
9ebbca7d 15346 const char *q, *after_last_slash, *last_period = 0;
9878760c
RK		 15347 char *p;
15348 int len;
9878760c
RK		 15349
15350 after_last_slash = filename;
15351 for (q = filename; *q; q++)
11e5fe42
RK		 15352 {
15353 if (*q == '/')
15354 after_last_slash = q + 1;
15355 else if (*q == '.')
15356 last_period = q;
15357 }
9878760c 15358
11e5fe42 15359 len = strlen (after_last_slash) + strlen (section_desc) + 2;
6d9f628e 15360 *buf = (char *) xmalloc (len);
9878760c
RK		 15361
15362 p = *buf;
15363 *p++ = '_';
15364
15365 for (q = after_last_slash; *q; q++)
15366 {
11e5fe42 15367 if (q == last_period)
c4ad648e 15368 {
9878760c
RK		 15369 strcpy (p, section_desc);
15370 p += strlen (section_desc);
e3981aab 15371 break;
c4ad648e 15372 }
9878760c 15373
e9a780ec 15374 else if (ISALNUM (*q))
c4ad648e 15375 *p++ = *q;
9878760c
RK		 15376 }
15377
11e5fe42 15378 if (last_period == 0)
9878760c
RK		 15379 strcpy (p, section_desc);
15380 else
15381 *p = '\0';
15382}
e165f3f0 15383\f
a4f6c312 15384/* Emit profile function. */
411707f4 15385
411707f4 15386void
a2369ed3 15387output_profile_hook (int labelno ATTRIBUTE_UNUSED)
411707f4 15388{
858081ad
AH		 15389 /* Non-standard profiling for kernels, which just saves LR then calls
15390 _mcount without worrying about arg saves. The idea is to change
15391 the function prologue as little as possible as it isn't easy to
15392 account for arg save/restore code added just for _mcount. */
ffcfcb5f
AM		 15393 if (TARGET_PROFILE_KERNEL)
15394 return;
15395
8480e480
CC		 15396 if (DEFAULT_ABI == ABI_AIX)
15397 {
9739c90c
JJ		 15398#ifndef NO_PROFILE_COUNTERS
15399# define NO_PROFILE_COUNTERS 0
15400#endif
f676971a 15401 if (NO_PROFILE_COUNTERS)
9739c90c
JJ		 15402 emit_library_call (init_one_libfunc (RS6000_MCOUNT), 0, VOIDmode, 0);
15403 else
15404 {
15405 char buf[30];
15406 const char *label_name;
15407 rtx fun;
411707f4 15408
9739c90c
JJ		 15409 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
15410 label_name = (*targetm.strip_name_encoding) (ggc_strdup (buf));
15411 fun = gen_rtx_SYMBOL_REF (Pmode, label_name);
411707f4 15412
9739c90c
JJ		 15413 emit_library_call (init_one_libfunc (RS6000_MCOUNT), 0, VOIDmode, 1,
15414 fun, Pmode);
15415 }
8480e480 15416 }
ee890fe2
SS		 15417 else if (DEFAULT_ABI == ABI_DARWIN)
15418 {
d5fa86ba 15419 const char *mcount_name = RS6000_MCOUNT;
ee890fe2
SS		 15420 int caller_addr_regno = LINK_REGISTER_REGNUM;
15421
15422 /* Be conservative and always set this, at least for now. */
15423 current_function_uses_pic_offset_table = 1;
15424
15425#if TARGET_MACHO
15426 /* For PIC code, set up a stub and collect the caller's address
15427 from r0, which is where the prologue puts it. */
11abc112
MM		 15428 if (MACHOPIC_INDIRECT
15429 && current_function_uses_pic_offset_table)
15430 caller_addr_regno = 0;
ee890fe2
SS		 15431#endif
15432 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mcount_name),
15433 0, VOIDmode, 1,
15434 gen_rtx_REG (Pmode, caller_addr_regno), Pmode);
15435 }
411707f4
CC		 15436}
15437
a4f6c312 15438/* Write function profiler code. */
e165f3f0
RK		 15439
15440void
a2369ed3 15441output_function_profiler (FILE *file, int labelno)
e165f3f0 15442{
3daf36a4 15443 char buf[100];
e165f3f0 15444
38c1f2d7 15445 switch (DEFAULT_ABI)
3daf36a4 15446 {
38c1f2d7 15447 default:
37409796 15448 gcc_unreachable ();
38c1f2d7
MM		 15449
15450 case ABI_V4:
09eeeacb
AM		 15451 if (!TARGET_32BIT)
15452 {
d4ee4d25 15453 warning (0, "no profiling of 64-bit code for this ABI");
09eeeacb
AM		 15454 return;
15455 }
ffcfcb5f 15456 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
38c1f2d7 15457 fprintf (file, "\tmflr %s\n", reg_names[0]);
71625f3d
AM		 15458 if (NO_PROFILE_COUNTERS)
15459 {
15460 asm_fprintf (file, "\t{st|stw} %s,4(%s)\n",
15461 reg_names[0], reg_names[1]);
15462 }
15463 else if (TARGET_SECURE_PLT && flag_pic)
15464 {
15465 asm_fprintf (file, "\tbcl 20,31,1f\n1:\n\t{st|stw} %s,4(%s)\n",
15466 reg_names[0], reg_names[1]);
15467 asm_fprintf (file, "\tmflr %s\n", reg_names[12]);
15468 asm_fprintf (file, "\t{cau|addis} %s,%s,",
15469 reg_names[12], reg_names[12]);
15470 assemble_name (file, buf);
15471 asm_fprintf (file, "-1b@ha\n\t{cal|la} %s,", reg_names[0]);
15472 assemble_name (file, buf);
15473 asm_fprintf (file, "-1b@l(%s)\n", reg_names[12]);
15474 }
15475 else if (flag_pic == 1)
38c1f2d7 15476 {
dfdfa60f 15477 fputs ("\tbl _GLOBAL_OFFSET_TABLE_@local-4\n", file);
71625f3d
AM		 15478 asm_fprintf (file, "\t{st|stw} %s,4(%s)\n",
15479 reg_names[0], reg_names[1]);
17167fd8 15480 asm_fprintf (file, "\tmflr %s\n", reg_names[12]);
dfdfa60f 15481 asm_fprintf (file, "\t{l|lwz} %s,", reg_names[0]);
38c1f2d7 15482 assemble_name (file, buf);
17167fd8 15483 asm_fprintf (file, "@got(%s)\n", reg_names[12]);
38c1f2d7 15484 }
9ebbca7d 15485 else if (flag_pic > 1)
38c1f2d7 15486 {
71625f3d
AM		 15487 asm_fprintf (file, "\t{st|stw} %s,4(%s)\n",
15488 reg_names[0], reg_names[1]);
9ebbca7d 15489 /* Now, we need to get the address of the label. */
71625f3d 15490 fputs ("\tbcl 20,31,1f\n\t.long ", file);
034e84c4 15491 assemble_name (file, buf);
9ebbca7d
GK		 15492 fputs ("-.\n1:", file);
15493 asm_fprintf (file, "\tmflr %s\n", reg_names[11]);
f676971a 15494 asm_fprintf (file, "\t{l|lwz} %s,0(%s)\n",
9ebbca7d
GK		 15495 reg_names[0], reg_names[11]);
15496 asm_fprintf (file, "\t{cax|add} %s,%s,%s\n",
15497 reg_names[0], reg_names[0], reg_names[11]);
38c1f2d7 15498 }
38c1f2d7
MM		 15499 else
15500 {
17167fd8 15501 asm_fprintf (file, "\t{liu|lis} %s,", reg_names[12]);
38c1f2d7 15502 assemble_name (file, buf);
dfdfa60f 15503 fputs ("@ha\n", file);
71625f3d
AM		 15504 asm_fprintf (file, "\t{st|stw} %s,4(%s)\n",
15505 reg_names[0], reg_names[1]);
a260abc9 15506 asm_fprintf (file, "\t{cal|la} %s,", reg_names[0]);
38c1f2d7 15507 assemble_name (file, buf);
17167fd8 15508 asm_fprintf (file, "@l(%s)\n", reg_names[12]);
38c1f2d7
MM		 15509 }
15510
50d440bc 15511 /* ABI_V4 saves the static chain reg with ASM_OUTPUT_REG_PUSH. */
3b6ce0af
DE		 15512 fprintf (file, "\tbl %s%s\n",
15513 RS6000_MCOUNT, flag_pic ? "@plt" : "");
38c1f2d7
MM		 15514 break;
15515
15516 case ABI_AIX:
ee890fe2 15517 case ABI_DARWIN:
ffcfcb5f
AM		 15518 if (!TARGET_PROFILE_KERNEL)
15519 {
a3c9585f 15520 /* Don't do anything, done in output_profile_hook (). */
ffcfcb5f
AM		 15521 }
15522 else
15523 {
37409796 15524 gcc_assert (!TARGET_32BIT);
ffcfcb5f
AM		 15525
15526 asm_fprintf (file, "\tmflr %s\n", reg_names[0]);
15527 asm_fprintf (file, "\tstd %s,16(%s)\n", reg_names[0], reg_names[1]);
15528
6de9cd9a 15529 if (cfun->static_chain_decl != NULL)
ffcfcb5f
AM		 15530 {
15531 asm_fprintf (file, "\tstd %s,24(%s)\n",
15532 reg_names[STATIC_CHAIN_REGNUM], reg_names[1]);
15533 fprintf (file, "\tbl %s\n", RS6000_MCOUNT);
15534 asm_fprintf (file, "\tld %s,24(%s)\n",
15535 reg_names[STATIC_CHAIN_REGNUM], reg_names[1]);
15536 }
15537 else
15538 fprintf (file, "\tbl %s\n", RS6000_MCOUNT);
15539 }
38c1f2d7
MM		 15540 break;
15541 }
e165f3f0 15542}
a251ffd0 15543
b54cf83a 15544\f
b54cf83a
DE		 15545/* Power4 load update and store update instructions are cracked into a
15546 load or store and an integer insn which are executed in the same cycle.
15547 Branches have their own dispatch slot which does not count against the
15548 GCC issue rate, but it changes the program flow so there are no other
15549 instructions to issue in this cycle. */
15550
15551static int
f676971a
EC		 15552rs6000_variable_issue (FILE *stream ATTRIBUTE_UNUSED,
15553 int verbose ATTRIBUTE_UNUSED,
a2369ed3 15554 rtx insn, int more)
b54cf83a
DE		 15555{
15556 if (GET_CODE (PATTERN (insn)) == USE
15557 || GET_CODE (PATTERN (insn)) == CLOBBER)
15558 return more;
15559
ec507f2d 15560 if (rs6000_sched_groups)
b54cf83a 15561 {
cbe26ab8 15562 if (is_microcoded_insn (insn))
c4ad648e 15563 return 0;
cbe26ab8 15564 else if (is_cracked_insn (insn))
c4ad648e 15565 return more > 2 ? more - 2 : 0;
b54cf83a 15566 }
165b263e
DE		 15567
15568 return more - 1;
b54cf83a
DE		 15569}
15570
a251ffd0
TG		 15571/* Adjust the cost of a scheduling dependency. Return the new cost of
15572 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
15573
c237e94a 15574static int
0a4f0294 15575rs6000_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
a251ffd0
TG		 15576{
15577 if (! recog_memoized (insn))
15578 return 0;
15579
15580 if (REG_NOTE_KIND (link) != 0)
15581 return 0;
15582
15583 if (REG_NOTE_KIND (link) == 0)
15584 {
ed947a96
DJ		 15585 /* Data dependency; DEP_INSN writes a register that INSN reads
15586 some cycles later. */
c9dbf840
DE		 15587
15588 /* Separate a load from a narrower, dependent store. */
15589 if (rs6000_sched_groups
15590 && GET_CODE (PATTERN (insn)) == SET
15591 && GET_CODE (PATTERN (dep_insn)) == SET
15592 && GET_CODE (XEXP (PATTERN (insn), 1)) == MEM
15593 && GET_CODE (XEXP (PATTERN (dep_insn), 0)) == MEM
15594 && (GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (insn), 1)))
15595 > GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (dep_insn), 0)))))
15596 return cost + 14;
15597
ed947a96
DJ		 15598 switch (get_attr_type (insn))
15599 {
15600 case TYPE_JMPREG:
309323c2 15601 /* Tell the first scheduling pass about the latency between
ed947a96
DJ		 15602 a mtctr and bctr (and mtlr and br/blr). The first
15603 scheduling pass will not know about this latency since
15604 the mtctr instruction, which has the latency associated
15605 to it, will be generated by reload. */
309323c2 15606 return TARGET_POWER ? 5 : 4;
ed947a96
DJ		 15607 case TYPE_BRANCH:
15608 /* Leave some extra cycles between a compare and its
15609 dependent branch, to inhibit expensive mispredicts. */
309323c2
DE		 15610 if ((rs6000_cpu_attr == CPU_PPC603
15611 || rs6000_cpu_attr == CPU_PPC604
15612 || rs6000_cpu_attr == CPU_PPC604E
15613 || rs6000_cpu_attr == CPU_PPC620
15614 || rs6000_cpu_attr == CPU_PPC630
15615 || rs6000_cpu_attr == CPU_PPC750
15616 || rs6000_cpu_attr == CPU_PPC7400
15617 || rs6000_cpu_attr == CPU_PPC7450
ec507f2d
DE		 15618 || rs6000_cpu_attr == CPU_POWER4
15619 || rs6000_cpu_attr == CPU_POWER5)
ed947a96
DJ		 15620 && recog_memoized (dep_insn)
15621 && (INSN_CODE (dep_insn) >= 0)
b54cf83a
DE		 15622 && (get_attr_type (dep_insn) == TYPE_CMP
15623 || get_attr_type (dep_insn) == TYPE_COMPARE
ed947a96 15624 || get_attr_type (dep_insn) == TYPE_DELAYED_COMPARE
9259f3b0
DE		 15625 || get_attr_type (dep_insn) == TYPE_IMUL_COMPARE
15626 || get_attr_type (dep_insn) == TYPE_LMUL_COMPARE
ed947a96 15627 || get_attr_type (dep_insn) == TYPE_FPCOMPARE
b54cf83a
DE		 15628 || get_attr_type (dep_insn) == TYPE_CR_LOGICAL
15629 || get_attr_type (dep_insn) == TYPE_DELAYED_CR))
ed947a96
DJ		 15630 return cost + 2;
15631 default:
15632 break;
15633 }
a251ffd0
TG		 15634 /* Fall out to return default cost. */
15635 }
15636
15637 return cost;
15638}
b6c9286a 15639
cbe26ab8 15640/* The function returns a true if INSN is microcoded.
839a4992 15641 Return false otherwise. */
cbe26ab8
DN		 15642
15643static bool
15644is_microcoded_insn (rtx insn)
15645{
15646 if (!insn || !INSN_P (insn)
15647 || GET_CODE (PATTERN (insn)) == USE
15648 || GET_CODE (PATTERN (insn)) == CLOBBER)
15649 return false;
15650
ec507f2d 15651 if (rs6000_sched_groups)
cbe26ab8
DN		 15652 {
15653 enum attr_type type = get_attr_type (insn);
15654 if (type == TYPE_LOAD_EXT_U
15655 || type == TYPE_LOAD_EXT_UX
15656 || type == TYPE_LOAD_UX
15657 || type == TYPE_STORE_UX
15658 || type == TYPE_MFCR)
c4ad648e 15659 return true;
cbe26ab8
DN		 15660 }
15661
15662 return false;
15663}
15664
5c425df5 15665/* The function returns a nonzero value if INSN can be scheduled only
cbe26ab8
DN		 15666 as the first insn in a dispatch group ("dispatch-slot restricted").
15667 In this case, the returned value indicates how many dispatch slots
15668 the insn occupies (at the beginning of the group).
79ae11c4
DN		 15669 Return 0 otherwise. */
15670
cbe26ab8 15671static int
79ae11c4
DN		 15672is_dispatch_slot_restricted (rtx insn)
15673{
15674 enum attr_type type;
15675
ec507f2d 15676 if (!rs6000_sched_groups)
79ae11c4
DN		 15677 return 0;
15678
15679 if (!insn
15680 || insn == NULL_RTX
15681 || GET_CODE (insn) == NOTE
15682 || GET_CODE (PATTERN (insn)) == USE
15683 || GET_CODE (PATTERN (insn)) == CLOBBER)
15684 return 0;
15685
15686 type = get_attr_type (insn);
15687
ec507f2d
DE		 15688 switch (type)
15689 {
15690 case TYPE_MFCR:
15691 case TYPE_MFCRF:
15692 case TYPE_MTCR:
15693 case TYPE_DELAYED_CR:
15694 case TYPE_CR_LOGICAL:
15695 case TYPE_MTJMPR:
15696 case TYPE_MFJMPR:
15697 return 1;
15698 case TYPE_IDIV:
15699 case TYPE_LDIV:
15700 return 2;
15701 default:
15702 if (rs6000_cpu == PROCESSOR_POWER5
15703 && is_cracked_insn (insn))
15704 return 2;
15705 return 0;
15706 }
79ae11c4
DN		 15707}
15708
cbe26ab8
DN		 15709/* The function returns true if INSN is cracked into 2 instructions
15710 by the processor (and therefore occupies 2 issue slots). */
15711
15712static bool
15713is_cracked_insn (rtx insn)
15714{
15715 if (!insn || !INSN_P (insn)
15716 || GET_CODE (PATTERN (insn)) == USE
15717 || GET_CODE (PATTERN (insn)) == CLOBBER)
15718 return false;
15719
ec507f2d 15720 if (rs6000_sched_groups)
cbe26ab8
DN		 15721 {
15722 enum attr_type type = get_attr_type (insn);
15723 if (type == TYPE_LOAD_U || type == TYPE_STORE_U
c4ad648e
AM		 15724 || type == TYPE_FPLOAD_U || type == TYPE_FPSTORE_U
15725 || type == TYPE_FPLOAD_UX || type == TYPE_FPSTORE_UX
15726 || type == TYPE_LOAD_EXT || type == TYPE_DELAYED_CR
15727 || type == TYPE_COMPARE || type == TYPE_DELAYED_COMPARE
15728 || type == TYPE_IMUL_COMPARE || type == TYPE_LMUL_COMPARE
15729 || type == TYPE_IDIV || type == TYPE_LDIV
15730 || type == TYPE_INSERT_WORD)
15731 return true;
cbe26ab8
DN		 15732 }
15733
15734 return false;
15735}
15736
15737/* The function returns true if INSN can be issued only from
a3c9585f 15738 the branch slot. */
cbe26ab8
DN		 15739
15740static bool
15741is_branch_slot_insn (rtx insn)
15742{
15743 if (!insn || !INSN_P (insn)
15744 || GET_CODE (PATTERN (insn)) == USE
15745 || GET_CODE (PATTERN (insn)) == CLOBBER)
15746 return false;
15747
ec507f2d 15748 if (rs6000_sched_groups)
cbe26ab8
DN		 15749 {
15750 enum attr_type type = get_attr_type (insn);
15751 if (type == TYPE_BRANCH || type == TYPE_JMPREG)
f676971a 15752 return true;
cbe26ab8
DN		 15753 return false;
15754 }
15755
15756 return false;
15757}
79ae11c4 15758
a4f6c312 15759/* A C statement (sans semicolon) to update the integer scheduling
79ae11c4
DN		 15760 priority INSN_PRIORITY (INSN). Increase the priority to execute the
15761 INSN earlier, reduce the priority to execute INSN later. Do not
a4f6c312
SS		 15762 define this macro if you do not need to adjust the scheduling
15763 priorities of insns. */
bef84347 15764
c237e94a 15765static int
a2369ed3 15766rs6000_adjust_priority (rtx insn ATTRIBUTE_UNUSED, int priority)
bef84347 15767{
a4f6c312
SS		 15768 /* On machines (like the 750) which have asymmetric integer units,
15769 where one integer unit can do multiply and divides and the other
15770 can't, reduce the priority of multiply/divide so it is scheduled
15771 before other integer operations. */
bef84347
VM		 15772
15773#if 0
2c3c49de 15774 if (! INSN_P (insn))
bef84347
VM		 15775 return priority;
15776
15777 if (GET_CODE (PATTERN (insn)) == USE)
15778 return priority;
15779
15780 switch (rs6000_cpu_attr) {
15781 case CPU_PPC750:
15782 switch (get_attr_type (insn))
15783 {
15784 default:
15785 break;
15786
15787 case TYPE_IMUL:
15788 case TYPE_IDIV:
3cb999d8
DE		 15789 fprintf (stderr, "priority was %#x (%d) before adjustment\n",
15790 priority, priority);
bef84347
VM		 15791 if (priority >= 0 && priority < 0x01000000)
15792 priority >>= 3;
15793 break;
15794 }
15795 }
15796#endif
15797
79ae11c4
DN		 15798 if (is_dispatch_slot_restricted (insn)
15799 && reload_completed
f676971a 15800 && current_sched_info->sched_max_insns_priority
79ae11c4
DN		 15801 && rs6000_sched_restricted_insns_priority)
15802 {
15803
c4ad648e
AM		 15804 /* Prioritize insns that can be dispatched only in the first
15805 dispatch slot. */
79ae11c4 15806 if (rs6000_sched_restricted_insns_priority == 1)
f676971a
EC		 15807 /* Attach highest priority to insn. This means that in
15808 haifa-sched.c:ready_sort(), dispatch-slot restriction considerations
79ae11c4 15809 precede 'priority' (critical path) considerations. */
f676971a 15810 return current_sched_info->sched_max_insns_priority;
79ae11c4 15811 else if (rs6000_sched_restricted_insns_priority == 2)
f676971a 15812 /* Increase priority of insn by a minimal amount. This means that in
c4ad648e
AM		 15813 haifa-sched.c:ready_sort(), only 'priority' (critical path)
15814 considerations precede dispatch-slot restriction considerations. */
f676971a
EC		 15815 return (priority + 1);
15816 }
79ae11c4 15817
bef84347
VM		 15818 return priority;
15819}
15820
a4f6c312
SS		 15821/* Return how many instructions the machine can issue per cycle. */
15822
c237e94a 15823static int
863d938c 15824rs6000_issue_rate (void)
b6c9286a 15825{
3317bab1
DE		 15826 /* Use issue rate of 1 for first scheduling pass to decrease degradation. */
15827 if (!reload_completed)
15828 return 1;
15829
b6c9286a 15830 switch (rs6000_cpu_attr) {
3cb999d8
DE		 15831 case CPU_RIOS1: /* ? */
15832 case CPU_RS64A:
15833 case CPU_PPC601: /* ? */
ed947a96 15834 case CPU_PPC7450:
3cb999d8 15835 return 3;
b54cf83a 15836 case CPU_PPC440:
b6c9286a 15837 case CPU_PPC603:
bef84347 15838 case CPU_PPC750:
ed947a96 15839 case CPU_PPC7400:
be12c2b0 15840 case CPU_PPC8540:
f676971a 15841 return 2;
3cb999d8 15842 case CPU_RIOS2:
b6c9286a 15843 case CPU_PPC604:
19684119 15844 case CPU_PPC604E:
b6c9286a 15845 case CPU_PPC620:
3cb999d8 15846 case CPU_PPC630:
b6c9286a 15847 return 4;
cbe26ab8 15848 case CPU_POWER4:
ec507f2d 15849 case CPU_POWER5:
cbe26ab8 15850 return 5;
b6c9286a
MM		 15851 default:
15852 return 1;
15853 }
15854}
15855
be12c2b0
VM		 15856/* Return how many instructions to look ahead for better insn
15857 scheduling. */
15858
15859static int
863d938c 15860rs6000_use_sched_lookahead (void)
be12c2b0
VM		 15861{
15862 if (rs6000_cpu_attr == CPU_PPC8540)
15863 return 4;
15864 return 0;
15865}
15866
569fa502
DN		 15867/* Determine is PAT refers to memory. */
15868
15869static bool
15870is_mem_ref (rtx pat)
15871{
15872 const char * fmt;
15873 int i, j;
15874 bool ret = false;
15875
15876 if (GET_CODE (pat) == MEM)
15877 return true;
15878
15879 /* Recursively process the pattern. */
15880 fmt = GET_RTX_FORMAT (GET_CODE (pat));
15881
15882 for (i = GET_RTX_LENGTH (GET_CODE (pat)) - 1; i >= 0 && !ret; i--)
15883 {
15884 if (fmt[i] == 'e')
15885 ret |= is_mem_ref (XEXP (pat, i));
15886 else if (fmt[i] == 'E')
15887 for (j = XVECLEN (pat, i) - 1; j >= 0; j--)
15888 ret |= is_mem_ref (XVECEXP (pat, i, j));
15889 }
15890
15891 return ret;
15892}
15893
15894/* Determine if PAT is a PATTERN of a load insn. */
f676971a 15895
569fa502
DN		 15896static bool
15897is_load_insn1 (rtx pat)
15898{
15899 if (!pat || pat == NULL_RTX)
15900 return false;
15901
15902 if (GET_CODE (pat) == SET)
15903 return is_mem_ref (SET_SRC (pat));
15904
15905 if (GET_CODE (pat) == PARALLEL)
15906 {
15907 int i;
15908
15909 for (i = 0; i < XVECLEN (pat, 0); i++)
15910 if (is_load_insn1 (XVECEXP (pat, 0, i)))
15911 return true;
15912 }
15913
15914 return false;
15915}
15916
15917/* Determine if INSN loads from memory. */
15918
15919static bool
15920is_load_insn (rtx insn)
15921{
15922 if (!insn || !INSN_P (insn))
15923 return false;
15924
15925 if (GET_CODE (insn) == CALL_INSN)
15926 return false;
15927
15928 return is_load_insn1 (PATTERN (insn));
15929}
15930
15931/* Determine if PAT is a PATTERN of a store insn. */
15932
15933static bool
15934is_store_insn1 (rtx pat)
15935{
15936 if (!pat || pat == NULL_RTX)
15937 return false;
15938
15939 if (GET_CODE (pat) == SET)
15940 return is_mem_ref (SET_DEST (pat));
15941
15942 if (GET_CODE (pat) == PARALLEL)
15943 {
15944 int i;
15945
15946 for (i = 0; i < XVECLEN (pat, 0); i++)
15947 if (is_store_insn1 (XVECEXP (pat, 0, i)))
15948 return true;
15949 }
15950
15951 return false;
15952}
15953
15954/* Determine if INSN stores to memory. */
15955
15956static bool
15957is_store_insn (rtx insn)
15958{
15959 if (!insn || !INSN_P (insn))
15960 return false;
15961
15962 return is_store_insn1 (PATTERN (insn));
15963}
15964
15965/* Returns whether the dependence between INSN and NEXT is considered
15966 costly by the given target. */
15967
15968static bool
c4ad648e
AM		 15969rs6000_is_costly_dependence (rtx insn, rtx next, rtx link, int cost,
15970 int distance)
f676971a 15971{
aabcd309 15972 /* If the flag is not enabled - no dependence is considered costly;
f676971a 15973 allow all dependent insns in the same group.
569fa502
DN		 15974 This is the most aggressive option. */
15975 if (rs6000_sched_costly_dep == no_dep_costly)
15976 return false;
15977
f676971a 15978 /* If the flag is set to 1 - a dependence is always considered costly;
569fa502
DN		 15979 do not allow dependent instructions in the same group.
15980 This is the most conservative option. */
15981 if (rs6000_sched_costly_dep == all_deps_costly)
f676971a 15982 return true;
569fa502 15983
f676971a
EC		 15984 if (rs6000_sched_costly_dep == store_to_load_dep_costly
15985 && is_load_insn (next)
569fa502
DN		 15986 && is_store_insn (insn))
15987 /* Prevent load after store in the same group. */
15988 return true;
15989
15990 if (rs6000_sched_costly_dep == true_store_to_load_dep_costly
f676971a 15991 && is_load_insn (next)
569fa502
DN		 15992 && is_store_insn (insn)
15993 && (!link || (int) REG_NOTE_KIND (link) == 0))
c4ad648e
AM		 15994 /* Prevent load after store in the same group if it is a true
15995 dependence. */
569fa502 15996 return true;
f676971a
EC		 15997
15998 /* The flag is set to X; dependences with latency >= X are considered costly,
569fa502
DN		 15999 and will not be scheduled in the same group. */
16000 if (rs6000_sched_costly_dep <= max_dep_latency
16001 && ((cost - distance) >= (int)rs6000_sched_costly_dep))
16002 return true;
16003
16004 return false;
16005}
16006
f676971a 16007/* Return the next insn after INSN that is found before TAIL is reached,
cbe26ab8
DN		 16008 skipping any "non-active" insns - insns that will not actually occupy
16009 an issue slot. Return NULL_RTX if such an insn is not found. */
16010
16011static rtx
16012get_next_active_insn (rtx insn, rtx tail)
16013{
16014 rtx next_insn;
16015
16016 if (!insn || insn == tail)
16017 return NULL_RTX;
16018
16019 next_insn = NEXT_INSN (insn);
16020
16021 while (next_insn
16022 && next_insn != tail
9390387d 16023 && (GET_CODE (next_insn) == NOTE
cbe26ab8
DN		 16024 || GET_CODE (PATTERN (next_insn)) == USE
16025 || GET_CODE (PATTERN (next_insn)) == CLOBBER))
16026 {
16027 next_insn = NEXT_INSN (next_insn);
16028 }
16029
16030 if (!next_insn || next_insn == tail)
16031 return NULL_RTX;
16032
16033 return next_insn;
16034}
16035
839a4992 16036/* Return whether the presence of INSN causes a dispatch group termination
cbe26ab8
DN		 16037 of group WHICH_GROUP.
16038
16039 If WHICH_GROUP == current_group, this function will return true if INSN
16040 causes the termination of the current group (i.e, the dispatch group to
16041 which INSN belongs). This means that INSN will be the last insn in the
16042 group it belongs to.
16043
16044 If WHICH_GROUP == previous_group, this function will return true if INSN
16045 causes the termination of the previous group (i.e, the dispatch group that
16046 precedes the group to which INSN belongs). This means that INSN will be
16047 the first insn in the group it belongs to). */
16048
16049static bool
16050insn_terminates_group_p (rtx insn, enum group_termination which_group)
16051{
16052 enum attr_type type;
16053
16054 if (! insn)
16055 return false;
569fa502 16056
cbe26ab8
DN		 16057 type = get_attr_type (insn);
16058
16059 if (is_microcoded_insn (insn))
16060 return true;
16061
16062 if (which_group == current_group)
16063 {
16064 if (is_branch_slot_insn (insn))
c4ad648e 16065 return true;
cbe26ab8
DN		 16066 return false;
16067 }
16068 else if (which_group == previous_group)
16069 {
16070 if (is_dispatch_slot_restricted (insn))
c4ad648e 16071 return true;
cbe26ab8
DN		 16072 return false;
16073 }
16074
16075 return false;
16076}
16077
839a4992 16078/* Return true if it is recommended to keep NEXT_INSN "far" (in a separate
cbe26ab8
DN		 16079 dispatch group) from the insns in GROUP_INSNS. Return false otherwise. */
16080
16081static bool
16082is_costly_group (rtx *group_insns, rtx next_insn)
16083{
16084 int i;
16085 rtx link;
16086 int cost;
16087 int issue_rate = rs6000_issue_rate ();
16088
16089 for (i = 0; i < issue_rate; i++)
16090 {
16091 rtx insn = group_insns[i];
16092 if (!insn)
c4ad648e 16093 continue;
cbe26ab8 16094 for (link = INSN_DEPEND (insn); link != 0; link = XEXP (link, 1))
c4ad648e
AM		 16095 {
16096 rtx next = XEXP (link, 0);
16097 if (next == next_insn)
16098 {
16099 cost = insn_cost (insn, link, next_insn);
16100 if (rs6000_is_costly_dependence (insn, next_insn, link, cost, 0))
16101 return true;
16102 }
16103 }
cbe26ab8
DN		 16104 }
16105
16106 return false;
16107}
16108
f676971a 16109/* Utility of the function redefine_groups.
cbe26ab8
DN		 16110 Check if it is too costly to schedule NEXT_INSN together with GROUP_INSNS
16111 in the same dispatch group. If so, insert nops before NEXT_INSN, in order
16112 to keep it "far" (in a separate group) from GROUP_INSNS, following
16113 one of the following schemes, depending on the value of the flag
16114 -minsert_sched_nops = X:
16115 (1) X == sched_finish_regroup_exact: insert exactly as many nops as needed
839a4992 16116 in order to force NEXT_INSN into a separate group.
f676971a
EC		 16117 (2) X < sched_finish_regroup_exact: insert exactly X nops.
16118 GROUP_END, CAN_ISSUE_MORE and GROUP_COUNT record the state after nop
cbe26ab8
DN		 16119 insertion (has a group just ended, how many vacant issue slots remain in the
16120 last group, and how many dispatch groups were encountered so far). */
16121
f676971a 16122static int
c4ad648e
AM		 16123force_new_group (int sched_verbose, FILE *dump, rtx *group_insns,
16124 rtx next_insn, bool *group_end, int can_issue_more,
16125 int *group_count)
cbe26ab8
DN		 16126{
16127 rtx nop;
16128 bool force;
16129 int issue_rate = rs6000_issue_rate ();
16130 bool end = *group_end;
16131 int i;
16132
16133 if (next_insn == NULL_RTX)
16134 return can_issue_more;
16135
16136 if (rs6000_sched_insert_nops > sched_finish_regroup_exact)
16137 return can_issue_more;
16138
16139 force = is_costly_group (group_insns, next_insn);
16140 if (!force)
16141 return can_issue_more;
16142
16143 if (sched_verbose > 6)
16144 fprintf (dump,"force: group count = %d, can_issue_more = %d\n",
c4ad648e 16145 *group_count ,can_issue_more);
cbe26ab8
DN		 16146
16147 if (rs6000_sched_insert_nops == sched_finish_regroup_exact)
16148 {
16149 if (*group_end)
c4ad648e 16150 can_issue_more = 0;
cbe26ab8
DN		 16151
16152 /* Since only a branch can be issued in the last issue_slot, it is
16153 sufficient to insert 'can_issue_more - 1' nops if next_insn is not
16154 a branch. If next_insn is a branch, we insert 'can_issue_more' nops;
c4ad648e
AM		 16155 in this case the last nop will start a new group and the branch
16156 will be forced to the new group. */
cbe26ab8 16157 if (can_issue_more && !is_branch_slot_insn (next_insn))
c4ad648e 16158 can_issue_more--;
cbe26ab8
DN		 16159
16160 while (can_issue_more > 0)
c4ad648e 16161 {
9390387d 16162 nop = gen_nop ();
c4ad648e
AM		 16163 emit_insn_before (nop, next_insn);
16164 can_issue_more--;
16165 }
cbe26ab8
DN		 16166
16167 *group_end = true;
16168 return 0;
f676971a 16169 }
cbe26ab8
DN		 16170
16171 if (rs6000_sched_insert_nops < sched_finish_regroup_exact)
16172 {
16173 int n_nops = rs6000_sched_insert_nops;
16174
f676971a 16175 /* Nops can't be issued from the branch slot, so the effective
c4ad648e 16176 issue_rate for nops is 'issue_rate - 1'. */
cbe26ab8 16177 if (can_issue_more == 0)
c4ad648e 16178 can_issue_more = issue_rate;
cbe26ab8
DN		 16179 can_issue_more--;
16180 if (can_issue_more == 0)
c4ad648e
AM		 16181 {
16182 can_issue_more = issue_rate - 1;
16183 (*group_count)++;
16184 end = true;
16185 for (i = 0; i < issue_rate; i++)
16186 {
16187 group_insns[i] = 0;
16188 }
16189 }
cbe26ab8
DN		 16190
16191 while (n_nops > 0)
c4ad648e
AM		 16192 {
16193 nop = gen_nop ();
16194 emit_insn_before (nop, next_insn);
16195 if (can_issue_more == issue_rate - 1) /* new group begins */
16196 end = false;
16197 can_issue_more--;
16198 if (can_issue_more == 0)
16199 {
16200 can_issue_more = issue_rate - 1;
16201 (*group_count)++;
16202 end = true;
16203 for (i = 0; i < issue_rate; i++)
16204 {
16205 group_insns[i] = 0;
16206 }
16207 }
16208 n_nops--;
16209 }
cbe26ab8
DN		 16210
16211 /* Scale back relative to 'issue_rate' (instead of 'issue_rate - 1'). */
f676971a 16212 can_issue_more++;
cbe26ab8 16213
c4ad648e
AM		 16214 /* Is next_insn going to start a new group? */
16215 *group_end
16216 = (end
cbe26ab8
DN		 16217 || (can_issue_more == 1 && !is_branch_slot_insn (next_insn))
16218 || (can_issue_more <= 2 && is_cracked_insn (next_insn))
16219 || (can_issue_more < issue_rate &&
c4ad648e 16220 insn_terminates_group_p (next_insn, previous_group)));
cbe26ab8 16221 if (*group_end && end)
c4ad648e 16222 (*group_count)--;
cbe26ab8
DN		 16223
16224 if (sched_verbose > 6)
c4ad648e
AM		 16225 fprintf (dump, "done force: group count = %d, can_issue_more = %d\n",
16226 *group_count, can_issue_more);
f676971a
EC		 16227 return can_issue_more;
16228 }
cbe26ab8
DN		 16229
16230 return can_issue_more;
16231}
16232
16233/* This function tries to synch the dispatch groups that the compiler "sees"
f676971a 16234 with the dispatch groups that the processor dispatcher is expected to
cbe26ab8
DN		 16235 form in practice. It tries to achieve this synchronization by forcing the
16236 estimated processor grouping on the compiler (as opposed to the function
16237 'pad_goups' which tries to force the scheduler's grouping on the processor).
16238
16239 The function scans the insn sequence between PREV_HEAD_INSN and TAIL and
16240 examines the (estimated) dispatch groups that will be formed by the processor
16241 dispatcher. It marks these group boundaries to reflect the estimated
16242 processor grouping, overriding the grouping that the scheduler had marked.
16243 Depending on the value of the flag '-minsert-sched-nops' this function can
16244 force certain insns into separate groups or force a certain distance between
16245 them by inserting nops, for example, if there exists a "costly dependence"
16246 between the insns.
16247
16248 The function estimates the group boundaries that the processor will form as
0fa2e4df 16249 follows: It keeps track of how many vacant issue slots are available after
cbe26ab8
DN		 16250 each insn. A subsequent insn will start a new group if one of the following
16251 4 cases applies:
16252 - no more vacant issue slots remain in the current dispatch group.
16253 - only the last issue slot, which is the branch slot, is vacant, but the next
16254 insn is not a branch.
16255 - only the last 2 or less issue slots, including the branch slot, are vacant,
16256 which means that a cracked insn (which occupies two issue slots) can't be
16257 issued in this group.
f676971a 16258 - less than 'issue_rate' slots are vacant, and the next insn always needs to
cbe26ab8
DN		 16259 start a new group. */
16260
16261static int
16262redefine_groups (FILE *dump, int sched_verbose, rtx prev_head_insn, rtx tail)
16263{
16264 rtx insn, next_insn;
16265 int issue_rate;
16266 int can_issue_more;
16267 int slot, i;
16268 bool group_end;
16269 int group_count = 0;
16270 rtx *group_insns;
16271
16272 /* Initialize. */
16273 issue_rate = rs6000_issue_rate ();
16274 group_insns = alloca (issue_rate * sizeof (rtx));
f676971a 16275 for (i = 0; i < issue_rate; i++)
cbe26ab8
DN		 16276 {
16277 group_insns[i] = 0;
16278 }
16279 can_issue_more = issue_rate;
16280 slot = 0;
16281 insn = get_next_active_insn (prev_head_insn, tail);
16282 group_end = false;
16283
16284 while (insn != NULL_RTX)
16285 {
16286 slot = (issue_rate - can_issue_more);
16287 group_insns[slot] = insn;
16288 can_issue_more =
c4ad648e 16289 rs6000_variable_issue (dump, sched_verbose, insn, can_issue_more);
cbe26ab8 16290 if (insn_terminates_group_p (insn, current_group))
c4ad648e 16291 can_issue_more = 0;
cbe26ab8
DN		 16292
16293 next_insn = get_next_active_insn (insn, tail);
16294 if (next_insn == NULL_RTX)
c4ad648e 16295 return group_count + 1;
cbe26ab8 16296
c4ad648e
AM		 16297 /* Is next_insn going to start a new group? */
16298 group_end
16299 = (can_issue_more == 0
16300 || (can_issue_more == 1 && !is_branch_slot_insn (next_insn))
16301 || (can_issue_more <= 2 && is_cracked_insn (next_insn))
16302 || (can_issue_more < issue_rate &&
16303 insn_terminates_group_p (next_insn, previous_group)));
cbe26ab8 16304
f676971a 16305 can_issue_more = force_new_group (sched_verbose, dump, group_insns,
c4ad648e
AM		 16306 next_insn, &group_end, can_issue_more,
16307 &group_count);
cbe26ab8
DN		 16308
16309 if (group_end)
c4ad648e
AM		 16310 {
16311 group_count++;
16312 can_issue_more = 0;
16313 for (i = 0; i < issue_rate; i++)
16314 {
16315 group_insns[i] = 0;
16316 }
16317 }
cbe26ab8
DN		 16318
16319 if (GET_MODE (next_insn) == TImode && can_issue_more)
9390387d 16320 PUT_MODE (next_insn, VOIDmode);
cbe26ab8 16321 else if (!can_issue_more && GET_MODE (next_insn) != TImode)
c4ad648e 16322 PUT_MODE (next_insn, TImode);
cbe26ab8
DN		 16323
16324 insn = next_insn;
16325 if (can_issue_more == 0)
c4ad648e
AM		 16326 can_issue_more = issue_rate;
16327 } /* while */
cbe26ab8
DN		 16328
16329 return group_count;
16330}
16331
16332/* Scan the insn sequence between PREV_HEAD_INSN and TAIL and examine the
16333 dispatch group boundaries that the scheduler had marked. Pad with nops
16334 any dispatch groups which have vacant issue slots, in order to force the
16335 scheduler's grouping on the processor dispatcher. The function
16336 returns the number of dispatch groups found. */
16337
16338static int
16339pad_groups (FILE *dump, int sched_verbose, rtx prev_head_insn, rtx tail)
16340{
16341 rtx insn, next_insn;
16342 rtx nop;
16343 int issue_rate;
16344 int can_issue_more;
16345 int group_end;
16346 int group_count = 0;
16347
16348 /* Initialize issue_rate. */
16349 issue_rate = rs6000_issue_rate ();
16350 can_issue_more = issue_rate;
16351
16352 insn = get_next_active_insn (prev_head_insn, tail);
16353 next_insn = get_next_active_insn (insn, tail);
16354
16355 while (insn != NULL_RTX)
16356 {
16357 can_issue_more =
16358 rs6000_variable_issue (dump, sched_verbose, insn, can_issue_more);
16359
16360 group_end = (next_insn == NULL_RTX || GET_MODE (next_insn) == TImode);
16361
16362 if (next_insn == NULL_RTX)
c4ad648e 16363 break;
cbe26ab8
DN		 16364
16365 if (group_end)
c4ad648e
AM		 16366 {
16367 /* If the scheduler had marked group termination at this location
16368 (between insn and next_indn), and neither insn nor next_insn will
16369 force group termination, pad the group with nops to force group
16370 termination. */
16371 if (can_issue_more
16372 && (rs6000_sched_insert_nops == sched_finish_pad_groups)
16373 && !insn_terminates_group_p (insn, current_group)
16374 && !insn_terminates_group_p (next_insn, previous_group))
16375 {
9390387d 16376 if (!is_branch_slot_insn (next_insn))
c4ad648e
AM		 16377 can_issue_more--;
16378
16379 while (can_issue_more)
16380 {
16381 nop = gen_nop ();
16382 emit_insn_before (nop, next_insn);
16383 can_issue_more--;
16384 }
16385 }
16386
16387 can_issue_more = issue_rate;
16388 group_count++;
16389 }
cbe26ab8
DN		 16390
16391 insn = next_insn;
16392 next_insn = get_next_active_insn (insn, tail);
16393 }
16394
16395 return group_count;
16396}
16397
16398/* The following function is called at the end of scheduling BB.
16399 After reload, it inserts nops at insn group bundling. */
16400
16401static void
38f391a5 16402rs6000_sched_finish (FILE *dump, int sched_verbose)
cbe26ab8
DN		 16403{
16404 int n_groups;
16405
16406 if (sched_verbose)
16407 fprintf (dump, "=== Finishing schedule.\n");
16408
ec507f2d 16409 if (reload_completed && rs6000_sched_groups)
cbe26ab8
DN		 16410 {
16411 if (rs6000_sched_insert_nops == sched_finish_none)
c4ad648e 16412 return;
cbe26ab8
DN		 16413
16414 if (rs6000_sched_insert_nops == sched_finish_pad_groups)
c4ad648e
AM		 16415 n_groups = pad_groups (dump, sched_verbose,
16416 current_sched_info->prev_head,
16417 current_sched_info->next_tail);
cbe26ab8 16418 else
c4ad648e
AM		 16419 n_groups = redefine_groups (dump, sched_verbose,
16420 current_sched_info->prev_head,
16421 current_sched_info->next_tail);
cbe26ab8
DN		 16422
16423 if (sched_verbose >= 6)
16424 {
16425 fprintf (dump, "ngroups = %d\n", n_groups);
16426 print_rtl (dump, current_sched_info->prev_head);
16427 fprintf (dump, "Done finish_sched\n");
16428 }
16429 }
16430}
b6c9286a 16431\f
b6c9286a
MM		 16432/* Length in units of the trampoline for entering a nested function. */
16433
16434int
863d938c 16435rs6000_trampoline_size (void)
b6c9286a
MM		 16436{
16437 int ret = 0;
16438
16439 switch (DEFAULT_ABI)
16440 {
16441 default:
37409796 16442 gcc_unreachable ();
b6c9286a
MM		 16443
16444 case ABI_AIX:
8f802bfb 16445 ret = (TARGET_32BIT) ? 12 : 24;
b6c9286a
MM		 16446 break;
16447
4dabc42d 16448 case ABI_DARWIN:
b6c9286a 16449 case ABI_V4:
03a7e1a5 16450 ret = (TARGET_32BIT) ? 40 : 48;
b6c9286a 16451 break;
b6c9286a
MM		 16452 }
16453
16454 return ret;
16455}
16456
16457/* Emit RTL insns to initialize the variable parts of a trampoline.
16458 FNADDR is an RTX for the address of the function's pure code.
16459 CXT is an RTX for the static chain value for the function. */
16460
16461void
a2369ed3 16462rs6000_initialize_trampoline (rtx addr, rtx fnaddr, rtx cxt)
b6c9286a 16463{
ac2a93a1 16464 enum machine_mode pmode = Pmode;
8bd04c56
MM		 16465 int regsize = (TARGET_32BIT) ? 4 : 8;
16466 rtx ctx_reg = force_reg (pmode, cxt);
b6c9286a
MM		 16467
16468 switch (DEFAULT_ABI)
16469 {
16470 default:
37409796 16471 gcc_unreachable ();
b6c9286a 16472
8bd04c56 16473/* Macros to shorten the code expansions below. */
39403d82 16474#define MEM_DEREF(addr) gen_rtx_MEM (pmode, memory_address (pmode, addr))
c5c76735
JL		 16475#define MEM_PLUS(addr,offset) \
16476 gen_rtx_MEM (pmode, memory_address (pmode, plus_constant (addr, offset)))
7c59dc5d 16477
b6c9286a
MM		 16478 /* Under AIX, just build the 3 word function descriptor */
16479 case ABI_AIX:
8bd04c56
MM		 16480 {
16481 rtx fn_reg = gen_reg_rtx (pmode);
16482 rtx toc_reg = gen_reg_rtx (pmode);
16483 emit_move_insn (fn_reg, MEM_DEREF (fnaddr));
1cb18e3c 16484 emit_move_insn (toc_reg, MEM_PLUS (fnaddr, regsize));
8bd04c56
MM		 16485 emit_move_insn (MEM_DEREF (addr), fn_reg);
16486 emit_move_insn (MEM_PLUS (addr, regsize), toc_reg);
16487 emit_move_insn (MEM_PLUS (addr, 2*regsize), ctx_reg);
16488 }
b6c9286a
MM		 16489 break;
16490
4dabc42d
TC		 16491 /* Under V.4/eabi/darwin, __trampoline_setup does the real work. */
16492 case ABI_DARWIN:
b6c9286a 16493 case ABI_V4:
39403d82 16494 emit_library_call (gen_rtx_SYMBOL_REF (SImode, "__trampoline_setup"),
eaf1bcf1
MM		 16495 FALSE, VOIDmode, 4,
16496 addr, pmode,
16497 GEN_INT (rs6000_trampoline_size ()), SImode,
16498 fnaddr, pmode,
16499 ctx_reg, pmode);
b6c9286a 16500 break;
b6c9286a
MM		 16501 }
16502
16503 return;
16504}
7509c759
MM		 16505
16506\f
91d231cb 16507/* Table of valid machine attributes. */
a4f6c312 16508
91d231cb 16509const struct attribute_spec rs6000_attribute_table[] =
7509c759 16510{
91d231cb 16511 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
8bb418a3 16512 { "altivec", 1, 1, false, true, false, rs6000_handle_altivec_attribute },
a5c76ee6
ZW		 16513 { "longcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute },
16514 { "shortcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute },
005c1a13
GK		 16515#ifdef SUBTARGET_ATTRIBUTE_TABLE
16516 SUBTARGET_ATTRIBUTE_TABLE,
16517#endif
a5c76ee6 16518 { NULL, 0, 0, false, false, false, NULL }
91d231cb 16519};
7509c759 16520
8bb418a3
ZL		 16521/* Handle the "altivec" attribute. The attribute may have
16522 arguments as follows:
f676971a 16523
8bb418a3
ZL		 16524 __attribute__((altivec(vector__)))
16525 __attribute__((altivec(pixel__))) (always followed by 'unsigned short')
16526 __attribute__((altivec(bool__))) (always followed by 'unsigned')
16527
16528 and may appear more than once (e.g., 'vector bool char') in a
16529 given declaration. */
16530
16531static tree
f90ac3f0
UP		 16532rs6000_handle_altivec_attribute (tree *node,
16533 tree name ATTRIBUTE_UNUSED,
16534 tree args,
8bb418a3
ZL		 16535 int flags ATTRIBUTE_UNUSED,
16536 bool *no_add_attrs)
16537{
16538 tree type = *node, result = NULL_TREE;
16539 enum machine_mode mode;
16540 int unsigned_p;
16541 char altivec_type
16542 = ((args && TREE_CODE (args) == TREE_LIST && TREE_VALUE (args)
16543 && TREE_CODE (TREE_VALUE (args)) == IDENTIFIER_NODE)
16544 ? *IDENTIFIER_POINTER (TREE_VALUE (args))
f676971a 16545 : '?');
8bb418a3
ZL		 16546
16547 while (POINTER_TYPE_P (type)
16548 || TREE_CODE (type) == FUNCTION_TYPE
16549 || TREE_CODE (type) == METHOD_TYPE
16550 || TREE_CODE (type) == ARRAY_TYPE)
16551 type = TREE_TYPE (type);
16552
16553 mode = TYPE_MODE (type);
16554
f90ac3f0
UP		 16555 /* Check for invalid AltiVec type qualifiers. */
16556 if (type == long_unsigned_type_node || type == long_integer_type_node)
16557 {
16558 if (TARGET_64BIT)
16559 error ("use of %<long%> in AltiVec types is invalid for 64-bit code");
16560 else if (rs6000_warn_altivec_long)
d4ee4d25 16561 warning (0, "use of %<long%> in AltiVec types is deprecated; use %<int%>");
f90ac3f0
UP		 16562 }
16563 else if (type == long_long_unsigned_type_node
16564 || type == long_long_integer_type_node)
16565 error ("use of %<long long%> in AltiVec types is invalid");
16566 else if (type == double_type_node)
16567 error ("use of %<double%> in AltiVec types is invalid");
16568 else if (type == long_double_type_node)
16569 error ("use of %<long double%> in AltiVec types is invalid");
16570 else if (type == boolean_type_node)
16571 error ("use of boolean types in AltiVec types is invalid");
16572 else if (TREE_CODE (type) == COMPLEX_TYPE)
16573 error ("use of %<complex%> in AltiVec types is invalid");
8bb418a3
ZL		 16574
16575 switch (altivec_type)
16576 {
16577 case 'v':
8df83eae 16578 unsigned_p = TYPE_UNSIGNED (type);
8bb418a3
ZL		 16579 switch (mode)
16580 {
c4ad648e
AM		 16581 case SImode:
16582 result = (unsigned_p ? unsigned_V4SI_type_node : V4SI_type_node);
16583 break;
16584 case HImode:
16585 result = (unsigned_p ? unsigned_V8HI_type_node : V8HI_type_node);
16586 break;
16587 case QImode:
16588 result = (unsigned_p ? unsigned_V16QI_type_node : V16QI_type_node);
16589 break;
16590 case SFmode: result = V4SF_type_node; break;
16591 /* If the user says 'vector int bool', we may be handed the 'bool'
16592 attribute _before_ the 'vector' attribute, and so select the
16593 proper type in the 'b' case below. */
16594 case V4SImode: case V8HImode: case V16QImode: case V4SFmode:
16595 result = type;
16596 default: break;
8bb418a3
ZL		 16597 }
16598 break;
16599 case 'b':
16600 switch (mode)
16601 {
c4ad648e
AM		 16602 case SImode: case V4SImode: result = bool_V4SI_type_node; break;
16603 case HImode: case V8HImode: result = bool_V8HI_type_node; break;
16604 case QImode: case V16QImode: result = bool_V16QI_type_node;
16605 default: break;
8bb418a3
ZL		 16606 }
16607 break;
16608 case 'p':
16609 switch (mode)
16610 {
c4ad648e
AM		 16611 case V8HImode: result = pixel_V8HI_type_node;
16612 default: break;
8bb418a3
ZL		 16613 }
16614 default: break;
16615 }
16616
7958a2a6
FJ		 16617 if (result && result != type && TYPE_READONLY (type))
16618 result = build_qualified_type (result, TYPE_QUAL_CONST);
16619
8bb418a3
ZL		 16620 *no_add_attrs = true; /* No need to hang on to the attribute. */
16621
f90ac3f0 16622 if (result)
8bb418a3
ZL		 16623 *node = reconstruct_complex_type (*node, result);
16624
16625 return NULL_TREE;
16626}
16627
f18eca82
ZL		 16628/* AltiVec defines four built-in scalar types that serve as vector
16629 elements; we must teach the compiler how to mangle them. */
16630
16631static const char *
16632rs6000_mangle_fundamental_type (tree type)
16633{
16634 if (type == bool_char_type_node) return "U6__boolc";
16635 if (type == bool_short_type_node) return "U6__bools";
16636 if (type == pixel_type_node) return "u7__pixel";
16637 if (type == bool_int_type_node) return "U6__booli";
16638
16639 /* For all other types, use normal C++ mangling. */
16640 return NULL;
16641}
16642
a5c76ee6
ZW		 16643/* Handle a "longcall" or "shortcall" attribute; arguments as in
16644 struct attribute_spec.handler. */
a4f6c312 16645
91d231cb 16646static tree
f676971a
EC		 16647rs6000_handle_longcall_attribute (tree *node, tree name,
16648 tree args ATTRIBUTE_UNUSED,
16649 int flags ATTRIBUTE_UNUSED,
a2369ed3 16650 bool *no_add_attrs)
91d231cb
JM		 16651{
16652 if (TREE_CODE (*node) != FUNCTION_TYPE
16653 && TREE_CODE (*node) != FIELD_DECL
16654 && TREE_CODE (*node) != TYPE_DECL)
16655 {
5c498b10 16656 warning (OPT_Wattributes, "%qs attribute only applies to functions",
91d231cb
JM		 16657 IDENTIFIER_POINTER (name));
16658 *no_add_attrs = true;
16659 }
6a4cee5f 16660
91d231cb 16661 return NULL_TREE;
7509c759
MM		 16662}
16663
a5c76ee6
ZW		 16664/* Set longcall attributes on all functions declared when
16665 rs6000_default_long_calls is true. */
16666static void
a2369ed3 16667rs6000_set_default_type_attributes (tree type)
a5c76ee6
ZW		 16668{
16669 if (rs6000_default_long_calls
16670 && (TREE_CODE (type) == FUNCTION_TYPE
16671 || TREE_CODE (type) == METHOD_TYPE))
16672 TYPE_ATTRIBUTES (type) = tree_cons (get_identifier ("longcall"),
16673 NULL_TREE,
16674 TYPE_ATTRIBUTES (type));
16675}
16676
3cb999d8
DE		 16677/* Return a reference suitable for calling a function with the
16678 longcall attribute. */
a4f6c312 16679
9390387d 16680rtx
a2369ed3 16681rs6000_longcall_ref (rtx call_ref)
6a4cee5f 16682{
d330fd93 16683 const char *call_name;
6a4cee5f
MM		 16684 tree node;
16685
16686 if (GET_CODE (call_ref) != SYMBOL_REF)
16687 return call_ref;
16688
16689 /* System V adds '.' to the internal name, so skip them. */
16690 call_name = XSTR (call_ref, 0);
16691 if (*call_name == '.')
16692 {
16693 while (*call_name == '.')
16694 call_name++;
16695
16696 node = get_identifier (call_name);
39403d82 16697 call_ref = gen_rtx_SYMBOL_REF (VOIDmode, IDENTIFIER_POINTER (node));
6a4cee5f
MM		 16698 }
16699
16700 return force_reg (Pmode, call_ref);
16701}
7509c759 16702\f
b64a1b53
RH		 16703#ifdef USING_ELFOS_H
16704
7509c759
MM		 16705/* A C statement or statements to switch to the appropriate section
16706 for output of RTX in mode MODE. You can assume that RTX is some
16707 kind of constant in RTL. The argument MODE is redundant except in
16708 the case of a `const_int' rtx. Select the section by calling
16709 `text_section' or one of the alternatives for other sections.
16710
16711 Do not define this macro if you put all constants in the read-only
16712 data section. */
16713
b64a1b53 16714static void
f676971a 16715rs6000_elf_select_rtx_section (enum machine_mode mode, rtx x,
a2369ed3 16716 unsigned HOST_WIDE_INT align)
7509c759 16717{
a9098fd0 16718 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode))
7509c759 16719 toc_section ();
7509c759 16720 else
b64a1b53 16721 default_elf_select_rtx_section (mode, x, align);
7509c759
MM		 16722}
16723
16724/* A C statement or statements to switch to the appropriate
16725 section for output of DECL. DECL is either a `VAR_DECL' node
16726 or a constant of some sort. RELOC indicates whether forming
16727 the initial value of DECL requires link-time relocations. */
16728
ae46c4e0 16729static void
f676971a 16730rs6000_elf_select_section (tree decl, int reloc,
a2369ed3 16731 unsigned HOST_WIDE_INT align)
7509c759 16732{
f1384257
AM		 16733 /* Pretend that we're always building for a shared library when
16734 ABI_AIX, because otherwise we end up with dynamic relocations
16735 in read-only sections. This happens for function pointers,
16736 references to vtables in typeinfo, and probably other cases. */
0e5dbd9b
DE		 16737 default_elf_select_section_1 (decl, reloc, align,
16738 flag_pic || DEFAULT_ABI == ABI_AIX);
63019373
GK		 16739}
16740
16741/* A C statement to build up a unique section name, expressed as a
16742 STRING_CST node, and assign it to DECL_SECTION_NAME (decl).
16743 RELOC indicates whether the initial value of EXP requires
16744 link-time relocations. If you do not define this macro, GCC will use
16745 the symbol name prefixed by `.' as the section name. Note - this
f5143c46 16746 macro can now be called for uninitialized data items as well as
4912a07c 16747 initialized data and functions. */
63019373 16748
ae46c4e0 16749static void
a2369ed3 16750rs6000_elf_unique_section (tree decl, int reloc)
63019373 16751{
f1384257
AM		 16752 /* As above, pretend that we're always building for a shared library
16753 when ABI_AIX, to avoid dynamic relocations in read-only sections. */
0e5dbd9b
DE		 16754 default_unique_section_1 (decl, reloc,
16755 flag_pic || DEFAULT_ABI == ABI_AIX);
7509c759 16756}
d9407988 16757\f
d1908feb
JJ		 16758/* For a SYMBOL_REF, set generic flags and then perform some
16759 target-specific processing.
16760
d1908feb
JJ		 16761 When the AIX ABI is requested on a non-AIX system, replace the
16762 function name with the real name (with a leading .) rather than the
16763 function descriptor name. This saves a lot of overriding code to
16764 read the prefixes. */
d9407988 16765
fb49053f 16766static void
a2369ed3 16767rs6000_elf_encode_section_info (tree decl, rtx rtl, int first)
d9407988 16768{
d1908feb 16769 default_encode_section_info (decl, rtl, first);
b2003250 16770
d1908feb
JJ		 16771 if (first
16772 && TREE_CODE (decl) == FUNCTION_DECL
16773 && !TARGET_AIX
16774 && DEFAULT_ABI == ABI_AIX)
d9407988 16775 {
c6a2438a 16776 rtx sym_ref = XEXP (rtl, 0);
d1908feb
JJ		 16777 size_t len = strlen (XSTR (sym_ref, 0));
16778 char *str = alloca (len + 2);
16779 str[0] = '.';
16780 memcpy (str + 1, XSTR (sym_ref, 0), len + 1);
16781 XSTR (sym_ref, 0) = ggc_alloc_string (str, len + 1);
d9407988 16782 }
d9407988
MM		 16783}
16784
0e5dbd9b 16785static bool
a2369ed3 16786rs6000_elf_in_small_data_p (tree decl)
0e5dbd9b
DE		 16787{
16788 if (rs6000_sdata == SDATA_NONE)
16789 return false;
16790
7482ad25
AF		 16791 /* We want to merge strings, so we never consider them small data. */
16792 if (TREE_CODE (decl) == STRING_CST)
16793 return false;
16794
16795 /* Functions are never in the small data area. */
16796 if (TREE_CODE (decl) == FUNCTION_DECL)
16797 return false;
16798
0e5dbd9b
DE		 16799 if (TREE_CODE (decl) == VAR_DECL && DECL_SECTION_NAME (decl))
16800 {
16801 const char *section = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
16802 if (strcmp (section, ".sdata") == 0
16803 || strcmp (section, ".sdata2") == 0
20bfcd69
GK		 16804 || strcmp (section, ".sbss") == 0
16805 || strcmp (section, ".sbss2") == 0
16806 || strcmp (section, ".PPC.EMB.sdata0") == 0
16807 || strcmp (section, ".PPC.EMB.sbss0") == 0)
0e5dbd9b
DE		 16808 return true;
16809 }
16810 else
16811 {
16812 HOST_WIDE_INT size = int_size_in_bytes (TREE_TYPE (decl));
16813
16814 if (size > 0
307b599c 16815 && (unsigned HOST_WIDE_INT) size <= g_switch_value
20bfcd69
GK		 16816 /* If it's not public, and we're not going to reference it there,
16817 there's no need to put it in the small data section. */
0e5dbd9b
DE		 16818 && (rs6000_sdata != SDATA_DATA || TREE_PUBLIC (decl)))
16819 return true;
16820 }
16821
16822 return false;
16823}
16824
b91da81f 16825#endif /* USING_ELFOS_H */
000034eb 16826
a6c2a102 16827\f
000034eb 16828/* Return a REG that occurs in ADDR with coefficient 1.
02441cd6
JL		 16829 ADDR can be effectively incremented by incrementing REG.
16830
16831 r0 is special and we must not select it as an address
16832 register by this routine since our caller will try to
16833 increment the returned register via an "la" instruction. */
000034eb 16834
9390387d 16835rtx
a2369ed3 16836find_addr_reg (rtx addr)
000034eb
DE		 16837{
16838 while (GET_CODE (addr) == PLUS)
16839 {
02441cd6
JL		 16840 if (GET_CODE (XEXP (addr, 0)) == REG
16841 && REGNO (XEXP (addr, 0)) != 0)
000034eb 16842 addr = XEXP (addr, 0);
02441cd6
JL		 16843 else if (GET_CODE (XEXP (addr, 1)) == REG
16844 && REGNO (XEXP (addr, 1)) != 0)
000034eb
DE		 16845 addr = XEXP (addr, 1);
16846 else if (CONSTANT_P (XEXP (addr, 0)))
16847 addr = XEXP (addr, 1);
16848 else if (CONSTANT_P (XEXP (addr, 1)))
16849 addr = XEXP (addr, 0);
16850 else
37409796 16851 gcc_unreachable ();
000034eb 16852 }
37409796
NS		 16853 gcc_assert (GET_CODE (addr) == REG && REGNO (addr) != 0);
16854 return addr;
000034eb
DE		 16855}
16856
a6c2a102 16857void
a2369ed3 16858rs6000_fatal_bad_address (rtx op)
a6c2a102
DE		 16859{
16860 fatal_insn ("bad address", op);
16861}
c8023011 16862
ee890fe2
SS		 16863#if TARGET_MACHO
16864
efdba735 16865static tree branch_island_list = 0;
ee890fe2 16866
efdba735
SH		 16867/* Remember to generate a branch island for far calls to the given
16868 function. */
ee890fe2 16869
f676971a 16870static void
c4ad648e
AM		 16871add_compiler_branch_island (tree label_name, tree function_name,
16872 int line_number)
ee890fe2 16873{
efdba735 16874 tree branch_island = build_tree_list (function_name, label_name);
7d60be94 16875 TREE_TYPE (branch_island) = build_int_cst (NULL_TREE, line_number);
efdba735
SH		 16876 TREE_CHAIN (branch_island) = branch_island_list;
16877 branch_island_list = branch_island;
ee890fe2
SS		 16878}
16879
efdba735
SH		 16880#define BRANCH_ISLAND_LABEL_NAME(BRANCH_ISLAND) TREE_VALUE (BRANCH_ISLAND)
16881#define BRANCH_ISLAND_FUNCTION_NAME(BRANCH_ISLAND) TREE_PURPOSE (BRANCH_ISLAND)
16882#define BRANCH_ISLAND_LINE_NUMBER(BRANCH_ISLAND) \
16883 TREE_INT_CST_LOW (TREE_TYPE (BRANCH_ISLAND))
ee890fe2 16884
efdba735
SH		 16885/* Generate far-jump branch islands for everything on the
16886 branch_island_list. Invoked immediately after the last instruction
16887 of the epilogue has been emitted; the branch-islands must be
16888 appended to, and contiguous with, the function body. Mach-O stubs
16889 are generated in machopic_output_stub(). */
ee890fe2 16890
efdba735
SH		 16891static void
16892macho_branch_islands (void)
16893{
16894 char tmp_buf[512];
16895 tree branch_island;
16896
16897 for (branch_island = branch_island_list;
16898 branch_island;
16899 branch_island = TREE_CHAIN (branch_island))
16900 {
16901 const char *label =
16902 IDENTIFIER_POINTER (BRANCH_ISLAND_LABEL_NAME (branch_island));
16903 const char *name =
11abc112 16904 IDENTIFIER_POINTER (BRANCH_ISLAND_FUNCTION_NAME (branch_island));
efdba735
SH		 16905 char name_buf[512];
16906 /* Cheap copy of the details from the Darwin ASM_OUTPUT_LABELREF(). */
16907 if (name[0] == '*' || name[0] == '&')
16908 strcpy (name_buf, name+1);
16909 else
16910 {
16911 name_buf[0] = '_';
16912 strcpy (name_buf+1, name);
16913 }
16914 strcpy (tmp_buf, "\n");
16915 strcat (tmp_buf, label);
ee890fe2 16916#if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
efdba735 16917 if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG)
93a27b7b 16918 dbxout_stabd (N_SLINE, BRANCH_ISLAND_LINE_NUMBER (branch_island));
ee890fe2 16919#endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
efdba735
SH		 16920 if (flag_pic)
16921 {
16922 strcat (tmp_buf, ":\n\tmflr r0\n\tbcl 20,31,");
16923 strcat (tmp_buf, label);
16924 strcat (tmp_buf, "_pic\n");
16925 strcat (tmp_buf, label);
16926 strcat (tmp_buf, "_pic:\n\tmflr r11\n");
f676971a 16927
efdba735
SH		 16928 strcat (tmp_buf, "\taddis r11,r11,ha16(");
16929 strcat (tmp_buf, name_buf);
16930 strcat (tmp_buf, " - ");
16931 strcat (tmp_buf, label);
16932 strcat (tmp_buf, "_pic)\n");
f676971a 16933
efdba735 16934 strcat (tmp_buf, "\tmtlr r0\n");
f676971a 16935
efdba735
SH		 16936 strcat (tmp_buf, "\taddi r12,r11,lo16(");
16937 strcat (tmp_buf, name_buf);
16938 strcat (tmp_buf, " - ");
16939 strcat (tmp_buf, label);
16940 strcat (tmp_buf, "_pic)\n");
f676971a 16941
efdba735
SH		 16942 strcat (tmp_buf, "\tmtctr r12\n\tbctr\n");
16943 }
16944 else
16945 {
16946 strcat (tmp_buf, ":\nlis r12,hi16(");
16947 strcat (tmp_buf, name_buf);
16948 strcat (tmp_buf, ")\n\tori r12,r12,lo16(");
16949 strcat (tmp_buf, name_buf);
16950 strcat (tmp_buf, ")\n\tmtctr r12\n\tbctr");
16951 }
16952 output_asm_insn (tmp_buf, 0);
ee890fe2 16953#if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
efdba735 16954 if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG)
93a27b7b 16955 dbxout_stabd (N_SLINE, BRANCH_ISLAND_LINE_NUMBER (branch_island));
ee890fe2 16956#endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
efdba735 16957 }
ee890fe2 16958
efdba735 16959 branch_island_list = 0;
ee890fe2
SS		 16960}
16961
16962/* NO_PREVIOUS_DEF checks in the link list whether the function name is
16963 already there or not. */
16964
efdba735 16965static int
a2369ed3 16966no_previous_def (tree function_name)
ee890fe2 16967{
efdba735
SH		 16968 tree branch_island;
16969 for (branch_island = branch_island_list;
16970 branch_island;
16971 branch_island = TREE_CHAIN (branch_island))
16972 if (function_name == BRANCH_ISLAND_FUNCTION_NAME (branch_island))
ee890fe2
SS		 16973 return 0;
16974 return 1;
16975}
16976
16977/* GET_PREV_LABEL gets the label name from the previous definition of
16978 the function. */
16979
efdba735 16980static tree
a2369ed3 16981get_prev_label (tree function_name)
ee890fe2 16982{
efdba735
SH		 16983 tree branch_island;
16984 for (branch_island = branch_island_list;
16985 branch_island;
16986 branch_island = TREE_CHAIN (branch_island))
16987 if (function_name == BRANCH_ISLAND_FUNCTION_NAME (branch_island))
16988 return BRANCH_ISLAND_LABEL_NAME (branch_island);
ee890fe2
SS		 16989 return 0;
16990}
16991
16992/* INSN is either a function call or a millicode call. It may have an
f676971a 16993 unconditional jump in its delay slot.
ee890fe2
SS		 16994
16995 CALL_DEST is the routine we are calling. */
16996
16997char *
c4ad648e
AM		 16998output_call (rtx insn, rtx *operands, int dest_operand_number,
16999 int cookie_operand_number)
ee890fe2
SS		 17000{
17001 static char buf[256];
efdba735
SH		 17002 if (GET_CODE (operands[dest_operand_number]) == SYMBOL_REF
17003 && (INTVAL (operands[cookie_operand_number]) & CALL_LONG))
ee890fe2
SS		 17004 {
17005 tree labelname;
efdba735 17006 tree funname = get_identifier (XSTR (operands[dest_operand_number], 0));
f676971a 17007
ee890fe2
SS		 17008 if (no_previous_def (funname))
17009 {
308c142a 17010 int line_number = 0;
ee890fe2
SS		 17011 rtx label_rtx = gen_label_rtx ();
17012 char *label_buf, temp_buf[256];
17013 ASM_GENERATE_INTERNAL_LABEL (temp_buf, "L",
17014 CODE_LABEL_NUMBER (label_rtx));
17015 label_buf = temp_buf[0] == '*' ? temp_buf + 1 : temp_buf;
17016 labelname = get_identifier (label_buf);
17017 for (; insn && GET_CODE (insn) != NOTE; insn = PREV_INSN (insn));
17018 if (insn)
17019 line_number = NOTE_LINE_NUMBER (insn);
efdba735 17020 add_compiler_branch_island (labelname, funname, line_number);
ee890fe2
SS		 17021 }
17022 else
17023 labelname = get_prev_label (funname);
17024
efdba735
SH		 17025 /* "jbsr foo, L42" is Mach-O for "Link as 'bl foo' if a 'bl'
17026 instruction will reach 'foo', otherwise link as 'bl L42'".
17027 "L42" should be a 'branch island', that will do a far jump to
17028 'foo'. Branch islands are generated in
17029 macho_branch_islands(). */
ee890fe2 17030 sprintf (buf, "jbsr %%z%d,%.246s",
efdba735 17031 dest_operand_number, IDENTIFIER_POINTER (labelname));
ee890fe2
SS		 17032 }
17033 else
efdba735
SH		 17034 sprintf (buf, "bl %%z%d", dest_operand_number);
17035 return buf;
ee890fe2
SS		 17036}
17037
ee890fe2
SS		 17038/* Generate PIC and indirect symbol stubs. */
17039
17040void
a2369ed3 17041machopic_output_stub (FILE *file, const char *symb, const char *stub)
ee890fe2
SS		 17042{
17043 unsigned int length;
a4f6c312
SS		 17044 char *symbol_name, *lazy_ptr_name;
17045 char *local_label_0;
ee890fe2
SS		 17046 static int label = 0;
17047
df56a27f 17048 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
772c5265 17049 symb = (*targetm.strip_name_encoding) (symb);
df56a27f 17050
ee890fe2 17051
ee890fe2
SS		 17052 length = strlen (symb);
17053 symbol_name = alloca (length + 32);
17054 GEN_SYMBOL_NAME_FOR_SYMBOL (symbol_name, symb, length);
17055
17056 lazy_ptr_name = alloca (length + 32);
17057 GEN_LAZY_PTR_NAME_FOR_SYMBOL (lazy_ptr_name, symb, length);
17058
ee890fe2 17059 if (flag_pic == 2)
d3c300d2 17060 machopic_picsymbol_stub1_section ();
ee890fe2 17061 else
d3c300d2 17062 machopic_symbol_stub1_section ();
ee890fe2
SS		 17063
17064 if (flag_pic == 2)
17065 {
d974312d
DJ		 17066 fprintf (file, "\t.align 5\n");
17067
17068 fprintf (file, "%s:\n", stub);
17069 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
17070
876455fa 17071 label++;
89da1f32 17072 local_label_0 = alloca (sizeof ("\"L00000000000$spb\""));
876455fa 17073 sprintf (local_label_0, "\"L%011d$spb\"", label);
f676971a 17074
ee890fe2
SS		 17075 fprintf (file, "\tmflr r0\n");
17076 fprintf (file, "\tbcl 20,31,%s\n", local_label_0);
17077 fprintf (file, "%s:\n\tmflr r11\n", local_label_0);
17078 fprintf (file, "\taddis r11,r11,ha16(%s-%s)\n",
17079 lazy_ptr_name, local_label_0);
17080 fprintf (file, "\tmtlr r0\n");
3d0e2d58
SS		 17081 fprintf (file, "\t%s r12,lo16(%s-%s)(r11)\n",
17082 (TARGET_64BIT ? "ldu" : "lwzu"),
ee890fe2
SS		 17083 lazy_ptr_name, local_label_0);
17084 fprintf (file, "\tmtctr r12\n");
ee890fe2
SS		 17085 fprintf (file, "\tbctr\n");
17086 }
17087 else
d974312d
DJ		 17088 {
17089 fprintf (file, "\t.align 4\n");
17090
17091 fprintf (file, "%s:\n", stub);
17092 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
17093
17094 fprintf (file, "\tlis r11,ha16(%s)\n", lazy_ptr_name);
d9e4e4f5
SS		 17095 fprintf (file, "\t%s r12,lo16(%s)(r11)\n",
17096 (TARGET_64BIT ? "ldu" : "lwzu"),
17097 lazy_ptr_name);
d974312d
DJ		 17098 fprintf (file, "\tmtctr r12\n");
17099 fprintf (file, "\tbctr\n");
17100 }
f676971a 17101
ee890fe2
SS		 17102 machopic_lazy_symbol_ptr_section ();
17103 fprintf (file, "%s:\n", lazy_ptr_name);
17104 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
49bd1d27
SS		 17105 fprintf (file, "%sdyld_stub_binding_helper\n",
17106 (TARGET_64BIT ? DOUBLE_INT_ASM_OP : "\t.long\t"));
ee890fe2
SS		 17107}
17108
17109/* Legitimize PIC addresses. If the address is already
17110 position-independent, we return ORIG. Newly generated
17111 position-independent addresses go into a reg. This is REG if non
17112 zero, otherwise we allocate register(s) as necessary. */
17113
9390387d 17114#define SMALL_INT(X) ((unsigned) (INTVAL (X) + 0x8000) < 0x10000)
ee890fe2
SS		 17115
17116rtx
f676971a 17117rs6000_machopic_legitimize_pic_address (rtx orig, enum machine_mode mode,
a2369ed3 17118 rtx reg)
ee890fe2
SS		 17119{
17120 rtx base, offset;
17121
17122 if (reg == NULL && ! reload_in_progress && ! reload_completed)
17123 reg = gen_reg_rtx (Pmode);
17124
17125 if (GET_CODE (orig) == CONST)
17126 {
37409796
NS		 17127 rtx reg_temp;
17128
ee890fe2
SS		 17129 if (GET_CODE (XEXP (orig, 0)) == PLUS
17130 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
17131 return orig;
17132
37409796
NS		 17133 gcc_assert (GET_CODE (XEXP (orig, 0)) == PLUS);
17134
17135 /* Use a different reg for the intermediate value, as
17136 it will be marked UNCHANGING. */
17137 reg_temp = no_new_pseudos ? reg : gen_reg_rtx (Pmode);
17138 base = rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 0),
17139 Pmode, reg_temp);
17140 offset =
17141 rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 1),
17142 Pmode, reg);
17143
ee890fe2
SS		 17144 if (GET_CODE (offset) == CONST_INT)
17145 {
17146 if (SMALL_INT (offset))
ed8908e7 17147 return plus_constant (base, INTVAL (offset));
ee890fe2
SS		 17148 else if (! reload_in_progress && ! reload_completed)
17149 offset = force_reg (Pmode, offset);
17150 else
c859cda6
DJ		 17151 {
17152 rtx mem = force_const_mem (Pmode, orig);
17153 return machopic_legitimize_pic_address (mem, Pmode, reg);
17154 }
ee890fe2 17155 }
f1c25d3b 17156 return gen_rtx_PLUS (Pmode, base, offset);
ee890fe2
SS		 17157 }
17158
17159 /* Fall back on generic machopic code. */
17160 return machopic_legitimize_pic_address (orig, mode, reg);
17161}
17162
17163/* This is just a placeholder to make linking work without having to
17164 add this to the generic Darwin EXTRA_SECTIONS. If -mcall-aix is
17165 ever needed for Darwin (not too likely!) this would have to get a
17166 real definition. */
17167
17168void
863d938c 17169toc_section (void)
ee890fe2
SS		 17170{
17171}
17172
c4e18b1c
GK		 17173/* Output a .machine directive for the Darwin assembler, and call
17174 the generic start_file routine. */
17175
17176static void
17177rs6000_darwin_file_start (void)
17178{
94ff898d 17179 static const struct
c4e18b1c
GK		 17180 {
17181 const char *arg;
17182 const char *name;
17183 int if_set;
17184 } mapping[] = {
55dbfb48 17185 { "ppc64", "ppc64", MASK_64BIT },
c4e18b1c
GK		 17186 { "970", "ppc970", MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64 },
17187 { "power4", "ppc970", 0 },
17188 { "G5", "ppc970", 0 },
17189 { "7450", "ppc7450", 0 },
17190 { "7400", "ppc7400", MASK_ALTIVEC },
17191 { "G4", "ppc7400", 0 },
17192 { "750", "ppc750", 0 },
17193 { "740", "ppc750", 0 },
17194 { "G3", "ppc750", 0 },
17195 { "604e", "ppc604e", 0 },
17196 { "604", "ppc604", 0 },
17197 { "603e", "ppc603", 0 },
17198 { "603", "ppc603", 0 },
17199 { "601", "ppc601", 0 },
17200 { NULL, "ppc", 0 } };
17201 const char *cpu_id = "";
17202 size_t i;
94ff898d 17203
9390387d 17204 rs6000_file_start ();
c4e18b1c
GK		 17205
17206 /* Determine the argument to -mcpu=. Default to G3 if not specified. */
17207 for (i = 0; i < ARRAY_SIZE (rs6000_select); i++)
17208 if (rs6000_select[i].set_arch_p && rs6000_select[i].string
17209 && rs6000_select[i].string[0] != '\0')
17210 cpu_id = rs6000_select[i].string;
17211
17212 /* Look through the mapping array. Pick the first name that either
17213 matches the argument, has a bit set in IF_SET that is also set
17214 in the target flags, or has a NULL name. */
17215
17216 i = 0;
17217 while (mapping[i].arg != NULL
17218 && strcmp (mapping[i].arg, cpu_id) != 0
17219 && (mapping[i].if_set & target_flags) == 0)
17220 i++;
17221
17222 fprintf (asm_out_file, "\t.machine %s\n", mapping[i].name);
17223}
17224
ee890fe2 17225#endif /* TARGET_MACHO */
7c262518
RH		 17226
17227#if TARGET_ELF
17228static unsigned int
a2369ed3 17229rs6000_elf_section_type_flags (tree decl, const char *name, int reloc)
7c262518 17230{
1ff8f81a
AM		 17231 return default_section_type_flags_1 (decl, name, reloc,
17232 flag_pic || DEFAULT_ABI == ABI_AIX);
7c262518 17233}
d9f6800d
RH		 17234
17235/* Record an element in the table of global constructors. SYMBOL is
17236 a SYMBOL_REF of the function to be called; PRIORITY is a number
17237 between 0 and MAX_INIT_PRIORITY.
17238
17239 This differs from default_named_section_asm_out_constructor in
17240 that we have special handling for -mrelocatable. */
17241
17242static void
a2369ed3 17243rs6000_elf_asm_out_constructor (rtx symbol, int priority)
d9f6800d
RH		 17244{
17245 const char *section = ".ctors";
17246 char buf[16];
17247
17248 if (priority != DEFAULT_INIT_PRIORITY)
17249 {
17250 sprintf (buf, ".ctors.%.5u",
c4ad648e
AM		 17251 /* Invert the numbering so the linker puts us in the proper
17252 order; constructors are run from right to left, and the
17253 linker sorts in increasing order. */
17254 MAX_INIT_PRIORITY - priority);
d9f6800d
RH		 17255 section = buf;
17256 }
17257
715bdd29
RH		 17258 named_section_flags (section, SECTION_WRITE);
17259 assemble_align (POINTER_SIZE);
d9f6800d
RH		 17260
17261 if (TARGET_RELOCATABLE)
17262 {
17263 fputs ("\t.long (", asm_out_file);
17264 output_addr_const (asm_out_file, symbol);
17265 fputs (")@fixup\n", asm_out_file);
17266 }
17267 else
c8af3574 17268 assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1);
d9f6800d
RH		 17269}
17270
17271static void
a2369ed3 17272rs6000_elf_asm_out_destructor (rtx symbol, int priority)
d9f6800d
RH		 17273{
17274 const char *section = ".dtors";
17275 char buf[16];
17276
17277 if (priority != DEFAULT_INIT_PRIORITY)
17278 {
17279 sprintf (buf, ".dtors.%.5u",
c4ad648e
AM		 17280 /* Invert the numbering so the linker puts us in the proper
17281 order; constructors are run from right to left, and the
17282 linker sorts in increasing order. */
17283 MAX_INIT_PRIORITY - priority);
d9f6800d
RH		 17284 section = buf;
17285 }
17286
715bdd29
RH		 17287 named_section_flags (section, SECTION_WRITE);
17288 assemble_align (POINTER_SIZE);
d9f6800d
RH		 17289
17290 if (TARGET_RELOCATABLE)
17291 {
17292 fputs ("\t.long (", asm_out_file);
17293 output_addr_const (asm_out_file, symbol);
17294 fputs (")@fixup\n", asm_out_file);
17295 }
17296 else
c8af3574 17297 assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1);
d9f6800d 17298}
9739c90c
JJ		 17299
17300void
a2369ed3 17301rs6000_elf_declare_function_name (FILE *file, const char *name, tree decl)
9739c90c
JJ		 17302{
17303 if (TARGET_64BIT)
17304 {
17305 fputs ("\t.section\t\".opd\",\"aw\"\n\t.align 3\n", file);
17306 ASM_OUTPUT_LABEL (file, name);
17307 fputs (DOUBLE_INT_ASM_OP, file);
85b776df
AM		 17308 rs6000_output_function_entry (file, name);
17309 fputs (",.TOC.@tocbase,0\n\t.previous\n", file);
17310 if (DOT_SYMBOLS)
9739c90c 17311 {
85b776df 17312 fputs ("\t.size\t", file);
9739c90c 17313 assemble_name (file, name);
85b776df
AM		 17314 fputs (",24\n\t.type\t.", file);
17315 assemble_name (file, name);
17316 fputs (",@function\n", file);
17317 if (TREE_PUBLIC (decl) && ! DECL_WEAK (decl))
17318 {
17319 fputs ("\t.globl\t.", file);
17320 assemble_name (file, name);
17321 putc ('\n', file);
17322 }
9739c90c 17323 }
85b776df
AM		 17324 else
17325 ASM_OUTPUT_TYPE_DIRECTIVE (file, name, "function");
9739c90c 17326 ASM_DECLARE_RESULT (file, DECL_RESULT (decl));
85b776df
AM		 17327 rs6000_output_function_entry (file, name);
17328 fputs (":\n", file);
9739c90c
JJ		 17329 return;
17330 }
17331
17332 if (TARGET_RELOCATABLE
7f970b70 17333 && !TARGET_SECURE_PLT
9739c90c 17334 && (get_pool_size () != 0 || current_function_profile)
3c9eb5f4 17335 && uses_TOC ())
9739c90c
JJ		 17336 {
17337 char buf[256];
17338
17339 (*targetm.asm_out.internal_label) (file, "LCL", rs6000_pic_labelno);
17340
17341 ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1);
17342 fprintf (file, "\t.long ");
17343 assemble_name (file, buf);
17344 putc ('-', file);
17345 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
17346 assemble_name (file, buf);
17347 putc ('\n', file);
17348 }
17349
17350 ASM_OUTPUT_TYPE_DIRECTIVE (file, name, "function");
17351 ASM_DECLARE_RESULT (file, DECL_RESULT (decl));
17352
17353 if (DEFAULT_ABI == ABI_AIX)
17354 {
17355 const char *desc_name, *orig_name;
17356
17357 orig_name = (*targetm.strip_name_encoding) (name);
17358 desc_name = orig_name;
17359 while (*desc_name == '.')
17360 desc_name++;
17361
17362 if (TREE_PUBLIC (decl))
17363 fprintf (file, "\t.globl %s\n", desc_name);
17364
17365 fprintf (file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
17366 fprintf (file, "%s:\n", desc_name);
17367 fprintf (file, "\t.long %s\n", orig_name);
17368 fputs ("\t.long _GLOBAL_OFFSET_TABLE_\n", file);
17369 if (DEFAULT_ABI == ABI_AIX)
17370 fputs ("\t.long 0\n", file);
17371 fprintf (file, "\t.previous\n");
17372 }
17373 ASM_OUTPUT_LABEL (file, name);
17374}
1334b570
AM		 17375
17376static void
17377rs6000_elf_end_indicate_exec_stack (void)
17378{
17379 if (TARGET_32BIT)
17380 file_end_indicate_exec_stack ();
17381}
7c262518
RH		 17382#endif
17383
cbaaba19 17384#if TARGET_XCOFF
7c262518 17385static void
a2369ed3 17386rs6000_xcoff_asm_globalize_label (FILE *stream, const char *name)
b275d088
DE		 17387{
17388 fputs (GLOBAL_ASM_OP, stream);
17389 RS6000_OUTPUT_BASENAME (stream, name);
17390 putc ('\n', stream);
17391}
17392
17393static void
c18a5b6c
MM		 17394rs6000_xcoff_asm_named_section (const char *name, unsigned int flags,
17395 tree decl ATTRIBUTE_UNUSED)
7c262518 17396{
0e5dbd9b
DE		 17397 int smclass;
17398 static const char * const suffix[3] = { "PR", "RO", "RW" };
17399
17400 if (flags & SECTION_CODE)
17401 smclass = 0;
17402 else if (flags & SECTION_WRITE)
17403 smclass = 2;
17404 else
17405 smclass = 1;
17406
5b5198f7 17407 fprintf (asm_out_file, "\t.csect %s%s[%s],%u\n",
0e5dbd9b 17408 (flags & SECTION_CODE) ? "." : "",
5b5198f7 17409 name, suffix[smclass], flags & SECTION_ENTSIZE);
7c262518 17410}
ae46c4e0
RH		 17411
17412static void
f676971a 17413rs6000_xcoff_select_section (tree decl, int reloc,
c4ad648e 17414 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
ae46c4e0 17415{
5add3202 17416 if (decl_readonly_section_1 (decl, reloc, 1))
ae46c4e0 17417 {
0e5dbd9b 17418 if (TREE_PUBLIC (decl))
c4ad648e 17419 read_only_data_section ();
ae46c4e0 17420 else
c4ad648e 17421 read_only_private_data_section ();
ae46c4e0
RH		 17422 }
17423 else
17424 {
0e5dbd9b 17425 if (TREE_PUBLIC (decl))
c4ad648e 17426 data_section ();
ae46c4e0 17427 else
c4ad648e 17428 private_data_section ();
ae46c4e0
RH		 17429 }
17430}
17431
17432static void
a2369ed3 17433rs6000_xcoff_unique_section (tree decl, int reloc ATTRIBUTE_UNUSED)
ae46c4e0
RH		 17434{
17435 const char *name;
ae46c4e0 17436
5b5198f7
DE		 17437 /* Use select_section for private and uninitialized data. */
17438 if (!TREE_PUBLIC (decl)
17439 || DECL_COMMON (decl)
0e5dbd9b
DE		 17440 || DECL_INITIAL (decl) == NULL_TREE
17441 || DECL_INITIAL (decl) == error_mark_node
17442 || (flag_zero_initialized_in_bss
17443 && initializer_zerop (DECL_INITIAL (decl))))
17444 return;
17445
17446 name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
17447 name = (*targetm.strip_name_encoding) (name);
17448 DECL_SECTION_NAME (decl) = build_string (strlen (name), name);
ae46c4e0 17449}
b64a1b53 17450
fb49053f
RH		 17451/* Select section for constant in constant pool.
17452
17453 On RS/6000, all constants are in the private read-only data area.
17454 However, if this is being placed in the TOC it must be output as a
17455 toc entry. */
17456
b64a1b53 17457static void
f676971a 17458rs6000_xcoff_select_rtx_section (enum machine_mode mode, rtx x,
c4ad648e 17459 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
b64a1b53
RH		 17460{
17461 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode))
17462 toc_section ();
17463 else
17464 read_only_private_data_section ();
17465}
772c5265
RH		 17466
17467/* Remove any trailing [DS] or the like from the symbol name. */
17468
17469static const char *
a2369ed3 17470rs6000_xcoff_strip_name_encoding (const char *name)
772c5265
RH		 17471{
17472 size_t len;
17473 if (*name == '*')
17474 name++;
17475 len = strlen (name);
17476 if (name[len - 1] == ']')
17477 return ggc_alloc_string (name, len - 4);
17478 else
17479 return name;
17480}
17481
5add3202
DE		 17482/* Section attributes. AIX is always PIC. */
17483
17484static unsigned int
a2369ed3 17485rs6000_xcoff_section_type_flags (tree decl, const char *name, int reloc)
5add3202 17486{
5b5198f7
DE		 17487 unsigned int align;
17488 unsigned int flags = default_section_type_flags_1 (decl, name, reloc, 1);
17489
17490 /* Align to at least UNIT size. */
17491 if (flags & SECTION_CODE)
17492 align = MIN_UNITS_PER_WORD;
17493 else
17494 /* Increase alignment of large objects if not already stricter. */
17495 align = MAX ((DECL_ALIGN (decl) / BITS_PER_UNIT),
17496 int_size_in_bytes (TREE_TYPE (decl)) > MIN_UNITS_PER_WORD
17497 ? UNITS_PER_FP_WORD : MIN_UNITS_PER_WORD);
17498
17499 return flags | (exact_log2 (align) & SECTION_ENTSIZE);
5add3202 17500}
a5fe455b 17501
1bc7c5b6
ZW		 17502/* Output at beginning of assembler file.
17503
17504 Initialize the section names for the RS/6000 at this point.
17505
17506 Specify filename, including full path, to assembler.
17507
17508 We want to go into the TOC section so at least one .toc will be emitted.
17509 Also, in order to output proper .bs/.es pairs, we need at least one static
17510 [RW] section emitted.
17511
17512 Finally, declare mcount when profiling to make the assembler happy. */
17513
17514static void
863d938c 17515rs6000_xcoff_file_start (void)
1bc7c5b6
ZW		 17516{
17517 rs6000_gen_section_name (&xcoff_bss_section_name,
17518 main_input_filename, ".bss_");
17519 rs6000_gen_section_name (&xcoff_private_data_section_name,
17520 main_input_filename, ".rw_");
17521 rs6000_gen_section_name (&xcoff_read_only_section_name,
17522 main_input_filename, ".ro_");
17523
17524 fputs ("\t.file\t", asm_out_file);
17525 output_quoted_string (asm_out_file, main_input_filename);
17526 fputc ('\n', asm_out_file);
1bc7c5b6
ZW		 17527 if (write_symbols != NO_DEBUG)
17528 private_data_section ();
17529 text_section ();
17530 if (profile_flag)
17531 fprintf (asm_out_file, "\t.extern %s\n", RS6000_MCOUNT);
17532 rs6000_file_start ();
17533}
17534
a5fe455b
ZW		 17535/* Output at end of assembler file.
17536 On the RS/6000, referencing data should automatically pull in text. */
17537
17538static void
863d938c 17539rs6000_xcoff_file_end (void)
a5fe455b
ZW		 17540{
17541 text_section ();
17542 fputs ("_section_.text:\n", asm_out_file);
17543 data_section ();
17544 fputs (TARGET_32BIT
17545 ? "\t.long _section_.text\n" : "\t.llong _section_.text\n",
17546 asm_out_file);
17547}
f1384257 17548#endif /* TARGET_XCOFF */
0e5dbd9b 17549
3c50106f
RH		 17550/* Compute a (partial) cost for rtx X. Return true if the complete
17551 cost has been computed, and false if subexpressions should be
17552 scanned. In either case, *TOTAL contains the cost result. */
17553
17554static bool
1494c534 17555rs6000_rtx_costs (rtx x, int code, int outer_code, int *total)
3c50106f 17556{
f0517163
RS		 17557 enum machine_mode mode = GET_MODE (x);
17558
3c50106f
RH		 17559 switch (code)
17560 {
30a555d9 17561 /* On the RS/6000, if it is valid in the insn, it is free. */
3c50106f 17562 case CONST_INT:
066cd967
DE		 17563 if (((outer_code == SET
17564 || outer_code == PLUS
17565 || outer_code == MINUS)
17566 && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'I')
17567 || CONST_OK_FOR_LETTER_P (INTVAL (x), 'L')))
066cd967
DE		 17568 || (outer_code == AND
17569 && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'K')
22e54023
DE		 17570 || (CONST_OK_FOR_LETTER_P (INTVAL (x),
17571 mode == SImode ? 'L' : 'J'))
d5861a7a 17572 || mask_operand (x, VOIDmode)))
22e54023
DE		 17573 || ((outer_code == IOR || outer_code == XOR)
17574 && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'K')
17575 || (CONST_OK_FOR_LETTER_P (INTVAL (x),
17576 mode == SImode ? 'L' : 'J'))))
066cd967
DE		 17577 || outer_code == ASHIFT
17578 || outer_code == ASHIFTRT
17579 || outer_code == LSHIFTRT
17580 || outer_code == ROTATE
17581 || outer_code == ROTATERT
d5861a7a 17582 || outer_code == ZERO_EXTRACT
066cd967
DE		 17583 || (outer_code == MULT
17584 && CONST_OK_FOR_LETTER_P (INTVAL (x), 'I'))
22e54023
DE		 17585 || ((outer_code == DIV || outer_code == UDIV
17586 || outer_code == MOD || outer_code == UMOD)
17587 && exact_log2 (INTVAL (x)) >= 0)
066cd967
DE		 17588 || (outer_code == COMPARE
17589 && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'I')
22e54023
DE		 17590 || CONST_OK_FOR_LETTER_P (INTVAL (x), 'K')))
17591 || (outer_code == EQ
17592 && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'I')
17593 || CONST_OK_FOR_LETTER_P (INTVAL (x), 'K')
17594 || (CONST_OK_FOR_LETTER_P (INTVAL (x),
17595 mode == SImode ? 'L' : 'J'))))
17596 || (outer_code == GTU
17597 && CONST_OK_FOR_LETTER_P (INTVAL (x), 'I'))
17598 || (outer_code == LTU
17599 && CONST_OK_FOR_LETTER_P (INTVAL (x), 'P')))
066cd967
DE		 17600 {
17601 *total = 0;
17602 return true;
17603 }
17604 else if ((outer_code == PLUS
4ae234b0 17605 && reg_or_add_cint_operand (x, VOIDmode))
066cd967 17606 || (outer_code == MINUS
4ae234b0 17607 && reg_or_sub_cint_operand (x, VOIDmode))
066cd967
DE		 17608 || ((outer_code == SET
17609 || outer_code == IOR
17610 || outer_code == XOR)
17611 && (INTVAL (x)
17612 & ~ (unsigned HOST_WIDE_INT) 0xffffffff) == 0))
17613 {
17614 *total = COSTS_N_INSNS (1);
17615 return true;
17616 }
17617 /* FALLTHRU */
17618
17619 case CONST_DOUBLE:
17620 if (mode == DImode
17621 && ((outer_code == AND
17622 && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'K')
17623 || CONST_OK_FOR_LETTER_P (INTVAL (x), 'L')
4ae234b0 17624 || mask_operand (x, DImode)))
066cd967
DE		 17625 || ((outer_code == IOR || outer_code == XOR)
17626 && CONST_DOUBLE_HIGH (x) == 0
17627 && (CONST_DOUBLE_LOW (x)
17628 & ~ (unsigned HOST_WIDE_INT) 0xffff) == 0)))
17629 {
17630 *total = 0;
17631 return true;
17632 }
17633 else if (mode == DImode
17634 && (outer_code == SET
17635 || outer_code == IOR
17636 || outer_code == XOR)
17637 && CONST_DOUBLE_HIGH (x) == 0)
17638 {
17639 *total = COSTS_N_INSNS (1);
17640 return true;
17641 }
17642 /* FALLTHRU */
17643
3c50106f 17644 case CONST:
066cd967 17645 case HIGH:
3c50106f 17646 case SYMBOL_REF:
066cd967
DE		 17647 case MEM:
17648 /* When optimizing for size, MEM should be slightly more expensive
17649 than generating address, e.g., (plus (reg) (const)).
c112cf2b 17650 L1 cache latency is about two instructions. */
066cd967 17651 *total = optimize_size ? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (2);
3c50106f
RH		 17652 return true;
17653
30a555d9
DE		 17654 case LABEL_REF:
17655 *total = 0;
17656 return true;
17657
3c50106f 17658 case PLUS:
f0517163 17659 if (mode == DFmode)
066cd967
DE		 17660 {
17661 if (GET_CODE (XEXP (x, 0)) == MULT)
17662 {
17663 /* FNMA accounted in outer NEG. */
17664 if (outer_code == NEG)
17665 *total = rs6000_cost->dmul - rs6000_cost->fp;
17666 else
17667 *total = rs6000_cost->dmul;
17668 }
17669 else
17670 *total = rs6000_cost->fp;
17671 }
f0517163 17672 else if (mode == SFmode)
066cd967
DE		 17673 {
17674 /* FNMA accounted in outer NEG. */
17675 if (outer_code == NEG && GET_CODE (XEXP (x, 0)) == MULT)
17676 *total = 0;
17677 else
17678 *total = rs6000_cost->fp;
17679 }
938bf747
RS		 17680 else if (GET_CODE (XEXP (x, 0)) == MULT)
17681 {
17682 /* The rs6000 doesn't have shift-and-add instructions. */
17683 rs6000_rtx_costs (XEXP (x, 0), MULT, PLUS, total);
17684 *total += COSTS_N_INSNS (1);
17685 }
f0517163 17686 else
066cd967
DE		 17687 *total = COSTS_N_INSNS (1);
17688 return false;
3c50106f 17689
52190329 17690 case MINUS:
f0517163 17691 if (mode == DFmode)
066cd967
DE		 17692 {
17693 if (GET_CODE (XEXP (x, 0)) == MULT)
17694 {
17695 /* FNMA accounted in outer NEG. */
17696 if (outer_code == NEG)
17697 *total = 0;
17698 else
17699 *total = rs6000_cost->dmul;
17700 }
17701 else
17702 *total = rs6000_cost->fp;
17703 }
f0517163 17704 else if (mode == SFmode)
066cd967
DE		 17705 {
17706 /* FNMA accounted in outer NEG. */
17707 if (outer_code == NEG && GET_CODE (XEXP (x, 0)) == MULT)
17708 *total = 0;
17709 else
17710 *total = rs6000_cost->fp;
17711 }
938bf747
RS		 17712 else if (GET_CODE (XEXP (x, 0)) == MULT)
17713 {
17714 /* The rs6000 doesn't have shift-and-sub instructions. */
17715 rs6000_rtx_costs (XEXP (x, 0), MULT, MINUS, total);
17716 *total += COSTS_N_INSNS (1);
17717 }
f0517163 17718 else
c4ad648e 17719 *total = COSTS_N_INSNS (1);
066cd967 17720 return false;
3c50106f
RH		 17721
17722 case MULT:
c9dbf840
DE		 17723 if (GET_CODE (XEXP (x, 1)) == CONST_INT
17724 && CONST_OK_FOR_LETTER_P (INTVAL (XEXP (x, 1)), 'I'))
3c50106f 17725 {
8b897cfa
RS		 17726 if (INTVAL (XEXP (x, 1)) >= -256
17727 && INTVAL (XEXP (x, 1)) <= 255)
06a67bdd 17728 *total = rs6000_cost->mulsi_const9;
8b897cfa 17729 else
06a67bdd 17730 *total = rs6000_cost->mulsi_const;
3c50106f 17731 }
066cd967
DE		 17732 /* FMA accounted in outer PLUS/MINUS. */
17733 else if ((mode == DFmode || mode == SFmode)
17734 && (outer_code == PLUS || outer_code == MINUS))
17735 *total = 0;
f0517163 17736 else if (mode == DFmode)
06a67bdd 17737 *total = rs6000_cost->dmul;
f0517163 17738 else if (mode == SFmode)
06a67bdd 17739 *total = rs6000_cost->fp;
f0517163 17740 else if (mode == DImode)
06a67bdd 17741 *total = rs6000_cost->muldi;
8b897cfa 17742 else
06a67bdd 17743 *total = rs6000_cost->mulsi;
066cd967 17744 return false;
3c50106f
RH		 17745
17746 case DIV:
17747 case MOD:
f0517163
RS		 17748 if (FLOAT_MODE_P (mode))
17749 {
06a67bdd
RS		 17750 *total = mode == DFmode ? rs6000_cost->ddiv
17751 : rs6000_cost->sdiv;
066cd967 17752 return false;
f0517163 17753 }
5efb1046 17754 /* FALLTHRU */
3c50106f
RH		 17755
17756 case UDIV:
17757 case UMOD:
627b6fe2
DJ		 17758 if (GET_CODE (XEXP (x, 1)) == CONST_INT
17759 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0)
17760 {
17761 if (code == DIV || code == MOD)
17762 /* Shift, addze */
17763 *total = COSTS_N_INSNS (2);
17764 else
17765 /* Shift */
17766 *total = COSTS_N_INSNS (1);
17767 }
c4ad648e 17768 else
627b6fe2
DJ		 17769 {
17770 if (GET_MODE (XEXP (x, 1)) == DImode)
17771 *total = rs6000_cost->divdi;
17772 else
17773 *total = rs6000_cost->divsi;
17774 }
17775 /* Add in shift and subtract for MOD. */
17776 if (code == MOD || code == UMOD)
17777 *total += COSTS_N_INSNS (2);
066cd967 17778 return false;
3c50106f
RH		 17779
17780 case FFS:
17781 *total = COSTS_N_INSNS (4);
066cd967 17782 return false;
3c50106f 17783
06a67bdd 17784 case NOT:
066cd967
DE		 17785 if (outer_code == AND || outer_code == IOR || outer_code == XOR)
17786 {
17787 *total = 0;
17788 return false;
17789 }
17790 /* FALLTHRU */
17791
17792 case AND:
17793 case IOR:
17794 case XOR:
d5861a7a
DE		 17795 case ZERO_EXTRACT:
17796 *total = COSTS_N_INSNS (1);
17797 return false;
17798
066cd967
DE		 17799 case ASHIFT:
17800 case ASHIFTRT:
17801 case LSHIFTRT:
17802 case ROTATE:
17803 case ROTATERT:
d5861a7a 17804 /* Handle mul_highpart. */
066cd967
DE		 17805 if (outer_code == TRUNCATE
17806 && GET_CODE (XEXP (x, 0)) == MULT)
17807 {
17808 if (mode == DImode)
17809 *total = rs6000_cost->muldi;
17810 else
17811 *total = rs6000_cost->mulsi;
17812 return true;
17813 }
d5861a7a
DE		 17814 else if (outer_code == AND)
17815 *total = 0;
17816 else
17817 *total = COSTS_N_INSNS (1);
17818 return false;
17819
17820 case SIGN_EXTEND:
17821 case ZERO_EXTEND:
17822 if (GET_CODE (XEXP (x, 0)) == MEM)
17823 *total = 0;
17824 else
17825 *total = COSTS_N_INSNS (1);
066cd967 17826 return false;
06a67bdd 17827
066cd967
DE		 17828 case COMPARE:
17829 case NEG:
17830 case ABS:
17831 if (!FLOAT_MODE_P (mode))
17832 {
17833 *total = COSTS_N_INSNS (1);
17834 return false;
17835 }
17836 /* FALLTHRU */
17837
17838 case FLOAT:
17839 case UNSIGNED_FLOAT:
17840 case FIX:
17841 case UNSIGNED_FIX:
17842 case FLOAT_EXTEND:
06a67bdd
RS		 17843 case FLOAT_TRUNCATE:
17844 *total = rs6000_cost->fp;
066cd967 17845 return false;
06a67bdd
RS		 17846
17847 case UNSPEC:
17848 switch (XINT (x, 1))
17849 {
17850 case UNSPEC_FRSP:
17851 *total = rs6000_cost->fp;
17852 return true;
17853
17854 default:
17855 break;
17856 }
17857 break;
17858
17859 case CALL:
17860 case IF_THEN_ELSE:
17861 if (optimize_size)
17862 {
17863 *total = COSTS_N_INSNS (1);
17864 return true;
17865 }
066cd967
DE		 17866 else if (FLOAT_MODE_P (mode)
17867 && TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS)
17868 {
17869 *total = rs6000_cost->fp;
17870 return false;
17871 }
06a67bdd
RS		 17872 break;
17873
c0600ecd
DE		 17874 case EQ:
17875 case GTU:
17876 case LTU:
22e54023
DE		 17877 /* Carry bit requires mode == Pmode.
17878 NEG or PLUS already counted so only add one. */
17879 if (mode == Pmode
17880 && (outer_code == NEG || outer_code == PLUS))
c0600ecd 17881 {
22e54023
DE		 17882 *total = COSTS_N_INSNS (1);
17883 return true;
17884 }
17885 if (outer_code == SET)
17886 {
17887 if (XEXP (x, 1) == const0_rtx)
c0600ecd 17888 {
22e54023 17889 *total = COSTS_N_INSNS (2);
c0600ecd 17890 return true;
c0600ecd 17891 }
22e54023
DE		 17892 else if (mode == Pmode)
17893 {
17894 *total = COSTS_N_INSNS (3);
17895 return false;
17896 }
17897 }
17898 /* FALLTHRU */
17899
17900 case GT:
17901 case LT:
17902 case UNORDERED:
17903 if (outer_code == SET && (XEXP (x, 1) == const0_rtx))
17904 {
17905 *total = COSTS_N_INSNS (2);
17906 return true;
c0600ecd 17907 }
22e54023
DE		 17908 /* CC COMPARE. */
17909 if (outer_code == COMPARE)
17910 {
17911 *total = 0;
17912 return true;
17913 }
17914 break;
c0600ecd 17915
3c50106f 17916 default:
06a67bdd 17917 break;
3c50106f 17918 }
06a67bdd
RS		 17919
17920 return false;
3c50106f
RH		 17921}
17922
34bb030a
DE		 17923/* A C expression returning the cost of moving data from a register of class
17924 CLASS1 to one of CLASS2. */
17925
17926int
f676971a 17927rs6000_register_move_cost (enum machine_mode mode,
a2369ed3 17928 enum reg_class from, enum reg_class to)
34bb030a
DE		 17929{
17930 /* Moves from/to GENERAL_REGS. */
17931 if (reg_classes_intersect_p (to, GENERAL_REGS)
17932 || reg_classes_intersect_p (from, GENERAL_REGS))
17933 {
17934 if (! reg_classes_intersect_p (to, GENERAL_REGS))
17935 from = to;
17936
17937 if (from == FLOAT_REGS || from == ALTIVEC_REGS)
17938 return (rs6000_memory_move_cost (mode, from, 0)
17939 + rs6000_memory_move_cost (mode, GENERAL_REGS, 0));
17940
c4ad648e
AM		 17941 /* It's more expensive to move CR_REGS than CR0_REGS because of the
17942 shift. */
34bb030a
DE		 17943 else if (from == CR_REGS)
17944 return 4;
17945
17946 else
c4ad648e 17947 /* A move will cost one instruction per GPR moved. */
c8b622ff 17948 return 2 * hard_regno_nregs[0][mode];
34bb030a
DE		 17949 }
17950
c4ad648e 17951 /* Moving between two similar registers is just one instruction. */
34bb030a
DE		 17952 else if (reg_classes_intersect_p (to, from))
17953 return mode == TFmode ? 4 : 2;
17954
c4ad648e 17955 /* Everything else has to go through GENERAL_REGS. */
34bb030a 17956 else
f676971a 17957 return (rs6000_register_move_cost (mode, GENERAL_REGS, to)
34bb030a
DE		 17958 + rs6000_register_move_cost (mode, from, GENERAL_REGS));
17959}
17960
17961/* A C expressions returning the cost of moving data of MODE from a register to
17962 or from memory. */
17963
17964int
f676971a 17965rs6000_memory_move_cost (enum machine_mode mode, enum reg_class class,
a2369ed3 17966 int in ATTRIBUTE_UNUSED)
34bb030a
DE		 17967{
17968 if (reg_classes_intersect_p (class, GENERAL_REGS))
c8b622ff 17969 return 4 * hard_regno_nregs[0][mode];
34bb030a 17970 else if (reg_classes_intersect_p (class, FLOAT_REGS))
c8b622ff 17971 return 4 * hard_regno_nregs[32][mode];
34bb030a 17972 else if (reg_classes_intersect_p (class, ALTIVEC_REGS))
c8b622ff 17973 return 4 * hard_regno_nregs[FIRST_ALTIVEC_REGNO][mode];
34bb030a
DE		 17974 else
17975 return 4 + rs6000_register_move_cost (mode, class, GENERAL_REGS);
17976}
17977
ef765ea9
DE		 17978/* Newton-Raphson approximation of single-precision floating point divide n/d.
17979 Assumes no trapping math and finite arguments. */
17980
17981void
17982rs6000_emit_swdivsf (rtx res, rtx n, rtx d)
17983{
17984 rtx x0, e0, e1, y1, u0, v0, one;
17985
17986 x0 = gen_reg_rtx (SFmode);
17987 e0 = gen_reg_rtx (SFmode);
17988 e1 = gen_reg_rtx (SFmode);
17989 y1 = gen_reg_rtx (SFmode);
17990 u0 = gen_reg_rtx (SFmode);
17991 v0 = gen_reg_rtx (SFmode);
17992 one = force_reg (SFmode, CONST_DOUBLE_FROM_REAL_VALUE (dconst1, SFmode));
17993
17994 /* x0 = 1./d estimate */
17995 emit_insn (gen_rtx_SET (VOIDmode, x0,
17996 gen_rtx_UNSPEC (SFmode, gen_rtvec (1, d),
17997 UNSPEC_FRES)));
17998 /* e0 = 1. - d * x0 */
17999 emit_insn (gen_rtx_SET (VOIDmode, e0,
18000 gen_rtx_MINUS (SFmode, one,
18001 gen_rtx_MULT (SFmode, d, x0))));
18002 /* e1 = e0 + e0 * e0 */
18003 emit_insn (gen_rtx_SET (VOIDmode, e1,
18004 gen_rtx_PLUS (SFmode,
18005 gen_rtx_MULT (SFmode, e0, e0), e0)));
18006 /* y1 = x0 + e1 * x0 */
18007 emit_insn (gen_rtx_SET (VOIDmode, y1,
18008 gen_rtx_PLUS (SFmode,
18009 gen_rtx_MULT (SFmode, e1, x0), x0)));
18010 /* u0 = n * y1 */
18011 emit_insn (gen_rtx_SET (VOIDmode, u0,
18012 gen_rtx_MULT (SFmode, n, y1)));
18013 /* v0 = n - d * u0 */
18014 emit_insn (gen_rtx_SET (VOIDmode, v0,
18015 gen_rtx_MINUS (SFmode, n,
18016 gen_rtx_MULT (SFmode, d, u0))));
18017 /* res = u0 + v0 * y1 */
18018 emit_insn (gen_rtx_SET (VOIDmode, res,
18019 gen_rtx_PLUS (SFmode,
18020 gen_rtx_MULT (SFmode, v0, y1), u0)));
18021}
18022
18023/* Newton-Raphson approximation of double-precision floating point divide n/d.
18024 Assumes no trapping math and finite arguments. */
18025
18026void
18027rs6000_emit_swdivdf (rtx res, rtx n, rtx d)
18028{
18029 rtx x0, e0, e1, e2, y1, y2, y3, u0, v0, one;
18030
18031 x0 = gen_reg_rtx (DFmode);
18032 e0 = gen_reg_rtx (DFmode);
18033 e1 = gen_reg_rtx (DFmode);
18034 e2 = gen_reg_rtx (DFmode);
18035 y1 = gen_reg_rtx (DFmode);
18036 y2 = gen_reg_rtx (DFmode);
18037 y3 = gen_reg_rtx (DFmode);
18038 u0 = gen_reg_rtx (DFmode);
18039 v0 = gen_reg_rtx (DFmode);
18040 one = force_reg (DFmode, CONST_DOUBLE_FROM_REAL_VALUE (dconst1, DFmode));
18041
18042 /* x0 = 1./d estimate */
18043 emit_insn (gen_rtx_SET (VOIDmode, x0,
18044 gen_rtx_UNSPEC (DFmode, gen_rtvec (1, d),
18045 UNSPEC_FRES)));
18046 /* e0 = 1. - d * x0 */
18047 emit_insn (gen_rtx_SET (VOIDmode, e0,
18048 gen_rtx_MINUS (DFmode, one,
18049 gen_rtx_MULT (SFmode, d, x0))));
18050 /* y1 = x0 + e0 * x0 */
18051 emit_insn (gen_rtx_SET (VOIDmode, y1,
18052 gen_rtx_PLUS (DFmode,
18053 gen_rtx_MULT (DFmode, e0, x0), x0)));
18054 /* e1 = e0 * e0 */
18055 emit_insn (gen_rtx_SET (VOIDmode, e1,
18056 gen_rtx_MULT (DFmode, e0, e0)));
18057 /* y2 = y1 + e1 * y1 */
18058 emit_insn (gen_rtx_SET (VOIDmode, y2,
18059 gen_rtx_PLUS (DFmode,
18060 gen_rtx_MULT (DFmode, e1, y1), y1)));
18061 /* e2 = e1 * e1 */
18062 emit_insn (gen_rtx_SET (VOIDmode, e2,
18063 gen_rtx_MULT (DFmode, e1, e1)));
18064 /* y3 = y2 + e2 * y2 */
18065 emit_insn (gen_rtx_SET (VOIDmode, y3,
18066 gen_rtx_PLUS (DFmode,
18067 gen_rtx_MULT (DFmode, e2, y2), y2)));
18068 /* u0 = n * y3 */
18069 emit_insn (gen_rtx_SET (VOIDmode, u0,
18070 gen_rtx_MULT (DFmode, n, y3)));
18071 /* v0 = n - d * u0 */
18072 emit_insn (gen_rtx_SET (VOIDmode, v0,
18073 gen_rtx_MINUS (DFmode, n,
18074 gen_rtx_MULT (DFmode, d, u0))));
18075 /* res = u0 + v0 * y3 */
18076 emit_insn (gen_rtx_SET (VOIDmode, res,
18077 gen_rtx_PLUS (DFmode,
18078 gen_rtx_MULT (DFmode, v0, y3), u0)));
18079}
18080
ded9bf77
AH		 18081/* Return an RTX representing where to find the function value of a
18082 function returning MODE. */
18083static rtx
18084rs6000_complex_function_value (enum machine_mode mode)
18085{
18086 unsigned int regno;
18087 rtx r1, r2;
18088 enum machine_mode inner = GET_MODE_INNER (mode);
fb7e4164 18089 unsigned int inner_bytes = GET_MODE_SIZE (inner);
ded9bf77 18090
18f63bfa
AH		 18091 if (FLOAT_MODE_P (mode) && TARGET_HARD_FLOAT && TARGET_FPRS)
18092 regno = FP_ARG_RETURN;
354ed18f
AH		 18093 else
18094 {
18f63bfa 18095 regno = GP_ARG_RETURN;
ded9bf77 18096
18f63bfa
AH		 18097 /* 32-bit is OK since it'll go in r3/r4. */
18098 if (TARGET_32BIT && inner_bytes >= 4)
ded9bf77
AH		 18099 return gen_rtx_REG (mode, regno);
18100 }
18101
18f63bfa
AH		 18102 if (inner_bytes >= 8)
18103 return gen_rtx_REG (mode, regno);
18104
ded9bf77
AH		 18105 r1 = gen_rtx_EXPR_LIST (inner, gen_rtx_REG (inner, regno),
18106 const0_rtx);
18107 r2 = gen_rtx_EXPR_LIST (inner, gen_rtx_REG (inner, regno + 1),
fb7e4164 18108 GEN_INT (inner_bytes));
ded9bf77
AH		 18109 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r2));
18110}
18111
a6ebc39a
AH		 18112/* Define how to find the value returned by a function.
18113 VALTYPE is the data type of the value (as a tree).
18114 If the precise function being called is known, FUNC is its FUNCTION_DECL;
18115 otherwise, FUNC is 0.
18116
18117 On the SPE, both FPs and vectors are returned in r3.
18118
18119 On RS/6000 an integer value is in r3 and a floating-point value is in
18120 fp1, unless -msoft-float. */
18121
18122rtx
18123rs6000_function_value (tree valtype, tree func ATTRIBUTE_UNUSED)
18124{
18125 enum machine_mode mode;
2a8fa26c 18126 unsigned int regno;
a6ebc39a 18127
594a51fe
SS		 18128 /* Special handling for structs in darwin64. */
18129 if (rs6000_darwin64_abi
18130 && TYPE_MODE (valtype) == BLKmode
0b5383eb
DJ		 18131 && TREE_CODE (valtype) == RECORD_TYPE
18132 && int_size_in_bytes (valtype) > 0)
594a51fe
SS		 18133 {
18134 CUMULATIVE_ARGS valcum;
18135 rtx valret;
18136
0b5383eb 18137 valcum.words = 0;
594a51fe
SS		 18138 valcum.fregno = FP_ARG_MIN_REG;
18139 valcum.vregno = ALTIVEC_ARG_MIN_REG;
0b5383eb
DJ		 18140 /* Do a trial code generation as if this were going to be passed as
18141 an argument; if any part goes in memory, we return NULL. */
18142 valret = rs6000_darwin64_record_arg (&valcum, valtype, 1, true);
594a51fe
SS		 18143 if (valret)
18144 return valret;
18145 /* Otherwise fall through to standard ABI rules. */
18146 }
18147
0e67400a
FJ		 18148 if (TARGET_32BIT && TARGET_POWERPC64 && TYPE_MODE (valtype) == DImode)
18149 {
18150 /* Long long return value need be split in -mpowerpc64, 32bit ABI. */
18151 return gen_rtx_PARALLEL (DImode,
18152 gen_rtvec (2,
18153 gen_rtx_EXPR_LIST (VOIDmode,
18154 gen_rtx_REG (SImode, GP_ARG_RETURN),
18155 const0_rtx),
18156 gen_rtx_EXPR_LIST (VOIDmode,
18157 gen_rtx_REG (SImode,
18158 GP_ARG_RETURN + 1),
18159 GEN_INT (4))));
18160 }
18161
a6ebc39a
AH		 18162 if ((INTEGRAL_TYPE_P (valtype)
18163 && TYPE_PRECISION (valtype) < BITS_PER_WORD)
18164 || POINTER_TYPE_P (valtype))
b78d48dd 18165 mode = TARGET_32BIT ? SImode : DImode;
a6ebc39a
AH		 18166 else
18167 mode = TYPE_MODE (valtype);
18168
4ed78545 18169 if (SCALAR_FLOAT_TYPE_P (valtype) && TARGET_HARD_FLOAT && TARGET_FPRS)
2a8fa26c 18170 regno = FP_ARG_RETURN;
ded9bf77 18171 else if (TREE_CODE (valtype) == COMPLEX_TYPE
42ba5130 18172 && targetm.calls.split_complex_arg)
ded9bf77 18173 return rs6000_complex_function_value (mode);
44688022 18174 else if (TREE_CODE (valtype) == VECTOR_TYPE
d0b2079e 18175 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI
23ba09f0 18176 && ALTIVEC_VECTOR_MODE (mode))
a6ebc39a 18177 regno = ALTIVEC_ARG_RETURN;
18f63bfa
AH		 18178 else if (TARGET_E500_DOUBLE && TARGET_HARD_FLOAT
18179 && (mode == DFmode || mode == DCmode))
18180 return spe_build_register_parallel (mode, GP_ARG_RETURN);
a6ebc39a
AH		 18181 else
18182 regno = GP_ARG_RETURN;
18183
18184 return gen_rtx_REG (mode, regno);
18185}
18186
ded9bf77
AH		 18187/* Define how to find the value returned by a library function
18188 assuming the value has mode MODE. */
18189rtx
18190rs6000_libcall_value (enum machine_mode mode)
18191{
18192 unsigned int regno;
18193
2e6c9641
FJ		 18194 if (TARGET_32BIT && TARGET_POWERPC64 && mode == DImode)
18195 {
18196 /* Long long return value need be split in -mpowerpc64, 32bit ABI. */
18197 return gen_rtx_PARALLEL (DImode,
18198 gen_rtvec (2,
18199 gen_rtx_EXPR_LIST (VOIDmode,
18200 gen_rtx_REG (SImode, GP_ARG_RETURN),
18201 const0_rtx),
18202 gen_rtx_EXPR_LIST (VOIDmode,
18203 gen_rtx_REG (SImode,
18204 GP_ARG_RETURN + 1),
18205 GEN_INT (4))));
18206 }
18207
ded9bf77
AH		 18208 if (GET_MODE_CLASS (mode) == MODE_FLOAT
18209 && TARGET_HARD_FLOAT && TARGET_FPRS)
18210 regno = FP_ARG_RETURN;
44688022
AM		 18211 else if (ALTIVEC_VECTOR_MODE (mode)
18212 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI)
ded9bf77 18213 regno = ALTIVEC_ARG_RETURN;
42ba5130 18214 else if (COMPLEX_MODE_P (mode) && targetm.calls.split_complex_arg)
ded9bf77 18215 return rs6000_complex_function_value (mode);
18f63bfa
AH		 18216 else if (TARGET_E500_DOUBLE && TARGET_HARD_FLOAT
18217 && (mode == DFmode || mode == DCmode))
18218 return spe_build_register_parallel (mode, GP_ARG_RETURN);
ded9bf77
AH		 18219 else
18220 regno = GP_ARG_RETURN;
18221
18222 return gen_rtx_REG (mode, regno);
18223}
18224
d1d0c603
JJ		 18225/* Define the offset between two registers, FROM to be eliminated and its
18226 replacement TO, at the start of a routine. */
18227HOST_WIDE_INT
18228rs6000_initial_elimination_offset (int from, int to)
18229{
18230 rs6000_stack_t *info = rs6000_stack_info ();
18231 HOST_WIDE_INT offset;
18232
18233 if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
18234 offset = info->push_p ? 0 : -info->total_size;
18235 else if (from == ARG_POINTER_REGNUM && to == FRAME_POINTER_REGNUM)
18236 offset = info->total_size;
18237 else if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
18238 offset = info->push_p ? info->total_size : 0;
18239 else if (from == RS6000_PIC_OFFSET_TABLE_REGNUM)
18240 offset = 0;
18241 else
37409796 18242 gcc_unreachable ();
d1d0c603
JJ		 18243
18244 return offset;
18245}
18246
58646b77 18247/* Return true if TYPE is a SPE or AltiVec opaque type. */
62e1dfcf 18248
c8e4f0e9 18249static bool
58646b77 18250rs6000_is_opaque_type (tree type)
62e1dfcf 18251{
58646b77 18252 return (type == opaque_V2SI_type_node
2abe3e28 18253 || type == opaque_V2SF_type_node
58646b77
PB		 18254 || type == opaque_p_V2SI_type_node
18255 || type == opaque_V4SI_type_node);
62e1dfcf
NC		 18256}
18257
96714395 18258static rtx
a2369ed3 18259rs6000_dwarf_register_span (rtx reg)
96714395
AH		 18260{
18261 unsigned regno;
18262
4d4cbc0e
AH		 18263 if (TARGET_SPE
18264 && (SPE_VECTOR_MODE (GET_MODE (reg))
18265 || (TARGET_E500_DOUBLE && GET_MODE (reg) == DFmode)))
18266 ;
18267 else
96714395
AH		 18268 return NULL_RTX;
18269
18270 regno = REGNO (reg);
18271
18272 /* The duality of the SPE register size wreaks all kinds of havoc.
18273 This is a way of distinguishing r0 in 32-bits from r0 in
18274 64-bits. */
18275 return
18276 gen_rtx_PARALLEL (VOIDmode,
3bd104d1
AH		 18277 BYTES_BIG_ENDIAN
18278 ? gen_rtvec (2,
18279 gen_rtx_REG (SImode, regno + 1200),
18280 gen_rtx_REG (SImode, regno))
18281 : gen_rtvec (2,
18282 gen_rtx_REG (SImode, regno),
18283 gen_rtx_REG (SImode, regno + 1200)));
96714395
AH		 18284}
18285
93c9d1ba
AM		 18286/* Map internal gcc register numbers to DWARF2 register numbers. */
18287
18288unsigned int
18289rs6000_dbx_register_number (unsigned int regno)
18290{
18291 if (regno <= 63 || write_symbols != DWARF2_DEBUG)
18292 return regno;
18293 if (regno == MQ_REGNO)
18294 return 100;
18295 if (regno == LINK_REGISTER_REGNUM)
18296 return 108;
18297 if (regno == COUNT_REGISTER_REGNUM)
18298 return 109;
18299 if (CR_REGNO_P (regno))
18300 return regno - CR0_REGNO + 86;
18301 if (regno == XER_REGNO)
18302 return 101;
18303 if (ALTIVEC_REGNO_P (regno))
18304 return regno - FIRST_ALTIVEC_REGNO + 1124;
18305 if (regno == VRSAVE_REGNO)
18306 return 356;
18307 if (regno == VSCR_REGNO)
18308 return 67;
18309 if (regno == SPE_ACC_REGNO)
18310 return 99;
18311 if (regno == SPEFSCR_REGNO)
18312 return 612;
18313 /* SPE high reg number. We get these values of regno from
18314 rs6000_dwarf_register_span. */
37409796
NS		 18315 gcc_assert (regno >= 1200 && regno < 1232);
18316 return regno;
93c9d1ba
AM		 18317}
18318
93f90be6 18319/* target hook eh_return_filter_mode */
f676971a 18320static enum machine_mode
93f90be6
FJ		 18321rs6000_eh_return_filter_mode (void)
18322{
18323 return TARGET_32BIT ? SImode : word_mode;
18324}
18325
f676971a
EC		 18326/* Target hook for vector_mode_supported_p. */
18327static bool
18328rs6000_vector_mode_supported_p (enum machine_mode mode)
18329{
18330
18331 if (TARGET_SPE && SPE_VECTOR_MODE (mode))
18332 return true;
18333
18334 else if (TARGET_ALTIVEC && ALTIVEC_VECTOR_MODE (mode))
18335 return true;
18336
18337 else
18338 return false;
18339}
18340
4d3e6fae
FJ		 18341/* Target hook for invalid_arg_for_unprototyped_fn. */
18342static const char *
18343invalid_arg_for_unprototyped_fn (tree typelist, tree funcdecl, tree val)
18344{
18345 return (!rs6000_darwin64_abi
18346 && typelist == 0
18347 && TREE_CODE (TREE_TYPE (val)) == VECTOR_TYPE
18348 && (funcdecl == NULL_TREE
18349 || (TREE_CODE (funcdecl) == FUNCTION_DECL
18350 && DECL_BUILT_IN_CLASS (funcdecl) != BUILT_IN_MD)))
18351 ? N_("AltiVec argument passed to unprototyped function")
18352 : NULL;
18353}
18354
17211ab5 18355#include "gt-rs6000.h"
Mirror of https://gcc.gnu.org/git/gcc.git