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Commit | Line | Data |
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9878760c | 1 | /* Subroutines used for code generation on IBM RS/6000. |
f676971a | 2 | Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, |
5b86a469 | 3 | 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc. |
fab3bcc3 | 4 | Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu) |
9878760c | 5 | |
5de601cf | 6 | This file is part of GCC. |
9878760c | 7 | |
5de601cf NC |
8 | GCC is free software; you can redistribute it and/or modify it |
9 | under the terms of the GNU General Public License as published | |
10 | by the Free Software Foundation; either version 2, or (at your | |
11 | option) any later version. | |
9878760c | 12 | |
5de601cf NC |
13 | GCC is distributed in the hope that it will be useful, but WITHOUT |
14 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
15 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
16 | License for more details. | |
9878760c | 17 | |
5de601cf NC |
18 | You should have received a copy of the GNU General Public License |
19 | along with GCC; see the file COPYING. If not, write to the | |
20 | Free Software Foundation, 59 Temple Place - Suite 330, Boston, | |
21 | MA 02111-1307, USA. */ | |
9878760c | 22 | |
956d6950 | 23 | #include "config.h" |
c4d38ccb | 24 | #include "system.h" |
4977bab6 ZW |
25 | #include "coretypes.h" |
26 | #include "tm.h" | |
9878760c RK |
27 | #include "rtl.h" |
28 | #include "regs.h" | |
29 | #include "hard-reg-set.h" | |
30 | #include "real.h" | |
31 | #include "insn-config.h" | |
32 | #include "conditions.h" | |
9878760c RK |
33 | #include "insn-attr.h" |
34 | #include "flags.h" | |
35 | #include "recog.h" | |
9878760c | 36 | #include "obstack.h" |
9b30bae2 | 37 | #include "tree.h" |
dfafc897 | 38 | #include "expr.h" |
2fc1c679 | 39 | #include "optabs.h" |
2a430ec1 | 40 | #include "except.h" |
a7df97e6 | 41 | #include "function.h" |
296b8152 | 42 | #include "output.h" |
d5fa86ba | 43 | #include "basic-block.h" |
d0101753 | 44 | #include "integrate.h" |
296b8152 | 45 | #include "toplev.h" |
c8023011 | 46 | #include "ggc.h" |
9ebbca7d GK |
47 | #include "hashtab.h" |
48 | #include "tm_p.h" | |
672a6f42 NB |
49 | #include "target.h" |
50 | #include "target-def.h" | |
3ac88239 | 51 | #include "langhooks.h" |
24ea750e | 52 | #include "reload.h" |
117dca74 | 53 | #include "cfglayout.h" |
79ae11c4 | 54 | #include "sched-int.h" |
cd3ce9b4 | 55 | #include "tree-gimple.h" |
4d3e6fae | 56 | #include "intl.h" |
1bc7c5b6 ZW |
57 | #if TARGET_XCOFF |
58 | #include "xcoffout.h" /* get declarations of xcoff_*_section_name */ | |
59 | #endif | |
93a27b7b ZW |
60 | #if TARGET_MACHO |
61 | #include "gstab.h" /* for N_SLINE */ | |
62 | #endif | |
9b30bae2 | 63 | |
7509c759 MM |
64 | #ifndef TARGET_NO_PROTOTYPE |
65 | #define TARGET_NO_PROTOTYPE 0 | |
66 | #endif | |
67 | ||
9878760c RK |
68 | #define min(A,B) ((A) < (B) ? (A) : (B)) |
69 | #define max(A,B) ((A) > (B) ? (A) : (B)) | |
70 | ||
d1d0c603 JJ |
71 | /* Structure used to define the rs6000 stack */ |
72 | typedef struct rs6000_stack { | |
73 | int first_gp_reg_save; /* first callee saved GP register used */ | |
74 | int first_fp_reg_save; /* first callee saved FP register used */ | |
75 | int first_altivec_reg_save; /* first callee saved AltiVec register used */ | |
76 | int lr_save_p; /* true if the link reg needs to be saved */ | |
77 | int cr_save_p; /* true if the CR reg needs to be saved */ | |
78 | unsigned int vrsave_mask; /* mask of vec registers to save */ | |
79 | int toc_save_p; /* true if the TOC needs to be saved */ | |
80 | int push_p; /* true if we need to allocate stack space */ | |
81 | int calls_p; /* true if the function makes any calls */ | |
c4ad648e | 82 | int world_save_p; /* true if we're saving *everything*: |
d62294f5 | 83 | r13-r31, cr, f14-f31, vrsave, v20-v31 */ |
d1d0c603 JJ |
84 | enum rs6000_abi abi; /* which ABI to use */ |
85 | int gp_save_offset; /* offset to save GP regs from initial SP */ | |
86 | int fp_save_offset; /* offset to save FP regs from initial SP */ | |
87 | int altivec_save_offset; /* offset to save AltiVec regs from initial SP */ | |
88 | int lr_save_offset; /* offset to save LR from initial SP */ | |
89 | int cr_save_offset; /* offset to save CR from initial SP */ | |
90 | int vrsave_save_offset; /* offset to save VRSAVE from initial SP */ | |
91 | int spe_gp_save_offset; /* offset to save spe 64-bit gprs */ | |
92 | int toc_save_offset; /* offset to save the TOC pointer */ | |
93 | int varargs_save_offset; /* offset to save the varargs registers */ | |
94 | int ehrd_offset; /* offset to EH return data */ | |
95 | int reg_size; /* register size (4 or 8) */ | |
96 | int varargs_size; /* size to hold V.4 args passed in regs */ | |
97 | HOST_WIDE_INT vars_size; /* variable save area size */ | |
98 | int parm_size; /* outgoing parameter size */ | |
99 | int save_size; /* save area size */ | |
100 | int fixed_size; /* fixed size of stack frame */ | |
101 | int gp_size; /* size of saved GP registers */ | |
102 | int fp_size; /* size of saved FP registers */ | |
103 | int altivec_size; /* size of saved AltiVec registers */ | |
104 | int cr_size; /* size to hold CR if not in save_size */ | |
105 | int lr_size; /* size to hold LR if not in save_size */ | |
106 | int vrsave_size; /* size to hold VRSAVE if not in save_size */ | |
107 | int altivec_padding_size; /* size of altivec alignment padding if | |
108 | not in save_size */ | |
109 | int spe_gp_size; /* size of 64-bit GPR save size for SPE */ | |
110 | int spe_padding_size; | |
111 | int toc_size; /* size to hold TOC if not in save_size */ | |
112 | HOST_WIDE_INT total_size; /* total bytes allocated for stack */ | |
113 | int spe_64bit_regs_used; | |
114 | } rs6000_stack_t; | |
115 | ||
5248c961 RK |
116 | /* Target cpu type */ |
117 | ||
118 | enum processor_type rs6000_cpu; | |
8e3f41e7 MM |
119 | struct rs6000_cpu_select rs6000_select[3] = |
120 | { | |
815cdc52 MM |
121 | /* switch name, tune arch */ |
122 | { (const char *)0, "--with-cpu=", 1, 1 }, | |
123 | { (const char *)0, "-mcpu=", 1, 1 }, | |
124 | { (const char *)0, "-mtune=", 1, 0 }, | |
8e3f41e7 | 125 | }; |
5248c961 | 126 | |
ec507f2d DE |
127 | /* Always emit branch hint bits. */ |
128 | static GTY(()) bool rs6000_always_hint; | |
129 | ||
130 | /* Schedule instructions for group formation. */ | |
131 | static GTY(()) bool rs6000_sched_groups; | |
132 | ||
f676971a | 133 | /* Support adjust_priority scheduler hook |
79ae11c4 DN |
134 | and -mprioritize-restricted-insns= option. */ |
135 | const char *rs6000_sched_restricted_insns_priority_str; | |
136 | int rs6000_sched_restricted_insns_priority; | |
137 | ||
569fa502 DN |
138 | /* Support for -msched-costly-dep option. */ |
139 | const char *rs6000_sched_costly_dep_str; | |
140 | enum rs6000_dependence_cost rs6000_sched_costly_dep; | |
141 | ||
cbe26ab8 DN |
142 | /* Support for -minsert-sched-nops option. */ |
143 | const char *rs6000_sched_insert_nops_str; | |
144 | enum rs6000_nop_insertion rs6000_sched_insert_nops; | |
145 | ||
7ccf35ed | 146 | /* Support targetm.vectorize.builtin_mask_for_load. */ |
13c62176 | 147 | static GTY(()) tree altivec_builtin_mask_for_load; |
7ccf35ed | 148 | |
6fa3f289 ZW |
149 | /* Size of long double */ |
150 | const char *rs6000_long_double_size_string; | |
151 | int rs6000_long_double_type_size; | |
152 | ||
153 | /* Whether -mabi=altivec has appeared */ | |
154 | int rs6000_altivec_abi; | |
155 | ||
08b57fb3 AH |
156 | /* Whether VRSAVE instructions should be generated. */ |
157 | int rs6000_altivec_vrsave; | |
158 | ||
159 | /* String from -mvrsave= option. */ | |
160 | const char *rs6000_altivec_vrsave_string; | |
161 | ||
a3170dc6 AH |
162 | /* Nonzero if we want SPE ABI extensions. */ |
163 | int rs6000_spe_abi; | |
164 | ||
165 | /* Whether isel instructions should be generated. */ | |
166 | int rs6000_isel; | |
167 | ||
993f19a8 AH |
168 | /* Whether SPE simd instructions should be generated. */ |
169 | int rs6000_spe; | |
170 | ||
5da702b1 AH |
171 | /* Nonzero if floating point operations are done in the GPRs. */ |
172 | int rs6000_float_gprs = 0; | |
173 | ||
594a51fe SS |
174 | /* Nonzero if we want Darwin's struct-by-value-in-regs ABI. */ |
175 | int rs6000_darwin64_abi; | |
176 | ||
5da702b1 AH |
177 | /* String from -mfloat-gprs=. */ |
178 | const char *rs6000_float_gprs_string; | |
a3170dc6 AH |
179 | |
180 | /* String from -misel=. */ | |
181 | const char *rs6000_isel_string; | |
182 | ||
993f19a8 AH |
183 | /* String from -mspe=. */ |
184 | const char *rs6000_spe_string; | |
185 | ||
a0ab749a | 186 | /* Set to nonzero once AIX common-mode calls have been defined. */ |
bbfb86aa | 187 | static GTY(()) int common_mode_defined; |
c81bebd7 | 188 | |
9878760c RK |
189 | /* Save information from a "cmpxx" operation until the branch or scc is |
190 | emitted. */ | |
9878760c RK |
191 | rtx rs6000_compare_op0, rs6000_compare_op1; |
192 | int rs6000_compare_fp_p; | |
874a0744 | 193 | |
874a0744 MM |
194 | /* Label number of label created for -mrelocatable, to call to so we can |
195 | get the address of the GOT section */ | |
196 | int rs6000_pic_labelno; | |
c81bebd7 | 197 | |
b91da81f | 198 | #ifdef USING_ELFOS_H |
c81bebd7 | 199 | /* Which abi to adhere to */ |
9739c90c | 200 | const char *rs6000_abi_name; |
d9407988 MM |
201 | |
202 | /* Semantics of the small data area */ | |
203 | enum rs6000_sdata_type rs6000_sdata = SDATA_DATA; | |
204 | ||
205 | /* Which small data model to use */ | |
815cdc52 | 206 | const char *rs6000_sdata_name = (char *)0; |
9ebbca7d GK |
207 | |
208 | /* Counter for labels which are to be placed in .fixup. */ | |
209 | int fixuplabelno = 0; | |
874a0744 | 210 | #endif |
4697a36c | 211 | |
c4501e62 JJ |
212 | /* Bit size of immediate TLS offsets and string from which it is decoded. */ |
213 | int rs6000_tls_size = 32; | |
214 | const char *rs6000_tls_size_string; | |
215 | ||
b6c9286a MM |
216 | /* ABI enumeration available for subtarget to use. */ |
217 | enum rs6000_abi rs6000_current_abi; | |
218 | ||
0ac081f6 AH |
219 | /* ABI string from -mabi= option. */ |
220 | const char *rs6000_abi_string; | |
221 | ||
85b776df AM |
222 | /* Whether to use variant of AIX ABI for PowerPC64 Linux. */ |
223 | int dot_symbols; | |
224 | ||
38c1f2d7 | 225 | /* Debug flags */ |
815cdc52 | 226 | const char *rs6000_debug_name; |
38c1f2d7 MM |
227 | int rs6000_debug_stack; /* debug stack applications */ |
228 | int rs6000_debug_arg; /* debug argument handling */ | |
229 | ||
aabcd309 | 230 | /* Value is TRUE if register/mode pair is acceptable. */ |
0d1fbc8c AH |
231 | bool rs6000_hard_regno_mode_ok_p[NUM_MACHINE_MODES][FIRST_PSEUDO_REGISTER]; |
232 | ||
6035d635 | 233 | /* Opaque types. */ |
2abe3e28 | 234 | static GTY(()) tree opaque_V2SI_type_node; |
2abe3e28 | 235 | static GTY(()) tree opaque_V2SF_type_node; |
6035d635 | 236 | static GTY(()) tree opaque_p_V2SI_type_node; |
4a5eab38 PB |
237 | static GTY(()) tree V16QI_type_node; |
238 | static GTY(()) tree V2SI_type_node; | |
239 | static GTY(()) tree V2SF_type_node; | |
240 | static GTY(()) tree V4HI_type_node; | |
241 | static GTY(()) tree V4SI_type_node; | |
242 | static GTY(()) tree V4SF_type_node; | |
243 | static GTY(()) tree V8HI_type_node; | |
244 | static GTY(()) tree unsigned_V16QI_type_node; | |
245 | static GTY(()) tree unsigned_V8HI_type_node; | |
246 | static GTY(()) tree unsigned_V4SI_type_node; | |
8bb418a3 ZL |
247 | static GTY(()) tree bool_char_type_node; /* __bool char */ |
248 | static GTY(()) tree bool_short_type_node; /* __bool short */ | |
249 | static GTY(()) tree bool_int_type_node; /* __bool int */ | |
250 | static GTY(()) tree pixel_type_node; /* __pixel */ | |
251 | static GTY(()) tree bool_V16QI_type_node; /* __vector __bool char */ | |
252 | static GTY(()) tree bool_V8HI_type_node; /* __vector __bool short */ | |
253 | static GTY(()) tree bool_V4SI_type_node; /* __vector __bool int */ | |
254 | static GTY(()) tree pixel_V8HI_type_node; /* __vector __pixel */ | |
255 | ||
256 | int rs6000_warn_altivec_long = 1; /* On by default. */ | |
257 | const char *rs6000_warn_altivec_long_switch; | |
258 | ||
57ac7be9 AM |
259 | const char *rs6000_traceback_name; |
260 | static enum { | |
261 | traceback_default = 0, | |
262 | traceback_none, | |
263 | traceback_part, | |
264 | traceback_full | |
265 | } rs6000_traceback; | |
266 | ||
38c1f2d7 MM |
267 | /* Flag to say the TOC is initialized */ |
268 | int toc_initialized; | |
9ebbca7d | 269 | char toc_label_name[10]; |
38c1f2d7 | 270 | |
9ebbca7d | 271 | /* Alias set for saves and restores from the rs6000 stack. */ |
f103e34d | 272 | static GTY(()) int rs6000_sr_alias_set; |
c8023011 | 273 | |
a5c76ee6 ZW |
274 | /* Call distance, overridden by -mlongcall and #pragma longcall(1). |
275 | The only place that looks at this is rs6000_set_default_type_attributes; | |
276 | everywhere else should rely on the presence or absence of a longcall | |
3eb4e360 AM |
277 | attribute on the function declaration. Exception: init_cumulative_args |
278 | looks at it too, for libcalls. */ | |
a5c76ee6 ZW |
279 | int rs6000_default_long_calls; |
280 | const char *rs6000_longcall_switch; | |
281 | ||
a3c9585f KH |
282 | /* Control alignment for fields within structures. */ |
283 | /* String from -malign-XXXXX. */ | |
025d9908 KH |
284 | const char *rs6000_alignment_string; |
285 | int rs6000_alignment_flags; | |
286 | ||
a3170dc6 AH |
287 | struct builtin_description |
288 | { | |
289 | /* mask is not const because we're going to alter it below. This | |
290 | nonsense will go away when we rewrite the -march infrastructure | |
291 | to give us more target flag bits. */ | |
292 | unsigned int mask; | |
293 | const enum insn_code icode; | |
294 | const char *const name; | |
295 | const enum rs6000_builtins code; | |
296 | }; | |
8b897cfa RS |
297 | \f |
298 | /* Target cpu costs. */ | |
299 | ||
300 | struct processor_costs { | |
c4ad648e | 301 | const int mulsi; /* cost of SImode multiplication. */ |
8b897cfa RS |
302 | const int mulsi_const; /* cost of SImode multiplication by constant. */ |
303 | const int mulsi_const9; /* cost of SImode mult by short constant. */ | |
c4ad648e AM |
304 | const int muldi; /* cost of DImode multiplication. */ |
305 | const int divsi; /* cost of SImode division. */ | |
306 | const int divdi; /* cost of DImode division. */ | |
307 | const int fp; /* cost of simple SFmode and DFmode insns. */ | |
308 | const int dmul; /* cost of DFmode multiplication (and fmadd). */ | |
309 | const int sdiv; /* cost of SFmode division (fdivs). */ | |
310 | const int ddiv; /* cost of DFmode division (fdiv). */ | |
8b897cfa RS |
311 | }; |
312 | ||
313 | const struct processor_costs *rs6000_cost; | |
314 | ||
315 | /* Processor costs (relative to an add) */ | |
316 | ||
317 | /* Instruction size costs on 32bit processors. */ | |
318 | static const | |
319 | struct processor_costs size32_cost = { | |
06a67bdd RS |
320 | COSTS_N_INSNS (1), /* mulsi */ |
321 | COSTS_N_INSNS (1), /* mulsi_const */ | |
322 | COSTS_N_INSNS (1), /* mulsi_const9 */ | |
323 | COSTS_N_INSNS (1), /* muldi */ | |
324 | COSTS_N_INSNS (1), /* divsi */ | |
325 | COSTS_N_INSNS (1), /* divdi */ | |
326 | COSTS_N_INSNS (1), /* fp */ | |
327 | COSTS_N_INSNS (1), /* dmul */ | |
328 | COSTS_N_INSNS (1), /* sdiv */ | |
329 | COSTS_N_INSNS (1), /* ddiv */ | |
8b897cfa RS |
330 | }; |
331 | ||
332 | /* Instruction size costs on 64bit processors. */ | |
333 | static const | |
334 | struct processor_costs size64_cost = { | |
06a67bdd RS |
335 | COSTS_N_INSNS (1), /* mulsi */ |
336 | COSTS_N_INSNS (1), /* mulsi_const */ | |
337 | COSTS_N_INSNS (1), /* mulsi_const9 */ | |
338 | COSTS_N_INSNS (1), /* muldi */ | |
339 | COSTS_N_INSNS (1), /* divsi */ | |
340 | COSTS_N_INSNS (1), /* divdi */ | |
341 | COSTS_N_INSNS (1), /* fp */ | |
342 | COSTS_N_INSNS (1), /* dmul */ | |
343 | COSTS_N_INSNS (1), /* sdiv */ | |
344 | COSTS_N_INSNS (1), /* ddiv */ | |
8b897cfa RS |
345 | }; |
346 | ||
347 | /* Instruction costs on RIOS1 processors. */ | |
348 | static const | |
349 | struct processor_costs rios1_cost = { | |
06a67bdd RS |
350 | COSTS_N_INSNS (5), /* mulsi */ |
351 | COSTS_N_INSNS (4), /* mulsi_const */ | |
352 | COSTS_N_INSNS (3), /* mulsi_const9 */ | |
353 | COSTS_N_INSNS (5), /* muldi */ | |
354 | COSTS_N_INSNS (19), /* divsi */ | |
355 | COSTS_N_INSNS (19), /* divdi */ | |
356 | COSTS_N_INSNS (2), /* fp */ | |
357 | COSTS_N_INSNS (2), /* dmul */ | |
358 | COSTS_N_INSNS (19), /* sdiv */ | |
359 | COSTS_N_INSNS (19), /* ddiv */ | |
8b897cfa RS |
360 | }; |
361 | ||
362 | /* Instruction costs on RIOS2 processors. */ | |
363 | static const | |
364 | struct processor_costs rios2_cost = { | |
06a67bdd RS |
365 | COSTS_N_INSNS (2), /* mulsi */ |
366 | COSTS_N_INSNS (2), /* mulsi_const */ | |
367 | COSTS_N_INSNS (2), /* mulsi_const9 */ | |
368 | COSTS_N_INSNS (2), /* muldi */ | |
369 | COSTS_N_INSNS (13), /* divsi */ | |
370 | COSTS_N_INSNS (13), /* divdi */ | |
371 | COSTS_N_INSNS (2), /* fp */ | |
372 | COSTS_N_INSNS (2), /* dmul */ | |
373 | COSTS_N_INSNS (17), /* sdiv */ | |
374 | COSTS_N_INSNS (17), /* ddiv */ | |
8b897cfa RS |
375 | }; |
376 | ||
377 | /* Instruction costs on RS64A processors. */ | |
378 | static const | |
379 | struct processor_costs rs64a_cost = { | |
06a67bdd RS |
380 | COSTS_N_INSNS (20), /* mulsi */ |
381 | COSTS_N_INSNS (12), /* mulsi_const */ | |
382 | COSTS_N_INSNS (8), /* mulsi_const9 */ | |
383 | COSTS_N_INSNS (34), /* muldi */ | |
384 | COSTS_N_INSNS (65), /* divsi */ | |
385 | COSTS_N_INSNS (67), /* divdi */ | |
386 | COSTS_N_INSNS (4), /* fp */ | |
387 | COSTS_N_INSNS (4), /* dmul */ | |
388 | COSTS_N_INSNS (31), /* sdiv */ | |
389 | COSTS_N_INSNS (31), /* ddiv */ | |
8b897cfa RS |
390 | }; |
391 | ||
392 | /* Instruction costs on MPCCORE processors. */ | |
393 | static const | |
394 | struct processor_costs mpccore_cost = { | |
06a67bdd RS |
395 | COSTS_N_INSNS (2), /* mulsi */ |
396 | COSTS_N_INSNS (2), /* mulsi_const */ | |
397 | COSTS_N_INSNS (2), /* mulsi_const9 */ | |
398 | COSTS_N_INSNS (2), /* muldi */ | |
399 | COSTS_N_INSNS (6), /* divsi */ | |
400 | COSTS_N_INSNS (6), /* divdi */ | |
401 | COSTS_N_INSNS (4), /* fp */ | |
402 | COSTS_N_INSNS (5), /* dmul */ | |
403 | COSTS_N_INSNS (10), /* sdiv */ | |
404 | COSTS_N_INSNS (17), /* ddiv */ | |
8b897cfa RS |
405 | }; |
406 | ||
407 | /* Instruction costs on PPC403 processors. */ | |
408 | static const | |
409 | struct processor_costs ppc403_cost = { | |
06a67bdd RS |
410 | COSTS_N_INSNS (4), /* mulsi */ |
411 | COSTS_N_INSNS (4), /* mulsi_const */ | |
412 | COSTS_N_INSNS (4), /* mulsi_const9 */ | |
413 | COSTS_N_INSNS (4), /* muldi */ | |
414 | COSTS_N_INSNS (33), /* divsi */ | |
415 | COSTS_N_INSNS (33), /* divdi */ | |
416 | COSTS_N_INSNS (11), /* fp */ | |
417 | COSTS_N_INSNS (11), /* dmul */ | |
418 | COSTS_N_INSNS (11), /* sdiv */ | |
419 | COSTS_N_INSNS (11), /* ddiv */ | |
8b897cfa RS |
420 | }; |
421 | ||
422 | /* Instruction costs on PPC405 processors. */ | |
423 | static const | |
424 | struct processor_costs ppc405_cost = { | |
06a67bdd RS |
425 | COSTS_N_INSNS (5), /* mulsi */ |
426 | COSTS_N_INSNS (4), /* mulsi_const */ | |
427 | COSTS_N_INSNS (3), /* mulsi_const9 */ | |
428 | COSTS_N_INSNS (5), /* muldi */ | |
429 | COSTS_N_INSNS (35), /* divsi */ | |
430 | COSTS_N_INSNS (35), /* divdi */ | |
431 | COSTS_N_INSNS (11), /* fp */ | |
432 | COSTS_N_INSNS (11), /* dmul */ | |
433 | COSTS_N_INSNS (11), /* sdiv */ | |
434 | COSTS_N_INSNS (11), /* ddiv */ | |
8b897cfa RS |
435 | }; |
436 | ||
437 | /* Instruction costs on PPC440 processors. */ | |
438 | static const | |
439 | struct processor_costs ppc440_cost = { | |
06a67bdd RS |
440 | COSTS_N_INSNS (3), /* mulsi */ |
441 | COSTS_N_INSNS (2), /* mulsi_const */ | |
442 | COSTS_N_INSNS (2), /* mulsi_const9 */ | |
443 | COSTS_N_INSNS (3), /* muldi */ | |
444 | COSTS_N_INSNS (34), /* divsi */ | |
445 | COSTS_N_INSNS (34), /* divdi */ | |
446 | COSTS_N_INSNS (5), /* fp */ | |
447 | COSTS_N_INSNS (5), /* dmul */ | |
448 | COSTS_N_INSNS (19), /* sdiv */ | |
449 | COSTS_N_INSNS (33), /* ddiv */ | |
8b897cfa RS |
450 | }; |
451 | ||
452 | /* Instruction costs on PPC601 processors. */ | |
453 | static const | |
454 | struct processor_costs ppc601_cost = { | |
06a67bdd RS |
455 | COSTS_N_INSNS (5), /* mulsi */ |
456 | COSTS_N_INSNS (5), /* mulsi_const */ | |
457 | COSTS_N_INSNS (5), /* mulsi_const9 */ | |
458 | COSTS_N_INSNS (5), /* muldi */ | |
459 | COSTS_N_INSNS (36), /* divsi */ | |
460 | COSTS_N_INSNS (36), /* divdi */ | |
461 | COSTS_N_INSNS (4), /* fp */ | |
462 | COSTS_N_INSNS (5), /* dmul */ | |
463 | COSTS_N_INSNS (17), /* sdiv */ | |
464 | COSTS_N_INSNS (31), /* ddiv */ | |
8b897cfa RS |
465 | }; |
466 | ||
467 | /* Instruction costs on PPC603 processors. */ | |
468 | static const | |
469 | struct processor_costs ppc603_cost = { | |
06a67bdd RS |
470 | COSTS_N_INSNS (5), /* mulsi */ |
471 | COSTS_N_INSNS (3), /* mulsi_const */ | |
472 | COSTS_N_INSNS (2), /* mulsi_const9 */ | |
473 | COSTS_N_INSNS (5), /* muldi */ | |
474 | COSTS_N_INSNS (37), /* divsi */ | |
475 | COSTS_N_INSNS (37), /* divdi */ | |
476 | COSTS_N_INSNS (3), /* fp */ | |
477 | COSTS_N_INSNS (4), /* dmul */ | |
478 | COSTS_N_INSNS (18), /* sdiv */ | |
479 | COSTS_N_INSNS (33), /* ddiv */ | |
8b897cfa RS |
480 | }; |
481 | ||
482 | /* Instruction costs on PPC604 processors. */ | |
483 | static const | |
484 | struct processor_costs ppc604_cost = { | |
06a67bdd RS |
485 | COSTS_N_INSNS (4), /* mulsi */ |
486 | COSTS_N_INSNS (4), /* mulsi_const */ | |
487 | COSTS_N_INSNS (4), /* mulsi_const9 */ | |
488 | COSTS_N_INSNS (4), /* muldi */ | |
489 | COSTS_N_INSNS (20), /* divsi */ | |
490 | COSTS_N_INSNS (20), /* divdi */ | |
491 | COSTS_N_INSNS (3), /* fp */ | |
492 | COSTS_N_INSNS (3), /* dmul */ | |
493 | COSTS_N_INSNS (18), /* sdiv */ | |
494 | COSTS_N_INSNS (32), /* ddiv */ | |
8b897cfa RS |
495 | }; |
496 | ||
497 | /* Instruction costs on PPC604e processors. */ | |
498 | static const | |
499 | struct processor_costs ppc604e_cost = { | |
06a67bdd RS |
500 | COSTS_N_INSNS (2), /* mulsi */ |
501 | COSTS_N_INSNS (2), /* mulsi_const */ | |
502 | COSTS_N_INSNS (2), /* mulsi_const9 */ | |
503 | COSTS_N_INSNS (2), /* muldi */ | |
504 | COSTS_N_INSNS (20), /* divsi */ | |
505 | COSTS_N_INSNS (20), /* divdi */ | |
506 | COSTS_N_INSNS (3), /* fp */ | |
507 | COSTS_N_INSNS (3), /* dmul */ | |
508 | COSTS_N_INSNS (18), /* sdiv */ | |
509 | COSTS_N_INSNS (32), /* ddiv */ | |
8b897cfa RS |
510 | }; |
511 | ||
f0517163 | 512 | /* Instruction costs on PPC620 processors. */ |
8b897cfa RS |
513 | static const |
514 | struct processor_costs ppc620_cost = { | |
06a67bdd RS |
515 | COSTS_N_INSNS (5), /* mulsi */ |
516 | COSTS_N_INSNS (4), /* mulsi_const */ | |
517 | COSTS_N_INSNS (3), /* mulsi_const9 */ | |
518 | COSTS_N_INSNS (7), /* muldi */ | |
519 | COSTS_N_INSNS (21), /* divsi */ | |
520 | COSTS_N_INSNS (37), /* divdi */ | |
521 | COSTS_N_INSNS (3), /* fp */ | |
522 | COSTS_N_INSNS (3), /* dmul */ | |
523 | COSTS_N_INSNS (18), /* sdiv */ | |
524 | COSTS_N_INSNS (32), /* ddiv */ | |
f0517163 RS |
525 | }; |
526 | ||
527 | /* Instruction costs on PPC630 processors. */ | |
528 | static const | |
529 | struct processor_costs ppc630_cost = { | |
06a67bdd RS |
530 | COSTS_N_INSNS (5), /* mulsi */ |
531 | COSTS_N_INSNS (4), /* mulsi_const */ | |
532 | COSTS_N_INSNS (3), /* mulsi_const9 */ | |
533 | COSTS_N_INSNS (7), /* muldi */ | |
534 | COSTS_N_INSNS (21), /* divsi */ | |
535 | COSTS_N_INSNS (37), /* divdi */ | |
536 | COSTS_N_INSNS (3), /* fp */ | |
537 | COSTS_N_INSNS (3), /* dmul */ | |
538 | COSTS_N_INSNS (17), /* sdiv */ | |
539 | COSTS_N_INSNS (21), /* ddiv */ | |
8b897cfa RS |
540 | }; |
541 | ||
542 | /* Instruction costs on PPC750 and PPC7400 processors. */ | |
543 | static const | |
544 | struct processor_costs ppc750_cost = { | |
06a67bdd RS |
545 | COSTS_N_INSNS (5), /* mulsi */ |
546 | COSTS_N_INSNS (3), /* mulsi_const */ | |
547 | COSTS_N_INSNS (2), /* mulsi_const9 */ | |
548 | COSTS_N_INSNS (5), /* muldi */ | |
549 | COSTS_N_INSNS (17), /* divsi */ | |
550 | COSTS_N_INSNS (17), /* divdi */ | |
551 | COSTS_N_INSNS (3), /* fp */ | |
552 | COSTS_N_INSNS (3), /* dmul */ | |
553 | COSTS_N_INSNS (17), /* sdiv */ | |
554 | COSTS_N_INSNS (31), /* ddiv */ | |
8b897cfa RS |
555 | }; |
556 | ||
557 | /* Instruction costs on PPC7450 processors. */ | |
558 | static const | |
559 | struct processor_costs ppc7450_cost = { | |
06a67bdd RS |
560 | COSTS_N_INSNS (4), /* mulsi */ |
561 | COSTS_N_INSNS (3), /* mulsi_const */ | |
562 | COSTS_N_INSNS (3), /* mulsi_const9 */ | |
563 | COSTS_N_INSNS (4), /* muldi */ | |
564 | COSTS_N_INSNS (23), /* divsi */ | |
565 | COSTS_N_INSNS (23), /* divdi */ | |
566 | COSTS_N_INSNS (5), /* fp */ | |
567 | COSTS_N_INSNS (5), /* dmul */ | |
568 | COSTS_N_INSNS (21), /* sdiv */ | |
569 | COSTS_N_INSNS (35), /* ddiv */ | |
8b897cfa | 570 | }; |
a3170dc6 | 571 | |
8b897cfa RS |
572 | /* Instruction costs on PPC8540 processors. */ |
573 | static const | |
574 | struct processor_costs ppc8540_cost = { | |
06a67bdd RS |
575 | COSTS_N_INSNS (4), /* mulsi */ |
576 | COSTS_N_INSNS (4), /* mulsi_const */ | |
577 | COSTS_N_INSNS (4), /* mulsi_const9 */ | |
578 | COSTS_N_INSNS (4), /* muldi */ | |
579 | COSTS_N_INSNS (19), /* divsi */ | |
580 | COSTS_N_INSNS (19), /* divdi */ | |
581 | COSTS_N_INSNS (4), /* fp */ | |
582 | COSTS_N_INSNS (4), /* dmul */ | |
583 | COSTS_N_INSNS (29), /* sdiv */ | |
584 | COSTS_N_INSNS (29), /* ddiv */ | |
8b897cfa RS |
585 | }; |
586 | ||
587 | /* Instruction costs on POWER4 and POWER5 processors. */ | |
588 | static const | |
589 | struct processor_costs power4_cost = { | |
06a67bdd RS |
590 | COSTS_N_INSNS (3), /* mulsi */ |
591 | COSTS_N_INSNS (2), /* mulsi_const */ | |
592 | COSTS_N_INSNS (2), /* mulsi_const9 */ | |
593 | COSTS_N_INSNS (4), /* muldi */ | |
594 | COSTS_N_INSNS (18), /* divsi */ | |
595 | COSTS_N_INSNS (34), /* divdi */ | |
596 | COSTS_N_INSNS (3), /* fp */ | |
597 | COSTS_N_INSNS (3), /* dmul */ | |
598 | COSTS_N_INSNS (17), /* sdiv */ | |
599 | COSTS_N_INSNS (17), /* ddiv */ | |
8b897cfa RS |
600 | }; |
601 | ||
602 | \f | |
a2369ed3 | 603 | static bool rs6000_function_ok_for_sibcall (tree, tree); |
a2369ed3 DJ |
604 | static rtx rs6000_generate_compare (enum rtx_code); |
605 | static void rs6000_maybe_dead (rtx); | |
606 | static void rs6000_emit_stack_tie (void); | |
607 | static void rs6000_frame_related (rtx, rtx, HOST_WIDE_INT, rtx, rtx); | |
608 | static rtx spe_synthesize_frame_save (rtx); | |
609 | static bool spe_func_has_64bit_regs_p (void); | |
b20a9cca | 610 | static void emit_frame_save (rtx, rtx, enum machine_mode, unsigned int, |
d1d0c603 | 611 | int, HOST_WIDE_INT); |
a2369ed3 DJ |
612 | static rtx gen_frame_mem_offset (enum machine_mode, rtx, int); |
613 | static void rs6000_emit_allocate_stack (HOST_WIDE_INT, int); | |
614 | static unsigned rs6000_hash_constant (rtx); | |
615 | static unsigned toc_hash_function (const void *); | |
616 | static int toc_hash_eq (const void *, const void *); | |
617 | static int constant_pool_expr_1 (rtx, int *, int *); | |
618 | static bool constant_pool_expr_p (rtx); | |
a2369ed3 | 619 | static bool legitimate_small_data_p (enum machine_mode, rtx); |
a2369ed3 | 620 | static bool legitimate_indexed_address_p (rtx, int); |
a2369ed3 DJ |
621 | static bool legitimate_lo_sum_address_p (enum machine_mode, rtx, int); |
622 | static struct machine_function * rs6000_init_machine_status (void); | |
623 | static bool rs6000_assemble_integer (rtx, unsigned int, int); | |
5add3202 | 624 | #ifdef HAVE_GAS_HIDDEN |
a2369ed3 | 625 | static void rs6000_assemble_visibility (tree, int); |
5add3202 | 626 | #endif |
a2369ed3 DJ |
627 | static int rs6000_ra_ever_killed (void); |
628 | static tree rs6000_handle_longcall_attribute (tree *, tree, tree, int, bool *); | |
8bb418a3 | 629 | static tree rs6000_handle_altivec_attribute (tree *, tree, tree, int, bool *); |
76d2b81d | 630 | static void rs6000_eliminate_indexed_memrefs (rtx operands[2]); |
f18eca82 | 631 | static const char *rs6000_mangle_fundamental_type (tree); |
b86fe7b4 | 632 | extern const struct attribute_spec rs6000_attribute_table[]; |
a2369ed3 DJ |
633 | static void rs6000_set_default_type_attributes (tree); |
634 | static void rs6000_output_function_prologue (FILE *, HOST_WIDE_INT); | |
635 | static void rs6000_output_function_epilogue (FILE *, HOST_WIDE_INT); | |
b20a9cca AM |
636 | static void rs6000_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT, |
637 | tree); | |
a2369ed3 | 638 | static rtx rs6000_emit_set_long_const (rtx, HOST_WIDE_INT, HOST_WIDE_INT); |
c6e8c921 | 639 | static bool rs6000_return_in_memory (tree, tree); |
a2369ed3 | 640 | static void rs6000_file_start (void); |
7c262518 | 641 | #if TARGET_ELF |
a2369ed3 DJ |
642 | static unsigned int rs6000_elf_section_type_flags (tree, const char *, int); |
643 | static void rs6000_elf_asm_out_constructor (rtx, int); | |
644 | static void rs6000_elf_asm_out_destructor (rtx, int); | |
1334b570 | 645 | static void rs6000_elf_end_indicate_exec_stack (void) ATTRIBUTE_UNUSED; |
a2369ed3 DJ |
646 | static void rs6000_elf_select_section (tree, int, unsigned HOST_WIDE_INT); |
647 | static void rs6000_elf_unique_section (tree, int); | |
648 | static void rs6000_elf_select_rtx_section (enum machine_mode, rtx, | |
b20a9cca | 649 | unsigned HOST_WIDE_INT); |
a56d7372 | 650 | static void rs6000_elf_encode_section_info (tree, rtx, int) |
0e5dbd9b | 651 | ATTRIBUTE_UNUSED; |
a2369ed3 | 652 | static bool rs6000_elf_in_small_data_p (tree); |
7c262518 | 653 | #endif |
cbaaba19 | 654 | #if TARGET_XCOFF |
a2369ed3 | 655 | static void rs6000_xcoff_asm_globalize_label (FILE *, const char *); |
8210e4c4 | 656 | static void rs6000_xcoff_asm_named_section (const char *, unsigned int, tree); |
a2369ed3 DJ |
657 | static void rs6000_xcoff_select_section (tree, int, unsigned HOST_WIDE_INT); |
658 | static void rs6000_xcoff_unique_section (tree, int); | |
659 | static void rs6000_xcoff_select_rtx_section (enum machine_mode, rtx, | |
b20a9cca | 660 | unsigned HOST_WIDE_INT); |
a2369ed3 DJ |
661 | static const char * rs6000_xcoff_strip_name_encoding (const char *); |
662 | static unsigned int rs6000_xcoff_section_type_flags (tree, const char *, int); | |
663 | static void rs6000_xcoff_file_start (void); | |
664 | static void rs6000_xcoff_file_end (void); | |
f1384257 AM |
665 | #endif |
666 | #if TARGET_MACHO | |
a2369ed3 | 667 | static bool rs6000_binds_local_p (tree); |
f1384257 | 668 | #endif |
a2369ed3 DJ |
669 | static int rs6000_variable_issue (FILE *, int, rtx, int); |
670 | static bool rs6000_rtx_costs (rtx, int, int, int *); | |
671 | static int rs6000_adjust_cost (rtx, rtx, rtx, int); | |
cbe26ab8 | 672 | static bool is_microcoded_insn (rtx); |
79ae11c4 | 673 | static int is_dispatch_slot_restricted (rtx); |
cbe26ab8 DN |
674 | static bool is_cracked_insn (rtx); |
675 | static bool is_branch_slot_insn (rtx); | |
a2369ed3 DJ |
676 | static int rs6000_adjust_priority (rtx, int); |
677 | static int rs6000_issue_rate (void); | |
569fa502 | 678 | static bool rs6000_is_costly_dependence (rtx, rtx, rtx, int, int); |
cbe26ab8 DN |
679 | static rtx get_next_active_insn (rtx, rtx); |
680 | static bool insn_terminates_group_p (rtx , enum group_termination); | |
681 | static bool is_costly_group (rtx *, rtx); | |
682 | static int force_new_group (int, FILE *, rtx *, rtx, bool *, int, int *); | |
683 | static int redefine_groups (FILE *, int, rtx, rtx); | |
684 | static int pad_groups (FILE *, int, rtx, rtx); | |
685 | static void rs6000_sched_finish (FILE *, int); | |
a2369ed3 | 686 | static int rs6000_use_sched_lookahead (void); |
7ccf35ed | 687 | static tree rs6000_builtin_mask_for_load (void); |
a2369ed3 DJ |
688 | |
689 | static void rs6000_init_builtins (void); | |
690 | static rtx rs6000_expand_unop_builtin (enum insn_code, tree, rtx); | |
691 | static rtx rs6000_expand_binop_builtin (enum insn_code, tree, rtx); | |
692 | static rtx rs6000_expand_ternop_builtin (enum insn_code, tree, rtx); | |
693 | static rtx rs6000_expand_builtin (tree, rtx, rtx, enum machine_mode, int); | |
694 | static void altivec_init_builtins (void); | |
695 | static void rs6000_common_init_builtins (void); | |
c15c90bb | 696 | static void rs6000_init_libfuncs (void); |
a2369ed3 | 697 | |
b20a9cca AM |
698 | static void enable_mask_for_builtins (struct builtin_description *, int, |
699 | enum rs6000_builtins, | |
700 | enum rs6000_builtins); | |
7c62e993 | 701 | static tree build_opaque_vector_type (tree, int); |
a2369ed3 DJ |
702 | static void spe_init_builtins (void); |
703 | static rtx spe_expand_builtin (tree, rtx, bool *); | |
61bea3b0 | 704 | static rtx spe_expand_stv_builtin (enum insn_code, tree); |
a2369ed3 DJ |
705 | static rtx spe_expand_predicate_builtin (enum insn_code, tree, rtx); |
706 | static rtx spe_expand_evsel_builtin (enum insn_code, tree, rtx); | |
707 | static int rs6000_emit_int_cmove (rtx, rtx, rtx, rtx); | |
d1d0c603 JJ |
708 | static rs6000_stack_t *rs6000_stack_info (void); |
709 | static void debug_stack_info (rs6000_stack_t *); | |
a2369ed3 DJ |
710 | |
711 | static rtx altivec_expand_builtin (tree, rtx, bool *); | |
712 | static rtx altivec_expand_ld_builtin (tree, rtx, bool *); | |
713 | static rtx altivec_expand_st_builtin (tree, rtx, bool *); | |
714 | static rtx altivec_expand_dst_builtin (tree, rtx, bool *); | |
715 | static rtx altivec_expand_abs_builtin (enum insn_code, tree, rtx); | |
f676971a | 716 | static rtx altivec_expand_predicate_builtin (enum insn_code, |
c4ad648e | 717 | const char *, tree, rtx); |
b4a62fa0 | 718 | static rtx altivec_expand_lv_builtin (enum insn_code, tree, rtx); |
a2369ed3 DJ |
719 | static rtx altivec_expand_stv_builtin (enum insn_code, tree); |
720 | static void rs6000_parse_abi_options (void); | |
721 | static void rs6000_parse_alignment_option (void); | |
722 | static void rs6000_parse_tls_size_option (void); | |
5da702b1 | 723 | static void rs6000_parse_yes_no_option (const char *, const char *, int *); |
4d4cbc0e | 724 | static void rs6000_parse_float_gprs_option (void); |
a2369ed3 DJ |
725 | static int first_altivec_reg_to_save (void); |
726 | static unsigned int compute_vrsave_mask (void); | |
9390387d | 727 | static void compute_save_world_info (rs6000_stack_t *info_ptr); |
a2369ed3 DJ |
728 | static void is_altivec_return_reg (rtx, void *); |
729 | static rtx generate_set_vrsave (rtx, rs6000_stack_t *, int); | |
730 | int easy_vector_constant (rtx, enum machine_mode); | |
a2369ed3 DJ |
731 | static bool is_ev64_opaque_type (tree); |
732 | static rtx rs6000_dwarf_register_span (rtx); | |
733 | static rtx rs6000_legitimize_tls_address (rtx, enum tls_model); | |
734 | static rtx rs6000_tls_get_addr (void); | |
735 | static rtx rs6000_got_sym (void); | |
9390387d | 736 | static int rs6000_tls_symbol_ref_1 (rtx *, void *); |
a2369ed3 DJ |
737 | static const char *rs6000_get_some_local_dynamic_name (void); |
738 | static int rs6000_get_some_local_dynamic_name_1 (rtx *, void *); | |
ded9bf77 | 739 | static rtx rs6000_complex_function_value (enum machine_mode); |
b20a9cca | 740 | static rtx rs6000_spe_function_arg (CUMULATIVE_ARGS *, |
a2369ed3 | 741 | enum machine_mode, tree); |
0b5383eb DJ |
742 | static void rs6000_darwin64_record_arg_advance_flush (CUMULATIVE_ARGS *, |
743 | HOST_WIDE_INT); | |
744 | static void rs6000_darwin64_record_arg_advance_recurse (CUMULATIVE_ARGS *, | |
745 | tree, HOST_WIDE_INT); | |
746 | static void rs6000_darwin64_record_arg_flush (CUMULATIVE_ARGS *, | |
747 | HOST_WIDE_INT, | |
748 | rtx[], int *); | |
749 | static void rs6000_darwin64_record_arg_recurse (CUMULATIVE_ARGS *, | |
750 | tree, HOST_WIDE_INT, | |
751 | rtx[], int *); | |
752 | static rtx rs6000_darwin64_record_arg (CUMULATIVE_ARGS *, tree, int, bool); | |
ec6376ab | 753 | static rtx rs6000_mixed_function_arg (enum machine_mode, tree, int); |
b1917422 | 754 | static void rs6000_move_block_from_reg (int regno, rtx x, int nregs); |
c6e8c921 GK |
755 | static void setup_incoming_varargs (CUMULATIVE_ARGS *, |
756 | enum machine_mode, tree, | |
757 | int *, int); | |
8cd5a4e0 RH |
758 | static bool rs6000_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode, |
759 | tree, bool); | |
78a52f11 RH |
760 | static int rs6000_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode, |
761 | tree, bool); | |
4d3e6fae | 762 | static const char *invalid_arg_for_unprototyped_fn (tree, tree, tree); |
efdba735 SH |
763 | #if TARGET_MACHO |
764 | static void macho_branch_islands (void); | |
765 | static void add_compiler_branch_island (tree, tree, int); | |
766 | static int no_previous_def (tree function_name); | |
767 | static tree get_prev_label (tree function_name); | |
c4e18b1c | 768 | static void rs6000_darwin_file_start (void); |
efdba735 SH |
769 | #endif |
770 | ||
c35d187f | 771 | static tree rs6000_build_builtin_va_list (void); |
23a60a04 | 772 | static tree rs6000_gimplify_va_arg (tree, tree, tree *, tree *); |
fe984136 | 773 | static bool rs6000_must_pass_in_stack (enum machine_mode, tree); |
f676971a | 774 | static bool rs6000_vector_mode_supported_p (enum machine_mode); |
94ff898d | 775 | static int get_vec_cmp_insn (enum rtx_code, enum machine_mode, |
21213b4c | 776 | enum machine_mode); |
94ff898d | 777 | static rtx rs6000_emit_vector_compare (enum rtx_code, rtx, rtx, |
21213b4c DP |
778 | enum machine_mode); |
779 | static int get_vsel_insn (enum machine_mode); | |
780 | static void rs6000_emit_vector_select (rtx, rtx, rtx, rtx); | |
17211ab5 | 781 | |
21213b4c DP |
782 | |
783 | const int INSN_NOT_AVAILABLE = -1; | |
93f90be6 FJ |
784 | static enum machine_mode rs6000_eh_return_filter_mode (void); |
785 | ||
17211ab5 GK |
786 | /* Hash table stuff for keeping track of TOC entries. */ |
787 | ||
788 | struct toc_hash_struct GTY(()) | |
789 | { | |
790 | /* `key' will satisfy CONSTANT_P; in fact, it will satisfy | |
791 | ASM_OUTPUT_SPECIAL_POOL_ENTRY_P. */ | |
792 | rtx key; | |
793 | enum machine_mode key_mode; | |
794 | int labelno; | |
795 | }; | |
796 | ||
797 | static GTY ((param_is (struct toc_hash_struct))) htab_t toc_hash_table; | |
c81bebd7 MM |
798 | \f |
799 | /* Default register names. */ | |
800 | char rs6000_reg_names[][8] = | |
801 | { | |
802a0058 MM |
802 | "0", "1", "2", "3", "4", "5", "6", "7", |
803 | "8", "9", "10", "11", "12", "13", "14", "15", | |
804 | "16", "17", "18", "19", "20", "21", "22", "23", | |
805 | "24", "25", "26", "27", "28", "29", "30", "31", | |
806 | "0", "1", "2", "3", "4", "5", "6", "7", | |
807 | "8", "9", "10", "11", "12", "13", "14", "15", | |
808 | "16", "17", "18", "19", "20", "21", "22", "23", | |
809 | "24", "25", "26", "27", "28", "29", "30", "31", | |
810 | "mq", "lr", "ctr","ap", | |
811 | "0", "1", "2", "3", "4", "5", "6", "7", | |
0ac081f6 AH |
812 | "xer", |
813 | /* AltiVec registers. */ | |
0cd5e3a1 AH |
814 | "0", "1", "2", "3", "4", "5", "6", "7", |
815 | "8", "9", "10", "11", "12", "13", "14", "15", | |
816 | "16", "17", "18", "19", "20", "21", "22", "23", | |
817 | "24", "25", "26", "27", "28", "29", "30", "31", | |
59a4c851 AH |
818 | "vrsave", "vscr", |
819 | /* SPE registers. */ | |
820 | "spe_acc", "spefscr" | |
c81bebd7 MM |
821 | }; |
822 | ||
823 | #ifdef TARGET_REGNAMES | |
8b60264b | 824 | static const char alt_reg_names[][8] = |
c81bebd7 | 825 | { |
802a0058 MM |
826 | "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7", |
827 | "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15", | |
828 | "%r16", "%r17", "%r18", "%r19", "%r20", "%r21", "%r22", "%r23", | |
829 | "%r24", "%r25", "%r26", "%r27", "%r28", "%r29", "%r30", "%r31", | |
830 | "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7", | |
831 | "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15", | |
832 | "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23", | |
833 | "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31", | |
834 | "mq", "lr", "ctr", "ap", | |
835 | "%cr0", "%cr1", "%cr2", "%cr3", "%cr4", "%cr5", "%cr6", "%cr7", | |
0ac081f6 | 836 | "xer", |
59a4c851 | 837 | /* AltiVec registers. */ |
0ac081f6 | 838 | "%v0", "%v1", "%v2", "%v3", "%v4", "%v5", "%v6", "%v7", |
59a4c851 AH |
839 | "%v8", "%v9", "%v10", "%v11", "%v12", "%v13", "%v14", "%v15", |
840 | "%v16", "%v17", "%v18", "%v19", "%v20", "%v21", "%v22", "%v23", | |
841 | "%v24", "%v25", "%v26", "%v27", "%v28", "%v29", "%v30", "%v31", | |
842 | "vrsave", "vscr", | |
843 | /* SPE registers. */ | |
844 | "spe_acc", "spefscr" | |
c81bebd7 MM |
845 | }; |
846 | #endif | |
9878760c | 847 | \f |
daf11973 MM |
848 | #ifndef MASK_STRICT_ALIGN |
849 | #define MASK_STRICT_ALIGN 0 | |
850 | #endif | |
ffcfcb5f AM |
851 | #ifndef TARGET_PROFILE_KERNEL |
852 | #define TARGET_PROFILE_KERNEL 0 | |
853 | #endif | |
3961e8fe RH |
854 | |
855 | /* The VRSAVE bitmask puts bit %v0 as the most significant bit. */ | |
856 | #define ALTIVEC_REG_BIT(REGNO) (0x80000000 >> ((REGNO) - FIRST_ALTIVEC_REGNO)) | |
672a6f42 NB |
857 | \f |
858 | /* Initialize the GCC target structure. */ | |
91d231cb JM |
859 | #undef TARGET_ATTRIBUTE_TABLE |
860 | #define TARGET_ATTRIBUTE_TABLE rs6000_attribute_table | |
a5c76ee6 ZW |
861 | #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES |
862 | #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES rs6000_set_default_type_attributes | |
daf11973 | 863 | |
301d03af RS |
864 | #undef TARGET_ASM_ALIGNED_DI_OP |
865 | #define TARGET_ASM_ALIGNED_DI_OP DOUBLE_INT_ASM_OP | |
866 | ||
867 | /* Default unaligned ops are only provided for ELF. Find the ops needed | |
868 | for non-ELF systems. */ | |
869 | #ifndef OBJECT_FORMAT_ELF | |
cbaaba19 | 870 | #if TARGET_XCOFF |
ae6c1efd | 871 | /* For XCOFF. rs6000_assemble_integer will handle unaligned DIs on |
301d03af RS |
872 | 64-bit targets. */ |
873 | #undef TARGET_ASM_UNALIGNED_HI_OP | |
874 | #define TARGET_ASM_UNALIGNED_HI_OP "\t.vbyte\t2," | |
875 | #undef TARGET_ASM_UNALIGNED_SI_OP | |
876 | #define TARGET_ASM_UNALIGNED_SI_OP "\t.vbyte\t4," | |
877 | #undef TARGET_ASM_UNALIGNED_DI_OP | |
878 | #define TARGET_ASM_UNALIGNED_DI_OP "\t.vbyte\t8," | |
879 | #else | |
880 | /* For Darwin. */ | |
881 | #undef TARGET_ASM_UNALIGNED_HI_OP | |
882 | #define TARGET_ASM_UNALIGNED_HI_OP "\t.short\t" | |
883 | #undef TARGET_ASM_UNALIGNED_SI_OP | |
884 | #define TARGET_ASM_UNALIGNED_SI_OP "\t.long\t" | |
49bd1d27 SS |
885 | #undef TARGET_ASM_UNALIGNED_DI_OP |
886 | #define TARGET_ASM_UNALIGNED_DI_OP "\t.quad\t" | |
887 | #undef TARGET_ASM_ALIGNED_DI_OP | |
888 | #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t" | |
301d03af RS |
889 | #endif |
890 | #endif | |
891 | ||
892 | /* This hook deals with fixups for relocatable code and DI-mode objects | |
893 | in 64-bit code. */ | |
894 | #undef TARGET_ASM_INTEGER | |
895 | #define TARGET_ASM_INTEGER rs6000_assemble_integer | |
896 | ||
93638d7a AM |
897 | #ifdef HAVE_GAS_HIDDEN |
898 | #undef TARGET_ASM_ASSEMBLE_VISIBILITY | |
899 | #define TARGET_ASM_ASSEMBLE_VISIBILITY rs6000_assemble_visibility | |
900 | #endif | |
901 | ||
c4501e62 JJ |
902 | #undef TARGET_HAVE_TLS |
903 | #define TARGET_HAVE_TLS HAVE_AS_TLS | |
904 | ||
905 | #undef TARGET_CANNOT_FORCE_CONST_MEM | |
906 | #define TARGET_CANNOT_FORCE_CONST_MEM rs6000_tls_referenced_p | |
907 | ||
08c148a8 NB |
908 | #undef TARGET_ASM_FUNCTION_PROLOGUE |
909 | #define TARGET_ASM_FUNCTION_PROLOGUE rs6000_output_function_prologue | |
910 | #undef TARGET_ASM_FUNCTION_EPILOGUE | |
911 | #define TARGET_ASM_FUNCTION_EPILOGUE rs6000_output_function_epilogue | |
912 | ||
b54cf83a DE |
913 | #undef TARGET_SCHED_VARIABLE_ISSUE |
914 | #define TARGET_SCHED_VARIABLE_ISSUE rs6000_variable_issue | |
915 | ||
c237e94a ZW |
916 | #undef TARGET_SCHED_ISSUE_RATE |
917 | #define TARGET_SCHED_ISSUE_RATE rs6000_issue_rate | |
918 | #undef TARGET_SCHED_ADJUST_COST | |
919 | #define TARGET_SCHED_ADJUST_COST rs6000_adjust_cost | |
920 | #undef TARGET_SCHED_ADJUST_PRIORITY | |
921 | #define TARGET_SCHED_ADJUST_PRIORITY rs6000_adjust_priority | |
f676971a | 922 | #undef TARGET_SCHED_IS_COSTLY_DEPENDENCE |
569fa502 | 923 | #define TARGET_SCHED_IS_COSTLY_DEPENDENCE rs6000_is_costly_dependence |
cbe26ab8 DN |
924 | #undef TARGET_SCHED_FINISH |
925 | #define TARGET_SCHED_FINISH rs6000_sched_finish | |
c237e94a | 926 | |
be12c2b0 VM |
927 | #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD |
928 | #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD rs6000_use_sched_lookahead | |
929 | ||
7ccf35ed DN |
930 | #undef TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD |
931 | #define TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD rs6000_builtin_mask_for_load | |
932 | ||
0ac081f6 AH |
933 | #undef TARGET_INIT_BUILTINS |
934 | #define TARGET_INIT_BUILTINS rs6000_init_builtins | |
935 | ||
936 | #undef TARGET_EXPAND_BUILTIN | |
937 | #define TARGET_EXPAND_BUILTIN rs6000_expand_builtin | |
938 | ||
f18eca82 ZL |
939 | #undef TARGET_MANGLE_FUNDAMENTAL_TYPE |
940 | #define TARGET_MANGLE_FUNDAMENTAL_TYPE rs6000_mangle_fundamental_type | |
941 | ||
c15c90bb ZW |
942 | #undef TARGET_INIT_LIBFUNCS |
943 | #define TARGET_INIT_LIBFUNCS rs6000_init_libfuncs | |
944 | ||
f1384257 | 945 | #if TARGET_MACHO |
0e5dbd9b DE |
946 | #undef TARGET_BINDS_LOCAL_P |
947 | #define TARGET_BINDS_LOCAL_P rs6000_binds_local_p | |
f1384257 | 948 | #endif |
0e5dbd9b | 949 | |
3961e8fe RH |
950 | #undef TARGET_ASM_OUTPUT_MI_THUNK |
951 | #define TARGET_ASM_OUTPUT_MI_THUNK rs6000_output_mi_thunk | |
952 | ||
3961e8fe | 953 | #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK |
5b71a4e7 | 954 | #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_tree_hwi_hwi_tree_true |
00b960c7 | 955 | |
4977bab6 ZW |
956 | #undef TARGET_FUNCTION_OK_FOR_SIBCALL |
957 | #define TARGET_FUNCTION_OK_FOR_SIBCALL rs6000_function_ok_for_sibcall | |
958 | ||
3c50106f RH |
959 | #undef TARGET_RTX_COSTS |
960 | #define TARGET_RTX_COSTS rs6000_rtx_costs | |
dcefdf67 RH |
961 | #undef TARGET_ADDRESS_COST |
962 | #define TARGET_ADDRESS_COST hook_int_rtx_0 | |
3c50106f | 963 | |
c8e4f0e9 AH |
964 | #undef TARGET_VECTOR_OPAQUE_P |
965 | #define TARGET_VECTOR_OPAQUE_P is_ev64_opaque_type | |
62e1dfcf | 966 | |
96714395 AH |
967 | #undef TARGET_DWARF_REGISTER_SPAN |
968 | #define TARGET_DWARF_REGISTER_SPAN rs6000_dwarf_register_span | |
969 | ||
c6e8c921 GK |
970 | /* On rs6000, function arguments are promoted, as are function return |
971 | values. */ | |
972 | #undef TARGET_PROMOTE_FUNCTION_ARGS | |
973 | #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true | |
974 | #undef TARGET_PROMOTE_FUNCTION_RETURN | |
975 | #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true | |
976 | ||
c6e8c921 GK |
977 | #undef TARGET_RETURN_IN_MEMORY |
978 | #define TARGET_RETURN_IN_MEMORY rs6000_return_in_memory | |
979 | ||
980 | #undef TARGET_SETUP_INCOMING_VARARGS | |
981 | #define TARGET_SETUP_INCOMING_VARARGS setup_incoming_varargs | |
982 | ||
983 | /* Always strict argument naming on rs6000. */ | |
984 | #undef TARGET_STRICT_ARGUMENT_NAMING | |
985 | #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true | |
986 | #undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED | |
987 | #define TARGET_PRETEND_OUTGOING_VARARGS_NAMED hook_bool_CUMULATIVE_ARGS_true | |
42ba5130 RH |
988 | #undef TARGET_SPLIT_COMPLEX_ARG |
989 | #define TARGET_SPLIT_COMPLEX_ARG hook_bool_tree_true | |
fe984136 RH |
990 | #undef TARGET_MUST_PASS_IN_STACK |
991 | #define TARGET_MUST_PASS_IN_STACK rs6000_must_pass_in_stack | |
8cd5a4e0 RH |
992 | #undef TARGET_PASS_BY_REFERENCE |
993 | #define TARGET_PASS_BY_REFERENCE rs6000_pass_by_reference | |
78a52f11 RH |
994 | #undef TARGET_ARG_PARTIAL_BYTES |
995 | #define TARGET_ARG_PARTIAL_BYTES rs6000_arg_partial_bytes | |
c6e8c921 | 996 | |
c35d187f RH |
997 | #undef TARGET_BUILD_BUILTIN_VA_LIST |
998 | #define TARGET_BUILD_BUILTIN_VA_LIST rs6000_build_builtin_va_list | |
999 | ||
cd3ce9b4 JM |
1000 | #undef TARGET_GIMPLIFY_VA_ARG_EXPR |
1001 | #define TARGET_GIMPLIFY_VA_ARG_EXPR rs6000_gimplify_va_arg | |
1002 | ||
93f90be6 FJ |
1003 | #undef TARGET_EH_RETURN_FILTER_MODE |
1004 | #define TARGET_EH_RETURN_FILTER_MODE rs6000_eh_return_filter_mode | |
1005 | ||
f676971a EC |
1006 | #undef TARGET_VECTOR_MODE_SUPPORTED_P |
1007 | #define TARGET_VECTOR_MODE_SUPPORTED_P rs6000_vector_mode_supported_p | |
1008 | ||
4d3e6fae FJ |
1009 | #undef TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN |
1010 | #define TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN invalid_arg_for_unprototyped_fn | |
1011 | ||
445cf5eb JM |
1012 | /* MPC604EUM 3.5.2 Weak Consistency between Multiple Processors |
1013 | The PowerPC architecture requires only weak consistency among | |
1014 | processors--that is, memory accesses between processors need not be | |
1015 | sequentially consistent and memory accesses among processors can occur | |
1016 | in any order. The ability to order memory accesses weakly provides | |
1017 | opportunities for more efficient use of the system bus. Unless a | |
1018 | dependency exists, the 604e allows read operations to precede store | |
1019 | operations. */ | |
1020 | #undef TARGET_RELAXED_ORDERING | |
1021 | #define TARGET_RELAXED_ORDERING true | |
1022 | ||
f6897b10 | 1023 | struct gcc_target targetm = TARGET_INITIALIZER; |
672a6f42 | 1024 | \f |
0d1fbc8c AH |
1025 | |
1026 | /* Value is 1 if hard register REGNO can hold a value of machine-mode | |
1027 | MODE. */ | |
1028 | static int | |
1029 | rs6000_hard_regno_mode_ok (int regno, enum machine_mode mode) | |
1030 | { | |
1031 | /* The GPRs can hold any mode, but values bigger than one register | |
1032 | cannot go past R31. */ | |
1033 | if (INT_REGNO_P (regno)) | |
1034 | return INT_REGNO_P (regno + HARD_REGNO_NREGS (regno, mode) - 1); | |
1035 | ||
1036 | /* The float registers can only hold floating modes and DImode. */ | |
1037 | if (FP_REGNO_P (regno)) | |
1038 | return | |
1039 | (GET_MODE_CLASS (mode) == MODE_FLOAT | |
1040 | && FP_REGNO_P (regno + HARD_REGNO_NREGS (regno, mode) - 1)) | |
1041 | || (GET_MODE_CLASS (mode) == MODE_INT | |
1042 | && GET_MODE_SIZE (mode) == UNITS_PER_FP_WORD); | |
1043 | ||
1044 | /* The CR register can only hold CC modes. */ | |
1045 | if (CR_REGNO_P (regno)) | |
1046 | return GET_MODE_CLASS (mode) == MODE_CC; | |
1047 | ||
1048 | if (XER_REGNO_P (regno)) | |
1049 | return mode == PSImode; | |
1050 | ||
1051 | /* AltiVec only in AldyVec registers. */ | |
1052 | if (ALTIVEC_REGNO_P (regno)) | |
1053 | return ALTIVEC_VECTOR_MODE (mode); | |
1054 | ||
1055 | /* ...but GPRs can hold SIMD data on the SPE in one register. */ | |
1056 | if (SPE_SIMD_REGNO_P (regno) && TARGET_SPE && SPE_VECTOR_MODE (mode)) | |
1057 | return 1; | |
1058 | ||
1059 | /* We cannot put TImode anywhere except general register and it must be | |
1060 | able to fit within the register set. */ | |
1061 | ||
1062 | return GET_MODE_SIZE (mode) <= UNITS_PER_WORD; | |
1063 | } | |
1064 | ||
1065 | /* Initialize rs6000_hard_regno_mode_ok_p table. */ | |
1066 | static void | |
1067 | rs6000_init_hard_regno_mode_ok (void) | |
1068 | { | |
1069 | int r, m; | |
1070 | ||
1071 | for (r = 0; r < FIRST_PSEUDO_REGISTER; ++r) | |
1072 | for (m = 0; m < NUM_MACHINE_MODES; ++m) | |
1073 | if (rs6000_hard_regno_mode_ok (r, m)) | |
1074 | rs6000_hard_regno_mode_ok_p[m][r] = true; | |
1075 | } | |
1076 | ||
c1e55850 GK |
1077 | /* If not otherwise specified by a target, make 'long double' equivalent to |
1078 | 'double'. */ | |
1079 | ||
1080 | #ifndef RS6000_DEFAULT_LONG_DOUBLE_SIZE | |
1081 | #define RS6000_DEFAULT_LONG_DOUBLE_SIZE 64 | |
1082 | #endif | |
1083 | ||
5248c961 RK |
1084 | /* Override command line options. Mostly we process the processor |
1085 | type and sometimes adjust other TARGET_ options. */ | |
1086 | ||
1087 | void | |
d779d0dc | 1088 | rs6000_override_options (const char *default_cpu) |
5248c961 | 1089 | { |
c4d38ccb | 1090 | size_t i, j; |
8e3f41e7 | 1091 | struct rs6000_cpu_select *ptr; |
66188a7e | 1092 | int set_masks; |
5248c961 | 1093 | |
66188a7e | 1094 | /* Simplifications for entries below. */ |
85638c0d | 1095 | |
66188a7e GK |
1096 | enum { |
1097 | POWERPC_BASE_MASK = MASK_POWERPC | MASK_NEW_MNEMONICS, | |
1098 | POWERPC_7400_MASK = POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_ALTIVEC | |
1099 | }; | |
85638c0d | 1100 | |
66188a7e GK |
1101 | /* This table occasionally claims that a processor does not support |
1102 | a particular feature even though it does, but the feature is slower | |
1103 | than the alternative. Thus, it shouldn't be relied on as a | |
f676971a | 1104 | complete description of the processor's support. |
66188a7e GK |
1105 | |
1106 | Please keep this list in order, and don't forget to update the | |
1107 | documentation in invoke.texi when adding a new processor or | |
1108 | flag. */ | |
5248c961 RK |
1109 | static struct ptt |
1110 | { | |
8b60264b KG |
1111 | const char *const name; /* Canonical processor name. */ |
1112 | const enum processor_type processor; /* Processor type enum value. */ | |
1113 | const int target_enable; /* Target flags to enable. */ | |
8b60264b | 1114 | } const processor_target_table[] |
66188a7e | 1115 | = {{"401", PROCESSOR_PPC403, POWERPC_BASE_MASK | MASK_SOFT_FLOAT}, |
49a0b204 | 1116 | {"403", PROCESSOR_PPC403, |
66188a7e GK |
1117 | POWERPC_BASE_MASK | MASK_SOFT_FLOAT | MASK_STRICT_ALIGN}, |
1118 | {"405", PROCESSOR_PPC405, POWERPC_BASE_MASK | MASK_SOFT_FLOAT}, | |
1119 | {"405fp", PROCESSOR_PPC405, POWERPC_BASE_MASK}, | |
1120 | {"440", PROCESSOR_PPC440, POWERPC_BASE_MASK | MASK_SOFT_FLOAT}, | |
1121 | {"440fp", PROCESSOR_PPC440, POWERPC_BASE_MASK}, | |
1122 | {"505", PROCESSOR_MPCCORE, POWERPC_BASE_MASK}, | |
5248c961 | 1123 | {"601", PROCESSOR_PPC601, |
66188a7e GK |
1124 | MASK_POWER | POWERPC_BASE_MASK | MASK_MULTIPLE | MASK_STRING}, |
1125 | {"602", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT}, | |
1126 | {"603", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT}, | |
1127 | {"603e", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT}, | |
1128 | {"604", PROCESSOR_PPC604, POWERPC_BASE_MASK | MASK_PPC_GFXOPT}, | |
1129 | {"604e", PROCESSOR_PPC604e, POWERPC_BASE_MASK | MASK_PPC_GFXOPT}, | |
7ddb6568 AM |
1130 | {"620", PROCESSOR_PPC620, |
1131 | POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64}, | |
1132 | {"630", PROCESSOR_PPC630, | |
1133 | POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64}, | |
66188a7e GK |
1134 | {"740", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT}, |
1135 | {"7400", PROCESSOR_PPC7400, POWERPC_7400_MASK}, | |
1136 | {"7450", PROCESSOR_PPC7450, POWERPC_7400_MASK}, | |
1137 | {"750", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT}, | |
1138 | {"801", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT}, | |
1139 | {"821", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT}, | |
1140 | {"823", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT}, | |
1141 | {"8540", PROCESSOR_PPC8540, POWERPC_BASE_MASK | MASK_PPC_GFXOPT}, | |
4d4cbc0e AH |
1142 | /* 8548 has a dummy entry for now. */ |
1143 | {"8548", PROCESSOR_PPC8540, POWERPC_BASE_MASK | MASK_PPC_GFXOPT}, | |
66188a7e | 1144 | {"860", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT}, |
7177e720 | 1145 | {"970", PROCESSOR_POWER4, |
66188a7e GK |
1146 | POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64}, |
1147 | {"common", PROCESSOR_COMMON, MASK_NEW_MNEMONICS}, | |
1148 | {"ec603e", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_SOFT_FLOAT}, | |
1149 | {"G3", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT}, | |
1150 | {"G4", PROCESSOR_PPC7450, POWERPC_7400_MASK}, | |
49ffe578 | 1151 | {"G5", PROCESSOR_POWER4, |
66188a7e GK |
1152 | POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64}, |
1153 | {"power", PROCESSOR_POWER, MASK_POWER | MASK_MULTIPLE | MASK_STRING}, | |
1154 | {"power2", PROCESSOR_POWER, | |
1155 | MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING}, | |
7ddb6568 AM |
1156 | {"power3", PROCESSOR_PPC630, |
1157 | POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64}, | |
1158 | {"power4", PROCESSOR_POWER4, | |
fc091c8e | 1159 | POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POWERPC64}, |
ec507f2d | 1160 | {"power5", PROCESSOR_POWER5, |
fc091c8e | 1161 | POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POWERPC64}, |
66188a7e GK |
1162 | {"powerpc", PROCESSOR_POWERPC, POWERPC_BASE_MASK}, |
1163 | {"powerpc64", PROCESSOR_POWERPC64, | |
98c41d98 | 1164 | POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64}, |
66188a7e GK |
1165 | {"rios", PROCESSOR_RIOS1, MASK_POWER | MASK_MULTIPLE | MASK_STRING}, |
1166 | {"rios1", PROCESSOR_RIOS1, MASK_POWER | MASK_MULTIPLE | MASK_STRING}, | |
1167 | {"rios2", PROCESSOR_RIOS2, | |
1168 | MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING}, | |
1169 | {"rsc", PROCESSOR_PPC601, MASK_POWER | MASK_MULTIPLE | MASK_STRING}, | |
1170 | {"rsc1", PROCESSOR_PPC601, MASK_POWER | MASK_MULTIPLE | MASK_STRING}, | |
98c41d98 DE |
1171 | {"rs64", PROCESSOR_RS64A, |
1172 | POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64} | |
66188a7e | 1173 | }; |
5248c961 | 1174 | |
ca7558fc | 1175 | const size_t ptt_size = ARRAY_SIZE (processor_target_table); |
5248c961 | 1176 | |
66188a7e GK |
1177 | /* Some OSs don't support saving the high part of 64-bit registers on |
1178 | context switch. Other OSs don't support saving Altivec registers. | |
1179 | On those OSs, we don't touch the MASK_POWERPC64 or MASK_ALTIVEC | |
1180 | settings; if the user wants either, the user must explicitly specify | |
1181 | them and we won't interfere with the user's specification. */ | |
1182 | ||
1183 | enum { | |
1184 | POWER_MASKS = MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING, | |
f676971a | 1185 | POWERPC_MASKS = (POWERPC_BASE_MASK | MASK_PPC_GPOPT |
66188a7e GK |
1186 | | MASK_PPC_GFXOPT | MASK_POWERPC64 | MASK_ALTIVEC |
1187 | | MASK_MFCRF) | |
1188 | }; | |
0d1fbc8c AH |
1189 | |
1190 | rs6000_init_hard_regno_mode_ok (); | |
1191 | ||
c4ad648e | 1192 | set_masks = POWER_MASKS | POWERPC_MASKS | MASK_SOFT_FLOAT; |
66188a7e GK |
1193 | #ifdef OS_MISSING_POWERPC64 |
1194 | if (OS_MISSING_POWERPC64) | |
1195 | set_masks &= ~MASK_POWERPC64; | |
1196 | #endif | |
1197 | #ifdef OS_MISSING_ALTIVEC | |
1198 | if (OS_MISSING_ALTIVEC) | |
1199 | set_masks &= ~MASK_ALTIVEC; | |
1200 | #endif | |
1201 | ||
768875a8 AM |
1202 | /* Don't override by the processor default if given explicitly. */ |
1203 | set_masks &= ~target_flags_explicit; | |
957211c3 | 1204 | |
a4f6c312 | 1205 | /* Identify the processor type. */ |
8e3f41e7 | 1206 | rs6000_select[0].string = default_cpu; |
3cb999d8 | 1207 | rs6000_cpu = TARGET_POWERPC64 ? PROCESSOR_DEFAULT64 : PROCESSOR_DEFAULT; |
8e3f41e7 | 1208 | |
b6a1cbae | 1209 | for (i = 0; i < ARRAY_SIZE (rs6000_select); i++) |
5248c961 | 1210 | { |
8e3f41e7 MM |
1211 | ptr = &rs6000_select[i]; |
1212 | if (ptr->string != (char *)0 && ptr->string[0] != '\0') | |
5248c961 | 1213 | { |
8e3f41e7 MM |
1214 | for (j = 0; j < ptt_size; j++) |
1215 | if (! strcmp (ptr->string, processor_target_table[j].name)) | |
1216 | { | |
1217 | if (ptr->set_tune_p) | |
1218 | rs6000_cpu = processor_target_table[j].processor; | |
1219 | ||
1220 | if (ptr->set_arch_p) | |
1221 | { | |
66188a7e GK |
1222 | target_flags &= ~set_masks; |
1223 | target_flags |= (processor_target_table[j].target_enable | |
1224 | & set_masks); | |
8e3f41e7 MM |
1225 | } |
1226 | break; | |
1227 | } | |
1228 | ||
4406229e | 1229 | if (j == ptt_size) |
8e3f41e7 | 1230 | error ("bad value (%s) for %s switch", ptr->string, ptr->name); |
5248c961 RK |
1231 | } |
1232 | } | |
8a61d227 | 1233 | |
993f19a8 | 1234 | if (TARGET_E500) |
a3170dc6 AH |
1235 | rs6000_isel = 1; |
1236 | ||
dff9f1b6 DE |
1237 | /* If we are optimizing big endian systems for space, use the load/store |
1238 | multiple and string instructions. */ | |
ef792183 | 1239 | if (BYTES_BIG_ENDIAN && optimize_size) |
957211c3 | 1240 | target_flags |= ~target_flags_explicit & (MASK_MULTIPLE | MASK_STRING); |
938937d8 | 1241 | |
a4f6c312 SS |
1242 | /* Don't allow -mmultiple or -mstring on little endian systems |
1243 | unless the cpu is a 750, because the hardware doesn't support the | |
1244 | instructions used in little endian mode, and causes an alignment | |
1245 | trap. The 750 does not cause an alignment trap (except when the | |
1246 | target is unaligned). */ | |
bef84347 | 1247 | |
b21fb038 | 1248 | if (!BYTES_BIG_ENDIAN && rs6000_cpu != PROCESSOR_PPC750) |
7e69e155 MM |
1249 | { |
1250 | if (TARGET_MULTIPLE) | |
1251 | { | |
1252 | target_flags &= ~MASK_MULTIPLE; | |
b21fb038 | 1253 | if ((target_flags_explicit & MASK_MULTIPLE) != 0) |
d4ee4d25 | 1254 | warning (0, "-mmultiple is not supported on little endian systems"); |
7e69e155 MM |
1255 | } |
1256 | ||
1257 | if (TARGET_STRING) | |
1258 | { | |
1259 | target_flags &= ~MASK_STRING; | |
b21fb038 | 1260 | if ((target_flags_explicit & MASK_STRING) != 0) |
d4ee4d25 | 1261 | warning (0, "-mstring is not supported on little endian systems"); |
7e69e155 MM |
1262 | } |
1263 | } | |
3933e0e1 | 1264 | |
38c1f2d7 MM |
1265 | /* Set debug flags */ |
1266 | if (rs6000_debug_name) | |
1267 | { | |
bfc79d3b | 1268 | if (! strcmp (rs6000_debug_name, "all")) |
38c1f2d7 | 1269 | rs6000_debug_stack = rs6000_debug_arg = 1; |
bfc79d3b | 1270 | else if (! strcmp (rs6000_debug_name, "stack")) |
38c1f2d7 | 1271 | rs6000_debug_stack = 1; |
bfc79d3b | 1272 | else if (! strcmp (rs6000_debug_name, "arg")) |
38c1f2d7 MM |
1273 | rs6000_debug_arg = 1; |
1274 | else | |
c725bd79 | 1275 | error ("unknown -mdebug-%s switch", rs6000_debug_name); |
38c1f2d7 MM |
1276 | } |
1277 | ||
57ac7be9 AM |
1278 | if (rs6000_traceback_name) |
1279 | { | |
1280 | if (! strncmp (rs6000_traceback_name, "full", 4)) | |
1281 | rs6000_traceback = traceback_full; | |
1282 | else if (! strncmp (rs6000_traceback_name, "part", 4)) | |
1283 | rs6000_traceback = traceback_part; | |
1284 | else if (! strncmp (rs6000_traceback_name, "no", 2)) | |
1285 | rs6000_traceback = traceback_none; | |
1286 | else | |
9e637a26 | 1287 | error ("unknown -mtraceback arg %qs; expecting %<full%>, %<partial%> or %<none%>", |
57ac7be9 AM |
1288 | rs6000_traceback_name); |
1289 | } | |
1290 | ||
6fa3f289 | 1291 | /* Set size of long double */ |
c1e55850 | 1292 | rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE; |
6fa3f289 ZW |
1293 | if (rs6000_long_double_size_string) |
1294 | { | |
1295 | char *tail; | |
1296 | int size = strtol (rs6000_long_double_size_string, &tail, 10); | |
1297 | if (*tail != '\0' || (size != 64 && size != 128)) | |
1298 | error ("Unknown switch -mlong-double-%s", | |
1299 | rs6000_long_double_size_string); | |
1300 | else | |
1301 | rs6000_long_double_type_size = size; | |
1302 | } | |
1303 | ||
6d0ef01e HP |
1304 | /* Set Altivec ABI as default for powerpc64 linux. */ |
1305 | if (TARGET_ELF && TARGET_64BIT) | |
1306 | { | |
1307 | rs6000_altivec_abi = 1; | |
1308 | rs6000_altivec_vrsave = 1; | |
1309 | } | |
1310 | ||
594a51fe SS |
1311 | /* Set the Darwin64 ABI as default for 64-bit Darwin. */ |
1312 | if (DEFAULT_ABI == ABI_DARWIN && TARGET_64BIT) | |
1313 | { | |
1314 | rs6000_darwin64_abi = 1; | |
9c7956fd | 1315 | #if TARGET_MACHO |
6ac49599 | 1316 | darwin_one_byte_bool = 1; |
9c7956fd | 1317 | #endif |
d9168963 SS |
1318 | /* Default to natural alignment, for better performance. */ |
1319 | rs6000_alignment_flags = MASK_ALIGN_NATURAL; | |
594a51fe SS |
1320 | } |
1321 | ||
0ac081f6 AH |
1322 | /* Handle -mabi= options. */ |
1323 | rs6000_parse_abi_options (); | |
1324 | ||
025d9908 KH |
1325 | /* Handle -malign-XXXXX option. */ |
1326 | rs6000_parse_alignment_option (); | |
1327 | ||
4d4cbc0e AH |
1328 | rs6000_parse_float_gprs_option (); |
1329 | ||
5da702b1 AH |
1330 | /* Handle generic -mFOO=YES/NO options. */ |
1331 | rs6000_parse_yes_no_option ("vrsave", rs6000_altivec_vrsave_string, | |
1332 | &rs6000_altivec_vrsave); | |
1333 | rs6000_parse_yes_no_option ("isel", rs6000_isel_string, | |
1334 | &rs6000_isel); | |
1335 | rs6000_parse_yes_no_option ("spe", rs6000_spe_string, &rs6000_spe); | |
993f19a8 | 1336 | |
c4501e62 JJ |
1337 | /* Handle -mtls-size option. */ |
1338 | rs6000_parse_tls_size_option (); | |
1339 | ||
a7ae18e2 AH |
1340 | #ifdef SUBTARGET_OVERRIDE_OPTIONS |
1341 | SUBTARGET_OVERRIDE_OPTIONS; | |
1342 | #endif | |
1343 | #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS | |
1344 | SUBSUBTARGET_OVERRIDE_OPTIONS; | |
1345 | #endif | |
4d4cbc0e AH |
1346 | #ifdef SUB3TARGET_OVERRIDE_OPTIONS |
1347 | SUB3TARGET_OVERRIDE_OPTIONS; | |
1348 | #endif | |
a7ae18e2 | 1349 | |
5da702b1 AH |
1350 | if (TARGET_E500) |
1351 | { | |
e4463bf1 AH |
1352 | if (TARGET_ALTIVEC) |
1353 | error ("AltiVec and E500 instructions cannot coexist"); | |
1354 | ||
5da702b1 AH |
1355 | /* The e500 does not have string instructions, and we set |
1356 | MASK_STRING above when optimizing for size. */ | |
1357 | if ((target_flags & MASK_STRING) != 0) | |
1358 | target_flags = target_flags & ~MASK_STRING; | |
b6e59a3a AH |
1359 | |
1360 | /* No SPE means 64-bit long doubles, even if an E500. */ | |
1361 | if (rs6000_spe_string != 0 | |
c4ad648e | 1362 | && !strcmp (rs6000_spe_string, "no")) |
b6e59a3a | 1363 | rs6000_long_double_type_size = 64; |
5da702b1 AH |
1364 | } |
1365 | else if (rs6000_select[1].string != NULL) | |
1366 | { | |
1367 | /* For the powerpc-eabispe configuration, we set all these by | |
1368 | default, so let's unset them if we manually set another | |
1369 | CPU that is not the E500. */ | |
1370 | if (rs6000_abi_string == 0) | |
1371 | rs6000_spe_abi = 0; | |
1372 | if (rs6000_spe_string == 0) | |
1373 | rs6000_spe = 0; | |
1374 | if (rs6000_float_gprs_string == 0) | |
1375 | rs6000_float_gprs = 0; | |
1376 | if (rs6000_isel_string == 0) | |
1377 | rs6000_isel = 0; | |
b6e59a3a | 1378 | if (rs6000_long_double_size_string == 0) |
c1e55850 | 1379 | rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE; |
5da702b1 | 1380 | } |
b5044283 | 1381 | |
ec507f2d DE |
1382 | rs6000_always_hint = (rs6000_cpu != PROCESSOR_POWER4 |
1383 | && rs6000_cpu != PROCESSOR_POWER5); | |
1384 | rs6000_sched_groups = (rs6000_cpu == PROCESSOR_POWER4 | |
1385 | || rs6000_cpu == PROCESSOR_POWER5); | |
1386 | ||
a5c76ee6 ZW |
1387 | /* Handle -m(no-)longcall option. This is a bit of a cheap hack, |
1388 | using TARGET_OPTIONS to handle a toggle switch, but we're out of | |
1389 | bits in target_flags so TARGET_SWITCHES cannot be used. | |
1390 | Assumption here is that rs6000_longcall_switch points into the | |
1391 | text of the complete option, rather than being a copy, so we can | |
1392 | scan back for the presence or absence of the no- modifier. */ | |
1393 | if (rs6000_longcall_switch) | |
1394 | { | |
1395 | const char *base = rs6000_longcall_switch; | |
1396 | while (base[-1] != 'm') base--; | |
1397 | ||
1398 | if (*rs6000_longcall_switch != '\0') | |
9e637a26 | 1399 | error ("invalid option %qs", base); |
a5c76ee6 ZW |
1400 | rs6000_default_long_calls = (base[0] != 'n'); |
1401 | } | |
1402 | ||
8bb418a3 ZL |
1403 | /* Handle -m(no-)warn-altivec-long similarly. */ |
1404 | if (rs6000_warn_altivec_long_switch) | |
1405 | { | |
1406 | const char *base = rs6000_warn_altivec_long_switch; | |
1407 | while (base[-1] != 'm') base--; | |
1408 | ||
1409 | if (*rs6000_warn_altivec_long_switch != '\0') | |
9e637a26 | 1410 | error ("invalid option %qs", base); |
8bb418a3 ZL |
1411 | rs6000_warn_altivec_long = (base[0] != 'n'); |
1412 | } | |
1413 | ||
cbe26ab8 | 1414 | /* Handle -mprioritize-restricted-insns option. */ |
ec507f2d DE |
1415 | rs6000_sched_restricted_insns_priority |
1416 | = (rs6000_sched_groups ? 1 : 0); | |
79ae11c4 DN |
1417 | if (rs6000_sched_restricted_insns_priority_str) |
1418 | rs6000_sched_restricted_insns_priority = | |
1419 | atoi (rs6000_sched_restricted_insns_priority_str); | |
1420 | ||
569fa502 | 1421 | /* Handle -msched-costly-dep option. */ |
ec507f2d DE |
1422 | rs6000_sched_costly_dep |
1423 | = (rs6000_sched_groups ? store_to_load_dep_costly : no_dep_costly); | |
569fa502 DN |
1424 | if (rs6000_sched_costly_dep_str) |
1425 | { | |
f676971a | 1426 | if (! strcmp (rs6000_sched_costly_dep_str, "no")) |
c4ad648e | 1427 | rs6000_sched_costly_dep = no_dep_costly; |
569fa502 | 1428 | else if (! strcmp (rs6000_sched_costly_dep_str, "all")) |
c4ad648e | 1429 | rs6000_sched_costly_dep = all_deps_costly; |
569fa502 | 1430 | else if (! strcmp (rs6000_sched_costly_dep_str, "true_store_to_load")) |
c4ad648e | 1431 | rs6000_sched_costly_dep = true_store_to_load_dep_costly; |
569fa502 | 1432 | else if (! strcmp (rs6000_sched_costly_dep_str, "store_to_load")) |
c4ad648e | 1433 | rs6000_sched_costly_dep = store_to_load_dep_costly; |
f676971a | 1434 | else |
c4ad648e | 1435 | rs6000_sched_costly_dep = atoi (rs6000_sched_costly_dep_str); |
cbe26ab8 DN |
1436 | } |
1437 | ||
1438 | /* Handle -minsert-sched-nops option. */ | |
ec507f2d DE |
1439 | rs6000_sched_insert_nops |
1440 | = (rs6000_sched_groups ? sched_finish_regroup_exact : sched_finish_none); | |
cbe26ab8 DN |
1441 | if (rs6000_sched_insert_nops_str) |
1442 | { | |
1443 | if (! strcmp (rs6000_sched_insert_nops_str, "no")) | |
c4ad648e | 1444 | rs6000_sched_insert_nops = sched_finish_none; |
cbe26ab8 | 1445 | else if (! strcmp (rs6000_sched_insert_nops_str, "pad")) |
c4ad648e | 1446 | rs6000_sched_insert_nops = sched_finish_pad_groups; |
cbe26ab8 | 1447 | else if (! strcmp (rs6000_sched_insert_nops_str, "regroup_exact")) |
c4ad648e | 1448 | rs6000_sched_insert_nops = sched_finish_regroup_exact; |
cbe26ab8 | 1449 | else |
c4ad648e | 1450 | rs6000_sched_insert_nops = atoi (rs6000_sched_insert_nops_str); |
569fa502 DN |
1451 | } |
1452 | ||
c81bebd7 | 1453 | #ifdef TARGET_REGNAMES |
a4f6c312 SS |
1454 | /* If the user desires alternate register names, copy in the |
1455 | alternate names now. */ | |
c81bebd7 | 1456 | if (TARGET_REGNAMES) |
4e135bdd | 1457 | memcpy (rs6000_reg_names, alt_reg_names, sizeof (rs6000_reg_names)); |
c81bebd7 MM |
1458 | #endif |
1459 | ||
6fa3f289 ZW |
1460 | /* Set TARGET_AIX_STRUCT_RET last, after the ABI is determined. |
1461 | If -maix-struct-return or -msvr4-struct-return was explicitly | |
1462 | used, don't override with the ABI default. */ | |
b21fb038 | 1463 | if ((target_flags_explicit & MASK_AIX_STRUCT_RET) == 0) |
6fa3f289 ZW |
1464 | { |
1465 | if (DEFAULT_ABI == ABI_V4 && !DRAFT_V4_STRUCT_RET) | |
1466 | target_flags = (target_flags & ~MASK_AIX_STRUCT_RET); | |
1467 | else | |
1468 | target_flags |= MASK_AIX_STRUCT_RET; | |
1469 | } | |
1470 | ||
fcce224d DE |
1471 | if (TARGET_LONG_DOUBLE_128 |
1472 | && (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)) | |
70a01792 | 1473 | REAL_MODE_FORMAT (TFmode) = &ibm_extended_format; |
fcce224d | 1474 | |
9ebbca7d GK |
1475 | /* Allocate an alias set for register saves & restores from stack. */ |
1476 | rs6000_sr_alias_set = new_alias_set (); | |
1477 | ||
f676971a | 1478 | if (TARGET_TOC) |
9ebbca7d | 1479 | ASM_GENERATE_INTERNAL_LABEL (toc_label_name, "LCTOC", 1); |
71f123ca | 1480 | |
301d03af RS |
1481 | /* We can only guarantee the availability of DI pseudo-ops when |
1482 | assembling for 64-bit targets. */ | |
ae6c1efd | 1483 | if (!TARGET_64BIT) |
301d03af RS |
1484 | { |
1485 | targetm.asm_out.aligned_op.di = NULL; | |
1486 | targetm.asm_out.unaligned_op.di = NULL; | |
1487 | } | |
1488 | ||
1494c534 DE |
1489 | /* Set branch target alignment, if not optimizing for size. */ |
1490 | if (!optimize_size) | |
1491 | { | |
1492 | if (rs6000_sched_groups) | |
1493 | { | |
1494 | if (align_functions <= 0) | |
1495 | align_functions = 16; | |
1496 | if (align_jumps <= 0) | |
1497 | align_jumps = 16; | |
1498 | if (align_loops <= 0) | |
1499 | align_loops = 16; | |
1500 | } | |
1501 | if (align_jumps_max_skip <= 0) | |
1502 | align_jumps_max_skip = 15; | |
1503 | if (align_loops_max_skip <= 0) | |
1504 | align_loops_max_skip = 15; | |
1505 | } | |
2792d578 | 1506 | |
71f123ca FS |
1507 | /* Arrange to save and restore machine status around nested functions. */ |
1508 | init_machine_status = rs6000_init_machine_status; | |
42ba5130 RH |
1509 | |
1510 | /* We should always be splitting complex arguments, but we can't break | |
1511 | Linux and Darwin ABIs at the moment. For now, only AIX is fixed. */ | |
18f63bfa | 1512 | if (DEFAULT_ABI != ABI_AIX) |
42ba5130 | 1513 | targetm.calls.split_complex_arg = NULL; |
8b897cfa RS |
1514 | |
1515 | /* Initialize rs6000_cost with the appropriate target costs. */ | |
1516 | if (optimize_size) | |
1517 | rs6000_cost = TARGET_POWERPC64 ? &size64_cost : &size32_cost; | |
1518 | else | |
1519 | switch (rs6000_cpu) | |
1520 | { | |
1521 | case PROCESSOR_RIOS1: | |
1522 | rs6000_cost = &rios1_cost; | |
1523 | break; | |
1524 | ||
1525 | case PROCESSOR_RIOS2: | |
1526 | rs6000_cost = &rios2_cost; | |
1527 | break; | |
1528 | ||
1529 | case PROCESSOR_RS64A: | |
1530 | rs6000_cost = &rs64a_cost; | |
1531 | break; | |
1532 | ||
1533 | case PROCESSOR_MPCCORE: | |
1534 | rs6000_cost = &mpccore_cost; | |
1535 | break; | |
1536 | ||
1537 | case PROCESSOR_PPC403: | |
1538 | rs6000_cost = &ppc403_cost; | |
1539 | break; | |
1540 | ||
1541 | case PROCESSOR_PPC405: | |
1542 | rs6000_cost = &ppc405_cost; | |
1543 | break; | |
1544 | ||
1545 | case PROCESSOR_PPC440: | |
1546 | rs6000_cost = &ppc440_cost; | |
1547 | break; | |
1548 | ||
1549 | case PROCESSOR_PPC601: | |
1550 | rs6000_cost = &ppc601_cost; | |
1551 | break; | |
1552 | ||
1553 | case PROCESSOR_PPC603: | |
1554 | rs6000_cost = &ppc603_cost; | |
1555 | break; | |
1556 | ||
1557 | case PROCESSOR_PPC604: | |
1558 | rs6000_cost = &ppc604_cost; | |
1559 | break; | |
1560 | ||
1561 | case PROCESSOR_PPC604e: | |
1562 | rs6000_cost = &ppc604e_cost; | |
1563 | break; | |
1564 | ||
1565 | case PROCESSOR_PPC620: | |
8b897cfa RS |
1566 | rs6000_cost = &ppc620_cost; |
1567 | break; | |
1568 | ||
f0517163 RS |
1569 | case PROCESSOR_PPC630: |
1570 | rs6000_cost = &ppc630_cost; | |
1571 | break; | |
1572 | ||
8b897cfa RS |
1573 | case PROCESSOR_PPC750: |
1574 | case PROCESSOR_PPC7400: | |
1575 | rs6000_cost = &ppc750_cost; | |
1576 | break; | |
1577 | ||
1578 | case PROCESSOR_PPC7450: | |
1579 | rs6000_cost = &ppc7450_cost; | |
1580 | break; | |
1581 | ||
1582 | case PROCESSOR_PPC8540: | |
1583 | rs6000_cost = &ppc8540_cost; | |
1584 | break; | |
1585 | ||
1586 | case PROCESSOR_POWER4: | |
1587 | case PROCESSOR_POWER5: | |
1588 | rs6000_cost = &power4_cost; | |
1589 | break; | |
1590 | ||
1591 | default: | |
37409796 | 1592 | gcc_unreachable (); |
8b897cfa | 1593 | } |
5248c961 | 1594 | } |
5accd822 | 1595 | |
7ccf35ed DN |
1596 | /* Implement targetm.vectorize.builtin_mask_for_load. */ |
1597 | static tree | |
1598 | rs6000_builtin_mask_for_load (void) | |
1599 | { | |
1600 | if (TARGET_ALTIVEC) | |
1601 | return altivec_builtin_mask_for_load; | |
1602 | else | |
1603 | return 0; | |
1604 | } | |
1605 | ||
5da702b1 AH |
1606 | /* Handle generic options of the form -mfoo=yes/no. |
1607 | NAME is the option name. | |
1608 | VALUE is the option value. | |
1609 | FLAG is the pointer to the flag where to store a 1 or 0, depending on | |
1610 | whether the option value is 'yes' or 'no' respectively. */ | |
993f19a8 | 1611 | static void |
5da702b1 | 1612 | rs6000_parse_yes_no_option (const char *name, const char *value, int *flag) |
993f19a8 | 1613 | { |
5da702b1 | 1614 | if (value == 0) |
993f19a8 | 1615 | return; |
5da702b1 AH |
1616 | else if (!strcmp (value, "yes")) |
1617 | *flag = 1; | |
1618 | else if (!strcmp (value, "no")) | |
1619 | *flag = 0; | |
08b57fb3 | 1620 | else |
5da702b1 | 1621 | error ("unknown -m%s= option specified: '%s'", name, value); |
08b57fb3 AH |
1622 | } |
1623 | ||
0ac081f6 | 1624 | /* Handle -mabi= options. */ |
00b960c7 | 1625 | static void |
863d938c | 1626 | rs6000_parse_abi_options (void) |
0ac081f6 AH |
1627 | { |
1628 | if (rs6000_abi_string == 0) | |
1629 | return; | |
1630 | else if (! strcmp (rs6000_abi_string, "altivec")) | |
5cc73f91 AH |
1631 | { |
1632 | rs6000_altivec_abi = 1; | |
1633 | rs6000_spe_abi = 0; | |
1634 | } | |
76a773f3 AH |
1635 | else if (! strcmp (rs6000_abi_string, "no-altivec")) |
1636 | rs6000_altivec_abi = 0; | |
a3170dc6 | 1637 | else if (! strcmp (rs6000_abi_string, "spe")) |
01f4962d NS |
1638 | { |
1639 | rs6000_spe_abi = 1; | |
5cc73f91 | 1640 | rs6000_altivec_abi = 0; |
01f4962d NS |
1641 | if (!TARGET_SPE_ABI) |
1642 | error ("not configured for ABI: '%s'", rs6000_abi_string); | |
1643 | } | |
f676971a | 1644 | |
594a51fe SS |
1645 | /* These are here for testing during development only, do not |
1646 | document in the manual please. */ | |
1647 | else if (! strcmp (rs6000_abi_string, "d64")) | |
1648 | { | |
1649 | rs6000_darwin64_abi = 1; | |
d4ee4d25 | 1650 | warning (0, "Using darwin64 ABI"); |
594a51fe SS |
1651 | } |
1652 | else if (! strcmp (rs6000_abi_string, "d32")) | |
1653 | { | |
1654 | rs6000_darwin64_abi = 0; | |
d4ee4d25 | 1655 | warning (0, "Using old darwin ABI"); |
594a51fe SS |
1656 | } |
1657 | ||
a3170dc6 AH |
1658 | else if (! strcmp (rs6000_abi_string, "no-spe")) |
1659 | rs6000_spe_abi = 0; | |
0ac081f6 | 1660 | else |
c725bd79 | 1661 | error ("unknown ABI specified: '%s'", rs6000_abi_string); |
0ac081f6 AH |
1662 | } |
1663 | ||
4d4cbc0e AH |
1664 | /* Handle -mfloat-gprs= options. */ |
1665 | static void | |
1666 | rs6000_parse_float_gprs_option (void) | |
1667 | { | |
1668 | if (rs6000_float_gprs_string == 0) | |
1669 | return; | |
1670 | else if (! strcmp (rs6000_float_gprs_string, "yes") | |
1671 | || ! strcmp (rs6000_float_gprs_string, "single")) | |
1672 | rs6000_float_gprs = 1; | |
1673 | else if (! strcmp (rs6000_float_gprs_string, "double")) | |
1674 | rs6000_float_gprs = 2; | |
1675 | else if (! strcmp (rs6000_float_gprs_string, "no")) | |
1676 | rs6000_float_gprs = 0; | |
1677 | else | |
1678 | error ("invalid option for -mfloat-gprs"); | |
1679 | } | |
1680 | ||
025d9908 KH |
1681 | /* Handle -malign-XXXXXX options. */ |
1682 | static void | |
863d938c | 1683 | rs6000_parse_alignment_option (void) |
025d9908 | 1684 | { |
b20a9cca AM |
1685 | if (rs6000_alignment_string == 0) |
1686 | return; | |
1687 | else if (! strcmp (rs6000_alignment_string, "power")) | |
d9168963 SS |
1688 | { |
1689 | /* On 64-bit Darwin, power alignment is ABI-incompatible with | |
1690 | some C library functions, so warn about it. The flag may be | |
1691 | useful for performance studies from time to time though, so | |
1692 | don't disable it entirely. */ | |
1693 | if (DEFAULT_ABI == ABI_DARWIN && TARGET_64BIT) | |
d4ee4d25 | 1694 | warning (0, "-malign-power is not supported for 64-bit Darwin;" |
d9168963 SS |
1695 | " it is incompatible with the installed C and C++ libraries"); |
1696 | rs6000_alignment_flags = MASK_ALIGN_POWER; | |
1697 | } | |
025d9908 KH |
1698 | else if (! strcmp (rs6000_alignment_string, "natural")) |
1699 | rs6000_alignment_flags = MASK_ALIGN_NATURAL; | |
1700 | else | |
1701 | error ("unknown -malign-XXXXX option specified: '%s'", | |
1702 | rs6000_alignment_string); | |
1703 | } | |
1704 | ||
c4501e62 JJ |
1705 | /* Validate and record the size specified with the -mtls-size option. */ |
1706 | ||
1707 | static void | |
863d938c | 1708 | rs6000_parse_tls_size_option (void) |
c4501e62 JJ |
1709 | { |
1710 | if (rs6000_tls_size_string == 0) | |
1711 | return; | |
1712 | else if (strcmp (rs6000_tls_size_string, "16") == 0) | |
1713 | rs6000_tls_size = 16; | |
1714 | else if (strcmp (rs6000_tls_size_string, "32") == 0) | |
1715 | rs6000_tls_size = 32; | |
1716 | else if (strcmp (rs6000_tls_size_string, "64") == 0) | |
1717 | rs6000_tls_size = 64; | |
1718 | else | |
9e637a26 | 1719 | error ("bad value %qs for -mtls-size switch", rs6000_tls_size_string); |
c4501e62 JJ |
1720 | } |
1721 | ||
5accd822 | 1722 | void |
a2369ed3 | 1723 | optimization_options (int level ATTRIBUTE_UNUSED, int size ATTRIBUTE_UNUSED) |
5accd822 | 1724 | { |
5accd822 | 1725 | } |
3cfa4909 MM |
1726 | \f |
1727 | /* Do anything needed at the start of the asm file. */ | |
1728 | ||
1bc7c5b6 | 1729 | static void |
863d938c | 1730 | rs6000_file_start (void) |
3cfa4909 | 1731 | { |
c4d38ccb | 1732 | size_t i; |
3cfa4909 | 1733 | char buffer[80]; |
d330fd93 | 1734 | const char *start = buffer; |
3cfa4909 | 1735 | struct rs6000_cpu_select *ptr; |
1bc7c5b6 ZW |
1736 | const char *default_cpu = TARGET_CPU_DEFAULT; |
1737 | FILE *file = asm_out_file; | |
1738 | ||
1739 | default_file_start (); | |
1740 | ||
1741 | #ifdef TARGET_BI_ARCH | |
1742 | if ((TARGET_DEFAULT ^ target_flags) & MASK_64BIT) | |
1743 | default_cpu = 0; | |
1744 | #endif | |
3cfa4909 MM |
1745 | |
1746 | if (flag_verbose_asm) | |
1747 | { | |
1748 | sprintf (buffer, "\n%s rs6000/powerpc options:", ASM_COMMENT_START); | |
1749 | rs6000_select[0].string = default_cpu; | |
1750 | ||
b6a1cbae | 1751 | for (i = 0; i < ARRAY_SIZE (rs6000_select); i++) |
3cfa4909 MM |
1752 | { |
1753 | ptr = &rs6000_select[i]; | |
1754 | if (ptr->string != (char *)0 && ptr->string[0] != '\0') | |
1755 | { | |
1756 | fprintf (file, "%s %s%s", start, ptr->name, ptr->string); | |
1757 | start = ""; | |
1758 | } | |
1759 | } | |
1760 | ||
b91da81f | 1761 | #ifdef USING_ELFOS_H |
3cfa4909 MM |
1762 | switch (rs6000_sdata) |
1763 | { | |
1764 | case SDATA_NONE: fprintf (file, "%s -msdata=none", start); start = ""; break; | |
1765 | case SDATA_DATA: fprintf (file, "%s -msdata=data", start); start = ""; break; | |
1766 | case SDATA_SYSV: fprintf (file, "%s -msdata=sysv", start); start = ""; break; | |
1767 | case SDATA_EABI: fprintf (file, "%s -msdata=eabi", start); start = ""; break; | |
1768 | } | |
1769 | ||
1770 | if (rs6000_sdata && g_switch_value) | |
1771 | { | |
307b599c MK |
1772 | fprintf (file, "%s -G " HOST_WIDE_INT_PRINT_UNSIGNED, start, |
1773 | g_switch_value); | |
3cfa4909 MM |
1774 | start = ""; |
1775 | } | |
1776 | #endif | |
1777 | ||
1778 | if (*start == '\0') | |
949ea356 | 1779 | putc ('\n', file); |
3cfa4909 | 1780 | } |
b723e82f JJ |
1781 | |
1782 | if (DEFAULT_ABI == ABI_AIX || (TARGET_ELF && flag_pic == 2)) | |
1783 | { | |
1784 | toc_section (); | |
1785 | text_section (); | |
1786 | } | |
3cfa4909 | 1787 | } |
c4e18b1c | 1788 | |
5248c961 | 1789 | \f |
a0ab749a | 1790 | /* Return nonzero if this function is known to have a null epilogue. */ |
9878760c RK |
1791 | |
1792 | int | |
863d938c | 1793 | direct_return (void) |
9878760c | 1794 | { |
4697a36c MM |
1795 | if (reload_completed) |
1796 | { | |
1797 | rs6000_stack_t *info = rs6000_stack_info (); | |
1798 | ||
1799 | if (info->first_gp_reg_save == 32 | |
1800 | && info->first_fp_reg_save == 64 | |
00b960c7 | 1801 | && info->first_altivec_reg_save == LAST_ALTIVEC_REGNO + 1 |
c81fc13e DE |
1802 | && ! info->lr_save_p |
1803 | && ! info->cr_save_p | |
00b960c7 | 1804 | && info->vrsave_mask == 0 |
c81fc13e | 1805 | && ! info->push_p) |
4697a36c MM |
1806 | return 1; |
1807 | } | |
1808 | ||
1809 | return 0; | |
9878760c RK |
1810 | } |
1811 | ||
4e74d8ec MM |
1812 | /* Return the number of instructions it takes to form a constant in an |
1813 | integer register. */ | |
1814 | ||
48d72335 | 1815 | int |
a2369ed3 | 1816 | num_insns_constant_wide (HOST_WIDE_INT value) |
4e74d8ec MM |
1817 | { |
1818 | /* signed constant loadable with {cal|addi} */ | |
5f59ecb7 | 1819 | if (CONST_OK_FOR_LETTER_P (value, 'I')) |
0865c631 GK |
1820 | return 1; |
1821 | ||
4e74d8ec | 1822 | /* constant loadable with {cau|addis} */ |
5f59ecb7 | 1823 | else if (CONST_OK_FOR_LETTER_P (value, 'L')) |
4e74d8ec MM |
1824 | return 1; |
1825 | ||
5f59ecb7 | 1826 | #if HOST_BITS_PER_WIDE_INT == 64 |
c81fc13e | 1827 | else if (TARGET_POWERPC64) |
4e74d8ec | 1828 | { |
a65c591c DE |
1829 | HOST_WIDE_INT low = ((value & 0xffffffff) ^ 0x80000000) - 0x80000000; |
1830 | HOST_WIDE_INT high = value >> 31; | |
4e74d8ec | 1831 | |
a65c591c | 1832 | if (high == 0 || high == -1) |
4e74d8ec MM |
1833 | return 2; |
1834 | ||
a65c591c | 1835 | high >>= 1; |
4e74d8ec | 1836 | |
a65c591c | 1837 | if (low == 0) |
4e74d8ec | 1838 | return num_insns_constant_wide (high) + 1; |
4e74d8ec MM |
1839 | else |
1840 | return (num_insns_constant_wide (high) | |
e396202a | 1841 | + num_insns_constant_wide (low) + 1); |
4e74d8ec MM |
1842 | } |
1843 | #endif | |
1844 | ||
1845 | else | |
1846 | return 2; | |
1847 | } | |
1848 | ||
1849 | int | |
a2369ed3 | 1850 | num_insns_constant (rtx op, enum machine_mode mode) |
4e74d8ec | 1851 | { |
37409796 NS |
1852 | HOST_WIDE_INT low, high; |
1853 | ||
1854 | switch (GET_CODE (op)) | |
0d30d435 | 1855 | { |
37409796 | 1856 | case CONST_INT: |
0d30d435 | 1857 | #if HOST_BITS_PER_WIDE_INT == 64 |
4e2c1c44 DE |
1858 | if ((INTVAL (op) >> 31) != 0 && (INTVAL (op) >> 31) != -1 |
1859 | && mask64_operand (op, mode)) | |
c4ad648e | 1860 | return 2; |
0d30d435 DE |
1861 | else |
1862 | #endif | |
1863 | return num_insns_constant_wide (INTVAL (op)); | |
4e74d8ec | 1864 | |
37409796 NS |
1865 | case CONST_DOUBLE: |
1866 | if (mode == SFmode) | |
1867 | { | |
1868 | long l; | |
1869 | REAL_VALUE_TYPE rv; | |
1870 | ||
1871 | REAL_VALUE_FROM_CONST_DOUBLE (rv, op); | |
1872 | REAL_VALUE_TO_TARGET_SINGLE (rv, l); | |
1873 | return num_insns_constant_wide ((HOST_WIDE_INT) l); | |
1874 | } | |
a260abc9 | 1875 | |
37409796 NS |
1876 | if (mode == VOIDmode || mode == DImode) |
1877 | { | |
1878 | high = CONST_DOUBLE_HIGH (op); | |
1879 | low = CONST_DOUBLE_LOW (op); | |
1880 | } | |
1881 | else | |
1882 | { | |
1883 | long l[2]; | |
1884 | REAL_VALUE_TYPE rv; | |
1885 | ||
1886 | REAL_VALUE_FROM_CONST_DOUBLE (rv, op); | |
1887 | REAL_VALUE_TO_TARGET_DOUBLE (rv, l); | |
1888 | high = l[WORDS_BIG_ENDIAN == 0]; | |
1889 | low = l[WORDS_BIG_ENDIAN != 0]; | |
1890 | } | |
47ad8c61 | 1891 | |
37409796 NS |
1892 | if (TARGET_32BIT) |
1893 | return (num_insns_constant_wide (low) | |
1894 | + num_insns_constant_wide (high)); | |
1895 | else | |
1896 | { | |
1897 | if ((high == 0 && low >= 0) | |
1898 | || (high == -1 && low < 0)) | |
1899 | return num_insns_constant_wide (low); | |
1900 | ||
1901 | else if (mask64_operand (op, mode)) | |
1902 | return 2; | |
1903 | ||
1904 | else if (low == 0) | |
1905 | return num_insns_constant_wide (high) + 1; | |
1906 | ||
1907 | else | |
1908 | return (num_insns_constant_wide (high) | |
1909 | + num_insns_constant_wide (low) + 1); | |
1910 | } | |
1911 | ||
1912 | default: | |
1913 | gcc_unreachable (); | |
4e74d8ec | 1914 | } |
4e74d8ec MM |
1915 | } |
1916 | ||
effa5d5d | 1917 | /* Returns the constant for the splat instruction, if exists. */ |
452a7d36 | 1918 | |
48d72335 | 1919 | int |
452a7d36 HP |
1920 | easy_vector_splat_const (int cst, enum machine_mode mode) |
1921 | { | |
f676971a | 1922 | switch (mode) |
452a7d36 HP |
1923 | { |
1924 | case V4SImode: | |
f676971a EC |
1925 | if (EASY_VECTOR_15 (cst) |
1926 | || EASY_VECTOR_15_ADD_SELF (cst)) | |
452a7d36 HP |
1927 | return cst; |
1928 | if ((cst & 0xffff) != ((cst >> 16) & 0xffff)) | |
1929 | break; | |
1930 | cst = cst >> 16; | |
c4ad648e AM |
1931 | /* Fall thru */ |
1932 | ||
452a7d36 | 1933 | case V8HImode: |
f676971a EC |
1934 | if (EASY_VECTOR_15 (cst) |
1935 | || EASY_VECTOR_15_ADD_SELF (cst)) | |
452a7d36 HP |
1936 | return cst; |
1937 | if ((cst & 0xff) != ((cst >> 8) & 0xff)) | |
1938 | break; | |
1939 | cst = cst >> 8; | |
c4ad648e AM |
1940 | /* Fall thru */ |
1941 | ||
452a7d36 | 1942 | case V16QImode: |
c4ad648e AM |
1943 | if (EASY_VECTOR_15 (cst) |
1944 | || EASY_VECTOR_15_ADD_SELF (cst)) | |
1945 | return cst; | |
f676971a | 1946 | default: |
452a7d36 HP |
1947 | break; |
1948 | } | |
1949 | return 0; | |
1950 | } | |
1951 | ||
72ac76be | 1952 | /* Return nonzero if all elements of a vector have the same value. */ |
69ef87e2 | 1953 | |
48d72335 | 1954 | int |
a2369ed3 | 1955 | easy_vector_same (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
d744e06e AH |
1956 | { |
1957 | int units, i, cst; | |
1958 | ||
1959 | units = CONST_VECTOR_NUNITS (op); | |
1960 | ||
1961 | cst = INTVAL (CONST_VECTOR_ELT (op, 0)); | |
1962 | for (i = 1; i < units; ++i) | |
1963 | if (INTVAL (CONST_VECTOR_ELT (op, i)) != cst) | |
1964 | break; | |
452a7d36 | 1965 | if (i == units && easy_vector_splat_const (cst, mode)) |
d744e06e AH |
1966 | return 1; |
1967 | return 0; | |
1968 | } | |
1969 | ||
452a7d36 | 1970 | /* Generate easy_vector_constant out of a easy_vector_constant_add_self. */ |
d744e06e | 1971 | |
f676971a | 1972 | rtx |
452a7d36 HP |
1973 | gen_easy_vector_constant_add_self (rtx op) |
1974 | { | |
1975 | int i, units; | |
1976 | rtvec v; | |
1977 | units = GET_MODE_NUNITS (GET_MODE (op)); | |
1978 | v = rtvec_alloc (units); | |
1979 | ||
1980 | for (i = 0; i < units; i++) | |
f676971a | 1981 | RTVEC_ELT (v, i) = |
452a7d36 HP |
1982 | GEN_INT (INTVAL (CONST_VECTOR_ELT (op, i)) >> 1); |
1983 | return gen_rtx_raw_CONST_VECTOR (GET_MODE (op), v); | |
d744e06e AH |
1984 | } |
1985 | ||
1986 | const char * | |
a2369ed3 | 1987 | output_vec_const_move (rtx *operands) |
d744e06e AH |
1988 | { |
1989 | int cst, cst2; | |
1990 | enum machine_mode mode; | |
1991 | rtx dest, vec; | |
1992 | ||
1993 | dest = operands[0]; | |
1994 | vec = operands[1]; | |
69ef87e2 | 1995 | |
d744e06e AH |
1996 | cst = INTVAL (CONST_VECTOR_ELT (vec, 0)); |
1997 | cst2 = INTVAL (CONST_VECTOR_ELT (vec, 1)); | |
1998 | mode = GET_MODE (dest); | |
69ef87e2 | 1999 | |
d744e06e AH |
2000 | if (TARGET_ALTIVEC) |
2001 | { | |
2002 | if (zero_constant (vec, mode)) | |
2003 | return "vxor %0,%0,%0"; | |
37409796 NS |
2004 | |
2005 | gcc_assert (easy_vector_constant (vec, mode)); | |
2006 | ||
2007 | operands[1] = GEN_INT (cst); | |
2008 | switch (mode) | |
98ef3137 | 2009 | { |
37409796 NS |
2010 | case V4SImode: |
2011 | if (EASY_VECTOR_15 (cst)) | |
d744e06e | 2012 | { |
37409796 NS |
2013 | operands[1] = GEN_INT (cst); |
2014 | return "vspltisw %0,%1"; | |
2015 | } | |
2016 | else if (EASY_VECTOR_15_ADD_SELF (cst)) | |
2017 | return "#"; | |
2018 | cst = cst >> 16; | |
2019 | /* Fall thru */ | |
c4ad648e | 2020 | |
37409796 NS |
2021 | case V8HImode: |
2022 | if (EASY_VECTOR_15 (cst)) | |
2023 | { | |
2024 | operands[1] = GEN_INT (cst); | |
2025 | return "vspltish %0,%1"; | |
2026 | } | |
2027 | else if (EASY_VECTOR_15_ADD_SELF (cst)) | |
2028 | return "#"; | |
2029 | cst = cst >> 8; | |
2030 | /* Fall thru */ | |
c4ad648e | 2031 | |
37409796 NS |
2032 | case V16QImode: |
2033 | if (EASY_VECTOR_15 (cst)) | |
2034 | { | |
2035 | operands[1] = GEN_INT (cst); | |
2036 | return "vspltisb %0,%1"; | |
d744e06e | 2037 | } |
37409796 NS |
2038 | else if (EASY_VECTOR_15_ADD_SELF (cst)) |
2039 | return "#"; | |
2040 | ||
2041 | default: | |
2042 | gcc_unreachable (); | |
98ef3137 | 2043 | } |
69ef87e2 AH |
2044 | } |
2045 | ||
37409796 NS |
2046 | gcc_assert (TARGET_SPE); |
2047 | ||
2048 | /* Vector constant 0 is handled as a splitter of V2SI, and in the | |
2049 | pattern of V1DI, V4HI, and V2SF. | |
2050 | ||
2051 | FIXME: We should probably return # and add post reload | |
2052 | splitters for these, but this way is so easy ;-). */ | |
2053 | operands[1] = GEN_INT (cst); | |
2054 | operands[2] = GEN_INT (cst2); | |
2055 | if (cst == cst2) | |
2056 | return "li %0,%1\n\tevmergelo %0,%0,%0"; | |
2057 | else | |
2058 | return "li %0,%1\n\tevmergelo %0,%0,%0\n\tli %0,%2"; | |
69ef87e2 AH |
2059 | } |
2060 | ||
914c2e77 | 2061 | int |
e1e2e653 NS |
2062 | mask64_1or2_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED, |
2063 | bool allow_one) | |
0ba1b2ff AM |
2064 | { |
2065 | if (GET_CODE (op) == CONST_INT) | |
a260abc9 | 2066 | { |
0ba1b2ff | 2067 | HOST_WIDE_INT c, lsb; |
e1e2e653 NS |
2068 | bool one_ok; |
2069 | ||
0ba1b2ff | 2070 | c = INTVAL (op); |
a260abc9 | 2071 | |
0ba1b2ff AM |
2072 | /* Disallow all zeros. */ |
2073 | if (c == 0) | |
2074 | return 0; | |
a260abc9 | 2075 | |
e1e2e653 NS |
2076 | /* We can use a single rlwinm insn if no upper bits of C are set |
2077 | AND there are zero, one or two transitions in the _whole_ of | |
2078 | C. */ | |
2079 | one_ok = !(c & ~(HOST_WIDE_INT)0xffffffff); | |
2080 | ||
0ba1b2ff AM |
2081 | /* We don't change the number of transitions by inverting, |
2082 | so make sure we start with the LS bit zero. */ | |
2083 | if (c & 1) | |
2084 | c = ~c; | |
a260abc9 | 2085 | |
0ba1b2ff AM |
2086 | /* Find the first transition. */ |
2087 | lsb = c & -c; | |
a260abc9 | 2088 | |
0ba1b2ff AM |
2089 | /* Invert to look for a second transition. */ |
2090 | c = ~c; | |
2091 | ||
2092 | /* Erase first transition. */ | |
2093 | c &= -lsb; | |
2094 | ||
2095 | /* Find the second transition. */ | |
2096 | lsb = c & -c; | |
2097 | ||
2098 | /* Invert to look for a third transition. */ | |
2099 | c = ~c; | |
2100 | ||
2101 | /* Erase second transition. */ | |
2102 | c &= -lsb; | |
2103 | ||
e1e2e653 NS |
2104 | if (one_ok && !(allow_one || c)) |
2105 | return 0; | |
2106 | ||
0ba1b2ff AM |
2107 | /* Find the third transition (if any). */ |
2108 | lsb = c & -c; | |
2109 | ||
2110 | /* Match if all the bits above are 1's (or c is zero). */ | |
2111 | return c == -lsb; | |
2112 | } | |
2113 | return 0; | |
2114 | } | |
2115 | ||
2116 | /* Generates shifts and masks for a pair of rldicl or rldicr insns to | |
2117 | implement ANDing by the mask IN. */ | |
2118 | void | |
a2369ed3 | 2119 | build_mask64_2_operands (rtx in, rtx *out) |
0ba1b2ff AM |
2120 | { |
2121 | #if HOST_BITS_PER_WIDE_INT >= 64 | |
2122 | unsigned HOST_WIDE_INT c, lsb, m1, m2; | |
2123 | int shift; | |
2124 | ||
37409796 | 2125 | gcc_assert (GET_CODE (in) == CONST_INT); |
0ba1b2ff AM |
2126 | |
2127 | c = INTVAL (in); | |
2128 | if (c & 1) | |
2129 | { | |
2130 | /* Assume c initially something like 0x00fff000000fffff. The idea | |
2131 | is to rotate the word so that the middle ^^^^^^ group of zeros | |
2132 | is at the MS end and can be cleared with an rldicl mask. We then | |
2133 | rotate back and clear off the MS ^^ group of zeros with a | |
2134 | second rldicl. */ | |
2135 | c = ~c; /* c == 0xff000ffffff00000 */ | |
2136 | lsb = c & -c; /* lsb == 0x0000000000100000 */ | |
2137 | m1 = -lsb; /* m1 == 0xfffffffffff00000 */ | |
2138 | c = ~c; /* c == 0x00fff000000fffff */ | |
2139 | c &= -lsb; /* c == 0x00fff00000000000 */ | |
2140 | lsb = c & -c; /* lsb == 0x0000100000000000 */ | |
2141 | c = ~c; /* c == 0xff000fffffffffff */ | |
2142 | c &= -lsb; /* c == 0xff00000000000000 */ | |
2143 | shift = 0; | |
2144 | while ((lsb >>= 1) != 0) | |
2145 | shift++; /* shift == 44 on exit from loop */ | |
2146 | m1 <<= 64 - shift; /* m1 == 0xffffff0000000000 */ | |
2147 | m1 = ~m1; /* m1 == 0x000000ffffffffff */ | |
2148 | m2 = ~c; /* m2 == 0x00ffffffffffffff */ | |
a260abc9 DE |
2149 | } |
2150 | else | |
0ba1b2ff AM |
2151 | { |
2152 | /* Assume c initially something like 0xff000f0000000000. The idea | |
2153 | is to rotate the word so that the ^^^ middle group of zeros | |
2154 | is at the LS end and can be cleared with an rldicr mask. We then | |
2155 | rotate back and clear off the LS group of ^^^^^^^^^^ zeros with | |
2156 | a second rldicr. */ | |
2157 | lsb = c & -c; /* lsb == 0x0000010000000000 */ | |
2158 | m2 = -lsb; /* m2 == 0xffffff0000000000 */ | |
2159 | c = ~c; /* c == 0x00fff0ffffffffff */ | |
2160 | c &= -lsb; /* c == 0x00fff00000000000 */ | |
2161 | lsb = c & -c; /* lsb == 0x0000100000000000 */ | |
2162 | c = ~c; /* c == 0xff000fffffffffff */ | |
2163 | c &= -lsb; /* c == 0xff00000000000000 */ | |
2164 | shift = 0; | |
2165 | while ((lsb >>= 1) != 0) | |
2166 | shift++; /* shift == 44 on exit from loop */ | |
2167 | m1 = ~c; /* m1 == 0x00ffffffffffffff */ | |
2168 | m1 >>= shift; /* m1 == 0x0000000000000fff */ | |
2169 | m1 = ~m1; /* m1 == 0xfffffffffffff000 */ | |
2170 | } | |
2171 | ||
2172 | /* Note that when we only have two 0->1 and 1->0 transitions, one of the | |
2173 | masks will be all 1's. We are guaranteed more than one transition. */ | |
2174 | out[0] = GEN_INT (64 - shift); | |
2175 | out[1] = GEN_INT (m1); | |
2176 | out[2] = GEN_INT (shift); | |
2177 | out[3] = GEN_INT (m2); | |
2178 | #else | |
045572c7 GK |
2179 | (void)in; |
2180 | (void)out; | |
37409796 | 2181 | gcc_unreachable (); |
0ba1b2ff | 2182 | #endif |
a260abc9 DE |
2183 | } |
2184 | ||
54b695e7 | 2185 | /* Return TRUE if OP is an invalid SUBREG operation on the e500. */ |
48d72335 DE |
2186 | |
2187 | bool | |
54b695e7 AH |
2188 | invalid_e500_subreg (rtx op, enum machine_mode mode) |
2189 | { | |
2190 | /* Reject (subreg:SI (reg:DF)). */ | |
2191 | if (GET_CODE (op) == SUBREG | |
2192 | && mode == SImode | |
2193 | && REG_P (SUBREG_REG (op)) | |
2194 | && GET_MODE (SUBREG_REG (op)) == DFmode) | |
2195 | return true; | |
2196 | ||
2197 | /* Reject (subreg:DF (reg:DI)). */ | |
2198 | if (GET_CODE (op) == SUBREG | |
2199 | && mode == DFmode | |
2200 | && REG_P (SUBREG_REG (op)) | |
2201 | && GET_MODE (SUBREG_REG (op)) == DImode) | |
2202 | return true; | |
2203 | ||
2204 | return false; | |
2205 | } | |
2206 | ||
95727fb8 AP |
2207 | /* Darwin, AIX increases natural record alignment to doubleword if the first |
2208 | field is an FP double while the FP fields remain word aligned. */ | |
2209 | ||
19d66194 | 2210 | unsigned int |
95727fb8 AP |
2211 | rs6000_special_round_type_align (tree type, int computed, int specified) |
2212 | { | |
2213 | tree field = TYPE_FIELDS (type); | |
95727fb8 | 2214 | |
85962ac8 AP |
2215 | /* Skip all non field decls */ |
2216 | while (field != NULL && TREE_CODE (field) != FIELD_DECL) | |
95727fb8 AP |
2217 | field = TREE_CHAIN (field); |
2218 | ||
3ce5437a | 2219 | if (field == NULL || field == type || DECL_MODE (field) != DFmode) |
95727fb8 AP |
2220 | return MAX (computed, specified); |
2221 | ||
2222 | return MAX (MAX (computed, specified), 64); | |
2223 | } | |
2224 | ||
a4f6c312 | 2225 | /* Return 1 for an operand in small memory on V.4/eabi. */ |
7509c759 MM |
2226 | |
2227 | int | |
f676971a | 2228 | small_data_operand (rtx op ATTRIBUTE_UNUSED, |
a2369ed3 | 2229 | enum machine_mode mode ATTRIBUTE_UNUSED) |
7509c759 | 2230 | { |
38c1f2d7 | 2231 | #if TARGET_ELF |
5f59ecb7 | 2232 | rtx sym_ref; |
7509c759 | 2233 | |
d9407988 | 2234 | if (rs6000_sdata == SDATA_NONE || rs6000_sdata == SDATA_DATA) |
a54d04b7 | 2235 | return 0; |
a54d04b7 | 2236 | |
f607bc57 | 2237 | if (DEFAULT_ABI != ABI_V4) |
7509c759 MM |
2238 | return 0; |
2239 | ||
88228c4b MM |
2240 | if (GET_CODE (op) == SYMBOL_REF) |
2241 | sym_ref = op; | |
2242 | ||
2243 | else if (GET_CODE (op) != CONST | |
2244 | || GET_CODE (XEXP (op, 0)) != PLUS | |
2245 | || GET_CODE (XEXP (XEXP (op, 0), 0)) != SYMBOL_REF | |
2246 | || GET_CODE (XEXP (XEXP (op, 0), 1)) != CONST_INT) | |
7509c759 MM |
2247 | return 0; |
2248 | ||
88228c4b | 2249 | else |
dbf55e53 MM |
2250 | { |
2251 | rtx sum = XEXP (op, 0); | |
2252 | HOST_WIDE_INT summand; | |
2253 | ||
2254 | /* We have to be careful here, because it is the referenced address | |
c4ad648e | 2255 | that must be 32k from _SDA_BASE_, not just the symbol. */ |
dbf55e53 | 2256 | summand = INTVAL (XEXP (sum, 1)); |
307b599c | 2257 | if (summand < 0 || (unsigned HOST_WIDE_INT) summand > g_switch_value) |
9390387d | 2258 | return 0; |
dbf55e53 MM |
2259 | |
2260 | sym_ref = XEXP (sum, 0); | |
2261 | } | |
88228c4b | 2262 | |
20bfcd69 | 2263 | return SYMBOL_REF_SMALL_P (sym_ref); |
d9407988 MM |
2264 | #else |
2265 | return 0; | |
2266 | #endif | |
7509c759 | 2267 | } |
46c07df8 | 2268 | |
3a1f863f | 2269 | /* Return true if either operand is a general purpose register. */ |
46c07df8 | 2270 | |
3a1f863f DE |
2271 | bool |
2272 | gpr_or_gpr_p (rtx op0, rtx op1) | |
46c07df8 | 2273 | { |
3a1f863f DE |
2274 | return ((REG_P (op0) && INT_REGNO_P (REGNO (op0))) |
2275 | || (REG_P (op1) && INT_REGNO_P (REGNO (op1)))); | |
46c07df8 HP |
2276 | } |
2277 | ||
9ebbca7d | 2278 | \f |
4d588c14 RH |
2279 | /* Subroutines of rs6000_legitimize_address and rs6000_legitimate_address. */ |
2280 | ||
f676971a EC |
2281 | static int |
2282 | constant_pool_expr_1 (rtx op, int *have_sym, int *have_toc) | |
9ebbca7d | 2283 | { |
9390387d | 2284 | switch (GET_CODE (op)) |
9ebbca7d GK |
2285 | { |
2286 | case SYMBOL_REF: | |
c4501e62 JJ |
2287 | if (RS6000_SYMBOL_REF_TLS_P (op)) |
2288 | return 0; | |
2289 | else if (CONSTANT_POOL_ADDRESS_P (op)) | |
a4f6c312 SS |
2290 | { |
2291 | if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (op), Pmode)) | |
2292 | { | |
2293 | *have_sym = 1; | |
2294 | return 1; | |
2295 | } | |
2296 | else | |
2297 | return 0; | |
2298 | } | |
2299 | else if (! strcmp (XSTR (op, 0), toc_label_name)) | |
2300 | { | |
2301 | *have_toc = 1; | |
2302 | return 1; | |
2303 | } | |
2304 | else | |
2305 | return 0; | |
9ebbca7d GK |
2306 | case PLUS: |
2307 | case MINUS: | |
c1f11548 DE |
2308 | return (constant_pool_expr_1 (XEXP (op, 0), have_sym, have_toc) |
2309 | && constant_pool_expr_1 (XEXP (op, 1), have_sym, have_toc)); | |
9ebbca7d | 2310 | case CONST: |
a4f6c312 | 2311 | return constant_pool_expr_1 (XEXP (op, 0), have_sym, have_toc); |
9ebbca7d | 2312 | case CONST_INT: |
a4f6c312 | 2313 | return 1; |
9ebbca7d | 2314 | default: |
a4f6c312 | 2315 | return 0; |
9ebbca7d GK |
2316 | } |
2317 | } | |
2318 | ||
4d588c14 | 2319 | static bool |
a2369ed3 | 2320 | constant_pool_expr_p (rtx op) |
9ebbca7d GK |
2321 | { |
2322 | int have_sym = 0; | |
2323 | int have_toc = 0; | |
2324 | return constant_pool_expr_1 (op, &have_sym, &have_toc) && have_sym; | |
2325 | } | |
2326 | ||
48d72335 | 2327 | bool |
a2369ed3 | 2328 | toc_relative_expr_p (rtx op) |
9ebbca7d | 2329 | { |
4d588c14 RH |
2330 | int have_sym = 0; |
2331 | int have_toc = 0; | |
2332 | return constant_pool_expr_1 (op, &have_sym, &have_toc) && have_toc; | |
2333 | } | |
2334 | ||
4d588c14 | 2335 | bool |
a2369ed3 | 2336 | legitimate_constant_pool_address_p (rtx x) |
4d588c14 RH |
2337 | { |
2338 | return (TARGET_TOC | |
2339 | && GET_CODE (x) == PLUS | |
2340 | && GET_CODE (XEXP (x, 0)) == REG | |
2341 | && (TARGET_MINIMAL_TOC || REGNO (XEXP (x, 0)) == TOC_REGISTER) | |
2342 | && constant_pool_expr_p (XEXP (x, 1))); | |
2343 | } | |
2344 | ||
2345 | static bool | |
a2369ed3 | 2346 | legitimate_small_data_p (enum machine_mode mode, rtx x) |
4d588c14 RH |
2347 | { |
2348 | return (DEFAULT_ABI == ABI_V4 | |
2349 | && !flag_pic && !TARGET_TOC | |
2350 | && (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST) | |
2351 | && small_data_operand (x, mode)); | |
2352 | } | |
2353 | ||
60cdabab DE |
2354 | /* SPE offset addressing is limited to 5-bits worth of double words. */ |
2355 | #define SPE_CONST_OFFSET_OK(x) (((x) & ~0xf8) == 0) | |
2356 | ||
76d2b81d DJ |
2357 | bool |
2358 | rs6000_legitimate_offset_address_p (enum machine_mode mode, rtx x, int strict) | |
4d588c14 RH |
2359 | { |
2360 | unsigned HOST_WIDE_INT offset, extra; | |
2361 | ||
2362 | if (GET_CODE (x) != PLUS) | |
2363 | return false; | |
2364 | if (GET_CODE (XEXP (x, 0)) != REG) | |
2365 | return false; | |
2366 | if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict)) | |
2367 | return false; | |
60cdabab DE |
2368 | if (legitimate_constant_pool_address_p (x)) |
2369 | return true; | |
4d588c14 RH |
2370 | if (GET_CODE (XEXP (x, 1)) != CONST_INT) |
2371 | return false; | |
2372 | ||
2373 | offset = INTVAL (XEXP (x, 1)); | |
2374 | extra = 0; | |
2375 | switch (mode) | |
2376 | { | |
2377 | case V16QImode: | |
2378 | case V8HImode: | |
2379 | case V4SFmode: | |
2380 | case V4SImode: | |
2381 | /* AltiVec vector modes. Only reg+reg addressing is valid here, | |
2382 | which leaves the only valid constant offset of zero, which by | |
2383 | canonicalization rules is also invalid. */ | |
2384 | return false; | |
2385 | ||
2386 | case V4HImode: | |
2387 | case V2SImode: | |
2388 | case V1DImode: | |
2389 | case V2SFmode: | |
2390 | /* SPE vector modes. */ | |
2391 | return SPE_CONST_OFFSET_OK (offset); | |
2392 | ||
2393 | case DFmode: | |
4d4cbc0e AH |
2394 | if (TARGET_E500_DOUBLE) |
2395 | return SPE_CONST_OFFSET_OK (offset); | |
2396 | ||
4d588c14 | 2397 | case DImode: |
54b695e7 AH |
2398 | /* On e500v2, we may have: |
2399 | ||
2400 | (subreg:DF (mem:DI (plus (reg) (const_int))) 0). | |
2401 | ||
2402 | Which gets addressed with evldd instructions. */ | |
2403 | if (TARGET_E500_DOUBLE) | |
2404 | return SPE_CONST_OFFSET_OK (offset); | |
2405 | ||
3364872d | 2406 | if (mode == DFmode || !TARGET_POWERPC64) |
4d588c14 RH |
2407 | extra = 4; |
2408 | else if (offset & 3) | |
2409 | return false; | |
2410 | break; | |
2411 | ||
2412 | case TFmode: | |
2413 | case TImode: | |
3364872d | 2414 | if (mode == TFmode || !TARGET_POWERPC64) |
4d588c14 RH |
2415 | extra = 12; |
2416 | else if (offset & 3) | |
2417 | return false; | |
2418 | else | |
2419 | extra = 8; | |
2420 | break; | |
2421 | ||
2422 | default: | |
2423 | break; | |
2424 | } | |
2425 | ||
b1917422 AM |
2426 | offset += 0x8000; |
2427 | return (offset < 0x10000) && (offset + extra < 0x10000); | |
4d588c14 RH |
2428 | } |
2429 | ||
2430 | static bool | |
a2369ed3 | 2431 | legitimate_indexed_address_p (rtx x, int strict) |
4d588c14 RH |
2432 | { |
2433 | rtx op0, op1; | |
2434 | ||
2435 | if (GET_CODE (x) != PLUS) | |
2436 | return false; | |
850e8d3d | 2437 | |
4d588c14 RH |
2438 | op0 = XEXP (x, 0); |
2439 | op1 = XEXP (x, 1); | |
2440 | ||
2441 | if (!REG_P (op0) || !REG_P (op1)) | |
2442 | return false; | |
2443 | ||
2444 | return ((INT_REG_OK_FOR_BASE_P (op0, strict) | |
2445 | && INT_REG_OK_FOR_INDEX_P (op1, strict)) | |
2446 | || (INT_REG_OK_FOR_BASE_P (op1, strict) | |
2447 | && INT_REG_OK_FOR_INDEX_P (op0, strict))); | |
9ebbca7d GK |
2448 | } |
2449 | ||
48d72335 | 2450 | inline bool |
a2369ed3 | 2451 | legitimate_indirect_address_p (rtx x, int strict) |
4d588c14 RH |
2452 | { |
2453 | return GET_CODE (x) == REG && INT_REG_OK_FOR_BASE_P (x, strict); | |
2454 | } | |
2455 | ||
48d72335 | 2456 | bool |
4c81e946 FJ |
2457 | macho_lo_sum_memory_operand (rtx x, enum machine_mode mode) |
2458 | { | |
c4ad648e | 2459 | if (!TARGET_MACHO || !flag_pic |
9390387d | 2460 | || mode != SImode || GET_CODE (x) != MEM) |
c4ad648e AM |
2461 | return false; |
2462 | x = XEXP (x, 0); | |
4c81e946 FJ |
2463 | |
2464 | if (GET_CODE (x) != LO_SUM) | |
2465 | return false; | |
2466 | if (GET_CODE (XEXP (x, 0)) != REG) | |
2467 | return false; | |
2468 | if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), 0)) | |
2469 | return false; | |
2470 | x = XEXP (x, 1); | |
2471 | ||
2472 | return CONSTANT_P (x); | |
2473 | } | |
2474 | ||
4d588c14 | 2475 | static bool |
a2369ed3 | 2476 | legitimate_lo_sum_address_p (enum machine_mode mode, rtx x, int strict) |
4d588c14 RH |
2477 | { |
2478 | if (GET_CODE (x) != LO_SUM) | |
2479 | return false; | |
2480 | if (GET_CODE (XEXP (x, 0)) != REG) | |
2481 | return false; | |
2482 | if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict)) | |
2483 | return false; | |
54b695e7 AH |
2484 | /* Restrict addressing for DI because of our SUBREG hackery. */ |
2485 | if (TARGET_E500_DOUBLE && (mode == DFmode || mode == DImode)) | |
f82f556d | 2486 | return false; |
4d588c14 RH |
2487 | x = XEXP (x, 1); |
2488 | ||
8622e235 | 2489 | if (TARGET_ELF || TARGET_MACHO) |
4d588c14 | 2490 | { |
a29077da | 2491 | if (DEFAULT_ABI != ABI_AIX && DEFAULT_ABI != ABI_DARWIN && flag_pic) |
4d588c14 RH |
2492 | return false; |
2493 | if (TARGET_TOC) | |
2494 | return false; | |
2495 | if (GET_MODE_NUNITS (mode) != 1) | |
2496 | return false; | |
5e5f01b9 | 2497 | if (GET_MODE_BITSIZE (mode) > 64 |
3c028f65 AM |
2498 | || (GET_MODE_BITSIZE (mode) > 32 && !TARGET_POWERPC64 |
2499 | && !(TARGET_HARD_FLOAT && TARGET_FPRS && mode == DFmode))) | |
4d588c14 RH |
2500 | return false; |
2501 | ||
2502 | return CONSTANT_P (x); | |
2503 | } | |
2504 | ||
2505 | return false; | |
2506 | } | |
2507 | ||
2508 | ||
9ebbca7d GK |
2509 | /* Try machine-dependent ways of modifying an illegitimate address |
2510 | to be legitimate. If we find one, return the new, valid address. | |
2511 | This is used from only one place: `memory_address' in explow.c. | |
2512 | ||
a4f6c312 SS |
2513 | OLDX is the address as it was before break_out_memory_refs was |
2514 | called. In some cases it is useful to look at this to decide what | |
2515 | needs to be done. | |
9ebbca7d | 2516 | |
a4f6c312 | 2517 | MODE is passed so that this function can use GO_IF_LEGITIMATE_ADDRESS. |
9ebbca7d | 2518 | |
a4f6c312 SS |
2519 | It is always safe for this function to do nothing. It exists to |
2520 | recognize opportunities to optimize the output. | |
9ebbca7d GK |
2521 | |
2522 | On RS/6000, first check for the sum of a register with a constant | |
2523 | integer that is out of range. If so, generate code to add the | |
2524 | constant with the low-order 16 bits masked to the register and force | |
2525 | this result into another register (this can be done with `cau'). | |
2526 | Then generate an address of REG+(CONST&0xffff), allowing for the | |
2527 | possibility of bit 16 being a one. | |
2528 | ||
2529 | Then check for the sum of a register and something not constant, try to | |
2530 | load the other things into a register and return the sum. */ | |
4d588c14 | 2531 | |
9ebbca7d | 2532 | rtx |
a2369ed3 DJ |
2533 | rs6000_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED, |
2534 | enum machine_mode mode) | |
0ac081f6 | 2535 | { |
c4501e62 JJ |
2536 | if (GET_CODE (x) == SYMBOL_REF) |
2537 | { | |
2538 | enum tls_model model = SYMBOL_REF_TLS_MODEL (x); | |
2539 | if (model != 0) | |
2540 | return rs6000_legitimize_tls_address (x, model); | |
2541 | } | |
2542 | ||
f676971a | 2543 | if (GET_CODE (x) == PLUS |
9ebbca7d GK |
2544 | && GET_CODE (XEXP (x, 0)) == REG |
2545 | && GET_CODE (XEXP (x, 1)) == CONST_INT | |
2546 | && (unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 1)) + 0x8000) >= 0x10000) | |
f676971a | 2547 | { |
9ebbca7d GK |
2548 | HOST_WIDE_INT high_int, low_int; |
2549 | rtx sum; | |
a65c591c DE |
2550 | low_int = ((INTVAL (XEXP (x, 1)) & 0xffff) ^ 0x8000) - 0x8000; |
2551 | high_int = INTVAL (XEXP (x, 1)) - low_int; | |
9ebbca7d GK |
2552 | sum = force_operand (gen_rtx_PLUS (Pmode, XEXP (x, 0), |
2553 | GEN_INT (high_int)), 0); | |
2554 | return gen_rtx_PLUS (Pmode, sum, GEN_INT (low_int)); | |
2555 | } | |
f676971a | 2556 | else if (GET_CODE (x) == PLUS |
9ebbca7d GK |
2557 | && GET_CODE (XEXP (x, 0)) == REG |
2558 | && GET_CODE (XEXP (x, 1)) != CONST_INT | |
6ac7bf2c | 2559 | && GET_MODE_NUNITS (mode) == 1 |
a3170dc6 AH |
2560 | && ((TARGET_HARD_FLOAT && TARGET_FPRS) |
2561 | || TARGET_POWERPC64 | |
54b695e7 AH |
2562 | || (((mode != DImode && mode != DFmode) || TARGET_E500_DOUBLE) |
2563 | && mode != TFmode)) | |
9ebbca7d GK |
2564 | && (TARGET_POWERPC64 || mode != DImode) |
2565 | && mode != TImode) | |
2566 | { | |
2567 | return gen_rtx_PLUS (Pmode, XEXP (x, 0), | |
2568 | force_reg (Pmode, force_operand (XEXP (x, 1), 0))); | |
2569 | } | |
0ac081f6 AH |
2570 | else if (ALTIVEC_VECTOR_MODE (mode)) |
2571 | { | |
2572 | rtx reg; | |
2573 | ||
2574 | /* Make sure both operands are registers. */ | |
2575 | if (GET_CODE (x) == PLUS) | |
9f85ed45 | 2576 | return gen_rtx_PLUS (Pmode, force_reg (Pmode, XEXP (x, 0)), |
0ac081f6 AH |
2577 | force_reg (Pmode, XEXP (x, 1))); |
2578 | ||
2579 | reg = force_reg (Pmode, x); | |
2580 | return reg; | |
2581 | } | |
4d4cbc0e | 2582 | else if (SPE_VECTOR_MODE (mode) |
54b695e7 AH |
2583 | || (TARGET_E500_DOUBLE && (mode == DFmode |
2584 | || mode == DImode))) | |
a3170dc6 | 2585 | { |
54b695e7 AH |
2586 | if (mode == DImode) |
2587 | return NULL_RTX; | |
a3170dc6 AH |
2588 | /* We accept [reg + reg] and [reg + OFFSET]. */ |
2589 | ||
2590 | if (GET_CODE (x) == PLUS) | |
c4ad648e AM |
2591 | { |
2592 | rtx op1 = XEXP (x, 0); | |
2593 | rtx op2 = XEXP (x, 1); | |
a3170dc6 | 2594 | |
c4ad648e | 2595 | op1 = force_reg (Pmode, op1); |
a3170dc6 | 2596 | |
c4ad648e AM |
2597 | if (GET_CODE (op2) != REG |
2598 | && (GET_CODE (op2) != CONST_INT | |
2599 | || !SPE_CONST_OFFSET_OK (INTVAL (op2)))) | |
2600 | op2 = force_reg (Pmode, op2); | |
a3170dc6 | 2601 | |
c4ad648e AM |
2602 | return gen_rtx_PLUS (Pmode, op1, op2); |
2603 | } | |
a3170dc6 AH |
2604 | |
2605 | return force_reg (Pmode, x); | |
2606 | } | |
f1384257 AM |
2607 | else if (TARGET_ELF |
2608 | && TARGET_32BIT | |
2609 | && TARGET_NO_TOC | |
2610 | && ! flag_pic | |
9ebbca7d | 2611 | && GET_CODE (x) != CONST_INT |
f676971a | 2612 | && GET_CODE (x) != CONST_DOUBLE |
9ebbca7d | 2613 | && CONSTANT_P (x) |
6ac7bf2c GK |
2614 | && GET_MODE_NUNITS (mode) == 1 |
2615 | && (GET_MODE_BITSIZE (mode) <= 32 | |
a3170dc6 | 2616 | || ((TARGET_HARD_FLOAT && TARGET_FPRS) && mode == DFmode))) |
9ebbca7d GK |
2617 | { |
2618 | rtx reg = gen_reg_rtx (Pmode); | |
8a1977f3 GK |
2619 | emit_insn (gen_elf_high (reg, x)); |
2620 | return gen_rtx_LO_SUM (Pmode, reg, x); | |
9ebbca7d | 2621 | } |
ee890fe2 SS |
2622 | else if (TARGET_MACHO && TARGET_32BIT && TARGET_NO_TOC |
2623 | && ! flag_pic | |
ab82a49f AP |
2624 | #if TARGET_MACHO |
2625 | && ! MACHO_DYNAMIC_NO_PIC_P | |
2626 | #endif | |
ee890fe2 | 2627 | && GET_CODE (x) != CONST_INT |
f676971a | 2628 | && GET_CODE (x) != CONST_DOUBLE |
ee890fe2 | 2629 | && CONSTANT_P (x) |
f82f556d | 2630 | && ((TARGET_HARD_FLOAT && TARGET_FPRS) || mode != DFmode) |
f676971a | 2631 | && mode != DImode |
ee890fe2 SS |
2632 | && mode != TImode) |
2633 | { | |
2634 | rtx reg = gen_reg_rtx (Pmode); | |
8a1977f3 GK |
2635 | emit_insn (gen_macho_high (reg, x)); |
2636 | return gen_rtx_LO_SUM (Pmode, reg, x); | |
ee890fe2 | 2637 | } |
f676971a | 2638 | else if (TARGET_TOC |
4d588c14 | 2639 | && constant_pool_expr_p (x) |
a9098fd0 | 2640 | && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x), Pmode)) |
9ebbca7d GK |
2641 | { |
2642 | return create_TOC_reference (x); | |
2643 | } | |
2644 | else | |
2645 | return NULL_RTX; | |
2646 | } | |
258bfae2 | 2647 | |
c973d557 JJ |
2648 | /* This is called from dwarf2out.c via ASM_OUTPUT_DWARF_DTPREL. |
2649 | We need to emit DTP-relative relocations. */ | |
2650 | ||
2651 | void | |
2652 | rs6000_output_dwarf_dtprel (FILE *file, int size, rtx x) | |
2653 | { | |
2654 | switch (size) | |
2655 | { | |
2656 | case 4: | |
2657 | fputs ("\t.long\t", file); | |
2658 | break; | |
2659 | case 8: | |
2660 | fputs (DOUBLE_INT_ASM_OP, file); | |
2661 | break; | |
2662 | default: | |
37409796 | 2663 | gcc_unreachable (); |
c973d557 JJ |
2664 | } |
2665 | output_addr_const (file, x); | |
2666 | fputs ("@dtprel+0x8000", file); | |
2667 | } | |
2668 | ||
c4501e62 JJ |
2669 | /* Construct the SYMBOL_REF for the tls_get_addr function. */ |
2670 | ||
2671 | static GTY(()) rtx rs6000_tls_symbol; | |
2672 | static rtx | |
863d938c | 2673 | rs6000_tls_get_addr (void) |
c4501e62 JJ |
2674 | { |
2675 | if (!rs6000_tls_symbol) | |
2676 | rs6000_tls_symbol = init_one_libfunc ("__tls_get_addr"); | |
2677 | ||
2678 | return rs6000_tls_symbol; | |
2679 | } | |
2680 | ||
2681 | /* Construct the SYMBOL_REF for TLS GOT references. */ | |
2682 | ||
2683 | static GTY(()) rtx rs6000_got_symbol; | |
2684 | static rtx | |
863d938c | 2685 | rs6000_got_sym (void) |
c4501e62 JJ |
2686 | { |
2687 | if (!rs6000_got_symbol) | |
2688 | { | |
2689 | rs6000_got_symbol = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_"); | |
2690 | SYMBOL_REF_FLAGS (rs6000_got_symbol) |= SYMBOL_FLAG_LOCAL; | |
2691 | SYMBOL_REF_FLAGS (rs6000_got_symbol) |= SYMBOL_FLAG_EXTERNAL; | |
f676971a | 2692 | } |
c4501e62 JJ |
2693 | |
2694 | return rs6000_got_symbol; | |
2695 | } | |
2696 | ||
2697 | /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute | |
2698 | this (thread-local) address. */ | |
2699 | ||
2700 | static rtx | |
a2369ed3 | 2701 | rs6000_legitimize_tls_address (rtx addr, enum tls_model model) |
c4501e62 JJ |
2702 | { |
2703 | rtx dest, insn; | |
2704 | ||
2705 | dest = gen_reg_rtx (Pmode); | |
2706 | if (model == TLS_MODEL_LOCAL_EXEC && rs6000_tls_size == 16) | |
2707 | { | |
2708 | rtx tlsreg; | |
2709 | ||
2710 | if (TARGET_64BIT) | |
2711 | { | |
2712 | tlsreg = gen_rtx_REG (Pmode, 13); | |
2713 | insn = gen_tls_tprel_64 (dest, tlsreg, addr); | |
2714 | } | |
2715 | else | |
2716 | { | |
2717 | tlsreg = gen_rtx_REG (Pmode, 2); | |
2718 | insn = gen_tls_tprel_32 (dest, tlsreg, addr); | |
2719 | } | |
2720 | emit_insn (insn); | |
2721 | } | |
2722 | else if (model == TLS_MODEL_LOCAL_EXEC && rs6000_tls_size == 32) | |
2723 | { | |
2724 | rtx tlsreg, tmp; | |
2725 | ||
2726 | tmp = gen_reg_rtx (Pmode); | |
2727 | if (TARGET_64BIT) | |
2728 | { | |
2729 | tlsreg = gen_rtx_REG (Pmode, 13); | |
2730 | insn = gen_tls_tprel_ha_64 (tmp, tlsreg, addr); | |
2731 | } | |
2732 | else | |
2733 | { | |
2734 | tlsreg = gen_rtx_REG (Pmode, 2); | |
2735 | insn = gen_tls_tprel_ha_32 (tmp, tlsreg, addr); | |
2736 | } | |
2737 | emit_insn (insn); | |
2738 | if (TARGET_64BIT) | |
2739 | insn = gen_tls_tprel_lo_64 (dest, tmp, addr); | |
2740 | else | |
2741 | insn = gen_tls_tprel_lo_32 (dest, tmp, addr); | |
2742 | emit_insn (insn); | |
2743 | } | |
2744 | else | |
2745 | { | |
2746 | rtx r3, got, tga, tmp1, tmp2, eqv; | |
2747 | ||
2748 | if (TARGET_64BIT) | |
2749 | got = gen_rtx_REG (Pmode, TOC_REGISTER); | |
2750 | else | |
2751 | { | |
2752 | if (flag_pic == 1) | |
2753 | got = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM); | |
2754 | else | |
2755 | { | |
2756 | rtx gsym = rs6000_got_sym (); | |
2757 | got = gen_reg_rtx (Pmode); | |
2758 | if (flag_pic == 0) | |
2759 | rs6000_emit_move (got, gsym, Pmode); | |
2760 | else | |
2761 | { | |
ccbca5e4 | 2762 | rtx tempLR, tmp3, mem; |
c4501e62 JJ |
2763 | rtx first, last; |
2764 | ||
c4501e62 JJ |
2765 | tempLR = gen_reg_rtx (Pmode); |
2766 | tmp1 = gen_reg_rtx (Pmode); | |
2767 | tmp2 = gen_reg_rtx (Pmode); | |
2768 | tmp3 = gen_reg_rtx (Pmode); | |
542a8afa | 2769 | mem = gen_const_mem (Pmode, tmp1); |
c4501e62 | 2770 | |
ccbca5e4 | 2771 | first = emit_insn (gen_load_toc_v4_PIC_1b (tempLR, gsym)); |
c4501e62 JJ |
2772 | emit_move_insn (tmp1, tempLR); |
2773 | emit_move_insn (tmp2, mem); | |
2774 | emit_insn (gen_addsi3 (tmp3, tmp1, tmp2)); | |
2775 | last = emit_move_insn (got, tmp3); | |
2776 | REG_NOTES (last) = gen_rtx_EXPR_LIST (REG_EQUAL, gsym, | |
2777 | REG_NOTES (last)); | |
2778 | REG_NOTES (first) = gen_rtx_INSN_LIST (REG_LIBCALL, last, | |
2779 | REG_NOTES (first)); | |
2780 | REG_NOTES (last) = gen_rtx_INSN_LIST (REG_RETVAL, first, | |
2781 | REG_NOTES (last)); | |
2782 | } | |
2783 | } | |
2784 | } | |
2785 | ||
2786 | if (model == TLS_MODEL_GLOBAL_DYNAMIC) | |
2787 | { | |
2788 | r3 = gen_rtx_REG (Pmode, 3); | |
2789 | if (TARGET_64BIT) | |
2790 | insn = gen_tls_gd_64 (r3, got, addr); | |
2791 | else | |
2792 | insn = gen_tls_gd_32 (r3, got, addr); | |
2793 | start_sequence (); | |
2794 | emit_insn (insn); | |
2795 | tga = gen_rtx_MEM (Pmode, rs6000_tls_get_addr ()); | |
2796 | insn = gen_call_value (r3, tga, const0_rtx, const0_rtx); | |
2797 | insn = emit_call_insn (insn); | |
2798 | CONST_OR_PURE_CALL_P (insn) = 1; | |
2799 | use_reg (&CALL_INSN_FUNCTION_USAGE (insn), r3); | |
2800 | insn = get_insns (); | |
2801 | end_sequence (); | |
2802 | emit_libcall_block (insn, dest, r3, addr); | |
2803 | } | |
2804 | else if (model == TLS_MODEL_LOCAL_DYNAMIC) | |
2805 | { | |
2806 | r3 = gen_rtx_REG (Pmode, 3); | |
2807 | if (TARGET_64BIT) | |
2808 | insn = gen_tls_ld_64 (r3, got); | |
2809 | else | |
2810 | insn = gen_tls_ld_32 (r3, got); | |
2811 | start_sequence (); | |
2812 | emit_insn (insn); | |
2813 | tga = gen_rtx_MEM (Pmode, rs6000_tls_get_addr ()); | |
2814 | insn = gen_call_value (r3, tga, const0_rtx, const0_rtx); | |
2815 | insn = emit_call_insn (insn); | |
2816 | CONST_OR_PURE_CALL_P (insn) = 1; | |
2817 | use_reg (&CALL_INSN_FUNCTION_USAGE (insn), r3); | |
2818 | insn = get_insns (); | |
2819 | end_sequence (); | |
2820 | tmp1 = gen_reg_rtx (Pmode); | |
2821 | eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), | |
2822 | UNSPEC_TLSLD); | |
2823 | emit_libcall_block (insn, tmp1, r3, eqv); | |
2824 | if (rs6000_tls_size == 16) | |
2825 | { | |
2826 | if (TARGET_64BIT) | |
2827 | insn = gen_tls_dtprel_64 (dest, tmp1, addr); | |
2828 | else | |
2829 | insn = gen_tls_dtprel_32 (dest, tmp1, addr); | |
2830 | } | |
2831 | else if (rs6000_tls_size == 32) | |
2832 | { | |
2833 | tmp2 = gen_reg_rtx (Pmode); | |
2834 | if (TARGET_64BIT) | |
2835 | insn = gen_tls_dtprel_ha_64 (tmp2, tmp1, addr); | |
2836 | else | |
2837 | insn = gen_tls_dtprel_ha_32 (tmp2, tmp1, addr); | |
2838 | emit_insn (insn); | |
2839 | if (TARGET_64BIT) | |
2840 | insn = gen_tls_dtprel_lo_64 (dest, tmp2, addr); | |
2841 | else | |
2842 | insn = gen_tls_dtprel_lo_32 (dest, tmp2, addr); | |
2843 | } | |
2844 | else | |
2845 | { | |
2846 | tmp2 = gen_reg_rtx (Pmode); | |
2847 | if (TARGET_64BIT) | |
2848 | insn = gen_tls_got_dtprel_64 (tmp2, got, addr); | |
2849 | else | |
2850 | insn = gen_tls_got_dtprel_32 (tmp2, got, addr); | |
2851 | emit_insn (insn); | |
2852 | insn = gen_rtx_SET (Pmode, dest, | |
2853 | gen_rtx_PLUS (Pmode, tmp2, tmp1)); | |
2854 | } | |
2855 | emit_insn (insn); | |
2856 | } | |
2857 | else | |
2858 | { | |
2859 | /* IE, or 64 bit offset LE. */ | |
2860 | tmp2 = gen_reg_rtx (Pmode); | |
2861 | if (TARGET_64BIT) | |
2862 | insn = gen_tls_got_tprel_64 (tmp2, got, addr); | |
2863 | else | |
2864 | insn = gen_tls_got_tprel_32 (tmp2, got, addr); | |
2865 | emit_insn (insn); | |
2866 | if (TARGET_64BIT) | |
2867 | insn = gen_tls_tls_64 (dest, tmp2, addr); | |
2868 | else | |
2869 | insn = gen_tls_tls_32 (dest, tmp2, addr); | |
2870 | emit_insn (insn); | |
2871 | } | |
2872 | } | |
2873 | ||
2874 | return dest; | |
2875 | } | |
2876 | ||
c4501e62 JJ |
2877 | /* Return 1 if X contains a thread-local symbol. */ |
2878 | ||
2879 | bool | |
a2369ed3 | 2880 | rs6000_tls_referenced_p (rtx x) |
c4501e62 | 2881 | { |
cd413cab AP |
2882 | if (! TARGET_HAVE_TLS) |
2883 | return false; | |
2884 | ||
c4501e62 JJ |
2885 | return for_each_rtx (&x, &rs6000_tls_symbol_ref_1, 0); |
2886 | } | |
2887 | ||
2888 | /* Return 1 if *X is a thread-local symbol. This is the same as | |
2889 | rs6000_tls_symbol_ref except for the type of the unused argument. */ | |
2890 | ||
9390387d | 2891 | static int |
a2369ed3 | 2892 | rs6000_tls_symbol_ref_1 (rtx *x, void *data ATTRIBUTE_UNUSED) |
c4501e62 JJ |
2893 | { |
2894 | return RS6000_SYMBOL_REF_TLS_P (*x); | |
2895 | } | |
2896 | ||
24ea750e DJ |
2897 | /* The convention appears to be to define this wherever it is used. |
2898 | With legitimize_reload_address now defined here, REG_MODE_OK_FOR_BASE_P | |
2899 | is now used here. */ | |
2900 | #ifndef REG_MODE_OK_FOR_BASE_P | |
2901 | #define REG_MODE_OK_FOR_BASE_P(REGNO, MODE) REG_OK_FOR_BASE_P (REGNO) | |
2902 | #endif | |
2903 | ||
2904 | /* Our implementation of LEGITIMIZE_RELOAD_ADDRESS. Returns a value to | |
2905 | replace the input X, or the original X if no replacement is called for. | |
2906 | The output parameter *WIN is 1 if the calling macro should goto WIN, | |
2907 | 0 if it should not. | |
2908 | ||
2909 | For RS/6000, we wish to handle large displacements off a base | |
2910 | register by splitting the addend across an addiu/addis and the mem insn. | |
2911 | This cuts number of extra insns needed from 3 to 1. | |
2912 | ||
2913 | On Darwin, we use this to generate code for floating point constants. | |
2914 | A movsf_low is generated so we wind up with 2 instructions rather than 3. | |
2915 | The Darwin code is inside #if TARGET_MACHO because only then is | |
2916 | machopic_function_base_name() defined. */ | |
2917 | rtx | |
f676971a | 2918 | rs6000_legitimize_reload_address (rtx x, enum machine_mode mode, |
c4ad648e AM |
2919 | int opnum, int type, |
2920 | int ind_levels ATTRIBUTE_UNUSED, int *win) | |
24ea750e | 2921 | { |
f676971a | 2922 | /* We must recognize output that we have already generated ourselves. */ |
24ea750e DJ |
2923 | if (GET_CODE (x) == PLUS |
2924 | && GET_CODE (XEXP (x, 0)) == PLUS | |
2925 | && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG | |
2926 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT | |
2927 | && GET_CODE (XEXP (x, 1)) == CONST_INT) | |
2928 | { | |
2929 | push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL, | |
c4ad648e AM |
2930 | BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0, |
2931 | opnum, (enum reload_type)type); | |
24ea750e DJ |
2932 | *win = 1; |
2933 | return x; | |
2934 | } | |
3deb2758 | 2935 | |
24ea750e DJ |
2936 | #if TARGET_MACHO |
2937 | if (DEFAULT_ABI == ABI_DARWIN && flag_pic | |
2938 | && GET_CODE (x) == LO_SUM | |
2939 | && GET_CODE (XEXP (x, 0)) == PLUS | |
2940 | && XEXP (XEXP (x, 0), 0) == pic_offset_table_rtx | |
2941 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == HIGH | |
2942 | && GET_CODE (XEXP (XEXP (XEXP (x, 0), 1), 0)) == CONST | |
2943 | && XEXP (XEXP (XEXP (x, 0), 1), 0) == XEXP (x, 1) | |
2944 | && GET_CODE (XEXP (XEXP (x, 1), 0)) == MINUS | |
2945 | && GET_CODE (XEXP (XEXP (XEXP (x, 1), 0), 0)) == SYMBOL_REF | |
2946 | && GET_CODE (XEXP (XEXP (XEXP (x, 1), 0), 1)) == SYMBOL_REF) | |
2947 | { | |
2948 | /* Result of previous invocation of this function on Darwin | |
6f317ef3 | 2949 | floating point constant. */ |
24ea750e | 2950 | push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL, |
c4ad648e AM |
2951 | BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, |
2952 | opnum, (enum reload_type)type); | |
24ea750e DJ |
2953 | *win = 1; |
2954 | return x; | |
2955 | } | |
2956 | #endif | |
4937d02d DE |
2957 | |
2958 | /* Force ld/std non-word aligned offset into base register by wrapping | |
2959 | in offset 0. */ | |
2960 | if (GET_CODE (x) == PLUS | |
2961 | && GET_CODE (XEXP (x, 0)) == REG | |
2962 | && REGNO (XEXP (x, 0)) < 32 | |
2963 | && REG_MODE_OK_FOR_BASE_P (XEXP (x, 0), mode) | |
2964 | && GET_CODE (XEXP (x, 1)) == CONST_INT | |
2965 | && (INTVAL (XEXP (x, 1)) & 3) != 0 | |
78796ad5 | 2966 | && !ALTIVEC_VECTOR_MODE (mode) |
4937d02d DE |
2967 | && GET_MODE_SIZE (mode) >= UNITS_PER_WORD |
2968 | && TARGET_POWERPC64) | |
2969 | { | |
2970 | x = gen_rtx_PLUS (GET_MODE (x), x, GEN_INT (0)); | |
2971 | push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL, | |
2972 | BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0, | |
2973 | opnum, (enum reload_type) type); | |
2974 | *win = 1; | |
2975 | return x; | |
2976 | } | |
2977 | ||
24ea750e DJ |
2978 | if (GET_CODE (x) == PLUS |
2979 | && GET_CODE (XEXP (x, 0)) == REG | |
2980 | && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER | |
2981 | && REG_MODE_OK_FOR_BASE_P (XEXP (x, 0), mode) | |
78c875e8 | 2982 | && GET_CODE (XEXP (x, 1)) == CONST_INT |
93638d7a | 2983 | && !SPE_VECTOR_MODE (mode) |
54b695e7 AH |
2984 | && !(TARGET_E500_DOUBLE && (mode == DFmode |
2985 | || mode == DImode)) | |
78c875e8 | 2986 | && !ALTIVEC_VECTOR_MODE (mode)) |
24ea750e DJ |
2987 | { |
2988 | HOST_WIDE_INT val = INTVAL (XEXP (x, 1)); | |
2989 | HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000; | |
2990 | HOST_WIDE_INT high | |
c4ad648e | 2991 | = (((val - low) & 0xffffffff) ^ 0x80000000) - 0x80000000; |
24ea750e DJ |
2992 | |
2993 | /* Check for 32-bit overflow. */ | |
2994 | if (high + low != val) | |
c4ad648e | 2995 | { |
24ea750e DJ |
2996 | *win = 0; |
2997 | return x; | |
2998 | } | |
2999 | ||
3000 | /* Reload the high part into a base reg; leave the low part | |
c4ad648e | 3001 | in the mem directly. */ |
24ea750e DJ |
3002 | |
3003 | x = gen_rtx_PLUS (GET_MODE (x), | |
c4ad648e AM |
3004 | gen_rtx_PLUS (GET_MODE (x), XEXP (x, 0), |
3005 | GEN_INT (high)), | |
3006 | GEN_INT (low)); | |
24ea750e DJ |
3007 | |
3008 | push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL, | |
c4ad648e AM |
3009 | BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0, |
3010 | opnum, (enum reload_type)type); | |
24ea750e DJ |
3011 | *win = 1; |
3012 | return x; | |
3013 | } | |
4937d02d | 3014 | |
24ea750e DJ |
3015 | #if TARGET_MACHO |
3016 | if (GET_CODE (x) == SYMBOL_REF | |
3017 | && DEFAULT_ABI == ABI_DARWIN | |
69ef87e2 | 3018 | && !ALTIVEC_VECTOR_MODE (mode) |
a29077da | 3019 | && (flag_pic || MACHO_DYNAMIC_NO_PIC_P) |
0d8c1c97 AM |
3020 | /* Don't do this for TFmode, since the result isn't offsettable. |
3021 | The same goes for DImode without 64-bit gprs. */ | |
3022 | && mode != TFmode | |
3023 | && (mode != DImode || TARGET_POWERPC64)) | |
24ea750e | 3024 | { |
a29077da GK |
3025 | if (flag_pic) |
3026 | { | |
3027 | rtx offset = gen_rtx_CONST (Pmode, | |
3028 | gen_rtx_MINUS (Pmode, x, | |
11abc112 | 3029 | machopic_function_base_sym ())); |
a29077da GK |
3030 | x = gen_rtx_LO_SUM (GET_MODE (x), |
3031 | gen_rtx_PLUS (Pmode, pic_offset_table_rtx, | |
3032 | gen_rtx_HIGH (Pmode, offset)), offset); | |
3033 | } | |
3034 | else | |
3035 | x = gen_rtx_LO_SUM (GET_MODE (x), | |
c4ad648e | 3036 | gen_rtx_HIGH (Pmode, x), x); |
a29077da | 3037 | |
24ea750e | 3038 | push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL, |
a29077da GK |
3039 | BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, |
3040 | opnum, (enum reload_type)type); | |
24ea750e DJ |
3041 | *win = 1; |
3042 | return x; | |
3043 | } | |
3044 | #endif | |
4937d02d | 3045 | |
24ea750e | 3046 | if (TARGET_TOC |
4d588c14 | 3047 | && constant_pool_expr_p (x) |
c1f11548 | 3048 | && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x), mode)) |
24ea750e DJ |
3049 | { |
3050 | (x) = create_TOC_reference (x); | |
3051 | *win = 1; | |
3052 | return x; | |
3053 | } | |
3054 | *win = 0; | |
3055 | return x; | |
f676971a | 3056 | } |
24ea750e | 3057 | |
258bfae2 FS |
3058 | /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression |
3059 | that is a valid memory address for an instruction. | |
3060 | The MODE argument is the machine mode for the MEM expression | |
3061 | that wants to use this address. | |
3062 | ||
3063 | On the RS/6000, there are four valid address: a SYMBOL_REF that | |
3064 | refers to a constant pool entry of an address (or the sum of it | |
3065 | plus a constant), a short (16-bit signed) constant plus a register, | |
3066 | the sum of two registers, or a register indirect, possibly with an | |
5bdc5878 | 3067 | auto-increment. For DFmode and DImode with a constant plus register, |
258bfae2 FS |
3068 | we must ensure that both words are addressable or PowerPC64 with offset |
3069 | word aligned. | |
3070 | ||
3071 | For modes spanning multiple registers (DFmode in 32-bit GPRs, | |
76d2b81d | 3072 | 32-bit DImode, TImode, TFmode), indexed addressing cannot be used because |
258bfae2 FS |
3073 | adjacent memory cells are accessed by adding word-sized offsets |
3074 | during assembly output. */ | |
3075 | int | |
a2369ed3 | 3076 | rs6000_legitimate_address (enum machine_mode mode, rtx x, int reg_ok_strict) |
258bfae2 | 3077 | { |
850e8d3d DN |
3078 | /* If this is an unaligned stvx/ldvx type address, discard the outer AND. */ |
3079 | if (TARGET_ALTIVEC | |
3080 | && ALTIVEC_VECTOR_MODE (mode) | |
3081 | && GET_CODE (x) == AND | |
3082 | && GET_CODE (XEXP (x, 1)) == CONST_INT | |
3083 | && INTVAL (XEXP (x, 1)) == -16) | |
3084 | x = XEXP (x, 0); | |
3085 | ||
c4501e62 JJ |
3086 | if (RS6000_SYMBOL_REF_TLS_P (x)) |
3087 | return 0; | |
4d588c14 | 3088 | if (legitimate_indirect_address_p (x, reg_ok_strict)) |
258bfae2 FS |
3089 | return 1; |
3090 | if ((GET_CODE (x) == PRE_INC || GET_CODE (x) == PRE_DEC) | |
0d6d6892 | 3091 | && !ALTIVEC_VECTOR_MODE (mode) |
a3170dc6 | 3092 | && !SPE_VECTOR_MODE (mode) |
54b695e7 AH |
3093 | /* Restrict addressing for DI because of our SUBREG hackery. */ |
3094 | && !(TARGET_E500_DOUBLE && (mode == DFmode || mode == DImode)) | |
258bfae2 | 3095 | && TARGET_UPDATE |
4d588c14 | 3096 | && legitimate_indirect_address_p (XEXP (x, 0), reg_ok_strict)) |
258bfae2 | 3097 | return 1; |
4d588c14 | 3098 | if (legitimate_small_data_p (mode, x)) |
258bfae2 | 3099 | return 1; |
4d588c14 | 3100 | if (legitimate_constant_pool_address_p (x)) |
258bfae2 FS |
3101 | return 1; |
3102 | /* If not REG_OK_STRICT (before reload) let pass any stack offset. */ | |
3103 | if (! reg_ok_strict | |
3104 | && GET_CODE (x) == PLUS | |
3105 | && GET_CODE (XEXP (x, 0)) == REG | |
708d2456 | 3106 | && (XEXP (x, 0) == virtual_stack_vars_rtx |
c4ad648e | 3107 | || XEXP (x, 0) == arg_pointer_rtx) |
258bfae2 FS |
3108 | && GET_CODE (XEXP (x, 1)) == CONST_INT) |
3109 | return 1; | |
76d2b81d | 3110 | if (rs6000_legitimate_offset_address_p (mode, x, reg_ok_strict)) |
258bfae2 FS |
3111 | return 1; |
3112 | if (mode != TImode | |
76d2b81d | 3113 | && mode != TFmode |
a3170dc6 AH |
3114 | && ((TARGET_HARD_FLOAT && TARGET_FPRS) |
3115 | || TARGET_POWERPC64 | |
4d4cbc0e | 3116 | || ((mode != DFmode || TARGET_E500_DOUBLE) && mode != TFmode)) |
258bfae2 | 3117 | && (TARGET_POWERPC64 || mode != DImode) |
4d588c14 | 3118 | && legitimate_indexed_address_p (x, reg_ok_strict)) |
258bfae2 | 3119 | return 1; |
4d588c14 | 3120 | if (legitimate_lo_sum_address_p (mode, x, reg_ok_strict)) |
258bfae2 FS |
3121 | return 1; |
3122 | return 0; | |
3123 | } | |
4d588c14 RH |
3124 | |
3125 | /* Go to LABEL if ADDR (a legitimate address expression) | |
3126 | has an effect that depends on the machine mode it is used for. | |
3127 | ||
3128 | On the RS/6000 this is true of all integral offsets (since AltiVec | |
3129 | modes don't allow them) or is a pre-increment or decrement. | |
3130 | ||
3131 | ??? Except that due to conceptual problems in offsettable_address_p | |
3132 | we can't really report the problems of integral offsets. So leave | |
f676971a | 3133 | this assuming that the adjustable offset must be valid for the |
4d588c14 RH |
3134 | sub-words of a TFmode operand, which is what we had before. */ |
3135 | ||
3136 | bool | |
a2369ed3 | 3137 | rs6000_mode_dependent_address (rtx addr) |
4d588c14 RH |
3138 | { |
3139 | switch (GET_CODE (addr)) | |
3140 | { | |
3141 | case PLUS: | |
3142 | if (GET_CODE (XEXP (addr, 1)) == CONST_INT) | |
3143 | { | |
3144 | unsigned HOST_WIDE_INT val = INTVAL (XEXP (addr, 1)); | |
3145 | return val + 12 + 0x8000 >= 0x10000; | |
3146 | } | |
3147 | break; | |
3148 | ||
3149 | case LO_SUM: | |
3150 | return true; | |
3151 | ||
3152 | case PRE_INC: | |
3153 | case PRE_DEC: | |
3154 | return TARGET_UPDATE; | |
3155 | ||
3156 | default: | |
3157 | break; | |
3158 | } | |
3159 | ||
3160 | return false; | |
3161 | } | |
d8ecbcdb AH |
3162 | |
3163 | /* Return number of consecutive hard regs needed starting at reg REGNO | |
3164 | to hold something of mode MODE. | |
3165 | This is ordinarily the length in words of a value of mode MODE | |
3166 | but can be less for certain modes in special long registers. | |
3167 | ||
3168 | For the SPE, GPRs are 64 bits but only 32 bits are visible in | |
3169 | scalar instructions. The upper 32 bits are only available to the | |
3170 | SIMD instructions. | |
3171 | ||
3172 | POWER and PowerPC GPRs hold 32 bits worth; | |
3173 | PowerPC64 GPRs and FPRs point register holds 64 bits worth. */ | |
3174 | ||
3175 | int | |
3176 | rs6000_hard_regno_nregs (int regno, enum machine_mode mode) | |
3177 | { | |
3178 | if (FP_REGNO_P (regno)) | |
3179 | return (GET_MODE_SIZE (mode) + UNITS_PER_FP_WORD - 1) / UNITS_PER_FP_WORD; | |
3180 | ||
4d4cbc0e AH |
3181 | if (TARGET_E500_DOUBLE && mode == DFmode) |
3182 | return 1; | |
3183 | ||
d8ecbcdb AH |
3184 | if (SPE_SIMD_REGNO_P (regno) && TARGET_SPE && SPE_VECTOR_MODE (mode)) |
3185 | return (GET_MODE_SIZE (mode) + UNITS_PER_SPE_WORD - 1) / UNITS_PER_SPE_WORD; | |
3186 | ||
3187 | if (ALTIVEC_REGNO_P (regno)) | |
3188 | return | |
3189 | (GET_MODE_SIZE (mode) + UNITS_PER_ALTIVEC_WORD - 1) / UNITS_PER_ALTIVEC_WORD; | |
3190 | ||
3191 | return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD; | |
3192 | } | |
2aa4498c AH |
3193 | |
3194 | /* Change register usage conditional on target flags. */ | |
3195 | void | |
3196 | rs6000_conditional_register_usage (void) | |
3197 | { | |
3198 | int i; | |
3199 | ||
3200 | /* Set MQ register fixed (already call_used) if not POWER | |
3201 | architecture (RIOS1, RIOS2, RSC, and PPC601) so that it will not | |
3202 | be allocated. */ | |
3203 | if (! TARGET_POWER) | |
3204 | fixed_regs[64] = 1; | |
3205 | ||
3206 | /* 64-bit AIX reserves GPR13 for thread-private data. */ | |
3207 | if (TARGET_64BIT) | |
3208 | fixed_regs[13] = call_used_regs[13] | |
3209 | = call_really_used_regs[13] = 1; | |
3210 | ||
3211 | /* Conditionally disable FPRs. */ | |
3212 | if (TARGET_SOFT_FLOAT || !TARGET_FPRS) | |
3213 | for (i = 32; i < 64; i++) | |
3214 | fixed_regs[i] = call_used_regs[i] | |
c4ad648e | 3215 | = call_really_used_regs[i] = 1; |
2aa4498c AH |
3216 | |
3217 | if (DEFAULT_ABI == ABI_V4 | |
3218 | && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM | |
3219 | && flag_pic == 2) | |
3220 | fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1; | |
3221 | ||
3222 | if (DEFAULT_ABI == ABI_V4 | |
3223 | && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM | |
3224 | && flag_pic == 1) | |
3225 | fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] | |
3226 | = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] | |
3227 | = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1; | |
3228 | ||
3229 | if (DEFAULT_ABI == ABI_DARWIN | |
3230 | && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) | |
3231 | global_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] | |
3232 | = fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] | |
3233 | = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] | |
3234 | = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1; | |
3235 | ||
b4db40bf JJ |
3236 | if (TARGET_TOC && TARGET_MINIMAL_TOC) |
3237 | fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] | |
3238 | = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1; | |
3239 | ||
2aa4498c AH |
3240 | if (TARGET_ALTIVEC) |
3241 | global_regs[VSCR_REGNO] = 1; | |
3242 | ||
3243 | if (TARGET_SPE) | |
3244 | { | |
3245 | global_regs[SPEFSCR_REGNO] = 1; | |
3246 | fixed_regs[FIXED_SCRATCH] | |
c4ad648e | 3247 | = call_used_regs[FIXED_SCRATCH] |
2aa4498c AH |
3248 | = call_really_used_regs[FIXED_SCRATCH] = 1; |
3249 | } | |
3250 | ||
3251 | if (! TARGET_ALTIVEC) | |
3252 | { | |
3253 | for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i) | |
3254 | fixed_regs[i] = call_used_regs[i] = call_really_used_regs[i] = 1; | |
3255 | call_really_used_regs[VRSAVE_REGNO] = 1; | |
3256 | } | |
3257 | ||
3258 | if (TARGET_ALTIVEC_ABI) | |
3259 | for (i = FIRST_ALTIVEC_REGNO; i < FIRST_ALTIVEC_REGNO + 20; ++i) | |
3260 | call_used_regs[i] = call_really_used_regs[i] = 1; | |
3261 | } | |
fb4d4348 | 3262 | \f |
a4f6c312 SS |
3263 | /* Try to output insns to set TARGET equal to the constant C if it can |
3264 | be done in less than N insns. Do all computations in MODE. | |
3265 | Returns the place where the output has been placed if it can be | |
3266 | done and the insns have been emitted. If it would take more than N | |
3267 | insns, zero is returned and no insns and emitted. */ | |
2bfcf297 DB |
3268 | |
3269 | rtx | |
f676971a | 3270 | rs6000_emit_set_const (rtx dest, enum machine_mode mode, |
a2369ed3 | 3271 | rtx source, int n ATTRIBUTE_UNUSED) |
2bfcf297 | 3272 | { |
af8cb5c5 | 3273 | rtx result, insn, set; |
2bfcf297 DB |
3274 | HOST_WIDE_INT c0, c1; |
3275 | ||
37409796 | 3276 | switch (mode) |
2bfcf297 | 3277 | { |
37409796 NS |
3278 | case QImode: |
3279 | case HImode: | |
2bfcf297 | 3280 | if (dest == NULL) |
c4ad648e | 3281 | dest = gen_reg_rtx (mode); |
2bfcf297 DB |
3282 | emit_insn (gen_rtx_SET (VOIDmode, dest, source)); |
3283 | return dest; | |
37409796 NS |
3284 | |
3285 | case SImode: | |
af8cb5c5 | 3286 | result = no_new_pseudos ? dest : gen_reg_rtx (SImode); |
37409796 | 3287 | |
af8cb5c5 DE |
3288 | emit_insn (gen_rtx_SET (VOIDmode, result, |
3289 | GEN_INT (INTVAL (source) | |
3290 | & (~ (HOST_WIDE_INT) 0xffff)))); | |
3291 | emit_insn (gen_rtx_SET (VOIDmode, dest, | |
3292 | gen_rtx_IOR (SImode, result, | |
3293 | GEN_INT (INTVAL (source) & 0xffff)))); | |
3294 | result = dest; | |
37409796 NS |
3295 | break; |
3296 | ||
3297 | case DImode: | |
3298 | switch (GET_CODE (source)) | |
af8cb5c5 | 3299 | { |
37409796 | 3300 | case CONST_INT: |
af8cb5c5 DE |
3301 | c0 = INTVAL (source); |
3302 | c1 = -(c0 < 0); | |
37409796 NS |
3303 | break; |
3304 | ||
3305 | case CONST_DOUBLE: | |
2bfcf297 | 3306 | #if HOST_BITS_PER_WIDE_INT >= 64 |
af8cb5c5 DE |
3307 | c0 = CONST_DOUBLE_LOW (source); |
3308 | c1 = -(c0 < 0); | |
2bfcf297 | 3309 | #else |
af8cb5c5 DE |
3310 | c0 = CONST_DOUBLE_LOW (source); |
3311 | c1 = CONST_DOUBLE_HIGH (source); | |
2bfcf297 | 3312 | #endif |
37409796 NS |
3313 | break; |
3314 | ||
3315 | default: | |
3316 | gcc_unreachable (); | |
af8cb5c5 | 3317 | } |
af8cb5c5 DE |
3318 | |
3319 | result = rs6000_emit_set_long_const (dest, c0, c1); | |
37409796 NS |
3320 | break; |
3321 | ||
3322 | default: | |
3323 | gcc_unreachable (); | |
2bfcf297 | 3324 | } |
2bfcf297 | 3325 | |
af8cb5c5 DE |
3326 | insn = get_last_insn (); |
3327 | set = single_set (insn); | |
3328 | if (! CONSTANT_P (SET_SRC (set))) | |
3329 | set_unique_reg_note (insn, REG_EQUAL, source); | |
3330 | ||
3331 | return result; | |
2bfcf297 DB |
3332 | } |
3333 | ||
3334 | /* Having failed to find a 3 insn sequence in rs6000_emit_set_const, | |
3335 | fall back to a straight forward decomposition. We do this to avoid | |
3336 | exponential run times encountered when looking for longer sequences | |
3337 | with rs6000_emit_set_const. */ | |
3338 | static rtx | |
a2369ed3 | 3339 | rs6000_emit_set_long_const (rtx dest, HOST_WIDE_INT c1, HOST_WIDE_INT c2) |
2bfcf297 DB |
3340 | { |
3341 | if (!TARGET_POWERPC64) | |
3342 | { | |
3343 | rtx operand1, operand2; | |
3344 | ||
3345 | operand1 = operand_subword_force (dest, WORDS_BIG_ENDIAN == 0, | |
3346 | DImode); | |
3347 | operand2 = operand_subword_force (dest, WORDS_BIG_ENDIAN != 0, | |
3348 | DImode); | |
3349 | emit_move_insn (operand1, GEN_INT (c1)); | |
3350 | emit_move_insn (operand2, GEN_INT (c2)); | |
3351 | } | |
3352 | else | |
3353 | { | |
bc06712d | 3354 | HOST_WIDE_INT ud1, ud2, ud3, ud4; |
252b88f7 | 3355 | |
bc06712d | 3356 | ud1 = c1 & 0xffff; |
f921c9c9 | 3357 | ud2 = (c1 & 0xffff0000) >> 16; |
2bfcf297 | 3358 | #if HOST_BITS_PER_WIDE_INT >= 64 |
bc06712d | 3359 | c2 = c1 >> 32; |
2bfcf297 | 3360 | #endif |
bc06712d | 3361 | ud3 = c2 & 0xffff; |
f921c9c9 | 3362 | ud4 = (c2 & 0xffff0000) >> 16; |
2bfcf297 | 3363 | |
f676971a | 3364 | if ((ud4 == 0xffff && ud3 == 0xffff && ud2 == 0xffff && (ud1 & 0x8000)) |
bc06712d | 3365 | || (ud4 == 0 && ud3 == 0 && ud2 == 0 && ! (ud1 & 0x8000))) |
2bfcf297 | 3366 | { |
bc06712d | 3367 | if (ud1 & 0x8000) |
b78d48dd | 3368 | emit_move_insn (dest, GEN_INT (((ud1 ^ 0x8000) - 0x8000))); |
bc06712d TR |
3369 | else |
3370 | emit_move_insn (dest, GEN_INT (ud1)); | |
2bfcf297 | 3371 | } |
2bfcf297 | 3372 | |
f676971a | 3373 | else if ((ud4 == 0xffff && ud3 == 0xffff && (ud2 & 0x8000)) |
bc06712d | 3374 | || (ud4 == 0 && ud3 == 0 && ! (ud2 & 0x8000))) |
252b88f7 | 3375 | { |
bc06712d | 3376 | if (ud2 & 0x8000) |
f676971a | 3377 | emit_move_insn (dest, GEN_INT (((ud2 << 16) ^ 0x80000000) |
bc06712d | 3378 | - 0x80000000)); |
252b88f7 | 3379 | else |
bc06712d TR |
3380 | emit_move_insn (dest, GEN_INT (ud2 << 16)); |
3381 | if (ud1 != 0) | |
3382 | emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud1))); | |
252b88f7 | 3383 | } |
f676971a | 3384 | else if ((ud4 == 0xffff && (ud3 & 0x8000)) |
bc06712d TR |
3385 | || (ud4 == 0 && ! (ud3 & 0x8000))) |
3386 | { | |
3387 | if (ud3 & 0x8000) | |
f676971a | 3388 | emit_move_insn (dest, GEN_INT (((ud3 << 16) ^ 0x80000000) |
bc06712d TR |
3389 | - 0x80000000)); |
3390 | else | |
3391 | emit_move_insn (dest, GEN_INT (ud3 << 16)); | |
3392 | ||
3393 | if (ud2 != 0) | |
3394 | emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud2))); | |
3395 | emit_move_insn (dest, gen_rtx_ASHIFT (DImode, dest, GEN_INT (16))); | |
3396 | if (ud1 != 0) | |
3397 | emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud1))); | |
3398 | } | |
f676971a | 3399 | else |
bc06712d TR |
3400 | { |
3401 | if (ud4 & 0x8000) | |
f676971a | 3402 | emit_move_insn (dest, GEN_INT (((ud4 << 16) ^ 0x80000000) |
bc06712d TR |
3403 | - 0x80000000)); |
3404 | else | |
3405 | emit_move_insn (dest, GEN_INT (ud4 << 16)); | |
3406 | ||
3407 | if (ud3 != 0) | |
3408 | emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud3))); | |
2bfcf297 | 3409 | |
bc06712d TR |
3410 | emit_move_insn (dest, gen_rtx_ASHIFT (DImode, dest, GEN_INT (32))); |
3411 | if (ud2 != 0) | |
f676971a EC |
3412 | emit_move_insn (dest, gen_rtx_IOR (DImode, dest, |
3413 | GEN_INT (ud2 << 16))); | |
bc06712d TR |
3414 | if (ud1 != 0) |
3415 | emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud1))); | |
3416 | } | |
3417 | } | |
2bfcf297 DB |
3418 | return dest; |
3419 | } | |
3420 | ||
76d2b81d DJ |
3421 | /* Helper for the following. Get rid of [r+r] memory refs |
3422 | in cases where it won't work (TImode, TFmode). */ | |
3423 | ||
3424 | static void | |
3425 | rs6000_eliminate_indexed_memrefs (rtx operands[2]) | |
3426 | { | |
3427 | if (GET_CODE (operands[0]) == MEM | |
3428 | && GET_CODE (XEXP (operands[0], 0)) != REG | |
55aa0757 | 3429 | && ! legitimate_constant_pool_address_p (XEXP (operands[0], 0)) |
76d2b81d DJ |
3430 | && ! reload_in_progress) |
3431 | operands[0] | |
3432 | = replace_equiv_address (operands[0], | |
3433 | copy_addr_to_reg (XEXP (operands[0], 0))); | |
3434 | ||
3435 | if (GET_CODE (operands[1]) == MEM | |
3436 | && GET_CODE (XEXP (operands[1], 0)) != REG | |
55aa0757 | 3437 | && ! legitimate_constant_pool_address_p (XEXP (operands[1], 0)) |
76d2b81d DJ |
3438 | && ! reload_in_progress) |
3439 | operands[1] | |
3440 | = replace_equiv_address (operands[1], | |
3441 | copy_addr_to_reg (XEXP (operands[1], 0))); | |
3442 | } | |
3443 | ||
fb4d4348 GK |
3444 | /* Emit a move from SOURCE to DEST in mode MODE. */ |
3445 | void | |
a2369ed3 | 3446 | rs6000_emit_move (rtx dest, rtx source, enum machine_mode mode) |
fb4d4348 GK |
3447 | { |
3448 | rtx operands[2]; | |
3449 | operands[0] = dest; | |
3450 | operands[1] = source; | |
f676971a | 3451 | |
fb4d4348 GK |
3452 | /* Sanity checks. Check that we get CONST_DOUBLE only when we should. */ |
3453 | if (GET_CODE (operands[1]) == CONST_DOUBLE | |
3454 | && ! FLOAT_MODE_P (mode) | |
3455 | && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT) | |
3456 | { | |
3457 | /* FIXME. This should never happen. */ | |
3458 | /* Since it seems that it does, do the safe thing and convert | |
3459 | to a CONST_INT. */ | |
2496c7bd | 3460 | operands[1] = gen_int_mode (CONST_DOUBLE_LOW (operands[1]), mode); |
fb4d4348 | 3461 | } |
37409796 NS |
3462 | gcc_assert (GET_CODE (operands[1]) != CONST_DOUBLE |
3463 | || FLOAT_MODE_P (mode) | |
3464 | || ((CONST_DOUBLE_HIGH (operands[1]) != 0 | |
3465 | || CONST_DOUBLE_LOW (operands[1]) < 0) | |
3466 | && (CONST_DOUBLE_HIGH (operands[1]) != -1 | |
3467 | || CONST_DOUBLE_LOW (operands[1]) >= 0))); | |
3468 | ||
c9e8cb32 DD |
3469 | /* Check if GCC is setting up a block move that will end up using FP |
3470 | registers as temporaries. We must make sure this is acceptable. */ | |
3471 | if (GET_CODE (operands[0]) == MEM | |
3472 | && GET_CODE (operands[1]) == MEM | |
3473 | && mode == DImode | |
41543739 GK |
3474 | && (SLOW_UNALIGNED_ACCESS (DImode, MEM_ALIGN (operands[0])) |
3475 | || SLOW_UNALIGNED_ACCESS (DImode, MEM_ALIGN (operands[1]))) | |
3476 | && ! (SLOW_UNALIGNED_ACCESS (SImode, (MEM_ALIGN (operands[0]) > 32 | |
3477 | ? 32 : MEM_ALIGN (operands[0]))) | |
3478 | || SLOW_UNALIGNED_ACCESS (SImode, (MEM_ALIGN (operands[1]) > 32 | |
f676971a | 3479 | ? 32 |
41543739 GK |
3480 | : MEM_ALIGN (operands[1])))) |
3481 | && ! MEM_VOLATILE_P (operands [0]) | |
3482 | && ! MEM_VOLATILE_P (operands [1])) | |
c9e8cb32 | 3483 | { |
41543739 GK |
3484 | emit_move_insn (adjust_address (operands[0], SImode, 0), |
3485 | adjust_address (operands[1], SImode, 0)); | |
3486 | emit_move_insn (adjust_address (operands[0], SImode, 4), | |
3487 | adjust_address (operands[1], SImode, 4)); | |
c9e8cb32 DD |
3488 | return; |
3489 | } | |
630d42a0 | 3490 | |
55aa0757 | 3491 | if (!no_new_pseudos && GET_CODE (operands[0]) == MEM |
c9dbf840 | 3492 | && !gpc_reg_operand (operands[1], mode)) |
f6219a5e | 3493 | operands[1] = force_reg (mode, operands[1]); |
a9098fd0 | 3494 | |
a3170dc6 AH |
3495 | if (mode == SFmode && ! TARGET_POWERPC |
3496 | && TARGET_HARD_FLOAT && TARGET_FPRS | |
ffc14f31 | 3497 | && GET_CODE (operands[0]) == MEM) |
fb4d4348 | 3498 | { |
ffc14f31 GK |
3499 | int regnum; |
3500 | ||
3501 | if (reload_in_progress || reload_completed) | |
3502 | regnum = true_regnum (operands[1]); | |
3503 | else if (GET_CODE (operands[1]) == REG) | |
3504 | regnum = REGNO (operands[1]); | |
3505 | else | |
3506 | regnum = -1; | |
f676971a | 3507 | |
fb4d4348 GK |
3508 | /* If operands[1] is a register, on POWER it may have |
3509 | double-precision data in it, so truncate it to single | |
3510 | precision. */ | |
3511 | if (FP_REGNO_P (regnum) || regnum >= FIRST_PSEUDO_REGISTER) | |
3512 | { | |
3513 | rtx newreg; | |
3514 | newreg = (no_new_pseudos ? operands[1] : gen_reg_rtx (mode)); | |
3515 | emit_insn (gen_aux_truncdfsf2 (newreg, operands[1])); | |
3516 | operands[1] = newreg; | |
3517 | } | |
3518 | } | |
3519 | ||
c4501e62 JJ |
3520 | /* Recognize the case where operand[1] is a reference to thread-local |
3521 | data and load its address to a register. */ | |
3522 | if (GET_CODE (operands[1]) == SYMBOL_REF) | |
3523 | { | |
3524 | enum tls_model model = SYMBOL_REF_TLS_MODEL (operands[1]); | |
3525 | if (model != 0) | |
3526 | operands[1] = rs6000_legitimize_tls_address (operands[1], model); | |
3527 | } | |
3528 | ||
8f4e6caf RH |
3529 | /* Handle the case where reload calls us with an invalid address. */ |
3530 | if (reload_in_progress && mode == Pmode | |
69ef87e2 | 3531 | && (! general_operand (operands[1], mode) |
8f4e6caf RH |
3532 | || ! nonimmediate_operand (operands[0], mode))) |
3533 | goto emit_set; | |
3534 | ||
a9baceb1 GK |
3535 | /* 128-bit constant floating-point values on Darwin should really be |
3536 | loaded as two parts. */ | |
3537 | if ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) | |
3538 | && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128 | |
3539 | && mode == TFmode && GET_CODE (operands[1]) == CONST_DOUBLE) | |
3540 | { | |
3541 | /* DImode is used, not DFmode, because simplify_gen_subreg doesn't | |
3542 | know how to get a DFmode SUBREG of a TFmode. */ | |
3543 | rs6000_emit_move (simplify_gen_subreg (DImode, operands[0], mode, 0), | |
3544 | simplify_gen_subreg (DImode, operands[1], mode, 0), | |
3545 | DImode); | |
3546 | rs6000_emit_move (simplify_gen_subreg (DImode, operands[0], mode, | |
3547 | GET_MODE_SIZE (DImode)), | |
3548 | simplify_gen_subreg (DImode, operands[1], mode, | |
3549 | GET_MODE_SIZE (DImode)), | |
3550 | DImode); | |
3551 | return; | |
3552 | } | |
3553 | ||
fb4d4348 GK |
3554 | /* FIXME: In the long term, this switch statement should go away |
3555 | and be replaced by a sequence of tests based on things like | |
3556 | mode == Pmode. */ | |
3557 | switch (mode) | |
3558 | { | |
3559 | case HImode: | |
3560 | case QImode: | |
3561 | if (CONSTANT_P (operands[1]) | |
3562 | && GET_CODE (operands[1]) != CONST_INT) | |
a9098fd0 | 3563 | operands[1] = force_const_mem (mode, operands[1]); |
fb4d4348 GK |
3564 | break; |
3565 | ||
06f4e019 | 3566 | case TFmode: |
76d2b81d DJ |
3567 | rs6000_eliminate_indexed_memrefs (operands); |
3568 | /* fall through */ | |
3569 | ||
fb4d4348 GK |
3570 | case DFmode: |
3571 | case SFmode: | |
f676971a | 3572 | if (CONSTANT_P (operands[1]) |
fb4d4348 | 3573 | && ! easy_fp_constant (operands[1], mode)) |
a9098fd0 | 3574 | operands[1] = force_const_mem (mode, operands[1]); |
fb4d4348 | 3575 | break; |
f676971a | 3576 | |
0ac081f6 AH |
3577 | case V16QImode: |
3578 | case V8HImode: | |
3579 | case V4SFmode: | |
3580 | case V4SImode: | |
a3170dc6 AH |
3581 | case V4HImode: |
3582 | case V2SFmode: | |
3583 | case V2SImode: | |
00a892b8 | 3584 | case V1DImode: |
69ef87e2 | 3585 | if (CONSTANT_P (operands[1]) |
d744e06e | 3586 | && !easy_vector_constant (operands[1], mode)) |
0ac081f6 AH |
3587 | operands[1] = force_const_mem (mode, operands[1]); |
3588 | break; | |
f676971a | 3589 | |
fb4d4348 | 3590 | case SImode: |
a9098fd0 | 3591 | case DImode: |
fb4d4348 GK |
3592 | /* Use default pattern for address of ELF small data */ |
3593 | if (TARGET_ELF | |
a9098fd0 | 3594 | && mode == Pmode |
f607bc57 | 3595 | && DEFAULT_ABI == ABI_V4 |
f676971a | 3596 | && (GET_CODE (operands[1]) == SYMBOL_REF |
a9098fd0 GK |
3597 | || GET_CODE (operands[1]) == CONST) |
3598 | && small_data_operand (operands[1], mode)) | |
fb4d4348 GK |
3599 | { |
3600 | emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1])); | |
3601 | return; | |
3602 | } | |
3603 | ||
f607bc57 | 3604 | if (DEFAULT_ABI == ABI_V4 |
a9098fd0 GK |
3605 | && mode == Pmode && mode == SImode |
3606 | && flag_pic == 1 && got_operand (operands[1], mode)) | |
fb4d4348 GK |
3607 | { |
3608 | emit_insn (gen_movsi_got (operands[0], operands[1])); | |
3609 | return; | |
3610 | } | |
3611 | ||
ee890fe2 | 3612 | if ((TARGET_ELF || DEFAULT_ABI == ABI_DARWIN) |
f1384257 AM |
3613 | && TARGET_NO_TOC |
3614 | && ! flag_pic | |
a9098fd0 | 3615 | && mode == Pmode |
fb4d4348 GK |
3616 | && CONSTANT_P (operands[1]) |
3617 | && GET_CODE (operands[1]) != HIGH | |
3618 | && GET_CODE (operands[1]) != CONST_INT) | |
3619 | { | |
a9098fd0 | 3620 | rtx target = (no_new_pseudos ? operands[0] : gen_reg_rtx (mode)); |
fb4d4348 GK |
3621 | |
3622 | /* If this is a function address on -mcall-aixdesc, | |
3623 | convert it to the address of the descriptor. */ | |
3624 | if (DEFAULT_ABI == ABI_AIX | |
3625 | && GET_CODE (operands[1]) == SYMBOL_REF | |
3626 | && XSTR (operands[1], 0)[0] == '.') | |
3627 | { | |
3628 | const char *name = XSTR (operands[1], 0); | |
3629 | rtx new_ref; | |
3630 | while (*name == '.') | |
3631 | name++; | |
3632 | new_ref = gen_rtx_SYMBOL_REF (Pmode, name); | |
3633 | CONSTANT_POOL_ADDRESS_P (new_ref) | |
3634 | = CONSTANT_POOL_ADDRESS_P (operands[1]); | |
d1908feb | 3635 | SYMBOL_REF_FLAGS (new_ref) = SYMBOL_REF_FLAGS (operands[1]); |
fb4d4348 | 3636 | SYMBOL_REF_USED (new_ref) = SYMBOL_REF_USED (operands[1]); |
d1908feb | 3637 | SYMBOL_REF_DECL (new_ref) = SYMBOL_REF_DECL (operands[1]); |
fb4d4348 GK |
3638 | operands[1] = new_ref; |
3639 | } | |
7509c759 | 3640 | |
ee890fe2 SS |
3641 | if (DEFAULT_ABI == ABI_DARWIN) |
3642 | { | |
ab82a49f AP |
3643 | #if TARGET_MACHO |
3644 | if (MACHO_DYNAMIC_NO_PIC_P) | |
3645 | { | |
3646 | /* Take care of any required data indirection. */ | |
3647 | operands[1] = rs6000_machopic_legitimize_pic_address ( | |
3648 | operands[1], mode, operands[0]); | |
3649 | if (operands[0] != operands[1]) | |
3650 | emit_insn (gen_rtx_SET (VOIDmode, | |
c4ad648e | 3651 | operands[0], operands[1])); |
ab82a49f AP |
3652 | return; |
3653 | } | |
3654 | #endif | |
b8a55285 AP |
3655 | emit_insn (gen_macho_high (target, operands[1])); |
3656 | emit_insn (gen_macho_low (operands[0], target, operands[1])); | |
ee890fe2 SS |
3657 | return; |
3658 | } | |
3659 | ||
fb4d4348 GK |
3660 | emit_insn (gen_elf_high (target, operands[1])); |
3661 | emit_insn (gen_elf_low (operands[0], target, operands[1])); | |
3662 | return; | |
3663 | } | |
3664 | ||
a9098fd0 GK |
3665 | /* If this is a SYMBOL_REF that refers to a constant pool entry, |
3666 | and we have put it in the TOC, we just need to make a TOC-relative | |
3667 | reference to it. */ | |
3668 | if (TARGET_TOC | |
3669 | && GET_CODE (operands[1]) == SYMBOL_REF | |
4d588c14 | 3670 | && constant_pool_expr_p (operands[1]) |
a9098fd0 GK |
3671 | && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (operands[1]), |
3672 | get_pool_mode (operands[1]))) | |
fb4d4348 | 3673 | { |
a9098fd0 | 3674 | operands[1] = create_TOC_reference (operands[1]); |
fb4d4348 | 3675 | } |
a9098fd0 GK |
3676 | else if (mode == Pmode |
3677 | && CONSTANT_P (operands[1]) | |
38886f37 AO |
3678 | && ((GET_CODE (operands[1]) != CONST_INT |
3679 | && ! easy_fp_constant (operands[1], mode)) | |
3680 | || (GET_CODE (operands[1]) == CONST_INT | |
3681 | && num_insns_constant (operands[1], mode) > 2) | |
3682 | || (GET_CODE (operands[0]) == REG | |
3683 | && FP_REGNO_P (REGNO (operands[0])))) | |
a9098fd0 | 3684 | && GET_CODE (operands[1]) != HIGH |
4d588c14 RH |
3685 | && ! legitimate_constant_pool_address_p (operands[1]) |
3686 | && ! toc_relative_expr_p (operands[1])) | |
fb4d4348 GK |
3687 | { |
3688 | /* Emit a USE operation so that the constant isn't deleted if | |
3689 | expensive optimizations are turned on because nobody | |
3690 | references it. This should only be done for operands that | |
3691 | contain SYMBOL_REFs with CONSTANT_POOL_ADDRESS_P set. | |
3692 | This should not be done for operands that contain LABEL_REFs. | |
3693 | For now, we just handle the obvious case. */ | |
3694 | if (GET_CODE (operands[1]) != LABEL_REF) | |
3695 | emit_insn (gen_rtx_USE (VOIDmode, operands[1])); | |
3696 | ||
c859cda6 | 3697 | #if TARGET_MACHO |
ee890fe2 | 3698 | /* Darwin uses a special PIC legitimizer. */ |
ab82a49f | 3699 | if (DEFAULT_ABI == ABI_DARWIN && MACHOPIC_INDIRECT) |
ee890fe2 | 3700 | { |
ee890fe2 SS |
3701 | operands[1] = |
3702 | rs6000_machopic_legitimize_pic_address (operands[1], mode, | |
c859cda6 DJ |
3703 | operands[0]); |
3704 | if (operands[0] != operands[1]) | |
3705 | emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1])); | |
ee890fe2 SS |
3706 | return; |
3707 | } | |
c859cda6 | 3708 | #endif |
ee890fe2 | 3709 | |
fb4d4348 GK |
3710 | /* If we are to limit the number of things we put in the TOC and |
3711 | this is a symbol plus a constant we can add in one insn, | |
3712 | just put the symbol in the TOC and add the constant. Don't do | |
3713 | this if reload is in progress. */ | |
3714 | if (GET_CODE (operands[1]) == CONST | |
3715 | && TARGET_NO_SUM_IN_TOC && ! reload_in_progress | |
3716 | && GET_CODE (XEXP (operands[1], 0)) == PLUS | |
a9098fd0 | 3717 | && add_operand (XEXP (XEXP (operands[1], 0), 1), mode) |
fb4d4348 GK |
3718 | && (GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == LABEL_REF |
3719 | || GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == SYMBOL_REF) | |
3720 | && ! side_effects_p (operands[0])) | |
3721 | { | |
a4f6c312 SS |
3722 | rtx sym = |
3723 | force_const_mem (mode, XEXP (XEXP (operands[1], 0), 0)); | |
fb4d4348 GK |
3724 | rtx other = XEXP (XEXP (operands[1], 0), 1); |
3725 | ||
a9098fd0 GK |
3726 | sym = force_reg (mode, sym); |
3727 | if (mode == SImode) | |
3728 | emit_insn (gen_addsi3 (operands[0], sym, other)); | |
3729 | else | |
3730 | emit_insn (gen_adddi3 (operands[0], sym, other)); | |
fb4d4348 GK |
3731 | return; |
3732 | } | |
3733 | ||
a9098fd0 | 3734 | operands[1] = force_const_mem (mode, operands[1]); |
fb4d4348 | 3735 | |
f676971a | 3736 | if (TARGET_TOC |
4d588c14 | 3737 | && constant_pool_expr_p (XEXP (operands[1], 0)) |
d34c5b80 DE |
3738 | && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P ( |
3739 | get_pool_constant (XEXP (operands[1], 0)), | |
3740 | get_pool_mode (XEXP (operands[1], 0)))) | |
a9098fd0 | 3741 | { |
ba4828e0 | 3742 | operands[1] |
542a8afa | 3743 | = gen_const_mem (mode, |
c4ad648e | 3744 | create_TOC_reference (XEXP (operands[1], 0))); |
ba4828e0 | 3745 | set_mem_alias_set (operands[1], get_TOC_alias_set ()); |
a9098fd0 | 3746 | } |
fb4d4348 GK |
3747 | } |
3748 | break; | |
a9098fd0 | 3749 | |
fb4d4348 | 3750 | case TImode: |
76d2b81d DJ |
3751 | rs6000_eliminate_indexed_memrefs (operands); |
3752 | ||
27dc0551 DE |
3753 | if (TARGET_POWER) |
3754 | { | |
3755 | emit_insn (gen_rtx_PARALLEL (VOIDmode, | |
3756 | gen_rtvec (2, | |
3757 | gen_rtx_SET (VOIDmode, | |
3758 | operands[0], operands[1]), | |
3759 | gen_rtx_CLOBBER (VOIDmode, | |
3760 | gen_rtx_SCRATCH (SImode))))); | |
3761 | return; | |
3762 | } | |
fb4d4348 GK |
3763 | break; |
3764 | ||
3765 | default: | |
37409796 | 3766 | gcc_unreachable (); |
fb4d4348 GK |
3767 | } |
3768 | ||
a9098fd0 GK |
3769 | /* Above, we may have called force_const_mem which may have returned |
3770 | an invalid address. If we can, fix this up; otherwise, reload will | |
3771 | have to deal with it. */ | |
8f4e6caf RH |
3772 | if (GET_CODE (operands[1]) == MEM && ! reload_in_progress) |
3773 | operands[1] = validize_mem (operands[1]); | |
a9098fd0 | 3774 | |
8f4e6caf | 3775 | emit_set: |
fb4d4348 GK |
3776 | emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1])); |
3777 | } | |
4697a36c | 3778 | \f |
2858f73a GK |
3779 | /* Nonzero if we can use a floating-point register to pass this arg. */ |
3780 | #define USE_FP_FOR_ARG_P(CUM,MODE,TYPE) \ | |
3781 | (GET_MODE_CLASS (MODE) == MODE_FLOAT \ | |
3782 | && (CUM)->fregno <= FP_ARG_MAX_REG \ | |
3783 | && TARGET_HARD_FLOAT && TARGET_FPRS) | |
3784 | ||
3785 | /* Nonzero if we can use an AltiVec register to pass this arg. */ | |
3786 | #define USE_ALTIVEC_FOR_ARG_P(CUM,MODE,TYPE,NAMED) \ | |
3787 | (ALTIVEC_VECTOR_MODE (MODE) \ | |
3788 | && (CUM)->vregno <= ALTIVEC_ARG_MAX_REG \ | |
3789 | && TARGET_ALTIVEC_ABI \ | |
83953138 | 3790 | && (NAMED)) |
2858f73a | 3791 | |
c6e8c921 GK |
3792 | /* Return a nonzero value to say to return the function value in |
3793 | memory, just as large structures are always returned. TYPE will be | |
3794 | the data type of the value, and FNTYPE will be the type of the | |
3795 | function doing the returning, or @code{NULL} for libcalls. | |
3796 | ||
3797 | The AIX ABI for the RS/6000 specifies that all structures are | |
3798 | returned in memory. The Darwin ABI does the same. The SVR4 ABI | |
3799 | specifies that structures <= 8 bytes are returned in r3/r4, but a | |
3800 | draft put them in memory, and GCC used to implement the draft | |
3801 | instead of the final standard. Therefore, TARGET_AIX_STRUCT_RET | |
3802 | controls this instead of DEFAULT_ABI; V.4 targets needing backward | |
3803 | compatibility can change DRAFT_V4_STRUCT_RET to override the | |
3804 | default, and -m switches get the final word. See | |
3805 | rs6000_override_options for more details. | |
3806 | ||
3807 | The PPC32 SVR4 ABI uses IEEE double extended for long double, if 128-bit | |
3808 | long double support is enabled. These values are returned in memory. | |
3809 | ||
3810 | int_size_in_bytes returns -1 for variable size objects, which go in | |
3811 | memory always. The cast to unsigned makes -1 > 8. */ | |
3812 | ||
3813 | static bool | |
3814 | rs6000_return_in_memory (tree type, tree fntype ATTRIBUTE_UNUSED) | |
3815 | { | |
594a51fe SS |
3816 | /* In the darwin64 abi, try to use registers for larger structs |
3817 | if possible. */ | |
0b5383eb | 3818 | if (rs6000_darwin64_abi |
594a51fe | 3819 | && TREE_CODE (type) == RECORD_TYPE |
0b5383eb DJ |
3820 | && int_size_in_bytes (type) > 0) |
3821 | { | |
3822 | CUMULATIVE_ARGS valcum; | |
3823 | rtx valret; | |
3824 | ||
3825 | valcum.words = 0; | |
3826 | valcum.fregno = FP_ARG_MIN_REG; | |
3827 | valcum.vregno = ALTIVEC_ARG_MIN_REG; | |
3828 | /* Do a trial code generation as if this were going to be passed | |
3829 | as an argument; if any part goes in memory, we return NULL. */ | |
3830 | valret = rs6000_darwin64_record_arg (&valcum, type, 1, true); | |
3831 | if (valret) | |
3832 | return false; | |
3833 | /* Otherwise fall through to more conventional ABI rules. */ | |
3834 | } | |
594a51fe | 3835 | |
c6e8c921 GK |
3836 | if (AGGREGATE_TYPE_P (type) |
3837 | && (TARGET_AIX_STRUCT_RET | |
3838 | || (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 8)) | |
3839 | return true; | |
b693336b | 3840 | |
bada2eb8 DE |
3841 | /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector |
3842 | modes only exist for GCC vector types if -maltivec. */ | |
3843 | if (TARGET_32BIT && !TARGET_ALTIVEC_ABI | |
3844 | && ALTIVEC_VECTOR_MODE (TYPE_MODE (type))) | |
3845 | return false; | |
3846 | ||
b693336b PB |
3847 | /* Return synthetic vectors in memory. */ |
3848 | if (TREE_CODE (type) == VECTOR_TYPE | |
ad630bef | 3849 | && int_size_in_bytes (type) > (TARGET_ALTIVEC_ABI ? 16 : 8)) |
b693336b PB |
3850 | { |
3851 | static bool warned_for_return_big_vectors = false; | |
3852 | if (!warned_for_return_big_vectors) | |
3853 | { | |
d4ee4d25 | 3854 | warning (0, "GCC vector returned by reference: " |
b693336b PB |
3855 | "non-standard ABI extension with no compatibility guarantee"); |
3856 | warned_for_return_big_vectors = true; | |
3857 | } | |
3858 | return true; | |
3859 | } | |
3860 | ||
c6e8c921 GK |
3861 | if (DEFAULT_ABI == ABI_V4 && TYPE_MODE (type) == TFmode) |
3862 | return true; | |
ad630bef | 3863 | |
c6e8c921 GK |
3864 | return false; |
3865 | } | |
3866 | ||
4697a36c MM |
3867 | /* Initialize a variable CUM of type CUMULATIVE_ARGS |
3868 | for a call to a function whose data type is FNTYPE. | |
3869 | For a library call, FNTYPE is 0. | |
3870 | ||
3871 | For incoming args we set the number of arguments in the prototype large | |
1c20ae99 | 3872 | so we never return a PARALLEL. */ |
4697a36c MM |
3873 | |
3874 | void | |
f676971a | 3875 | init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype, |
0f6937fe AM |
3876 | rtx libname ATTRIBUTE_UNUSED, int incoming, |
3877 | int libcall, int n_named_args) | |
4697a36c MM |
3878 | { |
3879 | static CUMULATIVE_ARGS zero_cumulative; | |
3880 | ||
3881 | *cum = zero_cumulative; | |
3882 | cum->words = 0; | |
3883 | cum->fregno = FP_ARG_MIN_REG; | |
0ac081f6 | 3884 | cum->vregno = ALTIVEC_ARG_MIN_REG; |
4697a36c | 3885 | cum->prototype = (fntype && TYPE_ARG_TYPES (fntype)); |
ddcc8263 DE |
3886 | cum->call_cookie = ((DEFAULT_ABI == ABI_V4 && libcall) |
3887 | ? CALL_LIBCALL : CALL_NORMAL); | |
4cc833b7 | 3888 | cum->sysv_gregno = GP_ARG_MIN_REG; |
a6c9bed4 AH |
3889 | cum->stdarg = fntype |
3890 | && (TYPE_ARG_TYPES (fntype) != 0 | |
3891 | && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype))) | |
3892 | != void_type_node)); | |
4697a36c | 3893 | |
0f6937fe AM |
3894 | cum->nargs_prototype = 0; |
3895 | if (incoming || cum->prototype) | |
3896 | cum->nargs_prototype = n_named_args; | |
4697a36c | 3897 | |
a5c76ee6 | 3898 | /* Check for a longcall attribute. */ |
3eb4e360 AM |
3899 | if ((!fntype && rs6000_default_long_calls) |
3900 | || (fntype | |
3901 | && lookup_attribute ("longcall", TYPE_ATTRIBUTES (fntype)) | |
3902 | && !lookup_attribute ("shortcall", TYPE_ATTRIBUTES (fntype)))) | |
3903 | cum->call_cookie |= CALL_LONG; | |
6a4cee5f | 3904 | |
4697a36c MM |
3905 | if (TARGET_DEBUG_ARG) |
3906 | { | |
3907 | fprintf (stderr, "\ninit_cumulative_args:"); | |
3908 | if (fntype) | |
3909 | { | |
3910 | tree ret_type = TREE_TYPE (fntype); | |
3911 | fprintf (stderr, " ret code = %s,", | |
3912 | tree_code_name[ (int)TREE_CODE (ret_type) ]); | |
3913 | } | |
3914 | ||
6a4cee5f MM |
3915 | if (cum->call_cookie & CALL_LONG) |
3916 | fprintf (stderr, " longcall,"); | |
3917 | ||
4697a36c MM |
3918 | fprintf (stderr, " proto = %d, nargs = %d\n", |
3919 | cum->prototype, cum->nargs_prototype); | |
3920 | } | |
f676971a | 3921 | |
c4ad648e AM |
3922 | if (fntype |
3923 | && !TARGET_ALTIVEC | |
3924 | && TARGET_ALTIVEC_ABI | |
3925 | && ALTIVEC_VECTOR_MODE (TYPE_MODE (TREE_TYPE (fntype)))) | |
3926 | { | |
3927 | error ("Cannot return value in vector register because" | |
3928 | " altivec instructions are disabled, use -maltivec" | |
3929 | " to enable them."); | |
3930 | } | |
4697a36c MM |
3931 | } |
3932 | \f | |
fe984136 RH |
3933 | /* Return true if TYPE must be passed on the stack and not in registers. */ |
3934 | ||
3935 | static bool | |
3936 | rs6000_must_pass_in_stack (enum machine_mode mode, tree type) | |
3937 | { | |
3938 | if (DEFAULT_ABI == ABI_AIX || TARGET_64BIT) | |
3939 | return must_pass_in_stack_var_size (mode, type); | |
3940 | else | |
3941 | return must_pass_in_stack_var_size_or_pad (mode, type); | |
3942 | } | |
3943 | ||
c229cba9 DE |
3944 | /* If defined, a C expression which determines whether, and in which |
3945 | direction, to pad out an argument with extra space. The value | |
3946 | should be of type `enum direction': either `upward' to pad above | |
3947 | the argument, `downward' to pad below, or `none' to inhibit | |
3948 | padding. | |
3949 | ||
3950 | For the AIX ABI structs are always stored left shifted in their | |
3951 | argument slot. */ | |
3952 | ||
9ebbca7d | 3953 | enum direction |
a2369ed3 | 3954 | function_arg_padding (enum machine_mode mode, tree type) |
c229cba9 | 3955 | { |
6e985040 AM |
3956 | #ifndef AGGREGATE_PADDING_FIXED |
3957 | #define AGGREGATE_PADDING_FIXED 0 | |
3958 | #endif | |
3959 | #ifndef AGGREGATES_PAD_UPWARD_ALWAYS | |
3960 | #define AGGREGATES_PAD_UPWARD_ALWAYS 0 | |
3961 | #endif | |
3962 | ||
3963 | if (!AGGREGATE_PADDING_FIXED) | |
3964 | { | |
3965 | /* GCC used to pass structures of the same size as integer types as | |
3966 | if they were in fact integers, ignoring FUNCTION_ARG_PADDING. | |
19525b57 | 3967 | i.e. Structures of size 1 or 2 (or 4 when TARGET_64BIT) were |
6e985040 AM |
3968 | passed padded downward, except that -mstrict-align further |
3969 | muddied the water in that multi-component structures of 2 and 4 | |
3970 | bytes in size were passed padded upward. | |
3971 | ||
3972 | The following arranges for best compatibility with previous | |
3973 | versions of gcc, but removes the -mstrict-align dependency. */ | |
3974 | if (BYTES_BIG_ENDIAN) | |
3975 | { | |
3976 | HOST_WIDE_INT size = 0; | |
3977 | ||
3978 | if (mode == BLKmode) | |
3979 | { | |
3980 | if (type && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST) | |
3981 | size = int_size_in_bytes (type); | |
3982 | } | |
3983 | else | |
3984 | size = GET_MODE_SIZE (mode); | |
3985 | ||
3986 | if (size == 1 || size == 2 || size == 4) | |
3987 | return downward; | |
3988 | } | |
3989 | return upward; | |
3990 | } | |
3991 | ||
3992 | if (AGGREGATES_PAD_UPWARD_ALWAYS) | |
3993 | { | |
3994 | if (type != 0 && AGGREGATE_TYPE_P (type)) | |
3995 | return upward; | |
3996 | } | |
c229cba9 | 3997 | |
d3704c46 KH |
3998 | /* Fall back to the default. */ |
3999 | return DEFAULT_FUNCTION_ARG_PADDING (mode, type); | |
c229cba9 DE |
4000 | } |
4001 | ||
b6c9286a | 4002 | /* If defined, a C expression that gives the alignment boundary, in bits, |
f676971a | 4003 | of an argument with the specified mode and type. If it is not defined, |
b6c9286a | 4004 | PARM_BOUNDARY is used for all arguments. |
f676971a | 4005 | |
b693336b PB |
4006 | V.4 wants long longs to be double word aligned. |
4007 | Doubleword align SPE vectors. | |
4008 | Quadword align Altivec vectors. | |
4009 | Quadword align large synthetic vector types. */ | |
b6c9286a MM |
4010 | |
4011 | int | |
b693336b | 4012 | function_arg_boundary (enum machine_mode mode, tree type) |
b6c9286a | 4013 | { |
4ed78545 AM |
4014 | if (DEFAULT_ABI == ABI_V4 && GET_MODE_SIZE (mode) == 8) |
4015 | return 64; | |
ad630bef DE |
4016 | else if (SPE_VECTOR_MODE (mode) |
4017 | || (type && TREE_CODE (type) == VECTOR_TYPE | |
4018 | && int_size_in_bytes (type) >= 8 | |
4019 | && int_size_in_bytes (type) < 16)) | |
e1f83b4d | 4020 | return 64; |
ad630bef DE |
4021 | else if (ALTIVEC_VECTOR_MODE (mode) |
4022 | || (type && TREE_CODE (type) == VECTOR_TYPE | |
4023 | && int_size_in_bytes (type) >= 16)) | |
0ac081f6 | 4024 | return 128; |
0b5383eb DJ |
4025 | else if (rs6000_darwin64_abi && mode == BLKmode |
4026 | && type && TYPE_ALIGN (type) > 64) | |
4027 | return 128; | |
9ebbca7d | 4028 | else |
b6c9286a | 4029 | return PARM_BOUNDARY; |
b6c9286a | 4030 | } |
c53bdcf5 | 4031 | |
294bd182 AM |
4032 | /* For a function parm of MODE and TYPE, return the starting word in |
4033 | the parameter area. NWORDS of the parameter area are already used. */ | |
4034 | ||
4035 | static unsigned int | |
4036 | rs6000_parm_start (enum machine_mode mode, tree type, unsigned int nwords) | |
4037 | { | |
4038 | unsigned int align; | |
4039 | unsigned int parm_offset; | |
4040 | ||
4041 | align = function_arg_boundary (mode, type) / PARM_BOUNDARY - 1; | |
4042 | parm_offset = DEFAULT_ABI == ABI_V4 ? 2 : 6; | |
4043 | return nwords + (-(parm_offset + nwords) & align); | |
4044 | } | |
4045 | ||
c53bdcf5 AM |
4046 | /* Compute the size (in words) of a function argument. */ |
4047 | ||
4048 | static unsigned long | |
4049 | rs6000_arg_size (enum machine_mode mode, tree type) | |
4050 | { | |
4051 | unsigned long size; | |
4052 | ||
4053 | if (mode != BLKmode) | |
4054 | size = GET_MODE_SIZE (mode); | |
4055 | else | |
4056 | size = int_size_in_bytes (type); | |
4057 | ||
4058 | if (TARGET_32BIT) | |
4059 | return (size + 3) >> 2; | |
4060 | else | |
4061 | return (size + 7) >> 3; | |
4062 | } | |
b6c9286a | 4063 | \f |
0b5383eb | 4064 | /* Use this to flush pending int fields. */ |
594a51fe SS |
4065 | |
4066 | static void | |
0b5383eb DJ |
4067 | rs6000_darwin64_record_arg_advance_flush (CUMULATIVE_ARGS *cum, |
4068 | HOST_WIDE_INT bitpos) | |
594a51fe | 4069 | { |
0b5383eb DJ |
4070 | unsigned int startbit, endbit; |
4071 | int intregs, intoffset; | |
4072 | enum machine_mode mode; | |
594a51fe | 4073 | |
0b5383eb DJ |
4074 | if (cum->intoffset == -1) |
4075 | return; | |
594a51fe | 4076 | |
0b5383eb DJ |
4077 | intoffset = cum->intoffset; |
4078 | cum->intoffset = -1; | |
4079 | ||
4080 | if (intoffset % BITS_PER_WORD != 0) | |
4081 | { | |
4082 | mode = mode_for_size (BITS_PER_WORD - intoffset % BITS_PER_WORD, | |
4083 | MODE_INT, 0); | |
4084 | if (mode == BLKmode) | |
594a51fe | 4085 | { |
0b5383eb DJ |
4086 | /* We couldn't find an appropriate mode, which happens, |
4087 | e.g., in packed structs when there are 3 bytes to load. | |
4088 | Back intoffset back to the beginning of the word in this | |
4089 | case. */ | |
4090 | intoffset = intoffset & -BITS_PER_WORD; | |
594a51fe | 4091 | } |
594a51fe | 4092 | } |
0b5383eb DJ |
4093 | |
4094 | startbit = intoffset & -BITS_PER_WORD; | |
4095 | endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD; | |
4096 | intregs = (endbit - startbit) / BITS_PER_WORD; | |
4097 | cum->words += intregs; | |
4098 | } | |
4099 | ||
4100 | /* The darwin64 ABI calls for us to recurse down through structs, | |
4101 | looking for elements passed in registers. Unfortunately, we have | |
4102 | to track int register count here also because of misalignments | |
4103 | in powerpc alignment mode. */ | |
4104 | ||
4105 | static void | |
4106 | rs6000_darwin64_record_arg_advance_recurse (CUMULATIVE_ARGS *cum, | |
4107 | tree type, | |
4108 | HOST_WIDE_INT startbitpos) | |
4109 | { | |
4110 | tree f; | |
4111 | ||
4112 | for (f = TYPE_FIELDS (type); f ; f = TREE_CHAIN (f)) | |
4113 | if (TREE_CODE (f) == FIELD_DECL) | |
4114 | { | |
4115 | HOST_WIDE_INT bitpos = startbitpos; | |
4116 | tree ftype = TREE_TYPE (f); | |
4117 | enum machine_mode mode = TYPE_MODE (ftype); | |
4118 | ||
4119 | if (DECL_SIZE (f) != 0 | |
4120 | && host_integerp (bit_position (f), 1)) | |
4121 | bitpos += int_bit_position (f); | |
4122 | ||
4123 | /* ??? FIXME: else assume zero offset. */ | |
4124 | ||
4125 | if (TREE_CODE (ftype) == RECORD_TYPE) | |
4126 | rs6000_darwin64_record_arg_advance_recurse (cum, ftype, bitpos); | |
4127 | else if (USE_FP_FOR_ARG_P (cum, mode, ftype)) | |
4128 | { | |
4129 | rs6000_darwin64_record_arg_advance_flush (cum, bitpos); | |
4130 | cum->fregno += (GET_MODE_SIZE (mode) + 7) >> 3; | |
4131 | cum->words += (GET_MODE_SIZE (mode) + 7) >> 3; | |
4132 | } | |
4133 | else if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, 1)) | |
4134 | { | |
4135 | rs6000_darwin64_record_arg_advance_flush (cum, bitpos); | |
4136 | cum->vregno++; | |
4137 | cum->words += 2; | |
4138 | } | |
4139 | else if (cum->intoffset == -1) | |
4140 | cum->intoffset = bitpos; | |
4141 | } | |
594a51fe SS |
4142 | } |
4143 | ||
4697a36c MM |
4144 | /* Update the data in CUM to advance over an argument |
4145 | of mode MODE and data type TYPE. | |
b2d04ecf AM |
4146 | (TYPE is null for libcalls where that information may not be available.) |
4147 | ||
4148 | Note that for args passed by reference, function_arg will be called | |
4149 | with MODE and TYPE set to that of the pointer to the arg, not the arg | |
4150 | itself. */ | |
4697a36c MM |
4151 | |
4152 | void | |
f676971a | 4153 | function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode, |
594a51fe | 4154 | tree type, int named, int depth) |
4697a36c | 4155 | { |
0b5383eb DJ |
4156 | int size; |
4157 | ||
594a51fe SS |
4158 | /* Only tick off an argument if we're not recursing. */ |
4159 | if (depth == 0) | |
4160 | cum->nargs_prototype--; | |
4697a36c | 4161 | |
ad630bef DE |
4162 | if (TARGET_ALTIVEC_ABI |
4163 | && (ALTIVEC_VECTOR_MODE (mode) | |
4164 | || (type && TREE_CODE (type) == VECTOR_TYPE | |
4165 | && int_size_in_bytes (type) == 16))) | |
0ac081f6 | 4166 | { |
4ed78545 AM |
4167 | bool stack = false; |
4168 | ||
2858f73a | 4169 | if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named)) |
c4ad648e | 4170 | { |
6d0ef01e HP |
4171 | cum->vregno++; |
4172 | if (!TARGET_ALTIVEC) | |
4173 | error ("Cannot pass argument in vector register because" | |
4174 | " altivec instructions are disabled, use -maltivec" | |
4175 | " to enable them."); | |
4ed78545 AM |
4176 | |
4177 | /* PowerPC64 Linux and AIX allocate GPRs for a vector argument | |
f676971a | 4178 | even if it is going to be passed in a vector register. |
4ed78545 AM |
4179 | Darwin does the same for variable-argument functions. */ |
4180 | if ((DEFAULT_ABI == ABI_AIX && TARGET_64BIT) | |
4181 | || (cum->stdarg && DEFAULT_ABI != ABI_V4)) | |
4182 | stack = true; | |
6d0ef01e | 4183 | } |
4ed78545 AM |
4184 | else |
4185 | stack = true; | |
4186 | ||
4187 | if (stack) | |
c4ad648e | 4188 | { |
a594a19c | 4189 | int align; |
f676971a | 4190 | |
2858f73a GK |
4191 | /* Vector parameters must be 16-byte aligned. This places |
4192 | them at 2 mod 4 in terms of words in 32-bit mode, since | |
4193 | the parameter save area starts at offset 24 from the | |
4194 | stack. In 64-bit mode, they just have to start on an | |
4195 | even word, since the parameter save area is 16-byte | |
4196 | aligned. Space for GPRs is reserved even if the argument | |
4197 | will be passed in memory. */ | |
4198 | if (TARGET_32BIT) | |
4ed78545 | 4199 | align = (2 - cum->words) & 3; |
2858f73a GK |
4200 | else |
4201 | align = cum->words & 1; | |
c53bdcf5 | 4202 | cum->words += align + rs6000_arg_size (mode, type); |
f676971a | 4203 | |
a594a19c GK |
4204 | if (TARGET_DEBUG_ARG) |
4205 | { | |
f676971a | 4206 | fprintf (stderr, "function_adv: words = %2d, align=%d, ", |
a594a19c GK |
4207 | cum->words, align); |
4208 | fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s\n", | |
f676971a | 4209 | cum->nargs_prototype, cum->prototype, |
2858f73a | 4210 | GET_MODE_NAME (mode)); |
a594a19c GK |
4211 | } |
4212 | } | |
0ac081f6 | 4213 | } |
a4b0320c | 4214 | else if (TARGET_SPE_ABI && TARGET_SPE && SPE_VECTOR_MODE (mode) |
a6c9bed4 AH |
4215 | && !cum->stdarg |
4216 | && cum->sysv_gregno <= GP_ARG_MAX_REG) | |
a4b0320c | 4217 | cum->sysv_gregno++; |
594a51fe SS |
4218 | |
4219 | else if (rs6000_darwin64_abi | |
4220 | && mode == BLKmode | |
0b5383eb DJ |
4221 | && TREE_CODE (type) == RECORD_TYPE |
4222 | && (size = int_size_in_bytes (type)) > 0) | |
4223 | { | |
4224 | /* Variable sized types have size == -1 and are | |
4225 | treated as if consisting entirely of ints. | |
4226 | Pad to 16 byte boundary if needed. */ | |
4227 | if (TYPE_ALIGN (type) >= 2 * BITS_PER_WORD | |
4228 | && (cum->words % 2) != 0) | |
4229 | cum->words++; | |
4230 | /* For varargs, we can just go up by the size of the struct. */ | |
4231 | if (!named) | |
4232 | cum->words += (size + 7) / 8; | |
4233 | else | |
4234 | { | |
4235 | /* It is tempting to say int register count just goes up by | |
4236 | sizeof(type)/8, but this is wrong in a case such as | |
4237 | { int; double; int; } [powerpc alignment]. We have to | |
4238 | grovel through the fields for these too. */ | |
4239 | cum->intoffset = 0; | |
4240 | rs6000_darwin64_record_arg_advance_recurse (cum, type, 0); | |
4241 | rs6000_darwin64_record_arg_advance_flush (cum, | |
4242 | size * BITS_PER_UNIT); | |
4243 | } | |
4244 | } | |
f607bc57 | 4245 | else if (DEFAULT_ABI == ABI_V4) |
4697a36c | 4246 | { |
a3170dc6 | 4247 | if (TARGET_HARD_FLOAT && TARGET_FPRS |
4cc833b7 | 4248 | && (mode == SFmode || mode == DFmode)) |
4697a36c | 4249 | { |
4cc833b7 RH |
4250 | if (cum->fregno <= FP_ARG_V4_MAX_REG) |
4251 | cum->fregno++; | |
4252 | else | |
4253 | { | |
4254 | if (mode == DFmode) | |
c4ad648e | 4255 | cum->words += cum->words & 1; |
c53bdcf5 | 4256 | cum->words += rs6000_arg_size (mode, type); |
4cc833b7 | 4257 | } |
4697a36c | 4258 | } |
4cc833b7 RH |
4259 | else |
4260 | { | |
b2d04ecf | 4261 | int n_words = rs6000_arg_size (mode, type); |
4cc833b7 RH |
4262 | int gregno = cum->sysv_gregno; |
4263 | ||
4ed78545 AM |
4264 | /* Long long and SPE vectors are put in (r3,r4), (r5,r6), |
4265 | (r7,r8) or (r9,r10). As does any other 2 word item such | |
4266 | as complex int due to a historical mistake. */ | |
4267 | if (n_words == 2) | |
4268 | gregno += (1 - gregno) & 1; | |
4cc833b7 | 4269 | |
4ed78545 | 4270 | /* Multi-reg args are not split between registers and stack. */ |
4cc833b7 RH |
4271 | if (gregno + n_words - 1 > GP_ARG_MAX_REG) |
4272 | { | |
4ed78545 AM |
4273 | /* Long long and SPE vectors are aligned on the stack. |
4274 | So are other 2 word items such as complex int due to | |
4275 | a historical mistake. */ | |
4cc833b7 RH |
4276 | if (n_words == 2) |
4277 | cum->words += cum->words & 1; | |
4278 | cum->words += n_words; | |
4279 | } | |
4697a36c | 4280 | |
4cc833b7 RH |
4281 | /* Note: continuing to accumulate gregno past when we've started |
4282 | spilling to the stack indicates the fact that we've started | |
4283 | spilling to the stack to expand_builtin_saveregs. */ | |
4284 | cum->sysv_gregno = gregno + n_words; | |
4285 | } | |
4697a36c | 4286 | |
4cc833b7 RH |
4287 | if (TARGET_DEBUG_ARG) |
4288 | { | |
4289 | fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ", | |
4290 | cum->words, cum->fregno); | |
4291 | fprintf (stderr, "gregno = %2d, nargs = %4d, proto = %d, ", | |
4292 | cum->sysv_gregno, cum->nargs_prototype, cum->prototype); | |
4293 | fprintf (stderr, "mode = %4s, named = %d\n", | |
4294 | GET_MODE_NAME (mode), named); | |
4295 | } | |
4697a36c MM |
4296 | } |
4297 | else | |
4cc833b7 | 4298 | { |
b2d04ecf | 4299 | int n_words = rs6000_arg_size (mode, type); |
294bd182 AM |
4300 | int start_words = cum->words; |
4301 | int align_words = rs6000_parm_start (mode, type, start_words); | |
a4f6c312 | 4302 | |
294bd182 | 4303 | cum->words = align_words + n_words; |
4697a36c | 4304 | |
a3170dc6 AH |
4305 | if (GET_MODE_CLASS (mode) == MODE_FLOAT |
4306 | && TARGET_HARD_FLOAT && TARGET_FPRS) | |
c53bdcf5 | 4307 | cum->fregno += (GET_MODE_SIZE (mode) + 7) >> 3; |
4cc833b7 RH |
4308 | |
4309 | if (TARGET_DEBUG_ARG) | |
4310 | { | |
4311 | fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ", | |
4312 | cum->words, cum->fregno); | |
4313 | fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s, ", | |
4314 | cum->nargs_prototype, cum->prototype, GET_MODE_NAME (mode)); | |
594a51fe | 4315 | fprintf (stderr, "named = %d, align = %d, depth = %d\n", |
294bd182 | 4316 | named, align_words - start_words, depth); |
4cc833b7 RH |
4317 | } |
4318 | } | |
4697a36c | 4319 | } |
a6c9bed4 | 4320 | |
f82f556d AH |
4321 | static rtx |
4322 | spe_build_register_parallel (enum machine_mode mode, int gregno) | |
4323 | { | |
54b695e7 | 4324 | rtx r1, r3; |
f82f556d | 4325 | |
37409796 | 4326 | switch (mode) |
f82f556d | 4327 | { |
37409796 | 4328 | case DFmode: |
54b695e7 AH |
4329 | r1 = gen_rtx_REG (DImode, gregno); |
4330 | r1 = gen_rtx_EXPR_LIST (VOIDmode, r1, const0_rtx); | |
4331 | return gen_rtx_PARALLEL (mode, gen_rtvec (1, r1)); | |
37409796 NS |
4332 | |
4333 | case DCmode: | |
54b695e7 AH |
4334 | r1 = gen_rtx_REG (DImode, gregno); |
4335 | r1 = gen_rtx_EXPR_LIST (VOIDmode, r1, const0_rtx); | |
4336 | r3 = gen_rtx_REG (DImode, gregno + 2); | |
4337 | r3 = gen_rtx_EXPR_LIST (VOIDmode, r3, GEN_INT (8)); | |
4338 | return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r3)); | |
37409796 NS |
4339 | |
4340 | default: | |
4341 | gcc_unreachable (); | |
f82f556d | 4342 | } |
f82f556d | 4343 | } |
b78d48dd | 4344 | |
f82f556d | 4345 | /* Determine where to put a SIMD argument on the SPE. */ |
a6c9bed4 | 4346 | static rtx |
f676971a | 4347 | rs6000_spe_function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode, |
a2369ed3 | 4348 | tree type) |
a6c9bed4 | 4349 | { |
f82f556d AH |
4350 | int gregno = cum->sysv_gregno; |
4351 | ||
4352 | /* On E500 v2, double arithmetic is done on the full 64-bit GPR, but | |
600e1f95 | 4353 | are passed and returned in a pair of GPRs for ABI compatibility. */ |
18f63bfa | 4354 | if (TARGET_E500_DOUBLE && (mode == DFmode || mode == DCmode)) |
f82f556d | 4355 | { |
b5870bee AH |
4356 | int n_words = rs6000_arg_size (mode, type); |
4357 | ||
f82f556d | 4358 | /* Doubles go in an odd/even register pair (r5/r6, etc). */ |
b5870bee AH |
4359 | if (mode == DFmode) |
4360 | gregno += (1 - gregno) & 1; | |
f82f556d | 4361 | |
b5870bee AH |
4362 | /* Multi-reg args are not split between registers and stack. */ |
4363 | if (gregno + n_words - 1 > GP_ARG_MAX_REG) | |
f82f556d AH |
4364 | return NULL_RTX; |
4365 | ||
4366 | return spe_build_register_parallel (mode, gregno); | |
4367 | } | |
a6c9bed4 AH |
4368 | if (cum->stdarg) |
4369 | { | |
c53bdcf5 | 4370 | int n_words = rs6000_arg_size (mode, type); |
a6c9bed4 AH |
4371 | |
4372 | /* SPE vectors are put in odd registers. */ | |
4373 | if (n_words == 2 && (gregno & 1) == 0) | |
4374 | gregno += 1; | |
4375 | ||
4376 | if (gregno + n_words - 1 <= GP_ARG_MAX_REG) | |
4377 | { | |
4378 | rtx r1, r2; | |
4379 | enum machine_mode m = SImode; | |
4380 | ||
4381 | r1 = gen_rtx_REG (m, gregno); | |
4382 | r1 = gen_rtx_EXPR_LIST (m, r1, const0_rtx); | |
4383 | r2 = gen_rtx_REG (m, gregno + 1); | |
4384 | r2 = gen_rtx_EXPR_LIST (m, r2, GEN_INT (4)); | |
4385 | return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r2)); | |
4386 | } | |
4387 | else | |
b78d48dd | 4388 | return NULL_RTX; |
a6c9bed4 AH |
4389 | } |
4390 | else | |
4391 | { | |
f82f556d AH |
4392 | if (gregno <= GP_ARG_MAX_REG) |
4393 | return gen_rtx_REG (mode, gregno); | |
a6c9bed4 | 4394 | else |
b78d48dd | 4395 | return NULL_RTX; |
a6c9bed4 AH |
4396 | } |
4397 | } | |
4398 | ||
0b5383eb DJ |
4399 | /* A subroutine of rs6000_darwin64_record_arg. Assign the bits of the |
4400 | structure between cum->intoffset and bitpos to integer registers. */ | |
594a51fe | 4401 | |
0b5383eb DJ |
4402 | static void |
4403 | rs6000_darwin64_record_arg_flush (CUMULATIVE_ARGS *cum, | |
4404 | HOST_WIDE_INT bitpos, rtx rvec[], int *k) | |
594a51fe | 4405 | { |
0b5383eb DJ |
4406 | enum machine_mode mode; |
4407 | unsigned int regno; | |
4408 | unsigned int startbit, endbit; | |
4409 | int this_regno, intregs, intoffset; | |
4410 | rtx reg; | |
594a51fe | 4411 | |
0b5383eb DJ |
4412 | if (cum->intoffset == -1) |
4413 | return; | |
4414 | ||
4415 | intoffset = cum->intoffset; | |
4416 | cum->intoffset = -1; | |
4417 | ||
4418 | /* If this is the trailing part of a word, try to only load that | |
4419 | much into the register. Otherwise load the whole register. Note | |
4420 | that in the latter case we may pick up unwanted bits. It's not a | |
4421 | problem at the moment but may wish to revisit. */ | |
4422 | ||
4423 | if (intoffset % BITS_PER_WORD != 0) | |
594a51fe | 4424 | { |
0b5383eb DJ |
4425 | mode = mode_for_size (BITS_PER_WORD - intoffset % BITS_PER_WORD, |
4426 | MODE_INT, 0); | |
4427 | if (mode == BLKmode) | |
4428 | { | |
4429 | /* We couldn't find an appropriate mode, which happens, | |
4430 | e.g., in packed structs when there are 3 bytes to load. | |
4431 | Back intoffset back to the beginning of the word in this | |
4432 | case. */ | |
4433 | intoffset = intoffset & -BITS_PER_WORD; | |
4434 | mode = word_mode; | |
4435 | } | |
4436 | } | |
4437 | else | |
4438 | mode = word_mode; | |
4439 | ||
4440 | startbit = intoffset & -BITS_PER_WORD; | |
4441 | endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD; | |
4442 | intregs = (endbit - startbit) / BITS_PER_WORD; | |
4443 | this_regno = cum->words + intoffset / BITS_PER_WORD; | |
4444 | ||
4445 | if (intregs > 0 && intregs > GP_ARG_NUM_REG - this_regno) | |
4446 | cum->use_stack = 1; | |
4447 | ||
4448 | intregs = MIN (intregs, GP_ARG_NUM_REG - this_regno); | |
4449 | if (intregs <= 0) | |
4450 | return; | |
4451 | ||
4452 | intoffset /= BITS_PER_UNIT; | |
4453 | do | |
4454 | { | |
4455 | regno = GP_ARG_MIN_REG + this_regno; | |
4456 | reg = gen_rtx_REG (mode, regno); | |
4457 | rvec[(*k)++] = | |
4458 | gen_rtx_EXPR_LIST (VOIDmode, reg, GEN_INT (intoffset)); | |
4459 | ||
4460 | this_regno += 1; | |
4461 | intoffset = (intoffset | (UNITS_PER_WORD-1)) + 1; | |
4462 | mode = word_mode; | |
4463 | intregs -= 1; | |
4464 | } | |
4465 | while (intregs > 0); | |
4466 | } | |
4467 | ||
4468 | /* Recursive workhorse for the following. */ | |
4469 | ||
4470 | static void | |
4471 | rs6000_darwin64_record_arg_recurse (CUMULATIVE_ARGS *cum, tree type, | |
4472 | HOST_WIDE_INT startbitpos, rtx rvec[], | |
4473 | int *k) | |
4474 | { | |
4475 | tree f; | |
4476 | ||
4477 | for (f = TYPE_FIELDS (type); f ; f = TREE_CHAIN (f)) | |
4478 | if (TREE_CODE (f) == FIELD_DECL) | |
4479 | { | |
4480 | HOST_WIDE_INT bitpos = startbitpos; | |
4481 | tree ftype = TREE_TYPE (f); | |
4482 | enum machine_mode mode = TYPE_MODE (ftype); | |
4483 | ||
4484 | if (DECL_SIZE (f) != 0 | |
4485 | && host_integerp (bit_position (f), 1)) | |
4486 | bitpos += int_bit_position (f); | |
4487 | ||
4488 | /* ??? FIXME: else assume zero offset. */ | |
4489 | ||
4490 | if (TREE_CODE (ftype) == RECORD_TYPE) | |
4491 | rs6000_darwin64_record_arg_recurse (cum, ftype, bitpos, rvec, k); | |
4492 | else if (cum->named && USE_FP_FOR_ARG_P (cum, mode, ftype)) | |
594a51fe | 4493 | { |
0b5383eb DJ |
4494 | #if 0 |
4495 | switch (mode) | |
594a51fe | 4496 | { |
0b5383eb DJ |
4497 | case SCmode: mode = SFmode; break; |
4498 | case DCmode: mode = DFmode; break; | |
4499 | case TCmode: mode = TFmode; break; | |
4500 | default: break; | |
594a51fe | 4501 | } |
0b5383eb DJ |
4502 | #endif |
4503 | rs6000_darwin64_record_arg_flush (cum, bitpos, rvec, k); | |
4504 | rvec[(*k)++] | |
4505 | = gen_rtx_EXPR_LIST (VOIDmode, | |
4506 | gen_rtx_REG (mode, cum->fregno++), | |
4507 | GEN_INT (bitpos / BITS_PER_UNIT)); | |
4508 | if (mode == TFmode) | |
4509 | cum->fregno++; | |
594a51fe | 4510 | } |
0b5383eb DJ |
4511 | else if (cum->named && USE_ALTIVEC_FOR_ARG_P (cum, mode, ftype, 1)) |
4512 | { | |
4513 | rs6000_darwin64_record_arg_flush (cum, bitpos, rvec, k); | |
4514 | rvec[(*k)++] | |
4515 | = gen_rtx_EXPR_LIST (VOIDmode, | |
4516 | gen_rtx_REG (mode, cum->vregno++), | |
4517 | GEN_INT (bitpos / BITS_PER_UNIT)); | |
4518 | } | |
4519 | else if (cum->intoffset == -1) | |
4520 | cum->intoffset = bitpos; | |
4521 | } | |
4522 | } | |
594a51fe | 4523 | |
0b5383eb DJ |
4524 | /* For the darwin64 ABI, we want to construct a PARALLEL consisting of |
4525 | the register(s) to be used for each field and subfield of a struct | |
4526 | being passed by value, along with the offset of where the | |
4527 | register's value may be found in the block. FP fields go in FP | |
4528 | register, vector fields go in vector registers, and everything | |
4529 | else goes in int registers, packed as in memory. | |
8ff40a74 | 4530 | |
0b5383eb DJ |
4531 | This code is also used for function return values. RETVAL indicates |
4532 | whether this is the case. | |
8ff40a74 | 4533 | |
0b5383eb DJ |
4534 | Much of this is taken from the Sparc V9 port, which has a similar |
4535 | calling convention. */ | |
594a51fe | 4536 | |
0b5383eb DJ |
4537 | static rtx |
4538 | rs6000_darwin64_record_arg (CUMULATIVE_ARGS *orig_cum, tree type, | |
4539 | int named, bool retval) | |
4540 | { | |
4541 | rtx rvec[FIRST_PSEUDO_REGISTER]; | |
4542 | int k = 1, kbase = 1; | |
4543 | HOST_WIDE_INT typesize = int_size_in_bytes (type); | |
4544 | /* This is a copy; modifications are not visible to our caller. */ | |
4545 | CUMULATIVE_ARGS copy_cum = *orig_cum; | |
4546 | CUMULATIVE_ARGS *cum = ©_cum; | |
4547 | ||
4548 | /* Pad to 16 byte boundary if needed. */ | |
4549 | if (!retval && TYPE_ALIGN (type) >= 2 * BITS_PER_WORD | |
4550 | && (cum->words % 2) != 0) | |
4551 | cum->words++; | |
4552 | ||
4553 | cum->intoffset = 0; | |
4554 | cum->use_stack = 0; | |
4555 | cum->named = named; | |
4556 | ||
4557 | /* Put entries into rvec[] for individual FP and vector fields, and | |
4558 | for the chunks of memory that go in int regs. Note we start at | |
4559 | element 1; 0 is reserved for an indication of using memory, and | |
4560 | may or may not be filled in below. */ | |
4561 | rs6000_darwin64_record_arg_recurse (cum, type, 0, rvec, &k); | |
4562 | rs6000_darwin64_record_arg_flush (cum, typesize * BITS_PER_UNIT, rvec, &k); | |
4563 | ||
4564 | /* If any part of the struct went on the stack put all of it there. | |
4565 | This hack is because the generic code for | |
4566 | FUNCTION_ARG_PARTIAL_NREGS cannot handle cases where the register | |
4567 | parts of the struct are not at the beginning. */ | |
4568 | if (cum->use_stack) | |
4569 | { | |
4570 | if (retval) | |
4571 | return NULL_RTX; /* doesn't go in registers at all */ | |
4572 | kbase = 0; | |
4573 | rvec[0] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx); | |
4574 | } | |
4575 | if (k > 1 || cum->use_stack) | |
4576 | return gen_rtx_PARALLEL (BLKmode, gen_rtvec_v (k - kbase, &rvec[kbase])); | |
594a51fe SS |
4577 | else |
4578 | return NULL_RTX; | |
4579 | } | |
4580 | ||
b78d48dd FJ |
4581 | /* Determine where to place an argument in 64-bit mode with 32-bit ABI. */ |
4582 | ||
4583 | static rtx | |
ec6376ab | 4584 | rs6000_mixed_function_arg (enum machine_mode mode, tree type, int align_words) |
b78d48dd | 4585 | { |
ec6376ab AM |
4586 | int n_units; |
4587 | int i, k; | |
4588 | rtx rvec[GP_ARG_NUM_REG + 1]; | |
4589 | ||
4590 | if (align_words >= GP_ARG_NUM_REG) | |
4591 | return NULL_RTX; | |
4592 | ||
4593 | n_units = rs6000_arg_size (mode, type); | |
4594 | ||
4595 | /* Optimize the simple case where the arg fits in one gpr, except in | |
4596 | the case of BLKmode due to assign_parms assuming that registers are | |
4597 | BITS_PER_WORD wide. */ | |
4598 | if (n_units == 0 | |
4599 | || (n_units == 1 && mode != BLKmode)) | |
4600 | return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words); | |
4601 | ||
4602 | k = 0; | |
4603 | if (align_words + n_units > GP_ARG_NUM_REG) | |
4604 | /* Not all of the arg fits in gprs. Say that it goes in memory too, | |
4605 | using a magic NULL_RTX component. | |
4606 | FIXME: This is not strictly correct. Only some of the arg | |
4607 | belongs in memory, not all of it. However, there isn't any way | |
4608 | to do this currently, apart from building rtx descriptions for | |
4609 | the pieces of memory we want stored. Due to bugs in the generic | |
4610 | code we can't use the normal function_arg_partial_nregs scheme | |
4611 | with the PARALLEL arg description we emit here. | |
4612 | In any case, the code to store the whole arg to memory is often | |
4613 | more efficient than code to store pieces, and we know that space | |
4614 | is available in the right place for the whole arg. */ | |
78a52f11 RH |
4615 | /* FIXME: This should be fixed since the conversion to |
4616 | TARGET_ARG_PARTIAL_BYTES. */ | |
ec6376ab AM |
4617 | rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx); |
4618 | ||
4619 | i = 0; | |
4620 | do | |
36a454e1 | 4621 | { |
ec6376ab AM |
4622 | rtx r = gen_rtx_REG (SImode, GP_ARG_MIN_REG + align_words); |
4623 | rtx off = GEN_INT (i++ * 4); | |
4624 | rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off); | |
36a454e1 | 4625 | } |
ec6376ab AM |
4626 | while (++align_words < GP_ARG_NUM_REG && --n_units != 0); |
4627 | ||
4628 | return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec)); | |
b78d48dd FJ |
4629 | } |
4630 | ||
4697a36c MM |
4631 | /* Determine where to put an argument to a function. |
4632 | Value is zero to push the argument on the stack, | |
4633 | or a hard register in which to store the argument. | |
4634 | ||
4635 | MODE is the argument's machine mode. | |
4636 | TYPE is the data type of the argument (as a tree). | |
4637 | This is null for libcalls where that information may | |
4638 | not be available. | |
4639 | CUM is a variable of type CUMULATIVE_ARGS which gives info about | |
0b5383eb DJ |
4640 | the preceding args and about the function being called. It is |
4641 | not modified in this routine. | |
4697a36c MM |
4642 | NAMED is nonzero if this argument is a named parameter |
4643 | (otherwise it is an extra parameter matching an ellipsis). | |
4644 | ||
4645 | On RS/6000 the first eight words of non-FP are normally in registers | |
4646 | and the rest are pushed. Under AIX, the first 13 FP args are in registers. | |
4647 | Under V.4, the first 8 FP args are in registers. | |
4648 | ||
4649 | If this is floating-point and no prototype is specified, we use | |
4650 | both an FP and integer register (or possibly FP reg and stack). Library | |
b9599e46 | 4651 | functions (when CALL_LIBCALL is set) always have the proper types for args, |
4697a36c | 4652 | so we can pass the FP value just in one register. emit_library_function |
b2d04ecf AM |
4653 | doesn't support PARALLEL anyway. |
4654 | ||
4655 | Note that for args passed by reference, function_arg will be called | |
4656 | with MODE and TYPE set to that of the pointer to the arg, not the arg | |
4657 | itself. */ | |
4697a36c | 4658 | |
9390387d | 4659 | rtx |
f676971a | 4660 | function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode, |
a2369ed3 | 4661 | tree type, int named) |
4697a36c | 4662 | { |
4cc833b7 | 4663 | enum rs6000_abi abi = DEFAULT_ABI; |
4697a36c | 4664 | |
a4f6c312 SS |
4665 | /* Return a marker to indicate whether CR1 needs to set or clear the |
4666 | bit that V.4 uses to say fp args were passed in registers. | |
4667 | Assume that we don't need the marker for software floating point, | |
4668 | or compiler generated library calls. */ | |
4697a36c MM |
4669 | if (mode == VOIDmode) |
4670 | { | |
f607bc57 | 4671 | if (abi == ABI_V4 |
7509c759 | 4672 | && cum->nargs_prototype < 0 |
b9599e46 FS |
4673 | && (cum->call_cookie & CALL_LIBCALL) == 0 |
4674 | && (cum->prototype || TARGET_NO_PROTOTYPE)) | |
7509c759 | 4675 | { |
a3170dc6 AH |
4676 | /* For the SPE, we need to crxor CR6 always. */ |
4677 | if (TARGET_SPE_ABI) | |
4678 | return GEN_INT (cum->call_cookie | CALL_V4_SET_FP_ARGS); | |
4679 | else if (TARGET_HARD_FLOAT && TARGET_FPRS) | |
4680 | return GEN_INT (cum->call_cookie | |
4681 | | ((cum->fregno == FP_ARG_MIN_REG) | |
4682 | ? CALL_V4_SET_FP_ARGS | |
4683 | : CALL_V4_CLEAR_FP_ARGS)); | |
7509c759 | 4684 | } |
4697a36c | 4685 | |
7509c759 | 4686 | return GEN_INT (cum->call_cookie); |
4697a36c MM |
4687 | } |
4688 | ||
0b5383eb DJ |
4689 | if (rs6000_darwin64_abi && mode == BLKmode |
4690 | && TREE_CODE (type) == RECORD_TYPE) | |
8ff40a74 | 4691 | { |
0b5383eb | 4692 | rtx rslt = rs6000_darwin64_record_arg (cum, type, named, false); |
8ff40a74 SS |
4693 | if (rslt != NULL_RTX) |
4694 | return rslt; | |
4695 | /* Else fall through to usual handling. */ | |
4696 | } | |
4697 | ||
2858f73a | 4698 | if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named)) |
c72d6c26 HP |
4699 | if (TARGET_64BIT && ! cum->prototype) |
4700 | { | |
c4ad648e AM |
4701 | /* Vector parameters get passed in vector register |
4702 | and also in GPRs or memory, in absence of prototype. */ | |
4703 | int align_words; | |
4704 | rtx slot; | |
4705 | align_words = (cum->words + 1) & ~1; | |
4706 | ||
4707 | if (align_words >= GP_ARG_NUM_REG) | |
4708 | { | |
4709 | slot = NULL_RTX; | |
4710 | } | |
4711 | else | |
4712 | { | |
4713 | slot = gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words); | |
4714 | } | |
4715 | return gen_rtx_PARALLEL (mode, | |
4716 | gen_rtvec (2, | |
4717 | gen_rtx_EXPR_LIST (VOIDmode, | |
4718 | slot, const0_rtx), | |
4719 | gen_rtx_EXPR_LIST (VOIDmode, | |
4720 | gen_rtx_REG (mode, cum->vregno), | |
4721 | const0_rtx))); | |
c72d6c26 HP |
4722 | } |
4723 | else | |
4724 | return gen_rtx_REG (mode, cum->vregno); | |
ad630bef DE |
4725 | else if (TARGET_ALTIVEC_ABI |
4726 | && (ALTIVEC_VECTOR_MODE (mode) | |
4727 | || (type && TREE_CODE (type) == VECTOR_TYPE | |
4728 | && int_size_in_bytes (type) == 16))) | |
0ac081f6 | 4729 | { |
2858f73a | 4730 | if (named || abi == ABI_V4) |
a594a19c | 4731 | return NULL_RTX; |
0ac081f6 | 4732 | else |
a594a19c GK |
4733 | { |
4734 | /* Vector parameters to varargs functions under AIX or Darwin | |
4735 | get passed in memory and possibly also in GPRs. */ | |
ec6376ab AM |
4736 | int align, align_words, n_words; |
4737 | enum machine_mode part_mode; | |
a594a19c GK |
4738 | |
4739 | /* Vector parameters must be 16-byte aligned. This places them at | |
2858f73a GK |
4740 | 2 mod 4 in terms of words in 32-bit mode, since the parameter |
4741 | save area starts at offset 24 from the stack. In 64-bit mode, | |
4742 | they just have to start on an even word, since the parameter | |
4743 | save area is 16-byte aligned. */ | |
4744 | if (TARGET_32BIT) | |
4ed78545 | 4745 | align = (2 - cum->words) & 3; |
2858f73a GK |
4746 | else |
4747 | align = cum->words & 1; | |
a594a19c GK |
4748 | align_words = cum->words + align; |
4749 | ||
4750 | /* Out of registers? Memory, then. */ | |
4751 | if (align_words >= GP_ARG_NUM_REG) | |
4752 | return NULL_RTX; | |
ec6376ab AM |
4753 | |
4754 | if (TARGET_32BIT && TARGET_POWERPC64) | |
4755 | return rs6000_mixed_function_arg (mode, type, align_words); | |
4756 | ||
2858f73a GK |
4757 | /* The vector value goes in GPRs. Only the part of the |
4758 | value in GPRs is reported here. */ | |
ec6376ab AM |
4759 | part_mode = mode; |
4760 | n_words = rs6000_arg_size (mode, type); | |
4761 | if (align_words + n_words > GP_ARG_NUM_REG) | |
839a4992 | 4762 | /* Fortunately, there are only two possibilities, the value |
2858f73a GK |
4763 | is either wholly in GPRs or half in GPRs and half not. */ |
4764 | part_mode = DImode; | |
ec6376ab AM |
4765 | |
4766 | return gen_rtx_REG (part_mode, GP_ARG_MIN_REG + align_words); | |
a594a19c | 4767 | } |
0ac081f6 | 4768 | } |
f82f556d AH |
4769 | else if (TARGET_SPE_ABI && TARGET_SPE |
4770 | && (SPE_VECTOR_MODE (mode) | |
18f63bfa AH |
4771 | || (TARGET_E500_DOUBLE && (mode == DFmode |
4772 | || mode == DCmode)))) | |
a6c9bed4 | 4773 | return rs6000_spe_function_arg (cum, mode, type); |
594a51fe | 4774 | |
f607bc57 | 4775 | else if (abi == ABI_V4) |
4697a36c | 4776 | { |
a3170dc6 | 4777 | if (TARGET_HARD_FLOAT && TARGET_FPRS |
4cc833b7 RH |
4778 | && (mode == SFmode || mode == DFmode)) |
4779 | { | |
4780 | if (cum->fregno <= FP_ARG_V4_MAX_REG) | |
4781 | return gen_rtx_REG (mode, cum->fregno); | |
4782 | else | |
b78d48dd | 4783 | return NULL_RTX; |
4cc833b7 RH |
4784 | } |
4785 | else | |
4786 | { | |
b2d04ecf | 4787 | int n_words = rs6000_arg_size (mode, type); |
4cc833b7 RH |
4788 | int gregno = cum->sysv_gregno; |
4789 | ||
4ed78545 AM |
4790 | /* Long long and SPE vectors are put in (r3,r4), (r5,r6), |
4791 | (r7,r8) or (r9,r10). As does any other 2 word item such | |
4792 | as complex int due to a historical mistake. */ | |
4793 | if (n_words == 2) | |
4794 | gregno += (1 - gregno) & 1; | |
4cc833b7 | 4795 | |
4ed78545 | 4796 | /* Multi-reg args are not split between registers and stack. */ |
ec6376ab | 4797 | if (gregno + n_words - 1 > GP_ARG_MAX_REG) |
b78d48dd | 4798 | return NULL_RTX; |
ec6376ab AM |
4799 | |
4800 | if (TARGET_32BIT && TARGET_POWERPC64) | |
4801 | return rs6000_mixed_function_arg (mode, type, | |
4802 | gregno - GP_ARG_MIN_REG); | |
4803 | return gen_rtx_REG (mode, gregno); | |
4cc833b7 | 4804 | } |
4697a36c | 4805 | } |
4cc833b7 RH |
4806 | else |
4807 | { | |
294bd182 | 4808 | int align_words = rs6000_parm_start (mode, type, cum->words); |
b78d48dd | 4809 | |
2858f73a | 4810 | if (USE_FP_FOR_ARG_P (cum, mode, type)) |
4cc833b7 | 4811 | { |
ec6376ab AM |
4812 | rtx rvec[GP_ARG_NUM_REG + 1]; |
4813 | rtx r; | |
4814 | int k; | |
c53bdcf5 AM |
4815 | bool needs_psave; |
4816 | enum machine_mode fmode = mode; | |
c53bdcf5 AM |
4817 | unsigned long n_fpreg = (GET_MODE_SIZE (mode) + 7) >> 3; |
4818 | ||
4819 | if (cum->fregno + n_fpreg > FP_ARG_MAX_REG + 1) | |
4820 | { | |
c53bdcf5 AM |
4821 | /* Currently, we only ever need one reg here because complex |
4822 | doubles are split. */ | |
37409796 | 4823 | gcc_assert (cum->fregno == FP_ARG_MAX_REG && fmode == TFmode); |
ec6376ab AM |
4824 | |
4825 | /* Long double split over regs and memory. */ | |
4826 | fmode = DFmode; | |
c53bdcf5 | 4827 | } |
c53bdcf5 AM |
4828 | |
4829 | /* Do we also need to pass this arg in the parameter save | |
4830 | area? */ | |
4831 | needs_psave = (type | |
4832 | && (cum->nargs_prototype <= 0 | |
4833 | || (DEFAULT_ABI == ABI_AIX | |
de17c25f | 4834 | && TARGET_XL_COMPAT |
c53bdcf5 AM |
4835 | && align_words >= GP_ARG_NUM_REG))); |
4836 | ||
4837 | if (!needs_psave && mode == fmode) | |
ec6376ab | 4838 | return gen_rtx_REG (fmode, cum->fregno); |
c53bdcf5 | 4839 | |
ec6376ab | 4840 | k = 0; |
c53bdcf5 AM |
4841 | if (needs_psave) |
4842 | { | |
ec6376ab | 4843 | /* Describe the part that goes in gprs or the stack. |
c53bdcf5 | 4844 | This piece must come first, before the fprs. */ |
c53bdcf5 AM |
4845 | if (align_words < GP_ARG_NUM_REG) |
4846 | { | |
4847 | unsigned long n_words = rs6000_arg_size (mode, type); | |
ec6376ab AM |
4848 | |
4849 | if (align_words + n_words > GP_ARG_NUM_REG | |
4850 | || (TARGET_32BIT && TARGET_POWERPC64)) | |
4851 | { | |
4852 | /* If this is partially on the stack, then we only | |
4853 | include the portion actually in registers here. */ | |
4854 | enum machine_mode rmode = TARGET_32BIT ? SImode : DImode; | |
4855 | rtx off; | |
2e6c9641 | 4856 | int i=0; |
c4ad648e AM |
4857 | if (align_words + n_words > GP_ARG_NUM_REG |
4858 | && (TARGET_32BIT && TARGET_POWERPC64)) | |
4859 | /* Not all of the arg fits in gprs. Say that it | |
4860 | goes in memory too, using a magic NULL_RTX | |
4861 | component. Also see comment in | |
4862 | rs6000_mixed_function_arg for why the normal | |
4863 | function_arg_partial_nregs scheme doesn't work | |
4864 | in this case. */ | |
4865 | rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, | |
4866 | const0_rtx); | |
ec6376ab AM |
4867 | do |
4868 | { | |
4869 | r = gen_rtx_REG (rmode, | |
4870 | GP_ARG_MIN_REG + align_words); | |
2e6c9641 | 4871 | off = GEN_INT (i++ * GET_MODE_SIZE (rmode)); |
ec6376ab AM |
4872 | rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off); |
4873 | } | |
4874 | while (++align_words < GP_ARG_NUM_REG && --n_words != 0); | |
4875 | } | |
4876 | else | |
4877 | { | |
4878 | /* The whole arg fits in gprs. */ | |
4879 | r = gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words); | |
4880 | rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, const0_rtx); | |
4881 | } | |
c53bdcf5 | 4882 | } |
ec6376ab AM |
4883 | else |
4884 | /* It's entirely in memory. */ | |
4885 | rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx); | |
c53bdcf5 AM |
4886 | } |
4887 | ||
ec6376ab AM |
4888 | /* Describe where this piece goes in the fprs. */ |
4889 | r = gen_rtx_REG (fmode, cum->fregno); | |
4890 | rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, const0_rtx); | |
4891 | ||
4892 | return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec)); | |
4cc833b7 RH |
4893 | } |
4894 | else if (align_words < GP_ARG_NUM_REG) | |
b2d04ecf | 4895 | { |
ec6376ab AM |
4896 | if (TARGET_32BIT && TARGET_POWERPC64) |
4897 | return rs6000_mixed_function_arg (mode, type, align_words); | |
b2d04ecf | 4898 | |
4eeca74f AM |
4899 | if (mode == BLKmode) |
4900 | mode = Pmode; | |
4901 | ||
b2d04ecf AM |
4902 | return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words); |
4903 | } | |
4cc833b7 RH |
4904 | else |
4905 | return NULL_RTX; | |
4697a36c | 4906 | } |
4697a36c MM |
4907 | } |
4908 | \f | |
ec6376ab | 4909 | /* For an arg passed partly in registers and partly in memory, this is |
fb63c729 AM |
4910 | the number of bytes passed in registers. For args passed entirely in |
4911 | registers or entirely in memory, zero. When an arg is described by a | |
4912 | PARALLEL, perhaps using more than one register type, this function | |
4913 | returns the number of bytes used by the first element of the PARALLEL. */ | |
4697a36c | 4914 | |
78a52f11 RH |
4915 | static int |
4916 | rs6000_arg_partial_bytes (CUMULATIVE_ARGS *cum, enum machine_mode mode, | |
4917 | tree type, bool named) | |
4697a36c | 4918 | { |
c53bdcf5 | 4919 | int ret = 0; |
ec6376ab | 4920 | int align_words; |
c53bdcf5 | 4921 | |
f607bc57 | 4922 | if (DEFAULT_ABI == ABI_V4) |
4697a36c | 4923 | return 0; |
4697a36c | 4924 | |
c53bdcf5 AM |
4925 | if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named) |
4926 | && cum->nargs_prototype >= 0) | |
4927 | return 0; | |
4928 | ||
0b5383eb DJ |
4929 | /* In this complicated case we just disable the partial_nregs code. */ |
4930 | if (rs6000_darwin64_abi && mode == BLKmode | |
4931 | && TREE_CODE (type) == RECORD_TYPE | |
4932 | && int_size_in_bytes (type) > 0) | |
4933 | return 0; | |
4934 | ||
294bd182 | 4935 | align_words = rs6000_parm_start (mode, type, cum->words); |
ec6376ab AM |
4936 | |
4937 | if (USE_FP_FOR_ARG_P (cum, mode, type) | |
fb63c729 AM |
4938 | /* If we are passing this arg in the fixed parameter save area |
4939 | (gprs or memory) as well as fprs, then this function should | |
4940 | return the number of bytes passed in the parameter save area | |
4941 | rather than bytes passed in fprs. */ | |
ec6376ab AM |
4942 | && !(type |
4943 | && (cum->nargs_prototype <= 0 | |
4944 | || (DEFAULT_ABI == ABI_AIX | |
de17c25f | 4945 | && TARGET_XL_COMPAT |
ec6376ab | 4946 | && align_words >= GP_ARG_NUM_REG)))) |
4697a36c | 4947 | { |
c53bdcf5 | 4948 | if (cum->fregno + ((GET_MODE_SIZE (mode) + 7) >> 3) > FP_ARG_MAX_REG + 1) |
ac7e839c | 4949 | ret = (FP_ARG_MAX_REG + 1 - cum->fregno) * 8; |
c53bdcf5 | 4950 | else if (cum->nargs_prototype >= 0) |
4697a36c MM |
4951 | return 0; |
4952 | } | |
4953 | ||
ec6376ab AM |
4954 | if (align_words < GP_ARG_NUM_REG |
4955 | && GP_ARG_NUM_REG < align_words + rs6000_arg_size (mode, type)) | |
ac7e839c | 4956 | ret = (GP_ARG_NUM_REG - align_words) * (TARGET_32BIT ? 4 : 8); |
78a52f11 | 4957 | |
c53bdcf5 | 4958 | if (ret != 0 && TARGET_DEBUG_ARG) |
78a52f11 | 4959 | fprintf (stderr, "rs6000_arg_partial_bytes: %d\n", ret); |
4697a36c | 4960 | |
c53bdcf5 | 4961 | return ret; |
4697a36c MM |
4962 | } |
4963 | \f | |
4964 | /* A C expression that indicates when an argument must be passed by | |
4965 | reference. If nonzero for an argument, a copy of that argument is | |
4966 | made in memory and a pointer to the argument is passed instead of | |
4967 | the argument itself. The pointer is passed in whatever way is | |
4968 | appropriate for passing a pointer to that type. | |
4969 | ||
b2d04ecf AM |
4970 | Under V.4, aggregates and long double are passed by reference. |
4971 | ||
4972 | As an extension to all 32-bit ABIs, AltiVec vectors are passed by | |
4973 | reference unless the AltiVec vector extension ABI is in force. | |
c8c99a68 DE |
4974 | |
4975 | As an extension to all ABIs, variable sized types are passed by | |
4976 | reference. */ | |
4697a36c | 4977 | |
8cd5a4e0 | 4978 | static bool |
f676971a | 4979 | rs6000_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED, |
bada2eb8 DE |
4980 | enum machine_mode mode, tree type, |
4981 | bool named ATTRIBUTE_UNUSED) | |
4697a36c | 4982 | { |
bada2eb8 | 4983 | if (DEFAULT_ABI == ABI_V4 && mode == TFmode) |
4697a36c MM |
4984 | { |
4985 | if (TARGET_DEBUG_ARG) | |
bada2eb8 DE |
4986 | fprintf (stderr, "function_arg_pass_by_reference: V4 long double\n"); |
4987 | return 1; | |
4988 | } | |
4989 | ||
4990 | if (!type) | |
4991 | return 0; | |
4697a36c | 4992 | |
bada2eb8 DE |
4993 | if (DEFAULT_ABI == ABI_V4 && AGGREGATE_TYPE_P (type)) |
4994 | { | |
4995 | if (TARGET_DEBUG_ARG) | |
4996 | fprintf (stderr, "function_arg_pass_by_reference: V4 aggregate\n"); | |
4997 | return 1; | |
4998 | } | |
4999 | ||
5000 | if (int_size_in_bytes (type) < 0) | |
5001 | { | |
5002 | if (TARGET_DEBUG_ARG) | |
5003 | fprintf (stderr, "function_arg_pass_by_reference: variable size\n"); | |
5004 | return 1; | |
5005 | } | |
5006 | ||
5007 | /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector | |
5008 | modes only exist for GCC vector types if -maltivec. */ | |
5009 | if (TARGET_32BIT && !TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode)) | |
5010 | { | |
5011 | if (TARGET_DEBUG_ARG) | |
5012 | fprintf (stderr, "function_arg_pass_by_reference: AltiVec\n"); | |
4697a36c MM |
5013 | return 1; |
5014 | } | |
b693336b PB |
5015 | |
5016 | /* Pass synthetic vectors in memory. */ | |
bada2eb8 | 5017 | if (TREE_CODE (type) == VECTOR_TYPE |
ad630bef | 5018 | && int_size_in_bytes (type) > (TARGET_ALTIVEC_ABI ? 16 : 8)) |
b693336b PB |
5019 | { |
5020 | static bool warned_for_pass_big_vectors = false; | |
5021 | if (TARGET_DEBUG_ARG) | |
5022 | fprintf (stderr, "function_arg_pass_by_reference: synthetic vector\n"); | |
5023 | if (!warned_for_pass_big_vectors) | |
5024 | { | |
d4ee4d25 | 5025 | warning (0, "GCC vector passed by reference: " |
b693336b PB |
5026 | "non-standard ABI extension with no compatibility guarantee"); |
5027 | warned_for_pass_big_vectors = true; | |
5028 | } | |
5029 | return 1; | |
5030 | } | |
5031 | ||
b2d04ecf | 5032 | return 0; |
4697a36c | 5033 | } |
5985c7a6 FJ |
5034 | |
5035 | static void | |
2d9db8eb | 5036 | rs6000_move_block_from_reg (int regno, rtx x, int nregs) |
5985c7a6 FJ |
5037 | { |
5038 | int i; | |
5039 | enum machine_mode reg_mode = TARGET_32BIT ? SImode : DImode; | |
5040 | ||
5041 | if (nregs == 0) | |
5042 | return; | |
5043 | ||
c4ad648e | 5044 | for (i = 0; i < nregs; i++) |
5985c7a6 | 5045 | { |
9390387d | 5046 | rtx tem = adjust_address_nv (x, reg_mode, i * GET_MODE_SIZE (reg_mode)); |
5985c7a6 | 5047 | if (reload_completed) |
c4ad648e AM |
5048 | { |
5049 | if (! strict_memory_address_p (reg_mode, XEXP (tem, 0))) | |
5050 | tem = NULL_RTX; | |
5051 | else | |
5052 | tem = simplify_gen_subreg (reg_mode, x, BLKmode, | |
9390387d | 5053 | i * GET_MODE_SIZE (reg_mode)); |
c4ad648e | 5054 | } |
5985c7a6 FJ |
5055 | else |
5056 | tem = replace_equiv_address (tem, XEXP (tem, 0)); | |
5057 | ||
37409796 | 5058 | gcc_assert (tem); |
5985c7a6 FJ |
5059 | |
5060 | emit_move_insn (tem, gen_rtx_REG (reg_mode, regno + i)); | |
5061 | } | |
5062 | } | |
4697a36c MM |
5063 | \f |
5064 | /* Perform any needed actions needed for a function that is receiving a | |
f676971a | 5065 | variable number of arguments. |
4697a36c MM |
5066 | |
5067 | CUM is as above. | |
5068 | ||
5069 | MODE and TYPE are the mode and type of the current parameter. | |
5070 | ||
5071 | PRETEND_SIZE is a variable that should be set to the amount of stack | |
5072 | that must be pushed by the prolog to pretend that our caller pushed | |
5073 | it. | |
5074 | ||
5075 | Normally, this macro will push all remaining incoming registers on the | |
5076 | stack and set PRETEND_SIZE to the length of the registers pushed. */ | |
5077 | ||
c6e8c921 | 5078 | static void |
f676971a | 5079 | setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode, |
c4ad648e AM |
5080 | tree type, int *pretend_size ATTRIBUTE_UNUSED, |
5081 | int no_rtl) | |
4697a36c | 5082 | { |
4cc833b7 RH |
5083 | CUMULATIVE_ARGS next_cum; |
5084 | int reg_size = TARGET_32BIT ? 4 : 8; | |
ca5adc63 | 5085 | rtx save_area = NULL_RTX, mem; |
dfafc897 | 5086 | int first_reg_offset, set; |
4697a36c | 5087 | |
f31bf321 | 5088 | /* Skip the last named argument. */ |
d34c5b80 | 5089 | next_cum = *cum; |
594a51fe | 5090 | function_arg_advance (&next_cum, mode, type, 1, 0); |
4cc833b7 | 5091 | |
f607bc57 | 5092 | if (DEFAULT_ABI == ABI_V4) |
d34c5b80 | 5093 | { |
60e2d0ca | 5094 | if (! no_rtl) |
2c4974b7 | 5095 | save_area = plus_constant (virtual_stack_vars_rtx, |
bd227acc | 5096 | - RS6000_VARARGS_SIZE); |
4cc833b7 RH |
5097 | |
5098 | first_reg_offset = next_cum.sysv_gregno - GP_ARG_MIN_REG; | |
4697a36c | 5099 | } |
60e2d0ca | 5100 | else |
4697a36c | 5101 | { |
d34c5b80 | 5102 | first_reg_offset = next_cum.words; |
4cc833b7 | 5103 | save_area = virtual_incoming_args_rtx; |
4697a36c | 5104 | |
fe984136 | 5105 | if (targetm.calls.must_pass_in_stack (mode, type)) |
c53bdcf5 | 5106 | first_reg_offset += rs6000_arg_size (TYPE_MODE (type), type); |
4cc833b7 | 5107 | } |
4697a36c | 5108 | |
dfafc897 | 5109 | set = get_varargs_alias_set (); |
9d30f3c1 JJ |
5110 | if (! no_rtl && first_reg_offset < GP_ARG_NUM_REG |
5111 | && cfun->va_list_gpr_size) | |
4cc833b7 | 5112 | { |
9d30f3c1 JJ |
5113 | int nregs = GP_ARG_NUM_REG - first_reg_offset; |
5114 | ||
5115 | if (va_list_gpr_counter_field) | |
5116 | { | |
5117 | /* V4 va_list_gpr_size counts number of registers needed. */ | |
5118 | if (nregs > cfun->va_list_gpr_size) | |
5119 | nregs = cfun->va_list_gpr_size; | |
5120 | } | |
5121 | else | |
5122 | { | |
5123 | /* char * va_list instead counts number of bytes needed. */ | |
5124 | if (nregs > cfun->va_list_gpr_size / reg_size) | |
5125 | nregs = cfun->va_list_gpr_size / reg_size; | |
5126 | } | |
5127 | ||
dfafc897 | 5128 | mem = gen_rtx_MEM (BLKmode, |
c4ad648e | 5129 | plus_constant (save_area, |
dfafc897 | 5130 | first_reg_offset * reg_size)), |
ba4828e0 | 5131 | set_mem_alias_set (mem, set); |
8ac61af7 | 5132 | set_mem_align (mem, BITS_PER_WORD); |
dfafc897 | 5133 | |
f676971a | 5134 | rs6000_move_block_from_reg (GP_ARG_MIN_REG + first_reg_offset, mem, |
9d30f3c1 | 5135 | nregs); |
4697a36c MM |
5136 | } |
5137 | ||
4697a36c | 5138 | /* Save FP registers if needed. */ |
f607bc57 | 5139 | if (DEFAULT_ABI == ABI_V4 |
a3170dc6 AH |
5140 | && TARGET_HARD_FLOAT && TARGET_FPRS |
5141 | && ! no_rtl | |
9d30f3c1 JJ |
5142 | && next_cum.fregno <= FP_ARG_V4_MAX_REG |
5143 | && cfun->va_list_fpr_size) | |
4697a36c | 5144 | { |
9d30f3c1 | 5145 | int fregno = next_cum.fregno, nregs; |
9ebbca7d | 5146 | rtx cr1 = gen_rtx_REG (CCmode, CR1_REGNO); |
4cc833b7 RH |
5147 | rtx lab = gen_label_rtx (); |
5148 | int off = (GP_ARG_NUM_REG * reg_size) + ((fregno - FP_ARG_MIN_REG) * 8); | |
4697a36c | 5149 | |
c4ad648e AM |
5150 | emit_jump_insn |
5151 | (gen_rtx_SET (VOIDmode, | |
5152 | pc_rtx, | |
5153 | gen_rtx_IF_THEN_ELSE (VOIDmode, | |
4cc833b7 | 5154 | gen_rtx_NE (VOIDmode, cr1, |
c4ad648e | 5155 | const0_rtx), |
39403d82 | 5156 | gen_rtx_LABEL_REF (VOIDmode, lab), |
4697a36c MM |
5157 | pc_rtx))); |
5158 | ||
9d30f3c1 JJ |
5159 | for (nregs = 0; |
5160 | fregno <= FP_ARG_V4_MAX_REG && nregs < cfun->va_list_fpr_size; | |
5161 | fregno++, off += 8, nregs++) | |
4cc833b7 | 5162 | { |
5496b36f | 5163 | mem = gen_rtx_MEM (DFmode, plus_constant (save_area, off)); |
c4ad648e | 5164 | set_mem_alias_set (mem, set); |
94ff898d | 5165 | set_mem_align (mem, GET_MODE_ALIGNMENT (DFmode)); |
dfafc897 | 5166 | emit_move_insn (mem, gen_rtx_REG (DFmode, fregno)); |
4697a36c | 5167 | } |
4cc833b7 RH |
5168 | |
5169 | emit_label (lab); | |
4697a36c | 5170 | } |
4697a36c | 5171 | } |
4697a36c | 5172 | |
dfafc897 | 5173 | /* Create the va_list data type. */ |
2c4974b7 | 5174 | |
c35d187f RH |
5175 | static tree |
5176 | rs6000_build_builtin_va_list (void) | |
dfafc897 | 5177 | { |
64c2816f | 5178 | tree f_gpr, f_fpr, f_res, f_ovf, f_sav, record, type_decl; |
4697a36c | 5179 | |
9ebbca7d GK |
5180 | /* For AIX, prefer 'char *' because that's what the system |
5181 | header files like. */ | |
f607bc57 | 5182 | if (DEFAULT_ABI != ABI_V4) |
9ebbca7d | 5183 | return build_pointer_type (char_type_node); |
dfafc897 | 5184 | |
f1e639b1 | 5185 | record = (*lang_hooks.types.make_type) (RECORD_TYPE); |
bab45a51 | 5186 | type_decl = build_decl (TYPE_DECL, get_identifier ("__va_list_tag"), record); |
0f4fd75d | 5187 | |
f676971a | 5188 | f_gpr = build_decl (FIELD_DECL, get_identifier ("gpr"), |
9ebbca7d | 5189 | unsigned_char_type_node); |
f676971a | 5190 | f_fpr = build_decl (FIELD_DECL, get_identifier ("fpr"), |
9ebbca7d | 5191 | unsigned_char_type_node); |
64c2816f DT |
5192 | /* Give the two bytes of padding a name, so that -Wpadded won't warn on |
5193 | every user file. */ | |
5194 | f_res = build_decl (FIELD_DECL, get_identifier ("reserved"), | |
5195 | short_unsigned_type_node); | |
dfafc897 FS |
5196 | f_ovf = build_decl (FIELD_DECL, get_identifier ("overflow_arg_area"), |
5197 | ptr_type_node); | |
5198 | f_sav = build_decl (FIELD_DECL, get_identifier ("reg_save_area"), | |
5199 | ptr_type_node); | |
5200 | ||
9d30f3c1 JJ |
5201 | va_list_gpr_counter_field = f_gpr; |
5202 | va_list_fpr_counter_field = f_fpr; | |
5203 | ||
dfafc897 FS |
5204 | DECL_FIELD_CONTEXT (f_gpr) = record; |
5205 | DECL_FIELD_CONTEXT (f_fpr) = record; | |
64c2816f | 5206 | DECL_FIELD_CONTEXT (f_res) = record; |
dfafc897 FS |
5207 | DECL_FIELD_CONTEXT (f_ovf) = record; |
5208 | DECL_FIELD_CONTEXT (f_sav) = record; | |
5209 | ||
bab45a51 FS |
5210 | TREE_CHAIN (record) = type_decl; |
5211 | TYPE_NAME (record) = type_decl; | |
dfafc897 FS |
5212 | TYPE_FIELDS (record) = f_gpr; |
5213 | TREE_CHAIN (f_gpr) = f_fpr; | |
64c2816f DT |
5214 | TREE_CHAIN (f_fpr) = f_res; |
5215 | TREE_CHAIN (f_res) = f_ovf; | |
dfafc897 FS |
5216 | TREE_CHAIN (f_ovf) = f_sav; |
5217 | ||
5218 | layout_type (record); | |
5219 | ||
5220 | /* The correct type is an array type of one element. */ | |
5221 | return build_array_type (record, build_index_type (size_zero_node)); | |
5222 | } | |
5223 | ||
5224 | /* Implement va_start. */ | |
5225 | ||
5226 | void | |
a2369ed3 | 5227 | rs6000_va_start (tree valist, rtx nextarg) |
4697a36c | 5228 | { |
dfafc897 | 5229 | HOST_WIDE_INT words, n_gpr, n_fpr; |
c566f9bd | 5230 | tree f_gpr, f_fpr, f_res, f_ovf, f_sav; |
dfafc897 | 5231 | tree gpr, fpr, ovf, sav, t; |
2c4974b7 | 5232 | |
dfafc897 | 5233 | /* Only SVR4 needs something special. */ |
f607bc57 | 5234 | if (DEFAULT_ABI != ABI_V4) |
dfafc897 | 5235 | { |
e5faf155 | 5236 | std_expand_builtin_va_start (valist, nextarg); |
dfafc897 FS |
5237 | return; |
5238 | } | |
5239 | ||
973a648b | 5240 | f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node)); |
dfafc897 | 5241 | f_fpr = TREE_CHAIN (f_gpr); |
c566f9bd DT |
5242 | f_res = TREE_CHAIN (f_fpr); |
5243 | f_ovf = TREE_CHAIN (f_res); | |
dfafc897 FS |
5244 | f_sav = TREE_CHAIN (f_ovf); |
5245 | ||
872a65b5 | 5246 | valist = build_va_arg_indirect_ref (valist); |
44de5aeb RK |
5247 | gpr = build (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE); |
5248 | fpr = build (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE); | |
5249 | ovf = build (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE); | |
5250 | sav = build (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE); | |
dfafc897 FS |
5251 | |
5252 | /* Count number of gp and fp argument registers used. */ | |
4cc833b7 | 5253 | words = current_function_args_info.words; |
987732e0 DE |
5254 | n_gpr = MIN (current_function_args_info.sysv_gregno - GP_ARG_MIN_REG, |
5255 | GP_ARG_NUM_REG); | |
5256 | n_fpr = MIN (current_function_args_info.fregno - FP_ARG_MIN_REG, | |
5257 | FP_ARG_NUM_REG); | |
dfafc897 FS |
5258 | |
5259 | if (TARGET_DEBUG_ARG) | |
4a0a75dd KG |
5260 | fprintf (stderr, "va_start: words = "HOST_WIDE_INT_PRINT_DEC", n_gpr = " |
5261 | HOST_WIDE_INT_PRINT_DEC", n_fpr = "HOST_WIDE_INT_PRINT_DEC"\n", | |
5262 | words, n_gpr, n_fpr); | |
dfafc897 | 5263 | |
9d30f3c1 JJ |
5264 | if (cfun->va_list_gpr_size) |
5265 | { | |
5266 | t = build (MODIFY_EXPR, TREE_TYPE (gpr), gpr, | |
5267 | build_int_cst (NULL_TREE, n_gpr)); | |
5268 | TREE_SIDE_EFFECTS (t) = 1; | |
5269 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
5270 | } | |
58c8adc1 | 5271 | |
9d30f3c1 JJ |
5272 | if (cfun->va_list_fpr_size) |
5273 | { | |
5274 | t = build (MODIFY_EXPR, TREE_TYPE (fpr), fpr, | |
5275 | build_int_cst (NULL_TREE, n_fpr)); | |
5276 | TREE_SIDE_EFFECTS (t) = 1; | |
5277 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
5278 | } | |
dfafc897 FS |
5279 | |
5280 | /* Find the overflow area. */ | |
5281 | t = make_tree (TREE_TYPE (ovf), virtual_incoming_args_rtx); | |
5282 | if (words != 0) | |
5283 | t = build (PLUS_EXPR, TREE_TYPE (ovf), t, | |
7d60be94 | 5284 | build_int_cst (NULL_TREE, words * UNITS_PER_WORD)); |
dfafc897 FS |
5285 | t = build (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t); |
5286 | TREE_SIDE_EFFECTS (t) = 1; | |
5287 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
5288 | ||
9d30f3c1 JJ |
5289 | /* If there were no va_arg invocations, don't set up the register |
5290 | save area. */ | |
5291 | if (!cfun->va_list_gpr_size | |
5292 | && !cfun->va_list_fpr_size | |
5293 | && n_gpr < GP_ARG_NUM_REG | |
5294 | && n_fpr < FP_ARG_V4_MAX_REG) | |
5295 | return; | |
5296 | ||
dfafc897 FS |
5297 | /* Find the register save area. */ |
5298 | t = make_tree (TREE_TYPE (sav), virtual_stack_vars_rtx); | |
5299 | t = build (PLUS_EXPR, TREE_TYPE (sav), t, | |
7d60be94 | 5300 | build_int_cst (NULL_TREE, -RS6000_VARARGS_SIZE)); |
dfafc897 FS |
5301 | t = build (MODIFY_EXPR, TREE_TYPE (sav), sav, t); |
5302 | TREE_SIDE_EFFECTS (t) = 1; | |
5303 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
5304 | } | |
5305 | ||
5306 | /* Implement va_arg. */ | |
5307 | ||
23a60a04 JM |
5308 | tree |
5309 | rs6000_gimplify_va_arg (tree valist, tree type, tree *pre_p, tree *post_p) | |
cd3ce9b4 | 5310 | { |
cd3ce9b4 JM |
5311 | tree f_gpr, f_fpr, f_res, f_ovf, f_sav; |
5312 | tree gpr, fpr, ovf, sav, reg, t, u; | |
08b0dc1b | 5313 | int size, rsize, n_reg, sav_ofs, sav_scale; |
cd3ce9b4 JM |
5314 | tree lab_false, lab_over, addr; |
5315 | int align; | |
5316 | tree ptrtype = build_pointer_type (type); | |
5317 | ||
08b0dc1b RH |
5318 | if (pass_by_reference (NULL, TYPE_MODE (type), type, false)) |
5319 | { | |
5320 | t = rs6000_gimplify_va_arg (valist, ptrtype, pre_p, post_p); | |
872a65b5 | 5321 | return build_va_arg_indirect_ref (t); |
08b0dc1b RH |
5322 | } |
5323 | ||
cd3ce9b4 JM |
5324 | if (DEFAULT_ABI != ABI_V4) |
5325 | { | |
08b0dc1b | 5326 | if (targetm.calls.split_complex_arg && TREE_CODE (type) == COMPLEX_TYPE) |
cd3ce9b4 JM |
5327 | { |
5328 | tree elem_type = TREE_TYPE (type); | |
5329 | enum machine_mode elem_mode = TYPE_MODE (elem_type); | |
5330 | int elem_size = GET_MODE_SIZE (elem_mode); | |
5331 | ||
5332 | if (elem_size < UNITS_PER_WORD) | |
5333 | { | |
23a60a04 | 5334 | tree real_part, imag_part; |
cd3ce9b4 JM |
5335 | tree post = NULL_TREE; |
5336 | ||
23a60a04 JM |
5337 | real_part = rs6000_gimplify_va_arg (valist, elem_type, pre_p, |
5338 | &post); | |
5339 | /* Copy the value into a temporary, lest the formal temporary | |
5340 | be reused out from under us. */ | |
5341 | real_part = get_initialized_tmp_var (real_part, pre_p, &post); | |
cd3ce9b4 JM |
5342 | append_to_statement_list (post, pre_p); |
5343 | ||
23a60a04 JM |
5344 | imag_part = rs6000_gimplify_va_arg (valist, elem_type, pre_p, |
5345 | post_p); | |
cd3ce9b4 | 5346 | |
23a60a04 | 5347 | return build (COMPLEX_EXPR, type, real_part, imag_part); |
cd3ce9b4 JM |
5348 | } |
5349 | } | |
5350 | ||
23a60a04 | 5351 | return std_gimplify_va_arg_expr (valist, type, pre_p, post_p); |
cd3ce9b4 JM |
5352 | } |
5353 | ||
5354 | f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node)); | |
5355 | f_fpr = TREE_CHAIN (f_gpr); | |
5356 | f_res = TREE_CHAIN (f_fpr); | |
5357 | f_ovf = TREE_CHAIN (f_res); | |
5358 | f_sav = TREE_CHAIN (f_ovf); | |
5359 | ||
872a65b5 | 5360 | valist = build_va_arg_indirect_ref (valist); |
44de5aeb RK |
5361 | gpr = build (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE); |
5362 | fpr = build (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE); | |
5363 | ovf = build (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE); | |
5364 | sav = build (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE); | |
cd3ce9b4 JM |
5365 | |
5366 | size = int_size_in_bytes (type); | |
5367 | rsize = (size + 3) / 4; | |
5368 | align = 1; | |
5369 | ||
08b0dc1b RH |
5370 | if (TARGET_HARD_FLOAT && TARGET_FPRS |
5371 | && (TYPE_MODE (type) == SFmode || TYPE_MODE (type) == DFmode)) | |
cd3ce9b4 JM |
5372 | { |
5373 | /* FP args go in FP registers, if present. */ | |
cd3ce9b4 JM |
5374 | reg = fpr; |
5375 | n_reg = 1; | |
5376 | sav_ofs = 8*4; | |
5377 | sav_scale = 8; | |
5378 | if (TYPE_MODE (type) == DFmode) | |
5379 | align = 8; | |
5380 | } | |
5381 | else | |
5382 | { | |
5383 | /* Otherwise into GP registers. */ | |
cd3ce9b4 JM |
5384 | reg = gpr; |
5385 | n_reg = rsize; | |
5386 | sav_ofs = 0; | |
5387 | sav_scale = 4; | |
5388 | if (n_reg == 2) | |
5389 | align = 8; | |
5390 | } | |
5391 | ||
5392 | /* Pull the value out of the saved registers.... */ | |
5393 | ||
5394 | lab_over = NULL; | |
5395 | addr = create_tmp_var (ptr_type_node, "addr"); | |
5396 | DECL_POINTER_ALIAS_SET (addr) = get_varargs_alias_set (); | |
5397 | ||
5398 | /* AltiVec vectors never go in registers when -mabi=altivec. */ | |
5399 | if (TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (TYPE_MODE (type))) | |
5400 | align = 16; | |
5401 | else | |
5402 | { | |
5403 | lab_false = create_artificial_label (); | |
5404 | lab_over = create_artificial_label (); | |
5405 | ||
5406 | /* Long long and SPE vectors are aligned in the registers. | |
5407 | As are any other 2 gpr item such as complex int due to a | |
5408 | historical mistake. */ | |
5409 | u = reg; | |
5410 | if (n_reg == 2) | |
5411 | { | |
5412 | u = build2 (BIT_AND_EXPR, TREE_TYPE (reg), reg, | |
95674810 | 5413 | size_int (n_reg - 1)); |
cd3ce9b4 JM |
5414 | u = build2 (POSTINCREMENT_EXPR, TREE_TYPE (reg), reg, u); |
5415 | } | |
5416 | ||
95674810 | 5417 | t = fold_convert (TREE_TYPE (reg), size_int (8 - n_reg + 1)); |
cd3ce9b4 JM |
5418 | t = build2 (GE_EXPR, boolean_type_node, u, t); |
5419 | u = build1 (GOTO_EXPR, void_type_node, lab_false); | |
5420 | t = build3 (COND_EXPR, void_type_node, t, u, NULL_TREE); | |
5421 | gimplify_and_add (t, pre_p); | |
5422 | ||
5423 | t = sav; | |
5424 | if (sav_ofs) | |
95674810 | 5425 | t = build2 (PLUS_EXPR, ptr_type_node, sav, size_int (sav_ofs)); |
cd3ce9b4 | 5426 | |
95674810 | 5427 | u = build2 (POSTINCREMENT_EXPR, TREE_TYPE (reg), reg, size_int (n_reg)); |
cd3ce9b4 | 5428 | u = build1 (CONVERT_EXPR, integer_type_node, u); |
95674810 | 5429 | u = build2 (MULT_EXPR, integer_type_node, u, size_int (sav_scale)); |
cd3ce9b4 JM |
5430 | t = build2 (PLUS_EXPR, ptr_type_node, t, u); |
5431 | ||
5432 | t = build2 (MODIFY_EXPR, void_type_node, addr, t); | |
5433 | gimplify_and_add (t, pre_p); | |
5434 | ||
5435 | t = build1 (GOTO_EXPR, void_type_node, lab_over); | |
5436 | gimplify_and_add (t, pre_p); | |
5437 | ||
5438 | t = build1 (LABEL_EXPR, void_type_node, lab_false); | |
5439 | append_to_statement_list (t, pre_p); | |
5440 | ||
5441 | if (n_reg > 2) | |
5442 | { | |
5443 | /* Ensure that we don't find any more args in regs. | |
5444 | Alignment has taken care of the n_reg == 2 case. */ | |
95674810 | 5445 | t = build (MODIFY_EXPR, TREE_TYPE (reg), reg, size_int (8)); |
cd3ce9b4 JM |
5446 | gimplify_and_add (t, pre_p); |
5447 | } | |
5448 | } | |
5449 | ||
5450 | /* ... otherwise out of the overflow area. */ | |
5451 | ||
5452 | /* Care for on-stack alignment if needed. */ | |
5453 | t = ovf; | |
5454 | if (align != 1) | |
5455 | { | |
95674810 | 5456 | t = build2 (PLUS_EXPR, TREE_TYPE (t), t, size_int (align - 1)); |
4a90aeeb | 5457 | t = build2 (BIT_AND_EXPR, TREE_TYPE (t), t, |
7d60be94 | 5458 | build_int_cst (NULL_TREE, -align)); |
cd3ce9b4 JM |
5459 | } |
5460 | gimplify_expr (&t, pre_p, NULL, is_gimple_val, fb_rvalue); | |
5461 | ||
5462 | u = build2 (MODIFY_EXPR, void_type_node, addr, t); | |
5463 | gimplify_and_add (u, pre_p); | |
5464 | ||
95674810 | 5465 | t = build2 (PLUS_EXPR, TREE_TYPE (t), t, size_int (size)); |
cd3ce9b4 JM |
5466 | t = build2 (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t); |
5467 | gimplify_and_add (t, pre_p); | |
5468 | ||
5469 | if (lab_over) | |
5470 | { | |
5471 | t = build1 (LABEL_EXPR, void_type_node, lab_over); | |
5472 | append_to_statement_list (t, pre_p); | |
5473 | } | |
5474 | ||
08b0dc1b | 5475 | addr = fold_convert (ptrtype, addr); |
872a65b5 | 5476 | return build_va_arg_indirect_ref (addr); |
cd3ce9b4 JM |
5477 | } |
5478 | ||
0ac081f6 AH |
5479 | /* Builtins. */ |
5480 | ||
6e34d3a3 JM |
5481 | #define def_builtin(MASK, NAME, TYPE, CODE) \ |
5482 | do { \ | |
5483 | if ((MASK) & target_flags) \ | |
5484 | lang_hooks.builtin_function ((NAME), (TYPE), (CODE), BUILT_IN_MD, \ | |
5485 | NULL, NULL_TREE); \ | |
0ac081f6 AH |
5486 | } while (0) |
5487 | ||
24408032 AH |
5488 | /* Simple ternary operations: VECd = foo (VECa, VECb, VECc). */ |
5489 | ||
2212663f | 5490 | static const struct builtin_description bdesc_3arg[] = |
24408032 AH |
5491 | { |
5492 | { MASK_ALTIVEC, CODE_FOR_altivec_vmaddfp, "__builtin_altivec_vmaddfp", ALTIVEC_BUILTIN_VMADDFP }, | |
5493 | { MASK_ALTIVEC, CODE_FOR_altivec_vmhaddshs, "__builtin_altivec_vmhaddshs", ALTIVEC_BUILTIN_VMHADDSHS }, | |
5494 | { MASK_ALTIVEC, CODE_FOR_altivec_vmhraddshs, "__builtin_altivec_vmhraddshs", ALTIVEC_BUILTIN_VMHRADDSHS }, | |
5495 | { MASK_ALTIVEC, CODE_FOR_altivec_vmladduhm, "__builtin_altivec_vmladduhm", ALTIVEC_BUILTIN_VMLADDUHM}, | |
5496 | { MASK_ALTIVEC, CODE_FOR_altivec_vmsumubm, "__builtin_altivec_vmsumubm", ALTIVEC_BUILTIN_VMSUMUBM }, | |
5497 | { MASK_ALTIVEC, CODE_FOR_altivec_vmsummbm, "__builtin_altivec_vmsummbm", ALTIVEC_BUILTIN_VMSUMMBM }, | |
5498 | { MASK_ALTIVEC, CODE_FOR_altivec_vmsumuhm, "__builtin_altivec_vmsumuhm", ALTIVEC_BUILTIN_VMSUMUHM }, | |
5499 | { MASK_ALTIVEC, CODE_FOR_altivec_vmsumshm, "__builtin_altivec_vmsumshm", ALTIVEC_BUILTIN_VMSUMSHM }, | |
5500 | { MASK_ALTIVEC, CODE_FOR_altivec_vmsumuhs, "__builtin_altivec_vmsumuhs", ALTIVEC_BUILTIN_VMSUMUHS }, | |
5501 | { MASK_ALTIVEC, CODE_FOR_altivec_vmsumshs, "__builtin_altivec_vmsumshs", ALTIVEC_BUILTIN_VMSUMSHS }, | |
f676971a | 5502 | { MASK_ALTIVEC, CODE_FOR_altivec_vnmsubfp, "__builtin_altivec_vnmsubfp", ALTIVEC_BUILTIN_VNMSUBFP }, |
aba5fb01 NS |
5503 | { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v4sf, "__builtin_altivec_vperm_4sf", ALTIVEC_BUILTIN_VPERM_4SF }, |
5504 | { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v4si, "__builtin_altivec_vperm_4si", ALTIVEC_BUILTIN_VPERM_4SI }, | |
5505 | { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v8hi, "__builtin_altivec_vperm_8hi", ALTIVEC_BUILTIN_VPERM_8HI }, | |
5506 | { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v16qi, "__builtin_altivec_vperm_16qi", ALTIVEC_BUILTIN_VPERM_16QI }, | |
5507 | { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v4sf, "__builtin_altivec_vsel_4sf", ALTIVEC_BUILTIN_VSEL_4SF }, | |
5508 | { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v4si, "__builtin_altivec_vsel_4si", ALTIVEC_BUILTIN_VSEL_4SI }, | |
5509 | { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v8hi, "__builtin_altivec_vsel_8hi", ALTIVEC_BUILTIN_VSEL_8HI }, | |
5510 | { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v16qi, "__builtin_altivec_vsel_16qi", ALTIVEC_BUILTIN_VSEL_16QI }, | |
5511 | { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v16qi, "__builtin_altivec_vsldoi_16qi", ALTIVEC_BUILTIN_VSLDOI_16QI }, | |
5512 | { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v8hi, "__builtin_altivec_vsldoi_8hi", ALTIVEC_BUILTIN_VSLDOI_8HI }, | |
5513 | { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v4si, "__builtin_altivec_vsldoi_4si", ALTIVEC_BUILTIN_VSLDOI_4SI }, | |
5514 | { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v4sf, "__builtin_altivec_vsldoi_4sf", ALTIVEC_BUILTIN_VSLDOI_4SF }, | |
24408032 | 5515 | }; |
2212663f | 5516 | |
95385cbb AH |
5517 | /* DST operations: void foo (void *, const int, const char). */ |
5518 | ||
5519 | static const struct builtin_description bdesc_dst[] = | |
5520 | { | |
5521 | { MASK_ALTIVEC, CODE_FOR_altivec_dst, "__builtin_altivec_dst", ALTIVEC_BUILTIN_DST }, | |
5522 | { MASK_ALTIVEC, CODE_FOR_altivec_dstt, "__builtin_altivec_dstt", ALTIVEC_BUILTIN_DSTT }, | |
5523 | { MASK_ALTIVEC, CODE_FOR_altivec_dstst, "__builtin_altivec_dstst", ALTIVEC_BUILTIN_DSTST }, | |
5524 | { MASK_ALTIVEC, CODE_FOR_altivec_dststt, "__builtin_altivec_dststt", ALTIVEC_BUILTIN_DSTSTT } | |
5525 | }; | |
5526 | ||
2212663f | 5527 | /* Simple binary operations: VECc = foo (VECa, VECb). */ |
24408032 | 5528 | |
a3170dc6 | 5529 | static struct builtin_description bdesc_2arg[] = |
0ac081f6 | 5530 | { |
f18c054f DB |
5531 | { MASK_ALTIVEC, CODE_FOR_addv16qi3, "__builtin_altivec_vaddubm", ALTIVEC_BUILTIN_VADDUBM }, |
5532 | { MASK_ALTIVEC, CODE_FOR_addv8hi3, "__builtin_altivec_vadduhm", ALTIVEC_BUILTIN_VADDUHM }, | |
5533 | { MASK_ALTIVEC, CODE_FOR_addv4si3, "__builtin_altivec_vadduwm", ALTIVEC_BUILTIN_VADDUWM }, | |
5534 | { MASK_ALTIVEC, CODE_FOR_addv4sf3, "__builtin_altivec_vaddfp", ALTIVEC_BUILTIN_VADDFP }, | |
0ac081f6 AH |
5535 | { MASK_ALTIVEC, CODE_FOR_altivec_vaddcuw, "__builtin_altivec_vaddcuw", ALTIVEC_BUILTIN_VADDCUW }, |
5536 | { MASK_ALTIVEC, CODE_FOR_altivec_vaddubs, "__builtin_altivec_vaddubs", ALTIVEC_BUILTIN_VADDUBS }, | |
5537 | { MASK_ALTIVEC, CODE_FOR_altivec_vaddsbs, "__builtin_altivec_vaddsbs", ALTIVEC_BUILTIN_VADDSBS }, | |
5538 | { MASK_ALTIVEC, CODE_FOR_altivec_vadduhs, "__builtin_altivec_vadduhs", ALTIVEC_BUILTIN_VADDUHS }, | |
5539 | { MASK_ALTIVEC, CODE_FOR_altivec_vaddshs, "__builtin_altivec_vaddshs", ALTIVEC_BUILTIN_VADDSHS }, | |
5540 | { MASK_ALTIVEC, CODE_FOR_altivec_vadduws, "__builtin_altivec_vadduws", ALTIVEC_BUILTIN_VADDUWS }, | |
5541 | { MASK_ALTIVEC, CODE_FOR_altivec_vaddsws, "__builtin_altivec_vaddsws", ALTIVEC_BUILTIN_VADDSWS }, | |
f18c054f | 5542 | { MASK_ALTIVEC, CODE_FOR_andv4si3, "__builtin_altivec_vand", ALTIVEC_BUILTIN_VAND }, |
aba5fb01 | 5543 | { MASK_ALTIVEC, CODE_FOR_andcv4si3, "__builtin_altivec_vandc", ALTIVEC_BUILTIN_VANDC }, |
0ac081f6 AH |
5544 | { MASK_ALTIVEC, CODE_FOR_altivec_vavgub, "__builtin_altivec_vavgub", ALTIVEC_BUILTIN_VAVGUB }, |
5545 | { MASK_ALTIVEC, CODE_FOR_altivec_vavgsb, "__builtin_altivec_vavgsb", ALTIVEC_BUILTIN_VAVGSB }, | |
5546 | { MASK_ALTIVEC, CODE_FOR_altivec_vavguh, "__builtin_altivec_vavguh", ALTIVEC_BUILTIN_VAVGUH }, | |
5547 | { MASK_ALTIVEC, CODE_FOR_altivec_vavgsh, "__builtin_altivec_vavgsh", ALTIVEC_BUILTIN_VAVGSH }, | |
5548 | { MASK_ALTIVEC, CODE_FOR_altivec_vavguw, "__builtin_altivec_vavguw", ALTIVEC_BUILTIN_VAVGUW }, | |
5549 | { MASK_ALTIVEC, CODE_FOR_altivec_vavgsw, "__builtin_altivec_vavgsw", ALTIVEC_BUILTIN_VAVGSW }, | |
617e0e1d DB |
5550 | { MASK_ALTIVEC, CODE_FOR_altivec_vcfux, "__builtin_altivec_vcfux", ALTIVEC_BUILTIN_VCFUX }, |
5551 | { MASK_ALTIVEC, CODE_FOR_altivec_vcfsx, "__builtin_altivec_vcfsx", ALTIVEC_BUILTIN_VCFSX }, | |
0ac081f6 AH |
5552 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpbfp, "__builtin_altivec_vcmpbfp", ALTIVEC_BUILTIN_VCMPBFP }, |
5553 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequb, "__builtin_altivec_vcmpequb", ALTIVEC_BUILTIN_VCMPEQUB }, | |
5554 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequh, "__builtin_altivec_vcmpequh", ALTIVEC_BUILTIN_VCMPEQUH }, | |
5555 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequw, "__builtin_altivec_vcmpequw", ALTIVEC_BUILTIN_VCMPEQUW }, | |
5556 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpeqfp, "__builtin_altivec_vcmpeqfp", ALTIVEC_BUILTIN_VCMPEQFP }, | |
5557 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgefp, "__builtin_altivec_vcmpgefp", ALTIVEC_BUILTIN_VCMPGEFP }, | |
5558 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtub, "__builtin_altivec_vcmpgtub", ALTIVEC_BUILTIN_VCMPGTUB }, | |
5559 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsb, "__builtin_altivec_vcmpgtsb", ALTIVEC_BUILTIN_VCMPGTSB }, | |
5560 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtuh, "__builtin_altivec_vcmpgtuh", ALTIVEC_BUILTIN_VCMPGTUH }, | |
5561 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsh, "__builtin_altivec_vcmpgtsh", ALTIVEC_BUILTIN_VCMPGTSH }, | |
5562 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtuw, "__builtin_altivec_vcmpgtuw", ALTIVEC_BUILTIN_VCMPGTUW }, | |
5563 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsw, "__builtin_altivec_vcmpgtsw", ALTIVEC_BUILTIN_VCMPGTSW }, | |
5564 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtfp, "__builtin_altivec_vcmpgtfp", ALTIVEC_BUILTIN_VCMPGTFP }, | |
617e0e1d DB |
5565 | { MASK_ALTIVEC, CODE_FOR_altivec_vctsxs, "__builtin_altivec_vctsxs", ALTIVEC_BUILTIN_VCTSXS }, |
5566 | { MASK_ALTIVEC, CODE_FOR_altivec_vctuxs, "__builtin_altivec_vctuxs", ALTIVEC_BUILTIN_VCTUXS }, | |
f18c054f DB |
5567 | { MASK_ALTIVEC, CODE_FOR_umaxv16qi3, "__builtin_altivec_vmaxub", ALTIVEC_BUILTIN_VMAXUB }, |
5568 | { MASK_ALTIVEC, CODE_FOR_smaxv16qi3, "__builtin_altivec_vmaxsb", ALTIVEC_BUILTIN_VMAXSB }, | |
df966bff AH |
5569 | { MASK_ALTIVEC, CODE_FOR_umaxv8hi3, "__builtin_altivec_vmaxuh", ALTIVEC_BUILTIN_VMAXUH }, |
5570 | { MASK_ALTIVEC, CODE_FOR_smaxv8hi3, "__builtin_altivec_vmaxsh", ALTIVEC_BUILTIN_VMAXSH }, | |
5571 | { MASK_ALTIVEC, CODE_FOR_umaxv4si3, "__builtin_altivec_vmaxuw", ALTIVEC_BUILTIN_VMAXUW }, | |
5572 | { MASK_ALTIVEC, CODE_FOR_smaxv4si3, "__builtin_altivec_vmaxsw", ALTIVEC_BUILTIN_VMAXSW }, | |
5573 | { MASK_ALTIVEC, CODE_FOR_smaxv4sf3, "__builtin_altivec_vmaxfp", ALTIVEC_BUILTIN_VMAXFP }, | |
0ac081f6 AH |
5574 | { MASK_ALTIVEC, CODE_FOR_altivec_vmrghb, "__builtin_altivec_vmrghb", ALTIVEC_BUILTIN_VMRGHB }, |
5575 | { MASK_ALTIVEC, CODE_FOR_altivec_vmrghh, "__builtin_altivec_vmrghh", ALTIVEC_BUILTIN_VMRGHH }, | |
5576 | { MASK_ALTIVEC, CODE_FOR_altivec_vmrghw, "__builtin_altivec_vmrghw", ALTIVEC_BUILTIN_VMRGHW }, | |
5577 | { MASK_ALTIVEC, CODE_FOR_altivec_vmrglb, "__builtin_altivec_vmrglb", ALTIVEC_BUILTIN_VMRGLB }, | |
5578 | { MASK_ALTIVEC, CODE_FOR_altivec_vmrglh, "__builtin_altivec_vmrglh", ALTIVEC_BUILTIN_VMRGLH }, | |
5579 | { MASK_ALTIVEC, CODE_FOR_altivec_vmrglw, "__builtin_altivec_vmrglw", ALTIVEC_BUILTIN_VMRGLW }, | |
f18c054f DB |
5580 | { MASK_ALTIVEC, CODE_FOR_uminv16qi3, "__builtin_altivec_vminub", ALTIVEC_BUILTIN_VMINUB }, |
5581 | { MASK_ALTIVEC, CODE_FOR_sminv16qi3, "__builtin_altivec_vminsb", ALTIVEC_BUILTIN_VMINSB }, | |
5582 | { MASK_ALTIVEC, CODE_FOR_uminv8hi3, "__builtin_altivec_vminuh", ALTIVEC_BUILTIN_VMINUH }, | |
5583 | { MASK_ALTIVEC, CODE_FOR_sminv8hi3, "__builtin_altivec_vminsh", ALTIVEC_BUILTIN_VMINSH }, | |
5584 | { MASK_ALTIVEC, CODE_FOR_uminv4si3, "__builtin_altivec_vminuw", ALTIVEC_BUILTIN_VMINUW }, | |
5585 | { MASK_ALTIVEC, CODE_FOR_sminv4si3, "__builtin_altivec_vminsw", ALTIVEC_BUILTIN_VMINSW }, | |
5586 | { MASK_ALTIVEC, CODE_FOR_sminv4sf3, "__builtin_altivec_vminfp", ALTIVEC_BUILTIN_VMINFP }, | |
0ac081f6 AH |
5587 | { MASK_ALTIVEC, CODE_FOR_altivec_vmuleub, "__builtin_altivec_vmuleub", ALTIVEC_BUILTIN_VMULEUB }, |
5588 | { MASK_ALTIVEC, CODE_FOR_altivec_vmulesb, "__builtin_altivec_vmulesb", ALTIVEC_BUILTIN_VMULESB }, | |
5589 | { MASK_ALTIVEC, CODE_FOR_altivec_vmuleuh, "__builtin_altivec_vmuleuh", ALTIVEC_BUILTIN_VMULEUH }, | |
5590 | { MASK_ALTIVEC, CODE_FOR_altivec_vmulesh, "__builtin_altivec_vmulesh", ALTIVEC_BUILTIN_VMULESH }, | |
5591 | { MASK_ALTIVEC, CODE_FOR_altivec_vmuloub, "__builtin_altivec_vmuloub", ALTIVEC_BUILTIN_VMULOUB }, | |
5592 | { MASK_ALTIVEC, CODE_FOR_altivec_vmulosb, "__builtin_altivec_vmulosb", ALTIVEC_BUILTIN_VMULOSB }, | |
5593 | { MASK_ALTIVEC, CODE_FOR_altivec_vmulouh, "__builtin_altivec_vmulouh", ALTIVEC_BUILTIN_VMULOUH }, | |
5594 | { MASK_ALTIVEC, CODE_FOR_altivec_vmulosh, "__builtin_altivec_vmulosh", ALTIVEC_BUILTIN_VMULOSH }, | |
f96bc213 | 5595 | { MASK_ALTIVEC, CODE_FOR_altivec_norv4si3, "__builtin_altivec_vnor", ALTIVEC_BUILTIN_VNOR }, |
f18c054f | 5596 | { MASK_ALTIVEC, CODE_FOR_iorv4si3, "__builtin_altivec_vor", ALTIVEC_BUILTIN_VOR }, |
0ac081f6 AH |
5597 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhum, "__builtin_altivec_vpkuhum", ALTIVEC_BUILTIN_VPKUHUM }, |
5598 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwum, "__builtin_altivec_vpkuwum", ALTIVEC_BUILTIN_VPKUWUM }, | |
5599 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkpx, "__builtin_altivec_vpkpx", ALTIVEC_BUILTIN_VPKPX }, | |
5600 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhss, "__builtin_altivec_vpkuhss", ALTIVEC_BUILTIN_VPKUHSS }, | |
5601 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkshss, "__builtin_altivec_vpkshss", ALTIVEC_BUILTIN_VPKSHSS }, | |
5602 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwss, "__builtin_altivec_vpkuwss", ALTIVEC_BUILTIN_VPKUWSS }, | |
5603 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkswss, "__builtin_altivec_vpkswss", ALTIVEC_BUILTIN_VPKSWSS }, | |
5604 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhus, "__builtin_altivec_vpkuhus", ALTIVEC_BUILTIN_VPKUHUS }, | |
5605 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkshus, "__builtin_altivec_vpkshus", ALTIVEC_BUILTIN_VPKSHUS }, | |
5606 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwus, "__builtin_altivec_vpkuwus", ALTIVEC_BUILTIN_VPKUWUS }, | |
5607 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkswus, "__builtin_altivec_vpkswus", ALTIVEC_BUILTIN_VPKSWUS }, | |
5608 | { MASK_ALTIVEC, CODE_FOR_altivec_vrlb, "__builtin_altivec_vrlb", ALTIVEC_BUILTIN_VRLB }, | |
5609 | { MASK_ALTIVEC, CODE_FOR_altivec_vrlh, "__builtin_altivec_vrlh", ALTIVEC_BUILTIN_VRLH }, | |
5610 | { MASK_ALTIVEC, CODE_FOR_altivec_vrlw, "__builtin_altivec_vrlw", ALTIVEC_BUILTIN_VRLW }, | |
5611 | { MASK_ALTIVEC, CODE_FOR_altivec_vslb, "__builtin_altivec_vslb", ALTIVEC_BUILTIN_VSLB }, | |
5612 | { MASK_ALTIVEC, CODE_FOR_altivec_vslh, "__builtin_altivec_vslh", ALTIVEC_BUILTIN_VSLH }, | |
5613 | { MASK_ALTIVEC, CODE_FOR_altivec_vslw, "__builtin_altivec_vslw", ALTIVEC_BUILTIN_VSLW }, | |
5614 | { MASK_ALTIVEC, CODE_FOR_altivec_vsl, "__builtin_altivec_vsl", ALTIVEC_BUILTIN_VSL }, | |
5615 | { MASK_ALTIVEC, CODE_FOR_altivec_vslo, "__builtin_altivec_vslo", ALTIVEC_BUILTIN_VSLO }, | |
2212663f DB |
5616 | { MASK_ALTIVEC, CODE_FOR_altivec_vspltb, "__builtin_altivec_vspltb", ALTIVEC_BUILTIN_VSPLTB }, |
5617 | { MASK_ALTIVEC, CODE_FOR_altivec_vsplth, "__builtin_altivec_vsplth", ALTIVEC_BUILTIN_VSPLTH }, | |
5618 | { MASK_ALTIVEC, CODE_FOR_altivec_vspltw, "__builtin_altivec_vspltw", ALTIVEC_BUILTIN_VSPLTW }, | |
3e0de9d1 DP |
5619 | { MASK_ALTIVEC, CODE_FOR_lshrv16qi3, "__builtin_altivec_vsrb", ALTIVEC_BUILTIN_VSRB }, |
5620 | { MASK_ALTIVEC, CODE_FOR_lshrv8hi3, "__builtin_altivec_vsrh", ALTIVEC_BUILTIN_VSRH }, | |
5621 | { MASK_ALTIVEC, CODE_FOR_lshrv4si3, "__builtin_altivec_vsrw", ALTIVEC_BUILTIN_VSRW }, | |
5622 | { MASK_ALTIVEC, CODE_FOR_ashrv16qi3, "__builtin_altivec_vsrab", ALTIVEC_BUILTIN_VSRAB }, | |
5623 | { MASK_ALTIVEC, CODE_FOR_ashrv8hi3, "__builtin_altivec_vsrah", ALTIVEC_BUILTIN_VSRAH }, | |
5624 | { MASK_ALTIVEC, CODE_FOR_ashrv4si3, "__builtin_altivec_vsraw", ALTIVEC_BUILTIN_VSRAW }, | |
0ac081f6 AH |
5625 | { MASK_ALTIVEC, CODE_FOR_altivec_vsr, "__builtin_altivec_vsr", ALTIVEC_BUILTIN_VSR }, |
5626 | { MASK_ALTIVEC, CODE_FOR_altivec_vsro, "__builtin_altivec_vsro", ALTIVEC_BUILTIN_VSRO }, | |
f18c054f DB |
5627 | { MASK_ALTIVEC, CODE_FOR_subv16qi3, "__builtin_altivec_vsububm", ALTIVEC_BUILTIN_VSUBUBM }, |
5628 | { MASK_ALTIVEC, CODE_FOR_subv8hi3, "__builtin_altivec_vsubuhm", ALTIVEC_BUILTIN_VSUBUHM }, | |
5629 | { MASK_ALTIVEC, CODE_FOR_subv4si3, "__builtin_altivec_vsubuwm", ALTIVEC_BUILTIN_VSUBUWM }, | |
5630 | { MASK_ALTIVEC, CODE_FOR_subv4sf3, "__builtin_altivec_vsubfp", ALTIVEC_BUILTIN_VSUBFP }, | |
0ac081f6 AH |
5631 | { MASK_ALTIVEC, CODE_FOR_altivec_vsubcuw, "__builtin_altivec_vsubcuw", ALTIVEC_BUILTIN_VSUBCUW }, |
5632 | { MASK_ALTIVEC, CODE_FOR_altivec_vsububs, "__builtin_altivec_vsububs", ALTIVEC_BUILTIN_VSUBUBS }, | |
5633 | { MASK_ALTIVEC, CODE_FOR_altivec_vsubsbs, "__builtin_altivec_vsubsbs", ALTIVEC_BUILTIN_VSUBSBS }, | |
5634 | { MASK_ALTIVEC, CODE_FOR_altivec_vsubuhs, "__builtin_altivec_vsubuhs", ALTIVEC_BUILTIN_VSUBUHS }, | |
5635 | { MASK_ALTIVEC, CODE_FOR_altivec_vsubshs, "__builtin_altivec_vsubshs", ALTIVEC_BUILTIN_VSUBSHS }, | |
5636 | { MASK_ALTIVEC, CODE_FOR_altivec_vsubuws, "__builtin_altivec_vsubuws", ALTIVEC_BUILTIN_VSUBUWS }, | |
5637 | { MASK_ALTIVEC, CODE_FOR_altivec_vsubsws, "__builtin_altivec_vsubsws", ALTIVEC_BUILTIN_VSUBSWS }, | |
5638 | { MASK_ALTIVEC, CODE_FOR_altivec_vsum4ubs, "__builtin_altivec_vsum4ubs", ALTIVEC_BUILTIN_VSUM4UBS }, | |
5639 | { MASK_ALTIVEC, CODE_FOR_altivec_vsum4sbs, "__builtin_altivec_vsum4sbs", ALTIVEC_BUILTIN_VSUM4SBS }, | |
5640 | { MASK_ALTIVEC, CODE_FOR_altivec_vsum4shs, "__builtin_altivec_vsum4shs", ALTIVEC_BUILTIN_VSUM4SHS }, | |
5641 | { MASK_ALTIVEC, CODE_FOR_altivec_vsum2sws, "__builtin_altivec_vsum2sws", ALTIVEC_BUILTIN_VSUM2SWS }, | |
5642 | { MASK_ALTIVEC, CODE_FOR_altivec_vsumsws, "__builtin_altivec_vsumsws", ALTIVEC_BUILTIN_VSUMSWS }, | |
f18c054f | 5643 | { MASK_ALTIVEC, CODE_FOR_xorv4si3, "__builtin_altivec_vxor", ALTIVEC_BUILTIN_VXOR }, |
a3170dc6 AH |
5644 | |
5645 | /* Place holder, leave as first spe builtin. */ | |
5646 | { 0, CODE_FOR_spe_evaddw, "__builtin_spe_evaddw", SPE_BUILTIN_EVADDW }, | |
5647 | { 0, CODE_FOR_spe_evand, "__builtin_spe_evand", SPE_BUILTIN_EVAND }, | |
5648 | { 0, CODE_FOR_spe_evandc, "__builtin_spe_evandc", SPE_BUILTIN_EVANDC }, | |
5649 | { 0, CODE_FOR_spe_evdivws, "__builtin_spe_evdivws", SPE_BUILTIN_EVDIVWS }, | |
5650 | { 0, CODE_FOR_spe_evdivwu, "__builtin_spe_evdivwu", SPE_BUILTIN_EVDIVWU }, | |
5651 | { 0, CODE_FOR_spe_eveqv, "__builtin_spe_eveqv", SPE_BUILTIN_EVEQV }, | |
5652 | { 0, CODE_FOR_spe_evfsadd, "__builtin_spe_evfsadd", SPE_BUILTIN_EVFSADD }, | |
5653 | { 0, CODE_FOR_spe_evfsdiv, "__builtin_spe_evfsdiv", SPE_BUILTIN_EVFSDIV }, | |
5654 | { 0, CODE_FOR_spe_evfsmul, "__builtin_spe_evfsmul", SPE_BUILTIN_EVFSMUL }, | |
5655 | { 0, CODE_FOR_spe_evfssub, "__builtin_spe_evfssub", SPE_BUILTIN_EVFSSUB }, | |
5656 | { 0, CODE_FOR_spe_evmergehi, "__builtin_spe_evmergehi", SPE_BUILTIN_EVMERGEHI }, | |
5657 | { 0, CODE_FOR_spe_evmergehilo, "__builtin_spe_evmergehilo", SPE_BUILTIN_EVMERGEHILO }, | |
5658 | { 0, CODE_FOR_spe_evmergelo, "__builtin_spe_evmergelo", SPE_BUILTIN_EVMERGELO }, | |
5659 | { 0, CODE_FOR_spe_evmergelohi, "__builtin_spe_evmergelohi", SPE_BUILTIN_EVMERGELOHI }, | |
5660 | { 0, CODE_FOR_spe_evmhegsmfaa, "__builtin_spe_evmhegsmfaa", SPE_BUILTIN_EVMHEGSMFAA }, | |
5661 | { 0, CODE_FOR_spe_evmhegsmfan, "__builtin_spe_evmhegsmfan", SPE_BUILTIN_EVMHEGSMFAN }, | |
5662 | { 0, CODE_FOR_spe_evmhegsmiaa, "__builtin_spe_evmhegsmiaa", SPE_BUILTIN_EVMHEGSMIAA }, | |
5663 | { 0, CODE_FOR_spe_evmhegsmian, "__builtin_spe_evmhegsmian", SPE_BUILTIN_EVMHEGSMIAN }, | |
5664 | { 0, CODE_FOR_spe_evmhegumiaa, "__builtin_spe_evmhegumiaa", SPE_BUILTIN_EVMHEGUMIAA }, | |
5665 | { 0, CODE_FOR_spe_evmhegumian, "__builtin_spe_evmhegumian", SPE_BUILTIN_EVMHEGUMIAN }, | |
5666 | { 0, CODE_FOR_spe_evmhesmf, "__builtin_spe_evmhesmf", SPE_BUILTIN_EVMHESMF }, | |
5667 | { 0, CODE_FOR_spe_evmhesmfa, "__builtin_spe_evmhesmfa", SPE_BUILTIN_EVMHESMFA }, | |
5668 | { 0, CODE_FOR_spe_evmhesmfaaw, "__builtin_spe_evmhesmfaaw", SPE_BUILTIN_EVMHESMFAAW }, | |
5669 | { 0, CODE_FOR_spe_evmhesmfanw, "__builtin_spe_evmhesmfanw", SPE_BUILTIN_EVMHESMFANW }, | |
5670 | { 0, CODE_FOR_spe_evmhesmi, "__builtin_spe_evmhesmi", SPE_BUILTIN_EVMHESMI }, | |
5671 | { 0, CODE_FOR_spe_evmhesmia, "__builtin_spe_evmhesmia", SPE_BUILTIN_EVMHESMIA }, | |
5672 | { 0, CODE_FOR_spe_evmhesmiaaw, "__builtin_spe_evmhesmiaaw", SPE_BUILTIN_EVMHESMIAAW }, | |
5673 | { 0, CODE_FOR_spe_evmhesmianw, "__builtin_spe_evmhesmianw", SPE_BUILTIN_EVMHESMIANW }, | |
5674 | { 0, CODE_FOR_spe_evmhessf, "__builtin_spe_evmhessf", SPE_BUILTIN_EVMHESSF }, | |
5675 | { 0, CODE_FOR_spe_evmhessfa, "__builtin_spe_evmhessfa", SPE_BUILTIN_EVMHESSFA }, | |
5676 | { 0, CODE_FOR_spe_evmhessfaaw, "__builtin_spe_evmhessfaaw", SPE_BUILTIN_EVMHESSFAAW }, | |
5677 | { 0, CODE_FOR_spe_evmhessfanw, "__builtin_spe_evmhessfanw", SPE_BUILTIN_EVMHESSFANW }, | |
5678 | { 0, CODE_FOR_spe_evmhessiaaw, "__builtin_spe_evmhessiaaw", SPE_BUILTIN_EVMHESSIAAW }, | |
5679 | { 0, CODE_FOR_spe_evmhessianw, "__builtin_spe_evmhessianw", SPE_BUILTIN_EVMHESSIANW }, | |
5680 | { 0, CODE_FOR_spe_evmheumi, "__builtin_spe_evmheumi", SPE_BUILTIN_EVMHEUMI }, | |
5681 | { 0, CODE_FOR_spe_evmheumia, "__builtin_spe_evmheumia", SPE_BUILTIN_EVMHEUMIA }, | |
5682 | { 0, CODE_FOR_spe_evmheumiaaw, "__builtin_spe_evmheumiaaw", SPE_BUILTIN_EVMHEUMIAAW }, | |
5683 | { 0, CODE_FOR_spe_evmheumianw, "__builtin_spe_evmheumianw", SPE_BUILTIN_EVMHEUMIANW }, | |
5684 | { 0, CODE_FOR_spe_evmheusiaaw, "__builtin_spe_evmheusiaaw", SPE_BUILTIN_EVMHEUSIAAW }, | |
5685 | { 0, CODE_FOR_spe_evmheusianw, "__builtin_spe_evmheusianw", SPE_BUILTIN_EVMHEUSIANW }, | |
5686 | { 0, CODE_FOR_spe_evmhogsmfaa, "__builtin_spe_evmhogsmfaa", SPE_BUILTIN_EVMHOGSMFAA }, | |
5687 | { 0, CODE_FOR_spe_evmhogsmfan, "__builtin_spe_evmhogsmfan", SPE_BUILTIN_EVMHOGSMFAN }, | |
5688 | { 0, CODE_FOR_spe_evmhogsmiaa, "__builtin_spe_evmhogsmiaa", SPE_BUILTIN_EVMHOGSMIAA }, | |
5689 | { 0, CODE_FOR_spe_evmhogsmian, "__builtin_spe_evmhogsmian", SPE_BUILTIN_EVMHOGSMIAN }, | |
5690 | { 0, CODE_FOR_spe_evmhogumiaa, "__builtin_spe_evmhogumiaa", SPE_BUILTIN_EVMHOGUMIAA }, | |
5691 | { 0, CODE_FOR_spe_evmhogumian, "__builtin_spe_evmhogumian", SPE_BUILTIN_EVMHOGUMIAN }, | |
5692 | { 0, CODE_FOR_spe_evmhosmf, "__builtin_spe_evmhosmf", SPE_BUILTIN_EVMHOSMF }, | |
5693 | { 0, CODE_FOR_spe_evmhosmfa, "__builtin_spe_evmhosmfa", SPE_BUILTIN_EVMHOSMFA }, | |
5694 | { 0, CODE_FOR_spe_evmhosmfaaw, "__builtin_spe_evmhosmfaaw", SPE_BUILTIN_EVMHOSMFAAW }, | |
5695 | { 0, CODE_FOR_spe_evmhosmfanw, "__builtin_spe_evmhosmfanw", SPE_BUILTIN_EVMHOSMFANW }, | |
5696 | { 0, CODE_FOR_spe_evmhosmi, "__builtin_spe_evmhosmi", SPE_BUILTIN_EVMHOSMI }, | |
5697 | { 0, CODE_FOR_spe_evmhosmia, "__builtin_spe_evmhosmia", SPE_BUILTIN_EVMHOSMIA }, | |
5698 | { 0, CODE_FOR_spe_evmhosmiaaw, "__builtin_spe_evmhosmiaaw", SPE_BUILTIN_EVMHOSMIAAW }, | |
5699 | { 0, CODE_FOR_spe_evmhosmianw, "__builtin_spe_evmhosmianw", SPE_BUILTIN_EVMHOSMIANW }, | |
5700 | { 0, CODE_FOR_spe_evmhossf, "__builtin_spe_evmhossf", SPE_BUILTIN_EVMHOSSF }, | |
5701 | { 0, CODE_FOR_spe_evmhossfa, "__builtin_spe_evmhossfa", SPE_BUILTIN_EVMHOSSFA }, | |
5702 | { 0, CODE_FOR_spe_evmhossfaaw, "__builtin_spe_evmhossfaaw", SPE_BUILTIN_EVMHOSSFAAW }, | |
5703 | { 0, CODE_FOR_spe_evmhossfanw, "__builtin_spe_evmhossfanw", SPE_BUILTIN_EVMHOSSFANW }, | |
5704 | { 0, CODE_FOR_spe_evmhossiaaw, "__builtin_spe_evmhossiaaw", SPE_BUILTIN_EVMHOSSIAAW }, | |
5705 | { 0, CODE_FOR_spe_evmhossianw, "__builtin_spe_evmhossianw", SPE_BUILTIN_EVMHOSSIANW }, | |
5706 | { 0, CODE_FOR_spe_evmhoumi, "__builtin_spe_evmhoumi", SPE_BUILTIN_EVMHOUMI }, | |
5707 | { 0, CODE_FOR_spe_evmhoumia, "__builtin_spe_evmhoumia", SPE_BUILTIN_EVMHOUMIA }, | |
5708 | { 0, CODE_FOR_spe_evmhoumiaaw, "__builtin_spe_evmhoumiaaw", SPE_BUILTIN_EVMHOUMIAAW }, | |
5709 | { 0, CODE_FOR_spe_evmhoumianw, "__builtin_spe_evmhoumianw", SPE_BUILTIN_EVMHOUMIANW }, | |
5710 | { 0, CODE_FOR_spe_evmhousiaaw, "__builtin_spe_evmhousiaaw", SPE_BUILTIN_EVMHOUSIAAW }, | |
5711 | { 0, CODE_FOR_spe_evmhousianw, "__builtin_spe_evmhousianw", SPE_BUILTIN_EVMHOUSIANW }, | |
5712 | { 0, CODE_FOR_spe_evmwhsmf, "__builtin_spe_evmwhsmf", SPE_BUILTIN_EVMWHSMF }, | |
5713 | { 0, CODE_FOR_spe_evmwhsmfa, "__builtin_spe_evmwhsmfa", SPE_BUILTIN_EVMWHSMFA }, | |
5714 | { 0, CODE_FOR_spe_evmwhsmi, "__builtin_spe_evmwhsmi", SPE_BUILTIN_EVMWHSMI }, | |
5715 | { 0, CODE_FOR_spe_evmwhsmia, "__builtin_spe_evmwhsmia", SPE_BUILTIN_EVMWHSMIA }, | |
5716 | { 0, CODE_FOR_spe_evmwhssf, "__builtin_spe_evmwhssf", SPE_BUILTIN_EVMWHSSF }, | |
5717 | { 0, CODE_FOR_spe_evmwhssfa, "__builtin_spe_evmwhssfa", SPE_BUILTIN_EVMWHSSFA }, | |
5718 | { 0, CODE_FOR_spe_evmwhumi, "__builtin_spe_evmwhumi", SPE_BUILTIN_EVMWHUMI }, | |
5719 | { 0, CODE_FOR_spe_evmwhumia, "__builtin_spe_evmwhumia", SPE_BUILTIN_EVMWHUMIA }, | |
a3170dc6 AH |
5720 | { 0, CODE_FOR_spe_evmwlsmiaaw, "__builtin_spe_evmwlsmiaaw", SPE_BUILTIN_EVMWLSMIAAW }, |
5721 | { 0, CODE_FOR_spe_evmwlsmianw, "__builtin_spe_evmwlsmianw", SPE_BUILTIN_EVMWLSMIANW }, | |
a3170dc6 AH |
5722 | { 0, CODE_FOR_spe_evmwlssiaaw, "__builtin_spe_evmwlssiaaw", SPE_BUILTIN_EVMWLSSIAAW }, |
5723 | { 0, CODE_FOR_spe_evmwlssianw, "__builtin_spe_evmwlssianw", SPE_BUILTIN_EVMWLSSIANW }, | |
5724 | { 0, CODE_FOR_spe_evmwlumi, "__builtin_spe_evmwlumi", SPE_BUILTIN_EVMWLUMI }, | |
5725 | { 0, CODE_FOR_spe_evmwlumia, "__builtin_spe_evmwlumia", SPE_BUILTIN_EVMWLUMIA }, | |
5726 | { 0, CODE_FOR_spe_evmwlumiaaw, "__builtin_spe_evmwlumiaaw", SPE_BUILTIN_EVMWLUMIAAW }, | |
5727 | { 0, CODE_FOR_spe_evmwlumianw, "__builtin_spe_evmwlumianw", SPE_BUILTIN_EVMWLUMIANW }, | |
5728 | { 0, CODE_FOR_spe_evmwlusiaaw, "__builtin_spe_evmwlusiaaw", SPE_BUILTIN_EVMWLUSIAAW }, | |
5729 | { 0, CODE_FOR_spe_evmwlusianw, "__builtin_spe_evmwlusianw", SPE_BUILTIN_EVMWLUSIANW }, | |
5730 | { 0, CODE_FOR_spe_evmwsmf, "__builtin_spe_evmwsmf", SPE_BUILTIN_EVMWSMF }, | |
5731 | { 0, CODE_FOR_spe_evmwsmfa, "__builtin_spe_evmwsmfa", SPE_BUILTIN_EVMWSMFA }, | |
5732 | { 0, CODE_FOR_spe_evmwsmfaa, "__builtin_spe_evmwsmfaa", SPE_BUILTIN_EVMWSMFAA }, | |
5733 | { 0, CODE_FOR_spe_evmwsmfan, "__builtin_spe_evmwsmfan", SPE_BUILTIN_EVMWSMFAN }, | |
5734 | { 0, CODE_FOR_spe_evmwsmi, "__builtin_spe_evmwsmi", SPE_BUILTIN_EVMWSMI }, | |
5735 | { 0, CODE_FOR_spe_evmwsmia, "__builtin_spe_evmwsmia", SPE_BUILTIN_EVMWSMIA }, | |
5736 | { 0, CODE_FOR_spe_evmwsmiaa, "__builtin_spe_evmwsmiaa", SPE_BUILTIN_EVMWSMIAA }, | |
5737 | { 0, CODE_FOR_spe_evmwsmian, "__builtin_spe_evmwsmian", SPE_BUILTIN_EVMWSMIAN }, | |
5738 | { 0, CODE_FOR_spe_evmwssf, "__builtin_spe_evmwssf", SPE_BUILTIN_EVMWSSF }, | |
5739 | { 0, CODE_FOR_spe_evmwssfa, "__builtin_spe_evmwssfa", SPE_BUILTIN_EVMWSSFA }, | |
5740 | { 0, CODE_FOR_spe_evmwssfaa, "__builtin_spe_evmwssfaa", SPE_BUILTIN_EVMWSSFAA }, | |
5741 | { 0, CODE_FOR_spe_evmwssfan, "__builtin_spe_evmwssfan", SPE_BUILTIN_EVMWSSFAN }, | |
5742 | { 0, CODE_FOR_spe_evmwumi, "__builtin_spe_evmwumi", SPE_BUILTIN_EVMWUMI }, | |
5743 | { 0, CODE_FOR_spe_evmwumia, "__builtin_spe_evmwumia", SPE_BUILTIN_EVMWUMIA }, | |
5744 | { 0, CODE_FOR_spe_evmwumiaa, "__builtin_spe_evmwumiaa", SPE_BUILTIN_EVMWUMIAA }, | |
5745 | { 0, CODE_FOR_spe_evmwumian, "__builtin_spe_evmwumian", SPE_BUILTIN_EVMWUMIAN }, | |
5746 | { 0, CODE_FOR_spe_evnand, "__builtin_spe_evnand", SPE_BUILTIN_EVNAND }, | |
5747 | { 0, CODE_FOR_spe_evnor, "__builtin_spe_evnor", SPE_BUILTIN_EVNOR }, | |
5748 | { 0, CODE_FOR_spe_evor, "__builtin_spe_evor", SPE_BUILTIN_EVOR }, | |
5749 | { 0, CODE_FOR_spe_evorc, "__builtin_spe_evorc", SPE_BUILTIN_EVORC }, | |
5750 | { 0, CODE_FOR_spe_evrlw, "__builtin_spe_evrlw", SPE_BUILTIN_EVRLW }, | |
5751 | { 0, CODE_FOR_spe_evslw, "__builtin_spe_evslw", SPE_BUILTIN_EVSLW }, | |
5752 | { 0, CODE_FOR_spe_evsrws, "__builtin_spe_evsrws", SPE_BUILTIN_EVSRWS }, | |
5753 | { 0, CODE_FOR_spe_evsrwu, "__builtin_spe_evsrwu", SPE_BUILTIN_EVSRWU }, | |
5754 | { 0, CODE_FOR_spe_evsubfw, "__builtin_spe_evsubfw", SPE_BUILTIN_EVSUBFW }, | |
5755 | ||
5756 | /* SPE binary operations expecting a 5-bit unsigned literal. */ | |
5757 | { 0, CODE_FOR_spe_evaddiw, "__builtin_spe_evaddiw", SPE_BUILTIN_EVADDIW }, | |
5758 | ||
5759 | { 0, CODE_FOR_spe_evrlwi, "__builtin_spe_evrlwi", SPE_BUILTIN_EVRLWI }, | |
5760 | { 0, CODE_FOR_spe_evslwi, "__builtin_spe_evslwi", SPE_BUILTIN_EVSLWI }, | |
5761 | { 0, CODE_FOR_spe_evsrwis, "__builtin_spe_evsrwis", SPE_BUILTIN_EVSRWIS }, | |
5762 | { 0, CODE_FOR_spe_evsrwiu, "__builtin_spe_evsrwiu", SPE_BUILTIN_EVSRWIU }, | |
5763 | { 0, CODE_FOR_spe_evsubifw, "__builtin_spe_evsubifw", SPE_BUILTIN_EVSUBIFW }, | |
5764 | { 0, CODE_FOR_spe_evmwhssfaa, "__builtin_spe_evmwhssfaa", SPE_BUILTIN_EVMWHSSFAA }, | |
5765 | { 0, CODE_FOR_spe_evmwhssmaa, "__builtin_spe_evmwhssmaa", SPE_BUILTIN_EVMWHSSMAA }, | |
5766 | { 0, CODE_FOR_spe_evmwhsmfaa, "__builtin_spe_evmwhsmfaa", SPE_BUILTIN_EVMWHSMFAA }, | |
5767 | { 0, CODE_FOR_spe_evmwhsmiaa, "__builtin_spe_evmwhsmiaa", SPE_BUILTIN_EVMWHSMIAA }, | |
5768 | { 0, CODE_FOR_spe_evmwhusiaa, "__builtin_spe_evmwhusiaa", SPE_BUILTIN_EVMWHUSIAA }, | |
5769 | { 0, CODE_FOR_spe_evmwhumiaa, "__builtin_spe_evmwhumiaa", SPE_BUILTIN_EVMWHUMIAA }, | |
5770 | { 0, CODE_FOR_spe_evmwhssfan, "__builtin_spe_evmwhssfan", SPE_BUILTIN_EVMWHSSFAN }, | |
5771 | { 0, CODE_FOR_spe_evmwhssian, "__builtin_spe_evmwhssian", SPE_BUILTIN_EVMWHSSIAN }, | |
5772 | { 0, CODE_FOR_spe_evmwhsmfan, "__builtin_spe_evmwhsmfan", SPE_BUILTIN_EVMWHSMFAN }, | |
5773 | { 0, CODE_FOR_spe_evmwhsmian, "__builtin_spe_evmwhsmian", SPE_BUILTIN_EVMWHSMIAN }, | |
5774 | { 0, CODE_FOR_spe_evmwhusian, "__builtin_spe_evmwhusian", SPE_BUILTIN_EVMWHUSIAN }, | |
5775 | { 0, CODE_FOR_spe_evmwhumian, "__builtin_spe_evmwhumian", SPE_BUILTIN_EVMWHUMIAN }, | |
5776 | { 0, CODE_FOR_spe_evmwhgssfaa, "__builtin_spe_evmwhgssfaa", SPE_BUILTIN_EVMWHGSSFAA }, | |
5777 | { 0, CODE_FOR_spe_evmwhgsmfaa, "__builtin_spe_evmwhgsmfaa", SPE_BUILTIN_EVMWHGSMFAA }, | |
5778 | { 0, CODE_FOR_spe_evmwhgsmiaa, "__builtin_spe_evmwhgsmiaa", SPE_BUILTIN_EVMWHGSMIAA }, | |
5779 | { 0, CODE_FOR_spe_evmwhgumiaa, "__builtin_spe_evmwhgumiaa", SPE_BUILTIN_EVMWHGUMIAA }, | |
5780 | { 0, CODE_FOR_spe_evmwhgssfan, "__builtin_spe_evmwhgssfan", SPE_BUILTIN_EVMWHGSSFAN }, | |
5781 | { 0, CODE_FOR_spe_evmwhgsmfan, "__builtin_spe_evmwhgsmfan", SPE_BUILTIN_EVMWHGSMFAN }, | |
5782 | { 0, CODE_FOR_spe_evmwhgsmian, "__builtin_spe_evmwhgsmian", SPE_BUILTIN_EVMWHGSMIAN }, | |
5783 | { 0, CODE_FOR_spe_evmwhgumian, "__builtin_spe_evmwhgumian", SPE_BUILTIN_EVMWHGUMIAN }, | |
5784 | { 0, CODE_FOR_spe_brinc, "__builtin_spe_brinc", SPE_BUILTIN_BRINC }, | |
5785 | ||
5786 | /* Place-holder. Leave as last binary SPE builtin. */ | |
17edbda5 | 5787 | { 0, CODE_FOR_xorv2si3, "__builtin_spe_evxor", SPE_BUILTIN_EVXOR }, |
ae4b4a02 AH |
5788 | }; |
5789 | ||
5790 | /* AltiVec predicates. */ | |
5791 | ||
5792 | struct builtin_description_predicates | |
5793 | { | |
5794 | const unsigned int mask; | |
5795 | const enum insn_code icode; | |
5796 | const char *opcode; | |
5797 | const char *const name; | |
5798 | const enum rs6000_builtins code; | |
5799 | }; | |
5800 | ||
5801 | static const struct builtin_description_predicates bdesc_altivec_preds[] = | |
5802 | { | |
5803 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpbfp.", "__builtin_altivec_vcmpbfp_p", ALTIVEC_BUILTIN_VCMPBFP_P }, | |
5804 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpeqfp.", "__builtin_altivec_vcmpeqfp_p", ALTIVEC_BUILTIN_VCMPEQFP_P }, | |
5805 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpgefp.", "__builtin_altivec_vcmpgefp_p", ALTIVEC_BUILTIN_VCMPGEFP_P }, | |
5806 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpgtfp.", "__builtin_altivec_vcmpgtfp_p", ALTIVEC_BUILTIN_VCMPGTFP_P }, | |
5807 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpequw.", "__builtin_altivec_vcmpequw_p", ALTIVEC_BUILTIN_VCMPEQUW_P }, | |
5808 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpgtsw.", "__builtin_altivec_vcmpgtsw_p", ALTIVEC_BUILTIN_VCMPGTSW_P }, | |
5809 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpgtuw.", "__builtin_altivec_vcmpgtuw_p", ALTIVEC_BUILTIN_VCMPGTUW_P }, | |
5810 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpgtuh.", "__builtin_altivec_vcmpgtuh_p", ALTIVEC_BUILTIN_VCMPGTUH_P }, | |
5811 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpgtsh.", "__builtin_altivec_vcmpgtsh_p", ALTIVEC_BUILTIN_VCMPGTSH_P }, | |
5812 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpequh.", "__builtin_altivec_vcmpequh_p", ALTIVEC_BUILTIN_VCMPEQUH_P }, | |
5813 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpequb.", "__builtin_altivec_vcmpequb_p", ALTIVEC_BUILTIN_VCMPEQUB_P }, | |
5814 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpgtsb.", "__builtin_altivec_vcmpgtsb_p", ALTIVEC_BUILTIN_VCMPGTSB_P }, | |
5815 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpgtub.", "__builtin_altivec_vcmpgtub_p", ALTIVEC_BUILTIN_VCMPGTUB_P } | |
0ac081f6 | 5816 | }; |
24408032 | 5817 | |
a3170dc6 AH |
5818 | /* SPE predicates. */ |
5819 | static struct builtin_description bdesc_spe_predicates[] = | |
5820 | { | |
5821 | /* Place-holder. Leave as first. */ | |
5822 | { 0, CODE_FOR_spe_evcmpeq, "__builtin_spe_evcmpeq", SPE_BUILTIN_EVCMPEQ }, | |
5823 | { 0, CODE_FOR_spe_evcmpgts, "__builtin_spe_evcmpgts", SPE_BUILTIN_EVCMPGTS }, | |
5824 | { 0, CODE_FOR_spe_evcmpgtu, "__builtin_spe_evcmpgtu", SPE_BUILTIN_EVCMPGTU }, | |
5825 | { 0, CODE_FOR_spe_evcmplts, "__builtin_spe_evcmplts", SPE_BUILTIN_EVCMPLTS }, | |
5826 | { 0, CODE_FOR_spe_evcmpltu, "__builtin_spe_evcmpltu", SPE_BUILTIN_EVCMPLTU }, | |
5827 | { 0, CODE_FOR_spe_evfscmpeq, "__builtin_spe_evfscmpeq", SPE_BUILTIN_EVFSCMPEQ }, | |
5828 | { 0, CODE_FOR_spe_evfscmpgt, "__builtin_spe_evfscmpgt", SPE_BUILTIN_EVFSCMPGT }, | |
5829 | { 0, CODE_FOR_spe_evfscmplt, "__builtin_spe_evfscmplt", SPE_BUILTIN_EVFSCMPLT }, | |
5830 | { 0, CODE_FOR_spe_evfststeq, "__builtin_spe_evfststeq", SPE_BUILTIN_EVFSTSTEQ }, | |
5831 | { 0, CODE_FOR_spe_evfststgt, "__builtin_spe_evfststgt", SPE_BUILTIN_EVFSTSTGT }, | |
5832 | /* Place-holder. Leave as last. */ | |
5833 | { 0, CODE_FOR_spe_evfststlt, "__builtin_spe_evfststlt", SPE_BUILTIN_EVFSTSTLT }, | |
5834 | }; | |
5835 | ||
5836 | /* SPE evsel predicates. */ | |
5837 | static struct builtin_description bdesc_spe_evsel[] = | |
5838 | { | |
5839 | /* Place-holder. Leave as first. */ | |
5840 | { 0, CODE_FOR_spe_evcmpgts, "__builtin_spe_evsel_gts", SPE_BUILTIN_EVSEL_CMPGTS }, | |
5841 | { 0, CODE_FOR_spe_evcmpgtu, "__builtin_spe_evsel_gtu", SPE_BUILTIN_EVSEL_CMPGTU }, | |
5842 | { 0, CODE_FOR_spe_evcmplts, "__builtin_spe_evsel_lts", SPE_BUILTIN_EVSEL_CMPLTS }, | |
5843 | { 0, CODE_FOR_spe_evcmpltu, "__builtin_spe_evsel_ltu", SPE_BUILTIN_EVSEL_CMPLTU }, | |
5844 | { 0, CODE_FOR_spe_evcmpeq, "__builtin_spe_evsel_eq", SPE_BUILTIN_EVSEL_CMPEQ }, | |
5845 | { 0, CODE_FOR_spe_evfscmpgt, "__builtin_spe_evsel_fsgt", SPE_BUILTIN_EVSEL_FSCMPGT }, | |
5846 | { 0, CODE_FOR_spe_evfscmplt, "__builtin_spe_evsel_fslt", SPE_BUILTIN_EVSEL_FSCMPLT }, | |
5847 | { 0, CODE_FOR_spe_evfscmpeq, "__builtin_spe_evsel_fseq", SPE_BUILTIN_EVSEL_FSCMPEQ }, | |
5848 | { 0, CODE_FOR_spe_evfststgt, "__builtin_spe_evsel_fststgt", SPE_BUILTIN_EVSEL_FSTSTGT }, | |
5849 | { 0, CODE_FOR_spe_evfststlt, "__builtin_spe_evsel_fststlt", SPE_BUILTIN_EVSEL_FSTSTLT }, | |
5850 | /* Place-holder. Leave as last. */ | |
5851 | { 0, CODE_FOR_spe_evfststeq, "__builtin_spe_evsel_fststeq", SPE_BUILTIN_EVSEL_FSTSTEQ }, | |
5852 | }; | |
5853 | ||
b6d08ca1 | 5854 | /* ABS* operations. */ |
100c4561 AH |
5855 | |
5856 | static const struct builtin_description bdesc_abs[] = | |
5857 | { | |
5858 | { MASK_ALTIVEC, CODE_FOR_absv4si2, "__builtin_altivec_abs_v4si", ALTIVEC_BUILTIN_ABS_V4SI }, | |
5859 | { MASK_ALTIVEC, CODE_FOR_absv8hi2, "__builtin_altivec_abs_v8hi", ALTIVEC_BUILTIN_ABS_V8HI }, | |
5860 | { MASK_ALTIVEC, CODE_FOR_absv4sf2, "__builtin_altivec_abs_v4sf", ALTIVEC_BUILTIN_ABS_V4SF }, | |
5861 | { MASK_ALTIVEC, CODE_FOR_absv16qi2, "__builtin_altivec_abs_v16qi", ALTIVEC_BUILTIN_ABS_V16QI }, | |
5862 | { MASK_ALTIVEC, CODE_FOR_altivec_abss_v4si, "__builtin_altivec_abss_v4si", ALTIVEC_BUILTIN_ABSS_V4SI }, | |
5863 | { MASK_ALTIVEC, CODE_FOR_altivec_abss_v8hi, "__builtin_altivec_abss_v8hi", ALTIVEC_BUILTIN_ABSS_V8HI }, | |
5864 | { MASK_ALTIVEC, CODE_FOR_altivec_abss_v16qi, "__builtin_altivec_abss_v16qi", ALTIVEC_BUILTIN_ABSS_V16QI } | |
5865 | }; | |
5866 | ||
617e0e1d DB |
5867 | /* Simple unary operations: VECb = foo (unsigned literal) or VECb = |
5868 | foo (VECa). */ | |
24408032 | 5869 | |
a3170dc6 | 5870 | static struct builtin_description bdesc_1arg[] = |
2212663f | 5871 | { |
617e0e1d DB |
5872 | { MASK_ALTIVEC, CODE_FOR_altivec_vexptefp, "__builtin_altivec_vexptefp", ALTIVEC_BUILTIN_VEXPTEFP }, |
5873 | { MASK_ALTIVEC, CODE_FOR_altivec_vlogefp, "__builtin_altivec_vlogefp", ALTIVEC_BUILTIN_VLOGEFP }, | |
5874 | { MASK_ALTIVEC, CODE_FOR_altivec_vrefp, "__builtin_altivec_vrefp", ALTIVEC_BUILTIN_VREFP }, | |
5875 | { MASK_ALTIVEC, CODE_FOR_altivec_vrfim, "__builtin_altivec_vrfim", ALTIVEC_BUILTIN_VRFIM }, | |
5876 | { MASK_ALTIVEC, CODE_FOR_altivec_vrfin, "__builtin_altivec_vrfin", ALTIVEC_BUILTIN_VRFIN }, | |
5877 | { MASK_ALTIVEC, CODE_FOR_altivec_vrfip, "__builtin_altivec_vrfip", ALTIVEC_BUILTIN_VRFIP }, | |
5878 | { MASK_ALTIVEC, CODE_FOR_ftruncv4sf2, "__builtin_altivec_vrfiz", ALTIVEC_BUILTIN_VRFIZ }, | |
5879 | { MASK_ALTIVEC, CODE_FOR_altivec_vrsqrtefp, "__builtin_altivec_vrsqrtefp", ALTIVEC_BUILTIN_VRSQRTEFP }, | |
2212663f DB |
5880 | { MASK_ALTIVEC, CODE_FOR_altivec_vspltisb, "__builtin_altivec_vspltisb", ALTIVEC_BUILTIN_VSPLTISB }, |
5881 | { MASK_ALTIVEC, CODE_FOR_altivec_vspltish, "__builtin_altivec_vspltish", ALTIVEC_BUILTIN_VSPLTISH }, | |
5882 | { MASK_ALTIVEC, CODE_FOR_altivec_vspltisw, "__builtin_altivec_vspltisw", ALTIVEC_BUILTIN_VSPLTISW }, | |
20e26713 AH |
5883 | { MASK_ALTIVEC, CODE_FOR_altivec_vupkhsb, "__builtin_altivec_vupkhsb", ALTIVEC_BUILTIN_VUPKHSB }, |
5884 | { MASK_ALTIVEC, CODE_FOR_altivec_vupkhpx, "__builtin_altivec_vupkhpx", ALTIVEC_BUILTIN_VUPKHPX }, | |
5885 | { MASK_ALTIVEC, CODE_FOR_altivec_vupkhsh, "__builtin_altivec_vupkhsh", ALTIVEC_BUILTIN_VUPKHSH }, | |
5886 | { MASK_ALTIVEC, CODE_FOR_altivec_vupklsb, "__builtin_altivec_vupklsb", ALTIVEC_BUILTIN_VUPKLSB }, | |
5887 | { MASK_ALTIVEC, CODE_FOR_altivec_vupklpx, "__builtin_altivec_vupklpx", ALTIVEC_BUILTIN_VUPKLPX }, | |
5888 | { MASK_ALTIVEC, CODE_FOR_altivec_vupklsh, "__builtin_altivec_vupklsh", ALTIVEC_BUILTIN_VUPKLSH }, | |
a3170dc6 AH |
5889 | |
5890 | /* The SPE unary builtins must start with SPE_BUILTIN_EVABS and | |
5891 | end with SPE_BUILTIN_EVSUBFUSIAAW. */ | |
5892 | { 0, CODE_FOR_spe_evabs, "__builtin_spe_evabs", SPE_BUILTIN_EVABS }, | |
5893 | { 0, CODE_FOR_spe_evaddsmiaaw, "__builtin_spe_evaddsmiaaw", SPE_BUILTIN_EVADDSMIAAW }, | |
5894 | { 0, CODE_FOR_spe_evaddssiaaw, "__builtin_spe_evaddssiaaw", SPE_BUILTIN_EVADDSSIAAW }, | |
5895 | { 0, CODE_FOR_spe_evaddumiaaw, "__builtin_spe_evaddumiaaw", SPE_BUILTIN_EVADDUMIAAW }, | |
5896 | { 0, CODE_FOR_spe_evaddusiaaw, "__builtin_spe_evaddusiaaw", SPE_BUILTIN_EVADDUSIAAW }, | |
5897 | { 0, CODE_FOR_spe_evcntlsw, "__builtin_spe_evcntlsw", SPE_BUILTIN_EVCNTLSW }, | |
5898 | { 0, CODE_FOR_spe_evcntlzw, "__builtin_spe_evcntlzw", SPE_BUILTIN_EVCNTLZW }, | |
5899 | { 0, CODE_FOR_spe_evextsb, "__builtin_spe_evextsb", SPE_BUILTIN_EVEXTSB }, | |
5900 | { 0, CODE_FOR_spe_evextsh, "__builtin_spe_evextsh", SPE_BUILTIN_EVEXTSH }, | |
5901 | { 0, CODE_FOR_spe_evfsabs, "__builtin_spe_evfsabs", SPE_BUILTIN_EVFSABS }, | |
5902 | { 0, CODE_FOR_spe_evfscfsf, "__builtin_spe_evfscfsf", SPE_BUILTIN_EVFSCFSF }, | |
5903 | { 0, CODE_FOR_spe_evfscfsi, "__builtin_spe_evfscfsi", SPE_BUILTIN_EVFSCFSI }, | |
5904 | { 0, CODE_FOR_spe_evfscfuf, "__builtin_spe_evfscfuf", SPE_BUILTIN_EVFSCFUF }, | |
5905 | { 0, CODE_FOR_spe_evfscfui, "__builtin_spe_evfscfui", SPE_BUILTIN_EVFSCFUI }, | |
5906 | { 0, CODE_FOR_spe_evfsctsf, "__builtin_spe_evfsctsf", SPE_BUILTIN_EVFSCTSF }, | |
5907 | { 0, CODE_FOR_spe_evfsctsi, "__builtin_spe_evfsctsi", SPE_BUILTIN_EVFSCTSI }, | |
5908 | { 0, CODE_FOR_spe_evfsctsiz, "__builtin_spe_evfsctsiz", SPE_BUILTIN_EVFSCTSIZ }, | |
5909 | { 0, CODE_FOR_spe_evfsctuf, "__builtin_spe_evfsctuf", SPE_BUILTIN_EVFSCTUF }, | |
5910 | { 0, CODE_FOR_spe_evfsctui, "__builtin_spe_evfsctui", SPE_BUILTIN_EVFSCTUI }, | |
5911 | { 0, CODE_FOR_spe_evfsctuiz, "__builtin_spe_evfsctuiz", SPE_BUILTIN_EVFSCTUIZ }, | |
5912 | { 0, CODE_FOR_spe_evfsnabs, "__builtin_spe_evfsnabs", SPE_BUILTIN_EVFSNABS }, | |
5913 | { 0, CODE_FOR_spe_evfsneg, "__builtin_spe_evfsneg", SPE_BUILTIN_EVFSNEG }, | |
5914 | { 0, CODE_FOR_spe_evmra, "__builtin_spe_evmra", SPE_BUILTIN_EVMRA }, | |
6a599451 | 5915 | { 0, CODE_FOR_negv2si2, "__builtin_spe_evneg", SPE_BUILTIN_EVNEG }, |
a3170dc6 AH |
5916 | { 0, CODE_FOR_spe_evrndw, "__builtin_spe_evrndw", SPE_BUILTIN_EVRNDW }, |
5917 | { 0, CODE_FOR_spe_evsubfsmiaaw, "__builtin_spe_evsubfsmiaaw", SPE_BUILTIN_EVSUBFSMIAAW }, | |
5918 | { 0, CODE_FOR_spe_evsubfssiaaw, "__builtin_spe_evsubfssiaaw", SPE_BUILTIN_EVSUBFSSIAAW }, | |
5919 | { 0, CODE_FOR_spe_evsubfumiaaw, "__builtin_spe_evsubfumiaaw", SPE_BUILTIN_EVSUBFUMIAAW }, | |
a3170dc6 AH |
5920 | |
5921 | /* Place-holder. Leave as last unary SPE builtin. */ | |
5922 | { 0, CODE_FOR_spe_evsubfusiaaw, "__builtin_spe_evsubfusiaaw", SPE_BUILTIN_EVSUBFUSIAAW }, | |
2212663f DB |
5923 | }; |
5924 | ||
5925 | static rtx | |
a2369ed3 | 5926 | rs6000_expand_unop_builtin (enum insn_code icode, tree arglist, rtx target) |
2212663f DB |
5927 | { |
5928 | rtx pat; | |
5929 | tree arg0 = TREE_VALUE (arglist); | |
5930 | rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
5931 | enum machine_mode tmode = insn_data[icode].operand[0].mode; | |
5932 | enum machine_mode mode0 = insn_data[icode].operand[1].mode; | |
5933 | ||
0559cc77 DE |
5934 | if (icode == CODE_FOR_nothing) |
5935 | /* Builtin not supported on this processor. */ | |
5936 | return 0; | |
5937 | ||
20e26713 AH |
5938 | /* If we got invalid arguments bail out before generating bad rtl. */ |
5939 | if (arg0 == error_mark_node) | |
9a171fcd | 5940 | return const0_rtx; |
20e26713 | 5941 | |
0559cc77 DE |
5942 | if (icode == CODE_FOR_altivec_vspltisb |
5943 | || icode == CODE_FOR_altivec_vspltish | |
5944 | || icode == CODE_FOR_altivec_vspltisw | |
5945 | || icode == CODE_FOR_spe_evsplatfi | |
5946 | || icode == CODE_FOR_spe_evsplati) | |
b44140e7 AH |
5947 | { |
5948 | /* Only allow 5-bit *signed* literals. */ | |
b44140e7 AH |
5949 | if (GET_CODE (op0) != CONST_INT |
5950 | || INTVAL (op0) > 0x1f | |
5951 | || INTVAL (op0) < -0x1f) | |
5952 | { | |
5953 | error ("argument 1 must be a 5-bit signed literal"); | |
9a171fcd | 5954 | return const0_rtx; |
b44140e7 | 5955 | } |
b44140e7 AH |
5956 | } |
5957 | ||
c62f2db5 | 5958 | if (target == 0 |
2212663f DB |
5959 | || GET_MODE (target) != tmode |
5960 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
5961 | target = gen_reg_rtx (tmode); | |
5962 | ||
5963 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) | |
5964 | op0 = copy_to_mode_reg (mode0, op0); | |
5965 | ||
5966 | pat = GEN_FCN (icode) (target, op0); | |
5967 | if (! pat) | |
5968 | return 0; | |
5969 | emit_insn (pat); | |
0ac081f6 | 5970 | |
2212663f DB |
5971 | return target; |
5972 | } | |
ae4b4a02 | 5973 | |
100c4561 | 5974 | static rtx |
a2369ed3 | 5975 | altivec_expand_abs_builtin (enum insn_code icode, tree arglist, rtx target) |
100c4561 AH |
5976 | { |
5977 | rtx pat, scratch1, scratch2; | |
5978 | tree arg0 = TREE_VALUE (arglist); | |
5979 | rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
5980 | enum machine_mode tmode = insn_data[icode].operand[0].mode; | |
5981 | enum machine_mode mode0 = insn_data[icode].operand[1].mode; | |
5982 | ||
5983 | /* If we have invalid arguments, bail out before generating bad rtl. */ | |
5984 | if (arg0 == error_mark_node) | |
9a171fcd | 5985 | return const0_rtx; |
100c4561 AH |
5986 | |
5987 | if (target == 0 | |
5988 | || GET_MODE (target) != tmode | |
5989 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
5990 | target = gen_reg_rtx (tmode); | |
5991 | ||
5992 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) | |
5993 | op0 = copy_to_mode_reg (mode0, op0); | |
5994 | ||
5995 | scratch1 = gen_reg_rtx (mode0); | |
5996 | scratch2 = gen_reg_rtx (mode0); | |
5997 | ||
5998 | pat = GEN_FCN (icode) (target, op0, scratch1, scratch2); | |
5999 | if (! pat) | |
6000 | return 0; | |
6001 | emit_insn (pat); | |
6002 | ||
6003 | return target; | |
6004 | } | |
6005 | ||
0ac081f6 | 6006 | static rtx |
a2369ed3 | 6007 | rs6000_expand_binop_builtin (enum insn_code icode, tree arglist, rtx target) |
0ac081f6 AH |
6008 | { |
6009 | rtx pat; | |
6010 | tree arg0 = TREE_VALUE (arglist); | |
6011 | tree arg1 = TREE_VALUE (TREE_CHAIN (arglist)); | |
6012 | rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
6013 | rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); | |
6014 | enum machine_mode tmode = insn_data[icode].operand[0].mode; | |
6015 | enum machine_mode mode0 = insn_data[icode].operand[1].mode; | |
6016 | enum machine_mode mode1 = insn_data[icode].operand[2].mode; | |
6017 | ||
0559cc77 DE |
6018 | if (icode == CODE_FOR_nothing) |
6019 | /* Builtin not supported on this processor. */ | |
6020 | return 0; | |
6021 | ||
20e26713 AH |
6022 | /* If we got invalid arguments bail out before generating bad rtl. */ |
6023 | if (arg0 == error_mark_node || arg1 == error_mark_node) | |
9a171fcd | 6024 | return const0_rtx; |
20e26713 | 6025 | |
0559cc77 DE |
6026 | if (icode == CODE_FOR_altivec_vcfux |
6027 | || icode == CODE_FOR_altivec_vcfsx | |
6028 | || icode == CODE_FOR_altivec_vctsxs | |
6029 | || icode == CODE_FOR_altivec_vctuxs | |
6030 | || icode == CODE_FOR_altivec_vspltb | |
6031 | || icode == CODE_FOR_altivec_vsplth | |
6032 | || icode == CODE_FOR_altivec_vspltw | |
6033 | || icode == CODE_FOR_spe_evaddiw | |
6034 | || icode == CODE_FOR_spe_evldd | |
6035 | || icode == CODE_FOR_spe_evldh | |
6036 | || icode == CODE_FOR_spe_evldw | |
6037 | || icode == CODE_FOR_spe_evlhhesplat | |
6038 | || icode == CODE_FOR_spe_evlhhossplat | |
6039 | || icode == CODE_FOR_spe_evlhhousplat | |
6040 | || icode == CODE_FOR_spe_evlwhe | |
6041 | || icode == CODE_FOR_spe_evlwhos | |
6042 | || icode == CODE_FOR_spe_evlwhou | |
6043 | || icode == CODE_FOR_spe_evlwhsplat | |
6044 | || icode == CODE_FOR_spe_evlwwsplat | |
6045 | || icode == CODE_FOR_spe_evrlwi | |
6046 | || icode == CODE_FOR_spe_evslwi | |
6047 | || icode == CODE_FOR_spe_evsrwis | |
f5119d10 | 6048 | || icode == CODE_FOR_spe_evsubifw |
0559cc77 | 6049 | || icode == CODE_FOR_spe_evsrwiu) |
b44140e7 AH |
6050 | { |
6051 | /* Only allow 5-bit unsigned literals. */ | |
8bb418a3 | 6052 | STRIP_NOPS (arg1); |
b44140e7 AH |
6053 | if (TREE_CODE (arg1) != INTEGER_CST |
6054 | || TREE_INT_CST_LOW (arg1) & ~0x1f) | |
6055 | { | |
6056 | error ("argument 2 must be a 5-bit unsigned literal"); | |
9a171fcd | 6057 | return const0_rtx; |
b44140e7 | 6058 | } |
b44140e7 AH |
6059 | } |
6060 | ||
c62f2db5 | 6061 | if (target == 0 |
0ac081f6 AH |
6062 | || GET_MODE (target) != tmode |
6063 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
6064 | target = gen_reg_rtx (tmode); | |
6065 | ||
6066 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) | |
6067 | op0 = copy_to_mode_reg (mode0, op0); | |
6068 | if (! (*insn_data[icode].operand[2].predicate) (op1, mode1)) | |
6069 | op1 = copy_to_mode_reg (mode1, op1); | |
6070 | ||
6071 | pat = GEN_FCN (icode) (target, op0, op1); | |
6072 | if (! pat) | |
6073 | return 0; | |
6074 | emit_insn (pat); | |
6075 | ||
6076 | return target; | |
6077 | } | |
6525c0e7 | 6078 | |
ae4b4a02 | 6079 | static rtx |
f676971a | 6080 | altivec_expand_predicate_builtin (enum insn_code icode, const char *opcode, |
a2369ed3 | 6081 | tree arglist, rtx target) |
ae4b4a02 AH |
6082 | { |
6083 | rtx pat, scratch; | |
6084 | tree cr6_form = TREE_VALUE (arglist); | |
6085 | tree arg0 = TREE_VALUE (TREE_CHAIN (arglist)); | |
6086 | tree arg1 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist))); | |
6087 | rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
6088 | rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); | |
6089 | enum machine_mode tmode = SImode; | |
6090 | enum machine_mode mode0 = insn_data[icode].operand[1].mode; | |
6091 | enum machine_mode mode1 = insn_data[icode].operand[2].mode; | |
6092 | int cr6_form_int; | |
6093 | ||
6094 | if (TREE_CODE (cr6_form) != INTEGER_CST) | |
6095 | { | |
6096 | error ("argument 1 of __builtin_altivec_predicate must be a constant"); | |
9a171fcd | 6097 | return const0_rtx; |
ae4b4a02 AH |
6098 | } |
6099 | else | |
6100 | cr6_form_int = TREE_INT_CST_LOW (cr6_form); | |
6101 | ||
37409796 | 6102 | gcc_assert (mode0 == mode1); |
ae4b4a02 AH |
6103 | |
6104 | /* If we have invalid arguments, bail out before generating bad rtl. */ | |
6105 | if (arg0 == error_mark_node || arg1 == error_mark_node) | |
9a171fcd | 6106 | return const0_rtx; |
ae4b4a02 AH |
6107 | |
6108 | if (target == 0 | |
6109 | || GET_MODE (target) != tmode | |
6110 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
6111 | target = gen_reg_rtx (tmode); | |
6112 | ||
6113 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) | |
6114 | op0 = copy_to_mode_reg (mode0, op0); | |
6115 | if (! (*insn_data[icode].operand[2].predicate) (op1, mode1)) | |
6116 | op1 = copy_to_mode_reg (mode1, op1); | |
6117 | ||
6118 | scratch = gen_reg_rtx (mode0); | |
6119 | ||
6120 | pat = GEN_FCN (icode) (scratch, op0, op1, | |
f1c25d3b | 6121 | gen_rtx_SYMBOL_REF (Pmode, opcode)); |
ae4b4a02 AH |
6122 | if (! pat) |
6123 | return 0; | |
6124 | emit_insn (pat); | |
6125 | ||
6126 | /* The vec_any* and vec_all* predicates use the same opcodes for two | |
6127 | different operations, but the bits in CR6 will be different | |
6128 | depending on what information we want. So we have to play tricks | |
6129 | with CR6 to get the right bits out. | |
6130 | ||
6131 | If you think this is disgusting, look at the specs for the | |
6132 | AltiVec predicates. */ | |
6133 | ||
c4ad648e AM |
6134 | switch (cr6_form_int) |
6135 | { | |
6136 | case 0: | |
6137 | emit_insn (gen_cr6_test_for_zero (target)); | |
6138 | break; | |
6139 | case 1: | |
6140 | emit_insn (gen_cr6_test_for_zero_reverse (target)); | |
6141 | break; | |
6142 | case 2: | |
6143 | emit_insn (gen_cr6_test_for_lt (target)); | |
6144 | break; | |
6145 | case 3: | |
6146 | emit_insn (gen_cr6_test_for_lt_reverse (target)); | |
6147 | break; | |
6148 | default: | |
6149 | error ("argument 1 of __builtin_altivec_predicate is out of range"); | |
6150 | break; | |
6151 | } | |
ae4b4a02 AH |
6152 | |
6153 | return target; | |
6154 | } | |
6155 | ||
b4a62fa0 | 6156 | static rtx |
38f391a5 | 6157 | altivec_expand_lv_builtin (enum insn_code icode, tree arglist, rtx target) |
b4a62fa0 SB |
6158 | { |
6159 | rtx pat, addr; | |
6160 | tree arg0 = TREE_VALUE (arglist); | |
6161 | tree arg1 = TREE_VALUE (TREE_CHAIN (arglist)); | |
6162 | enum machine_mode tmode = insn_data[icode].operand[0].mode; | |
6163 | enum machine_mode mode0 = Pmode; | |
6164 | enum machine_mode mode1 = Pmode; | |
6165 | rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
6166 | rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); | |
6167 | ||
6168 | if (icode == CODE_FOR_nothing) | |
6169 | /* Builtin not supported on this processor. */ | |
6170 | return 0; | |
6171 | ||
6172 | /* If we got invalid arguments bail out before generating bad rtl. */ | |
6173 | if (arg0 == error_mark_node || arg1 == error_mark_node) | |
6174 | return const0_rtx; | |
6175 | ||
6176 | if (target == 0 | |
6177 | || GET_MODE (target) != tmode | |
6178 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
6179 | target = gen_reg_rtx (tmode); | |
6180 | ||
f676971a | 6181 | op1 = copy_to_mode_reg (mode1, op1); |
b4a62fa0 SB |
6182 | |
6183 | if (op0 == const0_rtx) | |
6184 | { | |
6185 | addr = gen_rtx_MEM (tmode, op1); | |
6186 | } | |
6187 | else | |
6188 | { | |
6189 | op0 = copy_to_mode_reg (mode0, op0); | |
6190 | addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op0, op1)); | |
6191 | } | |
6192 | ||
6193 | pat = GEN_FCN (icode) (target, addr); | |
6194 | ||
6195 | if (! pat) | |
6196 | return 0; | |
6197 | emit_insn (pat); | |
6198 | ||
6199 | return target; | |
6200 | } | |
6201 | ||
61bea3b0 AH |
6202 | static rtx |
6203 | spe_expand_stv_builtin (enum insn_code icode, tree arglist) | |
6204 | { | |
6205 | tree arg0 = TREE_VALUE (arglist); | |
6206 | tree arg1 = TREE_VALUE (TREE_CHAIN (arglist)); | |
6207 | tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist))); | |
6208 | rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
6209 | rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); | |
6210 | rtx op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0); | |
6211 | rtx pat; | |
6212 | enum machine_mode mode0 = insn_data[icode].operand[0].mode; | |
6213 | enum machine_mode mode1 = insn_data[icode].operand[1].mode; | |
6214 | enum machine_mode mode2 = insn_data[icode].operand[2].mode; | |
6215 | ||
6216 | /* Invalid arguments. Bail before doing anything stoopid! */ | |
6217 | if (arg0 == error_mark_node | |
6218 | || arg1 == error_mark_node | |
6219 | || arg2 == error_mark_node) | |
6220 | return const0_rtx; | |
6221 | ||
6222 | if (! (*insn_data[icode].operand[2].predicate) (op0, mode2)) | |
6223 | op0 = copy_to_mode_reg (mode2, op0); | |
6224 | if (! (*insn_data[icode].operand[0].predicate) (op1, mode0)) | |
6225 | op1 = copy_to_mode_reg (mode0, op1); | |
6226 | if (! (*insn_data[icode].operand[1].predicate) (op2, mode1)) | |
6227 | op2 = copy_to_mode_reg (mode1, op2); | |
6228 | ||
6229 | pat = GEN_FCN (icode) (op1, op2, op0); | |
6230 | if (pat) | |
6231 | emit_insn (pat); | |
6232 | return NULL_RTX; | |
6233 | } | |
6234 | ||
6525c0e7 | 6235 | static rtx |
a2369ed3 | 6236 | altivec_expand_stv_builtin (enum insn_code icode, tree arglist) |
6525c0e7 AH |
6237 | { |
6238 | tree arg0 = TREE_VALUE (arglist); | |
6239 | tree arg1 = TREE_VALUE (TREE_CHAIN (arglist)); | |
6240 | tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist))); | |
6241 | rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
6242 | rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); | |
6243 | rtx op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0); | |
b4a62fa0 SB |
6244 | rtx pat, addr; |
6245 | enum machine_mode tmode = insn_data[icode].operand[0].mode; | |
6246 | enum machine_mode mode1 = Pmode; | |
6247 | enum machine_mode mode2 = Pmode; | |
6525c0e7 AH |
6248 | |
6249 | /* Invalid arguments. Bail before doing anything stoopid! */ | |
6250 | if (arg0 == error_mark_node | |
6251 | || arg1 == error_mark_node | |
6252 | || arg2 == error_mark_node) | |
9a171fcd | 6253 | return const0_rtx; |
6525c0e7 | 6254 | |
b4a62fa0 SB |
6255 | if (! (*insn_data[icode].operand[1].predicate) (op0, tmode)) |
6256 | op0 = copy_to_mode_reg (tmode, op0); | |
6257 | ||
f676971a | 6258 | op2 = copy_to_mode_reg (mode2, op2); |
b4a62fa0 SB |
6259 | |
6260 | if (op1 == const0_rtx) | |
6261 | { | |
6262 | addr = gen_rtx_MEM (tmode, op2); | |
6263 | } | |
6264 | else | |
6265 | { | |
6266 | op1 = copy_to_mode_reg (mode1, op1); | |
6267 | addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op1, op2)); | |
6268 | } | |
6525c0e7 | 6269 | |
b4a62fa0 | 6270 | pat = GEN_FCN (icode) (addr, op0); |
6525c0e7 AH |
6271 | if (pat) |
6272 | emit_insn (pat); | |
6273 | return NULL_RTX; | |
6274 | } | |
6275 | ||
2212663f | 6276 | static rtx |
a2369ed3 | 6277 | rs6000_expand_ternop_builtin (enum insn_code icode, tree arglist, rtx target) |
2212663f DB |
6278 | { |
6279 | rtx pat; | |
6280 | tree arg0 = TREE_VALUE (arglist); | |
6281 | tree arg1 = TREE_VALUE (TREE_CHAIN (arglist)); | |
6282 | tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist))); | |
6283 | rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
6284 | rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); | |
6285 | rtx op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0); | |
6286 | enum machine_mode tmode = insn_data[icode].operand[0].mode; | |
6287 | enum machine_mode mode0 = insn_data[icode].operand[1].mode; | |
6288 | enum machine_mode mode1 = insn_data[icode].operand[2].mode; | |
6289 | enum machine_mode mode2 = insn_data[icode].operand[3].mode; | |
0ac081f6 | 6290 | |
774b5662 DE |
6291 | if (icode == CODE_FOR_nothing) |
6292 | /* Builtin not supported on this processor. */ | |
6293 | return 0; | |
6294 | ||
20e26713 AH |
6295 | /* If we got invalid arguments bail out before generating bad rtl. */ |
6296 | if (arg0 == error_mark_node | |
6297 | || arg1 == error_mark_node | |
6298 | || arg2 == error_mark_node) | |
9a171fcd | 6299 | return const0_rtx; |
20e26713 | 6300 | |
aba5fb01 NS |
6301 | if (icode == CODE_FOR_altivec_vsldoi_v4sf |
6302 | || icode == CODE_FOR_altivec_vsldoi_v4si | |
6303 | || icode == CODE_FOR_altivec_vsldoi_v8hi | |
6304 | || icode == CODE_FOR_altivec_vsldoi_v16qi) | |
b44140e7 AH |
6305 | { |
6306 | /* Only allow 4-bit unsigned literals. */ | |
8bb418a3 | 6307 | STRIP_NOPS (arg2); |
b44140e7 AH |
6308 | if (TREE_CODE (arg2) != INTEGER_CST |
6309 | || TREE_INT_CST_LOW (arg2) & ~0xf) | |
6310 | { | |
6311 | error ("argument 3 must be a 4-bit unsigned literal"); | |
e3277ffb | 6312 | return const0_rtx; |
b44140e7 | 6313 | } |
b44140e7 AH |
6314 | } |
6315 | ||
c62f2db5 | 6316 | if (target == 0 |
2212663f DB |
6317 | || GET_MODE (target) != tmode |
6318 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
6319 | target = gen_reg_rtx (tmode); | |
6320 | ||
6321 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) | |
6322 | op0 = copy_to_mode_reg (mode0, op0); | |
6323 | if (! (*insn_data[icode].operand[2].predicate) (op1, mode1)) | |
6324 | op1 = copy_to_mode_reg (mode1, op1); | |
6325 | if (! (*insn_data[icode].operand[3].predicate) (op2, mode2)) | |
6326 | op2 = copy_to_mode_reg (mode2, op2); | |
6327 | ||
6328 | pat = GEN_FCN (icode) (target, op0, op1, op2); | |
6329 | if (! pat) | |
6330 | return 0; | |
6331 | emit_insn (pat); | |
6332 | ||
6333 | return target; | |
6334 | } | |
92898235 | 6335 | |
3a9b8c7e | 6336 | /* Expand the lvx builtins. */ |
0ac081f6 | 6337 | static rtx |
a2369ed3 | 6338 | altivec_expand_ld_builtin (tree exp, rtx target, bool *expandedp) |
0ac081f6 | 6339 | { |
0ac081f6 AH |
6340 | tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0); |
6341 | tree arglist = TREE_OPERAND (exp, 1); | |
0ac081f6 | 6342 | unsigned int fcode = DECL_FUNCTION_CODE (fndecl); |
3a9b8c7e AH |
6343 | tree arg0; |
6344 | enum machine_mode tmode, mode0; | |
7c3abc73 | 6345 | rtx pat, op0; |
3a9b8c7e | 6346 | enum insn_code icode; |
92898235 | 6347 | |
0ac081f6 AH |
6348 | switch (fcode) |
6349 | { | |
f18c054f | 6350 | case ALTIVEC_BUILTIN_LD_INTERNAL_16qi: |
81466555 | 6351 | icode = CODE_FOR_altivec_lvx_v16qi; |
3a9b8c7e | 6352 | break; |
f18c054f | 6353 | case ALTIVEC_BUILTIN_LD_INTERNAL_8hi: |
81466555 | 6354 | icode = CODE_FOR_altivec_lvx_v8hi; |
3a9b8c7e AH |
6355 | break; |
6356 | case ALTIVEC_BUILTIN_LD_INTERNAL_4si: | |
81466555 | 6357 | icode = CODE_FOR_altivec_lvx_v4si; |
3a9b8c7e AH |
6358 | break; |
6359 | case ALTIVEC_BUILTIN_LD_INTERNAL_4sf: | |
81466555 | 6360 | icode = CODE_FOR_altivec_lvx_v4sf; |
3a9b8c7e AH |
6361 | break; |
6362 | default: | |
6363 | *expandedp = false; | |
6364 | return NULL_RTX; | |
6365 | } | |
0ac081f6 | 6366 | |
3a9b8c7e | 6367 | *expandedp = true; |
f18c054f | 6368 | |
3a9b8c7e AH |
6369 | arg0 = TREE_VALUE (arglist); |
6370 | op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
6371 | tmode = insn_data[icode].operand[0].mode; | |
6372 | mode0 = insn_data[icode].operand[1].mode; | |
f18c054f | 6373 | |
3a9b8c7e AH |
6374 | if (target == 0 |
6375 | || GET_MODE (target) != tmode | |
6376 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
6377 | target = gen_reg_rtx (tmode); | |
24408032 | 6378 | |
3a9b8c7e AH |
6379 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) |
6380 | op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0)); | |
f18c054f | 6381 | |
3a9b8c7e AH |
6382 | pat = GEN_FCN (icode) (target, op0); |
6383 | if (! pat) | |
6384 | return 0; | |
6385 | emit_insn (pat); | |
6386 | return target; | |
6387 | } | |
f18c054f | 6388 | |
3a9b8c7e AH |
6389 | /* Expand the stvx builtins. */ |
6390 | static rtx | |
f676971a | 6391 | altivec_expand_st_builtin (tree exp, rtx target ATTRIBUTE_UNUSED, |
a2369ed3 | 6392 | bool *expandedp) |
3a9b8c7e AH |
6393 | { |
6394 | tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0); | |
6395 | tree arglist = TREE_OPERAND (exp, 1); | |
6396 | unsigned int fcode = DECL_FUNCTION_CODE (fndecl); | |
6397 | tree arg0, arg1; | |
6398 | enum machine_mode mode0, mode1; | |
7c3abc73 | 6399 | rtx pat, op0, op1; |
3a9b8c7e | 6400 | enum insn_code icode; |
f18c054f | 6401 | |
3a9b8c7e AH |
6402 | switch (fcode) |
6403 | { | |
6404 | case ALTIVEC_BUILTIN_ST_INTERNAL_16qi: | |
81466555 | 6405 | icode = CODE_FOR_altivec_stvx_v16qi; |
3a9b8c7e AH |
6406 | break; |
6407 | case ALTIVEC_BUILTIN_ST_INTERNAL_8hi: | |
81466555 | 6408 | icode = CODE_FOR_altivec_stvx_v8hi; |
3a9b8c7e AH |
6409 | break; |
6410 | case ALTIVEC_BUILTIN_ST_INTERNAL_4si: | |
81466555 | 6411 | icode = CODE_FOR_altivec_stvx_v4si; |
3a9b8c7e AH |
6412 | break; |
6413 | case ALTIVEC_BUILTIN_ST_INTERNAL_4sf: | |
81466555 | 6414 | icode = CODE_FOR_altivec_stvx_v4sf; |
3a9b8c7e AH |
6415 | break; |
6416 | default: | |
6417 | *expandedp = false; | |
6418 | return NULL_RTX; | |
6419 | } | |
24408032 | 6420 | |
3a9b8c7e AH |
6421 | arg0 = TREE_VALUE (arglist); |
6422 | arg1 = TREE_VALUE (TREE_CHAIN (arglist)); | |
6423 | op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
6424 | op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); | |
6425 | mode0 = insn_data[icode].operand[0].mode; | |
6426 | mode1 = insn_data[icode].operand[1].mode; | |
f18c054f | 6427 | |
3a9b8c7e AH |
6428 | if (! (*insn_data[icode].operand[0].predicate) (op0, mode0)) |
6429 | op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0)); | |
6430 | if (! (*insn_data[icode].operand[1].predicate) (op1, mode1)) | |
6431 | op1 = copy_to_mode_reg (mode1, op1); | |
f18c054f | 6432 | |
3a9b8c7e AH |
6433 | pat = GEN_FCN (icode) (op0, op1); |
6434 | if (pat) | |
6435 | emit_insn (pat); | |
f18c054f | 6436 | |
3a9b8c7e AH |
6437 | *expandedp = true; |
6438 | return NULL_RTX; | |
6439 | } | |
f18c054f | 6440 | |
3a9b8c7e AH |
6441 | /* Expand the dst builtins. */ |
6442 | static rtx | |
f676971a | 6443 | altivec_expand_dst_builtin (tree exp, rtx target ATTRIBUTE_UNUSED, |
a2369ed3 | 6444 | bool *expandedp) |
3a9b8c7e AH |
6445 | { |
6446 | tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0); | |
6447 | tree arglist = TREE_OPERAND (exp, 1); | |
6448 | unsigned int fcode = DECL_FUNCTION_CODE (fndecl); | |
6449 | tree arg0, arg1, arg2; | |
6450 | enum machine_mode mode0, mode1, mode2; | |
7c3abc73 | 6451 | rtx pat, op0, op1, op2; |
3a9b8c7e | 6452 | struct builtin_description *d; |
a3170dc6 | 6453 | size_t i; |
f18c054f | 6454 | |
3a9b8c7e | 6455 | *expandedp = false; |
f18c054f | 6456 | |
3a9b8c7e AH |
6457 | /* Handle DST variants. */ |
6458 | d = (struct builtin_description *) bdesc_dst; | |
6459 | for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++) | |
6460 | if (d->code == fcode) | |
6461 | { | |
6462 | arg0 = TREE_VALUE (arglist); | |
6463 | arg1 = TREE_VALUE (TREE_CHAIN (arglist)); | |
6464 | arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist))); | |
6465 | op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
6466 | op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); | |
6467 | op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0); | |
6468 | mode0 = insn_data[d->icode].operand[0].mode; | |
6469 | mode1 = insn_data[d->icode].operand[1].mode; | |
6470 | mode2 = insn_data[d->icode].operand[2].mode; | |
24408032 | 6471 | |
3a9b8c7e AH |
6472 | /* Invalid arguments, bail out before generating bad rtl. */ |
6473 | if (arg0 == error_mark_node | |
6474 | || arg1 == error_mark_node | |
6475 | || arg2 == error_mark_node) | |
6476 | return const0_rtx; | |
f18c054f | 6477 | |
86e7df90 | 6478 | *expandedp = true; |
8bb418a3 | 6479 | STRIP_NOPS (arg2); |
3a9b8c7e AH |
6480 | if (TREE_CODE (arg2) != INTEGER_CST |
6481 | || TREE_INT_CST_LOW (arg2) & ~0x3) | |
6482 | { | |
9e637a26 | 6483 | error ("argument to %qs must be a 2-bit unsigned literal", d->name); |
3a9b8c7e AH |
6484 | return const0_rtx; |
6485 | } | |
f18c054f | 6486 | |
3a9b8c7e | 6487 | if (! (*insn_data[d->icode].operand[0].predicate) (op0, mode0)) |
666158b9 | 6488 | op0 = copy_to_mode_reg (Pmode, op0); |
3a9b8c7e AH |
6489 | if (! (*insn_data[d->icode].operand[1].predicate) (op1, mode1)) |
6490 | op1 = copy_to_mode_reg (mode1, op1); | |
24408032 | 6491 | |
3a9b8c7e AH |
6492 | pat = GEN_FCN (d->icode) (op0, op1, op2); |
6493 | if (pat != 0) | |
6494 | emit_insn (pat); | |
f18c054f | 6495 | |
3a9b8c7e AH |
6496 | return NULL_RTX; |
6497 | } | |
f18c054f | 6498 | |
3a9b8c7e AH |
6499 | return NULL_RTX; |
6500 | } | |
24408032 | 6501 | |
3a9b8c7e AH |
6502 | /* Expand the builtin in EXP and store the result in TARGET. Store |
6503 | true in *EXPANDEDP if we found a builtin to expand. */ | |
6504 | static rtx | |
a2369ed3 | 6505 | altivec_expand_builtin (tree exp, rtx target, bool *expandedp) |
3a9b8c7e AH |
6506 | { |
6507 | struct builtin_description *d; | |
6508 | struct builtin_description_predicates *dp; | |
6509 | size_t i; | |
6510 | enum insn_code icode; | |
6511 | tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0); | |
6512 | tree arglist = TREE_OPERAND (exp, 1); | |
7c3abc73 AH |
6513 | tree arg0; |
6514 | rtx op0, pat; | |
6515 | enum machine_mode tmode, mode0; | |
3a9b8c7e | 6516 | unsigned int fcode = DECL_FUNCTION_CODE (fndecl); |
0ac081f6 | 6517 | |
3a9b8c7e AH |
6518 | target = altivec_expand_ld_builtin (exp, target, expandedp); |
6519 | if (*expandedp) | |
6520 | return target; | |
0ac081f6 | 6521 | |
3a9b8c7e AH |
6522 | target = altivec_expand_st_builtin (exp, target, expandedp); |
6523 | if (*expandedp) | |
6524 | return target; | |
6525 | ||
6526 | target = altivec_expand_dst_builtin (exp, target, expandedp); | |
6527 | if (*expandedp) | |
6528 | return target; | |
6529 | ||
6530 | *expandedp = true; | |
95385cbb | 6531 | |
3a9b8c7e AH |
6532 | switch (fcode) |
6533 | { | |
6525c0e7 AH |
6534 | case ALTIVEC_BUILTIN_STVX: |
6535 | return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx, arglist); | |
6536 | case ALTIVEC_BUILTIN_STVEBX: | |
6537 | return altivec_expand_stv_builtin (CODE_FOR_altivec_stvebx, arglist); | |
6538 | case ALTIVEC_BUILTIN_STVEHX: | |
6539 | return altivec_expand_stv_builtin (CODE_FOR_altivec_stvehx, arglist); | |
6540 | case ALTIVEC_BUILTIN_STVEWX: | |
6541 | return altivec_expand_stv_builtin (CODE_FOR_altivec_stvewx, arglist); | |
6542 | case ALTIVEC_BUILTIN_STVXL: | |
6543 | return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl, arglist); | |
3a9b8c7e | 6544 | |
95385cbb AH |
6545 | case ALTIVEC_BUILTIN_MFVSCR: |
6546 | icode = CODE_FOR_altivec_mfvscr; | |
6547 | tmode = insn_data[icode].operand[0].mode; | |
6548 | ||
6549 | if (target == 0 | |
6550 | || GET_MODE (target) != tmode | |
6551 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
6552 | target = gen_reg_rtx (tmode); | |
f676971a | 6553 | |
95385cbb | 6554 | pat = GEN_FCN (icode) (target); |
0ac081f6 AH |
6555 | if (! pat) |
6556 | return 0; | |
6557 | emit_insn (pat); | |
95385cbb AH |
6558 | return target; |
6559 | ||
6560 | case ALTIVEC_BUILTIN_MTVSCR: | |
6561 | icode = CODE_FOR_altivec_mtvscr; | |
6562 | arg0 = TREE_VALUE (arglist); | |
6563 | op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
6564 | mode0 = insn_data[icode].operand[0].mode; | |
6565 | ||
6566 | /* If we got invalid arguments bail out before generating bad rtl. */ | |
6567 | if (arg0 == error_mark_node) | |
9a171fcd | 6568 | return const0_rtx; |
95385cbb AH |
6569 | |
6570 | if (! (*insn_data[icode].operand[0].predicate) (op0, mode0)) | |
6571 | op0 = copy_to_mode_reg (mode0, op0); | |
6572 | ||
6573 | pat = GEN_FCN (icode) (op0); | |
6574 | if (pat) | |
6575 | emit_insn (pat); | |
6576 | return NULL_RTX; | |
3a9b8c7e | 6577 | |
95385cbb AH |
6578 | case ALTIVEC_BUILTIN_DSSALL: |
6579 | emit_insn (gen_altivec_dssall ()); | |
6580 | return NULL_RTX; | |
6581 | ||
6582 | case ALTIVEC_BUILTIN_DSS: | |
6583 | icode = CODE_FOR_altivec_dss; | |
6584 | arg0 = TREE_VALUE (arglist); | |
8bb418a3 | 6585 | STRIP_NOPS (arg0); |
95385cbb AH |
6586 | op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); |
6587 | mode0 = insn_data[icode].operand[0].mode; | |
6588 | ||
6589 | /* If we got invalid arguments bail out before generating bad rtl. */ | |
6590 | if (arg0 == error_mark_node) | |
9a171fcd | 6591 | return const0_rtx; |
95385cbb | 6592 | |
b44140e7 AH |
6593 | if (TREE_CODE (arg0) != INTEGER_CST |
6594 | || TREE_INT_CST_LOW (arg0) & ~0x3) | |
6595 | { | |
6596 | error ("argument to dss must be a 2-bit unsigned literal"); | |
9a171fcd | 6597 | return const0_rtx; |
b44140e7 AH |
6598 | } |
6599 | ||
95385cbb AH |
6600 | if (! (*insn_data[icode].operand[0].predicate) (op0, mode0)) |
6601 | op0 = copy_to_mode_reg (mode0, op0); | |
6602 | ||
6603 | emit_insn (gen_altivec_dss (op0)); | |
0ac081f6 | 6604 | return NULL_RTX; |
f676971a | 6605 | |
8bb418a3 ZL |
6606 | case ALTIVEC_BUILTIN_COMPILETIME_ERROR: |
6607 | arg0 = TREE_VALUE (arglist); | |
97dc04b3 | 6608 | while (TREE_CODE (arg0) == NOP_EXPR || TREE_CODE (arg0) == ADDR_EXPR |
c4ad648e | 6609 | || TREE_CODE (arg0) == ARRAY_REF) |
8bb418a3 | 6610 | arg0 = TREE_OPERAND (arg0, 0); |
9e637a26 | 6611 | error ("invalid parameter combination for %qs AltiVec intrinsic", |
8bb418a3 ZL |
6612 | TREE_STRING_POINTER (arg0)); |
6613 | ||
6614 | return const0_rtx; | |
0ac081f6 | 6615 | } |
24408032 | 6616 | |
100c4561 AH |
6617 | /* Expand abs* operations. */ |
6618 | d = (struct builtin_description *) bdesc_abs; | |
ca7558fc | 6619 | for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++) |
100c4561 AH |
6620 | if (d->code == fcode) |
6621 | return altivec_expand_abs_builtin (d->icode, arglist, target); | |
6622 | ||
ae4b4a02 AH |
6623 | /* Expand the AltiVec predicates. */ |
6624 | dp = (struct builtin_description_predicates *) bdesc_altivec_preds; | |
ca7558fc | 6625 | for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, dp++) |
ae4b4a02 | 6626 | if (dp->code == fcode) |
c4ad648e AM |
6627 | return altivec_expand_predicate_builtin (dp->icode, dp->opcode, |
6628 | arglist, target); | |
ae4b4a02 | 6629 | |
6525c0e7 AH |
6630 | /* LV* are funky. We initialized them differently. */ |
6631 | switch (fcode) | |
6632 | { | |
6633 | case ALTIVEC_BUILTIN_LVSL: | |
b4a62fa0 | 6634 | return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsl, |
c4ad648e | 6635 | arglist, target); |
6525c0e7 | 6636 | case ALTIVEC_BUILTIN_LVSR: |
b4a62fa0 | 6637 | return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsr, |
c4ad648e | 6638 | arglist, target); |
6525c0e7 | 6639 | case ALTIVEC_BUILTIN_LVEBX: |
b4a62fa0 | 6640 | return altivec_expand_lv_builtin (CODE_FOR_altivec_lvebx, |
c4ad648e | 6641 | arglist, target); |
6525c0e7 | 6642 | case ALTIVEC_BUILTIN_LVEHX: |
b4a62fa0 | 6643 | return altivec_expand_lv_builtin (CODE_FOR_altivec_lvehx, |
c4ad648e | 6644 | arglist, target); |
6525c0e7 | 6645 | case ALTIVEC_BUILTIN_LVEWX: |
b4a62fa0 | 6646 | return altivec_expand_lv_builtin (CODE_FOR_altivec_lvewx, |
c4ad648e | 6647 | arglist, target); |
6525c0e7 | 6648 | case ALTIVEC_BUILTIN_LVXL: |
b4a62fa0 | 6649 | return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl, |
c4ad648e | 6650 | arglist, target); |
6525c0e7 | 6651 | case ALTIVEC_BUILTIN_LVX: |
b4a62fa0 | 6652 | return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx, |
c4ad648e | 6653 | arglist, target); |
6525c0e7 AH |
6654 | default: |
6655 | break; | |
6656 | /* Fall through. */ | |
6657 | } | |
95385cbb | 6658 | |
92898235 | 6659 | *expandedp = false; |
0ac081f6 AH |
6660 | return NULL_RTX; |
6661 | } | |
6662 | ||
a3170dc6 AH |
6663 | /* Binops that need to be initialized manually, but can be expanded |
6664 | automagically by rs6000_expand_binop_builtin. */ | |
6665 | static struct builtin_description bdesc_2arg_spe[] = | |
6666 | { | |
6667 | { 0, CODE_FOR_spe_evlddx, "__builtin_spe_evlddx", SPE_BUILTIN_EVLDDX }, | |
6668 | { 0, CODE_FOR_spe_evldwx, "__builtin_spe_evldwx", SPE_BUILTIN_EVLDWX }, | |
6669 | { 0, CODE_FOR_spe_evldhx, "__builtin_spe_evldhx", SPE_BUILTIN_EVLDHX }, | |
6670 | { 0, CODE_FOR_spe_evlwhex, "__builtin_spe_evlwhex", SPE_BUILTIN_EVLWHEX }, | |
6671 | { 0, CODE_FOR_spe_evlwhoux, "__builtin_spe_evlwhoux", SPE_BUILTIN_EVLWHOUX }, | |
6672 | { 0, CODE_FOR_spe_evlwhosx, "__builtin_spe_evlwhosx", SPE_BUILTIN_EVLWHOSX }, | |
6673 | { 0, CODE_FOR_spe_evlwwsplatx, "__builtin_spe_evlwwsplatx", SPE_BUILTIN_EVLWWSPLATX }, | |
6674 | { 0, CODE_FOR_spe_evlwhsplatx, "__builtin_spe_evlwhsplatx", SPE_BUILTIN_EVLWHSPLATX }, | |
6675 | { 0, CODE_FOR_spe_evlhhesplatx, "__builtin_spe_evlhhesplatx", SPE_BUILTIN_EVLHHESPLATX }, | |
6676 | { 0, CODE_FOR_spe_evlhhousplatx, "__builtin_spe_evlhhousplatx", SPE_BUILTIN_EVLHHOUSPLATX }, | |
6677 | { 0, CODE_FOR_spe_evlhhossplatx, "__builtin_spe_evlhhossplatx", SPE_BUILTIN_EVLHHOSSPLATX }, | |
6678 | { 0, CODE_FOR_spe_evldd, "__builtin_spe_evldd", SPE_BUILTIN_EVLDD }, | |
6679 | { 0, CODE_FOR_spe_evldw, "__builtin_spe_evldw", SPE_BUILTIN_EVLDW }, | |
6680 | { 0, CODE_FOR_spe_evldh, "__builtin_spe_evldh", SPE_BUILTIN_EVLDH }, | |
6681 | { 0, CODE_FOR_spe_evlwhe, "__builtin_spe_evlwhe", SPE_BUILTIN_EVLWHE }, | |
6682 | { 0, CODE_FOR_spe_evlwhou, "__builtin_spe_evlwhou", SPE_BUILTIN_EVLWHOU }, | |
6683 | { 0, CODE_FOR_spe_evlwhos, "__builtin_spe_evlwhos", SPE_BUILTIN_EVLWHOS }, | |
6684 | { 0, CODE_FOR_spe_evlwwsplat, "__builtin_spe_evlwwsplat", SPE_BUILTIN_EVLWWSPLAT }, | |
6685 | { 0, CODE_FOR_spe_evlwhsplat, "__builtin_spe_evlwhsplat", SPE_BUILTIN_EVLWHSPLAT }, | |
6686 | { 0, CODE_FOR_spe_evlhhesplat, "__builtin_spe_evlhhesplat", SPE_BUILTIN_EVLHHESPLAT }, | |
6687 | { 0, CODE_FOR_spe_evlhhousplat, "__builtin_spe_evlhhousplat", SPE_BUILTIN_EVLHHOUSPLAT }, | |
6688 | { 0, CODE_FOR_spe_evlhhossplat, "__builtin_spe_evlhhossplat", SPE_BUILTIN_EVLHHOSSPLAT } | |
6689 | }; | |
6690 | ||
6691 | /* Expand the builtin in EXP and store the result in TARGET. Store | |
6692 | true in *EXPANDEDP if we found a builtin to expand. | |
6693 | ||
6694 | This expands the SPE builtins that are not simple unary and binary | |
6695 | operations. */ | |
6696 | static rtx | |
a2369ed3 | 6697 | spe_expand_builtin (tree exp, rtx target, bool *expandedp) |
a3170dc6 AH |
6698 | { |
6699 | tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0); | |
6700 | tree arglist = TREE_OPERAND (exp, 1); | |
6701 | tree arg1, arg0; | |
6702 | unsigned int fcode = DECL_FUNCTION_CODE (fndecl); | |
6703 | enum insn_code icode; | |
6704 | enum machine_mode tmode, mode0; | |
6705 | rtx pat, op0; | |
6706 | struct builtin_description *d; | |
6707 | size_t i; | |
6708 | ||
6709 | *expandedp = true; | |
6710 | ||
6711 | /* Syntax check for a 5-bit unsigned immediate. */ | |
6712 | switch (fcode) | |
6713 | { | |
6714 | case SPE_BUILTIN_EVSTDD: | |
6715 | case SPE_BUILTIN_EVSTDH: | |
6716 | case SPE_BUILTIN_EVSTDW: | |
6717 | case SPE_BUILTIN_EVSTWHE: | |
6718 | case SPE_BUILTIN_EVSTWHO: | |
6719 | case SPE_BUILTIN_EVSTWWE: | |
6720 | case SPE_BUILTIN_EVSTWWO: | |
6721 | arg1 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist))); | |
6722 | if (TREE_CODE (arg1) != INTEGER_CST | |
6723 | || TREE_INT_CST_LOW (arg1) & ~0x1f) | |
6724 | { | |
6725 | error ("argument 2 must be a 5-bit unsigned literal"); | |
6726 | return const0_rtx; | |
6727 | } | |
6728 | break; | |
6729 | default: | |
6730 | break; | |
6731 | } | |
6732 | ||
00332c9f AH |
6733 | /* The evsplat*i instructions are not quite generic. */ |
6734 | switch (fcode) | |
6735 | { | |
6736 | case SPE_BUILTIN_EVSPLATFI: | |
6737 | return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplatfi, | |
6738 | arglist, target); | |
6739 | case SPE_BUILTIN_EVSPLATI: | |
6740 | return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplati, | |
6741 | arglist, target); | |
6742 | default: | |
6743 | break; | |
6744 | } | |
6745 | ||
a3170dc6 AH |
6746 | d = (struct builtin_description *) bdesc_2arg_spe; |
6747 | for (i = 0; i < ARRAY_SIZE (bdesc_2arg_spe); ++i, ++d) | |
6748 | if (d->code == fcode) | |
6749 | return rs6000_expand_binop_builtin (d->icode, arglist, target); | |
6750 | ||
6751 | d = (struct builtin_description *) bdesc_spe_predicates; | |
6752 | for (i = 0; i < ARRAY_SIZE (bdesc_spe_predicates); ++i, ++d) | |
6753 | if (d->code == fcode) | |
6754 | return spe_expand_predicate_builtin (d->icode, arglist, target); | |
6755 | ||
6756 | d = (struct builtin_description *) bdesc_spe_evsel; | |
6757 | for (i = 0; i < ARRAY_SIZE (bdesc_spe_evsel); ++i, ++d) | |
6758 | if (d->code == fcode) | |
6759 | return spe_expand_evsel_builtin (d->icode, arglist, target); | |
6760 | ||
6761 | switch (fcode) | |
6762 | { | |
6763 | case SPE_BUILTIN_EVSTDDX: | |
61bea3b0 | 6764 | return spe_expand_stv_builtin (CODE_FOR_spe_evstddx, arglist); |
a3170dc6 | 6765 | case SPE_BUILTIN_EVSTDHX: |
61bea3b0 | 6766 | return spe_expand_stv_builtin (CODE_FOR_spe_evstdhx, arglist); |
a3170dc6 | 6767 | case SPE_BUILTIN_EVSTDWX: |
61bea3b0 | 6768 | return spe_expand_stv_builtin (CODE_FOR_spe_evstdwx, arglist); |
a3170dc6 | 6769 | case SPE_BUILTIN_EVSTWHEX: |
61bea3b0 | 6770 | return spe_expand_stv_builtin (CODE_FOR_spe_evstwhex, arglist); |
a3170dc6 | 6771 | case SPE_BUILTIN_EVSTWHOX: |
61bea3b0 | 6772 | return spe_expand_stv_builtin (CODE_FOR_spe_evstwhox, arglist); |
a3170dc6 | 6773 | case SPE_BUILTIN_EVSTWWEX: |
61bea3b0 | 6774 | return spe_expand_stv_builtin (CODE_FOR_spe_evstwwex, arglist); |
a3170dc6 | 6775 | case SPE_BUILTIN_EVSTWWOX: |
61bea3b0 | 6776 | return spe_expand_stv_builtin (CODE_FOR_spe_evstwwox, arglist); |
a3170dc6 | 6777 | case SPE_BUILTIN_EVSTDD: |
61bea3b0 | 6778 | return spe_expand_stv_builtin (CODE_FOR_spe_evstdd, arglist); |
a3170dc6 | 6779 | case SPE_BUILTIN_EVSTDH: |
61bea3b0 | 6780 | return spe_expand_stv_builtin (CODE_FOR_spe_evstdh, arglist); |
a3170dc6 | 6781 | case SPE_BUILTIN_EVSTDW: |
61bea3b0 | 6782 | return spe_expand_stv_builtin (CODE_FOR_spe_evstdw, arglist); |
a3170dc6 | 6783 | case SPE_BUILTIN_EVSTWHE: |
61bea3b0 | 6784 | return spe_expand_stv_builtin (CODE_FOR_spe_evstwhe, arglist); |
a3170dc6 | 6785 | case SPE_BUILTIN_EVSTWHO: |
61bea3b0 | 6786 | return spe_expand_stv_builtin (CODE_FOR_spe_evstwho, arglist); |
a3170dc6 | 6787 | case SPE_BUILTIN_EVSTWWE: |
61bea3b0 | 6788 | return spe_expand_stv_builtin (CODE_FOR_spe_evstwwe, arglist); |
a3170dc6 | 6789 | case SPE_BUILTIN_EVSTWWO: |
61bea3b0 | 6790 | return spe_expand_stv_builtin (CODE_FOR_spe_evstwwo, arglist); |
a3170dc6 AH |
6791 | case SPE_BUILTIN_MFSPEFSCR: |
6792 | icode = CODE_FOR_spe_mfspefscr; | |
6793 | tmode = insn_data[icode].operand[0].mode; | |
6794 | ||
6795 | if (target == 0 | |
6796 | || GET_MODE (target) != tmode | |
6797 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
6798 | target = gen_reg_rtx (tmode); | |
f676971a | 6799 | |
a3170dc6 AH |
6800 | pat = GEN_FCN (icode) (target); |
6801 | if (! pat) | |
6802 | return 0; | |
6803 | emit_insn (pat); | |
6804 | return target; | |
6805 | case SPE_BUILTIN_MTSPEFSCR: | |
6806 | icode = CODE_FOR_spe_mtspefscr; | |
6807 | arg0 = TREE_VALUE (arglist); | |
6808 | op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
6809 | mode0 = insn_data[icode].operand[0].mode; | |
6810 | ||
6811 | if (arg0 == error_mark_node) | |
6812 | return const0_rtx; | |
6813 | ||
6814 | if (! (*insn_data[icode].operand[0].predicate) (op0, mode0)) | |
6815 | op0 = copy_to_mode_reg (mode0, op0); | |
6816 | ||
6817 | pat = GEN_FCN (icode) (op0); | |
6818 | if (pat) | |
6819 | emit_insn (pat); | |
6820 | return NULL_RTX; | |
6821 | default: | |
6822 | break; | |
6823 | } | |
6824 | ||
6825 | *expandedp = false; | |
6826 | return NULL_RTX; | |
6827 | } | |
6828 | ||
6829 | static rtx | |
a2369ed3 | 6830 | spe_expand_predicate_builtin (enum insn_code icode, tree arglist, rtx target) |
a3170dc6 AH |
6831 | { |
6832 | rtx pat, scratch, tmp; | |
6833 | tree form = TREE_VALUE (arglist); | |
6834 | tree arg0 = TREE_VALUE (TREE_CHAIN (arglist)); | |
6835 | tree arg1 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist))); | |
6836 | rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
6837 | rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); | |
6838 | enum machine_mode mode0 = insn_data[icode].operand[1].mode; | |
6839 | enum machine_mode mode1 = insn_data[icode].operand[2].mode; | |
6840 | int form_int; | |
6841 | enum rtx_code code; | |
6842 | ||
6843 | if (TREE_CODE (form) != INTEGER_CST) | |
6844 | { | |
6845 | error ("argument 1 of __builtin_spe_predicate must be a constant"); | |
6846 | return const0_rtx; | |
6847 | } | |
6848 | else | |
6849 | form_int = TREE_INT_CST_LOW (form); | |
6850 | ||
37409796 | 6851 | gcc_assert (mode0 == mode1); |
a3170dc6 AH |
6852 | |
6853 | if (arg0 == error_mark_node || arg1 == error_mark_node) | |
6854 | return const0_rtx; | |
6855 | ||
6856 | if (target == 0 | |
6857 | || GET_MODE (target) != SImode | |
6858 | || ! (*insn_data[icode].operand[0].predicate) (target, SImode)) | |
6859 | target = gen_reg_rtx (SImode); | |
6860 | ||
6861 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) | |
6862 | op0 = copy_to_mode_reg (mode0, op0); | |
6863 | if (! (*insn_data[icode].operand[2].predicate) (op1, mode1)) | |
6864 | op1 = copy_to_mode_reg (mode1, op1); | |
6865 | ||
6866 | scratch = gen_reg_rtx (CCmode); | |
6867 | ||
6868 | pat = GEN_FCN (icode) (scratch, op0, op1); | |
6869 | if (! pat) | |
6870 | return const0_rtx; | |
6871 | emit_insn (pat); | |
6872 | ||
6873 | /* There are 4 variants for each predicate: _any_, _all_, _upper_, | |
6874 | _lower_. We use one compare, but look in different bits of the | |
6875 | CR for each variant. | |
6876 | ||
6877 | There are 2 elements in each SPE simd type (upper/lower). The CR | |
6878 | bits are set as follows: | |
6879 | ||
6880 | BIT0 | BIT 1 | BIT 2 | BIT 3 | |
6881 | U | L | (U | L) | (U & L) | |
6882 | ||
6883 | So, for an "all" relationship, BIT 3 would be set. | |
6884 | For an "any" relationship, BIT 2 would be set. Etc. | |
6885 | ||
6886 | Following traditional nomenclature, these bits map to: | |
6887 | ||
6888 | BIT0 | BIT 1 | BIT 2 | BIT 3 | |
6889 | LT | GT | EQ | OV | |
6890 | ||
6891 | Later, we will generate rtl to look in the LT/EQ/EQ/OV bits. | |
6892 | */ | |
6893 | ||
6894 | switch (form_int) | |
6895 | { | |
6896 | /* All variant. OV bit. */ | |
6897 | case 0: | |
6898 | /* We need to get to the OV bit, which is the ORDERED bit. We | |
6899 | could generate (ordered:SI (reg:CC xx) (const_int 0)), but | |
6900 | that's ugly and will trigger a validate_condition_mode abort. | |
6901 | So let's just use another pattern. */ | |
6902 | emit_insn (gen_move_from_CR_ov_bit (target, scratch)); | |
6903 | return target; | |
6904 | /* Any variant. EQ bit. */ | |
6905 | case 1: | |
6906 | code = EQ; | |
6907 | break; | |
6908 | /* Upper variant. LT bit. */ | |
6909 | case 2: | |
6910 | code = LT; | |
6911 | break; | |
6912 | /* Lower variant. GT bit. */ | |
6913 | case 3: | |
6914 | code = GT; | |
6915 | break; | |
6916 | default: | |
6917 | error ("argument 1 of __builtin_spe_predicate is out of range"); | |
6918 | return const0_rtx; | |
6919 | } | |
6920 | ||
6921 | tmp = gen_rtx_fmt_ee (code, SImode, scratch, const0_rtx); | |
6922 | emit_move_insn (target, tmp); | |
6923 | ||
6924 | return target; | |
6925 | } | |
6926 | ||
6927 | /* The evsel builtins look like this: | |
6928 | ||
6929 | e = __builtin_spe_evsel_OP (a, b, c, d); | |
6930 | ||
6931 | and work like this: | |
6932 | ||
6933 | e[upper] = a[upper] *OP* b[upper] ? c[upper] : d[upper]; | |
6934 | e[lower] = a[lower] *OP* b[lower] ? c[lower] : d[lower]; | |
6935 | */ | |
6936 | ||
6937 | static rtx | |
a2369ed3 | 6938 | spe_expand_evsel_builtin (enum insn_code icode, tree arglist, rtx target) |
a3170dc6 AH |
6939 | { |
6940 | rtx pat, scratch; | |
6941 | tree arg0 = TREE_VALUE (arglist); | |
6942 | tree arg1 = TREE_VALUE (TREE_CHAIN (arglist)); | |
6943 | tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist))); | |
6944 | tree arg3 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (TREE_CHAIN (arglist)))); | |
6945 | rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
6946 | rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); | |
6947 | rtx op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0); | |
6948 | rtx op3 = expand_expr (arg3, NULL_RTX, VOIDmode, 0); | |
6949 | enum machine_mode mode0 = insn_data[icode].operand[1].mode; | |
6950 | enum machine_mode mode1 = insn_data[icode].operand[2].mode; | |
6951 | ||
37409796 | 6952 | gcc_assert (mode0 == mode1); |
a3170dc6 AH |
6953 | |
6954 | if (arg0 == error_mark_node || arg1 == error_mark_node | |
6955 | || arg2 == error_mark_node || arg3 == error_mark_node) | |
6956 | return const0_rtx; | |
6957 | ||
6958 | if (target == 0 | |
6959 | || GET_MODE (target) != mode0 | |
6960 | || ! (*insn_data[icode].operand[0].predicate) (target, mode0)) | |
6961 | target = gen_reg_rtx (mode0); | |
6962 | ||
6963 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) | |
6964 | op0 = copy_to_mode_reg (mode0, op0); | |
6965 | if (! (*insn_data[icode].operand[1].predicate) (op1, mode1)) | |
6966 | op1 = copy_to_mode_reg (mode0, op1); | |
6967 | if (! (*insn_data[icode].operand[1].predicate) (op2, mode1)) | |
6968 | op2 = copy_to_mode_reg (mode0, op2); | |
6969 | if (! (*insn_data[icode].operand[1].predicate) (op3, mode1)) | |
6970 | op3 = copy_to_mode_reg (mode0, op3); | |
6971 | ||
6972 | /* Generate the compare. */ | |
6973 | scratch = gen_reg_rtx (CCmode); | |
6974 | pat = GEN_FCN (icode) (scratch, op0, op1); | |
6975 | if (! pat) | |
6976 | return const0_rtx; | |
6977 | emit_insn (pat); | |
6978 | ||
6979 | if (mode0 == V2SImode) | |
6980 | emit_insn (gen_spe_evsel (target, op2, op3, scratch)); | |
6981 | else | |
6982 | emit_insn (gen_spe_evsel_fs (target, op2, op3, scratch)); | |
6983 | ||
6984 | return target; | |
6985 | } | |
6986 | ||
0ac081f6 AH |
6987 | /* Expand an expression EXP that calls a built-in function, |
6988 | with result going to TARGET if that's convenient | |
6989 | (and in mode MODE if that's convenient). | |
6990 | SUBTARGET may be used as the target for computing one of EXP's operands. | |
6991 | IGNORE is nonzero if the value is to be ignored. */ | |
6992 | ||
6993 | static rtx | |
a2369ed3 | 6994 | rs6000_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED, |
c4ad648e AM |
6995 | enum machine_mode mode ATTRIBUTE_UNUSED, |
6996 | int ignore ATTRIBUTE_UNUSED) | |
0ac081f6 | 6997 | { |
92898235 AH |
6998 | tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0); |
6999 | tree arglist = TREE_OPERAND (exp, 1); | |
7000 | unsigned int fcode = DECL_FUNCTION_CODE (fndecl); | |
7001 | struct builtin_description *d; | |
7002 | size_t i; | |
7003 | rtx ret; | |
7004 | bool success; | |
f676971a | 7005 | |
7ccf35ed DN |
7006 | if (fcode == ALTIVEC_BUILTIN_MASK_FOR_LOAD |
7007 | || fcode == ALTIVEC_BUILTIN_MASK_FOR_STORE) | |
7008 | { | |
7009 | int icode = (int) CODE_FOR_altivec_lvsr; | |
7010 | enum machine_mode tmode = insn_data[icode].operand[0].mode; | |
7011 | enum machine_mode mode = insn_data[icode].operand[1].mode; | |
7012 | tree arg; | |
7013 | rtx op, addr, pat; | |
7014 | ||
37409796 | 7015 | gcc_assert (TARGET_ALTIVEC); |
7ccf35ed DN |
7016 | |
7017 | arg = TREE_VALUE (arglist); | |
37409796 | 7018 | gcc_assert (TREE_CODE (TREE_TYPE (arg)) == POINTER_TYPE); |
7ccf35ed DN |
7019 | op = expand_expr (arg, NULL_RTX, Pmode, EXPAND_NORMAL); |
7020 | addr = memory_address (mode, op); | |
7021 | if (fcode == ALTIVEC_BUILTIN_MASK_FOR_STORE) | |
7022 | op = addr; | |
7023 | else | |
7024 | { | |
7025 | /* For the load case need to negate the address. */ | |
7026 | op = gen_reg_rtx (GET_MODE (addr)); | |
7027 | emit_insn (gen_rtx_SET (VOIDmode, op, | |
7028 | gen_rtx_NEG (GET_MODE (addr), addr))); | |
c4ad648e | 7029 | } |
7ccf35ed DN |
7030 | op = gen_rtx_MEM (mode, op); |
7031 | ||
7032 | if (target == 0 | |
7033 | || GET_MODE (target) != tmode | |
7034 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
7035 | target = gen_reg_rtx (tmode); | |
7036 | ||
7037 | /*pat = gen_altivec_lvsr (target, op);*/ | |
7038 | pat = GEN_FCN (icode) (target, op); | |
7039 | if (!pat) | |
7040 | return 0; | |
7041 | emit_insn (pat); | |
7042 | ||
7043 | return target; | |
7044 | } | |
7045 | ||
0ac081f6 | 7046 | if (TARGET_ALTIVEC) |
92898235 AH |
7047 | { |
7048 | ret = altivec_expand_builtin (exp, target, &success); | |
7049 | ||
a3170dc6 AH |
7050 | if (success) |
7051 | return ret; | |
7052 | } | |
7053 | if (TARGET_SPE) | |
7054 | { | |
7055 | ret = spe_expand_builtin (exp, target, &success); | |
7056 | ||
92898235 AH |
7057 | if (success) |
7058 | return ret; | |
7059 | } | |
7060 | ||
37409796 NS |
7061 | gcc_assert (TARGET_ALTIVEC || TARGET_SPE); |
7062 | ||
7063 | /* Handle simple unary operations. */ | |
7064 | d = (struct builtin_description *) bdesc_1arg; | |
7065 | for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++) | |
7066 | if (d->code == fcode) | |
7067 | return rs6000_expand_unop_builtin (d->icode, arglist, target); | |
7068 | ||
7069 | /* Handle simple binary operations. */ | |
7070 | d = (struct builtin_description *) bdesc_2arg; | |
7071 | for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++) | |
7072 | if (d->code == fcode) | |
7073 | return rs6000_expand_binop_builtin (d->icode, arglist, target); | |
0ac081f6 | 7074 | |
37409796 NS |
7075 | /* Handle simple ternary operations. */ |
7076 | d = (struct builtin_description *) bdesc_3arg; | |
7077 | for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++) | |
7078 | if (d->code == fcode) | |
7079 | return rs6000_expand_ternop_builtin (d->icode, arglist, target); | |
7080 | ||
7081 | gcc_unreachable (); | |
0ac081f6 AH |
7082 | } |
7083 | ||
7c62e993 PB |
7084 | static tree |
7085 | build_opaque_vector_type (tree node, int nunits) | |
7086 | { | |
7087 | node = copy_node (node); | |
7088 | TYPE_MAIN_VARIANT (node) = node; | |
7089 | return build_vector_type (node, nunits); | |
7090 | } | |
7091 | ||
0ac081f6 | 7092 | static void |
863d938c | 7093 | rs6000_init_builtins (void) |
0ac081f6 | 7094 | { |
4a5eab38 PB |
7095 | V2SI_type_node = build_vector_type (intSI_type_node, 2); |
7096 | V2SF_type_node = build_vector_type (float_type_node, 2); | |
7097 | V4HI_type_node = build_vector_type (intHI_type_node, 4); | |
7098 | V4SI_type_node = build_vector_type (intSI_type_node, 4); | |
7099 | V4SF_type_node = build_vector_type (float_type_node, 4); | |
7e463bda | 7100 | V8HI_type_node = build_vector_type (intHI_type_node, 8); |
4a5eab38 PB |
7101 | V16QI_type_node = build_vector_type (intQI_type_node, 16); |
7102 | ||
7103 | unsigned_V16QI_type_node = build_vector_type (unsigned_intQI_type_node, 16); | |
7104 | unsigned_V8HI_type_node = build_vector_type (unsigned_intHI_type_node, 8); | |
7105 | unsigned_V4SI_type_node = build_vector_type (unsigned_intSI_type_node, 4); | |
7106 | ||
7c62e993 PB |
7107 | opaque_V2SF_type_node = build_opaque_vector_type (float_type_node, 2); |
7108 | opaque_V2SI_type_node = build_opaque_vector_type (intSI_type_node, 2); | |
6035d635 | 7109 | opaque_p_V2SI_type_node = build_pointer_type (opaque_V2SI_type_node); |
3fdaa45a | 7110 | |
8bb418a3 ZL |
7111 | /* The 'vector bool ...' types must be kept distinct from 'vector unsigned ...' |
7112 | types, especially in C++ land. Similarly, 'vector pixel' is distinct from | |
7113 | 'vector unsigned short'. */ | |
7114 | ||
8dd16ecc NS |
7115 | bool_char_type_node = build_distinct_type_copy (unsigned_intQI_type_node); |
7116 | bool_short_type_node = build_distinct_type_copy (unsigned_intHI_type_node); | |
7117 | bool_int_type_node = build_distinct_type_copy (unsigned_intSI_type_node); | |
7118 | pixel_type_node = build_distinct_type_copy (unsigned_intHI_type_node); | |
8bb418a3 ZL |
7119 | |
7120 | (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL, | |
7121 | get_identifier ("__bool char"), | |
7122 | bool_char_type_node)); | |
7123 | (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL, | |
7124 | get_identifier ("__bool short"), | |
7125 | bool_short_type_node)); | |
7126 | (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL, | |
7127 | get_identifier ("__bool int"), | |
7128 | bool_int_type_node)); | |
7129 | (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL, | |
7130 | get_identifier ("__pixel"), | |
7131 | pixel_type_node)); | |
7132 | ||
4a5eab38 PB |
7133 | bool_V16QI_type_node = build_vector_type (bool_char_type_node, 16); |
7134 | bool_V8HI_type_node = build_vector_type (bool_short_type_node, 8); | |
7135 | bool_V4SI_type_node = build_vector_type (bool_int_type_node, 4); | |
7136 | pixel_V8HI_type_node = build_vector_type (pixel_type_node, 8); | |
8bb418a3 ZL |
7137 | |
7138 | (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL, | |
7139 | get_identifier ("__vector unsigned char"), | |
7140 | unsigned_V16QI_type_node)); | |
7141 | (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL, | |
7142 | get_identifier ("__vector signed char"), | |
7143 | V16QI_type_node)); | |
7144 | (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL, | |
7145 | get_identifier ("__vector __bool char"), | |
7146 | bool_V16QI_type_node)); | |
7147 | ||
7148 | (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL, | |
7149 | get_identifier ("__vector unsigned short"), | |
7150 | unsigned_V8HI_type_node)); | |
7151 | (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL, | |
7152 | get_identifier ("__vector signed short"), | |
7153 | V8HI_type_node)); | |
7154 | (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL, | |
7155 | get_identifier ("__vector __bool short"), | |
7156 | bool_V8HI_type_node)); | |
7157 | ||
7158 | (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL, | |
7159 | get_identifier ("__vector unsigned int"), | |
7160 | unsigned_V4SI_type_node)); | |
7161 | (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL, | |
7162 | get_identifier ("__vector signed int"), | |
7163 | V4SI_type_node)); | |
7164 | (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL, | |
7165 | get_identifier ("__vector __bool int"), | |
7166 | bool_V4SI_type_node)); | |
7167 | ||
7168 | (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL, | |
7169 | get_identifier ("__vector float"), | |
7170 | V4SF_type_node)); | |
7171 | (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL, | |
7172 | get_identifier ("__vector __pixel"), | |
7173 | pixel_V8HI_type_node)); | |
7174 | ||
a3170dc6 | 7175 | if (TARGET_SPE) |
3fdaa45a | 7176 | spe_init_builtins (); |
0ac081f6 AH |
7177 | if (TARGET_ALTIVEC) |
7178 | altivec_init_builtins (); | |
0559cc77 DE |
7179 | if (TARGET_ALTIVEC || TARGET_SPE) |
7180 | rs6000_common_init_builtins (); | |
0ac081f6 AH |
7181 | } |
7182 | ||
a3170dc6 AH |
7183 | /* Search through a set of builtins and enable the mask bits. |
7184 | DESC is an array of builtins. | |
b6d08ca1 | 7185 | SIZE is the total number of builtins. |
a3170dc6 AH |
7186 | START is the builtin enum at which to start. |
7187 | END is the builtin enum at which to end. */ | |
0ac081f6 | 7188 | static void |
a2369ed3 | 7189 | enable_mask_for_builtins (struct builtin_description *desc, int size, |
f676971a | 7190 | enum rs6000_builtins start, |
a2369ed3 | 7191 | enum rs6000_builtins end) |
a3170dc6 AH |
7192 | { |
7193 | int i; | |
7194 | ||
7195 | for (i = 0; i < size; ++i) | |
7196 | if (desc[i].code == start) | |
7197 | break; | |
7198 | ||
7199 | if (i == size) | |
7200 | return; | |
7201 | ||
7202 | for (; i < size; ++i) | |
7203 | { | |
7204 | /* Flip all the bits on. */ | |
7205 | desc[i].mask = target_flags; | |
7206 | if (desc[i].code == end) | |
7207 | break; | |
7208 | } | |
7209 | } | |
7210 | ||
7211 | static void | |
863d938c | 7212 | spe_init_builtins (void) |
0ac081f6 | 7213 | { |
a3170dc6 AH |
7214 | tree endlink = void_list_node; |
7215 | tree puint_type_node = build_pointer_type (unsigned_type_node); | |
7216 | tree pushort_type_node = build_pointer_type (short_unsigned_type_node); | |
ae4b4a02 | 7217 | struct builtin_description *d; |
0ac081f6 AH |
7218 | size_t i; |
7219 | ||
a3170dc6 AH |
7220 | tree v2si_ftype_4_v2si |
7221 | = build_function_type | |
3fdaa45a AH |
7222 | (opaque_V2SI_type_node, |
7223 | tree_cons (NULL_TREE, opaque_V2SI_type_node, | |
7224 | tree_cons (NULL_TREE, opaque_V2SI_type_node, | |
7225 | tree_cons (NULL_TREE, opaque_V2SI_type_node, | |
7226 | tree_cons (NULL_TREE, opaque_V2SI_type_node, | |
a3170dc6 AH |
7227 | endlink))))); |
7228 | ||
7229 | tree v2sf_ftype_4_v2sf | |
7230 | = build_function_type | |
3fdaa45a AH |
7231 | (opaque_V2SF_type_node, |
7232 | tree_cons (NULL_TREE, opaque_V2SF_type_node, | |
7233 | tree_cons (NULL_TREE, opaque_V2SF_type_node, | |
7234 | tree_cons (NULL_TREE, opaque_V2SF_type_node, | |
7235 | tree_cons (NULL_TREE, opaque_V2SF_type_node, | |
a3170dc6 AH |
7236 | endlink))))); |
7237 | ||
7238 | tree int_ftype_int_v2si_v2si | |
7239 | = build_function_type | |
7240 | (integer_type_node, | |
7241 | tree_cons (NULL_TREE, integer_type_node, | |
3fdaa45a AH |
7242 | tree_cons (NULL_TREE, opaque_V2SI_type_node, |
7243 | tree_cons (NULL_TREE, opaque_V2SI_type_node, | |
a3170dc6 AH |
7244 | endlink)))); |
7245 | ||
7246 | tree int_ftype_int_v2sf_v2sf | |
7247 | = build_function_type | |
7248 | (integer_type_node, | |
7249 | tree_cons (NULL_TREE, integer_type_node, | |
3fdaa45a AH |
7250 | tree_cons (NULL_TREE, opaque_V2SF_type_node, |
7251 | tree_cons (NULL_TREE, opaque_V2SF_type_node, | |
a3170dc6 AH |
7252 | endlink)))); |
7253 | ||
7254 | tree void_ftype_v2si_puint_int | |
7255 | = build_function_type (void_type_node, | |
3fdaa45a | 7256 | tree_cons (NULL_TREE, opaque_V2SI_type_node, |
a3170dc6 AH |
7257 | tree_cons (NULL_TREE, puint_type_node, |
7258 | tree_cons (NULL_TREE, | |
7259 | integer_type_node, | |
7260 | endlink)))); | |
7261 | ||
7262 | tree void_ftype_v2si_puint_char | |
7263 | = build_function_type (void_type_node, | |
3fdaa45a | 7264 | tree_cons (NULL_TREE, opaque_V2SI_type_node, |
a3170dc6 AH |
7265 | tree_cons (NULL_TREE, puint_type_node, |
7266 | tree_cons (NULL_TREE, | |
7267 | char_type_node, | |
7268 | endlink)))); | |
7269 | ||
7270 | tree void_ftype_v2si_pv2si_int | |
7271 | = build_function_type (void_type_node, | |
3fdaa45a | 7272 | tree_cons (NULL_TREE, opaque_V2SI_type_node, |
6035d635 | 7273 | tree_cons (NULL_TREE, opaque_p_V2SI_type_node, |
a3170dc6 AH |
7274 | tree_cons (NULL_TREE, |
7275 | integer_type_node, | |
7276 | endlink)))); | |
7277 | ||
7278 | tree void_ftype_v2si_pv2si_char | |
7279 | = build_function_type (void_type_node, | |
3fdaa45a | 7280 | tree_cons (NULL_TREE, opaque_V2SI_type_node, |
6035d635 | 7281 | tree_cons (NULL_TREE, opaque_p_V2SI_type_node, |
a3170dc6 AH |
7282 | tree_cons (NULL_TREE, |
7283 | char_type_node, | |
7284 | endlink)))); | |
7285 | ||
7286 | tree void_ftype_int | |
7287 | = build_function_type (void_type_node, | |
7288 | tree_cons (NULL_TREE, integer_type_node, endlink)); | |
7289 | ||
7290 | tree int_ftype_void | |
36e8d515 | 7291 | = build_function_type (integer_type_node, endlink); |
a3170dc6 AH |
7292 | |
7293 | tree v2si_ftype_pv2si_int | |
3fdaa45a | 7294 | = build_function_type (opaque_V2SI_type_node, |
6035d635 | 7295 | tree_cons (NULL_TREE, opaque_p_V2SI_type_node, |
a3170dc6 AH |
7296 | tree_cons (NULL_TREE, integer_type_node, |
7297 | endlink))); | |
7298 | ||
7299 | tree v2si_ftype_puint_int | |
3fdaa45a | 7300 | = build_function_type (opaque_V2SI_type_node, |
a3170dc6 AH |
7301 | tree_cons (NULL_TREE, puint_type_node, |
7302 | tree_cons (NULL_TREE, integer_type_node, | |
7303 | endlink))); | |
7304 | ||
7305 | tree v2si_ftype_pushort_int | |
3fdaa45a | 7306 | = build_function_type (opaque_V2SI_type_node, |
a3170dc6 AH |
7307 | tree_cons (NULL_TREE, pushort_type_node, |
7308 | tree_cons (NULL_TREE, integer_type_node, | |
7309 | endlink))); | |
7310 | ||
00332c9f AH |
7311 | tree v2si_ftype_signed_char |
7312 | = build_function_type (opaque_V2SI_type_node, | |
7313 | tree_cons (NULL_TREE, signed_char_type_node, | |
7314 | endlink)); | |
7315 | ||
a3170dc6 AH |
7316 | /* The initialization of the simple binary and unary builtins is |
7317 | done in rs6000_common_init_builtins, but we have to enable the | |
7318 | mask bits here manually because we have run out of `target_flags' | |
7319 | bits. We really need to redesign this mask business. */ | |
7320 | ||
7321 | enable_mask_for_builtins ((struct builtin_description *) bdesc_2arg, | |
7322 | ARRAY_SIZE (bdesc_2arg), | |
7323 | SPE_BUILTIN_EVADDW, | |
7324 | SPE_BUILTIN_EVXOR); | |
7325 | enable_mask_for_builtins ((struct builtin_description *) bdesc_1arg, | |
7326 | ARRAY_SIZE (bdesc_1arg), | |
7327 | SPE_BUILTIN_EVABS, | |
7328 | SPE_BUILTIN_EVSUBFUSIAAW); | |
7329 | enable_mask_for_builtins ((struct builtin_description *) bdesc_spe_predicates, | |
7330 | ARRAY_SIZE (bdesc_spe_predicates), | |
7331 | SPE_BUILTIN_EVCMPEQ, | |
7332 | SPE_BUILTIN_EVFSTSTLT); | |
7333 | enable_mask_for_builtins ((struct builtin_description *) bdesc_spe_evsel, | |
7334 | ARRAY_SIZE (bdesc_spe_evsel), | |
7335 | SPE_BUILTIN_EVSEL_CMPGTS, | |
7336 | SPE_BUILTIN_EVSEL_FSTSTEQ); | |
7337 | ||
36252949 AH |
7338 | (*lang_hooks.decls.pushdecl) |
7339 | (build_decl (TYPE_DECL, get_identifier ("__ev64_opaque__"), | |
7340 | opaque_V2SI_type_node)); | |
7341 | ||
a3170dc6 | 7342 | /* Initialize irregular SPE builtins. */ |
f676971a | 7343 | |
a3170dc6 AH |
7344 | def_builtin (target_flags, "__builtin_spe_mtspefscr", void_ftype_int, SPE_BUILTIN_MTSPEFSCR); |
7345 | def_builtin (target_flags, "__builtin_spe_mfspefscr", int_ftype_void, SPE_BUILTIN_MFSPEFSCR); | |
7346 | def_builtin (target_flags, "__builtin_spe_evstddx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDDX); | |
7347 | def_builtin (target_flags, "__builtin_spe_evstdhx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDHX); | |
7348 | def_builtin (target_flags, "__builtin_spe_evstdwx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDWX); | |
7349 | def_builtin (target_flags, "__builtin_spe_evstwhex", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWHEX); | |
7350 | def_builtin (target_flags, "__builtin_spe_evstwhox", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWHOX); | |
7351 | def_builtin (target_flags, "__builtin_spe_evstwwex", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWWEX); | |
7352 | def_builtin (target_flags, "__builtin_spe_evstwwox", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWWOX); | |
7353 | def_builtin (target_flags, "__builtin_spe_evstdd", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDD); | |
7354 | def_builtin (target_flags, "__builtin_spe_evstdh", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDH); | |
7355 | def_builtin (target_flags, "__builtin_spe_evstdw", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDW); | |
7356 | def_builtin (target_flags, "__builtin_spe_evstwhe", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWHE); | |
7357 | def_builtin (target_flags, "__builtin_spe_evstwho", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWHO); | |
7358 | def_builtin (target_flags, "__builtin_spe_evstwwe", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWWE); | |
7359 | def_builtin (target_flags, "__builtin_spe_evstwwo", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWWO); | |
00332c9f AH |
7360 | def_builtin (target_flags, "__builtin_spe_evsplatfi", v2si_ftype_signed_char, SPE_BUILTIN_EVSPLATFI); |
7361 | def_builtin (target_flags, "__builtin_spe_evsplati", v2si_ftype_signed_char, SPE_BUILTIN_EVSPLATI); | |
a3170dc6 AH |
7362 | |
7363 | /* Loads. */ | |
7364 | def_builtin (target_flags, "__builtin_spe_evlddx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDDX); | |
7365 | def_builtin (target_flags, "__builtin_spe_evldwx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDWX); | |
7366 | def_builtin (target_flags, "__builtin_spe_evldhx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDHX); | |
7367 | def_builtin (target_flags, "__builtin_spe_evlwhex", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHEX); | |
7368 | def_builtin (target_flags, "__builtin_spe_evlwhoux", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOUX); | |
7369 | def_builtin (target_flags, "__builtin_spe_evlwhosx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOSX); | |
7370 | def_builtin (target_flags, "__builtin_spe_evlwwsplatx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWWSPLATX); | |
7371 | def_builtin (target_flags, "__builtin_spe_evlwhsplatx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHSPLATX); | |
7372 | def_builtin (target_flags, "__builtin_spe_evlhhesplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHESPLATX); | |
7373 | def_builtin (target_flags, "__builtin_spe_evlhhousplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOUSPLATX); | |
7374 | def_builtin (target_flags, "__builtin_spe_evlhhossplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOSSPLATX); | |
7375 | def_builtin (target_flags, "__builtin_spe_evldd", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDD); | |
7376 | def_builtin (target_flags, "__builtin_spe_evldw", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDW); | |
7377 | def_builtin (target_flags, "__builtin_spe_evldh", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDH); | |
7378 | def_builtin (target_flags, "__builtin_spe_evlhhesplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHESPLAT); | |
7379 | def_builtin (target_flags, "__builtin_spe_evlhhossplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOSSPLAT); | |
7380 | def_builtin (target_flags, "__builtin_spe_evlhhousplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOUSPLAT); | |
7381 | def_builtin (target_flags, "__builtin_spe_evlwhe", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHE); | |
7382 | def_builtin (target_flags, "__builtin_spe_evlwhos", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOS); | |
7383 | def_builtin (target_flags, "__builtin_spe_evlwhou", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOU); | |
7384 | def_builtin (target_flags, "__builtin_spe_evlwhsplat", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHSPLAT); | |
7385 | def_builtin (target_flags, "__builtin_spe_evlwwsplat", v2si_ftype_puint_int, SPE_BUILTIN_EVLWWSPLAT); | |
7386 | ||
7387 | /* Predicates. */ | |
7388 | d = (struct builtin_description *) bdesc_spe_predicates; | |
7389 | for (i = 0; i < ARRAY_SIZE (bdesc_spe_predicates); ++i, d++) | |
7390 | { | |
7391 | tree type; | |
7392 | ||
7393 | switch (insn_data[d->icode].operand[1].mode) | |
7394 | { | |
7395 | case V2SImode: | |
7396 | type = int_ftype_int_v2si_v2si; | |
7397 | break; | |
7398 | case V2SFmode: | |
7399 | type = int_ftype_int_v2sf_v2sf; | |
7400 | break; | |
7401 | default: | |
37409796 | 7402 | gcc_unreachable (); |
a3170dc6 AH |
7403 | } |
7404 | ||
7405 | def_builtin (d->mask, d->name, type, d->code); | |
7406 | } | |
7407 | ||
7408 | /* Evsel predicates. */ | |
7409 | d = (struct builtin_description *) bdesc_spe_evsel; | |
7410 | for (i = 0; i < ARRAY_SIZE (bdesc_spe_evsel); ++i, d++) | |
7411 | { | |
7412 | tree type; | |
7413 | ||
7414 | switch (insn_data[d->icode].operand[1].mode) | |
7415 | { | |
7416 | case V2SImode: | |
7417 | type = v2si_ftype_4_v2si; | |
7418 | break; | |
7419 | case V2SFmode: | |
7420 | type = v2sf_ftype_4_v2sf; | |
7421 | break; | |
7422 | default: | |
37409796 | 7423 | gcc_unreachable (); |
a3170dc6 AH |
7424 | } |
7425 | ||
7426 | def_builtin (d->mask, d->name, type, d->code); | |
7427 | } | |
7428 | } | |
7429 | ||
7430 | static void | |
863d938c | 7431 | altivec_init_builtins (void) |
a3170dc6 AH |
7432 | { |
7433 | struct builtin_description *d; | |
7434 | struct builtin_description_predicates *dp; | |
7435 | size_t i; | |
7436 | tree pfloat_type_node = build_pointer_type (float_type_node); | |
7437 | tree pint_type_node = build_pointer_type (integer_type_node); | |
7438 | tree pshort_type_node = build_pointer_type (short_integer_type_node); | |
7439 | tree pchar_type_node = build_pointer_type (char_type_node); | |
7440 | ||
7441 | tree pvoid_type_node = build_pointer_type (void_type_node); | |
7442 | ||
0dbc3651 ZW |
7443 | tree pcfloat_type_node = build_pointer_type (build_qualified_type (float_type_node, TYPE_QUAL_CONST)); |
7444 | tree pcint_type_node = build_pointer_type (build_qualified_type (integer_type_node, TYPE_QUAL_CONST)); | |
7445 | tree pcshort_type_node = build_pointer_type (build_qualified_type (short_integer_type_node, TYPE_QUAL_CONST)); | |
7446 | tree pcchar_type_node = build_pointer_type (build_qualified_type (char_type_node, TYPE_QUAL_CONST)); | |
7447 | ||
7448 | tree pcvoid_type_node = build_pointer_type (build_qualified_type (void_type_node, TYPE_QUAL_CONST)); | |
7449 | ||
a3170dc6 AH |
7450 | tree int_ftype_int_v4si_v4si |
7451 | = build_function_type_list (integer_type_node, | |
7452 | integer_type_node, V4SI_type_node, | |
7453 | V4SI_type_node, NULL_TREE); | |
0dbc3651 ZW |
7454 | tree v4sf_ftype_pcfloat |
7455 | = build_function_type_list (V4SF_type_node, pcfloat_type_node, NULL_TREE); | |
a3170dc6 | 7456 | tree void_ftype_pfloat_v4sf |
b4de2f7d | 7457 | = build_function_type_list (void_type_node, |
a3170dc6 | 7458 | pfloat_type_node, V4SF_type_node, NULL_TREE); |
0dbc3651 ZW |
7459 | tree v4si_ftype_pcint |
7460 | = build_function_type_list (V4SI_type_node, pcint_type_node, NULL_TREE); | |
7461 | tree void_ftype_pint_v4si | |
b4de2f7d AH |
7462 | = build_function_type_list (void_type_node, |
7463 | pint_type_node, V4SI_type_node, NULL_TREE); | |
0dbc3651 ZW |
7464 | tree v8hi_ftype_pcshort |
7465 | = build_function_type_list (V8HI_type_node, pcshort_type_node, NULL_TREE); | |
f18c054f | 7466 | tree void_ftype_pshort_v8hi |
b4de2f7d AH |
7467 | = build_function_type_list (void_type_node, |
7468 | pshort_type_node, V8HI_type_node, NULL_TREE); | |
0dbc3651 ZW |
7469 | tree v16qi_ftype_pcchar |
7470 | = build_function_type_list (V16QI_type_node, pcchar_type_node, NULL_TREE); | |
f18c054f | 7471 | tree void_ftype_pchar_v16qi |
b4de2f7d AH |
7472 | = build_function_type_list (void_type_node, |
7473 | pchar_type_node, V16QI_type_node, NULL_TREE); | |
95385cbb | 7474 | tree void_ftype_v4si |
b4de2f7d | 7475 | = build_function_type_list (void_type_node, V4SI_type_node, NULL_TREE); |
a3170dc6 AH |
7476 | tree v8hi_ftype_void |
7477 | = build_function_type (V8HI_type_node, void_list_node); | |
7478 | tree void_ftype_void | |
7479 | = build_function_type (void_type_node, void_list_node); | |
e34b6648 JJ |
7480 | tree void_ftype_int |
7481 | = build_function_type_list (void_type_node, integer_type_node, NULL_TREE); | |
0dbc3651 | 7482 | |
b4a62fa0 | 7483 | tree v16qi_ftype_long_pcvoid |
a3170dc6 | 7484 | = build_function_type_list (V16QI_type_node, |
b4a62fa0 SB |
7485 | long_integer_type_node, pcvoid_type_node, NULL_TREE); |
7486 | tree v8hi_ftype_long_pcvoid | |
a3170dc6 | 7487 | = build_function_type_list (V8HI_type_node, |
b4a62fa0 SB |
7488 | long_integer_type_node, pcvoid_type_node, NULL_TREE); |
7489 | tree v4si_ftype_long_pcvoid | |
a3170dc6 | 7490 | = build_function_type_list (V4SI_type_node, |
b4a62fa0 | 7491 | long_integer_type_node, pcvoid_type_node, NULL_TREE); |
0dbc3651 | 7492 | |
b4a62fa0 | 7493 | tree void_ftype_v4si_long_pvoid |
b4de2f7d | 7494 | = build_function_type_list (void_type_node, |
b4a62fa0 | 7495 | V4SI_type_node, long_integer_type_node, |
b4de2f7d | 7496 | pvoid_type_node, NULL_TREE); |
b4a62fa0 | 7497 | tree void_ftype_v16qi_long_pvoid |
b4de2f7d | 7498 | = build_function_type_list (void_type_node, |
b4a62fa0 | 7499 | V16QI_type_node, long_integer_type_node, |
b4de2f7d | 7500 | pvoid_type_node, NULL_TREE); |
b4a62fa0 | 7501 | tree void_ftype_v8hi_long_pvoid |
b4de2f7d | 7502 | = build_function_type_list (void_type_node, |
b4a62fa0 | 7503 | V8HI_type_node, long_integer_type_node, |
b4de2f7d | 7504 | pvoid_type_node, NULL_TREE); |
a3170dc6 AH |
7505 | tree int_ftype_int_v8hi_v8hi |
7506 | = build_function_type_list (integer_type_node, | |
7507 | integer_type_node, V8HI_type_node, | |
7508 | V8HI_type_node, NULL_TREE); | |
7509 | tree int_ftype_int_v16qi_v16qi | |
7510 | = build_function_type_list (integer_type_node, | |
7511 | integer_type_node, V16QI_type_node, | |
7512 | V16QI_type_node, NULL_TREE); | |
7513 | tree int_ftype_int_v4sf_v4sf | |
7514 | = build_function_type_list (integer_type_node, | |
7515 | integer_type_node, V4SF_type_node, | |
7516 | V4SF_type_node, NULL_TREE); | |
7517 | tree v4si_ftype_v4si | |
7518 | = build_function_type_list (V4SI_type_node, V4SI_type_node, NULL_TREE); | |
7519 | tree v8hi_ftype_v8hi | |
7520 | = build_function_type_list (V8HI_type_node, V8HI_type_node, NULL_TREE); | |
7521 | tree v16qi_ftype_v16qi | |
7522 | = build_function_type_list (V16QI_type_node, V16QI_type_node, NULL_TREE); | |
7523 | tree v4sf_ftype_v4sf | |
7524 | = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE); | |
8bb418a3 | 7525 | tree void_ftype_pcvoid_int_int |
a3170dc6 | 7526 | = build_function_type_list (void_type_node, |
0dbc3651 | 7527 | pcvoid_type_node, integer_type_node, |
8bb418a3 ZL |
7528 | integer_type_node, NULL_TREE); |
7529 | tree int_ftype_pcchar | |
7530 | = build_function_type_list (integer_type_node, | |
7531 | pcchar_type_node, NULL_TREE); | |
7532 | ||
0dbc3651 ZW |
7533 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_4sf", v4sf_ftype_pcfloat, |
7534 | ALTIVEC_BUILTIN_LD_INTERNAL_4sf); | |
7535 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_4sf", void_ftype_pfloat_v4sf, | |
7536 | ALTIVEC_BUILTIN_ST_INTERNAL_4sf); | |
7537 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_4si", v4si_ftype_pcint, | |
7538 | ALTIVEC_BUILTIN_LD_INTERNAL_4si); | |
7539 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_4si", void_ftype_pint_v4si, | |
7540 | ALTIVEC_BUILTIN_ST_INTERNAL_4si); | |
7541 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_8hi", v8hi_ftype_pcshort, | |
7542 | ALTIVEC_BUILTIN_LD_INTERNAL_8hi); | |
7543 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_8hi", void_ftype_pshort_v8hi, | |
7544 | ALTIVEC_BUILTIN_ST_INTERNAL_8hi); | |
7545 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_16qi", v16qi_ftype_pcchar, | |
7546 | ALTIVEC_BUILTIN_LD_INTERNAL_16qi); | |
7547 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_16qi", void_ftype_pchar_v16qi, | |
7548 | ALTIVEC_BUILTIN_ST_INTERNAL_16qi); | |
a3170dc6 AH |
7549 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_mtvscr", void_ftype_v4si, ALTIVEC_BUILTIN_MTVSCR); |
7550 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_mfvscr", v8hi_ftype_void, ALTIVEC_BUILTIN_MFVSCR); | |
7551 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_dssall", void_ftype_void, ALTIVEC_BUILTIN_DSSALL); | |
e34b6648 | 7552 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_dss", void_ftype_int, ALTIVEC_BUILTIN_DSS); |
b4a62fa0 SB |
7553 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvsl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSL); |
7554 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvsr", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSR); | |
7555 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvebx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEBX); | |
7556 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvehx", v8hi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEHX); | |
7557 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvewx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEWX); | |
7558 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvxl", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVXL); | |
7559 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVX); | |
7560 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVX); | |
7561 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvewx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVEWX); | |
7562 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvxl", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVXL); | |
7563 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvebx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVEBX); | |
7564 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvehx", void_ftype_v8hi_long_pvoid, ALTIVEC_BUILTIN_STVEHX); | |
a3170dc6 | 7565 | |
8bb418a3 ZL |
7566 | /* See altivec.h for usage of "__builtin_altivec_compiletime_error". */ |
7567 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_compiletime_error", int_ftype_pcchar, | |
7568 | ALTIVEC_BUILTIN_COMPILETIME_ERROR); | |
7569 | ||
a3170dc6 AH |
7570 | /* Add the DST variants. */ |
7571 | d = (struct builtin_description *) bdesc_dst; | |
7572 | for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++) | |
8bb418a3 | 7573 | def_builtin (d->mask, d->name, void_ftype_pcvoid_int_int, d->code); |
a3170dc6 AH |
7574 | |
7575 | /* Initialize the predicates. */ | |
7576 | dp = (struct builtin_description_predicates *) bdesc_altivec_preds; | |
7577 | for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, dp++) | |
7578 | { | |
7579 | enum machine_mode mode1; | |
7580 | tree type; | |
7581 | ||
7582 | mode1 = insn_data[dp->icode].operand[1].mode; | |
7583 | ||
7584 | switch (mode1) | |
7585 | { | |
7586 | case V4SImode: | |
7587 | type = int_ftype_int_v4si_v4si; | |
7588 | break; | |
7589 | case V8HImode: | |
7590 | type = int_ftype_int_v8hi_v8hi; | |
7591 | break; | |
7592 | case V16QImode: | |
7593 | type = int_ftype_int_v16qi_v16qi; | |
7594 | break; | |
7595 | case V4SFmode: | |
7596 | type = int_ftype_int_v4sf_v4sf; | |
7597 | break; | |
7598 | default: | |
37409796 | 7599 | gcc_unreachable (); |
a3170dc6 | 7600 | } |
f676971a | 7601 | |
a3170dc6 AH |
7602 | def_builtin (dp->mask, dp->name, type, dp->code); |
7603 | } | |
7604 | ||
7605 | /* Initialize the abs* operators. */ | |
7606 | d = (struct builtin_description *) bdesc_abs; | |
7607 | for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++) | |
7608 | { | |
7609 | enum machine_mode mode0; | |
7610 | tree type; | |
7611 | ||
7612 | mode0 = insn_data[d->icode].operand[0].mode; | |
7613 | ||
7614 | switch (mode0) | |
7615 | { | |
7616 | case V4SImode: | |
7617 | type = v4si_ftype_v4si; | |
7618 | break; | |
7619 | case V8HImode: | |
7620 | type = v8hi_ftype_v8hi; | |
7621 | break; | |
7622 | case V16QImode: | |
7623 | type = v16qi_ftype_v16qi; | |
7624 | break; | |
7625 | case V4SFmode: | |
7626 | type = v4sf_ftype_v4sf; | |
7627 | break; | |
7628 | default: | |
37409796 | 7629 | gcc_unreachable (); |
a3170dc6 | 7630 | } |
f676971a | 7631 | |
a3170dc6 AH |
7632 | def_builtin (d->mask, d->name, type, d->code); |
7633 | } | |
7ccf35ed | 7634 | |
13c62176 DN |
7635 | if (TARGET_ALTIVEC) |
7636 | { | |
7637 | tree decl; | |
7638 | ||
7639 | /* Initialize target builtin that implements | |
7640 | targetm.vectorize.builtin_mask_for_load. */ | |
7641 | ||
7642 | decl = lang_hooks.builtin_function ("__builtin_altivec_mask_for_load", | |
8bb46326 DN |
7643 | v16qi_ftype_long_pcvoid, |
7644 | ALTIVEC_BUILTIN_MASK_FOR_LOAD, | |
7645 | BUILT_IN_MD, NULL, | |
7646 | tree_cons (get_identifier ("const"), | |
7647 | NULL_TREE, NULL_TREE)); | |
13c62176 DN |
7648 | /* Record the decl. Will be used by rs6000_builtin_mask_for_load. */ |
7649 | altivec_builtin_mask_for_load = decl; | |
13c62176 | 7650 | } |
a3170dc6 AH |
7651 | } |
7652 | ||
7653 | static void | |
863d938c | 7654 | rs6000_common_init_builtins (void) |
a3170dc6 AH |
7655 | { |
7656 | struct builtin_description *d; | |
7657 | size_t i; | |
7658 | ||
7659 | tree v4sf_ftype_v4sf_v4sf_v16qi | |
7660 | = build_function_type_list (V4SF_type_node, | |
7661 | V4SF_type_node, V4SF_type_node, | |
7662 | V16QI_type_node, NULL_TREE); | |
7663 | tree v4si_ftype_v4si_v4si_v16qi | |
7664 | = build_function_type_list (V4SI_type_node, | |
7665 | V4SI_type_node, V4SI_type_node, | |
7666 | V16QI_type_node, NULL_TREE); | |
7667 | tree v8hi_ftype_v8hi_v8hi_v16qi | |
7668 | = build_function_type_list (V8HI_type_node, | |
7669 | V8HI_type_node, V8HI_type_node, | |
7670 | V16QI_type_node, NULL_TREE); | |
7671 | tree v16qi_ftype_v16qi_v16qi_v16qi | |
7672 | = build_function_type_list (V16QI_type_node, | |
7673 | V16QI_type_node, V16QI_type_node, | |
7674 | V16QI_type_node, NULL_TREE); | |
b9e4e5d1 ZL |
7675 | tree v4si_ftype_int |
7676 | = build_function_type_list (V4SI_type_node, integer_type_node, NULL_TREE); | |
7677 | tree v8hi_ftype_int | |
7678 | = build_function_type_list (V8HI_type_node, integer_type_node, NULL_TREE); | |
7679 | tree v16qi_ftype_int | |
7680 | = build_function_type_list (V16QI_type_node, integer_type_node, NULL_TREE); | |
a3170dc6 AH |
7681 | tree v8hi_ftype_v16qi |
7682 | = build_function_type_list (V8HI_type_node, V16QI_type_node, NULL_TREE); | |
7683 | tree v4sf_ftype_v4sf | |
7684 | = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE); | |
7685 | ||
7686 | tree v2si_ftype_v2si_v2si | |
2abe3e28 AH |
7687 | = build_function_type_list (opaque_V2SI_type_node, |
7688 | opaque_V2SI_type_node, | |
7689 | opaque_V2SI_type_node, NULL_TREE); | |
a3170dc6 AH |
7690 | |
7691 | tree v2sf_ftype_v2sf_v2sf | |
2abe3e28 AH |
7692 | = build_function_type_list (opaque_V2SF_type_node, |
7693 | opaque_V2SF_type_node, | |
7694 | opaque_V2SF_type_node, NULL_TREE); | |
a3170dc6 AH |
7695 | |
7696 | tree v2si_ftype_int_int | |
2abe3e28 | 7697 | = build_function_type_list (opaque_V2SI_type_node, |
a3170dc6 AH |
7698 | integer_type_node, integer_type_node, |
7699 | NULL_TREE); | |
7700 | ||
7701 | tree v2si_ftype_v2si | |
2abe3e28 AH |
7702 | = build_function_type_list (opaque_V2SI_type_node, |
7703 | opaque_V2SI_type_node, NULL_TREE); | |
a3170dc6 AH |
7704 | |
7705 | tree v2sf_ftype_v2sf | |
2abe3e28 AH |
7706 | = build_function_type_list (opaque_V2SF_type_node, |
7707 | opaque_V2SF_type_node, NULL_TREE); | |
f676971a | 7708 | |
a3170dc6 | 7709 | tree v2sf_ftype_v2si |
2abe3e28 AH |
7710 | = build_function_type_list (opaque_V2SF_type_node, |
7711 | opaque_V2SI_type_node, NULL_TREE); | |
a3170dc6 AH |
7712 | |
7713 | tree v2si_ftype_v2sf | |
2abe3e28 AH |
7714 | = build_function_type_list (opaque_V2SI_type_node, |
7715 | opaque_V2SF_type_node, NULL_TREE); | |
a3170dc6 AH |
7716 | |
7717 | tree v2si_ftype_v2si_char | |
2abe3e28 AH |
7718 | = build_function_type_list (opaque_V2SI_type_node, |
7719 | opaque_V2SI_type_node, | |
7720 | char_type_node, NULL_TREE); | |
a3170dc6 AH |
7721 | |
7722 | tree v2si_ftype_int_char | |
2abe3e28 | 7723 | = build_function_type_list (opaque_V2SI_type_node, |
a3170dc6 AH |
7724 | integer_type_node, char_type_node, NULL_TREE); |
7725 | ||
7726 | tree v2si_ftype_char | |
2abe3e28 AH |
7727 | = build_function_type_list (opaque_V2SI_type_node, |
7728 | char_type_node, NULL_TREE); | |
a3170dc6 AH |
7729 | |
7730 | tree int_ftype_int_int | |
7731 | = build_function_type_list (integer_type_node, | |
7732 | integer_type_node, integer_type_node, | |
7733 | NULL_TREE); | |
95385cbb | 7734 | |
0ac081f6 | 7735 | tree v4si_ftype_v4si_v4si |
b4de2f7d AH |
7736 | = build_function_type_list (V4SI_type_node, |
7737 | V4SI_type_node, V4SI_type_node, NULL_TREE); | |
b9e4e5d1 | 7738 | tree v4sf_ftype_v4si_int |
b4de2f7d | 7739 | = build_function_type_list (V4SF_type_node, |
b9e4e5d1 ZL |
7740 | V4SI_type_node, integer_type_node, NULL_TREE); |
7741 | tree v4si_ftype_v4sf_int | |
b4de2f7d | 7742 | = build_function_type_list (V4SI_type_node, |
b9e4e5d1 ZL |
7743 | V4SF_type_node, integer_type_node, NULL_TREE); |
7744 | tree v4si_ftype_v4si_int | |
b4de2f7d | 7745 | = build_function_type_list (V4SI_type_node, |
b9e4e5d1 ZL |
7746 | V4SI_type_node, integer_type_node, NULL_TREE); |
7747 | tree v8hi_ftype_v8hi_int | |
b4de2f7d | 7748 | = build_function_type_list (V8HI_type_node, |
b9e4e5d1 ZL |
7749 | V8HI_type_node, integer_type_node, NULL_TREE); |
7750 | tree v16qi_ftype_v16qi_int | |
b4de2f7d | 7751 | = build_function_type_list (V16QI_type_node, |
b9e4e5d1 ZL |
7752 | V16QI_type_node, integer_type_node, NULL_TREE); |
7753 | tree v16qi_ftype_v16qi_v16qi_int | |
b4de2f7d AH |
7754 | = build_function_type_list (V16QI_type_node, |
7755 | V16QI_type_node, V16QI_type_node, | |
b9e4e5d1 ZL |
7756 | integer_type_node, NULL_TREE); |
7757 | tree v8hi_ftype_v8hi_v8hi_int | |
b4de2f7d AH |
7758 | = build_function_type_list (V8HI_type_node, |
7759 | V8HI_type_node, V8HI_type_node, | |
b9e4e5d1 ZL |
7760 | integer_type_node, NULL_TREE); |
7761 | tree v4si_ftype_v4si_v4si_int | |
b4de2f7d AH |
7762 | = build_function_type_list (V4SI_type_node, |
7763 | V4SI_type_node, V4SI_type_node, | |
b9e4e5d1 ZL |
7764 | integer_type_node, NULL_TREE); |
7765 | tree v4sf_ftype_v4sf_v4sf_int | |
b4de2f7d AH |
7766 | = build_function_type_list (V4SF_type_node, |
7767 | V4SF_type_node, V4SF_type_node, | |
b9e4e5d1 | 7768 | integer_type_node, NULL_TREE); |
0ac081f6 | 7769 | tree v4sf_ftype_v4sf_v4sf |
b4de2f7d AH |
7770 | = build_function_type_list (V4SF_type_node, |
7771 | V4SF_type_node, V4SF_type_node, NULL_TREE); | |
617e0e1d | 7772 | tree v4sf_ftype_v4sf_v4sf_v4si |
b4de2f7d AH |
7773 | = build_function_type_list (V4SF_type_node, |
7774 | V4SF_type_node, V4SF_type_node, | |
7775 | V4SI_type_node, NULL_TREE); | |
2212663f | 7776 | tree v4sf_ftype_v4sf_v4sf_v4sf |
b4de2f7d AH |
7777 | = build_function_type_list (V4SF_type_node, |
7778 | V4SF_type_node, V4SF_type_node, | |
7779 | V4SF_type_node, NULL_TREE); | |
f676971a | 7780 | tree v4si_ftype_v4si_v4si_v4si |
b4de2f7d AH |
7781 | = build_function_type_list (V4SI_type_node, |
7782 | V4SI_type_node, V4SI_type_node, | |
7783 | V4SI_type_node, NULL_TREE); | |
0ac081f6 | 7784 | tree v8hi_ftype_v8hi_v8hi |
b4de2f7d AH |
7785 | = build_function_type_list (V8HI_type_node, |
7786 | V8HI_type_node, V8HI_type_node, NULL_TREE); | |
2212663f | 7787 | tree v8hi_ftype_v8hi_v8hi_v8hi |
b4de2f7d AH |
7788 | = build_function_type_list (V8HI_type_node, |
7789 | V8HI_type_node, V8HI_type_node, | |
7790 | V8HI_type_node, NULL_TREE); | |
c4ad648e | 7791 | tree v4si_ftype_v8hi_v8hi_v4si |
b4de2f7d AH |
7792 | = build_function_type_list (V4SI_type_node, |
7793 | V8HI_type_node, V8HI_type_node, | |
7794 | V4SI_type_node, NULL_TREE); | |
c4ad648e | 7795 | tree v4si_ftype_v16qi_v16qi_v4si |
b4de2f7d AH |
7796 | = build_function_type_list (V4SI_type_node, |
7797 | V16QI_type_node, V16QI_type_node, | |
7798 | V4SI_type_node, NULL_TREE); | |
0ac081f6 | 7799 | tree v16qi_ftype_v16qi_v16qi |
b4de2f7d AH |
7800 | = build_function_type_list (V16QI_type_node, |
7801 | V16QI_type_node, V16QI_type_node, NULL_TREE); | |
0ac081f6 | 7802 | tree v4si_ftype_v4sf_v4sf |
b4de2f7d AH |
7803 | = build_function_type_list (V4SI_type_node, |
7804 | V4SF_type_node, V4SF_type_node, NULL_TREE); | |
0ac081f6 | 7805 | tree v8hi_ftype_v16qi_v16qi |
b4de2f7d AH |
7806 | = build_function_type_list (V8HI_type_node, |
7807 | V16QI_type_node, V16QI_type_node, NULL_TREE); | |
0ac081f6 | 7808 | tree v4si_ftype_v8hi_v8hi |
b4de2f7d AH |
7809 | = build_function_type_list (V4SI_type_node, |
7810 | V8HI_type_node, V8HI_type_node, NULL_TREE); | |
0ac081f6 | 7811 | tree v8hi_ftype_v4si_v4si |
b4de2f7d AH |
7812 | = build_function_type_list (V8HI_type_node, |
7813 | V4SI_type_node, V4SI_type_node, NULL_TREE); | |
0ac081f6 | 7814 | tree v16qi_ftype_v8hi_v8hi |
b4de2f7d AH |
7815 | = build_function_type_list (V16QI_type_node, |
7816 | V8HI_type_node, V8HI_type_node, NULL_TREE); | |
0ac081f6 | 7817 | tree v4si_ftype_v16qi_v4si |
b4de2f7d AH |
7818 | = build_function_type_list (V4SI_type_node, |
7819 | V16QI_type_node, V4SI_type_node, NULL_TREE); | |
fa066a23 | 7820 | tree v4si_ftype_v16qi_v16qi |
b4de2f7d AH |
7821 | = build_function_type_list (V4SI_type_node, |
7822 | V16QI_type_node, V16QI_type_node, NULL_TREE); | |
0ac081f6 | 7823 | tree v4si_ftype_v8hi_v4si |
b4de2f7d AH |
7824 | = build_function_type_list (V4SI_type_node, |
7825 | V8HI_type_node, V4SI_type_node, NULL_TREE); | |
a3170dc6 AH |
7826 | tree v4si_ftype_v8hi |
7827 | = build_function_type_list (V4SI_type_node, V8HI_type_node, NULL_TREE); | |
7828 | tree int_ftype_v4si_v4si | |
7829 | = build_function_type_list (integer_type_node, | |
7830 | V4SI_type_node, V4SI_type_node, NULL_TREE); | |
7831 | tree int_ftype_v4sf_v4sf | |
7832 | = build_function_type_list (integer_type_node, | |
7833 | V4SF_type_node, V4SF_type_node, NULL_TREE); | |
7834 | tree int_ftype_v16qi_v16qi | |
7835 | = build_function_type_list (integer_type_node, | |
7836 | V16QI_type_node, V16QI_type_node, NULL_TREE); | |
0ac081f6 | 7837 | tree int_ftype_v8hi_v8hi |
b4de2f7d AH |
7838 | = build_function_type_list (integer_type_node, |
7839 | V8HI_type_node, V8HI_type_node, NULL_TREE); | |
0ac081f6 | 7840 | |
6f317ef3 | 7841 | /* Add the simple ternary operators. */ |
2212663f | 7842 | d = (struct builtin_description *) bdesc_3arg; |
ca7558fc | 7843 | for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++) |
2212663f | 7844 | { |
f676971a | 7845 | |
2212663f DB |
7846 | enum machine_mode mode0, mode1, mode2, mode3; |
7847 | tree type; | |
7848 | ||
0559cc77 | 7849 | if (d->name == 0 || d->icode == CODE_FOR_nothing) |
2212663f | 7850 | continue; |
f676971a | 7851 | |
2212663f DB |
7852 | mode0 = insn_data[d->icode].operand[0].mode; |
7853 | mode1 = insn_data[d->icode].operand[1].mode; | |
7854 | mode2 = insn_data[d->icode].operand[2].mode; | |
7855 | mode3 = insn_data[d->icode].operand[3].mode; | |
f676971a | 7856 | |
2212663f DB |
7857 | /* When all four are of the same mode. */ |
7858 | if (mode0 == mode1 && mode1 == mode2 && mode2 == mode3) | |
7859 | { | |
7860 | switch (mode0) | |
7861 | { | |
617e0e1d DB |
7862 | case V4SImode: |
7863 | type = v4si_ftype_v4si_v4si_v4si; | |
7864 | break; | |
2212663f DB |
7865 | case V4SFmode: |
7866 | type = v4sf_ftype_v4sf_v4sf_v4sf; | |
7867 | break; | |
7868 | case V8HImode: | |
7869 | type = v8hi_ftype_v8hi_v8hi_v8hi; | |
f676971a | 7870 | break; |
2212663f DB |
7871 | case V16QImode: |
7872 | type = v16qi_ftype_v16qi_v16qi_v16qi; | |
f676971a | 7873 | break; |
2212663f | 7874 | default: |
37409796 | 7875 | gcc_unreachable (); |
2212663f DB |
7876 | } |
7877 | } | |
7878 | else if (mode0 == mode1 && mode1 == mode2 && mode3 == V16QImode) | |
c4ad648e | 7879 | { |
2212663f DB |
7880 | switch (mode0) |
7881 | { | |
7882 | case V4SImode: | |
7883 | type = v4si_ftype_v4si_v4si_v16qi; | |
7884 | break; | |
7885 | case V4SFmode: | |
7886 | type = v4sf_ftype_v4sf_v4sf_v16qi; | |
7887 | break; | |
7888 | case V8HImode: | |
7889 | type = v8hi_ftype_v8hi_v8hi_v16qi; | |
f676971a | 7890 | break; |
2212663f DB |
7891 | case V16QImode: |
7892 | type = v16qi_ftype_v16qi_v16qi_v16qi; | |
f676971a | 7893 | break; |
2212663f | 7894 | default: |
37409796 | 7895 | gcc_unreachable (); |
2212663f DB |
7896 | } |
7897 | } | |
f676971a | 7898 | else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V16QImode |
2212663f | 7899 | && mode3 == V4SImode) |
24408032 | 7900 | type = v4si_ftype_v16qi_v16qi_v4si; |
f676971a | 7901 | else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V8HImode |
2212663f | 7902 | && mode3 == V4SImode) |
24408032 | 7903 | type = v4si_ftype_v8hi_v8hi_v4si; |
f676971a | 7904 | else if (mode0 == V4SFmode && mode1 == V4SFmode && mode2 == V4SFmode |
617e0e1d | 7905 | && mode3 == V4SImode) |
24408032 AH |
7906 | type = v4sf_ftype_v4sf_v4sf_v4si; |
7907 | ||
7908 | /* vchar, vchar, vchar, 4 bit literal. */ | |
7909 | else if (mode0 == V16QImode && mode1 == mode0 && mode2 == mode0 | |
7910 | && mode3 == QImode) | |
b9e4e5d1 | 7911 | type = v16qi_ftype_v16qi_v16qi_int; |
24408032 AH |
7912 | |
7913 | /* vshort, vshort, vshort, 4 bit literal. */ | |
7914 | else if (mode0 == V8HImode && mode1 == mode0 && mode2 == mode0 | |
7915 | && mode3 == QImode) | |
b9e4e5d1 | 7916 | type = v8hi_ftype_v8hi_v8hi_int; |
24408032 AH |
7917 | |
7918 | /* vint, vint, vint, 4 bit literal. */ | |
7919 | else if (mode0 == V4SImode && mode1 == mode0 && mode2 == mode0 | |
7920 | && mode3 == QImode) | |
b9e4e5d1 | 7921 | type = v4si_ftype_v4si_v4si_int; |
24408032 AH |
7922 | |
7923 | /* vfloat, vfloat, vfloat, 4 bit literal. */ | |
7924 | else if (mode0 == V4SFmode && mode1 == mode0 && mode2 == mode0 | |
7925 | && mode3 == QImode) | |
b9e4e5d1 | 7926 | type = v4sf_ftype_v4sf_v4sf_int; |
24408032 | 7927 | |
2212663f | 7928 | else |
37409796 | 7929 | gcc_unreachable (); |
2212663f DB |
7930 | |
7931 | def_builtin (d->mask, d->name, type, d->code); | |
7932 | } | |
7933 | ||
0ac081f6 | 7934 | /* Add the simple binary operators. */ |
00b960c7 | 7935 | d = (struct builtin_description *) bdesc_2arg; |
ca7558fc | 7936 | for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++) |
0ac081f6 AH |
7937 | { |
7938 | enum machine_mode mode0, mode1, mode2; | |
7939 | tree type; | |
7940 | ||
0559cc77 | 7941 | if (d->name == 0 || d->icode == CODE_FOR_nothing) |
0ac081f6 | 7942 | continue; |
f676971a | 7943 | |
0ac081f6 AH |
7944 | mode0 = insn_data[d->icode].operand[0].mode; |
7945 | mode1 = insn_data[d->icode].operand[1].mode; | |
7946 | mode2 = insn_data[d->icode].operand[2].mode; | |
7947 | ||
7948 | /* When all three operands are of the same mode. */ | |
7949 | if (mode0 == mode1 && mode1 == mode2) | |
7950 | { | |
7951 | switch (mode0) | |
7952 | { | |
7953 | case V4SFmode: | |
7954 | type = v4sf_ftype_v4sf_v4sf; | |
7955 | break; | |
7956 | case V4SImode: | |
7957 | type = v4si_ftype_v4si_v4si; | |
7958 | break; | |
7959 | case V16QImode: | |
7960 | type = v16qi_ftype_v16qi_v16qi; | |
7961 | break; | |
7962 | case V8HImode: | |
7963 | type = v8hi_ftype_v8hi_v8hi; | |
7964 | break; | |
a3170dc6 AH |
7965 | case V2SImode: |
7966 | type = v2si_ftype_v2si_v2si; | |
7967 | break; | |
7968 | case V2SFmode: | |
7969 | type = v2sf_ftype_v2sf_v2sf; | |
7970 | break; | |
7971 | case SImode: | |
7972 | type = int_ftype_int_int; | |
7973 | break; | |
0ac081f6 | 7974 | default: |
37409796 | 7975 | gcc_unreachable (); |
0ac081f6 AH |
7976 | } |
7977 | } | |
7978 | ||
7979 | /* A few other combos we really don't want to do manually. */ | |
7980 | ||
7981 | /* vint, vfloat, vfloat. */ | |
7982 | else if (mode0 == V4SImode && mode1 == V4SFmode && mode2 == V4SFmode) | |
7983 | type = v4si_ftype_v4sf_v4sf; | |
7984 | ||
7985 | /* vshort, vchar, vchar. */ | |
7986 | else if (mode0 == V8HImode && mode1 == V16QImode && mode2 == V16QImode) | |
7987 | type = v8hi_ftype_v16qi_v16qi; | |
7988 | ||
7989 | /* vint, vshort, vshort. */ | |
7990 | else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V8HImode) | |
7991 | type = v4si_ftype_v8hi_v8hi; | |
7992 | ||
7993 | /* vshort, vint, vint. */ | |
7994 | else if (mode0 == V8HImode && mode1 == V4SImode && mode2 == V4SImode) | |
7995 | type = v8hi_ftype_v4si_v4si; | |
7996 | ||
7997 | /* vchar, vshort, vshort. */ | |
7998 | else if (mode0 == V16QImode && mode1 == V8HImode && mode2 == V8HImode) | |
7999 | type = v16qi_ftype_v8hi_v8hi; | |
8000 | ||
8001 | /* vint, vchar, vint. */ | |
8002 | else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V4SImode) | |
8003 | type = v4si_ftype_v16qi_v4si; | |
8004 | ||
fa066a23 AH |
8005 | /* vint, vchar, vchar. */ |
8006 | else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V16QImode) | |
8007 | type = v4si_ftype_v16qi_v16qi; | |
8008 | ||
0ac081f6 AH |
8009 | /* vint, vshort, vint. */ |
8010 | else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V4SImode) | |
8011 | type = v4si_ftype_v8hi_v4si; | |
f676971a | 8012 | |
2212663f DB |
8013 | /* vint, vint, 5 bit literal. */ |
8014 | else if (mode0 == V4SImode && mode1 == V4SImode && mode2 == QImode) | |
b9e4e5d1 | 8015 | type = v4si_ftype_v4si_int; |
f676971a | 8016 | |
2212663f DB |
8017 | /* vshort, vshort, 5 bit literal. */ |
8018 | else if (mode0 == V8HImode && mode1 == V8HImode && mode2 == QImode) | |
b9e4e5d1 | 8019 | type = v8hi_ftype_v8hi_int; |
f676971a | 8020 | |
2212663f DB |
8021 | /* vchar, vchar, 5 bit literal. */ |
8022 | else if (mode0 == V16QImode && mode1 == V16QImode && mode2 == QImode) | |
b9e4e5d1 | 8023 | type = v16qi_ftype_v16qi_int; |
0ac081f6 | 8024 | |
617e0e1d DB |
8025 | /* vfloat, vint, 5 bit literal. */ |
8026 | else if (mode0 == V4SFmode && mode1 == V4SImode && mode2 == QImode) | |
b9e4e5d1 | 8027 | type = v4sf_ftype_v4si_int; |
f676971a | 8028 | |
617e0e1d DB |
8029 | /* vint, vfloat, 5 bit literal. */ |
8030 | else if (mode0 == V4SImode && mode1 == V4SFmode && mode2 == QImode) | |
b9e4e5d1 | 8031 | type = v4si_ftype_v4sf_int; |
617e0e1d | 8032 | |
a3170dc6 AH |
8033 | else if (mode0 == V2SImode && mode1 == SImode && mode2 == SImode) |
8034 | type = v2si_ftype_int_int; | |
8035 | ||
8036 | else if (mode0 == V2SImode && mode1 == V2SImode && mode2 == QImode) | |
8037 | type = v2si_ftype_v2si_char; | |
8038 | ||
8039 | else if (mode0 == V2SImode && mode1 == SImode && mode2 == QImode) | |
8040 | type = v2si_ftype_int_char; | |
8041 | ||
37409796 | 8042 | else |
0ac081f6 | 8043 | { |
37409796 NS |
8044 | /* int, x, x. */ |
8045 | gcc_assert (mode0 == SImode); | |
0ac081f6 AH |
8046 | switch (mode1) |
8047 | { | |
8048 | case V4SImode: | |
8049 | type = int_ftype_v4si_v4si; | |
8050 | break; | |
8051 | case V4SFmode: | |
8052 | type = int_ftype_v4sf_v4sf; | |
8053 | break; | |
8054 | case V16QImode: | |
8055 | type = int_ftype_v16qi_v16qi; | |
8056 | break; | |
8057 | case V8HImode: | |
8058 | type = int_ftype_v8hi_v8hi; | |
8059 | break; | |
8060 | default: | |
37409796 | 8061 | gcc_unreachable (); |
0ac081f6 AH |
8062 | } |
8063 | } | |
8064 | ||
2212663f DB |
8065 | def_builtin (d->mask, d->name, type, d->code); |
8066 | } | |
24408032 | 8067 | |
2212663f DB |
8068 | /* Add the simple unary operators. */ |
8069 | d = (struct builtin_description *) bdesc_1arg; | |
ca7558fc | 8070 | for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++) |
2212663f DB |
8071 | { |
8072 | enum machine_mode mode0, mode1; | |
8073 | tree type; | |
8074 | ||
0559cc77 | 8075 | if (d->name == 0 || d->icode == CODE_FOR_nothing) |
2212663f | 8076 | continue; |
f676971a | 8077 | |
2212663f DB |
8078 | mode0 = insn_data[d->icode].operand[0].mode; |
8079 | mode1 = insn_data[d->icode].operand[1].mode; | |
8080 | ||
8081 | if (mode0 == V4SImode && mode1 == QImode) | |
c4ad648e | 8082 | type = v4si_ftype_int; |
2212663f | 8083 | else if (mode0 == V8HImode && mode1 == QImode) |
c4ad648e | 8084 | type = v8hi_ftype_int; |
2212663f | 8085 | else if (mode0 == V16QImode && mode1 == QImode) |
c4ad648e | 8086 | type = v16qi_ftype_int; |
617e0e1d DB |
8087 | else if (mode0 == V4SFmode && mode1 == V4SFmode) |
8088 | type = v4sf_ftype_v4sf; | |
20e26713 AH |
8089 | else if (mode0 == V8HImode && mode1 == V16QImode) |
8090 | type = v8hi_ftype_v16qi; | |
8091 | else if (mode0 == V4SImode && mode1 == V8HImode) | |
8092 | type = v4si_ftype_v8hi; | |
a3170dc6 AH |
8093 | else if (mode0 == V2SImode && mode1 == V2SImode) |
8094 | type = v2si_ftype_v2si; | |
8095 | else if (mode0 == V2SFmode && mode1 == V2SFmode) | |
8096 | type = v2sf_ftype_v2sf; | |
8097 | else if (mode0 == V2SFmode && mode1 == V2SImode) | |
8098 | type = v2sf_ftype_v2si; | |
8099 | else if (mode0 == V2SImode && mode1 == V2SFmode) | |
8100 | type = v2si_ftype_v2sf; | |
8101 | else if (mode0 == V2SImode && mode1 == QImode) | |
8102 | type = v2si_ftype_char; | |
2212663f | 8103 | else |
37409796 | 8104 | gcc_unreachable (); |
2212663f | 8105 | |
0ac081f6 AH |
8106 | def_builtin (d->mask, d->name, type, d->code); |
8107 | } | |
8108 | } | |
8109 | ||
c15c90bb ZW |
8110 | static void |
8111 | rs6000_init_libfuncs (void) | |
8112 | { | |
8113 | if (!TARGET_HARD_FLOAT) | |
8114 | return; | |
8115 | ||
c9034561 | 8116 | if (DEFAULT_ABI != ABI_V4) |
c15c90bb | 8117 | { |
c9034561 | 8118 | if (TARGET_XCOFF && ! TARGET_POWER2 && ! TARGET_POWERPC) |
c15c90bb | 8119 | { |
c9034561 | 8120 | /* AIX library routines for float->int conversion. */ |
85363ca0 ZW |
8121 | set_conv_libfunc (sfix_optab, SImode, DFmode, "__itrunc"); |
8122 | set_conv_libfunc (ufix_optab, SImode, DFmode, "__uitrunc"); | |
4274207b DE |
8123 | set_conv_libfunc (sfix_optab, SImode, TFmode, "_qitrunc"); |
8124 | set_conv_libfunc (ufix_optab, SImode, TFmode, "_quitrunc"); | |
c15c90bb ZW |
8125 | } |
8126 | ||
98c41d98 DE |
8127 | /* AIX/Darwin/64-bit Linux quad floating point routines. */ |
8128 | if (!TARGET_XL_COMPAT) | |
8129 | { | |
8130 | set_optab_libfunc (add_optab, TFmode, "__gcc_qadd"); | |
8131 | set_optab_libfunc (sub_optab, TFmode, "__gcc_qsub"); | |
8132 | set_optab_libfunc (smul_optab, TFmode, "__gcc_qmul"); | |
8133 | set_optab_libfunc (sdiv_optab, TFmode, "__gcc_qdiv"); | |
8134 | } | |
8135 | else | |
8136 | { | |
8137 | set_optab_libfunc (add_optab, TFmode, "_xlqadd"); | |
8138 | set_optab_libfunc (sub_optab, TFmode, "_xlqsub"); | |
8139 | set_optab_libfunc (smul_optab, TFmode, "_xlqmul"); | |
8140 | set_optab_libfunc (sdiv_optab, TFmode, "_xlqdiv"); | |
8141 | } | |
c15c90bb | 8142 | } |
c9034561 | 8143 | else |
c15c90bb | 8144 | { |
c9034561 | 8145 | /* 32-bit SVR4 quad floating point routines. */ |
c15c90bb ZW |
8146 | |
8147 | set_optab_libfunc (add_optab, TFmode, "_q_add"); | |
8148 | set_optab_libfunc (sub_optab, TFmode, "_q_sub"); | |
8149 | set_optab_libfunc (neg_optab, TFmode, "_q_neg"); | |
8150 | set_optab_libfunc (smul_optab, TFmode, "_q_mul"); | |
8151 | set_optab_libfunc (sdiv_optab, TFmode, "_q_div"); | |
8152 | if (TARGET_PPC_GPOPT || TARGET_POWER2) | |
8153 | set_optab_libfunc (sqrt_optab, TFmode, "_q_sqrt"); | |
8154 | ||
c9034561 ZW |
8155 | set_optab_libfunc (eq_optab, TFmode, "_q_feq"); |
8156 | set_optab_libfunc (ne_optab, TFmode, "_q_fne"); | |
8157 | set_optab_libfunc (gt_optab, TFmode, "_q_fgt"); | |
8158 | set_optab_libfunc (ge_optab, TFmode, "_q_fge"); | |
8159 | set_optab_libfunc (lt_optab, TFmode, "_q_flt"); | |
8160 | set_optab_libfunc (le_optab, TFmode, "_q_fle"); | |
8161 | ||
85363ca0 ZW |
8162 | set_conv_libfunc (sext_optab, TFmode, SFmode, "_q_stoq"); |
8163 | set_conv_libfunc (sext_optab, TFmode, DFmode, "_q_dtoq"); | |
8164 | set_conv_libfunc (trunc_optab, SFmode, TFmode, "_q_qtos"); | |
8165 | set_conv_libfunc (trunc_optab, DFmode, TFmode, "_q_qtod"); | |
8166 | set_conv_libfunc (sfix_optab, SImode, TFmode, "_q_qtoi"); | |
8167 | set_conv_libfunc (ufix_optab, SImode, TFmode, "_q_qtou"); | |
8168 | set_conv_libfunc (sfloat_optab, TFmode, SImode, "_q_itoq"); | |
c15c90bb ZW |
8169 | } |
8170 | } | |
fba73eb1 DE |
8171 | |
8172 | \f | |
8173 | /* Expand a block clear operation, and return 1 if successful. Return 0 | |
8174 | if we should let the compiler generate normal code. | |
8175 | ||
8176 | operands[0] is the destination | |
8177 | operands[1] is the length | |
8178 | operands[2] is the alignment */ | |
8179 | ||
8180 | int | |
8181 | expand_block_clear (rtx operands[]) | |
8182 | { | |
8183 | rtx orig_dest = operands[0]; | |
8184 | rtx bytes_rtx = operands[1]; | |
8185 | rtx align_rtx = operands[2]; | |
5514620a GK |
8186 | bool constp = (GET_CODE (bytes_rtx) == CONST_INT); |
8187 | HOST_WIDE_INT align; | |
8188 | HOST_WIDE_INT bytes; | |
fba73eb1 DE |
8189 | int offset; |
8190 | int clear_bytes; | |
5514620a | 8191 | int clear_step; |
fba73eb1 DE |
8192 | |
8193 | /* If this is not a fixed size move, just call memcpy */ | |
8194 | if (! constp) | |
8195 | return 0; | |
8196 | ||
37409796 NS |
8197 | /* This must be a fixed size alignment */ |
8198 | gcc_assert (GET_CODE (align_rtx) == CONST_INT); | |
fba73eb1 DE |
8199 | align = INTVAL (align_rtx) * BITS_PER_UNIT; |
8200 | ||
8201 | /* Anything to clear? */ | |
8202 | bytes = INTVAL (bytes_rtx); | |
8203 | if (bytes <= 0) | |
8204 | return 1; | |
8205 | ||
5514620a GK |
8206 | /* Use the builtin memset after a point, to avoid huge code bloat. |
8207 | When optimize_size, avoid any significant code bloat; calling | |
8208 | memset is about 4 instructions, so allow for one instruction to | |
8209 | load zero and three to do clearing. */ | |
8210 | if (TARGET_ALTIVEC && align >= 128) | |
8211 | clear_step = 16; | |
8212 | else if (TARGET_POWERPC64 && align >= 32) | |
8213 | clear_step = 8; | |
8214 | else | |
8215 | clear_step = 4; | |
fba73eb1 | 8216 | |
5514620a GK |
8217 | if (optimize_size && bytes > 3 * clear_step) |
8218 | return 0; | |
8219 | if (! optimize_size && bytes > 8 * clear_step) | |
fba73eb1 DE |
8220 | return 0; |
8221 | ||
8222 | for (offset = 0; bytes > 0; offset += clear_bytes, bytes -= clear_bytes) | |
8223 | { | |
fba73eb1 DE |
8224 | enum machine_mode mode = BLKmode; |
8225 | rtx dest; | |
f676971a | 8226 | |
5514620a GK |
8227 | if (bytes >= 16 && TARGET_ALTIVEC && align >= 128) |
8228 | { | |
8229 | clear_bytes = 16; | |
8230 | mode = V4SImode; | |
8231 | } | |
8232 | else if (bytes >= 8 && TARGET_POWERPC64 | |
8233 | /* 64-bit loads and stores require word-aligned | |
8234 | displacements. */ | |
8235 | && (align >= 64 || (!STRICT_ALIGNMENT && align >= 32))) | |
fba73eb1 DE |
8236 | { |
8237 | clear_bytes = 8; | |
8238 | mode = DImode; | |
fba73eb1 | 8239 | } |
5514620a | 8240 | else if (bytes >= 4 && (align >= 32 || !STRICT_ALIGNMENT)) |
fba73eb1 DE |
8241 | { /* move 4 bytes */ |
8242 | clear_bytes = 4; | |
8243 | mode = SImode; | |
fba73eb1 | 8244 | } |
5514620a | 8245 | else if (bytes == 2 && (align >= 16 || !STRICT_ALIGNMENT)) |
fba73eb1 DE |
8246 | { /* move 2 bytes */ |
8247 | clear_bytes = 2; | |
8248 | mode = HImode; | |
fba73eb1 DE |
8249 | } |
8250 | else /* move 1 byte at a time */ | |
8251 | { | |
8252 | clear_bytes = 1; | |
8253 | mode = QImode; | |
fba73eb1 | 8254 | } |
f676971a | 8255 | |
fba73eb1 | 8256 | dest = adjust_address (orig_dest, mode, offset); |
f676971a | 8257 | |
5514620a | 8258 | emit_move_insn (dest, CONST0_RTX (mode)); |
fba73eb1 DE |
8259 | } |
8260 | ||
8261 | return 1; | |
8262 | } | |
8263 | ||
35aff10b | 8264 | \f |
7e69e155 MM |
8265 | /* Expand a block move operation, and return 1 if successful. Return 0 |
8266 | if we should let the compiler generate normal code. | |
8267 | ||
8268 | operands[0] is the destination | |
8269 | operands[1] is the source | |
8270 | operands[2] is the length | |
8271 | operands[3] is the alignment */ | |
8272 | ||
3933e0e1 MM |
8273 | #define MAX_MOVE_REG 4 |
8274 | ||
7e69e155 | 8275 | int |
a2369ed3 | 8276 | expand_block_move (rtx operands[]) |
7e69e155 | 8277 | { |
b6c9286a MM |
8278 | rtx orig_dest = operands[0]; |
8279 | rtx orig_src = operands[1]; | |
7e69e155 | 8280 | rtx bytes_rtx = operands[2]; |
7e69e155 | 8281 | rtx align_rtx = operands[3]; |
3933e0e1 | 8282 | int constp = (GET_CODE (bytes_rtx) == CONST_INT); |
5ee95df6 | 8283 | int align; |
3933e0e1 MM |
8284 | int bytes; |
8285 | int offset; | |
7e69e155 | 8286 | int move_bytes; |
cabfd258 GK |
8287 | rtx stores[MAX_MOVE_REG]; |
8288 | int num_reg = 0; | |
7e69e155 | 8289 | |
3933e0e1 | 8290 | /* If this is not a fixed size move, just call memcpy */ |
cc0d9ba8 | 8291 | if (! constp) |
3933e0e1 MM |
8292 | return 0; |
8293 | ||
37409796 NS |
8294 | /* This must be a fixed size alignment */ |
8295 | gcc_assert (GET_CODE (align_rtx) == CONST_INT); | |
fba73eb1 | 8296 | align = INTVAL (align_rtx) * BITS_PER_UNIT; |
5ee95df6 | 8297 | |
7e69e155 | 8298 | /* Anything to move? */ |
3933e0e1 MM |
8299 | bytes = INTVAL (bytes_rtx); |
8300 | if (bytes <= 0) | |
7e69e155 MM |
8301 | return 1; |
8302 | ||
ea9982a8 | 8303 | /* store_one_arg depends on expand_block_move to handle at least the size of |
f676971a | 8304 | reg_parm_stack_space. */ |
ea9982a8 | 8305 | if (bytes > (TARGET_POWERPC64 ? 64 : 32)) |
7e69e155 MM |
8306 | return 0; |
8307 | ||
cabfd258 | 8308 | for (offset = 0; bytes > 0; offset += move_bytes, bytes -= move_bytes) |
7e69e155 | 8309 | { |
cabfd258 | 8310 | union { |
70128ad9 | 8311 | rtx (*movmemsi) (rtx, rtx, rtx, rtx); |
a2369ed3 | 8312 | rtx (*mov) (rtx, rtx); |
cabfd258 GK |
8313 | } gen_func; |
8314 | enum machine_mode mode = BLKmode; | |
8315 | rtx src, dest; | |
f676971a | 8316 | |
5514620a GK |
8317 | /* Altivec first, since it will be faster than a string move |
8318 | when it applies, and usually not significantly larger. */ | |
8319 | if (TARGET_ALTIVEC && bytes >= 16 && align >= 128) | |
8320 | { | |
8321 | move_bytes = 16; | |
8322 | mode = V4SImode; | |
8323 | gen_func.mov = gen_movv4si; | |
8324 | } | |
8325 | else if (TARGET_STRING | |
cabfd258 GK |
8326 | && bytes > 24 /* move up to 32 bytes at a time */ |
8327 | && ! fixed_regs[5] | |
8328 | && ! fixed_regs[6] | |
8329 | && ! fixed_regs[7] | |
8330 | && ! fixed_regs[8] | |
8331 | && ! fixed_regs[9] | |
8332 | && ! fixed_regs[10] | |
8333 | && ! fixed_regs[11] | |
8334 | && ! fixed_regs[12]) | |
7e69e155 | 8335 | { |
cabfd258 | 8336 | move_bytes = (bytes > 32) ? 32 : bytes; |
70128ad9 | 8337 | gen_func.movmemsi = gen_movmemsi_8reg; |
cabfd258 GK |
8338 | } |
8339 | else if (TARGET_STRING | |
8340 | && bytes > 16 /* move up to 24 bytes at a time */ | |
8341 | && ! fixed_regs[5] | |
8342 | && ! fixed_regs[6] | |
8343 | && ! fixed_regs[7] | |
8344 | && ! fixed_regs[8] | |
8345 | && ! fixed_regs[9] | |
8346 | && ! fixed_regs[10]) | |
8347 | { | |
8348 | move_bytes = (bytes > 24) ? 24 : bytes; | |
70128ad9 | 8349 | gen_func.movmemsi = gen_movmemsi_6reg; |
cabfd258 GK |
8350 | } |
8351 | else if (TARGET_STRING | |
8352 | && bytes > 8 /* move up to 16 bytes at a time */ | |
8353 | && ! fixed_regs[5] | |
8354 | && ! fixed_regs[6] | |
8355 | && ! fixed_regs[7] | |
8356 | && ! fixed_regs[8]) | |
8357 | { | |
8358 | move_bytes = (bytes > 16) ? 16 : bytes; | |
70128ad9 | 8359 | gen_func.movmemsi = gen_movmemsi_4reg; |
cabfd258 GK |
8360 | } |
8361 | else if (bytes >= 8 && TARGET_POWERPC64 | |
8362 | /* 64-bit loads and stores require word-aligned | |
8363 | displacements. */ | |
fba73eb1 | 8364 | && (align >= 64 || (!STRICT_ALIGNMENT && align >= 32))) |
cabfd258 GK |
8365 | { |
8366 | move_bytes = 8; | |
8367 | mode = DImode; | |
8368 | gen_func.mov = gen_movdi; | |
8369 | } | |
8370 | else if (TARGET_STRING && bytes > 4 && !TARGET_POWERPC64) | |
8371 | { /* move up to 8 bytes at a time */ | |
8372 | move_bytes = (bytes > 8) ? 8 : bytes; | |
70128ad9 | 8373 | gen_func.movmemsi = gen_movmemsi_2reg; |
cabfd258 | 8374 | } |
cd7d9ca4 | 8375 | else if (bytes >= 4 && (align >= 32 || !STRICT_ALIGNMENT)) |
cabfd258 GK |
8376 | { /* move 4 bytes */ |
8377 | move_bytes = 4; | |
8378 | mode = SImode; | |
8379 | gen_func.mov = gen_movsi; | |
8380 | } | |
cd7d9ca4 | 8381 | else if (bytes == 2 && (align >= 16 || !STRICT_ALIGNMENT)) |
cabfd258 GK |
8382 | { /* move 2 bytes */ |
8383 | move_bytes = 2; | |
8384 | mode = HImode; | |
8385 | gen_func.mov = gen_movhi; | |
8386 | } | |
8387 | else if (TARGET_STRING && bytes > 1) | |
8388 | { /* move up to 4 bytes at a time */ | |
8389 | move_bytes = (bytes > 4) ? 4 : bytes; | |
70128ad9 | 8390 | gen_func.movmemsi = gen_movmemsi_1reg; |
cabfd258 GK |
8391 | } |
8392 | else /* move 1 byte at a time */ | |
8393 | { | |
8394 | move_bytes = 1; | |
8395 | mode = QImode; | |
8396 | gen_func.mov = gen_movqi; | |
8397 | } | |
f676971a | 8398 | |
cabfd258 GK |
8399 | src = adjust_address (orig_src, mode, offset); |
8400 | dest = adjust_address (orig_dest, mode, offset); | |
f676971a EC |
8401 | |
8402 | if (mode != BLKmode) | |
cabfd258 GK |
8403 | { |
8404 | rtx tmp_reg = gen_reg_rtx (mode); | |
f676971a | 8405 | |
cabfd258 GK |
8406 | emit_insn ((*gen_func.mov) (tmp_reg, src)); |
8407 | stores[num_reg++] = (*gen_func.mov) (dest, tmp_reg); | |
4c64a852 | 8408 | } |
3933e0e1 | 8409 | |
cabfd258 GK |
8410 | if (mode == BLKmode || num_reg >= MAX_MOVE_REG || bytes == move_bytes) |
8411 | { | |
8412 | int i; | |
8413 | for (i = 0; i < num_reg; i++) | |
8414 | emit_insn (stores[i]); | |
8415 | num_reg = 0; | |
8416 | } | |
35aff10b | 8417 | |
cabfd258 | 8418 | if (mode == BLKmode) |
7e69e155 | 8419 | { |
70128ad9 | 8420 | /* Move the address into scratch registers. The movmemsi |
cabfd258 GK |
8421 | patterns require zero offset. */ |
8422 | if (!REG_P (XEXP (src, 0))) | |
b6c9286a | 8423 | { |
cabfd258 GK |
8424 | rtx src_reg = copy_addr_to_reg (XEXP (src, 0)); |
8425 | src = replace_equiv_address (src, src_reg); | |
b6c9286a | 8426 | } |
cabfd258 | 8427 | set_mem_size (src, GEN_INT (move_bytes)); |
f676971a | 8428 | |
cabfd258 | 8429 | if (!REG_P (XEXP (dest, 0))) |
3933e0e1 | 8430 | { |
cabfd258 GK |
8431 | rtx dest_reg = copy_addr_to_reg (XEXP (dest, 0)); |
8432 | dest = replace_equiv_address (dest, dest_reg); | |
7e69e155 | 8433 | } |
cabfd258 | 8434 | set_mem_size (dest, GEN_INT (move_bytes)); |
f676971a | 8435 | |
70128ad9 | 8436 | emit_insn ((*gen_func.movmemsi) (dest, src, |
cabfd258 GK |
8437 | GEN_INT (move_bytes & 31), |
8438 | align_rtx)); | |
7e69e155 | 8439 | } |
7e69e155 MM |
8440 | } |
8441 | ||
8442 | return 1; | |
8443 | } | |
8444 | ||
d62294f5 | 8445 | \f |
9caa3eb2 DE |
8446 | /* Return a string to perform a load_multiple operation. |
8447 | operands[0] is the vector. | |
8448 | operands[1] is the source address. | |
8449 | operands[2] is the first destination register. */ | |
8450 | ||
8451 | const char * | |
a2369ed3 | 8452 | rs6000_output_load_multiple (rtx operands[3]) |
9caa3eb2 DE |
8453 | { |
8454 | /* We have to handle the case where the pseudo used to contain the address | |
8455 | is assigned to one of the output registers. */ | |
8456 | int i, j; | |
8457 | int words = XVECLEN (operands[0], 0); | |
8458 | rtx xop[10]; | |
8459 | ||
8460 | if (XVECLEN (operands[0], 0) == 1) | |
8461 | return "{l|lwz} %2,0(%1)"; | |
8462 | ||
8463 | for (i = 0; i < words; i++) | |
8464 | if (refers_to_regno_p (REGNO (operands[2]) + i, | |
8465 | REGNO (operands[2]) + i + 1, operands[1], 0)) | |
8466 | { | |
8467 | if (i == words-1) | |
8468 | { | |
8469 | xop[0] = GEN_INT (4 * (words-1)); | |
8470 | xop[1] = operands[1]; | |
8471 | xop[2] = operands[2]; | |
8472 | output_asm_insn ("{lsi|lswi} %2,%1,%0\n\t{l|lwz} %1,%0(%1)", xop); | |
8473 | return ""; | |
8474 | } | |
8475 | else if (i == 0) | |
8476 | { | |
8477 | xop[0] = GEN_INT (4 * (words-1)); | |
8478 | xop[1] = operands[1]; | |
8479 | xop[2] = gen_rtx_REG (SImode, REGNO (operands[2]) + 1); | |
8480 | output_asm_insn ("{cal %1,4(%1)|addi %1,%1,4}\n\t{lsi|lswi} %2,%1,%0\n\t{l|lwz} %1,-4(%1)", xop); | |
8481 | return ""; | |
8482 | } | |
8483 | else | |
8484 | { | |
8485 | for (j = 0; j < words; j++) | |
8486 | if (j != i) | |
8487 | { | |
8488 | xop[0] = GEN_INT (j * 4); | |
8489 | xop[1] = operands[1]; | |
8490 | xop[2] = gen_rtx_REG (SImode, REGNO (operands[2]) + j); | |
8491 | output_asm_insn ("{l|lwz} %2,%0(%1)", xop); | |
8492 | } | |
8493 | xop[0] = GEN_INT (i * 4); | |
8494 | xop[1] = operands[1]; | |
8495 | output_asm_insn ("{l|lwz} %1,%0(%1)", xop); | |
8496 | return ""; | |
8497 | } | |
8498 | } | |
8499 | ||
8500 | return "{lsi|lswi} %2,%1,%N0"; | |
8501 | } | |
8502 | ||
9878760c | 8503 | \f |
a4f6c312 SS |
8504 | /* A validation routine: say whether CODE, a condition code, and MODE |
8505 | match. The other alternatives either don't make sense or should | |
8506 | never be generated. */ | |
39a10a29 | 8507 | |
48d72335 | 8508 | void |
a2369ed3 | 8509 | validate_condition_mode (enum rtx_code code, enum machine_mode mode) |
39a10a29 | 8510 | { |
37409796 NS |
8511 | gcc_assert ((GET_RTX_CLASS (code) == RTX_COMPARE |
8512 | || GET_RTX_CLASS (code) == RTX_COMM_COMPARE) | |
8513 | && GET_MODE_CLASS (mode) == MODE_CC); | |
39a10a29 GK |
8514 | |
8515 | /* These don't make sense. */ | |
37409796 NS |
8516 | gcc_assert ((code != GT && code != LT && code != GE && code != LE) |
8517 | || mode != CCUNSmode); | |
39a10a29 | 8518 | |
37409796 NS |
8519 | gcc_assert ((code != GTU && code != LTU && code != GEU && code != LEU) |
8520 | || mode == CCUNSmode); | |
39a10a29 | 8521 | |
37409796 NS |
8522 | gcc_assert (mode == CCFPmode |
8523 | || (code != ORDERED && code != UNORDERED | |
8524 | && code != UNEQ && code != LTGT | |
8525 | && code != UNGT && code != UNLT | |
8526 | && code != UNGE && code != UNLE)); | |
f676971a EC |
8527 | |
8528 | /* These should never be generated except for | |
bc9ec0e0 | 8529 | flag_finite_math_only. */ |
37409796 NS |
8530 | gcc_assert (mode != CCFPmode |
8531 | || flag_finite_math_only | |
8532 | || (code != LE && code != GE | |
8533 | && code != UNEQ && code != LTGT | |
8534 | && code != UNGT && code != UNLT)); | |
39a10a29 GK |
8535 | |
8536 | /* These are invalid; the information is not there. */ | |
37409796 | 8537 | gcc_assert (mode != CCEQmode || code == EQ || code == NE); |
39a10a29 GK |
8538 | } |
8539 | ||
9878760c RK |
8540 | \f |
8541 | /* Return 1 if ANDOP is a mask that has no bits on that are not in the | |
8542 | mask required to convert the result of a rotate insn into a shift | |
b1765bde | 8543 | left insn of SHIFTOP bits. Both are known to be SImode CONST_INT. */ |
9878760c RK |
8544 | |
8545 | int | |
a2369ed3 | 8546 | includes_lshift_p (rtx shiftop, rtx andop) |
9878760c | 8547 | { |
e2c953b6 DE |
8548 | unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0; |
8549 | ||
8550 | shift_mask <<= INTVAL (shiftop); | |
9878760c | 8551 | |
b1765bde | 8552 | return (INTVAL (andop) & 0xffffffff & ~shift_mask) == 0; |
9878760c RK |
8553 | } |
8554 | ||
8555 | /* Similar, but for right shift. */ | |
8556 | ||
8557 | int | |
a2369ed3 | 8558 | includes_rshift_p (rtx shiftop, rtx andop) |
9878760c | 8559 | { |
a7653a2c | 8560 | unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0; |
9878760c RK |
8561 | |
8562 | shift_mask >>= INTVAL (shiftop); | |
8563 | ||
b1765bde | 8564 | return (INTVAL (andop) & 0xffffffff & ~shift_mask) == 0; |
e2c953b6 DE |
8565 | } |
8566 | ||
c5059423 AM |
8567 | /* Return 1 if ANDOP is a mask suitable for use with an rldic insn |
8568 | to perform a left shift. It must have exactly SHIFTOP least | |
b6d08ca1 | 8569 | significant 0's, then one or more 1's, then zero or more 0's. */ |
e2c953b6 DE |
8570 | |
8571 | int | |
a2369ed3 | 8572 | includes_rldic_lshift_p (rtx shiftop, rtx andop) |
e2c953b6 | 8573 | { |
c5059423 AM |
8574 | if (GET_CODE (andop) == CONST_INT) |
8575 | { | |
02071907 | 8576 | HOST_WIDE_INT c, lsb, shift_mask; |
e2c953b6 | 8577 | |
c5059423 | 8578 | c = INTVAL (andop); |
02071907 | 8579 | if (c == 0 || c == ~0) |
c5059423 | 8580 | return 0; |
e2c953b6 | 8581 | |
02071907 | 8582 | shift_mask = ~0; |
c5059423 AM |
8583 | shift_mask <<= INTVAL (shiftop); |
8584 | ||
b6d08ca1 | 8585 | /* Find the least significant one bit. */ |
c5059423 AM |
8586 | lsb = c & -c; |
8587 | ||
8588 | /* It must coincide with the LSB of the shift mask. */ | |
8589 | if (-lsb != shift_mask) | |
8590 | return 0; | |
e2c953b6 | 8591 | |
c5059423 AM |
8592 | /* Invert to look for the next transition (if any). */ |
8593 | c = ~c; | |
8594 | ||
8595 | /* Remove the low group of ones (originally low group of zeros). */ | |
8596 | c &= -lsb; | |
8597 | ||
8598 | /* Again find the lsb, and check we have all 1's above. */ | |
8599 | lsb = c & -c; | |
8600 | return c == -lsb; | |
8601 | } | |
8602 | else if (GET_CODE (andop) == CONST_DOUBLE | |
8603 | && (GET_MODE (andop) == VOIDmode || GET_MODE (andop) == DImode)) | |
8604 | { | |
02071907 AM |
8605 | HOST_WIDE_INT low, high, lsb; |
8606 | HOST_WIDE_INT shift_mask_low, shift_mask_high; | |
c5059423 AM |
8607 | |
8608 | low = CONST_DOUBLE_LOW (andop); | |
8609 | if (HOST_BITS_PER_WIDE_INT < 64) | |
8610 | high = CONST_DOUBLE_HIGH (andop); | |
8611 | ||
8612 | if ((low == 0 && (HOST_BITS_PER_WIDE_INT >= 64 || high == 0)) | |
02071907 | 8613 | || (low == ~0 && (HOST_BITS_PER_WIDE_INT >= 64 || high == ~0))) |
c5059423 AM |
8614 | return 0; |
8615 | ||
8616 | if (HOST_BITS_PER_WIDE_INT < 64 && low == 0) | |
8617 | { | |
02071907 | 8618 | shift_mask_high = ~0; |
c5059423 AM |
8619 | if (INTVAL (shiftop) > 32) |
8620 | shift_mask_high <<= INTVAL (shiftop) - 32; | |
8621 | ||
8622 | lsb = high & -high; | |
8623 | ||
8624 | if (-lsb != shift_mask_high || INTVAL (shiftop) < 32) | |
8625 | return 0; | |
8626 | ||
8627 | high = ~high; | |
8628 | high &= -lsb; | |
8629 | ||
8630 | lsb = high & -high; | |
8631 | return high == -lsb; | |
8632 | } | |
8633 | ||
02071907 | 8634 | shift_mask_low = ~0; |
c5059423 AM |
8635 | shift_mask_low <<= INTVAL (shiftop); |
8636 | ||
8637 | lsb = low & -low; | |
8638 | ||
8639 | if (-lsb != shift_mask_low) | |
8640 | return 0; | |
8641 | ||
8642 | if (HOST_BITS_PER_WIDE_INT < 64) | |
8643 | high = ~high; | |
8644 | low = ~low; | |
8645 | low &= -lsb; | |
8646 | ||
8647 | if (HOST_BITS_PER_WIDE_INT < 64 && low == 0) | |
8648 | { | |
8649 | lsb = high & -high; | |
8650 | return high == -lsb; | |
8651 | } | |
8652 | ||
8653 | lsb = low & -low; | |
8654 | return low == -lsb && (HOST_BITS_PER_WIDE_INT >= 64 || high == ~0); | |
8655 | } | |
8656 | else | |
8657 | return 0; | |
8658 | } | |
e2c953b6 | 8659 | |
c5059423 AM |
8660 | /* Return 1 if ANDOP is a mask suitable for use with an rldicr insn |
8661 | to perform a left shift. It must have SHIFTOP or more least | |
c1207243 | 8662 | significant 0's, with the remainder of the word 1's. */ |
e2c953b6 | 8663 | |
c5059423 | 8664 | int |
a2369ed3 | 8665 | includes_rldicr_lshift_p (rtx shiftop, rtx andop) |
c5059423 | 8666 | { |
e2c953b6 | 8667 | if (GET_CODE (andop) == CONST_INT) |
c5059423 | 8668 | { |
02071907 | 8669 | HOST_WIDE_INT c, lsb, shift_mask; |
c5059423 | 8670 | |
02071907 | 8671 | shift_mask = ~0; |
c5059423 AM |
8672 | shift_mask <<= INTVAL (shiftop); |
8673 | c = INTVAL (andop); | |
8674 | ||
c1207243 | 8675 | /* Find the least significant one bit. */ |
c5059423 AM |
8676 | lsb = c & -c; |
8677 | ||
8678 | /* It must be covered by the shift mask. | |
a4f6c312 | 8679 | This test also rejects c == 0. */ |
c5059423 AM |
8680 | if ((lsb & shift_mask) == 0) |
8681 | return 0; | |
8682 | ||
8683 | /* Check we have all 1's above the transition, and reject all 1's. */ | |
8684 | return c == -lsb && lsb != 1; | |
8685 | } | |
8686 | else if (GET_CODE (andop) == CONST_DOUBLE | |
8687 | && (GET_MODE (andop) == VOIDmode || GET_MODE (andop) == DImode)) | |
8688 | { | |
02071907 | 8689 | HOST_WIDE_INT low, lsb, shift_mask_low; |
c5059423 AM |
8690 | |
8691 | low = CONST_DOUBLE_LOW (andop); | |
8692 | ||
8693 | if (HOST_BITS_PER_WIDE_INT < 64) | |
8694 | { | |
02071907 | 8695 | HOST_WIDE_INT high, shift_mask_high; |
c5059423 AM |
8696 | |
8697 | high = CONST_DOUBLE_HIGH (andop); | |
8698 | ||
8699 | if (low == 0) | |
8700 | { | |
02071907 | 8701 | shift_mask_high = ~0; |
c5059423 AM |
8702 | if (INTVAL (shiftop) > 32) |
8703 | shift_mask_high <<= INTVAL (shiftop) - 32; | |
8704 | ||
8705 | lsb = high & -high; | |
8706 | ||
8707 | if ((lsb & shift_mask_high) == 0) | |
8708 | return 0; | |
8709 | ||
8710 | return high == -lsb; | |
8711 | } | |
8712 | if (high != ~0) | |
8713 | return 0; | |
8714 | } | |
8715 | ||
02071907 | 8716 | shift_mask_low = ~0; |
c5059423 AM |
8717 | shift_mask_low <<= INTVAL (shiftop); |
8718 | ||
8719 | lsb = low & -low; | |
8720 | ||
8721 | if ((lsb & shift_mask_low) == 0) | |
8722 | return 0; | |
8723 | ||
8724 | return low == -lsb && lsb != 1; | |
8725 | } | |
e2c953b6 | 8726 | else |
c5059423 | 8727 | return 0; |
9878760c | 8728 | } |
35068b43 | 8729 | |
11ac38b2 DE |
8730 | /* Return 1 if operands will generate a valid arguments to rlwimi |
8731 | instruction for insert with right shift in 64-bit mode. The mask may | |
8732 | not start on the first bit or stop on the last bit because wrap-around | |
8733 | effects of instruction do not correspond to semantics of RTL insn. */ | |
8734 | ||
8735 | int | |
8736 | insvdi_rshift_rlwimi_p (rtx sizeop, rtx startop, rtx shiftop) | |
8737 | { | |
8738 | if (INTVAL (startop) < 64 | |
8739 | && INTVAL (startop) > 32 | |
8740 | && (INTVAL (sizeop) + INTVAL (startop) < 64) | |
8741 | && (INTVAL (sizeop) + INTVAL (startop) > 33) | |
8742 | && (INTVAL (sizeop) + INTVAL (startop) + INTVAL (shiftop) < 96) | |
8743 | && (INTVAL (sizeop) + INTVAL (startop) + INTVAL (shiftop) >= 64) | |
8744 | && (64 - (INTVAL (shiftop) & 63)) >= INTVAL (sizeop)) | |
8745 | return 1; | |
8746 | ||
8747 | return 0; | |
8748 | } | |
8749 | ||
35068b43 | 8750 | /* Return 1 if REGNO (reg1) == REGNO (reg2) - 1 making them candidates |
90f81f99 | 8751 | for lfq and stfq insns iff the registers are hard registers. */ |
35068b43 RK |
8752 | |
8753 | int | |
a2369ed3 | 8754 | registers_ok_for_quad_peep (rtx reg1, rtx reg2) |
35068b43 RK |
8755 | { |
8756 | /* We might have been passed a SUBREG. */ | |
f676971a | 8757 | if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG) |
35068b43 | 8758 | return 0; |
f676971a | 8759 | |
90f81f99 AP |
8760 | /* We might have been passed non floating point registers. */ |
8761 | if (!FP_REGNO_P (REGNO (reg1)) | |
8762 | || !FP_REGNO_P (REGNO (reg2))) | |
8763 | return 0; | |
35068b43 RK |
8764 | |
8765 | return (REGNO (reg1) == REGNO (reg2) - 1); | |
8766 | } | |
8767 | ||
a4f6c312 SS |
8768 | /* Return 1 if addr1 and addr2 are suitable for lfq or stfq insn. |
8769 | addr1 and addr2 must be in consecutive memory locations | |
8770 | (addr2 == addr1 + 8). */ | |
35068b43 RK |
8771 | |
8772 | int | |
90f81f99 | 8773 | mems_ok_for_quad_peep (rtx mem1, rtx mem2) |
35068b43 | 8774 | { |
90f81f99 | 8775 | rtx addr1, addr2; |
e2c953b6 | 8776 | unsigned int reg1; |
35068b43 RK |
8777 | int offset1; |
8778 | ||
90f81f99 AP |
8779 | /* The mems cannot be volatile. */ |
8780 | if (MEM_VOLATILE_P (mem1) || MEM_VOLATILE_P (mem2)) | |
8781 | return 0; | |
f676971a | 8782 | |
90f81f99 AP |
8783 | addr1 = XEXP (mem1, 0); |
8784 | addr2 = XEXP (mem2, 0); | |
8785 | ||
35068b43 RK |
8786 | /* Extract an offset (if used) from the first addr. */ |
8787 | if (GET_CODE (addr1) == PLUS) | |
8788 | { | |
8789 | /* If not a REG, return zero. */ | |
8790 | if (GET_CODE (XEXP (addr1, 0)) != REG) | |
8791 | return 0; | |
8792 | else | |
8793 | { | |
c4ad648e | 8794 | reg1 = REGNO (XEXP (addr1, 0)); |
35068b43 RK |
8795 | /* The offset must be constant! */ |
8796 | if (GET_CODE (XEXP (addr1, 1)) != CONST_INT) | |
c4ad648e AM |
8797 | return 0; |
8798 | offset1 = INTVAL (XEXP (addr1, 1)); | |
35068b43 RK |
8799 | } |
8800 | } | |
8801 | else if (GET_CODE (addr1) != REG) | |
8802 | return 0; | |
8803 | else | |
8804 | { | |
8805 | reg1 = REGNO (addr1); | |
8806 | /* This was a simple (mem (reg)) expression. Offset is 0. */ | |
8807 | offset1 = 0; | |
8808 | } | |
8809 | ||
a2369ed3 | 8810 | /* Make sure the second address is a (mem (plus (reg) (const_int))) |
f676971a | 8811 | or if it is (mem (reg)) then make sure that offset1 is -8 and the same |
0f6937fe | 8812 | register as addr1. */ |
984e25ac | 8813 | if (offset1 == -8 && GET_CODE (addr2) == REG && reg1 == REGNO (addr2)) |
0f6937fe | 8814 | return 1; |
35068b43 RK |
8815 | if (GET_CODE (addr2) != PLUS) |
8816 | return 0; | |
8817 | ||
8818 | if (GET_CODE (XEXP (addr2, 0)) != REG | |
8819 | || GET_CODE (XEXP (addr2, 1)) != CONST_INT) | |
8820 | return 0; | |
8821 | ||
8822 | if (reg1 != REGNO (XEXP (addr2, 0))) | |
8823 | return 0; | |
8824 | ||
8825 | /* The offset for the second addr must be 8 more than the first addr. */ | |
8826 | if (INTVAL (XEXP (addr2, 1)) != offset1 + 8) | |
8827 | return 0; | |
8828 | ||
8829 | /* All the tests passed. addr1 and addr2 are valid for lfq or stfq | |
8830 | instructions. */ | |
8831 | return 1; | |
8832 | } | |
9878760c RK |
8833 | \f |
8834 | /* Return the register class of a scratch register needed to copy IN into | |
8835 | or out of a register in CLASS in MODE. If it can be done directly, | |
8836 | NO_REGS is returned. */ | |
8837 | ||
8838 | enum reg_class | |
f676971a | 8839 | secondary_reload_class (enum reg_class class, |
a9baceb1 GK |
8840 | enum machine_mode mode ATTRIBUTE_UNUSED, |
8841 | rtx in) | |
9878760c | 8842 | { |
5accd822 | 8843 | int regno; |
9878760c | 8844 | |
ab82a49f AP |
8845 | if (TARGET_ELF || (DEFAULT_ABI == ABI_DARWIN |
8846 | #if TARGET_MACHO | |
c4ad648e | 8847 | && MACHOPIC_INDIRECT |
ab82a49f | 8848 | #endif |
c4ad648e | 8849 | )) |
46fad5b7 DJ |
8850 | { |
8851 | /* We cannot copy a symbolic operand directly into anything | |
c4ad648e AM |
8852 | other than BASE_REGS for TARGET_ELF. So indicate that a |
8853 | register from BASE_REGS is needed as an intermediate | |
8854 | register. | |
f676971a | 8855 | |
46fad5b7 DJ |
8856 | On Darwin, pic addresses require a load from memory, which |
8857 | needs a base register. */ | |
8858 | if (class != BASE_REGS | |
c4ad648e AM |
8859 | && (GET_CODE (in) == SYMBOL_REF |
8860 | || GET_CODE (in) == HIGH | |
8861 | || GET_CODE (in) == LABEL_REF | |
8862 | || GET_CODE (in) == CONST)) | |
8863 | return BASE_REGS; | |
46fad5b7 | 8864 | } |
e7b7998a | 8865 | |
5accd822 DE |
8866 | if (GET_CODE (in) == REG) |
8867 | { | |
8868 | regno = REGNO (in); | |
8869 | if (regno >= FIRST_PSEUDO_REGISTER) | |
8870 | { | |
8871 | regno = true_regnum (in); | |
8872 | if (regno >= FIRST_PSEUDO_REGISTER) | |
8873 | regno = -1; | |
8874 | } | |
8875 | } | |
8876 | else if (GET_CODE (in) == SUBREG) | |
8877 | { | |
8878 | regno = true_regnum (in); | |
8879 | if (regno >= FIRST_PSEUDO_REGISTER) | |
8880 | regno = -1; | |
8881 | } | |
8882 | else | |
8883 | regno = -1; | |
8884 | ||
9878760c RK |
8885 | /* We can place anything into GENERAL_REGS and can put GENERAL_REGS |
8886 | into anything. */ | |
8887 | if (class == GENERAL_REGS || class == BASE_REGS | |
8888 | || (regno >= 0 && INT_REGNO_P (regno))) | |
8889 | return NO_REGS; | |
8890 | ||
8891 | /* Constants, memory, and FP registers can go into FP registers. */ | |
8892 | if ((regno == -1 || FP_REGNO_P (regno)) | |
8893 | && (class == FLOAT_REGS || class == NON_SPECIAL_REGS)) | |
8894 | return NO_REGS; | |
8895 | ||
0ac081f6 AH |
8896 | /* Memory, and AltiVec registers can go into AltiVec registers. */ |
8897 | if ((regno == -1 || ALTIVEC_REGNO_P (regno)) | |
8898 | && class == ALTIVEC_REGS) | |
8899 | return NO_REGS; | |
8900 | ||
9878760c RK |
8901 | /* We can copy among the CR registers. */ |
8902 | if ((class == CR_REGS || class == CR0_REGS) | |
8903 | && regno >= 0 && CR_REGNO_P (regno)) | |
8904 | return NO_REGS; | |
8905 | ||
8906 | /* Otherwise, we need GENERAL_REGS. */ | |
8907 | return GENERAL_REGS; | |
8908 | } | |
8909 | \f | |
8910 | /* Given a comparison operation, return the bit number in CCR to test. We | |
f676971a | 8911 | know this is a valid comparison. |
9878760c RK |
8912 | |
8913 | SCC_P is 1 if this is for an scc. That means that %D will have been | |
8914 | used instead of %C, so the bits will be in different places. | |
8915 | ||
b4ac57ab | 8916 | Return -1 if OP isn't a valid comparison for some reason. */ |
9878760c RK |
8917 | |
8918 | int | |
a2369ed3 | 8919 | ccr_bit (rtx op, int scc_p) |
9878760c RK |
8920 | { |
8921 | enum rtx_code code = GET_CODE (op); | |
8922 | enum machine_mode cc_mode; | |
8923 | int cc_regnum; | |
8924 | int base_bit; | |
9ebbca7d | 8925 | rtx reg; |
9878760c | 8926 | |
ec8e098d | 8927 | if (!COMPARISON_P (op)) |
9878760c RK |
8928 | return -1; |
8929 | ||
9ebbca7d GK |
8930 | reg = XEXP (op, 0); |
8931 | ||
37409796 | 8932 | gcc_assert (GET_CODE (reg) == REG && CR_REGNO_P (REGNO (reg))); |
9ebbca7d GK |
8933 | |
8934 | cc_mode = GET_MODE (reg); | |
8935 | cc_regnum = REGNO (reg); | |
8936 | base_bit = 4 * (cc_regnum - CR0_REGNO); | |
9878760c | 8937 | |
39a10a29 | 8938 | validate_condition_mode (code, cc_mode); |
c5defebb | 8939 | |
b7053a3f GK |
8940 | /* When generating a sCOND operation, only positive conditions are |
8941 | allowed. */ | |
37409796 NS |
8942 | gcc_assert (!scc_p |
8943 | || code == EQ || code == GT || code == LT || code == UNORDERED | |
8944 | || code == GTU || code == LTU); | |
f676971a | 8945 | |
9878760c RK |
8946 | switch (code) |
8947 | { | |
8948 | case NE: | |
8949 | return scc_p ? base_bit + 3 : base_bit + 2; | |
8950 | case EQ: | |
8951 | return base_bit + 2; | |
1c882ea4 | 8952 | case GT: case GTU: case UNLE: |
9878760c | 8953 | return base_bit + 1; |
1c882ea4 | 8954 | case LT: case LTU: case UNGE: |
9878760c | 8955 | return base_bit; |
1c882ea4 GK |
8956 | case ORDERED: case UNORDERED: |
8957 | return base_bit + 3; | |
9878760c RK |
8958 | |
8959 | case GE: case GEU: | |
39a10a29 | 8960 | /* If scc, we will have done a cror to put the bit in the |
9878760c RK |
8961 | unordered position. So test that bit. For integer, this is ! LT |
8962 | unless this is an scc insn. */ | |
39a10a29 | 8963 | return scc_p ? base_bit + 3 : base_bit; |
9878760c RK |
8964 | |
8965 | case LE: case LEU: | |
39a10a29 | 8966 | return scc_p ? base_bit + 3 : base_bit + 1; |
1c882ea4 | 8967 | |
9878760c | 8968 | default: |
37409796 | 8969 | gcc_unreachable (); |
9878760c RK |
8970 | } |
8971 | } | |
1ff7789b | 8972 | \f |
8d30c4ee | 8973 | /* Return the GOT register. */ |
1ff7789b | 8974 | |
9390387d | 8975 | rtx |
a2369ed3 | 8976 | rs6000_got_register (rtx value ATTRIBUTE_UNUSED) |
1ff7789b | 8977 | { |
a4f6c312 SS |
8978 | /* The second flow pass currently (June 1999) can't update |
8979 | regs_ever_live without disturbing other parts of the compiler, so | |
8980 | update it here to make the prolog/epilogue code happy. */ | |
1db02437 FS |
8981 | if (no_new_pseudos && ! regs_ever_live[RS6000_PIC_OFFSET_TABLE_REGNUM]) |
8982 | regs_ever_live[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1; | |
1ff7789b | 8983 | |
8d30c4ee | 8984 | current_function_uses_pic_offset_table = 1; |
3cb999d8 | 8985 | |
1ff7789b MM |
8986 | return pic_offset_table_rtx; |
8987 | } | |
a7df97e6 | 8988 | \f |
e2500fed GK |
8989 | /* Function to init struct machine_function. |
8990 | This will be called, via a pointer variable, | |
8991 | from push_function_context. */ | |
a7df97e6 | 8992 | |
e2500fed | 8993 | static struct machine_function * |
863d938c | 8994 | rs6000_init_machine_status (void) |
a7df97e6 | 8995 | { |
e2500fed | 8996 | return ggc_alloc_cleared (sizeof (machine_function)); |
a7df97e6 | 8997 | } |
9878760c | 8998 | \f |
0ba1b2ff AM |
8999 | /* These macros test for integers and extract the low-order bits. */ |
9000 | #define INT_P(X) \ | |
9001 | ((GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST_DOUBLE) \ | |
9002 | && GET_MODE (X) == VOIDmode) | |
9003 | ||
9004 | #define INT_LOWPART(X) \ | |
9005 | (GET_CODE (X) == CONST_INT ? INTVAL (X) : CONST_DOUBLE_LOW (X)) | |
9006 | ||
9007 | int | |
a2369ed3 | 9008 | extract_MB (rtx op) |
0ba1b2ff AM |
9009 | { |
9010 | int i; | |
9011 | unsigned long val = INT_LOWPART (op); | |
9012 | ||
9013 | /* If the high bit is zero, the value is the first 1 bit we find | |
9014 | from the left. */ | |
9015 | if ((val & 0x80000000) == 0) | |
9016 | { | |
37409796 | 9017 | gcc_assert (val & 0xffffffff); |
0ba1b2ff AM |
9018 | |
9019 | i = 1; | |
9020 | while (((val <<= 1) & 0x80000000) == 0) | |
9021 | ++i; | |
9022 | return i; | |
9023 | } | |
9024 | ||
9025 | /* If the high bit is set and the low bit is not, or the mask is all | |
9026 | 1's, the value is zero. */ | |
9027 | if ((val & 1) == 0 || (val & 0xffffffff) == 0xffffffff) | |
9028 | return 0; | |
9029 | ||
9030 | /* Otherwise we have a wrap-around mask. Look for the first 0 bit | |
9031 | from the right. */ | |
9032 | i = 31; | |
9033 | while (((val >>= 1) & 1) != 0) | |
9034 | --i; | |
9035 | ||
9036 | return i; | |
9037 | } | |
9038 | ||
9039 | int | |
a2369ed3 | 9040 | extract_ME (rtx op) |
0ba1b2ff AM |
9041 | { |
9042 | int i; | |
9043 | unsigned long val = INT_LOWPART (op); | |
9044 | ||
9045 | /* If the low bit is zero, the value is the first 1 bit we find from | |
9046 | the right. */ | |
9047 | if ((val & 1) == 0) | |
9048 | { | |
37409796 | 9049 | gcc_assert (val & 0xffffffff); |
0ba1b2ff AM |
9050 | |
9051 | i = 30; | |
9052 | while (((val >>= 1) & 1) == 0) | |
9053 | --i; | |
9054 | ||
9055 | return i; | |
9056 | } | |
9057 | ||
9058 | /* If the low bit is set and the high bit is not, or the mask is all | |
9059 | 1's, the value is 31. */ | |
9060 | if ((val & 0x80000000) == 0 || (val & 0xffffffff) == 0xffffffff) | |
9061 | return 31; | |
9062 | ||
9063 | /* Otherwise we have a wrap-around mask. Look for the first 0 bit | |
9064 | from the left. */ | |
9065 | i = 0; | |
9066 | while (((val <<= 1) & 0x80000000) != 0) | |
9067 | ++i; | |
9068 | ||
9069 | return i; | |
9070 | } | |
9071 | ||
c4501e62 JJ |
9072 | /* Locate some local-dynamic symbol still in use by this function |
9073 | so that we can print its name in some tls_ld pattern. */ | |
9074 | ||
9075 | static const char * | |
863d938c | 9076 | rs6000_get_some_local_dynamic_name (void) |
c4501e62 JJ |
9077 | { |
9078 | rtx insn; | |
9079 | ||
9080 | if (cfun->machine->some_ld_name) | |
9081 | return cfun->machine->some_ld_name; | |
9082 | ||
9083 | for (insn = get_insns (); insn ; insn = NEXT_INSN (insn)) | |
9084 | if (INSN_P (insn) | |
9085 | && for_each_rtx (&PATTERN (insn), | |
9086 | rs6000_get_some_local_dynamic_name_1, 0)) | |
9087 | return cfun->machine->some_ld_name; | |
9088 | ||
37409796 | 9089 | gcc_unreachable (); |
c4501e62 JJ |
9090 | } |
9091 | ||
9092 | /* Helper function for rs6000_get_some_local_dynamic_name. */ | |
9093 | ||
9094 | static int | |
a2369ed3 | 9095 | rs6000_get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED) |
c4501e62 JJ |
9096 | { |
9097 | rtx x = *px; | |
9098 | ||
9099 | if (GET_CODE (x) == SYMBOL_REF) | |
9100 | { | |
9101 | const char *str = XSTR (x, 0); | |
9102 | if (SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC) | |
9103 | { | |
9104 | cfun->machine->some_ld_name = str; | |
9105 | return 1; | |
9106 | } | |
9107 | } | |
9108 | ||
9109 | return 0; | |
9110 | } | |
9111 | ||
85b776df AM |
9112 | /* Write out a function code label. */ |
9113 | ||
9114 | void | |
9115 | rs6000_output_function_entry (FILE *file, const char *fname) | |
9116 | { | |
9117 | if (fname[0] != '.') | |
9118 | { | |
9119 | switch (DEFAULT_ABI) | |
9120 | { | |
9121 | default: | |
37409796 | 9122 | gcc_unreachable (); |
85b776df AM |
9123 | |
9124 | case ABI_AIX: | |
9125 | if (DOT_SYMBOLS) | |
9126 | putc ('.', file); | |
9127 | else | |
9128 | ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "L."); | |
9129 | break; | |
9130 | ||
9131 | case ABI_V4: | |
9132 | case ABI_DARWIN: | |
9133 | break; | |
9134 | } | |
9135 | } | |
9136 | if (TARGET_AIX) | |
9137 | RS6000_OUTPUT_BASENAME (file, fname); | |
9138 | else | |
9139 | assemble_name (file, fname); | |
9140 | } | |
9141 | ||
9878760c RK |
9142 | /* Print an operand. Recognize special options, documented below. */ |
9143 | ||
38c1f2d7 | 9144 | #if TARGET_ELF |
d9407988 | 9145 | #define SMALL_DATA_RELOC ((rs6000_sdata == SDATA_EABI) ? "sda21" : "sdarel") |
8fbd2dc7 | 9146 | #define SMALL_DATA_REG ((rs6000_sdata == SDATA_EABI) ? 0 : 13) |
ba5e43aa MM |
9147 | #else |
9148 | #define SMALL_DATA_RELOC "sda21" | |
8fbd2dc7 | 9149 | #define SMALL_DATA_REG 0 |
ba5e43aa MM |
9150 | #endif |
9151 | ||
9878760c | 9152 | void |
a2369ed3 | 9153 | print_operand (FILE *file, rtx x, int code) |
9878760c RK |
9154 | { |
9155 | int i; | |
a260abc9 | 9156 | HOST_WIDE_INT val; |
0ba1b2ff | 9157 | unsigned HOST_WIDE_INT uval; |
9878760c RK |
9158 | |
9159 | switch (code) | |
9160 | { | |
a8b3aeda | 9161 | case '.': |
a85d226b RK |
9162 | /* Write out an instruction after the call which may be replaced |
9163 | with glue code by the loader. This depends on the AIX version. */ | |
9164 | asm_fprintf (file, RS6000_CALL_GLUE); | |
a8b3aeda RK |
9165 | return; |
9166 | ||
81eace42 GK |
9167 | /* %a is output_address. */ |
9168 | ||
9854d9ed RK |
9169 | case 'A': |
9170 | /* If X is a constant integer whose low-order 5 bits are zero, | |
9171 | write 'l'. Otherwise, write 'r'. This is a kludge to fix a bug | |
76229ac8 | 9172 | in the AIX assembler where "sri" with a zero shift count |
20e26713 | 9173 | writes a trash instruction. */ |
9854d9ed | 9174 | if (GET_CODE (x) == CONST_INT && (INTVAL (x) & 31) == 0) |
76229ac8 | 9175 | putc ('l', file); |
9854d9ed | 9176 | else |
76229ac8 | 9177 | putc ('r', file); |
9854d9ed RK |
9178 | return; |
9179 | ||
9180 | case 'b': | |
e2c953b6 DE |
9181 | /* If constant, low-order 16 bits of constant, unsigned. |
9182 | Otherwise, write normally. */ | |
9183 | if (INT_P (x)) | |
9184 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 0xffff); | |
9185 | else | |
9186 | print_operand (file, x, 0); | |
cad12a8d RK |
9187 | return; |
9188 | ||
a260abc9 DE |
9189 | case 'B': |
9190 | /* If the low-order bit is zero, write 'r'; otherwise, write 'l' | |
9191 | for 64-bit mask direction. */ | |
9390387d | 9192 | putc (((INT_LOWPART (x) & 1) == 0 ? 'r' : 'l'), file); |
a238cd8b | 9193 | return; |
a260abc9 | 9194 | |
81eace42 GK |
9195 | /* %c is output_addr_const if a CONSTANT_ADDRESS_P, otherwise |
9196 | output_operand. */ | |
9197 | ||
423c1189 AH |
9198 | case 'c': |
9199 | /* X is a CR register. Print the number of the GT bit of the CR. */ | |
9200 | if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x))) | |
9201 | output_operand_lossage ("invalid %%E value"); | |
9202 | else | |
9203 | fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO) + 1); | |
9204 | return; | |
9205 | ||
9206 | case 'D': | |
6b1fedc3 | 9207 | /* Like 'J' but get to the EQ bit. */ |
37409796 | 9208 | gcc_assert (GET_CODE (x) == REG); |
423c1189 | 9209 | |
6b1fedc3 AH |
9210 | /* Bit 1 is EQ bit. */ |
9211 | i = 4 * (REGNO (x) - CR0_REGNO) + 2; | |
423c1189 | 9212 | |
64022b5d | 9213 | fprintf (file, "%d", i); |
423c1189 AH |
9214 | return; |
9215 | ||
9854d9ed | 9216 | case 'E': |
39a10a29 | 9217 | /* X is a CR register. Print the number of the EQ bit of the CR */ |
9854d9ed RK |
9218 | if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x))) |
9219 | output_operand_lossage ("invalid %%E value"); | |
78fbdbf7 | 9220 | else |
39a10a29 | 9221 | fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO) + 2); |
a85d226b | 9222 | return; |
9854d9ed RK |
9223 | |
9224 | case 'f': | |
9225 | /* X is a CR register. Print the shift count needed to move it | |
9226 | to the high-order four bits. */ | |
9227 | if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x))) | |
9228 | output_operand_lossage ("invalid %%f value"); | |
9229 | else | |
9ebbca7d | 9230 | fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO)); |
9854d9ed RK |
9231 | return; |
9232 | ||
9233 | case 'F': | |
9234 | /* Similar, but print the count for the rotate in the opposite | |
9235 | direction. */ | |
9236 | if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x))) | |
9237 | output_operand_lossage ("invalid %%F value"); | |
9238 | else | |
9ebbca7d | 9239 | fprintf (file, "%d", 32 - 4 * (REGNO (x) - CR0_REGNO)); |
9854d9ed RK |
9240 | return; |
9241 | ||
9242 | case 'G': | |
9243 | /* X is a constant integer. If it is negative, print "m", | |
43aa4e05 | 9244 | otherwise print "z". This is to make an aze or ame insn. */ |
9854d9ed RK |
9245 | if (GET_CODE (x) != CONST_INT) |
9246 | output_operand_lossage ("invalid %%G value"); | |
9247 | else if (INTVAL (x) >= 0) | |
76229ac8 | 9248 | putc ('z', file); |
9854d9ed | 9249 | else |
76229ac8 | 9250 | putc ('m', file); |
9854d9ed | 9251 | return; |
e2c953b6 | 9252 | |
9878760c | 9253 | case 'h': |
a4f6c312 SS |
9254 | /* If constant, output low-order five bits. Otherwise, write |
9255 | normally. */ | |
9878760c | 9256 | if (INT_P (x)) |
5f59ecb7 | 9257 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 31); |
9878760c RK |
9258 | else |
9259 | print_operand (file, x, 0); | |
9260 | return; | |
9261 | ||
64305719 | 9262 | case 'H': |
a4f6c312 SS |
9263 | /* If constant, output low-order six bits. Otherwise, write |
9264 | normally. */ | |
64305719 | 9265 | if (INT_P (x)) |
5f59ecb7 | 9266 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 63); |
64305719 DE |
9267 | else |
9268 | print_operand (file, x, 0); | |
9269 | return; | |
9270 | ||
9854d9ed RK |
9271 | case 'I': |
9272 | /* Print `i' if this is a constant, else nothing. */ | |
9878760c | 9273 | if (INT_P (x)) |
76229ac8 | 9274 | putc ('i', file); |
9878760c RK |
9275 | return; |
9276 | ||
9854d9ed RK |
9277 | case 'j': |
9278 | /* Write the bit number in CCR for jump. */ | |
9279 | i = ccr_bit (x, 0); | |
9280 | if (i == -1) | |
9281 | output_operand_lossage ("invalid %%j code"); | |
9878760c | 9282 | else |
9854d9ed | 9283 | fprintf (file, "%d", i); |
9878760c RK |
9284 | return; |
9285 | ||
9854d9ed RK |
9286 | case 'J': |
9287 | /* Similar, but add one for shift count in rlinm for scc and pass | |
9288 | scc flag to `ccr_bit'. */ | |
9289 | i = ccr_bit (x, 1); | |
9290 | if (i == -1) | |
9291 | output_operand_lossage ("invalid %%J code"); | |
9292 | else | |
a0466a68 RK |
9293 | /* If we want bit 31, write a shift count of zero, not 32. */ |
9294 | fprintf (file, "%d", i == 31 ? 0 : i + 1); | |
9878760c RK |
9295 | return; |
9296 | ||
9854d9ed RK |
9297 | case 'k': |
9298 | /* X must be a constant. Write the 1's complement of the | |
9299 | constant. */ | |
9878760c | 9300 | if (! INT_P (x)) |
9854d9ed | 9301 | output_operand_lossage ("invalid %%k value"); |
e2c953b6 DE |
9302 | else |
9303 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, ~ INT_LOWPART (x)); | |
9878760c RK |
9304 | return; |
9305 | ||
81eace42 | 9306 | case 'K': |
9ebbca7d GK |
9307 | /* X must be a symbolic constant on ELF. Write an |
9308 | expression suitable for an 'addi' that adds in the low 16 | |
9309 | bits of the MEM. */ | |
9310 | if (GET_CODE (x) != CONST) | |
9311 | { | |
9312 | print_operand_address (file, x); | |
9313 | fputs ("@l", file); | |
9314 | } | |
9315 | else | |
9316 | { | |
9317 | if (GET_CODE (XEXP (x, 0)) != PLUS | |
9318 | || (GET_CODE (XEXP (XEXP (x, 0), 0)) != SYMBOL_REF | |
9319 | && GET_CODE (XEXP (XEXP (x, 0), 0)) != LABEL_REF) | |
9320 | || GET_CODE (XEXP (XEXP (x, 0), 1)) != CONST_INT) | |
53cd5d6c | 9321 | output_operand_lossage ("invalid %%K value"); |
9ebbca7d GK |
9322 | print_operand_address (file, XEXP (XEXP (x, 0), 0)); |
9323 | fputs ("@l", file); | |
ed8d2920 MM |
9324 | /* For GNU as, there must be a non-alphanumeric character |
9325 | between 'l' and the number. The '-' is added by | |
9326 | print_operand() already. */ | |
9327 | if (INTVAL (XEXP (XEXP (x, 0), 1)) >= 0) | |
9328 | fputs ("+", file); | |
9ebbca7d GK |
9329 | print_operand (file, XEXP (XEXP (x, 0), 1), 0); |
9330 | } | |
81eace42 GK |
9331 | return; |
9332 | ||
9333 | /* %l is output_asm_label. */ | |
9ebbca7d | 9334 | |
9854d9ed RK |
9335 | case 'L': |
9336 | /* Write second word of DImode or DFmode reference. Works on register | |
9337 | or non-indexed memory only. */ | |
9338 | if (GET_CODE (x) == REG) | |
fb5c67a7 | 9339 | fputs (reg_names[REGNO (x) + 1], file); |
9854d9ed RK |
9340 | else if (GET_CODE (x) == MEM) |
9341 | { | |
9342 | /* Handle possible auto-increment. Since it is pre-increment and | |
1427100a | 9343 | we have already done it, we can just use an offset of word. */ |
9854d9ed RK |
9344 | if (GET_CODE (XEXP (x, 0)) == PRE_INC |
9345 | || GET_CODE (XEXP (x, 0)) == PRE_DEC) | |
ed8908e7 RK |
9346 | output_address (plus_constant (XEXP (XEXP (x, 0), 0), |
9347 | UNITS_PER_WORD)); | |
9854d9ed | 9348 | else |
d7624dc0 RK |
9349 | output_address (XEXP (adjust_address_nv (x, SImode, |
9350 | UNITS_PER_WORD), | |
9351 | 0)); | |
ed8908e7 | 9352 | |
ba5e43aa | 9353 | if (small_data_operand (x, GET_MODE (x))) |
8fbd2dc7 MM |
9354 | fprintf (file, "@%s(%s)", SMALL_DATA_RELOC, |
9355 | reg_names[SMALL_DATA_REG]); | |
9854d9ed | 9356 | } |
9878760c | 9357 | return; |
f676971a | 9358 | |
9878760c RK |
9359 | case 'm': |
9360 | /* MB value for a mask operand. */ | |
b1765bde | 9361 | if (! mask_operand (x, SImode)) |
9878760c RK |
9362 | output_operand_lossage ("invalid %%m value"); |
9363 | ||
0ba1b2ff | 9364 | fprintf (file, "%d", extract_MB (x)); |
9878760c RK |
9365 | return; |
9366 | ||
9367 | case 'M': | |
9368 | /* ME value for a mask operand. */ | |
b1765bde | 9369 | if (! mask_operand (x, SImode)) |
a260abc9 | 9370 | output_operand_lossage ("invalid %%M value"); |
9878760c | 9371 | |
0ba1b2ff | 9372 | fprintf (file, "%d", extract_ME (x)); |
9878760c RK |
9373 | return; |
9374 | ||
81eace42 GK |
9375 | /* %n outputs the negative of its operand. */ |
9376 | ||
9878760c RK |
9377 | case 'N': |
9378 | /* Write the number of elements in the vector times 4. */ | |
9379 | if (GET_CODE (x) != PARALLEL) | |
9380 | output_operand_lossage ("invalid %%N value"); | |
e2c953b6 DE |
9381 | else |
9382 | fprintf (file, "%d", XVECLEN (x, 0) * 4); | |
9878760c RK |
9383 | return; |
9384 | ||
9385 | case 'O': | |
9386 | /* Similar, but subtract 1 first. */ | |
9387 | if (GET_CODE (x) != PARALLEL) | |
1427100a | 9388 | output_operand_lossage ("invalid %%O value"); |
e2c953b6 DE |
9389 | else |
9390 | fprintf (file, "%d", (XVECLEN (x, 0) - 1) * 4); | |
9878760c RK |
9391 | return; |
9392 | ||
9854d9ed RK |
9393 | case 'p': |
9394 | /* X is a CONST_INT that is a power of two. Output the logarithm. */ | |
9395 | if (! INT_P (x) | |
2bfcf297 | 9396 | || INT_LOWPART (x) < 0 |
9854d9ed RK |
9397 | || (i = exact_log2 (INT_LOWPART (x))) < 0) |
9398 | output_operand_lossage ("invalid %%p value"); | |
e2c953b6 DE |
9399 | else |
9400 | fprintf (file, "%d", i); | |
9854d9ed RK |
9401 | return; |
9402 | ||
9878760c RK |
9403 | case 'P': |
9404 | /* The operand must be an indirect memory reference. The result | |
8bb418a3 | 9405 | is the register name. */ |
9878760c RK |
9406 | if (GET_CODE (x) != MEM || GET_CODE (XEXP (x, 0)) != REG |
9407 | || REGNO (XEXP (x, 0)) >= 32) | |
9408 | output_operand_lossage ("invalid %%P value"); | |
e2c953b6 | 9409 | else |
fb5c67a7 | 9410 | fputs (reg_names[REGNO (XEXP (x, 0))], file); |
9878760c RK |
9411 | return; |
9412 | ||
dfbdccdb GK |
9413 | case 'q': |
9414 | /* This outputs the logical code corresponding to a boolean | |
9415 | expression. The expression may have one or both operands | |
39a10a29 | 9416 | negated (if one, only the first one). For condition register |
c4ad648e AM |
9417 | logical operations, it will also treat the negated |
9418 | CR codes as NOTs, but not handle NOTs of them. */ | |
dfbdccdb | 9419 | { |
63bc1d05 | 9420 | const char *const *t = 0; |
dfbdccdb GK |
9421 | const char *s; |
9422 | enum rtx_code code = GET_CODE (x); | |
9423 | static const char * const tbl[3][3] = { | |
9424 | { "and", "andc", "nor" }, | |
9425 | { "or", "orc", "nand" }, | |
9426 | { "xor", "eqv", "xor" } }; | |
9427 | ||
9428 | if (code == AND) | |
9429 | t = tbl[0]; | |
9430 | else if (code == IOR) | |
9431 | t = tbl[1]; | |
9432 | else if (code == XOR) | |
9433 | t = tbl[2]; | |
9434 | else | |
9435 | output_operand_lossage ("invalid %%q value"); | |
9436 | ||
9437 | if (GET_CODE (XEXP (x, 0)) != NOT) | |
9438 | s = t[0]; | |
9439 | else | |
9440 | { | |
9441 | if (GET_CODE (XEXP (x, 1)) == NOT) | |
9442 | s = t[2]; | |
9443 | else | |
9444 | s = t[1]; | |
9445 | } | |
f676971a | 9446 | |
dfbdccdb GK |
9447 | fputs (s, file); |
9448 | } | |
9449 | return; | |
9450 | ||
2c4a9cff DE |
9451 | case 'Q': |
9452 | if (TARGET_MFCRF) | |
3b6ce0af | 9453 | fputc (',', file); |
5efb1046 | 9454 | /* FALLTHRU */ |
2c4a9cff DE |
9455 | else |
9456 | return; | |
9457 | ||
9854d9ed RK |
9458 | case 'R': |
9459 | /* X is a CR register. Print the mask for `mtcrf'. */ | |
9460 | if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x))) | |
9461 | output_operand_lossage ("invalid %%R value"); | |
9462 | else | |
9ebbca7d | 9463 | fprintf (file, "%d", 128 >> (REGNO (x) - CR0_REGNO)); |
9878760c | 9464 | return; |
9854d9ed RK |
9465 | |
9466 | case 's': | |
9467 | /* Low 5 bits of 32 - value */ | |
9468 | if (! INT_P (x)) | |
9469 | output_operand_lossage ("invalid %%s value"); | |
e2c953b6 DE |
9470 | else |
9471 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, (32 - INT_LOWPART (x)) & 31); | |
9878760c | 9472 | return; |
9854d9ed | 9473 | |
a260abc9 | 9474 | case 'S': |
0ba1b2ff | 9475 | /* PowerPC64 mask position. All 0's is excluded. |
a260abc9 DE |
9476 | CONST_INT 32-bit mask is considered sign-extended so any |
9477 | transition must occur within the CONST_INT, not on the boundary. */ | |
b1765bde | 9478 | if (! mask64_operand (x, DImode)) |
a260abc9 DE |
9479 | output_operand_lossage ("invalid %%S value"); |
9480 | ||
0ba1b2ff | 9481 | uval = INT_LOWPART (x); |
a260abc9 | 9482 | |
0ba1b2ff | 9483 | if (uval & 1) /* Clear Left */ |
a260abc9 | 9484 | { |
f099d360 GK |
9485 | #if HOST_BITS_PER_WIDE_INT > 64 |
9486 | uval &= ((unsigned HOST_WIDE_INT) 1 << 64) - 1; | |
9487 | #endif | |
0ba1b2ff | 9488 | i = 64; |
a260abc9 | 9489 | } |
0ba1b2ff | 9490 | else /* Clear Right */ |
a260abc9 | 9491 | { |
0ba1b2ff | 9492 | uval = ~uval; |
f099d360 GK |
9493 | #if HOST_BITS_PER_WIDE_INT > 64 |
9494 | uval &= ((unsigned HOST_WIDE_INT) 1 << 64) - 1; | |
9495 | #endif | |
0ba1b2ff | 9496 | i = 63; |
a260abc9 | 9497 | } |
0ba1b2ff AM |
9498 | while (uval != 0) |
9499 | --i, uval >>= 1; | |
37409796 | 9500 | gcc_assert (i >= 0); |
0ba1b2ff AM |
9501 | fprintf (file, "%d", i); |
9502 | return; | |
a260abc9 | 9503 | |
a3170dc6 AH |
9504 | case 't': |
9505 | /* Like 'J' but get to the OVERFLOW/UNORDERED bit. */ | |
37409796 | 9506 | gcc_assert (GET_CODE (x) == REG && GET_MODE (x) == CCmode); |
a3170dc6 AH |
9507 | |
9508 | /* Bit 3 is OV bit. */ | |
9509 | i = 4 * (REGNO (x) - CR0_REGNO) + 3; | |
9510 | ||
9511 | /* If we want bit 31, write a shift count of zero, not 32. */ | |
9512 | fprintf (file, "%d", i == 31 ? 0 : i + 1); | |
9513 | return; | |
9514 | ||
cccf3bdc DE |
9515 | case 'T': |
9516 | /* Print the symbolic name of a branch target register. */ | |
9517 | if (GET_CODE (x) != REG || (REGNO (x) != LINK_REGISTER_REGNUM | |
9518 | && REGNO (x) != COUNT_REGISTER_REGNUM)) | |
9519 | output_operand_lossage ("invalid %%T value"); | |
e2c953b6 | 9520 | else if (REGNO (x) == LINK_REGISTER_REGNUM) |
cccf3bdc DE |
9521 | fputs (TARGET_NEW_MNEMONICS ? "lr" : "r", file); |
9522 | else | |
9523 | fputs ("ctr", file); | |
9524 | return; | |
9525 | ||
9854d9ed | 9526 | case 'u': |
802a0058 | 9527 | /* High-order 16 bits of constant for use in unsigned operand. */ |
9854d9ed RK |
9528 | if (! INT_P (x)) |
9529 | output_operand_lossage ("invalid %%u value"); | |
e2c953b6 | 9530 | else |
f676971a | 9531 | fprintf (file, HOST_WIDE_INT_PRINT_HEX, |
e2c953b6 | 9532 | (INT_LOWPART (x) >> 16) & 0xffff); |
9878760c RK |
9533 | return; |
9534 | ||
802a0058 MM |
9535 | case 'v': |
9536 | /* High-order 16 bits of constant for use in signed operand. */ | |
9537 | if (! INT_P (x)) | |
9538 | output_operand_lossage ("invalid %%v value"); | |
e2c953b6 | 9539 | else |
134c32f6 DE |
9540 | fprintf (file, HOST_WIDE_INT_PRINT_HEX, |
9541 | (INT_LOWPART (x) >> 16) & 0xffff); | |
9542 | return; | |
802a0058 | 9543 | |
9854d9ed RK |
9544 | case 'U': |
9545 | /* Print `u' if this has an auto-increment or auto-decrement. */ | |
9546 | if (GET_CODE (x) == MEM | |
9547 | && (GET_CODE (XEXP (x, 0)) == PRE_INC | |
9548 | || GET_CODE (XEXP (x, 0)) == PRE_DEC)) | |
76229ac8 | 9549 | putc ('u', file); |
9854d9ed | 9550 | return; |
9878760c | 9551 | |
e0cd0770 JC |
9552 | case 'V': |
9553 | /* Print the trap code for this operand. */ | |
9554 | switch (GET_CODE (x)) | |
9555 | { | |
9556 | case EQ: | |
9557 | fputs ("eq", file); /* 4 */ | |
9558 | break; | |
9559 | case NE: | |
9560 | fputs ("ne", file); /* 24 */ | |
9561 | break; | |
9562 | case LT: | |
9563 | fputs ("lt", file); /* 16 */ | |
9564 | break; | |
9565 | case LE: | |
9566 | fputs ("le", file); /* 20 */ | |
9567 | break; | |
9568 | case GT: | |
9569 | fputs ("gt", file); /* 8 */ | |
9570 | break; | |
9571 | case GE: | |
9572 | fputs ("ge", file); /* 12 */ | |
9573 | break; | |
9574 | case LTU: | |
9575 | fputs ("llt", file); /* 2 */ | |
9576 | break; | |
9577 | case LEU: | |
9578 | fputs ("lle", file); /* 6 */ | |
9579 | break; | |
9580 | case GTU: | |
9581 | fputs ("lgt", file); /* 1 */ | |
9582 | break; | |
9583 | case GEU: | |
9584 | fputs ("lge", file); /* 5 */ | |
9585 | break; | |
9586 | default: | |
37409796 | 9587 | gcc_unreachable (); |
e0cd0770 JC |
9588 | } |
9589 | break; | |
9590 | ||
9854d9ed RK |
9591 | case 'w': |
9592 | /* If constant, low-order 16 bits of constant, signed. Otherwise, write | |
9593 | normally. */ | |
9594 | if (INT_P (x)) | |
f676971a | 9595 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, |
5f59ecb7 | 9596 | ((INT_LOWPART (x) & 0xffff) ^ 0x8000) - 0x8000); |
9854d9ed RK |
9597 | else |
9598 | print_operand (file, x, 0); | |
9878760c RK |
9599 | return; |
9600 | ||
9854d9ed | 9601 | case 'W': |
e2c953b6 | 9602 | /* MB value for a PowerPC64 rldic operand. */ |
e2c953b6 DE |
9603 | val = (GET_CODE (x) == CONST_INT |
9604 | ? INTVAL (x) : CONST_DOUBLE_HIGH (x)); | |
9605 | ||
9606 | if (val < 0) | |
9607 | i = -1; | |
9854d9ed | 9608 | else |
e2c953b6 DE |
9609 | for (i = 0; i < HOST_BITS_PER_WIDE_INT; i++) |
9610 | if ((val <<= 1) < 0) | |
9611 | break; | |
9612 | ||
9613 | #if HOST_BITS_PER_WIDE_INT == 32 | |
9614 | if (GET_CODE (x) == CONST_INT && i >= 0) | |
9615 | i += 32; /* zero-extend high-part was all 0's */ | |
9616 | else if (GET_CODE (x) == CONST_DOUBLE && i == 32) | |
9617 | { | |
9618 | val = CONST_DOUBLE_LOW (x); | |
9619 | ||
37409796 NS |
9620 | gcc_assert (val); |
9621 | if (val < 0) | |
e2c953b6 DE |
9622 | --i; |
9623 | else | |
9624 | for ( ; i < 64; i++) | |
9625 | if ((val <<= 1) < 0) | |
9626 | break; | |
9627 | } | |
9628 | #endif | |
9629 | ||
9630 | fprintf (file, "%d", i + 1); | |
9854d9ed | 9631 | return; |
9878760c | 9632 | |
9854d9ed RK |
9633 | case 'X': |
9634 | if (GET_CODE (x) == MEM | |
4d588c14 | 9635 | && legitimate_indexed_address_p (XEXP (x, 0), 0)) |
76229ac8 | 9636 | putc ('x', file); |
9854d9ed | 9637 | return; |
9878760c | 9638 | |
9854d9ed RK |
9639 | case 'Y': |
9640 | /* Like 'L', for third word of TImode */ | |
9641 | if (GET_CODE (x) == REG) | |
fb5c67a7 | 9642 | fputs (reg_names[REGNO (x) + 2], file); |
9854d9ed | 9643 | else if (GET_CODE (x) == MEM) |
9878760c | 9644 | { |
9854d9ed RK |
9645 | if (GET_CODE (XEXP (x, 0)) == PRE_INC |
9646 | || GET_CODE (XEXP (x, 0)) == PRE_DEC) | |
a54d04b7 | 9647 | output_address (plus_constant (XEXP (XEXP (x, 0), 0), 8)); |
9854d9ed | 9648 | else |
d7624dc0 | 9649 | output_address (XEXP (adjust_address_nv (x, SImode, 8), 0)); |
ba5e43aa | 9650 | if (small_data_operand (x, GET_MODE (x))) |
8fbd2dc7 MM |
9651 | fprintf (file, "@%s(%s)", SMALL_DATA_RELOC, |
9652 | reg_names[SMALL_DATA_REG]); | |
9878760c RK |
9653 | } |
9654 | return; | |
f676971a | 9655 | |
9878760c | 9656 | case 'z': |
b4ac57ab RS |
9657 | /* X is a SYMBOL_REF. Write out the name preceded by a |
9658 | period and without any trailing data in brackets. Used for function | |
4d30c363 MM |
9659 | names. If we are configured for System V (or the embedded ABI) on |
9660 | the PowerPC, do not emit the period, since those systems do not use | |
9661 | TOCs and the like. */ | |
37409796 | 9662 | gcc_assert (GET_CODE (x) == SYMBOL_REF); |
9878760c | 9663 | |
c4ad648e AM |
9664 | /* Mark the decl as referenced so that cgraph will output the |
9665 | function. */ | |
9bf6462a | 9666 | if (SYMBOL_REF_DECL (x)) |
c4ad648e | 9667 | mark_decl_referenced (SYMBOL_REF_DECL (x)); |
9bf6462a | 9668 | |
85b776df | 9669 | /* For macho, check to see if we need a stub. */ |
f9da97f0 AP |
9670 | if (TARGET_MACHO) |
9671 | { | |
9672 | const char *name = XSTR (x, 0); | |
a031e781 | 9673 | #if TARGET_MACHO |
3b48085e | 9674 | if (MACHOPIC_INDIRECT |
11abc112 MM |
9675 | && machopic_classify_symbol (x) == MACHOPIC_UNDEFINED_FUNCTION) |
9676 | name = machopic_indirection_name (x, /*stub_p=*/true); | |
f9da97f0 AP |
9677 | #endif |
9678 | assemble_name (file, name); | |
9679 | } | |
85b776df | 9680 | else if (!DOT_SYMBOLS) |
9739c90c | 9681 | assemble_name (file, XSTR (x, 0)); |
85b776df AM |
9682 | else |
9683 | rs6000_output_function_entry (file, XSTR (x, 0)); | |
9878760c RK |
9684 | return; |
9685 | ||
9854d9ed RK |
9686 | case 'Z': |
9687 | /* Like 'L', for last word of TImode. */ | |
9688 | if (GET_CODE (x) == REG) | |
fb5c67a7 | 9689 | fputs (reg_names[REGNO (x) + 3], file); |
9854d9ed RK |
9690 | else if (GET_CODE (x) == MEM) |
9691 | { | |
9692 | if (GET_CODE (XEXP (x, 0)) == PRE_INC | |
9693 | || GET_CODE (XEXP (x, 0)) == PRE_DEC) | |
a54d04b7 | 9694 | output_address (plus_constant (XEXP (XEXP (x, 0), 0), 12)); |
9854d9ed | 9695 | else |
d7624dc0 | 9696 | output_address (XEXP (adjust_address_nv (x, SImode, 12), 0)); |
ba5e43aa | 9697 | if (small_data_operand (x, GET_MODE (x))) |
8fbd2dc7 MM |
9698 | fprintf (file, "@%s(%s)", SMALL_DATA_RELOC, |
9699 | reg_names[SMALL_DATA_REG]); | |
9854d9ed | 9700 | } |
5c23c401 | 9701 | return; |
0ac081f6 | 9702 | |
a3170dc6 | 9703 | /* Print AltiVec or SPE memory operand. */ |
0ac081f6 AH |
9704 | case 'y': |
9705 | { | |
9706 | rtx tmp; | |
9707 | ||
37409796 | 9708 | gcc_assert (GET_CODE (x) == MEM); |
0ac081f6 AH |
9709 | |
9710 | tmp = XEXP (x, 0); | |
9711 | ||
993f19a8 | 9712 | if (TARGET_E500) |
a3170dc6 AH |
9713 | { |
9714 | /* Handle [reg]. */ | |
9715 | if (GET_CODE (tmp) == REG) | |
9716 | { | |
9717 | fprintf (file, "0(%s)", reg_names[REGNO (tmp)]); | |
9718 | break; | |
9719 | } | |
9720 | /* Handle [reg+UIMM]. */ | |
9721 | else if (GET_CODE (tmp) == PLUS && | |
9722 | GET_CODE (XEXP (tmp, 1)) == CONST_INT) | |
9723 | { | |
9724 | int x; | |
9725 | ||
37409796 | 9726 | gcc_assert (GET_CODE (XEXP (tmp, 0)) == REG); |
a3170dc6 AH |
9727 | |
9728 | x = INTVAL (XEXP (tmp, 1)); | |
9729 | fprintf (file, "%d(%s)", x, reg_names[REGNO (XEXP (tmp, 0))]); | |
9730 | break; | |
9731 | } | |
9732 | ||
9733 | /* Fall through. Must be [reg+reg]. */ | |
9734 | } | |
850e8d3d DN |
9735 | if (TARGET_ALTIVEC |
9736 | && GET_CODE (tmp) == AND | |
9737 | && GET_CODE (XEXP (tmp, 1)) == CONST_INT | |
9738 | && INTVAL (XEXP (tmp, 1)) == -16) | |
9739 | tmp = XEXP (tmp, 0); | |
0ac081f6 | 9740 | if (GET_CODE (tmp) == REG) |
c62f2db5 | 9741 | fprintf (file, "0,%s", reg_names[REGNO (tmp)]); |
37409796 | 9742 | else |
0ac081f6 | 9743 | { |
37409796 NS |
9744 | gcc_assert (GET_CODE (tmp) == PLUS |
9745 | && GET_CODE (XEXP (tmp, 1)) == REG); | |
9746 | ||
0ac081f6 AH |
9747 | if (REGNO (XEXP (tmp, 0)) == 0) |
9748 | fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 1)) ], | |
9749 | reg_names[ REGNO (XEXP (tmp, 0)) ]); | |
9750 | else | |
9751 | fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 0)) ], | |
9752 | reg_names[ REGNO (XEXP (tmp, 1)) ]); | |
9753 | } | |
0ac081f6 AH |
9754 | break; |
9755 | } | |
f676971a | 9756 | |
9878760c RK |
9757 | case 0: |
9758 | if (GET_CODE (x) == REG) | |
9759 | fprintf (file, "%s", reg_names[REGNO (x)]); | |
9760 | else if (GET_CODE (x) == MEM) | |
9761 | { | |
9762 | /* We need to handle PRE_INC and PRE_DEC here, since we need to | |
9763 | know the width from the mode. */ | |
9764 | if (GET_CODE (XEXP (x, 0)) == PRE_INC) | |
79ba6d34 MM |
9765 | fprintf (file, "%d(%s)", GET_MODE_SIZE (GET_MODE (x)), |
9766 | reg_names[REGNO (XEXP (XEXP (x, 0), 0))]); | |
9878760c | 9767 | else if (GET_CODE (XEXP (x, 0)) == PRE_DEC) |
79ba6d34 MM |
9768 | fprintf (file, "%d(%s)", - GET_MODE_SIZE (GET_MODE (x)), |
9769 | reg_names[REGNO (XEXP (XEXP (x, 0), 0))]); | |
9878760c | 9770 | else |
a54d04b7 | 9771 | output_address (XEXP (x, 0)); |
9878760c RK |
9772 | } |
9773 | else | |
a54d04b7 | 9774 | output_addr_const (file, x); |
a85d226b | 9775 | return; |
9878760c | 9776 | |
c4501e62 JJ |
9777 | case '&': |
9778 | assemble_name (file, rs6000_get_some_local_dynamic_name ()); | |
9779 | return; | |
9780 | ||
9878760c RK |
9781 | default: |
9782 | output_operand_lossage ("invalid %%xn code"); | |
9783 | } | |
9784 | } | |
9785 | \f | |
9786 | /* Print the address of an operand. */ | |
9787 | ||
9788 | void | |
a2369ed3 | 9789 | print_operand_address (FILE *file, rtx x) |
9878760c RK |
9790 | { |
9791 | if (GET_CODE (x) == REG) | |
4697a36c | 9792 | fprintf (file, "0(%s)", reg_names[ REGNO (x) ]); |
9ebbca7d GK |
9793 | else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST |
9794 | || GET_CODE (x) == LABEL_REF) | |
9878760c RK |
9795 | { |
9796 | output_addr_const (file, x); | |
ba5e43aa | 9797 | if (small_data_operand (x, GET_MODE (x))) |
8fbd2dc7 MM |
9798 | fprintf (file, "@%s(%s)", SMALL_DATA_RELOC, |
9799 | reg_names[SMALL_DATA_REG]); | |
37409796 NS |
9800 | else |
9801 | gcc_assert (!TARGET_TOC); | |
9878760c RK |
9802 | } |
9803 | else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == REG) | |
9804 | { | |
9805 | if (REGNO (XEXP (x, 0)) == 0) | |
4697a36c MM |
9806 | fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 1)) ], |
9807 | reg_names[ REGNO (XEXP (x, 0)) ]); | |
9878760c | 9808 | else |
4697a36c MM |
9809 | fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 0)) ], |
9810 | reg_names[ REGNO (XEXP (x, 1)) ]); | |
9878760c RK |
9811 | } |
9812 | else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT) | |
4a0a75dd KG |
9813 | fprintf (file, HOST_WIDE_INT_PRINT_DEC "(%s)", |
9814 | INTVAL (XEXP (x, 1)), reg_names[ REGNO (XEXP (x, 0)) ]); | |
3cb999d8 DE |
9815 | #if TARGET_ELF |
9816 | else if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 0)) == REG | |
c4ad648e | 9817 | && CONSTANT_P (XEXP (x, 1))) |
4697a36c MM |
9818 | { |
9819 | output_addr_const (file, XEXP (x, 1)); | |
9820 | fprintf (file, "@l(%s)", reg_names[ REGNO (XEXP (x, 0)) ]); | |
9821 | } | |
c859cda6 DJ |
9822 | #endif |
9823 | #if TARGET_MACHO | |
9824 | else if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 0)) == REG | |
c4ad648e | 9825 | && CONSTANT_P (XEXP (x, 1))) |
c859cda6 DJ |
9826 | { |
9827 | fprintf (file, "lo16("); | |
9828 | output_addr_const (file, XEXP (x, 1)); | |
9829 | fprintf (file, ")(%s)", reg_names[ REGNO (XEXP (x, 0)) ]); | |
9830 | } | |
3cb999d8 | 9831 | #endif |
4d588c14 | 9832 | else if (legitimate_constant_pool_address_p (x)) |
9ebbca7d | 9833 | { |
2bfcf297 | 9834 | if (TARGET_AIX && (!TARGET_ELF || !TARGET_MINIMAL_TOC)) |
9ebbca7d | 9835 | { |
2bfcf297 DB |
9836 | rtx contains_minus = XEXP (x, 1); |
9837 | rtx minus, symref; | |
9838 | const char *name; | |
f676971a | 9839 | |
9ebbca7d | 9840 | /* Find the (minus (sym) (toc)) buried in X, and temporarily |
a4f6c312 | 9841 | turn it into (sym) for output_addr_const. */ |
9ebbca7d GK |
9842 | while (GET_CODE (XEXP (contains_minus, 0)) != MINUS) |
9843 | contains_minus = XEXP (contains_minus, 0); | |
9844 | ||
2bfcf297 DB |
9845 | minus = XEXP (contains_minus, 0); |
9846 | symref = XEXP (minus, 0); | |
9847 | XEXP (contains_minus, 0) = symref; | |
9848 | if (TARGET_ELF) | |
9849 | { | |
9850 | char *newname; | |
9851 | ||
9852 | name = XSTR (symref, 0); | |
9853 | newname = alloca (strlen (name) + sizeof ("@toc")); | |
9854 | strcpy (newname, name); | |
9855 | strcat (newname, "@toc"); | |
9856 | XSTR (symref, 0) = newname; | |
9857 | } | |
9858 | output_addr_const (file, XEXP (x, 1)); | |
9859 | if (TARGET_ELF) | |
9860 | XSTR (symref, 0) = name; | |
9ebbca7d GK |
9861 | XEXP (contains_minus, 0) = minus; |
9862 | } | |
9863 | else | |
9864 | output_addr_const (file, XEXP (x, 1)); | |
9865 | ||
9866 | fprintf (file, "(%s)", reg_names[REGNO (XEXP (x, 0))]); | |
9867 | } | |
9878760c | 9868 | else |
37409796 | 9869 | gcc_unreachable (); |
9878760c RK |
9870 | } |
9871 | \f | |
88cad84b | 9872 | /* Target hook for assembling integer objects. The PowerPC version has |
301d03af RS |
9873 | to handle fixup entries for relocatable code if RELOCATABLE_NEEDS_FIXUP |
9874 | is defined. It also needs to handle DI-mode objects on 64-bit | |
9875 | targets. */ | |
9876 | ||
9877 | static bool | |
a2369ed3 | 9878 | rs6000_assemble_integer (rtx x, unsigned int size, int aligned_p) |
301d03af | 9879 | { |
f4f4921e | 9880 | #ifdef RELOCATABLE_NEEDS_FIXUP |
301d03af | 9881 | /* Special handling for SI values. */ |
84dcde01 | 9882 | if (RELOCATABLE_NEEDS_FIXUP && size == 4 && aligned_p) |
301d03af | 9883 | { |
a2369ed3 | 9884 | extern int in_toc_section (void); |
301d03af | 9885 | static int recurse = 0; |
f676971a | 9886 | |
301d03af RS |
9887 | /* For -mrelocatable, we mark all addresses that need to be fixed up |
9888 | in the .fixup section. */ | |
9889 | if (TARGET_RELOCATABLE | |
9890 | && !in_toc_section () | |
9891 | && !in_text_section () | |
642af3be | 9892 | && !in_unlikely_text_section () |
301d03af RS |
9893 | && !recurse |
9894 | && GET_CODE (x) != CONST_INT | |
9895 | && GET_CODE (x) != CONST_DOUBLE | |
9896 | && CONSTANT_P (x)) | |
9897 | { | |
9898 | char buf[256]; | |
9899 | ||
9900 | recurse = 1; | |
9901 | ASM_GENERATE_INTERNAL_LABEL (buf, "LCP", fixuplabelno); | |
9902 | fixuplabelno++; | |
9903 | ASM_OUTPUT_LABEL (asm_out_file, buf); | |
9904 | fprintf (asm_out_file, "\t.long\t("); | |
9905 | output_addr_const (asm_out_file, x); | |
9906 | fprintf (asm_out_file, ")@fixup\n"); | |
9907 | fprintf (asm_out_file, "\t.section\t\".fixup\",\"aw\"\n"); | |
9908 | ASM_OUTPUT_ALIGN (asm_out_file, 2); | |
9909 | fprintf (asm_out_file, "\t.long\t"); | |
9910 | assemble_name (asm_out_file, buf); | |
9911 | fprintf (asm_out_file, "\n\t.previous\n"); | |
9912 | recurse = 0; | |
9913 | return true; | |
9914 | } | |
9915 | /* Remove initial .'s to turn a -mcall-aixdesc function | |
9916 | address into the address of the descriptor, not the function | |
9917 | itself. */ | |
9918 | else if (GET_CODE (x) == SYMBOL_REF | |
9919 | && XSTR (x, 0)[0] == '.' | |
9920 | && DEFAULT_ABI == ABI_AIX) | |
9921 | { | |
9922 | const char *name = XSTR (x, 0); | |
9923 | while (*name == '.') | |
9924 | name++; | |
9925 | ||
9926 | fprintf (asm_out_file, "\t.long\t%s\n", name); | |
9927 | return true; | |
9928 | } | |
9929 | } | |
f4f4921e | 9930 | #endif /* RELOCATABLE_NEEDS_FIXUP */ |
301d03af RS |
9931 | return default_assemble_integer (x, size, aligned_p); |
9932 | } | |
93638d7a AM |
9933 | |
9934 | #ifdef HAVE_GAS_HIDDEN | |
9935 | /* Emit an assembler directive to set symbol visibility for DECL to | |
9936 | VISIBILITY_TYPE. */ | |
9937 | ||
5add3202 | 9938 | static void |
a2369ed3 | 9939 | rs6000_assemble_visibility (tree decl, int vis) |
93638d7a | 9940 | { |
93638d7a AM |
9941 | /* Functions need to have their entry point symbol visibility set as |
9942 | well as their descriptor symbol visibility. */ | |
85b776df AM |
9943 | if (DEFAULT_ABI == ABI_AIX |
9944 | && DOT_SYMBOLS | |
9945 | && TREE_CODE (decl) == FUNCTION_DECL) | |
93638d7a | 9946 | { |
25fdb4dc | 9947 | static const char * const visibility_types[] = { |
c4ad648e | 9948 | NULL, "internal", "hidden", "protected" |
25fdb4dc RH |
9949 | }; |
9950 | ||
9951 | const char *name, *type; | |
93638d7a AM |
9952 | |
9953 | name = ((* targetm.strip_name_encoding) | |
9954 | (IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl)))); | |
25fdb4dc | 9955 | type = visibility_types[vis]; |
93638d7a | 9956 | |
25fdb4dc RH |
9957 | fprintf (asm_out_file, "\t.%s\t%s\n", type, name); |
9958 | fprintf (asm_out_file, "\t.%s\t.%s\n", type, name); | |
93638d7a | 9959 | } |
25fdb4dc RH |
9960 | else |
9961 | default_assemble_visibility (decl, vis); | |
93638d7a AM |
9962 | } |
9963 | #endif | |
301d03af | 9964 | \f |
39a10a29 | 9965 | enum rtx_code |
a2369ed3 | 9966 | rs6000_reverse_condition (enum machine_mode mode, enum rtx_code code) |
39a10a29 GK |
9967 | { |
9968 | /* Reversal of FP compares takes care -- an ordered compare | |
9969 | becomes an unordered compare and vice versa. */ | |
f676971a | 9970 | if (mode == CCFPmode |
bc9ec0e0 GK |
9971 | && (!flag_finite_math_only |
9972 | || code == UNLT || code == UNLE || code == UNGT || code == UNGE | |
9973 | || code == UNEQ || code == LTGT)) | |
bab6226b | 9974 | return reverse_condition_maybe_unordered (code); |
39a10a29 | 9975 | else |
bab6226b | 9976 | return reverse_condition (code); |
39a10a29 GK |
9977 | } |
9978 | ||
39a10a29 GK |
9979 | /* Generate a compare for CODE. Return a brand-new rtx that |
9980 | represents the result of the compare. */ | |
a4f6c312 | 9981 | |
39a10a29 | 9982 | static rtx |
a2369ed3 | 9983 | rs6000_generate_compare (enum rtx_code code) |
39a10a29 GK |
9984 | { |
9985 | enum machine_mode comp_mode; | |
9986 | rtx compare_result; | |
9987 | ||
9988 | if (rs6000_compare_fp_p) | |
9989 | comp_mode = CCFPmode; | |
9990 | else if (code == GTU || code == LTU | |
c4ad648e | 9991 | || code == GEU || code == LEU) |
39a10a29 | 9992 | comp_mode = CCUNSmode; |
60934f9c NS |
9993 | else if ((code == EQ || code == NE) |
9994 | && GET_CODE (rs6000_compare_op0) == SUBREG | |
9995 | && GET_CODE (rs6000_compare_op1) == SUBREG | |
9996 | && SUBREG_PROMOTED_UNSIGNED_P (rs6000_compare_op0) | |
9997 | && SUBREG_PROMOTED_UNSIGNED_P (rs6000_compare_op1)) | |
9998 | /* These are unsigned values, perhaps there will be a later | |
9999 | ordering compare that can be shared with this one. | |
10000 | Unfortunately we cannot detect the signedness of the operands | |
10001 | for non-subregs. */ | |
10002 | comp_mode = CCUNSmode; | |
39a10a29 GK |
10003 | else |
10004 | comp_mode = CCmode; | |
10005 | ||
10006 | /* First, the compare. */ | |
10007 | compare_result = gen_reg_rtx (comp_mode); | |
a3170dc6 AH |
10008 | |
10009 | /* SPE FP compare instructions on the GPRs. Yuck! */ | |
993f19a8 AH |
10010 | if ((TARGET_E500 && !TARGET_FPRS && TARGET_HARD_FLOAT) |
10011 | && rs6000_compare_fp_p) | |
a3170dc6 | 10012 | { |
64022b5d | 10013 | rtx cmp, or_result, compare_result2; |
4d4cbc0e AH |
10014 | enum machine_mode op_mode = GET_MODE (rs6000_compare_op0); |
10015 | ||
10016 | if (op_mode == VOIDmode) | |
10017 | op_mode = GET_MODE (rs6000_compare_op1); | |
a3170dc6 | 10018 | |
423c1189 AH |
10019 | /* Note: The E500 comparison instructions set the GT bit (x + |
10020 | 1), on success. This explains the mess. */ | |
10021 | ||
a3170dc6 AH |
10022 | switch (code) |
10023 | { | |
423c1189 | 10024 | case EQ: case UNEQ: case NE: case LTGT: |
37409796 NS |
10025 | switch (op_mode) |
10026 | { | |
10027 | case SFmode: | |
10028 | cmp = flag_unsafe_math_optimizations | |
10029 | ? gen_tstsfeq_gpr (compare_result, rs6000_compare_op0, | |
10030 | rs6000_compare_op1) | |
10031 | : gen_cmpsfeq_gpr (compare_result, rs6000_compare_op0, | |
10032 | rs6000_compare_op1); | |
10033 | break; | |
10034 | ||
10035 | case DFmode: | |
10036 | cmp = flag_unsafe_math_optimizations | |
10037 | ? gen_tstdfeq_gpr (compare_result, rs6000_compare_op0, | |
10038 | rs6000_compare_op1) | |
10039 | : gen_cmpdfeq_gpr (compare_result, rs6000_compare_op0, | |
10040 | rs6000_compare_op1); | |
10041 | break; | |
10042 | ||
10043 | default: | |
10044 | gcc_unreachable (); | |
10045 | } | |
a3170dc6 | 10046 | break; |
37409796 | 10047 | |
423c1189 | 10048 | case GT: case GTU: case UNGT: case UNGE: case GE: case GEU: |
37409796 NS |
10049 | switch (op_mode) |
10050 | { | |
10051 | case SFmode: | |
10052 | cmp = flag_unsafe_math_optimizations | |
10053 | ? gen_tstsfgt_gpr (compare_result, rs6000_compare_op0, | |
10054 | rs6000_compare_op1) | |
10055 | : gen_cmpsfgt_gpr (compare_result, rs6000_compare_op0, | |
10056 | rs6000_compare_op1); | |
10057 | break; | |
10058 | ||
10059 | case DFmode: | |
10060 | cmp = flag_unsafe_math_optimizations | |
10061 | ? gen_tstdfgt_gpr (compare_result, rs6000_compare_op0, | |
10062 | rs6000_compare_op1) | |
10063 | : gen_cmpdfgt_gpr (compare_result, rs6000_compare_op0, | |
10064 | rs6000_compare_op1); | |
10065 | break; | |
10066 | ||
10067 | default: | |
10068 | gcc_unreachable (); | |
10069 | } | |
a3170dc6 | 10070 | break; |
37409796 | 10071 | |
423c1189 | 10072 | case LT: case LTU: case UNLT: case UNLE: case LE: case LEU: |
37409796 NS |
10073 | switch (op_mode) |
10074 | { | |
10075 | case SFmode: | |
10076 | cmp = flag_unsafe_math_optimizations | |
10077 | ? gen_tstsflt_gpr (compare_result, rs6000_compare_op0, | |
10078 | rs6000_compare_op1) | |
10079 | : gen_cmpsflt_gpr (compare_result, rs6000_compare_op0, | |
10080 | rs6000_compare_op1); | |
10081 | break; | |
10082 | ||
10083 | case DFmode: | |
10084 | cmp = flag_unsafe_math_optimizations | |
10085 | ? gen_tstdflt_gpr (compare_result, rs6000_compare_op0, | |
10086 | rs6000_compare_op1) | |
10087 | : gen_cmpdflt_gpr (compare_result, rs6000_compare_op0, | |
10088 | rs6000_compare_op1); | |
10089 | break; | |
10090 | ||
10091 | default: | |
10092 | gcc_unreachable (); | |
10093 | } | |
a3170dc6 | 10094 | break; |
4d4cbc0e | 10095 | default: |
37409796 | 10096 | gcc_unreachable (); |
a3170dc6 AH |
10097 | } |
10098 | ||
10099 | /* Synthesize LE and GE from LT/GT || EQ. */ | |
10100 | if (code == LE || code == GE || code == LEU || code == GEU) | |
10101 | { | |
a3170dc6 AH |
10102 | emit_insn (cmp); |
10103 | ||
10104 | switch (code) | |
10105 | { | |
10106 | case LE: code = LT; break; | |
10107 | case GE: code = GT; break; | |
10108 | case LEU: code = LT; break; | |
10109 | case GEU: code = GT; break; | |
37409796 | 10110 | default: gcc_unreachable (); |
a3170dc6 AH |
10111 | } |
10112 | ||
a3170dc6 AH |
10113 | compare_result2 = gen_reg_rtx (CCFPmode); |
10114 | ||
10115 | /* Do the EQ. */ | |
37409796 NS |
10116 | switch (op_mode) |
10117 | { | |
10118 | case SFmode: | |
10119 | cmp = flag_unsafe_math_optimizations | |
10120 | ? gen_tstsfeq_gpr (compare_result2, rs6000_compare_op0, | |
10121 | rs6000_compare_op1) | |
10122 | : gen_cmpsfeq_gpr (compare_result2, rs6000_compare_op0, | |
10123 | rs6000_compare_op1); | |
10124 | break; | |
10125 | ||
10126 | case DFmode: | |
10127 | cmp = flag_unsafe_math_optimizations | |
10128 | ? gen_tstdfeq_gpr (compare_result2, rs6000_compare_op0, | |
10129 | rs6000_compare_op1) | |
10130 | : gen_cmpdfeq_gpr (compare_result2, rs6000_compare_op0, | |
10131 | rs6000_compare_op1); | |
10132 | break; | |
10133 | ||
10134 | default: | |
10135 | gcc_unreachable (); | |
10136 | } | |
a3170dc6 AH |
10137 | emit_insn (cmp); |
10138 | ||
a3170dc6 | 10139 | /* OR them together. */ |
64022b5d AH |
10140 | or_result = gen_reg_rtx (CCFPmode); |
10141 | cmp = gen_e500_cr_ior_compare (or_result, compare_result, | |
10142 | compare_result2); | |
a3170dc6 AH |
10143 | compare_result = or_result; |
10144 | code = EQ; | |
10145 | } | |
10146 | else | |
10147 | { | |
a3170dc6 | 10148 | if (code == NE || code == LTGT) |
a3170dc6 | 10149 | code = NE; |
423c1189 AH |
10150 | else |
10151 | code = EQ; | |
a3170dc6 AH |
10152 | } |
10153 | ||
10154 | emit_insn (cmp); | |
10155 | } | |
10156 | else | |
de17c25f DE |
10157 | { |
10158 | /* Generate XLC-compatible TFmode compare as PARALLEL with extra | |
10159 | CLOBBERs to match cmptf_internal2 pattern. */ | |
10160 | if (comp_mode == CCFPmode && TARGET_XL_COMPAT | |
10161 | && GET_MODE (rs6000_compare_op0) == TFmode | |
10162 | && (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) | |
10163 | && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128) | |
10164 | emit_insn (gen_rtx_PARALLEL (VOIDmode, | |
10165 | gen_rtvec (9, | |
10166 | gen_rtx_SET (VOIDmode, | |
10167 | compare_result, | |
10168 | gen_rtx_COMPARE (comp_mode, | |
10169 | rs6000_compare_op0, | |
10170 | rs6000_compare_op1)), | |
10171 | gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)), | |
10172 | gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)), | |
10173 | gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)), | |
10174 | gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)), | |
10175 | gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)), | |
10176 | gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)), | |
10177 | gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)), | |
10178 | gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode))))); | |
10179 | else | |
10180 | emit_insn (gen_rtx_SET (VOIDmode, compare_result, | |
10181 | gen_rtx_COMPARE (comp_mode, | |
10182 | rs6000_compare_op0, | |
10183 | rs6000_compare_op1))); | |
10184 | } | |
f676971a | 10185 | |
ca5adc63 | 10186 | /* Some kinds of FP comparisons need an OR operation; |
e7108df9 | 10187 | under flag_finite_math_only we don't bother. */ |
39a10a29 | 10188 | if (rs6000_compare_fp_p |
e7108df9 DE |
10189 | && !flag_finite_math_only |
10190 | && !(TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS) | |
39a10a29 GK |
10191 | && (code == LE || code == GE |
10192 | || code == UNEQ || code == LTGT | |
10193 | || code == UNGT || code == UNLT)) | |
10194 | { | |
10195 | enum rtx_code or1, or2; | |
10196 | rtx or1_rtx, or2_rtx, compare2_rtx; | |
10197 | rtx or_result = gen_reg_rtx (CCEQmode); | |
f676971a | 10198 | |
39a10a29 GK |
10199 | switch (code) |
10200 | { | |
10201 | case LE: or1 = LT; or2 = EQ; break; | |
10202 | case GE: or1 = GT; or2 = EQ; break; | |
10203 | case UNEQ: or1 = UNORDERED; or2 = EQ; break; | |
10204 | case LTGT: or1 = LT; or2 = GT; break; | |
10205 | case UNGT: or1 = UNORDERED; or2 = GT; break; | |
10206 | case UNLT: or1 = UNORDERED; or2 = LT; break; | |
37409796 | 10207 | default: gcc_unreachable (); |
39a10a29 GK |
10208 | } |
10209 | validate_condition_mode (or1, comp_mode); | |
10210 | validate_condition_mode (or2, comp_mode); | |
1c563bed KH |
10211 | or1_rtx = gen_rtx_fmt_ee (or1, SImode, compare_result, const0_rtx); |
10212 | or2_rtx = gen_rtx_fmt_ee (or2, SImode, compare_result, const0_rtx); | |
39a10a29 GK |
10213 | compare2_rtx = gen_rtx_COMPARE (CCEQmode, |
10214 | gen_rtx_IOR (SImode, or1_rtx, or2_rtx), | |
10215 | const_true_rtx); | |
10216 | emit_insn (gen_rtx_SET (VOIDmode, or_result, compare2_rtx)); | |
10217 | ||
10218 | compare_result = or_result; | |
10219 | code = EQ; | |
10220 | } | |
10221 | ||
10222 | validate_condition_mode (code, GET_MODE (compare_result)); | |
f676971a | 10223 | |
1c563bed | 10224 | return gen_rtx_fmt_ee (code, VOIDmode, compare_result, const0_rtx); |
39a10a29 GK |
10225 | } |
10226 | ||
10227 | ||
10228 | /* Emit the RTL for an sCOND pattern. */ | |
10229 | ||
10230 | void | |
a2369ed3 | 10231 | rs6000_emit_sCOND (enum rtx_code code, rtx result) |
39a10a29 GK |
10232 | { |
10233 | rtx condition_rtx; | |
10234 | enum machine_mode op_mode; | |
b7053a3f | 10235 | enum rtx_code cond_code; |
39a10a29 GK |
10236 | |
10237 | condition_rtx = rs6000_generate_compare (code); | |
b7053a3f GK |
10238 | cond_code = GET_CODE (condition_rtx); |
10239 | ||
423c1189 AH |
10240 | if (TARGET_E500 && rs6000_compare_fp_p |
10241 | && !TARGET_FPRS && TARGET_HARD_FLOAT) | |
10242 | { | |
10243 | rtx t; | |
10244 | ||
10245 | PUT_MODE (condition_rtx, SImode); | |
10246 | t = XEXP (condition_rtx, 0); | |
10247 | ||
37409796 | 10248 | gcc_assert (cond_code == NE || cond_code == EQ); |
423c1189 AH |
10249 | |
10250 | if (cond_code == NE) | |
64022b5d | 10251 | emit_insn (gen_e500_flip_gt_bit (t, t)); |
423c1189 | 10252 | |
64022b5d | 10253 | emit_insn (gen_move_from_CR_gt_bit (result, t)); |
423c1189 AH |
10254 | return; |
10255 | } | |
10256 | ||
b7053a3f GK |
10257 | if (cond_code == NE |
10258 | || cond_code == GE || cond_code == LE | |
10259 | || cond_code == GEU || cond_code == LEU | |
10260 | || cond_code == ORDERED || cond_code == UNGE || cond_code == UNLE) | |
10261 | { | |
10262 | rtx not_result = gen_reg_rtx (CCEQmode); | |
10263 | rtx not_op, rev_cond_rtx; | |
10264 | enum machine_mode cc_mode; | |
f676971a | 10265 | |
b7053a3f GK |
10266 | cc_mode = GET_MODE (XEXP (condition_rtx, 0)); |
10267 | ||
1c563bed | 10268 | rev_cond_rtx = gen_rtx_fmt_ee (rs6000_reverse_condition (cc_mode, cond_code), |
0f4c242b | 10269 | SImode, XEXP (condition_rtx, 0), const0_rtx); |
b7053a3f GK |
10270 | not_op = gen_rtx_COMPARE (CCEQmode, rev_cond_rtx, const0_rtx); |
10271 | emit_insn (gen_rtx_SET (VOIDmode, not_result, not_op)); | |
10272 | condition_rtx = gen_rtx_EQ (VOIDmode, not_result, const0_rtx); | |
10273 | } | |
39a10a29 GK |
10274 | |
10275 | op_mode = GET_MODE (rs6000_compare_op0); | |
10276 | if (op_mode == VOIDmode) | |
10277 | op_mode = GET_MODE (rs6000_compare_op1); | |
10278 | ||
10279 | if (TARGET_POWERPC64 && (op_mode == DImode || rs6000_compare_fp_p)) | |
10280 | { | |
10281 | PUT_MODE (condition_rtx, DImode); | |
10282 | convert_move (result, condition_rtx, 0); | |
10283 | } | |
10284 | else | |
10285 | { | |
10286 | PUT_MODE (condition_rtx, SImode); | |
10287 | emit_insn (gen_rtx_SET (VOIDmode, result, condition_rtx)); | |
10288 | } | |
10289 | } | |
10290 | ||
39a10a29 GK |
10291 | /* Emit a branch of kind CODE to location LOC. */ |
10292 | ||
10293 | void | |
a2369ed3 | 10294 | rs6000_emit_cbranch (enum rtx_code code, rtx loc) |
39a10a29 GK |
10295 | { |
10296 | rtx condition_rtx, loc_ref; | |
10297 | ||
10298 | condition_rtx = rs6000_generate_compare (code); | |
10299 | loc_ref = gen_rtx_LABEL_REF (VOIDmode, loc); | |
10300 | emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, | |
10301 | gen_rtx_IF_THEN_ELSE (VOIDmode, condition_rtx, | |
10302 | loc_ref, pc_rtx))); | |
10303 | } | |
10304 | ||
12a4e8c5 GK |
10305 | /* Return the string to output a conditional branch to LABEL, which is |
10306 | the operand number of the label, or -1 if the branch is really a | |
f676971a | 10307 | conditional return. |
12a4e8c5 GK |
10308 | |
10309 | OP is the conditional expression. XEXP (OP, 0) is assumed to be a | |
10310 | condition code register and its mode specifies what kind of | |
10311 | comparison we made. | |
10312 | ||
a0ab749a | 10313 | REVERSED is nonzero if we should reverse the sense of the comparison. |
12a4e8c5 GK |
10314 | |
10315 | INSN is the insn. */ | |
10316 | ||
10317 | char * | |
a2369ed3 | 10318 | output_cbranch (rtx op, const char *label, int reversed, rtx insn) |
12a4e8c5 GK |
10319 | { |
10320 | static char string[64]; | |
10321 | enum rtx_code code = GET_CODE (op); | |
10322 | rtx cc_reg = XEXP (op, 0); | |
10323 | enum machine_mode mode = GET_MODE (cc_reg); | |
10324 | int cc_regno = REGNO (cc_reg) - CR0_REGNO; | |
39a10a29 | 10325 | int need_longbranch = label != NULL && get_attr_length (insn) == 8; |
12a4e8c5 GK |
10326 | int really_reversed = reversed ^ need_longbranch; |
10327 | char *s = string; | |
10328 | const char *ccode; | |
10329 | const char *pred; | |
10330 | rtx note; | |
10331 | ||
39a10a29 GK |
10332 | validate_condition_mode (code, mode); |
10333 | ||
10334 | /* Work out which way this really branches. We could use | |
10335 | reverse_condition_maybe_unordered here always but this | |
10336 | makes the resulting assembler clearer. */ | |
12a4e8c5 | 10337 | if (really_reversed) |
de40e1df DJ |
10338 | { |
10339 | /* Reversal of FP compares takes care -- an ordered compare | |
10340 | becomes an unordered compare and vice versa. */ | |
10341 | if (mode == CCFPmode) | |
10342 | code = reverse_condition_maybe_unordered (code); | |
10343 | else | |
10344 | code = reverse_condition (code); | |
10345 | } | |
12a4e8c5 | 10346 | |
993f19a8 | 10347 | if ((TARGET_E500 && !TARGET_FPRS && TARGET_HARD_FLOAT) && mode == CCFPmode) |
a3170dc6 AH |
10348 | { |
10349 | /* The efscmp/tst* instructions twiddle bit 2, which maps nicely | |
10350 | to the GT bit. */ | |
37409796 NS |
10351 | switch (code) |
10352 | { | |
10353 | case EQ: | |
10354 | /* Opposite of GT. */ | |
10355 | code = GT; | |
10356 | break; | |
10357 | ||
10358 | case NE: | |
10359 | code = UNLE; | |
10360 | break; | |
10361 | ||
10362 | default: | |
10363 | gcc_unreachable (); | |
10364 | } | |
a3170dc6 AH |
10365 | } |
10366 | ||
39a10a29 | 10367 | switch (code) |
12a4e8c5 GK |
10368 | { |
10369 | /* Not all of these are actually distinct opcodes, but | |
10370 | we distinguish them for clarity of the resulting assembler. */ | |
50a0b056 GK |
10371 | case NE: case LTGT: |
10372 | ccode = "ne"; break; | |
10373 | case EQ: case UNEQ: | |
10374 | ccode = "eq"; break; | |
f676971a | 10375 | case GE: case GEU: |
50a0b056 | 10376 | ccode = "ge"; break; |
f676971a | 10377 | case GT: case GTU: case UNGT: |
50a0b056 | 10378 | ccode = "gt"; break; |
f676971a | 10379 | case LE: case LEU: |
50a0b056 | 10380 | ccode = "le"; break; |
f676971a | 10381 | case LT: case LTU: case UNLT: |
50a0b056 | 10382 | ccode = "lt"; break; |
12a4e8c5 GK |
10383 | case UNORDERED: ccode = "un"; break; |
10384 | case ORDERED: ccode = "nu"; break; | |
10385 | case UNGE: ccode = "nl"; break; | |
10386 | case UNLE: ccode = "ng"; break; | |
10387 | default: | |
37409796 | 10388 | gcc_unreachable (); |
12a4e8c5 | 10389 | } |
f676971a EC |
10390 | |
10391 | /* Maybe we have a guess as to how likely the branch is. | |
94a54f47 | 10392 | The old mnemonics don't have a way to specify this information. */ |
f4857b9b | 10393 | pred = ""; |
12a4e8c5 GK |
10394 | note = find_reg_note (insn, REG_BR_PROB, NULL_RTX); |
10395 | if (note != NULL_RTX) | |
10396 | { | |
10397 | /* PROB is the difference from 50%. */ | |
10398 | int prob = INTVAL (XEXP (note, 0)) - REG_BR_PROB_BASE / 2; | |
f4857b9b AM |
10399 | |
10400 | /* Only hint for highly probable/improbable branches on newer | |
10401 | cpus as static prediction overrides processor dynamic | |
10402 | prediction. For older cpus we may as well always hint, but | |
10403 | assume not taken for branches that are very close to 50% as a | |
10404 | mispredicted taken branch is more expensive than a | |
f676971a | 10405 | mispredicted not-taken branch. */ |
ec507f2d | 10406 | if (rs6000_always_hint |
f4857b9b AM |
10407 | || abs (prob) > REG_BR_PROB_BASE / 100 * 48) |
10408 | { | |
10409 | if (abs (prob) > REG_BR_PROB_BASE / 20 | |
10410 | && ((prob > 0) ^ need_longbranch)) | |
c4ad648e | 10411 | pred = "+"; |
f4857b9b AM |
10412 | else |
10413 | pred = "-"; | |
10414 | } | |
12a4e8c5 | 10415 | } |
12a4e8c5 GK |
10416 | |
10417 | if (label == NULL) | |
94a54f47 | 10418 | s += sprintf (s, "{b%sr|b%slr%s} ", ccode, ccode, pred); |
12a4e8c5 | 10419 | else |
94a54f47 | 10420 | s += sprintf (s, "{b%s|b%s%s} ", ccode, ccode, pred); |
12a4e8c5 | 10421 | |
37c67319 | 10422 | /* We need to escape any '%' characters in the reg_names string. |
a3c9585f | 10423 | Assume they'd only be the first character.... */ |
37c67319 GK |
10424 | if (reg_names[cc_regno + CR0_REGNO][0] == '%') |
10425 | *s++ = '%'; | |
94a54f47 | 10426 | s += sprintf (s, "%s", reg_names[cc_regno + CR0_REGNO]); |
12a4e8c5 GK |
10427 | |
10428 | if (label != NULL) | |
10429 | { | |
10430 | /* If the branch distance was too far, we may have to use an | |
10431 | unconditional branch to go the distance. */ | |
10432 | if (need_longbranch) | |
44518ddd | 10433 | s += sprintf (s, ",$+8\n\tb %s", label); |
12a4e8c5 GK |
10434 | else |
10435 | s += sprintf (s, ",%s", label); | |
10436 | } | |
10437 | ||
10438 | return string; | |
10439 | } | |
50a0b056 | 10440 | |
64022b5d | 10441 | /* Return the string to flip the GT bit on a CR. */ |
423c1189 | 10442 | char * |
64022b5d | 10443 | output_e500_flip_gt_bit (rtx dst, rtx src) |
423c1189 AH |
10444 | { |
10445 | static char string[64]; | |
10446 | int a, b; | |
10447 | ||
37409796 NS |
10448 | gcc_assert (GET_CODE (dst) == REG && CR_REGNO_P (REGNO (dst)) |
10449 | && GET_CODE (src) == REG && CR_REGNO_P (REGNO (src))); | |
423c1189 | 10450 | |
64022b5d AH |
10451 | /* GT bit. */ |
10452 | a = 4 * (REGNO (dst) - CR0_REGNO) + 1; | |
10453 | b = 4 * (REGNO (src) - CR0_REGNO) + 1; | |
423c1189 AH |
10454 | |
10455 | sprintf (string, "crnot %d,%d", a, b); | |
10456 | return string; | |
10457 | } | |
10458 | ||
21213b4c DP |
10459 | /* Return insn index for the vector compare instruction for given CODE, |
10460 | and DEST_MODE, OP_MODE. Return INSN_NOT_AVAILABLE if valid insn is | |
10461 | not available. */ | |
10462 | ||
10463 | static int | |
94ff898d | 10464 | get_vec_cmp_insn (enum rtx_code code, |
21213b4c DP |
10465 | enum machine_mode dest_mode, |
10466 | enum machine_mode op_mode) | |
10467 | { | |
10468 | if (!TARGET_ALTIVEC) | |
10469 | return INSN_NOT_AVAILABLE; | |
10470 | ||
10471 | switch (code) | |
10472 | { | |
10473 | case EQ: | |
10474 | if (dest_mode == V16QImode && op_mode == V16QImode) | |
10475 | return UNSPEC_VCMPEQUB; | |
10476 | if (dest_mode == V8HImode && op_mode == V8HImode) | |
10477 | return UNSPEC_VCMPEQUH; | |
10478 | if (dest_mode == V4SImode && op_mode == V4SImode) | |
10479 | return UNSPEC_VCMPEQUW; | |
10480 | if (dest_mode == V4SImode && op_mode == V4SFmode) | |
10481 | return UNSPEC_VCMPEQFP; | |
10482 | break; | |
10483 | case GE: | |
10484 | if (dest_mode == V4SImode && op_mode == V4SFmode) | |
10485 | return UNSPEC_VCMPGEFP; | |
10486 | case GT: | |
10487 | if (dest_mode == V16QImode && op_mode == V16QImode) | |
10488 | return UNSPEC_VCMPGTSB; | |
10489 | if (dest_mode == V8HImode && op_mode == V8HImode) | |
10490 | return UNSPEC_VCMPGTSH; | |
10491 | if (dest_mode == V4SImode && op_mode == V4SImode) | |
10492 | return UNSPEC_VCMPGTSW; | |
10493 | if (dest_mode == V4SImode && op_mode == V4SFmode) | |
10494 | return UNSPEC_VCMPGTFP; | |
10495 | break; | |
10496 | case GTU: | |
10497 | if (dest_mode == V16QImode && op_mode == V16QImode) | |
10498 | return UNSPEC_VCMPGTUB; | |
10499 | if (dest_mode == V8HImode && op_mode == V8HImode) | |
10500 | return UNSPEC_VCMPGTUH; | |
10501 | if (dest_mode == V4SImode && op_mode == V4SImode) | |
10502 | return UNSPEC_VCMPGTUW; | |
10503 | break; | |
10504 | default: | |
10505 | break; | |
10506 | } | |
10507 | return INSN_NOT_AVAILABLE; | |
10508 | } | |
10509 | ||
10510 | /* Emit vector compare for operands OP0 and OP1 using code RCODE. | |
10511 | DMODE is expected destination mode. This is a recursive function. */ | |
10512 | ||
10513 | static rtx | |
10514 | rs6000_emit_vector_compare (enum rtx_code rcode, | |
10515 | rtx op0, rtx op1, | |
10516 | enum machine_mode dmode) | |
10517 | { | |
10518 | int vec_cmp_insn; | |
10519 | rtx mask; | |
10520 | enum machine_mode dest_mode; | |
10521 | enum machine_mode op_mode = GET_MODE (op1); | |
10522 | ||
37409796 NS |
10523 | gcc_assert (TARGET_ALTIVEC); |
10524 | gcc_assert (GET_MODE (op0) == GET_MODE (op1)); | |
21213b4c DP |
10525 | |
10526 | /* Floating point vector compare instructions uses destination V4SImode. | |
10527 | Move destination to appropriate mode later. */ | |
10528 | if (dmode == V4SFmode) | |
10529 | dest_mode = V4SImode; | |
10530 | else | |
10531 | dest_mode = dmode; | |
10532 | ||
10533 | mask = gen_reg_rtx (dest_mode); | |
10534 | vec_cmp_insn = get_vec_cmp_insn (rcode, dest_mode, op_mode); | |
10535 | ||
10536 | if (vec_cmp_insn == INSN_NOT_AVAILABLE) | |
10537 | { | |
10538 | bool swap_operands = false; | |
10539 | bool try_again = false; | |
10540 | switch (rcode) | |
10541 | { | |
10542 | case LT: | |
10543 | rcode = GT; | |
10544 | swap_operands = true; | |
10545 | try_again = true; | |
10546 | break; | |
10547 | case LTU: | |
10548 | rcode = GTU; | |
10549 | swap_operands = true; | |
10550 | try_again = true; | |
10551 | break; | |
10552 | case NE: | |
10553 | /* Treat A != B as ~(A==B). */ | |
10554 | { | |
10555 | enum insn_code nor_code; | |
10556 | rtx eq_rtx = rs6000_emit_vector_compare (EQ, op0, op1, | |
10557 | dest_mode); | |
94ff898d | 10558 | |
21213b4c | 10559 | nor_code = one_cmpl_optab->handlers[(int)dest_mode].insn_code; |
37409796 | 10560 | gcc_assert (nor_code != CODE_FOR_nothing); |
21213b4c DP |
10561 | emit_insn (GEN_FCN (nor_code) (mask, eq_rtx)); |
10562 | ||
10563 | if (dmode != dest_mode) | |
10564 | { | |
10565 | rtx temp = gen_reg_rtx (dest_mode); | |
10566 | convert_move (temp, mask, 0); | |
10567 | return temp; | |
10568 | } | |
10569 | return mask; | |
10570 | } | |
10571 | break; | |
10572 | case GE: | |
10573 | case GEU: | |
10574 | case LE: | |
10575 | case LEU: | |
10576 | /* Try GT/GTU/LT/LTU OR EQ */ | |
10577 | { | |
10578 | rtx c_rtx, eq_rtx; | |
10579 | enum insn_code ior_code; | |
10580 | enum rtx_code new_code; | |
10581 | ||
37409796 NS |
10582 | switch (rcode) |
10583 | { | |
10584 | case GE: | |
10585 | new_code = GT; | |
10586 | break; | |
10587 | ||
10588 | case GEU: | |
10589 | new_code = GTU; | |
10590 | break; | |
10591 | ||
10592 | case LE: | |
10593 | new_code = LT; | |
10594 | break; | |
10595 | ||
10596 | case LEU: | |
10597 | new_code = LTU; | |
10598 | break; | |
10599 | ||
10600 | default: | |
10601 | gcc_unreachable (); | |
10602 | } | |
21213b4c DP |
10603 | |
10604 | c_rtx = rs6000_emit_vector_compare (new_code, | |
10605 | op0, op1, dest_mode); | |
10606 | eq_rtx = rs6000_emit_vector_compare (EQ, op0, op1, | |
10607 | dest_mode); | |
10608 | ||
10609 | ior_code = ior_optab->handlers[(int)dest_mode].insn_code; | |
37409796 | 10610 | gcc_assert (ior_code != CODE_FOR_nothing); |
21213b4c DP |
10611 | emit_insn (GEN_FCN (ior_code) (mask, c_rtx, eq_rtx)); |
10612 | if (dmode != dest_mode) | |
10613 | { | |
10614 | rtx temp = gen_reg_rtx (dest_mode); | |
10615 | convert_move (temp, mask, 0); | |
10616 | return temp; | |
10617 | } | |
10618 | return mask; | |
10619 | } | |
10620 | break; | |
10621 | default: | |
37409796 | 10622 | gcc_unreachable (); |
21213b4c DP |
10623 | } |
10624 | ||
10625 | if (try_again) | |
10626 | { | |
10627 | vec_cmp_insn = get_vec_cmp_insn (rcode, dest_mode, op_mode); | |
37409796 NS |
10628 | /* You only get two chances. */ |
10629 | gcc_assert (vec_cmp_insn != INSN_NOT_AVAILABLE); | |
21213b4c DP |
10630 | } |
10631 | ||
10632 | if (swap_operands) | |
10633 | { | |
10634 | rtx tmp; | |
10635 | tmp = op0; | |
10636 | op0 = op1; | |
10637 | op1 = tmp; | |
10638 | } | |
10639 | } | |
10640 | ||
915167f5 GK |
10641 | emit_insn (gen_rtx_SET (VOIDmode, mask, |
10642 | gen_rtx_UNSPEC (dest_mode, | |
10643 | gen_rtvec (2, op0, op1), | |
10644 | vec_cmp_insn))); | |
21213b4c DP |
10645 | if (dmode != dest_mode) |
10646 | { | |
10647 | rtx temp = gen_reg_rtx (dest_mode); | |
10648 | convert_move (temp, mask, 0); | |
10649 | return temp; | |
10650 | } | |
10651 | return mask; | |
10652 | } | |
10653 | ||
10654 | /* Return vector select instruction for MODE. Return INSN_NOT_AVAILABLE, if | |
10655 | valid insn doesn exist for given mode. */ | |
10656 | ||
10657 | static int | |
10658 | get_vsel_insn (enum machine_mode mode) | |
10659 | { | |
10660 | switch (mode) | |
10661 | { | |
10662 | case V4SImode: | |
10663 | return UNSPEC_VSEL4SI; | |
10664 | break; | |
10665 | case V4SFmode: | |
10666 | return UNSPEC_VSEL4SF; | |
10667 | break; | |
10668 | case V8HImode: | |
10669 | return UNSPEC_VSEL8HI; | |
10670 | break; | |
10671 | case V16QImode: | |
10672 | return UNSPEC_VSEL16QI; | |
10673 | break; | |
10674 | default: | |
10675 | return INSN_NOT_AVAILABLE; | |
10676 | break; | |
10677 | } | |
10678 | return INSN_NOT_AVAILABLE; | |
10679 | } | |
10680 | ||
10681 | /* Emit vector select insn where DEST is destination using | |
10682 | operands OP1, OP2 and MASK. */ | |
10683 | ||
10684 | static void | |
10685 | rs6000_emit_vector_select (rtx dest, rtx op1, rtx op2, rtx mask) | |
10686 | { | |
10687 | rtx t, temp; | |
10688 | enum machine_mode dest_mode = GET_MODE (dest); | |
10689 | int vsel_insn_index = get_vsel_insn (GET_MODE (dest)); | |
10690 | ||
10691 | temp = gen_reg_rtx (dest_mode); | |
94ff898d | 10692 | |
19f1ebc7 DP |
10693 | /* For each vector element, select op1 when mask is 1 otherwise |
10694 | select op2. */ | |
915167f5 GK |
10695 | t = gen_rtx_SET (VOIDmode, temp, |
10696 | gen_rtx_UNSPEC (dest_mode, | |
10697 | gen_rtvec (3, op2, op1, mask), | |
10698 | vsel_insn_index)); | |
21213b4c DP |
10699 | emit_insn (t); |
10700 | emit_move_insn (dest, temp); | |
10701 | return; | |
10702 | } | |
10703 | ||
94ff898d | 10704 | /* Emit vector conditional expression. |
21213b4c DP |
10705 | DEST is destination. OP1 and OP2 are two VEC_COND_EXPR operands. |
10706 | CC_OP0 and CC_OP1 are the two operands for the relation operation COND. */ | |
10707 | ||
10708 | int | |
10709 | rs6000_emit_vector_cond_expr (rtx dest, rtx op1, rtx op2, | |
10710 | rtx cond, rtx cc_op0, rtx cc_op1) | |
10711 | { | |
10712 | enum machine_mode dest_mode = GET_MODE (dest); | |
10713 | enum rtx_code rcode = GET_CODE (cond); | |
10714 | rtx mask; | |
10715 | ||
10716 | if (!TARGET_ALTIVEC) | |
10717 | return 0; | |
10718 | ||
10719 | /* Get the vector mask for the given relational operations. */ | |
10720 | mask = rs6000_emit_vector_compare (rcode, cc_op0, cc_op1, dest_mode); | |
10721 | ||
10722 | rs6000_emit_vector_select (dest, op1, op2, mask); | |
10723 | ||
10724 | return 1; | |
10725 | } | |
10726 | ||
50a0b056 GK |
10727 | /* Emit a conditional move: move TRUE_COND to DEST if OP of the |
10728 | operands of the last comparison is nonzero/true, FALSE_COND if it | |
10729 | is zero/false. Return 0 if the hardware has no such operation. */ | |
a4f6c312 | 10730 | |
50a0b056 | 10731 | int |
a2369ed3 | 10732 | rs6000_emit_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond) |
50a0b056 GK |
10733 | { |
10734 | enum rtx_code code = GET_CODE (op); | |
10735 | rtx op0 = rs6000_compare_op0; | |
10736 | rtx op1 = rs6000_compare_op1; | |
10737 | REAL_VALUE_TYPE c1; | |
3148ad6d DJ |
10738 | enum machine_mode compare_mode = GET_MODE (op0); |
10739 | enum machine_mode result_mode = GET_MODE (dest); | |
50a0b056 | 10740 | rtx temp; |
add2402e | 10741 | bool is_against_zero; |
50a0b056 | 10742 | |
a3c9585f | 10743 | /* These modes should always match. */ |
a3170dc6 AH |
10744 | if (GET_MODE (op1) != compare_mode |
10745 | /* In the isel case however, we can use a compare immediate, so | |
10746 | op1 may be a small constant. */ | |
10747 | && (!TARGET_ISEL || !short_cint_operand (op1, VOIDmode))) | |
3148ad6d | 10748 | return 0; |
178c3eff | 10749 | if (GET_MODE (true_cond) != result_mode) |
3148ad6d | 10750 | return 0; |
178c3eff | 10751 | if (GET_MODE (false_cond) != result_mode) |
3148ad6d DJ |
10752 | return 0; |
10753 | ||
50a0b056 | 10754 | /* First, work out if the hardware can do this at all, or |
a3c9585f | 10755 | if it's too slow.... */ |
50a0b056 | 10756 | if (! rs6000_compare_fp_p) |
a3170dc6 AH |
10757 | { |
10758 | if (TARGET_ISEL) | |
10759 | return rs6000_emit_int_cmove (dest, op, true_cond, false_cond); | |
10760 | return 0; | |
10761 | } | |
fef98bf2 AH |
10762 | else if (TARGET_E500 && TARGET_HARD_FLOAT && !TARGET_FPRS |
10763 | && GET_MODE_CLASS (compare_mode) == MODE_FLOAT) | |
10764 | return 0; | |
50a0b056 | 10765 | |
add2402e | 10766 | is_against_zero = op1 == CONST0_RTX (compare_mode); |
94ff898d | 10767 | |
add2402e GK |
10768 | /* A floating-point subtract might overflow, underflow, or produce |
10769 | an inexact result, thus changing the floating-point flags, so it | |
10770 | can't be generated if we care about that. It's safe if one side | |
10771 | of the construct is zero, since then no subtract will be | |
10772 | generated. */ | |
10773 | if (GET_MODE_CLASS (compare_mode) == MODE_FLOAT | |
10774 | && flag_trapping_math && ! is_against_zero) | |
10775 | return 0; | |
10776 | ||
50a0b056 GK |
10777 | /* Eliminate half of the comparisons by switching operands, this |
10778 | makes the remaining code simpler. */ | |
10779 | if (code == UNLT || code == UNGT || code == UNORDERED || code == NE | |
bc9ec0e0 | 10780 | || code == LTGT || code == LT || code == UNLE) |
50a0b056 GK |
10781 | { |
10782 | code = reverse_condition_maybe_unordered (code); | |
10783 | temp = true_cond; | |
10784 | true_cond = false_cond; | |
10785 | false_cond = temp; | |
10786 | } | |
10787 | ||
10788 | /* UNEQ and LTGT take four instructions for a comparison with zero, | |
10789 | it'll probably be faster to use a branch here too. */ | |
bc9ec0e0 | 10790 | if (code == UNEQ && HONOR_NANS (compare_mode)) |
50a0b056 | 10791 | return 0; |
f676971a | 10792 | |
50a0b056 GK |
10793 | if (GET_CODE (op1) == CONST_DOUBLE) |
10794 | REAL_VALUE_FROM_CONST_DOUBLE (c1, op1); | |
f676971a | 10795 | |
b6d08ca1 | 10796 | /* We're going to try to implement comparisons by performing |
50a0b056 GK |
10797 | a subtract, then comparing against zero. Unfortunately, |
10798 | Inf - Inf is NaN which is not zero, and so if we don't | |
27d30956 | 10799 | know that the operand is finite and the comparison |
50a0b056 | 10800 | would treat EQ different to UNORDERED, we can't do it. */ |
bc9ec0e0 | 10801 | if (HONOR_INFINITIES (compare_mode) |
50a0b056 | 10802 | && code != GT && code != UNGE |
045572c7 | 10803 | && (GET_CODE (op1) != CONST_DOUBLE || real_isinf (&c1)) |
50a0b056 GK |
10804 | /* Constructs of the form (a OP b ? a : b) are safe. */ |
10805 | && ((! rtx_equal_p (op0, false_cond) && ! rtx_equal_p (op1, false_cond)) | |
f676971a | 10806 | || (! rtx_equal_p (op0, true_cond) |
50a0b056 GK |
10807 | && ! rtx_equal_p (op1, true_cond)))) |
10808 | return 0; | |
add2402e | 10809 | |
50a0b056 GK |
10810 | /* At this point we know we can use fsel. */ |
10811 | ||
10812 | /* Reduce the comparison to a comparison against zero. */ | |
add2402e GK |
10813 | if (! is_against_zero) |
10814 | { | |
10815 | temp = gen_reg_rtx (compare_mode); | |
10816 | emit_insn (gen_rtx_SET (VOIDmode, temp, | |
10817 | gen_rtx_MINUS (compare_mode, op0, op1))); | |
10818 | op0 = temp; | |
10819 | op1 = CONST0_RTX (compare_mode); | |
10820 | } | |
50a0b056 GK |
10821 | |
10822 | /* If we don't care about NaNs we can reduce some of the comparisons | |
10823 | down to faster ones. */ | |
bc9ec0e0 | 10824 | if (! HONOR_NANS (compare_mode)) |
50a0b056 GK |
10825 | switch (code) |
10826 | { | |
10827 | case GT: | |
10828 | code = LE; | |
10829 | temp = true_cond; | |
10830 | true_cond = false_cond; | |
10831 | false_cond = temp; | |
10832 | break; | |
10833 | case UNGE: | |
10834 | code = GE; | |
10835 | break; | |
10836 | case UNEQ: | |
10837 | code = EQ; | |
10838 | break; | |
10839 | default: | |
10840 | break; | |
10841 | } | |
10842 | ||
10843 | /* Now, reduce everything down to a GE. */ | |
10844 | switch (code) | |
10845 | { | |
10846 | case GE: | |
10847 | break; | |
10848 | ||
10849 | case LE: | |
3148ad6d DJ |
10850 | temp = gen_reg_rtx (compare_mode); |
10851 | emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0))); | |
50a0b056 GK |
10852 | op0 = temp; |
10853 | break; | |
10854 | ||
10855 | case ORDERED: | |
3148ad6d DJ |
10856 | temp = gen_reg_rtx (compare_mode); |
10857 | emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_ABS (compare_mode, op0))); | |
50a0b056 GK |
10858 | op0 = temp; |
10859 | break; | |
10860 | ||
10861 | case EQ: | |
3148ad6d | 10862 | temp = gen_reg_rtx (compare_mode); |
f676971a | 10863 | emit_insn (gen_rtx_SET (VOIDmode, temp, |
3148ad6d DJ |
10864 | gen_rtx_NEG (compare_mode, |
10865 | gen_rtx_ABS (compare_mode, op0)))); | |
50a0b056 GK |
10866 | op0 = temp; |
10867 | break; | |
10868 | ||
10869 | case UNGE: | |
bc9ec0e0 | 10870 | /* a UNGE 0 <-> (a GE 0 || -a UNLT 0) */ |
3148ad6d | 10871 | temp = gen_reg_rtx (result_mode); |
50a0b056 | 10872 | emit_insn (gen_rtx_SET (VOIDmode, temp, |
3148ad6d | 10873 | gen_rtx_IF_THEN_ELSE (result_mode, |
50a0b056 GK |
10874 | gen_rtx_GE (VOIDmode, |
10875 | op0, op1), | |
10876 | true_cond, false_cond))); | |
bc9ec0e0 GK |
10877 | false_cond = true_cond; |
10878 | true_cond = temp; | |
50a0b056 | 10879 | |
3148ad6d DJ |
10880 | temp = gen_reg_rtx (compare_mode); |
10881 | emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0))); | |
50a0b056 GK |
10882 | op0 = temp; |
10883 | break; | |
10884 | ||
10885 | case GT: | |
bc9ec0e0 | 10886 | /* a GT 0 <-> (a GE 0 && -a UNLT 0) */ |
3148ad6d | 10887 | temp = gen_reg_rtx (result_mode); |
50a0b056 | 10888 | emit_insn (gen_rtx_SET (VOIDmode, temp, |
f676971a | 10889 | gen_rtx_IF_THEN_ELSE (result_mode, |
50a0b056 GK |
10890 | gen_rtx_GE (VOIDmode, |
10891 | op0, op1), | |
10892 | true_cond, false_cond))); | |
bc9ec0e0 GK |
10893 | true_cond = false_cond; |
10894 | false_cond = temp; | |
50a0b056 | 10895 | |
3148ad6d DJ |
10896 | temp = gen_reg_rtx (compare_mode); |
10897 | emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0))); | |
50a0b056 GK |
10898 | op0 = temp; |
10899 | break; | |
10900 | ||
10901 | default: | |
37409796 | 10902 | gcc_unreachable (); |
50a0b056 GK |
10903 | } |
10904 | ||
10905 | emit_insn (gen_rtx_SET (VOIDmode, dest, | |
3148ad6d | 10906 | gen_rtx_IF_THEN_ELSE (result_mode, |
50a0b056 GK |
10907 | gen_rtx_GE (VOIDmode, |
10908 | op0, op1), | |
10909 | true_cond, false_cond))); | |
10910 | return 1; | |
10911 | } | |
10912 | ||
a3170dc6 AH |
10913 | /* Same as above, but for ints (isel). */ |
10914 | ||
10915 | static int | |
a2369ed3 | 10916 | rs6000_emit_int_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond) |
a3170dc6 AH |
10917 | { |
10918 | rtx condition_rtx, cr; | |
10919 | ||
10920 | /* All isel implementations thus far are 32-bits. */ | |
10921 | if (GET_MODE (rs6000_compare_op0) != SImode) | |
10922 | return 0; | |
10923 | ||
10924 | /* We still have to do the compare, because isel doesn't do a | |
10925 | compare, it just looks at the CRx bits set by a previous compare | |
10926 | instruction. */ | |
10927 | condition_rtx = rs6000_generate_compare (GET_CODE (op)); | |
10928 | cr = XEXP (condition_rtx, 0); | |
10929 | ||
10930 | if (GET_MODE (cr) == CCmode) | |
10931 | emit_insn (gen_isel_signed (dest, condition_rtx, | |
10932 | true_cond, false_cond, cr)); | |
10933 | else | |
10934 | emit_insn (gen_isel_unsigned (dest, condition_rtx, | |
10935 | true_cond, false_cond, cr)); | |
10936 | ||
10937 | return 1; | |
10938 | } | |
10939 | ||
10940 | const char * | |
a2369ed3 | 10941 | output_isel (rtx *operands) |
a3170dc6 AH |
10942 | { |
10943 | enum rtx_code code; | |
10944 | ||
10945 | code = GET_CODE (operands[1]); | |
10946 | if (code == GE || code == GEU || code == LE || code == LEU || code == NE) | |
10947 | { | |
10948 | PUT_CODE (operands[1], reverse_condition (code)); | |
10949 | return "isel %0,%3,%2,%j1"; | |
10950 | } | |
10951 | else | |
10952 | return "isel %0,%2,%3,%j1"; | |
10953 | } | |
10954 | ||
50a0b056 | 10955 | void |
a2369ed3 | 10956 | rs6000_emit_minmax (rtx dest, enum rtx_code code, rtx op0, rtx op1) |
50a0b056 GK |
10957 | { |
10958 | enum machine_mode mode = GET_MODE (op0); | |
5dc8d536 | 10959 | enum rtx_code c; |
50a0b056 | 10960 | rtx target; |
5dc8d536 AH |
10961 | |
10962 | if (code == SMAX || code == SMIN) | |
10963 | c = GE; | |
10964 | else | |
10965 | c = GEU; | |
10966 | ||
50a0b056 | 10967 | if (code == SMAX || code == UMAX) |
f676971a | 10968 | target = emit_conditional_move (dest, c, op0, op1, mode, |
50a0b056 GK |
10969 | op0, op1, mode, 0); |
10970 | else | |
f676971a | 10971 | target = emit_conditional_move (dest, c, op0, op1, mode, |
50a0b056 | 10972 | op1, op0, mode, 0); |
37409796 | 10973 | gcc_assert (target); |
50a0b056 GK |
10974 | if (target != dest) |
10975 | emit_move_insn (dest, target); | |
10976 | } | |
46c07df8 | 10977 | |
915167f5 GK |
10978 | /* Emit instructions to perform a load-reserved/store-conditional operation. |
10979 | The operation performed is an atomic | |
10980 | (set M (CODE:MODE M OP)) | |
10981 | If not NULL, BEFORE is atomically set to M before the operation, and | |
10982 | AFTER is set to M after the operation (that is, (CODE:MODE M OP)). | |
10983 | If SYNC_P then a memory barrier is emitted before the operation. | |
10984 | Either OP or M may be wrapped in a NOT operation. */ | |
10985 | ||
10986 | void | |
10987 | rs6000_emit_sync (enum rtx_code code, enum machine_mode mode, | |
10988 | rtx m, rtx op, rtx before_param, rtx after_param, | |
10989 | bool sync_p) | |
10990 | { | |
10991 | enum machine_mode used_mode; | |
10992 | rtx the_op, set_before, set_after, set_atomic, cc_scratch, before, after; | |
10993 | rtx used_m; | |
10994 | rtvec vec; | |
10995 | HOST_WIDE_INT imask = GET_MODE_MASK (mode); | |
10996 | rtx shift = NULL_RTX; | |
10997 | ||
10998 | if (sync_p) | |
10999 | emit_insn (gen_memory_barrier ()); | |
11000 | ||
11001 | if (GET_CODE (m) == NOT) | |
11002 | used_m = XEXP (m, 0); | |
11003 | else | |
11004 | used_m = m; | |
11005 | ||
11006 | /* If this is smaller than SImode, we'll have to use SImode with | |
11007 | adjustments. */ | |
11008 | if (mode == QImode || mode == HImode) | |
11009 | { | |
11010 | rtx newop, oldop; | |
11011 | ||
11012 | if (MEM_ALIGN (used_m) >= 32) | |
11013 | { | |
11014 | int ishift = 0; | |
11015 | if (BYTES_BIG_ENDIAN) | |
11016 | ishift = GET_MODE_BITSIZE (SImode) - GET_MODE_BITSIZE (mode); | |
11017 | ||
11018 | shift = GEN_INT (ishift); | |
11019 | } | |
11020 | else | |
11021 | { | |
11022 | rtx addrSI, aligned_addr; | |
11023 | ||
11024 | addrSI = force_reg (SImode, gen_lowpart_common (SImode, | |
11025 | XEXP (used_m, 0))); | |
11026 | shift = gen_reg_rtx (SImode); | |
11027 | ||
11028 | emit_insn (gen_rlwinm (shift, addrSI, GEN_INT (3), | |
11029 | GEN_INT (0x18))); | |
11030 | ||
11031 | aligned_addr = expand_binop (Pmode, and_optab, | |
11032 | XEXP (used_m, 0), | |
11033 | GEN_INT (-4), NULL_RTX, | |
11034 | 1, OPTAB_LIB_WIDEN); | |
11035 | used_m = change_address (used_m, SImode, aligned_addr); | |
11036 | set_mem_align (used_m, 32); | |
11037 | /* It's safe to keep the old alias set of USED_M, because | |
11038 | the operation is atomic and only affects the original | |
11039 | USED_M. */ | |
11040 | if (GET_CODE (m) == NOT) | |
11041 | m = gen_rtx_NOT (SImode, used_m); | |
11042 | else | |
11043 | m = used_m; | |
11044 | } | |
11045 | ||
11046 | if (GET_CODE (op) == NOT) | |
11047 | { | |
11048 | oldop = lowpart_subreg (SImode, XEXP (op, 0), mode); | |
11049 | oldop = gen_rtx_NOT (SImode, oldop); | |
11050 | } | |
11051 | else | |
11052 | oldop = lowpart_subreg (SImode, op, mode); | |
11053 | switch (code) | |
11054 | { | |
11055 | case IOR: | |
11056 | case XOR: | |
11057 | newop = expand_binop (SImode, and_optab, | |
11058 | oldop, GEN_INT (imask), NULL_RTX, | |
11059 | 1, OPTAB_LIB_WIDEN); | |
11060 | emit_insn (gen_ashlsi3 (newop, newop, shift)); | |
11061 | break; | |
11062 | ||
11063 | case AND: | |
11064 | newop = expand_binop (SImode, ior_optab, | |
11065 | oldop, GEN_INT (~imask), NULL_RTX, | |
11066 | 1, OPTAB_LIB_WIDEN); | |
11067 | emit_insn (gen_ashlsi3 (newop, newop, shift)); | |
11068 | break; | |
11069 | ||
11070 | case PLUS: | |
11071 | { | |
11072 | rtx mask; | |
11073 | ||
11074 | newop = expand_binop (SImode, and_optab, | |
11075 | oldop, GEN_INT (imask), NULL_RTX, | |
11076 | 1, OPTAB_LIB_WIDEN); | |
11077 | emit_insn (gen_ashlsi3 (newop, newop, shift)); | |
11078 | ||
11079 | mask = gen_reg_rtx (SImode); | |
11080 | emit_move_insn (mask, GEN_INT (imask)); | |
11081 | emit_insn (gen_ashlsi3 (mask, mask, shift)); | |
11082 | ||
11083 | newop = gen_rtx_AND (SImode, gen_rtx_PLUS (SImode, m, newop), | |
11084 | mask); | |
11085 | newop = gen_rtx_IOR (SImode, newop, | |
11086 | gen_rtx_AND (SImode, | |
11087 | gen_rtx_NOT (SImode, mask), | |
11088 | m)); | |
11089 | break; | |
11090 | } | |
11091 | ||
11092 | default: | |
11093 | gcc_unreachable (); | |
11094 | } | |
11095 | ||
11096 | op = newop; | |
11097 | used_mode = SImode; | |
11098 | before = gen_reg_rtx (used_mode); | |
11099 | after = gen_reg_rtx (used_mode); | |
11100 | } | |
11101 | else | |
11102 | { | |
11103 | used_mode = mode; | |
11104 | before = before_param; | |
11105 | after = after_param; | |
11106 | ||
11107 | if (before == NULL_RTX) | |
11108 | before = gen_reg_rtx (used_mode); | |
11109 | if (after == NULL_RTX) | |
11110 | after = gen_reg_rtx (used_mode); | |
11111 | } | |
11112 | ||
11113 | if (code == PLUS && used_mode != mode) | |
11114 | the_op = op; /* Computed above. */ | |
11115 | else if (GET_CODE (op) == NOT && GET_CODE (m) != NOT) | |
11116 | the_op = gen_rtx_fmt_ee (code, used_mode, op, m); | |
11117 | else | |
11118 | the_op = gen_rtx_fmt_ee (code, used_mode, m, op); | |
11119 | ||
11120 | set_after = gen_rtx_SET (VOIDmode, after, the_op); | |
11121 | set_before = gen_rtx_SET (VOIDmode, before, used_m); | |
11122 | set_atomic = gen_rtx_SET (VOIDmode, used_m, | |
11123 | gen_rtx_UNSPEC (used_mode, gen_rtvec (1, the_op), | |
11124 | UNSPEC_SYNC_OP)); | |
11125 | cc_scratch = gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (CCmode)); | |
11126 | ||
11127 | if (code == PLUS && used_mode != mode) | |
11128 | vec = gen_rtvec (5, set_after, set_before, set_atomic, cc_scratch, | |
11129 | gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (SImode))); | |
11130 | else | |
11131 | vec = gen_rtvec (4, set_after, set_before, set_atomic, cc_scratch); | |
11132 | emit_insn (gen_rtx_PARALLEL (VOIDmode, vec)); | |
11133 | ||
11134 | /* Shift and mask the return values properly. */ | |
11135 | if (used_mode != mode && before_param) | |
11136 | { | |
11137 | emit_insn (gen_lshrsi3 (before, before, shift)); | |
11138 | convert_move (before_param, before, 1); | |
11139 | } | |
11140 | ||
11141 | if (used_mode != mode && after_param) | |
11142 | { | |
11143 | emit_insn (gen_lshrsi3 (after, after, shift)); | |
11144 | convert_move (after_param, after, 1); | |
11145 | } | |
11146 | ||
11147 | /* The previous sequence will end with a branch that's dependent on | |
11148 | the conditional store, so placing an isync will ensure that no | |
11149 | other instructions (especially, no load or store instructions) | |
11150 | can start before the atomic operation completes. */ | |
11151 | if (sync_p) | |
11152 | emit_insn (gen_isync ()); | |
11153 | } | |
11154 | ||
a9baceb1 GK |
11155 | /* Emit instructions to move SRC to DST. Called by splitters for |
11156 | multi-register moves. It will emit at most one instruction for | |
11157 | each register that is accessed; that is, it won't emit li/lis pairs | |
11158 | (or equivalent for 64-bit code). One of SRC or DST must be a hard | |
11159 | register. */ | |
46c07df8 | 11160 | |
46c07df8 | 11161 | void |
a9baceb1 | 11162 | rs6000_split_multireg_move (rtx dst, rtx src) |
46c07df8 | 11163 | { |
a9baceb1 GK |
11164 | /* The register number of the first register being moved. */ |
11165 | int reg; | |
11166 | /* The mode that is to be moved. */ | |
11167 | enum machine_mode mode; | |
11168 | /* The mode that the move is being done in, and its size. */ | |
11169 | enum machine_mode reg_mode; | |
11170 | int reg_mode_size; | |
11171 | /* The number of registers that will be moved. */ | |
11172 | int nregs; | |
11173 | ||
11174 | reg = REG_P (dst) ? REGNO (dst) : REGNO (src); | |
11175 | mode = GET_MODE (dst); | |
11176 | nregs = HARD_REGNO_NREGS (reg, mode); | |
11177 | if (FP_REGNO_P (reg)) | |
11178 | reg_mode = DFmode; | |
11179 | else if (ALTIVEC_REGNO_P (reg)) | |
11180 | reg_mode = V16QImode; | |
11181 | else | |
11182 | reg_mode = word_mode; | |
11183 | reg_mode_size = GET_MODE_SIZE (reg_mode); | |
f676971a | 11184 | |
37409796 | 11185 | gcc_assert (reg_mode_size * nregs == GET_MODE_SIZE (mode)); |
f676971a | 11186 | |
a9baceb1 GK |
11187 | if (REG_P (src) && REG_P (dst) && (REGNO (src) < REGNO (dst))) |
11188 | { | |
11189 | /* Move register range backwards, if we might have destructive | |
11190 | overlap. */ | |
11191 | int i; | |
11192 | for (i = nregs - 1; i >= 0; i--) | |
f676971a | 11193 | emit_insn (gen_rtx_SET (VOIDmode, |
a9baceb1 GK |
11194 | simplify_gen_subreg (reg_mode, dst, mode, |
11195 | i * reg_mode_size), | |
11196 | simplify_gen_subreg (reg_mode, src, mode, | |
11197 | i * reg_mode_size))); | |
11198 | } | |
46c07df8 HP |
11199 | else |
11200 | { | |
a9baceb1 GK |
11201 | int i; |
11202 | int j = -1; | |
11203 | bool used_update = false; | |
46c07df8 | 11204 | |
c1e55850 | 11205 | if (MEM_P (src) && INT_REGNO_P (reg)) |
c4ad648e AM |
11206 | { |
11207 | rtx breg; | |
3a1f863f | 11208 | |
a9baceb1 GK |
11209 | if (GET_CODE (XEXP (src, 0)) == PRE_INC |
11210 | || GET_CODE (XEXP (src, 0)) == PRE_DEC) | |
3a1f863f DE |
11211 | { |
11212 | rtx delta_rtx; | |
a9baceb1 | 11213 | breg = XEXP (XEXP (src, 0), 0); |
c4ad648e AM |
11214 | delta_rtx = (GET_CODE (XEXP (src, 0)) == PRE_INC |
11215 | ? GEN_INT (GET_MODE_SIZE (GET_MODE (src))) | |
11216 | : GEN_INT (-GET_MODE_SIZE (GET_MODE (src)))); | |
a9baceb1 GK |
11217 | emit_insn (TARGET_32BIT |
11218 | ? gen_addsi3 (breg, breg, delta_rtx) | |
11219 | : gen_adddi3 (breg, breg, delta_rtx)); | |
3a1f863f DE |
11220 | src = gen_rtx_MEM (mode, breg); |
11221 | } | |
c1e55850 GK |
11222 | else if (! offsettable_memref_p (src)) |
11223 | { | |
11224 | rtx newsrc, basereg; | |
11225 | basereg = gen_rtx_REG (Pmode, reg); | |
11226 | emit_insn (gen_rtx_SET (VOIDmode, basereg, XEXP (src, 0))); | |
11227 | newsrc = gen_rtx_MEM (GET_MODE (src), basereg); | |
11228 | MEM_COPY_ATTRIBUTES (newsrc, src); | |
11229 | src = newsrc; | |
11230 | } | |
3a1f863f | 11231 | |
0423421f AM |
11232 | breg = XEXP (src, 0); |
11233 | if (GET_CODE (breg) == PLUS || GET_CODE (breg) == LO_SUM) | |
11234 | breg = XEXP (breg, 0); | |
11235 | ||
11236 | /* If the base register we are using to address memory is | |
11237 | also a destination reg, then change that register last. */ | |
11238 | if (REG_P (breg) | |
11239 | && REGNO (breg) >= REGNO (dst) | |
3a1f863f DE |
11240 | && REGNO (breg) < REGNO (dst) + nregs) |
11241 | j = REGNO (breg) - REGNO (dst); | |
c4ad648e | 11242 | } |
46c07df8 | 11243 | |
a9baceb1 | 11244 | if (GET_CODE (dst) == MEM && INT_REGNO_P (reg)) |
3a1f863f DE |
11245 | { |
11246 | rtx breg; | |
11247 | ||
a9baceb1 GK |
11248 | if (GET_CODE (XEXP (dst, 0)) == PRE_INC |
11249 | || GET_CODE (XEXP (dst, 0)) == PRE_DEC) | |
3a1f863f DE |
11250 | { |
11251 | rtx delta_rtx; | |
a9baceb1 | 11252 | breg = XEXP (XEXP (dst, 0), 0); |
c4ad648e AM |
11253 | delta_rtx = (GET_CODE (XEXP (dst, 0)) == PRE_INC |
11254 | ? GEN_INT (GET_MODE_SIZE (GET_MODE (dst))) | |
11255 | : GEN_INT (-GET_MODE_SIZE (GET_MODE (dst)))); | |
3a1f863f DE |
11256 | |
11257 | /* We have to update the breg before doing the store. | |
11258 | Use store with update, if available. */ | |
11259 | ||
11260 | if (TARGET_UPDATE) | |
11261 | { | |
a9baceb1 | 11262 | rtx nsrc = simplify_gen_subreg (reg_mode, src, mode, 0); |
c4ad648e AM |
11263 | emit_insn (TARGET_32BIT |
11264 | ? (TARGET_POWERPC64 | |
11265 | ? gen_movdi_si_update (breg, breg, delta_rtx, nsrc) | |
11266 | : gen_movsi_update (breg, breg, delta_rtx, nsrc)) | |
11267 | : gen_movdi_di_update (breg, breg, delta_rtx, nsrc)); | |
a9baceb1 | 11268 | used_update = true; |
3a1f863f DE |
11269 | } |
11270 | else | |
a9baceb1 GK |
11271 | emit_insn (TARGET_32BIT |
11272 | ? gen_addsi3 (breg, breg, delta_rtx) | |
11273 | : gen_adddi3 (breg, breg, delta_rtx)); | |
3a1f863f DE |
11274 | dst = gen_rtx_MEM (mode, breg); |
11275 | } | |
37409796 NS |
11276 | else |
11277 | gcc_assert (offsettable_memref_p (dst)); | |
3a1f863f DE |
11278 | } |
11279 | ||
46c07df8 | 11280 | for (i = 0; i < nregs; i++) |
f676971a | 11281 | { |
3a1f863f DE |
11282 | /* Calculate index to next subword. */ |
11283 | ++j; | |
f676971a | 11284 | if (j == nregs) |
3a1f863f | 11285 | j = 0; |
46c07df8 | 11286 | |
112cdef5 | 11287 | /* If compiler already emitted move of first word by |
a9baceb1 | 11288 | store with update, no need to do anything. */ |
3a1f863f | 11289 | if (j == 0 && used_update) |
a9baceb1 | 11290 | continue; |
f676971a | 11291 | |
a9baceb1 GK |
11292 | emit_insn (gen_rtx_SET (VOIDmode, |
11293 | simplify_gen_subreg (reg_mode, dst, mode, | |
11294 | j * reg_mode_size), | |
11295 | simplify_gen_subreg (reg_mode, src, mode, | |
11296 | j * reg_mode_size))); | |
3a1f863f | 11297 | } |
46c07df8 HP |
11298 | } |
11299 | } | |
11300 | ||
12a4e8c5 | 11301 | \f |
a4f6c312 SS |
11302 | /* This page contains routines that are used to determine what the |
11303 | function prologue and epilogue code will do and write them out. */ | |
9878760c | 11304 | |
a4f6c312 SS |
11305 | /* Return the first fixed-point register that is required to be |
11306 | saved. 32 if none. */ | |
9878760c RK |
11307 | |
11308 | int | |
863d938c | 11309 | first_reg_to_save (void) |
9878760c RK |
11310 | { |
11311 | int first_reg; | |
11312 | ||
11313 | /* Find lowest numbered live register. */ | |
11314 | for (first_reg = 13; first_reg <= 31; first_reg++) | |
f676971a | 11315 | if (regs_ever_live[first_reg] |
a38d360d | 11316 | && (! call_used_regs[first_reg] |
1db02437 | 11317 | || (first_reg == RS6000_PIC_OFFSET_TABLE_REGNUM |
14f00213 | 11318 | && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0) |
b4db40bf JJ |
11319 | || (DEFAULT_ABI == ABI_DARWIN && flag_pic) |
11320 | || (TARGET_TOC && TARGET_MINIMAL_TOC))))) | |
9878760c RK |
11321 | break; |
11322 | ||
ee890fe2 | 11323 | #if TARGET_MACHO |
93638d7a AM |
11324 | if (flag_pic |
11325 | && current_function_uses_pic_offset_table | |
11326 | && first_reg > RS6000_PIC_OFFSET_TABLE_REGNUM) | |
1db02437 | 11327 | return RS6000_PIC_OFFSET_TABLE_REGNUM; |
ee890fe2 SS |
11328 | #endif |
11329 | ||
9878760c RK |
11330 | return first_reg; |
11331 | } | |
11332 | ||
11333 | /* Similar, for FP regs. */ | |
11334 | ||
11335 | int | |
863d938c | 11336 | first_fp_reg_to_save (void) |
9878760c RK |
11337 | { |
11338 | int first_reg; | |
11339 | ||
11340 | /* Find lowest numbered live register. */ | |
11341 | for (first_reg = 14 + 32; first_reg <= 63; first_reg++) | |
11342 | if (regs_ever_live[first_reg]) | |
11343 | break; | |
11344 | ||
11345 | return first_reg; | |
11346 | } | |
00b960c7 AH |
11347 | |
11348 | /* Similar, for AltiVec regs. */ | |
11349 | ||
11350 | static int | |
863d938c | 11351 | first_altivec_reg_to_save (void) |
00b960c7 AH |
11352 | { |
11353 | int i; | |
11354 | ||
11355 | /* Stack frame remains as is unless we are in AltiVec ABI. */ | |
11356 | if (! TARGET_ALTIVEC_ABI) | |
11357 | return LAST_ALTIVEC_REGNO + 1; | |
11358 | ||
11359 | /* Find lowest numbered live register. */ | |
11360 | for (i = FIRST_ALTIVEC_REGNO + 20; i <= LAST_ALTIVEC_REGNO; ++i) | |
11361 | if (regs_ever_live[i]) | |
11362 | break; | |
11363 | ||
11364 | return i; | |
11365 | } | |
11366 | ||
11367 | /* Return a 32-bit mask of the AltiVec registers we need to set in | |
11368 | VRSAVE. Bit n of the return value is 1 if Vn is live. The MSB in | |
11369 | the 32-bit word is 0. */ | |
11370 | ||
11371 | static unsigned int | |
863d938c | 11372 | compute_vrsave_mask (void) |
00b960c7 AH |
11373 | { |
11374 | unsigned int i, mask = 0; | |
11375 | ||
11376 | /* First, find out if we use _any_ altivec registers. */ | |
11377 | for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i) | |
11378 | if (regs_ever_live[i]) | |
11379 | mask |= ALTIVEC_REG_BIT (i); | |
11380 | ||
11381 | if (mask == 0) | |
11382 | return mask; | |
11383 | ||
00b960c7 AH |
11384 | /* Next, remove the argument registers from the set. These must |
11385 | be in the VRSAVE mask set by the caller, so we don't need to add | |
11386 | them in again. More importantly, the mask we compute here is | |
11387 | used to generate CLOBBERs in the set_vrsave insn, and we do not | |
11388 | wish the argument registers to die. */ | |
a6cf80f2 | 11389 | for (i = cfun->args_info.vregno - 1; i >= ALTIVEC_ARG_MIN_REG; --i) |
00b960c7 AH |
11390 | mask &= ~ALTIVEC_REG_BIT (i); |
11391 | ||
11392 | /* Similarly, remove the return value from the set. */ | |
11393 | { | |
11394 | bool yes = false; | |
11395 | diddle_return_value (is_altivec_return_reg, &yes); | |
11396 | if (yes) | |
11397 | mask &= ~ALTIVEC_REG_BIT (ALTIVEC_ARG_RETURN); | |
11398 | } | |
11399 | ||
11400 | return mask; | |
11401 | } | |
11402 | ||
d62294f5 | 11403 | /* For a very restricted set of circumstances, we can cut down the |
f57fe068 AM |
11404 | size of prologues/epilogues by calling our own save/restore-the-world |
11405 | routines. */ | |
d62294f5 FJ |
11406 | |
11407 | static void | |
f57fe068 AM |
11408 | compute_save_world_info (rs6000_stack_t *info_ptr) |
11409 | { | |
11410 | info_ptr->world_save_p = 1; | |
11411 | info_ptr->world_save_p | |
11412 | = (WORLD_SAVE_P (info_ptr) | |
11413 | && DEFAULT_ABI == ABI_DARWIN | |
11414 | && ! (current_function_calls_setjmp && flag_exceptions) | |
11415 | && info_ptr->first_fp_reg_save == FIRST_SAVED_FP_REGNO | |
11416 | && info_ptr->first_gp_reg_save == FIRST_SAVED_GP_REGNO | |
11417 | && info_ptr->first_altivec_reg_save == FIRST_SAVED_ALTIVEC_REGNO | |
11418 | && info_ptr->cr_save_p); | |
f676971a | 11419 | |
d62294f5 FJ |
11420 | /* This will not work in conjunction with sibcalls. Make sure there |
11421 | are none. (This check is expensive, but seldom executed.) */ | |
f57fe068 | 11422 | if (WORLD_SAVE_P (info_ptr)) |
f676971a | 11423 | { |
d62294f5 FJ |
11424 | rtx insn; |
11425 | for ( insn = get_last_insn_anywhere (); insn; insn = PREV_INSN (insn)) | |
c4ad648e AM |
11426 | if ( GET_CODE (insn) == CALL_INSN |
11427 | && SIBLING_CALL_P (insn)) | |
11428 | { | |
11429 | info_ptr->world_save_p = 0; | |
11430 | break; | |
11431 | } | |
d62294f5 | 11432 | } |
f676971a | 11433 | |
f57fe068 | 11434 | if (WORLD_SAVE_P (info_ptr)) |
d62294f5 FJ |
11435 | { |
11436 | /* Even if we're not touching VRsave, make sure there's room on the | |
11437 | stack for it, if it looks like we're calling SAVE_WORLD, which | |
c4ad648e | 11438 | will attempt to save it. */ |
d62294f5 FJ |
11439 | info_ptr->vrsave_size = 4; |
11440 | ||
11441 | /* "Save" the VRsave register too if we're saving the world. */ | |
11442 | if (info_ptr->vrsave_mask == 0) | |
c4ad648e | 11443 | info_ptr->vrsave_mask = compute_vrsave_mask (); |
d62294f5 FJ |
11444 | |
11445 | /* Because the Darwin register save/restore routines only handle | |
c4ad648e AM |
11446 | F14 .. F31 and V20 .. V31 as per the ABI, perform a consistency |
11447 | check and abort if there's something worng. */ | |
37409796 NS |
11448 | gcc_assert (info_ptr->first_fp_reg_save >= FIRST_SAVED_FP_REGNO |
11449 | && (info_ptr->first_altivec_reg_save | |
11450 | >= FIRST_SAVED_ALTIVEC_REGNO)); | |
d62294f5 | 11451 | } |
f676971a | 11452 | return; |
d62294f5 FJ |
11453 | } |
11454 | ||
11455 | ||
00b960c7 | 11456 | static void |
a2369ed3 | 11457 | is_altivec_return_reg (rtx reg, void *xyes) |
00b960c7 AH |
11458 | { |
11459 | bool *yes = (bool *) xyes; | |
11460 | if (REGNO (reg) == ALTIVEC_ARG_RETURN) | |
11461 | *yes = true; | |
11462 | } | |
11463 | ||
4697a36c MM |
11464 | \f |
11465 | /* Calculate the stack information for the current function. This is | |
11466 | complicated by having two separate calling sequences, the AIX calling | |
11467 | sequence and the V.4 calling sequence. | |
11468 | ||
592696dd | 11469 | AIX (and Darwin/Mac OS X) stack frames look like: |
a260abc9 | 11470 | 32-bit 64-bit |
4697a36c | 11471 | SP----> +---------------------------------------+ |
a260abc9 | 11472 | | back chain to caller | 0 0 |
4697a36c | 11473 | +---------------------------------------+ |
a260abc9 | 11474 | | saved CR | 4 8 (8-11) |
4697a36c | 11475 | +---------------------------------------+ |
a260abc9 | 11476 | | saved LR | 8 16 |
4697a36c | 11477 | +---------------------------------------+ |
a260abc9 | 11478 | | reserved for compilers | 12 24 |
4697a36c | 11479 | +---------------------------------------+ |
a260abc9 | 11480 | | reserved for binders | 16 32 |
4697a36c | 11481 | +---------------------------------------+ |
a260abc9 | 11482 | | saved TOC pointer | 20 40 |
4697a36c | 11483 | +---------------------------------------+ |
a260abc9 | 11484 | | Parameter save area (P) | 24 48 |
4697a36c | 11485 | +---------------------------------------+ |
a260abc9 | 11486 | | Alloca space (A) | 24+P etc. |
802a0058 | 11487 | +---------------------------------------+ |
a7df97e6 | 11488 | | Local variable space (L) | 24+P+A |
4697a36c | 11489 | +---------------------------------------+ |
a7df97e6 | 11490 | | Float/int conversion temporary (X) | 24+P+A+L |
4697a36c | 11491 | +---------------------------------------+ |
00b960c7 AH |
11492 | | Save area for AltiVec registers (W) | 24+P+A+L+X |
11493 | +---------------------------------------+ | |
11494 | | AltiVec alignment padding (Y) | 24+P+A+L+X+W | |
11495 | +---------------------------------------+ | |
11496 | | Save area for VRSAVE register (Z) | 24+P+A+L+X+W+Y | |
4697a36c | 11497 | +---------------------------------------+ |
00b960c7 AH |
11498 | | Save area for GP registers (G) | 24+P+A+X+L+X+W+Y+Z |
11499 | +---------------------------------------+ | |
11500 | | Save area for FP registers (F) | 24+P+A+X+L+X+W+Y+Z+G | |
4697a36c MM |
11501 | +---------------------------------------+ |
11502 | old SP->| back chain to caller's caller | | |
11503 | +---------------------------------------+ | |
11504 | ||
5376a30c KR |
11505 | The required alignment for AIX configurations is two words (i.e., 8 |
11506 | or 16 bytes). | |
11507 | ||
11508 | ||
4697a36c MM |
11509 | V.4 stack frames look like: |
11510 | ||
11511 | SP----> +---------------------------------------+ | |
11512 | | back chain to caller | 0 | |
11513 | +---------------------------------------+ | |
5eb387b8 | 11514 | | caller's saved LR | 4 |
4697a36c MM |
11515 | +---------------------------------------+ |
11516 | | Parameter save area (P) | 8 | |
11517 | +---------------------------------------+ | |
a7df97e6 | 11518 | | Alloca space (A) | 8+P |
f676971a | 11519 | +---------------------------------------+ |
a7df97e6 | 11520 | | Varargs save area (V) | 8+P+A |
f676971a | 11521 | +---------------------------------------+ |
a7df97e6 | 11522 | | Local variable space (L) | 8+P+A+V |
f676971a | 11523 | +---------------------------------------+ |
a7df97e6 | 11524 | | Float/int conversion temporary (X) | 8+P+A+V+L |
4697a36c | 11525 | +---------------------------------------+ |
00b960c7 AH |
11526 | | Save area for AltiVec registers (W) | 8+P+A+V+L+X |
11527 | +---------------------------------------+ | |
11528 | | AltiVec alignment padding (Y) | 8+P+A+V+L+X+W | |
11529 | +---------------------------------------+ | |
11530 | | Save area for VRSAVE register (Z) | 8+P+A+V+L+X+W+Y | |
11531 | +---------------------------------------+ | |
c4ad648e AM |
11532 | | SPE: area for 64-bit GP registers | |
11533 | +---------------------------------------+ | |
11534 | | SPE alignment padding | | |
11535 | +---------------------------------------+ | |
00b960c7 | 11536 | | saved CR (C) | 8+P+A+V+L+X+W+Y+Z |
f676971a | 11537 | +---------------------------------------+ |
00b960c7 | 11538 | | Save area for GP registers (G) | 8+P+A+V+L+X+W+Y+Z+C |
f676971a | 11539 | +---------------------------------------+ |
00b960c7 | 11540 | | Save area for FP registers (F) | 8+P+A+V+L+X+W+Y+Z+C+G |
4697a36c MM |
11541 | +---------------------------------------+ |
11542 | old SP->| back chain to caller's caller | | |
11543 | +---------------------------------------+ | |
b6c9286a | 11544 | |
5376a30c KR |
11545 | The required alignment for V.4 is 16 bytes, or 8 bytes if -meabi is |
11546 | given. (But note below and in sysv4.h that we require only 8 and | |
11547 | may round up the size of our stack frame anyways. The historical | |
11548 | reason is early versions of powerpc-linux which didn't properly | |
11549 | align the stack at program startup. A happy side-effect is that | |
11550 | -mno-eabi libraries can be used with -meabi programs.) | |
11551 | ||
50d440bc | 11552 | The EABI configuration defaults to the V.4 layout. However, |
5376a30c KR |
11553 | the stack alignment requirements may differ. If -mno-eabi is not |
11554 | given, the required stack alignment is 8 bytes; if -mno-eabi is | |
11555 | given, the required alignment is 16 bytes. (But see V.4 comment | |
11556 | above.) */ | |
4697a36c | 11557 | |
61b2fbe7 MM |
11558 | #ifndef ABI_STACK_BOUNDARY |
11559 | #define ABI_STACK_BOUNDARY STACK_BOUNDARY | |
11560 | #endif | |
11561 | ||
d1d0c603 | 11562 | static rs6000_stack_t * |
863d938c | 11563 | rs6000_stack_info (void) |
4697a36c MM |
11564 | { |
11565 | static rs6000_stack_t info, zero_info; | |
11566 | rs6000_stack_t *info_ptr = &info; | |
327e5343 | 11567 | int reg_size = TARGET_32BIT ? 4 : 8; |
83720594 | 11568 | int ehrd_size; |
64045029 | 11569 | int save_align; |
44688022 | 11570 | HOST_WIDE_INT non_fixed_size; |
4697a36c | 11571 | |
a4f6c312 | 11572 | /* Zero all fields portably. */ |
4697a36c MM |
11573 | info = zero_info; |
11574 | ||
c19de7aa AH |
11575 | if (TARGET_SPE) |
11576 | { | |
11577 | /* Cache value so we don't rescan instruction chain over and over. */ | |
9b7b447f | 11578 | if (cfun->machine->insn_chain_scanned_p == 0) |
b5a5beb9 AH |
11579 | cfun->machine->insn_chain_scanned_p |
11580 | = spe_func_has_64bit_regs_p () + 1; | |
11581 | info_ptr->spe_64bit_regs_used = cfun->machine->insn_chain_scanned_p - 1; | |
c19de7aa AH |
11582 | } |
11583 | ||
a4f6c312 | 11584 | /* Select which calling sequence. */ |
178274da | 11585 | info_ptr->abi = DEFAULT_ABI; |
9878760c | 11586 | |
a4f6c312 | 11587 | /* Calculate which registers need to be saved & save area size. */ |
4697a36c | 11588 | info_ptr->first_gp_reg_save = first_reg_to_save (); |
f676971a | 11589 | /* Assume that we will have to save RS6000_PIC_OFFSET_TABLE_REGNUM, |
906fb125 | 11590 | even if it currently looks like we won't. */ |
2bfcf297 | 11591 | if (((TARGET_TOC && TARGET_MINIMAL_TOC) |
178274da AM |
11592 | || (flag_pic == 1 && DEFAULT_ABI == ABI_V4) |
11593 | || (flag_pic && DEFAULT_ABI == ABI_DARWIN)) | |
1db02437 FS |
11594 | && info_ptr->first_gp_reg_save > RS6000_PIC_OFFSET_TABLE_REGNUM) |
11595 | info_ptr->gp_size = reg_size * (32 - RS6000_PIC_OFFSET_TABLE_REGNUM); | |
906fb125 GK |
11596 | else |
11597 | info_ptr->gp_size = reg_size * (32 - info_ptr->first_gp_reg_save); | |
4697a36c | 11598 | |
a3170dc6 AH |
11599 | /* For the SPE, we have an additional upper 32-bits on each GPR. |
11600 | Ideally we should save the entire 64-bits only when the upper | |
11601 | half is used in SIMD instructions. Since we only record | |
11602 | registers live (not the size they are used in), this proves | |
11603 | difficult because we'd have to traverse the instruction chain at | |
11604 | the right time, taking reload into account. This is a real pain, | |
c19de7aa AH |
11605 | so we opt to save the GPRs in 64-bits always if but one register |
11606 | gets used in 64-bits. Otherwise, all the registers in the frame | |
11607 | get saved in 32-bits. | |
a3170dc6 | 11608 | |
c19de7aa | 11609 | So... since when we save all GPRs (except the SP) in 64-bits, the |
a3170dc6 | 11610 | traditional GP save area will be empty. */ |
c19de7aa | 11611 | if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0) |
a3170dc6 AH |
11612 | info_ptr->gp_size = 0; |
11613 | ||
4697a36c MM |
11614 | info_ptr->first_fp_reg_save = first_fp_reg_to_save (); |
11615 | info_ptr->fp_size = 8 * (64 - info_ptr->first_fp_reg_save); | |
11616 | ||
00b960c7 AH |
11617 | info_ptr->first_altivec_reg_save = first_altivec_reg_to_save (); |
11618 | info_ptr->altivec_size = 16 * (LAST_ALTIVEC_REGNO + 1 | |
11619 | - info_ptr->first_altivec_reg_save); | |
11620 | ||
592696dd | 11621 | /* Does this function call anything? */ |
71f123ca FS |
11622 | info_ptr->calls_p = (! current_function_is_leaf |
11623 | || cfun->machine->ra_needs_full_frame); | |
b6c9286a | 11624 | |
a4f6c312 | 11625 | /* Determine if we need to save the link register. */ |
71f123ca | 11626 | if (rs6000_ra_ever_killed () |
ffcfcb5f AM |
11627 | || (DEFAULT_ABI == ABI_AIX |
11628 | && current_function_profile | |
11629 | && !TARGET_PROFILE_KERNEL) | |
4697a36c MM |
11630 | #ifdef TARGET_RELOCATABLE |
11631 | || (TARGET_RELOCATABLE && (get_pool_size () != 0)) | |
11632 | #endif | |
11633 | || (info_ptr->first_fp_reg_save != 64 | |
11634 | && !FP_SAVE_INLINE (info_ptr->first_fp_reg_save)) | |
00b960c7 | 11635 | || info_ptr->first_altivec_reg_save <= LAST_ALTIVEC_REGNO |
178274da | 11636 | || (DEFAULT_ABI == ABI_V4 && current_function_calls_alloca) |
a4f6c312 SS |
11637 | || (DEFAULT_ABI == ABI_DARWIN |
11638 | && flag_pic | |
11639 | && current_function_uses_pic_offset_table) | |
4697a36c MM |
11640 | || info_ptr->calls_p) |
11641 | { | |
11642 | info_ptr->lr_save_p = 1; | |
9ebbca7d | 11643 | regs_ever_live[LINK_REGISTER_REGNUM] = 1; |
4697a36c MM |
11644 | } |
11645 | ||
9ebbca7d | 11646 | /* Determine if we need to save the condition code registers. */ |
f676971a | 11647 | if (regs_ever_live[CR2_REGNO] |
9ebbca7d GK |
11648 | || regs_ever_live[CR3_REGNO] |
11649 | || regs_ever_live[CR4_REGNO]) | |
4697a36c MM |
11650 | { |
11651 | info_ptr->cr_save_p = 1; | |
178274da | 11652 | if (DEFAULT_ABI == ABI_V4) |
4697a36c MM |
11653 | info_ptr->cr_size = reg_size; |
11654 | } | |
11655 | ||
83720594 RH |
11656 | /* If the current function calls __builtin_eh_return, then we need |
11657 | to allocate stack space for registers that will hold data for | |
11658 | the exception handler. */ | |
11659 | if (current_function_calls_eh_return) | |
11660 | { | |
11661 | unsigned int i; | |
11662 | for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; ++i) | |
11663 | continue; | |
a3170dc6 AH |
11664 | |
11665 | /* SPE saves EH registers in 64-bits. */ | |
c19de7aa AH |
11666 | ehrd_size = i * (TARGET_SPE_ABI |
11667 | && info_ptr->spe_64bit_regs_used != 0 | |
11668 | ? UNITS_PER_SPE_WORD : UNITS_PER_WORD); | |
83720594 RH |
11669 | } |
11670 | else | |
11671 | ehrd_size = 0; | |
11672 | ||
592696dd | 11673 | /* Determine various sizes. */ |
4697a36c MM |
11674 | info_ptr->reg_size = reg_size; |
11675 | info_ptr->fixed_size = RS6000_SAVE_AREA; | |
11676 | info_ptr->varargs_size = RS6000_VARARGS_AREA; | |
189e03e3 | 11677 | info_ptr->vars_size = RS6000_ALIGN (get_frame_size (), 8); |
a4f6c312 | 11678 | info_ptr->parm_size = RS6000_ALIGN (current_function_outgoing_args_size, |
03e007d7 | 11679 | TARGET_ALTIVEC ? 16 : 8); |
00b960c7 | 11680 | |
c19de7aa | 11681 | if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0) |
a3170dc6 AH |
11682 | info_ptr->spe_gp_size = 8 * (32 - info_ptr->first_gp_reg_save); |
11683 | else | |
11684 | info_ptr->spe_gp_size = 0; | |
11685 | ||
4d774ff8 HP |
11686 | if (TARGET_ALTIVEC_ABI) |
11687 | info_ptr->vrsave_mask = compute_vrsave_mask (); | |
00b960c7 | 11688 | else |
4d774ff8 HP |
11689 | info_ptr->vrsave_mask = 0; |
11690 | ||
11691 | if (TARGET_ALTIVEC_VRSAVE && info_ptr->vrsave_mask) | |
11692 | info_ptr->vrsave_size = 4; | |
11693 | else | |
11694 | info_ptr->vrsave_size = 0; | |
b6c9286a | 11695 | |
d62294f5 FJ |
11696 | compute_save_world_info (info_ptr); |
11697 | ||
592696dd | 11698 | /* Calculate the offsets. */ |
178274da | 11699 | switch (DEFAULT_ABI) |
4697a36c | 11700 | { |
b6c9286a | 11701 | case ABI_NONE: |
24d304eb | 11702 | default: |
37409796 | 11703 | gcc_unreachable (); |
b6c9286a MM |
11704 | |
11705 | case ABI_AIX: | |
ee890fe2 | 11706 | case ABI_DARWIN: |
b6c9286a MM |
11707 | info_ptr->fp_save_offset = - info_ptr->fp_size; |
11708 | info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size; | |
00b960c7 AH |
11709 | |
11710 | if (TARGET_ALTIVEC_ABI) | |
11711 | { | |
11712 | info_ptr->vrsave_save_offset | |
11713 | = info_ptr->gp_save_offset - info_ptr->vrsave_size; | |
11714 | ||
11715 | /* Align stack so vector save area is on a quadword boundary. */ | |
11716 | if (info_ptr->altivec_size != 0) | |
11717 | info_ptr->altivec_padding_size | |
11718 | = 16 - (-info_ptr->vrsave_save_offset % 16); | |
11719 | else | |
11720 | info_ptr->altivec_padding_size = 0; | |
11721 | ||
11722 | info_ptr->altivec_save_offset | |
11723 | = info_ptr->vrsave_save_offset | |
11724 | - info_ptr->altivec_padding_size | |
11725 | - info_ptr->altivec_size; | |
11726 | ||
11727 | /* Adjust for AltiVec case. */ | |
11728 | info_ptr->ehrd_offset = info_ptr->altivec_save_offset - ehrd_size; | |
11729 | } | |
11730 | else | |
11731 | info_ptr->ehrd_offset = info_ptr->gp_save_offset - ehrd_size; | |
a260abc9 DE |
11732 | info_ptr->cr_save_offset = reg_size; /* first word when 64-bit. */ |
11733 | info_ptr->lr_save_offset = 2*reg_size; | |
24d304eb RK |
11734 | break; |
11735 | ||
11736 | case ABI_V4: | |
b6c9286a MM |
11737 | info_ptr->fp_save_offset = - info_ptr->fp_size; |
11738 | info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size; | |
a7df97e6 | 11739 | info_ptr->cr_save_offset = info_ptr->gp_save_offset - info_ptr->cr_size; |
00b960c7 | 11740 | |
c19de7aa | 11741 | if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0) |
c4ad648e AM |
11742 | { |
11743 | /* Align stack so SPE GPR save area is aligned on a | |
11744 | double-word boundary. */ | |
11745 | if (info_ptr->spe_gp_size != 0) | |
11746 | info_ptr->spe_padding_size | |
11747 | = 8 - (-info_ptr->cr_save_offset % 8); | |
11748 | else | |
11749 | info_ptr->spe_padding_size = 0; | |
11750 | ||
11751 | info_ptr->spe_gp_save_offset | |
11752 | = info_ptr->cr_save_offset | |
11753 | - info_ptr->spe_padding_size | |
11754 | - info_ptr->spe_gp_size; | |
11755 | ||
11756 | /* Adjust for SPE case. */ | |
11757 | info_ptr->toc_save_offset | |
11758 | = info_ptr->spe_gp_save_offset - info_ptr->toc_size; | |
11759 | } | |
a3170dc6 | 11760 | else if (TARGET_ALTIVEC_ABI) |
00b960c7 AH |
11761 | { |
11762 | info_ptr->vrsave_save_offset | |
11763 | = info_ptr->cr_save_offset - info_ptr->vrsave_size; | |
11764 | ||
11765 | /* Align stack so vector save area is on a quadword boundary. */ | |
11766 | if (info_ptr->altivec_size != 0) | |
11767 | info_ptr->altivec_padding_size | |
11768 | = 16 - (-info_ptr->vrsave_save_offset % 16); | |
11769 | else | |
11770 | info_ptr->altivec_padding_size = 0; | |
11771 | ||
11772 | info_ptr->altivec_save_offset | |
11773 | = info_ptr->vrsave_save_offset | |
11774 | - info_ptr->altivec_padding_size | |
11775 | - info_ptr->altivec_size; | |
11776 | ||
11777 | /* Adjust for AltiVec case. */ | |
11778 | info_ptr->toc_save_offset | |
11779 | = info_ptr->altivec_save_offset - info_ptr->toc_size; | |
11780 | } | |
11781 | else | |
11782 | info_ptr->toc_save_offset = info_ptr->cr_save_offset - info_ptr->toc_size; | |
83720594 | 11783 | info_ptr->ehrd_offset = info_ptr->toc_save_offset - ehrd_size; |
b6c9286a MM |
11784 | info_ptr->lr_save_offset = reg_size; |
11785 | break; | |
4697a36c MM |
11786 | } |
11787 | ||
64045029 | 11788 | save_align = (TARGET_ALTIVEC_ABI || DEFAULT_ABI == ABI_DARWIN) ? 16 : 8; |
00b960c7 AH |
11789 | info_ptr->save_size = RS6000_ALIGN (info_ptr->fp_size |
11790 | + info_ptr->gp_size | |
11791 | + info_ptr->altivec_size | |
11792 | + info_ptr->altivec_padding_size | |
a3170dc6 AH |
11793 | + info_ptr->spe_gp_size |
11794 | + info_ptr->spe_padding_size | |
00b960c7 AH |
11795 | + ehrd_size |
11796 | + info_ptr->cr_size | |
11797 | + info_ptr->lr_size | |
11798 | + info_ptr->vrsave_size | |
11799 | + info_ptr->toc_size, | |
64045029 | 11800 | save_align); |
00b960c7 | 11801 | |
44688022 | 11802 | non_fixed_size = (info_ptr->vars_size |
ff381587 | 11803 | + info_ptr->parm_size |
ff381587 | 11804 | + info_ptr->save_size |
44688022 | 11805 | + info_ptr->varargs_size); |
ff381587 | 11806 | |
44688022 AM |
11807 | info_ptr->total_size = RS6000_ALIGN (non_fixed_size + info_ptr->fixed_size, |
11808 | ABI_STACK_BOUNDARY / BITS_PER_UNIT); | |
ff381587 MM |
11809 | |
11810 | /* Determine if we need to allocate any stack frame: | |
11811 | ||
a4f6c312 SS |
11812 | For AIX we need to push the stack if a frame pointer is needed |
11813 | (because the stack might be dynamically adjusted), if we are | |
11814 | debugging, if we make calls, or if the sum of fp_save, gp_save, | |
11815 | and local variables are more than the space needed to save all | |
11816 | non-volatile registers: 32-bit: 18*8 + 19*4 = 220 or 64-bit: 18*8 | |
11817 | + 18*8 = 288 (GPR13 reserved). | |
ff381587 | 11818 | |
a4f6c312 SS |
11819 | For V.4 we don't have the stack cushion that AIX uses, but assume |
11820 | that the debugger can handle stackless frames. */ | |
ff381587 MM |
11821 | |
11822 | if (info_ptr->calls_p) | |
11823 | info_ptr->push_p = 1; | |
11824 | ||
178274da | 11825 | else if (DEFAULT_ABI == ABI_V4) |
44688022 | 11826 | info_ptr->push_p = non_fixed_size != 0; |
ff381587 | 11827 | |
178274da AM |
11828 | else if (frame_pointer_needed) |
11829 | info_ptr->push_p = 1; | |
11830 | ||
11831 | else if (TARGET_XCOFF && write_symbols != NO_DEBUG) | |
11832 | info_ptr->push_p = 1; | |
11833 | ||
ff381587 | 11834 | else |
44688022 | 11835 | info_ptr->push_p = non_fixed_size > (TARGET_32BIT ? 220 : 288); |
ff381587 | 11836 | |
a4f6c312 | 11837 | /* Zero offsets if we're not saving those registers. */ |
8dda1a21 | 11838 | if (info_ptr->fp_size == 0) |
4697a36c MM |
11839 | info_ptr->fp_save_offset = 0; |
11840 | ||
8dda1a21 | 11841 | if (info_ptr->gp_size == 0) |
4697a36c MM |
11842 | info_ptr->gp_save_offset = 0; |
11843 | ||
00b960c7 AH |
11844 | if (! TARGET_ALTIVEC_ABI || info_ptr->altivec_size == 0) |
11845 | info_ptr->altivec_save_offset = 0; | |
11846 | ||
11847 | if (! TARGET_ALTIVEC_ABI || info_ptr->vrsave_mask == 0) | |
11848 | info_ptr->vrsave_save_offset = 0; | |
11849 | ||
c19de7aa AH |
11850 | if (! TARGET_SPE_ABI |
11851 | || info_ptr->spe_64bit_regs_used == 0 | |
11852 | || info_ptr->spe_gp_size == 0) | |
a3170dc6 AH |
11853 | info_ptr->spe_gp_save_offset = 0; |
11854 | ||
c81fc13e | 11855 | if (! info_ptr->lr_save_p) |
4697a36c MM |
11856 | info_ptr->lr_save_offset = 0; |
11857 | ||
c81fc13e | 11858 | if (! info_ptr->cr_save_p) |
4697a36c MM |
11859 | info_ptr->cr_save_offset = 0; |
11860 | ||
c81fc13e | 11861 | if (! info_ptr->toc_save_p) |
b6c9286a MM |
11862 | info_ptr->toc_save_offset = 0; |
11863 | ||
4697a36c MM |
11864 | return info_ptr; |
11865 | } | |
11866 | ||
c19de7aa AH |
11867 | /* Return true if the current function uses any GPRs in 64-bit SIMD |
11868 | mode. */ | |
11869 | ||
11870 | static bool | |
863d938c | 11871 | spe_func_has_64bit_regs_p (void) |
c19de7aa AH |
11872 | { |
11873 | rtx insns, insn; | |
11874 | ||
11875 | /* Functions that save and restore all the call-saved registers will | |
11876 | need to save/restore the registers in 64-bits. */ | |
11877 | if (current_function_calls_eh_return | |
11878 | || current_function_calls_setjmp | |
11879 | || current_function_has_nonlocal_goto) | |
11880 | return true; | |
11881 | ||
11882 | insns = get_insns (); | |
11883 | ||
11884 | for (insn = NEXT_INSN (insns); insn != NULL_RTX; insn = NEXT_INSN (insn)) | |
11885 | { | |
11886 | if (INSN_P (insn)) | |
11887 | { | |
11888 | rtx i; | |
11889 | ||
b5a5beb9 AH |
11890 | /* FIXME: This should be implemented with attributes... |
11891 | ||
11892 | (set_attr "spe64" "true")....then, | |
11893 | if (get_spe64(insn)) return true; | |
11894 | ||
11895 | It's the only reliable way to do the stuff below. */ | |
11896 | ||
c19de7aa | 11897 | i = PATTERN (insn); |
f82f556d AH |
11898 | if (GET_CODE (i) == SET) |
11899 | { | |
11900 | enum machine_mode mode = GET_MODE (SET_SRC (i)); | |
11901 | ||
11902 | if (SPE_VECTOR_MODE (mode)) | |
11903 | return true; | |
11904 | if (TARGET_E500_DOUBLE && mode == DFmode) | |
11905 | return true; | |
11906 | } | |
c19de7aa AH |
11907 | } |
11908 | } | |
11909 | ||
11910 | return false; | |
11911 | } | |
11912 | ||
d1d0c603 | 11913 | static void |
a2369ed3 | 11914 | debug_stack_info (rs6000_stack_t *info) |
9878760c | 11915 | { |
d330fd93 | 11916 | const char *abi_string; |
24d304eb | 11917 | |
c81fc13e | 11918 | if (! info) |
4697a36c MM |
11919 | info = rs6000_stack_info (); |
11920 | ||
11921 | fprintf (stderr, "\nStack information for function %s:\n", | |
11922 | ((current_function_decl && DECL_NAME (current_function_decl)) | |
11923 | ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl)) | |
11924 | : "<unknown>")); | |
11925 | ||
24d304eb RK |
11926 | switch (info->abi) |
11927 | { | |
b6c9286a MM |
11928 | default: abi_string = "Unknown"; break; |
11929 | case ABI_NONE: abi_string = "NONE"; break; | |
50d440bc | 11930 | case ABI_AIX: abi_string = "AIX"; break; |
ee890fe2 | 11931 | case ABI_DARWIN: abi_string = "Darwin"; break; |
b6c9286a | 11932 | case ABI_V4: abi_string = "V.4"; break; |
24d304eb RK |
11933 | } |
11934 | ||
11935 | fprintf (stderr, "\tABI = %5s\n", abi_string); | |
11936 | ||
00b960c7 AH |
11937 | if (TARGET_ALTIVEC_ABI) |
11938 | fprintf (stderr, "\tALTIVEC ABI extensions enabled.\n"); | |
11939 | ||
a3170dc6 AH |
11940 | if (TARGET_SPE_ABI) |
11941 | fprintf (stderr, "\tSPE ABI extensions enabled.\n"); | |
11942 | ||
4697a36c MM |
11943 | if (info->first_gp_reg_save != 32) |
11944 | fprintf (stderr, "\tfirst_gp_reg_save = %5d\n", info->first_gp_reg_save); | |
11945 | ||
11946 | if (info->first_fp_reg_save != 64) | |
11947 | fprintf (stderr, "\tfirst_fp_reg_save = %5d\n", info->first_fp_reg_save); | |
9878760c | 11948 | |
00b960c7 AH |
11949 | if (info->first_altivec_reg_save <= LAST_ALTIVEC_REGNO) |
11950 | fprintf (stderr, "\tfirst_altivec_reg_save = %5d\n", | |
11951 | info->first_altivec_reg_save); | |
11952 | ||
4697a36c MM |
11953 | if (info->lr_save_p) |
11954 | fprintf (stderr, "\tlr_save_p = %5d\n", info->lr_save_p); | |
9878760c | 11955 | |
4697a36c MM |
11956 | if (info->cr_save_p) |
11957 | fprintf (stderr, "\tcr_save_p = %5d\n", info->cr_save_p); | |
11958 | ||
b6c9286a MM |
11959 | if (info->toc_save_p) |
11960 | fprintf (stderr, "\ttoc_save_p = %5d\n", info->toc_save_p); | |
11961 | ||
00b960c7 AH |
11962 | if (info->vrsave_mask) |
11963 | fprintf (stderr, "\tvrsave_mask = 0x%x\n", info->vrsave_mask); | |
11964 | ||
4697a36c MM |
11965 | if (info->push_p) |
11966 | fprintf (stderr, "\tpush_p = %5d\n", info->push_p); | |
11967 | ||
11968 | if (info->calls_p) | |
11969 | fprintf (stderr, "\tcalls_p = %5d\n", info->calls_p); | |
11970 | ||
4697a36c MM |
11971 | if (info->gp_save_offset) |
11972 | fprintf (stderr, "\tgp_save_offset = %5d\n", info->gp_save_offset); | |
11973 | ||
11974 | if (info->fp_save_offset) | |
11975 | fprintf (stderr, "\tfp_save_offset = %5d\n", info->fp_save_offset); | |
11976 | ||
00b960c7 AH |
11977 | if (info->altivec_save_offset) |
11978 | fprintf (stderr, "\taltivec_save_offset = %5d\n", | |
11979 | info->altivec_save_offset); | |
11980 | ||
a3170dc6 AH |
11981 | if (info->spe_gp_save_offset) |
11982 | fprintf (stderr, "\tspe_gp_save_offset = %5d\n", | |
11983 | info->spe_gp_save_offset); | |
11984 | ||
00b960c7 AH |
11985 | if (info->vrsave_save_offset) |
11986 | fprintf (stderr, "\tvrsave_save_offset = %5d\n", | |
11987 | info->vrsave_save_offset); | |
11988 | ||
4697a36c MM |
11989 | if (info->lr_save_offset) |
11990 | fprintf (stderr, "\tlr_save_offset = %5d\n", info->lr_save_offset); | |
11991 | ||
11992 | if (info->cr_save_offset) | |
11993 | fprintf (stderr, "\tcr_save_offset = %5d\n", info->cr_save_offset); | |
11994 | ||
b6c9286a MM |
11995 | if (info->toc_save_offset) |
11996 | fprintf (stderr, "\ttoc_save_offset = %5d\n", info->toc_save_offset); | |
11997 | ||
4697a36c MM |
11998 | if (info->varargs_save_offset) |
11999 | fprintf (stderr, "\tvarargs_save_offset = %5d\n", info->varargs_save_offset); | |
12000 | ||
12001 | if (info->total_size) | |
d1d0c603 JJ |
12002 | fprintf (stderr, "\ttotal_size = "HOST_WIDE_INT_PRINT_DEC"\n", |
12003 | info->total_size); | |
4697a36c MM |
12004 | |
12005 | if (info->varargs_size) | |
12006 | fprintf (stderr, "\tvarargs_size = %5d\n", info->varargs_size); | |
12007 | ||
12008 | if (info->vars_size) | |
d1d0c603 JJ |
12009 | fprintf (stderr, "\tvars_size = "HOST_WIDE_INT_PRINT_DEC"\n", |
12010 | info->vars_size); | |
4697a36c MM |
12011 | |
12012 | if (info->parm_size) | |
12013 | fprintf (stderr, "\tparm_size = %5d\n", info->parm_size); | |
12014 | ||
12015 | if (info->fixed_size) | |
12016 | fprintf (stderr, "\tfixed_size = %5d\n", info->fixed_size); | |
12017 | ||
12018 | if (info->gp_size) | |
12019 | fprintf (stderr, "\tgp_size = %5d\n", info->gp_size); | |
12020 | ||
a3170dc6 AH |
12021 | if (info->spe_gp_size) |
12022 | fprintf (stderr, "\tspe_gp_size = %5d\n", info->spe_gp_size); | |
12023 | ||
4697a36c MM |
12024 | if (info->fp_size) |
12025 | fprintf (stderr, "\tfp_size = %5d\n", info->fp_size); | |
12026 | ||
00b960c7 AH |
12027 | if (info->altivec_size) |
12028 | fprintf (stderr, "\taltivec_size = %5d\n", info->altivec_size); | |
12029 | ||
12030 | if (info->vrsave_size) | |
12031 | fprintf (stderr, "\tvrsave_size = %5d\n", info->vrsave_size); | |
12032 | ||
12033 | if (info->altivec_padding_size) | |
12034 | fprintf (stderr, "\taltivec_padding_size= %5d\n", | |
12035 | info->altivec_padding_size); | |
12036 | ||
a3170dc6 AH |
12037 | if (info->spe_padding_size) |
12038 | fprintf (stderr, "\tspe_padding_size = %5d\n", | |
12039 | info->spe_padding_size); | |
12040 | ||
a4f6c312 | 12041 | if (info->lr_size) |
ed947a96 | 12042 | fprintf (stderr, "\tlr_size = %5d\n", info->lr_size); |
b6c9286a | 12043 | |
4697a36c MM |
12044 | if (info->cr_size) |
12045 | fprintf (stderr, "\tcr_size = %5d\n", info->cr_size); | |
12046 | ||
a4f6c312 | 12047 | if (info->toc_size) |
b6c9286a MM |
12048 | fprintf (stderr, "\ttoc_size = %5d\n", info->toc_size); |
12049 | ||
4697a36c MM |
12050 | if (info->save_size) |
12051 | fprintf (stderr, "\tsave_size = %5d\n", info->save_size); | |
12052 | ||
12053 | if (info->reg_size != 4) | |
12054 | fprintf (stderr, "\treg_size = %5d\n", info->reg_size); | |
12055 | ||
12056 | fprintf (stderr, "\n"); | |
9878760c | 12057 | } |
71f123ca FS |
12058 | |
12059 | rtx | |
a2369ed3 | 12060 | rs6000_return_addr (int count, rtx frame) |
71f123ca | 12061 | { |
a4f6c312 SS |
12062 | /* Currently we don't optimize very well between prolog and body |
12063 | code and for PIC code the code can be actually quite bad, so | |
12064 | don't try to be too clever here. */ | |
f1384257 | 12065 | if (count != 0 || (DEFAULT_ABI != ABI_AIX && flag_pic)) |
71f123ca FS |
12066 | { |
12067 | cfun->machine->ra_needs_full_frame = 1; | |
8ac61af7 RK |
12068 | |
12069 | return | |
12070 | gen_rtx_MEM | |
12071 | (Pmode, | |
12072 | memory_address | |
12073 | (Pmode, | |
12074 | plus_constant (copy_to_reg | |
12075 | (gen_rtx_MEM (Pmode, | |
12076 | memory_address (Pmode, frame))), | |
12077 | RETURN_ADDRESS_OFFSET))); | |
71f123ca FS |
12078 | } |
12079 | ||
8c29550d | 12080 | cfun->machine->ra_need_lr = 1; |
9e2f7ec7 | 12081 | return get_hard_reg_initial_val (Pmode, LINK_REGISTER_REGNUM); |
71f123ca FS |
12082 | } |
12083 | ||
5e1bf043 DJ |
12084 | /* Say whether a function is a candidate for sibcall handling or not. |
12085 | We do not allow indirect calls to be optimized into sibling calls. | |
12086 | Also, we can't do it if there are any vector parameters; there's | |
12087 | nowhere to put the VRsave code so it works; note that functions with | |
12088 | vector parameters are required to have a prototype, so the argument | |
12089 | type info must be available here. (The tail recursion case can work | |
12090 | with vector parameters, but there's no way to distinguish here.) */ | |
4977bab6 | 12091 | static bool |
a2369ed3 | 12092 | rs6000_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED) |
5e1bf043 DJ |
12093 | { |
12094 | tree type; | |
4977bab6 | 12095 | if (decl) |
5e1bf043 DJ |
12096 | { |
12097 | if (TARGET_ALTIVEC_VRSAVE) | |
c4ad648e | 12098 | { |
4977bab6 | 12099 | for (type = TYPE_ARG_TYPES (TREE_TYPE (decl)); |
5e1bf043 DJ |
12100 | type; type = TREE_CHAIN (type)) |
12101 | { | |
c15b529f | 12102 | if (TREE_CODE (TREE_VALUE (type)) == VECTOR_TYPE) |
4977bab6 | 12103 | return false; |
5e1bf043 | 12104 | } |
c4ad648e | 12105 | } |
5e1bf043 | 12106 | if (DEFAULT_ABI == ABI_DARWIN |
4977bab6 | 12107 | || (*targetm.binds_local_p) (decl)) |
2bcc50d0 | 12108 | { |
4977bab6 | 12109 | tree attr_list = TYPE_ATTRIBUTES (TREE_TYPE (decl)); |
2bcc50d0 AM |
12110 | |
12111 | if (!lookup_attribute ("longcall", attr_list) | |
12112 | || lookup_attribute ("shortcall", attr_list)) | |
4977bab6 | 12113 | return true; |
2bcc50d0 | 12114 | } |
5e1bf043 | 12115 | } |
4977bab6 | 12116 | return false; |
5e1bf043 DJ |
12117 | } |
12118 | ||
71f123ca | 12119 | static int |
863d938c | 12120 | rs6000_ra_ever_killed (void) |
71f123ca FS |
12121 | { |
12122 | rtx top; | |
5e1bf043 DJ |
12123 | rtx reg; |
12124 | rtx insn; | |
71f123ca | 12125 | |
dd292d0a | 12126 | if (current_function_is_thunk) |
71f123ca | 12127 | return 0; |
eb0424da | 12128 | |
36f7e964 AH |
12129 | /* regs_ever_live has LR marked as used if any sibcalls are present, |
12130 | but this should not force saving and restoring in the | |
12131 | pro/epilogue. Likewise, reg_set_between_p thinks a sibcall | |
a3c9585f | 12132 | clobbers LR, so that is inappropriate. */ |
36f7e964 | 12133 | |
5e1bf043 DJ |
12134 | /* Also, the prologue can generate a store into LR that |
12135 | doesn't really count, like this: | |
36f7e964 | 12136 | |
5e1bf043 DJ |
12137 | move LR->R0 |
12138 | bcl to set PIC register | |
12139 | move LR->R31 | |
12140 | move R0->LR | |
36f7e964 AH |
12141 | |
12142 | When we're called from the epilogue, we need to avoid counting | |
12143 | this as a store. */ | |
f676971a | 12144 | |
71f123ca FS |
12145 | push_topmost_sequence (); |
12146 | top = get_insns (); | |
12147 | pop_topmost_sequence (); | |
5e1bf043 | 12148 | reg = gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM); |
71f123ca | 12149 | |
5e1bf043 DJ |
12150 | for (insn = NEXT_INSN (top); insn != NULL_RTX; insn = NEXT_INSN (insn)) |
12151 | { | |
12152 | if (INSN_P (insn)) | |
12153 | { | |
12154 | if (FIND_REG_INC_NOTE (insn, reg)) | |
12155 | return 1; | |
f676971a | 12156 | else if (GET_CODE (insn) == CALL_INSN |
c15b529f | 12157 | && !SIBLING_CALL_P (insn)) |
5e1bf043 | 12158 | return 1; |
36f7e964 AH |
12159 | else if (set_of (reg, insn) != NULL_RTX |
12160 | && !prologue_epilogue_contains (insn)) | |
5e1bf043 DJ |
12161 | return 1; |
12162 | } | |
12163 | } | |
12164 | return 0; | |
71f123ca | 12165 | } |
4697a36c | 12166 | \f |
8cd8f856 GK |
12167 | /* Add a REG_MAYBE_DEAD note to the insn. */ |
12168 | static void | |
a2369ed3 | 12169 | rs6000_maybe_dead (rtx insn) |
8cd8f856 GK |
12170 | { |
12171 | REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD, | |
12172 | const0_rtx, | |
12173 | REG_NOTES (insn)); | |
12174 | } | |
12175 | ||
9ebbca7d | 12176 | /* Emit instructions needed to load the TOC register. |
c7ca610e | 12177 | This is only needed when TARGET_TOC, TARGET_MINIMAL_TOC, and there is |
9ebbca7d | 12178 | a constant pool; or for SVR4 -fpic. */ |
c7ca610e RK |
12179 | |
12180 | void | |
a2369ed3 | 12181 | rs6000_emit_load_toc_table (int fromprolog) |
c7ca610e | 12182 | { |
027fbf43 | 12183 | rtx dest, insn; |
1db02437 | 12184 | dest = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM); |
c7ca610e | 12185 | |
20b71b17 AM |
12186 | if (TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 1) |
12187 | { | |
12188 | rtx temp = (fromprolog | |
12189 | ? gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM) | |
12190 | : gen_reg_rtx (Pmode)); | |
027fbf43 JJ |
12191 | insn = emit_insn (gen_load_toc_v4_pic_si (temp)); |
12192 | if (fromprolog) | |
12193 | rs6000_maybe_dead (insn); | |
12194 | insn = emit_move_insn (dest, temp); | |
12195 | if (fromprolog) | |
12196 | rs6000_maybe_dead (insn); | |
20b71b17 AM |
12197 | } |
12198 | else if (TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2) | |
12199 | { | |
12200 | char buf[30]; | |
12201 | rtx tempLR = (fromprolog | |
12202 | ? gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM) | |
12203 | : gen_reg_rtx (Pmode)); | |
12204 | rtx temp0 = (fromprolog | |
12205 | ? gen_rtx_REG (Pmode, 0) | |
12206 | : gen_reg_rtx (Pmode)); | |
20b71b17 | 12207 | |
20b71b17 AM |
12208 | if (fromprolog) |
12209 | { | |
ccbca5e4 | 12210 | rtx symF, symL; |
38c1f2d7 | 12211 | |
20b71b17 AM |
12212 | ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno); |
12213 | symF = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); | |
9ebbca7d | 12214 | |
20b71b17 AM |
12215 | ASM_GENERATE_INTERNAL_LABEL (buf, "LCL", rs6000_pic_labelno); |
12216 | symL = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); | |
12217 | ||
12218 | rs6000_maybe_dead (emit_insn (gen_load_toc_v4_PIC_1 (tempLR, | |
12219 | symF))); | |
12220 | rs6000_maybe_dead (emit_move_insn (dest, tempLR)); | |
12221 | rs6000_maybe_dead (emit_insn (gen_load_toc_v4_PIC_2 (temp0, dest, | |
12222 | symL, | |
12223 | symF))); | |
9ebbca7d GK |
12224 | } |
12225 | else | |
20b71b17 AM |
12226 | { |
12227 | rtx tocsym; | |
20b71b17 AM |
12228 | |
12229 | tocsym = gen_rtx_SYMBOL_REF (Pmode, toc_label_name); | |
ccbca5e4 | 12230 | emit_insn (gen_load_toc_v4_PIC_1b (tempLR, tocsym)); |
027fbf43 JJ |
12231 | emit_move_insn (dest, tempLR); |
12232 | emit_move_insn (temp0, gen_rtx_MEM (Pmode, dest)); | |
20b71b17 | 12233 | } |
027fbf43 JJ |
12234 | insn = emit_insn (gen_addsi3 (dest, temp0, dest)); |
12235 | if (fromprolog) | |
12236 | rs6000_maybe_dead (insn); | |
9ebbca7d | 12237 | } |
20b71b17 AM |
12238 | else if (TARGET_ELF && !TARGET_AIX && flag_pic == 0 && TARGET_MINIMAL_TOC) |
12239 | { | |
12240 | /* This is for AIX code running in non-PIC ELF32. */ | |
12241 | char buf[30]; | |
12242 | rtx realsym; | |
12243 | ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1); | |
12244 | realsym = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); | |
12245 | ||
027fbf43 JJ |
12246 | insn = emit_insn (gen_elf_high (dest, realsym)); |
12247 | if (fromprolog) | |
12248 | rs6000_maybe_dead (insn); | |
12249 | insn = emit_insn (gen_elf_low (dest, dest, realsym)); | |
12250 | if (fromprolog) | |
12251 | rs6000_maybe_dead (insn); | |
20b71b17 | 12252 | } |
37409796 | 12253 | else |
9ebbca7d | 12254 | { |
37409796 NS |
12255 | gcc_assert (DEFAULT_ABI == ABI_AIX); |
12256 | ||
9ebbca7d | 12257 | if (TARGET_32BIT) |
027fbf43 | 12258 | insn = emit_insn (gen_load_toc_aix_si (dest)); |
9ebbca7d | 12259 | else |
027fbf43 JJ |
12260 | insn = emit_insn (gen_load_toc_aix_di (dest)); |
12261 | if (fromprolog) | |
12262 | rs6000_maybe_dead (insn); | |
9ebbca7d GK |
12263 | } |
12264 | } | |
12265 | ||
d1d0c603 JJ |
12266 | /* Emit instructions to restore the link register after determining where |
12267 | its value has been stored. */ | |
12268 | ||
12269 | void | |
12270 | rs6000_emit_eh_reg_restore (rtx source, rtx scratch) | |
12271 | { | |
12272 | rs6000_stack_t *info = rs6000_stack_info (); | |
12273 | rtx operands[2]; | |
12274 | ||
12275 | operands[0] = source; | |
12276 | operands[1] = scratch; | |
12277 | ||
12278 | if (info->lr_save_p) | |
12279 | { | |
12280 | rtx frame_rtx = stack_pointer_rtx; | |
12281 | HOST_WIDE_INT sp_offset = 0; | |
12282 | rtx tmp; | |
12283 | ||
12284 | if (frame_pointer_needed | |
12285 | || current_function_calls_alloca | |
12286 | || info->total_size > 32767) | |
12287 | { | |
12288 | emit_move_insn (operands[1], gen_rtx_MEM (Pmode, frame_rtx)); | |
12289 | frame_rtx = operands[1]; | |
12290 | } | |
12291 | else if (info->push_p) | |
12292 | sp_offset = info->total_size; | |
12293 | ||
12294 | tmp = plus_constant (frame_rtx, info->lr_save_offset + sp_offset); | |
12295 | tmp = gen_rtx_MEM (Pmode, tmp); | |
12296 | emit_move_insn (tmp, operands[0]); | |
12297 | } | |
12298 | else | |
12299 | emit_move_insn (gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM), operands[0]); | |
12300 | } | |
12301 | ||
f103e34d GK |
12302 | static GTY(()) int set = -1; |
12303 | ||
f676971a | 12304 | int |
863d938c | 12305 | get_TOC_alias_set (void) |
9ebbca7d | 12306 | { |
f103e34d GK |
12307 | if (set == -1) |
12308 | set = new_alias_set (); | |
12309 | return set; | |
f676971a | 12310 | } |
9ebbca7d | 12311 | |
c1207243 | 12312 | /* This returns nonzero if the current function uses the TOC. This is |
3c9eb5f4 AM |
12313 | determined by the presence of (use (unspec ... UNSPEC_TOC)), which |
12314 | is generated by the ABI_V4 load_toc_* patterns. */ | |
c954844a | 12315 | #if TARGET_ELF |
3c9eb5f4 | 12316 | static int |
f676971a | 12317 | uses_TOC (void) |
9ebbca7d | 12318 | { |
c4501e62 | 12319 | rtx insn; |
38c1f2d7 | 12320 | |
c4501e62 JJ |
12321 | for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) |
12322 | if (INSN_P (insn)) | |
12323 | { | |
12324 | rtx pat = PATTERN (insn); | |
12325 | int i; | |
9ebbca7d | 12326 | |
f676971a | 12327 | if (GET_CODE (pat) == PARALLEL) |
c4501e62 JJ |
12328 | for (i = 0; i < XVECLEN (pat, 0); i++) |
12329 | { | |
12330 | rtx sub = XVECEXP (pat, 0, i); | |
12331 | if (GET_CODE (sub) == USE) | |
12332 | { | |
12333 | sub = XEXP (sub, 0); | |
12334 | if (GET_CODE (sub) == UNSPEC | |
12335 | && XINT (sub, 1) == UNSPEC_TOC) | |
12336 | return 1; | |
12337 | } | |
12338 | } | |
12339 | } | |
12340 | return 0; | |
9ebbca7d | 12341 | } |
c954844a | 12342 | #endif |
38c1f2d7 | 12343 | |
9ebbca7d | 12344 | rtx |
f676971a | 12345 | create_TOC_reference (rtx symbol) |
9ebbca7d | 12346 | { |
f676971a | 12347 | return gen_rtx_PLUS (Pmode, |
a8a05998 | 12348 | gen_rtx_REG (Pmode, TOC_REGISTER), |
f676971a EC |
12349 | gen_rtx_CONST (Pmode, |
12350 | gen_rtx_MINUS (Pmode, symbol, | |
b999aaeb | 12351 | gen_rtx_SYMBOL_REF (Pmode, toc_label_name)))); |
9ebbca7d | 12352 | } |
38c1f2d7 | 12353 | |
fc4767bb JJ |
12354 | /* If _Unwind_* has been called from within the same module, |
12355 | toc register is not guaranteed to be saved to 40(1) on function | |
12356 | entry. Save it there in that case. */ | |
c7ca610e | 12357 | |
9ebbca7d | 12358 | void |
863d938c | 12359 | rs6000_aix_emit_builtin_unwind_init (void) |
9ebbca7d GK |
12360 | { |
12361 | rtx mem; | |
12362 | rtx stack_top = gen_reg_rtx (Pmode); | |
12363 | rtx opcode_addr = gen_reg_rtx (Pmode); | |
fc4767bb JJ |
12364 | rtx opcode = gen_reg_rtx (SImode); |
12365 | rtx tocompare = gen_reg_rtx (SImode); | |
12366 | rtx no_toc_save_needed = gen_label_rtx (); | |
9ebbca7d GK |
12367 | |
12368 | mem = gen_rtx_MEM (Pmode, hard_frame_pointer_rtx); | |
12369 | emit_move_insn (stack_top, mem); | |
12370 | ||
fc4767bb JJ |
12371 | mem = gen_rtx_MEM (Pmode, |
12372 | gen_rtx_PLUS (Pmode, stack_top, | |
9ebbca7d GK |
12373 | GEN_INT (2 * GET_MODE_SIZE (Pmode)))); |
12374 | emit_move_insn (opcode_addr, mem); | |
fc4767bb JJ |
12375 | emit_move_insn (opcode, gen_rtx_MEM (SImode, opcode_addr)); |
12376 | emit_move_insn (tocompare, gen_int_mode (TARGET_32BIT ? 0x80410014 | |
2496c7bd | 12377 | : 0xE8410028, SImode)); |
9ebbca7d | 12378 | |
fc4767bb | 12379 | do_compare_rtx_and_jump (opcode, tocompare, EQ, 1, |
06f4e019 | 12380 | SImode, NULL_RTX, NULL_RTX, |
fc4767bb | 12381 | no_toc_save_needed); |
9ebbca7d | 12382 | |
fc4767bb JJ |
12383 | mem = gen_rtx_MEM (Pmode, |
12384 | gen_rtx_PLUS (Pmode, stack_top, | |
12385 | GEN_INT (5 * GET_MODE_SIZE (Pmode)))); | |
12386 | emit_move_insn (mem, gen_rtx_REG (Pmode, 2)); | |
12387 | emit_label (no_toc_save_needed); | |
9ebbca7d | 12388 | } |
38c1f2d7 | 12389 | \f |
ba4828e0 RK |
12390 | /* This ties together stack memory (MEM with an alias set of |
12391 | rs6000_sr_alias_set) and the change to the stack pointer. */ | |
12392 | ||
9ebbca7d | 12393 | static void |
863d938c | 12394 | rs6000_emit_stack_tie (void) |
9ebbca7d | 12395 | { |
ba4828e0 RK |
12396 | rtx mem = gen_rtx_MEM (BLKmode, gen_rtx_REG (Pmode, STACK_POINTER_REGNUM)); |
12397 | ||
12398 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
9ebbca7d GK |
12399 | emit_insn (gen_stack_tie (mem)); |
12400 | } | |
38c1f2d7 | 12401 | |
9ebbca7d GK |
12402 | /* Emit the correct code for allocating stack space, as insns. |
12403 | If COPY_R12, make sure a copy of the old frame is left in r12. | |
12404 | The generated code may use hard register 0 as a temporary. */ | |
12405 | ||
12406 | static void | |
a2369ed3 | 12407 | rs6000_emit_allocate_stack (HOST_WIDE_INT size, int copy_r12) |
38c1f2d7 | 12408 | { |
9ebbca7d GK |
12409 | rtx insn; |
12410 | rtx stack_reg = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM); | |
12411 | rtx tmp_reg = gen_rtx_REG (Pmode, 0); | |
61168ff1 RS |
12412 | rtx todec = gen_int_mode (-size, Pmode); |
12413 | ||
12414 | if (INTVAL (todec) != -size) | |
12415 | { | |
d4ee4d25 | 12416 | warning (0, "stack frame too large"); |
61168ff1 RS |
12417 | emit_insn (gen_trap ()); |
12418 | return; | |
12419 | } | |
a157febd GK |
12420 | |
12421 | if (current_function_limit_stack) | |
12422 | { | |
12423 | if (REG_P (stack_limit_rtx) | |
f676971a | 12424 | && REGNO (stack_limit_rtx) > 1 |
a157febd GK |
12425 | && REGNO (stack_limit_rtx) <= 31) |
12426 | { | |
5b71a4e7 | 12427 | emit_insn (TARGET_32BIT |
9ebbca7d GK |
12428 | ? gen_addsi3 (tmp_reg, |
12429 | stack_limit_rtx, | |
12430 | GEN_INT (size)) | |
12431 | : gen_adddi3 (tmp_reg, | |
12432 | stack_limit_rtx, | |
12433 | GEN_INT (size))); | |
5b71a4e7 | 12434 | |
9ebbca7d GK |
12435 | emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg, |
12436 | const0_rtx)); | |
a157febd GK |
12437 | } |
12438 | else if (GET_CODE (stack_limit_rtx) == SYMBOL_REF | |
9ebbca7d | 12439 | && TARGET_32BIT |
f607bc57 | 12440 | && DEFAULT_ABI == ABI_V4) |
a157febd | 12441 | { |
9ebbca7d | 12442 | rtx toload = gen_rtx_CONST (VOIDmode, |
f676971a EC |
12443 | gen_rtx_PLUS (Pmode, |
12444 | stack_limit_rtx, | |
9ebbca7d | 12445 | GEN_INT (size))); |
5b71a4e7 | 12446 | |
9ebbca7d GK |
12447 | emit_insn (gen_elf_high (tmp_reg, toload)); |
12448 | emit_insn (gen_elf_low (tmp_reg, tmp_reg, toload)); | |
12449 | emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg, | |
12450 | const0_rtx)); | |
a157febd GK |
12451 | } |
12452 | else | |
d4ee4d25 | 12453 | warning (0, "stack limit expression is not supported"); |
a157febd GK |
12454 | } |
12455 | ||
9ebbca7d GK |
12456 | if (copy_r12 || ! TARGET_UPDATE) |
12457 | emit_move_insn (gen_rtx_REG (Pmode, 12), stack_reg); | |
12458 | ||
38c1f2d7 MM |
12459 | if (TARGET_UPDATE) |
12460 | { | |
9ebbca7d | 12461 | if (size > 32767) |
38c1f2d7 | 12462 | { |
9ebbca7d | 12463 | /* Need a note here so that try_split doesn't get confused. */ |
9390387d | 12464 | if (get_last_insn () == NULL_RTX) |
2e040219 | 12465 | emit_note (NOTE_INSN_DELETED); |
9ebbca7d GK |
12466 | insn = emit_move_insn (tmp_reg, todec); |
12467 | try_split (PATTERN (insn), insn, 0); | |
12468 | todec = tmp_reg; | |
38c1f2d7 | 12469 | } |
5b71a4e7 DE |
12470 | |
12471 | insn = emit_insn (TARGET_32BIT | |
12472 | ? gen_movsi_update (stack_reg, stack_reg, | |
12473 | todec, stack_reg) | |
c4ad648e | 12474 | : gen_movdi_di_update (stack_reg, stack_reg, |
9ebbca7d | 12475 | todec, stack_reg)); |
38c1f2d7 MM |
12476 | } |
12477 | else | |
12478 | { | |
5b71a4e7 DE |
12479 | insn = emit_insn (TARGET_32BIT |
12480 | ? gen_addsi3 (stack_reg, stack_reg, todec) | |
12481 | : gen_adddi3 (stack_reg, stack_reg, todec)); | |
9ebbca7d GK |
12482 | emit_move_insn (gen_rtx_MEM (Pmode, stack_reg), |
12483 | gen_rtx_REG (Pmode, 12)); | |
12484 | } | |
f676971a | 12485 | |
9ebbca7d | 12486 | RTX_FRAME_RELATED_P (insn) = 1; |
f676971a | 12487 | REG_NOTES (insn) = |
9ebbca7d | 12488 | gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, |
f676971a | 12489 | gen_rtx_SET (VOIDmode, stack_reg, |
9ebbca7d GK |
12490 | gen_rtx_PLUS (Pmode, stack_reg, |
12491 | GEN_INT (-size))), | |
12492 | REG_NOTES (insn)); | |
12493 | } | |
12494 | ||
a4f6c312 SS |
12495 | /* Add to 'insn' a note which is PATTERN (INSN) but with REG replaced |
12496 | with (plus:P (reg 1) VAL), and with REG2 replaced with RREG if REG2 | |
12497 | is not NULL. It would be nice if dwarf2out_frame_debug_expr could | |
12498 | deduce these equivalences by itself so it wasn't necessary to hold | |
12499 | its hand so much. */ | |
9ebbca7d GK |
12500 | |
12501 | static void | |
f676971a | 12502 | rs6000_frame_related (rtx insn, rtx reg, HOST_WIDE_INT val, |
a2369ed3 | 12503 | rtx reg2, rtx rreg) |
9ebbca7d GK |
12504 | { |
12505 | rtx real, temp; | |
12506 | ||
e56c4463 JL |
12507 | /* copy_rtx will not make unique copies of registers, so we need to |
12508 | ensure we don't have unwanted sharing here. */ | |
12509 | if (reg == reg2) | |
12510 | reg = gen_raw_REG (GET_MODE (reg), REGNO (reg)); | |
12511 | ||
12512 | if (reg == rreg) | |
12513 | reg = gen_raw_REG (GET_MODE (reg), REGNO (reg)); | |
12514 | ||
9ebbca7d GK |
12515 | real = copy_rtx (PATTERN (insn)); |
12516 | ||
89e7058f AH |
12517 | if (reg2 != NULL_RTX) |
12518 | real = replace_rtx (real, reg2, rreg); | |
f676971a EC |
12519 | |
12520 | real = replace_rtx (real, reg, | |
9ebbca7d GK |
12521 | gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode, |
12522 | STACK_POINTER_REGNUM), | |
12523 | GEN_INT (val))); | |
f676971a | 12524 | |
9ebbca7d GK |
12525 | /* We expect that 'real' is either a SET or a PARALLEL containing |
12526 | SETs (and possibly other stuff). In a PARALLEL, all the SETs | |
12527 | are important so they all have to be marked RTX_FRAME_RELATED_P. */ | |
12528 | ||
12529 | if (GET_CODE (real) == SET) | |
12530 | { | |
12531 | rtx set = real; | |
f676971a | 12532 | |
9ebbca7d GK |
12533 | temp = simplify_rtx (SET_SRC (set)); |
12534 | if (temp) | |
12535 | SET_SRC (set) = temp; | |
12536 | temp = simplify_rtx (SET_DEST (set)); | |
12537 | if (temp) | |
12538 | SET_DEST (set) = temp; | |
12539 | if (GET_CODE (SET_DEST (set)) == MEM) | |
38c1f2d7 | 12540 | { |
9ebbca7d GK |
12541 | temp = simplify_rtx (XEXP (SET_DEST (set), 0)); |
12542 | if (temp) | |
12543 | XEXP (SET_DEST (set), 0) = temp; | |
38c1f2d7 | 12544 | } |
38c1f2d7 | 12545 | } |
37409796 | 12546 | else |
9ebbca7d GK |
12547 | { |
12548 | int i; | |
37409796 NS |
12549 | |
12550 | gcc_assert (GET_CODE (real) == PARALLEL); | |
9ebbca7d GK |
12551 | for (i = 0; i < XVECLEN (real, 0); i++) |
12552 | if (GET_CODE (XVECEXP (real, 0, i)) == SET) | |
12553 | { | |
12554 | rtx set = XVECEXP (real, 0, i); | |
f676971a | 12555 | |
9ebbca7d GK |
12556 | temp = simplify_rtx (SET_SRC (set)); |
12557 | if (temp) | |
12558 | SET_SRC (set) = temp; | |
12559 | temp = simplify_rtx (SET_DEST (set)); | |
12560 | if (temp) | |
12561 | SET_DEST (set) = temp; | |
12562 | if (GET_CODE (SET_DEST (set)) == MEM) | |
12563 | { | |
12564 | temp = simplify_rtx (XEXP (SET_DEST (set), 0)); | |
12565 | if (temp) | |
12566 | XEXP (SET_DEST (set), 0) = temp; | |
12567 | } | |
12568 | RTX_FRAME_RELATED_P (set) = 1; | |
12569 | } | |
12570 | } | |
c19de7aa AH |
12571 | |
12572 | if (TARGET_SPE) | |
12573 | real = spe_synthesize_frame_save (real); | |
12574 | ||
9ebbca7d GK |
12575 | RTX_FRAME_RELATED_P (insn) = 1; |
12576 | REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, | |
12577 | real, | |
12578 | REG_NOTES (insn)); | |
38c1f2d7 MM |
12579 | } |
12580 | ||
c19de7aa AH |
12581 | /* Given an SPE frame note, return a PARALLEL of SETs with the |
12582 | original note, plus a synthetic register save. */ | |
12583 | ||
12584 | static rtx | |
a2369ed3 | 12585 | spe_synthesize_frame_save (rtx real) |
c19de7aa AH |
12586 | { |
12587 | rtx synth, offset, reg, real2; | |
12588 | ||
12589 | if (GET_CODE (real) != SET | |
12590 | || GET_MODE (SET_SRC (real)) != V2SImode) | |
12591 | return real; | |
12592 | ||
12593 | /* For the SPE, registers saved in 64-bits, get a PARALLEL for their | |
12594 | frame related note. The parallel contains a set of the register | |
41f3a930 | 12595 | being saved, and another set to a synthetic register (n+1200). |
c19de7aa AH |
12596 | This is so we can differentiate between 64-bit and 32-bit saves. |
12597 | Words cannot describe this nastiness. */ | |
12598 | ||
37409796 NS |
12599 | gcc_assert (GET_CODE (SET_DEST (real)) == MEM |
12600 | && GET_CODE (XEXP (SET_DEST (real), 0)) == PLUS | |
12601 | && GET_CODE (SET_SRC (real)) == REG); | |
c19de7aa AH |
12602 | |
12603 | /* Transform: | |
12604 | (set (mem (plus (reg x) (const y))) | |
12605 | (reg z)) | |
12606 | into: | |
12607 | (set (mem (plus (reg x) (const y+4))) | |
41f3a930 | 12608 | (reg z+1200)) |
c19de7aa AH |
12609 | */ |
12610 | ||
12611 | real2 = copy_rtx (real); | |
12612 | PUT_MODE (SET_DEST (real2), SImode); | |
12613 | reg = SET_SRC (real2); | |
12614 | real2 = replace_rtx (real2, reg, gen_rtx_REG (SImode, REGNO (reg))); | |
12615 | synth = copy_rtx (real2); | |
12616 | ||
12617 | if (BYTES_BIG_ENDIAN) | |
12618 | { | |
12619 | offset = XEXP (XEXP (SET_DEST (real2), 0), 1); | |
12620 | real2 = replace_rtx (real2, offset, GEN_INT (INTVAL (offset) + 4)); | |
12621 | } | |
12622 | ||
12623 | reg = SET_SRC (synth); | |
41f3a930 | 12624 | |
c19de7aa | 12625 | synth = replace_rtx (synth, reg, |
41f3a930 | 12626 | gen_rtx_REG (SImode, REGNO (reg) + 1200)); |
c19de7aa AH |
12627 | |
12628 | offset = XEXP (XEXP (SET_DEST (synth), 0), 1); | |
12629 | synth = replace_rtx (synth, offset, | |
12630 | GEN_INT (INTVAL (offset) | |
12631 | + (BYTES_BIG_ENDIAN ? 0 : 4))); | |
12632 | ||
12633 | RTX_FRAME_RELATED_P (synth) = 1; | |
12634 | RTX_FRAME_RELATED_P (real2) = 1; | |
12635 | if (BYTES_BIG_ENDIAN) | |
12636 | real = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, synth, real2)); | |
12637 | else | |
12638 | real = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, real2, synth)); | |
12639 | ||
12640 | return real; | |
12641 | } | |
12642 | ||
00b960c7 AH |
12643 | /* Returns an insn that has a vrsave set operation with the |
12644 | appropriate CLOBBERs. */ | |
12645 | ||
12646 | static rtx | |
a2369ed3 | 12647 | generate_set_vrsave (rtx reg, rs6000_stack_t *info, int epiloguep) |
00b960c7 AH |
12648 | { |
12649 | int nclobs, i; | |
12650 | rtx insn, clobs[TOTAL_ALTIVEC_REGS + 1]; | |
a004eb82 | 12651 | rtx vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO); |
00b960c7 | 12652 | |
a004eb82 AH |
12653 | clobs[0] |
12654 | = gen_rtx_SET (VOIDmode, | |
12655 | vrsave, | |
12656 | gen_rtx_UNSPEC_VOLATILE (SImode, | |
12657 | gen_rtvec (2, reg, vrsave), | |
12658 | 30)); | |
00b960c7 AH |
12659 | |
12660 | nclobs = 1; | |
12661 | ||
9aa86737 AH |
12662 | /* We need to clobber the registers in the mask so the scheduler |
12663 | does not move sets to VRSAVE before sets of AltiVec registers. | |
12664 | ||
12665 | However, if the function receives nonlocal gotos, reload will set | |
12666 | all call saved registers live. We will end up with: | |
12667 | ||
12668 | (set (reg 999) (mem)) | |
12669 | (parallel [ (set (reg vrsave) (unspec blah)) | |
12670 | (clobber (reg 999))]) | |
12671 | ||
12672 | The clobber will cause the store into reg 999 to be dead, and | |
12673 | flow will attempt to delete an epilogue insn. In this case, we | |
12674 | need an unspec use/set of the register. */ | |
00b960c7 AH |
12675 | |
12676 | for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i) | |
44688022 | 12677 | if (info->vrsave_mask & ALTIVEC_REG_BIT (i)) |
9aa86737 AH |
12678 | { |
12679 | if (!epiloguep || call_used_regs [i]) | |
12680 | clobs[nclobs++] = gen_rtx_CLOBBER (VOIDmode, | |
12681 | gen_rtx_REG (V4SImode, i)); | |
12682 | else | |
12683 | { | |
12684 | rtx reg = gen_rtx_REG (V4SImode, i); | |
9aa86737 AH |
12685 | |
12686 | clobs[nclobs++] | |
a004eb82 AH |
12687 | = gen_rtx_SET (VOIDmode, |
12688 | reg, | |
12689 | gen_rtx_UNSPEC (V4SImode, | |
12690 | gen_rtvec (1, reg), 27)); | |
9aa86737 AH |
12691 | } |
12692 | } | |
00b960c7 AH |
12693 | |
12694 | insn = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (nclobs)); | |
12695 | ||
12696 | for (i = 0; i < nclobs; ++i) | |
12697 | XVECEXP (insn, 0, i) = clobs[i]; | |
12698 | ||
12699 | return insn; | |
12700 | } | |
12701 | ||
89e7058f AH |
12702 | /* Save a register into the frame, and emit RTX_FRAME_RELATED_P notes. |
12703 | Save REGNO into [FRAME_REG + OFFSET] in mode MODE. */ | |
12704 | ||
12705 | static void | |
f676971a | 12706 | emit_frame_save (rtx frame_reg, rtx frame_ptr, enum machine_mode mode, |
d1d0c603 | 12707 | unsigned int regno, int offset, HOST_WIDE_INT total_size) |
89e7058f AH |
12708 | { |
12709 | rtx reg, offset_rtx, insn, mem, addr, int_rtx; | |
12710 | rtx replacea, replaceb; | |
12711 | ||
12712 | int_rtx = GEN_INT (offset); | |
12713 | ||
12714 | /* Some cases that need register indexed addressing. */ | |
12715 | if ((TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode)) | |
4d4cbc0e | 12716 | || (TARGET_E500_DOUBLE && mode == DFmode) |
a3170dc6 AH |
12717 | || (TARGET_SPE_ABI |
12718 | && SPE_VECTOR_MODE (mode) | |
12719 | && !SPE_CONST_OFFSET_OK (offset))) | |
89e7058f AH |
12720 | { |
12721 | /* Whomever calls us must make sure r11 is available in the | |
c4ad648e | 12722 | flow path of instructions in the prologue. */ |
89e7058f AH |
12723 | offset_rtx = gen_rtx_REG (Pmode, 11); |
12724 | emit_move_insn (offset_rtx, int_rtx); | |
12725 | ||
12726 | replacea = offset_rtx; | |
12727 | replaceb = int_rtx; | |
12728 | } | |
12729 | else | |
12730 | { | |
12731 | offset_rtx = int_rtx; | |
12732 | replacea = NULL_RTX; | |
12733 | replaceb = NULL_RTX; | |
12734 | } | |
12735 | ||
12736 | reg = gen_rtx_REG (mode, regno); | |
12737 | addr = gen_rtx_PLUS (Pmode, frame_reg, offset_rtx); | |
12738 | mem = gen_rtx_MEM (mode, addr); | |
12739 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
12740 | ||
12741 | insn = emit_move_insn (mem, reg); | |
12742 | ||
12743 | rs6000_frame_related (insn, frame_ptr, total_size, replacea, replaceb); | |
12744 | } | |
12745 | ||
a3170dc6 AH |
12746 | /* Emit an offset memory reference suitable for a frame store, while |
12747 | converting to a valid addressing mode. */ | |
12748 | ||
12749 | static rtx | |
a2369ed3 | 12750 | gen_frame_mem_offset (enum machine_mode mode, rtx reg, int offset) |
a3170dc6 AH |
12751 | { |
12752 | rtx int_rtx, offset_rtx; | |
12753 | ||
12754 | int_rtx = GEN_INT (offset); | |
12755 | ||
4d4cbc0e AH |
12756 | if ((TARGET_SPE_ABI && SPE_VECTOR_MODE (mode)) |
12757 | || (TARGET_E500_DOUBLE && mode == DFmode)) | |
a3170dc6 AH |
12758 | { |
12759 | offset_rtx = gen_rtx_REG (Pmode, FIXED_SCRATCH); | |
12760 | emit_move_insn (offset_rtx, int_rtx); | |
12761 | } | |
12762 | else | |
12763 | offset_rtx = int_rtx; | |
12764 | ||
12765 | return gen_rtx_MEM (mode, gen_rtx_PLUS (Pmode, reg, offset_rtx)); | |
12766 | } | |
12767 | ||
699c914a MS |
12768 | #ifndef TARGET_FIX_AND_CONTINUE |
12769 | #define TARGET_FIX_AND_CONTINUE 0 | |
12770 | #endif | |
12771 | ||
9ebbca7d GK |
12772 | /* Emit function prologue as insns. */ |
12773 | ||
9878760c | 12774 | void |
863d938c | 12775 | rs6000_emit_prologue (void) |
9878760c | 12776 | { |
4697a36c | 12777 | rs6000_stack_t *info = rs6000_stack_info (); |
0e67400a | 12778 | enum machine_mode reg_mode = Pmode; |
327e5343 | 12779 | int reg_size = TARGET_32BIT ? 4 : 8; |
9ebbca7d GK |
12780 | rtx sp_reg_rtx = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM); |
12781 | rtx frame_ptr_rtx = gen_rtx_REG (Pmode, 12); | |
12782 | rtx frame_reg_rtx = sp_reg_rtx; | |
b78d48dd | 12783 | rtx cr_save_rtx = NULL_RTX; |
9ebbca7d GK |
12784 | rtx insn; |
12785 | int saving_FPRs_inline; | |
12786 | int using_store_multiple; | |
12787 | HOST_WIDE_INT sp_offset = 0; | |
f676971a | 12788 | |
699c914a MS |
12789 | if (TARGET_FIX_AND_CONTINUE) |
12790 | { | |
12791 | /* gdb on darwin arranges to forward a function from the old | |
de2ab0ca | 12792 | address by modifying the first 5 instructions of the function |
699c914a MS |
12793 | to branch to the overriding function. This is necessary to |
12794 | permit function pointers that point to the old function to | |
12795 | actually forward to the new function. */ | |
12796 | emit_insn (gen_nop ()); | |
12797 | emit_insn (gen_nop ()); | |
de2ab0ca | 12798 | emit_insn (gen_nop ()); |
699c914a MS |
12799 | emit_insn (gen_nop ()); |
12800 | emit_insn (gen_nop ()); | |
12801 | } | |
12802 | ||
12803 | if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0) | |
12804 | { | |
12805 | reg_mode = V2SImode; | |
12806 | reg_size = 8; | |
12807 | } | |
a3170dc6 | 12808 | |
9ebbca7d | 12809 | using_store_multiple = (TARGET_MULTIPLE && ! TARGET_POWERPC64 |
c19de7aa AH |
12810 | && (!TARGET_SPE_ABI |
12811 | || info->spe_64bit_regs_used == 0) | |
9ebbca7d GK |
12812 | && info->first_gp_reg_save < 31); |
12813 | saving_FPRs_inline = (info->first_fp_reg_save == 64 | |
8c29550d | 12814 | || FP_SAVE_INLINE (info->first_fp_reg_save) |
acd0b319 | 12815 | || current_function_calls_eh_return |
8c29550d | 12816 | || cfun->machine->ra_need_lr); |
9ebbca7d GK |
12817 | |
12818 | /* For V.4, update stack before we do any saving and set back pointer. */ | |
fc4767bb | 12819 | if (info->push_p |
acd0b319 AM |
12820 | && (DEFAULT_ABI == ABI_V4 |
12821 | || current_function_calls_eh_return)) | |
9ebbca7d GK |
12822 | { |
12823 | if (info->total_size < 32767) | |
12824 | sp_offset = info->total_size; | |
12825 | else | |
12826 | frame_reg_rtx = frame_ptr_rtx; | |
f676971a | 12827 | rs6000_emit_allocate_stack (info->total_size, |
9ebbca7d GK |
12828 | (frame_reg_rtx != sp_reg_rtx |
12829 | && (info->cr_save_p | |
12830 | || info->lr_save_p | |
12831 | || info->first_fp_reg_save < 64 | |
12832 | || info->first_gp_reg_save < 32 | |
12833 | ))); | |
12834 | if (frame_reg_rtx != sp_reg_rtx) | |
12835 | rs6000_emit_stack_tie (); | |
12836 | } | |
12837 | ||
d62294f5 | 12838 | /* Handle world saves specially here. */ |
f57fe068 | 12839 | if (WORLD_SAVE_P (info)) |
d62294f5 FJ |
12840 | { |
12841 | int i, j, sz; | |
12842 | rtx treg; | |
12843 | rtvec p; | |
12844 | ||
12845 | /* save_world expects lr in r0. */ | |
12846 | if (info->lr_save_p) | |
c4ad648e AM |
12847 | { |
12848 | insn = emit_move_insn (gen_rtx_REG (Pmode, 0), | |
12849 | gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)); | |
12850 | RTX_FRAME_RELATED_P (insn) = 1; | |
12851 | } | |
d62294f5 FJ |
12852 | |
12853 | /* The SAVE_WORLD and RESTORE_WORLD routines make a number of | |
c4ad648e AM |
12854 | assumptions about the offsets of various bits of the stack |
12855 | frame. Abort if things aren't what they should be. */ | |
37409796 NS |
12856 | gcc_assert (info->gp_save_offset == -220 |
12857 | && info->fp_save_offset == -144 | |
12858 | && info->lr_save_offset == 8 | |
12859 | && info->cr_save_offset == 4 | |
12860 | && info->push_p | |
12861 | && info->lr_save_p | |
12862 | && (!current_function_calls_eh_return | |
12863 | || info->ehrd_offset == -432) | |
12864 | && info->vrsave_save_offset == -224 | |
12865 | && info->altivec_save_offset == (-224 -16 -192)); | |
d62294f5 FJ |
12866 | |
12867 | treg = gen_rtx_REG (SImode, 11); | |
12868 | emit_move_insn (treg, GEN_INT (-info->total_size)); | |
12869 | ||
12870 | /* SAVE_WORLD takes the caller's LR in R0 and the frame size | |
c4ad648e | 12871 | in R11. It also clobbers R12, so beware! */ |
d62294f5 FJ |
12872 | |
12873 | /* Preserve CR2 for save_world prologues */ | |
12874 | sz = 6; | |
12875 | sz += 32 - info->first_gp_reg_save; | |
12876 | sz += 64 - info->first_fp_reg_save; | |
12877 | sz += LAST_ALTIVEC_REGNO - info->first_altivec_reg_save + 1; | |
12878 | p = rtvec_alloc (sz); | |
12879 | j = 0; | |
12880 | RTVEC_ELT (p, j++) = gen_rtx_CLOBBER (VOIDmode, | |
c4ad648e AM |
12881 | gen_rtx_REG (Pmode, |
12882 | LINK_REGISTER_REGNUM)); | |
d62294f5 | 12883 | RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode, |
c4ad648e AM |
12884 | gen_rtx_SYMBOL_REF (Pmode, |
12885 | "*save_world")); | |
d62294f5 | 12886 | /* We do floats first so that the instruction pattern matches |
c4ad648e AM |
12887 | properly. */ |
12888 | for (i = 0; i < 64 - info->first_fp_reg_save; i++) | |
12889 | { | |
12890 | rtx reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i); | |
12891 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
12892 | GEN_INT (info->fp_save_offset | |
12893 | + sp_offset + 8 * i)); | |
12894 | rtx mem = gen_rtx_MEM (DFmode, addr); | |
12895 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
12896 | ||
12897 | RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg); | |
12898 | } | |
d62294f5 | 12899 | for (i = 0; info->first_altivec_reg_save + i <= LAST_ALTIVEC_REGNO; i++) |
c4ad648e AM |
12900 | { |
12901 | rtx reg = gen_rtx_REG (V4SImode, info->first_altivec_reg_save + i); | |
12902 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
12903 | GEN_INT (info->altivec_save_offset | |
12904 | + sp_offset + 16 * i)); | |
12905 | rtx mem = gen_rtx_MEM (V4SImode, addr); | |
12906 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
12907 | ||
12908 | RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg); | |
12909 | } | |
d62294f5 | 12910 | for (i = 0; i < 32 - info->first_gp_reg_save; i++) |
c4ad648e AM |
12911 | { |
12912 | rtx reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i); | |
12913 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
12914 | GEN_INT (info->gp_save_offset | |
12915 | + sp_offset + reg_size * i)); | |
12916 | rtx mem = gen_rtx_MEM (reg_mode, addr); | |
12917 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
12918 | ||
12919 | RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg); | |
12920 | } | |
12921 | ||
12922 | { | |
12923 | /* CR register traditionally saved as CR2. */ | |
12924 | rtx reg = gen_rtx_REG (reg_mode, CR2_REGNO); | |
12925 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
12926 | GEN_INT (info->cr_save_offset | |
12927 | + sp_offset)); | |
12928 | rtx mem = gen_rtx_MEM (reg_mode, addr); | |
12929 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
12930 | ||
12931 | RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg); | |
12932 | } | |
d62294f5 FJ |
12933 | /* Prevent any attempt to delete the setting of r0 and treg! */ |
12934 | RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode, gen_rtx_REG (Pmode, 0)); | |
12935 | RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode, treg); | |
12936 | RTVEC_ELT (p, j++) = gen_rtx_CLOBBER (VOIDmode, sp_reg_rtx); | |
12937 | ||
12938 | insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p)); | |
12939 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, | |
c4ad648e | 12940 | NULL_RTX, NULL_RTX); |
d62294f5 FJ |
12941 | |
12942 | if (current_function_calls_eh_return) | |
c4ad648e AM |
12943 | { |
12944 | unsigned int i; | |
12945 | for (i = 0; ; ++i) | |
12946 | { | |
12947 | unsigned int regno = EH_RETURN_DATA_REGNO (i); | |
12948 | if (regno == INVALID_REGNUM) | |
12949 | break; | |
12950 | emit_frame_save (frame_reg_rtx, frame_ptr_rtx, reg_mode, regno, | |
12951 | info->ehrd_offset + sp_offset | |
12952 | + reg_size * (int) i, | |
12953 | info->total_size); | |
12954 | } | |
12955 | } | |
d62294f5 FJ |
12956 | } |
12957 | ||
9aa86737 | 12958 | /* Save AltiVec registers if needed. */ |
f57fe068 | 12959 | if (!WORLD_SAVE_P (info) && TARGET_ALTIVEC_ABI && info->altivec_size != 0) |
9aa86737 AH |
12960 | { |
12961 | int i; | |
12962 | ||
12963 | /* There should be a non inline version of this, for when we | |
12964 | are saving lots of vector registers. */ | |
12965 | for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i) | |
12966 | if (info->vrsave_mask & ALTIVEC_REG_BIT (i)) | |
12967 | { | |
12968 | rtx areg, savereg, mem; | |
12969 | int offset; | |
12970 | ||
12971 | offset = info->altivec_save_offset + sp_offset | |
12972 | + 16 * (i - info->first_altivec_reg_save); | |
12973 | ||
12974 | savereg = gen_rtx_REG (V4SImode, i); | |
12975 | ||
12976 | areg = gen_rtx_REG (Pmode, 0); | |
12977 | emit_move_insn (areg, GEN_INT (offset)); | |
12978 | ||
12979 | /* AltiVec addressing mode is [reg+reg]. */ | |
12980 | mem = gen_rtx_MEM (V4SImode, | |
12981 | gen_rtx_PLUS (Pmode, frame_reg_rtx, areg)); | |
f676971a | 12982 | |
9aa86737 AH |
12983 | set_mem_alias_set (mem, rs6000_sr_alias_set); |
12984 | ||
12985 | insn = emit_move_insn (mem, savereg); | |
12986 | ||
5c242421 SB |
12987 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, |
12988 | areg, GEN_INT (offset)); | |
9aa86737 AH |
12989 | } |
12990 | } | |
12991 | ||
12992 | /* VRSAVE is a bit vector representing which AltiVec registers | |
12993 | are used. The OS uses this to determine which vector | |
12994 | registers to save on a context switch. We need to save | |
12995 | VRSAVE on the stack frame, add whatever AltiVec registers we | |
12996 | used in this function, and do the corresponding magic in the | |
12997 | epilogue. */ | |
12998 | ||
4d774ff8 | 12999 | if (TARGET_ALTIVEC && TARGET_ALTIVEC_VRSAVE |
f57fe068 | 13000 | && !WORLD_SAVE_P (info) && info->vrsave_mask != 0) |
9aa86737 | 13001 | { |
a004eb82 | 13002 | rtx reg, mem, vrsave; |
9aa86737 AH |
13003 | int offset; |
13004 | ||
eab97e44 AM |
13005 | /* Get VRSAVE onto a GPR. Note that ABI_V4 might be using r12 |
13006 | as frame_reg_rtx and r11 as the static chain pointer for | |
13007 | nested functions. */ | |
13008 | reg = gen_rtx_REG (SImode, 0); | |
a004eb82 | 13009 | vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO); |
b188f760 AH |
13010 | if (TARGET_MACHO) |
13011 | emit_insn (gen_get_vrsave_internal (reg)); | |
13012 | else | |
13013 | emit_insn (gen_rtx_SET (VOIDmode, reg, vrsave)); | |
9aa86737 AH |
13014 | |
13015 | /* Save VRSAVE. */ | |
13016 | offset = info->vrsave_save_offset + sp_offset; | |
13017 | mem | |
13018 | = gen_rtx_MEM (SImode, | |
13019 | gen_rtx_PLUS (Pmode, frame_reg_rtx, GEN_INT (offset))); | |
13020 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
13021 | insn = emit_move_insn (mem, reg); | |
13022 | ||
13023 | /* Include the registers in the mask. */ | |
13024 | emit_insn (gen_iorsi3 (reg, reg, GEN_INT ((int) info->vrsave_mask))); | |
13025 | ||
13026 | insn = emit_insn (generate_set_vrsave (reg, info, 0)); | |
13027 | } | |
13028 | ||
9ebbca7d | 13029 | /* If we use the link register, get it into r0. */ |
f57fe068 | 13030 | if (!WORLD_SAVE_P (info) && info->lr_save_p) |
f8a57be8 GK |
13031 | { |
13032 | insn = emit_move_insn (gen_rtx_REG (Pmode, 0), | |
13033 | gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)); | |
13034 | RTX_FRAME_RELATED_P (insn) = 1; | |
13035 | } | |
9ebbca7d GK |
13036 | |
13037 | /* If we need to save CR, put it into r12. */ | |
f57fe068 | 13038 | if (!WORLD_SAVE_P (info) && info->cr_save_p && frame_reg_rtx != frame_ptr_rtx) |
9ebbca7d | 13039 | { |
f8a57be8 | 13040 | rtx set; |
f676971a | 13041 | |
9ebbca7d | 13042 | cr_save_rtx = gen_rtx_REG (SImode, 12); |
f8a57be8 GK |
13043 | insn = emit_insn (gen_movesi_from_cr (cr_save_rtx)); |
13044 | RTX_FRAME_RELATED_P (insn) = 1; | |
13045 | /* Now, there's no way that dwarf2out_frame_debug_expr is going | |
13046 | to understand '(unspec:SI [(reg:CC 68) ...] UNSPEC_MOVESI_FROM_CR)'. | |
13047 | But that's OK. All we have to do is specify that _one_ condition | |
13048 | code register is saved in this stack slot. The thrower's epilogue | |
13049 | will then restore all the call-saved registers. | |
13050 | We use CR2_REGNO (70) to be compatible with gcc-2.95 on Linux. */ | |
13051 | set = gen_rtx_SET (VOIDmode, cr_save_rtx, | |
13052 | gen_rtx_REG (SImode, CR2_REGNO)); | |
13053 | REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, | |
13054 | set, | |
13055 | REG_NOTES (insn)); | |
9ebbca7d GK |
13056 | } |
13057 | ||
a4f6c312 SS |
13058 | /* Do any required saving of fpr's. If only one or two to save, do |
13059 | it ourselves. Otherwise, call function. */ | |
f57fe068 | 13060 | if (!WORLD_SAVE_P (info) && saving_FPRs_inline) |
9ebbca7d GK |
13061 | { |
13062 | int i; | |
13063 | for (i = 0; i < 64 - info->first_fp_reg_save; i++) | |
f676971a | 13064 | if ((regs_ever_live[info->first_fp_reg_save+i] |
9ebbca7d | 13065 | && ! call_used_regs[info->first_fp_reg_save+i])) |
89e7058f AH |
13066 | emit_frame_save (frame_reg_rtx, frame_ptr_rtx, DFmode, |
13067 | info->first_fp_reg_save + i, | |
13068 | info->fp_save_offset + sp_offset + 8 * i, | |
13069 | info->total_size); | |
9ebbca7d | 13070 | } |
f57fe068 | 13071 | else if (!WORLD_SAVE_P (info) && info->first_fp_reg_save != 64) |
9ebbca7d GK |
13072 | { |
13073 | int i; | |
13074 | char rname[30]; | |
520a57c8 | 13075 | const char *alloc_rname; |
9ebbca7d GK |
13076 | rtvec p; |
13077 | p = rtvec_alloc (2 + 64 - info->first_fp_reg_save); | |
f676971a EC |
13078 | |
13079 | RTVEC_ELT (p, 0) = gen_rtx_CLOBBER (VOIDmode, | |
13080 | gen_rtx_REG (Pmode, | |
9ebbca7d GK |
13081 | LINK_REGISTER_REGNUM)); |
13082 | sprintf (rname, "%s%d%s", SAVE_FP_PREFIX, | |
13083 | info->first_fp_reg_save - 32, SAVE_FP_SUFFIX); | |
a8a05998 | 13084 | alloc_rname = ggc_strdup (rname); |
9ebbca7d GK |
13085 | RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode, |
13086 | gen_rtx_SYMBOL_REF (Pmode, | |
13087 | alloc_rname)); | |
13088 | for (i = 0; i < 64 - info->first_fp_reg_save; i++) | |
13089 | { | |
13090 | rtx addr, reg, mem; | |
13091 | reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i); | |
13092 | addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
f676971a | 13093 | GEN_INT (info->fp_save_offset |
9ebbca7d GK |
13094 | + sp_offset + 8*i)); |
13095 | mem = gen_rtx_MEM (DFmode, addr); | |
ba4828e0 | 13096 | set_mem_alias_set (mem, rs6000_sr_alias_set); |
9ebbca7d GK |
13097 | |
13098 | RTVEC_ELT (p, i + 2) = gen_rtx_SET (VOIDmode, mem, reg); | |
13099 | } | |
13100 | insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p)); | |
f676971a | 13101 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, |
9ebbca7d GK |
13102 | NULL_RTX, NULL_RTX); |
13103 | } | |
b6c9286a | 13104 | |
9ebbca7d GK |
13105 | /* Save GPRs. This is done as a PARALLEL if we are using |
13106 | the store-multiple instructions. */ | |
f57fe068 | 13107 | if (!WORLD_SAVE_P (info) && using_store_multiple) |
b6c9286a | 13108 | { |
308c142a | 13109 | rtvec p; |
9ebbca7d GK |
13110 | int i; |
13111 | p = rtvec_alloc (32 - info->first_gp_reg_save); | |
9ebbca7d GK |
13112 | for (i = 0; i < 32 - info->first_gp_reg_save; i++) |
13113 | { | |
13114 | rtx addr, reg, mem; | |
13115 | reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i); | |
f676971a EC |
13116 | addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, |
13117 | GEN_INT (info->gp_save_offset | |
13118 | + sp_offset | |
9ebbca7d GK |
13119 | + reg_size * i)); |
13120 | mem = gen_rtx_MEM (reg_mode, addr); | |
ba4828e0 | 13121 | set_mem_alias_set (mem, rs6000_sr_alias_set); |
9ebbca7d GK |
13122 | |
13123 | RTVEC_ELT (p, i) = gen_rtx_SET (VOIDmode, mem, reg); | |
13124 | } | |
13125 | insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p)); | |
f676971a | 13126 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, |
9ebbca7d | 13127 | NULL_RTX, NULL_RTX); |
b6c9286a | 13128 | } |
f57fe068 | 13129 | else if (!WORLD_SAVE_P (info)) |
b6c9286a | 13130 | { |
9ebbca7d GK |
13131 | int i; |
13132 | for (i = 0; i < 32 - info->first_gp_reg_save; i++) | |
f676971a | 13133 | if ((regs_ever_live[info->first_gp_reg_save+i] |
b4db40bf JJ |
13134 | && (! call_used_regs[info->first_gp_reg_save+i] |
13135 | || (i+info->first_gp_reg_save | |
13136 | == RS6000_PIC_OFFSET_TABLE_REGNUM | |
13137 | && TARGET_TOC && TARGET_MINIMAL_TOC))) | |
1db02437 | 13138 | || (i+info->first_gp_reg_save == RS6000_PIC_OFFSET_TABLE_REGNUM |
14f00213 | 13139 | && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0) |
f607bc57 | 13140 | || (DEFAULT_ABI == ABI_DARWIN && flag_pic)))) |
a3170dc6 AH |
13141 | { |
13142 | rtx addr, reg, mem; | |
13143 | reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i); | |
13144 | ||
c19de7aa | 13145 | if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0) |
a3170dc6 AH |
13146 | { |
13147 | int offset = info->spe_gp_save_offset + sp_offset + 8 * i; | |
13148 | rtx b; | |
13149 | ||
13150 | if (!SPE_CONST_OFFSET_OK (offset)) | |
13151 | { | |
13152 | b = gen_rtx_REG (Pmode, FIXED_SCRATCH); | |
13153 | emit_move_insn (b, GEN_INT (offset)); | |
13154 | } | |
13155 | else | |
13156 | b = GEN_INT (offset); | |
13157 | ||
13158 | addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, b); | |
13159 | mem = gen_rtx_MEM (V2SImode, addr); | |
13160 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
13161 | insn = emit_move_insn (mem, reg); | |
13162 | ||
13163 | if (GET_CODE (b) == CONST_INT) | |
13164 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, | |
13165 | NULL_RTX, NULL_RTX); | |
13166 | else | |
13167 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, | |
13168 | b, GEN_INT (offset)); | |
13169 | } | |
13170 | else | |
13171 | { | |
f676971a EC |
13172 | addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, |
13173 | GEN_INT (info->gp_save_offset | |
13174 | + sp_offset | |
a3170dc6 AH |
13175 | + reg_size * i)); |
13176 | mem = gen_rtx_MEM (reg_mode, addr); | |
13177 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
13178 | ||
13179 | insn = emit_move_insn (mem, reg); | |
f676971a | 13180 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, |
a3170dc6 AH |
13181 | NULL_RTX, NULL_RTX); |
13182 | } | |
13183 | } | |
9ebbca7d GK |
13184 | } |
13185 | ||
83720594 RH |
13186 | /* ??? There's no need to emit actual instructions here, but it's the |
13187 | easiest way to get the frame unwind information emitted. */ | |
f57fe068 | 13188 | if (!WORLD_SAVE_P (info) && current_function_calls_eh_return) |
83720594 | 13189 | { |
78e1b90d DE |
13190 | unsigned int i, regno; |
13191 | ||
fc4767bb JJ |
13192 | /* In AIX ABI we need to pretend we save r2 here. */ |
13193 | if (TARGET_AIX) | |
13194 | { | |
13195 | rtx addr, reg, mem; | |
13196 | ||
13197 | reg = gen_rtx_REG (reg_mode, 2); | |
13198 | addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
13199 | GEN_INT (sp_offset + 5 * reg_size)); | |
13200 | mem = gen_rtx_MEM (reg_mode, addr); | |
13201 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
13202 | ||
13203 | insn = emit_move_insn (mem, reg); | |
f676971a | 13204 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, |
fc4767bb JJ |
13205 | NULL_RTX, NULL_RTX); |
13206 | PATTERN (insn) = gen_blockage (); | |
13207 | } | |
13208 | ||
83720594 RH |
13209 | for (i = 0; ; ++i) |
13210 | { | |
83720594 RH |
13211 | regno = EH_RETURN_DATA_REGNO (i); |
13212 | if (regno == INVALID_REGNUM) | |
13213 | break; | |
13214 | ||
89e7058f AH |
13215 | emit_frame_save (frame_reg_rtx, frame_ptr_rtx, reg_mode, regno, |
13216 | info->ehrd_offset + sp_offset | |
13217 | + reg_size * (int) i, | |
13218 | info->total_size); | |
83720594 RH |
13219 | } |
13220 | } | |
13221 | ||
9ebbca7d | 13222 | /* Save lr if we used it. */ |
f57fe068 | 13223 | if (!WORLD_SAVE_P (info) && info->lr_save_p) |
9ebbca7d GK |
13224 | { |
13225 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
13226 | GEN_INT (info->lr_save_offset + sp_offset)); | |
13227 | rtx reg = gen_rtx_REG (Pmode, 0); | |
13228 | rtx mem = gen_rtx_MEM (Pmode, addr); | |
13229 | /* This should not be of rs6000_sr_alias_set, because of | |
13230 | __builtin_return_address. */ | |
f676971a | 13231 | |
9ebbca7d | 13232 | insn = emit_move_insn (mem, reg); |
f676971a | 13233 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, |
f8a57be8 | 13234 | NULL_RTX, NULL_RTX); |
9ebbca7d GK |
13235 | } |
13236 | ||
13237 | /* Save CR if we use any that must be preserved. */ | |
f57fe068 | 13238 | if (!WORLD_SAVE_P (info) && info->cr_save_p) |
9ebbca7d GK |
13239 | { |
13240 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
13241 | GEN_INT (info->cr_save_offset + sp_offset)); | |
13242 | rtx mem = gen_rtx_MEM (SImode, addr); | |
f8a57be8 GK |
13243 | /* See the large comment above about why CR2_REGNO is used. */ |
13244 | rtx magic_eh_cr_reg = gen_rtx_REG (SImode, CR2_REGNO); | |
ba4828e0 RK |
13245 | |
13246 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
9ebbca7d GK |
13247 | |
13248 | /* If r12 was used to hold the original sp, copy cr into r0 now | |
13249 | that it's free. */ | |
13250 | if (REGNO (frame_reg_rtx) == 12) | |
13251 | { | |
f8a57be8 GK |
13252 | rtx set; |
13253 | ||
9ebbca7d | 13254 | cr_save_rtx = gen_rtx_REG (SImode, 0); |
f8a57be8 GK |
13255 | insn = emit_insn (gen_movesi_from_cr (cr_save_rtx)); |
13256 | RTX_FRAME_RELATED_P (insn) = 1; | |
13257 | set = gen_rtx_SET (VOIDmode, cr_save_rtx, magic_eh_cr_reg); | |
13258 | REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, | |
13259 | set, | |
13260 | REG_NOTES (insn)); | |
f676971a | 13261 | |
9ebbca7d GK |
13262 | } |
13263 | insn = emit_move_insn (mem, cr_save_rtx); | |
13264 | ||
f676971a | 13265 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, |
f8a57be8 | 13266 | NULL_RTX, NULL_RTX); |
9ebbca7d GK |
13267 | } |
13268 | ||
f676971a | 13269 | /* Update stack and set back pointer unless this is V.4, |
9ebbca7d | 13270 | for which it was done previously. */ |
f57fe068 | 13271 | if (!WORLD_SAVE_P (info) && info->push_p |
fc4767bb | 13272 | && !(DEFAULT_ABI == ABI_V4 || current_function_calls_eh_return)) |
9ebbca7d GK |
13273 | rs6000_emit_allocate_stack (info->total_size, FALSE); |
13274 | ||
13275 | /* Set frame pointer, if needed. */ | |
13276 | if (frame_pointer_needed) | |
13277 | { | |
f676971a | 13278 | insn = emit_move_insn (gen_rtx_REG (Pmode, FRAME_POINTER_REGNUM), |
9ebbca7d GK |
13279 | sp_reg_rtx); |
13280 | RTX_FRAME_RELATED_P (insn) = 1; | |
b6c9286a | 13281 | } |
9878760c | 13282 | |
1db02437 | 13283 | /* If we are using RS6000_PIC_OFFSET_TABLE_REGNUM, we need to set it up. */ |
9ebbca7d | 13284 | if ((TARGET_TOC && TARGET_MINIMAL_TOC && get_pool_size () != 0) |
f607bc57 | 13285 | || (DEFAULT_ABI == ABI_V4 && flag_pic == 1 |
1db02437 | 13286 | && regs_ever_live[RS6000_PIC_OFFSET_TABLE_REGNUM])) |
c4ad648e AM |
13287 | { |
13288 | /* If emit_load_toc_table will use the link register, we need to save | |
13289 | it. We use R12 for this purpose because emit_load_toc_table | |
13290 | can use register 0. This allows us to use a plain 'blr' to return | |
13291 | from the procedure more often. */ | |
13292 | int save_LR_around_toc_setup = (TARGET_ELF | |
13293 | && DEFAULT_ABI != ABI_AIX | |
13294 | && flag_pic | |
13295 | && ! info->lr_save_p | |
13296 | && EDGE_COUNT (EXIT_BLOCK_PTR->preds) > 0); | |
13297 | if (save_LR_around_toc_setup) | |
13298 | { | |
13299 | rtx lr = gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM); | |
f8a57be8 | 13300 | |
c4ad648e AM |
13301 | insn = emit_move_insn (frame_ptr_rtx, lr); |
13302 | rs6000_maybe_dead (insn); | |
13303 | RTX_FRAME_RELATED_P (insn) = 1; | |
f8a57be8 | 13304 | |
c4ad648e | 13305 | rs6000_emit_load_toc_table (TRUE); |
f8a57be8 | 13306 | |
c4ad648e AM |
13307 | insn = emit_move_insn (lr, frame_ptr_rtx); |
13308 | rs6000_maybe_dead (insn); | |
13309 | RTX_FRAME_RELATED_P (insn) = 1; | |
13310 | } | |
13311 | else | |
13312 | rs6000_emit_load_toc_table (TRUE); | |
13313 | } | |
ee890fe2 | 13314 | |
fcce224d | 13315 | #if TARGET_MACHO |
ee890fe2 SS |
13316 | if (DEFAULT_ABI == ABI_DARWIN |
13317 | && flag_pic && current_function_uses_pic_offset_table) | |
13318 | { | |
f8a57be8 | 13319 | rtx lr = gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM); |
11abc112 | 13320 | rtx src = machopic_function_base_sym (); |
ee890fe2 | 13321 | |
f8a57be8 | 13322 | rs6000_maybe_dead (emit_insn (gen_load_macho_picbase (lr, src))); |
ee890fe2 | 13323 | |
f676971a | 13324 | insn = emit_move_insn (gen_rtx_REG (Pmode, |
f8a57be8 GK |
13325 | RS6000_PIC_OFFSET_TABLE_REGNUM), |
13326 | lr); | |
13327 | rs6000_maybe_dead (insn); | |
ee890fe2 | 13328 | } |
fcce224d | 13329 | #endif |
9ebbca7d GK |
13330 | } |
13331 | ||
9ebbca7d | 13332 | /* Write function prologue. */ |
a4f6c312 | 13333 | |
08c148a8 | 13334 | static void |
f676971a | 13335 | rs6000_output_function_prologue (FILE *file, |
a2369ed3 | 13336 | HOST_WIDE_INT size ATTRIBUTE_UNUSED) |
9ebbca7d GK |
13337 | { |
13338 | rs6000_stack_t *info = rs6000_stack_info (); | |
13339 | ||
4697a36c MM |
13340 | if (TARGET_DEBUG_STACK) |
13341 | debug_stack_info (info); | |
9878760c | 13342 | |
a4f6c312 SS |
13343 | /* Write .extern for any function we will call to save and restore |
13344 | fp values. */ | |
13345 | if (info->first_fp_reg_save < 64 | |
13346 | && !FP_SAVE_INLINE (info->first_fp_reg_save)) | |
4d30c363 | 13347 | fprintf (file, "\t.extern %s%d%s\n\t.extern %s%d%s\n", |
4697a36c | 13348 | SAVE_FP_PREFIX, info->first_fp_reg_save - 32, SAVE_FP_SUFFIX, |
a4f6c312 SS |
13349 | RESTORE_FP_PREFIX, info->first_fp_reg_save - 32, |
13350 | RESTORE_FP_SUFFIX); | |
9878760c | 13351 | |
c764f757 RK |
13352 | /* Write .extern for AIX common mode routines, if needed. */ |
13353 | if (! TARGET_POWER && ! TARGET_POWERPC && ! common_mode_defined) | |
13354 | { | |
f6709c70 JW |
13355 | fputs ("\t.extern __mulh\n", file); |
13356 | fputs ("\t.extern __mull\n", file); | |
13357 | fputs ("\t.extern __divss\n", file); | |
13358 | fputs ("\t.extern __divus\n", file); | |
13359 | fputs ("\t.extern __quoss\n", file); | |
13360 | fputs ("\t.extern __quous\n", file); | |
c764f757 RK |
13361 | common_mode_defined = 1; |
13362 | } | |
9878760c | 13363 | |
9ebbca7d | 13364 | if (! HAVE_prologue) |
979721f8 | 13365 | { |
9ebbca7d | 13366 | start_sequence (); |
9dda4cc8 | 13367 | |
a4f6c312 SS |
13368 | /* A NOTE_INSN_DELETED is supposed to be at the start and end of |
13369 | the "toplevel" insn chain. */ | |
2e040219 | 13370 | emit_note (NOTE_INSN_DELETED); |
9ebbca7d | 13371 | rs6000_emit_prologue (); |
2e040219 | 13372 | emit_note (NOTE_INSN_DELETED); |
178c3eff | 13373 | |
a3c9585f | 13374 | /* Expand INSN_ADDRESSES so final() doesn't crash. */ |
178c3eff DJ |
13375 | { |
13376 | rtx insn; | |
13377 | unsigned addr = 0; | |
13378 | for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn)) | |
13379 | { | |
13380 | INSN_ADDRESSES_NEW (insn, addr); | |
13381 | addr += 4; | |
13382 | } | |
13383 | } | |
9dda4cc8 | 13384 | |
9ebbca7d | 13385 | if (TARGET_DEBUG_STACK) |
a4f6c312 | 13386 | debug_rtx_list (get_insns (), 100); |
c9d691e9 | 13387 | final (get_insns (), file, FALSE); |
9ebbca7d | 13388 | end_sequence (); |
979721f8 MM |
13389 | } |
13390 | ||
9ebbca7d GK |
13391 | rs6000_pic_labelno++; |
13392 | } | |
f676971a | 13393 | |
9ebbca7d | 13394 | /* Emit function epilogue as insns. |
9878760c | 13395 | |
9ebbca7d GK |
13396 | At present, dwarf2out_frame_debug_expr doesn't understand |
13397 | register restores, so we don't bother setting RTX_FRAME_RELATED_P | |
13398 | anywhere in the epilogue. Most of the insns below would in any case | |
13399 | need special notes to explain where r11 is in relation to the stack. */ | |
9878760c | 13400 | |
9ebbca7d | 13401 | void |
a2369ed3 | 13402 | rs6000_emit_epilogue (int sibcall) |
9ebbca7d GK |
13403 | { |
13404 | rs6000_stack_t *info; | |
13405 | int restoring_FPRs_inline; | |
13406 | int using_load_multiple; | |
13407 | int using_mfcr_multiple; | |
13408 | int use_backchain_to_restore_sp; | |
13409 | int sp_offset = 0; | |
13410 | rtx sp_reg_rtx = gen_rtx_REG (Pmode, 1); | |
13411 | rtx frame_reg_rtx = sp_reg_rtx; | |
0e67400a | 13412 | enum machine_mode reg_mode = Pmode; |
327e5343 | 13413 | int reg_size = TARGET_32BIT ? 4 : 8; |
9ebbca7d GK |
13414 | int i; |
13415 | ||
c19de7aa AH |
13416 | info = rs6000_stack_info (); |
13417 | ||
13418 | if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0) | |
a3170dc6 AH |
13419 | { |
13420 | reg_mode = V2SImode; | |
13421 | reg_size = 8; | |
13422 | } | |
13423 | ||
9ebbca7d | 13424 | using_load_multiple = (TARGET_MULTIPLE && ! TARGET_POWERPC64 |
c19de7aa AH |
13425 | && (!TARGET_SPE_ABI |
13426 | || info->spe_64bit_regs_used == 0) | |
9ebbca7d GK |
13427 | && info->first_gp_reg_save < 31); |
13428 | restoring_FPRs_inline = (sibcall | |
83720594 | 13429 | || current_function_calls_eh_return |
9ebbca7d GK |
13430 | || info->first_fp_reg_save == 64 |
13431 | || FP_SAVE_INLINE (info->first_fp_reg_save)); | |
f676971a | 13432 | use_backchain_to_restore_sp = (frame_pointer_needed |
9ebbca7d GK |
13433 | || current_function_calls_alloca |
13434 | || info->total_size > 32767); | |
13435 | using_mfcr_multiple = (rs6000_cpu == PROCESSOR_PPC601 | |
13436 | || rs6000_cpu == PROCESSOR_PPC603 | |
13437 | || rs6000_cpu == PROCESSOR_PPC750 | |
13438 | || optimize_size); | |
13439 | ||
f57fe068 | 13440 | if (WORLD_SAVE_P (info)) |
d62294f5 FJ |
13441 | { |
13442 | int i, j; | |
13443 | char rname[30]; | |
13444 | const char *alloc_rname; | |
13445 | rtvec p; | |
13446 | ||
13447 | /* eh_rest_world_r10 will return to the location saved in the LR | |
c4ad648e AM |
13448 | stack slot (which is not likely to be our caller.) |
13449 | Input: R10 -- stack adjustment. Clobbers R0, R11, R12, R7, R8. | |
13450 | rest_world is similar, except any R10 parameter is ignored. | |
13451 | The exception-handling stuff that was here in 2.95 is no | |
13452 | longer necessary. */ | |
d62294f5 FJ |
13453 | |
13454 | p = rtvec_alloc (9 | |
13455 | + 1 | |
f676971a | 13456 | + 32 - info->first_gp_reg_save |
c4ad648e AM |
13457 | + LAST_ALTIVEC_REGNO + 1 - info->first_altivec_reg_save |
13458 | + 63 + 1 - info->first_fp_reg_save); | |
d62294f5 | 13459 | |
c4ad648e AM |
13460 | strcpy (rname, ((current_function_calls_eh_return) ? |
13461 | "*eh_rest_world_r10" : "*rest_world")); | |
d62294f5 FJ |
13462 | alloc_rname = ggc_strdup (rname); |
13463 | ||
13464 | j = 0; | |
13465 | RTVEC_ELT (p, j++) = gen_rtx_RETURN (VOIDmode); | |
13466 | RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode, | |
c4ad648e AM |
13467 | gen_rtx_REG (Pmode, |
13468 | LINK_REGISTER_REGNUM)); | |
d62294f5 | 13469 | RTVEC_ELT (p, j++) |
c4ad648e | 13470 | = gen_rtx_USE (VOIDmode, gen_rtx_SYMBOL_REF (Pmode, alloc_rname)); |
d62294f5 | 13471 | /* The instruction pattern requires a clobber here; |
c4ad648e | 13472 | it is shared with the restVEC helper. */ |
d62294f5 | 13473 | RTVEC_ELT (p, j++) |
c4ad648e | 13474 | = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 11)); |
d62294f5 FJ |
13475 | |
13476 | { | |
c4ad648e AM |
13477 | /* CR register traditionally saved as CR2. */ |
13478 | rtx reg = gen_rtx_REG (reg_mode, CR2_REGNO); | |
13479 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
13480 | GEN_INT (info->cr_save_offset)); | |
13481 | rtx mem = gen_rtx_MEM (reg_mode, addr); | |
13482 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
13483 | ||
13484 | RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem); | |
d62294f5 FJ |
13485 | } |
13486 | ||
13487 | for (i = 0; i < 32 - info->first_gp_reg_save; i++) | |
c4ad648e AM |
13488 | { |
13489 | rtx reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i); | |
13490 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
13491 | GEN_INT (info->gp_save_offset | |
13492 | + reg_size * i)); | |
13493 | rtx mem = gen_rtx_MEM (reg_mode, addr); | |
13494 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
13495 | ||
13496 | RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem); | |
13497 | } | |
d62294f5 | 13498 | for (i = 0; info->first_altivec_reg_save + i <= LAST_ALTIVEC_REGNO; i++) |
c4ad648e AM |
13499 | { |
13500 | rtx reg = gen_rtx_REG (V4SImode, info->first_altivec_reg_save + i); | |
13501 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
13502 | GEN_INT (info->altivec_save_offset | |
13503 | + 16 * i)); | |
13504 | rtx mem = gen_rtx_MEM (V4SImode, addr); | |
13505 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
13506 | ||
13507 | RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem); | |
13508 | } | |
d62294f5 | 13509 | for (i = 0; info->first_fp_reg_save + i <= 63; i++) |
c4ad648e AM |
13510 | { |
13511 | rtx reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i); | |
13512 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
13513 | GEN_INT (info->fp_save_offset | |
13514 | + 8 * i)); | |
13515 | rtx mem = gen_rtx_MEM (DFmode, addr); | |
13516 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
13517 | ||
13518 | RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem); | |
13519 | } | |
d62294f5 | 13520 | RTVEC_ELT (p, j++) |
c4ad648e | 13521 | = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 0)); |
d62294f5 | 13522 | RTVEC_ELT (p, j++) |
c4ad648e | 13523 | = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 12)); |
d62294f5 | 13524 | RTVEC_ELT (p, j++) |
c4ad648e | 13525 | = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 7)); |
d62294f5 | 13526 | RTVEC_ELT (p, j++) |
c4ad648e | 13527 | = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 8)); |
d62294f5 | 13528 | RTVEC_ELT (p, j++) |
c4ad648e | 13529 | = gen_rtx_USE (VOIDmode, gen_rtx_REG (SImode, 10)); |
d62294f5 FJ |
13530 | emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p)); |
13531 | ||
13532 | return; | |
13533 | } | |
13534 | ||
9ebbca7d GK |
13535 | /* If we have a frame pointer, a call to alloca, or a large stack |
13536 | frame, restore the old stack pointer using the backchain. Otherwise, | |
13537 | we know what size to update it with. */ | |
13538 | if (use_backchain_to_restore_sp) | |
bacbde18 | 13539 | { |
9ebbca7d GK |
13540 | /* Under V.4, don't reset the stack pointer until after we're done |
13541 | loading the saved registers. */ | |
f607bc57 | 13542 | if (DEFAULT_ABI == ABI_V4) |
9ebbca7d | 13543 | frame_reg_rtx = gen_rtx_REG (Pmode, 11); |
4697a36c | 13544 | |
9ebbca7d GK |
13545 | emit_move_insn (frame_reg_rtx, |
13546 | gen_rtx_MEM (Pmode, sp_reg_rtx)); | |
f676971a | 13547 | |
bacbde18 | 13548 | } |
9ebbca7d | 13549 | else if (info->push_p) |
85638c0d | 13550 | { |
fc4767bb JJ |
13551 | if (DEFAULT_ABI == ABI_V4 |
13552 | || current_function_calls_eh_return) | |
9ebbca7d GK |
13553 | sp_offset = info->total_size; |
13554 | else | |
13555 | { | |
13556 | emit_insn (TARGET_32BIT | |
13557 | ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx, | |
13558 | GEN_INT (info->total_size)) | |
13559 | : gen_adddi3 (sp_reg_rtx, sp_reg_rtx, | |
13560 | GEN_INT (info->total_size))); | |
13561 | } | |
85638c0d | 13562 | } |
f676971a | 13563 | |
9aa86737 AH |
13564 | /* Restore AltiVec registers if needed. */ |
13565 | if (TARGET_ALTIVEC_ABI && info->altivec_size != 0) | |
13566 | { | |
13567 | int i; | |
13568 | ||
13569 | for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i) | |
13570 | if (info->vrsave_mask & ALTIVEC_REG_BIT (i)) | |
13571 | { | |
13572 | rtx addr, areg, mem; | |
13573 | ||
13574 | areg = gen_rtx_REG (Pmode, 0); | |
13575 | emit_move_insn | |
13576 | (areg, GEN_INT (info->altivec_save_offset | |
13577 | + sp_offset | |
13578 | + 16 * (i - info->first_altivec_reg_save))); | |
13579 | ||
13580 | /* AltiVec addressing mode is [reg+reg]. */ | |
13581 | addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, areg); | |
13582 | mem = gen_rtx_MEM (V4SImode, addr); | |
13583 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
13584 | ||
13585 | emit_move_insn (gen_rtx_REG (V4SImode, i), mem); | |
13586 | } | |
13587 | } | |
13588 | ||
13589 | /* Restore VRSAVE if needed. */ | |
44688022 | 13590 | if (TARGET_ALTIVEC && TARGET_ALTIVEC_VRSAVE |
4d774ff8 | 13591 | && info->vrsave_mask != 0) |
9aa86737 AH |
13592 | { |
13593 | rtx addr, mem, reg; | |
13594 | ||
13595 | addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
13596 | GEN_INT (info->vrsave_save_offset + sp_offset)); | |
13597 | mem = gen_rtx_MEM (SImode, addr); | |
13598 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
13599 | reg = gen_rtx_REG (SImode, 12); | |
13600 | emit_move_insn (reg, mem); | |
13601 | ||
13602 | emit_insn (generate_set_vrsave (reg, info, 1)); | |
13603 | } | |
13604 | ||
9ebbca7d GK |
13605 | /* Get the old lr if we saved it. */ |
13606 | if (info->lr_save_p) | |
b6c9286a | 13607 | { |
a3170dc6 AH |
13608 | rtx mem = gen_frame_mem_offset (Pmode, frame_reg_rtx, |
13609 | info->lr_save_offset + sp_offset); | |
ba4828e0 RK |
13610 | |
13611 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
b6c9286a | 13612 | |
9ebbca7d | 13613 | emit_move_insn (gen_rtx_REG (Pmode, 0), mem); |
b6c9286a | 13614 | } |
f676971a | 13615 | |
9ebbca7d GK |
13616 | /* Get the old cr if we saved it. */ |
13617 | if (info->cr_save_p) | |
13618 | { | |
13619 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
13620 | GEN_INT (info->cr_save_offset + sp_offset)); | |
13621 | rtx mem = gen_rtx_MEM (SImode, addr); | |
ba4828e0 RK |
13622 | |
13623 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
b6c9286a | 13624 | |
9ebbca7d GK |
13625 | emit_move_insn (gen_rtx_REG (SImode, 12), mem); |
13626 | } | |
f676971a | 13627 | |
9ebbca7d | 13628 | /* Set LR here to try to overlap restores below. */ |
4697a36c | 13629 | if (info->lr_save_p) |
9ebbca7d GK |
13630 | emit_move_insn (gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM), |
13631 | gen_rtx_REG (Pmode, 0)); | |
f676971a | 13632 | |
83720594 RH |
13633 | /* Load exception handler data registers, if needed. */ |
13634 | if (current_function_calls_eh_return) | |
13635 | { | |
78e1b90d DE |
13636 | unsigned int i, regno; |
13637 | ||
fc4767bb JJ |
13638 | if (TARGET_AIX) |
13639 | { | |
13640 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
13641 | GEN_INT (sp_offset + 5 * reg_size)); | |
13642 | rtx mem = gen_rtx_MEM (reg_mode, addr); | |
13643 | ||
13644 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
13645 | ||
13646 | emit_move_insn (gen_rtx_REG (reg_mode, 2), mem); | |
13647 | } | |
13648 | ||
83720594 RH |
13649 | for (i = 0; ; ++i) |
13650 | { | |
a3170dc6 | 13651 | rtx mem; |
83720594 RH |
13652 | |
13653 | regno = EH_RETURN_DATA_REGNO (i); | |
13654 | if (regno == INVALID_REGNUM) | |
13655 | break; | |
13656 | ||
a3170dc6 AH |
13657 | mem = gen_frame_mem_offset (reg_mode, frame_reg_rtx, |
13658 | info->ehrd_offset + sp_offset | |
13659 | + reg_size * (int) i); | |
ba4828e0 | 13660 | set_mem_alias_set (mem, rs6000_sr_alias_set); |
83720594 RH |
13661 | |
13662 | emit_move_insn (gen_rtx_REG (reg_mode, regno), mem); | |
13663 | } | |
13664 | } | |
f676971a | 13665 | |
9ebbca7d GK |
13666 | /* Restore GPRs. This is done as a PARALLEL if we are using |
13667 | the load-multiple instructions. */ | |
13668 | if (using_load_multiple) | |
979721f8 | 13669 | { |
9ebbca7d GK |
13670 | rtvec p; |
13671 | p = rtvec_alloc (32 - info->first_gp_reg_save); | |
13672 | for (i = 0; i < 32 - info->first_gp_reg_save; i++) | |
979721f8 | 13673 | { |
f676971a EC |
13674 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, |
13675 | GEN_INT (info->gp_save_offset | |
13676 | + sp_offset | |
9ebbca7d GK |
13677 | + reg_size * i)); |
13678 | rtx mem = gen_rtx_MEM (reg_mode, addr); | |
ba4828e0 RK |
13679 | |
13680 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
9ebbca7d | 13681 | |
f676971a | 13682 | RTVEC_ELT (p, i) = |
9ebbca7d GK |
13683 | gen_rtx_SET (VOIDmode, |
13684 | gen_rtx_REG (reg_mode, info->first_gp_reg_save + i), | |
13685 | mem); | |
979721f8 | 13686 | } |
9ebbca7d | 13687 | emit_insn (gen_rtx_PARALLEL (VOIDmode, p)); |
979721f8 | 13688 | } |
9ebbca7d GK |
13689 | else |
13690 | for (i = 0; i < 32 - info->first_gp_reg_save; i++) | |
f676971a | 13691 | if ((regs_ever_live[info->first_gp_reg_save+i] |
b4db40bf JJ |
13692 | && (! call_used_regs[info->first_gp_reg_save+i] |
13693 | || (i+info->first_gp_reg_save == RS6000_PIC_OFFSET_TABLE_REGNUM | |
13694 | && TARGET_TOC && TARGET_MINIMAL_TOC))) | |
1db02437 | 13695 | || (i+info->first_gp_reg_save == RS6000_PIC_OFFSET_TABLE_REGNUM |
14f00213 | 13696 | && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0) |
f607bc57 | 13697 | || (DEFAULT_ABI == ABI_DARWIN && flag_pic)))) |
9ebbca7d | 13698 | { |
f676971a EC |
13699 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, |
13700 | GEN_INT (info->gp_save_offset | |
13701 | + sp_offset | |
9ebbca7d GK |
13702 | + reg_size * i)); |
13703 | rtx mem = gen_rtx_MEM (reg_mode, addr); | |
ba4828e0 | 13704 | |
a3170dc6 | 13705 | /* Restore 64-bit quantities for SPE. */ |
c19de7aa | 13706 | if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0) |
a3170dc6 AH |
13707 | { |
13708 | int offset = info->spe_gp_save_offset + sp_offset + 8 * i; | |
13709 | rtx b; | |
13710 | ||
13711 | if (!SPE_CONST_OFFSET_OK (offset)) | |
13712 | { | |
13713 | b = gen_rtx_REG (Pmode, FIXED_SCRATCH); | |
13714 | emit_move_insn (b, GEN_INT (offset)); | |
13715 | } | |
13716 | else | |
13717 | b = GEN_INT (offset); | |
13718 | ||
13719 | addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, b); | |
13720 | mem = gen_rtx_MEM (V2SImode, addr); | |
13721 | } | |
13722 | ||
ba4828e0 | 13723 | set_mem_alias_set (mem, rs6000_sr_alias_set); |
9ebbca7d | 13724 | |
f676971a | 13725 | emit_move_insn (gen_rtx_REG (reg_mode, |
a3170dc6 | 13726 | info->first_gp_reg_save + i), mem); |
9ebbca7d | 13727 | } |
9878760c | 13728 | |
9ebbca7d GK |
13729 | /* Restore fpr's if we need to do it without calling a function. */ |
13730 | if (restoring_FPRs_inline) | |
13731 | for (i = 0; i < 64 - info->first_fp_reg_save; i++) | |
f676971a | 13732 | if ((regs_ever_live[info->first_fp_reg_save+i] |
9ebbca7d GK |
13733 | && ! call_used_regs[info->first_fp_reg_save+i])) |
13734 | { | |
13735 | rtx addr, mem; | |
13736 | addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
f676971a EC |
13737 | GEN_INT (info->fp_save_offset |
13738 | + sp_offset | |
a4f6c312 | 13739 | + 8 * i)); |
9ebbca7d | 13740 | mem = gen_rtx_MEM (DFmode, addr); |
ba4828e0 | 13741 | set_mem_alias_set (mem, rs6000_sr_alias_set); |
9ebbca7d | 13742 | |
f676971a | 13743 | emit_move_insn (gen_rtx_REG (DFmode, |
9ebbca7d GK |
13744 | info->first_fp_reg_save + i), |
13745 | mem); | |
13746 | } | |
8d30c4ee | 13747 | |
9ebbca7d GK |
13748 | /* If we saved cr, restore it here. Just those that were used. */ |
13749 | if (info->cr_save_p) | |
979721f8 | 13750 | { |
9ebbca7d | 13751 | rtx r12_rtx = gen_rtx_REG (SImode, 12); |
e35b9579 | 13752 | int count = 0; |
f676971a | 13753 | |
9ebbca7d | 13754 | if (using_mfcr_multiple) |
979721f8 | 13755 | { |
9ebbca7d GK |
13756 | for (i = 0; i < 8; i++) |
13757 | if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i]) | |
e35b9579 | 13758 | count++; |
37409796 | 13759 | gcc_assert (count); |
e35b9579 GK |
13760 | } |
13761 | ||
13762 | if (using_mfcr_multiple && count > 1) | |
13763 | { | |
13764 | rtvec p; | |
13765 | int ndx; | |
f676971a | 13766 | |
e35b9579 | 13767 | p = rtvec_alloc (count); |
9ebbca7d | 13768 | |
e35b9579 | 13769 | ndx = 0; |
9ebbca7d GK |
13770 | for (i = 0; i < 8; i++) |
13771 | if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i]) | |
13772 | { | |
13773 | rtvec r = rtvec_alloc (2); | |
13774 | RTVEC_ELT (r, 0) = r12_rtx; | |
13775 | RTVEC_ELT (r, 1) = GEN_INT (1 << (7-i)); | |
e35b9579 | 13776 | RTVEC_ELT (p, ndx) = |
f676971a | 13777 | gen_rtx_SET (VOIDmode, gen_rtx_REG (CCmode, CR0_REGNO+i), |
615158e2 | 13778 | gen_rtx_UNSPEC (CCmode, r, UNSPEC_MOVESI_TO_CR)); |
e35b9579 | 13779 | ndx++; |
9ebbca7d GK |
13780 | } |
13781 | emit_insn (gen_rtx_PARALLEL (VOIDmode, p)); | |
37409796 | 13782 | gcc_assert (ndx == count); |
979721f8 MM |
13783 | } |
13784 | else | |
9ebbca7d GK |
13785 | for (i = 0; i < 8; i++) |
13786 | if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i]) | |
979721f8 | 13787 | { |
f676971a | 13788 | emit_insn (gen_movsi_to_cr_one (gen_rtx_REG (CCmode, |
9ebbca7d GK |
13789 | CR0_REGNO+i), |
13790 | r12_rtx)); | |
979721f8 | 13791 | } |
979721f8 MM |
13792 | } |
13793 | ||
9ebbca7d GK |
13794 | /* If this is V.4, unwind the stack pointer after all of the loads |
13795 | have been done. We need to emit a block here so that sched | |
13796 | doesn't decide to move the sp change before the register restores | |
13797 | (which may not have any obvious dependency on the stack). This | |
13798 | doesn't hurt performance, because there is no scheduling that can | |
13799 | be done after this point. */ | |
fc4767bb JJ |
13800 | if (DEFAULT_ABI == ABI_V4 |
13801 | || current_function_calls_eh_return) | |
b6c9286a | 13802 | { |
9ebbca7d | 13803 | if (frame_reg_rtx != sp_reg_rtx) |
c4ad648e | 13804 | rs6000_emit_stack_tie (); |
b6c9286a | 13805 | |
9ebbca7d | 13806 | if (use_backchain_to_restore_sp) |
b6c9286a | 13807 | { |
9ebbca7d | 13808 | emit_move_insn (sp_reg_rtx, frame_reg_rtx); |
b6c9286a | 13809 | } |
9ebbca7d | 13810 | else if (sp_offset != 0) |
13f1623b | 13811 | { |
5b71a4e7 | 13812 | emit_insn (TARGET_32BIT |
9ebbca7d GK |
13813 | ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx, |
13814 | GEN_INT (sp_offset)) | |
13815 | : gen_adddi3 (sp_reg_rtx, sp_reg_rtx, | |
13816 | GEN_INT (sp_offset))); | |
13f1623b | 13817 | } |
9ebbca7d | 13818 | } |
b6c9286a | 13819 | |
83720594 RH |
13820 | if (current_function_calls_eh_return) |
13821 | { | |
13822 | rtx sa = EH_RETURN_STACKADJ_RTX; | |
5b71a4e7 | 13823 | emit_insn (TARGET_32BIT |
83720594 RH |
13824 | ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx, sa) |
13825 | : gen_adddi3 (sp_reg_rtx, sp_reg_rtx, sa)); | |
13826 | } | |
13827 | ||
9ebbca7d GK |
13828 | if (!sibcall) |
13829 | { | |
13830 | rtvec p; | |
13831 | if (! restoring_FPRs_inline) | |
13832 | p = rtvec_alloc (3 + 64 - info->first_fp_reg_save); | |
13833 | else | |
13834 | p = rtvec_alloc (2); | |
b6c9286a | 13835 | |
e35b9579 | 13836 | RTVEC_ELT (p, 0) = gen_rtx_RETURN (VOIDmode); |
f676971a EC |
13837 | RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode, |
13838 | gen_rtx_REG (Pmode, | |
9ebbca7d | 13839 | LINK_REGISTER_REGNUM)); |
9ebbca7d GK |
13840 | |
13841 | /* If we have to restore more than two FP registers, branch to the | |
13842 | restore function. It will return to our caller. */ | |
13843 | if (! restoring_FPRs_inline) | |
13844 | { | |
13845 | int i; | |
13846 | char rname[30]; | |
520a57c8 | 13847 | const char *alloc_rname; |
979721f8 | 13848 | |
f676971a | 13849 | sprintf (rname, "%s%d%s", RESTORE_FP_PREFIX, |
9ebbca7d | 13850 | info->first_fp_reg_save - 32, RESTORE_FP_SUFFIX); |
a8a05998 | 13851 | alloc_rname = ggc_strdup (rname); |
9ebbca7d GK |
13852 | RTVEC_ELT (p, 2) = gen_rtx_USE (VOIDmode, |
13853 | gen_rtx_SYMBOL_REF (Pmode, | |
13854 | alloc_rname)); | |
b6c9286a | 13855 | |
9ebbca7d GK |
13856 | for (i = 0; i < 64 - info->first_fp_reg_save; i++) |
13857 | { | |
13858 | rtx addr, mem; | |
13859 | addr = gen_rtx_PLUS (Pmode, sp_reg_rtx, | |
13860 | GEN_INT (info->fp_save_offset + 8*i)); | |
13861 | mem = gen_rtx_MEM (DFmode, addr); | |
ba4828e0 | 13862 | set_mem_alias_set (mem, rs6000_sr_alias_set); |
9ebbca7d | 13863 | |
f676971a | 13864 | RTVEC_ELT (p, i+3) = |
9ebbca7d GK |
13865 | gen_rtx_SET (VOIDmode, |
13866 | gen_rtx_REG (DFmode, info->first_fp_reg_save + i), | |
13867 | mem); | |
b6c9286a MM |
13868 | } |
13869 | } | |
f676971a | 13870 | |
9ebbca7d | 13871 | emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p)); |
3daf36a4 | 13872 | } |
9878760c RK |
13873 | } |
13874 | ||
13875 | /* Write function epilogue. */ | |
13876 | ||
08c148a8 | 13877 | static void |
f676971a | 13878 | rs6000_output_function_epilogue (FILE *file, |
a2369ed3 | 13879 | HOST_WIDE_INT size ATTRIBUTE_UNUSED) |
9878760c | 13880 | { |
4697a36c | 13881 | rs6000_stack_t *info = rs6000_stack_info (); |
9878760c | 13882 | |
9ebbca7d | 13883 | if (! HAVE_epilogue) |
9878760c | 13884 | { |
9ebbca7d GK |
13885 | rtx insn = get_last_insn (); |
13886 | /* If the last insn was a BARRIER, we don't have to write anything except | |
13887 | the trace table. */ | |
13888 | if (GET_CODE (insn) == NOTE) | |
13889 | insn = prev_nonnote_insn (insn); | |
13890 | if (insn == 0 || GET_CODE (insn) != BARRIER) | |
4697a36c | 13891 | { |
9ebbca7d GK |
13892 | /* This is slightly ugly, but at least we don't have two |
13893 | copies of the epilogue-emitting code. */ | |
13894 | start_sequence (); | |
13895 | ||
13896 | /* A NOTE_INSN_DELETED is supposed to be at the start | |
13897 | and end of the "toplevel" insn chain. */ | |
2e040219 | 13898 | emit_note (NOTE_INSN_DELETED); |
9ebbca7d | 13899 | rs6000_emit_epilogue (FALSE); |
2e040219 | 13900 | emit_note (NOTE_INSN_DELETED); |
9ebbca7d | 13901 | |
a3c9585f | 13902 | /* Expand INSN_ADDRESSES so final() doesn't crash. */ |
178c3eff DJ |
13903 | { |
13904 | rtx insn; | |
13905 | unsigned addr = 0; | |
13906 | for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn)) | |
13907 | { | |
13908 | INSN_ADDRESSES_NEW (insn, addr); | |
13909 | addr += 4; | |
13910 | } | |
13911 | } | |
13912 | ||
9ebbca7d | 13913 | if (TARGET_DEBUG_STACK) |
a4f6c312 | 13914 | debug_rtx_list (get_insns (), 100); |
c9d691e9 | 13915 | final (get_insns (), file, FALSE); |
9ebbca7d | 13916 | end_sequence (); |
4697a36c | 13917 | } |
9878760c | 13918 | } |
b4ac57ab | 13919 | |
efdba735 SH |
13920 | #if TARGET_MACHO |
13921 | macho_branch_islands (); | |
0e5da0be GK |
13922 | /* Mach-O doesn't support labels at the end of objects, so if |
13923 | it looks like we might want one, insert a NOP. */ | |
13924 | { | |
13925 | rtx insn = get_last_insn (); | |
13926 | while (insn | |
13927 | && NOTE_P (insn) | |
13928 | && NOTE_LINE_NUMBER (insn) != NOTE_INSN_DELETED_LABEL) | |
13929 | insn = PREV_INSN (insn); | |
f676971a EC |
13930 | if (insn |
13931 | && (LABEL_P (insn) | |
0e5da0be GK |
13932 | || (NOTE_P (insn) |
13933 | && NOTE_LINE_NUMBER (insn) == NOTE_INSN_DELETED_LABEL))) | |
13934 | fputs ("\tnop\n", file); | |
13935 | } | |
13936 | #endif | |
13937 | ||
9b30bae2 | 13938 | /* Output a traceback table here. See /usr/include/sys/debug.h for info |
314fc5a9 ILT |
13939 | on its format. |
13940 | ||
13941 | We don't output a traceback table if -finhibit-size-directive was | |
13942 | used. The documentation for -finhibit-size-directive reads | |
13943 | ``don't output a @code{.size} assembler directive, or anything | |
13944 | else that would cause trouble if the function is split in the | |
13945 | middle, and the two halves are placed at locations far apart in | |
13946 | memory.'' The traceback table has this property, since it | |
13947 | includes the offset from the start of the function to the | |
4d30c363 MM |
13948 | traceback table itself. |
13949 | ||
13950 | System V.4 Powerpc's (and the embedded ABI derived from it) use a | |
b6c9286a | 13951 | different traceback table. */ |
57ac7be9 AM |
13952 | if (DEFAULT_ABI == ABI_AIX && ! flag_inhibit_size_directive |
13953 | && rs6000_traceback != traceback_none) | |
9b30bae2 | 13954 | { |
69c75916 | 13955 | const char *fname = NULL; |
3ac88239 | 13956 | const char *language_string = lang_hooks.name; |
6041bf2f | 13957 | int fixed_parms = 0, float_parms = 0, parm_info = 0; |
314fc5a9 | 13958 | int i; |
57ac7be9 AM |
13959 | int optional_tbtab; |
13960 | ||
13961 | if (rs6000_traceback == traceback_full) | |
13962 | optional_tbtab = 1; | |
13963 | else if (rs6000_traceback == traceback_part) | |
13964 | optional_tbtab = 0; | |
13965 | else | |
13966 | optional_tbtab = !optimize_size && !TARGET_ELF; | |
314fc5a9 | 13967 | |
69c75916 AM |
13968 | if (optional_tbtab) |
13969 | { | |
13970 | fname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0); | |
13971 | while (*fname == '.') /* V.4 encodes . in the name */ | |
13972 | fname++; | |
13973 | ||
13974 | /* Need label immediately before tbtab, so we can compute | |
13975 | its offset from the function start. */ | |
13976 | ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT"); | |
13977 | ASM_OUTPUT_LABEL (file, fname); | |
13978 | } | |
314fc5a9 ILT |
13979 | |
13980 | /* The .tbtab pseudo-op can only be used for the first eight | |
13981 | expressions, since it can't handle the possibly variable | |
13982 | length fields that follow. However, if you omit the optional | |
13983 | fields, the assembler outputs zeros for all optional fields | |
13984 | anyways, giving each variable length field is minimum length | |
13985 | (as defined in sys/debug.h). Thus we can not use the .tbtab | |
13986 | pseudo-op at all. */ | |
13987 | ||
13988 | /* An all-zero word flags the start of the tbtab, for debuggers | |
13989 | that have to find it by searching forward from the entry | |
13990 | point or from the current pc. */ | |
19d2d16f | 13991 | fputs ("\t.long 0\n", file); |
314fc5a9 ILT |
13992 | |
13993 | /* Tbtab format type. Use format type 0. */ | |
19d2d16f | 13994 | fputs ("\t.byte 0,", file); |
314fc5a9 | 13995 | |
5fc921c1 DE |
13996 | /* Language type. Unfortunately, there does not seem to be any |
13997 | official way to discover the language being compiled, so we | |
13998 | use language_string. | |
13999 | C is 0. Fortran is 1. Pascal is 2. Ada is 3. C++ is 9. | |
14000 | Java is 13. Objective-C is 14. */ | |
14001 | if (! strcmp (language_string, "GNU C")) | |
314fc5a9 | 14002 | i = 0; |
6de9cd9a DN |
14003 | else if (! strcmp (language_string, "GNU F77") |
14004 | || ! strcmp (language_string, "GNU F95")) | |
314fc5a9 | 14005 | i = 1; |
8b83775b | 14006 | else if (! strcmp (language_string, "GNU Pascal")) |
314fc5a9 | 14007 | i = 2; |
5fc921c1 DE |
14008 | else if (! strcmp (language_string, "GNU Ada")) |
14009 | i = 3; | |
314fc5a9 ILT |
14010 | else if (! strcmp (language_string, "GNU C++")) |
14011 | i = 9; | |
9517ead8 AG |
14012 | else if (! strcmp (language_string, "GNU Java")) |
14013 | i = 13; | |
5fc921c1 DE |
14014 | else if (! strcmp (language_string, "GNU Objective-C")) |
14015 | i = 14; | |
314fc5a9 | 14016 | else |
37409796 | 14017 | gcc_unreachable (); |
314fc5a9 ILT |
14018 | fprintf (file, "%d,", i); |
14019 | ||
14020 | /* 8 single bit fields: global linkage (not set for C extern linkage, | |
14021 | apparently a PL/I convention?), out-of-line epilogue/prologue, offset | |
14022 | from start of procedure stored in tbtab, internal function, function | |
14023 | has controlled storage, function has no toc, function uses fp, | |
14024 | function logs/aborts fp operations. */ | |
14025 | /* Assume that fp operations are used if any fp reg must be saved. */ | |
6041bf2f DE |
14026 | fprintf (file, "%d,", |
14027 | (optional_tbtab << 5) | ((info->first_fp_reg_save != 64) << 1)); | |
314fc5a9 ILT |
14028 | |
14029 | /* 6 bitfields: function is interrupt handler, name present in | |
14030 | proc table, function calls alloca, on condition directives | |
14031 | (controls stack walks, 3 bits), saves condition reg, saves | |
14032 | link reg. */ | |
14033 | /* The `function calls alloca' bit seems to be set whenever reg 31 is | |
14034 | set up as a frame pointer, even when there is no alloca call. */ | |
14035 | fprintf (file, "%d,", | |
6041bf2f DE |
14036 | ((optional_tbtab << 6) |
14037 | | ((optional_tbtab & frame_pointer_needed) << 5) | |
14038 | | (info->cr_save_p << 1) | |
14039 | | (info->lr_save_p))); | |
314fc5a9 | 14040 | |
6041bf2f | 14041 | /* 3 bitfields: saves backchain, fixup code, number of fpr saved |
314fc5a9 ILT |
14042 | (6 bits). */ |
14043 | fprintf (file, "%d,", | |
4697a36c | 14044 | (info->push_p << 7) | (64 - info->first_fp_reg_save)); |
314fc5a9 ILT |
14045 | |
14046 | /* 2 bitfields: spare bits (2 bits), number of gpr saved (6 bits). */ | |
14047 | fprintf (file, "%d,", (32 - first_reg_to_save ())); | |
14048 | ||
6041bf2f DE |
14049 | if (optional_tbtab) |
14050 | { | |
14051 | /* Compute the parameter info from the function decl argument | |
14052 | list. */ | |
14053 | tree decl; | |
14054 | int next_parm_info_bit = 31; | |
314fc5a9 | 14055 | |
6041bf2f DE |
14056 | for (decl = DECL_ARGUMENTS (current_function_decl); |
14057 | decl; decl = TREE_CHAIN (decl)) | |
14058 | { | |
14059 | rtx parameter = DECL_INCOMING_RTL (decl); | |
14060 | enum machine_mode mode = GET_MODE (parameter); | |
314fc5a9 | 14061 | |
6041bf2f DE |
14062 | if (GET_CODE (parameter) == REG) |
14063 | { | |
14064 | if (GET_MODE_CLASS (mode) == MODE_FLOAT) | |
14065 | { | |
14066 | int bits; | |
14067 | ||
14068 | float_parms++; | |
14069 | ||
37409796 NS |
14070 | switch (mode) |
14071 | { | |
14072 | case SFmode: | |
14073 | bits = 0x2; | |
14074 | break; | |
14075 | ||
14076 | case DFmode: | |
14077 | case TFmode: | |
14078 | bits = 0x3; | |
14079 | break; | |
14080 | ||
14081 | default: | |
14082 | gcc_unreachable (); | |
14083 | } | |
6041bf2f DE |
14084 | |
14085 | /* If only one bit will fit, don't or in this entry. */ | |
14086 | if (next_parm_info_bit > 0) | |
14087 | parm_info |= (bits << (next_parm_info_bit - 1)); | |
14088 | next_parm_info_bit -= 2; | |
14089 | } | |
14090 | else | |
14091 | { | |
14092 | fixed_parms += ((GET_MODE_SIZE (mode) | |
14093 | + (UNITS_PER_WORD - 1)) | |
14094 | / UNITS_PER_WORD); | |
14095 | next_parm_info_bit -= 1; | |
14096 | } | |
14097 | } | |
14098 | } | |
14099 | } | |
314fc5a9 ILT |
14100 | |
14101 | /* Number of fixed point parameters. */ | |
14102 | /* This is actually the number of words of fixed point parameters; thus | |
14103 | an 8 byte struct counts as 2; and thus the maximum value is 8. */ | |
14104 | fprintf (file, "%d,", fixed_parms); | |
14105 | ||
14106 | /* 2 bitfields: number of floating point parameters (7 bits), parameters | |
14107 | all on stack. */ | |
14108 | /* This is actually the number of fp registers that hold parameters; | |
14109 | and thus the maximum value is 13. */ | |
14110 | /* Set parameters on stack bit if parameters are not in their original | |
14111 | registers, regardless of whether they are on the stack? Xlc | |
14112 | seems to set the bit when not optimizing. */ | |
14113 | fprintf (file, "%d\n", ((float_parms << 1) | (! optimize))); | |
14114 | ||
6041bf2f DE |
14115 | if (! optional_tbtab) |
14116 | return; | |
14117 | ||
314fc5a9 ILT |
14118 | /* Optional fields follow. Some are variable length. */ |
14119 | ||
14120 | /* Parameter types, left adjusted bit fields: 0 fixed, 10 single float, | |
14121 | 11 double float. */ | |
14122 | /* There is an entry for each parameter in a register, in the order that | |
14123 | they occur in the parameter list. Any intervening arguments on the | |
14124 | stack are ignored. If the list overflows a long (max possible length | |
14125 | 34 bits) then completely leave off all elements that don't fit. */ | |
14126 | /* Only emit this long if there was at least one parameter. */ | |
14127 | if (fixed_parms || float_parms) | |
14128 | fprintf (file, "\t.long %d\n", parm_info); | |
14129 | ||
14130 | /* Offset from start of code to tb table. */ | |
19d2d16f | 14131 | fputs ("\t.long ", file); |
314fc5a9 | 14132 | ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT"); |
85b776df AM |
14133 | if (TARGET_AIX) |
14134 | RS6000_OUTPUT_BASENAME (file, fname); | |
14135 | else | |
14136 | assemble_name (file, fname); | |
14137 | putc ('-', file); | |
14138 | rs6000_output_function_entry (file, fname); | |
19d2d16f | 14139 | putc ('\n', file); |
314fc5a9 ILT |
14140 | |
14141 | /* Interrupt handler mask. */ | |
14142 | /* Omit this long, since we never set the interrupt handler bit | |
14143 | above. */ | |
14144 | ||
14145 | /* Number of CTL (controlled storage) anchors. */ | |
14146 | /* Omit this long, since the has_ctl bit is never set above. */ | |
14147 | ||
14148 | /* Displacement into stack of each CTL anchor. */ | |
14149 | /* Omit this list of longs, because there are no CTL anchors. */ | |
14150 | ||
14151 | /* Length of function name. */ | |
69c75916 AM |
14152 | if (*fname == '*') |
14153 | ++fname; | |
296b8152 | 14154 | fprintf (file, "\t.short %d\n", (int) strlen (fname)); |
314fc5a9 ILT |
14155 | |
14156 | /* Function name. */ | |
14157 | assemble_string (fname, strlen (fname)); | |
14158 | ||
14159 | /* Register for alloca automatic storage; this is always reg 31. | |
14160 | Only emit this if the alloca bit was set above. */ | |
14161 | if (frame_pointer_needed) | |
19d2d16f | 14162 | fputs ("\t.byte 31\n", file); |
b1765bde DE |
14163 | |
14164 | fputs ("\t.align 2\n", file); | |
9b30bae2 | 14165 | } |
9878760c | 14166 | } |
17167fd8 | 14167 | \f |
a4f6c312 SS |
14168 | /* A C compound statement that outputs the assembler code for a thunk |
14169 | function, used to implement C++ virtual function calls with | |
14170 | multiple inheritance. The thunk acts as a wrapper around a virtual | |
14171 | function, adjusting the implicit object parameter before handing | |
14172 | control off to the real function. | |
14173 | ||
14174 | First, emit code to add the integer DELTA to the location that | |
14175 | contains the incoming first argument. Assume that this argument | |
14176 | contains a pointer, and is the one used to pass the `this' pointer | |
14177 | in C++. This is the incoming argument *before* the function | |
14178 | prologue, e.g. `%o0' on a sparc. The addition must preserve the | |
14179 | values of all other incoming arguments. | |
17167fd8 MM |
14180 | |
14181 | After the addition, emit code to jump to FUNCTION, which is a | |
a4f6c312 SS |
14182 | `FUNCTION_DECL'. This is a direct pure jump, not a call, and does |
14183 | not touch the return address. Hence returning from FUNCTION will | |
14184 | return to whoever called the current `thunk'. | |
17167fd8 | 14185 | |
a4f6c312 SS |
14186 | The effect must be as if FUNCTION had been called directly with the |
14187 | adjusted first argument. This macro is responsible for emitting | |
14188 | all of the code for a thunk function; output_function_prologue() | |
14189 | and output_function_epilogue() are not invoked. | |
17167fd8 | 14190 | |
a4f6c312 SS |
14191 | The THUNK_FNDECL is redundant. (DELTA and FUNCTION have already |
14192 | been extracted from it.) It might possibly be useful on some | |
14193 | targets, but probably not. | |
17167fd8 | 14194 | |
a4f6c312 SS |
14195 | If you do not define this macro, the target-independent code in the |
14196 | C++ frontend will generate a less efficient heavyweight thunk that | |
14197 | calls FUNCTION instead of jumping to it. The generic approach does | |
14198 | not support varargs. */ | |
17167fd8 | 14199 | |
3961e8fe | 14200 | static void |
f676971a EC |
14201 | rs6000_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED, |
14202 | HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset, | |
a2369ed3 | 14203 | tree function) |
17167fd8 | 14204 | { |
5b71a4e7 | 14205 | rtx this, insn, funexp; |
17167fd8 | 14206 | |
5b71a4e7 | 14207 | reload_completed = 1; |
fe3ad572 | 14208 | epilogue_completed = 1; |
5b71a4e7 | 14209 | no_new_pseudos = 1; |
6429e3be | 14210 | reset_block_changes (); |
56a7189a | 14211 | |
5b71a4e7 | 14212 | /* Mark the end of the (empty) prologue. */ |
2e040219 | 14213 | emit_note (NOTE_INSN_PROLOGUE_END); |
17167fd8 | 14214 | |
5b71a4e7 DE |
14215 | /* Find the "this" pointer. If the function returns a structure, |
14216 | the structure return pointer is in r3. */ | |
61f71b34 | 14217 | if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function)) |
5b71a4e7 | 14218 | this = gen_rtx_REG (Pmode, 4); |
56a7189a | 14219 | else |
5b71a4e7 | 14220 | this = gen_rtx_REG (Pmode, 3); |
17167fd8 | 14221 | |
5b71a4e7 DE |
14222 | /* Apply the constant offset, if required. */ |
14223 | if (delta) | |
14224 | { | |
14225 | rtx delta_rtx = GEN_INT (delta); | |
14226 | emit_insn (TARGET_32BIT | |
14227 | ? gen_addsi3 (this, this, delta_rtx) | |
14228 | : gen_adddi3 (this, this, delta_rtx)); | |
17167fd8 MM |
14229 | } |
14230 | ||
5b71a4e7 DE |
14231 | /* Apply the offset from the vtable, if required. */ |
14232 | if (vcall_offset) | |
17167fd8 | 14233 | { |
5b71a4e7 DE |
14234 | rtx vcall_offset_rtx = GEN_INT (vcall_offset); |
14235 | rtx tmp = gen_rtx_REG (Pmode, 12); | |
17167fd8 | 14236 | |
5b71a4e7 | 14237 | emit_move_insn (tmp, gen_rtx_MEM (Pmode, this)); |
eeff9307 JJ |
14238 | if (((unsigned HOST_WIDE_INT) vcall_offset) + 0x8000 >= 0x10000) |
14239 | { | |
14240 | emit_insn (TARGET_32BIT | |
14241 | ? gen_addsi3 (tmp, tmp, vcall_offset_rtx) | |
14242 | : gen_adddi3 (tmp, tmp, vcall_offset_rtx)); | |
14243 | emit_move_insn (tmp, gen_rtx_MEM (Pmode, tmp)); | |
14244 | } | |
14245 | else | |
14246 | { | |
14247 | rtx loc = gen_rtx_PLUS (Pmode, tmp, vcall_offset_rtx); | |
14248 | ||
14249 | emit_move_insn (tmp, gen_rtx_MEM (Pmode, loc)); | |
14250 | } | |
5b71a4e7 DE |
14251 | emit_insn (TARGET_32BIT |
14252 | ? gen_addsi3 (this, this, tmp) | |
14253 | : gen_adddi3 (this, this, tmp)); | |
17167fd8 MM |
14254 | } |
14255 | ||
5b71a4e7 DE |
14256 | /* Generate a tail call to the target function. */ |
14257 | if (!TREE_USED (function)) | |
14258 | { | |
14259 | assemble_external (function); | |
14260 | TREE_USED (function) = 1; | |
14261 | } | |
14262 | funexp = XEXP (DECL_RTL (function), 0); | |
5b71a4e7 | 14263 | funexp = gen_rtx_MEM (FUNCTION_MODE, funexp); |
ee890fe2 SS |
14264 | |
14265 | #if TARGET_MACHO | |
ab82a49f | 14266 | if (MACHOPIC_INDIRECT) |
5b71a4e7 | 14267 | funexp = machopic_indirect_call_target (funexp); |
ee890fe2 | 14268 | #endif |
5b71a4e7 DE |
14269 | |
14270 | /* gen_sibcall expects reload to convert scratch pseudo to LR so we must | |
14271 | generate sibcall RTL explicitly to avoid constraint abort. */ | |
14272 | insn = emit_call_insn ( | |
14273 | gen_rtx_PARALLEL (VOIDmode, | |
14274 | gen_rtvec (4, | |
14275 | gen_rtx_CALL (VOIDmode, | |
14276 | funexp, const0_rtx), | |
14277 | gen_rtx_USE (VOIDmode, const0_rtx), | |
14278 | gen_rtx_USE (VOIDmode, | |
14279 | gen_rtx_REG (SImode, | |
14280 | LINK_REGISTER_REGNUM)), | |
14281 | gen_rtx_RETURN (VOIDmode)))); | |
14282 | SIBLING_CALL_P (insn) = 1; | |
14283 | emit_barrier (); | |
14284 | ||
14285 | /* Run just enough of rest_of_compilation to get the insns emitted. | |
14286 | There's not really enough bulk here to make other passes such as | |
14287 | instruction scheduling worth while. Note that use_thunk calls | |
14288 | assemble_start_function and assemble_end_function. */ | |
14289 | insn = get_insns (); | |
a2855205 | 14290 | insn_locators_initialize (); |
5b71a4e7 DE |
14291 | shorten_branches (insn); |
14292 | final_start_function (insn, file, 1); | |
c9d691e9 | 14293 | final (insn, file, 1); |
5b71a4e7 DE |
14294 | final_end_function (); |
14295 | ||
14296 | reload_completed = 0; | |
fe3ad572 | 14297 | epilogue_completed = 0; |
5b71a4e7 | 14298 | no_new_pseudos = 0; |
9ebbca7d | 14299 | } |
9ebbca7d GK |
14300 | \f |
14301 | /* A quick summary of the various types of 'constant-pool tables' | |
14302 | under PowerPC: | |
14303 | ||
f676971a | 14304 | Target Flags Name One table per |
9ebbca7d GK |
14305 | AIX (none) AIX TOC object file |
14306 | AIX -mfull-toc AIX TOC object file | |
14307 | AIX -mminimal-toc AIX minimal TOC translation unit | |
14308 | SVR4/EABI (none) SVR4 SDATA object file | |
14309 | SVR4/EABI -fpic SVR4 pic object file | |
14310 | SVR4/EABI -fPIC SVR4 PIC translation unit | |
14311 | SVR4/EABI -mrelocatable EABI TOC function | |
14312 | SVR4/EABI -maix AIX TOC object file | |
f676971a | 14313 | SVR4/EABI -maix -mminimal-toc |
9ebbca7d GK |
14314 | AIX minimal TOC translation unit |
14315 | ||
14316 | Name Reg. Set by entries contains: | |
14317 | made by addrs? fp? sum? | |
14318 | ||
14319 | AIX TOC 2 crt0 as Y option option | |
14320 | AIX minimal TOC 30 prolog gcc Y Y option | |
14321 | SVR4 SDATA 13 crt0 gcc N Y N | |
14322 | SVR4 pic 30 prolog ld Y not yet N | |
14323 | SVR4 PIC 30 prolog gcc Y option option | |
14324 | EABI TOC 30 prolog gcc Y option option | |
14325 | ||
14326 | */ | |
14327 | ||
9ebbca7d GK |
14328 | /* Hash functions for the hash table. */ |
14329 | ||
14330 | static unsigned | |
a2369ed3 | 14331 | rs6000_hash_constant (rtx k) |
9ebbca7d | 14332 | { |
46b33600 RH |
14333 | enum rtx_code code = GET_CODE (k); |
14334 | enum machine_mode mode = GET_MODE (k); | |
14335 | unsigned result = (code << 3) ^ mode; | |
14336 | const char *format; | |
14337 | int flen, fidx; | |
f676971a | 14338 | |
46b33600 RH |
14339 | format = GET_RTX_FORMAT (code); |
14340 | flen = strlen (format); | |
14341 | fidx = 0; | |
9ebbca7d | 14342 | |
46b33600 RH |
14343 | switch (code) |
14344 | { | |
14345 | case LABEL_REF: | |
14346 | return result * 1231 + (unsigned) INSN_UID (XEXP (k, 0)); | |
14347 | ||
14348 | case CONST_DOUBLE: | |
14349 | if (mode != VOIDmode) | |
14350 | return real_hash (CONST_DOUBLE_REAL_VALUE (k)) * result; | |
14351 | flen = 2; | |
14352 | break; | |
14353 | ||
14354 | case CODE_LABEL: | |
14355 | fidx = 3; | |
14356 | break; | |
14357 | ||
14358 | default: | |
14359 | break; | |
14360 | } | |
9ebbca7d GK |
14361 | |
14362 | for (; fidx < flen; fidx++) | |
14363 | switch (format[fidx]) | |
14364 | { | |
14365 | case 's': | |
14366 | { | |
14367 | unsigned i, len; | |
14368 | const char *str = XSTR (k, fidx); | |
14369 | len = strlen (str); | |
14370 | result = result * 613 + len; | |
14371 | for (i = 0; i < len; i++) | |
14372 | result = result * 613 + (unsigned) str[i]; | |
17167fd8 MM |
14373 | break; |
14374 | } | |
9ebbca7d GK |
14375 | case 'u': |
14376 | case 'e': | |
14377 | result = result * 1231 + rs6000_hash_constant (XEXP (k, fidx)); | |
14378 | break; | |
14379 | case 'i': | |
14380 | case 'n': | |
14381 | result = result * 613 + (unsigned) XINT (k, fidx); | |
14382 | break; | |
14383 | case 'w': | |
14384 | if (sizeof (unsigned) >= sizeof (HOST_WIDE_INT)) | |
14385 | result = result * 613 + (unsigned) XWINT (k, fidx); | |
14386 | else | |
14387 | { | |
14388 | size_t i; | |
9390387d | 14389 | for (i = 0; i < sizeof (HOST_WIDE_INT) / sizeof (unsigned); i++) |
9ebbca7d GK |
14390 | result = result * 613 + (unsigned) (XWINT (k, fidx) |
14391 | >> CHAR_BIT * i); | |
14392 | } | |
14393 | break; | |
09501938 DE |
14394 | case '0': |
14395 | break; | |
9ebbca7d | 14396 | default: |
37409796 | 14397 | gcc_unreachable (); |
9ebbca7d | 14398 | } |
46b33600 | 14399 | |
9ebbca7d GK |
14400 | return result; |
14401 | } | |
14402 | ||
14403 | static unsigned | |
a2369ed3 | 14404 | toc_hash_function (const void *hash_entry) |
9ebbca7d | 14405 | { |
f676971a | 14406 | const struct toc_hash_struct *thc = |
a9098fd0 GK |
14407 | (const struct toc_hash_struct *) hash_entry; |
14408 | return rs6000_hash_constant (thc->key) ^ thc->key_mode; | |
9ebbca7d GK |
14409 | } |
14410 | ||
14411 | /* Compare H1 and H2 for equivalence. */ | |
14412 | ||
14413 | static int | |
a2369ed3 | 14414 | toc_hash_eq (const void *h1, const void *h2) |
9ebbca7d GK |
14415 | { |
14416 | rtx r1 = ((const struct toc_hash_struct *) h1)->key; | |
14417 | rtx r2 = ((const struct toc_hash_struct *) h2)->key; | |
14418 | ||
a9098fd0 GK |
14419 | if (((const struct toc_hash_struct *) h1)->key_mode |
14420 | != ((const struct toc_hash_struct *) h2)->key_mode) | |
14421 | return 0; | |
14422 | ||
5692c7bc | 14423 | return rtx_equal_p (r1, r2); |
9ebbca7d GK |
14424 | } |
14425 | ||
28e510bd MM |
14426 | /* These are the names given by the C++ front-end to vtables, and |
14427 | vtable-like objects. Ideally, this logic should not be here; | |
14428 | instead, there should be some programmatic way of inquiring as | |
14429 | to whether or not an object is a vtable. */ | |
14430 | ||
14431 | #define VTABLE_NAME_P(NAME) \ | |
9390387d | 14432 | (strncmp ("_vt.", name, strlen ("_vt.")) == 0 \ |
28e510bd MM |
14433 | || strncmp ("_ZTV", name, strlen ("_ZTV")) == 0 \ |
14434 | || strncmp ("_ZTT", name, strlen ("_ZTT")) == 0 \ | |
26be75db | 14435 | || strncmp ("_ZTI", name, strlen ("_ZTI")) == 0 \ |
f676971a | 14436 | || strncmp ("_ZTC", name, strlen ("_ZTC")) == 0) |
28e510bd MM |
14437 | |
14438 | void | |
a2369ed3 | 14439 | rs6000_output_symbol_ref (FILE *file, rtx x) |
28e510bd MM |
14440 | { |
14441 | /* Currently C++ toc references to vtables can be emitted before it | |
14442 | is decided whether the vtable is public or private. If this is | |
14443 | the case, then the linker will eventually complain that there is | |
f676971a | 14444 | a reference to an unknown section. Thus, for vtables only, |
28e510bd MM |
14445 | we emit the TOC reference to reference the symbol and not the |
14446 | section. */ | |
14447 | const char *name = XSTR (x, 0); | |
54ee9799 | 14448 | |
f676971a | 14449 | if (VTABLE_NAME_P (name)) |
54ee9799 DE |
14450 | { |
14451 | RS6000_OUTPUT_BASENAME (file, name); | |
14452 | } | |
14453 | else | |
14454 | assemble_name (file, name); | |
28e510bd MM |
14455 | } |
14456 | ||
a4f6c312 SS |
14457 | /* Output a TOC entry. We derive the entry name from what is being |
14458 | written. */ | |
9878760c RK |
14459 | |
14460 | void | |
a2369ed3 | 14461 | output_toc (FILE *file, rtx x, int labelno, enum machine_mode mode) |
9878760c RK |
14462 | { |
14463 | char buf[256]; | |
3cce094d | 14464 | const char *name = buf; |
ec940faa | 14465 | const char *real_name; |
9878760c RK |
14466 | rtx base = x; |
14467 | int offset = 0; | |
14468 | ||
37409796 | 14469 | gcc_assert (!TARGET_NO_TOC); |
4697a36c | 14470 | |
9ebbca7d GK |
14471 | /* When the linker won't eliminate them, don't output duplicate |
14472 | TOC entries (this happens on AIX if there is any kind of TOC, | |
17211ab5 GK |
14473 | and on SVR4 under -fPIC or -mrelocatable). Don't do this for |
14474 | CODE_LABELs. */ | |
14475 | if (TARGET_TOC && GET_CODE (x) != LABEL_REF) | |
9ebbca7d GK |
14476 | { |
14477 | struct toc_hash_struct *h; | |
14478 | void * * found; | |
f676971a | 14479 | |
17211ab5 | 14480 | /* Create toc_hash_table. This can't be done at OVERRIDE_OPTIONS |
c4ad648e | 14481 | time because GGC is not initialized at that point. */ |
17211ab5 | 14482 | if (toc_hash_table == NULL) |
f676971a | 14483 | toc_hash_table = htab_create_ggc (1021, toc_hash_function, |
17211ab5 GK |
14484 | toc_hash_eq, NULL); |
14485 | ||
9ebbca7d GK |
14486 | h = ggc_alloc (sizeof (*h)); |
14487 | h->key = x; | |
a9098fd0 | 14488 | h->key_mode = mode; |
9ebbca7d | 14489 | h->labelno = labelno; |
f676971a | 14490 | |
9ebbca7d GK |
14491 | found = htab_find_slot (toc_hash_table, h, 1); |
14492 | if (*found == NULL) | |
14493 | *found = h; | |
f676971a | 14494 | else /* This is indeed a duplicate. |
9ebbca7d GK |
14495 | Set this label equal to that label. */ |
14496 | { | |
14497 | fputs ("\t.set ", file); | |
14498 | ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC"); | |
14499 | fprintf (file, "%d,", labelno); | |
14500 | ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC"); | |
f676971a | 14501 | fprintf (file, "%d\n", ((*(const struct toc_hash_struct **) |
9ebbca7d GK |
14502 | found)->labelno)); |
14503 | return; | |
14504 | } | |
14505 | } | |
14506 | ||
14507 | /* If we're going to put a double constant in the TOC, make sure it's | |
14508 | aligned properly when strict alignment is on. */ | |
ff1720ed RK |
14509 | if (GET_CODE (x) == CONST_DOUBLE |
14510 | && STRICT_ALIGNMENT | |
a9098fd0 | 14511 | && GET_MODE_BITSIZE (mode) >= 64 |
ff1720ed RK |
14512 | && ! (TARGET_NO_FP_IN_TOC && ! TARGET_MINIMAL_TOC)) { |
14513 | ASM_OUTPUT_ALIGN (file, 3); | |
14514 | } | |
14515 | ||
4977bab6 | 14516 | (*targetm.asm_out.internal_label) (file, "LC", labelno); |
9878760c | 14517 | |
37c37a57 RK |
14518 | /* Handle FP constants specially. Note that if we have a minimal |
14519 | TOC, things we put here aren't actually in the TOC, so we can allow | |
14520 | FP constants. */ | |
fcce224d DE |
14521 | if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == TFmode) |
14522 | { | |
14523 | REAL_VALUE_TYPE rv; | |
14524 | long k[4]; | |
14525 | ||
14526 | REAL_VALUE_FROM_CONST_DOUBLE (rv, x); | |
14527 | REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv, k); | |
14528 | ||
14529 | if (TARGET_64BIT) | |
14530 | { | |
14531 | if (TARGET_MINIMAL_TOC) | |
14532 | fputs (DOUBLE_INT_ASM_OP, file); | |
14533 | else | |
14534 | fprintf (file, "\t.tc FT_%lx_%lx_%lx_%lx[TC],", | |
14535 | k[0] & 0xffffffff, k[1] & 0xffffffff, | |
14536 | k[2] & 0xffffffff, k[3] & 0xffffffff); | |
14537 | fprintf (file, "0x%lx%08lx,0x%lx%08lx\n", | |
14538 | k[0] & 0xffffffff, k[1] & 0xffffffff, | |
14539 | k[2] & 0xffffffff, k[3] & 0xffffffff); | |
14540 | return; | |
14541 | } | |
14542 | else | |
14543 | { | |
14544 | if (TARGET_MINIMAL_TOC) | |
14545 | fputs ("\t.long ", file); | |
14546 | else | |
14547 | fprintf (file, "\t.tc FT_%lx_%lx_%lx_%lx[TC],", | |
14548 | k[0] & 0xffffffff, k[1] & 0xffffffff, | |
14549 | k[2] & 0xffffffff, k[3] & 0xffffffff); | |
14550 | fprintf (file, "0x%lx,0x%lx,0x%lx,0x%lx\n", | |
14551 | k[0] & 0xffffffff, k[1] & 0xffffffff, | |
14552 | k[2] & 0xffffffff, k[3] & 0xffffffff); | |
14553 | return; | |
14554 | } | |
14555 | } | |
14556 | else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == DFmode) | |
9878760c | 14557 | { |
042259f2 DE |
14558 | REAL_VALUE_TYPE rv; |
14559 | long k[2]; | |
0adc764e | 14560 | |
042259f2 DE |
14561 | REAL_VALUE_FROM_CONST_DOUBLE (rv, x); |
14562 | REAL_VALUE_TO_TARGET_DOUBLE (rv, k); | |
31bfaa0b | 14563 | |
13ded975 DE |
14564 | if (TARGET_64BIT) |
14565 | { | |
14566 | if (TARGET_MINIMAL_TOC) | |
2bfcf297 | 14567 | fputs (DOUBLE_INT_ASM_OP, file); |
13ded975 | 14568 | else |
2f0552b6 AM |
14569 | fprintf (file, "\t.tc FD_%lx_%lx[TC],", |
14570 | k[0] & 0xffffffff, k[1] & 0xffffffff); | |
14571 | fprintf (file, "0x%lx%08lx\n", | |
14572 | k[0] & 0xffffffff, k[1] & 0xffffffff); | |
13ded975 DE |
14573 | return; |
14574 | } | |
1875cc88 | 14575 | else |
13ded975 DE |
14576 | { |
14577 | if (TARGET_MINIMAL_TOC) | |
2bfcf297 | 14578 | fputs ("\t.long ", file); |
13ded975 | 14579 | else |
2f0552b6 AM |
14580 | fprintf (file, "\t.tc FD_%lx_%lx[TC],", |
14581 | k[0] & 0xffffffff, k[1] & 0xffffffff); | |
14582 | fprintf (file, "0x%lx,0x%lx\n", | |
14583 | k[0] & 0xffffffff, k[1] & 0xffffffff); | |
13ded975 DE |
14584 | return; |
14585 | } | |
9878760c | 14586 | } |
a9098fd0 | 14587 | else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == SFmode) |
9878760c | 14588 | { |
042259f2 DE |
14589 | REAL_VALUE_TYPE rv; |
14590 | long l; | |
9878760c | 14591 | |
042259f2 DE |
14592 | REAL_VALUE_FROM_CONST_DOUBLE (rv, x); |
14593 | REAL_VALUE_TO_TARGET_SINGLE (rv, l); | |
14594 | ||
31bfaa0b DE |
14595 | if (TARGET_64BIT) |
14596 | { | |
14597 | if (TARGET_MINIMAL_TOC) | |
2bfcf297 | 14598 | fputs (DOUBLE_INT_ASM_OP, file); |
31bfaa0b | 14599 | else |
2f0552b6 AM |
14600 | fprintf (file, "\t.tc FS_%lx[TC],", l & 0xffffffff); |
14601 | fprintf (file, "0x%lx00000000\n", l & 0xffffffff); | |
31bfaa0b DE |
14602 | return; |
14603 | } | |
042259f2 | 14604 | else |
31bfaa0b DE |
14605 | { |
14606 | if (TARGET_MINIMAL_TOC) | |
2bfcf297 | 14607 | fputs ("\t.long ", file); |
31bfaa0b | 14608 | else |
2f0552b6 AM |
14609 | fprintf (file, "\t.tc FS_%lx[TC],", l & 0xffffffff); |
14610 | fprintf (file, "0x%lx\n", l & 0xffffffff); | |
31bfaa0b DE |
14611 | return; |
14612 | } | |
042259f2 | 14613 | } |
f176e826 | 14614 | else if (GET_MODE (x) == VOIDmode |
a9098fd0 | 14615 | && (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE)) |
042259f2 | 14616 | { |
e2c953b6 | 14617 | unsigned HOST_WIDE_INT low; |
042259f2 DE |
14618 | HOST_WIDE_INT high; |
14619 | ||
14620 | if (GET_CODE (x) == CONST_DOUBLE) | |
14621 | { | |
14622 | low = CONST_DOUBLE_LOW (x); | |
14623 | high = CONST_DOUBLE_HIGH (x); | |
14624 | } | |
14625 | else | |
14626 | #if HOST_BITS_PER_WIDE_INT == 32 | |
14627 | { | |
14628 | low = INTVAL (x); | |
0858c623 | 14629 | high = (low & 0x80000000) ? ~0 : 0; |
042259f2 DE |
14630 | } |
14631 | #else | |
14632 | { | |
c4ad648e AM |
14633 | low = INTVAL (x) & 0xffffffff; |
14634 | high = (HOST_WIDE_INT) INTVAL (x) >> 32; | |
042259f2 DE |
14635 | } |
14636 | #endif | |
9878760c | 14637 | |
a9098fd0 GK |
14638 | /* TOC entries are always Pmode-sized, but since this |
14639 | is a bigendian machine then if we're putting smaller | |
14640 | integer constants in the TOC we have to pad them. | |
14641 | (This is still a win over putting the constants in | |
14642 | a separate constant pool, because then we'd have | |
02a4ec28 FS |
14643 | to have both a TOC entry _and_ the actual constant.) |
14644 | ||
14645 | For a 32-bit target, CONST_INT values are loaded and shifted | |
14646 | entirely within `low' and can be stored in one TOC entry. */ | |
14647 | ||
37409796 NS |
14648 | /* It would be easy to make this work, but it doesn't now. */ |
14649 | gcc_assert (!TARGET_64BIT || POINTER_SIZE >= GET_MODE_BITSIZE (mode)); | |
02a4ec28 FS |
14650 | |
14651 | if (POINTER_SIZE > GET_MODE_BITSIZE (mode)) | |
fb52d8de AM |
14652 | { |
14653 | #if HOST_BITS_PER_WIDE_INT == 32 | |
14654 | lshift_double (low, high, POINTER_SIZE - GET_MODE_BITSIZE (mode), | |
14655 | POINTER_SIZE, &low, &high, 0); | |
14656 | #else | |
14657 | low |= high << 32; | |
14658 | low <<= POINTER_SIZE - GET_MODE_BITSIZE (mode); | |
14659 | high = (HOST_WIDE_INT) low >> 32; | |
14660 | low &= 0xffffffff; | |
14661 | #endif | |
14662 | } | |
a9098fd0 | 14663 | |
13ded975 DE |
14664 | if (TARGET_64BIT) |
14665 | { | |
14666 | if (TARGET_MINIMAL_TOC) | |
2bfcf297 | 14667 | fputs (DOUBLE_INT_ASM_OP, file); |
13ded975 | 14668 | else |
2f0552b6 AM |
14669 | fprintf (file, "\t.tc ID_%lx_%lx[TC],", |
14670 | (long) high & 0xffffffff, (long) low & 0xffffffff); | |
14671 | fprintf (file, "0x%lx%08lx\n", | |
14672 | (long) high & 0xffffffff, (long) low & 0xffffffff); | |
13ded975 DE |
14673 | return; |
14674 | } | |
1875cc88 | 14675 | else |
13ded975 | 14676 | { |
02a4ec28 FS |
14677 | if (POINTER_SIZE < GET_MODE_BITSIZE (mode)) |
14678 | { | |
14679 | if (TARGET_MINIMAL_TOC) | |
2bfcf297 | 14680 | fputs ("\t.long ", file); |
02a4ec28 | 14681 | else |
2bfcf297 | 14682 | fprintf (file, "\t.tc ID_%lx_%lx[TC],", |
2f0552b6 AM |
14683 | (long) high & 0xffffffff, (long) low & 0xffffffff); |
14684 | fprintf (file, "0x%lx,0x%lx\n", | |
14685 | (long) high & 0xffffffff, (long) low & 0xffffffff); | |
02a4ec28 | 14686 | } |
13ded975 | 14687 | else |
02a4ec28 FS |
14688 | { |
14689 | if (TARGET_MINIMAL_TOC) | |
2bfcf297 | 14690 | fputs ("\t.long ", file); |
02a4ec28 | 14691 | else |
2f0552b6 AM |
14692 | fprintf (file, "\t.tc IS_%lx[TC],", (long) low & 0xffffffff); |
14693 | fprintf (file, "0x%lx\n", (long) low & 0xffffffff); | |
02a4ec28 | 14694 | } |
13ded975 DE |
14695 | return; |
14696 | } | |
9878760c RK |
14697 | } |
14698 | ||
14699 | if (GET_CODE (x) == CONST) | |
14700 | { | |
37409796 | 14701 | gcc_assert (GET_CODE (XEXP (x, 0)) == PLUS); |
2bfcf297 | 14702 | |
9878760c RK |
14703 | base = XEXP (XEXP (x, 0), 0); |
14704 | offset = INTVAL (XEXP (XEXP (x, 0), 1)); | |
14705 | } | |
f676971a | 14706 | |
37409796 NS |
14707 | switch (GET_CODE (base)) |
14708 | { | |
14709 | case SYMBOL_REF: | |
14710 | name = XSTR (base, 0); | |
14711 | break; | |
14712 | ||
14713 | case LABEL_REF: | |
14714 | ASM_GENERATE_INTERNAL_LABEL (buf, "L", | |
14715 | CODE_LABEL_NUMBER (XEXP (base, 0))); | |
14716 | break; | |
14717 | ||
14718 | case CODE_LABEL: | |
14719 | ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (base)); | |
14720 | break; | |
14721 | ||
14722 | default: | |
14723 | gcc_unreachable (); | |
14724 | } | |
9878760c | 14725 | |
772c5265 | 14726 | real_name = (*targetm.strip_name_encoding) (name); |
1875cc88 | 14727 | if (TARGET_MINIMAL_TOC) |
2bfcf297 | 14728 | fputs (TARGET_32BIT ? "\t.long " : DOUBLE_INT_ASM_OP, file); |
1875cc88 JW |
14729 | else |
14730 | { | |
b6c9286a | 14731 | fprintf (file, "\t.tc %s", real_name); |
9878760c | 14732 | |
1875cc88 JW |
14733 | if (offset < 0) |
14734 | fprintf (file, ".N%d", - offset); | |
14735 | else if (offset) | |
14736 | fprintf (file, ".P%d", offset); | |
9878760c | 14737 | |
19d2d16f | 14738 | fputs ("[TC],", file); |
1875cc88 | 14739 | } |
581bc4de MM |
14740 | |
14741 | /* Currently C++ toc references to vtables can be emitted before it | |
14742 | is decided whether the vtable is public or private. If this is | |
14743 | the case, then the linker will eventually complain that there is | |
14744 | a TOC reference to an unknown section. Thus, for vtables only, | |
14745 | we emit the TOC reference to reference the symbol and not the | |
14746 | section. */ | |
28e510bd | 14747 | if (VTABLE_NAME_P (name)) |
581bc4de | 14748 | { |
54ee9799 | 14749 | RS6000_OUTPUT_BASENAME (file, name); |
581bc4de MM |
14750 | if (offset < 0) |
14751 | fprintf (file, "%d", offset); | |
14752 | else if (offset > 0) | |
14753 | fprintf (file, "+%d", offset); | |
14754 | } | |
14755 | else | |
14756 | output_addr_const (file, x); | |
19d2d16f | 14757 | putc ('\n', file); |
9878760c RK |
14758 | } |
14759 | \f | |
14760 | /* Output an assembler pseudo-op to write an ASCII string of N characters | |
14761 | starting at P to FILE. | |
14762 | ||
14763 | On the RS/6000, we have to do this using the .byte operation and | |
14764 | write out special characters outside the quoted string. | |
14765 | Also, the assembler is broken; very long strings are truncated, | |
a4f6c312 | 14766 | so we must artificially break them up early. */ |
9878760c RK |
14767 | |
14768 | void | |
a2369ed3 | 14769 | output_ascii (FILE *file, const char *p, int n) |
9878760c RK |
14770 | { |
14771 | char c; | |
14772 | int i, count_string; | |
d330fd93 KG |
14773 | const char *for_string = "\t.byte \""; |
14774 | const char *for_decimal = "\t.byte "; | |
14775 | const char *to_close = NULL; | |
9878760c RK |
14776 | |
14777 | count_string = 0; | |
14778 | for (i = 0; i < n; i++) | |
14779 | { | |
14780 | c = *p++; | |
14781 | if (c >= ' ' && c < 0177) | |
14782 | { | |
14783 | if (for_string) | |
14784 | fputs (for_string, file); | |
14785 | putc (c, file); | |
14786 | ||
14787 | /* Write two quotes to get one. */ | |
14788 | if (c == '"') | |
14789 | { | |
14790 | putc (c, file); | |
14791 | ++count_string; | |
14792 | } | |
14793 | ||
14794 | for_string = NULL; | |
14795 | for_decimal = "\"\n\t.byte "; | |
14796 | to_close = "\"\n"; | |
14797 | ++count_string; | |
14798 | ||
14799 | if (count_string >= 512) | |
14800 | { | |
14801 | fputs (to_close, file); | |
14802 | ||
14803 | for_string = "\t.byte \""; | |
14804 | for_decimal = "\t.byte "; | |
14805 | to_close = NULL; | |
14806 | count_string = 0; | |
14807 | } | |
14808 | } | |
14809 | else | |
14810 | { | |
14811 | if (for_decimal) | |
14812 | fputs (for_decimal, file); | |
14813 | fprintf (file, "%d", c); | |
14814 | ||
14815 | for_string = "\n\t.byte \""; | |
14816 | for_decimal = ", "; | |
14817 | to_close = "\n"; | |
14818 | count_string = 0; | |
14819 | } | |
14820 | } | |
14821 | ||
14822 | /* Now close the string if we have written one. Then end the line. */ | |
14823 | if (to_close) | |
9ebbca7d | 14824 | fputs (to_close, file); |
9878760c RK |
14825 | } |
14826 | \f | |
14827 | /* Generate a unique section name for FILENAME for a section type | |
14828 | represented by SECTION_DESC. Output goes into BUF. | |
14829 | ||
14830 | SECTION_DESC can be any string, as long as it is different for each | |
14831 | possible section type. | |
14832 | ||
14833 | We name the section in the same manner as xlc. The name begins with an | |
14834 | underscore followed by the filename (after stripping any leading directory | |
11e5fe42 RK |
14835 | names) with the last period replaced by the string SECTION_DESC. If |
14836 | FILENAME does not contain a period, SECTION_DESC is appended to the end of | |
14837 | the name. */ | |
9878760c RK |
14838 | |
14839 | void | |
f676971a | 14840 | rs6000_gen_section_name (char **buf, const char *filename, |
c4ad648e | 14841 | const char *section_desc) |
9878760c | 14842 | { |
9ebbca7d | 14843 | const char *q, *after_last_slash, *last_period = 0; |
9878760c RK |
14844 | char *p; |
14845 | int len; | |
9878760c RK |
14846 | |
14847 | after_last_slash = filename; | |
14848 | for (q = filename; *q; q++) | |
11e5fe42 RK |
14849 | { |
14850 | if (*q == '/') | |
14851 | after_last_slash = q + 1; | |
14852 | else if (*q == '.') | |
14853 | last_period = q; | |
14854 | } | |
9878760c | 14855 | |
11e5fe42 | 14856 | len = strlen (after_last_slash) + strlen (section_desc) + 2; |
6d9f628e | 14857 | *buf = (char *) xmalloc (len); |
9878760c RK |
14858 | |
14859 | p = *buf; | |
14860 | *p++ = '_'; | |
14861 | ||
14862 | for (q = after_last_slash; *q; q++) | |
14863 | { | |
11e5fe42 | 14864 | if (q == last_period) |
c4ad648e | 14865 | { |
9878760c RK |
14866 | strcpy (p, section_desc); |
14867 | p += strlen (section_desc); | |
e3981aab | 14868 | break; |
c4ad648e | 14869 | } |
9878760c | 14870 | |
e9a780ec | 14871 | else if (ISALNUM (*q)) |
c4ad648e | 14872 | *p++ = *q; |
9878760c RK |
14873 | } |
14874 | ||
11e5fe42 | 14875 | if (last_period == 0) |
9878760c RK |
14876 | strcpy (p, section_desc); |
14877 | else | |
14878 | *p = '\0'; | |
14879 | } | |
e165f3f0 | 14880 | \f |
a4f6c312 | 14881 | /* Emit profile function. */ |
411707f4 | 14882 | |
411707f4 | 14883 | void |
a2369ed3 | 14884 | output_profile_hook (int labelno ATTRIBUTE_UNUSED) |
411707f4 | 14885 | { |
ffcfcb5f AM |
14886 | if (TARGET_PROFILE_KERNEL) |
14887 | return; | |
14888 | ||
8480e480 CC |
14889 | if (DEFAULT_ABI == ABI_AIX) |
14890 | { | |
9739c90c JJ |
14891 | #ifndef NO_PROFILE_COUNTERS |
14892 | # define NO_PROFILE_COUNTERS 0 | |
14893 | #endif | |
f676971a | 14894 | if (NO_PROFILE_COUNTERS) |
9739c90c JJ |
14895 | emit_library_call (init_one_libfunc (RS6000_MCOUNT), 0, VOIDmode, 0); |
14896 | else | |
14897 | { | |
14898 | char buf[30]; | |
14899 | const char *label_name; | |
14900 | rtx fun; | |
411707f4 | 14901 | |
9739c90c JJ |
14902 | ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno); |
14903 | label_name = (*targetm.strip_name_encoding) (ggc_strdup (buf)); | |
14904 | fun = gen_rtx_SYMBOL_REF (Pmode, label_name); | |
411707f4 | 14905 | |
9739c90c JJ |
14906 | emit_library_call (init_one_libfunc (RS6000_MCOUNT), 0, VOIDmode, 1, |
14907 | fun, Pmode); | |
14908 | } | |
8480e480 | 14909 | } |
ee890fe2 SS |
14910 | else if (DEFAULT_ABI == ABI_DARWIN) |
14911 | { | |
d5fa86ba | 14912 | const char *mcount_name = RS6000_MCOUNT; |
ee890fe2 SS |
14913 | int caller_addr_regno = LINK_REGISTER_REGNUM; |
14914 | ||
14915 | /* Be conservative and always set this, at least for now. */ | |
14916 | current_function_uses_pic_offset_table = 1; | |
14917 | ||
14918 | #if TARGET_MACHO | |
14919 | /* For PIC code, set up a stub and collect the caller's address | |
14920 | from r0, which is where the prologue puts it. */ | |
11abc112 MM |
14921 | if (MACHOPIC_INDIRECT |
14922 | && current_function_uses_pic_offset_table) | |
14923 | caller_addr_regno = 0; | |
ee890fe2 SS |
14924 | #endif |
14925 | emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mcount_name), | |
14926 | 0, VOIDmode, 1, | |
14927 | gen_rtx_REG (Pmode, caller_addr_regno), Pmode); | |
14928 | } | |
411707f4 CC |
14929 | } |
14930 | ||
a4f6c312 | 14931 | /* Write function profiler code. */ |
e165f3f0 RK |
14932 | |
14933 | void | |
a2369ed3 | 14934 | output_function_profiler (FILE *file, int labelno) |
e165f3f0 | 14935 | { |
3daf36a4 | 14936 | char buf[100]; |
09eeeacb | 14937 | int save_lr = 8; |
e165f3f0 | 14938 | |
38c1f2d7 | 14939 | switch (DEFAULT_ABI) |
3daf36a4 | 14940 | { |
38c1f2d7 | 14941 | default: |
37409796 | 14942 | gcc_unreachable (); |
38c1f2d7 MM |
14943 | |
14944 | case ABI_V4: | |
09eeeacb | 14945 | save_lr = 4; |
09eeeacb AM |
14946 | if (!TARGET_32BIT) |
14947 | { | |
d4ee4d25 | 14948 | warning (0, "no profiling of 64-bit code for this ABI"); |
09eeeacb AM |
14949 | return; |
14950 | } | |
ffcfcb5f | 14951 | ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno); |
38c1f2d7 MM |
14952 | fprintf (file, "\tmflr %s\n", reg_names[0]); |
14953 | if (flag_pic == 1) | |
14954 | { | |
dfdfa60f | 14955 | fputs ("\tbl _GLOBAL_OFFSET_TABLE_@local-4\n", file); |
09eeeacb AM |
14956 | asm_fprintf (file, "\t{st|stw} %s,%d(%s)\n", |
14957 | reg_names[0], save_lr, reg_names[1]); | |
17167fd8 | 14958 | asm_fprintf (file, "\tmflr %s\n", reg_names[12]); |
dfdfa60f | 14959 | asm_fprintf (file, "\t{l|lwz} %s,", reg_names[0]); |
38c1f2d7 | 14960 | assemble_name (file, buf); |
17167fd8 | 14961 | asm_fprintf (file, "@got(%s)\n", reg_names[12]); |
38c1f2d7 | 14962 | } |
9ebbca7d | 14963 | else if (flag_pic > 1) |
38c1f2d7 | 14964 | { |
09eeeacb AM |
14965 | asm_fprintf (file, "\t{st|stw} %s,%d(%s)\n", |
14966 | reg_names[0], save_lr, reg_names[1]); | |
9ebbca7d GK |
14967 | /* Now, we need to get the address of the label. */ |
14968 | fputs ("\tbl 1f\n\t.long ", file); | |
034e84c4 | 14969 | assemble_name (file, buf); |
9ebbca7d GK |
14970 | fputs ("-.\n1:", file); |
14971 | asm_fprintf (file, "\tmflr %s\n", reg_names[11]); | |
f676971a | 14972 | asm_fprintf (file, "\t{l|lwz} %s,0(%s)\n", |
9ebbca7d GK |
14973 | reg_names[0], reg_names[11]); |
14974 | asm_fprintf (file, "\t{cax|add} %s,%s,%s\n", | |
14975 | reg_names[0], reg_names[0], reg_names[11]); | |
38c1f2d7 | 14976 | } |
38c1f2d7 MM |
14977 | else |
14978 | { | |
17167fd8 | 14979 | asm_fprintf (file, "\t{liu|lis} %s,", reg_names[12]); |
38c1f2d7 | 14980 | assemble_name (file, buf); |
dfdfa60f | 14981 | fputs ("@ha\n", file); |
09eeeacb AM |
14982 | asm_fprintf (file, "\t{st|stw} %s,%d(%s)\n", |
14983 | reg_names[0], save_lr, reg_names[1]); | |
a260abc9 | 14984 | asm_fprintf (file, "\t{cal|la} %s,", reg_names[0]); |
38c1f2d7 | 14985 | assemble_name (file, buf); |
17167fd8 | 14986 | asm_fprintf (file, "@l(%s)\n", reg_names[12]); |
38c1f2d7 MM |
14987 | } |
14988 | ||
50d440bc | 14989 | /* ABI_V4 saves the static chain reg with ASM_OUTPUT_REG_PUSH. */ |
3b6ce0af DE |
14990 | fprintf (file, "\tbl %s%s\n", |
14991 | RS6000_MCOUNT, flag_pic ? "@plt" : ""); | |
38c1f2d7 MM |
14992 | break; |
14993 | ||
14994 | case ABI_AIX: | |
ee890fe2 | 14995 | case ABI_DARWIN: |
ffcfcb5f AM |
14996 | if (!TARGET_PROFILE_KERNEL) |
14997 | { | |
a3c9585f | 14998 | /* Don't do anything, done in output_profile_hook (). */ |
ffcfcb5f AM |
14999 | } |
15000 | else | |
15001 | { | |
37409796 | 15002 | gcc_assert (!TARGET_32BIT); |
ffcfcb5f AM |
15003 | |
15004 | asm_fprintf (file, "\tmflr %s\n", reg_names[0]); | |
15005 | asm_fprintf (file, "\tstd %s,16(%s)\n", reg_names[0], reg_names[1]); | |
15006 | ||
6de9cd9a | 15007 | if (cfun->static_chain_decl != NULL) |
ffcfcb5f AM |
15008 | { |
15009 | asm_fprintf (file, "\tstd %s,24(%s)\n", | |
15010 | reg_names[STATIC_CHAIN_REGNUM], reg_names[1]); | |
15011 | fprintf (file, "\tbl %s\n", RS6000_MCOUNT); | |
15012 | asm_fprintf (file, "\tld %s,24(%s)\n", | |
15013 | reg_names[STATIC_CHAIN_REGNUM], reg_names[1]); | |
15014 | } | |
15015 | else | |
15016 | fprintf (file, "\tbl %s\n", RS6000_MCOUNT); | |
15017 | } | |
38c1f2d7 MM |
15018 | break; |
15019 | } | |
e165f3f0 | 15020 | } |
a251ffd0 | 15021 | |
b54cf83a | 15022 | \f |
b54cf83a DE |
15023 | /* Power4 load update and store update instructions are cracked into a |
15024 | load or store and an integer insn which are executed in the same cycle. | |
15025 | Branches have their own dispatch slot which does not count against the | |
15026 | GCC issue rate, but it changes the program flow so there are no other | |
15027 | instructions to issue in this cycle. */ | |
15028 | ||
15029 | static int | |
f676971a EC |
15030 | rs6000_variable_issue (FILE *stream ATTRIBUTE_UNUSED, |
15031 | int verbose ATTRIBUTE_UNUSED, | |
a2369ed3 | 15032 | rtx insn, int more) |
b54cf83a DE |
15033 | { |
15034 | if (GET_CODE (PATTERN (insn)) == USE | |
15035 | || GET_CODE (PATTERN (insn)) == CLOBBER) | |
15036 | return more; | |
15037 | ||
ec507f2d | 15038 | if (rs6000_sched_groups) |
b54cf83a | 15039 | { |
cbe26ab8 | 15040 | if (is_microcoded_insn (insn)) |
c4ad648e | 15041 | return 0; |
cbe26ab8 | 15042 | else if (is_cracked_insn (insn)) |
c4ad648e | 15043 | return more > 2 ? more - 2 : 0; |
b54cf83a | 15044 | } |
165b263e DE |
15045 | |
15046 | return more - 1; | |
b54cf83a DE |
15047 | } |
15048 | ||
a251ffd0 TG |
15049 | /* Adjust the cost of a scheduling dependency. Return the new cost of |
15050 | a dependency LINK or INSN on DEP_INSN. COST is the current cost. */ | |
15051 | ||
c237e94a | 15052 | static int |
0a4f0294 | 15053 | rs6000_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost) |
a251ffd0 TG |
15054 | { |
15055 | if (! recog_memoized (insn)) | |
15056 | return 0; | |
15057 | ||
15058 | if (REG_NOTE_KIND (link) != 0) | |
15059 | return 0; | |
15060 | ||
15061 | if (REG_NOTE_KIND (link) == 0) | |
15062 | { | |
ed947a96 DJ |
15063 | /* Data dependency; DEP_INSN writes a register that INSN reads |
15064 | some cycles later. */ | |
c9dbf840 DE |
15065 | |
15066 | /* Separate a load from a narrower, dependent store. */ | |
15067 | if (rs6000_sched_groups | |
15068 | && GET_CODE (PATTERN (insn)) == SET | |
15069 | && GET_CODE (PATTERN (dep_insn)) == SET | |
15070 | && GET_CODE (XEXP (PATTERN (insn), 1)) == MEM | |
15071 | && GET_CODE (XEXP (PATTERN (dep_insn), 0)) == MEM | |
15072 | && (GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (insn), 1))) | |
15073 | > GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (dep_insn), 0))))) | |
15074 | return cost + 14; | |
15075 | ||
ed947a96 DJ |
15076 | switch (get_attr_type (insn)) |
15077 | { | |
15078 | case TYPE_JMPREG: | |
309323c2 | 15079 | /* Tell the first scheduling pass about the latency between |
ed947a96 DJ |
15080 | a mtctr and bctr (and mtlr and br/blr). The first |
15081 | scheduling pass will not know about this latency since | |
15082 | the mtctr instruction, which has the latency associated | |
15083 | to it, will be generated by reload. */ | |
309323c2 | 15084 | return TARGET_POWER ? 5 : 4; |
ed947a96 DJ |
15085 | case TYPE_BRANCH: |
15086 | /* Leave some extra cycles between a compare and its | |
15087 | dependent branch, to inhibit expensive mispredicts. */ | |
309323c2 DE |
15088 | if ((rs6000_cpu_attr == CPU_PPC603 |
15089 | || rs6000_cpu_attr == CPU_PPC604 | |
15090 | || rs6000_cpu_attr == CPU_PPC604E | |
15091 | || rs6000_cpu_attr == CPU_PPC620 | |
15092 | || rs6000_cpu_attr == CPU_PPC630 | |
15093 | || rs6000_cpu_attr == CPU_PPC750 | |
15094 | || rs6000_cpu_attr == CPU_PPC7400 | |
15095 | || rs6000_cpu_attr == CPU_PPC7450 | |
ec507f2d DE |
15096 | || rs6000_cpu_attr == CPU_POWER4 |
15097 | || rs6000_cpu_attr == CPU_POWER5) | |
ed947a96 DJ |
15098 | && recog_memoized (dep_insn) |
15099 | && (INSN_CODE (dep_insn) >= 0) | |
b54cf83a DE |
15100 | && (get_attr_type (dep_insn) == TYPE_CMP |
15101 | || get_attr_type (dep_insn) == TYPE_COMPARE | |
ed947a96 | 15102 | || get_attr_type (dep_insn) == TYPE_DELAYED_COMPARE |
9259f3b0 DE |
15103 | || get_attr_type (dep_insn) == TYPE_IMUL_COMPARE |
15104 | || get_attr_type (dep_insn) == TYPE_LMUL_COMPARE | |
ed947a96 | 15105 | || get_attr_type (dep_insn) == TYPE_FPCOMPARE |
b54cf83a DE |
15106 | || get_attr_type (dep_insn) == TYPE_CR_LOGICAL |
15107 | || get_attr_type (dep_insn) == TYPE_DELAYED_CR)) | |
ed947a96 DJ |
15108 | return cost + 2; |
15109 | default: | |
15110 | break; | |
15111 | } | |
a251ffd0 TG |
15112 | /* Fall out to return default cost. */ |
15113 | } | |
15114 | ||
15115 | return cost; | |
15116 | } | |
b6c9286a | 15117 | |
cbe26ab8 | 15118 | /* The function returns a true if INSN is microcoded. |
839a4992 | 15119 | Return false otherwise. */ |
cbe26ab8 DN |
15120 | |
15121 | static bool | |
15122 | is_microcoded_insn (rtx insn) | |
15123 | { | |
15124 | if (!insn || !INSN_P (insn) | |
15125 | || GET_CODE (PATTERN (insn)) == USE | |
15126 | || GET_CODE (PATTERN (insn)) == CLOBBER) | |
15127 | return false; | |
15128 | ||
ec507f2d | 15129 | if (rs6000_sched_groups) |
cbe26ab8 DN |
15130 | { |
15131 | enum attr_type type = get_attr_type (insn); | |
15132 | if (type == TYPE_LOAD_EXT_U | |
15133 | || type == TYPE_LOAD_EXT_UX | |
15134 | || type == TYPE_LOAD_UX | |
15135 | || type == TYPE_STORE_UX | |
15136 | || type == TYPE_MFCR) | |
c4ad648e | 15137 | return true; |
cbe26ab8 DN |
15138 | } |
15139 | ||
15140 | return false; | |
15141 | } | |
15142 | ||
5c425df5 | 15143 | /* The function returns a nonzero value if INSN can be scheduled only |
cbe26ab8 DN |
15144 | as the first insn in a dispatch group ("dispatch-slot restricted"). |
15145 | In this case, the returned value indicates how many dispatch slots | |
15146 | the insn occupies (at the beginning of the group). | |
79ae11c4 DN |
15147 | Return 0 otherwise. */ |
15148 | ||
cbe26ab8 | 15149 | static int |
79ae11c4 DN |
15150 | is_dispatch_slot_restricted (rtx insn) |
15151 | { | |
15152 | enum attr_type type; | |
15153 | ||
ec507f2d | 15154 | if (!rs6000_sched_groups) |
79ae11c4 DN |
15155 | return 0; |
15156 | ||
15157 | if (!insn | |
15158 | || insn == NULL_RTX | |
15159 | || GET_CODE (insn) == NOTE | |
15160 | || GET_CODE (PATTERN (insn)) == USE | |
15161 | || GET_CODE (PATTERN (insn)) == CLOBBER) | |
15162 | return 0; | |
15163 | ||
15164 | type = get_attr_type (insn); | |
15165 | ||
ec507f2d DE |
15166 | switch (type) |
15167 | { | |
15168 | case TYPE_MFCR: | |
15169 | case TYPE_MFCRF: | |
15170 | case TYPE_MTCR: | |
15171 | case TYPE_DELAYED_CR: | |
15172 | case TYPE_CR_LOGICAL: | |
15173 | case TYPE_MTJMPR: | |
15174 | case TYPE_MFJMPR: | |
15175 | return 1; | |
15176 | case TYPE_IDIV: | |
15177 | case TYPE_LDIV: | |
15178 | return 2; | |
15179 | default: | |
15180 | if (rs6000_cpu == PROCESSOR_POWER5 | |
15181 | && is_cracked_insn (insn)) | |
15182 | return 2; | |
15183 | return 0; | |
15184 | } | |
79ae11c4 DN |
15185 | } |
15186 | ||
cbe26ab8 DN |
15187 | /* The function returns true if INSN is cracked into 2 instructions |
15188 | by the processor (and therefore occupies 2 issue slots). */ | |
15189 | ||
15190 | static bool | |
15191 | is_cracked_insn (rtx insn) | |
15192 | { | |
15193 | if (!insn || !INSN_P (insn) | |
15194 | || GET_CODE (PATTERN (insn)) == USE | |
15195 | || GET_CODE (PATTERN (insn)) == CLOBBER) | |
15196 | return false; | |
15197 | ||
ec507f2d | 15198 | if (rs6000_sched_groups) |
cbe26ab8 DN |
15199 | { |
15200 | enum attr_type type = get_attr_type (insn); | |
15201 | if (type == TYPE_LOAD_U || type == TYPE_STORE_U | |
c4ad648e AM |
15202 | || type == TYPE_FPLOAD_U || type == TYPE_FPSTORE_U |
15203 | || type == TYPE_FPLOAD_UX || type == TYPE_FPSTORE_UX | |
15204 | || type == TYPE_LOAD_EXT || type == TYPE_DELAYED_CR | |
15205 | || type == TYPE_COMPARE || type == TYPE_DELAYED_COMPARE | |
15206 | || type == TYPE_IMUL_COMPARE || type == TYPE_LMUL_COMPARE | |
15207 | || type == TYPE_IDIV || type == TYPE_LDIV | |
15208 | || type == TYPE_INSERT_WORD) | |
15209 | return true; | |
cbe26ab8 DN |
15210 | } |
15211 | ||
15212 | return false; | |
15213 | } | |
15214 | ||
15215 | /* The function returns true if INSN can be issued only from | |
a3c9585f | 15216 | the branch slot. */ |
cbe26ab8 DN |
15217 | |
15218 | static bool | |
15219 | is_branch_slot_insn (rtx insn) | |
15220 | { | |
15221 | if (!insn || !INSN_P (insn) | |
15222 | || GET_CODE (PATTERN (insn)) == USE | |
15223 | || GET_CODE (PATTERN (insn)) == CLOBBER) | |
15224 | return false; | |
15225 | ||
ec507f2d | 15226 | if (rs6000_sched_groups) |
cbe26ab8 DN |
15227 | { |
15228 | enum attr_type type = get_attr_type (insn); | |
15229 | if (type == TYPE_BRANCH || type == TYPE_JMPREG) | |
f676971a | 15230 | return true; |
cbe26ab8 DN |
15231 | return false; |
15232 | } | |
15233 | ||
15234 | return false; | |
15235 | } | |
79ae11c4 | 15236 | |
a4f6c312 | 15237 | /* A C statement (sans semicolon) to update the integer scheduling |
79ae11c4 DN |
15238 | priority INSN_PRIORITY (INSN). Increase the priority to execute the |
15239 | INSN earlier, reduce the priority to execute INSN later. Do not | |
a4f6c312 SS |
15240 | define this macro if you do not need to adjust the scheduling |
15241 | priorities of insns. */ | |
bef84347 | 15242 | |
c237e94a | 15243 | static int |
a2369ed3 | 15244 | rs6000_adjust_priority (rtx insn ATTRIBUTE_UNUSED, int priority) |
bef84347 | 15245 | { |
a4f6c312 SS |
15246 | /* On machines (like the 750) which have asymmetric integer units, |
15247 | where one integer unit can do multiply and divides and the other | |
15248 | can't, reduce the priority of multiply/divide so it is scheduled | |
15249 | before other integer operations. */ | |
bef84347 VM |
15250 | |
15251 | #if 0 | |
2c3c49de | 15252 | if (! INSN_P (insn)) |
bef84347 VM |
15253 | return priority; |
15254 | ||
15255 | if (GET_CODE (PATTERN (insn)) == USE) | |
15256 | return priority; | |
15257 | ||
15258 | switch (rs6000_cpu_attr) { | |
15259 | case CPU_PPC750: | |
15260 | switch (get_attr_type (insn)) | |
15261 | { | |
15262 | default: | |
15263 | break; | |
15264 | ||
15265 | case TYPE_IMUL: | |
15266 | case TYPE_IDIV: | |
3cb999d8 DE |
15267 | fprintf (stderr, "priority was %#x (%d) before adjustment\n", |
15268 | priority, priority); | |
bef84347 VM |
15269 | if (priority >= 0 && priority < 0x01000000) |
15270 | priority >>= 3; | |
15271 | break; | |
15272 | } | |
15273 | } | |
15274 | #endif | |
15275 | ||
79ae11c4 DN |
15276 | if (is_dispatch_slot_restricted (insn) |
15277 | && reload_completed | |
f676971a | 15278 | && current_sched_info->sched_max_insns_priority |
79ae11c4 DN |
15279 | && rs6000_sched_restricted_insns_priority) |
15280 | { | |
15281 | ||
c4ad648e AM |
15282 | /* Prioritize insns that can be dispatched only in the first |
15283 | dispatch slot. */ | |
79ae11c4 | 15284 | if (rs6000_sched_restricted_insns_priority == 1) |
f676971a EC |
15285 | /* Attach highest priority to insn. This means that in |
15286 | haifa-sched.c:ready_sort(), dispatch-slot restriction considerations | |
79ae11c4 | 15287 | precede 'priority' (critical path) considerations. */ |
f676971a | 15288 | return current_sched_info->sched_max_insns_priority; |
79ae11c4 | 15289 | else if (rs6000_sched_restricted_insns_priority == 2) |
f676971a | 15290 | /* Increase priority of insn by a minimal amount. This means that in |
c4ad648e AM |
15291 | haifa-sched.c:ready_sort(), only 'priority' (critical path) |
15292 | considerations precede dispatch-slot restriction considerations. */ | |
f676971a EC |
15293 | return (priority + 1); |
15294 | } | |
79ae11c4 | 15295 | |
bef84347 VM |
15296 | return priority; |
15297 | } | |
15298 | ||
a4f6c312 SS |
15299 | /* Return how many instructions the machine can issue per cycle. */ |
15300 | ||
c237e94a | 15301 | static int |
863d938c | 15302 | rs6000_issue_rate (void) |
b6c9286a | 15303 | { |
3317bab1 DE |
15304 | /* Use issue rate of 1 for first scheduling pass to decrease degradation. */ |
15305 | if (!reload_completed) | |
15306 | return 1; | |
15307 | ||
b6c9286a | 15308 | switch (rs6000_cpu_attr) { |
3cb999d8 DE |
15309 | case CPU_RIOS1: /* ? */ |
15310 | case CPU_RS64A: | |
15311 | case CPU_PPC601: /* ? */ | |
ed947a96 | 15312 | case CPU_PPC7450: |
3cb999d8 | 15313 | return 3; |
b54cf83a | 15314 | case CPU_PPC440: |
b6c9286a | 15315 | case CPU_PPC603: |
bef84347 | 15316 | case CPU_PPC750: |
ed947a96 | 15317 | case CPU_PPC7400: |
be12c2b0 | 15318 | case CPU_PPC8540: |
f676971a | 15319 | return 2; |
3cb999d8 | 15320 | case CPU_RIOS2: |
b6c9286a | 15321 | case CPU_PPC604: |
19684119 | 15322 | case CPU_PPC604E: |
b6c9286a | 15323 | case CPU_PPC620: |
3cb999d8 | 15324 | case CPU_PPC630: |
b6c9286a | 15325 | return 4; |
cbe26ab8 | 15326 | case CPU_POWER4: |
ec507f2d | 15327 | case CPU_POWER5: |
cbe26ab8 | 15328 | return 5; |
b6c9286a MM |
15329 | default: |
15330 | return 1; | |
15331 | } | |
15332 | } | |
15333 | ||
be12c2b0 VM |
15334 | /* Return how many instructions to look ahead for better insn |
15335 | scheduling. */ | |
15336 | ||
15337 | static int | |
863d938c | 15338 | rs6000_use_sched_lookahead (void) |
be12c2b0 VM |
15339 | { |
15340 | if (rs6000_cpu_attr == CPU_PPC8540) | |
15341 | return 4; | |
15342 | return 0; | |
15343 | } | |
15344 | ||
569fa502 DN |
15345 | /* Determine is PAT refers to memory. */ |
15346 | ||
15347 | static bool | |
15348 | is_mem_ref (rtx pat) | |
15349 | { | |
15350 | const char * fmt; | |
15351 | int i, j; | |
15352 | bool ret = false; | |
15353 | ||
15354 | if (GET_CODE (pat) == MEM) | |
15355 | return true; | |
15356 | ||
15357 | /* Recursively process the pattern. */ | |
15358 | fmt = GET_RTX_FORMAT (GET_CODE (pat)); | |
15359 | ||
15360 | for (i = GET_RTX_LENGTH (GET_CODE (pat)) - 1; i >= 0 && !ret; i--) | |
15361 | { | |
15362 | if (fmt[i] == 'e') | |
15363 | ret |= is_mem_ref (XEXP (pat, i)); | |
15364 | else if (fmt[i] == 'E') | |
15365 | for (j = XVECLEN (pat, i) - 1; j >= 0; j--) | |
15366 | ret |= is_mem_ref (XVECEXP (pat, i, j)); | |
15367 | } | |
15368 | ||
15369 | return ret; | |
15370 | } | |
15371 | ||
15372 | /* Determine if PAT is a PATTERN of a load insn. */ | |
f676971a | 15373 | |
569fa502 DN |
15374 | static bool |
15375 | is_load_insn1 (rtx pat) | |
15376 | { | |
15377 | if (!pat || pat == NULL_RTX) | |
15378 | return false; | |
15379 | ||
15380 | if (GET_CODE (pat) == SET) | |
15381 | return is_mem_ref (SET_SRC (pat)); | |
15382 | ||
15383 | if (GET_CODE (pat) == PARALLEL) | |
15384 | { | |
15385 | int i; | |
15386 | ||
15387 | for (i = 0; i < XVECLEN (pat, 0); i++) | |
15388 | if (is_load_insn1 (XVECEXP (pat, 0, i))) | |
15389 | return true; | |
15390 | } | |
15391 | ||
15392 | return false; | |
15393 | } | |
15394 | ||
15395 | /* Determine if INSN loads from memory. */ | |
15396 | ||
15397 | static bool | |
15398 | is_load_insn (rtx insn) | |
15399 | { | |
15400 | if (!insn || !INSN_P (insn)) | |
15401 | return false; | |
15402 | ||
15403 | if (GET_CODE (insn) == CALL_INSN) | |
15404 | return false; | |
15405 | ||
15406 | return is_load_insn1 (PATTERN (insn)); | |
15407 | } | |
15408 | ||
15409 | /* Determine if PAT is a PATTERN of a store insn. */ | |
15410 | ||
15411 | static bool | |
15412 | is_store_insn1 (rtx pat) | |
15413 | { | |
15414 | if (!pat || pat == NULL_RTX) | |
15415 | return false; | |
15416 | ||
15417 | if (GET_CODE (pat) == SET) | |
15418 | return is_mem_ref (SET_DEST (pat)); | |
15419 | ||
15420 | if (GET_CODE (pat) == PARALLEL) | |
15421 | { | |
15422 | int i; | |
15423 | ||
15424 | for (i = 0; i < XVECLEN (pat, 0); i++) | |
15425 | if (is_store_insn1 (XVECEXP (pat, 0, i))) | |
15426 | return true; | |
15427 | } | |
15428 | ||
15429 | return false; | |
15430 | } | |
15431 | ||
15432 | /* Determine if INSN stores to memory. */ | |
15433 | ||
15434 | static bool | |
15435 | is_store_insn (rtx insn) | |
15436 | { | |
15437 | if (!insn || !INSN_P (insn)) | |
15438 | return false; | |
15439 | ||
15440 | return is_store_insn1 (PATTERN (insn)); | |
15441 | } | |
15442 | ||
15443 | /* Returns whether the dependence between INSN and NEXT is considered | |
15444 | costly by the given target. */ | |
15445 | ||
15446 | static bool | |
c4ad648e AM |
15447 | rs6000_is_costly_dependence (rtx insn, rtx next, rtx link, int cost, |
15448 | int distance) | |
f676971a | 15449 | { |
aabcd309 | 15450 | /* If the flag is not enabled - no dependence is considered costly; |
f676971a | 15451 | allow all dependent insns in the same group. |
569fa502 DN |
15452 | This is the most aggressive option. */ |
15453 | if (rs6000_sched_costly_dep == no_dep_costly) | |
15454 | return false; | |
15455 | ||
f676971a | 15456 | /* If the flag is set to 1 - a dependence is always considered costly; |
569fa502 DN |
15457 | do not allow dependent instructions in the same group. |
15458 | This is the most conservative option. */ | |
15459 | if (rs6000_sched_costly_dep == all_deps_costly) | |
f676971a | 15460 | return true; |
569fa502 | 15461 | |
f676971a EC |
15462 | if (rs6000_sched_costly_dep == store_to_load_dep_costly |
15463 | && is_load_insn (next) | |
569fa502 DN |
15464 | && is_store_insn (insn)) |
15465 | /* Prevent load after store in the same group. */ | |
15466 | return true; | |
15467 | ||
15468 | if (rs6000_sched_costly_dep == true_store_to_load_dep_costly | |
f676971a | 15469 | && is_load_insn (next) |
569fa502 DN |
15470 | && is_store_insn (insn) |
15471 | && (!link || (int) REG_NOTE_KIND (link) == 0)) | |
c4ad648e AM |
15472 | /* Prevent load after store in the same group if it is a true |
15473 | dependence. */ | |
569fa502 | 15474 | return true; |
f676971a EC |
15475 | |
15476 | /* The flag is set to X; dependences with latency >= X are considered costly, | |
569fa502 DN |
15477 | and will not be scheduled in the same group. */ |
15478 | if (rs6000_sched_costly_dep <= max_dep_latency | |
15479 | && ((cost - distance) >= (int)rs6000_sched_costly_dep)) | |
15480 | return true; | |
15481 | ||
15482 | return false; | |
15483 | } | |
15484 | ||
f676971a | 15485 | /* Return the next insn after INSN that is found before TAIL is reached, |
cbe26ab8 DN |
15486 | skipping any "non-active" insns - insns that will not actually occupy |
15487 | an issue slot. Return NULL_RTX if such an insn is not found. */ | |
15488 | ||
15489 | static rtx | |
15490 | get_next_active_insn (rtx insn, rtx tail) | |
15491 | { | |
15492 | rtx next_insn; | |
15493 | ||
15494 | if (!insn || insn == tail) | |
15495 | return NULL_RTX; | |
15496 | ||
15497 | next_insn = NEXT_INSN (insn); | |
15498 | ||
15499 | while (next_insn | |
15500 | && next_insn != tail | |
9390387d | 15501 | && (GET_CODE (next_insn) == NOTE |
cbe26ab8 DN |
15502 | || GET_CODE (PATTERN (next_insn)) == USE |
15503 | || GET_CODE (PATTERN (next_insn)) == CLOBBER)) | |
15504 | { | |
15505 | next_insn = NEXT_INSN (next_insn); | |
15506 | } | |
15507 | ||
15508 | if (!next_insn || next_insn == tail) | |
15509 | return NULL_RTX; | |
15510 | ||
15511 | return next_insn; | |
15512 | } | |
15513 | ||
839a4992 | 15514 | /* Return whether the presence of INSN causes a dispatch group termination |
cbe26ab8 DN |
15515 | of group WHICH_GROUP. |
15516 | ||
15517 | If WHICH_GROUP == current_group, this function will return true if INSN | |
15518 | causes the termination of the current group (i.e, the dispatch group to | |
15519 | which INSN belongs). This means that INSN will be the last insn in the | |
15520 | group it belongs to. | |
15521 | ||
15522 | If WHICH_GROUP == previous_group, this function will return true if INSN | |
15523 | causes the termination of the previous group (i.e, the dispatch group that | |
15524 | precedes the group to which INSN belongs). This means that INSN will be | |
15525 | the first insn in the group it belongs to). */ | |
15526 | ||
15527 | static bool | |
15528 | insn_terminates_group_p (rtx insn, enum group_termination which_group) | |
15529 | { | |
15530 | enum attr_type type; | |
15531 | ||
15532 | if (! insn) | |
15533 | return false; | |
569fa502 | 15534 | |
cbe26ab8 DN |
15535 | type = get_attr_type (insn); |
15536 | ||
15537 | if (is_microcoded_insn (insn)) | |
15538 | return true; | |
15539 | ||
15540 | if (which_group == current_group) | |
15541 | { | |
15542 | if (is_branch_slot_insn (insn)) | |
c4ad648e | 15543 | return true; |
cbe26ab8 DN |
15544 | return false; |
15545 | } | |
15546 | else if (which_group == previous_group) | |
15547 | { | |
15548 | if (is_dispatch_slot_restricted (insn)) | |
c4ad648e | 15549 | return true; |
cbe26ab8 DN |
15550 | return false; |
15551 | } | |
15552 | ||
15553 | return false; | |
15554 | } | |
15555 | ||
839a4992 | 15556 | /* Return true if it is recommended to keep NEXT_INSN "far" (in a separate |
cbe26ab8 DN |
15557 | dispatch group) from the insns in GROUP_INSNS. Return false otherwise. */ |
15558 | ||
15559 | static bool | |
15560 | is_costly_group (rtx *group_insns, rtx next_insn) | |
15561 | { | |
15562 | int i; | |
15563 | rtx link; | |
15564 | int cost; | |
15565 | int issue_rate = rs6000_issue_rate (); | |
15566 | ||
15567 | for (i = 0; i < issue_rate; i++) | |
15568 | { | |
15569 | rtx insn = group_insns[i]; | |
15570 | if (!insn) | |
c4ad648e | 15571 | continue; |
cbe26ab8 | 15572 | for (link = INSN_DEPEND (insn); link != 0; link = XEXP (link, 1)) |
c4ad648e AM |
15573 | { |
15574 | rtx next = XEXP (link, 0); | |
15575 | if (next == next_insn) | |
15576 | { | |
15577 | cost = insn_cost (insn, link, next_insn); | |
15578 | if (rs6000_is_costly_dependence (insn, next_insn, link, cost, 0)) | |
15579 | return true; | |
15580 | } | |
15581 | } | |
cbe26ab8 DN |
15582 | } |
15583 | ||
15584 | return false; | |
15585 | } | |
15586 | ||
f676971a | 15587 | /* Utility of the function redefine_groups. |
cbe26ab8 DN |
15588 | Check if it is too costly to schedule NEXT_INSN together with GROUP_INSNS |
15589 | in the same dispatch group. If so, insert nops before NEXT_INSN, in order | |
15590 | to keep it "far" (in a separate group) from GROUP_INSNS, following | |
15591 | one of the following schemes, depending on the value of the flag | |
15592 | -minsert_sched_nops = X: | |
15593 | (1) X == sched_finish_regroup_exact: insert exactly as many nops as needed | |
839a4992 | 15594 | in order to force NEXT_INSN into a separate group. |
f676971a EC |
15595 | (2) X < sched_finish_regroup_exact: insert exactly X nops. |
15596 | GROUP_END, CAN_ISSUE_MORE and GROUP_COUNT record the state after nop | |
cbe26ab8 DN |
15597 | insertion (has a group just ended, how many vacant issue slots remain in the |
15598 | last group, and how many dispatch groups were encountered so far). */ | |
15599 | ||
f676971a | 15600 | static int |
c4ad648e AM |
15601 | force_new_group (int sched_verbose, FILE *dump, rtx *group_insns, |
15602 | rtx next_insn, bool *group_end, int can_issue_more, | |
15603 | int *group_count) | |
cbe26ab8 DN |
15604 | { |
15605 | rtx nop; | |
15606 | bool force; | |
15607 | int issue_rate = rs6000_issue_rate (); | |
15608 | bool end = *group_end; | |
15609 | int i; | |
15610 | ||
15611 | if (next_insn == NULL_RTX) | |
15612 | return can_issue_more; | |
15613 | ||
15614 | if (rs6000_sched_insert_nops > sched_finish_regroup_exact) | |
15615 | return can_issue_more; | |
15616 | ||
15617 | force = is_costly_group (group_insns, next_insn); | |
15618 | if (!force) | |
15619 | return can_issue_more; | |
15620 | ||
15621 | if (sched_verbose > 6) | |
15622 | fprintf (dump,"force: group count = %d, can_issue_more = %d\n", | |
c4ad648e | 15623 | *group_count ,can_issue_more); |
cbe26ab8 DN |
15624 | |
15625 | if (rs6000_sched_insert_nops == sched_finish_regroup_exact) | |
15626 | { | |
15627 | if (*group_end) | |
c4ad648e | 15628 | can_issue_more = 0; |
cbe26ab8 DN |
15629 | |
15630 | /* Since only a branch can be issued in the last issue_slot, it is | |
15631 | sufficient to insert 'can_issue_more - 1' nops if next_insn is not | |
15632 | a branch. If next_insn is a branch, we insert 'can_issue_more' nops; | |
c4ad648e AM |
15633 | in this case the last nop will start a new group and the branch |
15634 | will be forced to the new group. */ | |
cbe26ab8 | 15635 | if (can_issue_more && !is_branch_slot_insn (next_insn)) |
c4ad648e | 15636 | can_issue_more--; |
cbe26ab8 DN |
15637 | |
15638 | while (can_issue_more > 0) | |
c4ad648e | 15639 | { |
9390387d | 15640 | nop = gen_nop (); |
c4ad648e AM |
15641 | emit_insn_before (nop, next_insn); |
15642 | can_issue_more--; | |
15643 | } | |
cbe26ab8 DN |
15644 | |
15645 | *group_end = true; | |
15646 | return 0; | |
f676971a | 15647 | } |
cbe26ab8 DN |
15648 | |
15649 | if (rs6000_sched_insert_nops < sched_finish_regroup_exact) | |
15650 | { | |
15651 | int n_nops = rs6000_sched_insert_nops; | |
15652 | ||
f676971a | 15653 | /* Nops can't be issued from the branch slot, so the effective |
c4ad648e | 15654 | issue_rate for nops is 'issue_rate - 1'. */ |
cbe26ab8 | 15655 | if (can_issue_more == 0) |
c4ad648e | 15656 | can_issue_more = issue_rate; |
cbe26ab8 DN |
15657 | can_issue_more--; |
15658 | if (can_issue_more == 0) | |
c4ad648e AM |
15659 | { |
15660 | can_issue_more = issue_rate - 1; | |
15661 | (*group_count)++; | |
15662 | end = true; | |
15663 | for (i = 0; i < issue_rate; i++) | |
15664 | { | |
15665 | group_insns[i] = 0; | |
15666 | } | |
15667 | } | |
cbe26ab8 DN |
15668 | |
15669 | while (n_nops > 0) | |
c4ad648e AM |
15670 | { |
15671 | nop = gen_nop (); | |
15672 | emit_insn_before (nop, next_insn); | |
15673 | if (can_issue_more == issue_rate - 1) /* new group begins */ | |
15674 | end = false; | |
15675 | can_issue_more--; | |
15676 | if (can_issue_more == 0) | |
15677 | { | |
15678 | can_issue_more = issue_rate - 1; | |
15679 | (*group_count)++; | |
15680 | end = true; | |
15681 | for (i = 0; i < issue_rate; i++) | |
15682 | { | |
15683 | group_insns[i] = 0; | |
15684 | } | |
15685 | } | |
15686 | n_nops--; | |
15687 | } | |
cbe26ab8 DN |
15688 | |
15689 | /* Scale back relative to 'issue_rate' (instead of 'issue_rate - 1'). */ | |
f676971a | 15690 | can_issue_more++; |
cbe26ab8 | 15691 | |
c4ad648e AM |
15692 | /* Is next_insn going to start a new group? */ |
15693 | *group_end | |
15694 | = (end | |
cbe26ab8 DN |
15695 | || (can_issue_more == 1 && !is_branch_slot_insn (next_insn)) |
15696 | || (can_issue_more <= 2 && is_cracked_insn (next_insn)) | |
15697 | || (can_issue_more < issue_rate && | |
c4ad648e | 15698 | insn_terminates_group_p (next_insn, previous_group))); |
cbe26ab8 | 15699 | if (*group_end && end) |
c4ad648e | 15700 | (*group_count)--; |
cbe26ab8 DN |
15701 | |
15702 | if (sched_verbose > 6) | |
c4ad648e AM |
15703 | fprintf (dump, "done force: group count = %d, can_issue_more = %d\n", |
15704 | *group_count, can_issue_more); | |
f676971a EC |
15705 | return can_issue_more; |
15706 | } | |
cbe26ab8 DN |
15707 | |
15708 | return can_issue_more; | |
15709 | } | |
15710 | ||
15711 | /* This function tries to synch the dispatch groups that the compiler "sees" | |
f676971a | 15712 | with the dispatch groups that the processor dispatcher is expected to |
cbe26ab8 DN |
15713 | form in practice. It tries to achieve this synchronization by forcing the |
15714 | estimated processor grouping on the compiler (as opposed to the function | |
15715 | 'pad_goups' which tries to force the scheduler's grouping on the processor). | |
15716 | ||
15717 | The function scans the insn sequence between PREV_HEAD_INSN and TAIL and | |
15718 | examines the (estimated) dispatch groups that will be formed by the processor | |
15719 | dispatcher. It marks these group boundaries to reflect the estimated | |
15720 | processor grouping, overriding the grouping that the scheduler had marked. | |
15721 | Depending on the value of the flag '-minsert-sched-nops' this function can | |
15722 | force certain insns into separate groups or force a certain distance between | |
15723 | them by inserting nops, for example, if there exists a "costly dependence" | |
15724 | between the insns. | |
15725 | ||
15726 | The function estimates the group boundaries that the processor will form as | |
15727 | folllows: It keeps track of how many vacant issue slots are available after | |
15728 | each insn. A subsequent insn will start a new group if one of the following | |
15729 | 4 cases applies: | |
15730 | - no more vacant issue slots remain in the current dispatch group. | |
15731 | - only the last issue slot, which is the branch slot, is vacant, but the next | |
15732 | insn is not a branch. | |
15733 | - only the last 2 or less issue slots, including the branch slot, are vacant, | |
15734 | which means that a cracked insn (which occupies two issue slots) can't be | |
15735 | issued in this group. | |
f676971a | 15736 | - less than 'issue_rate' slots are vacant, and the next insn always needs to |
cbe26ab8 DN |
15737 | start a new group. */ |
15738 | ||
15739 | static int | |
15740 | redefine_groups (FILE *dump, int sched_verbose, rtx prev_head_insn, rtx tail) | |
15741 | { | |
15742 | rtx insn, next_insn; | |
15743 | int issue_rate; | |
15744 | int can_issue_more; | |
15745 | int slot, i; | |
15746 | bool group_end; | |
15747 | int group_count = 0; | |
15748 | rtx *group_insns; | |
15749 | ||
15750 | /* Initialize. */ | |
15751 | issue_rate = rs6000_issue_rate (); | |
15752 | group_insns = alloca (issue_rate * sizeof (rtx)); | |
f676971a | 15753 | for (i = 0; i < issue_rate; i++) |
cbe26ab8 DN |
15754 | { |
15755 | group_insns[i] = 0; | |
15756 | } | |
15757 | can_issue_more = issue_rate; | |
15758 | slot = 0; | |
15759 | insn = get_next_active_insn (prev_head_insn, tail); | |
15760 | group_end = false; | |
15761 | ||
15762 | while (insn != NULL_RTX) | |
15763 | { | |
15764 | slot = (issue_rate - can_issue_more); | |
15765 | group_insns[slot] = insn; | |
15766 | can_issue_more = | |
c4ad648e | 15767 | rs6000_variable_issue (dump, sched_verbose, insn, can_issue_more); |
cbe26ab8 | 15768 | if (insn_terminates_group_p (insn, current_group)) |
c4ad648e | 15769 | can_issue_more = 0; |
cbe26ab8 DN |
15770 | |
15771 | next_insn = get_next_active_insn (insn, tail); | |
15772 | if (next_insn == NULL_RTX) | |
c4ad648e | 15773 | return group_count + 1; |
cbe26ab8 | 15774 | |
c4ad648e AM |
15775 | /* Is next_insn going to start a new group? */ |
15776 | group_end | |
15777 | = (can_issue_more == 0 | |
15778 | || (can_issue_more == 1 && !is_branch_slot_insn (next_insn)) | |
15779 | || (can_issue_more <= 2 && is_cracked_insn (next_insn)) | |
15780 | || (can_issue_more < issue_rate && | |
15781 | insn_terminates_group_p (next_insn, previous_group))); | |
cbe26ab8 | 15782 | |
f676971a | 15783 | can_issue_more = force_new_group (sched_verbose, dump, group_insns, |
c4ad648e AM |
15784 | next_insn, &group_end, can_issue_more, |
15785 | &group_count); | |
cbe26ab8 DN |
15786 | |
15787 | if (group_end) | |
c4ad648e AM |
15788 | { |
15789 | group_count++; | |
15790 | can_issue_more = 0; | |
15791 | for (i = 0; i < issue_rate; i++) | |
15792 | { | |
15793 | group_insns[i] = 0; | |
15794 | } | |
15795 | } | |
cbe26ab8 DN |
15796 | |
15797 | if (GET_MODE (next_insn) == TImode && can_issue_more) | |
9390387d | 15798 | PUT_MODE (next_insn, VOIDmode); |
cbe26ab8 | 15799 | else if (!can_issue_more && GET_MODE (next_insn) != TImode) |
c4ad648e | 15800 | PUT_MODE (next_insn, TImode); |
cbe26ab8 DN |
15801 | |
15802 | insn = next_insn; | |
15803 | if (can_issue_more == 0) | |
c4ad648e AM |
15804 | can_issue_more = issue_rate; |
15805 | } /* while */ | |
cbe26ab8 DN |
15806 | |
15807 | return group_count; | |
15808 | } | |
15809 | ||
15810 | /* Scan the insn sequence between PREV_HEAD_INSN and TAIL and examine the | |
15811 | dispatch group boundaries that the scheduler had marked. Pad with nops | |
15812 | any dispatch groups which have vacant issue slots, in order to force the | |
15813 | scheduler's grouping on the processor dispatcher. The function | |
15814 | returns the number of dispatch groups found. */ | |
15815 | ||
15816 | static int | |
15817 | pad_groups (FILE *dump, int sched_verbose, rtx prev_head_insn, rtx tail) | |
15818 | { | |
15819 | rtx insn, next_insn; | |
15820 | rtx nop; | |
15821 | int issue_rate; | |
15822 | int can_issue_more; | |
15823 | int group_end; | |
15824 | int group_count = 0; | |
15825 | ||
15826 | /* Initialize issue_rate. */ | |
15827 | issue_rate = rs6000_issue_rate (); | |
15828 | can_issue_more = issue_rate; | |
15829 | ||
15830 | insn = get_next_active_insn (prev_head_insn, tail); | |
15831 | next_insn = get_next_active_insn (insn, tail); | |
15832 | ||
15833 | while (insn != NULL_RTX) | |
15834 | { | |
15835 | can_issue_more = | |
15836 | rs6000_variable_issue (dump, sched_verbose, insn, can_issue_more); | |
15837 | ||
15838 | group_end = (next_insn == NULL_RTX || GET_MODE (next_insn) == TImode); | |
15839 | ||
15840 | if (next_insn == NULL_RTX) | |
c4ad648e | 15841 | break; |
cbe26ab8 DN |
15842 | |
15843 | if (group_end) | |
c4ad648e AM |
15844 | { |
15845 | /* If the scheduler had marked group termination at this location | |
15846 | (between insn and next_indn), and neither insn nor next_insn will | |
15847 | force group termination, pad the group with nops to force group | |
15848 | termination. */ | |
15849 | if (can_issue_more | |
15850 | && (rs6000_sched_insert_nops == sched_finish_pad_groups) | |
15851 | && !insn_terminates_group_p (insn, current_group) | |
15852 | && !insn_terminates_group_p (next_insn, previous_group)) | |
15853 | { | |
9390387d | 15854 | if (!is_branch_slot_insn (next_insn)) |
c4ad648e AM |
15855 | can_issue_more--; |
15856 | ||
15857 | while (can_issue_more) | |
15858 | { | |
15859 | nop = gen_nop (); | |
15860 | emit_insn_before (nop, next_insn); | |
15861 | can_issue_more--; | |
15862 | } | |
15863 | } | |
15864 | ||
15865 | can_issue_more = issue_rate; | |
15866 | group_count++; | |
15867 | } | |
cbe26ab8 DN |
15868 | |
15869 | insn = next_insn; | |
15870 | next_insn = get_next_active_insn (insn, tail); | |
15871 | } | |
15872 | ||
15873 | return group_count; | |
15874 | } | |
15875 | ||
15876 | /* The following function is called at the end of scheduling BB. | |
15877 | After reload, it inserts nops at insn group bundling. */ | |
15878 | ||
15879 | static void | |
38f391a5 | 15880 | rs6000_sched_finish (FILE *dump, int sched_verbose) |
cbe26ab8 DN |
15881 | { |
15882 | int n_groups; | |
15883 | ||
15884 | if (sched_verbose) | |
15885 | fprintf (dump, "=== Finishing schedule.\n"); | |
15886 | ||
ec507f2d | 15887 | if (reload_completed && rs6000_sched_groups) |
cbe26ab8 DN |
15888 | { |
15889 | if (rs6000_sched_insert_nops == sched_finish_none) | |
c4ad648e | 15890 | return; |
cbe26ab8 DN |
15891 | |
15892 | if (rs6000_sched_insert_nops == sched_finish_pad_groups) | |
c4ad648e AM |
15893 | n_groups = pad_groups (dump, sched_verbose, |
15894 | current_sched_info->prev_head, | |
15895 | current_sched_info->next_tail); | |
cbe26ab8 | 15896 | else |
c4ad648e AM |
15897 | n_groups = redefine_groups (dump, sched_verbose, |
15898 | current_sched_info->prev_head, | |
15899 | current_sched_info->next_tail); | |
cbe26ab8 DN |
15900 | |
15901 | if (sched_verbose >= 6) | |
15902 | { | |
15903 | fprintf (dump, "ngroups = %d\n", n_groups); | |
15904 | print_rtl (dump, current_sched_info->prev_head); | |
15905 | fprintf (dump, "Done finish_sched\n"); | |
15906 | } | |
15907 | } | |
15908 | } | |
b6c9286a | 15909 | \f |
b6c9286a MM |
15910 | /* Length in units of the trampoline for entering a nested function. */ |
15911 | ||
15912 | int | |
863d938c | 15913 | rs6000_trampoline_size (void) |
b6c9286a MM |
15914 | { |
15915 | int ret = 0; | |
15916 | ||
15917 | switch (DEFAULT_ABI) | |
15918 | { | |
15919 | default: | |
37409796 | 15920 | gcc_unreachable (); |
b6c9286a MM |
15921 | |
15922 | case ABI_AIX: | |
8f802bfb | 15923 | ret = (TARGET_32BIT) ? 12 : 24; |
b6c9286a MM |
15924 | break; |
15925 | ||
4dabc42d | 15926 | case ABI_DARWIN: |
b6c9286a | 15927 | case ABI_V4: |
03a7e1a5 | 15928 | ret = (TARGET_32BIT) ? 40 : 48; |
b6c9286a | 15929 | break; |
b6c9286a MM |
15930 | } |
15931 | ||
15932 | return ret; | |
15933 | } | |
15934 | ||
15935 | /* Emit RTL insns to initialize the variable parts of a trampoline. | |
15936 | FNADDR is an RTX for the address of the function's pure code. | |
15937 | CXT is an RTX for the static chain value for the function. */ | |
15938 | ||
15939 | void | |
a2369ed3 | 15940 | rs6000_initialize_trampoline (rtx addr, rtx fnaddr, rtx cxt) |
b6c9286a | 15941 | { |
ac2a93a1 | 15942 | enum machine_mode pmode = Pmode; |
8bd04c56 MM |
15943 | int regsize = (TARGET_32BIT) ? 4 : 8; |
15944 | rtx ctx_reg = force_reg (pmode, cxt); | |
b6c9286a MM |
15945 | |
15946 | switch (DEFAULT_ABI) | |
15947 | { | |
15948 | default: | |
37409796 | 15949 | gcc_unreachable (); |
b6c9286a | 15950 | |
8bd04c56 | 15951 | /* Macros to shorten the code expansions below. */ |
39403d82 | 15952 | #define MEM_DEREF(addr) gen_rtx_MEM (pmode, memory_address (pmode, addr)) |
c5c76735 JL |
15953 | #define MEM_PLUS(addr,offset) \ |
15954 | gen_rtx_MEM (pmode, memory_address (pmode, plus_constant (addr, offset))) | |
7c59dc5d | 15955 | |
b6c9286a MM |
15956 | /* Under AIX, just build the 3 word function descriptor */ |
15957 | case ABI_AIX: | |
8bd04c56 MM |
15958 | { |
15959 | rtx fn_reg = gen_reg_rtx (pmode); | |
15960 | rtx toc_reg = gen_reg_rtx (pmode); | |
15961 | emit_move_insn (fn_reg, MEM_DEREF (fnaddr)); | |
1cb18e3c | 15962 | emit_move_insn (toc_reg, MEM_PLUS (fnaddr, regsize)); |
8bd04c56 MM |
15963 | emit_move_insn (MEM_DEREF (addr), fn_reg); |
15964 | emit_move_insn (MEM_PLUS (addr, regsize), toc_reg); | |
15965 | emit_move_insn (MEM_PLUS (addr, 2*regsize), ctx_reg); | |
15966 | } | |
b6c9286a MM |
15967 | break; |
15968 | ||
4dabc42d TC |
15969 | /* Under V.4/eabi/darwin, __trampoline_setup does the real work. */ |
15970 | case ABI_DARWIN: | |
b6c9286a | 15971 | case ABI_V4: |
39403d82 | 15972 | emit_library_call (gen_rtx_SYMBOL_REF (SImode, "__trampoline_setup"), |
eaf1bcf1 MM |
15973 | FALSE, VOIDmode, 4, |
15974 | addr, pmode, | |
15975 | GEN_INT (rs6000_trampoline_size ()), SImode, | |
15976 | fnaddr, pmode, | |
15977 | ctx_reg, pmode); | |
b6c9286a | 15978 | break; |
b6c9286a MM |
15979 | } |
15980 | ||
15981 | return; | |
15982 | } | |
7509c759 MM |
15983 | |
15984 | \f | |
91d231cb | 15985 | /* Table of valid machine attributes. */ |
a4f6c312 | 15986 | |
91d231cb | 15987 | const struct attribute_spec rs6000_attribute_table[] = |
7509c759 | 15988 | { |
91d231cb | 15989 | /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */ |
8bb418a3 | 15990 | { "altivec", 1, 1, false, true, false, rs6000_handle_altivec_attribute }, |
a5c76ee6 ZW |
15991 | { "longcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute }, |
15992 | { "shortcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute }, | |
005c1a13 GK |
15993 | #ifdef SUBTARGET_ATTRIBUTE_TABLE |
15994 | SUBTARGET_ATTRIBUTE_TABLE, | |
15995 | #endif | |
a5c76ee6 | 15996 | { NULL, 0, 0, false, false, false, NULL } |
91d231cb | 15997 | }; |
7509c759 | 15998 | |
8bb418a3 ZL |
15999 | /* Handle the "altivec" attribute. The attribute may have |
16000 | arguments as follows: | |
f676971a | 16001 | |
8bb418a3 ZL |
16002 | __attribute__((altivec(vector__))) |
16003 | __attribute__((altivec(pixel__))) (always followed by 'unsigned short') | |
16004 | __attribute__((altivec(bool__))) (always followed by 'unsigned') | |
16005 | ||
16006 | and may appear more than once (e.g., 'vector bool char') in a | |
16007 | given declaration. */ | |
16008 | ||
16009 | static tree | |
f90ac3f0 UP |
16010 | rs6000_handle_altivec_attribute (tree *node, |
16011 | tree name ATTRIBUTE_UNUSED, | |
16012 | tree args, | |
8bb418a3 ZL |
16013 | int flags ATTRIBUTE_UNUSED, |
16014 | bool *no_add_attrs) | |
16015 | { | |
16016 | tree type = *node, result = NULL_TREE; | |
16017 | enum machine_mode mode; | |
16018 | int unsigned_p; | |
16019 | char altivec_type | |
16020 | = ((args && TREE_CODE (args) == TREE_LIST && TREE_VALUE (args) | |
16021 | && TREE_CODE (TREE_VALUE (args)) == IDENTIFIER_NODE) | |
16022 | ? *IDENTIFIER_POINTER (TREE_VALUE (args)) | |
f676971a | 16023 | : '?'); |
8bb418a3 ZL |
16024 | |
16025 | while (POINTER_TYPE_P (type) | |
16026 | || TREE_CODE (type) == FUNCTION_TYPE | |
16027 | || TREE_CODE (type) == METHOD_TYPE | |
16028 | || TREE_CODE (type) == ARRAY_TYPE) | |
16029 | type = TREE_TYPE (type); | |
16030 | ||
16031 | mode = TYPE_MODE (type); | |
16032 | ||
f90ac3f0 UP |
16033 | /* Check for invalid AltiVec type qualifiers. */ |
16034 | if (type == long_unsigned_type_node || type == long_integer_type_node) | |
16035 | { | |
16036 | if (TARGET_64BIT) | |
16037 | error ("use of %<long%> in AltiVec types is invalid for 64-bit code"); | |
16038 | else if (rs6000_warn_altivec_long) | |
d4ee4d25 | 16039 | warning (0, "use of %<long%> in AltiVec types is deprecated; use %<int%>"); |
f90ac3f0 UP |
16040 | } |
16041 | else if (type == long_long_unsigned_type_node | |
16042 | || type == long_long_integer_type_node) | |
16043 | error ("use of %<long long%> in AltiVec types is invalid"); | |
16044 | else if (type == double_type_node) | |
16045 | error ("use of %<double%> in AltiVec types is invalid"); | |
16046 | else if (type == long_double_type_node) | |
16047 | error ("use of %<long double%> in AltiVec types is invalid"); | |
16048 | else if (type == boolean_type_node) | |
16049 | error ("use of boolean types in AltiVec types is invalid"); | |
16050 | else if (TREE_CODE (type) == COMPLEX_TYPE) | |
16051 | error ("use of %<complex%> in AltiVec types is invalid"); | |
8bb418a3 ZL |
16052 | |
16053 | switch (altivec_type) | |
16054 | { | |
16055 | case 'v': | |
8df83eae | 16056 | unsigned_p = TYPE_UNSIGNED (type); |
8bb418a3 ZL |
16057 | switch (mode) |
16058 | { | |
c4ad648e AM |
16059 | case SImode: |
16060 | result = (unsigned_p ? unsigned_V4SI_type_node : V4SI_type_node); | |
16061 | break; | |
16062 | case HImode: | |
16063 | result = (unsigned_p ? unsigned_V8HI_type_node : V8HI_type_node); | |
16064 | break; | |
16065 | case QImode: | |
16066 | result = (unsigned_p ? unsigned_V16QI_type_node : V16QI_type_node); | |
16067 | break; | |
16068 | case SFmode: result = V4SF_type_node; break; | |
16069 | /* If the user says 'vector int bool', we may be handed the 'bool' | |
16070 | attribute _before_ the 'vector' attribute, and so select the | |
16071 | proper type in the 'b' case below. */ | |
16072 | case V4SImode: case V8HImode: case V16QImode: case V4SFmode: | |
16073 | result = type; | |
16074 | default: break; | |
8bb418a3 ZL |
16075 | } |
16076 | break; | |
16077 | case 'b': | |
16078 | switch (mode) | |
16079 | { | |
c4ad648e AM |
16080 | case SImode: case V4SImode: result = bool_V4SI_type_node; break; |
16081 | case HImode: case V8HImode: result = bool_V8HI_type_node; break; | |
16082 | case QImode: case V16QImode: result = bool_V16QI_type_node; | |
16083 | default: break; | |
8bb418a3 ZL |
16084 | } |
16085 | break; | |
16086 | case 'p': | |
16087 | switch (mode) | |
16088 | { | |
c4ad648e AM |
16089 | case V8HImode: result = pixel_V8HI_type_node; |
16090 | default: break; | |
8bb418a3 ZL |
16091 | } |
16092 | default: break; | |
16093 | } | |
16094 | ||
7958a2a6 FJ |
16095 | if (result && result != type && TYPE_READONLY (type)) |
16096 | result = build_qualified_type (result, TYPE_QUAL_CONST); | |
16097 | ||
8bb418a3 ZL |
16098 | *no_add_attrs = true; /* No need to hang on to the attribute. */ |
16099 | ||
f90ac3f0 | 16100 | if (result) |
8bb418a3 ZL |
16101 | *node = reconstruct_complex_type (*node, result); |
16102 | ||
16103 | return NULL_TREE; | |
16104 | } | |
16105 | ||
f18eca82 ZL |
16106 | /* AltiVec defines four built-in scalar types that serve as vector |
16107 | elements; we must teach the compiler how to mangle them. */ | |
16108 | ||
16109 | static const char * | |
16110 | rs6000_mangle_fundamental_type (tree type) | |
16111 | { | |
16112 | if (type == bool_char_type_node) return "U6__boolc"; | |
16113 | if (type == bool_short_type_node) return "U6__bools"; | |
16114 | if (type == pixel_type_node) return "u7__pixel"; | |
16115 | if (type == bool_int_type_node) return "U6__booli"; | |
16116 | ||
16117 | /* For all other types, use normal C++ mangling. */ | |
16118 | return NULL; | |
16119 | } | |
16120 | ||
a5c76ee6 ZW |
16121 | /* Handle a "longcall" or "shortcall" attribute; arguments as in |
16122 | struct attribute_spec.handler. */ | |
a4f6c312 | 16123 | |
91d231cb | 16124 | static tree |
f676971a EC |
16125 | rs6000_handle_longcall_attribute (tree *node, tree name, |
16126 | tree args ATTRIBUTE_UNUSED, | |
16127 | int flags ATTRIBUTE_UNUSED, | |
a2369ed3 | 16128 | bool *no_add_attrs) |
91d231cb JM |
16129 | { |
16130 | if (TREE_CODE (*node) != FUNCTION_TYPE | |
16131 | && TREE_CODE (*node) != FIELD_DECL | |
16132 | && TREE_CODE (*node) != TYPE_DECL) | |
16133 | { | |
d4ee4d25 | 16134 | warning (0, "%qs attribute only applies to functions", |
91d231cb JM |
16135 | IDENTIFIER_POINTER (name)); |
16136 | *no_add_attrs = true; | |
16137 | } | |
6a4cee5f | 16138 | |
91d231cb | 16139 | return NULL_TREE; |
7509c759 MM |
16140 | } |
16141 | ||
a5c76ee6 ZW |
16142 | /* Set longcall attributes on all functions declared when |
16143 | rs6000_default_long_calls is true. */ | |
16144 | static void | |
a2369ed3 | 16145 | rs6000_set_default_type_attributes (tree type) |
a5c76ee6 ZW |
16146 | { |
16147 | if (rs6000_default_long_calls | |
16148 | && (TREE_CODE (type) == FUNCTION_TYPE | |
16149 | || TREE_CODE (type) == METHOD_TYPE)) | |
16150 | TYPE_ATTRIBUTES (type) = tree_cons (get_identifier ("longcall"), | |
16151 | NULL_TREE, | |
16152 | TYPE_ATTRIBUTES (type)); | |
16153 | } | |
16154 | ||
3cb999d8 DE |
16155 | /* Return a reference suitable for calling a function with the |
16156 | longcall attribute. */ | |
a4f6c312 | 16157 | |
9390387d | 16158 | rtx |
a2369ed3 | 16159 | rs6000_longcall_ref (rtx call_ref) |
6a4cee5f | 16160 | { |
d330fd93 | 16161 | const char *call_name; |
6a4cee5f MM |
16162 | tree node; |
16163 | ||
16164 | if (GET_CODE (call_ref) != SYMBOL_REF) | |
16165 | return call_ref; | |
16166 | ||
16167 | /* System V adds '.' to the internal name, so skip them. */ | |
16168 | call_name = XSTR (call_ref, 0); | |
16169 | if (*call_name == '.') | |
16170 | { | |
16171 | while (*call_name == '.') | |
16172 | call_name++; | |
16173 | ||
16174 | node = get_identifier (call_name); | |
39403d82 | 16175 | call_ref = gen_rtx_SYMBOL_REF (VOIDmode, IDENTIFIER_POINTER (node)); |
6a4cee5f MM |
16176 | } |
16177 | ||
16178 | return force_reg (Pmode, call_ref); | |
16179 | } | |
7509c759 | 16180 | \f |
b64a1b53 RH |
16181 | #ifdef USING_ELFOS_H |
16182 | ||
7509c759 MM |
16183 | /* A C statement or statements to switch to the appropriate section |
16184 | for output of RTX in mode MODE. You can assume that RTX is some | |
16185 | kind of constant in RTL. The argument MODE is redundant except in | |
16186 | the case of a `const_int' rtx. Select the section by calling | |
16187 | `text_section' or one of the alternatives for other sections. | |
16188 | ||
16189 | Do not define this macro if you put all constants in the read-only | |
16190 | data section. */ | |
16191 | ||
b64a1b53 | 16192 | static void |
f676971a | 16193 | rs6000_elf_select_rtx_section (enum machine_mode mode, rtx x, |
a2369ed3 | 16194 | unsigned HOST_WIDE_INT align) |
7509c759 | 16195 | { |
a9098fd0 | 16196 | if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode)) |
7509c759 | 16197 | toc_section (); |
7509c759 | 16198 | else |
b64a1b53 | 16199 | default_elf_select_rtx_section (mode, x, align); |
7509c759 MM |
16200 | } |
16201 | ||
16202 | /* A C statement or statements to switch to the appropriate | |
16203 | section for output of DECL. DECL is either a `VAR_DECL' node | |
16204 | or a constant of some sort. RELOC indicates whether forming | |
16205 | the initial value of DECL requires link-time relocations. */ | |
16206 | ||
ae46c4e0 | 16207 | static void |
f676971a | 16208 | rs6000_elf_select_section (tree decl, int reloc, |
a2369ed3 | 16209 | unsigned HOST_WIDE_INT align) |
7509c759 | 16210 | { |
f1384257 AM |
16211 | /* Pretend that we're always building for a shared library when |
16212 | ABI_AIX, because otherwise we end up with dynamic relocations | |
16213 | in read-only sections. This happens for function pointers, | |
16214 | references to vtables in typeinfo, and probably other cases. */ | |
0e5dbd9b DE |
16215 | default_elf_select_section_1 (decl, reloc, align, |
16216 | flag_pic || DEFAULT_ABI == ABI_AIX); | |
63019373 GK |
16217 | } |
16218 | ||
16219 | /* A C statement to build up a unique section name, expressed as a | |
16220 | STRING_CST node, and assign it to DECL_SECTION_NAME (decl). | |
16221 | RELOC indicates whether the initial value of EXP requires | |
16222 | link-time relocations. If you do not define this macro, GCC will use | |
16223 | the symbol name prefixed by `.' as the section name. Note - this | |
f5143c46 | 16224 | macro can now be called for uninitialized data items as well as |
4912a07c | 16225 | initialized data and functions. */ |
63019373 | 16226 | |
ae46c4e0 | 16227 | static void |
a2369ed3 | 16228 | rs6000_elf_unique_section (tree decl, int reloc) |
63019373 | 16229 | { |
f1384257 AM |
16230 | /* As above, pretend that we're always building for a shared library |
16231 | when ABI_AIX, to avoid dynamic relocations in read-only sections. */ | |
0e5dbd9b DE |
16232 | default_unique_section_1 (decl, reloc, |
16233 | flag_pic || DEFAULT_ABI == ABI_AIX); | |
7509c759 | 16234 | } |
d9407988 | 16235 | \f |
d1908feb JJ |
16236 | /* For a SYMBOL_REF, set generic flags and then perform some |
16237 | target-specific processing. | |
16238 | ||
d1908feb JJ |
16239 | When the AIX ABI is requested on a non-AIX system, replace the |
16240 | function name with the real name (with a leading .) rather than the | |
16241 | function descriptor name. This saves a lot of overriding code to | |
16242 | read the prefixes. */ | |
d9407988 | 16243 | |
fb49053f | 16244 | static void |
a2369ed3 | 16245 | rs6000_elf_encode_section_info (tree decl, rtx rtl, int first) |
d9407988 | 16246 | { |
d1908feb | 16247 | default_encode_section_info (decl, rtl, first); |
b2003250 | 16248 | |
d1908feb JJ |
16249 | if (first |
16250 | && TREE_CODE (decl) == FUNCTION_DECL | |
16251 | && !TARGET_AIX | |
16252 | && DEFAULT_ABI == ABI_AIX) | |
d9407988 | 16253 | { |
c6a2438a | 16254 | rtx sym_ref = XEXP (rtl, 0); |
d1908feb JJ |
16255 | size_t len = strlen (XSTR (sym_ref, 0)); |
16256 | char *str = alloca (len + 2); | |
16257 | str[0] = '.'; | |
16258 | memcpy (str + 1, XSTR (sym_ref, 0), len + 1); | |
16259 | XSTR (sym_ref, 0) = ggc_alloc_string (str, len + 1); | |
d9407988 | 16260 | } |
d9407988 MM |
16261 | } |
16262 | ||
0e5dbd9b | 16263 | static bool |
a2369ed3 | 16264 | rs6000_elf_in_small_data_p (tree decl) |
0e5dbd9b DE |
16265 | { |
16266 | if (rs6000_sdata == SDATA_NONE) | |
16267 | return false; | |
16268 | ||
7482ad25 AF |
16269 | /* We want to merge strings, so we never consider them small data. */ |
16270 | if (TREE_CODE (decl) == STRING_CST) | |
16271 | return false; | |
16272 | ||
16273 | /* Functions are never in the small data area. */ | |
16274 | if (TREE_CODE (decl) == FUNCTION_DECL) | |
16275 | return false; | |
16276 | ||
0e5dbd9b DE |
16277 | if (TREE_CODE (decl) == VAR_DECL && DECL_SECTION_NAME (decl)) |
16278 | { | |
16279 | const char *section = TREE_STRING_POINTER (DECL_SECTION_NAME (decl)); | |
16280 | if (strcmp (section, ".sdata") == 0 | |
16281 | || strcmp (section, ".sdata2") == 0 | |
20bfcd69 GK |
16282 | || strcmp (section, ".sbss") == 0 |
16283 | || strcmp (section, ".sbss2") == 0 | |
16284 | || strcmp (section, ".PPC.EMB.sdata0") == 0 | |
16285 | || strcmp (section, ".PPC.EMB.sbss0") == 0) | |
0e5dbd9b DE |
16286 | return true; |
16287 | } | |
16288 | else | |
16289 | { | |
16290 | HOST_WIDE_INT size = int_size_in_bytes (TREE_TYPE (decl)); | |
16291 | ||
16292 | if (size > 0 | |
307b599c | 16293 | && (unsigned HOST_WIDE_INT) size <= g_switch_value |
20bfcd69 GK |
16294 | /* If it's not public, and we're not going to reference it there, |
16295 | there's no need to put it in the small data section. */ | |
0e5dbd9b DE |
16296 | && (rs6000_sdata != SDATA_DATA || TREE_PUBLIC (decl))) |
16297 | return true; | |
16298 | } | |
16299 | ||
16300 | return false; | |
16301 | } | |
16302 | ||
b91da81f | 16303 | #endif /* USING_ELFOS_H */ |
000034eb | 16304 | |
a6c2a102 | 16305 | \f |
000034eb | 16306 | /* Return a REG that occurs in ADDR with coefficient 1. |
02441cd6 JL |
16307 | ADDR can be effectively incremented by incrementing REG. |
16308 | ||
16309 | r0 is special and we must not select it as an address | |
16310 | register by this routine since our caller will try to | |
16311 | increment the returned register via an "la" instruction. */ | |
000034eb | 16312 | |
9390387d | 16313 | rtx |
a2369ed3 | 16314 | find_addr_reg (rtx addr) |
000034eb DE |
16315 | { |
16316 | while (GET_CODE (addr) == PLUS) | |
16317 | { | |
02441cd6 JL |
16318 | if (GET_CODE (XEXP (addr, 0)) == REG |
16319 | && REGNO (XEXP (addr, 0)) != 0) | |
000034eb | 16320 | addr = XEXP (addr, 0); |
02441cd6 JL |
16321 | else if (GET_CODE (XEXP (addr, 1)) == REG |
16322 | && REGNO (XEXP (addr, 1)) != 0) | |
000034eb DE |
16323 | addr = XEXP (addr, 1); |
16324 | else if (CONSTANT_P (XEXP (addr, 0))) | |
16325 | addr = XEXP (addr, 1); | |
16326 | else if (CONSTANT_P (XEXP (addr, 1))) | |
16327 | addr = XEXP (addr, 0); | |
16328 | else | |
37409796 | 16329 | gcc_unreachable (); |
000034eb | 16330 | } |
37409796 NS |
16331 | gcc_assert (GET_CODE (addr) == REG && REGNO (addr) != 0); |
16332 | return addr; | |
000034eb DE |
16333 | } |
16334 | ||
a6c2a102 | 16335 | void |
a2369ed3 | 16336 | rs6000_fatal_bad_address (rtx op) |
a6c2a102 DE |
16337 | { |
16338 | fatal_insn ("bad address", op); | |
16339 | } | |
c8023011 | 16340 | |
ee890fe2 SS |
16341 | #if TARGET_MACHO |
16342 | ||
efdba735 | 16343 | static tree branch_island_list = 0; |
ee890fe2 | 16344 | |
efdba735 SH |
16345 | /* Remember to generate a branch island for far calls to the given |
16346 | function. */ | |
ee890fe2 | 16347 | |
f676971a | 16348 | static void |
c4ad648e AM |
16349 | add_compiler_branch_island (tree label_name, tree function_name, |
16350 | int line_number) | |
ee890fe2 | 16351 | { |
efdba735 | 16352 | tree branch_island = build_tree_list (function_name, label_name); |
7d60be94 | 16353 | TREE_TYPE (branch_island) = build_int_cst (NULL_TREE, line_number); |
efdba735 SH |
16354 | TREE_CHAIN (branch_island) = branch_island_list; |
16355 | branch_island_list = branch_island; | |
ee890fe2 SS |
16356 | } |
16357 | ||
efdba735 SH |
16358 | #define BRANCH_ISLAND_LABEL_NAME(BRANCH_ISLAND) TREE_VALUE (BRANCH_ISLAND) |
16359 | #define BRANCH_ISLAND_FUNCTION_NAME(BRANCH_ISLAND) TREE_PURPOSE (BRANCH_ISLAND) | |
16360 | #define BRANCH_ISLAND_LINE_NUMBER(BRANCH_ISLAND) \ | |
16361 | TREE_INT_CST_LOW (TREE_TYPE (BRANCH_ISLAND)) | |
ee890fe2 | 16362 | |
efdba735 SH |
16363 | /* Generate far-jump branch islands for everything on the |
16364 | branch_island_list. Invoked immediately after the last instruction | |
16365 | of the epilogue has been emitted; the branch-islands must be | |
16366 | appended to, and contiguous with, the function body. Mach-O stubs | |
16367 | are generated in machopic_output_stub(). */ | |
ee890fe2 | 16368 | |
efdba735 SH |
16369 | static void |
16370 | macho_branch_islands (void) | |
16371 | { | |
16372 | char tmp_buf[512]; | |
16373 | tree branch_island; | |
16374 | ||
16375 | for (branch_island = branch_island_list; | |
16376 | branch_island; | |
16377 | branch_island = TREE_CHAIN (branch_island)) | |
16378 | { | |
16379 | const char *label = | |
16380 | IDENTIFIER_POINTER (BRANCH_ISLAND_LABEL_NAME (branch_island)); | |
16381 | const char *name = | |
11abc112 | 16382 | IDENTIFIER_POINTER (BRANCH_ISLAND_FUNCTION_NAME (branch_island)); |
efdba735 SH |
16383 | char name_buf[512]; |
16384 | /* Cheap copy of the details from the Darwin ASM_OUTPUT_LABELREF(). */ | |
16385 | if (name[0] == '*' || name[0] == '&') | |
16386 | strcpy (name_buf, name+1); | |
16387 | else | |
16388 | { | |
16389 | name_buf[0] = '_'; | |
16390 | strcpy (name_buf+1, name); | |
16391 | } | |
16392 | strcpy (tmp_buf, "\n"); | |
16393 | strcat (tmp_buf, label); | |
ee890fe2 | 16394 | #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO) |
efdba735 | 16395 | if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG) |
93a27b7b | 16396 | dbxout_stabd (N_SLINE, BRANCH_ISLAND_LINE_NUMBER (branch_island)); |
ee890fe2 | 16397 | #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */ |
efdba735 SH |
16398 | if (flag_pic) |
16399 | { | |
16400 | strcat (tmp_buf, ":\n\tmflr r0\n\tbcl 20,31,"); | |
16401 | strcat (tmp_buf, label); | |
16402 | strcat (tmp_buf, "_pic\n"); | |
16403 | strcat (tmp_buf, label); | |
16404 | strcat (tmp_buf, "_pic:\n\tmflr r11\n"); | |
f676971a | 16405 | |
efdba735 SH |
16406 | strcat (tmp_buf, "\taddis r11,r11,ha16("); |
16407 | strcat (tmp_buf, name_buf); | |
16408 | strcat (tmp_buf, " - "); | |
16409 | strcat (tmp_buf, label); | |
16410 | strcat (tmp_buf, "_pic)\n"); | |
f676971a | 16411 | |
efdba735 | 16412 | strcat (tmp_buf, "\tmtlr r0\n"); |
f676971a | 16413 | |
efdba735 SH |
16414 | strcat (tmp_buf, "\taddi r12,r11,lo16("); |
16415 | strcat (tmp_buf, name_buf); | |
16416 | strcat (tmp_buf, " - "); | |
16417 | strcat (tmp_buf, label); | |
16418 | strcat (tmp_buf, "_pic)\n"); | |
f676971a | 16419 | |
efdba735 SH |
16420 | strcat (tmp_buf, "\tmtctr r12\n\tbctr\n"); |
16421 | } | |
16422 | else | |
16423 | { | |
16424 | strcat (tmp_buf, ":\nlis r12,hi16("); | |
16425 | strcat (tmp_buf, name_buf); | |
16426 | strcat (tmp_buf, ")\n\tori r12,r12,lo16("); | |
16427 | strcat (tmp_buf, name_buf); | |
16428 | strcat (tmp_buf, ")\n\tmtctr r12\n\tbctr"); | |
16429 | } | |
16430 | output_asm_insn (tmp_buf, 0); | |
ee890fe2 | 16431 | #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO) |
efdba735 | 16432 | if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG) |
93a27b7b | 16433 | dbxout_stabd (N_SLINE, BRANCH_ISLAND_LINE_NUMBER (branch_island)); |
ee890fe2 | 16434 | #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */ |
efdba735 | 16435 | } |
ee890fe2 | 16436 | |
efdba735 | 16437 | branch_island_list = 0; |
ee890fe2 SS |
16438 | } |
16439 | ||
16440 | /* NO_PREVIOUS_DEF checks in the link list whether the function name is | |
16441 | already there or not. */ | |
16442 | ||
efdba735 | 16443 | static int |
a2369ed3 | 16444 | no_previous_def (tree function_name) |
ee890fe2 | 16445 | { |
efdba735 SH |
16446 | tree branch_island; |
16447 | for (branch_island = branch_island_list; | |
16448 | branch_island; | |
16449 | branch_island = TREE_CHAIN (branch_island)) | |
16450 | if (function_name == BRANCH_ISLAND_FUNCTION_NAME (branch_island)) | |
ee890fe2 SS |
16451 | return 0; |
16452 | return 1; | |
16453 | } | |
16454 | ||
16455 | /* GET_PREV_LABEL gets the label name from the previous definition of | |
16456 | the function. */ | |
16457 | ||
efdba735 | 16458 | static tree |
a2369ed3 | 16459 | get_prev_label (tree function_name) |
ee890fe2 | 16460 | { |
efdba735 SH |
16461 | tree branch_island; |
16462 | for (branch_island = branch_island_list; | |
16463 | branch_island; | |
16464 | branch_island = TREE_CHAIN (branch_island)) | |
16465 | if (function_name == BRANCH_ISLAND_FUNCTION_NAME (branch_island)) | |
16466 | return BRANCH_ISLAND_LABEL_NAME (branch_island); | |
ee890fe2 SS |
16467 | return 0; |
16468 | } | |
16469 | ||
16470 | /* INSN is either a function call or a millicode call. It may have an | |
f676971a | 16471 | unconditional jump in its delay slot. |
ee890fe2 SS |
16472 | |
16473 | CALL_DEST is the routine we are calling. */ | |
16474 | ||
16475 | char * | |
c4ad648e AM |
16476 | output_call (rtx insn, rtx *operands, int dest_operand_number, |
16477 | int cookie_operand_number) | |
ee890fe2 SS |
16478 | { |
16479 | static char buf[256]; | |
efdba735 SH |
16480 | if (GET_CODE (operands[dest_operand_number]) == SYMBOL_REF |
16481 | && (INTVAL (operands[cookie_operand_number]) & CALL_LONG)) | |
ee890fe2 SS |
16482 | { |
16483 | tree labelname; | |
efdba735 | 16484 | tree funname = get_identifier (XSTR (operands[dest_operand_number], 0)); |
f676971a | 16485 | |
ee890fe2 SS |
16486 | if (no_previous_def (funname)) |
16487 | { | |
308c142a | 16488 | int line_number = 0; |
ee890fe2 SS |
16489 | rtx label_rtx = gen_label_rtx (); |
16490 | char *label_buf, temp_buf[256]; | |
16491 | ASM_GENERATE_INTERNAL_LABEL (temp_buf, "L", | |
16492 | CODE_LABEL_NUMBER (label_rtx)); | |
16493 | label_buf = temp_buf[0] == '*' ? temp_buf + 1 : temp_buf; | |
16494 | labelname = get_identifier (label_buf); | |
16495 | for (; insn && GET_CODE (insn) != NOTE; insn = PREV_INSN (insn)); | |
16496 | if (insn) | |
16497 | line_number = NOTE_LINE_NUMBER (insn); | |
efdba735 | 16498 | add_compiler_branch_island (labelname, funname, line_number); |
ee890fe2 SS |
16499 | } |
16500 | else | |
16501 | labelname = get_prev_label (funname); | |
16502 | ||
efdba735 SH |
16503 | /* "jbsr foo, L42" is Mach-O for "Link as 'bl foo' if a 'bl' |
16504 | instruction will reach 'foo', otherwise link as 'bl L42'". | |
16505 | "L42" should be a 'branch island', that will do a far jump to | |
16506 | 'foo'. Branch islands are generated in | |
16507 | macho_branch_islands(). */ | |
ee890fe2 | 16508 | sprintf (buf, "jbsr %%z%d,%.246s", |
efdba735 | 16509 | dest_operand_number, IDENTIFIER_POINTER (labelname)); |
ee890fe2 SS |
16510 | } |
16511 | else | |
efdba735 SH |
16512 | sprintf (buf, "bl %%z%d", dest_operand_number); |
16513 | return buf; | |
ee890fe2 SS |
16514 | } |
16515 | ||
ee890fe2 SS |
16516 | /* Generate PIC and indirect symbol stubs. */ |
16517 | ||
16518 | void | |
a2369ed3 | 16519 | machopic_output_stub (FILE *file, const char *symb, const char *stub) |
ee890fe2 SS |
16520 | { |
16521 | unsigned int length; | |
a4f6c312 SS |
16522 | char *symbol_name, *lazy_ptr_name; |
16523 | char *local_label_0; | |
ee890fe2 SS |
16524 | static int label = 0; |
16525 | ||
df56a27f | 16526 | /* Lose our funky encoding stuff so it doesn't contaminate the stub. */ |
772c5265 | 16527 | symb = (*targetm.strip_name_encoding) (symb); |
df56a27f | 16528 | |
ee890fe2 | 16529 | |
ee890fe2 SS |
16530 | length = strlen (symb); |
16531 | symbol_name = alloca (length + 32); | |
16532 | GEN_SYMBOL_NAME_FOR_SYMBOL (symbol_name, symb, length); | |
16533 | ||
16534 | lazy_ptr_name = alloca (length + 32); | |
16535 | GEN_LAZY_PTR_NAME_FOR_SYMBOL (lazy_ptr_name, symb, length); | |
16536 | ||
ee890fe2 | 16537 | if (flag_pic == 2) |
d3c300d2 | 16538 | machopic_picsymbol_stub1_section (); |
ee890fe2 | 16539 | else |
d3c300d2 | 16540 | machopic_symbol_stub1_section (); |
ee890fe2 SS |
16541 | |
16542 | if (flag_pic == 2) | |
16543 | { | |
d974312d DJ |
16544 | fprintf (file, "\t.align 5\n"); |
16545 | ||
16546 | fprintf (file, "%s:\n", stub); | |
16547 | fprintf (file, "\t.indirect_symbol %s\n", symbol_name); | |
16548 | ||
876455fa | 16549 | label++; |
89da1f32 | 16550 | local_label_0 = alloca (sizeof ("\"L00000000000$spb\"")); |
876455fa | 16551 | sprintf (local_label_0, "\"L%011d$spb\"", label); |
f676971a | 16552 | |
ee890fe2 SS |
16553 | fprintf (file, "\tmflr r0\n"); |
16554 | fprintf (file, "\tbcl 20,31,%s\n", local_label_0); | |
16555 | fprintf (file, "%s:\n\tmflr r11\n", local_label_0); | |
16556 | fprintf (file, "\taddis r11,r11,ha16(%s-%s)\n", | |
16557 | lazy_ptr_name, local_label_0); | |
16558 | fprintf (file, "\tmtlr r0\n"); | |
3d0e2d58 SS |
16559 | fprintf (file, "\t%s r12,lo16(%s-%s)(r11)\n", |
16560 | (TARGET_64BIT ? "ldu" : "lwzu"), | |
ee890fe2 SS |
16561 | lazy_ptr_name, local_label_0); |
16562 | fprintf (file, "\tmtctr r12\n"); | |
ee890fe2 SS |
16563 | fprintf (file, "\tbctr\n"); |
16564 | } | |
16565 | else | |
d974312d DJ |
16566 | { |
16567 | fprintf (file, "\t.align 4\n"); | |
16568 | ||
16569 | fprintf (file, "%s:\n", stub); | |
16570 | fprintf (file, "\t.indirect_symbol %s\n", symbol_name); | |
16571 | ||
16572 | fprintf (file, "\tlis r11,ha16(%s)\n", lazy_ptr_name); | |
d9e4e4f5 SS |
16573 | fprintf (file, "\t%s r12,lo16(%s)(r11)\n", |
16574 | (TARGET_64BIT ? "ldu" : "lwzu"), | |
16575 | lazy_ptr_name); | |
d974312d DJ |
16576 | fprintf (file, "\tmtctr r12\n"); |
16577 | fprintf (file, "\tbctr\n"); | |
16578 | } | |
f676971a | 16579 | |
ee890fe2 SS |
16580 | machopic_lazy_symbol_ptr_section (); |
16581 | fprintf (file, "%s:\n", lazy_ptr_name); | |
16582 | fprintf (file, "\t.indirect_symbol %s\n", symbol_name); | |
49bd1d27 SS |
16583 | fprintf (file, "%sdyld_stub_binding_helper\n", |
16584 | (TARGET_64BIT ? DOUBLE_INT_ASM_OP : "\t.long\t")); | |
ee890fe2 SS |
16585 | } |
16586 | ||
16587 | /* Legitimize PIC addresses. If the address is already | |
16588 | position-independent, we return ORIG. Newly generated | |
16589 | position-independent addresses go into a reg. This is REG if non | |
16590 | zero, otherwise we allocate register(s) as necessary. */ | |
16591 | ||
9390387d | 16592 | #define SMALL_INT(X) ((unsigned) (INTVAL (X) + 0x8000) < 0x10000) |
ee890fe2 SS |
16593 | |
16594 | rtx | |
f676971a | 16595 | rs6000_machopic_legitimize_pic_address (rtx orig, enum machine_mode mode, |
a2369ed3 | 16596 | rtx reg) |
ee890fe2 SS |
16597 | { |
16598 | rtx base, offset; | |
16599 | ||
16600 | if (reg == NULL && ! reload_in_progress && ! reload_completed) | |
16601 | reg = gen_reg_rtx (Pmode); | |
16602 | ||
16603 | if (GET_CODE (orig) == CONST) | |
16604 | { | |
37409796 NS |
16605 | rtx reg_temp; |
16606 | ||
ee890fe2 SS |
16607 | if (GET_CODE (XEXP (orig, 0)) == PLUS |
16608 | && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx) | |
16609 | return orig; | |
16610 | ||
37409796 NS |
16611 | gcc_assert (GET_CODE (XEXP (orig, 0)) == PLUS); |
16612 | ||
16613 | /* Use a different reg for the intermediate value, as | |
16614 | it will be marked UNCHANGING. */ | |
16615 | reg_temp = no_new_pseudos ? reg : gen_reg_rtx (Pmode); | |
16616 | base = rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 0), | |
16617 | Pmode, reg_temp); | |
16618 | offset = | |
16619 | rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 1), | |
16620 | Pmode, reg); | |
16621 | ||
ee890fe2 SS |
16622 | if (GET_CODE (offset) == CONST_INT) |
16623 | { | |
16624 | if (SMALL_INT (offset)) | |
ed8908e7 | 16625 | return plus_constant (base, INTVAL (offset)); |
ee890fe2 SS |
16626 | else if (! reload_in_progress && ! reload_completed) |
16627 | offset = force_reg (Pmode, offset); | |
16628 | else | |
c859cda6 DJ |
16629 | { |
16630 | rtx mem = force_const_mem (Pmode, orig); | |
16631 | return machopic_legitimize_pic_address (mem, Pmode, reg); | |
16632 | } | |
ee890fe2 | 16633 | } |
f1c25d3b | 16634 | return gen_rtx_PLUS (Pmode, base, offset); |
ee890fe2 SS |
16635 | } |
16636 | ||
16637 | /* Fall back on generic machopic code. */ | |
16638 | return machopic_legitimize_pic_address (orig, mode, reg); | |
16639 | } | |
16640 | ||
16641 | /* This is just a placeholder to make linking work without having to | |
16642 | add this to the generic Darwin EXTRA_SECTIONS. If -mcall-aix is | |
16643 | ever needed for Darwin (not too likely!) this would have to get a | |
16644 | real definition. */ | |
16645 | ||
16646 | void | |
863d938c | 16647 | toc_section (void) |
ee890fe2 SS |
16648 | { |
16649 | } | |
16650 | ||
c4e18b1c GK |
16651 | /* Output a .machine directive for the Darwin assembler, and call |
16652 | the generic start_file routine. */ | |
16653 | ||
16654 | static void | |
16655 | rs6000_darwin_file_start (void) | |
16656 | { | |
94ff898d | 16657 | static const struct |
c4e18b1c GK |
16658 | { |
16659 | const char *arg; | |
16660 | const char *name; | |
16661 | int if_set; | |
16662 | } mapping[] = { | |
55dbfb48 | 16663 | { "ppc64", "ppc64", MASK_64BIT }, |
c4e18b1c GK |
16664 | { "970", "ppc970", MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64 }, |
16665 | { "power4", "ppc970", 0 }, | |
16666 | { "G5", "ppc970", 0 }, | |
16667 | { "7450", "ppc7450", 0 }, | |
16668 | { "7400", "ppc7400", MASK_ALTIVEC }, | |
16669 | { "G4", "ppc7400", 0 }, | |
16670 | { "750", "ppc750", 0 }, | |
16671 | { "740", "ppc750", 0 }, | |
16672 | { "G3", "ppc750", 0 }, | |
16673 | { "604e", "ppc604e", 0 }, | |
16674 | { "604", "ppc604", 0 }, | |
16675 | { "603e", "ppc603", 0 }, | |
16676 | { "603", "ppc603", 0 }, | |
16677 | { "601", "ppc601", 0 }, | |
16678 | { NULL, "ppc", 0 } }; | |
16679 | const char *cpu_id = ""; | |
16680 | size_t i; | |
94ff898d | 16681 | |
9390387d | 16682 | rs6000_file_start (); |
c4e18b1c GK |
16683 | |
16684 | /* Determine the argument to -mcpu=. Default to G3 if not specified. */ | |
16685 | for (i = 0; i < ARRAY_SIZE (rs6000_select); i++) | |
16686 | if (rs6000_select[i].set_arch_p && rs6000_select[i].string | |
16687 | && rs6000_select[i].string[0] != '\0') | |
16688 | cpu_id = rs6000_select[i].string; | |
16689 | ||
16690 | /* Look through the mapping array. Pick the first name that either | |
16691 | matches the argument, has a bit set in IF_SET that is also set | |
16692 | in the target flags, or has a NULL name. */ | |
16693 | ||
16694 | i = 0; | |
16695 | while (mapping[i].arg != NULL | |
16696 | && strcmp (mapping[i].arg, cpu_id) != 0 | |
16697 | && (mapping[i].if_set & target_flags) == 0) | |
16698 | i++; | |
16699 | ||
16700 | fprintf (asm_out_file, "\t.machine %s\n", mapping[i].name); | |
16701 | } | |
16702 | ||
ee890fe2 | 16703 | #endif /* TARGET_MACHO */ |
7c262518 RH |
16704 | |
16705 | #if TARGET_ELF | |
16706 | static unsigned int | |
a2369ed3 | 16707 | rs6000_elf_section_type_flags (tree decl, const char *name, int reloc) |
7c262518 | 16708 | { |
1ff8f81a AM |
16709 | return default_section_type_flags_1 (decl, name, reloc, |
16710 | flag_pic || DEFAULT_ABI == ABI_AIX); | |
7c262518 | 16711 | } |
d9f6800d RH |
16712 | |
16713 | /* Record an element in the table of global constructors. SYMBOL is | |
16714 | a SYMBOL_REF of the function to be called; PRIORITY is a number | |
16715 | between 0 and MAX_INIT_PRIORITY. | |
16716 | ||
16717 | This differs from default_named_section_asm_out_constructor in | |
16718 | that we have special handling for -mrelocatable. */ | |
16719 | ||
16720 | static void | |
a2369ed3 | 16721 | rs6000_elf_asm_out_constructor (rtx symbol, int priority) |
d9f6800d RH |
16722 | { |
16723 | const char *section = ".ctors"; | |
16724 | char buf[16]; | |
16725 | ||
16726 | if (priority != DEFAULT_INIT_PRIORITY) | |
16727 | { | |
16728 | sprintf (buf, ".ctors.%.5u", | |
c4ad648e AM |
16729 | /* Invert the numbering so the linker puts us in the proper |
16730 | order; constructors are run from right to left, and the | |
16731 | linker sorts in increasing order. */ | |
16732 | MAX_INIT_PRIORITY - priority); | |
d9f6800d RH |
16733 | section = buf; |
16734 | } | |
16735 | ||
715bdd29 RH |
16736 | named_section_flags (section, SECTION_WRITE); |
16737 | assemble_align (POINTER_SIZE); | |
d9f6800d RH |
16738 | |
16739 | if (TARGET_RELOCATABLE) | |
16740 | { | |
16741 | fputs ("\t.long (", asm_out_file); | |
16742 | output_addr_const (asm_out_file, symbol); | |
16743 | fputs (")@fixup\n", asm_out_file); | |
16744 | } | |
16745 | else | |
c8af3574 | 16746 | assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1); |
d9f6800d RH |
16747 | } |
16748 | ||
16749 | static void | |
a2369ed3 | 16750 | rs6000_elf_asm_out_destructor (rtx symbol, int priority) |
d9f6800d RH |
16751 | { |
16752 | const char *section = ".dtors"; | |
16753 | char buf[16]; | |
16754 | ||
16755 | if (priority != DEFAULT_INIT_PRIORITY) | |
16756 | { | |
16757 | sprintf (buf, ".dtors.%.5u", | |
c4ad648e AM |
16758 | /* Invert the numbering so the linker puts us in the proper |
16759 | order; constructors are run from right to left, and the | |
16760 | linker sorts in increasing order. */ | |
16761 | MAX_INIT_PRIORITY - priority); | |
d9f6800d RH |
16762 | section = buf; |
16763 | } | |
16764 | ||
715bdd29 RH |
16765 | named_section_flags (section, SECTION_WRITE); |
16766 | assemble_align (POINTER_SIZE); | |
d9f6800d RH |
16767 | |
16768 | if (TARGET_RELOCATABLE) | |
16769 | { | |
16770 | fputs ("\t.long (", asm_out_file); | |
16771 | output_addr_const (asm_out_file, symbol); | |
16772 | fputs (")@fixup\n", asm_out_file); | |
16773 | } | |
16774 | else | |
c8af3574 | 16775 | assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1); |
d9f6800d | 16776 | } |
9739c90c JJ |
16777 | |
16778 | void | |
a2369ed3 | 16779 | rs6000_elf_declare_function_name (FILE *file, const char *name, tree decl) |
9739c90c JJ |
16780 | { |
16781 | if (TARGET_64BIT) | |
16782 | { | |
16783 | fputs ("\t.section\t\".opd\",\"aw\"\n\t.align 3\n", file); | |
16784 | ASM_OUTPUT_LABEL (file, name); | |
16785 | fputs (DOUBLE_INT_ASM_OP, file); | |
85b776df AM |
16786 | rs6000_output_function_entry (file, name); |
16787 | fputs (",.TOC.@tocbase,0\n\t.previous\n", file); | |
16788 | if (DOT_SYMBOLS) | |
9739c90c | 16789 | { |
85b776df | 16790 | fputs ("\t.size\t", file); |
9739c90c | 16791 | assemble_name (file, name); |
85b776df AM |
16792 | fputs (",24\n\t.type\t.", file); |
16793 | assemble_name (file, name); | |
16794 | fputs (",@function\n", file); | |
16795 | if (TREE_PUBLIC (decl) && ! DECL_WEAK (decl)) | |
16796 | { | |
16797 | fputs ("\t.globl\t.", file); | |
16798 | assemble_name (file, name); | |
16799 | putc ('\n', file); | |
16800 | } | |
9739c90c | 16801 | } |
85b776df AM |
16802 | else |
16803 | ASM_OUTPUT_TYPE_DIRECTIVE (file, name, "function"); | |
9739c90c | 16804 | ASM_DECLARE_RESULT (file, DECL_RESULT (decl)); |
85b776df AM |
16805 | rs6000_output_function_entry (file, name); |
16806 | fputs (":\n", file); | |
9739c90c JJ |
16807 | return; |
16808 | } | |
16809 | ||
16810 | if (TARGET_RELOCATABLE | |
16811 | && (get_pool_size () != 0 || current_function_profile) | |
3c9eb5f4 | 16812 | && uses_TOC ()) |
9739c90c JJ |
16813 | { |
16814 | char buf[256]; | |
16815 | ||
16816 | (*targetm.asm_out.internal_label) (file, "LCL", rs6000_pic_labelno); | |
16817 | ||
16818 | ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1); | |
16819 | fprintf (file, "\t.long "); | |
16820 | assemble_name (file, buf); | |
16821 | putc ('-', file); | |
16822 | ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno); | |
16823 | assemble_name (file, buf); | |
16824 | putc ('\n', file); | |
16825 | } | |
16826 | ||
16827 | ASM_OUTPUT_TYPE_DIRECTIVE (file, name, "function"); | |
16828 | ASM_DECLARE_RESULT (file, DECL_RESULT (decl)); | |
16829 | ||
16830 | if (DEFAULT_ABI == ABI_AIX) | |
16831 | { | |
16832 | const char *desc_name, *orig_name; | |
16833 | ||
16834 | orig_name = (*targetm.strip_name_encoding) (name); | |
16835 | desc_name = orig_name; | |
16836 | while (*desc_name == '.') | |
16837 | desc_name++; | |
16838 | ||
16839 | if (TREE_PUBLIC (decl)) | |
16840 | fprintf (file, "\t.globl %s\n", desc_name); | |
16841 | ||
16842 | fprintf (file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP); | |
16843 | fprintf (file, "%s:\n", desc_name); | |
16844 | fprintf (file, "\t.long %s\n", orig_name); | |
16845 | fputs ("\t.long _GLOBAL_OFFSET_TABLE_\n", file); | |
16846 | if (DEFAULT_ABI == ABI_AIX) | |
16847 | fputs ("\t.long 0\n", file); | |
16848 | fprintf (file, "\t.previous\n"); | |
16849 | } | |
16850 | ASM_OUTPUT_LABEL (file, name); | |
16851 | } | |
1334b570 AM |
16852 | |
16853 | static void | |
16854 | rs6000_elf_end_indicate_exec_stack (void) | |
16855 | { | |
16856 | if (TARGET_32BIT) | |
16857 | file_end_indicate_exec_stack (); | |
16858 | } | |
7c262518 RH |
16859 | #endif |
16860 | ||
cbaaba19 | 16861 | #if TARGET_XCOFF |
7c262518 | 16862 | static void |
a2369ed3 | 16863 | rs6000_xcoff_asm_globalize_label (FILE *stream, const char *name) |
b275d088 DE |
16864 | { |
16865 | fputs (GLOBAL_ASM_OP, stream); | |
16866 | RS6000_OUTPUT_BASENAME (stream, name); | |
16867 | putc ('\n', stream); | |
16868 | } | |
16869 | ||
16870 | static void | |
c18a5b6c MM |
16871 | rs6000_xcoff_asm_named_section (const char *name, unsigned int flags, |
16872 | tree decl ATTRIBUTE_UNUSED) | |
7c262518 | 16873 | { |
0e5dbd9b DE |
16874 | int smclass; |
16875 | static const char * const suffix[3] = { "PR", "RO", "RW" }; | |
16876 | ||
16877 | if (flags & SECTION_CODE) | |
16878 | smclass = 0; | |
16879 | else if (flags & SECTION_WRITE) | |
16880 | smclass = 2; | |
16881 | else | |
16882 | smclass = 1; | |
16883 | ||
5b5198f7 | 16884 | fprintf (asm_out_file, "\t.csect %s%s[%s],%u\n", |
0e5dbd9b | 16885 | (flags & SECTION_CODE) ? "." : "", |
5b5198f7 | 16886 | name, suffix[smclass], flags & SECTION_ENTSIZE); |
7c262518 | 16887 | } |
ae46c4e0 RH |
16888 | |
16889 | static void | |
f676971a | 16890 | rs6000_xcoff_select_section (tree decl, int reloc, |
c4ad648e | 16891 | unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED) |
ae46c4e0 | 16892 | { |
5add3202 | 16893 | if (decl_readonly_section_1 (decl, reloc, 1)) |
ae46c4e0 | 16894 | { |
0e5dbd9b | 16895 | if (TREE_PUBLIC (decl)) |
c4ad648e | 16896 | read_only_data_section (); |
ae46c4e0 | 16897 | else |
c4ad648e | 16898 | read_only_private_data_section (); |
ae46c4e0 RH |
16899 | } |
16900 | else | |
16901 | { | |
0e5dbd9b | 16902 | if (TREE_PUBLIC (decl)) |
c4ad648e | 16903 | data_section (); |
ae46c4e0 | 16904 | else |
c4ad648e | 16905 | private_data_section (); |
ae46c4e0 RH |
16906 | } |
16907 | } | |
16908 | ||
16909 | static void | |
a2369ed3 | 16910 | rs6000_xcoff_unique_section (tree decl, int reloc ATTRIBUTE_UNUSED) |
ae46c4e0 RH |
16911 | { |
16912 | const char *name; | |
ae46c4e0 | 16913 | |
5b5198f7 DE |
16914 | /* Use select_section for private and uninitialized data. */ |
16915 | if (!TREE_PUBLIC (decl) | |
16916 | || DECL_COMMON (decl) | |
0e5dbd9b DE |
16917 | || DECL_INITIAL (decl) == NULL_TREE |
16918 | || DECL_INITIAL (decl) == error_mark_node | |
16919 | || (flag_zero_initialized_in_bss | |
16920 | && initializer_zerop (DECL_INITIAL (decl)))) | |
16921 | return; | |
16922 | ||
16923 | name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl)); | |
16924 | name = (*targetm.strip_name_encoding) (name); | |
16925 | DECL_SECTION_NAME (decl) = build_string (strlen (name), name); | |
ae46c4e0 | 16926 | } |
b64a1b53 | 16927 | |
fb49053f RH |
16928 | /* Select section for constant in constant pool. |
16929 | ||
16930 | On RS/6000, all constants are in the private read-only data area. | |
16931 | However, if this is being placed in the TOC it must be output as a | |
16932 | toc entry. */ | |
16933 | ||
b64a1b53 | 16934 | static void |
f676971a | 16935 | rs6000_xcoff_select_rtx_section (enum machine_mode mode, rtx x, |
c4ad648e | 16936 | unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED) |
b64a1b53 RH |
16937 | { |
16938 | if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode)) | |
16939 | toc_section (); | |
16940 | else | |
16941 | read_only_private_data_section (); | |
16942 | } | |
772c5265 RH |
16943 | |
16944 | /* Remove any trailing [DS] or the like from the symbol name. */ | |
16945 | ||
16946 | static const char * | |
a2369ed3 | 16947 | rs6000_xcoff_strip_name_encoding (const char *name) |
772c5265 RH |
16948 | { |
16949 | size_t len; | |
16950 | if (*name == '*') | |
16951 | name++; | |
16952 | len = strlen (name); | |
16953 | if (name[len - 1] == ']') | |
16954 | return ggc_alloc_string (name, len - 4); | |
16955 | else | |
16956 | return name; | |
16957 | } | |
16958 | ||
5add3202 DE |
16959 | /* Section attributes. AIX is always PIC. */ |
16960 | ||
16961 | static unsigned int | |
a2369ed3 | 16962 | rs6000_xcoff_section_type_flags (tree decl, const char *name, int reloc) |
5add3202 | 16963 | { |
5b5198f7 DE |
16964 | unsigned int align; |
16965 | unsigned int flags = default_section_type_flags_1 (decl, name, reloc, 1); | |
16966 | ||
16967 | /* Align to at least UNIT size. */ | |
16968 | if (flags & SECTION_CODE) | |
16969 | align = MIN_UNITS_PER_WORD; | |
16970 | else | |
16971 | /* Increase alignment of large objects if not already stricter. */ | |
16972 | align = MAX ((DECL_ALIGN (decl) / BITS_PER_UNIT), | |
16973 | int_size_in_bytes (TREE_TYPE (decl)) > MIN_UNITS_PER_WORD | |
16974 | ? UNITS_PER_FP_WORD : MIN_UNITS_PER_WORD); | |
16975 | ||
16976 | return flags | (exact_log2 (align) & SECTION_ENTSIZE); | |
5add3202 | 16977 | } |
a5fe455b | 16978 | |
1bc7c5b6 ZW |
16979 | /* Output at beginning of assembler file. |
16980 | ||
16981 | Initialize the section names for the RS/6000 at this point. | |
16982 | ||
16983 | Specify filename, including full path, to assembler. | |
16984 | ||
16985 | We want to go into the TOC section so at least one .toc will be emitted. | |
16986 | Also, in order to output proper .bs/.es pairs, we need at least one static | |
16987 | [RW] section emitted. | |
16988 | ||
16989 | Finally, declare mcount when profiling to make the assembler happy. */ | |
16990 | ||
16991 | static void | |
863d938c | 16992 | rs6000_xcoff_file_start (void) |
1bc7c5b6 ZW |
16993 | { |
16994 | rs6000_gen_section_name (&xcoff_bss_section_name, | |
16995 | main_input_filename, ".bss_"); | |
16996 | rs6000_gen_section_name (&xcoff_private_data_section_name, | |
16997 | main_input_filename, ".rw_"); | |
16998 | rs6000_gen_section_name (&xcoff_read_only_section_name, | |
16999 | main_input_filename, ".ro_"); | |
17000 | ||
17001 | fputs ("\t.file\t", asm_out_file); | |
17002 | output_quoted_string (asm_out_file, main_input_filename); | |
17003 | fputc ('\n', asm_out_file); | |
1bc7c5b6 ZW |
17004 | if (write_symbols != NO_DEBUG) |
17005 | private_data_section (); | |
17006 | text_section (); | |
17007 | if (profile_flag) | |
17008 | fprintf (asm_out_file, "\t.extern %s\n", RS6000_MCOUNT); | |
17009 | rs6000_file_start (); | |
17010 | } | |
17011 | ||
a5fe455b ZW |
17012 | /* Output at end of assembler file. |
17013 | On the RS/6000, referencing data should automatically pull in text. */ | |
17014 | ||
17015 | static void | |
863d938c | 17016 | rs6000_xcoff_file_end (void) |
a5fe455b ZW |
17017 | { |
17018 | text_section (); | |
17019 | fputs ("_section_.text:\n", asm_out_file); | |
17020 | data_section (); | |
17021 | fputs (TARGET_32BIT | |
17022 | ? "\t.long _section_.text\n" : "\t.llong _section_.text\n", | |
17023 | asm_out_file); | |
17024 | } | |
f1384257 | 17025 | #endif /* TARGET_XCOFF */ |
0e5dbd9b | 17026 | |
f1384257 AM |
17027 | #if TARGET_MACHO |
17028 | /* Cross-module name binding. Darwin does not support overriding | |
7f3d8013 | 17029 | functions at dynamic-link time. */ |
0e5dbd9b | 17030 | |
2bcc50d0 | 17031 | static bool |
a2369ed3 | 17032 | rs6000_binds_local_p (tree decl) |
0e5dbd9b | 17033 | { |
f1384257 | 17034 | return default_binds_local_p_1 (decl, 0); |
0e5dbd9b | 17035 | } |
f1384257 | 17036 | #endif |
34bb030a | 17037 | |
3c50106f RH |
17038 | /* Compute a (partial) cost for rtx X. Return true if the complete |
17039 | cost has been computed, and false if subexpressions should be | |
17040 | scanned. In either case, *TOTAL contains the cost result. */ | |
17041 | ||
17042 | static bool | |
1494c534 | 17043 | rs6000_rtx_costs (rtx x, int code, int outer_code, int *total) |
3c50106f | 17044 | { |
f0517163 RS |
17045 | enum machine_mode mode = GET_MODE (x); |
17046 | ||
3c50106f RH |
17047 | switch (code) |
17048 | { | |
30a555d9 | 17049 | /* On the RS/6000, if it is valid in the insn, it is free. */ |
3c50106f | 17050 | case CONST_INT: |
066cd967 DE |
17051 | if (((outer_code == SET |
17052 | || outer_code == PLUS | |
17053 | || outer_code == MINUS) | |
17054 | && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'I') | |
17055 | || CONST_OK_FOR_LETTER_P (INTVAL (x), 'L'))) | |
066cd967 DE |
17056 | || (outer_code == AND |
17057 | && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'K') | |
22e54023 DE |
17058 | || (CONST_OK_FOR_LETTER_P (INTVAL (x), |
17059 | mode == SImode ? 'L' : 'J')) | |
d5861a7a | 17060 | || mask_operand (x, VOIDmode))) |
22e54023 DE |
17061 | || ((outer_code == IOR || outer_code == XOR) |
17062 | && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'K') | |
17063 | || (CONST_OK_FOR_LETTER_P (INTVAL (x), | |
17064 | mode == SImode ? 'L' : 'J')))) | |
066cd967 DE |
17065 | || outer_code == ASHIFT |
17066 | || outer_code == ASHIFTRT | |
17067 | || outer_code == LSHIFTRT | |
17068 | || outer_code == ROTATE | |
17069 | || outer_code == ROTATERT | |
d5861a7a | 17070 | || outer_code == ZERO_EXTRACT |
066cd967 DE |
17071 | || (outer_code == MULT |
17072 | && CONST_OK_FOR_LETTER_P (INTVAL (x), 'I')) | |
22e54023 DE |
17073 | || ((outer_code == DIV || outer_code == UDIV |
17074 | || outer_code == MOD || outer_code == UMOD) | |
17075 | && exact_log2 (INTVAL (x)) >= 0) | |
066cd967 DE |
17076 | || (outer_code == COMPARE |
17077 | && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'I') | |
22e54023 DE |
17078 | || CONST_OK_FOR_LETTER_P (INTVAL (x), 'K'))) |
17079 | || (outer_code == EQ | |
17080 | && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'I') | |
17081 | || CONST_OK_FOR_LETTER_P (INTVAL (x), 'K') | |
17082 | || (CONST_OK_FOR_LETTER_P (INTVAL (x), | |
17083 | mode == SImode ? 'L' : 'J')))) | |
17084 | || (outer_code == GTU | |
17085 | && CONST_OK_FOR_LETTER_P (INTVAL (x), 'I')) | |
17086 | || (outer_code == LTU | |
17087 | && CONST_OK_FOR_LETTER_P (INTVAL (x), 'P'))) | |
066cd967 DE |
17088 | { |
17089 | *total = 0; | |
17090 | return true; | |
17091 | } | |
17092 | else if ((outer_code == PLUS | |
17093 | && reg_or_add_cint64_operand (x, VOIDmode)) | |
17094 | || (outer_code == MINUS | |
17095 | && reg_or_sub_cint64_operand (x, VOIDmode)) | |
17096 | || ((outer_code == SET | |
17097 | || outer_code == IOR | |
17098 | || outer_code == XOR) | |
17099 | && (INTVAL (x) | |
17100 | & ~ (unsigned HOST_WIDE_INT) 0xffffffff) == 0)) | |
17101 | { | |
17102 | *total = COSTS_N_INSNS (1); | |
17103 | return true; | |
17104 | } | |
17105 | /* FALLTHRU */ | |
17106 | ||
17107 | case CONST_DOUBLE: | |
17108 | if (mode == DImode | |
17109 | && ((outer_code == AND | |
17110 | && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'K') | |
17111 | || CONST_OK_FOR_LETTER_P (INTVAL (x), 'L') | |
d5861a7a | 17112 | || mask64_operand (x, DImode))) |
066cd967 DE |
17113 | || ((outer_code == IOR || outer_code == XOR) |
17114 | && CONST_DOUBLE_HIGH (x) == 0 | |
17115 | && (CONST_DOUBLE_LOW (x) | |
17116 | & ~ (unsigned HOST_WIDE_INT) 0xffff) == 0))) | |
17117 | { | |
17118 | *total = 0; | |
17119 | return true; | |
17120 | } | |
17121 | else if (mode == DImode | |
17122 | && (outer_code == SET | |
17123 | || outer_code == IOR | |
17124 | || outer_code == XOR) | |
17125 | && CONST_DOUBLE_HIGH (x) == 0) | |
17126 | { | |
17127 | *total = COSTS_N_INSNS (1); | |
17128 | return true; | |
17129 | } | |
17130 | /* FALLTHRU */ | |
17131 | ||
3c50106f | 17132 | case CONST: |
066cd967 | 17133 | case HIGH: |
3c50106f | 17134 | case SYMBOL_REF: |
066cd967 DE |
17135 | case MEM: |
17136 | /* When optimizing for size, MEM should be slightly more expensive | |
17137 | than generating address, e.g., (plus (reg) (const)). | |
c112cf2b | 17138 | L1 cache latency is about two instructions. */ |
066cd967 | 17139 | *total = optimize_size ? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (2); |
3c50106f RH |
17140 | return true; |
17141 | ||
30a555d9 DE |
17142 | case LABEL_REF: |
17143 | *total = 0; | |
17144 | return true; | |
17145 | ||
3c50106f | 17146 | case PLUS: |
f0517163 | 17147 | if (mode == DFmode) |
066cd967 DE |
17148 | { |
17149 | if (GET_CODE (XEXP (x, 0)) == MULT) | |
17150 | { | |
17151 | /* FNMA accounted in outer NEG. */ | |
17152 | if (outer_code == NEG) | |
17153 | *total = rs6000_cost->dmul - rs6000_cost->fp; | |
17154 | else | |
17155 | *total = rs6000_cost->dmul; | |
17156 | } | |
17157 | else | |
17158 | *total = rs6000_cost->fp; | |
17159 | } | |
f0517163 | 17160 | else if (mode == SFmode) |
066cd967 DE |
17161 | { |
17162 | /* FNMA accounted in outer NEG. */ | |
17163 | if (outer_code == NEG && GET_CODE (XEXP (x, 0)) == MULT) | |
17164 | *total = 0; | |
17165 | else | |
17166 | *total = rs6000_cost->fp; | |
17167 | } | |
938bf747 RS |
17168 | else if (GET_CODE (XEXP (x, 0)) == MULT) |
17169 | { | |
17170 | /* The rs6000 doesn't have shift-and-add instructions. */ | |
17171 | rs6000_rtx_costs (XEXP (x, 0), MULT, PLUS, total); | |
17172 | *total += COSTS_N_INSNS (1); | |
17173 | } | |
f0517163 | 17174 | else |
066cd967 DE |
17175 | *total = COSTS_N_INSNS (1); |
17176 | return false; | |
3c50106f | 17177 | |
52190329 | 17178 | case MINUS: |
f0517163 | 17179 | if (mode == DFmode) |
066cd967 DE |
17180 | { |
17181 | if (GET_CODE (XEXP (x, 0)) == MULT) | |
17182 | { | |
17183 | /* FNMA accounted in outer NEG. */ | |
17184 | if (outer_code == NEG) | |
17185 | *total = 0; | |
17186 | else | |
17187 | *total = rs6000_cost->dmul; | |
17188 | } | |
17189 | else | |
17190 | *total = rs6000_cost->fp; | |
17191 | } | |
f0517163 | 17192 | else if (mode == SFmode) |
066cd967 DE |
17193 | { |
17194 | /* FNMA accounted in outer NEG. */ | |
17195 | if (outer_code == NEG && GET_CODE (XEXP (x, 0)) == MULT) | |
17196 | *total = 0; | |
17197 | else | |
17198 | *total = rs6000_cost->fp; | |
17199 | } | |
938bf747 RS |
17200 | else if (GET_CODE (XEXP (x, 0)) == MULT) |
17201 | { | |
17202 | /* The rs6000 doesn't have shift-and-sub instructions. */ | |
17203 | rs6000_rtx_costs (XEXP (x, 0), MULT, MINUS, total); | |
17204 | *total += COSTS_N_INSNS (1); | |
17205 | } | |
f0517163 | 17206 | else |
c4ad648e | 17207 | *total = COSTS_N_INSNS (1); |
066cd967 | 17208 | return false; |
3c50106f RH |
17209 | |
17210 | case MULT: | |
c9dbf840 DE |
17211 | if (GET_CODE (XEXP (x, 1)) == CONST_INT |
17212 | && CONST_OK_FOR_LETTER_P (INTVAL (XEXP (x, 1)), 'I')) | |
3c50106f | 17213 | { |
8b897cfa RS |
17214 | if (INTVAL (XEXP (x, 1)) >= -256 |
17215 | && INTVAL (XEXP (x, 1)) <= 255) | |
06a67bdd | 17216 | *total = rs6000_cost->mulsi_const9; |
8b897cfa | 17217 | else |
06a67bdd | 17218 | *total = rs6000_cost->mulsi_const; |
3c50106f | 17219 | } |
066cd967 DE |
17220 | /* FMA accounted in outer PLUS/MINUS. */ |
17221 | else if ((mode == DFmode || mode == SFmode) | |
17222 | && (outer_code == PLUS || outer_code == MINUS)) | |
17223 | *total = 0; | |
f0517163 | 17224 | else if (mode == DFmode) |
06a67bdd | 17225 | *total = rs6000_cost->dmul; |
f0517163 | 17226 | else if (mode == SFmode) |
06a67bdd | 17227 | *total = rs6000_cost->fp; |
f0517163 | 17228 | else if (mode == DImode) |
06a67bdd | 17229 | *total = rs6000_cost->muldi; |
8b897cfa | 17230 | else |
06a67bdd | 17231 | *total = rs6000_cost->mulsi; |
066cd967 | 17232 | return false; |
3c50106f RH |
17233 | |
17234 | case DIV: | |
17235 | case MOD: | |
f0517163 RS |
17236 | if (FLOAT_MODE_P (mode)) |
17237 | { | |
06a67bdd RS |
17238 | *total = mode == DFmode ? rs6000_cost->ddiv |
17239 | : rs6000_cost->sdiv; | |
066cd967 | 17240 | return false; |
f0517163 | 17241 | } |
5efb1046 | 17242 | /* FALLTHRU */ |
3c50106f RH |
17243 | |
17244 | case UDIV: | |
17245 | case UMOD: | |
627b6fe2 DJ |
17246 | if (GET_CODE (XEXP (x, 1)) == CONST_INT |
17247 | && exact_log2 (INTVAL (XEXP (x, 1))) >= 0) | |
17248 | { | |
17249 | if (code == DIV || code == MOD) | |
17250 | /* Shift, addze */ | |
17251 | *total = COSTS_N_INSNS (2); | |
17252 | else | |
17253 | /* Shift */ | |
17254 | *total = COSTS_N_INSNS (1); | |
17255 | } | |
c4ad648e | 17256 | else |
627b6fe2 DJ |
17257 | { |
17258 | if (GET_MODE (XEXP (x, 1)) == DImode) | |
17259 | *total = rs6000_cost->divdi; | |
17260 | else | |
17261 | *total = rs6000_cost->divsi; | |
17262 | } | |
17263 | /* Add in shift and subtract for MOD. */ | |
17264 | if (code == MOD || code == UMOD) | |
17265 | *total += COSTS_N_INSNS (2); | |
066cd967 | 17266 | return false; |
3c50106f RH |
17267 | |
17268 | case FFS: | |
17269 | *total = COSTS_N_INSNS (4); | |
066cd967 | 17270 | return false; |
3c50106f | 17271 | |
06a67bdd | 17272 | case NOT: |
066cd967 DE |
17273 | if (outer_code == AND || outer_code == IOR || outer_code == XOR) |
17274 | { | |
17275 | *total = 0; | |
17276 | return false; | |
17277 | } | |
17278 | /* FALLTHRU */ | |
17279 | ||
17280 | case AND: | |
17281 | case IOR: | |
17282 | case XOR: | |
d5861a7a DE |
17283 | case ZERO_EXTRACT: |
17284 | *total = COSTS_N_INSNS (1); | |
17285 | return false; | |
17286 | ||
066cd967 DE |
17287 | case ASHIFT: |
17288 | case ASHIFTRT: | |
17289 | case LSHIFTRT: | |
17290 | case ROTATE: | |
17291 | case ROTATERT: | |
d5861a7a | 17292 | /* Handle mul_highpart. */ |
066cd967 DE |
17293 | if (outer_code == TRUNCATE |
17294 | && GET_CODE (XEXP (x, 0)) == MULT) | |
17295 | { | |
17296 | if (mode == DImode) | |
17297 | *total = rs6000_cost->muldi; | |
17298 | else | |
17299 | *total = rs6000_cost->mulsi; | |
17300 | return true; | |
17301 | } | |
d5861a7a DE |
17302 | else if (outer_code == AND) |
17303 | *total = 0; | |
17304 | else | |
17305 | *total = COSTS_N_INSNS (1); | |
17306 | return false; | |
17307 | ||
17308 | case SIGN_EXTEND: | |
17309 | case ZERO_EXTEND: | |
17310 | if (GET_CODE (XEXP (x, 0)) == MEM) | |
17311 | *total = 0; | |
17312 | else | |
17313 | *total = COSTS_N_INSNS (1); | |
066cd967 | 17314 | return false; |
06a67bdd | 17315 | |
066cd967 DE |
17316 | case COMPARE: |
17317 | case NEG: | |
17318 | case ABS: | |
17319 | if (!FLOAT_MODE_P (mode)) | |
17320 | { | |
17321 | *total = COSTS_N_INSNS (1); | |
17322 | return false; | |
17323 | } | |
17324 | /* FALLTHRU */ | |
17325 | ||
17326 | case FLOAT: | |
17327 | case UNSIGNED_FLOAT: | |
17328 | case FIX: | |
17329 | case UNSIGNED_FIX: | |
17330 | case FLOAT_EXTEND: | |
06a67bdd RS |
17331 | case FLOAT_TRUNCATE: |
17332 | *total = rs6000_cost->fp; | |
066cd967 | 17333 | return false; |
06a67bdd RS |
17334 | |
17335 | case UNSPEC: | |
17336 | switch (XINT (x, 1)) | |
17337 | { | |
17338 | case UNSPEC_FRSP: | |
17339 | *total = rs6000_cost->fp; | |
17340 | return true; | |
17341 | ||
17342 | default: | |
17343 | break; | |
17344 | } | |
17345 | break; | |
17346 | ||
17347 | case CALL: | |
17348 | case IF_THEN_ELSE: | |
17349 | if (optimize_size) | |
17350 | { | |
17351 | *total = COSTS_N_INSNS (1); | |
17352 | return true; | |
17353 | } | |
066cd967 DE |
17354 | else if (FLOAT_MODE_P (mode) |
17355 | && TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS) | |
17356 | { | |
17357 | *total = rs6000_cost->fp; | |
17358 | return false; | |
17359 | } | |
06a67bdd RS |
17360 | break; |
17361 | ||
c0600ecd DE |
17362 | case EQ: |
17363 | case GTU: | |
17364 | case LTU: | |
22e54023 DE |
17365 | /* Carry bit requires mode == Pmode. |
17366 | NEG or PLUS already counted so only add one. */ | |
17367 | if (mode == Pmode | |
17368 | && (outer_code == NEG || outer_code == PLUS)) | |
c0600ecd | 17369 | { |
22e54023 DE |
17370 | *total = COSTS_N_INSNS (1); |
17371 | return true; | |
17372 | } | |
17373 | if (outer_code == SET) | |
17374 | { | |
17375 | if (XEXP (x, 1) == const0_rtx) | |
c0600ecd | 17376 | { |
22e54023 | 17377 | *total = COSTS_N_INSNS (2); |
c0600ecd | 17378 | return true; |
c0600ecd | 17379 | } |
22e54023 DE |
17380 | else if (mode == Pmode) |
17381 | { | |
17382 | *total = COSTS_N_INSNS (3); | |
17383 | return false; | |
17384 | } | |
17385 | } | |
17386 | /* FALLTHRU */ | |
17387 | ||
17388 | case GT: | |
17389 | case LT: | |
17390 | case UNORDERED: | |
17391 | if (outer_code == SET && (XEXP (x, 1) == const0_rtx)) | |
17392 | { | |
17393 | *total = COSTS_N_INSNS (2); | |
17394 | return true; | |
c0600ecd | 17395 | } |
22e54023 DE |
17396 | /* CC COMPARE. */ |
17397 | if (outer_code == COMPARE) | |
17398 | { | |
17399 | *total = 0; | |
17400 | return true; | |
17401 | } | |
17402 | break; | |
c0600ecd | 17403 | |
3c50106f | 17404 | default: |
06a67bdd | 17405 | break; |
3c50106f | 17406 | } |
06a67bdd RS |
17407 | |
17408 | return false; | |
3c50106f RH |
17409 | } |
17410 | ||
34bb030a DE |
17411 | /* A C expression returning the cost of moving data from a register of class |
17412 | CLASS1 to one of CLASS2. */ | |
17413 | ||
17414 | int | |
f676971a | 17415 | rs6000_register_move_cost (enum machine_mode mode, |
a2369ed3 | 17416 | enum reg_class from, enum reg_class to) |
34bb030a DE |
17417 | { |
17418 | /* Moves from/to GENERAL_REGS. */ | |
17419 | if (reg_classes_intersect_p (to, GENERAL_REGS) | |
17420 | || reg_classes_intersect_p (from, GENERAL_REGS)) | |
17421 | { | |
17422 | if (! reg_classes_intersect_p (to, GENERAL_REGS)) | |
17423 | from = to; | |
17424 | ||
17425 | if (from == FLOAT_REGS || from == ALTIVEC_REGS) | |
17426 | return (rs6000_memory_move_cost (mode, from, 0) | |
17427 | + rs6000_memory_move_cost (mode, GENERAL_REGS, 0)); | |
17428 | ||
c4ad648e AM |
17429 | /* It's more expensive to move CR_REGS than CR0_REGS because of the |
17430 | shift. */ | |
34bb030a DE |
17431 | else if (from == CR_REGS) |
17432 | return 4; | |
17433 | ||
17434 | else | |
c4ad648e | 17435 | /* A move will cost one instruction per GPR moved. */ |
34bb030a DE |
17436 | return 2 * HARD_REGNO_NREGS (0, mode); |
17437 | } | |
17438 | ||
c4ad648e | 17439 | /* Moving between two similar registers is just one instruction. */ |
34bb030a DE |
17440 | else if (reg_classes_intersect_p (to, from)) |
17441 | return mode == TFmode ? 4 : 2; | |
17442 | ||
c4ad648e | 17443 | /* Everything else has to go through GENERAL_REGS. */ |
34bb030a | 17444 | else |
f676971a | 17445 | return (rs6000_register_move_cost (mode, GENERAL_REGS, to) |
34bb030a DE |
17446 | + rs6000_register_move_cost (mode, from, GENERAL_REGS)); |
17447 | } | |
17448 | ||
17449 | /* A C expressions returning the cost of moving data of MODE from a register to | |
17450 | or from memory. */ | |
17451 | ||
17452 | int | |
f676971a | 17453 | rs6000_memory_move_cost (enum machine_mode mode, enum reg_class class, |
a2369ed3 | 17454 | int in ATTRIBUTE_UNUSED) |
34bb030a DE |
17455 | { |
17456 | if (reg_classes_intersect_p (class, GENERAL_REGS)) | |
17457 | return 4 * HARD_REGNO_NREGS (0, mode); | |
17458 | else if (reg_classes_intersect_p (class, FLOAT_REGS)) | |
17459 | return 4 * HARD_REGNO_NREGS (32, mode); | |
17460 | else if (reg_classes_intersect_p (class, ALTIVEC_REGS)) | |
17461 | return 4 * HARD_REGNO_NREGS (FIRST_ALTIVEC_REGNO, mode); | |
17462 | else | |
17463 | return 4 + rs6000_register_move_cost (mode, class, GENERAL_REGS); | |
17464 | } | |
17465 | ||
ded9bf77 AH |
17466 | /* Return an RTX representing where to find the function value of a |
17467 | function returning MODE. */ | |
17468 | static rtx | |
17469 | rs6000_complex_function_value (enum machine_mode mode) | |
17470 | { | |
17471 | unsigned int regno; | |
17472 | rtx r1, r2; | |
17473 | enum machine_mode inner = GET_MODE_INNER (mode); | |
fb7e4164 | 17474 | unsigned int inner_bytes = GET_MODE_SIZE (inner); |
ded9bf77 | 17475 | |
18f63bfa AH |
17476 | if (FLOAT_MODE_P (mode) && TARGET_HARD_FLOAT && TARGET_FPRS) |
17477 | regno = FP_ARG_RETURN; | |
354ed18f AH |
17478 | else |
17479 | { | |
18f63bfa | 17480 | regno = GP_ARG_RETURN; |
ded9bf77 | 17481 | |
18f63bfa AH |
17482 | /* 32-bit is OK since it'll go in r3/r4. */ |
17483 | if (TARGET_32BIT && inner_bytes >= 4) | |
ded9bf77 AH |
17484 | return gen_rtx_REG (mode, regno); |
17485 | } | |
17486 | ||
18f63bfa AH |
17487 | if (inner_bytes >= 8) |
17488 | return gen_rtx_REG (mode, regno); | |
17489 | ||
ded9bf77 AH |
17490 | r1 = gen_rtx_EXPR_LIST (inner, gen_rtx_REG (inner, regno), |
17491 | const0_rtx); | |
17492 | r2 = gen_rtx_EXPR_LIST (inner, gen_rtx_REG (inner, regno + 1), | |
fb7e4164 | 17493 | GEN_INT (inner_bytes)); |
ded9bf77 AH |
17494 | return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r2)); |
17495 | } | |
17496 | ||
a6ebc39a AH |
17497 | /* Define how to find the value returned by a function. |
17498 | VALTYPE is the data type of the value (as a tree). | |
17499 | If the precise function being called is known, FUNC is its FUNCTION_DECL; | |
17500 | otherwise, FUNC is 0. | |
17501 | ||
17502 | On the SPE, both FPs and vectors are returned in r3. | |
17503 | ||
17504 | On RS/6000 an integer value is in r3 and a floating-point value is in | |
17505 | fp1, unless -msoft-float. */ | |
17506 | ||
17507 | rtx | |
17508 | rs6000_function_value (tree valtype, tree func ATTRIBUTE_UNUSED) | |
17509 | { | |
17510 | enum machine_mode mode; | |
2a8fa26c | 17511 | unsigned int regno; |
a6ebc39a | 17512 | |
594a51fe SS |
17513 | /* Special handling for structs in darwin64. */ |
17514 | if (rs6000_darwin64_abi | |
17515 | && TYPE_MODE (valtype) == BLKmode | |
0b5383eb DJ |
17516 | && TREE_CODE (valtype) == RECORD_TYPE |
17517 | && int_size_in_bytes (valtype) > 0) | |
594a51fe SS |
17518 | { |
17519 | CUMULATIVE_ARGS valcum; | |
17520 | rtx valret; | |
17521 | ||
0b5383eb | 17522 | valcum.words = 0; |
594a51fe SS |
17523 | valcum.fregno = FP_ARG_MIN_REG; |
17524 | valcum.vregno = ALTIVEC_ARG_MIN_REG; | |
0b5383eb DJ |
17525 | /* Do a trial code generation as if this were going to be passed as |
17526 | an argument; if any part goes in memory, we return NULL. */ | |
17527 | valret = rs6000_darwin64_record_arg (&valcum, valtype, 1, true); | |
594a51fe SS |
17528 | if (valret) |
17529 | return valret; | |
17530 | /* Otherwise fall through to standard ABI rules. */ | |
17531 | } | |
17532 | ||
0e67400a FJ |
17533 | if (TARGET_32BIT && TARGET_POWERPC64 && TYPE_MODE (valtype) == DImode) |
17534 | { | |
17535 | /* Long long return value need be split in -mpowerpc64, 32bit ABI. */ | |
17536 | return gen_rtx_PARALLEL (DImode, | |
17537 | gen_rtvec (2, | |
17538 | gen_rtx_EXPR_LIST (VOIDmode, | |
17539 | gen_rtx_REG (SImode, GP_ARG_RETURN), | |
17540 | const0_rtx), | |
17541 | gen_rtx_EXPR_LIST (VOIDmode, | |
17542 | gen_rtx_REG (SImode, | |
17543 | GP_ARG_RETURN + 1), | |
17544 | GEN_INT (4)))); | |
17545 | } | |
17546 | ||
a6ebc39a AH |
17547 | if ((INTEGRAL_TYPE_P (valtype) |
17548 | && TYPE_PRECISION (valtype) < BITS_PER_WORD) | |
17549 | || POINTER_TYPE_P (valtype)) | |
b78d48dd | 17550 | mode = TARGET_32BIT ? SImode : DImode; |
a6ebc39a AH |
17551 | else |
17552 | mode = TYPE_MODE (valtype); | |
17553 | ||
4ed78545 | 17554 | if (SCALAR_FLOAT_TYPE_P (valtype) && TARGET_HARD_FLOAT && TARGET_FPRS) |
2a8fa26c | 17555 | regno = FP_ARG_RETURN; |
ded9bf77 | 17556 | else if (TREE_CODE (valtype) == COMPLEX_TYPE |
42ba5130 | 17557 | && targetm.calls.split_complex_arg) |
ded9bf77 | 17558 | return rs6000_complex_function_value (mode); |
44688022 | 17559 | else if (TREE_CODE (valtype) == VECTOR_TYPE |
d0b2079e | 17560 | && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI |
23ba09f0 | 17561 | && ALTIVEC_VECTOR_MODE (mode)) |
a6ebc39a | 17562 | regno = ALTIVEC_ARG_RETURN; |
18f63bfa AH |
17563 | else if (TARGET_E500_DOUBLE && TARGET_HARD_FLOAT |
17564 | && (mode == DFmode || mode == DCmode)) | |
17565 | return spe_build_register_parallel (mode, GP_ARG_RETURN); | |
a6ebc39a AH |
17566 | else |
17567 | regno = GP_ARG_RETURN; | |
17568 | ||
17569 | return gen_rtx_REG (mode, regno); | |
17570 | } | |
17571 | ||
ded9bf77 AH |
17572 | /* Define how to find the value returned by a library function |
17573 | assuming the value has mode MODE. */ | |
17574 | rtx | |
17575 | rs6000_libcall_value (enum machine_mode mode) | |
17576 | { | |
17577 | unsigned int regno; | |
17578 | ||
2e6c9641 FJ |
17579 | if (TARGET_32BIT && TARGET_POWERPC64 && mode == DImode) |
17580 | { | |
17581 | /* Long long return value need be split in -mpowerpc64, 32bit ABI. */ | |
17582 | return gen_rtx_PARALLEL (DImode, | |
17583 | gen_rtvec (2, | |
17584 | gen_rtx_EXPR_LIST (VOIDmode, | |
17585 | gen_rtx_REG (SImode, GP_ARG_RETURN), | |
17586 | const0_rtx), | |
17587 | gen_rtx_EXPR_LIST (VOIDmode, | |
17588 | gen_rtx_REG (SImode, | |
17589 | GP_ARG_RETURN + 1), | |
17590 | GEN_INT (4)))); | |
17591 | } | |
17592 | ||
ded9bf77 AH |
17593 | if (GET_MODE_CLASS (mode) == MODE_FLOAT |
17594 | && TARGET_HARD_FLOAT && TARGET_FPRS) | |
17595 | regno = FP_ARG_RETURN; | |
44688022 AM |
17596 | else if (ALTIVEC_VECTOR_MODE (mode) |
17597 | && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI) | |
ded9bf77 | 17598 | regno = ALTIVEC_ARG_RETURN; |
42ba5130 | 17599 | else if (COMPLEX_MODE_P (mode) && targetm.calls.split_complex_arg) |
ded9bf77 | 17600 | return rs6000_complex_function_value (mode); |
18f63bfa AH |
17601 | else if (TARGET_E500_DOUBLE && TARGET_HARD_FLOAT |
17602 | && (mode == DFmode || mode == DCmode)) | |
17603 | return spe_build_register_parallel (mode, GP_ARG_RETURN); | |
ded9bf77 AH |
17604 | else |
17605 | regno = GP_ARG_RETURN; | |
17606 | ||
17607 | return gen_rtx_REG (mode, regno); | |
17608 | } | |
17609 | ||
d1d0c603 JJ |
17610 | /* Define the offset between two registers, FROM to be eliminated and its |
17611 | replacement TO, at the start of a routine. */ | |
17612 | HOST_WIDE_INT | |
17613 | rs6000_initial_elimination_offset (int from, int to) | |
17614 | { | |
17615 | rs6000_stack_t *info = rs6000_stack_info (); | |
17616 | HOST_WIDE_INT offset; | |
17617 | ||
17618 | if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM) | |
17619 | offset = info->push_p ? 0 : -info->total_size; | |
17620 | else if (from == ARG_POINTER_REGNUM && to == FRAME_POINTER_REGNUM) | |
17621 | offset = info->total_size; | |
17622 | else if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM) | |
17623 | offset = info->push_p ? info->total_size : 0; | |
17624 | else if (from == RS6000_PIC_OFFSET_TABLE_REGNUM) | |
17625 | offset = 0; | |
17626 | else | |
37409796 | 17627 | gcc_unreachable (); |
d1d0c603 JJ |
17628 | |
17629 | return offset; | |
17630 | } | |
17631 | ||
62e1dfcf NC |
17632 | /* Return true if TYPE is of type __ev64_opaque__. */ |
17633 | ||
c8e4f0e9 | 17634 | static bool |
a2369ed3 | 17635 | is_ev64_opaque_type (tree type) |
62e1dfcf | 17636 | { |
c8e4f0e9 | 17637 | return (TARGET_SPE |
2abe3e28 AH |
17638 | && (type == opaque_V2SI_type_node |
17639 | || type == opaque_V2SF_type_node | |
36252949 | 17640 | || type == opaque_p_V2SI_type_node)); |
62e1dfcf NC |
17641 | } |
17642 | ||
96714395 | 17643 | static rtx |
a2369ed3 | 17644 | rs6000_dwarf_register_span (rtx reg) |
96714395 AH |
17645 | { |
17646 | unsigned regno; | |
17647 | ||
4d4cbc0e AH |
17648 | if (TARGET_SPE |
17649 | && (SPE_VECTOR_MODE (GET_MODE (reg)) | |
17650 | || (TARGET_E500_DOUBLE && GET_MODE (reg) == DFmode))) | |
17651 | ; | |
17652 | else | |
96714395 AH |
17653 | return NULL_RTX; |
17654 | ||
17655 | regno = REGNO (reg); | |
17656 | ||
17657 | /* The duality of the SPE register size wreaks all kinds of havoc. | |
17658 | This is a way of distinguishing r0 in 32-bits from r0 in | |
17659 | 64-bits. */ | |
17660 | return | |
17661 | gen_rtx_PARALLEL (VOIDmode, | |
3bd104d1 AH |
17662 | BYTES_BIG_ENDIAN |
17663 | ? gen_rtvec (2, | |
17664 | gen_rtx_REG (SImode, regno + 1200), | |
17665 | gen_rtx_REG (SImode, regno)) | |
17666 | : gen_rtvec (2, | |
17667 | gen_rtx_REG (SImode, regno), | |
17668 | gen_rtx_REG (SImode, regno + 1200))); | |
96714395 AH |
17669 | } |
17670 | ||
93c9d1ba AM |
17671 | /* Map internal gcc register numbers to DWARF2 register numbers. */ |
17672 | ||
17673 | unsigned int | |
17674 | rs6000_dbx_register_number (unsigned int regno) | |
17675 | { | |
17676 | if (regno <= 63 || write_symbols != DWARF2_DEBUG) | |
17677 | return regno; | |
17678 | if (regno == MQ_REGNO) | |
17679 | return 100; | |
17680 | if (regno == LINK_REGISTER_REGNUM) | |
17681 | return 108; | |
17682 | if (regno == COUNT_REGISTER_REGNUM) | |
17683 | return 109; | |
17684 | if (CR_REGNO_P (regno)) | |
17685 | return regno - CR0_REGNO + 86; | |
17686 | if (regno == XER_REGNO) | |
17687 | return 101; | |
17688 | if (ALTIVEC_REGNO_P (regno)) | |
17689 | return regno - FIRST_ALTIVEC_REGNO + 1124; | |
17690 | if (regno == VRSAVE_REGNO) | |
17691 | return 356; | |
17692 | if (regno == VSCR_REGNO) | |
17693 | return 67; | |
17694 | if (regno == SPE_ACC_REGNO) | |
17695 | return 99; | |
17696 | if (regno == SPEFSCR_REGNO) | |
17697 | return 612; | |
17698 | /* SPE high reg number. We get these values of regno from | |
17699 | rs6000_dwarf_register_span. */ | |
37409796 NS |
17700 | gcc_assert (regno >= 1200 && regno < 1232); |
17701 | return regno; | |
93c9d1ba AM |
17702 | } |
17703 | ||
93f90be6 | 17704 | /* target hook eh_return_filter_mode */ |
f676971a | 17705 | static enum machine_mode |
93f90be6 FJ |
17706 | rs6000_eh_return_filter_mode (void) |
17707 | { | |
17708 | return TARGET_32BIT ? SImode : word_mode; | |
17709 | } | |
17710 | ||
f676971a EC |
17711 | /* Target hook for vector_mode_supported_p. */ |
17712 | static bool | |
17713 | rs6000_vector_mode_supported_p (enum machine_mode mode) | |
17714 | { | |
17715 | ||
17716 | if (TARGET_SPE && SPE_VECTOR_MODE (mode)) | |
17717 | return true; | |
17718 | ||
17719 | else if (TARGET_ALTIVEC && ALTIVEC_VECTOR_MODE (mode)) | |
17720 | return true; | |
17721 | ||
17722 | else | |
17723 | return false; | |
17724 | } | |
17725 | ||
4d3e6fae FJ |
17726 | /* Target hook for invalid_arg_for_unprototyped_fn. */ |
17727 | static const char * | |
17728 | invalid_arg_for_unprototyped_fn (tree typelist, tree funcdecl, tree val) | |
17729 | { | |
17730 | return (!rs6000_darwin64_abi | |
17731 | && typelist == 0 | |
17732 | && TREE_CODE (TREE_TYPE (val)) == VECTOR_TYPE | |
17733 | && (funcdecl == NULL_TREE | |
17734 | || (TREE_CODE (funcdecl) == FUNCTION_DECL | |
17735 | && DECL_BUILT_IN_CLASS (funcdecl) != BUILT_IN_MD))) | |
17736 | ? N_("AltiVec argument passed to unprototyped function") | |
17737 | : NULL; | |
17738 | } | |
17739 | ||
17211ab5 | 17740 | #include "gt-rs6000.h" |