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9878760c 1/* Subroutines used for code generation on IBM RS/6000.
f676971a 2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
5b86a469 3 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
fab3bcc3 4 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
9878760c 5
5de601cf 6 This file is part of GCC.
9878760c 7
5de601cf
NC		 8 GCC is free software; you can redistribute it and/or modify it
9 under the terms of the GNU General Public License as published
10 by the Free Software Foundation; either version 2, or (at your
11 option) any later version.
9878760c 12
5de601cf
NC		 13 GCC is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
9878760c 17
5de601cf
NC		 18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING. If not, write to the
20 Free Software Foundation, 59 Temple Place - Suite 330, Boston,
21 MA 02111-1307, USA. */
9878760c 22
956d6950 23#include "config.h"
c4d38ccb 24#include "system.h"
4977bab6
ZW		 25#include "coretypes.h"
26#include "tm.h"
9878760c
RK		 27#include "rtl.h"
28#include "regs.h"
29#include "hard-reg-set.h"
30#include "real.h"
31#include "insn-config.h"
32#include "conditions.h"
9878760c
RK		 33#include "insn-attr.h"
34#include "flags.h"
35#include "recog.h"
9878760c 36#include "obstack.h"
9b30bae2 37#include "tree.h"
dfafc897 38#include "expr.h"
2fc1c679 39#include "optabs.h"
2a430ec1 40#include "except.h"
a7df97e6 41#include "function.h"
296b8152 42#include "output.h"
d5fa86ba 43#include "basic-block.h"
d0101753 44#include "integrate.h"
296b8152 45#include "toplev.h"
c8023011 46#include "ggc.h"
9ebbca7d
GK		 47#include "hashtab.h"
48#include "tm_p.h"
672a6f42
NB		 49#include "target.h"
50#include "target-def.h"
3ac88239 51#include "langhooks.h"
24ea750e 52#include "reload.h"
117dca74 53#include "cfglayout.h"
79ae11c4 54#include "sched-int.h"
cd3ce9b4 55#include "tree-gimple.h"
4d3e6fae 56#include "intl.h"
1bc7c5b6
ZW		 57#if TARGET_XCOFF
58#include "xcoffout.h" /* get declarations of xcoff_*_section_name */
59#endif
93a27b7b
ZW		 60#if TARGET_MACHO
61#include "gstab.h" /* for N_SLINE */
62#endif
9b30bae2 63
7509c759
MM		 64#ifndef TARGET_NO_PROTOTYPE
65#define TARGET_NO_PROTOTYPE 0
66#endif
67
9878760c
RK		 68#define min(A,B) ((A) < (B) ? (A) : (B))
69#define max(A,B) ((A) > (B) ? (A) : (B))
70
d1d0c603
JJ		 71/* Structure used to define the rs6000 stack */
72typedef struct rs6000_stack {
73 int first_gp_reg_save; /* first callee saved GP register used */
74 int first_fp_reg_save; /* first callee saved FP register used */
75 int first_altivec_reg_save; /* first callee saved AltiVec register used */
76 int lr_save_p; /* true if the link reg needs to be saved */
77 int cr_save_p; /* true if the CR reg needs to be saved */
78 unsigned int vrsave_mask; /* mask of vec registers to save */
79 int toc_save_p; /* true if the TOC needs to be saved */
80 int push_p; /* true if we need to allocate stack space */
81 int calls_p; /* true if the function makes any calls */
c4ad648e 82 int world_save_p; /* true if we're saving *everything*:
d62294f5 83 r13-r31, cr, f14-f31, vrsave, v20-v31 */
d1d0c603
JJ		 84 enum rs6000_abi abi; /* which ABI to use */
85 int gp_save_offset; /* offset to save GP regs from initial SP */
86 int fp_save_offset; /* offset to save FP regs from initial SP */
87 int altivec_save_offset; /* offset to save AltiVec regs from initial SP */
88 int lr_save_offset; /* offset to save LR from initial SP */
89 int cr_save_offset; /* offset to save CR from initial SP */
90 int vrsave_save_offset; /* offset to save VRSAVE from initial SP */
91 int spe_gp_save_offset; /* offset to save spe 64-bit gprs */
92 int toc_save_offset; /* offset to save the TOC pointer */
93 int varargs_save_offset; /* offset to save the varargs registers */
94 int ehrd_offset; /* offset to EH return data */
95 int reg_size; /* register size (4 or 8) */
96 int varargs_size; /* size to hold V.4 args passed in regs */
97 HOST_WIDE_INT vars_size; /* variable save area size */
98 int parm_size; /* outgoing parameter size */
99 int save_size; /* save area size */
100 int fixed_size; /* fixed size of stack frame */
101 int gp_size; /* size of saved GP registers */
102 int fp_size; /* size of saved FP registers */
103 int altivec_size; /* size of saved AltiVec registers */
104 int cr_size; /* size to hold CR if not in save_size */
105 int lr_size; /* size to hold LR if not in save_size */
106 int vrsave_size; /* size to hold VRSAVE if not in save_size */
107 int altivec_padding_size; /* size of altivec alignment padding if
108 not in save_size */
109 int spe_gp_size; /* size of 64-bit GPR save size for SPE */
110 int spe_padding_size;
111 int toc_size; /* size to hold TOC if not in save_size */
112 HOST_WIDE_INT total_size; /* total bytes allocated for stack */
113 int spe_64bit_regs_used;
114} rs6000_stack_t;
115
5248c961
RK		 116/* Target cpu type */
117
118enum processor_type rs6000_cpu;
8e3f41e7
MM		 119struct rs6000_cpu_select rs6000_select[3] =
120{
815cdc52
MM		 121 /* switch name, tune arch */
122 { (const char *)0, "--with-cpu=", 1, 1 },
123 { (const char *)0, "-mcpu=", 1, 1 },
124 { (const char *)0, "-mtune=", 1, 0 },
8e3f41e7 125};
5248c961 126
ec507f2d
DE		 127/* Always emit branch hint bits. */
128static GTY(()) bool rs6000_always_hint;
129
130/* Schedule instructions for group formation. */
131static GTY(()) bool rs6000_sched_groups;
132
f676971a 133/* Support adjust_priority scheduler hook
79ae11c4
DN		 134 and -mprioritize-restricted-insns= option. */
135const char *rs6000_sched_restricted_insns_priority_str;
136int rs6000_sched_restricted_insns_priority;
137
569fa502
DN		 138/* Support for -msched-costly-dep option. */
139const char *rs6000_sched_costly_dep_str;
140enum rs6000_dependence_cost rs6000_sched_costly_dep;
141
cbe26ab8
DN		 142/* Support for -minsert-sched-nops option. */
143const char *rs6000_sched_insert_nops_str;
144enum rs6000_nop_insertion rs6000_sched_insert_nops;
145
7ccf35ed 146/* Support targetm.vectorize.builtin_mask_for_load. */
13c62176 147static GTY(()) tree altivec_builtin_mask_for_load;
7ccf35ed 148
6fa3f289
ZW		 149/* Size of long double */
150const char *rs6000_long_double_size_string;
151int rs6000_long_double_type_size;
152
153/* Whether -mabi=altivec has appeared */
154int rs6000_altivec_abi;
155
08b57fb3
AH		 156/* Whether VRSAVE instructions should be generated. */
157int rs6000_altivec_vrsave;
158
159/* String from -mvrsave= option. */
160const char *rs6000_altivec_vrsave_string;
161
a3170dc6
AH		 162/* Nonzero if we want SPE ABI extensions. */
163int rs6000_spe_abi;
164
165/* Whether isel instructions should be generated. */
166int rs6000_isel;
167
993f19a8
AH		 168/* Whether SPE simd instructions should be generated. */
169int rs6000_spe;
170
5da702b1
AH		 171/* Nonzero if floating point operations are done in the GPRs. */
172int rs6000_float_gprs = 0;
173
594a51fe
SS		 174/* Nonzero if we want Darwin's struct-by-value-in-regs ABI. */
175int rs6000_darwin64_abi;
176
5da702b1
AH		 177/* String from -mfloat-gprs=. */
178const char *rs6000_float_gprs_string;
a3170dc6
AH		 179
180/* String from -misel=. */
181const char *rs6000_isel_string;
182
993f19a8
AH		 183/* String from -mspe=. */
184const char *rs6000_spe_string;
185
a0ab749a 186/* Set to nonzero once AIX common-mode calls have been defined. */
bbfb86aa 187static GTY(()) int common_mode_defined;
c81bebd7 188
9878760c
RK		 189/* Save information from a "cmpxx" operation until the branch or scc is
190 emitted. */
9878760c
RK		 191rtx rs6000_compare_op0, rs6000_compare_op1;
192int rs6000_compare_fp_p;
874a0744 193
874a0744
MM		 194/* Label number of label created for -mrelocatable, to call to so we can
195 get the address of the GOT section */
196int rs6000_pic_labelno;
c81bebd7 197
b91da81f 198#ifdef USING_ELFOS_H
c81bebd7 199/* Which abi to adhere to */
9739c90c 200const char *rs6000_abi_name;
d9407988
MM		 201
202/* Semantics of the small data area */
203enum rs6000_sdata_type rs6000_sdata = SDATA_DATA;
204
205/* Which small data model to use */
815cdc52 206const char *rs6000_sdata_name = (char *)0;
9ebbca7d
GK		 207
208/* Counter for labels which are to be placed in .fixup. */
209int fixuplabelno = 0;
874a0744 210#endif
4697a36c 211
c4501e62
JJ		 212/* Bit size of immediate TLS offsets and string from which it is decoded. */
213int rs6000_tls_size = 32;
214const char *rs6000_tls_size_string;
215
b6c9286a
MM		 216/* ABI enumeration available for subtarget to use. */
217enum rs6000_abi rs6000_current_abi;
218
0ac081f6
AH		 219/* ABI string from -mabi= option. */
220const char *rs6000_abi_string;
221
85b776df
AM		 222/* Whether to use variant of AIX ABI for PowerPC64 Linux. */
223int dot_symbols;
224
38c1f2d7 225/* Debug flags */
815cdc52 226const char *rs6000_debug_name;
38c1f2d7
MM		 227int rs6000_debug_stack; /* debug stack applications */
228int rs6000_debug_arg; /* debug argument handling */
229
0d1fbc8c
AH		 230/* Value is TRUE if register/mode pair is accepatable. */
231bool rs6000_hard_regno_mode_ok_p[NUM_MACHINE_MODES][FIRST_PSEUDO_REGISTER];
232
6035d635 233/* Opaque types. */
2abe3e28 234static GTY(()) tree opaque_V2SI_type_node;
2abe3e28 235static GTY(()) tree opaque_V2SF_type_node;
6035d635 236static GTY(()) tree opaque_p_V2SI_type_node;
4a5eab38
PB		 237static GTY(()) tree V16QI_type_node;
238static GTY(()) tree V2SI_type_node;
239static GTY(()) tree V2SF_type_node;
240static GTY(()) tree V4HI_type_node;
241static GTY(()) tree V4SI_type_node;
242static GTY(()) tree V4SF_type_node;
243static GTY(()) tree V8HI_type_node;
244static GTY(()) tree unsigned_V16QI_type_node;
245static GTY(()) tree unsigned_V8HI_type_node;
246static GTY(()) tree unsigned_V4SI_type_node;
8bb418a3
ZL		 247static GTY(()) tree bool_char_type_node; /* __bool char */
248static GTY(()) tree bool_short_type_node; /* __bool short */
249static GTY(()) tree bool_int_type_node; /* __bool int */
250static GTY(()) tree pixel_type_node; /* __pixel */
251static GTY(()) tree bool_V16QI_type_node; /* __vector __bool char */
252static GTY(()) tree bool_V8HI_type_node; /* __vector __bool short */
253static GTY(()) tree bool_V4SI_type_node; /* __vector __bool int */
254static GTY(()) tree pixel_V8HI_type_node; /* __vector __pixel */
255
256int rs6000_warn_altivec_long = 1; /* On by default. */
257const char *rs6000_warn_altivec_long_switch;
258
57ac7be9
AM		 259const char *rs6000_traceback_name;
260static enum {
261 traceback_default = 0,
262 traceback_none,
263 traceback_part,
264 traceback_full
265} rs6000_traceback;
266
38c1f2d7
MM		 267/* Flag to say the TOC is initialized */
268int toc_initialized;
9ebbca7d 269char toc_label_name[10];
38c1f2d7 270
9ebbca7d 271/* Alias set for saves and restores from the rs6000 stack. */
f103e34d 272static GTY(()) int rs6000_sr_alias_set;
c8023011 273
a5c76ee6
ZW		 274/* Call distance, overridden by -mlongcall and #pragma longcall(1).
275 The only place that looks at this is rs6000_set_default_type_attributes;
276 everywhere else should rely on the presence or absence of a longcall
3eb4e360
AM		 277 attribute on the function declaration. Exception: init_cumulative_args
278 looks at it too, for libcalls. */
a5c76ee6
ZW		 279int rs6000_default_long_calls;
280const char *rs6000_longcall_switch;
281
a3c9585f
KH		 282/* Control alignment for fields within structures. */
283/* String from -malign-XXXXX. */
025d9908
KH		 284const char *rs6000_alignment_string;
285int rs6000_alignment_flags;
286
a3170dc6
AH		 287struct builtin_description
288{
289 /* mask is not const because we're going to alter it below. This
290 nonsense will go away when we rewrite the -march infrastructure
291 to give us more target flag bits. */
292 unsigned int mask;
293 const enum insn_code icode;
294 const char *const name;
295 const enum rs6000_builtins code;
296};
8b897cfa
RS		 297\f
298/* Target cpu costs. */
299
300struct processor_costs {
c4ad648e 301 const int mulsi; /* cost of SImode multiplication. */
8b897cfa
RS		 302 const int mulsi_const; /* cost of SImode multiplication by constant. */
303 const int mulsi_const9; /* cost of SImode mult by short constant. */
c4ad648e
AM		 304 const int muldi; /* cost of DImode multiplication. */
305 const int divsi; /* cost of SImode division. */
306 const int divdi; /* cost of DImode division. */
307 const int fp; /* cost of simple SFmode and DFmode insns. */
308 const int dmul; /* cost of DFmode multiplication (and fmadd). */
309 const int sdiv; /* cost of SFmode division (fdivs). */
310 const int ddiv; /* cost of DFmode division (fdiv). */
8b897cfa
RS		 311};
312
313const struct processor_costs *rs6000_cost;
314
315/* Processor costs (relative to an add) */
316
317/* Instruction size costs on 32bit processors. */
318static const
319struct processor_costs size32_cost = {
06a67bdd
RS		 320 COSTS_N_INSNS (1), /* mulsi */
321 COSTS_N_INSNS (1), /* mulsi_const */
322 COSTS_N_INSNS (1), /* mulsi_const9 */
323 COSTS_N_INSNS (1), /* muldi */
324 COSTS_N_INSNS (1), /* divsi */
325 COSTS_N_INSNS (1), /* divdi */
326 COSTS_N_INSNS (1), /* fp */
327 COSTS_N_INSNS (1), /* dmul */
328 COSTS_N_INSNS (1), /* sdiv */
329 COSTS_N_INSNS (1), /* ddiv */
8b897cfa
RS		 330};
331
332/* Instruction size costs on 64bit processors. */
333static const
334struct processor_costs size64_cost = {
06a67bdd
RS		 335 COSTS_N_INSNS (1), /* mulsi */
336 COSTS_N_INSNS (1), /* mulsi_const */
337 COSTS_N_INSNS (1), /* mulsi_const9 */
338 COSTS_N_INSNS (1), /* muldi */
339 COSTS_N_INSNS (1), /* divsi */
340 COSTS_N_INSNS (1), /* divdi */
341 COSTS_N_INSNS (1), /* fp */
342 COSTS_N_INSNS (1), /* dmul */
343 COSTS_N_INSNS (1), /* sdiv */
344 COSTS_N_INSNS (1), /* ddiv */
8b897cfa
RS		 345};
346
347/* Instruction costs on RIOS1 processors. */
348static const
349struct processor_costs rios1_cost = {
06a67bdd
RS		 350 COSTS_N_INSNS (5), /* mulsi */
351 COSTS_N_INSNS (4), /* mulsi_const */
352 COSTS_N_INSNS (3), /* mulsi_const9 */
353 COSTS_N_INSNS (5), /* muldi */
354 COSTS_N_INSNS (19), /* divsi */
355 COSTS_N_INSNS (19), /* divdi */
356 COSTS_N_INSNS (2), /* fp */
357 COSTS_N_INSNS (2), /* dmul */
358 COSTS_N_INSNS (19), /* sdiv */
359 COSTS_N_INSNS (19), /* ddiv */
8b897cfa
RS		 360};
361
362/* Instruction costs on RIOS2 processors. */
363static const
364struct processor_costs rios2_cost = {
06a67bdd
RS		 365 COSTS_N_INSNS (2), /* mulsi */
366 COSTS_N_INSNS (2), /* mulsi_const */
367 COSTS_N_INSNS (2), /* mulsi_const9 */
368 COSTS_N_INSNS (2), /* muldi */
369 COSTS_N_INSNS (13), /* divsi */
370 COSTS_N_INSNS (13), /* divdi */
371 COSTS_N_INSNS (2), /* fp */
372 COSTS_N_INSNS (2), /* dmul */
373 COSTS_N_INSNS (17), /* sdiv */
374 COSTS_N_INSNS (17), /* ddiv */
8b897cfa
RS		 375};
376
377/* Instruction costs on RS64A processors. */
378static const
379struct processor_costs rs64a_cost = {
06a67bdd
RS		 380 COSTS_N_INSNS (20), /* mulsi */
381 COSTS_N_INSNS (12), /* mulsi_const */
382 COSTS_N_INSNS (8), /* mulsi_const9 */
383 COSTS_N_INSNS (34), /* muldi */
384 COSTS_N_INSNS (65), /* divsi */
385 COSTS_N_INSNS (67), /* divdi */
386 COSTS_N_INSNS (4), /* fp */
387 COSTS_N_INSNS (4), /* dmul */
388 COSTS_N_INSNS (31), /* sdiv */
389 COSTS_N_INSNS (31), /* ddiv */
8b897cfa
RS		 390};
391
392/* Instruction costs on MPCCORE processors. */
393static const
394struct processor_costs mpccore_cost = {
06a67bdd
RS		 395 COSTS_N_INSNS (2), /* mulsi */
396 COSTS_N_INSNS (2), /* mulsi_const */
397 COSTS_N_INSNS (2), /* mulsi_const9 */
398 COSTS_N_INSNS (2), /* muldi */
399 COSTS_N_INSNS (6), /* divsi */
400 COSTS_N_INSNS (6), /* divdi */
401 COSTS_N_INSNS (4), /* fp */
402 COSTS_N_INSNS (5), /* dmul */
403 COSTS_N_INSNS (10), /* sdiv */
404 COSTS_N_INSNS (17), /* ddiv */
8b897cfa
RS		 405};
406
407/* Instruction costs on PPC403 processors. */
408static const
409struct processor_costs ppc403_cost = {
06a67bdd
RS		 410 COSTS_N_INSNS (4), /* mulsi */
411 COSTS_N_INSNS (4), /* mulsi_const */
412 COSTS_N_INSNS (4), /* mulsi_const9 */
413 COSTS_N_INSNS (4), /* muldi */
414 COSTS_N_INSNS (33), /* divsi */
415 COSTS_N_INSNS (33), /* divdi */
416 COSTS_N_INSNS (11), /* fp */
417 COSTS_N_INSNS (11), /* dmul */
418 COSTS_N_INSNS (11), /* sdiv */
419 COSTS_N_INSNS (11), /* ddiv */
8b897cfa
RS		 420};
421
422/* Instruction costs on PPC405 processors. */
423static const
424struct processor_costs ppc405_cost = {
06a67bdd
RS		 425 COSTS_N_INSNS (5), /* mulsi */
426 COSTS_N_INSNS (4), /* mulsi_const */
427 COSTS_N_INSNS (3), /* mulsi_const9 */
428 COSTS_N_INSNS (5), /* muldi */
429 COSTS_N_INSNS (35), /* divsi */
430 COSTS_N_INSNS (35), /* divdi */
431 COSTS_N_INSNS (11), /* fp */
432 COSTS_N_INSNS (11), /* dmul */
433 COSTS_N_INSNS (11), /* sdiv */
434 COSTS_N_INSNS (11), /* ddiv */
8b897cfa
RS		 435};
436
437/* Instruction costs on PPC440 processors. */
438static const
439struct processor_costs ppc440_cost = {
06a67bdd
RS		 440 COSTS_N_INSNS (3), /* mulsi */
441 COSTS_N_INSNS (2), /* mulsi_const */
442 COSTS_N_INSNS (2), /* mulsi_const9 */
443 COSTS_N_INSNS (3), /* muldi */
444 COSTS_N_INSNS (34), /* divsi */
445 COSTS_N_INSNS (34), /* divdi */
446 COSTS_N_INSNS (5), /* fp */
447 COSTS_N_INSNS (5), /* dmul */
448 COSTS_N_INSNS (19), /* sdiv */
449 COSTS_N_INSNS (33), /* ddiv */
8b897cfa
RS		 450};
451
452/* Instruction costs on PPC601 processors. */
453static const
454struct processor_costs ppc601_cost = {
06a67bdd
RS		 455 COSTS_N_INSNS (5), /* mulsi */
456 COSTS_N_INSNS (5), /* mulsi_const */
457 COSTS_N_INSNS (5), /* mulsi_const9 */
458 COSTS_N_INSNS (5), /* muldi */
459 COSTS_N_INSNS (36), /* divsi */
460 COSTS_N_INSNS (36), /* divdi */
461 COSTS_N_INSNS (4), /* fp */
462 COSTS_N_INSNS (5), /* dmul */
463 COSTS_N_INSNS (17), /* sdiv */
464 COSTS_N_INSNS (31), /* ddiv */
8b897cfa
RS		 465};
466
467/* Instruction costs on PPC603 processors. */
468static const
469struct processor_costs ppc603_cost = {
06a67bdd
RS		 470 COSTS_N_INSNS (5), /* mulsi */
471 COSTS_N_INSNS (3), /* mulsi_const */
472 COSTS_N_INSNS (2), /* mulsi_const9 */
473 COSTS_N_INSNS (5), /* muldi */
474 COSTS_N_INSNS (37), /* divsi */
475 COSTS_N_INSNS (37), /* divdi */
476 COSTS_N_INSNS (3), /* fp */
477 COSTS_N_INSNS (4), /* dmul */
478 COSTS_N_INSNS (18), /* sdiv */
479 COSTS_N_INSNS (33), /* ddiv */
8b897cfa
RS		 480};
481
482/* Instruction costs on PPC604 processors. */
483static const
484struct processor_costs ppc604_cost = {
06a67bdd
RS		 485 COSTS_N_INSNS (4), /* mulsi */
486 COSTS_N_INSNS (4), /* mulsi_const */
487 COSTS_N_INSNS (4), /* mulsi_const9 */
488 COSTS_N_INSNS (4), /* muldi */
489 COSTS_N_INSNS (20), /* divsi */
490 COSTS_N_INSNS (20), /* divdi */
491 COSTS_N_INSNS (3), /* fp */
492 COSTS_N_INSNS (3), /* dmul */
493 COSTS_N_INSNS (18), /* sdiv */
494 COSTS_N_INSNS (32), /* ddiv */
8b897cfa
RS		 495};
496
497/* Instruction costs on PPC604e processors. */
498static const
499struct processor_costs ppc604e_cost = {
06a67bdd
RS		 500 COSTS_N_INSNS (2), /* mulsi */
501 COSTS_N_INSNS (2), /* mulsi_const */
502 COSTS_N_INSNS (2), /* mulsi_const9 */
503 COSTS_N_INSNS (2), /* muldi */
504 COSTS_N_INSNS (20), /* divsi */
505 COSTS_N_INSNS (20), /* divdi */
506 COSTS_N_INSNS (3), /* fp */
507 COSTS_N_INSNS (3), /* dmul */
508 COSTS_N_INSNS (18), /* sdiv */
509 COSTS_N_INSNS (32), /* ddiv */
8b897cfa
RS		 510};
511
f0517163 512/* Instruction costs on PPC620 processors. */
8b897cfa
RS		 513static const
514struct processor_costs ppc620_cost = {
06a67bdd
RS		 515 COSTS_N_INSNS (5), /* mulsi */
516 COSTS_N_INSNS (4), /* mulsi_const */
517 COSTS_N_INSNS (3), /* mulsi_const9 */
518 COSTS_N_INSNS (7), /* muldi */
519 COSTS_N_INSNS (21), /* divsi */
520 COSTS_N_INSNS (37), /* divdi */
521 COSTS_N_INSNS (3), /* fp */
522 COSTS_N_INSNS (3), /* dmul */
523 COSTS_N_INSNS (18), /* sdiv */
524 COSTS_N_INSNS (32), /* ddiv */
f0517163
RS		 525};
526
527/* Instruction costs on PPC630 processors. */
528static const
529struct processor_costs ppc630_cost = {
06a67bdd
RS		 530 COSTS_N_INSNS (5), /* mulsi */
531 COSTS_N_INSNS (4), /* mulsi_const */
532 COSTS_N_INSNS (3), /* mulsi_const9 */
533 COSTS_N_INSNS (7), /* muldi */
534 COSTS_N_INSNS (21), /* divsi */
535 COSTS_N_INSNS (37), /* divdi */
536 COSTS_N_INSNS (3), /* fp */
537 COSTS_N_INSNS (3), /* dmul */
538 COSTS_N_INSNS (17), /* sdiv */
539 COSTS_N_INSNS (21), /* ddiv */
8b897cfa
RS		 540};
541
542/* Instruction costs on PPC750 and PPC7400 processors. */
543static const
544struct processor_costs ppc750_cost = {
06a67bdd
RS		 545 COSTS_N_INSNS (5), /* mulsi */
546 COSTS_N_INSNS (3), /* mulsi_const */
547 COSTS_N_INSNS (2), /* mulsi_const9 */
548 COSTS_N_INSNS (5), /* muldi */
549 COSTS_N_INSNS (17), /* divsi */
550 COSTS_N_INSNS (17), /* divdi */
551 COSTS_N_INSNS (3), /* fp */
552 COSTS_N_INSNS (3), /* dmul */
553 COSTS_N_INSNS (17), /* sdiv */
554 COSTS_N_INSNS (31), /* ddiv */
8b897cfa
RS		 555};
556
557/* Instruction costs on PPC7450 processors. */
558static const
559struct processor_costs ppc7450_cost = {
06a67bdd
RS		 560 COSTS_N_INSNS (4), /* mulsi */
561 COSTS_N_INSNS (3), /* mulsi_const */
562 COSTS_N_INSNS (3), /* mulsi_const9 */
563 COSTS_N_INSNS (4), /* muldi */
564 COSTS_N_INSNS (23), /* divsi */
565 COSTS_N_INSNS (23), /* divdi */
566 COSTS_N_INSNS (5), /* fp */
567 COSTS_N_INSNS (5), /* dmul */
568 COSTS_N_INSNS (21), /* sdiv */
569 COSTS_N_INSNS (35), /* ddiv */
8b897cfa 570};
a3170dc6 571
8b897cfa
RS		 572/* Instruction costs on PPC8540 processors. */
573static const
574struct processor_costs ppc8540_cost = {
06a67bdd
RS		 575 COSTS_N_INSNS (4), /* mulsi */
576 COSTS_N_INSNS (4), /* mulsi_const */
577 COSTS_N_INSNS (4), /* mulsi_const9 */
578 COSTS_N_INSNS (4), /* muldi */
579 COSTS_N_INSNS (19), /* divsi */
580 COSTS_N_INSNS (19), /* divdi */
581 COSTS_N_INSNS (4), /* fp */
582 COSTS_N_INSNS (4), /* dmul */
583 COSTS_N_INSNS (29), /* sdiv */
584 COSTS_N_INSNS (29), /* ddiv */
8b897cfa
RS		 585};
586
587/* Instruction costs on POWER4 and POWER5 processors. */
588static const
589struct processor_costs power4_cost = {
06a67bdd
RS		 590 COSTS_N_INSNS (3), /* mulsi */
591 COSTS_N_INSNS (2), /* mulsi_const */
592 COSTS_N_INSNS (2), /* mulsi_const9 */
593 COSTS_N_INSNS (4), /* muldi */
594 COSTS_N_INSNS (18), /* divsi */
595 COSTS_N_INSNS (34), /* divdi */
596 COSTS_N_INSNS (3), /* fp */
597 COSTS_N_INSNS (3), /* dmul */
598 COSTS_N_INSNS (17), /* sdiv */
599 COSTS_N_INSNS (17), /* ddiv */
8b897cfa
RS		 600};
601
602\f
a2369ed3 603static bool rs6000_function_ok_for_sibcall (tree, tree);
a2369ed3
DJ		 604static rtx rs6000_generate_compare (enum rtx_code);
605static void rs6000_maybe_dead (rtx);
606static void rs6000_emit_stack_tie (void);
607static void rs6000_frame_related (rtx, rtx, HOST_WIDE_INT, rtx, rtx);
608static rtx spe_synthesize_frame_save (rtx);
609static bool spe_func_has_64bit_regs_p (void);
b20a9cca 610static void emit_frame_save (rtx, rtx, enum machine_mode, unsigned int,
d1d0c603 611 int, HOST_WIDE_INT);
a2369ed3
DJ		 612static rtx gen_frame_mem_offset (enum machine_mode, rtx, int);
613static void rs6000_emit_allocate_stack (HOST_WIDE_INT, int);
614static unsigned rs6000_hash_constant (rtx);
615static unsigned toc_hash_function (const void *);
616static int toc_hash_eq (const void *, const void *);
617static int constant_pool_expr_1 (rtx, int *, int *);
618static bool constant_pool_expr_p (rtx);
a2369ed3 619static bool legitimate_small_data_p (enum machine_mode, rtx);
a2369ed3 620static bool legitimate_indexed_address_p (rtx, int);
a2369ed3
DJ		 621static bool legitimate_lo_sum_address_p (enum machine_mode, rtx, int);
622static struct machine_function * rs6000_init_machine_status (void);
623static bool rs6000_assemble_integer (rtx, unsigned int, int);
5add3202 624#ifdef HAVE_GAS_HIDDEN
a2369ed3 625static void rs6000_assemble_visibility (tree, int);
5add3202 626#endif
a2369ed3
DJ		 627static int rs6000_ra_ever_killed (void);
628static tree rs6000_handle_longcall_attribute (tree *, tree, tree, int, bool *);
8bb418a3 629static tree rs6000_handle_altivec_attribute (tree *, tree, tree, int, bool *);
76d2b81d 630static void rs6000_eliminate_indexed_memrefs (rtx operands[2]);
f18eca82 631static const char *rs6000_mangle_fundamental_type (tree);
b86fe7b4 632extern const struct attribute_spec rs6000_attribute_table[];
a2369ed3
DJ		 633static void rs6000_set_default_type_attributes (tree);
634static void rs6000_output_function_prologue (FILE *, HOST_WIDE_INT);
635static void rs6000_output_function_epilogue (FILE *, HOST_WIDE_INT);
b20a9cca
AM		 636static void rs6000_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT,
637 tree);
a2369ed3 638static rtx rs6000_emit_set_long_const (rtx, HOST_WIDE_INT, HOST_WIDE_INT);
c6e8c921 639static bool rs6000_return_in_memory (tree, tree);
a2369ed3 640static void rs6000_file_start (void);
7c262518 641#if TARGET_ELF
a2369ed3
DJ		 642static unsigned int rs6000_elf_section_type_flags (tree, const char *, int);
643static void rs6000_elf_asm_out_constructor (rtx, int);
644static void rs6000_elf_asm_out_destructor (rtx, int);
645static void rs6000_elf_select_section (tree, int, unsigned HOST_WIDE_INT);
646static void rs6000_elf_unique_section (tree, int);
647static void rs6000_elf_select_rtx_section (enum machine_mode, rtx,
b20a9cca 648 unsigned HOST_WIDE_INT);
a56d7372 649static void rs6000_elf_encode_section_info (tree, rtx, int)
0e5dbd9b 650 ATTRIBUTE_UNUSED;
a2369ed3 651static bool rs6000_elf_in_small_data_p (tree);
7c262518 652#endif
cbaaba19 653#if TARGET_XCOFF
a2369ed3 654static void rs6000_xcoff_asm_globalize_label (FILE *, const char *);
8210e4c4 655static void rs6000_xcoff_asm_named_section (const char *, unsigned int, tree);
a2369ed3
DJ		 656static void rs6000_xcoff_select_section (tree, int, unsigned HOST_WIDE_INT);
657static void rs6000_xcoff_unique_section (tree, int);
658static void rs6000_xcoff_select_rtx_section (enum machine_mode, rtx,
b20a9cca 659 unsigned HOST_WIDE_INT);
a2369ed3
DJ		 660static const char * rs6000_xcoff_strip_name_encoding (const char *);
661static unsigned int rs6000_xcoff_section_type_flags (tree, const char *, int);
662static void rs6000_xcoff_file_start (void);
663static void rs6000_xcoff_file_end (void);
f1384257
AM		 664#endif
665#if TARGET_MACHO
a2369ed3 666static bool rs6000_binds_local_p (tree);
f1384257 667#endif
a2369ed3
DJ		 668static int rs6000_variable_issue (FILE *, int, rtx, int);
669static bool rs6000_rtx_costs (rtx, int, int, int *);
670static int rs6000_adjust_cost (rtx, rtx, rtx, int);
cbe26ab8 671static bool is_microcoded_insn (rtx);
79ae11c4 672static int is_dispatch_slot_restricted (rtx);
cbe26ab8
DN		 673static bool is_cracked_insn (rtx);
674static bool is_branch_slot_insn (rtx);
a2369ed3
DJ		 675static int rs6000_adjust_priority (rtx, int);
676static int rs6000_issue_rate (void);
569fa502 677static bool rs6000_is_costly_dependence (rtx, rtx, rtx, int, int);
cbe26ab8
DN		 678static rtx get_next_active_insn (rtx, rtx);
679static bool insn_terminates_group_p (rtx , enum group_termination);
680static bool is_costly_group (rtx *, rtx);
681static int force_new_group (int, FILE *, rtx *, rtx, bool *, int, int *);
682static int redefine_groups (FILE *, int, rtx, rtx);
683static int pad_groups (FILE *, int, rtx, rtx);
684static void rs6000_sched_finish (FILE *, int);
a2369ed3 685static int rs6000_use_sched_lookahead (void);
7ccf35ed 686static tree rs6000_builtin_mask_for_load (void);
a2369ed3
DJ		 687
688static void rs6000_init_builtins (void);
689static rtx rs6000_expand_unop_builtin (enum insn_code, tree, rtx);
690static rtx rs6000_expand_binop_builtin (enum insn_code, tree, rtx);
691static rtx rs6000_expand_ternop_builtin (enum insn_code, tree, rtx);
692static rtx rs6000_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
693static void altivec_init_builtins (void);
694static void rs6000_common_init_builtins (void);
c15c90bb 695static void rs6000_init_libfuncs (void);
a2369ed3 696
b20a9cca
AM		 697static void enable_mask_for_builtins (struct builtin_description *, int,
698 enum rs6000_builtins,
699 enum rs6000_builtins);
7c62e993 700static tree build_opaque_vector_type (tree, int);
a2369ed3
DJ		 701static void spe_init_builtins (void);
702static rtx spe_expand_builtin (tree, rtx, bool *);
61bea3b0 703static rtx spe_expand_stv_builtin (enum insn_code, tree);
a2369ed3
DJ		 704static rtx spe_expand_predicate_builtin (enum insn_code, tree, rtx);
705static rtx spe_expand_evsel_builtin (enum insn_code, tree, rtx);
706static int rs6000_emit_int_cmove (rtx, rtx, rtx, rtx);
d1d0c603
JJ		 707static rs6000_stack_t *rs6000_stack_info (void);
708static void debug_stack_info (rs6000_stack_t *);
a2369ed3
DJ		 709
710static rtx altivec_expand_builtin (tree, rtx, bool *);
711static rtx altivec_expand_ld_builtin (tree, rtx, bool *);
712static rtx altivec_expand_st_builtin (tree, rtx, bool *);
713static rtx altivec_expand_dst_builtin (tree, rtx, bool *);
714static rtx altivec_expand_abs_builtin (enum insn_code, tree, rtx);
f676971a 715static rtx altivec_expand_predicate_builtin (enum insn_code,
c4ad648e 716 const char *, tree, rtx);
b4a62fa0 717static rtx altivec_expand_lv_builtin (enum insn_code, tree, rtx);
a2369ed3
DJ		 718static rtx altivec_expand_stv_builtin (enum insn_code, tree);
719static void rs6000_parse_abi_options (void);
720static void rs6000_parse_alignment_option (void);
721static void rs6000_parse_tls_size_option (void);
5da702b1 722static void rs6000_parse_yes_no_option (const char *, const char *, int *);
4d4cbc0e 723static void rs6000_parse_float_gprs_option (void);
a2369ed3
DJ		 724static int first_altivec_reg_to_save (void);
725static unsigned int compute_vrsave_mask (void);
9390387d 726static void compute_save_world_info (rs6000_stack_t *info_ptr);
a2369ed3
DJ		 727static void is_altivec_return_reg (rtx, void *);
728static rtx generate_set_vrsave (rtx, rs6000_stack_t *, int);
729int easy_vector_constant (rtx, enum machine_mode);
a2369ed3
DJ		 730static bool is_ev64_opaque_type (tree);
731static rtx rs6000_dwarf_register_span (rtx);
732static rtx rs6000_legitimize_tls_address (rtx, enum tls_model);
733static rtx rs6000_tls_get_addr (void);
734static rtx rs6000_got_sym (void);
9390387d 735static int rs6000_tls_symbol_ref_1 (rtx *, void *);
a2369ed3
DJ		 736static const char *rs6000_get_some_local_dynamic_name (void);
737static int rs6000_get_some_local_dynamic_name_1 (rtx *, void *);
ded9bf77 738static rtx rs6000_complex_function_value (enum machine_mode);
b20a9cca 739static rtx rs6000_spe_function_arg (CUMULATIVE_ARGS *,
a2369ed3 740 enum machine_mode, tree);
0b5383eb
DJ		 741static void rs6000_darwin64_record_arg_advance_flush (CUMULATIVE_ARGS *,
742 HOST_WIDE_INT);
743static void rs6000_darwin64_record_arg_advance_recurse (CUMULATIVE_ARGS *,
744 tree, HOST_WIDE_INT);
745static void rs6000_darwin64_record_arg_flush (CUMULATIVE_ARGS *,
746 HOST_WIDE_INT,
747 rtx[], int *);
748static void rs6000_darwin64_record_arg_recurse (CUMULATIVE_ARGS *,
749 tree, HOST_WIDE_INT,
750 rtx[], int *);
751static rtx rs6000_darwin64_record_arg (CUMULATIVE_ARGS *, tree, int, bool);
ec6376ab 752static rtx rs6000_mixed_function_arg (enum machine_mode, tree, int);
b1917422 753static void rs6000_move_block_from_reg (int regno, rtx x, int nregs);
c6e8c921
GK		 754static void setup_incoming_varargs (CUMULATIVE_ARGS *,
755 enum machine_mode, tree,
756 int *, int);
8cd5a4e0
RH		 757static bool rs6000_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode,
758 tree, bool);
78a52f11
RH		 759static int rs6000_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode,
760 tree, bool);
4d3e6fae 761static const char *invalid_arg_for_unprototyped_fn (tree, tree, tree);
efdba735
SH		 762#if TARGET_MACHO
763static void macho_branch_islands (void);
764static void add_compiler_branch_island (tree, tree, int);
765static int no_previous_def (tree function_name);
766static tree get_prev_label (tree function_name);
c4e18b1c 767static void rs6000_darwin_file_start (void);
efdba735
SH		 768#endif
769
c35d187f 770static tree rs6000_build_builtin_va_list (void);
23a60a04 771static tree rs6000_gimplify_va_arg (tree, tree, tree *, tree *);
fe984136 772static bool rs6000_must_pass_in_stack (enum machine_mode, tree);
f676971a 773static bool rs6000_vector_mode_supported_p (enum machine_mode);
94ff898d 774static int get_vec_cmp_insn (enum rtx_code, enum machine_mode,
21213b4c 775 enum machine_mode);
94ff898d 776static rtx rs6000_emit_vector_compare (enum rtx_code, rtx, rtx,
21213b4c
DP		 777 enum machine_mode);
778static int get_vsel_insn (enum machine_mode);
779static void rs6000_emit_vector_select (rtx, rtx, rtx, rtx);
17211ab5 780
21213b4c
DP		 781
782const int INSN_NOT_AVAILABLE = -1;
93f90be6
FJ		 783static enum machine_mode rs6000_eh_return_filter_mode (void);
784
17211ab5
GK		 785/* Hash table stuff for keeping track of TOC entries. */
786
787struct toc_hash_struct GTY(())
788{
789 /* `key' will satisfy CONSTANT_P; in fact, it will satisfy
790 ASM_OUTPUT_SPECIAL_POOL_ENTRY_P. */
791 rtx key;
792 enum machine_mode key_mode;
793 int labelno;
794};
795
796static GTY ((param_is (struct toc_hash_struct))) htab_t toc_hash_table;
c81bebd7
MM		 797\f
798/* Default register names. */
799char rs6000_reg_names[][8] =
800{
802a0058
MM		 801 "0", "1", "2", "3", "4", "5", "6", "7",
802 "8", "9", "10", "11", "12", "13", "14", "15",
803 "16", "17", "18", "19", "20", "21", "22", "23",
804 "24", "25", "26", "27", "28", "29", "30", "31",
805 "0", "1", "2", "3", "4", "5", "6", "7",
806 "8", "9", "10", "11", "12", "13", "14", "15",
807 "16", "17", "18", "19", "20", "21", "22", "23",
808 "24", "25", "26", "27", "28", "29", "30", "31",
809 "mq", "lr", "ctr","ap",
810 "0", "1", "2", "3", "4", "5", "6", "7",
0ac081f6
AH		 811 "xer",
812 /* AltiVec registers. */
0cd5e3a1
AH		 813 "0", "1", "2", "3", "4", "5", "6", "7",
814 "8", "9", "10", "11", "12", "13", "14", "15",
815 "16", "17", "18", "19", "20", "21", "22", "23",
816 "24", "25", "26", "27", "28", "29", "30", "31",
59a4c851
AH		 817 "vrsave", "vscr",
818 /* SPE registers. */
819 "spe_acc", "spefscr"
c81bebd7
MM		 820};
821
822#ifdef TARGET_REGNAMES
8b60264b 823static const char alt_reg_names[][8] =
c81bebd7 824{
802a0058
MM		 825 "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7",
826 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15",
827 "%r16", "%r17", "%r18", "%r19", "%r20", "%r21", "%r22", "%r23",
828 "%r24", "%r25", "%r26", "%r27", "%r28", "%r29", "%r30", "%r31",
829 "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7",
830 "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15",
831 "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23",
832 "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31",
833 "mq", "lr", "ctr", "ap",
834 "%cr0", "%cr1", "%cr2", "%cr3", "%cr4", "%cr5", "%cr6", "%cr7",
0ac081f6 835 "xer",
59a4c851 836 /* AltiVec registers. */
0ac081f6 837 "%v0", "%v1", "%v2", "%v3", "%v4", "%v5", "%v6", "%v7",
59a4c851
AH		 838 "%v8", "%v9", "%v10", "%v11", "%v12", "%v13", "%v14", "%v15",
839 "%v16", "%v17", "%v18", "%v19", "%v20", "%v21", "%v22", "%v23",
840 "%v24", "%v25", "%v26", "%v27", "%v28", "%v29", "%v30", "%v31",
841 "vrsave", "vscr",
842 /* SPE registers. */
843 "spe_acc", "spefscr"
c81bebd7
MM		 844};
845#endif
9878760c 846\f
daf11973
MM		 847#ifndef MASK_STRICT_ALIGN
848#define MASK_STRICT_ALIGN 0
849#endif
ffcfcb5f
AM		 850#ifndef TARGET_PROFILE_KERNEL
851#define TARGET_PROFILE_KERNEL 0
852#endif
3961e8fe
RH		 853
854/* The VRSAVE bitmask puts bit %v0 as the most significant bit. */
855#define ALTIVEC_REG_BIT(REGNO) (0x80000000 >> ((REGNO) - FIRST_ALTIVEC_REGNO))
672a6f42
NB		 856\f
857/* Initialize the GCC target structure. */
91d231cb
JM		 858#undef TARGET_ATTRIBUTE_TABLE
859#define TARGET_ATTRIBUTE_TABLE rs6000_attribute_table
a5c76ee6
ZW		 860#undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES
861#define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES rs6000_set_default_type_attributes
daf11973 862
301d03af
RS		 863#undef TARGET_ASM_ALIGNED_DI_OP
864#define TARGET_ASM_ALIGNED_DI_OP DOUBLE_INT_ASM_OP
865
866/* Default unaligned ops are only provided for ELF. Find the ops needed
867 for non-ELF systems. */
868#ifndef OBJECT_FORMAT_ELF
cbaaba19 869#if TARGET_XCOFF
ae6c1efd 870/* For XCOFF. rs6000_assemble_integer will handle unaligned DIs on
301d03af
RS		 871 64-bit targets. */
872#undef TARGET_ASM_UNALIGNED_HI_OP
873#define TARGET_ASM_UNALIGNED_HI_OP "\t.vbyte\t2,"
874#undef TARGET_ASM_UNALIGNED_SI_OP
875#define TARGET_ASM_UNALIGNED_SI_OP "\t.vbyte\t4,"
876#undef TARGET_ASM_UNALIGNED_DI_OP
877#define TARGET_ASM_UNALIGNED_DI_OP "\t.vbyte\t8,"
878#else
879/* For Darwin. */
880#undef TARGET_ASM_UNALIGNED_HI_OP
881#define TARGET_ASM_UNALIGNED_HI_OP "\t.short\t"
882#undef TARGET_ASM_UNALIGNED_SI_OP
883#define TARGET_ASM_UNALIGNED_SI_OP "\t.long\t"
49bd1d27
SS		 884#undef TARGET_ASM_UNALIGNED_DI_OP
885#define TARGET_ASM_UNALIGNED_DI_OP "\t.quad\t"
886#undef TARGET_ASM_ALIGNED_DI_OP
887#define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
301d03af
RS		 888#endif
889#endif
890
891/* This hook deals with fixups for relocatable code and DI-mode objects
892 in 64-bit code. */
893#undef TARGET_ASM_INTEGER
894#define TARGET_ASM_INTEGER rs6000_assemble_integer
895
93638d7a
AM		 896#ifdef HAVE_GAS_HIDDEN
897#undef TARGET_ASM_ASSEMBLE_VISIBILITY
898#define TARGET_ASM_ASSEMBLE_VISIBILITY rs6000_assemble_visibility
899#endif
900
c4501e62
JJ		 901#undef TARGET_HAVE_TLS
902#define TARGET_HAVE_TLS HAVE_AS_TLS
903
904#undef TARGET_CANNOT_FORCE_CONST_MEM
905#define TARGET_CANNOT_FORCE_CONST_MEM rs6000_tls_referenced_p
906
08c148a8
NB		 907#undef TARGET_ASM_FUNCTION_PROLOGUE
908#define TARGET_ASM_FUNCTION_PROLOGUE rs6000_output_function_prologue
909#undef TARGET_ASM_FUNCTION_EPILOGUE
910#define TARGET_ASM_FUNCTION_EPILOGUE rs6000_output_function_epilogue
911
b54cf83a
DE		 912#undef TARGET_SCHED_VARIABLE_ISSUE
913#define TARGET_SCHED_VARIABLE_ISSUE rs6000_variable_issue
914
c237e94a
ZW		 915#undef TARGET_SCHED_ISSUE_RATE
916#define TARGET_SCHED_ISSUE_RATE rs6000_issue_rate
917#undef TARGET_SCHED_ADJUST_COST
918#define TARGET_SCHED_ADJUST_COST rs6000_adjust_cost
919#undef TARGET_SCHED_ADJUST_PRIORITY
920#define TARGET_SCHED_ADJUST_PRIORITY rs6000_adjust_priority
f676971a 921#undef TARGET_SCHED_IS_COSTLY_DEPENDENCE
569fa502 922#define TARGET_SCHED_IS_COSTLY_DEPENDENCE rs6000_is_costly_dependence
cbe26ab8
DN		 923#undef TARGET_SCHED_FINISH
924#define TARGET_SCHED_FINISH rs6000_sched_finish
c237e94a 925
be12c2b0
VM		 926#undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
927#define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD rs6000_use_sched_lookahead
928
7ccf35ed
DN		 929#undef TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD
930#define TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD rs6000_builtin_mask_for_load
931
0ac081f6
AH		 932#undef TARGET_INIT_BUILTINS
933#define TARGET_INIT_BUILTINS rs6000_init_builtins
934
935#undef TARGET_EXPAND_BUILTIN
936#define TARGET_EXPAND_BUILTIN rs6000_expand_builtin
937
f18eca82
ZL		 938#undef TARGET_MANGLE_FUNDAMENTAL_TYPE
939#define TARGET_MANGLE_FUNDAMENTAL_TYPE rs6000_mangle_fundamental_type
940
c15c90bb
ZW		 941#undef TARGET_INIT_LIBFUNCS
942#define TARGET_INIT_LIBFUNCS rs6000_init_libfuncs
943
f1384257 944#if TARGET_MACHO
0e5dbd9b
DE		 945#undef TARGET_BINDS_LOCAL_P
946#define TARGET_BINDS_LOCAL_P rs6000_binds_local_p
f1384257 947#endif
0e5dbd9b 948
3961e8fe
RH		 949#undef TARGET_ASM_OUTPUT_MI_THUNK
950#define TARGET_ASM_OUTPUT_MI_THUNK rs6000_output_mi_thunk
951
3961e8fe 952#undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
5b71a4e7 953#define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_tree_hwi_hwi_tree_true
00b960c7 954
4977bab6
ZW		 955#undef TARGET_FUNCTION_OK_FOR_SIBCALL
956#define TARGET_FUNCTION_OK_FOR_SIBCALL rs6000_function_ok_for_sibcall
957
3c50106f
RH		 958#undef TARGET_RTX_COSTS
959#define TARGET_RTX_COSTS rs6000_rtx_costs
dcefdf67
RH		 960#undef TARGET_ADDRESS_COST
961#define TARGET_ADDRESS_COST hook_int_rtx_0
3c50106f 962
c8e4f0e9
AH		 963#undef TARGET_VECTOR_OPAQUE_P
964#define TARGET_VECTOR_OPAQUE_P is_ev64_opaque_type
62e1dfcf 965
96714395
AH		 966#undef TARGET_DWARF_REGISTER_SPAN
967#define TARGET_DWARF_REGISTER_SPAN rs6000_dwarf_register_span
968
c6e8c921
GK		 969/* On rs6000, function arguments are promoted, as are function return
970 values. */
971#undef TARGET_PROMOTE_FUNCTION_ARGS
972#define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
973#undef TARGET_PROMOTE_FUNCTION_RETURN
974#define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
975
c6e8c921
GK		 976#undef TARGET_RETURN_IN_MEMORY
977#define TARGET_RETURN_IN_MEMORY rs6000_return_in_memory
978
979#undef TARGET_SETUP_INCOMING_VARARGS
980#define TARGET_SETUP_INCOMING_VARARGS setup_incoming_varargs
981
982/* Always strict argument naming on rs6000. */
983#undef TARGET_STRICT_ARGUMENT_NAMING
984#define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
985#undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED
986#define TARGET_PRETEND_OUTGOING_VARARGS_NAMED hook_bool_CUMULATIVE_ARGS_true
42ba5130
RH		 987#undef TARGET_SPLIT_COMPLEX_ARG
988#define TARGET_SPLIT_COMPLEX_ARG hook_bool_tree_true
fe984136
RH		 989#undef TARGET_MUST_PASS_IN_STACK
990#define TARGET_MUST_PASS_IN_STACK rs6000_must_pass_in_stack
8cd5a4e0
RH		 991#undef TARGET_PASS_BY_REFERENCE
992#define TARGET_PASS_BY_REFERENCE rs6000_pass_by_reference
78a52f11
RH		 993#undef TARGET_ARG_PARTIAL_BYTES
994#define TARGET_ARG_PARTIAL_BYTES rs6000_arg_partial_bytes
c6e8c921 995
c35d187f
RH		 996#undef TARGET_BUILD_BUILTIN_VA_LIST
997#define TARGET_BUILD_BUILTIN_VA_LIST rs6000_build_builtin_va_list
998
cd3ce9b4
JM		 999#undef TARGET_GIMPLIFY_VA_ARG_EXPR
1000#define TARGET_GIMPLIFY_VA_ARG_EXPR rs6000_gimplify_va_arg
1001
93f90be6
FJ		 1002#undef TARGET_EH_RETURN_FILTER_MODE
1003#define TARGET_EH_RETURN_FILTER_MODE rs6000_eh_return_filter_mode
1004
f676971a
EC		 1005#undef TARGET_VECTOR_MODE_SUPPORTED_P
1006#define TARGET_VECTOR_MODE_SUPPORTED_P rs6000_vector_mode_supported_p
1007
4d3e6fae
FJ		 1008#undef TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN
1009#define TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN invalid_arg_for_unprototyped_fn
1010
445cf5eb
JM		 1011/* MPC604EUM 3.5.2 Weak Consistency between Multiple Processors
1012 The PowerPC architecture requires only weak consistency among
1013 processors--that is, memory accesses between processors need not be
1014 sequentially consistent and memory accesses among processors can occur
1015 in any order. The ability to order memory accesses weakly provides
1016 opportunities for more efficient use of the system bus. Unless a
1017 dependency exists, the 604e allows read operations to precede store
1018 operations. */
1019#undef TARGET_RELAXED_ORDERING
1020#define TARGET_RELAXED_ORDERING true
1021
f6897b10 1022struct gcc_target targetm = TARGET_INITIALIZER;
672a6f42 1023\f
0d1fbc8c
AH		 1024
1025/* Value is 1 if hard register REGNO can hold a value of machine-mode
1026 MODE. */
1027static int
1028rs6000_hard_regno_mode_ok (int regno, enum machine_mode mode)
1029{
1030 /* The GPRs can hold any mode, but values bigger than one register
1031 cannot go past R31. */
1032 if (INT_REGNO_P (regno))
1033 return INT_REGNO_P (regno + HARD_REGNO_NREGS (regno, mode) - 1);
1034
1035 /* The float registers can only hold floating modes and DImode. */
1036 if (FP_REGNO_P (regno))
1037 return
1038 (GET_MODE_CLASS (mode) == MODE_FLOAT
1039 && FP_REGNO_P (regno + HARD_REGNO_NREGS (regno, mode) - 1))
1040 || (GET_MODE_CLASS (mode) == MODE_INT
1041 && GET_MODE_SIZE (mode) == UNITS_PER_FP_WORD);
1042
1043 /* The CR register can only hold CC modes. */
1044 if (CR_REGNO_P (regno))
1045 return GET_MODE_CLASS (mode) == MODE_CC;
1046
1047 if (XER_REGNO_P (regno))
1048 return mode == PSImode;
1049
1050 /* AltiVec only in AldyVec registers. */
1051 if (ALTIVEC_REGNO_P (regno))
1052 return ALTIVEC_VECTOR_MODE (mode);
1053
1054 /* ...but GPRs can hold SIMD data on the SPE in one register. */
1055 if (SPE_SIMD_REGNO_P (regno) && TARGET_SPE && SPE_VECTOR_MODE (mode))
1056 return 1;
1057
1058 /* We cannot put TImode anywhere except general register and it must be
1059 able to fit within the register set. */
1060
1061 return GET_MODE_SIZE (mode) <= UNITS_PER_WORD;
1062}
1063
1064/* Initialize rs6000_hard_regno_mode_ok_p table. */
1065static void
1066rs6000_init_hard_regno_mode_ok (void)
1067{
1068 int r, m;
1069
1070 for (r = 0; r < FIRST_PSEUDO_REGISTER; ++r)
1071 for (m = 0; m < NUM_MACHINE_MODES; ++m)
1072 if (rs6000_hard_regno_mode_ok (r, m))
1073 rs6000_hard_regno_mode_ok_p[m][r] = true;
1074}
1075
c1e55850
GK		 1076/* If not otherwise specified by a target, make 'long double' equivalent to
1077 'double'. */
1078
1079#ifndef RS6000_DEFAULT_LONG_DOUBLE_SIZE
1080#define RS6000_DEFAULT_LONG_DOUBLE_SIZE 64
1081#endif
1082
5248c961
RK		 1083/* Override command line options. Mostly we process the processor
1084 type and sometimes adjust other TARGET_ options. */
1085
1086void
d779d0dc 1087rs6000_override_options (const char *default_cpu)
5248c961 1088{
c4d38ccb 1089 size_t i, j;
8e3f41e7 1090 struct rs6000_cpu_select *ptr;
66188a7e 1091 int set_masks;
5248c961 1092
66188a7e 1093 /* Simplifications for entries below. */
85638c0d 1094
66188a7e
GK		 1095 enum {
1096 POWERPC_BASE_MASK = MASK_POWERPC | MASK_NEW_MNEMONICS,
1097 POWERPC_7400_MASK = POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_ALTIVEC
1098 };
85638c0d 1099
66188a7e
GK		 1100 /* This table occasionally claims that a processor does not support
1101 a particular feature even though it does, but the feature is slower
1102 than the alternative. Thus, it shouldn't be relied on as a
f676971a 1103 complete description of the processor's support.
66188a7e
GK		 1104
1105 Please keep this list in order, and don't forget to update the
1106 documentation in invoke.texi when adding a new processor or
1107 flag. */
5248c961
RK		 1108 static struct ptt
1109 {
8b60264b
KG		 1110 const char *const name; /* Canonical processor name. */
1111 const enum processor_type processor; /* Processor type enum value. */
1112 const int target_enable; /* Target flags to enable. */
8b60264b 1113 } const processor_target_table[]
66188a7e 1114 = {{"401", PROCESSOR_PPC403, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
49a0b204 1115 {"403", PROCESSOR_PPC403,
66188a7e
GK		 1116 POWERPC_BASE_MASK | MASK_SOFT_FLOAT | MASK_STRICT_ALIGN},
1117 {"405", PROCESSOR_PPC405, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1118 {"405fp", PROCESSOR_PPC405, POWERPC_BASE_MASK},
1119 {"440", PROCESSOR_PPC440, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1120 {"440fp", PROCESSOR_PPC440, POWERPC_BASE_MASK},
1121 {"505", PROCESSOR_MPCCORE, POWERPC_BASE_MASK},
5248c961 1122 {"601", PROCESSOR_PPC601,
66188a7e
GK		 1123 MASK_POWER | POWERPC_BASE_MASK | MASK_MULTIPLE | MASK_STRING},
1124 {"602", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1125 {"603", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1126 {"603e", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1127 {"604", PROCESSOR_PPC604, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1128 {"604e", PROCESSOR_PPC604e, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
7ddb6568
AM		 1129 {"620", PROCESSOR_PPC620,
1130 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
1131 {"630", PROCESSOR_PPC630,
1132 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
66188a7e
GK		 1133 {"740", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1134 {"7400", PROCESSOR_PPC7400, POWERPC_7400_MASK},
1135 {"7450", PROCESSOR_PPC7450, POWERPC_7400_MASK},
1136 {"750", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1137 {"801", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1138 {"821", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1139 {"823", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1140 {"8540", PROCESSOR_PPC8540, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
4d4cbc0e
AH		 1141 /* 8548 has a dummy entry for now. */
1142 {"8548", PROCESSOR_PPC8540, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
66188a7e 1143 {"860", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
7177e720 1144 {"970", PROCESSOR_POWER4,
66188a7e
GK		 1145 POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64},
1146 {"common", PROCESSOR_COMMON, MASK_NEW_MNEMONICS},
1147 {"ec603e", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1148 {"G3", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1149 {"G4", PROCESSOR_PPC7450, POWERPC_7400_MASK},
49ffe578 1150 {"G5", PROCESSOR_POWER4,
66188a7e
GK		 1151 POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64},
1152 {"power", PROCESSOR_POWER, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1153 {"power2", PROCESSOR_POWER,
1154 MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING},
7ddb6568
AM		 1155 {"power3", PROCESSOR_PPC630,
1156 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
1157 {"power4", PROCESSOR_POWER4,
fc091c8e 1158 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POWERPC64},
ec507f2d 1159 {"power5", PROCESSOR_POWER5,
fc091c8e 1160 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POWERPC64},
66188a7e
GK		 1161 {"powerpc", PROCESSOR_POWERPC, POWERPC_BASE_MASK},
1162 {"powerpc64", PROCESSOR_POWERPC64,
1163 POWERPC_BASE_MASK | MASK_POWERPC64},
1164 {"rios", PROCESSOR_RIOS1, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1165 {"rios1", PROCESSOR_RIOS1, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1166 {"rios2", PROCESSOR_RIOS2,
1167 MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING},
1168 {"rsc", PROCESSOR_PPC601, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1169 {"rsc1", PROCESSOR_PPC601, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
7ddb6568 1170 {"rs64a", PROCESSOR_RS64A, POWERPC_BASE_MASK | MASK_POWERPC64},
66188a7e 1171 };
5248c961 1172
ca7558fc 1173 const size_t ptt_size = ARRAY_SIZE (processor_target_table);
5248c961 1174
66188a7e
GK		 1175 /* Some OSs don't support saving the high part of 64-bit registers on
1176 context switch. Other OSs don't support saving Altivec registers.
1177 On those OSs, we don't touch the MASK_POWERPC64 or MASK_ALTIVEC
1178 settings; if the user wants either, the user must explicitly specify
1179 them and we won't interfere with the user's specification. */
1180
1181 enum {
1182 POWER_MASKS = MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING,
f676971a 1183 POWERPC_MASKS = (POWERPC_BASE_MASK | MASK_PPC_GPOPT
66188a7e
GK		 1184 | MASK_PPC_GFXOPT | MASK_POWERPC64 | MASK_ALTIVEC
1185 | MASK_MFCRF)
1186 };
0d1fbc8c
AH		 1187
1188 rs6000_init_hard_regno_mode_ok ();
1189
c4ad648e 1190 set_masks = POWER_MASKS | POWERPC_MASKS | MASK_SOFT_FLOAT;
66188a7e
GK		 1191#ifdef OS_MISSING_POWERPC64
1192 if (OS_MISSING_POWERPC64)
1193 set_masks &= ~MASK_POWERPC64;
1194#endif
1195#ifdef OS_MISSING_ALTIVEC
1196 if (OS_MISSING_ALTIVEC)
1197 set_masks &= ~MASK_ALTIVEC;
1198#endif
1199
768875a8
AM		 1200 /* Don't override by the processor default if given explicitly. */
1201 set_masks &= ~target_flags_explicit;
957211c3 1202
a4f6c312 1203 /* Identify the processor type. */
8e3f41e7 1204 rs6000_select[0].string = default_cpu;
3cb999d8 1205 rs6000_cpu = TARGET_POWERPC64 ? PROCESSOR_DEFAULT64 : PROCESSOR_DEFAULT;
8e3f41e7 1206
b6a1cbae 1207 for (i = 0; i < ARRAY_SIZE (rs6000_select); i++)
5248c961 1208 {
8e3f41e7
MM		 1209 ptr = &rs6000_select[i];
1210 if (ptr->string != (char *)0 && ptr->string[0] != '\0')
5248c961 1211 {
8e3f41e7
MM		 1212 for (j = 0; j < ptt_size; j++)
1213 if (! strcmp (ptr->string, processor_target_table[j].name))
1214 {
1215 if (ptr->set_tune_p)
1216 rs6000_cpu = processor_target_table[j].processor;
1217
1218 if (ptr->set_arch_p)
1219 {
66188a7e
GK		 1220 target_flags &= ~set_masks;
1221 target_flags |= (processor_target_table[j].target_enable
1222 & set_masks);
8e3f41e7
MM		 1223 }
1224 break;
1225 }
1226
4406229e 1227 if (j == ptt_size)
8e3f41e7 1228 error ("bad value (%s) for %s switch", ptr->string, ptr->name);
5248c961
RK		 1229 }
1230 }
8a61d227 1231
993f19a8 1232 if (TARGET_E500)
a3170dc6
AH		 1233 rs6000_isel = 1;
1234
dff9f1b6
DE		 1235 /* If we are optimizing big endian systems for space, use the load/store
1236 multiple and string instructions. */
ef792183 1237 if (BYTES_BIG_ENDIAN && optimize_size)
957211c3 1238 target_flags |= ~target_flags_explicit & (MASK_MULTIPLE | MASK_STRING);
938937d8 1239
a4f6c312
SS		 1240 /* Don't allow -mmultiple or -mstring on little endian systems
1241 unless the cpu is a 750, because the hardware doesn't support the
1242 instructions used in little endian mode, and causes an alignment
1243 trap. The 750 does not cause an alignment trap (except when the
1244 target is unaligned). */
bef84347 1245
b21fb038 1246 if (!BYTES_BIG_ENDIAN && rs6000_cpu != PROCESSOR_PPC750)
7e69e155
MM		 1247 {
1248 if (TARGET_MULTIPLE)
1249 {
1250 target_flags &= ~MASK_MULTIPLE;
b21fb038 1251 if ((target_flags_explicit & MASK_MULTIPLE) != 0)
7e69e155
MM		 1252 warning ("-mmultiple is not supported on little endian systems");
1253 }
1254
1255 if (TARGET_STRING)
1256 {
1257 target_flags &= ~MASK_STRING;
b21fb038 1258 if ((target_flags_explicit & MASK_STRING) != 0)
938937d8 1259 warning ("-mstring is not supported on little endian systems");
7e69e155
MM		 1260 }
1261 }
3933e0e1 1262
38c1f2d7
MM		 1263 /* Set debug flags */
1264 if (rs6000_debug_name)
1265 {
bfc79d3b 1266 if (! strcmp (rs6000_debug_name, "all"))
38c1f2d7 1267 rs6000_debug_stack = rs6000_debug_arg = 1;
bfc79d3b 1268 else if (! strcmp (rs6000_debug_name, "stack"))
38c1f2d7 1269 rs6000_debug_stack = 1;
bfc79d3b 1270 else if (! strcmp (rs6000_debug_name, "arg"))
38c1f2d7
MM		 1271 rs6000_debug_arg = 1;
1272 else
c725bd79 1273 error ("unknown -mdebug-%s switch", rs6000_debug_name);
38c1f2d7
MM		 1274 }
1275
57ac7be9
AM		 1276 if (rs6000_traceback_name)
1277 {
1278 if (! strncmp (rs6000_traceback_name, "full", 4))
1279 rs6000_traceback = traceback_full;
1280 else if (! strncmp (rs6000_traceback_name, "part", 4))
1281 rs6000_traceback = traceback_part;
1282 else if (! strncmp (rs6000_traceback_name, "no", 2))
1283 rs6000_traceback = traceback_none;
1284 else
9e637a26 1285 error ("unknown -mtraceback arg %qs; expecting %<full%>, %<partial%> or %<none%>",
57ac7be9
AM		 1286 rs6000_traceback_name);
1287 }
1288
6fa3f289 1289 /* Set size of long double */
c1e55850 1290 rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE;
6fa3f289
ZW		 1291 if (rs6000_long_double_size_string)
1292 {
1293 char *tail;
1294 int size = strtol (rs6000_long_double_size_string, &tail, 10);
1295 if (*tail != '\0' || (size != 64 && size != 128))
1296 error ("Unknown switch -mlong-double-%s",
1297 rs6000_long_double_size_string);
1298 else
1299 rs6000_long_double_type_size = size;
1300 }
1301
6d0ef01e
HP		 1302 /* Set Altivec ABI as default for powerpc64 linux. */
1303 if (TARGET_ELF && TARGET_64BIT)
1304 {
1305 rs6000_altivec_abi = 1;
1306 rs6000_altivec_vrsave = 1;
1307 }
1308
594a51fe
SS		 1309 /* Set the Darwin64 ABI as default for 64-bit Darwin. */
1310 if (DEFAULT_ABI == ABI_DARWIN && TARGET_64BIT)
1311 {
1312 rs6000_darwin64_abi = 1;
7bd3a493 1313 /* Setting to empty string is same as "-mone-byte-bool". */
9c7956fd 1314#if TARGET_MACHO
7bd3a493 1315 darwin_one_byte_bool = "";
9c7956fd 1316#endif
d9168963
SS		 1317 /* Default to natural alignment, for better performance. */
1318 rs6000_alignment_flags = MASK_ALIGN_NATURAL;
594a51fe
SS		 1319 }
1320
0ac081f6
AH		 1321 /* Handle -mabi= options. */
1322 rs6000_parse_abi_options ();
1323
025d9908
KH		 1324 /* Handle -malign-XXXXX option. */
1325 rs6000_parse_alignment_option ();
1326
4d4cbc0e
AH		 1327 rs6000_parse_float_gprs_option ();
1328
5da702b1
AH		 1329 /* Handle generic -mFOO=YES/NO options. */
1330 rs6000_parse_yes_no_option ("vrsave", rs6000_altivec_vrsave_string,
1331 &rs6000_altivec_vrsave);
1332 rs6000_parse_yes_no_option ("isel", rs6000_isel_string,
1333 &rs6000_isel);
1334 rs6000_parse_yes_no_option ("spe", rs6000_spe_string, &rs6000_spe);
993f19a8 1335
c4501e62
JJ		 1336 /* Handle -mtls-size option. */
1337 rs6000_parse_tls_size_option ();
1338
a7ae18e2
AH		 1339#ifdef SUBTARGET_OVERRIDE_OPTIONS
1340 SUBTARGET_OVERRIDE_OPTIONS;
1341#endif
1342#ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
1343 SUBSUBTARGET_OVERRIDE_OPTIONS;
1344#endif
4d4cbc0e
AH		 1345#ifdef SUB3TARGET_OVERRIDE_OPTIONS
1346 SUB3TARGET_OVERRIDE_OPTIONS;
1347#endif
a7ae18e2 1348
5da702b1
AH		 1349 if (TARGET_E500)
1350 {
e4463bf1
AH		 1351 if (TARGET_ALTIVEC)
1352 error ("AltiVec and E500 instructions cannot coexist");
1353
5da702b1
AH		 1354 /* The e500 does not have string instructions, and we set
1355 MASK_STRING above when optimizing for size. */
1356 if ((target_flags & MASK_STRING) != 0)
1357 target_flags = target_flags & ~MASK_STRING;
b6e59a3a
AH		 1358
1359 /* No SPE means 64-bit long doubles, even if an E500. */
1360 if (rs6000_spe_string != 0
c4ad648e 1361 && !strcmp (rs6000_spe_string, "no"))
b6e59a3a 1362 rs6000_long_double_type_size = 64;
5da702b1
AH		 1363 }
1364 else if (rs6000_select[1].string != NULL)
1365 {
1366 /* For the powerpc-eabispe configuration, we set all these by
1367 default, so let's unset them if we manually set another
1368 CPU that is not the E500. */
1369 if (rs6000_abi_string == 0)
1370 rs6000_spe_abi = 0;
1371 if (rs6000_spe_string == 0)
1372 rs6000_spe = 0;
1373 if (rs6000_float_gprs_string == 0)
1374 rs6000_float_gprs = 0;
1375 if (rs6000_isel_string == 0)
1376 rs6000_isel = 0;
b6e59a3a 1377 if (rs6000_long_double_size_string == 0)
c1e55850 1378 rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE;
5da702b1 1379 }
b5044283 1380
ec507f2d
DE		 1381 rs6000_always_hint = (rs6000_cpu != PROCESSOR_POWER4
1382 && rs6000_cpu != PROCESSOR_POWER5);
1383 rs6000_sched_groups = (rs6000_cpu == PROCESSOR_POWER4
1384 || rs6000_cpu == PROCESSOR_POWER5);
1385
a5c76ee6
ZW		 1386 /* Handle -m(no-)longcall option. This is a bit of a cheap hack,
1387 using TARGET_OPTIONS to handle a toggle switch, but we're out of
1388 bits in target_flags so TARGET_SWITCHES cannot be used.
1389 Assumption here is that rs6000_longcall_switch points into the
1390 text of the complete option, rather than being a copy, so we can
1391 scan back for the presence or absence of the no- modifier. */
1392 if (rs6000_longcall_switch)
1393 {
1394 const char *base = rs6000_longcall_switch;
1395 while (base[-1] != 'm') base--;
1396
1397 if (*rs6000_longcall_switch != '\0')
9e637a26 1398 error ("invalid option %qs", base);
a5c76ee6
ZW		 1399 rs6000_default_long_calls = (base[0] != 'n');
1400 }
1401
8bb418a3
ZL		 1402 /* Handle -m(no-)warn-altivec-long similarly. */
1403 if (rs6000_warn_altivec_long_switch)
1404 {
1405 const char *base = rs6000_warn_altivec_long_switch;
1406 while (base[-1] != 'm') base--;
1407
1408 if (*rs6000_warn_altivec_long_switch != '\0')
9e637a26 1409 error ("invalid option %qs", base);
8bb418a3
ZL		 1410 rs6000_warn_altivec_long = (base[0] != 'n');
1411 }
1412
cbe26ab8 1413 /* Handle -mprioritize-restricted-insns option. */
ec507f2d
DE		 1414 rs6000_sched_restricted_insns_priority
1415 = (rs6000_sched_groups ? 1 : 0);
79ae11c4
DN		 1416 if (rs6000_sched_restricted_insns_priority_str)
1417 rs6000_sched_restricted_insns_priority =
1418 atoi (rs6000_sched_restricted_insns_priority_str);
1419
569fa502 1420 /* Handle -msched-costly-dep option. */
ec507f2d
DE		 1421 rs6000_sched_costly_dep
1422 = (rs6000_sched_groups ? store_to_load_dep_costly : no_dep_costly);
569fa502
DN		 1423 if (rs6000_sched_costly_dep_str)
1424 {
f676971a 1425 if (! strcmp (rs6000_sched_costly_dep_str, "no"))
c4ad648e 1426 rs6000_sched_costly_dep = no_dep_costly;
569fa502 1427 else if (! strcmp (rs6000_sched_costly_dep_str, "all"))
c4ad648e 1428 rs6000_sched_costly_dep = all_deps_costly;
569fa502 1429 else if (! strcmp (rs6000_sched_costly_dep_str, "true_store_to_load"))
c4ad648e 1430 rs6000_sched_costly_dep = true_store_to_load_dep_costly;
569fa502 1431 else if (! strcmp (rs6000_sched_costly_dep_str, "store_to_load"))
c4ad648e 1432 rs6000_sched_costly_dep = store_to_load_dep_costly;
f676971a 1433 else
c4ad648e 1434 rs6000_sched_costly_dep = atoi (rs6000_sched_costly_dep_str);
cbe26ab8
DN		 1435 }
1436
1437 /* Handle -minsert-sched-nops option. */
ec507f2d
DE		 1438 rs6000_sched_insert_nops
1439 = (rs6000_sched_groups ? sched_finish_regroup_exact : sched_finish_none);
cbe26ab8
DN		 1440 if (rs6000_sched_insert_nops_str)
1441 {
1442 if (! strcmp (rs6000_sched_insert_nops_str, "no"))
c4ad648e 1443 rs6000_sched_insert_nops = sched_finish_none;
cbe26ab8 1444 else if (! strcmp (rs6000_sched_insert_nops_str, "pad"))
c4ad648e 1445 rs6000_sched_insert_nops = sched_finish_pad_groups;
cbe26ab8 1446 else if (! strcmp (rs6000_sched_insert_nops_str, "regroup_exact"))
c4ad648e 1447 rs6000_sched_insert_nops = sched_finish_regroup_exact;
cbe26ab8 1448 else
c4ad648e 1449 rs6000_sched_insert_nops = atoi (rs6000_sched_insert_nops_str);
569fa502
DN		 1450 }
1451
c81bebd7 1452#ifdef TARGET_REGNAMES
a4f6c312
SS		 1453 /* If the user desires alternate register names, copy in the
1454 alternate names now. */
c81bebd7 1455 if (TARGET_REGNAMES)
4e135bdd 1456 memcpy (rs6000_reg_names, alt_reg_names, sizeof (rs6000_reg_names));
c81bebd7
MM		 1457#endif
1458
6fa3f289
ZW		 1459 /* Set TARGET_AIX_STRUCT_RET last, after the ABI is determined.
1460 If -maix-struct-return or -msvr4-struct-return was explicitly
1461 used, don't override with the ABI default. */
b21fb038 1462 if ((target_flags_explicit & MASK_AIX_STRUCT_RET) == 0)
6fa3f289
ZW		 1463 {
1464 if (DEFAULT_ABI == ABI_V4 && !DRAFT_V4_STRUCT_RET)
1465 target_flags = (target_flags & ~MASK_AIX_STRUCT_RET);
1466 else
1467 target_flags |= MASK_AIX_STRUCT_RET;
1468 }
1469
fcce224d
DE		 1470 if (TARGET_LONG_DOUBLE_128
1471 && (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN))
70a01792 1472 REAL_MODE_FORMAT (TFmode) = &ibm_extended_format;
fcce224d 1473
9ebbca7d
GK		 1474 /* Allocate an alias set for register saves & restores from stack. */
1475 rs6000_sr_alias_set = new_alias_set ();
1476
f676971a 1477 if (TARGET_TOC)
9ebbca7d 1478 ASM_GENERATE_INTERNAL_LABEL (toc_label_name, "LCTOC", 1);
71f123ca 1479
301d03af
RS		 1480 /* We can only guarantee the availability of DI pseudo-ops when
1481 assembling for 64-bit targets. */
ae6c1efd 1482 if (!TARGET_64BIT)
301d03af
RS		 1483 {
1484 targetm.asm_out.aligned_op.di = NULL;
1485 targetm.asm_out.unaligned_op.di = NULL;
1486 }
1487
1494c534
DE		 1488 /* Set branch target alignment, if not optimizing for size. */
1489 if (!optimize_size)
1490 {
1491 if (rs6000_sched_groups)
1492 {
1493 if (align_functions <= 0)
1494 align_functions = 16;
1495 if (align_jumps <= 0)
1496 align_jumps = 16;
1497 if (align_loops <= 0)
1498 align_loops = 16;
1499 }
1500 if (align_jumps_max_skip <= 0)
1501 align_jumps_max_skip = 15;
1502 if (align_loops_max_skip <= 0)
1503 align_loops_max_skip = 15;
1504 }
2792d578 1505
71f123ca
FS		 1506 /* Arrange to save and restore machine status around nested functions. */
1507 init_machine_status = rs6000_init_machine_status;
42ba5130
RH		 1508
1509 /* We should always be splitting complex arguments, but we can't break
1510 Linux and Darwin ABIs at the moment. For now, only AIX is fixed. */
18f63bfa 1511 if (DEFAULT_ABI != ABI_AIX)
42ba5130 1512 targetm.calls.split_complex_arg = NULL;
8b897cfa
RS		 1513
1514 /* Initialize rs6000_cost with the appropriate target costs. */
1515 if (optimize_size)
1516 rs6000_cost = TARGET_POWERPC64 ? &size64_cost : &size32_cost;
1517 else
1518 switch (rs6000_cpu)
1519 {
1520 case PROCESSOR_RIOS1:
1521 rs6000_cost = &rios1_cost;
1522 break;
1523
1524 case PROCESSOR_RIOS2:
1525 rs6000_cost = &rios2_cost;
1526 break;
1527
1528 case PROCESSOR_RS64A:
1529 rs6000_cost = &rs64a_cost;
1530 break;
1531
1532 case PROCESSOR_MPCCORE:
1533 rs6000_cost = &mpccore_cost;
1534 break;
1535
1536 case PROCESSOR_PPC403:
1537 rs6000_cost = &ppc403_cost;
1538 break;
1539
1540 case PROCESSOR_PPC405:
1541 rs6000_cost = &ppc405_cost;
1542 break;
1543
1544 case PROCESSOR_PPC440:
1545 rs6000_cost = &ppc440_cost;
1546 break;
1547
1548 case PROCESSOR_PPC601:
1549 rs6000_cost = &ppc601_cost;
1550 break;
1551
1552 case PROCESSOR_PPC603:
1553 rs6000_cost = &ppc603_cost;
1554 break;
1555
1556 case PROCESSOR_PPC604:
1557 rs6000_cost = &ppc604_cost;
1558 break;
1559
1560 case PROCESSOR_PPC604e:
1561 rs6000_cost = &ppc604e_cost;
1562 break;
1563
1564 case PROCESSOR_PPC620:
8b897cfa
RS		 1565 rs6000_cost = &ppc620_cost;
1566 break;
1567
f0517163
RS		 1568 case PROCESSOR_PPC630:
1569 rs6000_cost = &ppc630_cost;
1570 break;
1571
8b897cfa
RS		 1572 case PROCESSOR_PPC750:
1573 case PROCESSOR_PPC7400:
1574 rs6000_cost = &ppc750_cost;
1575 break;
1576
1577 case PROCESSOR_PPC7450:
1578 rs6000_cost = &ppc7450_cost;
1579 break;
1580
1581 case PROCESSOR_PPC8540:
1582 rs6000_cost = &ppc8540_cost;
1583 break;
1584
1585 case PROCESSOR_POWER4:
1586 case PROCESSOR_POWER5:
1587 rs6000_cost = &power4_cost;
1588 break;
1589
1590 default:
1591 abort ();
1592 }
5248c961 1593}
5accd822 1594
7ccf35ed
DN		 1595/* Implement targetm.vectorize.builtin_mask_for_load. */
1596static tree
1597rs6000_builtin_mask_for_load (void)
1598{
1599 if (TARGET_ALTIVEC)
1600 return altivec_builtin_mask_for_load;
1601 else
1602 return 0;
1603}
1604
5da702b1
AH		 1605/* Handle generic options of the form -mfoo=yes/no.
1606 NAME is the option name.
1607 VALUE is the option value.
1608 FLAG is the pointer to the flag where to store a 1 or 0, depending on
1609 whether the option value is 'yes' or 'no' respectively. */
993f19a8 1610static void
5da702b1 1611rs6000_parse_yes_no_option (const char *name, const char *value, int *flag)
993f19a8 1612{
5da702b1 1613 if (value == 0)
993f19a8 1614 return;
5da702b1
AH		 1615 else if (!strcmp (value, "yes"))
1616 *flag = 1;
1617 else if (!strcmp (value, "no"))
1618 *flag = 0;
08b57fb3 1619 else
5da702b1 1620 error ("unknown -m%s= option specified: '%s'", name, value);
08b57fb3
AH		 1621}
1622
0ac081f6 1623/* Handle -mabi= options. */
00b960c7 1624static void
863d938c 1625rs6000_parse_abi_options (void)
0ac081f6
AH		 1626{
1627 if (rs6000_abi_string == 0)
1628 return;
1629 else if (! strcmp (rs6000_abi_string, "altivec"))
5cc73f91
AH		 1630 {
1631 rs6000_altivec_abi = 1;
1632 rs6000_spe_abi = 0;
1633 }
76a773f3
AH		 1634 else if (! strcmp (rs6000_abi_string, "no-altivec"))
1635 rs6000_altivec_abi = 0;
a3170dc6 1636 else if (! strcmp (rs6000_abi_string, "spe"))
01f4962d
NS		 1637 {
1638 rs6000_spe_abi = 1;
5cc73f91 1639 rs6000_altivec_abi = 0;
01f4962d
NS		 1640 if (!TARGET_SPE_ABI)
1641 error ("not configured for ABI: '%s'", rs6000_abi_string);
1642 }
f676971a 1643
594a51fe
SS		 1644 /* These are here for testing during development only, do not
1645 document in the manual please. */
1646 else if (! strcmp (rs6000_abi_string, "d64"))
1647 {
1648 rs6000_darwin64_abi = 1;
1649 warning ("Using darwin64 ABI");
1650 }
1651 else if (! strcmp (rs6000_abi_string, "d32"))
1652 {
1653 rs6000_darwin64_abi = 0;
1654 warning ("Using old darwin ABI");
1655 }
1656
a3170dc6
AH		 1657 else if (! strcmp (rs6000_abi_string, "no-spe"))
1658 rs6000_spe_abi = 0;
0ac081f6 1659 else
c725bd79 1660 error ("unknown ABI specified: '%s'", rs6000_abi_string);
0ac081f6
AH		 1661}
1662
4d4cbc0e
AH		 1663/* Handle -mfloat-gprs= options. */
1664static void
1665rs6000_parse_float_gprs_option (void)
1666{
1667 if (rs6000_float_gprs_string == 0)
1668 return;
1669 else if (! strcmp (rs6000_float_gprs_string, "yes")
1670 || ! strcmp (rs6000_float_gprs_string, "single"))
1671 rs6000_float_gprs = 1;
1672 else if (! strcmp (rs6000_float_gprs_string, "double"))
1673 rs6000_float_gprs = 2;
1674 else if (! strcmp (rs6000_float_gprs_string, "no"))
1675 rs6000_float_gprs = 0;
1676 else
1677 error ("invalid option for -mfloat-gprs");
1678}
1679
025d9908
KH		 1680/* Handle -malign-XXXXXX options. */
1681static void
863d938c 1682rs6000_parse_alignment_option (void)
025d9908 1683{
b20a9cca
AM		 1684 if (rs6000_alignment_string == 0)
1685 return;
1686 else if (! strcmp (rs6000_alignment_string, "power"))
d9168963
SS		 1687 {
1688 /* On 64-bit Darwin, power alignment is ABI-incompatible with
1689 some C library functions, so warn about it. The flag may be
1690 useful for performance studies from time to time though, so
1691 don't disable it entirely. */
1692 if (DEFAULT_ABI == ABI_DARWIN && TARGET_64BIT)
1693 warning ("-malign-power is not supported for 64-bit Darwin;"
1694 " it is incompatible with the installed C and C++ libraries");
1695 rs6000_alignment_flags = MASK_ALIGN_POWER;
1696 }
025d9908
KH		 1697 else if (! strcmp (rs6000_alignment_string, "natural"))
1698 rs6000_alignment_flags = MASK_ALIGN_NATURAL;
1699 else
1700 error ("unknown -malign-XXXXX option specified: '%s'",
1701 rs6000_alignment_string);
1702}
1703
c4501e62
JJ		 1704/* Validate and record the size specified with the -mtls-size option. */
1705
1706static void
863d938c 1707rs6000_parse_tls_size_option (void)
c4501e62
JJ		 1708{
1709 if (rs6000_tls_size_string == 0)
1710 return;
1711 else if (strcmp (rs6000_tls_size_string, "16") == 0)
1712 rs6000_tls_size = 16;
1713 else if (strcmp (rs6000_tls_size_string, "32") == 0)
1714 rs6000_tls_size = 32;
1715 else if (strcmp (rs6000_tls_size_string, "64") == 0)
1716 rs6000_tls_size = 64;
1717 else
9e637a26 1718 error ("bad value %qs for -mtls-size switch", rs6000_tls_size_string);
c4501e62
JJ		 1719}
1720
5accd822 1721void
a2369ed3 1722optimization_options (int level ATTRIBUTE_UNUSED, int size ATTRIBUTE_UNUSED)
5accd822 1723{
5accd822 1724}
3cfa4909
MM		 1725\f
1726/* Do anything needed at the start of the asm file. */
1727
1bc7c5b6 1728static void
863d938c 1729rs6000_file_start (void)
3cfa4909 1730{
c4d38ccb 1731 size_t i;
3cfa4909 1732 char buffer[80];
d330fd93 1733 const char *start = buffer;
3cfa4909 1734 struct rs6000_cpu_select *ptr;
1bc7c5b6
ZW		 1735 const char *default_cpu = TARGET_CPU_DEFAULT;
1736 FILE *file = asm_out_file;
1737
1738 default_file_start ();
1739
1740#ifdef TARGET_BI_ARCH
1741 if ((TARGET_DEFAULT ^ target_flags) & MASK_64BIT)
1742 default_cpu = 0;
1743#endif
3cfa4909
MM		 1744
1745 if (flag_verbose_asm)
1746 {
1747 sprintf (buffer, "\n%s rs6000/powerpc options:", ASM_COMMENT_START);
1748 rs6000_select[0].string = default_cpu;
1749
b6a1cbae 1750 for (i = 0; i < ARRAY_SIZE (rs6000_select); i++)
3cfa4909
MM		 1751 {
1752 ptr = &rs6000_select[i];
1753 if (ptr->string != (char *)0 && ptr->string[0] != '\0')
1754 {
1755 fprintf (file, "%s %s%s", start, ptr->name, ptr->string);
1756 start = "";
1757 }
1758 }
1759
b91da81f 1760#ifdef USING_ELFOS_H
3cfa4909
MM		 1761 switch (rs6000_sdata)
1762 {
1763 case SDATA_NONE: fprintf (file, "%s -msdata=none", start); start = ""; break;
1764 case SDATA_DATA: fprintf (file, "%s -msdata=data", start); start = ""; break;
1765 case SDATA_SYSV: fprintf (file, "%s -msdata=sysv", start); start = ""; break;
1766 case SDATA_EABI: fprintf (file, "%s -msdata=eabi", start); start = ""; break;
1767 }
1768
1769 if (rs6000_sdata && g_switch_value)
1770 {
307b599c
MK		 1771 fprintf (file, "%s -G " HOST_WIDE_INT_PRINT_UNSIGNED, start,
1772 g_switch_value);
3cfa4909
MM		 1773 start = "";
1774 }
1775#endif
1776
1777 if (*start == '\0')
949ea356 1778 putc ('\n', file);
3cfa4909 1779 }
b723e82f
JJ		 1780
1781 if (DEFAULT_ABI == ABI_AIX || (TARGET_ELF && flag_pic == 2))
1782 {
1783 toc_section ();
1784 text_section ();
1785 }
3cfa4909 1786}
c4e18b1c 1787
5248c961 1788\f
a0ab749a 1789/* Return nonzero if this function is known to have a null epilogue. */
9878760c
RK		 1790
1791int
863d938c 1792direct_return (void)
9878760c 1793{
4697a36c
MM		 1794 if (reload_completed)
1795 {
1796 rs6000_stack_t *info = rs6000_stack_info ();
1797
1798 if (info->first_gp_reg_save == 32
1799 && info->first_fp_reg_save == 64
00b960c7 1800 && info->first_altivec_reg_save == LAST_ALTIVEC_REGNO + 1
c81fc13e
DE		 1801 && ! info->lr_save_p
1802 && ! info->cr_save_p
00b960c7 1803 && info->vrsave_mask == 0
c81fc13e 1804 && ! info->push_p)
4697a36c
MM		 1805 return 1;
1806 }
1807
1808 return 0;
9878760c
RK		 1809}
1810
4e74d8ec
MM		 1811/* Return the number of instructions it takes to form a constant in an
1812 integer register. */
1813
48d72335 1814int
a2369ed3 1815num_insns_constant_wide (HOST_WIDE_INT value)
4e74d8ec
MM		 1816{
1817 /* signed constant loadable with {cal|addi} */
5f59ecb7 1818 if (CONST_OK_FOR_LETTER_P (value, 'I'))
0865c631
GK		 1819 return 1;
1820
4e74d8ec 1821 /* constant loadable with {cau|addis} */
5f59ecb7 1822 else if (CONST_OK_FOR_LETTER_P (value, 'L'))
4e74d8ec
MM		 1823 return 1;
1824
5f59ecb7 1825#if HOST_BITS_PER_WIDE_INT == 64
c81fc13e 1826 else if (TARGET_POWERPC64)
4e74d8ec 1827 {
a65c591c
DE		 1828 HOST_WIDE_INT low = ((value & 0xffffffff) ^ 0x80000000) - 0x80000000;
1829 HOST_WIDE_INT high = value >> 31;
4e74d8ec 1830
a65c591c 1831 if (high == 0 || high == -1)
4e74d8ec
MM		 1832 return 2;
1833
a65c591c 1834 high >>= 1;
4e74d8ec 1835
a65c591c 1836 if (low == 0)
4e74d8ec 1837 return num_insns_constant_wide (high) + 1;
4e74d8ec
MM		 1838 else
1839 return (num_insns_constant_wide (high)
e396202a 1840 + num_insns_constant_wide (low) + 1);
4e74d8ec
MM		 1841 }
1842#endif
1843
1844 else
1845 return 2;
1846}
1847
1848int
a2369ed3 1849num_insns_constant (rtx op, enum machine_mode mode)
4e74d8ec 1850{
4e74d8ec 1851 if (GET_CODE (op) == CONST_INT)
0d30d435
DE		 1852 {
1853#if HOST_BITS_PER_WIDE_INT == 64
4e2c1c44
DE		 1854 if ((INTVAL (op) >> 31) != 0 && (INTVAL (op) >> 31) != -1
1855 && mask64_operand (op, mode))
c4ad648e 1856 return 2;
0d30d435
DE		 1857 else
1858#endif
1859 return num_insns_constant_wide (INTVAL (op));
1860 }
4e74d8ec 1861
6fc48950
MM		 1862 else if (GET_CODE (op) == CONST_DOUBLE && mode == SFmode)
1863 {
1864 long l;
1865 REAL_VALUE_TYPE rv;
1866
1867 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
1868 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
e72247f4 1869 return num_insns_constant_wide ((HOST_WIDE_INT) l);
6fc48950
MM		 1870 }
1871
47ad8c61 1872 else if (GET_CODE (op) == CONST_DOUBLE)
4e74d8ec 1873 {
47ad8c61
MM		 1874 HOST_WIDE_INT low;
1875 HOST_WIDE_INT high;
1876 long l[2];
1877 REAL_VALUE_TYPE rv;
1878 int endian = (WORDS_BIG_ENDIAN == 0);
4e74d8ec 1879
47ad8c61
MM		 1880 if (mode == VOIDmode || mode == DImode)
1881 {
1882 high = CONST_DOUBLE_HIGH (op);
1883 low = CONST_DOUBLE_LOW (op);
1884 }
1885 else
1886 {
1887 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
1888 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
1889 high = l[endian];
1890 low = l[1 - endian];
1891 }
4e74d8ec 1892
47ad8c61
MM		 1893 if (TARGET_32BIT)
1894 return (num_insns_constant_wide (low)
1895 + num_insns_constant_wide (high));
4e74d8ec
MM		 1896
1897 else
47ad8c61 1898 {
e72247f4 1899 if (high == 0 && low >= 0)
47ad8c61
MM		 1900 return num_insns_constant_wide (low);
1901
e72247f4 1902 else if (high == -1 && low < 0)
47ad8c61
MM		 1903 return num_insns_constant_wide (low);
1904
a260abc9
DE		 1905 else if (mask64_operand (op, mode))
1906 return 2;
1907
47ad8c61
MM		 1908 else if (low == 0)
1909 return num_insns_constant_wide (high) + 1;
1910
1911 else
1912 return (num_insns_constant_wide (high)
1913 + num_insns_constant_wide (low) + 1);
1914 }
4e74d8ec
MM		 1915 }
1916
1917 else
1918 abort ();
1919}
1920
effa5d5d 1921/* Returns the constant for the splat instruction, if exists. */
452a7d36 1922
48d72335 1923int
452a7d36
HP		 1924easy_vector_splat_const (int cst, enum machine_mode mode)
1925{
f676971a 1926 switch (mode)
452a7d36
HP		 1927 {
1928 case V4SImode:
f676971a
EC		 1929 if (EASY_VECTOR_15 (cst)
1930 || EASY_VECTOR_15_ADD_SELF (cst))
452a7d36
HP		 1931 return cst;
1932 if ((cst & 0xffff) != ((cst >> 16) & 0xffff))
1933 break;
1934 cst = cst >> 16;
c4ad648e
AM		 1935 /* Fall thru */
1936
452a7d36 1937 case V8HImode:
f676971a
EC		 1938 if (EASY_VECTOR_15 (cst)
1939 || EASY_VECTOR_15_ADD_SELF (cst))
452a7d36
HP		 1940 return cst;
1941 if ((cst & 0xff) != ((cst >> 8) & 0xff))
1942 break;
1943 cst = cst >> 8;
c4ad648e
AM		 1944 /* Fall thru */
1945
452a7d36 1946 case V16QImode:
c4ad648e
AM		 1947 if (EASY_VECTOR_15 (cst)
1948 || EASY_VECTOR_15_ADD_SELF (cst))
1949 return cst;
f676971a 1950 default:
452a7d36
HP		 1951 break;
1952 }
1953 return 0;
1954}
1955
72ac76be 1956/* Return nonzero if all elements of a vector have the same value. */
69ef87e2 1957
48d72335 1958int
a2369ed3 1959easy_vector_same (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
d744e06e
AH		 1960{
1961 int units, i, cst;
1962
1963 units = CONST_VECTOR_NUNITS (op);
1964
1965 cst = INTVAL (CONST_VECTOR_ELT (op, 0));
1966 for (i = 1; i < units; ++i)
1967 if (INTVAL (CONST_VECTOR_ELT (op, i)) != cst)
1968 break;
452a7d36 1969 if (i == units && easy_vector_splat_const (cst, mode))
d744e06e
AH		 1970 return 1;
1971 return 0;
1972}
1973
452a7d36 1974/* Generate easy_vector_constant out of a easy_vector_constant_add_self. */
d744e06e 1975
f676971a 1976rtx
452a7d36
HP		 1977gen_easy_vector_constant_add_self (rtx op)
1978{
1979 int i, units;
1980 rtvec v;
1981 units = GET_MODE_NUNITS (GET_MODE (op));
1982 v = rtvec_alloc (units);
1983
1984 for (i = 0; i < units; i++)
f676971a 1985 RTVEC_ELT (v, i) =
452a7d36
HP		 1986 GEN_INT (INTVAL (CONST_VECTOR_ELT (op, i)) >> 1);
1987 return gen_rtx_raw_CONST_VECTOR (GET_MODE (op), v);
d744e06e
AH		 1988}
1989
1990const char *
a2369ed3 1991output_vec_const_move (rtx *operands)
d744e06e
AH		 1992{
1993 int cst, cst2;
1994 enum machine_mode mode;
1995 rtx dest, vec;
1996
1997 dest = operands[0];
1998 vec = operands[1];
69ef87e2 1999
d744e06e
AH		 2000 cst = INTVAL (CONST_VECTOR_ELT (vec, 0));
2001 cst2 = INTVAL (CONST_VECTOR_ELT (vec, 1));
2002 mode = GET_MODE (dest);
69ef87e2 2003
d744e06e
AH		 2004 if (TARGET_ALTIVEC)
2005 {
2006 if (zero_constant (vec, mode))
2007 return "vxor %0,%0,%0";
ce1f50b2 2008 else if (easy_vector_constant (vec, mode))
98ef3137 2009 {
d744e06e
AH		 2010 operands[1] = GEN_INT (cst);
2011 switch (mode)
2012 {
2013 case V4SImode:
452a7d36 2014 if (EASY_VECTOR_15 (cst))
ce1f50b2
HP		 2015 {
2016 operands[1] = GEN_INT (cst);
2017 return "vspltisw %0,%1";
2018 }
452a7d36
HP		 2019 else if (EASY_VECTOR_15_ADD_SELF (cst))
2020 return "#";
ce1f50b2 2021 cst = cst >> 16;
c4ad648e
AM		 2022 /* Fall thru */
2023
d744e06e 2024 case V8HImode:
452a7d36 2025 if (EASY_VECTOR_15 (cst))
ce1f50b2
HP		 2026 {
2027 operands[1] = GEN_INT (cst);
2028 return "vspltish %0,%1";
2029 }
452a7d36
HP		 2030 else if (EASY_VECTOR_15_ADD_SELF (cst))
2031 return "#";
ce1f50b2 2032 cst = cst >> 8;
c4ad648e
AM		 2033 /* Fall thru */
2034
d744e06e 2035 case V16QImode:
452a7d36 2036 if (EASY_VECTOR_15 (cst))
ce1f50b2
HP		 2037 {
2038 operands[1] = GEN_INT (cst);
2039 return "vspltisb %0,%1";
2040 }
452a7d36
HP		 2041 else if (EASY_VECTOR_15_ADD_SELF (cst))
2042 return "#";
c4ad648e 2043
d744e06e
AH		 2044 default:
2045 abort ();
2046 }
98ef3137 2047 }
d744e06e
AH		 2048 else
2049 abort ();
69ef87e2
AH		 2050 }
2051
d744e06e
AH		 2052 if (TARGET_SPE)
2053 {
2054 /* Vector constant 0 is handled as a splitter of V2SI, and in the
2055 pattern of V1DI, V4HI, and V2SF.
2056
c1207243 2057 FIXME: We should probably return # and add post reload
c4ad648e 2058 splitters for these, but this way is so easy ;-). */
d744e06e
AH		 2059 operands[1] = GEN_INT (cst);
2060 operands[2] = GEN_INT (cst2);
2061 if (cst == cst2)
2062 return "li %0,%1\n\tevmergelo %0,%0,%0";
2063 else
2064 return "li %0,%1\n\tevmergelo %0,%0,%0\n\tli %0,%2";
2065 }
2066
2067 abort ();
69ef87e2
AH		 2068}
2069
914c2e77 2070int
e1e2e653
NS		 2071mask64_1or2_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED,
2072 bool allow_one)
0ba1b2ff
AM		 2073{
2074 if (GET_CODE (op) == CONST_INT)
a260abc9 2075 {
0ba1b2ff 2076 HOST_WIDE_INT c, lsb;
e1e2e653
NS		 2077 bool one_ok;
2078
0ba1b2ff 2079 c = INTVAL (op);
a260abc9 2080
0ba1b2ff
AM		 2081 /* Disallow all zeros. */
2082 if (c == 0)
2083 return 0;
a260abc9 2084
e1e2e653
NS		 2085 /* We can use a single rlwinm insn if no upper bits of C are set
2086 AND there are zero, one or two transitions in the _whole_ of
2087 C. */
2088 one_ok = !(c & ~(HOST_WIDE_INT)0xffffffff);
2089
0ba1b2ff
AM		 2090 /* We don't change the number of transitions by inverting,
2091 so make sure we start with the LS bit zero. */
2092 if (c & 1)
2093 c = ~c;
a260abc9 2094
0ba1b2ff
AM		 2095 /* Find the first transition. */
2096 lsb = c & -c;
a260abc9 2097
0ba1b2ff
AM		 2098 /* Invert to look for a second transition. */
2099 c = ~c;
2100
2101 /* Erase first transition. */
2102 c &= -lsb;
2103
2104 /* Find the second transition. */
2105 lsb = c & -c;
2106
2107 /* Invert to look for a third transition. */
2108 c = ~c;
2109
2110 /* Erase second transition. */
2111 c &= -lsb;
2112
e1e2e653
NS		 2113 if (one_ok && !(allow_one || c))
2114 return 0;
2115
0ba1b2ff
AM		 2116 /* Find the third transition (if any). */
2117 lsb = c & -c;
2118
2119 /* Match if all the bits above are 1's (or c is zero). */
2120 return c == -lsb;
2121 }
2122 return 0;
2123}
2124
2125/* Generates shifts and masks for a pair of rldicl or rldicr insns to
2126 implement ANDing by the mask IN. */
2127void
a2369ed3 2128build_mask64_2_operands (rtx in, rtx *out)
0ba1b2ff
AM		 2129{
2130#if HOST_BITS_PER_WIDE_INT >= 64
2131 unsigned HOST_WIDE_INT c, lsb, m1, m2;
2132 int shift;
2133
2134 if (GET_CODE (in) != CONST_INT)
2135 abort ();
2136
2137 c = INTVAL (in);
2138 if (c & 1)
2139 {
2140 /* Assume c initially something like 0x00fff000000fffff. The idea
2141 is to rotate the word so that the middle ^^^^^^ group of zeros
2142 is at the MS end and can be cleared with an rldicl mask. We then
2143 rotate back and clear off the MS ^^ group of zeros with a
2144 second rldicl. */
2145 c = ~c; /* c == 0xff000ffffff00000 */
2146 lsb = c & -c; /* lsb == 0x0000000000100000 */
2147 m1 = -lsb; /* m1 == 0xfffffffffff00000 */
2148 c = ~c; /* c == 0x00fff000000fffff */
2149 c &= -lsb; /* c == 0x00fff00000000000 */
2150 lsb = c & -c; /* lsb == 0x0000100000000000 */
2151 c = ~c; /* c == 0xff000fffffffffff */
2152 c &= -lsb; /* c == 0xff00000000000000 */
2153 shift = 0;
2154 while ((lsb >>= 1) != 0)
2155 shift++; /* shift == 44 on exit from loop */
2156 m1 <<= 64 - shift; /* m1 == 0xffffff0000000000 */
2157 m1 = ~m1; /* m1 == 0x000000ffffffffff */
2158 m2 = ~c; /* m2 == 0x00ffffffffffffff */
a260abc9
DE		 2159 }
2160 else
0ba1b2ff
AM		 2161 {
2162 /* Assume c initially something like 0xff000f0000000000. The idea
2163 is to rotate the word so that the ^^^ middle group of zeros
2164 is at the LS end and can be cleared with an rldicr mask. We then
2165 rotate back and clear off the LS group of ^^^^^^^^^^ zeros with
2166 a second rldicr. */
2167 lsb = c & -c; /* lsb == 0x0000010000000000 */
2168 m2 = -lsb; /* m2 == 0xffffff0000000000 */
2169 c = ~c; /* c == 0x00fff0ffffffffff */
2170 c &= -lsb; /* c == 0x00fff00000000000 */
2171 lsb = c & -c; /* lsb == 0x0000100000000000 */
2172 c = ~c; /* c == 0xff000fffffffffff */
2173 c &= -lsb; /* c == 0xff00000000000000 */
2174 shift = 0;
2175 while ((lsb >>= 1) != 0)
2176 shift++; /* shift == 44 on exit from loop */
2177 m1 = ~c; /* m1 == 0x00ffffffffffffff */
2178 m1 >>= shift; /* m1 == 0x0000000000000fff */
2179 m1 = ~m1; /* m1 == 0xfffffffffffff000 */
2180 }
2181
2182 /* Note that when we only have two 0->1 and 1->0 transitions, one of the
2183 masks will be all 1's. We are guaranteed more than one transition. */
2184 out[0] = GEN_INT (64 - shift);
2185 out[1] = GEN_INT (m1);
2186 out[2] = GEN_INT (shift);
2187 out[3] = GEN_INT (m2);
2188#else
045572c7
GK		 2189 (void)in;
2190 (void)out;
0ba1b2ff
AM		 2191 abort ();
2192#endif
a260abc9
DE		 2193}
2194
54b695e7 2195/* Return TRUE if OP is an invalid SUBREG operation on the e500. */
48d72335
DE		 2196
2197bool
54b695e7
AH		 2198invalid_e500_subreg (rtx op, enum machine_mode mode)
2199{
2200 /* Reject (subreg:SI (reg:DF)). */
2201 if (GET_CODE (op) == SUBREG
2202 && mode == SImode
2203 && REG_P (SUBREG_REG (op))
2204 && GET_MODE (SUBREG_REG (op)) == DFmode)
2205 return true;
2206
2207 /* Reject (subreg:DF (reg:DI)). */
2208 if (GET_CODE (op) == SUBREG
2209 && mode == DFmode
2210 && REG_P (SUBREG_REG (op))
2211 && GET_MODE (SUBREG_REG (op)) == DImode)
2212 return true;
2213
2214 return false;
2215}
2216
95727fb8
AP		 2217/* Darwin, AIX increases natural record alignment to doubleword if the first
2218 field is an FP double while the FP fields remain word aligned. */
2219
19d66194 2220unsigned int
95727fb8
AP		 2221rs6000_special_round_type_align (tree type, int computed, int specified)
2222{
2223 tree field = TYPE_FIELDS (type);
95727fb8 2224
85962ac8
AP		 2225 /* Skip all non field decls */
2226 while (field != NULL && TREE_CODE (field) != FIELD_DECL)
95727fb8
AP		 2227 field = TREE_CHAIN (field);
2228
3ce5437a 2229 if (field == NULL || field == type || DECL_MODE (field) != DFmode)
95727fb8
AP		 2230 return MAX (computed, specified);
2231
2232 return MAX (MAX (computed, specified), 64);
2233}
2234
a4f6c312 2235/* Return 1 for an operand in small memory on V.4/eabi. */
7509c759
MM		 2236
2237int
f676971a 2238small_data_operand (rtx op ATTRIBUTE_UNUSED,
a2369ed3 2239 enum machine_mode mode ATTRIBUTE_UNUSED)
7509c759 2240{
38c1f2d7 2241#if TARGET_ELF
5f59ecb7 2242 rtx sym_ref;
7509c759 2243
d9407988 2244 if (rs6000_sdata == SDATA_NONE || rs6000_sdata == SDATA_DATA)
a54d04b7 2245 return 0;
a54d04b7 2246
f607bc57 2247 if (DEFAULT_ABI != ABI_V4)
7509c759
MM		 2248 return 0;
2249
88228c4b
MM		 2250 if (GET_CODE (op) == SYMBOL_REF)
2251 sym_ref = op;
2252
2253 else if (GET_CODE (op) != CONST
2254 || GET_CODE (XEXP (op, 0)) != PLUS
2255 || GET_CODE (XEXP (XEXP (op, 0), 0)) != SYMBOL_REF
2256 || GET_CODE (XEXP (XEXP (op, 0), 1)) != CONST_INT)
7509c759
MM		 2257 return 0;
2258
88228c4b 2259 else
dbf55e53
MM		 2260 {
2261 rtx sum = XEXP (op, 0);
2262 HOST_WIDE_INT summand;
2263
2264 /* We have to be careful here, because it is the referenced address
c4ad648e 2265 that must be 32k from _SDA_BASE_, not just the symbol. */
dbf55e53 2266 summand = INTVAL (XEXP (sum, 1));
307b599c 2267 if (summand < 0 || (unsigned HOST_WIDE_INT) summand > g_switch_value)
9390387d 2268 return 0;
dbf55e53
MM		 2269
2270 sym_ref = XEXP (sum, 0);
2271 }
88228c4b 2272
20bfcd69 2273 return SYMBOL_REF_SMALL_P (sym_ref);
d9407988
MM		 2274#else
2275 return 0;
2276#endif
7509c759 2277}
46c07df8 2278
d2288d5d
HP		 2279/* Return true, if operand is a memory operand and has a
2280 displacement divisible by 4. */
2281
2282int
2283word_offset_memref_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2284{
2285 rtx addr;
2286 int off = 0;
2287
2288 if (!memory_operand (op, mode))
2289 return 0;
2290
2291 addr = XEXP (op, 0);
2292 if (GET_CODE (addr) == PLUS
2293 && GET_CODE (XEXP (addr, 0)) == REG
2294 && GET_CODE (XEXP (addr, 1)) == CONST_INT)
2295 off = INTVAL (XEXP (addr, 1));
2296
2297 return (off % 4) == 0;
2298}
2299
3a1f863f 2300/* Return true if either operand is a general purpose register. */
46c07df8 2301
3a1f863f
DE		 2302bool
2303gpr_or_gpr_p (rtx op0, rtx op1)
46c07df8 2304{
3a1f863f
DE		 2305 return ((REG_P (op0) && INT_REGNO_P (REGNO (op0)))
2306 || (REG_P (op1) && INT_REGNO_P (REGNO (op1))));
46c07df8
HP		 2307}
2308
9ebbca7d 2309\f
4d588c14
RH		 2310/* Subroutines of rs6000_legitimize_address and rs6000_legitimate_address. */
2311
f676971a
EC		 2312static int
2313constant_pool_expr_1 (rtx op, int *have_sym, int *have_toc)
9ebbca7d 2314{
9390387d 2315 switch (GET_CODE (op))
9ebbca7d
GK		 2316 {
2317 case SYMBOL_REF:
c4501e62
JJ		 2318 if (RS6000_SYMBOL_REF_TLS_P (op))
2319 return 0;
2320 else if (CONSTANT_POOL_ADDRESS_P (op))
a4f6c312
SS		 2321 {
2322 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (op), Pmode))
2323 {
2324 *have_sym = 1;
2325 return 1;
2326 }
2327 else
2328 return 0;
2329 }
2330 else if (! strcmp (XSTR (op, 0), toc_label_name))
2331 {
2332 *have_toc = 1;
2333 return 1;
2334 }
2335 else
2336 return 0;
9ebbca7d
GK		 2337 case PLUS:
2338 case MINUS:
c1f11548
DE		 2339 return (constant_pool_expr_1 (XEXP (op, 0), have_sym, have_toc)
2340 && constant_pool_expr_1 (XEXP (op, 1), have_sym, have_toc));
9ebbca7d 2341 case CONST:
a4f6c312 2342 return constant_pool_expr_1 (XEXP (op, 0), have_sym, have_toc);
9ebbca7d 2343 case CONST_INT:
a4f6c312 2344 return 1;
9ebbca7d 2345 default:
a4f6c312 2346 return 0;
9ebbca7d
GK		 2347 }
2348}
2349
4d588c14 2350static bool
a2369ed3 2351constant_pool_expr_p (rtx op)
9ebbca7d
GK		 2352{
2353 int have_sym = 0;
2354 int have_toc = 0;
2355 return constant_pool_expr_1 (op, &have_sym, &have_toc) && have_sym;
2356}
2357
48d72335 2358bool
a2369ed3 2359toc_relative_expr_p (rtx op)
9ebbca7d 2360{
4d588c14
RH		 2361 int have_sym = 0;
2362 int have_toc = 0;
2363 return constant_pool_expr_1 (op, &have_sym, &have_toc) && have_toc;
2364}
2365
4d588c14 2366bool
a2369ed3 2367legitimate_constant_pool_address_p (rtx x)
4d588c14
RH		 2368{
2369 return (TARGET_TOC
2370 && GET_CODE (x) == PLUS
2371 && GET_CODE (XEXP (x, 0)) == REG
2372 && (TARGET_MINIMAL_TOC || REGNO (XEXP (x, 0)) == TOC_REGISTER)
2373 && constant_pool_expr_p (XEXP (x, 1)));
2374}
2375
2376static bool
a2369ed3 2377legitimate_small_data_p (enum machine_mode mode, rtx x)
4d588c14
RH		 2378{
2379 return (DEFAULT_ABI == ABI_V4
2380 && !flag_pic && !TARGET_TOC
2381 && (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST)
2382 && small_data_operand (x, mode));
2383}
2384
60cdabab
DE		 2385/* SPE offset addressing is limited to 5-bits worth of double words. */
2386#define SPE_CONST_OFFSET_OK(x) (((x) & ~0xf8) == 0)
2387
76d2b81d
DJ		 2388bool
2389rs6000_legitimate_offset_address_p (enum machine_mode mode, rtx x, int strict)
4d588c14
RH		 2390{
2391 unsigned HOST_WIDE_INT offset, extra;
2392
2393 if (GET_CODE (x) != PLUS)
2394 return false;
2395 if (GET_CODE (XEXP (x, 0)) != REG)
2396 return false;
2397 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict))
2398 return false;
60cdabab
DE		 2399 if (legitimate_constant_pool_address_p (x))
2400 return true;
4d588c14
RH		 2401 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
2402 return false;
2403
2404 offset = INTVAL (XEXP (x, 1));
2405 extra = 0;
2406 switch (mode)
2407 {
2408 case V16QImode:
2409 case V8HImode:
2410 case V4SFmode:
2411 case V4SImode:
2412 /* AltiVec vector modes. Only reg+reg addressing is valid here,
2413 which leaves the only valid constant offset of zero, which by
2414 canonicalization rules is also invalid. */
2415 return false;
2416
2417 case V4HImode:
2418 case V2SImode:
2419 case V1DImode:
2420 case V2SFmode:
2421 /* SPE vector modes. */
2422 return SPE_CONST_OFFSET_OK (offset);
2423
2424 case DFmode:
4d4cbc0e
AH		 2425 if (TARGET_E500_DOUBLE)
2426 return SPE_CONST_OFFSET_OK (offset);
2427
4d588c14 2428 case DImode:
54b695e7
AH		 2429 /* On e500v2, we may have:
2430
2431 (subreg:DF (mem:DI (plus (reg) (const_int))) 0).
2432
2433 Which gets addressed with evldd instructions. */
2434 if (TARGET_E500_DOUBLE)
2435 return SPE_CONST_OFFSET_OK (offset);
2436
3364872d 2437 if (mode == DFmode || !TARGET_POWERPC64)
4d588c14
RH		 2438 extra = 4;
2439 else if (offset & 3)
2440 return false;
2441 break;
2442
2443 case TFmode:
2444 case TImode:
3364872d 2445 if (mode == TFmode || !TARGET_POWERPC64)
4d588c14
RH		 2446 extra = 12;
2447 else if (offset & 3)
2448 return false;
2449 else
2450 extra = 8;
2451 break;
2452
2453 default:
2454 break;
2455 }
2456
b1917422
AM		 2457 offset += 0x8000;
2458 return (offset < 0x10000) && (offset + extra < 0x10000);
4d588c14
RH		 2459}
2460
2461static bool
a2369ed3 2462legitimate_indexed_address_p (rtx x, int strict)
4d588c14
RH		 2463{
2464 rtx op0, op1;
2465
2466 if (GET_CODE (x) != PLUS)
2467 return false;
850e8d3d 2468
4d588c14
RH		 2469 op0 = XEXP (x, 0);
2470 op1 = XEXP (x, 1);
2471
2472 if (!REG_P (op0) || !REG_P (op1))
2473 return false;
2474
2475 return ((INT_REG_OK_FOR_BASE_P (op0, strict)
2476 && INT_REG_OK_FOR_INDEX_P (op1, strict))
2477 || (INT_REG_OK_FOR_BASE_P (op1, strict)
2478 && INT_REG_OK_FOR_INDEX_P (op0, strict)));
9ebbca7d
GK		 2479}
2480
48d72335 2481inline bool
a2369ed3 2482legitimate_indirect_address_p (rtx x, int strict)
4d588c14
RH		 2483{
2484 return GET_CODE (x) == REG && INT_REG_OK_FOR_BASE_P (x, strict);
2485}
2486
48d72335 2487bool
4c81e946
FJ		 2488macho_lo_sum_memory_operand (rtx x, enum machine_mode mode)
2489{
c4ad648e 2490 if (!TARGET_MACHO || !flag_pic
9390387d 2491 || mode != SImode || GET_CODE (x) != MEM)
c4ad648e
AM		 2492 return false;
2493 x = XEXP (x, 0);
4c81e946
FJ		 2494
2495 if (GET_CODE (x) != LO_SUM)
2496 return false;
2497 if (GET_CODE (XEXP (x, 0)) != REG)
2498 return false;
2499 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), 0))
2500 return false;
2501 x = XEXP (x, 1);
2502
2503 return CONSTANT_P (x);
2504}
2505
4d588c14 2506static bool
a2369ed3 2507legitimate_lo_sum_address_p (enum machine_mode mode, rtx x, int strict)
4d588c14
RH		 2508{
2509 if (GET_CODE (x) != LO_SUM)
2510 return false;
2511 if (GET_CODE (XEXP (x, 0)) != REG)
2512 return false;
2513 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict))
2514 return false;
54b695e7
AH		 2515 /* Restrict addressing for DI because of our SUBREG hackery. */
2516 if (TARGET_E500_DOUBLE && (mode == DFmode || mode == DImode))
f82f556d 2517 return false;
4d588c14
RH		 2518 x = XEXP (x, 1);
2519
8622e235 2520 if (TARGET_ELF || TARGET_MACHO)
4d588c14 2521 {
a29077da 2522 if (DEFAULT_ABI != ABI_AIX && DEFAULT_ABI != ABI_DARWIN && flag_pic)
4d588c14
RH		 2523 return false;
2524 if (TARGET_TOC)
2525 return false;
2526 if (GET_MODE_NUNITS (mode) != 1)
2527 return false;
5e5f01b9 2528 if (GET_MODE_BITSIZE (mode) > 64
3c028f65
AM		 2529 || (GET_MODE_BITSIZE (mode) > 32 && !TARGET_POWERPC64
2530 && !(TARGET_HARD_FLOAT && TARGET_FPRS && mode == DFmode)))
4d588c14
RH		 2531 return false;
2532
2533 return CONSTANT_P (x);
2534 }
2535
2536 return false;
2537}
2538
2539
9ebbca7d
GK		 2540/* Try machine-dependent ways of modifying an illegitimate address
2541 to be legitimate. If we find one, return the new, valid address.
2542 This is used from only one place: `memory_address' in explow.c.
2543
a4f6c312
SS		 2544 OLDX is the address as it was before break_out_memory_refs was
2545 called. In some cases it is useful to look at this to decide what
2546 needs to be done.
9ebbca7d 2547
a4f6c312 2548 MODE is passed so that this function can use GO_IF_LEGITIMATE_ADDRESS.
9ebbca7d 2549
a4f6c312
SS		 2550 It is always safe for this function to do nothing. It exists to
2551 recognize opportunities to optimize the output.
9ebbca7d
GK		 2552
2553 On RS/6000, first check for the sum of a register with a constant
2554 integer that is out of range. If so, generate code to add the
2555 constant with the low-order 16 bits masked to the register and force
2556 this result into another register (this can be done with `cau').
2557 Then generate an address of REG+(CONST&0xffff), allowing for the
2558 possibility of bit 16 being a one.
2559
2560 Then check for the sum of a register and something not constant, try to
2561 load the other things into a register and return the sum. */
4d588c14 2562
9ebbca7d 2563rtx
a2369ed3
DJ		 2564rs6000_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
2565 enum machine_mode mode)
0ac081f6 2566{
c4501e62
JJ		 2567 if (GET_CODE (x) == SYMBOL_REF)
2568 {
2569 enum tls_model model = SYMBOL_REF_TLS_MODEL (x);
2570 if (model != 0)
2571 return rs6000_legitimize_tls_address (x, model);
2572 }
2573
f676971a 2574 if (GET_CODE (x) == PLUS
9ebbca7d
GK		 2575 && GET_CODE (XEXP (x, 0)) == REG
2576 && GET_CODE (XEXP (x, 1)) == CONST_INT
2577 && (unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 1)) + 0x8000) >= 0x10000)
f676971a 2578 {
9ebbca7d
GK		 2579 HOST_WIDE_INT high_int, low_int;
2580 rtx sum;
a65c591c
DE		 2581 low_int = ((INTVAL (XEXP (x, 1)) & 0xffff) ^ 0x8000) - 0x8000;
2582 high_int = INTVAL (XEXP (x, 1)) - low_int;
9ebbca7d
GK		 2583 sum = force_operand (gen_rtx_PLUS (Pmode, XEXP (x, 0),
2584 GEN_INT (high_int)), 0);
2585 return gen_rtx_PLUS (Pmode, sum, GEN_INT (low_int));
2586 }
f676971a 2587 else if (GET_CODE (x) == PLUS
9ebbca7d
GK		 2588 && GET_CODE (XEXP (x, 0)) == REG
2589 && GET_CODE (XEXP (x, 1)) != CONST_INT
6ac7bf2c 2590 && GET_MODE_NUNITS (mode) == 1
a3170dc6
AH		 2591 && ((TARGET_HARD_FLOAT && TARGET_FPRS)
2592 || TARGET_POWERPC64
54b695e7
AH		 2593 || (((mode != DImode && mode != DFmode) || TARGET_E500_DOUBLE)
2594 && mode != TFmode))
9ebbca7d
GK		 2595 && (TARGET_POWERPC64 || mode != DImode)
2596 && mode != TImode)
2597 {
2598 return gen_rtx_PLUS (Pmode, XEXP (x, 0),
2599 force_reg (Pmode, force_operand (XEXP (x, 1), 0)));
2600 }
0ac081f6
AH		 2601 else if (ALTIVEC_VECTOR_MODE (mode))
2602 {
2603 rtx reg;
2604
2605 /* Make sure both operands are registers. */
2606 if (GET_CODE (x) == PLUS)
9f85ed45 2607 return gen_rtx_PLUS (Pmode, force_reg (Pmode, XEXP (x, 0)),
0ac081f6
AH		 2608 force_reg (Pmode, XEXP (x, 1)));
2609
2610 reg = force_reg (Pmode, x);
2611 return reg;
2612 }
4d4cbc0e 2613 else if (SPE_VECTOR_MODE (mode)
54b695e7
AH		 2614 || (TARGET_E500_DOUBLE && (mode == DFmode
2615 || mode == DImode)))
a3170dc6 2616 {
54b695e7
AH		 2617 if (mode == DImode)
2618 return NULL_RTX;
a3170dc6
AH		 2619 /* We accept [reg + reg] and [reg + OFFSET]. */
2620
2621 if (GET_CODE (x) == PLUS)
c4ad648e
AM		 2622 {
2623 rtx op1 = XEXP (x, 0);
2624 rtx op2 = XEXP (x, 1);
a3170dc6 2625
c4ad648e 2626 op1 = force_reg (Pmode, op1);
a3170dc6 2627
c4ad648e
AM		 2628 if (GET_CODE (op2) != REG
2629 && (GET_CODE (op2) != CONST_INT
2630 || !SPE_CONST_OFFSET_OK (INTVAL (op2))))
2631 op2 = force_reg (Pmode, op2);
a3170dc6 2632
c4ad648e
AM		 2633 return gen_rtx_PLUS (Pmode, op1, op2);
2634 }
a3170dc6
AH		 2635
2636 return force_reg (Pmode, x);
2637 }
f1384257
AM		 2638 else if (TARGET_ELF
2639 && TARGET_32BIT
2640 && TARGET_NO_TOC
2641 && ! flag_pic
9ebbca7d 2642 && GET_CODE (x) != CONST_INT
f676971a 2643 && GET_CODE (x) != CONST_DOUBLE
9ebbca7d 2644 && CONSTANT_P (x)
6ac7bf2c
GK		 2645 && GET_MODE_NUNITS (mode) == 1
2646 && (GET_MODE_BITSIZE (mode) <= 32
a3170dc6 2647 || ((TARGET_HARD_FLOAT && TARGET_FPRS) && mode == DFmode)))
9ebbca7d
GK		 2648 {
2649 rtx reg = gen_reg_rtx (Pmode);
8a1977f3
GK		 2650 emit_insn (gen_elf_high (reg, x));
2651 return gen_rtx_LO_SUM (Pmode, reg, x);
9ebbca7d 2652 }
ee890fe2
SS		 2653 else if (TARGET_MACHO && TARGET_32BIT && TARGET_NO_TOC
2654 && ! flag_pic
ab82a49f
AP		 2655#if TARGET_MACHO
2656 && ! MACHO_DYNAMIC_NO_PIC_P
2657#endif
ee890fe2 2658 && GET_CODE (x) != CONST_INT
f676971a 2659 && GET_CODE (x) != CONST_DOUBLE
ee890fe2 2660 && CONSTANT_P (x)
f82f556d 2661 && ((TARGET_HARD_FLOAT && TARGET_FPRS) || mode != DFmode)
f676971a 2662 && mode != DImode
ee890fe2
SS		 2663 && mode != TImode)
2664 {
2665 rtx reg = gen_reg_rtx (Pmode);
8a1977f3
GK		 2666 emit_insn (gen_macho_high (reg, x));
2667 return gen_rtx_LO_SUM (Pmode, reg, x);
ee890fe2 2668 }
f676971a 2669 else if (TARGET_TOC
4d588c14 2670 && constant_pool_expr_p (x)
a9098fd0 2671 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x), Pmode))
9ebbca7d
GK		 2672 {
2673 return create_TOC_reference (x);
2674 }
2675 else
2676 return NULL_RTX;
2677}
258bfae2 2678
c973d557
JJ		 2679/* This is called from dwarf2out.c via ASM_OUTPUT_DWARF_DTPREL.
2680 We need to emit DTP-relative relocations. */
2681
2682void
2683rs6000_output_dwarf_dtprel (FILE *file, int size, rtx x)
2684{
2685 switch (size)
2686 {
2687 case 4:
2688 fputs ("\t.long\t", file);
2689 break;
2690 case 8:
2691 fputs (DOUBLE_INT_ASM_OP, file);
2692 break;
2693 default:
2694 abort ();
2695 }
2696 output_addr_const (file, x);
2697 fputs ("@dtprel+0x8000", file);
2698}
2699
c4501e62
JJ		 2700/* Construct the SYMBOL_REF for the tls_get_addr function. */
2701
2702static GTY(()) rtx rs6000_tls_symbol;
2703static rtx
863d938c 2704rs6000_tls_get_addr (void)
c4501e62
JJ		 2705{
2706 if (!rs6000_tls_symbol)
2707 rs6000_tls_symbol = init_one_libfunc ("__tls_get_addr");
2708
2709 return rs6000_tls_symbol;
2710}
2711
2712/* Construct the SYMBOL_REF for TLS GOT references. */
2713
2714static GTY(()) rtx rs6000_got_symbol;
2715static rtx
863d938c 2716rs6000_got_sym (void)
c4501e62
JJ		 2717{
2718 if (!rs6000_got_symbol)
2719 {
2720 rs6000_got_symbol = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
2721 SYMBOL_REF_FLAGS (rs6000_got_symbol) |= SYMBOL_FLAG_LOCAL;
2722 SYMBOL_REF_FLAGS (rs6000_got_symbol) |= SYMBOL_FLAG_EXTERNAL;
f676971a 2723 }
c4501e62
JJ		 2724
2725 return rs6000_got_symbol;
2726}
2727
2728/* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
2729 this (thread-local) address. */
2730
2731static rtx
a2369ed3 2732rs6000_legitimize_tls_address (rtx addr, enum tls_model model)
c4501e62
JJ		 2733{
2734 rtx dest, insn;
2735
2736 dest = gen_reg_rtx (Pmode);
2737 if (model == TLS_MODEL_LOCAL_EXEC && rs6000_tls_size == 16)
2738 {
2739 rtx tlsreg;
2740
2741 if (TARGET_64BIT)
2742 {
2743 tlsreg = gen_rtx_REG (Pmode, 13);
2744 insn = gen_tls_tprel_64 (dest, tlsreg, addr);
2745 }
2746 else
2747 {
2748 tlsreg = gen_rtx_REG (Pmode, 2);
2749 insn = gen_tls_tprel_32 (dest, tlsreg, addr);
2750 }
2751 emit_insn (insn);
2752 }
2753 else if (model == TLS_MODEL_LOCAL_EXEC && rs6000_tls_size == 32)
2754 {
2755 rtx tlsreg, tmp;
2756
2757 tmp = gen_reg_rtx (Pmode);
2758 if (TARGET_64BIT)
2759 {
2760 tlsreg = gen_rtx_REG (Pmode, 13);
2761 insn = gen_tls_tprel_ha_64 (tmp, tlsreg, addr);
2762 }
2763 else
2764 {
2765 tlsreg = gen_rtx_REG (Pmode, 2);
2766 insn = gen_tls_tprel_ha_32 (tmp, tlsreg, addr);
2767 }
2768 emit_insn (insn);
2769 if (TARGET_64BIT)
2770 insn = gen_tls_tprel_lo_64 (dest, tmp, addr);
2771 else
2772 insn = gen_tls_tprel_lo_32 (dest, tmp, addr);
2773 emit_insn (insn);
2774 }
2775 else
2776 {
2777 rtx r3, got, tga, tmp1, tmp2, eqv;
2778
2779 if (TARGET_64BIT)
2780 got = gen_rtx_REG (Pmode, TOC_REGISTER);
2781 else
2782 {
2783 if (flag_pic == 1)
2784 got = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
2785 else
2786 {
2787 rtx gsym = rs6000_got_sym ();
2788 got = gen_reg_rtx (Pmode);
2789 if (flag_pic == 0)
2790 rs6000_emit_move (got, gsym, Pmode);
2791 else
2792 {
2793 char buf[30];
2794 static int tls_got_labelno = 0;
2795 rtx tempLR, lab, tmp3, mem;
2796 rtx first, last;
2797
2798 ASM_GENERATE_INTERNAL_LABEL (buf, "LTLS", tls_got_labelno++);
2799 lab = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
2800 tempLR = gen_reg_rtx (Pmode);
2801 tmp1 = gen_reg_rtx (Pmode);
2802 tmp2 = gen_reg_rtx (Pmode);
2803 tmp3 = gen_reg_rtx (Pmode);
542a8afa 2804 mem = gen_const_mem (Pmode, tmp1);
c4501e62
JJ		 2805
2806 first = emit_insn (gen_load_toc_v4_PIC_1b (tempLR, lab,
2807 gsym));
2808 emit_move_insn (tmp1, tempLR);
2809 emit_move_insn (tmp2, mem);
2810 emit_insn (gen_addsi3 (tmp3, tmp1, tmp2));
2811 last = emit_move_insn (got, tmp3);
2812 REG_NOTES (last) = gen_rtx_EXPR_LIST (REG_EQUAL, gsym,
2813 REG_NOTES (last));
2814 REG_NOTES (first) = gen_rtx_INSN_LIST (REG_LIBCALL, last,
2815 REG_NOTES (first));
2816 REG_NOTES (last) = gen_rtx_INSN_LIST (REG_RETVAL, first,
2817 REG_NOTES (last));
2818 }
2819 }
2820 }
2821
2822 if (model == TLS_MODEL_GLOBAL_DYNAMIC)
2823 {
2824 r3 = gen_rtx_REG (Pmode, 3);
2825 if (TARGET_64BIT)
2826 insn = gen_tls_gd_64 (r3, got, addr);
2827 else
2828 insn = gen_tls_gd_32 (r3, got, addr);
2829 start_sequence ();
2830 emit_insn (insn);
2831 tga = gen_rtx_MEM (Pmode, rs6000_tls_get_addr ());
2832 insn = gen_call_value (r3, tga, const0_rtx, const0_rtx);
2833 insn = emit_call_insn (insn);
2834 CONST_OR_PURE_CALL_P (insn) = 1;
2835 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), r3);
2836 insn = get_insns ();
2837 end_sequence ();
2838 emit_libcall_block (insn, dest, r3, addr);
2839 }
2840 else if (model == TLS_MODEL_LOCAL_DYNAMIC)
2841 {
2842 r3 = gen_rtx_REG (Pmode, 3);
2843 if (TARGET_64BIT)
2844 insn = gen_tls_ld_64 (r3, got);
2845 else
2846 insn = gen_tls_ld_32 (r3, got);
2847 start_sequence ();
2848 emit_insn (insn);
2849 tga = gen_rtx_MEM (Pmode, rs6000_tls_get_addr ());
2850 insn = gen_call_value (r3, tga, const0_rtx, const0_rtx);
2851 insn = emit_call_insn (insn);
2852 CONST_OR_PURE_CALL_P (insn) = 1;
2853 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), r3);
2854 insn = get_insns ();
2855 end_sequence ();
2856 tmp1 = gen_reg_rtx (Pmode);
2857 eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
2858 UNSPEC_TLSLD);
2859 emit_libcall_block (insn, tmp1, r3, eqv);
2860 if (rs6000_tls_size == 16)
2861 {
2862 if (TARGET_64BIT)
2863 insn = gen_tls_dtprel_64 (dest, tmp1, addr);
2864 else
2865 insn = gen_tls_dtprel_32 (dest, tmp1, addr);
2866 }
2867 else if (rs6000_tls_size == 32)
2868 {
2869 tmp2 = gen_reg_rtx (Pmode);
2870 if (TARGET_64BIT)
2871 insn = gen_tls_dtprel_ha_64 (tmp2, tmp1, addr);
2872 else
2873 insn = gen_tls_dtprel_ha_32 (tmp2, tmp1, addr);
2874 emit_insn (insn);
2875 if (TARGET_64BIT)
2876 insn = gen_tls_dtprel_lo_64 (dest, tmp2, addr);
2877 else
2878 insn = gen_tls_dtprel_lo_32 (dest, tmp2, addr);
2879 }
2880 else
2881 {
2882 tmp2 = gen_reg_rtx (Pmode);
2883 if (TARGET_64BIT)
2884 insn = gen_tls_got_dtprel_64 (tmp2, got, addr);
2885 else
2886 insn = gen_tls_got_dtprel_32 (tmp2, got, addr);
2887 emit_insn (insn);
2888 insn = gen_rtx_SET (Pmode, dest,
2889 gen_rtx_PLUS (Pmode, tmp2, tmp1));
2890 }
2891 emit_insn (insn);
2892 }
2893 else
2894 {
2895 /* IE, or 64 bit offset LE. */
2896 tmp2 = gen_reg_rtx (Pmode);
2897 if (TARGET_64BIT)
2898 insn = gen_tls_got_tprel_64 (tmp2, got, addr);
2899 else
2900 insn = gen_tls_got_tprel_32 (tmp2, got, addr);
2901 emit_insn (insn);
2902 if (TARGET_64BIT)
2903 insn = gen_tls_tls_64 (dest, tmp2, addr);
2904 else
2905 insn = gen_tls_tls_32 (dest, tmp2, addr);
2906 emit_insn (insn);
2907 }
2908 }
2909
2910 return dest;
2911}
2912
c4501e62
JJ		 2913/* Return 1 if X contains a thread-local symbol. */
2914
2915bool
a2369ed3 2916rs6000_tls_referenced_p (rtx x)
c4501e62 2917{
cd413cab
AP		 2918 if (! TARGET_HAVE_TLS)
2919 return false;
2920
c4501e62
JJ		 2921 return for_each_rtx (&x, &rs6000_tls_symbol_ref_1, 0);
2922}
2923
2924/* Return 1 if *X is a thread-local symbol. This is the same as
2925 rs6000_tls_symbol_ref except for the type of the unused argument. */
2926
9390387d 2927static int
a2369ed3 2928rs6000_tls_symbol_ref_1 (rtx *x, void *data ATTRIBUTE_UNUSED)
c4501e62
JJ		 2929{
2930 return RS6000_SYMBOL_REF_TLS_P (*x);
2931}
2932
24ea750e
DJ		 2933/* The convention appears to be to define this wherever it is used.
2934 With legitimize_reload_address now defined here, REG_MODE_OK_FOR_BASE_P
2935 is now used here. */
2936#ifndef REG_MODE_OK_FOR_BASE_P
2937#define REG_MODE_OK_FOR_BASE_P(REGNO, MODE) REG_OK_FOR_BASE_P (REGNO)
2938#endif
2939
2940/* Our implementation of LEGITIMIZE_RELOAD_ADDRESS. Returns a value to
2941 replace the input X, or the original X if no replacement is called for.
2942 The output parameter *WIN is 1 if the calling macro should goto WIN,
2943 0 if it should not.
2944
2945 For RS/6000, we wish to handle large displacements off a base
2946 register by splitting the addend across an addiu/addis and the mem insn.
2947 This cuts number of extra insns needed from 3 to 1.
2948
2949 On Darwin, we use this to generate code for floating point constants.
2950 A movsf_low is generated so we wind up with 2 instructions rather than 3.
2951 The Darwin code is inside #if TARGET_MACHO because only then is
2952 machopic_function_base_name() defined. */
2953rtx
f676971a 2954rs6000_legitimize_reload_address (rtx x, enum machine_mode mode,
c4ad648e
AM		 2955 int opnum, int type,
2956 int ind_levels ATTRIBUTE_UNUSED, int *win)
24ea750e 2957{
f676971a 2958 /* We must recognize output that we have already generated ourselves. */
24ea750e
DJ		 2959 if (GET_CODE (x) == PLUS
2960 && GET_CODE (XEXP (x, 0)) == PLUS
2961 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
2962 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
2963 && GET_CODE (XEXP (x, 1)) == CONST_INT)
2964 {
2965 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
c4ad648e
AM		 2966 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
2967 opnum, (enum reload_type)type);
24ea750e
DJ		 2968 *win = 1;
2969 return x;
2970 }
3deb2758 2971
24ea750e
DJ		 2972#if TARGET_MACHO
2973 if (DEFAULT_ABI == ABI_DARWIN && flag_pic
2974 && GET_CODE (x) == LO_SUM
2975 && GET_CODE (XEXP (x, 0)) == PLUS
2976 && XEXP (XEXP (x, 0), 0) == pic_offset_table_rtx
2977 && GET_CODE (XEXP (XEXP (x, 0), 1)) == HIGH
2978 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 1), 0)) == CONST
2979 && XEXP (XEXP (XEXP (x, 0), 1), 0) == XEXP (x, 1)
2980 && GET_CODE (XEXP (XEXP (x, 1), 0)) == MINUS
2981 && GET_CODE (XEXP (XEXP (XEXP (x, 1), 0), 0)) == SYMBOL_REF
2982 && GET_CODE (XEXP (XEXP (XEXP (x, 1), 0), 1)) == SYMBOL_REF)
2983 {
2984 /* Result of previous invocation of this function on Darwin
6f317ef3 2985 floating point constant. */
24ea750e 2986 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
c4ad648e
AM		 2987 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
2988 opnum, (enum reload_type)type);
24ea750e
DJ		 2989 *win = 1;
2990 return x;
2991 }
2992#endif
4937d02d
DE		 2993
2994 /* Force ld/std non-word aligned offset into base register by wrapping
2995 in offset 0. */
2996 if (GET_CODE (x) == PLUS
2997 && GET_CODE (XEXP (x, 0)) == REG
2998 && REGNO (XEXP (x, 0)) < 32
2999 && REG_MODE_OK_FOR_BASE_P (XEXP (x, 0), mode)
3000 && GET_CODE (XEXP (x, 1)) == CONST_INT
3001 && (INTVAL (XEXP (x, 1)) & 3) != 0
78796ad5 3002 && !ALTIVEC_VECTOR_MODE (mode)
4937d02d
DE		 3003 && GET_MODE_SIZE (mode) >= UNITS_PER_WORD
3004 && TARGET_POWERPC64)
3005 {
3006 x = gen_rtx_PLUS (GET_MODE (x), x, GEN_INT (0));
3007 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3008 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
3009 opnum, (enum reload_type) type);
3010 *win = 1;
3011 return x;
3012 }
3013
24ea750e
DJ		 3014 if (GET_CODE (x) == PLUS
3015 && GET_CODE (XEXP (x, 0)) == REG
3016 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
3017 && REG_MODE_OK_FOR_BASE_P (XEXP (x, 0), mode)
78c875e8 3018 && GET_CODE (XEXP (x, 1)) == CONST_INT
93638d7a 3019 && !SPE_VECTOR_MODE (mode)
54b695e7
AH		 3020 && !(TARGET_E500_DOUBLE && (mode == DFmode
3021 || mode == DImode))
78c875e8 3022 && !ALTIVEC_VECTOR_MODE (mode))
24ea750e
DJ		 3023 {
3024 HOST_WIDE_INT val = INTVAL (XEXP (x, 1));
3025 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
3026 HOST_WIDE_INT high
c4ad648e 3027 = (((val - low) & 0xffffffff) ^ 0x80000000) - 0x80000000;
24ea750e
DJ		 3028
3029 /* Check for 32-bit overflow. */
3030 if (high + low != val)
c4ad648e 3031 {
24ea750e
DJ		 3032 *win = 0;
3033 return x;
3034 }
3035
3036 /* Reload the high part into a base reg; leave the low part
c4ad648e 3037 in the mem directly. */
24ea750e
DJ		 3038
3039 x = gen_rtx_PLUS (GET_MODE (x),
c4ad648e
AM		 3040 gen_rtx_PLUS (GET_MODE (x), XEXP (x, 0),
3041 GEN_INT (high)),
3042 GEN_INT (low));
24ea750e
DJ		 3043
3044 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
c4ad648e
AM		 3045 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
3046 opnum, (enum reload_type)type);
24ea750e
DJ		 3047 *win = 1;
3048 return x;
3049 }
4937d02d 3050
24ea750e
DJ		 3051#if TARGET_MACHO
3052 if (GET_CODE (x) == SYMBOL_REF
3053 && DEFAULT_ABI == ABI_DARWIN
69ef87e2 3054 && !ALTIVEC_VECTOR_MODE (mode)
a29077da 3055 && (flag_pic || MACHO_DYNAMIC_NO_PIC_P)
0d8c1c97
AM		 3056 /* Don't do this for TFmode, since the result isn't offsettable.
3057 The same goes for DImode without 64-bit gprs. */
3058 && mode != TFmode
3059 && (mode != DImode || TARGET_POWERPC64))
24ea750e 3060 {
a29077da
GK		 3061 if (flag_pic)
3062 {
3063 rtx offset = gen_rtx_CONST (Pmode,
3064 gen_rtx_MINUS (Pmode, x,
11abc112 3065 machopic_function_base_sym ()));
a29077da
GK		 3066 x = gen_rtx_LO_SUM (GET_MODE (x),
3067 gen_rtx_PLUS (Pmode, pic_offset_table_rtx,
3068 gen_rtx_HIGH (Pmode, offset)), offset);
3069 }
3070 else
3071 x = gen_rtx_LO_SUM (GET_MODE (x),
c4ad648e 3072 gen_rtx_HIGH (Pmode, x), x);
a29077da 3073
24ea750e 3074 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
a29077da
GK		 3075 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
3076 opnum, (enum reload_type)type);
24ea750e
DJ		 3077 *win = 1;
3078 return x;
3079 }
3080#endif
4937d02d 3081
24ea750e 3082 if (TARGET_TOC
4d588c14 3083 && constant_pool_expr_p (x)
c1f11548 3084 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x), mode))
24ea750e
DJ		 3085 {
3086 (x) = create_TOC_reference (x);
3087 *win = 1;
3088 return x;
3089 }
3090 *win = 0;
3091 return x;
f676971a 3092}
24ea750e 3093
258bfae2
FS		 3094/* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
3095 that is a valid memory address for an instruction.
3096 The MODE argument is the machine mode for the MEM expression
3097 that wants to use this address.
3098
3099 On the RS/6000, there are four valid address: a SYMBOL_REF that
3100 refers to a constant pool entry of an address (or the sum of it
3101 plus a constant), a short (16-bit signed) constant plus a register,
3102 the sum of two registers, or a register indirect, possibly with an
5bdc5878 3103 auto-increment. For DFmode and DImode with a constant plus register,
258bfae2
FS		 3104 we must ensure that both words are addressable or PowerPC64 with offset
3105 word aligned.
3106
3107 For modes spanning multiple registers (DFmode in 32-bit GPRs,
76d2b81d 3108 32-bit DImode, TImode, TFmode), indexed addressing cannot be used because
258bfae2
FS		 3109 adjacent memory cells are accessed by adding word-sized offsets
3110 during assembly output. */
3111int
a2369ed3 3112rs6000_legitimate_address (enum machine_mode mode, rtx x, int reg_ok_strict)
258bfae2 3113{
850e8d3d
DN		 3114 /* If this is an unaligned stvx/ldvx type address, discard the outer AND. */
3115 if (TARGET_ALTIVEC
3116 && ALTIVEC_VECTOR_MODE (mode)
3117 && GET_CODE (x) == AND
3118 && GET_CODE (XEXP (x, 1)) == CONST_INT
3119 && INTVAL (XEXP (x, 1)) == -16)
3120 x = XEXP (x, 0);
3121
c4501e62
JJ		 3122 if (RS6000_SYMBOL_REF_TLS_P (x))
3123 return 0;
4d588c14 3124 if (legitimate_indirect_address_p (x, reg_ok_strict))
258bfae2
FS		 3125 return 1;
3126 if ((GET_CODE (x) == PRE_INC || GET_CODE (x) == PRE_DEC)
0d6d6892 3127 && !ALTIVEC_VECTOR_MODE (mode)
a3170dc6 3128 && !SPE_VECTOR_MODE (mode)
54b695e7
AH		 3129 /* Restrict addressing for DI because of our SUBREG hackery. */
3130 && !(TARGET_E500_DOUBLE && (mode == DFmode || mode == DImode))
258bfae2 3131 && TARGET_UPDATE
4d588c14 3132 && legitimate_indirect_address_p (XEXP (x, 0), reg_ok_strict))
258bfae2 3133 return 1;
4d588c14 3134 if (legitimate_small_data_p (mode, x))
258bfae2 3135 return 1;
4d588c14 3136 if (legitimate_constant_pool_address_p (x))
258bfae2
FS		 3137 return 1;
3138 /* If not REG_OK_STRICT (before reload) let pass any stack offset. */
3139 if (! reg_ok_strict
3140 && GET_CODE (x) == PLUS
3141 && GET_CODE (XEXP (x, 0)) == REG
708d2456 3142 && (XEXP (x, 0) == virtual_stack_vars_rtx
c4ad648e 3143 || XEXP (x, 0) == arg_pointer_rtx)
258bfae2
FS		 3144 && GET_CODE (XEXP (x, 1)) == CONST_INT)
3145 return 1;
76d2b81d 3146 if (rs6000_legitimate_offset_address_p (mode, x, reg_ok_strict))
258bfae2
FS		 3147 return 1;
3148 if (mode != TImode
76d2b81d 3149 && mode != TFmode
a3170dc6
AH		 3150 && ((TARGET_HARD_FLOAT && TARGET_FPRS)
3151 || TARGET_POWERPC64
4d4cbc0e 3152 || ((mode != DFmode || TARGET_E500_DOUBLE) && mode != TFmode))
258bfae2 3153 && (TARGET_POWERPC64 || mode != DImode)
4d588c14 3154 && legitimate_indexed_address_p (x, reg_ok_strict))
258bfae2 3155 return 1;
4d588c14 3156 if (legitimate_lo_sum_address_p (mode, x, reg_ok_strict))
258bfae2
FS		 3157 return 1;
3158 return 0;
3159}
4d588c14
RH		 3160
3161/* Go to LABEL if ADDR (a legitimate address expression)
3162 has an effect that depends on the machine mode it is used for.
3163
3164 On the RS/6000 this is true of all integral offsets (since AltiVec
3165 modes don't allow them) or is a pre-increment or decrement.
3166
3167 ??? Except that due to conceptual problems in offsettable_address_p
3168 we can't really report the problems of integral offsets. So leave
f676971a 3169 this assuming that the adjustable offset must be valid for the
4d588c14
RH		 3170 sub-words of a TFmode operand, which is what we had before. */
3171
3172bool
a2369ed3 3173rs6000_mode_dependent_address (rtx addr)
4d588c14
RH		 3174{
3175 switch (GET_CODE (addr))
3176 {
3177 case PLUS:
3178 if (GET_CODE (XEXP (addr, 1)) == CONST_INT)
3179 {
3180 unsigned HOST_WIDE_INT val = INTVAL (XEXP (addr, 1));
3181 return val + 12 + 0x8000 >= 0x10000;
3182 }
3183 break;
3184
3185 case LO_SUM:
3186 return true;
3187
3188 case PRE_INC:
3189 case PRE_DEC:
3190 return TARGET_UPDATE;
3191
3192 default:
3193 break;
3194 }
3195
3196 return false;
3197}
d8ecbcdb
AH		 3198
3199/* Return number of consecutive hard regs needed starting at reg REGNO
3200 to hold something of mode MODE.
3201 This is ordinarily the length in words of a value of mode MODE
3202 but can be less for certain modes in special long registers.
3203
3204 For the SPE, GPRs are 64 bits but only 32 bits are visible in
3205 scalar instructions. The upper 32 bits are only available to the
3206 SIMD instructions.
3207
3208 POWER and PowerPC GPRs hold 32 bits worth;
3209 PowerPC64 GPRs and FPRs point register holds 64 bits worth. */
3210
3211int
3212rs6000_hard_regno_nregs (int regno, enum machine_mode mode)
3213{
3214 if (FP_REGNO_P (regno))
3215 return (GET_MODE_SIZE (mode) + UNITS_PER_FP_WORD - 1) / UNITS_PER_FP_WORD;
3216
4d4cbc0e
AH		 3217 if (TARGET_E500_DOUBLE && mode == DFmode)
3218 return 1;
3219
d8ecbcdb
AH		 3220 if (SPE_SIMD_REGNO_P (regno) && TARGET_SPE && SPE_VECTOR_MODE (mode))
3221 return (GET_MODE_SIZE (mode) + UNITS_PER_SPE_WORD - 1) / UNITS_PER_SPE_WORD;
3222
3223 if (ALTIVEC_REGNO_P (regno))
3224 return
3225 (GET_MODE_SIZE (mode) + UNITS_PER_ALTIVEC_WORD - 1) / UNITS_PER_ALTIVEC_WORD;
3226
3227 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
3228}
2aa4498c
AH		 3229
3230/* Change register usage conditional on target flags. */
3231void
3232rs6000_conditional_register_usage (void)
3233{
3234 int i;
3235
3236 /* Set MQ register fixed (already call_used) if not POWER
3237 architecture (RIOS1, RIOS2, RSC, and PPC601) so that it will not
3238 be allocated. */
3239 if (! TARGET_POWER)
3240 fixed_regs[64] = 1;
3241
3242 /* 64-bit AIX reserves GPR13 for thread-private data. */
3243 if (TARGET_64BIT)
3244 fixed_regs[13] = call_used_regs[13]
3245 = call_really_used_regs[13] = 1;
3246
3247 /* Conditionally disable FPRs. */
3248 if (TARGET_SOFT_FLOAT || !TARGET_FPRS)
3249 for (i = 32; i < 64; i++)
3250 fixed_regs[i] = call_used_regs[i]
c4ad648e 3251 = call_really_used_regs[i] = 1;
2aa4498c
AH		 3252
3253 if (DEFAULT_ABI == ABI_V4
3254 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM
3255 && flag_pic == 2)
3256 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
3257
3258 if (DEFAULT_ABI == ABI_V4
3259 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM
3260 && flag_pic == 1)
3261 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
3262 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
3263 = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
3264
3265 if (DEFAULT_ABI == ABI_DARWIN
3266 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM)
3267 global_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
3268 = fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
3269 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
3270 = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
3271
b4db40bf
JJ		 3272 if (TARGET_TOC && TARGET_MINIMAL_TOC)
3273 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
3274 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
3275
2aa4498c
AH		 3276 if (TARGET_ALTIVEC)
3277 global_regs[VSCR_REGNO] = 1;
3278
3279 if (TARGET_SPE)
3280 {
3281 global_regs[SPEFSCR_REGNO] = 1;
3282 fixed_regs[FIXED_SCRATCH]
c4ad648e 3283 = call_used_regs[FIXED_SCRATCH]
2aa4498c
AH		 3284 = call_really_used_regs[FIXED_SCRATCH] = 1;
3285 }
3286
3287 if (! TARGET_ALTIVEC)
3288 {
3289 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
3290 fixed_regs[i] = call_used_regs[i] = call_really_used_regs[i] = 1;
3291 call_really_used_regs[VRSAVE_REGNO] = 1;
3292 }
3293
3294 if (TARGET_ALTIVEC_ABI)
3295 for (i = FIRST_ALTIVEC_REGNO; i < FIRST_ALTIVEC_REGNO + 20; ++i)
3296 call_used_regs[i] = call_really_used_regs[i] = 1;
3297}
fb4d4348 3298\f
a4f6c312
SS		 3299/* Try to output insns to set TARGET equal to the constant C if it can
3300 be done in less than N insns. Do all computations in MODE.
3301 Returns the place where the output has been placed if it can be
3302 done and the insns have been emitted. If it would take more than N
3303 insns, zero is returned and no insns and emitted. */
2bfcf297
DB		 3304
3305rtx
f676971a 3306rs6000_emit_set_const (rtx dest, enum machine_mode mode,
a2369ed3 3307 rtx source, int n ATTRIBUTE_UNUSED)
2bfcf297 3308{
af8cb5c5 3309 rtx result, insn, set;
2bfcf297
DB		 3310 HOST_WIDE_INT c0, c1;
3311
af8cb5c5 3312 if (mode == QImode || mode == HImode)
2bfcf297
DB		 3313 {
3314 if (dest == NULL)
c4ad648e 3315 dest = gen_reg_rtx (mode);
2bfcf297
DB		 3316 emit_insn (gen_rtx_SET (VOIDmode, dest, source));
3317 return dest;
3318 }
af8cb5c5 3319 else if (mode == SImode)
2bfcf297 3320 {
af8cb5c5
DE		 3321 result = no_new_pseudos ? dest : gen_reg_rtx (SImode);
3322
3323 emit_insn (gen_rtx_SET (VOIDmode, result,
3324 GEN_INT (INTVAL (source)
3325 & (~ (HOST_WIDE_INT) 0xffff))));
3326 emit_insn (gen_rtx_SET (VOIDmode, dest,
3327 gen_rtx_IOR (SImode, result,
3328 GEN_INT (INTVAL (source) & 0xffff))));
3329 result = dest;
2bfcf297 3330 }
af8cb5c5 3331 else if (mode == DImode)
2bfcf297 3332 {
af8cb5c5
DE		 3333 if (GET_CODE (source) == CONST_INT)
3334 {
3335 c0 = INTVAL (source);
3336 c1 = -(c0 < 0);
3337 }
3338 else if (GET_CODE (source) == CONST_DOUBLE)
3339 {
2bfcf297 3340#if HOST_BITS_PER_WIDE_INT >= 64
af8cb5c5
DE		 3341 c0 = CONST_DOUBLE_LOW (source);
3342 c1 = -(c0 < 0);
2bfcf297 3343#else
af8cb5c5
DE		 3344 c0 = CONST_DOUBLE_LOW (source);
3345 c1 = CONST_DOUBLE_HIGH (source);
2bfcf297 3346#endif
af8cb5c5
DE		 3347 }
3348 else
3349 abort ();
3350
3351 result = rs6000_emit_set_long_const (dest, c0, c1);
2bfcf297
DB		 3352 }
3353 else
a4f6c312 3354 abort ();
2bfcf297 3355
af8cb5c5
DE		 3356 insn = get_last_insn ();
3357 set = single_set (insn);
3358 if (! CONSTANT_P (SET_SRC (set)))
3359 set_unique_reg_note (insn, REG_EQUAL, source);
3360
3361 return result;
2bfcf297
DB		 3362}
3363
3364/* Having failed to find a 3 insn sequence in rs6000_emit_set_const,
3365 fall back to a straight forward decomposition. We do this to avoid
3366 exponential run times encountered when looking for longer sequences
3367 with rs6000_emit_set_const. */
3368static rtx
a2369ed3 3369rs6000_emit_set_long_const (rtx dest, HOST_WIDE_INT c1, HOST_WIDE_INT c2)
2bfcf297
DB		 3370{
3371 if (!TARGET_POWERPC64)
3372 {
3373 rtx operand1, operand2;
3374
3375 operand1 = operand_subword_force (dest, WORDS_BIG_ENDIAN == 0,
3376 DImode);
3377 operand2 = operand_subword_force (dest, WORDS_BIG_ENDIAN != 0,
3378 DImode);
3379 emit_move_insn (operand1, GEN_INT (c1));
3380 emit_move_insn (operand2, GEN_INT (c2));
3381 }
3382 else
3383 {
bc06712d 3384 HOST_WIDE_INT ud1, ud2, ud3, ud4;
252b88f7 3385
bc06712d 3386 ud1 = c1 & 0xffff;
f921c9c9 3387 ud2 = (c1 & 0xffff0000) >> 16;
2bfcf297 3388#if HOST_BITS_PER_WIDE_INT >= 64
bc06712d 3389 c2 = c1 >> 32;
2bfcf297 3390#endif
bc06712d 3391 ud3 = c2 & 0xffff;
f921c9c9 3392 ud4 = (c2 & 0xffff0000) >> 16;
2bfcf297 3393
f676971a 3394 if ((ud4 == 0xffff && ud3 == 0xffff && ud2 == 0xffff && (ud1 & 0x8000))
bc06712d 3395 || (ud4 == 0 && ud3 == 0 && ud2 == 0 && ! (ud1 & 0x8000)))
2bfcf297 3396 {
bc06712d 3397 if (ud1 & 0x8000)
b78d48dd 3398 emit_move_insn (dest, GEN_INT (((ud1 ^ 0x8000) - 0x8000)));
bc06712d
TR		 3399 else
3400 emit_move_insn (dest, GEN_INT (ud1));
2bfcf297 3401 }
2bfcf297 3402
f676971a 3403 else if ((ud4 == 0xffff && ud3 == 0xffff && (ud2 & 0x8000))
bc06712d 3404 || (ud4 == 0 && ud3 == 0 && ! (ud2 & 0x8000)))
252b88f7 3405 {
bc06712d 3406 if (ud2 & 0x8000)
f676971a 3407 emit_move_insn (dest, GEN_INT (((ud2 << 16) ^ 0x80000000)
bc06712d 3408 - 0x80000000));
252b88f7 3409 else
bc06712d
TR		 3410 emit_move_insn (dest, GEN_INT (ud2 << 16));
3411 if (ud1 != 0)
3412 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud1)));
252b88f7 3413 }
f676971a 3414 else if ((ud4 == 0xffff && (ud3 & 0x8000))
bc06712d
TR		 3415 || (ud4 == 0 && ! (ud3 & 0x8000)))
3416 {
3417 if (ud3 & 0x8000)
f676971a 3418 emit_move_insn (dest, GEN_INT (((ud3 << 16) ^ 0x80000000)
bc06712d
TR		 3419 - 0x80000000));
3420 else
3421 emit_move_insn (dest, GEN_INT (ud3 << 16));
3422
3423 if (ud2 != 0)
3424 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud2)));
3425 emit_move_insn (dest, gen_rtx_ASHIFT (DImode, dest, GEN_INT (16)));
3426 if (ud1 != 0)
3427 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud1)));
3428 }
f676971a 3429 else
bc06712d
TR		 3430 {
3431 if (ud4 & 0x8000)
f676971a 3432 emit_move_insn (dest, GEN_INT (((ud4 << 16) ^ 0x80000000)
bc06712d
TR		 3433 - 0x80000000));
3434 else
3435 emit_move_insn (dest, GEN_INT (ud4 << 16));
3436
3437 if (ud3 != 0)
3438 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud3)));
2bfcf297 3439
bc06712d
TR		 3440 emit_move_insn (dest, gen_rtx_ASHIFT (DImode, dest, GEN_INT (32)));
3441 if (ud2 != 0)
f676971a
EC		 3442 emit_move_insn (dest, gen_rtx_IOR (DImode, dest,
3443 GEN_INT (ud2 << 16)));
bc06712d
TR		 3444 if (ud1 != 0)
3445 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud1)));
3446 }
3447 }
2bfcf297
DB		 3448 return dest;
3449}
3450
76d2b81d
DJ		 3451/* Helper for the following. Get rid of [r+r] memory refs
3452 in cases where it won't work (TImode, TFmode). */
3453
3454static void
3455rs6000_eliminate_indexed_memrefs (rtx operands[2])
3456{
3457 if (GET_CODE (operands[0]) == MEM
3458 && GET_CODE (XEXP (operands[0], 0)) != REG
55aa0757 3459 && ! legitimate_constant_pool_address_p (XEXP (operands[0], 0))
76d2b81d
DJ		 3460 && ! reload_in_progress)
3461 operands[0]
3462 = replace_equiv_address (operands[0],
3463 copy_addr_to_reg (XEXP (operands[0], 0)));
3464
3465 if (GET_CODE (operands[1]) == MEM
3466 && GET_CODE (XEXP (operands[1], 0)) != REG
55aa0757 3467 && ! legitimate_constant_pool_address_p (XEXP (operands[1], 0))
76d2b81d
DJ		 3468 && ! reload_in_progress)
3469 operands[1]
3470 = replace_equiv_address (operands[1],
3471 copy_addr_to_reg (XEXP (operands[1], 0)));
3472}
3473
fb4d4348
GK		 3474/* Emit a move from SOURCE to DEST in mode MODE. */
3475void
a2369ed3 3476rs6000_emit_move (rtx dest, rtx source, enum machine_mode mode)
fb4d4348
GK		 3477{
3478 rtx operands[2];
3479 operands[0] = dest;
3480 operands[1] = source;
f676971a 3481
fb4d4348
GK		 3482 /* Sanity checks. Check that we get CONST_DOUBLE only when we should. */
3483 if (GET_CODE (operands[1]) == CONST_DOUBLE
3484 && ! FLOAT_MODE_P (mode)
3485 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
3486 {
3487 /* FIXME. This should never happen. */
3488 /* Since it seems that it does, do the safe thing and convert
3489 to a CONST_INT. */
2496c7bd 3490 operands[1] = gen_int_mode (CONST_DOUBLE_LOW (operands[1]), mode);
fb4d4348
GK		 3491 }
3492 if (GET_CODE (operands[1]) == CONST_DOUBLE
3493 && ! FLOAT_MODE_P (mode)
3494 && ((CONST_DOUBLE_HIGH (operands[1]) == 0
3495 && CONST_DOUBLE_LOW (operands[1]) >= 0)
3496 || (CONST_DOUBLE_HIGH (operands[1]) == -1
3497 && CONST_DOUBLE_LOW (operands[1]) < 0)))
3498 abort ();
c9e8cb32
DD		 3499
3500 /* Check if GCC is setting up a block move that will end up using FP
3501 registers as temporaries. We must make sure this is acceptable. */
3502 if (GET_CODE (operands[0]) == MEM
3503 && GET_CODE (operands[1]) == MEM
3504 && mode == DImode
41543739
GK		 3505 && (SLOW_UNALIGNED_ACCESS (DImode, MEM_ALIGN (operands[0]))
3506 || SLOW_UNALIGNED_ACCESS (DImode, MEM_ALIGN (operands[1])))
3507 && ! (SLOW_UNALIGNED_ACCESS (SImode, (MEM_ALIGN (operands[0]) > 32
3508 ? 32 : MEM_ALIGN (operands[0])))
3509 || SLOW_UNALIGNED_ACCESS (SImode, (MEM_ALIGN (operands[1]) > 32
f676971a 3510 ? 32
41543739
GK		 3511 : MEM_ALIGN (operands[1]))))
3512 && ! MEM_VOLATILE_P (operands [0])
3513 && ! MEM_VOLATILE_P (operands [1]))
c9e8cb32 3514 {
41543739
GK		 3515 emit_move_insn (adjust_address (operands[0], SImode, 0),
3516 adjust_address (operands[1], SImode, 0));
3517 emit_move_insn (adjust_address (operands[0], SImode, 4),
3518 adjust_address (operands[1], SImode, 4));
c9e8cb32
DD		 3519 return;
3520 }
630d42a0 3521
55aa0757 3522 if (!no_new_pseudos && GET_CODE (operands[0]) == MEM
c9dbf840 3523 && !gpc_reg_operand (operands[1], mode))
f6219a5e 3524 operands[1] = force_reg (mode, operands[1]);
a9098fd0 3525
a3170dc6
AH		 3526 if (mode == SFmode && ! TARGET_POWERPC
3527 && TARGET_HARD_FLOAT && TARGET_FPRS
ffc14f31 3528 && GET_CODE (operands[0]) == MEM)
fb4d4348 3529 {
ffc14f31
GK		 3530 int regnum;
3531
3532 if (reload_in_progress || reload_completed)
3533 regnum = true_regnum (operands[1]);
3534 else if (GET_CODE (operands[1]) == REG)
3535 regnum = REGNO (operands[1]);
3536 else
3537 regnum = -1;
f676971a 3538
fb4d4348
GK		 3539 /* If operands[1] is a register, on POWER it may have
3540 double-precision data in it, so truncate it to single
3541 precision. */
3542 if (FP_REGNO_P (regnum) || regnum >= FIRST_PSEUDO_REGISTER)
3543 {
3544 rtx newreg;
3545 newreg = (no_new_pseudos ? operands[1] : gen_reg_rtx (mode));
3546 emit_insn (gen_aux_truncdfsf2 (newreg, operands[1]));
3547 operands[1] = newreg;
3548 }
3549 }
3550
c4501e62
JJ		 3551 /* Recognize the case where operand[1] is a reference to thread-local
3552 data and load its address to a register. */
3553 if (GET_CODE (operands[1]) == SYMBOL_REF)
3554 {
3555 enum tls_model model = SYMBOL_REF_TLS_MODEL (operands[1]);
3556 if (model != 0)
3557 operands[1] = rs6000_legitimize_tls_address (operands[1], model);
3558 }
3559
8f4e6caf
RH		 3560 /* Handle the case where reload calls us with an invalid address. */
3561 if (reload_in_progress && mode == Pmode
69ef87e2 3562 && (! general_operand (operands[1], mode)
8f4e6caf
RH		 3563 || ! nonimmediate_operand (operands[0], mode)))
3564 goto emit_set;
3565
a9baceb1
GK		 3566 /* 128-bit constant floating-point values on Darwin should really be
3567 loaded as two parts. */
3568 if ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
3569 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128
3570 && mode == TFmode && GET_CODE (operands[1]) == CONST_DOUBLE)
3571 {
3572 /* DImode is used, not DFmode, because simplify_gen_subreg doesn't
3573 know how to get a DFmode SUBREG of a TFmode. */
3574 rs6000_emit_move (simplify_gen_subreg (DImode, operands[0], mode, 0),
3575 simplify_gen_subreg (DImode, operands[1], mode, 0),
3576 DImode);
3577 rs6000_emit_move (simplify_gen_subreg (DImode, operands[0], mode,
3578 GET_MODE_SIZE (DImode)),
3579 simplify_gen_subreg (DImode, operands[1], mode,
3580 GET_MODE_SIZE (DImode)),
3581 DImode);
3582 return;
3583 }
3584
fb4d4348
GK		 3585 /* FIXME: In the long term, this switch statement should go away
3586 and be replaced by a sequence of tests based on things like
3587 mode == Pmode. */
3588 switch (mode)
3589 {
3590 case HImode:
3591 case QImode:
3592 if (CONSTANT_P (operands[1])
3593 && GET_CODE (operands[1]) != CONST_INT)
a9098fd0 3594 operands[1] = force_const_mem (mode, operands[1]);
fb4d4348
GK		 3595 break;
3596
06f4e019 3597 case TFmode:
76d2b81d
DJ		 3598 rs6000_eliminate_indexed_memrefs (operands);
3599 /* fall through */
3600
fb4d4348
GK		 3601 case DFmode:
3602 case SFmode:
f676971a 3603 if (CONSTANT_P (operands[1])
fb4d4348 3604 && ! easy_fp_constant (operands[1], mode))
a9098fd0 3605 operands[1] = force_const_mem (mode, operands[1]);
fb4d4348 3606 break;
f676971a 3607
0ac081f6
AH		 3608 case V16QImode:
3609 case V8HImode:
3610 case V4SFmode:
3611 case V4SImode:
a3170dc6
AH		 3612 case V4HImode:
3613 case V2SFmode:
3614 case V2SImode:
00a892b8 3615 case V1DImode:
69ef87e2 3616 if (CONSTANT_P (operands[1])
d744e06e 3617 && !easy_vector_constant (operands[1], mode))
0ac081f6
AH		 3618 operands[1] = force_const_mem (mode, operands[1]);
3619 break;
f676971a 3620
fb4d4348 3621 case SImode:
a9098fd0 3622 case DImode:
fb4d4348
GK		 3623 /* Use default pattern for address of ELF small data */
3624 if (TARGET_ELF
a9098fd0 3625 && mode == Pmode
f607bc57 3626 && DEFAULT_ABI == ABI_V4
f676971a 3627 && (GET_CODE (operands[1]) == SYMBOL_REF
a9098fd0
GK		 3628 || GET_CODE (operands[1]) == CONST)
3629 && small_data_operand (operands[1], mode))
fb4d4348
GK		 3630 {
3631 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
3632 return;
3633 }
3634
f607bc57 3635 if (DEFAULT_ABI == ABI_V4
a9098fd0
GK		 3636 && mode == Pmode && mode == SImode
3637 && flag_pic == 1 && got_operand (operands[1], mode))
fb4d4348
GK		 3638 {
3639 emit_insn (gen_movsi_got (operands[0], operands[1]));
3640 return;
3641 }
3642
ee890fe2 3643 if ((TARGET_ELF || DEFAULT_ABI == ABI_DARWIN)
f1384257
AM		 3644 && TARGET_NO_TOC
3645 && ! flag_pic
a9098fd0 3646 && mode == Pmode
fb4d4348
GK		 3647 && CONSTANT_P (operands[1])
3648 && GET_CODE (operands[1]) != HIGH
3649 && GET_CODE (operands[1]) != CONST_INT)
3650 {
a9098fd0 3651 rtx target = (no_new_pseudos ? operands[0] : gen_reg_rtx (mode));
fb4d4348
GK		 3652
3653 /* If this is a function address on -mcall-aixdesc,
3654 convert it to the address of the descriptor. */
3655 if (DEFAULT_ABI == ABI_AIX
3656 && GET_CODE (operands[1]) == SYMBOL_REF
3657 && XSTR (operands[1], 0)[0] == '.')
3658 {
3659 const char *name = XSTR (operands[1], 0);
3660 rtx new_ref;
3661 while (*name == '.')
3662 name++;
3663 new_ref = gen_rtx_SYMBOL_REF (Pmode, name);
3664 CONSTANT_POOL_ADDRESS_P (new_ref)
3665 = CONSTANT_POOL_ADDRESS_P (operands[1]);
d1908feb 3666 SYMBOL_REF_FLAGS (new_ref) = SYMBOL_REF_FLAGS (operands[1]);
fb4d4348 3667 SYMBOL_REF_USED (new_ref) = SYMBOL_REF_USED (operands[1]);
d1908feb 3668 SYMBOL_REF_DECL (new_ref) = SYMBOL_REF_DECL (operands[1]);
fb4d4348
GK		 3669 operands[1] = new_ref;
3670 }
7509c759 3671
ee890fe2
SS		 3672 if (DEFAULT_ABI == ABI_DARWIN)
3673 {
ab82a49f
AP		 3674#if TARGET_MACHO
3675 if (MACHO_DYNAMIC_NO_PIC_P)
3676 {
3677 /* Take care of any required data indirection. */
3678 operands[1] = rs6000_machopic_legitimize_pic_address (
3679 operands[1], mode, operands[0]);
3680 if (operands[0] != operands[1])
3681 emit_insn (gen_rtx_SET (VOIDmode,
c4ad648e 3682 operands[0], operands[1]));
ab82a49f
AP		 3683 return;
3684 }
3685#endif
b8a55285
AP		 3686 emit_insn (gen_macho_high (target, operands[1]));
3687 emit_insn (gen_macho_low (operands[0], target, operands[1]));
ee890fe2
SS		 3688 return;
3689 }
3690
fb4d4348
GK		 3691 emit_insn (gen_elf_high (target, operands[1]));
3692 emit_insn (gen_elf_low (operands[0], target, operands[1]));
3693 return;
3694 }
3695
a9098fd0
GK		 3696 /* If this is a SYMBOL_REF that refers to a constant pool entry,
3697 and we have put it in the TOC, we just need to make a TOC-relative
3698 reference to it. */
3699 if (TARGET_TOC
3700 && GET_CODE (operands[1]) == SYMBOL_REF
4d588c14 3701 && constant_pool_expr_p (operands[1])
a9098fd0
GK		 3702 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (operands[1]),
3703 get_pool_mode (operands[1])))
fb4d4348 3704 {
a9098fd0 3705 operands[1] = create_TOC_reference (operands[1]);
fb4d4348 3706 }
a9098fd0
GK		 3707 else if (mode == Pmode
3708 && CONSTANT_P (operands[1])
38886f37
AO		 3709 && ((GET_CODE (operands[1]) != CONST_INT
3710 && ! easy_fp_constant (operands[1], mode))
3711 || (GET_CODE (operands[1]) == CONST_INT
3712 && num_insns_constant (operands[1], mode) > 2)
3713 || (GET_CODE (operands[0]) == REG
3714 && FP_REGNO_P (REGNO (operands[0]))))
a9098fd0 3715 && GET_CODE (operands[1]) != HIGH
4d588c14
RH		 3716 && ! legitimate_constant_pool_address_p (operands[1])
3717 && ! toc_relative_expr_p (operands[1]))
fb4d4348
GK		 3718 {
3719 /* Emit a USE operation so that the constant isn't deleted if
3720 expensive optimizations are turned on because nobody
3721 references it. This should only be done for operands that
3722 contain SYMBOL_REFs with CONSTANT_POOL_ADDRESS_P set.
3723 This should not be done for operands that contain LABEL_REFs.
3724 For now, we just handle the obvious case. */
3725 if (GET_CODE (operands[1]) != LABEL_REF)
3726 emit_insn (gen_rtx_USE (VOIDmode, operands[1]));
3727
c859cda6 3728#if TARGET_MACHO
ee890fe2 3729 /* Darwin uses a special PIC legitimizer. */
ab82a49f 3730 if (DEFAULT_ABI == ABI_DARWIN && MACHOPIC_INDIRECT)
ee890fe2 3731 {
ee890fe2
SS		 3732 operands[1] =
3733 rs6000_machopic_legitimize_pic_address (operands[1], mode,
c859cda6
DJ		 3734 operands[0]);
3735 if (operands[0] != operands[1])
3736 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
ee890fe2
SS		 3737 return;
3738 }
c859cda6 3739#endif
ee890fe2 3740
fb4d4348
GK		 3741 /* If we are to limit the number of things we put in the TOC and
3742 this is a symbol plus a constant we can add in one insn,
3743 just put the symbol in the TOC and add the constant. Don't do
3744 this if reload is in progress. */
3745 if (GET_CODE (operands[1]) == CONST
3746 && TARGET_NO_SUM_IN_TOC && ! reload_in_progress
3747 && GET_CODE (XEXP (operands[1], 0)) == PLUS
a9098fd0 3748 && add_operand (XEXP (XEXP (operands[1], 0), 1), mode)
fb4d4348
GK		 3749 && (GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == LABEL_REF
3750 || GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == SYMBOL_REF)
3751 && ! side_effects_p (operands[0]))
3752 {
a4f6c312
SS		 3753 rtx sym =
3754 force_const_mem (mode, XEXP (XEXP (operands[1], 0), 0));
fb4d4348
GK		 3755 rtx other = XEXP (XEXP (operands[1], 0), 1);
3756
a9098fd0
GK		 3757 sym = force_reg (mode, sym);
3758 if (mode == SImode)
3759 emit_insn (gen_addsi3 (operands[0], sym, other));
3760 else
3761 emit_insn (gen_adddi3 (operands[0], sym, other));
fb4d4348
GK		 3762 return;
3763 }
3764
a9098fd0 3765 operands[1] = force_const_mem (mode, operands[1]);
fb4d4348 3766
f676971a 3767 if (TARGET_TOC
4d588c14 3768 && constant_pool_expr_p (XEXP (operands[1], 0))
d34c5b80
DE		 3769 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (
3770 get_pool_constant (XEXP (operands[1], 0)),
3771 get_pool_mode (XEXP (operands[1], 0))))
a9098fd0 3772 {
ba4828e0 3773 operands[1]
542a8afa 3774 = gen_const_mem (mode,
c4ad648e 3775 create_TOC_reference (XEXP (operands[1], 0)));
ba4828e0 3776 set_mem_alias_set (operands[1], get_TOC_alias_set ());
a9098fd0 3777 }
fb4d4348
GK		 3778 }
3779 break;
a9098fd0 3780
fb4d4348 3781 case TImode:
76d2b81d
DJ		 3782 rs6000_eliminate_indexed_memrefs (operands);
3783
27dc0551
DE		 3784 if (TARGET_POWER)
3785 {
3786 emit_insn (gen_rtx_PARALLEL (VOIDmode,
3787 gen_rtvec (2,
3788 gen_rtx_SET (VOIDmode,
3789 operands[0], operands[1]),
3790 gen_rtx_CLOBBER (VOIDmode,
3791 gen_rtx_SCRATCH (SImode)))));
3792 return;
3793 }
fb4d4348
GK		 3794 break;
3795
3796 default:
3797 abort ();
3798 }
3799
a9098fd0
GK		 3800 /* Above, we may have called force_const_mem which may have returned
3801 an invalid address. If we can, fix this up; otherwise, reload will
3802 have to deal with it. */
8f4e6caf
RH		 3803 if (GET_CODE (operands[1]) == MEM && ! reload_in_progress)
3804 operands[1] = validize_mem (operands[1]);
a9098fd0 3805
8f4e6caf 3806 emit_set:
fb4d4348
GK		 3807 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
3808}
4697a36c 3809\f
2858f73a
GK		 3810/* Nonzero if we can use a floating-point register to pass this arg. */
3811#define USE_FP_FOR_ARG_P(CUM,MODE,TYPE) \
3812 (GET_MODE_CLASS (MODE) == MODE_FLOAT \
3813 && (CUM)->fregno <= FP_ARG_MAX_REG \
3814 && TARGET_HARD_FLOAT && TARGET_FPRS)
3815
3816/* Nonzero if we can use an AltiVec register to pass this arg. */
3817#define USE_ALTIVEC_FOR_ARG_P(CUM,MODE,TYPE,NAMED) \
3818 (ALTIVEC_VECTOR_MODE (MODE) \
3819 && (CUM)->vregno <= ALTIVEC_ARG_MAX_REG \
3820 && TARGET_ALTIVEC_ABI \
83953138 3821 && (NAMED))
2858f73a 3822
c6e8c921
GK		 3823/* Return a nonzero value to say to return the function value in
3824 memory, just as large structures are always returned. TYPE will be
3825 the data type of the value, and FNTYPE will be the type of the
3826 function doing the returning, or @code{NULL} for libcalls.
3827
3828 The AIX ABI for the RS/6000 specifies that all structures are
3829 returned in memory. The Darwin ABI does the same. The SVR4 ABI
3830 specifies that structures <= 8 bytes are returned in r3/r4, but a
3831 draft put them in memory, and GCC used to implement the draft
3832 instead of the final standard. Therefore, TARGET_AIX_STRUCT_RET
3833 controls this instead of DEFAULT_ABI; V.4 targets needing backward
3834 compatibility can change DRAFT_V4_STRUCT_RET to override the
3835 default, and -m switches get the final word. See
3836 rs6000_override_options for more details.
3837
3838 The PPC32 SVR4 ABI uses IEEE double extended for long double, if 128-bit
3839 long double support is enabled. These values are returned in memory.
3840
3841 int_size_in_bytes returns -1 for variable size objects, which go in
3842 memory always. The cast to unsigned makes -1 > 8. */
3843
3844static bool
3845rs6000_return_in_memory (tree type, tree fntype ATTRIBUTE_UNUSED)
3846{
594a51fe
SS		 3847 /* In the darwin64 abi, try to use registers for larger structs
3848 if possible. */
0b5383eb 3849 if (rs6000_darwin64_abi
594a51fe 3850 && TREE_CODE (type) == RECORD_TYPE
0b5383eb
DJ		 3851 && int_size_in_bytes (type) > 0)
3852 {
3853 CUMULATIVE_ARGS valcum;
3854 rtx valret;
3855
3856 valcum.words = 0;
3857 valcum.fregno = FP_ARG_MIN_REG;
3858 valcum.vregno = ALTIVEC_ARG_MIN_REG;
3859 /* Do a trial code generation as if this were going to be passed
3860 as an argument; if any part goes in memory, we return NULL. */
3861 valret = rs6000_darwin64_record_arg (&valcum, type, 1, true);
3862 if (valret)
3863 return false;
3864 /* Otherwise fall through to more conventional ABI rules. */
3865 }
594a51fe 3866
c6e8c921
GK		 3867 if (AGGREGATE_TYPE_P (type)
3868 && (TARGET_AIX_STRUCT_RET
3869 || (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 8))
3870 return true;
b693336b 3871
bada2eb8
DE		 3872 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
3873 modes only exist for GCC vector types if -maltivec. */
3874 if (TARGET_32BIT && !TARGET_ALTIVEC_ABI
3875 && ALTIVEC_VECTOR_MODE (TYPE_MODE (type)))
3876 return false;
3877
b693336b
PB		 3878 /* Return synthetic vectors in memory. */
3879 if (TREE_CODE (type) == VECTOR_TYPE
ad630bef 3880 && int_size_in_bytes (type) > (TARGET_ALTIVEC_ABI ? 16 : 8))
b693336b
PB		 3881 {
3882 static bool warned_for_return_big_vectors = false;
3883 if (!warned_for_return_big_vectors)
3884 {
bada2eb8 3885 warning ("GCC vector returned by reference: "
b693336b
PB		 3886 "non-standard ABI extension with no compatibility guarantee");
3887 warned_for_return_big_vectors = true;
3888 }
3889 return true;
3890 }
3891
c6e8c921
GK		 3892 if (DEFAULT_ABI == ABI_V4 && TYPE_MODE (type) == TFmode)
3893 return true;
ad630bef 3894
c6e8c921
GK		 3895 return false;
3896}
3897
4697a36c
MM		 3898/* Initialize a variable CUM of type CUMULATIVE_ARGS
3899 for a call to a function whose data type is FNTYPE.
3900 For a library call, FNTYPE is 0.
3901
3902 For incoming args we set the number of arguments in the prototype large
1c20ae99 3903 so we never return a PARALLEL. */
4697a36c
MM		 3904
3905void
f676971a 3906init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype,
0f6937fe
AM		 3907 rtx libname ATTRIBUTE_UNUSED, int incoming,
3908 int libcall, int n_named_args)
4697a36c
MM		 3909{
3910 static CUMULATIVE_ARGS zero_cumulative;
3911
3912 *cum = zero_cumulative;
3913 cum->words = 0;
3914 cum->fregno = FP_ARG_MIN_REG;
0ac081f6 3915 cum->vregno = ALTIVEC_ARG_MIN_REG;
4697a36c 3916 cum->prototype = (fntype && TYPE_ARG_TYPES (fntype));
ddcc8263
DE		 3917 cum->call_cookie = ((DEFAULT_ABI == ABI_V4 && libcall)
3918 ? CALL_LIBCALL : CALL_NORMAL);
4cc833b7 3919 cum->sysv_gregno = GP_ARG_MIN_REG;
a6c9bed4
AH		 3920 cum->stdarg = fntype
3921 && (TYPE_ARG_TYPES (fntype) != 0
3922 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype)))
3923 != void_type_node));
4697a36c 3924
0f6937fe
AM		 3925 cum->nargs_prototype = 0;
3926 if (incoming || cum->prototype)
3927 cum->nargs_prototype = n_named_args;
4697a36c 3928
a5c76ee6 3929 /* Check for a longcall attribute. */
3eb4e360
AM		 3930 if ((!fntype && rs6000_default_long_calls)
3931 || (fntype
3932 && lookup_attribute ("longcall", TYPE_ATTRIBUTES (fntype))
3933 && !lookup_attribute ("shortcall", TYPE_ATTRIBUTES (fntype))))
3934 cum->call_cookie |= CALL_LONG;
6a4cee5f 3935
4697a36c
MM		 3936 if (TARGET_DEBUG_ARG)
3937 {
3938 fprintf (stderr, "\ninit_cumulative_args:");
3939 if (fntype)
3940 {
3941 tree ret_type = TREE_TYPE (fntype);
3942 fprintf (stderr, " ret code = %s,",
3943 tree_code_name[ (int)TREE_CODE (ret_type) ]);
3944 }
3945
6a4cee5f
MM		 3946 if (cum->call_cookie & CALL_LONG)
3947 fprintf (stderr, " longcall,");
3948
4697a36c
MM		 3949 fprintf (stderr, " proto = %d, nargs = %d\n",
3950 cum->prototype, cum->nargs_prototype);
3951 }
f676971a 3952
c4ad648e
AM		 3953 if (fntype
3954 && !TARGET_ALTIVEC
3955 && TARGET_ALTIVEC_ABI
3956 && ALTIVEC_VECTOR_MODE (TYPE_MODE (TREE_TYPE (fntype))))
3957 {
3958 error ("Cannot return value in vector register because"
3959 " altivec instructions are disabled, use -maltivec"
3960 " to enable them.");
3961 }
4697a36c
MM		 3962}
3963\f
fe984136
RH		 3964/* Return true if TYPE must be passed on the stack and not in registers. */
3965
3966static bool
3967rs6000_must_pass_in_stack (enum machine_mode mode, tree type)
3968{
3969 if (DEFAULT_ABI == ABI_AIX || TARGET_64BIT)
3970 return must_pass_in_stack_var_size (mode, type);
3971 else
3972 return must_pass_in_stack_var_size_or_pad (mode, type);
3973}
3974
c229cba9
DE		 3975/* If defined, a C expression which determines whether, and in which
3976 direction, to pad out an argument with extra space. The value
3977 should be of type `enum direction': either `upward' to pad above
3978 the argument, `downward' to pad below, or `none' to inhibit
3979 padding.
3980
3981 For the AIX ABI structs are always stored left shifted in their
3982 argument slot. */
3983
9ebbca7d 3984enum direction
a2369ed3 3985function_arg_padding (enum machine_mode mode, tree type)
c229cba9 3986{
6e985040
AM		 3987#ifndef AGGREGATE_PADDING_FIXED
3988#define AGGREGATE_PADDING_FIXED 0
3989#endif
3990#ifndef AGGREGATES_PAD_UPWARD_ALWAYS
3991#define AGGREGATES_PAD_UPWARD_ALWAYS 0
3992#endif
3993
3994 if (!AGGREGATE_PADDING_FIXED)
3995 {
3996 /* GCC used to pass structures of the same size as integer types as
3997 if they were in fact integers, ignoring FUNCTION_ARG_PADDING.
19525b57 3998 i.e. Structures of size 1 or 2 (or 4 when TARGET_64BIT) were
6e985040
AM		 3999 passed padded downward, except that -mstrict-align further
4000 muddied the water in that multi-component structures of 2 and 4
4001 bytes in size were passed padded upward.
4002
4003 The following arranges for best compatibility with previous
4004 versions of gcc, but removes the -mstrict-align dependency. */
4005 if (BYTES_BIG_ENDIAN)
4006 {
4007 HOST_WIDE_INT size = 0;
4008
4009 if (mode == BLKmode)
4010 {
4011 if (type && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST)
4012 size = int_size_in_bytes (type);
4013 }
4014 else
4015 size = GET_MODE_SIZE (mode);
4016
4017 if (size == 1 || size == 2 || size == 4)
4018 return downward;
4019 }
4020 return upward;
4021 }
4022
4023 if (AGGREGATES_PAD_UPWARD_ALWAYS)
4024 {
4025 if (type != 0 && AGGREGATE_TYPE_P (type))
4026 return upward;
4027 }
c229cba9 4028
d3704c46
KH		 4029 /* Fall back to the default. */
4030 return DEFAULT_FUNCTION_ARG_PADDING (mode, type);
c229cba9
DE		 4031}
4032
b6c9286a 4033/* If defined, a C expression that gives the alignment boundary, in bits,
f676971a 4034 of an argument with the specified mode and type. If it is not defined,
b6c9286a 4035 PARM_BOUNDARY is used for all arguments.
f676971a 4036
b693336b
PB		 4037 V.4 wants long longs to be double word aligned.
4038 Doubleword align SPE vectors.
4039 Quadword align Altivec vectors.
4040 Quadword align large synthetic vector types. */
b6c9286a
MM		 4041
4042int
b693336b 4043function_arg_boundary (enum machine_mode mode, tree type)
b6c9286a 4044{
4ed78545
AM		 4045 if (DEFAULT_ABI == ABI_V4 && GET_MODE_SIZE (mode) == 8)
4046 return 64;
ad630bef
DE		 4047 else if (SPE_VECTOR_MODE (mode)
4048 || (type && TREE_CODE (type) == VECTOR_TYPE
4049 && int_size_in_bytes (type) >= 8
4050 && int_size_in_bytes (type) < 16))
e1f83b4d 4051 return 64;
ad630bef
DE		 4052 else if (ALTIVEC_VECTOR_MODE (mode)
4053 || (type && TREE_CODE (type) == VECTOR_TYPE
4054 && int_size_in_bytes (type) >= 16))
0ac081f6 4055 return 128;
0b5383eb
DJ		 4056 else if (rs6000_darwin64_abi && mode == BLKmode
4057 && type && TYPE_ALIGN (type) > 64)
4058 return 128;
9ebbca7d 4059 else
b6c9286a 4060 return PARM_BOUNDARY;
b6c9286a 4061}
c53bdcf5
AM		 4062
4063/* Compute the size (in words) of a function argument. */
4064
4065static unsigned long
4066rs6000_arg_size (enum machine_mode mode, tree type)
4067{
4068 unsigned long size;
4069
4070 if (mode != BLKmode)
4071 size = GET_MODE_SIZE (mode);
4072 else
4073 size = int_size_in_bytes (type);
4074
4075 if (TARGET_32BIT)
4076 return (size + 3) >> 2;
4077 else
4078 return (size + 7) >> 3;
4079}
b6c9286a 4080\f
0b5383eb 4081/* Use this to flush pending int fields. */
594a51fe
SS		 4082
4083static void
0b5383eb
DJ		 4084rs6000_darwin64_record_arg_advance_flush (CUMULATIVE_ARGS *cum,
4085 HOST_WIDE_INT bitpos)
594a51fe 4086{
0b5383eb
DJ		 4087 unsigned int startbit, endbit;
4088 int intregs, intoffset;
4089 enum machine_mode mode;
594a51fe 4090
0b5383eb
DJ		 4091 if (cum->intoffset == -1)
4092 return;
594a51fe 4093
0b5383eb
DJ		 4094 intoffset = cum->intoffset;
4095 cum->intoffset = -1;
4096
4097 if (intoffset % BITS_PER_WORD != 0)
4098 {
4099 mode = mode_for_size (BITS_PER_WORD - intoffset % BITS_PER_WORD,
4100 MODE_INT, 0);
4101 if (mode == BLKmode)
594a51fe 4102 {
0b5383eb
DJ		 4103 /* We couldn't find an appropriate mode, which happens,
4104 e.g., in packed structs when there are 3 bytes to load.
4105 Back intoffset back to the beginning of the word in this
4106 case. */
4107 intoffset = intoffset & -BITS_PER_WORD;
594a51fe 4108 }
594a51fe 4109 }
0b5383eb
DJ		 4110
4111 startbit = intoffset & -BITS_PER_WORD;
4112 endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD;
4113 intregs = (endbit - startbit) / BITS_PER_WORD;
4114 cum->words += intregs;
4115}
4116
4117/* The darwin64 ABI calls for us to recurse down through structs,
4118 looking for elements passed in registers. Unfortunately, we have
4119 to track int register count here also because of misalignments
4120 in powerpc alignment mode. */
4121
4122static void
4123rs6000_darwin64_record_arg_advance_recurse (CUMULATIVE_ARGS *cum,
4124 tree type,
4125 HOST_WIDE_INT startbitpos)
4126{
4127 tree f;
4128
4129 for (f = TYPE_FIELDS (type); f ; f = TREE_CHAIN (f))
4130 if (TREE_CODE (f) == FIELD_DECL)
4131 {
4132 HOST_WIDE_INT bitpos = startbitpos;
4133 tree ftype = TREE_TYPE (f);
4134 enum machine_mode mode = TYPE_MODE (ftype);
4135
4136 if (DECL_SIZE (f) != 0
4137 && host_integerp (bit_position (f), 1))
4138 bitpos += int_bit_position (f);
4139
4140 /* ??? FIXME: else assume zero offset. */
4141
4142 if (TREE_CODE (ftype) == RECORD_TYPE)
4143 rs6000_darwin64_record_arg_advance_recurse (cum, ftype, bitpos);
4144 else if (USE_FP_FOR_ARG_P (cum, mode, ftype))
4145 {
4146 rs6000_darwin64_record_arg_advance_flush (cum, bitpos);
4147 cum->fregno += (GET_MODE_SIZE (mode) + 7) >> 3;
4148 cum->words += (GET_MODE_SIZE (mode) + 7) >> 3;
4149 }
4150 else if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, 1))
4151 {
4152 rs6000_darwin64_record_arg_advance_flush (cum, bitpos);
4153 cum->vregno++;
4154 cum->words += 2;
4155 }
4156 else if (cum->intoffset == -1)
4157 cum->intoffset = bitpos;
4158 }
594a51fe
SS		 4159}
4160
4697a36c
MM		 4161/* Update the data in CUM to advance over an argument
4162 of mode MODE and data type TYPE.
b2d04ecf
AM		 4163 (TYPE is null for libcalls where that information may not be available.)
4164
4165 Note that for args passed by reference, function_arg will be called
4166 with MODE and TYPE set to that of the pointer to the arg, not the arg
4167 itself. */
4697a36c
MM		 4168
4169void
f676971a 4170function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
594a51fe 4171 tree type, int named, int depth)
4697a36c 4172{
0b5383eb
DJ		 4173 int size;
4174
594a51fe
SS		 4175 /* Only tick off an argument if we're not recursing. */
4176 if (depth == 0)
4177 cum->nargs_prototype--;
4697a36c 4178
ad630bef
DE		 4179 if (TARGET_ALTIVEC_ABI
4180 && (ALTIVEC_VECTOR_MODE (mode)
4181 || (type && TREE_CODE (type) == VECTOR_TYPE
4182 && int_size_in_bytes (type) == 16)))
0ac081f6 4183 {
4ed78545
AM		 4184 bool stack = false;
4185
2858f73a 4186 if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named))
c4ad648e 4187 {
6d0ef01e
HP		 4188 cum->vregno++;
4189 if (!TARGET_ALTIVEC)
4190 error ("Cannot pass argument in vector register because"
4191 " altivec instructions are disabled, use -maltivec"
4192 " to enable them.");
4ed78545
AM		 4193
4194 /* PowerPC64 Linux and AIX allocate GPRs for a vector argument
f676971a 4195 even if it is going to be passed in a vector register.
4ed78545
AM		 4196 Darwin does the same for variable-argument functions. */
4197 if ((DEFAULT_ABI == ABI_AIX && TARGET_64BIT)
4198 || (cum->stdarg && DEFAULT_ABI != ABI_V4))
4199 stack = true;
6d0ef01e 4200 }
4ed78545
AM		 4201 else
4202 stack = true;
4203
4204 if (stack)
c4ad648e 4205 {
a594a19c 4206 int align;
f676971a 4207
2858f73a
GK		 4208 /* Vector parameters must be 16-byte aligned. This places
4209 them at 2 mod 4 in terms of words in 32-bit mode, since
4210 the parameter save area starts at offset 24 from the
4211 stack. In 64-bit mode, they just have to start on an
4212 even word, since the parameter save area is 16-byte
4213 aligned. Space for GPRs is reserved even if the argument
4214 will be passed in memory. */
4215 if (TARGET_32BIT)
4ed78545 4216 align = (2 - cum->words) & 3;
2858f73a
GK		 4217 else
4218 align = cum->words & 1;
c53bdcf5 4219 cum->words += align + rs6000_arg_size (mode, type);
f676971a 4220
a594a19c
GK		 4221 if (TARGET_DEBUG_ARG)
4222 {
f676971a 4223 fprintf (stderr, "function_adv: words = %2d, align=%d, ",
a594a19c
GK		 4224 cum->words, align);
4225 fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s\n",
f676971a 4226 cum->nargs_prototype, cum->prototype,
2858f73a 4227 GET_MODE_NAME (mode));
a594a19c
GK		 4228 }
4229 }
0ac081f6 4230 }
a4b0320c 4231 else if (TARGET_SPE_ABI && TARGET_SPE && SPE_VECTOR_MODE (mode)
a6c9bed4
AH		 4232 && !cum->stdarg
4233 && cum->sysv_gregno <= GP_ARG_MAX_REG)
a4b0320c 4234 cum->sysv_gregno++;
594a51fe
SS		 4235
4236 else if (rs6000_darwin64_abi
4237 && mode == BLKmode
0b5383eb
DJ		 4238 && TREE_CODE (type) == RECORD_TYPE
4239 && (size = int_size_in_bytes (type)) > 0)
4240 {
4241 /* Variable sized types have size == -1 and are
4242 treated as if consisting entirely of ints.
4243 Pad to 16 byte boundary if needed. */
4244 if (TYPE_ALIGN (type) >= 2 * BITS_PER_WORD
4245 && (cum->words % 2) != 0)
4246 cum->words++;
4247 /* For varargs, we can just go up by the size of the struct. */
4248 if (!named)
4249 cum->words += (size + 7) / 8;
4250 else
4251 {
4252 /* It is tempting to say int register count just goes up by
4253 sizeof(type)/8, but this is wrong in a case such as
4254 { int; double; int; } [powerpc alignment]. We have to
4255 grovel through the fields for these too. */
4256 cum->intoffset = 0;
4257 rs6000_darwin64_record_arg_advance_recurse (cum, type, 0);
4258 rs6000_darwin64_record_arg_advance_flush (cum,
4259 size * BITS_PER_UNIT);
4260 }
4261 }
f607bc57 4262 else if (DEFAULT_ABI == ABI_V4)
4697a36c 4263 {
a3170dc6 4264 if (TARGET_HARD_FLOAT && TARGET_FPRS
4cc833b7 4265 && (mode == SFmode || mode == DFmode))
4697a36c 4266 {
4cc833b7
RH		 4267 if (cum->fregno <= FP_ARG_V4_MAX_REG)
4268 cum->fregno++;
4269 else
4270 {
4271 if (mode == DFmode)
c4ad648e 4272 cum->words += cum->words & 1;
c53bdcf5 4273 cum->words += rs6000_arg_size (mode, type);
4cc833b7 4274 }
4697a36c 4275 }
4cc833b7
RH		 4276 else
4277 {
b2d04ecf 4278 int n_words = rs6000_arg_size (mode, type);
4cc833b7
RH		 4279 int gregno = cum->sysv_gregno;
4280
4ed78545
AM		 4281 /* Long long and SPE vectors are put in (r3,r4), (r5,r6),
4282 (r7,r8) or (r9,r10). As does any other 2 word item such
4283 as complex int due to a historical mistake. */
4284 if (n_words == 2)
4285 gregno += (1 - gregno) & 1;
4cc833b7 4286
4ed78545 4287 /* Multi-reg args are not split between registers and stack. */
4cc833b7
RH		 4288 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
4289 {
4ed78545
AM		 4290 /* Long long and SPE vectors are aligned on the stack.
4291 So are other 2 word items such as complex int due to
4292 a historical mistake. */
4cc833b7
RH		 4293 if (n_words == 2)
4294 cum->words += cum->words & 1;
4295 cum->words += n_words;
4296 }
4697a36c 4297
4cc833b7
RH		 4298 /* Note: continuing to accumulate gregno past when we've started
4299 spilling to the stack indicates the fact that we've started
4300 spilling to the stack to expand_builtin_saveregs. */
4301 cum->sysv_gregno = gregno + n_words;
4302 }
4697a36c 4303
4cc833b7
RH		 4304 if (TARGET_DEBUG_ARG)
4305 {
4306 fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ",
4307 cum->words, cum->fregno);
4308 fprintf (stderr, "gregno = %2d, nargs = %4d, proto = %d, ",
4309 cum->sysv_gregno, cum->nargs_prototype, cum->prototype);
4310 fprintf (stderr, "mode = %4s, named = %d\n",
4311 GET_MODE_NAME (mode), named);
4312 }
4697a36c
MM		 4313 }
4314 else
4cc833b7 4315 {
b2d04ecf
AM		 4316 int n_words = rs6000_arg_size (mode, type);
4317 int align = function_arg_boundary (mode, type) / PARM_BOUNDARY - 1;
a4f6c312 4318
b2d04ecf
AM		 4319 /* The simple alignment calculation here works because
4320 function_arg_boundary / PARM_BOUNDARY will only be 1 or 2.
4321 If we ever want to handle alignments larger than 8 bytes for
4322 32-bit or 16 bytes for 64-bit, then we'll need to take into
4323 account the offset to the start of the parm save area. */
4324 align &= cum->words;
4325 cum->words += align + n_words;
4697a36c 4326
a3170dc6
AH		 4327 if (GET_MODE_CLASS (mode) == MODE_FLOAT
4328 && TARGET_HARD_FLOAT && TARGET_FPRS)
c53bdcf5 4329 cum->fregno += (GET_MODE_SIZE (mode) + 7) >> 3;
4cc833b7
RH		 4330
4331 if (TARGET_DEBUG_ARG)
4332 {
4333 fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ",
4334 cum->words, cum->fregno);
4335 fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s, ",
4336 cum->nargs_prototype, cum->prototype, GET_MODE_NAME (mode));
594a51fe
SS		 4337 fprintf (stderr, "named = %d, align = %d, depth = %d\n",
4338 named, align, depth);
4cc833b7
RH		 4339 }
4340 }
4697a36c 4341}
a6c9bed4 4342
f82f556d
AH		 4343static rtx
4344spe_build_register_parallel (enum machine_mode mode, int gregno)
4345{
54b695e7 4346 rtx r1, r3;
f82f556d
AH		 4347
4348 if (mode == DFmode)
4349 {
54b695e7
AH		 4350 r1 = gen_rtx_REG (DImode, gregno);
4351 r1 = gen_rtx_EXPR_LIST (VOIDmode, r1, const0_rtx);
4352 return gen_rtx_PARALLEL (mode, gen_rtvec (1, r1));
18f63bfa
AH		 4353 }
4354 else if (mode == DCmode)
4355 {
54b695e7
AH		 4356 r1 = gen_rtx_REG (DImode, gregno);
4357 r1 = gen_rtx_EXPR_LIST (VOIDmode, r1, const0_rtx);
4358 r3 = gen_rtx_REG (DImode, gregno + 2);
4359 r3 = gen_rtx_EXPR_LIST (VOIDmode, r3, GEN_INT (8));
4360 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r3));
f82f556d 4361 }
9390387d 4362 abort ();
18f63bfa 4363 return NULL_RTX;
f82f556d 4364}
b78d48dd 4365
f82f556d 4366/* Determine where to put a SIMD argument on the SPE. */
a6c9bed4 4367static rtx
f676971a 4368rs6000_spe_function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
a2369ed3 4369 tree type)
a6c9bed4 4370{
f82f556d
AH		 4371 int gregno = cum->sysv_gregno;
4372
4373 /* On E500 v2, double arithmetic is done on the full 64-bit GPR, but
600e1f95 4374 are passed and returned in a pair of GPRs for ABI compatibility. */
18f63bfa 4375 if (TARGET_E500_DOUBLE && (mode == DFmode || mode == DCmode))
f82f556d 4376 {
b5870bee
AH		 4377 int n_words = rs6000_arg_size (mode, type);
4378
f82f556d 4379 /* Doubles go in an odd/even register pair (r5/r6, etc). */
b5870bee
AH		 4380 if (mode == DFmode)
4381 gregno += (1 - gregno) & 1;
f82f556d 4382
b5870bee
AH		 4383 /* Multi-reg args are not split between registers and stack. */
4384 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
f82f556d
AH		 4385 return NULL_RTX;
4386
4387 return spe_build_register_parallel (mode, gregno);
4388 }
a6c9bed4
AH		 4389 if (cum->stdarg)
4390 {
c53bdcf5 4391 int n_words = rs6000_arg_size (mode, type);
a6c9bed4
AH		 4392
4393 /* SPE vectors are put in odd registers. */
4394 if (n_words == 2 && (gregno & 1) == 0)
4395 gregno += 1;
4396
4397 if (gregno + n_words - 1 <= GP_ARG_MAX_REG)
4398 {
4399 rtx r1, r2;
4400 enum machine_mode m = SImode;
4401
4402 r1 = gen_rtx_REG (m, gregno);
4403 r1 = gen_rtx_EXPR_LIST (m, r1, const0_rtx);
4404 r2 = gen_rtx_REG (m, gregno + 1);
4405 r2 = gen_rtx_EXPR_LIST (m, r2, GEN_INT (4));
4406 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r2));
4407 }
4408 else
b78d48dd 4409 return NULL_RTX;
a6c9bed4
AH		 4410 }
4411 else
4412 {
f82f556d
AH		 4413 if (gregno <= GP_ARG_MAX_REG)
4414 return gen_rtx_REG (mode, gregno);
a6c9bed4 4415 else
b78d48dd 4416 return NULL_RTX;
a6c9bed4
AH		 4417 }
4418}
4419
0b5383eb
DJ		 4420/* A subroutine of rs6000_darwin64_record_arg. Assign the bits of the
4421 structure between cum->intoffset and bitpos to integer registers. */
594a51fe 4422
0b5383eb
DJ		 4423static void
4424rs6000_darwin64_record_arg_flush (CUMULATIVE_ARGS *cum,
4425 HOST_WIDE_INT bitpos, rtx rvec[], int *k)
594a51fe 4426{
0b5383eb
DJ		 4427 enum machine_mode mode;
4428 unsigned int regno;
4429 unsigned int startbit, endbit;
4430 int this_regno, intregs, intoffset;
4431 rtx reg;
594a51fe 4432
0b5383eb
DJ		 4433 if (cum->intoffset == -1)
4434 return;
4435
4436 intoffset = cum->intoffset;
4437 cum->intoffset = -1;
4438
4439 /* If this is the trailing part of a word, try to only load that
4440 much into the register. Otherwise load the whole register. Note
4441 that in the latter case we may pick up unwanted bits. It's not a
4442 problem at the moment but may wish to revisit. */
4443
4444 if (intoffset % BITS_PER_WORD != 0)
594a51fe 4445 {
0b5383eb
DJ		 4446 mode = mode_for_size (BITS_PER_WORD - intoffset % BITS_PER_WORD,
4447 MODE_INT, 0);
4448 if (mode == BLKmode)
4449 {
4450 /* We couldn't find an appropriate mode, which happens,
4451 e.g., in packed structs when there are 3 bytes to load.
4452 Back intoffset back to the beginning of the word in this
4453 case. */
4454 intoffset = intoffset & -BITS_PER_WORD;
4455 mode = word_mode;
4456 }
4457 }
4458 else
4459 mode = word_mode;
4460
4461 startbit = intoffset & -BITS_PER_WORD;
4462 endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD;
4463 intregs = (endbit - startbit) / BITS_PER_WORD;
4464 this_regno = cum->words + intoffset / BITS_PER_WORD;
4465
4466 if (intregs > 0 && intregs > GP_ARG_NUM_REG - this_regno)
4467 cum->use_stack = 1;
4468
4469 intregs = MIN (intregs, GP_ARG_NUM_REG - this_regno);
4470 if (intregs <= 0)
4471 return;
4472
4473 intoffset /= BITS_PER_UNIT;
4474 do
4475 {
4476 regno = GP_ARG_MIN_REG + this_regno;
4477 reg = gen_rtx_REG (mode, regno);
4478 rvec[(*k)++] =
4479 gen_rtx_EXPR_LIST (VOIDmode, reg, GEN_INT (intoffset));
4480
4481 this_regno += 1;
4482 intoffset = (intoffset | (UNITS_PER_WORD-1)) + 1;
4483 mode = word_mode;
4484 intregs -= 1;
4485 }
4486 while (intregs > 0);
4487}
4488
4489/* Recursive workhorse for the following. */
4490
4491static void
4492rs6000_darwin64_record_arg_recurse (CUMULATIVE_ARGS *cum, tree type,
4493 HOST_WIDE_INT startbitpos, rtx rvec[],
4494 int *k)
4495{
4496 tree f;
4497
4498 for (f = TYPE_FIELDS (type); f ; f = TREE_CHAIN (f))
4499 if (TREE_CODE (f) == FIELD_DECL)
4500 {
4501 HOST_WIDE_INT bitpos = startbitpos;
4502 tree ftype = TREE_TYPE (f);
4503 enum machine_mode mode = TYPE_MODE (ftype);
4504
4505 if (DECL_SIZE (f) != 0
4506 && host_integerp (bit_position (f), 1))
4507 bitpos += int_bit_position (f);
4508
4509 /* ??? FIXME: else assume zero offset. */
4510
4511 if (TREE_CODE (ftype) == RECORD_TYPE)
4512 rs6000_darwin64_record_arg_recurse (cum, ftype, bitpos, rvec, k);
4513 else if (cum->named && USE_FP_FOR_ARG_P (cum, mode, ftype))
594a51fe 4514 {
0b5383eb
DJ		 4515#if 0
4516 switch (mode)
594a51fe 4517 {
0b5383eb
DJ		 4518 case SCmode: mode = SFmode; break;
4519 case DCmode: mode = DFmode; break;
4520 case TCmode: mode = TFmode; break;
4521 default: break;
594a51fe 4522 }
0b5383eb
DJ		 4523#endif
4524 rs6000_darwin64_record_arg_flush (cum, bitpos, rvec, k);
4525 rvec[(*k)++]
4526 = gen_rtx_EXPR_LIST (VOIDmode,
4527 gen_rtx_REG (mode, cum->fregno++),
4528 GEN_INT (bitpos / BITS_PER_UNIT));
4529 if (mode == TFmode)
4530 cum->fregno++;
594a51fe 4531 }
0b5383eb
DJ		 4532 else if (cum->named && USE_ALTIVEC_FOR_ARG_P (cum, mode, ftype, 1))
4533 {
4534 rs6000_darwin64_record_arg_flush (cum, bitpos, rvec, k);
4535 rvec[(*k)++]
4536 = gen_rtx_EXPR_LIST (VOIDmode,
4537 gen_rtx_REG (mode, cum->vregno++),
4538 GEN_INT (bitpos / BITS_PER_UNIT));
4539 }
4540 else if (cum->intoffset == -1)
4541 cum->intoffset = bitpos;
4542 }
4543}
594a51fe 4544
0b5383eb
DJ		 4545/* For the darwin64 ABI, we want to construct a PARALLEL consisting of
4546 the register(s) to be used for each field and subfield of a struct
4547 being passed by value, along with the offset of where the
4548 register's value may be found in the block. FP fields go in FP
4549 register, vector fields go in vector registers, and everything
4550 else goes in int registers, packed as in memory.
8ff40a74 4551
0b5383eb
DJ		 4552 This code is also used for function return values. RETVAL indicates
4553 whether this is the case.
8ff40a74 4554
0b5383eb
DJ		 4555 Much of this is taken from the Sparc V9 port, which has a similar
4556 calling convention. */
594a51fe 4557
0b5383eb
DJ		 4558static rtx
4559rs6000_darwin64_record_arg (CUMULATIVE_ARGS *orig_cum, tree type,
4560 int named, bool retval)
4561{
4562 rtx rvec[FIRST_PSEUDO_REGISTER];
4563 int k = 1, kbase = 1;
4564 HOST_WIDE_INT typesize = int_size_in_bytes (type);
4565 /* This is a copy; modifications are not visible to our caller. */
4566 CUMULATIVE_ARGS copy_cum = *orig_cum;
4567 CUMULATIVE_ARGS *cum = &copy_cum;
4568
4569 /* Pad to 16 byte boundary if needed. */
4570 if (!retval && TYPE_ALIGN (type) >= 2 * BITS_PER_WORD
4571 && (cum->words % 2) != 0)
4572 cum->words++;
4573
4574 cum->intoffset = 0;
4575 cum->use_stack = 0;
4576 cum->named = named;
4577
4578 /* Put entries into rvec[] for individual FP and vector fields, and
4579 for the chunks of memory that go in int regs. Note we start at
4580 element 1; 0 is reserved for an indication of using memory, and
4581 may or may not be filled in below. */
4582 rs6000_darwin64_record_arg_recurse (cum, type, 0, rvec, &k);
4583 rs6000_darwin64_record_arg_flush (cum, typesize * BITS_PER_UNIT, rvec, &k);
4584
4585 /* If any part of the struct went on the stack put all of it there.
4586 This hack is because the generic code for
4587 FUNCTION_ARG_PARTIAL_NREGS cannot handle cases where the register
4588 parts of the struct are not at the beginning. */
4589 if (cum->use_stack)
4590 {
4591 if (retval)
4592 return NULL_RTX; /* doesn't go in registers at all */
4593 kbase = 0;
4594 rvec[0] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
4595 }
4596 if (k > 1 || cum->use_stack)
4597 return gen_rtx_PARALLEL (BLKmode, gen_rtvec_v (k - kbase, &rvec[kbase]));
594a51fe
SS		 4598 else
4599 return NULL_RTX;
4600}
4601
b78d48dd
FJ		 4602/* Determine where to place an argument in 64-bit mode with 32-bit ABI. */
4603
4604static rtx
ec6376ab 4605rs6000_mixed_function_arg (enum machine_mode mode, tree type, int align_words)
b78d48dd 4606{
ec6376ab
AM		 4607 int n_units;
4608 int i, k;
4609 rtx rvec[GP_ARG_NUM_REG + 1];
4610
4611 if (align_words >= GP_ARG_NUM_REG)
4612 return NULL_RTX;
4613
4614 n_units = rs6000_arg_size (mode, type);
4615
4616 /* Optimize the simple case where the arg fits in one gpr, except in
4617 the case of BLKmode due to assign_parms assuming that registers are
4618 BITS_PER_WORD wide. */
4619 if (n_units == 0
4620 || (n_units == 1 && mode != BLKmode))
4621 return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
4622
4623 k = 0;
4624 if (align_words + n_units > GP_ARG_NUM_REG)
4625 /* Not all of the arg fits in gprs. Say that it goes in memory too,
4626 using a magic NULL_RTX component.
4627 FIXME: This is not strictly correct. Only some of the arg
4628 belongs in memory, not all of it. However, there isn't any way
4629 to do this currently, apart from building rtx descriptions for
4630 the pieces of memory we want stored. Due to bugs in the generic
4631 code we can't use the normal function_arg_partial_nregs scheme
4632 with the PARALLEL arg description we emit here.
4633 In any case, the code to store the whole arg to memory is often
4634 more efficient than code to store pieces, and we know that space
4635 is available in the right place for the whole arg. */
78a52f11
RH		 4636 /* FIXME: This should be fixed since the conversion to
4637 TARGET_ARG_PARTIAL_BYTES. */
ec6376ab
AM		 4638 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
4639
4640 i = 0;
4641 do
36a454e1 4642 {
ec6376ab
AM		 4643 rtx r = gen_rtx_REG (SImode, GP_ARG_MIN_REG + align_words);
4644 rtx off = GEN_INT (i++ * 4);
4645 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
36a454e1 4646 }
ec6376ab
AM		 4647 while (++align_words < GP_ARG_NUM_REG && --n_units != 0);
4648
4649 return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec));
b78d48dd
FJ		 4650}
4651
4697a36c
MM		 4652/* Determine where to put an argument to a function.
4653 Value is zero to push the argument on the stack,
4654 or a hard register in which to store the argument.
4655
4656 MODE is the argument's machine mode.
4657 TYPE is the data type of the argument (as a tree).
4658 This is null for libcalls where that information may
4659 not be available.
4660 CUM is a variable of type CUMULATIVE_ARGS which gives info about
0b5383eb
DJ		 4661 the preceding args and about the function being called. It is
4662 not modified in this routine.
4697a36c
MM		 4663 NAMED is nonzero if this argument is a named parameter
4664 (otherwise it is an extra parameter matching an ellipsis).
4665
4666 On RS/6000 the first eight words of non-FP are normally in registers
4667 and the rest are pushed. Under AIX, the first 13 FP args are in registers.
4668 Under V.4, the first 8 FP args are in registers.
4669
4670 If this is floating-point and no prototype is specified, we use
4671 both an FP and integer register (or possibly FP reg and stack). Library
b9599e46 4672 functions (when CALL_LIBCALL is set) always have the proper types for args,
4697a36c 4673 so we can pass the FP value just in one register. emit_library_function
b2d04ecf
AM		 4674 doesn't support PARALLEL anyway.
4675
4676 Note that for args passed by reference, function_arg will be called
4677 with MODE and TYPE set to that of the pointer to the arg, not the arg
4678 itself. */
4697a36c 4679
9390387d 4680rtx
f676971a 4681function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
a2369ed3 4682 tree type, int named)
4697a36c 4683{
4cc833b7 4684 enum rs6000_abi abi = DEFAULT_ABI;
4697a36c 4685
a4f6c312
SS		 4686 /* Return a marker to indicate whether CR1 needs to set or clear the
4687 bit that V.4 uses to say fp args were passed in registers.
4688 Assume that we don't need the marker for software floating point,
4689 or compiler generated library calls. */
4697a36c
MM		 4690 if (mode == VOIDmode)
4691 {
f607bc57 4692 if (abi == ABI_V4
7509c759 4693 && cum->nargs_prototype < 0
b9599e46
FS		 4694 && (cum->call_cookie & CALL_LIBCALL) == 0
4695 && (cum->prototype || TARGET_NO_PROTOTYPE))
7509c759 4696 {
a3170dc6
AH		 4697 /* For the SPE, we need to crxor CR6 always. */
4698 if (TARGET_SPE_ABI)
4699 return GEN_INT (cum->call_cookie | CALL_V4_SET_FP_ARGS);
4700 else if (TARGET_HARD_FLOAT && TARGET_FPRS)
4701 return GEN_INT (cum->call_cookie
4702 | ((cum->fregno == FP_ARG_MIN_REG)
4703 ? CALL_V4_SET_FP_ARGS
4704 : CALL_V4_CLEAR_FP_ARGS));
7509c759 4705 }
4697a36c 4706
7509c759 4707 return GEN_INT (cum->call_cookie);
4697a36c
MM		 4708 }
4709
0b5383eb
DJ		 4710 if (rs6000_darwin64_abi && mode == BLKmode
4711 && TREE_CODE (type) == RECORD_TYPE)
8ff40a74 4712 {
0b5383eb 4713 rtx rslt = rs6000_darwin64_record_arg (cum, type, named, false);
8ff40a74
SS		 4714 if (rslt != NULL_RTX)
4715 return rslt;
4716 /* Else fall through to usual handling. */
4717 }
4718
2858f73a 4719 if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named))
c72d6c26
HP		 4720 if (TARGET_64BIT && ! cum->prototype)
4721 {
c4ad648e
AM		 4722 /* Vector parameters get passed in vector register
4723 and also in GPRs or memory, in absence of prototype. */
4724 int align_words;
4725 rtx slot;
4726 align_words = (cum->words + 1) & ~1;
4727
4728 if (align_words >= GP_ARG_NUM_REG)
4729 {
4730 slot = NULL_RTX;
4731 }
4732 else
4733 {
4734 slot = gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
4735 }
4736 return gen_rtx_PARALLEL (mode,
4737 gen_rtvec (2,
4738 gen_rtx_EXPR_LIST (VOIDmode,
4739 slot, const0_rtx),
4740 gen_rtx_EXPR_LIST (VOIDmode,
4741 gen_rtx_REG (mode, cum->vregno),
4742 const0_rtx)));
c72d6c26
HP		 4743 }
4744 else
4745 return gen_rtx_REG (mode, cum->vregno);
ad630bef
DE		 4746 else if (TARGET_ALTIVEC_ABI
4747 && (ALTIVEC_VECTOR_MODE (mode)
4748 || (type && TREE_CODE (type) == VECTOR_TYPE
4749 && int_size_in_bytes (type) == 16)))
0ac081f6 4750 {
2858f73a 4751 if (named || abi == ABI_V4)
a594a19c 4752 return NULL_RTX;
0ac081f6 4753 else
a594a19c
GK		 4754 {
4755 /* Vector parameters to varargs functions under AIX or Darwin
4756 get passed in memory and possibly also in GPRs. */
ec6376ab
AM		 4757 int align, align_words, n_words;
4758 enum machine_mode part_mode;
a594a19c
GK		 4759
4760 /* Vector parameters must be 16-byte aligned. This places them at
2858f73a
GK		 4761 2 mod 4 in terms of words in 32-bit mode, since the parameter
4762 save area starts at offset 24 from the stack. In 64-bit mode,
4763 they just have to start on an even word, since the parameter
4764 save area is 16-byte aligned. */
4765 if (TARGET_32BIT)
4ed78545 4766 align = (2 - cum->words) & 3;
2858f73a
GK		 4767 else
4768 align = cum->words & 1;
a594a19c
GK		 4769 align_words = cum->words + align;
4770
4771 /* Out of registers? Memory, then. */
4772 if (align_words >= GP_ARG_NUM_REG)
4773 return NULL_RTX;
ec6376ab
AM		 4774
4775 if (TARGET_32BIT && TARGET_POWERPC64)
4776 return rs6000_mixed_function_arg (mode, type, align_words);
4777
2858f73a
GK		 4778 /* The vector value goes in GPRs. Only the part of the
4779 value in GPRs is reported here. */
ec6376ab
AM		 4780 part_mode = mode;
4781 n_words = rs6000_arg_size (mode, type);
4782 if (align_words + n_words > GP_ARG_NUM_REG)
839a4992 4783 /* Fortunately, there are only two possibilities, the value
2858f73a
GK		 4784 is either wholly in GPRs or half in GPRs and half not. */
4785 part_mode = DImode;
ec6376ab
AM		 4786
4787 return gen_rtx_REG (part_mode, GP_ARG_MIN_REG + align_words);
a594a19c 4788 }
0ac081f6 4789 }
f82f556d
AH		 4790 else if (TARGET_SPE_ABI && TARGET_SPE
4791 && (SPE_VECTOR_MODE (mode)
18f63bfa
AH		 4792 || (TARGET_E500_DOUBLE && (mode == DFmode
4793 || mode == DCmode))))
a6c9bed4 4794 return rs6000_spe_function_arg (cum, mode, type);
594a51fe 4795
f607bc57 4796 else if (abi == ABI_V4)
4697a36c 4797 {
a3170dc6 4798 if (TARGET_HARD_FLOAT && TARGET_FPRS
4cc833b7
RH		 4799 && (mode == SFmode || mode == DFmode))
4800 {
4801 if (cum->fregno <= FP_ARG_V4_MAX_REG)
4802 return gen_rtx_REG (mode, cum->fregno);
4803 else
b78d48dd 4804 return NULL_RTX;
4cc833b7
RH		 4805 }
4806 else
4807 {
b2d04ecf 4808 int n_words = rs6000_arg_size (mode, type);
4cc833b7
RH		 4809 int gregno = cum->sysv_gregno;
4810
4ed78545
AM		 4811 /* Long long and SPE vectors are put in (r3,r4), (r5,r6),
4812 (r7,r8) or (r9,r10). As does any other 2 word item such
4813 as complex int due to a historical mistake. */
4814 if (n_words == 2)
4815 gregno += (1 - gregno) & 1;
4cc833b7 4816
4ed78545 4817 /* Multi-reg args are not split between registers and stack. */
ec6376ab 4818 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
b78d48dd 4819 return NULL_RTX;
ec6376ab
AM		 4820
4821 if (TARGET_32BIT && TARGET_POWERPC64)
4822 return rs6000_mixed_function_arg (mode, type,
4823 gregno - GP_ARG_MIN_REG);
4824 return gen_rtx_REG (mode, gregno);
4cc833b7 4825 }
4697a36c 4826 }
4cc833b7
RH		 4827 else
4828 {
b2d04ecf
AM		 4829 int align = function_arg_boundary (mode, type) / PARM_BOUNDARY - 1;
4830 int align_words = cum->words + (cum->words & align);
b78d48dd 4831
2858f73a 4832 if (USE_FP_FOR_ARG_P (cum, mode, type))
4cc833b7 4833 {
ec6376ab
AM		 4834 rtx rvec[GP_ARG_NUM_REG + 1];
4835 rtx r;
4836 int k;
c53bdcf5
AM		 4837 bool needs_psave;
4838 enum machine_mode fmode = mode;
c53bdcf5
AM		 4839 unsigned long n_fpreg = (GET_MODE_SIZE (mode) + 7) >> 3;
4840
4841 if (cum->fregno + n_fpreg > FP_ARG_MAX_REG + 1)
4842 {
c53bdcf5
AM		 4843 /* Currently, we only ever need one reg here because complex
4844 doubles are split. */
ec6376ab 4845 if (cum->fregno != FP_ARG_MAX_REG || fmode != TFmode)
c53bdcf5 4846 abort ();
ec6376ab
AM		 4847
4848 /* Long double split over regs and memory. */
4849 fmode = DFmode;
c53bdcf5 4850 }
c53bdcf5
AM		 4851
4852 /* Do we also need to pass this arg in the parameter save
4853 area? */
4854 needs_psave = (type
4855 && (cum->nargs_prototype <= 0
4856 || (DEFAULT_ABI == ABI_AIX
de17c25f 4857 && TARGET_XL_COMPAT
c53bdcf5
AM		 4858 && align_words >= GP_ARG_NUM_REG)));
4859
4860 if (!needs_psave && mode == fmode)
ec6376ab 4861 return gen_rtx_REG (fmode, cum->fregno);
c53bdcf5 4862
ec6376ab 4863 k = 0;
c53bdcf5
AM		 4864 if (needs_psave)
4865 {
ec6376ab 4866 /* Describe the part that goes in gprs or the stack.
c53bdcf5 4867 This piece must come first, before the fprs. */
c53bdcf5
AM		 4868 if (align_words < GP_ARG_NUM_REG)
4869 {
4870 unsigned long n_words = rs6000_arg_size (mode, type);
ec6376ab
AM		 4871
4872 if (align_words + n_words > GP_ARG_NUM_REG
4873 || (TARGET_32BIT && TARGET_POWERPC64))
4874 {
4875 /* If this is partially on the stack, then we only
4876 include the portion actually in registers here. */
4877 enum machine_mode rmode = TARGET_32BIT ? SImode : DImode;
4878 rtx off;
2e6c9641 4879 int i=0;
c4ad648e
AM		 4880 if (align_words + n_words > GP_ARG_NUM_REG
4881 && (TARGET_32BIT && TARGET_POWERPC64))
4882 /* Not all of the arg fits in gprs. Say that it
4883 goes in memory too, using a magic NULL_RTX
4884 component. Also see comment in
4885 rs6000_mixed_function_arg for why the normal
4886 function_arg_partial_nregs scheme doesn't work
4887 in this case. */
4888 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX,
4889 const0_rtx);
ec6376ab
AM		 4890 do
4891 {
4892 r = gen_rtx_REG (rmode,
4893 GP_ARG_MIN_REG + align_words);
2e6c9641 4894 off = GEN_INT (i++ * GET_MODE_SIZE (rmode));
ec6376ab
AM		 4895 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
4896 }
4897 while (++align_words < GP_ARG_NUM_REG && --n_words != 0);
4898 }
4899 else
4900 {
4901 /* The whole arg fits in gprs. */
4902 r = gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
4903 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, const0_rtx);
4904 }
c53bdcf5 4905 }
ec6376ab
AM		 4906 else
4907 /* It's entirely in memory. */
4908 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
c53bdcf5
AM		 4909 }
4910
ec6376ab
AM		 4911 /* Describe where this piece goes in the fprs. */
4912 r = gen_rtx_REG (fmode, cum->fregno);
4913 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, const0_rtx);
4914
4915 return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec));
4cc833b7
RH		 4916 }
4917 else if (align_words < GP_ARG_NUM_REG)
b2d04ecf 4918 {
ec6376ab
AM		 4919 if (TARGET_32BIT && TARGET_POWERPC64)
4920 return rs6000_mixed_function_arg (mode, type, align_words);
b2d04ecf 4921
4eeca74f
AM		 4922 if (mode == BLKmode)
4923 mode = Pmode;
4924
b2d04ecf
AM		 4925 return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
4926 }
4cc833b7
RH		 4927 else
4928 return NULL_RTX;
4697a36c 4929 }
4697a36c
MM		 4930}
4931\f
ec6376ab
AM		 4932/* For an arg passed partly in registers and partly in memory, this is
4933 the number of registers used. For args passed entirely in registers
4934 or entirely in memory, zero. When an arg is described by a PARALLEL,
4935 perhaps using more than one register type, this function returns the
78a52f11 4936 number of bytes of registers used by the PARALLEL. */
4697a36c 4937
78a52f11
RH		 4938static int
4939rs6000_arg_partial_bytes (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4940 tree type, bool named)
4697a36c 4941{
c53bdcf5 4942 int ret = 0;
ec6376ab
AM		 4943 int align;
4944 int parm_offset;
4945 int align_words;
c53bdcf5 4946
f607bc57 4947 if (DEFAULT_ABI == ABI_V4)
4697a36c 4948 return 0;
4697a36c 4949
c53bdcf5
AM		 4950 if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named)
4951 && cum->nargs_prototype >= 0)
4952 return 0;
4953
0b5383eb
DJ		 4954 /* In this complicated case we just disable the partial_nregs code. */
4955 if (rs6000_darwin64_abi && mode == BLKmode
4956 && TREE_CODE (type) == RECORD_TYPE
4957 && int_size_in_bytes (type) > 0)
4958 return 0;
4959
ec6376ab
AM		 4960 align = function_arg_boundary (mode, type) / PARM_BOUNDARY - 1;
4961 parm_offset = TARGET_32BIT ? 2 : 0;
4962 align_words = cum->words + ((parm_offset - cum->words) & align);
4963
4964 if (USE_FP_FOR_ARG_P (cum, mode, type)
4965 /* If we are passing this arg in gprs as well, then this function
4966 should return the number of gprs (or memory) partially passed,
4967 *not* the number of fprs. */
4968 && !(type
4969 && (cum->nargs_prototype <= 0
4970 || (DEFAULT_ABI == ABI_AIX
de17c25f 4971 && TARGET_XL_COMPAT
ec6376ab 4972 && align_words >= GP_ARG_NUM_REG))))
4697a36c 4973 {
c53bdcf5 4974 if (cum->fregno + ((GET_MODE_SIZE (mode) + 7) >> 3) > FP_ARG_MAX_REG + 1)
ec6376ab 4975 ret = FP_ARG_MAX_REG + 1 - cum->fregno;
c53bdcf5 4976 else if (cum->nargs_prototype >= 0)
4697a36c
MM		 4977 return 0;
4978 }
4979
ec6376ab
AM		 4980 if (align_words < GP_ARG_NUM_REG
4981 && GP_ARG_NUM_REG < align_words + rs6000_arg_size (mode, type))
4982 ret = GP_ARG_NUM_REG - align_words;
4697a36c 4983
78a52f11
RH		 4984 ret *= (TARGET_32BIT ? 4 : 8);
4985
c53bdcf5 4986 if (ret != 0 && TARGET_DEBUG_ARG)
78a52f11 4987 fprintf (stderr, "rs6000_arg_partial_bytes: %d\n", ret);
4697a36c 4988
c53bdcf5 4989 return ret;
4697a36c
MM		 4990}
4991\f
4992/* A C expression that indicates when an argument must be passed by
4993 reference. If nonzero for an argument, a copy of that argument is
4994 made in memory and a pointer to the argument is passed instead of
4995 the argument itself. The pointer is passed in whatever way is
4996 appropriate for passing a pointer to that type.
4997
b2d04ecf
AM		 4998 Under V.4, aggregates and long double are passed by reference.
4999
5000 As an extension to all 32-bit ABIs, AltiVec vectors are passed by
5001 reference unless the AltiVec vector extension ABI is in force.
c8c99a68
DE		 5002
5003 As an extension to all ABIs, variable sized types are passed by
5004 reference. */
4697a36c 5005
8cd5a4e0 5006static bool
f676971a 5007rs6000_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
bada2eb8
DE		 5008 enum machine_mode mode, tree type,
5009 bool named ATTRIBUTE_UNUSED)
4697a36c 5010{
bada2eb8 5011 if (DEFAULT_ABI == ABI_V4 && mode == TFmode)
4697a36c
MM		 5012 {
5013 if (TARGET_DEBUG_ARG)
bada2eb8
DE		 5014 fprintf (stderr, "function_arg_pass_by_reference: V4 long double\n");
5015 return 1;
5016 }
5017
5018 if (!type)
5019 return 0;
4697a36c 5020
bada2eb8
DE		 5021 if (DEFAULT_ABI == ABI_V4 && AGGREGATE_TYPE_P (type))
5022 {
5023 if (TARGET_DEBUG_ARG)
5024 fprintf (stderr, "function_arg_pass_by_reference: V4 aggregate\n");
5025 return 1;
5026 }
5027
5028 if (int_size_in_bytes (type) < 0)
5029 {
5030 if (TARGET_DEBUG_ARG)
5031 fprintf (stderr, "function_arg_pass_by_reference: variable size\n");
5032 return 1;
5033 }
5034
5035 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
5036 modes only exist for GCC vector types if -maltivec. */
5037 if (TARGET_32BIT && !TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
5038 {
5039 if (TARGET_DEBUG_ARG)
5040 fprintf (stderr, "function_arg_pass_by_reference: AltiVec\n");
4697a36c
MM		 5041 return 1;
5042 }
b693336b
PB		 5043
5044 /* Pass synthetic vectors in memory. */
bada2eb8 5045 if (TREE_CODE (type) == VECTOR_TYPE
ad630bef 5046 && int_size_in_bytes (type) > (TARGET_ALTIVEC_ABI ? 16 : 8))
b693336b
PB		 5047 {
5048 static bool warned_for_pass_big_vectors = false;
5049 if (TARGET_DEBUG_ARG)
5050 fprintf (stderr, "function_arg_pass_by_reference: synthetic vector\n");
5051 if (!warned_for_pass_big_vectors)
5052 {
bada2eb8 5053 warning ("GCC vector passed by reference: "
b693336b
PB		 5054 "non-standard ABI extension with no compatibility guarantee");
5055 warned_for_pass_big_vectors = true;
5056 }
5057 return 1;
5058 }
5059
b2d04ecf 5060 return 0;
4697a36c 5061}
5985c7a6
FJ		 5062
5063static void
2d9db8eb 5064rs6000_move_block_from_reg (int regno, rtx x, int nregs)
5985c7a6
FJ		 5065{
5066 int i;
5067 enum machine_mode reg_mode = TARGET_32BIT ? SImode : DImode;
5068
5069 if (nregs == 0)
5070 return;
5071
c4ad648e 5072 for (i = 0; i < nregs; i++)
5985c7a6 5073 {
9390387d 5074 rtx tem = adjust_address_nv (x, reg_mode, i * GET_MODE_SIZE (reg_mode));
5985c7a6 5075 if (reload_completed)
c4ad648e
AM		 5076 {
5077 if (! strict_memory_address_p (reg_mode, XEXP (tem, 0)))
5078 tem = NULL_RTX;
5079 else
5080 tem = simplify_gen_subreg (reg_mode, x, BLKmode,
9390387d 5081 i * GET_MODE_SIZE (reg_mode));
c4ad648e 5082 }
5985c7a6
FJ		 5083 else
5084 tem = replace_equiv_address (tem, XEXP (tem, 0));
5085
5086 if (tem == NULL_RTX)
c4ad648e 5087 abort ();
5985c7a6
FJ		 5088
5089 emit_move_insn (tem, gen_rtx_REG (reg_mode, regno + i));
5090 }
5091}
4697a36c
MM		 5092\f
5093/* Perform any needed actions needed for a function that is receiving a
f676971a 5094 variable number of arguments.
4697a36c
MM		 5095
5096 CUM is as above.
5097
5098 MODE and TYPE are the mode and type of the current parameter.
5099
5100 PRETEND_SIZE is a variable that should be set to the amount of stack
5101 that must be pushed by the prolog to pretend that our caller pushed
5102 it.
5103
5104 Normally, this macro will push all remaining incoming registers on the
5105 stack and set PRETEND_SIZE to the length of the registers pushed. */
5106
c6e8c921 5107static void
f676971a 5108setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
c4ad648e
AM		 5109 tree type, int *pretend_size ATTRIBUTE_UNUSED,
5110 int no_rtl)
4697a36c 5111{
4cc833b7
RH		 5112 CUMULATIVE_ARGS next_cum;
5113 int reg_size = TARGET_32BIT ? 4 : 8;
ca5adc63 5114 rtx save_area = NULL_RTX, mem;
dfafc897 5115 int first_reg_offset, set;
4697a36c 5116
f31bf321 5117 /* Skip the last named argument. */
d34c5b80 5118 next_cum = *cum;
594a51fe 5119 function_arg_advance (&next_cum, mode, type, 1, 0);
4cc833b7 5120
f607bc57 5121 if (DEFAULT_ABI == ABI_V4)
d34c5b80 5122 {
60e2d0ca 5123 if (! no_rtl)
2c4974b7 5124 save_area = plus_constant (virtual_stack_vars_rtx,
bd227acc 5125 - RS6000_VARARGS_SIZE);
4cc833b7
RH		 5126
5127 first_reg_offset = next_cum.sysv_gregno - GP_ARG_MIN_REG;
4697a36c 5128 }
60e2d0ca 5129 else
4697a36c 5130 {
d34c5b80 5131 first_reg_offset = next_cum.words;
4cc833b7 5132 save_area = virtual_incoming_args_rtx;
4697a36c 5133
fe984136 5134 if (targetm.calls.must_pass_in_stack (mode, type))
c53bdcf5 5135 first_reg_offset += rs6000_arg_size (TYPE_MODE (type), type);
4cc833b7 5136 }
4697a36c 5137
dfafc897 5138 set = get_varargs_alias_set ();
5496b36f 5139 if (! no_rtl && first_reg_offset < GP_ARG_NUM_REG)
4cc833b7 5140 {
dfafc897 5141 mem = gen_rtx_MEM (BLKmode,
c4ad648e 5142 plus_constant (save_area,
dfafc897 5143 first_reg_offset * reg_size)),
ba4828e0 5144 set_mem_alias_set (mem, set);
8ac61af7 5145 set_mem_align (mem, BITS_PER_WORD);
dfafc897 5146
f676971a 5147 rs6000_move_block_from_reg (GP_ARG_MIN_REG + first_reg_offset, mem,
c4ad648e 5148 GP_ARG_NUM_REG - first_reg_offset);
4697a36c
MM		 5149 }
5150
4697a36c 5151 /* Save FP registers if needed. */
f607bc57 5152 if (DEFAULT_ABI == ABI_V4
a3170dc6
AH		 5153 && TARGET_HARD_FLOAT && TARGET_FPRS
5154 && ! no_rtl
5496b36f 5155 && next_cum.fregno <= FP_ARG_V4_MAX_REG)
4697a36c 5156 {
5496b36f 5157 int fregno = next_cum.fregno;
9ebbca7d 5158 rtx cr1 = gen_rtx_REG (CCmode, CR1_REGNO);
4cc833b7
RH		 5159 rtx lab = gen_label_rtx ();
5160 int off = (GP_ARG_NUM_REG * reg_size) + ((fregno - FP_ARG_MIN_REG) * 8);
4697a36c 5161
c4ad648e
AM		 5162 emit_jump_insn
5163 (gen_rtx_SET (VOIDmode,
5164 pc_rtx,
5165 gen_rtx_IF_THEN_ELSE (VOIDmode,
4cc833b7 5166 gen_rtx_NE (VOIDmode, cr1,
c4ad648e 5167 const0_rtx),
39403d82 5168 gen_rtx_LABEL_REF (VOIDmode, lab),
4697a36c
MM		 5169 pc_rtx)));
5170
5496b36f 5171 while (fregno <= FP_ARG_V4_MAX_REG)
4cc833b7 5172 {
5496b36f 5173 mem = gen_rtx_MEM (DFmode, plus_constant (save_area, off));
c4ad648e 5174 set_mem_alias_set (mem, set);
94ff898d 5175 set_mem_align (mem, GET_MODE_ALIGNMENT (DFmode));
dfafc897 5176 emit_move_insn (mem, gen_rtx_REG (DFmode, fregno));
5496b36f
JJ		 5177 fregno++;
5178 off += 8;
4697a36c 5179 }
4cc833b7
RH		 5180
5181 emit_label (lab);
4697a36c 5182 }
4697a36c 5183}
4697a36c 5184
dfafc897 5185/* Create the va_list data type. */
2c4974b7 5186
c35d187f
RH		 5187static tree
5188rs6000_build_builtin_va_list (void)
dfafc897 5189{
64c2816f 5190 tree f_gpr, f_fpr, f_res, f_ovf, f_sav, record, type_decl;
4697a36c 5191
9ebbca7d
GK		 5192 /* For AIX, prefer 'char *' because that's what the system
5193 header files like. */
f607bc57 5194 if (DEFAULT_ABI != ABI_V4)
9ebbca7d 5195 return build_pointer_type (char_type_node);
dfafc897 5196
f1e639b1 5197 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
bab45a51 5198 type_decl = build_decl (TYPE_DECL, get_identifier ("__va_list_tag"), record);
0f4fd75d 5199
f676971a 5200 f_gpr = build_decl (FIELD_DECL, get_identifier ("gpr"),
9ebbca7d 5201 unsigned_char_type_node);
f676971a 5202 f_fpr = build_decl (FIELD_DECL, get_identifier ("fpr"),
9ebbca7d 5203 unsigned_char_type_node);
64c2816f
DT		 5204 /* Give the two bytes of padding a name, so that -Wpadded won't warn on
5205 every user file. */
5206 f_res = build_decl (FIELD_DECL, get_identifier ("reserved"),
5207 short_unsigned_type_node);
dfafc897
FS		 5208 f_ovf = build_decl (FIELD_DECL, get_identifier ("overflow_arg_area"),
5209 ptr_type_node);
5210 f_sav = build_decl (FIELD_DECL, get_identifier ("reg_save_area"),
5211 ptr_type_node);
5212
5213 DECL_FIELD_CONTEXT (f_gpr) = record;
5214 DECL_FIELD_CONTEXT (f_fpr) = record;
64c2816f 5215 DECL_FIELD_CONTEXT (f_res) = record;
dfafc897
FS		 5216 DECL_FIELD_CONTEXT (f_ovf) = record;
5217 DECL_FIELD_CONTEXT (f_sav) = record;
5218
bab45a51
FS		 5219 TREE_CHAIN (record) = type_decl;
5220 TYPE_NAME (record) = type_decl;
dfafc897
FS		 5221 TYPE_FIELDS (record) = f_gpr;
5222 TREE_CHAIN (f_gpr) = f_fpr;
64c2816f
DT		 5223 TREE_CHAIN (f_fpr) = f_res;
5224 TREE_CHAIN (f_res) = f_ovf;
dfafc897
FS		 5225 TREE_CHAIN (f_ovf) = f_sav;
5226
5227 layout_type (record);
5228
5229 /* The correct type is an array type of one element. */
5230 return build_array_type (record, build_index_type (size_zero_node));
5231}
5232
5233/* Implement va_start. */
5234
5235void
a2369ed3 5236rs6000_va_start (tree valist, rtx nextarg)
4697a36c 5237{
dfafc897 5238 HOST_WIDE_INT words, n_gpr, n_fpr;
c566f9bd 5239 tree f_gpr, f_fpr, f_res, f_ovf, f_sav;
dfafc897 5240 tree gpr, fpr, ovf, sav, t;
2c4974b7 5241
dfafc897 5242 /* Only SVR4 needs something special. */
f607bc57 5243 if (DEFAULT_ABI != ABI_V4)
dfafc897 5244 {
e5faf155 5245 std_expand_builtin_va_start (valist, nextarg);
dfafc897
FS		 5246 return;
5247 }
5248
973a648b 5249 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
dfafc897 5250 f_fpr = TREE_CHAIN (f_gpr);
c566f9bd
DT		 5251 f_res = TREE_CHAIN (f_fpr);
5252 f_ovf = TREE_CHAIN (f_res);
dfafc897
FS		 5253 f_sav = TREE_CHAIN (f_ovf);
5254
872a65b5 5255 valist = build_va_arg_indirect_ref (valist);
44de5aeb
RK		 5256 gpr = build (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
5257 fpr = build (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
5258 ovf = build (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
5259 sav = build (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
dfafc897
FS		 5260
5261 /* Count number of gp and fp argument registers used. */
4cc833b7 5262 words = current_function_args_info.words;
987732e0
DE		 5263 n_gpr = MIN (current_function_args_info.sysv_gregno - GP_ARG_MIN_REG,
5264 GP_ARG_NUM_REG);
5265 n_fpr = MIN (current_function_args_info.fregno - FP_ARG_MIN_REG,
5266 FP_ARG_NUM_REG);
dfafc897
FS		 5267
5268 if (TARGET_DEBUG_ARG)
4a0a75dd
KG		 5269 fprintf (stderr, "va_start: words = "HOST_WIDE_INT_PRINT_DEC", n_gpr = "
5270 HOST_WIDE_INT_PRINT_DEC", n_fpr = "HOST_WIDE_INT_PRINT_DEC"\n",
5271 words, n_gpr, n_fpr);
dfafc897 5272
5496b36f
JJ		 5273 t = build (MODIFY_EXPR, TREE_TYPE (gpr), gpr,
5274 build_int_cst (NULL_TREE, n_gpr));
5275 TREE_SIDE_EFFECTS (t) = 1;
5276 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
58c8adc1 5277
5496b36f
JJ		 5278 t = build (MODIFY_EXPR, TREE_TYPE (fpr), fpr,
5279 build_int_cst (NULL_TREE, n_fpr));
5280 TREE_SIDE_EFFECTS (t) = 1;
5281 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
dfafc897
FS		 5282
5283 /* Find the overflow area. */
5284 t = make_tree (TREE_TYPE (ovf), virtual_incoming_args_rtx);
5285 if (words != 0)
5286 t = build (PLUS_EXPR, TREE_TYPE (ovf), t,
7d60be94 5287 build_int_cst (NULL_TREE, words * UNITS_PER_WORD));
dfafc897
FS		 5288 t = build (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t);
5289 TREE_SIDE_EFFECTS (t) = 1;
5290 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5291
5292 /* Find the register save area. */
5293 t = make_tree (TREE_TYPE (sav), virtual_stack_vars_rtx);
5294 t = build (PLUS_EXPR, TREE_TYPE (sav), t,
7d60be94 5295 build_int_cst (NULL_TREE, -RS6000_VARARGS_SIZE));
dfafc897
FS		 5296 t = build (MODIFY_EXPR, TREE_TYPE (sav), sav, t);
5297 TREE_SIDE_EFFECTS (t) = 1;
5298 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5299}
5300
5301/* Implement va_arg. */
5302
23a60a04
JM		 5303tree
5304rs6000_gimplify_va_arg (tree valist, tree type, tree *pre_p, tree *post_p)
cd3ce9b4 5305{
cd3ce9b4
JM		 5306 tree f_gpr, f_fpr, f_res, f_ovf, f_sav;
5307 tree gpr, fpr, ovf, sav, reg, t, u;
08b0dc1b 5308 int size, rsize, n_reg, sav_ofs, sav_scale;
cd3ce9b4
JM		 5309 tree lab_false, lab_over, addr;
5310 int align;
5311 tree ptrtype = build_pointer_type (type);
5312
08b0dc1b
RH		 5313 if (pass_by_reference (NULL, TYPE_MODE (type), type, false))
5314 {
5315 t = rs6000_gimplify_va_arg (valist, ptrtype, pre_p, post_p);
872a65b5 5316 return build_va_arg_indirect_ref (t);
08b0dc1b
RH		 5317 }
5318
cd3ce9b4
JM		 5319 if (DEFAULT_ABI != ABI_V4)
5320 {
08b0dc1b 5321 if (targetm.calls.split_complex_arg && TREE_CODE (type) == COMPLEX_TYPE)
cd3ce9b4
JM		 5322 {
5323 tree elem_type = TREE_TYPE (type);
5324 enum machine_mode elem_mode = TYPE_MODE (elem_type);
5325 int elem_size = GET_MODE_SIZE (elem_mode);
5326
5327 if (elem_size < UNITS_PER_WORD)
5328 {
23a60a04 5329 tree real_part, imag_part;
cd3ce9b4
JM		 5330 tree post = NULL_TREE;
5331
23a60a04
JM		 5332 real_part = rs6000_gimplify_va_arg (valist, elem_type, pre_p,
5333 &post);
5334 /* Copy the value into a temporary, lest the formal temporary
5335 be reused out from under us. */
5336 real_part = get_initialized_tmp_var (real_part, pre_p, &post);
cd3ce9b4
JM		 5337 append_to_statement_list (post, pre_p);
5338
23a60a04
JM		 5339 imag_part = rs6000_gimplify_va_arg (valist, elem_type, pre_p,
5340 post_p);
cd3ce9b4 5341
23a60a04 5342 return build (COMPLEX_EXPR, type, real_part, imag_part);
cd3ce9b4
JM		 5343 }
5344 }
5345
23a60a04 5346 return std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
cd3ce9b4
JM		 5347 }
5348
5349 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
5350 f_fpr = TREE_CHAIN (f_gpr);
5351 f_res = TREE_CHAIN (f_fpr);
5352 f_ovf = TREE_CHAIN (f_res);
5353 f_sav = TREE_CHAIN (f_ovf);
5354
872a65b5 5355 valist = build_va_arg_indirect_ref (valist);
44de5aeb
RK		 5356 gpr = build (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
5357 fpr = build (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
5358 ovf = build (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
5359 sav = build (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
cd3ce9b4
JM		 5360
5361 size = int_size_in_bytes (type);
5362 rsize = (size + 3) / 4;
5363 align = 1;
5364
08b0dc1b
RH		 5365 if (TARGET_HARD_FLOAT && TARGET_FPRS
5366 && (TYPE_MODE (type) == SFmode || TYPE_MODE (type) == DFmode))
cd3ce9b4
JM		 5367 {
5368 /* FP args go in FP registers, if present. */
cd3ce9b4
JM		 5369 reg = fpr;
5370 n_reg = 1;
5371 sav_ofs = 8*4;
5372 sav_scale = 8;
5373 if (TYPE_MODE (type) == DFmode)
5374 align = 8;
5375 }
5376 else
5377 {
5378 /* Otherwise into GP registers. */
cd3ce9b4
JM		 5379 reg = gpr;
5380 n_reg = rsize;
5381 sav_ofs = 0;
5382 sav_scale = 4;
5383 if (n_reg == 2)
5384 align = 8;
5385 }
5386
5387 /* Pull the value out of the saved registers.... */
5388
5389 lab_over = NULL;
5390 addr = create_tmp_var (ptr_type_node, "addr");
5391 DECL_POINTER_ALIAS_SET (addr) = get_varargs_alias_set ();
5392
5393 /* AltiVec vectors never go in registers when -mabi=altivec. */
5394 if (TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (TYPE_MODE (type)))
5395 align = 16;
5396 else
5397 {
5398 lab_false = create_artificial_label ();
5399 lab_over = create_artificial_label ();
5400
5401 /* Long long and SPE vectors are aligned in the registers.
5402 As are any other 2 gpr item such as complex int due to a
5403 historical mistake. */
5404 u = reg;
5405 if (n_reg == 2)
5406 {
5407 u = build2 (BIT_AND_EXPR, TREE_TYPE (reg), reg,
95674810 5408 size_int (n_reg - 1));
cd3ce9b4
JM		 5409 u = build2 (POSTINCREMENT_EXPR, TREE_TYPE (reg), reg, u);
5410 }
5411
95674810 5412 t = fold_convert (TREE_TYPE (reg), size_int (8 - n_reg + 1));
cd3ce9b4
JM		 5413 t = build2 (GE_EXPR, boolean_type_node, u, t);
5414 u = build1 (GOTO_EXPR, void_type_node, lab_false);
5415 t = build3 (COND_EXPR, void_type_node, t, u, NULL_TREE);
5416 gimplify_and_add (t, pre_p);
5417
5418 t = sav;
5419 if (sav_ofs)
95674810 5420 t = build2 (PLUS_EXPR, ptr_type_node, sav, size_int (sav_ofs));
cd3ce9b4 5421
95674810 5422 u = build2 (POSTINCREMENT_EXPR, TREE_TYPE (reg), reg, size_int (n_reg));
cd3ce9b4 5423 u = build1 (CONVERT_EXPR, integer_type_node, u);
95674810 5424 u = build2 (MULT_EXPR, integer_type_node, u, size_int (sav_scale));
cd3ce9b4
JM		 5425 t = build2 (PLUS_EXPR, ptr_type_node, t, u);
5426
5427 t = build2 (MODIFY_EXPR, void_type_node, addr, t);
5428 gimplify_and_add (t, pre_p);
5429
5430 t = build1 (GOTO_EXPR, void_type_node, lab_over);
5431 gimplify_and_add (t, pre_p);
5432
5433 t = build1 (LABEL_EXPR, void_type_node, lab_false);
5434 append_to_statement_list (t, pre_p);
5435
5436 if (n_reg > 2)
5437 {
5438 /* Ensure that we don't find any more args in regs.
5439 Alignment has taken care of the n_reg == 2 case. */
95674810 5440 t = build (MODIFY_EXPR, TREE_TYPE (reg), reg, size_int (8));
cd3ce9b4
JM		 5441 gimplify_and_add (t, pre_p);
5442 }
5443 }
5444
5445 /* ... otherwise out of the overflow area. */
5446
5447 /* Care for on-stack alignment if needed. */
5448 t = ovf;
5449 if (align != 1)
5450 {
95674810 5451 t = build2 (PLUS_EXPR, TREE_TYPE (t), t, size_int (align - 1));
4a90aeeb 5452 t = build2 (BIT_AND_EXPR, TREE_TYPE (t), t,
7d60be94 5453 build_int_cst (NULL_TREE, -align));
cd3ce9b4
JM		 5454 }
5455 gimplify_expr (&t, pre_p, NULL, is_gimple_val, fb_rvalue);
5456
5457 u = build2 (MODIFY_EXPR, void_type_node, addr, t);
5458 gimplify_and_add (u, pre_p);
5459
95674810 5460 t = build2 (PLUS_EXPR, TREE_TYPE (t), t, size_int (size));
cd3ce9b4
JM		 5461 t = build2 (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t);
5462 gimplify_and_add (t, pre_p);
5463
5464 if (lab_over)
5465 {
5466 t = build1 (LABEL_EXPR, void_type_node, lab_over);
5467 append_to_statement_list (t, pre_p);
5468 }
5469
08b0dc1b 5470 addr = fold_convert (ptrtype, addr);
872a65b5 5471 return build_va_arg_indirect_ref (addr);
cd3ce9b4
JM		 5472}
5473
0ac081f6
AH		 5474/* Builtins. */
5475
6e34d3a3
JM		 5476#define def_builtin(MASK, NAME, TYPE, CODE) \
5477do { \
5478 if ((MASK) & target_flags) \
5479 lang_hooks.builtin_function ((NAME), (TYPE), (CODE), BUILT_IN_MD, \
5480 NULL, NULL_TREE); \
0ac081f6
AH		 5481} while (0)
5482
24408032
AH		 5483/* Simple ternary operations: VECd = foo (VECa, VECb, VECc). */
5484
2212663f 5485static const struct builtin_description bdesc_3arg[] =
24408032
AH		 5486{
5487 { MASK_ALTIVEC, CODE_FOR_altivec_vmaddfp, "__builtin_altivec_vmaddfp", ALTIVEC_BUILTIN_VMADDFP },
5488 { MASK_ALTIVEC, CODE_FOR_altivec_vmhaddshs, "__builtin_altivec_vmhaddshs", ALTIVEC_BUILTIN_VMHADDSHS },
5489 { MASK_ALTIVEC, CODE_FOR_altivec_vmhraddshs, "__builtin_altivec_vmhraddshs", ALTIVEC_BUILTIN_VMHRADDSHS },
5490 { MASK_ALTIVEC, CODE_FOR_altivec_vmladduhm, "__builtin_altivec_vmladduhm", ALTIVEC_BUILTIN_VMLADDUHM},
5491 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumubm, "__builtin_altivec_vmsumubm", ALTIVEC_BUILTIN_VMSUMUBM },
5492 { MASK_ALTIVEC, CODE_FOR_altivec_vmsummbm, "__builtin_altivec_vmsummbm", ALTIVEC_BUILTIN_VMSUMMBM },
5493 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumuhm, "__builtin_altivec_vmsumuhm", ALTIVEC_BUILTIN_VMSUMUHM },
5494 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumshm, "__builtin_altivec_vmsumshm", ALTIVEC_BUILTIN_VMSUMSHM },
5495 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumuhs, "__builtin_altivec_vmsumuhs", ALTIVEC_BUILTIN_VMSUMUHS },
5496 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumshs, "__builtin_altivec_vmsumshs", ALTIVEC_BUILTIN_VMSUMSHS },
f676971a 5497 { MASK_ALTIVEC, CODE_FOR_altivec_vnmsubfp, "__builtin_altivec_vnmsubfp", ALTIVEC_BUILTIN_VNMSUBFP },
aba5fb01
NS		 5498 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v4sf, "__builtin_altivec_vperm_4sf", ALTIVEC_BUILTIN_VPERM_4SF },
5499 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v4si, "__builtin_altivec_vperm_4si", ALTIVEC_BUILTIN_VPERM_4SI },
5500 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v8hi, "__builtin_altivec_vperm_8hi", ALTIVEC_BUILTIN_VPERM_8HI },
5501 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v16qi, "__builtin_altivec_vperm_16qi", ALTIVEC_BUILTIN_VPERM_16QI },
5502 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v4sf, "__builtin_altivec_vsel_4sf", ALTIVEC_BUILTIN_VSEL_4SF },
5503 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v4si, "__builtin_altivec_vsel_4si", ALTIVEC_BUILTIN_VSEL_4SI },
5504 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v8hi, "__builtin_altivec_vsel_8hi", ALTIVEC_BUILTIN_VSEL_8HI },
5505 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v16qi, "__builtin_altivec_vsel_16qi", ALTIVEC_BUILTIN_VSEL_16QI },
5506 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v16qi, "__builtin_altivec_vsldoi_16qi", ALTIVEC_BUILTIN_VSLDOI_16QI },
5507 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v8hi, "__builtin_altivec_vsldoi_8hi", ALTIVEC_BUILTIN_VSLDOI_8HI },
5508 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v4si, "__builtin_altivec_vsldoi_4si", ALTIVEC_BUILTIN_VSLDOI_4SI },
5509 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v4sf, "__builtin_altivec_vsldoi_4sf", ALTIVEC_BUILTIN_VSLDOI_4SF },
24408032 5510};
2212663f 5511
95385cbb
AH		 5512/* DST operations: void foo (void *, const int, const char). */
5513
5514static const struct builtin_description bdesc_dst[] =
5515{
5516 { MASK_ALTIVEC, CODE_FOR_altivec_dst, "__builtin_altivec_dst", ALTIVEC_BUILTIN_DST },
5517 { MASK_ALTIVEC, CODE_FOR_altivec_dstt, "__builtin_altivec_dstt", ALTIVEC_BUILTIN_DSTT },
5518 { MASK_ALTIVEC, CODE_FOR_altivec_dstst, "__builtin_altivec_dstst", ALTIVEC_BUILTIN_DSTST },
5519 { MASK_ALTIVEC, CODE_FOR_altivec_dststt, "__builtin_altivec_dststt", ALTIVEC_BUILTIN_DSTSTT }
5520};
5521
2212663f 5522/* Simple binary operations: VECc = foo (VECa, VECb). */
24408032 5523
a3170dc6 5524static struct builtin_description bdesc_2arg[] =
0ac081f6 5525{
f18c054f
DB		 5526 { MASK_ALTIVEC, CODE_FOR_addv16qi3, "__builtin_altivec_vaddubm", ALTIVEC_BUILTIN_VADDUBM },
5527 { MASK_ALTIVEC, CODE_FOR_addv8hi3, "__builtin_altivec_vadduhm", ALTIVEC_BUILTIN_VADDUHM },
5528 { MASK_ALTIVEC, CODE_FOR_addv4si3, "__builtin_altivec_vadduwm", ALTIVEC_BUILTIN_VADDUWM },
5529 { MASK_ALTIVEC, CODE_FOR_addv4sf3, "__builtin_altivec_vaddfp", ALTIVEC_BUILTIN_VADDFP },
0ac081f6
AH		 5530 { MASK_ALTIVEC, CODE_FOR_altivec_vaddcuw, "__builtin_altivec_vaddcuw", ALTIVEC_BUILTIN_VADDCUW },
5531 { MASK_ALTIVEC, CODE_FOR_altivec_vaddubs, "__builtin_altivec_vaddubs", ALTIVEC_BUILTIN_VADDUBS },
5532 { MASK_ALTIVEC, CODE_FOR_altivec_vaddsbs, "__builtin_altivec_vaddsbs", ALTIVEC_BUILTIN_VADDSBS },
5533 { MASK_ALTIVEC, CODE_FOR_altivec_vadduhs, "__builtin_altivec_vadduhs", ALTIVEC_BUILTIN_VADDUHS },
5534 { MASK_ALTIVEC, CODE_FOR_altivec_vaddshs, "__builtin_altivec_vaddshs", ALTIVEC_BUILTIN_VADDSHS },
5535 { MASK_ALTIVEC, CODE_FOR_altivec_vadduws, "__builtin_altivec_vadduws", ALTIVEC_BUILTIN_VADDUWS },
5536 { MASK_ALTIVEC, CODE_FOR_altivec_vaddsws, "__builtin_altivec_vaddsws", ALTIVEC_BUILTIN_VADDSWS },
f18c054f 5537 { MASK_ALTIVEC, CODE_FOR_andv4si3, "__builtin_altivec_vand", ALTIVEC_BUILTIN_VAND },
aba5fb01 5538 { MASK_ALTIVEC, CODE_FOR_andcv4si3, "__builtin_altivec_vandc", ALTIVEC_BUILTIN_VANDC },
0ac081f6
AH		 5539 { MASK_ALTIVEC, CODE_FOR_altivec_vavgub, "__builtin_altivec_vavgub", ALTIVEC_BUILTIN_VAVGUB },
5540 { MASK_ALTIVEC, CODE_FOR_altivec_vavgsb, "__builtin_altivec_vavgsb", ALTIVEC_BUILTIN_VAVGSB },
5541 { MASK_ALTIVEC, CODE_FOR_altivec_vavguh, "__builtin_altivec_vavguh", ALTIVEC_BUILTIN_VAVGUH },
5542 { MASK_ALTIVEC, CODE_FOR_altivec_vavgsh, "__builtin_altivec_vavgsh", ALTIVEC_BUILTIN_VAVGSH },
5543 { MASK_ALTIVEC, CODE_FOR_altivec_vavguw, "__builtin_altivec_vavguw", ALTIVEC_BUILTIN_VAVGUW },
5544 { MASK_ALTIVEC, CODE_FOR_altivec_vavgsw, "__builtin_altivec_vavgsw", ALTIVEC_BUILTIN_VAVGSW },
617e0e1d
DB		 5545 { MASK_ALTIVEC, CODE_FOR_altivec_vcfux, "__builtin_altivec_vcfux", ALTIVEC_BUILTIN_VCFUX },
5546 { MASK_ALTIVEC, CODE_FOR_altivec_vcfsx, "__builtin_altivec_vcfsx", ALTIVEC_BUILTIN_VCFSX },
0ac081f6
AH		 5547 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpbfp, "__builtin_altivec_vcmpbfp", ALTIVEC_BUILTIN_VCMPBFP },
5548 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequb, "__builtin_altivec_vcmpequb", ALTIVEC_BUILTIN_VCMPEQUB },
5549 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequh, "__builtin_altivec_vcmpequh", ALTIVEC_BUILTIN_VCMPEQUH },
5550 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequw, "__builtin_altivec_vcmpequw", ALTIVEC_BUILTIN_VCMPEQUW },
5551 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpeqfp, "__builtin_altivec_vcmpeqfp", ALTIVEC_BUILTIN_VCMPEQFP },
5552 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgefp, "__builtin_altivec_vcmpgefp", ALTIVEC_BUILTIN_VCMPGEFP },
5553 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtub, "__builtin_altivec_vcmpgtub", ALTIVEC_BUILTIN_VCMPGTUB },
5554 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsb, "__builtin_altivec_vcmpgtsb", ALTIVEC_BUILTIN_VCMPGTSB },
5555 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtuh, "__builtin_altivec_vcmpgtuh", ALTIVEC_BUILTIN_VCMPGTUH },
5556 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsh, "__builtin_altivec_vcmpgtsh", ALTIVEC_BUILTIN_VCMPGTSH },
5557 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtuw, "__builtin_altivec_vcmpgtuw", ALTIVEC_BUILTIN_VCMPGTUW },
5558 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsw, "__builtin_altivec_vcmpgtsw", ALTIVEC_BUILTIN_VCMPGTSW },
5559 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtfp, "__builtin_altivec_vcmpgtfp", ALTIVEC_BUILTIN_VCMPGTFP },
617e0e1d
DB		 5560 { MASK_ALTIVEC, CODE_FOR_altivec_vctsxs, "__builtin_altivec_vctsxs", ALTIVEC_BUILTIN_VCTSXS },
5561 { MASK_ALTIVEC, CODE_FOR_altivec_vctuxs, "__builtin_altivec_vctuxs", ALTIVEC_BUILTIN_VCTUXS },
f18c054f
DB		 5562 { MASK_ALTIVEC, CODE_FOR_umaxv16qi3, "__builtin_altivec_vmaxub", ALTIVEC_BUILTIN_VMAXUB },
5563 { MASK_ALTIVEC, CODE_FOR_smaxv16qi3, "__builtin_altivec_vmaxsb", ALTIVEC_BUILTIN_VMAXSB },
df966bff
AH		 5564 { MASK_ALTIVEC, CODE_FOR_umaxv8hi3, "__builtin_altivec_vmaxuh", ALTIVEC_BUILTIN_VMAXUH },
5565 { MASK_ALTIVEC, CODE_FOR_smaxv8hi3, "__builtin_altivec_vmaxsh", ALTIVEC_BUILTIN_VMAXSH },
5566 { MASK_ALTIVEC, CODE_FOR_umaxv4si3, "__builtin_altivec_vmaxuw", ALTIVEC_BUILTIN_VMAXUW },
5567 { MASK_ALTIVEC, CODE_FOR_smaxv4si3, "__builtin_altivec_vmaxsw", ALTIVEC_BUILTIN_VMAXSW },
5568 { MASK_ALTIVEC, CODE_FOR_smaxv4sf3, "__builtin_altivec_vmaxfp", ALTIVEC_BUILTIN_VMAXFP },
0ac081f6
AH		 5569 { MASK_ALTIVEC, CODE_FOR_altivec_vmrghb, "__builtin_altivec_vmrghb", ALTIVEC_BUILTIN_VMRGHB },
5570 { MASK_ALTIVEC, CODE_FOR_altivec_vmrghh, "__builtin_altivec_vmrghh", ALTIVEC_BUILTIN_VMRGHH },
5571 { MASK_ALTIVEC, CODE_FOR_altivec_vmrghw, "__builtin_altivec_vmrghw", ALTIVEC_BUILTIN_VMRGHW },
5572 { MASK_ALTIVEC, CODE_FOR_altivec_vmrglb, "__builtin_altivec_vmrglb", ALTIVEC_BUILTIN_VMRGLB },
5573 { MASK_ALTIVEC, CODE_FOR_altivec_vmrglh, "__builtin_altivec_vmrglh", ALTIVEC_BUILTIN_VMRGLH },
5574 { MASK_ALTIVEC, CODE_FOR_altivec_vmrglw, "__builtin_altivec_vmrglw", ALTIVEC_BUILTIN_VMRGLW },
f18c054f
DB		 5575 { MASK_ALTIVEC, CODE_FOR_uminv16qi3, "__builtin_altivec_vminub", ALTIVEC_BUILTIN_VMINUB },
5576 { MASK_ALTIVEC, CODE_FOR_sminv16qi3, "__builtin_altivec_vminsb", ALTIVEC_BUILTIN_VMINSB },
5577 { MASK_ALTIVEC, CODE_FOR_uminv8hi3, "__builtin_altivec_vminuh", ALTIVEC_BUILTIN_VMINUH },
5578 { MASK_ALTIVEC, CODE_FOR_sminv8hi3, "__builtin_altivec_vminsh", ALTIVEC_BUILTIN_VMINSH },
5579 { MASK_ALTIVEC, CODE_FOR_uminv4si3, "__builtin_altivec_vminuw", ALTIVEC_BUILTIN_VMINUW },
5580 { MASK_ALTIVEC, CODE_FOR_sminv4si3, "__builtin_altivec_vminsw", ALTIVEC_BUILTIN_VMINSW },
5581 { MASK_ALTIVEC, CODE_FOR_sminv4sf3, "__builtin_altivec_vminfp", ALTIVEC_BUILTIN_VMINFP },
0ac081f6
AH		 5582 { MASK_ALTIVEC, CODE_FOR_altivec_vmuleub, "__builtin_altivec_vmuleub", ALTIVEC_BUILTIN_VMULEUB },
5583 { MASK_ALTIVEC, CODE_FOR_altivec_vmulesb, "__builtin_altivec_vmulesb", ALTIVEC_BUILTIN_VMULESB },
5584 { MASK_ALTIVEC, CODE_FOR_altivec_vmuleuh, "__builtin_altivec_vmuleuh", ALTIVEC_BUILTIN_VMULEUH },
5585 { MASK_ALTIVEC, CODE_FOR_altivec_vmulesh, "__builtin_altivec_vmulesh", ALTIVEC_BUILTIN_VMULESH },
5586 { MASK_ALTIVEC, CODE_FOR_altivec_vmuloub, "__builtin_altivec_vmuloub", ALTIVEC_BUILTIN_VMULOUB },
5587 { MASK_ALTIVEC, CODE_FOR_altivec_vmulosb, "__builtin_altivec_vmulosb", ALTIVEC_BUILTIN_VMULOSB },
5588 { MASK_ALTIVEC, CODE_FOR_altivec_vmulouh, "__builtin_altivec_vmulouh", ALTIVEC_BUILTIN_VMULOUH },
5589 { MASK_ALTIVEC, CODE_FOR_altivec_vmulosh, "__builtin_altivec_vmulosh", ALTIVEC_BUILTIN_VMULOSH },
f96bc213 5590 { MASK_ALTIVEC, CODE_FOR_altivec_norv4si3, "__builtin_altivec_vnor", ALTIVEC_BUILTIN_VNOR },
f18c054f 5591 { MASK_ALTIVEC, CODE_FOR_iorv4si3, "__builtin_altivec_vor", ALTIVEC_BUILTIN_VOR },
0ac081f6
AH		 5592 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhum, "__builtin_altivec_vpkuhum", ALTIVEC_BUILTIN_VPKUHUM },
5593 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwum, "__builtin_altivec_vpkuwum", ALTIVEC_BUILTIN_VPKUWUM },
5594 { MASK_ALTIVEC, CODE_FOR_altivec_vpkpx, "__builtin_altivec_vpkpx", ALTIVEC_BUILTIN_VPKPX },
5595 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhss, "__builtin_altivec_vpkuhss", ALTIVEC_BUILTIN_VPKUHSS },
5596 { MASK_ALTIVEC, CODE_FOR_altivec_vpkshss, "__builtin_altivec_vpkshss", ALTIVEC_BUILTIN_VPKSHSS },
5597 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwss, "__builtin_altivec_vpkuwss", ALTIVEC_BUILTIN_VPKUWSS },
5598 { MASK_ALTIVEC, CODE_FOR_altivec_vpkswss, "__builtin_altivec_vpkswss", ALTIVEC_BUILTIN_VPKSWSS },
5599 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhus, "__builtin_altivec_vpkuhus", ALTIVEC_BUILTIN_VPKUHUS },
5600 { MASK_ALTIVEC, CODE_FOR_altivec_vpkshus, "__builtin_altivec_vpkshus", ALTIVEC_BUILTIN_VPKSHUS },
5601 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwus, "__builtin_altivec_vpkuwus", ALTIVEC_BUILTIN_VPKUWUS },
5602 { MASK_ALTIVEC, CODE_FOR_altivec_vpkswus, "__builtin_altivec_vpkswus", ALTIVEC_BUILTIN_VPKSWUS },
5603 { MASK_ALTIVEC, CODE_FOR_altivec_vrlb, "__builtin_altivec_vrlb", ALTIVEC_BUILTIN_VRLB },
5604 { MASK_ALTIVEC, CODE_FOR_altivec_vrlh, "__builtin_altivec_vrlh", ALTIVEC_BUILTIN_VRLH },
5605 { MASK_ALTIVEC, CODE_FOR_altivec_vrlw, "__builtin_altivec_vrlw", ALTIVEC_BUILTIN_VRLW },
5606 { MASK_ALTIVEC, CODE_FOR_altivec_vslb, "__builtin_altivec_vslb", ALTIVEC_BUILTIN_VSLB },
5607 { MASK_ALTIVEC, CODE_FOR_altivec_vslh, "__builtin_altivec_vslh", ALTIVEC_BUILTIN_VSLH },
5608 { MASK_ALTIVEC, CODE_FOR_altivec_vslw, "__builtin_altivec_vslw", ALTIVEC_BUILTIN_VSLW },
5609 { MASK_ALTIVEC, CODE_FOR_altivec_vsl, "__builtin_altivec_vsl", ALTIVEC_BUILTIN_VSL },
5610 { MASK_ALTIVEC, CODE_FOR_altivec_vslo, "__builtin_altivec_vslo", ALTIVEC_BUILTIN_VSLO },
2212663f
DB		 5611 { MASK_ALTIVEC, CODE_FOR_altivec_vspltb, "__builtin_altivec_vspltb", ALTIVEC_BUILTIN_VSPLTB },
5612 { MASK_ALTIVEC, CODE_FOR_altivec_vsplth, "__builtin_altivec_vsplth", ALTIVEC_BUILTIN_VSPLTH },
5613 { MASK_ALTIVEC, CODE_FOR_altivec_vspltw, "__builtin_altivec_vspltw", ALTIVEC_BUILTIN_VSPLTW },
0ac081f6 5614 { MASK_ALTIVEC, CODE_FOR_altivec_vsrb, "__builtin_altivec_vsrb", ALTIVEC_BUILTIN_VSRB },
f18c054f
DB		 5615 { MASK_ALTIVEC, CODE_FOR_altivec_vsrh, "__builtin_altivec_vsrh", ALTIVEC_BUILTIN_VSRH },
5616 { MASK_ALTIVEC, CODE_FOR_altivec_vsrw, "__builtin_altivec_vsrw", ALTIVEC_BUILTIN_VSRW },
0ac081f6
AH		 5617 { MASK_ALTIVEC, CODE_FOR_altivec_vsrab, "__builtin_altivec_vsrab", ALTIVEC_BUILTIN_VSRAB },
5618 { MASK_ALTIVEC, CODE_FOR_altivec_vsrah, "__builtin_altivec_vsrah", ALTIVEC_BUILTIN_VSRAH },
5619 { MASK_ALTIVEC, CODE_FOR_altivec_vsraw, "__builtin_altivec_vsraw", ALTIVEC_BUILTIN_VSRAW },
5620 { MASK_ALTIVEC, CODE_FOR_altivec_vsr, "__builtin_altivec_vsr", ALTIVEC_BUILTIN_VSR },
5621 { MASK_ALTIVEC, CODE_FOR_altivec_vsro, "__builtin_altivec_vsro", ALTIVEC_BUILTIN_VSRO },
f18c054f
DB		 5622 { MASK_ALTIVEC, CODE_FOR_subv16qi3, "__builtin_altivec_vsububm", ALTIVEC_BUILTIN_VSUBUBM },
5623 { MASK_ALTIVEC, CODE_FOR_subv8hi3, "__builtin_altivec_vsubuhm", ALTIVEC_BUILTIN_VSUBUHM },
5624 { MASK_ALTIVEC, CODE_FOR_subv4si3, "__builtin_altivec_vsubuwm", ALTIVEC_BUILTIN_VSUBUWM },
5625 { MASK_ALTIVEC, CODE_FOR_subv4sf3, "__builtin_altivec_vsubfp", ALTIVEC_BUILTIN_VSUBFP },
0ac081f6
AH		 5626 { MASK_ALTIVEC, CODE_FOR_altivec_vsubcuw, "__builtin_altivec_vsubcuw", ALTIVEC_BUILTIN_VSUBCUW },
5627 { MASK_ALTIVEC, CODE_FOR_altivec_vsububs, "__builtin_altivec_vsububs", ALTIVEC_BUILTIN_VSUBUBS },
5628 { MASK_ALTIVEC, CODE_FOR_altivec_vsubsbs, "__builtin_altivec_vsubsbs", ALTIVEC_BUILTIN_VSUBSBS },
5629 { MASK_ALTIVEC, CODE_FOR_altivec_vsubuhs, "__builtin_altivec_vsubuhs", ALTIVEC_BUILTIN_VSUBUHS },
5630 { MASK_ALTIVEC, CODE_FOR_altivec_vsubshs, "__builtin_altivec_vsubshs", ALTIVEC_BUILTIN_VSUBSHS },
5631 { MASK_ALTIVEC, CODE_FOR_altivec_vsubuws, "__builtin_altivec_vsubuws", ALTIVEC_BUILTIN_VSUBUWS },
5632 { MASK_ALTIVEC, CODE_FOR_altivec_vsubsws, "__builtin_altivec_vsubsws", ALTIVEC_BUILTIN_VSUBSWS },
5633 { MASK_ALTIVEC, CODE_FOR_altivec_vsum4ubs, "__builtin_altivec_vsum4ubs", ALTIVEC_BUILTIN_VSUM4UBS },
5634 { MASK_ALTIVEC, CODE_FOR_altivec_vsum4sbs, "__builtin_altivec_vsum4sbs", ALTIVEC_BUILTIN_VSUM4SBS },
5635 { MASK_ALTIVEC, CODE_FOR_altivec_vsum4shs, "__builtin_altivec_vsum4shs", ALTIVEC_BUILTIN_VSUM4SHS },
5636 { MASK_ALTIVEC, CODE_FOR_altivec_vsum2sws, "__builtin_altivec_vsum2sws", ALTIVEC_BUILTIN_VSUM2SWS },
5637 { MASK_ALTIVEC, CODE_FOR_altivec_vsumsws, "__builtin_altivec_vsumsws", ALTIVEC_BUILTIN_VSUMSWS },
f18c054f 5638 { MASK_ALTIVEC, CODE_FOR_xorv4si3, "__builtin_altivec_vxor", ALTIVEC_BUILTIN_VXOR },
a3170dc6
AH		 5639
5640 /* Place holder, leave as first spe builtin. */
5641 { 0, CODE_FOR_spe_evaddw, "__builtin_spe_evaddw", SPE_BUILTIN_EVADDW },
5642 { 0, CODE_FOR_spe_evand, "__builtin_spe_evand", SPE_BUILTIN_EVAND },
5643 { 0, CODE_FOR_spe_evandc, "__builtin_spe_evandc", SPE_BUILTIN_EVANDC },
5644 { 0, CODE_FOR_spe_evdivws, "__builtin_spe_evdivws", SPE_BUILTIN_EVDIVWS },
5645 { 0, CODE_FOR_spe_evdivwu, "__builtin_spe_evdivwu", SPE_BUILTIN_EVDIVWU },
5646 { 0, CODE_FOR_spe_eveqv, "__builtin_spe_eveqv", SPE_BUILTIN_EVEQV },
5647 { 0, CODE_FOR_spe_evfsadd, "__builtin_spe_evfsadd", SPE_BUILTIN_EVFSADD },
5648 { 0, CODE_FOR_spe_evfsdiv, "__builtin_spe_evfsdiv", SPE_BUILTIN_EVFSDIV },
5649 { 0, CODE_FOR_spe_evfsmul, "__builtin_spe_evfsmul", SPE_BUILTIN_EVFSMUL },
5650 { 0, CODE_FOR_spe_evfssub, "__builtin_spe_evfssub", SPE_BUILTIN_EVFSSUB },
5651 { 0, CODE_FOR_spe_evmergehi, "__builtin_spe_evmergehi", SPE_BUILTIN_EVMERGEHI },
5652 { 0, CODE_FOR_spe_evmergehilo, "__builtin_spe_evmergehilo", SPE_BUILTIN_EVMERGEHILO },
5653 { 0, CODE_FOR_spe_evmergelo, "__builtin_spe_evmergelo", SPE_BUILTIN_EVMERGELO },
5654 { 0, CODE_FOR_spe_evmergelohi, "__builtin_spe_evmergelohi", SPE_BUILTIN_EVMERGELOHI },
5655 { 0, CODE_FOR_spe_evmhegsmfaa, "__builtin_spe_evmhegsmfaa", SPE_BUILTIN_EVMHEGSMFAA },
5656 { 0, CODE_FOR_spe_evmhegsmfan, "__builtin_spe_evmhegsmfan", SPE_BUILTIN_EVMHEGSMFAN },
5657 { 0, CODE_FOR_spe_evmhegsmiaa, "__builtin_spe_evmhegsmiaa", SPE_BUILTIN_EVMHEGSMIAA },
5658 { 0, CODE_FOR_spe_evmhegsmian, "__builtin_spe_evmhegsmian", SPE_BUILTIN_EVMHEGSMIAN },
5659 { 0, CODE_FOR_spe_evmhegumiaa, "__builtin_spe_evmhegumiaa", SPE_BUILTIN_EVMHEGUMIAA },
5660 { 0, CODE_FOR_spe_evmhegumian, "__builtin_spe_evmhegumian", SPE_BUILTIN_EVMHEGUMIAN },
5661 { 0, CODE_FOR_spe_evmhesmf, "__builtin_spe_evmhesmf", SPE_BUILTIN_EVMHESMF },
5662 { 0, CODE_FOR_spe_evmhesmfa, "__builtin_spe_evmhesmfa", SPE_BUILTIN_EVMHESMFA },
5663 { 0, CODE_FOR_spe_evmhesmfaaw, "__builtin_spe_evmhesmfaaw", SPE_BUILTIN_EVMHESMFAAW },
5664 { 0, CODE_FOR_spe_evmhesmfanw, "__builtin_spe_evmhesmfanw", SPE_BUILTIN_EVMHESMFANW },
5665 { 0, CODE_FOR_spe_evmhesmi, "__builtin_spe_evmhesmi", SPE_BUILTIN_EVMHESMI },
5666 { 0, CODE_FOR_spe_evmhesmia, "__builtin_spe_evmhesmia", SPE_BUILTIN_EVMHESMIA },
5667 { 0, CODE_FOR_spe_evmhesmiaaw, "__builtin_spe_evmhesmiaaw", SPE_BUILTIN_EVMHESMIAAW },
5668 { 0, CODE_FOR_spe_evmhesmianw, "__builtin_spe_evmhesmianw", SPE_BUILTIN_EVMHESMIANW },
5669 { 0, CODE_FOR_spe_evmhessf, "__builtin_spe_evmhessf", SPE_BUILTIN_EVMHESSF },
5670 { 0, CODE_FOR_spe_evmhessfa, "__builtin_spe_evmhessfa", SPE_BUILTIN_EVMHESSFA },
5671 { 0, CODE_FOR_spe_evmhessfaaw, "__builtin_spe_evmhessfaaw", SPE_BUILTIN_EVMHESSFAAW },
5672 { 0, CODE_FOR_spe_evmhessfanw, "__builtin_spe_evmhessfanw", SPE_BUILTIN_EVMHESSFANW },
5673 { 0, CODE_FOR_spe_evmhessiaaw, "__builtin_spe_evmhessiaaw", SPE_BUILTIN_EVMHESSIAAW },
5674 { 0, CODE_FOR_spe_evmhessianw, "__builtin_spe_evmhessianw", SPE_BUILTIN_EVMHESSIANW },
5675 { 0, CODE_FOR_spe_evmheumi, "__builtin_spe_evmheumi", SPE_BUILTIN_EVMHEUMI },
5676 { 0, CODE_FOR_spe_evmheumia, "__builtin_spe_evmheumia", SPE_BUILTIN_EVMHEUMIA },
5677 { 0, CODE_FOR_spe_evmheumiaaw, "__builtin_spe_evmheumiaaw", SPE_BUILTIN_EVMHEUMIAAW },
5678 { 0, CODE_FOR_spe_evmheumianw, "__builtin_spe_evmheumianw", SPE_BUILTIN_EVMHEUMIANW },
5679 { 0, CODE_FOR_spe_evmheusiaaw, "__builtin_spe_evmheusiaaw", SPE_BUILTIN_EVMHEUSIAAW },
5680 { 0, CODE_FOR_spe_evmheusianw, "__builtin_spe_evmheusianw", SPE_BUILTIN_EVMHEUSIANW },
5681 { 0, CODE_FOR_spe_evmhogsmfaa, "__builtin_spe_evmhogsmfaa", SPE_BUILTIN_EVMHOGSMFAA },
5682 { 0, CODE_FOR_spe_evmhogsmfan, "__builtin_spe_evmhogsmfan", SPE_BUILTIN_EVMHOGSMFAN },
5683 { 0, CODE_FOR_spe_evmhogsmiaa, "__builtin_spe_evmhogsmiaa", SPE_BUILTIN_EVMHOGSMIAA },
5684 { 0, CODE_FOR_spe_evmhogsmian, "__builtin_spe_evmhogsmian", SPE_BUILTIN_EVMHOGSMIAN },
5685 { 0, CODE_FOR_spe_evmhogumiaa, "__builtin_spe_evmhogumiaa", SPE_BUILTIN_EVMHOGUMIAA },
5686 { 0, CODE_FOR_spe_evmhogumian, "__builtin_spe_evmhogumian", SPE_BUILTIN_EVMHOGUMIAN },
5687 { 0, CODE_FOR_spe_evmhosmf, "__builtin_spe_evmhosmf", SPE_BUILTIN_EVMHOSMF },
5688 { 0, CODE_FOR_spe_evmhosmfa, "__builtin_spe_evmhosmfa", SPE_BUILTIN_EVMHOSMFA },
5689 { 0, CODE_FOR_spe_evmhosmfaaw, "__builtin_spe_evmhosmfaaw", SPE_BUILTIN_EVMHOSMFAAW },
5690 { 0, CODE_FOR_spe_evmhosmfanw, "__builtin_spe_evmhosmfanw", SPE_BUILTIN_EVMHOSMFANW },
5691 { 0, CODE_FOR_spe_evmhosmi, "__builtin_spe_evmhosmi", SPE_BUILTIN_EVMHOSMI },
5692 { 0, CODE_FOR_spe_evmhosmia, "__builtin_spe_evmhosmia", SPE_BUILTIN_EVMHOSMIA },
5693 { 0, CODE_FOR_spe_evmhosmiaaw, "__builtin_spe_evmhosmiaaw", SPE_BUILTIN_EVMHOSMIAAW },
5694 { 0, CODE_FOR_spe_evmhosmianw, "__builtin_spe_evmhosmianw", SPE_BUILTIN_EVMHOSMIANW },
5695 { 0, CODE_FOR_spe_evmhossf, "__builtin_spe_evmhossf", SPE_BUILTIN_EVMHOSSF },
5696 { 0, CODE_FOR_spe_evmhossfa, "__builtin_spe_evmhossfa", SPE_BUILTIN_EVMHOSSFA },
5697 { 0, CODE_FOR_spe_evmhossfaaw, "__builtin_spe_evmhossfaaw", SPE_BUILTIN_EVMHOSSFAAW },
5698 { 0, CODE_FOR_spe_evmhossfanw, "__builtin_spe_evmhossfanw", SPE_BUILTIN_EVMHOSSFANW },
5699 { 0, CODE_FOR_spe_evmhossiaaw, "__builtin_spe_evmhossiaaw", SPE_BUILTIN_EVMHOSSIAAW },
5700 { 0, CODE_FOR_spe_evmhossianw, "__builtin_spe_evmhossianw", SPE_BUILTIN_EVMHOSSIANW },
5701 { 0, CODE_FOR_spe_evmhoumi, "__builtin_spe_evmhoumi", SPE_BUILTIN_EVMHOUMI },
5702 { 0, CODE_FOR_spe_evmhoumia, "__builtin_spe_evmhoumia", SPE_BUILTIN_EVMHOUMIA },
5703 { 0, CODE_FOR_spe_evmhoumiaaw, "__builtin_spe_evmhoumiaaw", SPE_BUILTIN_EVMHOUMIAAW },
5704 { 0, CODE_FOR_spe_evmhoumianw, "__builtin_spe_evmhoumianw", SPE_BUILTIN_EVMHOUMIANW },
5705 { 0, CODE_FOR_spe_evmhousiaaw, "__builtin_spe_evmhousiaaw", SPE_BUILTIN_EVMHOUSIAAW },
5706 { 0, CODE_FOR_spe_evmhousianw, "__builtin_spe_evmhousianw", SPE_BUILTIN_EVMHOUSIANW },
5707 { 0, CODE_FOR_spe_evmwhsmf, "__builtin_spe_evmwhsmf", SPE_BUILTIN_EVMWHSMF },
5708 { 0, CODE_FOR_spe_evmwhsmfa, "__builtin_spe_evmwhsmfa", SPE_BUILTIN_EVMWHSMFA },
5709 { 0, CODE_FOR_spe_evmwhsmi, "__builtin_spe_evmwhsmi", SPE_BUILTIN_EVMWHSMI },
5710 { 0, CODE_FOR_spe_evmwhsmia, "__builtin_spe_evmwhsmia", SPE_BUILTIN_EVMWHSMIA },
5711 { 0, CODE_FOR_spe_evmwhssf, "__builtin_spe_evmwhssf", SPE_BUILTIN_EVMWHSSF },
5712 { 0, CODE_FOR_spe_evmwhssfa, "__builtin_spe_evmwhssfa", SPE_BUILTIN_EVMWHSSFA },
5713 { 0, CODE_FOR_spe_evmwhumi, "__builtin_spe_evmwhumi", SPE_BUILTIN_EVMWHUMI },
5714 { 0, CODE_FOR_spe_evmwhumia, "__builtin_spe_evmwhumia", SPE_BUILTIN_EVMWHUMIA },
a3170dc6
AH		 5715 { 0, CODE_FOR_spe_evmwlsmiaaw, "__builtin_spe_evmwlsmiaaw", SPE_BUILTIN_EVMWLSMIAAW },
5716 { 0, CODE_FOR_spe_evmwlsmianw, "__builtin_spe_evmwlsmianw", SPE_BUILTIN_EVMWLSMIANW },
a3170dc6
AH		 5717 { 0, CODE_FOR_spe_evmwlssiaaw, "__builtin_spe_evmwlssiaaw", SPE_BUILTIN_EVMWLSSIAAW },
5718 { 0, CODE_FOR_spe_evmwlssianw, "__builtin_spe_evmwlssianw", SPE_BUILTIN_EVMWLSSIANW },
5719 { 0, CODE_FOR_spe_evmwlumi, "__builtin_spe_evmwlumi", SPE_BUILTIN_EVMWLUMI },
5720 { 0, CODE_FOR_spe_evmwlumia, "__builtin_spe_evmwlumia", SPE_BUILTIN_EVMWLUMIA },
5721 { 0, CODE_FOR_spe_evmwlumiaaw, "__builtin_spe_evmwlumiaaw", SPE_BUILTIN_EVMWLUMIAAW },
5722 { 0, CODE_FOR_spe_evmwlumianw, "__builtin_spe_evmwlumianw", SPE_BUILTIN_EVMWLUMIANW },
5723 { 0, CODE_FOR_spe_evmwlusiaaw, "__builtin_spe_evmwlusiaaw", SPE_BUILTIN_EVMWLUSIAAW },
5724 { 0, CODE_FOR_spe_evmwlusianw, "__builtin_spe_evmwlusianw", SPE_BUILTIN_EVMWLUSIANW },
5725 { 0, CODE_FOR_spe_evmwsmf, "__builtin_spe_evmwsmf", SPE_BUILTIN_EVMWSMF },
5726 { 0, CODE_FOR_spe_evmwsmfa, "__builtin_spe_evmwsmfa", SPE_BUILTIN_EVMWSMFA },
5727 { 0, CODE_FOR_spe_evmwsmfaa, "__builtin_spe_evmwsmfaa", SPE_BUILTIN_EVMWSMFAA },
5728 { 0, CODE_FOR_spe_evmwsmfan, "__builtin_spe_evmwsmfan", SPE_BUILTIN_EVMWSMFAN },
5729 { 0, CODE_FOR_spe_evmwsmi, "__builtin_spe_evmwsmi", SPE_BUILTIN_EVMWSMI },
5730 { 0, CODE_FOR_spe_evmwsmia, "__builtin_spe_evmwsmia", SPE_BUILTIN_EVMWSMIA },
5731 { 0, CODE_FOR_spe_evmwsmiaa, "__builtin_spe_evmwsmiaa", SPE_BUILTIN_EVMWSMIAA },
5732 { 0, CODE_FOR_spe_evmwsmian, "__builtin_spe_evmwsmian", SPE_BUILTIN_EVMWSMIAN },
5733 { 0, CODE_FOR_spe_evmwssf, "__builtin_spe_evmwssf", SPE_BUILTIN_EVMWSSF },
5734 { 0, CODE_FOR_spe_evmwssfa, "__builtin_spe_evmwssfa", SPE_BUILTIN_EVMWSSFA },
5735 { 0, CODE_FOR_spe_evmwssfaa, "__builtin_spe_evmwssfaa", SPE_BUILTIN_EVMWSSFAA },
5736 { 0, CODE_FOR_spe_evmwssfan, "__builtin_spe_evmwssfan", SPE_BUILTIN_EVMWSSFAN },
5737 { 0, CODE_FOR_spe_evmwumi, "__builtin_spe_evmwumi", SPE_BUILTIN_EVMWUMI },
5738 { 0, CODE_FOR_spe_evmwumia, "__builtin_spe_evmwumia", SPE_BUILTIN_EVMWUMIA },
5739 { 0, CODE_FOR_spe_evmwumiaa, "__builtin_spe_evmwumiaa", SPE_BUILTIN_EVMWUMIAA },
5740 { 0, CODE_FOR_spe_evmwumian, "__builtin_spe_evmwumian", SPE_BUILTIN_EVMWUMIAN },
5741 { 0, CODE_FOR_spe_evnand, "__builtin_spe_evnand", SPE_BUILTIN_EVNAND },
5742 { 0, CODE_FOR_spe_evnor, "__builtin_spe_evnor", SPE_BUILTIN_EVNOR },
5743 { 0, CODE_FOR_spe_evor, "__builtin_spe_evor", SPE_BUILTIN_EVOR },
5744 { 0, CODE_FOR_spe_evorc, "__builtin_spe_evorc", SPE_BUILTIN_EVORC },
5745 { 0, CODE_FOR_spe_evrlw, "__builtin_spe_evrlw", SPE_BUILTIN_EVRLW },
5746 { 0, CODE_FOR_spe_evslw, "__builtin_spe_evslw", SPE_BUILTIN_EVSLW },
5747 { 0, CODE_FOR_spe_evsrws, "__builtin_spe_evsrws", SPE_BUILTIN_EVSRWS },
5748 { 0, CODE_FOR_spe_evsrwu, "__builtin_spe_evsrwu", SPE_BUILTIN_EVSRWU },
5749 { 0, CODE_FOR_spe_evsubfw, "__builtin_spe_evsubfw", SPE_BUILTIN_EVSUBFW },
5750
5751 /* SPE binary operations expecting a 5-bit unsigned literal. */
5752 { 0, CODE_FOR_spe_evaddiw, "__builtin_spe_evaddiw", SPE_BUILTIN_EVADDIW },
5753
5754 { 0, CODE_FOR_spe_evrlwi, "__builtin_spe_evrlwi", SPE_BUILTIN_EVRLWI },
5755 { 0, CODE_FOR_spe_evslwi, "__builtin_spe_evslwi", SPE_BUILTIN_EVSLWI },
5756 { 0, CODE_FOR_spe_evsrwis, "__builtin_spe_evsrwis", SPE_BUILTIN_EVSRWIS },
5757 { 0, CODE_FOR_spe_evsrwiu, "__builtin_spe_evsrwiu", SPE_BUILTIN_EVSRWIU },
5758 { 0, CODE_FOR_spe_evsubifw, "__builtin_spe_evsubifw", SPE_BUILTIN_EVSUBIFW },
5759 { 0, CODE_FOR_spe_evmwhssfaa, "__builtin_spe_evmwhssfaa", SPE_BUILTIN_EVMWHSSFAA },
5760 { 0, CODE_FOR_spe_evmwhssmaa, "__builtin_spe_evmwhssmaa", SPE_BUILTIN_EVMWHSSMAA },
5761 { 0, CODE_FOR_spe_evmwhsmfaa, "__builtin_spe_evmwhsmfaa", SPE_BUILTIN_EVMWHSMFAA },
5762 { 0, CODE_FOR_spe_evmwhsmiaa, "__builtin_spe_evmwhsmiaa", SPE_BUILTIN_EVMWHSMIAA },
5763 { 0, CODE_FOR_spe_evmwhusiaa, "__builtin_spe_evmwhusiaa", SPE_BUILTIN_EVMWHUSIAA },
5764 { 0, CODE_FOR_spe_evmwhumiaa, "__builtin_spe_evmwhumiaa", SPE_BUILTIN_EVMWHUMIAA },
5765 { 0, CODE_FOR_spe_evmwhssfan, "__builtin_spe_evmwhssfan", SPE_BUILTIN_EVMWHSSFAN },
5766 { 0, CODE_FOR_spe_evmwhssian, "__builtin_spe_evmwhssian", SPE_BUILTIN_EVMWHSSIAN },
5767 { 0, CODE_FOR_spe_evmwhsmfan, "__builtin_spe_evmwhsmfan", SPE_BUILTIN_EVMWHSMFAN },
5768 { 0, CODE_FOR_spe_evmwhsmian, "__builtin_spe_evmwhsmian", SPE_BUILTIN_EVMWHSMIAN },
5769 { 0, CODE_FOR_spe_evmwhusian, "__builtin_spe_evmwhusian", SPE_BUILTIN_EVMWHUSIAN },
5770 { 0, CODE_FOR_spe_evmwhumian, "__builtin_spe_evmwhumian", SPE_BUILTIN_EVMWHUMIAN },
5771 { 0, CODE_FOR_spe_evmwhgssfaa, "__builtin_spe_evmwhgssfaa", SPE_BUILTIN_EVMWHGSSFAA },
5772 { 0, CODE_FOR_spe_evmwhgsmfaa, "__builtin_spe_evmwhgsmfaa", SPE_BUILTIN_EVMWHGSMFAA },
5773 { 0, CODE_FOR_spe_evmwhgsmiaa, "__builtin_spe_evmwhgsmiaa", SPE_BUILTIN_EVMWHGSMIAA },
5774 { 0, CODE_FOR_spe_evmwhgumiaa, "__builtin_spe_evmwhgumiaa", SPE_BUILTIN_EVMWHGUMIAA },
5775 { 0, CODE_FOR_spe_evmwhgssfan, "__builtin_spe_evmwhgssfan", SPE_BUILTIN_EVMWHGSSFAN },
5776 { 0, CODE_FOR_spe_evmwhgsmfan, "__builtin_spe_evmwhgsmfan", SPE_BUILTIN_EVMWHGSMFAN },
5777 { 0, CODE_FOR_spe_evmwhgsmian, "__builtin_spe_evmwhgsmian", SPE_BUILTIN_EVMWHGSMIAN },
5778 { 0, CODE_FOR_spe_evmwhgumian, "__builtin_spe_evmwhgumian", SPE_BUILTIN_EVMWHGUMIAN },
5779 { 0, CODE_FOR_spe_brinc, "__builtin_spe_brinc", SPE_BUILTIN_BRINC },
5780
5781 /* Place-holder. Leave as last binary SPE builtin. */
17edbda5 5782 { 0, CODE_FOR_xorv2si3, "__builtin_spe_evxor", SPE_BUILTIN_EVXOR },
ae4b4a02
AH		 5783};
5784
5785/* AltiVec predicates. */
5786
5787struct builtin_description_predicates
5788{
5789 const unsigned int mask;
5790 const enum insn_code icode;
5791 const char *opcode;
5792 const char *const name;
5793 const enum rs6000_builtins code;
5794};
5795
5796static const struct builtin_description_predicates bdesc_altivec_preds[] =
5797{
5798 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpbfp.", "__builtin_altivec_vcmpbfp_p", ALTIVEC_BUILTIN_VCMPBFP_P },
5799 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpeqfp.", "__builtin_altivec_vcmpeqfp_p", ALTIVEC_BUILTIN_VCMPEQFP_P },
5800 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpgefp.", "__builtin_altivec_vcmpgefp_p", ALTIVEC_BUILTIN_VCMPGEFP_P },
5801 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpgtfp.", "__builtin_altivec_vcmpgtfp_p", ALTIVEC_BUILTIN_VCMPGTFP_P },
5802 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpequw.", "__builtin_altivec_vcmpequw_p", ALTIVEC_BUILTIN_VCMPEQUW_P },
5803 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpgtsw.", "__builtin_altivec_vcmpgtsw_p", ALTIVEC_BUILTIN_VCMPGTSW_P },
5804 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpgtuw.", "__builtin_altivec_vcmpgtuw_p", ALTIVEC_BUILTIN_VCMPGTUW_P },
5805 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpgtuh.", "__builtin_altivec_vcmpgtuh_p", ALTIVEC_BUILTIN_VCMPGTUH_P },
5806 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpgtsh.", "__builtin_altivec_vcmpgtsh_p", ALTIVEC_BUILTIN_VCMPGTSH_P },
5807 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpequh.", "__builtin_altivec_vcmpequh_p", ALTIVEC_BUILTIN_VCMPEQUH_P },
5808 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpequb.", "__builtin_altivec_vcmpequb_p", ALTIVEC_BUILTIN_VCMPEQUB_P },
5809 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpgtsb.", "__builtin_altivec_vcmpgtsb_p", ALTIVEC_BUILTIN_VCMPGTSB_P },
5810 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpgtub.", "__builtin_altivec_vcmpgtub_p", ALTIVEC_BUILTIN_VCMPGTUB_P }
0ac081f6 5811};
24408032 5812
a3170dc6
AH		 5813/* SPE predicates. */
5814static struct builtin_description bdesc_spe_predicates[] =
5815{
5816 /* Place-holder. Leave as first. */
5817 { 0, CODE_FOR_spe_evcmpeq, "__builtin_spe_evcmpeq", SPE_BUILTIN_EVCMPEQ },
5818 { 0, CODE_FOR_spe_evcmpgts, "__builtin_spe_evcmpgts", SPE_BUILTIN_EVCMPGTS },
5819 { 0, CODE_FOR_spe_evcmpgtu, "__builtin_spe_evcmpgtu", SPE_BUILTIN_EVCMPGTU },
5820 { 0, CODE_FOR_spe_evcmplts, "__builtin_spe_evcmplts", SPE_BUILTIN_EVCMPLTS },
5821 { 0, CODE_FOR_spe_evcmpltu, "__builtin_spe_evcmpltu", SPE_BUILTIN_EVCMPLTU },
5822 { 0, CODE_FOR_spe_evfscmpeq, "__builtin_spe_evfscmpeq", SPE_BUILTIN_EVFSCMPEQ },
5823 { 0, CODE_FOR_spe_evfscmpgt, "__builtin_spe_evfscmpgt", SPE_BUILTIN_EVFSCMPGT },
5824 { 0, CODE_FOR_spe_evfscmplt, "__builtin_spe_evfscmplt", SPE_BUILTIN_EVFSCMPLT },
5825 { 0, CODE_FOR_spe_evfststeq, "__builtin_spe_evfststeq", SPE_BUILTIN_EVFSTSTEQ },
5826 { 0, CODE_FOR_spe_evfststgt, "__builtin_spe_evfststgt", SPE_BUILTIN_EVFSTSTGT },
5827 /* Place-holder. Leave as last. */
5828 { 0, CODE_FOR_spe_evfststlt, "__builtin_spe_evfststlt", SPE_BUILTIN_EVFSTSTLT },
5829};
5830
5831/* SPE evsel predicates. */
5832static struct builtin_description bdesc_spe_evsel[] =
5833{
5834 /* Place-holder. Leave as first. */
5835 { 0, CODE_FOR_spe_evcmpgts, "__builtin_spe_evsel_gts", SPE_BUILTIN_EVSEL_CMPGTS },
5836 { 0, CODE_FOR_spe_evcmpgtu, "__builtin_spe_evsel_gtu", SPE_BUILTIN_EVSEL_CMPGTU },
5837 { 0, CODE_FOR_spe_evcmplts, "__builtin_spe_evsel_lts", SPE_BUILTIN_EVSEL_CMPLTS },
5838 { 0, CODE_FOR_spe_evcmpltu, "__builtin_spe_evsel_ltu", SPE_BUILTIN_EVSEL_CMPLTU },
5839 { 0, CODE_FOR_spe_evcmpeq, "__builtin_spe_evsel_eq", SPE_BUILTIN_EVSEL_CMPEQ },
5840 { 0, CODE_FOR_spe_evfscmpgt, "__builtin_spe_evsel_fsgt", SPE_BUILTIN_EVSEL_FSCMPGT },
5841 { 0, CODE_FOR_spe_evfscmplt, "__builtin_spe_evsel_fslt", SPE_BUILTIN_EVSEL_FSCMPLT },
5842 { 0, CODE_FOR_spe_evfscmpeq, "__builtin_spe_evsel_fseq", SPE_BUILTIN_EVSEL_FSCMPEQ },
5843 { 0, CODE_FOR_spe_evfststgt, "__builtin_spe_evsel_fststgt", SPE_BUILTIN_EVSEL_FSTSTGT },
5844 { 0, CODE_FOR_spe_evfststlt, "__builtin_spe_evsel_fststlt", SPE_BUILTIN_EVSEL_FSTSTLT },
5845 /* Place-holder. Leave as last. */
5846 { 0, CODE_FOR_spe_evfststeq, "__builtin_spe_evsel_fststeq", SPE_BUILTIN_EVSEL_FSTSTEQ },
5847};
5848
b6d08ca1 5849/* ABS* operations. */
100c4561
AH		 5850
5851static const struct builtin_description bdesc_abs[] =
5852{
5853 { MASK_ALTIVEC, CODE_FOR_absv4si2, "__builtin_altivec_abs_v4si", ALTIVEC_BUILTIN_ABS_V4SI },
5854 { MASK_ALTIVEC, CODE_FOR_absv8hi2, "__builtin_altivec_abs_v8hi", ALTIVEC_BUILTIN_ABS_V8HI },
5855 { MASK_ALTIVEC, CODE_FOR_absv4sf2, "__builtin_altivec_abs_v4sf", ALTIVEC_BUILTIN_ABS_V4SF },
5856 { MASK_ALTIVEC, CODE_FOR_absv16qi2, "__builtin_altivec_abs_v16qi", ALTIVEC_BUILTIN_ABS_V16QI },
5857 { MASK_ALTIVEC, CODE_FOR_altivec_abss_v4si, "__builtin_altivec_abss_v4si", ALTIVEC_BUILTIN_ABSS_V4SI },
5858 { MASK_ALTIVEC, CODE_FOR_altivec_abss_v8hi, "__builtin_altivec_abss_v8hi", ALTIVEC_BUILTIN_ABSS_V8HI },
5859 { MASK_ALTIVEC, CODE_FOR_altivec_abss_v16qi, "__builtin_altivec_abss_v16qi", ALTIVEC_BUILTIN_ABSS_V16QI }
5860};
5861
617e0e1d
DB		 5862/* Simple unary operations: VECb = foo (unsigned literal) or VECb =
5863 foo (VECa). */
24408032 5864
a3170dc6 5865static struct builtin_description bdesc_1arg[] =
2212663f 5866{
617e0e1d
DB		 5867 { MASK_ALTIVEC, CODE_FOR_altivec_vexptefp, "__builtin_altivec_vexptefp", ALTIVEC_BUILTIN_VEXPTEFP },
5868 { MASK_ALTIVEC, CODE_FOR_altivec_vlogefp, "__builtin_altivec_vlogefp", ALTIVEC_BUILTIN_VLOGEFP },
5869 { MASK_ALTIVEC, CODE_FOR_altivec_vrefp, "__builtin_altivec_vrefp", ALTIVEC_BUILTIN_VREFP },
5870 { MASK_ALTIVEC, CODE_FOR_altivec_vrfim, "__builtin_altivec_vrfim", ALTIVEC_BUILTIN_VRFIM },
5871 { MASK_ALTIVEC, CODE_FOR_altivec_vrfin, "__builtin_altivec_vrfin", ALTIVEC_BUILTIN_VRFIN },
5872 { MASK_ALTIVEC, CODE_FOR_altivec_vrfip, "__builtin_altivec_vrfip", ALTIVEC_BUILTIN_VRFIP },
5873 { MASK_ALTIVEC, CODE_FOR_ftruncv4sf2, "__builtin_altivec_vrfiz", ALTIVEC_BUILTIN_VRFIZ },
5874 { MASK_ALTIVEC, CODE_FOR_altivec_vrsqrtefp, "__builtin_altivec_vrsqrtefp", ALTIVEC_BUILTIN_VRSQRTEFP },
2212663f
DB		 5875 { MASK_ALTIVEC, CODE_FOR_altivec_vspltisb, "__builtin_altivec_vspltisb", ALTIVEC_BUILTIN_VSPLTISB },
5876 { MASK_ALTIVEC, CODE_FOR_altivec_vspltish, "__builtin_altivec_vspltish", ALTIVEC_BUILTIN_VSPLTISH },
5877 { MASK_ALTIVEC, CODE_FOR_altivec_vspltisw, "__builtin_altivec_vspltisw", ALTIVEC_BUILTIN_VSPLTISW },
20e26713
AH		 5878 { MASK_ALTIVEC, CODE_FOR_altivec_vupkhsb, "__builtin_altivec_vupkhsb", ALTIVEC_BUILTIN_VUPKHSB },
5879 { MASK_ALTIVEC, CODE_FOR_altivec_vupkhpx, "__builtin_altivec_vupkhpx", ALTIVEC_BUILTIN_VUPKHPX },
5880 { MASK_ALTIVEC, CODE_FOR_altivec_vupkhsh, "__builtin_altivec_vupkhsh", ALTIVEC_BUILTIN_VUPKHSH },
5881 { MASK_ALTIVEC, CODE_FOR_altivec_vupklsb, "__builtin_altivec_vupklsb", ALTIVEC_BUILTIN_VUPKLSB },
5882 { MASK_ALTIVEC, CODE_FOR_altivec_vupklpx, "__builtin_altivec_vupklpx", ALTIVEC_BUILTIN_VUPKLPX },
5883 { MASK_ALTIVEC, CODE_FOR_altivec_vupklsh, "__builtin_altivec_vupklsh", ALTIVEC_BUILTIN_VUPKLSH },
a3170dc6
AH		 5884
5885 /* The SPE unary builtins must start with SPE_BUILTIN_EVABS and
5886 end with SPE_BUILTIN_EVSUBFUSIAAW. */
5887 { 0, CODE_FOR_spe_evabs, "__builtin_spe_evabs", SPE_BUILTIN_EVABS },
5888 { 0, CODE_FOR_spe_evaddsmiaaw, "__builtin_spe_evaddsmiaaw", SPE_BUILTIN_EVADDSMIAAW },
5889 { 0, CODE_FOR_spe_evaddssiaaw, "__builtin_spe_evaddssiaaw", SPE_BUILTIN_EVADDSSIAAW },
5890 { 0, CODE_FOR_spe_evaddumiaaw, "__builtin_spe_evaddumiaaw", SPE_BUILTIN_EVADDUMIAAW },
5891 { 0, CODE_FOR_spe_evaddusiaaw, "__builtin_spe_evaddusiaaw", SPE_BUILTIN_EVADDUSIAAW },
5892 { 0, CODE_FOR_spe_evcntlsw, "__builtin_spe_evcntlsw", SPE_BUILTIN_EVCNTLSW },
5893 { 0, CODE_FOR_spe_evcntlzw, "__builtin_spe_evcntlzw", SPE_BUILTIN_EVCNTLZW },
5894 { 0, CODE_FOR_spe_evextsb, "__builtin_spe_evextsb", SPE_BUILTIN_EVEXTSB },
5895 { 0, CODE_FOR_spe_evextsh, "__builtin_spe_evextsh", SPE_BUILTIN_EVEXTSH },
5896 { 0, CODE_FOR_spe_evfsabs, "__builtin_spe_evfsabs", SPE_BUILTIN_EVFSABS },
5897 { 0, CODE_FOR_spe_evfscfsf, "__builtin_spe_evfscfsf", SPE_BUILTIN_EVFSCFSF },
5898 { 0, CODE_FOR_spe_evfscfsi, "__builtin_spe_evfscfsi", SPE_BUILTIN_EVFSCFSI },
5899 { 0, CODE_FOR_spe_evfscfuf, "__builtin_spe_evfscfuf", SPE_BUILTIN_EVFSCFUF },
5900 { 0, CODE_FOR_spe_evfscfui, "__builtin_spe_evfscfui", SPE_BUILTIN_EVFSCFUI },
5901 { 0, CODE_FOR_spe_evfsctsf, "__builtin_spe_evfsctsf", SPE_BUILTIN_EVFSCTSF },
5902 { 0, CODE_FOR_spe_evfsctsi, "__builtin_spe_evfsctsi", SPE_BUILTIN_EVFSCTSI },
5903 { 0, CODE_FOR_spe_evfsctsiz, "__builtin_spe_evfsctsiz", SPE_BUILTIN_EVFSCTSIZ },
5904 { 0, CODE_FOR_spe_evfsctuf, "__builtin_spe_evfsctuf", SPE_BUILTIN_EVFSCTUF },
5905 { 0, CODE_FOR_spe_evfsctui, "__builtin_spe_evfsctui", SPE_BUILTIN_EVFSCTUI },
5906 { 0, CODE_FOR_spe_evfsctuiz, "__builtin_spe_evfsctuiz", SPE_BUILTIN_EVFSCTUIZ },
5907 { 0, CODE_FOR_spe_evfsnabs, "__builtin_spe_evfsnabs", SPE_BUILTIN_EVFSNABS },
5908 { 0, CODE_FOR_spe_evfsneg, "__builtin_spe_evfsneg", SPE_BUILTIN_EVFSNEG },
5909 { 0, CODE_FOR_spe_evmra, "__builtin_spe_evmra", SPE_BUILTIN_EVMRA },
6a599451 5910 { 0, CODE_FOR_negv2si2, "__builtin_spe_evneg", SPE_BUILTIN_EVNEG },
a3170dc6
AH		 5911 { 0, CODE_FOR_spe_evrndw, "__builtin_spe_evrndw", SPE_BUILTIN_EVRNDW },
5912 { 0, CODE_FOR_spe_evsubfsmiaaw, "__builtin_spe_evsubfsmiaaw", SPE_BUILTIN_EVSUBFSMIAAW },
5913 { 0, CODE_FOR_spe_evsubfssiaaw, "__builtin_spe_evsubfssiaaw", SPE_BUILTIN_EVSUBFSSIAAW },
5914 { 0, CODE_FOR_spe_evsubfumiaaw, "__builtin_spe_evsubfumiaaw", SPE_BUILTIN_EVSUBFUMIAAW },
a3170dc6
AH		 5915
5916 /* Place-holder. Leave as last unary SPE builtin. */
5917 { 0, CODE_FOR_spe_evsubfusiaaw, "__builtin_spe_evsubfusiaaw", SPE_BUILTIN_EVSUBFUSIAAW },
2212663f
DB		 5918};
5919
5920static rtx
a2369ed3 5921rs6000_expand_unop_builtin (enum insn_code icode, tree arglist, rtx target)
2212663f
DB		 5922{
5923 rtx pat;
5924 tree arg0 = TREE_VALUE (arglist);
5925 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
5926 enum machine_mode tmode = insn_data[icode].operand[0].mode;
5927 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
5928
0559cc77
DE		 5929 if (icode == CODE_FOR_nothing)
5930 /* Builtin not supported on this processor. */
5931 return 0;
5932
20e26713
AH		 5933 /* If we got invalid arguments bail out before generating bad rtl. */
5934 if (arg0 == error_mark_node)
9a171fcd 5935 return const0_rtx;
20e26713 5936
0559cc77
DE		 5937 if (icode == CODE_FOR_altivec_vspltisb
5938 || icode == CODE_FOR_altivec_vspltish
5939 || icode == CODE_FOR_altivec_vspltisw
5940 || icode == CODE_FOR_spe_evsplatfi
5941 || icode == CODE_FOR_spe_evsplati)
b44140e7
AH		 5942 {
5943 /* Only allow 5-bit *signed* literals. */
b44140e7
AH		 5944 if (GET_CODE (op0) != CONST_INT
5945 || INTVAL (op0) > 0x1f
5946 || INTVAL (op0) < -0x1f)
5947 {
5948 error ("argument 1 must be a 5-bit signed literal");
9a171fcd 5949 return const0_rtx;
b44140e7 5950 }
b44140e7
AH		 5951 }
5952
c62f2db5 5953 if (target == 0
2212663f
DB		 5954 || GET_MODE (target) != tmode
5955 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
5956 target = gen_reg_rtx (tmode);
5957
5958 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
5959 op0 = copy_to_mode_reg (mode0, op0);
5960
5961 pat = GEN_FCN (icode) (target, op0);
5962 if (! pat)
5963 return 0;
5964 emit_insn (pat);
0ac081f6 5965
2212663f
DB		 5966 return target;
5967}
ae4b4a02 5968
100c4561 5969static rtx
a2369ed3 5970altivec_expand_abs_builtin (enum insn_code icode, tree arglist, rtx target)
100c4561
AH		 5971{
5972 rtx pat, scratch1, scratch2;
5973 tree arg0 = TREE_VALUE (arglist);
5974 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
5975 enum machine_mode tmode = insn_data[icode].operand[0].mode;
5976 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
5977
5978 /* If we have invalid arguments, bail out before generating bad rtl. */
5979 if (arg0 == error_mark_node)
9a171fcd 5980 return const0_rtx;
100c4561
AH		 5981
5982 if (target == 0
5983 || GET_MODE (target) != tmode
5984 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
5985 target = gen_reg_rtx (tmode);
5986
5987 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
5988 op0 = copy_to_mode_reg (mode0, op0);
5989
5990 scratch1 = gen_reg_rtx (mode0);
5991 scratch2 = gen_reg_rtx (mode0);
5992
5993 pat = GEN_FCN (icode) (target, op0, scratch1, scratch2);
5994 if (! pat)
5995 return 0;
5996 emit_insn (pat);
5997
5998 return target;
5999}
6000
0ac081f6 6001static rtx
a2369ed3 6002rs6000_expand_binop_builtin (enum insn_code icode, tree arglist, rtx target)
0ac081f6
AH		 6003{
6004 rtx pat;
6005 tree arg0 = TREE_VALUE (arglist);
6006 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6007 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6008 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6009 enum machine_mode tmode = insn_data[icode].operand[0].mode;
6010 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
6011 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
6012
0559cc77
DE		 6013 if (icode == CODE_FOR_nothing)
6014 /* Builtin not supported on this processor. */
6015 return 0;
6016
20e26713
AH		 6017 /* If we got invalid arguments bail out before generating bad rtl. */
6018 if (arg0 == error_mark_node || arg1 == error_mark_node)
9a171fcd 6019 return const0_rtx;
20e26713 6020
0559cc77
DE		 6021 if (icode == CODE_FOR_altivec_vcfux
6022 || icode == CODE_FOR_altivec_vcfsx
6023 || icode == CODE_FOR_altivec_vctsxs
6024 || icode == CODE_FOR_altivec_vctuxs
6025 || icode == CODE_FOR_altivec_vspltb
6026 || icode == CODE_FOR_altivec_vsplth
6027 || icode == CODE_FOR_altivec_vspltw
6028 || icode == CODE_FOR_spe_evaddiw
6029 || icode == CODE_FOR_spe_evldd
6030 || icode == CODE_FOR_spe_evldh
6031 || icode == CODE_FOR_spe_evldw
6032 || icode == CODE_FOR_spe_evlhhesplat
6033 || icode == CODE_FOR_spe_evlhhossplat
6034 || icode == CODE_FOR_spe_evlhhousplat
6035 || icode == CODE_FOR_spe_evlwhe
6036 || icode == CODE_FOR_spe_evlwhos
6037 || icode == CODE_FOR_spe_evlwhou
6038 || icode == CODE_FOR_spe_evlwhsplat
6039 || icode == CODE_FOR_spe_evlwwsplat
6040 || icode == CODE_FOR_spe_evrlwi
6041 || icode == CODE_FOR_spe_evslwi
6042 || icode == CODE_FOR_spe_evsrwis
f5119d10 6043 || icode == CODE_FOR_spe_evsubifw
0559cc77 6044 || icode == CODE_FOR_spe_evsrwiu)
b44140e7
AH		 6045 {
6046 /* Only allow 5-bit unsigned literals. */
8bb418a3 6047 STRIP_NOPS (arg1);
b44140e7
AH		 6048 if (TREE_CODE (arg1) != INTEGER_CST
6049 || TREE_INT_CST_LOW (arg1) & ~0x1f)
6050 {
6051 error ("argument 2 must be a 5-bit unsigned literal");
9a171fcd 6052 return const0_rtx;
b44140e7 6053 }
b44140e7
AH		 6054 }
6055
c62f2db5 6056 if (target == 0
0ac081f6
AH		 6057 || GET_MODE (target) != tmode
6058 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6059 target = gen_reg_rtx (tmode);
6060
6061 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
6062 op0 = copy_to_mode_reg (mode0, op0);
6063 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
6064 op1 = copy_to_mode_reg (mode1, op1);
6065
6066 pat = GEN_FCN (icode) (target, op0, op1);
6067 if (! pat)
6068 return 0;
6069 emit_insn (pat);
6070
6071 return target;
6072}
6525c0e7 6073
ae4b4a02 6074static rtx
f676971a 6075altivec_expand_predicate_builtin (enum insn_code icode, const char *opcode,
a2369ed3 6076 tree arglist, rtx target)
ae4b4a02
AH		 6077{
6078 rtx pat, scratch;
6079 tree cr6_form = TREE_VALUE (arglist);
6080 tree arg0 = TREE_VALUE (TREE_CHAIN (arglist));
6081 tree arg1 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
6082 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6083 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6084 enum machine_mode tmode = SImode;
6085 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
6086 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
6087 int cr6_form_int;
6088
6089 if (TREE_CODE (cr6_form) != INTEGER_CST)
6090 {
6091 error ("argument 1 of __builtin_altivec_predicate must be a constant");
9a171fcd 6092 return const0_rtx;
ae4b4a02
AH		 6093 }
6094 else
6095 cr6_form_int = TREE_INT_CST_LOW (cr6_form);
6096
6097 if (mode0 != mode1)
6098 abort ();
6099
6100 /* If we have invalid arguments, bail out before generating bad rtl. */
6101 if (arg0 == error_mark_node || arg1 == error_mark_node)
9a171fcd 6102 return const0_rtx;
ae4b4a02
AH		 6103
6104 if (target == 0
6105 || GET_MODE (target) != tmode
6106 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6107 target = gen_reg_rtx (tmode);
6108
6109 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
6110 op0 = copy_to_mode_reg (mode0, op0);
6111 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
6112 op1 = copy_to_mode_reg (mode1, op1);
6113
6114 scratch = gen_reg_rtx (mode0);
6115
6116 pat = GEN_FCN (icode) (scratch, op0, op1,
f1c25d3b 6117 gen_rtx_SYMBOL_REF (Pmode, opcode));
ae4b4a02
AH		 6118 if (! pat)
6119 return 0;
6120 emit_insn (pat);
6121
6122 /* The vec_any* and vec_all* predicates use the same opcodes for two
6123 different operations, but the bits in CR6 will be different
6124 depending on what information we want. So we have to play tricks
6125 with CR6 to get the right bits out.
6126
6127 If you think this is disgusting, look at the specs for the
6128 AltiVec predicates. */
6129
c4ad648e
AM		 6130 switch (cr6_form_int)
6131 {
6132 case 0:
6133 emit_insn (gen_cr6_test_for_zero (target));
6134 break;
6135 case 1:
6136 emit_insn (gen_cr6_test_for_zero_reverse (target));
6137 break;
6138 case 2:
6139 emit_insn (gen_cr6_test_for_lt (target));
6140 break;
6141 case 3:
6142 emit_insn (gen_cr6_test_for_lt_reverse (target));
6143 break;
6144 default:
6145 error ("argument 1 of __builtin_altivec_predicate is out of range");
6146 break;
6147 }
ae4b4a02
AH		 6148
6149 return target;
6150}
6151
b4a62fa0 6152static rtx
38f391a5 6153altivec_expand_lv_builtin (enum insn_code icode, tree arglist, rtx target)
b4a62fa0
SB		 6154{
6155 rtx pat, addr;
6156 tree arg0 = TREE_VALUE (arglist);
6157 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6158 enum machine_mode tmode = insn_data[icode].operand[0].mode;
6159 enum machine_mode mode0 = Pmode;
6160 enum machine_mode mode1 = Pmode;
6161 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6162 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6163
6164 if (icode == CODE_FOR_nothing)
6165 /* Builtin not supported on this processor. */
6166 return 0;
6167
6168 /* If we got invalid arguments bail out before generating bad rtl. */
6169 if (arg0 == error_mark_node || arg1 == error_mark_node)
6170 return const0_rtx;
6171
6172 if (target == 0
6173 || GET_MODE (target) != tmode
6174 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6175 target = gen_reg_rtx (tmode);
6176
f676971a 6177 op1 = copy_to_mode_reg (mode1, op1);
b4a62fa0
SB		 6178
6179 if (op0 == const0_rtx)
6180 {
6181 addr = gen_rtx_MEM (tmode, op1);
6182 }
6183 else
6184 {
6185 op0 = copy_to_mode_reg (mode0, op0);
6186 addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op0, op1));
6187 }
6188
6189 pat = GEN_FCN (icode) (target, addr);
6190
6191 if (! pat)
6192 return 0;
6193 emit_insn (pat);
6194
6195 return target;
6196}
6197
61bea3b0
AH		 6198static rtx
6199spe_expand_stv_builtin (enum insn_code icode, tree arglist)
6200{
6201 tree arg0 = TREE_VALUE (arglist);
6202 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6203 tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
6204 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6205 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6206 rtx op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
6207 rtx pat;
6208 enum machine_mode mode0 = insn_data[icode].operand[0].mode;
6209 enum machine_mode mode1 = insn_data[icode].operand[1].mode;
6210 enum machine_mode mode2 = insn_data[icode].operand[2].mode;
6211
6212 /* Invalid arguments. Bail before doing anything stoopid! */
6213 if (arg0 == error_mark_node
6214 || arg1 == error_mark_node
6215 || arg2 == error_mark_node)
6216 return const0_rtx;
6217
6218 if (! (*insn_data[icode].operand[2].predicate) (op0, mode2))
6219 op0 = copy_to_mode_reg (mode2, op0);
6220 if (! (*insn_data[icode].operand[0].predicate) (op1, mode0))
6221 op1 = copy_to_mode_reg (mode0, op1);
6222 if (! (*insn_data[icode].operand[1].predicate) (op2, mode1))
6223 op2 = copy_to_mode_reg (mode1, op2);
6224
6225 pat = GEN_FCN (icode) (op1, op2, op0);
6226 if (pat)
6227 emit_insn (pat);
6228 return NULL_RTX;
6229}
6230
6525c0e7 6231static rtx
a2369ed3 6232altivec_expand_stv_builtin (enum insn_code icode, tree arglist)
6525c0e7
AH		 6233{
6234 tree arg0 = TREE_VALUE (arglist);
6235 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6236 tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
6237 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6238 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6239 rtx op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
b4a62fa0
SB		 6240 rtx pat, addr;
6241 enum machine_mode tmode = insn_data[icode].operand[0].mode;
6242 enum machine_mode mode1 = Pmode;
6243 enum machine_mode mode2 = Pmode;
6525c0e7
AH		 6244
6245 /* Invalid arguments. Bail before doing anything stoopid! */
6246 if (arg0 == error_mark_node
6247 || arg1 == error_mark_node
6248 || arg2 == error_mark_node)
9a171fcd 6249 return const0_rtx;
6525c0e7 6250
b4a62fa0
SB		 6251 if (! (*insn_data[icode].operand[1].predicate) (op0, tmode))
6252 op0 = copy_to_mode_reg (tmode, op0);
6253
f676971a 6254 op2 = copy_to_mode_reg (mode2, op2);
b4a62fa0
SB		 6255
6256 if (op1 == const0_rtx)
6257 {
6258 addr = gen_rtx_MEM (tmode, op2);
6259 }
6260 else
6261 {
6262 op1 = copy_to_mode_reg (mode1, op1);
6263 addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op1, op2));
6264 }
6525c0e7 6265
b4a62fa0 6266 pat = GEN_FCN (icode) (addr, op0);
6525c0e7
AH		 6267 if (pat)
6268 emit_insn (pat);
6269 return NULL_RTX;
6270}
6271
2212663f 6272static rtx
a2369ed3 6273rs6000_expand_ternop_builtin (enum insn_code icode, tree arglist, rtx target)
2212663f
DB		 6274{
6275 rtx pat;
6276 tree arg0 = TREE_VALUE (arglist);
6277 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6278 tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
6279 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6280 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6281 rtx op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
6282 enum machine_mode tmode = insn_data[icode].operand[0].mode;
6283 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
6284 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
6285 enum machine_mode mode2 = insn_data[icode].operand[3].mode;
0ac081f6 6286
774b5662
DE		 6287 if (icode == CODE_FOR_nothing)
6288 /* Builtin not supported on this processor. */
6289 return 0;
6290
20e26713
AH		 6291 /* If we got invalid arguments bail out before generating bad rtl. */
6292 if (arg0 == error_mark_node
6293 || arg1 == error_mark_node
6294 || arg2 == error_mark_node)
9a171fcd 6295 return const0_rtx;
20e26713 6296
aba5fb01
NS		 6297 if (icode == CODE_FOR_altivec_vsldoi_v4sf
6298 || icode == CODE_FOR_altivec_vsldoi_v4si
6299 || icode == CODE_FOR_altivec_vsldoi_v8hi
6300 || icode == CODE_FOR_altivec_vsldoi_v16qi)
b44140e7
AH		 6301 {
6302 /* Only allow 4-bit unsigned literals. */
8bb418a3 6303 STRIP_NOPS (arg2);
b44140e7
AH		 6304 if (TREE_CODE (arg2) != INTEGER_CST
6305 || TREE_INT_CST_LOW (arg2) & ~0xf)
6306 {
6307 error ("argument 3 must be a 4-bit unsigned literal");
e3277ffb 6308 return const0_rtx;
b44140e7 6309 }
b44140e7
AH		 6310 }
6311
c62f2db5 6312 if (target == 0
2212663f
DB		 6313 || GET_MODE (target) != tmode
6314 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6315 target = gen_reg_rtx (tmode);
6316
6317 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
6318 op0 = copy_to_mode_reg (mode0, op0);
6319 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
6320 op1 = copy_to_mode_reg (mode1, op1);
6321 if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
6322 op2 = copy_to_mode_reg (mode2, op2);
6323
6324 pat = GEN_FCN (icode) (target, op0, op1, op2);
6325 if (! pat)
6326 return 0;
6327 emit_insn (pat);
6328
6329 return target;
6330}
92898235 6331
3a9b8c7e 6332/* Expand the lvx builtins. */
0ac081f6 6333static rtx
a2369ed3 6334altivec_expand_ld_builtin (tree exp, rtx target, bool *expandedp)
0ac081f6 6335{
0ac081f6
AH		 6336 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
6337 tree arglist = TREE_OPERAND (exp, 1);
0ac081f6 6338 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
3a9b8c7e
AH		 6339 tree arg0;
6340 enum machine_mode tmode, mode0;
7c3abc73 6341 rtx pat, op0;
3a9b8c7e 6342 enum insn_code icode;
92898235 6343
0ac081f6
AH		 6344 switch (fcode)
6345 {
f18c054f 6346 case ALTIVEC_BUILTIN_LD_INTERNAL_16qi:
81466555 6347 icode = CODE_FOR_altivec_lvx_v16qi;
3a9b8c7e 6348 break;
f18c054f 6349 case ALTIVEC_BUILTIN_LD_INTERNAL_8hi:
81466555 6350 icode = CODE_FOR_altivec_lvx_v8hi;
3a9b8c7e
AH		 6351 break;
6352 case ALTIVEC_BUILTIN_LD_INTERNAL_4si:
81466555 6353 icode = CODE_FOR_altivec_lvx_v4si;
3a9b8c7e
AH		 6354 break;
6355 case ALTIVEC_BUILTIN_LD_INTERNAL_4sf:
81466555 6356 icode = CODE_FOR_altivec_lvx_v4sf;
3a9b8c7e
AH		 6357 break;
6358 default:
6359 *expandedp = false;
6360 return NULL_RTX;
6361 }
0ac081f6 6362
3a9b8c7e 6363 *expandedp = true;
f18c054f 6364
3a9b8c7e
AH		 6365 arg0 = TREE_VALUE (arglist);
6366 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6367 tmode = insn_data[icode].operand[0].mode;
6368 mode0 = insn_data[icode].operand[1].mode;
f18c054f 6369
3a9b8c7e
AH		 6370 if (target == 0
6371 || GET_MODE (target) != tmode
6372 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6373 target = gen_reg_rtx (tmode);
24408032 6374
3a9b8c7e
AH		 6375 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
6376 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
f18c054f 6377
3a9b8c7e
AH		 6378 pat = GEN_FCN (icode) (target, op0);
6379 if (! pat)
6380 return 0;
6381 emit_insn (pat);
6382 return target;
6383}
f18c054f 6384
3a9b8c7e
AH		 6385/* Expand the stvx builtins. */
6386static rtx
f676971a 6387altivec_expand_st_builtin (tree exp, rtx target ATTRIBUTE_UNUSED,
a2369ed3 6388 bool *expandedp)
3a9b8c7e
AH		 6389{
6390 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
6391 tree arglist = TREE_OPERAND (exp, 1);
6392 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
6393 tree arg0, arg1;
6394 enum machine_mode mode0, mode1;
7c3abc73 6395 rtx pat, op0, op1;
3a9b8c7e 6396 enum insn_code icode;
f18c054f 6397
3a9b8c7e
AH		 6398 switch (fcode)
6399 {
6400 case ALTIVEC_BUILTIN_ST_INTERNAL_16qi:
81466555 6401 icode = CODE_FOR_altivec_stvx_v16qi;
3a9b8c7e
AH		 6402 break;
6403 case ALTIVEC_BUILTIN_ST_INTERNAL_8hi:
81466555 6404 icode = CODE_FOR_altivec_stvx_v8hi;
3a9b8c7e
AH		 6405 break;
6406 case ALTIVEC_BUILTIN_ST_INTERNAL_4si:
81466555 6407 icode = CODE_FOR_altivec_stvx_v4si;
3a9b8c7e
AH		 6408 break;
6409 case ALTIVEC_BUILTIN_ST_INTERNAL_4sf:
81466555 6410 icode = CODE_FOR_altivec_stvx_v4sf;
3a9b8c7e
AH		 6411 break;
6412 default:
6413 *expandedp = false;
6414 return NULL_RTX;
6415 }
24408032 6416
3a9b8c7e
AH		 6417 arg0 = TREE_VALUE (arglist);
6418 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6419 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6420 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6421 mode0 = insn_data[icode].operand[0].mode;
6422 mode1 = insn_data[icode].operand[1].mode;
f18c054f 6423
3a9b8c7e
AH		 6424 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
6425 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
6426 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
6427 op1 = copy_to_mode_reg (mode1, op1);
f18c054f 6428
3a9b8c7e
AH		 6429 pat = GEN_FCN (icode) (op0, op1);
6430 if (pat)
6431 emit_insn (pat);
f18c054f 6432
3a9b8c7e
AH		 6433 *expandedp = true;
6434 return NULL_RTX;
6435}
f18c054f 6436
3a9b8c7e
AH		 6437/* Expand the dst builtins. */
6438static rtx
f676971a 6439altivec_expand_dst_builtin (tree exp, rtx target ATTRIBUTE_UNUSED,
a2369ed3 6440 bool *expandedp)
3a9b8c7e
AH		 6441{
6442 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
6443 tree arglist = TREE_OPERAND (exp, 1);
6444 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
6445 tree arg0, arg1, arg2;
6446 enum machine_mode mode0, mode1, mode2;
7c3abc73 6447 rtx pat, op0, op1, op2;
3a9b8c7e 6448 struct builtin_description *d;
a3170dc6 6449 size_t i;
f18c054f 6450
3a9b8c7e 6451 *expandedp = false;
f18c054f 6452
3a9b8c7e
AH		 6453 /* Handle DST variants. */
6454 d = (struct builtin_description *) bdesc_dst;
6455 for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++)
6456 if (d->code == fcode)
6457 {
6458 arg0 = TREE_VALUE (arglist);
6459 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6460 arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
6461 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6462 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6463 op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
6464 mode0 = insn_data[d->icode].operand[0].mode;
6465 mode1 = insn_data[d->icode].operand[1].mode;
6466 mode2 = insn_data[d->icode].operand[2].mode;
24408032 6467
3a9b8c7e
AH		 6468 /* Invalid arguments, bail out before generating bad rtl. */
6469 if (arg0 == error_mark_node
6470 || arg1 == error_mark_node
6471 || arg2 == error_mark_node)
6472 return const0_rtx;
f18c054f 6473
86e7df90 6474 *expandedp = true;
8bb418a3 6475 STRIP_NOPS (arg2);
3a9b8c7e
AH		 6476 if (TREE_CODE (arg2) != INTEGER_CST
6477 || TREE_INT_CST_LOW (arg2) & ~0x3)
6478 {
9e637a26 6479 error ("argument to %qs must be a 2-bit unsigned literal", d->name);
3a9b8c7e
AH		 6480 return const0_rtx;
6481 }
f18c054f 6482
3a9b8c7e 6483 if (! (*insn_data[d->icode].operand[0].predicate) (op0, mode0))
666158b9 6484 op0 = copy_to_mode_reg (Pmode, op0);
3a9b8c7e
AH		 6485 if (! (*insn_data[d->icode].operand[1].predicate) (op1, mode1))
6486 op1 = copy_to_mode_reg (mode1, op1);
24408032 6487
3a9b8c7e
AH		 6488 pat = GEN_FCN (d->icode) (op0, op1, op2);
6489 if (pat != 0)
6490 emit_insn (pat);
f18c054f 6491
3a9b8c7e
AH		 6492 return NULL_RTX;
6493 }
f18c054f 6494
3a9b8c7e
AH		 6495 return NULL_RTX;
6496}
24408032 6497
3a9b8c7e
AH		 6498/* Expand the builtin in EXP and store the result in TARGET. Store
6499 true in *EXPANDEDP if we found a builtin to expand. */
6500static rtx
a2369ed3 6501altivec_expand_builtin (tree exp, rtx target, bool *expandedp)
3a9b8c7e
AH		 6502{
6503 struct builtin_description *d;
6504 struct builtin_description_predicates *dp;
6505 size_t i;
6506 enum insn_code icode;
6507 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
6508 tree arglist = TREE_OPERAND (exp, 1);
7c3abc73
AH		 6509 tree arg0;
6510 rtx op0, pat;
6511 enum machine_mode tmode, mode0;
3a9b8c7e 6512 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
0ac081f6 6513
3a9b8c7e
AH		 6514 target = altivec_expand_ld_builtin (exp, target, expandedp);
6515 if (*expandedp)
6516 return target;
0ac081f6 6517
3a9b8c7e
AH		 6518 target = altivec_expand_st_builtin (exp, target, expandedp);
6519 if (*expandedp)
6520 return target;
6521
6522 target = altivec_expand_dst_builtin (exp, target, expandedp);
6523 if (*expandedp)
6524 return target;
6525
6526 *expandedp = true;
95385cbb 6527
3a9b8c7e
AH		 6528 switch (fcode)
6529 {
6525c0e7
AH		 6530 case ALTIVEC_BUILTIN_STVX:
6531 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx, arglist);
6532 case ALTIVEC_BUILTIN_STVEBX:
6533 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvebx, arglist);
6534 case ALTIVEC_BUILTIN_STVEHX:
6535 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvehx, arglist);
6536 case ALTIVEC_BUILTIN_STVEWX:
6537 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvewx, arglist);
6538 case ALTIVEC_BUILTIN_STVXL:
6539 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl, arglist);
3a9b8c7e 6540
95385cbb
AH		 6541 case ALTIVEC_BUILTIN_MFVSCR:
6542 icode = CODE_FOR_altivec_mfvscr;
6543 tmode = insn_data[icode].operand[0].mode;
6544
6545 if (target == 0
6546 || GET_MODE (target) != tmode
6547 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6548 target = gen_reg_rtx (tmode);
f676971a 6549
95385cbb 6550 pat = GEN_FCN (icode) (target);
0ac081f6
AH		 6551 if (! pat)
6552 return 0;
6553 emit_insn (pat);
95385cbb
AH		 6554 return target;
6555
6556 case ALTIVEC_BUILTIN_MTVSCR:
6557 icode = CODE_FOR_altivec_mtvscr;
6558 arg0 = TREE_VALUE (arglist);
6559 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6560 mode0 = insn_data[icode].operand[0].mode;
6561
6562 /* If we got invalid arguments bail out before generating bad rtl. */
6563 if (arg0 == error_mark_node)
9a171fcd 6564 return const0_rtx;
95385cbb
AH		 6565
6566 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
6567 op0 = copy_to_mode_reg (mode0, op0);
6568
6569 pat = GEN_FCN (icode) (op0);
6570 if (pat)
6571 emit_insn (pat);
6572 return NULL_RTX;
3a9b8c7e 6573
95385cbb
AH		 6574 case ALTIVEC_BUILTIN_DSSALL:
6575 emit_insn (gen_altivec_dssall ());
6576 return NULL_RTX;
6577
6578 case ALTIVEC_BUILTIN_DSS:
6579 icode = CODE_FOR_altivec_dss;
6580 arg0 = TREE_VALUE (arglist);
8bb418a3 6581 STRIP_NOPS (arg0);
95385cbb
AH		 6582 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6583 mode0 = insn_data[icode].operand[0].mode;
6584
6585 /* If we got invalid arguments bail out before generating bad rtl. */
6586 if (arg0 == error_mark_node)
9a171fcd 6587 return const0_rtx;
95385cbb 6588
b44140e7
AH		 6589 if (TREE_CODE (arg0) != INTEGER_CST
6590 || TREE_INT_CST_LOW (arg0) & ~0x3)
6591 {
6592 error ("argument to dss must be a 2-bit unsigned literal");
9a171fcd 6593 return const0_rtx;
b44140e7
AH		 6594 }
6595
95385cbb
AH		 6596 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
6597 op0 = copy_to_mode_reg (mode0, op0);
6598
6599 emit_insn (gen_altivec_dss (op0));
0ac081f6 6600 return NULL_RTX;
f676971a 6601
8bb418a3
ZL		 6602 case ALTIVEC_BUILTIN_COMPILETIME_ERROR:
6603 arg0 = TREE_VALUE (arglist);
97dc04b3 6604 while (TREE_CODE (arg0) == NOP_EXPR || TREE_CODE (arg0) == ADDR_EXPR
c4ad648e 6605 || TREE_CODE (arg0) == ARRAY_REF)
8bb418a3 6606 arg0 = TREE_OPERAND (arg0, 0);
9e637a26 6607 error ("invalid parameter combination for %qs AltiVec intrinsic",
8bb418a3
ZL		 6608 TREE_STRING_POINTER (arg0));
6609
6610 return const0_rtx;
0ac081f6 6611 }
24408032 6612
100c4561
AH		 6613 /* Expand abs* operations. */
6614 d = (struct builtin_description *) bdesc_abs;
ca7558fc 6615 for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++)
100c4561
AH		 6616 if (d->code == fcode)
6617 return altivec_expand_abs_builtin (d->icode, arglist, target);
6618
ae4b4a02
AH		 6619 /* Expand the AltiVec predicates. */
6620 dp = (struct builtin_description_predicates *) bdesc_altivec_preds;
ca7558fc 6621 for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, dp++)
ae4b4a02 6622 if (dp->code == fcode)
c4ad648e
AM		 6623 return altivec_expand_predicate_builtin (dp->icode, dp->opcode,
6624 arglist, target);
ae4b4a02 6625
6525c0e7
AH		 6626 /* LV* are funky. We initialized them differently. */
6627 switch (fcode)
6628 {
6629 case ALTIVEC_BUILTIN_LVSL:
b4a62fa0 6630 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsl,
c4ad648e 6631 arglist, target);
6525c0e7 6632 case ALTIVEC_BUILTIN_LVSR:
b4a62fa0 6633 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsr,
c4ad648e 6634 arglist, target);
6525c0e7 6635 case ALTIVEC_BUILTIN_LVEBX:
b4a62fa0 6636 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvebx,
c4ad648e 6637 arglist, target);
6525c0e7 6638 case ALTIVEC_BUILTIN_LVEHX:
b4a62fa0 6639 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvehx,
c4ad648e 6640 arglist, target);
6525c0e7 6641 case ALTIVEC_BUILTIN_LVEWX:
b4a62fa0 6642 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvewx,
c4ad648e 6643 arglist, target);
6525c0e7 6644 case ALTIVEC_BUILTIN_LVXL:
b4a62fa0 6645 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl,
c4ad648e 6646 arglist, target);
6525c0e7 6647 case ALTIVEC_BUILTIN_LVX:
b4a62fa0 6648 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx,
c4ad648e 6649 arglist, target);
6525c0e7
AH		 6650 default:
6651 break;
6652 /* Fall through. */
6653 }
95385cbb 6654
92898235 6655 *expandedp = false;
0ac081f6
AH		 6656 return NULL_RTX;
6657}
6658
a3170dc6
AH		 6659/* Binops that need to be initialized manually, but can be expanded
6660 automagically by rs6000_expand_binop_builtin. */
6661static struct builtin_description bdesc_2arg_spe[] =
6662{
6663 { 0, CODE_FOR_spe_evlddx, "__builtin_spe_evlddx", SPE_BUILTIN_EVLDDX },
6664 { 0, CODE_FOR_spe_evldwx, "__builtin_spe_evldwx", SPE_BUILTIN_EVLDWX },
6665 { 0, CODE_FOR_spe_evldhx, "__builtin_spe_evldhx", SPE_BUILTIN_EVLDHX },
6666 { 0, CODE_FOR_spe_evlwhex, "__builtin_spe_evlwhex", SPE_BUILTIN_EVLWHEX },
6667 { 0, CODE_FOR_spe_evlwhoux, "__builtin_spe_evlwhoux", SPE_BUILTIN_EVLWHOUX },
6668 { 0, CODE_FOR_spe_evlwhosx, "__builtin_spe_evlwhosx", SPE_BUILTIN_EVLWHOSX },
6669 { 0, CODE_FOR_spe_evlwwsplatx, "__builtin_spe_evlwwsplatx", SPE_BUILTIN_EVLWWSPLATX },
6670 { 0, CODE_FOR_spe_evlwhsplatx, "__builtin_spe_evlwhsplatx", SPE_BUILTIN_EVLWHSPLATX },
6671 { 0, CODE_FOR_spe_evlhhesplatx, "__builtin_spe_evlhhesplatx", SPE_BUILTIN_EVLHHESPLATX },
6672 { 0, CODE_FOR_spe_evlhhousplatx, "__builtin_spe_evlhhousplatx", SPE_BUILTIN_EVLHHOUSPLATX },
6673 { 0, CODE_FOR_spe_evlhhossplatx, "__builtin_spe_evlhhossplatx", SPE_BUILTIN_EVLHHOSSPLATX },
6674 { 0, CODE_FOR_spe_evldd, "__builtin_spe_evldd", SPE_BUILTIN_EVLDD },
6675 { 0, CODE_FOR_spe_evldw, "__builtin_spe_evldw", SPE_BUILTIN_EVLDW },
6676 { 0, CODE_FOR_spe_evldh, "__builtin_spe_evldh", SPE_BUILTIN_EVLDH },
6677 { 0, CODE_FOR_spe_evlwhe, "__builtin_spe_evlwhe", SPE_BUILTIN_EVLWHE },
6678 { 0, CODE_FOR_spe_evlwhou, "__builtin_spe_evlwhou", SPE_BUILTIN_EVLWHOU },
6679 { 0, CODE_FOR_spe_evlwhos, "__builtin_spe_evlwhos", SPE_BUILTIN_EVLWHOS },
6680 { 0, CODE_FOR_spe_evlwwsplat, "__builtin_spe_evlwwsplat", SPE_BUILTIN_EVLWWSPLAT },
6681 { 0, CODE_FOR_spe_evlwhsplat, "__builtin_spe_evlwhsplat", SPE_BUILTIN_EVLWHSPLAT },
6682 { 0, CODE_FOR_spe_evlhhesplat, "__builtin_spe_evlhhesplat", SPE_BUILTIN_EVLHHESPLAT },
6683 { 0, CODE_FOR_spe_evlhhousplat, "__builtin_spe_evlhhousplat", SPE_BUILTIN_EVLHHOUSPLAT },
6684 { 0, CODE_FOR_spe_evlhhossplat, "__builtin_spe_evlhhossplat", SPE_BUILTIN_EVLHHOSSPLAT }
6685};
6686
6687/* Expand the builtin in EXP and store the result in TARGET. Store
6688 true in *EXPANDEDP if we found a builtin to expand.
6689
6690 This expands the SPE builtins that are not simple unary and binary
6691 operations. */
6692static rtx
a2369ed3 6693spe_expand_builtin (tree exp, rtx target, bool *expandedp)
a3170dc6
AH		 6694{
6695 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
6696 tree arglist = TREE_OPERAND (exp, 1);
6697 tree arg1, arg0;
6698 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
6699 enum insn_code icode;
6700 enum machine_mode tmode, mode0;
6701 rtx pat, op0;
6702 struct builtin_description *d;
6703 size_t i;
6704
6705 *expandedp = true;
6706
6707 /* Syntax check for a 5-bit unsigned immediate. */
6708 switch (fcode)
6709 {
6710 case SPE_BUILTIN_EVSTDD:
6711 case SPE_BUILTIN_EVSTDH:
6712 case SPE_BUILTIN_EVSTDW:
6713 case SPE_BUILTIN_EVSTWHE:
6714 case SPE_BUILTIN_EVSTWHO:
6715 case SPE_BUILTIN_EVSTWWE:
6716 case SPE_BUILTIN_EVSTWWO:
6717 arg1 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
6718 if (TREE_CODE (arg1) != INTEGER_CST
6719 || TREE_INT_CST_LOW (arg1) & ~0x1f)
6720 {
6721 error ("argument 2 must be a 5-bit unsigned literal");
6722 return const0_rtx;
6723 }
6724 break;
6725 default:
6726 break;
6727 }
6728
00332c9f
AH		 6729 /* The evsplat*i instructions are not quite generic. */
6730 switch (fcode)
6731 {
6732 case SPE_BUILTIN_EVSPLATFI:
6733 return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplatfi,
6734 arglist, target);
6735 case SPE_BUILTIN_EVSPLATI:
6736 return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplati,
6737 arglist, target);
6738 default:
6739 break;
6740 }
6741
a3170dc6
AH		 6742 d = (struct builtin_description *) bdesc_2arg_spe;
6743 for (i = 0; i < ARRAY_SIZE (bdesc_2arg_spe); ++i, ++d)
6744 if (d->code == fcode)
6745 return rs6000_expand_binop_builtin (d->icode, arglist, target);
6746
6747 d = (struct builtin_description *) bdesc_spe_predicates;
6748 for (i = 0; i < ARRAY_SIZE (bdesc_spe_predicates); ++i, ++d)
6749 if (d->code == fcode)
6750 return spe_expand_predicate_builtin (d->icode, arglist, target);
6751
6752 d = (struct builtin_description *) bdesc_spe_evsel;
6753 for (i = 0; i < ARRAY_SIZE (bdesc_spe_evsel); ++i, ++d)
6754 if (d->code == fcode)
6755 return spe_expand_evsel_builtin (d->icode, arglist, target);
6756
6757 switch (fcode)
6758 {
6759 case SPE_BUILTIN_EVSTDDX:
61bea3b0 6760 return spe_expand_stv_builtin (CODE_FOR_spe_evstddx, arglist);
a3170dc6 6761 case SPE_BUILTIN_EVSTDHX:
61bea3b0 6762 return spe_expand_stv_builtin (CODE_FOR_spe_evstdhx, arglist);
a3170dc6 6763 case SPE_BUILTIN_EVSTDWX:
61bea3b0 6764 return spe_expand_stv_builtin (CODE_FOR_spe_evstdwx, arglist);
a3170dc6 6765 case SPE_BUILTIN_EVSTWHEX:
61bea3b0 6766 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhex, arglist);
a3170dc6 6767 case SPE_BUILTIN_EVSTWHOX:
61bea3b0 6768 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhox, arglist);
a3170dc6 6769 case SPE_BUILTIN_EVSTWWEX:
61bea3b0 6770 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwex, arglist);
a3170dc6 6771 case SPE_BUILTIN_EVSTWWOX:
61bea3b0 6772 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwox, arglist);
a3170dc6 6773 case SPE_BUILTIN_EVSTDD:
61bea3b0 6774 return spe_expand_stv_builtin (CODE_FOR_spe_evstdd, arglist);
a3170dc6 6775 case SPE_BUILTIN_EVSTDH:
61bea3b0 6776 return spe_expand_stv_builtin (CODE_FOR_spe_evstdh, arglist);
a3170dc6 6777 case SPE_BUILTIN_EVSTDW:
61bea3b0 6778 return spe_expand_stv_builtin (CODE_FOR_spe_evstdw, arglist);
a3170dc6 6779 case SPE_BUILTIN_EVSTWHE:
61bea3b0 6780 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhe, arglist);
a3170dc6 6781 case SPE_BUILTIN_EVSTWHO:
61bea3b0 6782 return spe_expand_stv_builtin (CODE_FOR_spe_evstwho, arglist);
a3170dc6 6783 case SPE_BUILTIN_EVSTWWE:
61bea3b0 6784 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwe, arglist);
a3170dc6 6785 case SPE_BUILTIN_EVSTWWO:
61bea3b0 6786 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwo, arglist);
a3170dc6
AH		 6787 case SPE_BUILTIN_MFSPEFSCR:
6788 icode = CODE_FOR_spe_mfspefscr;
6789 tmode = insn_data[icode].operand[0].mode;
6790
6791 if (target == 0
6792 || GET_MODE (target) != tmode
6793 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6794 target = gen_reg_rtx (tmode);
f676971a 6795
a3170dc6
AH		 6796 pat = GEN_FCN (icode) (target);
6797 if (! pat)
6798 return 0;
6799 emit_insn (pat);
6800 return target;
6801 case SPE_BUILTIN_MTSPEFSCR:
6802 icode = CODE_FOR_spe_mtspefscr;
6803 arg0 = TREE_VALUE (arglist);
6804 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6805 mode0 = insn_data[icode].operand[0].mode;
6806
6807 if (arg0 == error_mark_node)
6808 return const0_rtx;
6809
6810 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
6811 op0 = copy_to_mode_reg (mode0, op0);
6812
6813 pat = GEN_FCN (icode) (op0);
6814 if (pat)
6815 emit_insn (pat);
6816 return NULL_RTX;
6817 default:
6818 break;
6819 }
6820
6821 *expandedp = false;
6822 return NULL_RTX;
6823}
6824
6825static rtx
a2369ed3 6826spe_expand_predicate_builtin (enum insn_code icode, tree arglist, rtx target)
a3170dc6
AH		 6827{
6828 rtx pat, scratch, tmp;
6829 tree form = TREE_VALUE (arglist);
6830 tree arg0 = TREE_VALUE (TREE_CHAIN (arglist));
6831 tree arg1 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
6832 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6833 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6834 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
6835 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
6836 int form_int;
6837 enum rtx_code code;
6838
6839 if (TREE_CODE (form) != INTEGER_CST)
6840 {
6841 error ("argument 1 of __builtin_spe_predicate must be a constant");
6842 return const0_rtx;
6843 }
6844 else
6845 form_int = TREE_INT_CST_LOW (form);
6846
6847 if (mode0 != mode1)
6848 abort ();
6849
6850 if (arg0 == error_mark_node || arg1 == error_mark_node)
6851 return const0_rtx;
6852
6853 if (target == 0
6854 || GET_MODE (target) != SImode
6855 || ! (*insn_data[icode].operand[0].predicate) (target, SImode))
6856 target = gen_reg_rtx (SImode);
6857
6858 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
6859 op0 = copy_to_mode_reg (mode0, op0);
6860 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
6861 op1 = copy_to_mode_reg (mode1, op1);
6862
6863 scratch = gen_reg_rtx (CCmode);
6864
6865 pat = GEN_FCN (icode) (scratch, op0, op1);
6866 if (! pat)
6867 return const0_rtx;
6868 emit_insn (pat);
6869
6870 /* There are 4 variants for each predicate: _any_, _all_, _upper_,
6871 _lower_. We use one compare, but look in different bits of the
6872 CR for each variant.
6873
6874 There are 2 elements in each SPE simd type (upper/lower). The CR
6875 bits are set as follows:
6876
6877 BIT0 | BIT 1 | BIT 2 | BIT 3
6878 U | L | (U | L) | (U & L)
6879
6880 So, for an "all" relationship, BIT 3 would be set.
6881 For an "any" relationship, BIT 2 would be set. Etc.
6882
6883 Following traditional nomenclature, these bits map to:
6884
6885 BIT0 | BIT 1 | BIT 2 | BIT 3
6886 LT | GT | EQ | OV
6887
6888 Later, we will generate rtl to look in the LT/EQ/EQ/OV bits.
6889 */
6890
6891 switch (form_int)
6892 {
6893 /* All variant. OV bit. */
6894 case 0:
6895 /* We need to get to the OV bit, which is the ORDERED bit. We
6896 could generate (ordered:SI (reg:CC xx) (const_int 0)), but
6897 that's ugly and will trigger a validate_condition_mode abort.
6898 So let's just use another pattern. */
6899 emit_insn (gen_move_from_CR_ov_bit (target, scratch));
6900 return target;
6901 /* Any variant. EQ bit. */
6902 case 1:
6903 code = EQ;
6904 break;
6905 /* Upper variant. LT bit. */
6906 case 2:
6907 code = LT;
6908 break;
6909 /* Lower variant. GT bit. */
6910 case 3:
6911 code = GT;
6912 break;
6913 default:
6914 error ("argument 1 of __builtin_spe_predicate is out of range");
6915 return const0_rtx;
6916 }
6917
6918 tmp = gen_rtx_fmt_ee (code, SImode, scratch, const0_rtx);
6919 emit_move_insn (target, tmp);
6920
6921 return target;
6922}
6923
6924/* The evsel builtins look like this:
6925
6926 e = __builtin_spe_evsel_OP (a, b, c, d);
6927
6928 and work like this:
6929
6930 e[upper] = a[upper] *OP* b[upper] ? c[upper] : d[upper];
6931 e[lower] = a[lower] *OP* b[lower] ? c[lower] : d[lower];
6932*/
6933
6934static rtx
a2369ed3 6935spe_expand_evsel_builtin (enum insn_code icode, tree arglist, rtx target)
a3170dc6
AH		 6936{
6937 rtx pat, scratch;
6938 tree arg0 = TREE_VALUE (arglist);
6939 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6940 tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
6941 tree arg3 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (TREE_CHAIN (arglist))));
6942 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6943 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6944 rtx op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
6945 rtx op3 = expand_expr (arg3, NULL_RTX, VOIDmode, 0);
6946 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
6947 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
6948
6949 if (mode0 != mode1)
6950 abort ();
6951
6952 if (arg0 == error_mark_node || arg1 == error_mark_node
6953 || arg2 == error_mark_node || arg3 == error_mark_node)
6954 return const0_rtx;
6955
6956 if (target == 0
6957 || GET_MODE (target) != mode0
6958 || ! (*insn_data[icode].operand[0].predicate) (target, mode0))
6959 target = gen_reg_rtx (mode0);
6960
6961 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
6962 op0 = copy_to_mode_reg (mode0, op0);
6963 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
6964 op1 = copy_to_mode_reg (mode0, op1);
6965 if (! (*insn_data[icode].operand[1].predicate) (op2, mode1))
6966 op2 = copy_to_mode_reg (mode0, op2);
6967 if (! (*insn_data[icode].operand[1].predicate) (op3, mode1))
6968 op3 = copy_to_mode_reg (mode0, op3);
6969
6970 /* Generate the compare. */
6971 scratch = gen_reg_rtx (CCmode);
6972 pat = GEN_FCN (icode) (scratch, op0, op1);
6973 if (! pat)
6974 return const0_rtx;
6975 emit_insn (pat);
6976
6977 if (mode0 == V2SImode)
6978 emit_insn (gen_spe_evsel (target, op2, op3, scratch));
6979 else
6980 emit_insn (gen_spe_evsel_fs (target, op2, op3, scratch));
6981
6982 return target;
6983}
6984
0ac081f6
AH		 6985/* Expand an expression EXP that calls a built-in function,
6986 with result going to TARGET if that's convenient
6987 (and in mode MODE if that's convenient).
6988 SUBTARGET may be used as the target for computing one of EXP's operands.
6989 IGNORE is nonzero if the value is to be ignored. */
6990
6991static rtx
a2369ed3 6992rs6000_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
c4ad648e
AM		 6993 enum machine_mode mode ATTRIBUTE_UNUSED,
6994 int ignore ATTRIBUTE_UNUSED)
0ac081f6 6995{
92898235
AH		 6996 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
6997 tree arglist = TREE_OPERAND (exp, 1);
6998 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
6999 struct builtin_description *d;
7000 size_t i;
7001 rtx ret;
7002 bool success;
f676971a 7003
7ccf35ed
DN		 7004 if (fcode == ALTIVEC_BUILTIN_MASK_FOR_LOAD
7005 || fcode == ALTIVEC_BUILTIN_MASK_FOR_STORE)
7006 {
7007 int icode = (int) CODE_FOR_altivec_lvsr;
7008 enum machine_mode tmode = insn_data[icode].operand[0].mode;
7009 enum machine_mode mode = insn_data[icode].operand[1].mode;
7010 tree arg;
7011 rtx op, addr, pat;
7012
7013 if (!TARGET_ALTIVEC)
7014 abort ();
7015
7016 arg = TREE_VALUE (arglist);
7017 if (TREE_CODE (TREE_TYPE (arg)) != POINTER_TYPE)
7018 abort ();
7019 op = expand_expr (arg, NULL_RTX, Pmode, EXPAND_NORMAL);
7020 addr = memory_address (mode, op);
7021 if (fcode == ALTIVEC_BUILTIN_MASK_FOR_STORE)
7022 op = addr;
7023 else
7024 {
7025 /* For the load case need to negate the address. */
7026 op = gen_reg_rtx (GET_MODE (addr));
7027 emit_insn (gen_rtx_SET (VOIDmode, op,
7028 gen_rtx_NEG (GET_MODE (addr), addr)));
c4ad648e 7029 }
7ccf35ed
DN		 7030 op = gen_rtx_MEM (mode, op);
7031
7032 if (target == 0
7033 || GET_MODE (target) != tmode
7034 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7035 target = gen_reg_rtx (tmode);
7036
7037 /*pat = gen_altivec_lvsr (target, op);*/
7038 pat = GEN_FCN (icode) (target, op);
7039 if (!pat)
7040 return 0;
7041 emit_insn (pat);
7042
7043 return target;
7044 }
7045
0ac081f6 7046 if (TARGET_ALTIVEC)
92898235
AH		 7047 {
7048 ret = altivec_expand_builtin (exp, target, &success);
7049
a3170dc6
AH		 7050 if (success)
7051 return ret;
7052 }
7053 if (TARGET_SPE)
7054 {
7055 ret = spe_expand_builtin (exp, target, &success);
7056
92898235
AH		 7057 if (success)
7058 return ret;
7059 }
7060
0559cc77
DE		 7061 if (TARGET_ALTIVEC || TARGET_SPE)
7062 {
7063 /* Handle simple unary operations. */
7064 d = (struct builtin_description *) bdesc_1arg;
7065 for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
7066 if (d->code == fcode)
7067 return rs6000_expand_unop_builtin (d->icode, arglist, target);
7068
7069 /* Handle simple binary operations. */
7070 d = (struct builtin_description *) bdesc_2arg;
7071 for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
7072 if (d->code == fcode)
7073 return rs6000_expand_binop_builtin (d->icode, arglist, target);
7074
7075 /* Handle simple ternary operations. */
7076 d = (struct builtin_description *) bdesc_3arg;
7077 for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++)
7078 if (d->code == fcode)
7079 return rs6000_expand_ternop_builtin (d->icode, arglist, target);
7080 }
0ac081f6
AH		 7081
7082 abort ();
92898235 7083 return NULL_RTX;
0ac081f6
AH		 7084}
7085
7c62e993
PB		 7086static tree
7087build_opaque_vector_type (tree node, int nunits)
7088{
7089 node = copy_node (node);
7090 TYPE_MAIN_VARIANT (node) = node;
7091 return build_vector_type (node, nunits);
7092}
7093
0ac081f6 7094static void
863d938c 7095rs6000_init_builtins (void)
0ac081f6 7096{
4a5eab38
PB		 7097 V2SI_type_node = build_vector_type (intSI_type_node, 2);
7098 V2SF_type_node = build_vector_type (float_type_node, 2);
7099 V4HI_type_node = build_vector_type (intHI_type_node, 4);
7100 V4SI_type_node = build_vector_type (intSI_type_node, 4);
7101 V4SF_type_node = build_vector_type (float_type_node, 4);
7e463bda 7102 V8HI_type_node = build_vector_type (intHI_type_node, 8);
4a5eab38
PB		 7103 V16QI_type_node = build_vector_type (intQI_type_node, 16);
7104
7105 unsigned_V16QI_type_node = build_vector_type (unsigned_intQI_type_node, 16);
7106 unsigned_V8HI_type_node = build_vector_type (unsigned_intHI_type_node, 8);
7107 unsigned_V4SI_type_node = build_vector_type (unsigned_intSI_type_node, 4);
7108
7c62e993
PB		 7109 opaque_V2SF_type_node = build_opaque_vector_type (float_type_node, 2);
7110 opaque_V2SI_type_node = build_opaque_vector_type (intSI_type_node, 2);
6035d635 7111 opaque_p_V2SI_type_node = build_pointer_type (opaque_V2SI_type_node);
3fdaa45a 7112
8bb418a3
ZL		 7113 /* The 'vector bool ...' types must be kept distinct from 'vector unsigned ...'
7114 types, especially in C++ land. Similarly, 'vector pixel' is distinct from
7115 'vector unsigned short'. */
7116
8dd16ecc
NS		 7117 bool_char_type_node = build_distinct_type_copy (unsigned_intQI_type_node);
7118 bool_short_type_node = build_distinct_type_copy (unsigned_intHI_type_node);
7119 bool_int_type_node = build_distinct_type_copy (unsigned_intSI_type_node);
7120 pixel_type_node = build_distinct_type_copy (unsigned_intHI_type_node);
8bb418a3
ZL		 7121
7122 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7123 get_identifier ("__bool char"),
7124 bool_char_type_node));
7125 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7126 get_identifier ("__bool short"),
7127 bool_short_type_node));
7128 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7129 get_identifier ("__bool int"),
7130 bool_int_type_node));
7131 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7132 get_identifier ("__pixel"),
7133 pixel_type_node));
7134
4a5eab38
PB		 7135 bool_V16QI_type_node = build_vector_type (bool_char_type_node, 16);
7136 bool_V8HI_type_node = build_vector_type (bool_short_type_node, 8);
7137 bool_V4SI_type_node = build_vector_type (bool_int_type_node, 4);
7138 pixel_V8HI_type_node = build_vector_type (pixel_type_node, 8);
8bb418a3
ZL		 7139
7140 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7141 get_identifier ("__vector unsigned char"),
7142 unsigned_V16QI_type_node));
7143 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7144 get_identifier ("__vector signed char"),
7145 V16QI_type_node));
7146 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7147 get_identifier ("__vector __bool char"),
7148 bool_V16QI_type_node));
7149
7150 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7151 get_identifier ("__vector unsigned short"),
7152 unsigned_V8HI_type_node));
7153 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7154 get_identifier ("__vector signed short"),
7155 V8HI_type_node));
7156 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7157 get_identifier ("__vector __bool short"),
7158 bool_V8HI_type_node));
7159
7160 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7161 get_identifier ("__vector unsigned int"),
7162 unsigned_V4SI_type_node));
7163 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7164 get_identifier ("__vector signed int"),
7165 V4SI_type_node));
7166 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7167 get_identifier ("__vector __bool int"),
7168 bool_V4SI_type_node));
7169
7170 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7171 get_identifier ("__vector float"),
7172 V4SF_type_node));
7173 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7174 get_identifier ("__vector __pixel"),
7175 pixel_V8HI_type_node));
7176
a3170dc6 7177 if (TARGET_SPE)
3fdaa45a 7178 spe_init_builtins ();
0ac081f6
AH		 7179 if (TARGET_ALTIVEC)
7180 altivec_init_builtins ();
0559cc77
DE		 7181 if (TARGET_ALTIVEC || TARGET_SPE)
7182 rs6000_common_init_builtins ();
0ac081f6
AH		 7183}
7184
a3170dc6
AH		 7185/* Search through a set of builtins and enable the mask bits.
7186 DESC is an array of builtins.
b6d08ca1 7187 SIZE is the total number of builtins.
a3170dc6
AH		 7188 START is the builtin enum at which to start.
7189 END is the builtin enum at which to end. */
0ac081f6 7190static void
a2369ed3 7191enable_mask_for_builtins (struct builtin_description *desc, int size,
f676971a 7192 enum rs6000_builtins start,
a2369ed3 7193 enum rs6000_builtins end)
a3170dc6
AH		 7194{
7195 int i;
7196
7197 for (i = 0; i < size; ++i)
7198 if (desc[i].code == start)
7199 break;
7200
7201 if (i == size)
7202 return;
7203
7204 for (; i < size; ++i)
7205 {
7206 /* Flip all the bits on. */
7207 desc[i].mask = target_flags;
7208 if (desc[i].code == end)
7209 break;
7210 }
7211}
7212
7213static void
863d938c 7214spe_init_builtins (void)
0ac081f6 7215{
a3170dc6
AH		 7216 tree endlink = void_list_node;
7217 tree puint_type_node = build_pointer_type (unsigned_type_node);
7218 tree pushort_type_node = build_pointer_type (short_unsigned_type_node);
ae4b4a02 7219 struct builtin_description *d;
0ac081f6
AH		 7220 size_t i;
7221
a3170dc6
AH		 7222 tree v2si_ftype_4_v2si
7223 = build_function_type
3fdaa45a
AH		 7224 (opaque_V2SI_type_node,
7225 tree_cons (NULL_TREE, opaque_V2SI_type_node,
7226 tree_cons (NULL_TREE, opaque_V2SI_type_node,
7227 tree_cons (NULL_TREE, opaque_V2SI_type_node,
7228 tree_cons (NULL_TREE, opaque_V2SI_type_node,
a3170dc6
AH		 7229 endlink)))));
7230
7231 tree v2sf_ftype_4_v2sf
7232 = build_function_type
3fdaa45a
AH		 7233 (opaque_V2SF_type_node,
7234 tree_cons (NULL_TREE, opaque_V2SF_type_node,
7235 tree_cons (NULL_TREE, opaque_V2SF_type_node,
7236 tree_cons (NULL_TREE, opaque_V2SF_type_node,
7237 tree_cons (NULL_TREE, opaque_V2SF_type_node,
a3170dc6
AH		 7238 endlink)))));
7239
7240 tree int_ftype_int_v2si_v2si
7241 = build_function_type
7242 (integer_type_node,
7243 tree_cons (NULL_TREE, integer_type_node,
3fdaa45a
AH		 7244 tree_cons (NULL_TREE, opaque_V2SI_type_node,
7245 tree_cons (NULL_TREE, opaque_V2SI_type_node,
a3170dc6
AH		 7246 endlink))));
7247
7248 tree int_ftype_int_v2sf_v2sf
7249 = build_function_type
7250 (integer_type_node,
7251 tree_cons (NULL_TREE, integer_type_node,
3fdaa45a
AH		 7252 tree_cons (NULL_TREE, opaque_V2SF_type_node,
7253 tree_cons (NULL_TREE, opaque_V2SF_type_node,
a3170dc6
AH		 7254 endlink))));
7255
7256 tree void_ftype_v2si_puint_int
7257 = build_function_type (void_type_node,
3fdaa45a 7258 tree_cons (NULL_TREE, opaque_V2SI_type_node,
a3170dc6
AH		 7259 tree_cons (NULL_TREE, puint_type_node,
7260 tree_cons (NULL_TREE,
7261 integer_type_node,
7262 endlink))));
7263
7264 tree void_ftype_v2si_puint_char
7265 = build_function_type (void_type_node,
3fdaa45a 7266 tree_cons (NULL_TREE, opaque_V2SI_type_node,
a3170dc6
AH		 7267 tree_cons (NULL_TREE, puint_type_node,
7268 tree_cons (NULL_TREE,
7269 char_type_node,
7270 endlink))));
7271
7272 tree void_ftype_v2si_pv2si_int
7273 = build_function_type (void_type_node,
3fdaa45a 7274 tree_cons (NULL_TREE, opaque_V2SI_type_node,
6035d635 7275 tree_cons (NULL_TREE, opaque_p_V2SI_type_node,
a3170dc6
AH		 7276 tree_cons (NULL_TREE,
7277 integer_type_node,
7278 endlink))));
7279
7280 tree void_ftype_v2si_pv2si_char
7281 = build_function_type (void_type_node,
3fdaa45a 7282 tree_cons (NULL_TREE, opaque_V2SI_type_node,
6035d635 7283 tree_cons (NULL_TREE, opaque_p_V2SI_type_node,
a3170dc6
AH		 7284 tree_cons (NULL_TREE,
7285 char_type_node,
7286 endlink))));
7287
7288 tree void_ftype_int
7289 = build_function_type (void_type_node,
7290 tree_cons (NULL_TREE, integer_type_node, endlink));
7291
7292 tree int_ftype_void
36e8d515 7293 = build_function_type (integer_type_node, endlink);
a3170dc6
AH		 7294
7295 tree v2si_ftype_pv2si_int
3fdaa45a 7296 = build_function_type (opaque_V2SI_type_node,
6035d635 7297 tree_cons (NULL_TREE, opaque_p_V2SI_type_node,
a3170dc6
AH		 7298 tree_cons (NULL_TREE, integer_type_node,
7299 endlink)));
7300
7301 tree v2si_ftype_puint_int
3fdaa45a 7302 = build_function_type (opaque_V2SI_type_node,
a3170dc6
AH		 7303 tree_cons (NULL_TREE, puint_type_node,
7304 tree_cons (NULL_TREE, integer_type_node,
7305 endlink)));
7306
7307 tree v2si_ftype_pushort_int
3fdaa45a 7308 = build_function_type (opaque_V2SI_type_node,
a3170dc6
AH		 7309 tree_cons (NULL_TREE, pushort_type_node,
7310 tree_cons (NULL_TREE, integer_type_node,
7311 endlink)));
7312
00332c9f
AH		 7313 tree v2si_ftype_signed_char
7314 = build_function_type (opaque_V2SI_type_node,
7315 tree_cons (NULL_TREE, signed_char_type_node,
7316 endlink));
7317
a3170dc6
AH		 7318 /* The initialization of the simple binary and unary builtins is
7319 done in rs6000_common_init_builtins, but we have to enable the
7320 mask bits here manually because we have run out of `target_flags'
7321 bits. We really need to redesign this mask business. */
7322
7323 enable_mask_for_builtins ((struct builtin_description *) bdesc_2arg,
7324 ARRAY_SIZE (bdesc_2arg),
7325 SPE_BUILTIN_EVADDW,
7326 SPE_BUILTIN_EVXOR);
7327 enable_mask_for_builtins ((struct builtin_description *) bdesc_1arg,
7328 ARRAY_SIZE (bdesc_1arg),
7329 SPE_BUILTIN_EVABS,
7330 SPE_BUILTIN_EVSUBFUSIAAW);
7331 enable_mask_for_builtins ((struct builtin_description *) bdesc_spe_predicates,
7332 ARRAY_SIZE (bdesc_spe_predicates),
7333 SPE_BUILTIN_EVCMPEQ,
7334 SPE_BUILTIN_EVFSTSTLT);
7335 enable_mask_for_builtins ((struct builtin_description *) bdesc_spe_evsel,
7336 ARRAY_SIZE (bdesc_spe_evsel),
7337 SPE_BUILTIN_EVSEL_CMPGTS,
7338 SPE_BUILTIN_EVSEL_FSTSTEQ);
7339
36252949
AH		 7340 (*lang_hooks.decls.pushdecl)
7341 (build_decl (TYPE_DECL, get_identifier ("__ev64_opaque__"),
7342 opaque_V2SI_type_node));
7343
a3170dc6 7344 /* Initialize irregular SPE builtins. */
f676971a 7345
a3170dc6
AH		 7346 def_builtin (target_flags, "__builtin_spe_mtspefscr", void_ftype_int, SPE_BUILTIN_MTSPEFSCR);
7347 def_builtin (target_flags, "__builtin_spe_mfspefscr", int_ftype_void, SPE_BUILTIN_MFSPEFSCR);
7348 def_builtin (target_flags, "__builtin_spe_evstddx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDDX);
7349 def_builtin (target_flags, "__builtin_spe_evstdhx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDHX);
7350 def_builtin (target_flags, "__builtin_spe_evstdwx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDWX);
7351 def_builtin (target_flags, "__builtin_spe_evstwhex", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWHEX);
7352 def_builtin (target_flags, "__builtin_spe_evstwhox", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWHOX);
7353 def_builtin (target_flags, "__builtin_spe_evstwwex", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWWEX);
7354 def_builtin (target_flags, "__builtin_spe_evstwwox", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWWOX);
7355 def_builtin (target_flags, "__builtin_spe_evstdd", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDD);
7356 def_builtin (target_flags, "__builtin_spe_evstdh", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDH);
7357 def_builtin (target_flags, "__builtin_spe_evstdw", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDW);
7358 def_builtin (target_flags, "__builtin_spe_evstwhe", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWHE);
7359 def_builtin (target_flags, "__builtin_spe_evstwho", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWHO);
7360 def_builtin (target_flags, "__builtin_spe_evstwwe", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWWE);
7361 def_builtin (target_flags, "__builtin_spe_evstwwo", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWWO);
00332c9f
AH		 7362 def_builtin (target_flags, "__builtin_spe_evsplatfi", v2si_ftype_signed_char, SPE_BUILTIN_EVSPLATFI);
7363 def_builtin (target_flags, "__builtin_spe_evsplati", v2si_ftype_signed_char, SPE_BUILTIN_EVSPLATI);
a3170dc6
AH		 7364
7365 /* Loads. */
7366 def_builtin (target_flags, "__builtin_spe_evlddx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDDX);
7367 def_builtin (target_flags, "__builtin_spe_evldwx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDWX);
7368 def_builtin (target_flags, "__builtin_spe_evldhx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDHX);
7369 def_builtin (target_flags, "__builtin_spe_evlwhex", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHEX);
7370 def_builtin (target_flags, "__builtin_spe_evlwhoux", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOUX);
7371 def_builtin (target_flags, "__builtin_spe_evlwhosx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOSX);
7372 def_builtin (target_flags, "__builtin_spe_evlwwsplatx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWWSPLATX);
7373 def_builtin (target_flags, "__builtin_spe_evlwhsplatx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHSPLATX);
7374 def_builtin (target_flags, "__builtin_spe_evlhhesplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHESPLATX);
7375 def_builtin (target_flags, "__builtin_spe_evlhhousplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOUSPLATX);
7376 def_builtin (target_flags, "__builtin_spe_evlhhossplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOSSPLATX);
7377 def_builtin (target_flags, "__builtin_spe_evldd", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDD);
7378 def_builtin (target_flags, "__builtin_spe_evldw", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDW);
7379 def_builtin (target_flags, "__builtin_spe_evldh", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDH);
7380 def_builtin (target_flags, "__builtin_spe_evlhhesplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHESPLAT);
7381 def_builtin (target_flags, "__builtin_spe_evlhhossplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOSSPLAT);
7382 def_builtin (target_flags, "__builtin_spe_evlhhousplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOUSPLAT);
7383 def_builtin (target_flags, "__builtin_spe_evlwhe", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHE);
7384 def_builtin (target_flags, "__builtin_spe_evlwhos", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOS);
7385 def_builtin (target_flags, "__builtin_spe_evlwhou", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOU);
7386 def_builtin (target_flags, "__builtin_spe_evlwhsplat", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHSPLAT);
7387 def_builtin (target_flags, "__builtin_spe_evlwwsplat", v2si_ftype_puint_int, SPE_BUILTIN_EVLWWSPLAT);
7388
7389 /* Predicates. */
7390 d = (struct builtin_description *) bdesc_spe_predicates;
7391 for (i = 0; i < ARRAY_SIZE (bdesc_spe_predicates); ++i, d++)
7392 {
7393 tree type;
7394
7395 switch (insn_data[d->icode].operand[1].mode)
7396 {
7397 case V2SImode:
7398 type = int_ftype_int_v2si_v2si;
7399 break;
7400 case V2SFmode:
7401 type = int_ftype_int_v2sf_v2sf;
7402 break;
7403 default:
7404 abort ();
7405 }
7406
7407 def_builtin (d->mask, d->name, type, d->code);
7408 }
7409
7410 /* Evsel predicates. */
7411 d = (struct builtin_description *) bdesc_spe_evsel;
7412 for (i = 0; i < ARRAY_SIZE (bdesc_spe_evsel); ++i, d++)
7413 {
7414 tree type;
7415
7416 switch (insn_data[d->icode].operand[1].mode)
7417 {
7418 case V2SImode:
7419 type = v2si_ftype_4_v2si;
7420 break;
7421 case V2SFmode:
7422 type = v2sf_ftype_4_v2sf;
7423 break;
7424 default:
7425 abort ();
7426 }
7427
7428 def_builtin (d->mask, d->name, type, d->code);
7429 }
7430}
7431
7432static void
863d938c 7433altivec_init_builtins (void)
a3170dc6
AH		 7434{
7435 struct builtin_description *d;
7436 struct builtin_description_predicates *dp;
7437 size_t i;
7438 tree pfloat_type_node = build_pointer_type (float_type_node);
7439 tree pint_type_node = build_pointer_type (integer_type_node);
7440 tree pshort_type_node = build_pointer_type (short_integer_type_node);
7441 tree pchar_type_node = build_pointer_type (char_type_node);
7442
7443 tree pvoid_type_node = build_pointer_type (void_type_node);
7444
0dbc3651
ZW		 7445 tree pcfloat_type_node = build_pointer_type (build_qualified_type (float_type_node, TYPE_QUAL_CONST));
7446 tree pcint_type_node = build_pointer_type (build_qualified_type (integer_type_node, TYPE_QUAL_CONST));
7447 tree pcshort_type_node = build_pointer_type (build_qualified_type (short_integer_type_node, TYPE_QUAL_CONST));
7448 tree pcchar_type_node = build_pointer_type (build_qualified_type (char_type_node, TYPE_QUAL_CONST));
7449
7450 tree pcvoid_type_node = build_pointer_type (build_qualified_type (void_type_node, TYPE_QUAL_CONST));
7451
a3170dc6
AH		 7452 tree int_ftype_int_v4si_v4si
7453 = build_function_type_list (integer_type_node,
7454 integer_type_node, V4SI_type_node,
7455 V4SI_type_node, NULL_TREE);
0dbc3651
ZW		 7456 tree v4sf_ftype_pcfloat
7457 = build_function_type_list (V4SF_type_node, pcfloat_type_node, NULL_TREE);
a3170dc6 7458 tree void_ftype_pfloat_v4sf
b4de2f7d 7459 = build_function_type_list (void_type_node,
a3170dc6 7460 pfloat_type_node, V4SF_type_node, NULL_TREE);
0dbc3651
ZW		 7461 tree v4si_ftype_pcint
7462 = build_function_type_list (V4SI_type_node, pcint_type_node, NULL_TREE);
7463 tree void_ftype_pint_v4si
b4de2f7d
AH		 7464 = build_function_type_list (void_type_node,
7465 pint_type_node, V4SI_type_node, NULL_TREE);
0dbc3651
ZW		 7466 tree v8hi_ftype_pcshort
7467 = build_function_type_list (V8HI_type_node, pcshort_type_node, NULL_TREE);
f18c054f 7468 tree void_ftype_pshort_v8hi
b4de2f7d
AH		 7469 = build_function_type_list (void_type_node,
7470 pshort_type_node, V8HI_type_node, NULL_TREE);
0dbc3651
ZW		 7471 tree v16qi_ftype_pcchar
7472 = build_function_type_list (V16QI_type_node, pcchar_type_node, NULL_TREE);
f18c054f 7473 tree void_ftype_pchar_v16qi
b4de2f7d
AH		 7474 = build_function_type_list (void_type_node,
7475 pchar_type_node, V16QI_type_node, NULL_TREE);
95385cbb 7476 tree void_ftype_v4si
b4de2f7d 7477 = build_function_type_list (void_type_node, V4SI_type_node, NULL_TREE);
a3170dc6
AH		 7478 tree v8hi_ftype_void
7479 = build_function_type (V8HI_type_node, void_list_node);
7480 tree void_ftype_void
7481 = build_function_type (void_type_node, void_list_node);
e34b6648
JJ		 7482 tree void_ftype_int
7483 = build_function_type_list (void_type_node, integer_type_node, NULL_TREE);
0dbc3651 7484
b4a62fa0 7485 tree v16qi_ftype_long_pcvoid
a3170dc6 7486 = build_function_type_list (V16QI_type_node,
b4a62fa0
SB		 7487 long_integer_type_node, pcvoid_type_node, NULL_TREE);
7488 tree v8hi_ftype_long_pcvoid
a3170dc6 7489 = build_function_type_list (V8HI_type_node,
b4a62fa0
SB		 7490 long_integer_type_node, pcvoid_type_node, NULL_TREE);
7491 tree v4si_ftype_long_pcvoid
a3170dc6 7492 = build_function_type_list (V4SI_type_node,
b4a62fa0 7493 long_integer_type_node, pcvoid_type_node, NULL_TREE);
0dbc3651 7494
b4a62fa0 7495 tree void_ftype_v4si_long_pvoid
b4de2f7d 7496 = build_function_type_list (void_type_node,
b4a62fa0 7497 V4SI_type_node, long_integer_type_node,
b4de2f7d 7498 pvoid_type_node, NULL_TREE);
b4a62fa0 7499 tree void_ftype_v16qi_long_pvoid
b4de2f7d 7500 = build_function_type_list (void_type_node,
b4a62fa0 7501 V16QI_type_node, long_integer_type_node,
b4de2f7d 7502 pvoid_type_node, NULL_TREE);
b4a62fa0 7503 tree void_ftype_v8hi_long_pvoid
b4de2f7d 7504 = build_function_type_list (void_type_node,
b4a62fa0 7505 V8HI_type_node, long_integer_type_node,
b4de2f7d 7506 pvoid_type_node, NULL_TREE);
a3170dc6
AH		 7507 tree int_ftype_int_v8hi_v8hi
7508 = build_function_type_list (integer_type_node,
7509 integer_type_node, V8HI_type_node,
7510 V8HI_type_node, NULL_TREE);
7511 tree int_ftype_int_v16qi_v16qi
7512 = build_function_type_list (integer_type_node,
7513 integer_type_node, V16QI_type_node,
7514 V16QI_type_node, NULL_TREE);
7515 tree int_ftype_int_v4sf_v4sf
7516 = build_function_type_list (integer_type_node,
7517 integer_type_node, V4SF_type_node,
7518 V4SF_type_node, NULL_TREE);
7519 tree v4si_ftype_v4si
7520 = build_function_type_list (V4SI_type_node, V4SI_type_node, NULL_TREE);
7521 tree v8hi_ftype_v8hi
7522 = build_function_type_list (V8HI_type_node, V8HI_type_node, NULL_TREE);
7523 tree v16qi_ftype_v16qi
7524 = build_function_type_list (V16QI_type_node, V16QI_type_node, NULL_TREE);
7525 tree v4sf_ftype_v4sf
7526 = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE);
8bb418a3 7527 tree void_ftype_pcvoid_int_int
a3170dc6 7528 = build_function_type_list (void_type_node,
0dbc3651 7529 pcvoid_type_node, integer_type_node,
8bb418a3
ZL		 7530 integer_type_node, NULL_TREE);
7531 tree int_ftype_pcchar
7532 = build_function_type_list (integer_type_node,
7533 pcchar_type_node, NULL_TREE);
7534
0dbc3651
ZW		 7535 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_4sf", v4sf_ftype_pcfloat,
7536 ALTIVEC_BUILTIN_LD_INTERNAL_4sf);
7537 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_4sf", void_ftype_pfloat_v4sf,
7538 ALTIVEC_BUILTIN_ST_INTERNAL_4sf);
7539 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_4si", v4si_ftype_pcint,
7540 ALTIVEC_BUILTIN_LD_INTERNAL_4si);
7541 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_4si", void_ftype_pint_v4si,
7542 ALTIVEC_BUILTIN_ST_INTERNAL_4si);
7543 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_8hi", v8hi_ftype_pcshort,
7544 ALTIVEC_BUILTIN_LD_INTERNAL_8hi);
7545 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_8hi", void_ftype_pshort_v8hi,
7546 ALTIVEC_BUILTIN_ST_INTERNAL_8hi);
7547 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_16qi", v16qi_ftype_pcchar,
7548 ALTIVEC_BUILTIN_LD_INTERNAL_16qi);
7549 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_16qi", void_ftype_pchar_v16qi,
7550 ALTIVEC_BUILTIN_ST_INTERNAL_16qi);
a3170dc6
AH		 7551 def_builtin (MASK_ALTIVEC, "__builtin_altivec_mtvscr", void_ftype_v4si, ALTIVEC_BUILTIN_MTVSCR);
7552 def_builtin (MASK_ALTIVEC, "__builtin_altivec_mfvscr", v8hi_ftype_void, ALTIVEC_BUILTIN_MFVSCR);
7553 def_builtin (MASK_ALTIVEC, "__builtin_altivec_dssall", void_ftype_void, ALTIVEC_BUILTIN_DSSALL);
e34b6648 7554 def_builtin (MASK_ALTIVEC, "__builtin_altivec_dss", void_ftype_int, ALTIVEC_BUILTIN_DSS);
b4a62fa0
SB		 7555 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvsl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSL);
7556 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvsr", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSR);
7557 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvebx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEBX);
7558 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvehx", v8hi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEHX);
7559 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvewx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEWX);
7560 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvxl", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVXL);
7561 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVX);
7562 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVX);
7563 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvewx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVEWX);
7564 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvxl", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVXL);
7565 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvebx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVEBX);
7566 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvehx", void_ftype_v8hi_long_pvoid, ALTIVEC_BUILTIN_STVEHX);
a3170dc6 7567
8bb418a3
ZL		 7568 /* See altivec.h for usage of "__builtin_altivec_compiletime_error". */
7569 def_builtin (MASK_ALTIVEC, "__builtin_altivec_compiletime_error", int_ftype_pcchar,
7570 ALTIVEC_BUILTIN_COMPILETIME_ERROR);
7571
a3170dc6
AH		 7572 /* Add the DST variants. */
7573 d = (struct builtin_description *) bdesc_dst;
7574 for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++)
8bb418a3 7575 def_builtin (d->mask, d->name, void_ftype_pcvoid_int_int, d->code);
a3170dc6
AH		 7576
7577 /* Initialize the predicates. */
7578 dp = (struct builtin_description_predicates *) bdesc_altivec_preds;
7579 for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, dp++)
7580 {
7581 enum machine_mode mode1;
7582 tree type;
7583
7584 mode1 = insn_data[dp->icode].operand[1].mode;
7585
7586 switch (mode1)
7587 {
7588 case V4SImode:
7589 type = int_ftype_int_v4si_v4si;
7590 break;
7591 case V8HImode:
7592 type = int_ftype_int_v8hi_v8hi;
7593 break;
7594 case V16QImode:
7595 type = int_ftype_int_v16qi_v16qi;
7596 break;
7597 case V4SFmode:
7598 type = int_ftype_int_v4sf_v4sf;
7599 break;
7600 default:
7601 abort ();
7602 }
f676971a 7603
a3170dc6
AH		 7604 def_builtin (dp->mask, dp->name, type, dp->code);
7605 }
7606
7607 /* Initialize the abs* operators. */
7608 d = (struct builtin_description *) bdesc_abs;
7609 for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++)
7610 {
7611 enum machine_mode mode0;
7612 tree type;
7613
7614 mode0 = insn_data[d->icode].operand[0].mode;
7615
7616 switch (mode0)
7617 {
7618 case V4SImode:
7619 type = v4si_ftype_v4si;
7620 break;
7621 case V8HImode:
7622 type = v8hi_ftype_v8hi;
7623 break;
7624 case V16QImode:
7625 type = v16qi_ftype_v16qi;
7626 break;
7627 case V4SFmode:
7628 type = v4sf_ftype_v4sf;
7629 break;
7630 default:
7631 abort ();
7632 }
f676971a 7633
a3170dc6
AH		 7634 def_builtin (d->mask, d->name, type, d->code);
7635 }
7ccf35ed 7636
13c62176
DN		 7637 if (TARGET_ALTIVEC)
7638 {
7639 tree decl;
7640
7641 /* Initialize target builtin that implements
7642 targetm.vectorize.builtin_mask_for_load. */
7643
7644 decl = lang_hooks.builtin_function ("__builtin_altivec_mask_for_load",
9390387d
AM		 7645 v16qi_ftype_long_pcvoid,
7646 ALTIVEC_BUILTIN_MASK_FOR_LOAD,
7647 BUILT_IN_MD, NULL, NULL_TREE);
13c62176
DN		 7648 /* Record the decl. Will be used by rs6000_builtin_mask_for_load. */
7649 altivec_builtin_mask_for_load = decl;
13c62176 7650 }
a3170dc6
AH		 7651}
7652
7653static void
863d938c 7654rs6000_common_init_builtins (void)
a3170dc6
AH		 7655{
7656 struct builtin_description *d;
7657 size_t i;
7658
7659 tree v4sf_ftype_v4sf_v4sf_v16qi
7660 = build_function_type_list (V4SF_type_node,
7661 V4SF_type_node, V4SF_type_node,
7662 V16QI_type_node, NULL_TREE);
7663 tree v4si_ftype_v4si_v4si_v16qi
7664 = build_function_type_list (V4SI_type_node,
7665 V4SI_type_node, V4SI_type_node,
7666 V16QI_type_node, NULL_TREE);
7667 tree v8hi_ftype_v8hi_v8hi_v16qi
7668 = build_function_type_list (V8HI_type_node,
7669 V8HI_type_node, V8HI_type_node,
7670 V16QI_type_node, NULL_TREE);
7671 tree v16qi_ftype_v16qi_v16qi_v16qi
7672 = build_function_type_list (V16QI_type_node,
7673 V16QI_type_node, V16QI_type_node,
7674 V16QI_type_node, NULL_TREE);
b9e4e5d1
ZL		 7675 tree v4si_ftype_int
7676 = build_function_type_list (V4SI_type_node, integer_type_node, NULL_TREE);
7677 tree v8hi_ftype_int
7678 = build_function_type_list (V8HI_type_node, integer_type_node, NULL_TREE);
7679 tree v16qi_ftype_int
7680 = build_function_type_list (V16QI_type_node, integer_type_node, NULL_TREE);
a3170dc6
AH		 7681 tree v8hi_ftype_v16qi
7682 = build_function_type_list (V8HI_type_node, V16QI_type_node, NULL_TREE);
7683 tree v4sf_ftype_v4sf
7684 = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE);
7685
7686 tree v2si_ftype_v2si_v2si
2abe3e28
AH		 7687 = build_function_type_list (opaque_V2SI_type_node,
7688 opaque_V2SI_type_node,
7689 opaque_V2SI_type_node, NULL_TREE);
a3170dc6
AH		 7690
7691 tree v2sf_ftype_v2sf_v2sf
2abe3e28
AH		 7692 = build_function_type_list (opaque_V2SF_type_node,
7693 opaque_V2SF_type_node,
7694 opaque_V2SF_type_node, NULL_TREE);
a3170dc6
AH		 7695
7696 tree v2si_ftype_int_int
2abe3e28 7697 = build_function_type_list (opaque_V2SI_type_node,
a3170dc6
AH		 7698 integer_type_node, integer_type_node,
7699 NULL_TREE);
7700
7701 tree v2si_ftype_v2si
2abe3e28
AH		 7702 = build_function_type_list (opaque_V2SI_type_node,
7703 opaque_V2SI_type_node, NULL_TREE);
a3170dc6
AH		 7704
7705 tree v2sf_ftype_v2sf
2abe3e28
AH		 7706 = build_function_type_list (opaque_V2SF_type_node,
7707 opaque_V2SF_type_node, NULL_TREE);
f676971a 7708
a3170dc6 7709 tree v2sf_ftype_v2si
2abe3e28
AH		 7710 = build_function_type_list (opaque_V2SF_type_node,
7711 opaque_V2SI_type_node, NULL_TREE);
a3170dc6
AH		 7712
7713 tree v2si_ftype_v2sf
2abe3e28
AH		 7714 = build_function_type_list (opaque_V2SI_type_node,
7715 opaque_V2SF_type_node, NULL_TREE);
a3170dc6
AH		 7716
7717 tree v2si_ftype_v2si_char
2abe3e28
AH		 7718 = build_function_type_list (opaque_V2SI_type_node,
7719 opaque_V2SI_type_node,
7720 char_type_node, NULL_TREE);
a3170dc6
AH		 7721
7722 tree v2si_ftype_int_char
2abe3e28 7723 = build_function_type_list (opaque_V2SI_type_node,
a3170dc6
AH		 7724 integer_type_node, char_type_node, NULL_TREE);
7725
7726 tree v2si_ftype_char
2abe3e28
AH		 7727 = build_function_type_list (opaque_V2SI_type_node,
7728 char_type_node, NULL_TREE);
a3170dc6
AH		 7729
7730 tree int_ftype_int_int
7731 = build_function_type_list (integer_type_node,
7732 integer_type_node, integer_type_node,
7733 NULL_TREE);
95385cbb 7734
0ac081f6 7735 tree v4si_ftype_v4si_v4si
b4de2f7d
AH		 7736 = build_function_type_list (V4SI_type_node,
7737 V4SI_type_node, V4SI_type_node, NULL_TREE);
b9e4e5d1 7738 tree v4sf_ftype_v4si_int
b4de2f7d 7739 = build_function_type_list (V4SF_type_node,
b9e4e5d1
ZL		 7740 V4SI_type_node, integer_type_node, NULL_TREE);
7741 tree v4si_ftype_v4sf_int
b4de2f7d 7742 = build_function_type_list (V4SI_type_node,
b9e4e5d1
ZL		 7743 V4SF_type_node, integer_type_node, NULL_TREE);
7744 tree v4si_ftype_v4si_int
b4de2f7d 7745 = build_function_type_list (V4SI_type_node,
b9e4e5d1
ZL		 7746 V4SI_type_node, integer_type_node, NULL_TREE);
7747 tree v8hi_ftype_v8hi_int
b4de2f7d 7748 = build_function_type_list (V8HI_type_node,
b9e4e5d1
ZL		 7749 V8HI_type_node, integer_type_node, NULL_TREE);
7750 tree v16qi_ftype_v16qi_int
b4de2f7d 7751 = build_function_type_list (V16QI_type_node,
b9e4e5d1
ZL		 7752 V16QI_type_node, integer_type_node, NULL_TREE);
7753 tree v16qi_ftype_v16qi_v16qi_int
b4de2f7d
AH		 7754 = build_function_type_list (V16QI_type_node,
7755 V16QI_type_node, V16QI_type_node,
b9e4e5d1
ZL		 7756 integer_type_node, NULL_TREE);
7757 tree v8hi_ftype_v8hi_v8hi_int
b4de2f7d
AH		 7758 = build_function_type_list (V8HI_type_node,
7759 V8HI_type_node, V8HI_type_node,
b9e4e5d1
ZL		 7760 integer_type_node, NULL_TREE);
7761 tree v4si_ftype_v4si_v4si_int
b4de2f7d
AH		 7762 = build_function_type_list (V4SI_type_node,
7763 V4SI_type_node, V4SI_type_node,
b9e4e5d1
ZL		 7764 integer_type_node, NULL_TREE);
7765 tree v4sf_ftype_v4sf_v4sf_int
b4de2f7d
AH		 7766 = build_function_type_list (V4SF_type_node,
7767 V4SF_type_node, V4SF_type_node,
b9e4e5d1 7768 integer_type_node, NULL_TREE);
0ac081f6 7769 tree v4sf_ftype_v4sf_v4sf
b4de2f7d
AH		 7770 = build_function_type_list (V4SF_type_node,
7771 V4SF_type_node, V4SF_type_node, NULL_TREE);
617e0e1d 7772 tree v4sf_ftype_v4sf_v4sf_v4si
b4de2f7d
AH		 7773 = build_function_type_list (V4SF_type_node,
7774 V4SF_type_node, V4SF_type_node,
7775 V4SI_type_node, NULL_TREE);
2212663f 7776 tree v4sf_ftype_v4sf_v4sf_v4sf
b4de2f7d
AH		 7777 = build_function_type_list (V4SF_type_node,
7778 V4SF_type_node, V4SF_type_node,
7779 V4SF_type_node, NULL_TREE);
f676971a 7780 tree v4si_ftype_v4si_v4si_v4si
b4de2f7d
AH		 7781 = build_function_type_list (V4SI_type_node,
7782 V4SI_type_node, V4SI_type_node,
7783 V4SI_type_node, NULL_TREE);
0ac081f6 7784 tree v8hi_ftype_v8hi_v8hi
b4de2f7d
AH		 7785 = build_function_type_list (V8HI_type_node,
7786 V8HI_type_node, V8HI_type_node, NULL_TREE);
2212663f 7787 tree v8hi_ftype_v8hi_v8hi_v8hi
b4de2f7d
AH		 7788 = build_function_type_list (V8HI_type_node,
7789 V8HI_type_node, V8HI_type_node,
7790 V8HI_type_node, NULL_TREE);
c4ad648e 7791 tree v4si_ftype_v8hi_v8hi_v4si
b4de2f7d
AH		 7792 = build_function_type_list (V4SI_type_node,
7793 V8HI_type_node, V8HI_type_node,
7794 V4SI_type_node, NULL_TREE);
c4ad648e 7795 tree v4si_ftype_v16qi_v16qi_v4si
b4de2f7d
AH		 7796 = build_function_type_list (V4SI_type_node,
7797 V16QI_type_node, V16QI_type_node,
7798 V4SI_type_node, NULL_TREE);
0ac081f6 7799 tree v16qi_ftype_v16qi_v16qi
b4de2f7d
AH		 7800 = build_function_type_list (V16QI_type_node,
7801 V16QI_type_node, V16QI_type_node, NULL_TREE);
0ac081f6 7802 tree v4si_ftype_v4sf_v4sf
b4de2f7d
AH		 7803 = build_function_type_list (V4SI_type_node,
7804 V4SF_type_node, V4SF_type_node, NULL_TREE);
0ac081f6 7805 tree v8hi_ftype_v16qi_v16qi
b4de2f7d
AH		 7806 = build_function_type_list (V8HI_type_node,
7807 V16QI_type_node, V16QI_type_node, NULL_TREE);
0ac081f6 7808 tree v4si_ftype_v8hi_v8hi
b4de2f7d
AH		 7809 = build_function_type_list (V4SI_type_node,
7810 V8HI_type_node, V8HI_type_node, NULL_TREE);
0ac081f6 7811 tree v8hi_ftype_v4si_v4si
b4de2f7d
AH		 7812 = build_function_type_list (V8HI_type_node,
7813 V4SI_type_node, V4SI_type_node, NULL_TREE);
0ac081f6 7814 tree v16qi_ftype_v8hi_v8hi
b4de2f7d
AH		 7815 = build_function_type_list (V16QI_type_node,
7816 V8HI_type_node, V8HI_type_node, NULL_TREE);
0ac081f6 7817 tree v4si_ftype_v16qi_v4si
b4de2f7d
AH		 7818 = build_function_type_list (V4SI_type_node,
7819 V16QI_type_node, V4SI_type_node, NULL_TREE);
fa066a23 7820 tree v4si_ftype_v16qi_v16qi
b4de2f7d
AH		 7821 = build_function_type_list (V4SI_type_node,
7822 V16QI_type_node, V16QI_type_node, NULL_TREE);
0ac081f6 7823 tree v4si_ftype_v8hi_v4si
b4de2f7d
AH		 7824 = build_function_type_list (V4SI_type_node,
7825 V8HI_type_node, V4SI_type_node, NULL_TREE);
a3170dc6
AH		 7826 tree v4si_ftype_v8hi
7827 = build_function_type_list (V4SI_type_node, V8HI_type_node, NULL_TREE);
7828 tree int_ftype_v4si_v4si
7829 = build_function_type_list (integer_type_node,
7830 V4SI_type_node, V4SI_type_node, NULL_TREE);
7831 tree int_ftype_v4sf_v4sf
7832 = build_function_type_list (integer_type_node,
7833 V4SF_type_node, V4SF_type_node, NULL_TREE);
7834 tree int_ftype_v16qi_v16qi
7835 = build_function_type_list (integer_type_node,
7836 V16QI_type_node, V16QI_type_node, NULL_TREE);
0ac081f6 7837 tree int_ftype_v8hi_v8hi
b4de2f7d
AH		 7838 = build_function_type_list (integer_type_node,
7839 V8HI_type_node, V8HI_type_node, NULL_TREE);
0ac081f6 7840
6f317ef3 7841 /* Add the simple ternary operators. */
2212663f 7842 d = (struct builtin_description *) bdesc_3arg;
ca7558fc 7843 for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++)
2212663f 7844 {
f676971a 7845
2212663f
DB		 7846 enum machine_mode mode0, mode1, mode2, mode3;
7847 tree type;
7848
0559cc77 7849 if (d->name == 0 || d->icode == CODE_FOR_nothing)
2212663f 7850 continue;
f676971a 7851
2212663f
DB		 7852 mode0 = insn_data[d->icode].operand[0].mode;
7853 mode1 = insn_data[d->icode].operand[1].mode;
7854 mode2 = insn_data[d->icode].operand[2].mode;
7855 mode3 = insn_data[d->icode].operand[3].mode;
f676971a 7856
2212663f
DB		 7857 /* When all four are of the same mode. */
7858 if (mode0 == mode1 && mode1 == mode2 && mode2 == mode3)
7859 {
7860 switch (mode0)
7861 {
617e0e1d
DB		 7862 case V4SImode:
7863 type = v4si_ftype_v4si_v4si_v4si;
7864 break;
2212663f
DB		 7865 case V4SFmode:
7866 type = v4sf_ftype_v4sf_v4sf_v4sf;
7867 break;
7868 case V8HImode:
7869 type = v8hi_ftype_v8hi_v8hi_v8hi;
f676971a 7870 break;
2212663f
DB		 7871 case V16QImode:
7872 type = v16qi_ftype_v16qi_v16qi_v16qi;
f676971a 7873 break;
2212663f 7874 default:
9390387d 7875 abort ();
2212663f
DB		 7876 }
7877 }
7878 else if (mode0 == mode1 && mode1 == mode2 && mode3 == V16QImode)
c4ad648e 7879 {
2212663f
DB		 7880 switch (mode0)
7881 {
7882 case V4SImode:
7883 type = v4si_ftype_v4si_v4si_v16qi;
7884 break;
7885 case V4SFmode:
7886 type = v4sf_ftype_v4sf_v4sf_v16qi;
7887 break;
7888 case V8HImode:
7889 type = v8hi_ftype_v8hi_v8hi_v16qi;
f676971a 7890 break;
2212663f
DB		 7891 case V16QImode:
7892 type = v16qi_ftype_v16qi_v16qi_v16qi;
f676971a 7893 break;
2212663f 7894 default:
9390387d 7895 abort ();
2212663f
DB		 7896 }
7897 }
f676971a 7898 else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V16QImode
2212663f 7899 && mode3 == V4SImode)
24408032 7900 type = v4si_ftype_v16qi_v16qi_v4si;
f676971a 7901 else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V8HImode
2212663f 7902 && mode3 == V4SImode)
24408032 7903 type = v4si_ftype_v8hi_v8hi_v4si;
f676971a 7904 else if (mode0 == V4SFmode && mode1 == V4SFmode && mode2 == V4SFmode
617e0e1d 7905 && mode3 == V4SImode)
24408032
AH		 7906 type = v4sf_ftype_v4sf_v4sf_v4si;
7907
7908 /* vchar, vchar, vchar, 4 bit literal. */
7909 else if (mode0 == V16QImode && mode1 == mode0 && mode2 == mode0
7910 && mode3 == QImode)
b9e4e5d1 7911 type = v16qi_ftype_v16qi_v16qi_int;
24408032
AH		 7912
7913 /* vshort, vshort, vshort, 4 bit literal. */
7914 else if (mode0 == V8HImode && mode1 == mode0 && mode2 == mode0
7915 && mode3 == QImode)
b9e4e5d1 7916 type = v8hi_ftype_v8hi_v8hi_int;
24408032
AH		 7917
7918 /* vint, vint, vint, 4 bit literal. */
7919 else if (mode0 == V4SImode && mode1 == mode0 && mode2 == mode0
7920 && mode3 == QImode)
b9e4e5d1 7921 type = v4si_ftype_v4si_v4si_int;
24408032
AH		 7922
7923 /* vfloat, vfloat, vfloat, 4 bit literal. */
7924 else if (mode0 == V4SFmode && mode1 == mode0 && mode2 == mode0
7925 && mode3 == QImode)
b9e4e5d1 7926 type = v4sf_ftype_v4sf_v4sf_int;
24408032 7927
2212663f
DB		 7928 else
7929 abort ();
7930
7931 def_builtin (d->mask, d->name, type, d->code);
7932 }
7933
0ac081f6 7934 /* Add the simple binary operators. */
00b960c7 7935 d = (struct builtin_description *) bdesc_2arg;
ca7558fc 7936 for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
0ac081f6
AH		 7937 {
7938 enum machine_mode mode0, mode1, mode2;
7939 tree type;
7940
0559cc77 7941 if (d->name == 0 || d->icode == CODE_FOR_nothing)
0ac081f6 7942 continue;
f676971a 7943
0ac081f6
AH		 7944 mode0 = insn_data[d->icode].operand[0].mode;
7945 mode1 = insn_data[d->icode].operand[1].mode;
7946 mode2 = insn_data[d->icode].operand[2].mode;
7947
7948 /* When all three operands are of the same mode. */
7949 if (mode0 == mode1 && mode1 == mode2)
7950 {
7951 switch (mode0)
7952 {
7953 case V4SFmode:
7954 type = v4sf_ftype_v4sf_v4sf;
7955 break;
7956 case V4SImode:
7957 type = v4si_ftype_v4si_v4si;
7958 break;
7959 case V16QImode:
7960 type = v16qi_ftype_v16qi_v16qi;
7961 break;
7962 case V8HImode:
7963 type = v8hi_ftype_v8hi_v8hi;
7964 break;
a3170dc6
AH		 7965 case V2SImode:
7966 type = v2si_ftype_v2si_v2si;
7967 break;
7968 case V2SFmode:
7969 type = v2sf_ftype_v2sf_v2sf;
7970 break;
7971 case SImode:
7972 type = int_ftype_int_int;
7973 break;
0ac081f6
AH		 7974 default:
7975 abort ();
7976 }
7977 }
7978
7979 /* A few other combos we really don't want to do manually. */
7980
7981 /* vint, vfloat, vfloat. */
7982 else if (mode0 == V4SImode && mode1 == V4SFmode && mode2 == V4SFmode)
7983 type = v4si_ftype_v4sf_v4sf;
7984
7985 /* vshort, vchar, vchar. */
7986 else if (mode0 == V8HImode && mode1 == V16QImode && mode2 == V16QImode)
7987 type = v8hi_ftype_v16qi_v16qi;
7988
7989 /* vint, vshort, vshort. */
7990 else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V8HImode)
7991 type = v4si_ftype_v8hi_v8hi;
7992
7993 /* vshort, vint, vint. */
7994 else if (mode0 == V8HImode && mode1 == V4SImode && mode2 == V4SImode)
7995 type = v8hi_ftype_v4si_v4si;
7996
7997 /* vchar, vshort, vshort. */
7998 else if (mode0 == V16QImode && mode1 == V8HImode && mode2 == V8HImode)
7999 type = v16qi_ftype_v8hi_v8hi;
8000
8001 /* vint, vchar, vint. */
8002 else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V4SImode)
8003 type = v4si_ftype_v16qi_v4si;
8004
fa066a23
AH		 8005 /* vint, vchar, vchar. */
8006 else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V16QImode)
8007 type = v4si_ftype_v16qi_v16qi;
8008
0ac081f6
AH		 8009 /* vint, vshort, vint. */
8010 else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V4SImode)
8011 type = v4si_ftype_v8hi_v4si;
f676971a 8012
2212663f
DB		 8013 /* vint, vint, 5 bit literal. */
8014 else if (mode0 == V4SImode && mode1 == V4SImode && mode2 == QImode)
b9e4e5d1 8015 type = v4si_ftype_v4si_int;
f676971a 8016
2212663f
DB		 8017 /* vshort, vshort, 5 bit literal. */
8018 else if (mode0 == V8HImode && mode1 == V8HImode && mode2 == QImode)
b9e4e5d1 8019 type = v8hi_ftype_v8hi_int;
f676971a 8020
2212663f
DB		 8021 /* vchar, vchar, 5 bit literal. */
8022 else if (mode0 == V16QImode && mode1 == V16QImode && mode2 == QImode)
b9e4e5d1 8023 type = v16qi_ftype_v16qi_int;
0ac081f6 8024
617e0e1d
DB		 8025 /* vfloat, vint, 5 bit literal. */
8026 else if (mode0 == V4SFmode && mode1 == V4SImode && mode2 == QImode)
b9e4e5d1 8027 type = v4sf_ftype_v4si_int;
f676971a 8028
617e0e1d
DB		 8029 /* vint, vfloat, 5 bit literal. */
8030 else if (mode0 == V4SImode && mode1 == V4SFmode && mode2 == QImode)
b9e4e5d1 8031 type = v4si_ftype_v4sf_int;
617e0e1d 8032
a3170dc6
AH		 8033 else if (mode0 == V2SImode && mode1 == SImode && mode2 == SImode)
8034 type = v2si_ftype_int_int;
8035
8036 else if (mode0 == V2SImode && mode1 == V2SImode && mode2 == QImode)
8037 type = v2si_ftype_v2si_char;
8038
8039 else if (mode0 == V2SImode && mode1 == SImode && mode2 == QImode)
8040 type = v2si_ftype_int_char;
8041
0ac081f6
AH		 8042 /* int, x, x. */
8043 else if (mode0 == SImode)
8044 {
8045 switch (mode1)
8046 {
8047 case V4SImode:
8048 type = int_ftype_v4si_v4si;
8049 break;
8050 case V4SFmode:
8051 type = int_ftype_v4sf_v4sf;
8052 break;
8053 case V16QImode:
8054 type = int_ftype_v16qi_v16qi;
8055 break;
8056 case V8HImode:
8057 type = int_ftype_v8hi_v8hi;
8058 break;
8059 default:
8060 abort ();
8061 }
8062 }
8063
8064 else
8065 abort ();
8066
2212663f
DB		 8067 def_builtin (d->mask, d->name, type, d->code);
8068 }
24408032 8069
2212663f
DB		 8070 /* Add the simple unary operators. */
8071 d = (struct builtin_description *) bdesc_1arg;
ca7558fc 8072 for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
2212663f
DB		 8073 {
8074 enum machine_mode mode0, mode1;
8075 tree type;
8076
0559cc77 8077 if (d->name == 0 || d->icode == CODE_FOR_nothing)
2212663f 8078 continue;
f676971a 8079
2212663f
DB		 8080 mode0 = insn_data[d->icode].operand[0].mode;
8081 mode1 = insn_data[d->icode].operand[1].mode;
8082
8083 if (mode0 == V4SImode && mode1 == QImode)
c4ad648e 8084 type = v4si_ftype_int;
2212663f 8085 else if (mode0 == V8HImode && mode1 == QImode)
c4ad648e 8086 type = v8hi_ftype_int;
2212663f 8087 else if (mode0 == V16QImode && mode1 == QImode)
c4ad648e 8088 type = v16qi_ftype_int;
617e0e1d
DB		 8089 else if (mode0 == V4SFmode && mode1 == V4SFmode)
8090 type = v4sf_ftype_v4sf;
20e26713
AH		 8091 else if (mode0 == V8HImode && mode1 == V16QImode)
8092 type = v8hi_ftype_v16qi;
8093 else if (mode0 == V4SImode && mode1 == V8HImode)
8094 type = v4si_ftype_v8hi;
a3170dc6
AH		 8095 else if (mode0 == V2SImode && mode1 == V2SImode)
8096 type = v2si_ftype_v2si;
8097 else if (mode0 == V2SFmode && mode1 == V2SFmode)
8098 type = v2sf_ftype_v2sf;
8099 else if (mode0 == V2SFmode && mode1 == V2SImode)
8100 type = v2sf_ftype_v2si;
8101 else if (mode0 == V2SImode && mode1 == V2SFmode)
8102 type = v2si_ftype_v2sf;
8103 else if (mode0 == V2SImode && mode1 == QImode)
8104 type = v2si_ftype_char;
2212663f
DB		 8105 else
8106 abort ();
8107
0ac081f6
AH		 8108 def_builtin (d->mask, d->name, type, d->code);
8109 }
8110}
8111
c15c90bb
ZW		 8112static void
8113rs6000_init_libfuncs (void)
8114{
8115 if (!TARGET_HARD_FLOAT)
8116 return;
8117
c9034561 8118 if (DEFAULT_ABI != ABI_V4)
c15c90bb 8119 {
c9034561 8120 if (TARGET_XCOFF && ! TARGET_POWER2 && ! TARGET_POWERPC)
c15c90bb 8121 {
c9034561 8122 /* AIX library routines for float->int conversion. */
85363ca0
ZW		 8123 set_conv_libfunc (sfix_optab, SImode, DFmode, "__itrunc");
8124 set_conv_libfunc (ufix_optab, SImode, DFmode, "__uitrunc");
4274207b
DE		 8125 set_conv_libfunc (sfix_optab, SImode, TFmode, "_qitrunc");
8126 set_conv_libfunc (ufix_optab, SImode, TFmode, "_quitrunc");
c15c90bb
ZW		 8127 }
8128
c9034561 8129 /* Standard AIX/Darwin/64-bit SVR4 quad floating point routines. */
6f85d0c4
DE		 8130 set_optab_libfunc (add_optab, TFmode, "__gcc_qadd");
8131 set_optab_libfunc (sub_optab, TFmode, "__gcc_qsub");
8132 set_optab_libfunc (smul_optab, TFmode, "__gcc_qmul");
8133 set_optab_libfunc (sdiv_optab, TFmode, "__gcc_qdiv");
c15c90bb 8134 }
c9034561 8135 else
c15c90bb 8136 {
c9034561 8137 /* 32-bit SVR4 quad floating point routines. */
c15c90bb
ZW		 8138
8139 set_optab_libfunc (add_optab, TFmode, "_q_add");
8140 set_optab_libfunc (sub_optab, TFmode, "_q_sub");
8141 set_optab_libfunc (neg_optab, TFmode, "_q_neg");
8142 set_optab_libfunc (smul_optab, TFmode, "_q_mul");
8143 set_optab_libfunc (sdiv_optab, TFmode, "_q_div");
8144 if (TARGET_PPC_GPOPT || TARGET_POWER2)
8145 set_optab_libfunc (sqrt_optab, TFmode, "_q_sqrt");
8146
c9034561
ZW		 8147 set_optab_libfunc (eq_optab, TFmode, "_q_feq");
8148 set_optab_libfunc (ne_optab, TFmode, "_q_fne");
8149 set_optab_libfunc (gt_optab, TFmode, "_q_fgt");
8150 set_optab_libfunc (ge_optab, TFmode, "_q_fge");
8151 set_optab_libfunc (lt_optab, TFmode, "_q_flt");
8152 set_optab_libfunc (le_optab, TFmode, "_q_fle");
8153
85363ca0
ZW		 8154 set_conv_libfunc (sext_optab, TFmode, SFmode, "_q_stoq");
8155 set_conv_libfunc (sext_optab, TFmode, DFmode, "_q_dtoq");
8156 set_conv_libfunc (trunc_optab, SFmode, TFmode, "_q_qtos");
8157 set_conv_libfunc (trunc_optab, DFmode, TFmode, "_q_qtod");
8158 set_conv_libfunc (sfix_optab, SImode, TFmode, "_q_qtoi");
8159 set_conv_libfunc (ufix_optab, SImode, TFmode, "_q_qtou");
8160 set_conv_libfunc (sfloat_optab, TFmode, SImode, "_q_itoq");
c15c90bb
ZW		 8161 }
8162}
fba73eb1
DE		 8163
8164\f
8165/* Expand a block clear operation, and return 1 if successful. Return 0
8166 if we should let the compiler generate normal code.
8167
8168 operands[0] is the destination
8169 operands[1] is the length
8170 operands[2] is the alignment */
8171
8172int
8173expand_block_clear (rtx operands[])
8174{
8175 rtx orig_dest = operands[0];
8176 rtx bytes_rtx = operands[1];
8177 rtx align_rtx = operands[2];
5514620a
GK		 8178 bool constp = (GET_CODE (bytes_rtx) == CONST_INT);
8179 HOST_WIDE_INT align;
8180 HOST_WIDE_INT bytes;
fba73eb1
DE		 8181 int offset;
8182 int clear_bytes;
5514620a 8183 int clear_step;
fba73eb1
DE		 8184
8185 /* If this is not a fixed size move, just call memcpy */
8186 if (! constp)
8187 return 0;
8188
8189 /* If this is not a fixed size alignment, abort */
8190 if (GET_CODE (align_rtx) != CONST_INT)
8191 abort ();
8192 align = INTVAL (align_rtx) * BITS_PER_UNIT;
8193
8194 /* Anything to clear? */
8195 bytes = INTVAL (bytes_rtx);
8196 if (bytes <= 0)
8197 return 1;
8198
5514620a
GK		 8199 /* Use the builtin memset after a point, to avoid huge code bloat.
8200 When optimize_size, avoid any significant code bloat; calling
8201 memset is about 4 instructions, so allow for one instruction to
8202 load zero and three to do clearing. */
8203 if (TARGET_ALTIVEC && align >= 128)
8204 clear_step = 16;
8205 else if (TARGET_POWERPC64 && align >= 32)
8206 clear_step = 8;
8207 else
8208 clear_step = 4;
fba73eb1 8209
5514620a
GK		 8210 if (optimize_size && bytes > 3 * clear_step)
8211 return 0;
8212 if (! optimize_size && bytes > 8 * clear_step)
fba73eb1
DE		 8213 return 0;
8214
8215 for (offset = 0; bytes > 0; offset += clear_bytes, bytes -= clear_bytes)
8216 {
fba73eb1
DE		 8217 enum machine_mode mode = BLKmode;
8218 rtx dest;
f676971a 8219
5514620a
GK		 8220 if (bytes >= 16 && TARGET_ALTIVEC && align >= 128)
8221 {
8222 clear_bytes = 16;
8223 mode = V4SImode;
8224 }
8225 else if (bytes >= 8 && TARGET_POWERPC64
8226 /* 64-bit loads and stores require word-aligned
8227 displacements. */
8228 && (align >= 64 || (!STRICT_ALIGNMENT && align >= 32)))
fba73eb1
DE		 8229 {
8230 clear_bytes = 8;
8231 mode = DImode;
fba73eb1 8232 }
5514620a 8233 else if (bytes >= 4 && (align >= 32 || !STRICT_ALIGNMENT))
fba73eb1
DE		 8234 { /* move 4 bytes */
8235 clear_bytes = 4;
8236 mode = SImode;
fba73eb1 8237 }
5514620a 8238 else if (bytes == 2 && (align >= 16 || !STRICT_ALIGNMENT))
fba73eb1
DE		 8239 { /* move 2 bytes */
8240 clear_bytes = 2;
8241 mode = HImode;
fba73eb1
DE		 8242 }
8243 else /* move 1 byte at a time */
8244 {
8245 clear_bytes = 1;
8246 mode = QImode;
fba73eb1 8247 }
f676971a 8248
fba73eb1 8249 dest = adjust_address (orig_dest, mode, offset);
f676971a 8250
5514620a 8251 emit_move_insn (dest, CONST0_RTX (mode));
fba73eb1
DE		 8252 }
8253
8254 return 1;
8255}
8256
35aff10b 8257\f
7e69e155
MM		 8258/* Expand a block move operation, and return 1 if successful. Return 0
8259 if we should let the compiler generate normal code.
8260
8261 operands[0] is the destination
8262 operands[1] is the source
8263 operands[2] is the length
8264 operands[3] is the alignment */
8265
3933e0e1
MM		 8266#define MAX_MOVE_REG 4
8267
7e69e155 8268int
a2369ed3 8269expand_block_move (rtx operands[])
7e69e155 8270{
b6c9286a
MM		 8271 rtx orig_dest = operands[0];
8272 rtx orig_src = operands[1];
7e69e155 8273 rtx bytes_rtx = operands[2];
7e69e155 8274 rtx align_rtx = operands[3];
3933e0e1 8275 int constp = (GET_CODE (bytes_rtx) == CONST_INT);
5ee95df6 8276 int align;
3933e0e1
MM		 8277 int bytes;
8278 int offset;
7e69e155 8279 int move_bytes;
cabfd258
GK		 8280 rtx stores[MAX_MOVE_REG];
8281 int num_reg = 0;
7e69e155 8282
3933e0e1 8283 /* If this is not a fixed size move, just call memcpy */
cc0d9ba8 8284 if (! constp)
3933e0e1
MM		 8285 return 0;
8286
5ee95df6
FS		 8287 /* If this is not a fixed size alignment, abort */
8288 if (GET_CODE (align_rtx) != CONST_INT)
8289 abort ();
fba73eb1 8290 align = INTVAL (align_rtx) * BITS_PER_UNIT;
5ee95df6 8291
7e69e155 8292 /* Anything to move? */
3933e0e1
MM		 8293 bytes = INTVAL (bytes_rtx);
8294 if (bytes <= 0)
7e69e155
MM		 8295 return 1;
8296
ea9982a8 8297 /* store_one_arg depends on expand_block_move to handle at least the size of
f676971a 8298 reg_parm_stack_space. */
ea9982a8 8299 if (bytes > (TARGET_POWERPC64 ? 64 : 32))
7e69e155
MM		 8300 return 0;
8301
cabfd258 8302 for (offset = 0; bytes > 0; offset += move_bytes, bytes -= move_bytes)
7e69e155 8303 {
cabfd258 8304 union {
70128ad9 8305 rtx (*movmemsi) (rtx, rtx, rtx, rtx);
a2369ed3 8306 rtx (*mov) (rtx, rtx);
cabfd258
GK		 8307 } gen_func;
8308 enum machine_mode mode = BLKmode;
8309 rtx src, dest;
f676971a 8310
5514620a
GK		 8311 /* Altivec first, since it will be faster than a string move
8312 when it applies, and usually not significantly larger. */
8313 if (TARGET_ALTIVEC && bytes >= 16 && align >= 128)
8314 {
8315 move_bytes = 16;
8316 mode = V4SImode;
8317 gen_func.mov = gen_movv4si;
8318 }
8319 else if (TARGET_STRING
cabfd258
GK		 8320 && bytes > 24 /* move up to 32 bytes at a time */
8321 && ! fixed_regs[5]
8322 && ! fixed_regs[6]
8323 && ! fixed_regs[7]
8324 && ! fixed_regs[8]
8325 && ! fixed_regs[9]
8326 && ! fixed_regs[10]
8327 && ! fixed_regs[11]
8328 && ! fixed_regs[12])
7e69e155 8329 {
cabfd258 8330 move_bytes = (bytes > 32) ? 32 : bytes;
70128ad9 8331 gen_func.movmemsi = gen_movmemsi_8reg;
cabfd258
GK		 8332 }
8333 else if (TARGET_STRING
8334 && bytes > 16 /* move up to 24 bytes at a time */
8335 && ! fixed_regs[5]
8336 && ! fixed_regs[6]
8337 && ! fixed_regs[7]
8338 && ! fixed_regs[8]
8339 && ! fixed_regs[9]
8340 && ! fixed_regs[10])
8341 {
8342 move_bytes = (bytes > 24) ? 24 : bytes;
70128ad9 8343 gen_func.movmemsi = gen_movmemsi_6reg;
cabfd258
GK		 8344 }
8345 else if (TARGET_STRING
8346 && bytes > 8 /* move up to 16 bytes at a time */
8347 && ! fixed_regs[5]
8348 && ! fixed_regs[6]
8349 && ! fixed_regs[7]
8350 && ! fixed_regs[8])
8351 {
8352 move_bytes = (bytes > 16) ? 16 : bytes;
70128ad9 8353 gen_func.movmemsi = gen_movmemsi_4reg;
cabfd258
GK		 8354 }
8355 else if (bytes >= 8 && TARGET_POWERPC64
8356 /* 64-bit loads and stores require word-aligned
8357 displacements. */
fba73eb1 8358 && (align >= 64 || (!STRICT_ALIGNMENT && align >= 32)))
cabfd258
GK		 8359 {
8360 move_bytes = 8;
8361 mode = DImode;
8362 gen_func.mov = gen_movdi;
8363 }
8364 else if (TARGET_STRING && bytes > 4 && !TARGET_POWERPC64)
8365 { /* move up to 8 bytes at a time */
8366 move_bytes = (bytes > 8) ? 8 : bytes;
70128ad9 8367 gen_func.movmemsi = gen_movmemsi_2reg;
cabfd258 8368 }
cd7d9ca4 8369 else if (bytes >= 4 && (align >= 32 || !STRICT_ALIGNMENT))
cabfd258
GK		 8370 { /* move 4 bytes */
8371 move_bytes = 4;
8372 mode = SImode;
8373 gen_func.mov = gen_movsi;
8374 }
cd7d9ca4 8375 else if (bytes == 2 && (align >= 16 || !STRICT_ALIGNMENT))
cabfd258
GK		 8376 { /* move 2 bytes */
8377 move_bytes = 2;
8378 mode = HImode;
8379 gen_func.mov = gen_movhi;
8380 }
8381 else if (TARGET_STRING && bytes > 1)
8382 { /* move up to 4 bytes at a time */
8383 move_bytes = (bytes > 4) ? 4 : bytes;
70128ad9 8384 gen_func.movmemsi = gen_movmemsi_1reg;
cabfd258
GK		 8385 }
8386 else /* move 1 byte at a time */
8387 {
8388 move_bytes = 1;
8389 mode = QImode;
8390 gen_func.mov = gen_movqi;
8391 }
f676971a 8392
cabfd258
GK		 8393 src = adjust_address (orig_src, mode, offset);
8394 dest = adjust_address (orig_dest, mode, offset);
f676971a
EC		 8395
8396 if (mode != BLKmode)
cabfd258
GK		 8397 {
8398 rtx tmp_reg = gen_reg_rtx (mode);
f676971a 8399
cabfd258
GK		 8400 emit_insn ((*gen_func.mov) (tmp_reg, src));
8401 stores[num_reg++] = (*gen_func.mov) (dest, tmp_reg);
4c64a852 8402 }
3933e0e1 8403
cabfd258
GK		 8404 if (mode == BLKmode || num_reg >= MAX_MOVE_REG || bytes == move_bytes)
8405 {
8406 int i;
8407 for (i = 0; i < num_reg; i++)
8408 emit_insn (stores[i]);
8409 num_reg = 0;
8410 }
35aff10b 8411
cabfd258 8412 if (mode == BLKmode)
7e69e155 8413 {
70128ad9 8414 /* Move the address into scratch registers. The movmemsi
cabfd258
GK		 8415 patterns require zero offset. */
8416 if (!REG_P (XEXP (src, 0)))
b6c9286a 8417 {
cabfd258
GK		 8418 rtx src_reg = copy_addr_to_reg (XEXP (src, 0));
8419 src = replace_equiv_address (src, src_reg);
b6c9286a 8420 }
cabfd258 8421 set_mem_size (src, GEN_INT (move_bytes));
f676971a 8422
cabfd258 8423 if (!REG_P (XEXP (dest, 0)))
3933e0e1 8424 {
cabfd258
GK		 8425 rtx dest_reg = copy_addr_to_reg (XEXP (dest, 0));
8426 dest = replace_equiv_address (dest, dest_reg);
7e69e155 8427 }
cabfd258 8428 set_mem_size (dest, GEN_INT (move_bytes));
f676971a 8429
70128ad9 8430 emit_insn ((*gen_func.movmemsi) (dest, src,
cabfd258
GK		 8431 GEN_INT (move_bytes & 31),
8432 align_rtx));
7e69e155 8433 }
7e69e155
MM		 8434 }
8435
8436 return 1;
8437}
8438
d62294f5 8439\f
9caa3eb2
DE		 8440/* Return a string to perform a load_multiple operation.
8441 operands[0] is the vector.
8442 operands[1] is the source address.
8443 operands[2] is the first destination register. */
8444
8445const char *
a2369ed3 8446rs6000_output_load_multiple (rtx operands[3])
9caa3eb2
DE		 8447{
8448 /* We have to handle the case where the pseudo used to contain the address
8449 is assigned to one of the output registers. */
8450 int i, j;
8451 int words = XVECLEN (operands[0], 0);
8452 rtx xop[10];
8453
8454 if (XVECLEN (operands[0], 0) == 1)
8455 return "{l|lwz} %2,0(%1)";
8456
8457 for (i = 0; i < words; i++)
8458 if (refers_to_regno_p (REGNO (operands[2]) + i,
8459 REGNO (operands[2]) + i + 1, operands[1], 0))
8460 {
8461 if (i == words-1)
8462 {
8463 xop[0] = GEN_INT (4 * (words-1));
8464 xop[1] = operands[1];
8465 xop[2] = operands[2];
8466 output_asm_insn ("{lsi|lswi} %2,%1,%0\n\t{l|lwz} %1,%0(%1)", xop);
8467 return "";
8468 }
8469 else if (i == 0)
8470 {
8471 xop[0] = GEN_INT (4 * (words-1));
8472 xop[1] = operands[1];
8473 xop[2] = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
8474 output_asm_insn ("{cal %1,4(%1)|addi %1,%1,4}\n\t{lsi|lswi} %2,%1,%0\n\t{l|lwz} %1,-4(%1)", xop);
8475 return "";
8476 }
8477 else
8478 {
8479 for (j = 0; j < words; j++)
8480 if (j != i)
8481 {
8482 xop[0] = GEN_INT (j * 4);
8483 xop[1] = operands[1];
8484 xop[2] = gen_rtx_REG (SImode, REGNO (operands[2]) + j);
8485 output_asm_insn ("{l|lwz} %2,%0(%1)", xop);
8486 }
8487 xop[0] = GEN_INT (i * 4);
8488 xop[1] = operands[1];
8489 output_asm_insn ("{l|lwz} %1,%0(%1)", xop);
8490 return "";
8491 }
8492 }
8493
8494 return "{lsi|lswi} %2,%1,%N0";
8495}
8496
9878760c 8497\f
a4f6c312
SS		 8498/* A validation routine: say whether CODE, a condition code, and MODE
8499 match. The other alternatives either don't make sense or should
8500 never be generated. */
39a10a29 8501
48d72335 8502void
a2369ed3 8503validate_condition_mode (enum rtx_code code, enum machine_mode mode)
39a10a29 8504{
ec8e098d
PB		 8505 if ((GET_RTX_CLASS (code) != RTX_COMPARE
8506 && GET_RTX_CLASS (code) != RTX_COMM_COMPARE)
39a10a29
GK		 8507 || GET_MODE_CLASS (mode) != MODE_CC)
8508 abort ();
8509
8510 /* These don't make sense. */
8511 if ((code == GT || code == LT || code == GE || code == LE)
8512 && mode == CCUNSmode)
8513 abort ();
8514
8515 if ((code == GTU || code == LTU || code == GEU || code == LEU)
8516 && mode != CCUNSmode)
8517 abort ();
8518
8519 if (mode != CCFPmode
8520 && (code == ORDERED || code == UNORDERED
8521 || code == UNEQ || code == LTGT
8522 || code == UNGT || code == UNLT
8523 || code == UNGE || code == UNLE))
a4f6c312 8524 abort ();
f676971a
EC		 8525
8526 /* These should never be generated except for
bc9ec0e0 8527 flag_finite_math_only. */
39a10a29 8528 if (mode == CCFPmode
ad72b533 8529 && ! flag_finite_math_only
39a10a29
GK		 8530 && (code == LE || code == GE
8531 || code == UNEQ || code == LTGT
8532 || code == UNGT || code == UNLT))
8533 abort ();
8534
8535 /* These are invalid; the information is not there. */
f676971a 8536 if (mode == CCEQmode
39a10a29
GK		 8537 && code != EQ && code != NE)
8538 abort ();
8539}
8540
9878760c
RK		 8541\f
8542/* Return 1 if ANDOP is a mask that has no bits on that are not in the
8543 mask required to convert the result of a rotate insn into a shift
b1765bde 8544 left insn of SHIFTOP bits. Both are known to be SImode CONST_INT. */
9878760c
RK		 8545
8546int
a2369ed3 8547includes_lshift_p (rtx shiftop, rtx andop)
9878760c 8548{
e2c953b6
DE		 8549 unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0;
8550
8551 shift_mask <<= INTVAL (shiftop);
9878760c 8552
b1765bde 8553 return (INTVAL (andop) & 0xffffffff & ~shift_mask) == 0;
9878760c
RK		 8554}
8555
8556/* Similar, but for right shift. */
8557
8558int
a2369ed3 8559includes_rshift_p (rtx shiftop, rtx andop)
9878760c 8560{
a7653a2c 8561 unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0;
9878760c
RK		 8562
8563 shift_mask >>= INTVAL (shiftop);
8564
b1765bde 8565 return (INTVAL (andop) & 0xffffffff & ~shift_mask) == 0;
e2c953b6
DE		 8566}
8567
c5059423
AM		 8568/* Return 1 if ANDOP is a mask suitable for use with an rldic insn
8569 to perform a left shift. It must have exactly SHIFTOP least
b6d08ca1 8570 significant 0's, then one or more 1's, then zero or more 0's. */
e2c953b6
DE		 8571
8572int
a2369ed3 8573includes_rldic_lshift_p (rtx shiftop, rtx andop)
e2c953b6 8574{
c5059423
AM		 8575 if (GET_CODE (andop) == CONST_INT)
8576 {
02071907 8577 HOST_WIDE_INT c, lsb, shift_mask;
e2c953b6 8578
c5059423 8579 c = INTVAL (andop);
02071907 8580 if (c == 0 || c == ~0)
c5059423 8581 return 0;
e2c953b6 8582
02071907 8583 shift_mask = ~0;
c5059423
AM		 8584 shift_mask <<= INTVAL (shiftop);
8585
b6d08ca1 8586 /* Find the least significant one bit. */
c5059423
AM		 8587 lsb = c & -c;
8588
8589 /* It must coincide with the LSB of the shift mask. */
8590 if (-lsb != shift_mask)
8591 return 0;
e2c953b6 8592
c5059423
AM		 8593 /* Invert to look for the next transition (if any). */
8594 c = ~c;
8595
8596 /* Remove the low group of ones (originally low group of zeros). */
8597 c &= -lsb;
8598
8599 /* Again find the lsb, and check we have all 1's above. */
8600 lsb = c & -c;
8601 return c == -lsb;
8602 }
8603 else if (GET_CODE (andop) == CONST_DOUBLE
8604 && (GET_MODE (andop) == VOIDmode || GET_MODE (andop) == DImode))
8605 {
02071907
AM		 8606 HOST_WIDE_INT low, high, lsb;
8607 HOST_WIDE_INT shift_mask_low, shift_mask_high;
c5059423
AM		 8608
8609 low = CONST_DOUBLE_LOW (andop);
8610 if (HOST_BITS_PER_WIDE_INT < 64)
8611 high = CONST_DOUBLE_HIGH (andop);
8612
8613 if ((low == 0 && (HOST_BITS_PER_WIDE_INT >= 64 || high == 0))
02071907 8614 || (low == ~0 && (HOST_BITS_PER_WIDE_INT >= 64 || high == ~0)))
c5059423
AM		 8615 return 0;
8616
8617 if (HOST_BITS_PER_WIDE_INT < 64 && low == 0)
8618 {
02071907 8619 shift_mask_high = ~0;
c5059423
AM		 8620 if (INTVAL (shiftop) > 32)
8621 shift_mask_high <<= INTVAL (shiftop) - 32;
8622
8623 lsb = high & -high;
8624
8625 if (-lsb != shift_mask_high || INTVAL (shiftop) < 32)
8626 return 0;
8627
8628 high = ~high;
8629 high &= -lsb;
8630
8631 lsb = high & -high;
8632 return high == -lsb;
8633 }
8634
02071907 8635 shift_mask_low = ~0;
c5059423
AM		 8636 shift_mask_low <<= INTVAL (shiftop);
8637
8638 lsb = low & -low;
8639
8640 if (-lsb != shift_mask_low)
8641 return 0;
8642
8643 if (HOST_BITS_PER_WIDE_INT < 64)
8644 high = ~high;
8645 low = ~low;
8646 low &= -lsb;
8647
8648 if (HOST_BITS_PER_WIDE_INT < 64 && low == 0)
8649 {
8650 lsb = high & -high;
8651 return high == -lsb;
8652 }
8653
8654 lsb = low & -low;
8655 return low == -lsb && (HOST_BITS_PER_WIDE_INT >= 64 || high == ~0);
8656 }
8657 else
8658 return 0;
8659}
e2c953b6 8660
c5059423
AM		 8661/* Return 1 if ANDOP is a mask suitable for use with an rldicr insn
8662 to perform a left shift. It must have SHIFTOP or more least
c1207243 8663 significant 0's, with the remainder of the word 1's. */
e2c953b6 8664
c5059423 8665int
a2369ed3 8666includes_rldicr_lshift_p (rtx shiftop, rtx andop)
c5059423 8667{
e2c953b6 8668 if (GET_CODE (andop) == CONST_INT)
c5059423 8669 {
02071907 8670 HOST_WIDE_INT c, lsb, shift_mask;
c5059423 8671
02071907 8672 shift_mask = ~0;
c5059423
AM		 8673 shift_mask <<= INTVAL (shiftop);
8674 c = INTVAL (andop);
8675
c1207243 8676 /* Find the least significant one bit. */
c5059423
AM		 8677 lsb = c & -c;
8678
8679 /* It must be covered by the shift mask.
a4f6c312 8680 This test also rejects c == 0. */
c5059423
AM		 8681 if ((lsb & shift_mask) == 0)
8682 return 0;
8683
8684 /* Check we have all 1's above the transition, and reject all 1's. */
8685 return c == -lsb && lsb != 1;
8686 }
8687 else if (GET_CODE (andop) == CONST_DOUBLE
8688 && (GET_MODE (andop) == VOIDmode || GET_MODE (andop) == DImode))
8689 {
02071907 8690 HOST_WIDE_INT low, lsb, shift_mask_low;
c5059423
AM		 8691
8692 low = CONST_DOUBLE_LOW (andop);
8693
8694 if (HOST_BITS_PER_WIDE_INT < 64)
8695 {
02071907 8696 HOST_WIDE_INT high, shift_mask_high;
c5059423
AM		 8697
8698 high = CONST_DOUBLE_HIGH (andop);
8699
8700 if (low == 0)
8701 {
02071907 8702 shift_mask_high = ~0;
c5059423
AM		 8703 if (INTVAL (shiftop) > 32)
8704 shift_mask_high <<= INTVAL (shiftop) - 32;
8705
8706 lsb = high & -high;
8707
8708 if ((lsb & shift_mask_high) == 0)
8709 return 0;
8710
8711 return high == -lsb;
8712 }
8713 if (high != ~0)
8714 return 0;
8715 }
8716
02071907 8717 shift_mask_low = ~0;
c5059423
AM		 8718 shift_mask_low <<= INTVAL (shiftop);
8719
8720 lsb = low & -low;
8721
8722 if ((lsb & shift_mask_low) == 0)
8723 return 0;
8724
8725 return low == -lsb && lsb != 1;
8726 }
e2c953b6 8727 else
c5059423 8728 return 0;
9878760c 8729}
35068b43 8730
11ac38b2
DE		 8731/* Return 1 if operands will generate a valid arguments to rlwimi
8732instruction for insert with right shift in 64-bit mode. The mask may
8733not start on the first bit or stop on the last bit because wrap-around
8734effects of instruction do not correspond to semantics of RTL insn. */
8735
8736int
8737insvdi_rshift_rlwimi_p (rtx sizeop, rtx startop, rtx shiftop)
8738{
8739 if (INTVAL (startop) < 64
8740 && INTVAL (startop) > 32
8741 && (INTVAL (sizeop) + INTVAL (startop) < 64)
8742 && (INTVAL (sizeop) + INTVAL (startop) > 33)
8743 && (INTVAL (sizeop) + INTVAL (startop) + INTVAL (shiftop) < 96)
8744 && (INTVAL (sizeop) + INTVAL (startop) + INTVAL (shiftop) >= 64)
8745 && (64 - (INTVAL (shiftop) & 63)) >= INTVAL (sizeop))
8746 return 1;
8747
8748 return 0;
8749}
8750
35068b43 8751/* Return 1 if REGNO (reg1) == REGNO (reg2) - 1 making them candidates
90f81f99 8752 for lfq and stfq insns iff the registers are hard registers. */
35068b43
RK		 8753
8754int
a2369ed3 8755registers_ok_for_quad_peep (rtx reg1, rtx reg2)
35068b43
RK		 8756{
8757 /* We might have been passed a SUBREG. */
f676971a 8758 if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG)
35068b43 8759 return 0;
f676971a 8760
90f81f99
AP		 8761 /* We might have been passed non floating point registers. */
8762 if (!FP_REGNO_P (REGNO (reg1))
8763 || !FP_REGNO_P (REGNO (reg2)))
8764 return 0;
35068b43
RK		 8765
8766 return (REGNO (reg1) == REGNO (reg2) - 1);
8767}
8768
a4f6c312
SS		 8769/* Return 1 if addr1 and addr2 are suitable for lfq or stfq insn.
8770 addr1 and addr2 must be in consecutive memory locations
8771 (addr2 == addr1 + 8). */
35068b43
RK		 8772
8773int
90f81f99 8774mems_ok_for_quad_peep (rtx mem1, rtx mem2)
35068b43 8775{
90f81f99 8776 rtx addr1, addr2;
e2c953b6 8777 unsigned int reg1;
35068b43
RK		 8778 int offset1;
8779
90f81f99
AP		 8780 /* The mems cannot be volatile. */
8781 if (MEM_VOLATILE_P (mem1) || MEM_VOLATILE_P (mem2))
8782 return 0;
f676971a 8783
90f81f99
AP		 8784 addr1 = XEXP (mem1, 0);
8785 addr2 = XEXP (mem2, 0);
8786
35068b43
RK		 8787 /* Extract an offset (if used) from the first addr. */
8788 if (GET_CODE (addr1) == PLUS)
8789 {
8790 /* If not a REG, return zero. */
8791 if (GET_CODE (XEXP (addr1, 0)) != REG)
8792 return 0;
8793 else
8794 {
c4ad648e 8795 reg1 = REGNO (XEXP (addr1, 0));
35068b43
RK		 8796 /* The offset must be constant! */
8797 if (GET_CODE (XEXP (addr1, 1)) != CONST_INT)
c4ad648e
AM		 8798 return 0;
8799 offset1 = INTVAL (XEXP (addr1, 1));
35068b43
RK		 8800 }
8801 }
8802 else if (GET_CODE (addr1) != REG)
8803 return 0;
8804 else
8805 {
8806 reg1 = REGNO (addr1);
8807 /* This was a simple (mem (reg)) expression. Offset is 0. */
8808 offset1 = 0;
8809 }
8810
a2369ed3 8811 /* Make sure the second address is a (mem (plus (reg) (const_int)))
f676971a 8812 or if it is (mem (reg)) then make sure that offset1 is -8 and the same
0f6937fe 8813 register as addr1. */
984e25ac 8814 if (offset1 == -8 && GET_CODE (addr2) == REG && reg1 == REGNO (addr2))
0f6937fe 8815 return 1;
35068b43
RK		 8816 if (GET_CODE (addr2) != PLUS)
8817 return 0;
8818
8819 if (GET_CODE (XEXP (addr2, 0)) != REG
8820 || GET_CODE (XEXP (addr2, 1)) != CONST_INT)
8821 return 0;
8822
8823 if (reg1 != REGNO (XEXP (addr2, 0)))
8824 return 0;
8825
8826 /* The offset for the second addr must be 8 more than the first addr. */
8827 if (INTVAL (XEXP (addr2, 1)) != offset1 + 8)
8828 return 0;
8829
8830 /* All the tests passed. addr1 and addr2 are valid for lfq or stfq
8831 instructions. */
8832 return 1;
8833}
9878760c
RK		 8834\f
8835/* Return the register class of a scratch register needed to copy IN into
8836 or out of a register in CLASS in MODE. If it can be done directly,
8837 NO_REGS is returned. */
8838
8839enum reg_class
f676971a 8840secondary_reload_class (enum reg_class class,
a9baceb1
GK		 8841 enum machine_mode mode ATTRIBUTE_UNUSED,
8842 rtx in)
9878760c 8843{
5accd822 8844 int regno;
9878760c 8845
ab82a49f
AP		 8846 if (TARGET_ELF || (DEFAULT_ABI == ABI_DARWIN
8847#if TARGET_MACHO
c4ad648e 8848 && MACHOPIC_INDIRECT
ab82a49f 8849#endif
c4ad648e 8850 ))
46fad5b7
DJ		 8851 {
8852 /* We cannot copy a symbolic operand directly into anything
c4ad648e
AM		 8853 other than BASE_REGS for TARGET_ELF. So indicate that a
8854 register from BASE_REGS is needed as an intermediate
8855 register.
f676971a 8856
46fad5b7
DJ		 8857 On Darwin, pic addresses require a load from memory, which
8858 needs a base register. */
8859 if (class != BASE_REGS
c4ad648e
AM		 8860 && (GET_CODE (in) == SYMBOL_REF
8861 || GET_CODE (in) == HIGH
8862 || GET_CODE (in) == LABEL_REF
8863 || GET_CODE (in) == CONST))
8864 return BASE_REGS;
46fad5b7 8865 }
e7b7998a 8866
5accd822
DE		 8867 if (GET_CODE (in) == REG)
8868 {
8869 regno = REGNO (in);
8870 if (regno >= FIRST_PSEUDO_REGISTER)
8871 {
8872 regno = true_regnum (in);
8873 if (regno >= FIRST_PSEUDO_REGISTER)
8874 regno = -1;
8875 }
8876 }
8877 else if (GET_CODE (in) == SUBREG)
8878 {
8879 regno = true_regnum (in);
8880 if (regno >= FIRST_PSEUDO_REGISTER)
8881 regno = -1;
8882 }
8883 else
8884 regno = -1;
8885
9878760c
RK		 8886 /* We can place anything into GENERAL_REGS and can put GENERAL_REGS
8887 into anything. */
8888 if (class == GENERAL_REGS || class == BASE_REGS
8889 || (regno >= 0 && INT_REGNO_P (regno)))
8890 return NO_REGS;
8891
8892 /* Constants, memory, and FP registers can go into FP registers. */
8893 if ((regno == -1 || FP_REGNO_P (regno))
8894 && (class == FLOAT_REGS || class == NON_SPECIAL_REGS))
8895 return NO_REGS;
8896
0ac081f6
AH		 8897 /* Memory, and AltiVec registers can go into AltiVec registers. */
8898 if ((regno == -1 || ALTIVEC_REGNO_P (regno))
8899 && class == ALTIVEC_REGS)
8900 return NO_REGS;
8901
9878760c
RK		 8902 /* We can copy among the CR registers. */
8903 if ((class == CR_REGS || class == CR0_REGS)
8904 && regno >= 0 && CR_REGNO_P (regno))
8905 return NO_REGS;
8906
8907 /* Otherwise, we need GENERAL_REGS. */
8908 return GENERAL_REGS;
8909}
8910\f
8911/* Given a comparison operation, return the bit number in CCR to test. We
f676971a 8912 know this is a valid comparison.
9878760c
RK		 8913
8914 SCC_P is 1 if this is for an scc. That means that %D will have been
8915 used instead of %C, so the bits will be in different places.
8916
b4ac57ab 8917 Return -1 if OP isn't a valid comparison for some reason. */
9878760c
RK		 8918
8919int
a2369ed3 8920ccr_bit (rtx op, int scc_p)
9878760c
RK		 8921{
8922 enum rtx_code code = GET_CODE (op);
8923 enum machine_mode cc_mode;
8924 int cc_regnum;
8925 int base_bit;
9ebbca7d 8926 rtx reg;
9878760c 8927
ec8e098d 8928 if (!COMPARISON_P (op))
9878760c
RK		 8929 return -1;
8930
9ebbca7d
GK		 8931 reg = XEXP (op, 0);
8932
8933 if (GET_CODE (reg) != REG
8934 || ! CR_REGNO_P (REGNO (reg)))
8935 abort ();
8936
8937 cc_mode = GET_MODE (reg);
8938 cc_regnum = REGNO (reg);
8939 base_bit = 4 * (cc_regnum - CR0_REGNO);
9878760c 8940
39a10a29 8941 validate_condition_mode (code, cc_mode);
c5defebb 8942
b7053a3f
GK		 8943 /* When generating a sCOND operation, only positive conditions are
8944 allowed. */
8945 if (scc_p && code != EQ && code != GT && code != LT && code != UNORDERED
8946 && code != GTU && code != LTU)
8947 abort ();
f676971a 8948
9878760c
RK		 8949 switch (code)
8950 {
8951 case NE:
8952 return scc_p ? base_bit + 3 : base_bit + 2;
8953 case EQ:
8954 return base_bit + 2;
1c882ea4 8955 case GT: case GTU: case UNLE:
9878760c 8956 return base_bit + 1;
1c882ea4 8957 case LT: case LTU: case UNGE:
9878760c 8958 return base_bit;
1c882ea4
GK		 8959 case ORDERED: case UNORDERED:
8960 return base_bit + 3;
9878760c
RK		 8961
8962 case GE: case GEU:
39a10a29 8963 /* If scc, we will have done a cror to put the bit in the
9878760c
RK		 8964 unordered position. So test that bit. For integer, this is ! LT
8965 unless this is an scc insn. */
39a10a29 8966 return scc_p ? base_bit + 3 : base_bit;
9878760c
RK		 8967
8968 case LE: case LEU:
39a10a29 8969 return scc_p ? base_bit + 3 : base_bit + 1;
1c882ea4 8970
9878760c
RK		 8971 default:
8972 abort ();
8973 }
8974}
1ff7789b 8975\f
8d30c4ee 8976/* Return the GOT register. */
1ff7789b 8977
9390387d 8978rtx
a2369ed3 8979rs6000_got_register (rtx value ATTRIBUTE_UNUSED)
1ff7789b 8980{
a4f6c312
SS		 8981 /* The second flow pass currently (June 1999) can't update
8982 regs_ever_live without disturbing other parts of the compiler, so
8983 update it here to make the prolog/epilogue code happy. */
1db02437
FS		 8984 if (no_new_pseudos && ! regs_ever_live[RS6000_PIC_OFFSET_TABLE_REGNUM])
8985 regs_ever_live[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
1ff7789b 8986
8d30c4ee 8987 current_function_uses_pic_offset_table = 1;
3cb999d8 8988
1ff7789b
MM		 8989 return pic_offset_table_rtx;
8990}
a7df97e6 8991\f
e2500fed
GK		 8992/* Function to init struct machine_function.
8993 This will be called, via a pointer variable,
8994 from push_function_context. */
a7df97e6 8995
e2500fed 8996static struct machine_function *
863d938c 8997rs6000_init_machine_status (void)
a7df97e6 8998{
e2500fed 8999 return ggc_alloc_cleared (sizeof (machine_function));
a7df97e6 9000}
9878760c 9001\f
0ba1b2ff
AM		 9002/* These macros test for integers and extract the low-order bits. */
9003#define INT_P(X) \
9004((GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST_DOUBLE) \
9005 && GET_MODE (X) == VOIDmode)
9006
9007#define INT_LOWPART(X) \
9008 (GET_CODE (X) == CONST_INT ? INTVAL (X) : CONST_DOUBLE_LOW (X))
9009
9010int
a2369ed3 9011extract_MB (rtx op)
0ba1b2ff
AM		 9012{
9013 int i;
9014 unsigned long val = INT_LOWPART (op);
9015
9016 /* If the high bit is zero, the value is the first 1 bit we find
9017 from the left. */
9018 if ((val & 0x80000000) == 0)
9019 {
9020 if ((val & 0xffffffff) == 0)
9021 abort ();
9022
9023 i = 1;
9024 while (((val <<= 1) & 0x80000000) == 0)
9025 ++i;
9026 return i;
9027 }
9028
9029 /* If the high bit is set and the low bit is not, or the mask is all
9030 1's, the value is zero. */
9031 if ((val & 1) == 0 || (val & 0xffffffff) == 0xffffffff)
9032 return 0;
9033
9034 /* Otherwise we have a wrap-around mask. Look for the first 0 bit
9035 from the right. */
9036 i = 31;
9037 while (((val >>= 1) & 1) != 0)
9038 --i;
9039
9040 return i;
9041}
9042
9043int
a2369ed3 9044extract_ME (rtx op)
0ba1b2ff
AM		 9045{
9046 int i;
9047 unsigned long val = INT_LOWPART (op);
9048
9049 /* If the low bit is zero, the value is the first 1 bit we find from
9050 the right. */
9051 if ((val & 1) == 0)
9052 {
9053 if ((val & 0xffffffff) == 0)
9054 abort ();
9055
9056 i = 30;
9057 while (((val >>= 1) & 1) == 0)
9058 --i;
9059
9060 return i;
9061 }
9062
9063 /* If the low bit is set and the high bit is not, or the mask is all
9064 1's, the value is 31. */
9065 if ((val & 0x80000000) == 0 || (val & 0xffffffff) == 0xffffffff)
9066 return 31;
9067
9068 /* Otherwise we have a wrap-around mask. Look for the first 0 bit
9069 from the left. */
9070 i = 0;
9071 while (((val <<= 1) & 0x80000000) != 0)
9072 ++i;
9073
9074 return i;
9075}
9076
c4501e62
JJ		 9077/* Locate some local-dynamic symbol still in use by this function
9078 so that we can print its name in some tls_ld pattern. */
9079
9080static const char *
863d938c 9081rs6000_get_some_local_dynamic_name (void)
c4501e62
JJ		 9082{
9083 rtx insn;
9084
9085 if (cfun->machine->some_ld_name)
9086 return cfun->machine->some_ld_name;
9087
9088 for (insn = get_insns (); insn ; insn = NEXT_INSN (insn))
9089 if (INSN_P (insn)
9090 && for_each_rtx (&PATTERN (insn),
9091 rs6000_get_some_local_dynamic_name_1, 0))
9092 return cfun->machine->some_ld_name;
9093
9094 abort ();
9095}
9096
9097/* Helper function for rs6000_get_some_local_dynamic_name. */
9098
9099static int
a2369ed3 9100rs6000_get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
c4501e62
JJ		 9101{
9102 rtx x = *px;
9103
9104 if (GET_CODE (x) == SYMBOL_REF)
9105 {
9106 const char *str = XSTR (x, 0);
9107 if (SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC)
9108 {
9109 cfun->machine->some_ld_name = str;
9110 return 1;
9111 }
9112 }
9113
9114 return 0;
9115}
9116
85b776df
AM		 9117/* Write out a function code label. */
9118
9119void
9120rs6000_output_function_entry (FILE *file, const char *fname)
9121{
9122 if (fname[0] != '.')
9123 {
9124 switch (DEFAULT_ABI)
9125 {
9126 default:
9127 abort ();
9128
9129 case ABI_AIX:
9130 if (DOT_SYMBOLS)
9131 putc ('.', file);
9132 else
9133 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "L.");
9134 break;
9135
9136 case ABI_V4:
9137 case ABI_DARWIN:
9138 break;
9139 }
9140 }
9141 if (TARGET_AIX)
9142 RS6000_OUTPUT_BASENAME (file, fname);
9143 else
9144 assemble_name (file, fname);
9145}
9146
9878760c
RK		 9147/* Print an operand. Recognize special options, documented below. */
9148
38c1f2d7 9149#if TARGET_ELF
d9407988 9150#define SMALL_DATA_RELOC ((rs6000_sdata == SDATA_EABI) ? "sda21" : "sdarel")
8fbd2dc7 9151#define SMALL_DATA_REG ((rs6000_sdata == SDATA_EABI) ? 0 : 13)
ba5e43aa
MM		 9152#else
9153#define SMALL_DATA_RELOC "sda21"
8fbd2dc7 9154#define SMALL_DATA_REG 0
ba5e43aa
MM		 9155#endif
9156
9878760c 9157void
a2369ed3 9158print_operand (FILE *file, rtx x, int code)
9878760c
RK		 9159{
9160 int i;
a260abc9 9161 HOST_WIDE_INT val;
0ba1b2ff 9162 unsigned HOST_WIDE_INT uval;
9878760c
RK		 9163
9164 switch (code)
9165 {
a8b3aeda 9166 case '.':
a85d226b
RK		 9167 /* Write out an instruction after the call which may be replaced
9168 with glue code by the loader. This depends on the AIX version. */
9169 asm_fprintf (file, RS6000_CALL_GLUE);
a8b3aeda
RK		 9170 return;
9171
81eace42
GK		 9172 /* %a is output_address. */
9173
9854d9ed
RK		 9174 case 'A':
9175 /* If X is a constant integer whose low-order 5 bits are zero,
9176 write 'l'. Otherwise, write 'r'. This is a kludge to fix a bug
76229ac8 9177 in the AIX assembler where "sri" with a zero shift count
20e26713 9178 writes a trash instruction. */
9854d9ed 9179 if (GET_CODE (x) == CONST_INT && (INTVAL (x) & 31) == 0)
76229ac8 9180 putc ('l', file);
9854d9ed 9181 else
76229ac8 9182 putc ('r', file);
9854d9ed
RK		 9183 return;
9184
9185 case 'b':
e2c953b6
DE		 9186 /* If constant, low-order 16 bits of constant, unsigned.
9187 Otherwise, write normally. */
9188 if (INT_P (x))
9189 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 0xffff);
9190 else
9191 print_operand (file, x, 0);
cad12a8d
RK		 9192 return;
9193
a260abc9
DE		 9194 case 'B':
9195 /* If the low-order bit is zero, write 'r'; otherwise, write 'l'
9196 for 64-bit mask direction. */
9390387d 9197 putc (((INT_LOWPART (x) & 1) == 0 ? 'r' : 'l'), file);
a238cd8b 9198 return;
a260abc9 9199
81eace42
GK		 9200 /* %c is output_addr_const if a CONSTANT_ADDRESS_P, otherwise
9201 output_operand. */
9202
423c1189
AH		 9203 case 'c':
9204 /* X is a CR register. Print the number of the GT bit of the CR. */
9205 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
9206 output_operand_lossage ("invalid %%E value");
9207 else
9208 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO) + 1);
9209 return;
9210
9211 case 'D':
6b1fedc3 9212 /* Like 'J' but get to the EQ bit. */
423c1189
AH		 9213 if (GET_CODE (x) != REG)
9214 abort ();
9215
6b1fedc3
AH		 9216 /* Bit 1 is EQ bit. */
9217 i = 4 * (REGNO (x) - CR0_REGNO) + 2;
423c1189 9218
64022b5d 9219 fprintf (file, "%d", i);
423c1189
AH		 9220 return;
9221
9854d9ed 9222 case 'E':
39a10a29 9223 /* X is a CR register. Print the number of the EQ bit of the CR */
9854d9ed
RK		 9224 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
9225 output_operand_lossage ("invalid %%E value");
78fbdbf7 9226 else
39a10a29 9227 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO) + 2);
a85d226b 9228 return;
9854d9ed
RK		 9229
9230 case 'f':
9231 /* X is a CR register. Print the shift count needed to move it
9232 to the high-order four bits. */
9233 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
9234 output_operand_lossage ("invalid %%f value");
9235 else
9ebbca7d 9236 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO));
9854d9ed
RK		 9237 return;
9238
9239 case 'F':
9240 /* Similar, but print the count for the rotate in the opposite
9241 direction. */
9242 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
9243 output_operand_lossage ("invalid %%F value");
9244 else
9ebbca7d 9245 fprintf (file, "%d", 32 - 4 * (REGNO (x) - CR0_REGNO));
9854d9ed
RK		 9246 return;
9247
9248 case 'G':
9249 /* X is a constant integer. If it is negative, print "m",
43aa4e05 9250 otherwise print "z". This is to make an aze or ame insn. */
9854d9ed
RK		 9251 if (GET_CODE (x) != CONST_INT)
9252 output_operand_lossage ("invalid %%G value");
9253 else if (INTVAL (x) >= 0)
76229ac8 9254 putc ('z', file);
9854d9ed 9255 else
76229ac8 9256 putc ('m', file);
9854d9ed 9257 return;
e2c953b6 9258
9878760c 9259 case 'h':
a4f6c312
SS		 9260 /* If constant, output low-order five bits. Otherwise, write
9261 normally. */
9878760c 9262 if (INT_P (x))
5f59ecb7 9263 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 31);
9878760c
RK		 9264 else
9265 print_operand (file, x, 0);
9266 return;
9267
64305719 9268 case 'H':
a4f6c312
SS		 9269 /* If constant, output low-order six bits. Otherwise, write
9270 normally. */
64305719 9271 if (INT_P (x))
5f59ecb7 9272 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 63);
64305719
DE		 9273 else
9274 print_operand (file, x, 0);
9275 return;
9276
9854d9ed
RK		 9277 case 'I':
9278 /* Print `i' if this is a constant, else nothing. */
9878760c 9279 if (INT_P (x))
76229ac8 9280 putc ('i', file);
9878760c
RK		 9281 return;
9282
9854d9ed
RK		 9283 case 'j':
9284 /* Write the bit number in CCR for jump. */
9285 i = ccr_bit (x, 0);
9286 if (i == -1)
9287 output_operand_lossage ("invalid %%j code");
9878760c 9288 else
9854d9ed 9289 fprintf (file, "%d", i);
9878760c
RK		 9290 return;
9291
9854d9ed
RK		 9292 case 'J':
9293 /* Similar, but add one for shift count in rlinm for scc and pass
9294 scc flag to `ccr_bit'. */
9295 i = ccr_bit (x, 1);
9296 if (i == -1)
9297 output_operand_lossage ("invalid %%J code");
9298 else
a0466a68
RK		 9299 /* If we want bit 31, write a shift count of zero, not 32. */
9300 fprintf (file, "%d", i == 31 ? 0 : i + 1);
9878760c
RK		 9301 return;
9302
9854d9ed
RK		 9303 case 'k':
9304 /* X must be a constant. Write the 1's complement of the
9305 constant. */
9878760c 9306 if (! INT_P (x))
9854d9ed 9307 output_operand_lossage ("invalid %%k value");
e2c953b6
DE		 9308 else
9309 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ~ INT_LOWPART (x));
9878760c
RK		 9310 return;
9311
81eace42 9312 case 'K':
9ebbca7d
GK		 9313 /* X must be a symbolic constant on ELF. Write an
9314 expression suitable for an 'addi' that adds in the low 16
9315 bits of the MEM. */
9316 if (GET_CODE (x) != CONST)
9317 {
9318 print_operand_address (file, x);
9319 fputs ("@l", file);
9320 }
9321 else
9322 {
9323 if (GET_CODE (XEXP (x, 0)) != PLUS
9324 || (GET_CODE (XEXP (XEXP (x, 0), 0)) != SYMBOL_REF
9325 && GET_CODE (XEXP (XEXP (x, 0), 0)) != LABEL_REF)
9326 || GET_CODE (XEXP (XEXP (x, 0), 1)) != CONST_INT)
53cd5d6c 9327 output_operand_lossage ("invalid %%K value");
9ebbca7d
GK		 9328 print_operand_address (file, XEXP (XEXP (x, 0), 0));
9329 fputs ("@l", file);
ed8d2920
MM		 9330 /* For GNU as, there must be a non-alphanumeric character
9331 between 'l' and the number. The '-' is added by
9332 print_operand() already. */
9333 if (INTVAL (XEXP (XEXP (x, 0), 1)) >= 0)
9334 fputs ("+", file);
9ebbca7d
GK		 9335 print_operand (file, XEXP (XEXP (x, 0), 1), 0);
9336 }
81eace42
GK		 9337 return;
9338
9339 /* %l is output_asm_label. */
9ebbca7d 9340
9854d9ed
RK		 9341 case 'L':
9342 /* Write second word of DImode or DFmode reference. Works on register
9343 or non-indexed memory only. */
9344 if (GET_CODE (x) == REG)
fb5c67a7 9345 fputs (reg_names[REGNO (x) + 1], file);
9854d9ed
RK		 9346 else if (GET_CODE (x) == MEM)
9347 {
9348 /* Handle possible auto-increment. Since it is pre-increment and
1427100a 9349 we have already done it, we can just use an offset of word. */
9854d9ed
RK		 9350 if (GET_CODE (XEXP (x, 0)) == PRE_INC
9351 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
ed8908e7
RK		 9352 output_address (plus_constant (XEXP (XEXP (x, 0), 0),
9353 UNITS_PER_WORD));
9854d9ed 9354 else
d7624dc0
RK		 9355 output_address (XEXP (adjust_address_nv (x, SImode,
9356 UNITS_PER_WORD),
9357 0));
ed8908e7 9358
ba5e43aa 9359 if (small_data_operand (x, GET_MODE (x)))
8fbd2dc7
MM		 9360 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
9361 reg_names[SMALL_DATA_REG]);
9854d9ed 9362 }
9878760c 9363 return;
f676971a 9364
9878760c
RK		 9365 case 'm':
9366 /* MB value for a mask operand. */
b1765bde 9367 if (! mask_operand (x, SImode))
9878760c
RK		 9368 output_operand_lossage ("invalid %%m value");
9369
0ba1b2ff 9370 fprintf (file, "%d", extract_MB (x));
9878760c
RK		 9371 return;
9372
9373 case 'M':
9374 /* ME value for a mask operand. */
b1765bde 9375 if (! mask_operand (x, SImode))
a260abc9 9376 output_operand_lossage ("invalid %%M value");
9878760c 9377
0ba1b2ff 9378 fprintf (file, "%d", extract_ME (x));
9878760c
RK		 9379 return;
9380
81eace42
GK		 9381 /* %n outputs the negative of its operand. */
9382
9878760c
RK		 9383 case 'N':
9384 /* Write the number of elements in the vector times 4. */
9385 if (GET_CODE (x) != PARALLEL)
9386 output_operand_lossage ("invalid %%N value");
e2c953b6
DE		 9387 else
9388 fprintf (file, "%d", XVECLEN (x, 0) * 4);
9878760c
RK		 9389 return;
9390
9391 case 'O':
9392 /* Similar, but subtract 1 first. */
9393 if (GET_CODE (x) != PARALLEL)
1427100a 9394 output_operand_lossage ("invalid %%O value");
e2c953b6
DE		 9395 else
9396 fprintf (file, "%d", (XVECLEN (x, 0) - 1) * 4);
9878760c
RK		 9397 return;
9398
9854d9ed
RK		 9399 case 'p':
9400 /* X is a CONST_INT that is a power of two. Output the logarithm. */
9401 if (! INT_P (x)
2bfcf297 9402 || INT_LOWPART (x) < 0
9854d9ed
RK		 9403 || (i = exact_log2 (INT_LOWPART (x))) < 0)
9404 output_operand_lossage ("invalid %%p value");
e2c953b6
DE		 9405 else
9406 fprintf (file, "%d", i);
9854d9ed
RK		 9407 return;
9408
9878760c
RK		 9409 case 'P':
9410 /* The operand must be an indirect memory reference. The result
8bb418a3 9411 is the register name. */
9878760c
RK		 9412 if (GET_CODE (x) != MEM || GET_CODE (XEXP (x, 0)) != REG
9413 || REGNO (XEXP (x, 0)) >= 32)
9414 output_operand_lossage ("invalid %%P value");
e2c953b6 9415 else
fb5c67a7 9416 fputs (reg_names[REGNO (XEXP (x, 0))], file);
9878760c
RK		 9417 return;
9418
dfbdccdb
GK		 9419 case 'q':
9420 /* This outputs the logical code corresponding to a boolean
9421 expression. The expression may have one or both operands
39a10a29 9422 negated (if one, only the first one). For condition register
c4ad648e
AM		 9423 logical operations, it will also treat the negated
9424 CR codes as NOTs, but not handle NOTs of them. */
dfbdccdb 9425 {
63bc1d05 9426 const char *const *t = 0;
dfbdccdb
GK		 9427 const char *s;
9428 enum rtx_code code = GET_CODE (x);
9429 static const char * const tbl[3][3] = {
9430 { "and", "andc", "nor" },
9431 { "or", "orc", "nand" },
9432 { "xor", "eqv", "xor" } };
9433
9434 if (code == AND)
9435 t = tbl[0];
9436 else if (code == IOR)
9437 t = tbl[1];
9438 else if (code == XOR)
9439 t = tbl[2];
9440 else
9441 output_operand_lossage ("invalid %%q value");
9442
9443 if (GET_CODE (XEXP (x, 0)) != NOT)
9444 s = t[0];
9445 else
9446 {
9447 if (GET_CODE (XEXP (x, 1)) == NOT)
9448 s = t[2];
9449 else
9450 s = t[1];
9451 }
f676971a 9452
dfbdccdb
GK		 9453 fputs (s, file);
9454 }
9455 return;
9456
2c4a9cff
DE		 9457 case 'Q':
9458 if (TARGET_MFCRF)
3b6ce0af 9459 fputc (',', file);
5efb1046 9460 /* FALLTHRU */
2c4a9cff
DE		 9461 else
9462 return;
9463
9854d9ed
RK		 9464 case 'R':
9465 /* X is a CR register. Print the mask for `mtcrf'. */
9466 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
9467 output_operand_lossage ("invalid %%R value");
9468 else
9ebbca7d 9469 fprintf (file, "%d", 128 >> (REGNO (x) - CR0_REGNO));
9878760c 9470 return;
9854d9ed
RK		 9471
9472 case 's':
9473 /* Low 5 bits of 32 - value */
9474 if (! INT_P (x))
9475 output_operand_lossage ("invalid %%s value");
e2c953b6
DE		 9476 else
9477 fprintf (file, HOST_WIDE_INT_PRINT_DEC, (32 - INT_LOWPART (x)) & 31);
9878760c 9478 return;
9854d9ed 9479
a260abc9 9480 case 'S':
0ba1b2ff 9481 /* PowerPC64 mask position. All 0's is excluded.
a260abc9
DE		 9482 CONST_INT 32-bit mask is considered sign-extended so any
9483 transition must occur within the CONST_INT, not on the boundary. */
b1765bde 9484 if (! mask64_operand (x, DImode))
a260abc9
DE		 9485 output_operand_lossage ("invalid %%S value");
9486
0ba1b2ff 9487 uval = INT_LOWPART (x);
a260abc9 9488
0ba1b2ff 9489 if (uval & 1) /* Clear Left */
a260abc9 9490 {
f099d360
GK		 9491#if HOST_BITS_PER_WIDE_INT > 64
9492 uval &= ((unsigned HOST_WIDE_INT) 1 << 64) - 1;
9493#endif
0ba1b2ff 9494 i = 64;
a260abc9 9495 }
0ba1b2ff 9496 else /* Clear Right */
a260abc9 9497 {
0ba1b2ff 9498 uval = ~uval;
f099d360
GK		 9499#if HOST_BITS_PER_WIDE_INT > 64
9500 uval &= ((unsigned HOST_WIDE_INT) 1 << 64) - 1;
9501#endif
0ba1b2ff 9502 i = 63;
a260abc9 9503 }
0ba1b2ff
AM		 9504 while (uval != 0)
9505 --i, uval >>= 1;
9506 if (i < 0)
9507 abort ();
9508 fprintf (file, "%d", i);
9509 return;
a260abc9 9510
a3170dc6
AH		 9511 case 't':
9512 /* Like 'J' but get to the OVERFLOW/UNORDERED bit. */
9513 if (GET_CODE (x) != REG || GET_MODE (x) != CCmode)
9514 abort ();
9515
9516 /* Bit 3 is OV bit. */
9517 i = 4 * (REGNO (x) - CR0_REGNO) + 3;
9518
9519 /* If we want bit 31, write a shift count of zero, not 32. */
9520 fprintf (file, "%d", i == 31 ? 0 : i + 1);
9521 return;
9522
cccf3bdc
DE		 9523 case 'T':
9524 /* Print the symbolic name of a branch target register. */
9525 if (GET_CODE (x) != REG || (REGNO (x) != LINK_REGISTER_REGNUM
9526 && REGNO (x) != COUNT_REGISTER_REGNUM))
9527 output_operand_lossage ("invalid %%T value");
e2c953b6 9528 else if (REGNO (x) == LINK_REGISTER_REGNUM)
cccf3bdc
DE		 9529 fputs (TARGET_NEW_MNEMONICS ? "lr" : "r", file);
9530 else
9531 fputs ("ctr", file);
9532 return;
9533
9854d9ed 9534 case 'u':
802a0058 9535 /* High-order 16 bits of constant for use in unsigned operand. */
9854d9ed
RK		 9536 if (! INT_P (x))
9537 output_operand_lossage ("invalid %%u value");
e2c953b6 9538 else
f676971a 9539 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
e2c953b6 9540 (INT_LOWPART (x) >> 16) & 0xffff);
9878760c
RK		 9541 return;
9542
802a0058
MM		 9543 case 'v':
9544 /* High-order 16 bits of constant for use in signed operand. */
9545 if (! INT_P (x))
9546 output_operand_lossage ("invalid %%v value");
e2c953b6 9547 else
134c32f6
DE		 9548 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
9549 (INT_LOWPART (x) >> 16) & 0xffff);
9550 return;
802a0058 9551
9854d9ed
RK		 9552 case 'U':
9553 /* Print `u' if this has an auto-increment or auto-decrement. */
9554 if (GET_CODE (x) == MEM
9555 && (GET_CODE (XEXP (x, 0)) == PRE_INC
9556 || GET_CODE (XEXP (x, 0)) == PRE_DEC))
76229ac8 9557 putc ('u', file);
9854d9ed 9558 return;
9878760c 9559
e0cd0770
JC		 9560 case 'V':
9561 /* Print the trap code for this operand. */
9562 switch (GET_CODE (x))
9563 {
9564 case EQ:
9565 fputs ("eq", file); /* 4 */
9566 break;
9567 case NE:
9568 fputs ("ne", file); /* 24 */
9569 break;
9570 case LT:
9571 fputs ("lt", file); /* 16 */
9572 break;
9573 case LE:
9574 fputs ("le", file); /* 20 */
9575 break;
9576 case GT:
9577 fputs ("gt", file); /* 8 */
9578 break;
9579 case GE:
9580 fputs ("ge", file); /* 12 */
9581 break;
9582 case LTU:
9583 fputs ("llt", file); /* 2 */
9584 break;
9585 case LEU:
9586 fputs ("lle", file); /* 6 */
9587 break;
9588 case GTU:
9589 fputs ("lgt", file); /* 1 */
9590 break;
9591 case GEU:
9592 fputs ("lge", file); /* 5 */
9593 break;
9594 default:
9595 abort ();
9596 }
9597 break;
9598
9854d9ed
RK		 9599 case 'w':
9600 /* If constant, low-order 16 bits of constant, signed. Otherwise, write
9601 normally. */
9602 if (INT_P (x))
f676971a 9603 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
5f59ecb7 9604 ((INT_LOWPART (x) & 0xffff) ^ 0x8000) - 0x8000);
9854d9ed
RK		 9605 else
9606 print_operand (file, x, 0);
9878760c
RK		 9607 return;
9608
9854d9ed 9609 case 'W':
e2c953b6 9610 /* MB value for a PowerPC64 rldic operand. */
e2c953b6
DE		 9611 val = (GET_CODE (x) == CONST_INT
9612 ? INTVAL (x) : CONST_DOUBLE_HIGH (x));
9613
9614 if (val < 0)
9615 i = -1;
9854d9ed 9616 else
e2c953b6
DE		 9617 for (i = 0; i < HOST_BITS_PER_WIDE_INT; i++)
9618 if ((val <<= 1) < 0)
9619 break;
9620
9621#if HOST_BITS_PER_WIDE_INT == 32
9622 if (GET_CODE (x) == CONST_INT && i >= 0)
9623 i += 32; /* zero-extend high-part was all 0's */
9624 else if (GET_CODE (x) == CONST_DOUBLE && i == 32)
9625 {
9626 val = CONST_DOUBLE_LOW (x);
9627
9628 if (val == 0)
a4f6c312 9629 abort ();
e2c953b6
DE		 9630 else if (val < 0)
9631 --i;
9632 else
9633 for ( ; i < 64; i++)
9634 if ((val <<= 1) < 0)
9635 break;
9636 }
9637#endif
9638
9639 fprintf (file, "%d", i + 1);
9854d9ed 9640 return;
9878760c 9641
9854d9ed
RK		 9642 case 'X':
9643 if (GET_CODE (x) == MEM
4d588c14 9644 && legitimate_indexed_address_p (XEXP (x, 0), 0))
76229ac8 9645 putc ('x', file);
9854d9ed 9646 return;
9878760c 9647
9854d9ed
RK		 9648 case 'Y':
9649 /* Like 'L', for third word of TImode */
9650 if (GET_CODE (x) == REG)
fb5c67a7 9651 fputs (reg_names[REGNO (x) + 2], file);
9854d9ed 9652 else if (GET_CODE (x) == MEM)
9878760c 9653 {
9854d9ed
RK		 9654 if (GET_CODE (XEXP (x, 0)) == PRE_INC
9655 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
a54d04b7 9656 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 8));
9854d9ed 9657 else
d7624dc0 9658 output_address (XEXP (adjust_address_nv (x, SImode, 8), 0));
ba5e43aa 9659 if (small_data_operand (x, GET_MODE (x)))
8fbd2dc7
MM		 9660 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
9661 reg_names[SMALL_DATA_REG]);
9878760c
RK		 9662 }
9663 return;
f676971a 9664
9878760c 9665 case 'z':
b4ac57ab
RS		 9666 /* X is a SYMBOL_REF. Write out the name preceded by a
9667 period and without any trailing data in brackets. Used for function
4d30c363
MM		 9668 names. If we are configured for System V (or the embedded ABI) on
9669 the PowerPC, do not emit the period, since those systems do not use
9670 TOCs and the like. */
9878760c
RK		 9671 if (GET_CODE (x) != SYMBOL_REF)
9672 abort ();
9673
c4ad648e
AM		 9674 /* Mark the decl as referenced so that cgraph will output the
9675 function. */
9bf6462a 9676 if (SYMBOL_REF_DECL (x))
c4ad648e 9677 mark_decl_referenced (SYMBOL_REF_DECL (x));
9bf6462a 9678
85b776df 9679 /* For macho, check to see if we need a stub. */
f9da97f0
AP		 9680 if (TARGET_MACHO)
9681 {
9682 const char *name = XSTR (x, 0);
a031e781 9683#if TARGET_MACHO
3b48085e 9684 if (MACHOPIC_INDIRECT
11abc112
MM		 9685 && machopic_classify_symbol (x) == MACHOPIC_UNDEFINED_FUNCTION)
9686 name = machopic_indirection_name (x, /*stub_p=*/true);
f9da97f0
AP		 9687#endif
9688 assemble_name (file, name);
9689 }
85b776df 9690 else if (!DOT_SYMBOLS)
9739c90c 9691 assemble_name (file, XSTR (x, 0));
85b776df
AM		 9692 else
9693 rs6000_output_function_entry (file, XSTR (x, 0));
9878760c
RK		 9694 return;
9695
9854d9ed
RK		 9696 case 'Z':
9697 /* Like 'L', for last word of TImode. */
9698 if (GET_CODE (x) == REG)
fb5c67a7 9699 fputs (reg_names[REGNO (x) + 3], file);
9854d9ed
RK		 9700 else if (GET_CODE (x) == MEM)
9701 {
9702 if (GET_CODE (XEXP (x, 0)) == PRE_INC
9703 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
a54d04b7 9704 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 12));
9854d9ed 9705 else
d7624dc0 9706 output_address (XEXP (adjust_address_nv (x, SImode, 12), 0));
ba5e43aa 9707 if (small_data_operand (x, GET_MODE (x)))
8fbd2dc7
MM		 9708 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
9709 reg_names[SMALL_DATA_REG]);
9854d9ed 9710 }
5c23c401 9711 return;
0ac081f6 9712
a3170dc6 9713 /* Print AltiVec or SPE memory operand. */
0ac081f6
AH		 9714 case 'y':
9715 {
9716 rtx tmp;
9717
9718 if (GET_CODE (x) != MEM)
9719 abort ();
9720
9721 tmp = XEXP (x, 0);
9722
993f19a8 9723 if (TARGET_E500)
a3170dc6
AH		 9724 {
9725 /* Handle [reg]. */
9726 if (GET_CODE (tmp) == REG)
9727 {
9728 fprintf (file, "0(%s)", reg_names[REGNO (tmp)]);
9729 break;
9730 }
9731 /* Handle [reg+UIMM]. */
9732 else if (GET_CODE (tmp) == PLUS &&
9733 GET_CODE (XEXP (tmp, 1)) == CONST_INT)
9734 {
9735 int x;
9736
9737 if (GET_CODE (XEXP (tmp, 0)) != REG)
9738 abort ();
9739
9740 x = INTVAL (XEXP (tmp, 1));
9741 fprintf (file, "%d(%s)", x, reg_names[REGNO (XEXP (tmp, 0))]);
9742 break;
9743 }
9744
9745 /* Fall through. Must be [reg+reg]. */
9746 }
850e8d3d
DN		 9747 if (TARGET_ALTIVEC
9748 && GET_CODE (tmp) == AND
9749 && GET_CODE (XEXP (tmp, 1)) == CONST_INT
9750 && INTVAL (XEXP (tmp, 1)) == -16)
9751 tmp = XEXP (tmp, 0);
0ac081f6 9752 if (GET_CODE (tmp) == REG)
c62f2db5 9753 fprintf (file, "0,%s", reg_names[REGNO (tmp)]);
0ac081f6
AH		 9754 else if (GET_CODE (tmp) == PLUS && GET_CODE (XEXP (tmp, 1)) == REG)
9755 {
9756 if (REGNO (XEXP (tmp, 0)) == 0)
9757 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 1)) ],
9758 reg_names[ REGNO (XEXP (tmp, 0)) ]);
9759 else
9760 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 0)) ],
9761 reg_names[ REGNO (XEXP (tmp, 1)) ]);
9762 }
9763 else
9764 abort ();
9765 break;
9766 }
f676971a 9767
9878760c
RK		 9768 case 0:
9769 if (GET_CODE (x) == REG)
9770 fprintf (file, "%s", reg_names[REGNO (x)]);
9771 else if (GET_CODE (x) == MEM)
9772 {
9773 /* We need to handle PRE_INC and PRE_DEC here, since we need to
9774 know the width from the mode. */
9775 if (GET_CODE (XEXP (x, 0)) == PRE_INC)
79ba6d34
MM		 9776 fprintf (file, "%d(%s)", GET_MODE_SIZE (GET_MODE (x)),
9777 reg_names[REGNO (XEXP (XEXP (x, 0), 0))]);
9878760c 9778 else if (GET_CODE (XEXP (x, 0)) == PRE_DEC)
79ba6d34
MM		 9779 fprintf (file, "%d(%s)", - GET_MODE_SIZE (GET_MODE (x)),
9780 reg_names[REGNO (XEXP (XEXP (x, 0), 0))]);
9878760c 9781 else
a54d04b7 9782 output_address (XEXP (x, 0));
9878760c
RK		 9783 }
9784 else
a54d04b7 9785 output_addr_const (file, x);
a85d226b 9786 return;
9878760c 9787
c4501e62
JJ		 9788 case '&':
9789 assemble_name (file, rs6000_get_some_local_dynamic_name ());
9790 return;
9791
9878760c
RK		 9792 default:
9793 output_operand_lossage ("invalid %%xn code");
9794 }
9795}
9796\f
9797/* Print the address of an operand. */
9798
9799void
a2369ed3 9800print_operand_address (FILE *file, rtx x)
9878760c
RK		 9801{
9802 if (GET_CODE (x) == REG)
4697a36c 9803 fprintf (file, "0(%s)", reg_names[ REGNO (x) ]);
9ebbca7d
GK		 9804 else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST
9805 || GET_CODE (x) == LABEL_REF)
9878760c
RK		 9806 {
9807 output_addr_const (file, x);
ba5e43aa 9808 if (small_data_operand (x, GET_MODE (x)))
8fbd2dc7
MM		 9809 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
9810 reg_names[SMALL_DATA_REG]);
9ebbca7d 9811 else if (TARGET_TOC)
a4f6c312 9812 abort ();
9878760c
RK		 9813 }
9814 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == REG)
9815 {
9816 if (REGNO (XEXP (x, 0)) == 0)
4697a36c
MM		 9817 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 1)) ],
9818 reg_names[ REGNO (XEXP (x, 0)) ]);
9878760c 9819 else
4697a36c
MM		 9820 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 0)) ],
9821 reg_names[ REGNO (XEXP (x, 1)) ]);
9878760c
RK		 9822 }
9823 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT)
4a0a75dd
KG		 9824 fprintf (file, HOST_WIDE_INT_PRINT_DEC "(%s)",
9825 INTVAL (XEXP (x, 1)), reg_names[ REGNO (XEXP (x, 0)) ]);
3cb999d8
DE		 9826#if TARGET_ELF
9827 else if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 0)) == REG
c4ad648e 9828 && CONSTANT_P (XEXP (x, 1)))
4697a36c
MM		 9829 {
9830 output_addr_const (file, XEXP (x, 1));
9831 fprintf (file, "@l(%s)", reg_names[ REGNO (XEXP (x, 0)) ]);
9832 }
c859cda6
DJ		 9833#endif
9834#if TARGET_MACHO
9835 else if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 0)) == REG
c4ad648e 9836 && CONSTANT_P (XEXP (x, 1)))
c859cda6
DJ		 9837 {
9838 fprintf (file, "lo16(");
9839 output_addr_const (file, XEXP (x, 1));
9840 fprintf (file, ")(%s)", reg_names[ REGNO (XEXP (x, 0)) ]);
9841 }
3cb999d8 9842#endif
4d588c14 9843 else if (legitimate_constant_pool_address_p (x))
9ebbca7d 9844 {
2bfcf297 9845 if (TARGET_AIX && (!TARGET_ELF || !TARGET_MINIMAL_TOC))
9ebbca7d 9846 {
2bfcf297
DB		 9847 rtx contains_minus = XEXP (x, 1);
9848 rtx minus, symref;
9849 const char *name;
f676971a 9850
9ebbca7d 9851 /* Find the (minus (sym) (toc)) buried in X, and temporarily
a4f6c312 9852 turn it into (sym) for output_addr_const. */
9ebbca7d
GK		 9853 while (GET_CODE (XEXP (contains_minus, 0)) != MINUS)
9854 contains_minus = XEXP (contains_minus, 0);
9855
2bfcf297
DB		 9856 minus = XEXP (contains_minus, 0);
9857 symref = XEXP (minus, 0);
9858 XEXP (contains_minus, 0) = symref;
9859 if (TARGET_ELF)
9860 {
9861 char *newname;
9862
9863 name = XSTR (symref, 0);
9864 newname = alloca (strlen (name) + sizeof ("@toc"));
9865 strcpy (newname, name);
9866 strcat (newname, "@toc");
9867 XSTR (symref, 0) = newname;
9868 }
9869 output_addr_const (file, XEXP (x, 1));
9870 if (TARGET_ELF)
9871 XSTR (symref, 0) = name;
9ebbca7d
GK		 9872 XEXP (contains_minus, 0) = minus;
9873 }
9874 else
9875 output_addr_const (file, XEXP (x, 1));
9876
9877 fprintf (file, "(%s)", reg_names[REGNO (XEXP (x, 0))]);
9878 }
9878760c
RK		 9879 else
9880 abort ();
9881}
9882\f
88cad84b 9883/* Target hook for assembling integer objects. The PowerPC version has
301d03af
RS		 9884 to handle fixup entries for relocatable code if RELOCATABLE_NEEDS_FIXUP
9885 is defined. It also needs to handle DI-mode objects on 64-bit
9886 targets. */
9887
9888static bool
a2369ed3 9889rs6000_assemble_integer (rtx x, unsigned int size, int aligned_p)
301d03af 9890{
f4f4921e 9891#ifdef RELOCATABLE_NEEDS_FIXUP
301d03af 9892 /* Special handling for SI values. */
84dcde01 9893 if (RELOCATABLE_NEEDS_FIXUP && size == 4 && aligned_p)
301d03af 9894 {
a2369ed3 9895 extern int in_toc_section (void);
301d03af 9896 static int recurse = 0;
f676971a 9897
301d03af
RS		 9898 /* For -mrelocatable, we mark all addresses that need to be fixed up
9899 in the .fixup section. */
9900 if (TARGET_RELOCATABLE
9901 && !in_toc_section ()
9902 && !in_text_section ()
642af3be 9903 && !in_unlikely_text_section ()
301d03af
RS		 9904 && !recurse
9905 && GET_CODE (x) != CONST_INT
9906 && GET_CODE (x) != CONST_DOUBLE
9907 && CONSTANT_P (x))
9908 {
9909 char buf[256];
9910
9911 recurse = 1;
9912 ASM_GENERATE_INTERNAL_LABEL (buf, "LCP", fixuplabelno);
9913 fixuplabelno++;
9914 ASM_OUTPUT_LABEL (asm_out_file, buf);
9915 fprintf (asm_out_file, "\t.long\t(");
9916 output_addr_const (asm_out_file, x);
9917 fprintf (asm_out_file, ")@fixup\n");
9918 fprintf (asm_out_file, "\t.section\t\".fixup\",\"aw\"\n");
9919 ASM_OUTPUT_ALIGN (asm_out_file, 2);
9920 fprintf (asm_out_file, "\t.long\t");
9921 assemble_name (asm_out_file, buf);
9922 fprintf (asm_out_file, "\n\t.previous\n");
9923 recurse = 0;
9924 return true;
9925 }
9926 /* Remove initial .'s to turn a -mcall-aixdesc function
9927 address into the address of the descriptor, not the function
9928 itself. */
9929 else if (GET_CODE (x) == SYMBOL_REF
9930 && XSTR (x, 0)[0] == '.'
9931 && DEFAULT_ABI == ABI_AIX)
9932 {
9933 const char *name = XSTR (x, 0);
9934 while (*name == '.')
9935 name++;
9936
9937 fprintf (asm_out_file, "\t.long\t%s\n", name);
9938 return true;
9939 }
9940 }
f4f4921e 9941#endif /* RELOCATABLE_NEEDS_FIXUP */
301d03af
RS		 9942 return default_assemble_integer (x, size, aligned_p);
9943}
93638d7a
AM		 9944
9945#ifdef HAVE_GAS_HIDDEN
9946/* Emit an assembler directive to set symbol visibility for DECL to
9947 VISIBILITY_TYPE. */
9948
5add3202 9949static void
a2369ed3 9950rs6000_assemble_visibility (tree decl, int vis)
93638d7a 9951{
93638d7a
AM		 9952 /* Functions need to have their entry point symbol visibility set as
9953 well as their descriptor symbol visibility. */
85b776df
AM		 9954 if (DEFAULT_ABI == ABI_AIX
9955 && DOT_SYMBOLS
9956 && TREE_CODE (decl) == FUNCTION_DECL)
93638d7a 9957 {
25fdb4dc 9958 static const char * const visibility_types[] = {
c4ad648e 9959 NULL, "internal", "hidden", "protected"
25fdb4dc
RH		 9960 };
9961
9962 const char *name, *type;
93638d7a
AM		 9963
9964 name = ((* targetm.strip_name_encoding)
9965 (IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl))));
25fdb4dc 9966 type = visibility_types[vis];
93638d7a 9967
25fdb4dc
RH		 9968 fprintf (asm_out_file, "\t.%s\t%s\n", type, name);
9969 fprintf (asm_out_file, "\t.%s\t.%s\n", type, name);
93638d7a 9970 }
25fdb4dc
RH		 9971 else
9972 default_assemble_visibility (decl, vis);
93638d7a
AM		 9973}
9974#endif
301d03af 9975\f
39a10a29 9976enum rtx_code
a2369ed3 9977rs6000_reverse_condition (enum machine_mode mode, enum rtx_code code)
39a10a29
GK		 9978{
9979 /* Reversal of FP compares takes care -- an ordered compare
9980 becomes an unordered compare and vice versa. */
f676971a 9981 if (mode == CCFPmode
bc9ec0e0
GK		 9982 && (!flag_finite_math_only
9983 || code == UNLT || code == UNLE || code == UNGT || code == UNGE
9984 || code == UNEQ || code == LTGT))
bab6226b 9985 return reverse_condition_maybe_unordered (code);
39a10a29 9986 else
bab6226b 9987 return reverse_condition (code);
39a10a29
GK		 9988}
9989
39a10a29
GK		 9990/* Generate a compare for CODE. Return a brand-new rtx that
9991 represents the result of the compare. */
a4f6c312 9992
39a10a29 9993static rtx
a2369ed3 9994rs6000_generate_compare (enum rtx_code code)
39a10a29
GK		 9995{
9996 enum machine_mode comp_mode;
9997 rtx compare_result;
9998
9999 if (rs6000_compare_fp_p)
10000 comp_mode = CCFPmode;
10001 else if (code == GTU || code == LTU
c4ad648e 10002 || code == GEU || code == LEU)
39a10a29 10003 comp_mode = CCUNSmode;
60934f9c
NS		 10004 else if ((code == EQ || code == NE)
10005 && GET_CODE (rs6000_compare_op0) == SUBREG
10006 && GET_CODE (rs6000_compare_op1) == SUBREG
10007 && SUBREG_PROMOTED_UNSIGNED_P (rs6000_compare_op0)
10008 && SUBREG_PROMOTED_UNSIGNED_P (rs6000_compare_op1))
10009 /* These are unsigned values, perhaps there will be a later
10010 ordering compare that can be shared with this one.
10011 Unfortunately we cannot detect the signedness of the operands
10012 for non-subregs. */
10013 comp_mode = CCUNSmode;
39a10a29
GK		 10014 else
10015 comp_mode = CCmode;
10016
10017 /* First, the compare. */
10018 compare_result = gen_reg_rtx (comp_mode);
a3170dc6
AH		 10019
10020 /* SPE FP compare instructions on the GPRs. Yuck! */
993f19a8
AH		 10021 if ((TARGET_E500 && !TARGET_FPRS && TARGET_HARD_FLOAT)
10022 && rs6000_compare_fp_p)
a3170dc6 10023 {
64022b5d 10024 rtx cmp, or_result, compare_result2;
4d4cbc0e
AH		 10025 enum machine_mode op_mode = GET_MODE (rs6000_compare_op0);
10026
10027 if (op_mode == VOIDmode)
10028 op_mode = GET_MODE (rs6000_compare_op1);
a3170dc6 10029
423c1189
AH		 10030 /* Note: The E500 comparison instructions set the GT bit (x +
10031 1), on success. This explains the mess. */
10032
a3170dc6
AH		 10033 switch (code)
10034 {
423c1189 10035 case EQ: case UNEQ: case NE: case LTGT:
4d4cbc0e 10036 if (op_mode == SFmode)
5ca18999 10037 cmp = flag_unsafe_math_optimizations
4d4cbc0e
AH		 10038 ? gen_tstsfeq_gpr (compare_result, rs6000_compare_op0,
10039 rs6000_compare_op1)
10040 : gen_cmpsfeq_gpr (compare_result, rs6000_compare_op0,
10041 rs6000_compare_op1);
10042 else if (op_mode == DFmode)
5ca18999 10043 cmp = flag_unsafe_math_optimizations
4d4cbc0e
AH		 10044 ? gen_tstdfeq_gpr (compare_result, rs6000_compare_op0,
10045 rs6000_compare_op1)
10046 : gen_cmpdfeq_gpr (compare_result, rs6000_compare_op0,
10047 rs6000_compare_op1);
10048 else abort ();
a3170dc6 10049 break;
423c1189 10050 case GT: case GTU: case UNGT: case UNGE: case GE: case GEU:
4d4cbc0e 10051 if (op_mode == SFmode)
5ca18999 10052 cmp = flag_unsafe_math_optimizations
4d4cbc0e
AH		 10053 ? gen_tstsfgt_gpr (compare_result, rs6000_compare_op0,
10054 rs6000_compare_op1)
10055 : gen_cmpsfgt_gpr (compare_result, rs6000_compare_op0,
10056 rs6000_compare_op1);
10057 else if (op_mode == DFmode)
5ca18999 10058 cmp = flag_unsafe_math_optimizations
4d4cbc0e
AH		 10059 ? gen_tstdfgt_gpr (compare_result, rs6000_compare_op0,
10060 rs6000_compare_op1)
10061 : gen_cmpdfgt_gpr (compare_result, rs6000_compare_op0,
10062 rs6000_compare_op1);
10063 else abort ();
a3170dc6 10064 break;
423c1189 10065 case LT: case LTU: case UNLT: case UNLE: case LE: case LEU:
4d4cbc0e 10066 if (op_mode == SFmode)
5ca18999 10067 cmp = flag_unsafe_math_optimizations
4d4cbc0e
AH		 10068 ? gen_tstsflt_gpr (compare_result, rs6000_compare_op0,
10069 rs6000_compare_op1)
10070 : gen_cmpsflt_gpr (compare_result, rs6000_compare_op0,
10071 rs6000_compare_op1);
10072 else if (op_mode == DFmode)
5ca18999 10073 cmp = flag_unsafe_math_optimizations
4d4cbc0e
AH		 10074 ? gen_tstdflt_gpr (compare_result, rs6000_compare_op0,
10075 rs6000_compare_op1)
10076 : gen_cmpdflt_gpr (compare_result, rs6000_compare_op0,
10077 rs6000_compare_op1);
10078 else abort ();
a3170dc6 10079 break;
4d4cbc0e
AH		 10080 default:
10081 abort ();
a3170dc6
AH		 10082 }
10083
10084 /* Synthesize LE and GE from LT/GT || EQ. */
10085 if (code == LE || code == GE || code == LEU || code == GEU)
10086 {
a3170dc6
AH		 10087 emit_insn (cmp);
10088
10089 switch (code)
10090 {
10091 case LE: code = LT; break;
10092 case GE: code = GT; break;
10093 case LEU: code = LT; break;
10094 case GEU: code = GT; break;
10095 default: abort ();
10096 }
10097
a3170dc6
AH		 10098 compare_result2 = gen_reg_rtx (CCFPmode);
10099
10100 /* Do the EQ. */
4d4cbc0e 10101 if (op_mode == SFmode)
5ca18999 10102 cmp = flag_unsafe_math_optimizations
4d4cbc0e
AH		 10103 ? gen_tstsfeq_gpr (compare_result2, rs6000_compare_op0,
10104 rs6000_compare_op1)
10105 : gen_cmpsfeq_gpr (compare_result2, rs6000_compare_op0,
10106 rs6000_compare_op1);
10107 else if (op_mode == DFmode)
5ca18999 10108 cmp = flag_unsafe_math_optimizations
4d4cbc0e
AH		 10109 ? gen_tstdfeq_gpr (compare_result2, rs6000_compare_op0,
10110 rs6000_compare_op1)
10111 : gen_cmpdfeq_gpr (compare_result2, rs6000_compare_op0,
10112 rs6000_compare_op1);
10113 else abort ();
a3170dc6
AH		 10114 emit_insn (cmp);
10115
a3170dc6 10116 /* OR them together. */
64022b5d
AH		 10117 or_result = gen_reg_rtx (CCFPmode);
10118 cmp = gen_e500_cr_ior_compare (or_result, compare_result,
10119 compare_result2);
a3170dc6
AH		 10120 compare_result = or_result;
10121 code = EQ;
10122 }
10123 else
10124 {
a3170dc6 10125 if (code == NE || code == LTGT)
a3170dc6 10126 code = NE;
423c1189
AH		 10127 else
10128 code = EQ;
a3170dc6
AH		 10129 }
10130
10131 emit_insn (cmp);
10132 }
10133 else
de17c25f
DE		 10134 {
10135 /* Generate XLC-compatible TFmode compare as PARALLEL with extra
10136 CLOBBERs to match cmptf_internal2 pattern. */
10137 if (comp_mode == CCFPmode && TARGET_XL_COMPAT
10138 && GET_MODE (rs6000_compare_op0) == TFmode
10139 && (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
10140 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128)
10141 emit_insn (gen_rtx_PARALLEL (VOIDmode,
10142 gen_rtvec (9,
10143 gen_rtx_SET (VOIDmode,
10144 compare_result,
10145 gen_rtx_COMPARE (comp_mode,
10146 rs6000_compare_op0,
10147 rs6000_compare_op1)),
10148 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
10149 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
10150 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
10151 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
10152 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
10153 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
10154 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
10155 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)))));
10156 else
10157 emit_insn (gen_rtx_SET (VOIDmode, compare_result,
10158 gen_rtx_COMPARE (comp_mode,
10159 rs6000_compare_op0,
10160 rs6000_compare_op1)));
10161 }
f676971a 10162
ca5adc63 10163 /* Some kinds of FP comparisons need an OR operation;
5ca18999 10164 under flag_unsafe_math_optimizations we don't bother. */
39a10a29 10165 if (rs6000_compare_fp_p
5ca18999 10166 && ! flag_unsafe_math_optimizations
993f19a8 10167 && ! (TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS)
39a10a29
GK		 10168 && (code == LE || code == GE
10169 || code == UNEQ || code == LTGT
10170 || code == UNGT || code == UNLT))
10171 {
10172 enum rtx_code or1, or2;
10173 rtx or1_rtx, or2_rtx, compare2_rtx;
10174 rtx or_result = gen_reg_rtx (CCEQmode);
f676971a 10175
39a10a29
GK		 10176 switch (code)
10177 {
10178 case LE: or1 = LT; or2 = EQ; break;
10179 case GE: or1 = GT; or2 = EQ; break;
10180 case UNEQ: or1 = UNORDERED; or2 = EQ; break;
10181 case LTGT: or1 = LT; or2 = GT; break;
10182 case UNGT: or1 = UNORDERED; or2 = GT; break;
10183 case UNLT: or1 = UNORDERED; or2 = LT; break;
10184 default: abort ();
10185 }
10186 validate_condition_mode (or1, comp_mode);
10187 validate_condition_mode (or2, comp_mode);
1c563bed
KH		 10188 or1_rtx = gen_rtx_fmt_ee (or1, SImode, compare_result, const0_rtx);
10189 or2_rtx = gen_rtx_fmt_ee (or2, SImode, compare_result, const0_rtx);
39a10a29
GK		 10190 compare2_rtx = gen_rtx_COMPARE (CCEQmode,
10191 gen_rtx_IOR (SImode, or1_rtx, or2_rtx),
10192 const_true_rtx);
10193 emit_insn (gen_rtx_SET (VOIDmode, or_result, compare2_rtx));
10194
10195 compare_result = or_result;
10196 code = EQ;
10197 }
10198
10199 validate_condition_mode (code, GET_MODE (compare_result));
f676971a 10200
1c563bed 10201 return gen_rtx_fmt_ee (code, VOIDmode, compare_result, const0_rtx);
39a10a29
GK		 10202}
10203
10204
10205/* Emit the RTL for an sCOND pattern. */
10206
10207void
a2369ed3 10208rs6000_emit_sCOND (enum rtx_code code, rtx result)
39a10a29
GK		 10209{
10210 rtx condition_rtx;
10211 enum machine_mode op_mode;
b7053a3f 10212 enum rtx_code cond_code;
39a10a29
GK		 10213
10214 condition_rtx = rs6000_generate_compare (code);
b7053a3f
GK		 10215 cond_code = GET_CODE (condition_rtx);
10216
423c1189
AH		 10217 if (TARGET_E500 && rs6000_compare_fp_p
10218 && !TARGET_FPRS && TARGET_HARD_FLOAT)
10219 {
10220 rtx t;
10221
10222 PUT_MODE (condition_rtx, SImode);
10223 t = XEXP (condition_rtx, 0);
10224
10225 if (cond_code != NE && cond_code != EQ)
10226 abort ();
10227
10228 if (cond_code == NE)
64022b5d 10229 emit_insn (gen_e500_flip_gt_bit (t, t));
423c1189 10230
64022b5d 10231 emit_insn (gen_move_from_CR_gt_bit (result, t));
423c1189
AH		 10232 return;
10233 }
10234
b7053a3f
GK		 10235 if (cond_code == NE
10236 || cond_code == GE || cond_code == LE
10237 || cond_code == GEU || cond_code == LEU
10238 || cond_code == ORDERED || cond_code == UNGE || cond_code == UNLE)
10239 {
10240 rtx not_result = gen_reg_rtx (CCEQmode);
10241 rtx not_op, rev_cond_rtx;
10242 enum machine_mode cc_mode;
f676971a 10243
b7053a3f
GK		 10244 cc_mode = GET_MODE (XEXP (condition_rtx, 0));
10245
1c563bed 10246 rev_cond_rtx = gen_rtx_fmt_ee (rs6000_reverse_condition (cc_mode, cond_code),
0f4c242b 10247 SImode, XEXP (condition_rtx, 0), const0_rtx);
b7053a3f
GK		 10248 not_op = gen_rtx_COMPARE (CCEQmode, rev_cond_rtx, const0_rtx);
10249 emit_insn (gen_rtx_SET (VOIDmode, not_result, not_op));
10250 condition_rtx = gen_rtx_EQ (VOIDmode, not_result, const0_rtx);
10251 }
39a10a29
GK		 10252
10253 op_mode = GET_MODE (rs6000_compare_op0);
10254 if (op_mode == VOIDmode)
10255 op_mode = GET_MODE (rs6000_compare_op1);
10256
10257 if (TARGET_POWERPC64 && (op_mode == DImode || rs6000_compare_fp_p))
10258 {
10259 PUT_MODE (condition_rtx, DImode);
10260 convert_move (result, condition_rtx, 0);
10261 }
10262 else
10263 {
10264 PUT_MODE (condition_rtx, SImode);
10265 emit_insn (gen_rtx_SET (VOIDmode, result, condition_rtx));
10266 }
10267}
10268
39a10a29
GK		 10269/* Emit a branch of kind CODE to location LOC. */
10270
10271void
a2369ed3 10272rs6000_emit_cbranch (enum rtx_code code, rtx loc)
39a10a29
GK		 10273{
10274 rtx condition_rtx, loc_ref;
10275
10276 condition_rtx = rs6000_generate_compare (code);
10277 loc_ref = gen_rtx_LABEL_REF (VOIDmode, loc);
10278 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
10279 gen_rtx_IF_THEN_ELSE (VOIDmode, condition_rtx,
10280 loc_ref, pc_rtx)));
10281}
10282
12a4e8c5
GK		 10283/* Return the string to output a conditional branch to LABEL, which is
10284 the operand number of the label, or -1 if the branch is really a
f676971a 10285 conditional return.
12a4e8c5
GK		 10286
10287 OP is the conditional expression. XEXP (OP, 0) is assumed to be a
10288 condition code register and its mode specifies what kind of
10289 comparison we made.
10290
a0ab749a 10291 REVERSED is nonzero if we should reverse the sense of the comparison.
12a4e8c5
GK		 10292
10293 INSN is the insn. */
10294
10295char *
a2369ed3 10296output_cbranch (rtx op, const char *label, int reversed, rtx insn)
12a4e8c5
GK		 10297{
10298 static char string[64];
10299 enum rtx_code code = GET_CODE (op);
10300 rtx cc_reg = XEXP (op, 0);
10301 enum machine_mode mode = GET_MODE (cc_reg);
10302 int cc_regno = REGNO (cc_reg) - CR0_REGNO;
39a10a29 10303 int need_longbranch = label != NULL && get_attr_length (insn) == 8;
12a4e8c5
GK		 10304 int really_reversed = reversed ^ need_longbranch;
10305 char *s = string;
10306 const char *ccode;
10307 const char *pred;
10308 rtx note;
10309
39a10a29
GK		 10310 validate_condition_mode (code, mode);
10311
10312 /* Work out which way this really branches. We could use
10313 reverse_condition_maybe_unordered here always but this
10314 makes the resulting assembler clearer. */
12a4e8c5 10315 if (really_reversed)
de40e1df
DJ		 10316 {
10317 /* Reversal of FP compares takes care -- an ordered compare
10318 becomes an unordered compare and vice versa. */
10319 if (mode == CCFPmode)
10320 code = reverse_condition_maybe_unordered (code);
10321 else
10322 code = reverse_condition (code);
10323 }
12a4e8c5 10324
993f19a8 10325 if ((TARGET_E500 && !TARGET_FPRS && TARGET_HARD_FLOAT) && mode == CCFPmode)
a3170dc6
AH		 10326 {
10327 /* The efscmp/tst* instructions twiddle bit 2, which maps nicely
10328 to the GT bit. */
10329 if (code == EQ)
10330 /* Opposite of GT. */
a3170dc6 10331 code = GT;
423c1189
AH		 10332 else if (code == NE)
10333 code = UNLE;
a3170dc6
AH		 10334 else
10335 abort ();
10336 }
10337
39a10a29 10338 switch (code)
12a4e8c5
GK		 10339 {
10340 /* Not all of these are actually distinct opcodes, but
10341 we distinguish them for clarity of the resulting assembler. */
50a0b056
GK		 10342 case NE: case LTGT:
10343 ccode = "ne"; break;
10344 case EQ: case UNEQ:
10345 ccode = "eq"; break;
f676971a 10346 case GE: case GEU:
50a0b056 10347 ccode = "ge"; break;
f676971a 10348 case GT: case GTU: case UNGT:
50a0b056 10349 ccode = "gt"; break;
f676971a 10350 case LE: case LEU:
50a0b056 10351 ccode = "le"; break;
f676971a 10352 case LT: case LTU: case UNLT:
50a0b056 10353 ccode = "lt"; break;
12a4e8c5
GK		 10354 case UNORDERED: ccode = "un"; break;
10355 case ORDERED: ccode = "nu"; break;
10356 case UNGE: ccode = "nl"; break;
10357 case UNLE: ccode = "ng"; break;
10358 default:
a4f6c312 10359 abort ();
12a4e8c5 10360 }
f676971a
EC		 10361
10362 /* Maybe we have a guess as to how likely the branch is.
94a54f47 10363 The old mnemonics don't have a way to specify this information. */
f4857b9b 10364 pred = "";
12a4e8c5
GK		 10365 note = find_reg_note (insn, REG_BR_PROB, NULL_RTX);
10366 if (note != NULL_RTX)
10367 {
10368 /* PROB is the difference from 50%. */
10369 int prob = INTVAL (XEXP (note, 0)) - REG_BR_PROB_BASE / 2;
f4857b9b
AM		 10370
10371 /* Only hint for highly probable/improbable branches on newer
10372 cpus as static prediction overrides processor dynamic
10373 prediction. For older cpus we may as well always hint, but
10374 assume not taken for branches that are very close to 50% as a
10375 mispredicted taken branch is more expensive than a
f676971a 10376 mispredicted not-taken branch. */
ec507f2d 10377 if (rs6000_always_hint
f4857b9b
AM		 10378 || abs (prob) > REG_BR_PROB_BASE / 100 * 48)
10379 {
10380 if (abs (prob) > REG_BR_PROB_BASE / 20
10381 && ((prob > 0) ^ need_longbranch))
c4ad648e 10382 pred = "+";
f4857b9b
AM		 10383 else
10384 pred = "-";
10385 }
12a4e8c5 10386 }
12a4e8c5
GK		 10387
10388 if (label == NULL)
94a54f47 10389 s += sprintf (s, "{b%sr|b%slr%s} ", ccode, ccode, pred);
12a4e8c5 10390 else
94a54f47 10391 s += sprintf (s, "{b%s|b%s%s} ", ccode, ccode, pred);
12a4e8c5 10392
37c67319 10393 /* We need to escape any '%' characters in the reg_names string.
a3c9585f 10394 Assume they'd only be the first character.... */
37c67319
GK		 10395 if (reg_names[cc_regno + CR0_REGNO][0] == '%')
10396 *s++ = '%';
94a54f47 10397 s += sprintf (s, "%s", reg_names[cc_regno + CR0_REGNO]);
12a4e8c5
GK		 10398
10399 if (label != NULL)
10400 {
10401 /* If the branch distance was too far, we may have to use an
10402 unconditional branch to go the distance. */
10403 if (need_longbranch)
44518ddd 10404 s += sprintf (s, ",$+8\n\tb %s", label);
12a4e8c5
GK		 10405 else
10406 s += sprintf (s, ",%s", label);
10407 }
10408
10409 return string;
10410}
50a0b056 10411
64022b5d 10412/* Return the string to flip the GT bit on a CR. */
423c1189 10413char *
64022b5d 10414output_e500_flip_gt_bit (rtx dst, rtx src)
423c1189
AH		 10415{
10416 static char string[64];
10417 int a, b;
10418
10419 if (GET_CODE (dst) != REG || ! CR_REGNO_P (REGNO (dst))
10420 || GET_CODE (src) != REG || ! CR_REGNO_P (REGNO (src)))
10421 abort ();
10422
64022b5d
AH		 10423 /* GT bit. */
10424 a = 4 * (REGNO (dst) - CR0_REGNO) + 1;
10425 b = 4 * (REGNO (src) - CR0_REGNO) + 1;
423c1189
AH		 10426
10427 sprintf (string, "crnot %d,%d", a, b);
10428 return string;
10429}
10430
21213b4c
DP		 10431/* Return insn index for the vector compare instruction for given CODE,
10432 and DEST_MODE, OP_MODE. Return INSN_NOT_AVAILABLE if valid insn is
10433 not available. */
10434
10435static int
94ff898d 10436get_vec_cmp_insn (enum rtx_code code,
21213b4c
DP		 10437 enum machine_mode dest_mode,
10438 enum machine_mode op_mode)
10439{
10440 if (!TARGET_ALTIVEC)
10441 return INSN_NOT_AVAILABLE;
10442
10443 switch (code)
10444 {
10445 case EQ:
10446 if (dest_mode == V16QImode && op_mode == V16QImode)
10447 return UNSPEC_VCMPEQUB;
10448 if (dest_mode == V8HImode && op_mode == V8HImode)
10449 return UNSPEC_VCMPEQUH;
10450 if (dest_mode == V4SImode && op_mode == V4SImode)
10451 return UNSPEC_VCMPEQUW;
10452 if (dest_mode == V4SImode && op_mode == V4SFmode)
10453 return UNSPEC_VCMPEQFP;
10454 break;
10455 case GE:
10456 if (dest_mode == V4SImode && op_mode == V4SFmode)
10457 return UNSPEC_VCMPGEFP;
10458 case GT:
10459 if (dest_mode == V16QImode && op_mode == V16QImode)
10460 return UNSPEC_VCMPGTSB;
10461 if (dest_mode == V8HImode && op_mode == V8HImode)
10462 return UNSPEC_VCMPGTSH;
10463 if (dest_mode == V4SImode && op_mode == V4SImode)
10464 return UNSPEC_VCMPGTSW;
10465 if (dest_mode == V4SImode && op_mode == V4SFmode)
10466 return UNSPEC_VCMPGTFP;
10467 break;
10468 case GTU:
10469 if (dest_mode == V16QImode && op_mode == V16QImode)
10470 return UNSPEC_VCMPGTUB;
10471 if (dest_mode == V8HImode && op_mode == V8HImode)
10472 return UNSPEC_VCMPGTUH;
10473 if (dest_mode == V4SImode && op_mode == V4SImode)
10474 return UNSPEC_VCMPGTUW;
10475 break;
10476 default:
10477 break;
10478 }
10479 return INSN_NOT_AVAILABLE;
10480}
10481
10482/* Emit vector compare for operands OP0 and OP1 using code RCODE.
10483 DMODE is expected destination mode. This is a recursive function. */
10484
10485static rtx
10486rs6000_emit_vector_compare (enum rtx_code rcode,
10487 rtx op0, rtx op1,
10488 enum machine_mode dmode)
10489{
10490 int vec_cmp_insn;
10491 rtx mask;
10492 enum machine_mode dest_mode;
10493 enum machine_mode op_mode = GET_MODE (op1);
10494
10495#ifdef ENABLE_CHECKING
10496 if (!TARGET_ALTIVEC)
10497 abort ();
10498
10499 if (GET_MODE (op0) != GET_MODE (op1))
10500 abort ();
10501#endif
10502
10503 /* Floating point vector compare instructions uses destination V4SImode.
10504 Move destination to appropriate mode later. */
10505 if (dmode == V4SFmode)
10506 dest_mode = V4SImode;
10507 else
10508 dest_mode = dmode;
10509
10510 mask = gen_reg_rtx (dest_mode);
10511 vec_cmp_insn = get_vec_cmp_insn (rcode, dest_mode, op_mode);
10512
10513 if (vec_cmp_insn == INSN_NOT_AVAILABLE)
10514 {
10515 bool swap_operands = false;
10516 bool try_again = false;
10517 switch (rcode)
10518 {
10519 case LT:
10520 rcode = GT;
10521 swap_operands = true;
10522 try_again = true;
10523 break;
10524 case LTU:
10525 rcode = GTU;
10526 swap_operands = true;
10527 try_again = true;
10528 break;
10529 case NE:
10530 /* Treat A != B as ~(A==B). */
10531 {
10532 enum insn_code nor_code;
10533 rtx eq_rtx = rs6000_emit_vector_compare (EQ, op0, op1,
10534 dest_mode);
94ff898d 10535
21213b4c
DP		 10536 nor_code = one_cmpl_optab->handlers[(int)dest_mode].insn_code;
10537 if (nor_code == CODE_FOR_nothing)
10538 abort ();
10539 emit_insn (GEN_FCN (nor_code) (mask, eq_rtx));
10540
10541 if (dmode != dest_mode)
10542 {
10543 rtx temp = gen_reg_rtx (dest_mode);
10544 convert_move (temp, mask, 0);
10545 return temp;
10546 }
10547 return mask;
10548 }
10549 break;
10550 case GE:
10551 case GEU:
10552 case LE:
10553 case LEU:
10554 /* Try GT/GTU/LT/LTU OR EQ */
10555 {
10556 rtx c_rtx, eq_rtx;
10557 enum insn_code ior_code;
10558 enum rtx_code new_code;
10559
10560 if (rcode == GE)
10561 new_code = GT;
10562 else if (rcode == GEU)
10563 new_code = GTU;
10564 else if (rcode == LE)
10565 new_code = LT;
10566 else if (rcode == LEU)
10567 new_code = LTU;
10568 else
10569 abort ();
10570
10571 c_rtx = rs6000_emit_vector_compare (new_code,
10572 op0, op1, dest_mode);
10573 eq_rtx = rs6000_emit_vector_compare (EQ, op0, op1,
10574 dest_mode);
10575
10576 ior_code = ior_optab->handlers[(int)dest_mode].insn_code;
10577 if (ior_code == CODE_FOR_nothing)
10578 abort ();
10579 emit_insn (GEN_FCN (ior_code) (mask, c_rtx, eq_rtx));
10580 if (dmode != dest_mode)
10581 {
10582 rtx temp = gen_reg_rtx (dest_mode);
10583 convert_move (temp, mask, 0);
10584 return temp;
10585 }
10586 return mask;
10587 }
10588 break;
10589 default:
10590 abort ();
10591 }
10592
10593 if (try_again)
10594 {
10595 vec_cmp_insn = get_vec_cmp_insn (rcode, dest_mode, op_mode);
10596 if (vec_cmp_insn == INSN_NOT_AVAILABLE)
10597 /* You only get two chances. */
10598 abort ();
10599 }
10600
10601 if (swap_operands)
10602 {
10603 rtx tmp;
10604 tmp = op0;
10605 op0 = op1;
10606 op1 = tmp;
10607 }
10608 }
10609
10610 emit_insn (gen_rtx_fmt_ee (SET,
10611 VOIDmode,
10612 mask,
10613 gen_rtx_fmt_Ei (UNSPEC, dest_mode,
10614 gen_rtvec (2, op0, op1),
10615 vec_cmp_insn)));
10616 if (dmode != dest_mode)
10617 {
10618 rtx temp = gen_reg_rtx (dest_mode);
10619 convert_move (temp, mask, 0);
10620 return temp;
10621 }
10622 return mask;
10623}
10624
10625/* Return vector select instruction for MODE. Return INSN_NOT_AVAILABLE, if
10626 valid insn doesn exist for given mode. */
10627
10628static int
10629get_vsel_insn (enum machine_mode mode)
10630{
10631 switch (mode)
10632 {
10633 case V4SImode:
10634 return UNSPEC_VSEL4SI;
10635 break;
10636 case V4SFmode:
10637 return UNSPEC_VSEL4SF;
10638 break;
10639 case V8HImode:
10640 return UNSPEC_VSEL8HI;
10641 break;
10642 case V16QImode:
10643 return UNSPEC_VSEL16QI;
10644 break;
10645 default:
10646 return INSN_NOT_AVAILABLE;
10647 break;
10648 }
10649 return INSN_NOT_AVAILABLE;
10650}
10651
10652/* Emit vector select insn where DEST is destination using
10653 operands OP1, OP2 and MASK. */
10654
10655static void
10656rs6000_emit_vector_select (rtx dest, rtx op1, rtx op2, rtx mask)
10657{
10658 rtx t, temp;
10659 enum machine_mode dest_mode = GET_MODE (dest);
10660 int vsel_insn_index = get_vsel_insn (GET_MODE (dest));
10661
10662 temp = gen_reg_rtx (dest_mode);
94ff898d 10663
21213b4c
DP		 10664 t = gen_rtx_fmt_ee (SET, VOIDmode, temp,
10665 gen_rtx_fmt_Ei (UNSPEC, dest_mode,
10666 gen_rtvec (3, op1, op2, mask),
10667 vsel_insn_index));
10668 emit_insn (t);
10669 emit_move_insn (dest, temp);
10670 return;
10671}
10672
94ff898d 10673/* Emit vector conditional expression.
21213b4c
DP		 10674 DEST is destination. OP1 and OP2 are two VEC_COND_EXPR operands.
10675 CC_OP0 and CC_OP1 are the two operands for the relation operation COND. */
10676
10677int
10678rs6000_emit_vector_cond_expr (rtx dest, rtx op1, rtx op2,
10679 rtx cond, rtx cc_op0, rtx cc_op1)
10680{
10681 enum machine_mode dest_mode = GET_MODE (dest);
10682 enum rtx_code rcode = GET_CODE (cond);
10683 rtx mask;
10684
10685 if (!TARGET_ALTIVEC)
10686 return 0;
10687
10688 /* Get the vector mask for the given relational operations. */
10689 mask = rs6000_emit_vector_compare (rcode, cc_op0, cc_op1, dest_mode);
10690
10691 rs6000_emit_vector_select (dest, op1, op2, mask);
10692
10693 return 1;
10694}
10695
50a0b056
GK		 10696/* Emit a conditional move: move TRUE_COND to DEST if OP of the
10697 operands of the last comparison is nonzero/true, FALSE_COND if it
10698 is zero/false. Return 0 if the hardware has no such operation. */
a4f6c312 10699
50a0b056 10700int
a2369ed3 10701rs6000_emit_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond)
50a0b056
GK		 10702{
10703 enum rtx_code code = GET_CODE (op);
10704 rtx op0 = rs6000_compare_op0;
10705 rtx op1 = rs6000_compare_op1;
10706 REAL_VALUE_TYPE c1;
3148ad6d
DJ		 10707 enum machine_mode compare_mode = GET_MODE (op0);
10708 enum machine_mode result_mode = GET_MODE (dest);
50a0b056 10709 rtx temp;
add2402e 10710 bool is_against_zero;
50a0b056 10711
a3c9585f 10712 /* These modes should always match. */
a3170dc6
AH		 10713 if (GET_MODE (op1) != compare_mode
10714 /* In the isel case however, we can use a compare immediate, so
10715 op1 may be a small constant. */
10716 && (!TARGET_ISEL || !short_cint_operand (op1, VOIDmode)))
3148ad6d 10717 return 0;
178c3eff 10718 if (GET_MODE (true_cond) != result_mode)
3148ad6d 10719 return 0;
178c3eff 10720 if (GET_MODE (false_cond) != result_mode)
3148ad6d
DJ		 10721 return 0;
10722
50a0b056 10723 /* First, work out if the hardware can do this at all, or
a3c9585f 10724 if it's too slow.... */
50a0b056 10725 if (! rs6000_compare_fp_p)
a3170dc6
AH		 10726 {
10727 if (TARGET_ISEL)
10728 return rs6000_emit_int_cmove (dest, op, true_cond, false_cond);
10729 return 0;
10730 }
fef98bf2
AH		 10731 else if (TARGET_E500 && TARGET_HARD_FLOAT && !TARGET_FPRS
10732 && GET_MODE_CLASS (compare_mode) == MODE_FLOAT)
10733 return 0;
50a0b056 10734
add2402e 10735 is_against_zero = op1 == CONST0_RTX (compare_mode);
94ff898d 10736
add2402e
GK		 10737 /* A floating-point subtract might overflow, underflow, or produce
10738 an inexact result, thus changing the floating-point flags, so it
10739 can't be generated if we care about that. It's safe if one side
10740 of the construct is zero, since then no subtract will be
10741 generated. */
10742 if (GET_MODE_CLASS (compare_mode) == MODE_FLOAT
10743 && flag_trapping_math && ! is_against_zero)
10744 return 0;
10745
50a0b056
GK		 10746 /* Eliminate half of the comparisons by switching operands, this
10747 makes the remaining code simpler. */
10748 if (code == UNLT || code == UNGT || code == UNORDERED || code == NE
bc9ec0e0 10749 || code == LTGT || code == LT || code == UNLE)
50a0b056
GK		 10750 {
10751 code = reverse_condition_maybe_unordered (code);
10752 temp = true_cond;
10753 true_cond = false_cond;
10754 false_cond = temp;
10755 }
10756
10757 /* UNEQ and LTGT take four instructions for a comparison with zero,
10758 it'll probably be faster to use a branch here too. */
bc9ec0e0 10759 if (code == UNEQ && HONOR_NANS (compare_mode))
50a0b056 10760 return 0;
f676971a 10761
50a0b056
GK		 10762 if (GET_CODE (op1) == CONST_DOUBLE)
10763 REAL_VALUE_FROM_CONST_DOUBLE (c1, op1);
f676971a 10764
b6d08ca1 10765 /* We're going to try to implement comparisons by performing
50a0b056
GK		 10766 a subtract, then comparing against zero. Unfortunately,
10767 Inf - Inf is NaN which is not zero, and so if we don't
27d30956 10768 know that the operand is finite and the comparison
50a0b056 10769 would treat EQ different to UNORDERED, we can't do it. */
bc9ec0e0 10770 if (HONOR_INFINITIES (compare_mode)
50a0b056 10771 && code != GT && code != UNGE
045572c7 10772 && (GET_CODE (op1) != CONST_DOUBLE || real_isinf (&c1))
50a0b056
GK		 10773 /* Constructs of the form (a OP b ? a : b) are safe. */
10774 && ((! rtx_equal_p (op0, false_cond) && ! rtx_equal_p (op1, false_cond))
f676971a 10775 || (! rtx_equal_p (op0, true_cond)
50a0b056
GK		 10776 && ! rtx_equal_p (op1, true_cond))))
10777 return 0;
add2402e 10778
50a0b056
GK		 10779 /* At this point we know we can use fsel. */
10780
10781 /* Reduce the comparison to a comparison against zero. */
add2402e
GK		 10782 if (! is_against_zero)
10783 {
10784 temp = gen_reg_rtx (compare_mode);
10785 emit_insn (gen_rtx_SET (VOIDmode, temp,
10786 gen_rtx_MINUS (compare_mode, op0, op1)));
10787 op0 = temp;
10788 op1 = CONST0_RTX (compare_mode);
10789 }
50a0b056
GK		 10790
10791 /* If we don't care about NaNs we can reduce some of the comparisons
10792 down to faster ones. */
bc9ec0e0 10793 if (! HONOR_NANS (compare_mode))
50a0b056
GK		 10794 switch (code)
10795 {
10796 case GT:
10797 code = LE;
10798 temp = true_cond;
10799 true_cond = false_cond;
10800 false_cond = temp;
10801 break;
10802 case UNGE:
10803 code = GE;
10804 break;
10805 case UNEQ:
10806 code = EQ;
10807 break;
10808 default:
10809 break;
10810 }
10811
10812 /* Now, reduce everything down to a GE. */
10813 switch (code)
10814 {
10815 case GE:
10816 break;
10817
10818 case LE:
3148ad6d
DJ		 10819 temp = gen_reg_rtx (compare_mode);
10820 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
50a0b056
GK		 10821 op0 = temp;
10822 break;
10823
10824 case ORDERED:
3148ad6d
DJ		 10825 temp = gen_reg_rtx (compare_mode);
10826 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_ABS (compare_mode, op0)));
50a0b056
GK		 10827 op0 = temp;
10828 break;
10829
10830 case EQ:
3148ad6d 10831 temp = gen_reg_rtx (compare_mode);
f676971a 10832 emit_insn (gen_rtx_SET (VOIDmode, temp,
3148ad6d
DJ		 10833 gen_rtx_NEG (compare_mode,
10834 gen_rtx_ABS (compare_mode, op0))));
50a0b056
GK		 10835 op0 = temp;
10836 break;
10837
10838 case UNGE:
bc9ec0e0 10839 /* a UNGE 0 <-> (a GE 0 || -a UNLT 0) */
3148ad6d 10840 temp = gen_reg_rtx (result_mode);
50a0b056 10841 emit_insn (gen_rtx_SET (VOIDmode, temp,
3148ad6d 10842 gen_rtx_IF_THEN_ELSE (result_mode,
50a0b056
GK		 10843 gen_rtx_GE (VOIDmode,
10844 op0, op1),
10845 true_cond, false_cond)));
bc9ec0e0
GK		 10846 false_cond = true_cond;
10847 true_cond = temp;
50a0b056 10848
3148ad6d
DJ		 10849 temp = gen_reg_rtx (compare_mode);
10850 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
50a0b056
GK		 10851 op0 = temp;
10852 break;
10853
10854 case GT:
bc9ec0e0 10855 /* a GT 0 <-> (a GE 0 && -a UNLT 0) */
3148ad6d 10856 temp = gen_reg_rtx (result_mode);
50a0b056 10857 emit_insn (gen_rtx_SET (VOIDmode, temp,
f676971a 10858 gen_rtx_IF_THEN_ELSE (result_mode,
50a0b056
GK		 10859 gen_rtx_GE (VOIDmode,
10860 op0, op1),
10861 true_cond, false_cond)));
bc9ec0e0
GK		 10862 true_cond = false_cond;
10863 false_cond = temp;
50a0b056 10864
3148ad6d
DJ		 10865 temp = gen_reg_rtx (compare_mode);
10866 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
50a0b056
GK		 10867 op0 = temp;
10868 break;
10869
10870 default:
10871 abort ();
10872 }
10873
10874 emit_insn (gen_rtx_SET (VOIDmode, dest,
3148ad6d 10875 gen_rtx_IF_THEN_ELSE (result_mode,
50a0b056
GK		 10876 gen_rtx_GE (VOIDmode,
10877 op0, op1),
10878 true_cond, false_cond)));
10879 return 1;
10880}
10881
a3170dc6
AH		 10882/* Same as above, but for ints (isel). */
10883
10884static int
a2369ed3 10885rs6000_emit_int_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond)
a3170dc6
AH		 10886{
10887 rtx condition_rtx, cr;
10888
10889 /* All isel implementations thus far are 32-bits. */
10890 if (GET_MODE (rs6000_compare_op0) != SImode)
10891 return 0;
10892
10893 /* We still have to do the compare, because isel doesn't do a
10894 compare, it just looks at the CRx bits set by a previous compare
10895 instruction. */
10896 condition_rtx = rs6000_generate_compare (GET_CODE (op));
10897 cr = XEXP (condition_rtx, 0);
10898
10899 if (GET_MODE (cr) == CCmode)
10900 emit_insn (gen_isel_signed (dest, condition_rtx,
10901 true_cond, false_cond, cr));
10902 else
10903 emit_insn (gen_isel_unsigned (dest, condition_rtx,
10904 true_cond, false_cond, cr));
10905
10906 return 1;
10907}
10908
10909const char *
a2369ed3 10910output_isel (rtx *operands)
a3170dc6
AH		 10911{
10912 enum rtx_code code;
10913
10914 code = GET_CODE (operands[1]);
10915 if (code == GE || code == GEU || code == LE || code == LEU || code == NE)
10916 {
10917 PUT_CODE (operands[1], reverse_condition (code));
10918 return "isel %0,%3,%2,%j1";
10919 }
10920 else
10921 return "isel %0,%2,%3,%j1";
10922}
10923
50a0b056 10924void
a2369ed3 10925rs6000_emit_minmax (rtx dest, enum rtx_code code, rtx op0, rtx op1)
50a0b056
GK		 10926{
10927 enum machine_mode mode = GET_MODE (op0);
5dc8d536 10928 enum rtx_code c;
50a0b056 10929 rtx target;
5dc8d536
AH		 10930
10931 if (code == SMAX || code == SMIN)
10932 c = GE;
10933 else
10934 c = GEU;
10935
50a0b056 10936 if (code == SMAX || code == UMAX)
f676971a 10937 target = emit_conditional_move (dest, c, op0, op1, mode,
50a0b056
GK		 10938 op0, op1, mode, 0);
10939 else
f676971a 10940 target = emit_conditional_move (dest, c, op0, op1, mode,
50a0b056
GK		 10941 op1, op0, mode, 0);
10942 if (target == NULL_RTX)
10943 abort ();
10944 if (target != dest)
10945 emit_move_insn (dest, target);
10946}
46c07df8 10947
a9baceb1
GK		 10948/* Emit instructions to move SRC to DST. Called by splitters for
10949 multi-register moves. It will emit at most one instruction for
10950 each register that is accessed; that is, it won't emit li/lis pairs
10951 (or equivalent for 64-bit code). One of SRC or DST must be a hard
10952 register. */
46c07df8 10953
46c07df8 10954void
a9baceb1 10955rs6000_split_multireg_move (rtx dst, rtx src)
46c07df8 10956{
a9baceb1
GK		 10957 /* The register number of the first register being moved. */
10958 int reg;
10959 /* The mode that is to be moved. */
10960 enum machine_mode mode;
10961 /* The mode that the move is being done in, and its size. */
10962 enum machine_mode reg_mode;
10963 int reg_mode_size;
10964 /* The number of registers that will be moved. */
10965 int nregs;
10966
10967 reg = REG_P (dst) ? REGNO (dst) : REGNO (src);
10968 mode = GET_MODE (dst);
10969 nregs = HARD_REGNO_NREGS (reg, mode);
10970 if (FP_REGNO_P (reg))
10971 reg_mode = DFmode;
10972 else if (ALTIVEC_REGNO_P (reg))
10973 reg_mode = V16QImode;
10974 else
10975 reg_mode = word_mode;
10976 reg_mode_size = GET_MODE_SIZE (reg_mode);
f676971a 10977
a9baceb1
GK		 10978 if (reg_mode_size * nregs != GET_MODE_SIZE (mode))
10979 abort ();
f676971a 10980
a9baceb1
GK		 10981 if (REG_P (src) && REG_P (dst) && (REGNO (src) < REGNO (dst)))
10982 {
10983 /* Move register range backwards, if we might have destructive
10984 overlap. */
10985 int i;
10986 for (i = nregs - 1; i >= 0; i--)
f676971a 10987 emit_insn (gen_rtx_SET (VOIDmode,
a9baceb1
GK		 10988 simplify_gen_subreg (reg_mode, dst, mode,
10989 i * reg_mode_size),
10990 simplify_gen_subreg (reg_mode, src, mode,
10991 i * reg_mode_size)));
10992 }
46c07df8
HP		 10993 else
10994 {
a9baceb1
GK		 10995 int i;
10996 int j = -1;
10997 bool used_update = false;
46c07df8 10998
c1e55850 10999 if (MEM_P (src) && INT_REGNO_P (reg))
c4ad648e
AM		 11000 {
11001 rtx breg;
3a1f863f 11002
a9baceb1
GK		 11003 if (GET_CODE (XEXP (src, 0)) == PRE_INC
11004 || GET_CODE (XEXP (src, 0)) == PRE_DEC)
3a1f863f
DE		 11005 {
11006 rtx delta_rtx;
a9baceb1 11007 breg = XEXP (XEXP (src, 0), 0);
c4ad648e
AM		 11008 delta_rtx = (GET_CODE (XEXP (src, 0)) == PRE_INC
11009 ? GEN_INT (GET_MODE_SIZE (GET_MODE (src)))
11010 : GEN_INT (-GET_MODE_SIZE (GET_MODE (src))));
a9baceb1
GK		 11011 emit_insn (TARGET_32BIT
11012 ? gen_addsi3 (breg, breg, delta_rtx)
11013 : gen_adddi3 (breg, breg, delta_rtx));
3a1f863f
DE		 11014 src = gen_rtx_MEM (mode, breg);
11015 }
c1e55850
GK		 11016 else if (! offsettable_memref_p (src))
11017 {
11018 rtx newsrc, basereg;
11019 basereg = gen_rtx_REG (Pmode, reg);
11020 emit_insn (gen_rtx_SET (VOIDmode, basereg, XEXP (src, 0)));
11021 newsrc = gen_rtx_MEM (GET_MODE (src), basereg);
11022 MEM_COPY_ATTRIBUTES (newsrc, src);
11023 src = newsrc;
11024 }
3a1f863f 11025
0423421f
AM		 11026 breg = XEXP (src, 0);
11027 if (GET_CODE (breg) == PLUS || GET_CODE (breg) == LO_SUM)
11028 breg = XEXP (breg, 0);
11029
11030 /* If the base register we are using to address memory is
11031 also a destination reg, then change that register last. */
11032 if (REG_P (breg)
11033 && REGNO (breg) >= REGNO (dst)
3a1f863f
DE		 11034 && REGNO (breg) < REGNO (dst) + nregs)
11035 j = REGNO (breg) - REGNO (dst);
c4ad648e 11036 }
46c07df8 11037
a9baceb1 11038 if (GET_CODE (dst) == MEM && INT_REGNO_P (reg))
3a1f863f
DE		 11039 {
11040 rtx breg;
11041
a9baceb1
GK		 11042 if (GET_CODE (XEXP (dst, 0)) == PRE_INC
11043 || GET_CODE (XEXP (dst, 0)) == PRE_DEC)
3a1f863f
DE		 11044 {
11045 rtx delta_rtx;
a9baceb1 11046 breg = XEXP (XEXP (dst, 0), 0);
c4ad648e
AM		 11047 delta_rtx = (GET_CODE (XEXP (dst, 0)) == PRE_INC
11048 ? GEN_INT (GET_MODE_SIZE (GET_MODE (dst)))
11049 : GEN_INT (-GET_MODE_SIZE (GET_MODE (dst))));
3a1f863f
DE		 11050
11051 /* We have to update the breg before doing the store.
11052 Use store with update, if available. */
11053
11054 if (TARGET_UPDATE)
11055 {
a9baceb1 11056 rtx nsrc = simplify_gen_subreg (reg_mode, src, mode, 0);
c4ad648e
AM		 11057 emit_insn (TARGET_32BIT
11058 ? (TARGET_POWERPC64
11059 ? gen_movdi_si_update (breg, breg, delta_rtx, nsrc)
11060 : gen_movsi_update (breg, breg, delta_rtx, nsrc))
11061 : gen_movdi_di_update (breg, breg, delta_rtx, nsrc));
a9baceb1 11062 used_update = true;
3a1f863f
DE		 11063 }
11064 else
a9baceb1
GK		 11065 emit_insn (TARGET_32BIT
11066 ? gen_addsi3 (breg, breg, delta_rtx)
11067 : gen_adddi3 (breg, breg, delta_rtx));
3a1f863f
DE		 11068 dst = gen_rtx_MEM (mode, breg);
11069 }
c1e55850 11070 else if (! offsettable_memref_p (dst))
112ccb83 11071 abort ();
3a1f863f
DE		 11072 }
11073
46c07df8 11074 for (i = 0; i < nregs; i++)
f676971a 11075 {
3a1f863f
DE		 11076 /* Calculate index to next subword. */
11077 ++j;
f676971a 11078 if (j == nregs)
3a1f863f 11079 j = 0;
46c07df8 11080
112cdef5 11081 /* If compiler already emitted move of first word by
a9baceb1 11082 store with update, no need to do anything. */
3a1f863f 11083 if (j == 0 && used_update)
a9baceb1 11084 continue;
f676971a 11085
a9baceb1
GK		 11086 emit_insn (gen_rtx_SET (VOIDmode,
11087 simplify_gen_subreg (reg_mode, dst, mode,
11088 j * reg_mode_size),
11089 simplify_gen_subreg (reg_mode, src, mode,
11090 j * reg_mode_size)));
3a1f863f 11091 }
46c07df8
HP		 11092 }
11093}
11094
12a4e8c5 11095\f
a4f6c312
SS		 11096/* This page contains routines that are used to determine what the
11097 function prologue and epilogue code will do and write them out. */
9878760c 11098
a4f6c312
SS		 11099/* Return the first fixed-point register that is required to be
11100 saved. 32 if none. */
9878760c
RK		 11101
11102int
863d938c 11103first_reg_to_save (void)
9878760c
RK		 11104{
11105 int first_reg;
11106
11107 /* Find lowest numbered live register. */
11108 for (first_reg = 13; first_reg <= 31; first_reg++)
f676971a 11109 if (regs_ever_live[first_reg]
a38d360d 11110 && (! call_used_regs[first_reg]
1db02437 11111 || (first_reg == RS6000_PIC_OFFSET_TABLE_REGNUM
14f00213 11112 && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0)
b4db40bf
JJ		 11113 || (DEFAULT_ABI == ABI_DARWIN && flag_pic)
11114 || (TARGET_TOC && TARGET_MINIMAL_TOC)))))
9878760c
RK		 11115 break;
11116
ee890fe2 11117#if TARGET_MACHO
93638d7a
AM		 11118 if (flag_pic
11119 && current_function_uses_pic_offset_table
11120 && first_reg > RS6000_PIC_OFFSET_TABLE_REGNUM)
1db02437 11121 return RS6000_PIC_OFFSET_TABLE_REGNUM;
ee890fe2
SS		 11122#endif
11123
9878760c
RK		 11124 return first_reg;
11125}
11126
11127/* Similar, for FP regs. */
11128
11129int
863d938c 11130first_fp_reg_to_save (void)
9878760c
RK		 11131{
11132 int first_reg;
11133
11134 /* Find lowest numbered live register. */
11135 for (first_reg = 14 + 32; first_reg <= 63; first_reg++)
11136 if (regs_ever_live[first_reg])
11137 break;
11138
11139 return first_reg;
11140}
00b960c7
AH		 11141
11142/* Similar, for AltiVec regs. */
11143
11144static int
863d938c 11145first_altivec_reg_to_save (void)
00b960c7
AH		 11146{
11147 int i;
11148
11149 /* Stack frame remains as is unless we are in AltiVec ABI. */
11150 if (! TARGET_ALTIVEC_ABI)
11151 return LAST_ALTIVEC_REGNO + 1;
11152
11153 /* Find lowest numbered live register. */
11154 for (i = FIRST_ALTIVEC_REGNO + 20; i <= LAST_ALTIVEC_REGNO; ++i)
11155 if (regs_ever_live[i])
11156 break;
11157
11158 return i;
11159}
11160
11161/* Return a 32-bit mask of the AltiVec registers we need to set in
11162 VRSAVE. Bit n of the return value is 1 if Vn is live. The MSB in
11163 the 32-bit word is 0. */
11164
11165static unsigned int
863d938c 11166compute_vrsave_mask (void)
00b960c7
AH		 11167{
11168 unsigned int i, mask = 0;
11169
11170 /* First, find out if we use _any_ altivec registers. */
11171 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
11172 if (regs_ever_live[i])
11173 mask |= ALTIVEC_REG_BIT (i);
11174
11175 if (mask == 0)
11176 return mask;
11177
00b960c7
AH		 11178 /* Next, remove the argument registers from the set. These must
11179 be in the VRSAVE mask set by the caller, so we don't need to add
11180 them in again. More importantly, the mask we compute here is
11181 used to generate CLOBBERs in the set_vrsave insn, and we do not
11182 wish the argument registers to die. */
a6cf80f2 11183 for (i = cfun->args_info.vregno - 1; i >= ALTIVEC_ARG_MIN_REG; --i)
00b960c7
AH		 11184 mask &= ~ALTIVEC_REG_BIT (i);
11185
11186 /* Similarly, remove the return value from the set. */
11187 {
11188 bool yes = false;
11189 diddle_return_value (is_altivec_return_reg, &yes);
11190 if (yes)
11191 mask &= ~ALTIVEC_REG_BIT (ALTIVEC_ARG_RETURN);
11192 }
11193
11194 return mask;
11195}
11196
d62294f5 11197/* For a very restricted set of circumstances, we can cut down the
f57fe068
AM		 11198 size of prologues/epilogues by calling our own save/restore-the-world
11199 routines. */
d62294f5
FJ		 11200
11201static void
f57fe068
AM		 11202compute_save_world_info (rs6000_stack_t *info_ptr)
11203{
11204 info_ptr->world_save_p = 1;
11205 info_ptr->world_save_p
11206 = (WORLD_SAVE_P (info_ptr)
11207 && DEFAULT_ABI == ABI_DARWIN
11208 && ! (current_function_calls_setjmp && flag_exceptions)
11209 && info_ptr->first_fp_reg_save == FIRST_SAVED_FP_REGNO
11210 && info_ptr->first_gp_reg_save == FIRST_SAVED_GP_REGNO
11211 && info_ptr->first_altivec_reg_save == FIRST_SAVED_ALTIVEC_REGNO
11212 && info_ptr->cr_save_p);
f676971a 11213
d62294f5
FJ		 11214 /* This will not work in conjunction with sibcalls. Make sure there
11215 are none. (This check is expensive, but seldom executed.) */
f57fe068 11216 if (WORLD_SAVE_P (info_ptr))
f676971a 11217 {
d62294f5
FJ		 11218 rtx insn;
11219 for ( insn = get_last_insn_anywhere (); insn; insn = PREV_INSN (insn))
c4ad648e
AM		 11220 if ( GET_CODE (insn) == CALL_INSN
11221 && SIBLING_CALL_P (insn))
11222 {
11223 info_ptr->world_save_p = 0;
11224 break;
11225 }
d62294f5 11226 }
f676971a 11227
f57fe068 11228 if (WORLD_SAVE_P (info_ptr))
d62294f5
FJ		 11229 {
11230 /* Even if we're not touching VRsave, make sure there's room on the
11231 stack for it, if it looks like we're calling SAVE_WORLD, which
c4ad648e 11232 will attempt to save it. */
d62294f5
FJ		 11233 info_ptr->vrsave_size = 4;
11234
11235 /* "Save" the VRsave register too if we're saving the world. */
11236 if (info_ptr->vrsave_mask == 0)
c4ad648e 11237 info_ptr->vrsave_mask = compute_vrsave_mask ();
d62294f5
FJ		 11238
11239 /* Because the Darwin register save/restore routines only handle
c4ad648e
AM		 11240 F14 .. F31 and V20 .. V31 as per the ABI, perform a consistency
11241 check and abort if there's something worng. */
f676971a 11242 if (info_ptr->first_fp_reg_save < FIRST_SAVED_FP_REGNO
c4ad648e
AM		 11243 || info_ptr->first_altivec_reg_save < FIRST_SAVED_ALTIVEC_REGNO)
11244 abort ();
d62294f5 11245 }
f676971a 11246 return;
d62294f5
FJ		 11247}
11248
11249
00b960c7 11250static void
a2369ed3 11251is_altivec_return_reg (rtx reg, void *xyes)
00b960c7
AH		 11252{
11253 bool *yes = (bool *) xyes;
11254 if (REGNO (reg) == ALTIVEC_ARG_RETURN)
11255 *yes = true;
11256}
11257
4697a36c
MM		 11258\f
11259/* Calculate the stack information for the current function. This is
11260 complicated by having two separate calling sequences, the AIX calling
11261 sequence and the V.4 calling sequence.
11262
592696dd 11263 AIX (and Darwin/Mac OS X) stack frames look like:
a260abc9 11264 32-bit 64-bit
4697a36c 11265 SP----> +---------------------------------------+
a260abc9 11266 | back chain to caller | 0 0
4697a36c 11267 +---------------------------------------+
a260abc9 11268 | saved CR | 4 8 (8-11)
4697a36c 11269 +---------------------------------------+
a260abc9 11270 | saved LR | 8 16
4697a36c 11271 +---------------------------------------+
a260abc9 11272 | reserved for compilers | 12 24
4697a36c 11273 +---------------------------------------+
a260abc9 11274 | reserved for binders | 16 32
4697a36c 11275 +---------------------------------------+
a260abc9 11276 | saved TOC pointer | 20 40
4697a36c 11277 +---------------------------------------+
a260abc9 11278 | Parameter save area (P) | 24 48
4697a36c 11279 +---------------------------------------+
a260abc9 11280 | Alloca space (A) | 24+P etc.
802a0058 11281 +---------------------------------------+
a7df97e6 11282 | Local variable space (L) | 24+P+A
4697a36c 11283 +---------------------------------------+
a7df97e6 11284 | Float/int conversion temporary (X) | 24+P+A+L
4697a36c 11285 +---------------------------------------+
00b960c7
AH		 11286 | Save area for AltiVec registers (W) | 24+P+A+L+X
11287 +---------------------------------------+
11288 | AltiVec alignment padding (Y) | 24+P+A+L+X+W
11289 +---------------------------------------+
11290 | Save area for VRSAVE register (Z) | 24+P+A+L+X+W+Y
4697a36c 11291 +---------------------------------------+
00b960c7
AH		 11292 | Save area for GP registers (G) | 24+P+A+X+L+X+W+Y+Z
11293 +---------------------------------------+
11294 | Save area for FP registers (F) | 24+P+A+X+L+X+W+Y+Z+G
4697a36c
MM		 11295 +---------------------------------------+
11296 old SP->| back chain to caller's caller |
11297 +---------------------------------------+
11298
5376a30c
KR		 11299 The required alignment for AIX configurations is two words (i.e., 8
11300 or 16 bytes).
11301
11302
4697a36c
MM		 11303 V.4 stack frames look like:
11304
11305 SP----> +---------------------------------------+
11306 | back chain to caller | 0
11307 +---------------------------------------+
5eb387b8 11308 | caller's saved LR | 4
4697a36c
MM		 11309 +---------------------------------------+
11310 | Parameter save area (P) | 8
11311 +---------------------------------------+
a7df97e6 11312 | Alloca space (A) | 8+P
f676971a 11313 +---------------------------------------+
a7df97e6 11314 | Varargs save area (V) | 8+P+A
f676971a 11315 +---------------------------------------+
a7df97e6 11316 | Local variable space (L) | 8+P+A+V
f676971a 11317 +---------------------------------------+
a7df97e6 11318 | Float/int conversion temporary (X) | 8+P+A+V+L
4697a36c 11319 +---------------------------------------+
00b960c7
AH		 11320 | Save area for AltiVec registers (W) | 8+P+A+V+L+X
11321 +---------------------------------------+
11322 | AltiVec alignment padding (Y) | 8+P+A+V+L+X+W
11323 +---------------------------------------+
11324 | Save area for VRSAVE register (Z) | 8+P+A+V+L+X+W+Y
11325 +---------------------------------------+
c4ad648e
AM		 11326 | SPE: area for 64-bit GP registers |
11327 +---------------------------------------+
11328 | SPE alignment padding |
11329 +---------------------------------------+
00b960c7 11330 | saved CR (C) | 8+P+A+V+L+X+W+Y+Z
f676971a 11331 +---------------------------------------+
00b960c7 11332 | Save area for GP registers (G) | 8+P+A+V+L+X+W+Y+Z+C
f676971a 11333 +---------------------------------------+
00b960c7 11334 | Save area for FP registers (F) | 8+P+A+V+L+X+W+Y+Z+C+G
4697a36c
MM		 11335 +---------------------------------------+
11336 old SP->| back chain to caller's caller |
11337 +---------------------------------------+
b6c9286a 11338
5376a30c
KR		 11339 The required alignment for V.4 is 16 bytes, or 8 bytes if -meabi is
11340 given. (But note below and in sysv4.h that we require only 8 and
11341 may round up the size of our stack frame anyways. The historical
11342 reason is early versions of powerpc-linux which didn't properly
11343 align the stack at program startup. A happy side-effect is that
11344 -mno-eabi libraries can be used with -meabi programs.)
11345
50d440bc 11346 The EABI configuration defaults to the V.4 layout. However,
5376a30c
KR		 11347 the stack alignment requirements may differ. If -mno-eabi is not
11348 given, the required stack alignment is 8 bytes; if -mno-eabi is
11349 given, the required alignment is 16 bytes. (But see V.4 comment
11350 above.) */
4697a36c 11351
61b2fbe7
MM		 11352#ifndef ABI_STACK_BOUNDARY
11353#define ABI_STACK_BOUNDARY STACK_BOUNDARY
11354#endif
11355
d1d0c603 11356static rs6000_stack_t *
863d938c 11357rs6000_stack_info (void)
4697a36c
MM		 11358{
11359 static rs6000_stack_t info, zero_info;
11360 rs6000_stack_t *info_ptr = &info;
327e5343 11361 int reg_size = TARGET_32BIT ? 4 : 8;
83720594 11362 int ehrd_size;
64045029 11363 int save_align;
44688022 11364 HOST_WIDE_INT non_fixed_size;
4697a36c 11365
a4f6c312 11366 /* Zero all fields portably. */
4697a36c
MM		 11367 info = zero_info;
11368
c19de7aa
AH		 11369 if (TARGET_SPE)
11370 {
11371 /* Cache value so we don't rescan instruction chain over and over. */
9b7b447f 11372 if (cfun->machine->insn_chain_scanned_p == 0)
b5a5beb9
AH		 11373 cfun->machine->insn_chain_scanned_p
11374 = spe_func_has_64bit_regs_p () + 1;
11375 info_ptr->spe_64bit_regs_used = cfun->machine->insn_chain_scanned_p - 1;
c19de7aa
AH		 11376 }
11377
a4f6c312 11378 /* Select which calling sequence. */
178274da 11379 info_ptr->abi = DEFAULT_ABI;
9878760c 11380
a4f6c312 11381 /* Calculate which registers need to be saved & save area size. */
4697a36c 11382 info_ptr->first_gp_reg_save = first_reg_to_save ();
f676971a 11383 /* Assume that we will have to save RS6000_PIC_OFFSET_TABLE_REGNUM,
906fb125 11384 even if it currently looks like we won't. */
2bfcf297 11385 if (((TARGET_TOC && TARGET_MINIMAL_TOC)
178274da
AM		 11386 || (flag_pic == 1 && DEFAULT_ABI == ABI_V4)
11387 || (flag_pic && DEFAULT_ABI == ABI_DARWIN))
1db02437
FS		 11388 && info_ptr->first_gp_reg_save > RS6000_PIC_OFFSET_TABLE_REGNUM)
11389 info_ptr->gp_size = reg_size * (32 - RS6000_PIC_OFFSET_TABLE_REGNUM);
906fb125
GK		 11390 else
11391 info_ptr->gp_size = reg_size * (32 - info_ptr->first_gp_reg_save);
4697a36c 11392
a3170dc6
AH		 11393 /* For the SPE, we have an additional upper 32-bits on each GPR.
11394 Ideally we should save the entire 64-bits only when the upper
11395 half is used in SIMD instructions. Since we only record
11396 registers live (not the size they are used in), this proves
11397 difficult because we'd have to traverse the instruction chain at
11398 the right time, taking reload into account. This is a real pain,
c19de7aa
AH		 11399 so we opt to save the GPRs in 64-bits always if but one register
11400 gets used in 64-bits. Otherwise, all the registers in the frame
11401 get saved in 32-bits.
a3170dc6 11402
c19de7aa 11403 So... since when we save all GPRs (except the SP) in 64-bits, the
a3170dc6 11404 traditional GP save area will be empty. */
c19de7aa 11405 if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
a3170dc6
AH		 11406 info_ptr->gp_size = 0;
11407
4697a36c
MM		 11408 info_ptr->first_fp_reg_save = first_fp_reg_to_save ();
11409 info_ptr->fp_size = 8 * (64 - info_ptr->first_fp_reg_save);
11410
00b960c7
AH		 11411 info_ptr->first_altivec_reg_save = first_altivec_reg_to_save ();
11412 info_ptr->altivec_size = 16 * (LAST_ALTIVEC_REGNO + 1
11413 - info_ptr->first_altivec_reg_save);
11414
592696dd 11415 /* Does this function call anything? */
71f123ca
FS		 11416 info_ptr->calls_p = (! current_function_is_leaf
11417 || cfun->machine->ra_needs_full_frame);
b6c9286a 11418
a4f6c312 11419 /* Determine if we need to save the link register. */
71f123ca 11420 if (rs6000_ra_ever_killed ()
ffcfcb5f
AM		 11421 || (DEFAULT_ABI == ABI_AIX
11422 && current_function_profile
11423 && !TARGET_PROFILE_KERNEL)
4697a36c
MM		 11424#ifdef TARGET_RELOCATABLE
11425 || (TARGET_RELOCATABLE && (get_pool_size () != 0))
11426#endif
11427 || (info_ptr->first_fp_reg_save != 64
11428 && !FP_SAVE_INLINE (info_ptr->first_fp_reg_save))
00b960c7 11429 || info_ptr->first_altivec_reg_save <= LAST_ALTIVEC_REGNO
178274da 11430 || (DEFAULT_ABI == ABI_V4 && current_function_calls_alloca)
a4f6c312
SS		 11431 || (DEFAULT_ABI == ABI_DARWIN
11432 && flag_pic
11433 && current_function_uses_pic_offset_table)
4697a36c
MM		 11434 || info_ptr->calls_p)
11435 {
11436 info_ptr->lr_save_p = 1;
9ebbca7d 11437 regs_ever_live[LINK_REGISTER_REGNUM] = 1;
4697a36c
MM		 11438 }
11439
9ebbca7d 11440 /* Determine if we need to save the condition code registers. */
f676971a 11441 if (regs_ever_live[CR2_REGNO]
9ebbca7d
GK		 11442 || regs_ever_live[CR3_REGNO]
11443 || regs_ever_live[CR4_REGNO])
4697a36c
MM		 11444 {
11445 info_ptr->cr_save_p = 1;
178274da 11446 if (DEFAULT_ABI == ABI_V4)
4697a36c
MM		 11447 info_ptr->cr_size = reg_size;
11448 }
11449
83720594
RH		 11450 /* If the current function calls __builtin_eh_return, then we need
11451 to allocate stack space for registers that will hold data for
11452 the exception handler. */
11453 if (current_function_calls_eh_return)
11454 {
11455 unsigned int i;
11456 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; ++i)
11457 continue;
a3170dc6
AH		 11458
11459 /* SPE saves EH registers in 64-bits. */
c19de7aa
AH		 11460 ehrd_size = i * (TARGET_SPE_ABI
11461 && info_ptr->spe_64bit_regs_used != 0
11462 ? UNITS_PER_SPE_WORD : UNITS_PER_WORD);
83720594
RH		 11463 }
11464 else
11465 ehrd_size = 0;
11466
592696dd 11467 /* Determine various sizes. */
4697a36c
MM		 11468 info_ptr->reg_size = reg_size;
11469 info_ptr->fixed_size = RS6000_SAVE_AREA;
11470 info_ptr->varargs_size = RS6000_VARARGS_AREA;
189e03e3 11471 info_ptr->vars_size = RS6000_ALIGN (get_frame_size (), 8);
a4f6c312 11472 info_ptr->parm_size = RS6000_ALIGN (current_function_outgoing_args_size,
03e007d7 11473 TARGET_ALTIVEC ? 16 : 8);
00b960c7 11474
c19de7aa 11475 if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
a3170dc6
AH		 11476 info_ptr->spe_gp_size = 8 * (32 - info_ptr->first_gp_reg_save);
11477 else
11478 info_ptr->spe_gp_size = 0;
11479
4d774ff8
HP		 11480 if (TARGET_ALTIVEC_ABI)
11481 info_ptr->vrsave_mask = compute_vrsave_mask ();
00b960c7 11482 else
4d774ff8
HP		 11483 info_ptr->vrsave_mask = 0;
11484
11485 if (TARGET_ALTIVEC_VRSAVE && info_ptr->vrsave_mask)
11486 info_ptr->vrsave_size = 4;
11487 else
11488 info_ptr->vrsave_size = 0;
b6c9286a 11489
d62294f5
FJ		 11490 compute_save_world_info (info_ptr);
11491
592696dd 11492 /* Calculate the offsets. */
178274da 11493 switch (DEFAULT_ABI)
4697a36c 11494 {
b6c9286a 11495 case ABI_NONE:
24d304eb 11496 default:
b6c9286a
MM		 11497 abort ();
11498
11499 case ABI_AIX:
ee890fe2 11500 case ABI_DARWIN:
b6c9286a
MM		 11501 info_ptr->fp_save_offset = - info_ptr->fp_size;
11502 info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size;
00b960c7
AH		 11503
11504 if (TARGET_ALTIVEC_ABI)
11505 {
11506 info_ptr->vrsave_save_offset
11507 = info_ptr->gp_save_offset - info_ptr->vrsave_size;
11508
11509 /* Align stack so vector save area is on a quadword boundary. */
11510 if (info_ptr->altivec_size != 0)
11511 info_ptr->altivec_padding_size
11512 = 16 - (-info_ptr->vrsave_save_offset % 16);
11513 else
11514 info_ptr->altivec_padding_size = 0;
11515
11516 info_ptr->altivec_save_offset
11517 = info_ptr->vrsave_save_offset
11518 - info_ptr->altivec_padding_size
11519 - info_ptr->altivec_size;
11520
11521 /* Adjust for AltiVec case. */
11522 info_ptr->ehrd_offset = info_ptr->altivec_save_offset - ehrd_size;
11523 }
11524 else
11525 info_ptr->ehrd_offset = info_ptr->gp_save_offset - ehrd_size;
a260abc9
DE		 11526 info_ptr->cr_save_offset = reg_size; /* first word when 64-bit. */
11527 info_ptr->lr_save_offset = 2*reg_size;
24d304eb
RK		 11528 break;
11529
11530 case ABI_V4:
b6c9286a
MM		 11531 info_ptr->fp_save_offset = - info_ptr->fp_size;
11532 info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size;
a7df97e6 11533 info_ptr->cr_save_offset = info_ptr->gp_save_offset - info_ptr->cr_size;
00b960c7 11534
c19de7aa 11535 if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
c4ad648e
AM		 11536 {
11537 /* Align stack so SPE GPR save area is aligned on a
11538 double-word boundary. */
11539 if (info_ptr->spe_gp_size != 0)
11540 info_ptr->spe_padding_size
11541 = 8 - (-info_ptr->cr_save_offset % 8);
11542 else
11543 info_ptr->spe_padding_size = 0;
11544
11545 info_ptr->spe_gp_save_offset
11546 = info_ptr->cr_save_offset
11547 - info_ptr->spe_padding_size
11548 - info_ptr->spe_gp_size;
11549
11550 /* Adjust for SPE case. */
11551 info_ptr->toc_save_offset
11552 = info_ptr->spe_gp_save_offset - info_ptr->toc_size;
11553 }
a3170dc6 11554 else if (TARGET_ALTIVEC_ABI)
00b960c7
AH		 11555 {
11556 info_ptr->vrsave_save_offset
11557 = info_ptr->cr_save_offset - info_ptr->vrsave_size;
11558
11559 /* Align stack so vector save area is on a quadword boundary. */
11560 if (info_ptr->altivec_size != 0)
11561 info_ptr->altivec_padding_size
11562 = 16 - (-info_ptr->vrsave_save_offset % 16);
11563 else
11564 info_ptr->altivec_padding_size = 0;
11565
11566 info_ptr->altivec_save_offset
11567 = info_ptr->vrsave_save_offset
11568 - info_ptr->altivec_padding_size
11569 - info_ptr->altivec_size;
11570
11571 /* Adjust for AltiVec case. */
11572 info_ptr->toc_save_offset
11573 = info_ptr->altivec_save_offset - info_ptr->toc_size;
11574 }
11575 else
11576 info_ptr->toc_save_offset = info_ptr->cr_save_offset - info_ptr->toc_size;
83720594 11577 info_ptr->ehrd_offset = info_ptr->toc_save_offset - ehrd_size;
b6c9286a
MM		 11578 info_ptr->lr_save_offset = reg_size;
11579 break;
4697a36c
MM		 11580 }
11581
64045029 11582 save_align = (TARGET_ALTIVEC_ABI || DEFAULT_ABI == ABI_DARWIN) ? 16 : 8;
00b960c7
AH		 11583 info_ptr->save_size = RS6000_ALIGN (info_ptr->fp_size
11584 + info_ptr->gp_size
11585 + info_ptr->altivec_size
11586 + info_ptr->altivec_padding_size
a3170dc6
AH		 11587 + info_ptr->spe_gp_size
11588 + info_ptr->spe_padding_size
00b960c7
AH		 11589 + ehrd_size
11590 + info_ptr->cr_size
11591 + info_ptr->lr_size
11592 + info_ptr->vrsave_size
11593 + info_ptr->toc_size,
64045029 11594 save_align);
00b960c7 11595
44688022 11596 non_fixed_size = (info_ptr->vars_size
ff381587 11597 + info_ptr->parm_size
ff381587 11598 + info_ptr->save_size
44688022 11599 + info_ptr->varargs_size);
ff381587 11600
44688022
AM		 11601 info_ptr->total_size = RS6000_ALIGN (non_fixed_size + info_ptr->fixed_size,
11602 ABI_STACK_BOUNDARY / BITS_PER_UNIT);
ff381587
MM		 11603
11604 /* Determine if we need to allocate any stack frame:
11605
a4f6c312
SS		 11606 For AIX we need to push the stack if a frame pointer is needed
11607 (because the stack might be dynamically adjusted), if we are
11608 debugging, if we make calls, or if the sum of fp_save, gp_save,
11609 and local variables are more than the space needed to save all
11610 non-volatile registers: 32-bit: 18*8 + 19*4 = 220 or 64-bit: 18*8
11611 + 18*8 = 288 (GPR13 reserved).
ff381587 11612
a4f6c312
SS		 11613 For V.4 we don't have the stack cushion that AIX uses, but assume
11614 that the debugger can handle stackless frames. */
ff381587
MM		 11615
11616 if (info_ptr->calls_p)
11617 info_ptr->push_p = 1;
11618
178274da 11619 else if (DEFAULT_ABI == ABI_V4)
44688022 11620 info_ptr->push_p = non_fixed_size != 0;
ff381587 11621
178274da
AM		 11622 else if (frame_pointer_needed)
11623 info_ptr->push_p = 1;
11624
11625 else if (TARGET_XCOFF && write_symbols != NO_DEBUG)
11626 info_ptr->push_p = 1;
11627
ff381587 11628 else
44688022 11629 info_ptr->push_p = non_fixed_size > (TARGET_32BIT ? 220 : 288);
ff381587 11630
a4f6c312 11631 /* Zero offsets if we're not saving those registers. */
8dda1a21 11632 if (info_ptr->fp_size == 0)
4697a36c
MM		 11633 info_ptr->fp_save_offset = 0;
11634
8dda1a21 11635 if (info_ptr->gp_size == 0)
4697a36c
MM		 11636 info_ptr->gp_save_offset = 0;
11637
00b960c7
AH		 11638 if (! TARGET_ALTIVEC_ABI || info_ptr->altivec_size == 0)
11639 info_ptr->altivec_save_offset = 0;
11640
11641 if (! TARGET_ALTIVEC_ABI || info_ptr->vrsave_mask == 0)
11642 info_ptr->vrsave_save_offset = 0;
11643
c19de7aa
AH		 11644 if (! TARGET_SPE_ABI
11645 || info_ptr->spe_64bit_regs_used == 0
11646 || info_ptr->spe_gp_size == 0)
a3170dc6
AH		 11647 info_ptr->spe_gp_save_offset = 0;
11648
c81fc13e 11649 if (! info_ptr->lr_save_p)
4697a36c
MM		 11650 info_ptr->lr_save_offset = 0;
11651
c81fc13e 11652 if (! info_ptr->cr_save_p)
4697a36c
MM		 11653 info_ptr->cr_save_offset = 0;
11654
c81fc13e 11655 if (! info_ptr->toc_save_p)
b6c9286a
MM		 11656 info_ptr->toc_save_offset = 0;
11657
4697a36c
MM		 11658 return info_ptr;
11659}
11660
c19de7aa
AH		 11661/* Return true if the current function uses any GPRs in 64-bit SIMD
11662 mode. */
11663
11664static bool
863d938c 11665spe_func_has_64bit_regs_p (void)
c19de7aa
AH		 11666{
11667 rtx insns, insn;
11668
11669 /* Functions that save and restore all the call-saved registers will
11670 need to save/restore the registers in 64-bits. */
11671 if (current_function_calls_eh_return
11672 || current_function_calls_setjmp
11673 || current_function_has_nonlocal_goto)
11674 return true;
11675
11676 insns = get_insns ();
11677
11678 for (insn = NEXT_INSN (insns); insn != NULL_RTX; insn = NEXT_INSN (insn))
11679 {
11680 if (INSN_P (insn))
11681 {
11682 rtx i;
11683
b5a5beb9
AH		 11684 /* FIXME: This should be implemented with attributes...
11685
11686 (set_attr "spe64" "true")....then,
11687 if (get_spe64(insn)) return true;
11688
11689 It's the only reliable way to do the stuff below. */
11690
c19de7aa 11691 i = PATTERN (insn);
f82f556d
AH		 11692 if (GET_CODE (i) == SET)
11693 {
11694 enum machine_mode mode = GET_MODE (SET_SRC (i));
11695
11696 if (SPE_VECTOR_MODE (mode))
11697 return true;
11698 if (TARGET_E500_DOUBLE && mode == DFmode)
11699 return true;
11700 }
c19de7aa
AH		 11701 }
11702 }
11703
11704 return false;
11705}
11706
d1d0c603 11707static void
a2369ed3 11708debug_stack_info (rs6000_stack_t *info)
9878760c 11709{
d330fd93 11710 const char *abi_string;
24d304eb 11711
c81fc13e 11712 if (! info)
4697a36c
MM		 11713 info = rs6000_stack_info ();
11714
11715 fprintf (stderr, "\nStack information for function %s:\n",
11716 ((current_function_decl && DECL_NAME (current_function_decl))
11717 ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl))
11718 : "<unknown>"));
11719
24d304eb
RK		 11720 switch (info->abi)
11721 {
b6c9286a
MM		 11722 default: abi_string = "Unknown"; break;
11723 case ABI_NONE: abi_string = "NONE"; break;
50d440bc 11724 case ABI_AIX: abi_string = "AIX"; break;
ee890fe2 11725 case ABI_DARWIN: abi_string = "Darwin"; break;
b6c9286a 11726 case ABI_V4: abi_string = "V.4"; break;
24d304eb
RK		 11727 }
11728
11729 fprintf (stderr, "\tABI = %5s\n", abi_string);
11730
00b960c7
AH		 11731 if (TARGET_ALTIVEC_ABI)
11732 fprintf (stderr, "\tALTIVEC ABI extensions enabled.\n");
11733
a3170dc6
AH		 11734 if (TARGET_SPE_ABI)
11735 fprintf (stderr, "\tSPE ABI extensions enabled.\n");
11736
4697a36c
MM		 11737 if (info->first_gp_reg_save != 32)
11738 fprintf (stderr, "\tfirst_gp_reg_save = %5d\n", info->first_gp_reg_save);
11739
11740 if (info->first_fp_reg_save != 64)
11741 fprintf (stderr, "\tfirst_fp_reg_save = %5d\n", info->first_fp_reg_save);
9878760c 11742
00b960c7
AH		 11743 if (info->first_altivec_reg_save <= LAST_ALTIVEC_REGNO)
11744 fprintf (stderr, "\tfirst_altivec_reg_save = %5d\n",
11745 info->first_altivec_reg_save);
11746
4697a36c
MM		 11747 if (info->lr_save_p)
11748 fprintf (stderr, "\tlr_save_p = %5d\n", info->lr_save_p);
9878760c 11749
4697a36c
MM		 11750 if (info->cr_save_p)
11751 fprintf (stderr, "\tcr_save_p = %5d\n", info->cr_save_p);
11752
b6c9286a
MM		 11753 if (info->toc_save_p)
11754 fprintf (stderr, "\ttoc_save_p = %5d\n", info->toc_save_p);
11755
00b960c7
AH		 11756 if (info->vrsave_mask)
11757 fprintf (stderr, "\tvrsave_mask = 0x%x\n", info->vrsave_mask);
11758
4697a36c
MM		 11759 if (info->push_p)
11760 fprintf (stderr, "\tpush_p = %5d\n", info->push_p);
11761
11762 if (info->calls_p)
11763 fprintf (stderr, "\tcalls_p = %5d\n", info->calls_p);
11764
4697a36c
MM		 11765 if (info->gp_save_offset)
11766 fprintf (stderr, "\tgp_save_offset = %5d\n", info->gp_save_offset);
11767
11768 if (info->fp_save_offset)
11769 fprintf (stderr, "\tfp_save_offset = %5d\n", info->fp_save_offset);
11770
00b960c7
AH		 11771 if (info->altivec_save_offset)
11772 fprintf (stderr, "\taltivec_save_offset = %5d\n",
11773 info->altivec_save_offset);
11774
a3170dc6
AH		 11775 if (info->spe_gp_save_offset)
11776 fprintf (stderr, "\tspe_gp_save_offset = %5d\n",
11777 info->spe_gp_save_offset);
11778
00b960c7
AH		 11779 if (info->vrsave_save_offset)
11780 fprintf (stderr, "\tvrsave_save_offset = %5d\n",
11781 info->vrsave_save_offset);
11782
4697a36c
MM		 11783 if (info->lr_save_offset)
11784 fprintf (stderr, "\tlr_save_offset = %5d\n", info->lr_save_offset);
11785
11786 if (info->cr_save_offset)
11787 fprintf (stderr, "\tcr_save_offset = %5d\n", info->cr_save_offset);
11788
b6c9286a
MM		 11789 if (info->toc_save_offset)
11790 fprintf (stderr, "\ttoc_save_offset = %5d\n", info->toc_save_offset);
11791
4697a36c
MM		 11792 if (info->varargs_save_offset)
11793 fprintf (stderr, "\tvarargs_save_offset = %5d\n", info->varargs_save_offset);
11794
11795 if (info->total_size)
d1d0c603
JJ		 11796 fprintf (stderr, "\ttotal_size = "HOST_WIDE_INT_PRINT_DEC"\n",
11797 info->total_size);
4697a36c
MM		 11798
11799 if (info->varargs_size)
11800 fprintf (stderr, "\tvarargs_size = %5d\n", info->varargs_size);
11801
11802 if (info->vars_size)
d1d0c603
JJ		 11803 fprintf (stderr, "\tvars_size = "HOST_WIDE_INT_PRINT_DEC"\n",
11804 info->vars_size);
4697a36c
MM		 11805
11806 if (info->parm_size)
11807 fprintf (stderr, "\tparm_size = %5d\n", info->parm_size);
11808
11809 if (info->fixed_size)
11810 fprintf (stderr, "\tfixed_size = %5d\n", info->fixed_size);
11811
11812 if (info->gp_size)
11813 fprintf (stderr, "\tgp_size = %5d\n", info->gp_size);
11814
a3170dc6
AH		 11815 if (info->spe_gp_size)
11816 fprintf (stderr, "\tspe_gp_size = %5d\n", info->spe_gp_size);
11817
4697a36c
MM		 11818 if (info->fp_size)
11819 fprintf (stderr, "\tfp_size = %5d\n", info->fp_size);
11820
00b960c7
AH		 11821 if (info->altivec_size)
11822 fprintf (stderr, "\taltivec_size = %5d\n", info->altivec_size);
11823
11824 if (info->vrsave_size)
11825 fprintf (stderr, "\tvrsave_size = %5d\n", info->vrsave_size);
11826
11827 if (info->altivec_padding_size)
11828 fprintf (stderr, "\taltivec_padding_size= %5d\n",
11829 info->altivec_padding_size);
11830
a3170dc6
AH		 11831 if (info->spe_padding_size)
11832 fprintf (stderr, "\tspe_padding_size = %5d\n",
11833 info->spe_padding_size);
11834
a4f6c312 11835 if (info->lr_size)
ed947a96 11836 fprintf (stderr, "\tlr_size = %5d\n", info->lr_size);
b6c9286a 11837
4697a36c
MM		 11838 if (info->cr_size)
11839 fprintf (stderr, "\tcr_size = %5d\n", info->cr_size);
11840
a4f6c312 11841 if (info->toc_size)
b6c9286a
MM		 11842 fprintf (stderr, "\ttoc_size = %5d\n", info->toc_size);
11843
4697a36c
MM		 11844 if (info->save_size)
11845 fprintf (stderr, "\tsave_size = %5d\n", info->save_size);
11846
11847 if (info->reg_size != 4)
11848 fprintf (stderr, "\treg_size = %5d\n", info->reg_size);
11849
11850 fprintf (stderr, "\n");
9878760c 11851}
71f123ca
FS		 11852
11853rtx
a2369ed3 11854rs6000_return_addr (int count, rtx frame)
71f123ca 11855{
a4f6c312
SS		 11856 /* Currently we don't optimize very well between prolog and body
11857 code and for PIC code the code can be actually quite bad, so
11858 don't try to be too clever here. */
f1384257 11859 if (count != 0 || (DEFAULT_ABI != ABI_AIX && flag_pic))
71f123ca
FS		 11860 {
11861 cfun->machine->ra_needs_full_frame = 1;
8ac61af7
RK		 11862
11863 return
11864 gen_rtx_MEM
11865 (Pmode,
11866 memory_address
11867 (Pmode,
11868 plus_constant (copy_to_reg
11869 (gen_rtx_MEM (Pmode,
11870 memory_address (Pmode, frame))),
11871 RETURN_ADDRESS_OFFSET)));
71f123ca
FS		 11872 }
11873
8c29550d 11874 cfun->machine->ra_need_lr = 1;
9e2f7ec7 11875 return get_hard_reg_initial_val (Pmode, LINK_REGISTER_REGNUM);
71f123ca
FS		 11876}
11877
5e1bf043
DJ		 11878/* Say whether a function is a candidate for sibcall handling or not.
11879 We do not allow indirect calls to be optimized into sibling calls.
11880 Also, we can't do it if there are any vector parameters; there's
11881 nowhere to put the VRsave code so it works; note that functions with
11882 vector parameters are required to have a prototype, so the argument
11883 type info must be available here. (The tail recursion case can work
11884 with vector parameters, but there's no way to distinguish here.) */
4977bab6 11885static bool
a2369ed3 11886rs6000_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
5e1bf043
DJ		 11887{
11888 tree type;
4977bab6 11889 if (decl)
5e1bf043
DJ		 11890 {
11891 if (TARGET_ALTIVEC_VRSAVE)
c4ad648e 11892 {
4977bab6 11893 for (type = TYPE_ARG_TYPES (TREE_TYPE (decl));
5e1bf043
DJ		 11894 type; type = TREE_CHAIN (type))
11895 {
c15b529f 11896 if (TREE_CODE (TREE_VALUE (type)) == VECTOR_TYPE)
4977bab6 11897 return false;
5e1bf043 11898 }
c4ad648e 11899 }
5e1bf043 11900 if (DEFAULT_ABI == ABI_DARWIN
4977bab6 11901 || (*targetm.binds_local_p) (decl))
2bcc50d0 11902 {
4977bab6 11903 tree attr_list = TYPE_ATTRIBUTES (TREE_TYPE (decl));
2bcc50d0
AM		 11904
11905 if (!lookup_attribute ("longcall", attr_list)
11906 || lookup_attribute ("shortcall", attr_list))
4977bab6 11907 return true;
2bcc50d0 11908 }
5e1bf043 11909 }
4977bab6 11910 return false;
5e1bf043
DJ		 11911}
11912
71f123ca 11913static int
863d938c 11914rs6000_ra_ever_killed (void)
71f123ca
FS		 11915{
11916 rtx top;
5e1bf043
DJ		 11917 rtx reg;
11918 rtx insn;
71f123ca 11919
dd292d0a 11920 if (current_function_is_thunk)
71f123ca 11921 return 0;
eb0424da 11922
36f7e964
AH		 11923 /* regs_ever_live has LR marked as used if any sibcalls are present,
11924 but this should not force saving and restoring in the
11925 pro/epilogue. Likewise, reg_set_between_p thinks a sibcall
a3c9585f 11926 clobbers LR, so that is inappropriate. */
36f7e964 11927
5e1bf043
DJ		 11928 /* Also, the prologue can generate a store into LR that
11929 doesn't really count, like this:
36f7e964 11930
5e1bf043
DJ		 11931 move LR->R0
11932 bcl to set PIC register
11933 move LR->R31
11934 move R0->LR
36f7e964
AH		 11935
11936 When we're called from the epilogue, we need to avoid counting
11937 this as a store. */
f676971a 11938
71f123ca
FS		 11939 push_topmost_sequence ();
11940 top = get_insns ();
11941 pop_topmost_sequence ();
5e1bf043 11942 reg = gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM);
71f123ca 11943
5e1bf043
DJ		 11944 for (insn = NEXT_INSN (top); insn != NULL_RTX; insn = NEXT_INSN (insn))
11945 {
11946 if (INSN_P (insn))
11947 {
11948 if (FIND_REG_INC_NOTE (insn, reg))
11949 return 1;
f676971a 11950 else if (GET_CODE (insn) == CALL_INSN
c15b529f 11951 && !SIBLING_CALL_P (insn))
5e1bf043 11952 return 1;
36f7e964
AH		 11953 else if (set_of (reg, insn) != NULL_RTX
11954 && !prologue_epilogue_contains (insn))
5e1bf043
DJ		 11955 return 1;
11956 }
11957 }
11958 return 0;
71f123ca 11959}
4697a36c 11960\f
8cd8f856
GK		 11961/* Add a REG_MAYBE_DEAD note to the insn. */
11962static void
a2369ed3 11963rs6000_maybe_dead (rtx insn)
8cd8f856
GK		 11964{
11965 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD,
11966 const0_rtx,
11967 REG_NOTES (insn));
11968}
11969
9ebbca7d 11970/* Emit instructions needed to load the TOC register.
c7ca610e 11971 This is only needed when TARGET_TOC, TARGET_MINIMAL_TOC, and there is
9ebbca7d 11972 a constant pool; or for SVR4 -fpic. */
c7ca610e
RK		 11973
11974void
a2369ed3 11975rs6000_emit_load_toc_table (int fromprolog)
c7ca610e 11976{
027fbf43 11977 rtx dest, insn;
1db02437 11978 dest = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
c7ca610e 11979
20b71b17
AM		 11980 if (TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 1)
11981 {
11982 rtx temp = (fromprolog
11983 ? gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)
11984 : gen_reg_rtx (Pmode));
027fbf43
JJ		 11985 insn = emit_insn (gen_load_toc_v4_pic_si (temp));
11986 if (fromprolog)
11987 rs6000_maybe_dead (insn);
11988 insn = emit_move_insn (dest, temp);
11989 if (fromprolog)
11990 rs6000_maybe_dead (insn);
20b71b17
AM		 11991 }
11992 else if (TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2)
11993 {
11994 char buf[30];
11995 rtx tempLR = (fromprolog
11996 ? gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)
11997 : gen_reg_rtx (Pmode));
11998 rtx temp0 = (fromprolog
11999 ? gen_rtx_REG (Pmode, 0)
12000 : gen_reg_rtx (Pmode));
12001 rtx symF;
12002
20b71b17
AM		 12003 if (fromprolog)
12004 {
12005 rtx symL;
38c1f2d7 12006
20b71b17
AM		 12007 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
12008 symF = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
9ebbca7d 12009
20b71b17
AM		 12010 ASM_GENERATE_INTERNAL_LABEL (buf, "LCL", rs6000_pic_labelno);
12011 symL = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
12012
12013 rs6000_maybe_dead (emit_insn (gen_load_toc_v4_PIC_1 (tempLR,
12014 symF)));
12015 rs6000_maybe_dead (emit_move_insn (dest, tempLR));
12016 rs6000_maybe_dead (emit_insn (gen_load_toc_v4_PIC_2 (temp0, dest,
12017 symL,
12018 symF)));
9ebbca7d
GK		 12019 }
12020 else
20b71b17
AM		 12021 {
12022 rtx tocsym;
12023 static int reload_toc_labelno = 0;
12024
12025 tocsym = gen_rtx_SYMBOL_REF (Pmode, toc_label_name);
12026
12027 ASM_GENERATE_INTERNAL_LABEL (buf, "LCG", reload_toc_labelno++);
12028 symF = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
12029
027fbf43
JJ		 12030 emit_insn (gen_load_toc_v4_PIC_1b (tempLR, symF, tocsym));
12031 emit_move_insn (dest, tempLR);
12032 emit_move_insn (temp0, gen_rtx_MEM (Pmode, dest));
20b71b17 12033 }
027fbf43
JJ		 12034 insn = emit_insn (gen_addsi3 (dest, temp0, dest));
12035 if (fromprolog)
12036 rs6000_maybe_dead (insn);
9ebbca7d 12037 }
20b71b17
AM		 12038 else if (TARGET_ELF && !TARGET_AIX && flag_pic == 0 && TARGET_MINIMAL_TOC)
12039 {
12040 /* This is for AIX code running in non-PIC ELF32. */
12041 char buf[30];
12042 rtx realsym;
12043 ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1);
12044 realsym = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
12045
027fbf43
JJ		 12046 insn = emit_insn (gen_elf_high (dest, realsym));
12047 if (fromprolog)
12048 rs6000_maybe_dead (insn);
12049 insn = emit_insn (gen_elf_low (dest, dest, realsym));
12050 if (fromprolog)
12051 rs6000_maybe_dead (insn);
20b71b17
AM		 12052 }
12053 else if (DEFAULT_ABI == ABI_AIX)
9ebbca7d
GK		 12054 {
12055 if (TARGET_32BIT)
027fbf43 12056 insn = emit_insn (gen_load_toc_aix_si (dest));
9ebbca7d 12057 else
027fbf43
JJ		 12058 insn = emit_insn (gen_load_toc_aix_di (dest));
12059 if (fromprolog)
12060 rs6000_maybe_dead (insn);
9ebbca7d 12061 }
20b71b17
AM		 12062 else
12063 abort ();
9ebbca7d
GK		 12064}
12065
d1d0c603
JJ		 12066/* Emit instructions to restore the link register after determining where
12067 its value has been stored. */
12068
12069void
12070rs6000_emit_eh_reg_restore (rtx source, rtx scratch)
12071{
12072 rs6000_stack_t *info = rs6000_stack_info ();
12073 rtx operands[2];
12074
12075 operands[0] = source;
12076 operands[1] = scratch;
12077
12078 if (info->lr_save_p)
12079 {
12080 rtx frame_rtx = stack_pointer_rtx;
12081 HOST_WIDE_INT sp_offset = 0;
12082 rtx tmp;
12083
12084 if (frame_pointer_needed
12085 || current_function_calls_alloca
12086 || info->total_size > 32767)
12087 {
12088 emit_move_insn (operands[1], gen_rtx_MEM (Pmode, frame_rtx));
12089 frame_rtx = operands[1];
12090 }
12091 else if (info->push_p)
12092 sp_offset = info->total_size;
12093
12094 tmp = plus_constant (frame_rtx, info->lr_save_offset + sp_offset);
12095 tmp = gen_rtx_MEM (Pmode, tmp);
12096 emit_move_insn (tmp, operands[0]);
12097 }
12098 else
12099 emit_move_insn (gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM), operands[0]);
12100}
12101
f103e34d
GK		 12102static GTY(()) int set = -1;
12103
f676971a 12104int
863d938c 12105get_TOC_alias_set (void)
9ebbca7d 12106{
f103e34d
GK		 12107 if (set == -1)
12108 set = new_alias_set ();
12109 return set;
f676971a 12110}
9ebbca7d 12111
c1207243 12112/* This returns nonzero if the current function uses the TOC. This is
3c9eb5f4
AM		 12113 determined by the presence of (use (unspec ... UNSPEC_TOC)), which
12114 is generated by the ABI_V4 load_toc_* patterns. */
c954844a 12115#if TARGET_ELF
3c9eb5f4 12116static int
f676971a 12117uses_TOC (void)
9ebbca7d 12118{
c4501e62 12119 rtx insn;
38c1f2d7 12120
c4501e62
JJ		 12121 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
12122 if (INSN_P (insn))
12123 {
12124 rtx pat = PATTERN (insn);
12125 int i;
9ebbca7d 12126
f676971a 12127 if (GET_CODE (pat) == PARALLEL)
c4501e62
JJ		 12128 for (i = 0; i < XVECLEN (pat, 0); i++)
12129 {
12130 rtx sub = XVECEXP (pat, 0, i);
12131 if (GET_CODE (sub) == USE)
12132 {
12133 sub = XEXP (sub, 0);
12134 if (GET_CODE (sub) == UNSPEC
12135 && XINT (sub, 1) == UNSPEC_TOC)
12136 return 1;
12137 }
12138 }
12139 }
12140 return 0;
9ebbca7d 12141}
c954844a 12142#endif
38c1f2d7 12143
9ebbca7d 12144rtx
f676971a 12145create_TOC_reference (rtx symbol)
9ebbca7d 12146{
f676971a 12147 return gen_rtx_PLUS (Pmode,
a8a05998 12148 gen_rtx_REG (Pmode, TOC_REGISTER),
f676971a
EC		 12149 gen_rtx_CONST (Pmode,
12150 gen_rtx_MINUS (Pmode, symbol,
b999aaeb 12151 gen_rtx_SYMBOL_REF (Pmode, toc_label_name))));
9ebbca7d 12152}
38c1f2d7 12153
fc4767bb
JJ		 12154/* If _Unwind_* has been called from within the same module,
12155 toc register is not guaranteed to be saved to 40(1) on function
12156 entry. Save it there in that case. */
c7ca610e 12157
9ebbca7d 12158void
863d938c 12159rs6000_aix_emit_builtin_unwind_init (void)
9ebbca7d
GK		 12160{
12161 rtx mem;
12162 rtx stack_top = gen_reg_rtx (Pmode);
12163 rtx opcode_addr = gen_reg_rtx (Pmode);
fc4767bb
JJ		 12164 rtx opcode = gen_reg_rtx (SImode);
12165 rtx tocompare = gen_reg_rtx (SImode);
12166 rtx no_toc_save_needed = gen_label_rtx ();
9ebbca7d
GK		 12167
12168 mem = gen_rtx_MEM (Pmode, hard_frame_pointer_rtx);
12169 emit_move_insn (stack_top, mem);
12170
fc4767bb
JJ		 12171 mem = gen_rtx_MEM (Pmode,
12172 gen_rtx_PLUS (Pmode, stack_top,
9ebbca7d
GK		 12173 GEN_INT (2 * GET_MODE_SIZE (Pmode))));
12174 emit_move_insn (opcode_addr, mem);
fc4767bb
JJ		 12175 emit_move_insn (opcode, gen_rtx_MEM (SImode, opcode_addr));
12176 emit_move_insn (tocompare, gen_int_mode (TARGET_32BIT ? 0x80410014
2496c7bd 12177 : 0xE8410028, SImode));
9ebbca7d 12178
fc4767bb 12179 do_compare_rtx_and_jump (opcode, tocompare, EQ, 1,
06f4e019 12180 SImode, NULL_RTX, NULL_RTX,
fc4767bb 12181 no_toc_save_needed);
9ebbca7d 12182
fc4767bb
JJ		 12183 mem = gen_rtx_MEM (Pmode,
12184 gen_rtx_PLUS (Pmode, stack_top,
12185 GEN_INT (5 * GET_MODE_SIZE (Pmode))));
12186 emit_move_insn (mem, gen_rtx_REG (Pmode, 2));
12187 emit_label (no_toc_save_needed);
9ebbca7d 12188}
38c1f2d7 12189\f
ba4828e0
RK		 12190/* This ties together stack memory (MEM with an alias set of
12191 rs6000_sr_alias_set) and the change to the stack pointer. */
12192
9ebbca7d 12193static void
863d938c 12194rs6000_emit_stack_tie (void)
9ebbca7d 12195{
ba4828e0
RK		 12196 rtx mem = gen_rtx_MEM (BLKmode, gen_rtx_REG (Pmode, STACK_POINTER_REGNUM));
12197
12198 set_mem_alias_set (mem, rs6000_sr_alias_set);
9ebbca7d
GK		 12199 emit_insn (gen_stack_tie (mem));
12200}
38c1f2d7 12201
9ebbca7d
GK		 12202/* Emit the correct code for allocating stack space, as insns.
12203 If COPY_R12, make sure a copy of the old frame is left in r12.
12204 The generated code may use hard register 0 as a temporary. */
12205
12206static void
a2369ed3 12207rs6000_emit_allocate_stack (HOST_WIDE_INT size, int copy_r12)
38c1f2d7 12208{
9ebbca7d
GK		 12209 rtx insn;
12210 rtx stack_reg = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
12211 rtx tmp_reg = gen_rtx_REG (Pmode, 0);
61168ff1
RS		 12212 rtx todec = gen_int_mode (-size, Pmode);
12213
12214 if (INTVAL (todec) != -size)
12215 {
9390387d 12216 warning ("stack frame too large");
61168ff1
RS		 12217 emit_insn (gen_trap ());
12218 return;
12219 }
a157febd
GK		 12220
12221 if (current_function_limit_stack)
12222 {
12223 if (REG_P (stack_limit_rtx)
f676971a 12224 && REGNO (stack_limit_rtx) > 1
a157febd
GK		 12225 && REGNO (stack_limit_rtx) <= 31)
12226 {
5b71a4e7 12227 emit_insn (TARGET_32BIT
9ebbca7d
GK		 12228 ? gen_addsi3 (tmp_reg,
12229 stack_limit_rtx,
12230 GEN_INT (size))
12231 : gen_adddi3 (tmp_reg,
12232 stack_limit_rtx,
12233 GEN_INT (size)));
5b71a4e7 12234
9ebbca7d
GK		 12235 emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg,
12236 const0_rtx));
a157febd
GK		 12237 }
12238 else if (GET_CODE (stack_limit_rtx) == SYMBOL_REF
9ebbca7d 12239 && TARGET_32BIT
f607bc57 12240 && DEFAULT_ABI == ABI_V4)
a157febd 12241 {
9ebbca7d 12242 rtx toload = gen_rtx_CONST (VOIDmode,
f676971a
EC		 12243 gen_rtx_PLUS (Pmode,
12244 stack_limit_rtx,
9ebbca7d 12245 GEN_INT (size)));
5b71a4e7 12246
9ebbca7d
GK		 12247 emit_insn (gen_elf_high (tmp_reg, toload));
12248 emit_insn (gen_elf_low (tmp_reg, tmp_reg, toload));
12249 emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg,
12250 const0_rtx));
a157febd
GK		 12251 }
12252 else
12253 warning ("stack limit expression is not supported");
12254 }
12255
9ebbca7d
GK		 12256 if (copy_r12 || ! TARGET_UPDATE)
12257 emit_move_insn (gen_rtx_REG (Pmode, 12), stack_reg);
12258
38c1f2d7
MM		 12259 if (TARGET_UPDATE)
12260 {
9ebbca7d 12261 if (size > 32767)
38c1f2d7 12262 {
9ebbca7d 12263 /* Need a note here so that try_split doesn't get confused. */
9390387d 12264 if (get_last_insn () == NULL_RTX)
2e040219 12265 emit_note (NOTE_INSN_DELETED);
9ebbca7d
GK		 12266 insn = emit_move_insn (tmp_reg, todec);
12267 try_split (PATTERN (insn), insn, 0);
12268 todec = tmp_reg;
38c1f2d7 12269 }
5b71a4e7
DE		 12270
12271 insn = emit_insn (TARGET_32BIT
12272 ? gen_movsi_update (stack_reg, stack_reg,
12273 todec, stack_reg)
c4ad648e 12274 : gen_movdi_di_update (stack_reg, stack_reg,
9ebbca7d 12275 todec, stack_reg));
38c1f2d7
MM		 12276 }
12277 else
12278 {
5b71a4e7
DE		 12279 insn = emit_insn (TARGET_32BIT
12280 ? gen_addsi3 (stack_reg, stack_reg, todec)
12281 : gen_adddi3 (stack_reg, stack_reg, todec));
9ebbca7d
GK		 12282 emit_move_insn (gen_rtx_MEM (Pmode, stack_reg),
12283 gen_rtx_REG (Pmode, 12));
12284 }
f676971a 12285
9ebbca7d 12286 RTX_FRAME_RELATED_P (insn) = 1;
f676971a 12287 REG_NOTES (insn) =
9ebbca7d 12288 gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
f676971a 12289 gen_rtx_SET (VOIDmode, stack_reg,
9ebbca7d
GK		 12290 gen_rtx_PLUS (Pmode, stack_reg,
12291 GEN_INT (-size))),
12292 REG_NOTES (insn));
12293}
12294
a4f6c312
SS		 12295/* Add to 'insn' a note which is PATTERN (INSN) but with REG replaced
12296 with (plus:P (reg 1) VAL), and with REG2 replaced with RREG if REG2
12297 is not NULL. It would be nice if dwarf2out_frame_debug_expr could
12298 deduce these equivalences by itself so it wasn't necessary to hold
12299 its hand so much. */
9ebbca7d
GK		 12300
12301static void
f676971a 12302rs6000_frame_related (rtx insn, rtx reg, HOST_WIDE_INT val,
a2369ed3 12303 rtx reg2, rtx rreg)
9ebbca7d
GK		 12304{
12305 rtx real, temp;
12306
e56c4463
JL		 12307 /* copy_rtx will not make unique copies of registers, so we need to
12308 ensure we don't have unwanted sharing here. */
12309 if (reg == reg2)
12310 reg = gen_raw_REG (GET_MODE (reg), REGNO (reg));
12311
12312 if (reg == rreg)
12313 reg = gen_raw_REG (GET_MODE (reg), REGNO (reg));
12314
9ebbca7d
GK		 12315 real = copy_rtx (PATTERN (insn));
12316
89e7058f
AH		 12317 if (reg2 != NULL_RTX)
12318 real = replace_rtx (real, reg2, rreg);
f676971a
EC		 12319
12320 real = replace_rtx (real, reg,
9ebbca7d
GK		 12321 gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode,
12322 STACK_POINTER_REGNUM),
12323 GEN_INT (val)));
f676971a 12324
9ebbca7d
GK		 12325 /* We expect that 'real' is either a SET or a PARALLEL containing
12326 SETs (and possibly other stuff). In a PARALLEL, all the SETs
12327 are important so they all have to be marked RTX_FRAME_RELATED_P. */
12328
12329 if (GET_CODE (real) == SET)
12330 {
12331 rtx set = real;
f676971a 12332
9ebbca7d
GK		 12333 temp = simplify_rtx (SET_SRC (set));
12334 if (temp)
12335 SET_SRC (set) = temp;
12336 temp = simplify_rtx (SET_DEST (set));
12337 if (temp)
12338 SET_DEST (set) = temp;
12339 if (GET_CODE (SET_DEST (set)) == MEM)
38c1f2d7 12340 {
9ebbca7d
GK		 12341 temp = simplify_rtx (XEXP (SET_DEST (set), 0));
12342 if (temp)
12343 XEXP (SET_DEST (set), 0) = temp;
38c1f2d7 12344 }
38c1f2d7 12345 }
9ebbca7d
GK		 12346 else if (GET_CODE (real) == PARALLEL)
12347 {
12348 int i;
12349 for (i = 0; i < XVECLEN (real, 0); i++)
12350 if (GET_CODE (XVECEXP (real, 0, i)) == SET)
12351 {
12352 rtx set = XVECEXP (real, 0, i);
f676971a 12353
9ebbca7d
GK		 12354 temp = simplify_rtx (SET_SRC (set));
12355 if (temp)
12356 SET_SRC (set) = temp;
12357 temp = simplify_rtx (SET_DEST (set));
12358 if (temp)
12359 SET_DEST (set) = temp;
12360 if (GET_CODE (SET_DEST (set)) == MEM)
12361 {
12362 temp = simplify_rtx (XEXP (SET_DEST (set), 0));
12363 if (temp)
12364 XEXP (SET_DEST (set), 0) = temp;
12365 }
12366 RTX_FRAME_RELATED_P (set) = 1;
12367 }
12368 }
12369 else
a4f6c312 12370 abort ();
c19de7aa
AH		 12371
12372 if (TARGET_SPE)
12373 real = spe_synthesize_frame_save (real);
12374
9ebbca7d
GK		 12375 RTX_FRAME_RELATED_P (insn) = 1;
12376 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
12377 real,
12378 REG_NOTES (insn));
38c1f2d7
MM		 12379}
12380
c19de7aa
AH		 12381/* Given an SPE frame note, return a PARALLEL of SETs with the
12382 original note, plus a synthetic register save. */
12383
12384static rtx
a2369ed3 12385spe_synthesize_frame_save (rtx real)
c19de7aa
AH		 12386{
12387 rtx synth, offset, reg, real2;
12388
12389 if (GET_CODE (real) != SET
12390 || GET_MODE (SET_SRC (real)) != V2SImode)
12391 return real;
12392
12393 /* For the SPE, registers saved in 64-bits, get a PARALLEL for their
12394 frame related note. The parallel contains a set of the register
41f3a930 12395 being saved, and another set to a synthetic register (n+1200).
c19de7aa
AH		 12396 This is so we can differentiate between 64-bit and 32-bit saves.
12397 Words cannot describe this nastiness. */
12398
12399 if (GET_CODE (SET_DEST (real)) != MEM
12400 || GET_CODE (XEXP (SET_DEST (real), 0)) != PLUS
12401 || GET_CODE (SET_SRC (real)) != REG)
12402 abort ();
12403
12404 /* Transform:
12405 (set (mem (plus (reg x) (const y)))
12406 (reg z))
12407 into:
12408 (set (mem (plus (reg x) (const y+4)))
41f3a930 12409 (reg z+1200))
c19de7aa
AH		 12410 */
12411
12412 real2 = copy_rtx (real);
12413 PUT_MODE (SET_DEST (real2), SImode);
12414 reg = SET_SRC (real2);
12415 real2 = replace_rtx (real2, reg, gen_rtx_REG (SImode, REGNO (reg)));
12416 synth = copy_rtx (real2);
12417
12418 if (BYTES_BIG_ENDIAN)
12419 {
12420 offset = XEXP (XEXP (SET_DEST (real2), 0), 1);
12421 real2 = replace_rtx (real2, offset, GEN_INT (INTVAL (offset) + 4));
12422 }
12423
12424 reg = SET_SRC (synth);
41f3a930 12425
c19de7aa 12426 synth = replace_rtx (synth, reg,
41f3a930 12427 gen_rtx_REG (SImode, REGNO (reg) + 1200));
c19de7aa
AH		 12428
12429 offset = XEXP (XEXP (SET_DEST (synth), 0), 1);
12430 synth = replace_rtx (synth, offset,
12431 GEN_INT (INTVAL (offset)
12432 + (BYTES_BIG_ENDIAN ? 0 : 4)));
12433
12434 RTX_FRAME_RELATED_P (synth) = 1;
12435 RTX_FRAME_RELATED_P (real2) = 1;
12436 if (BYTES_BIG_ENDIAN)
12437 real = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, synth, real2));
12438 else
12439 real = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, real2, synth));
12440
12441 return real;
12442}
12443
00b960c7
AH		 12444/* Returns an insn that has a vrsave set operation with the
12445 appropriate CLOBBERs. */
12446
12447static rtx
a2369ed3 12448generate_set_vrsave (rtx reg, rs6000_stack_t *info, int epiloguep)
00b960c7
AH		 12449{
12450 int nclobs, i;
12451 rtx insn, clobs[TOTAL_ALTIVEC_REGS + 1];
a004eb82 12452 rtx vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO);
00b960c7 12453
a004eb82
AH		 12454 clobs[0]
12455 = gen_rtx_SET (VOIDmode,
12456 vrsave,
12457 gen_rtx_UNSPEC_VOLATILE (SImode,
12458 gen_rtvec (2, reg, vrsave),
12459 30));
00b960c7
AH		 12460
12461 nclobs = 1;
12462
9aa86737
AH		 12463 /* We need to clobber the registers in the mask so the scheduler
12464 does not move sets to VRSAVE before sets of AltiVec registers.
12465
12466 However, if the function receives nonlocal gotos, reload will set
12467 all call saved registers live. We will end up with:
12468
12469 (set (reg 999) (mem))
12470 (parallel [ (set (reg vrsave) (unspec blah))
12471 (clobber (reg 999))])
12472
12473 The clobber will cause the store into reg 999 to be dead, and
12474 flow will attempt to delete an epilogue insn. In this case, we
12475 need an unspec use/set of the register. */
00b960c7
AH		 12476
12477 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
44688022 12478 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
9aa86737
AH		 12479 {
12480 if (!epiloguep || call_used_regs [i])
12481 clobs[nclobs++] = gen_rtx_CLOBBER (VOIDmode,
12482 gen_rtx_REG (V4SImode, i));
12483 else
12484 {
12485 rtx reg = gen_rtx_REG (V4SImode, i);
9aa86737
AH		 12486
12487 clobs[nclobs++]
a004eb82
AH		 12488 = gen_rtx_SET (VOIDmode,
12489 reg,
12490 gen_rtx_UNSPEC (V4SImode,
12491 gen_rtvec (1, reg), 27));
9aa86737
AH		 12492 }
12493 }
00b960c7
AH		 12494
12495 insn = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (nclobs));
12496
12497 for (i = 0; i < nclobs; ++i)
12498 XVECEXP (insn, 0, i) = clobs[i];
12499
12500 return insn;
12501}
12502
89e7058f
AH		 12503/* Save a register into the frame, and emit RTX_FRAME_RELATED_P notes.
12504 Save REGNO into [FRAME_REG + OFFSET] in mode MODE. */
12505
12506static void
f676971a 12507emit_frame_save (rtx frame_reg, rtx frame_ptr, enum machine_mode mode,
d1d0c603 12508 unsigned int regno, int offset, HOST_WIDE_INT total_size)
89e7058f
AH		 12509{
12510 rtx reg, offset_rtx, insn, mem, addr, int_rtx;
12511 rtx replacea, replaceb;
12512
12513 int_rtx = GEN_INT (offset);
12514
12515 /* Some cases that need register indexed addressing. */
12516 if ((TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
4d4cbc0e 12517 || (TARGET_E500_DOUBLE && mode == DFmode)
a3170dc6
AH		 12518 || (TARGET_SPE_ABI
12519 && SPE_VECTOR_MODE (mode)
12520 && !SPE_CONST_OFFSET_OK (offset)))
89e7058f
AH		 12521 {
12522 /* Whomever calls us must make sure r11 is available in the
c4ad648e 12523 flow path of instructions in the prologue. */
89e7058f
AH		 12524 offset_rtx = gen_rtx_REG (Pmode, 11);
12525 emit_move_insn (offset_rtx, int_rtx);
12526
12527 replacea = offset_rtx;
12528 replaceb = int_rtx;
12529 }
12530 else
12531 {
12532 offset_rtx = int_rtx;
12533 replacea = NULL_RTX;
12534 replaceb = NULL_RTX;
12535 }
12536
12537 reg = gen_rtx_REG (mode, regno);
12538 addr = gen_rtx_PLUS (Pmode, frame_reg, offset_rtx);
12539 mem = gen_rtx_MEM (mode, addr);
12540 set_mem_alias_set (mem, rs6000_sr_alias_set);
12541
12542 insn = emit_move_insn (mem, reg);
12543
12544 rs6000_frame_related (insn, frame_ptr, total_size, replacea, replaceb);
12545}
12546
a3170dc6
AH		 12547/* Emit an offset memory reference suitable for a frame store, while
12548 converting to a valid addressing mode. */
12549
12550static rtx
a2369ed3 12551gen_frame_mem_offset (enum machine_mode mode, rtx reg, int offset)
a3170dc6
AH		 12552{
12553 rtx int_rtx, offset_rtx;
12554
12555 int_rtx = GEN_INT (offset);
12556
4d4cbc0e
AH		 12557 if ((TARGET_SPE_ABI && SPE_VECTOR_MODE (mode))
12558 || (TARGET_E500_DOUBLE && mode == DFmode))
a3170dc6
AH		 12559 {
12560 offset_rtx = gen_rtx_REG (Pmode, FIXED_SCRATCH);
12561 emit_move_insn (offset_rtx, int_rtx);
12562 }
12563 else
12564 offset_rtx = int_rtx;
12565
12566 return gen_rtx_MEM (mode, gen_rtx_PLUS (Pmode, reg, offset_rtx));
12567}
12568
699c914a
MS		 12569#ifndef TARGET_FIX_AND_CONTINUE
12570#define TARGET_FIX_AND_CONTINUE 0
12571#endif
12572
9ebbca7d
GK		 12573/* Emit function prologue as insns. */
12574
9878760c 12575void
863d938c 12576rs6000_emit_prologue (void)
9878760c 12577{
4697a36c 12578 rs6000_stack_t *info = rs6000_stack_info ();
0e67400a 12579 enum machine_mode reg_mode = Pmode;
327e5343 12580 int reg_size = TARGET_32BIT ? 4 : 8;
9ebbca7d
GK		 12581 rtx sp_reg_rtx = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
12582 rtx frame_ptr_rtx = gen_rtx_REG (Pmode, 12);
12583 rtx frame_reg_rtx = sp_reg_rtx;
b78d48dd 12584 rtx cr_save_rtx = NULL_RTX;
9ebbca7d
GK		 12585 rtx insn;
12586 int saving_FPRs_inline;
12587 int using_store_multiple;
12588 HOST_WIDE_INT sp_offset = 0;
f676971a 12589
699c914a
MS		 12590 if (TARGET_FIX_AND_CONTINUE)
12591 {
12592 /* gdb on darwin arranges to forward a function from the old
12593 address by modifying the first 4 instructions of the function
12594 to branch to the overriding function. This is necessary to
12595 permit function pointers that point to the old function to
12596 actually forward to the new function. */
12597 emit_insn (gen_nop ());
12598 emit_insn (gen_nop ());
12599 emit_insn (gen_nop ());
12600 emit_insn (gen_nop ());
12601 }
12602
12603 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
12604 {
12605 reg_mode = V2SImode;
12606 reg_size = 8;
12607 }
a3170dc6 12608
9ebbca7d 12609 using_store_multiple = (TARGET_MULTIPLE && ! TARGET_POWERPC64
c19de7aa
AH		 12610 && (!TARGET_SPE_ABI
12611 || info->spe_64bit_regs_used == 0)
9ebbca7d
GK		 12612 && info->first_gp_reg_save < 31);
12613 saving_FPRs_inline = (info->first_fp_reg_save == 64
8c29550d 12614 || FP_SAVE_INLINE (info->first_fp_reg_save)
acd0b319 12615 || current_function_calls_eh_return
8c29550d 12616 || cfun->machine->ra_need_lr);
9ebbca7d
GK		 12617
12618 /* For V.4, update stack before we do any saving and set back pointer. */
fc4767bb 12619 if (info->push_p
acd0b319
AM		 12620 && (DEFAULT_ABI == ABI_V4
12621 || current_function_calls_eh_return))
9ebbca7d
GK		 12622 {
12623 if (info->total_size < 32767)
12624 sp_offset = info->total_size;
12625 else
12626 frame_reg_rtx = frame_ptr_rtx;
f676971a 12627 rs6000_emit_allocate_stack (info->total_size,
9ebbca7d
GK		 12628 (frame_reg_rtx != sp_reg_rtx
12629 && (info->cr_save_p
12630 || info->lr_save_p
12631 || info->first_fp_reg_save < 64
12632 || info->first_gp_reg_save < 32
12633 )));
12634 if (frame_reg_rtx != sp_reg_rtx)
12635 rs6000_emit_stack_tie ();
12636 }
12637
d62294f5 12638 /* Handle world saves specially here. */
f57fe068 12639 if (WORLD_SAVE_P (info))
d62294f5
FJ		 12640 {
12641 int i, j, sz;
12642 rtx treg;
12643 rtvec p;
12644
12645 /* save_world expects lr in r0. */
12646 if (info->lr_save_p)
c4ad648e
AM		 12647 {
12648 insn = emit_move_insn (gen_rtx_REG (Pmode, 0),
12649 gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM));
12650 RTX_FRAME_RELATED_P (insn) = 1;
12651 }
d62294f5
FJ		 12652
12653 /* The SAVE_WORLD and RESTORE_WORLD routines make a number of
c4ad648e
AM		 12654 assumptions about the offsets of various bits of the stack
12655 frame. Abort if things aren't what they should be. */
d62294f5 12656 if (info->gp_save_offset != -220
c4ad648e
AM		 12657 || info->fp_save_offset != -144
12658 || info->lr_save_offset != 8
12659 || info->cr_save_offset != 4
12660 || !info->push_p
12661 || !info->lr_save_p
12662 || (current_function_calls_eh_return && info->ehrd_offset != -432)
12663 || (info->vrsave_save_offset != -224
12664 || info->altivec_save_offset != (-224 -16 -192)))
12665 abort ();
d62294f5
FJ		 12666
12667 treg = gen_rtx_REG (SImode, 11);
12668 emit_move_insn (treg, GEN_INT (-info->total_size));
12669
12670 /* SAVE_WORLD takes the caller's LR in R0 and the frame size
c4ad648e 12671 in R11. It also clobbers R12, so beware! */
d62294f5
FJ		 12672
12673 /* Preserve CR2 for save_world prologues */
12674 sz = 6;
12675 sz += 32 - info->first_gp_reg_save;
12676 sz += 64 - info->first_fp_reg_save;
12677 sz += LAST_ALTIVEC_REGNO - info->first_altivec_reg_save + 1;
12678 p = rtvec_alloc (sz);
12679 j = 0;
12680 RTVEC_ELT (p, j++) = gen_rtx_CLOBBER (VOIDmode,
c4ad648e
AM		 12681 gen_rtx_REG (Pmode,
12682 LINK_REGISTER_REGNUM));
d62294f5 12683 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode,
c4ad648e
AM		 12684 gen_rtx_SYMBOL_REF (Pmode,
12685 "*save_world"));
d62294f5 12686 /* We do floats first so that the instruction pattern matches
c4ad648e
AM		 12687 properly. */
12688 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
12689 {
12690 rtx reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i);
12691 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
12692 GEN_INT (info->fp_save_offset
12693 + sp_offset + 8 * i));
12694 rtx mem = gen_rtx_MEM (DFmode, addr);
12695 set_mem_alias_set (mem, rs6000_sr_alias_set);
12696
12697 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
12698 }
d62294f5 12699 for (i = 0; info->first_altivec_reg_save + i <= LAST_ALTIVEC_REGNO; i++)
c4ad648e
AM		 12700 {
12701 rtx reg = gen_rtx_REG (V4SImode, info->first_altivec_reg_save + i);
12702 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
12703 GEN_INT (info->altivec_save_offset
12704 + sp_offset + 16 * i));
12705 rtx mem = gen_rtx_MEM (V4SImode, addr);
12706 set_mem_alias_set (mem, rs6000_sr_alias_set);
12707
12708 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
12709 }
d62294f5 12710 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
c4ad648e
AM		 12711 {
12712 rtx reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
12713 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
12714 GEN_INT (info->gp_save_offset
12715 + sp_offset + reg_size * i));
12716 rtx mem = gen_rtx_MEM (reg_mode, addr);
12717 set_mem_alias_set (mem, rs6000_sr_alias_set);
12718
12719 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
12720 }
12721
12722 {
12723 /* CR register traditionally saved as CR2. */
12724 rtx reg = gen_rtx_REG (reg_mode, CR2_REGNO);
12725 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
12726 GEN_INT (info->cr_save_offset
12727 + sp_offset));
12728 rtx mem = gen_rtx_MEM (reg_mode, addr);
12729 set_mem_alias_set (mem, rs6000_sr_alias_set);
12730
12731 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
12732 }
d62294f5
FJ		 12733 /* Prevent any attempt to delete the setting of r0 and treg! */
12734 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode, gen_rtx_REG (Pmode, 0));
12735 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode, treg);
12736 RTVEC_ELT (p, j++) = gen_rtx_CLOBBER (VOIDmode, sp_reg_rtx);
12737
12738 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
12739 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
c4ad648e 12740 NULL_RTX, NULL_RTX);
d62294f5
FJ		 12741
12742 if (current_function_calls_eh_return)
c4ad648e
AM		 12743 {
12744 unsigned int i;
12745 for (i = 0; ; ++i)
12746 {
12747 unsigned int regno = EH_RETURN_DATA_REGNO (i);
12748 if (regno == INVALID_REGNUM)
12749 break;
12750 emit_frame_save (frame_reg_rtx, frame_ptr_rtx, reg_mode, regno,
12751 info->ehrd_offset + sp_offset
12752 + reg_size * (int) i,
12753 info->total_size);
12754 }
12755 }
d62294f5
FJ		 12756 }
12757
9aa86737 12758 /* Save AltiVec registers if needed. */
f57fe068 12759 if (!WORLD_SAVE_P (info) && TARGET_ALTIVEC_ABI && info->altivec_size != 0)
9aa86737
AH		 12760 {
12761 int i;
12762
12763 /* There should be a non inline version of this, for when we
12764 are saving lots of vector registers. */
12765 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
12766 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
12767 {
12768 rtx areg, savereg, mem;
12769 int offset;
12770
12771 offset = info->altivec_save_offset + sp_offset
12772 + 16 * (i - info->first_altivec_reg_save);
12773
12774 savereg = gen_rtx_REG (V4SImode, i);
12775
12776 areg = gen_rtx_REG (Pmode, 0);
12777 emit_move_insn (areg, GEN_INT (offset));
12778
12779 /* AltiVec addressing mode is [reg+reg]. */
12780 mem = gen_rtx_MEM (V4SImode,
12781 gen_rtx_PLUS (Pmode, frame_reg_rtx, areg));
f676971a 12782
9aa86737
AH		 12783 set_mem_alias_set (mem, rs6000_sr_alias_set);
12784
12785 insn = emit_move_insn (mem, savereg);
12786
5c242421
SB		 12787 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
12788 areg, GEN_INT (offset));
9aa86737
AH		 12789 }
12790 }
12791
12792 /* VRSAVE is a bit vector representing which AltiVec registers
12793 are used. The OS uses this to determine which vector
12794 registers to save on a context switch. We need to save
12795 VRSAVE on the stack frame, add whatever AltiVec registers we
12796 used in this function, and do the corresponding magic in the
12797 epilogue. */
12798
4d774ff8 12799 if (TARGET_ALTIVEC && TARGET_ALTIVEC_VRSAVE
f57fe068 12800 && !WORLD_SAVE_P (info) && info->vrsave_mask != 0)
9aa86737 12801 {
a004eb82 12802 rtx reg, mem, vrsave;
9aa86737
AH		 12803 int offset;
12804
eab97e44
AM		 12805 /* Get VRSAVE onto a GPR. Note that ABI_V4 might be using r12
12806 as frame_reg_rtx and r11 as the static chain pointer for
12807 nested functions. */
12808 reg = gen_rtx_REG (SImode, 0);
a004eb82 12809 vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO);
b188f760
AH		 12810 if (TARGET_MACHO)
12811 emit_insn (gen_get_vrsave_internal (reg));
12812 else
12813 emit_insn (gen_rtx_SET (VOIDmode, reg, vrsave));
9aa86737
AH		 12814
12815 /* Save VRSAVE. */
12816 offset = info->vrsave_save_offset + sp_offset;
12817 mem
12818 = gen_rtx_MEM (SImode,
12819 gen_rtx_PLUS (Pmode, frame_reg_rtx, GEN_INT (offset)));
12820 set_mem_alias_set (mem, rs6000_sr_alias_set);
12821 insn = emit_move_insn (mem, reg);
12822
12823 /* Include the registers in the mask. */
12824 emit_insn (gen_iorsi3 (reg, reg, GEN_INT ((int) info->vrsave_mask)));
12825
12826 insn = emit_insn (generate_set_vrsave (reg, info, 0));
12827 }
12828
9ebbca7d 12829 /* If we use the link register, get it into r0. */
f57fe068 12830 if (!WORLD_SAVE_P (info) && info->lr_save_p)
f8a57be8
GK		 12831 {
12832 insn = emit_move_insn (gen_rtx_REG (Pmode, 0),
12833 gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM));
12834 RTX_FRAME_RELATED_P (insn) = 1;
12835 }
9ebbca7d
GK		 12836
12837 /* If we need to save CR, put it into r12. */
f57fe068 12838 if (!WORLD_SAVE_P (info) && info->cr_save_p && frame_reg_rtx != frame_ptr_rtx)
9ebbca7d 12839 {
f8a57be8 12840 rtx set;
f676971a 12841
9ebbca7d 12842 cr_save_rtx = gen_rtx_REG (SImode, 12);
f8a57be8
GK		 12843 insn = emit_insn (gen_movesi_from_cr (cr_save_rtx));
12844 RTX_FRAME_RELATED_P (insn) = 1;
12845 /* Now, there's no way that dwarf2out_frame_debug_expr is going
12846 to understand '(unspec:SI [(reg:CC 68) ...] UNSPEC_MOVESI_FROM_CR)'.
12847 But that's OK. All we have to do is specify that _one_ condition
12848 code register is saved in this stack slot. The thrower's epilogue
12849 will then restore all the call-saved registers.
12850 We use CR2_REGNO (70) to be compatible with gcc-2.95 on Linux. */
12851 set = gen_rtx_SET (VOIDmode, cr_save_rtx,
12852 gen_rtx_REG (SImode, CR2_REGNO));
12853 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
12854 set,
12855 REG_NOTES (insn));
9ebbca7d
GK		 12856 }
12857
a4f6c312
SS		 12858 /* Do any required saving of fpr's. If only one or two to save, do
12859 it ourselves. Otherwise, call function. */
f57fe068 12860 if (!WORLD_SAVE_P (info) && saving_FPRs_inline)
9ebbca7d
GK		 12861 {
12862 int i;
12863 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
f676971a 12864 if ((regs_ever_live[info->first_fp_reg_save+i]
9ebbca7d 12865 && ! call_used_regs[info->first_fp_reg_save+i]))
89e7058f
AH		 12866 emit_frame_save (frame_reg_rtx, frame_ptr_rtx, DFmode,
12867 info->first_fp_reg_save + i,
12868 info->fp_save_offset + sp_offset + 8 * i,
12869 info->total_size);
9ebbca7d 12870 }
f57fe068 12871 else if (!WORLD_SAVE_P (info) && info->first_fp_reg_save != 64)
9ebbca7d
GK		 12872 {
12873 int i;
12874 char rname[30];
520a57c8 12875 const char *alloc_rname;
9ebbca7d
GK		 12876 rtvec p;
12877 p = rtvec_alloc (2 + 64 - info->first_fp_reg_save);
f676971a
EC		 12878
12879 RTVEC_ELT (p, 0) = gen_rtx_CLOBBER (VOIDmode,
12880 gen_rtx_REG (Pmode,
9ebbca7d
GK		 12881 LINK_REGISTER_REGNUM));
12882 sprintf (rname, "%s%d%s", SAVE_FP_PREFIX,
12883 info->first_fp_reg_save - 32, SAVE_FP_SUFFIX);
a8a05998 12884 alloc_rname = ggc_strdup (rname);
9ebbca7d
GK		 12885 RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode,
12886 gen_rtx_SYMBOL_REF (Pmode,
12887 alloc_rname));
12888 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
12889 {
12890 rtx addr, reg, mem;
12891 reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i);
12892 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
f676971a 12893 GEN_INT (info->fp_save_offset
9ebbca7d
GK		 12894 + sp_offset + 8*i));
12895 mem = gen_rtx_MEM (DFmode, addr);
ba4828e0 12896 set_mem_alias_set (mem, rs6000_sr_alias_set);
9ebbca7d
GK		 12897
12898 RTVEC_ELT (p, i + 2) = gen_rtx_SET (VOIDmode, mem, reg);
12899 }
12900 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
f676971a 12901 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
9ebbca7d
GK		 12902 NULL_RTX, NULL_RTX);
12903 }
b6c9286a 12904
9ebbca7d
GK		 12905 /* Save GPRs. This is done as a PARALLEL if we are using
12906 the store-multiple instructions. */
f57fe068 12907 if (!WORLD_SAVE_P (info) && using_store_multiple)
b6c9286a 12908 {
308c142a 12909 rtvec p;
9ebbca7d
GK		 12910 int i;
12911 p = rtvec_alloc (32 - info->first_gp_reg_save);
9ebbca7d
GK		 12912 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
12913 {
12914 rtx addr, reg, mem;
12915 reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
f676971a
EC		 12916 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
12917 GEN_INT (info->gp_save_offset
12918 + sp_offset
9ebbca7d
GK		 12919 + reg_size * i));
12920 mem = gen_rtx_MEM (reg_mode, addr);
ba4828e0 12921 set_mem_alias_set (mem, rs6000_sr_alias_set);
9ebbca7d
GK		 12922
12923 RTVEC_ELT (p, i) = gen_rtx_SET (VOIDmode, mem, reg);
12924 }
12925 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
f676971a 12926 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
9ebbca7d 12927 NULL_RTX, NULL_RTX);
b6c9286a 12928 }
f57fe068 12929 else if (!WORLD_SAVE_P (info))
b6c9286a 12930 {
9ebbca7d
GK		 12931 int i;
12932 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
f676971a 12933 if ((regs_ever_live[info->first_gp_reg_save+i]
b4db40bf
JJ		 12934 && (! call_used_regs[info->first_gp_reg_save+i]
12935 || (i+info->first_gp_reg_save
12936 == RS6000_PIC_OFFSET_TABLE_REGNUM
12937 && TARGET_TOC && TARGET_MINIMAL_TOC)))
1db02437 12938 || (i+info->first_gp_reg_save == RS6000_PIC_OFFSET_TABLE_REGNUM
14f00213 12939 && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0)
f607bc57 12940 || (DEFAULT_ABI == ABI_DARWIN && flag_pic))))
a3170dc6
AH		 12941 {
12942 rtx addr, reg, mem;
12943 reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
12944
c19de7aa 12945 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
a3170dc6
AH		 12946 {
12947 int offset = info->spe_gp_save_offset + sp_offset + 8 * i;
12948 rtx b;
12949
12950 if (!SPE_CONST_OFFSET_OK (offset))
12951 {
12952 b = gen_rtx_REG (Pmode, FIXED_SCRATCH);
12953 emit_move_insn (b, GEN_INT (offset));
12954 }
12955 else
12956 b = GEN_INT (offset);
12957
12958 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, b);
12959 mem = gen_rtx_MEM (V2SImode, addr);
12960 set_mem_alias_set (mem, rs6000_sr_alias_set);
12961 insn = emit_move_insn (mem, reg);
12962
12963 if (GET_CODE (b) == CONST_INT)
12964 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
12965 NULL_RTX, NULL_RTX);
12966 else
12967 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
12968 b, GEN_INT (offset));
12969 }
12970 else
12971 {
f676971a
EC		 12972 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
12973 GEN_INT (info->gp_save_offset
12974 + sp_offset
a3170dc6
AH		 12975 + reg_size * i));
12976 mem = gen_rtx_MEM (reg_mode, addr);
12977 set_mem_alias_set (mem, rs6000_sr_alias_set);
12978
12979 insn = emit_move_insn (mem, reg);
f676971a 12980 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
a3170dc6
AH		 12981 NULL_RTX, NULL_RTX);
12982 }
12983 }
9ebbca7d
GK		 12984 }
12985
83720594
RH		 12986 /* ??? There's no need to emit actual instructions here, but it's the
12987 easiest way to get the frame unwind information emitted. */
f57fe068 12988 if (!WORLD_SAVE_P (info) && current_function_calls_eh_return)
83720594 12989 {
78e1b90d
DE		 12990 unsigned int i, regno;
12991
fc4767bb
JJ		 12992 /* In AIX ABI we need to pretend we save r2 here. */
12993 if (TARGET_AIX)
12994 {
12995 rtx addr, reg, mem;
12996
12997 reg = gen_rtx_REG (reg_mode, 2);
12998 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
12999 GEN_INT (sp_offset + 5 * reg_size));
13000 mem = gen_rtx_MEM (reg_mode, addr);
13001 set_mem_alias_set (mem, rs6000_sr_alias_set);
13002
13003 insn = emit_move_insn (mem, reg);
f676971a 13004 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
fc4767bb
JJ		 13005 NULL_RTX, NULL_RTX);
13006 PATTERN (insn) = gen_blockage ();
13007 }
13008
83720594
RH		 13009 for (i = 0; ; ++i)
13010 {
83720594
RH		 13011 regno = EH_RETURN_DATA_REGNO (i);
13012 if (regno == INVALID_REGNUM)
13013 break;
13014
89e7058f
AH		 13015 emit_frame_save (frame_reg_rtx, frame_ptr_rtx, reg_mode, regno,
13016 info->ehrd_offset + sp_offset
13017 + reg_size * (int) i,
13018 info->total_size);
83720594
RH		 13019 }
13020 }
13021
9ebbca7d 13022 /* Save lr if we used it. */
f57fe068 13023 if (!WORLD_SAVE_P (info) && info->lr_save_p)
9ebbca7d
GK		 13024 {
13025 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13026 GEN_INT (info->lr_save_offset + sp_offset));
13027 rtx reg = gen_rtx_REG (Pmode, 0);
13028 rtx mem = gen_rtx_MEM (Pmode, addr);
13029 /* This should not be of rs6000_sr_alias_set, because of
13030 __builtin_return_address. */
f676971a 13031
9ebbca7d 13032 insn = emit_move_insn (mem, reg);
f676971a 13033 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
f8a57be8 13034 NULL_RTX, NULL_RTX);
9ebbca7d
GK		 13035 }
13036
13037 /* Save CR if we use any that must be preserved. */
f57fe068 13038 if (!WORLD_SAVE_P (info) && info->cr_save_p)
9ebbca7d
GK		 13039 {
13040 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13041 GEN_INT (info->cr_save_offset + sp_offset));
13042 rtx mem = gen_rtx_MEM (SImode, addr);
f8a57be8
GK		 13043 /* See the large comment above about why CR2_REGNO is used. */
13044 rtx magic_eh_cr_reg = gen_rtx_REG (SImode, CR2_REGNO);
ba4828e0
RK		 13045
13046 set_mem_alias_set (mem, rs6000_sr_alias_set);
9ebbca7d
GK		 13047
13048 /* If r12 was used to hold the original sp, copy cr into r0 now
13049 that it's free. */
13050 if (REGNO (frame_reg_rtx) == 12)
13051 {
f8a57be8
GK		 13052 rtx set;
13053
9ebbca7d 13054 cr_save_rtx = gen_rtx_REG (SImode, 0);
f8a57be8
GK		 13055 insn = emit_insn (gen_movesi_from_cr (cr_save_rtx));
13056 RTX_FRAME_RELATED_P (insn) = 1;
13057 set = gen_rtx_SET (VOIDmode, cr_save_rtx, magic_eh_cr_reg);
13058 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
13059 set,
13060 REG_NOTES (insn));
f676971a 13061
9ebbca7d
GK		 13062 }
13063 insn = emit_move_insn (mem, cr_save_rtx);
13064
f676971a 13065 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
f8a57be8 13066 NULL_RTX, NULL_RTX);
9ebbca7d
GK		 13067 }
13068
f676971a 13069 /* Update stack and set back pointer unless this is V.4,
9ebbca7d 13070 for which it was done previously. */
f57fe068 13071 if (!WORLD_SAVE_P (info) && info->push_p
fc4767bb 13072 && !(DEFAULT_ABI == ABI_V4 || current_function_calls_eh_return))
9ebbca7d
GK		 13073 rs6000_emit_allocate_stack (info->total_size, FALSE);
13074
13075 /* Set frame pointer, if needed. */
13076 if (frame_pointer_needed)
13077 {
f676971a 13078 insn = emit_move_insn (gen_rtx_REG (Pmode, FRAME_POINTER_REGNUM),
9ebbca7d
GK		 13079 sp_reg_rtx);
13080 RTX_FRAME_RELATED_P (insn) = 1;
b6c9286a 13081 }
9878760c 13082
1db02437 13083 /* If we are using RS6000_PIC_OFFSET_TABLE_REGNUM, we need to set it up. */
9ebbca7d 13084 if ((TARGET_TOC && TARGET_MINIMAL_TOC && get_pool_size () != 0)
f607bc57 13085 || (DEFAULT_ABI == ABI_V4 && flag_pic == 1
1db02437 13086 && regs_ever_live[RS6000_PIC_OFFSET_TABLE_REGNUM]))
c4ad648e
AM		 13087 {
13088 /* If emit_load_toc_table will use the link register, we need to save
13089 it. We use R12 for this purpose because emit_load_toc_table
13090 can use register 0. This allows us to use a plain 'blr' to return
13091 from the procedure more often. */
13092 int save_LR_around_toc_setup = (TARGET_ELF
13093 && DEFAULT_ABI != ABI_AIX
13094 && flag_pic
13095 && ! info->lr_save_p
13096 && EDGE_COUNT (EXIT_BLOCK_PTR->preds) > 0);
13097 if (save_LR_around_toc_setup)
13098 {
13099 rtx lr = gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM);
f8a57be8 13100
c4ad648e
AM		 13101 insn = emit_move_insn (frame_ptr_rtx, lr);
13102 rs6000_maybe_dead (insn);
13103 RTX_FRAME_RELATED_P (insn) = 1;
f8a57be8 13104
c4ad648e 13105 rs6000_emit_load_toc_table (TRUE);
f8a57be8 13106
c4ad648e
AM		 13107 insn = emit_move_insn (lr, frame_ptr_rtx);
13108 rs6000_maybe_dead (insn);
13109 RTX_FRAME_RELATED_P (insn) = 1;
13110 }
13111 else
13112 rs6000_emit_load_toc_table (TRUE);
13113 }
ee890fe2 13114
fcce224d 13115#if TARGET_MACHO
ee890fe2
SS		 13116 if (DEFAULT_ABI == ABI_DARWIN
13117 && flag_pic && current_function_uses_pic_offset_table)
13118 {
f8a57be8 13119 rtx lr = gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM);
11abc112 13120 rtx src = machopic_function_base_sym ();
ee890fe2 13121
f8a57be8 13122 rs6000_maybe_dead (emit_insn (gen_load_macho_picbase (lr, src)));
ee890fe2 13123
f676971a 13124 insn = emit_move_insn (gen_rtx_REG (Pmode,
f8a57be8
GK		 13125 RS6000_PIC_OFFSET_TABLE_REGNUM),
13126 lr);
13127 rs6000_maybe_dead (insn);
ee890fe2 13128 }
fcce224d 13129#endif
9ebbca7d
GK		 13130}
13131
9ebbca7d 13132/* Write function prologue. */
a4f6c312 13133
08c148a8 13134static void
f676971a 13135rs6000_output_function_prologue (FILE *file,
a2369ed3 13136 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
9ebbca7d
GK		 13137{
13138 rs6000_stack_t *info = rs6000_stack_info ();
13139
4697a36c
MM		 13140 if (TARGET_DEBUG_STACK)
13141 debug_stack_info (info);
9878760c 13142
a4f6c312
SS		 13143 /* Write .extern for any function we will call to save and restore
13144 fp values. */
13145 if (info->first_fp_reg_save < 64
13146 && !FP_SAVE_INLINE (info->first_fp_reg_save))
4d30c363 13147 fprintf (file, "\t.extern %s%d%s\n\t.extern %s%d%s\n",
4697a36c 13148 SAVE_FP_PREFIX, info->first_fp_reg_save - 32, SAVE_FP_SUFFIX,
a4f6c312
SS		 13149 RESTORE_FP_PREFIX, info->first_fp_reg_save - 32,
13150 RESTORE_FP_SUFFIX);
9878760c 13151
c764f757
RK		 13152 /* Write .extern for AIX common mode routines, if needed. */
13153 if (! TARGET_POWER && ! TARGET_POWERPC && ! common_mode_defined)
13154 {
f6709c70
JW		 13155 fputs ("\t.extern __mulh\n", file);
13156 fputs ("\t.extern __mull\n", file);
13157 fputs ("\t.extern __divss\n", file);
13158 fputs ("\t.extern __divus\n", file);
13159 fputs ("\t.extern __quoss\n", file);
13160 fputs ("\t.extern __quous\n", file);
c764f757
RK		 13161 common_mode_defined = 1;
13162 }
9878760c 13163
9ebbca7d 13164 if (! HAVE_prologue)
979721f8 13165 {
9ebbca7d 13166 start_sequence ();
9dda4cc8 13167
a4f6c312
SS		 13168 /* A NOTE_INSN_DELETED is supposed to be at the start and end of
13169 the "toplevel" insn chain. */
2e040219 13170 emit_note (NOTE_INSN_DELETED);
9ebbca7d 13171 rs6000_emit_prologue ();
2e040219 13172 emit_note (NOTE_INSN_DELETED);
178c3eff 13173
a3c9585f 13174 /* Expand INSN_ADDRESSES so final() doesn't crash. */
178c3eff
DJ		 13175 {
13176 rtx insn;
13177 unsigned addr = 0;
13178 for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
13179 {
13180 INSN_ADDRESSES_NEW (insn, addr);
13181 addr += 4;
13182 }
13183 }
9dda4cc8 13184
9ebbca7d 13185 if (TARGET_DEBUG_STACK)
a4f6c312
SS		 13186 debug_rtx_list (get_insns (), 100);
13187 final (get_insns (), file, FALSE, FALSE);
9ebbca7d 13188 end_sequence ();
979721f8
MM		 13189 }
13190
9ebbca7d
GK		 13191 rs6000_pic_labelno++;
13192}
f676971a 13193
9ebbca7d 13194/* Emit function epilogue as insns.
9878760c 13195
9ebbca7d
GK		 13196 At present, dwarf2out_frame_debug_expr doesn't understand
13197 register restores, so we don't bother setting RTX_FRAME_RELATED_P
13198 anywhere in the epilogue. Most of the insns below would in any case
13199 need special notes to explain where r11 is in relation to the stack. */
9878760c 13200
9ebbca7d 13201void
a2369ed3 13202rs6000_emit_epilogue (int sibcall)
9ebbca7d
GK		 13203{
13204 rs6000_stack_t *info;
13205 int restoring_FPRs_inline;
13206 int using_load_multiple;
13207 int using_mfcr_multiple;
13208 int use_backchain_to_restore_sp;
13209 int sp_offset = 0;
13210 rtx sp_reg_rtx = gen_rtx_REG (Pmode, 1);
13211 rtx frame_reg_rtx = sp_reg_rtx;
0e67400a 13212 enum machine_mode reg_mode = Pmode;
327e5343 13213 int reg_size = TARGET_32BIT ? 4 : 8;
9ebbca7d
GK		 13214 int i;
13215
c19de7aa
AH		 13216 info = rs6000_stack_info ();
13217
13218 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
a3170dc6
AH		 13219 {
13220 reg_mode = V2SImode;
13221 reg_size = 8;
13222 }
13223
9ebbca7d 13224 using_load_multiple = (TARGET_MULTIPLE && ! TARGET_POWERPC64
c19de7aa
AH		 13225 && (!TARGET_SPE_ABI
13226 || info->spe_64bit_regs_used == 0)
9ebbca7d
GK		 13227 && info->first_gp_reg_save < 31);
13228 restoring_FPRs_inline = (sibcall
83720594 13229 || current_function_calls_eh_return
9ebbca7d
GK		 13230 || info->first_fp_reg_save == 64
13231 || FP_SAVE_INLINE (info->first_fp_reg_save));
f676971a 13232 use_backchain_to_restore_sp = (frame_pointer_needed
9ebbca7d
GK		 13233 || current_function_calls_alloca
13234 || info->total_size > 32767);
13235 using_mfcr_multiple = (rs6000_cpu == PROCESSOR_PPC601
13236 || rs6000_cpu == PROCESSOR_PPC603
13237 || rs6000_cpu == PROCESSOR_PPC750
13238 || optimize_size);
13239
f57fe068 13240 if (WORLD_SAVE_P (info))
d62294f5
FJ		 13241 {
13242 int i, j;
13243 char rname[30];
13244 const char *alloc_rname;
13245 rtvec p;
13246
13247 /* eh_rest_world_r10 will return to the location saved in the LR
c4ad648e
AM		 13248 stack slot (which is not likely to be our caller.)
13249 Input: R10 -- stack adjustment. Clobbers R0, R11, R12, R7, R8.
13250 rest_world is similar, except any R10 parameter is ignored.
13251 The exception-handling stuff that was here in 2.95 is no
13252 longer necessary. */
d62294f5
FJ		 13253
13254 p = rtvec_alloc (9
13255 + 1
f676971a 13256 + 32 - info->first_gp_reg_save
c4ad648e
AM		 13257 + LAST_ALTIVEC_REGNO + 1 - info->first_altivec_reg_save
13258 + 63 + 1 - info->first_fp_reg_save);
d62294f5 13259
c4ad648e
AM		 13260 strcpy (rname, ((current_function_calls_eh_return) ?
13261 "*eh_rest_world_r10" : "*rest_world"));
d62294f5
FJ		 13262 alloc_rname = ggc_strdup (rname);
13263
13264 j = 0;
13265 RTVEC_ELT (p, j++) = gen_rtx_RETURN (VOIDmode);
13266 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode,
c4ad648e
AM		 13267 gen_rtx_REG (Pmode,
13268 LINK_REGISTER_REGNUM));
d62294f5 13269 RTVEC_ELT (p, j++)
c4ad648e 13270 = gen_rtx_USE (VOIDmode, gen_rtx_SYMBOL_REF (Pmode, alloc_rname));
d62294f5 13271 /* The instruction pattern requires a clobber here;
c4ad648e 13272 it is shared with the restVEC helper. */
d62294f5 13273 RTVEC_ELT (p, j++)
c4ad648e 13274 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 11));
d62294f5
FJ		 13275
13276 {
c4ad648e
AM		 13277 /* CR register traditionally saved as CR2. */
13278 rtx reg = gen_rtx_REG (reg_mode, CR2_REGNO);
13279 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13280 GEN_INT (info->cr_save_offset));
13281 rtx mem = gen_rtx_MEM (reg_mode, addr);
13282 set_mem_alias_set (mem, rs6000_sr_alias_set);
13283
13284 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
d62294f5
FJ		 13285 }
13286
13287 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
c4ad648e
AM		 13288 {
13289 rtx reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
13290 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13291 GEN_INT (info->gp_save_offset
13292 + reg_size * i));
13293 rtx mem = gen_rtx_MEM (reg_mode, addr);
13294 set_mem_alias_set (mem, rs6000_sr_alias_set);
13295
13296 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
13297 }
d62294f5 13298 for (i = 0; info->first_altivec_reg_save + i <= LAST_ALTIVEC_REGNO; i++)
c4ad648e
AM		 13299 {
13300 rtx reg = gen_rtx_REG (V4SImode, info->first_altivec_reg_save + i);
13301 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13302 GEN_INT (info->altivec_save_offset
13303 + 16 * i));
13304 rtx mem = gen_rtx_MEM (V4SImode, addr);
13305 set_mem_alias_set (mem, rs6000_sr_alias_set);
13306
13307 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
13308 }
d62294f5 13309 for (i = 0; info->first_fp_reg_save + i <= 63; i++)
c4ad648e
AM		 13310 {
13311 rtx reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i);
13312 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13313 GEN_INT (info->fp_save_offset
13314 + 8 * i));
13315 rtx mem = gen_rtx_MEM (DFmode, addr);
13316 set_mem_alias_set (mem, rs6000_sr_alias_set);
13317
13318 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
13319 }
d62294f5 13320 RTVEC_ELT (p, j++)
c4ad648e 13321 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 0));
d62294f5 13322 RTVEC_ELT (p, j++)
c4ad648e 13323 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 12));
d62294f5 13324 RTVEC_ELT (p, j++)
c4ad648e 13325 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 7));
d62294f5 13326 RTVEC_ELT (p, j++)
c4ad648e 13327 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 8));
d62294f5 13328 RTVEC_ELT (p, j++)
c4ad648e 13329 = gen_rtx_USE (VOIDmode, gen_rtx_REG (SImode, 10));
d62294f5
FJ		 13330 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
13331
13332 return;
13333 }
13334
9ebbca7d
GK		 13335 /* If we have a frame pointer, a call to alloca, or a large stack
13336 frame, restore the old stack pointer using the backchain. Otherwise,
13337 we know what size to update it with. */
13338 if (use_backchain_to_restore_sp)
bacbde18 13339 {
9ebbca7d
GK		 13340 /* Under V.4, don't reset the stack pointer until after we're done
13341 loading the saved registers. */
f607bc57 13342 if (DEFAULT_ABI == ABI_V4)
9ebbca7d 13343 frame_reg_rtx = gen_rtx_REG (Pmode, 11);
4697a36c 13344
9ebbca7d
GK		 13345 emit_move_insn (frame_reg_rtx,
13346 gen_rtx_MEM (Pmode, sp_reg_rtx));
f676971a 13347
bacbde18 13348 }
9ebbca7d 13349 else if (info->push_p)
85638c0d 13350 {
fc4767bb
JJ		 13351 if (DEFAULT_ABI == ABI_V4
13352 || current_function_calls_eh_return)
9ebbca7d
GK		 13353 sp_offset = info->total_size;
13354 else
13355 {
13356 emit_insn (TARGET_32BIT
13357 ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx,
13358 GEN_INT (info->total_size))
13359 : gen_adddi3 (sp_reg_rtx, sp_reg_rtx,
13360 GEN_INT (info->total_size)));
13361 }
85638c0d 13362 }
f676971a 13363
9aa86737
AH		 13364 /* Restore AltiVec registers if needed. */
13365 if (TARGET_ALTIVEC_ABI && info->altivec_size != 0)
13366 {
13367 int i;
13368
13369 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
13370 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
13371 {
13372 rtx addr, areg, mem;
13373
13374 areg = gen_rtx_REG (Pmode, 0);
13375 emit_move_insn
13376 (areg, GEN_INT (info->altivec_save_offset
13377 + sp_offset
13378 + 16 * (i - info->first_altivec_reg_save)));
13379
13380 /* AltiVec addressing mode is [reg+reg]. */
13381 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, areg);
13382 mem = gen_rtx_MEM (V4SImode, addr);
13383 set_mem_alias_set (mem, rs6000_sr_alias_set);
13384
13385 emit_move_insn (gen_rtx_REG (V4SImode, i), mem);
13386 }
13387 }
13388
13389 /* Restore VRSAVE if needed. */
44688022 13390 if (TARGET_ALTIVEC && TARGET_ALTIVEC_VRSAVE
4d774ff8 13391 && info->vrsave_mask != 0)
9aa86737
AH		 13392 {
13393 rtx addr, mem, reg;
13394
13395 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13396 GEN_INT (info->vrsave_save_offset + sp_offset));
13397 mem = gen_rtx_MEM (SImode, addr);
13398 set_mem_alias_set (mem, rs6000_sr_alias_set);
13399 reg = gen_rtx_REG (SImode, 12);
13400 emit_move_insn (reg, mem);
13401
13402 emit_insn (generate_set_vrsave (reg, info, 1));
13403 }
13404
9ebbca7d
GK		 13405 /* Get the old lr if we saved it. */
13406 if (info->lr_save_p)
b6c9286a 13407 {
a3170dc6
AH		 13408 rtx mem = gen_frame_mem_offset (Pmode, frame_reg_rtx,
13409 info->lr_save_offset + sp_offset);
ba4828e0
RK		 13410
13411 set_mem_alias_set (mem, rs6000_sr_alias_set);
b6c9286a 13412
9ebbca7d 13413 emit_move_insn (gen_rtx_REG (Pmode, 0), mem);
b6c9286a 13414 }
f676971a 13415
9ebbca7d
GK		 13416 /* Get the old cr if we saved it. */
13417 if (info->cr_save_p)
13418 {
13419 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13420 GEN_INT (info->cr_save_offset + sp_offset));
13421 rtx mem = gen_rtx_MEM (SImode, addr);
ba4828e0
RK		 13422
13423 set_mem_alias_set (mem, rs6000_sr_alias_set);
b6c9286a 13424
9ebbca7d
GK		 13425 emit_move_insn (gen_rtx_REG (SImode, 12), mem);
13426 }
f676971a 13427
9ebbca7d 13428 /* Set LR here to try to overlap restores below. */
4697a36c 13429 if (info->lr_save_p)
9ebbca7d
GK		 13430 emit_move_insn (gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM),
13431 gen_rtx_REG (Pmode, 0));
f676971a 13432
83720594
RH		 13433 /* Load exception handler data registers, if needed. */
13434 if (current_function_calls_eh_return)
13435 {
78e1b90d
DE		 13436 unsigned int i, regno;
13437
fc4767bb
JJ		 13438 if (TARGET_AIX)
13439 {
13440 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13441 GEN_INT (sp_offset + 5 * reg_size));
13442 rtx mem = gen_rtx_MEM (reg_mode, addr);
13443
13444 set_mem_alias_set (mem, rs6000_sr_alias_set);
13445
13446 emit_move_insn (gen_rtx_REG (reg_mode, 2), mem);
13447 }
13448
83720594
RH		 13449 for (i = 0; ; ++i)
13450 {
a3170dc6 13451 rtx mem;
83720594
RH		 13452
13453 regno = EH_RETURN_DATA_REGNO (i);
13454 if (regno == INVALID_REGNUM)
13455 break;
13456
a3170dc6
AH		 13457 mem = gen_frame_mem_offset (reg_mode, frame_reg_rtx,
13458 info->ehrd_offset + sp_offset
13459 + reg_size * (int) i);
ba4828e0 13460 set_mem_alias_set (mem, rs6000_sr_alias_set);
83720594
RH		 13461
13462 emit_move_insn (gen_rtx_REG (reg_mode, regno), mem);
13463 }
13464 }
f676971a 13465
9ebbca7d
GK		 13466 /* Restore GPRs. This is done as a PARALLEL if we are using
13467 the load-multiple instructions. */
13468 if (using_load_multiple)
979721f8 13469 {
9ebbca7d
GK		 13470 rtvec p;
13471 p = rtvec_alloc (32 - info->first_gp_reg_save);
13472 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
979721f8 13473 {
f676971a
EC		 13474 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13475 GEN_INT (info->gp_save_offset
13476 + sp_offset
9ebbca7d
GK		 13477 + reg_size * i));
13478 rtx mem = gen_rtx_MEM (reg_mode, addr);
ba4828e0
RK		 13479
13480 set_mem_alias_set (mem, rs6000_sr_alias_set);
9ebbca7d 13481
f676971a 13482 RTVEC_ELT (p, i) =
9ebbca7d
GK		 13483 gen_rtx_SET (VOIDmode,
13484 gen_rtx_REG (reg_mode, info->first_gp_reg_save + i),
13485 mem);
979721f8 13486 }
9ebbca7d 13487 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
979721f8 13488 }
9ebbca7d
GK		 13489 else
13490 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
f676971a 13491 if ((regs_ever_live[info->first_gp_reg_save+i]
b4db40bf
JJ		 13492 && (! call_used_regs[info->first_gp_reg_save+i]
13493 || (i+info->first_gp_reg_save == RS6000_PIC_OFFSET_TABLE_REGNUM
13494 && TARGET_TOC && TARGET_MINIMAL_TOC)))
1db02437 13495 || (i+info->first_gp_reg_save == RS6000_PIC_OFFSET_TABLE_REGNUM
14f00213 13496 && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0)
f607bc57 13497 || (DEFAULT_ABI == ABI_DARWIN && flag_pic))))
9ebbca7d 13498 {
f676971a
EC		 13499 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13500 GEN_INT (info->gp_save_offset
13501 + sp_offset
9ebbca7d
GK		 13502 + reg_size * i));
13503 rtx mem = gen_rtx_MEM (reg_mode, addr);
ba4828e0 13504
a3170dc6 13505 /* Restore 64-bit quantities for SPE. */
c19de7aa 13506 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
a3170dc6
AH		 13507 {
13508 int offset = info->spe_gp_save_offset + sp_offset + 8 * i;
13509 rtx b;
13510
13511 if (!SPE_CONST_OFFSET_OK (offset))
13512 {
13513 b = gen_rtx_REG (Pmode, FIXED_SCRATCH);
13514 emit_move_insn (b, GEN_INT (offset));
13515 }
13516 else
13517 b = GEN_INT (offset);
13518
13519 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, b);
13520 mem = gen_rtx_MEM (V2SImode, addr);
13521 }
13522
ba4828e0 13523 set_mem_alias_set (mem, rs6000_sr_alias_set);
9ebbca7d 13524
f676971a 13525 emit_move_insn (gen_rtx_REG (reg_mode,
a3170dc6 13526 info->first_gp_reg_save + i), mem);
9ebbca7d 13527 }
9878760c 13528
9ebbca7d
GK		 13529 /* Restore fpr's if we need to do it without calling a function. */
13530 if (restoring_FPRs_inline)
13531 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
f676971a 13532 if ((regs_ever_live[info->first_fp_reg_save+i]
9ebbca7d
GK		 13533 && ! call_used_regs[info->first_fp_reg_save+i]))
13534 {
13535 rtx addr, mem;
13536 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
f676971a
EC		 13537 GEN_INT (info->fp_save_offset
13538 + sp_offset
a4f6c312 13539 + 8 * i));
9ebbca7d 13540 mem = gen_rtx_MEM (DFmode, addr);
ba4828e0 13541 set_mem_alias_set (mem, rs6000_sr_alias_set);
9ebbca7d 13542
f676971a 13543 emit_move_insn (gen_rtx_REG (DFmode,
9ebbca7d
GK		 13544 info->first_fp_reg_save + i),
13545 mem);
13546 }
8d30c4ee 13547
9ebbca7d
GK		 13548 /* If we saved cr, restore it here. Just those that were used. */
13549 if (info->cr_save_p)
979721f8 13550 {
9ebbca7d 13551 rtx r12_rtx = gen_rtx_REG (SImode, 12);
e35b9579 13552 int count = 0;
f676971a 13553
9ebbca7d 13554 if (using_mfcr_multiple)
979721f8 13555 {
9ebbca7d
GK		 13556 for (i = 0; i < 8; i++)
13557 if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i])
e35b9579 13558 count++;
9ebbca7d 13559 if (count == 0)
e35b9579
GK		 13560 abort ();
13561 }
13562
13563 if (using_mfcr_multiple && count > 1)
13564 {
13565 rtvec p;
13566 int ndx;
f676971a 13567
e35b9579 13568 p = rtvec_alloc (count);
9ebbca7d 13569
e35b9579 13570 ndx = 0;
9ebbca7d
GK		 13571 for (i = 0; i < 8; i++)
13572 if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i])
13573 {
13574 rtvec r = rtvec_alloc (2);
13575 RTVEC_ELT (r, 0) = r12_rtx;
13576 RTVEC_ELT (r, 1) = GEN_INT (1 << (7-i));
e35b9579 13577 RTVEC_ELT (p, ndx) =
f676971a 13578 gen_rtx_SET (VOIDmode, gen_rtx_REG (CCmode, CR0_REGNO+i),
615158e2 13579 gen_rtx_UNSPEC (CCmode, r, UNSPEC_MOVESI_TO_CR));
e35b9579 13580 ndx++;
9ebbca7d
GK		 13581 }
13582 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
e35b9579
GK		 13583 if (ndx != count)
13584 abort ();
979721f8
MM		 13585 }
13586 else
9ebbca7d
GK		 13587 for (i = 0; i < 8; i++)
13588 if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i])
979721f8 13589 {
f676971a 13590 emit_insn (gen_movsi_to_cr_one (gen_rtx_REG (CCmode,
9ebbca7d
GK		 13591 CR0_REGNO+i),
13592 r12_rtx));
979721f8 13593 }
979721f8
MM		 13594 }
13595
9ebbca7d
GK		 13596 /* If this is V.4, unwind the stack pointer after all of the loads
13597 have been done. We need to emit a block here so that sched
13598 doesn't decide to move the sp change before the register restores
13599 (which may not have any obvious dependency on the stack). This
13600 doesn't hurt performance, because there is no scheduling that can
13601 be done after this point. */
fc4767bb
JJ		 13602 if (DEFAULT_ABI == ABI_V4
13603 || current_function_calls_eh_return)
b6c9286a 13604 {
9ebbca7d 13605 if (frame_reg_rtx != sp_reg_rtx)
c4ad648e 13606 rs6000_emit_stack_tie ();
b6c9286a 13607
9ebbca7d 13608 if (use_backchain_to_restore_sp)
b6c9286a 13609 {
9ebbca7d 13610 emit_move_insn (sp_reg_rtx, frame_reg_rtx);
b6c9286a 13611 }
9ebbca7d 13612 else if (sp_offset != 0)
13f1623b 13613 {
5b71a4e7 13614 emit_insn (TARGET_32BIT
9ebbca7d
GK		 13615 ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx,
13616 GEN_INT (sp_offset))
13617 : gen_adddi3 (sp_reg_rtx, sp_reg_rtx,
13618 GEN_INT (sp_offset)));
13f1623b 13619 }
9ebbca7d 13620 }
b6c9286a 13621
83720594
RH		 13622 if (current_function_calls_eh_return)
13623 {
13624 rtx sa = EH_RETURN_STACKADJ_RTX;
5b71a4e7 13625 emit_insn (TARGET_32BIT
83720594
RH		 13626 ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx, sa)
13627 : gen_adddi3 (sp_reg_rtx, sp_reg_rtx, sa));
13628 }
13629
9ebbca7d
GK		 13630 if (!sibcall)
13631 {
13632 rtvec p;
13633 if (! restoring_FPRs_inline)
13634 p = rtvec_alloc (3 + 64 - info->first_fp_reg_save);
13635 else
13636 p = rtvec_alloc (2);
b6c9286a 13637
e35b9579 13638 RTVEC_ELT (p, 0) = gen_rtx_RETURN (VOIDmode);
f676971a
EC		 13639 RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode,
13640 gen_rtx_REG (Pmode,
9ebbca7d 13641 LINK_REGISTER_REGNUM));
9ebbca7d
GK		 13642
13643 /* If we have to restore more than two FP registers, branch to the
13644 restore function. It will return to our caller. */
13645 if (! restoring_FPRs_inline)
13646 {
13647 int i;
13648 char rname[30];
520a57c8 13649 const char *alloc_rname;
979721f8 13650
f676971a 13651 sprintf (rname, "%s%d%s", RESTORE_FP_PREFIX,
9ebbca7d 13652 info->first_fp_reg_save - 32, RESTORE_FP_SUFFIX);
a8a05998 13653 alloc_rname = ggc_strdup (rname);
9ebbca7d
GK		 13654 RTVEC_ELT (p, 2) = gen_rtx_USE (VOIDmode,
13655 gen_rtx_SYMBOL_REF (Pmode,
13656 alloc_rname));
b6c9286a 13657
9ebbca7d
GK		 13658 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
13659 {
13660 rtx addr, mem;
13661 addr = gen_rtx_PLUS (Pmode, sp_reg_rtx,
13662 GEN_INT (info->fp_save_offset + 8*i));
13663 mem = gen_rtx_MEM (DFmode, addr);
ba4828e0 13664 set_mem_alias_set (mem, rs6000_sr_alias_set);
9ebbca7d 13665
f676971a 13666 RTVEC_ELT (p, i+3) =
9ebbca7d
GK		 13667 gen_rtx_SET (VOIDmode,
13668 gen_rtx_REG (DFmode, info->first_fp_reg_save + i),
13669 mem);
b6c9286a
MM		 13670 }
13671 }
f676971a 13672
9ebbca7d 13673 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
3daf36a4 13674 }
9878760c
RK		 13675}
13676
13677/* Write function epilogue. */
13678
08c148a8 13679static void
f676971a 13680rs6000_output_function_epilogue (FILE *file,
a2369ed3 13681 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
9878760c 13682{
4697a36c 13683 rs6000_stack_t *info = rs6000_stack_info ();
9878760c 13684
9ebbca7d 13685 if (! HAVE_epilogue)
9878760c 13686 {
9ebbca7d
GK		 13687 rtx insn = get_last_insn ();
13688 /* If the last insn was a BARRIER, we don't have to write anything except
13689 the trace table. */
13690 if (GET_CODE (insn) == NOTE)
13691 insn = prev_nonnote_insn (insn);
13692 if (insn == 0 || GET_CODE (insn) != BARRIER)
4697a36c 13693 {
9ebbca7d
GK		 13694 /* This is slightly ugly, but at least we don't have two
13695 copies of the epilogue-emitting code. */
13696 start_sequence ();
13697
13698 /* A NOTE_INSN_DELETED is supposed to be at the start
13699 and end of the "toplevel" insn chain. */
2e040219 13700 emit_note (NOTE_INSN_DELETED);
9ebbca7d 13701 rs6000_emit_epilogue (FALSE);
2e040219 13702 emit_note (NOTE_INSN_DELETED);
9ebbca7d 13703
a3c9585f 13704 /* Expand INSN_ADDRESSES so final() doesn't crash. */
178c3eff
DJ		 13705 {
13706 rtx insn;
13707 unsigned addr = 0;
13708 for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
13709 {
13710 INSN_ADDRESSES_NEW (insn, addr);
13711 addr += 4;
13712 }
13713 }
13714
9ebbca7d 13715 if (TARGET_DEBUG_STACK)
a4f6c312
SS		 13716 debug_rtx_list (get_insns (), 100);
13717 final (get_insns (), file, FALSE, FALSE);
9ebbca7d 13718 end_sequence ();
4697a36c 13719 }
9878760c 13720 }
b4ac57ab 13721
efdba735
SH		 13722#if TARGET_MACHO
13723 macho_branch_islands ();
0e5da0be
GK		 13724 /* Mach-O doesn't support labels at the end of objects, so if
13725 it looks like we might want one, insert a NOP. */
13726 {
13727 rtx insn = get_last_insn ();
13728 while (insn
13729 && NOTE_P (insn)
13730 && NOTE_LINE_NUMBER (insn) != NOTE_INSN_DELETED_LABEL)
13731 insn = PREV_INSN (insn);
f676971a
EC		 13732 if (insn
13733 && (LABEL_P (insn)
0e5da0be
GK		 13734 || (NOTE_P (insn)
13735 && NOTE_LINE_NUMBER (insn) == NOTE_INSN_DELETED_LABEL)))
13736 fputs ("\tnop\n", file);
13737 }
13738#endif
13739
9b30bae2 13740 /* Output a traceback table here. See /usr/include/sys/debug.h for info
314fc5a9
ILT		 13741 on its format.
13742
13743 We don't output a traceback table if -finhibit-size-directive was
13744 used. The documentation for -finhibit-size-directive reads
13745 ``don't output a @code{.size} assembler directive, or anything
13746 else that would cause trouble if the function is split in the
13747 middle, and the two halves are placed at locations far apart in
13748 memory.'' The traceback table has this property, since it
13749 includes the offset from the start of the function to the
4d30c363
MM		 13750 traceback table itself.
13751
13752 System V.4 Powerpc's (and the embedded ABI derived from it) use a
b6c9286a 13753 different traceback table. */
57ac7be9
AM		 13754 if (DEFAULT_ABI == ABI_AIX && ! flag_inhibit_size_directive
13755 && rs6000_traceback != traceback_none)
9b30bae2 13756 {
69c75916 13757 const char *fname = NULL;
3ac88239 13758 const char *language_string = lang_hooks.name;
6041bf2f 13759 int fixed_parms = 0, float_parms = 0, parm_info = 0;
314fc5a9 13760 int i;
57ac7be9
AM		 13761 int optional_tbtab;
13762
13763 if (rs6000_traceback == traceback_full)
13764 optional_tbtab = 1;
13765 else if (rs6000_traceback == traceback_part)
13766 optional_tbtab = 0;
13767 else
13768 optional_tbtab = !optimize_size && !TARGET_ELF;
314fc5a9 13769
69c75916
AM		 13770 if (optional_tbtab)
13771 {
13772 fname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
13773 while (*fname == '.') /* V.4 encodes . in the name */
13774 fname++;
13775
13776 /* Need label immediately before tbtab, so we can compute
13777 its offset from the function start. */
13778 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT");
13779 ASM_OUTPUT_LABEL (file, fname);
13780 }
314fc5a9
ILT		 13781
13782 /* The .tbtab pseudo-op can only be used for the first eight
13783 expressions, since it can't handle the possibly variable
13784 length fields that follow. However, if you omit the optional
13785 fields, the assembler outputs zeros for all optional fields
13786 anyways, giving each variable length field is minimum length
13787 (as defined in sys/debug.h). Thus we can not use the .tbtab
13788 pseudo-op at all. */
13789
13790 /* An all-zero word flags the start of the tbtab, for debuggers
13791 that have to find it by searching forward from the entry
13792 point or from the current pc. */
19d2d16f 13793 fputs ("\t.long 0\n", file);
314fc5a9
ILT		 13794
13795 /* Tbtab format type. Use format type 0. */
19d2d16f 13796 fputs ("\t.byte 0,", file);
314fc5a9 13797
5fc921c1
DE		 13798 /* Language type. Unfortunately, there does not seem to be any
13799 official way to discover the language being compiled, so we
13800 use language_string.
13801 C is 0. Fortran is 1. Pascal is 2. Ada is 3. C++ is 9.
13802 Java is 13. Objective-C is 14. */
13803 if (! strcmp (language_string, "GNU C"))
314fc5a9 13804 i = 0;
6de9cd9a
DN		 13805 else if (! strcmp (language_string, "GNU F77")
13806 || ! strcmp (language_string, "GNU F95"))
314fc5a9 13807 i = 1;
8b83775b 13808 else if (! strcmp (language_string, "GNU Pascal"))
314fc5a9 13809 i = 2;
5fc921c1
DE		 13810 else if (! strcmp (language_string, "GNU Ada"))
13811 i = 3;
314fc5a9
ILT		 13812 else if (! strcmp (language_string, "GNU C++"))
13813 i = 9;
9517ead8
AG		 13814 else if (! strcmp (language_string, "GNU Java"))
13815 i = 13;
5fc921c1
DE		 13816 else if (! strcmp (language_string, "GNU Objective-C"))
13817 i = 14;
314fc5a9
ILT		 13818 else
13819 abort ();
13820 fprintf (file, "%d,", i);
13821
13822 /* 8 single bit fields: global linkage (not set for C extern linkage,
13823 apparently a PL/I convention?), out-of-line epilogue/prologue, offset
13824 from start of procedure stored in tbtab, internal function, function
13825 has controlled storage, function has no toc, function uses fp,
13826 function logs/aborts fp operations. */
13827 /* Assume that fp operations are used if any fp reg must be saved. */
6041bf2f
DE		 13828 fprintf (file, "%d,",
13829 (optional_tbtab << 5) | ((info->first_fp_reg_save != 64) << 1));
314fc5a9
ILT		 13830
13831 /* 6 bitfields: function is interrupt handler, name present in
13832 proc table, function calls alloca, on condition directives
13833 (controls stack walks, 3 bits), saves condition reg, saves
13834 link reg. */
13835 /* The `function calls alloca' bit seems to be set whenever reg 31 is
13836 set up as a frame pointer, even when there is no alloca call. */
13837 fprintf (file, "%d,",
6041bf2f
DE		 13838 ((optional_tbtab << 6)
13839 | ((optional_tbtab & frame_pointer_needed) << 5)
13840 | (info->cr_save_p << 1)
13841 | (info->lr_save_p)));
314fc5a9 13842
6041bf2f 13843 /* 3 bitfields: saves backchain, fixup code, number of fpr saved
314fc5a9
ILT		 13844 (6 bits). */
13845 fprintf (file, "%d,",
4697a36c 13846 (info->push_p << 7) | (64 - info->first_fp_reg_save));
314fc5a9
ILT		 13847
13848 /* 2 bitfields: spare bits (2 bits), number of gpr saved (6 bits). */
13849 fprintf (file, "%d,", (32 - first_reg_to_save ()));
13850
6041bf2f
DE		 13851 if (optional_tbtab)
13852 {
13853 /* Compute the parameter info from the function decl argument
13854 list. */
13855 tree decl;
13856 int next_parm_info_bit = 31;
314fc5a9 13857
6041bf2f
DE		 13858 for (decl = DECL_ARGUMENTS (current_function_decl);
13859 decl; decl = TREE_CHAIN (decl))
13860 {
13861 rtx parameter = DECL_INCOMING_RTL (decl);
13862 enum machine_mode mode = GET_MODE (parameter);
314fc5a9 13863
6041bf2f
DE		 13864 if (GET_CODE (parameter) == REG)
13865 {
13866 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
13867 {
13868 int bits;
13869
13870 float_parms++;
13871
13872 if (mode == SFmode)
13873 bits = 0x2;
fcce224d 13874 else if (mode == DFmode || mode == TFmode)
6041bf2f
DE		 13875 bits = 0x3;
13876 else
13877 abort ();
13878
13879 /* If only one bit will fit, don't or in this entry. */
13880 if (next_parm_info_bit > 0)
13881 parm_info |= (bits << (next_parm_info_bit - 1));
13882 next_parm_info_bit -= 2;
13883 }
13884 else
13885 {
13886 fixed_parms += ((GET_MODE_SIZE (mode)
13887 + (UNITS_PER_WORD - 1))
13888 / UNITS_PER_WORD);
13889 next_parm_info_bit -= 1;
13890 }
13891 }
13892 }
13893 }
314fc5a9
ILT		 13894
13895 /* Number of fixed point parameters. */
13896 /* This is actually the number of words of fixed point parameters; thus
13897 an 8 byte struct counts as 2; and thus the maximum value is 8. */
13898 fprintf (file, "%d,", fixed_parms);
13899
13900 /* 2 bitfields: number of floating point parameters (7 bits), parameters
13901 all on stack. */
13902 /* This is actually the number of fp registers that hold parameters;
13903 and thus the maximum value is 13. */
13904 /* Set parameters on stack bit if parameters are not in their original
13905 registers, regardless of whether they are on the stack? Xlc
13906 seems to set the bit when not optimizing. */
13907 fprintf (file, "%d\n", ((float_parms << 1) | (! optimize)));
13908
6041bf2f
DE		 13909 if (! optional_tbtab)
13910 return;
13911
314fc5a9
ILT		 13912 /* Optional fields follow. Some are variable length. */
13913
13914 /* Parameter types, left adjusted bit fields: 0 fixed, 10 single float,
13915 11 double float. */
13916 /* There is an entry for each parameter in a register, in the order that
13917 they occur in the parameter list. Any intervening arguments on the
13918 stack are ignored. If the list overflows a long (max possible length
13919 34 bits) then completely leave off all elements that don't fit. */
13920 /* Only emit this long if there was at least one parameter. */
13921 if (fixed_parms || float_parms)
13922 fprintf (file, "\t.long %d\n", parm_info);
13923
13924 /* Offset from start of code to tb table. */
19d2d16f 13925 fputs ("\t.long ", file);
314fc5a9 13926 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT");
85b776df
AM		 13927 if (TARGET_AIX)
13928 RS6000_OUTPUT_BASENAME (file, fname);
13929 else
13930 assemble_name (file, fname);
13931 putc ('-', file);
13932 rs6000_output_function_entry (file, fname);
19d2d16f 13933 putc ('\n', file);
314fc5a9
ILT		 13934
13935 /* Interrupt handler mask. */
13936 /* Omit this long, since we never set the interrupt handler bit
13937 above. */
13938
13939 /* Number of CTL (controlled storage) anchors. */
13940 /* Omit this long, since the has_ctl bit is never set above. */
13941
13942 /* Displacement into stack of each CTL anchor. */
13943 /* Omit this list of longs, because there are no CTL anchors. */
13944
13945 /* Length of function name. */
69c75916
AM		 13946 if (*fname == '*')
13947 ++fname;
296b8152 13948 fprintf (file, "\t.short %d\n", (int) strlen (fname));
314fc5a9
ILT		 13949
13950 /* Function name. */
13951 assemble_string (fname, strlen (fname));
13952
13953 /* Register for alloca automatic storage; this is always reg 31.
13954 Only emit this if the alloca bit was set above. */
13955 if (frame_pointer_needed)
19d2d16f 13956 fputs ("\t.byte 31\n", file);
b1765bde
DE		 13957
13958 fputs ("\t.align 2\n", file);
9b30bae2 13959 }
9878760c 13960}
17167fd8 13961\f
a4f6c312
SS		 13962/* A C compound statement that outputs the assembler code for a thunk
13963 function, used to implement C++ virtual function calls with
13964 multiple inheritance. The thunk acts as a wrapper around a virtual
13965 function, adjusting the implicit object parameter before handing
13966 control off to the real function.
13967
13968 First, emit code to add the integer DELTA to the location that
13969 contains the incoming first argument. Assume that this argument
13970 contains a pointer, and is the one used to pass the `this' pointer
13971 in C++. This is the incoming argument *before* the function
13972 prologue, e.g. `%o0' on a sparc. The addition must preserve the
13973 values of all other incoming arguments.
17167fd8
MM		 13974
13975 After the addition, emit code to jump to FUNCTION, which is a
a4f6c312
SS		 13976 `FUNCTION_DECL'. This is a direct pure jump, not a call, and does
13977 not touch the return address. Hence returning from FUNCTION will
13978 return to whoever called the current `thunk'.
17167fd8 13979
a4f6c312
SS		 13980 The effect must be as if FUNCTION had been called directly with the
13981 adjusted first argument. This macro is responsible for emitting
13982 all of the code for a thunk function; output_function_prologue()
13983 and output_function_epilogue() are not invoked.
17167fd8 13984
a4f6c312
SS		 13985 The THUNK_FNDECL is redundant. (DELTA and FUNCTION have already
13986 been extracted from it.) It might possibly be useful on some
13987 targets, but probably not.
17167fd8 13988
a4f6c312
SS		 13989 If you do not define this macro, the target-independent code in the
13990 C++ frontend will generate a less efficient heavyweight thunk that
13991 calls FUNCTION instead of jumping to it. The generic approach does
13992 not support varargs. */
17167fd8 13993
3961e8fe 13994static void
f676971a
EC		 13995rs6000_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
13996 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
a2369ed3 13997 tree function)
17167fd8 13998{
5b71a4e7 13999 rtx this, insn, funexp;
17167fd8 14000
5b71a4e7 14001 reload_completed = 1;
fe3ad572 14002 epilogue_completed = 1;
5b71a4e7 14003 no_new_pseudos = 1;
6429e3be 14004 reset_block_changes ();
56a7189a 14005
5b71a4e7 14006 /* Mark the end of the (empty) prologue. */
2e040219 14007 emit_note (NOTE_INSN_PROLOGUE_END);
17167fd8 14008
5b71a4e7
DE		 14009 /* Find the "this" pointer. If the function returns a structure,
14010 the structure return pointer is in r3. */
61f71b34 14011 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
5b71a4e7 14012 this = gen_rtx_REG (Pmode, 4);
56a7189a 14013 else
5b71a4e7 14014 this = gen_rtx_REG (Pmode, 3);
17167fd8 14015
5b71a4e7
DE		 14016 /* Apply the constant offset, if required. */
14017 if (delta)
14018 {
14019 rtx delta_rtx = GEN_INT (delta);
14020 emit_insn (TARGET_32BIT
14021 ? gen_addsi3 (this, this, delta_rtx)
14022 : gen_adddi3 (this, this, delta_rtx));
17167fd8
MM		 14023 }
14024
5b71a4e7
DE		 14025 /* Apply the offset from the vtable, if required. */
14026 if (vcall_offset)
17167fd8 14027 {
5b71a4e7
DE		 14028 rtx vcall_offset_rtx = GEN_INT (vcall_offset);
14029 rtx tmp = gen_rtx_REG (Pmode, 12);
17167fd8 14030
5b71a4e7 14031 emit_move_insn (tmp, gen_rtx_MEM (Pmode, this));
eeff9307
JJ		 14032 if (((unsigned HOST_WIDE_INT) vcall_offset) + 0x8000 >= 0x10000)
14033 {
14034 emit_insn (TARGET_32BIT
14035 ? gen_addsi3 (tmp, tmp, vcall_offset_rtx)
14036 : gen_adddi3 (tmp, tmp, vcall_offset_rtx));
14037 emit_move_insn (tmp, gen_rtx_MEM (Pmode, tmp));
14038 }
14039 else
14040 {
14041 rtx loc = gen_rtx_PLUS (Pmode, tmp, vcall_offset_rtx);
14042
14043 emit_move_insn (tmp, gen_rtx_MEM (Pmode, loc));
14044 }
5b71a4e7
DE		 14045 emit_insn (TARGET_32BIT
14046 ? gen_addsi3 (this, this, tmp)
14047 : gen_adddi3 (this, this, tmp));
17167fd8
MM		 14048 }
14049
5b71a4e7
DE		 14050 /* Generate a tail call to the target function. */
14051 if (!TREE_USED (function))
14052 {
14053 assemble_external (function);
14054 TREE_USED (function) = 1;
14055 }
14056 funexp = XEXP (DECL_RTL (function), 0);
5b71a4e7 14057 funexp = gen_rtx_MEM (FUNCTION_MODE, funexp);
ee890fe2
SS		 14058
14059#if TARGET_MACHO
ab82a49f 14060 if (MACHOPIC_INDIRECT)
5b71a4e7 14061 funexp = machopic_indirect_call_target (funexp);
ee890fe2 14062#endif
5b71a4e7
DE		 14063
14064 /* gen_sibcall expects reload to convert scratch pseudo to LR so we must
14065 generate sibcall RTL explicitly to avoid constraint abort. */
14066 insn = emit_call_insn (
14067 gen_rtx_PARALLEL (VOIDmode,
14068 gen_rtvec (4,
14069 gen_rtx_CALL (VOIDmode,
14070 funexp, const0_rtx),
14071 gen_rtx_USE (VOIDmode, const0_rtx),
14072 gen_rtx_USE (VOIDmode,
14073 gen_rtx_REG (SImode,
14074 LINK_REGISTER_REGNUM)),
14075 gen_rtx_RETURN (VOIDmode))));
14076 SIBLING_CALL_P (insn) = 1;
14077 emit_barrier ();
14078
14079 /* Run just enough of rest_of_compilation to get the insns emitted.
14080 There's not really enough bulk here to make other passes such as
14081 instruction scheduling worth while. Note that use_thunk calls
14082 assemble_start_function and assemble_end_function. */
14083 insn = get_insns ();
a2855205 14084 insn_locators_initialize ();
5b71a4e7
DE		 14085 shorten_branches (insn);
14086 final_start_function (insn, file, 1);
14087 final (insn, file, 1, 0);
14088 final_end_function ();
14089
14090 reload_completed = 0;
fe3ad572 14091 epilogue_completed = 0;
5b71a4e7 14092 no_new_pseudos = 0;
9ebbca7d 14093}
9ebbca7d
GK		 14094\f
14095/* A quick summary of the various types of 'constant-pool tables'
14096 under PowerPC:
14097
f676971a 14098 Target Flags Name One table per
9ebbca7d
GK		 14099 AIX (none) AIX TOC object file
14100 AIX -mfull-toc AIX TOC object file
14101 AIX -mminimal-toc AIX minimal TOC translation unit
14102 SVR4/EABI (none) SVR4 SDATA object file
14103 SVR4/EABI -fpic SVR4 pic object file
14104 SVR4/EABI -fPIC SVR4 PIC translation unit
14105 SVR4/EABI -mrelocatable EABI TOC function
14106 SVR4/EABI -maix AIX TOC object file
f676971a 14107 SVR4/EABI -maix -mminimal-toc
9ebbca7d
GK		 14108 AIX minimal TOC translation unit
14109
14110 Name Reg. Set by entries contains:
14111 made by addrs? fp? sum?
14112
14113 AIX TOC 2 crt0 as Y option option
14114 AIX minimal TOC 30 prolog gcc Y Y option
14115 SVR4 SDATA 13 crt0 gcc N Y N
14116 SVR4 pic 30 prolog ld Y not yet N
14117 SVR4 PIC 30 prolog gcc Y option option
14118 EABI TOC 30 prolog gcc Y option option
14119
14120*/
14121
9ebbca7d
GK		 14122/* Hash functions for the hash table. */
14123
14124static unsigned
a2369ed3 14125rs6000_hash_constant (rtx k)
9ebbca7d 14126{
46b33600
RH		 14127 enum rtx_code code = GET_CODE (k);
14128 enum machine_mode mode = GET_MODE (k);
14129 unsigned result = (code << 3) ^ mode;
14130 const char *format;
14131 int flen, fidx;
f676971a 14132
46b33600
RH		 14133 format = GET_RTX_FORMAT (code);
14134 flen = strlen (format);
14135 fidx = 0;
9ebbca7d 14136
46b33600
RH		 14137 switch (code)
14138 {
14139 case LABEL_REF:
14140 return result * 1231 + (unsigned) INSN_UID (XEXP (k, 0));
14141
14142 case CONST_DOUBLE:
14143 if (mode != VOIDmode)
14144 return real_hash (CONST_DOUBLE_REAL_VALUE (k)) * result;
14145 flen = 2;
14146 break;
14147
14148 case CODE_LABEL:
14149 fidx = 3;
14150 break;
14151
14152 default:
14153 break;
14154 }
9ebbca7d
GK		 14155
14156 for (; fidx < flen; fidx++)
14157 switch (format[fidx])
14158 {
14159 case 's':
14160 {
14161 unsigned i, len;
14162 const char *str = XSTR (k, fidx);
14163 len = strlen (str);
14164 result = result * 613 + len;
14165 for (i = 0; i < len; i++)
14166 result = result * 613 + (unsigned) str[i];
17167fd8
MM		 14167 break;
14168 }
9ebbca7d
GK		 14169 case 'u':
14170 case 'e':
14171 result = result * 1231 + rs6000_hash_constant (XEXP (k, fidx));
14172 break;
14173 case 'i':
14174 case 'n':
14175 result = result * 613 + (unsigned) XINT (k, fidx);
14176 break;
14177 case 'w':
14178 if (sizeof (unsigned) >= sizeof (HOST_WIDE_INT))
14179 result = result * 613 + (unsigned) XWINT (k, fidx);
14180 else
14181 {
14182 size_t i;
9390387d 14183 for (i = 0; i < sizeof (HOST_WIDE_INT) / sizeof (unsigned); i++)
9ebbca7d
GK		 14184 result = result * 613 + (unsigned) (XWINT (k, fidx)
14185 >> CHAR_BIT * i);
14186 }
14187 break;
09501938
DE		 14188 case '0':
14189 break;
9ebbca7d 14190 default:
a4f6c312 14191 abort ();
9ebbca7d 14192 }
46b33600 14193
9ebbca7d
GK		 14194 return result;
14195}
14196
14197static unsigned
a2369ed3 14198toc_hash_function (const void *hash_entry)
9ebbca7d 14199{
f676971a 14200 const struct toc_hash_struct *thc =
a9098fd0
GK		 14201 (const struct toc_hash_struct *) hash_entry;
14202 return rs6000_hash_constant (thc->key) ^ thc->key_mode;
9ebbca7d
GK		 14203}
14204
14205/* Compare H1 and H2 for equivalence. */
14206
14207static int
a2369ed3 14208toc_hash_eq (const void *h1, const void *h2)
9ebbca7d
GK		 14209{
14210 rtx r1 = ((const struct toc_hash_struct *) h1)->key;
14211 rtx r2 = ((const struct toc_hash_struct *) h2)->key;
14212
a9098fd0
GK		 14213 if (((const struct toc_hash_struct *) h1)->key_mode
14214 != ((const struct toc_hash_struct *) h2)->key_mode)
14215 return 0;
14216
5692c7bc 14217 return rtx_equal_p (r1, r2);
9ebbca7d
GK		 14218}
14219
28e510bd
MM		 14220/* These are the names given by the C++ front-end to vtables, and
14221 vtable-like objects. Ideally, this logic should not be here;
14222 instead, there should be some programmatic way of inquiring as
14223 to whether or not an object is a vtable. */
14224
14225#define VTABLE_NAME_P(NAME) \
9390387d 14226 (strncmp ("_vt.", name, strlen ("_vt.")) == 0 \
28e510bd
MM		 14227 || strncmp ("_ZTV", name, strlen ("_ZTV")) == 0 \
14228 || strncmp ("_ZTT", name, strlen ("_ZTT")) == 0 \
26be75db 14229 || strncmp ("_ZTI", name, strlen ("_ZTI")) == 0 \
f676971a 14230 || strncmp ("_ZTC", name, strlen ("_ZTC")) == 0)
28e510bd
MM		 14231
14232void
a2369ed3 14233rs6000_output_symbol_ref (FILE *file, rtx x)
28e510bd
MM		 14234{
14235 /* Currently C++ toc references to vtables can be emitted before it
14236 is decided whether the vtable is public or private. If this is
14237 the case, then the linker will eventually complain that there is
f676971a 14238 a reference to an unknown section. Thus, for vtables only,
28e510bd
MM		 14239 we emit the TOC reference to reference the symbol and not the
14240 section. */
14241 const char *name = XSTR (x, 0);
54ee9799 14242
f676971a 14243 if (VTABLE_NAME_P (name))
54ee9799
DE		 14244 {
14245 RS6000_OUTPUT_BASENAME (file, name);
14246 }
14247 else
14248 assemble_name (file, name);
28e510bd
MM		 14249}
14250
a4f6c312
SS		 14251/* Output a TOC entry. We derive the entry name from what is being
14252 written. */
9878760c
RK		 14253
14254void
a2369ed3 14255output_toc (FILE *file, rtx x, int labelno, enum machine_mode mode)
9878760c
RK		 14256{
14257 char buf[256];
3cce094d 14258 const char *name = buf;
ec940faa 14259 const char *real_name;
9878760c
RK		 14260 rtx base = x;
14261 int offset = 0;
14262
4697a36c
MM		 14263 if (TARGET_NO_TOC)
14264 abort ();
14265
9ebbca7d
GK		 14266 /* When the linker won't eliminate them, don't output duplicate
14267 TOC entries (this happens on AIX if there is any kind of TOC,
17211ab5
GK		 14268 and on SVR4 under -fPIC or -mrelocatable). Don't do this for
14269 CODE_LABELs. */
14270 if (TARGET_TOC && GET_CODE (x) != LABEL_REF)
9ebbca7d
GK		 14271 {
14272 struct toc_hash_struct *h;
14273 void * * found;
f676971a 14274
17211ab5 14275 /* Create toc_hash_table. This can't be done at OVERRIDE_OPTIONS
c4ad648e 14276 time because GGC is not initialized at that point. */
17211ab5 14277 if (toc_hash_table == NULL)
f676971a 14278 toc_hash_table = htab_create_ggc (1021, toc_hash_function,
17211ab5
GK		 14279 toc_hash_eq, NULL);
14280
9ebbca7d
GK		 14281 h = ggc_alloc (sizeof (*h));
14282 h->key = x;
a9098fd0 14283 h->key_mode = mode;
9ebbca7d 14284 h->labelno = labelno;
f676971a 14285
9ebbca7d
GK		 14286 found = htab_find_slot (toc_hash_table, h, 1);
14287 if (*found == NULL)
14288 *found = h;
f676971a 14289 else /* This is indeed a duplicate.
9ebbca7d
GK		 14290 Set this label equal to that label. */
14291 {
14292 fputs ("\t.set ", file);
14293 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC");
14294 fprintf (file, "%d,", labelno);
14295 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC");
f676971a 14296 fprintf (file, "%d\n", ((*(const struct toc_hash_struct **)
9ebbca7d
GK		 14297 found)->labelno));
14298 return;
14299 }
14300 }
14301
14302 /* If we're going to put a double constant in the TOC, make sure it's
14303 aligned properly when strict alignment is on. */
ff1720ed
RK		 14304 if (GET_CODE (x) == CONST_DOUBLE
14305 && STRICT_ALIGNMENT
a9098fd0 14306 && GET_MODE_BITSIZE (mode) >= 64
ff1720ed
RK		 14307 && ! (TARGET_NO_FP_IN_TOC && ! TARGET_MINIMAL_TOC)) {
14308 ASM_OUTPUT_ALIGN (file, 3);
14309 }
14310
4977bab6 14311 (*targetm.asm_out.internal_label) (file, "LC", labelno);
9878760c 14312
37c37a57
RK		 14313 /* Handle FP constants specially. Note that if we have a minimal
14314 TOC, things we put here aren't actually in the TOC, so we can allow
14315 FP constants. */
fcce224d
DE		 14316 if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == TFmode)
14317 {
14318 REAL_VALUE_TYPE rv;
14319 long k[4];
14320
14321 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
14322 REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv, k);
14323
14324 if (TARGET_64BIT)
14325 {
14326 if (TARGET_MINIMAL_TOC)
14327 fputs (DOUBLE_INT_ASM_OP, file);
14328 else
14329 fprintf (file, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
14330 k[0] & 0xffffffff, k[1] & 0xffffffff,
14331 k[2] & 0xffffffff, k[3] & 0xffffffff);
14332 fprintf (file, "0x%lx%08lx,0x%lx%08lx\n",
14333 k[0] & 0xffffffff, k[1] & 0xffffffff,
14334 k[2] & 0xffffffff, k[3] & 0xffffffff);
14335 return;
14336 }
14337 else
14338 {
14339 if (TARGET_MINIMAL_TOC)
14340 fputs ("\t.long ", file);
14341 else
14342 fprintf (file, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
14343 k[0] & 0xffffffff, k[1] & 0xffffffff,
14344 k[2] & 0xffffffff, k[3] & 0xffffffff);
14345 fprintf (file, "0x%lx,0x%lx,0x%lx,0x%lx\n",
14346 k[0] & 0xffffffff, k[1] & 0xffffffff,
14347 k[2] & 0xffffffff, k[3] & 0xffffffff);
14348 return;
14349 }
14350 }
14351 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == DFmode)
9878760c 14352 {
042259f2
DE		 14353 REAL_VALUE_TYPE rv;
14354 long k[2];
0adc764e 14355
042259f2
DE		 14356 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
14357 REAL_VALUE_TO_TARGET_DOUBLE (rv, k);
31bfaa0b 14358
13ded975
DE		 14359 if (TARGET_64BIT)
14360 {
14361 if (TARGET_MINIMAL_TOC)
2bfcf297 14362 fputs (DOUBLE_INT_ASM_OP, file);
13ded975 14363 else
2f0552b6
AM		 14364 fprintf (file, "\t.tc FD_%lx_%lx[TC],",
14365 k[0] & 0xffffffff, k[1] & 0xffffffff);
14366 fprintf (file, "0x%lx%08lx\n",
14367 k[0] & 0xffffffff, k[1] & 0xffffffff);
13ded975
DE		 14368 return;
14369 }
1875cc88 14370 else
13ded975
DE		 14371 {
14372 if (TARGET_MINIMAL_TOC)
2bfcf297 14373 fputs ("\t.long ", file);
13ded975 14374 else
2f0552b6
AM		 14375 fprintf (file, "\t.tc FD_%lx_%lx[TC],",
14376 k[0] & 0xffffffff, k[1] & 0xffffffff);
14377 fprintf (file, "0x%lx,0x%lx\n",
14378 k[0] & 0xffffffff, k[1] & 0xffffffff);
13ded975
DE		 14379 return;
14380 }
9878760c 14381 }
a9098fd0 14382 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == SFmode)
9878760c 14383 {
042259f2
DE		 14384 REAL_VALUE_TYPE rv;
14385 long l;
9878760c 14386
042259f2
DE		 14387 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
14388 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
14389
31bfaa0b
DE		 14390 if (TARGET_64BIT)
14391 {
14392 if (TARGET_MINIMAL_TOC)
2bfcf297 14393 fputs (DOUBLE_INT_ASM_OP, file);
31bfaa0b 14394 else
2f0552b6
AM		 14395 fprintf (file, "\t.tc FS_%lx[TC],", l & 0xffffffff);
14396 fprintf (file, "0x%lx00000000\n", l & 0xffffffff);
31bfaa0b
DE		 14397 return;
14398 }
042259f2 14399 else
31bfaa0b
DE		 14400 {
14401 if (TARGET_MINIMAL_TOC)
2bfcf297 14402 fputs ("\t.long ", file);
31bfaa0b 14403 else
2f0552b6
AM		 14404 fprintf (file, "\t.tc FS_%lx[TC],", l & 0xffffffff);
14405 fprintf (file, "0x%lx\n", l & 0xffffffff);
31bfaa0b
DE		 14406 return;
14407 }
042259f2 14408 }
f176e826 14409 else if (GET_MODE (x) == VOIDmode
a9098fd0 14410 && (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE))
042259f2 14411 {
e2c953b6 14412 unsigned HOST_WIDE_INT low;
042259f2
DE		 14413 HOST_WIDE_INT high;
14414
14415 if (GET_CODE (x) == CONST_DOUBLE)
14416 {
14417 low = CONST_DOUBLE_LOW (x);
14418 high = CONST_DOUBLE_HIGH (x);
14419 }
14420 else
14421#if HOST_BITS_PER_WIDE_INT == 32
14422 {
14423 low = INTVAL (x);
0858c623 14424 high = (low & 0x80000000) ? ~0 : 0;
042259f2
DE		 14425 }
14426#else
14427 {
c4ad648e
AM		 14428 low = INTVAL (x) & 0xffffffff;
14429 high = (HOST_WIDE_INT) INTVAL (x) >> 32;
042259f2
DE		 14430 }
14431#endif
9878760c 14432
a9098fd0
GK		 14433 /* TOC entries are always Pmode-sized, but since this
14434 is a bigendian machine then if we're putting smaller
14435 integer constants in the TOC we have to pad them.
14436 (This is still a win over putting the constants in
14437 a separate constant pool, because then we'd have
02a4ec28
FS		 14438 to have both a TOC entry _and_ the actual constant.)
14439
14440 For a 32-bit target, CONST_INT values are loaded and shifted
14441 entirely within `low' and can be stored in one TOC entry. */
14442
14443 if (TARGET_64BIT && POINTER_SIZE < GET_MODE_BITSIZE (mode))
a9098fd0 14444 abort ();/* It would be easy to make this work, but it doesn't now. */
02a4ec28
FS		 14445
14446 if (POINTER_SIZE > GET_MODE_BITSIZE (mode))
fb52d8de
AM		 14447 {
14448#if HOST_BITS_PER_WIDE_INT == 32
14449 lshift_double (low, high, POINTER_SIZE - GET_MODE_BITSIZE (mode),
14450 POINTER_SIZE, &low, &high, 0);
14451#else
14452 low |= high << 32;
14453 low <<= POINTER_SIZE - GET_MODE_BITSIZE (mode);
14454 high = (HOST_WIDE_INT) low >> 32;
14455 low &= 0xffffffff;
14456#endif
14457 }
a9098fd0 14458
13ded975
DE		 14459 if (TARGET_64BIT)
14460 {
14461 if (TARGET_MINIMAL_TOC)
2bfcf297 14462 fputs (DOUBLE_INT_ASM_OP, file);
13ded975 14463 else
2f0552b6
AM		 14464 fprintf (file, "\t.tc ID_%lx_%lx[TC],",
14465 (long) high & 0xffffffff, (long) low & 0xffffffff);
14466 fprintf (file, "0x%lx%08lx\n",
14467 (long) high & 0xffffffff, (long) low & 0xffffffff);
13ded975
DE		 14468 return;
14469 }
1875cc88 14470 else
13ded975 14471 {
02a4ec28
FS		 14472 if (POINTER_SIZE < GET_MODE_BITSIZE (mode))
14473 {
14474 if (TARGET_MINIMAL_TOC)
2bfcf297 14475 fputs ("\t.long ", file);
02a4ec28 14476 else
2bfcf297 14477 fprintf (file, "\t.tc ID_%lx_%lx[TC],",
2f0552b6
AM		 14478 (long) high & 0xffffffff, (long) low & 0xffffffff);
14479 fprintf (file, "0x%lx,0x%lx\n",
14480 (long) high & 0xffffffff, (long) low & 0xffffffff);
02a4ec28 14481 }
13ded975 14482 else
02a4ec28
FS		 14483 {
14484 if (TARGET_MINIMAL_TOC)
2bfcf297 14485 fputs ("\t.long ", file);
02a4ec28 14486 else
2f0552b6
AM		 14487 fprintf (file, "\t.tc IS_%lx[TC],", (long) low & 0xffffffff);
14488 fprintf (file, "0x%lx\n", (long) low & 0xffffffff);
02a4ec28 14489 }
13ded975
DE		 14490 return;
14491 }
9878760c
RK		 14492 }
14493
14494 if (GET_CODE (x) == CONST)
14495 {
2bfcf297
DB		 14496 if (GET_CODE (XEXP (x, 0)) != PLUS)
14497 abort ();
14498
9878760c
RK		 14499 base = XEXP (XEXP (x, 0), 0);
14500 offset = INTVAL (XEXP (XEXP (x, 0), 1));
14501 }
f676971a 14502
9878760c
RK		 14503 if (GET_CODE (base) == SYMBOL_REF)
14504 name = XSTR (base, 0);
14505 else if (GET_CODE (base) == LABEL_REF)
14506 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (XEXP (base, 0)));
14507 else if (GET_CODE (base) == CODE_LABEL)
14508 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (base));
14509 else
14510 abort ();
14511
772c5265 14512 real_name = (*targetm.strip_name_encoding) (name);
1875cc88 14513 if (TARGET_MINIMAL_TOC)
2bfcf297 14514 fputs (TARGET_32BIT ? "\t.long " : DOUBLE_INT_ASM_OP, file);
1875cc88
JW		 14515 else
14516 {
b6c9286a 14517 fprintf (file, "\t.tc %s", real_name);
9878760c 14518
1875cc88
JW		 14519 if (offset < 0)
14520 fprintf (file, ".N%d", - offset);
14521 else if (offset)
14522 fprintf (file, ".P%d", offset);
9878760c 14523
19d2d16f 14524 fputs ("[TC],", file);
1875cc88 14525 }
581bc4de
MM		 14526
14527 /* Currently C++ toc references to vtables can be emitted before it
14528 is decided whether the vtable is public or private. If this is
14529 the case, then the linker will eventually complain that there is
14530 a TOC reference to an unknown section. Thus, for vtables only,
14531 we emit the TOC reference to reference the symbol and not the
14532 section. */
28e510bd 14533 if (VTABLE_NAME_P (name))
581bc4de 14534 {
54ee9799 14535 RS6000_OUTPUT_BASENAME (file, name);
581bc4de
MM		 14536 if (offset < 0)
14537 fprintf (file, "%d", offset);
14538 else if (offset > 0)
14539 fprintf (file, "+%d", offset);
14540 }
14541 else
14542 output_addr_const (file, x);
19d2d16f 14543 putc ('\n', file);
9878760c
RK		 14544}
14545\f
14546/* Output an assembler pseudo-op to write an ASCII string of N characters
14547 starting at P to FILE.
14548
14549 On the RS/6000, we have to do this using the .byte operation and
14550 write out special characters outside the quoted string.
14551 Also, the assembler is broken; very long strings are truncated,
a4f6c312 14552 so we must artificially break them up early. */
9878760c
RK		 14553
14554void
a2369ed3 14555output_ascii (FILE *file, const char *p, int n)
9878760c
RK		 14556{
14557 char c;
14558 int i, count_string;
d330fd93
KG		 14559 const char *for_string = "\t.byte \"";
14560 const char *for_decimal = "\t.byte ";
14561 const char *to_close = NULL;
9878760c
RK		 14562
14563 count_string = 0;
14564 for (i = 0; i < n; i++)
14565 {
14566 c = *p++;
14567 if (c >= ' ' && c < 0177)
14568 {
14569 if (for_string)
14570 fputs (for_string, file);
14571 putc (c, file);
14572
14573 /* Write two quotes to get one. */
14574 if (c == '"')
14575 {
14576 putc (c, file);
14577 ++count_string;
14578 }
14579
14580 for_string = NULL;
14581 for_decimal = "\"\n\t.byte ";
14582 to_close = "\"\n";
14583 ++count_string;
14584
14585 if (count_string >= 512)
14586 {
14587 fputs (to_close, file);
14588
14589 for_string = "\t.byte \"";
14590 for_decimal = "\t.byte ";
14591 to_close = NULL;
14592 count_string = 0;
14593 }
14594 }
14595 else
14596 {
14597 if (for_decimal)
14598 fputs (for_decimal, file);
14599 fprintf (file, "%d", c);
14600
14601 for_string = "\n\t.byte \"";
14602 for_decimal = ", ";
14603 to_close = "\n";
14604 count_string = 0;
14605 }
14606 }
14607
14608 /* Now close the string if we have written one. Then end the line. */
14609 if (to_close)
9ebbca7d 14610 fputs (to_close, file);
9878760c
RK		 14611}
14612\f
14613/* Generate a unique section name for FILENAME for a section type
14614 represented by SECTION_DESC. Output goes into BUF.
14615
14616 SECTION_DESC can be any string, as long as it is different for each
14617 possible section type.
14618
14619 We name the section in the same manner as xlc. The name begins with an
14620 underscore followed by the filename (after stripping any leading directory
11e5fe42
RK		 14621 names) with the last period replaced by the string SECTION_DESC. If
14622 FILENAME does not contain a period, SECTION_DESC is appended to the end of
14623 the name. */
9878760c
RK		 14624
14625void
f676971a 14626rs6000_gen_section_name (char **buf, const char *filename,
c4ad648e 14627 const char *section_desc)
9878760c 14628{
9ebbca7d 14629 const char *q, *after_last_slash, *last_period = 0;
9878760c
RK		 14630 char *p;
14631 int len;
9878760c
RK		 14632
14633 after_last_slash = filename;
14634 for (q = filename; *q; q++)
11e5fe42
RK		 14635 {
14636 if (*q == '/')
14637 after_last_slash = q + 1;
14638 else if (*q == '.')
14639 last_period = q;
14640 }
9878760c 14641
11e5fe42 14642 len = strlen (after_last_slash) + strlen (section_desc) + 2;
6d9f628e 14643 *buf = (char *) xmalloc (len);
9878760c
RK		 14644
14645 p = *buf;
14646 *p++ = '_';
14647
14648 for (q = after_last_slash; *q; q++)
14649 {
11e5fe42 14650 if (q == last_period)
c4ad648e 14651 {
9878760c
RK		 14652 strcpy (p, section_desc);
14653 p += strlen (section_desc);
e3981aab 14654 break;
c4ad648e 14655 }
9878760c 14656
e9a780ec 14657 else if (ISALNUM (*q))
c4ad648e 14658 *p++ = *q;
9878760c
RK		 14659 }
14660
11e5fe42 14661 if (last_period == 0)
9878760c
RK		 14662 strcpy (p, section_desc);
14663 else
14664 *p = '\0';
14665}
e165f3f0 14666\f
a4f6c312 14667/* Emit profile function. */
411707f4 14668
411707f4 14669void
a2369ed3 14670output_profile_hook (int labelno ATTRIBUTE_UNUSED)
411707f4 14671{
ffcfcb5f
AM		 14672 if (TARGET_PROFILE_KERNEL)
14673 return;
14674
8480e480
CC		 14675 if (DEFAULT_ABI == ABI_AIX)
14676 {
9739c90c
JJ		 14677#ifndef NO_PROFILE_COUNTERS
14678# define NO_PROFILE_COUNTERS 0
14679#endif
f676971a 14680 if (NO_PROFILE_COUNTERS)
9739c90c
JJ		 14681 emit_library_call (init_one_libfunc (RS6000_MCOUNT), 0, VOIDmode, 0);
14682 else
14683 {
14684 char buf[30];
14685 const char *label_name;
14686 rtx fun;
411707f4 14687
9739c90c
JJ		 14688 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
14689 label_name = (*targetm.strip_name_encoding) (ggc_strdup (buf));
14690 fun = gen_rtx_SYMBOL_REF (Pmode, label_name);
411707f4 14691
9739c90c
JJ		 14692 emit_library_call (init_one_libfunc (RS6000_MCOUNT), 0, VOIDmode, 1,
14693 fun, Pmode);
14694 }
8480e480 14695 }
ee890fe2
SS		 14696 else if (DEFAULT_ABI == ABI_DARWIN)
14697 {
d5fa86ba 14698 const char *mcount_name = RS6000_MCOUNT;
ee890fe2
SS		 14699 int caller_addr_regno = LINK_REGISTER_REGNUM;
14700
14701 /* Be conservative and always set this, at least for now. */
14702 current_function_uses_pic_offset_table = 1;
14703
14704#if TARGET_MACHO
14705 /* For PIC code, set up a stub and collect the caller's address
14706 from r0, which is where the prologue puts it. */
11abc112
MM		 14707 if (MACHOPIC_INDIRECT
14708 && current_function_uses_pic_offset_table)
14709 caller_addr_regno = 0;
ee890fe2
SS		 14710#endif
14711 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mcount_name),
14712 0, VOIDmode, 1,
14713 gen_rtx_REG (Pmode, caller_addr_regno), Pmode);
14714 }
411707f4
CC		 14715}
14716
a4f6c312 14717/* Write function profiler code. */
e165f3f0
RK		 14718
14719void
a2369ed3 14720output_function_profiler (FILE *file, int labelno)
e165f3f0 14721{
3daf36a4 14722 char buf[100];
09eeeacb 14723 int save_lr = 8;
e165f3f0 14724
38c1f2d7 14725 switch (DEFAULT_ABI)
3daf36a4 14726 {
38c1f2d7
MM		 14727 default:
14728 abort ();
14729
14730 case ABI_V4:
09eeeacb 14731 save_lr = 4;
09eeeacb
AM		 14732 if (!TARGET_32BIT)
14733 {
14734 warning ("no profiling of 64-bit code for this ABI");
14735 return;
14736 }
ffcfcb5f 14737 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
38c1f2d7
MM		 14738 fprintf (file, "\tmflr %s\n", reg_names[0]);
14739 if (flag_pic == 1)
14740 {
dfdfa60f 14741 fputs ("\tbl _GLOBAL_OFFSET_TABLE_@local-4\n", file);
09eeeacb
AM		 14742 asm_fprintf (file, "\t{st|stw} %s,%d(%s)\n",
14743 reg_names[0], save_lr, reg_names[1]);
17167fd8 14744 asm_fprintf (file, "\tmflr %s\n", reg_names[12]);
dfdfa60f 14745 asm_fprintf (file, "\t{l|lwz} %s,", reg_names[0]);
38c1f2d7 14746 assemble_name (file, buf);
17167fd8 14747 asm_fprintf (file, "@got(%s)\n", reg_names[12]);
38c1f2d7 14748 }
9ebbca7d 14749 else if (flag_pic > 1)
38c1f2d7 14750 {
09eeeacb
AM		 14751 asm_fprintf (file, "\t{st|stw} %s,%d(%s)\n",
14752 reg_names[0], save_lr, reg_names[1]);
9ebbca7d
GK		 14753 /* Now, we need to get the address of the label. */
14754 fputs ("\tbl 1f\n\t.long ", file);
034e84c4 14755 assemble_name (file, buf);
9ebbca7d
GK		 14756 fputs ("-.\n1:", file);
14757 asm_fprintf (file, "\tmflr %s\n", reg_names[11]);
f676971a 14758 asm_fprintf (file, "\t{l|lwz} %s,0(%s)\n",
9ebbca7d
GK		 14759 reg_names[0], reg_names[11]);
14760 asm_fprintf (file, "\t{cax|add} %s,%s,%s\n",
14761 reg_names[0], reg_names[0], reg_names[11]);
38c1f2d7 14762 }
38c1f2d7
MM		 14763 else
14764 {
17167fd8 14765 asm_fprintf (file, "\t{liu|lis} %s,", reg_names[12]);
38c1f2d7 14766 assemble_name (file, buf);
dfdfa60f 14767 fputs ("@ha\n", file);
09eeeacb
AM		 14768 asm_fprintf (file, "\t{st|stw} %s,%d(%s)\n",
14769 reg_names[0], save_lr, reg_names[1]);
a260abc9 14770 asm_fprintf (file, "\t{cal|la} %s,", reg_names[0]);
38c1f2d7 14771 assemble_name (file, buf);
17167fd8 14772 asm_fprintf (file, "@l(%s)\n", reg_names[12]);
38c1f2d7
MM		 14773 }
14774
50d440bc 14775 /* ABI_V4 saves the static chain reg with ASM_OUTPUT_REG_PUSH. */
3b6ce0af
DE		 14776 fprintf (file, "\tbl %s%s\n",
14777 RS6000_MCOUNT, flag_pic ? "@plt" : "");
38c1f2d7
MM		 14778 break;
14779
14780 case ABI_AIX:
ee890fe2 14781 case ABI_DARWIN:
ffcfcb5f
AM		 14782 if (!TARGET_PROFILE_KERNEL)
14783 {
a3c9585f 14784 /* Don't do anything, done in output_profile_hook (). */
ffcfcb5f
AM		 14785 }
14786 else
14787 {
14788 if (TARGET_32BIT)
14789 abort ();
14790
14791 asm_fprintf (file, "\tmflr %s\n", reg_names[0]);
14792 asm_fprintf (file, "\tstd %s,16(%s)\n", reg_names[0], reg_names[1]);
14793
6de9cd9a 14794 if (cfun->static_chain_decl != NULL)
ffcfcb5f
AM		 14795 {
14796 asm_fprintf (file, "\tstd %s,24(%s)\n",
14797 reg_names[STATIC_CHAIN_REGNUM], reg_names[1]);
14798 fprintf (file, "\tbl %s\n", RS6000_MCOUNT);
14799 asm_fprintf (file, "\tld %s,24(%s)\n",
14800 reg_names[STATIC_CHAIN_REGNUM], reg_names[1]);
14801 }
14802 else
14803 fprintf (file, "\tbl %s\n", RS6000_MCOUNT);
14804 }
38c1f2d7
MM		 14805 break;
14806 }
e165f3f0 14807}
a251ffd0 14808
b54cf83a 14809\f
b54cf83a
DE		 14810/* Power4 load update and store update instructions are cracked into a
14811 load or store and an integer insn which are executed in the same cycle.
14812 Branches have their own dispatch slot which does not count against the
14813 GCC issue rate, but it changes the program flow so there are no other
14814 instructions to issue in this cycle. */
14815
14816static int
f676971a
EC		 14817rs6000_variable_issue (FILE *stream ATTRIBUTE_UNUSED,
14818 int verbose ATTRIBUTE_UNUSED,
a2369ed3 14819 rtx insn, int more)
b54cf83a
DE		 14820{
14821 if (GET_CODE (PATTERN (insn)) == USE
14822 || GET_CODE (PATTERN (insn)) == CLOBBER)
14823 return more;
14824
ec507f2d 14825 if (rs6000_sched_groups)
b54cf83a 14826 {
cbe26ab8 14827 if (is_microcoded_insn (insn))
c4ad648e 14828 return 0;
cbe26ab8 14829 else if (is_cracked_insn (insn))
c4ad648e 14830 return more > 2 ? more - 2 : 0;
b54cf83a 14831 }
165b263e
DE		 14832
14833 return more - 1;
b54cf83a
DE		 14834}
14835
a251ffd0
TG		 14836/* Adjust the cost of a scheduling dependency. Return the new cost of
14837 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
14838
c237e94a 14839static int
0a4f0294 14840rs6000_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
a251ffd0
TG		 14841{
14842 if (! recog_memoized (insn))
14843 return 0;
14844
14845 if (REG_NOTE_KIND (link) != 0)
14846 return 0;
14847
14848 if (REG_NOTE_KIND (link) == 0)
14849 {
ed947a96
DJ		 14850 /* Data dependency; DEP_INSN writes a register that INSN reads
14851 some cycles later. */
c9dbf840
DE		 14852
14853 /* Separate a load from a narrower, dependent store. */
14854 if (rs6000_sched_groups
14855 && GET_CODE (PATTERN (insn)) == SET
14856 && GET_CODE (PATTERN (dep_insn)) == SET
14857 && GET_CODE (XEXP (PATTERN (insn), 1)) == MEM
14858 && GET_CODE (XEXP (PATTERN (dep_insn), 0)) == MEM
14859 && (GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (insn), 1)))
14860 > GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (dep_insn), 0)))))
14861 return cost + 14;
14862
ed947a96
DJ		 14863 switch (get_attr_type (insn))
14864 {
14865 case TYPE_JMPREG:
309323c2 14866 /* Tell the first scheduling pass about the latency between
ed947a96
DJ		 14867 a mtctr and bctr (and mtlr and br/blr). The first
14868 scheduling pass will not know about this latency since
14869 the mtctr instruction, which has the latency associated
14870 to it, will be generated by reload. */
309323c2 14871 return TARGET_POWER ? 5 : 4;
ed947a96
DJ		 14872 case TYPE_BRANCH:
14873 /* Leave some extra cycles between a compare and its
14874 dependent branch, to inhibit expensive mispredicts. */
309323c2
DE		 14875 if ((rs6000_cpu_attr == CPU_PPC603
14876 || rs6000_cpu_attr == CPU_PPC604
14877 || rs6000_cpu_attr == CPU_PPC604E
14878 || rs6000_cpu_attr == CPU_PPC620
14879 || rs6000_cpu_attr == CPU_PPC630
14880 || rs6000_cpu_attr == CPU_PPC750
14881 || rs6000_cpu_attr == CPU_PPC7400
14882 || rs6000_cpu_attr == CPU_PPC7450
ec507f2d
DE		 14883 || rs6000_cpu_attr == CPU_POWER4
14884 || rs6000_cpu_attr == CPU_POWER5)
ed947a96
DJ		 14885 && recog_memoized (dep_insn)
14886 && (INSN_CODE (dep_insn) >= 0)
b54cf83a
DE		 14887 && (get_attr_type (dep_insn) == TYPE_CMP
14888 || get_attr_type (dep_insn) == TYPE_COMPARE
ed947a96 14889 || get_attr_type (dep_insn) == TYPE_DELAYED_COMPARE
9259f3b0
DE		 14890 || get_attr_type (dep_insn) == TYPE_IMUL_COMPARE
14891 || get_attr_type (dep_insn) == TYPE_LMUL_COMPARE
ed947a96 14892 || get_attr_type (dep_insn) == TYPE_FPCOMPARE
b54cf83a
DE		 14893 || get_attr_type (dep_insn) == TYPE_CR_LOGICAL
14894 || get_attr_type (dep_insn) == TYPE_DELAYED_CR))
ed947a96
DJ		 14895 return cost + 2;
14896 default:
14897 break;
14898 }
a251ffd0
TG		 14899 /* Fall out to return default cost. */
14900 }
14901
14902 return cost;
14903}
b6c9286a 14904
cbe26ab8 14905/* The function returns a true if INSN is microcoded.
839a4992 14906 Return false otherwise. */
cbe26ab8
DN		 14907
14908static bool
14909is_microcoded_insn (rtx insn)
14910{
14911 if (!insn || !INSN_P (insn)
14912 || GET_CODE (PATTERN (insn)) == USE
14913 || GET_CODE (PATTERN (insn)) == CLOBBER)
14914 return false;
14915
ec507f2d 14916 if (rs6000_sched_groups)
cbe26ab8
DN		 14917 {
14918 enum attr_type type = get_attr_type (insn);
14919 if (type == TYPE_LOAD_EXT_U
14920 || type == TYPE_LOAD_EXT_UX
14921 || type == TYPE_LOAD_UX
14922 || type == TYPE_STORE_UX
14923 || type == TYPE_MFCR)
c4ad648e 14924 return true;
cbe26ab8
DN		 14925 }
14926
14927 return false;
14928}
14929
5c425df5 14930/* The function returns a nonzero value if INSN can be scheduled only
cbe26ab8
DN		 14931 as the first insn in a dispatch group ("dispatch-slot restricted").
14932 In this case, the returned value indicates how many dispatch slots
14933 the insn occupies (at the beginning of the group).
79ae11c4
DN		 14934 Return 0 otherwise. */
14935
cbe26ab8 14936static int
79ae11c4
DN		 14937is_dispatch_slot_restricted (rtx insn)
14938{
14939 enum attr_type type;
14940
ec507f2d 14941 if (!rs6000_sched_groups)
79ae11c4
DN		 14942 return 0;
14943
14944 if (!insn
14945 || insn == NULL_RTX
14946 || GET_CODE (insn) == NOTE
14947 || GET_CODE (PATTERN (insn)) == USE
14948 || GET_CODE (PATTERN (insn)) == CLOBBER)
14949 return 0;
14950
14951 type = get_attr_type (insn);
14952
ec507f2d
DE		 14953 switch (type)
14954 {
14955 case TYPE_MFCR:
14956 case TYPE_MFCRF:
14957 case TYPE_MTCR:
14958 case TYPE_DELAYED_CR:
14959 case TYPE_CR_LOGICAL:
14960 case TYPE_MTJMPR:
14961 case TYPE_MFJMPR:
14962 return 1;
14963 case TYPE_IDIV:
14964 case TYPE_LDIV:
14965 return 2;
14966 default:
14967 if (rs6000_cpu == PROCESSOR_POWER5
14968 && is_cracked_insn (insn))
14969 return 2;
14970 return 0;
14971 }
79ae11c4
DN		 14972}
14973
cbe26ab8
DN		 14974/* The function returns true if INSN is cracked into 2 instructions
14975 by the processor (and therefore occupies 2 issue slots). */
14976
14977static bool
14978is_cracked_insn (rtx insn)
14979{
14980 if (!insn || !INSN_P (insn)
14981 || GET_CODE (PATTERN (insn)) == USE
14982 || GET_CODE (PATTERN (insn)) == CLOBBER)
14983 return false;
14984
ec507f2d 14985 if (rs6000_sched_groups)
cbe26ab8
DN		 14986 {
14987 enum attr_type type = get_attr_type (insn);
14988 if (type == TYPE_LOAD_U || type == TYPE_STORE_U
c4ad648e
AM		 14989 || type == TYPE_FPLOAD_U || type == TYPE_FPSTORE_U
14990 || type == TYPE_FPLOAD_UX || type == TYPE_FPSTORE_UX
14991 || type == TYPE_LOAD_EXT || type == TYPE_DELAYED_CR
14992 || type == TYPE_COMPARE || type == TYPE_DELAYED_COMPARE
14993 || type == TYPE_IMUL_COMPARE || type == TYPE_LMUL_COMPARE
14994 || type == TYPE_IDIV || type == TYPE_LDIV
14995 || type == TYPE_INSERT_WORD)
14996 return true;
cbe26ab8
DN		 14997 }
14998
14999 return false;
15000}
15001
15002/* The function returns true if INSN can be issued only from
a3c9585f 15003 the branch slot. */
cbe26ab8
DN		 15004
15005static bool
15006is_branch_slot_insn (rtx insn)
15007{
15008 if (!insn || !INSN_P (insn)
15009 || GET_CODE (PATTERN (insn)) == USE
15010 || GET_CODE (PATTERN (insn)) == CLOBBER)
15011 return false;
15012
ec507f2d 15013 if (rs6000_sched_groups)
cbe26ab8
DN		 15014 {
15015 enum attr_type type = get_attr_type (insn);
15016 if (type == TYPE_BRANCH || type == TYPE_JMPREG)
f676971a 15017 return true;
cbe26ab8
DN		 15018 return false;
15019 }
15020
15021 return false;
15022}
79ae11c4 15023
a4f6c312 15024/* A C statement (sans semicolon) to update the integer scheduling
79ae11c4
DN		 15025 priority INSN_PRIORITY (INSN). Increase the priority to execute the
15026 INSN earlier, reduce the priority to execute INSN later. Do not
a4f6c312
SS		 15027 define this macro if you do not need to adjust the scheduling
15028 priorities of insns. */
bef84347 15029
c237e94a 15030static int
a2369ed3 15031rs6000_adjust_priority (rtx insn ATTRIBUTE_UNUSED, int priority)
bef84347 15032{
a4f6c312
SS		 15033 /* On machines (like the 750) which have asymmetric integer units,
15034 where one integer unit can do multiply and divides and the other
15035 can't, reduce the priority of multiply/divide so it is scheduled
15036 before other integer operations. */
bef84347
VM		 15037
15038#if 0
2c3c49de 15039 if (! INSN_P (insn))
bef84347
VM		 15040 return priority;
15041
15042 if (GET_CODE (PATTERN (insn)) == USE)
15043 return priority;
15044
15045 switch (rs6000_cpu_attr) {
15046 case CPU_PPC750:
15047 switch (get_attr_type (insn))
15048 {
15049 default:
15050 break;
15051
15052 case TYPE_IMUL:
15053 case TYPE_IDIV:
3cb999d8
DE		 15054 fprintf (stderr, "priority was %#x (%d) before adjustment\n",
15055 priority, priority);
bef84347
VM		 15056 if (priority >= 0 && priority < 0x01000000)
15057 priority >>= 3;
15058 break;
15059 }
15060 }
15061#endif
15062
79ae11c4
DN		 15063 if (is_dispatch_slot_restricted (insn)
15064 && reload_completed
f676971a 15065 && current_sched_info->sched_max_insns_priority
79ae11c4
DN		 15066 && rs6000_sched_restricted_insns_priority)
15067 {
15068
c4ad648e
AM		 15069 /* Prioritize insns that can be dispatched only in the first
15070 dispatch slot. */
79ae11c4 15071 if (rs6000_sched_restricted_insns_priority == 1)
f676971a
EC		 15072 /* Attach highest priority to insn. This means that in
15073 haifa-sched.c:ready_sort(), dispatch-slot restriction considerations
79ae11c4 15074 precede 'priority' (critical path) considerations. */
f676971a 15075 return current_sched_info->sched_max_insns_priority;
79ae11c4 15076 else if (rs6000_sched_restricted_insns_priority == 2)
f676971a 15077 /* Increase priority of insn by a minimal amount. This means that in
c4ad648e
AM		 15078 haifa-sched.c:ready_sort(), only 'priority' (critical path)
15079 considerations precede dispatch-slot restriction considerations. */
f676971a
EC		 15080 return (priority + 1);
15081 }
79ae11c4 15082
bef84347
VM		 15083 return priority;
15084}
15085
a4f6c312
SS		 15086/* Return how many instructions the machine can issue per cycle. */
15087
c237e94a 15088static int
863d938c 15089rs6000_issue_rate (void)
b6c9286a 15090{
3317bab1
DE		 15091 /* Use issue rate of 1 for first scheduling pass to decrease degradation. */
15092 if (!reload_completed)
15093 return 1;
15094
b6c9286a 15095 switch (rs6000_cpu_attr) {
3cb999d8
DE		 15096 case CPU_RIOS1: /* ? */
15097 case CPU_RS64A:
15098 case CPU_PPC601: /* ? */
ed947a96 15099 case CPU_PPC7450:
3cb999d8 15100 return 3;
b54cf83a 15101 case CPU_PPC440:
b6c9286a 15102 case CPU_PPC603:
bef84347 15103 case CPU_PPC750:
ed947a96 15104 case CPU_PPC7400:
be12c2b0 15105 case CPU_PPC8540:
f676971a 15106 return 2;
3cb999d8 15107 case CPU_RIOS2:
b6c9286a 15108 case CPU_PPC604:
19684119 15109 case CPU_PPC604E:
b6c9286a 15110 case CPU_PPC620:
3cb999d8 15111 case CPU_PPC630:
b6c9286a 15112 return 4;
cbe26ab8 15113 case CPU_POWER4:
ec507f2d 15114 case CPU_POWER5:
cbe26ab8 15115 return 5;
b6c9286a
MM		 15116 default:
15117 return 1;
15118 }
15119}
15120
be12c2b0
VM		 15121/* Return how many instructions to look ahead for better insn
15122 scheduling. */
15123
15124static int
863d938c 15125rs6000_use_sched_lookahead (void)
be12c2b0
VM		 15126{
15127 if (rs6000_cpu_attr == CPU_PPC8540)
15128 return 4;
15129 return 0;
15130}
15131
569fa502
DN		 15132/* Determine is PAT refers to memory. */
15133
15134static bool
15135is_mem_ref (rtx pat)
15136{
15137 const char * fmt;
15138 int i, j;
15139 bool ret = false;
15140
15141 if (GET_CODE (pat) == MEM)
15142 return true;
15143
15144 /* Recursively process the pattern. */
15145 fmt = GET_RTX_FORMAT (GET_CODE (pat));
15146
15147 for (i = GET_RTX_LENGTH (GET_CODE (pat)) - 1; i >= 0 && !ret; i--)
15148 {
15149 if (fmt[i] == 'e')
15150 ret |= is_mem_ref (XEXP (pat, i));
15151 else if (fmt[i] == 'E')
15152 for (j = XVECLEN (pat, i) - 1; j >= 0; j--)
15153 ret |= is_mem_ref (XVECEXP (pat, i, j));
15154 }
15155
15156 return ret;
15157}
15158
15159/* Determine if PAT is a PATTERN of a load insn. */
f676971a 15160
569fa502
DN		 15161static bool
15162is_load_insn1 (rtx pat)
15163{
15164 if (!pat || pat == NULL_RTX)
15165 return false;
15166
15167 if (GET_CODE (pat) == SET)
15168 return is_mem_ref (SET_SRC (pat));
15169
15170 if (GET_CODE (pat) == PARALLEL)
15171 {
15172 int i;
15173
15174 for (i = 0; i < XVECLEN (pat, 0); i++)
15175 if (is_load_insn1 (XVECEXP (pat, 0, i)))
15176 return true;
15177 }
15178
15179 return false;
15180}
15181
15182/* Determine if INSN loads from memory. */
15183
15184static bool
15185is_load_insn (rtx insn)
15186{
15187 if (!insn || !INSN_P (insn))
15188 return false;
15189
15190 if (GET_CODE (insn) == CALL_INSN)
15191 return false;
15192
15193 return is_load_insn1 (PATTERN (insn));
15194}
15195
15196/* Determine if PAT is a PATTERN of a store insn. */
15197
15198static bool
15199is_store_insn1 (rtx pat)
15200{
15201 if (!pat || pat == NULL_RTX)
15202 return false;
15203
15204 if (GET_CODE (pat) == SET)
15205 return is_mem_ref (SET_DEST (pat));
15206
15207 if (GET_CODE (pat) == PARALLEL)
15208 {
15209 int i;
15210
15211 for (i = 0; i < XVECLEN (pat, 0); i++)
15212 if (is_store_insn1 (XVECEXP (pat, 0, i)))
15213 return true;
15214 }
15215
15216 return false;
15217}
15218
15219/* Determine if INSN stores to memory. */
15220
15221static bool
15222is_store_insn (rtx insn)
15223{
15224 if (!insn || !INSN_P (insn))
15225 return false;
15226
15227 return is_store_insn1 (PATTERN (insn));
15228}
15229
15230/* Returns whether the dependence between INSN and NEXT is considered
15231 costly by the given target. */
15232
15233static bool
c4ad648e
AM		 15234rs6000_is_costly_dependence (rtx insn, rtx next, rtx link, int cost,
15235 int distance)
f676971a 15236{
569fa502 15237 /* If the flag is not enbled - no dependence is considered costly;
f676971a 15238 allow all dependent insns in the same group.
569fa502
DN		 15239 This is the most aggressive option. */
15240 if (rs6000_sched_costly_dep == no_dep_costly)
15241 return false;
15242
f676971a 15243 /* If the flag is set to 1 - a dependence is always considered costly;
569fa502
DN		 15244 do not allow dependent instructions in the same group.
15245 This is the most conservative option. */
15246 if (rs6000_sched_costly_dep == all_deps_costly)
f676971a 15247 return true;
569fa502 15248
f676971a
EC		 15249 if (rs6000_sched_costly_dep == store_to_load_dep_costly
15250 && is_load_insn (next)
569fa502
DN		 15251 && is_store_insn (insn))
15252 /* Prevent load after store in the same group. */
15253 return true;
15254
15255 if (rs6000_sched_costly_dep == true_store_to_load_dep_costly
f676971a 15256 && is_load_insn (next)
569fa502
DN		 15257 && is_store_insn (insn)
15258 && (!link || (int) REG_NOTE_KIND (link) == 0))
c4ad648e
AM		 15259 /* Prevent load after store in the same group if it is a true
15260 dependence. */
569fa502 15261 return true;
f676971a
EC		 15262
15263 /* The flag is set to X; dependences with latency >= X are considered costly,
569fa502
DN		 15264 and will not be scheduled in the same group. */
15265 if (rs6000_sched_costly_dep <= max_dep_latency
15266 && ((cost - distance) >= (int)rs6000_sched_costly_dep))
15267 return true;
15268
15269 return false;
15270}
15271
f676971a 15272/* Return the next insn after INSN that is found before TAIL is reached,
cbe26ab8
DN		 15273 skipping any "non-active" insns - insns that will not actually occupy
15274 an issue slot. Return NULL_RTX if such an insn is not found. */
15275
15276static rtx
15277get_next_active_insn (rtx insn, rtx tail)
15278{
15279 rtx next_insn;
15280
15281 if (!insn || insn == tail)
15282 return NULL_RTX;
15283
15284 next_insn = NEXT_INSN (insn);
15285
15286 while (next_insn
15287 && next_insn != tail
9390387d 15288 && (GET_CODE (next_insn) == NOTE
cbe26ab8
DN		 15289 || GET_CODE (PATTERN (next_insn)) == USE
15290 || GET_CODE (PATTERN (next_insn)) == CLOBBER))
15291 {
15292 next_insn = NEXT_INSN (next_insn);
15293 }
15294
15295 if (!next_insn || next_insn == tail)
15296 return NULL_RTX;
15297
15298 return next_insn;
15299}
15300
839a4992 15301/* Return whether the presence of INSN causes a dispatch group termination
cbe26ab8
DN		 15302 of group WHICH_GROUP.
15303
15304 If WHICH_GROUP == current_group, this function will return true if INSN
15305 causes the termination of the current group (i.e, the dispatch group to
15306 which INSN belongs). This means that INSN will be the last insn in the
15307 group it belongs to.
15308
15309 If WHICH_GROUP == previous_group, this function will return true if INSN
15310 causes the termination of the previous group (i.e, the dispatch group that
15311 precedes the group to which INSN belongs). This means that INSN will be
15312 the first insn in the group it belongs to). */
15313
15314static bool
15315insn_terminates_group_p (rtx insn, enum group_termination which_group)
15316{
15317 enum attr_type type;
15318
15319 if (! insn)
15320 return false;
569fa502 15321
cbe26ab8
DN		 15322 type = get_attr_type (insn);
15323
15324 if (is_microcoded_insn (insn))
15325 return true;
15326
15327 if (which_group == current_group)
15328 {
15329 if (is_branch_slot_insn (insn))
c4ad648e 15330 return true;
cbe26ab8
DN		 15331 return false;
15332 }
15333 else if (which_group == previous_group)
15334 {
15335 if (is_dispatch_slot_restricted (insn))
c4ad648e 15336 return true;
cbe26ab8
DN		 15337 return false;
15338 }
15339
15340 return false;
15341}
15342
839a4992 15343/* Return true if it is recommended to keep NEXT_INSN "far" (in a separate
cbe26ab8
DN		 15344 dispatch group) from the insns in GROUP_INSNS. Return false otherwise. */
15345
15346static bool
15347is_costly_group (rtx *group_insns, rtx next_insn)
15348{
15349 int i;
15350 rtx link;
15351 int cost;
15352 int issue_rate = rs6000_issue_rate ();
15353
15354 for (i = 0; i < issue_rate; i++)
15355 {
15356 rtx insn = group_insns[i];
15357 if (!insn)
c4ad648e 15358 continue;
cbe26ab8 15359 for (link = INSN_DEPEND (insn); link != 0; link = XEXP (link, 1))
c4ad648e
AM		 15360 {
15361 rtx next = XEXP (link, 0);
15362 if (next == next_insn)
15363 {
15364 cost = insn_cost (insn, link, next_insn);
15365 if (rs6000_is_costly_dependence (insn, next_insn, link, cost, 0))
15366 return true;
15367 }
15368 }
cbe26ab8
DN		 15369 }
15370
15371 return false;
15372}
15373
f676971a 15374/* Utility of the function redefine_groups.
cbe26ab8
DN		 15375 Check if it is too costly to schedule NEXT_INSN together with GROUP_INSNS
15376 in the same dispatch group. If so, insert nops before NEXT_INSN, in order
15377 to keep it "far" (in a separate group) from GROUP_INSNS, following
15378 one of the following schemes, depending on the value of the flag
15379 -minsert_sched_nops = X:
15380 (1) X == sched_finish_regroup_exact: insert exactly as many nops as needed
839a4992 15381 in order to force NEXT_INSN into a separate group.
f676971a
EC		 15382 (2) X < sched_finish_regroup_exact: insert exactly X nops.
15383 GROUP_END, CAN_ISSUE_MORE and GROUP_COUNT record the state after nop
cbe26ab8
DN		 15384 insertion (has a group just ended, how many vacant issue slots remain in the
15385 last group, and how many dispatch groups were encountered so far). */
15386
f676971a 15387static int
c4ad648e
AM		 15388force_new_group (int sched_verbose, FILE *dump, rtx *group_insns,
15389 rtx next_insn, bool *group_end, int can_issue_more,
15390 int *group_count)
cbe26ab8
DN		 15391{
15392 rtx nop;
15393 bool force;
15394 int issue_rate = rs6000_issue_rate ();
15395 bool end = *group_end;
15396 int i;
15397
15398 if (next_insn == NULL_RTX)
15399 return can_issue_more;
15400
15401 if (rs6000_sched_insert_nops > sched_finish_regroup_exact)
15402 return can_issue_more;
15403
15404 force = is_costly_group (group_insns, next_insn);
15405 if (!force)
15406 return can_issue_more;
15407
15408 if (sched_verbose > 6)
15409 fprintf (dump,"force: group count = %d, can_issue_more = %d\n",
c4ad648e 15410 *group_count ,can_issue_more);
cbe26ab8
DN		 15411
15412 if (rs6000_sched_insert_nops == sched_finish_regroup_exact)
15413 {
15414 if (*group_end)
c4ad648e 15415 can_issue_more = 0;
cbe26ab8
DN		 15416
15417 /* Since only a branch can be issued in the last issue_slot, it is
15418 sufficient to insert 'can_issue_more - 1' nops if next_insn is not
15419 a branch. If next_insn is a branch, we insert 'can_issue_more' nops;
c4ad648e
AM		 15420 in this case the last nop will start a new group and the branch
15421 will be forced to the new group. */
cbe26ab8 15422 if (can_issue_more && !is_branch_slot_insn (next_insn))
c4ad648e 15423 can_issue_more--;
cbe26ab8
DN		 15424
15425 while (can_issue_more > 0)
c4ad648e 15426 {
9390387d 15427 nop = gen_nop ();
c4ad648e
AM		 15428 emit_insn_before (nop, next_insn);
15429 can_issue_more--;
15430 }
cbe26ab8
DN		 15431
15432 *group_end = true;
15433 return 0;
f676971a 15434 }
cbe26ab8
DN		 15435
15436 if (rs6000_sched_insert_nops < sched_finish_regroup_exact)
15437 {
15438 int n_nops = rs6000_sched_insert_nops;
15439
f676971a 15440 /* Nops can't be issued from the branch slot, so the effective
c4ad648e 15441 issue_rate for nops is 'issue_rate - 1'. */
cbe26ab8 15442 if (can_issue_more == 0)
c4ad648e 15443 can_issue_more = issue_rate;
cbe26ab8
DN		 15444 can_issue_more--;
15445 if (can_issue_more == 0)
c4ad648e
AM		 15446 {
15447 can_issue_more = issue_rate - 1;
15448 (*group_count)++;
15449 end = true;
15450 for (i = 0; i < issue_rate; i++)
15451 {
15452 group_insns[i] = 0;
15453 }
15454 }
cbe26ab8
DN		 15455
15456 while (n_nops > 0)
c4ad648e
AM		 15457 {
15458 nop = gen_nop ();
15459 emit_insn_before (nop, next_insn);
15460 if (can_issue_more == issue_rate - 1) /* new group begins */
15461 end = false;
15462 can_issue_more--;
15463 if (can_issue_more == 0)
15464 {
15465 can_issue_more = issue_rate - 1;
15466 (*group_count)++;
15467 end = true;
15468 for (i = 0; i < issue_rate; i++)
15469 {
15470 group_insns[i] = 0;
15471 }
15472 }
15473 n_nops--;
15474 }
cbe26ab8
DN		 15475
15476 /* Scale back relative to 'issue_rate' (instead of 'issue_rate - 1'). */
f676971a 15477 can_issue_more++;
cbe26ab8 15478
c4ad648e
AM		 15479 /* Is next_insn going to start a new group? */
15480 *group_end
15481 = (end
cbe26ab8
DN		 15482 || (can_issue_more == 1 && !is_branch_slot_insn (next_insn))
15483 || (can_issue_more <= 2 && is_cracked_insn (next_insn))
15484 || (can_issue_more < issue_rate &&
c4ad648e 15485 insn_terminates_group_p (next_insn, previous_group)));
cbe26ab8 15486 if (*group_end && end)
c4ad648e 15487 (*group_count)--;
cbe26ab8
DN		 15488
15489 if (sched_verbose > 6)
c4ad648e
AM		 15490 fprintf (dump, "done force: group count = %d, can_issue_more = %d\n",
15491 *group_count, can_issue_more);
f676971a
EC		 15492 return can_issue_more;
15493 }
cbe26ab8
DN		 15494
15495 return can_issue_more;
15496}
15497
15498/* This function tries to synch the dispatch groups that the compiler "sees"
f676971a 15499 with the dispatch groups that the processor dispatcher is expected to
cbe26ab8
DN		 15500 form in practice. It tries to achieve this synchronization by forcing the
15501 estimated processor grouping on the compiler (as opposed to the function
15502 'pad_goups' which tries to force the scheduler's grouping on the processor).
15503
15504 The function scans the insn sequence between PREV_HEAD_INSN and TAIL and
15505 examines the (estimated) dispatch groups that will be formed by the processor
15506 dispatcher. It marks these group boundaries to reflect the estimated
15507 processor grouping, overriding the grouping that the scheduler had marked.
15508 Depending on the value of the flag '-minsert-sched-nops' this function can
15509 force certain insns into separate groups or force a certain distance between
15510 them by inserting nops, for example, if there exists a "costly dependence"
15511 between the insns.
15512
15513 The function estimates the group boundaries that the processor will form as
15514 folllows: It keeps track of how many vacant issue slots are available after
15515 each insn. A subsequent insn will start a new group if one of the following
15516 4 cases applies:
15517 - no more vacant issue slots remain in the current dispatch group.
15518 - only the last issue slot, which is the branch slot, is vacant, but the next
15519 insn is not a branch.
15520 - only the last 2 or less issue slots, including the branch slot, are vacant,
15521 which means that a cracked insn (which occupies two issue slots) can't be
15522 issued in this group.
f676971a 15523 - less than 'issue_rate' slots are vacant, and the next insn always needs to
cbe26ab8
DN		 15524 start a new group. */
15525
15526static int
15527redefine_groups (FILE *dump, int sched_verbose, rtx prev_head_insn, rtx tail)
15528{
15529 rtx insn, next_insn;
15530 int issue_rate;
15531 int can_issue_more;
15532 int slot, i;
15533 bool group_end;
15534 int group_count = 0;
15535 rtx *group_insns;
15536
15537 /* Initialize. */
15538 issue_rate = rs6000_issue_rate ();
15539 group_insns = alloca (issue_rate * sizeof (rtx));
f676971a 15540 for (i = 0; i < issue_rate; i++)
cbe26ab8
DN		 15541 {
15542 group_insns[i] = 0;
15543 }
15544 can_issue_more = issue_rate;
15545 slot = 0;
15546 insn = get_next_active_insn (prev_head_insn, tail);
15547 group_end = false;
15548
15549 while (insn != NULL_RTX)
15550 {
15551 slot = (issue_rate - can_issue_more);
15552 group_insns[slot] = insn;
15553 can_issue_more =
c4ad648e 15554 rs6000_variable_issue (dump, sched_verbose, insn, can_issue_more);
cbe26ab8 15555 if (insn_terminates_group_p (insn, current_group))
c4ad648e 15556 can_issue_more = 0;
cbe26ab8
DN		 15557
15558 next_insn = get_next_active_insn (insn, tail);
15559 if (next_insn == NULL_RTX)
c4ad648e 15560 return group_count + 1;
cbe26ab8 15561
c4ad648e
AM		 15562 /* Is next_insn going to start a new group? */
15563 group_end
15564 = (can_issue_more == 0
15565 || (can_issue_more == 1 && !is_branch_slot_insn (next_insn))
15566 || (can_issue_more <= 2 && is_cracked_insn (next_insn))
15567 || (can_issue_more < issue_rate &&
15568 insn_terminates_group_p (next_insn, previous_group)));
cbe26ab8 15569
f676971a 15570 can_issue_more = force_new_group (sched_verbose, dump, group_insns,
c4ad648e
AM		 15571 next_insn, &group_end, can_issue_more,
15572 &group_count);
cbe26ab8
DN		 15573
15574 if (group_end)
c4ad648e
AM		 15575 {
15576 group_count++;
15577 can_issue_more = 0;
15578 for (i = 0; i < issue_rate; i++)
15579 {
15580 group_insns[i] = 0;
15581 }
15582 }
cbe26ab8
DN		 15583
15584 if (GET_MODE (next_insn) == TImode && can_issue_more)
9390387d 15585 PUT_MODE (next_insn, VOIDmode);
cbe26ab8 15586 else if (!can_issue_more && GET_MODE (next_insn) != TImode)
c4ad648e 15587 PUT_MODE (next_insn, TImode);
cbe26ab8
DN		 15588
15589 insn = next_insn;
15590 if (can_issue_more == 0)
c4ad648e
AM		 15591 can_issue_more = issue_rate;
15592 } /* while */
cbe26ab8
DN		 15593
15594 return group_count;
15595}
15596
15597/* Scan the insn sequence between PREV_HEAD_INSN and TAIL and examine the
15598 dispatch group boundaries that the scheduler had marked. Pad with nops
15599 any dispatch groups which have vacant issue slots, in order to force the
15600 scheduler's grouping on the processor dispatcher. The function
15601 returns the number of dispatch groups found. */
15602
15603static int
15604pad_groups (FILE *dump, int sched_verbose, rtx prev_head_insn, rtx tail)
15605{
15606 rtx insn, next_insn;
15607 rtx nop;
15608 int issue_rate;
15609 int can_issue_more;
15610 int group_end;
15611 int group_count = 0;
15612
15613 /* Initialize issue_rate. */
15614 issue_rate = rs6000_issue_rate ();
15615 can_issue_more = issue_rate;
15616
15617 insn = get_next_active_insn (prev_head_insn, tail);
15618 next_insn = get_next_active_insn (insn, tail);
15619
15620 while (insn != NULL_RTX)
15621 {
15622 can_issue_more =
15623 rs6000_variable_issue (dump, sched_verbose, insn, can_issue_more);
15624
15625 group_end = (next_insn == NULL_RTX || GET_MODE (next_insn) == TImode);
15626
15627 if (next_insn == NULL_RTX)
c4ad648e 15628 break;
cbe26ab8
DN		 15629
15630 if (group_end)
c4ad648e
AM		 15631 {
15632 /* If the scheduler had marked group termination at this location
15633 (between insn and next_indn), and neither insn nor next_insn will
15634 force group termination, pad the group with nops to force group
15635 termination. */
15636 if (can_issue_more
15637 && (rs6000_sched_insert_nops == sched_finish_pad_groups)
15638 && !insn_terminates_group_p (insn, current_group)
15639 && !insn_terminates_group_p (next_insn, previous_group))
15640 {
9390387d 15641 if (!is_branch_slot_insn (next_insn))
c4ad648e
AM		 15642 can_issue_more--;
15643
15644 while (can_issue_more)
15645 {
15646 nop = gen_nop ();
15647 emit_insn_before (nop, next_insn);
15648 can_issue_more--;
15649 }
15650 }
15651
15652 can_issue_more = issue_rate;
15653 group_count++;
15654 }
cbe26ab8
DN		 15655
15656 insn = next_insn;
15657 next_insn = get_next_active_insn (insn, tail);
15658 }
15659
15660 return group_count;
15661}
15662
15663/* The following function is called at the end of scheduling BB.
15664 After reload, it inserts nops at insn group bundling. */
15665
15666static void
38f391a5 15667rs6000_sched_finish (FILE *dump, int sched_verbose)
cbe26ab8
DN		 15668{
15669 int n_groups;
15670
15671 if (sched_verbose)
15672 fprintf (dump, "=== Finishing schedule.\n");
15673
ec507f2d 15674 if (reload_completed && rs6000_sched_groups)
cbe26ab8
DN		 15675 {
15676 if (rs6000_sched_insert_nops == sched_finish_none)
c4ad648e 15677 return;
cbe26ab8
DN		 15678
15679 if (rs6000_sched_insert_nops == sched_finish_pad_groups)
c4ad648e
AM		 15680 n_groups = pad_groups (dump, sched_verbose,
15681 current_sched_info->prev_head,
15682 current_sched_info->next_tail);
cbe26ab8 15683 else
c4ad648e
AM		 15684 n_groups = redefine_groups (dump, sched_verbose,
15685 current_sched_info->prev_head,
15686 current_sched_info->next_tail);
cbe26ab8
DN		 15687
15688 if (sched_verbose >= 6)
15689 {
15690 fprintf (dump, "ngroups = %d\n", n_groups);
15691 print_rtl (dump, current_sched_info->prev_head);
15692 fprintf (dump, "Done finish_sched\n");
15693 }
15694 }
15695}
b6c9286a 15696\f
b6c9286a
MM		 15697/* Length in units of the trampoline for entering a nested function. */
15698
15699int
863d938c 15700rs6000_trampoline_size (void)
b6c9286a
MM		 15701{
15702 int ret = 0;
15703
15704 switch (DEFAULT_ABI)
15705 {
15706 default:
15707 abort ();
15708
15709 case ABI_AIX:
8f802bfb 15710 ret = (TARGET_32BIT) ? 12 : 24;
b6c9286a
MM		 15711 break;
15712
4dabc42d 15713 case ABI_DARWIN:
b6c9286a 15714 case ABI_V4:
03a7e1a5 15715 ret = (TARGET_32BIT) ? 40 : 48;
b6c9286a 15716 break;
b6c9286a
MM		 15717 }
15718
15719 return ret;
15720}
15721
15722/* Emit RTL insns to initialize the variable parts of a trampoline.
15723 FNADDR is an RTX for the address of the function's pure code.
15724 CXT is an RTX for the static chain value for the function. */
15725
15726void
a2369ed3 15727rs6000_initialize_trampoline (rtx addr, rtx fnaddr, rtx cxt)
b6c9286a 15728{
ac2a93a1 15729 enum machine_mode pmode = Pmode;
8bd04c56
MM		 15730 int regsize = (TARGET_32BIT) ? 4 : 8;
15731 rtx ctx_reg = force_reg (pmode, cxt);
b6c9286a
MM		 15732
15733 switch (DEFAULT_ABI)
15734 {
15735 default:
15736 abort ();
15737
8bd04c56 15738/* Macros to shorten the code expansions below. */
39403d82 15739#define MEM_DEREF(addr) gen_rtx_MEM (pmode, memory_address (pmode, addr))
c5c76735
JL		 15740#define MEM_PLUS(addr,offset) \
15741 gen_rtx_MEM (pmode, memory_address (pmode, plus_constant (addr, offset)))
7c59dc5d 15742
b6c9286a
MM		 15743 /* Under AIX, just build the 3 word function descriptor */
15744 case ABI_AIX:
8bd04c56
MM		 15745 {
15746 rtx fn_reg = gen_reg_rtx (pmode);
15747 rtx toc_reg = gen_reg_rtx (pmode);
15748 emit_move_insn (fn_reg, MEM_DEREF (fnaddr));
1cb18e3c 15749 emit_move_insn (toc_reg, MEM_PLUS (fnaddr, regsize));
8bd04c56
MM		 15750 emit_move_insn (MEM_DEREF (addr), fn_reg);
15751 emit_move_insn (MEM_PLUS (addr, regsize), toc_reg);
15752 emit_move_insn (MEM_PLUS (addr, 2*regsize), ctx_reg);
15753 }
b6c9286a
MM		 15754 break;
15755
4dabc42d
TC		 15756 /* Under V.4/eabi/darwin, __trampoline_setup does the real work. */
15757 case ABI_DARWIN:
b6c9286a 15758 case ABI_V4:
39403d82 15759 emit_library_call (gen_rtx_SYMBOL_REF (SImode, "__trampoline_setup"),
eaf1bcf1
MM		 15760 FALSE, VOIDmode, 4,
15761 addr, pmode,
15762 GEN_INT (rs6000_trampoline_size ()), SImode,
15763 fnaddr, pmode,
15764 ctx_reg, pmode);
b6c9286a 15765 break;
b6c9286a
MM		 15766 }
15767
15768 return;
15769}
7509c759
MM		 15770
15771\f
91d231cb 15772/* Table of valid machine attributes. */
a4f6c312 15773
91d231cb 15774const struct attribute_spec rs6000_attribute_table[] =
7509c759 15775{
91d231cb 15776 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
8bb418a3 15777 { "altivec", 1, 1, false, true, false, rs6000_handle_altivec_attribute },
a5c76ee6
ZW		 15778 { "longcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute },
15779 { "shortcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute },
005c1a13
GK		 15780#ifdef SUBTARGET_ATTRIBUTE_TABLE
15781 SUBTARGET_ATTRIBUTE_TABLE,
15782#endif
a5c76ee6 15783 { NULL, 0, 0, false, false, false, NULL }
91d231cb 15784};
7509c759 15785
8bb418a3
ZL		 15786/* Handle the "altivec" attribute. The attribute may have
15787 arguments as follows:
f676971a 15788
8bb418a3
ZL		 15789 __attribute__((altivec(vector__)))
15790 __attribute__((altivec(pixel__))) (always followed by 'unsigned short')
15791 __attribute__((altivec(bool__))) (always followed by 'unsigned')
15792
15793 and may appear more than once (e.g., 'vector bool char') in a
15794 given declaration. */
15795
15796static tree
f90ac3f0
UP		 15797rs6000_handle_altivec_attribute (tree *node,
15798 tree name ATTRIBUTE_UNUSED,
15799 tree args,
8bb418a3
ZL		 15800 int flags ATTRIBUTE_UNUSED,
15801 bool *no_add_attrs)
15802{
15803 tree type = *node, result = NULL_TREE;
15804 enum machine_mode mode;
15805 int unsigned_p;
15806 char altivec_type
15807 = ((args && TREE_CODE (args) == TREE_LIST && TREE_VALUE (args)
15808 && TREE_CODE (TREE_VALUE (args)) == IDENTIFIER_NODE)
15809 ? *IDENTIFIER_POINTER (TREE_VALUE (args))
f676971a 15810 : '?');
8bb418a3
ZL		 15811
15812 while (POINTER_TYPE_P (type)
15813 || TREE_CODE (type) == FUNCTION_TYPE
15814 || TREE_CODE (type) == METHOD_TYPE
15815 || TREE_CODE (type) == ARRAY_TYPE)
15816 type = TREE_TYPE (type);
15817
15818 mode = TYPE_MODE (type);
15819
f90ac3f0
UP		 15820 /* Check for invalid AltiVec type qualifiers. */
15821 if (type == long_unsigned_type_node || type == long_integer_type_node)
15822 {
15823 if (TARGET_64BIT)
15824 error ("use of %<long%> in AltiVec types is invalid for 64-bit code");
15825 else if (rs6000_warn_altivec_long)
15826 warning ("use of %<long%> in AltiVec types is deprecated; use %<int%>");
15827 }
15828 else if (type == long_long_unsigned_type_node
15829 || type == long_long_integer_type_node)
15830 error ("use of %<long long%> in AltiVec types is invalid");
15831 else if (type == double_type_node)
15832 error ("use of %<double%> in AltiVec types is invalid");
15833 else if (type == long_double_type_node)
15834 error ("use of %<long double%> in AltiVec types is invalid");
15835 else if (type == boolean_type_node)
15836 error ("use of boolean types in AltiVec types is invalid");
15837 else if (TREE_CODE (type) == COMPLEX_TYPE)
15838 error ("use of %<complex%> in AltiVec types is invalid");
8bb418a3
ZL		 15839
15840 switch (altivec_type)
15841 {
15842 case 'v':
8df83eae 15843 unsigned_p = TYPE_UNSIGNED (type);
8bb418a3
ZL		 15844 switch (mode)
15845 {
c4ad648e
AM		 15846 case SImode:
15847 result = (unsigned_p ? unsigned_V4SI_type_node : V4SI_type_node);
15848 break;
15849 case HImode:
15850 result = (unsigned_p ? unsigned_V8HI_type_node : V8HI_type_node);
15851 break;
15852 case QImode:
15853 result = (unsigned_p ? unsigned_V16QI_type_node : V16QI_type_node);
15854 break;
15855 case SFmode: result = V4SF_type_node; break;
15856 /* If the user says 'vector int bool', we may be handed the 'bool'
15857 attribute _before_ the 'vector' attribute, and so select the
15858 proper type in the 'b' case below. */
15859 case V4SImode: case V8HImode: case V16QImode: case V4SFmode:
15860 result = type;
15861 default: break;
8bb418a3
ZL		 15862 }
15863 break;
15864 case 'b':
15865 switch (mode)
15866 {
c4ad648e
AM		 15867 case SImode: case V4SImode: result = bool_V4SI_type_node; break;
15868 case HImode: case V8HImode: result = bool_V8HI_type_node; break;
15869 case QImode: case V16QImode: result = bool_V16QI_type_node;
15870 default: break;
8bb418a3
ZL		 15871 }
15872 break;
15873 case 'p':
15874 switch (mode)
15875 {
c4ad648e
AM		 15876 case V8HImode: result = pixel_V8HI_type_node;
15877 default: break;
8bb418a3
ZL		 15878 }
15879 default: break;
15880 }
15881
7958a2a6
FJ		 15882 if (result && result != type && TYPE_READONLY (type))
15883 result = build_qualified_type (result, TYPE_QUAL_CONST);
15884
8bb418a3
ZL		 15885 *no_add_attrs = true; /* No need to hang on to the attribute. */
15886
f90ac3f0 15887 if (result)
8bb418a3
ZL		 15888 *node = reconstruct_complex_type (*node, result);
15889
15890 return NULL_TREE;
15891}
15892
f18eca82
ZL		 15893/* AltiVec defines four built-in scalar types that serve as vector
15894 elements; we must teach the compiler how to mangle them. */
15895
15896static const char *
15897rs6000_mangle_fundamental_type (tree type)
15898{
15899 if (type == bool_char_type_node) return "U6__boolc";
15900 if (type == bool_short_type_node) return "U6__bools";
15901 if (type == pixel_type_node) return "u7__pixel";
15902 if (type == bool_int_type_node) return "U6__booli";
15903
15904 /* For all other types, use normal C++ mangling. */
15905 return NULL;
15906}
15907
a5c76ee6
ZW		 15908/* Handle a "longcall" or "shortcall" attribute; arguments as in
15909 struct attribute_spec.handler. */
a4f6c312 15910
91d231cb 15911static tree
f676971a
EC		 15912rs6000_handle_longcall_attribute (tree *node, tree name,
15913 tree args ATTRIBUTE_UNUSED,
15914 int flags ATTRIBUTE_UNUSED,
a2369ed3 15915 bool *no_add_attrs)
91d231cb
JM		 15916{
15917 if (TREE_CODE (*node) != FUNCTION_TYPE
15918 && TREE_CODE (*node) != FIELD_DECL
15919 && TREE_CODE (*node) != TYPE_DECL)
15920 {
9e637a26 15921 warning ("%qs attribute only applies to functions",
91d231cb
JM		 15922 IDENTIFIER_POINTER (name));
15923 *no_add_attrs = true;
15924 }
6a4cee5f 15925
91d231cb 15926 return NULL_TREE;
7509c759
MM		 15927}
15928
a5c76ee6
ZW		 15929/* Set longcall attributes on all functions declared when
15930 rs6000_default_long_calls is true. */
15931static void
a2369ed3 15932rs6000_set_default_type_attributes (tree type)
a5c76ee6
ZW		 15933{
15934 if (rs6000_default_long_calls
15935 && (TREE_CODE (type) == FUNCTION_TYPE
15936 || TREE_CODE (type) == METHOD_TYPE))
15937 TYPE_ATTRIBUTES (type) = tree_cons (get_identifier ("longcall"),
15938 NULL_TREE,
15939 TYPE_ATTRIBUTES (type));
15940}
15941
3cb999d8
DE		 15942/* Return a reference suitable for calling a function with the
15943 longcall attribute. */
a4f6c312 15944
9390387d 15945rtx
a2369ed3 15946rs6000_longcall_ref (rtx call_ref)
6a4cee5f 15947{
d330fd93 15948 const char *call_name;
6a4cee5f
MM		 15949 tree node;
15950
15951 if (GET_CODE (call_ref) != SYMBOL_REF)
15952 return call_ref;
15953
15954 /* System V adds '.' to the internal name, so skip them. */
15955 call_name = XSTR (call_ref, 0);
15956 if (*call_name == '.')
15957 {
15958 while (*call_name == '.')
15959 call_name++;
15960
15961 node = get_identifier (call_name);
39403d82 15962 call_ref = gen_rtx_SYMBOL_REF (VOIDmode, IDENTIFIER_POINTER (node));
6a4cee5f
MM		 15963 }
15964
15965 return force_reg (Pmode, call_ref);
15966}
7509c759 15967\f
b64a1b53
RH		 15968#ifdef USING_ELFOS_H
15969
7509c759
MM		 15970/* A C statement or statements to switch to the appropriate section
15971 for output of RTX in mode MODE. You can assume that RTX is some
15972 kind of constant in RTL. The argument MODE is redundant except in
15973 the case of a `const_int' rtx. Select the section by calling
15974 `text_section' or one of the alternatives for other sections.
15975
15976 Do not define this macro if you put all constants in the read-only
15977 data section. */
15978
b64a1b53 15979static void
f676971a 15980rs6000_elf_select_rtx_section (enum machine_mode mode, rtx x,
a2369ed3 15981 unsigned HOST_WIDE_INT align)
7509c759 15982{
a9098fd0 15983 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode))
7509c759 15984 toc_section ();
7509c759 15985 else
b64a1b53 15986 default_elf_select_rtx_section (mode, x, align);
7509c759
MM		 15987}
15988
15989/* A C statement or statements to switch to the appropriate
15990 section for output of DECL. DECL is either a `VAR_DECL' node
15991 or a constant of some sort. RELOC indicates whether forming
15992 the initial value of DECL requires link-time relocations. */
15993
ae46c4e0 15994static void
f676971a 15995rs6000_elf_select_section (tree decl, int reloc,
a2369ed3 15996 unsigned HOST_WIDE_INT align)
7509c759 15997{
f1384257
AM		 15998 /* Pretend that we're always building for a shared library when
15999 ABI_AIX, because otherwise we end up with dynamic relocations
16000 in read-only sections. This happens for function pointers,
16001 references to vtables in typeinfo, and probably other cases. */
0e5dbd9b
DE		 16002 default_elf_select_section_1 (decl, reloc, align,
16003 flag_pic || DEFAULT_ABI == ABI_AIX);
63019373
GK		 16004}
16005
16006/* A C statement to build up a unique section name, expressed as a
16007 STRING_CST node, and assign it to DECL_SECTION_NAME (decl).
16008 RELOC indicates whether the initial value of EXP requires
16009 link-time relocations. If you do not define this macro, GCC will use
16010 the symbol name prefixed by `.' as the section name. Note - this
f5143c46 16011 macro can now be called for uninitialized data items as well as
4912a07c 16012 initialized data and functions. */
63019373 16013
ae46c4e0 16014static void
a2369ed3 16015rs6000_elf_unique_section (tree decl, int reloc)
63019373 16016{
f1384257
AM		 16017 /* As above, pretend that we're always building for a shared library
16018 when ABI_AIX, to avoid dynamic relocations in read-only sections. */
0e5dbd9b
DE		 16019 default_unique_section_1 (decl, reloc,
16020 flag_pic || DEFAULT_ABI == ABI_AIX);
7509c759 16021}
d9407988 16022\f
d1908feb
JJ		 16023/* For a SYMBOL_REF, set generic flags and then perform some
16024 target-specific processing.
16025
d1908feb
JJ		 16026 When the AIX ABI is requested on a non-AIX system, replace the
16027 function name with the real name (with a leading .) rather than the
16028 function descriptor name. This saves a lot of overriding code to
16029 read the prefixes. */
d9407988 16030
fb49053f 16031static void
a2369ed3 16032rs6000_elf_encode_section_info (tree decl, rtx rtl, int first)
d9407988 16033{
d1908feb 16034 default_encode_section_info (decl, rtl, first);
b2003250 16035
d1908feb
JJ		 16036 if (first
16037 && TREE_CODE (decl) == FUNCTION_DECL
16038 && !TARGET_AIX
16039 && DEFAULT_ABI == ABI_AIX)
d9407988 16040 {
c6a2438a 16041 rtx sym_ref = XEXP (rtl, 0);
d1908feb
JJ		 16042 size_t len = strlen (XSTR (sym_ref, 0));
16043 char *str = alloca (len + 2);
16044 str[0] = '.';
16045 memcpy (str + 1, XSTR (sym_ref, 0), len + 1);
16046 XSTR (sym_ref, 0) = ggc_alloc_string (str, len + 1);
d9407988 16047 }
d9407988
MM		 16048}
16049
0e5dbd9b 16050static bool
a2369ed3 16051rs6000_elf_in_small_data_p (tree decl)
0e5dbd9b
DE		 16052{
16053 if (rs6000_sdata == SDATA_NONE)
16054 return false;
16055
7482ad25
AF		 16056 /* We want to merge strings, so we never consider them small data. */
16057 if (TREE_CODE (decl) == STRING_CST)
16058 return false;
16059
16060 /* Functions are never in the small data area. */
16061 if (TREE_CODE (decl) == FUNCTION_DECL)
16062 return false;
16063
0e5dbd9b
DE		 16064 if (TREE_CODE (decl) == VAR_DECL && DECL_SECTION_NAME (decl))
16065 {
16066 const char *section = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
16067 if (strcmp (section, ".sdata") == 0
16068 || strcmp (section, ".sdata2") == 0
20bfcd69
GK		 16069 || strcmp (section, ".sbss") == 0
16070 || strcmp (section, ".sbss2") == 0
16071 || strcmp (section, ".PPC.EMB.sdata0") == 0
16072 || strcmp (section, ".PPC.EMB.sbss0") == 0)
0e5dbd9b
DE		 16073 return true;
16074 }
16075 else
16076 {
16077 HOST_WIDE_INT size = int_size_in_bytes (TREE_TYPE (decl));
16078
16079 if (size > 0
307b599c 16080 && (unsigned HOST_WIDE_INT) size <= g_switch_value
20bfcd69
GK		 16081 /* If it's not public, and we're not going to reference it there,
16082 there's no need to put it in the small data section. */
0e5dbd9b
DE		 16083 && (rs6000_sdata != SDATA_DATA || TREE_PUBLIC (decl)))
16084 return true;
16085 }
16086
16087 return false;
16088}
16089
b91da81f 16090#endif /* USING_ELFOS_H */
000034eb 16091
a6c2a102 16092\f
000034eb 16093/* Return a REG that occurs in ADDR with coefficient 1.
02441cd6
JL		 16094 ADDR can be effectively incremented by incrementing REG.
16095
16096 r0 is special and we must not select it as an address
16097 register by this routine since our caller will try to
16098 increment the returned register via an "la" instruction. */
000034eb 16099
9390387d 16100rtx
a2369ed3 16101find_addr_reg (rtx addr)
000034eb
DE		 16102{
16103 while (GET_CODE (addr) == PLUS)
16104 {
02441cd6
JL		 16105 if (GET_CODE (XEXP (addr, 0)) == REG
16106 && REGNO (XEXP (addr, 0)) != 0)
000034eb 16107 addr = XEXP (addr, 0);
02441cd6
JL		 16108 else if (GET_CODE (XEXP (addr, 1)) == REG
16109 && REGNO (XEXP (addr, 1)) != 0)
000034eb
DE		 16110 addr = XEXP (addr, 1);
16111 else if (CONSTANT_P (XEXP (addr, 0)))
16112 addr = XEXP (addr, 1);
16113 else if (CONSTANT_P (XEXP (addr, 1)))
16114 addr = XEXP (addr, 0);
16115 else
16116 abort ();
16117 }
02441cd6 16118 if (GET_CODE (addr) == REG && REGNO (addr) != 0)
000034eb
DE		 16119 return addr;
16120 abort ();
16121}
16122
a6c2a102 16123void
a2369ed3 16124rs6000_fatal_bad_address (rtx op)
a6c2a102
DE		 16125{
16126 fatal_insn ("bad address", op);
16127}
c8023011 16128
ee890fe2
SS		 16129#if TARGET_MACHO
16130
efdba735 16131static tree branch_island_list = 0;
ee890fe2 16132
efdba735
SH		 16133/* Remember to generate a branch island for far calls to the given
16134 function. */
ee890fe2 16135
f676971a 16136static void
c4ad648e
AM		 16137add_compiler_branch_island (tree label_name, tree function_name,
16138 int line_number)
ee890fe2 16139{
efdba735 16140 tree branch_island = build_tree_list (function_name, label_name);
7d60be94 16141 TREE_TYPE (branch_island) = build_int_cst (NULL_TREE, line_number);
efdba735
SH		 16142 TREE_CHAIN (branch_island) = branch_island_list;
16143 branch_island_list = branch_island;
ee890fe2
SS		 16144}
16145
efdba735
SH		 16146#define BRANCH_ISLAND_LABEL_NAME(BRANCH_ISLAND) TREE_VALUE (BRANCH_ISLAND)
16147#define BRANCH_ISLAND_FUNCTION_NAME(BRANCH_ISLAND) TREE_PURPOSE (BRANCH_ISLAND)
16148#define BRANCH_ISLAND_LINE_NUMBER(BRANCH_ISLAND) \
16149 TREE_INT_CST_LOW (TREE_TYPE (BRANCH_ISLAND))
ee890fe2 16150
efdba735
SH		 16151/* Generate far-jump branch islands for everything on the
16152 branch_island_list. Invoked immediately after the last instruction
16153 of the epilogue has been emitted; the branch-islands must be
16154 appended to, and contiguous with, the function body. Mach-O stubs
16155 are generated in machopic_output_stub(). */
ee890fe2 16156
efdba735
SH		 16157static void
16158macho_branch_islands (void)
16159{
16160 char tmp_buf[512];
16161 tree branch_island;
16162
16163 for (branch_island = branch_island_list;
16164 branch_island;
16165 branch_island = TREE_CHAIN (branch_island))
16166 {
16167 const char *label =
16168 IDENTIFIER_POINTER (BRANCH_ISLAND_LABEL_NAME (branch_island));
16169 const char *name =
11abc112 16170 IDENTIFIER_POINTER (BRANCH_ISLAND_FUNCTION_NAME (branch_island));
efdba735
SH		 16171 char name_buf[512];
16172 /* Cheap copy of the details from the Darwin ASM_OUTPUT_LABELREF(). */
16173 if (name[0] == '*' || name[0] == '&')
16174 strcpy (name_buf, name+1);
16175 else
16176 {
16177 name_buf[0] = '_';
16178 strcpy (name_buf+1, name);
16179 }
16180 strcpy (tmp_buf, "\n");
16181 strcat (tmp_buf, label);
ee890fe2 16182#if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
efdba735 16183 if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG)
93a27b7b 16184 dbxout_stabd (N_SLINE, BRANCH_ISLAND_LINE_NUMBER (branch_island));
ee890fe2 16185#endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
efdba735
SH		 16186 if (flag_pic)
16187 {
16188 strcat (tmp_buf, ":\n\tmflr r0\n\tbcl 20,31,");
16189 strcat (tmp_buf, label);
16190 strcat (tmp_buf, "_pic\n");
16191 strcat (tmp_buf, label);
16192 strcat (tmp_buf, "_pic:\n\tmflr r11\n");
f676971a 16193
efdba735
SH		 16194 strcat (tmp_buf, "\taddis r11,r11,ha16(");
16195 strcat (tmp_buf, name_buf);
16196 strcat (tmp_buf, " - ");
16197 strcat (tmp_buf, label);
16198 strcat (tmp_buf, "_pic)\n");
f676971a 16199
efdba735 16200 strcat (tmp_buf, "\tmtlr r0\n");
f676971a 16201
efdba735
SH		 16202 strcat (tmp_buf, "\taddi r12,r11,lo16(");
16203 strcat (tmp_buf, name_buf);
16204 strcat (tmp_buf, " - ");
16205 strcat (tmp_buf, label);
16206 strcat (tmp_buf, "_pic)\n");
f676971a 16207
efdba735
SH		 16208 strcat (tmp_buf, "\tmtctr r12\n\tbctr\n");
16209 }
16210 else
16211 {
16212 strcat (tmp_buf, ":\nlis r12,hi16(");
16213 strcat (tmp_buf, name_buf);
16214 strcat (tmp_buf, ")\n\tori r12,r12,lo16(");
16215 strcat (tmp_buf, name_buf);
16216 strcat (tmp_buf, ")\n\tmtctr r12\n\tbctr");
16217 }
16218 output_asm_insn (tmp_buf, 0);
ee890fe2 16219#if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
efdba735 16220 if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG)
93a27b7b 16221 dbxout_stabd (N_SLINE, BRANCH_ISLAND_LINE_NUMBER (branch_island));
ee890fe2 16222#endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
efdba735 16223 }
ee890fe2 16224
efdba735 16225 branch_island_list = 0;
ee890fe2
SS		 16226}
16227
16228/* NO_PREVIOUS_DEF checks in the link list whether the function name is
16229 already there or not. */
16230
efdba735 16231static int
a2369ed3 16232no_previous_def (tree function_name)
ee890fe2 16233{
efdba735
SH		 16234 tree branch_island;
16235 for (branch_island = branch_island_list;
16236 branch_island;
16237 branch_island = TREE_CHAIN (branch_island))
16238 if (function_name == BRANCH_ISLAND_FUNCTION_NAME (branch_island))
ee890fe2
SS		 16239 return 0;
16240 return 1;
16241}
16242
16243/* GET_PREV_LABEL gets the label name from the previous definition of
16244 the function. */
16245
efdba735 16246static tree
a2369ed3 16247get_prev_label (tree function_name)
ee890fe2 16248{
efdba735
SH		 16249 tree branch_island;
16250 for (branch_island = branch_island_list;
16251 branch_island;
16252 branch_island = TREE_CHAIN (branch_island))
16253 if (function_name == BRANCH_ISLAND_FUNCTION_NAME (branch_island))
16254 return BRANCH_ISLAND_LABEL_NAME (branch_island);
ee890fe2
SS		 16255 return 0;
16256}
16257
16258/* INSN is either a function call or a millicode call. It may have an
f676971a 16259 unconditional jump in its delay slot.
ee890fe2
SS		 16260
16261 CALL_DEST is the routine we are calling. */
16262
16263char *
c4ad648e
AM		 16264output_call (rtx insn, rtx *operands, int dest_operand_number,
16265 int cookie_operand_number)
ee890fe2
SS		 16266{
16267 static char buf[256];
efdba735
SH		 16268 if (GET_CODE (operands[dest_operand_number]) == SYMBOL_REF
16269 && (INTVAL (operands[cookie_operand_number]) & CALL_LONG))
ee890fe2
SS		 16270 {
16271 tree labelname;
efdba735 16272 tree funname = get_identifier (XSTR (operands[dest_operand_number], 0));
f676971a 16273
ee890fe2
SS		 16274 if (no_previous_def (funname))
16275 {
308c142a 16276 int line_number = 0;
ee890fe2
SS		 16277 rtx label_rtx = gen_label_rtx ();
16278 char *label_buf, temp_buf[256];
16279 ASM_GENERATE_INTERNAL_LABEL (temp_buf, "L",
16280 CODE_LABEL_NUMBER (label_rtx));
16281 label_buf = temp_buf[0] == '*' ? temp_buf + 1 : temp_buf;
16282 labelname = get_identifier (label_buf);
16283 for (; insn && GET_CODE (insn) != NOTE; insn = PREV_INSN (insn));
16284 if (insn)
16285 line_number = NOTE_LINE_NUMBER (insn);
efdba735 16286 add_compiler_branch_island (labelname, funname, line_number);
ee890fe2
SS		 16287 }
16288 else
16289 labelname = get_prev_label (funname);
16290
efdba735
SH		 16291 /* "jbsr foo, L42" is Mach-O for "Link as 'bl foo' if a 'bl'
16292 instruction will reach 'foo', otherwise link as 'bl L42'".
16293 "L42" should be a 'branch island', that will do a far jump to
16294 'foo'. Branch islands are generated in
16295 macho_branch_islands(). */
ee890fe2 16296 sprintf (buf, "jbsr %%z%d,%.246s",
efdba735 16297 dest_operand_number, IDENTIFIER_POINTER (labelname));
ee890fe2
SS		 16298 }
16299 else
efdba735
SH		 16300 sprintf (buf, "bl %%z%d", dest_operand_number);
16301 return buf;
ee890fe2
SS		 16302}
16303
ee890fe2
SS		 16304/* Generate PIC and indirect symbol stubs. */
16305
16306void
a2369ed3 16307machopic_output_stub (FILE *file, const char *symb, const char *stub)
ee890fe2
SS		 16308{
16309 unsigned int length;
a4f6c312
SS		 16310 char *symbol_name, *lazy_ptr_name;
16311 char *local_label_0;
ee890fe2
SS		 16312 static int label = 0;
16313
df56a27f 16314 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
772c5265 16315 symb = (*targetm.strip_name_encoding) (symb);
df56a27f 16316
ee890fe2 16317
ee890fe2
SS		 16318 length = strlen (symb);
16319 symbol_name = alloca (length + 32);
16320 GEN_SYMBOL_NAME_FOR_SYMBOL (symbol_name, symb, length);
16321
16322 lazy_ptr_name = alloca (length + 32);
16323 GEN_LAZY_PTR_NAME_FOR_SYMBOL (lazy_ptr_name, symb, length);
16324
ee890fe2 16325 if (flag_pic == 2)
d3c300d2 16326 machopic_picsymbol_stub1_section ();
ee890fe2 16327 else
d3c300d2 16328 machopic_symbol_stub1_section ();
ee890fe2
SS		 16329
16330 if (flag_pic == 2)
16331 {
d974312d
DJ		 16332 fprintf (file, "\t.align 5\n");
16333
16334 fprintf (file, "%s:\n", stub);
16335 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
16336
876455fa 16337 label++;
9390387d 16338 local_label_0 = alloca (sizeof ("\"L0000000000$spb\""));
876455fa 16339 sprintf (local_label_0, "\"L%011d$spb\"", label);
f676971a 16340
ee890fe2
SS		 16341 fprintf (file, "\tmflr r0\n");
16342 fprintf (file, "\tbcl 20,31,%s\n", local_label_0);
16343 fprintf (file, "%s:\n\tmflr r11\n", local_label_0);
16344 fprintf (file, "\taddis r11,r11,ha16(%s-%s)\n",
16345 lazy_ptr_name, local_label_0);
16346 fprintf (file, "\tmtlr r0\n");
3d0e2d58
SS		 16347 fprintf (file, "\t%s r12,lo16(%s-%s)(r11)\n",
16348 (TARGET_64BIT ? "ldu" : "lwzu"),
ee890fe2
SS		 16349 lazy_ptr_name, local_label_0);
16350 fprintf (file, "\tmtctr r12\n");
ee890fe2
SS		 16351 fprintf (file, "\tbctr\n");
16352 }
16353 else
d974312d
DJ		 16354 {
16355 fprintf (file, "\t.align 4\n");
16356
16357 fprintf (file, "%s:\n", stub);
16358 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
16359
16360 fprintf (file, "\tlis r11,ha16(%s)\n", lazy_ptr_name);
d9e4e4f5
SS		 16361 fprintf (file, "\t%s r12,lo16(%s)(r11)\n",
16362 (TARGET_64BIT ? "ldu" : "lwzu"),
16363 lazy_ptr_name);
d974312d
DJ		 16364 fprintf (file, "\tmtctr r12\n");
16365 fprintf (file, "\tbctr\n");
16366 }
f676971a 16367
ee890fe2
SS		 16368 machopic_lazy_symbol_ptr_section ();
16369 fprintf (file, "%s:\n", lazy_ptr_name);
16370 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
49bd1d27
SS		 16371 fprintf (file, "%sdyld_stub_binding_helper\n",
16372 (TARGET_64BIT ? DOUBLE_INT_ASM_OP : "\t.long\t"));
ee890fe2
SS		 16373}
16374
16375/* Legitimize PIC addresses. If the address is already
16376 position-independent, we return ORIG. Newly generated
16377 position-independent addresses go into a reg. This is REG if non
16378 zero, otherwise we allocate register(s) as necessary. */
16379
9390387d 16380#define SMALL_INT(X) ((unsigned) (INTVAL (X) + 0x8000) < 0x10000)
ee890fe2
SS		 16381
16382rtx
f676971a 16383rs6000_machopic_legitimize_pic_address (rtx orig, enum machine_mode mode,
a2369ed3 16384 rtx reg)
ee890fe2
SS		 16385{
16386 rtx base, offset;
16387
16388 if (reg == NULL && ! reload_in_progress && ! reload_completed)
16389 reg = gen_reg_rtx (Pmode);
16390
16391 if (GET_CODE (orig) == CONST)
16392 {
16393 if (GET_CODE (XEXP (orig, 0)) == PLUS
16394 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
16395 return orig;
16396
16397 if (GET_CODE (XEXP (orig, 0)) == PLUS)
16398 {
2cf520bf 16399 /* Use a different reg for the intermediate value, as
a3c9585f 16400 it will be marked UNCHANGING. */
2cf520bf
GK		 16401 rtx reg_temp = no_new_pseudos ? reg : gen_reg_rtx (Pmode);
16402
a4f6c312
SS		 16403 base =
16404 rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 0),
2cf520bf 16405 Pmode, reg_temp);
a4f6c312
SS		 16406 offset =
16407 rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 1),
16408 Pmode, reg);
ee890fe2
SS		 16409 }
16410 else
16411 abort ();
16412
16413 if (GET_CODE (offset) == CONST_INT)
16414 {
16415 if (SMALL_INT (offset))
ed8908e7 16416 return plus_constant (base, INTVAL (offset));
ee890fe2
SS		 16417 else if (! reload_in_progress && ! reload_completed)
16418 offset = force_reg (Pmode, offset);
16419 else
c859cda6
DJ		 16420 {
16421 rtx mem = force_const_mem (Pmode, orig);
16422 return machopic_legitimize_pic_address (mem, Pmode, reg);
16423 }
ee890fe2 16424 }
f1c25d3b 16425 return gen_rtx_PLUS (Pmode, base, offset);
ee890fe2
SS		 16426 }
16427
16428 /* Fall back on generic machopic code. */
16429 return machopic_legitimize_pic_address (orig, mode, reg);
16430}
16431
16432/* This is just a placeholder to make linking work without having to
16433 add this to the generic Darwin EXTRA_SECTIONS. If -mcall-aix is
16434 ever needed for Darwin (not too likely!) this would have to get a
16435 real definition. */
16436
16437void
863d938c 16438toc_section (void)
ee890fe2
SS		 16439{
16440}
16441
c4e18b1c
GK		 16442/* Output a .machine directive for the Darwin assembler, and call
16443 the generic start_file routine. */
16444
16445static void
16446rs6000_darwin_file_start (void)
16447{
94ff898d 16448 static const struct
c4e18b1c
GK		 16449 {
16450 const char *arg;
16451 const char *name;
16452 int if_set;
16453 } mapping[] = {
55dbfb48 16454 { "ppc64", "ppc64", MASK_64BIT },
c4e18b1c
GK		 16455 { "970", "ppc970", MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64 },
16456 { "power4", "ppc970", 0 },
16457 { "G5", "ppc970", 0 },
16458 { "7450", "ppc7450", 0 },
16459 { "7400", "ppc7400", MASK_ALTIVEC },
16460 { "G4", "ppc7400", 0 },
16461 { "750", "ppc750", 0 },
16462 { "740", "ppc750", 0 },
16463 { "G3", "ppc750", 0 },
16464 { "604e", "ppc604e", 0 },
16465 { "604", "ppc604", 0 },
16466 { "603e", "ppc603", 0 },
16467 { "603", "ppc603", 0 },
16468 { "601", "ppc601", 0 },
16469 { NULL, "ppc", 0 } };
16470 const char *cpu_id = "";
16471 size_t i;
94ff898d 16472
9390387d 16473 rs6000_file_start ();
c4e18b1c
GK		 16474
16475 /* Determine the argument to -mcpu=. Default to G3 if not specified. */
16476 for (i = 0; i < ARRAY_SIZE (rs6000_select); i++)
16477 if (rs6000_select[i].set_arch_p && rs6000_select[i].string
16478 && rs6000_select[i].string[0] != '\0')
16479 cpu_id = rs6000_select[i].string;
16480
16481 /* Look through the mapping array. Pick the first name that either
16482 matches the argument, has a bit set in IF_SET that is also set
16483 in the target flags, or has a NULL name. */
16484
16485 i = 0;
16486 while (mapping[i].arg != NULL
16487 && strcmp (mapping[i].arg, cpu_id) != 0
16488 && (mapping[i].if_set & target_flags) == 0)
16489 i++;
16490
16491 fprintf (asm_out_file, "\t.machine %s\n", mapping[i].name);
16492}
16493
ee890fe2 16494#endif /* TARGET_MACHO */
7c262518
RH		 16495
16496#if TARGET_ELF
16497static unsigned int
a2369ed3 16498rs6000_elf_section_type_flags (tree decl, const char *name, int reloc)
7c262518 16499{
1ff8f81a
AM		 16500 return default_section_type_flags_1 (decl, name, reloc,
16501 flag_pic || DEFAULT_ABI == ABI_AIX);
7c262518 16502}
d9f6800d
RH		 16503
16504/* Record an element in the table of global constructors. SYMBOL is
16505 a SYMBOL_REF of the function to be called; PRIORITY is a number
16506 between 0 and MAX_INIT_PRIORITY.
16507
16508 This differs from default_named_section_asm_out_constructor in
16509 that we have special handling for -mrelocatable. */
16510
16511static void
a2369ed3 16512rs6000_elf_asm_out_constructor (rtx symbol, int priority)
d9f6800d
RH		 16513{
16514 const char *section = ".ctors";
16515 char buf[16];
16516
16517 if (priority != DEFAULT_INIT_PRIORITY)
16518 {
16519 sprintf (buf, ".ctors.%.5u",
c4ad648e
AM		 16520 /* Invert the numbering so the linker puts us in the proper
16521 order; constructors are run from right to left, and the
16522 linker sorts in increasing order. */
16523 MAX_INIT_PRIORITY - priority);
d9f6800d
RH		 16524 section = buf;
16525 }
16526
715bdd29
RH		 16527 named_section_flags (section, SECTION_WRITE);
16528 assemble_align (POINTER_SIZE);
d9f6800d
RH		 16529
16530 if (TARGET_RELOCATABLE)
16531 {
16532 fputs ("\t.long (", asm_out_file);
16533 output_addr_const (asm_out_file, symbol);
16534 fputs (")@fixup\n", asm_out_file);
16535 }
16536 else
c8af3574 16537 assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1);
d9f6800d
RH		 16538}
16539
16540static void
a2369ed3 16541rs6000_elf_asm_out_destructor (rtx symbol, int priority)
d9f6800d
RH		 16542{
16543 const char *section = ".dtors";
16544 char buf[16];
16545
16546 if (priority != DEFAULT_INIT_PRIORITY)
16547 {
16548 sprintf (buf, ".dtors.%.5u",
c4ad648e
AM		 16549 /* Invert the numbering so the linker puts us in the proper
16550 order; constructors are run from right to left, and the
16551 linker sorts in increasing order. */
16552 MAX_INIT_PRIORITY - priority);
d9f6800d
RH		 16553 section = buf;
16554 }
16555
715bdd29
RH		 16556 named_section_flags (section, SECTION_WRITE);
16557 assemble_align (POINTER_SIZE);
d9f6800d
RH		 16558
16559 if (TARGET_RELOCATABLE)
16560 {
16561 fputs ("\t.long (", asm_out_file);
16562 output_addr_const (asm_out_file, symbol);
16563 fputs (")@fixup\n", asm_out_file);
16564 }
16565 else
c8af3574 16566 assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1);
d9f6800d 16567}
9739c90c
JJ		 16568
16569void
a2369ed3 16570rs6000_elf_declare_function_name (FILE *file, const char *name, tree decl)
9739c90c
JJ		 16571{
16572 if (TARGET_64BIT)
16573 {
16574 fputs ("\t.section\t\".opd\",\"aw\"\n\t.align 3\n", file);
16575 ASM_OUTPUT_LABEL (file, name);
16576 fputs (DOUBLE_INT_ASM_OP, file);
85b776df
AM		 16577 rs6000_output_function_entry (file, name);
16578 fputs (",.TOC.@tocbase,0\n\t.previous\n", file);
16579 if (DOT_SYMBOLS)
9739c90c 16580 {
85b776df 16581 fputs ("\t.size\t", file);
9739c90c 16582 assemble_name (file, name);
85b776df
AM		 16583 fputs (",24\n\t.type\t.", file);
16584 assemble_name (file, name);
16585 fputs (",@function\n", file);
16586 if (TREE_PUBLIC (decl) && ! DECL_WEAK (decl))
16587 {
16588 fputs ("\t.globl\t.", file);
16589 assemble_name (file, name);
16590 putc ('\n', file);
16591 }
9739c90c 16592 }
85b776df
AM		 16593 else
16594 ASM_OUTPUT_TYPE_DIRECTIVE (file, name, "function");
9739c90c 16595 ASM_DECLARE_RESULT (file, DECL_RESULT (decl));
85b776df
AM		 16596 rs6000_output_function_entry (file, name);
16597 fputs (":\n", file);
9739c90c
JJ		 16598 return;
16599 }
16600
16601 if (TARGET_RELOCATABLE
16602 && (get_pool_size () != 0 || current_function_profile)
3c9eb5f4 16603 && uses_TOC ())
9739c90c
JJ		 16604 {
16605 char buf[256];
16606
16607 (*targetm.asm_out.internal_label) (file, "LCL", rs6000_pic_labelno);
16608
16609 ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1);
16610 fprintf (file, "\t.long ");
16611 assemble_name (file, buf);
16612 putc ('-', file);
16613 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
16614 assemble_name (file, buf);
16615 putc ('\n', file);
16616 }
16617
16618 ASM_OUTPUT_TYPE_DIRECTIVE (file, name, "function");
16619 ASM_DECLARE_RESULT (file, DECL_RESULT (decl));
16620
16621 if (DEFAULT_ABI == ABI_AIX)
16622 {
16623 const char *desc_name, *orig_name;
16624
16625 orig_name = (*targetm.strip_name_encoding) (name);
16626 desc_name = orig_name;
16627 while (*desc_name == '.')
16628 desc_name++;
16629
16630 if (TREE_PUBLIC (decl))
16631 fprintf (file, "\t.globl %s\n", desc_name);
16632
16633 fprintf (file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
16634 fprintf (file, "%s:\n", desc_name);
16635 fprintf (file, "\t.long %s\n", orig_name);
16636 fputs ("\t.long _GLOBAL_OFFSET_TABLE_\n", file);
16637 if (DEFAULT_ABI == ABI_AIX)
16638 fputs ("\t.long 0\n", file);
16639 fprintf (file, "\t.previous\n");
16640 }
16641 ASM_OUTPUT_LABEL (file, name);
16642}
7c262518
RH		 16643#endif
16644
cbaaba19 16645#if TARGET_XCOFF
7c262518 16646static void
a2369ed3 16647rs6000_xcoff_asm_globalize_label (FILE *stream, const char *name)
b275d088
DE		 16648{
16649 fputs (GLOBAL_ASM_OP, stream);
16650 RS6000_OUTPUT_BASENAME (stream, name);
16651 putc ('\n', stream);
16652}
16653
16654static void
c18a5b6c
MM		 16655rs6000_xcoff_asm_named_section (const char *name, unsigned int flags,
16656 tree decl ATTRIBUTE_UNUSED)
7c262518 16657{
0e5dbd9b
DE		 16658 int smclass;
16659 static const char * const suffix[3] = { "PR", "RO", "RW" };
16660
16661 if (flags & SECTION_CODE)
16662 smclass = 0;
16663 else if (flags & SECTION_WRITE)
16664 smclass = 2;
16665 else
16666 smclass = 1;
16667
5b5198f7 16668 fprintf (asm_out_file, "\t.csect %s%s[%s],%u\n",
0e5dbd9b 16669 (flags & SECTION_CODE) ? "." : "",
5b5198f7 16670 name, suffix[smclass], flags & SECTION_ENTSIZE);
7c262518 16671}
ae46c4e0
RH		 16672
16673static void
f676971a 16674rs6000_xcoff_select_section (tree decl, int reloc,
c4ad648e 16675 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
ae46c4e0 16676{
5add3202 16677 if (decl_readonly_section_1 (decl, reloc, 1))
ae46c4e0 16678 {
0e5dbd9b 16679 if (TREE_PUBLIC (decl))
c4ad648e 16680 read_only_data_section ();
ae46c4e0 16681 else
c4ad648e 16682 read_only_private_data_section ();
ae46c4e0
RH		 16683 }
16684 else
16685 {
0e5dbd9b 16686 if (TREE_PUBLIC (decl))
c4ad648e 16687 data_section ();
ae46c4e0 16688 else
c4ad648e 16689 private_data_section ();
ae46c4e0
RH		 16690 }
16691}
16692
16693static void
a2369ed3 16694rs6000_xcoff_unique_section (tree decl, int reloc ATTRIBUTE_UNUSED)
ae46c4e0
RH		 16695{
16696 const char *name;
ae46c4e0 16697
5b5198f7
DE		 16698 /* Use select_section for private and uninitialized data. */
16699 if (!TREE_PUBLIC (decl)
16700 || DECL_COMMON (decl)
0e5dbd9b
DE		 16701 || DECL_INITIAL (decl) == NULL_TREE
16702 || DECL_INITIAL (decl) == error_mark_node
16703 || (flag_zero_initialized_in_bss
16704 && initializer_zerop (DECL_INITIAL (decl))))
16705 return;
16706
16707 name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
16708 name = (*targetm.strip_name_encoding) (name);
16709 DECL_SECTION_NAME (decl) = build_string (strlen (name), name);
ae46c4e0 16710}
b64a1b53 16711
fb49053f
RH		 16712/* Select section for constant in constant pool.
16713
16714 On RS/6000, all constants are in the private read-only data area.
16715 However, if this is being placed in the TOC it must be output as a
16716 toc entry. */
16717
b64a1b53 16718static void
f676971a 16719rs6000_xcoff_select_rtx_section (enum machine_mode mode, rtx x,
c4ad648e 16720 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
b64a1b53
RH		 16721{
16722 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode))
16723 toc_section ();
16724 else
16725 read_only_private_data_section ();
16726}
772c5265
RH		 16727
16728/* Remove any trailing [DS] or the like from the symbol name. */
16729
16730static const char *
a2369ed3 16731rs6000_xcoff_strip_name_encoding (const char *name)
772c5265
RH		 16732{
16733 size_t len;
16734 if (*name == '*')
16735 name++;
16736 len = strlen (name);
16737 if (name[len - 1] == ']')
16738 return ggc_alloc_string (name, len - 4);
16739 else
16740 return name;
16741}
16742
5add3202
DE		 16743/* Section attributes. AIX is always PIC. */
16744
16745static unsigned int
a2369ed3 16746rs6000_xcoff_section_type_flags (tree decl, const char *name, int reloc)
5add3202 16747{
5b5198f7
DE		 16748 unsigned int align;
16749 unsigned int flags = default_section_type_flags_1 (decl, name, reloc, 1);
16750
16751 /* Align to at least UNIT size. */
16752 if (flags & SECTION_CODE)
16753 align = MIN_UNITS_PER_WORD;
16754 else
16755 /* Increase alignment of large objects if not already stricter. */
16756 align = MAX ((DECL_ALIGN (decl) / BITS_PER_UNIT),
16757 int_size_in_bytes (TREE_TYPE (decl)) > MIN_UNITS_PER_WORD
16758 ? UNITS_PER_FP_WORD : MIN_UNITS_PER_WORD);
16759
16760 return flags | (exact_log2 (align) & SECTION_ENTSIZE);
5add3202 16761}
a5fe455b 16762
1bc7c5b6
ZW		 16763/* Output at beginning of assembler file.
16764
16765 Initialize the section names for the RS/6000 at this point.
16766
16767 Specify filename, including full path, to assembler.
16768
16769 We want to go into the TOC section so at least one .toc will be emitted.
16770 Also, in order to output proper .bs/.es pairs, we need at least one static
16771 [RW] section emitted.
16772
16773 Finally, declare mcount when profiling to make the assembler happy. */
16774
16775static void
863d938c 16776rs6000_xcoff_file_start (void)
1bc7c5b6
ZW		 16777{
16778 rs6000_gen_section_name (&xcoff_bss_section_name,
16779 main_input_filename, ".bss_");
16780 rs6000_gen_section_name (&xcoff_private_data_section_name,
16781 main_input_filename, ".rw_");
16782 rs6000_gen_section_name (&xcoff_read_only_section_name,
16783 main_input_filename, ".ro_");
16784
16785 fputs ("\t.file\t", asm_out_file);
16786 output_quoted_string (asm_out_file, main_input_filename);
16787 fputc ('\n', asm_out_file);
1bc7c5b6
ZW		 16788 if (write_symbols != NO_DEBUG)
16789 private_data_section ();
16790 text_section ();
16791 if (profile_flag)
16792 fprintf (asm_out_file, "\t.extern %s\n", RS6000_MCOUNT);
16793 rs6000_file_start ();
16794}
16795
a5fe455b
ZW		 16796/* Output at end of assembler file.
16797 On the RS/6000, referencing data should automatically pull in text. */
16798
16799static void
863d938c 16800rs6000_xcoff_file_end (void)
a5fe455b
ZW		 16801{
16802 text_section ();
16803 fputs ("_section_.text:\n", asm_out_file);
16804 data_section ();
16805 fputs (TARGET_32BIT
16806 ? "\t.long _section_.text\n" : "\t.llong _section_.text\n",
16807 asm_out_file);
16808}
f1384257 16809#endif /* TARGET_XCOFF */
0e5dbd9b 16810
f1384257
AM		 16811#if TARGET_MACHO
16812/* Cross-module name binding. Darwin does not support overriding
7f3d8013 16813 functions at dynamic-link time. */
0e5dbd9b 16814
2bcc50d0 16815static bool
a2369ed3 16816rs6000_binds_local_p (tree decl)
0e5dbd9b 16817{
f1384257 16818 return default_binds_local_p_1 (decl, 0);
0e5dbd9b 16819}
f1384257 16820#endif
34bb030a 16821
3c50106f
RH		 16822/* Compute a (partial) cost for rtx X. Return true if the complete
16823 cost has been computed, and false if subexpressions should be
16824 scanned. In either case, *TOTAL contains the cost result. */
16825
16826static bool
1494c534 16827rs6000_rtx_costs (rtx x, int code, int outer_code, int *total)
3c50106f 16828{
f0517163
RS		 16829 enum machine_mode mode = GET_MODE (x);
16830
3c50106f
RH		 16831 switch (code)
16832 {
30a555d9 16833 /* On the RS/6000, if it is valid in the insn, it is free. */
3c50106f 16834 case CONST_INT:
066cd967
DE		 16835 if (((outer_code == SET
16836 || outer_code == PLUS
16837 || outer_code == MINUS)
16838 && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'I')
16839 || CONST_OK_FOR_LETTER_P (INTVAL (x), 'L')))
066cd967
DE		 16840 || (outer_code == AND
16841 && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'K')
22e54023
DE		 16842 || (CONST_OK_FOR_LETTER_P (INTVAL (x),
16843 mode == SImode ? 'L' : 'J'))
d5861a7a 16844 || mask_operand (x, VOIDmode)))
22e54023
DE		 16845 || ((outer_code == IOR || outer_code == XOR)
16846 && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'K')
16847 || (CONST_OK_FOR_LETTER_P (INTVAL (x),
16848 mode == SImode ? 'L' : 'J'))))
066cd967
DE		 16849 || outer_code == ASHIFT
16850 || outer_code == ASHIFTRT
16851 || outer_code == LSHIFTRT
16852 || outer_code == ROTATE
16853 || outer_code == ROTATERT
d5861a7a 16854 || outer_code == ZERO_EXTRACT
066cd967
DE		 16855 || (outer_code == MULT
16856 && CONST_OK_FOR_LETTER_P (INTVAL (x), 'I'))
22e54023
DE		 16857 || ((outer_code == DIV || outer_code == UDIV
16858 || outer_code == MOD || outer_code == UMOD)
16859 && exact_log2 (INTVAL (x)) >= 0)
066cd967
DE		 16860 || (outer_code == COMPARE
16861 && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'I')
22e54023
DE		 16862 || CONST_OK_FOR_LETTER_P (INTVAL (x), 'K')))
16863 || (outer_code == EQ
16864 && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'I')
16865 || CONST_OK_FOR_LETTER_P (INTVAL (x), 'K')
16866 || (CONST_OK_FOR_LETTER_P (INTVAL (x),
16867 mode == SImode ? 'L' : 'J'))))
16868 || (outer_code == GTU
16869 && CONST_OK_FOR_LETTER_P (INTVAL (x), 'I'))
16870 || (outer_code == LTU
16871 && CONST_OK_FOR_LETTER_P (INTVAL (x), 'P')))
066cd967
DE		 16872 {
16873 *total = 0;
16874 return true;
16875 }
16876 else if ((outer_code == PLUS
16877 && reg_or_add_cint64_operand (x, VOIDmode))
16878 || (outer_code == MINUS
16879 && reg_or_sub_cint64_operand (x, VOIDmode))
16880 || ((outer_code == SET
16881 || outer_code == IOR
16882 || outer_code == XOR)
16883 && (INTVAL (x)
16884 & ~ (unsigned HOST_WIDE_INT) 0xffffffff) == 0))
16885 {
16886 *total = COSTS_N_INSNS (1);
16887 return true;
16888 }
16889 /* FALLTHRU */
16890
16891 case CONST_DOUBLE:
16892 if (mode == DImode
16893 && ((outer_code == AND
16894 && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'K')
16895 || CONST_OK_FOR_LETTER_P (INTVAL (x), 'L')
d5861a7a 16896 || mask64_operand (x, DImode)))
066cd967
DE		 16897 || ((outer_code == IOR || outer_code == XOR)
16898 && CONST_DOUBLE_HIGH (x) == 0
16899 && (CONST_DOUBLE_LOW (x)
16900 & ~ (unsigned HOST_WIDE_INT) 0xffff) == 0)))
16901 {
16902 *total = 0;
16903 return true;
16904 }
16905 else if (mode == DImode
16906 && (outer_code == SET
16907 || outer_code == IOR
16908 || outer_code == XOR)
16909 && CONST_DOUBLE_HIGH (x) == 0)
16910 {
16911 *total = COSTS_N_INSNS (1);
16912 return true;
16913 }
16914 /* FALLTHRU */
16915
3c50106f 16916 case CONST:
066cd967 16917 case HIGH:
3c50106f 16918 case SYMBOL_REF:
066cd967
DE		 16919 case MEM:
16920 /* When optimizing for size, MEM should be slightly more expensive
16921 than generating address, e.g., (plus (reg) (const)).
c112cf2b 16922 L1 cache latency is about two instructions. */
066cd967 16923 *total = optimize_size ? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (2);
3c50106f
RH		 16924 return true;
16925
30a555d9
DE		 16926 case LABEL_REF:
16927 *total = 0;
16928 return true;
16929
3c50106f 16930 case PLUS:
f0517163 16931 if (mode == DFmode)
066cd967
DE		 16932 {
16933 if (GET_CODE (XEXP (x, 0)) == MULT)
16934 {
16935 /* FNMA accounted in outer NEG. */
16936 if (outer_code == NEG)
16937 *total = rs6000_cost->dmul - rs6000_cost->fp;
16938 else
16939 *total = rs6000_cost->dmul;
16940 }
16941 else
16942 *total = rs6000_cost->fp;
16943 }
f0517163 16944 else if (mode == SFmode)
066cd967
DE		 16945 {
16946 /* FNMA accounted in outer NEG. */
16947 if (outer_code == NEG && GET_CODE (XEXP (x, 0)) == MULT)
16948 *total = 0;
16949 else
16950 *total = rs6000_cost->fp;
16951 }
938bf747
RS		 16952 else if (GET_CODE (XEXP (x, 0)) == MULT)
16953 {
16954 /* The rs6000 doesn't have shift-and-add instructions. */
16955 rs6000_rtx_costs (XEXP (x, 0), MULT, PLUS, total);
16956 *total += COSTS_N_INSNS (1);
16957 }
f0517163 16958 else
066cd967
DE		 16959 *total = COSTS_N_INSNS (1);
16960 return false;
3c50106f 16961
52190329 16962 case MINUS:
f0517163 16963 if (mode == DFmode)
066cd967
DE		 16964 {
16965 if (GET_CODE (XEXP (x, 0)) == MULT)
16966 {
16967 /* FNMA accounted in outer NEG. */
16968 if (outer_code == NEG)
16969 *total = 0;
16970 else
16971 *total = rs6000_cost->dmul;
16972 }
16973 else
16974 *total = rs6000_cost->fp;
16975 }
f0517163 16976 else if (mode == SFmode)
066cd967
DE		 16977 {
16978 /* FNMA accounted in outer NEG. */
16979 if (outer_code == NEG && GET_CODE (XEXP (x, 0)) == MULT)
16980 *total = 0;
16981 else
16982 *total = rs6000_cost->fp;
16983 }
938bf747
RS		 16984 else if (GET_CODE (XEXP (x, 0)) == MULT)
16985 {
16986 /* The rs6000 doesn't have shift-and-sub instructions. */
16987 rs6000_rtx_costs (XEXP (x, 0), MULT, MINUS, total);
16988 *total += COSTS_N_INSNS (1);
16989 }
f0517163 16990 else
c4ad648e 16991 *total = COSTS_N_INSNS (1);
066cd967 16992 return false;
3c50106f
RH		 16993
16994 case MULT:
c9dbf840
DE		 16995 if (GET_CODE (XEXP (x, 1)) == CONST_INT
16996 && CONST_OK_FOR_LETTER_P (INTVAL (XEXP (x, 1)), 'I'))
3c50106f 16997 {
8b897cfa
RS		 16998 if (INTVAL (XEXP (x, 1)) >= -256
16999 && INTVAL (XEXP (x, 1)) <= 255)
06a67bdd 17000 *total = rs6000_cost->mulsi_const9;
8b897cfa 17001 else
06a67bdd 17002 *total = rs6000_cost->mulsi_const;
3c50106f 17003 }
066cd967
DE		 17004 /* FMA accounted in outer PLUS/MINUS. */
17005 else if ((mode == DFmode || mode == SFmode)
17006 && (outer_code == PLUS || outer_code == MINUS))
17007 *total = 0;
f0517163 17008 else if (mode == DFmode)
06a67bdd 17009 *total = rs6000_cost->dmul;
f0517163 17010 else if (mode == SFmode)
06a67bdd 17011 *total = rs6000_cost->fp;
f0517163 17012 else if (mode == DImode)
06a67bdd 17013 *total = rs6000_cost->muldi;
8b897cfa 17014 else
06a67bdd 17015 *total = rs6000_cost->mulsi;
066cd967 17016 return false;
3c50106f
RH		 17017
17018 case DIV:
17019 case MOD:
f0517163
RS		 17020 if (FLOAT_MODE_P (mode))
17021 {
06a67bdd
RS		 17022 *total = mode == DFmode ? rs6000_cost->ddiv
17023 : rs6000_cost->sdiv;
066cd967 17024 return false;
f0517163 17025 }
5efb1046 17026 /* FALLTHRU */
3c50106f
RH		 17027
17028 case UDIV:
17029 case UMOD:
627b6fe2
DJ		 17030 if (GET_CODE (XEXP (x, 1)) == CONST_INT
17031 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0)
17032 {
17033 if (code == DIV || code == MOD)
17034 /* Shift, addze */
17035 *total = COSTS_N_INSNS (2);
17036 else
17037 /* Shift */
17038 *total = COSTS_N_INSNS (1);
17039 }
c4ad648e 17040 else
627b6fe2
DJ		 17041 {
17042 if (GET_MODE (XEXP (x, 1)) == DImode)
17043 *total = rs6000_cost->divdi;
17044 else
17045 *total = rs6000_cost->divsi;
17046 }
17047 /* Add in shift and subtract for MOD. */
17048 if (code == MOD || code == UMOD)
17049 *total += COSTS_N_INSNS (2);
066cd967 17050 return false;
3c50106f
RH		 17051
17052 case FFS:
17053 *total = COSTS_N_INSNS (4);
066cd967 17054 return false;
3c50106f 17055
06a67bdd 17056 case NOT:
066cd967
DE		 17057 if (outer_code == AND || outer_code == IOR || outer_code == XOR)
17058 {
17059 *total = 0;
17060 return false;
17061 }
17062 /* FALLTHRU */
17063
17064 case AND:
17065 case IOR:
17066 case XOR:
d5861a7a
DE		 17067 case ZERO_EXTRACT:
17068 *total = COSTS_N_INSNS (1);
17069 return false;
17070
066cd967
DE		 17071 case ASHIFT:
17072 case ASHIFTRT:
17073 case LSHIFTRT:
17074 case ROTATE:
17075 case ROTATERT:
d5861a7a 17076 /* Handle mul_highpart. */
066cd967
DE		 17077 if (outer_code == TRUNCATE
17078 && GET_CODE (XEXP (x, 0)) == MULT)
17079 {
17080 if (mode == DImode)
17081 *total = rs6000_cost->muldi;
17082 else
17083 *total = rs6000_cost->mulsi;
17084 return true;
17085 }
d5861a7a
DE		 17086 else if (outer_code == AND)
17087 *total = 0;
17088 else
17089 *total = COSTS_N_INSNS (1);
17090 return false;
17091
17092 case SIGN_EXTEND:
17093 case ZERO_EXTEND:
17094 if (GET_CODE (XEXP (x, 0)) == MEM)
17095 *total = 0;
17096 else
17097 *total = COSTS_N_INSNS (1);
066cd967 17098 return false;
06a67bdd 17099
066cd967
DE		 17100 case COMPARE:
17101 case NEG:
17102 case ABS:
17103 if (!FLOAT_MODE_P (mode))
17104 {
17105 *total = COSTS_N_INSNS (1);
17106 return false;
17107 }
17108 /* FALLTHRU */
17109
17110 case FLOAT:
17111 case UNSIGNED_FLOAT:
17112 case FIX:
17113 case UNSIGNED_FIX:
17114 case FLOAT_EXTEND:
06a67bdd
RS		 17115 case FLOAT_TRUNCATE:
17116 *total = rs6000_cost->fp;
066cd967 17117 return false;
06a67bdd
RS		 17118
17119 case UNSPEC:
17120 switch (XINT (x, 1))
17121 {
17122 case UNSPEC_FRSP:
17123 *total = rs6000_cost->fp;
17124 return true;
17125
17126 default:
17127 break;
17128 }
17129 break;
17130
17131 case CALL:
17132 case IF_THEN_ELSE:
17133 if (optimize_size)
17134 {
17135 *total = COSTS_N_INSNS (1);
17136 return true;
17137 }
066cd967
DE		 17138 else if (FLOAT_MODE_P (mode)
17139 && TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS)
17140 {
17141 *total = rs6000_cost->fp;
17142 return false;
17143 }
06a67bdd
RS		 17144 break;
17145
c0600ecd
DE		 17146 case EQ:
17147 case GTU:
17148 case LTU:
22e54023
DE		 17149 /* Carry bit requires mode == Pmode.
17150 NEG or PLUS already counted so only add one. */
17151 if (mode == Pmode
17152 && (outer_code == NEG || outer_code == PLUS))
c0600ecd 17153 {
22e54023
DE		 17154 *total = COSTS_N_INSNS (1);
17155 return true;
17156 }
17157 if (outer_code == SET)
17158 {
17159 if (XEXP (x, 1) == const0_rtx)
c0600ecd 17160 {
22e54023 17161 *total = COSTS_N_INSNS (2);
c0600ecd 17162 return true;
c0600ecd 17163 }
22e54023
DE		 17164 else if (mode == Pmode)
17165 {
17166 *total = COSTS_N_INSNS (3);
17167 return false;
17168 }
17169 }
17170 /* FALLTHRU */
17171
17172 case GT:
17173 case LT:
17174 case UNORDERED:
17175 if (outer_code == SET && (XEXP (x, 1) == const0_rtx))
17176 {
17177 *total = COSTS_N_INSNS (2);
17178 return true;
c0600ecd 17179 }
22e54023
DE		 17180 /* CC COMPARE. */
17181 if (outer_code == COMPARE)
17182 {
17183 *total = 0;
17184 return true;
17185 }
17186 break;
c0600ecd 17187
3c50106f 17188 default:
06a67bdd 17189 break;
3c50106f 17190 }
06a67bdd
RS		 17191
17192 return false;
3c50106f
RH		 17193}
17194
34bb030a
DE		 17195/* A C expression returning the cost of moving data from a register of class
17196 CLASS1 to one of CLASS2. */
17197
17198int
f676971a 17199rs6000_register_move_cost (enum machine_mode mode,
a2369ed3 17200 enum reg_class from, enum reg_class to)
34bb030a
DE		 17201{
17202 /* Moves from/to GENERAL_REGS. */
17203 if (reg_classes_intersect_p (to, GENERAL_REGS)
17204 || reg_classes_intersect_p (from, GENERAL_REGS))
17205 {
17206 if (! reg_classes_intersect_p (to, GENERAL_REGS))
17207 from = to;
17208
17209 if (from == FLOAT_REGS || from == ALTIVEC_REGS)
17210 return (rs6000_memory_move_cost (mode, from, 0)
17211 + rs6000_memory_move_cost (mode, GENERAL_REGS, 0));
17212
c4ad648e
AM		 17213 /* It's more expensive to move CR_REGS than CR0_REGS because of the
17214 shift. */
34bb030a
DE		 17215 else if (from == CR_REGS)
17216 return 4;
17217
17218 else
c4ad648e 17219 /* A move will cost one instruction per GPR moved. */
34bb030a
DE		 17220 return 2 * HARD_REGNO_NREGS (0, mode);
17221 }
17222
c4ad648e 17223 /* Moving between two similar registers is just one instruction. */
34bb030a
DE		 17224 else if (reg_classes_intersect_p (to, from))
17225 return mode == TFmode ? 4 : 2;
17226
c4ad648e 17227 /* Everything else has to go through GENERAL_REGS. */
34bb030a 17228 else
f676971a 17229 return (rs6000_register_move_cost (mode, GENERAL_REGS, to)
34bb030a
DE		 17230 + rs6000_register_move_cost (mode, from, GENERAL_REGS));
17231}
17232
17233/* A C expressions returning the cost of moving data of MODE from a register to
17234 or from memory. */
17235
17236int
f676971a 17237rs6000_memory_move_cost (enum machine_mode mode, enum reg_class class,
a2369ed3 17238 int in ATTRIBUTE_UNUSED)
34bb030a
DE		 17239{
17240 if (reg_classes_intersect_p (class, GENERAL_REGS))
17241 return 4 * HARD_REGNO_NREGS (0, mode);
17242 else if (reg_classes_intersect_p (class, FLOAT_REGS))
17243 return 4 * HARD_REGNO_NREGS (32, mode);
17244 else if (reg_classes_intersect_p (class, ALTIVEC_REGS))
17245 return 4 * HARD_REGNO_NREGS (FIRST_ALTIVEC_REGNO, mode);
17246 else
17247 return 4 + rs6000_register_move_cost (mode, class, GENERAL_REGS);
17248}
17249
ded9bf77
AH		 17250/* Return an RTX representing where to find the function value of a
17251 function returning MODE. */
17252static rtx
17253rs6000_complex_function_value (enum machine_mode mode)
17254{
17255 unsigned int regno;
17256 rtx r1, r2;
17257 enum machine_mode inner = GET_MODE_INNER (mode);
fb7e4164 17258 unsigned int inner_bytes = GET_MODE_SIZE (inner);
ded9bf77 17259
18f63bfa
AH		 17260 if (FLOAT_MODE_P (mode) && TARGET_HARD_FLOAT && TARGET_FPRS)
17261 regno = FP_ARG_RETURN;
354ed18f
AH		 17262 else
17263 {
18f63bfa 17264 regno = GP_ARG_RETURN;
ded9bf77 17265
18f63bfa
AH		 17266 /* 32-bit is OK since it'll go in r3/r4. */
17267 if (TARGET_32BIT && inner_bytes >= 4)
ded9bf77
AH		 17268 return gen_rtx_REG (mode, regno);
17269 }
17270
18f63bfa
AH		 17271 if (inner_bytes >= 8)
17272 return gen_rtx_REG (mode, regno);
17273
ded9bf77
AH		 17274 r1 = gen_rtx_EXPR_LIST (inner, gen_rtx_REG (inner, regno),
17275 const0_rtx);
17276 r2 = gen_rtx_EXPR_LIST (inner, gen_rtx_REG (inner, regno + 1),
fb7e4164 17277 GEN_INT (inner_bytes));
ded9bf77
AH		 17278 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r2));
17279}
17280
a6ebc39a
AH		 17281/* Define how to find the value returned by a function.
17282 VALTYPE is the data type of the value (as a tree).
17283 If the precise function being called is known, FUNC is its FUNCTION_DECL;
17284 otherwise, FUNC is 0.
17285
17286 On the SPE, both FPs and vectors are returned in r3.
17287
17288 On RS/6000 an integer value is in r3 and a floating-point value is in
17289 fp1, unless -msoft-float. */
17290
17291rtx
17292rs6000_function_value (tree valtype, tree func ATTRIBUTE_UNUSED)
17293{
17294 enum machine_mode mode;
2a8fa26c 17295 unsigned int regno;
a6ebc39a 17296
594a51fe
SS		 17297 /* Special handling for structs in darwin64. */
17298 if (rs6000_darwin64_abi
17299 && TYPE_MODE (valtype) == BLKmode
0b5383eb
DJ		 17300 && TREE_CODE (valtype) == RECORD_TYPE
17301 && int_size_in_bytes (valtype) > 0)
594a51fe
SS		 17302 {
17303 CUMULATIVE_ARGS valcum;
17304 rtx valret;
17305
0b5383eb 17306 valcum.words = 0;
594a51fe
SS		 17307 valcum.fregno = FP_ARG_MIN_REG;
17308 valcum.vregno = ALTIVEC_ARG_MIN_REG;
0b5383eb
DJ		 17309 /* Do a trial code generation as if this were going to be passed as
17310 an argument; if any part goes in memory, we return NULL. */
17311 valret = rs6000_darwin64_record_arg (&valcum, valtype, 1, true);
594a51fe
SS		 17312 if (valret)
17313 return valret;
17314 /* Otherwise fall through to standard ABI rules. */
17315 }
17316
0e67400a
FJ		 17317 if (TARGET_32BIT && TARGET_POWERPC64 && TYPE_MODE (valtype) == DImode)
17318 {
17319 /* Long long return value need be split in -mpowerpc64, 32bit ABI. */
17320 return gen_rtx_PARALLEL (DImode,
17321 gen_rtvec (2,
17322 gen_rtx_EXPR_LIST (VOIDmode,
17323 gen_rtx_REG (SImode, GP_ARG_RETURN),
17324 const0_rtx),
17325 gen_rtx_EXPR_LIST (VOIDmode,
17326 gen_rtx_REG (SImode,
17327 GP_ARG_RETURN + 1),
17328 GEN_INT (4))));
17329 }
17330
a6ebc39a
AH		 17331 if ((INTEGRAL_TYPE_P (valtype)
17332 && TYPE_PRECISION (valtype) < BITS_PER_WORD)
17333 || POINTER_TYPE_P (valtype))
b78d48dd 17334 mode = TARGET_32BIT ? SImode : DImode;
a6ebc39a
AH		 17335 else
17336 mode = TYPE_MODE (valtype);
17337
4ed78545 17338 if (SCALAR_FLOAT_TYPE_P (valtype) && TARGET_HARD_FLOAT && TARGET_FPRS)
2a8fa26c 17339 regno = FP_ARG_RETURN;
ded9bf77 17340 else if (TREE_CODE (valtype) == COMPLEX_TYPE
42ba5130 17341 && targetm.calls.split_complex_arg)
ded9bf77 17342 return rs6000_complex_function_value (mode);
44688022 17343 else if (TREE_CODE (valtype) == VECTOR_TYPE
d0b2079e 17344 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI
23ba09f0 17345 && ALTIVEC_VECTOR_MODE (mode))
a6ebc39a 17346 regno = ALTIVEC_ARG_RETURN;
18f63bfa
AH		 17347 else if (TARGET_E500_DOUBLE && TARGET_HARD_FLOAT
17348 && (mode == DFmode || mode == DCmode))
17349 return spe_build_register_parallel (mode, GP_ARG_RETURN);
a6ebc39a
AH		 17350 else
17351 regno = GP_ARG_RETURN;
17352
17353 return gen_rtx_REG (mode, regno);
17354}
17355
ded9bf77
AH		 17356/* Define how to find the value returned by a library function
17357 assuming the value has mode MODE. */
17358rtx
17359rs6000_libcall_value (enum machine_mode mode)
17360{
17361 unsigned int regno;
17362
2e6c9641
FJ		 17363 if (TARGET_32BIT && TARGET_POWERPC64 && mode == DImode)
17364 {
17365 /* Long long return value need be split in -mpowerpc64, 32bit ABI. */
17366 return gen_rtx_PARALLEL (DImode,
17367 gen_rtvec (2,
17368 gen_rtx_EXPR_LIST (VOIDmode,
17369 gen_rtx_REG (SImode, GP_ARG_RETURN),
17370 const0_rtx),
17371 gen_rtx_EXPR_LIST (VOIDmode,
17372 gen_rtx_REG (SImode,
17373 GP_ARG_RETURN + 1),
17374 GEN_INT (4))));
17375 }
17376
ded9bf77
AH		 17377 if (GET_MODE_CLASS (mode) == MODE_FLOAT
17378 && TARGET_HARD_FLOAT && TARGET_FPRS)
17379 regno = FP_ARG_RETURN;
44688022
AM		 17380 else if (ALTIVEC_VECTOR_MODE (mode)
17381 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI)
ded9bf77 17382 regno = ALTIVEC_ARG_RETURN;
42ba5130 17383 else if (COMPLEX_MODE_P (mode) && targetm.calls.split_complex_arg)
ded9bf77 17384 return rs6000_complex_function_value (mode);
18f63bfa
AH		 17385 else if (TARGET_E500_DOUBLE && TARGET_HARD_FLOAT
17386 && (mode == DFmode || mode == DCmode))
17387 return spe_build_register_parallel (mode, GP_ARG_RETURN);
ded9bf77
AH		 17388 else
17389 regno = GP_ARG_RETURN;
17390
17391 return gen_rtx_REG (mode, regno);
17392}
17393
d1d0c603
JJ		 17394/* Define the offset between two registers, FROM to be eliminated and its
17395 replacement TO, at the start of a routine. */
17396HOST_WIDE_INT
17397rs6000_initial_elimination_offset (int from, int to)
17398{
17399 rs6000_stack_t *info = rs6000_stack_info ();
17400 HOST_WIDE_INT offset;
17401
17402 if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
17403 offset = info->push_p ? 0 : -info->total_size;
17404 else if (from == ARG_POINTER_REGNUM && to == FRAME_POINTER_REGNUM)
17405 offset = info->total_size;
17406 else if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
17407 offset = info->push_p ? info->total_size : 0;
17408 else if (from == RS6000_PIC_OFFSET_TABLE_REGNUM)
17409 offset = 0;
17410 else
17411 abort ();
17412
17413 return offset;
17414}
17415
62e1dfcf
NC		 17416/* Return true if TYPE is of type __ev64_opaque__. */
17417
c8e4f0e9 17418static bool
a2369ed3 17419is_ev64_opaque_type (tree type)
62e1dfcf 17420{
c8e4f0e9 17421 return (TARGET_SPE
2abe3e28
AH		 17422 && (type == opaque_V2SI_type_node
17423 || type == opaque_V2SF_type_node
36252949 17424 || type == opaque_p_V2SI_type_node));
62e1dfcf
NC		 17425}
17426
96714395 17427static rtx
a2369ed3 17428rs6000_dwarf_register_span (rtx reg)
96714395
AH		 17429{
17430 unsigned regno;
17431
4d4cbc0e
AH		 17432 if (TARGET_SPE
17433 && (SPE_VECTOR_MODE (GET_MODE (reg))
17434 || (TARGET_E500_DOUBLE && GET_MODE (reg) == DFmode)))
17435 ;
17436 else
96714395
AH		 17437 return NULL_RTX;
17438
17439 regno = REGNO (reg);
17440
17441 /* The duality of the SPE register size wreaks all kinds of havoc.
17442 This is a way of distinguishing r0 in 32-bits from r0 in
17443 64-bits. */
17444 return
17445 gen_rtx_PARALLEL (VOIDmode,
3bd104d1
AH		 17446 BYTES_BIG_ENDIAN
17447 ? gen_rtvec (2,
17448 gen_rtx_REG (SImode, regno + 1200),
17449 gen_rtx_REG (SImode, regno))
17450 : gen_rtvec (2,
17451 gen_rtx_REG (SImode, regno),
17452 gen_rtx_REG (SImode, regno + 1200)));
96714395
AH		 17453}
17454
93c9d1ba
AM		 17455/* Map internal gcc register numbers to DWARF2 register numbers. */
17456
17457unsigned int
17458rs6000_dbx_register_number (unsigned int regno)
17459{
17460 if (regno <= 63 || write_symbols != DWARF2_DEBUG)
17461 return regno;
17462 if (regno == MQ_REGNO)
17463 return 100;
17464 if (regno == LINK_REGISTER_REGNUM)
17465 return 108;
17466 if (regno == COUNT_REGISTER_REGNUM)
17467 return 109;
17468 if (CR_REGNO_P (regno))
17469 return regno - CR0_REGNO + 86;
17470 if (regno == XER_REGNO)
17471 return 101;
17472 if (ALTIVEC_REGNO_P (regno))
17473 return regno - FIRST_ALTIVEC_REGNO + 1124;
17474 if (regno == VRSAVE_REGNO)
17475 return 356;
17476 if (regno == VSCR_REGNO)
17477 return 67;
17478 if (regno == SPE_ACC_REGNO)
17479 return 99;
17480 if (regno == SPEFSCR_REGNO)
17481 return 612;
17482 /* SPE high reg number. We get these values of regno from
17483 rs6000_dwarf_register_span. */
17484 if (regno >= 1200 && regno < 1232)
17485 return regno;
17486
17487 abort ();
17488}
17489
93f90be6 17490/* target hook eh_return_filter_mode */
f676971a 17491static enum machine_mode
93f90be6
FJ		 17492rs6000_eh_return_filter_mode (void)
17493{
17494 return TARGET_32BIT ? SImode : word_mode;
17495}
17496
f676971a
EC		 17497/* Target hook for vector_mode_supported_p. */
17498static bool
17499rs6000_vector_mode_supported_p (enum machine_mode mode)
17500{
17501
17502 if (TARGET_SPE && SPE_VECTOR_MODE (mode))
17503 return true;
17504
17505 else if (TARGET_ALTIVEC && ALTIVEC_VECTOR_MODE (mode))
17506 return true;
17507
17508 else
17509 return false;
17510}
17511
4d3e6fae
FJ		 17512/* Target hook for invalid_arg_for_unprototyped_fn. */
17513static const char *
17514invalid_arg_for_unprototyped_fn (tree typelist, tree funcdecl, tree val)
17515{
17516 return (!rs6000_darwin64_abi
17517 && typelist == 0
17518 && TREE_CODE (TREE_TYPE (val)) == VECTOR_TYPE
17519 && (funcdecl == NULL_TREE
17520 || (TREE_CODE (funcdecl) == FUNCTION_DECL
17521 && DECL_BUILT_IN_CLASS (funcdecl) != BUILT_IN_MD)))
17522 ? N_("AltiVec argument passed to unprototyped function")
17523 : NULL;
17524}
17525
17211ab5 17526#include "gt-rs6000.h"
Mirror of https://gcc.gnu.org/git/gcc.git