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Commit | Line | Data |
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9878760c | 1 | /* Subroutines used for code generation on IBM RS/6000. |
f676971a | 2 | Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, |
66647d44 | 3 | 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009 |
337bde91 | 4 | Free Software Foundation, Inc. |
fab3bcc3 | 5 | Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu) |
9878760c | 6 | |
5de601cf | 7 | This file is part of GCC. |
9878760c | 8 | |
5de601cf NC |
9 | GCC is free software; you can redistribute it and/or modify it |
10 | under the terms of the GNU General Public License as published | |
2f83c7d6 | 11 | by the Free Software Foundation; either version 3, or (at your |
5de601cf | 12 | option) any later version. |
9878760c | 13 | |
5de601cf NC |
14 | GCC is distributed in the hope that it will be useful, but WITHOUT |
15 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
16 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
17 | License for more details. | |
9878760c | 18 | |
5de601cf | 19 | You should have received a copy of the GNU General Public License |
2f83c7d6 NC |
20 | along with GCC; see the file COPYING3. If not see |
21 | <http://www.gnu.org/licenses/>. */ | |
9878760c | 22 | |
956d6950 | 23 | #include "config.h" |
c4d38ccb | 24 | #include "system.h" |
4977bab6 ZW |
25 | #include "coretypes.h" |
26 | #include "tm.h" | |
9878760c RK |
27 | #include "rtl.h" |
28 | #include "regs.h" | |
29 | #include "hard-reg-set.h" | |
30 | #include "real.h" | |
31 | #include "insn-config.h" | |
32 | #include "conditions.h" | |
9878760c RK |
33 | #include "insn-attr.h" |
34 | #include "flags.h" | |
35 | #include "recog.h" | |
9878760c | 36 | #include "obstack.h" |
9b30bae2 | 37 | #include "tree.h" |
dfafc897 | 38 | #include "expr.h" |
2fc1c679 | 39 | #include "optabs.h" |
2a430ec1 | 40 | #include "except.h" |
a7df97e6 | 41 | #include "function.h" |
296b8152 | 42 | #include "output.h" |
d5fa86ba | 43 | #include "basic-block.h" |
d0101753 | 44 | #include "integrate.h" |
296b8152 | 45 | #include "toplev.h" |
c8023011 | 46 | #include "ggc.h" |
9ebbca7d GK |
47 | #include "hashtab.h" |
48 | #include "tm_p.h" | |
672a6f42 NB |
49 | #include "target.h" |
50 | #include "target-def.h" | |
3ac88239 | 51 | #include "langhooks.h" |
24ea750e | 52 | #include "reload.h" |
117dca74 | 53 | #include "cfglayout.h" |
79ae11c4 | 54 | #include "sched-int.h" |
726a989a | 55 | #include "gimple.h" |
e41b2a33 | 56 | #include "tree-flow.h" |
4d3e6fae | 57 | #include "intl.h" |
59d6560b | 58 | #include "params.h" |
279bb624 | 59 | #include "tm-constrs.h" |
1bc7c5b6 ZW |
60 | #if TARGET_XCOFF |
61 | #include "xcoffout.h" /* get declarations of xcoff_*_section_name */ | |
62 | #endif | |
93a27b7b ZW |
63 | #if TARGET_MACHO |
64 | #include "gstab.h" /* for N_SLINE */ | |
65 | #endif | |
9b30bae2 | 66 | |
7509c759 MM |
67 | #ifndef TARGET_NO_PROTOTYPE |
68 | #define TARGET_NO_PROTOTYPE 0 | |
69 | #endif | |
70 | ||
9878760c RK |
71 | #define min(A,B) ((A) < (B) ? (A) : (B)) |
72 | #define max(A,B) ((A) > (B) ? (A) : (B)) | |
73 | ||
d1d0c603 JJ |
74 | /* Structure used to define the rs6000 stack */ |
75 | typedef struct rs6000_stack { | |
76 | int first_gp_reg_save; /* first callee saved GP register used */ | |
77 | int first_fp_reg_save; /* first callee saved FP register used */ | |
78 | int first_altivec_reg_save; /* first callee saved AltiVec register used */ | |
79 | int lr_save_p; /* true if the link reg needs to be saved */ | |
80 | int cr_save_p; /* true if the CR reg needs to be saved */ | |
81 | unsigned int vrsave_mask; /* mask of vec registers to save */ | |
d1d0c603 JJ |
82 | int push_p; /* true if we need to allocate stack space */ |
83 | int calls_p; /* true if the function makes any calls */ | |
c4ad648e | 84 | int world_save_p; /* true if we're saving *everything*: |
d62294f5 | 85 | r13-r31, cr, f14-f31, vrsave, v20-v31 */ |
d1d0c603 JJ |
86 | enum rs6000_abi abi; /* which ABI to use */ |
87 | int gp_save_offset; /* offset to save GP regs from initial SP */ | |
88 | int fp_save_offset; /* offset to save FP regs from initial SP */ | |
89 | int altivec_save_offset; /* offset to save AltiVec regs from initial SP */ | |
90 | int lr_save_offset; /* offset to save LR from initial SP */ | |
91 | int cr_save_offset; /* offset to save CR from initial SP */ | |
92 | int vrsave_save_offset; /* offset to save VRSAVE from initial SP */ | |
93 | int spe_gp_save_offset; /* offset to save spe 64-bit gprs */ | |
d1d0c603 JJ |
94 | int varargs_save_offset; /* offset to save the varargs registers */ |
95 | int ehrd_offset; /* offset to EH return data */ | |
96 | int reg_size; /* register size (4 or 8) */ | |
d1d0c603 JJ |
97 | HOST_WIDE_INT vars_size; /* variable save area size */ |
98 | int parm_size; /* outgoing parameter size */ | |
99 | int save_size; /* save area size */ | |
100 | int fixed_size; /* fixed size of stack frame */ | |
101 | int gp_size; /* size of saved GP registers */ | |
102 | int fp_size; /* size of saved FP registers */ | |
103 | int altivec_size; /* size of saved AltiVec registers */ | |
104 | int cr_size; /* size to hold CR if not in save_size */ | |
d1d0c603 JJ |
105 | int vrsave_size; /* size to hold VRSAVE if not in save_size */ |
106 | int altivec_padding_size; /* size of altivec alignment padding if | |
107 | not in save_size */ | |
108 | int spe_gp_size; /* size of 64-bit GPR save size for SPE */ | |
109 | int spe_padding_size; | |
d1d0c603 JJ |
110 | HOST_WIDE_INT total_size; /* total bytes allocated for stack */ |
111 | int spe_64bit_regs_used; | |
112 | } rs6000_stack_t; | |
113 | ||
5b667039 JJ |
114 | /* A C structure for machine-specific, per-function data. |
115 | This is added to the cfun structure. */ | |
116 | typedef struct machine_function GTY(()) | |
117 | { | |
118 | /* Flags if __builtin_return_address (n) with n >= 1 was used. */ | |
119 | int ra_needs_full_frame; | |
120 | /* Some local-dynamic symbol. */ | |
121 | const char *some_ld_name; | |
122 | /* Whether the instruction chain has been scanned already. */ | |
123 | int insn_chain_scanned_p; | |
124 | /* Flags if __builtin_return_address (0) was used. */ | |
125 | int ra_need_lr; | |
126 | /* Offset from virtual_stack_vars_rtx to the start of the ABI_V4 | |
127 | varargs save area. */ | |
128 | HOST_WIDE_INT varargs_save_offset; | |
e41b2a33 PB |
129 | /* Temporary stack slot to use for SDmode copies. This slot is |
130 | 64-bits wide and is allocated early enough so that the offset | |
131 | does not overflow the 16-bit load/store offset field. */ | |
132 | rtx sdmode_stack_slot; | |
5b667039 JJ |
133 | } machine_function; |
134 | ||
5248c961 RK |
135 | /* Target cpu type */ |
136 | ||
137 | enum processor_type rs6000_cpu; | |
8e3f41e7 MM |
138 | struct rs6000_cpu_select rs6000_select[3] = |
139 | { | |
815cdc52 MM |
140 | /* switch name, tune arch */ |
141 | { (const char *)0, "--with-cpu=", 1, 1 }, | |
142 | { (const char *)0, "-mcpu=", 1, 1 }, | |
143 | { (const char *)0, "-mtune=", 1, 0 }, | |
8e3f41e7 | 144 | }; |
5248c961 | 145 | |
ec507f2d DE |
146 | /* Always emit branch hint bits. */ |
147 | static GTY(()) bool rs6000_always_hint; | |
148 | ||
149 | /* Schedule instructions for group formation. */ | |
150 | static GTY(()) bool rs6000_sched_groups; | |
151 | ||
44cd321e PS |
152 | /* Align branch targets. */ |
153 | static GTY(()) bool rs6000_align_branch_targets; | |
154 | ||
569fa502 DN |
155 | /* Support for -msched-costly-dep option. */ |
156 | const char *rs6000_sched_costly_dep_str; | |
157 | enum rs6000_dependence_cost rs6000_sched_costly_dep; | |
158 | ||
cbe26ab8 DN |
159 | /* Support for -minsert-sched-nops option. */ |
160 | const char *rs6000_sched_insert_nops_str; | |
161 | enum rs6000_nop_insertion rs6000_sched_insert_nops; | |
162 | ||
7ccf35ed | 163 | /* Support targetm.vectorize.builtin_mask_for_load. */ |
13c62176 | 164 | static GTY(()) tree altivec_builtin_mask_for_load; |
7ccf35ed | 165 | |
602ea4d3 | 166 | /* Size of long double. */ |
6fa3f289 ZW |
167 | int rs6000_long_double_type_size; |
168 | ||
602ea4d3 JJ |
169 | /* IEEE quad extended precision long double. */ |
170 | int rs6000_ieeequad; | |
171 | ||
a2db2771 | 172 | /* Nonzero to use AltiVec ABI. */ |
6fa3f289 ZW |
173 | int rs6000_altivec_abi; |
174 | ||
94f4765c NF |
175 | /* Nonzero if we want SPE SIMD instructions. */ |
176 | int rs6000_spe; | |
177 | ||
a3170dc6 AH |
178 | /* Nonzero if we want SPE ABI extensions. */ |
179 | int rs6000_spe_abi; | |
180 | ||
94f4765c NF |
181 | /* Nonzero to use isel instructions. */ |
182 | int rs6000_isel; | |
183 | ||
5da702b1 AH |
184 | /* Nonzero if floating point operations are done in the GPRs. */ |
185 | int rs6000_float_gprs = 0; | |
186 | ||
594a51fe SS |
187 | /* Nonzero if we want Darwin's struct-by-value-in-regs ABI. */ |
188 | int rs6000_darwin64_abi; | |
189 | ||
a0ab749a | 190 | /* Set to nonzero once AIX common-mode calls have been defined. */ |
bbfb86aa | 191 | static GTY(()) int common_mode_defined; |
c81bebd7 | 192 | |
9878760c RK |
193 | /* Save information from a "cmpxx" operation until the branch or scc is |
194 | emitted. */ | |
9878760c RK |
195 | rtx rs6000_compare_op0, rs6000_compare_op1; |
196 | int rs6000_compare_fp_p; | |
874a0744 | 197 | |
874a0744 MM |
198 | /* Label number of label created for -mrelocatable, to call to so we can |
199 | get the address of the GOT section */ | |
200 | int rs6000_pic_labelno; | |
c81bebd7 | 201 | |
b91da81f | 202 | #ifdef USING_ELFOS_H |
c81bebd7 | 203 | /* Which abi to adhere to */ |
9739c90c | 204 | const char *rs6000_abi_name; |
d9407988 MM |
205 | |
206 | /* Semantics of the small data area */ | |
207 | enum rs6000_sdata_type rs6000_sdata = SDATA_DATA; | |
208 | ||
209 | /* Which small data model to use */ | |
815cdc52 | 210 | const char *rs6000_sdata_name = (char *)0; |
9ebbca7d GK |
211 | |
212 | /* Counter for labels which are to be placed in .fixup. */ | |
213 | int fixuplabelno = 0; | |
874a0744 | 214 | #endif |
4697a36c | 215 | |
c4501e62 JJ |
216 | /* Bit size of immediate TLS offsets and string from which it is decoded. */ |
217 | int rs6000_tls_size = 32; | |
218 | const char *rs6000_tls_size_string; | |
219 | ||
b6c9286a MM |
220 | /* ABI enumeration available for subtarget to use. */ |
221 | enum rs6000_abi rs6000_current_abi; | |
222 | ||
85b776df AM |
223 | /* Whether to use variant of AIX ABI for PowerPC64 Linux. */ |
224 | int dot_symbols; | |
225 | ||
38c1f2d7 | 226 | /* Debug flags */ |
815cdc52 | 227 | const char *rs6000_debug_name; |
38c1f2d7 MM |
228 | int rs6000_debug_stack; /* debug stack applications */ |
229 | int rs6000_debug_arg; /* debug argument handling */ | |
230 | ||
aabcd309 | 231 | /* Value is TRUE if register/mode pair is acceptable. */ |
0d1fbc8c AH |
232 | bool rs6000_hard_regno_mode_ok_p[NUM_MACHINE_MODES][FIRST_PSEUDO_REGISTER]; |
233 | ||
58646b77 PB |
234 | /* Built in types. */ |
235 | ||
236 | tree rs6000_builtin_types[RS6000_BTI_MAX]; | |
237 | tree rs6000_builtin_decls[RS6000_BUILTIN_COUNT]; | |
8bb418a3 | 238 | |
57ac7be9 AM |
239 | const char *rs6000_traceback_name; |
240 | static enum { | |
241 | traceback_default = 0, | |
242 | traceback_none, | |
243 | traceback_part, | |
244 | traceback_full | |
245 | } rs6000_traceback; | |
246 | ||
38c1f2d7 MM |
247 | /* Flag to say the TOC is initialized */ |
248 | int toc_initialized; | |
9ebbca7d | 249 | char toc_label_name[10]; |
38c1f2d7 | 250 | |
44cd321e PS |
251 | /* Cached value of rs6000_variable_issue. This is cached in |
252 | rs6000_variable_issue hook and returned from rs6000_sched_reorder2. */ | |
253 | static short cached_can_issue_more; | |
254 | ||
d6b5193b RS |
255 | static GTY(()) section *read_only_data_section; |
256 | static GTY(()) section *private_data_section; | |
257 | static GTY(()) section *read_only_private_data_section; | |
258 | static GTY(()) section *sdata2_section; | |
259 | static GTY(()) section *toc_section; | |
260 | ||
a3c9585f KH |
261 | /* Control alignment for fields within structures. */ |
262 | /* String from -malign-XXXXX. */ | |
025d9908 KH |
263 | int rs6000_alignment_flags; |
264 | ||
78f5898b AH |
265 | /* True for any options that were explicitly set. */ |
266 | struct { | |
df01da37 | 267 | bool aix_struct_ret; /* True if -maix-struct-ret was used. */ |
78f5898b | 268 | bool alignment; /* True if -malign- was used. */ |
a2db2771 JJ |
269 | bool spe_abi; /* True if -mabi=spe/no-spe was used. */ |
270 | bool altivec_abi; /* True if -mabi=altivec/no-altivec used. */ | |
78f5898b AH |
271 | bool spe; /* True if -mspe= was used. */ |
272 | bool float_gprs; /* True if -mfloat-gprs= was used. */ | |
273 | bool isel; /* True if -misel was used. */ | |
274 | bool long_double; /* True if -mlong-double- was used. */ | |
d3603e8c | 275 | bool ieee; /* True if -mabi=ieee/ibmlongdouble used. */ |
a2db2771 | 276 | bool vrsave; /* True if -mvrsave was used. */ |
78f5898b AH |
277 | } rs6000_explicit_options; |
278 | ||
a3170dc6 AH |
279 | struct builtin_description |
280 | { | |
281 | /* mask is not const because we're going to alter it below. This | |
282 | nonsense will go away when we rewrite the -march infrastructure | |
283 | to give us more target flag bits. */ | |
284 | unsigned int mask; | |
285 | const enum insn_code icode; | |
286 | const char *const name; | |
287 | const enum rs6000_builtins code; | |
288 | }; | |
8b897cfa RS |
289 | \f |
290 | /* Target cpu costs. */ | |
291 | ||
292 | struct processor_costs { | |
c4ad648e | 293 | const int mulsi; /* cost of SImode multiplication. */ |
8b897cfa RS |
294 | const int mulsi_const; /* cost of SImode multiplication by constant. */ |
295 | const int mulsi_const9; /* cost of SImode mult by short constant. */ | |
c4ad648e AM |
296 | const int muldi; /* cost of DImode multiplication. */ |
297 | const int divsi; /* cost of SImode division. */ | |
298 | const int divdi; /* cost of DImode division. */ | |
299 | const int fp; /* cost of simple SFmode and DFmode insns. */ | |
300 | const int dmul; /* cost of DFmode multiplication (and fmadd). */ | |
301 | const int sdiv; /* cost of SFmode division (fdivs). */ | |
302 | const int ddiv; /* cost of DFmode division (fdiv). */ | |
5f732aba DE |
303 | const int cache_line_size; /* cache line size in bytes. */ |
304 | const int l1_cache_size; /* size of l1 cache, in kilobytes. */ | |
305 | const int l2_cache_size; /* size of l2 cache, in kilobytes. */ | |
0b11da67 DE |
306 | const int simultaneous_prefetches; /* number of parallel prefetch |
307 | operations. */ | |
8b897cfa RS |
308 | }; |
309 | ||
310 | const struct processor_costs *rs6000_cost; | |
311 | ||
312 | /* Processor costs (relative to an add) */ | |
313 | ||
314 | /* Instruction size costs on 32bit processors. */ | |
315 | static const | |
316 | struct processor_costs size32_cost = { | |
06a67bdd RS |
317 | COSTS_N_INSNS (1), /* mulsi */ |
318 | COSTS_N_INSNS (1), /* mulsi_const */ | |
319 | COSTS_N_INSNS (1), /* mulsi_const9 */ | |
320 | COSTS_N_INSNS (1), /* muldi */ | |
321 | COSTS_N_INSNS (1), /* divsi */ | |
322 | COSTS_N_INSNS (1), /* divdi */ | |
323 | COSTS_N_INSNS (1), /* fp */ | |
324 | COSTS_N_INSNS (1), /* dmul */ | |
325 | COSTS_N_INSNS (1), /* sdiv */ | |
326 | COSTS_N_INSNS (1), /* ddiv */ | |
0b11da67 DE |
327 | 32, |
328 | 0, | |
329 | 0, | |
5f732aba | 330 | 0, |
8b897cfa RS |
331 | }; |
332 | ||
333 | /* Instruction size costs on 64bit processors. */ | |
334 | static const | |
335 | struct processor_costs size64_cost = { | |
06a67bdd RS |
336 | COSTS_N_INSNS (1), /* mulsi */ |
337 | COSTS_N_INSNS (1), /* mulsi_const */ | |
338 | COSTS_N_INSNS (1), /* mulsi_const9 */ | |
339 | COSTS_N_INSNS (1), /* muldi */ | |
340 | COSTS_N_INSNS (1), /* divsi */ | |
341 | COSTS_N_INSNS (1), /* divdi */ | |
342 | COSTS_N_INSNS (1), /* fp */ | |
343 | COSTS_N_INSNS (1), /* dmul */ | |
344 | COSTS_N_INSNS (1), /* sdiv */ | |
345 | COSTS_N_INSNS (1), /* ddiv */ | |
0b11da67 DE |
346 | 128, |
347 | 0, | |
348 | 0, | |
5f732aba | 349 | 0, |
8b897cfa RS |
350 | }; |
351 | ||
352 | /* Instruction costs on RIOS1 processors. */ | |
353 | static const | |
354 | struct processor_costs rios1_cost = { | |
06a67bdd RS |
355 | COSTS_N_INSNS (5), /* mulsi */ |
356 | COSTS_N_INSNS (4), /* mulsi_const */ | |
357 | COSTS_N_INSNS (3), /* mulsi_const9 */ | |
358 | COSTS_N_INSNS (5), /* muldi */ | |
359 | COSTS_N_INSNS (19), /* divsi */ | |
360 | COSTS_N_INSNS (19), /* divdi */ | |
361 | COSTS_N_INSNS (2), /* fp */ | |
362 | COSTS_N_INSNS (2), /* dmul */ | |
363 | COSTS_N_INSNS (19), /* sdiv */ | |
364 | COSTS_N_INSNS (19), /* ddiv */ | |
0d158b6e | 365 | 128, /* cache line size */ |
5f732aba DE |
366 | 64, /* l1 cache */ |
367 | 512, /* l2 cache */ | |
0b11da67 | 368 | 0, /* streams */ |
8b897cfa RS |
369 | }; |
370 | ||
371 | /* Instruction costs on RIOS2 processors. */ | |
372 | static const | |
373 | struct processor_costs rios2_cost = { | |
06a67bdd RS |
374 | COSTS_N_INSNS (2), /* mulsi */ |
375 | COSTS_N_INSNS (2), /* mulsi_const */ | |
376 | COSTS_N_INSNS (2), /* mulsi_const9 */ | |
377 | COSTS_N_INSNS (2), /* muldi */ | |
378 | COSTS_N_INSNS (13), /* divsi */ | |
379 | COSTS_N_INSNS (13), /* divdi */ | |
380 | COSTS_N_INSNS (2), /* fp */ | |
381 | COSTS_N_INSNS (2), /* dmul */ | |
382 | COSTS_N_INSNS (17), /* sdiv */ | |
383 | COSTS_N_INSNS (17), /* ddiv */ | |
0d158b6e | 384 | 256, /* cache line size */ |
5f732aba DE |
385 | 256, /* l1 cache */ |
386 | 1024, /* l2 cache */ | |
0b11da67 | 387 | 0, /* streams */ |
8b897cfa RS |
388 | }; |
389 | ||
390 | /* Instruction costs on RS64A processors. */ | |
391 | static const | |
392 | struct processor_costs rs64a_cost = { | |
06a67bdd RS |
393 | COSTS_N_INSNS (20), /* mulsi */ |
394 | COSTS_N_INSNS (12), /* mulsi_const */ | |
395 | COSTS_N_INSNS (8), /* mulsi_const9 */ | |
396 | COSTS_N_INSNS (34), /* muldi */ | |
397 | COSTS_N_INSNS (65), /* divsi */ | |
398 | COSTS_N_INSNS (67), /* divdi */ | |
399 | COSTS_N_INSNS (4), /* fp */ | |
400 | COSTS_N_INSNS (4), /* dmul */ | |
401 | COSTS_N_INSNS (31), /* sdiv */ | |
402 | COSTS_N_INSNS (31), /* ddiv */ | |
0d158b6e | 403 | 128, /* cache line size */ |
5f732aba DE |
404 | 128, /* l1 cache */ |
405 | 2048, /* l2 cache */ | |
0b11da67 | 406 | 1, /* streams */ |
8b897cfa RS |
407 | }; |
408 | ||
409 | /* Instruction costs on MPCCORE processors. */ | |
410 | static const | |
411 | struct processor_costs mpccore_cost = { | |
06a67bdd RS |
412 | COSTS_N_INSNS (2), /* mulsi */ |
413 | COSTS_N_INSNS (2), /* mulsi_const */ | |
414 | COSTS_N_INSNS (2), /* mulsi_const9 */ | |
415 | COSTS_N_INSNS (2), /* muldi */ | |
416 | COSTS_N_INSNS (6), /* divsi */ | |
417 | COSTS_N_INSNS (6), /* divdi */ | |
418 | COSTS_N_INSNS (4), /* fp */ | |
419 | COSTS_N_INSNS (5), /* dmul */ | |
420 | COSTS_N_INSNS (10), /* sdiv */ | |
421 | COSTS_N_INSNS (17), /* ddiv */ | |
0d158b6e | 422 | 32, /* cache line size */ |
5f732aba DE |
423 | 4, /* l1 cache */ |
424 | 16, /* l2 cache */ | |
0b11da67 | 425 | 1, /* streams */ |
8b897cfa RS |
426 | }; |
427 | ||
428 | /* Instruction costs on PPC403 processors. */ | |
429 | static const | |
430 | struct processor_costs ppc403_cost = { | |
06a67bdd RS |
431 | COSTS_N_INSNS (4), /* mulsi */ |
432 | COSTS_N_INSNS (4), /* mulsi_const */ | |
433 | COSTS_N_INSNS (4), /* mulsi_const9 */ | |
434 | COSTS_N_INSNS (4), /* muldi */ | |
435 | COSTS_N_INSNS (33), /* divsi */ | |
436 | COSTS_N_INSNS (33), /* divdi */ | |
437 | COSTS_N_INSNS (11), /* fp */ | |
438 | COSTS_N_INSNS (11), /* dmul */ | |
439 | COSTS_N_INSNS (11), /* sdiv */ | |
440 | COSTS_N_INSNS (11), /* ddiv */ | |
0d158b6e | 441 | 32, /* cache line size */ |
5f732aba DE |
442 | 4, /* l1 cache */ |
443 | 16, /* l2 cache */ | |
0b11da67 | 444 | 1, /* streams */ |
8b897cfa RS |
445 | }; |
446 | ||
447 | /* Instruction costs on PPC405 processors. */ | |
448 | static const | |
449 | struct processor_costs ppc405_cost = { | |
06a67bdd RS |
450 | COSTS_N_INSNS (5), /* mulsi */ |
451 | COSTS_N_INSNS (4), /* mulsi_const */ | |
452 | COSTS_N_INSNS (3), /* mulsi_const9 */ | |
453 | COSTS_N_INSNS (5), /* muldi */ | |
454 | COSTS_N_INSNS (35), /* divsi */ | |
455 | COSTS_N_INSNS (35), /* divdi */ | |
456 | COSTS_N_INSNS (11), /* fp */ | |
457 | COSTS_N_INSNS (11), /* dmul */ | |
458 | COSTS_N_INSNS (11), /* sdiv */ | |
459 | COSTS_N_INSNS (11), /* ddiv */ | |
0d158b6e | 460 | 32, /* cache line size */ |
5f732aba DE |
461 | 16, /* l1 cache */ |
462 | 128, /* l2 cache */ | |
0b11da67 | 463 | 1, /* streams */ |
8b897cfa RS |
464 | }; |
465 | ||
466 | /* Instruction costs on PPC440 processors. */ | |
467 | static const | |
468 | struct processor_costs ppc440_cost = { | |
06a67bdd RS |
469 | COSTS_N_INSNS (3), /* mulsi */ |
470 | COSTS_N_INSNS (2), /* mulsi_const */ | |
471 | COSTS_N_INSNS (2), /* mulsi_const9 */ | |
472 | COSTS_N_INSNS (3), /* muldi */ | |
473 | COSTS_N_INSNS (34), /* divsi */ | |
474 | COSTS_N_INSNS (34), /* divdi */ | |
475 | COSTS_N_INSNS (5), /* fp */ | |
476 | COSTS_N_INSNS (5), /* dmul */ | |
477 | COSTS_N_INSNS (19), /* sdiv */ | |
478 | COSTS_N_INSNS (33), /* ddiv */ | |
0d158b6e | 479 | 32, /* cache line size */ |
5f732aba DE |
480 | 32, /* l1 cache */ |
481 | 256, /* l2 cache */ | |
0b11da67 | 482 | 1, /* streams */ |
8b897cfa RS |
483 | }; |
484 | ||
485 | /* Instruction costs on PPC601 processors. */ | |
486 | static const | |
487 | struct processor_costs ppc601_cost = { | |
06a67bdd RS |
488 | COSTS_N_INSNS (5), /* mulsi */ |
489 | COSTS_N_INSNS (5), /* mulsi_const */ | |
490 | COSTS_N_INSNS (5), /* mulsi_const9 */ | |
491 | COSTS_N_INSNS (5), /* muldi */ | |
492 | COSTS_N_INSNS (36), /* divsi */ | |
493 | COSTS_N_INSNS (36), /* divdi */ | |
494 | COSTS_N_INSNS (4), /* fp */ | |
495 | COSTS_N_INSNS (5), /* dmul */ | |
496 | COSTS_N_INSNS (17), /* sdiv */ | |
497 | COSTS_N_INSNS (31), /* ddiv */ | |
0d158b6e | 498 | 32, /* cache line size */ |
5f732aba DE |
499 | 32, /* l1 cache */ |
500 | 256, /* l2 cache */ | |
0b11da67 | 501 | 1, /* streams */ |
8b897cfa RS |
502 | }; |
503 | ||
504 | /* Instruction costs on PPC603 processors. */ | |
505 | static const | |
506 | struct processor_costs ppc603_cost = { | |
06a67bdd RS |
507 | COSTS_N_INSNS (5), /* mulsi */ |
508 | COSTS_N_INSNS (3), /* mulsi_const */ | |
509 | COSTS_N_INSNS (2), /* mulsi_const9 */ | |
510 | COSTS_N_INSNS (5), /* muldi */ | |
511 | COSTS_N_INSNS (37), /* divsi */ | |
512 | COSTS_N_INSNS (37), /* divdi */ | |
513 | COSTS_N_INSNS (3), /* fp */ | |
514 | COSTS_N_INSNS (4), /* dmul */ | |
515 | COSTS_N_INSNS (18), /* sdiv */ | |
516 | COSTS_N_INSNS (33), /* ddiv */ | |
0d158b6e | 517 | 32, /* cache line size */ |
5f732aba DE |
518 | 8, /* l1 cache */ |
519 | 64, /* l2 cache */ | |
0b11da67 | 520 | 1, /* streams */ |
8b897cfa RS |
521 | }; |
522 | ||
523 | /* Instruction costs on PPC604 processors. */ | |
524 | static const | |
525 | struct processor_costs ppc604_cost = { | |
06a67bdd RS |
526 | COSTS_N_INSNS (4), /* mulsi */ |
527 | COSTS_N_INSNS (4), /* mulsi_const */ | |
528 | COSTS_N_INSNS (4), /* mulsi_const9 */ | |
529 | COSTS_N_INSNS (4), /* muldi */ | |
530 | COSTS_N_INSNS (20), /* divsi */ | |
531 | COSTS_N_INSNS (20), /* divdi */ | |
532 | COSTS_N_INSNS (3), /* fp */ | |
533 | COSTS_N_INSNS (3), /* dmul */ | |
534 | COSTS_N_INSNS (18), /* sdiv */ | |
535 | COSTS_N_INSNS (32), /* ddiv */ | |
0d158b6e | 536 | 32, /* cache line size */ |
5f732aba DE |
537 | 16, /* l1 cache */ |
538 | 512, /* l2 cache */ | |
0b11da67 | 539 | 1, /* streams */ |
8b897cfa RS |
540 | }; |
541 | ||
542 | /* Instruction costs on PPC604e processors. */ | |
543 | static const | |
544 | struct processor_costs ppc604e_cost = { | |
06a67bdd RS |
545 | COSTS_N_INSNS (2), /* mulsi */ |
546 | COSTS_N_INSNS (2), /* mulsi_const */ | |
547 | COSTS_N_INSNS (2), /* mulsi_const9 */ | |
548 | COSTS_N_INSNS (2), /* muldi */ | |
549 | COSTS_N_INSNS (20), /* divsi */ | |
550 | COSTS_N_INSNS (20), /* divdi */ | |
551 | COSTS_N_INSNS (3), /* fp */ | |
552 | COSTS_N_INSNS (3), /* dmul */ | |
553 | COSTS_N_INSNS (18), /* sdiv */ | |
554 | COSTS_N_INSNS (32), /* ddiv */ | |
0d158b6e | 555 | 32, /* cache line size */ |
5f732aba DE |
556 | 32, /* l1 cache */ |
557 | 1024, /* l2 cache */ | |
0b11da67 | 558 | 1, /* streams */ |
8b897cfa RS |
559 | }; |
560 | ||
f0517163 | 561 | /* Instruction costs on PPC620 processors. */ |
8b897cfa RS |
562 | static const |
563 | struct processor_costs ppc620_cost = { | |
06a67bdd RS |
564 | COSTS_N_INSNS (5), /* mulsi */ |
565 | COSTS_N_INSNS (4), /* mulsi_const */ | |
566 | COSTS_N_INSNS (3), /* mulsi_const9 */ | |
567 | COSTS_N_INSNS (7), /* muldi */ | |
568 | COSTS_N_INSNS (21), /* divsi */ | |
569 | COSTS_N_INSNS (37), /* divdi */ | |
570 | COSTS_N_INSNS (3), /* fp */ | |
571 | COSTS_N_INSNS (3), /* dmul */ | |
572 | COSTS_N_INSNS (18), /* sdiv */ | |
573 | COSTS_N_INSNS (32), /* ddiv */ | |
0d158b6e | 574 | 128, /* cache line size */ |
5f732aba DE |
575 | 32, /* l1 cache */ |
576 | 1024, /* l2 cache */ | |
0b11da67 | 577 | 1, /* streams */ |
f0517163 RS |
578 | }; |
579 | ||
580 | /* Instruction costs on PPC630 processors. */ | |
581 | static const | |
582 | struct processor_costs ppc630_cost = { | |
06a67bdd RS |
583 | COSTS_N_INSNS (5), /* mulsi */ |
584 | COSTS_N_INSNS (4), /* mulsi_const */ | |
585 | COSTS_N_INSNS (3), /* mulsi_const9 */ | |
586 | COSTS_N_INSNS (7), /* muldi */ | |
587 | COSTS_N_INSNS (21), /* divsi */ | |
588 | COSTS_N_INSNS (37), /* divdi */ | |
589 | COSTS_N_INSNS (3), /* fp */ | |
590 | COSTS_N_INSNS (3), /* dmul */ | |
591 | COSTS_N_INSNS (17), /* sdiv */ | |
592 | COSTS_N_INSNS (21), /* ddiv */ | |
0d158b6e | 593 | 128, /* cache line size */ |
5f732aba DE |
594 | 64, /* l1 cache */ |
595 | 1024, /* l2 cache */ | |
0b11da67 | 596 | 1, /* streams */ |
8b897cfa RS |
597 | }; |
598 | ||
d296e02e AP |
599 | /* Instruction costs on Cell processor. */ |
600 | /* COSTS_N_INSNS (1) ~ one add. */ | |
601 | static const | |
602 | struct processor_costs ppccell_cost = { | |
603 | COSTS_N_INSNS (9/2)+2, /* mulsi */ | |
604 | COSTS_N_INSNS (6/2), /* mulsi_const */ | |
605 | COSTS_N_INSNS (6/2), /* mulsi_const9 */ | |
606 | COSTS_N_INSNS (15/2)+2, /* muldi */ | |
607 | COSTS_N_INSNS (38/2), /* divsi */ | |
608 | COSTS_N_INSNS (70/2), /* divdi */ | |
609 | COSTS_N_INSNS (10/2), /* fp */ | |
610 | COSTS_N_INSNS (10/2), /* dmul */ | |
611 | COSTS_N_INSNS (74/2), /* sdiv */ | |
612 | COSTS_N_INSNS (74/2), /* ddiv */ | |
0d158b6e | 613 | 128, /* cache line size */ |
5f732aba DE |
614 | 32, /* l1 cache */ |
615 | 512, /* l2 cache */ | |
616 | 6, /* streams */ | |
d296e02e AP |
617 | }; |
618 | ||
8b897cfa RS |
619 | /* Instruction costs on PPC750 and PPC7400 processors. */ |
620 | static const | |
621 | struct processor_costs ppc750_cost = { | |
06a67bdd RS |
622 | COSTS_N_INSNS (5), /* mulsi */ |
623 | COSTS_N_INSNS (3), /* mulsi_const */ | |
624 | COSTS_N_INSNS (2), /* mulsi_const9 */ | |
625 | COSTS_N_INSNS (5), /* muldi */ | |
626 | COSTS_N_INSNS (17), /* divsi */ | |
627 | COSTS_N_INSNS (17), /* divdi */ | |
628 | COSTS_N_INSNS (3), /* fp */ | |
629 | COSTS_N_INSNS (3), /* dmul */ | |
630 | COSTS_N_INSNS (17), /* sdiv */ | |
631 | COSTS_N_INSNS (31), /* ddiv */ | |
0d158b6e | 632 | 32, /* cache line size */ |
5f732aba DE |
633 | 32, /* l1 cache */ |
634 | 512, /* l2 cache */ | |
0b11da67 | 635 | 1, /* streams */ |
8b897cfa RS |
636 | }; |
637 | ||
638 | /* Instruction costs on PPC7450 processors. */ | |
639 | static const | |
640 | struct processor_costs ppc7450_cost = { | |
06a67bdd RS |
641 | COSTS_N_INSNS (4), /* mulsi */ |
642 | COSTS_N_INSNS (3), /* mulsi_const */ | |
643 | COSTS_N_INSNS (3), /* mulsi_const9 */ | |
644 | COSTS_N_INSNS (4), /* muldi */ | |
645 | COSTS_N_INSNS (23), /* divsi */ | |
646 | COSTS_N_INSNS (23), /* divdi */ | |
647 | COSTS_N_INSNS (5), /* fp */ | |
648 | COSTS_N_INSNS (5), /* dmul */ | |
649 | COSTS_N_INSNS (21), /* sdiv */ | |
650 | COSTS_N_INSNS (35), /* ddiv */ | |
0d158b6e | 651 | 32, /* cache line size */ |
5f732aba DE |
652 | 32, /* l1 cache */ |
653 | 1024, /* l2 cache */ | |
0b11da67 | 654 | 1, /* streams */ |
8b897cfa | 655 | }; |
a3170dc6 | 656 | |
8b897cfa RS |
657 | /* Instruction costs on PPC8540 processors. */ |
658 | static const | |
659 | struct processor_costs ppc8540_cost = { | |
06a67bdd RS |
660 | COSTS_N_INSNS (4), /* mulsi */ |
661 | COSTS_N_INSNS (4), /* mulsi_const */ | |
662 | COSTS_N_INSNS (4), /* mulsi_const9 */ | |
663 | COSTS_N_INSNS (4), /* muldi */ | |
664 | COSTS_N_INSNS (19), /* divsi */ | |
665 | COSTS_N_INSNS (19), /* divdi */ | |
666 | COSTS_N_INSNS (4), /* fp */ | |
667 | COSTS_N_INSNS (4), /* dmul */ | |
668 | COSTS_N_INSNS (29), /* sdiv */ | |
669 | COSTS_N_INSNS (29), /* ddiv */ | |
0d158b6e | 670 | 32, /* cache line size */ |
5f732aba DE |
671 | 32, /* l1 cache */ |
672 | 256, /* l2 cache */ | |
0b11da67 | 673 | 1, /* prefetch streams /*/ |
8b897cfa RS |
674 | }; |
675 | ||
fa41c305 EW |
676 | /* Instruction costs on E300C2 and E300C3 cores. */ |
677 | static const | |
678 | struct processor_costs ppce300c2c3_cost = { | |
679 | COSTS_N_INSNS (4), /* mulsi */ | |
680 | COSTS_N_INSNS (4), /* mulsi_const */ | |
681 | COSTS_N_INSNS (4), /* mulsi_const9 */ | |
682 | COSTS_N_INSNS (4), /* muldi */ | |
683 | COSTS_N_INSNS (19), /* divsi */ | |
684 | COSTS_N_INSNS (19), /* divdi */ | |
685 | COSTS_N_INSNS (3), /* fp */ | |
686 | COSTS_N_INSNS (4), /* dmul */ | |
687 | COSTS_N_INSNS (18), /* sdiv */ | |
688 | COSTS_N_INSNS (33), /* ddiv */ | |
642639ce | 689 | 32, |
a19b7d46 EW |
690 | 16, /* l1 cache */ |
691 | 16, /* l2 cache */ | |
642639ce | 692 | 1, /* prefetch streams /*/ |
fa41c305 EW |
693 | }; |
694 | ||
edae5fe3 DE |
695 | /* Instruction costs on PPCE500MC processors. */ |
696 | static const | |
697 | struct processor_costs ppce500mc_cost = { | |
698 | COSTS_N_INSNS (4), /* mulsi */ | |
699 | COSTS_N_INSNS (4), /* mulsi_const */ | |
700 | COSTS_N_INSNS (4), /* mulsi_const9 */ | |
701 | COSTS_N_INSNS (4), /* muldi */ | |
702 | COSTS_N_INSNS (14), /* divsi */ | |
703 | COSTS_N_INSNS (14), /* divdi */ | |
704 | COSTS_N_INSNS (8), /* fp */ | |
705 | COSTS_N_INSNS (10), /* dmul */ | |
706 | COSTS_N_INSNS (36), /* sdiv */ | |
707 | COSTS_N_INSNS (66), /* ddiv */ | |
708 | 64, /* cache line size */ | |
709 | 32, /* l1 cache */ | |
710 | 128, /* l2 cache */ | |
711 | 1, /* prefetch streams /*/ | |
712 | }; | |
713 | ||
8b897cfa RS |
714 | /* Instruction costs on POWER4 and POWER5 processors. */ |
715 | static const | |
716 | struct processor_costs power4_cost = { | |
06a67bdd RS |
717 | COSTS_N_INSNS (3), /* mulsi */ |
718 | COSTS_N_INSNS (2), /* mulsi_const */ | |
719 | COSTS_N_INSNS (2), /* mulsi_const9 */ | |
720 | COSTS_N_INSNS (4), /* muldi */ | |
721 | COSTS_N_INSNS (18), /* divsi */ | |
722 | COSTS_N_INSNS (34), /* divdi */ | |
723 | COSTS_N_INSNS (3), /* fp */ | |
724 | COSTS_N_INSNS (3), /* dmul */ | |
725 | COSTS_N_INSNS (17), /* sdiv */ | |
726 | COSTS_N_INSNS (17), /* ddiv */ | |
0d158b6e | 727 | 128, /* cache line size */ |
5f732aba DE |
728 | 32, /* l1 cache */ |
729 | 1024, /* l2 cache */ | |
0b11da67 | 730 | 8, /* prefetch streams /*/ |
8b897cfa RS |
731 | }; |
732 | ||
44cd321e PS |
733 | /* Instruction costs on POWER6 processors. */ |
734 | static const | |
735 | struct processor_costs power6_cost = { | |
736 | COSTS_N_INSNS (8), /* mulsi */ | |
737 | COSTS_N_INSNS (8), /* mulsi_const */ | |
738 | COSTS_N_INSNS (8), /* mulsi_const9 */ | |
739 | COSTS_N_INSNS (8), /* muldi */ | |
740 | COSTS_N_INSNS (22), /* divsi */ | |
741 | COSTS_N_INSNS (28), /* divdi */ | |
742 | COSTS_N_INSNS (3), /* fp */ | |
743 | COSTS_N_INSNS (3), /* dmul */ | |
744 | COSTS_N_INSNS (13), /* sdiv */ | |
745 | COSTS_N_INSNS (16), /* ddiv */ | |
0d158b6e | 746 | 128, /* cache line size */ |
5f732aba DE |
747 | 64, /* l1 cache */ |
748 | 2048, /* l2 cache */ | |
0b11da67 | 749 | 16, /* prefetch streams */ |
44cd321e PS |
750 | }; |
751 | ||
8b897cfa | 752 | \f |
a2369ed3 | 753 | static bool rs6000_function_ok_for_sibcall (tree, tree); |
3101faab | 754 | static const char *rs6000_invalid_within_doloop (const_rtx); |
a2369ed3 | 755 | static rtx rs6000_generate_compare (enum rtx_code); |
a2369ed3 DJ |
756 | static void rs6000_emit_stack_tie (void); |
757 | static void rs6000_frame_related (rtx, rtx, HOST_WIDE_INT, rtx, rtx); | |
a2369ed3 | 758 | static bool spe_func_has_64bit_regs_p (void); |
b20a9cca | 759 | static void emit_frame_save (rtx, rtx, enum machine_mode, unsigned int, |
d1d0c603 | 760 | int, HOST_WIDE_INT); |
a2369ed3 | 761 | static rtx gen_frame_mem_offset (enum machine_mode, rtx, int); |
f78c3290 | 762 | static void rs6000_emit_allocate_stack (HOST_WIDE_INT, int, int); |
a2369ed3 DJ |
763 | static unsigned rs6000_hash_constant (rtx); |
764 | static unsigned toc_hash_function (const void *); | |
765 | static int toc_hash_eq (const void *, const void *); | |
a2369ed3 | 766 | static bool constant_pool_expr_p (rtx); |
d04b6e6e | 767 | static bool legitimate_small_data_p (enum machine_mode, rtx); |
a2369ed3 DJ |
768 | static bool legitimate_lo_sum_address_p (enum machine_mode, rtx, int); |
769 | static struct machine_function * rs6000_init_machine_status (void); | |
770 | static bool rs6000_assemble_integer (rtx, unsigned int, int); | |
f78c3290 | 771 | static bool no_global_regs_above (int, bool); |
5add3202 | 772 | #ifdef HAVE_GAS_HIDDEN |
a2369ed3 | 773 | static void rs6000_assemble_visibility (tree, int); |
5add3202 | 774 | #endif |
a2369ed3 DJ |
775 | static int rs6000_ra_ever_killed (void); |
776 | static tree rs6000_handle_longcall_attribute (tree *, tree, tree, int, bool *); | |
8bb418a3 | 777 | static tree rs6000_handle_altivec_attribute (tree *, tree, tree, int, bool *); |
3101faab | 778 | static bool rs6000_ms_bitfield_layout_p (const_tree); |
77ccdfed | 779 | static tree rs6000_handle_struct_attribute (tree *, tree, tree, int, bool *); |
76d2b81d | 780 | static void rs6000_eliminate_indexed_memrefs (rtx operands[2]); |
3101faab | 781 | static const char *rs6000_mangle_type (const_tree); |
b86fe7b4 | 782 | extern const struct attribute_spec rs6000_attribute_table[]; |
a2369ed3 | 783 | static void rs6000_set_default_type_attributes (tree); |
f78c3290 NF |
784 | static rtx rs6000_savres_routine_sym (rs6000_stack_t *, bool, bool, bool); |
785 | static void rs6000_emit_stack_reset (rs6000_stack_t *, rtx, rtx, int, bool); | |
786 | static rtx rs6000_make_savres_rtx (rs6000_stack_t *, rtx, int, | |
787 | enum machine_mode, bool, bool, bool); | |
52ff33d0 | 788 | static bool rs6000_reg_live_or_pic_offset_p (int); |
f78c3290 NF |
789 | static int rs6000_savres_strategy (rs6000_stack_t *, bool, int, int); |
790 | static void rs6000_restore_saved_cr (rtx, int); | |
a2369ed3 DJ |
791 | static void rs6000_output_function_prologue (FILE *, HOST_WIDE_INT); |
792 | static void rs6000_output_function_epilogue (FILE *, HOST_WIDE_INT); | |
b20a9cca AM |
793 | static void rs6000_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT, |
794 | tree); | |
a2369ed3 | 795 | static rtx rs6000_emit_set_long_const (rtx, HOST_WIDE_INT, HOST_WIDE_INT); |
586de218 | 796 | static bool rs6000_return_in_memory (const_tree, const_tree); |
a2369ed3 | 797 | static void rs6000_file_start (void); |
7c262518 | 798 | #if TARGET_ELF |
9b580a0b | 799 | static int rs6000_elf_reloc_rw_mask (void); |
a2369ed3 DJ |
800 | static void rs6000_elf_asm_out_constructor (rtx, int); |
801 | static void rs6000_elf_asm_out_destructor (rtx, int); | |
1334b570 | 802 | static void rs6000_elf_end_indicate_exec_stack (void) ATTRIBUTE_UNUSED; |
d6b5193b | 803 | static void rs6000_elf_asm_init_sections (void); |
d6b5193b RS |
804 | static section *rs6000_elf_select_rtx_section (enum machine_mode, rtx, |
805 | unsigned HOST_WIDE_INT); | |
a56d7372 | 806 | static void rs6000_elf_encode_section_info (tree, rtx, int) |
0e5dbd9b | 807 | ATTRIBUTE_UNUSED; |
7c262518 | 808 | #endif |
3101faab | 809 | static bool rs6000_use_blocks_for_constant_p (enum machine_mode, const_rtx); |
e41b2a33 PB |
810 | static void rs6000_alloc_sdmode_stack_slot (void); |
811 | static void rs6000_instantiate_decls (void); | |
cbaaba19 | 812 | #if TARGET_XCOFF |
0d5817b2 | 813 | static void rs6000_xcoff_asm_output_anchor (rtx); |
a2369ed3 | 814 | static void rs6000_xcoff_asm_globalize_label (FILE *, const char *); |
d6b5193b | 815 | static void rs6000_xcoff_asm_init_sections (void); |
9b580a0b | 816 | static int rs6000_xcoff_reloc_rw_mask (void); |
8210e4c4 | 817 | static void rs6000_xcoff_asm_named_section (const char *, unsigned int, tree); |
d6b5193b | 818 | static section *rs6000_xcoff_select_section (tree, int, |
b20a9cca | 819 | unsigned HOST_WIDE_INT); |
d6b5193b RS |
820 | static void rs6000_xcoff_unique_section (tree, int); |
821 | static section *rs6000_xcoff_select_rtx_section | |
822 | (enum machine_mode, rtx, unsigned HOST_WIDE_INT); | |
a2369ed3 DJ |
823 | static const char * rs6000_xcoff_strip_name_encoding (const char *); |
824 | static unsigned int rs6000_xcoff_section_type_flags (tree, const char *, int); | |
825 | static void rs6000_xcoff_file_start (void); | |
826 | static void rs6000_xcoff_file_end (void); | |
f1384257 | 827 | #endif |
a2369ed3 | 828 | static int rs6000_variable_issue (FILE *, int, rtx, int); |
f40751dd | 829 | static bool rs6000_rtx_costs (rtx, int, int, int *, bool); |
a2369ed3 | 830 | static int rs6000_adjust_cost (rtx, rtx, rtx, int); |
44cd321e | 831 | static void rs6000_sched_init (FILE *, int, int); |
cbe26ab8 | 832 | static bool is_microcoded_insn (rtx); |
d296e02e | 833 | static bool is_nonpipeline_insn (rtx); |
cbe26ab8 DN |
834 | static bool is_cracked_insn (rtx); |
835 | static bool is_branch_slot_insn (rtx); | |
44cd321e | 836 | static bool is_load_insn (rtx); |
e3a0e200 | 837 | static rtx get_store_dest (rtx pat); |
44cd321e PS |
838 | static bool is_store_insn (rtx); |
839 | static bool set_to_load_agen (rtx,rtx); | |
982afe02 | 840 | static bool adjacent_mem_locations (rtx,rtx); |
a2369ed3 DJ |
841 | static int rs6000_adjust_priority (rtx, int); |
842 | static int rs6000_issue_rate (void); | |
b198261f | 843 | static bool rs6000_is_costly_dependence (dep_t, int, int); |
cbe26ab8 DN |
844 | static rtx get_next_active_insn (rtx, rtx); |
845 | static bool insn_terminates_group_p (rtx , enum group_termination); | |
44cd321e PS |
846 | static bool insn_must_be_first_in_group (rtx); |
847 | static bool insn_must_be_last_in_group (rtx); | |
cbe26ab8 DN |
848 | static bool is_costly_group (rtx *, rtx); |
849 | static int force_new_group (int, FILE *, rtx *, rtx, bool *, int, int *); | |
850 | static int redefine_groups (FILE *, int, rtx, rtx); | |
851 | static int pad_groups (FILE *, int, rtx, rtx); | |
852 | static void rs6000_sched_finish (FILE *, int); | |
44cd321e PS |
853 | static int rs6000_sched_reorder (FILE *, int, rtx *, int *, int); |
854 | static int rs6000_sched_reorder2 (FILE *, int, rtx *, int *, int); | |
a2369ed3 | 855 | static int rs6000_use_sched_lookahead (void); |
d296e02e | 856 | static int rs6000_use_sched_lookahead_guard (rtx); |
e855c69d AB |
857 | static void * rs6000_alloc_sched_context (void); |
858 | static void rs6000_init_sched_context (void *, bool); | |
859 | static void rs6000_set_sched_context (void *); | |
860 | static void rs6000_free_sched_context (void *); | |
9c78b944 | 861 | static tree rs6000_builtin_reciprocal (unsigned int, bool, bool); |
7ccf35ed | 862 | static tree rs6000_builtin_mask_for_load (void); |
89d67cca DN |
863 | static tree rs6000_builtin_mul_widen_even (tree); |
864 | static tree rs6000_builtin_mul_widen_odd (tree); | |
f57d17f1 | 865 | static tree rs6000_builtin_conversion (enum tree_code, tree); |
0fca40f5 | 866 | static tree rs6000_builtin_vec_perm (tree, tree *); |
a2369ed3 | 867 | |
58646b77 | 868 | static void def_builtin (int, const char *, tree, int); |
3101faab | 869 | static bool rs6000_vector_alignment_reachable (const_tree, bool); |
a2369ed3 DJ |
870 | static void rs6000_init_builtins (void); |
871 | static rtx rs6000_expand_unop_builtin (enum insn_code, tree, rtx); | |
872 | static rtx rs6000_expand_binop_builtin (enum insn_code, tree, rtx); | |
873 | static rtx rs6000_expand_ternop_builtin (enum insn_code, tree, rtx); | |
874 | static rtx rs6000_expand_builtin (tree, rtx, rtx, enum machine_mode, int); | |
875 | static void altivec_init_builtins (void); | |
876 | static void rs6000_common_init_builtins (void); | |
c15c90bb | 877 | static void rs6000_init_libfuncs (void); |
a2369ed3 | 878 | |
96038623 DE |
879 | static void paired_init_builtins (void); |
880 | static rtx paired_expand_builtin (tree, rtx, bool *); | |
881 | static rtx paired_expand_lv_builtin (enum insn_code, tree, rtx); | |
882 | static rtx paired_expand_stv_builtin (enum insn_code, tree); | |
883 | static rtx paired_expand_predicate_builtin (enum insn_code, tree, rtx); | |
884 | ||
b20a9cca AM |
885 | static void enable_mask_for_builtins (struct builtin_description *, int, |
886 | enum rs6000_builtins, | |
887 | enum rs6000_builtins); | |
a2369ed3 DJ |
888 | static void spe_init_builtins (void); |
889 | static rtx spe_expand_builtin (tree, rtx, bool *); | |
61bea3b0 | 890 | static rtx spe_expand_stv_builtin (enum insn_code, tree); |
a2369ed3 DJ |
891 | static rtx spe_expand_predicate_builtin (enum insn_code, tree, rtx); |
892 | static rtx spe_expand_evsel_builtin (enum insn_code, tree, rtx); | |
893 | static int rs6000_emit_int_cmove (rtx, rtx, rtx, rtx); | |
d1d0c603 JJ |
894 | static rs6000_stack_t *rs6000_stack_info (void); |
895 | static void debug_stack_info (rs6000_stack_t *); | |
a2369ed3 DJ |
896 | |
897 | static rtx altivec_expand_builtin (tree, rtx, bool *); | |
898 | static rtx altivec_expand_ld_builtin (tree, rtx, bool *); | |
899 | static rtx altivec_expand_st_builtin (tree, rtx, bool *); | |
900 | static rtx altivec_expand_dst_builtin (tree, rtx, bool *); | |
901 | static rtx altivec_expand_abs_builtin (enum insn_code, tree, rtx); | |
f676971a | 902 | static rtx altivec_expand_predicate_builtin (enum insn_code, |
c4ad648e | 903 | const char *, tree, rtx); |
a2369ed3 | 904 | static rtx altivec_expand_stv_builtin (enum insn_code, tree); |
7a4eca66 DE |
905 | static rtx altivec_expand_vec_init_builtin (tree, tree, rtx); |
906 | static rtx altivec_expand_vec_set_builtin (tree); | |
907 | static rtx altivec_expand_vec_ext_builtin (tree, rtx); | |
908 | static int get_element_number (tree, tree); | |
78f5898b | 909 | static bool rs6000_handle_option (size_t, const char *, int); |
a2369ed3 | 910 | static void rs6000_parse_tls_size_option (void); |
5da702b1 | 911 | static void rs6000_parse_yes_no_option (const char *, const char *, int *); |
a2369ed3 DJ |
912 | static int first_altivec_reg_to_save (void); |
913 | static unsigned int compute_vrsave_mask (void); | |
9390387d | 914 | static void compute_save_world_info (rs6000_stack_t *info_ptr); |
a2369ed3 DJ |
915 | static void is_altivec_return_reg (rtx, void *); |
916 | static rtx generate_set_vrsave (rtx, rs6000_stack_t *, int); | |
917 | int easy_vector_constant (rtx, enum machine_mode); | |
a2369ed3 | 918 | static rtx rs6000_dwarf_register_span (rtx); |
37ea0b7e | 919 | static void rs6000_init_dwarf_reg_sizes_extra (tree); |
a2369ed3 | 920 | static rtx rs6000_legitimize_tls_address (rtx, enum tls_model); |
fdbe66f2 | 921 | static void rs6000_output_dwarf_dtprel (FILE *, int, rtx) ATTRIBUTE_UNUSED; |
a2369ed3 DJ |
922 | static rtx rs6000_tls_get_addr (void); |
923 | static rtx rs6000_got_sym (void); | |
9390387d | 924 | static int rs6000_tls_symbol_ref_1 (rtx *, void *); |
a2369ed3 DJ |
925 | static const char *rs6000_get_some_local_dynamic_name (void); |
926 | static int rs6000_get_some_local_dynamic_name_1 (rtx *, void *); | |
ded9bf77 | 927 | static rtx rs6000_complex_function_value (enum machine_mode); |
b20a9cca | 928 | static rtx rs6000_spe_function_arg (CUMULATIVE_ARGS *, |
a2369ed3 | 929 | enum machine_mode, tree); |
0b5383eb DJ |
930 | static void rs6000_darwin64_record_arg_advance_flush (CUMULATIVE_ARGS *, |
931 | HOST_WIDE_INT); | |
932 | static void rs6000_darwin64_record_arg_advance_recurse (CUMULATIVE_ARGS *, | |
933 | tree, HOST_WIDE_INT); | |
934 | static void rs6000_darwin64_record_arg_flush (CUMULATIVE_ARGS *, | |
935 | HOST_WIDE_INT, | |
936 | rtx[], int *); | |
937 | static void rs6000_darwin64_record_arg_recurse (CUMULATIVE_ARGS *, | |
586de218 KG |
938 | const_tree, HOST_WIDE_INT, |
939 | rtx[], int *); | |
940 | static rtx rs6000_darwin64_record_arg (CUMULATIVE_ARGS *, const_tree, int, bool); | |
ec6376ab | 941 | static rtx rs6000_mixed_function_arg (enum machine_mode, tree, int); |
b1917422 | 942 | static void rs6000_move_block_from_reg (int regno, rtx x, int nregs); |
c6e8c921 GK |
943 | static void setup_incoming_varargs (CUMULATIVE_ARGS *, |
944 | enum machine_mode, tree, | |
945 | int *, int); | |
8cd5a4e0 | 946 | static bool rs6000_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode, |
586de218 | 947 | const_tree, bool); |
78a52f11 RH |
948 | static int rs6000_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode, |
949 | tree, bool); | |
3101faab | 950 | static const char *invalid_arg_for_unprototyped_fn (const_tree, const_tree, const_tree); |
efdba735 SH |
951 | #if TARGET_MACHO |
952 | static void macho_branch_islands (void); | |
efdba735 SH |
953 | static int no_previous_def (tree function_name); |
954 | static tree get_prev_label (tree function_name); | |
c4e18b1c | 955 | static void rs6000_darwin_file_start (void); |
efdba735 SH |
956 | #endif |
957 | ||
c35d187f | 958 | static tree rs6000_build_builtin_va_list (void); |
d7bd8aeb | 959 | static void rs6000_va_start (tree, rtx); |
726a989a | 960 | static tree rs6000_gimplify_va_arg (tree, tree, gimple_seq *, gimple_seq *); |
586de218 | 961 | static bool rs6000_must_pass_in_stack (enum machine_mode, const_tree); |
00b79d54 | 962 | static bool rs6000_scalar_mode_supported_p (enum machine_mode); |
f676971a | 963 | static bool rs6000_vector_mode_supported_p (enum machine_mode); |
94ff898d | 964 | static int get_vec_cmp_insn (enum rtx_code, enum machine_mode, |
21213b4c | 965 | enum machine_mode); |
94ff898d | 966 | static rtx rs6000_emit_vector_compare (enum rtx_code, rtx, rtx, |
21213b4c DP |
967 | enum machine_mode); |
968 | static int get_vsel_insn (enum machine_mode); | |
969 | static void rs6000_emit_vector_select (rtx, rtx, rtx, rtx); | |
3aebbe5f | 970 | static tree rs6000_stack_protect_fail (void); |
21213b4c DP |
971 | |
972 | const int INSN_NOT_AVAILABLE = -1; | |
93f90be6 FJ |
973 | static enum machine_mode rs6000_eh_return_filter_mode (void); |
974 | ||
17211ab5 GK |
975 | /* Hash table stuff for keeping track of TOC entries. */ |
976 | ||
977 | struct toc_hash_struct GTY(()) | |
978 | { | |
979 | /* `key' will satisfy CONSTANT_P; in fact, it will satisfy | |
980 | ASM_OUTPUT_SPECIAL_POOL_ENTRY_P. */ | |
981 | rtx key; | |
982 | enum machine_mode key_mode; | |
983 | int labelno; | |
984 | }; | |
985 | ||
986 | static GTY ((param_is (struct toc_hash_struct))) htab_t toc_hash_table; | |
c81bebd7 MM |
987 | \f |
988 | /* Default register names. */ | |
989 | char rs6000_reg_names[][8] = | |
990 | { | |
802a0058 MM |
991 | "0", "1", "2", "3", "4", "5", "6", "7", |
992 | "8", "9", "10", "11", "12", "13", "14", "15", | |
993 | "16", "17", "18", "19", "20", "21", "22", "23", | |
994 | "24", "25", "26", "27", "28", "29", "30", "31", | |
995 | "0", "1", "2", "3", "4", "5", "6", "7", | |
996 | "8", "9", "10", "11", "12", "13", "14", "15", | |
997 | "16", "17", "18", "19", "20", "21", "22", "23", | |
998 | "24", "25", "26", "27", "28", "29", "30", "31", | |
999 | "mq", "lr", "ctr","ap", | |
1000 | "0", "1", "2", "3", "4", "5", "6", "7", | |
0ac081f6 AH |
1001 | "xer", |
1002 | /* AltiVec registers. */ | |
0cd5e3a1 AH |
1003 | "0", "1", "2", "3", "4", "5", "6", "7", |
1004 | "8", "9", "10", "11", "12", "13", "14", "15", | |
1005 | "16", "17", "18", "19", "20", "21", "22", "23", | |
1006 | "24", "25", "26", "27", "28", "29", "30", "31", | |
59a4c851 AH |
1007 | "vrsave", "vscr", |
1008 | /* SPE registers. */ | |
7d5175e1 JJ |
1009 | "spe_acc", "spefscr", |
1010 | /* Soft frame pointer. */ | |
1011 | "sfp" | |
c81bebd7 MM |
1012 | }; |
1013 | ||
1014 | #ifdef TARGET_REGNAMES | |
8b60264b | 1015 | static const char alt_reg_names[][8] = |
c81bebd7 | 1016 | { |
802a0058 MM |
1017 | "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7", |
1018 | "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15", | |
1019 | "%r16", "%r17", "%r18", "%r19", "%r20", "%r21", "%r22", "%r23", | |
1020 | "%r24", "%r25", "%r26", "%r27", "%r28", "%r29", "%r30", "%r31", | |
1021 | "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7", | |
1022 | "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15", | |
1023 | "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23", | |
1024 | "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31", | |
1025 | "mq", "lr", "ctr", "ap", | |
1026 | "%cr0", "%cr1", "%cr2", "%cr3", "%cr4", "%cr5", "%cr6", "%cr7", | |
0ac081f6 | 1027 | "xer", |
59a4c851 | 1028 | /* AltiVec registers. */ |
0ac081f6 | 1029 | "%v0", "%v1", "%v2", "%v3", "%v4", "%v5", "%v6", "%v7", |
59a4c851 AH |
1030 | "%v8", "%v9", "%v10", "%v11", "%v12", "%v13", "%v14", "%v15", |
1031 | "%v16", "%v17", "%v18", "%v19", "%v20", "%v21", "%v22", "%v23", | |
1032 | "%v24", "%v25", "%v26", "%v27", "%v28", "%v29", "%v30", "%v31", | |
1033 | "vrsave", "vscr", | |
1034 | /* SPE registers. */ | |
7d5175e1 JJ |
1035 | "spe_acc", "spefscr", |
1036 | /* Soft frame pointer. */ | |
1037 | "sfp" | |
c81bebd7 MM |
1038 | }; |
1039 | #endif | |
9878760c | 1040 | \f |
daf11973 MM |
1041 | #ifndef MASK_STRICT_ALIGN |
1042 | #define MASK_STRICT_ALIGN 0 | |
1043 | #endif | |
ffcfcb5f AM |
1044 | #ifndef TARGET_PROFILE_KERNEL |
1045 | #define TARGET_PROFILE_KERNEL 0 | |
1046 | #endif | |
3961e8fe RH |
1047 | |
1048 | /* The VRSAVE bitmask puts bit %v0 as the most significant bit. */ | |
1049 | #define ALTIVEC_REG_BIT(REGNO) (0x80000000 >> ((REGNO) - FIRST_ALTIVEC_REGNO)) | |
672a6f42 NB |
1050 | \f |
1051 | /* Initialize the GCC target structure. */ | |
91d231cb JM |
1052 | #undef TARGET_ATTRIBUTE_TABLE |
1053 | #define TARGET_ATTRIBUTE_TABLE rs6000_attribute_table | |
a5c76ee6 ZW |
1054 | #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES |
1055 | #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES rs6000_set_default_type_attributes | |
daf11973 | 1056 | |
301d03af RS |
1057 | #undef TARGET_ASM_ALIGNED_DI_OP |
1058 | #define TARGET_ASM_ALIGNED_DI_OP DOUBLE_INT_ASM_OP | |
1059 | ||
1060 | /* Default unaligned ops are only provided for ELF. Find the ops needed | |
1061 | for non-ELF systems. */ | |
1062 | #ifndef OBJECT_FORMAT_ELF | |
cbaaba19 | 1063 | #if TARGET_XCOFF |
ae6c1efd | 1064 | /* For XCOFF. rs6000_assemble_integer will handle unaligned DIs on |
301d03af RS |
1065 | 64-bit targets. */ |
1066 | #undef TARGET_ASM_UNALIGNED_HI_OP | |
1067 | #define TARGET_ASM_UNALIGNED_HI_OP "\t.vbyte\t2," | |
1068 | #undef TARGET_ASM_UNALIGNED_SI_OP | |
1069 | #define TARGET_ASM_UNALIGNED_SI_OP "\t.vbyte\t4," | |
1070 | #undef TARGET_ASM_UNALIGNED_DI_OP | |
1071 | #define TARGET_ASM_UNALIGNED_DI_OP "\t.vbyte\t8," | |
1072 | #else | |
1073 | /* For Darwin. */ | |
1074 | #undef TARGET_ASM_UNALIGNED_HI_OP | |
1075 | #define TARGET_ASM_UNALIGNED_HI_OP "\t.short\t" | |
1076 | #undef TARGET_ASM_UNALIGNED_SI_OP | |
1077 | #define TARGET_ASM_UNALIGNED_SI_OP "\t.long\t" | |
49bd1d27 SS |
1078 | #undef TARGET_ASM_UNALIGNED_DI_OP |
1079 | #define TARGET_ASM_UNALIGNED_DI_OP "\t.quad\t" | |
1080 | #undef TARGET_ASM_ALIGNED_DI_OP | |
1081 | #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t" | |
301d03af RS |
1082 | #endif |
1083 | #endif | |
1084 | ||
1085 | /* This hook deals with fixups for relocatable code and DI-mode objects | |
1086 | in 64-bit code. */ | |
1087 | #undef TARGET_ASM_INTEGER | |
1088 | #define TARGET_ASM_INTEGER rs6000_assemble_integer | |
1089 | ||
93638d7a AM |
1090 | #ifdef HAVE_GAS_HIDDEN |
1091 | #undef TARGET_ASM_ASSEMBLE_VISIBILITY | |
1092 | #define TARGET_ASM_ASSEMBLE_VISIBILITY rs6000_assemble_visibility | |
1093 | #endif | |
1094 | ||
c4501e62 JJ |
1095 | #undef TARGET_HAVE_TLS |
1096 | #define TARGET_HAVE_TLS HAVE_AS_TLS | |
1097 | ||
1098 | #undef TARGET_CANNOT_FORCE_CONST_MEM | |
a7e0b075 | 1099 | #define TARGET_CANNOT_FORCE_CONST_MEM rs6000_tls_referenced_p |
c4501e62 | 1100 | |
08c148a8 NB |
1101 | #undef TARGET_ASM_FUNCTION_PROLOGUE |
1102 | #define TARGET_ASM_FUNCTION_PROLOGUE rs6000_output_function_prologue | |
1103 | #undef TARGET_ASM_FUNCTION_EPILOGUE | |
1104 | #define TARGET_ASM_FUNCTION_EPILOGUE rs6000_output_function_epilogue | |
1105 | ||
b54cf83a DE |
1106 | #undef TARGET_SCHED_VARIABLE_ISSUE |
1107 | #define TARGET_SCHED_VARIABLE_ISSUE rs6000_variable_issue | |
1108 | ||
c237e94a ZW |
1109 | #undef TARGET_SCHED_ISSUE_RATE |
1110 | #define TARGET_SCHED_ISSUE_RATE rs6000_issue_rate | |
1111 | #undef TARGET_SCHED_ADJUST_COST | |
1112 | #define TARGET_SCHED_ADJUST_COST rs6000_adjust_cost | |
1113 | #undef TARGET_SCHED_ADJUST_PRIORITY | |
1114 | #define TARGET_SCHED_ADJUST_PRIORITY rs6000_adjust_priority | |
f676971a | 1115 | #undef TARGET_SCHED_IS_COSTLY_DEPENDENCE |
569fa502 | 1116 | #define TARGET_SCHED_IS_COSTLY_DEPENDENCE rs6000_is_costly_dependence |
44cd321e PS |
1117 | #undef TARGET_SCHED_INIT |
1118 | #define TARGET_SCHED_INIT rs6000_sched_init | |
cbe26ab8 DN |
1119 | #undef TARGET_SCHED_FINISH |
1120 | #define TARGET_SCHED_FINISH rs6000_sched_finish | |
44cd321e PS |
1121 | #undef TARGET_SCHED_REORDER |
1122 | #define TARGET_SCHED_REORDER rs6000_sched_reorder | |
1123 | #undef TARGET_SCHED_REORDER2 | |
1124 | #define TARGET_SCHED_REORDER2 rs6000_sched_reorder2 | |
c237e94a | 1125 | |
be12c2b0 VM |
1126 | #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD |
1127 | #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD rs6000_use_sched_lookahead | |
1128 | ||
d296e02e AP |
1129 | #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD |
1130 | #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD rs6000_use_sched_lookahead_guard | |
1131 | ||
e855c69d AB |
1132 | #undef TARGET_SCHED_ALLOC_SCHED_CONTEXT |
1133 | #define TARGET_SCHED_ALLOC_SCHED_CONTEXT rs6000_alloc_sched_context | |
1134 | #undef TARGET_SCHED_INIT_SCHED_CONTEXT | |
1135 | #define TARGET_SCHED_INIT_SCHED_CONTEXT rs6000_init_sched_context | |
1136 | #undef TARGET_SCHED_SET_SCHED_CONTEXT | |
1137 | #define TARGET_SCHED_SET_SCHED_CONTEXT rs6000_set_sched_context | |
1138 | #undef TARGET_SCHED_FREE_SCHED_CONTEXT | |
1139 | #define TARGET_SCHED_FREE_SCHED_CONTEXT rs6000_free_sched_context | |
1140 | ||
7ccf35ed DN |
1141 | #undef TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD |
1142 | #define TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD rs6000_builtin_mask_for_load | |
89d67cca DN |
1143 | #undef TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_EVEN |
1144 | #define TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_EVEN rs6000_builtin_mul_widen_even | |
1145 | #undef TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_ODD | |
1146 | #define TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_ODD rs6000_builtin_mul_widen_odd | |
f57d17f1 TM |
1147 | #undef TARGET_VECTORIZE_BUILTIN_CONVERSION |
1148 | #define TARGET_VECTORIZE_BUILTIN_CONVERSION rs6000_builtin_conversion | |
0fca40f5 IR |
1149 | #undef TARGET_VECTORIZE_BUILTIN_VEC_PERM |
1150 | #define TARGET_VECTORIZE_BUILTIN_VEC_PERM rs6000_builtin_vec_perm | |
7ccf35ed | 1151 | |
5b900a4c DN |
1152 | #undef TARGET_VECTOR_ALIGNMENT_REACHABLE |
1153 | #define TARGET_VECTOR_ALIGNMENT_REACHABLE rs6000_vector_alignment_reachable | |
1154 | ||
0ac081f6 AH |
1155 | #undef TARGET_INIT_BUILTINS |
1156 | #define TARGET_INIT_BUILTINS rs6000_init_builtins | |
1157 | ||
1158 | #undef TARGET_EXPAND_BUILTIN | |
1159 | #define TARGET_EXPAND_BUILTIN rs6000_expand_builtin | |
1160 | ||
608063c3 JB |
1161 | #undef TARGET_MANGLE_TYPE |
1162 | #define TARGET_MANGLE_TYPE rs6000_mangle_type | |
f18eca82 | 1163 | |
c15c90bb ZW |
1164 | #undef TARGET_INIT_LIBFUNCS |
1165 | #define TARGET_INIT_LIBFUNCS rs6000_init_libfuncs | |
1166 | ||
f1384257 | 1167 | #if TARGET_MACHO |
0e5dbd9b | 1168 | #undef TARGET_BINDS_LOCAL_P |
31920d83 | 1169 | #define TARGET_BINDS_LOCAL_P darwin_binds_local_p |
f1384257 | 1170 | #endif |
0e5dbd9b | 1171 | |
77ccdfed EC |
1172 | #undef TARGET_MS_BITFIELD_LAYOUT_P |
1173 | #define TARGET_MS_BITFIELD_LAYOUT_P rs6000_ms_bitfield_layout_p | |
1174 | ||
3961e8fe RH |
1175 | #undef TARGET_ASM_OUTPUT_MI_THUNK |
1176 | #define TARGET_ASM_OUTPUT_MI_THUNK rs6000_output_mi_thunk | |
1177 | ||
3961e8fe | 1178 | #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK |
3101faab | 1179 | #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true |
00b960c7 | 1180 | |
4977bab6 ZW |
1181 | #undef TARGET_FUNCTION_OK_FOR_SIBCALL |
1182 | #define TARGET_FUNCTION_OK_FOR_SIBCALL rs6000_function_ok_for_sibcall | |
1183 | ||
2e3f0db6 DJ |
1184 | #undef TARGET_INVALID_WITHIN_DOLOOP |
1185 | #define TARGET_INVALID_WITHIN_DOLOOP rs6000_invalid_within_doloop | |
9419649c | 1186 | |
3c50106f RH |
1187 | #undef TARGET_RTX_COSTS |
1188 | #define TARGET_RTX_COSTS rs6000_rtx_costs | |
dcefdf67 | 1189 | #undef TARGET_ADDRESS_COST |
f40751dd | 1190 | #define TARGET_ADDRESS_COST hook_int_rtx_bool_0 |
3c50106f | 1191 | |
96714395 AH |
1192 | #undef TARGET_DWARF_REGISTER_SPAN |
1193 | #define TARGET_DWARF_REGISTER_SPAN rs6000_dwarf_register_span | |
1194 | ||
37ea0b7e JM |
1195 | #undef TARGET_INIT_DWARF_REG_SIZES_EXTRA |
1196 | #define TARGET_INIT_DWARF_REG_SIZES_EXTRA rs6000_init_dwarf_reg_sizes_extra | |
1197 | ||
c6e8c921 GK |
1198 | /* On rs6000, function arguments are promoted, as are function return |
1199 | values. */ | |
1200 | #undef TARGET_PROMOTE_FUNCTION_ARGS | |
586de218 | 1201 | #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_const_tree_true |
c6e8c921 | 1202 | #undef TARGET_PROMOTE_FUNCTION_RETURN |
586de218 | 1203 | #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_const_tree_true |
c6e8c921 | 1204 | |
c6e8c921 GK |
1205 | #undef TARGET_RETURN_IN_MEMORY |
1206 | #define TARGET_RETURN_IN_MEMORY rs6000_return_in_memory | |
1207 | ||
1208 | #undef TARGET_SETUP_INCOMING_VARARGS | |
1209 | #define TARGET_SETUP_INCOMING_VARARGS setup_incoming_varargs | |
1210 | ||
1211 | /* Always strict argument naming on rs6000. */ | |
1212 | #undef TARGET_STRICT_ARGUMENT_NAMING | |
1213 | #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true | |
1214 | #undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED | |
1215 | #define TARGET_PRETEND_OUTGOING_VARARGS_NAMED hook_bool_CUMULATIVE_ARGS_true | |
42ba5130 | 1216 | #undef TARGET_SPLIT_COMPLEX_ARG |
3101faab | 1217 | #define TARGET_SPLIT_COMPLEX_ARG hook_bool_const_tree_true |
fe984136 RH |
1218 | #undef TARGET_MUST_PASS_IN_STACK |
1219 | #define TARGET_MUST_PASS_IN_STACK rs6000_must_pass_in_stack | |
8cd5a4e0 RH |
1220 | #undef TARGET_PASS_BY_REFERENCE |
1221 | #define TARGET_PASS_BY_REFERENCE rs6000_pass_by_reference | |
78a52f11 RH |
1222 | #undef TARGET_ARG_PARTIAL_BYTES |
1223 | #define TARGET_ARG_PARTIAL_BYTES rs6000_arg_partial_bytes | |
c6e8c921 | 1224 | |
c35d187f RH |
1225 | #undef TARGET_BUILD_BUILTIN_VA_LIST |
1226 | #define TARGET_BUILD_BUILTIN_VA_LIST rs6000_build_builtin_va_list | |
1227 | ||
d7bd8aeb JJ |
1228 | #undef TARGET_EXPAND_BUILTIN_VA_START |
1229 | #define TARGET_EXPAND_BUILTIN_VA_START rs6000_va_start | |
1230 | ||
cd3ce9b4 JM |
1231 | #undef TARGET_GIMPLIFY_VA_ARG_EXPR |
1232 | #define TARGET_GIMPLIFY_VA_ARG_EXPR rs6000_gimplify_va_arg | |
1233 | ||
93f90be6 FJ |
1234 | #undef TARGET_EH_RETURN_FILTER_MODE |
1235 | #define TARGET_EH_RETURN_FILTER_MODE rs6000_eh_return_filter_mode | |
1236 | ||
00b79d54 BE |
1237 | #undef TARGET_SCALAR_MODE_SUPPORTED_P |
1238 | #define TARGET_SCALAR_MODE_SUPPORTED_P rs6000_scalar_mode_supported_p | |
1239 | ||
f676971a EC |
1240 | #undef TARGET_VECTOR_MODE_SUPPORTED_P |
1241 | #define TARGET_VECTOR_MODE_SUPPORTED_P rs6000_vector_mode_supported_p | |
1242 | ||
4d3e6fae FJ |
1243 | #undef TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN |
1244 | #define TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN invalid_arg_for_unprototyped_fn | |
1245 | ||
78f5898b AH |
1246 | #undef TARGET_HANDLE_OPTION |
1247 | #define TARGET_HANDLE_OPTION rs6000_handle_option | |
1248 | ||
1249 | #undef TARGET_DEFAULT_TARGET_FLAGS | |
1250 | #define TARGET_DEFAULT_TARGET_FLAGS \ | |
716019c0 | 1251 | (TARGET_DEFAULT) |
78f5898b | 1252 | |
3aebbe5f JJ |
1253 | #undef TARGET_STACK_PROTECT_FAIL |
1254 | #define TARGET_STACK_PROTECT_FAIL rs6000_stack_protect_fail | |
1255 | ||
445cf5eb JM |
1256 | /* MPC604EUM 3.5.2 Weak Consistency between Multiple Processors |
1257 | The PowerPC architecture requires only weak consistency among | |
1258 | processors--that is, memory accesses between processors need not be | |
1259 | sequentially consistent and memory accesses among processors can occur | |
1260 | in any order. The ability to order memory accesses weakly provides | |
1261 | opportunities for more efficient use of the system bus. Unless a | |
1262 | dependency exists, the 604e allows read operations to precede store | |
1263 | operations. */ | |
1264 | #undef TARGET_RELAXED_ORDERING | |
1265 | #define TARGET_RELAXED_ORDERING true | |
1266 | ||
fdbe66f2 EB |
1267 | #ifdef HAVE_AS_TLS |
1268 | #undef TARGET_ASM_OUTPUT_DWARF_DTPREL | |
1269 | #define TARGET_ASM_OUTPUT_DWARF_DTPREL rs6000_output_dwarf_dtprel | |
1270 | #endif | |
1271 | ||
aacd3885 RS |
1272 | /* Use a 32-bit anchor range. This leads to sequences like: |
1273 | ||
1274 | addis tmp,anchor,high | |
1275 | add dest,tmp,low | |
1276 | ||
1277 | where tmp itself acts as an anchor, and can be shared between | |
1278 | accesses to the same 64k page. */ | |
1279 | #undef TARGET_MIN_ANCHOR_OFFSET | |
1280 | #define TARGET_MIN_ANCHOR_OFFSET -0x7fffffff - 1 | |
1281 | #undef TARGET_MAX_ANCHOR_OFFSET | |
1282 | #define TARGET_MAX_ANCHOR_OFFSET 0x7fffffff | |
1283 | #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P | |
1284 | #define TARGET_USE_BLOCKS_FOR_CONSTANT_P rs6000_use_blocks_for_constant_p | |
1285 | ||
9c78b944 DE |
1286 | #undef TARGET_BUILTIN_RECIPROCAL |
1287 | #define TARGET_BUILTIN_RECIPROCAL rs6000_builtin_reciprocal | |
1288 | ||
e41b2a33 PB |
1289 | #undef TARGET_EXPAND_TO_RTL_HOOK |
1290 | #define TARGET_EXPAND_TO_RTL_HOOK rs6000_alloc_sdmode_stack_slot | |
1291 | ||
1292 | #undef TARGET_INSTANTIATE_DECLS | |
1293 | #define TARGET_INSTANTIATE_DECLS rs6000_instantiate_decls | |
1294 | ||
f6897b10 | 1295 | struct gcc_target targetm = TARGET_INITIALIZER; |
672a6f42 | 1296 | \f |
0d1fbc8c AH |
1297 | |
1298 | /* Value is 1 if hard register REGNO can hold a value of machine-mode | |
1299 | MODE. */ | |
1300 | static int | |
1301 | rs6000_hard_regno_mode_ok (int regno, enum machine_mode mode) | |
1302 | { | |
1303 | /* The GPRs can hold any mode, but values bigger than one register | |
1304 | cannot go past R31. */ | |
1305 | if (INT_REGNO_P (regno)) | |
1306 | return INT_REGNO_P (regno + HARD_REGNO_NREGS (regno, mode) - 1); | |
1307 | ||
a5a97921 | 1308 | /* The float registers can only hold floating modes and DImode. |
7393f7f8 | 1309 | This excludes the 32-bit decimal float mode for now. */ |
0d1fbc8c AH |
1310 | if (FP_REGNO_P (regno)) |
1311 | return | |
96038623 | 1312 | ((SCALAR_FLOAT_MODE_P (mode) |
c092b045 | 1313 | && (mode != TDmode || (regno % 2) == 0) |
0d1fbc8c AH |
1314 | && FP_REGNO_P (regno + HARD_REGNO_NREGS (regno, mode) - 1)) |
1315 | || (GET_MODE_CLASS (mode) == MODE_INT | |
96038623 DE |
1316 | && GET_MODE_SIZE (mode) == UNITS_PER_FP_WORD) |
1317 | || (PAIRED_SIMD_REGNO_P (regno) && TARGET_PAIRED_FLOAT | |
1318 | && PAIRED_VECTOR_MODE (mode))); | |
0d1fbc8c AH |
1319 | |
1320 | /* The CR register can only hold CC modes. */ | |
1321 | if (CR_REGNO_P (regno)) | |
1322 | return GET_MODE_CLASS (mode) == MODE_CC; | |
1323 | ||
1324 | if (XER_REGNO_P (regno)) | |
1325 | return mode == PSImode; | |
1326 | ||
1327 | /* AltiVec only in AldyVec registers. */ | |
1328 | if (ALTIVEC_REGNO_P (regno)) | |
1329 | return ALTIVEC_VECTOR_MODE (mode); | |
1330 | ||
1331 | /* ...but GPRs can hold SIMD data on the SPE in one register. */ | |
1332 | if (SPE_SIMD_REGNO_P (regno) && TARGET_SPE && SPE_VECTOR_MODE (mode)) | |
1333 | return 1; | |
1334 | ||
1335 | /* We cannot put TImode anywhere except general register and it must be | |
1336 | able to fit within the register set. */ | |
1337 | ||
1338 | return GET_MODE_SIZE (mode) <= UNITS_PER_WORD; | |
1339 | } | |
1340 | ||
1341 | /* Initialize rs6000_hard_regno_mode_ok_p table. */ | |
1342 | static void | |
1343 | rs6000_init_hard_regno_mode_ok (void) | |
1344 | { | |
1345 | int r, m; | |
1346 | ||
1347 | for (r = 0; r < FIRST_PSEUDO_REGISTER; ++r) | |
1348 | for (m = 0; m < NUM_MACHINE_MODES; ++m) | |
bbbbb16a | 1349 | if (rs6000_hard_regno_mode_ok (r, (enum machine_mode) m)) |
0d1fbc8c AH |
1350 | rs6000_hard_regno_mode_ok_p[m][r] = true; |
1351 | } | |
1352 | ||
e4cad568 GK |
1353 | #if TARGET_MACHO |
1354 | /* The Darwin version of SUBTARGET_OVERRIDE_OPTIONS. */ | |
1355 | ||
1356 | static void | |
1357 | darwin_rs6000_override_options (void) | |
1358 | { | |
1359 | /* The Darwin ABI always includes AltiVec, can't be (validly) turned | |
1360 | off. */ | |
1361 | rs6000_altivec_abi = 1; | |
1362 | TARGET_ALTIVEC_VRSAVE = 1; | |
1363 | if (DEFAULT_ABI == ABI_DARWIN) | |
1364 | { | |
1365 | if (MACHO_DYNAMIC_NO_PIC_P) | |
1366 | { | |
1367 | if (flag_pic) | |
1368 | warning (0, "-mdynamic-no-pic overrides -fpic or -fPIC"); | |
1369 | flag_pic = 0; | |
1370 | } | |
1371 | else if (flag_pic == 1) | |
1372 | { | |
1373 | flag_pic = 2; | |
1374 | } | |
1375 | } | |
1376 | if (TARGET_64BIT && ! TARGET_POWERPC64) | |
1377 | { | |
1378 | target_flags |= MASK_POWERPC64; | |
1379 | warning (0, "-m64 requires PowerPC64 architecture, enabling"); | |
1380 | } | |
1381 | if (flag_mkernel) | |
1382 | { | |
1383 | rs6000_default_long_calls = 1; | |
1384 | target_flags |= MASK_SOFT_FLOAT; | |
1385 | } | |
1386 | ||
1387 | /* Make -m64 imply -maltivec. Darwin's 64-bit ABI includes | |
1388 | Altivec. */ | |
1389 | if (!flag_mkernel && !flag_apple_kext | |
1390 | && TARGET_64BIT | |
1391 | && ! (target_flags_explicit & MASK_ALTIVEC)) | |
1392 | target_flags |= MASK_ALTIVEC; | |
1393 | ||
1394 | /* Unless the user (not the configurer) has explicitly overridden | |
1395 | it with -mcpu=G3 or -mno-altivec, then 10.5+ targets default to | |
1396 | G4 unless targetting the kernel. */ | |
1397 | if (!flag_mkernel | |
1398 | && !flag_apple_kext | |
1399 | && strverscmp (darwin_macosx_version_min, "10.5") >= 0 | |
1400 | && ! (target_flags_explicit & MASK_ALTIVEC) | |
1401 | && ! rs6000_select[1].string) | |
1402 | { | |
1403 | target_flags |= MASK_ALTIVEC; | |
1404 | } | |
1405 | } | |
1406 | #endif | |
1407 | ||
c1e55850 GK |
1408 | /* If not otherwise specified by a target, make 'long double' equivalent to |
1409 | 'double'. */ | |
1410 | ||
1411 | #ifndef RS6000_DEFAULT_LONG_DOUBLE_SIZE | |
1412 | #define RS6000_DEFAULT_LONG_DOUBLE_SIZE 64 | |
1413 | #endif | |
1414 | ||
5248c961 RK |
1415 | /* Override command line options. Mostly we process the processor |
1416 | type and sometimes adjust other TARGET_ options. */ | |
1417 | ||
1418 | void | |
d779d0dc | 1419 | rs6000_override_options (const char *default_cpu) |
5248c961 | 1420 | { |
c4d38ccb | 1421 | size_t i, j; |
8e3f41e7 | 1422 | struct rs6000_cpu_select *ptr; |
66188a7e | 1423 | int set_masks; |
5248c961 | 1424 | |
66188a7e | 1425 | /* Simplifications for entries below. */ |
85638c0d | 1426 | |
66188a7e GK |
1427 | enum { |
1428 | POWERPC_BASE_MASK = MASK_POWERPC | MASK_NEW_MNEMONICS, | |
1429 | POWERPC_7400_MASK = POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_ALTIVEC | |
1430 | }; | |
85638c0d | 1431 | |
66188a7e GK |
1432 | /* This table occasionally claims that a processor does not support |
1433 | a particular feature even though it does, but the feature is slower | |
1434 | than the alternative. Thus, it shouldn't be relied on as a | |
f676971a | 1435 | complete description of the processor's support. |
66188a7e GK |
1436 | |
1437 | Please keep this list in order, and don't forget to update the | |
1438 | documentation in invoke.texi when adding a new processor or | |
1439 | flag. */ | |
5248c961 RK |
1440 | static struct ptt |
1441 | { | |
8b60264b KG |
1442 | const char *const name; /* Canonical processor name. */ |
1443 | const enum processor_type processor; /* Processor type enum value. */ | |
1444 | const int target_enable; /* Target flags to enable. */ | |
8b60264b | 1445 | } const processor_target_table[] |
66188a7e | 1446 | = {{"401", PROCESSOR_PPC403, POWERPC_BASE_MASK | MASK_SOFT_FLOAT}, |
49a0b204 | 1447 | {"403", PROCESSOR_PPC403, |
66188a7e | 1448 | POWERPC_BASE_MASK | MASK_SOFT_FLOAT | MASK_STRICT_ALIGN}, |
131aeb82 | 1449 | {"405", PROCESSOR_PPC405, |
716019c0 JM |
1450 | POWERPC_BASE_MASK | MASK_SOFT_FLOAT | MASK_MULHW | MASK_DLMZB}, |
1451 | {"405fp", PROCESSOR_PPC405, | |
1452 | POWERPC_BASE_MASK | MASK_MULHW | MASK_DLMZB}, | |
131aeb82 | 1453 | {"440", PROCESSOR_PPC440, |
716019c0 JM |
1454 | POWERPC_BASE_MASK | MASK_SOFT_FLOAT | MASK_MULHW | MASK_DLMZB}, |
1455 | {"440fp", PROCESSOR_PPC440, | |
1456 | POWERPC_BASE_MASK | MASK_MULHW | MASK_DLMZB}, | |
4adf8008 PB |
1457 | {"464", PROCESSOR_PPC440, |
1458 | POWERPC_BASE_MASK | MASK_SOFT_FLOAT | MASK_MULHW | MASK_DLMZB}, | |
1459 | {"464fp", PROCESSOR_PPC440, | |
1460 | POWERPC_BASE_MASK | MASK_MULHW | MASK_DLMZB}, | |
66188a7e | 1461 | {"505", PROCESSOR_MPCCORE, POWERPC_BASE_MASK}, |
5248c961 | 1462 | {"601", PROCESSOR_PPC601, |
66188a7e GK |
1463 | MASK_POWER | POWERPC_BASE_MASK | MASK_MULTIPLE | MASK_STRING}, |
1464 | {"602", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT}, | |
1465 | {"603", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT}, | |
1466 | {"603e", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT}, | |
1467 | {"604", PROCESSOR_PPC604, POWERPC_BASE_MASK | MASK_PPC_GFXOPT}, | |
1468 | {"604e", PROCESSOR_PPC604e, POWERPC_BASE_MASK | MASK_PPC_GFXOPT}, | |
7ddb6568 AM |
1469 | {"620", PROCESSOR_PPC620, |
1470 | POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64}, | |
1471 | {"630", PROCESSOR_PPC630, | |
1472 | POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64}, | |
66188a7e GK |
1473 | {"740", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT}, |
1474 | {"7400", PROCESSOR_PPC7400, POWERPC_7400_MASK}, | |
1475 | {"7450", PROCESSOR_PPC7450, POWERPC_7400_MASK}, | |
1476 | {"750", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT}, | |
1477 | {"801", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT}, | |
1478 | {"821", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT}, | |
1479 | {"823", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT}, | |
a45bce6e | 1480 | {"8540", PROCESSOR_PPC8540, POWERPC_BASE_MASK | MASK_STRICT_ALIGN}, |
4d4cbc0e | 1481 | /* 8548 has a dummy entry for now. */ |
a45bce6e | 1482 | {"8548", PROCESSOR_PPC8540, POWERPC_BASE_MASK | MASK_STRICT_ALIGN}, |
fa41c305 EW |
1483 | {"e300c2", PROCESSOR_PPCE300C2, POWERPC_BASE_MASK | MASK_SOFT_FLOAT}, |
1484 | {"e300c3", PROCESSOR_PPCE300C3, POWERPC_BASE_MASK}, | |
edae5fe3 | 1485 | {"e500mc", PROCESSOR_PPCE500MC, POWERPC_BASE_MASK | MASK_PPC_GFXOPT}, |
66188a7e | 1486 | {"860", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT}, |
7177e720 | 1487 | {"970", PROCESSOR_POWER4, |
66188a7e | 1488 | POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64}, |
d296e02e AP |
1489 | {"cell", PROCESSOR_CELL, |
1490 | POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64}, | |
66188a7e GK |
1491 | {"common", PROCESSOR_COMMON, MASK_NEW_MNEMONICS}, |
1492 | {"ec603e", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_SOFT_FLOAT}, | |
1493 | {"G3", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT}, | |
1494 | {"G4", PROCESSOR_PPC7450, POWERPC_7400_MASK}, | |
49ffe578 | 1495 | {"G5", PROCESSOR_POWER4, |
66188a7e GK |
1496 | POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64}, |
1497 | {"power", PROCESSOR_POWER, MASK_POWER | MASK_MULTIPLE | MASK_STRING}, | |
1498 | {"power2", PROCESSOR_POWER, | |
1499 | MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING}, | |
7ddb6568 AM |
1500 | {"power3", PROCESSOR_PPC630, |
1501 | POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64}, | |
1502 | {"power4", PROCESSOR_POWER4, | |
9a8d7941 | 1503 | POWERPC_BASE_MASK | MASK_POWERPC64 | MASK_PPC_GPOPT | MASK_PPC_GFXOPT |
1bc39d2f | 1504 | | MASK_MFCRF}, |
ec507f2d | 1505 | {"power5", PROCESSOR_POWER5, |
9a8d7941 | 1506 | POWERPC_BASE_MASK | MASK_POWERPC64 | MASK_PPC_GPOPT | MASK_PPC_GFXOPT |
432218ba | 1507 | | MASK_MFCRF | MASK_POPCNTB}, |
9719f3b7 | 1508 | {"power5+", PROCESSOR_POWER5, |
9a8d7941 | 1509 | POWERPC_BASE_MASK | MASK_POWERPC64 | MASK_PPC_GPOPT | MASK_PPC_GFXOPT |
9719f3b7 | 1510 | | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND}, |
44cd321e | 1511 | {"power6", PROCESSOR_POWER6, |
0783d48d DE |
1512 | POWERPC_BASE_MASK | MASK_POWERPC64 | MASK_PPC_GPOPT | MASK_PPC_GFXOPT |
1513 | | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND | MASK_CMPB | MASK_DFP}, | |
44cd321e | 1514 | {"power6x", PROCESSOR_POWER6, |
0783d48d DE |
1515 | POWERPC_BASE_MASK | MASK_POWERPC64 | MASK_PPC_GPOPT | MASK_PPC_GFXOPT |
1516 | | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND | MASK_CMPB | MASK_DFP | |
1517 | | MASK_MFPGPR}, | |
d40c9e33 PB |
1518 | {"power7", PROCESSOR_POWER5, |
1519 | POWERPC_7400_MASK | MASK_POWERPC64 | MASK_PPC_GPOPT | MASK_MFCRF | |
1520 | | MASK_POPCNTB | MASK_FPRND | MASK_CMPB | MASK_DFP}, | |
66188a7e GK |
1521 | {"powerpc", PROCESSOR_POWERPC, POWERPC_BASE_MASK}, |
1522 | {"powerpc64", PROCESSOR_POWERPC64, | |
98c41d98 | 1523 | POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64}, |
66188a7e GK |
1524 | {"rios", PROCESSOR_RIOS1, MASK_POWER | MASK_MULTIPLE | MASK_STRING}, |
1525 | {"rios1", PROCESSOR_RIOS1, MASK_POWER | MASK_MULTIPLE | MASK_STRING}, | |
1526 | {"rios2", PROCESSOR_RIOS2, | |
1527 | MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING}, | |
1528 | {"rsc", PROCESSOR_PPC601, MASK_POWER | MASK_MULTIPLE | MASK_STRING}, | |
1529 | {"rsc1", PROCESSOR_PPC601, MASK_POWER | MASK_MULTIPLE | MASK_STRING}, | |
98c41d98 DE |
1530 | {"rs64", PROCESSOR_RS64A, |
1531 | POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64} | |
66188a7e | 1532 | }; |
5248c961 | 1533 | |
ca7558fc | 1534 | const size_t ptt_size = ARRAY_SIZE (processor_target_table); |
5248c961 | 1535 | |
66188a7e GK |
1536 | /* Some OSs don't support saving the high part of 64-bit registers on |
1537 | context switch. Other OSs don't support saving Altivec registers. | |
1538 | On those OSs, we don't touch the MASK_POWERPC64 or MASK_ALTIVEC | |
1539 | settings; if the user wants either, the user must explicitly specify | |
1540 | them and we won't interfere with the user's specification. */ | |
1541 | ||
1542 | enum { | |
1543 | POWER_MASKS = MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING, | |
db2675d3 | 1544 | POWERPC_MASKS = (POWERPC_BASE_MASK | MASK_PPC_GPOPT | MASK_STRICT_ALIGN |
66188a7e | 1545 | | MASK_PPC_GFXOPT | MASK_POWERPC64 | MASK_ALTIVEC |
716019c0 | 1546 | | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND | MASK_MULHW |
b639c3c2 | 1547 | | MASK_DLMZB | MASK_CMPB | MASK_MFPGPR | MASK_DFP) |
66188a7e | 1548 | }; |
0d1fbc8c | 1549 | |
c4ad648e | 1550 | set_masks = POWER_MASKS | POWERPC_MASKS | MASK_SOFT_FLOAT; |
66188a7e GK |
1551 | #ifdef OS_MISSING_POWERPC64 |
1552 | if (OS_MISSING_POWERPC64) | |
1553 | set_masks &= ~MASK_POWERPC64; | |
1554 | #endif | |
1555 | #ifdef OS_MISSING_ALTIVEC | |
1556 | if (OS_MISSING_ALTIVEC) | |
1557 | set_masks &= ~MASK_ALTIVEC; | |
1558 | #endif | |
1559 | ||
768875a8 AM |
1560 | /* Don't override by the processor default if given explicitly. */ |
1561 | set_masks &= ~target_flags_explicit; | |
957211c3 | 1562 | |
a4f6c312 | 1563 | /* Identify the processor type. */ |
8e3f41e7 | 1564 | rs6000_select[0].string = default_cpu; |
3cb999d8 | 1565 | rs6000_cpu = TARGET_POWERPC64 ? PROCESSOR_DEFAULT64 : PROCESSOR_DEFAULT; |
8e3f41e7 | 1566 | |
b6a1cbae | 1567 | for (i = 0; i < ARRAY_SIZE (rs6000_select); i++) |
5248c961 | 1568 | { |
8e3f41e7 MM |
1569 | ptr = &rs6000_select[i]; |
1570 | if (ptr->string != (char *)0 && ptr->string[0] != '\0') | |
5248c961 | 1571 | { |
8e3f41e7 MM |
1572 | for (j = 0; j < ptt_size; j++) |
1573 | if (! strcmp (ptr->string, processor_target_table[j].name)) | |
1574 | { | |
1575 | if (ptr->set_tune_p) | |
1576 | rs6000_cpu = processor_target_table[j].processor; | |
1577 | ||
1578 | if (ptr->set_arch_p) | |
1579 | { | |
66188a7e GK |
1580 | target_flags &= ~set_masks; |
1581 | target_flags |= (processor_target_table[j].target_enable | |
1582 | & set_masks); | |
8e3f41e7 MM |
1583 | } |
1584 | break; | |
1585 | } | |
1586 | ||
4406229e | 1587 | if (j == ptt_size) |
8e3f41e7 | 1588 | error ("bad value (%s) for %s switch", ptr->string, ptr->name); |
5248c961 RK |
1589 | } |
1590 | } | |
8a61d227 | 1591 | |
edae5fe3 DE |
1592 | if ((TARGET_E500 || rs6000_cpu == PROCESSOR_PPCE500MC) |
1593 | && !rs6000_explicit_options.isel) | |
a3170dc6 AH |
1594 | rs6000_isel = 1; |
1595 | ||
edae5fe3 DE |
1596 | if (rs6000_cpu == PROCESSOR_PPCE300C2 || rs6000_cpu == PROCESSOR_PPCE300C3 |
1597 | || rs6000_cpu == PROCESSOR_PPCE500MC) | |
fa41c305 EW |
1598 | { |
1599 | if (TARGET_ALTIVEC) | |
1600 | error ("AltiVec not supported in this target"); | |
1601 | if (TARGET_SPE) | |
1602 | error ("Spe not supported in this target"); | |
1603 | } | |
1604 | ||
25696a75 | 1605 | /* Disable Cell microcode if we are optimizing for the Cell |
c921bad8 AP |
1606 | and not optimizing for size. */ |
1607 | if (rs6000_gen_cell_microcode == -1) | |
1608 | rs6000_gen_cell_microcode = !(rs6000_cpu == PROCESSOR_CELL | |
1609 | && !optimize_size); | |
1610 | ||
dff9f1b6 | 1611 | /* If we are optimizing big endian systems for space, use the load/store |
c921bad8 AP |
1612 | multiple and string instructions unless we are not generating |
1613 | Cell microcode. */ | |
1614 | if (BYTES_BIG_ENDIAN && optimize_size && !rs6000_gen_cell_microcode) | |
957211c3 | 1615 | target_flags |= ~target_flags_explicit & (MASK_MULTIPLE | MASK_STRING); |
938937d8 | 1616 | |
a4f6c312 SS |
1617 | /* Don't allow -mmultiple or -mstring on little endian systems |
1618 | unless the cpu is a 750, because the hardware doesn't support the | |
1619 | instructions used in little endian mode, and causes an alignment | |
1620 | trap. The 750 does not cause an alignment trap (except when the | |
1621 | target is unaligned). */ | |
bef84347 | 1622 | |
b21fb038 | 1623 | if (!BYTES_BIG_ENDIAN && rs6000_cpu != PROCESSOR_PPC750) |
7e69e155 MM |
1624 | { |
1625 | if (TARGET_MULTIPLE) | |
1626 | { | |
1627 | target_flags &= ~MASK_MULTIPLE; | |
b21fb038 | 1628 | if ((target_flags_explicit & MASK_MULTIPLE) != 0) |
d4ee4d25 | 1629 | warning (0, "-mmultiple is not supported on little endian systems"); |
7e69e155 MM |
1630 | } |
1631 | ||
1632 | if (TARGET_STRING) | |
1633 | { | |
1634 | target_flags &= ~MASK_STRING; | |
b21fb038 | 1635 | if ((target_flags_explicit & MASK_STRING) != 0) |
d4ee4d25 | 1636 | warning (0, "-mstring is not supported on little endian systems"); |
7e69e155 MM |
1637 | } |
1638 | } | |
3933e0e1 | 1639 | |
38c1f2d7 MM |
1640 | /* Set debug flags */ |
1641 | if (rs6000_debug_name) | |
1642 | { | |
bfc79d3b | 1643 | if (! strcmp (rs6000_debug_name, "all")) |
38c1f2d7 | 1644 | rs6000_debug_stack = rs6000_debug_arg = 1; |
bfc79d3b | 1645 | else if (! strcmp (rs6000_debug_name, "stack")) |
38c1f2d7 | 1646 | rs6000_debug_stack = 1; |
bfc79d3b | 1647 | else if (! strcmp (rs6000_debug_name, "arg")) |
38c1f2d7 MM |
1648 | rs6000_debug_arg = 1; |
1649 | else | |
c725bd79 | 1650 | error ("unknown -mdebug-%s switch", rs6000_debug_name); |
38c1f2d7 MM |
1651 | } |
1652 | ||
57ac7be9 AM |
1653 | if (rs6000_traceback_name) |
1654 | { | |
1655 | if (! strncmp (rs6000_traceback_name, "full", 4)) | |
1656 | rs6000_traceback = traceback_full; | |
1657 | else if (! strncmp (rs6000_traceback_name, "part", 4)) | |
1658 | rs6000_traceback = traceback_part; | |
1659 | else if (! strncmp (rs6000_traceback_name, "no", 2)) | |
1660 | rs6000_traceback = traceback_none; | |
1661 | else | |
9e637a26 | 1662 | error ("unknown -mtraceback arg %qs; expecting %<full%>, %<partial%> or %<none%>", |
57ac7be9 AM |
1663 | rs6000_traceback_name); |
1664 | } | |
1665 | ||
78f5898b AH |
1666 | if (!rs6000_explicit_options.long_double) |
1667 | rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE; | |
6fa3f289 | 1668 | |
602ea4d3 | 1669 | #ifndef POWERPC_LINUX |
d3603e8c | 1670 | if (!rs6000_explicit_options.ieee) |
602ea4d3 JJ |
1671 | rs6000_ieeequad = 1; |
1672 | #endif | |
1673 | ||
0db747be DE |
1674 | /* Enable Altivec ABI for AIX -maltivec. */ |
1675 | if (TARGET_XCOFF && TARGET_ALTIVEC) | |
1676 | rs6000_altivec_abi = 1; | |
1677 | ||
a2db2771 JJ |
1678 | /* The AltiVec ABI is the default for PowerPC-64 GNU/Linux. For |
1679 | PowerPC-32 GNU/Linux, -maltivec implies the AltiVec ABI. It can | |
1680 | be explicitly overridden in either case. */ | |
1681 | if (TARGET_ELF) | |
6d0ef01e | 1682 | { |
a2db2771 JJ |
1683 | if (!rs6000_explicit_options.altivec_abi |
1684 | && (TARGET_64BIT || TARGET_ALTIVEC)) | |
1685 | rs6000_altivec_abi = 1; | |
1686 | ||
1687 | /* Enable VRSAVE for AltiVec ABI, unless explicitly overridden. */ | |
1688 | if (!rs6000_explicit_options.vrsave) | |
1689 | TARGET_ALTIVEC_VRSAVE = rs6000_altivec_abi; | |
6d0ef01e HP |
1690 | } |
1691 | ||
594a51fe SS |
1692 | /* Set the Darwin64 ABI as default for 64-bit Darwin. */ |
1693 | if (DEFAULT_ABI == ABI_DARWIN && TARGET_64BIT) | |
1694 | { | |
1695 | rs6000_darwin64_abi = 1; | |
9c7956fd | 1696 | #if TARGET_MACHO |
6ac49599 | 1697 | darwin_one_byte_bool = 1; |
9c7956fd | 1698 | #endif |
d9168963 SS |
1699 | /* Default to natural alignment, for better performance. */ |
1700 | rs6000_alignment_flags = MASK_ALIGN_NATURAL; | |
594a51fe SS |
1701 | } |
1702 | ||
194c524a DE |
1703 | /* Place FP constants in the constant pool instead of TOC |
1704 | if section anchors enabled. */ | |
1705 | if (flag_section_anchors) | |
1706 | TARGET_NO_FP_IN_TOC = 1; | |
1707 | ||
c4501e62 JJ |
1708 | /* Handle -mtls-size option. */ |
1709 | rs6000_parse_tls_size_option (); | |
1710 | ||
a7ae18e2 AH |
1711 | #ifdef SUBTARGET_OVERRIDE_OPTIONS |
1712 | SUBTARGET_OVERRIDE_OPTIONS; | |
1713 | #endif | |
1714 | #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS | |
1715 | SUBSUBTARGET_OVERRIDE_OPTIONS; | |
1716 | #endif | |
4d4cbc0e AH |
1717 | #ifdef SUB3TARGET_OVERRIDE_OPTIONS |
1718 | SUB3TARGET_OVERRIDE_OPTIONS; | |
1719 | #endif | |
a7ae18e2 | 1720 | |
edae5fe3 | 1721 | if (TARGET_E500 || rs6000_cpu == PROCESSOR_PPCE500MC) |
5da702b1 | 1722 | { |
edae5fe3 | 1723 | /* The e500 and e500mc do not have string instructions, and we set |
5da702b1 AH |
1724 | MASK_STRING above when optimizing for size. */ |
1725 | if ((target_flags & MASK_STRING) != 0) | |
1726 | target_flags = target_flags & ~MASK_STRING; | |
1727 | } | |
1728 | else if (rs6000_select[1].string != NULL) | |
1729 | { | |
1730 | /* For the powerpc-eabispe configuration, we set all these by | |
1731 | default, so let's unset them if we manually set another | |
1732 | CPU that is not the E500. */ | |
a2db2771 | 1733 | if (!rs6000_explicit_options.spe_abi) |
5da702b1 | 1734 | rs6000_spe_abi = 0; |
78f5898b | 1735 | if (!rs6000_explicit_options.spe) |
5da702b1 | 1736 | rs6000_spe = 0; |
78f5898b | 1737 | if (!rs6000_explicit_options.float_gprs) |
5da702b1 | 1738 | rs6000_float_gprs = 0; |
78f5898b | 1739 | if (!rs6000_explicit_options.isel) |
5da702b1 AH |
1740 | rs6000_isel = 0; |
1741 | } | |
b5044283 | 1742 | |
eca0d5e8 JM |
1743 | /* Detect invalid option combinations with E500. */ |
1744 | CHECK_E500_OPTIONS; | |
1745 | ||
ec507f2d | 1746 | rs6000_always_hint = (rs6000_cpu != PROCESSOR_POWER4 |
44cd321e | 1747 | && rs6000_cpu != PROCESSOR_POWER5 |
d296e02e AP |
1748 | && rs6000_cpu != PROCESSOR_POWER6 |
1749 | && rs6000_cpu != PROCESSOR_CELL); | |
ec507f2d DE |
1750 | rs6000_sched_groups = (rs6000_cpu == PROCESSOR_POWER4 |
1751 | || rs6000_cpu == PROCESSOR_POWER5); | |
44cd321e PS |
1752 | rs6000_align_branch_targets = (rs6000_cpu == PROCESSOR_POWER4 |
1753 | || rs6000_cpu == PROCESSOR_POWER5 | |
1754 | || rs6000_cpu == PROCESSOR_POWER6); | |
ec507f2d | 1755 | |
ec507f2d DE |
1756 | rs6000_sched_restricted_insns_priority |
1757 | = (rs6000_sched_groups ? 1 : 0); | |
79ae11c4 | 1758 | |
569fa502 | 1759 | /* Handle -msched-costly-dep option. */ |
ec507f2d DE |
1760 | rs6000_sched_costly_dep |
1761 | = (rs6000_sched_groups ? store_to_load_dep_costly : no_dep_costly); | |
432218ba | 1762 | |
569fa502 DN |
1763 | if (rs6000_sched_costly_dep_str) |
1764 | { | |
f676971a | 1765 | if (! strcmp (rs6000_sched_costly_dep_str, "no")) |
c4ad648e | 1766 | rs6000_sched_costly_dep = no_dep_costly; |
569fa502 | 1767 | else if (! strcmp (rs6000_sched_costly_dep_str, "all")) |
c4ad648e | 1768 | rs6000_sched_costly_dep = all_deps_costly; |
569fa502 | 1769 | else if (! strcmp (rs6000_sched_costly_dep_str, "true_store_to_load")) |
c4ad648e | 1770 | rs6000_sched_costly_dep = true_store_to_load_dep_costly; |
569fa502 | 1771 | else if (! strcmp (rs6000_sched_costly_dep_str, "store_to_load")) |
c4ad648e | 1772 | rs6000_sched_costly_dep = store_to_load_dep_costly; |
f676971a | 1773 | else |
c4ad648e | 1774 | rs6000_sched_costly_dep = atoi (rs6000_sched_costly_dep_str); |
cbe26ab8 DN |
1775 | } |
1776 | ||
1777 | /* Handle -minsert-sched-nops option. */ | |
ec507f2d DE |
1778 | rs6000_sched_insert_nops |
1779 | = (rs6000_sched_groups ? sched_finish_regroup_exact : sched_finish_none); | |
432218ba | 1780 | |
cbe26ab8 DN |
1781 | if (rs6000_sched_insert_nops_str) |
1782 | { | |
1783 | if (! strcmp (rs6000_sched_insert_nops_str, "no")) | |
c4ad648e | 1784 | rs6000_sched_insert_nops = sched_finish_none; |
cbe26ab8 | 1785 | else if (! strcmp (rs6000_sched_insert_nops_str, "pad")) |
c4ad648e | 1786 | rs6000_sched_insert_nops = sched_finish_pad_groups; |
cbe26ab8 | 1787 | else if (! strcmp (rs6000_sched_insert_nops_str, "regroup_exact")) |
c4ad648e | 1788 | rs6000_sched_insert_nops = sched_finish_regroup_exact; |
cbe26ab8 | 1789 | else |
c4ad648e | 1790 | rs6000_sched_insert_nops = atoi (rs6000_sched_insert_nops_str); |
569fa502 DN |
1791 | } |
1792 | ||
c81bebd7 | 1793 | #ifdef TARGET_REGNAMES |
a4f6c312 SS |
1794 | /* If the user desires alternate register names, copy in the |
1795 | alternate names now. */ | |
c81bebd7 | 1796 | if (TARGET_REGNAMES) |
4e135bdd | 1797 | memcpy (rs6000_reg_names, alt_reg_names, sizeof (rs6000_reg_names)); |
c81bebd7 MM |
1798 | #endif |
1799 | ||
df01da37 | 1800 | /* Set aix_struct_return last, after the ABI is determined. |
6fa3f289 ZW |
1801 | If -maix-struct-return or -msvr4-struct-return was explicitly |
1802 | used, don't override with the ABI default. */ | |
df01da37 DE |
1803 | if (!rs6000_explicit_options.aix_struct_ret) |
1804 | aix_struct_return = (DEFAULT_ABI != ABI_V4 || DRAFT_V4_STRUCT_RET); | |
6fa3f289 | 1805 | |
602ea4d3 | 1806 | if (TARGET_LONG_DOUBLE_128 && !TARGET_IEEEQUAD) |
70a01792 | 1807 | REAL_MODE_FORMAT (TFmode) = &ibm_extended_format; |
fcce224d | 1808 | |
f676971a | 1809 | if (TARGET_TOC) |
9ebbca7d | 1810 | ASM_GENERATE_INTERNAL_LABEL (toc_label_name, "LCTOC", 1); |
71f123ca | 1811 | |
301d03af RS |
1812 | /* We can only guarantee the availability of DI pseudo-ops when |
1813 | assembling for 64-bit targets. */ | |
ae6c1efd | 1814 | if (!TARGET_64BIT) |
301d03af RS |
1815 | { |
1816 | targetm.asm_out.aligned_op.di = NULL; | |
1817 | targetm.asm_out.unaligned_op.di = NULL; | |
1818 | } | |
1819 | ||
1494c534 DE |
1820 | /* Set branch target alignment, if not optimizing for size. */ |
1821 | if (!optimize_size) | |
1822 | { | |
d296e02e AP |
1823 | /* Cell wants to be aligned 8byte for dual issue. */ |
1824 | if (rs6000_cpu == PROCESSOR_CELL) | |
1825 | { | |
1826 | if (align_functions <= 0) | |
1827 | align_functions = 8; | |
1828 | if (align_jumps <= 0) | |
1829 | align_jumps = 8; | |
1830 | if (align_loops <= 0) | |
1831 | align_loops = 8; | |
1832 | } | |
44cd321e | 1833 | if (rs6000_align_branch_targets) |
1494c534 DE |
1834 | { |
1835 | if (align_functions <= 0) | |
1836 | align_functions = 16; | |
1837 | if (align_jumps <= 0) | |
1838 | align_jumps = 16; | |
1839 | if (align_loops <= 0) | |
1840 | align_loops = 16; | |
1841 | } | |
1842 | if (align_jumps_max_skip <= 0) | |
1843 | align_jumps_max_skip = 15; | |
1844 | if (align_loops_max_skip <= 0) | |
1845 | align_loops_max_skip = 15; | |
1846 | } | |
2792d578 | 1847 | |
71f123ca FS |
1848 | /* Arrange to save and restore machine status around nested functions. */ |
1849 | init_machine_status = rs6000_init_machine_status; | |
42ba5130 RH |
1850 | |
1851 | /* We should always be splitting complex arguments, but we can't break | |
1852 | Linux and Darwin ABIs at the moment. For now, only AIX is fixed. */ | |
18f63bfa | 1853 | if (DEFAULT_ABI != ABI_AIX) |
42ba5130 | 1854 | targetm.calls.split_complex_arg = NULL; |
8b897cfa RS |
1855 | |
1856 | /* Initialize rs6000_cost with the appropriate target costs. */ | |
1857 | if (optimize_size) | |
1858 | rs6000_cost = TARGET_POWERPC64 ? &size64_cost : &size32_cost; | |
1859 | else | |
1860 | switch (rs6000_cpu) | |
1861 | { | |
1862 | case PROCESSOR_RIOS1: | |
1863 | rs6000_cost = &rios1_cost; | |
1864 | break; | |
1865 | ||
1866 | case PROCESSOR_RIOS2: | |
1867 | rs6000_cost = &rios2_cost; | |
1868 | break; | |
1869 | ||
1870 | case PROCESSOR_RS64A: | |
1871 | rs6000_cost = &rs64a_cost; | |
1872 | break; | |
1873 | ||
1874 | case PROCESSOR_MPCCORE: | |
1875 | rs6000_cost = &mpccore_cost; | |
1876 | break; | |
1877 | ||
1878 | case PROCESSOR_PPC403: | |
1879 | rs6000_cost = &ppc403_cost; | |
1880 | break; | |
1881 | ||
1882 | case PROCESSOR_PPC405: | |
1883 | rs6000_cost = &ppc405_cost; | |
1884 | break; | |
1885 | ||
1886 | case PROCESSOR_PPC440: | |
1887 | rs6000_cost = &ppc440_cost; | |
1888 | break; | |
1889 | ||
1890 | case PROCESSOR_PPC601: | |
1891 | rs6000_cost = &ppc601_cost; | |
1892 | break; | |
1893 | ||
1894 | case PROCESSOR_PPC603: | |
1895 | rs6000_cost = &ppc603_cost; | |
1896 | break; | |
1897 | ||
1898 | case PROCESSOR_PPC604: | |
1899 | rs6000_cost = &ppc604_cost; | |
1900 | break; | |
1901 | ||
1902 | case PROCESSOR_PPC604e: | |
1903 | rs6000_cost = &ppc604e_cost; | |
1904 | break; | |
1905 | ||
1906 | case PROCESSOR_PPC620: | |
8b897cfa RS |
1907 | rs6000_cost = &ppc620_cost; |
1908 | break; | |
1909 | ||
f0517163 RS |
1910 | case PROCESSOR_PPC630: |
1911 | rs6000_cost = &ppc630_cost; | |
1912 | break; | |
1913 | ||
982afe02 | 1914 | case PROCESSOR_CELL: |
d296e02e AP |
1915 | rs6000_cost = &ppccell_cost; |
1916 | break; | |
1917 | ||
8b897cfa RS |
1918 | case PROCESSOR_PPC750: |
1919 | case PROCESSOR_PPC7400: | |
1920 | rs6000_cost = &ppc750_cost; | |
1921 | break; | |
1922 | ||
1923 | case PROCESSOR_PPC7450: | |
1924 | rs6000_cost = &ppc7450_cost; | |
1925 | break; | |
1926 | ||
1927 | case PROCESSOR_PPC8540: | |
1928 | rs6000_cost = &ppc8540_cost; | |
1929 | break; | |
1930 | ||
fa41c305 EW |
1931 | case PROCESSOR_PPCE300C2: |
1932 | case PROCESSOR_PPCE300C3: | |
1933 | rs6000_cost = &ppce300c2c3_cost; | |
1934 | break; | |
1935 | ||
edae5fe3 DE |
1936 | case PROCESSOR_PPCE500MC: |
1937 | rs6000_cost = &ppce500mc_cost; | |
1938 | break; | |
1939 | ||
8b897cfa RS |
1940 | case PROCESSOR_POWER4: |
1941 | case PROCESSOR_POWER5: | |
1942 | rs6000_cost = &power4_cost; | |
1943 | break; | |
1944 | ||
44cd321e PS |
1945 | case PROCESSOR_POWER6: |
1946 | rs6000_cost = &power6_cost; | |
1947 | break; | |
1948 | ||
8b897cfa | 1949 | default: |
37409796 | 1950 | gcc_unreachable (); |
8b897cfa | 1951 | } |
0b11da67 DE |
1952 | |
1953 | if (!PARAM_SET_P (PARAM_SIMULTANEOUS_PREFETCHES)) | |
1954 | set_param_value ("simultaneous-prefetches", | |
1955 | rs6000_cost->simultaneous_prefetches); | |
1956 | if (!PARAM_SET_P (PARAM_L1_CACHE_SIZE)) | |
5f732aba | 1957 | set_param_value ("l1-cache-size", rs6000_cost->l1_cache_size); |
0b11da67 DE |
1958 | if (!PARAM_SET_P (PARAM_L1_CACHE_LINE_SIZE)) |
1959 | set_param_value ("l1-cache-line-size", rs6000_cost->cache_line_size); | |
5f732aba DE |
1960 | if (!PARAM_SET_P (PARAM_L2_CACHE_SIZE)) |
1961 | set_param_value ("l2-cache-size", rs6000_cost->l2_cache_size); | |
d7bd8aeb JJ |
1962 | |
1963 | /* If using typedef char *va_list, signal that __builtin_va_start (&ap, 0) | |
1964 | can be optimized to ap = __builtin_next_arg (0). */ | |
1965 | if (DEFAULT_ABI != ABI_V4) | |
1966 | targetm.expand_builtin_va_start = NULL; | |
696e45ba ME |
1967 | |
1968 | /* Set up single/double float flags. | |
1969 | If TARGET_HARD_FLOAT is set, but neither single or double is set, | |
1970 | then set both flags. */ | |
1971 | if (TARGET_HARD_FLOAT && TARGET_FPRS | |
1972 | && rs6000_single_float == 0 && rs6000_double_float == 0) | |
1973 | rs6000_single_float = rs6000_double_float = 1; | |
1974 | ||
1975 | /* Reset single and double FP flags if target is E500. */ | |
1976 | if (TARGET_E500) | |
1977 | { | |
1978 | rs6000_single_float = rs6000_double_float = 0; | |
1979 | if (TARGET_E500_SINGLE) | |
1980 | rs6000_single_float = 1; | |
1981 | if (TARGET_E500_DOUBLE) | |
1982 | rs6000_single_float = rs6000_double_float = 1; | |
1983 | } | |
1984 | ||
001b9eb6 PH |
1985 | /* If not explicitly specified via option, decide whether to generate indexed |
1986 | load/store instructions. */ | |
1987 | if (TARGET_AVOID_XFORM == -1) | |
1988 | /* Avoid indexed addressing when targeting Power6 in order to avoid | |
1989 | the DERAT mispredict penalty. */ | |
1990 | TARGET_AVOID_XFORM = (rs6000_cpu == PROCESSOR_POWER6 && TARGET_CMPB); | |
1991 | ||
696e45ba | 1992 | rs6000_init_hard_regno_mode_ok (); |
5248c961 | 1993 | } |
5accd822 | 1994 | |
7ccf35ed DN |
1995 | /* Implement targetm.vectorize.builtin_mask_for_load. */ |
1996 | static tree | |
1997 | rs6000_builtin_mask_for_load (void) | |
1998 | { | |
1999 | if (TARGET_ALTIVEC) | |
2000 | return altivec_builtin_mask_for_load; | |
2001 | else | |
2002 | return 0; | |
2003 | } | |
2004 | ||
7910ae0c DN |
2005 | /* Implement targetm.vectorize.builtin_conversion. |
2006 | Returns a decl of a function that implements conversion of an integer vector | |
2007 | into a floating-point vector, or vice-versa. TYPE is the type of the integer | |
2008 | side of the conversion. | |
2009 | Return NULL_TREE if it is not available. */ | |
f57d17f1 TM |
2010 | static tree |
2011 | rs6000_builtin_conversion (enum tree_code code, tree type) | |
2012 | { | |
2013 | if (!TARGET_ALTIVEC) | |
2014 | return NULL_TREE; | |
982afe02 | 2015 | |
f57d17f1 TM |
2016 | switch (code) |
2017 | { | |
7910ae0c DN |
2018 | case FIX_TRUNC_EXPR: |
2019 | switch (TYPE_MODE (type)) | |
2020 | { | |
2021 | case V4SImode: | |
2022 | return TYPE_UNSIGNED (type) | |
2023 | ? rs6000_builtin_decls[ALTIVEC_BUILTIN_VCTUXS] | |
2024 | : rs6000_builtin_decls[ALTIVEC_BUILTIN_VCTSXS]; | |
2025 | default: | |
2026 | return NULL_TREE; | |
2027 | } | |
2028 | ||
f57d17f1 TM |
2029 | case FLOAT_EXPR: |
2030 | switch (TYPE_MODE (type)) | |
2031 | { | |
2032 | case V4SImode: | |
7910ae0c DN |
2033 | return TYPE_UNSIGNED (type) |
2034 | ? rs6000_builtin_decls[ALTIVEC_BUILTIN_VCFUX] | |
2035 | : rs6000_builtin_decls[ALTIVEC_BUILTIN_VCFSX]; | |
f57d17f1 TM |
2036 | default: |
2037 | return NULL_TREE; | |
2038 | } | |
7910ae0c | 2039 | |
f57d17f1 TM |
2040 | default: |
2041 | return NULL_TREE; | |
2042 | } | |
2043 | } | |
2044 | ||
89d67cca DN |
2045 | /* Implement targetm.vectorize.builtin_mul_widen_even. */ |
2046 | static tree | |
2047 | rs6000_builtin_mul_widen_even (tree type) | |
2048 | { | |
2049 | if (!TARGET_ALTIVEC) | |
2050 | return NULL_TREE; | |
2051 | ||
2052 | switch (TYPE_MODE (type)) | |
2053 | { | |
2054 | case V8HImode: | |
7910ae0c DN |
2055 | return TYPE_UNSIGNED (type) |
2056 | ? rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULEUH] | |
2057 | : rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULESH]; | |
89d67cca DN |
2058 | |
2059 | case V16QImode: | |
7910ae0c DN |
2060 | return TYPE_UNSIGNED (type) |
2061 | ? rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULEUB] | |
2062 | : rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULESB]; | |
89d67cca DN |
2063 | default: |
2064 | return NULL_TREE; | |
2065 | } | |
2066 | } | |
2067 | ||
2068 | /* Implement targetm.vectorize.builtin_mul_widen_odd. */ | |
2069 | static tree | |
2070 | rs6000_builtin_mul_widen_odd (tree type) | |
2071 | { | |
2072 | if (!TARGET_ALTIVEC) | |
2073 | return NULL_TREE; | |
2074 | ||
2075 | switch (TYPE_MODE (type)) | |
2076 | { | |
2077 | case V8HImode: | |
7910ae0c DN |
2078 | return TYPE_UNSIGNED (type) |
2079 | ? rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULOUH] | |
2080 | : rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULOSH]; | |
89d67cca DN |
2081 | |
2082 | case V16QImode: | |
7910ae0c DN |
2083 | return TYPE_UNSIGNED (type) |
2084 | ? rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULOUB] | |
2085 | : rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULOSB]; | |
89d67cca DN |
2086 | default: |
2087 | return NULL_TREE; | |
2088 | } | |
2089 | } | |
2090 | ||
5b900a4c DN |
2091 | |
2092 | /* Return true iff, data reference of TYPE can reach vector alignment (16) | |
2093 | after applying N number of iterations. This routine does not determine | |
2094 | how may iterations are required to reach desired alignment. */ | |
2095 | ||
2096 | static bool | |
3101faab | 2097 | rs6000_vector_alignment_reachable (const_tree type ATTRIBUTE_UNUSED, bool is_packed) |
5b900a4c DN |
2098 | { |
2099 | if (is_packed) | |
2100 | return false; | |
2101 | ||
2102 | if (TARGET_32BIT) | |
2103 | { | |
2104 | if (rs6000_alignment_flags == MASK_ALIGN_NATURAL) | |
2105 | return true; | |
2106 | ||
2107 | if (rs6000_alignment_flags == MASK_ALIGN_POWER) | |
2108 | return true; | |
2109 | ||
2110 | return false; | |
2111 | } | |
2112 | else | |
2113 | { | |
2114 | if (TARGET_MACHO) | |
2115 | return false; | |
2116 | ||
2117 | /* Assuming that all other types are naturally aligned. CHECKME! */ | |
2118 | return true; | |
2119 | } | |
2120 | } | |
2121 | ||
0fca40f5 IR |
2122 | /* Implement targetm.vectorize.builtin_vec_perm. */ |
2123 | tree | |
2124 | rs6000_builtin_vec_perm (tree type, tree *mask_element_type) | |
2125 | { | |
2126 | tree d; | |
2127 | ||
2128 | *mask_element_type = unsigned_char_type_node; | |
2129 | ||
2130 | switch (TYPE_MODE (type)) | |
2131 | { | |
2132 | case V16QImode: | |
2133 | d = rs6000_builtin_decls[ALTIVEC_BUILTIN_VPERM_16QI]; | |
2134 | break; | |
2135 | ||
2136 | case V8HImode: | |
2137 | d = rs6000_builtin_decls[ALTIVEC_BUILTIN_VPERM_8HI]; | |
2138 | break; | |
2139 | ||
2140 | case V4SImode: | |
2141 | d = rs6000_builtin_decls[ALTIVEC_BUILTIN_VPERM_4SI]; | |
2142 | break; | |
2143 | ||
2144 | case V4SFmode: | |
2145 | d = rs6000_builtin_decls[ALTIVEC_BUILTIN_VPERM_4SF]; | |
2146 | break; | |
2147 | ||
2148 | default: | |
2149 | return NULL_TREE; | |
2150 | } | |
2151 | ||
2152 | gcc_assert (d); | |
2153 | return d; | |
2154 | } | |
2155 | ||
5da702b1 AH |
2156 | /* Handle generic options of the form -mfoo=yes/no. |
2157 | NAME is the option name. | |
2158 | VALUE is the option value. | |
2159 | FLAG is the pointer to the flag where to store a 1 or 0, depending on | |
2160 | whether the option value is 'yes' or 'no' respectively. */ | |
993f19a8 | 2161 | static void |
5da702b1 | 2162 | rs6000_parse_yes_no_option (const char *name, const char *value, int *flag) |
993f19a8 | 2163 | { |
5da702b1 | 2164 | if (value == 0) |
993f19a8 | 2165 | return; |
5da702b1 AH |
2166 | else if (!strcmp (value, "yes")) |
2167 | *flag = 1; | |
2168 | else if (!strcmp (value, "no")) | |
2169 | *flag = 0; | |
08b57fb3 | 2170 | else |
5da702b1 | 2171 | error ("unknown -m%s= option specified: '%s'", name, value); |
08b57fb3 AH |
2172 | } |
2173 | ||
c4501e62 JJ |
2174 | /* Validate and record the size specified with the -mtls-size option. */ |
2175 | ||
2176 | static void | |
863d938c | 2177 | rs6000_parse_tls_size_option (void) |
c4501e62 JJ |
2178 | { |
2179 | if (rs6000_tls_size_string == 0) | |
2180 | return; | |
2181 | else if (strcmp (rs6000_tls_size_string, "16") == 0) | |
2182 | rs6000_tls_size = 16; | |
2183 | else if (strcmp (rs6000_tls_size_string, "32") == 0) | |
2184 | rs6000_tls_size = 32; | |
2185 | else if (strcmp (rs6000_tls_size_string, "64") == 0) | |
2186 | rs6000_tls_size = 64; | |
2187 | else | |
9e637a26 | 2188 | error ("bad value %qs for -mtls-size switch", rs6000_tls_size_string); |
c4501e62 JJ |
2189 | } |
2190 | ||
5accd822 | 2191 | void |
a2369ed3 | 2192 | optimization_options (int level ATTRIBUTE_UNUSED, int size ATTRIBUTE_UNUSED) |
5accd822 | 2193 | { |
2e3f0db6 DJ |
2194 | if (DEFAULT_ABI == ABI_DARWIN) |
2195 | /* The Darwin libraries never set errno, so we might as well | |
2196 | avoid calling them when that's the only reason we would. */ | |
2197 | flag_errno_math = 0; | |
59d6560b DE |
2198 | |
2199 | /* Double growth factor to counter reduced min jump length. */ | |
2200 | set_param_value ("max-grow-copy-bb-insns", 16); | |
194c524a DE |
2201 | |
2202 | /* Enable section anchors by default. | |
2203 | Skip section anchors for Objective C and Objective C++ | |
2f3b0d4a ST |
2204 | until front-ends fixed. */ |
2205 | if (!TARGET_MACHO && lang_hooks.name[4] != 'O') | |
d6cc6ec9 | 2206 | flag_section_anchors = 2; |
5accd822 | 2207 | } |
78f5898b | 2208 | |
0bb7b92e ME |
2209 | static enum fpu_type_t |
2210 | rs6000_parse_fpu_option (const char *option) | |
2211 | { | |
2212 | if (!strcmp("none", option)) return FPU_NONE; | |
2213 | if (!strcmp("sp_lite", option)) return FPU_SF_LITE; | |
2214 | if (!strcmp("dp_lite", option)) return FPU_DF_LITE; | |
2215 | if (!strcmp("sp_full", option)) return FPU_SF_FULL; | |
2216 | if (!strcmp("dp_full", option)) return FPU_DF_FULL; | |
2217 | error("unknown value %s for -mfpu", option); | |
2218 | return FPU_NONE; | |
2219 | } | |
2220 | ||
78f5898b AH |
2221 | /* Implement TARGET_HANDLE_OPTION. */ |
2222 | ||
2223 | static bool | |
2224 | rs6000_handle_option (size_t code, const char *arg, int value) | |
2225 | { | |
0bb7b92e ME |
2226 | enum fpu_type_t fpu_type = FPU_NONE; |
2227 | ||
78f5898b AH |
2228 | switch (code) |
2229 | { | |
2230 | case OPT_mno_power: | |
2231 | target_flags &= ~(MASK_POWER | MASK_POWER2 | |
2232 | | MASK_MULTIPLE | MASK_STRING); | |
c2dba4ab AH |
2233 | target_flags_explicit |= (MASK_POWER | MASK_POWER2 |
2234 | | MASK_MULTIPLE | MASK_STRING); | |
78f5898b AH |
2235 | break; |
2236 | case OPT_mno_powerpc: | |
2237 | target_flags &= ~(MASK_POWERPC | MASK_PPC_GPOPT | |
2238 | | MASK_PPC_GFXOPT | MASK_POWERPC64); | |
c2dba4ab AH |
2239 | target_flags_explicit |= (MASK_POWERPC | MASK_PPC_GPOPT |
2240 | | MASK_PPC_GFXOPT | MASK_POWERPC64); | |
78f5898b AH |
2241 | break; |
2242 | case OPT_mfull_toc: | |
d2894ab5 DE |
2243 | target_flags &= ~MASK_MINIMAL_TOC; |
2244 | TARGET_NO_FP_IN_TOC = 0; | |
2245 | TARGET_NO_SUM_IN_TOC = 0; | |
2246 | target_flags_explicit |= MASK_MINIMAL_TOC; | |
78f5898b AH |
2247 | #ifdef TARGET_USES_SYSV4_OPT |
2248 | /* Note, V.4 no longer uses a normal TOC, so make -mfull-toc, be | |
2249 | just the same as -mminimal-toc. */ | |
2250 | target_flags |= MASK_MINIMAL_TOC; | |
c2dba4ab | 2251 | target_flags_explicit |= MASK_MINIMAL_TOC; |
78f5898b AH |
2252 | #endif |
2253 | break; | |
2254 | ||
2255 | #ifdef TARGET_USES_SYSV4_OPT | |
2256 | case OPT_mtoc: | |
2257 | /* Make -mtoc behave like -mminimal-toc. */ | |
2258 | target_flags |= MASK_MINIMAL_TOC; | |
c2dba4ab | 2259 | target_flags_explicit |= MASK_MINIMAL_TOC; |
78f5898b AH |
2260 | break; |
2261 | #endif | |
2262 | ||
2263 | #ifdef TARGET_USES_AIX64_OPT | |
2264 | case OPT_maix64: | |
2265 | #else | |
2266 | case OPT_m64: | |
2267 | #endif | |
2c9c9afd AM |
2268 | target_flags |= MASK_POWERPC64 | MASK_POWERPC; |
2269 | target_flags |= ~target_flags_explicit & MASK_PPC_GFXOPT; | |
2270 | target_flags_explicit |= MASK_POWERPC64 | MASK_POWERPC; | |
78f5898b AH |
2271 | break; |
2272 | ||
2273 | #ifdef TARGET_USES_AIX64_OPT | |
2274 | case OPT_maix32: | |
2275 | #else | |
2276 | case OPT_m32: | |
2277 | #endif | |
2278 | target_flags &= ~MASK_POWERPC64; | |
c2dba4ab | 2279 | target_flags_explicit |= MASK_POWERPC64; |
78f5898b AH |
2280 | break; |
2281 | ||
2282 | case OPT_minsert_sched_nops_: | |
2283 | rs6000_sched_insert_nops_str = arg; | |
2284 | break; | |
2285 | ||
2286 | case OPT_mminimal_toc: | |
2287 | if (value == 1) | |
2288 | { | |
d2894ab5 DE |
2289 | TARGET_NO_FP_IN_TOC = 0; |
2290 | TARGET_NO_SUM_IN_TOC = 0; | |
78f5898b AH |
2291 | } |
2292 | break; | |
2293 | ||
2294 | case OPT_mpower: | |
2295 | if (value == 1) | |
c2dba4ab AH |
2296 | { |
2297 | target_flags |= (MASK_MULTIPLE | MASK_STRING); | |
2298 | target_flags_explicit |= (MASK_MULTIPLE | MASK_STRING); | |
2299 | } | |
78f5898b AH |
2300 | break; |
2301 | ||
2302 | case OPT_mpower2: | |
2303 | if (value == 1) | |
c2dba4ab AH |
2304 | { |
2305 | target_flags |= (MASK_POWER | MASK_MULTIPLE | MASK_STRING); | |
2306 | target_flags_explicit |= (MASK_POWER | MASK_MULTIPLE | MASK_STRING); | |
2307 | } | |
78f5898b AH |
2308 | break; |
2309 | ||
2310 | case OPT_mpowerpc_gpopt: | |
2311 | case OPT_mpowerpc_gfxopt: | |
2312 | if (value == 1) | |
c2dba4ab AH |
2313 | { |
2314 | target_flags |= MASK_POWERPC; | |
2315 | target_flags_explicit |= MASK_POWERPC; | |
2316 | } | |
78f5898b AH |
2317 | break; |
2318 | ||
df01da37 DE |
2319 | case OPT_maix_struct_return: |
2320 | case OPT_msvr4_struct_return: | |
2321 | rs6000_explicit_options.aix_struct_ret = true; | |
2322 | break; | |
2323 | ||
b5e3caf2 BE |
2324 | case OPT_mvrsave: |
2325 | rs6000_explicit_options.vrsave = true; | |
2326 | TARGET_ALTIVEC_VRSAVE = value; | |
2327 | break; | |
2328 | ||
78f5898b | 2329 | case OPT_mvrsave_: |
a2db2771 | 2330 | rs6000_explicit_options.vrsave = true; |
78f5898b AH |
2331 | rs6000_parse_yes_no_option ("vrsave", arg, &(TARGET_ALTIVEC_VRSAVE)); |
2332 | break; | |
78f5898b | 2333 | |
94f4765c NF |
2334 | case OPT_misel: |
2335 | rs6000_explicit_options.isel = true; | |
2336 | rs6000_isel = value; | |
2337 | break; | |
2338 | ||
78f5898b AH |
2339 | case OPT_misel_: |
2340 | rs6000_explicit_options.isel = true; | |
2341 | rs6000_parse_yes_no_option ("isel", arg, &(rs6000_isel)); | |
2342 | break; | |
2343 | ||
94f4765c NF |
2344 | case OPT_mspe: |
2345 | rs6000_explicit_options.spe = true; | |
2346 | rs6000_spe = value; | |
2347 | break; | |
2348 | ||
78f5898b AH |
2349 | case OPT_mspe_: |
2350 | rs6000_explicit_options.spe = true; | |
2351 | rs6000_parse_yes_no_option ("spe", arg, &(rs6000_spe)); | |
78f5898b AH |
2352 | break; |
2353 | ||
2354 | case OPT_mdebug_: | |
2355 | rs6000_debug_name = arg; | |
2356 | break; | |
2357 | ||
2358 | #ifdef TARGET_USES_SYSV4_OPT | |
2359 | case OPT_mcall_: | |
2360 | rs6000_abi_name = arg; | |
2361 | break; | |
2362 | ||
2363 | case OPT_msdata_: | |
2364 | rs6000_sdata_name = arg; | |
2365 | break; | |
2366 | ||
2367 | case OPT_mtls_size_: | |
2368 | rs6000_tls_size_string = arg; | |
2369 | break; | |
2370 | ||
2371 | case OPT_mrelocatable: | |
2372 | if (value == 1) | |
c2dba4ab | 2373 | { |
e0bf274f AM |
2374 | target_flags |= MASK_MINIMAL_TOC; |
2375 | target_flags_explicit |= MASK_MINIMAL_TOC; | |
2376 | TARGET_NO_FP_IN_TOC = 1; | |
c2dba4ab | 2377 | } |
78f5898b AH |
2378 | break; |
2379 | ||
2380 | case OPT_mrelocatable_lib: | |
2381 | if (value == 1) | |
c2dba4ab | 2382 | { |
e0bf274f AM |
2383 | target_flags |= MASK_RELOCATABLE | MASK_MINIMAL_TOC; |
2384 | target_flags_explicit |= MASK_RELOCATABLE | MASK_MINIMAL_TOC; | |
2385 | TARGET_NO_FP_IN_TOC = 1; | |
c2dba4ab | 2386 | } |
78f5898b | 2387 | else |
c2dba4ab AH |
2388 | { |
2389 | target_flags &= ~MASK_RELOCATABLE; | |
2390 | target_flags_explicit |= MASK_RELOCATABLE; | |
2391 | } | |
78f5898b AH |
2392 | break; |
2393 | #endif | |
2394 | ||
2395 | case OPT_mabi_: | |
78f5898b AH |
2396 | if (!strcmp (arg, "altivec")) |
2397 | { | |
a2db2771 | 2398 | rs6000_explicit_options.altivec_abi = true; |
78f5898b | 2399 | rs6000_altivec_abi = 1; |
a2db2771 JJ |
2400 | |
2401 | /* Enabling the AltiVec ABI turns off the SPE ABI. */ | |
78f5898b AH |
2402 | rs6000_spe_abi = 0; |
2403 | } | |
2404 | else if (! strcmp (arg, "no-altivec")) | |
d3603e8c | 2405 | { |
a2db2771 | 2406 | rs6000_explicit_options.altivec_abi = true; |
d3603e8c AM |
2407 | rs6000_altivec_abi = 0; |
2408 | } | |
78f5898b AH |
2409 | else if (! strcmp (arg, "spe")) |
2410 | { | |
a2db2771 | 2411 | rs6000_explicit_options.spe_abi = true; |
78f5898b AH |
2412 | rs6000_spe_abi = 1; |
2413 | rs6000_altivec_abi = 0; | |
2414 | if (!TARGET_SPE_ABI) | |
2415 | error ("not configured for ABI: '%s'", arg); | |
2416 | } | |
2417 | else if (! strcmp (arg, "no-spe")) | |
d3603e8c | 2418 | { |
a2db2771 | 2419 | rs6000_explicit_options.spe_abi = true; |
d3603e8c AM |
2420 | rs6000_spe_abi = 0; |
2421 | } | |
78f5898b AH |
2422 | |
2423 | /* These are here for testing during development only, do not | |
2424 | document in the manual please. */ | |
2425 | else if (! strcmp (arg, "d64")) | |
2426 | { | |
2427 | rs6000_darwin64_abi = 1; | |
2428 | warning (0, "Using darwin64 ABI"); | |
2429 | } | |
2430 | else if (! strcmp (arg, "d32")) | |
2431 | { | |
2432 | rs6000_darwin64_abi = 0; | |
2433 | warning (0, "Using old darwin ABI"); | |
2434 | } | |
2435 | ||
602ea4d3 JJ |
2436 | else if (! strcmp (arg, "ibmlongdouble")) |
2437 | { | |
d3603e8c | 2438 | rs6000_explicit_options.ieee = true; |
602ea4d3 JJ |
2439 | rs6000_ieeequad = 0; |
2440 | warning (0, "Using IBM extended precision long double"); | |
2441 | } | |
2442 | else if (! strcmp (arg, "ieeelongdouble")) | |
2443 | { | |
d3603e8c | 2444 | rs6000_explicit_options.ieee = true; |
602ea4d3 JJ |
2445 | rs6000_ieeequad = 1; |
2446 | warning (0, "Using IEEE extended precision long double"); | |
2447 | } | |
2448 | ||
78f5898b AH |
2449 | else |
2450 | { | |
2451 | error ("unknown ABI specified: '%s'", arg); | |
2452 | return false; | |
2453 | } | |
2454 | break; | |
2455 | ||
2456 | case OPT_mcpu_: | |
2457 | rs6000_select[1].string = arg; | |
2458 | break; | |
2459 | ||
2460 | case OPT_mtune_: | |
2461 | rs6000_select[2].string = arg; | |
2462 | break; | |
2463 | ||
2464 | case OPT_mtraceback_: | |
2465 | rs6000_traceback_name = arg; | |
2466 | break; | |
2467 | ||
2468 | case OPT_mfloat_gprs_: | |
2469 | rs6000_explicit_options.float_gprs = true; | |
2470 | if (! strcmp (arg, "yes") || ! strcmp (arg, "single")) | |
2471 | rs6000_float_gprs = 1; | |
2472 | else if (! strcmp (arg, "double")) | |
2473 | rs6000_float_gprs = 2; | |
2474 | else if (! strcmp (arg, "no")) | |
2475 | rs6000_float_gprs = 0; | |
2476 | else | |
2477 | { | |
2478 | error ("invalid option for -mfloat-gprs: '%s'", arg); | |
2479 | return false; | |
2480 | } | |
2481 | break; | |
2482 | ||
2483 | case OPT_mlong_double_: | |
2484 | rs6000_explicit_options.long_double = true; | |
2485 | rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE; | |
2486 | if (value != 64 && value != 128) | |
2487 | { | |
2488 | error ("Unknown switch -mlong-double-%s", arg); | |
2489 | rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE; | |
2490 | return false; | |
2491 | } | |
2492 | else | |
2493 | rs6000_long_double_type_size = value; | |
2494 | break; | |
2495 | ||
2496 | case OPT_msched_costly_dep_: | |
2497 | rs6000_sched_costly_dep_str = arg; | |
2498 | break; | |
2499 | ||
2500 | case OPT_malign_: | |
2501 | rs6000_explicit_options.alignment = true; | |
2502 | if (! strcmp (arg, "power")) | |
2503 | { | |
2504 | /* On 64-bit Darwin, power alignment is ABI-incompatible with | |
2505 | some C library functions, so warn about it. The flag may be | |
2506 | useful for performance studies from time to time though, so | |
2507 | don't disable it entirely. */ | |
2508 | if (DEFAULT_ABI == ABI_DARWIN && TARGET_64BIT) | |
2509 | warning (0, "-malign-power is not supported for 64-bit Darwin;" | |
2510 | " it is incompatible with the installed C and C++ libraries"); | |
2511 | rs6000_alignment_flags = MASK_ALIGN_POWER; | |
2512 | } | |
2513 | else if (! strcmp (arg, "natural")) | |
2514 | rs6000_alignment_flags = MASK_ALIGN_NATURAL; | |
2515 | else | |
2516 | { | |
2517 | error ("unknown -malign-XXXXX option specified: '%s'", arg); | |
2518 | return false; | |
2519 | } | |
2520 | break; | |
696e45ba ME |
2521 | |
2522 | case OPT_msingle_float: | |
2523 | if (!TARGET_SINGLE_FPU) | |
2524 | warning (0, "-msingle-float option equivalent to -mhard-float"); | |
2525 | /* -msingle-float implies -mno-double-float and TARGET_HARD_FLOAT. */ | |
2526 | rs6000_double_float = 0; | |
2527 | target_flags &= ~MASK_SOFT_FLOAT; | |
2528 | target_flags_explicit |= MASK_SOFT_FLOAT; | |
2529 | break; | |
2530 | ||
2531 | case OPT_mdouble_float: | |
2532 | /* -mdouble-float implies -msingle-float and TARGET_HARD_FLOAT. */ | |
2533 | rs6000_single_float = 1; | |
2534 | target_flags &= ~MASK_SOFT_FLOAT; | |
2535 | target_flags_explicit |= MASK_SOFT_FLOAT; | |
2536 | break; | |
2537 | ||
2538 | case OPT_msimple_fpu: | |
2539 | if (!TARGET_SINGLE_FPU) | |
2540 | warning (0, "-msimple-fpu option ignored"); | |
2541 | break; | |
2542 | ||
2543 | case OPT_mhard_float: | |
2544 | /* -mhard_float implies -msingle-float and -mdouble-float. */ | |
2545 | rs6000_single_float = rs6000_double_float = 1; | |
2546 | break; | |
2547 | ||
2548 | case OPT_msoft_float: | |
2549 | /* -msoft_float implies -mnosingle-float and -mnodouble-float. */ | |
2550 | rs6000_single_float = rs6000_double_float = 0; | |
2551 | break; | |
0bb7b92e ME |
2552 | |
2553 | case OPT_mfpu_: | |
2554 | fpu_type = rs6000_parse_fpu_option(arg); | |
2555 | if (fpu_type != FPU_NONE) | |
2556 | /* If -mfpu is not none, then turn off SOFT_FLOAT, turn on HARD_FLOAT. */ | |
2557 | { | |
2558 | target_flags &= ~MASK_SOFT_FLOAT; | |
2559 | target_flags_explicit |= MASK_SOFT_FLOAT; | |
2560 | rs6000_xilinx_fpu = 1; | |
2561 | if (fpu_type == FPU_SF_LITE || fpu_type == FPU_SF_FULL) | |
2562 | rs6000_single_float = 1; | |
2563 | if (fpu_type == FPU_DF_LITE || fpu_type == FPU_DF_FULL) | |
2564 | rs6000_single_float = rs6000_double_float = 1; | |
2565 | if (fpu_type == FPU_SF_LITE || fpu_type == FPU_DF_LITE) | |
2566 | rs6000_simple_fpu = 1; | |
2567 | } | |
2568 | else | |
2569 | { | |
2570 | /* -mfpu=none is equivalent to -msoft-float */ | |
2571 | target_flags |= MASK_SOFT_FLOAT; | |
2572 | target_flags_explicit |= MASK_SOFT_FLOAT; | |
2573 | rs6000_single_float = rs6000_double_float = 0; | |
2574 | } | |
2575 | break; | |
78f5898b AH |
2576 | } |
2577 | return true; | |
2578 | } | |
3cfa4909 MM |
2579 | \f |
2580 | /* Do anything needed at the start of the asm file. */ | |
2581 | ||
1bc7c5b6 | 2582 | static void |
863d938c | 2583 | rs6000_file_start (void) |
3cfa4909 | 2584 | { |
c4d38ccb | 2585 | size_t i; |
3cfa4909 | 2586 | char buffer[80]; |
d330fd93 | 2587 | const char *start = buffer; |
3cfa4909 | 2588 | struct rs6000_cpu_select *ptr; |
1bc7c5b6 ZW |
2589 | const char *default_cpu = TARGET_CPU_DEFAULT; |
2590 | FILE *file = asm_out_file; | |
2591 | ||
2592 | default_file_start (); | |
2593 | ||
2594 | #ifdef TARGET_BI_ARCH | |
2595 | if ((TARGET_DEFAULT ^ target_flags) & MASK_64BIT) | |
2596 | default_cpu = 0; | |
2597 | #endif | |
3cfa4909 MM |
2598 | |
2599 | if (flag_verbose_asm) | |
2600 | { | |
2601 | sprintf (buffer, "\n%s rs6000/powerpc options:", ASM_COMMENT_START); | |
2602 | rs6000_select[0].string = default_cpu; | |
2603 | ||
b6a1cbae | 2604 | for (i = 0; i < ARRAY_SIZE (rs6000_select); i++) |
3cfa4909 MM |
2605 | { |
2606 | ptr = &rs6000_select[i]; | |
2607 | if (ptr->string != (char *)0 && ptr->string[0] != '\0') | |
2608 | { | |
2609 | fprintf (file, "%s %s%s", start, ptr->name, ptr->string); | |
2610 | start = ""; | |
2611 | } | |
2612 | } | |
2613 | ||
9c6b4ed9 | 2614 | if (PPC405_ERRATUM77) |
b0bfee6e | 2615 | { |
9c6b4ed9 | 2616 | fprintf (file, "%s PPC405CR_ERRATUM77", start); |
b0bfee6e DE |
2617 | start = ""; |
2618 | } | |
b0bfee6e | 2619 | |
b91da81f | 2620 | #ifdef USING_ELFOS_H |
3cfa4909 MM |
2621 | switch (rs6000_sdata) |
2622 | { | |
2623 | case SDATA_NONE: fprintf (file, "%s -msdata=none", start); start = ""; break; | |
2624 | case SDATA_DATA: fprintf (file, "%s -msdata=data", start); start = ""; break; | |
2625 | case SDATA_SYSV: fprintf (file, "%s -msdata=sysv", start); start = ""; break; | |
2626 | case SDATA_EABI: fprintf (file, "%s -msdata=eabi", start); start = ""; break; | |
2627 | } | |
2628 | ||
2629 | if (rs6000_sdata && g_switch_value) | |
2630 | { | |
307b599c MK |
2631 | fprintf (file, "%s -G " HOST_WIDE_INT_PRINT_UNSIGNED, start, |
2632 | g_switch_value); | |
3cfa4909 MM |
2633 | start = ""; |
2634 | } | |
2635 | #endif | |
2636 | ||
2637 | if (*start == '\0') | |
949ea356 | 2638 | putc ('\n', file); |
3cfa4909 | 2639 | } |
b723e82f | 2640 | |
e51917ae JM |
2641 | #ifdef HAVE_AS_GNU_ATTRIBUTE |
2642 | if (TARGET_32BIT && DEFAULT_ABI == ABI_V4) | |
aaa42494 DJ |
2643 | { |
2644 | fprintf (file, "\t.gnu_attribute 4, %d\n", | |
696e45ba ME |
2645 | ((TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT) ? 1 |
2646 | : (TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT) ? 3 | |
2647 | : 2)); | |
aaa42494 DJ |
2648 | fprintf (file, "\t.gnu_attribute 8, %d\n", |
2649 | (TARGET_ALTIVEC_ABI ? 2 | |
2650 | : TARGET_SPE_ABI ? 3 | |
2651 | : 1)); | |
f9fd1e77 NF |
2652 | fprintf (file, "\t.gnu_attribute 12, %d\n", |
2653 | aix_struct_return ? 2 : 1); | |
2654 | ||
aaa42494 | 2655 | } |
e51917ae JM |
2656 | #endif |
2657 | ||
b723e82f JJ |
2658 | if (DEFAULT_ABI == ABI_AIX || (TARGET_ELF && flag_pic == 2)) |
2659 | { | |
d6b5193b RS |
2660 | switch_to_section (toc_section); |
2661 | switch_to_section (text_section); | |
b723e82f | 2662 | } |
3cfa4909 | 2663 | } |
c4e18b1c | 2664 | |
5248c961 | 2665 | \f |
a0ab749a | 2666 | /* Return nonzero if this function is known to have a null epilogue. */ |
9878760c RK |
2667 | |
2668 | int | |
863d938c | 2669 | direct_return (void) |
9878760c | 2670 | { |
4697a36c MM |
2671 | if (reload_completed) |
2672 | { | |
2673 | rs6000_stack_t *info = rs6000_stack_info (); | |
2674 | ||
2675 | if (info->first_gp_reg_save == 32 | |
2676 | && info->first_fp_reg_save == 64 | |
00b960c7 | 2677 | && info->first_altivec_reg_save == LAST_ALTIVEC_REGNO + 1 |
c81fc13e DE |
2678 | && ! info->lr_save_p |
2679 | && ! info->cr_save_p | |
00b960c7 | 2680 | && info->vrsave_mask == 0 |
c81fc13e | 2681 | && ! info->push_p) |
4697a36c MM |
2682 | return 1; |
2683 | } | |
2684 | ||
2685 | return 0; | |
9878760c RK |
2686 | } |
2687 | ||
4e74d8ec MM |
2688 | /* Return the number of instructions it takes to form a constant in an |
2689 | integer register. */ | |
2690 | ||
48d72335 | 2691 | int |
a2369ed3 | 2692 | num_insns_constant_wide (HOST_WIDE_INT value) |
4e74d8ec MM |
2693 | { |
2694 | /* signed constant loadable with {cal|addi} */ | |
547b216d | 2695 | if ((unsigned HOST_WIDE_INT) (value + 0x8000) < 0x10000) |
0865c631 GK |
2696 | return 1; |
2697 | ||
4e74d8ec | 2698 | /* constant loadable with {cau|addis} */ |
547b216d DE |
2699 | else if ((value & 0xffff) == 0 |
2700 | && (value >> 31 == -1 || value >> 31 == 0)) | |
4e74d8ec MM |
2701 | return 1; |
2702 | ||
5f59ecb7 | 2703 | #if HOST_BITS_PER_WIDE_INT == 64 |
c81fc13e | 2704 | else if (TARGET_POWERPC64) |
4e74d8ec | 2705 | { |
a65c591c DE |
2706 | HOST_WIDE_INT low = ((value & 0xffffffff) ^ 0x80000000) - 0x80000000; |
2707 | HOST_WIDE_INT high = value >> 31; | |
4e74d8ec | 2708 | |
a65c591c | 2709 | if (high == 0 || high == -1) |
4e74d8ec MM |
2710 | return 2; |
2711 | ||
a65c591c | 2712 | high >>= 1; |
4e74d8ec | 2713 | |
a65c591c | 2714 | if (low == 0) |
4e74d8ec | 2715 | return num_insns_constant_wide (high) + 1; |
4e74d8ec MM |
2716 | else |
2717 | return (num_insns_constant_wide (high) | |
e396202a | 2718 | + num_insns_constant_wide (low) + 1); |
4e74d8ec MM |
2719 | } |
2720 | #endif | |
2721 | ||
2722 | else | |
2723 | return 2; | |
2724 | } | |
2725 | ||
2726 | int | |
a2369ed3 | 2727 | num_insns_constant (rtx op, enum machine_mode mode) |
4e74d8ec | 2728 | { |
37409796 | 2729 | HOST_WIDE_INT low, high; |
bb8df8a6 | 2730 | |
37409796 | 2731 | switch (GET_CODE (op)) |
0d30d435 | 2732 | { |
37409796 | 2733 | case CONST_INT: |
0d30d435 | 2734 | #if HOST_BITS_PER_WIDE_INT == 64 |
4e2c1c44 | 2735 | if ((INTVAL (op) >> 31) != 0 && (INTVAL (op) >> 31) != -1 |
1990cd79 | 2736 | && mask64_operand (op, mode)) |
c4ad648e | 2737 | return 2; |
0d30d435 DE |
2738 | else |
2739 | #endif | |
2740 | return num_insns_constant_wide (INTVAL (op)); | |
4e74d8ec | 2741 | |
37409796 | 2742 | case CONST_DOUBLE: |
e41b2a33 | 2743 | if (mode == SFmode || mode == SDmode) |
37409796 NS |
2744 | { |
2745 | long l; | |
2746 | REAL_VALUE_TYPE rv; | |
bb8df8a6 | 2747 | |
37409796 | 2748 | REAL_VALUE_FROM_CONST_DOUBLE (rv, op); |
e41b2a33 PB |
2749 | if (DECIMAL_FLOAT_MODE_P (mode)) |
2750 | REAL_VALUE_TO_TARGET_DECIMAL32 (rv, l); | |
2751 | else | |
2752 | REAL_VALUE_TO_TARGET_SINGLE (rv, l); | |
37409796 NS |
2753 | return num_insns_constant_wide ((HOST_WIDE_INT) l); |
2754 | } | |
a260abc9 | 2755 | |
37409796 NS |
2756 | if (mode == VOIDmode || mode == DImode) |
2757 | { | |
2758 | high = CONST_DOUBLE_HIGH (op); | |
2759 | low = CONST_DOUBLE_LOW (op); | |
2760 | } | |
2761 | else | |
2762 | { | |
2763 | long l[2]; | |
2764 | REAL_VALUE_TYPE rv; | |
bb8df8a6 | 2765 | |
37409796 | 2766 | REAL_VALUE_FROM_CONST_DOUBLE (rv, op); |
7393f7f8 BE |
2767 | if (DECIMAL_FLOAT_MODE_P (mode)) |
2768 | REAL_VALUE_TO_TARGET_DECIMAL64 (rv, l); | |
2769 | else | |
2770 | REAL_VALUE_TO_TARGET_DOUBLE (rv, l); | |
37409796 NS |
2771 | high = l[WORDS_BIG_ENDIAN == 0]; |
2772 | low = l[WORDS_BIG_ENDIAN != 0]; | |
2773 | } | |
47ad8c61 | 2774 | |
37409796 NS |
2775 | if (TARGET_32BIT) |
2776 | return (num_insns_constant_wide (low) | |
2777 | + num_insns_constant_wide (high)); | |
2778 | else | |
2779 | { | |
2780 | if ((high == 0 && low >= 0) | |
2781 | || (high == -1 && low < 0)) | |
2782 | return num_insns_constant_wide (low); | |
bb8df8a6 | 2783 | |
1990cd79 | 2784 | else if (mask64_operand (op, mode)) |
37409796 | 2785 | return 2; |
bb8df8a6 | 2786 | |
37409796 NS |
2787 | else if (low == 0) |
2788 | return num_insns_constant_wide (high) + 1; | |
bb8df8a6 | 2789 | |
37409796 NS |
2790 | else |
2791 | return (num_insns_constant_wide (high) | |
2792 | + num_insns_constant_wide (low) + 1); | |
2793 | } | |
bb8df8a6 | 2794 | |
37409796 NS |
2795 | default: |
2796 | gcc_unreachable (); | |
4e74d8ec | 2797 | } |
4e74d8ec MM |
2798 | } |
2799 | ||
0972012c RS |
2800 | /* Interpret element ELT of the CONST_VECTOR OP as an integer value. |
2801 | If the mode of OP is MODE_VECTOR_INT, this simply returns the | |
2802 | corresponding element of the vector, but for V4SFmode and V2SFmode, | |
2803 | the corresponding "float" is interpreted as an SImode integer. */ | |
2804 | ||
847535b6 | 2805 | HOST_WIDE_INT |
0972012c RS |
2806 | const_vector_elt_as_int (rtx op, unsigned int elt) |
2807 | { | |
2808 | rtx tmp = CONST_VECTOR_ELT (op, elt); | |
2809 | if (GET_MODE (op) == V4SFmode | |
2810 | || GET_MODE (op) == V2SFmode) | |
2811 | tmp = gen_lowpart (SImode, tmp); | |
2812 | return INTVAL (tmp); | |
2813 | } | |
452a7d36 | 2814 | |
77ccdfed | 2815 | /* Return true if OP can be synthesized with a particular vspltisb, vspltish |
66180ff3 PB |
2816 | or vspltisw instruction. OP is a CONST_VECTOR. Which instruction is used |
2817 | depends on STEP and COPIES, one of which will be 1. If COPIES > 1, | |
2818 | all items are set to the same value and contain COPIES replicas of the | |
2819 | vsplt's operand; if STEP > 1, one in STEP elements is set to the vsplt's | |
2820 | operand and the others are set to the value of the operand's msb. */ | |
2821 | ||
2822 | static bool | |
2823 | vspltis_constant (rtx op, unsigned step, unsigned copies) | |
452a7d36 | 2824 | { |
66180ff3 PB |
2825 | enum machine_mode mode = GET_MODE (op); |
2826 | enum machine_mode inner = GET_MODE_INNER (mode); | |
2827 | ||
2828 | unsigned i; | |
2829 | unsigned nunits = GET_MODE_NUNITS (mode); | |
2830 | unsigned bitsize = GET_MODE_BITSIZE (inner); | |
2831 | unsigned mask = GET_MODE_MASK (inner); | |
2832 | ||
0972012c | 2833 | HOST_WIDE_INT val = const_vector_elt_as_int (op, nunits - 1); |
66180ff3 PB |
2834 | HOST_WIDE_INT splat_val = val; |
2835 | HOST_WIDE_INT msb_val = val > 0 ? 0 : -1; | |
2836 | ||
2837 | /* Construct the value to be splatted, if possible. If not, return 0. */ | |
2838 | for (i = 2; i <= copies; i *= 2) | |
452a7d36 | 2839 | { |
66180ff3 PB |
2840 | HOST_WIDE_INT small_val; |
2841 | bitsize /= 2; | |
2842 | small_val = splat_val >> bitsize; | |
2843 | mask >>= bitsize; | |
2844 | if (splat_val != ((small_val << bitsize) | (small_val & mask))) | |
2845 | return false; | |
2846 | splat_val = small_val; | |
2847 | } | |
c4ad648e | 2848 | |
66180ff3 PB |
2849 | /* Check if SPLAT_VAL can really be the operand of a vspltis[bhw]. */ |
2850 | if (EASY_VECTOR_15 (splat_val)) | |
2851 | ; | |
2852 | ||
2853 | /* Also check if we can splat, and then add the result to itself. Do so if | |
2854 | the value is positive, of if the splat instruction is using OP's mode; | |
2855 | for splat_val < 0, the splat and the add should use the same mode. */ | |
2856 | else if (EASY_VECTOR_15_ADD_SELF (splat_val) | |
2857 | && (splat_val >= 0 || (step == 1 && copies == 1))) | |
2858 | ; | |
2859 | ||
2860 | else | |
2861 | return false; | |
2862 | ||
2863 | /* Check if VAL is present in every STEP-th element, and the | |
2864 | other elements are filled with its most significant bit. */ | |
2865 | for (i = 0; i < nunits - 1; ++i) | |
2866 | { | |
2867 | HOST_WIDE_INT desired_val; | |
2868 | if (((i + 1) & (step - 1)) == 0) | |
2869 | desired_val = val; | |
2870 | else | |
2871 | desired_val = msb_val; | |
2872 | ||
0972012c | 2873 | if (desired_val != const_vector_elt_as_int (op, i)) |
66180ff3 | 2874 | return false; |
452a7d36 | 2875 | } |
66180ff3 PB |
2876 | |
2877 | return true; | |
452a7d36 HP |
2878 | } |
2879 | ||
69ef87e2 | 2880 | |
77ccdfed | 2881 | /* Return true if OP is of the given MODE and can be synthesized |
66180ff3 PB |
2882 | with a vspltisb, vspltish or vspltisw. */ |
2883 | ||
2884 | bool | |
2885 | easy_altivec_constant (rtx op, enum machine_mode mode) | |
d744e06e | 2886 | { |
66180ff3 | 2887 | unsigned step, copies; |
d744e06e | 2888 | |
66180ff3 PB |
2889 | if (mode == VOIDmode) |
2890 | mode = GET_MODE (op); | |
2891 | else if (mode != GET_MODE (op)) | |
2892 | return false; | |
d744e06e | 2893 | |
66180ff3 PB |
2894 | /* Start with a vspltisw. */ |
2895 | step = GET_MODE_NUNITS (mode) / 4; | |
2896 | copies = 1; | |
2897 | ||
2898 | if (vspltis_constant (op, step, copies)) | |
2899 | return true; | |
2900 | ||
2901 | /* Then try with a vspltish. */ | |
2902 | if (step == 1) | |
2903 | copies <<= 1; | |
2904 | else | |
2905 | step >>= 1; | |
2906 | ||
2907 | if (vspltis_constant (op, step, copies)) | |
2908 | return true; | |
2909 | ||
2910 | /* And finally a vspltisb. */ | |
2911 | if (step == 1) | |
2912 | copies <<= 1; | |
2913 | else | |
2914 | step >>= 1; | |
2915 | ||
2916 | if (vspltis_constant (op, step, copies)) | |
2917 | return true; | |
2918 | ||
2919 | return false; | |
d744e06e AH |
2920 | } |
2921 | ||
66180ff3 PB |
2922 | /* Generate a VEC_DUPLICATE representing a vspltis[bhw] instruction whose |
2923 | result is OP. Abort if it is not possible. */ | |
d744e06e | 2924 | |
f676971a | 2925 | rtx |
66180ff3 | 2926 | gen_easy_altivec_constant (rtx op) |
452a7d36 | 2927 | { |
66180ff3 PB |
2928 | enum machine_mode mode = GET_MODE (op); |
2929 | int nunits = GET_MODE_NUNITS (mode); | |
2930 | rtx last = CONST_VECTOR_ELT (op, nunits - 1); | |
2931 | unsigned step = nunits / 4; | |
2932 | unsigned copies = 1; | |
2933 | ||
2934 | /* Start with a vspltisw. */ | |
2935 | if (vspltis_constant (op, step, copies)) | |
2936 | return gen_rtx_VEC_DUPLICATE (V4SImode, gen_lowpart (SImode, last)); | |
2937 | ||
2938 | /* Then try with a vspltish. */ | |
2939 | if (step == 1) | |
2940 | copies <<= 1; | |
2941 | else | |
2942 | step >>= 1; | |
2943 | ||
2944 | if (vspltis_constant (op, step, copies)) | |
2945 | return gen_rtx_VEC_DUPLICATE (V8HImode, gen_lowpart (HImode, last)); | |
2946 | ||
2947 | /* And finally a vspltisb. */ | |
2948 | if (step == 1) | |
2949 | copies <<= 1; | |
2950 | else | |
2951 | step >>= 1; | |
2952 | ||
2953 | if (vspltis_constant (op, step, copies)) | |
2954 | return gen_rtx_VEC_DUPLICATE (V16QImode, gen_lowpart (QImode, last)); | |
2955 | ||
2956 | gcc_unreachable (); | |
d744e06e AH |
2957 | } |
2958 | ||
2959 | const char * | |
a2369ed3 | 2960 | output_vec_const_move (rtx *operands) |
d744e06e AH |
2961 | { |
2962 | int cst, cst2; | |
2963 | enum machine_mode mode; | |
2964 | rtx dest, vec; | |
2965 | ||
2966 | dest = operands[0]; | |
2967 | vec = operands[1]; | |
d744e06e | 2968 | mode = GET_MODE (dest); |
69ef87e2 | 2969 | |
d744e06e AH |
2970 | if (TARGET_ALTIVEC) |
2971 | { | |
66180ff3 | 2972 | rtx splat_vec; |
d744e06e AH |
2973 | if (zero_constant (vec, mode)) |
2974 | return "vxor %0,%0,%0"; | |
37409796 | 2975 | |
66180ff3 PB |
2976 | splat_vec = gen_easy_altivec_constant (vec); |
2977 | gcc_assert (GET_CODE (splat_vec) == VEC_DUPLICATE); | |
2978 | operands[1] = XEXP (splat_vec, 0); | |
2979 | if (!EASY_VECTOR_15 (INTVAL (operands[1]))) | |
2980 | return "#"; | |
bb8df8a6 | 2981 | |
66180ff3 | 2982 | switch (GET_MODE (splat_vec)) |
98ef3137 | 2983 | { |
37409796 | 2984 | case V4SImode: |
66180ff3 | 2985 | return "vspltisw %0,%1"; |
c4ad648e | 2986 | |
37409796 | 2987 | case V8HImode: |
66180ff3 | 2988 | return "vspltish %0,%1"; |
c4ad648e | 2989 | |
37409796 | 2990 | case V16QImode: |
66180ff3 | 2991 | return "vspltisb %0,%1"; |
bb8df8a6 | 2992 | |
37409796 NS |
2993 | default: |
2994 | gcc_unreachable (); | |
98ef3137 | 2995 | } |
69ef87e2 AH |
2996 | } |
2997 | ||
37409796 | 2998 | gcc_assert (TARGET_SPE); |
bb8df8a6 | 2999 | |
37409796 NS |
3000 | /* Vector constant 0 is handled as a splitter of V2SI, and in the |
3001 | pattern of V1DI, V4HI, and V2SF. | |
3002 | ||
3003 | FIXME: We should probably return # and add post reload | |
3004 | splitters for these, but this way is so easy ;-). */ | |
e20dcbef PB |
3005 | cst = INTVAL (CONST_VECTOR_ELT (vec, 0)); |
3006 | cst2 = INTVAL (CONST_VECTOR_ELT (vec, 1)); | |
3007 | operands[1] = CONST_VECTOR_ELT (vec, 0); | |
3008 | operands[2] = CONST_VECTOR_ELT (vec, 1); | |
37409796 NS |
3009 | if (cst == cst2) |
3010 | return "li %0,%1\n\tevmergelo %0,%0,%0"; | |
3011 | else | |
3012 | return "li %0,%1\n\tevmergelo %0,%0,%0\n\tli %0,%2"; | |
69ef87e2 AH |
3013 | } |
3014 | ||
f5027409 RE |
3015 | /* Initialize TARGET of vector PAIRED to VALS. */ |
3016 | ||
3017 | void | |
3018 | paired_expand_vector_init (rtx target, rtx vals) | |
3019 | { | |
3020 | enum machine_mode mode = GET_MODE (target); | |
3021 | int n_elts = GET_MODE_NUNITS (mode); | |
3022 | int n_var = 0; | |
0a2aaacc | 3023 | rtx x, new_rtx, tmp, constant_op, op1, op2; |
f5027409 RE |
3024 | int i; |
3025 | ||
3026 | for (i = 0; i < n_elts; ++i) | |
3027 | { | |
3028 | x = XVECEXP (vals, 0, i); | |
3029 | if (!CONSTANT_P (x)) | |
3030 | ++n_var; | |
3031 | } | |
3032 | if (n_var == 0) | |
3033 | { | |
3034 | /* Load from constant pool. */ | |
3035 | emit_move_insn (target, gen_rtx_CONST_VECTOR (mode, XVEC (vals, 0))); | |
3036 | return; | |
3037 | } | |
3038 | ||
3039 | if (n_var == 2) | |
3040 | { | |
3041 | /* The vector is initialized only with non-constants. */ | |
0a2aaacc | 3042 | new_rtx = gen_rtx_VEC_CONCAT (V2SFmode, XVECEXP (vals, 0, 0), |
f5027409 RE |
3043 | XVECEXP (vals, 0, 1)); |
3044 | ||
0a2aaacc | 3045 | emit_move_insn (target, new_rtx); |
f5027409 RE |
3046 | return; |
3047 | } | |
3048 | ||
3049 | /* One field is non-constant and the other one is a constant. Load the | |
3050 | constant from the constant pool and use ps_merge instruction to | |
3051 | construct the whole vector. */ | |
3052 | op1 = XVECEXP (vals, 0, 0); | |
3053 | op2 = XVECEXP (vals, 0, 1); | |
3054 | ||
3055 | constant_op = (CONSTANT_P (op1)) ? op1 : op2; | |
3056 | ||
3057 | tmp = gen_reg_rtx (GET_MODE (constant_op)); | |
3058 | emit_move_insn (tmp, constant_op); | |
3059 | ||
3060 | if (CONSTANT_P (op1)) | |
0a2aaacc | 3061 | new_rtx = gen_rtx_VEC_CONCAT (V2SFmode, tmp, op2); |
f5027409 | 3062 | else |
0a2aaacc | 3063 | new_rtx = gen_rtx_VEC_CONCAT (V2SFmode, op1, tmp); |
f5027409 | 3064 | |
0a2aaacc | 3065 | emit_move_insn (target, new_rtx); |
f5027409 RE |
3066 | } |
3067 | ||
e2e95f45 RE |
3068 | void |
3069 | paired_expand_vector_move (rtx operands[]) | |
3070 | { | |
3071 | rtx op0 = operands[0], op1 = operands[1]; | |
3072 | ||
3073 | emit_move_insn (op0, op1); | |
3074 | } | |
3075 | ||
3076 | /* Emit vector compare for code RCODE. DEST is destination, OP1 and | |
3077 | OP2 are two VEC_COND_EXPR operands, CC_OP0 and CC_OP1 are the two | |
3078 | operands for the relation operation COND. This is a recursive | |
3079 | function. */ | |
3080 | ||
3081 | static void | |
3082 | paired_emit_vector_compare (enum rtx_code rcode, | |
3083 | rtx dest, rtx op0, rtx op1, | |
3084 | rtx cc_op0, rtx cc_op1) | |
3085 | { | |
3086 | rtx tmp = gen_reg_rtx (V2SFmode); | |
3087 | rtx tmp1, max, min, equal_zero; | |
3088 | ||
3089 | gcc_assert (TARGET_PAIRED_FLOAT); | |
3090 | gcc_assert (GET_MODE (op0) == GET_MODE (op1)); | |
3091 | ||
3092 | switch (rcode) | |
3093 | { | |
3094 | case LT: | |
3095 | case LTU: | |
3096 | paired_emit_vector_compare (GE, dest, op1, op0, cc_op0, cc_op1); | |
3097 | return; | |
3098 | case GE: | |
3099 | case GEU: | |
3100 | emit_insn (gen_subv2sf3 (tmp, cc_op0, cc_op1)); | |
3101 | emit_insn (gen_selv2sf4 (dest, tmp, op0, op1, CONST0_RTX (SFmode))); | |
3102 | return; | |
3103 | case LE: | |
3104 | case LEU: | |
3105 | paired_emit_vector_compare (GE, dest, op0, op1, cc_op1, cc_op0); | |
3106 | return; | |
3107 | case GT: | |
3108 | paired_emit_vector_compare (LE, dest, op1, op0, cc_op0, cc_op1); | |
3109 | return; | |
3110 | case EQ: | |
3111 | tmp1 = gen_reg_rtx (V2SFmode); | |
3112 | max = gen_reg_rtx (V2SFmode); | |
3113 | min = gen_reg_rtx (V2SFmode); | |
3114 | equal_zero = gen_reg_rtx (V2SFmode); | |
3115 | ||
3116 | emit_insn (gen_subv2sf3 (tmp, cc_op0, cc_op1)); | |
3117 | emit_insn (gen_selv2sf4 | |
3118 | (max, tmp, cc_op0, cc_op1, CONST0_RTX (SFmode))); | |
3119 | emit_insn (gen_subv2sf3 (tmp, cc_op1, cc_op0)); | |
3120 | emit_insn (gen_selv2sf4 | |
3121 | (min, tmp, cc_op0, cc_op1, CONST0_RTX (SFmode))); | |
3122 | emit_insn (gen_subv2sf3 (tmp1, min, max)); | |
3123 | emit_insn (gen_selv2sf4 (dest, tmp1, op0, op1, CONST0_RTX (SFmode))); | |
3124 | return; | |
3125 | case NE: | |
3126 | paired_emit_vector_compare (EQ, dest, op1, op0, cc_op0, cc_op1); | |
3127 | return; | |
3128 | case UNLE: | |
3129 | paired_emit_vector_compare (LE, dest, op1, op0, cc_op0, cc_op1); | |
3130 | return; | |
3131 | case UNLT: | |
3132 | paired_emit_vector_compare (LT, dest, op1, op0, cc_op0, cc_op1); | |
3133 | return; | |
3134 | case UNGE: | |
3135 | paired_emit_vector_compare (GE, dest, op1, op0, cc_op0, cc_op1); | |
3136 | return; | |
3137 | case UNGT: | |
3138 | paired_emit_vector_compare (GT, dest, op1, op0, cc_op0, cc_op1); | |
3139 | return; | |
3140 | default: | |
3141 | gcc_unreachable (); | |
3142 | } | |
3143 | ||
3144 | return; | |
3145 | } | |
3146 | ||
3147 | /* Emit vector conditional expression. | |
3148 | DEST is destination. OP1 and OP2 are two VEC_COND_EXPR operands. | |
3149 | CC_OP0 and CC_OP1 are the two operands for the relation operation COND. */ | |
3150 | ||
3151 | int | |
3152 | paired_emit_vector_cond_expr (rtx dest, rtx op1, rtx op2, | |
3153 | rtx cond, rtx cc_op0, rtx cc_op1) | |
3154 | { | |
3155 | enum rtx_code rcode = GET_CODE (cond); | |
3156 | ||
3157 | if (!TARGET_PAIRED_FLOAT) | |
3158 | return 0; | |
3159 | ||
3160 | paired_emit_vector_compare (rcode, dest, op1, op2, cc_op0, cc_op1); | |
3161 | ||
3162 | return 1; | |
3163 | } | |
3164 | ||
7a4eca66 DE |
3165 | /* Initialize vector TARGET to VALS. */ |
3166 | ||
3167 | void | |
3168 | rs6000_expand_vector_init (rtx target, rtx vals) | |
3169 | { | |
3170 | enum machine_mode mode = GET_MODE (target); | |
3171 | enum machine_mode inner_mode = GET_MODE_INNER (mode); | |
3172 | int n_elts = GET_MODE_NUNITS (mode); | |
3173 | int n_var = 0, one_var = -1; | |
3174 | bool all_same = true, all_const_zero = true; | |
3175 | rtx x, mem; | |
3176 | int i; | |
3177 | ||
3178 | for (i = 0; i < n_elts; ++i) | |
3179 | { | |
3180 | x = XVECEXP (vals, 0, i); | |
3181 | if (!CONSTANT_P (x)) | |
3182 | ++n_var, one_var = i; | |
3183 | else if (x != CONST0_RTX (inner_mode)) | |
3184 | all_const_zero = false; | |
3185 | ||
3186 | if (i > 0 && !rtx_equal_p (x, XVECEXP (vals, 0, 0))) | |
3187 | all_same = false; | |
3188 | } | |
3189 | ||
3190 | if (n_var == 0) | |
3191 | { | |
501fb355 | 3192 | rtx const_vec = gen_rtx_CONST_VECTOR (mode, XVEC (vals, 0)); |
7a4eca66 DE |
3193 | if (mode != V4SFmode && all_const_zero) |
3194 | { | |
3195 | /* Zero register. */ | |
3196 | emit_insn (gen_rtx_SET (VOIDmode, target, | |
3197 | gen_rtx_XOR (mode, target, target))); | |
3198 | return; | |
3199 | } | |
501fb355 | 3200 | else if (mode != V4SFmode && easy_vector_constant (const_vec, mode)) |
7a4eca66 DE |
3201 | { |
3202 | /* Splat immediate. */ | |
501fb355 | 3203 | emit_insn (gen_rtx_SET (VOIDmode, target, const_vec)); |
7a4eca66 DE |
3204 | return; |
3205 | } | |
3206 | else if (all_same) | |
3207 | ; /* Splat vector element. */ | |
3208 | else | |
3209 | { | |
3210 | /* Load from constant pool. */ | |
501fb355 | 3211 | emit_move_insn (target, const_vec); |
7a4eca66 DE |
3212 | return; |
3213 | } | |
3214 | } | |
3215 | ||
3216 | /* Store value to stack temp. Load vector element. Splat. */ | |
3217 | if (all_same) | |
3218 | { | |
3219 | mem = assign_stack_temp (mode, GET_MODE_SIZE (inner_mode), 0); | |
3220 | emit_move_insn (adjust_address_nv (mem, inner_mode, 0), | |
3221 | XVECEXP (vals, 0, 0)); | |
3222 | x = gen_rtx_UNSPEC (VOIDmode, | |
3223 | gen_rtvec (1, const0_rtx), UNSPEC_LVE); | |
3224 | emit_insn (gen_rtx_PARALLEL (VOIDmode, | |
3225 | gen_rtvec (2, | |
3226 | gen_rtx_SET (VOIDmode, | |
3227 | target, mem), | |
3228 | x))); | |
3229 | x = gen_rtx_VEC_SELECT (inner_mode, target, | |
3230 | gen_rtx_PARALLEL (VOIDmode, | |
3231 | gen_rtvec (1, const0_rtx))); | |
3232 | emit_insn (gen_rtx_SET (VOIDmode, target, | |
3233 | gen_rtx_VEC_DUPLICATE (mode, x))); | |
3234 | return; | |
3235 | } | |
3236 | ||
3237 | /* One field is non-constant. Load constant then overwrite | |
3238 | varying field. */ | |
3239 | if (n_var == 1) | |
3240 | { | |
3241 | rtx copy = copy_rtx (vals); | |
3242 | ||
57b51d4d | 3243 | /* Load constant part of vector, substitute neighboring value for |
7a4eca66 DE |
3244 | varying element. */ |
3245 | XVECEXP (copy, 0, one_var) = XVECEXP (vals, 0, (one_var + 1) % n_elts); | |
3246 | rs6000_expand_vector_init (target, copy); | |
3247 | ||
3248 | /* Insert variable. */ | |
3249 | rs6000_expand_vector_set (target, XVECEXP (vals, 0, one_var), one_var); | |
3250 | return; | |
3251 | } | |
3252 | ||
3253 | /* Construct the vector in memory one field at a time | |
3254 | and load the whole vector. */ | |
3255 | mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), 0); | |
3256 | for (i = 0; i < n_elts; i++) | |
3257 | emit_move_insn (adjust_address_nv (mem, inner_mode, | |
3258 | i * GET_MODE_SIZE (inner_mode)), | |
3259 | XVECEXP (vals, 0, i)); | |
3260 | emit_move_insn (target, mem); | |
3261 | } | |
3262 | ||
3263 | /* Set field ELT of TARGET to VAL. */ | |
3264 | ||
3265 | void | |
3266 | rs6000_expand_vector_set (rtx target, rtx val, int elt) | |
3267 | { | |
3268 | enum machine_mode mode = GET_MODE (target); | |
3269 | enum machine_mode inner_mode = GET_MODE_INNER (mode); | |
3270 | rtx reg = gen_reg_rtx (mode); | |
3271 | rtx mask, mem, x; | |
3272 | int width = GET_MODE_SIZE (inner_mode); | |
3273 | int i; | |
3274 | ||
3275 | /* Load single variable value. */ | |
3276 | mem = assign_stack_temp (mode, GET_MODE_SIZE (inner_mode), 0); | |
3277 | emit_move_insn (adjust_address_nv (mem, inner_mode, 0), val); | |
3278 | x = gen_rtx_UNSPEC (VOIDmode, | |
3279 | gen_rtvec (1, const0_rtx), UNSPEC_LVE); | |
3280 | emit_insn (gen_rtx_PARALLEL (VOIDmode, | |
3281 | gen_rtvec (2, | |
3282 | gen_rtx_SET (VOIDmode, | |
3283 | reg, mem), | |
3284 | x))); | |
3285 | ||
3286 | /* Linear sequence. */ | |
3287 | mask = gen_rtx_PARALLEL (V16QImode, rtvec_alloc (16)); | |
3288 | for (i = 0; i < 16; ++i) | |
3289 | XVECEXP (mask, 0, i) = GEN_INT (i); | |
3290 | ||
3291 | /* Set permute mask to insert element into target. */ | |
3292 | for (i = 0; i < width; ++i) | |
3293 | XVECEXP (mask, 0, elt*width + i) | |
3294 | = GEN_INT (i + 0x10); | |
3295 | x = gen_rtx_CONST_VECTOR (V16QImode, XVEC (mask, 0)); | |
3296 | x = gen_rtx_UNSPEC (mode, | |
3297 | gen_rtvec (3, target, reg, | |
3298 | force_reg (V16QImode, x)), | |
3299 | UNSPEC_VPERM); | |
3300 | emit_insn (gen_rtx_SET (VOIDmode, target, x)); | |
3301 | } | |
3302 | ||
3303 | /* Extract field ELT from VEC into TARGET. */ | |
3304 | ||
3305 | void | |
3306 | rs6000_expand_vector_extract (rtx target, rtx vec, int elt) | |
3307 | { | |
3308 | enum machine_mode mode = GET_MODE (vec); | |
3309 | enum machine_mode inner_mode = GET_MODE_INNER (mode); | |
3310 | rtx mem, x; | |
3311 | ||
3312 | /* Allocate mode-sized buffer. */ | |
3313 | mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), 0); | |
3314 | ||
3315 | /* Add offset to field within buffer matching vector element. */ | |
3316 | mem = adjust_address_nv (mem, mode, elt * GET_MODE_SIZE (inner_mode)); | |
3317 | ||
3318 | /* Store single field into mode-sized buffer. */ | |
3319 | x = gen_rtx_UNSPEC (VOIDmode, | |
3320 | gen_rtvec (1, const0_rtx), UNSPEC_STVE); | |
3321 | emit_insn (gen_rtx_PARALLEL (VOIDmode, | |
3322 | gen_rtvec (2, | |
3323 | gen_rtx_SET (VOIDmode, | |
3324 | mem, vec), | |
3325 | x))); | |
3326 | emit_move_insn (target, adjust_address_nv (mem, inner_mode, 0)); | |
3327 | } | |
3328 | ||
0ba1b2ff AM |
3329 | /* Generates shifts and masks for a pair of rldicl or rldicr insns to |
3330 | implement ANDing by the mask IN. */ | |
3331 | void | |
a2369ed3 | 3332 | build_mask64_2_operands (rtx in, rtx *out) |
0ba1b2ff AM |
3333 | { |
3334 | #if HOST_BITS_PER_WIDE_INT >= 64 | |
3335 | unsigned HOST_WIDE_INT c, lsb, m1, m2; | |
3336 | int shift; | |
3337 | ||
37409796 | 3338 | gcc_assert (GET_CODE (in) == CONST_INT); |
0ba1b2ff AM |
3339 | |
3340 | c = INTVAL (in); | |
3341 | if (c & 1) | |
3342 | { | |
3343 | /* Assume c initially something like 0x00fff000000fffff. The idea | |
3344 | is to rotate the word so that the middle ^^^^^^ group of zeros | |
3345 | is at the MS end and can be cleared with an rldicl mask. We then | |
3346 | rotate back and clear off the MS ^^ group of zeros with a | |
3347 | second rldicl. */ | |
3348 | c = ~c; /* c == 0xff000ffffff00000 */ | |
3349 | lsb = c & -c; /* lsb == 0x0000000000100000 */ | |
3350 | m1 = -lsb; /* m1 == 0xfffffffffff00000 */ | |
3351 | c = ~c; /* c == 0x00fff000000fffff */ | |
3352 | c &= -lsb; /* c == 0x00fff00000000000 */ | |
3353 | lsb = c & -c; /* lsb == 0x0000100000000000 */ | |
3354 | c = ~c; /* c == 0xff000fffffffffff */ | |
3355 | c &= -lsb; /* c == 0xff00000000000000 */ | |
3356 | shift = 0; | |
3357 | while ((lsb >>= 1) != 0) | |
3358 | shift++; /* shift == 44 on exit from loop */ | |
3359 | m1 <<= 64 - shift; /* m1 == 0xffffff0000000000 */ | |
3360 | m1 = ~m1; /* m1 == 0x000000ffffffffff */ | |
3361 | m2 = ~c; /* m2 == 0x00ffffffffffffff */ | |
a260abc9 DE |
3362 | } |
3363 | else | |
0ba1b2ff AM |
3364 | { |
3365 | /* Assume c initially something like 0xff000f0000000000. The idea | |
3366 | is to rotate the word so that the ^^^ middle group of zeros | |
3367 | is at the LS end and can be cleared with an rldicr mask. We then | |
3368 | rotate back and clear off the LS group of ^^^^^^^^^^ zeros with | |
3369 | a second rldicr. */ | |
3370 | lsb = c & -c; /* lsb == 0x0000010000000000 */ | |
3371 | m2 = -lsb; /* m2 == 0xffffff0000000000 */ | |
3372 | c = ~c; /* c == 0x00fff0ffffffffff */ | |
3373 | c &= -lsb; /* c == 0x00fff00000000000 */ | |
3374 | lsb = c & -c; /* lsb == 0x0000100000000000 */ | |
3375 | c = ~c; /* c == 0xff000fffffffffff */ | |
3376 | c &= -lsb; /* c == 0xff00000000000000 */ | |
3377 | shift = 0; | |
3378 | while ((lsb >>= 1) != 0) | |
3379 | shift++; /* shift == 44 on exit from loop */ | |
3380 | m1 = ~c; /* m1 == 0x00ffffffffffffff */ | |
3381 | m1 >>= shift; /* m1 == 0x0000000000000fff */ | |
3382 | m1 = ~m1; /* m1 == 0xfffffffffffff000 */ | |
3383 | } | |
3384 | ||
3385 | /* Note that when we only have two 0->1 and 1->0 transitions, one of the | |
3386 | masks will be all 1's. We are guaranteed more than one transition. */ | |
3387 | out[0] = GEN_INT (64 - shift); | |
3388 | out[1] = GEN_INT (m1); | |
3389 | out[2] = GEN_INT (shift); | |
3390 | out[3] = GEN_INT (m2); | |
3391 | #else | |
045572c7 GK |
3392 | (void)in; |
3393 | (void)out; | |
37409796 | 3394 | gcc_unreachable (); |
0ba1b2ff | 3395 | #endif |
a260abc9 DE |
3396 | } |
3397 | ||
54b695e7 | 3398 | /* Return TRUE if OP is an invalid SUBREG operation on the e500. */ |
48d72335 DE |
3399 | |
3400 | bool | |
54b695e7 AH |
3401 | invalid_e500_subreg (rtx op, enum machine_mode mode) |
3402 | { | |
61c76239 JM |
3403 | if (TARGET_E500_DOUBLE) |
3404 | { | |
17caeff2 | 3405 | /* Reject (subreg:SI (reg:DF)); likewise with subreg:DI or |
4f011e1e JM |
3406 | subreg:TI and reg:TF. Decimal float modes are like integer |
3407 | modes (only low part of each register used) for this | |
3408 | purpose. */ | |
61c76239 | 3409 | if (GET_CODE (op) == SUBREG |
4f011e1e JM |
3410 | && (mode == SImode || mode == DImode || mode == TImode |
3411 | || mode == DDmode || mode == TDmode) | |
61c76239 | 3412 | && REG_P (SUBREG_REG (op)) |
17caeff2 | 3413 | && (GET_MODE (SUBREG_REG (op)) == DFmode |
4f011e1e | 3414 | || GET_MODE (SUBREG_REG (op)) == TFmode)) |
61c76239 JM |
3415 | return true; |
3416 | ||
17caeff2 JM |
3417 | /* Reject (subreg:DF (reg:DI)); likewise with subreg:TF and |
3418 | reg:TI. */ | |
61c76239 | 3419 | if (GET_CODE (op) == SUBREG |
4f011e1e | 3420 | && (mode == DFmode || mode == TFmode) |
61c76239 | 3421 | && REG_P (SUBREG_REG (op)) |
17caeff2 | 3422 | && (GET_MODE (SUBREG_REG (op)) == DImode |
4f011e1e JM |
3423 | || GET_MODE (SUBREG_REG (op)) == TImode |
3424 | || GET_MODE (SUBREG_REG (op)) == DDmode | |
3425 | || GET_MODE (SUBREG_REG (op)) == TDmode)) | |
61c76239 JM |
3426 | return true; |
3427 | } | |
54b695e7 | 3428 | |
61c76239 JM |
3429 | if (TARGET_SPE |
3430 | && GET_CODE (op) == SUBREG | |
3431 | && mode == SImode | |
54b695e7 | 3432 | && REG_P (SUBREG_REG (op)) |
14502dad | 3433 | && SPE_VECTOR_MODE (GET_MODE (SUBREG_REG (op)))) |
54b695e7 AH |
3434 | return true; |
3435 | ||
3436 | return false; | |
3437 | } | |
3438 | ||
58182de3 | 3439 | /* AIX increases natural record alignment to doubleword if the first |
95727fb8 AP |
3440 | field is an FP double while the FP fields remain word aligned. */ |
3441 | ||
19d66194 | 3442 | unsigned int |
fa5b0972 AM |
3443 | rs6000_special_round_type_align (tree type, unsigned int computed, |
3444 | unsigned int specified) | |
95727fb8 | 3445 | { |
fa5b0972 | 3446 | unsigned int align = MAX (computed, specified); |
95727fb8 | 3447 | tree field = TYPE_FIELDS (type); |
95727fb8 | 3448 | |
bb8df8a6 | 3449 | /* Skip all non field decls */ |
85962ac8 | 3450 | while (field != NULL && TREE_CODE (field) != FIELD_DECL) |
95727fb8 AP |
3451 | field = TREE_CHAIN (field); |
3452 | ||
fa5b0972 AM |
3453 | if (field != NULL && field != type) |
3454 | { | |
3455 | type = TREE_TYPE (field); | |
3456 | while (TREE_CODE (type) == ARRAY_TYPE) | |
3457 | type = TREE_TYPE (type); | |
3458 | ||
3459 | if (type != error_mark_node && TYPE_MODE (type) == DFmode) | |
3460 | align = MAX (align, 64); | |
3461 | } | |
95727fb8 | 3462 | |
fa5b0972 | 3463 | return align; |
95727fb8 AP |
3464 | } |
3465 | ||
58182de3 GK |
3466 | /* Darwin increases record alignment to the natural alignment of |
3467 | the first field. */ | |
3468 | ||
3469 | unsigned int | |
3470 | darwin_rs6000_special_round_type_align (tree type, unsigned int computed, | |
3471 | unsigned int specified) | |
3472 | { | |
3473 | unsigned int align = MAX (computed, specified); | |
3474 | ||
3475 | if (TYPE_PACKED (type)) | |
3476 | return align; | |
3477 | ||
3478 | /* Find the first field, looking down into aggregates. */ | |
3479 | do { | |
3480 | tree field = TYPE_FIELDS (type); | |
3481 | /* Skip all non field decls */ | |
3482 | while (field != NULL && TREE_CODE (field) != FIELD_DECL) | |
3483 | field = TREE_CHAIN (field); | |
3484 | if (! field) | |
3485 | break; | |
3486 | type = TREE_TYPE (field); | |
3487 | while (TREE_CODE (type) == ARRAY_TYPE) | |
3488 | type = TREE_TYPE (type); | |
3489 | } while (AGGREGATE_TYPE_P (type)); | |
3490 | ||
3491 | if (! AGGREGATE_TYPE_P (type) && type != error_mark_node) | |
3492 | align = MAX (align, TYPE_ALIGN (type)); | |
3493 | ||
3494 | return align; | |
3495 | } | |
3496 | ||
a4f6c312 | 3497 | /* Return 1 for an operand in small memory on V.4/eabi. */ |
7509c759 MM |
3498 | |
3499 | int | |
f676971a | 3500 | small_data_operand (rtx op ATTRIBUTE_UNUSED, |
a2369ed3 | 3501 | enum machine_mode mode ATTRIBUTE_UNUSED) |
7509c759 | 3502 | { |
38c1f2d7 | 3503 | #if TARGET_ELF |
5f59ecb7 | 3504 | rtx sym_ref; |
7509c759 | 3505 | |
d9407988 | 3506 | if (rs6000_sdata == SDATA_NONE || rs6000_sdata == SDATA_DATA) |
a54d04b7 | 3507 | return 0; |
a54d04b7 | 3508 | |
f607bc57 | 3509 | if (DEFAULT_ABI != ABI_V4) |
7509c759 MM |
3510 | return 0; |
3511 | ||
2aa42e6e NF |
3512 | /* Vector and float memory instructions have a limited offset on the |
3513 | SPE, so using a vector or float variable directly as an operand is | |
3514 | not useful. */ | |
3515 | if (TARGET_SPE | |
3516 | && (SPE_VECTOR_MODE (mode) || FLOAT_MODE_P (mode))) | |
3517 | return 0; | |
3518 | ||
88228c4b MM |
3519 | if (GET_CODE (op) == SYMBOL_REF) |
3520 | sym_ref = op; | |
3521 | ||
3522 | else if (GET_CODE (op) != CONST | |
3523 | || GET_CODE (XEXP (op, 0)) != PLUS | |
3524 | || GET_CODE (XEXP (XEXP (op, 0), 0)) != SYMBOL_REF | |
3525 | || GET_CODE (XEXP (XEXP (op, 0), 1)) != CONST_INT) | |
7509c759 MM |
3526 | return 0; |
3527 | ||
88228c4b | 3528 | else |
dbf55e53 MM |
3529 | { |
3530 | rtx sum = XEXP (op, 0); | |
3531 | HOST_WIDE_INT summand; | |
3532 | ||
3533 | /* We have to be careful here, because it is the referenced address | |
c4ad648e | 3534 | that must be 32k from _SDA_BASE_, not just the symbol. */ |
dbf55e53 | 3535 | summand = INTVAL (XEXP (sum, 1)); |
307b599c | 3536 | if (summand < 0 || (unsigned HOST_WIDE_INT) summand > g_switch_value) |
9390387d | 3537 | return 0; |
dbf55e53 MM |
3538 | |
3539 | sym_ref = XEXP (sum, 0); | |
3540 | } | |
88228c4b | 3541 | |
20bfcd69 | 3542 | return SYMBOL_REF_SMALL_P (sym_ref); |
d9407988 MM |
3543 | #else |
3544 | return 0; | |
3545 | #endif | |
7509c759 | 3546 | } |
46c07df8 | 3547 | |
3a1f863f | 3548 | /* Return true if either operand is a general purpose register. */ |
46c07df8 | 3549 | |
3a1f863f DE |
3550 | bool |
3551 | gpr_or_gpr_p (rtx op0, rtx op1) | |
46c07df8 | 3552 | { |
3a1f863f DE |
3553 | return ((REG_P (op0) && INT_REGNO_P (REGNO (op0))) |
3554 | || (REG_P (op1) && INT_REGNO_P (REGNO (op1)))); | |
46c07df8 HP |
3555 | } |
3556 | ||
9ebbca7d | 3557 | \f |
4d588c14 RH |
3558 | /* Subroutines of rs6000_legitimize_address and rs6000_legitimate_address. */ |
3559 | ||
4d588c14 | 3560 | static bool |
a2369ed3 | 3561 | constant_pool_expr_p (rtx op) |
9ebbca7d | 3562 | { |
2e4316da RS |
3563 | rtx base, offset; |
3564 | ||
3565 | split_const (op, &base, &offset); | |
3566 | return (GET_CODE (base) == SYMBOL_REF | |
3567 | && CONSTANT_POOL_ADDRESS_P (base) | |
3568 | && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (base), Pmode)); | |
9ebbca7d GK |
3569 | } |
3570 | ||
48d72335 | 3571 | bool |
a2369ed3 | 3572 | toc_relative_expr_p (rtx op) |
9ebbca7d | 3573 | { |
2e4316da RS |
3574 | rtx base, offset; |
3575 | ||
3576 | if (GET_CODE (op) != CONST) | |
3577 | return false; | |
3578 | ||
3579 | split_const (op, &base, &offset); | |
3580 | return (GET_CODE (base) == UNSPEC | |
3581 | && XINT (base, 1) == UNSPEC_TOCREL); | |
4d588c14 RH |
3582 | } |
3583 | ||
4d588c14 | 3584 | bool |
a2369ed3 | 3585 | legitimate_constant_pool_address_p (rtx x) |
4d588c14 RH |
3586 | { |
3587 | return (TARGET_TOC | |
3588 | && GET_CODE (x) == PLUS | |
3589 | && GET_CODE (XEXP (x, 0)) == REG | |
3590 | && (TARGET_MINIMAL_TOC || REGNO (XEXP (x, 0)) == TOC_REGISTER) | |
2e4316da | 3591 | && toc_relative_expr_p (XEXP (x, 1))); |
4d588c14 RH |
3592 | } |
3593 | ||
d04b6e6e EB |
3594 | static bool |
3595 | legitimate_small_data_p (enum machine_mode mode, rtx x) | |
4d588c14 RH |
3596 | { |
3597 | return (DEFAULT_ABI == ABI_V4 | |
3598 | && !flag_pic && !TARGET_TOC | |
3599 | && (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST) | |
3600 | && small_data_operand (x, mode)); | |
3601 | } | |
3602 | ||
60cdabab DE |
3603 | /* SPE offset addressing is limited to 5-bits worth of double words. */ |
3604 | #define SPE_CONST_OFFSET_OK(x) (((x) & ~0xf8) == 0) | |
3605 | ||
76d2b81d DJ |
3606 | bool |
3607 | rs6000_legitimate_offset_address_p (enum machine_mode mode, rtx x, int strict) | |
4d588c14 RH |
3608 | { |
3609 | unsigned HOST_WIDE_INT offset, extra; | |
3610 | ||
3611 | if (GET_CODE (x) != PLUS) | |
3612 | return false; | |
3613 | if (GET_CODE (XEXP (x, 0)) != REG) | |
3614 | return false; | |
3615 | if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict)) | |
3616 | return false; | |
60cdabab DE |
3617 | if (legitimate_constant_pool_address_p (x)) |
3618 | return true; | |
4d588c14 RH |
3619 | if (GET_CODE (XEXP (x, 1)) != CONST_INT) |
3620 | return false; | |
3621 | ||
3622 | offset = INTVAL (XEXP (x, 1)); | |
3623 | extra = 0; | |
3624 | switch (mode) | |
3625 | { | |
3626 | case V16QImode: | |
3627 | case V8HImode: | |
3628 | case V4SFmode: | |
3629 | case V4SImode: | |
7a4eca66 | 3630 | /* AltiVec vector modes. Only reg+reg addressing is valid and |
1a23970d DE |
3631 | constant offset zero should not occur due to canonicalization. */ |
3632 | return false; | |
4d588c14 RH |
3633 | |
3634 | case V4HImode: | |
3635 | case V2SImode: | |
3636 | case V1DImode: | |
3637 | case V2SFmode: | |
d42a3bae | 3638 | /* Paired vector modes. Only reg+reg addressing is valid and |
1a23970d | 3639 | constant offset zero should not occur due to canonicalization. */ |
d42a3bae | 3640 | if (TARGET_PAIRED_FLOAT) |
1a23970d | 3641 | return false; |
4d588c14 RH |
3642 | /* SPE vector modes. */ |
3643 | return SPE_CONST_OFFSET_OK (offset); | |
3644 | ||
3645 | case DFmode: | |
4d4cbc0e AH |
3646 | if (TARGET_E500_DOUBLE) |
3647 | return SPE_CONST_OFFSET_OK (offset); | |
3648 | ||
4f011e1e | 3649 | case DDmode: |
4d588c14 | 3650 | case DImode: |
54b695e7 AH |
3651 | /* On e500v2, we may have: |
3652 | ||
3653 | (subreg:DF (mem:DI (plus (reg) (const_int))) 0). | |
3654 | ||
3655 | Which gets addressed with evldd instructions. */ | |
3656 | if (TARGET_E500_DOUBLE) | |
3657 | return SPE_CONST_OFFSET_OK (offset); | |
3658 | ||
7393f7f8 | 3659 | if (mode == DFmode || mode == DDmode || !TARGET_POWERPC64) |
4d588c14 RH |
3660 | extra = 4; |
3661 | else if (offset & 3) | |
3662 | return false; | |
3663 | break; | |
3664 | ||
3665 | case TFmode: | |
17caeff2 JM |
3666 | if (TARGET_E500_DOUBLE) |
3667 | return (SPE_CONST_OFFSET_OK (offset) | |
3668 | && SPE_CONST_OFFSET_OK (offset + 8)); | |
3669 | ||
4f011e1e | 3670 | case TDmode: |
4d588c14 | 3671 | case TImode: |
7393f7f8 | 3672 | if (mode == TFmode || mode == TDmode || !TARGET_POWERPC64) |
4d588c14 RH |
3673 | extra = 12; |
3674 | else if (offset & 3) | |
3675 | return false; | |
3676 | else | |
3677 | extra = 8; | |
3678 | break; | |
3679 | ||
3680 | default: | |
3681 | break; | |
3682 | } | |
3683 | ||
b1917422 AM |
3684 | offset += 0x8000; |
3685 | return (offset < 0x10000) && (offset + extra < 0x10000); | |
4d588c14 RH |
3686 | } |
3687 | ||
6fb5fa3c | 3688 | bool |
a2369ed3 | 3689 | legitimate_indexed_address_p (rtx x, int strict) |
4d588c14 RH |
3690 | { |
3691 | rtx op0, op1; | |
3692 | ||
3693 | if (GET_CODE (x) != PLUS) | |
3694 | return false; | |
850e8d3d | 3695 | |
4d588c14 RH |
3696 | op0 = XEXP (x, 0); |
3697 | op1 = XEXP (x, 1); | |
3698 | ||
bf00cc0f | 3699 | /* Recognize the rtl generated by reload which we know will later be |
9024f4b8 AM |
3700 | replaced with proper base and index regs. */ |
3701 | if (!strict | |
3702 | && reload_in_progress | |
3703 | && (REG_P (op0) || GET_CODE (op0) == PLUS) | |
3704 | && REG_P (op1)) | |
3705 | return true; | |
3706 | ||
3707 | return (REG_P (op0) && REG_P (op1) | |
3708 | && ((INT_REG_OK_FOR_BASE_P (op0, strict) | |
3709 | && INT_REG_OK_FOR_INDEX_P (op1, strict)) | |
3710 | || (INT_REG_OK_FOR_BASE_P (op1, strict) | |
3711 | && INT_REG_OK_FOR_INDEX_P (op0, strict)))); | |
9ebbca7d GK |
3712 | } |
3713 | ||
001b9eb6 PH |
3714 | bool |
3715 | avoiding_indexed_address_p (enum machine_mode mode) | |
3716 | { | |
3717 | /* Avoid indexed addressing for modes that have non-indexed | |
3718 | load/store instruction forms. */ | |
3719 | return TARGET_AVOID_XFORM && !ALTIVEC_VECTOR_MODE (mode); | |
3720 | } | |
3721 | ||
48d72335 | 3722 | inline bool |
a2369ed3 | 3723 | legitimate_indirect_address_p (rtx x, int strict) |
4d588c14 RH |
3724 | { |
3725 | return GET_CODE (x) == REG && INT_REG_OK_FOR_BASE_P (x, strict); | |
3726 | } | |
3727 | ||
48d72335 | 3728 | bool |
4c81e946 FJ |
3729 | macho_lo_sum_memory_operand (rtx x, enum machine_mode mode) |
3730 | { | |
c4ad648e | 3731 | if (!TARGET_MACHO || !flag_pic |
9390387d | 3732 | || mode != SImode || GET_CODE (x) != MEM) |
c4ad648e AM |
3733 | return false; |
3734 | x = XEXP (x, 0); | |
4c81e946 FJ |
3735 | |
3736 | if (GET_CODE (x) != LO_SUM) | |
3737 | return false; | |
3738 | if (GET_CODE (XEXP (x, 0)) != REG) | |
3739 | return false; | |
3740 | if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), 0)) | |
3741 | return false; | |
3742 | x = XEXP (x, 1); | |
3743 | ||
3744 | return CONSTANT_P (x); | |
3745 | } | |
3746 | ||
4d588c14 | 3747 | static bool |
a2369ed3 | 3748 | legitimate_lo_sum_address_p (enum machine_mode mode, rtx x, int strict) |
4d588c14 RH |
3749 | { |
3750 | if (GET_CODE (x) != LO_SUM) | |
3751 | return false; | |
3752 | if (GET_CODE (XEXP (x, 0)) != REG) | |
3753 | return false; | |
3754 | if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict)) | |
3755 | return false; | |
54b695e7 | 3756 | /* Restrict addressing for DI because of our SUBREG hackery. */ |
17caeff2 | 3757 | if (TARGET_E500_DOUBLE && (mode == DFmode || mode == TFmode |
4d4447b5 | 3758 | || mode == DDmode || mode == TDmode |
17caeff2 | 3759 | || mode == DImode)) |
f82f556d | 3760 | return false; |
4d588c14 RH |
3761 | x = XEXP (x, 1); |
3762 | ||
8622e235 | 3763 | if (TARGET_ELF || TARGET_MACHO) |
4d588c14 | 3764 | { |
a29077da | 3765 | if (DEFAULT_ABI != ABI_AIX && DEFAULT_ABI != ABI_DARWIN && flag_pic) |
4d588c14 RH |
3766 | return false; |
3767 | if (TARGET_TOC) | |
3768 | return false; | |
3769 | if (GET_MODE_NUNITS (mode) != 1) | |
3770 | return false; | |
5e5f01b9 | 3771 | if (GET_MODE_BITSIZE (mode) > 64 |
3c028f65 | 3772 | || (GET_MODE_BITSIZE (mode) > 32 && !TARGET_POWERPC64 |
696e45ba | 3773 | && !(TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT |
4d4447b5 | 3774 | && (mode == DFmode || mode == DDmode)))) |
4d588c14 RH |
3775 | return false; |
3776 | ||
3777 | return CONSTANT_P (x); | |
3778 | } | |
3779 | ||
3780 | return false; | |
3781 | } | |
3782 | ||
3783 | ||
9ebbca7d GK |
3784 | /* Try machine-dependent ways of modifying an illegitimate address |
3785 | to be legitimate. If we find one, return the new, valid address. | |
3786 | This is used from only one place: `memory_address' in explow.c. | |
3787 | ||
a4f6c312 SS |
3788 | OLDX is the address as it was before break_out_memory_refs was |
3789 | called. In some cases it is useful to look at this to decide what | |
3790 | needs to be done. | |
9ebbca7d | 3791 | |
a4f6c312 | 3792 | MODE is passed so that this function can use GO_IF_LEGITIMATE_ADDRESS. |
9ebbca7d | 3793 | |
a4f6c312 SS |
3794 | It is always safe for this function to do nothing. It exists to |
3795 | recognize opportunities to optimize the output. | |
9ebbca7d GK |
3796 | |
3797 | On RS/6000, first check for the sum of a register with a constant | |
3798 | integer that is out of range. If so, generate code to add the | |
3799 | constant with the low-order 16 bits masked to the register and force | |
3800 | this result into another register (this can be done with `cau'). | |
3801 | Then generate an address of REG+(CONST&0xffff), allowing for the | |
3802 | possibility of bit 16 being a one. | |
3803 | ||
3804 | Then check for the sum of a register and something not constant, try to | |
3805 | load the other things into a register and return the sum. */ | |
4d588c14 | 3806 | |
9ebbca7d | 3807 | rtx |
a2369ed3 DJ |
3808 | rs6000_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED, |
3809 | enum machine_mode mode) | |
0ac081f6 | 3810 | { |
c4501e62 JJ |
3811 | if (GET_CODE (x) == SYMBOL_REF) |
3812 | { | |
3813 | enum tls_model model = SYMBOL_REF_TLS_MODEL (x); | |
3814 | if (model != 0) | |
3815 | return rs6000_legitimize_tls_address (x, model); | |
3816 | } | |
3817 | ||
f676971a | 3818 | if (GET_CODE (x) == PLUS |
9ebbca7d GK |
3819 | && GET_CODE (XEXP (x, 0)) == REG |
3820 | && GET_CODE (XEXP (x, 1)) == CONST_INT | |
3c1eb9eb | 3821 | && (unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 1)) + 0x8000) >= 0x10000 |
7da13f1d NF |
3822 | && !((TARGET_POWERPC64 |
3823 | && (mode == DImode || mode == TImode) | |
3824 | && (INTVAL (XEXP (x, 1)) & 3) != 0) | |
3825 | || SPE_VECTOR_MODE (mode) | |
efc05e3c | 3826 | || ALTIVEC_VECTOR_MODE (mode) |
3c1eb9eb | 3827 | || (TARGET_E500_DOUBLE && (mode == DFmode || mode == TFmode |
4f011e1e JM |
3828 | || mode == DImode || mode == DDmode |
3829 | || mode == TDmode)))) | |
f676971a | 3830 | { |
9ebbca7d GK |
3831 | HOST_WIDE_INT high_int, low_int; |
3832 | rtx sum; | |
a65c591c DE |
3833 | low_int = ((INTVAL (XEXP (x, 1)) & 0xffff) ^ 0x8000) - 0x8000; |
3834 | high_int = INTVAL (XEXP (x, 1)) - low_int; | |
9ebbca7d GK |
3835 | sum = force_operand (gen_rtx_PLUS (Pmode, XEXP (x, 0), |
3836 | GEN_INT (high_int)), 0); | |
3837 | return gen_rtx_PLUS (Pmode, sum, GEN_INT (low_int)); | |
3838 | } | |
f676971a | 3839 | else if (GET_CODE (x) == PLUS |
9ebbca7d GK |
3840 | && GET_CODE (XEXP (x, 0)) == REG |
3841 | && GET_CODE (XEXP (x, 1)) != CONST_INT | |
6ac7bf2c | 3842 | && GET_MODE_NUNITS (mode) == 1 |
696e45ba | 3843 | && ((TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT) |
a3170dc6 | 3844 | || TARGET_POWERPC64 |
efc05e3c | 3845 | || ((mode != DImode && mode != DFmode && mode != DDmode) |
4f011e1e | 3846 | || (TARGET_E500_DOUBLE && mode != DDmode))) |
9ebbca7d | 3847 | && (TARGET_POWERPC64 || mode != DImode) |
001b9eb6 | 3848 | && !avoiding_indexed_address_p (mode) |
efc05e3c PB |
3849 | && mode != TImode |
3850 | && mode != TFmode | |
3851 | && mode != TDmode) | |
9ebbca7d GK |
3852 | { |
3853 | return gen_rtx_PLUS (Pmode, XEXP (x, 0), | |
3854 | force_reg (Pmode, force_operand (XEXP (x, 1), 0))); | |
3855 | } | |
0ac081f6 AH |
3856 | else if (ALTIVEC_VECTOR_MODE (mode)) |
3857 | { | |
3858 | rtx reg; | |
3859 | ||
3860 | /* Make sure both operands are registers. */ | |
3861 | if (GET_CODE (x) == PLUS) | |
9f85ed45 | 3862 | return gen_rtx_PLUS (Pmode, force_reg (Pmode, XEXP (x, 0)), |
0ac081f6 AH |
3863 | force_reg (Pmode, XEXP (x, 1))); |
3864 | ||
3865 | reg = force_reg (Pmode, x); | |
3866 | return reg; | |
3867 | } | |
4d4cbc0e | 3868 | else if (SPE_VECTOR_MODE (mode) |
17caeff2 | 3869 | || (TARGET_E500_DOUBLE && (mode == DFmode || mode == TFmode |
7393f7f8 | 3870 | || mode == DDmode || mode == TDmode |
54b695e7 | 3871 | || mode == DImode))) |
a3170dc6 | 3872 | { |
54b695e7 AH |
3873 | if (mode == DImode) |
3874 | return NULL_RTX; | |
a3170dc6 AH |
3875 | /* We accept [reg + reg] and [reg + OFFSET]. */ |
3876 | ||
3877 | if (GET_CODE (x) == PLUS) | |
61dd226f NF |
3878 | { |
3879 | rtx op1 = XEXP (x, 0); | |
3880 | rtx op2 = XEXP (x, 1); | |
3881 | rtx y; | |
3882 | ||
3883 | op1 = force_reg (Pmode, op1); | |
3884 | ||
3885 | if (GET_CODE (op2) != REG | |
3886 | && (GET_CODE (op2) != CONST_INT | |
3887 | || !SPE_CONST_OFFSET_OK (INTVAL (op2)) | |
3888 | || (GET_MODE_SIZE (mode) > 8 | |
3889 | && !SPE_CONST_OFFSET_OK (INTVAL (op2) + 8)))) | |
3890 | op2 = force_reg (Pmode, op2); | |
3891 | ||
3892 | /* We can't always do [reg + reg] for these, because [reg + | |
3893 | reg + offset] is not a legitimate addressing mode. */ | |
3894 | y = gen_rtx_PLUS (Pmode, op1, op2); | |
3895 | ||
4f011e1e | 3896 | if ((GET_MODE_SIZE (mode) > 8 || mode == DDmode) && REG_P (op2)) |
61dd226f NF |
3897 | return force_reg (Pmode, y); |
3898 | else | |
3899 | return y; | |
3900 | } | |
a3170dc6 AH |
3901 | |
3902 | return force_reg (Pmode, x); | |
3903 | } | |
f1384257 AM |
3904 | else if (TARGET_ELF |
3905 | && TARGET_32BIT | |
3906 | && TARGET_NO_TOC | |
3907 | && ! flag_pic | |
9ebbca7d | 3908 | && GET_CODE (x) != CONST_INT |
f676971a | 3909 | && GET_CODE (x) != CONST_DOUBLE |
9ebbca7d | 3910 | && CONSTANT_P (x) |
6ac7bf2c GK |
3911 | && GET_MODE_NUNITS (mode) == 1 |
3912 | && (GET_MODE_BITSIZE (mode) <= 32 | |
696e45ba | 3913 | || ((TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT) |
4d4447b5 | 3914 | && (mode == DFmode || mode == DDmode)))) |
9ebbca7d GK |
3915 | { |
3916 | rtx reg = gen_reg_rtx (Pmode); | |
8a1977f3 GK |
3917 | emit_insn (gen_elf_high (reg, x)); |
3918 | return gen_rtx_LO_SUM (Pmode, reg, x); | |
9ebbca7d | 3919 | } |
ee890fe2 SS |
3920 | else if (TARGET_MACHO && TARGET_32BIT && TARGET_NO_TOC |
3921 | && ! flag_pic | |
ab82a49f AP |
3922 | #if TARGET_MACHO |
3923 | && ! MACHO_DYNAMIC_NO_PIC_P | |
3924 | #endif | |
ee890fe2 | 3925 | && GET_CODE (x) != CONST_INT |
f676971a | 3926 | && GET_CODE (x) != CONST_DOUBLE |
ee890fe2 | 3927 | && CONSTANT_P (x) |
506a7bc8 | 3928 | && GET_MODE_NUNITS (mode) == 1 |
696e45ba | 3929 | && ((TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT) |
4d4447b5 | 3930 | || (mode != DFmode && mode != DDmode)) |
f676971a | 3931 | && mode != DImode |
ee890fe2 SS |
3932 | && mode != TImode) |
3933 | { | |
3934 | rtx reg = gen_reg_rtx (Pmode); | |
8a1977f3 GK |
3935 | emit_insn (gen_macho_high (reg, x)); |
3936 | return gen_rtx_LO_SUM (Pmode, reg, x); | |
ee890fe2 | 3937 | } |
f676971a | 3938 | else if (TARGET_TOC |
0cdc04e8 | 3939 | && GET_CODE (x) == SYMBOL_REF |
4d588c14 | 3940 | && constant_pool_expr_p (x) |
a9098fd0 | 3941 | && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x), Pmode)) |
9ebbca7d GK |
3942 | { |
3943 | return create_TOC_reference (x); | |
3944 | } | |
3945 | else | |
3946 | return NULL_RTX; | |
3947 | } | |
258bfae2 | 3948 | |
fdbe66f2 | 3949 | /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL. |
c973d557 JJ |
3950 | We need to emit DTP-relative relocations. */ |
3951 | ||
fdbe66f2 | 3952 | static void |
c973d557 JJ |
3953 | rs6000_output_dwarf_dtprel (FILE *file, int size, rtx x) |
3954 | { | |
3955 | switch (size) | |
3956 | { | |
3957 | case 4: | |
3958 | fputs ("\t.long\t", file); | |
3959 | break; | |
3960 | case 8: | |
3961 | fputs (DOUBLE_INT_ASM_OP, file); | |
3962 | break; | |
3963 | default: | |
37409796 | 3964 | gcc_unreachable (); |
c973d557 JJ |
3965 | } |
3966 | output_addr_const (file, x); | |
3967 | fputs ("@dtprel+0x8000", file); | |
3968 | } | |
3969 | ||
c4501e62 JJ |
3970 | /* Construct the SYMBOL_REF for the tls_get_addr function. */ |
3971 | ||
3972 | static GTY(()) rtx rs6000_tls_symbol; | |
3973 | static rtx | |
863d938c | 3974 | rs6000_tls_get_addr (void) |
c4501e62 JJ |
3975 | { |
3976 | if (!rs6000_tls_symbol) | |
3977 | rs6000_tls_symbol = init_one_libfunc ("__tls_get_addr"); | |
3978 | ||
3979 | return rs6000_tls_symbol; | |
3980 | } | |
3981 | ||
3982 | /* Construct the SYMBOL_REF for TLS GOT references. */ | |
3983 | ||
3984 | static GTY(()) rtx rs6000_got_symbol; | |
3985 | static rtx | |
863d938c | 3986 | rs6000_got_sym (void) |
c4501e62 JJ |
3987 | { |
3988 | if (!rs6000_got_symbol) | |
3989 | { | |
3990 | rs6000_got_symbol = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_"); | |
3991 | SYMBOL_REF_FLAGS (rs6000_got_symbol) |= SYMBOL_FLAG_LOCAL; | |
3992 | SYMBOL_REF_FLAGS (rs6000_got_symbol) |= SYMBOL_FLAG_EXTERNAL; | |
f676971a | 3993 | } |
c4501e62 JJ |
3994 | |
3995 | return rs6000_got_symbol; | |
3996 | } | |
3997 | ||
3998 | /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute | |
3999 | this (thread-local) address. */ | |
4000 | ||
4001 | static rtx | |
a2369ed3 | 4002 | rs6000_legitimize_tls_address (rtx addr, enum tls_model model) |
c4501e62 JJ |
4003 | { |
4004 | rtx dest, insn; | |
4005 | ||
4006 | dest = gen_reg_rtx (Pmode); | |
4007 | if (model == TLS_MODEL_LOCAL_EXEC && rs6000_tls_size == 16) | |
4008 | { | |
4009 | rtx tlsreg; | |
4010 | ||
4011 | if (TARGET_64BIT) | |
4012 | { | |
4013 | tlsreg = gen_rtx_REG (Pmode, 13); | |
4014 | insn = gen_tls_tprel_64 (dest, tlsreg, addr); | |
4015 | } | |
4016 | else | |
4017 | { | |
4018 | tlsreg = gen_rtx_REG (Pmode, 2); | |
4019 | insn = gen_tls_tprel_32 (dest, tlsreg, addr); | |
4020 | } | |
4021 | emit_insn (insn); | |
4022 | } | |
4023 | else if (model == TLS_MODEL_LOCAL_EXEC && rs6000_tls_size == 32) | |
4024 | { | |
4025 | rtx tlsreg, tmp; | |
4026 | ||
4027 | tmp = gen_reg_rtx (Pmode); | |
4028 | if (TARGET_64BIT) | |
4029 | { | |
4030 | tlsreg = gen_rtx_REG (Pmode, 13); | |
4031 | insn = gen_tls_tprel_ha_64 (tmp, tlsreg, addr); | |
4032 | } | |
4033 | else | |
4034 | { | |
4035 | tlsreg = gen_rtx_REG (Pmode, 2); | |
4036 | insn = gen_tls_tprel_ha_32 (tmp, tlsreg, addr); | |
4037 | } | |
4038 | emit_insn (insn); | |
4039 | if (TARGET_64BIT) | |
4040 | insn = gen_tls_tprel_lo_64 (dest, tmp, addr); | |
4041 | else | |
4042 | insn = gen_tls_tprel_lo_32 (dest, tmp, addr); | |
4043 | emit_insn (insn); | |
4044 | } | |
4045 | else | |
4046 | { | |
4047 | rtx r3, got, tga, tmp1, tmp2, eqv; | |
4048 | ||
4fed8f8f AM |
4049 | /* We currently use relocations like @got@tlsgd for tls, which |
4050 | means the linker will handle allocation of tls entries, placing | |
4051 | them in the .got section. So use a pointer to the .got section, | |
4052 | not one to secondary TOC sections used by 64-bit -mminimal-toc, | |
4053 | or to secondary GOT sections used by 32-bit -fPIC. */ | |
c4501e62 | 4054 | if (TARGET_64BIT) |
972f427b | 4055 | got = gen_rtx_REG (Pmode, 2); |
c4501e62 JJ |
4056 | else |
4057 | { | |
4058 | if (flag_pic == 1) | |
4059 | got = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM); | |
4060 | else | |
4061 | { | |
4062 | rtx gsym = rs6000_got_sym (); | |
4063 | got = gen_reg_rtx (Pmode); | |
4064 | if (flag_pic == 0) | |
4065 | rs6000_emit_move (got, gsym, Pmode); | |
4066 | else | |
4067 | { | |
e65a3857 | 4068 | rtx tmp3, mem; |
c4501e62 JJ |
4069 | rtx first, last; |
4070 | ||
c4501e62 JJ |
4071 | tmp1 = gen_reg_rtx (Pmode); |
4072 | tmp2 = gen_reg_rtx (Pmode); | |
4073 | tmp3 = gen_reg_rtx (Pmode); | |
542a8afa | 4074 | mem = gen_const_mem (Pmode, tmp1); |
c4501e62 | 4075 | |
e65a3857 DE |
4076 | first = emit_insn (gen_load_toc_v4_PIC_1b (gsym)); |
4077 | emit_move_insn (tmp1, | |
1de43f85 | 4078 | gen_rtx_REG (Pmode, LR_REGNO)); |
c4501e62 JJ |
4079 | emit_move_insn (tmp2, mem); |
4080 | emit_insn (gen_addsi3 (tmp3, tmp1, tmp2)); | |
4081 | last = emit_move_insn (got, tmp3); | |
bd94cb6e | 4082 | set_unique_reg_note (last, REG_EQUAL, gsym); |
c4501e62 JJ |
4083 | } |
4084 | } | |
4085 | } | |
4086 | ||
4087 | if (model == TLS_MODEL_GLOBAL_DYNAMIC) | |
4088 | { | |
4089 | r3 = gen_rtx_REG (Pmode, 3); | |
02135bc1 SB |
4090 | tga = rs6000_tls_get_addr (); |
4091 | ||
4092 | if (DEFAULT_ABI == ABI_AIX && TARGET_64BIT) | |
4093 | insn = gen_tls_gd_aix64 (r3, got, addr, tga, const0_rtx); | |
4094 | else if (DEFAULT_ABI == ABI_AIX && !TARGET_64BIT) | |
4095 | insn = gen_tls_gd_aix32 (r3, got, addr, tga, const0_rtx); | |
4096 | else if (DEFAULT_ABI == ABI_V4) | |
4097 | insn = gen_tls_gd_sysvsi (r3, got, addr, tga, const0_rtx); | |
c4501e62 | 4098 | else |
02135bc1 SB |
4099 | gcc_unreachable (); |
4100 | ||
c4501e62 | 4101 | start_sequence (); |
c4501e62 | 4102 | insn = emit_call_insn (insn); |
becfd6e5 | 4103 | RTL_CONST_CALL_P (insn) = 1; |
c4501e62 | 4104 | use_reg (&CALL_INSN_FUNCTION_USAGE (insn), r3); |
d161cb2d AM |
4105 | if (DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT && flag_pic) |
4106 | use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx); | |
c4501e62 JJ |
4107 | insn = get_insns (); |
4108 | end_sequence (); | |
4109 | emit_libcall_block (insn, dest, r3, addr); | |
4110 | } | |
4111 | else if (model == TLS_MODEL_LOCAL_DYNAMIC) | |
4112 | { | |
4113 | r3 = gen_rtx_REG (Pmode, 3); | |
02135bc1 SB |
4114 | tga = rs6000_tls_get_addr (); |
4115 | ||
4116 | if (DEFAULT_ABI == ABI_AIX && TARGET_64BIT) | |
4117 | insn = gen_tls_ld_aix64 (r3, got, tga, const0_rtx); | |
4118 | else if (DEFAULT_ABI == ABI_AIX && !TARGET_64BIT) | |
4119 | insn = gen_tls_ld_aix32 (r3, got, tga, const0_rtx); | |
4120 | else if (DEFAULT_ABI == ABI_V4) | |
4121 | insn = gen_tls_ld_sysvsi (r3, got, tga, const0_rtx); | |
c4501e62 | 4122 | else |
02135bc1 SB |
4123 | gcc_unreachable (); |
4124 | ||
c4501e62 | 4125 | start_sequence (); |
c4501e62 | 4126 | insn = emit_call_insn (insn); |
becfd6e5 | 4127 | RTL_CONST_CALL_P (insn) = 1; |
c4501e62 | 4128 | use_reg (&CALL_INSN_FUNCTION_USAGE (insn), r3); |
d161cb2d AM |
4129 | if (DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT && flag_pic) |
4130 | use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx); | |
c4501e62 JJ |
4131 | insn = get_insns (); |
4132 | end_sequence (); | |
4133 | tmp1 = gen_reg_rtx (Pmode); | |
4134 | eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), | |
4135 | UNSPEC_TLSLD); | |
4136 | emit_libcall_block (insn, tmp1, r3, eqv); | |
4137 | if (rs6000_tls_size == 16) | |
4138 | { | |
4139 | if (TARGET_64BIT) | |
4140 | insn = gen_tls_dtprel_64 (dest, tmp1, addr); | |
4141 | else | |
4142 | insn = gen_tls_dtprel_32 (dest, tmp1, addr); | |
4143 | } | |
4144 | else if (rs6000_tls_size == 32) | |
4145 | { | |
4146 | tmp2 = gen_reg_rtx (Pmode); | |
4147 | if (TARGET_64BIT) | |
4148 | insn = gen_tls_dtprel_ha_64 (tmp2, tmp1, addr); | |
4149 | else | |
4150 | insn = gen_tls_dtprel_ha_32 (tmp2, tmp1, addr); | |
4151 | emit_insn (insn); | |
4152 | if (TARGET_64BIT) | |
4153 | insn = gen_tls_dtprel_lo_64 (dest, tmp2, addr); | |
4154 | else | |
4155 | insn = gen_tls_dtprel_lo_32 (dest, tmp2, addr); | |
4156 | } | |
4157 | else | |
4158 | { | |
4159 | tmp2 = gen_reg_rtx (Pmode); | |
4160 | if (TARGET_64BIT) | |
4161 | insn = gen_tls_got_dtprel_64 (tmp2, got, addr); | |
4162 | else | |
4163 | insn = gen_tls_got_dtprel_32 (tmp2, got, addr); | |
4164 | emit_insn (insn); | |
4165 | insn = gen_rtx_SET (Pmode, dest, | |
4166 | gen_rtx_PLUS (Pmode, tmp2, tmp1)); | |
4167 | } | |
4168 | emit_insn (insn); | |
4169 | } | |
4170 | else | |
4171 | { | |
a7b376ee | 4172 | /* IE, or 64-bit offset LE. */ |
c4501e62 JJ |
4173 | tmp2 = gen_reg_rtx (Pmode); |
4174 | if (TARGET_64BIT) | |
4175 | insn = gen_tls_got_tprel_64 (tmp2, got, addr); | |
4176 | else | |
4177 | insn = gen_tls_got_tprel_32 (tmp2, got, addr); | |
4178 | emit_insn (insn); | |
4179 | if (TARGET_64BIT) | |
4180 | insn = gen_tls_tls_64 (dest, tmp2, addr); | |
4181 | else | |
4182 | insn = gen_tls_tls_32 (dest, tmp2, addr); | |
4183 | emit_insn (insn); | |
4184 | } | |
4185 | } | |
4186 | ||
4187 | return dest; | |
4188 | } | |
4189 | ||
c4501e62 JJ |
4190 | /* Return 1 if X contains a thread-local symbol. */ |
4191 | ||
4192 | bool | |
a2369ed3 | 4193 | rs6000_tls_referenced_p (rtx x) |
c4501e62 | 4194 | { |
cd413cab AP |
4195 | if (! TARGET_HAVE_TLS) |
4196 | return false; | |
4197 | ||
c4501e62 JJ |
4198 | return for_each_rtx (&x, &rs6000_tls_symbol_ref_1, 0); |
4199 | } | |
4200 | ||
4201 | /* Return 1 if *X is a thread-local symbol. This is the same as | |
4202 | rs6000_tls_symbol_ref except for the type of the unused argument. */ | |
4203 | ||
9390387d | 4204 | static int |
a2369ed3 | 4205 | rs6000_tls_symbol_ref_1 (rtx *x, void *data ATTRIBUTE_UNUSED) |
c4501e62 JJ |
4206 | { |
4207 | return RS6000_SYMBOL_REF_TLS_P (*x); | |
4208 | } | |
4209 | ||
24ea750e DJ |
4210 | /* The convention appears to be to define this wherever it is used. |
4211 | With legitimize_reload_address now defined here, REG_MODE_OK_FOR_BASE_P | |
4212 | is now used here. */ | |
4213 | #ifndef REG_MODE_OK_FOR_BASE_P | |
4214 | #define REG_MODE_OK_FOR_BASE_P(REGNO, MODE) REG_OK_FOR_BASE_P (REGNO) | |
4215 | #endif | |
4216 | ||
4217 | /* Our implementation of LEGITIMIZE_RELOAD_ADDRESS. Returns a value to | |
4218 | replace the input X, or the original X if no replacement is called for. | |
4219 | The output parameter *WIN is 1 if the calling macro should goto WIN, | |
4220 | 0 if it should not. | |
4221 | ||
4222 | For RS/6000, we wish to handle large displacements off a base | |
4223 | register by splitting the addend across an addiu/addis and the mem insn. | |
4224 | This cuts number of extra insns needed from 3 to 1. | |
4225 | ||
4226 | On Darwin, we use this to generate code for floating point constants. | |
4227 | A movsf_low is generated so we wind up with 2 instructions rather than 3. | |
08a6a74b RS |
4228 | The Darwin code is inside #if TARGET_MACHO because only then are the |
4229 | machopic_* functions defined. */ | |
24ea750e | 4230 | rtx |
f676971a | 4231 | rs6000_legitimize_reload_address (rtx x, enum machine_mode mode, |
c4ad648e AM |
4232 | int opnum, int type, |
4233 | int ind_levels ATTRIBUTE_UNUSED, int *win) | |
24ea750e | 4234 | { |
f676971a | 4235 | /* We must recognize output that we have already generated ourselves. */ |
24ea750e DJ |
4236 | if (GET_CODE (x) == PLUS |
4237 | && GET_CODE (XEXP (x, 0)) == PLUS | |
4238 | && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG | |
4239 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT | |
4240 | && GET_CODE (XEXP (x, 1)) == CONST_INT) | |
4241 | { | |
4242 | push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL, | |
c4ad648e AM |
4243 | BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0, |
4244 | opnum, (enum reload_type)type); | |
24ea750e DJ |
4245 | *win = 1; |
4246 | return x; | |
4247 | } | |
3deb2758 | 4248 | |
24ea750e DJ |
4249 | #if TARGET_MACHO |
4250 | if (DEFAULT_ABI == ABI_DARWIN && flag_pic | |
4251 | && GET_CODE (x) == LO_SUM | |
4252 | && GET_CODE (XEXP (x, 0)) == PLUS | |
4253 | && XEXP (XEXP (x, 0), 0) == pic_offset_table_rtx | |
4254 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == HIGH | |
24ea750e | 4255 | && XEXP (XEXP (XEXP (x, 0), 1), 0) == XEXP (x, 1) |
08a6a74b | 4256 | && machopic_operand_p (XEXP (x, 1))) |
24ea750e DJ |
4257 | { |
4258 | /* Result of previous invocation of this function on Darwin | |
6f317ef3 | 4259 | floating point constant. */ |
24ea750e | 4260 | push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL, |
c4ad648e AM |
4261 | BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, |
4262 | opnum, (enum reload_type)type); | |
24ea750e DJ |
4263 | *win = 1; |
4264 | return x; | |
4265 | } | |
4266 | #endif | |
4937d02d DE |
4267 | |
4268 | /* Force ld/std non-word aligned offset into base register by wrapping | |
4269 | in offset 0. */ | |
4270 | if (GET_CODE (x) == PLUS | |
4271 | && GET_CODE (XEXP (x, 0)) == REG | |
4272 | && REGNO (XEXP (x, 0)) < 32 | |
4273 | && REG_MODE_OK_FOR_BASE_P (XEXP (x, 0), mode) | |
4274 | && GET_CODE (XEXP (x, 1)) == CONST_INT | |
4275 | && (INTVAL (XEXP (x, 1)) & 3) != 0 | |
78796ad5 | 4276 | && !ALTIVEC_VECTOR_MODE (mode) |
4937d02d DE |
4277 | && GET_MODE_SIZE (mode) >= UNITS_PER_WORD |
4278 | && TARGET_POWERPC64) | |
4279 | { | |
4280 | x = gen_rtx_PLUS (GET_MODE (x), x, GEN_INT (0)); | |
4281 | push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL, | |
4282 | BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0, | |
4283 | opnum, (enum reload_type) type); | |
4284 | *win = 1; | |
4285 | return x; | |
4286 | } | |
4287 | ||
24ea750e DJ |
4288 | if (GET_CODE (x) == PLUS |
4289 | && GET_CODE (XEXP (x, 0)) == REG | |
4290 | && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER | |
4291 | && REG_MODE_OK_FOR_BASE_P (XEXP (x, 0), mode) | |
78c875e8 | 4292 | && GET_CODE (XEXP (x, 1)) == CONST_INT |
93638d7a | 4293 | && !SPE_VECTOR_MODE (mode) |
17caeff2 | 4294 | && !(TARGET_E500_DOUBLE && (mode == DFmode || mode == TFmode |
4d4447b5 | 4295 | || mode == DDmode || mode == TDmode |
54b695e7 | 4296 | || mode == DImode)) |
78c875e8 | 4297 | && !ALTIVEC_VECTOR_MODE (mode)) |
24ea750e DJ |
4298 | { |
4299 | HOST_WIDE_INT val = INTVAL (XEXP (x, 1)); | |
4300 | HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000; | |
4301 | HOST_WIDE_INT high | |
c4ad648e | 4302 | = (((val - low) & 0xffffffff) ^ 0x80000000) - 0x80000000; |
24ea750e DJ |
4303 | |
4304 | /* Check for 32-bit overflow. */ | |
4305 | if (high + low != val) | |
c4ad648e | 4306 | { |
24ea750e DJ |
4307 | *win = 0; |
4308 | return x; | |
4309 | } | |
4310 | ||
4311 | /* Reload the high part into a base reg; leave the low part | |
c4ad648e | 4312 | in the mem directly. */ |
24ea750e DJ |
4313 | |
4314 | x = gen_rtx_PLUS (GET_MODE (x), | |
c4ad648e AM |
4315 | gen_rtx_PLUS (GET_MODE (x), XEXP (x, 0), |
4316 | GEN_INT (high)), | |
4317 | GEN_INT (low)); | |
24ea750e DJ |
4318 | |
4319 | push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL, | |
c4ad648e AM |
4320 | BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0, |
4321 | opnum, (enum reload_type)type); | |
24ea750e DJ |
4322 | *win = 1; |
4323 | return x; | |
4324 | } | |
4937d02d | 4325 | |
24ea750e | 4326 | if (GET_CODE (x) == SYMBOL_REF |
69ef87e2 | 4327 | && !ALTIVEC_VECTOR_MODE (mode) |
1650e3f5 | 4328 | && !SPE_VECTOR_MODE (mode) |
8308679f DE |
4329 | #if TARGET_MACHO |
4330 | && DEFAULT_ABI == ABI_DARWIN | |
a29077da | 4331 | && (flag_pic || MACHO_DYNAMIC_NO_PIC_P) |
8308679f DE |
4332 | #else |
4333 | && DEFAULT_ABI == ABI_V4 | |
4334 | && !flag_pic | |
4335 | #endif | |
7393f7f8 | 4336 | /* Don't do this for TFmode or TDmode, since the result isn't offsettable. |
4d4447b5 | 4337 | The same goes for DImode without 64-bit gprs and DFmode and DDmode |
7b5d92b2 | 4338 | without fprs. */ |
0d8c1c97 | 4339 | && mode != TFmode |
7393f7f8 | 4340 | && mode != TDmode |
7b5d92b2 | 4341 | && (mode != DImode || TARGET_POWERPC64) |
4d4447b5 | 4342 | && ((mode != DFmode && mode != DDmode) || TARGET_POWERPC64 |
696e45ba | 4343 | || (TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT))) |
24ea750e | 4344 | { |
8308679f | 4345 | #if TARGET_MACHO |
a29077da GK |
4346 | if (flag_pic) |
4347 | { | |
08a6a74b | 4348 | rtx offset = machopic_gen_offset (x); |
a29077da GK |
4349 | x = gen_rtx_LO_SUM (GET_MODE (x), |
4350 | gen_rtx_PLUS (Pmode, pic_offset_table_rtx, | |
4351 | gen_rtx_HIGH (Pmode, offset)), offset); | |
4352 | } | |
4353 | else | |
8308679f | 4354 | #endif |
a29077da | 4355 | x = gen_rtx_LO_SUM (GET_MODE (x), |
c4ad648e | 4356 | gen_rtx_HIGH (Pmode, x), x); |
a29077da | 4357 | |
24ea750e | 4358 | push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL, |
a29077da GK |
4359 | BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, |
4360 | opnum, (enum reload_type)type); | |
24ea750e DJ |
4361 | *win = 1; |
4362 | return x; | |
4363 | } | |
4937d02d | 4364 | |
dec1f3aa DE |
4365 | /* Reload an offset address wrapped by an AND that represents the |
4366 | masking of the lower bits. Strip the outer AND and let reload | |
4367 | convert the offset address into an indirect address. */ | |
4368 | if (TARGET_ALTIVEC | |
4369 | && ALTIVEC_VECTOR_MODE (mode) | |
4370 | && GET_CODE (x) == AND | |
4371 | && GET_CODE (XEXP (x, 0)) == PLUS | |
4372 | && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG | |
4373 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT | |
4374 | && GET_CODE (XEXP (x, 1)) == CONST_INT | |
4375 | && INTVAL (XEXP (x, 1)) == -16) | |
4376 | { | |
4377 | x = XEXP (x, 0); | |
4378 | *win = 1; | |
4379 | return x; | |
4380 | } | |
4381 | ||
24ea750e | 4382 | if (TARGET_TOC |
0cdc04e8 | 4383 | && GET_CODE (x) == SYMBOL_REF |
4d588c14 | 4384 | && constant_pool_expr_p (x) |
c1f11548 | 4385 | && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x), mode)) |
24ea750e | 4386 | { |
194c524a | 4387 | x = create_TOC_reference (x); |
24ea750e DJ |
4388 | *win = 1; |
4389 | return x; | |
4390 | } | |
4391 | *win = 0; | |
4392 | return x; | |
f676971a | 4393 | } |
24ea750e | 4394 | |
258bfae2 FS |
4395 | /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression |
4396 | that is a valid memory address for an instruction. | |
4397 | The MODE argument is the machine mode for the MEM expression | |
4398 | that wants to use this address. | |
4399 | ||
4400 | On the RS/6000, there are four valid address: a SYMBOL_REF that | |
4401 | refers to a constant pool entry of an address (or the sum of it | |
4402 | plus a constant), a short (16-bit signed) constant plus a register, | |
4403 | the sum of two registers, or a register indirect, possibly with an | |
4d4447b5 PB |
4404 | auto-increment. For DFmode, DDmode and DImode with a constant plus |
4405 | register, we must ensure that both words are addressable or PowerPC64 | |
4406 | with offset word aligned. | |
258bfae2 | 4407 | |
4d4447b5 | 4408 | For modes spanning multiple registers (DFmode and DDmode in 32-bit GPRs, |
7393f7f8 BE |
4409 | 32-bit DImode, TImode, TFmode, TDmode), indexed addressing cannot be used |
4410 | because adjacent memory cells are accessed by adding word-sized offsets | |
258bfae2 FS |
4411 | during assembly output. */ |
4412 | int | |
a2369ed3 | 4413 | rs6000_legitimate_address (enum machine_mode mode, rtx x, int reg_ok_strict) |
258bfae2 | 4414 | { |
850e8d3d DN |
4415 | /* If this is an unaligned stvx/ldvx type address, discard the outer AND. */ |
4416 | if (TARGET_ALTIVEC | |
4417 | && ALTIVEC_VECTOR_MODE (mode) | |
4418 | && GET_CODE (x) == AND | |
4419 | && GET_CODE (XEXP (x, 1)) == CONST_INT | |
4420 | && INTVAL (XEXP (x, 1)) == -16) | |
4421 | x = XEXP (x, 0); | |
4422 | ||
c4501e62 JJ |
4423 | if (RS6000_SYMBOL_REF_TLS_P (x)) |
4424 | return 0; | |
4d588c14 | 4425 | if (legitimate_indirect_address_p (x, reg_ok_strict)) |
258bfae2 FS |
4426 | return 1; |
4427 | if ((GET_CODE (x) == PRE_INC || GET_CODE (x) == PRE_DEC) | |
0d6d6892 | 4428 | && !ALTIVEC_VECTOR_MODE (mode) |
a3170dc6 | 4429 | && !SPE_VECTOR_MODE (mode) |
429ec7dc | 4430 | && mode != TFmode |
7393f7f8 | 4431 | && mode != TDmode |
54b695e7 | 4432 | /* Restrict addressing for DI because of our SUBREG hackery. */ |
4d4447b5 PB |
4433 | && !(TARGET_E500_DOUBLE |
4434 | && (mode == DFmode || mode == DDmode || mode == DImode)) | |
258bfae2 | 4435 | && TARGET_UPDATE |
4d588c14 | 4436 | && legitimate_indirect_address_p (XEXP (x, 0), reg_ok_strict)) |
258bfae2 | 4437 | return 1; |
d04b6e6e | 4438 | if (legitimate_small_data_p (mode, x)) |
258bfae2 | 4439 | return 1; |
4d588c14 | 4440 | if (legitimate_constant_pool_address_p (x)) |
258bfae2 FS |
4441 | return 1; |
4442 | /* If not REG_OK_STRICT (before reload) let pass any stack offset. */ | |
4443 | if (! reg_ok_strict | |
4444 | && GET_CODE (x) == PLUS | |
4445 | && GET_CODE (XEXP (x, 0)) == REG | |
708d2456 | 4446 | && (XEXP (x, 0) == virtual_stack_vars_rtx |
c4ad648e | 4447 | || XEXP (x, 0) == arg_pointer_rtx) |
258bfae2 FS |
4448 | && GET_CODE (XEXP (x, 1)) == CONST_INT) |
4449 | return 1; | |
76d2b81d | 4450 | if (rs6000_legitimate_offset_address_p (mode, x, reg_ok_strict)) |
258bfae2 FS |
4451 | return 1; |
4452 | if (mode != TImode | |
76d2b81d | 4453 | && mode != TFmode |
7393f7f8 | 4454 | && mode != TDmode |
a3170dc6 AH |
4455 | && ((TARGET_HARD_FLOAT && TARGET_FPRS) |
4456 | || TARGET_POWERPC64 | |
4f011e1e JM |
4457 | || (mode != DFmode && mode != DDmode) |
4458 | || (TARGET_E500_DOUBLE && mode != DDmode)) | |
258bfae2 | 4459 | && (TARGET_POWERPC64 || mode != DImode) |
001b9eb6 | 4460 | && !avoiding_indexed_address_p (mode) |
4d588c14 | 4461 | && legitimate_indexed_address_p (x, reg_ok_strict)) |
258bfae2 | 4462 | return 1; |
6fb5fa3c DB |
4463 | if (GET_CODE (x) == PRE_MODIFY |
4464 | && mode != TImode | |
4465 | && mode != TFmode | |
4466 | && mode != TDmode | |
696e45ba | 4467 | && ((TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT) |
6fb5fa3c | 4468 | || TARGET_POWERPC64 |
4d4447b5 | 4469 | || ((mode != DFmode && mode != DDmode) || TARGET_E500_DOUBLE)) |
6fb5fa3c DB |
4470 | && (TARGET_POWERPC64 || mode != DImode) |
4471 | && !ALTIVEC_VECTOR_MODE (mode) | |
4472 | && !SPE_VECTOR_MODE (mode) | |
4473 | /* Restrict addressing for DI because of our SUBREG hackery. */ | |
4d4447b5 PB |
4474 | && !(TARGET_E500_DOUBLE |
4475 | && (mode == DFmode || mode == DDmode || mode == DImode)) | |
6fb5fa3c DB |
4476 | && TARGET_UPDATE |
4477 | && legitimate_indirect_address_p (XEXP (x, 0), reg_ok_strict) | |
4478 | && (rs6000_legitimate_offset_address_p (mode, XEXP (x, 1), reg_ok_strict) | |
001b9eb6 PH |
4479 | || (!avoiding_indexed_address_p (mode) |
4480 | && legitimate_indexed_address_p (XEXP (x, 1), reg_ok_strict))) | |
6fb5fa3c DB |
4481 | && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0))) |
4482 | return 1; | |
4d588c14 | 4483 | if (legitimate_lo_sum_address_p (mode, x, reg_ok_strict)) |
258bfae2 FS |
4484 | return 1; |
4485 | return 0; | |
4486 | } | |
4d588c14 RH |
4487 | |
4488 | /* Go to LABEL if ADDR (a legitimate address expression) | |
4489 | has an effect that depends on the machine mode it is used for. | |
4490 | ||
4491 | On the RS/6000 this is true of all integral offsets (since AltiVec | |
4492 | modes don't allow them) or is a pre-increment or decrement. | |
4493 | ||
4494 | ??? Except that due to conceptual problems in offsettable_address_p | |
4495 | we can't really report the problems of integral offsets. So leave | |
f676971a | 4496 | this assuming that the adjustable offset must be valid for the |
4d588c14 RH |
4497 | sub-words of a TFmode operand, which is what we had before. */ |
4498 | ||
4499 | bool | |
a2369ed3 | 4500 | rs6000_mode_dependent_address (rtx addr) |
4d588c14 RH |
4501 | { |
4502 | switch (GET_CODE (addr)) | |
4503 | { | |
4504 | case PLUS: | |
4505 | if (GET_CODE (XEXP (addr, 1)) == CONST_INT) | |
4506 | { | |
4507 | unsigned HOST_WIDE_INT val = INTVAL (XEXP (addr, 1)); | |
4508 | return val + 12 + 0x8000 >= 0x10000; | |
4509 | } | |
4510 | break; | |
4511 | ||
4512 | case LO_SUM: | |
4513 | return true; | |
4514 | ||
619fe064 | 4515 | /* Auto-increment cases are now treated generically in recog.c. */ |
6fb5fa3c DB |
4516 | case PRE_MODIFY: |
4517 | return TARGET_UPDATE; | |
4d588c14 RH |
4518 | |
4519 | default: | |
4520 | break; | |
4521 | } | |
4522 | ||
4523 | return false; | |
4524 | } | |
d8ecbcdb | 4525 | |
944258eb RS |
4526 | /* Implement FIND_BASE_TERM. */ |
4527 | ||
4528 | rtx | |
4529 | rs6000_find_base_term (rtx op) | |
4530 | { | |
4531 | rtx base, offset; | |
4532 | ||
4533 | split_const (op, &base, &offset); | |
4534 | if (GET_CODE (base) == UNSPEC) | |
4535 | switch (XINT (base, 1)) | |
4536 | { | |
4537 | case UNSPEC_TOCREL: | |
4538 | case UNSPEC_MACHOPIC_OFFSET: | |
4539 | /* OP represents SYM [+ OFFSET] - ANCHOR. SYM is the base term | |
4540 | for aliasing purposes. */ | |
4541 | return XVECEXP (base, 0, 0); | |
4542 | } | |
4543 | ||
4544 | return op; | |
4545 | } | |
4546 | ||
d04b6e6e EB |
4547 | /* More elaborate version of recog's offsettable_memref_p predicate |
4548 | that works around the ??? note of rs6000_mode_dependent_address. | |
4549 | In particular it accepts | |
4550 | ||
4551 | (mem:DI (plus:SI (reg/f:SI 31 31) (const_int 32760 [0x7ff8]))) | |
4552 | ||
4553 | in 32-bit mode, that the recog predicate rejects. */ | |
4554 | ||
4555 | bool | |
4556 | rs6000_offsettable_memref_p (rtx op) | |
4557 | { | |
4558 | if (!MEM_P (op)) | |
4559 | return false; | |
4560 | ||
4561 | /* First mimic offsettable_memref_p. */ | |
4562 | if (offsettable_address_p (1, GET_MODE (op), XEXP (op, 0))) | |
4563 | return true; | |
4564 | ||
4565 | /* offsettable_address_p invokes rs6000_mode_dependent_address, but | |
4566 | the latter predicate knows nothing about the mode of the memory | |
4567 | reference and, therefore, assumes that it is the largest supported | |
4568 | mode (TFmode). As a consequence, legitimate offsettable memory | |
4569 | references are rejected. rs6000_legitimate_offset_address_p contains | |
4570 | the correct logic for the PLUS case of rs6000_mode_dependent_address. */ | |
4571 | return rs6000_legitimate_offset_address_p (GET_MODE (op), XEXP (op, 0), 1); | |
4572 | } | |
4573 | ||
d8ecbcdb AH |
4574 | /* Return number of consecutive hard regs needed starting at reg REGNO |
4575 | to hold something of mode MODE. | |
4576 | This is ordinarily the length in words of a value of mode MODE | |
4577 | but can be less for certain modes in special long registers. | |
4578 | ||
4579 | For the SPE, GPRs are 64 bits but only 32 bits are visible in | |
4580 | scalar instructions. The upper 32 bits are only available to the | |
4581 | SIMD instructions. | |
4582 | ||
4583 | POWER and PowerPC GPRs hold 32 bits worth; | |
4584 | PowerPC64 GPRs and FPRs point register holds 64 bits worth. */ | |
4585 | ||
4586 | int | |
4587 | rs6000_hard_regno_nregs (int regno, enum machine_mode mode) | |
4588 | { | |
4589 | if (FP_REGNO_P (regno)) | |
4590 | return (GET_MODE_SIZE (mode) + UNITS_PER_FP_WORD - 1) / UNITS_PER_FP_WORD; | |
4591 | ||
4592 | if (SPE_SIMD_REGNO_P (regno) && TARGET_SPE && SPE_VECTOR_MODE (mode)) | |
4593 | return (GET_MODE_SIZE (mode) + UNITS_PER_SPE_WORD - 1) / UNITS_PER_SPE_WORD; | |
4594 | ||
4595 | if (ALTIVEC_REGNO_P (regno)) | |
4596 | return | |
4597 | (GET_MODE_SIZE (mode) + UNITS_PER_ALTIVEC_WORD - 1) / UNITS_PER_ALTIVEC_WORD; | |
4598 | ||
8521c414 JM |
4599 | /* The value returned for SCmode in the E500 double case is 2 for |
4600 | ABI compatibility; storing an SCmode value in a single register | |
4601 | would require function_arg and rs6000_spe_function_arg to handle | |
4602 | SCmode so as to pass the value correctly in a pair of | |
4603 | registers. */ | |
4f011e1e JM |
4604 | if (TARGET_E500_DOUBLE && FLOAT_MODE_P (mode) && mode != SCmode |
4605 | && !DECIMAL_FLOAT_MODE_P (mode)) | |
8521c414 JM |
4606 | return (GET_MODE_SIZE (mode) + UNITS_PER_FP_WORD - 1) / UNITS_PER_FP_WORD; |
4607 | ||
d8ecbcdb AH |
4608 | return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD; |
4609 | } | |
2aa4498c AH |
4610 | |
4611 | /* Change register usage conditional on target flags. */ | |
4612 | void | |
4613 | rs6000_conditional_register_usage (void) | |
4614 | { | |
4615 | int i; | |
4616 | ||
4617 | /* Set MQ register fixed (already call_used) if not POWER | |
4618 | architecture (RIOS1, RIOS2, RSC, and PPC601) so that it will not | |
4619 | be allocated. */ | |
4620 | if (! TARGET_POWER) | |
4621 | fixed_regs[64] = 1; | |
4622 | ||
7c9ac5c0 | 4623 | /* 64-bit AIX and Linux reserve GPR13 for thread-private data. */ |
2aa4498c AH |
4624 | if (TARGET_64BIT) |
4625 | fixed_regs[13] = call_used_regs[13] | |
4626 | = call_really_used_regs[13] = 1; | |
4627 | ||
4628 | /* Conditionally disable FPRs. */ | |
4629 | if (TARGET_SOFT_FLOAT || !TARGET_FPRS) | |
4630 | for (i = 32; i < 64; i++) | |
4631 | fixed_regs[i] = call_used_regs[i] | |
c4ad648e | 4632 | = call_really_used_regs[i] = 1; |
2aa4498c | 4633 | |
7c9ac5c0 PH |
4634 | /* The TOC register is not killed across calls in a way that is |
4635 | visible to the compiler. */ | |
4636 | if (DEFAULT_ABI == ABI_AIX) | |
4637 | call_really_used_regs[2] = 0; | |
4638 | ||
2aa4498c AH |
4639 | if (DEFAULT_ABI == ABI_V4 |
4640 | && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM | |
4641 | && flag_pic == 2) | |
4642 | fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1; | |
4643 | ||
4644 | if (DEFAULT_ABI == ABI_V4 | |
4645 | && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM | |
4646 | && flag_pic == 1) | |
4647 | fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] | |
4648 | = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] | |
4649 | = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1; | |
4650 | ||
4651 | if (DEFAULT_ABI == ABI_DARWIN | |
4652 | && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) | |
6d0a8091 | 4653 | fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] |
2aa4498c AH |
4654 | = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] |
4655 | = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1; | |
4656 | ||
b4db40bf JJ |
4657 | if (TARGET_TOC && TARGET_MINIMAL_TOC) |
4658 | fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] | |
4659 | = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1; | |
4660 | ||
2aa4498c AH |
4661 | if (TARGET_SPE) |
4662 | { | |
4663 | global_regs[SPEFSCR_REGNO] = 1; | |
52ff33d0 NF |
4664 | /* We used to use r14 as FIXED_SCRATCH to address SPE 64-bit |
4665 | registers in prologues and epilogues. We no longer use r14 | |
4666 | for FIXED_SCRATCH, but we're keeping r14 out of the allocation | |
4667 | pool for link-compatibility with older versions of GCC. Once | |
4668 | "old" code has died out, we can return r14 to the allocation | |
4669 | pool. */ | |
4670 | fixed_regs[14] | |
4671 | = call_used_regs[14] | |
4672 | = call_really_used_regs[14] = 1; | |
2aa4498c AH |
4673 | } |
4674 | ||
0db747be | 4675 | if (!TARGET_ALTIVEC) |
2aa4498c AH |
4676 | { |
4677 | for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i) | |
4678 | fixed_regs[i] = call_used_regs[i] = call_really_used_regs[i] = 1; | |
4679 | call_really_used_regs[VRSAVE_REGNO] = 1; | |
4680 | } | |
4681 | ||
0db747be DE |
4682 | if (TARGET_ALTIVEC) |
4683 | global_regs[VSCR_REGNO] = 1; | |
4684 | ||
2aa4498c | 4685 | if (TARGET_ALTIVEC_ABI) |
0db747be DE |
4686 | { |
4687 | for (i = FIRST_ALTIVEC_REGNO; i < FIRST_ALTIVEC_REGNO + 20; ++i) | |
4688 | call_used_regs[i] = call_really_used_regs[i] = 1; | |
4689 | ||
4690 | /* AIX reserves VR20:31 in non-extended ABI mode. */ | |
4691 | if (TARGET_XCOFF) | |
4692 | for (i = FIRST_ALTIVEC_REGNO + 20; i < FIRST_ALTIVEC_REGNO + 32; ++i) | |
4693 | fixed_regs[i] = call_used_regs[i] = call_really_used_regs[i] = 1; | |
4694 | } | |
2aa4498c | 4695 | } |
fb4d4348 | 4696 | \f |
a4f6c312 SS |
4697 | /* Try to output insns to set TARGET equal to the constant C if it can |
4698 | be done in less than N insns. Do all computations in MODE. | |
4699 | Returns the place where the output has been placed if it can be | |
4700 | done and the insns have been emitted. If it would take more than N | |
4701 | insns, zero is returned and no insns and emitted. */ | |
2bfcf297 DB |
4702 | |
4703 | rtx | |
f676971a | 4704 | rs6000_emit_set_const (rtx dest, enum machine_mode mode, |
a2369ed3 | 4705 | rtx source, int n ATTRIBUTE_UNUSED) |
2bfcf297 | 4706 | { |
af8cb5c5 | 4707 | rtx result, insn, set; |
2bfcf297 DB |
4708 | HOST_WIDE_INT c0, c1; |
4709 | ||
37409796 | 4710 | switch (mode) |
2bfcf297 | 4711 | { |
37409796 NS |
4712 | case QImode: |
4713 | case HImode: | |
2bfcf297 | 4714 | if (dest == NULL) |
c4ad648e | 4715 | dest = gen_reg_rtx (mode); |
2bfcf297 DB |
4716 | emit_insn (gen_rtx_SET (VOIDmode, dest, source)); |
4717 | return dest; | |
bb8df8a6 | 4718 | |
37409796 | 4719 | case SImode: |
b3a13419 | 4720 | result = !can_create_pseudo_p () ? dest : gen_reg_rtx (SImode); |
bb8df8a6 | 4721 | |
d448860e | 4722 | emit_insn (gen_rtx_SET (VOIDmode, copy_rtx (result), |
af8cb5c5 DE |
4723 | GEN_INT (INTVAL (source) |
4724 | & (~ (HOST_WIDE_INT) 0xffff)))); | |
4725 | emit_insn (gen_rtx_SET (VOIDmode, dest, | |
d448860e | 4726 | gen_rtx_IOR (SImode, copy_rtx (result), |
af8cb5c5 DE |
4727 | GEN_INT (INTVAL (source) & 0xffff)))); |
4728 | result = dest; | |
37409796 NS |
4729 | break; |
4730 | ||
4731 | case DImode: | |
4732 | switch (GET_CODE (source)) | |
af8cb5c5 | 4733 | { |
37409796 | 4734 | case CONST_INT: |
af8cb5c5 DE |
4735 | c0 = INTVAL (source); |
4736 | c1 = -(c0 < 0); | |
37409796 | 4737 | break; |
bb8df8a6 | 4738 | |
37409796 | 4739 | case CONST_DOUBLE: |
2bfcf297 | 4740 | #if HOST_BITS_PER_WIDE_INT >= 64 |
af8cb5c5 DE |
4741 | c0 = CONST_DOUBLE_LOW (source); |
4742 | c1 = -(c0 < 0); | |
2bfcf297 | 4743 | #else |
af8cb5c5 DE |
4744 | c0 = CONST_DOUBLE_LOW (source); |
4745 | c1 = CONST_DOUBLE_HIGH (source); | |
2bfcf297 | 4746 | #endif |
37409796 NS |
4747 | break; |
4748 | ||
4749 | default: | |
4750 | gcc_unreachable (); | |
af8cb5c5 | 4751 | } |
af8cb5c5 DE |
4752 | |
4753 | result = rs6000_emit_set_long_const (dest, c0, c1); | |
37409796 NS |
4754 | break; |
4755 | ||
4756 | default: | |
4757 | gcc_unreachable (); | |
2bfcf297 | 4758 | } |
2bfcf297 | 4759 | |
af8cb5c5 DE |
4760 | insn = get_last_insn (); |
4761 | set = single_set (insn); | |
4762 | if (! CONSTANT_P (SET_SRC (set))) | |
4763 | set_unique_reg_note (insn, REG_EQUAL, source); | |
4764 | ||
4765 | return result; | |
2bfcf297 DB |
4766 | } |
4767 | ||
4768 | /* Having failed to find a 3 insn sequence in rs6000_emit_set_const, | |
4769 | fall back to a straight forward decomposition. We do this to avoid | |
4770 | exponential run times encountered when looking for longer sequences | |
4771 | with rs6000_emit_set_const. */ | |
4772 | static rtx | |
a2369ed3 | 4773 | rs6000_emit_set_long_const (rtx dest, HOST_WIDE_INT c1, HOST_WIDE_INT c2) |
2bfcf297 DB |
4774 | { |
4775 | if (!TARGET_POWERPC64) | |
4776 | { | |
4777 | rtx operand1, operand2; | |
4778 | ||
4779 | operand1 = operand_subword_force (dest, WORDS_BIG_ENDIAN == 0, | |
4780 | DImode); | |
d448860e | 4781 | operand2 = operand_subword_force (copy_rtx (dest), WORDS_BIG_ENDIAN != 0, |
2bfcf297 DB |
4782 | DImode); |
4783 | emit_move_insn (operand1, GEN_INT (c1)); | |
4784 | emit_move_insn (operand2, GEN_INT (c2)); | |
4785 | } | |
4786 | else | |
4787 | { | |
bc06712d | 4788 | HOST_WIDE_INT ud1, ud2, ud3, ud4; |
252b88f7 | 4789 | |
bc06712d | 4790 | ud1 = c1 & 0xffff; |
f921c9c9 | 4791 | ud2 = (c1 & 0xffff0000) >> 16; |
2bfcf297 | 4792 | #if HOST_BITS_PER_WIDE_INT >= 64 |
bc06712d | 4793 | c2 = c1 >> 32; |
2bfcf297 | 4794 | #endif |
bc06712d | 4795 | ud3 = c2 & 0xffff; |
f921c9c9 | 4796 | ud4 = (c2 & 0xffff0000) >> 16; |
2bfcf297 | 4797 | |
f676971a | 4798 | if ((ud4 == 0xffff && ud3 == 0xffff && ud2 == 0xffff && (ud1 & 0x8000)) |
bc06712d | 4799 | || (ud4 == 0 && ud3 == 0 && ud2 == 0 && ! (ud1 & 0x8000))) |
2bfcf297 | 4800 | { |
bc06712d | 4801 | if (ud1 & 0x8000) |
b78d48dd | 4802 | emit_move_insn (dest, GEN_INT (((ud1 ^ 0x8000) - 0x8000))); |
bc06712d TR |
4803 | else |
4804 | emit_move_insn (dest, GEN_INT (ud1)); | |
2bfcf297 | 4805 | } |
2bfcf297 | 4806 | |
f676971a | 4807 | else if ((ud4 == 0xffff && ud3 == 0xffff && (ud2 & 0x8000)) |
bc06712d | 4808 | || (ud4 == 0 && ud3 == 0 && ! (ud2 & 0x8000))) |
252b88f7 | 4809 | { |
bc06712d | 4810 | if (ud2 & 0x8000) |
f676971a | 4811 | emit_move_insn (dest, GEN_INT (((ud2 << 16) ^ 0x80000000) |
bc06712d | 4812 | - 0x80000000)); |
252b88f7 | 4813 | else |
bc06712d TR |
4814 | emit_move_insn (dest, GEN_INT (ud2 << 16)); |
4815 | if (ud1 != 0) | |
d448860e JH |
4816 | emit_move_insn (copy_rtx (dest), |
4817 | gen_rtx_IOR (DImode, copy_rtx (dest), | |
4818 | GEN_INT (ud1))); | |
252b88f7 | 4819 | } |
f676971a | 4820 | else if ((ud4 == 0xffff && (ud3 & 0x8000)) |
bc06712d TR |
4821 | || (ud4 == 0 && ! (ud3 & 0x8000))) |
4822 | { | |
4823 | if (ud3 & 0x8000) | |
f676971a | 4824 | emit_move_insn (dest, GEN_INT (((ud3 << 16) ^ 0x80000000) |
bc06712d TR |
4825 | - 0x80000000)); |
4826 | else | |
4827 | emit_move_insn (dest, GEN_INT (ud3 << 16)); | |
4828 | ||
4829 | if (ud2 != 0) | |
d448860e JH |
4830 | emit_move_insn (copy_rtx (dest), |
4831 | gen_rtx_IOR (DImode, copy_rtx (dest), | |
4832 | GEN_INT (ud2))); | |
4833 | emit_move_insn (copy_rtx (dest), | |
4834 | gen_rtx_ASHIFT (DImode, copy_rtx (dest), | |
4835 | GEN_INT (16))); | |
bc06712d | 4836 | if (ud1 != 0) |
d448860e JH |
4837 | emit_move_insn (copy_rtx (dest), |
4838 | gen_rtx_IOR (DImode, copy_rtx (dest), | |
4839 | GEN_INT (ud1))); | |
bc06712d | 4840 | } |
f676971a | 4841 | else |
bc06712d TR |
4842 | { |
4843 | if (ud4 & 0x8000) | |
f676971a | 4844 | emit_move_insn (dest, GEN_INT (((ud4 << 16) ^ 0x80000000) |
bc06712d TR |
4845 | - 0x80000000)); |
4846 | else | |
4847 | emit_move_insn (dest, GEN_INT (ud4 << 16)); | |
4848 | ||
4849 | if (ud3 != 0) | |
d448860e JH |
4850 | emit_move_insn (copy_rtx (dest), |
4851 | gen_rtx_IOR (DImode, copy_rtx (dest), | |
4852 | GEN_INT (ud3))); | |
2bfcf297 | 4853 | |
d448860e JH |
4854 | emit_move_insn (copy_rtx (dest), |
4855 | gen_rtx_ASHIFT (DImode, copy_rtx (dest), | |
4856 | GEN_INT (32))); | |
bc06712d | 4857 | if (ud2 != 0) |
d448860e JH |
4858 | emit_move_insn (copy_rtx (dest), |
4859 | gen_rtx_IOR (DImode, copy_rtx (dest), | |
4860 | GEN_INT (ud2 << 16))); | |
bc06712d | 4861 | if (ud1 != 0) |
d448860e JH |
4862 | emit_move_insn (copy_rtx (dest), |
4863 | gen_rtx_IOR (DImode, copy_rtx (dest), GEN_INT (ud1))); | |
bc06712d TR |
4864 | } |
4865 | } | |
2bfcf297 DB |
4866 | return dest; |
4867 | } | |
4868 | ||
76d2b81d | 4869 | /* Helper for the following. Get rid of [r+r] memory refs |
7393f7f8 | 4870 | in cases where it won't work (TImode, TFmode, TDmode). */ |
76d2b81d DJ |
4871 | |
4872 | static void | |
4873 | rs6000_eliminate_indexed_memrefs (rtx operands[2]) | |
4874 | { | |
4875 | if (GET_CODE (operands[0]) == MEM | |
4876 | && GET_CODE (XEXP (operands[0], 0)) != REG | |
55aa0757 | 4877 | && ! legitimate_constant_pool_address_p (XEXP (operands[0], 0)) |
76d2b81d DJ |
4878 | && ! reload_in_progress) |
4879 | operands[0] | |
4880 | = replace_equiv_address (operands[0], | |
4881 | copy_addr_to_reg (XEXP (operands[0], 0))); | |
4882 | ||
4883 | if (GET_CODE (operands[1]) == MEM | |
4884 | && GET_CODE (XEXP (operands[1], 0)) != REG | |
55aa0757 | 4885 | && ! legitimate_constant_pool_address_p (XEXP (operands[1], 0)) |
76d2b81d DJ |
4886 | && ! reload_in_progress) |
4887 | operands[1] | |
4888 | = replace_equiv_address (operands[1], | |
4889 | copy_addr_to_reg (XEXP (operands[1], 0))); | |
4890 | } | |
4891 | ||
fb4d4348 GK |
4892 | /* Emit a move from SOURCE to DEST in mode MODE. */ |
4893 | void | |
a2369ed3 | 4894 | rs6000_emit_move (rtx dest, rtx source, enum machine_mode mode) |
fb4d4348 GK |
4895 | { |
4896 | rtx operands[2]; | |
4897 | operands[0] = dest; | |
4898 | operands[1] = source; | |
f676971a | 4899 | |
fb4d4348 GK |
4900 | /* Sanity checks. Check that we get CONST_DOUBLE only when we should. */ |
4901 | if (GET_CODE (operands[1]) == CONST_DOUBLE | |
4902 | && ! FLOAT_MODE_P (mode) | |
4903 | && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT) | |
4904 | { | |
4905 | /* FIXME. This should never happen. */ | |
4906 | /* Since it seems that it does, do the safe thing and convert | |
4907 | to a CONST_INT. */ | |
2496c7bd | 4908 | operands[1] = gen_int_mode (CONST_DOUBLE_LOW (operands[1]), mode); |
fb4d4348 | 4909 | } |
37409796 NS |
4910 | gcc_assert (GET_CODE (operands[1]) != CONST_DOUBLE |
4911 | || FLOAT_MODE_P (mode) | |
4912 | || ((CONST_DOUBLE_HIGH (operands[1]) != 0 | |
4913 | || CONST_DOUBLE_LOW (operands[1]) < 0) | |
4914 | && (CONST_DOUBLE_HIGH (operands[1]) != -1 | |
4915 | || CONST_DOUBLE_LOW (operands[1]) >= 0))); | |
bb8df8a6 | 4916 | |
c9e8cb32 DD |
4917 | /* Check if GCC is setting up a block move that will end up using FP |
4918 | registers as temporaries. We must make sure this is acceptable. */ | |
4919 | if (GET_CODE (operands[0]) == MEM | |
4920 | && GET_CODE (operands[1]) == MEM | |
4921 | && mode == DImode | |
41543739 GK |
4922 | && (SLOW_UNALIGNED_ACCESS (DImode, MEM_ALIGN (operands[0])) |
4923 | || SLOW_UNALIGNED_ACCESS (DImode, MEM_ALIGN (operands[1]))) | |
4924 | && ! (SLOW_UNALIGNED_ACCESS (SImode, (MEM_ALIGN (operands[0]) > 32 | |
4925 | ? 32 : MEM_ALIGN (operands[0]))) | |
4926 | || SLOW_UNALIGNED_ACCESS (SImode, (MEM_ALIGN (operands[1]) > 32 | |
f676971a | 4927 | ? 32 |
41543739 GK |
4928 | : MEM_ALIGN (operands[1])))) |
4929 | && ! MEM_VOLATILE_P (operands [0]) | |
4930 | && ! MEM_VOLATILE_P (operands [1])) | |
c9e8cb32 | 4931 | { |
41543739 GK |
4932 | emit_move_insn (adjust_address (operands[0], SImode, 0), |
4933 | adjust_address (operands[1], SImode, 0)); | |
d448860e JH |
4934 | emit_move_insn (adjust_address (copy_rtx (operands[0]), SImode, 4), |
4935 | adjust_address (copy_rtx (operands[1]), SImode, 4)); | |
c9e8cb32 DD |
4936 | return; |
4937 | } | |
630d42a0 | 4938 | |
b3a13419 | 4939 | if (can_create_pseudo_p () && GET_CODE (operands[0]) == MEM |
c9dbf840 | 4940 | && !gpc_reg_operand (operands[1], mode)) |
f6219a5e | 4941 | operands[1] = force_reg (mode, operands[1]); |
a9098fd0 | 4942 | |
a3170dc6 | 4943 | if (mode == SFmode && ! TARGET_POWERPC |
696e45ba | 4944 | && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT |
ffc14f31 | 4945 | && GET_CODE (operands[0]) == MEM) |
fb4d4348 | 4946 | { |
ffc14f31 GK |
4947 | int regnum; |
4948 | ||
4949 | if (reload_in_progress || reload_completed) | |
4950 | regnum = true_regnum (operands[1]); | |
4951 | else if (GET_CODE (operands[1]) == REG) | |
4952 | regnum = REGNO (operands[1]); | |
4953 | else | |
4954 | regnum = -1; | |
f676971a | 4955 | |
fb4d4348 GK |
4956 | /* If operands[1] is a register, on POWER it may have |
4957 | double-precision data in it, so truncate it to single | |
4958 | precision. */ | |
4959 | if (FP_REGNO_P (regnum) || regnum >= FIRST_PSEUDO_REGISTER) | |
4960 | { | |
4961 | rtx newreg; | |
b3a13419 | 4962 | newreg = (!can_create_pseudo_p () ? copy_rtx (operands[1]) |
d448860e | 4963 | : gen_reg_rtx (mode)); |
fb4d4348 GK |
4964 | emit_insn (gen_aux_truncdfsf2 (newreg, operands[1])); |
4965 | operands[1] = newreg; | |
4966 | } | |
4967 | } | |
4968 | ||
c4501e62 JJ |
4969 | /* Recognize the case where operand[1] is a reference to thread-local |
4970 | data and load its address to a register. */ | |
84f52ebd | 4971 | if (rs6000_tls_referenced_p (operands[1])) |
c4501e62 | 4972 | { |
84f52ebd RH |
4973 | enum tls_model model; |
4974 | rtx tmp = operands[1]; | |
4975 | rtx addend = NULL; | |
4976 | ||
4977 | if (GET_CODE (tmp) == CONST && GET_CODE (XEXP (tmp, 0)) == PLUS) | |
4978 | { | |
4979 | addend = XEXP (XEXP (tmp, 0), 1); | |
4980 | tmp = XEXP (XEXP (tmp, 0), 0); | |
4981 | } | |
4982 | ||
4983 | gcc_assert (GET_CODE (tmp) == SYMBOL_REF); | |
4984 | model = SYMBOL_REF_TLS_MODEL (tmp); | |
4985 | gcc_assert (model != 0); | |
4986 | ||
4987 | tmp = rs6000_legitimize_tls_address (tmp, model); | |
4988 | if (addend) | |
4989 | { | |
4990 | tmp = gen_rtx_PLUS (mode, tmp, addend); | |
4991 | tmp = force_operand (tmp, operands[0]); | |
4992 | } | |
4993 | operands[1] = tmp; | |
c4501e62 JJ |
4994 | } |
4995 | ||
8f4e6caf RH |
4996 | /* Handle the case where reload calls us with an invalid address. */ |
4997 | if (reload_in_progress && mode == Pmode | |
69ef87e2 | 4998 | && (! general_operand (operands[1], mode) |
8f4e6caf RH |
4999 | || ! nonimmediate_operand (operands[0], mode))) |
5000 | goto emit_set; | |
5001 | ||
a9baceb1 GK |
5002 | /* 128-bit constant floating-point values on Darwin should really be |
5003 | loaded as two parts. */ | |
8521c414 | 5004 | if (!TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128 |
a9baceb1 GK |
5005 | && mode == TFmode && GET_CODE (operands[1]) == CONST_DOUBLE) |
5006 | { | |
5007 | /* DImode is used, not DFmode, because simplify_gen_subreg doesn't | |
5008 | know how to get a DFmode SUBREG of a TFmode. */ | |
17caeff2 JM |
5009 | enum machine_mode imode = (TARGET_E500_DOUBLE ? DFmode : DImode); |
5010 | rs6000_emit_move (simplify_gen_subreg (imode, operands[0], mode, 0), | |
5011 | simplify_gen_subreg (imode, operands[1], mode, 0), | |
5012 | imode); | |
5013 | rs6000_emit_move (simplify_gen_subreg (imode, operands[0], mode, | |
5014 | GET_MODE_SIZE (imode)), | |
5015 | simplify_gen_subreg (imode, operands[1], mode, | |
5016 | GET_MODE_SIZE (imode)), | |
5017 | imode); | |
a9baceb1 GK |
5018 | return; |
5019 | } | |
5020 | ||
e41b2a33 PB |
5021 | if (reload_in_progress && cfun->machine->sdmode_stack_slot != NULL_RTX) |
5022 | cfun->machine->sdmode_stack_slot = | |
5023 | eliminate_regs (cfun->machine->sdmode_stack_slot, VOIDmode, NULL_RTX); | |
5024 | ||
5025 | if (reload_in_progress | |
5026 | && mode == SDmode | |
5027 | && MEM_P (operands[0]) | |
5028 | && rtx_equal_p (operands[0], cfun->machine->sdmode_stack_slot) | |
5029 | && REG_P (operands[1])) | |
5030 | { | |
5031 | if (FP_REGNO_P (REGNO (operands[1]))) | |
5032 | { | |
5033 | rtx mem = adjust_address_nv (operands[0], DDmode, 0); | |
5034 | mem = eliminate_regs (mem, VOIDmode, NULL_RTX); | |
5035 | emit_insn (gen_movsd_store (mem, operands[1])); | |
5036 | } | |
5037 | else if (INT_REGNO_P (REGNO (operands[1]))) | |
5038 | { | |
5039 | rtx mem = adjust_address_nv (operands[0], mode, 4); | |
5040 | mem = eliminate_regs (mem, VOIDmode, NULL_RTX); | |
5041 | emit_insn (gen_movsd_hardfloat (mem, operands[1])); | |
5042 | } | |
5043 | else | |
5044 | gcc_unreachable(); | |
5045 | return; | |
5046 | } | |
5047 | if (reload_in_progress | |
5048 | && mode == SDmode | |
5049 | && REG_P (operands[0]) | |
5050 | && MEM_P (operands[1]) | |
5051 | && rtx_equal_p (operands[1], cfun->machine->sdmode_stack_slot)) | |
5052 | { | |
5053 | if (FP_REGNO_P (REGNO (operands[0]))) | |
5054 | { | |
5055 | rtx mem = adjust_address_nv (operands[1], DDmode, 0); | |
5056 | mem = eliminate_regs (mem, VOIDmode, NULL_RTX); | |
5057 | emit_insn (gen_movsd_load (operands[0], mem)); | |
5058 | } | |
5059 | else if (INT_REGNO_P (REGNO (operands[0]))) | |
5060 | { | |
5061 | rtx mem = adjust_address_nv (operands[1], mode, 4); | |
5062 | mem = eliminate_regs (mem, VOIDmode, NULL_RTX); | |
5063 | emit_insn (gen_movsd_hardfloat (operands[0], mem)); | |
5064 | } | |
5065 | else | |
5066 | gcc_unreachable(); | |
5067 | return; | |
5068 | } | |
5069 | ||
fb4d4348 GK |
5070 | /* FIXME: In the long term, this switch statement should go away |
5071 | and be replaced by a sequence of tests based on things like | |
5072 | mode == Pmode. */ | |
5073 | switch (mode) | |
5074 | { | |
5075 | case HImode: | |
5076 | case QImode: | |
5077 | if (CONSTANT_P (operands[1]) | |
5078 | && GET_CODE (operands[1]) != CONST_INT) | |
a9098fd0 | 5079 | operands[1] = force_const_mem (mode, operands[1]); |
fb4d4348 GK |
5080 | break; |
5081 | ||
06f4e019 | 5082 | case TFmode: |
7393f7f8 | 5083 | case TDmode: |
76d2b81d DJ |
5084 | rs6000_eliminate_indexed_memrefs (operands); |
5085 | /* fall through */ | |
5086 | ||
fb4d4348 | 5087 | case DFmode: |
7393f7f8 | 5088 | case DDmode: |
fb4d4348 | 5089 | case SFmode: |
e41b2a33 | 5090 | case SDmode: |
f676971a | 5091 | if (CONSTANT_P (operands[1]) |
fb4d4348 | 5092 | && ! easy_fp_constant (operands[1], mode)) |
a9098fd0 | 5093 | operands[1] = force_const_mem (mode, operands[1]); |
fb4d4348 | 5094 | break; |
f676971a | 5095 | |
0ac081f6 AH |
5096 | case V16QImode: |
5097 | case V8HImode: | |
5098 | case V4SFmode: | |
5099 | case V4SImode: | |
a3170dc6 AH |
5100 | case V4HImode: |
5101 | case V2SFmode: | |
5102 | case V2SImode: | |
00a892b8 | 5103 | case V1DImode: |
69ef87e2 | 5104 | if (CONSTANT_P (operands[1]) |
d744e06e | 5105 | && !easy_vector_constant (operands[1], mode)) |
0ac081f6 AH |
5106 | operands[1] = force_const_mem (mode, operands[1]); |
5107 | break; | |
f676971a | 5108 | |
fb4d4348 | 5109 | case SImode: |
a9098fd0 | 5110 | case DImode: |
fb4d4348 GK |
5111 | /* Use default pattern for address of ELF small data */ |
5112 | if (TARGET_ELF | |
a9098fd0 | 5113 | && mode == Pmode |
f607bc57 | 5114 | && DEFAULT_ABI == ABI_V4 |
f676971a | 5115 | && (GET_CODE (operands[1]) == SYMBOL_REF |
a9098fd0 GK |
5116 | || GET_CODE (operands[1]) == CONST) |
5117 | && small_data_operand (operands[1], mode)) | |
fb4d4348 GK |
5118 | { |
5119 | emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1])); | |
5120 | return; | |
5121 | } | |
5122 | ||
f607bc57 | 5123 | if (DEFAULT_ABI == ABI_V4 |
a9098fd0 GK |
5124 | && mode == Pmode && mode == SImode |
5125 | && flag_pic == 1 && got_operand (operands[1], mode)) | |
fb4d4348 GK |
5126 | { |
5127 | emit_insn (gen_movsi_got (operands[0], operands[1])); | |
5128 | return; | |
5129 | } | |
5130 | ||
ee890fe2 | 5131 | if ((TARGET_ELF || DEFAULT_ABI == ABI_DARWIN) |
f1384257 AM |
5132 | && TARGET_NO_TOC |
5133 | && ! flag_pic | |
a9098fd0 | 5134 | && mode == Pmode |
fb4d4348 GK |
5135 | && CONSTANT_P (operands[1]) |
5136 | && GET_CODE (operands[1]) != HIGH | |
5137 | && GET_CODE (operands[1]) != CONST_INT) | |
5138 | { | |
b3a13419 ILT |
5139 | rtx target = (!can_create_pseudo_p () |
5140 | ? operands[0] | |
5141 | : gen_reg_rtx (mode)); | |
fb4d4348 GK |
5142 | |
5143 | /* If this is a function address on -mcall-aixdesc, | |
5144 | convert it to the address of the descriptor. */ | |
5145 | if (DEFAULT_ABI == ABI_AIX | |
5146 | && GET_CODE (operands[1]) == SYMBOL_REF | |
5147 | && XSTR (operands[1], 0)[0] == '.') | |
5148 | { | |
5149 | const char *name = XSTR (operands[1], 0); | |
5150 | rtx new_ref; | |
5151 | while (*name == '.') | |
5152 | name++; | |
5153 | new_ref = gen_rtx_SYMBOL_REF (Pmode, name); | |
5154 | CONSTANT_POOL_ADDRESS_P (new_ref) | |
5155 | = CONSTANT_POOL_ADDRESS_P (operands[1]); | |
d1908feb | 5156 | SYMBOL_REF_FLAGS (new_ref) = SYMBOL_REF_FLAGS (operands[1]); |
fb4d4348 | 5157 | SYMBOL_REF_USED (new_ref) = SYMBOL_REF_USED (operands[1]); |
c185c797 | 5158 | SYMBOL_REF_DATA (new_ref) = SYMBOL_REF_DATA (operands[1]); |
fb4d4348 GK |
5159 | operands[1] = new_ref; |
5160 | } | |
7509c759 | 5161 | |
ee890fe2 SS |
5162 | if (DEFAULT_ABI == ABI_DARWIN) |
5163 | { | |
ab82a49f AP |
5164 | #if TARGET_MACHO |
5165 | if (MACHO_DYNAMIC_NO_PIC_P) | |
5166 | { | |
5167 | /* Take care of any required data indirection. */ | |
5168 | operands[1] = rs6000_machopic_legitimize_pic_address ( | |
5169 | operands[1], mode, operands[0]); | |
5170 | if (operands[0] != operands[1]) | |
5171 | emit_insn (gen_rtx_SET (VOIDmode, | |
c4ad648e | 5172 | operands[0], operands[1])); |
ab82a49f AP |
5173 | return; |
5174 | } | |
5175 | #endif | |
b8a55285 AP |
5176 | emit_insn (gen_macho_high (target, operands[1])); |
5177 | emit_insn (gen_macho_low (operands[0], target, operands[1])); | |
ee890fe2 SS |
5178 | return; |
5179 | } | |
5180 | ||
fb4d4348 GK |
5181 | emit_insn (gen_elf_high (target, operands[1])); |
5182 | emit_insn (gen_elf_low (operands[0], target, operands[1])); | |
5183 | return; | |
5184 | } | |
5185 | ||
a9098fd0 GK |
5186 | /* If this is a SYMBOL_REF that refers to a constant pool entry, |
5187 | and we have put it in the TOC, we just need to make a TOC-relative | |
5188 | reference to it. */ | |
5189 | if (TARGET_TOC | |
5190 | && GET_CODE (operands[1]) == SYMBOL_REF | |
4d588c14 | 5191 | && constant_pool_expr_p (operands[1]) |
a9098fd0 GK |
5192 | && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (operands[1]), |
5193 | get_pool_mode (operands[1]))) | |
fb4d4348 | 5194 | { |
a9098fd0 | 5195 | operands[1] = create_TOC_reference (operands[1]); |
fb4d4348 | 5196 | } |
a9098fd0 GK |
5197 | else if (mode == Pmode |
5198 | && CONSTANT_P (operands[1]) | |
38886f37 AO |
5199 | && ((GET_CODE (operands[1]) != CONST_INT |
5200 | && ! easy_fp_constant (operands[1], mode)) | |
5201 | || (GET_CODE (operands[1]) == CONST_INT | |
5202 | && num_insns_constant (operands[1], mode) > 2) | |
5203 | || (GET_CODE (operands[0]) == REG | |
5204 | && FP_REGNO_P (REGNO (operands[0])))) | |
a9098fd0 | 5205 | && GET_CODE (operands[1]) != HIGH |
4d588c14 RH |
5206 | && ! legitimate_constant_pool_address_p (operands[1]) |
5207 | && ! toc_relative_expr_p (operands[1])) | |
fb4d4348 GK |
5208 | { |
5209 | /* Emit a USE operation so that the constant isn't deleted if | |
5210 | expensive optimizations are turned on because nobody | |
5211 | references it. This should only be done for operands that | |
5212 | contain SYMBOL_REFs with CONSTANT_POOL_ADDRESS_P set. | |
5213 | This should not be done for operands that contain LABEL_REFs. | |
5214 | For now, we just handle the obvious case. */ | |
5215 | if (GET_CODE (operands[1]) != LABEL_REF) | |
c41c1387 | 5216 | emit_use (operands[1]); |
fb4d4348 | 5217 | |
c859cda6 | 5218 | #if TARGET_MACHO |
ee890fe2 | 5219 | /* Darwin uses a special PIC legitimizer. */ |
ab82a49f | 5220 | if (DEFAULT_ABI == ABI_DARWIN && MACHOPIC_INDIRECT) |
ee890fe2 | 5221 | { |
ee890fe2 SS |
5222 | operands[1] = |
5223 | rs6000_machopic_legitimize_pic_address (operands[1], mode, | |
c859cda6 DJ |
5224 | operands[0]); |
5225 | if (operands[0] != operands[1]) | |
5226 | emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1])); | |
ee890fe2 SS |
5227 | return; |
5228 | } | |
c859cda6 | 5229 | #endif |
ee890fe2 | 5230 | |
fb4d4348 GK |
5231 | /* If we are to limit the number of things we put in the TOC and |
5232 | this is a symbol plus a constant we can add in one insn, | |
5233 | just put the symbol in the TOC and add the constant. Don't do | |
5234 | this if reload is in progress. */ | |
5235 | if (GET_CODE (operands[1]) == CONST | |
5236 | && TARGET_NO_SUM_IN_TOC && ! reload_in_progress | |
5237 | && GET_CODE (XEXP (operands[1], 0)) == PLUS | |
a9098fd0 | 5238 | && add_operand (XEXP (XEXP (operands[1], 0), 1), mode) |
fb4d4348 GK |
5239 | && (GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == LABEL_REF |
5240 | || GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == SYMBOL_REF) | |
5241 | && ! side_effects_p (operands[0])) | |
5242 | { | |
a4f6c312 SS |
5243 | rtx sym = |
5244 | force_const_mem (mode, XEXP (XEXP (operands[1], 0), 0)); | |
fb4d4348 GK |
5245 | rtx other = XEXP (XEXP (operands[1], 0), 1); |
5246 | ||
a9098fd0 GK |
5247 | sym = force_reg (mode, sym); |
5248 | if (mode == SImode) | |
5249 | emit_insn (gen_addsi3 (operands[0], sym, other)); | |
5250 | else | |
5251 | emit_insn (gen_adddi3 (operands[0], sym, other)); | |
fb4d4348 GK |
5252 | return; |
5253 | } | |
5254 | ||
a9098fd0 | 5255 | operands[1] = force_const_mem (mode, operands[1]); |
fb4d4348 | 5256 | |
f676971a | 5257 | if (TARGET_TOC |
0cdc04e8 | 5258 | && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF |
4d588c14 | 5259 | && constant_pool_expr_p (XEXP (operands[1], 0)) |
d34c5b80 DE |
5260 | && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P ( |
5261 | get_pool_constant (XEXP (operands[1], 0)), | |
5262 | get_pool_mode (XEXP (operands[1], 0)))) | |
a9098fd0 | 5263 | { |
ba4828e0 | 5264 | operands[1] |
542a8afa | 5265 | = gen_const_mem (mode, |
c4ad648e | 5266 | create_TOC_reference (XEXP (operands[1], 0))); |
ba4828e0 | 5267 | set_mem_alias_set (operands[1], get_TOC_alias_set ()); |
a9098fd0 | 5268 | } |
fb4d4348 GK |
5269 | } |
5270 | break; | |
a9098fd0 | 5271 | |
fb4d4348 | 5272 | case TImode: |
76d2b81d DJ |
5273 | rs6000_eliminate_indexed_memrefs (operands); |
5274 | ||
27dc0551 DE |
5275 | if (TARGET_POWER) |
5276 | { | |
5277 | emit_insn (gen_rtx_PARALLEL (VOIDmode, | |
5278 | gen_rtvec (2, | |
5279 | gen_rtx_SET (VOIDmode, | |
5280 | operands[0], operands[1]), | |
5281 | gen_rtx_CLOBBER (VOIDmode, | |
5282 | gen_rtx_SCRATCH (SImode))))); | |
5283 | return; | |
5284 | } | |
fb4d4348 GK |
5285 | break; |
5286 | ||
5287 | default: | |
37409796 | 5288 | gcc_unreachable (); |
fb4d4348 GK |
5289 | } |
5290 | ||
a9098fd0 GK |
5291 | /* Above, we may have called force_const_mem which may have returned |
5292 | an invalid address. If we can, fix this up; otherwise, reload will | |
5293 | have to deal with it. */ | |
8f4e6caf RH |
5294 | if (GET_CODE (operands[1]) == MEM && ! reload_in_progress) |
5295 | operands[1] = validize_mem (operands[1]); | |
a9098fd0 | 5296 | |
8f4e6caf | 5297 | emit_set: |
fb4d4348 GK |
5298 | emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1])); |
5299 | } | |
4697a36c | 5300 | \f |
2858f73a GK |
5301 | /* Nonzero if we can use a floating-point register to pass this arg. */ |
5302 | #define USE_FP_FOR_ARG_P(CUM,MODE,TYPE) \ | |
ebb109ad | 5303 | (SCALAR_FLOAT_MODE_P (MODE) \ |
2858f73a | 5304 | && (CUM)->fregno <= FP_ARG_MAX_REG \ |
56f4cc04 | 5305 | && TARGET_HARD_FLOAT && TARGET_FPRS) |
2858f73a GK |
5306 | |
5307 | /* Nonzero if we can use an AltiVec register to pass this arg. */ | |
5308 | #define USE_ALTIVEC_FOR_ARG_P(CUM,MODE,TYPE,NAMED) \ | |
5309 | (ALTIVEC_VECTOR_MODE (MODE) \ | |
5310 | && (CUM)->vregno <= ALTIVEC_ARG_MAX_REG \ | |
5311 | && TARGET_ALTIVEC_ABI \ | |
83953138 | 5312 | && (NAMED)) |
2858f73a | 5313 | |
c6e8c921 GK |
5314 | /* Return a nonzero value to say to return the function value in |
5315 | memory, just as large structures are always returned. TYPE will be | |
5316 | the data type of the value, and FNTYPE will be the type of the | |
5317 | function doing the returning, or @code{NULL} for libcalls. | |
5318 | ||
5319 | The AIX ABI for the RS/6000 specifies that all structures are | |
5320 | returned in memory. The Darwin ABI does the same. The SVR4 ABI | |
5321 | specifies that structures <= 8 bytes are returned in r3/r4, but a | |
5322 | draft put them in memory, and GCC used to implement the draft | |
df01da37 | 5323 | instead of the final standard. Therefore, aix_struct_return |
c6e8c921 GK |
5324 | controls this instead of DEFAULT_ABI; V.4 targets needing backward |
5325 | compatibility can change DRAFT_V4_STRUCT_RET to override the | |
5326 | default, and -m switches get the final word. See | |
5327 | rs6000_override_options for more details. | |
5328 | ||
5329 | The PPC32 SVR4 ABI uses IEEE double extended for long double, if 128-bit | |
5330 | long double support is enabled. These values are returned in memory. | |
5331 | ||
5332 | int_size_in_bytes returns -1 for variable size objects, which go in | |
5333 | memory always. The cast to unsigned makes -1 > 8. */ | |
5334 | ||
5335 | static bool | |
586de218 | 5336 | rs6000_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED) |
c6e8c921 | 5337 | { |
594a51fe SS |
5338 | /* In the darwin64 abi, try to use registers for larger structs |
5339 | if possible. */ | |
0b5383eb | 5340 | if (rs6000_darwin64_abi |
594a51fe | 5341 | && TREE_CODE (type) == RECORD_TYPE |
0b5383eb DJ |
5342 | && int_size_in_bytes (type) > 0) |
5343 | { | |
5344 | CUMULATIVE_ARGS valcum; | |
5345 | rtx valret; | |
5346 | ||
5347 | valcum.words = 0; | |
5348 | valcum.fregno = FP_ARG_MIN_REG; | |
5349 | valcum.vregno = ALTIVEC_ARG_MIN_REG; | |
5350 | /* Do a trial code generation as if this were going to be passed | |
5351 | as an argument; if any part goes in memory, we return NULL. */ | |
5352 | valret = rs6000_darwin64_record_arg (&valcum, type, 1, true); | |
5353 | if (valret) | |
5354 | return false; | |
5355 | /* Otherwise fall through to more conventional ABI rules. */ | |
5356 | } | |
594a51fe | 5357 | |
c6e8c921 | 5358 | if (AGGREGATE_TYPE_P (type) |
df01da37 | 5359 | && (aix_struct_return |
c6e8c921 GK |
5360 | || (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 8)) |
5361 | return true; | |
b693336b | 5362 | |
bada2eb8 DE |
5363 | /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector |
5364 | modes only exist for GCC vector types if -maltivec. */ | |
5365 | if (TARGET_32BIT && !TARGET_ALTIVEC_ABI | |
5366 | && ALTIVEC_VECTOR_MODE (TYPE_MODE (type))) | |
5367 | return false; | |
5368 | ||
b693336b PB |
5369 | /* Return synthetic vectors in memory. */ |
5370 | if (TREE_CODE (type) == VECTOR_TYPE | |
ad630bef | 5371 | && int_size_in_bytes (type) > (TARGET_ALTIVEC_ABI ? 16 : 8)) |
b693336b PB |
5372 | { |
5373 | static bool warned_for_return_big_vectors = false; | |
5374 | if (!warned_for_return_big_vectors) | |
5375 | { | |
d4ee4d25 | 5376 | warning (0, "GCC vector returned by reference: " |
b693336b PB |
5377 | "non-standard ABI extension with no compatibility guarantee"); |
5378 | warned_for_return_big_vectors = true; | |
5379 | } | |
5380 | return true; | |
5381 | } | |
5382 | ||
602ea4d3 | 5383 | if (DEFAULT_ABI == ABI_V4 && TARGET_IEEEQUAD && TYPE_MODE (type) == TFmode) |
c6e8c921 | 5384 | return true; |
ad630bef | 5385 | |
c6e8c921 GK |
5386 | return false; |
5387 | } | |
5388 | ||
4697a36c MM |
5389 | /* Initialize a variable CUM of type CUMULATIVE_ARGS |
5390 | for a call to a function whose data type is FNTYPE. | |
5391 | For a library call, FNTYPE is 0. | |
5392 | ||
5393 | For incoming args we set the number of arguments in the prototype large | |
1c20ae99 | 5394 | so we never return a PARALLEL. */ |
4697a36c MM |
5395 | |
5396 | void | |
f676971a | 5397 | init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype, |
0f6937fe AM |
5398 | rtx libname ATTRIBUTE_UNUSED, int incoming, |
5399 | int libcall, int n_named_args) | |
4697a36c MM |
5400 | { |
5401 | static CUMULATIVE_ARGS zero_cumulative; | |
5402 | ||
5403 | *cum = zero_cumulative; | |
5404 | cum->words = 0; | |
5405 | cum->fregno = FP_ARG_MIN_REG; | |
0ac081f6 | 5406 | cum->vregno = ALTIVEC_ARG_MIN_REG; |
4697a36c | 5407 | cum->prototype = (fntype && TYPE_ARG_TYPES (fntype)); |
ddcc8263 DE |
5408 | cum->call_cookie = ((DEFAULT_ABI == ABI_V4 && libcall) |
5409 | ? CALL_LIBCALL : CALL_NORMAL); | |
4cc833b7 | 5410 | cum->sysv_gregno = GP_ARG_MIN_REG; |
a6c9bed4 AH |
5411 | cum->stdarg = fntype |
5412 | && (TYPE_ARG_TYPES (fntype) != 0 | |
5413 | && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype))) | |
5414 | != void_type_node)); | |
4697a36c | 5415 | |
0f6937fe AM |
5416 | cum->nargs_prototype = 0; |
5417 | if (incoming || cum->prototype) | |
5418 | cum->nargs_prototype = n_named_args; | |
4697a36c | 5419 | |
a5c76ee6 | 5420 | /* Check for a longcall attribute. */ |
3eb4e360 AM |
5421 | if ((!fntype && rs6000_default_long_calls) |
5422 | || (fntype | |
5423 | && lookup_attribute ("longcall", TYPE_ATTRIBUTES (fntype)) | |
5424 | && !lookup_attribute ("shortcall", TYPE_ATTRIBUTES (fntype)))) | |
5425 | cum->call_cookie |= CALL_LONG; | |
6a4cee5f | 5426 | |
4697a36c MM |
5427 | if (TARGET_DEBUG_ARG) |
5428 | { | |
5429 | fprintf (stderr, "\ninit_cumulative_args:"); | |
5430 | if (fntype) | |
5431 | { | |
5432 | tree ret_type = TREE_TYPE (fntype); | |
5433 | fprintf (stderr, " ret code = %s,", | |
5434 | tree_code_name[ (int)TREE_CODE (ret_type) ]); | |
5435 | } | |
5436 | ||
6a4cee5f MM |
5437 | if (cum->call_cookie & CALL_LONG) |
5438 | fprintf (stderr, " longcall,"); | |
5439 | ||
4697a36c MM |
5440 | fprintf (stderr, " proto = %d, nargs = %d\n", |
5441 | cum->prototype, cum->nargs_prototype); | |
5442 | } | |
f676971a | 5443 | |
c4ad648e AM |
5444 | if (fntype |
5445 | && !TARGET_ALTIVEC | |
5446 | && TARGET_ALTIVEC_ABI | |
5447 | && ALTIVEC_VECTOR_MODE (TYPE_MODE (TREE_TYPE (fntype)))) | |
5448 | { | |
c85ce869 | 5449 | error ("cannot return value in vector register because" |
c4ad648e | 5450 | " altivec instructions are disabled, use -maltivec" |
c85ce869 | 5451 | " to enable them"); |
c4ad648e | 5452 | } |
4697a36c MM |
5453 | } |
5454 | \f | |
fe984136 RH |
5455 | /* Return true if TYPE must be passed on the stack and not in registers. */ |
5456 | ||
5457 | static bool | |
586de218 | 5458 | rs6000_must_pass_in_stack (enum machine_mode mode, const_tree type) |
fe984136 RH |
5459 | { |
5460 | if (DEFAULT_ABI == ABI_AIX || TARGET_64BIT) | |
5461 | return must_pass_in_stack_var_size (mode, type); | |
5462 | else | |
5463 | return must_pass_in_stack_var_size_or_pad (mode, type); | |
5464 | } | |
5465 | ||
c229cba9 DE |
5466 | /* If defined, a C expression which determines whether, and in which |
5467 | direction, to pad out an argument with extra space. The value | |
5468 | should be of type `enum direction': either `upward' to pad above | |
5469 | the argument, `downward' to pad below, or `none' to inhibit | |
5470 | padding. | |
5471 | ||
5472 | For the AIX ABI structs are always stored left shifted in their | |
5473 | argument slot. */ | |
5474 | ||
9ebbca7d | 5475 | enum direction |
586de218 | 5476 | function_arg_padding (enum machine_mode mode, const_tree type) |
c229cba9 | 5477 | { |
6e985040 AM |
5478 | #ifndef AGGREGATE_PADDING_FIXED |
5479 | #define AGGREGATE_PADDING_FIXED 0 | |
5480 | #endif | |
5481 | #ifndef AGGREGATES_PAD_UPWARD_ALWAYS | |
5482 | #define AGGREGATES_PAD_UPWARD_ALWAYS 0 | |
5483 | #endif | |
5484 | ||
5485 | if (!AGGREGATE_PADDING_FIXED) | |
5486 | { | |
5487 | /* GCC used to pass structures of the same size as integer types as | |
5488 | if they were in fact integers, ignoring FUNCTION_ARG_PADDING. | |
19525b57 | 5489 | i.e. Structures of size 1 or 2 (or 4 when TARGET_64BIT) were |
6e985040 AM |
5490 | passed padded downward, except that -mstrict-align further |
5491 | muddied the water in that multi-component structures of 2 and 4 | |
5492 | bytes in size were passed padded upward. | |
5493 | ||
5494 | The following arranges for best compatibility with previous | |
5495 | versions of gcc, but removes the -mstrict-align dependency. */ | |
5496 | if (BYTES_BIG_ENDIAN) | |
5497 | { | |
5498 | HOST_WIDE_INT size = 0; | |
5499 | ||
5500 | if (mode == BLKmode) | |
5501 | { | |
5502 | if (type && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST) | |
5503 | size = int_size_in_bytes (type); | |
5504 | } | |
5505 | else | |
5506 | size = GET_MODE_SIZE (mode); | |
5507 | ||
5508 | if (size == 1 || size == 2 || size == 4) | |
5509 | return downward; | |
5510 | } | |
5511 | return upward; | |
5512 | } | |
5513 | ||
5514 | if (AGGREGATES_PAD_UPWARD_ALWAYS) | |
5515 | { | |
5516 | if (type != 0 && AGGREGATE_TYPE_P (type)) | |
5517 | return upward; | |
5518 | } | |
c229cba9 | 5519 | |
d3704c46 KH |
5520 | /* Fall back to the default. */ |
5521 | return DEFAULT_FUNCTION_ARG_PADDING (mode, type); | |
c229cba9 DE |
5522 | } |
5523 | ||
b6c9286a | 5524 | /* If defined, a C expression that gives the alignment boundary, in bits, |
f676971a | 5525 | of an argument with the specified mode and type. If it is not defined, |
b6c9286a | 5526 | PARM_BOUNDARY is used for all arguments. |
f676971a | 5527 | |
84e9ad15 AM |
5528 | V.4 wants long longs and doubles to be double word aligned. Just |
5529 | testing the mode size is a boneheaded way to do this as it means | |
5530 | that other types such as complex int are also double word aligned. | |
5531 | However, we're stuck with this because changing the ABI might break | |
5532 | existing library interfaces. | |
5533 | ||
b693336b PB |
5534 | Doubleword align SPE vectors. |
5535 | Quadword align Altivec vectors. | |
5536 | Quadword align large synthetic vector types. */ | |
b6c9286a MM |
5537 | |
5538 | int | |
b693336b | 5539 | function_arg_boundary (enum machine_mode mode, tree type) |
b6c9286a | 5540 | { |
84e9ad15 AM |
5541 | if (DEFAULT_ABI == ABI_V4 |
5542 | && (GET_MODE_SIZE (mode) == 8 | |
5543 | || (TARGET_HARD_FLOAT | |
5544 | && TARGET_FPRS | |
7393f7f8 | 5545 | && (mode == TFmode || mode == TDmode)))) |
4ed78545 | 5546 | return 64; |
ad630bef DE |
5547 | else if (SPE_VECTOR_MODE (mode) |
5548 | || (type && TREE_CODE (type) == VECTOR_TYPE | |
5549 | && int_size_in_bytes (type) >= 8 | |
5550 | && int_size_in_bytes (type) < 16)) | |
e1f83b4d | 5551 | return 64; |
ad630bef DE |
5552 | else if (ALTIVEC_VECTOR_MODE (mode) |
5553 | || (type && TREE_CODE (type) == VECTOR_TYPE | |
5554 | && int_size_in_bytes (type) >= 16)) | |
0ac081f6 | 5555 | return 128; |
0b5383eb DJ |
5556 | else if (rs6000_darwin64_abi && mode == BLKmode |
5557 | && type && TYPE_ALIGN (type) > 64) | |
5558 | return 128; | |
9ebbca7d | 5559 | else |
b6c9286a | 5560 | return PARM_BOUNDARY; |
b6c9286a | 5561 | } |
c53bdcf5 | 5562 | |
294bd182 AM |
5563 | /* For a function parm of MODE and TYPE, return the starting word in |
5564 | the parameter area. NWORDS of the parameter area are already used. */ | |
5565 | ||
5566 | static unsigned int | |
5567 | rs6000_parm_start (enum machine_mode mode, tree type, unsigned int nwords) | |
5568 | { | |
5569 | unsigned int align; | |
5570 | unsigned int parm_offset; | |
5571 | ||
5572 | align = function_arg_boundary (mode, type) / PARM_BOUNDARY - 1; | |
5573 | parm_offset = DEFAULT_ABI == ABI_V4 ? 2 : 6; | |
5574 | return nwords + (-(parm_offset + nwords) & align); | |
5575 | } | |
5576 | ||
c53bdcf5 AM |
5577 | /* Compute the size (in words) of a function argument. */ |
5578 | ||
5579 | static unsigned long | |
5580 | rs6000_arg_size (enum machine_mode mode, tree type) | |
5581 | { | |
5582 | unsigned long size; | |
5583 | ||
5584 | if (mode != BLKmode) | |
5585 | size = GET_MODE_SIZE (mode); | |
5586 | else | |
5587 | size = int_size_in_bytes (type); | |
5588 | ||
5589 | if (TARGET_32BIT) | |
5590 | return (size + 3) >> 2; | |
5591 | else | |
5592 | return (size + 7) >> 3; | |
5593 | } | |
b6c9286a | 5594 | \f |
0b5383eb | 5595 | /* Use this to flush pending int fields. */ |
594a51fe SS |
5596 | |
5597 | static void | |
0b5383eb DJ |
5598 | rs6000_darwin64_record_arg_advance_flush (CUMULATIVE_ARGS *cum, |
5599 | HOST_WIDE_INT bitpos) | |
594a51fe | 5600 | { |
0b5383eb DJ |
5601 | unsigned int startbit, endbit; |
5602 | int intregs, intoffset; | |
5603 | enum machine_mode mode; | |
594a51fe | 5604 | |
0b5383eb DJ |
5605 | if (cum->intoffset == -1) |
5606 | return; | |
594a51fe | 5607 | |
0b5383eb DJ |
5608 | intoffset = cum->intoffset; |
5609 | cum->intoffset = -1; | |
5610 | ||
5611 | if (intoffset % BITS_PER_WORD != 0) | |
5612 | { | |
5613 | mode = mode_for_size (BITS_PER_WORD - intoffset % BITS_PER_WORD, | |
5614 | MODE_INT, 0); | |
5615 | if (mode == BLKmode) | |
594a51fe | 5616 | { |
0b5383eb DJ |
5617 | /* We couldn't find an appropriate mode, which happens, |
5618 | e.g., in packed structs when there are 3 bytes to load. | |
5619 | Back intoffset back to the beginning of the word in this | |
5620 | case. */ | |
5621 | intoffset = intoffset & -BITS_PER_WORD; | |
594a51fe | 5622 | } |
594a51fe | 5623 | } |
0b5383eb DJ |
5624 | |
5625 | startbit = intoffset & -BITS_PER_WORD; | |
5626 | endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD; | |
5627 | intregs = (endbit - startbit) / BITS_PER_WORD; | |
5628 | cum->words += intregs; | |
5629 | } | |
5630 | ||
5631 | /* The darwin64 ABI calls for us to recurse down through structs, | |
5632 | looking for elements passed in registers. Unfortunately, we have | |
5633 | to track int register count here also because of misalignments | |
5634 | in powerpc alignment mode. */ | |
5635 | ||
5636 | static void | |
5637 | rs6000_darwin64_record_arg_advance_recurse (CUMULATIVE_ARGS *cum, | |
5638 | tree type, | |
5639 | HOST_WIDE_INT startbitpos) | |
5640 | { | |
5641 | tree f; | |
5642 | ||
5643 | for (f = TYPE_FIELDS (type); f ; f = TREE_CHAIN (f)) | |
5644 | if (TREE_CODE (f) == FIELD_DECL) | |
5645 | { | |
5646 | HOST_WIDE_INT bitpos = startbitpos; | |
5647 | tree ftype = TREE_TYPE (f); | |
70fb00df AP |
5648 | enum machine_mode mode; |
5649 | if (ftype == error_mark_node) | |
5650 | continue; | |
5651 | mode = TYPE_MODE (ftype); | |
0b5383eb DJ |
5652 | |
5653 | if (DECL_SIZE (f) != 0 | |
5654 | && host_integerp (bit_position (f), 1)) | |
5655 | bitpos += int_bit_position (f); | |
5656 | ||
5657 | /* ??? FIXME: else assume zero offset. */ | |
5658 | ||
5659 | if (TREE_CODE (ftype) == RECORD_TYPE) | |
5660 | rs6000_darwin64_record_arg_advance_recurse (cum, ftype, bitpos); | |
5661 | else if (USE_FP_FOR_ARG_P (cum, mode, ftype)) | |
5662 | { | |
5663 | rs6000_darwin64_record_arg_advance_flush (cum, bitpos); | |
5664 | cum->fregno += (GET_MODE_SIZE (mode) + 7) >> 3; | |
5665 | cum->words += (GET_MODE_SIZE (mode) + 7) >> 3; | |
5666 | } | |
5667 | else if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, 1)) | |
5668 | { | |
5669 | rs6000_darwin64_record_arg_advance_flush (cum, bitpos); | |
5670 | cum->vregno++; | |
5671 | cum->words += 2; | |
5672 | } | |
5673 | else if (cum->intoffset == -1) | |
5674 | cum->intoffset = bitpos; | |
5675 | } | |
594a51fe SS |
5676 | } |
5677 | ||
4697a36c MM |
5678 | /* Update the data in CUM to advance over an argument |
5679 | of mode MODE and data type TYPE. | |
b2d04ecf AM |
5680 | (TYPE is null for libcalls where that information may not be available.) |
5681 | ||
5682 | Note that for args passed by reference, function_arg will be called | |
5683 | with MODE and TYPE set to that of the pointer to the arg, not the arg | |
5684 | itself. */ | |
4697a36c MM |
5685 | |
5686 | void | |
f676971a | 5687 | function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode, |
594a51fe | 5688 | tree type, int named, int depth) |
4697a36c | 5689 | { |
0b5383eb DJ |
5690 | int size; |
5691 | ||
594a51fe SS |
5692 | /* Only tick off an argument if we're not recursing. */ |
5693 | if (depth == 0) | |
5694 | cum->nargs_prototype--; | |
4697a36c | 5695 | |
ad630bef DE |
5696 | if (TARGET_ALTIVEC_ABI |
5697 | && (ALTIVEC_VECTOR_MODE (mode) | |
5698 | || (type && TREE_CODE (type) == VECTOR_TYPE | |
5699 | && int_size_in_bytes (type) == 16))) | |
0ac081f6 | 5700 | { |
4ed78545 AM |
5701 | bool stack = false; |
5702 | ||
2858f73a | 5703 | if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named)) |
c4ad648e | 5704 | { |
6d0ef01e HP |
5705 | cum->vregno++; |
5706 | if (!TARGET_ALTIVEC) | |
c85ce869 | 5707 | error ("cannot pass argument in vector register because" |
6d0ef01e | 5708 | " altivec instructions are disabled, use -maltivec" |
c85ce869 | 5709 | " to enable them"); |
4ed78545 AM |
5710 | |
5711 | /* PowerPC64 Linux and AIX allocate GPRs for a vector argument | |
f676971a | 5712 | even if it is going to be passed in a vector register. |
4ed78545 AM |
5713 | Darwin does the same for variable-argument functions. */ |
5714 | if ((DEFAULT_ABI == ABI_AIX && TARGET_64BIT) | |
5715 | || (cum->stdarg && DEFAULT_ABI != ABI_V4)) | |
5716 | stack = true; | |
6d0ef01e | 5717 | } |
4ed78545 AM |
5718 | else |
5719 | stack = true; | |
5720 | ||
5721 | if (stack) | |
c4ad648e | 5722 | { |
a594a19c | 5723 | int align; |
f676971a | 5724 | |
2858f73a GK |
5725 | /* Vector parameters must be 16-byte aligned. This places |
5726 | them at 2 mod 4 in terms of words in 32-bit mode, since | |
5727 | the parameter save area starts at offset 24 from the | |
5728 | stack. In 64-bit mode, they just have to start on an | |
5729 | even word, since the parameter save area is 16-byte | |
5730 | aligned. Space for GPRs is reserved even if the argument | |
5731 | will be passed in memory. */ | |
5732 | if (TARGET_32BIT) | |
4ed78545 | 5733 | align = (2 - cum->words) & 3; |
2858f73a GK |
5734 | else |
5735 | align = cum->words & 1; | |
c53bdcf5 | 5736 | cum->words += align + rs6000_arg_size (mode, type); |
f676971a | 5737 | |
a594a19c GK |
5738 | if (TARGET_DEBUG_ARG) |
5739 | { | |
f676971a | 5740 | fprintf (stderr, "function_adv: words = %2d, align=%d, ", |
a594a19c GK |
5741 | cum->words, align); |
5742 | fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s\n", | |
f676971a | 5743 | cum->nargs_prototype, cum->prototype, |
2858f73a | 5744 | GET_MODE_NAME (mode)); |
a594a19c GK |
5745 | } |
5746 | } | |
0ac081f6 | 5747 | } |
a4b0320c | 5748 | else if (TARGET_SPE_ABI && TARGET_SPE && SPE_VECTOR_MODE (mode) |
a6c9bed4 AH |
5749 | && !cum->stdarg |
5750 | && cum->sysv_gregno <= GP_ARG_MAX_REG) | |
a4b0320c | 5751 | cum->sysv_gregno++; |
594a51fe SS |
5752 | |
5753 | else if (rs6000_darwin64_abi | |
5754 | && mode == BLKmode | |
0b5383eb DJ |
5755 | && TREE_CODE (type) == RECORD_TYPE |
5756 | && (size = int_size_in_bytes (type)) > 0) | |
5757 | { | |
5758 | /* Variable sized types have size == -1 and are | |
5759 | treated as if consisting entirely of ints. | |
5760 | Pad to 16 byte boundary if needed. */ | |
5761 | if (TYPE_ALIGN (type) >= 2 * BITS_PER_WORD | |
5762 | && (cum->words % 2) != 0) | |
5763 | cum->words++; | |
5764 | /* For varargs, we can just go up by the size of the struct. */ | |
5765 | if (!named) | |
5766 | cum->words += (size + 7) / 8; | |
5767 | else | |
5768 | { | |
5769 | /* It is tempting to say int register count just goes up by | |
5770 | sizeof(type)/8, but this is wrong in a case such as | |
5771 | { int; double; int; } [powerpc alignment]. We have to | |
5772 | grovel through the fields for these too. */ | |
5773 | cum->intoffset = 0; | |
5774 | rs6000_darwin64_record_arg_advance_recurse (cum, type, 0); | |
bb8df8a6 | 5775 | rs6000_darwin64_record_arg_advance_flush (cum, |
0b5383eb DJ |
5776 | size * BITS_PER_UNIT); |
5777 | } | |
5778 | } | |
f607bc57 | 5779 | else if (DEFAULT_ABI == ABI_V4) |
4697a36c | 5780 | { |
a3170dc6 | 5781 | if (TARGET_HARD_FLOAT && TARGET_FPRS |
56f4cc04 DE |
5782 | && ((TARGET_SINGLE_FLOAT && mode == SFmode) |
5783 | || (TARGET_DOUBLE_FLOAT && mode == DFmode) | |
5784 | || (mode == TFmode && !TARGET_IEEEQUAD) | |
5785 | || mode == SDmode || mode == DDmode || mode == TDmode)) | |
4697a36c | 5786 | { |
2d83f070 JJ |
5787 | /* _Decimal128 must use an even/odd register pair. This assumes |
5788 | that the register number is odd when fregno is odd. */ | |
5789 | if (mode == TDmode && (cum->fregno % 2) == 1) | |
7393f7f8 BE |
5790 | cum->fregno++; |
5791 | ||
5792 | if (cum->fregno + (mode == TFmode || mode == TDmode ? 1 : 0) | |
5793 | <= FP_ARG_V4_MAX_REG) | |
602ea4d3 | 5794 | cum->fregno += (GET_MODE_SIZE (mode) + 7) >> 3; |
4cc833b7 RH |
5795 | else |
5796 | { | |
602ea4d3 | 5797 | cum->fregno = FP_ARG_V4_MAX_REG + 1; |
4d4447b5 PB |
5798 | if (mode == DFmode || mode == TFmode |
5799 | || mode == DDmode || mode == TDmode) | |
c4ad648e | 5800 | cum->words += cum->words & 1; |
c53bdcf5 | 5801 | cum->words += rs6000_arg_size (mode, type); |
4cc833b7 | 5802 | } |
4697a36c | 5803 | } |
4cc833b7 RH |
5804 | else |
5805 | { | |
b2d04ecf | 5806 | int n_words = rs6000_arg_size (mode, type); |
4cc833b7 RH |
5807 | int gregno = cum->sysv_gregno; |
5808 | ||
4ed78545 AM |
5809 | /* Long long and SPE vectors are put in (r3,r4), (r5,r6), |
5810 | (r7,r8) or (r9,r10). As does any other 2 word item such | |
5811 | as complex int due to a historical mistake. */ | |
5812 | if (n_words == 2) | |
5813 | gregno += (1 - gregno) & 1; | |
4cc833b7 | 5814 | |
4ed78545 | 5815 | /* Multi-reg args are not split between registers and stack. */ |
4cc833b7 RH |
5816 | if (gregno + n_words - 1 > GP_ARG_MAX_REG) |
5817 | { | |
4ed78545 AM |
5818 | /* Long long and SPE vectors are aligned on the stack. |
5819 | So are other 2 word items such as complex int due to | |
5820 | a historical mistake. */ | |
4cc833b7 RH |
5821 | if (n_words == 2) |
5822 | cum->words += cum->words & 1; | |
5823 | cum->words += n_words; | |
5824 | } | |
4697a36c | 5825 | |
4cc833b7 RH |
5826 | /* Note: continuing to accumulate gregno past when we've started |
5827 | spilling to the stack indicates the fact that we've started | |
5828 | spilling to the stack to expand_builtin_saveregs. */ | |
5829 | cum->sysv_gregno = gregno + n_words; | |
5830 | } | |
4697a36c | 5831 | |
4cc833b7 RH |
5832 | if (TARGET_DEBUG_ARG) |
5833 | { | |
5834 | fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ", | |
5835 | cum->words, cum->fregno); | |
5836 | fprintf (stderr, "gregno = %2d, nargs = %4d, proto = %d, ", | |
5837 | cum->sysv_gregno, cum->nargs_prototype, cum->prototype); | |
5838 | fprintf (stderr, "mode = %4s, named = %d\n", | |
5839 | GET_MODE_NAME (mode), named); | |
5840 | } | |
4697a36c MM |
5841 | } |
5842 | else | |
4cc833b7 | 5843 | { |
b2d04ecf | 5844 | int n_words = rs6000_arg_size (mode, type); |
294bd182 AM |
5845 | int start_words = cum->words; |
5846 | int align_words = rs6000_parm_start (mode, type, start_words); | |
a4f6c312 | 5847 | |
294bd182 | 5848 | cum->words = align_words + n_words; |
4697a36c | 5849 | |
ebb109ad | 5850 | if (SCALAR_FLOAT_MODE_P (mode) |
56f4cc04 | 5851 | && TARGET_HARD_FLOAT && TARGET_FPRS) |
2d83f070 JJ |
5852 | { |
5853 | /* _Decimal128 must be passed in an even/odd float register pair. | |
5854 | This assumes that the register number is odd when fregno is | |
5855 | odd. */ | |
5856 | if (mode == TDmode && (cum->fregno % 2) == 1) | |
5857 | cum->fregno++; | |
5858 | cum->fregno += (GET_MODE_SIZE (mode) + 7) >> 3; | |
5859 | } | |
4cc833b7 RH |
5860 | |
5861 | if (TARGET_DEBUG_ARG) | |
5862 | { | |
5863 | fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ", | |
5864 | cum->words, cum->fregno); | |
5865 | fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s, ", | |
5866 | cum->nargs_prototype, cum->prototype, GET_MODE_NAME (mode)); | |
594a51fe | 5867 | fprintf (stderr, "named = %d, align = %d, depth = %d\n", |
294bd182 | 5868 | named, align_words - start_words, depth); |
4cc833b7 RH |
5869 | } |
5870 | } | |
4697a36c | 5871 | } |
a6c9bed4 | 5872 | |
f82f556d AH |
5873 | static rtx |
5874 | spe_build_register_parallel (enum machine_mode mode, int gregno) | |
5875 | { | |
17caeff2 | 5876 | rtx r1, r3, r5, r7; |
f82f556d | 5877 | |
37409796 | 5878 | switch (mode) |
f82f556d | 5879 | { |
37409796 | 5880 | case DFmode: |
54b695e7 AH |
5881 | r1 = gen_rtx_REG (DImode, gregno); |
5882 | r1 = gen_rtx_EXPR_LIST (VOIDmode, r1, const0_rtx); | |
5883 | return gen_rtx_PARALLEL (mode, gen_rtvec (1, r1)); | |
37409796 NS |
5884 | |
5885 | case DCmode: | |
17caeff2 | 5886 | case TFmode: |
54b695e7 AH |
5887 | r1 = gen_rtx_REG (DImode, gregno); |
5888 | r1 = gen_rtx_EXPR_LIST (VOIDmode, r1, const0_rtx); | |
5889 | r3 = gen_rtx_REG (DImode, gregno + 2); | |
5890 | r3 = gen_rtx_EXPR_LIST (VOIDmode, r3, GEN_INT (8)); | |
5891 | return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r3)); | |
37409796 | 5892 | |
17caeff2 JM |
5893 | case TCmode: |
5894 | r1 = gen_rtx_REG (DImode, gregno); | |
5895 | r1 = gen_rtx_EXPR_LIST (VOIDmode, r1, const0_rtx); | |
5896 | r3 = gen_rtx_REG (DImode, gregno + 2); | |
5897 | r3 = gen_rtx_EXPR_LIST (VOIDmode, r3, GEN_INT (8)); | |
5898 | r5 = gen_rtx_REG (DImode, gregno + 4); | |
5899 | r5 = gen_rtx_EXPR_LIST (VOIDmode, r5, GEN_INT (16)); | |
5900 | r7 = gen_rtx_REG (DImode, gregno + 6); | |
5901 | r7 = gen_rtx_EXPR_LIST (VOIDmode, r7, GEN_INT (24)); | |
5902 | return gen_rtx_PARALLEL (mode, gen_rtvec (4, r1, r3, r5, r7)); | |
5903 | ||
37409796 NS |
5904 | default: |
5905 | gcc_unreachable (); | |
f82f556d | 5906 | } |
f82f556d | 5907 | } |
b78d48dd | 5908 | |
f82f556d | 5909 | /* Determine where to put a SIMD argument on the SPE. */ |
a6c9bed4 | 5910 | static rtx |
f676971a | 5911 | rs6000_spe_function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode, |
a2369ed3 | 5912 | tree type) |
a6c9bed4 | 5913 | { |
f82f556d AH |
5914 | int gregno = cum->sysv_gregno; |
5915 | ||
5916 | /* On E500 v2, double arithmetic is done on the full 64-bit GPR, but | |
600e1f95 | 5917 | are passed and returned in a pair of GPRs for ABI compatibility. */ |
4d4447b5 | 5918 | if (TARGET_E500_DOUBLE && (mode == DFmode || mode == TFmode |
4d4447b5 | 5919 | || mode == DCmode || mode == TCmode)) |
f82f556d | 5920 | { |
b5870bee AH |
5921 | int n_words = rs6000_arg_size (mode, type); |
5922 | ||
f82f556d | 5923 | /* Doubles go in an odd/even register pair (r5/r6, etc). */ |
4f011e1e | 5924 | if (mode == DFmode) |
b5870bee | 5925 | gregno += (1 - gregno) & 1; |
f82f556d | 5926 | |
b5870bee AH |
5927 | /* Multi-reg args are not split between registers and stack. */ |
5928 | if (gregno + n_words - 1 > GP_ARG_MAX_REG) | |
f82f556d AH |
5929 | return NULL_RTX; |
5930 | ||
5931 | return spe_build_register_parallel (mode, gregno); | |
5932 | } | |
a6c9bed4 AH |
5933 | if (cum->stdarg) |
5934 | { | |
c53bdcf5 | 5935 | int n_words = rs6000_arg_size (mode, type); |
a6c9bed4 AH |
5936 | |
5937 | /* SPE vectors are put in odd registers. */ | |
5938 | if (n_words == 2 && (gregno & 1) == 0) | |
5939 | gregno += 1; | |
5940 | ||
5941 | if (gregno + n_words - 1 <= GP_ARG_MAX_REG) | |
5942 | { | |
5943 | rtx r1, r2; | |
5944 | enum machine_mode m = SImode; | |
5945 | ||
5946 | r1 = gen_rtx_REG (m, gregno); | |
5947 | r1 = gen_rtx_EXPR_LIST (m, r1, const0_rtx); | |
5948 | r2 = gen_rtx_REG (m, gregno + 1); | |
5949 | r2 = gen_rtx_EXPR_LIST (m, r2, GEN_INT (4)); | |
5950 | return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r2)); | |
5951 | } | |
5952 | else | |
b78d48dd | 5953 | return NULL_RTX; |
a6c9bed4 AH |
5954 | } |
5955 | else | |
5956 | { | |
f82f556d AH |
5957 | if (gregno <= GP_ARG_MAX_REG) |
5958 | return gen_rtx_REG (mode, gregno); | |
a6c9bed4 | 5959 | else |
b78d48dd | 5960 | return NULL_RTX; |
a6c9bed4 AH |
5961 | } |
5962 | } | |
5963 | ||
0b5383eb DJ |
5964 | /* A subroutine of rs6000_darwin64_record_arg. Assign the bits of the |
5965 | structure between cum->intoffset and bitpos to integer registers. */ | |
594a51fe | 5966 | |
0b5383eb | 5967 | static void |
bb8df8a6 | 5968 | rs6000_darwin64_record_arg_flush (CUMULATIVE_ARGS *cum, |
0b5383eb | 5969 | HOST_WIDE_INT bitpos, rtx rvec[], int *k) |
594a51fe | 5970 | { |
0b5383eb DJ |
5971 | enum machine_mode mode; |
5972 | unsigned int regno; | |
5973 | unsigned int startbit, endbit; | |
5974 | int this_regno, intregs, intoffset; | |
5975 | rtx reg; | |
594a51fe | 5976 | |
0b5383eb DJ |
5977 | if (cum->intoffset == -1) |
5978 | return; | |
5979 | ||
5980 | intoffset = cum->intoffset; | |
5981 | cum->intoffset = -1; | |
5982 | ||
5983 | /* If this is the trailing part of a word, try to only load that | |
5984 | much into the register. Otherwise load the whole register. Note | |
5985 | that in the latter case we may pick up unwanted bits. It's not a | |
5986 | problem at the moment but may wish to revisit. */ | |
5987 | ||
5988 | if (intoffset % BITS_PER_WORD != 0) | |
594a51fe | 5989 | { |
0b5383eb DJ |
5990 | mode = mode_for_size (BITS_PER_WORD - intoffset % BITS_PER_WORD, |
5991 | MODE_INT, 0); | |
5992 | if (mode == BLKmode) | |
5993 | { | |
5994 | /* We couldn't find an appropriate mode, which happens, | |
5995 | e.g., in packed structs when there are 3 bytes to load. | |
5996 | Back intoffset back to the beginning of the word in this | |
5997 | case. */ | |
5998 | intoffset = intoffset & -BITS_PER_WORD; | |
5999 | mode = word_mode; | |
6000 | } | |
6001 | } | |
6002 | else | |
6003 | mode = word_mode; | |
6004 | ||
6005 | startbit = intoffset & -BITS_PER_WORD; | |
6006 | endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD; | |
6007 | intregs = (endbit - startbit) / BITS_PER_WORD; | |
6008 | this_regno = cum->words + intoffset / BITS_PER_WORD; | |
6009 | ||
6010 | if (intregs > 0 && intregs > GP_ARG_NUM_REG - this_regno) | |
6011 | cum->use_stack = 1; | |
bb8df8a6 | 6012 | |
0b5383eb DJ |
6013 | intregs = MIN (intregs, GP_ARG_NUM_REG - this_regno); |
6014 | if (intregs <= 0) | |
6015 | return; | |
6016 | ||
6017 | intoffset /= BITS_PER_UNIT; | |
6018 | do | |
6019 | { | |
6020 | regno = GP_ARG_MIN_REG + this_regno; | |
6021 | reg = gen_rtx_REG (mode, regno); | |
6022 | rvec[(*k)++] = | |
6023 | gen_rtx_EXPR_LIST (VOIDmode, reg, GEN_INT (intoffset)); | |
6024 | ||
6025 | this_regno += 1; | |
6026 | intoffset = (intoffset | (UNITS_PER_WORD-1)) + 1; | |
6027 | mode = word_mode; | |
6028 | intregs -= 1; | |
6029 | } | |
6030 | while (intregs > 0); | |
6031 | } | |
6032 | ||
6033 | /* Recursive workhorse for the following. */ | |
6034 | ||
6035 | static void | |
586de218 | 6036 | rs6000_darwin64_record_arg_recurse (CUMULATIVE_ARGS *cum, const_tree type, |
0b5383eb DJ |
6037 | HOST_WIDE_INT startbitpos, rtx rvec[], |
6038 | int *k) | |
6039 | { | |
6040 | tree f; | |
6041 | ||
6042 | for (f = TYPE_FIELDS (type); f ; f = TREE_CHAIN (f)) | |
6043 | if (TREE_CODE (f) == FIELD_DECL) | |
6044 | { | |
6045 | HOST_WIDE_INT bitpos = startbitpos; | |
6046 | tree ftype = TREE_TYPE (f); | |
70fb00df AP |
6047 | enum machine_mode mode; |
6048 | if (ftype == error_mark_node) | |
6049 | continue; | |
6050 | mode = TYPE_MODE (ftype); | |
0b5383eb DJ |
6051 | |
6052 | if (DECL_SIZE (f) != 0 | |
6053 | && host_integerp (bit_position (f), 1)) | |
6054 | bitpos += int_bit_position (f); | |
6055 | ||
6056 | /* ??? FIXME: else assume zero offset. */ | |
6057 | ||
6058 | if (TREE_CODE (ftype) == RECORD_TYPE) | |
6059 | rs6000_darwin64_record_arg_recurse (cum, ftype, bitpos, rvec, k); | |
6060 | else if (cum->named && USE_FP_FOR_ARG_P (cum, mode, ftype)) | |
594a51fe | 6061 | { |
0b5383eb DJ |
6062 | #if 0 |
6063 | switch (mode) | |
594a51fe | 6064 | { |
0b5383eb DJ |
6065 | case SCmode: mode = SFmode; break; |
6066 | case DCmode: mode = DFmode; break; | |
6067 | case TCmode: mode = TFmode; break; | |
6068 | default: break; | |
594a51fe | 6069 | } |
0b5383eb DJ |
6070 | #endif |
6071 | rs6000_darwin64_record_arg_flush (cum, bitpos, rvec, k); | |
6072 | rvec[(*k)++] | |
bb8df8a6 | 6073 | = gen_rtx_EXPR_LIST (VOIDmode, |
0b5383eb DJ |
6074 | gen_rtx_REG (mode, cum->fregno++), |
6075 | GEN_INT (bitpos / BITS_PER_UNIT)); | |
7393f7f8 | 6076 | if (mode == TFmode || mode == TDmode) |
0b5383eb | 6077 | cum->fregno++; |
594a51fe | 6078 | } |
0b5383eb DJ |
6079 | else if (cum->named && USE_ALTIVEC_FOR_ARG_P (cum, mode, ftype, 1)) |
6080 | { | |
6081 | rs6000_darwin64_record_arg_flush (cum, bitpos, rvec, k); | |
6082 | rvec[(*k)++] | |
bb8df8a6 EC |
6083 | = gen_rtx_EXPR_LIST (VOIDmode, |
6084 | gen_rtx_REG (mode, cum->vregno++), | |
0b5383eb DJ |
6085 | GEN_INT (bitpos / BITS_PER_UNIT)); |
6086 | } | |
6087 | else if (cum->intoffset == -1) | |
6088 | cum->intoffset = bitpos; | |
6089 | } | |
6090 | } | |
594a51fe | 6091 | |
0b5383eb DJ |
6092 | /* For the darwin64 ABI, we want to construct a PARALLEL consisting of |
6093 | the register(s) to be used for each field and subfield of a struct | |
6094 | being passed by value, along with the offset of where the | |
6095 | register's value may be found in the block. FP fields go in FP | |
6096 | register, vector fields go in vector registers, and everything | |
bb8df8a6 | 6097 | else goes in int registers, packed as in memory. |
8ff40a74 | 6098 | |
0b5383eb DJ |
6099 | This code is also used for function return values. RETVAL indicates |
6100 | whether this is the case. | |
8ff40a74 | 6101 | |
a4d05547 | 6102 | Much of this is taken from the SPARC V9 port, which has a similar |
0b5383eb | 6103 | calling convention. */ |
594a51fe | 6104 | |
0b5383eb | 6105 | static rtx |
586de218 | 6106 | rs6000_darwin64_record_arg (CUMULATIVE_ARGS *orig_cum, const_tree type, |
0b5383eb DJ |
6107 | int named, bool retval) |
6108 | { | |
6109 | rtx rvec[FIRST_PSEUDO_REGISTER]; | |
6110 | int k = 1, kbase = 1; | |
6111 | HOST_WIDE_INT typesize = int_size_in_bytes (type); | |
6112 | /* This is a copy; modifications are not visible to our caller. */ | |
6113 | CUMULATIVE_ARGS copy_cum = *orig_cum; | |
6114 | CUMULATIVE_ARGS *cum = ©_cum; | |
6115 | ||
6116 | /* Pad to 16 byte boundary if needed. */ | |
6117 | if (!retval && TYPE_ALIGN (type) >= 2 * BITS_PER_WORD | |
6118 | && (cum->words % 2) != 0) | |
6119 | cum->words++; | |
6120 | ||
6121 | cum->intoffset = 0; | |
6122 | cum->use_stack = 0; | |
6123 | cum->named = named; | |
6124 | ||
6125 | /* Put entries into rvec[] for individual FP and vector fields, and | |
6126 | for the chunks of memory that go in int regs. Note we start at | |
6127 | element 1; 0 is reserved for an indication of using memory, and | |
6128 | may or may not be filled in below. */ | |
6129 | rs6000_darwin64_record_arg_recurse (cum, type, 0, rvec, &k); | |
6130 | rs6000_darwin64_record_arg_flush (cum, typesize * BITS_PER_UNIT, rvec, &k); | |
6131 | ||
6132 | /* If any part of the struct went on the stack put all of it there. | |
6133 | This hack is because the generic code for | |
6134 | FUNCTION_ARG_PARTIAL_NREGS cannot handle cases where the register | |
6135 | parts of the struct are not at the beginning. */ | |
6136 | if (cum->use_stack) | |
6137 | { | |
6138 | if (retval) | |
6139 | return NULL_RTX; /* doesn't go in registers at all */ | |
6140 | kbase = 0; | |
6141 | rvec[0] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx); | |
6142 | } | |
6143 | if (k > 1 || cum->use_stack) | |
6144 | return gen_rtx_PARALLEL (BLKmode, gen_rtvec_v (k - kbase, &rvec[kbase])); | |
594a51fe SS |
6145 | else |
6146 | return NULL_RTX; | |
6147 | } | |
6148 | ||
b78d48dd FJ |
6149 | /* Determine where to place an argument in 64-bit mode with 32-bit ABI. */ |
6150 | ||
6151 | static rtx | |
ec6376ab | 6152 | rs6000_mixed_function_arg (enum machine_mode mode, tree type, int align_words) |
b78d48dd | 6153 | { |
ec6376ab AM |
6154 | int n_units; |
6155 | int i, k; | |
6156 | rtx rvec[GP_ARG_NUM_REG + 1]; | |
6157 | ||
6158 | if (align_words >= GP_ARG_NUM_REG) | |
6159 | return NULL_RTX; | |
6160 | ||
6161 | n_units = rs6000_arg_size (mode, type); | |
6162 | ||
6163 | /* Optimize the simple case where the arg fits in one gpr, except in | |
6164 | the case of BLKmode due to assign_parms assuming that registers are | |
6165 | BITS_PER_WORD wide. */ | |
6166 | if (n_units == 0 | |
6167 | || (n_units == 1 && mode != BLKmode)) | |
6168 | return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words); | |
6169 | ||
6170 | k = 0; | |
6171 | if (align_words + n_units > GP_ARG_NUM_REG) | |
6172 | /* Not all of the arg fits in gprs. Say that it goes in memory too, | |
6173 | using a magic NULL_RTX component. | |
79773478 AM |
6174 | This is not strictly correct. Only some of the arg belongs in |
6175 | memory, not all of it. However, the normal scheme using | |
6176 | function_arg_partial_nregs can result in unusual subregs, eg. | |
6177 | (subreg:SI (reg:DF) 4), which are not handled well. The code to | |
6178 | store the whole arg to memory is often more efficient than code | |
6179 | to store pieces, and we know that space is available in the right | |
6180 | place for the whole arg. */ | |
ec6376ab AM |
6181 | rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx); |
6182 | ||
6183 | i = 0; | |
6184 | do | |
36a454e1 | 6185 | { |
ec6376ab AM |
6186 | rtx r = gen_rtx_REG (SImode, GP_ARG_MIN_REG + align_words); |
6187 | rtx off = GEN_INT (i++ * 4); | |
6188 | rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off); | |
36a454e1 | 6189 | } |
ec6376ab AM |
6190 | while (++align_words < GP_ARG_NUM_REG && --n_units != 0); |
6191 | ||
6192 | return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec)); | |
b78d48dd FJ |
6193 | } |
6194 | ||
4697a36c MM |
6195 | /* Determine where to put an argument to a function. |
6196 | Value is zero to push the argument on the stack, | |
6197 | or a hard register in which to store the argument. | |
6198 | ||
6199 | MODE is the argument's machine mode. | |
6200 | TYPE is the data type of the argument (as a tree). | |
6201 | This is null for libcalls where that information may | |
6202 | not be available. | |
6203 | CUM is a variable of type CUMULATIVE_ARGS which gives info about | |
0b5383eb DJ |
6204 | the preceding args and about the function being called. It is |
6205 | not modified in this routine. | |
4697a36c MM |
6206 | NAMED is nonzero if this argument is a named parameter |
6207 | (otherwise it is an extra parameter matching an ellipsis). | |
6208 | ||
6209 | On RS/6000 the first eight words of non-FP are normally in registers | |
6210 | and the rest are pushed. Under AIX, the first 13 FP args are in registers. | |
6211 | Under V.4, the first 8 FP args are in registers. | |
6212 | ||
6213 | If this is floating-point and no prototype is specified, we use | |
6214 | both an FP and integer register (or possibly FP reg and stack). Library | |
b9599e46 | 6215 | functions (when CALL_LIBCALL is set) always have the proper types for args, |
4697a36c | 6216 | so we can pass the FP value just in one register. emit_library_function |
b2d04ecf AM |
6217 | doesn't support PARALLEL anyway. |
6218 | ||
6219 | Note that for args passed by reference, function_arg will be called | |
6220 | with MODE and TYPE set to that of the pointer to the arg, not the arg | |
6221 | itself. */ | |
4697a36c | 6222 | |
9390387d | 6223 | rtx |
f676971a | 6224 | function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode, |
a2369ed3 | 6225 | tree type, int named) |
4697a36c | 6226 | { |
4cc833b7 | 6227 | enum rs6000_abi abi = DEFAULT_ABI; |
4697a36c | 6228 | |
a4f6c312 SS |
6229 | /* Return a marker to indicate whether CR1 needs to set or clear the |
6230 | bit that V.4 uses to say fp args were passed in registers. | |
6231 | Assume that we don't need the marker for software floating point, | |
6232 | or compiler generated library calls. */ | |
4697a36c MM |
6233 | if (mode == VOIDmode) |
6234 | { | |
f607bc57 | 6235 | if (abi == ABI_V4 |
b9599e46 | 6236 | && (cum->call_cookie & CALL_LIBCALL) == 0 |
c1fa753e AM |
6237 | && (cum->stdarg |
6238 | || (cum->nargs_prototype < 0 | |
6239 | && (cum->prototype || TARGET_NO_PROTOTYPE)))) | |
7509c759 | 6240 | { |
a3170dc6 AH |
6241 | /* For the SPE, we need to crxor CR6 always. */ |
6242 | if (TARGET_SPE_ABI) | |
6243 | return GEN_INT (cum->call_cookie | CALL_V4_SET_FP_ARGS); | |
6244 | else if (TARGET_HARD_FLOAT && TARGET_FPRS) | |
6245 | return GEN_INT (cum->call_cookie | |
6246 | | ((cum->fregno == FP_ARG_MIN_REG) | |
6247 | ? CALL_V4_SET_FP_ARGS | |
6248 | : CALL_V4_CLEAR_FP_ARGS)); | |
7509c759 | 6249 | } |
4697a36c | 6250 | |
7509c759 | 6251 | return GEN_INT (cum->call_cookie); |
4697a36c MM |
6252 | } |
6253 | ||
0b5383eb DJ |
6254 | if (rs6000_darwin64_abi && mode == BLKmode |
6255 | && TREE_CODE (type) == RECORD_TYPE) | |
8ff40a74 | 6256 | { |
0b5383eb | 6257 | rtx rslt = rs6000_darwin64_record_arg (cum, type, named, false); |
8ff40a74 SS |
6258 | if (rslt != NULL_RTX) |
6259 | return rslt; | |
6260 | /* Else fall through to usual handling. */ | |
6261 | } | |
6262 | ||
2858f73a | 6263 | if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named)) |
c72d6c26 HP |
6264 | if (TARGET_64BIT && ! cum->prototype) |
6265 | { | |
c4ad648e AM |
6266 | /* Vector parameters get passed in vector register |
6267 | and also in GPRs or memory, in absence of prototype. */ | |
6268 | int align_words; | |
6269 | rtx slot; | |
6270 | align_words = (cum->words + 1) & ~1; | |
6271 | ||
6272 | if (align_words >= GP_ARG_NUM_REG) | |
6273 | { | |
6274 | slot = NULL_RTX; | |
6275 | } | |
6276 | else | |
6277 | { | |
6278 | slot = gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words); | |
6279 | } | |
6280 | return gen_rtx_PARALLEL (mode, | |
6281 | gen_rtvec (2, | |
6282 | gen_rtx_EXPR_LIST (VOIDmode, | |
6283 | slot, const0_rtx), | |
6284 | gen_rtx_EXPR_LIST (VOIDmode, | |
6285 | gen_rtx_REG (mode, cum->vregno), | |
6286 | const0_rtx))); | |
c72d6c26 HP |
6287 | } |
6288 | else | |
6289 | return gen_rtx_REG (mode, cum->vregno); | |
ad630bef DE |
6290 | else if (TARGET_ALTIVEC_ABI |
6291 | && (ALTIVEC_VECTOR_MODE (mode) | |
6292 | || (type && TREE_CODE (type) == VECTOR_TYPE | |
6293 | && int_size_in_bytes (type) == 16))) | |
0ac081f6 | 6294 | { |
2858f73a | 6295 | if (named || abi == ABI_V4) |
a594a19c | 6296 | return NULL_RTX; |
0ac081f6 | 6297 | else |
a594a19c GK |
6298 | { |
6299 | /* Vector parameters to varargs functions under AIX or Darwin | |
6300 | get passed in memory and possibly also in GPRs. */ | |
ec6376ab AM |
6301 | int align, align_words, n_words; |
6302 | enum machine_mode part_mode; | |
a594a19c GK |
6303 | |
6304 | /* Vector parameters must be 16-byte aligned. This places them at | |
2858f73a GK |
6305 | 2 mod 4 in terms of words in 32-bit mode, since the parameter |
6306 | save area starts at offset 24 from the stack. In 64-bit mode, | |
6307 | they just have to start on an even word, since the parameter | |
6308 | save area is 16-byte aligned. */ | |
6309 | if (TARGET_32BIT) | |
4ed78545 | 6310 | align = (2 - cum->words) & 3; |
2858f73a GK |
6311 | else |
6312 | align = cum->words & 1; | |
a594a19c GK |
6313 | align_words = cum->words + align; |
6314 | ||
6315 | /* Out of registers? Memory, then. */ | |
6316 | if (align_words >= GP_ARG_NUM_REG) | |
6317 | return NULL_RTX; | |
ec6376ab AM |
6318 | |
6319 | if (TARGET_32BIT && TARGET_POWERPC64) | |
6320 | return rs6000_mixed_function_arg (mode, type, align_words); | |
6321 | ||
2858f73a GK |
6322 | /* The vector value goes in GPRs. Only the part of the |
6323 | value in GPRs is reported here. */ | |
ec6376ab AM |
6324 | part_mode = mode; |
6325 | n_words = rs6000_arg_size (mode, type); | |
6326 | if (align_words + n_words > GP_ARG_NUM_REG) | |
839a4992 | 6327 | /* Fortunately, there are only two possibilities, the value |
2858f73a GK |
6328 | is either wholly in GPRs or half in GPRs and half not. */ |
6329 | part_mode = DImode; | |
ec6376ab AM |
6330 | |
6331 | return gen_rtx_REG (part_mode, GP_ARG_MIN_REG + align_words); | |
a594a19c | 6332 | } |
0ac081f6 | 6333 | } |
f82f556d AH |
6334 | else if (TARGET_SPE_ABI && TARGET_SPE |
6335 | && (SPE_VECTOR_MODE (mode) | |
18f63bfa | 6336 | || (TARGET_E500_DOUBLE && (mode == DFmode |
17caeff2 JM |
6337 | || mode == DCmode |
6338 | || mode == TFmode | |
6339 | || mode == TCmode)))) | |
a6c9bed4 | 6340 | return rs6000_spe_function_arg (cum, mode, type); |
594a51fe | 6341 | |
f607bc57 | 6342 | else if (abi == ABI_V4) |
4697a36c | 6343 | { |
a3170dc6 | 6344 | if (TARGET_HARD_FLOAT && TARGET_FPRS |
56f4cc04 DE |
6345 | && ((TARGET_SINGLE_FLOAT && mode == SFmode) |
6346 | || (TARGET_DOUBLE_FLOAT && mode == DFmode) | |
cf8e1455 DE |
6347 | || (mode == TFmode && !TARGET_IEEEQUAD) |
6348 | || mode == SDmode || mode == DDmode || mode == TDmode)) | |
4cc833b7 | 6349 | { |
2d83f070 JJ |
6350 | /* _Decimal128 must use an even/odd register pair. This assumes |
6351 | that the register number is odd when fregno is odd. */ | |
6352 | if (mode == TDmode && (cum->fregno % 2) == 1) | |
7393f7f8 BE |
6353 | cum->fregno++; |
6354 | ||
6355 | if (cum->fregno + (mode == TFmode || mode == TDmode ? 1 : 0) | |
6356 | <= FP_ARG_V4_MAX_REG) | |
4cc833b7 RH |
6357 | return gen_rtx_REG (mode, cum->fregno); |
6358 | else | |
b78d48dd | 6359 | return NULL_RTX; |
4cc833b7 RH |
6360 | } |
6361 | else | |
6362 | { | |
b2d04ecf | 6363 | int n_words = rs6000_arg_size (mode, type); |
4cc833b7 RH |
6364 | int gregno = cum->sysv_gregno; |
6365 | ||
4ed78545 AM |
6366 | /* Long long and SPE vectors are put in (r3,r4), (r5,r6), |
6367 | (r7,r8) or (r9,r10). As does any other 2 word item such | |
6368 | as complex int due to a historical mistake. */ | |
6369 | if (n_words == 2) | |
6370 | gregno += (1 - gregno) & 1; | |
4cc833b7 | 6371 | |
4ed78545 | 6372 | /* Multi-reg args are not split between registers and stack. */ |
ec6376ab | 6373 | if (gregno + n_words - 1 > GP_ARG_MAX_REG) |
b78d48dd | 6374 | return NULL_RTX; |
ec6376ab AM |
6375 | |
6376 | if (TARGET_32BIT && TARGET_POWERPC64) | |
6377 | return rs6000_mixed_function_arg (mode, type, | |
6378 | gregno - GP_ARG_MIN_REG); | |
6379 | return gen_rtx_REG (mode, gregno); | |
4cc833b7 | 6380 | } |
4697a36c | 6381 | } |
4cc833b7 RH |
6382 | else |
6383 | { | |
294bd182 | 6384 | int align_words = rs6000_parm_start (mode, type, cum->words); |
b78d48dd | 6385 | |
2d83f070 JJ |
6386 | /* _Decimal128 must be passed in an even/odd float register pair. |
6387 | This assumes that the register number is odd when fregno is odd. */ | |
6388 | if (mode == TDmode && (cum->fregno % 2) == 1) | |
6389 | cum->fregno++; | |
6390 | ||
2858f73a | 6391 | if (USE_FP_FOR_ARG_P (cum, mode, type)) |
4cc833b7 | 6392 | { |
ec6376ab AM |
6393 | rtx rvec[GP_ARG_NUM_REG + 1]; |
6394 | rtx r; | |
6395 | int k; | |
c53bdcf5 AM |
6396 | bool needs_psave; |
6397 | enum machine_mode fmode = mode; | |
c53bdcf5 AM |
6398 | unsigned long n_fpreg = (GET_MODE_SIZE (mode) + 7) >> 3; |
6399 | ||
6400 | if (cum->fregno + n_fpreg > FP_ARG_MAX_REG + 1) | |
6401 | { | |
c53bdcf5 AM |
6402 | /* Currently, we only ever need one reg here because complex |
6403 | doubles are split. */ | |
7393f7f8 BE |
6404 | gcc_assert (cum->fregno == FP_ARG_MAX_REG |
6405 | && (fmode == TFmode || fmode == TDmode)); | |
ec6376ab | 6406 | |
7393f7f8 BE |
6407 | /* Long double or _Decimal128 split over regs and memory. */ |
6408 | fmode = DECIMAL_FLOAT_MODE_P (fmode) ? DDmode : DFmode; | |
c53bdcf5 | 6409 | } |
c53bdcf5 AM |
6410 | |
6411 | /* Do we also need to pass this arg in the parameter save | |
6412 | area? */ | |
6413 | needs_psave = (type | |
6414 | && (cum->nargs_prototype <= 0 | |
6415 | || (DEFAULT_ABI == ABI_AIX | |
de17c25f | 6416 | && TARGET_XL_COMPAT |
c53bdcf5 AM |
6417 | && align_words >= GP_ARG_NUM_REG))); |
6418 | ||
6419 | if (!needs_psave && mode == fmode) | |
ec6376ab | 6420 | return gen_rtx_REG (fmode, cum->fregno); |
c53bdcf5 | 6421 | |
ec6376ab | 6422 | k = 0; |
c53bdcf5 AM |
6423 | if (needs_psave) |
6424 | { | |
ec6376ab | 6425 | /* Describe the part that goes in gprs or the stack. |
c53bdcf5 | 6426 | This piece must come first, before the fprs. */ |
c53bdcf5 AM |
6427 | if (align_words < GP_ARG_NUM_REG) |
6428 | { | |
6429 | unsigned long n_words = rs6000_arg_size (mode, type); | |
ec6376ab AM |
6430 | |
6431 | if (align_words + n_words > GP_ARG_NUM_REG | |
6432 | || (TARGET_32BIT && TARGET_POWERPC64)) | |
6433 | { | |
6434 | /* If this is partially on the stack, then we only | |
6435 | include the portion actually in registers here. */ | |
6436 | enum machine_mode rmode = TARGET_32BIT ? SImode : DImode; | |
6437 | rtx off; | |
79773478 AM |
6438 | int i = 0; |
6439 | if (align_words + n_words > GP_ARG_NUM_REG) | |
c4ad648e AM |
6440 | /* Not all of the arg fits in gprs. Say that it |
6441 | goes in memory too, using a magic NULL_RTX | |
6442 | component. Also see comment in | |
6443 | rs6000_mixed_function_arg for why the normal | |
6444 | function_arg_partial_nregs scheme doesn't work | |
6445 | in this case. */ | |
6446 | rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, | |
6447 | const0_rtx); | |
ec6376ab AM |
6448 | do |
6449 | { | |
6450 | r = gen_rtx_REG (rmode, | |
6451 | GP_ARG_MIN_REG + align_words); | |
2e6c9641 | 6452 | off = GEN_INT (i++ * GET_MODE_SIZE (rmode)); |
ec6376ab AM |
6453 | rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off); |
6454 | } | |
6455 | while (++align_words < GP_ARG_NUM_REG && --n_words != 0); | |
6456 | } | |
6457 | else | |
6458 | { | |
6459 | /* The whole arg fits in gprs. */ | |
6460 | r = gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words); | |
6461 | rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, const0_rtx); | |
6462 | } | |
c53bdcf5 | 6463 | } |
ec6376ab AM |
6464 | else |
6465 | /* It's entirely in memory. */ | |
6466 | rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx); | |
c53bdcf5 AM |
6467 | } |
6468 | ||
ec6376ab AM |
6469 | /* Describe where this piece goes in the fprs. */ |
6470 | r = gen_rtx_REG (fmode, cum->fregno); | |
6471 | rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, const0_rtx); | |
6472 | ||
6473 | return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec)); | |
4cc833b7 RH |
6474 | } |
6475 | else if (align_words < GP_ARG_NUM_REG) | |
b2d04ecf | 6476 | { |
ec6376ab AM |
6477 | if (TARGET_32BIT && TARGET_POWERPC64) |
6478 | return rs6000_mixed_function_arg (mode, type, align_words); | |
b2d04ecf | 6479 | |
4eeca74f AM |
6480 | if (mode == BLKmode) |
6481 | mode = Pmode; | |
6482 | ||
b2d04ecf AM |
6483 | return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words); |
6484 | } | |
4cc833b7 RH |
6485 | else |
6486 | return NULL_RTX; | |
4697a36c | 6487 | } |
4697a36c MM |
6488 | } |
6489 | \f | |
ec6376ab | 6490 | /* For an arg passed partly in registers and partly in memory, this is |
fb63c729 AM |
6491 | the number of bytes passed in registers. For args passed entirely in |
6492 | registers or entirely in memory, zero. When an arg is described by a | |
6493 | PARALLEL, perhaps using more than one register type, this function | |
6494 | returns the number of bytes used by the first element of the PARALLEL. */ | |
4697a36c | 6495 | |
78a52f11 RH |
6496 | static int |
6497 | rs6000_arg_partial_bytes (CUMULATIVE_ARGS *cum, enum machine_mode mode, | |
6498 | tree type, bool named) | |
4697a36c | 6499 | { |
c53bdcf5 | 6500 | int ret = 0; |
ec6376ab | 6501 | int align_words; |
c53bdcf5 | 6502 | |
f607bc57 | 6503 | if (DEFAULT_ABI == ABI_V4) |
4697a36c | 6504 | return 0; |
4697a36c | 6505 | |
c53bdcf5 AM |
6506 | if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named) |
6507 | && cum->nargs_prototype >= 0) | |
6508 | return 0; | |
6509 | ||
0b5383eb DJ |
6510 | /* In this complicated case we just disable the partial_nregs code. */ |
6511 | if (rs6000_darwin64_abi && mode == BLKmode | |
6512 | && TREE_CODE (type) == RECORD_TYPE | |
6513 | && int_size_in_bytes (type) > 0) | |
6514 | return 0; | |
6515 | ||
294bd182 | 6516 | align_words = rs6000_parm_start (mode, type, cum->words); |
ec6376ab | 6517 | |
79773478 AM |
6518 | if (USE_FP_FOR_ARG_P (cum, mode, type)) |
6519 | { | |
fb63c729 AM |
6520 | /* If we are passing this arg in the fixed parameter save area |
6521 | (gprs or memory) as well as fprs, then this function should | |
79773478 AM |
6522 | return the number of partial bytes passed in the parameter |
6523 | save area rather than partial bytes passed in fprs. */ | |
6524 | if (type | |
6525 | && (cum->nargs_prototype <= 0 | |
6526 | || (DEFAULT_ABI == ABI_AIX | |
6527 | && TARGET_XL_COMPAT | |
6528 | && align_words >= GP_ARG_NUM_REG))) | |
6529 | return 0; | |
6530 | else if (cum->fregno + ((GET_MODE_SIZE (mode) + 7) >> 3) | |
6531 | > FP_ARG_MAX_REG + 1) | |
ac7e839c | 6532 | ret = (FP_ARG_MAX_REG + 1 - cum->fregno) * 8; |
c53bdcf5 | 6533 | else if (cum->nargs_prototype >= 0) |
4697a36c MM |
6534 | return 0; |
6535 | } | |
6536 | ||
ec6376ab AM |
6537 | if (align_words < GP_ARG_NUM_REG |
6538 | && GP_ARG_NUM_REG < align_words + rs6000_arg_size (mode, type)) | |
ac7e839c | 6539 | ret = (GP_ARG_NUM_REG - align_words) * (TARGET_32BIT ? 4 : 8); |
78a52f11 | 6540 | |
c53bdcf5 | 6541 | if (ret != 0 && TARGET_DEBUG_ARG) |
78a52f11 | 6542 | fprintf (stderr, "rs6000_arg_partial_bytes: %d\n", ret); |
4697a36c | 6543 | |
c53bdcf5 | 6544 | return ret; |
4697a36c MM |
6545 | } |
6546 | \f | |
6547 | /* A C expression that indicates when an argument must be passed by | |
6548 | reference. If nonzero for an argument, a copy of that argument is | |
6549 | made in memory and a pointer to the argument is passed instead of | |
6550 | the argument itself. The pointer is passed in whatever way is | |
6551 | appropriate for passing a pointer to that type. | |
6552 | ||
b2d04ecf AM |
6553 | Under V.4, aggregates and long double are passed by reference. |
6554 | ||
6555 | As an extension to all 32-bit ABIs, AltiVec vectors are passed by | |
6556 | reference unless the AltiVec vector extension ABI is in force. | |
c8c99a68 DE |
6557 | |
6558 | As an extension to all ABIs, variable sized types are passed by | |
6559 | reference. */ | |
4697a36c | 6560 | |
8cd5a4e0 | 6561 | static bool |
f676971a | 6562 | rs6000_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED, |
586de218 | 6563 | enum machine_mode mode, const_tree type, |
bada2eb8 | 6564 | bool named ATTRIBUTE_UNUSED) |
4697a36c | 6565 | { |
602ea4d3 | 6566 | if (DEFAULT_ABI == ABI_V4 && TARGET_IEEEQUAD && mode == TFmode) |
4697a36c MM |
6567 | { |
6568 | if (TARGET_DEBUG_ARG) | |
bada2eb8 DE |
6569 | fprintf (stderr, "function_arg_pass_by_reference: V4 long double\n"); |
6570 | return 1; | |
6571 | } | |
6572 | ||
6573 | if (!type) | |
6574 | return 0; | |
4697a36c | 6575 | |
bada2eb8 DE |
6576 | if (DEFAULT_ABI == ABI_V4 && AGGREGATE_TYPE_P (type)) |
6577 | { | |
6578 | if (TARGET_DEBUG_ARG) | |
6579 | fprintf (stderr, "function_arg_pass_by_reference: V4 aggregate\n"); | |
6580 | return 1; | |
6581 | } | |
6582 | ||
6583 | if (int_size_in_bytes (type) < 0) | |
6584 | { | |
6585 | if (TARGET_DEBUG_ARG) | |
6586 | fprintf (stderr, "function_arg_pass_by_reference: variable size\n"); | |
6587 | return 1; | |
6588 | } | |
6589 | ||
6590 | /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector | |
6591 | modes only exist for GCC vector types if -maltivec. */ | |
6592 | if (TARGET_32BIT && !TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode)) | |
6593 | { | |
6594 | if (TARGET_DEBUG_ARG) | |
6595 | fprintf (stderr, "function_arg_pass_by_reference: AltiVec\n"); | |
4697a36c MM |
6596 | return 1; |
6597 | } | |
b693336b PB |
6598 | |
6599 | /* Pass synthetic vectors in memory. */ | |
bada2eb8 | 6600 | if (TREE_CODE (type) == VECTOR_TYPE |
ad630bef | 6601 | && int_size_in_bytes (type) > (TARGET_ALTIVEC_ABI ? 16 : 8)) |
b693336b PB |
6602 | { |
6603 | static bool warned_for_pass_big_vectors = false; | |
6604 | if (TARGET_DEBUG_ARG) | |
6605 | fprintf (stderr, "function_arg_pass_by_reference: synthetic vector\n"); | |
6606 | if (!warned_for_pass_big_vectors) | |
6607 | { | |
d4ee4d25 | 6608 | warning (0, "GCC vector passed by reference: " |
b693336b PB |
6609 | "non-standard ABI extension with no compatibility guarantee"); |
6610 | warned_for_pass_big_vectors = true; | |
6611 | } | |
6612 | return 1; | |
6613 | } | |
6614 | ||
b2d04ecf | 6615 | return 0; |
4697a36c | 6616 | } |
5985c7a6 FJ |
6617 | |
6618 | static void | |
2d9db8eb | 6619 | rs6000_move_block_from_reg (int regno, rtx x, int nregs) |
5985c7a6 FJ |
6620 | { |
6621 | int i; | |
6622 | enum machine_mode reg_mode = TARGET_32BIT ? SImode : DImode; | |
6623 | ||
6624 | if (nregs == 0) | |
6625 | return; | |
6626 | ||
c4ad648e | 6627 | for (i = 0; i < nregs; i++) |
5985c7a6 | 6628 | { |
9390387d | 6629 | rtx tem = adjust_address_nv (x, reg_mode, i * GET_MODE_SIZE (reg_mode)); |
5985c7a6 | 6630 | if (reload_completed) |
c4ad648e AM |
6631 | { |
6632 | if (! strict_memory_address_p (reg_mode, XEXP (tem, 0))) | |
6633 | tem = NULL_RTX; | |
6634 | else | |
6635 | tem = simplify_gen_subreg (reg_mode, x, BLKmode, | |
9390387d | 6636 | i * GET_MODE_SIZE (reg_mode)); |
c4ad648e | 6637 | } |
5985c7a6 FJ |
6638 | else |
6639 | tem = replace_equiv_address (tem, XEXP (tem, 0)); | |
6640 | ||
37409796 | 6641 | gcc_assert (tem); |
5985c7a6 FJ |
6642 | |
6643 | emit_move_insn (tem, gen_rtx_REG (reg_mode, regno + i)); | |
6644 | } | |
6645 | } | |
4697a36c MM |
6646 | \f |
6647 | /* Perform any needed actions needed for a function that is receiving a | |
f676971a | 6648 | variable number of arguments. |
4697a36c MM |
6649 | |
6650 | CUM is as above. | |
6651 | ||
6652 | MODE and TYPE are the mode and type of the current parameter. | |
6653 | ||
6654 | PRETEND_SIZE is a variable that should be set to the amount of stack | |
6655 | that must be pushed by the prolog to pretend that our caller pushed | |
6656 | it. | |
6657 | ||
6658 | Normally, this macro will push all remaining incoming registers on the | |
6659 | stack and set PRETEND_SIZE to the length of the registers pushed. */ | |
6660 | ||
c6e8c921 | 6661 | static void |
f676971a | 6662 | setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode, |
c4ad648e AM |
6663 | tree type, int *pretend_size ATTRIBUTE_UNUSED, |
6664 | int no_rtl) | |
4697a36c | 6665 | { |
4cc833b7 RH |
6666 | CUMULATIVE_ARGS next_cum; |
6667 | int reg_size = TARGET_32BIT ? 4 : 8; | |
ca5adc63 | 6668 | rtx save_area = NULL_RTX, mem; |
4862826d ILT |
6669 | int first_reg_offset; |
6670 | alias_set_type set; | |
4697a36c | 6671 | |
f31bf321 | 6672 | /* Skip the last named argument. */ |
d34c5b80 | 6673 | next_cum = *cum; |
594a51fe | 6674 | function_arg_advance (&next_cum, mode, type, 1, 0); |
4cc833b7 | 6675 | |
f607bc57 | 6676 | if (DEFAULT_ABI == ABI_V4) |
d34c5b80 | 6677 | { |
5b667039 JJ |
6678 | first_reg_offset = next_cum.sysv_gregno - GP_ARG_MIN_REG; |
6679 | ||
60e2d0ca | 6680 | if (! no_rtl) |
5b667039 JJ |
6681 | { |
6682 | int gpr_reg_num = 0, gpr_size = 0, fpr_size = 0; | |
6683 | HOST_WIDE_INT offset = 0; | |
6684 | ||
6685 | /* Try to optimize the size of the varargs save area. | |
6686 | The ABI requires that ap.reg_save_area is doubleword | |
6687 | aligned, but we don't need to allocate space for all | |
6688 | the bytes, only those to which we actually will save | |
6689 | anything. */ | |
6690 | if (cfun->va_list_gpr_size && first_reg_offset < GP_ARG_NUM_REG) | |
6691 | gpr_reg_num = GP_ARG_NUM_REG - first_reg_offset; | |
6692 | if (TARGET_HARD_FLOAT && TARGET_FPRS | |
6693 | && next_cum.fregno <= FP_ARG_V4_MAX_REG | |
6694 | && cfun->va_list_fpr_size) | |
6695 | { | |
6696 | if (gpr_reg_num) | |
6697 | fpr_size = (next_cum.fregno - FP_ARG_MIN_REG) | |
6698 | * UNITS_PER_FP_WORD; | |
6699 | if (cfun->va_list_fpr_size | |
6700 | < FP_ARG_V4_MAX_REG + 1 - next_cum.fregno) | |
6701 | fpr_size += cfun->va_list_fpr_size * UNITS_PER_FP_WORD; | |
6702 | else | |
6703 | fpr_size += (FP_ARG_V4_MAX_REG + 1 - next_cum.fregno) | |
6704 | * UNITS_PER_FP_WORD; | |
6705 | } | |
6706 | if (gpr_reg_num) | |
6707 | { | |
6708 | offset = -((first_reg_offset * reg_size) & ~7); | |
6709 | if (!fpr_size && gpr_reg_num > cfun->va_list_gpr_size) | |
6710 | { | |
6711 | gpr_reg_num = cfun->va_list_gpr_size; | |
6712 | if (reg_size == 4 && (first_reg_offset & 1)) | |
6713 | gpr_reg_num++; | |
6714 | } | |
6715 | gpr_size = (gpr_reg_num * reg_size + 7) & ~7; | |
6716 | } | |
6717 | else if (fpr_size) | |
6718 | offset = - (int) (next_cum.fregno - FP_ARG_MIN_REG) | |
6719 | * UNITS_PER_FP_WORD | |
6720 | - (int) (GP_ARG_NUM_REG * reg_size); | |
4cc833b7 | 6721 | |
5b667039 JJ |
6722 | if (gpr_size + fpr_size) |
6723 | { | |
6724 | rtx reg_save_area | |
6725 | = assign_stack_local (BLKmode, gpr_size + fpr_size, 64); | |
6726 | gcc_assert (GET_CODE (reg_save_area) == MEM); | |
6727 | reg_save_area = XEXP (reg_save_area, 0); | |
6728 | if (GET_CODE (reg_save_area) == PLUS) | |
6729 | { | |
6730 | gcc_assert (XEXP (reg_save_area, 0) | |
6731 | == virtual_stack_vars_rtx); | |
6732 | gcc_assert (GET_CODE (XEXP (reg_save_area, 1)) == CONST_INT); | |
6733 | offset += INTVAL (XEXP (reg_save_area, 1)); | |
6734 | } | |
6735 | else | |
6736 | gcc_assert (reg_save_area == virtual_stack_vars_rtx); | |
6737 | } | |
6738 | ||
6739 | cfun->machine->varargs_save_offset = offset; | |
6740 | save_area = plus_constant (virtual_stack_vars_rtx, offset); | |
6741 | } | |
4697a36c | 6742 | } |
60e2d0ca | 6743 | else |
4697a36c | 6744 | { |
d34c5b80 | 6745 | first_reg_offset = next_cum.words; |
4cc833b7 | 6746 | save_area = virtual_incoming_args_rtx; |
4697a36c | 6747 | |
fe984136 | 6748 | if (targetm.calls.must_pass_in_stack (mode, type)) |
c53bdcf5 | 6749 | first_reg_offset += rs6000_arg_size (TYPE_MODE (type), type); |
4cc833b7 | 6750 | } |
4697a36c | 6751 | |
dfafc897 | 6752 | set = get_varargs_alias_set (); |
9d30f3c1 JJ |
6753 | if (! no_rtl && first_reg_offset < GP_ARG_NUM_REG |
6754 | && cfun->va_list_gpr_size) | |
4cc833b7 | 6755 | { |
9d30f3c1 JJ |
6756 | int nregs = GP_ARG_NUM_REG - first_reg_offset; |
6757 | ||
6758 | if (va_list_gpr_counter_field) | |
6759 | { | |
6760 | /* V4 va_list_gpr_size counts number of registers needed. */ | |
6761 | if (nregs > cfun->va_list_gpr_size) | |
6762 | nregs = cfun->va_list_gpr_size; | |
6763 | } | |
6764 | else | |
6765 | { | |
6766 | /* char * va_list instead counts number of bytes needed. */ | |
6767 | if (nregs > cfun->va_list_gpr_size / reg_size) | |
6768 | nregs = cfun->va_list_gpr_size / reg_size; | |
6769 | } | |
6770 | ||
dfafc897 | 6771 | mem = gen_rtx_MEM (BLKmode, |
c4ad648e | 6772 | plus_constant (save_area, |
13e2e16e DE |
6773 | first_reg_offset * reg_size)); |
6774 | MEM_NOTRAP_P (mem) = 1; | |
ba4828e0 | 6775 | set_mem_alias_set (mem, set); |
8ac61af7 | 6776 | set_mem_align (mem, BITS_PER_WORD); |
dfafc897 | 6777 | |
f676971a | 6778 | rs6000_move_block_from_reg (GP_ARG_MIN_REG + first_reg_offset, mem, |
9d30f3c1 | 6779 | nregs); |
4697a36c MM |
6780 | } |
6781 | ||
4697a36c | 6782 | /* Save FP registers if needed. */ |
f607bc57 | 6783 | if (DEFAULT_ABI == ABI_V4 |
a3170dc6 AH |
6784 | && TARGET_HARD_FLOAT && TARGET_FPRS |
6785 | && ! no_rtl | |
9d30f3c1 JJ |
6786 | && next_cum.fregno <= FP_ARG_V4_MAX_REG |
6787 | && cfun->va_list_fpr_size) | |
4697a36c | 6788 | { |
9d30f3c1 | 6789 | int fregno = next_cum.fregno, nregs; |
9ebbca7d | 6790 | rtx cr1 = gen_rtx_REG (CCmode, CR1_REGNO); |
4cc833b7 | 6791 | rtx lab = gen_label_rtx (); |
5b667039 JJ |
6792 | int off = (GP_ARG_NUM_REG * reg_size) + ((fregno - FP_ARG_MIN_REG) |
6793 | * UNITS_PER_FP_WORD); | |
4697a36c | 6794 | |
c4ad648e AM |
6795 | emit_jump_insn |
6796 | (gen_rtx_SET (VOIDmode, | |
6797 | pc_rtx, | |
6798 | gen_rtx_IF_THEN_ELSE (VOIDmode, | |
4cc833b7 | 6799 | gen_rtx_NE (VOIDmode, cr1, |
c4ad648e | 6800 | const0_rtx), |
39403d82 | 6801 | gen_rtx_LABEL_REF (VOIDmode, lab), |
4697a36c MM |
6802 | pc_rtx))); |
6803 | ||
9d30f3c1 JJ |
6804 | for (nregs = 0; |
6805 | fregno <= FP_ARG_V4_MAX_REG && nregs < cfun->va_list_fpr_size; | |
5b667039 | 6806 | fregno++, off += UNITS_PER_FP_WORD, nregs++) |
4cc833b7 | 6807 | { |
696e45ba ME |
6808 | mem = gen_rtx_MEM ((TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT) |
6809 | ? DFmode : SFmode, | |
6810 | plus_constant (save_area, off)); | |
6811 | MEM_NOTRAP_P (mem) = 1; | |
6812 | set_mem_alias_set (mem, set); | |
6813 | set_mem_align (mem, GET_MODE_ALIGNMENT ( | |
6814 | (TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT) | |
6815 | ? DFmode : SFmode)); | |
6816 | emit_move_insn (mem, gen_rtx_REG ( | |
6817 | (TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT) | |
6818 | ? DFmode : SFmode, fregno)); | |
4697a36c | 6819 | } |
4cc833b7 RH |
6820 | |
6821 | emit_label (lab); | |
4697a36c | 6822 | } |
4697a36c | 6823 | } |
4697a36c | 6824 | |
dfafc897 | 6825 | /* Create the va_list data type. */ |
2c4974b7 | 6826 | |
c35d187f RH |
6827 | static tree |
6828 | rs6000_build_builtin_va_list (void) | |
dfafc897 | 6829 | { |
64c2816f | 6830 | tree f_gpr, f_fpr, f_res, f_ovf, f_sav, record, type_decl; |
4697a36c | 6831 | |
9ebbca7d GK |
6832 | /* For AIX, prefer 'char *' because that's what the system |
6833 | header files like. */ | |
f607bc57 | 6834 | if (DEFAULT_ABI != ABI_V4) |
9ebbca7d | 6835 | return build_pointer_type (char_type_node); |
dfafc897 | 6836 | |
f1e639b1 | 6837 | record = (*lang_hooks.types.make_type) (RECORD_TYPE); |
bab45a51 | 6838 | type_decl = build_decl (TYPE_DECL, get_identifier ("__va_list_tag"), record); |
0f4fd75d | 6839 | |
f676971a | 6840 | f_gpr = build_decl (FIELD_DECL, get_identifier ("gpr"), |
9ebbca7d | 6841 | unsigned_char_type_node); |
f676971a | 6842 | f_fpr = build_decl (FIELD_DECL, get_identifier ("fpr"), |
9ebbca7d | 6843 | unsigned_char_type_node); |
64c2816f DT |
6844 | /* Give the two bytes of padding a name, so that -Wpadded won't warn on |
6845 | every user file. */ | |
6846 | f_res = build_decl (FIELD_DECL, get_identifier ("reserved"), | |
6847 | short_unsigned_type_node); | |
dfafc897 FS |
6848 | f_ovf = build_decl (FIELD_DECL, get_identifier ("overflow_arg_area"), |
6849 | ptr_type_node); | |
6850 | f_sav = build_decl (FIELD_DECL, get_identifier ("reg_save_area"), | |
6851 | ptr_type_node); | |
6852 | ||
9d30f3c1 JJ |
6853 | va_list_gpr_counter_field = f_gpr; |
6854 | va_list_fpr_counter_field = f_fpr; | |
6855 | ||
dfafc897 FS |
6856 | DECL_FIELD_CONTEXT (f_gpr) = record; |
6857 | DECL_FIELD_CONTEXT (f_fpr) = record; | |
64c2816f | 6858 | DECL_FIELD_CONTEXT (f_res) = record; |
dfafc897 FS |
6859 | DECL_FIELD_CONTEXT (f_ovf) = record; |
6860 | DECL_FIELD_CONTEXT (f_sav) = record; | |
6861 | ||
bab45a51 FS |
6862 | TREE_CHAIN (record) = type_decl; |
6863 | TYPE_NAME (record) = type_decl; | |
dfafc897 FS |
6864 | TYPE_FIELDS (record) = f_gpr; |
6865 | TREE_CHAIN (f_gpr) = f_fpr; | |
64c2816f DT |
6866 | TREE_CHAIN (f_fpr) = f_res; |
6867 | TREE_CHAIN (f_res) = f_ovf; | |
dfafc897 FS |
6868 | TREE_CHAIN (f_ovf) = f_sav; |
6869 | ||
6870 | layout_type (record); | |
6871 | ||
6872 | /* The correct type is an array type of one element. */ | |
6873 | return build_array_type (record, build_index_type (size_zero_node)); | |
6874 | } | |
6875 | ||
6876 | /* Implement va_start. */ | |
6877 | ||
d7bd8aeb | 6878 | static void |
a2369ed3 | 6879 | rs6000_va_start (tree valist, rtx nextarg) |
4697a36c | 6880 | { |
dfafc897 | 6881 | HOST_WIDE_INT words, n_gpr, n_fpr; |
c566f9bd | 6882 | tree f_gpr, f_fpr, f_res, f_ovf, f_sav; |
dfafc897 | 6883 | tree gpr, fpr, ovf, sav, t; |
2c4974b7 | 6884 | |
dfafc897 | 6885 | /* Only SVR4 needs something special. */ |
f607bc57 | 6886 | if (DEFAULT_ABI != ABI_V4) |
dfafc897 | 6887 | { |
e5faf155 | 6888 | std_expand_builtin_va_start (valist, nextarg); |
dfafc897 FS |
6889 | return; |
6890 | } | |
6891 | ||
973a648b | 6892 | f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node)); |
dfafc897 | 6893 | f_fpr = TREE_CHAIN (f_gpr); |
c566f9bd DT |
6894 | f_res = TREE_CHAIN (f_fpr); |
6895 | f_ovf = TREE_CHAIN (f_res); | |
dfafc897 FS |
6896 | f_sav = TREE_CHAIN (f_ovf); |
6897 | ||
872a65b5 | 6898 | valist = build_va_arg_indirect_ref (valist); |
47a25a46 | 6899 | gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE); |
726a989a RB |
6900 | fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), unshare_expr (valist), |
6901 | f_fpr, NULL_TREE); | |
6902 | ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), unshare_expr (valist), | |
6903 | f_ovf, NULL_TREE); | |
6904 | sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), unshare_expr (valist), | |
6905 | f_sav, NULL_TREE); | |
dfafc897 FS |
6906 | |
6907 | /* Count number of gp and fp argument registers used. */ | |
38173d38 JH |
6908 | words = crtl->args.info.words; |
6909 | n_gpr = MIN (crtl->args.info.sysv_gregno - GP_ARG_MIN_REG, | |
987732e0 | 6910 | GP_ARG_NUM_REG); |
38173d38 | 6911 | n_fpr = MIN (crtl->args.info.fregno - FP_ARG_MIN_REG, |
987732e0 | 6912 | FP_ARG_NUM_REG); |
dfafc897 FS |
6913 | |
6914 | if (TARGET_DEBUG_ARG) | |
4a0a75dd KG |
6915 | fprintf (stderr, "va_start: words = "HOST_WIDE_INT_PRINT_DEC", n_gpr = " |
6916 | HOST_WIDE_INT_PRINT_DEC", n_fpr = "HOST_WIDE_INT_PRINT_DEC"\n", | |
6917 | words, n_gpr, n_fpr); | |
dfafc897 | 6918 | |
9d30f3c1 JJ |
6919 | if (cfun->va_list_gpr_size) |
6920 | { | |
726a989a | 6921 | t = build2 (MODIFY_EXPR, TREE_TYPE (gpr), gpr, |
47a25a46 | 6922 | build_int_cst (NULL_TREE, n_gpr)); |
9d30f3c1 JJ |
6923 | TREE_SIDE_EFFECTS (t) = 1; |
6924 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
6925 | } | |
58c8adc1 | 6926 | |
9d30f3c1 JJ |
6927 | if (cfun->va_list_fpr_size) |
6928 | { | |
726a989a | 6929 | t = build2 (MODIFY_EXPR, TREE_TYPE (fpr), fpr, |
47a25a46 | 6930 | build_int_cst (NULL_TREE, n_fpr)); |
9d30f3c1 JJ |
6931 | TREE_SIDE_EFFECTS (t) = 1; |
6932 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
6933 | } | |
dfafc897 FS |
6934 | |
6935 | /* Find the overflow area. */ | |
6936 | t = make_tree (TREE_TYPE (ovf), virtual_incoming_args_rtx); | |
6937 | if (words != 0) | |
5be014d5 AP |
6938 | t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (ovf), t, |
6939 | size_int (words * UNITS_PER_WORD)); | |
726a989a | 6940 | t = build2 (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t); |
dfafc897 FS |
6941 | TREE_SIDE_EFFECTS (t) = 1; |
6942 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
6943 | ||
9d30f3c1 JJ |
6944 | /* If there were no va_arg invocations, don't set up the register |
6945 | save area. */ | |
6946 | if (!cfun->va_list_gpr_size | |
6947 | && !cfun->va_list_fpr_size | |
6948 | && n_gpr < GP_ARG_NUM_REG | |
6949 | && n_fpr < FP_ARG_V4_MAX_REG) | |
6950 | return; | |
6951 | ||
dfafc897 FS |
6952 | /* Find the register save area. */ |
6953 | t = make_tree (TREE_TYPE (sav), virtual_stack_vars_rtx); | |
5b667039 | 6954 | if (cfun->machine->varargs_save_offset) |
5be014d5 AP |
6955 | t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (sav), t, |
6956 | size_int (cfun->machine->varargs_save_offset)); | |
726a989a | 6957 | t = build2 (MODIFY_EXPR, TREE_TYPE (sav), sav, t); |
dfafc897 FS |
6958 | TREE_SIDE_EFFECTS (t) = 1; |
6959 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
6960 | } | |
6961 | ||
6962 | /* Implement va_arg. */ | |
6963 | ||
23a60a04 | 6964 | tree |
726a989a RB |
6965 | rs6000_gimplify_va_arg (tree valist, tree type, gimple_seq *pre_p, |
6966 | gimple_seq *post_p) | |
cd3ce9b4 | 6967 | { |
cd3ce9b4 JM |
6968 | tree f_gpr, f_fpr, f_res, f_ovf, f_sav; |
6969 | tree gpr, fpr, ovf, sav, reg, t, u; | |
08b0dc1b | 6970 | int size, rsize, n_reg, sav_ofs, sav_scale; |
cd3ce9b4 JM |
6971 | tree lab_false, lab_over, addr; |
6972 | int align; | |
6973 | tree ptrtype = build_pointer_type (type); | |
7393f7f8 | 6974 | int regalign = 0; |
726a989a | 6975 | gimple stmt; |
cd3ce9b4 | 6976 | |
08b0dc1b RH |
6977 | if (pass_by_reference (NULL, TYPE_MODE (type), type, false)) |
6978 | { | |
6979 | t = rs6000_gimplify_va_arg (valist, ptrtype, pre_p, post_p); | |
872a65b5 | 6980 | return build_va_arg_indirect_ref (t); |
08b0dc1b RH |
6981 | } |
6982 | ||
cd3ce9b4 JM |
6983 | if (DEFAULT_ABI != ABI_V4) |
6984 | { | |
08b0dc1b | 6985 | if (targetm.calls.split_complex_arg && TREE_CODE (type) == COMPLEX_TYPE) |
cd3ce9b4 JM |
6986 | { |
6987 | tree elem_type = TREE_TYPE (type); | |
6988 | enum machine_mode elem_mode = TYPE_MODE (elem_type); | |
6989 | int elem_size = GET_MODE_SIZE (elem_mode); | |
6990 | ||
6991 | if (elem_size < UNITS_PER_WORD) | |
6992 | { | |
23a60a04 | 6993 | tree real_part, imag_part; |
726a989a | 6994 | gimple_seq post = NULL; |
cd3ce9b4 | 6995 | |
23a60a04 JM |
6996 | real_part = rs6000_gimplify_va_arg (valist, elem_type, pre_p, |
6997 | &post); | |
6998 | /* Copy the value into a temporary, lest the formal temporary | |
6999 | be reused out from under us. */ | |
7000 | real_part = get_initialized_tmp_var (real_part, pre_p, &post); | |
726a989a | 7001 | gimple_seq_add_seq (pre_p, post); |
cd3ce9b4 | 7002 | |
23a60a04 JM |
7003 | imag_part = rs6000_gimplify_va_arg (valist, elem_type, pre_p, |
7004 | post_p); | |
cd3ce9b4 | 7005 | |
47a25a46 | 7006 | return build2 (COMPLEX_EXPR, type, real_part, imag_part); |
cd3ce9b4 JM |
7007 | } |
7008 | } | |
7009 | ||
23a60a04 | 7010 | return std_gimplify_va_arg_expr (valist, type, pre_p, post_p); |
cd3ce9b4 JM |
7011 | } |
7012 | ||
7013 | f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node)); | |
7014 | f_fpr = TREE_CHAIN (f_gpr); | |
7015 | f_res = TREE_CHAIN (f_fpr); | |
7016 | f_ovf = TREE_CHAIN (f_res); | |
7017 | f_sav = TREE_CHAIN (f_ovf); | |
7018 | ||
872a65b5 | 7019 | valist = build_va_arg_indirect_ref (valist); |
47a25a46 | 7020 | gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE); |
726a989a RB |
7021 | fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), unshare_expr (valist), |
7022 | f_fpr, NULL_TREE); | |
7023 | ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), unshare_expr (valist), | |
7024 | f_ovf, NULL_TREE); | |
7025 | sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), unshare_expr (valist), | |
7026 | f_sav, NULL_TREE); | |
cd3ce9b4 JM |
7027 | |
7028 | size = int_size_in_bytes (type); | |
7029 | rsize = (size + 3) / 4; | |
7030 | align = 1; | |
7031 | ||
08b0dc1b | 7032 | if (TARGET_HARD_FLOAT && TARGET_FPRS |
696e45ba ME |
7033 | && ((TARGET_SINGLE_FLOAT && TYPE_MODE (type) == SFmode) |
7034 | || (TARGET_DOUBLE_FLOAT | |
7035 | && (TYPE_MODE (type) == DFmode | |
7036 | || TYPE_MODE (type) == TFmode | |
7037 | || TYPE_MODE (type) == SDmode | |
7038 | || TYPE_MODE (type) == DDmode | |
7039 | || TYPE_MODE (type) == TDmode)))) | |
cd3ce9b4 JM |
7040 | { |
7041 | /* FP args go in FP registers, if present. */ | |
cd3ce9b4 | 7042 | reg = fpr; |
602ea4d3 | 7043 | n_reg = (size + 7) / 8; |
696e45ba ME |
7044 | sav_ofs = ((TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT) ? 8 : 4) * 4; |
7045 | sav_scale = ((TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT) ? 8 : 4); | |
e41b2a33 | 7046 | if (TYPE_MODE (type) != SFmode && TYPE_MODE (type) != SDmode) |
cd3ce9b4 JM |
7047 | align = 8; |
7048 | } | |
7049 | else | |
7050 | { | |
7051 | /* Otherwise into GP registers. */ | |
cd3ce9b4 JM |
7052 | reg = gpr; |
7053 | n_reg = rsize; | |
7054 | sav_ofs = 0; | |
7055 | sav_scale = 4; | |
7056 | if (n_reg == 2) | |
7057 | align = 8; | |
7058 | } | |
7059 | ||
7060 | /* Pull the value out of the saved registers.... */ | |
7061 | ||
7062 | lab_over = NULL; | |
7063 | addr = create_tmp_var (ptr_type_node, "addr"); | |
7064 | DECL_POINTER_ALIAS_SET (addr) = get_varargs_alias_set (); | |
7065 | ||
7066 | /* AltiVec vectors never go in registers when -mabi=altivec. */ | |
7067 | if (TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (TYPE_MODE (type))) | |
7068 | align = 16; | |
7069 | else | |
7070 | { | |
7071 | lab_false = create_artificial_label (); | |
7072 | lab_over = create_artificial_label (); | |
7073 | ||
7074 | /* Long long and SPE vectors are aligned in the registers. | |
7075 | As are any other 2 gpr item such as complex int due to a | |
7076 | historical mistake. */ | |
7077 | u = reg; | |
602ea4d3 | 7078 | if (n_reg == 2 && reg == gpr) |
cd3ce9b4 | 7079 | { |
7393f7f8 | 7080 | regalign = 1; |
726a989a | 7081 | u = build2 (BIT_AND_EXPR, TREE_TYPE (reg), unshare_expr (reg), |
8fb632eb | 7082 | build_int_cst (TREE_TYPE (reg), n_reg - 1)); |
726a989a RB |
7083 | u = build2 (POSTINCREMENT_EXPR, TREE_TYPE (reg), |
7084 | unshare_expr (reg), u); | |
cd3ce9b4 | 7085 | } |
7393f7f8 BE |
7086 | /* _Decimal128 is passed in even/odd fpr pairs; the stored |
7087 | reg number is 0 for f1, so we want to make it odd. */ | |
7088 | else if (reg == fpr && TYPE_MODE (type) == TDmode) | |
7089 | { | |
726a989a | 7090 | t = build2 (BIT_IOR_EXPR, TREE_TYPE (reg), unshare_expr (reg), |
383e91e4 | 7091 | build_int_cst (TREE_TYPE (reg), 1)); |
726a989a | 7092 | u = build2 (MODIFY_EXPR, void_type_node, unshare_expr (reg), t); |
7393f7f8 | 7093 | } |
cd3ce9b4 | 7094 | |
95674810 | 7095 | t = fold_convert (TREE_TYPE (reg), size_int (8 - n_reg + 1)); |
cd3ce9b4 JM |
7096 | t = build2 (GE_EXPR, boolean_type_node, u, t); |
7097 | u = build1 (GOTO_EXPR, void_type_node, lab_false); | |
7098 | t = build3 (COND_EXPR, void_type_node, t, u, NULL_TREE); | |
7099 | gimplify_and_add (t, pre_p); | |
7100 | ||
7101 | t = sav; | |
7102 | if (sav_ofs) | |
5be014d5 | 7103 | t = build2 (POINTER_PLUS_EXPR, ptr_type_node, sav, size_int (sav_ofs)); |
cd3ce9b4 | 7104 | |
726a989a | 7105 | u = build2 (POSTINCREMENT_EXPR, TREE_TYPE (reg), unshare_expr (reg), |
8fb632eb | 7106 | build_int_cst (TREE_TYPE (reg), n_reg)); |
5be014d5 AP |
7107 | u = fold_convert (sizetype, u); |
7108 | u = build2 (MULT_EXPR, sizetype, u, size_int (sav_scale)); | |
7109 | t = build2 (POINTER_PLUS_EXPR, ptr_type_node, t, u); | |
cd3ce9b4 | 7110 | |
e41b2a33 PB |
7111 | /* _Decimal32 varargs are located in the second word of the 64-bit |
7112 | FP register for 32-bit binaries. */ | |
4f011e1e JM |
7113 | if (!TARGET_POWERPC64 |
7114 | && TARGET_HARD_FLOAT && TARGET_FPRS | |
7115 | && TYPE_MODE (type) == SDmode) | |
e41b2a33 PB |
7116 | t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (t), t, size_int (size)); |
7117 | ||
726a989a | 7118 | gimplify_assign (addr, t, pre_p); |
cd3ce9b4 | 7119 | |
726a989a | 7120 | gimple_seq_add_stmt (pre_p, gimple_build_goto (lab_over)); |
cd3ce9b4 | 7121 | |
726a989a RB |
7122 | stmt = gimple_build_label (lab_false); |
7123 | gimple_seq_add_stmt (pre_p, stmt); | |
cd3ce9b4 | 7124 | |
7393f7f8 | 7125 | if ((n_reg == 2 && !regalign) || n_reg > 2) |
cd3ce9b4 JM |
7126 | { |
7127 | /* Ensure that we don't find any more args in regs. | |
7393f7f8 | 7128 | Alignment has taken care of for special cases. */ |
726a989a | 7129 | gimplify_assign (reg, build_int_cst (TREE_TYPE (reg), 8), pre_p); |
cd3ce9b4 JM |
7130 | } |
7131 | } | |
7132 | ||
7133 | /* ... otherwise out of the overflow area. */ | |
7134 | ||
7135 | /* Care for on-stack alignment if needed. */ | |
7136 | t = ovf; | |
7137 | if (align != 1) | |
7138 | { | |
5be014d5 AP |
7139 | t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (t), t, size_int (align - 1)); |
7140 | t = fold_convert (sizetype, t); | |
4a90aeeb | 7141 | t = build2 (BIT_AND_EXPR, TREE_TYPE (t), t, |
5be014d5 AP |
7142 | size_int (-align)); |
7143 | t = fold_convert (TREE_TYPE (ovf), t); | |
cd3ce9b4 JM |
7144 | } |
7145 | gimplify_expr (&t, pre_p, NULL, is_gimple_val, fb_rvalue); | |
7146 | ||
726a989a | 7147 | gimplify_assign (unshare_expr (addr), t, pre_p); |
cd3ce9b4 | 7148 | |
5be014d5 | 7149 | t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (t), t, size_int (size)); |
726a989a | 7150 | gimplify_assign (unshare_expr (ovf), t, pre_p); |
cd3ce9b4 JM |
7151 | |
7152 | if (lab_over) | |
7153 | { | |
726a989a RB |
7154 | stmt = gimple_build_label (lab_over); |
7155 | gimple_seq_add_stmt (pre_p, stmt); | |
cd3ce9b4 JM |
7156 | } |
7157 | ||
0cfbc62b JM |
7158 | if (STRICT_ALIGNMENT |
7159 | && (TYPE_ALIGN (type) | |
7160 | > (unsigned) BITS_PER_UNIT * (align < 4 ? 4 : align))) | |
7161 | { | |
7162 | /* The value (of type complex double, for example) may not be | |
7163 | aligned in memory in the saved registers, so copy via a | |
7164 | temporary. (This is the same code as used for SPARC.) */ | |
7165 | tree tmp = create_tmp_var (type, "va_arg_tmp"); | |
7166 | tree dest_addr = build_fold_addr_expr (tmp); | |
7167 | ||
5039610b SL |
7168 | tree copy = build_call_expr (implicit_built_in_decls[BUILT_IN_MEMCPY], |
7169 | 3, dest_addr, addr, size_int (rsize * 4)); | |
0cfbc62b JM |
7170 | |
7171 | gimplify_and_add (copy, pre_p); | |
7172 | addr = dest_addr; | |
7173 | } | |
7174 | ||
08b0dc1b | 7175 | addr = fold_convert (ptrtype, addr); |
872a65b5 | 7176 | return build_va_arg_indirect_ref (addr); |
cd3ce9b4 JM |
7177 | } |
7178 | ||
0ac081f6 AH |
7179 | /* Builtins. */ |
7180 | ||
58646b77 PB |
7181 | static void |
7182 | def_builtin (int mask, const char *name, tree type, int code) | |
7183 | { | |
96038623 | 7184 | if ((mask & target_flags) || TARGET_PAIRED_FLOAT) |
58646b77 PB |
7185 | { |
7186 | if (rs6000_builtin_decls[code]) | |
7187 | abort (); | |
7188 | ||
7189 | rs6000_builtin_decls[code] = | |
c79efc4d RÁE |
7190 | add_builtin_function (name, type, code, BUILT_IN_MD, |
7191 | NULL, NULL_TREE); | |
58646b77 PB |
7192 | } |
7193 | } | |
0ac081f6 | 7194 | |
24408032 AH |
7195 | /* Simple ternary operations: VECd = foo (VECa, VECb, VECc). */ |
7196 | ||
2212663f | 7197 | static const struct builtin_description bdesc_3arg[] = |
24408032 AH |
7198 | { |
7199 | { MASK_ALTIVEC, CODE_FOR_altivec_vmaddfp, "__builtin_altivec_vmaddfp", ALTIVEC_BUILTIN_VMADDFP }, | |
7200 | { MASK_ALTIVEC, CODE_FOR_altivec_vmhaddshs, "__builtin_altivec_vmhaddshs", ALTIVEC_BUILTIN_VMHADDSHS }, | |
7201 | { MASK_ALTIVEC, CODE_FOR_altivec_vmhraddshs, "__builtin_altivec_vmhraddshs", ALTIVEC_BUILTIN_VMHRADDSHS }, | |
7202 | { MASK_ALTIVEC, CODE_FOR_altivec_vmladduhm, "__builtin_altivec_vmladduhm", ALTIVEC_BUILTIN_VMLADDUHM}, | |
7203 | { MASK_ALTIVEC, CODE_FOR_altivec_vmsumubm, "__builtin_altivec_vmsumubm", ALTIVEC_BUILTIN_VMSUMUBM }, | |
7204 | { MASK_ALTIVEC, CODE_FOR_altivec_vmsummbm, "__builtin_altivec_vmsummbm", ALTIVEC_BUILTIN_VMSUMMBM }, | |
7205 | { MASK_ALTIVEC, CODE_FOR_altivec_vmsumuhm, "__builtin_altivec_vmsumuhm", ALTIVEC_BUILTIN_VMSUMUHM }, | |
7206 | { MASK_ALTIVEC, CODE_FOR_altivec_vmsumshm, "__builtin_altivec_vmsumshm", ALTIVEC_BUILTIN_VMSUMSHM }, | |
7207 | { MASK_ALTIVEC, CODE_FOR_altivec_vmsumuhs, "__builtin_altivec_vmsumuhs", ALTIVEC_BUILTIN_VMSUMUHS }, | |
7208 | { MASK_ALTIVEC, CODE_FOR_altivec_vmsumshs, "__builtin_altivec_vmsumshs", ALTIVEC_BUILTIN_VMSUMSHS }, | |
f676971a | 7209 | { MASK_ALTIVEC, CODE_FOR_altivec_vnmsubfp, "__builtin_altivec_vnmsubfp", ALTIVEC_BUILTIN_VNMSUBFP }, |
aba5fb01 NS |
7210 | { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v4sf, "__builtin_altivec_vperm_4sf", ALTIVEC_BUILTIN_VPERM_4SF }, |
7211 | { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v4si, "__builtin_altivec_vperm_4si", ALTIVEC_BUILTIN_VPERM_4SI }, | |
7212 | { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v8hi, "__builtin_altivec_vperm_8hi", ALTIVEC_BUILTIN_VPERM_8HI }, | |
7213 | { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v16qi, "__builtin_altivec_vperm_16qi", ALTIVEC_BUILTIN_VPERM_16QI }, | |
7214 | { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v4sf, "__builtin_altivec_vsel_4sf", ALTIVEC_BUILTIN_VSEL_4SF }, | |
7215 | { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v4si, "__builtin_altivec_vsel_4si", ALTIVEC_BUILTIN_VSEL_4SI }, | |
7216 | { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v8hi, "__builtin_altivec_vsel_8hi", ALTIVEC_BUILTIN_VSEL_8HI }, | |
7217 | { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v16qi, "__builtin_altivec_vsel_16qi", ALTIVEC_BUILTIN_VSEL_16QI }, | |
7218 | { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v16qi, "__builtin_altivec_vsldoi_16qi", ALTIVEC_BUILTIN_VSLDOI_16QI }, | |
7219 | { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v8hi, "__builtin_altivec_vsldoi_8hi", ALTIVEC_BUILTIN_VSLDOI_8HI }, | |
7220 | { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v4si, "__builtin_altivec_vsldoi_4si", ALTIVEC_BUILTIN_VSLDOI_4SI }, | |
7221 | { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v4sf, "__builtin_altivec_vsldoi_4sf", ALTIVEC_BUILTIN_VSLDOI_4SF }, | |
58646b77 PB |
7222 | |
7223 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_madd", ALTIVEC_BUILTIN_VEC_MADD }, | |
7224 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_madds", ALTIVEC_BUILTIN_VEC_MADDS }, | |
7225 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mladd", ALTIVEC_BUILTIN_VEC_MLADD }, | |
7226 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mradds", ALTIVEC_BUILTIN_VEC_MRADDS }, | |
7227 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_msum", ALTIVEC_BUILTIN_VEC_MSUM }, | |
7228 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumshm", ALTIVEC_BUILTIN_VEC_VMSUMSHM }, | |
7229 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumuhm", ALTIVEC_BUILTIN_VEC_VMSUMUHM }, | |
7230 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsummbm", ALTIVEC_BUILTIN_VEC_VMSUMMBM }, | |
7231 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumubm", ALTIVEC_BUILTIN_VEC_VMSUMUBM }, | |
7232 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_msums", ALTIVEC_BUILTIN_VEC_MSUMS }, | |
7233 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumshs", ALTIVEC_BUILTIN_VEC_VMSUMSHS }, | |
7234 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumuhs", ALTIVEC_BUILTIN_VEC_VMSUMUHS }, | |
7235 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_nmsub", ALTIVEC_BUILTIN_VEC_NMSUB }, | |
7236 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_perm", ALTIVEC_BUILTIN_VEC_PERM }, | |
7237 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sel", ALTIVEC_BUILTIN_VEC_SEL }, | |
96038623 DE |
7238 | |
7239 | { 0, CODE_FOR_paired_msub, "__builtin_paired_msub", PAIRED_BUILTIN_MSUB }, | |
7240 | { 0, CODE_FOR_paired_madd, "__builtin_paired_madd", PAIRED_BUILTIN_MADD }, | |
7241 | { 0, CODE_FOR_paired_madds0, "__builtin_paired_madds0", PAIRED_BUILTIN_MADDS0 }, | |
7242 | { 0, CODE_FOR_paired_madds1, "__builtin_paired_madds1", PAIRED_BUILTIN_MADDS1 }, | |
7243 | { 0, CODE_FOR_paired_nmsub, "__builtin_paired_nmsub", PAIRED_BUILTIN_NMSUB }, | |
7244 | { 0, CODE_FOR_paired_nmadd, "__builtin_paired_nmadd", PAIRED_BUILTIN_NMADD }, | |
7245 | { 0, CODE_FOR_paired_sum0, "__builtin_paired_sum0", PAIRED_BUILTIN_SUM0 }, | |
7246 | { 0, CODE_FOR_paired_sum1, "__builtin_paired_sum1", PAIRED_BUILTIN_SUM1 }, | |
49e39588 | 7247 | { 0, CODE_FOR_selv2sf4, "__builtin_paired_selv2sf4", PAIRED_BUILTIN_SELV2SF4 }, |
24408032 | 7248 | }; |
2212663f | 7249 | |
95385cbb AH |
7250 | /* DST operations: void foo (void *, const int, const char). */ |
7251 | ||
7252 | static const struct builtin_description bdesc_dst[] = | |
7253 | { | |
7254 | { MASK_ALTIVEC, CODE_FOR_altivec_dst, "__builtin_altivec_dst", ALTIVEC_BUILTIN_DST }, | |
7255 | { MASK_ALTIVEC, CODE_FOR_altivec_dstt, "__builtin_altivec_dstt", ALTIVEC_BUILTIN_DSTT }, | |
7256 | { MASK_ALTIVEC, CODE_FOR_altivec_dstst, "__builtin_altivec_dstst", ALTIVEC_BUILTIN_DSTST }, | |
58646b77 PB |
7257 | { MASK_ALTIVEC, CODE_FOR_altivec_dststt, "__builtin_altivec_dststt", ALTIVEC_BUILTIN_DSTSTT }, |
7258 | ||
7259 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_dst", ALTIVEC_BUILTIN_VEC_DST }, | |
7260 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_dstt", ALTIVEC_BUILTIN_VEC_DSTT }, | |
7261 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_dstst", ALTIVEC_BUILTIN_VEC_DSTST }, | |
7262 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_dststt", ALTIVEC_BUILTIN_VEC_DSTSTT } | |
95385cbb AH |
7263 | }; |
7264 | ||
2212663f | 7265 | /* Simple binary operations: VECc = foo (VECa, VECb). */ |
24408032 | 7266 | |
a3170dc6 | 7267 | static struct builtin_description bdesc_2arg[] = |
0ac081f6 | 7268 | { |
f18c054f DB |
7269 | { MASK_ALTIVEC, CODE_FOR_addv16qi3, "__builtin_altivec_vaddubm", ALTIVEC_BUILTIN_VADDUBM }, |
7270 | { MASK_ALTIVEC, CODE_FOR_addv8hi3, "__builtin_altivec_vadduhm", ALTIVEC_BUILTIN_VADDUHM }, | |
7271 | { MASK_ALTIVEC, CODE_FOR_addv4si3, "__builtin_altivec_vadduwm", ALTIVEC_BUILTIN_VADDUWM }, | |
7272 | { MASK_ALTIVEC, CODE_FOR_addv4sf3, "__builtin_altivec_vaddfp", ALTIVEC_BUILTIN_VADDFP }, | |
0ac081f6 AH |
7273 | { MASK_ALTIVEC, CODE_FOR_altivec_vaddcuw, "__builtin_altivec_vaddcuw", ALTIVEC_BUILTIN_VADDCUW }, |
7274 | { MASK_ALTIVEC, CODE_FOR_altivec_vaddubs, "__builtin_altivec_vaddubs", ALTIVEC_BUILTIN_VADDUBS }, | |
7275 | { MASK_ALTIVEC, CODE_FOR_altivec_vaddsbs, "__builtin_altivec_vaddsbs", ALTIVEC_BUILTIN_VADDSBS }, | |
7276 | { MASK_ALTIVEC, CODE_FOR_altivec_vadduhs, "__builtin_altivec_vadduhs", ALTIVEC_BUILTIN_VADDUHS }, | |
7277 | { MASK_ALTIVEC, CODE_FOR_altivec_vaddshs, "__builtin_altivec_vaddshs", ALTIVEC_BUILTIN_VADDSHS }, | |
7278 | { MASK_ALTIVEC, CODE_FOR_altivec_vadduws, "__builtin_altivec_vadduws", ALTIVEC_BUILTIN_VADDUWS }, | |
7279 | { MASK_ALTIVEC, CODE_FOR_altivec_vaddsws, "__builtin_altivec_vaddsws", ALTIVEC_BUILTIN_VADDSWS }, | |
f18c054f | 7280 | { MASK_ALTIVEC, CODE_FOR_andv4si3, "__builtin_altivec_vand", ALTIVEC_BUILTIN_VAND }, |
aba5fb01 | 7281 | { MASK_ALTIVEC, CODE_FOR_andcv4si3, "__builtin_altivec_vandc", ALTIVEC_BUILTIN_VANDC }, |
0ac081f6 AH |
7282 | { MASK_ALTIVEC, CODE_FOR_altivec_vavgub, "__builtin_altivec_vavgub", ALTIVEC_BUILTIN_VAVGUB }, |
7283 | { MASK_ALTIVEC, CODE_FOR_altivec_vavgsb, "__builtin_altivec_vavgsb", ALTIVEC_BUILTIN_VAVGSB }, | |
7284 | { MASK_ALTIVEC, CODE_FOR_altivec_vavguh, "__builtin_altivec_vavguh", ALTIVEC_BUILTIN_VAVGUH }, | |
7285 | { MASK_ALTIVEC, CODE_FOR_altivec_vavgsh, "__builtin_altivec_vavgsh", ALTIVEC_BUILTIN_VAVGSH }, | |
7286 | { MASK_ALTIVEC, CODE_FOR_altivec_vavguw, "__builtin_altivec_vavguw", ALTIVEC_BUILTIN_VAVGUW }, | |
7287 | { MASK_ALTIVEC, CODE_FOR_altivec_vavgsw, "__builtin_altivec_vavgsw", ALTIVEC_BUILTIN_VAVGSW }, | |
617e0e1d DB |
7288 | { MASK_ALTIVEC, CODE_FOR_altivec_vcfux, "__builtin_altivec_vcfux", ALTIVEC_BUILTIN_VCFUX }, |
7289 | { MASK_ALTIVEC, CODE_FOR_altivec_vcfsx, "__builtin_altivec_vcfsx", ALTIVEC_BUILTIN_VCFSX }, | |
0ac081f6 AH |
7290 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpbfp, "__builtin_altivec_vcmpbfp", ALTIVEC_BUILTIN_VCMPBFP }, |
7291 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequb, "__builtin_altivec_vcmpequb", ALTIVEC_BUILTIN_VCMPEQUB }, | |
7292 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequh, "__builtin_altivec_vcmpequh", ALTIVEC_BUILTIN_VCMPEQUH }, | |
7293 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequw, "__builtin_altivec_vcmpequw", ALTIVEC_BUILTIN_VCMPEQUW }, | |
7294 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpeqfp, "__builtin_altivec_vcmpeqfp", ALTIVEC_BUILTIN_VCMPEQFP }, | |
7295 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgefp, "__builtin_altivec_vcmpgefp", ALTIVEC_BUILTIN_VCMPGEFP }, | |
7296 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtub, "__builtin_altivec_vcmpgtub", ALTIVEC_BUILTIN_VCMPGTUB }, | |
7297 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsb, "__builtin_altivec_vcmpgtsb", ALTIVEC_BUILTIN_VCMPGTSB }, | |
7298 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtuh, "__builtin_altivec_vcmpgtuh", ALTIVEC_BUILTIN_VCMPGTUH }, | |
7299 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsh, "__builtin_altivec_vcmpgtsh", ALTIVEC_BUILTIN_VCMPGTSH }, | |
7300 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtuw, "__builtin_altivec_vcmpgtuw", ALTIVEC_BUILTIN_VCMPGTUW }, | |
7301 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsw, "__builtin_altivec_vcmpgtsw", ALTIVEC_BUILTIN_VCMPGTSW }, | |
7302 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtfp, "__builtin_altivec_vcmpgtfp", ALTIVEC_BUILTIN_VCMPGTFP }, | |
617e0e1d DB |
7303 | { MASK_ALTIVEC, CODE_FOR_altivec_vctsxs, "__builtin_altivec_vctsxs", ALTIVEC_BUILTIN_VCTSXS }, |
7304 | { MASK_ALTIVEC, CODE_FOR_altivec_vctuxs, "__builtin_altivec_vctuxs", ALTIVEC_BUILTIN_VCTUXS }, | |
f18c054f DB |
7305 | { MASK_ALTIVEC, CODE_FOR_umaxv16qi3, "__builtin_altivec_vmaxub", ALTIVEC_BUILTIN_VMAXUB }, |
7306 | { MASK_ALTIVEC, CODE_FOR_smaxv16qi3, "__builtin_altivec_vmaxsb", ALTIVEC_BUILTIN_VMAXSB }, | |
df966bff AH |
7307 | { MASK_ALTIVEC, CODE_FOR_umaxv8hi3, "__builtin_altivec_vmaxuh", ALTIVEC_BUILTIN_VMAXUH }, |
7308 | { MASK_ALTIVEC, CODE_FOR_smaxv8hi3, "__builtin_altivec_vmaxsh", ALTIVEC_BUILTIN_VMAXSH }, | |
7309 | { MASK_ALTIVEC, CODE_FOR_umaxv4si3, "__builtin_altivec_vmaxuw", ALTIVEC_BUILTIN_VMAXUW }, | |
7310 | { MASK_ALTIVEC, CODE_FOR_smaxv4si3, "__builtin_altivec_vmaxsw", ALTIVEC_BUILTIN_VMAXSW }, | |
7311 | { MASK_ALTIVEC, CODE_FOR_smaxv4sf3, "__builtin_altivec_vmaxfp", ALTIVEC_BUILTIN_VMAXFP }, | |
0ac081f6 AH |
7312 | { MASK_ALTIVEC, CODE_FOR_altivec_vmrghb, "__builtin_altivec_vmrghb", ALTIVEC_BUILTIN_VMRGHB }, |
7313 | { MASK_ALTIVEC, CODE_FOR_altivec_vmrghh, "__builtin_altivec_vmrghh", ALTIVEC_BUILTIN_VMRGHH }, | |
7314 | { MASK_ALTIVEC, CODE_FOR_altivec_vmrghw, "__builtin_altivec_vmrghw", ALTIVEC_BUILTIN_VMRGHW }, | |
7315 | { MASK_ALTIVEC, CODE_FOR_altivec_vmrglb, "__builtin_altivec_vmrglb", ALTIVEC_BUILTIN_VMRGLB }, | |
7316 | { MASK_ALTIVEC, CODE_FOR_altivec_vmrglh, "__builtin_altivec_vmrglh", ALTIVEC_BUILTIN_VMRGLH }, | |
7317 | { MASK_ALTIVEC, CODE_FOR_altivec_vmrglw, "__builtin_altivec_vmrglw", ALTIVEC_BUILTIN_VMRGLW }, | |
f18c054f DB |
7318 | { MASK_ALTIVEC, CODE_FOR_uminv16qi3, "__builtin_altivec_vminub", ALTIVEC_BUILTIN_VMINUB }, |
7319 | { MASK_ALTIVEC, CODE_FOR_sminv16qi3, "__builtin_altivec_vminsb", ALTIVEC_BUILTIN_VMINSB }, | |
7320 | { MASK_ALTIVEC, CODE_FOR_uminv8hi3, "__builtin_altivec_vminuh", ALTIVEC_BUILTIN_VMINUH }, | |
7321 | { MASK_ALTIVEC, CODE_FOR_sminv8hi3, "__builtin_altivec_vminsh", ALTIVEC_BUILTIN_VMINSH }, | |
7322 | { MASK_ALTIVEC, CODE_FOR_uminv4si3, "__builtin_altivec_vminuw", ALTIVEC_BUILTIN_VMINUW }, | |
7323 | { MASK_ALTIVEC, CODE_FOR_sminv4si3, "__builtin_altivec_vminsw", ALTIVEC_BUILTIN_VMINSW }, | |
7324 | { MASK_ALTIVEC, CODE_FOR_sminv4sf3, "__builtin_altivec_vminfp", ALTIVEC_BUILTIN_VMINFP }, | |
0ac081f6 AH |
7325 | { MASK_ALTIVEC, CODE_FOR_altivec_vmuleub, "__builtin_altivec_vmuleub", ALTIVEC_BUILTIN_VMULEUB }, |
7326 | { MASK_ALTIVEC, CODE_FOR_altivec_vmulesb, "__builtin_altivec_vmulesb", ALTIVEC_BUILTIN_VMULESB }, | |
7327 | { MASK_ALTIVEC, CODE_FOR_altivec_vmuleuh, "__builtin_altivec_vmuleuh", ALTIVEC_BUILTIN_VMULEUH }, | |
7328 | { MASK_ALTIVEC, CODE_FOR_altivec_vmulesh, "__builtin_altivec_vmulesh", ALTIVEC_BUILTIN_VMULESH }, | |
7329 | { MASK_ALTIVEC, CODE_FOR_altivec_vmuloub, "__builtin_altivec_vmuloub", ALTIVEC_BUILTIN_VMULOUB }, | |
7330 | { MASK_ALTIVEC, CODE_FOR_altivec_vmulosb, "__builtin_altivec_vmulosb", ALTIVEC_BUILTIN_VMULOSB }, | |
7331 | { MASK_ALTIVEC, CODE_FOR_altivec_vmulouh, "__builtin_altivec_vmulouh", ALTIVEC_BUILTIN_VMULOUH }, | |
7332 | { MASK_ALTIVEC, CODE_FOR_altivec_vmulosh, "__builtin_altivec_vmulosh", ALTIVEC_BUILTIN_VMULOSH }, | |
f96bc213 | 7333 | { MASK_ALTIVEC, CODE_FOR_altivec_norv4si3, "__builtin_altivec_vnor", ALTIVEC_BUILTIN_VNOR }, |
f18c054f | 7334 | { MASK_ALTIVEC, CODE_FOR_iorv4si3, "__builtin_altivec_vor", ALTIVEC_BUILTIN_VOR }, |
0ac081f6 AH |
7335 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhum, "__builtin_altivec_vpkuhum", ALTIVEC_BUILTIN_VPKUHUM }, |
7336 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwum, "__builtin_altivec_vpkuwum", ALTIVEC_BUILTIN_VPKUWUM }, | |
7337 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkpx, "__builtin_altivec_vpkpx", ALTIVEC_BUILTIN_VPKPX }, | |
0ac081f6 | 7338 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkshss, "__builtin_altivec_vpkshss", ALTIVEC_BUILTIN_VPKSHSS }, |
0ac081f6 AH |
7339 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkswss, "__builtin_altivec_vpkswss", ALTIVEC_BUILTIN_VPKSWSS }, |
7340 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhus, "__builtin_altivec_vpkuhus", ALTIVEC_BUILTIN_VPKUHUS }, | |
7341 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkshus, "__builtin_altivec_vpkshus", ALTIVEC_BUILTIN_VPKSHUS }, | |
7342 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwus, "__builtin_altivec_vpkuwus", ALTIVEC_BUILTIN_VPKUWUS }, | |
7343 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkswus, "__builtin_altivec_vpkswus", ALTIVEC_BUILTIN_VPKSWUS }, | |
7344 | { MASK_ALTIVEC, CODE_FOR_altivec_vrlb, "__builtin_altivec_vrlb", ALTIVEC_BUILTIN_VRLB }, | |
7345 | { MASK_ALTIVEC, CODE_FOR_altivec_vrlh, "__builtin_altivec_vrlh", ALTIVEC_BUILTIN_VRLH }, | |
7346 | { MASK_ALTIVEC, CODE_FOR_altivec_vrlw, "__builtin_altivec_vrlw", ALTIVEC_BUILTIN_VRLW }, | |
71d46ca5 MM |
7347 | { MASK_ALTIVEC, CODE_FOR_vashlv16qi3, "__builtin_altivec_vslb", ALTIVEC_BUILTIN_VSLB }, |
7348 | { MASK_ALTIVEC, CODE_FOR_vashlv8hi3, "__builtin_altivec_vslh", ALTIVEC_BUILTIN_VSLH }, | |
7349 | { MASK_ALTIVEC, CODE_FOR_vashlv4si3, "__builtin_altivec_vslw", ALTIVEC_BUILTIN_VSLW }, | |
0ac081f6 AH |
7350 | { MASK_ALTIVEC, CODE_FOR_altivec_vsl, "__builtin_altivec_vsl", ALTIVEC_BUILTIN_VSL }, |
7351 | { MASK_ALTIVEC, CODE_FOR_altivec_vslo, "__builtin_altivec_vslo", ALTIVEC_BUILTIN_VSLO }, | |
2212663f DB |
7352 | { MASK_ALTIVEC, CODE_FOR_altivec_vspltb, "__builtin_altivec_vspltb", ALTIVEC_BUILTIN_VSPLTB }, |
7353 | { MASK_ALTIVEC, CODE_FOR_altivec_vsplth, "__builtin_altivec_vsplth", ALTIVEC_BUILTIN_VSPLTH }, | |
7354 | { MASK_ALTIVEC, CODE_FOR_altivec_vspltw, "__builtin_altivec_vspltw", ALTIVEC_BUILTIN_VSPLTW }, | |
71d46ca5 MM |
7355 | { MASK_ALTIVEC, CODE_FOR_vlshrv16qi3, "__builtin_altivec_vsrb", ALTIVEC_BUILTIN_VSRB }, |
7356 | { MASK_ALTIVEC, CODE_FOR_vlshrv8hi3, "__builtin_altivec_vsrh", ALTIVEC_BUILTIN_VSRH }, | |
7357 | { MASK_ALTIVEC, CODE_FOR_vlshrv4si3, "__builtin_altivec_vsrw", ALTIVEC_BUILTIN_VSRW }, | |
7358 | { MASK_ALTIVEC, CODE_FOR_vashrv16qi3, "__builtin_altivec_vsrab", ALTIVEC_BUILTIN_VSRAB }, | |
7359 | { MASK_ALTIVEC, CODE_FOR_vashrv8hi3, "__builtin_altivec_vsrah", ALTIVEC_BUILTIN_VSRAH }, | |
7360 | { MASK_ALTIVEC, CODE_FOR_vashrv4si3, "__builtin_altivec_vsraw", ALTIVEC_BUILTIN_VSRAW }, | |
0ac081f6 AH |
7361 | { MASK_ALTIVEC, CODE_FOR_altivec_vsr, "__builtin_altivec_vsr", ALTIVEC_BUILTIN_VSR }, |
7362 | { MASK_ALTIVEC, CODE_FOR_altivec_vsro, "__builtin_altivec_vsro", ALTIVEC_BUILTIN_VSRO }, | |
f18c054f DB |
7363 | { MASK_ALTIVEC, CODE_FOR_subv16qi3, "__builtin_altivec_vsububm", ALTIVEC_BUILTIN_VSUBUBM }, |
7364 | { MASK_ALTIVEC, CODE_FOR_subv8hi3, "__builtin_altivec_vsubuhm", ALTIVEC_BUILTIN_VSUBUHM }, | |
7365 | { MASK_ALTIVEC, CODE_FOR_subv4si3, "__builtin_altivec_vsubuwm", ALTIVEC_BUILTIN_VSUBUWM }, | |
7366 | { MASK_ALTIVEC, CODE_FOR_subv4sf3, "__builtin_altivec_vsubfp", ALTIVEC_BUILTIN_VSUBFP }, | |
0ac081f6 AH |
7367 | { MASK_ALTIVEC, CODE_FOR_altivec_vsubcuw, "__builtin_altivec_vsubcuw", ALTIVEC_BUILTIN_VSUBCUW }, |
7368 | { MASK_ALTIVEC, CODE_FOR_altivec_vsububs, "__builtin_altivec_vsububs", ALTIVEC_BUILTIN_VSUBUBS }, | |
7369 | { MASK_ALTIVEC, CODE_FOR_altivec_vsubsbs, "__builtin_altivec_vsubsbs", ALTIVEC_BUILTIN_VSUBSBS }, | |
7370 | { MASK_ALTIVEC, CODE_FOR_altivec_vsubuhs, "__builtin_altivec_vsubuhs", ALTIVEC_BUILTIN_VSUBUHS }, | |
7371 | { MASK_ALTIVEC, CODE_FOR_altivec_vsubshs, "__builtin_altivec_vsubshs", ALTIVEC_BUILTIN_VSUBSHS }, | |
7372 | { MASK_ALTIVEC, CODE_FOR_altivec_vsubuws, "__builtin_altivec_vsubuws", ALTIVEC_BUILTIN_VSUBUWS }, | |
7373 | { MASK_ALTIVEC, CODE_FOR_altivec_vsubsws, "__builtin_altivec_vsubsws", ALTIVEC_BUILTIN_VSUBSWS }, | |
7374 | { MASK_ALTIVEC, CODE_FOR_altivec_vsum4ubs, "__builtin_altivec_vsum4ubs", ALTIVEC_BUILTIN_VSUM4UBS }, | |
7375 | { MASK_ALTIVEC, CODE_FOR_altivec_vsum4sbs, "__builtin_altivec_vsum4sbs", ALTIVEC_BUILTIN_VSUM4SBS }, | |
7376 | { MASK_ALTIVEC, CODE_FOR_altivec_vsum4shs, "__builtin_altivec_vsum4shs", ALTIVEC_BUILTIN_VSUM4SHS }, | |
7377 | { MASK_ALTIVEC, CODE_FOR_altivec_vsum2sws, "__builtin_altivec_vsum2sws", ALTIVEC_BUILTIN_VSUM2SWS }, | |
7378 | { MASK_ALTIVEC, CODE_FOR_altivec_vsumsws, "__builtin_altivec_vsumsws", ALTIVEC_BUILTIN_VSUMSWS }, | |
f18c054f | 7379 | { MASK_ALTIVEC, CODE_FOR_xorv4si3, "__builtin_altivec_vxor", ALTIVEC_BUILTIN_VXOR }, |
a3170dc6 | 7380 | |
58646b77 PB |
7381 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_add", ALTIVEC_BUILTIN_VEC_ADD }, |
7382 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddfp", ALTIVEC_BUILTIN_VEC_VADDFP }, | |
7383 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vadduwm", ALTIVEC_BUILTIN_VEC_VADDUWM }, | |
7384 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vadduhm", ALTIVEC_BUILTIN_VEC_VADDUHM }, | |
7385 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddubm", ALTIVEC_BUILTIN_VEC_VADDUBM }, | |
7386 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_addc", ALTIVEC_BUILTIN_VEC_ADDC }, | |
7387 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_adds", ALTIVEC_BUILTIN_VEC_ADDS }, | |
7388 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddsws", ALTIVEC_BUILTIN_VEC_VADDSWS }, | |
7389 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vadduws", ALTIVEC_BUILTIN_VEC_VADDUWS }, | |
7390 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddshs", ALTIVEC_BUILTIN_VEC_VADDSHS }, | |
7391 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vadduhs", ALTIVEC_BUILTIN_VEC_VADDUHS }, | |
7392 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddsbs", ALTIVEC_BUILTIN_VEC_VADDSBS }, | |
7393 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddubs", ALTIVEC_BUILTIN_VEC_VADDUBS }, | |
7394 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_and", ALTIVEC_BUILTIN_VEC_AND }, | |
7395 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_andc", ALTIVEC_BUILTIN_VEC_ANDC }, | |
7396 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_avg", ALTIVEC_BUILTIN_VEC_AVG }, | |
7397 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavgsw", ALTIVEC_BUILTIN_VEC_VAVGSW }, | |
7398 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavguw", ALTIVEC_BUILTIN_VEC_VAVGUW }, | |
7399 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavgsh", ALTIVEC_BUILTIN_VEC_VAVGSH }, | |
7400 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavguh", ALTIVEC_BUILTIN_VEC_VAVGUH }, | |
7401 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavgsb", ALTIVEC_BUILTIN_VEC_VAVGSB }, | |
7402 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavgub", ALTIVEC_BUILTIN_VEC_VAVGUB }, | |
7403 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmpb", ALTIVEC_BUILTIN_VEC_CMPB }, | |
7404 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmpeq", ALTIVEC_BUILTIN_VEC_CMPEQ }, | |
7405 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpeqfp", ALTIVEC_BUILTIN_VEC_VCMPEQFP }, | |
7406 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpequw", ALTIVEC_BUILTIN_VEC_VCMPEQUW }, | |
7407 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpequh", ALTIVEC_BUILTIN_VEC_VCMPEQUH }, | |
7408 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpequb", ALTIVEC_BUILTIN_VEC_VCMPEQUB }, | |
7409 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmpge", ALTIVEC_BUILTIN_VEC_CMPGE }, | |
7410 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmpgt", ALTIVEC_BUILTIN_VEC_CMPGT }, | |
7411 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtfp", ALTIVEC_BUILTIN_VEC_VCMPGTFP }, | |
7412 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtsw", ALTIVEC_BUILTIN_VEC_VCMPGTSW }, | |
7413 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtuw", ALTIVEC_BUILTIN_VEC_VCMPGTUW }, | |
7414 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtsh", ALTIVEC_BUILTIN_VEC_VCMPGTSH }, | |
7415 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtuh", ALTIVEC_BUILTIN_VEC_VCMPGTUH }, | |
7416 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtsb", ALTIVEC_BUILTIN_VEC_VCMPGTSB }, | |
7417 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtub", ALTIVEC_BUILTIN_VEC_VCMPGTUB }, | |
7418 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmple", ALTIVEC_BUILTIN_VEC_CMPLE }, | |
7419 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmplt", ALTIVEC_BUILTIN_VEC_CMPLT }, | |
7420 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_max", ALTIVEC_BUILTIN_VEC_MAX }, | |
7421 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxfp", ALTIVEC_BUILTIN_VEC_VMAXFP }, | |
7422 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxsw", ALTIVEC_BUILTIN_VEC_VMAXSW }, | |
7423 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxuw", ALTIVEC_BUILTIN_VEC_VMAXUW }, | |
7424 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxsh", ALTIVEC_BUILTIN_VEC_VMAXSH }, | |
7425 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxuh", ALTIVEC_BUILTIN_VEC_VMAXUH }, | |
7426 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxsb", ALTIVEC_BUILTIN_VEC_VMAXSB }, | |
7427 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxub", ALTIVEC_BUILTIN_VEC_VMAXUB }, | |
7428 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mergeh", ALTIVEC_BUILTIN_VEC_MERGEH }, | |
7429 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrghw", ALTIVEC_BUILTIN_VEC_VMRGHW }, | |
7430 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrghh", ALTIVEC_BUILTIN_VEC_VMRGHH }, | |
7431 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrghb", ALTIVEC_BUILTIN_VEC_VMRGHB }, | |
7432 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mergel", ALTIVEC_BUILTIN_VEC_MERGEL }, | |
7433 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrglw", ALTIVEC_BUILTIN_VEC_VMRGLW }, | |
7434 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrglh", ALTIVEC_BUILTIN_VEC_VMRGLH }, | |
7435 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrglb", ALTIVEC_BUILTIN_VEC_VMRGLB }, | |
7436 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_min", ALTIVEC_BUILTIN_VEC_MIN }, | |
7437 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminfp", ALTIVEC_BUILTIN_VEC_VMINFP }, | |
7438 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminsw", ALTIVEC_BUILTIN_VEC_VMINSW }, | |
7439 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminuw", ALTIVEC_BUILTIN_VEC_VMINUW }, | |
7440 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminsh", ALTIVEC_BUILTIN_VEC_VMINSH }, | |
7441 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminuh", ALTIVEC_BUILTIN_VEC_VMINUH }, | |
7442 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminsb", ALTIVEC_BUILTIN_VEC_VMINSB }, | |
7443 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminub", ALTIVEC_BUILTIN_VEC_VMINUB }, | |
7444 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mule", ALTIVEC_BUILTIN_VEC_MULE }, | |
7445 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmuleub", ALTIVEC_BUILTIN_VEC_VMULEUB }, | |
7446 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulesb", ALTIVEC_BUILTIN_VEC_VMULESB }, | |
7447 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmuleuh", ALTIVEC_BUILTIN_VEC_VMULEUH }, | |
7448 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulesh", ALTIVEC_BUILTIN_VEC_VMULESH }, | |
7449 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mulo", ALTIVEC_BUILTIN_VEC_MULO }, | |
7450 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulosh", ALTIVEC_BUILTIN_VEC_VMULOSH }, | |
7451 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulouh", ALTIVEC_BUILTIN_VEC_VMULOUH }, | |
7452 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulosb", ALTIVEC_BUILTIN_VEC_VMULOSB }, | |
7453 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmuloub", ALTIVEC_BUILTIN_VEC_VMULOUB }, | |
7454 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_nor", ALTIVEC_BUILTIN_VEC_NOR }, | |
7455 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_or", ALTIVEC_BUILTIN_VEC_OR }, | |
7456 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_pack", ALTIVEC_BUILTIN_VEC_PACK }, | |
7457 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkuwum", ALTIVEC_BUILTIN_VEC_VPKUWUM }, | |
7458 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkuhum", ALTIVEC_BUILTIN_VEC_VPKUHUM }, | |
7459 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_packpx", ALTIVEC_BUILTIN_VEC_PACKPX }, | |
7460 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_packs", ALTIVEC_BUILTIN_VEC_PACKS }, | |
7461 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkswss", ALTIVEC_BUILTIN_VEC_VPKSWSS }, | |
7462 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkuwus", ALTIVEC_BUILTIN_VEC_VPKUWUS }, | |
7463 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkshss", ALTIVEC_BUILTIN_VEC_VPKSHSS }, | |
7464 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkuhus", ALTIVEC_BUILTIN_VEC_VPKUHUS }, | |
7465 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_packsu", ALTIVEC_BUILTIN_VEC_PACKSU }, | |
7466 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkswus", ALTIVEC_BUILTIN_VEC_VPKSWUS }, | |
7467 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkshus", ALTIVEC_BUILTIN_VEC_VPKSHUS }, | |
7468 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_rl", ALTIVEC_BUILTIN_VEC_RL }, | |
7469 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vrlw", ALTIVEC_BUILTIN_VEC_VRLW }, | |
7470 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vrlh", ALTIVEC_BUILTIN_VEC_VRLH }, | |
7471 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vrlb", ALTIVEC_BUILTIN_VEC_VRLB }, | |
7472 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sl", ALTIVEC_BUILTIN_VEC_SL }, | |
7473 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vslw", ALTIVEC_BUILTIN_VEC_VSLW }, | |
7474 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vslh", ALTIVEC_BUILTIN_VEC_VSLH }, | |
7475 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vslb", ALTIVEC_BUILTIN_VEC_VSLB }, | |
7476 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sll", ALTIVEC_BUILTIN_VEC_SLL }, | |
7477 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_slo", ALTIVEC_BUILTIN_VEC_SLO }, | |
7478 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sr", ALTIVEC_BUILTIN_VEC_SR }, | |
7479 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrw", ALTIVEC_BUILTIN_VEC_VSRW }, | |
7480 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrh", ALTIVEC_BUILTIN_VEC_VSRH }, | |
7481 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrb", ALTIVEC_BUILTIN_VEC_VSRB }, | |
7482 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sra", ALTIVEC_BUILTIN_VEC_SRA }, | |
7483 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsraw", ALTIVEC_BUILTIN_VEC_VSRAW }, | |
7484 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrah", ALTIVEC_BUILTIN_VEC_VSRAH }, | |
7485 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrab", ALTIVEC_BUILTIN_VEC_VSRAB }, | |
7486 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_srl", ALTIVEC_BUILTIN_VEC_SRL }, | |
7487 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sro", ALTIVEC_BUILTIN_VEC_SRO }, | |
7488 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sub", ALTIVEC_BUILTIN_VEC_SUB }, | |
7489 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubfp", ALTIVEC_BUILTIN_VEC_VSUBFP }, | |
7490 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubuwm", ALTIVEC_BUILTIN_VEC_VSUBUWM }, | |
7491 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubuhm", ALTIVEC_BUILTIN_VEC_VSUBUHM }, | |
7492 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsububm", ALTIVEC_BUILTIN_VEC_VSUBUBM }, | |
7493 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_subc", ALTIVEC_BUILTIN_VEC_SUBC }, | |
7494 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_subs", ALTIVEC_BUILTIN_VEC_SUBS }, | |
7495 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubsws", ALTIVEC_BUILTIN_VEC_VSUBSWS }, | |
7496 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubuws", ALTIVEC_BUILTIN_VEC_VSUBUWS }, | |
7497 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubshs", ALTIVEC_BUILTIN_VEC_VSUBSHS }, | |
7498 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubuhs", ALTIVEC_BUILTIN_VEC_VSUBUHS }, | |
7499 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubsbs", ALTIVEC_BUILTIN_VEC_VSUBSBS }, | |
7500 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsububs", ALTIVEC_BUILTIN_VEC_VSUBUBS }, | |
7501 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sum4s", ALTIVEC_BUILTIN_VEC_SUM4S }, | |
7502 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsum4shs", ALTIVEC_BUILTIN_VEC_VSUM4SHS }, | |
7503 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsum4sbs", ALTIVEC_BUILTIN_VEC_VSUM4SBS }, | |
7504 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsum4ubs", ALTIVEC_BUILTIN_VEC_VSUM4UBS }, | |
7505 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sum2s", ALTIVEC_BUILTIN_VEC_SUM2S }, | |
7506 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sums", ALTIVEC_BUILTIN_VEC_SUMS }, | |
7507 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_xor", ALTIVEC_BUILTIN_VEC_XOR }, | |
7508 | ||
96038623 DE |
7509 | { 0, CODE_FOR_divv2sf3, "__builtin_paired_divv2sf3", PAIRED_BUILTIN_DIVV2SF3 }, |
7510 | { 0, CODE_FOR_addv2sf3, "__builtin_paired_addv2sf3", PAIRED_BUILTIN_ADDV2SF3 }, | |
7511 | { 0, CODE_FOR_subv2sf3, "__builtin_paired_subv2sf3", PAIRED_BUILTIN_SUBV2SF3 }, | |
7512 | { 0, CODE_FOR_mulv2sf3, "__builtin_paired_mulv2sf3", PAIRED_BUILTIN_MULV2SF3 }, | |
7513 | { 0, CODE_FOR_paired_muls0, "__builtin_paired_muls0", PAIRED_BUILTIN_MULS0 }, | |
7514 | { 0, CODE_FOR_paired_muls1, "__builtin_paired_muls1", PAIRED_BUILTIN_MULS1 }, | |
7515 | { 0, CODE_FOR_paired_merge00, "__builtin_paired_merge00", PAIRED_BUILTIN_MERGE00 }, | |
7516 | { 0, CODE_FOR_paired_merge01, "__builtin_paired_merge01", PAIRED_BUILTIN_MERGE01 }, | |
7517 | { 0, CODE_FOR_paired_merge10, "__builtin_paired_merge10", PAIRED_BUILTIN_MERGE10 }, | |
7518 | { 0, CODE_FOR_paired_merge11, "__builtin_paired_merge11", PAIRED_BUILTIN_MERGE11 }, | |
7519 | ||
a3170dc6 AH |
7520 | /* Place holder, leave as first spe builtin. */ |
7521 | { 0, CODE_FOR_spe_evaddw, "__builtin_spe_evaddw", SPE_BUILTIN_EVADDW }, | |
7522 | { 0, CODE_FOR_spe_evand, "__builtin_spe_evand", SPE_BUILTIN_EVAND }, | |
7523 | { 0, CODE_FOR_spe_evandc, "__builtin_spe_evandc", SPE_BUILTIN_EVANDC }, | |
7524 | { 0, CODE_FOR_spe_evdivws, "__builtin_spe_evdivws", SPE_BUILTIN_EVDIVWS }, | |
7525 | { 0, CODE_FOR_spe_evdivwu, "__builtin_spe_evdivwu", SPE_BUILTIN_EVDIVWU }, | |
7526 | { 0, CODE_FOR_spe_eveqv, "__builtin_spe_eveqv", SPE_BUILTIN_EVEQV }, | |
7527 | { 0, CODE_FOR_spe_evfsadd, "__builtin_spe_evfsadd", SPE_BUILTIN_EVFSADD }, | |
7528 | { 0, CODE_FOR_spe_evfsdiv, "__builtin_spe_evfsdiv", SPE_BUILTIN_EVFSDIV }, | |
7529 | { 0, CODE_FOR_spe_evfsmul, "__builtin_spe_evfsmul", SPE_BUILTIN_EVFSMUL }, | |
7530 | { 0, CODE_FOR_spe_evfssub, "__builtin_spe_evfssub", SPE_BUILTIN_EVFSSUB }, | |
7531 | { 0, CODE_FOR_spe_evmergehi, "__builtin_spe_evmergehi", SPE_BUILTIN_EVMERGEHI }, | |
7532 | { 0, CODE_FOR_spe_evmergehilo, "__builtin_spe_evmergehilo", SPE_BUILTIN_EVMERGEHILO }, | |
7533 | { 0, CODE_FOR_spe_evmergelo, "__builtin_spe_evmergelo", SPE_BUILTIN_EVMERGELO }, | |
7534 | { 0, CODE_FOR_spe_evmergelohi, "__builtin_spe_evmergelohi", SPE_BUILTIN_EVMERGELOHI }, | |
7535 | { 0, CODE_FOR_spe_evmhegsmfaa, "__builtin_spe_evmhegsmfaa", SPE_BUILTIN_EVMHEGSMFAA }, | |
7536 | { 0, CODE_FOR_spe_evmhegsmfan, "__builtin_spe_evmhegsmfan", SPE_BUILTIN_EVMHEGSMFAN }, | |
7537 | { 0, CODE_FOR_spe_evmhegsmiaa, "__builtin_spe_evmhegsmiaa", SPE_BUILTIN_EVMHEGSMIAA }, | |
7538 | { 0, CODE_FOR_spe_evmhegsmian, "__builtin_spe_evmhegsmian", SPE_BUILTIN_EVMHEGSMIAN }, | |
7539 | { 0, CODE_FOR_spe_evmhegumiaa, "__builtin_spe_evmhegumiaa", SPE_BUILTIN_EVMHEGUMIAA }, | |
7540 | { 0, CODE_FOR_spe_evmhegumian, "__builtin_spe_evmhegumian", SPE_BUILTIN_EVMHEGUMIAN }, | |
7541 | { 0, CODE_FOR_spe_evmhesmf, "__builtin_spe_evmhesmf", SPE_BUILTIN_EVMHESMF }, | |
7542 | { 0, CODE_FOR_spe_evmhesmfa, "__builtin_spe_evmhesmfa", SPE_BUILTIN_EVMHESMFA }, | |
7543 | { 0, CODE_FOR_spe_evmhesmfaaw, "__builtin_spe_evmhesmfaaw", SPE_BUILTIN_EVMHESMFAAW }, | |
7544 | { 0, CODE_FOR_spe_evmhesmfanw, "__builtin_spe_evmhesmfanw", SPE_BUILTIN_EVMHESMFANW }, | |
7545 | { 0, CODE_FOR_spe_evmhesmi, "__builtin_spe_evmhesmi", SPE_BUILTIN_EVMHESMI }, | |
7546 | { 0, CODE_FOR_spe_evmhesmia, "__builtin_spe_evmhesmia", SPE_BUILTIN_EVMHESMIA }, | |
7547 | { 0, CODE_FOR_spe_evmhesmiaaw, "__builtin_spe_evmhesmiaaw", SPE_BUILTIN_EVMHESMIAAW }, | |
7548 | { 0, CODE_FOR_spe_evmhesmianw, "__builtin_spe_evmhesmianw", SPE_BUILTIN_EVMHESMIANW }, | |
7549 | { 0, CODE_FOR_spe_evmhessf, "__builtin_spe_evmhessf", SPE_BUILTIN_EVMHESSF }, | |
7550 | { 0, CODE_FOR_spe_evmhessfa, "__builtin_spe_evmhessfa", SPE_BUILTIN_EVMHESSFA }, | |
7551 | { 0, CODE_FOR_spe_evmhessfaaw, "__builtin_spe_evmhessfaaw", SPE_BUILTIN_EVMHESSFAAW }, | |
7552 | { 0, CODE_FOR_spe_evmhessfanw, "__builtin_spe_evmhessfanw", SPE_BUILTIN_EVMHESSFANW }, | |
7553 | { 0, CODE_FOR_spe_evmhessiaaw, "__builtin_spe_evmhessiaaw", SPE_BUILTIN_EVMHESSIAAW }, | |
7554 | { 0, CODE_FOR_spe_evmhessianw, "__builtin_spe_evmhessianw", SPE_BUILTIN_EVMHESSIANW }, | |
7555 | { 0, CODE_FOR_spe_evmheumi, "__builtin_spe_evmheumi", SPE_BUILTIN_EVMHEUMI }, | |
7556 | { 0, CODE_FOR_spe_evmheumia, "__builtin_spe_evmheumia", SPE_BUILTIN_EVMHEUMIA }, | |
7557 | { 0, CODE_FOR_spe_evmheumiaaw, "__builtin_spe_evmheumiaaw", SPE_BUILTIN_EVMHEUMIAAW }, | |
7558 | { 0, CODE_FOR_spe_evmheumianw, "__builtin_spe_evmheumianw", SPE_BUILTIN_EVMHEUMIANW }, | |
7559 | { 0, CODE_FOR_spe_evmheusiaaw, "__builtin_spe_evmheusiaaw", SPE_BUILTIN_EVMHEUSIAAW }, | |
7560 | { 0, CODE_FOR_spe_evmheusianw, "__builtin_spe_evmheusianw", SPE_BUILTIN_EVMHEUSIANW }, | |
7561 | { 0, CODE_FOR_spe_evmhogsmfaa, "__builtin_spe_evmhogsmfaa", SPE_BUILTIN_EVMHOGSMFAA }, | |
7562 | { 0, CODE_FOR_spe_evmhogsmfan, "__builtin_spe_evmhogsmfan", SPE_BUILTIN_EVMHOGSMFAN }, | |
7563 | { 0, CODE_FOR_spe_evmhogsmiaa, "__builtin_spe_evmhogsmiaa", SPE_BUILTIN_EVMHOGSMIAA }, | |
7564 | { 0, CODE_FOR_spe_evmhogsmian, "__builtin_spe_evmhogsmian", SPE_BUILTIN_EVMHOGSMIAN }, | |
7565 | { 0, CODE_FOR_spe_evmhogumiaa, "__builtin_spe_evmhogumiaa", SPE_BUILTIN_EVMHOGUMIAA }, | |
7566 | { 0, CODE_FOR_spe_evmhogumian, "__builtin_spe_evmhogumian", SPE_BUILTIN_EVMHOGUMIAN }, | |
7567 | { 0, CODE_FOR_spe_evmhosmf, "__builtin_spe_evmhosmf", SPE_BUILTIN_EVMHOSMF }, | |
7568 | { 0, CODE_FOR_spe_evmhosmfa, "__builtin_spe_evmhosmfa", SPE_BUILTIN_EVMHOSMFA }, | |
7569 | { 0, CODE_FOR_spe_evmhosmfaaw, "__builtin_spe_evmhosmfaaw", SPE_BUILTIN_EVMHOSMFAAW }, | |
7570 | { 0, CODE_FOR_spe_evmhosmfanw, "__builtin_spe_evmhosmfanw", SPE_BUILTIN_EVMHOSMFANW }, | |
7571 | { 0, CODE_FOR_spe_evmhosmi, "__builtin_spe_evmhosmi", SPE_BUILTIN_EVMHOSMI }, | |
7572 | { 0, CODE_FOR_spe_evmhosmia, "__builtin_spe_evmhosmia", SPE_BUILTIN_EVMHOSMIA }, | |
7573 | { 0, CODE_FOR_spe_evmhosmiaaw, "__builtin_spe_evmhosmiaaw", SPE_BUILTIN_EVMHOSMIAAW }, | |
7574 | { 0, CODE_FOR_spe_evmhosmianw, "__builtin_spe_evmhosmianw", SPE_BUILTIN_EVMHOSMIANW }, | |
7575 | { 0, CODE_FOR_spe_evmhossf, "__builtin_spe_evmhossf", SPE_BUILTIN_EVMHOSSF }, | |
7576 | { 0, CODE_FOR_spe_evmhossfa, "__builtin_spe_evmhossfa", SPE_BUILTIN_EVMHOSSFA }, | |
7577 | { 0, CODE_FOR_spe_evmhossfaaw, "__builtin_spe_evmhossfaaw", SPE_BUILTIN_EVMHOSSFAAW }, | |
7578 | { 0, CODE_FOR_spe_evmhossfanw, "__builtin_spe_evmhossfanw", SPE_BUILTIN_EVMHOSSFANW }, | |
7579 | { 0, CODE_FOR_spe_evmhossiaaw, "__builtin_spe_evmhossiaaw", SPE_BUILTIN_EVMHOSSIAAW }, | |
7580 | { 0, CODE_FOR_spe_evmhossianw, "__builtin_spe_evmhossianw", SPE_BUILTIN_EVMHOSSIANW }, | |
7581 | { 0, CODE_FOR_spe_evmhoumi, "__builtin_spe_evmhoumi", SPE_BUILTIN_EVMHOUMI }, | |
7582 | { 0, CODE_FOR_spe_evmhoumia, "__builtin_spe_evmhoumia", SPE_BUILTIN_EVMHOUMIA }, | |
7583 | { 0, CODE_FOR_spe_evmhoumiaaw, "__builtin_spe_evmhoumiaaw", SPE_BUILTIN_EVMHOUMIAAW }, | |
7584 | { 0, CODE_FOR_spe_evmhoumianw, "__builtin_spe_evmhoumianw", SPE_BUILTIN_EVMHOUMIANW }, | |
7585 | { 0, CODE_FOR_spe_evmhousiaaw, "__builtin_spe_evmhousiaaw", SPE_BUILTIN_EVMHOUSIAAW }, | |
7586 | { 0, CODE_FOR_spe_evmhousianw, "__builtin_spe_evmhousianw", SPE_BUILTIN_EVMHOUSIANW }, | |
7587 | { 0, CODE_FOR_spe_evmwhsmf, "__builtin_spe_evmwhsmf", SPE_BUILTIN_EVMWHSMF }, | |
7588 | { 0, CODE_FOR_spe_evmwhsmfa, "__builtin_spe_evmwhsmfa", SPE_BUILTIN_EVMWHSMFA }, | |
7589 | { 0, CODE_FOR_spe_evmwhsmi, "__builtin_spe_evmwhsmi", SPE_BUILTIN_EVMWHSMI }, | |
7590 | { 0, CODE_FOR_spe_evmwhsmia, "__builtin_spe_evmwhsmia", SPE_BUILTIN_EVMWHSMIA }, | |
7591 | { 0, CODE_FOR_spe_evmwhssf, "__builtin_spe_evmwhssf", SPE_BUILTIN_EVMWHSSF }, | |
7592 | { 0, CODE_FOR_spe_evmwhssfa, "__builtin_spe_evmwhssfa", SPE_BUILTIN_EVMWHSSFA }, | |
7593 | { 0, CODE_FOR_spe_evmwhumi, "__builtin_spe_evmwhumi", SPE_BUILTIN_EVMWHUMI }, | |
7594 | { 0, CODE_FOR_spe_evmwhumia, "__builtin_spe_evmwhumia", SPE_BUILTIN_EVMWHUMIA }, | |
a3170dc6 AH |
7595 | { 0, CODE_FOR_spe_evmwlsmiaaw, "__builtin_spe_evmwlsmiaaw", SPE_BUILTIN_EVMWLSMIAAW }, |
7596 | { 0, CODE_FOR_spe_evmwlsmianw, "__builtin_spe_evmwlsmianw", SPE_BUILTIN_EVMWLSMIANW }, | |
a3170dc6 AH |
7597 | { 0, CODE_FOR_spe_evmwlssiaaw, "__builtin_spe_evmwlssiaaw", SPE_BUILTIN_EVMWLSSIAAW }, |
7598 | { 0, CODE_FOR_spe_evmwlssianw, "__builtin_spe_evmwlssianw", SPE_BUILTIN_EVMWLSSIANW }, | |
7599 | { 0, CODE_FOR_spe_evmwlumi, "__builtin_spe_evmwlumi", SPE_BUILTIN_EVMWLUMI }, | |
7600 | { 0, CODE_FOR_spe_evmwlumia, "__builtin_spe_evmwlumia", SPE_BUILTIN_EVMWLUMIA }, | |
7601 | { 0, CODE_FOR_spe_evmwlumiaaw, "__builtin_spe_evmwlumiaaw", SPE_BUILTIN_EVMWLUMIAAW }, | |
7602 | { 0, CODE_FOR_spe_evmwlumianw, "__builtin_spe_evmwlumianw", SPE_BUILTIN_EVMWLUMIANW }, | |
7603 | { 0, CODE_FOR_spe_evmwlusiaaw, "__builtin_spe_evmwlusiaaw", SPE_BUILTIN_EVMWLUSIAAW }, | |
7604 | { 0, CODE_FOR_spe_evmwlusianw, "__builtin_spe_evmwlusianw", SPE_BUILTIN_EVMWLUSIANW }, | |
7605 | { 0, CODE_FOR_spe_evmwsmf, "__builtin_spe_evmwsmf", SPE_BUILTIN_EVMWSMF }, | |
7606 | { 0, CODE_FOR_spe_evmwsmfa, "__builtin_spe_evmwsmfa", SPE_BUILTIN_EVMWSMFA }, | |
7607 | { 0, CODE_FOR_spe_evmwsmfaa, "__builtin_spe_evmwsmfaa", SPE_BUILTIN_EVMWSMFAA }, | |
7608 | { 0, CODE_FOR_spe_evmwsmfan, "__builtin_spe_evmwsmfan", SPE_BUILTIN_EVMWSMFAN }, | |
7609 | { 0, CODE_FOR_spe_evmwsmi, "__builtin_spe_evmwsmi", SPE_BUILTIN_EVMWSMI }, | |
7610 | { 0, CODE_FOR_spe_evmwsmia, "__builtin_spe_evmwsmia", SPE_BUILTIN_EVMWSMIA }, | |
7611 | { 0, CODE_FOR_spe_evmwsmiaa, "__builtin_spe_evmwsmiaa", SPE_BUILTIN_EVMWSMIAA }, | |
7612 | { 0, CODE_FOR_spe_evmwsmian, "__builtin_spe_evmwsmian", SPE_BUILTIN_EVMWSMIAN }, | |
7613 | { 0, CODE_FOR_spe_evmwssf, "__builtin_spe_evmwssf", SPE_BUILTIN_EVMWSSF }, | |
7614 | { 0, CODE_FOR_spe_evmwssfa, "__builtin_spe_evmwssfa", SPE_BUILTIN_EVMWSSFA }, | |
7615 | { 0, CODE_FOR_spe_evmwssfaa, "__builtin_spe_evmwssfaa", SPE_BUILTIN_EVMWSSFAA }, | |
7616 | { 0, CODE_FOR_spe_evmwssfan, "__builtin_spe_evmwssfan", SPE_BUILTIN_EVMWSSFAN }, | |
7617 | { 0, CODE_FOR_spe_evmwumi, "__builtin_spe_evmwumi", SPE_BUILTIN_EVMWUMI }, | |
7618 | { 0, CODE_FOR_spe_evmwumia, "__builtin_spe_evmwumia", SPE_BUILTIN_EVMWUMIA }, | |
7619 | { 0, CODE_FOR_spe_evmwumiaa, "__builtin_spe_evmwumiaa", SPE_BUILTIN_EVMWUMIAA }, | |
7620 | { 0, CODE_FOR_spe_evmwumian, "__builtin_spe_evmwumian", SPE_BUILTIN_EVMWUMIAN }, | |
7621 | { 0, CODE_FOR_spe_evnand, "__builtin_spe_evnand", SPE_BUILTIN_EVNAND }, | |
7622 | { 0, CODE_FOR_spe_evnor, "__builtin_spe_evnor", SPE_BUILTIN_EVNOR }, | |
7623 | { 0, CODE_FOR_spe_evor, "__builtin_spe_evor", SPE_BUILTIN_EVOR }, | |
7624 | { 0, CODE_FOR_spe_evorc, "__builtin_spe_evorc", SPE_BUILTIN_EVORC }, | |
7625 | { 0, CODE_FOR_spe_evrlw, "__builtin_spe_evrlw", SPE_BUILTIN_EVRLW }, | |
7626 | { 0, CODE_FOR_spe_evslw, "__builtin_spe_evslw", SPE_BUILTIN_EVSLW }, | |
7627 | { 0, CODE_FOR_spe_evsrws, "__builtin_spe_evsrws", SPE_BUILTIN_EVSRWS }, | |
7628 | { 0, CODE_FOR_spe_evsrwu, "__builtin_spe_evsrwu", SPE_BUILTIN_EVSRWU }, | |
7629 | { 0, CODE_FOR_spe_evsubfw, "__builtin_spe_evsubfw", SPE_BUILTIN_EVSUBFW }, | |
7630 | ||
7631 | /* SPE binary operations expecting a 5-bit unsigned literal. */ | |
7632 | { 0, CODE_FOR_spe_evaddiw, "__builtin_spe_evaddiw", SPE_BUILTIN_EVADDIW }, | |
7633 | ||
7634 | { 0, CODE_FOR_spe_evrlwi, "__builtin_spe_evrlwi", SPE_BUILTIN_EVRLWI }, | |
7635 | { 0, CODE_FOR_spe_evslwi, "__builtin_spe_evslwi", SPE_BUILTIN_EVSLWI }, | |
7636 | { 0, CODE_FOR_spe_evsrwis, "__builtin_spe_evsrwis", SPE_BUILTIN_EVSRWIS }, | |
7637 | { 0, CODE_FOR_spe_evsrwiu, "__builtin_spe_evsrwiu", SPE_BUILTIN_EVSRWIU }, | |
7638 | { 0, CODE_FOR_spe_evsubifw, "__builtin_spe_evsubifw", SPE_BUILTIN_EVSUBIFW }, | |
7639 | { 0, CODE_FOR_spe_evmwhssfaa, "__builtin_spe_evmwhssfaa", SPE_BUILTIN_EVMWHSSFAA }, | |
7640 | { 0, CODE_FOR_spe_evmwhssmaa, "__builtin_spe_evmwhssmaa", SPE_BUILTIN_EVMWHSSMAA }, | |
7641 | { 0, CODE_FOR_spe_evmwhsmfaa, "__builtin_spe_evmwhsmfaa", SPE_BUILTIN_EVMWHSMFAA }, | |
7642 | { 0, CODE_FOR_spe_evmwhsmiaa, "__builtin_spe_evmwhsmiaa", SPE_BUILTIN_EVMWHSMIAA }, | |
7643 | { 0, CODE_FOR_spe_evmwhusiaa, "__builtin_spe_evmwhusiaa", SPE_BUILTIN_EVMWHUSIAA }, | |
7644 | { 0, CODE_FOR_spe_evmwhumiaa, "__builtin_spe_evmwhumiaa", SPE_BUILTIN_EVMWHUMIAA }, | |
7645 | { 0, CODE_FOR_spe_evmwhssfan, "__builtin_spe_evmwhssfan", SPE_BUILTIN_EVMWHSSFAN }, | |
7646 | { 0, CODE_FOR_spe_evmwhssian, "__builtin_spe_evmwhssian", SPE_BUILTIN_EVMWHSSIAN }, | |
7647 | { 0, CODE_FOR_spe_evmwhsmfan, "__builtin_spe_evmwhsmfan", SPE_BUILTIN_EVMWHSMFAN }, | |
7648 | { 0, CODE_FOR_spe_evmwhsmian, "__builtin_spe_evmwhsmian", SPE_BUILTIN_EVMWHSMIAN }, | |
7649 | { 0, CODE_FOR_spe_evmwhusian, "__builtin_spe_evmwhusian", SPE_BUILTIN_EVMWHUSIAN }, | |
7650 | { 0, CODE_FOR_spe_evmwhumian, "__builtin_spe_evmwhumian", SPE_BUILTIN_EVMWHUMIAN }, | |
7651 | { 0, CODE_FOR_spe_evmwhgssfaa, "__builtin_spe_evmwhgssfaa", SPE_BUILTIN_EVMWHGSSFAA }, | |
7652 | { 0, CODE_FOR_spe_evmwhgsmfaa, "__builtin_spe_evmwhgsmfaa", SPE_BUILTIN_EVMWHGSMFAA }, | |
7653 | { 0, CODE_FOR_spe_evmwhgsmiaa, "__builtin_spe_evmwhgsmiaa", SPE_BUILTIN_EVMWHGSMIAA }, | |
7654 | { 0, CODE_FOR_spe_evmwhgumiaa, "__builtin_spe_evmwhgumiaa", SPE_BUILTIN_EVMWHGUMIAA }, | |
7655 | { 0, CODE_FOR_spe_evmwhgssfan, "__builtin_spe_evmwhgssfan", SPE_BUILTIN_EVMWHGSSFAN }, | |
7656 | { 0, CODE_FOR_spe_evmwhgsmfan, "__builtin_spe_evmwhgsmfan", SPE_BUILTIN_EVMWHGSMFAN }, | |
7657 | { 0, CODE_FOR_spe_evmwhgsmian, "__builtin_spe_evmwhgsmian", SPE_BUILTIN_EVMWHGSMIAN }, | |
7658 | { 0, CODE_FOR_spe_evmwhgumian, "__builtin_spe_evmwhgumian", SPE_BUILTIN_EVMWHGUMIAN }, | |
7659 | { 0, CODE_FOR_spe_brinc, "__builtin_spe_brinc", SPE_BUILTIN_BRINC }, | |
7660 | ||
7661 | /* Place-holder. Leave as last binary SPE builtin. */ | |
58646b77 | 7662 | { 0, CODE_FOR_xorv2si3, "__builtin_spe_evxor", SPE_BUILTIN_EVXOR } |
ae4b4a02 AH |
7663 | }; |
7664 | ||
7665 | /* AltiVec predicates. */ | |
7666 | ||
7667 | struct builtin_description_predicates | |
7668 | { | |
7669 | const unsigned int mask; | |
7670 | const enum insn_code icode; | |
7671 | const char *opcode; | |
7672 | const char *const name; | |
7673 | const enum rs6000_builtins code; | |
7674 | }; | |
7675 | ||
7676 | static const struct builtin_description_predicates bdesc_altivec_preds[] = | |
7677 | { | |
7678 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpbfp.", "__builtin_altivec_vcmpbfp_p", ALTIVEC_BUILTIN_VCMPBFP_P }, | |
7679 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpeqfp.", "__builtin_altivec_vcmpeqfp_p", ALTIVEC_BUILTIN_VCMPEQFP_P }, | |
7680 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpgefp.", "__builtin_altivec_vcmpgefp_p", ALTIVEC_BUILTIN_VCMPGEFP_P }, | |
7681 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpgtfp.", "__builtin_altivec_vcmpgtfp_p", ALTIVEC_BUILTIN_VCMPGTFP_P }, | |
7682 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpequw.", "__builtin_altivec_vcmpequw_p", ALTIVEC_BUILTIN_VCMPEQUW_P }, | |
7683 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpgtsw.", "__builtin_altivec_vcmpgtsw_p", ALTIVEC_BUILTIN_VCMPGTSW_P }, | |
7684 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpgtuw.", "__builtin_altivec_vcmpgtuw_p", ALTIVEC_BUILTIN_VCMPGTUW_P }, | |
7685 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpgtuh.", "__builtin_altivec_vcmpgtuh_p", ALTIVEC_BUILTIN_VCMPGTUH_P }, | |
7686 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpgtsh.", "__builtin_altivec_vcmpgtsh_p", ALTIVEC_BUILTIN_VCMPGTSH_P }, | |
7687 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpequh.", "__builtin_altivec_vcmpequh_p", ALTIVEC_BUILTIN_VCMPEQUH_P }, | |
7688 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpequb.", "__builtin_altivec_vcmpequb_p", ALTIVEC_BUILTIN_VCMPEQUB_P }, | |
7689 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpgtsb.", "__builtin_altivec_vcmpgtsb_p", ALTIVEC_BUILTIN_VCMPGTSB_P }, | |
58646b77 PB |
7690 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpgtub.", "__builtin_altivec_vcmpgtub_p", ALTIVEC_BUILTIN_VCMPGTUB_P }, |
7691 | ||
7692 | { MASK_ALTIVEC, 0, NULL, "__builtin_vec_vcmpeq_p", ALTIVEC_BUILTIN_VCMPEQ_P }, | |
7693 | { MASK_ALTIVEC, 0, NULL, "__builtin_vec_vcmpgt_p", ALTIVEC_BUILTIN_VCMPGT_P }, | |
7694 | { MASK_ALTIVEC, 0, NULL, "__builtin_vec_vcmpge_p", ALTIVEC_BUILTIN_VCMPGE_P } | |
0ac081f6 | 7695 | }; |
24408032 | 7696 | |
a3170dc6 AH |
7697 | /* SPE predicates. */ |
7698 | static struct builtin_description bdesc_spe_predicates[] = | |
7699 | { | |
7700 | /* Place-holder. Leave as first. */ | |
7701 | { 0, CODE_FOR_spe_evcmpeq, "__builtin_spe_evcmpeq", SPE_BUILTIN_EVCMPEQ }, | |
7702 | { 0, CODE_FOR_spe_evcmpgts, "__builtin_spe_evcmpgts", SPE_BUILTIN_EVCMPGTS }, | |
7703 | { 0, CODE_FOR_spe_evcmpgtu, "__builtin_spe_evcmpgtu", SPE_BUILTIN_EVCMPGTU }, | |
7704 | { 0, CODE_FOR_spe_evcmplts, "__builtin_spe_evcmplts", SPE_BUILTIN_EVCMPLTS }, | |
7705 | { 0, CODE_FOR_spe_evcmpltu, "__builtin_spe_evcmpltu", SPE_BUILTIN_EVCMPLTU }, | |
7706 | { 0, CODE_FOR_spe_evfscmpeq, "__builtin_spe_evfscmpeq", SPE_BUILTIN_EVFSCMPEQ }, | |
7707 | { 0, CODE_FOR_spe_evfscmpgt, "__builtin_spe_evfscmpgt", SPE_BUILTIN_EVFSCMPGT }, | |
7708 | { 0, CODE_FOR_spe_evfscmplt, "__builtin_spe_evfscmplt", SPE_BUILTIN_EVFSCMPLT }, | |
7709 | { 0, CODE_FOR_spe_evfststeq, "__builtin_spe_evfststeq", SPE_BUILTIN_EVFSTSTEQ }, | |
7710 | { 0, CODE_FOR_spe_evfststgt, "__builtin_spe_evfststgt", SPE_BUILTIN_EVFSTSTGT }, | |
7711 | /* Place-holder. Leave as last. */ | |
7712 | { 0, CODE_FOR_spe_evfststlt, "__builtin_spe_evfststlt", SPE_BUILTIN_EVFSTSTLT }, | |
7713 | }; | |
7714 | ||
7715 | /* SPE evsel predicates. */ | |
7716 | static struct builtin_description bdesc_spe_evsel[] = | |
7717 | { | |
7718 | /* Place-holder. Leave as first. */ | |
7719 | { 0, CODE_FOR_spe_evcmpgts, "__builtin_spe_evsel_gts", SPE_BUILTIN_EVSEL_CMPGTS }, | |
7720 | { 0, CODE_FOR_spe_evcmpgtu, "__builtin_spe_evsel_gtu", SPE_BUILTIN_EVSEL_CMPGTU }, | |
7721 | { 0, CODE_FOR_spe_evcmplts, "__builtin_spe_evsel_lts", SPE_BUILTIN_EVSEL_CMPLTS }, | |
7722 | { 0, CODE_FOR_spe_evcmpltu, "__builtin_spe_evsel_ltu", SPE_BUILTIN_EVSEL_CMPLTU }, | |
7723 | { 0, CODE_FOR_spe_evcmpeq, "__builtin_spe_evsel_eq", SPE_BUILTIN_EVSEL_CMPEQ }, | |
7724 | { 0, CODE_FOR_spe_evfscmpgt, "__builtin_spe_evsel_fsgt", SPE_BUILTIN_EVSEL_FSCMPGT }, | |
7725 | { 0, CODE_FOR_spe_evfscmplt, "__builtin_spe_evsel_fslt", SPE_BUILTIN_EVSEL_FSCMPLT }, | |
7726 | { 0, CODE_FOR_spe_evfscmpeq, "__builtin_spe_evsel_fseq", SPE_BUILTIN_EVSEL_FSCMPEQ }, | |
7727 | { 0, CODE_FOR_spe_evfststgt, "__builtin_spe_evsel_fststgt", SPE_BUILTIN_EVSEL_FSTSTGT }, | |
7728 | { 0, CODE_FOR_spe_evfststlt, "__builtin_spe_evsel_fststlt", SPE_BUILTIN_EVSEL_FSTSTLT }, | |
7729 | /* Place-holder. Leave as last. */ | |
7730 | { 0, CODE_FOR_spe_evfststeq, "__builtin_spe_evsel_fststeq", SPE_BUILTIN_EVSEL_FSTSTEQ }, | |
7731 | }; | |
7732 | ||
96038623 DE |
7733 | /* PAIRED predicates. */ |
7734 | static const struct builtin_description bdesc_paired_preds[] = | |
7735 | { | |
7736 | /* Place-holder. Leave as first. */ | |
7737 | { 0, CODE_FOR_paired_cmpu0, "__builtin_paired_cmpu0", PAIRED_BUILTIN_CMPU0 }, | |
7738 | /* Place-holder. Leave as last. */ | |
7739 | { 0, CODE_FOR_paired_cmpu1, "__builtin_paired_cmpu1", PAIRED_BUILTIN_CMPU1 }, | |
7740 | }; | |
7741 | ||
b6d08ca1 | 7742 | /* ABS* operations. */ |
100c4561 AH |
7743 | |
7744 | static const struct builtin_description bdesc_abs[] = | |
7745 | { | |
7746 | { MASK_ALTIVEC, CODE_FOR_absv4si2, "__builtin_altivec_abs_v4si", ALTIVEC_BUILTIN_ABS_V4SI }, | |
7747 | { MASK_ALTIVEC, CODE_FOR_absv8hi2, "__builtin_altivec_abs_v8hi", ALTIVEC_BUILTIN_ABS_V8HI }, | |
7748 | { MASK_ALTIVEC, CODE_FOR_absv4sf2, "__builtin_altivec_abs_v4sf", ALTIVEC_BUILTIN_ABS_V4SF }, | |
7749 | { MASK_ALTIVEC, CODE_FOR_absv16qi2, "__builtin_altivec_abs_v16qi", ALTIVEC_BUILTIN_ABS_V16QI }, | |
7750 | { MASK_ALTIVEC, CODE_FOR_altivec_abss_v4si, "__builtin_altivec_abss_v4si", ALTIVEC_BUILTIN_ABSS_V4SI }, | |
7751 | { MASK_ALTIVEC, CODE_FOR_altivec_abss_v8hi, "__builtin_altivec_abss_v8hi", ALTIVEC_BUILTIN_ABSS_V8HI }, | |
7752 | { MASK_ALTIVEC, CODE_FOR_altivec_abss_v16qi, "__builtin_altivec_abss_v16qi", ALTIVEC_BUILTIN_ABSS_V16QI } | |
7753 | }; | |
7754 | ||
617e0e1d DB |
7755 | /* Simple unary operations: VECb = foo (unsigned literal) or VECb = |
7756 | foo (VECa). */ | |
24408032 | 7757 | |
a3170dc6 | 7758 | static struct builtin_description bdesc_1arg[] = |
2212663f | 7759 | { |
617e0e1d DB |
7760 | { MASK_ALTIVEC, CODE_FOR_altivec_vexptefp, "__builtin_altivec_vexptefp", ALTIVEC_BUILTIN_VEXPTEFP }, |
7761 | { MASK_ALTIVEC, CODE_FOR_altivec_vlogefp, "__builtin_altivec_vlogefp", ALTIVEC_BUILTIN_VLOGEFP }, | |
7762 | { MASK_ALTIVEC, CODE_FOR_altivec_vrefp, "__builtin_altivec_vrefp", ALTIVEC_BUILTIN_VREFP }, | |
7763 | { MASK_ALTIVEC, CODE_FOR_altivec_vrfim, "__builtin_altivec_vrfim", ALTIVEC_BUILTIN_VRFIM }, | |
7764 | { MASK_ALTIVEC, CODE_FOR_altivec_vrfin, "__builtin_altivec_vrfin", ALTIVEC_BUILTIN_VRFIN }, | |
7765 | { MASK_ALTIVEC, CODE_FOR_altivec_vrfip, "__builtin_altivec_vrfip", ALTIVEC_BUILTIN_VRFIP }, | |
7766 | { MASK_ALTIVEC, CODE_FOR_ftruncv4sf2, "__builtin_altivec_vrfiz", ALTIVEC_BUILTIN_VRFIZ }, | |
7767 | { MASK_ALTIVEC, CODE_FOR_altivec_vrsqrtefp, "__builtin_altivec_vrsqrtefp", ALTIVEC_BUILTIN_VRSQRTEFP }, | |
2212663f DB |
7768 | { MASK_ALTIVEC, CODE_FOR_altivec_vspltisb, "__builtin_altivec_vspltisb", ALTIVEC_BUILTIN_VSPLTISB }, |
7769 | { MASK_ALTIVEC, CODE_FOR_altivec_vspltish, "__builtin_altivec_vspltish", ALTIVEC_BUILTIN_VSPLTISH }, | |
7770 | { MASK_ALTIVEC, CODE_FOR_altivec_vspltisw, "__builtin_altivec_vspltisw", ALTIVEC_BUILTIN_VSPLTISW }, | |
20e26713 AH |
7771 | { MASK_ALTIVEC, CODE_FOR_altivec_vupkhsb, "__builtin_altivec_vupkhsb", ALTIVEC_BUILTIN_VUPKHSB }, |
7772 | { MASK_ALTIVEC, CODE_FOR_altivec_vupkhpx, "__builtin_altivec_vupkhpx", ALTIVEC_BUILTIN_VUPKHPX }, | |
7773 | { MASK_ALTIVEC, CODE_FOR_altivec_vupkhsh, "__builtin_altivec_vupkhsh", ALTIVEC_BUILTIN_VUPKHSH }, | |
7774 | { MASK_ALTIVEC, CODE_FOR_altivec_vupklsb, "__builtin_altivec_vupklsb", ALTIVEC_BUILTIN_VUPKLSB }, | |
7775 | { MASK_ALTIVEC, CODE_FOR_altivec_vupklpx, "__builtin_altivec_vupklpx", ALTIVEC_BUILTIN_VUPKLPX }, | |
7776 | { MASK_ALTIVEC, CODE_FOR_altivec_vupklsh, "__builtin_altivec_vupklsh", ALTIVEC_BUILTIN_VUPKLSH }, | |
a3170dc6 | 7777 | |
58646b77 PB |
7778 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_abs", ALTIVEC_BUILTIN_VEC_ABS }, |
7779 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_abss", ALTIVEC_BUILTIN_VEC_ABSS }, | |
7780 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_ceil", ALTIVEC_BUILTIN_VEC_CEIL }, | |
7781 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_expte", ALTIVEC_BUILTIN_VEC_EXPTE }, | |
7782 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_floor", ALTIVEC_BUILTIN_VEC_FLOOR }, | |
7783 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_loge", ALTIVEC_BUILTIN_VEC_LOGE }, | |
7784 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mtvscr", ALTIVEC_BUILTIN_VEC_MTVSCR }, | |
7785 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_re", ALTIVEC_BUILTIN_VEC_RE }, | |
7786 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_round", ALTIVEC_BUILTIN_VEC_ROUND }, | |
7787 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_rsqrte", ALTIVEC_BUILTIN_VEC_RSQRTE }, | |
7788 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_trunc", ALTIVEC_BUILTIN_VEC_TRUNC }, | |
7789 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_unpackh", ALTIVEC_BUILTIN_VEC_UNPACKH }, | |
7790 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupkhsh", ALTIVEC_BUILTIN_VEC_VUPKHSH }, | |
7791 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupkhpx", ALTIVEC_BUILTIN_VEC_VUPKHPX }, | |
7792 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupkhsb", ALTIVEC_BUILTIN_VEC_VUPKHSB }, | |
7793 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_unpackl", ALTIVEC_BUILTIN_VEC_UNPACKL }, | |
7794 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupklpx", ALTIVEC_BUILTIN_VEC_VUPKLPX }, | |
7795 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupklsh", ALTIVEC_BUILTIN_VEC_VUPKLSH }, | |
7796 | { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupklsb", ALTIVEC_BUILTIN_VEC_VUPKLSB }, | |
7797 | ||
a3170dc6 AH |
7798 | /* The SPE unary builtins must start with SPE_BUILTIN_EVABS and |
7799 | end with SPE_BUILTIN_EVSUBFUSIAAW. */ | |
7800 | { 0, CODE_FOR_spe_evabs, "__builtin_spe_evabs", SPE_BUILTIN_EVABS }, | |
7801 | { 0, CODE_FOR_spe_evaddsmiaaw, "__builtin_spe_evaddsmiaaw", SPE_BUILTIN_EVADDSMIAAW }, | |
7802 | { 0, CODE_FOR_spe_evaddssiaaw, "__builtin_spe_evaddssiaaw", SPE_BUILTIN_EVADDSSIAAW }, | |
7803 | { 0, CODE_FOR_spe_evaddumiaaw, "__builtin_spe_evaddumiaaw", SPE_BUILTIN_EVADDUMIAAW }, | |
7804 | { 0, CODE_FOR_spe_evaddusiaaw, "__builtin_spe_evaddusiaaw", SPE_BUILTIN_EVADDUSIAAW }, | |
7805 | { 0, CODE_FOR_spe_evcntlsw, "__builtin_spe_evcntlsw", SPE_BUILTIN_EVCNTLSW }, | |
7806 | { 0, CODE_FOR_spe_evcntlzw, "__builtin_spe_evcntlzw", SPE_BUILTIN_EVCNTLZW }, | |
7807 | { 0, CODE_FOR_spe_evextsb, "__builtin_spe_evextsb", SPE_BUILTIN_EVEXTSB }, | |
7808 | { 0, CODE_FOR_spe_evextsh, "__builtin_spe_evextsh", SPE_BUILTIN_EVEXTSH }, | |
7809 | { 0, CODE_FOR_spe_evfsabs, "__builtin_spe_evfsabs", SPE_BUILTIN_EVFSABS }, | |
7810 | { 0, CODE_FOR_spe_evfscfsf, "__builtin_spe_evfscfsf", SPE_BUILTIN_EVFSCFSF }, | |
7811 | { 0, CODE_FOR_spe_evfscfsi, "__builtin_spe_evfscfsi", SPE_BUILTIN_EVFSCFSI }, | |
7812 | { 0, CODE_FOR_spe_evfscfuf, "__builtin_spe_evfscfuf", SPE_BUILTIN_EVFSCFUF }, | |
7813 | { 0, CODE_FOR_spe_evfscfui, "__builtin_spe_evfscfui", SPE_BUILTIN_EVFSCFUI }, | |
7814 | { 0, CODE_FOR_spe_evfsctsf, "__builtin_spe_evfsctsf", SPE_BUILTIN_EVFSCTSF }, | |
7815 | { 0, CODE_FOR_spe_evfsctsi, "__builtin_spe_evfsctsi", SPE_BUILTIN_EVFSCTSI }, | |
7816 | { 0, CODE_FOR_spe_evfsctsiz, "__builtin_spe_evfsctsiz", SPE_BUILTIN_EVFSCTSIZ }, | |
7817 | { 0, CODE_FOR_spe_evfsctuf, "__builtin_spe_evfsctuf", SPE_BUILTIN_EVFSCTUF }, | |
7818 | { 0, CODE_FOR_spe_evfsctui, "__builtin_spe_evfsctui", SPE_BUILTIN_EVFSCTUI }, | |
7819 | { 0, CODE_FOR_spe_evfsctuiz, "__builtin_spe_evfsctuiz", SPE_BUILTIN_EVFSCTUIZ }, | |
7820 | { 0, CODE_FOR_spe_evfsnabs, "__builtin_spe_evfsnabs", SPE_BUILTIN_EVFSNABS }, | |
7821 | { 0, CODE_FOR_spe_evfsneg, "__builtin_spe_evfsneg", SPE_BUILTIN_EVFSNEG }, | |
7822 | { 0, CODE_FOR_spe_evmra, "__builtin_spe_evmra", SPE_BUILTIN_EVMRA }, | |
6a599451 | 7823 | { 0, CODE_FOR_negv2si2, "__builtin_spe_evneg", SPE_BUILTIN_EVNEG }, |
a3170dc6 AH |
7824 | { 0, CODE_FOR_spe_evrndw, "__builtin_spe_evrndw", SPE_BUILTIN_EVRNDW }, |
7825 | { 0, CODE_FOR_spe_evsubfsmiaaw, "__builtin_spe_evsubfsmiaaw", SPE_BUILTIN_EVSUBFSMIAAW }, | |
7826 | { 0, CODE_FOR_spe_evsubfssiaaw, "__builtin_spe_evsubfssiaaw", SPE_BUILTIN_EVSUBFSSIAAW }, | |
7827 | { 0, CODE_FOR_spe_evsubfumiaaw, "__builtin_spe_evsubfumiaaw", SPE_BUILTIN_EVSUBFUMIAAW }, | |
a3170dc6 AH |
7828 | |
7829 | /* Place-holder. Leave as last unary SPE builtin. */ | |
96038623 DE |
7830 | { 0, CODE_FOR_spe_evsubfusiaaw, "__builtin_spe_evsubfusiaaw", SPE_BUILTIN_EVSUBFUSIAAW }, |
7831 | ||
7832 | { 0, CODE_FOR_absv2sf2, "__builtin_paired_absv2sf2", PAIRED_BUILTIN_ABSV2SF2 }, | |
7833 | { 0, CODE_FOR_nabsv2sf2, "__builtin_paired_nabsv2sf2", PAIRED_BUILTIN_NABSV2SF2 }, | |
7834 | { 0, CODE_FOR_negv2sf2, "__builtin_paired_negv2sf2", PAIRED_BUILTIN_NEGV2SF2 }, | |
7835 | { 0, CODE_FOR_sqrtv2sf2, "__builtin_paired_sqrtv2sf2", PAIRED_BUILTIN_SQRTV2SF2 }, | |
7836 | { 0, CODE_FOR_resv2sf2, "__builtin_paired_resv2sf2", PAIRED_BUILTIN_RESV2SF2 } | |
2212663f DB |
7837 | }; |
7838 | ||
7839 | static rtx | |
5039610b | 7840 | rs6000_expand_unop_builtin (enum insn_code icode, tree exp, rtx target) |
2212663f DB |
7841 | { |
7842 | rtx pat; | |
5039610b | 7843 | tree arg0 = CALL_EXPR_ARG (exp, 0); |
84217346 | 7844 | rtx op0 = expand_normal (arg0); |
2212663f DB |
7845 | enum machine_mode tmode = insn_data[icode].operand[0].mode; |
7846 | enum machine_mode mode0 = insn_data[icode].operand[1].mode; | |
7847 | ||
0559cc77 DE |
7848 | if (icode == CODE_FOR_nothing) |
7849 | /* Builtin not supported on this processor. */ | |
7850 | return 0; | |
7851 | ||
20e26713 AH |
7852 | /* If we got invalid arguments bail out before generating bad rtl. */ |
7853 | if (arg0 == error_mark_node) | |
9a171fcd | 7854 | return const0_rtx; |
20e26713 | 7855 | |
0559cc77 DE |
7856 | if (icode == CODE_FOR_altivec_vspltisb |
7857 | || icode == CODE_FOR_altivec_vspltish | |
7858 | || icode == CODE_FOR_altivec_vspltisw | |
7859 | || icode == CODE_FOR_spe_evsplatfi | |
7860 | || icode == CODE_FOR_spe_evsplati) | |
b44140e7 AH |
7861 | { |
7862 | /* Only allow 5-bit *signed* literals. */ | |
b44140e7 | 7863 | if (GET_CODE (op0) != CONST_INT |
afca671b DP |
7864 | || INTVAL (op0) > 15 |
7865 | || INTVAL (op0) < -16) | |
b44140e7 AH |
7866 | { |
7867 | error ("argument 1 must be a 5-bit signed literal"); | |
9a171fcd | 7868 | return const0_rtx; |
b44140e7 | 7869 | } |
b44140e7 AH |
7870 | } |
7871 | ||
c62f2db5 | 7872 | if (target == 0 |
2212663f DB |
7873 | || GET_MODE (target) != tmode |
7874 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
7875 | target = gen_reg_rtx (tmode); | |
7876 | ||
7877 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) | |
7878 | op0 = copy_to_mode_reg (mode0, op0); | |
7879 | ||
7880 | pat = GEN_FCN (icode) (target, op0); | |
7881 | if (! pat) | |
7882 | return 0; | |
7883 | emit_insn (pat); | |
0ac081f6 | 7884 | |
2212663f DB |
7885 | return target; |
7886 | } | |
ae4b4a02 | 7887 | |
100c4561 | 7888 | static rtx |
5039610b | 7889 | altivec_expand_abs_builtin (enum insn_code icode, tree exp, rtx target) |
100c4561 AH |
7890 | { |
7891 | rtx pat, scratch1, scratch2; | |
5039610b | 7892 | tree arg0 = CALL_EXPR_ARG (exp, 0); |
84217346 | 7893 | rtx op0 = expand_normal (arg0); |
100c4561 AH |
7894 | enum machine_mode tmode = insn_data[icode].operand[0].mode; |
7895 | enum machine_mode mode0 = insn_data[icode].operand[1].mode; | |
7896 | ||
7897 | /* If we have invalid arguments, bail out before generating bad rtl. */ | |
7898 | if (arg0 == error_mark_node) | |
9a171fcd | 7899 | return const0_rtx; |
100c4561 AH |
7900 | |
7901 | if (target == 0 | |
7902 | || GET_MODE (target) != tmode | |
7903 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
7904 | target = gen_reg_rtx (tmode); | |
7905 | ||
7906 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) | |
7907 | op0 = copy_to_mode_reg (mode0, op0); | |
7908 | ||
7909 | scratch1 = gen_reg_rtx (mode0); | |
7910 | scratch2 = gen_reg_rtx (mode0); | |
7911 | ||
7912 | pat = GEN_FCN (icode) (target, op0, scratch1, scratch2); | |
7913 | if (! pat) | |
7914 | return 0; | |
7915 | emit_insn (pat); | |
7916 | ||
7917 | return target; | |
7918 | } | |
7919 | ||
0ac081f6 | 7920 | static rtx |
5039610b | 7921 | rs6000_expand_binop_builtin (enum insn_code icode, tree exp, rtx target) |
0ac081f6 AH |
7922 | { |
7923 | rtx pat; | |
5039610b SL |
7924 | tree arg0 = CALL_EXPR_ARG (exp, 0); |
7925 | tree arg1 = CALL_EXPR_ARG (exp, 1); | |
84217346 MD |
7926 | rtx op0 = expand_normal (arg0); |
7927 | rtx op1 = expand_normal (arg1); | |
0ac081f6 AH |
7928 | enum machine_mode tmode = insn_data[icode].operand[0].mode; |
7929 | enum machine_mode mode0 = insn_data[icode].operand[1].mode; | |
7930 | enum machine_mode mode1 = insn_data[icode].operand[2].mode; | |
7931 | ||
0559cc77 DE |
7932 | if (icode == CODE_FOR_nothing) |
7933 | /* Builtin not supported on this processor. */ | |
7934 | return 0; | |
7935 | ||
20e26713 AH |
7936 | /* If we got invalid arguments bail out before generating bad rtl. */ |
7937 | if (arg0 == error_mark_node || arg1 == error_mark_node) | |
9a171fcd | 7938 | return const0_rtx; |
20e26713 | 7939 | |
0559cc77 DE |
7940 | if (icode == CODE_FOR_altivec_vcfux |
7941 | || icode == CODE_FOR_altivec_vcfsx | |
7942 | || icode == CODE_FOR_altivec_vctsxs | |
7943 | || icode == CODE_FOR_altivec_vctuxs | |
7944 | || icode == CODE_FOR_altivec_vspltb | |
7945 | || icode == CODE_FOR_altivec_vsplth | |
7946 | || icode == CODE_FOR_altivec_vspltw | |
7947 | || icode == CODE_FOR_spe_evaddiw | |
7948 | || icode == CODE_FOR_spe_evldd | |
7949 | || icode == CODE_FOR_spe_evldh | |
7950 | || icode == CODE_FOR_spe_evldw | |
7951 | || icode == CODE_FOR_spe_evlhhesplat | |
7952 | || icode == CODE_FOR_spe_evlhhossplat | |
7953 | || icode == CODE_FOR_spe_evlhhousplat | |
7954 | || icode == CODE_FOR_spe_evlwhe | |
7955 | || icode == CODE_FOR_spe_evlwhos | |
7956 | || icode == CODE_FOR_spe_evlwhou | |
7957 | || icode == CODE_FOR_spe_evlwhsplat | |
7958 | || icode == CODE_FOR_spe_evlwwsplat | |
7959 | || icode == CODE_FOR_spe_evrlwi | |
7960 | || icode == CODE_FOR_spe_evslwi | |
7961 | || icode == CODE_FOR_spe_evsrwis | |
f5119d10 | 7962 | || icode == CODE_FOR_spe_evsubifw |
0559cc77 | 7963 | || icode == CODE_FOR_spe_evsrwiu) |
b44140e7 AH |
7964 | { |
7965 | /* Only allow 5-bit unsigned literals. */ | |
8bb418a3 | 7966 | STRIP_NOPS (arg1); |
b44140e7 AH |
7967 | if (TREE_CODE (arg1) != INTEGER_CST |
7968 | || TREE_INT_CST_LOW (arg1) & ~0x1f) | |
7969 | { | |
7970 | error ("argument 2 must be a 5-bit unsigned literal"); | |
9a171fcd | 7971 | return const0_rtx; |
b44140e7 | 7972 | } |
b44140e7 AH |
7973 | } |
7974 | ||
c62f2db5 | 7975 | if (target == 0 |
0ac081f6 AH |
7976 | || GET_MODE (target) != tmode |
7977 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
7978 | target = gen_reg_rtx (tmode); | |
7979 | ||
7980 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) | |
7981 | op0 = copy_to_mode_reg (mode0, op0); | |
7982 | if (! (*insn_data[icode].operand[2].predicate) (op1, mode1)) | |
7983 | op1 = copy_to_mode_reg (mode1, op1); | |
7984 | ||
7985 | pat = GEN_FCN (icode) (target, op0, op1); | |
7986 | if (! pat) | |
7987 | return 0; | |
7988 | emit_insn (pat); | |
7989 | ||
7990 | return target; | |
7991 | } | |
6525c0e7 | 7992 | |
ae4b4a02 | 7993 | static rtx |
f676971a | 7994 | altivec_expand_predicate_builtin (enum insn_code icode, const char *opcode, |
5039610b | 7995 | tree exp, rtx target) |
ae4b4a02 AH |
7996 | { |
7997 | rtx pat, scratch; | |
5039610b SL |
7998 | tree cr6_form = CALL_EXPR_ARG (exp, 0); |
7999 | tree arg0 = CALL_EXPR_ARG (exp, 1); | |
8000 | tree arg1 = CALL_EXPR_ARG (exp, 2); | |
84217346 MD |
8001 | rtx op0 = expand_normal (arg0); |
8002 | rtx op1 = expand_normal (arg1); | |
ae4b4a02 AH |
8003 | enum machine_mode tmode = SImode; |
8004 | enum machine_mode mode0 = insn_data[icode].operand[1].mode; | |
8005 | enum machine_mode mode1 = insn_data[icode].operand[2].mode; | |
8006 | int cr6_form_int; | |
8007 | ||
8008 | if (TREE_CODE (cr6_form) != INTEGER_CST) | |
8009 | { | |
8010 | error ("argument 1 of __builtin_altivec_predicate must be a constant"); | |
9a171fcd | 8011 | return const0_rtx; |
ae4b4a02 AH |
8012 | } |
8013 | else | |
8014 | cr6_form_int = TREE_INT_CST_LOW (cr6_form); | |
8015 | ||
37409796 | 8016 | gcc_assert (mode0 == mode1); |
ae4b4a02 AH |
8017 | |
8018 | /* If we have invalid arguments, bail out before generating bad rtl. */ | |
8019 | if (arg0 == error_mark_node || arg1 == error_mark_node) | |
9a171fcd | 8020 | return const0_rtx; |
ae4b4a02 AH |
8021 | |
8022 | if (target == 0 | |
8023 | || GET_MODE (target) != tmode | |
8024 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
8025 | target = gen_reg_rtx (tmode); | |
8026 | ||
8027 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) | |
8028 | op0 = copy_to_mode_reg (mode0, op0); | |
8029 | if (! (*insn_data[icode].operand[2].predicate) (op1, mode1)) | |
8030 | op1 = copy_to_mode_reg (mode1, op1); | |
8031 | ||
8032 | scratch = gen_reg_rtx (mode0); | |
8033 | ||
8034 | pat = GEN_FCN (icode) (scratch, op0, op1, | |
f1c25d3b | 8035 | gen_rtx_SYMBOL_REF (Pmode, opcode)); |
ae4b4a02 AH |
8036 | if (! pat) |
8037 | return 0; | |
8038 | emit_insn (pat); | |
8039 | ||
8040 | /* The vec_any* and vec_all* predicates use the same opcodes for two | |
8041 | different operations, but the bits in CR6 will be different | |
8042 | depending on what information we want. So we have to play tricks | |
8043 | with CR6 to get the right bits out. | |
8044 | ||
8045 | If you think this is disgusting, look at the specs for the | |
8046 | AltiVec predicates. */ | |
8047 | ||
c4ad648e AM |
8048 | switch (cr6_form_int) |
8049 | { | |
8050 | case 0: | |
8051 | emit_insn (gen_cr6_test_for_zero (target)); | |
8052 | break; | |
8053 | case 1: | |
8054 | emit_insn (gen_cr6_test_for_zero_reverse (target)); | |
8055 | break; | |
8056 | case 2: | |
8057 | emit_insn (gen_cr6_test_for_lt (target)); | |
8058 | break; | |
8059 | case 3: | |
8060 | emit_insn (gen_cr6_test_for_lt_reverse (target)); | |
8061 | break; | |
8062 | default: | |
8063 | error ("argument 1 of __builtin_altivec_predicate is out of range"); | |
8064 | break; | |
8065 | } | |
ae4b4a02 AH |
8066 | |
8067 | return target; | |
8068 | } | |
8069 | ||
96038623 DE |
8070 | static rtx |
8071 | paired_expand_lv_builtin (enum insn_code icode, tree exp, rtx target) | |
8072 | { | |
8073 | rtx pat, addr; | |
8074 | tree arg0 = CALL_EXPR_ARG (exp, 0); | |
8075 | tree arg1 = CALL_EXPR_ARG (exp, 1); | |
8076 | enum machine_mode tmode = insn_data[icode].operand[0].mode; | |
8077 | enum machine_mode mode0 = Pmode; | |
8078 | enum machine_mode mode1 = Pmode; | |
8079 | rtx op0 = expand_normal (arg0); | |
8080 | rtx op1 = expand_normal (arg1); | |
8081 | ||
8082 | if (icode == CODE_FOR_nothing) | |
8083 | /* Builtin not supported on this processor. */ | |
8084 | return 0; | |
8085 | ||
8086 | /* If we got invalid arguments bail out before generating bad rtl. */ | |
8087 | if (arg0 == error_mark_node || arg1 == error_mark_node) | |
8088 | return const0_rtx; | |
8089 | ||
8090 | if (target == 0 | |
8091 | || GET_MODE (target) != tmode | |
8092 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
8093 | target = gen_reg_rtx (tmode); | |
8094 | ||
8095 | op1 = copy_to_mode_reg (mode1, op1); | |
8096 | ||
8097 | if (op0 == const0_rtx) | |
8098 | { | |
8099 | addr = gen_rtx_MEM (tmode, op1); | |
8100 | } | |
8101 | else | |
8102 | { | |
8103 | op0 = copy_to_mode_reg (mode0, op0); | |
8104 | addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op0, op1)); | |
8105 | } | |
8106 | ||
8107 | pat = GEN_FCN (icode) (target, addr); | |
8108 | ||
8109 | if (! pat) | |
8110 | return 0; | |
8111 | emit_insn (pat); | |
8112 | ||
8113 | return target; | |
8114 | } | |
8115 | ||
b4a62fa0 | 8116 | static rtx |
0b61703c | 8117 | altivec_expand_lv_builtin (enum insn_code icode, tree exp, rtx target, bool blk) |
b4a62fa0 SB |
8118 | { |
8119 | rtx pat, addr; | |
5039610b SL |
8120 | tree arg0 = CALL_EXPR_ARG (exp, 0); |
8121 | tree arg1 = CALL_EXPR_ARG (exp, 1); | |
b4a62fa0 SB |
8122 | enum machine_mode tmode = insn_data[icode].operand[0].mode; |
8123 | enum machine_mode mode0 = Pmode; | |
8124 | enum machine_mode mode1 = Pmode; | |
84217346 MD |
8125 | rtx op0 = expand_normal (arg0); |
8126 | rtx op1 = expand_normal (arg1); | |
b4a62fa0 SB |
8127 | |
8128 | if (icode == CODE_FOR_nothing) | |
8129 | /* Builtin not supported on this processor. */ | |
8130 | return 0; | |
8131 | ||
8132 | /* If we got invalid arguments bail out before generating bad rtl. */ | |
8133 | if (arg0 == error_mark_node || arg1 == error_mark_node) | |
8134 | return const0_rtx; | |
8135 | ||
8136 | if (target == 0 | |
8137 | || GET_MODE (target) != tmode | |
8138 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
8139 | target = gen_reg_rtx (tmode); | |
8140 | ||
f676971a | 8141 | op1 = copy_to_mode_reg (mode1, op1); |
b4a62fa0 SB |
8142 | |
8143 | if (op0 == const0_rtx) | |
8144 | { | |
0b61703c | 8145 | addr = gen_rtx_MEM (blk ? BLKmode : tmode, op1); |
b4a62fa0 SB |
8146 | } |
8147 | else | |
8148 | { | |
8149 | op0 = copy_to_mode_reg (mode0, op0); | |
0b61703c | 8150 | addr = gen_rtx_MEM (blk ? BLKmode : tmode, gen_rtx_PLUS (Pmode, op0, op1)); |
b4a62fa0 SB |
8151 | } |
8152 | ||
8153 | pat = GEN_FCN (icode) (target, addr); | |
8154 | ||
8155 | if (! pat) | |
8156 | return 0; | |
8157 | emit_insn (pat); | |
8158 | ||
8159 | return target; | |
8160 | } | |
8161 | ||
61bea3b0 | 8162 | static rtx |
5039610b | 8163 | spe_expand_stv_builtin (enum insn_code icode, tree exp) |
61bea3b0 | 8164 | { |
5039610b SL |
8165 | tree arg0 = CALL_EXPR_ARG (exp, 0); |
8166 | tree arg1 = CALL_EXPR_ARG (exp, 1); | |
8167 | tree arg2 = CALL_EXPR_ARG (exp, 2); | |
84217346 MD |
8168 | rtx op0 = expand_normal (arg0); |
8169 | rtx op1 = expand_normal (arg1); | |
8170 | rtx op2 = expand_normal (arg2); | |
61bea3b0 AH |
8171 | rtx pat; |
8172 | enum machine_mode mode0 = insn_data[icode].operand[0].mode; | |
8173 | enum machine_mode mode1 = insn_data[icode].operand[1].mode; | |
8174 | enum machine_mode mode2 = insn_data[icode].operand[2].mode; | |
8175 | ||
8176 | /* Invalid arguments. Bail before doing anything stoopid! */ | |
8177 | if (arg0 == error_mark_node | |
8178 | || arg1 == error_mark_node | |
8179 | || arg2 == error_mark_node) | |
8180 | return const0_rtx; | |
8181 | ||
8182 | if (! (*insn_data[icode].operand[2].predicate) (op0, mode2)) | |
8183 | op0 = copy_to_mode_reg (mode2, op0); | |
8184 | if (! (*insn_data[icode].operand[0].predicate) (op1, mode0)) | |
8185 | op1 = copy_to_mode_reg (mode0, op1); | |
8186 | if (! (*insn_data[icode].operand[1].predicate) (op2, mode1)) | |
8187 | op2 = copy_to_mode_reg (mode1, op2); | |
8188 | ||
8189 | pat = GEN_FCN (icode) (op1, op2, op0); | |
8190 | if (pat) | |
8191 | emit_insn (pat); | |
8192 | return NULL_RTX; | |
8193 | } | |
8194 | ||
96038623 DE |
8195 | static rtx |
8196 | paired_expand_stv_builtin (enum insn_code icode, tree exp) | |
8197 | { | |
8198 | tree arg0 = CALL_EXPR_ARG (exp, 0); | |
8199 | tree arg1 = CALL_EXPR_ARG (exp, 1); | |
8200 | tree arg2 = CALL_EXPR_ARG (exp, 2); | |
8201 | rtx op0 = expand_normal (arg0); | |
8202 | rtx op1 = expand_normal (arg1); | |
8203 | rtx op2 = expand_normal (arg2); | |
8204 | rtx pat, addr; | |
8205 | enum machine_mode tmode = insn_data[icode].operand[0].mode; | |
8206 | enum machine_mode mode1 = Pmode; | |
8207 | enum machine_mode mode2 = Pmode; | |
8208 | ||
8209 | /* Invalid arguments. Bail before doing anything stoopid! */ | |
8210 | if (arg0 == error_mark_node | |
8211 | || arg1 == error_mark_node | |
8212 | || arg2 == error_mark_node) | |
8213 | return const0_rtx; | |
8214 | ||
8215 | if (! (*insn_data[icode].operand[1].predicate) (op0, tmode)) | |
8216 | op0 = copy_to_mode_reg (tmode, op0); | |
8217 | ||
8218 | op2 = copy_to_mode_reg (mode2, op2); | |
8219 | ||
8220 | if (op1 == const0_rtx) | |
8221 | { | |
8222 | addr = gen_rtx_MEM (tmode, op2); | |
8223 | } | |
8224 | else | |
8225 | { | |
8226 | op1 = copy_to_mode_reg (mode1, op1); | |
8227 | addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op1, op2)); | |
8228 | } | |
8229 | ||
8230 | pat = GEN_FCN (icode) (addr, op0); | |
8231 | if (pat) | |
8232 | emit_insn (pat); | |
8233 | return NULL_RTX; | |
8234 | } | |
8235 | ||
6525c0e7 | 8236 | static rtx |
5039610b | 8237 | altivec_expand_stv_builtin (enum insn_code icode, tree exp) |
6525c0e7 | 8238 | { |
5039610b SL |
8239 | tree arg0 = CALL_EXPR_ARG (exp, 0); |
8240 | tree arg1 = CALL_EXPR_ARG (exp, 1); | |
8241 | tree arg2 = CALL_EXPR_ARG (exp, 2); | |
84217346 MD |
8242 | rtx op0 = expand_normal (arg0); |
8243 | rtx op1 = expand_normal (arg1); | |
8244 | rtx op2 = expand_normal (arg2); | |
b4a62fa0 SB |
8245 | rtx pat, addr; |
8246 | enum machine_mode tmode = insn_data[icode].operand[0].mode; | |
8247 | enum machine_mode mode1 = Pmode; | |
8248 | enum machine_mode mode2 = Pmode; | |
6525c0e7 AH |
8249 | |
8250 | /* Invalid arguments. Bail before doing anything stoopid! */ | |
8251 | if (arg0 == error_mark_node | |
8252 | || arg1 == error_mark_node | |
8253 | || arg2 == error_mark_node) | |
9a171fcd | 8254 | return const0_rtx; |
6525c0e7 | 8255 | |
b4a62fa0 SB |
8256 | if (! (*insn_data[icode].operand[1].predicate) (op0, tmode)) |
8257 | op0 = copy_to_mode_reg (tmode, op0); | |
8258 | ||
f676971a | 8259 | op2 = copy_to_mode_reg (mode2, op2); |
b4a62fa0 SB |
8260 | |
8261 | if (op1 == const0_rtx) | |
8262 | { | |
8263 | addr = gen_rtx_MEM (tmode, op2); | |
8264 | } | |
8265 | else | |
8266 | { | |
8267 | op1 = copy_to_mode_reg (mode1, op1); | |
8268 | addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op1, op2)); | |
8269 | } | |
6525c0e7 | 8270 | |
b4a62fa0 | 8271 | pat = GEN_FCN (icode) (addr, op0); |
6525c0e7 AH |
8272 | if (pat) |
8273 | emit_insn (pat); | |
8274 | return NULL_RTX; | |
8275 | } | |
8276 | ||
2212663f | 8277 | static rtx |
5039610b | 8278 | rs6000_expand_ternop_builtin (enum insn_code icode, tree exp, rtx target) |
2212663f DB |
8279 | { |
8280 | rtx pat; | |
5039610b SL |
8281 | tree arg0 = CALL_EXPR_ARG (exp, 0); |
8282 | tree arg1 = CALL_EXPR_ARG (exp, 1); | |
8283 | tree arg2 = CALL_EXPR_ARG (exp, 2); | |
84217346 MD |
8284 | rtx op0 = expand_normal (arg0); |
8285 | rtx op1 = expand_normal (arg1); | |
8286 | rtx op2 = expand_normal (arg2); | |
2212663f DB |
8287 | enum machine_mode tmode = insn_data[icode].operand[0].mode; |
8288 | enum machine_mode mode0 = insn_data[icode].operand[1].mode; | |
8289 | enum machine_mode mode1 = insn_data[icode].operand[2].mode; | |
8290 | enum machine_mode mode2 = insn_data[icode].operand[3].mode; | |
0ac081f6 | 8291 | |
774b5662 DE |
8292 | if (icode == CODE_FOR_nothing) |
8293 | /* Builtin not supported on this processor. */ | |
8294 | return 0; | |
8295 | ||
20e26713 AH |
8296 | /* If we got invalid arguments bail out before generating bad rtl. */ |
8297 | if (arg0 == error_mark_node | |
8298 | || arg1 == error_mark_node | |
8299 | || arg2 == error_mark_node) | |
9a171fcd | 8300 | return const0_rtx; |
20e26713 | 8301 | |
aba5fb01 NS |
8302 | if (icode == CODE_FOR_altivec_vsldoi_v4sf |
8303 | || icode == CODE_FOR_altivec_vsldoi_v4si | |
8304 | || icode == CODE_FOR_altivec_vsldoi_v8hi | |
8305 | || icode == CODE_FOR_altivec_vsldoi_v16qi) | |
b44140e7 AH |
8306 | { |
8307 | /* Only allow 4-bit unsigned literals. */ | |
8bb418a3 | 8308 | STRIP_NOPS (arg2); |
b44140e7 AH |
8309 | if (TREE_CODE (arg2) != INTEGER_CST |
8310 | || TREE_INT_CST_LOW (arg2) & ~0xf) | |
8311 | { | |
8312 | error ("argument 3 must be a 4-bit unsigned literal"); | |
e3277ffb | 8313 | return const0_rtx; |
b44140e7 | 8314 | } |
b44140e7 AH |
8315 | } |
8316 | ||
c62f2db5 | 8317 | if (target == 0 |
2212663f DB |
8318 | || GET_MODE (target) != tmode |
8319 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
8320 | target = gen_reg_rtx (tmode); | |
8321 | ||
8322 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) | |
8323 | op0 = copy_to_mode_reg (mode0, op0); | |
8324 | if (! (*insn_data[icode].operand[2].predicate) (op1, mode1)) | |
8325 | op1 = copy_to_mode_reg (mode1, op1); | |
8326 | if (! (*insn_data[icode].operand[3].predicate) (op2, mode2)) | |
8327 | op2 = copy_to_mode_reg (mode2, op2); | |
8328 | ||
49e39588 RE |
8329 | if (TARGET_PAIRED_FLOAT && icode == CODE_FOR_selv2sf4) |
8330 | pat = GEN_FCN (icode) (target, op0, op1, op2, CONST0_RTX (SFmode)); | |
8331 | else | |
8332 | pat = GEN_FCN (icode) (target, op0, op1, op2); | |
2212663f DB |
8333 | if (! pat) |
8334 | return 0; | |
8335 | emit_insn (pat); | |
8336 | ||
8337 | return target; | |
8338 | } | |
92898235 | 8339 | |
3a9b8c7e | 8340 | /* Expand the lvx builtins. */ |
0ac081f6 | 8341 | static rtx |
a2369ed3 | 8342 | altivec_expand_ld_builtin (tree exp, rtx target, bool *expandedp) |
0ac081f6 | 8343 | { |
5039610b | 8344 | tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0); |
0ac081f6 | 8345 | unsigned int fcode = DECL_FUNCTION_CODE (fndecl); |
3a9b8c7e AH |
8346 | tree arg0; |
8347 | enum machine_mode tmode, mode0; | |
7c3abc73 | 8348 | rtx pat, op0; |
3a9b8c7e | 8349 | enum insn_code icode; |
92898235 | 8350 | |
0ac081f6 AH |
8351 | switch (fcode) |
8352 | { | |
f18c054f | 8353 | case ALTIVEC_BUILTIN_LD_INTERNAL_16qi: |
81466555 | 8354 | icode = CODE_FOR_altivec_lvx_v16qi; |
3a9b8c7e | 8355 | break; |
f18c054f | 8356 | case ALTIVEC_BUILTIN_LD_INTERNAL_8hi: |
81466555 | 8357 | icode = CODE_FOR_altivec_lvx_v8hi; |
3a9b8c7e AH |
8358 | break; |
8359 | case ALTIVEC_BUILTIN_LD_INTERNAL_4si: | |
81466555 | 8360 | icode = CODE_FOR_altivec_lvx_v4si; |
3a9b8c7e AH |
8361 | break; |
8362 | case ALTIVEC_BUILTIN_LD_INTERNAL_4sf: | |
81466555 | 8363 | icode = CODE_FOR_altivec_lvx_v4sf; |
3a9b8c7e AH |
8364 | break; |
8365 | default: | |
8366 | *expandedp = false; | |
8367 | return NULL_RTX; | |
8368 | } | |
0ac081f6 | 8369 | |
3a9b8c7e | 8370 | *expandedp = true; |
f18c054f | 8371 | |
5039610b | 8372 | arg0 = CALL_EXPR_ARG (exp, 0); |
84217346 | 8373 | op0 = expand_normal (arg0); |
3a9b8c7e AH |
8374 | tmode = insn_data[icode].operand[0].mode; |
8375 | mode0 = insn_data[icode].operand[1].mode; | |
f18c054f | 8376 | |
3a9b8c7e AH |
8377 | if (target == 0 |
8378 | || GET_MODE (target) != tmode | |
8379 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
8380 | target = gen_reg_rtx (tmode); | |
24408032 | 8381 | |
3a9b8c7e AH |
8382 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) |
8383 | op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0)); | |
f18c054f | 8384 | |
3a9b8c7e AH |
8385 | pat = GEN_FCN (icode) (target, op0); |
8386 | if (! pat) | |
8387 | return 0; | |
8388 | emit_insn (pat); | |
8389 | return target; | |
8390 | } | |
f18c054f | 8391 | |
3a9b8c7e AH |
8392 | /* Expand the stvx builtins. */ |
8393 | static rtx | |
f676971a | 8394 | altivec_expand_st_builtin (tree exp, rtx target ATTRIBUTE_UNUSED, |
a2369ed3 | 8395 | bool *expandedp) |
3a9b8c7e | 8396 | { |
5039610b | 8397 | tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0); |
3a9b8c7e AH |
8398 | unsigned int fcode = DECL_FUNCTION_CODE (fndecl); |
8399 | tree arg0, arg1; | |
8400 | enum machine_mode mode0, mode1; | |
7c3abc73 | 8401 | rtx pat, op0, op1; |
3a9b8c7e | 8402 | enum insn_code icode; |
f18c054f | 8403 | |
3a9b8c7e AH |
8404 | switch (fcode) |
8405 | { | |
8406 | case ALTIVEC_BUILTIN_ST_INTERNAL_16qi: | |
81466555 | 8407 | icode = CODE_FOR_altivec_stvx_v16qi; |
3a9b8c7e AH |
8408 | break; |
8409 | case ALTIVEC_BUILTIN_ST_INTERNAL_8hi: | |
81466555 | 8410 | icode = CODE_FOR_altivec_stvx_v8hi; |
3a9b8c7e AH |
8411 | break; |
8412 | case ALTIVEC_BUILTIN_ST_INTERNAL_4si: | |
81466555 | 8413 | icode = CODE_FOR_altivec_stvx_v4si; |
3a9b8c7e AH |
8414 | break; |
8415 | case ALTIVEC_BUILTIN_ST_INTERNAL_4sf: | |
81466555 | 8416 | icode = CODE_FOR_altivec_stvx_v4sf; |
3a9b8c7e AH |
8417 | break; |
8418 | default: | |
8419 | *expandedp = false; | |
8420 | return NULL_RTX; | |
8421 | } | |
24408032 | 8422 | |
5039610b SL |
8423 | arg0 = CALL_EXPR_ARG (exp, 0); |
8424 | arg1 = CALL_EXPR_ARG (exp, 1); | |
84217346 MD |
8425 | op0 = expand_normal (arg0); |
8426 | op1 = expand_normal (arg1); | |
3a9b8c7e AH |
8427 | mode0 = insn_data[icode].operand[0].mode; |
8428 | mode1 = insn_data[icode].operand[1].mode; | |
f18c054f | 8429 | |
3a9b8c7e AH |
8430 | if (! (*insn_data[icode].operand[0].predicate) (op0, mode0)) |
8431 | op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0)); | |
8432 | if (! (*insn_data[icode].operand[1].predicate) (op1, mode1)) | |
8433 | op1 = copy_to_mode_reg (mode1, op1); | |
f18c054f | 8434 | |
3a9b8c7e AH |
8435 | pat = GEN_FCN (icode) (op0, op1); |
8436 | if (pat) | |
8437 | emit_insn (pat); | |
f18c054f | 8438 | |
3a9b8c7e AH |
8439 | *expandedp = true; |
8440 | return NULL_RTX; | |
8441 | } | |
f18c054f | 8442 | |
3a9b8c7e AH |
8443 | /* Expand the dst builtins. */ |
8444 | static rtx | |
f676971a | 8445 | altivec_expand_dst_builtin (tree exp, rtx target ATTRIBUTE_UNUSED, |
a2369ed3 | 8446 | bool *expandedp) |
3a9b8c7e | 8447 | { |
5039610b | 8448 | tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0); |
3a9b8c7e AH |
8449 | unsigned int fcode = DECL_FUNCTION_CODE (fndecl); |
8450 | tree arg0, arg1, arg2; | |
8451 | enum machine_mode mode0, mode1, mode2; | |
7c3abc73 | 8452 | rtx pat, op0, op1, op2; |
586de218 | 8453 | const struct builtin_description *d; |
a3170dc6 | 8454 | size_t i; |
f18c054f | 8455 | |
3a9b8c7e | 8456 | *expandedp = false; |
f18c054f | 8457 | |
3a9b8c7e | 8458 | /* Handle DST variants. */ |
586de218 | 8459 | d = bdesc_dst; |
3a9b8c7e AH |
8460 | for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++) |
8461 | if (d->code == fcode) | |
8462 | { | |
5039610b SL |
8463 | arg0 = CALL_EXPR_ARG (exp, 0); |
8464 | arg1 = CALL_EXPR_ARG (exp, 1); | |
8465 | arg2 = CALL_EXPR_ARG (exp, 2); | |
84217346 MD |
8466 | op0 = expand_normal (arg0); |
8467 | op1 = expand_normal (arg1); | |
8468 | op2 = expand_normal (arg2); | |
3a9b8c7e AH |
8469 | mode0 = insn_data[d->icode].operand[0].mode; |
8470 | mode1 = insn_data[d->icode].operand[1].mode; | |
8471 | mode2 = insn_data[d->icode].operand[2].mode; | |
24408032 | 8472 | |
3a9b8c7e AH |
8473 | /* Invalid arguments, bail out before generating bad rtl. */ |
8474 | if (arg0 == error_mark_node | |
8475 | || arg1 == error_mark_node | |
8476 | || arg2 == error_mark_node) | |
8477 | return const0_rtx; | |
f18c054f | 8478 | |
86e7df90 | 8479 | *expandedp = true; |
8bb418a3 | 8480 | STRIP_NOPS (arg2); |
3a9b8c7e AH |
8481 | if (TREE_CODE (arg2) != INTEGER_CST |
8482 | || TREE_INT_CST_LOW (arg2) & ~0x3) | |
8483 | { | |
9e637a26 | 8484 | error ("argument to %qs must be a 2-bit unsigned literal", d->name); |
3a9b8c7e AH |
8485 | return const0_rtx; |
8486 | } | |
f18c054f | 8487 | |
3a9b8c7e | 8488 | if (! (*insn_data[d->icode].operand[0].predicate) (op0, mode0)) |
666158b9 | 8489 | op0 = copy_to_mode_reg (Pmode, op0); |
3a9b8c7e AH |
8490 | if (! (*insn_data[d->icode].operand[1].predicate) (op1, mode1)) |
8491 | op1 = copy_to_mode_reg (mode1, op1); | |
24408032 | 8492 | |
3a9b8c7e AH |
8493 | pat = GEN_FCN (d->icode) (op0, op1, op2); |
8494 | if (pat != 0) | |
8495 | emit_insn (pat); | |
f18c054f | 8496 | |
3a9b8c7e AH |
8497 | return NULL_RTX; |
8498 | } | |
f18c054f | 8499 | |
3a9b8c7e AH |
8500 | return NULL_RTX; |
8501 | } | |
24408032 | 8502 | |
7a4eca66 DE |
8503 | /* Expand vec_init builtin. */ |
8504 | static rtx | |
5039610b | 8505 | altivec_expand_vec_init_builtin (tree type, tree exp, rtx target) |
7a4eca66 DE |
8506 | { |
8507 | enum machine_mode tmode = TYPE_MODE (type); | |
8508 | enum machine_mode inner_mode = GET_MODE_INNER (tmode); | |
8509 | int i, n_elt = GET_MODE_NUNITS (tmode); | |
8510 | rtvec v = rtvec_alloc (n_elt); | |
8511 | ||
8512 | gcc_assert (VECTOR_MODE_P (tmode)); | |
5039610b | 8513 | gcc_assert (n_elt == call_expr_nargs (exp)); |
982afe02 | 8514 | |
5039610b | 8515 | for (i = 0; i < n_elt; ++i) |
7a4eca66 | 8516 | { |
5039610b | 8517 | rtx x = expand_normal (CALL_EXPR_ARG (exp, i)); |
7a4eca66 DE |
8518 | RTVEC_ELT (v, i) = gen_lowpart (inner_mode, x); |
8519 | } | |
8520 | ||
7a4eca66 DE |
8521 | if (!target || !register_operand (target, tmode)) |
8522 | target = gen_reg_rtx (tmode); | |
8523 | ||
8524 | rs6000_expand_vector_init (target, gen_rtx_PARALLEL (tmode, v)); | |
8525 | return target; | |
8526 | } | |
8527 | ||
8528 | /* Return the integer constant in ARG. Constrain it to be in the range | |
8529 | of the subparts of VEC_TYPE; issue an error if not. */ | |
8530 | ||
8531 | static int | |
8532 | get_element_number (tree vec_type, tree arg) | |
8533 | { | |
8534 | unsigned HOST_WIDE_INT elt, max = TYPE_VECTOR_SUBPARTS (vec_type) - 1; | |
8535 | ||
8536 | if (!host_integerp (arg, 1) | |
8537 | || (elt = tree_low_cst (arg, 1), elt > max)) | |
8538 | { | |
8539 | error ("selector must be an integer constant in the range 0..%wi", max); | |
8540 | return 0; | |
8541 | } | |
8542 | ||
8543 | return elt; | |
8544 | } | |
8545 | ||
8546 | /* Expand vec_set builtin. */ | |
8547 | static rtx | |
5039610b | 8548 | altivec_expand_vec_set_builtin (tree exp) |
7a4eca66 DE |
8549 | { |
8550 | enum machine_mode tmode, mode1; | |
8551 | tree arg0, arg1, arg2; | |
8552 | int elt; | |
8553 | rtx op0, op1; | |
8554 | ||
5039610b SL |
8555 | arg0 = CALL_EXPR_ARG (exp, 0); |
8556 | arg1 = CALL_EXPR_ARG (exp, 1); | |
8557 | arg2 = CALL_EXPR_ARG (exp, 2); | |
7a4eca66 DE |
8558 | |
8559 | tmode = TYPE_MODE (TREE_TYPE (arg0)); | |
8560 | mode1 = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0))); | |
8561 | gcc_assert (VECTOR_MODE_P (tmode)); | |
8562 | ||
bbbbb16a ILT |
8563 | op0 = expand_expr (arg0, NULL_RTX, tmode, EXPAND_NORMAL); |
8564 | op1 = expand_expr (arg1, NULL_RTX, mode1, EXPAND_NORMAL); | |
7a4eca66 DE |
8565 | elt = get_element_number (TREE_TYPE (arg0), arg2); |
8566 | ||
8567 | if (GET_MODE (op1) != mode1 && GET_MODE (op1) != VOIDmode) | |
8568 | op1 = convert_modes (mode1, GET_MODE (op1), op1, true); | |
8569 | ||
8570 | op0 = force_reg (tmode, op0); | |
8571 | op1 = force_reg (mode1, op1); | |
8572 | ||
8573 | rs6000_expand_vector_set (op0, op1, elt); | |
8574 | ||
8575 | return op0; | |
8576 | } | |
8577 | ||
8578 | /* Expand vec_ext builtin. */ | |
8579 | static rtx | |
5039610b | 8580 | altivec_expand_vec_ext_builtin (tree exp, rtx target) |
7a4eca66 DE |
8581 | { |
8582 | enum machine_mode tmode, mode0; | |
8583 | tree arg0, arg1; | |
8584 | int elt; | |
8585 | rtx op0; | |
8586 | ||
5039610b SL |
8587 | arg0 = CALL_EXPR_ARG (exp, 0); |
8588 | arg1 = CALL_EXPR_ARG (exp, 1); | |
7a4eca66 | 8589 | |
84217346 | 8590 | op0 = expand_normal (arg0); |
7a4eca66 DE |
8591 | elt = get_element_number (TREE_TYPE (arg0), arg1); |
8592 | ||
8593 | tmode = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0))); | |
8594 | mode0 = TYPE_MODE (TREE_TYPE (arg0)); | |
8595 | gcc_assert (VECTOR_MODE_P (mode0)); | |
8596 | ||
8597 | op0 = force_reg (mode0, op0); | |
8598 | ||
8599 | if (optimize || !target || !register_operand (target, tmode)) | |
8600 | target = gen_reg_rtx (tmode); | |
8601 | ||
8602 | rs6000_expand_vector_extract (target, op0, elt); | |
8603 | ||
8604 | return target; | |
8605 | } | |
8606 | ||
3a9b8c7e AH |
8607 | /* Expand the builtin in EXP and store the result in TARGET. Store |
8608 | true in *EXPANDEDP if we found a builtin to expand. */ | |
8609 | static rtx | |
a2369ed3 | 8610 | altivec_expand_builtin (tree exp, rtx target, bool *expandedp) |
3a9b8c7e | 8611 | { |
586de218 KG |
8612 | const struct builtin_description *d; |
8613 | const struct builtin_description_predicates *dp; | |
3a9b8c7e AH |
8614 | size_t i; |
8615 | enum insn_code icode; | |
5039610b | 8616 | tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0); |
7c3abc73 AH |
8617 | tree arg0; |
8618 | rtx op0, pat; | |
8619 | enum machine_mode tmode, mode0; | |
3a9b8c7e | 8620 | unsigned int fcode = DECL_FUNCTION_CODE (fndecl); |
0ac081f6 | 8621 | |
58646b77 PB |
8622 | if (fcode >= ALTIVEC_BUILTIN_OVERLOADED_FIRST |
8623 | && fcode <= ALTIVEC_BUILTIN_OVERLOADED_LAST) | |
8624 | { | |
8625 | *expandedp = true; | |
ea40ba9c | 8626 | error ("unresolved overload for Altivec builtin %qF", fndecl); |
58646b77 PB |
8627 | return const0_rtx; |
8628 | } | |
8629 | ||
3a9b8c7e AH |
8630 | target = altivec_expand_ld_builtin (exp, target, expandedp); |
8631 | if (*expandedp) | |
8632 | return target; | |
0ac081f6 | 8633 | |
3a9b8c7e AH |
8634 | target = altivec_expand_st_builtin (exp, target, expandedp); |
8635 | if (*expandedp) | |
8636 | return target; | |
8637 | ||
8638 | target = altivec_expand_dst_builtin (exp, target, expandedp); | |
8639 | if (*expandedp) | |
8640 | return target; | |
8641 | ||
8642 | *expandedp = true; | |
95385cbb | 8643 | |
3a9b8c7e AH |
8644 | switch (fcode) |
8645 | { | |
6525c0e7 | 8646 | case ALTIVEC_BUILTIN_STVX: |
5039610b | 8647 | return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx, exp); |
6525c0e7 | 8648 | case ALTIVEC_BUILTIN_STVEBX: |
5039610b | 8649 | return altivec_expand_stv_builtin (CODE_FOR_altivec_stvebx, exp); |
6525c0e7 | 8650 | case ALTIVEC_BUILTIN_STVEHX: |
5039610b | 8651 | return altivec_expand_stv_builtin (CODE_FOR_altivec_stvehx, exp); |
6525c0e7 | 8652 | case ALTIVEC_BUILTIN_STVEWX: |
5039610b | 8653 | return altivec_expand_stv_builtin (CODE_FOR_altivec_stvewx, exp); |
6525c0e7 | 8654 | case ALTIVEC_BUILTIN_STVXL: |
5039610b | 8655 | return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl, exp); |
3a9b8c7e | 8656 | |
0b61703c AP |
8657 | case ALTIVEC_BUILTIN_STVLX: |
8658 | return altivec_expand_stv_builtin (CODE_FOR_altivec_stvlx, exp); | |
8659 | case ALTIVEC_BUILTIN_STVLXL: | |
8660 | return altivec_expand_stv_builtin (CODE_FOR_altivec_stvlxl, exp); | |
8661 | case ALTIVEC_BUILTIN_STVRX: | |
8662 | return altivec_expand_stv_builtin (CODE_FOR_altivec_stvrx, exp); | |
8663 | case ALTIVEC_BUILTIN_STVRXL: | |
8664 | return altivec_expand_stv_builtin (CODE_FOR_altivec_stvrxl, exp); | |
8665 | ||
95385cbb AH |
8666 | case ALTIVEC_BUILTIN_MFVSCR: |
8667 | icode = CODE_FOR_altivec_mfvscr; | |
8668 | tmode = insn_data[icode].operand[0].mode; | |
8669 | ||
8670 | if (target == 0 | |
8671 | || GET_MODE (target) != tmode | |
8672 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
8673 | target = gen_reg_rtx (tmode); | |
f676971a | 8674 | |
95385cbb | 8675 | pat = GEN_FCN (icode) (target); |
0ac081f6 AH |
8676 | if (! pat) |
8677 | return 0; | |
8678 | emit_insn (pat); | |
95385cbb AH |
8679 | return target; |
8680 | ||
8681 | case ALTIVEC_BUILTIN_MTVSCR: | |
8682 | icode = CODE_FOR_altivec_mtvscr; | |
5039610b | 8683 | arg0 = CALL_EXPR_ARG (exp, 0); |
84217346 | 8684 | op0 = expand_normal (arg0); |
95385cbb AH |
8685 | mode0 = insn_data[icode].operand[0].mode; |
8686 | ||
8687 | /* If we got invalid arguments bail out before generating bad rtl. */ | |
8688 | if (arg0 == error_mark_node) | |
9a171fcd | 8689 | return const0_rtx; |
95385cbb AH |
8690 | |
8691 | if (! (*insn_data[icode].operand[0].predicate) (op0, mode0)) | |
8692 | op0 = copy_to_mode_reg (mode0, op0); | |
8693 | ||
8694 | pat = GEN_FCN (icode) (op0); | |
8695 | if (pat) | |
8696 | emit_insn (pat); | |
8697 | return NULL_RTX; | |
3a9b8c7e | 8698 | |
95385cbb AH |
8699 | case ALTIVEC_BUILTIN_DSSALL: |
8700 | emit_insn (gen_altivec_dssall ()); | |
8701 | return NULL_RTX; | |
8702 | ||
8703 | case ALTIVEC_BUILTIN_DSS: | |
8704 | icode = CODE_FOR_altivec_dss; | |
5039610b | 8705 | arg0 = CALL_EXPR_ARG (exp, 0); |
8bb418a3 | 8706 | STRIP_NOPS (arg0); |
84217346 | 8707 | op0 = expand_normal (arg0); |
95385cbb AH |
8708 | mode0 = insn_data[icode].operand[0].mode; |
8709 | ||
8710 | /* If we got invalid arguments bail out before generating bad rtl. */ | |
8711 | if (arg0 == error_mark_node) | |
9a171fcd | 8712 | return const0_rtx; |
95385cbb | 8713 | |
b44140e7 AH |
8714 | if (TREE_CODE (arg0) != INTEGER_CST |
8715 | || TREE_INT_CST_LOW (arg0) & ~0x3) | |
8716 | { | |
8717 | error ("argument to dss must be a 2-bit unsigned literal"); | |
9a171fcd | 8718 | return const0_rtx; |
b44140e7 AH |
8719 | } |
8720 | ||
95385cbb AH |
8721 | if (! (*insn_data[icode].operand[0].predicate) (op0, mode0)) |
8722 | op0 = copy_to_mode_reg (mode0, op0); | |
8723 | ||
8724 | emit_insn (gen_altivec_dss (op0)); | |
0ac081f6 | 8725 | return NULL_RTX; |
7a4eca66 DE |
8726 | |
8727 | case ALTIVEC_BUILTIN_VEC_INIT_V4SI: | |
8728 | case ALTIVEC_BUILTIN_VEC_INIT_V8HI: | |
8729 | case ALTIVEC_BUILTIN_VEC_INIT_V16QI: | |
8730 | case ALTIVEC_BUILTIN_VEC_INIT_V4SF: | |
5039610b | 8731 | return altivec_expand_vec_init_builtin (TREE_TYPE (exp), exp, target); |
7a4eca66 DE |
8732 | |
8733 | case ALTIVEC_BUILTIN_VEC_SET_V4SI: | |
8734 | case ALTIVEC_BUILTIN_VEC_SET_V8HI: | |
8735 | case ALTIVEC_BUILTIN_VEC_SET_V16QI: | |
8736 | case ALTIVEC_BUILTIN_VEC_SET_V4SF: | |
5039610b | 8737 | return altivec_expand_vec_set_builtin (exp); |
7a4eca66 DE |
8738 | |
8739 | case ALTIVEC_BUILTIN_VEC_EXT_V4SI: | |
8740 | case ALTIVEC_BUILTIN_VEC_EXT_V8HI: | |
8741 | case ALTIVEC_BUILTIN_VEC_EXT_V16QI: | |
8742 | case ALTIVEC_BUILTIN_VEC_EXT_V4SF: | |
5039610b | 8743 | return altivec_expand_vec_ext_builtin (exp, target); |
7a4eca66 DE |
8744 | |
8745 | default: | |
8746 | break; | |
8747 | /* Fall through. */ | |
0ac081f6 | 8748 | } |
24408032 | 8749 | |
100c4561 | 8750 | /* Expand abs* operations. */ |
586de218 | 8751 | d = bdesc_abs; |
ca7558fc | 8752 | for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++) |
100c4561 | 8753 | if (d->code == fcode) |
5039610b | 8754 | return altivec_expand_abs_builtin (d->icode, exp, target); |
100c4561 | 8755 | |
ae4b4a02 | 8756 | /* Expand the AltiVec predicates. */ |
586de218 | 8757 | dp = bdesc_altivec_preds; |
ca7558fc | 8758 | for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, dp++) |
ae4b4a02 | 8759 | if (dp->code == fcode) |
c4ad648e | 8760 | return altivec_expand_predicate_builtin (dp->icode, dp->opcode, |
5039610b | 8761 | exp, target); |
ae4b4a02 | 8762 | |
6525c0e7 AH |
8763 | /* LV* are funky. We initialized them differently. */ |
8764 | switch (fcode) | |
8765 | { | |
8766 | case ALTIVEC_BUILTIN_LVSL: | |
b4a62fa0 | 8767 | return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsl, |
0b61703c | 8768 | exp, target, false); |
6525c0e7 | 8769 | case ALTIVEC_BUILTIN_LVSR: |
b4a62fa0 | 8770 | return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsr, |
0b61703c | 8771 | exp, target, false); |
6525c0e7 | 8772 | case ALTIVEC_BUILTIN_LVEBX: |
b4a62fa0 | 8773 | return altivec_expand_lv_builtin (CODE_FOR_altivec_lvebx, |
0b61703c | 8774 | exp, target, false); |
6525c0e7 | 8775 | case ALTIVEC_BUILTIN_LVEHX: |
b4a62fa0 | 8776 | return altivec_expand_lv_builtin (CODE_FOR_altivec_lvehx, |
0b61703c | 8777 | exp, target, false); |
6525c0e7 | 8778 | case ALTIVEC_BUILTIN_LVEWX: |
b4a62fa0 | 8779 | return altivec_expand_lv_builtin (CODE_FOR_altivec_lvewx, |
0b61703c | 8780 | exp, target, false); |
6525c0e7 | 8781 | case ALTIVEC_BUILTIN_LVXL: |
b4a62fa0 | 8782 | return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl, |
0b61703c | 8783 | exp, target, false); |
6525c0e7 | 8784 | case ALTIVEC_BUILTIN_LVX: |
b4a62fa0 | 8785 | return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx, |
0b61703c AP |
8786 | exp, target, false); |
8787 | case ALTIVEC_BUILTIN_LVLX: | |
8788 | return altivec_expand_lv_builtin (CODE_FOR_altivec_lvlx, | |
8789 | exp, target, true); | |
8790 | case ALTIVEC_BUILTIN_LVLXL: | |
8791 | return altivec_expand_lv_builtin (CODE_FOR_altivec_lvlxl, | |
8792 | exp, target, true); | |
8793 | case ALTIVEC_BUILTIN_LVRX: | |
8794 | return altivec_expand_lv_builtin (CODE_FOR_altivec_lvrx, | |
8795 | exp, target, true); | |
8796 | case ALTIVEC_BUILTIN_LVRXL: | |
8797 | return altivec_expand_lv_builtin (CODE_FOR_altivec_lvrxl, | |
8798 | exp, target, true); | |
6525c0e7 AH |
8799 | default: |
8800 | break; | |
8801 | /* Fall through. */ | |
8802 | } | |
95385cbb | 8803 | |
92898235 | 8804 | *expandedp = false; |
0ac081f6 AH |
8805 | return NULL_RTX; |
8806 | } | |
8807 | ||
96038623 DE |
8808 | /* Expand the builtin in EXP and store the result in TARGET. Store |
8809 | true in *EXPANDEDP if we found a builtin to expand. */ | |
8810 | static rtx | |
8811 | paired_expand_builtin (tree exp, rtx target, bool * expandedp) | |
8812 | { | |
8813 | tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0); | |
8814 | unsigned int fcode = DECL_FUNCTION_CODE (fndecl); | |
23a651fc | 8815 | const struct builtin_description *d; |
96038623 DE |
8816 | size_t i; |
8817 | ||
8818 | *expandedp = true; | |
8819 | ||
8820 | switch (fcode) | |
8821 | { | |
8822 | case PAIRED_BUILTIN_STX: | |
8823 | return paired_expand_stv_builtin (CODE_FOR_paired_stx, exp); | |
8824 | case PAIRED_BUILTIN_LX: | |
8825 | return paired_expand_lv_builtin (CODE_FOR_paired_lx, exp, target); | |
8826 | default: | |
8827 | break; | |
8828 | /* Fall through. */ | |
8829 | } | |
8830 | ||
8831 | /* Expand the paired predicates. */ | |
23a651fc | 8832 | d = bdesc_paired_preds; |
96038623 DE |
8833 | for (i = 0; i < ARRAY_SIZE (bdesc_paired_preds); i++, d++) |
8834 | if (d->code == fcode) | |
8835 | return paired_expand_predicate_builtin (d->icode, exp, target); | |
8836 | ||
8837 | *expandedp = false; | |
8838 | return NULL_RTX; | |
8839 | } | |
8840 | ||
a3170dc6 AH |
8841 | /* Binops that need to be initialized manually, but can be expanded |
8842 | automagically by rs6000_expand_binop_builtin. */ | |
8843 | static struct builtin_description bdesc_2arg_spe[] = | |
8844 | { | |
8845 | { 0, CODE_FOR_spe_evlddx, "__builtin_spe_evlddx", SPE_BUILTIN_EVLDDX }, | |
8846 | { 0, CODE_FOR_spe_evldwx, "__builtin_spe_evldwx", SPE_BUILTIN_EVLDWX }, | |
8847 | { 0, CODE_FOR_spe_evldhx, "__builtin_spe_evldhx", SPE_BUILTIN_EVLDHX }, | |
8848 | { 0, CODE_FOR_spe_evlwhex, "__builtin_spe_evlwhex", SPE_BUILTIN_EVLWHEX }, | |
8849 | { 0, CODE_FOR_spe_evlwhoux, "__builtin_spe_evlwhoux", SPE_BUILTIN_EVLWHOUX }, | |
8850 | { 0, CODE_FOR_spe_evlwhosx, "__builtin_spe_evlwhosx", SPE_BUILTIN_EVLWHOSX }, | |
8851 | { 0, CODE_FOR_spe_evlwwsplatx, "__builtin_spe_evlwwsplatx", SPE_BUILTIN_EVLWWSPLATX }, | |
8852 | { 0, CODE_FOR_spe_evlwhsplatx, "__builtin_spe_evlwhsplatx", SPE_BUILTIN_EVLWHSPLATX }, | |
8853 | { 0, CODE_FOR_spe_evlhhesplatx, "__builtin_spe_evlhhesplatx", SPE_BUILTIN_EVLHHESPLATX }, | |
8854 | { 0, CODE_FOR_spe_evlhhousplatx, "__builtin_spe_evlhhousplatx", SPE_BUILTIN_EVLHHOUSPLATX }, | |
8855 | { 0, CODE_FOR_spe_evlhhossplatx, "__builtin_spe_evlhhossplatx", SPE_BUILTIN_EVLHHOSSPLATX }, | |
8856 | { 0, CODE_FOR_spe_evldd, "__builtin_spe_evldd", SPE_BUILTIN_EVLDD }, | |
8857 | { 0, CODE_FOR_spe_evldw, "__builtin_spe_evldw", SPE_BUILTIN_EVLDW }, | |
8858 | { 0, CODE_FOR_spe_evldh, "__builtin_spe_evldh", SPE_BUILTIN_EVLDH }, | |
8859 | { 0, CODE_FOR_spe_evlwhe, "__builtin_spe_evlwhe", SPE_BUILTIN_EVLWHE }, | |
8860 | { 0, CODE_FOR_spe_evlwhou, "__builtin_spe_evlwhou", SPE_BUILTIN_EVLWHOU }, | |
8861 | { 0, CODE_FOR_spe_evlwhos, "__builtin_spe_evlwhos", SPE_BUILTIN_EVLWHOS }, | |
8862 | { 0, CODE_FOR_spe_evlwwsplat, "__builtin_spe_evlwwsplat", SPE_BUILTIN_EVLWWSPLAT }, | |
8863 | { 0, CODE_FOR_spe_evlwhsplat, "__builtin_spe_evlwhsplat", SPE_BUILTIN_EVLWHSPLAT }, | |
8864 | { 0, CODE_FOR_spe_evlhhesplat, "__builtin_spe_evlhhesplat", SPE_BUILTIN_EVLHHESPLAT }, | |
8865 | { 0, CODE_FOR_spe_evlhhousplat, "__builtin_spe_evlhhousplat", SPE_BUILTIN_EVLHHOUSPLAT }, | |
8866 | { 0, CODE_FOR_spe_evlhhossplat, "__builtin_spe_evlhhossplat", SPE_BUILTIN_EVLHHOSSPLAT } | |
8867 | }; | |
8868 | ||
8869 | /* Expand the builtin in EXP and store the result in TARGET. Store | |
8870 | true in *EXPANDEDP if we found a builtin to expand. | |
8871 | ||
8872 | This expands the SPE builtins that are not simple unary and binary | |
8873 | operations. */ | |
8874 | static rtx | |
a2369ed3 | 8875 | spe_expand_builtin (tree exp, rtx target, bool *expandedp) |
a3170dc6 | 8876 | { |
5039610b | 8877 | tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0); |
a3170dc6 AH |
8878 | tree arg1, arg0; |
8879 | unsigned int fcode = DECL_FUNCTION_CODE (fndecl); | |
8880 | enum insn_code icode; | |
8881 | enum machine_mode tmode, mode0; | |
8882 | rtx pat, op0; | |
8883 | struct builtin_description *d; | |
8884 | size_t i; | |
8885 | ||
8886 | *expandedp = true; | |
8887 | ||
8888 | /* Syntax check for a 5-bit unsigned immediate. */ | |
8889 | switch (fcode) | |
8890 | { | |
8891 | case SPE_BUILTIN_EVSTDD: | |
8892 | case SPE_BUILTIN_EVSTDH: | |
8893 | case SPE_BUILTIN_EVSTDW: | |
8894 | case SPE_BUILTIN_EVSTWHE: | |
8895 | case SPE_BUILTIN_EVSTWHO: | |
8896 | case SPE_BUILTIN_EVSTWWE: | |
8897 | case SPE_BUILTIN_EVSTWWO: | |
5039610b | 8898 | arg1 = CALL_EXPR_ARG (exp, 2); |
a3170dc6 AH |
8899 | if (TREE_CODE (arg1) != INTEGER_CST |
8900 | || TREE_INT_CST_LOW (arg1) & ~0x1f) | |
8901 | { | |
8902 | error ("argument 2 must be a 5-bit unsigned literal"); | |
8903 | return const0_rtx; | |
8904 | } | |
8905 | break; | |
8906 | default: | |
8907 | break; | |
8908 | } | |
8909 | ||
00332c9f AH |
8910 | /* The evsplat*i instructions are not quite generic. */ |
8911 | switch (fcode) | |
8912 | { | |
8913 | case SPE_BUILTIN_EVSPLATFI: | |
8914 | return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplatfi, | |
5039610b | 8915 | exp, target); |
00332c9f AH |
8916 | case SPE_BUILTIN_EVSPLATI: |
8917 | return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplati, | |
5039610b | 8918 | exp, target); |
00332c9f AH |
8919 | default: |
8920 | break; | |
8921 | } | |
8922 | ||
a3170dc6 AH |
8923 | d = (struct builtin_description *) bdesc_2arg_spe; |
8924 | for (i = 0; i < ARRAY_SIZE (bdesc_2arg_spe); ++i, ++d) | |
8925 | if (d->code == fcode) | |
5039610b | 8926 | return rs6000_expand_binop_builtin (d->icode, exp, target); |
a3170dc6 AH |
8927 | |
8928 | d = (struct builtin_description *) bdesc_spe_predicates; | |
8929 | for (i = 0; i < ARRAY_SIZE (bdesc_spe_predicates); ++i, ++d) | |
8930 | if (d->code == fcode) | |
5039610b | 8931 | return spe_expand_predicate_builtin (d->icode, exp, target); |
a3170dc6 AH |
8932 | |
8933 | d = (struct builtin_description *) bdesc_spe_evsel; | |
8934 | for (i = 0; i < ARRAY_SIZE (bdesc_spe_evsel); ++i, ++d) | |
8935 | if (d->code == fcode) | |
5039610b | 8936 | return spe_expand_evsel_builtin (d->icode, exp, target); |
a3170dc6 AH |
8937 | |
8938 | switch (fcode) | |
8939 | { | |
8940 | case SPE_BUILTIN_EVSTDDX: | |
5039610b | 8941 | return spe_expand_stv_builtin (CODE_FOR_spe_evstddx, exp); |
a3170dc6 | 8942 | case SPE_BUILTIN_EVSTDHX: |
5039610b | 8943 | return spe_expand_stv_builtin (CODE_FOR_spe_evstdhx, exp); |
a3170dc6 | 8944 | case SPE_BUILTIN_EVSTDWX: |
5039610b | 8945 | return spe_expand_stv_builtin (CODE_FOR_spe_evstdwx, exp); |
a3170dc6 | 8946 | case SPE_BUILTIN_EVSTWHEX: |
5039610b | 8947 | return spe_expand_stv_builtin (CODE_FOR_spe_evstwhex, exp); |
a3170dc6 | 8948 | case SPE_BUILTIN_EVSTWHOX: |
5039610b | 8949 | return spe_expand_stv_builtin (CODE_FOR_spe_evstwhox, exp); |
a3170dc6 | 8950 | case SPE_BUILTIN_EVSTWWEX: |
5039610b | 8951 | return spe_expand_stv_builtin (CODE_FOR_spe_evstwwex, exp); |
a3170dc6 | 8952 | case SPE_BUILTIN_EVSTWWOX: |
5039610b | 8953 | return spe_expand_stv_builtin (CODE_FOR_spe_evstwwox, exp); |
a3170dc6 | 8954 | case SPE_BUILTIN_EVSTDD: |
5039610b | 8955 | return spe_expand_stv_builtin (CODE_FOR_spe_evstdd, exp); |
a3170dc6 | 8956 | case SPE_BUILTIN_EVSTDH: |
5039610b | 8957 | return spe_expand_stv_builtin (CODE_FOR_spe_evstdh, exp); |
a3170dc6 | 8958 | case SPE_BUILTIN_EVSTDW: |
5039610b | 8959 | return spe_expand_stv_builtin (CODE_FOR_spe_evstdw, exp); |
a3170dc6 | 8960 | case SPE_BUILTIN_EVSTWHE: |
5039610b | 8961 | return spe_expand_stv_builtin (CODE_FOR_spe_evstwhe, exp); |
a3170dc6 | 8962 | case SPE_BUILTIN_EVSTWHO: |
5039610b | 8963 | return spe_expand_stv_builtin (CODE_FOR_spe_evstwho, exp); |
a3170dc6 | 8964 | case SPE_BUILTIN_EVSTWWE: |
5039610b | 8965 | return spe_expand_stv_builtin (CODE_FOR_spe_evstwwe, exp); |
a3170dc6 | 8966 | case SPE_BUILTIN_EVSTWWO: |
5039610b | 8967 | return spe_expand_stv_builtin (CODE_FOR_spe_evstwwo, exp); |
a3170dc6 AH |
8968 | case SPE_BUILTIN_MFSPEFSCR: |
8969 | icode = CODE_FOR_spe_mfspefscr; | |
8970 | tmode = insn_data[icode].operand[0].mode; | |
8971 | ||
8972 | if (target == 0 | |
8973 | || GET_MODE (target) != tmode | |
8974 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
8975 | target = gen_reg_rtx (tmode); | |
f676971a | 8976 | |
a3170dc6 AH |
8977 | pat = GEN_FCN (icode) (target); |
8978 | if (! pat) | |
8979 | return 0; | |
8980 | emit_insn (pat); | |
8981 | return target; | |
8982 | case SPE_BUILTIN_MTSPEFSCR: | |
8983 | icode = CODE_FOR_spe_mtspefscr; | |
5039610b | 8984 | arg0 = CALL_EXPR_ARG (exp, 0); |
84217346 | 8985 | op0 = expand_normal (arg0); |
a3170dc6 AH |
8986 | mode0 = insn_data[icode].operand[0].mode; |
8987 | ||
8988 | if (arg0 == error_mark_node) | |
8989 | return const0_rtx; | |
8990 | ||
8991 | if (! (*insn_data[icode].operand[0].predicate) (op0, mode0)) | |
8992 | op0 = copy_to_mode_reg (mode0, op0); | |
8993 | ||
8994 | pat = GEN_FCN (icode) (op0); | |
8995 | if (pat) | |
8996 | emit_insn (pat); | |
8997 | return NULL_RTX; | |
8998 | default: | |
8999 | break; | |
9000 | } | |
9001 | ||
9002 | *expandedp = false; | |
9003 | return NULL_RTX; | |
9004 | } | |
9005 | ||
96038623 DE |
9006 | static rtx |
9007 | paired_expand_predicate_builtin (enum insn_code icode, tree exp, rtx target) | |
9008 | { | |
9009 | rtx pat, scratch, tmp; | |
9010 | tree form = CALL_EXPR_ARG (exp, 0); | |
9011 | tree arg0 = CALL_EXPR_ARG (exp, 1); | |
9012 | tree arg1 = CALL_EXPR_ARG (exp, 2); | |
9013 | rtx op0 = expand_normal (arg0); | |
9014 | rtx op1 = expand_normal (arg1); | |
9015 | enum machine_mode mode0 = insn_data[icode].operand[1].mode; | |
9016 | enum machine_mode mode1 = insn_data[icode].operand[2].mode; | |
9017 | int form_int; | |
9018 | enum rtx_code code; | |
9019 | ||
9020 | if (TREE_CODE (form) != INTEGER_CST) | |
9021 | { | |
9022 | error ("argument 1 of __builtin_paired_predicate must be a constant"); | |
9023 | return const0_rtx; | |
9024 | } | |
9025 | else | |
9026 | form_int = TREE_INT_CST_LOW (form); | |
9027 | ||
9028 | gcc_assert (mode0 == mode1); | |
9029 | ||
9030 | if (arg0 == error_mark_node || arg1 == error_mark_node) | |
9031 | return const0_rtx; | |
9032 | ||
9033 | if (target == 0 | |
9034 | || GET_MODE (target) != SImode | |
9035 | || !(*insn_data[icode].operand[0].predicate) (target, SImode)) | |
9036 | target = gen_reg_rtx (SImode); | |
9037 | if (!(*insn_data[icode].operand[1].predicate) (op0, mode0)) | |
9038 | op0 = copy_to_mode_reg (mode0, op0); | |
9039 | if (!(*insn_data[icode].operand[2].predicate) (op1, mode1)) | |
9040 | op1 = copy_to_mode_reg (mode1, op1); | |
9041 | ||
9042 | scratch = gen_reg_rtx (CCFPmode); | |
9043 | ||
9044 | pat = GEN_FCN (icode) (scratch, op0, op1); | |
9045 | if (!pat) | |
9046 | return const0_rtx; | |
9047 | ||
9048 | emit_insn (pat); | |
9049 | ||
9050 | switch (form_int) | |
9051 | { | |
9052 | /* LT bit. */ | |
9053 | case 0: | |
9054 | code = LT; | |
9055 | break; | |
9056 | /* GT bit. */ | |
9057 | case 1: | |
9058 | code = GT; | |
9059 | break; | |
9060 | /* EQ bit. */ | |
9061 | case 2: | |
9062 | code = EQ; | |
9063 | break; | |
9064 | /* UN bit. */ | |
9065 | case 3: | |
9066 | emit_insn (gen_move_from_CR_ov_bit (target, scratch)); | |
9067 | return target; | |
9068 | default: | |
9069 | error ("argument 1 of __builtin_paired_predicate is out of range"); | |
9070 | return const0_rtx; | |
9071 | } | |
9072 | ||
9073 | tmp = gen_rtx_fmt_ee (code, SImode, scratch, const0_rtx); | |
9074 | emit_move_insn (target, tmp); | |
9075 | return target; | |
9076 | } | |
9077 | ||
a3170dc6 | 9078 | static rtx |
5039610b | 9079 | spe_expand_predicate_builtin (enum insn_code icode, tree exp, rtx target) |
a3170dc6 AH |
9080 | { |
9081 | rtx pat, scratch, tmp; | |
5039610b SL |
9082 | tree form = CALL_EXPR_ARG (exp, 0); |
9083 | tree arg0 = CALL_EXPR_ARG (exp, 1); | |
9084 | tree arg1 = CALL_EXPR_ARG (exp, 2); | |
84217346 MD |
9085 | rtx op0 = expand_normal (arg0); |
9086 | rtx op1 = expand_normal (arg1); | |
a3170dc6 AH |
9087 | enum machine_mode mode0 = insn_data[icode].operand[1].mode; |
9088 | enum machine_mode mode1 = insn_data[icode].operand[2].mode; | |
9089 | int form_int; | |
9090 | enum rtx_code code; | |
9091 | ||
9092 | if (TREE_CODE (form) != INTEGER_CST) | |
9093 | { | |
9094 | error ("argument 1 of __builtin_spe_predicate must be a constant"); | |
9095 | return const0_rtx; | |
9096 | } | |
9097 | else | |
9098 | form_int = TREE_INT_CST_LOW (form); | |
9099 | ||
37409796 | 9100 | gcc_assert (mode0 == mode1); |
a3170dc6 AH |
9101 | |
9102 | if (arg0 == error_mark_node || arg1 == error_mark_node) | |
9103 | return const0_rtx; | |
9104 | ||
9105 | if (target == 0 | |
9106 | || GET_MODE (target) != SImode | |
9107 | || ! (*insn_data[icode].operand[0].predicate) (target, SImode)) | |
9108 | target = gen_reg_rtx (SImode); | |
9109 | ||
9110 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) | |
9111 | op0 = copy_to_mode_reg (mode0, op0); | |
9112 | if (! (*insn_data[icode].operand[2].predicate) (op1, mode1)) | |
9113 | op1 = copy_to_mode_reg (mode1, op1); | |
9114 | ||
9115 | scratch = gen_reg_rtx (CCmode); | |
9116 | ||
9117 | pat = GEN_FCN (icode) (scratch, op0, op1); | |
9118 | if (! pat) | |
9119 | return const0_rtx; | |
9120 | emit_insn (pat); | |
9121 | ||
9122 | /* There are 4 variants for each predicate: _any_, _all_, _upper_, | |
9123 | _lower_. We use one compare, but look in different bits of the | |
9124 | CR for each variant. | |
9125 | ||
9126 | There are 2 elements in each SPE simd type (upper/lower). The CR | |
9127 | bits are set as follows: | |
9128 | ||
9129 | BIT0 | BIT 1 | BIT 2 | BIT 3 | |
9130 | U | L | (U | L) | (U & L) | |
9131 | ||
9132 | So, for an "all" relationship, BIT 3 would be set. | |
9133 | For an "any" relationship, BIT 2 would be set. Etc. | |
9134 | ||
9135 | Following traditional nomenclature, these bits map to: | |
9136 | ||
9137 | BIT0 | BIT 1 | BIT 2 | BIT 3 | |
9138 | LT | GT | EQ | OV | |
9139 | ||
9140 | Later, we will generate rtl to look in the LT/EQ/EQ/OV bits. | |
9141 | */ | |
9142 | ||
9143 | switch (form_int) | |
9144 | { | |
9145 | /* All variant. OV bit. */ | |
9146 | case 0: | |
9147 | /* We need to get to the OV bit, which is the ORDERED bit. We | |
9148 | could generate (ordered:SI (reg:CC xx) (const_int 0)), but | |
992d08b1 | 9149 | that's ugly and will make validate_condition_mode die. |
a3170dc6 AH |
9150 | So let's just use another pattern. */ |
9151 | emit_insn (gen_move_from_CR_ov_bit (target, scratch)); | |
9152 | return target; | |
9153 | /* Any variant. EQ bit. */ | |
9154 | case 1: | |
9155 | code = EQ; | |
9156 | break; | |
9157 | /* Upper variant. LT bit. */ | |
9158 | case 2: | |
9159 | code = LT; | |
9160 | break; | |
9161 | /* Lower variant. GT bit. */ | |
9162 | case 3: | |
9163 | code = GT; | |
9164 | break; | |
9165 | default: | |
9166 | error ("argument 1 of __builtin_spe_predicate is out of range"); | |
9167 | return const0_rtx; | |
9168 | } | |
9169 | ||
9170 | tmp = gen_rtx_fmt_ee (code, SImode, scratch, const0_rtx); | |
9171 | emit_move_insn (target, tmp); | |
9172 | ||
9173 | return target; | |
9174 | } | |
9175 | ||
9176 | /* The evsel builtins look like this: | |
9177 | ||
9178 | e = __builtin_spe_evsel_OP (a, b, c, d); | |
9179 | ||
9180 | and work like this: | |
9181 | ||
9182 | e[upper] = a[upper] *OP* b[upper] ? c[upper] : d[upper]; | |
9183 | e[lower] = a[lower] *OP* b[lower] ? c[lower] : d[lower]; | |
9184 | */ | |
9185 | ||
9186 | static rtx | |
5039610b | 9187 | spe_expand_evsel_builtin (enum insn_code icode, tree exp, rtx target) |
a3170dc6 AH |
9188 | { |
9189 | rtx pat, scratch; | |
5039610b SL |
9190 | tree arg0 = CALL_EXPR_ARG (exp, 0); |
9191 | tree arg1 = CALL_EXPR_ARG (exp, 1); | |
9192 | tree arg2 = CALL_EXPR_ARG (exp, 2); | |
9193 | tree arg3 = CALL_EXPR_ARG (exp, 3); | |
84217346 MD |
9194 | rtx op0 = expand_normal (arg0); |
9195 | rtx op1 = expand_normal (arg1); | |
9196 | rtx op2 = expand_normal (arg2); | |
9197 | rtx op3 = expand_normal (arg3); | |
a3170dc6 AH |
9198 | enum machine_mode mode0 = insn_data[icode].operand[1].mode; |
9199 | enum machine_mode mode1 = insn_data[icode].operand[2].mode; | |
9200 | ||
37409796 | 9201 | gcc_assert (mode0 == mode1); |
a3170dc6 AH |
9202 | |
9203 | if (arg0 == error_mark_node || arg1 == error_mark_node | |
9204 | || arg2 == error_mark_node || arg3 == error_mark_node) | |
9205 | return const0_rtx; | |
9206 | ||
9207 | if (target == 0 | |
9208 | || GET_MODE (target) != mode0 | |
9209 | || ! (*insn_data[icode].operand[0].predicate) (target, mode0)) | |
9210 | target = gen_reg_rtx (mode0); | |
9211 | ||
9212 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) | |
9213 | op0 = copy_to_mode_reg (mode0, op0); | |
9214 | if (! (*insn_data[icode].operand[1].predicate) (op1, mode1)) | |
9215 | op1 = copy_to_mode_reg (mode0, op1); | |
9216 | if (! (*insn_data[icode].operand[1].predicate) (op2, mode1)) | |
9217 | op2 = copy_to_mode_reg (mode0, op2); | |
9218 | if (! (*insn_data[icode].operand[1].predicate) (op3, mode1)) | |
9219 | op3 = copy_to_mode_reg (mode0, op3); | |
9220 | ||
9221 | /* Generate the compare. */ | |
9222 | scratch = gen_reg_rtx (CCmode); | |
9223 | pat = GEN_FCN (icode) (scratch, op0, op1); | |
9224 | if (! pat) | |
9225 | return const0_rtx; | |
9226 | emit_insn (pat); | |
9227 | ||
9228 | if (mode0 == V2SImode) | |
9229 | emit_insn (gen_spe_evsel (target, op2, op3, scratch)); | |
9230 | else | |
9231 | emit_insn (gen_spe_evsel_fs (target, op2, op3, scratch)); | |
9232 | ||
9233 | return target; | |
9234 | } | |
9235 | ||
0ac081f6 AH |
9236 | /* Expand an expression EXP that calls a built-in function, |
9237 | with result going to TARGET if that's convenient | |
9238 | (and in mode MODE if that's convenient). | |
9239 | SUBTARGET may be used as the target for computing one of EXP's operands. | |
9240 | IGNORE is nonzero if the value is to be ignored. */ | |
9241 | ||
9242 | static rtx | |
a2369ed3 | 9243 | rs6000_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED, |
c4ad648e AM |
9244 | enum machine_mode mode ATTRIBUTE_UNUSED, |
9245 | int ignore ATTRIBUTE_UNUSED) | |
0ac081f6 | 9246 | { |
5039610b | 9247 | tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0); |
92898235 | 9248 | unsigned int fcode = DECL_FUNCTION_CODE (fndecl); |
586de218 | 9249 | const struct builtin_description *d; |
92898235 AH |
9250 | size_t i; |
9251 | rtx ret; | |
9252 | bool success; | |
f676971a | 9253 | |
9c78b944 DE |
9254 | if (fcode == RS6000_BUILTIN_RECIP) |
9255 | return rs6000_expand_binop_builtin (CODE_FOR_recipdf3, exp, target); | |
9256 | ||
9257 | if (fcode == RS6000_BUILTIN_RECIPF) | |
9258 | return rs6000_expand_binop_builtin (CODE_FOR_recipsf3, exp, target); | |
9259 | ||
9260 | if (fcode == RS6000_BUILTIN_RSQRTF) | |
9261 | return rs6000_expand_unop_builtin (CODE_FOR_rsqrtsf2, exp, target); | |
9262 | ||
7ccf35ed DN |
9263 | if (fcode == ALTIVEC_BUILTIN_MASK_FOR_LOAD |
9264 | || fcode == ALTIVEC_BUILTIN_MASK_FOR_STORE) | |
9265 | { | |
9266 | int icode = (int) CODE_FOR_altivec_lvsr; | |
9267 | enum machine_mode tmode = insn_data[icode].operand[0].mode; | |
9268 | enum machine_mode mode = insn_data[icode].operand[1].mode; | |
9269 | tree arg; | |
9270 | rtx op, addr, pat; | |
9271 | ||
37409796 | 9272 | gcc_assert (TARGET_ALTIVEC); |
7ccf35ed | 9273 | |
5039610b | 9274 | arg = CALL_EXPR_ARG (exp, 0); |
37409796 | 9275 | gcc_assert (TREE_CODE (TREE_TYPE (arg)) == POINTER_TYPE); |
7ccf35ed DN |
9276 | op = expand_expr (arg, NULL_RTX, Pmode, EXPAND_NORMAL); |
9277 | addr = memory_address (mode, op); | |
9278 | if (fcode == ALTIVEC_BUILTIN_MASK_FOR_STORE) | |
9279 | op = addr; | |
9280 | else | |
9281 | { | |
9282 | /* For the load case need to negate the address. */ | |
9283 | op = gen_reg_rtx (GET_MODE (addr)); | |
9284 | emit_insn (gen_rtx_SET (VOIDmode, op, | |
9285 | gen_rtx_NEG (GET_MODE (addr), addr))); | |
c4ad648e | 9286 | } |
7ccf35ed DN |
9287 | op = gen_rtx_MEM (mode, op); |
9288 | ||
9289 | if (target == 0 | |
9290 | || GET_MODE (target) != tmode | |
9291 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
9292 | target = gen_reg_rtx (tmode); | |
9293 | ||
9294 | /*pat = gen_altivec_lvsr (target, op);*/ | |
9295 | pat = GEN_FCN (icode) (target, op); | |
9296 | if (!pat) | |
9297 | return 0; | |
9298 | emit_insn (pat); | |
9299 | ||
9300 | return target; | |
9301 | } | |
5039610b SL |
9302 | |
9303 | /* FIXME: There's got to be a nicer way to handle this case than | |
9304 | constructing a new CALL_EXPR. */ | |
f57d17f1 | 9305 | if (fcode == ALTIVEC_BUILTIN_VCFUX |
7910ae0c DN |
9306 | || fcode == ALTIVEC_BUILTIN_VCFSX |
9307 | || fcode == ALTIVEC_BUILTIN_VCTUXS | |
9308 | || fcode == ALTIVEC_BUILTIN_VCTSXS) | |
f57d17f1 | 9309 | { |
5039610b SL |
9310 | if (call_expr_nargs (exp) == 1) |
9311 | exp = build_call_nary (TREE_TYPE (exp), CALL_EXPR_FN (exp), | |
9312 | 2, CALL_EXPR_ARG (exp, 0), integer_zero_node); | |
982afe02 | 9313 | } |
7ccf35ed | 9314 | |
0ac081f6 | 9315 | if (TARGET_ALTIVEC) |
92898235 AH |
9316 | { |
9317 | ret = altivec_expand_builtin (exp, target, &success); | |
9318 | ||
a3170dc6 AH |
9319 | if (success) |
9320 | return ret; | |
9321 | } | |
9322 | if (TARGET_SPE) | |
9323 | { | |
9324 | ret = spe_expand_builtin (exp, target, &success); | |
9325 | ||
92898235 AH |
9326 | if (success) |
9327 | return ret; | |
9328 | } | |
96038623 DE |
9329 | if (TARGET_PAIRED_FLOAT) |
9330 | { | |
9331 | ret = paired_expand_builtin (exp, target, &success); | |
9332 | ||
9333 | if (success) | |
9334 | return ret; | |
9335 | } | |
92898235 | 9336 | |
96038623 | 9337 | gcc_assert (TARGET_ALTIVEC || TARGET_SPE || TARGET_PAIRED_FLOAT); |
bb8df8a6 | 9338 | |
37409796 NS |
9339 | /* Handle simple unary operations. */ |
9340 | d = (struct builtin_description *) bdesc_1arg; | |
9341 | for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++) | |
9342 | if (d->code == fcode) | |
5039610b | 9343 | return rs6000_expand_unop_builtin (d->icode, exp, target); |
bb8df8a6 | 9344 | |
37409796 NS |
9345 | /* Handle simple binary operations. */ |
9346 | d = (struct builtin_description *) bdesc_2arg; | |
9347 | for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++) | |
9348 | if (d->code == fcode) | |
5039610b | 9349 | return rs6000_expand_binop_builtin (d->icode, exp, target); |
0ac081f6 | 9350 | |
37409796 | 9351 | /* Handle simple ternary operations. */ |
586de218 | 9352 | d = bdesc_3arg; |
37409796 NS |
9353 | for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++) |
9354 | if (d->code == fcode) | |
5039610b | 9355 | return rs6000_expand_ternop_builtin (d->icode, exp, target); |
bb8df8a6 | 9356 | |
37409796 | 9357 | gcc_unreachable (); |
0ac081f6 AH |
9358 | } |
9359 | ||
9360 | static void | |
863d938c | 9361 | rs6000_init_builtins (void) |
0ac081f6 | 9362 | { |
5afaa917 NS |
9363 | tree tdecl; |
9364 | ||
4a5eab38 PB |
9365 | V2SI_type_node = build_vector_type (intSI_type_node, 2); |
9366 | V2SF_type_node = build_vector_type (float_type_node, 2); | |
9367 | V4HI_type_node = build_vector_type (intHI_type_node, 4); | |
9368 | V4SI_type_node = build_vector_type (intSI_type_node, 4); | |
9369 | V4SF_type_node = build_vector_type (float_type_node, 4); | |
7e463bda | 9370 | V8HI_type_node = build_vector_type (intHI_type_node, 8); |
4a5eab38 PB |
9371 | V16QI_type_node = build_vector_type (intQI_type_node, 16); |
9372 | ||
9373 | unsigned_V16QI_type_node = build_vector_type (unsigned_intQI_type_node, 16); | |
9374 | unsigned_V8HI_type_node = build_vector_type (unsigned_intHI_type_node, 8); | |
9375 | unsigned_V4SI_type_node = build_vector_type (unsigned_intSI_type_node, 4); | |
9376 | ||
7c62e993 PB |
9377 | opaque_V2SF_type_node = build_opaque_vector_type (float_type_node, 2); |
9378 | opaque_V2SI_type_node = build_opaque_vector_type (intSI_type_node, 2); | |
6035d635 | 9379 | opaque_p_V2SI_type_node = build_pointer_type (opaque_V2SI_type_node); |
b6fc2cdb | 9380 | opaque_V4SI_type_node = build_opaque_vector_type (intSI_type_node, 4); |
3fdaa45a | 9381 | |
8bb418a3 ZL |
9382 | /* The 'vector bool ...' types must be kept distinct from 'vector unsigned ...' |
9383 | types, especially in C++ land. Similarly, 'vector pixel' is distinct from | |
9384 | 'vector unsigned short'. */ | |
9385 | ||
8dd16ecc NS |
9386 | bool_char_type_node = build_distinct_type_copy (unsigned_intQI_type_node); |
9387 | bool_short_type_node = build_distinct_type_copy (unsigned_intHI_type_node); | |
9388 | bool_int_type_node = build_distinct_type_copy (unsigned_intSI_type_node); | |
9389 | pixel_type_node = build_distinct_type_copy (unsigned_intHI_type_node); | |
8bb418a3 | 9390 | |
58646b77 PB |
9391 | long_integer_type_internal_node = long_integer_type_node; |
9392 | long_unsigned_type_internal_node = long_unsigned_type_node; | |
9393 | intQI_type_internal_node = intQI_type_node; | |
9394 | uintQI_type_internal_node = unsigned_intQI_type_node; | |
9395 | intHI_type_internal_node = intHI_type_node; | |
9396 | uintHI_type_internal_node = unsigned_intHI_type_node; | |
9397 | intSI_type_internal_node = intSI_type_node; | |
9398 | uintSI_type_internal_node = unsigned_intSI_type_node; | |
9399 | float_type_internal_node = float_type_node; | |
9400 | void_type_internal_node = void_type_node; | |
9401 | ||
5afaa917 NS |
9402 | tdecl = build_decl (TYPE_DECL, get_identifier ("__bool char"), |
9403 | bool_char_type_node); | |
9404 | TYPE_NAME (bool_char_type_node) = tdecl; | |
9405 | (*lang_hooks.decls.pushdecl) (tdecl); | |
9406 | tdecl = build_decl (TYPE_DECL, get_identifier ("__bool short"), | |
9407 | bool_short_type_node); | |
9408 | TYPE_NAME (bool_short_type_node) = tdecl; | |
9409 | (*lang_hooks.decls.pushdecl) (tdecl); | |
9410 | tdecl = build_decl (TYPE_DECL, get_identifier ("__bool int"), | |
9411 | bool_int_type_node); | |
9412 | TYPE_NAME (bool_int_type_node) = tdecl; | |
9413 | (*lang_hooks.decls.pushdecl) (tdecl); | |
9414 | tdecl = build_decl (TYPE_DECL, get_identifier ("__pixel"), | |
9415 | pixel_type_node); | |
9416 | TYPE_NAME (pixel_type_node) = tdecl; | |
9417 | (*lang_hooks.decls.pushdecl) (tdecl); | |
8bb418a3 | 9418 | |
4a5eab38 PB |
9419 | bool_V16QI_type_node = build_vector_type (bool_char_type_node, 16); |
9420 | bool_V8HI_type_node = build_vector_type (bool_short_type_node, 8); | |
9421 | bool_V4SI_type_node = build_vector_type (bool_int_type_node, 4); | |
9422 | pixel_V8HI_type_node = build_vector_type (pixel_type_node, 8); | |
8bb418a3 | 9423 | |
5afaa917 NS |
9424 | tdecl = build_decl (TYPE_DECL, get_identifier ("__vector unsigned char"), |
9425 | unsigned_V16QI_type_node); | |
9426 | TYPE_NAME (unsigned_V16QI_type_node) = tdecl; | |
9427 | (*lang_hooks.decls.pushdecl) (tdecl); | |
9428 | tdecl = build_decl (TYPE_DECL, get_identifier ("__vector signed char"), | |
9429 | V16QI_type_node); | |
9430 | TYPE_NAME (V16QI_type_node) = tdecl; | |
9431 | (*lang_hooks.decls.pushdecl) (tdecl); | |
9432 | tdecl = build_decl (TYPE_DECL, get_identifier ("__vector __bool char"), | |
9433 | bool_V16QI_type_node); | |
9434 | TYPE_NAME ( bool_V16QI_type_node) = tdecl; | |
9435 | (*lang_hooks.decls.pushdecl) (tdecl); | |
9436 | ||
9437 | tdecl = build_decl (TYPE_DECL, get_identifier ("__vector unsigned short"), | |
9438 | unsigned_V8HI_type_node); | |
9439 | TYPE_NAME (unsigned_V8HI_type_node) = tdecl; | |
9440 | (*lang_hooks.decls.pushdecl) (tdecl); | |
9441 | tdecl = build_decl (TYPE_DECL, get_identifier ("__vector signed short"), | |
9442 | V8HI_type_node); | |
9443 | TYPE_NAME (V8HI_type_node) = tdecl; | |
9444 | (*lang_hooks.decls.pushdecl) (tdecl); | |
9445 | tdecl = build_decl (TYPE_DECL, get_identifier ("__vector __bool short"), | |
9446 | bool_V8HI_type_node); | |
9447 | TYPE_NAME (bool_V8HI_type_node) = tdecl; | |
9448 | (*lang_hooks.decls.pushdecl) (tdecl); | |
9449 | ||
9450 | tdecl = build_decl (TYPE_DECL, get_identifier ("__vector unsigned int"), | |
9451 | unsigned_V4SI_type_node); | |
9452 | TYPE_NAME (unsigned_V4SI_type_node) = tdecl; | |
9453 | (*lang_hooks.decls.pushdecl) (tdecl); | |
9454 | tdecl = build_decl (TYPE_DECL, get_identifier ("__vector signed int"), | |
9455 | V4SI_type_node); | |
9456 | TYPE_NAME (V4SI_type_node) = tdecl; | |
9457 | (*lang_hooks.decls.pushdecl) (tdecl); | |
9458 | tdecl = build_decl (TYPE_DECL, get_identifier ("__vector __bool int"), | |
9459 | bool_V4SI_type_node); | |
9460 | TYPE_NAME (bool_V4SI_type_node) = tdecl; | |
9461 | (*lang_hooks.decls.pushdecl) (tdecl); | |
9462 | ||
9463 | tdecl = build_decl (TYPE_DECL, get_identifier ("__vector float"), | |
9464 | V4SF_type_node); | |
9465 | TYPE_NAME (V4SF_type_node) = tdecl; | |
9466 | (*lang_hooks.decls.pushdecl) (tdecl); | |
9467 | tdecl = build_decl (TYPE_DECL, get_identifier ("__vector __pixel"), | |
9468 | pixel_V8HI_type_node); | |
9469 | TYPE_NAME (pixel_V8HI_type_node) = tdecl; | |
9470 | (*lang_hooks.decls.pushdecl) (tdecl); | |
8bb418a3 | 9471 | |
96038623 DE |
9472 | if (TARGET_PAIRED_FLOAT) |
9473 | paired_init_builtins (); | |
a3170dc6 | 9474 | if (TARGET_SPE) |
3fdaa45a | 9475 | spe_init_builtins (); |
0ac081f6 AH |
9476 | if (TARGET_ALTIVEC) |
9477 | altivec_init_builtins (); | |
96038623 | 9478 | if (TARGET_ALTIVEC || TARGET_SPE || TARGET_PAIRED_FLOAT) |
0559cc77 | 9479 | rs6000_common_init_builtins (); |
9c78b944 DE |
9480 | if (TARGET_PPC_GFXOPT) |
9481 | { | |
9482 | tree ftype = build_function_type_list (float_type_node, | |
9483 | float_type_node, | |
9484 | float_type_node, | |
9485 | NULL_TREE); | |
9486 | def_builtin (MASK_PPC_GFXOPT, "__builtin_recipdivf", ftype, | |
9487 | RS6000_BUILTIN_RECIPF); | |
9488 | ||
9489 | ftype = build_function_type_list (float_type_node, | |
9490 | float_type_node, | |
9491 | NULL_TREE); | |
9492 | def_builtin (MASK_PPC_GFXOPT, "__builtin_rsqrtf", ftype, | |
9493 | RS6000_BUILTIN_RSQRTF); | |
9494 | } | |
9495 | if (TARGET_POPCNTB) | |
9496 | { | |
9497 | tree ftype = build_function_type_list (double_type_node, | |
9498 | double_type_node, | |
9499 | double_type_node, | |
9500 | NULL_TREE); | |
9501 | def_builtin (MASK_POPCNTB, "__builtin_recipdiv", ftype, | |
9502 | RS6000_BUILTIN_RECIP); | |
9503 | ||
9504 | } | |
69ca3549 DE |
9505 | |
9506 | #if TARGET_XCOFF | |
9507 | /* AIX libm provides clog as __clog. */ | |
9508 | if (built_in_decls [BUILT_IN_CLOG]) | |
9509 | set_user_assembler_name (built_in_decls [BUILT_IN_CLOG], "__clog"); | |
9510 | #endif | |
fb220235 FXC |
9511 | |
9512 | #ifdef SUBTARGET_INIT_BUILTINS | |
9513 | SUBTARGET_INIT_BUILTINS; | |
9514 | #endif | |
0ac081f6 AH |
9515 | } |
9516 | ||
a3170dc6 AH |
9517 | /* Search through a set of builtins and enable the mask bits. |
9518 | DESC is an array of builtins. | |
b6d08ca1 | 9519 | SIZE is the total number of builtins. |
a3170dc6 AH |
9520 | START is the builtin enum at which to start. |
9521 | END is the builtin enum at which to end. */ | |
0ac081f6 | 9522 | static void |
a2369ed3 | 9523 | enable_mask_for_builtins (struct builtin_description *desc, int size, |
f676971a | 9524 | enum rs6000_builtins start, |
a2369ed3 | 9525 | enum rs6000_builtins end) |
a3170dc6 AH |
9526 | { |
9527 | int i; | |
9528 | ||
9529 | for (i = 0; i < size; ++i) | |
9530 | if (desc[i].code == start) | |
9531 | break; | |
9532 | ||
9533 | if (i == size) | |
9534 | return; | |
9535 | ||
9536 | for (; i < size; ++i) | |
9537 | { | |
9538 | /* Flip all the bits on. */ | |
9539 | desc[i].mask = target_flags; | |
9540 | if (desc[i].code == end) | |
9541 | break; | |
9542 | } | |
9543 | } | |
9544 | ||
9545 | static void | |
863d938c | 9546 | spe_init_builtins (void) |
0ac081f6 | 9547 | { |
a3170dc6 AH |
9548 | tree endlink = void_list_node; |
9549 | tree puint_type_node = build_pointer_type (unsigned_type_node); | |
9550 | tree pushort_type_node = build_pointer_type (short_unsigned_type_node); | |
ae4b4a02 | 9551 | struct builtin_description *d; |
0ac081f6 AH |
9552 | size_t i; |
9553 | ||
a3170dc6 AH |
9554 | tree v2si_ftype_4_v2si |
9555 | = build_function_type | |
3fdaa45a AH |
9556 | (opaque_V2SI_type_node, |
9557 | tree_cons (NULL_TREE, opaque_V2SI_type_node, | |
9558 | tree_cons (NULL_TREE, opaque_V2SI_type_node, | |
9559 | tree_cons (NULL_TREE, opaque_V2SI_type_node, | |
9560 | tree_cons (NULL_TREE, opaque_V2SI_type_node, | |
a3170dc6 AH |
9561 | endlink))))); |
9562 | ||
9563 | tree v2sf_ftype_4_v2sf | |
9564 | = build_function_type | |
3fdaa45a AH |
9565 | (opaque_V2SF_type_node, |
9566 | tree_cons (NULL_TREE, opaque_V2SF_type_node, | |
9567 | tree_cons (NULL_TREE, opaque_V2SF_type_node, | |
9568 | tree_cons (NULL_TREE, opaque_V2SF_type_node, | |
9569 | tree_cons (NULL_TREE, opaque_V2SF_type_node, | |
a3170dc6 AH |
9570 | endlink))))); |
9571 | ||
9572 | tree int_ftype_int_v2si_v2si | |
9573 | = build_function_type | |
9574 | (integer_type_node, | |
9575 | tree_cons (NULL_TREE, integer_type_node, | |
3fdaa45a AH |
9576 | tree_cons (NULL_TREE, opaque_V2SI_type_node, |
9577 | tree_cons (NULL_TREE, opaque_V2SI_type_node, | |
a3170dc6 AH |
9578 | endlink)))); |
9579 | ||
9580 | tree int_ftype_int_v2sf_v2sf | |
9581 | = build_function_type | |
9582 | (integer_type_node, | |
9583 | tree_cons (NULL_TREE, integer_type_node, | |
3fdaa45a AH |
9584 | tree_cons (NULL_TREE, opaque_V2SF_type_node, |
9585 | tree_cons (NULL_TREE, opaque_V2SF_type_node, | |
a3170dc6 AH |
9586 | endlink)))); |
9587 | ||
9588 | tree void_ftype_v2si_puint_int | |
9589 | = build_function_type (void_type_node, | |
3fdaa45a | 9590 | tree_cons (NULL_TREE, opaque_V2SI_type_node, |
a3170dc6 AH |
9591 | tree_cons (NULL_TREE, puint_type_node, |
9592 | tree_cons (NULL_TREE, | |
9593 | integer_type_node, | |
9594 | endlink)))); | |
9595 | ||
9596 | tree void_ftype_v2si_puint_char | |
9597 | = build_function_type (void_type_node, | |
3fdaa45a | 9598 | tree_cons (NULL_TREE, opaque_V2SI_type_node, |
a3170dc6 AH |
9599 | tree_cons (NULL_TREE, puint_type_node, |
9600 | tree_cons (NULL_TREE, | |
9601 | char_type_node, | |
9602 | endlink)))); | |
9603 | ||
9604 | tree void_ftype_v2si_pv2si_int | |
9605 | = build_function_type (void_type_node, | |
3fdaa45a | 9606 | tree_cons (NULL_TREE, opaque_V2SI_type_node, |
6035d635 | 9607 | tree_cons (NULL_TREE, opaque_p_V2SI_type_node, |
a3170dc6 AH |
9608 | tree_cons (NULL_TREE, |
9609 | integer_type_node, | |
9610 | endlink)))); | |
9611 | ||
9612 | tree void_ftype_v2si_pv2si_char | |
9613 | = build_function_type (void_type_node, | |
3fdaa45a | 9614 | tree_cons (NULL_TREE, opaque_V2SI_type_node, |
6035d635 | 9615 | tree_cons (NULL_TREE, opaque_p_V2SI_type_node, |
a3170dc6 AH |
9616 | tree_cons (NULL_TREE, |
9617 | char_type_node, | |
9618 | endlink)))); | |
9619 | ||
9620 | tree void_ftype_int | |
9621 | = build_function_type (void_type_node, | |
9622 | tree_cons (NULL_TREE, integer_type_node, endlink)); | |
9623 | ||
9624 | tree int_ftype_void | |
36e8d515 | 9625 | = build_function_type (integer_type_node, endlink); |
a3170dc6 AH |
9626 | |
9627 | tree v2si_ftype_pv2si_int | |
3fdaa45a | 9628 | = build_function_type (opaque_V2SI_type_node, |
6035d635 | 9629 | tree_cons (NULL_TREE, opaque_p_V2SI_type_node, |
a3170dc6 AH |
9630 | tree_cons (NULL_TREE, integer_type_node, |
9631 | endlink))); | |
9632 | ||
9633 | tree v2si_ftype_puint_int | |
3fdaa45a | 9634 | = build_function_type (opaque_V2SI_type_node, |
a3170dc6 AH |
9635 | tree_cons (NULL_TREE, puint_type_node, |
9636 | tree_cons (NULL_TREE, integer_type_node, | |
9637 | endlink))); | |
9638 | ||
9639 | tree v2si_ftype_pushort_int | |
3fdaa45a | 9640 | = build_function_type (opaque_V2SI_type_node, |
a3170dc6 AH |
9641 | tree_cons (NULL_TREE, pushort_type_node, |
9642 | tree_cons (NULL_TREE, integer_type_node, | |
9643 | endlink))); | |
9644 | ||
00332c9f AH |
9645 | tree v2si_ftype_signed_char |
9646 | = build_function_type (opaque_V2SI_type_node, | |
9647 | tree_cons (NULL_TREE, signed_char_type_node, | |
9648 | endlink)); | |
9649 | ||
a3170dc6 AH |
9650 | /* The initialization of the simple binary and unary builtins is |
9651 | done in rs6000_common_init_builtins, but we have to enable the | |
9652 | mask bits here manually because we have run out of `target_flags' | |
9653 | bits. We really need to redesign this mask business. */ | |
9654 | ||
9655 | enable_mask_for_builtins ((struct builtin_description *) bdesc_2arg, | |
9656 | ARRAY_SIZE (bdesc_2arg), | |
9657 | SPE_BUILTIN_EVADDW, | |
9658 | SPE_BUILTIN_EVXOR); | |
9659 | enable_mask_for_builtins ((struct builtin_description *) bdesc_1arg, | |
9660 | ARRAY_SIZE (bdesc_1arg), | |
9661 | SPE_BUILTIN_EVABS, | |
9662 | SPE_BUILTIN_EVSUBFUSIAAW); | |
9663 | enable_mask_for_builtins ((struct builtin_description *) bdesc_spe_predicates, | |
9664 | ARRAY_SIZE (bdesc_spe_predicates), | |
9665 | SPE_BUILTIN_EVCMPEQ, | |
9666 | SPE_BUILTIN_EVFSTSTLT); | |
9667 | enable_mask_for_builtins ((struct builtin_description *) bdesc_spe_evsel, | |
9668 | ARRAY_SIZE (bdesc_spe_evsel), | |
9669 | SPE_BUILTIN_EVSEL_CMPGTS, | |
9670 | SPE_BUILTIN_EVSEL_FSTSTEQ); | |
9671 | ||
36252949 AH |
9672 | (*lang_hooks.decls.pushdecl) |
9673 | (build_decl (TYPE_DECL, get_identifier ("__ev64_opaque__"), | |
9674 | opaque_V2SI_type_node)); | |
9675 | ||
a3170dc6 | 9676 | /* Initialize irregular SPE builtins. */ |
f676971a | 9677 | |
a3170dc6 AH |
9678 | def_builtin (target_flags, "__builtin_spe_mtspefscr", void_ftype_int, SPE_BUILTIN_MTSPEFSCR); |
9679 | def_builtin (target_flags, "__builtin_spe_mfspefscr", int_ftype_void, SPE_BUILTIN_MFSPEFSCR); | |
9680 | def_builtin (target_flags, "__builtin_spe_evstddx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDDX); | |
9681 | def_builtin (target_flags, "__builtin_spe_evstdhx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDHX); | |
9682 | def_builtin (target_flags, "__builtin_spe_evstdwx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDWX); | |
9683 | def_builtin (target_flags, "__builtin_spe_evstwhex", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWHEX); | |
9684 | def_builtin (target_flags, "__builtin_spe_evstwhox", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWHOX); | |
9685 | def_builtin (target_flags, "__builtin_spe_evstwwex", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWWEX); | |
9686 | def_builtin (target_flags, "__builtin_spe_evstwwox", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWWOX); | |
9687 | def_builtin (target_flags, "__builtin_spe_evstdd", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDD); | |
9688 | def_builtin (target_flags, "__builtin_spe_evstdh", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDH); | |
9689 | def_builtin (target_flags, "__builtin_spe_evstdw", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDW); | |
9690 | def_builtin (target_flags, "__builtin_spe_evstwhe", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWHE); | |
9691 | def_builtin (target_flags, "__builtin_spe_evstwho", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWHO); | |
9692 | def_builtin (target_flags, "__builtin_spe_evstwwe", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWWE); | |
9693 | def_builtin (target_flags, "__builtin_spe_evstwwo", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWWO); | |
00332c9f AH |
9694 | def_builtin (target_flags, "__builtin_spe_evsplatfi", v2si_ftype_signed_char, SPE_BUILTIN_EVSPLATFI); |
9695 | def_builtin (target_flags, "__builtin_spe_evsplati", v2si_ftype_signed_char, SPE_BUILTIN_EVSPLATI); | |
a3170dc6 AH |
9696 | |
9697 | /* Loads. */ | |
9698 | def_builtin (target_flags, "__builtin_spe_evlddx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDDX); | |
9699 | def_builtin (target_flags, "__builtin_spe_evldwx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDWX); | |
9700 | def_builtin (target_flags, "__builtin_spe_evldhx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDHX); | |
9701 | def_builtin (target_flags, "__builtin_spe_evlwhex", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHEX); | |
9702 | def_builtin (target_flags, "__builtin_spe_evlwhoux", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOUX); | |
9703 | def_builtin (target_flags, "__builtin_spe_evlwhosx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOSX); | |
9704 | def_builtin (target_flags, "__builtin_spe_evlwwsplatx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWWSPLATX); | |
9705 | def_builtin (target_flags, "__builtin_spe_evlwhsplatx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHSPLATX); | |
9706 | def_builtin (target_flags, "__builtin_spe_evlhhesplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHESPLATX); | |
9707 | def_builtin (target_flags, "__builtin_spe_evlhhousplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOUSPLATX); | |
9708 | def_builtin (target_flags, "__builtin_spe_evlhhossplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOSSPLATX); | |
9709 | def_builtin (target_flags, "__builtin_spe_evldd", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDD); | |
9710 | def_builtin (target_flags, "__builtin_spe_evldw", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDW); | |
9711 | def_builtin (target_flags, "__builtin_spe_evldh", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDH); | |
9712 | def_builtin (target_flags, "__builtin_spe_evlhhesplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHESPLAT); | |
9713 | def_builtin (target_flags, "__builtin_spe_evlhhossplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOSSPLAT); | |
9714 | def_builtin (target_flags, "__builtin_spe_evlhhousplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOUSPLAT); | |
9715 | def_builtin (target_flags, "__builtin_spe_evlwhe", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHE); | |
9716 | def_builtin (target_flags, "__builtin_spe_evlwhos", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOS); | |
9717 | def_builtin (target_flags, "__builtin_spe_evlwhou", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOU); | |
9718 | def_builtin (target_flags, "__builtin_spe_evlwhsplat", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHSPLAT); | |
9719 | def_builtin (target_flags, "__builtin_spe_evlwwsplat", v2si_ftype_puint_int, SPE_BUILTIN_EVLWWSPLAT); | |
9720 | ||
9721 | /* Predicates. */ | |
9722 | d = (struct builtin_description *) bdesc_spe_predicates; | |
9723 | for (i = 0; i < ARRAY_SIZE (bdesc_spe_predicates); ++i, d++) | |
9724 | { | |
9725 | tree type; | |
9726 | ||
9727 | switch (insn_data[d->icode].operand[1].mode) | |
9728 | { | |
9729 | case V2SImode: | |
9730 | type = int_ftype_int_v2si_v2si; | |
9731 | break; | |
9732 | case V2SFmode: | |
9733 | type = int_ftype_int_v2sf_v2sf; | |
9734 | break; | |
9735 | default: | |
37409796 | 9736 | gcc_unreachable (); |
a3170dc6 AH |
9737 | } |
9738 | ||
9739 | def_builtin (d->mask, d->name, type, d->code); | |
9740 | } | |
9741 | ||
9742 | /* Evsel predicates. */ | |
9743 | d = (struct builtin_description *) bdesc_spe_evsel; | |
9744 | for (i = 0; i < ARRAY_SIZE (bdesc_spe_evsel); ++i, d++) | |
9745 | { | |
9746 | tree type; | |
9747 | ||
9748 | switch (insn_data[d->icode].operand[1].mode) | |
9749 | { | |
9750 | case V2SImode: | |
9751 | type = v2si_ftype_4_v2si; | |
9752 | break; | |
9753 | case V2SFmode: | |
9754 | type = v2sf_ftype_4_v2sf; | |
9755 | break; | |
9756 | default: | |
37409796 | 9757 | gcc_unreachable (); |
a3170dc6 AH |
9758 | } |
9759 | ||
9760 | def_builtin (d->mask, d->name, type, d->code); | |
9761 | } | |
9762 | } | |
9763 | ||
96038623 DE |
9764 | static void |
9765 | paired_init_builtins (void) | |
9766 | { | |
23a651fc | 9767 | const struct builtin_description *d; |
96038623 DE |
9768 | size_t i; |
9769 | tree endlink = void_list_node; | |
9770 | ||
9771 | tree int_ftype_int_v2sf_v2sf | |
9772 | = build_function_type | |
9773 | (integer_type_node, | |
9774 | tree_cons (NULL_TREE, integer_type_node, | |
9775 | tree_cons (NULL_TREE, V2SF_type_node, | |
9776 | tree_cons (NULL_TREE, V2SF_type_node, | |
9777 | endlink)))); | |
9778 | tree pcfloat_type_node = | |
9779 | build_pointer_type (build_qualified_type | |
9780 | (float_type_node, TYPE_QUAL_CONST)); | |
9781 | ||
9782 | tree v2sf_ftype_long_pcfloat = build_function_type_list (V2SF_type_node, | |
9783 | long_integer_type_node, | |
9784 | pcfloat_type_node, | |
9785 | NULL_TREE); | |
9786 | tree void_ftype_v2sf_long_pcfloat = | |
9787 | build_function_type_list (void_type_node, | |
9788 | V2SF_type_node, | |
9789 | long_integer_type_node, | |
9790 | pcfloat_type_node, | |
9791 | NULL_TREE); | |
9792 | ||
9793 | ||
9794 | def_builtin (0, "__builtin_paired_lx", v2sf_ftype_long_pcfloat, | |
9795 | PAIRED_BUILTIN_LX); | |
9796 | ||
9797 | ||
9798 | def_builtin (0, "__builtin_paired_stx", void_ftype_v2sf_long_pcfloat, | |
9799 | PAIRED_BUILTIN_STX); | |
9800 | ||
9801 | /* Predicates. */ | |
23a651fc | 9802 | d = bdesc_paired_preds; |
96038623 DE |
9803 | for (i = 0; i < ARRAY_SIZE (bdesc_paired_preds); ++i, d++) |
9804 | { | |
9805 | tree type; | |
9806 | ||
9807 | switch (insn_data[d->icode].operand[1].mode) | |
9808 | { | |
9809 | case V2SFmode: | |
9810 | type = int_ftype_int_v2sf_v2sf; | |
9811 | break; | |
9812 | default: | |
9813 | gcc_unreachable (); | |
9814 | } | |
9815 | ||
9816 | def_builtin (d->mask, d->name, type, d->code); | |
9817 | } | |
9818 | } | |
9819 | ||
a3170dc6 | 9820 | static void |
863d938c | 9821 | altivec_init_builtins (void) |
a3170dc6 | 9822 | { |
586de218 KG |
9823 | const struct builtin_description *d; |
9824 | const struct builtin_description_predicates *dp; | |
a3170dc6 | 9825 | size_t i; |
7a4eca66 DE |
9826 | tree ftype; |
9827 | ||
a3170dc6 AH |
9828 | tree pfloat_type_node = build_pointer_type (float_type_node); |
9829 | tree pint_type_node = build_pointer_type (integer_type_node); | |
9830 | tree pshort_type_node = build_pointer_type (short_integer_type_node); | |
9831 | tree pchar_type_node = build_pointer_type (char_type_node); | |
9832 | ||
9833 | tree pvoid_type_node = build_pointer_type (void_type_node); | |
9834 | ||
0dbc3651 ZW |
9835 | tree pcfloat_type_node = build_pointer_type (build_qualified_type (float_type_node, TYPE_QUAL_CONST)); |
9836 | tree pcint_type_node = build_pointer_type (build_qualified_type (integer_type_node, TYPE_QUAL_CONST)); | |
9837 | tree pcshort_type_node = build_pointer_type (build_qualified_type (short_integer_type_node, TYPE_QUAL_CONST)); | |
9838 | tree pcchar_type_node = build_pointer_type (build_qualified_type (char_type_node, TYPE_QUAL_CONST)); | |
9839 | ||
9840 | tree pcvoid_type_node = build_pointer_type (build_qualified_type (void_type_node, TYPE_QUAL_CONST)); | |
9841 | ||
58646b77 PB |
9842 | tree int_ftype_opaque |
9843 | = build_function_type_list (integer_type_node, | |
9844 | opaque_V4SI_type_node, NULL_TREE); | |
266b4890 AP |
9845 | tree opaque_ftype_opaque |
9846 | = build_function_type (integer_type_node, | |
9847 | NULL_TREE); | |
58646b77 PB |
9848 | tree opaque_ftype_opaque_int |
9849 | = build_function_type_list (opaque_V4SI_type_node, | |
9850 | opaque_V4SI_type_node, integer_type_node, NULL_TREE); | |
9851 | tree opaque_ftype_opaque_opaque_int | |
9852 | = build_function_type_list (opaque_V4SI_type_node, | |
9853 | opaque_V4SI_type_node, opaque_V4SI_type_node, | |
9854 | integer_type_node, NULL_TREE); | |
9855 | tree int_ftype_int_opaque_opaque | |
9856 | = build_function_type_list (integer_type_node, | |
9857 | integer_type_node, opaque_V4SI_type_node, | |
9858 | opaque_V4SI_type_node, NULL_TREE); | |
a3170dc6 AH |
9859 | tree int_ftype_int_v4si_v4si |
9860 | = build_function_type_list (integer_type_node, | |
9861 | integer_type_node, V4SI_type_node, | |
9862 | V4SI_type_node, NULL_TREE); | |
0dbc3651 ZW |
9863 | tree v4sf_ftype_pcfloat |
9864 | = build_function_type_list (V4SF_type_node, pcfloat_type_node, NULL_TREE); | |
a3170dc6 | 9865 | tree void_ftype_pfloat_v4sf |
b4de2f7d | 9866 | = build_function_type_list (void_type_node, |
a3170dc6 | 9867 | pfloat_type_node, V4SF_type_node, NULL_TREE); |
0dbc3651 ZW |
9868 | tree v4si_ftype_pcint |
9869 | = build_function_type_list (V4SI_type_node, pcint_type_node, NULL_TREE); | |
9870 | tree void_ftype_pint_v4si | |
b4de2f7d AH |
9871 | = build_function_type_list (void_type_node, |
9872 | pint_type_node, V4SI_type_node, NULL_TREE); | |
0dbc3651 ZW |
9873 | tree v8hi_ftype_pcshort |
9874 | = build_function_type_list (V8HI_type_node, pcshort_type_node, NULL_TREE); | |
f18c054f | 9875 | tree void_ftype_pshort_v8hi |
b4de2f7d AH |
9876 | = build_function_type_list (void_type_node, |
9877 | pshort_type_node, V8HI_type_node, NULL_TREE); | |
0dbc3651 ZW |
9878 | tree v16qi_ftype_pcchar |
9879 | = build_function_type_list (V16QI_type_node, pcchar_type_node, NULL_TREE); | |
f18c054f | 9880 | tree void_ftype_pchar_v16qi |
b4de2f7d AH |
9881 | = build_function_type_list (void_type_node, |
9882 | pchar_type_node, V16QI_type_node, NULL_TREE); | |
95385cbb | 9883 | tree void_ftype_v4si |
b4de2f7d | 9884 | = build_function_type_list (void_type_node, V4SI_type_node, NULL_TREE); |
a3170dc6 AH |
9885 | tree v8hi_ftype_void |
9886 | = build_function_type (V8HI_type_node, void_list_node); | |
9887 | tree void_ftype_void | |
9888 | = build_function_type (void_type_node, void_list_node); | |
e34b6648 JJ |
9889 | tree void_ftype_int |
9890 | = build_function_type_list (void_type_node, integer_type_node, NULL_TREE); | |
0dbc3651 | 9891 | |
58646b77 PB |
9892 | tree opaque_ftype_long_pcvoid |
9893 | = build_function_type_list (opaque_V4SI_type_node, | |
9894 | long_integer_type_node, pcvoid_type_node, NULL_TREE); | |
b4a62fa0 | 9895 | tree v16qi_ftype_long_pcvoid |
a3170dc6 | 9896 | = build_function_type_list (V16QI_type_node, |
b4a62fa0 SB |
9897 | long_integer_type_node, pcvoid_type_node, NULL_TREE); |
9898 | tree v8hi_ftype_long_pcvoid | |
a3170dc6 | 9899 | = build_function_type_list (V8HI_type_node, |
b4a62fa0 SB |
9900 | long_integer_type_node, pcvoid_type_node, NULL_TREE); |
9901 | tree v4si_ftype_long_pcvoid | |
a3170dc6 | 9902 | = build_function_type_list (V4SI_type_node, |
b4a62fa0 | 9903 | long_integer_type_node, pcvoid_type_node, NULL_TREE); |
0dbc3651 | 9904 | |
58646b77 PB |
9905 | tree void_ftype_opaque_long_pvoid |
9906 | = build_function_type_list (void_type_node, | |
9907 | opaque_V4SI_type_node, long_integer_type_node, | |
9908 | pvoid_type_node, NULL_TREE); | |
b4a62fa0 | 9909 | tree void_ftype_v4si_long_pvoid |
b4de2f7d | 9910 | = build_function_type_list (void_type_node, |
b4a62fa0 | 9911 | V4SI_type_node, long_integer_type_node, |
b4de2f7d | 9912 | pvoid_type_node, NULL_TREE); |
b4a62fa0 | 9913 | tree void_ftype_v16qi_long_pvoid |
b4de2f7d | 9914 | = build_function_type_list (void_type_node, |
b4a62fa0 | 9915 | V16QI_type_node, long_integer_type_node, |
b4de2f7d | 9916 | pvoid_type_node, NULL_TREE); |
b4a62fa0 | 9917 | tree void_ftype_v8hi_long_pvoid |
b4de2f7d | 9918 | = build_function_type_list (void_type_node, |
b4a62fa0 | 9919 | V8HI_type_node, long_integer_type_node, |
b4de2f7d | 9920 | pvoid_type_node, NULL_TREE); |
a3170dc6 AH |
9921 | tree int_ftype_int_v8hi_v8hi |
9922 | = build_function_type_list (integer_type_node, | |
9923 | integer_type_node, V8HI_type_node, | |
9924 | V8HI_type_node, NULL_TREE); | |
9925 | tree int_ftype_int_v16qi_v16qi | |
9926 | = build_function_type_list (integer_type_node, | |
9927 | integer_type_node, V16QI_type_node, | |
9928 | V16QI_type_node, NULL_TREE); | |
9929 | tree int_ftype_int_v4sf_v4sf | |
9930 | = build_function_type_list (integer_type_node, | |
9931 | integer_type_node, V4SF_type_node, | |
9932 | V4SF_type_node, NULL_TREE); | |
9933 | tree v4si_ftype_v4si | |
9934 | = build_function_type_list (V4SI_type_node, V4SI_type_node, NULL_TREE); | |
9935 | tree v8hi_ftype_v8hi | |
9936 | = build_function_type_list (V8HI_type_node, V8HI_type_node, NULL_TREE); | |
9937 | tree v16qi_ftype_v16qi | |
9938 | = build_function_type_list (V16QI_type_node, V16QI_type_node, NULL_TREE); | |
9939 | tree v4sf_ftype_v4sf | |
9940 | = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE); | |
8bb418a3 | 9941 | tree void_ftype_pcvoid_int_int |
a3170dc6 | 9942 | = build_function_type_list (void_type_node, |
0dbc3651 | 9943 | pcvoid_type_node, integer_type_node, |
8bb418a3 | 9944 | integer_type_node, NULL_TREE); |
8bb418a3 | 9945 | |
0dbc3651 ZW |
9946 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_4sf", v4sf_ftype_pcfloat, |
9947 | ALTIVEC_BUILTIN_LD_INTERNAL_4sf); | |
9948 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_4sf", void_ftype_pfloat_v4sf, | |
9949 | ALTIVEC_BUILTIN_ST_INTERNAL_4sf); | |
9950 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_4si", v4si_ftype_pcint, | |
9951 | ALTIVEC_BUILTIN_LD_INTERNAL_4si); | |
9952 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_4si", void_ftype_pint_v4si, | |
9953 | ALTIVEC_BUILTIN_ST_INTERNAL_4si); | |
9954 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_8hi", v8hi_ftype_pcshort, | |
9955 | ALTIVEC_BUILTIN_LD_INTERNAL_8hi); | |
9956 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_8hi", void_ftype_pshort_v8hi, | |
9957 | ALTIVEC_BUILTIN_ST_INTERNAL_8hi); | |
9958 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_16qi", v16qi_ftype_pcchar, | |
9959 | ALTIVEC_BUILTIN_LD_INTERNAL_16qi); | |
9960 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_16qi", void_ftype_pchar_v16qi, | |
9961 | ALTIVEC_BUILTIN_ST_INTERNAL_16qi); | |
a3170dc6 AH |
9962 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_mtvscr", void_ftype_v4si, ALTIVEC_BUILTIN_MTVSCR); |
9963 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_mfvscr", v8hi_ftype_void, ALTIVEC_BUILTIN_MFVSCR); | |
9964 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_dssall", void_ftype_void, ALTIVEC_BUILTIN_DSSALL); | |
e34b6648 | 9965 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_dss", void_ftype_int, ALTIVEC_BUILTIN_DSS); |
b4a62fa0 SB |
9966 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvsl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSL); |
9967 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvsr", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSR); | |
9968 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvebx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEBX); | |
9969 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvehx", v8hi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEHX); | |
9970 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvewx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEWX); | |
9971 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvxl", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVXL); | |
9972 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVX); | |
9973 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVX); | |
9974 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvewx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVEWX); | |
9975 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvxl", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVXL); | |
9976 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvebx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVEBX); | |
9977 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvehx", void_ftype_v8hi_long_pvoid, ALTIVEC_BUILTIN_STVEHX); | |
58646b77 PB |
9978 | def_builtin (MASK_ALTIVEC, "__builtin_vec_ld", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LD); |
9979 | def_builtin (MASK_ALTIVEC, "__builtin_vec_lde", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LDE); | |
9980 | def_builtin (MASK_ALTIVEC, "__builtin_vec_ldl", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LDL); | |
9981 | def_builtin (MASK_ALTIVEC, "__builtin_vec_lvsl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVSL); | |
9982 | def_builtin (MASK_ALTIVEC, "__builtin_vec_lvsr", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVSR); | |
9983 | def_builtin (MASK_ALTIVEC, "__builtin_vec_lvebx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEBX); | |
9984 | def_builtin (MASK_ALTIVEC, "__builtin_vec_lvehx", v8hi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEHX); | |
9985 | def_builtin (MASK_ALTIVEC, "__builtin_vec_lvewx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEWX); | |
9986 | def_builtin (MASK_ALTIVEC, "__builtin_vec_st", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_ST); | |
9987 | def_builtin (MASK_ALTIVEC, "__builtin_vec_ste", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STE); | |
9988 | def_builtin (MASK_ALTIVEC, "__builtin_vec_stl", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STL); | |
9989 | def_builtin (MASK_ALTIVEC, "__builtin_vec_stvewx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEWX); | |
9990 | def_builtin (MASK_ALTIVEC, "__builtin_vec_stvebx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEBX); | |
9991 | def_builtin (MASK_ALTIVEC, "__builtin_vec_stvehx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEHX); | |
9992 | ||
0b61703c AP |
9993 | if (rs6000_cpu == PROCESSOR_CELL) |
9994 | { | |
9995 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvlx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVLX); | |
9996 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvlxl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVLXL); | |
9997 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvrx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVRX); | |
9998 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvrxl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVRXL); | |
9999 | ||
10000 | def_builtin (MASK_ALTIVEC, "__builtin_vec_lvlx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVLX); | |
10001 | def_builtin (MASK_ALTIVEC, "__builtin_vec_lvlxl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVLXL); | |
10002 | def_builtin (MASK_ALTIVEC, "__builtin_vec_lvrx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVRX); | |
10003 | def_builtin (MASK_ALTIVEC, "__builtin_vec_lvrxl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVRXL); | |
10004 | ||
10005 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvlx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVLX); | |
10006 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvlxl", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVLXL); | |
10007 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvrx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVRX); | |
10008 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvrxl", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVRXL); | |
10009 | ||
10010 | def_builtin (MASK_ALTIVEC, "__builtin_vec_stvlx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_VEC_STVLX); | |
10011 | def_builtin (MASK_ALTIVEC, "__builtin_vec_stvlxl", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_VEC_STVLXL); | |
10012 | def_builtin (MASK_ALTIVEC, "__builtin_vec_stvrx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_VEC_STVRX); | |
10013 | def_builtin (MASK_ALTIVEC, "__builtin_vec_stvrxl", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_VEC_STVRXL); | |
10014 | } | |
58646b77 | 10015 | def_builtin (MASK_ALTIVEC, "__builtin_vec_step", int_ftype_opaque, ALTIVEC_BUILTIN_VEC_STEP); |
266b4890 AP |
10016 | def_builtin (MASK_ALTIVEC, "__builtin_vec_splats", opaque_ftype_opaque, ALTIVEC_BUILTIN_VEC_SPLATS); |
10017 | def_builtin (MASK_ALTIVEC, "__builtin_vec_promote", opaque_ftype_opaque, ALTIVEC_BUILTIN_VEC_PROMOTE); | |
58646b77 PB |
10018 | |
10019 | def_builtin (MASK_ALTIVEC, "__builtin_vec_sld", opaque_ftype_opaque_opaque_int, ALTIVEC_BUILTIN_VEC_SLD); | |
10020 | def_builtin (MASK_ALTIVEC, "__builtin_vec_splat", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_SPLAT); | |
266b4890 AP |
10021 | def_builtin (MASK_ALTIVEC, "__builtin_vec_extract", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_EXTRACT); |
10022 | def_builtin (MASK_ALTIVEC, "__builtin_vec_insert", opaque_ftype_opaque_opaque_int, ALTIVEC_BUILTIN_VEC_INSERT); | |
58646b77 PB |
10023 | def_builtin (MASK_ALTIVEC, "__builtin_vec_vspltw", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTW); |
10024 | def_builtin (MASK_ALTIVEC, "__builtin_vec_vsplth", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTH); | |
10025 | def_builtin (MASK_ALTIVEC, "__builtin_vec_vspltb", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTB); | |
10026 | def_builtin (MASK_ALTIVEC, "__builtin_vec_ctf", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTF); | |
10027 | def_builtin (MASK_ALTIVEC, "__builtin_vec_vcfsx", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VCFSX); | |
10028 | def_builtin (MASK_ALTIVEC, "__builtin_vec_vcfux", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VCFUX); | |
10029 | def_builtin (MASK_ALTIVEC, "__builtin_vec_cts", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTS); | |
10030 | def_builtin (MASK_ALTIVEC, "__builtin_vec_ctu", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTU); | |
8bb418a3 | 10031 | |
a3170dc6 | 10032 | /* Add the DST variants. */ |
586de218 | 10033 | d = bdesc_dst; |
a3170dc6 | 10034 | for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++) |
8bb418a3 | 10035 | def_builtin (d->mask, d->name, void_ftype_pcvoid_int_int, d->code); |
a3170dc6 AH |
10036 | |
10037 | /* Initialize the predicates. */ | |
586de218 | 10038 | dp = bdesc_altivec_preds; |
a3170dc6 AH |
10039 | for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, dp++) |
10040 | { | |
10041 | enum machine_mode mode1; | |
10042 | tree type; | |
58646b77 PB |
10043 | bool is_overloaded = dp->code >= ALTIVEC_BUILTIN_OVERLOADED_FIRST |
10044 | && dp->code <= ALTIVEC_BUILTIN_OVERLOADED_LAST; | |
a3170dc6 | 10045 | |
58646b77 PB |
10046 | if (is_overloaded) |
10047 | mode1 = VOIDmode; | |
10048 | else | |
10049 | mode1 = insn_data[dp->icode].operand[1].mode; | |
a3170dc6 AH |
10050 | |
10051 | switch (mode1) | |
10052 | { | |
58646b77 PB |
10053 | case VOIDmode: |
10054 | type = int_ftype_int_opaque_opaque; | |
10055 | break; | |
a3170dc6 AH |
10056 | case V4SImode: |
10057 | type = int_ftype_int_v4si_v4si; | |
10058 | break; | |
10059 | case V8HImode: | |
10060 | type = int_ftype_int_v8hi_v8hi; | |
10061 | break; | |
10062 | case V16QImode: | |
10063 | type = int_ftype_int_v16qi_v16qi; | |
10064 | break; | |
10065 | case V4SFmode: | |
10066 | type = int_ftype_int_v4sf_v4sf; | |
10067 | break; | |
10068 | default: | |
37409796 | 10069 | gcc_unreachable (); |
a3170dc6 | 10070 | } |
f676971a | 10071 | |
a3170dc6 AH |
10072 | def_builtin (dp->mask, dp->name, type, dp->code); |
10073 | } | |
10074 | ||
10075 | /* Initialize the abs* operators. */ | |
586de218 | 10076 | d = bdesc_abs; |
a3170dc6 AH |
10077 | for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++) |
10078 | { | |
10079 | enum machine_mode mode0; | |
10080 | tree type; | |
10081 | ||
10082 | mode0 = insn_data[d->icode].operand[0].mode; | |
10083 | ||
10084 | switch (mode0) | |
10085 | { | |
10086 | case V4SImode: | |
10087 | type = v4si_ftype_v4si; | |
10088 | break; | |
10089 | case V8HImode: | |
10090 | type = v8hi_ftype_v8hi; | |
10091 | break; | |
10092 | case V16QImode: | |
10093 | type = v16qi_ftype_v16qi; | |
10094 | break; | |
10095 | case V4SFmode: | |
10096 | type = v4sf_ftype_v4sf; | |
10097 | break; | |
10098 | default: | |
37409796 | 10099 | gcc_unreachable (); |
a3170dc6 | 10100 | } |
f676971a | 10101 | |
a3170dc6 AH |
10102 | def_builtin (d->mask, d->name, type, d->code); |
10103 | } | |
7ccf35ed | 10104 | |
13c62176 DN |
10105 | if (TARGET_ALTIVEC) |
10106 | { | |
10107 | tree decl; | |
10108 | ||
10109 | /* Initialize target builtin that implements | |
10110 | targetm.vectorize.builtin_mask_for_load. */ | |
10111 | ||
c79efc4d RÁE |
10112 | decl = add_builtin_function ("__builtin_altivec_mask_for_load", |
10113 | v16qi_ftype_long_pcvoid, | |
10114 | ALTIVEC_BUILTIN_MASK_FOR_LOAD, | |
61210b72 AP |
10115 | BUILT_IN_MD, NULL, NULL_TREE); |
10116 | TREE_READONLY (decl) = 1; | |
13c62176 DN |
10117 | /* Record the decl. Will be used by rs6000_builtin_mask_for_load. */ |
10118 | altivec_builtin_mask_for_load = decl; | |
13c62176 | 10119 | } |
7a4eca66 DE |
10120 | |
10121 | /* Access to the vec_init patterns. */ | |
10122 | ftype = build_function_type_list (V4SI_type_node, integer_type_node, | |
10123 | integer_type_node, integer_type_node, | |
10124 | integer_type_node, NULL_TREE); | |
10125 | def_builtin (MASK_ALTIVEC, "__builtin_vec_init_v4si", ftype, | |
10126 | ALTIVEC_BUILTIN_VEC_INIT_V4SI); | |
10127 | ||
10128 | ftype = build_function_type_list (V8HI_type_node, short_integer_type_node, | |
10129 | short_integer_type_node, | |
10130 | short_integer_type_node, | |
10131 | short_integer_type_node, | |
10132 | short_integer_type_node, | |
10133 | short_integer_type_node, | |
10134 | short_integer_type_node, | |
10135 | short_integer_type_node, NULL_TREE); | |
10136 | def_builtin (MASK_ALTIVEC, "__builtin_vec_init_v8hi", ftype, | |
10137 | ALTIVEC_BUILTIN_VEC_INIT_V8HI); | |
10138 | ||
10139 | ftype = build_function_type_list (V16QI_type_node, char_type_node, | |
10140 | char_type_node, char_type_node, | |
10141 | char_type_node, char_type_node, | |
10142 | char_type_node, char_type_node, | |
10143 | char_type_node, char_type_node, | |
10144 | char_type_node, char_type_node, | |
10145 | char_type_node, char_type_node, | |
10146 | char_type_node, char_type_node, | |
10147 | char_type_node, NULL_TREE); | |
10148 | def_builtin (MASK_ALTIVEC, "__builtin_vec_init_v16qi", ftype, | |
10149 | ALTIVEC_BUILTIN_VEC_INIT_V16QI); | |
10150 | ||
10151 | ftype = build_function_type_list (V4SF_type_node, float_type_node, | |
10152 | float_type_node, float_type_node, | |
10153 | float_type_node, NULL_TREE); | |
10154 | def_builtin (MASK_ALTIVEC, "__builtin_vec_init_v4sf", ftype, | |
10155 | ALTIVEC_BUILTIN_VEC_INIT_V4SF); | |
10156 | ||
10157 | /* Access to the vec_set patterns. */ | |
10158 | ftype = build_function_type_list (V4SI_type_node, V4SI_type_node, | |
10159 | intSI_type_node, | |
10160 | integer_type_node, NULL_TREE); | |
10161 | def_builtin (MASK_ALTIVEC, "__builtin_vec_set_v4si", ftype, | |
10162 | ALTIVEC_BUILTIN_VEC_SET_V4SI); | |
10163 | ||
10164 | ftype = build_function_type_list (V8HI_type_node, V8HI_type_node, | |
10165 | intHI_type_node, | |
10166 | integer_type_node, NULL_TREE); | |
10167 | def_builtin (MASK_ALTIVEC, "__builtin_vec_set_v8hi", ftype, | |
10168 | ALTIVEC_BUILTIN_VEC_SET_V8HI); | |
10169 | ||
10170 | ftype = build_function_type_list (V8HI_type_node, V16QI_type_node, | |
10171 | intQI_type_node, | |
10172 | integer_type_node, NULL_TREE); | |
10173 | def_builtin (MASK_ALTIVEC, "__builtin_vec_set_v16qi", ftype, | |
10174 | ALTIVEC_BUILTIN_VEC_SET_V16QI); | |
10175 | ||
10176 | ftype = build_function_type_list (V4SF_type_node, V4SF_type_node, | |
10177 | float_type_node, | |
10178 | integer_type_node, NULL_TREE); | |
10179 | def_builtin (MASK_ALTIVEC, "__builtin_vec_set_v4sf", ftype, | |
10180 | ALTIVEC_BUILTIN_VEC_SET_V4SF); | |
10181 | ||
10182 | /* Access to the vec_extract patterns. */ | |
10183 | ftype = build_function_type_list (intSI_type_node, V4SI_type_node, | |
10184 | integer_type_node, NULL_TREE); | |
10185 | def_builtin (MASK_ALTIVEC, "__builtin_vec_ext_v4si", ftype, | |
10186 | ALTIVEC_BUILTIN_VEC_EXT_V4SI); | |
10187 | ||
10188 | ftype = build_function_type_list (intHI_type_node, V8HI_type_node, | |
10189 | integer_type_node, NULL_TREE); | |
10190 | def_builtin (MASK_ALTIVEC, "__builtin_vec_ext_v8hi", ftype, | |
10191 | ALTIVEC_BUILTIN_VEC_EXT_V8HI); | |
10192 | ||
10193 | ftype = build_function_type_list (intQI_type_node, V16QI_type_node, | |
10194 | integer_type_node, NULL_TREE); | |
10195 | def_builtin (MASK_ALTIVEC, "__builtin_vec_ext_v16qi", ftype, | |
10196 | ALTIVEC_BUILTIN_VEC_EXT_V16QI); | |
10197 | ||
10198 | ftype = build_function_type_list (float_type_node, V4SF_type_node, | |
10199 | integer_type_node, NULL_TREE); | |
10200 | def_builtin (MASK_ALTIVEC, "__builtin_vec_ext_v4sf", ftype, | |
10201 | ALTIVEC_BUILTIN_VEC_EXT_V4SF); | |
a3170dc6 AH |
10202 | } |
10203 | ||
10204 | static void | |
863d938c | 10205 | rs6000_common_init_builtins (void) |
a3170dc6 | 10206 | { |
586de218 | 10207 | const struct builtin_description *d; |
a3170dc6 AH |
10208 | size_t i; |
10209 | ||
96038623 DE |
10210 | tree v2sf_ftype_v2sf_v2sf_v2sf |
10211 | = build_function_type_list (V2SF_type_node, | |
10212 | V2SF_type_node, V2SF_type_node, | |
10213 | V2SF_type_node, NULL_TREE); | |
10214 | ||
a3170dc6 AH |
10215 | tree v4sf_ftype_v4sf_v4sf_v16qi |
10216 | = build_function_type_list (V4SF_type_node, | |
10217 | V4SF_type_node, V4SF_type_node, | |
10218 | V16QI_type_node, NULL_TREE); | |
10219 | tree v4si_ftype_v4si_v4si_v16qi | |
10220 | = build_function_type_list (V4SI_type_node, | |
10221 | V4SI_type_node, V4SI_type_node, | |
10222 | V16QI_type_node, NULL_TREE); | |
10223 | tree v8hi_ftype_v8hi_v8hi_v16qi | |
10224 | = build_function_type_list (V8HI_type_node, | |
10225 | V8HI_type_node, V8HI_type_node, | |
10226 | V16QI_type_node, NULL_TREE); | |
10227 | tree v16qi_ftype_v16qi_v16qi_v16qi | |
10228 | = build_function_type_list (V16QI_type_node, | |
10229 | V16QI_type_node, V16QI_type_node, | |
10230 | V16QI_type_node, NULL_TREE); | |
b9e4e5d1 ZL |
10231 | tree v4si_ftype_int |
10232 | = build_function_type_list (V4SI_type_node, integer_type_node, NULL_TREE); | |
10233 | tree v8hi_ftype_int | |
10234 | = build_function_type_list (V8HI_type_node, integer_type_node, NULL_TREE); | |
10235 | tree v16qi_ftype_int | |
10236 | = build_function_type_list (V16QI_type_node, integer_type_node, NULL_TREE); | |
a3170dc6 AH |
10237 | tree v8hi_ftype_v16qi |
10238 | = build_function_type_list (V8HI_type_node, V16QI_type_node, NULL_TREE); | |
10239 | tree v4sf_ftype_v4sf | |
10240 | = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE); | |
10241 | ||
10242 | tree v2si_ftype_v2si_v2si | |
2abe3e28 AH |
10243 | = build_function_type_list (opaque_V2SI_type_node, |
10244 | opaque_V2SI_type_node, | |
10245 | opaque_V2SI_type_node, NULL_TREE); | |
a3170dc6 | 10246 | |
96038623 | 10247 | tree v2sf_ftype_v2sf_v2sf_spe |
2abe3e28 AH |
10248 | = build_function_type_list (opaque_V2SF_type_node, |
10249 | opaque_V2SF_type_node, | |
10250 | opaque_V2SF_type_node, NULL_TREE); | |
a3170dc6 | 10251 | |
96038623 DE |
10252 | tree v2sf_ftype_v2sf_v2sf |
10253 | = build_function_type_list (V2SF_type_node, | |
10254 | V2SF_type_node, | |
10255 | V2SF_type_node, NULL_TREE); | |
10256 | ||
10257 | ||
a3170dc6 | 10258 | tree v2si_ftype_int_int |
2abe3e28 | 10259 | = build_function_type_list (opaque_V2SI_type_node, |
a3170dc6 AH |
10260 | integer_type_node, integer_type_node, |
10261 | NULL_TREE); | |
10262 | ||
58646b77 PB |
10263 | tree opaque_ftype_opaque |
10264 | = build_function_type_list (opaque_V4SI_type_node, | |
10265 | opaque_V4SI_type_node, NULL_TREE); | |
10266 | ||
a3170dc6 | 10267 | tree v2si_ftype_v2si |
2abe3e28 AH |
10268 | = build_function_type_list (opaque_V2SI_type_node, |
10269 | opaque_V2SI_type_node, NULL_TREE); | |
a3170dc6 | 10270 | |
96038623 | 10271 | tree v2sf_ftype_v2sf_spe |
2abe3e28 AH |
10272 | = build_function_type_list (opaque_V2SF_type_node, |
10273 | opaque_V2SF_type_node, NULL_TREE); | |
f676971a | 10274 | |
96038623 DE |
10275 | tree v2sf_ftype_v2sf |
10276 | = build_function_type_list (V2SF_type_node, | |
10277 | V2SF_type_node, NULL_TREE); | |
10278 | ||
a3170dc6 | 10279 | tree v2sf_ftype_v2si |
2abe3e28 AH |
10280 | = build_function_type_list (opaque_V2SF_type_node, |
10281 | opaque_V2SI_type_node, NULL_TREE); | |
a3170dc6 AH |
10282 | |
10283 | tree v2si_ftype_v2sf | |
2abe3e28 AH |
10284 | = build_function_type_list (opaque_V2SI_type_node, |
10285 | opaque_V2SF_type_node, NULL_TREE); | |
a3170dc6 AH |
10286 | |
10287 | tree v2si_ftype_v2si_char | |
2abe3e28 AH |
10288 | = build_function_type_list (opaque_V2SI_type_node, |
10289 | opaque_V2SI_type_node, | |
10290 | char_type_node, NULL_TREE); | |
a3170dc6 AH |
10291 | |
10292 | tree v2si_ftype_int_char | |
2abe3e28 | 10293 | = build_function_type_list (opaque_V2SI_type_node, |
a3170dc6 AH |
10294 | integer_type_node, char_type_node, NULL_TREE); |
10295 | ||
10296 | tree v2si_ftype_char | |
2abe3e28 AH |
10297 | = build_function_type_list (opaque_V2SI_type_node, |
10298 | char_type_node, NULL_TREE); | |
a3170dc6 AH |
10299 | |
10300 | tree int_ftype_int_int | |
10301 | = build_function_type_list (integer_type_node, | |
10302 | integer_type_node, integer_type_node, | |
10303 | NULL_TREE); | |
95385cbb | 10304 | |
58646b77 PB |
10305 | tree opaque_ftype_opaque_opaque |
10306 | = build_function_type_list (opaque_V4SI_type_node, | |
10307 | opaque_V4SI_type_node, opaque_V4SI_type_node, NULL_TREE); | |
0ac081f6 | 10308 | tree v4si_ftype_v4si_v4si |
b4de2f7d AH |
10309 | = build_function_type_list (V4SI_type_node, |
10310 | V4SI_type_node, V4SI_type_node, NULL_TREE); | |
b9e4e5d1 | 10311 | tree v4sf_ftype_v4si_int |
b4de2f7d | 10312 | = build_function_type_list (V4SF_type_node, |
b9e4e5d1 ZL |
10313 | V4SI_type_node, integer_type_node, NULL_TREE); |
10314 | tree v4si_ftype_v4sf_int | |
b4de2f7d | 10315 | = build_function_type_list (V4SI_type_node, |
b9e4e5d1 ZL |
10316 | V4SF_type_node, integer_type_node, NULL_TREE); |
10317 | tree v4si_ftype_v4si_int | |
b4de2f7d | 10318 | = build_function_type_list (V4SI_type_node, |
b9e4e5d1 ZL |
10319 | V4SI_type_node, integer_type_node, NULL_TREE); |
10320 | tree v8hi_ftype_v8hi_int | |
b4de2f7d | 10321 | = build_function_type_list (V8HI_type_node, |
b9e4e5d1 ZL |
10322 | V8HI_type_node, integer_type_node, NULL_TREE); |
10323 | tree v16qi_ftype_v16qi_int | |
b4de2f7d | 10324 | = build_function_type_list (V16QI_type_node, |
b9e4e5d1 ZL |
10325 | V16QI_type_node, integer_type_node, NULL_TREE); |
10326 | tree v16qi_ftype_v16qi_v16qi_int | |
b4de2f7d AH |
10327 | = build_function_type_list (V16QI_type_node, |
10328 | V16QI_type_node, V16QI_type_node, | |
b9e4e5d1 ZL |
10329 | integer_type_node, NULL_TREE); |
10330 | tree v8hi_ftype_v8hi_v8hi_int | |
b4de2f7d AH |
10331 | = build_function_type_list (V8HI_type_node, |
10332 | V8HI_type_node, V8HI_type_node, | |
b9e4e5d1 ZL |
10333 | integer_type_node, NULL_TREE); |
10334 | tree v4si_ftype_v4si_v4si_int | |
b4de2f7d AH |
10335 | = build_function_type_list (V4SI_type_node, |
10336 | V4SI_type_node, V4SI_type_node, | |
b9e4e5d1 ZL |
10337 | integer_type_node, NULL_TREE); |
10338 | tree v4sf_ftype_v4sf_v4sf_int | |
b4de2f7d AH |
10339 | = build_function_type_list (V4SF_type_node, |
10340 | V4SF_type_node, V4SF_type_node, | |
b9e4e5d1 | 10341 | integer_type_node, NULL_TREE); |
0ac081f6 | 10342 | tree v4sf_ftype_v4sf_v4sf |
b4de2f7d AH |
10343 | = build_function_type_list (V4SF_type_node, |
10344 | V4SF_type_node, V4SF_type_node, NULL_TREE); | |
58646b77 PB |
10345 | tree opaque_ftype_opaque_opaque_opaque |
10346 | = build_function_type_list (opaque_V4SI_type_node, | |
10347 | opaque_V4SI_type_node, opaque_V4SI_type_node, | |
10348 | opaque_V4SI_type_node, NULL_TREE); | |
617e0e1d | 10349 | tree v4sf_ftype_v4sf_v4sf_v4si |
b4de2f7d AH |
10350 | = build_function_type_list (V4SF_type_node, |
10351 | V4SF_type_node, V4SF_type_node, | |
10352 | V4SI_type_node, NULL_TREE); | |
2212663f | 10353 | tree v4sf_ftype_v4sf_v4sf_v4sf |
b4de2f7d AH |
10354 | = build_function_type_list (V4SF_type_node, |
10355 | V4SF_type_node, V4SF_type_node, | |
10356 | V4SF_type_node, NULL_TREE); | |
f676971a | 10357 | tree v4si_ftype_v4si_v4si_v4si |
b4de2f7d AH |
10358 | = build_function_type_list (V4SI_type_node, |
10359 | V4SI_type_node, V4SI_type_node, | |
10360 | V4SI_type_node, NULL_TREE); | |
0ac081f6 | 10361 | tree v8hi_ftype_v8hi_v8hi |
b4de2f7d AH |
10362 | = build_function_type_list (V8HI_type_node, |
10363 | V8HI_type_node, V8HI_type_node, NULL_TREE); | |
2212663f | 10364 | tree v8hi_ftype_v8hi_v8hi_v8hi |
b4de2f7d AH |
10365 | = build_function_type_list (V8HI_type_node, |
10366 | V8HI_type_node, V8HI_type_node, | |
10367 | V8HI_type_node, NULL_TREE); | |
c4ad648e | 10368 | tree v4si_ftype_v8hi_v8hi_v4si |
b4de2f7d AH |
10369 | = build_function_type_list (V4SI_type_node, |
10370 | V8HI_type_node, V8HI_type_node, | |
10371 | V4SI_type_node, NULL_TREE); | |
c4ad648e | 10372 | tree v4si_ftype_v16qi_v16qi_v4si |
b4de2f7d AH |
10373 | = build_function_type_list (V4SI_type_node, |
10374 | V16QI_type_node, V16QI_type_node, | |
10375 | V4SI_type_node, NULL_TREE); | |
0ac081f6 | 10376 | tree v16qi_ftype_v16qi_v16qi |
b4de2f7d AH |
10377 | = build_function_type_list (V16QI_type_node, |
10378 | V16QI_type_node, V16QI_type_node, NULL_TREE); | |
0ac081f6 | 10379 | tree v4si_ftype_v4sf_v4sf |
b4de2f7d AH |
10380 | = build_function_type_list (V4SI_type_node, |
10381 | V4SF_type_node, V4SF_type_node, NULL_TREE); | |
0ac081f6 | 10382 | tree v8hi_ftype_v16qi_v16qi |
b4de2f7d AH |
10383 | = build_function_type_list (V8HI_type_node, |
10384 | V16QI_type_node, V16QI_type_node, NULL_TREE); | |
0ac081f6 | 10385 | tree v4si_ftype_v8hi_v8hi |
b4de2f7d AH |
10386 | = build_function_type_list (V4SI_type_node, |
10387 | V8HI_type_node, V8HI_type_node, NULL_TREE); | |
0ac081f6 | 10388 | tree v8hi_ftype_v4si_v4si |
b4de2f7d AH |
10389 | = build_function_type_list (V8HI_type_node, |
10390 | V4SI_type_node, V4SI_type_node, NULL_TREE); | |
0ac081f6 | 10391 | tree v16qi_ftype_v8hi_v8hi |
b4de2f7d AH |
10392 | = build_function_type_list (V16QI_type_node, |
10393 | V8HI_type_node, V8HI_type_node, NULL_TREE); | |
0ac081f6 | 10394 | tree v4si_ftype_v16qi_v4si |
b4de2f7d AH |
10395 | = build_function_type_list (V4SI_type_node, |
10396 | V16QI_type_node, V4SI_type_node, NULL_TREE); | |
fa066a23 | 10397 | tree v4si_ftype_v16qi_v16qi |
b4de2f7d AH |
10398 | = build_function_type_list (V4SI_type_node, |
10399 | V16QI_type_node, V16QI_type_node, NULL_TREE); | |
0ac081f6 | 10400 | tree v4si_ftype_v8hi_v4si |
b4de2f7d AH |
10401 | = build_function_type_list (V4SI_type_node, |
10402 | V8HI_type_node, V4SI_type_node, NULL_TREE); | |
a3170dc6 AH |
10403 | tree v4si_ftype_v8hi |
10404 | = build_function_type_list (V4SI_type_node, V8HI_type_node, NULL_TREE); | |
10405 | tree int_ftype_v4si_v4si | |
10406 | = build_function_type_list (integer_type_node, | |
10407 | V4SI_type_node, V4SI_type_node, NULL_TREE); | |
10408 | tree int_ftype_v4sf_v4sf | |
10409 | = build_function_type_list (integer_type_node, | |
10410 | V4SF_type_node, V4SF_type_node, NULL_TREE); | |
10411 | tree int_ftype_v16qi_v16qi | |
10412 | = build_function_type_list (integer_type_node, | |
10413 | V16QI_type_node, V16QI_type_node, NULL_TREE); | |
0ac081f6 | 10414 | tree int_ftype_v8hi_v8hi |
b4de2f7d AH |
10415 | = build_function_type_list (integer_type_node, |
10416 | V8HI_type_node, V8HI_type_node, NULL_TREE); | |
0ac081f6 | 10417 | |
6f317ef3 | 10418 | /* Add the simple ternary operators. */ |
586de218 | 10419 | d = bdesc_3arg; |
ca7558fc | 10420 | for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++) |
2212663f | 10421 | { |
2212663f DB |
10422 | enum machine_mode mode0, mode1, mode2, mode3; |
10423 | tree type; | |
58646b77 PB |
10424 | bool is_overloaded = d->code >= ALTIVEC_BUILTIN_OVERLOADED_FIRST |
10425 | && d->code <= ALTIVEC_BUILTIN_OVERLOADED_LAST; | |
2212663f | 10426 | |
58646b77 PB |
10427 | if (is_overloaded) |
10428 | { | |
10429 | mode0 = VOIDmode; | |
10430 | mode1 = VOIDmode; | |
10431 | mode2 = VOIDmode; | |
10432 | mode3 = VOIDmode; | |
10433 | } | |
10434 | else | |
10435 | { | |
10436 | if (d->name == 0 || d->icode == CODE_FOR_nothing) | |
10437 | continue; | |
f676971a | 10438 | |
58646b77 PB |
10439 | mode0 = insn_data[d->icode].operand[0].mode; |
10440 | mode1 = insn_data[d->icode].operand[1].mode; | |
10441 | mode2 = insn_data[d->icode].operand[2].mode; | |
10442 | mode3 = insn_data[d->icode].operand[3].mode; | |
10443 | } | |
bb8df8a6 | 10444 | |
2212663f DB |
10445 | /* When all four are of the same mode. */ |
10446 | if (mode0 == mode1 && mode1 == mode2 && mode2 == mode3) | |
10447 | { | |
10448 | switch (mode0) | |
10449 | { | |
58646b77 PB |
10450 | case VOIDmode: |
10451 | type = opaque_ftype_opaque_opaque_opaque; | |
10452 | break; | |
617e0e1d DB |
10453 | case V4SImode: |
10454 | type = v4si_ftype_v4si_v4si_v4si; | |
10455 | break; | |
2212663f DB |
10456 | case V4SFmode: |
10457 | type = v4sf_ftype_v4sf_v4sf_v4sf; | |
10458 | break; | |
10459 | case V8HImode: | |
10460 | type = v8hi_ftype_v8hi_v8hi_v8hi; | |
f676971a | 10461 | break; |
2212663f DB |
10462 | case V16QImode: |
10463 | type = v16qi_ftype_v16qi_v16qi_v16qi; | |
f676971a | 10464 | break; |
96038623 DE |
10465 | case V2SFmode: |
10466 | type = v2sf_ftype_v2sf_v2sf_v2sf; | |
10467 | break; | |
2212663f | 10468 | default: |
37409796 | 10469 | gcc_unreachable (); |
2212663f DB |
10470 | } |
10471 | } | |
10472 | else if (mode0 == mode1 && mode1 == mode2 && mode3 == V16QImode) | |
c4ad648e | 10473 | { |
2212663f DB |
10474 | switch (mode0) |
10475 | { | |
10476 | case V4SImode: | |
10477 | type = v4si_ftype_v4si_v4si_v16qi; | |
10478 | break; | |
10479 | case V4SFmode: | |
10480 | type = v4sf_ftype_v4sf_v4sf_v16qi; | |
10481 | break; | |
10482 | case V8HImode: | |
10483 | type = v8hi_ftype_v8hi_v8hi_v16qi; | |
f676971a | 10484 | break; |
2212663f DB |
10485 | case V16QImode: |
10486 | type = v16qi_ftype_v16qi_v16qi_v16qi; | |
f676971a | 10487 | break; |
2212663f | 10488 | default: |
37409796 | 10489 | gcc_unreachable (); |
2212663f DB |
10490 | } |
10491 | } | |
f676971a | 10492 | else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V16QImode |
2212663f | 10493 | && mode3 == V4SImode) |
24408032 | 10494 | type = v4si_ftype_v16qi_v16qi_v4si; |
f676971a | 10495 | else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V8HImode |
2212663f | 10496 | && mode3 == V4SImode) |
24408032 | 10497 | type = v4si_ftype_v8hi_v8hi_v4si; |
f676971a | 10498 | else if (mode0 == V4SFmode && mode1 == V4SFmode && mode2 == V4SFmode |
617e0e1d | 10499 | && mode3 == V4SImode) |
24408032 AH |
10500 | type = v4sf_ftype_v4sf_v4sf_v4si; |
10501 | ||
a7b376ee | 10502 | /* vchar, vchar, vchar, 4-bit literal. */ |
24408032 AH |
10503 | else if (mode0 == V16QImode && mode1 == mode0 && mode2 == mode0 |
10504 | && mode3 == QImode) | |
b9e4e5d1 | 10505 | type = v16qi_ftype_v16qi_v16qi_int; |
24408032 | 10506 | |
a7b376ee | 10507 | /* vshort, vshort, vshort, 4-bit literal. */ |
24408032 AH |
10508 | else if (mode0 == V8HImode && mode1 == mode0 && mode2 == mode0 |
10509 | && mode3 == QImode) | |
b9e4e5d1 | 10510 | type = v8hi_ftype_v8hi_v8hi_int; |
24408032 | 10511 | |
a7b376ee | 10512 | /* vint, vint, vint, 4-bit literal. */ |
24408032 AH |
10513 | else if (mode0 == V4SImode && mode1 == mode0 && mode2 == mode0 |
10514 | && mode3 == QImode) | |
b9e4e5d1 | 10515 | type = v4si_ftype_v4si_v4si_int; |
24408032 | 10516 | |
a7b376ee | 10517 | /* vfloat, vfloat, vfloat, 4-bit literal. */ |
24408032 AH |
10518 | else if (mode0 == V4SFmode && mode1 == mode0 && mode2 == mode0 |
10519 | && mode3 == QImode) | |
b9e4e5d1 | 10520 | type = v4sf_ftype_v4sf_v4sf_int; |
24408032 | 10521 | |
2212663f | 10522 | else |
37409796 | 10523 | gcc_unreachable (); |
2212663f DB |
10524 | |
10525 | def_builtin (d->mask, d->name, type, d->code); | |
10526 | } | |
10527 | ||
0ac081f6 | 10528 | /* Add the simple binary operators. */ |
00b960c7 | 10529 | d = (struct builtin_description *) bdesc_2arg; |
ca7558fc | 10530 | for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++) |
0ac081f6 AH |
10531 | { |
10532 | enum machine_mode mode0, mode1, mode2; | |
10533 | tree type; | |
58646b77 PB |
10534 | bool is_overloaded = d->code >= ALTIVEC_BUILTIN_OVERLOADED_FIRST |
10535 | && d->code <= ALTIVEC_BUILTIN_OVERLOADED_LAST; | |
0ac081f6 | 10536 | |
58646b77 PB |
10537 | if (is_overloaded) |
10538 | { | |
10539 | mode0 = VOIDmode; | |
10540 | mode1 = VOIDmode; | |
10541 | mode2 = VOIDmode; | |
10542 | } | |
10543 | else | |
bb8df8a6 | 10544 | { |
58646b77 PB |
10545 | if (d->name == 0 || d->icode == CODE_FOR_nothing) |
10546 | continue; | |
f676971a | 10547 | |
58646b77 PB |
10548 | mode0 = insn_data[d->icode].operand[0].mode; |
10549 | mode1 = insn_data[d->icode].operand[1].mode; | |
10550 | mode2 = insn_data[d->icode].operand[2].mode; | |
10551 | } | |
0ac081f6 AH |
10552 | |
10553 | /* When all three operands are of the same mode. */ | |
10554 | if (mode0 == mode1 && mode1 == mode2) | |
10555 | { | |
10556 | switch (mode0) | |
10557 | { | |
58646b77 PB |
10558 | case VOIDmode: |
10559 | type = opaque_ftype_opaque_opaque; | |
10560 | break; | |
0ac081f6 AH |
10561 | case V4SFmode: |
10562 | type = v4sf_ftype_v4sf_v4sf; | |
10563 | break; | |
10564 | case V4SImode: | |
10565 | type = v4si_ftype_v4si_v4si; | |
10566 | break; | |
10567 | case V16QImode: | |
10568 | type = v16qi_ftype_v16qi_v16qi; | |
10569 | break; | |
10570 | case V8HImode: | |
10571 | type = v8hi_ftype_v8hi_v8hi; | |
10572 | break; | |
a3170dc6 AH |
10573 | case V2SImode: |
10574 | type = v2si_ftype_v2si_v2si; | |
10575 | break; | |
96038623 DE |
10576 | case V2SFmode: |
10577 | if (TARGET_PAIRED_FLOAT) | |
10578 | type = v2sf_ftype_v2sf_v2sf; | |
10579 | else | |
10580 | type = v2sf_ftype_v2sf_v2sf_spe; | |
a3170dc6 AH |
10581 | break; |
10582 | case SImode: | |
10583 | type = int_ftype_int_int; | |
10584 | break; | |
0ac081f6 | 10585 | default: |
37409796 | 10586 | gcc_unreachable (); |
0ac081f6 AH |
10587 | } |
10588 | } | |
10589 | ||
10590 | /* A few other combos we really don't want to do manually. */ | |
10591 | ||
10592 | /* vint, vfloat, vfloat. */ | |
10593 | else if (mode0 == V4SImode && mode1 == V4SFmode && mode2 == V4SFmode) | |
10594 | type = v4si_ftype_v4sf_v4sf; | |
10595 | ||
10596 | /* vshort, vchar, vchar. */ | |
10597 | else if (mode0 == V8HImode && mode1 == V16QImode && mode2 == V16QImode) | |
10598 | type = v8hi_ftype_v16qi_v16qi; | |
10599 | ||
10600 | /* vint, vshort, vshort. */ | |
10601 | else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V8HImode) | |
10602 | type = v4si_ftype_v8hi_v8hi; | |
10603 | ||
10604 | /* vshort, vint, vint. */ | |
10605 | else if (mode0 == V8HImode && mode1 == V4SImode && mode2 == V4SImode) | |
10606 | type = v8hi_ftype_v4si_v4si; | |
10607 | ||
10608 | /* vchar, vshort, vshort. */ | |
10609 | else if (mode0 == V16QImode && mode1 == V8HImode && mode2 == V8HImode) | |
10610 | type = v16qi_ftype_v8hi_v8hi; | |
10611 | ||
10612 | /* vint, vchar, vint. */ | |
10613 | else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V4SImode) | |
10614 | type = v4si_ftype_v16qi_v4si; | |
10615 | ||
fa066a23 AH |
10616 | /* vint, vchar, vchar. */ |
10617 | else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V16QImode) | |
10618 | type = v4si_ftype_v16qi_v16qi; | |
10619 | ||
0ac081f6 AH |
10620 | /* vint, vshort, vint. */ |
10621 | else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V4SImode) | |
10622 | type = v4si_ftype_v8hi_v4si; | |
f676971a | 10623 | |
a7b376ee | 10624 | /* vint, vint, 5-bit literal. */ |
2212663f | 10625 | else if (mode0 == V4SImode && mode1 == V4SImode && mode2 == QImode) |
b9e4e5d1 | 10626 | type = v4si_ftype_v4si_int; |
f676971a | 10627 | |
a7b376ee | 10628 | /* vshort, vshort, 5-bit literal. */ |
2212663f | 10629 | else if (mode0 == V8HImode && mode1 == V8HImode && mode2 == QImode) |
b9e4e5d1 | 10630 | type = v8hi_ftype_v8hi_int; |
f676971a | 10631 | |
a7b376ee | 10632 | /* vchar, vchar, 5-bit literal. */ |
2212663f | 10633 | else if (mode0 == V16QImode && mode1 == V16QImode && mode2 == QImode) |
b9e4e5d1 | 10634 | type = v16qi_ftype_v16qi_int; |
0ac081f6 | 10635 | |
a7b376ee | 10636 | /* vfloat, vint, 5-bit literal. */ |
617e0e1d | 10637 | else if (mode0 == V4SFmode && mode1 == V4SImode && mode2 == QImode) |
b9e4e5d1 | 10638 | type = v4sf_ftype_v4si_int; |
f676971a | 10639 | |
a7b376ee | 10640 | /* vint, vfloat, 5-bit literal. */ |
617e0e1d | 10641 | else if (mode0 == V4SImode && mode1 == V4SFmode && mode2 == QImode) |
b9e4e5d1 | 10642 | type = v4si_ftype_v4sf_int; |
617e0e1d | 10643 | |
a3170dc6 AH |
10644 | else if (mode0 == V2SImode && mode1 == SImode && mode2 == SImode) |
10645 | type = v2si_ftype_int_int; | |
10646 | ||
10647 | else if (mode0 == V2SImode && mode1 == V2SImode && mode2 == QImode) | |
10648 | type = v2si_ftype_v2si_char; | |
10649 | ||
10650 | else if (mode0 == V2SImode && mode1 == SImode && mode2 == QImode) | |
10651 | type = v2si_ftype_int_char; | |
10652 | ||
37409796 | 10653 | else |
0ac081f6 | 10654 | { |
37409796 NS |
10655 | /* int, x, x. */ |
10656 | gcc_assert (mode0 == SImode); | |
0ac081f6 AH |
10657 | switch (mode1) |
10658 | { | |
10659 | case V4SImode: | |
10660 | type = int_ftype_v4si_v4si; | |
10661 | break; | |
10662 | case V4SFmode: | |
10663 | type = int_ftype_v4sf_v4sf; | |
10664 | break; | |
10665 | case V16QImode: | |
10666 | type = int_ftype_v16qi_v16qi; | |
10667 | break; | |
10668 | case V8HImode: | |
10669 | type = int_ftype_v8hi_v8hi; | |
10670 | break; | |
10671 | default: | |
37409796 | 10672 | gcc_unreachable (); |
0ac081f6 AH |
10673 | } |
10674 | } | |
10675 | ||
2212663f DB |
10676 | def_builtin (d->mask, d->name, type, d->code); |
10677 | } | |
24408032 | 10678 | |
2212663f DB |
10679 | /* Add the simple unary operators. */ |
10680 | d = (struct builtin_description *) bdesc_1arg; | |
ca7558fc | 10681 | for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++) |
2212663f DB |
10682 | { |
10683 | enum machine_mode mode0, mode1; | |
10684 | tree type; | |
58646b77 PB |
10685 | bool is_overloaded = d->code >= ALTIVEC_BUILTIN_OVERLOADED_FIRST |
10686 | && d->code <= ALTIVEC_BUILTIN_OVERLOADED_LAST; | |
10687 | ||
10688 | if (is_overloaded) | |
10689 | { | |
10690 | mode0 = VOIDmode; | |
10691 | mode1 = VOIDmode; | |
10692 | } | |
10693 | else | |
10694 | { | |
10695 | if (d->name == 0 || d->icode == CODE_FOR_nothing) | |
10696 | continue; | |
bb8df8a6 | 10697 | |
58646b77 PB |
10698 | mode0 = insn_data[d->icode].operand[0].mode; |
10699 | mode1 = insn_data[d->icode].operand[1].mode; | |
10700 | } | |
2212663f DB |
10701 | |
10702 | if (mode0 == V4SImode && mode1 == QImode) | |
c4ad648e | 10703 | type = v4si_ftype_int; |
2212663f | 10704 | else if (mode0 == V8HImode && mode1 == QImode) |
c4ad648e | 10705 | type = v8hi_ftype_int; |
2212663f | 10706 | else if (mode0 == V16QImode && mode1 == QImode) |
c4ad648e | 10707 | type = v16qi_ftype_int; |
58646b77 PB |
10708 | else if (mode0 == VOIDmode && mode1 == VOIDmode) |
10709 | type = opaque_ftype_opaque; | |
617e0e1d DB |
10710 | else if (mode0 == V4SFmode && mode1 == V4SFmode) |
10711 | type = v4sf_ftype_v4sf; | |
20e26713 AH |
10712 | else if (mode0 == V8HImode && mode1 == V16QImode) |
10713 | type = v8hi_ftype_v16qi; | |
10714 | else if (mode0 == V4SImode && mode1 == V8HImode) | |
10715 | type = v4si_ftype_v8hi; | |
a3170dc6 AH |
10716 | else if (mode0 == V2SImode && mode1 == V2SImode) |
10717 | type = v2si_ftype_v2si; | |
10718 | else if (mode0 == V2SFmode && mode1 == V2SFmode) | |
96038623 DE |
10719 | { |
10720 | if (TARGET_PAIRED_FLOAT) | |
10721 | type = v2sf_ftype_v2sf; | |
10722 | else | |
10723 | type = v2sf_ftype_v2sf_spe; | |
10724 | } | |
a3170dc6 AH |
10725 | else if (mode0 == V2SFmode && mode1 == V2SImode) |
10726 | type = v2sf_ftype_v2si; | |
10727 | else if (mode0 == V2SImode && mode1 == V2SFmode) | |
10728 | type = v2si_ftype_v2sf; | |
10729 | else if (mode0 == V2SImode && mode1 == QImode) | |
10730 | type = v2si_ftype_char; | |
2212663f | 10731 | else |
37409796 | 10732 | gcc_unreachable (); |
2212663f | 10733 | |
0ac081f6 AH |
10734 | def_builtin (d->mask, d->name, type, d->code); |
10735 | } | |
10736 | } | |
10737 | ||
c15c90bb ZW |
10738 | static void |
10739 | rs6000_init_libfuncs (void) | |
10740 | { | |
602ea4d3 JJ |
10741 | if (DEFAULT_ABI != ABI_V4 && TARGET_XCOFF |
10742 | && !TARGET_POWER2 && !TARGET_POWERPC) | |
c15c90bb | 10743 | { |
602ea4d3 JJ |
10744 | /* AIX library routines for float->int conversion. */ |
10745 | set_conv_libfunc (sfix_optab, SImode, DFmode, "__itrunc"); | |
10746 | set_conv_libfunc (ufix_optab, SImode, DFmode, "__uitrunc"); | |
10747 | set_conv_libfunc (sfix_optab, SImode, TFmode, "_qitrunc"); | |
10748 | set_conv_libfunc (ufix_optab, SImode, TFmode, "_quitrunc"); | |
10749 | } | |
c15c90bb | 10750 | |
602ea4d3 | 10751 | if (!TARGET_IEEEQUAD) |
98c41d98 | 10752 | /* AIX/Darwin/64-bit Linux quad floating point routines. */ |
602ea4d3 JJ |
10753 | if (!TARGET_XL_COMPAT) |
10754 | { | |
10755 | set_optab_libfunc (add_optab, TFmode, "__gcc_qadd"); | |
10756 | set_optab_libfunc (sub_optab, TFmode, "__gcc_qsub"); | |
10757 | set_optab_libfunc (smul_optab, TFmode, "__gcc_qmul"); | |
10758 | set_optab_libfunc (sdiv_optab, TFmode, "__gcc_qdiv"); | |
d0768f19 | 10759 | |
17caeff2 | 10760 | if (!(TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE))) |
d0768f19 DE |
10761 | { |
10762 | set_optab_libfunc (neg_optab, TFmode, "__gcc_qneg"); | |
10763 | set_optab_libfunc (eq_optab, TFmode, "__gcc_qeq"); | |
10764 | set_optab_libfunc (ne_optab, TFmode, "__gcc_qne"); | |
10765 | set_optab_libfunc (gt_optab, TFmode, "__gcc_qgt"); | |
10766 | set_optab_libfunc (ge_optab, TFmode, "__gcc_qge"); | |
10767 | set_optab_libfunc (lt_optab, TFmode, "__gcc_qlt"); | |
10768 | set_optab_libfunc (le_optab, TFmode, "__gcc_qle"); | |
d0768f19 DE |
10769 | |
10770 | set_conv_libfunc (sext_optab, TFmode, SFmode, "__gcc_stoq"); | |
10771 | set_conv_libfunc (sext_optab, TFmode, DFmode, "__gcc_dtoq"); | |
10772 | set_conv_libfunc (trunc_optab, SFmode, TFmode, "__gcc_qtos"); | |
10773 | set_conv_libfunc (trunc_optab, DFmode, TFmode, "__gcc_qtod"); | |
10774 | set_conv_libfunc (sfix_optab, SImode, TFmode, "__gcc_qtoi"); | |
10775 | set_conv_libfunc (ufix_optab, SImode, TFmode, "__gcc_qtou"); | |
10776 | set_conv_libfunc (sfloat_optab, TFmode, SImode, "__gcc_itoq"); | |
10777 | set_conv_libfunc (ufloat_optab, TFmode, SImode, "__gcc_utoq"); | |
10778 | } | |
b26941b4 JM |
10779 | |
10780 | if (!(TARGET_HARD_FLOAT && TARGET_FPRS)) | |
10781 | set_optab_libfunc (unord_optab, TFmode, "__gcc_qunord"); | |
602ea4d3 JJ |
10782 | } |
10783 | else | |
10784 | { | |
10785 | set_optab_libfunc (add_optab, TFmode, "_xlqadd"); | |
10786 | set_optab_libfunc (sub_optab, TFmode, "_xlqsub"); | |
10787 | set_optab_libfunc (smul_optab, TFmode, "_xlqmul"); | |
10788 | set_optab_libfunc (sdiv_optab, TFmode, "_xlqdiv"); | |
10789 | } | |
c9034561 | 10790 | else |
c15c90bb | 10791 | { |
c9034561 | 10792 | /* 32-bit SVR4 quad floating point routines. */ |
c15c90bb ZW |
10793 | |
10794 | set_optab_libfunc (add_optab, TFmode, "_q_add"); | |
10795 | set_optab_libfunc (sub_optab, TFmode, "_q_sub"); | |
10796 | set_optab_libfunc (neg_optab, TFmode, "_q_neg"); | |
10797 | set_optab_libfunc (smul_optab, TFmode, "_q_mul"); | |
10798 | set_optab_libfunc (sdiv_optab, TFmode, "_q_div"); | |
10799 | if (TARGET_PPC_GPOPT || TARGET_POWER2) | |
10800 | set_optab_libfunc (sqrt_optab, TFmode, "_q_sqrt"); | |
10801 | ||
c9034561 ZW |
10802 | set_optab_libfunc (eq_optab, TFmode, "_q_feq"); |
10803 | set_optab_libfunc (ne_optab, TFmode, "_q_fne"); | |
10804 | set_optab_libfunc (gt_optab, TFmode, "_q_fgt"); | |
10805 | set_optab_libfunc (ge_optab, TFmode, "_q_fge"); | |
10806 | set_optab_libfunc (lt_optab, TFmode, "_q_flt"); | |
10807 | set_optab_libfunc (le_optab, TFmode, "_q_fle"); | |
10808 | ||
85363ca0 ZW |
10809 | set_conv_libfunc (sext_optab, TFmode, SFmode, "_q_stoq"); |
10810 | set_conv_libfunc (sext_optab, TFmode, DFmode, "_q_dtoq"); | |
10811 | set_conv_libfunc (trunc_optab, SFmode, TFmode, "_q_qtos"); | |
10812 | set_conv_libfunc (trunc_optab, DFmode, TFmode, "_q_qtod"); | |
10813 | set_conv_libfunc (sfix_optab, SImode, TFmode, "_q_qtoi"); | |
10814 | set_conv_libfunc (ufix_optab, SImode, TFmode, "_q_qtou"); | |
10815 | set_conv_libfunc (sfloat_optab, TFmode, SImode, "_q_itoq"); | |
57904aa7 | 10816 | set_conv_libfunc (ufloat_optab, TFmode, SImode, "_q_utoq"); |
c15c90bb ZW |
10817 | } |
10818 | } | |
fba73eb1 DE |
10819 | |
10820 | \f | |
10821 | /* Expand a block clear operation, and return 1 if successful. Return 0 | |
10822 | if we should let the compiler generate normal code. | |
10823 | ||
10824 | operands[0] is the destination | |
10825 | operands[1] is the length | |
57e84f18 | 10826 | operands[3] is the alignment */ |
fba73eb1 DE |
10827 | |
10828 | int | |
10829 | expand_block_clear (rtx operands[]) | |
10830 | { | |
10831 | rtx orig_dest = operands[0]; | |
10832 | rtx bytes_rtx = operands[1]; | |
57e84f18 | 10833 | rtx align_rtx = operands[3]; |
5514620a GK |
10834 | bool constp = (GET_CODE (bytes_rtx) == CONST_INT); |
10835 | HOST_WIDE_INT align; | |
10836 | HOST_WIDE_INT bytes; | |
fba73eb1 DE |
10837 | int offset; |
10838 | int clear_bytes; | |
5514620a | 10839 | int clear_step; |
fba73eb1 DE |
10840 | |
10841 | /* If this is not a fixed size move, just call memcpy */ | |
10842 | if (! constp) | |
10843 | return 0; | |
10844 | ||
37409796 NS |
10845 | /* This must be a fixed size alignment */ |
10846 | gcc_assert (GET_CODE (align_rtx) == CONST_INT); | |
fba73eb1 DE |
10847 | align = INTVAL (align_rtx) * BITS_PER_UNIT; |
10848 | ||
10849 | /* Anything to clear? */ | |
10850 | bytes = INTVAL (bytes_rtx); | |
10851 | if (bytes <= 0) | |
10852 | return 1; | |
10853 | ||
5514620a GK |
10854 | /* Use the builtin memset after a point, to avoid huge code bloat. |
10855 | When optimize_size, avoid any significant code bloat; calling | |
10856 | memset is about 4 instructions, so allow for one instruction to | |
10857 | load zero and three to do clearing. */ | |
10858 | if (TARGET_ALTIVEC && align >= 128) | |
10859 | clear_step = 16; | |
10860 | else if (TARGET_POWERPC64 && align >= 32) | |
10861 | clear_step = 8; | |
21d818ff NF |
10862 | else if (TARGET_SPE && align >= 64) |
10863 | clear_step = 8; | |
5514620a GK |
10864 | else |
10865 | clear_step = 4; | |
fba73eb1 | 10866 | |
5514620a GK |
10867 | if (optimize_size && bytes > 3 * clear_step) |
10868 | return 0; | |
10869 | if (! optimize_size && bytes > 8 * clear_step) | |
fba73eb1 DE |
10870 | return 0; |
10871 | ||
10872 | for (offset = 0; bytes > 0; offset += clear_bytes, bytes -= clear_bytes) | |
10873 | { | |
fba73eb1 DE |
10874 | enum machine_mode mode = BLKmode; |
10875 | rtx dest; | |
f676971a | 10876 | |
5514620a GK |
10877 | if (bytes >= 16 && TARGET_ALTIVEC && align >= 128) |
10878 | { | |
10879 | clear_bytes = 16; | |
10880 | mode = V4SImode; | |
10881 | } | |
21d818ff NF |
10882 | else if (bytes >= 8 && TARGET_SPE && align >= 64) |
10883 | { | |
10884 | clear_bytes = 8; | |
10885 | mode = V2SImode; | |
10886 | } | |
5514620a | 10887 | else if (bytes >= 8 && TARGET_POWERPC64 |
21d818ff NF |
10888 | /* 64-bit loads and stores require word-aligned |
10889 | displacements. */ | |
10890 | && (align >= 64 || (!STRICT_ALIGNMENT && align >= 32))) | |
fba73eb1 DE |
10891 | { |
10892 | clear_bytes = 8; | |
10893 | mode = DImode; | |
fba73eb1 | 10894 | } |
5514620a | 10895 | else if (bytes >= 4 && (align >= 32 || !STRICT_ALIGNMENT)) |
fba73eb1 DE |
10896 | { /* move 4 bytes */ |
10897 | clear_bytes = 4; | |
10898 | mode = SImode; | |
fba73eb1 | 10899 | } |
ec53fc93 | 10900 | else if (bytes >= 2 && (align >= 16 || !STRICT_ALIGNMENT)) |
fba73eb1 DE |
10901 | { /* move 2 bytes */ |
10902 | clear_bytes = 2; | |
10903 | mode = HImode; | |
fba73eb1 DE |
10904 | } |
10905 | else /* move 1 byte at a time */ | |
10906 | { | |
10907 | clear_bytes = 1; | |
10908 | mode = QImode; | |
fba73eb1 | 10909 | } |
f676971a | 10910 | |
fba73eb1 | 10911 | dest = adjust_address (orig_dest, mode, offset); |
f676971a | 10912 | |
5514620a | 10913 | emit_move_insn (dest, CONST0_RTX (mode)); |
fba73eb1 DE |
10914 | } |
10915 | ||
10916 | return 1; | |
10917 | } | |
10918 | ||
35aff10b | 10919 | \f |
7e69e155 MM |
10920 | /* Expand a block move operation, and return 1 if successful. Return 0 |
10921 | if we should let the compiler generate normal code. | |
10922 | ||
10923 | operands[0] is the destination | |
10924 | operands[1] is the source | |
10925 | operands[2] is the length | |
10926 | operands[3] is the alignment */ | |
10927 | ||
3933e0e1 MM |
10928 | #define MAX_MOVE_REG 4 |
10929 | ||
7e69e155 | 10930 | int |
a2369ed3 | 10931 | expand_block_move (rtx operands[]) |
7e69e155 | 10932 | { |
b6c9286a MM |
10933 | rtx orig_dest = operands[0]; |
10934 | rtx orig_src = operands[1]; | |
7e69e155 | 10935 | rtx bytes_rtx = operands[2]; |
7e69e155 | 10936 | rtx align_rtx = operands[3]; |
3933e0e1 | 10937 | int constp = (GET_CODE (bytes_rtx) == CONST_INT); |
5ee95df6 | 10938 | int align; |
3933e0e1 MM |
10939 | int bytes; |
10940 | int offset; | |
7e69e155 | 10941 | int move_bytes; |
cabfd258 GK |
10942 | rtx stores[MAX_MOVE_REG]; |
10943 | int num_reg = 0; | |
7e69e155 | 10944 | |
3933e0e1 | 10945 | /* If this is not a fixed size move, just call memcpy */ |
cc0d9ba8 | 10946 | if (! constp) |
3933e0e1 MM |
10947 | return 0; |
10948 | ||
37409796 NS |
10949 | /* This must be a fixed size alignment */ |
10950 | gcc_assert (GET_CODE (align_rtx) == CONST_INT); | |
fba73eb1 | 10951 | align = INTVAL (align_rtx) * BITS_PER_UNIT; |
5ee95df6 | 10952 | |
7e69e155 | 10953 | /* Anything to move? */ |
3933e0e1 MM |
10954 | bytes = INTVAL (bytes_rtx); |
10955 | if (bytes <= 0) | |
7e69e155 MM |
10956 | return 1; |
10957 | ||
ea9982a8 | 10958 | /* store_one_arg depends on expand_block_move to handle at least the size of |
f676971a | 10959 | reg_parm_stack_space. */ |
ea9982a8 | 10960 | if (bytes > (TARGET_POWERPC64 ? 64 : 32)) |
7e69e155 MM |
10961 | return 0; |
10962 | ||
cabfd258 | 10963 | for (offset = 0; bytes > 0; offset += move_bytes, bytes -= move_bytes) |
7e69e155 | 10964 | { |
cabfd258 | 10965 | union { |
70128ad9 | 10966 | rtx (*movmemsi) (rtx, rtx, rtx, rtx); |
a2369ed3 | 10967 | rtx (*mov) (rtx, rtx); |
cabfd258 GK |
10968 | } gen_func; |
10969 | enum machine_mode mode = BLKmode; | |
10970 | rtx src, dest; | |
f676971a | 10971 | |
5514620a GK |
10972 | /* Altivec first, since it will be faster than a string move |
10973 | when it applies, and usually not significantly larger. */ | |
10974 | if (TARGET_ALTIVEC && bytes >= 16 && align >= 128) | |
10975 | { | |
10976 | move_bytes = 16; | |
10977 | mode = V4SImode; | |
10978 | gen_func.mov = gen_movv4si; | |
10979 | } | |
21d818ff NF |
10980 | else if (TARGET_SPE && bytes >= 8 && align >= 64) |
10981 | { | |
10982 | move_bytes = 8; | |
10983 | mode = V2SImode; | |
10984 | gen_func.mov = gen_movv2si; | |
10985 | } | |
5514620a | 10986 | else if (TARGET_STRING |
cabfd258 GK |
10987 | && bytes > 24 /* move up to 32 bytes at a time */ |
10988 | && ! fixed_regs[5] | |
10989 | && ! fixed_regs[6] | |
10990 | && ! fixed_regs[7] | |
10991 | && ! fixed_regs[8] | |
10992 | && ! fixed_regs[9] | |
10993 | && ! fixed_regs[10] | |
10994 | && ! fixed_regs[11] | |
10995 | && ! fixed_regs[12]) | |
7e69e155 | 10996 | { |
cabfd258 | 10997 | move_bytes = (bytes > 32) ? 32 : bytes; |
70128ad9 | 10998 | gen_func.movmemsi = gen_movmemsi_8reg; |
cabfd258 GK |
10999 | } |
11000 | else if (TARGET_STRING | |
11001 | && bytes > 16 /* move up to 24 bytes at a time */ | |
11002 | && ! fixed_regs[5] | |
11003 | && ! fixed_regs[6] | |
11004 | && ! fixed_regs[7] | |
11005 | && ! fixed_regs[8] | |
11006 | && ! fixed_regs[9] | |
11007 | && ! fixed_regs[10]) | |
11008 | { | |
11009 | move_bytes = (bytes > 24) ? 24 : bytes; | |
70128ad9 | 11010 | gen_func.movmemsi = gen_movmemsi_6reg; |
cabfd258 GK |
11011 | } |
11012 | else if (TARGET_STRING | |
11013 | && bytes > 8 /* move up to 16 bytes at a time */ | |
11014 | && ! fixed_regs[5] | |
11015 | && ! fixed_regs[6] | |
11016 | && ! fixed_regs[7] | |
11017 | && ! fixed_regs[8]) | |
11018 | { | |
11019 | move_bytes = (bytes > 16) ? 16 : bytes; | |
70128ad9 | 11020 | gen_func.movmemsi = gen_movmemsi_4reg; |
cabfd258 GK |
11021 | } |
11022 | else if (bytes >= 8 && TARGET_POWERPC64 | |
11023 | /* 64-bit loads and stores require word-aligned | |
11024 | displacements. */ | |
fba73eb1 | 11025 | && (align >= 64 || (!STRICT_ALIGNMENT && align >= 32))) |
cabfd258 GK |
11026 | { |
11027 | move_bytes = 8; | |
11028 | mode = DImode; | |
11029 | gen_func.mov = gen_movdi; | |
11030 | } | |
11031 | else if (TARGET_STRING && bytes > 4 && !TARGET_POWERPC64) | |
11032 | { /* move up to 8 bytes at a time */ | |
11033 | move_bytes = (bytes > 8) ? 8 : bytes; | |
70128ad9 | 11034 | gen_func.movmemsi = gen_movmemsi_2reg; |
cabfd258 | 11035 | } |
cd7d9ca4 | 11036 | else if (bytes >= 4 && (align >= 32 || !STRICT_ALIGNMENT)) |
cabfd258 GK |
11037 | { /* move 4 bytes */ |
11038 | move_bytes = 4; | |
11039 | mode = SImode; | |
11040 | gen_func.mov = gen_movsi; | |
11041 | } | |
ec53fc93 | 11042 | else if (bytes >= 2 && (align >= 16 || !STRICT_ALIGNMENT)) |
cabfd258 GK |
11043 | { /* move 2 bytes */ |
11044 | move_bytes = 2; | |
11045 | mode = HImode; | |
11046 | gen_func.mov = gen_movhi; | |
11047 | } | |
11048 | else if (TARGET_STRING && bytes > 1) | |
11049 | { /* move up to 4 bytes at a time */ | |
11050 | move_bytes = (bytes > 4) ? 4 : bytes; | |
70128ad9 | 11051 | gen_func.movmemsi = gen_movmemsi_1reg; |
cabfd258 GK |
11052 | } |
11053 | else /* move 1 byte at a time */ | |
11054 | { | |
11055 | move_bytes = 1; | |
11056 | mode = QImode; | |
11057 | gen_func.mov = gen_movqi; | |
11058 | } | |
f676971a | 11059 | |
cabfd258 GK |
11060 | src = adjust_address (orig_src, mode, offset); |
11061 | dest = adjust_address (orig_dest, mode, offset); | |
f676971a EC |
11062 | |
11063 | if (mode != BLKmode) | |
cabfd258 GK |
11064 | { |
11065 | rtx tmp_reg = gen_reg_rtx (mode); | |
f676971a | 11066 | |
cabfd258 GK |
11067 | emit_insn ((*gen_func.mov) (tmp_reg, src)); |
11068 | stores[num_reg++] = (*gen_func.mov) (dest, tmp_reg); | |
4c64a852 | 11069 | } |
3933e0e1 | 11070 | |
cabfd258 GK |
11071 | if (mode == BLKmode || num_reg >= MAX_MOVE_REG || bytes == move_bytes) |
11072 | { | |
11073 | int i; | |
11074 | for (i = 0; i < num_reg; i++) | |
11075 | emit_insn (stores[i]); | |
11076 | num_reg = 0; | |
11077 | } | |
35aff10b | 11078 | |
cabfd258 | 11079 | if (mode == BLKmode) |
7e69e155 | 11080 | { |
70128ad9 | 11081 | /* Move the address into scratch registers. The movmemsi |
cabfd258 GK |
11082 | patterns require zero offset. */ |
11083 | if (!REG_P (XEXP (src, 0))) | |
b6c9286a | 11084 | { |
cabfd258 GK |
11085 | rtx src_reg = copy_addr_to_reg (XEXP (src, 0)); |
11086 | src = replace_equiv_address (src, src_reg); | |
b6c9286a | 11087 | } |
cabfd258 | 11088 | set_mem_size (src, GEN_INT (move_bytes)); |
f676971a | 11089 | |
cabfd258 | 11090 | if (!REG_P (XEXP (dest, 0))) |
3933e0e1 | 11091 | { |
cabfd258 GK |
11092 | rtx dest_reg = copy_addr_to_reg (XEXP (dest, 0)); |
11093 | dest = replace_equiv_address (dest, dest_reg); | |
7e69e155 | 11094 | } |
cabfd258 | 11095 | set_mem_size (dest, GEN_INT (move_bytes)); |
f676971a | 11096 | |
70128ad9 | 11097 | emit_insn ((*gen_func.movmemsi) (dest, src, |
cabfd258 GK |
11098 | GEN_INT (move_bytes & 31), |
11099 | align_rtx)); | |
7e69e155 | 11100 | } |
7e69e155 MM |
11101 | } |
11102 | ||
11103 | return 1; | |
11104 | } | |
11105 | ||
d62294f5 | 11106 | \f |
9caa3eb2 DE |
11107 | /* Return a string to perform a load_multiple operation. |
11108 | operands[0] is the vector. | |
11109 | operands[1] is the source address. | |
11110 | operands[2] is the first destination register. */ | |
11111 | ||
11112 | const char * | |
a2369ed3 | 11113 | rs6000_output_load_multiple (rtx operands[3]) |
9caa3eb2 DE |
11114 | { |
11115 | /* We have to handle the case where the pseudo used to contain the address | |
11116 | is assigned to one of the output registers. */ | |
11117 | int i, j; | |
11118 | int words = XVECLEN (operands[0], 0); | |
11119 | rtx xop[10]; | |
11120 | ||
11121 | if (XVECLEN (operands[0], 0) == 1) | |
11122 | return "{l|lwz} %2,0(%1)"; | |
11123 | ||
11124 | for (i = 0; i < words; i++) | |
11125 | if (refers_to_regno_p (REGNO (operands[2]) + i, | |
11126 | REGNO (operands[2]) + i + 1, operands[1], 0)) | |
11127 | { | |
11128 | if (i == words-1) | |
11129 | { | |
11130 | xop[0] = GEN_INT (4 * (words-1)); | |
11131 | xop[1] = operands[1]; | |
11132 | xop[2] = operands[2]; | |
11133 | output_asm_insn ("{lsi|lswi} %2,%1,%0\n\t{l|lwz} %1,%0(%1)", xop); | |
11134 | return ""; | |
11135 | } | |
11136 | else if (i == 0) | |
11137 | { | |
11138 | xop[0] = GEN_INT (4 * (words-1)); | |
11139 | xop[1] = operands[1]; | |
11140 | xop[2] = gen_rtx_REG (SImode, REGNO (operands[2]) + 1); | |
11141 | output_asm_insn ("{cal %1,4(%1)|addi %1,%1,4}\n\t{lsi|lswi} %2,%1,%0\n\t{l|lwz} %1,-4(%1)", xop); | |
11142 | return ""; | |
11143 | } | |
11144 | else | |
11145 | { | |
11146 | for (j = 0; j < words; j++) | |
11147 | if (j != i) | |
11148 | { | |
11149 | xop[0] = GEN_INT (j * 4); | |
11150 | xop[1] = operands[1]; | |
11151 | xop[2] = gen_rtx_REG (SImode, REGNO (operands[2]) + j); | |
11152 | output_asm_insn ("{l|lwz} %2,%0(%1)", xop); | |
11153 | } | |
11154 | xop[0] = GEN_INT (i * 4); | |
11155 | xop[1] = operands[1]; | |
11156 | output_asm_insn ("{l|lwz} %1,%0(%1)", xop); | |
11157 | return ""; | |
11158 | } | |
11159 | } | |
11160 | ||
11161 | return "{lsi|lswi} %2,%1,%N0"; | |
11162 | } | |
11163 | ||
9878760c | 11164 | \f |
a4f6c312 SS |
11165 | /* A validation routine: say whether CODE, a condition code, and MODE |
11166 | match. The other alternatives either don't make sense or should | |
11167 | never be generated. */ | |
39a10a29 | 11168 | |
48d72335 | 11169 | void |
a2369ed3 | 11170 | validate_condition_mode (enum rtx_code code, enum machine_mode mode) |
39a10a29 | 11171 | { |
37409796 NS |
11172 | gcc_assert ((GET_RTX_CLASS (code) == RTX_COMPARE |
11173 | || GET_RTX_CLASS (code) == RTX_COMM_COMPARE) | |
11174 | && GET_MODE_CLASS (mode) == MODE_CC); | |
39a10a29 GK |
11175 | |
11176 | /* These don't make sense. */ | |
37409796 NS |
11177 | gcc_assert ((code != GT && code != LT && code != GE && code != LE) |
11178 | || mode != CCUNSmode); | |
39a10a29 | 11179 | |
37409796 NS |
11180 | gcc_assert ((code != GTU && code != LTU && code != GEU && code != LEU) |
11181 | || mode == CCUNSmode); | |
39a10a29 | 11182 | |
37409796 NS |
11183 | gcc_assert (mode == CCFPmode |
11184 | || (code != ORDERED && code != UNORDERED | |
11185 | && code != UNEQ && code != LTGT | |
11186 | && code != UNGT && code != UNLT | |
11187 | && code != UNGE && code != UNLE)); | |
f676971a EC |
11188 | |
11189 | /* These should never be generated except for | |
bc9ec0e0 | 11190 | flag_finite_math_only. */ |
37409796 NS |
11191 | gcc_assert (mode != CCFPmode |
11192 | || flag_finite_math_only | |
11193 | || (code != LE && code != GE | |
11194 | && code != UNEQ && code != LTGT | |
11195 | && code != UNGT && code != UNLT)); | |
39a10a29 GK |
11196 | |
11197 | /* These are invalid; the information is not there. */ | |
37409796 | 11198 | gcc_assert (mode != CCEQmode || code == EQ || code == NE); |
39a10a29 GK |
11199 | } |
11200 | ||
9878760c RK |
11201 | \f |
11202 | /* Return 1 if ANDOP is a mask that has no bits on that are not in the | |
11203 | mask required to convert the result of a rotate insn into a shift | |
b1765bde | 11204 | left insn of SHIFTOP bits. Both are known to be SImode CONST_INT. */ |
9878760c RK |
11205 | |
11206 | int | |
a2369ed3 | 11207 | includes_lshift_p (rtx shiftop, rtx andop) |
9878760c | 11208 | { |
e2c953b6 DE |
11209 | unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0; |
11210 | ||
11211 | shift_mask <<= INTVAL (shiftop); | |
9878760c | 11212 | |
b1765bde | 11213 | return (INTVAL (andop) & 0xffffffff & ~shift_mask) == 0; |
9878760c RK |
11214 | } |
11215 | ||
11216 | /* Similar, but for right shift. */ | |
11217 | ||
11218 | int | |
a2369ed3 | 11219 | includes_rshift_p (rtx shiftop, rtx andop) |
9878760c | 11220 | { |
a7653a2c | 11221 | unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0; |
9878760c RK |
11222 | |
11223 | shift_mask >>= INTVAL (shiftop); | |
11224 | ||
b1765bde | 11225 | return (INTVAL (andop) & 0xffffffff & ~shift_mask) == 0; |
e2c953b6 DE |
11226 | } |
11227 | ||
c5059423 AM |
11228 | /* Return 1 if ANDOP is a mask suitable for use with an rldic insn |
11229 | to perform a left shift. It must have exactly SHIFTOP least | |
b6d08ca1 | 11230 | significant 0's, then one or more 1's, then zero or more 0's. */ |
e2c953b6 DE |
11231 | |
11232 | int | |
a2369ed3 | 11233 | includes_rldic_lshift_p (rtx shiftop, rtx andop) |
e2c953b6 | 11234 | { |
c5059423 AM |
11235 | if (GET_CODE (andop) == CONST_INT) |
11236 | { | |
02071907 | 11237 | HOST_WIDE_INT c, lsb, shift_mask; |
e2c953b6 | 11238 | |
c5059423 | 11239 | c = INTVAL (andop); |
02071907 | 11240 | if (c == 0 || c == ~0) |
c5059423 | 11241 | return 0; |
e2c953b6 | 11242 | |
02071907 | 11243 | shift_mask = ~0; |
c5059423 AM |
11244 | shift_mask <<= INTVAL (shiftop); |
11245 | ||
b6d08ca1 | 11246 | /* Find the least significant one bit. */ |
c5059423 AM |
11247 | lsb = c & -c; |
11248 | ||
11249 | /* It must coincide with the LSB of the shift mask. */ | |
11250 | if (-lsb != shift_mask) | |
11251 | return 0; | |
e2c953b6 | 11252 | |
c5059423 AM |
11253 | /* Invert to look for the next transition (if any). */ |
11254 | c = ~c; | |
11255 | ||
11256 | /* Remove the low group of ones (originally low group of zeros). */ | |
11257 | c &= -lsb; | |
11258 | ||
11259 | /* Again find the lsb, and check we have all 1's above. */ | |
11260 | lsb = c & -c; | |
11261 | return c == -lsb; | |
11262 | } | |
11263 | else if (GET_CODE (andop) == CONST_DOUBLE | |
11264 | && (GET_MODE (andop) == VOIDmode || GET_MODE (andop) == DImode)) | |
11265 | { | |
02071907 AM |
11266 | HOST_WIDE_INT low, high, lsb; |
11267 | HOST_WIDE_INT shift_mask_low, shift_mask_high; | |
c5059423 AM |
11268 | |
11269 | low = CONST_DOUBLE_LOW (andop); | |
11270 | if (HOST_BITS_PER_WIDE_INT < 64) | |
11271 | high = CONST_DOUBLE_HIGH (andop); | |
11272 | ||
11273 | if ((low == 0 && (HOST_BITS_PER_WIDE_INT >= 64 || high == 0)) | |
02071907 | 11274 | || (low == ~0 && (HOST_BITS_PER_WIDE_INT >= 64 || high == ~0))) |
c5059423 AM |
11275 | return 0; |
11276 | ||
11277 | if (HOST_BITS_PER_WIDE_INT < 64 && low == 0) | |
11278 | { | |
02071907 | 11279 | shift_mask_high = ~0; |
c5059423 AM |
11280 | if (INTVAL (shiftop) > 32) |
11281 | shift_mask_high <<= INTVAL (shiftop) - 32; | |
11282 | ||
11283 | lsb = high & -high; | |
11284 | ||
11285 | if (-lsb != shift_mask_high || INTVAL (shiftop) < 32) | |
11286 | return 0; | |
11287 | ||
11288 | high = ~high; | |
11289 | high &= -lsb; | |
11290 | ||
11291 | lsb = high & -high; | |
11292 | return high == -lsb; | |
11293 | } | |
11294 | ||
02071907 | 11295 | shift_mask_low = ~0; |
c5059423 AM |
11296 | shift_mask_low <<= INTVAL (shiftop); |
11297 | ||
11298 | lsb = low & -low; | |
11299 | ||
11300 | if (-lsb != shift_mask_low) | |
11301 | return 0; | |
11302 | ||
11303 | if (HOST_BITS_PER_WIDE_INT < 64) | |
11304 | high = ~high; | |
11305 | low = ~low; | |
11306 | low &= -lsb; | |
11307 | ||
11308 | if (HOST_BITS_PER_WIDE_INT < 64 && low == 0) | |
11309 | { | |
11310 | lsb = high & -high; | |
11311 | return high == -lsb; | |
11312 | } | |
11313 | ||
11314 | lsb = low & -low; | |
11315 | return low == -lsb && (HOST_BITS_PER_WIDE_INT >= 64 || high == ~0); | |
11316 | } | |
11317 | else | |
11318 | return 0; | |
11319 | } | |
e2c953b6 | 11320 | |
c5059423 AM |
11321 | /* Return 1 if ANDOP is a mask suitable for use with an rldicr insn |
11322 | to perform a left shift. It must have SHIFTOP or more least | |
c1207243 | 11323 | significant 0's, with the remainder of the word 1's. */ |
e2c953b6 | 11324 | |
c5059423 | 11325 | int |
a2369ed3 | 11326 | includes_rldicr_lshift_p (rtx shiftop, rtx andop) |
c5059423 | 11327 | { |
e2c953b6 | 11328 | if (GET_CODE (andop) == CONST_INT) |
c5059423 | 11329 | { |
02071907 | 11330 | HOST_WIDE_INT c, lsb, shift_mask; |
c5059423 | 11331 | |
02071907 | 11332 | shift_mask = ~0; |
c5059423 AM |
11333 | shift_mask <<= INTVAL (shiftop); |
11334 | c = INTVAL (andop); | |
11335 | ||
c1207243 | 11336 | /* Find the least significant one bit. */ |
c5059423 AM |
11337 | lsb = c & -c; |
11338 | ||
11339 | /* It must be covered by the shift mask. | |
a4f6c312 | 11340 | This test also rejects c == 0. */ |
c5059423 AM |
11341 | if ((lsb & shift_mask) == 0) |
11342 | return 0; | |
11343 | ||
11344 | /* Check we have all 1's above the transition, and reject all 1's. */ | |
11345 | return c == -lsb && lsb != 1; | |
11346 | } | |
11347 | else if (GET_CODE (andop) == CONST_DOUBLE | |
11348 | && (GET_MODE (andop) == VOIDmode || GET_MODE (andop) == DImode)) | |
11349 | { | |
02071907 | 11350 | HOST_WIDE_INT low, lsb, shift_mask_low; |
c5059423 AM |
11351 | |
11352 | low = CONST_DOUBLE_LOW (andop); | |
11353 | ||
11354 | if (HOST_BITS_PER_WIDE_INT < 64) | |
11355 | { | |
02071907 | 11356 | HOST_WIDE_INT high, shift_mask_high; |
c5059423 AM |
11357 | |
11358 | high = CONST_DOUBLE_HIGH (andop); | |
11359 | ||
11360 | if (low == 0) | |
11361 | { | |
02071907 | 11362 | shift_mask_high = ~0; |
c5059423 AM |
11363 | if (INTVAL (shiftop) > 32) |
11364 | shift_mask_high <<= INTVAL (shiftop) - 32; | |
11365 | ||
11366 | lsb = high & -high; | |
11367 | ||
11368 | if ((lsb & shift_mask_high) == 0) | |
11369 | return 0; | |
11370 | ||
11371 | return high == -lsb; | |
11372 | } | |
11373 | if (high != ~0) | |
11374 | return 0; | |
11375 | } | |
11376 | ||
02071907 | 11377 | shift_mask_low = ~0; |
c5059423 AM |
11378 | shift_mask_low <<= INTVAL (shiftop); |
11379 | ||
11380 | lsb = low & -low; | |
11381 | ||
11382 | if ((lsb & shift_mask_low) == 0) | |
11383 | return 0; | |
11384 | ||
11385 | return low == -lsb && lsb != 1; | |
11386 | } | |
e2c953b6 | 11387 | else |
c5059423 | 11388 | return 0; |
9878760c | 11389 | } |
35068b43 | 11390 | |
11ac38b2 DE |
11391 | /* Return 1 if operands will generate a valid arguments to rlwimi |
11392 | instruction for insert with right shift in 64-bit mode. The mask may | |
11393 | not start on the first bit or stop on the last bit because wrap-around | |
11394 | effects of instruction do not correspond to semantics of RTL insn. */ | |
11395 | ||
11396 | int | |
11397 | insvdi_rshift_rlwimi_p (rtx sizeop, rtx startop, rtx shiftop) | |
11398 | { | |
429ec7dc DE |
11399 | if (INTVAL (startop) > 32 |
11400 | && INTVAL (startop) < 64 | |
11401 | && INTVAL (sizeop) > 1 | |
11402 | && INTVAL (sizeop) + INTVAL (startop) < 64 | |
11403 | && INTVAL (shiftop) > 0 | |
11404 | && INTVAL (sizeop) + INTVAL (shiftop) < 32 | |
11ac38b2 DE |
11405 | && (64 - (INTVAL (shiftop) & 63)) >= INTVAL (sizeop)) |
11406 | return 1; | |
11407 | ||
11408 | return 0; | |
11409 | } | |
11410 | ||
35068b43 | 11411 | /* Return 1 if REGNO (reg1) == REGNO (reg2) - 1 making them candidates |
90f81f99 | 11412 | for lfq and stfq insns iff the registers are hard registers. */ |
35068b43 RK |
11413 | |
11414 | int | |
a2369ed3 | 11415 | registers_ok_for_quad_peep (rtx reg1, rtx reg2) |
35068b43 RK |
11416 | { |
11417 | /* We might have been passed a SUBREG. */ | |
f676971a | 11418 | if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG) |
35068b43 | 11419 | return 0; |
f676971a | 11420 | |
90f81f99 AP |
11421 | /* We might have been passed non floating point registers. */ |
11422 | if (!FP_REGNO_P (REGNO (reg1)) | |
11423 | || !FP_REGNO_P (REGNO (reg2))) | |
11424 | return 0; | |
35068b43 RK |
11425 | |
11426 | return (REGNO (reg1) == REGNO (reg2) - 1); | |
11427 | } | |
11428 | ||
a4f6c312 SS |
11429 | /* Return 1 if addr1 and addr2 are suitable for lfq or stfq insn. |
11430 | addr1 and addr2 must be in consecutive memory locations | |
11431 | (addr2 == addr1 + 8). */ | |
35068b43 RK |
11432 | |
11433 | int | |
90f81f99 | 11434 | mems_ok_for_quad_peep (rtx mem1, rtx mem2) |
35068b43 | 11435 | { |
90f81f99 | 11436 | rtx addr1, addr2; |
bb8df8a6 EC |
11437 | unsigned int reg1, reg2; |
11438 | int offset1, offset2; | |
35068b43 | 11439 | |
90f81f99 AP |
11440 | /* The mems cannot be volatile. */ |
11441 | if (MEM_VOLATILE_P (mem1) || MEM_VOLATILE_P (mem2)) | |
11442 | return 0; | |
f676971a | 11443 | |
90f81f99 AP |
11444 | addr1 = XEXP (mem1, 0); |
11445 | addr2 = XEXP (mem2, 0); | |
11446 | ||
35068b43 RK |
11447 | /* Extract an offset (if used) from the first addr. */ |
11448 | if (GET_CODE (addr1) == PLUS) | |
11449 | { | |
11450 | /* If not a REG, return zero. */ | |
11451 | if (GET_CODE (XEXP (addr1, 0)) != REG) | |
11452 | return 0; | |
11453 | else | |
11454 | { | |
c4ad648e | 11455 | reg1 = REGNO (XEXP (addr1, 0)); |
35068b43 RK |
11456 | /* The offset must be constant! */ |
11457 | if (GET_CODE (XEXP (addr1, 1)) != CONST_INT) | |
c4ad648e AM |
11458 | return 0; |
11459 | offset1 = INTVAL (XEXP (addr1, 1)); | |
35068b43 RK |
11460 | } |
11461 | } | |
11462 | else if (GET_CODE (addr1) != REG) | |
11463 | return 0; | |
11464 | else | |
11465 | { | |
11466 | reg1 = REGNO (addr1); | |
11467 | /* This was a simple (mem (reg)) expression. Offset is 0. */ | |
11468 | offset1 = 0; | |
11469 | } | |
11470 | ||
bb8df8a6 EC |
11471 | /* And now for the second addr. */ |
11472 | if (GET_CODE (addr2) == PLUS) | |
11473 | { | |
11474 | /* If not a REG, return zero. */ | |
11475 | if (GET_CODE (XEXP (addr2, 0)) != REG) | |
11476 | return 0; | |
11477 | else | |
11478 | { | |
11479 | reg2 = REGNO (XEXP (addr2, 0)); | |
11480 | /* The offset must be constant. */ | |
11481 | if (GET_CODE (XEXP (addr2, 1)) != CONST_INT) | |
11482 | return 0; | |
11483 | offset2 = INTVAL (XEXP (addr2, 1)); | |
11484 | } | |
11485 | } | |
11486 | else if (GET_CODE (addr2) != REG) | |
35068b43 | 11487 | return 0; |
bb8df8a6 EC |
11488 | else |
11489 | { | |
11490 | reg2 = REGNO (addr2); | |
11491 | /* This was a simple (mem (reg)) expression. Offset is 0. */ | |
11492 | offset2 = 0; | |
11493 | } | |
35068b43 | 11494 | |
bb8df8a6 EC |
11495 | /* Both of these must have the same base register. */ |
11496 | if (reg1 != reg2) | |
35068b43 RK |
11497 | return 0; |
11498 | ||
11499 | /* The offset for the second addr must be 8 more than the first addr. */ | |
bb8df8a6 | 11500 | if (offset2 != offset1 + 8) |
35068b43 RK |
11501 | return 0; |
11502 | ||
11503 | /* All the tests passed. addr1 and addr2 are valid for lfq or stfq | |
11504 | instructions. */ | |
11505 | return 1; | |
11506 | } | |
9878760c | 11507 | \f |
e41b2a33 PB |
11508 | |
11509 | rtx | |
11510 | rs6000_secondary_memory_needed_rtx (enum machine_mode mode) | |
11511 | { | |
11512 | static bool eliminated = false; | |
11513 | if (mode != SDmode) | |
11514 | return assign_stack_local (mode, GET_MODE_SIZE (mode), 0); | |
11515 | else | |
11516 | { | |
11517 | rtx mem = cfun->machine->sdmode_stack_slot; | |
11518 | gcc_assert (mem != NULL_RTX); | |
11519 | ||
11520 | if (!eliminated) | |
11521 | { | |
11522 | mem = eliminate_regs (mem, VOIDmode, NULL_RTX); | |
11523 | cfun->machine->sdmode_stack_slot = mem; | |
11524 | eliminated = true; | |
11525 | } | |
11526 | return mem; | |
11527 | } | |
11528 | } | |
11529 | ||
11530 | static tree | |
11531 | rs6000_check_sdmode (tree *tp, int *walk_subtrees, void *data ATTRIBUTE_UNUSED) | |
11532 | { | |
11533 | /* Don't walk into types. */ | |
11534 | if (*tp == NULL_TREE || *tp == error_mark_node || TYPE_P (*tp)) | |
11535 | { | |
11536 | *walk_subtrees = 0; | |
11537 | return NULL_TREE; | |
11538 | } | |
11539 | ||
11540 | switch (TREE_CODE (*tp)) | |
11541 | { | |
11542 | case VAR_DECL: | |
11543 | case PARM_DECL: | |
11544 | case FIELD_DECL: | |
11545 | case RESULT_DECL: | |
11546 | case REAL_CST: | |
fdf4f148 | 11547 | case INDIRECT_REF: |
a0f39282 JJ |
11548 | case ALIGN_INDIRECT_REF: |
11549 | case MISALIGNED_INDIRECT_REF: | |
fdf4f148 | 11550 | case VIEW_CONVERT_EXPR: |
e41b2a33 PB |
11551 | if (TYPE_MODE (TREE_TYPE (*tp)) == SDmode) |
11552 | return *tp; | |
11553 | break; | |
11554 | default: | |
11555 | break; | |
11556 | } | |
11557 | ||
11558 | return NULL_TREE; | |
11559 | } | |
11560 | ||
11561 | ||
11562 | /* Allocate a 64-bit stack slot to be used for copying SDmode | |
11563 | values through if this function has any SDmode references. */ | |
11564 | ||
11565 | static void | |
11566 | rs6000_alloc_sdmode_stack_slot (void) | |
11567 | { | |
11568 | tree t; | |
11569 | basic_block bb; | |
726a989a | 11570 | gimple_stmt_iterator gsi; |
e41b2a33 PB |
11571 | |
11572 | gcc_assert (cfun->machine->sdmode_stack_slot == NULL_RTX); | |
11573 | ||
11574 | FOR_EACH_BB (bb) | |
726a989a | 11575 | for (gsi = gsi_start_bb (bb); !gsi_end_p (gsi); gsi_next (&gsi)) |
e41b2a33 | 11576 | { |
726a989a | 11577 | tree ret = walk_gimple_op (gsi_stmt (gsi), rs6000_check_sdmode, NULL); |
e41b2a33 PB |
11578 | if (ret) |
11579 | { | |
11580 | rtx stack = assign_stack_local (DDmode, GET_MODE_SIZE (DDmode), 0); | |
11581 | cfun->machine->sdmode_stack_slot = adjust_address_nv (stack, | |
11582 | SDmode, 0); | |
11583 | return; | |
11584 | } | |
11585 | } | |
11586 | ||
11587 | /* Check for any SDmode parameters of the function. */ | |
11588 | for (t = DECL_ARGUMENTS (cfun->decl); t; t = TREE_CHAIN (t)) | |
11589 | { | |
11590 | if (TREE_TYPE (t) == error_mark_node) | |
11591 | continue; | |
11592 | ||
11593 | if (TYPE_MODE (TREE_TYPE (t)) == SDmode | |
11594 | || TYPE_MODE (DECL_ARG_TYPE (t)) == SDmode) | |
11595 | { | |
11596 | rtx stack = assign_stack_local (DDmode, GET_MODE_SIZE (DDmode), 0); | |
11597 | cfun->machine->sdmode_stack_slot = adjust_address_nv (stack, | |
11598 | SDmode, 0); | |
11599 | return; | |
11600 | } | |
11601 | } | |
11602 | } | |
11603 | ||
11604 | static void | |
11605 | rs6000_instantiate_decls (void) | |
11606 | { | |
11607 | if (cfun->machine->sdmode_stack_slot != NULL_RTX) | |
11608 | instantiate_decl_rtl (cfun->machine->sdmode_stack_slot); | |
11609 | } | |
11610 | ||
9878760c | 11611 | /* Return the register class of a scratch register needed to copy IN into |
0a2aaacc | 11612 | or out of a register in RCLASS in MODE. If it can be done directly, |
9878760c RK |
11613 | NO_REGS is returned. */ |
11614 | ||
11615 | enum reg_class | |
0a2aaacc | 11616 | rs6000_secondary_reload_class (enum reg_class rclass, |
3c4774e0 R |
11617 | enum machine_mode mode ATTRIBUTE_UNUSED, |
11618 | rtx in) | |
9878760c | 11619 | { |
5accd822 | 11620 | int regno; |
9878760c | 11621 | |
ab82a49f AP |
11622 | if (TARGET_ELF || (DEFAULT_ABI == ABI_DARWIN |
11623 | #if TARGET_MACHO | |
c4ad648e | 11624 | && MACHOPIC_INDIRECT |
ab82a49f | 11625 | #endif |
c4ad648e | 11626 | )) |
46fad5b7 DJ |
11627 | { |
11628 | /* We cannot copy a symbolic operand directly into anything | |
c4ad648e AM |
11629 | other than BASE_REGS for TARGET_ELF. So indicate that a |
11630 | register from BASE_REGS is needed as an intermediate | |
11631 | register. | |
f676971a | 11632 | |
46fad5b7 DJ |
11633 | On Darwin, pic addresses require a load from memory, which |
11634 | needs a base register. */ | |
0a2aaacc | 11635 | if (rclass != BASE_REGS |
c4ad648e AM |
11636 | && (GET_CODE (in) == SYMBOL_REF |
11637 | || GET_CODE (in) == HIGH | |
11638 | || GET_CODE (in) == LABEL_REF | |
11639 | || GET_CODE (in) == CONST)) | |
11640 | return BASE_REGS; | |
46fad5b7 | 11641 | } |
e7b7998a | 11642 | |
5accd822 DE |
11643 | if (GET_CODE (in) == REG) |
11644 | { | |
11645 | regno = REGNO (in); | |
11646 | if (regno >= FIRST_PSEUDO_REGISTER) | |
11647 | { | |
11648 | regno = true_regnum (in); | |
11649 | if (regno >= FIRST_PSEUDO_REGISTER) | |
11650 | regno = -1; | |
11651 | } | |
11652 | } | |
11653 | else if (GET_CODE (in) == SUBREG) | |
11654 | { | |
11655 | regno = true_regnum (in); | |
11656 | if (regno >= FIRST_PSEUDO_REGISTER) | |
11657 | regno = -1; | |
11658 | } | |
11659 | else | |
11660 | regno = -1; | |
11661 | ||
9878760c RK |
11662 | /* We can place anything into GENERAL_REGS and can put GENERAL_REGS |
11663 | into anything. */ | |
0a2aaacc | 11664 | if (rclass == GENERAL_REGS || rclass == BASE_REGS |
9878760c RK |
11665 | || (regno >= 0 && INT_REGNO_P (regno))) |
11666 | return NO_REGS; | |
11667 | ||
11668 | /* Constants, memory, and FP registers can go into FP registers. */ | |
11669 | if ((regno == -1 || FP_REGNO_P (regno)) | |
0a2aaacc | 11670 | && (rclass == FLOAT_REGS || rclass == NON_SPECIAL_REGS)) |
e41b2a33 | 11671 | return (mode != SDmode) ? NO_REGS : GENERAL_REGS; |
9878760c | 11672 | |
0ac081f6 AH |
11673 | /* Memory, and AltiVec registers can go into AltiVec registers. */ |
11674 | if ((regno == -1 || ALTIVEC_REGNO_P (regno)) | |
0a2aaacc | 11675 | && rclass == ALTIVEC_REGS) |
0ac081f6 AH |
11676 | return NO_REGS; |
11677 | ||
9878760c | 11678 | /* We can copy among the CR registers. */ |
0a2aaacc | 11679 | if ((rclass == CR_REGS || rclass == CR0_REGS) |
9878760c RK |
11680 | && regno >= 0 && CR_REGNO_P (regno)) |
11681 | return NO_REGS; | |
11682 | ||
11683 | /* Otherwise, we need GENERAL_REGS. */ | |
11684 | return GENERAL_REGS; | |
11685 | } | |
11686 | \f | |
11687 | /* Given a comparison operation, return the bit number in CCR to test. We | |
f676971a | 11688 | know this is a valid comparison. |
9878760c RK |
11689 | |
11690 | SCC_P is 1 if this is for an scc. That means that %D will have been | |
11691 | used instead of %C, so the bits will be in different places. | |
11692 | ||
b4ac57ab | 11693 | Return -1 if OP isn't a valid comparison for some reason. */ |
9878760c RK |
11694 | |
11695 | int | |
a2369ed3 | 11696 | ccr_bit (rtx op, int scc_p) |
9878760c RK |
11697 | { |
11698 | enum rtx_code code = GET_CODE (op); | |
11699 | enum machine_mode cc_mode; | |
11700 | int cc_regnum; | |
11701 | int base_bit; | |
9ebbca7d | 11702 | rtx reg; |
9878760c | 11703 | |
ec8e098d | 11704 | if (!COMPARISON_P (op)) |
9878760c RK |
11705 | return -1; |
11706 | ||
9ebbca7d GK |
11707 | reg = XEXP (op, 0); |
11708 | ||
37409796 | 11709 | gcc_assert (GET_CODE (reg) == REG && CR_REGNO_P (REGNO (reg))); |
9ebbca7d GK |
11710 | |
11711 | cc_mode = GET_MODE (reg); | |
11712 | cc_regnum = REGNO (reg); | |
11713 | base_bit = 4 * (cc_regnum - CR0_REGNO); | |
9878760c | 11714 | |
39a10a29 | 11715 | validate_condition_mode (code, cc_mode); |
c5defebb | 11716 | |
b7053a3f GK |
11717 | /* When generating a sCOND operation, only positive conditions are |
11718 | allowed. */ | |
37409796 NS |
11719 | gcc_assert (!scc_p |
11720 | || code == EQ || code == GT || code == LT || code == UNORDERED | |
11721 | || code == GTU || code == LTU); | |
f676971a | 11722 | |
9878760c RK |
11723 | switch (code) |
11724 | { | |
11725 | case NE: | |
11726 | return scc_p ? base_bit + 3 : base_bit + 2; | |
11727 | case EQ: | |
11728 | return base_bit + 2; | |
1c882ea4 | 11729 | case GT: case GTU: case UNLE: |
9878760c | 11730 | return base_bit + 1; |
1c882ea4 | 11731 | case LT: case LTU: case UNGE: |
9878760c | 11732 | return base_bit; |
1c882ea4 GK |
11733 | case ORDERED: case UNORDERED: |
11734 | return base_bit + 3; | |
9878760c RK |
11735 | |
11736 | case GE: case GEU: | |
39a10a29 | 11737 | /* If scc, we will have done a cror to put the bit in the |
9878760c RK |
11738 | unordered position. So test that bit. For integer, this is ! LT |
11739 | unless this is an scc insn. */ | |
39a10a29 | 11740 | return scc_p ? base_bit + 3 : base_bit; |
9878760c RK |
11741 | |
11742 | case LE: case LEU: | |
39a10a29 | 11743 | return scc_p ? base_bit + 3 : base_bit + 1; |
1c882ea4 | 11744 | |
9878760c | 11745 | default: |
37409796 | 11746 | gcc_unreachable (); |
9878760c RK |
11747 | } |
11748 | } | |
1ff7789b | 11749 | \f |
8d30c4ee | 11750 | /* Return the GOT register. */ |
1ff7789b | 11751 | |
9390387d | 11752 | rtx |
a2369ed3 | 11753 | rs6000_got_register (rtx value ATTRIBUTE_UNUSED) |
1ff7789b | 11754 | { |
a4f6c312 SS |
11755 | /* The second flow pass currently (June 1999) can't update |
11756 | regs_ever_live without disturbing other parts of the compiler, so | |
11757 | update it here to make the prolog/epilogue code happy. */ | |
b3a13419 ILT |
11758 | if (!can_create_pseudo_p () |
11759 | && !df_regs_ever_live_p (RS6000_PIC_OFFSET_TABLE_REGNUM)) | |
6fb5fa3c | 11760 | df_set_regs_ever_live (RS6000_PIC_OFFSET_TABLE_REGNUM, true); |
1ff7789b | 11761 | |
e3b5732b | 11762 | crtl->uses_pic_offset_table = 1; |
3cb999d8 | 11763 | |
1ff7789b MM |
11764 | return pic_offset_table_rtx; |
11765 | } | |
a7df97e6 | 11766 | \f |
e2500fed GK |
11767 | /* Function to init struct machine_function. |
11768 | This will be called, via a pointer variable, | |
11769 | from push_function_context. */ | |
a7df97e6 | 11770 | |
e2500fed | 11771 | static struct machine_function * |
863d938c | 11772 | rs6000_init_machine_status (void) |
a7df97e6 | 11773 | { |
5ead67f6 | 11774 | return GGC_CNEW (machine_function); |
a7df97e6 | 11775 | } |
9878760c | 11776 | \f |
0ba1b2ff AM |
11777 | /* These macros test for integers and extract the low-order bits. */ |
11778 | #define INT_P(X) \ | |
11779 | ((GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST_DOUBLE) \ | |
11780 | && GET_MODE (X) == VOIDmode) | |
11781 | ||
11782 | #define INT_LOWPART(X) \ | |
11783 | (GET_CODE (X) == CONST_INT ? INTVAL (X) : CONST_DOUBLE_LOW (X)) | |
11784 | ||
11785 | int | |
a2369ed3 | 11786 | extract_MB (rtx op) |
0ba1b2ff AM |
11787 | { |
11788 | int i; | |
11789 | unsigned long val = INT_LOWPART (op); | |
11790 | ||
11791 | /* If the high bit is zero, the value is the first 1 bit we find | |
11792 | from the left. */ | |
11793 | if ((val & 0x80000000) == 0) | |
11794 | { | |
37409796 | 11795 | gcc_assert (val & 0xffffffff); |
0ba1b2ff AM |
11796 | |
11797 | i = 1; | |
11798 | while (((val <<= 1) & 0x80000000) == 0) | |
11799 | ++i; | |
11800 | return i; | |
11801 | } | |
11802 | ||
11803 | /* If the high bit is set and the low bit is not, or the mask is all | |
11804 | 1's, the value is zero. */ | |
11805 | if ((val & 1) == 0 || (val & 0xffffffff) == 0xffffffff) | |
11806 | return 0; | |
11807 | ||
11808 | /* Otherwise we have a wrap-around mask. Look for the first 0 bit | |
11809 | from the right. */ | |
11810 | i = 31; | |
11811 | while (((val >>= 1) & 1) != 0) | |
11812 | --i; | |
11813 | ||
11814 | return i; | |
11815 | } | |
11816 | ||
11817 | int | |
a2369ed3 | 11818 | extract_ME (rtx op) |
0ba1b2ff AM |
11819 | { |
11820 | int i; | |
11821 | unsigned long val = INT_LOWPART (op); | |
11822 | ||
11823 | /* If the low bit is zero, the value is the first 1 bit we find from | |
11824 | the right. */ | |
11825 | if ((val & 1) == 0) | |
11826 | { | |
37409796 | 11827 | gcc_assert (val & 0xffffffff); |
0ba1b2ff AM |
11828 | |
11829 | i = 30; | |
11830 | while (((val >>= 1) & 1) == 0) | |
11831 | --i; | |
11832 | ||
11833 | return i; | |
11834 | } | |
11835 | ||
11836 | /* If the low bit is set and the high bit is not, or the mask is all | |
11837 | 1's, the value is 31. */ | |
11838 | if ((val & 0x80000000) == 0 || (val & 0xffffffff) == 0xffffffff) | |
11839 | return 31; | |
11840 | ||
11841 | /* Otherwise we have a wrap-around mask. Look for the first 0 bit | |
11842 | from the left. */ | |
11843 | i = 0; | |
11844 | while (((val <<= 1) & 0x80000000) != 0) | |
11845 | ++i; | |
11846 | ||
11847 | return i; | |
11848 | } | |
11849 | ||
c4501e62 JJ |
11850 | /* Locate some local-dynamic symbol still in use by this function |
11851 | so that we can print its name in some tls_ld pattern. */ | |
11852 | ||
11853 | static const char * | |
863d938c | 11854 | rs6000_get_some_local_dynamic_name (void) |
c4501e62 JJ |
11855 | { |
11856 | rtx insn; | |
11857 | ||
11858 | if (cfun->machine->some_ld_name) | |
11859 | return cfun->machine->some_ld_name; | |
11860 | ||
11861 | for (insn = get_insns (); insn ; insn = NEXT_INSN (insn)) | |
11862 | if (INSN_P (insn) | |
11863 | && for_each_rtx (&PATTERN (insn), | |
11864 | rs6000_get_some_local_dynamic_name_1, 0)) | |
11865 | return cfun->machine->some_ld_name; | |
11866 | ||
37409796 | 11867 | gcc_unreachable (); |
c4501e62 JJ |
11868 | } |
11869 | ||
11870 | /* Helper function for rs6000_get_some_local_dynamic_name. */ | |
11871 | ||
11872 | static int | |
a2369ed3 | 11873 | rs6000_get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED) |
c4501e62 JJ |
11874 | { |
11875 | rtx x = *px; | |
11876 | ||
11877 | if (GET_CODE (x) == SYMBOL_REF) | |
11878 | { | |
11879 | const char *str = XSTR (x, 0); | |
11880 | if (SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC) | |
11881 | { | |
11882 | cfun->machine->some_ld_name = str; | |
11883 | return 1; | |
11884 | } | |
11885 | } | |
11886 | ||
11887 | return 0; | |
11888 | } | |
11889 | ||
85b776df AM |
11890 | /* Write out a function code label. */ |
11891 | ||
11892 | void | |
11893 | rs6000_output_function_entry (FILE *file, const char *fname) | |
11894 | { | |
11895 | if (fname[0] != '.') | |
11896 | { | |
11897 | switch (DEFAULT_ABI) | |
11898 | { | |
11899 | default: | |
37409796 | 11900 | gcc_unreachable (); |
85b776df AM |
11901 | |
11902 | case ABI_AIX: | |
11903 | if (DOT_SYMBOLS) | |
11904 | putc ('.', file); | |
11905 | else | |
11906 | ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "L."); | |
11907 | break; | |
11908 | ||
11909 | case ABI_V4: | |
11910 | case ABI_DARWIN: | |
11911 | break; | |
11912 | } | |
11913 | } | |
11914 | if (TARGET_AIX) | |
11915 | RS6000_OUTPUT_BASENAME (file, fname); | |
11916 | else | |
11917 | assemble_name (file, fname); | |
11918 | } | |
11919 | ||
9878760c RK |
11920 | /* Print an operand. Recognize special options, documented below. */ |
11921 | ||
38c1f2d7 | 11922 | #if TARGET_ELF |
d9407988 | 11923 | #define SMALL_DATA_RELOC ((rs6000_sdata == SDATA_EABI) ? "sda21" : "sdarel") |
8fbd2dc7 | 11924 | #define SMALL_DATA_REG ((rs6000_sdata == SDATA_EABI) ? 0 : 13) |
ba5e43aa MM |
11925 | #else |
11926 | #define SMALL_DATA_RELOC "sda21" | |
8fbd2dc7 | 11927 | #define SMALL_DATA_REG 0 |
ba5e43aa MM |
11928 | #endif |
11929 | ||
9878760c | 11930 | void |
a2369ed3 | 11931 | print_operand (FILE *file, rtx x, int code) |
9878760c RK |
11932 | { |
11933 | int i; | |
a260abc9 | 11934 | HOST_WIDE_INT val; |
0ba1b2ff | 11935 | unsigned HOST_WIDE_INT uval; |
9878760c RK |
11936 | |
11937 | switch (code) | |
11938 | { | |
a8b3aeda | 11939 | case '.': |
a85d226b RK |
11940 | /* Write out an instruction after the call which may be replaced |
11941 | with glue code by the loader. This depends on the AIX version. */ | |
11942 | asm_fprintf (file, RS6000_CALL_GLUE); | |
a8b3aeda RK |
11943 | return; |
11944 | ||
81eace42 GK |
11945 | /* %a is output_address. */ |
11946 | ||
9854d9ed RK |
11947 | case 'A': |
11948 | /* If X is a constant integer whose low-order 5 bits are zero, | |
11949 | write 'l'. Otherwise, write 'r'. This is a kludge to fix a bug | |
76229ac8 | 11950 | in the AIX assembler where "sri" with a zero shift count |
20e26713 | 11951 | writes a trash instruction. */ |
9854d9ed | 11952 | if (GET_CODE (x) == CONST_INT && (INTVAL (x) & 31) == 0) |
76229ac8 | 11953 | putc ('l', file); |
9854d9ed | 11954 | else |
76229ac8 | 11955 | putc ('r', file); |
9854d9ed RK |
11956 | return; |
11957 | ||
11958 | case 'b': | |
e2c953b6 DE |
11959 | /* If constant, low-order 16 bits of constant, unsigned. |
11960 | Otherwise, write normally. */ | |
11961 | if (INT_P (x)) | |
11962 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 0xffff); | |
11963 | else | |
11964 | print_operand (file, x, 0); | |
cad12a8d RK |
11965 | return; |
11966 | ||
a260abc9 DE |
11967 | case 'B': |
11968 | /* If the low-order bit is zero, write 'r'; otherwise, write 'l' | |
11969 | for 64-bit mask direction. */ | |
9390387d | 11970 | putc (((INT_LOWPART (x) & 1) == 0 ? 'r' : 'l'), file); |
a238cd8b | 11971 | return; |
a260abc9 | 11972 | |
81eace42 GK |
11973 | /* %c is output_addr_const if a CONSTANT_ADDRESS_P, otherwise |
11974 | output_operand. */ | |
11975 | ||
423c1189 AH |
11976 | case 'c': |
11977 | /* X is a CR register. Print the number of the GT bit of the CR. */ | |
11978 | if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x))) | |
11979 | output_operand_lossage ("invalid %%E value"); | |
11980 | else | |
11981 | fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO) + 1); | |
11982 | return; | |
11983 | ||
11984 | case 'D': | |
cef6b86c | 11985 | /* Like 'J' but get to the GT bit only. */ |
37409796 | 11986 | gcc_assert (GET_CODE (x) == REG); |
423c1189 | 11987 | |
cef6b86c EB |
11988 | /* Bit 1 is GT bit. */ |
11989 | i = 4 * (REGNO (x) - CR0_REGNO) + 1; | |
423c1189 | 11990 | |
cef6b86c EB |
11991 | /* Add one for shift count in rlinm for scc. */ |
11992 | fprintf (file, "%d", i + 1); | |
423c1189 AH |
11993 | return; |
11994 | ||
9854d9ed | 11995 | case 'E': |
39a10a29 | 11996 | /* X is a CR register. Print the number of the EQ bit of the CR */ |
9854d9ed RK |
11997 | if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x))) |
11998 | output_operand_lossage ("invalid %%E value"); | |
78fbdbf7 | 11999 | else |
39a10a29 | 12000 | fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO) + 2); |
a85d226b | 12001 | return; |
9854d9ed RK |
12002 | |
12003 | case 'f': | |
12004 | /* X is a CR register. Print the shift count needed to move it | |
12005 | to the high-order four bits. */ | |
12006 | if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x))) | |
12007 | output_operand_lossage ("invalid %%f value"); | |
12008 | else | |
9ebbca7d | 12009 | fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO)); |
9854d9ed RK |
12010 | return; |
12011 | ||
12012 | case 'F': | |
12013 | /* Similar, but print the count for the rotate in the opposite | |
12014 | direction. */ | |
12015 | if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x))) | |
12016 | output_operand_lossage ("invalid %%F value"); | |
12017 | else | |
9ebbca7d | 12018 | fprintf (file, "%d", 32 - 4 * (REGNO (x) - CR0_REGNO)); |
9854d9ed RK |
12019 | return; |
12020 | ||
12021 | case 'G': | |
12022 | /* X is a constant integer. If it is negative, print "m", | |
43aa4e05 | 12023 | otherwise print "z". This is to make an aze or ame insn. */ |
9854d9ed RK |
12024 | if (GET_CODE (x) != CONST_INT) |
12025 | output_operand_lossage ("invalid %%G value"); | |
12026 | else if (INTVAL (x) >= 0) | |
76229ac8 | 12027 | putc ('z', file); |
9854d9ed | 12028 | else |
76229ac8 | 12029 | putc ('m', file); |
9854d9ed | 12030 | return; |
e2c953b6 | 12031 | |
9878760c | 12032 | case 'h': |
a4f6c312 SS |
12033 | /* If constant, output low-order five bits. Otherwise, write |
12034 | normally. */ | |
9878760c | 12035 | if (INT_P (x)) |
5f59ecb7 | 12036 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 31); |
9878760c RK |
12037 | else |
12038 | print_operand (file, x, 0); | |
12039 | return; | |
12040 | ||
64305719 | 12041 | case 'H': |
a4f6c312 SS |
12042 | /* If constant, output low-order six bits. Otherwise, write |
12043 | normally. */ | |
64305719 | 12044 | if (INT_P (x)) |
5f59ecb7 | 12045 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 63); |
64305719 DE |
12046 | else |
12047 | print_operand (file, x, 0); | |
12048 | return; | |
12049 | ||
9854d9ed RK |
12050 | case 'I': |
12051 | /* Print `i' if this is a constant, else nothing. */ | |
9878760c | 12052 | if (INT_P (x)) |
76229ac8 | 12053 | putc ('i', file); |
9878760c RK |
12054 | return; |
12055 | ||
9854d9ed RK |
12056 | case 'j': |
12057 | /* Write the bit number in CCR for jump. */ | |
12058 | i = ccr_bit (x, 0); | |
12059 | if (i == -1) | |
12060 | output_operand_lossage ("invalid %%j code"); | |
9878760c | 12061 | else |
9854d9ed | 12062 | fprintf (file, "%d", i); |
9878760c RK |
12063 | return; |
12064 | ||
9854d9ed RK |
12065 | case 'J': |
12066 | /* Similar, but add one for shift count in rlinm for scc and pass | |
12067 | scc flag to `ccr_bit'. */ | |
12068 | i = ccr_bit (x, 1); | |
12069 | if (i == -1) | |
12070 | output_operand_lossage ("invalid %%J code"); | |
12071 | else | |
a0466a68 RK |
12072 | /* If we want bit 31, write a shift count of zero, not 32. */ |
12073 | fprintf (file, "%d", i == 31 ? 0 : i + 1); | |
9878760c RK |
12074 | return; |
12075 | ||
9854d9ed RK |
12076 | case 'k': |
12077 | /* X must be a constant. Write the 1's complement of the | |
12078 | constant. */ | |
9878760c | 12079 | if (! INT_P (x)) |
9854d9ed | 12080 | output_operand_lossage ("invalid %%k value"); |
e2c953b6 DE |
12081 | else |
12082 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, ~ INT_LOWPART (x)); | |
9878760c RK |
12083 | return; |
12084 | ||
81eace42 | 12085 | case 'K': |
9ebbca7d GK |
12086 | /* X must be a symbolic constant on ELF. Write an |
12087 | expression suitable for an 'addi' that adds in the low 16 | |
12088 | bits of the MEM. */ | |
12089 | if (GET_CODE (x) != CONST) | |
12090 | { | |
12091 | print_operand_address (file, x); | |
12092 | fputs ("@l", file); | |
12093 | } | |
12094 | else | |
12095 | { | |
12096 | if (GET_CODE (XEXP (x, 0)) != PLUS | |
12097 | || (GET_CODE (XEXP (XEXP (x, 0), 0)) != SYMBOL_REF | |
12098 | && GET_CODE (XEXP (XEXP (x, 0), 0)) != LABEL_REF) | |
12099 | || GET_CODE (XEXP (XEXP (x, 0), 1)) != CONST_INT) | |
53cd5d6c | 12100 | output_operand_lossage ("invalid %%K value"); |
9ebbca7d GK |
12101 | print_operand_address (file, XEXP (XEXP (x, 0), 0)); |
12102 | fputs ("@l", file); | |
ed8d2920 MM |
12103 | /* For GNU as, there must be a non-alphanumeric character |
12104 | between 'l' and the number. The '-' is added by | |
12105 | print_operand() already. */ | |
12106 | if (INTVAL (XEXP (XEXP (x, 0), 1)) >= 0) | |
12107 | fputs ("+", file); | |
9ebbca7d GK |
12108 | print_operand (file, XEXP (XEXP (x, 0), 1), 0); |
12109 | } | |
81eace42 GK |
12110 | return; |
12111 | ||
12112 | /* %l is output_asm_label. */ | |
9ebbca7d | 12113 | |
9854d9ed RK |
12114 | case 'L': |
12115 | /* Write second word of DImode or DFmode reference. Works on register | |
12116 | or non-indexed memory only. */ | |
12117 | if (GET_CODE (x) == REG) | |
fb5c67a7 | 12118 | fputs (reg_names[REGNO (x) + 1], file); |
9854d9ed RK |
12119 | else if (GET_CODE (x) == MEM) |
12120 | { | |
12121 | /* Handle possible auto-increment. Since it is pre-increment and | |
1427100a | 12122 | we have already done it, we can just use an offset of word. */ |
9854d9ed RK |
12123 | if (GET_CODE (XEXP (x, 0)) == PRE_INC |
12124 | || GET_CODE (XEXP (x, 0)) == PRE_DEC) | |
ed8908e7 RK |
12125 | output_address (plus_constant (XEXP (XEXP (x, 0), 0), |
12126 | UNITS_PER_WORD)); | |
6fb5fa3c DB |
12127 | else if (GET_CODE (XEXP (x, 0)) == PRE_MODIFY) |
12128 | output_address (plus_constant (XEXP (XEXP (x, 0), 0), | |
12129 | UNITS_PER_WORD)); | |
9854d9ed | 12130 | else |
d7624dc0 RK |
12131 | output_address (XEXP (adjust_address_nv (x, SImode, |
12132 | UNITS_PER_WORD), | |
12133 | 0)); | |
ed8908e7 | 12134 | |
ba5e43aa | 12135 | if (small_data_operand (x, GET_MODE (x))) |
8fbd2dc7 MM |
12136 | fprintf (file, "@%s(%s)", SMALL_DATA_RELOC, |
12137 | reg_names[SMALL_DATA_REG]); | |
9854d9ed | 12138 | } |
9878760c | 12139 | return; |
f676971a | 12140 | |
9878760c RK |
12141 | case 'm': |
12142 | /* MB value for a mask operand. */ | |
b1765bde | 12143 | if (! mask_operand (x, SImode)) |
9878760c RK |
12144 | output_operand_lossage ("invalid %%m value"); |
12145 | ||
0ba1b2ff | 12146 | fprintf (file, "%d", extract_MB (x)); |
9878760c RK |
12147 | return; |
12148 | ||
12149 | case 'M': | |
12150 | /* ME value for a mask operand. */ | |
b1765bde | 12151 | if (! mask_operand (x, SImode)) |
a260abc9 | 12152 | output_operand_lossage ("invalid %%M value"); |
9878760c | 12153 | |
0ba1b2ff | 12154 | fprintf (file, "%d", extract_ME (x)); |
9878760c RK |
12155 | return; |
12156 | ||
81eace42 GK |
12157 | /* %n outputs the negative of its operand. */ |
12158 | ||
9878760c RK |
12159 | case 'N': |
12160 | /* Write the number of elements in the vector times 4. */ | |
12161 | if (GET_CODE (x) != PARALLEL) | |
12162 | output_operand_lossage ("invalid %%N value"); | |
e2c953b6 DE |
12163 | else |
12164 | fprintf (file, "%d", XVECLEN (x, 0) * 4); | |
9878760c RK |
12165 | return; |
12166 | ||
12167 | case 'O': | |
12168 | /* Similar, but subtract 1 first. */ | |
12169 | if (GET_CODE (x) != PARALLEL) | |
1427100a | 12170 | output_operand_lossage ("invalid %%O value"); |
e2c953b6 DE |
12171 | else |
12172 | fprintf (file, "%d", (XVECLEN (x, 0) - 1) * 4); | |
9878760c RK |
12173 | return; |
12174 | ||
9854d9ed RK |
12175 | case 'p': |
12176 | /* X is a CONST_INT that is a power of two. Output the logarithm. */ | |
12177 | if (! INT_P (x) | |
2bfcf297 | 12178 | || INT_LOWPART (x) < 0 |
9854d9ed RK |
12179 | || (i = exact_log2 (INT_LOWPART (x))) < 0) |
12180 | output_operand_lossage ("invalid %%p value"); | |
e2c953b6 DE |
12181 | else |
12182 | fprintf (file, "%d", i); | |
9854d9ed RK |
12183 | return; |
12184 | ||
9878760c RK |
12185 | case 'P': |
12186 | /* The operand must be an indirect memory reference. The result | |
8bb418a3 | 12187 | is the register name. */ |
9878760c RK |
12188 | if (GET_CODE (x) != MEM || GET_CODE (XEXP (x, 0)) != REG |
12189 | || REGNO (XEXP (x, 0)) >= 32) | |
12190 | output_operand_lossage ("invalid %%P value"); | |
e2c953b6 | 12191 | else |
fb5c67a7 | 12192 | fputs (reg_names[REGNO (XEXP (x, 0))], file); |
9878760c RK |
12193 | return; |
12194 | ||
dfbdccdb GK |
12195 | case 'q': |
12196 | /* This outputs the logical code corresponding to a boolean | |
12197 | expression. The expression may have one or both operands | |
39a10a29 | 12198 | negated (if one, only the first one). For condition register |
c4ad648e AM |
12199 | logical operations, it will also treat the negated |
12200 | CR codes as NOTs, but not handle NOTs of them. */ | |
dfbdccdb | 12201 | { |
63bc1d05 | 12202 | const char *const *t = 0; |
dfbdccdb GK |
12203 | const char *s; |
12204 | enum rtx_code code = GET_CODE (x); | |
12205 | static const char * const tbl[3][3] = { | |
12206 | { "and", "andc", "nor" }, | |
12207 | { "or", "orc", "nand" }, | |
12208 | { "xor", "eqv", "xor" } }; | |
12209 | ||
12210 | if (code == AND) | |
12211 | t = tbl[0]; | |
12212 | else if (code == IOR) | |
12213 | t = tbl[1]; | |
12214 | else if (code == XOR) | |
12215 | t = tbl[2]; | |
12216 | else | |
12217 | output_operand_lossage ("invalid %%q value"); | |
12218 | ||
12219 | if (GET_CODE (XEXP (x, 0)) != NOT) | |
12220 | s = t[0]; | |
12221 | else | |
12222 | { | |
12223 | if (GET_CODE (XEXP (x, 1)) == NOT) | |
12224 | s = t[2]; | |
12225 | else | |
12226 | s = t[1]; | |
12227 | } | |
f676971a | 12228 | |
dfbdccdb GK |
12229 | fputs (s, file); |
12230 | } | |
12231 | return; | |
12232 | ||
2c4a9cff DE |
12233 | case 'Q': |
12234 | if (TARGET_MFCRF) | |
3b6ce0af | 12235 | fputc (',', file); |
5efb1046 | 12236 | /* FALLTHRU */ |
2c4a9cff DE |
12237 | else |
12238 | return; | |
12239 | ||
9854d9ed RK |
12240 | case 'R': |
12241 | /* X is a CR register. Print the mask for `mtcrf'. */ | |
12242 | if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x))) | |
12243 | output_operand_lossage ("invalid %%R value"); | |
12244 | else | |
9ebbca7d | 12245 | fprintf (file, "%d", 128 >> (REGNO (x) - CR0_REGNO)); |
9878760c | 12246 | return; |
9854d9ed RK |
12247 | |
12248 | case 's': | |
12249 | /* Low 5 bits of 32 - value */ | |
12250 | if (! INT_P (x)) | |
12251 | output_operand_lossage ("invalid %%s value"); | |
e2c953b6 DE |
12252 | else |
12253 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, (32 - INT_LOWPART (x)) & 31); | |
9878760c | 12254 | return; |
9854d9ed | 12255 | |
a260abc9 | 12256 | case 'S': |
0ba1b2ff | 12257 | /* PowerPC64 mask position. All 0's is excluded. |
a260abc9 DE |
12258 | CONST_INT 32-bit mask is considered sign-extended so any |
12259 | transition must occur within the CONST_INT, not on the boundary. */ | |
1990cd79 | 12260 | if (! mask64_operand (x, DImode)) |
a260abc9 DE |
12261 | output_operand_lossage ("invalid %%S value"); |
12262 | ||
0ba1b2ff | 12263 | uval = INT_LOWPART (x); |
a260abc9 | 12264 | |
0ba1b2ff | 12265 | if (uval & 1) /* Clear Left */ |
a260abc9 | 12266 | { |
f099d360 GK |
12267 | #if HOST_BITS_PER_WIDE_INT > 64 |
12268 | uval &= ((unsigned HOST_WIDE_INT) 1 << 64) - 1; | |
12269 | #endif | |
0ba1b2ff | 12270 | i = 64; |
a260abc9 | 12271 | } |
0ba1b2ff | 12272 | else /* Clear Right */ |
a260abc9 | 12273 | { |
0ba1b2ff | 12274 | uval = ~uval; |
f099d360 GK |
12275 | #if HOST_BITS_PER_WIDE_INT > 64 |
12276 | uval &= ((unsigned HOST_WIDE_INT) 1 << 64) - 1; | |
12277 | #endif | |
0ba1b2ff | 12278 | i = 63; |
a260abc9 | 12279 | } |
0ba1b2ff AM |
12280 | while (uval != 0) |
12281 | --i, uval >>= 1; | |
37409796 | 12282 | gcc_assert (i >= 0); |
0ba1b2ff AM |
12283 | fprintf (file, "%d", i); |
12284 | return; | |
a260abc9 | 12285 | |
a3170dc6 AH |
12286 | case 't': |
12287 | /* Like 'J' but get to the OVERFLOW/UNORDERED bit. */ | |
37409796 | 12288 | gcc_assert (GET_CODE (x) == REG && GET_MODE (x) == CCmode); |
a3170dc6 AH |
12289 | |
12290 | /* Bit 3 is OV bit. */ | |
12291 | i = 4 * (REGNO (x) - CR0_REGNO) + 3; | |
12292 | ||
12293 | /* If we want bit 31, write a shift count of zero, not 32. */ | |
12294 | fprintf (file, "%d", i == 31 ? 0 : i + 1); | |
12295 | return; | |
12296 | ||
cccf3bdc DE |
12297 | case 'T': |
12298 | /* Print the symbolic name of a branch target register. */ | |
1de43f85 DE |
12299 | if (GET_CODE (x) != REG || (REGNO (x) != LR_REGNO |
12300 | && REGNO (x) != CTR_REGNO)) | |
cccf3bdc | 12301 | output_operand_lossage ("invalid %%T value"); |
1de43f85 | 12302 | else if (REGNO (x) == LR_REGNO) |
cccf3bdc DE |
12303 | fputs (TARGET_NEW_MNEMONICS ? "lr" : "r", file); |
12304 | else | |
12305 | fputs ("ctr", file); | |
12306 | return; | |
12307 | ||
9854d9ed | 12308 | case 'u': |
802a0058 | 12309 | /* High-order 16 bits of constant for use in unsigned operand. */ |
9854d9ed RK |
12310 | if (! INT_P (x)) |
12311 | output_operand_lossage ("invalid %%u value"); | |
e2c953b6 | 12312 | else |
f676971a | 12313 | fprintf (file, HOST_WIDE_INT_PRINT_HEX, |
e2c953b6 | 12314 | (INT_LOWPART (x) >> 16) & 0xffff); |
9878760c RK |
12315 | return; |
12316 | ||
802a0058 MM |
12317 | case 'v': |
12318 | /* High-order 16 bits of constant for use in signed operand. */ | |
12319 | if (! INT_P (x)) | |
12320 | output_operand_lossage ("invalid %%v value"); | |
e2c953b6 | 12321 | else |
134c32f6 DE |
12322 | fprintf (file, HOST_WIDE_INT_PRINT_HEX, |
12323 | (INT_LOWPART (x) >> 16) & 0xffff); | |
12324 | return; | |
802a0058 | 12325 | |
9854d9ed RK |
12326 | case 'U': |
12327 | /* Print `u' if this has an auto-increment or auto-decrement. */ | |
12328 | if (GET_CODE (x) == MEM | |
12329 | && (GET_CODE (XEXP (x, 0)) == PRE_INC | |
6fb5fa3c DB |
12330 | || GET_CODE (XEXP (x, 0)) == PRE_DEC |
12331 | || GET_CODE (XEXP (x, 0)) == PRE_MODIFY)) | |
76229ac8 | 12332 | putc ('u', file); |
9854d9ed | 12333 | return; |
9878760c | 12334 | |
e0cd0770 JC |
12335 | case 'V': |
12336 | /* Print the trap code for this operand. */ | |
12337 | switch (GET_CODE (x)) | |
12338 | { | |
12339 | case EQ: | |
12340 | fputs ("eq", file); /* 4 */ | |
12341 | break; | |
12342 | case NE: | |
12343 | fputs ("ne", file); /* 24 */ | |
12344 | break; | |
12345 | case LT: | |
12346 | fputs ("lt", file); /* 16 */ | |
12347 | break; | |
12348 | case LE: | |
12349 | fputs ("le", file); /* 20 */ | |
12350 | break; | |
12351 | case GT: | |
12352 | fputs ("gt", file); /* 8 */ | |
12353 | break; | |
12354 | case GE: | |
12355 | fputs ("ge", file); /* 12 */ | |
12356 | break; | |
12357 | case LTU: | |
12358 | fputs ("llt", file); /* 2 */ | |
12359 | break; | |
12360 | case LEU: | |
12361 | fputs ("lle", file); /* 6 */ | |
12362 | break; | |
12363 | case GTU: | |
12364 | fputs ("lgt", file); /* 1 */ | |
12365 | break; | |
12366 | case GEU: | |
12367 | fputs ("lge", file); /* 5 */ | |
12368 | break; | |
12369 | default: | |
37409796 | 12370 | gcc_unreachable (); |
e0cd0770 JC |
12371 | } |
12372 | break; | |
12373 | ||
9854d9ed RK |
12374 | case 'w': |
12375 | /* If constant, low-order 16 bits of constant, signed. Otherwise, write | |
12376 | normally. */ | |
12377 | if (INT_P (x)) | |
f676971a | 12378 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, |
5f59ecb7 | 12379 | ((INT_LOWPART (x) & 0xffff) ^ 0x8000) - 0x8000); |
9854d9ed RK |
12380 | else |
12381 | print_operand (file, x, 0); | |
9878760c RK |
12382 | return; |
12383 | ||
9854d9ed | 12384 | case 'W': |
e2c953b6 | 12385 | /* MB value for a PowerPC64 rldic operand. */ |
e2c953b6 DE |
12386 | val = (GET_CODE (x) == CONST_INT |
12387 | ? INTVAL (x) : CONST_DOUBLE_HIGH (x)); | |
12388 | ||
12389 | if (val < 0) | |
12390 | i = -1; | |
9854d9ed | 12391 | else |
e2c953b6 DE |
12392 | for (i = 0; i < HOST_BITS_PER_WIDE_INT; i++) |
12393 | if ((val <<= 1) < 0) | |
12394 | break; | |
12395 | ||
12396 | #if HOST_BITS_PER_WIDE_INT == 32 | |
12397 | if (GET_CODE (x) == CONST_INT && i >= 0) | |
12398 | i += 32; /* zero-extend high-part was all 0's */ | |
12399 | else if (GET_CODE (x) == CONST_DOUBLE && i == 32) | |
12400 | { | |
12401 | val = CONST_DOUBLE_LOW (x); | |
12402 | ||
37409796 NS |
12403 | gcc_assert (val); |
12404 | if (val < 0) | |
e2c953b6 DE |
12405 | --i; |
12406 | else | |
12407 | for ( ; i < 64; i++) | |
12408 | if ((val <<= 1) < 0) | |
12409 | break; | |
12410 | } | |
12411 | #endif | |
12412 | ||
12413 | fprintf (file, "%d", i + 1); | |
9854d9ed | 12414 | return; |
9878760c | 12415 | |
9854d9ed RK |
12416 | case 'X': |
12417 | if (GET_CODE (x) == MEM | |
6fb5fa3c DB |
12418 | && (legitimate_indexed_address_p (XEXP (x, 0), 0) |
12419 | || (GET_CODE (XEXP (x, 0)) == PRE_MODIFY | |
12420 | && legitimate_indexed_address_p (XEXP (XEXP (x, 0), 1), 0)))) | |
76229ac8 | 12421 | putc ('x', file); |
9854d9ed | 12422 | return; |
9878760c | 12423 | |
9854d9ed RK |
12424 | case 'Y': |
12425 | /* Like 'L', for third word of TImode */ | |
12426 | if (GET_CODE (x) == REG) | |
fb5c67a7 | 12427 | fputs (reg_names[REGNO (x) + 2], file); |
9854d9ed | 12428 | else if (GET_CODE (x) == MEM) |
9878760c | 12429 | { |
9854d9ed RK |
12430 | if (GET_CODE (XEXP (x, 0)) == PRE_INC |
12431 | || GET_CODE (XEXP (x, 0)) == PRE_DEC) | |
a54d04b7 | 12432 | output_address (plus_constant (XEXP (XEXP (x, 0), 0), 8)); |
6fb5fa3c DB |
12433 | else if (GET_CODE (XEXP (x, 0)) == PRE_MODIFY) |
12434 | output_address (plus_constant (XEXP (XEXP (x, 0), 0), 8)); | |
9854d9ed | 12435 | else |
d7624dc0 | 12436 | output_address (XEXP (adjust_address_nv (x, SImode, 8), 0)); |
ba5e43aa | 12437 | if (small_data_operand (x, GET_MODE (x))) |
8fbd2dc7 MM |
12438 | fprintf (file, "@%s(%s)", SMALL_DATA_RELOC, |
12439 | reg_names[SMALL_DATA_REG]); | |
9878760c RK |
12440 | } |
12441 | return; | |
f676971a | 12442 | |
9878760c | 12443 | case 'z': |
b4ac57ab RS |
12444 | /* X is a SYMBOL_REF. Write out the name preceded by a |
12445 | period and without any trailing data in brackets. Used for function | |
4d30c363 MM |
12446 | names. If we are configured for System V (or the embedded ABI) on |
12447 | the PowerPC, do not emit the period, since those systems do not use | |
12448 | TOCs and the like. */ | |
37409796 | 12449 | gcc_assert (GET_CODE (x) == SYMBOL_REF); |
9878760c | 12450 | |
c4ad648e AM |
12451 | /* Mark the decl as referenced so that cgraph will output the |
12452 | function. */ | |
9bf6462a | 12453 | if (SYMBOL_REF_DECL (x)) |
c4ad648e | 12454 | mark_decl_referenced (SYMBOL_REF_DECL (x)); |
9bf6462a | 12455 | |
85b776df | 12456 | /* For macho, check to see if we need a stub. */ |
f9da97f0 AP |
12457 | if (TARGET_MACHO) |
12458 | { | |
12459 | const char *name = XSTR (x, 0); | |
a031e781 | 12460 | #if TARGET_MACHO |
3b48085e | 12461 | if (MACHOPIC_INDIRECT |
11abc112 MM |
12462 | && machopic_classify_symbol (x) == MACHOPIC_UNDEFINED_FUNCTION) |
12463 | name = machopic_indirection_name (x, /*stub_p=*/true); | |
f9da97f0 AP |
12464 | #endif |
12465 | assemble_name (file, name); | |
12466 | } | |
85b776df | 12467 | else if (!DOT_SYMBOLS) |
9739c90c | 12468 | assemble_name (file, XSTR (x, 0)); |
85b776df AM |
12469 | else |
12470 | rs6000_output_function_entry (file, XSTR (x, 0)); | |
9878760c RK |
12471 | return; |
12472 | ||
9854d9ed RK |
12473 | case 'Z': |
12474 | /* Like 'L', for last word of TImode. */ | |
12475 | if (GET_CODE (x) == REG) | |
fb5c67a7 | 12476 | fputs (reg_names[REGNO (x) + 3], file); |
9854d9ed RK |
12477 | else if (GET_CODE (x) == MEM) |
12478 | { | |
12479 | if (GET_CODE (XEXP (x, 0)) == PRE_INC | |
12480 | || GET_CODE (XEXP (x, 0)) == PRE_DEC) | |
a54d04b7 | 12481 | output_address (plus_constant (XEXP (XEXP (x, 0), 0), 12)); |
6fb5fa3c DB |
12482 | else if (GET_CODE (XEXP (x, 0)) == PRE_MODIFY) |
12483 | output_address (plus_constant (XEXP (XEXP (x, 0), 0), 12)); | |
9854d9ed | 12484 | else |
d7624dc0 | 12485 | output_address (XEXP (adjust_address_nv (x, SImode, 12), 0)); |
ba5e43aa | 12486 | if (small_data_operand (x, GET_MODE (x))) |
8fbd2dc7 MM |
12487 | fprintf (file, "@%s(%s)", SMALL_DATA_RELOC, |
12488 | reg_names[SMALL_DATA_REG]); | |
9854d9ed | 12489 | } |
5c23c401 | 12490 | return; |
0ac081f6 | 12491 | |
a3170dc6 | 12492 | /* Print AltiVec or SPE memory operand. */ |
0ac081f6 AH |
12493 | case 'y': |
12494 | { | |
12495 | rtx tmp; | |
12496 | ||
37409796 | 12497 | gcc_assert (GET_CODE (x) == MEM); |
0ac081f6 AH |
12498 | |
12499 | tmp = XEXP (x, 0); | |
12500 | ||
90d3ff1c | 12501 | /* Ugly hack because %y is overloaded. */ |
8ef65e3d | 12502 | if ((TARGET_SPE || TARGET_E500_DOUBLE) |
17caeff2 JM |
12503 | && (GET_MODE_SIZE (GET_MODE (x)) == 8 |
12504 | || GET_MODE (x) == TFmode | |
12505 | || GET_MODE (x) == TImode)) | |
a3170dc6 AH |
12506 | { |
12507 | /* Handle [reg]. */ | |
12508 | if (GET_CODE (tmp) == REG) | |
12509 | { | |
12510 | fprintf (file, "0(%s)", reg_names[REGNO (tmp)]); | |
12511 | break; | |
12512 | } | |
12513 | /* Handle [reg+UIMM]. */ | |
12514 | else if (GET_CODE (tmp) == PLUS && | |
12515 | GET_CODE (XEXP (tmp, 1)) == CONST_INT) | |
12516 | { | |
12517 | int x; | |
12518 | ||
37409796 | 12519 | gcc_assert (GET_CODE (XEXP (tmp, 0)) == REG); |
a3170dc6 AH |
12520 | |
12521 | x = INTVAL (XEXP (tmp, 1)); | |
12522 | fprintf (file, "%d(%s)", x, reg_names[REGNO (XEXP (tmp, 0))]); | |
12523 | break; | |
12524 | } | |
12525 | ||
12526 | /* Fall through. Must be [reg+reg]. */ | |
12527 | } | |
850e8d3d DN |
12528 | if (TARGET_ALTIVEC |
12529 | && GET_CODE (tmp) == AND | |
12530 | && GET_CODE (XEXP (tmp, 1)) == CONST_INT | |
12531 | && INTVAL (XEXP (tmp, 1)) == -16) | |
12532 | tmp = XEXP (tmp, 0); | |
0ac081f6 | 12533 | if (GET_CODE (tmp) == REG) |
c62f2db5 | 12534 | fprintf (file, "0,%s", reg_names[REGNO (tmp)]); |
37409796 | 12535 | else |
0ac081f6 | 12536 | { |
cb8cc791 AP |
12537 | if (!GET_CODE (tmp) == PLUS |
12538 | || !REG_P (XEXP (tmp, 0)) | |
12539 | || !REG_P (XEXP (tmp, 1))) | |
12540 | { | |
12541 | output_operand_lossage ("invalid %%y value, try using the 'Z' constraint"); | |
12542 | break; | |
12543 | } | |
bb8df8a6 | 12544 | |
0ac081f6 AH |
12545 | if (REGNO (XEXP (tmp, 0)) == 0) |
12546 | fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 1)) ], | |
12547 | reg_names[ REGNO (XEXP (tmp, 0)) ]); | |
12548 | else | |
12549 | fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 0)) ], | |
12550 | reg_names[ REGNO (XEXP (tmp, 1)) ]); | |
12551 | } | |
0ac081f6 AH |
12552 | break; |
12553 | } | |
f676971a | 12554 | |
9878760c RK |
12555 | case 0: |
12556 | if (GET_CODE (x) == REG) | |
12557 | fprintf (file, "%s", reg_names[REGNO (x)]); | |
12558 | else if (GET_CODE (x) == MEM) | |
12559 | { | |
12560 | /* We need to handle PRE_INC and PRE_DEC here, since we need to | |
12561 | know the width from the mode. */ | |
12562 | if (GET_CODE (XEXP (x, 0)) == PRE_INC) | |
79ba6d34 MM |
12563 | fprintf (file, "%d(%s)", GET_MODE_SIZE (GET_MODE (x)), |
12564 | reg_names[REGNO (XEXP (XEXP (x, 0), 0))]); | |
9878760c | 12565 | else if (GET_CODE (XEXP (x, 0)) == PRE_DEC) |
79ba6d34 MM |
12566 | fprintf (file, "%d(%s)", - GET_MODE_SIZE (GET_MODE (x)), |
12567 | reg_names[REGNO (XEXP (XEXP (x, 0), 0))]); | |
6fb5fa3c DB |
12568 | else if (GET_CODE (XEXP (x, 0)) == PRE_MODIFY) |
12569 | output_address (XEXP (XEXP (x, 0), 1)); | |
9878760c | 12570 | else |
a54d04b7 | 12571 | output_address (XEXP (x, 0)); |
9878760c RK |
12572 | } |
12573 | else | |
a54d04b7 | 12574 | output_addr_const (file, x); |
a85d226b | 12575 | return; |
9878760c | 12576 | |
c4501e62 JJ |
12577 | case '&': |
12578 | assemble_name (file, rs6000_get_some_local_dynamic_name ()); | |
12579 | return; | |
12580 | ||
9878760c RK |
12581 | default: |
12582 | output_operand_lossage ("invalid %%xn code"); | |
12583 | } | |
12584 | } | |
12585 | \f | |
12586 | /* Print the address of an operand. */ | |
12587 | ||
12588 | void | |
a2369ed3 | 12589 | print_operand_address (FILE *file, rtx x) |
9878760c RK |
12590 | { |
12591 | if (GET_CODE (x) == REG) | |
4697a36c | 12592 | fprintf (file, "0(%s)", reg_names[ REGNO (x) ]); |
9ebbca7d GK |
12593 | else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST |
12594 | || GET_CODE (x) == LABEL_REF) | |
9878760c RK |
12595 | { |
12596 | output_addr_const (file, x); | |
ba5e43aa | 12597 | if (small_data_operand (x, GET_MODE (x))) |
8fbd2dc7 MM |
12598 | fprintf (file, "@%s(%s)", SMALL_DATA_RELOC, |
12599 | reg_names[SMALL_DATA_REG]); | |
37409796 NS |
12600 | else |
12601 | gcc_assert (!TARGET_TOC); | |
9878760c RK |
12602 | } |
12603 | else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == REG) | |
12604 | { | |
9024f4b8 | 12605 | gcc_assert (REG_P (XEXP (x, 0))); |
9878760c | 12606 | if (REGNO (XEXP (x, 0)) == 0) |
4697a36c MM |
12607 | fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 1)) ], |
12608 | reg_names[ REGNO (XEXP (x, 0)) ]); | |
9878760c | 12609 | else |
4697a36c MM |
12610 | fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 0)) ], |
12611 | reg_names[ REGNO (XEXP (x, 1)) ]); | |
9878760c RK |
12612 | } |
12613 | else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT) | |
4a0a75dd KG |
12614 | fprintf (file, HOST_WIDE_INT_PRINT_DEC "(%s)", |
12615 | INTVAL (XEXP (x, 1)), reg_names[ REGNO (XEXP (x, 0)) ]); | |
3cb999d8 DE |
12616 | #if TARGET_ELF |
12617 | else if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 0)) == REG | |
c4ad648e | 12618 | && CONSTANT_P (XEXP (x, 1))) |
4697a36c MM |
12619 | { |
12620 | output_addr_const (file, XEXP (x, 1)); | |
12621 | fprintf (file, "@l(%s)", reg_names[ REGNO (XEXP (x, 0)) ]); | |
12622 | } | |
c859cda6 DJ |
12623 | #endif |
12624 | #if TARGET_MACHO | |
12625 | else if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 0)) == REG | |
c4ad648e | 12626 | && CONSTANT_P (XEXP (x, 1))) |
c859cda6 DJ |
12627 | { |
12628 | fprintf (file, "lo16("); | |
12629 | output_addr_const (file, XEXP (x, 1)); | |
12630 | fprintf (file, ")(%s)", reg_names[ REGNO (XEXP (x, 0)) ]); | |
12631 | } | |
3cb999d8 | 12632 | #endif |
4d588c14 | 12633 | else if (legitimate_constant_pool_address_p (x)) |
9ebbca7d | 12634 | { |
2e4316da | 12635 | output_addr_const (file, XEXP (x, 1)); |
9ebbca7d GK |
12636 | fprintf (file, "(%s)", reg_names[REGNO (XEXP (x, 0))]); |
12637 | } | |
9878760c | 12638 | else |
37409796 | 12639 | gcc_unreachable (); |
9878760c RK |
12640 | } |
12641 | \f | |
2e4316da RS |
12642 | /* Implement OUTPUT_ADDR_CONST_EXTRA for address X. */ |
12643 | ||
12644 | bool | |
12645 | rs6000_output_addr_const_extra (FILE *file, rtx x) | |
12646 | { | |
12647 | if (GET_CODE (x) == UNSPEC) | |
12648 | switch (XINT (x, 1)) | |
12649 | { | |
12650 | case UNSPEC_TOCREL: | |
12651 | x = XVECEXP (x, 0, 0); | |
12652 | gcc_assert (GET_CODE (x) == SYMBOL_REF); | |
12653 | output_addr_const (file, x); | |
12654 | if (!TARGET_AIX || (TARGET_ELF && TARGET_MINIMAL_TOC)) | |
12655 | { | |
12656 | putc ('-', file); | |
12657 | assemble_name (file, toc_label_name); | |
12658 | } | |
12659 | else if (TARGET_ELF) | |
12660 | fputs ("@toc", file); | |
12661 | return true; | |
08a6a74b RS |
12662 | |
12663 | #if TARGET_MACHO | |
12664 | case UNSPEC_MACHOPIC_OFFSET: | |
12665 | output_addr_const (file, XVECEXP (x, 0, 0)); | |
12666 | putc ('-', file); | |
12667 | machopic_output_function_base_name (file); | |
12668 | return true; | |
12669 | #endif | |
2e4316da RS |
12670 | } |
12671 | return false; | |
12672 | } | |
12673 | \f | |
88cad84b | 12674 | /* Target hook for assembling integer objects. The PowerPC version has |
301d03af RS |
12675 | to handle fixup entries for relocatable code if RELOCATABLE_NEEDS_FIXUP |
12676 | is defined. It also needs to handle DI-mode objects on 64-bit | |
12677 | targets. */ | |
12678 | ||
12679 | static bool | |
a2369ed3 | 12680 | rs6000_assemble_integer (rtx x, unsigned int size, int aligned_p) |
301d03af | 12681 | { |
f4f4921e | 12682 | #ifdef RELOCATABLE_NEEDS_FIXUP |
301d03af | 12683 | /* Special handling for SI values. */ |
84dcde01 | 12684 | if (RELOCATABLE_NEEDS_FIXUP && size == 4 && aligned_p) |
301d03af | 12685 | { |
301d03af | 12686 | static int recurse = 0; |
f676971a | 12687 | |
301d03af RS |
12688 | /* For -mrelocatable, we mark all addresses that need to be fixed up |
12689 | in the .fixup section. */ | |
12690 | if (TARGET_RELOCATABLE | |
d6b5193b RS |
12691 | && in_section != toc_section |
12692 | && in_section != text_section | |
4325ca90 | 12693 | && !unlikely_text_section_p (in_section) |
301d03af RS |
12694 | && !recurse |
12695 | && GET_CODE (x) != CONST_INT | |
12696 | && GET_CODE (x) != CONST_DOUBLE | |
12697 | && CONSTANT_P (x)) | |
12698 | { | |
12699 | char buf[256]; | |
12700 | ||
12701 | recurse = 1; | |
12702 | ASM_GENERATE_INTERNAL_LABEL (buf, "LCP", fixuplabelno); | |
12703 | fixuplabelno++; | |
12704 | ASM_OUTPUT_LABEL (asm_out_file, buf); | |
12705 | fprintf (asm_out_file, "\t.long\t("); | |
12706 | output_addr_const (asm_out_file, x); | |
12707 | fprintf (asm_out_file, ")@fixup\n"); | |
12708 | fprintf (asm_out_file, "\t.section\t\".fixup\",\"aw\"\n"); | |
12709 | ASM_OUTPUT_ALIGN (asm_out_file, 2); | |
12710 | fprintf (asm_out_file, "\t.long\t"); | |
12711 | assemble_name (asm_out_file, buf); | |
12712 | fprintf (asm_out_file, "\n\t.previous\n"); | |
12713 | recurse = 0; | |
12714 | return true; | |
12715 | } | |
12716 | /* Remove initial .'s to turn a -mcall-aixdesc function | |
12717 | address into the address of the descriptor, not the function | |
12718 | itself. */ | |
12719 | else if (GET_CODE (x) == SYMBOL_REF | |
12720 | && XSTR (x, 0)[0] == '.' | |
12721 | && DEFAULT_ABI == ABI_AIX) | |
12722 | { | |
12723 | const char *name = XSTR (x, 0); | |
12724 | while (*name == '.') | |
12725 | name++; | |
12726 | ||
12727 | fprintf (asm_out_file, "\t.long\t%s\n", name); | |
12728 | return true; | |
12729 | } | |
12730 | } | |
f4f4921e | 12731 | #endif /* RELOCATABLE_NEEDS_FIXUP */ |
301d03af RS |
12732 | return default_assemble_integer (x, size, aligned_p); |
12733 | } | |
93638d7a AM |
12734 | |
12735 | #ifdef HAVE_GAS_HIDDEN | |
12736 | /* Emit an assembler directive to set symbol visibility for DECL to | |
12737 | VISIBILITY_TYPE. */ | |
12738 | ||
5add3202 | 12739 | static void |
a2369ed3 | 12740 | rs6000_assemble_visibility (tree decl, int vis) |
93638d7a | 12741 | { |
93638d7a AM |
12742 | /* Functions need to have their entry point symbol visibility set as |
12743 | well as their descriptor symbol visibility. */ | |
85b776df AM |
12744 | if (DEFAULT_ABI == ABI_AIX |
12745 | && DOT_SYMBOLS | |
12746 | && TREE_CODE (decl) == FUNCTION_DECL) | |
93638d7a | 12747 | { |
25fdb4dc | 12748 | static const char * const visibility_types[] = { |
c4ad648e | 12749 | NULL, "internal", "hidden", "protected" |
25fdb4dc RH |
12750 | }; |
12751 | ||
12752 | const char *name, *type; | |
93638d7a AM |
12753 | |
12754 | name = ((* targetm.strip_name_encoding) | |
12755 | (IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl)))); | |
25fdb4dc | 12756 | type = visibility_types[vis]; |
93638d7a | 12757 | |
25fdb4dc RH |
12758 | fprintf (asm_out_file, "\t.%s\t%s\n", type, name); |
12759 | fprintf (asm_out_file, "\t.%s\t.%s\n", type, name); | |
93638d7a | 12760 | } |
25fdb4dc RH |
12761 | else |
12762 | default_assemble_visibility (decl, vis); | |
93638d7a AM |
12763 | } |
12764 | #endif | |
301d03af | 12765 | \f |
39a10a29 | 12766 | enum rtx_code |
a2369ed3 | 12767 | rs6000_reverse_condition (enum machine_mode mode, enum rtx_code code) |
39a10a29 GK |
12768 | { |
12769 | /* Reversal of FP compares takes care -- an ordered compare | |
12770 | becomes an unordered compare and vice versa. */ | |
f676971a | 12771 | if (mode == CCFPmode |
bc9ec0e0 GK |
12772 | && (!flag_finite_math_only |
12773 | || code == UNLT || code == UNLE || code == UNGT || code == UNGE | |
12774 | || code == UNEQ || code == LTGT)) | |
bab6226b | 12775 | return reverse_condition_maybe_unordered (code); |
39a10a29 | 12776 | else |
bab6226b | 12777 | return reverse_condition (code); |
39a10a29 GK |
12778 | } |
12779 | ||
39a10a29 GK |
12780 | /* Generate a compare for CODE. Return a brand-new rtx that |
12781 | represents the result of the compare. */ | |
a4f6c312 | 12782 | |
39a10a29 | 12783 | static rtx |
a2369ed3 | 12784 | rs6000_generate_compare (enum rtx_code code) |
39a10a29 GK |
12785 | { |
12786 | enum machine_mode comp_mode; | |
12787 | rtx compare_result; | |
12788 | ||
12789 | if (rs6000_compare_fp_p) | |
12790 | comp_mode = CCFPmode; | |
12791 | else if (code == GTU || code == LTU | |
c4ad648e | 12792 | || code == GEU || code == LEU) |
39a10a29 | 12793 | comp_mode = CCUNSmode; |
60934f9c NS |
12794 | else if ((code == EQ || code == NE) |
12795 | && GET_CODE (rs6000_compare_op0) == SUBREG | |
12796 | && GET_CODE (rs6000_compare_op1) == SUBREG | |
12797 | && SUBREG_PROMOTED_UNSIGNED_P (rs6000_compare_op0) | |
12798 | && SUBREG_PROMOTED_UNSIGNED_P (rs6000_compare_op1)) | |
12799 | /* These are unsigned values, perhaps there will be a later | |
12800 | ordering compare that can be shared with this one. | |
12801 | Unfortunately we cannot detect the signedness of the operands | |
12802 | for non-subregs. */ | |
12803 | comp_mode = CCUNSmode; | |
39a10a29 GK |
12804 | else |
12805 | comp_mode = CCmode; | |
12806 | ||
12807 | /* First, the compare. */ | |
12808 | compare_result = gen_reg_rtx (comp_mode); | |
a3170dc6 | 12809 | |
cef6b86c | 12810 | /* E500 FP compare instructions on the GPRs. Yuck! */ |
8ef65e3d | 12811 | if ((!TARGET_FPRS && TARGET_HARD_FLOAT) |
993f19a8 | 12812 | && rs6000_compare_fp_p) |
a3170dc6 | 12813 | { |
64022b5d | 12814 | rtx cmp, or_result, compare_result2; |
4d4cbc0e AH |
12815 | enum machine_mode op_mode = GET_MODE (rs6000_compare_op0); |
12816 | ||
12817 | if (op_mode == VOIDmode) | |
12818 | op_mode = GET_MODE (rs6000_compare_op1); | |
a3170dc6 | 12819 | |
cef6b86c EB |
12820 | /* The E500 FP compare instructions toggle the GT bit (CR bit 1) only. |
12821 | This explains the following mess. */ | |
423c1189 | 12822 | |
a3170dc6 AH |
12823 | switch (code) |
12824 | { | |
423c1189 | 12825 | case EQ: case UNEQ: case NE: case LTGT: |
37409796 NS |
12826 | switch (op_mode) |
12827 | { | |
12828 | case SFmode: | |
1cdc0d8f | 12829 | cmp = (flag_finite_math_only && !flag_trapping_math) |
37409796 NS |
12830 | ? gen_tstsfeq_gpr (compare_result, rs6000_compare_op0, |
12831 | rs6000_compare_op1) | |
12832 | : gen_cmpsfeq_gpr (compare_result, rs6000_compare_op0, | |
12833 | rs6000_compare_op1); | |
12834 | break; | |
12835 | ||
12836 | case DFmode: | |
1cdc0d8f | 12837 | cmp = (flag_finite_math_only && !flag_trapping_math) |
37409796 NS |
12838 | ? gen_tstdfeq_gpr (compare_result, rs6000_compare_op0, |
12839 | rs6000_compare_op1) | |
12840 | : gen_cmpdfeq_gpr (compare_result, rs6000_compare_op0, | |
12841 | rs6000_compare_op1); | |
12842 | break; | |
12843 | ||
17caeff2 | 12844 | case TFmode: |
1cdc0d8f | 12845 | cmp = (flag_finite_math_only && !flag_trapping_math) |
17caeff2 JM |
12846 | ? gen_tsttfeq_gpr (compare_result, rs6000_compare_op0, |
12847 | rs6000_compare_op1) | |
12848 | : gen_cmptfeq_gpr (compare_result, rs6000_compare_op0, | |
12849 | rs6000_compare_op1); | |
12850 | break; | |
12851 | ||
37409796 NS |
12852 | default: |
12853 | gcc_unreachable (); | |
12854 | } | |
a3170dc6 | 12855 | break; |
bb8df8a6 | 12856 | |
423c1189 | 12857 | case GT: case GTU: case UNGT: case UNGE: case GE: case GEU: |
37409796 NS |
12858 | switch (op_mode) |
12859 | { | |
12860 | case SFmode: | |
1cdc0d8f | 12861 | cmp = (flag_finite_math_only && !flag_trapping_math) |
37409796 NS |
12862 | ? gen_tstsfgt_gpr (compare_result, rs6000_compare_op0, |
12863 | rs6000_compare_op1) | |
12864 | : gen_cmpsfgt_gpr (compare_result, rs6000_compare_op0, | |
12865 | rs6000_compare_op1); | |
12866 | break; | |
bb8df8a6 | 12867 | |
37409796 | 12868 | case DFmode: |
1cdc0d8f | 12869 | cmp = (flag_finite_math_only && !flag_trapping_math) |
37409796 NS |
12870 | ? gen_tstdfgt_gpr (compare_result, rs6000_compare_op0, |
12871 | rs6000_compare_op1) | |
12872 | : gen_cmpdfgt_gpr (compare_result, rs6000_compare_op0, | |
12873 | rs6000_compare_op1); | |
12874 | break; | |
12875 | ||
17caeff2 | 12876 | case TFmode: |
1cdc0d8f | 12877 | cmp = (flag_finite_math_only && !flag_trapping_math) |
17caeff2 JM |
12878 | ? gen_tsttfgt_gpr (compare_result, rs6000_compare_op0, |
12879 | rs6000_compare_op1) | |
12880 | : gen_cmptfgt_gpr (compare_result, rs6000_compare_op0, | |
12881 | rs6000_compare_op1); | |
12882 | break; | |
12883 | ||
37409796 NS |
12884 | default: |
12885 | gcc_unreachable (); | |
12886 | } | |
a3170dc6 | 12887 | break; |
bb8df8a6 | 12888 | |
423c1189 | 12889 | case LT: case LTU: case UNLT: case UNLE: case LE: case LEU: |
37409796 NS |
12890 | switch (op_mode) |
12891 | { | |
12892 | case SFmode: | |
1cdc0d8f | 12893 | cmp = (flag_finite_math_only && !flag_trapping_math) |
37409796 NS |
12894 | ? gen_tstsflt_gpr (compare_result, rs6000_compare_op0, |
12895 | rs6000_compare_op1) | |
12896 | : gen_cmpsflt_gpr (compare_result, rs6000_compare_op0, | |
12897 | rs6000_compare_op1); | |
12898 | break; | |
bb8df8a6 | 12899 | |
37409796 | 12900 | case DFmode: |
1cdc0d8f | 12901 | cmp = (flag_finite_math_only && !flag_trapping_math) |
37409796 NS |
12902 | ? gen_tstdflt_gpr (compare_result, rs6000_compare_op0, |
12903 | rs6000_compare_op1) | |
12904 | : gen_cmpdflt_gpr (compare_result, rs6000_compare_op0, | |
12905 | rs6000_compare_op1); | |
12906 | break; | |
12907 | ||
17caeff2 | 12908 | case TFmode: |
1cdc0d8f | 12909 | cmp = (flag_finite_math_only && !flag_trapping_math) |
17caeff2 JM |
12910 | ? gen_tsttflt_gpr (compare_result, rs6000_compare_op0, |
12911 | rs6000_compare_op1) | |
12912 | : gen_cmptflt_gpr (compare_result, rs6000_compare_op0, | |
12913 | rs6000_compare_op1); | |
12914 | break; | |
12915 | ||
37409796 NS |
12916 | default: |
12917 | gcc_unreachable (); | |
12918 | } | |
a3170dc6 | 12919 | break; |
4d4cbc0e | 12920 | default: |
37409796 | 12921 | gcc_unreachable (); |
a3170dc6 AH |
12922 | } |
12923 | ||
12924 | /* Synthesize LE and GE from LT/GT || EQ. */ | |
12925 | if (code == LE || code == GE || code == LEU || code == GEU) | |
12926 | { | |
a3170dc6 AH |
12927 | emit_insn (cmp); |
12928 | ||
12929 | switch (code) | |
12930 | { | |
12931 | case LE: code = LT; break; | |
12932 | case GE: code = GT; break; | |
12933 | case LEU: code = LT; break; | |
12934 | case GEU: code = GT; break; | |
37409796 | 12935 | default: gcc_unreachable (); |
a3170dc6 AH |
12936 | } |
12937 | ||
a3170dc6 AH |
12938 | compare_result2 = gen_reg_rtx (CCFPmode); |
12939 | ||
12940 | /* Do the EQ. */ | |
37409796 NS |
12941 | switch (op_mode) |
12942 | { | |
12943 | case SFmode: | |
1cdc0d8f | 12944 | cmp = (flag_finite_math_only && !flag_trapping_math) |
37409796 NS |
12945 | ? gen_tstsfeq_gpr (compare_result2, rs6000_compare_op0, |
12946 | rs6000_compare_op1) | |
12947 | : gen_cmpsfeq_gpr (compare_result2, rs6000_compare_op0, | |
12948 | rs6000_compare_op1); | |
12949 | break; | |
12950 | ||
12951 | case DFmode: | |
1cdc0d8f | 12952 | cmp = (flag_finite_math_only && !flag_trapping_math) |
37409796 NS |
12953 | ? gen_tstdfeq_gpr (compare_result2, rs6000_compare_op0, |
12954 | rs6000_compare_op1) | |
12955 | : gen_cmpdfeq_gpr (compare_result2, rs6000_compare_op0, | |
12956 | rs6000_compare_op1); | |
12957 | break; | |
12958 | ||
17caeff2 | 12959 | case TFmode: |
1cdc0d8f | 12960 | cmp = (flag_finite_math_only && !flag_trapping_math) |
17caeff2 JM |
12961 | ? gen_tsttfeq_gpr (compare_result2, rs6000_compare_op0, |
12962 | rs6000_compare_op1) | |
12963 | : gen_cmptfeq_gpr (compare_result2, rs6000_compare_op0, | |
12964 | rs6000_compare_op1); | |
12965 | break; | |
12966 | ||
37409796 NS |
12967 | default: |
12968 | gcc_unreachable (); | |
12969 | } | |
a3170dc6 AH |
12970 | emit_insn (cmp); |
12971 | ||
a3170dc6 | 12972 | /* OR them together. */ |
64022b5d AH |
12973 | or_result = gen_reg_rtx (CCFPmode); |
12974 | cmp = gen_e500_cr_ior_compare (or_result, compare_result, | |
12975 | compare_result2); | |
a3170dc6 AH |
12976 | compare_result = or_result; |
12977 | code = EQ; | |
12978 | } | |
12979 | else | |
12980 | { | |
a3170dc6 | 12981 | if (code == NE || code == LTGT) |
a3170dc6 | 12982 | code = NE; |
423c1189 AH |
12983 | else |
12984 | code = EQ; | |
a3170dc6 AH |
12985 | } |
12986 | ||
12987 | emit_insn (cmp); | |
12988 | } | |
12989 | else | |
de17c25f DE |
12990 | { |
12991 | /* Generate XLC-compatible TFmode compare as PARALLEL with extra | |
12992 | CLOBBERs to match cmptf_internal2 pattern. */ | |
12993 | if (comp_mode == CCFPmode && TARGET_XL_COMPAT | |
12994 | && GET_MODE (rs6000_compare_op0) == TFmode | |
602ea4d3 | 12995 | && !TARGET_IEEEQUAD |
de17c25f DE |
12996 | && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128) |
12997 | emit_insn (gen_rtx_PARALLEL (VOIDmode, | |
12998 | gen_rtvec (9, | |
12999 | gen_rtx_SET (VOIDmode, | |
13000 | compare_result, | |
13001 | gen_rtx_COMPARE (comp_mode, | |
13002 | rs6000_compare_op0, | |
13003 | rs6000_compare_op1)), | |
13004 | gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)), | |
13005 | gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)), | |
13006 | gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)), | |
13007 | gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)), | |
13008 | gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)), | |
13009 | gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)), | |
13010 | gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)), | |
13011 | gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode))))); | |
3aebbe5f JJ |
13012 | else if (GET_CODE (rs6000_compare_op1) == UNSPEC |
13013 | && XINT (rs6000_compare_op1, 1) == UNSPEC_SP_TEST) | |
13014 | { | |
13015 | rtx op1 = XVECEXP (rs6000_compare_op1, 0, 0); | |
13016 | comp_mode = CCEQmode; | |
13017 | compare_result = gen_reg_rtx (CCEQmode); | |
13018 | if (TARGET_64BIT) | |
13019 | emit_insn (gen_stack_protect_testdi (compare_result, | |
13020 | rs6000_compare_op0, op1)); | |
13021 | else | |
13022 | emit_insn (gen_stack_protect_testsi (compare_result, | |
13023 | rs6000_compare_op0, op1)); | |
13024 | } | |
de17c25f DE |
13025 | else |
13026 | emit_insn (gen_rtx_SET (VOIDmode, compare_result, | |
13027 | gen_rtx_COMPARE (comp_mode, | |
13028 | rs6000_compare_op0, | |
13029 | rs6000_compare_op1))); | |
13030 | } | |
f676971a | 13031 | |
ca5adc63 | 13032 | /* Some kinds of FP comparisons need an OR operation; |
e7108df9 | 13033 | under flag_finite_math_only we don't bother. */ |
39a10a29 | 13034 | if (rs6000_compare_fp_p |
e7108df9 | 13035 | && !flag_finite_math_only |
8ef65e3d | 13036 | && !(TARGET_HARD_FLOAT && !TARGET_FPRS) |
39a10a29 GK |
13037 | && (code == LE || code == GE |
13038 | || code == UNEQ || code == LTGT | |
13039 | || code == UNGT || code == UNLT)) | |
13040 | { | |
13041 | enum rtx_code or1, or2; | |
13042 | rtx or1_rtx, or2_rtx, compare2_rtx; | |
13043 | rtx or_result = gen_reg_rtx (CCEQmode); | |
f676971a | 13044 | |
39a10a29 GK |
13045 | switch (code) |
13046 | { | |
13047 | case LE: or1 = LT; or2 = EQ; break; | |
13048 | case GE: or1 = GT; or2 = EQ; break; | |
13049 | case UNEQ: or1 = UNORDERED; or2 = EQ; break; | |
13050 | case LTGT: or1 = LT; or2 = GT; break; | |
13051 | case UNGT: or1 = UNORDERED; or2 = GT; break; | |
13052 | case UNLT: or1 = UNORDERED; or2 = LT; break; | |
37409796 | 13053 | default: gcc_unreachable (); |
39a10a29 GK |
13054 | } |
13055 | validate_condition_mode (or1, comp_mode); | |
13056 | validate_condition_mode (or2, comp_mode); | |
1c563bed KH |
13057 | or1_rtx = gen_rtx_fmt_ee (or1, SImode, compare_result, const0_rtx); |
13058 | or2_rtx = gen_rtx_fmt_ee (or2, SImode, compare_result, const0_rtx); | |
39a10a29 GK |
13059 | compare2_rtx = gen_rtx_COMPARE (CCEQmode, |
13060 | gen_rtx_IOR (SImode, or1_rtx, or2_rtx), | |
13061 | const_true_rtx); | |
13062 | emit_insn (gen_rtx_SET (VOIDmode, or_result, compare2_rtx)); | |
13063 | ||
13064 | compare_result = or_result; | |
13065 | code = EQ; | |
13066 | } | |
13067 | ||
13068 | validate_condition_mode (code, GET_MODE (compare_result)); | |
f676971a | 13069 | |
1c563bed | 13070 | return gen_rtx_fmt_ee (code, VOIDmode, compare_result, const0_rtx); |
39a10a29 GK |
13071 | } |
13072 | ||
13073 | ||
13074 | /* Emit the RTL for an sCOND pattern. */ | |
13075 | ||
13076 | void | |
a2369ed3 | 13077 | rs6000_emit_sCOND (enum rtx_code code, rtx result) |
39a10a29 GK |
13078 | { |
13079 | rtx condition_rtx; | |
13080 | enum machine_mode op_mode; | |
b7053a3f | 13081 | enum rtx_code cond_code; |
39a10a29 GK |
13082 | |
13083 | condition_rtx = rs6000_generate_compare (code); | |
b7053a3f GK |
13084 | cond_code = GET_CODE (condition_rtx); |
13085 | ||
8ef65e3d | 13086 | if (rs6000_compare_fp_p |
423c1189 AH |
13087 | && !TARGET_FPRS && TARGET_HARD_FLOAT) |
13088 | { | |
13089 | rtx t; | |
13090 | ||
13091 | PUT_MODE (condition_rtx, SImode); | |
13092 | t = XEXP (condition_rtx, 0); | |
13093 | ||
37409796 | 13094 | gcc_assert (cond_code == NE || cond_code == EQ); |
423c1189 AH |
13095 | |
13096 | if (cond_code == NE) | |
64022b5d | 13097 | emit_insn (gen_e500_flip_gt_bit (t, t)); |
423c1189 | 13098 | |
64022b5d | 13099 | emit_insn (gen_move_from_CR_gt_bit (result, t)); |
423c1189 AH |
13100 | return; |
13101 | } | |
13102 | ||
b7053a3f GK |
13103 | if (cond_code == NE |
13104 | || cond_code == GE || cond_code == LE | |
13105 | || cond_code == GEU || cond_code == LEU | |
13106 | || cond_code == ORDERED || cond_code == UNGE || cond_code == UNLE) | |
13107 | { | |
13108 | rtx not_result = gen_reg_rtx (CCEQmode); | |
13109 | rtx not_op, rev_cond_rtx; | |
13110 | enum machine_mode cc_mode; | |
f676971a | 13111 | |
b7053a3f GK |
13112 | cc_mode = GET_MODE (XEXP (condition_rtx, 0)); |
13113 | ||
1c563bed | 13114 | rev_cond_rtx = gen_rtx_fmt_ee (rs6000_reverse_condition (cc_mode, cond_code), |
0f4c242b | 13115 | SImode, XEXP (condition_rtx, 0), const0_rtx); |
b7053a3f GK |
13116 | not_op = gen_rtx_COMPARE (CCEQmode, rev_cond_rtx, const0_rtx); |
13117 | emit_insn (gen_rtx_SET (VOIDmode, not_result, not_op)); | |
13118 | condition_rtx = gen_rtx_EQ (VOIDmode, not_result, const0_rtx); | |
13119 | } | |
39a10a29 GK |
13120 | |
13121 | op_mode = GET_MODE (rs6000_compare_op0); | |
13122 | if (op_mode == VOIDmode) | |
13123 | op_mode = GET_MODE (rs6000_compare_op1); | |
13124 | ||
13125 | if (TARGET_POWERPC64 && (op_mode == DImode || rs6000_compare_fp_p)) | |
13126 | { | |
13127 | PUT_MODE (condition_rtx, DImode); | |
13128 | convert_move (result, condition_rtx, 0); | |
13129 | } | |
13130 | else | |
13131 | { | |
13132 | PUT_MODE (condition_rtx, SImode); | |
13133 | emit_insn (gen_rtx_SET (VOIDmode, result, condition_rtx)); | |
13134 | } | |
13135 | } | |
13136 | ||
39a10a29 GK |
13137 | /* Emit a branch of kind CODE to location LOC. */ |
13138 | ||
13139 | void | |
a2369ed3 | 13140 | rs6000_emit_cbranch (enum rtx_code code, rtx loc) |
39a10a29 GK |
13141 | { |
13142 | rtx condition_rtx, loc_ref; | |
13143 | ||
13144 | condition_rtx = rs6000_generate_compare (code); | |
13145 | loc_ref = gen_rtx_LABEL_REF (VOIDmode, loc); | |
13146 | emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, | |
13147 | gen_rtx_IF_THEN_ELSE (VOIDmode, condition_rtx, | |
13148 | loc_ref, pc_rtx))); | |
13149 | } | |
13150 | ||
12a4e8c5 GK |
13151 | /* Return the string to output a conditional branch to LABEL, which is |
13152 | the operand number of the label, or -1 if the branch is really a | |
f676971a | 13153 | conditional return. |
12a4e8c5 GK |
13154 | |
13155 | OP is the conditional expression. XEXP (OP, 0) is assumed to be a | |
13156 | condition code register and its mode specifies what kind of | |
13157 | comparison we made. | |
13158 | ||
a0ab749a | 13159 | REVERSED is nonzero if we should reverse the sense of the comparison. |
12a4e8c5 GK |
13160 | |
13161 | INSN is the insn. */ | |
13162 | ||
13163 | char * | |
a2369ed3 | 13164 | output_cbranch (rtx op, const char *label, int reversed, rtx insn) |
12a4e8c5 GK |
13165 | { |
13166 | static char string[64]; | |
13167 | enum rtx_code code = GET_CODE (op); | |
13168 | rtx cc_reg = XEXP (op, 0); | |
13169 | enum machine_mode mode = GET_MODE (cc_reg); | |
13170 | int cc_regno = REGNO (cc_reg) - CR0_REGNO; | |
39a10a29 | 13171 | int need_longbranch = label != NULL && get_attr_length (insn) == 8; |
12a4e8c5 GK |
13172 | int really_reversed = reversed ^ need_longbranch; |
13173 | char *s = string; | |
13174 | const char *ccode; | |
13175 | const char *pred; | |
13176 | rtx note; | |
13177 | ||
39a10a29 GK |
13178 | validate_condition_mode (code, mode); |
13179 | ||
13180 | /* Work out which way this really branches. We could use | |
13181 | reverse_condition_maybe_unordered here always but this | |
13182 | makes the resulting assembler clearer. */ | |
12a4e8c5 | 13183 | if (really_reversed) |
de40e1df DJ |
13184 | { |
13185 | /* Reversal of FP compares takes care -- an ordered compare | |
13186 | becomes an unordered compare and vice versa. */ | |
13187 | if (mode == CCFPmode) | |
13188 | code = reverse_condition_maybe_unordered (code); | |
13189 | else | |
13190 | code = reverse_condition (code); | |
13191 | } | |
12a4e8c5 | 13192 | |
8ef65e3d | 13193 | if ((!TARGET_FPRS && TARGET_HARD_FLOAT) && mode == CCFPmode) |
a3170dc6 AH |
13194 | { |
13195 | /* The efscmp/tst* instructions twiddle bit 2, which maps nicely | |
13196 | to the GT bit. */ | |
37409796 NS |
13197 | switch (code) |
13198 | { | |
13199 | case EQ: | |
13200 | /* Opposite of GT. */ | |
13201 | code = GT; | |
13202 | break; | |
13203 | ||
13204 | case NE: | |
13205 | code = UNLE; | |
13206 | break; | |
13207 | ||
13208 | default: | |
13209 | gcc_unreachable (); | |
13210 | } | |
a3170dc6 AH |
13211 | } |
13212 | ||
39a10a29 | 13213 | switch (code) |
12a4e8c5 GK |
13214 | { |
13215 | /* Not all of these are actually distinct opcodes, but | |
13216 | we distinguish them for clarity of the resulting assembler. */ | |
50a0b056 GK |
13217 | case NE: case LTGT: |
13218 | ccode = "ne"; break; | |
13219 | case EQ: case UNEQ: | |
13220 | ccode = "eq"; break; | |
f676971a | 13221 | case GE: case GEU: |
50a0b056 | 13222 | ccode = "ge"; break; |
f676971a | 13223 | case GT: case GTU: case UNGT: |
50a0b056 | 13224 | ccode = "gt"; break; |
f676971a | 13225 | case LE: case LEU: |
50a0b056 | 13226 | ccode = "le"; break; |
f676971a | 13227 | case LT: case LTU: case UNLT: |
50a0b056 | 13228 | ccode = "lt"; break; |
12a4e8c5 GK |
13229 | case UNORDERED: ccode = "un"; break; |
13230 | case ORDERED: ccode = "nu"; break; | |
13231 | case UNGE: ccode = "nl"; break; | |
13232 | case UNLE: ccode = "ng"; break; | |
13233 | default: | |
37409796 | 13234 | gcc_unreachable (); |
12a4e8c5 | 13235 | } |
f676971a EC |
13236 | |
13237 | /* Maybe we have a guess as to how likely the branch is. | |
94a54f47 | 13238 | The old mnemonics don't have a way to specify this information. */ |
f4857b9b | 13239 | pred = ""; |
12a4e8c5 GK |
13240 | note = find_reg_note (insn, REG_BR_PROB, NULL_RTX); |
13241 | if (note != NULL_RTX) | |
13242 | { | |
13243 | /* PROB is the difference from 50%. */ | |
13244 | int prob = INTVAL (XEXP (note, 0)) - REG_BR_PROB_BASE / 2; | |
f4857b9b AM |
13245 | |
13246 | /* Only hint for highly probable/improbable branches on newer | |
13247 | cpus as static prediction overrides processor dynamic | |
13248 | prediction. For older cpus we may as well always hint, but | |
13249 | assume not taken for branches that are very close to 50% as a | |
13250 | mispredicted taken branch is more expensive than a | |
f676971a | 13251 | mispredicted not-taken branch. */ |
ec507f2d | 13252 | if (rs6000_always_hint |
2c9e13f3 JH |
13253 | || (abs (prob) > REG_BR_PROB_BASE / 100 * 48 |
13254 | && br_prob_note_reliable_p (note))) | |
f4857b9b AM |
13255 | { |
13256 | if (abs (prob) > REG_BR_PROB_BASE / 20 | |
13257 | && ((prob > 0) ^ need_longbranch)) | |
c4ad648e | 13258 | pred = "+"; |
f4857b9b AM |
13259 | else |
13260 | pred = "-"; | |
13261 | } | |
12a4e8c5 | 13262 | } |
12a4e8c5 GK |
13263 | |
13264 | if (label == NULL) | |
94a54f47 | 13265 | s += sprintf (s, "{b%sr|b%slr%s} ", ccode, ccode, pred); |
12a4e8c5 | 13266 | else |
94a54f47 | 13267 | s += sprintf (s, "{b%s|b%s%s} ", ccode, ccode, pred); |
12a4e8c5 | 13268 | |
37c67319 | 13269 | /* We need to escape any '%' characters in the reg_names string. |
a3c9585f | 13270 | Assume they'd only be the first character.... */ |
37c67319 GK |
13271 | if (reg_names[cc_regno + CR0_REGNO][0] == '%') |
13272 | *s++ = '%'; | |
94a54f47 | 13273 | s += sprintf (s, "%s", reg_names[cc_regno + CR0_REGNO]); |
12a4e8c5 GK |
13274 | |
13275 | if (label != NULL) | |
13276 | { | |
13277 | /* If the branch distance was too far, we may have to use an | |
13278 | unconditional branch to go the distance. */ | |
13279 | if (need_longbranch) | |
44518ddd | 13280 | s += sprintf (s, ",$+8\n\tb %s", label); |
12a4e8c5 GK |
13281 | else |
13282 | s += sprintf (s, ",%s", label); | |
13283 | } | |
13284 | ||
13285 | return string; | |
13286 | } | |
50a0b056 | 13287 | |
64022b5d | 13288 | /* Return the string to flip the GT bit on a CR. */ |
423c1189 | 13289 | char * |
64022b5d | 13290 | output_e500_flip_gt_bit (rtx dst, rtx src) |
423c1189 AH |
13291 | { |
13292 | static char string[64]; | |
13293 | int a, b; | |
13294 | ||
37409796 NS |
13295 | gcc_assert (GET_CODE (dst) == REG && CR_REGNO_P (REGNO (dst)) |
13296 | && GET_CODE (src) == REG && CR_REGNO_P (REGNO (src))); | |
423c1189 | 13297 | |
64022b5d AH |
13298 | /* GT bit. */ |
13299 | a = 4 * (REGNO (dst) - CR0_REGNO) + 1; | |
13300 | b = 4 * (REGNO (src) - CR0_REGNO) + 1; | |
423c1189 AH |
13301 | |
13302 | sprintf (string, "crnot %d,%d", a, b); | |
13303 | return string; | |
13304 | } | |
13305 | ||
21213b4c DP |
13306 | /* Return insn index for the vector compare instruction for given CODE, |
13307 | and DEST_MODE, OP_MODE. Return INSN_NOT_AVAILABLE if valid insn is | |
13308 | not available. */ | |
13309 | ||
13310 | static int | |
94ff898d | 13311 | get_vec_cmp_insn (enum rtx_code code, |
21213b4c DP |
13312 | enum machine_mode dest_mode, |
13313 | enum machine_mode op_mode) | |
13314 | { | |
13315 | if (!TARGET_ALTIVEC) | |
13316 | return INSN_NOT_AVAILABLE; | |
13317 | ||
13318 | switch (code) | |
13319 | { | |
13320 | case EQ: | |
13321 | if (dest_mode == V16QImode && op_mode == V16QImode) | |
13322 | return UNSPEC_VCMPEQUB; | |
13323 | if (dest_mode == V8HImode && op_mode == V8HImode) | |
13324 | return UNSPEC_VCMPEQUH; | |
13325 | if (dest_mode == V4SImode && op_mode == V4SImode) | |
13326 | return UNSPEC_VCMPEQUW; | |
13327 | if (dest_mode == V4SImode && op_mode == V4SFmode) | |
13328 | return UNSPEC_VCMPEQFP; | |
13329 | break; | |
13330 | case GE: | |
13331 | if (dest_mode == V4SImode && op_mode == V4SFmode) | |
13332 | return UNSPEC_VCMPGEFP; | |
13333 | case GT: | |
13334 | if (dest_mode == V16QImode && op_mode == V16QImode) | |
13335 | return UNSPEC_VCMPGTSB; | |
13336 | if (dest_mode == V8HImode && op_mode == V8HImode) | |
13337 | return UNSPEC_VCMPGTSH; | |
13338 | if (dest_mode == V4SImode && op_mode == V4SImode) | |
13339 | return UNSPEC_VCMPGTSW; | |
13340 | if (dest_mode == V4SImode && op_mode == V4SFmode) | |
13341 | return UNSPEC_VCMPGTFP; | |
13342 | break; | |
13343 | case GTU: | |
13344 | if (dest_mode == V16QImode && op_mode == V16QImode) | |
13345 | return UNSPEC_VCMPGTUB; | |
13346 | if (dest_mode == V8HImode && op_mode == V8HImode) | |
13347 | return UNSPEC_VCMPGTUH; | |
13348 | if (dest_mode == V4SImode && op_mode == V4SImode) | |
13349 | return UNSPEC_VCMPGTUW; | |
13350 | break; | |
13351 | default: | |
13352 | break; | |
13353 | } | |
13354 | return INSN_NOT_AVAILABLE; | |
13355 | } | |
13356 | ||
13357 | /* Emit vector compare for operands OP0 and OP1 using code RCODE. | |
13358 | DMODE is expected destination mode. This is a recursive function. */ | |
13359 | ||
13360 | static rtx | |
13361 | rs6000_emit_vector_compare (enum rtx_code rcode, | |
13362 | rtx op0, rtx op1, | |
13363 | enum machine_mode dmode) | |
13364 | { | |
13365 | int vec_cmp_insn; | |
13366 | rtx mask; | |
13367 | enum machine_mode dest_mode; | |
13368 | enum machine_mode op_mode = GET_MODE (op1); | |
13369 | ||
37409796 NS |
13370 | gcc_assert (TARGET_ALTIVEC); |
13371 | gcc_assert (GET_MODE (op0) == GET_MODE (op1)); | |
21213b4c DP |
13372 | |
13373 | /* Floating point vector compare instructions uses destination V4SImode. | |
13374 | Move destination to appropriate mode later. */ | |
13375 | if (dmode == V4SFmode) | |
13376 | dest_mode = V4SImode; | |
13377 | else | |
13378 | dest_mode = dmode; | |
13379 | ||
13380 | mask = gen_reg_rtx (dest_mode); | |
13381 | vec_cmp_insn = get_vec_cmp_insn (rcode, dest_mode, op_mode); | |
13382 | ||
13383 | if (vec_cmp_insn == INSN_NOT_AVAILABLE) | |
13384 | { | |
13385 | bool swap_operands = false; | |
13386 | bool try_again = false; | |
13387 | switch (rcode) | |
13388 | { | |
13389 | case LT: | |
13390 | rcode = GT; | |
13391 | swap_operands = true; | |
13392 | try_again = true; | |
13393 | break; | |
13394 | case LTU: | |
13395 | rcode = GTU; | |
13396 | swap_operands = true; | |
13397 | try_again = true; | |
13398 | break; | |
13399 | case NE: | |
370df7db JC |
13400 | case UNLE: |
13401 | case UNLT: | |
13402 | case UNGE: | |
13403 | case UNGT: | |
13404 | /* Invert condition and try again. | |
13405 | e.g., A != B becomes ~(A==B). */ | |
21213b4c | 13406 | { |
370df7db | 13407 | enum rtx_code rev_code; |
21213b4c | 13408 | enum insn_code nor_code; |
d1123cde | 13409 | rtx eq_rtx; |
370df7db JC |
13410 | |
13411 | rev_code = reverse_condition_maybe_unordered (rcode); | |
d1123cde MS |
13412 | eq_rtx = rs6000_emit_vector_compare (rev_code, op0, op1, |
13413 | dest_mode); | |
94ff898d | 13414 | |
166cdb08 | 13415 | nor_code = optab_handler (one_cmpl_optab, (int)dest_mode)->insn_code; |
37409796 | 13416 | gcc_assert (nor_code != CODE_FOR_nothing); |
21213b4c DP |
13417 | emit_insn (GEN_FCN (nor_code) (mask, eq_rtx)); |
13418 | ||
13419 | if (dmode != dest_mode) | |
13420 | { | |
13421 | rtx temp = gen_reg_rtx (dest_mode); | |
13422 | convert_move (temp, mask, 0); | |
13423 | return temp; | |
13424 | } | |
13425 | return mask; | |
13426 | } | |
13427 | break; | |
13428 | case GE: | |
13429 | case GEU: | |
13430 | case LE: | |
13431 | case LEU: | |
13432 | /* Try GT/GTU/LT/LTU OR EQ */ | |
13433 | { | |
13434 | rtx c_rtx, eq_rtx; | |
13435 | enum insn_code ior_code; | |
13436 | enum rtx_code new_code; | |
13437 | ||
37409796 NS |
13438 | switch (rcode) |
13439 | { | |
13440 | case GE: | |
13441 | new_code = GT; | |
13442 | break; | |
13443 | ||
13444 | case GEU: | |
13445 | new_code = GTU; | |
13446 | break; | |
13447 | ||
13448 | case LE: | |
13449 | new_code = LT; | |
13450 | break; | |
13451 | ||
13452 | case LEU: | |
13453 | new_code = LTU; | |
13454 | break; | |
13455 | ||
13456 | default: | |
13457 | gcc_unreachable (); | |
13458 | } | |
21213b4c DP |
13459 | |
13460 | c_rtx = rs6000_emit_vector_compare (new_code, | |
13461 | op0, op1, dest_mode); | |
13462 | eq_rtx = rs6000_emit_vector_compare (EQ, op0, op1, | |
13463 | dest_mode); | |
13464 | ||
166cdb08 | 13465 | ior_code = optab_handler (ior_optab, (int)dest_mode)->insn_code; |
37409796 | 13466 | gcc_assert (ior_code != CODE_FOR_nothing); |
21213b4c DP |
13467 | emit_insn (GEN_FCN (ior_code) (mask, c_rtx, eq_rtx)); |
13468 | if (dmode != dest_mode) | |
13469 | { | |
13470 | rtx temp = gen_reg_rtx (dest_mode); | |
13471 | convert_move (temp, mask, 0); | |
13472 | return temp; | |
13473 | } | |
13474 | return mask; | |
13475 | } | |
13476 | break; | |
13477 | default: | |
37409796 | 13478 | gcc_unreachable (); |
21213b4c DP |
13479 | } |
13480 | ||
13481 | if (try_again) | |
13482 | { | |
13483 | vec_cmp_insn = get_vec_cmp_insn (rcode, dest_mode, op_mode); | |
37409796 NS |
13484 | /* You only get two chances. */ |
13485 | gcc_assert (vec_cmp_insn != INSN_NOT_AVAILABLE); | |
21213b4c DP |
13486 | } |
13487 | ||
13488 | if (swap_operands) | |
13489 | { | |
13490 | rtx tmp; | |
13491 | tmp = op0; | |
13492 | op0 = op1; | |
13493 | op1 = tmp; | |
13494 | } | |
13495 | } | |
13496 | ||
915167f5 GK |
13497 | emit_insn (gen_rtx_SET (VOIDmode, mask, |
13498 | gen_rtx_UNSPEC (dest_mode, | |
13499 | gen_rtvec (2, op0, op1), | |
13500 | vec_cmp_insn))); | |
21213b4c DP |
13501 | if (dmode != dest_mode) |
13502 | { | |
13503 | rtx temp = gen_reg_rtx (dest_mode); | |
13504 | convert_move (temp, mask, 0); | |
13505 | return temp; | |
13506 | } | |
13507 | return mask; | |
13508 | } | |
13509 | ||
13510 | /* Return vector select instruction for MODE. Return INSN_NOT_AVAILABLE, if | |
13511 | valid insn doesn exist for given mode. */ | |
13512 | ||
13513 | static int | |
13514 | get_vsel_insn (enum machine_mode mode) | |
13515 | { | |
13516 | switch (mode) | |
13517 | { | |
13518 | case V4SImode: | |
13519 | return UNSPEC_VSEL4SI; | |
13520 | break; | |
13521 | case V4SFmode: | |
13522 | return UNSPEC_VSEL4SF; | |
13523 | break; | |
13524 | case V8HImode: | |
13525 | return UNSPEC_VSEL8HI; | |
13526 | break; | |
13527 | case V16QImode: | |
13528 | return UNSPEC_VSEL16QI; | |
13529 | break; | |
13530 | default: | |
13531 | return INSN_NOT_AVAILABLE; | |
13532 | break; | |
13533 | } | |
13534 | return INSN_NOT_AVAILABLE; | |
13535 | } | |
13536 | ||
13537 | /* Emit vector select insn where DEST is destination using | |
13538 | operands OP1, OP2 and MASK. */ | |
13539 | ||
13540 | static void | |
13541 | rs6000_emit_vector_select (rtx dest, rtx op1, rtx op2, rtx mask) | |
13542 | { | |
13543 | rtx t, temp; | |
13544 | enum machine_mode dest_mode = GET_MODE (dest); | |
13545 | int vsel_insn_index = get_vsel_insn (GET_MODE (dest)); | |
13546 | ||
13547 | temp = gen_reg_rtx (dest_mode); | |
94ff898d | 13548 | |
bb8df8a6 | 13549 | /* For each vector element, select op1 when mask is 1 otherwise |
19f1ebc7 | 13550 | select op2. */ |
915167f5 GK |
13551 | t = gen_rtx_SET (VOIDmode, temp, |
13552 | gen_rtx_UNSPEC (dest_mode, | |
13553 | gen_rtvec (3, op2, op1, mask), | |
13554 | vsel_insn_index)); | |
21213b4c DP |
13555 | emit_insn (t); |
13556 | emit_move_insn (dest, temp); | |
13557 | return; | |
13558 | } | |
13559 | ||
94ff898d | 13560 | /* Emit vector conditional expression. |
21213b4c DP |
13561 | DEST is destination. OP1 and OP2 are two VEC_COND_EXPR operands. |
13562 | CC_OP0 and CC_OP1 are the two operands for the relation operation COND. */ | |
13563 | ||
13564 | int | |
13565 | rs6000_emit_vector_cond_expr (rtx dest, rtx op1, rtx op2, | |
13566 | rtx cond, rtx cc_op0, rtx cc_op1) | |
13567 | { | |
13568 | enum machine_mode dest_mode = GET_MODE (dest); | |
13569 | enum rtx_code rcode = GET_CODE (cond); | |
13570 | rtx mask; | |
13571 | ||
13572 | if (!TARGET_ALTIVEC) | |
13573 | return 0; | |
13574 | ||
13575 | /* Get the vector mask for the given relational operations. */ | |
13576 | mask = rs6000_emit_vector_compare (rcode, cc_op0, cc_op1, dest_mode); | |
13577 | ||
13578 | rs6000_emit_vector_select (dest, op1, op2, mask); | |
13579 | ||
13580 | return 1; | |
13581 | } | |
13582 | ||
50a0b056 GK |
13583 | /* Emit a conditional move: move TRUE_COND to DEST if OP of the |
13584 | operands of the last comparison is nonzero/true, FALSE_COND if it | |
13585 | is zero/false. Return 0 if the hardware has no such operation. */ | |
a4f6c312 | 13586 | |
50a0b056 | 13587 | int |
a2369ed3 | 13588 | rs6000_emit_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond) |
50a0b056 GK |
13589 | { |
13590 | enum rtx_code code = GET_CODE (op); | |
13591 | rtx op0 = rs6000_compare_op0; | |
13592 | rtx op1 = rs6000_compare_op1; | |
13593 | REAL_VALUE_TYPE c1; | |
3148ad6d DJ |
13594 | enum machine_mode compare_mode = GET_MODE (op0); |
13595 | enum machine_mode result_mode = GET_MODE (dest); | |
50a0b056 | 13596 | rtx temp; |
add2402e | 13597 | bool is_against_zero; |
50a0b056 | 13598 | |
a3c9585f | 13599 | /* These modes should always match. */ |
a3170dc6 AH |
13600 | if (GET_MODE (op1) != compare_mode |
13601 | /* In the isel case however, we can use a compare immediate, so | |
13602 | op1 may be a small constant. */ | |
13603 | && (!TARGET_ISEL || !short_cint_operand (op1, VOIDmode))) | |
3148ad6d | 13604 | return 0; |
178c3eff | 13605 | if (GET_MODE (true_cond) != result_mode) |
3148ad6d | 13606 | return 0; |
178c3eff | 13607 | if (GET_MODE (false_cond) != result_mode) |
3148ad6d DJ |
13608 | return 0; |
13609 | ||
50a0b056 | 13610 | /* First, work out if the hardware can do this at all, or |
a3c9585f | 13611 | if it's too slow.... */ |
50a0b056 | 13612 | if (! rs6000_compare_fp_p) |
a3170dc6 AH |
13613 | { |
13614 | if (TARGET_ISEL) | |
13615 | return rs6000_emit_int_cmove (dest, op, true_cond, false_cond); | |
13616 | return 0; | |
13617 | } | |
8ef65e3d | 13618 | else if (TARGET_HARD_FLOAT && !TARGET_FPRS |
ebb109ad | 13619 | && SCALAR_FLOAT_MODE_P (compare_mode)) |
fef98bf2 | 13620 | return 0; |
50a0b056 | 13621 | |
add2402e | 13622 | is_against_zero = op1 == CONST0_RTX (compare_mode); |
94ff898d | 13623 | |
add2402e GK |
13624 | /* A floating-point subtract might overflow, underflow, or produce |
13625 | an inexact result, thus changing the floating-point flags, so it | |
13626 | can't be generated if we care about that. It's safe if one side | |
13627 | of the construct is zero, since then no subtract will be | |
13628 | generated. */ | |
ebb109ad | 13629 | if (SCALAR_FLOAT_MODE_P (compare_mode) |
add2402e GK |
13630 | && flag_trapping_math && ! is_against_zero) |
13631 | return 0; | |
13632 | ||
50a0b056 GK |
13633 | /* Eliminate half of the comparisons by switching operands, this |
13634 | makes the remaining code simpler. */ | |
13635 | if (code == UNLT || code == UNGT || code == UNORDERED || code == NE | |
bc9ec0e0 | 13636 | || code == LTGT || code == LT || code == UNLE) |
50a0b056 GK |
13637 | { |
13638 | code = reverse_condition_maybe_unordered (code); | |
13639 | temp = true_cond; | |
13640 | true_cond = false_cond; | |
13641 | false_cond = temp; | |
13642 | } | |
13643 | ||
13644 | /* UNEQ and LTGT take four instructions for a comparison with zero, | |
13645 | it'll probably be faster to use a branch here too. */ | |
bc9ec0e0 | 13646 | if (code == UNEQ && HONOR_NANS (compare_mode)) |
50a0b056 | 13647 | return 0; |
f676971a | 13648 | |
50a0b056 GK |
13649 | if (GET_CODE (op1) == CONST_DOUBLE) |
13650 | REAL_VALUE_FROM_CONST_DOUBLE (c1, op1); | |
f676971a | 13651 | |
b6d08ca1 | 13652 | /* We're going to try to implement comparisons by performing |
50a0b056 GK |
13653 | a subtract, then comparing against zero. Unfortunately, |
13654 | Inf - Inf is NaN which is not zero, and so if we don't | |
27d30956 | 13655 | know that the operand is finite and the comparison |
50a0b056 | 13656 | would treat EQ different to UNORDERED, we can't do it. */ |
bc9ec0e0 | 13657 | if (HONOR_INFINITIES (compare_mode) |
50a0b056 | 13658 | && code != GT && code != UNGE |
045572c7 | 13659 | && (GET_CODE (op1) != CONST_DOUBLE || real_isinf (&c1)) |
50a0b056 GK |
13660 | /* Constructs of the form (a OP b ? a : b) are safe. */ |
13661 | && ((! rtx_equal_p (op0, false_cond) && ! rtx_equal_p (op1, false_cond)) | |
f676971a | 13662 | || (! rtx_equal_p (op0, true_cond) |
50a0b056 GK |
13663 | && ! rtx_equal_p (op1, true_cond)))) |
13664 | return 0; | |
add2402e | 13665 | |
50a0b056 GK |
13666 | /* At this point we know we can use fsel. */ |
13667 | ||
13668 | /* Reduce the comparison to a comparison against zero. */ | |
add2402e GK |
13669 | if (! is_against_zero) |
13670 | { | |
13671 | temp = gen_reg_rtx (compare_mode); | |
13672 | emit_insn (gen_rtx_SET (VOIDmode, temp, | |
13673 | gen_rtx_MINUS (compare_mode, op0, op1))); | |
13674 | op0 = temp; | |
13675 | op1 = CONST0_RTX (compare_mode); | |
13676 | } | |
50a0b056 GK |
13677 | |
13678 | /* If we don't care about NaNs we can reduce some of the comparisons | |
13679 | down to faster ones. */ | |
bc9ec0e0 | 13680 | if (! HONOR_NANS (compare_mode)) |
50a0b056 GK |
13681 | switch (code) |
13682 | { | |
13683 | case GT: | |
13684 | code = LE; | |
13685 | temp = true_cond; | |
13686 | true_cond = false_cond; | |
13687 | false_cond = temp; | |
13688 | break; | |
13689 | case UNGE: | |
13690 | code = GE; | |
13691 | break; | |
13692 | case UNEQ: | |
13693 | code = EQ; | |
13694 | break; | |
13695 | default: | |
13696 | break; | |
13697 | } | |
13698 | ||
13699 | /* Now, reduce everything down to a GE. */ | |
13700 | switch (code) | |
13701 | { | |
13702 | case GE: | |
13703 | break; | |
13704 | ||
13705 | case LE: | |
3148ad6d DJ |
13706 | temp = gen_reg_rtx (compare_mode); |
13707 | emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0))); | |
50a0b056 GK |
13708 | op0 = temp; |
13709 | break; | |
13710 | ||
13711 | case ORDERED: | |
3148ad6d DJ |
13712 | temp = gen_reg_rtx (compare_mode); |
13713 | emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_ABS (compare_mode, op0))); | |
50a0b056 GK |
13714 | op0 = temp; |
13715 | break; | |
13716 | ||
13717 | case EQ: | |
3148ad6d | 13718 | temp = gen_reg_rtx (compare_mode); |
f676971a | 13719 | emit_insn (gen_rtx_SET (VOIDmode, temp, |
3148ad6d DJ |
13720 | gen_rtx_NEG (compare_mode, |
13721 | gen_rtx_ABS (compare_mode, op0)))); | |
50a0b056 GK |
13722 | op0 = temp; |
13723 | break; | |
13724 | ||
13725 | case UNGE: | |
bc9ec0e0 | 13726 | /* a UNGE 0 <-> (a GE 0 || -a UNLT 0) */ |
3148ad6d | 13727 | temp = gen_reg_rtx (result_mode); |
50a0b056 | 13728 | emit_insn (gen_rtx_SET (VOIDmode, temp, |
3148ad6d | 13729 | gen_rtx_IF_THEN_ELSE (result_mode, |
50a0b056 GK |
13730 | gen_rtx_GE (VOIDmode, |
13731 | op0, op1), | |
13732 | true_cond, false_cond))); | |
bc9ec0e0 GK |
13733 | false_cond = true_cond; |
13734 | true_cond = temp; | |
50a0b056 | 13735 | |
3148ad6d DJ |
13736 | temp = gen_reg_rtx (compare_mode); |
13737 | emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0))); | |
50a0b056 GK |
13738 | op0 = temp; |
13739 | break; | |
13740 | ||
13741 | case GT: | |
bc9ec0e0 | 13742 | /* a GT 0 <-> (a GE 0 && -a UNLT 0) */ |
3148ad6d | 13743 | temp = gen_reg_rtx (result_mode); |
50a0b056 | 13744 | emit_insn (gen_rtx_SET (VOIDmode, temp, |
f676971a | 13745 | gen_rtx_IF_THEN_ELSE (result_mode, |
50a0b056 GK |
13746 | gen_rtx_GE (VOIDmode, |
13747 | op0, op1), | |
13748 | true_cond, false_cond))); | |
bc9ec0e0 GK |
13749 | true_cond = false_cond; |
13750 | false_cond = temp; | |
50a0b056 | 13751 | |
3148ad6d DJ |
13752 | temp = gen_reg_rtx (compare_mode); |
13753 | emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0))); | |
50a0b056 GK |
13754 | op0 = temp; |
13755 | break; | |
13756 | ||
13757 | default: | |
37409796 | 13758 | gcc_unreachable (); |
50a0b056 GK |
13759 | } |
13760 | ||
13761 | emit_insn (gen_rtx_SET (VOIDmode, dest, | |
3148ad6d | 13762 | gen_rtx_IF_THEN_ELSE (result_mode, |
50a0b056 GK |
13763 | gen_rtx_GE (VOIDmode, |
13764 | op0, op1), | |
13765 | true_cond, false_cond))); | |
13766 | return 1; | |
13767 | } | |
13768 | ||
a3170dc6 AH |
13769 | /* Same as above, but for ints (isel). */ |
13770 | ||
13771 | static int | |
a2369ed3 | 13772 | rs6000_emit_int_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond) |
a3170dc6 AH |
13773 | { |
13774 | rtx condition_rtx, cr; | |
13775 | ||
13776 | /* All isel implementations thus far are 32-bits. */ | |
13777 | if (GET_MODE (rs6000_compare_op0) != SImode) | |
13778 | return 0; | |
13779 | ||
13780 | /* We still have to do the compare, because isel doesn't do a | |
13781 | compare, it just looks at the CRx bits set by a previous compare | |
13782 | instruction. */ | |
13783 | condition_rtx = rs6000_generate_compare (GET_CODE (op)); | |
13784 | cr = XEXP (condition_rtx, 0); | |
13785 | ||
13786 | if (GET_MODE (cr) == CCmode) | |
13787 | emit_insn (gen_isel_signed (dest, condition_rtx, | |
13788 | true_cond, false_cond, cr)); | |
13789 | else | |
13790 | emit_insn (gen_isel_unsigned (dest, condition_rtx, | |
13791 | true_cond, false_cond, cr)); | |
13792 | ||
13793 | return 1; | |
13794 | } | |
13795 | ||
13796 | const char * | |
a2369ed3 | 13797 | output_isel (rtx *operands) |
a3170dc6 AH |
13798 | { |
13799 | enum rtx_code code; | |
13800 | ||
13801 | code = GET_CODE (operands[1]); | |
13802 | if (code == GE || code == GEU || code == LE || code == LEU || code == NE) | |
13803 | { | |
13804 | PUT_CODE (operands[1], reverse_condition (code)); | |
13805 | return "isel %0,%3,%2,%j1"; | |
13806 | } | |
13807 | else | |
13808 | return "isel %0,%2,%3,%j1"; | |
13809 | } | |
13810 | ||
50a0b056 | 13811 | void |
a2369ed3 | 13812 | rs6000_emit_minmax (rtx dest, enum rtx_code code, rtx op0, rtx op1) |
50a0b056 GK |
13813 | { |
13814 | enum machine_mode mode = GET_MODE (op0); | |
5dc8d536 | 13815 | enum rtx_code c; |
50a0b056 | 13816 | rtx target; |
5dc8d536 AH |
13817 | |
13818 | if (code == SMAX || code == SMIN) | |
13819 | c = GE; | |
13820 | else | |
13821 | c = GEU; | |
13822 | ||
50a0b056 | 13823 | if (code == SMAX || code == UMAX) |
f676971a | 13824 | target = emit_conditional_move (dest, c, op0, op1, mode, |
50a0b056 GK |
13825 | op0, op1, mode, 0); |
13826 | else | |
f676971a | 13827 | target = emit_conditional_move (dest, c, op0, op1, mode, |
50a0b056 | 13828 | op1, op0, mode, 0); |
37409796 | 13829 | gcc_assert (target); |
50a0b056 GK |
13830 | if (target != dest) |
13831 | emit_move_insn (dest, target); | |
13832 | } | |
46c07df8 | 13833 | |
915167f5 GK |
13834 | /* Emit instructions to perform a load-reserved/store-conditional operation. |
13835 | The operation performed is an atomic | |
13836 | (set M (CODE:MODE M OP)) | |
13837 | If not NULL, BEFORE is atomically set to M before the operation, and | |
13838 | AFTER is set to M after the operation (that is, (CODE:MODE M OP)). | |
bb8df8a6 | 13839 | If SYNC_P then a memory barrier is emitted before the operation. |
915167f5 GK |
13840 | Either OP or M may be wrapped in a NOT operation. */ |
13841 | ||
13842 | void | |
13843 | rs6000_emit_sync (enum rtx_code code, enum machine_mode mode, | |
13844 | rtx m, rtx op, rtx before_param, rtx after_param, | |
13845 | bool sync_p) | |
13846 | { | |
13847 | enum machine_mode used_mode; | |
13848 | rtx the_op, set_before, set_after, set_atomic, cc_scratch, before, after; | |
13849 | rtx used_m; | |
13850 | rtvec vec; | |
13851 | HOST_WIDE_INT imask = GET_MODE_MASK (mode); | |
13852 | rtx shift = NULL_RTX; | |
bb8df8a6 | 13853 | |
915167f5 | 13854 | if (sync_p) |
a3cb4b82 | 13855 | emit_insn (gen_lwsync ()); |
bb8df8a6 | 13856 | |
915167f5 GK |
13857 | used_m = m; |
13858 | ||
13859 | /* If this is smaller than SImode, we'll have to use SImode with | |
13860 | adjustments. */ | |
13861 | if (mode == QImode || mode == HImode) | |
13862 | { | |
13863 | rtx newop, oldop; | |
13864 | ||
13865 | if (MEM_ALIGN (used_m) >= 32) | |
13866 | { | |
13867 | int ishift = 0; | |
13868 | if (BYTES_BIG_ENDIAN) | |
13869 | ishift = GET_MODE_BITSIZE (SImode) - GET_MODE_BITSIZE (mode); | |
bb8df8a6 | 13870 | |
915167f5 | 13871 | shift = GEN_INT (ishift); |
c75c6d11 | 13872 | used_m = change_address (used_m, SImode, 0); |
915167f5 GK |
13873 | } |
13874 | else | |
13875 | { | |
13876 | rtx addrSI, aligned_addr; | |
a9c9d3fa | 13877 | int shift_mask = mode == QImode ? 0x18 : 0x10; |
bb8df8a6 | 13878 | |
c75c6d11 JJ |
13879 | addrSI = gen_lowpart_common (SImode, |
13880 | force_reg (Pmode, XEXP (used_m, 0))); | |
13881 | addrSI = force_reg (SImode, addrSI); | |
915167f5 GK |
13882 | shift = gen_reg_rtx (SImode); |
13883 | ||
13884 | emit_insn (gen_rlwinm (shift, addrSI, GEN_INT (3), | |
a9c9d3fa GK |
13885 | GEN_INT (shift_mask))); |
13886 | emit_insn (gen_xorsi3 (shift, shift, GEN_INT (shift_mask))); | |
915167f5 GK |
13887 | |
13888 | aligned_addr = expand_binop (Pmode, and_optab, | |
13889 | XEXP (used_m, 0), | |
13890 | GEN_INT (-4), NULL_RTX, | |
13891 | 1, OPTAB_LIB_WIDEN); | |
13892 | used_m = change_address (used_m, SImode, aligned_addr); | |
13893 | set_mem_align (used_m, 32); | |
915167f5 | 13894 | } |
c75c6d11 JJ |
13895 | /* It's safe to keep the old alias set of USED_M, because |
13896 | the operation is atomic and only affects the original | |
13897 | USED_M. */ | |
f66f9865 | 13898 | m = used_m; |
915167f5 GK |
13899 | |
13900 | if (GET_CODE (op) == NOT) | |
13901 | { | |
13902 | oldop = lowpart_subreg (SImode, XEXP (op, 0), mode); | |
13903 | oldop = gen_rtx_NOT (SImode, oldop); | |
13904 | } | |
13905 | else | |
13906 | oldop = lowpart_subreg (SImode, op, mode); | |
9f0076e5 | 13907 | |
915167f5 GK |
13908 | switch (code) |
13909 | { | |
13910 | case IOR: | |
13911 | case XOR: | |
13912 | newop = expand_binop (SImode, and_optab, | |
13913 | oldop, GEN_INT (imask), NULL_RTX, | |
13914 | 1, OPTAB_LIB_WIDEN); | |
13915 | emit_insn (gen_ashlsi3 (newop, newop, shift)); | |
13916 | break; | |
13917 | ||
f66f9865 DE |
13918 | case NOT: /* NAND */ |
13919 | newop = expand_binop (SImode, ior_optab, | |
13920 | oldop, GEN_INT (~imask), NULL_RTX, | |
13921 | 1, OPTAB_LIB_WIDEN); | |
13922 | emit_insn (gen_rotlsi3 (newop, newop, shift)); | |
13923 | break; | |
13924 | ||
915167f5 GK |
13925 | case AND: |
13926 | newop = expand_binop (SImode, ior_optab, | |
13927 | oldop, GEN_INT (~imask), NULL_RTX, | |
13928 | 1, OPTAB_LIB_WIDEN); | |
a9c9d3fa | 13929 | emit_insn (gen_rotlsi3 (newop, newop, shift)); |
915167f5 GK |
13930 | break; |
13931 | ||
13932 | case PLUS: | |
9f0076e5 | 13933 | case MINUS: |
915167f5 GK |
13934 | { |
13935 | rtx mask; | |
bb8df8a6 | 13936 | |
915167f5 GK |
13937 | newop = expand_binop (SImode, and_optab, |
13938 | oldop, GEN_INT (imask), NULL_RTX, | |
13939 | 1, OPTAB_LIB_WIDEN); | |
13940 | emit_insn (gen_ashlsi3 (newop, newop, shift)); | |
13941 | ||
13942 | mask = gen_reg_rtx (SImode); | |
13943 | emit_move_insn (mask, GEN_INT (imask)); | |
13944 | emit_insn (gen_ashlsi3 (mask, mask, shift)); | |
13945 | ||
9f0076e5 DE |
13946 | if (code == PLUS) |
13947 | newop = gen_rtx_PLUS (SImode, m, newop); | |
13948 | else | |
13949 | newop = gen_rtx_MINUS (SImode, m, newop); | |
13950 | newop = gen_rtx_AND (SImode, newop, mask); | |
915167f5 GK |
13951 | newop = gen_rtx_IOR (SImode, newop, |
13952 | gen_rtx_AND (SImode, | |
13953 | gen_rtx_NOT (SImode, mask), | |
13954 | m)); | |
13955 | break; | |
13956 | } | |
13957 | ||
13958 | default: | |
13959 | gcc_unreachable (); | |
13960 | } | |
13961 | ||
13962 | op = newop; | |
13963 | used_mode = SImode; | |
13964 | before = gen_reg_rtx (used_mode); | |
13965 | after = gen_reg_rtx (used_mode); | |
13966 | } | |
13967 | else | |
13968 | { | |
13969 | used_mode = mode; | |
13970 | before = before_param; | |
13971 | after = after_param; | |
13972 | ||
13973 | if (before == NULL_RTX) | |
13974 | before = gen_reg_rtx (used_mode); | |
13975 | if (after == NULL_RTX) | |
13976 | after = gen_reg_rtx (used_mode); | |
13977 | } | |
bb8df8a6 | 13978 | |
f66f9865 | 13979 | if ((code == PLUS || code == MINUS) |
9f0076e5 | 13980 | && used_mode != mode) |
915167f5 GK |
13981 | the_op = op; /* Computed above. */ |
13982 | else if (GET_CODE (op) == NOT && GET_CODE (m) != NOT) | |
13983 | the_op = gen_rtx_fmt_ee (code, used_mode, op, m); | |
f66f9865 DE |
13984 | else if (code == NOT) |
13985 | the_op = gen_rtx_fmt_ee (IOR, used_mode, | |
13986 | gen_rtx_NOT (used_mode, m), | |
13987 | gen_rtx_NOT (used_mode, op)); | |
915167f5 GK |
13988 | else |
13989 | the_op = gen_rtx_fmt_ee (code, used_mode, m, op); | |
13990 | ||
13991 | set_after = gen_rtx_SET (VOIDmode, after, the_op); | |
13992 | set_before = gen_rtx_SET (VOIDmode, before, used_m); | |
13993 | set_atomic = gen_rtx_SET (VOIDmode, used_m, | |
9f0076e5 DE |
13994 | gen_rtx_UNSPEC (used_mode, |
13995 | gen_rtvec (1, the_op), | |
13996 | UNSPEC_SYNC_OP)); | |
915167f5 GK |
13997 | cc_scratch = gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (CCmode)); |
13998 | ||
9f0076e5 | 13999 | if ((code == PLUS || code == MINUS) && used_mode != mode) |
915167f5 GK |
14000 | vec = gen_rtvec (5, set_after, set_before, set_atomic, cc_scratch, |
14001 | gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (SImode))); | |
14002 | else | |
14003 | vec = gen_rtvec (4, set_after, set_before, set_atomic, cc_scratch); | |
14004 | emit_insn (gen_rtx_PARALLEL (VOIDmode, vec)); | |
14005 | ||
14006 | /* Shift and mask the return values properly. */ | |
14007 | if (used_mode != mode && before_param) | |
14008 | { | |
14009 | emit_insn (gen_lshrsi3 (before, before, shift)); | |
14010 | convert_move (before_param, before, 1); | |
14011 | } | |
14012 | ||
14013 | if (used_mode != mode && after_param) | |
14014 | { | |
14015 | emit_insn (gen_lshrsi3 (after, after, shift)); | |
14016 | convert_move (after_param, after, 1); | |
14017 | } | |
14018 | ||
14019 | /* The previous sequence will end with a branch that's dependent on | |
14020 | the conditional store, so placing an isync will ensure that no | |
14021 | other instructions (especially, no load or store instructions) | |
14022 | can start before the atomic operation completes. */ | |
14023 | if (sync_p) | |
14024 | emit_insn (gen_isync ()); | |
14025 | } | |
14026 | ||
b52110d4 DE |
14027 | /* A subroutine of the atomic operation splitters. Jump to LABEL if |
14028 | COND is true. Mark the jump as unlikely to be taken. */ | |
14029 | ||
14030 | static void | |
14031 | emit_unlikely_jump (rtx cond, rtx label) | |
14032 | { | |
14033 | rtx very_unlikely = GEN_INT (REG_BR_PROB_BASE / 100 - 1); | |
14034 | rtx x; | |
14035 | ||
14036 | x = gen_rtx_IF_THEN_ELSE (VOIDmode, cond, label, pc_rtx); | |
14037 | x = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, x)); | |
bbbbb16a | 14038 | add_reg_note (x, REG_BR_PROB, very_unlikely); |
b52110d4 DE |
14039 | } |
14040 | ||
14041 | /* A subroutine of the atomic operation splitters. Emit a load-locked | |
14042 | instruction in MODE. */ | |
14043 | ||
14044 | static void | |
14045 | emit_load_locked (enum machine_mode mode, rtx reg, rtx mem) | |
14046 | { | |
14047 | rtx (*fn) (rtx, rtx) = NULL; | |
14048 | if (mode == SImode) | |
14049 | fn = gen_load_locked_si; | |
14050 | else if (mode == DImode) | |
14051 | fn = gen_load_locked_di; | |
14052 | emit_insn (fn (reg, mem)); | |
14053 | } | |
14054 | ||
14055 | /* A subroutine of the atomic operation splitters. Emit a store-conditional | |
14056 | instruction in MODE. */ | |
14057 | ||
14058 | static void | |
14059 | emit_store_conditional (enum machine_mode mode, rtx res, rtx mem, rtx val) | |
14060 | { | |
14061 | rtx (*fn) (rtx, rtx, rtx) = NULL; | |
14062 | if (mode == SImode) | |
14063 | fn = gen_store_conditional_si; | |
14064 | else if (mode == DImode) | |
14065 | fn = gen_store_conditional_di; | |
14066 | ||
9f0076e5 | 14067 | /* Emit sync before stwcx. to address PPC405 Erratum. */ |
b52110d4 DE |
14068 | if (PPC405_ERRATUM77) |
14069 | emit_insn (gen_memory_barrier ()); | |
14070 | ||
14071 | emit_insn (fn (res, mem, val)); | |
14072 | } | |
14073 | ||
ea2c620c | 14074 | /* Expand an atomic fetch-and-operate pattern. CODE is the binary operation |
bb8df8a6 | 14075 | to perform. MEM is the memory on which to operate. VAL is the second |
9f0076e5 DE |
14076 | operand of the binary operator. BEFORE and AFTER are optional locations to |
14077 | return the value of MEM either before of after the operation. SCRATCH is | |
14078 | a scratch register. */ | |
14079 | ||
14080 | void | |
14081 | rs6000_split_atomic_op (enum rtx_code code, rtx mem, rtx val, | |
14082 | rtx before, rtx after, rtx scratch) | |
14083 | { | |
14084 | enum machine_mode mode = GET_MODE (mem); | |
14085 | rtx label, x, cond = gen_rtx_REG (CCmode, CR0_REGNO); | |
14086 | ||
a3cb4b82 | 14087 | emit_insn (gen_lwsync ()); |
9f0076e5 DE |
14088 | |
14089 | label = gen_label_rtx (); | |
14090 | emit_label (label); | |
14091 | label = gen_rtx_LABEL_REF (VOIDmode, label); | |
14092 | ||
14093 | if (before == NULL_RTX) | |
14094 | before = scratch; | |
14095 | emit_load_locked (mode, before, mem); | |
14096 | ||
14097 | if (code == NOT) | |
f66f9865 DE |
14098 | x = gen_rtx_IOR (mode, |
14099 | gen_rtx_NOT (mode, before), | |
14100 | gen_rtx_NOT (mode, val)); | |
9f0076e5 DE |
14101 | else if (code == AND) |
14102 | x = gen_rtx_UNSPEC (mode, gen_rtvec (2, before, val), UNSPEC_AND); | |
14103 | else | |
14104 | x = gen_rtx_fmt_ee (code, mode, before, val); | |
14105 | ||
14106 | if (after != NULL_RTX) | |
14107 | emit_insn (gen_rtx_SET (VOIDmode, after, copy_rtx (x))); | |
14108 | emit_insn (gen_rtx_SET (VOIDmode, scratch, x)); | |
14109 | ||
14110 | emit_store_conditional (mode, cond, mem, scratch); | |
14111 | ||
14112 | x = gen_rtx_NE (VOIDmode, cond, const0_rtx); | |
14113 | emit_unlikely_jump (x, label); | |
14114 | ||
14115 | emit_insn (gen_isync ()); | |
14116 | } | |
14117 | ||
b52110d4 DE |
14118 | /* Expand an atomic compare and swap operation. MEM is the memory on which |
14119 | to operate. OLDVAL is the old value to be compared. NEWVAL is the new | |
14120 | value to be stored. SCRATCH is a scratch GPR. */ | |
14121 | ||
14122 | void | |
14123 | rs6000_split_compare_and_swap (rtx retval, rtx mem, rtx oldval, rtx newval, | |
14124 | rtx scratch) | |
14125 | { | |
14126 | enum machine_mode mode = GET_MODE (mem); | |
14127 | rtx label1, label2, x, cond = gen_rtx_REG (CCmode, CR0_REGNO); | |
14128 | ||
a3cb4b82 | 14129 | emit_insn (gen_lwsync ()); |
b52110d4 DE |
14130 | |
14131 | label1 = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ()); | |
14132 | label2 = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ()); | |
14133 | emit_label (XEXP (label1, 0)); | |
14134 | ||
14135 | emit_load_locked (mode, retval, mem); | |
14136 | ||
14137 | x = gen_rtx_COMPARE (CCmode, retval, oldval); | |
14138 | emit_insn (gen_rtx_SET (VOIDmode, cond, x)); | |
14139 | ||
14140 | x = gen_rtx_NE (VOIDmode, cond, const0_rtx); | |
14141 | emit_unlikely_jump (x, label2); | |
14142 | ||
14143 | emit_move_insn (scratch, newval); | |
14144 | emit_store_conditional (mode, cond, mem, scratch); | |
14145 | ||
14146 | x = gen_rtx_NE (VOIDmode, cond, const0_rtx); | |
14147 | emit_unlikely_jump (x, label1); | |
14148 | ||
14149 | emit_insn (gen_isync ()); | |
14150 | emit_label (XEXP (label2, 0)); | |
14151 | } | |
14152 | ||
14153 | /* Expand an atomic test and set operation. MEM is the memory on which | |
14154 | to operate. VAL is the value set. SCRATCH is a scratch GPR. */ | |
14155 | ||
14156 | void | |
14157 | rs6000_split_lock_test_and_set (rtx retval, rtx mem, rtx val, rtx scratch) | |
14158 | { | |
14159 | enum machine_mode mode = GET_MODE (mem); | |
14160 | rtx label, x, cond = gen_rtx_REG (CCmode, CR0_REGNO); | |
14161 | ||
b52110d4 DE |
14162 | label = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ()); |
14163 | emit_label (XEXP (label, 0)); | |
14164 | ||
14165 | emit_load_locked (mode, retval, mem); | |
14166 | emit_move_insn (scratch, val); | |
14167 | emit_store_conditional (mode, cond, mem, scratch); | |
14168 | ||
14169 | x = gen_rtx_NE (VOIDmode, cond, const0_rtx); | |
14170 | emit_unlikely_jump (x, label); | |
14171 | ||
14172 | emit_insn (gen_isync ()); | |
14173 | } | |
14174 | ||
9fc75b97 DE |
14175 | void |
14176 | rs6000_expand_compare_and_swapqhi (rtx dst, rtx mem, rtx oldval, rtx newval) | |
14177 | { | |
14178 | enum machine_mode mode = GET_MODE (mem); | |
14179 | rtx addrSI, align, wdst, shift, mask; | |
14180 | HOST_WIDE_INT shift_mask = mode == QImode ? 0x18 : 0x10; | |
14181 | HOST_WIDE_INT imask = GET_MODE_MASK (mode); | |
14182 | ||
14183 | /* Shift amount for subword relative to aligned word. */ | |
4b49d9ce AP |
14184 | addrSI = force_reg (GET_MODE (XEXP (mem, 0)), XEXP (mem, 0)); |
14185 | addrSI = force_reg (SImode, gen_lowpart_common (SImode, addrSI)); | |
9fc75b97 DE |
14186 | shift = gen_reg_rtx (SImode); |
14187 | emit_insn (gen_rlwinm (shift, addrSI, GEN_INT (3), | |
14188 | GEN_INT (shift_mask))); | |
14189 | emit_insn (gen_xorsi3 (shift, shift, GEN_INT (shift_mask))); | |
14190 | ||
14191 | /* Shift and mask old value into position within word. */ | |
14192 | oldval = convert_modes (SImode, mode, oldval, 1); | |
14193 | oldval = expand_binop (SImode, and_optab, | |
14194 | oldval, GEN_INT (imask), NULL_RTX, | |
14195 | 1, OPTAB_LIB_WIDEN); | |
14196 | emit_insn (gen_ashlsi3 (oldval, oldval, shift)); | |
14197 | ||
14198 | /* Shift and mask new value into position within word. */ | |
14199 | newval = convert_modes (SImode, mode, newval, 1); | |
14200 | newval = expand_binop (SImode, and_optab, | |
14201 | newval, GEN_INT (imask), NULL_RTX, | |
14202 | 1, OPTAB_LIB_WIDEN); | |
14203 | emit_insn (gen_ashlsi3 (newval, newval, shift)); | |
14204 | ||
14205 | /* Mask for insertion. */ | |
14206 | mask = gen_reg_rtx (SImode); | |
14207 | emit_move_insn (mask, GEN_INT (imask)); | |
14208 | emit_insn (gen_ashlsi3 (mask, mask, shift)); | |
14209 | ||
14210 | /* Address of aligned word containing subword. */ | |
14211 | align = expand_binop (Pmode, and_optab, XEXP (mem, 0), GEN_INT (-4), | |
14212 | NULL_RTX, 1, OPTAB_LIB_WIDEN); | |
14213 | mem = change_address (mem, SImode, align); | |
14214 | set_mem_align (mem, 32); | |
14215 | MEM_VOLATILE_P (mem) = 1; | |
14216 | ||
14217 | wdst = gen_reg_rtx (SImode); | |
14218 | emit_insn (gen_sync_compare_and_swapqhi_internal (wdst, mask, | |
14219 | oldval, newval, mem)); | |
14220 | ||
2725b75c JJ |
14221 | /* Shift the result back. */ |
14222 | emit_insn (gen_lshrsi3 (wdst, wdst, shift)); | |
14223 | ||
9fc75b97 DE |
14224 | emit_move_insn (dst, gen_lowpart (mode, wdst)); |
14225 | } | |
14226 | ||
14227 | void | |
14228 | rs6000_split_compare_and_swapqhi (rtx dest, rtx mask, | |
14229 | rtx oldval, rtx newval, rtx mem, | |
14230 | rtx scratch) | |
14231 | { | |
14232 | rtx label1, label2, x, cond = gen_rtx_REG (CCmode, CR0_REGNO); | |
14233 | ||
a3cb4b82 | 14234 | emit_insn (gen_lwsync ()); |
9fc75b97 DE |
14235 | label1 = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ()); |
14236 | label2 = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ()); | |
14237 | emit_label (XEXP (label1, 0)); | |
14238 | ||
14239 | emit_load_locked (SImode, scratch, mem); | |
14240 | ||
14241 | /* Mask subword within loaded value for comparison with oldval. | |
14242 | Use UNSPEC_AND to avoid clobber.*/ | |
14243 | emit_insn (gen_rtx_SET (SImode, dest, | |
14244 | gen_rtx_UNSPEC (SImode, | |
14245 | gen_rtvec (2, scratch, mask), | |
14246 | UNSPEC_AND))); | |
14247 | ||
14248 | x = gen_rtx_COMPARE (CCmode, dest, oldval); | |
14249 | emit_insn (gen_rtx_SET (VOIDmode, cond, x)); | |
14250 | ||
14251 | x = gen_rtx_NE (VOIDmode, cond, const0_rtx); | |
14252 | emit_unlikely_jump (x, label2); | |
14253 | ||
14254 | /* Clear subword within loaded value for insertion of new value. */ | |
14255 | emit_insn (gen_rtx_SET (SImode, scratch, | |
14256 | gen_rtx_AND (SImode, | |
14257 | gen_rtx_NOT (SImode, mask), scratch))); | |
14258 | emit_insn (gen_iorsi3 (scratch, scratch, newval)); | |
14259 | emit_store_conditional (SImode, cond, mem, scratch); | |
14260 | ||
14261 | x = gen_rtx_NE (VOIDmode, cond, const0_rtx); | |
14262 | emit_unlikely_jump (x, label1); | |
14263 | ||
14264 | emit_insn (gen_isync ()); | |
14265 | emit_label (XEXP (label2, 0)); | |
14266 | } | |
14267 | ||
14268 | ||
b52110d4 | 14269 | /* Emit instructions to move SRC to DST. Called by splitters for |
a9baceb1 GK |
14270 | multi-register moves. It will emit at most one instruction for |
14271 | each register that is accessed; that is, it won't emit li/lis pairs | |
14272 | (or equivalent for 64-bit code). One of SRC or DST must be a hard | |
14273 | register. */ | |
46c07df8 | 14274 | |
46c07df8 | 14275 | void |
a9baceb1 | 14276 | rs6000_split_multireg_move (rtx dst, rtx src) |
46c07df8 | 14277 | { |
a9baceb1 GK |
14278 | /* The register number of the first register being moved. */ |
14279 | int reg; | |
14280 | /* The mode that is to be moved. */ | |
14281 | enum machine_mode mode; | |
14282 | /* The mode that the move is being done in, and its size. */ | |
14283 | enum machine_mode reg_mode; | |
14284 | int reg_mode_size; | |
14285 | /* The number of registers that will be moved. */ | |
14286 | int nregs; | |
14287 | ||
14288 | reg = REG_P (dst) ? REGNO (dst) : REGNO (src); | |
14289 | mode = GET_MODE (dst); | |
c8b622ff | 14290 | nregs = hard_regno_nregs[reg][mode]; |
a9baceb1 | 14291 | if (FP_REGNO_P (reg)) |
696e45ba ME |
14292 | reg_mode = DECIMAL_FLOAT_MODE_P (mode) ? DDmode : |
14293 | ((TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT) ? DFmode : SFmode); | |
a9baceb1 GK |
14294 | else if (ALTIVEC_REGNO_P (reg)) |
14295 | reg_mode = V16QImode; | |
4f011e1e JM |
14296 | else if (TARGET_E500_DOUBLE && mode == TFmode) |
14297 | reg_mode = DFmode; | |
a9baceb1 GK |
14298 | else |
14299 | reg_mode = word_mode; | |
14300 | reg_mode_size = GET_MODE_SIZE (reg_mode); | |
f676971a | 14301 | |
37409796 | 14302 | gcc_assert (reg_mode_size * nregs == GET_MODE_SIZE (mode)); |
f676971a | 14303 | |
a9baceb1 GK |
14304 | if (REG_P (src) && REG_P (dst) && (REGNO (src) < REGNO (dst))) |
14305 | { | |
14306 | /* Move register range backwards, if we might have destructive | |
14307 | overlap. */ | |
14308 | int i; | |
14309 | for (i = nregs - 1; i >= 0; i--) | |
f676971a | 14310 | emit_insn (gen_rtx_SET (VOIDmode, |
a9baceb1 GK |
14311 | simplify_gen_subreg (reg_mode, dst, mode, |
14312 | i * reg_mode_size), | |
14313 | simplify_gen_subreg (reg_mode, src, mode, | |
14314 | i * reg_mode_size))); | |
14315 | } | |
46c07df8 HP |
14316 | else |
14317 | { | |
a9baceb1 GK |
14318 | int i; |
14319 | int j = -1; | |
14320 | bool used_update = false; | |
46c07df8 | 14321 | |
c1e55850 | 14322 | if (MEM_P (src) && INT_REGNO_P (reg)) |
c4ad648e AM |
14323 | { |
14324 | rtx breg; | |
3a1f863f | 14325 | |
a9baceb1 GK |
14326 | if (GET_CODE (XEXP (src, 0)) == PRE_INC |
14327 | || GET_CODE (XEXP (src, 0)) == PRE_DEC) | |
3a1f863f DE |
14328 | { |
14329 | rtx delta_rtx; | |
a9baceb1 | 14330 | breg = XEXP (XEXP (src, 0), 0); |
c4ad648e AM |
14331 | delta_rtx = (GET_CODE (XEXP (src, 0)) == PRE_INC |
14332 | ? GEN_INT (GET_MODE_SIZE (GET_MODE (src))) | |
14333 | : GEN_INT (-GET_MODE_SIZE (GET_MODE (src)))); | |
a9baceb1 GK |
14334 | emit_insn (TARGET_32BIT |
14335 | ? gen_addsi3 (breg, breg, delta_rtx) | |
14336 | : gen_adddi3 (breg, breg, delta_rtx)); | |
13e2e16e | 14337 | src = replace_equiv_address (src, breg); |
3a1f863f | 14338 | } |
d04b6e6e | 14339 | else if (! rs6000_offsettable_memref_p (src)) |
c1e55850 | 14340 | { |
13e2e16e | 14341 | rtx basereg; |
c1e55850 GK |
14342 | basereg = gen_rtx_REG (Pmode, reg); |
14343 | emit_insn (gen_rtx_SET (VOIDmode, basereg, XEXP (src, 0))); | |
13e2e16e | 14344 | src = replace_equiv_address (src, basereg); |
c1e55850 | 14345 | } |
3a1f863f | 14346 | |
0423421f AM |
14347 | breg = XEXP (src, 0); |
14348 | if (GET_CODE (breg) == PLUS || GET_CODE (breg) == LO_SUM) | |
14349 | breg = XEXP (breg, 0); | |
14350 | ||
14351 | /* If the base register we are using to address memory is | |
14352 | also a destination reg, then change that register last. */ | |
14353 | if (REG_P (breg) | |
14354 | && REGNO (breg) >= REGNO (dst) | |
3a1f863f DE |
14355 | && REGNO (breg) < REGNO (dst) + nregs) |
14356 | j = REGNO (breg) - REGNO (dst); | |
c4ad648e | 14357 | } |
46c07df8 | 14358 | |
a9baceb1 | 14359 | if (GET_CODE (dst) == MEM && INT_REGNO_P (reg)) |
3a1f863f DE |
14360 | { |
14361 | rtx breg; | |
14362 | ||
a9baceb1 GK |
14363 | if (GET_CODE (XEXP (dst, 0)) == PRE_INC |
14364 | || GET_CODE (XEXP (dst, 0)) == PRE_DEC) | |
3a1f863f DE |
14365 | { |
14366 | rtx delta_rtx; | |
a9baceb1 | 14367 | breg = XEXP (XEXP (dst, 0), 0); |
c4ad648e AM |
14368 | delta_rtx = (GET_CODE (XEXP (dst, 0)) == PRE_INC |
14369 | ? GEN_INT (GET_MODE_SIZE (GET_MODE (dst))) | |
14370 | : GEN_INT (-GET_MODE_SIZE (GET_MODE (dst)))); | |
3a1f863f DE |
14371 | |
14372 | /* We have to update the breg before doing the store. | |
14373 | Use store with update, if available. */ | |
14374 | ||
14375 | if (TARGET_UPDATE) | |
14376 | { | |
a9baceb1 | 14377 | rtx nsrc = simplify_gen_subreg (reg_mode, src, mode, 0); |
c4ad648e AM |
14378 | emit_insn (TARGET_32BIT |
14379 | ? (TARGET_POWERPC64 | |
14380 | ? gen_movdi_si_update (breg, breg, delta_rtx, nsrc) | |
14381 | : gen_movsi_update (breg, breg, delta_rtx, nsrc)) | |
14382 | : gen_movdi_di_update (breg, breg, delta_rtx, nsrc)); | |
a9baceb1 | 14383 | used_update = true; |
3a1f863f DE |
14384 | } |
14385 | else | |
a9baceb1 GK |
14386 | emit_insn (TARGET_32BIT |
14387 | ? gen_addsi3 (breg, breg, delta_rtx) | |
14388 | : gen_adddi3 (breg, breg, delta_rtx)); | |
13e2e16e | 14389 | dst = replace_equiv_address (dst, breg); |
3a1f863f | 14390 | } |
37409796 | 14391 | else |
d04b6e6e | 14392 | gcc_assert (rs6000_offsettable_memref_p (dst)); |
3a1f863f DE |
14393 | } |
14394 | ||
46c07df8 | 14395 | for (i = 0; i < nregs; i++) |
f676971a | 14396 | { |
3a1f863f DE |
14397 | /* Calculate index to next subword. */ |
14398 | ++j; | |
f676971a | 14399 | if (j == nregs) |
3a1f863f | 14400 | j = 0; |
46c07df8 | 14401 | |
112cdef5 | 14402 | /* If compiler already emitted move of first word by |
a9baceb1 | 14403 | store with update, no need to do anything. */ |
3a1f863f | 14404 | if (j == 0 && used_update) |
a9baceb1 | 14405 | continue; |
f676971a | 14406 | |
a9baceb1 GK |
14407 | emit_insn (gen_rtx_SET (VOIDmode, |
14408 | simplify_gen_subreg (reg_mode, dst, mode, | |
14409 | j * reg_mode_size), | |
14410 | simplify_gen_subreg (reg_mode, src, mode, | |
14411 | j * reg_mode_size))); | |
3a1f863f | 14412 | } |
46c07df8 HP |
14413 | } |
14414 | } | |
14415 | ||
12a4e8c5 | 14416 | \f |
a4f6c312 SS |
14417 | /* This page contains routines that are used to determine what the |
14418 | function prologue and epilogue code will do and write them out. */ | |
9878760c | 14419 | |
a4f6c312 SS |
14420 | /* Return the first fixed-point register that is required to be |
14421 | saved. 32 if none. */ | |
9878760c RK |
14422 | |
14423 | int | |
863d938c | 14424 | first_reg_to_save (void) |
9878760c RK |
14425 | { |
14426 | int first_reg; | |
14427 | ||
14428 | /* Find lowest numbered live register. */ | |
14429 | for (first_reg = 13; first_reg <= 31; first_reg++) | |
6fb5fa3c | 14430 | if (df_regs_ever_live_p (first_reg) |
a38d360d | 14431 | && (! call_used_regs[first_reg] |
1db02437 | 14432 | || (first_reg == RS6000_PIC_OFFSET_TABLE_REGNUM |
14f00213 | 14433 | && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0) |
b4db40bf JJ |
14434 | || (DEFAULT_ABI == ABI_DARWIN && flag_pic) |
14435 | || (TARGET_TOC && TARGET_MINIMAL_TOC))))) | |
9878760c RK |
14436 | break; |
14437 | ||
ee890fe2 | 14438 | #if TARGET_MACHO |
93638d7a | 14439 | if (flag_pic |
e3b5732b | 14440 | && crtl->uses_pic_offset_table |
93638d7a | 14441 | && first_reg > RS6000_PIC_OFFSET_TABLE_REGNUM) |
1db02437 | 14442 | return RS6000_PIC_OFFSET_TABLE_REGNUM; |
ee890fe2 SS |
14443 | #endif |
14444 | ||
9878760c RK |
14445 | return first_reg; |
14446 | } | |
14447 | ||
14448 | /* Similar, for FP regs. */ | |
14449 | ||
14450 | int | |
863d938c | 14451 | first_fp_reg_to_save (void) |
9878760c RK |
14452 | { |
14453 | int first_reg; | |
14454 | ||
14455 | /* Find lowest numbered live register. */ | |
14456 | for (first_reg = 14 + 32; first_reg <= 63; first_reg++) | |
6fb5fa3c | 14457 | if (df_regs_ever_live_p (first_reg)) |
9878760c RK |
14458 | break; |
14459 | ||
14460 | return first_reg; | |
14461 | } | |
00b960c7 AH |
14462 | |
14463 | /* Similar, for AltiVec regs. */ | |
14464 | ||
14465 | static int | |
863d938c | 14466 | first_altivec_reg_to_save (void) |
00b960c7 AH |
14467 | { |
14468 | int i; | |
14469 | ||
14470 | /* Stack frame remains as is unless we are in AltiVec ABI. */ | |
14471 | if (! TARGET_ALTIVEC_ABI) | |
14472 | return LAST_ALTIVEC_REGNO + 1; | |
14473 | ||
22fa69da | 14474 | /* On Darwin, the unwind routines are compiled without |
982afe02 | 14475 | TARGET_ALTIVEC, and use save_world to save/restore the |
22fa69da | 14476 | altivec registers when necessary. */ |
e3b5732b | 14477 | if (DEFAULT_ABI == ABI_DARWIN && crtl->calls_eh_return |
22fa69da GK |
14478 | && ! TARGET_ALTIVEC) |
14479 | return FIRST_ALTIVEC_REGNO + 20; | |
14480 | ||
00b960c7 AH |
14481 | /* Find lowest numbered live register. */ |
14482 | for (i = FIRST_ALTIVEC_REGNO + 20; i <= LAST_ALTIVEC_REGNO; ++i) | |
6fb5fa3c | 14483 | if (df_regs_ever_live_p (i)) |
00b960c7 AH |
14484 | break; |
14485 | ||
14486 | return i; | |
14487 | } | |
14488 | ||
14489 | /* Return a 32-bit mask of the AltiVec registers we need to set in | |
14490 | VRSAVE. Bit n of the return value is 1 if Vn is live. The MSB in | |
14491 | the 32-bit word is 0. */ | |
14492 | ||
14493 | static unsigned int | |
863d938c | 14494 | compute_vrsave_mask (void) |
00b960c7 AH |
14495 | { |
14496 | unsigned int i, mask = 0; | |
14497 | ||
22fa69da | 14498 | /* On Darwin, the unwind routines are compiled without |
982afe02 | 14499 | TARGET_ALTIVEC, and use save_world to save/restore the |
22fa69da | 14500 | call-saved altivec registers when necessary. */ |
e3b5732b | 14501 | if (DEFAULT_ABI == ABI_DARWIN && crtl->calls_eh_return |
22fa69da GK |
14502 | && ! TARGET_ALTIVEC) |
14503 | mask |= 0xFFF; | |
14504 | ||
00b960c7 AH |
14505 | /* First, find out if we use _any_ altivec registers. */ |
14506 | for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i) | |
6fb5fa3c | 14507 | if (df_regs_ever_live_p (i)) |
00b960c7 AH |
14508 | mask |= ALTIVEC_REG_BIT (i); |
14509 | ||
14510 | if (mask == 0) | |
14511 | return mask; | |
14512 | ||
00b960c7 AH |
14513 | /* Next, remove the argument registers from the set. These must |
14514 | be in the VRSAVE mask set by the caller, so we don't need to add | |
14515 | them in again. More importantly, the mask we compute here is | |
14516 | used to generate CLOBBERs in the set_vrsave insn, and we do not | |
14517 | wish the argument registers to die. */ | |
38173d38 | 14518 | for (i = crtl->args.info.vregno - 1; i >= ALTIVEC_ARG_MIN_REG; --i) |
00b960c7 AH |
14519 | mask &= ~ALTIVEC_REG_BIT (i); |
14520 | ||
14521 | /* Similarly, remove the return value from the set. */ | |
14522 | { | |
14523 | bool yes = false; | |
14524 | diddle_return_value (is_altivec_return_reg, &yes); | |
14525 | if (yes) | |
14526 | mask &= ~ALTIVEC_REG_BIT (ALTIVEC_ARG_RETURN); | |
14527 | } | |
14528 | ||
14529 | return mask; | |
14530 | } | |
14531 | ||
d62294f5 | 14532 | /* For a very restricted set of circumstances, we can cut down the |
f57fe068 AM |
14533 | size of prologues/epilogues by calling our own save/restore-the-world |
14534 | routines. */ | |
d62294f5 FJ |
14535 | |
14536 | static void | |
f57fe068 AM |
14537 | compute_save_world_info (rs6000_stack_t *info_ptr) |
14538 | { | |
14539 | info_ptr->world_save_p = 1; | |
14540 | info_ptr->world_save_p | |
14541 | = (WORLD_SAVE_P (info_ptr) | |
14542 | && DEFAULT_ABI == ABI_DARWIN | |
e3b5732b | 14543 | && ! (cfun->calls_setjmp && flag_exceptions) |
f57fe068 AM |
14544 | && info_ptr->first_fp_reg_save == FIRST_SAVED_FP_REGNO |
14545 | && info_ptr->first_gp_reg_save == FIRST_SAVED_GP_REGNO | |
14546 | && info_ptr->first_altivec_reg_save == FIRST_SAVED_ALTIVEC_REGNO | |
14547 | && info_ptr->cr_save_p); | |
f676971a | 14548 | |
d62294f5 FJ |
14549 | /* This will not work in conjunction with sibcalls. Make sure there |
14550 | are none. (This check is expensive, but seldom executed.) */ | |
f57fe068 | 14551 | if (WORLD_SAVE_P (info_ptr)) |
f676971a | 14552 | { |
d62294f5 FJ |
14553 | rtx insn; |
14554 | for ( insn = get_last_insn_anywhere (); insn; insn = PREV_INSN (insn)) | |
c4ad648e AM |
14555 | if ( GET_CODE (insn) == CALL_INSN |
14556 | && SIBLING_CALL_P (insn)) | |
14557 | { | |
14558 | info_ptr->world_save_p = 0; | |
14559 | break; | |
14560 | } | |
d62294f5 | 14561 | } |
f676971a | 14562 | |
f57fe068 | 14563 | if (WORLD_SAVE_P (info_ptr)) |
d62294f5 FJ |
14564 | { |
14565 | /* Even if we're not touching VRsave, make sure there's room on the | |
14566 | stack for it, if it looks like we're calling SAVE_WORLD, which | |
c4ad648e | 14567 | will attempt to save it. */ |
d62294f5 FJ |
14568 | info_ptr->vrsave_size = 4; |
14569 | ||
298ac1dd AP |
14570 | /* If we are going to save the world, we need to save the link register too. */ |
14571 | info_ptr->lr_save_p = 1; | |
14572 | ||
d62294f5 FJ |
14573 | /* "Save" the VRsave register too if we're saving the world. */ |
14574 | if (info_ptr->vrsave_mask == 0) | |
c4ad648e | 14575 | info_ptr->vrsave_mask = compute_vrsave_mask (); |
d62294f5 FJ |
14576 | |
14577 | /* Because the Darwin register save/restore routines only handle | |
c4ad648e | 14578 | F14 .. F31 and V20 .. V31 as per the ABI, perform a consistency |
992d08b1 | 14579 | check. */ |
37409796 NS |
14580 | gcc_assert (info_ptr->first_fp_reg_save >= FIRST_SAVED_FP_REGNO |
14581 | && (info_ptr->first_altivec_reg_save | |
14582 | >= FIRST_SAVED_ALTIVEC_REGNO)); | |
d62294f5 | 14583 | } |
f676971a | 14584 | return; |
d62294f5 FJ |
14585 | } |
14586 | ||
14587 | ||
00b960c7 | 14588 | static void |
a2369ed3 | 14589 | is_altivec_return_reg (rtx reg, void *xyes) |
00b960c7 AH |
14590 | { |
14591 | bool *yes = (bool *) xyes; | |
14592 | if (REGNO (reg) == ALTIVEC_ARG_RETURN) | |
14593 | *yes = true; | |
14594 | } | |
14595 | ||
4697a36c MM |
14596 | \f |
14597 | /* Calculate the stack information for the current function. This is | |
14598 | complicated by having two separate calling sequences, the AIX calling | |
14599 | sequence and the V.4 calling sequence. | |
14600 | ||
592696dd | 14601 | AIX (and Darwin/Mac OS X) stack frames look like: |
a260abc9 | 14602 | 32-bit 64-bit |
4697a36c | 14603 | SP----> +---------------------------------------+ |
a260abc9 | 14604 | | back chain to caller | 0 0 |
4697a36c | 14605 | +---------------------------------------+ |
a260abc9 | 14606 | | saved CR | 4 8 (8-11) |
4697a36c | 14607 | +---------------------------------------+ |
a260abc9 | 14608 | | saved LR | 8 16 |
4697a36c | 14609 | +---------------------------------------+ |
a260abc9 | 14610 | | reserved for compilers | 12 24 |
4697a36c | 14611 | +---------------------------------------+ |
a260abc9 | 14612 | | reserved for binders | 16 32 |
4697a36c | 14613 | +---------------------------------------+ |
a260abc9 | 14614 | | saved TOC pointer | 20 40 |
4697a36c | 14615 | +---------------------------------------+ |
a260abc9 | 14616 | | Parameter save area (P) | 24 48 |
4697a36c | 14617 | +---------------------------------------+ |
a260abc9 | 14618 | | Alloca space (A) | 24+P etc. |
802a0058 | 14619 | +---------------------------------------+ |
a7df97e6 | 14620 | | Local variable space (L) | 24+P+A |
4697a36c | 14621 | +---------------------------------------+ |
a7df97e6 | 14622 | | Float/int conversion temporary (X) | 24+P+A+L |
4697a36c | 14623 | +---------------------------------------+ |
00b960c7 AH |
14624 | | Save area for AltiVec registers (W) | 24+P+A+L+X |
14625 | +---------------------------------------+ | |
14626 | | AltiVec alignment padding (Y) | 24+P+A+L+X+W | |
14627 | +---------------------------------------+ | |
14628 | | Save area for VRSAVE register (Z) | 24+P+A+L+X+W+Y | |
4697a36c | 14629 | +---------------------------------------+ |
00b960c7 AH |
14630 | | Save area for GP registers (G) | 24+P+A+X+L+X+W+Y+Z |
14631 | +---------------------------------------+ | |
14632 | | Save area for FP registers (F) | 24+P+A+X+L+X+W+Y+Z+G | |
4697a36c MM |
14633 | +---------------------------------------+ |
14634 | old SP->| back chain to caller's caller | | |
14635 | +---------------------------------------+ | |
14636 | ||
5376a30c KR |
14637 | The required alignment for AIX configurations is two words (i.e., 8 |
14638 | or 16 bytes). | |
14639 | ||
14640 | ||
4697a36c MM |
14641 | V.4 stack frames look like: |
14642 | ||
14643 | SP----> +---------------------------------------+ | |
14644 | | back chain to caller | 0 | |
14645 | +---------------------------------------+ | |
5eb387b8 | 14646 | | caller's saved LR | 4 |
4697a36c MM |
14647 | +---------------------------------------+ |
14648 | | Parameter save area (P) | 8 | |
14649 | +---------------------------------------+ | |
a7df97e6 | 14650 | | Alloca space (A) | 8+P |
f676971a | 14651 | +---------------------------------------+ |
a7df97e6 | 14652 | | Varargs save area (V) | 8+P+A |
f676971a | 14653 | +---------------------------------------+ |
a7df97e6 | 14654 | | Local variable space (L) | 8+P+A+V |
f676971a | 14655 | +---------------------------------------+ |
a7df97e6 | 14656 | | Float/int conversion temporary (X) | 8+P+A+V+L |
4697a36c | 14657 | +---------------------------------------+ |
00b960c7 AH |
14658 | | Save area for AltiVec registers (W) | 8+P+A+V+L+X |
14659 | +---------------------------------------+ | |
14660 | | AltiVec alignment padding (Y) | 8+P+A+V+L+X+W | |
14661 | +---------------------------------------+ | |
14662 | | Save area for VRSAVE register (Z) | 8+P+A+V+L+X+W+Y | |
14663 | +---------------------------------------+ | |
c4ad648e AM |
14664 | | SPE: area for 64-bit GP registers | |
14665 | +---------------------------------------+ | |
14666 | | SPE alignment padding | | |
14667 | +---------------------------------------+ | |
00b960c7 | 14668 | | saved CR (C) | 8+P+A+V+L+X+W+Y+Z |
f676971a | 14669 | +---------------------------------------+ |
00b960c7 | 14670 | | Save area for GP registers (G) | 8+P+A+V+L+X+W+Y+Z+C |
f676971a | 14671 | +---------------------------------------+ |
00b960c7 | 14672 | | Save area for FP registers (F) | 8+P+A+V+L+X+W+Y+Z+C+G |
4697a36c MM |
14673 | +---------------------------------------+ |
14674 | old SP->| back chain to caller's caller | | |
14675 | +---------------------------------------+ | |
b6c9286a | 14676 | |
5376a30c KR |
14677 | The required alignment for V.4 is 16 bytes, or 8 bytes if -meabi is |
14678 | given. (But note below and in sysv4.h that we require only 8 and | |
14679 | may round up the size of our stack frame anyways. The historical | |
14680 | reason is early versions of powerpc-linux which didn't properly | |
14681 | align the stack at program startup. A happy side-effect is that | |
14682 | -mno-eabi libraries can be used with -meabi programs.) | |
14683 | ||
50d440bc | 14684 | The EABI configuration defaults to the V.4 layout. However, |
5376a30c KR |
14685 | the stack alignment requirements may differ. If -mno-eabi is not |
14686 | given, the required stack alignment is 8 bytes; if -mno-eabi is | |
14687 | given, the required alignment is 16 bytes. (But see V.4 comment | |
14688 | above.) */ | |
4697a36c | 14689 | |
61b2fbe7 MM |
14690 | #ifndef ABI_STACK_BOUNDARY |
14691 | #define ABI_STACK_BOUNDARY STACK_BOUNDARY | |
14692 | #endif | |
14693 | ||
d1d0c603 | 14694 | static rs6000_stack_t * |
863d938c | 14695 | rs6000_stack_info (void) |
4697a36c | 14696 | { |
022123e6 | 14697 | static rs6000_stack_t info; |
4697a36c | 14698 | rs6000_stack_t *info_ptr = &info; |
327e5343 | 14699 | int reg_size = TARGET_32BIT ? 4 : 8; |
83720594 | 14700 | int ehrd_size; |
64045029 | 14701 | int save_align; |
8070c91a | 14702 | int first_gp; |
44688022 | 14703 | HOST_WIDE_INT non_fixed_size; |
4697a36c | 14704 | |
022123e6 | 14705 | memset (&info, 0, sizeof (info)); |
4697a36c | 14706 | |
c19de7aa AH |
14707 | if (TARGET_SPE) |
14708 | { | |
14709 | /* Cache value so we don't rescan instruction chain over and over. */ | |
9b7b447f | 14710 | if (cfun->machine->insn_chain_scanned_p == 0) |
b5a5beb9 AH |
14711 | cfun->machine->insn_chain_scanned_p |
14712 | = spe_func_has_64bit_regs_p () + 1; | |
14713 | info_ptr->spe_64bit_regs_used = cfun->machine->insn_chain_scanned_p - 1; | |
c19de7aa AH |
14714 | } |
14715 | ||
a4f6c312 | 14716 | /* Select which calling sequence. */ |
178274da | 14717 | info_ptr->abi = DEFAULT_ABI; |
9878760c | 14718 | |
a4f6c312 | 14719 | /* Calculate which registers need to be saved & save area size. */ |
4697a36c | 14720 | info_ptr->first_gp_reg_save = first_reg_to_save (); |
f676971a | 14721 | /* Assume that we will have to save RS6000_PIC_OFFSET_TABLE_REGNUM, |
8070c91a DJ |
14722 | even if it currently looks like we won't. Reload may need it to |
14723 | get at a constant; if so, it will have already created a constant | |
14724 | pool entry for it. */ | |
2bfcf297 | 14725 | if (((TARGET_TOC && TARGET_MINIMAL_TOC) |
178274da AM |
14726 | || (flag_pic == 1 && DEFAULT_ABI == ABI_V4) |
14727 | || (flag_pic && DEFAULT_ABI == ABI_DARWIN)) | |
e3b5732b | 14728 | && crtl->uses_const_pool |
1db02437 | 14729 | && info_ptr->first_gp_reg_save > RS6000_PIC_OFFSET_TABLE_REGNUM) |
8070c91a | 14730 | first_gp = RS6000_PIC_OFFSET_TABLE_REGNUM; |
906fb125 | 14731 | else |
8070c91a DJ |
14732 | first_gp = info_ptr->first_gp_reg_save; |
14733 | ||
14734 | info_ptr->gp_size = reg_size * (32 - first_gp); | |
4697a36c | 14735 | |
a3170dc6 AH |
14736 | /* For the SPE, we have an additional upper 32-bits on each GPR. |
14737 | Ideally we should save the entire 64-bits only when the upper | |
14738 | half is used in SIMD instructions. Since we only record | |
14739 | registers live (not the size they are used in), this proves | |
14740 | difficult because we'd have to traverse the instruction chain at | |
14741 | the right time, taking reload into account. This is a real pain, | |
c19de7aa AH |
14742 | so we opt to save the GPRs in 64-bits always if but one register |
14743 | gets used in 64-bits. Otherwise, all the registers in the frame | |
14744 | get saved in 32-bits. | |
a3170dc6 | 14745 | |
c19de7aa | 14746 | So... since when we save all GPRs (except the SP) in 64-bits, the |
a3170dc6 | 14747 | traditional GP save area will be empty. */ |
c19de7aa | 14748 | if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0) |
a3170dc6 AH |
14749 | info_ptr->gp_size = 0; |
14750 | ||
4697a36c MM |
14751 | info_ptr->first_fp_reg_save = first_fp_reg_to_save (); |
14752 | info_ptr->fp_size = 8 * (64 - info_ptr->first_fp_reg_save); | |
14753 | ||
00b960c7 AH |
14754 | info_ptr->first_altivec_reg_save = first_altivec_reg_to_save (); |
14755 | info_ptr->altivec_size = 16 * (LAST_ALTIVEC_REGNO + 1 | |
14756 | - info_ptr->first_altivec_reg_save); | |
14757 | ||
592696dd | 14758 | /* Does this function call anything? */ |
71f123ca FS |
14759 | info_ptr->calls_p = (! current_function_is_leaf |
14760 | || cfun->machine->ra_needs_full_frame); | |
b6c9286a | 14761 | |
a4f6c312 | 14762 | /* Determine if we need to save the link register. */ |
022123e6 | 14763 | if ((DEFAULT_ABI == ABI_AIX |
e3b5732b | 14764 | && crtl->profile |
022123e6 | 14765 | && !TARGET_PROFILE_KERNEL) |
4697a36c MM |
14766 | #ifdef TARGET_RELOCATABLE |
14767 | || (TARGET_RELOCATABLE && (get_pool_size () != 0)) | |
14768 | #endif | |
14769 | || (info_ptr->first_fp_reg_save != 64 | |
14770 | && !FP_SAVE_INLINE (info_ptr->first_fp_reg_save)) | |
e3b5732b | 14771 | || (DEFAULT_ABI == ABI_V4 && cfun->calls_alloca) |
022123e6 AM |
14772 | || info_ptr->calls_p |
14773 | || rs6000_ra_ever_killed ()) | |
4697a36c MM |
14774 | { |
14775 | info_ptr->lr_save_p = 1; | |
1de43f85 | 14776 | df_set_regs_ever_live (LR_REGNO, true); |
4697a36c MM |
14777 | } |
14778 | ||
9ebbca7d | 14779 | /* Determine if we need to save the condition code registers. */ |
6fb5fa3c DB |
14780 | if (df_regs_ever_live_p (CR2_REGNO) |
14781 | || df_regs_ever_live_p (CR3_REGNO) | |
14782 | || df_regs_ever_live_p (CR4_REGNO)) | |
4697a36c MM |
14783 | { |
14784 | info_ptr->cr_save_p = 1; | |
178274da | 14785 | if (DEFAULT_ABI == ABI_V4) |
4697a36c MM |
14786 | info_ptr->cr_size = reg_size; |
14787 | } | |
14788 | ||
83720594 RH |
14789 | /* If the current function calls __builtin_eh_return, then we need |
14790 | to allocate stack space for registers that will hold data for | |
14791 | the exception handler. */ | |
e3b5732b | 14792 | if (crtl->calls_eh_return) |
83720594 RH |
14793 | { |
14794 | unsigned int i; | |
14795 | for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; ++i) | |
14796 | continue; | |
a3170dc6 AH |
14797 | |
14798 | /* SPE saves EH registers in 64-bits. */ | |
c19de7aa AH |
14799 | ehrd_size = i * (TARGET_SPE_ABI |
14800 | && info_ptr->spe_64bit_regs_used != 0 | |
14801 | ? UNITS_PER_SPE_WORD : UNITS_PER_WORD); | |
83720594 RH |
14802 | } |
14803 | else | |
14804 | ehrd_size = 0; | |
14805 | ||
592696dd | 14806 | /* Determine various sizes. */ |
4697a36c MM |
14807 | info_ptr->reg_size = reg_size; |
14808 | info_ptr->fixed_size = RS6000_SAVE_AREA; | |
189e03e3 | 14809 | info_ptr->vars_size = RS6000_ALIGN (get_frame_size (), 8); |
38173d38 | 14810 | info_ptr->parm_size = RS6000_ALIGN (crtl->outgoing_args_size, |
03e007d7 | 14811 | TARGET_ALTIVEC ? 16 : 8); |
7d5175e1 JJ |
14812 | if (FRAME_GROWS_DOWNWARD) |
14813 | info_ptr->vars_size | |
5b667039 JJ |
14814 | += RS6000_ALIGN (info_ptr->fixed_size + info_ptr->vars_size |
14815 | + info_ptr->parm_size, | |
7d5175e1 | 14816 | ABI_STACK_BOUNDARY / BITS_PER_UNIT) |
5b667039 JJ |
14817 | - (info_ptr->fixed_size + info_ptr->vars_size |
14818 | + info_ptr->parm_size); | |
00b960c7 | 14819 | |
c19de7aa | 14820 | if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0) |
8070c91a | 14821 | info_ptr->spe_gp_size = 8 * (32 - first_gp); |
a3170dc6 AH |
14822 | else |
14823 | info_ptr->spe_gp_size = 0; | |
14824 | ||
4d774ff8 HP |
14825 | if (TARGET_ALTIVEC_ABI) |
14826 | info_ptr->vrsave_mask = compute_vrsave_mask (); | |
00b960c7 | 14827 | else |
4d774ff8 HP |
14828 | info_ptr->vrsave_mask = 0; |
14829 | ||
14830 | if (TARGET_ALTIVEC_VRSAVE && info_ptr->vrsave_mask) | |
14831 | info_ptr->vrsave_size = 4; | |
14832 | else | |
14833 | info_ptr->vrsave_size = 0; | |
b6c9286a | 14834 | |
d62294f5 FJ |
14835 | compute_save_world_info (info_ptr); |
14836 | ||
592696dd | 14837 | /* Calculate the offsets. */ |
178274da | 14838 | switch (DEFAULT_ABI) |
4697a36c | 14839 | { |
b6c9286a | 14840 | case ABI_NONE: |
24d304eb | 14841 | default: |
37409796 | 14842 | gcc_unreachable (); |
b6c9286a MM |
14843 | |
14844 | case ABI_AIX: | |
ee890fe2 | 14845 | case ABI_DARWIN: |
b6c9286a MM |
14846 | info_ptr->fp_save_offset = - info_ptr->fp_size; |
14847 | info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size; | |
00b960c7 AH |
14848 | |
14849 | if (TARGET_ALTIVEC_ABI) | |
14850 | { | |
14851 | info_ptr->vrsave_save_offset | |
14852 | = info_ptr->gp_save_offset - info_ptr->vrsave_size; | |
14853 | ||
982afe02 | 14854 | /* Align stack so vector save area is on a quadword boundary. |
9278121c | 14855 | The padding goes above the vectors. */ |
00b960c7 AH |
14856 | if (info_ptr->altivec_size != 0) |
14857 | info_ptr->altivec_padding_size | |
9278121c | 14858 | = info_ptr->vrsave_save_offset & 0xF; |
00b960c7 AH |
14859 | else |
14860 | info_ptr->altivec_padding_size = 0; | |
14861 | ||
14862 | info_ptr->altivec_save_offset | |
14863 | = info_ptr->vrsave_save_offset | |
14864 | - info_ptr->altivec_padding_size | |
14865 | - info_ptr->altivec_size; | |
9278121c GK |
14866 | gcc_assert (info_ptr->altivec_size == 0 |
14867 | || info_ptr->altivec_save_offset % 16 == 0); | |
00b960c7 AH |
14868 | |
14869 | /* Adjust for AltiVec case. */ | |
14870 | info_ptr->ehrd_offset = info_ptr->altivec_save_offset - ehrd_size; | |
14871 | } | |
14872 | else | |
14873 | info_ptr->ehrd_offset = info_ptr->gp_save_offset - ehrd_size; | |
a260abc9 DE |
14874 | info_ptr->cr_save_offset = reg_size; /* first word when 64-bit. */ |
14875 | info_ptr->lr_save_offset = 2*reg_size; | |
24d304eb RK |
14876 | break; |
14877 | ||
14878 | case ABI_V4: | |
b6c9286a MM |
14879 | info_ptr->fp_save_offset = - info_ptr->fp_size; |
14880 | info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size; | |
a7df97e6 | 14881 | info_ptr->cr_save_offset = info_ptr->gp_save_offset - info_ptr->cr_size; |
00b960c7 | 14882 | |
c19de7aa | 14883 | if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0) |
c4ad648e AM |
14884 | { |
14885 | /* Align stack so SPE GPR save area is aligned on a | |
14886 | double-word boundary. */ | |
f78c3290 | 14887 | if (info_ptr->spe_gp_size != 0 && info_ptr->cr_save_offset != 0) |
c4ad648e AM |
14888 | info_ptr->spe_padding_size |
14889 | = 8 - (-info_ptr->cr_save_offset % 8); | |
14890 | else | |
14891 | info_ptr->spe_padding_size = 0; | |
14892 | ||
14893 | info_ptr->spe_gp_save_offset | |
14894 | = info_ptr->cr_save_offset | |
14895 | - info_ptr->spe_padding_size | |
14896 | - info_ptr->spe_gp_size; | |
14897 | ||
14898 | /* Adjust for SPE case. */ | |
022123e6 | 14899 | info_ptr->ehrd_offset = info_ptr->spe_gp_save_offset; |
c4ad648e | 14900 | } |
a3170dc6 | 14901 | else if (TARGET_ALTIVEC_ABI) |
00b960c7 AH |
14902 | { |
14903 | info_ptr->vrsave_save_offset | |
14904 | = info_ptr->cr_save_offset - info_ptr->vrsave_size; | |
14905 | ||
14906 | /* Align stack so vector save area is on a quadword boundary. */ | |
14907 | if (info_ptr->altivec_size != 0) | |
14908 | info_ptr->altivec_padding_size | |
14909 | = 16 - (-info_ptr->vrsave_save_offset % 16); | |
14910 | else | |
14911 | info_ptr->altivec_padding_size = 0; | |
14912 | ||
14913 | info_ptr->altivec_save_offset | |
14914 | = info_ptr->vrsave_save_offset | |
14915 | - info_ptr->altivec_padding_size | |
14916 | - info_ptr->altivec_size; | |
14917 | ||
14918 | /* Adjust for AltiVec case. */ | |
022123e6 | 14919 | info_ptr->ehrd_offset = info_ptr->altivec_save_offset; |
00b960c7 AH |
14920 | } |
14921 | else | |
022123e6 AM |
14922 | info_ptr->ehrd_offset = info_ptr->cr_save_offset; |
14923 | info_ptr->ehrd_offset -= ehrd_size; | |
b6c9286a MM |
14924 | info_ptr->lr_save_offset = reg_size; |
14925 | break; | |
4697a36c MM |
14926 | } |
14927 | ||
64045029 | 14928 | save_align = (TARGET_ALTIVEC_ABI || DEFAULT_ABI == ABI_DARWIN) ? 16 : 8; |
00b960c7 AH |
14929 | info_ptr->save_size = RS6000_ALIGN (info_ptr->fp_size |
14930 | + info_ptr->gp_size | |
14931 | + info_ptr->altivec_size | |
14932 | + info_ptr->altivec_padding_size | |
a3170dc6 AH |
14933 | + info_ptr->spe_gp_size |
14934 | + info_ptr->spe_padding_size | |
00b960c7 AH |
14935 | + ehrd_size |
14936 | + info_ptr->cr_size | |
022123e6 | 14937 | + info_ptr->vrsave_size, |
64045029 | 14938 | save_align); |
00b960c7 | 14939 | |
44688022 | 14940 | non_fixed_size = (info_ptr->vars_size |
ff381587 | 14941 | + info_ptr->parm_size |
5b667039 | 14942 | + info_ptr->save_size); |
ff381587 | 14943 | |
44688022 AM |
14944 | info_ptr->total_size = RS6000_ALIGN (non_fixed_size + info_ptr->fixed_size, |
14945 | ABI_STACK_BOUNDARY / BITS_PER_UNIT); | |
ff381587 MM |
14946 | |
14947 | /* Determine if we need to allocate any stack frame: | |
14948 | ||
a4f6c312 SS |
14949 | For AIX we need to push the stack if a frame pointer is needed |
14950 | (because the stack might be dynamically adjusted), if we are | |
14951 | debugging, if we make calls, or if the sum of fp_save, gp_save, | |
14952 | and local variables are more than the space needed to save all | |
14953 | non-volatile registers: 32-bit: 18*8 + 19*4 = 220 or 64-bit: 18*8 | |
14954 | + 18*8 = 288 (GPR13 reserved). | |
ff381587 | 14955 | |
a4f6c312 SS |
14956 | For V.4 we don't have the stack cushion that AIX uses, but assume |
14957 | that the debugger can handle stackless frames. */ | |
ff381587 MM |
14958 | |
14959 | if (info_ptr->calls_p) | |
14960 | info_ptr->push_p = 1; | |
14961 | ||
178274da | 14962 | else if (DEFAULT_ABI == ABI_V4) |
44688022 | 14963 | info_ptr->push_p = non_fixed_size != 0; |
ff381587 | 14964 | |
178274da AM |
14965 | else if (frame_pointer_needed) |
14966 | info_ptr->push_p = 1; | |
14967 | ||
14968 | else if (TARGET_XCOFF && write_symbols != NO_DEBUG) | |
14969 | info_ptr->push_p = 1; | |
14970 | ||
ff381587 | 14971 | else |
44688022 | 14972 | info_ptr->push_p = non_fixed_size > (TARGET_32BIT ? 220 : 288); |
ff381587 | 14973 | |
a4f6c312 | 14974 | /* Zero offsets if we're not saving those registers. */ |
8dda1a21 | 14975 | if (info_ptr->fp_size == 0) |
4697a36c MM |
14976 | info_ptr->fp_save_offset = 0; |
14977 | ||
8dda1a21 | 14978 | if (info_ptr->gp_size == 0) |
4697a36c MM |
14979 | info_ptr->gp_save_offset = 0; |
14980 | ||
00b960c7 AH |
14981 | if (! TARGET_ALTIVEC_ABI || info_ptr->altivec_size == 0) |
14982 | info_ptr->altivec_save_offset = 0; | |
14983 | ||
14984 | if (! TARGET_ALTIVEC_ABI || info_ptr->vrsave_mask == 0) | |
14985 | info_ptr->vrsave_save_offset = 0; | |
14986 | ||
c19de7aa AH |
14987 | if (! TARGET_SPE_ABI |
14988 | || info_ptr->spe_64bit_regs_used == 0 | |
14989 | || info_ptr->spe_gp_size == 0) | |
a3170dc6 AH |
14990 | info_ptr->spe_gp_save_offset = 0; |
14991 | ||
c81fc13e | 14992 | if (! info_ptr->lr_save_p) |
4697a36c MM |
14993 | info_ptr->lr_save_offset = 0; |
14994 | ||
c81fc13e | 14995 | if (! info_ptr->cr_save_p) |
4697a36c MM |
14996 | info_ptr->cr_save_offset = 0; |
14997 | ||
14998 | return info_ptr; | |
14999 | } | |
15000 | ||
c19de7aa AH |
15001 | /* Return true if the current function uses any GPRs in 64-bit SIMD |
15002 | mode. */ | |
15003 | ||
15004 | static bool | |
863d938c | 15005 | spe_func_has_64bit_regs_p (void) |
c19de7aa AH |
15006 | { |
15007 | rtx insns, insn; | |
15008 | ||
15009 | /* Functions that save and restore all the call-saved registers will | |
15010 | need to save/restore the registers in 64-bits. */ | |
e3b5732b JH |
15011 | if (crtl->calls_eh_return |
15012 | || cfun->calls_setjmp | |
15013 | || crtl->has_nonlocal_goto) | |
c19de7aa AH |
15014 | return true; |
15015 | ||
15016 | insns = get_insns (); | |
15017 | ||
15018 | for (insn = NEXT_INSN (insns); insn != NULL_RTX; insn = NEXT_INSN (insn)) | |
15019 | { | |
15020 | if (INSN_P (insn)) | |
15021 | { | |
15022 | rtx i; | |
15023 | ||
b5a5beb9 AH |
15024 | /* FIXME: This should be implemented with attributes... |
15025 | ||
15026 | (set_attr "spe64" "true")....then, | |
15027 | if (get_spe64(insn)) return true; | |
15028 | ||
15029 | It's the only reliable way to do the stuff below. */ | |
15030 | ||
c19de7aa | 15031 | i = PATTERN (insn); |
f82f556d AH |
15032 | if (GET_CODE (i) == SET) |
15033 | { | |
15034 | enum machine_mode mode = GET_MODE (SET_SRC (i)); | |
15035 | ||
15036 | if (SPE_VECTOR_MODE (mode)) | |
15037 | return true; | |
4f011e1e | 15038 | if (TARGET_E500_DOUBLE && (mode == DFmode || mode == TFmode)) |
f82f556d AH |
15039 | return true; |
15040 | } | |
c19de7aa AH |
15041 | } |
15042 | } | |
15043 | ||
15044 | return false; | |
15045 | } | |
15046 | ||
d1d0c603 | 15047 | static void |
a2369ed3 | 15048 | debug_stack_info (rs6000_stack_t *info) |
9878760c | 15049 | { |
d330fd93 | 15050 | const char *abi_string; |
24d304eb | 15051 | |
c81fc13e | 15052 | if (! info) |
4697a36c MM |
15053 | info = rs6000_stack_info (); |
15054 | ||
15055 | fprintf (stderr, "\nStack information for function %s:\n", | |
15056 | ((current_function_decl && DECL_NAME (current_function_decl)) | |
15057 | ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl)) | |
15058 | : "<unknown>")); | |
15059 | ||
24d304eb RK |
15060 | switch (info->abi) |
15061 | { | |
b6c9286a MM |
15062 | default: abi_string = "Unknown"; break; |
15063 | case ABI_NONE: abi_string = "NONE"; break; | |
50d440bc | 15064 | case ABI_AIX: abi_string = "AIX"; break; |
ee890fe2 | 15065 | case ABI_DARWIN: abi_string = "Darwin"; break; |
b6c9286a | 15066 | case ABI_V4: abi_string = "V.4"; break; |
24d304eb RK |
15067 | } |
15068 | ||
15069 | fprintf (stderr, "\tABI = %5s\n", abi_string); | |
15070 | ||
00b960c7 AH |
15071 | if (TARGET_ALTIVEC_ABI) |
15072 | fprintf (stderr, "\tALTIVEC ABI extensions enabled.\n"); | |
15073 | ||
a3170dc6 AH |
15074 | if (TARGET_SPE_ABI) |
15075 | fprintf (stderr, "\tSPE ABI extensions enabled.\n"); | |
15076 | ||
4697a36c MM |
15077 | if (info->first_gp_reg_save != 32) |
15078 | fprintf (stderr, "\tfirst_gp_reg_save = %5d\n", info->first_gp_reg_save); | |
15079 | ||
15080 | if (info->first_fp_reg_save != 64) | |
15081 | fprintf (stderr, "\tfirst_fp_reg_save = %5d\n", info->first_fp_reg_save); | |
9878760c | 15082 | |
00b960c7 AH |
15083 | if (info->first_altivec_reg_save <= LAST_ALTIVEC_REGNO) |
15084 | fprintf (stderr, "\tfirst_altivec_reg_save = %5d\n", | |
15085 | info->first_altivec_reg_save); | |
15086 | ||
4697a36c MM |
15087 | if (info->lr_save_p) |
15088 | fprintf (stderr, "\tlr_save_p = %5d\n", info->lr_save_p); | |
9878760c | 15089 | |
4697a36c MM |
15090 | if (info->cr_save_p) |
15091 | fprintf (stderr, "\tcr_save_p = %5d\n", info->cr_save_p); | |
15092 | ||
00b960c7 AH |
15093 | if (info->vrsave_mask) |
15094 | fprintf (stderr, "\tvrsave_mask = 0x%x\n", info->vrsave_mask); | |
15095 | ||
4697a36c MM |
15096 | if (info->push_p) |
15097 | fprintf (stderr, "\tpush_p = %5d\n", info->push_p); | |
15098 | ||
15099 | if (info->calls_p) | |
15100 | fprintf (stderr, "\tcalls_p = %5d\n", info->calls_p); | |
15101 | ||
4697a36c MM |
15102 | if (info->gp_save_offset) |
15103 | fprintf (stderr, "\tgp_save_offset = %5d\n", info->gp_save_offset); | |
15104 | ||
15105 | if (info->fp_save_offset) | |
15106 | fprintf (stderr, "\tfp_save_offset = %5d\n", info->fp_save_offset); | |
15107 | ||
00b960c7 AH |
15108 | if (info->altivec_save_offset) |
15109 | fprintf (stderr, "\taltivec_save_offset = %5d\n", | |
15110 | info->altivec_save_offset); | |
15111 | ||
a3170dc6 AH |
15112 | if (info->spe_gp_save_offset) |
15113 | fprintf (stderr, "\tspe_gp_save_offset = %5d\n", | |
15114 | info->spe_gp_save_offset); | |
15115 | ||
00b960c7 AH |
15116 | if (info->vrsave_save_offset) |
15117 | fprintf (stderr, "\tvrsave_save_offset = %5d\n", | |
15118 | info->vrsave_save_offset); | |
15119 | ||
4697a36c MM |
15120 | if (info->lr_save_offset) |
15121 | fprintf (stderr, "\tlr_save_offset = %5d\n", info->lr_save_offset); | |
15122 | ||
15123 | if (info->cr_save_offset) | |
15124 | fprintf (stderr, "\tcr_save_offset = %5d\n", info->cr_save_offset); | |
15125 | ||
15126 | if (info->varargs_save_offset) | |
15127 | fprintf (stderr, "\tvarargs_save_offset = %5d\n", info->varargs_save_offset); | |
15128 | ||
15129 | if (info->total_size) | |
d1d0c603 JJ |
15130 | fprintf (stderr, "\ttotal_size = "HOST_WIDE_INT_PRINT_DEC"\n", |
15131 | info->total_size); | |
4697a36c | 15132 | |
4697a36c | 15133 | if (info->vars_size) |
d1d0c603 JJ |
15134 | fprintf (stderr, "\tvars_size = "HOST_WIDE_INT_PRINT_DEC"\n", |
15135 | info->vars_size); | |
4697a36c MM |
15136 | |
15137 | if (info->parm_size) | |
15138 | fprintf (stderr, "\tparm_size = %5d\n", info->parm_size); | |
15139 | ||
15140 | if (info->fixed_size) | |
15141 | fprintf (stderr, "\tfixed_size = %5d\n", info->fixed_size); | |
15142 | ||
15143 | if (info->gp_size) | |
15144 | fprintf (stderr, "\tgp_size = %5d\n", info->gp_size); | |
15145 | ||
a3170dc6 AH |
15146 | if (info->spe_gp_size) |
15147 | fprintf (stderr, "\tspe_gp_size = %5d\n", info->spe_gp_size); | |
15148 | ||
4697a36c MM |
15149 | if (info->fp_size) |
15150 | fprintf (stderr, "\tfp_size = %5d\n", info->fp_size); | |
15151 | ||
00b960c7 AH |
15152 | if (info->altivec_size) |
15153 | fprintf (stderr, "\taltivec_size = %5d\n", info->altivec_size); | |
15154 | ||
15155 | if (info->vrsave_size) | |
15156 | fprintf (stderr, "\tvrsave_size = %5d\n", info->vrsave_size); | |
15157 | ||
15158 | if (info->altivec_padding_size) | |
15159 | fprintf (stderr, "\taltivec_padding_size= %5d\n", | |
15160 | info->altivec_padding_size); | |
15161 | ||
a3170dc6 AH |
15162 | if (info->spe_padding_size) |
15163 | fprintf (stderr, "\tspe_padding_size = %5d\n", | |
15164 | info->spe_padding_size); | |
15165 | ||
4697a36c MM |
15166 | if (info->cr_size) |
15167 | fprintf (stderr, "\tcr_size = %5d\n", info->cr_size); | |
15168 | ||
15169 | if (info->save_size) | |
15170 | fprintf (stderr, "\tsave_size = %5d\n", info->save_size); | |
15171 | ||
15172 | if (info->reg_size != 4) | |
15173 | fprintf (stderr, "\treg_size = %5d\n", info->reg_size); | |
15174 | ||
15175 | fprintf (stderr, "\n"); | |
9878760c | 15176 | } |
71f123ca FS |
15177 | |
15178 | rtx | |
a2369ed3 | 15179 | rs6000_return_addr (int count, rtx frame) |
71f123ca | 15180 | { |
a4f6c312 SS |
15181 | /* Currently we don't optimize very well between prolog and body |
15182 | code and for PIC code the code can be actually quite bad, so | |
15183 | don't try to be too clever here. */ | |
f1384257 | 15184 | if (count != 0 || (DEFAULT_ABI != ABI_AIX && flag_pic)) |
71f123ca FS |
15185 | { |
15186 | cfun->machine->ra_needs_full_frame = 1; | |
8ac61af7 RK |
15187 | |
15188 | return | |
15189 | gen_rtx_MEM | |
15190 | (Pmode, | |
15191 | memory_address | |
15192 | (Pmode, | |
15193 | plus_constant (copy_to_reg | |
15194 | (gen_rtx_MEM (Pmode, | |
15195 | memory_address (Pmode, frame))), | |
15196 | RETURN_ADDRESS_OFFSET))); | |
71f123ca FS |
15197 | } |
15198 | ||
8c29550d | 15199 | cfun->machine->ra_need_lr = 1; |
1de43f85 | 15200 | return get_hard_reg_initial_val (Pmode, LR_REGNO); |
71f123ca FS |
15201 | } |
15202 | ||
5e1bf043 DJ |
15203 | /* Say whether a function is a candidate for sibcall handling or not. |
15204 | We do not allow indirect calls to be optimized into sibling calls. | |
15205 | Also, we can't do it if there are any vector parameters; there's | |
15206 | nowhere to put the VRsave code so it works; note that functions with | |
15207 | vector parameters are required to have a prototype, so the argument | |
15208 | type info must be available here. (The tail recursion case can work | |
15209 | with vector parameters, but there's no way to distinguish here.) */ | |
4977bab6 | 15210 | static bool |
a2369ed3 | 15211 | rs6000_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED) |
5e1bf043 DJ |
15212 | { |
15213 | tree type; | |
4977bab6 | 15214 | if (decl) |
5e1bf043 DJ |
15215 | { |
15216 | if (TARGET_ALTIVEC_VRSAVE) | |
c4ad648e | 15217 | { |
4977bab6 | 15218 | for (type = TYPE_ARG_TYPES (TREE_TYPE (decl)); |
5e1bf043 DJ |
15219 | type; type = TREE_CHAIN (type)) |
15220 | { | |
c15b529f | 15221 | if (TREE_CODE (TREE_VALUE (type)) == VECTOR_TYPE) |
4977bab6 | 15222 | return false; |
5e1bf043 | 15223 | } |
c4ad648e | 15224 | } |
5e1bf043 | 15225 | if (DEFAULT_ABI == ABI_DARWIN |
8aa19d95 JJ |
15226 | || ((*targetm.binds_local_p) (decl) |
15227 | && (DEFAULT_ABI != ABI_AIX || !DECL_EXTERNAL (decl)))) | |
2bcc50d0 | 15228 | { |
4977bab6 | 15229 | tree attr_list = TYPE_ATTRIBUTES (TREE_TYPE (decl)); |
2bcc50d0 AM |
15230 | |
15231 | if (!lookup_attribute ("longcall", attr_list) | |
15232 | || lookup_attribute ("shortcall", attr_list)) | |
4977bab6 | 15233 | return true; |
2bcc50d0 | 15234 | } |
5e1bf043 | 15235 | } |
4977bab6 | 15236 | return false; |
5e1bf043 DJ |
15237 | } |
15238 | ||
e7e64a25 AS |
15239 | /* NULL if INSN insn is valid within a low-overhead loop. |
15240 | Otherwise return why doloop cannot be applied. | |
9419649c DE |
15241 | PowerPC uses the COUNT register for branch on table instructions. */ |
15242 | ||
e7e64a25 | 15243 | static const char * |
3101faab | 15244 | rs6000_invalid_within_doloop (const_rtx insn) |
9419649c DE |
15245 | { |
15246 | if (CALL_P (insn)) | |
e7e64a25 | 15247 | return "Function call in the loop."; |
9419649c DE |
15248 | |
15249 | if (JUMP_P (insn) | |
15250 | && (GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC | |
15251 | || GET_CODE (PATTERN (insn)) == ADDR_VEC)) | |
e7e64a25 | 15252 | return "Computed branch in the loop."; |
9419649c | 15253 | |
e7e64a25 | 15254 | return NULL; |
9419649c DE |
15255 | } |
15256 | ||
71f123ca | 15257 | static int |
863d938c | 15258 | rs6000_ra_ever_killed (void) |
71f123ca FS |
15259 | { |
15260 | rtx top; | |
5e1bf043 DJ |
15261 | rtx reg; |
15262 | rtx insn; | |
71f123ca | 15263 | |
3c072c6b | 15264 | if (cfun->is_thunk) |
71f123ca | 15265 | return 0; |
eb0424da | 15266 | |
36f7e964 AH |
15267 | /* regs_ever_live has LR marked as used if any sibcalls are present, |
15268 | but this should not force saving and restoring in the | |
15269 | pro/epilogue. Likewise, reg_set_between_p thinks a sibcall | |
a3c9585f | 15270 | clobbers LR, so that is inappropriate. */ |
36f7e964 | 15271 | |
5e1bf043 DJ |
15272 | /* Also, the prologue can generate a store into LR that |
15273 | doesn't really count, like this: | |
36f7e964 | 15274 | |
5e1bf043 DJ |
15275 | move LR->R0 |
15276 | bcl to set PIC register | |
15277 | move LR->R31 | |
15278 | move R0->LR | |
36f7e964 AH |
15279 | |
15280 | When we're called from the epilogue, we need to avoid counting | |
15281 | this as a store. */ | |
f676971a | 15282 | |
71f123ca FS |
15283 | push_topmost_sequence (); |
15284 | top = get_insns (); | |
15285 | pop_topmost_sequence (); | |
1de43f85 | 15286 | reg = gen_rtx_REG (Pmode, LR_REGNO); |
71f123ca | 15287 | |
5e1bf043 DJ |
15288 | for (insn = NEXT_INSN (top); insn != NULL_RTX; insn = NEXT_INSN (insn)) |
15289 | { | |
15290 | if (INSN_P (insn)) | |
15291 | { | |
022123e6 AM |
15292 | if (CALL_P (insn)) |
15293 | { | |
15294 | if (!SIBLING_CALL_P (insn)) | |
15295 | return 1; | |
15296 | } | |
1de43f85 | 15297 | else if (find_regno_note (insn, REG_INC, LR_REGNO)) |
5e1bf043 | 15298 | return 1; |
36f7e964 AH |
15299 | else if (set_of (reg, insn) != NULL_RTX |
15300 | && !prologue_epilogue_contains (insn)) | |
5e1bf043 DJ |
15301 | return 1; |
15302 | } | |
15303 | } | |
15304 | return 0; | |
71f123ca | 15305 | } |
4697a36c | 15306 | \f |
9ebbca7d | 15307 | /* Emit instructions needed to load the TOC register. |
c7ca610e | 15308 | This is only needed when TARGET_TOC, TARGET_MINIMAL_TOC, and there is |
9ebbca7d | 15309 | a constant pool; or for SVR4 -fpic. */ |
c7ca610e RK |
15310 | |
15311 | void | |
a2369ed3 | 15312 | rs6000_emit_load_toc_table (int fromprolog) |
c7ca610e | 15313 | { |
6fb5fa3c | 15314 | rtx dest; |
1db02437 | 15315 | dest = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM); |
c7ca610e | 15316 | |
7f970b70 | 15317 | if (TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic) |
20b71b17 | 15318 | { |
7f970b70 | 15319 | char buf[30]; |
e65a3857 | 15320 | rtx lab, tmp1, tmp2, got; |
7f970b70 AM |
15321 | |
15322 | ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno); | |
15323 | lab = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); | |
15324 | if (flag_pic == 2) | |
15325 | got = gen_rtx_SYMBOL_REF (Pmode, toc_label_name); | |
15326 | else | |
15327 | got = rs6000_got_sym (); | |
15328 | tmp1 = tmp2 = dest; | |
15329 | if (!fromprolog) | |
15330 | { | |
15331 | tmp1 = gen_reg_rtx (Pmode); | |
15332 | tmp2 = gen_reg_rtx (Pmode); | |
15333 | } | |
6fb5fa3c DB |
15334 | emit_insn (gen_load_toc_v4_PIC_1 (lab)); |
15335 | emit_move_insn (tmp1, | |
1de43f85 | 15336 | gen_rtx_REG (Pmode, LR_REGNO)); |
6fb5fa3c DB |
15337 | emit_insn (gen_load_toc_v4_PIC_3b (tmp2, tmp1, got, lab)); |
15338 | emit_insn (gen_load_toc_v4_PIC_3c (dest, tmp2, got, lab)); | |
7f970b70 AM |
15339 | } |
15340 | else if (TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 1) | |
15341 | { | |
6fb5fa3c | 15342 | emit_insn (gen_load_toc_v4_pic_si ()); |
1de43f85 | 15343 | emit_move_insn (dest, gen_rtx_REG (Pmode, LR_REGNO)); |
20b71b17 AM |
15344 | } |
15345 | else if (TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2) | |
15346 | { | |
15347 | char buf[30]; | |
20b71b17 AM |
15348 | rtx temp0 = (fromprolog |
15349 | ? gen_rtx_REG (Pmode, 0) | |
15350 | : gen_reg_rtx (Pmode)); | |
20b71b17 | 15351 | |
20b71b17 AM |
15352 | if (fromprolog) |
15353 | { | |
ccbca5e4 | 15354 | rtx symF, symL; |
38c1f2d7 | 15355 | |
20b71b17 AM |
15356 | ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno); |
15357 | symF = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); | |
9ebbca7d | 15358 | |
20b71b17 AM |
15359 | ASM_GENERATE_INTERNAL_LABEL (buf, "LCL", rs6000_pic_labelno); |
15360 | symL = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); | |
15361 | ||
6fb5fa3c DB |
15362 | emit_insn (gen_load_toc_v4_PIC_1 (symF)); |
15363 | emit_move_insn (dest, | |
1de43f85 | 15364 | gen_rtx_REG (Pmode, LR_REGNO)); |
6fb5fa3c | 15365 | emit_insn (gen_load_toc_v4_PIC_2 (temp0, dest, symL, symF)); |
9ebbca7d GK |
15366 | } |
15367 | else | |
20b71b17 AM |
15368 | { |
15369 | rtx tocsym; | |
20b71b17 AM |
15370 | |
15371 | tocsym = gen_rtx_SYMBOL_REF (Pmode, toc_label_name); | |
e65a3857 DE |
15372 | emit_insn (gen_load_toc_v4_PIC_1b (tocsym)); |
15373 | emit_move_insn (dest, | |
1de43f85 | 15374 | gen_rtx_REG (Pmode, LR_REGNO)); |
027fbf43 | 15375 | emit_move_insn (temp0, gen_rtx_MEM (Pmode, dest)); |
20b71b17 | 15376 | } |
6fb5fa3c | 15377 | emit_insn (gen_addsi3 (dest, temp0, dest)); |
9ebbca7d | 15378 | } |
20b71b17 AM |
15379 | else if (TARGET_ELF && !TARGET_AIX && flag_pic == 0 && TARGET_MINIMAL_TOC) |
15380 | { | |
15381 | /* This is for AIX code running in non-PIC ELF32. */ | |
15382 | char buf[30]; | |
15383 | rtx realsym; | |
15384 | ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1); | |
15385 | realsym = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); | |
15386 | ||
6fb5fa3c DB |
15387 | emit_insn (gen_elf_high (dest, realsym)); |
15388 | emit_insn (gen_elf_low (dest, dest, realsym)); | |
20b71b17 | 15389 | } |
37409796 | 15390 | else |
9ebbca7d | 15391 | { |
37409796 | 15392 | gcc_assert (DEFAULT_ABI == ABI_AIX); |
bb8df8a6 | 15393 | |
9ebbca7d | 15394 | if (TARGET_32BIT) |
6fb5fa3c | 15395 | emit_insn (gen_load_toc_aix_si (dest)); |
9ebbca7d | 15396 | else |
6fb5fa3c | 15397 | emit_insn (gen_load_toc_aix_di (dest)); |
9ebbca7d GK |
15398 | } |
15399 | } | |
15400 | ||
d1d0c603 JJ |
15401 | /* Emit instructions to restore the link register after determining where |
15402 | its value has been stored. */ | |
15403 | ||
15404 | void | |
15405 | rs6000_emit_eh_reg_restore (rtx source, rtx scratch) | |
15406 | { | |
15407 | rs6000_stack_t *info = rs6000_stack_info (); | |
15408 | rtx operands[2]; | |
15409 | ||
15410 | operands[0] = source; | |
15411 | operands[1] = scratch; | |
15412 | ||
15413 | if (info->lr_save_p) | |
15414 | { | |
15415 | rtx frame_rtx = stack_pointer_rtx; | |
15416 | HOST_WIDE_INT sp_offset = 0; | |
15417 | rtx tmp; | |
15418 | ||
15419 | if (frame_pointer_needed | |
e3b5732b | 15420 | || cfun->calls_alloca |
d1d0c603 JJ |
15421 | || info->total_size > 32767) |
15422 | { | |
0be76840 | 15423 | tmp = gen_frame_mem (Pmode, frame_rtx); |
8308679f | 15424 | emit_move_insn (operands[1], tmp); |
d1d0c603 JJ |
15425 | frame_rtx = operands[1]; |
15426 | } | |
15427 | else if (info->push_p) | |
15428 | sp_offset = info->total_size; | |
15429 | ||
15430 | tmp = plus_constant (frame_rtx, info->lr_save_offset + sp_offset); | |
0be76840 | 15431 | tmp = gen_frame_mem (Pmode, tmp); |
d1d0c603 JJ |
15432 | emit_move_insn (tmp, operands[0]); |
15433 | } | |
15434 | else | |
1de43f85 | 15435 | emit_move_insn (gen_rtx_REG (Pmode, LR_REGNO), operands[0]); |
d1d0c603 JJ |
15436 | } |
15437 | ||
4862826d | 15438 | static GTY(()) alias_set_type set = -1; |
f103e34d | 15439 | |
4862826d | 15440 | alias_set_type |
863d938c | 15441 | get_TOC_alias_set (void) |
9ebbca7d | 15442 | { |
f103e34d GK |
15443 | if (set == -1) |
15444 | set = new_alias_set (); | |
15445 | return set; | |
f676971a | 15446 | } |
9ebbca7d | 15447 | |
c1207243 | 15448 | /* This returns nonzero if the current function uses the TOC. This is |
3c9eb5f4 AM |
15449 | determined by the presence of (use (unspec ... UNSPEC_TOC)), which |
15450 | is generated by the ABI_V4 load_toc_* patterns. */ | |
c954844a | 15451 | #if TARGET_ELF |
3c9eb5f4 | 15452 | static int |
f676971a | 15453 | uses_TOC (void) |
9ebbca7d | 15454 | { |
c4501e62 | 15455 | rtx insn; |
38c1f2d7 | 15456 | |
c4501e62 JJ |
15457 | for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) |
15458 | if (INSN_P (insn)) | |
15459 | { | |
15460 | rtx pat = PATTERN (insn); | |
15461 | int i; | |
9ebbca7d | 15462 | |
f676971a | 15463 | if (GET_CODE (pat) == PARALLEL) |
c4501e62 JJ |
15464 | for (i = 0; i < XVECLEN (pat, 0); i++) |
15465 | { | |
15466 | rtx sub = XVECEXP (pat, 0, i); | |
15467 | if (GET_CODE (sub) == USE) | |
15468 | { | |
15469 | sub = XEXP (sub, 0); | |
15470 | if (GET_CODE (sub) == UNSPEC | |
15471 | && XINT (sub, 1) == UNSPEC_TOC) | |
15472 | return 1; | |
15473 | } | |
15474 | } | |
15475 | } | |
15476 | return 0; | |
9ebbca7d | 15477 | } |
c954844a | 15478 | #endif |
38c1f2d7 | 15479 | |
9ebbca7d | 15480 | rtx |
f676971a | 15481 | create_TOC_reference (rtx symbol) |
9ebbca7d | 15482 | { |
b3a13419 | 15483 | if (!can_create_pseudo_p ()) |
6fb5fa3c | 15484 | df_set_regs_ever_live (TOC_REGISTER, true); |
f676971a | 15485 | return gen_rtx_PLUS (Pmode, |
a8a05998 | 15486 | gen_rtx_REG (Pmode, TOC_REGISTER), |
f676971a | 15487 | gen_rtx_CONST (Pmode, |
2e4316da | 15488 | gen_rtx_UNSPEC (Pmode, gen_rtvec (1, symbol), UNSPEC_TOCREL))); |
9ebbca7d | 15489 | } |
38c1f2d7 | 15490 | |
fc4767bb JJ |
15491 | /* If _Unwind_* has been called from within the same module, |
15492 | toc register is not guaranteed to be saved to 40(1) on function | |
15493 | entry. Save it there in that case. */ | |
c7ca610e | 15494 | |
9ebbca7d | 15495 | void |
863d938c | 15496 | rs6000_aix_emit_builtin_unwind_init (void) |
9ebbca7d GK |
15497 | { |
15498 | rtx mem; | |
15499 | rtx stack_top = gen_reg_rtx (Pmode); | |
15500 | rtx opcode_addr = gen_reg_rtx (Pmode); | |
fc4767bb JJ |
15501 | rtx opcode = gen_reg_rtx (SImode); |
15502 | rtx tocompare = gen_reg_rtx (SImode); | |
15503 | rtx no_toc_save_needed = gen_label_rtx (); | |
9ebbca7d | 15504 | |
8308679f | 15505 | mem = gen_frame_mem (Pmode, hard_frame_pointer_rtx); |
9ebbca7d GK |
15506 | emit_move_insn (stack_top, mem); |
15507 | ||
8308679f DE |
15508 | mem = gen_frame_mem (Pmode, |
15509 | gen_rtx_PLUS (Pmode, stack_top, | |
15510 | GEN_INT (2 * GET_MODE_SIZE (Pmode)))); | |
9ebbca7d | 15511 | emit_move_insn (opcode_addr, mem); |
fc4767bb JJ |
15512 | emit_move_insn (opcode, gen_rtx_MEM (SImode, opcode_addr)); |
15513 | emit_move_insn (tocompare, gen_int_mode (TARGET_32BIT ? 0x80410014 | |
2496c7bd | 15514 | : 0xE8410028, SImode)); |
9ebbca7d | 15515 | |
fc4767bb | 15516 | do_compare_rtx_and_jump (opcode, tocompare, EQ, 1, |
06f4e019 | 15517 | SImode, NULL_RTX, NULL_RTX, |
fc4767bb | 15518 | no_toc_save_needed); |
9ebbca7d | 15519 | |
8308679f DE |
15520 | mem = gen_frame_mem (Pmode, |
15521 | gen_rtx_PLUS (Pmode, stack_top, | |
15522 | GEN_INT (5 * GET_MODE_SIZE (Pmode)))); | |
fc4767bb JJ |
15523 | emit_move_insn (mem, gen_rtx_REG (Pmode, 2)); |
15524 | emit_label (no_toc_save_needed); | |
9ebbca7d | 15525 | } |
38c1f2d7 | 15526 | \f |
0be76840 DE |
15527 | /* This ties together stack memory (MEM with an alias set of frame_alias_set) |
15528 | and the change to the stack pointer. */ | |
ba4828e0 | 15529 | |
9ebbca7d | 15530 | static void |
863d938c | 15531 | rs6000_emit_stack_tie (void) |
9ebbca7d | 15532 | { |
0be76840 DE |
15533 | rtx mem = gen_frame_mem (BLKmode, |
15534 | gen_rtx_REG (Pmode, STACK_POINTER_REGNUM)); | |
ba4828e0 | 15535 | |
9ebbca7d GK |
15536 | emit_insn (gen_stack_tie (mem)); |
15537 | } | |
38c1f2d7 | 15538 | |
9ebbca7d GK |
15539 | /* Emit the correct code for allocating stack space, as insns. |
15540 | If COPY_R12, make sure a copy of the old frame is left in r12. | |
f78c3290 NF |
15541 | If COPY_R11, make sure a copy of the old frame is left in r11, |
15542 | in preference to r12 if COPY_R12. | |
9ebbca7d GK |
15543 | The generated code may use hard register 0 as a temporary. */ |
15544 | ||
15545 | static void | |
f78c3290 | 15546 | rs6000_emit_allocate_stack (HOST_WIDE_INT size, int copy_r12, int copy_r11) |
38c1f2d7 | 15547 | { |
9ebbca7d GK |
15548 | rtx insn; |
15549 | rtx stack_reg = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM); | |
15550 | rtx tmp_reg = gen_rtx_REG (Pmode, 0); | |
61168ff1 | 15551 | rtx todec = gen_int_mode (-size, Pmode); |
d4bacef0 | 15552 | rtx par, set, mem; |
61168ff1 RS |
15553 | |
15554 | if (INTVAL (todec) != -size) | |
15555 | { | |
d4ee4d25 | 15556 | warning (0, "stack frame too large"); |
61168ff1 RS |
15557 | emit_insn (gen_trap ()); |
15558 | return; | |
15559 | } | |
a157febd | 15560 | |
e3b5732b | 15561 | if (crtl->limit_stack) |
a157febd GK |
15562 | { |
15563 | if (REG_P (stack_limit_rtx) | |
f676971a | 15564 | && REGNO (stack_limit_rtx) > 1 |
a157febd GK |
15565 | && REGNO (stack_limit_rtx) <= 31) |
15566 | { | |
5b71a4e7 | 15567 | emit_insn (TARGET_32BIT |
9ebbca7d GK |
15568 | ? gen_addsi3 (tmp_reg, |
15569 | stack_limit_rtx, | |
15570 | GEN_INT (size)) | |
15571 | : gen_adddi3 (tmp_reg, | |
15572 | stack_limit_rtx, | |
15573 | GEN_INT (size))); | |
5b71a4e7 | 15574 | |
9ebbca7d GK |
15575 | emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg, |
15576 | const0_rtx)); | |
a157febd GK |
15577 | } |
15578 | else if (GET_CODE (stack_limit_rtx) == SYMBOL_REF | |
9ebbca7d | 15579 | && TARGET_32BIT |
f607bc57 | 15580 | && DEFAULT_ABI == ABI_V4) |
a157febd | 15581 | { |
9ebbca7d | 15582 | rtx toload = gen_rtx_CONST (VOIDmode, |
f676971a EC |
15583 | gen_rtx_PLUS (Pmode, |
15584 | stack_limit_rtx, | |
9ebbca7d | 15585 | GEN_INT (size))); |
5b71a4e7 | 15586 | |
9ebbca7d GK |
15587 | emit_insn (gen_elf_high (tmp_reg, toload)); |
15588 | emit_insn (gen_elf_low (tmp_reg, tmp_reg, toload)); | |
15589 | emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg, | |
15590 | const0_rtx)); | |
a157febd GK |
15591 | } |
15592 | else | |
d4ee4d25 | 15593 | warning (0, "stack limit expression is not supported"); |
a157febd GK |
15594 | } |
15595 | ||
d4bacef0 | 15596 | if (copy_r12 || copy_r11) |
f78c3290 NF |
15597 | emit_move_insn (copy_r11 |
15598 | ? gen_rtx_REG (Pmode, 11) | |
15599 | : gen_rtx_REG (Pmode, 12), | |
15600 | stack_reg); | |
9ebbca7d | 15601 | |
d4bacef0 | 15602 | if (size > 32767) |
38c1f2d7 | 15603 | { |
d4bacef0 BE |
15604 | /* Need a note here so that try_split doesn't get confused. */ |
15605 | if (get_last_insn () == NULL_RTX) | |
15606 | emit_note (NOTE_INSN_DELETED); | |
15607 | insn = emit_move_insn (tmp_reg, todec); | |
15608 | try_split (PATTERN (insn), insn, 0); | |
15609 | todec = tmp_reg; | |
9ebbca7d | 15610 | } |
d4bacef0 BE |
15611 | |
15612 | insn = emit_insn (TARGET_32BIT | |
15613 | ? gen_movsi_update_stack (stack_reg, stack_reg, | |
15614 | todec, stack_reg) | |
15615 | : gen_movdi_di_update_stack (stack_reg, stack_reg, | |
15616 | todec, stack_reg)); | |
15617 | /* Since we didn't use gen_frame_mem to generate the MEM, grab | |
15618 | it now and set the alias set/attributes. The above gen_*_update | |
15619 | calls will generate a PARALLEL with the MEM set being the first | |
15620 | operation. */ | |
15621 | par = PATTERN (insn); | |
15622 | gcc_assert (GET_CODE (par) == PARALLEL); | |
15623 | set = XVECEXP (par, 0, 0); | |
15624 | gcc_assert (GET_CODE (set) == SET); | |
15625 | mem = SET_DEST (set); | |
15626 | gcc_assert (MEM_P (mem)); | |
15627 | MEM_NOTRAP_P (mem) = 1; | |
15628 | set_mem_alias_set (mem, get_frame_alias_set ()); | |
f676971a | 15629 | |
9ebbca7d | 15630 | RTX_FRAME_RELATED_P (insn) = 1; |
bbbbb16a ILT |
15631 | add_reg_note (insn, REG_FRAME_RELATED_EXPR, |
15632 | gen_rtx_SET (VOIDmode, stack_reg, | |
15633 | gen_rtx_PLUS (Pmode, stack_reg, | |
15634 | GEN_INT (-size)))); | |
9ebbca7d GK |
15635 | } |
15636 | ||
a4f6c312 SS |
15637 | /* Add to 'insn' a note which is PATTERN (INSN) but with REG replaced |
15638 | with (plus:P (reg 1) VAL), and with REG2 replaced with RREG if REG2 | |
15639 | is not NULL. It would be nice if dwarf2out_frame_debug_expr could | |
15640 | deduce these equivalences by itself so it wasn't necessary to hold | |
15641 | its hand so much. */ | |
9ebbca7d GK |
15642 | |
15643 | static void | |
f676971a | 15644 | rs6000_frame_related (rtx insn, rtx reg, HOST_WIDE_INT val, |
a2369ed3 | 15645 | rtx reg2, rtx rreg) |
9ebbca7d GK |
15646 | { |
15647 | rtx real, temp; | |
15648 | ||
e56c4463 JL |
15649 | /* copy_rtx will not make unique copies of registers, so we need to |
15650 | ensure we don't have unwanted sharing here. */ | |
15651 | if (reg == reg2) | |
15652 | reg = gen_raw_REG (GET_MODE (reg), REGNO (reg)); | |
15653 | ||
15654 | if (reg == rreg) | |
15655 | reg = gen_raw_REG (GET_MODE (reg), REGNO (reg)); | |
15656 | ||
9ebbca7d GK |
15657 | real = copy_rtx (PATTERN (insn)); |
15658 | ||
89e7058f AH |
15659 | if (reg2 != NULL_RTX) |
15660 | real = replace_rtx (real, reg2, rreg); | |
f676971a EC |
15661 | |
15662 | real = replace_rtx (real, reg, | |
9ebbca7d GK |
15663 | gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode, |
15664 | STACK_POINTER_REGNUM), | |
15665 | GEN_INT (val))); | |
f676971a | 15666 | |
9ebbca7d GK |
15667 | /* We expect that 'real' is either a SET or a PARALLEL containing |
15668 | SETs (and possibly other stuff). In a PARALLEL, all the SETs | |
15669 | are important so they all have to be marked RTX_FRAME_RELATED_P. */ | |
15670 | ||
15671 | if (GET_CODE (real) == SET) | |
15672 | { | |
15673 | rtx set = real; | |
f676971a | 15674 | |
9ebbca7d GK |
15675 | temp = simplify_rtx (SET_SRC (set)); |
15676 | if (temp) | |
15677 | SET_SRC (set) = temp; | |
15678 | temp = simplify_rtx (SET_DEST (set)); | |
15679 | if (temp) | |
15680 | SET_DEST (set) = temp; | |
15681 | if (GET_CODE (SET_DEST (set)) == MEM) | |
38c1f2d7 | 15682 | { |
9ebbca7d GK |
15683 | temp = simplify_rtx (XEXP (SET_DEST (set), 0)); |
15684 | if (temp) | |
15685 | XEXP (SET_DEST (set), 0) = temp; | |
38c1f2d7 | 15686 | } |
38c1f2d7 | 15687 | } |
37409796 | 15688 | else |
9ebbca7d GK |
15689 | { |
15690 | int i; | |
37409796 NS |
15691 | |
15692 | gcc_assert (GET_CODE (real) == PARALLEL); | |
9ebbca7d GK |
15693 | for (i = 0; i < XVECLEN (real, 0); i++) |
15694 | if (GET_CODE (XVECEXP (real, 0, i)) == SET) | |
15695 | { | |
15696 | rtx set = XVECEXP (real, 0, i); | |
f676971a | 15697 | |
9ebbca7d GK |
15698 | temp = simplify_rtx (SET_SRC (set)); |
15699 | if (temp) | |
15700 | SET_SRC (set) = temp; | |
15701 | temp = simplify_rtx (SET_DEST (set)); | |
15702 | if (temp) | |
15703 | SET_DEST (set) = temp; | |
15704 | if (GET_CODE (SET_DEST (set)) == MEM) | |
15705 | { | |
15706 | temp = simplify_rtx (XEXP (SET_DEST (set), 0)); | |
15707 | if (temp) | |
15708 | XEXP (SET_DEST (set), 0) = temp; | |
15709 | } | |
15710 | RTX_FRAME_RELATED_P (set) = 1; | |
15711 | } | |
15712 | } | |
c19de7aa | 15713 | |
9ebbca7d | 15714 | RTX_FRAME_RELATED_P (insn) = 1; |
bbbbb16a | 15715 | add_reg_note (insn, REG_FRAME_RELATED_EXPR, real); |
38c1f2d7 MM |
15716 | } |
15717 | ||
00b960c7 AH |
15718 | /* Returns an insn that has a vrsave set operation with the |
15719 | appropriate CLOBBERs. */ | |
15720 | ||
15721 | static rtx | |
a2369ed3 | 15722 | generate_set_vrsave (rtx reg, rs6000_stack_t *info, int epiloguep) |
00b960c7 AH |
15723 | { |
15724 | int nclobs, i; | |
15725 | rtx insn, clobs[TOTAL_ALTIVEC_REGS + 1]; | |
a004eb82 | 15726 | rtx vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO); |
00b960c7 | 15727 | |
a004eb82 AH |
15728 | clobs[0] |
15729 | = gen_rtx_SET (VOIDmode, | |
15730 | vrsave, | |
15731 | gen_rtx_UNSPEC_VOLATILE (SImode, | |
15732 | gen_rtvec (2, reg, vrsave), | |
3aca4bff | 15733 | UNSPECV_SET_VRSAVE)); |
00b960c7 AH |
15734 | |
15735 | nclobs = 1; | |
15736 | ||
9aa86737 AH |
15737 | /* We need to clobber the registers in the mask so the scheduler |
15738 | does not move sets to VRSAVE before sets of AltiVec registers. | |
15739 | ||
15740 | However, if the function receives nonlocal gotos, reload will set | |
15741 | all call saved registers live. We will end up with: | |
15742 | ||
15743 | (set (reg 999) (mem)) | |
15744 | (parallel [ (set (reg vrsave) (unspec blah)) | |
15745 | (clobber (reg 999))]) | |
15746 | ||
15747 | The clobber will cause the store into reg 999 to be dead, and | |
15748 | flow will attempt to delete an epilogue insn. In this case, we | |
15749 | need an unspec use/set of the register. */ | |
00b960c7 AH |
15750 | |
15751 | for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i) | |
44688022 | 15752 | if (info->vrsave_mask & ALTIVEC_REG_BIT (i)) |
9aa86737 AH |
15753 | { |
15754 | if (!epiloguep || call_used_regs [i]) | |
15755 | clobs[nclobs++] = gen_rtx_CLOBBER (VOIDmode, | |
15756 | gen_rtx_REG (V4SImode, i)); | |
15757 | else | |
15758 | { | |
15759 | rtx reg = gen_rtx_REG (V4SImode, i); | |
9aa86737 AH |
15760 | |
15761 | clobs[nclobs++] | |
a004eb82 AH |
15762 | = gen_rtx_SET (VOIDmode, |
15763 | reg, | |
15764 | gen_rtx_UNSPEC (V4SImode, | |
15765 | gen_rtvec (1, reg), 27)); | |
9aa86737 AH |
15766 | } |
15767 | } | |
00b960c7 AH |
15768 | |
15769 | insn = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (nclobs)); | |
15770 | ||
15771 | for (i = 0; i < nclobs; ++i) | |
15772 | XVECEXP (insn, 0, i) = clobs[i]; | |
15773 | ||
15774 | return insn; | |
15775 | } | |
15776 | ||
89e7058f AH |
15777 | /* Save a register into the frame, and emit RTX_FRAME_RELATED_P notes. |
15778 | Save REGNO into [FRAME_REG + OFFSET] in mode MODE. */ | |
15779 | ||
15780 | static void | |
f676971a | 15781 | emit_frame_save (rtx frame_reg, rtx frame_ptr, enum machine_mode mode, |
d1d0c603 | 15782 | unsigned int regno, int offset, HOST_WIDE_INT total_size) |
89e7058f AH |
15783 | { |
15784 | rtx reg, offset_rtx, insn, mem, addr, int_rtx; | |
15785 | rtx replacea, replaceb; | |
15786 | ||
15787 | int_rtx = GEN_INT (offset); | |
15788 | ||
15789 | /* Some cases that need register indexed addressing. */ | |
15790 | if ((TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode)) | |
4f011e1e | 15791 | || (TARGET_E500_DOUBLE && mode == DFmode) |
a3170dc6 AH |
15792 | || (TARGET_SPE_ABI |
15793 | && SPE_VECTOR_MODE (mode) | |
15794 | && !SPE_CONST_OFFSET_OK (offset))) | |
89e7058f AH |
15795 | { |
15796 | /* Whomever calls us must make sure r11 is available in the | |
c4ad648e | 15797 | flow path of instructions in the prologue. */ |
89e7058f AH |
15798 | offset_rtx = gen_rtx_REG (Pmode, 11); |
15799 | emit_move_insn (offset_rtx, int_rtx); | |
15800 | ||
15801 | replacea = offset_rtx; | |
15802 | replaceb = int_rtx; | |
15803 | } | |
15804 | else | |
15805 | { | |
15806 | offset_rtx = int_rtx; | |
15807 | replacea = NULL_RTX; | |
15808 | replaceb = NULL_RTX; | |
15809 | } | |
15810 | ||
15811 | reg = gen_rtx_REG (mode, regno); | |
15812 | addr = gen_rtx_PLUS (Pmode, frame_reg, offset_rtx); | |
0be76840 | 15813 | mem = gen_frame_mem (mode, addr); |
89e7058f AH |
15814 | |
15815 | insn = emit_move_insn (mem, reg); | |
15816 | ||
15817 | rs6000_frame_related (insn, frame_ptr, total_size, replacea, replaceb); | |
15818 | } | |
15819 | ||
a3170dc6 AH |
15820 | /* Emit an offset memory reference suitable for a frame store, while |
15821 | converting to a valid addressing mode. */ | |
15822 | ||
15823 | static rtx | |
a2369ed3 | 15824 | gen_frame_mem_offset (enum machine_mode mode, rtx reg, int offset) |
a3170dc6 AH |
15825 | { |
15826 | rtx int_rtx, offset_rtx; | |
15827 | ||
15828 | int_rtx = GEN_INT (offset); | |
15829 | ||
4d4cbc0e | 15830 | if ((TARGET_SPE_ABI && SPE_VECTOR_MODE (mode)) |
4f011e1e | 15831 | || (TARGET_E500_DOUBLE && mode == DFmode)) |
a3170dc6 AH |
15832 | { |
15833 | offset_rtx = gen_rtx_REG (Pmode, FIXED_SCRATCH); | |
15834 | emit_move_insn (offset_rtx, int_rtx); | |
15835 | } | |
15836 | else | |
15837 | offset_rtx = int_rtx; | |
15838 | ||
0be76840 | 15839 | return gen_frame_mem (mode, gen_rtx_PLUS (Pmode, reg, offset_rtx)); |
a3170dc6 AH |
15840 | } |
15841 | ||
6d0a8091 DJ |
15842 | /* Look for user-defined global regs. We should not save and restore these, |
15843 | and cannot use stmw/lmw if there are any in its range. */ | |
15844 | ||
15845 | static bool | |
f78c3290 | 15846 | no_global_regs_above (int first, bool gpr) |
6d0a8091 DJ |
15847 | { |
15848 | int i; | |
e1ece9f1 | 15849 | for (i = first; i < gpr ? 32 : 64 ; i++) |
f78c3290 | 15850 | if (global_regs[i]) |
6d0a8091 DJ |
15851 | return false; |
15852 | return true; | |
15853 | } | |
15854 | ||
699c914a MS |
15855 | #ifndef TARGET_FIX_AND_CONTINUE |
15856 | #define TARGET_FIX_AND_CONTINUE 0 | |
15857 | #endif | |
15858 | ||
f78c3290 NF |
15859 | /* It's really GPR 13 and FPR 14, but we need the smaller of the two. */ |
15860 | #define FIRST_SAVRES_REGISTER FIRST_SAVED_GP_REGNO | |
15861 | #define LAST_SAVRES_REGISTER 31 | |
15862 | #define N_SAVRES_REGISTERS (LAST_SAVRES_REGISTER - FIRST_SAVRES_REGISTER + 1) | |
15863 | ||
15864 | static GTY(()) rtx savres_routine_syms[N_SAVRES_REGISTERS][8]; | |
15865 | ||
15866 | /* Return the symbol for an out-of-line register save/restore routine. | |
15867 | We are saving/restoring GPRs if GPR is true. */ | |
15868 | ||
15869 | static rtx | |
15870 | rs6000_savres_routine_sym (rs6000_stack_t *info, bool savep, bool gpr, bool exitp) | |
15871 | { | |
15872 | int regno = gpr ? info->first_gp_reg_save : (info->first_fp_reg_save - 32); | |
15873 | rtx sym; | |
15874 | int select = ((savep ? 1 : 0) << 2 | |
15875 | | (gpr | |
15876 | /* On the SPE, we never have any FPRs, but we do have | |
15877 | 32/64-bit versions of the routines. */ | |
15878 | ? (TARGET_SPE_ABI && info->spe_64bit_regs_used ? 1 : 0) | |
15879 | : 0) << 1 | |
15880 | | (exitp ? 1: 0)); | |
15881 | ||
15882 | /* Don't generate bogus routine names. */ | |
15883 | gcc_assert (FIRST_SAVRES_REGISTER <= regno && regno <= LAST_SAVRES_REGISTER); | |
15884 | ||
15885 | sym = savres_routine_syms[regno-FIRST_SAVRES_REGISTER][select]; | |
15886 | ||
15887 | if (sym == NULL) | |
15888 | { | |
15889 | char name[30]; | |
15890 | const char *action; | |
15891 | const char *regkind; | |
15892 | const char *exit_suffix; | |
15893 | ||
15894 | action = savep ? "save" : "rest"; | |
15895 | ||
15896 | /* SPE has slightly different names for its routines depending on | |
15897 | whether we are saving 32-bit or 64-bit registers. */ | |
15898 | if (TARGET_SPE_ABI) | |
15899 | { | |
15900 | /* No floating point saves on the SPE. */ | |
15901 | gcc_assert (gpr); | |
15902 | ||
15903 | regkind = info->spe_64bit_regs_used ? "64gpr" : "32gpr"; | |
15904 | } | |
15905 | else | |
15906 | regkind = gpr ? "gpr" : "fpr"; | |
15907 | ||
15908 | exit_suffix = exitp ? "_x" : ""; | |
15909 | ||
15910 | sprintf (name, "_%s%s_%d%s", action, regkind, regno, exit_suffix); | |
15911 | ||
15912 | sym = savres_routine_syms[regno-FIRST_SAVRES_REGISTER][select] | |
15913 | = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (name)); | |
15914 | } | |
15915 | ||
15916 | return sym; | |
15917 | } | |
15918 | ||
15919 | /* Emit a sequence of insns, including a stack tie if needed, for | |
15920 | resetting the stack pointer. If SAVRES is true, then don't reset the | |
15921 | stack pointer, but move the base of the frame into r11 for use by | |
15922 | out-of-line register restore routines. */ | |
15923 | ||
15924 | static void | |
15925 | rs6000_emit_stack_reset (rs6000_stack_t *info, | |
15926 | rtx sp_reg_rtx, rtx frame_reg_rtx, | |
15927 | int sp_offset, bool savres) | |
15928 | { | |
15929 | /* This blockage is needed so that sched doesn't decide to move | |
15930 | the sp change before the register restores. */ | |
15931 | if (frame_reg_rtx != sp_reg_rtx | |
15932 | || (TARGET_SPE_ABI | |
15933 | && info->spe_64bit_regs_used != 0 | |
15934 | && info->first_gp_reg_save != 32)) | |
15935 | rs6000_emit_stack_tie (); | |
15936 | ||
15937 | if (frame_reg_rtx != sp_reg_rtx) | |
15938 | { | |
f78c3290 NF |
15939 | if (sp_offset != 0) |
15940 | emit_insn (gen_addsi3 (sp_reg_rtx, frame_reg_rtx, | |
15941 | GEN_INT (sp_offset))); | |
15942 | else if (!savres) | |
15943 | emit_move_insn (sp_reg_rtx, frame_reg_rtx); | |
15944 | } | |
15945 | else if (sp_offset != 0) | |
15946 | { | |
15947 | /* If we are restoring registers out-of-line, we will be using the | |
15948 | "exit" variants of the restore routines, which will reset the | |
15949 | stack for us. But we do need to point r11 into the right place | |
15950 | for those routines. */ | |
15951 | rtx dest_reg = (savres | |
15952 | ? gen_rtx_REG (Pmode, 11) | |
15953 | : sp_reg_rtx); | |
15954 | ||
15955 | emit_insn (TARGET_32BIT | |
15956 | ? gen_addsi3 (dest_reg, sp_reg_rtx, | |
15957 | GEN_INT (sp_offset)) | |
15958 | : gen_adddi3 (dest_reg, sp_reg_rtx, | |
15959 | GEN_INT (sp_offset))); | |
15960 | } | |
15961 | } | |
15962 | ||
15963 | /* Construct a parallel rtx describing the effect of a call to an | |
15964 | out-of-line register save/restore routine. */ | |
15965 | ||
15966 | static rtx | |
15967 | rs6000_make_savres_rtx (rs6000_stack_t *info, | |
15968 | rtx frame_reg_rtx, int save_area_offset, | |
15969 | enum machine_mode reg_mode, | |
15970 | bool savep, bool gpr, bool exitp) | |
15971 | { | |
15972 | int i; | |
15973 | int offset, start_reg, end_reg, n_regs; | |
15974 | int reg_size = GET_MODE_SIZE (reg_mode); | |
15975 | rtx sym; | |
15976 | rtvec p; | |
15977 | ||
15978 | offset = 0; | |
15979 | start_reg = (gpr | |
15980 | ? info->first_gp_reg_save | |
15981 | : info->first_fp_reg_save); | |
15982 | end_reg = gpr ? 32 : 64; | |
15983 | n_regs = end_reg - start_reg; | |
15984 | p = rtvec_alloc ((exitp ? 4 : 3) + n_regs); | |
15985 | ||
15986 | /* If we're saving registers, then we should never say we're exiting. */ | |
15987 | gcc_assert ((savep && !exitp) || !savep); | |
15988 | ||
15989 | if (exitp) | |
15990 | RTVEC_ELT (p, offset++) = gen_rtx_RETURN (VOIDmode); | |
15991 | ||
15992 | RTVEC_ELT (p, offset++) | |
15993 | = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 65)); | |
15994 | ||
15995 | sym = rs6000_savres_routine_sym (info, savep, gpr, exitp); | |
15996 | RTVEC_ELT (p, offset++) = gen_rtx_USE (VOIDmode, sym); | |
15997 | RTVEC_ELT (p, offset++) = gen_rtx_USE (VOIDmode, gen_rtx_REG (Pmode, 11)); | |
15998 | ||
15999 | for (i = 0; i < end_reg - start_reg; i++) | |
16000 | { | |
16001 | rtx addr, reg, mem; | |
16002 | reg = gen_rtx_REG (reg_mode, start_reg + i); | |
16003 | addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
16004 | GEN_INT (save_area_offset + reg_size*i)); | |
16005 | mem = gen_frame_mem (reg_mode, addr); | |
16006 | ||
16007 | RTVEC_ELT (p, i + offset) = gen_rtx_SET (VOIDmode, | |
16008 | savep ? mem : reg, | |
16009 | savep ? reg : mem); | |
16010 | } | |
16011 | ||
16012 | return gen_rtx_PARALLEL (VOIDmode, p); | |
16013 | } | |
16014 | ||
52ff33d0 NF |
16015 | /* Determine whether the gp REG is really used. */ |
16016 | ||
16017 | static bool | |
16018 | rs6000_reg_live_or_pic_offset_p (int reg) | |
16019 | { | |
6fb5fa3c | 16020 | return ((df_regs_ever_live_p (reg) |
52ff33d0 NF |
16021 | && (!call_used_regs[reg] |
16022 | || (reg == RS6000_PIC_OFFSET_TABLE_REGNUM | |
16023 | && TARGET_TOC && TARGET_MINIMAL_TOC))) | |
16024 | || (reg == RS6000_PIC_OFFSET_TABLE_REGNUM | |
16025 | && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0) | |
16026 | || (DEFAULT_ABI == ABI_DARWIN && flag_pic)))); | |
16027 | } | |
16028 | ||
f78c3290 NF |
16029 | enum { |
16030 | SAVRES_MULTIPLE = 0x1, | |
16031 | SAVRES_INLINE_FPRS = 0x2, | |
16032 | SAVRES_INLINE_GPRS = 0x4 | |
16033 | }; | |
16034 | ||
16035 | /* Determine the strategy for savings/restoring registers. */ | |
16036 | ||
16037 | static int | |
16038 | rs6000_savres_strategy (rs6000_stack_t *info, bool savep, | |
16039 | int using_static_chain_p, int sibcall) | |
16040 | { | |
16041 | bool using_multiple_p; | |
16042 | bool common; | |
16043 | bool savres_fprs_inline; | |
16044 | bool savres_gprs_inline; | |
16045 | bool noclobber_global_gprs | |
16046 | = no_global_regs_above (info->first_gp_reg_save, /*gpr=*/true); | |
16047 | ||
16048 | using_multiple_p = (TARGET_MULTIPLE && ! TARGET_POWERPC64 | |
16049 | && (!TARGET_SPE_ABI | |
16050 | || info->spe_64bit_regs_used == 0) | |
16051 | && info->first_gp_reg_save < 31 | |
16052 | && noclobber_global_gprs); | |
16053 | /* Don't bother to try to save things out-of-line if r11 is occupied | |
16054 | by the static chain. It would require too much fiddling and the | |
16055 | static chain is rarely used anyway. */ | |
16056 | common = (using_static_chain_p | |
16057 | || sibcall | |
16058 | || crtl->calls_eh_return | |
16059 | || !info->lr_save_p | |
16060 | || cfun->machine->ra_need_lr | |
16061 | || info->total_size > 32767); | |
16062 | savres_fprs_inline = (common | |
16063 | || info->first_fp_reg_save == 64 | |
16064 | || !no_global_regs_above (info->first_fp_reg_save, | |
16065 | /*gpr=*/false) | |
16066 | || FP_SAVE_INLINE (info->first_fp_reg_save)); | |
16067 | savres_gprs_inline = (common | |
16068 | /* Saving CR interferes with the exit routines | |
16069 | used on the SPE, so just punt here. */ | |
16070 | || (!savep | |
16071 | && TARGET_SPE_ABI | |
16072 | && info->spe_64bit_regs_used != 0 | |
16073 | && info->cr_save_p != 0) | |
16074 | || info->first_gp_reg_save == 32 | |
16075 | || !noclobber_global_gprs | |
16076 | || GP_SAVE_INLINE (info->first_gp_reg_save)); | |
16077 | ||
16078 | if (savep) | |
16079 | /* If we are going to use store multiple, then don't even bother | |
16080 | with the out-of-line routines, since the store-multiple instruction | |
16081 | will always be smaller. */ | |
16082 | savres_gprs_inline = savres_gprs_inline || using_multiple_p; | |
16083 | else | |
16084 | { | |
16085 | /* The situation is more complicated with load multiple. We'd | |
16086 | prefer to use the out-of-line routines for restores, since the | |
16087 | "exit" out-of-line routines can handle the restore of LR and | |
16088 | the frame teardown. But we can only use the out-of-line | |
16089 | routines if we know that we've used store multiple or | |
16090 | out-of-line routines in the prologue, i.e. if we've saved all | |
16091 | the registers from first_gp_reg_save. Otherwise, we risk | |
16092 | loading garbage from the stack. Furthermore, we can only use | |
16093 | the "exit" out-of-line gpr restore if we haven't saved any | |
16094 | fprs. */ | |
16095 | bool saved_all = !savres_gprs_inline || using_multiple_p; | |
16096 | ||
16097 | if (saved_all && info->first_fp_reg_save != 64) | |
16098 | /* We can't use the exit routine; use load multiple if it's | |
16099 | available. */ | |
16100 | savres_gprs_inline = savres_gprs_inline || using_multiple_p; | |
16101 | } | |
16102 | ||
16103 | return (using_multiple_p | |
16104 | | (savres_fprs_inline << 1) | |
16105 | | (savres_gprs_inline << 2)); | |
16106 | } | |
16107 | ||
9ebbca7d GK |
16108 | /* Emit function prologue as insns. */ |
16109 | ||
9878760c | 16110 | void |
863d938c | 16111 | rs6000_emit_prologue (void) |
9878760c | 16112 | { |
4697a36c | 16113 | rs6000_stack_t *info = rs6000_stack_info (); |
0e67400a | 16114 | enum machine_mode reg_mode = Pmode; |
327e5343 | 16115 | int reg_size = TARGET_32BIT ? 4 : 8; |
9ebbca7d GK |
16116 | rtx sp_reg_rtx = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM); |
16117 | rtx frame_ptr_rtx = gen_rtx_REG (Pmode, 12); | |
16118 | rtx frame_reg_rtx = sp_reg_rtx; | |
b78d48dd | 16119 | rtx cr_save_rtx = NULL_RTX; |
9ebbca7d | 16120 | rtx insn; |
f78c3290 | 16121 | int strategy; |
9ebbca7d | 16122 | int saving_FPRs_inline; |
f78c3290 | 16123 | int saving_GPRs_inline; |
9ebbca7d | 16124 | int using_store_multiple; |
f78c3290 NF |
16125 | int using_static_chain_p = (cfun->static_chain_decl != NULL_TREE |
16126 | && df_regs_ever_live_p (STATIC_CHAIN_REGNUM) | |
e1ece9f1 | 16127 | && !call_used_regs[STATIC_CHAIN_REGNUM]); |
9ebbca7d | 16128 | HOST_WIDE_INT sp_offset = 0; |
f676971a | 16129 | |
699c914a MS |
16130 | if (TARGET_FIX_AND_CONTINUE) |
16131 | { | |
16132 | /* gdb on darwin arranges to forward a function from the old | |
de2ab0ca | 16133 | address by modifying the first 5 instructions of the function |
699c914a MS |
16134 | to branch to the overriding function. This is necessary to |
16135 | permit function pointers that point to the old function to | |
16136 | actually forward to the new function. */ | |
16137 | emit_insn (gen_nop ()); | |
16138 | emit_insn (gen_nop ()); | |
de2ab0ca | 16139 | emit_insn (gen_nop ()); |
699c914a MS |
16140 | emit_insn (gen_nop ()); |
16141 | emit_insn (gen_nop ()); | |
16142 | } | |
16143 | ||
16144 | if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0) | |
16145 | { | |
16146 | reg_mode = V2SImode; | |
16147 | reg_size = 8; | |
16148 | } | |
a3170dc6 | 16149 | |
f78c3290 NF |
16150 | strategy = rs6000_savres_strategy (info, /*savep=*/true, |
16151 | /*static_chain_p=*/using_static_chain_p, | |
16152 | /*sibcall=*/0); | |
16153 | using_store_multiple = strategy & SAVRES_MULTIPLE; | |
16154 | saving_FPRs_inline = strategy & SAVRES_INLINE_FPRS; | |
16155 | saving_GPRs_inline = strategy & SAVRES_INLINE_GPRS; | |
9ebbca7d GK |
16156 | |
16157 | /* For V.4, update stack before we do any saving and set back pointer. */ | |
22fa69da GK |
16158 | if (! WORLD_SAVE_P (info) |
16159 | && info->push_p | |
acd0b319 | 16160 | && (DEFAULT_ABI == ABI_V4 |
e3b5732b | 16161 | || crtl->calls_eh_return)) |
9ebbca7d | 16162 | { |
f78c3290 NF |
16163 | bool need_r11 = (TARGET_SPE |
16164 | ? (!saving_GPRs_inline | |
16165 | && info->spe_64bit_regs_used == 0) | |
16166 | : (!saving_FPRs_inline || !saving_GPRs_inline)); | |
9ebbca7d GK |
16167 | if (info->total_size < 32767) |
16168 | sp_offset = info->total_size; | |
16169 | else | |
f78c3290 NF |
16170 | frame_reg_rtx = (need_r11 |
16171 | ? gen_rtx_REG (Pmode, 11) | |
16172 | : frame_ptr_rtx); | |
f676971a | 16173 | rs6000_emit_allocate_stack (info->total_size, |
9ebbca7d GK |
16174 | (frame_reg_rtx != sp_reg_rtx |
16175 | && (info->cr_save_p | |
16176 | || info->lr_save_p | |
16177 | || info->first_fp_reg_save < 64 | |
16178 | || info->first_gp_reg_save < 32 | |
f78c3290 NF |
16179 | )), |
16180 | need_r11); | |
9ebbca7d GK |
16181 | if (frame_reg_rtx != sp_reg_rtx) |
16182 | rs6000_emit_stack_tie (); | |
16183 | } | |
16184 | ||
d62294f5 | 16185 | /* Handle world saves specially here. */ |
f57fe068 | 16186 | if (WORLD_SAVE_P (info)) |
d62294f5 FJ |
16187 | { |
16188 | int i, j, sz; | |
16189 | rtx treg; | |
16190 | rtvec p; | |
22fa69da | 16191 | rtx reg0; |
d62294f5 FJ |
16192 | |
16193 | /* save_world expects lr in r0. */ | |
22fa69da | 16194 | reg0 = gen_rtx_REG (Pmode, 0); |
d62294f5 | 16195 | if (info->lr_save_p) |
c4ad648e | 16196 | { |
22fa69da | 16197 | insn = emit_move_insn (reg0, |
1de43f85 | 16198 | gen_rtx_REG (Pmode, LR_REGNO)); |
c4ad648e AM |
16199 | RTX_FRAME_RELATED_P (insn) = 1; |
16200 | } | |
d62294f5 FJ |
16201 | |
16202 | /* The SAVE_WORLD and RESTORE_WORLD routines make a number of | |
c4ad648e | 16203 | assumptions about the offsets of various bits of the stack |
992d08b1 | 16204 | frame. */ |
37409796 NS |
16205 | gcc_assert (info->gp_save_offset == -220 |
16206 | && info->fp_save_offset == -144 | |
16207 | && info->lr_save_offset == 8 | |
16208 | && info->cr_save_offset == 4 | |
16209 | && info->push_p | |
16210 | && info->lr_save_p | |
e3b5732b | 16211 | && (!crtl->calls_eh_return |
37409796 NS |
16212 | || info->ehrd_offset == -432) |
16213 | && info->vrsave_save_offset == -224 | |
22fa69da | 16214 | && info->altivec_save_offset == -416); |
d62294f5 FJ |
16215 | |
16216 | treg = gen_rtx_REG (SImode, 11); | |
16217 | emit_move_insn (treg, GEN_INT (-info->total_size)); | |
16218 | ||
16219 | /* SAVE_WORLD takes the caller's LR in R0 and the frame size | |
c4ad648e | 16220 | in R11. It also clobbers R12, so beware! */ |
d62294f5 FJ |
16221 | |
16222 | /* Preserve CR2 for save_world prologues */ | |
22fa69da | 16223 | sz = 5; |
d62294f5 FJ |
16224 | sz += 32 - info->first_gp_reg_save; |
16225 | sz += 64 - info->first_fp_reg_save; | |
16226 | sz += LAST_ALTIVEC_REGNO - info->first_altivec_reg_save + 1; | |
16227 | p = rtvec_alloc (sz); | |
16228 | j = 0; | |
16229 | RTVEC_ELT (p, j++) = gen_rtx_CLOBBER (VOIDmode, | |
a5ad2017 | 16230 | gen_rtx_REG (SImode, |
1de43f85 | 16231 | LR_REGNO)); |
d62294f5 | 16232 | RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode, |
c4ad648e AM |
16233 | gen_rtx_SYMBOL_REF (Pmode, |
16234 | "*save_world")); | |
d62294f5 | 16235 | /* We do floats first so that the instruction pattern matches |
c4ad648e AM |
16236 | properly. */ |
16237 | for (i = 0; i < 64 - info->first_fp_reg_save; i++) | |
16238 | { | |
696e45ba ME |
16239 | rtx reg = gen_rtx_REG (((TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT) |
16240 | ? DFmode : SFmode), | |
16241 | info->first_fp_reg_save + i); | |
c4ad648e AM |
16242 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, |
16243 | GEN_INT (info->fp_save_offset | |
16244 | + sp_offset + 8 * i)); | |
696e45ba ME |
16245 | rtx mem = gen_frame_mem (((TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT) |
16246 | ? DFmode : SFmode), addr); | |
c4ad648e AM |
16247 | |
16248 | RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg); | |
16249 | } | |
d62294f5 | 16250 | for (i = 0; info->first_altivec_reg_save + i <= LAST_ALTIVEC_REGNO; i++) |
c4ad648e AM |
16251 | { |
16252 | rtx reg = gen_rtx_REG (V4SImode, info->first_altivec_reg_save + i); | |
16253 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
16254 | GEN_INT (info->altivec_save_offset | |
16255 | + sp_offset + 16 * i)); | |
0be76840 | 16256 | rtx mem = gen_frame_mem (V4SImode, addr); |
c4ad648e AM |
16257 | |
16258 | RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg); | |
16259 | } | |
d62294f5 | 16260 | for (i = 0; i < 32 - info->first_gp_reg_save; i++) |
c4ad648e AM |
16261 | { |
16262 | rtx reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i); | |
16263 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
16264 | GEN_INT (info->gp_save_offset | |
16265 | + sp_offset + reg_size * i)); | |
0be76840 | 16266 | rtx mem = gen_frame_mem (reg_mode, addr); |
c4ad648e AM |
16267 | |
16268 | RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg); | |
16269 | } | |
16270 | ||
16271 | { | |
16272 | /* CR register traditionally saved as CR2. */ | |
16273 | rtx reg = gen_rtx_REG (reg_mode, CR2_REGNO); | |
16274 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
16275 | GEN_INT (info->cr_save_offset | |
16276 | + sp_offset)); | |
0be76840 | 16277 | rtx mem = gen_frame_mem (reg_mode, addr); |
c4ad648e AM |
16278 | |
16279 | RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg); | |
16280 | } | |
22fa69da GK |
16281 | /* Explain about use of R0. */ |
16282 | if (info->lr_save_p) | |
16283 | { | |
16284 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
16285 | GEN_INT (info->lr_save_offset | |
16286 | + sp_offset)); | |
16287 | rtx mem = gen_frame_mem (reg_mode, addr); | |
982afe02 | 16288 | |
22fa69da GK |
16289 | RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg0); |
16290 | } | |
16291 | /* Explain what happens to the stack pointer. */ | |
16292 | { | |
16293 | rtx newval = gen_rtx_PLUS (Pmode, sp_reg_rtx, treg); | |
16294 | RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, sp_reg_rtx, newval); | |
16295 | } | |
d62294f5 FJ |
16296 | |
16297 | insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p)); | |
16298 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, | |
22fa69da GK |
16299 | treg, GEN_INT (-info->total_size)); |
16300 | sp_offset = info->total_size; | |
d62294f5 FJ |
16301 | } |
16302 | ||
9ebbca7d | 16303 | /* If we use the link register, get it into r0. */ |
f57fe068 | 16304 | if (!WORLD_SAVE_P (info) && info->lr_save_p) |
f8a57be8 | 16305 | { |
52ff33d0 NF |
16306 | rtx addr, reg, mem; |
16307 | ||
f8a57be8 | 16308 | insn = emit_move_insn (gen_rtx_REG (Pmode, 0), |
1de43f85 | 16309 | gen_rtx_REG (Pmode, LR_REGNO)); |
f8a57be8 | 16310 | RTX_FRAME_RELATED_P (insn) = 1; |
52ff33d0 NF |
16311 | |
16312 | addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
16313 | GEN_INT (info->lr_save_offset + sp_offset)); | |
16314 | reg = gen_rtx_REG (Pmode, 0); | |
16315 | mem = gen_rtx_MEM (Pmode, addr); | |
16316 | /* This should not be of rs6000_sr_alias_set, because of | |
16317 | __builtin_return_address. */ | |
16318 | ||
16319 | insn = emit_move_insn (mem, reg); | |
16320 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, | |
16321 | NULL_RTX, NULL_RTX); | |
f8a57be8 | 16322 | } |
9ebbca7d GK |
16323 | |
16324 | /* If we need to save CR, put it into r12. */ | |
f57fe068 | 16325 | if (!WORLD_SAVE_P (info) && info->cr_save_p && frame_reg_rtx != frame_ptr_rtx) |
9ebbca7d | 16326 | { |
f8a57be8 | 16327 | rtx set; |
f676971a | 16328 | |
9ebbca7d | 16329 | cr_save_rtx = gen_rtx_REG (SImode, 12); |
f8a57be8 GK |
16330 | insn = emit_insn (gen_movesi_from_cr (cr_save_rtx)); |
16331 | RTX_FRAME_RELATED_P (insn) = 1; | |
16332 | /* Now, there's no way that dwarf2out_frame_debug_expr is going | |
16333 | to understand '(unspec:SI [(reg:CC 68) ...] UNSPEC_MOVESI_FROM_CR)'. | |
16334 | But that's OK. All we have to do is specify that _one_ condition | |
16335 | code register is saved in this stack slot. The thrower's epilogue | |
16336 | will then restore all the call-saved registers. | |
16337 | We use CR2_REGNO (70) to be compatible with gcc-2.95 on Linux. */ | |
16338 | set = gen_rtx_SET (VOIDmode, cr_save_rtx, | |
16339 | gen_rtx_REG (SImode, CR2_REGNO)); | |
bbbbb16a | 16340 | add_reg_note (insn, REG_FRAME_RELATED_EXPR, set); |
9ebbca7d GK |
16341 | } |
16342 | ||
a4f6c312 SS |
16343 | /* Do any required saving of fpr's. If only one or two to save, do |
16344 | it ourselves. Otherwise, call function. */ | |
f57fe068 | 16345 | if (!WORLD_SAVE_P (info) && saving_FPRs_inline) |
9ebbca7d GK |
16346 | { |
16347 | int i; | |
16348 | for (i = 0; i < 64 - info->first_fp_reg_save; i++) | |
6fb5fa3c | 16349 | if ((df_regs_ever_live_p (info->first_fp_reg_save+i) |
9ebbca7d | 16350 | && ! call_used_regs[info->first_fp_reg_save+i])) |
696e45ba ME |
16351 | emit_frame_save (frame_reg_rtx, frame_ptr_rtx, |
16352 | (TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT) | |
16353 | ? DFmode : SFmode, | |
89e7058f AH |
16354 | info->first_fp_reg_save + i, |
16355 | info->fp_save_offset + sp_offset + 8 * i, | |
16356 | info->total_size); | |
9ebbca7d | 16357 | } |
f57fe068 | 16358 | else if (!WORLD_SAVE_P (info) && info->first_fp_reg_save != 64) |
f78c3290 NF |
16359 | { |
16360 | rtx par; | |
16361 | ||
16362 | par = rs6000_make_savres_rtx (info, frame_reg_rtx, | |
16363 | info->fp_save_offset + sp_offset, | |
16364 | DFmode, | |
16365 | /*savep=*/true, /*gpr=*/false, | |
16366 | /*exitp=*/false); | |
16367 | insn = emit_insn (par); | |
16368 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, | |
16369 | NULL_RTX, NULL_RTX); | |
16370 | } | |
16371 | ||
16372 | /* Save GPRs. This is done as a PARALLEL if we are using | |
16373 | the store-multiple instructions. */ | |
16374 | if (!WORLD_SAVE_P (info) | |
16375 | && TARGET_SPE_ABI | |
16376 | && info->spe_64bit_regs_used != 0 | |
16377 | && info->first_gp_reg_save != 32) | |
9ebbca7d GK |
16378 | { |
16379 | int i; | |
f78c3290 NF |
16380 | rtx spe_save_area_ptr; |
16381 | ||
16382 | /* Determine whether we can address all of the registers that need | |
16383 | to be saved with an offset from the stack pointer that fits in | |
16384 | the small const field for SPE memory instructions. */ | |
16385 | int spe_regs_addressable_via_sp | |
16386 | = (SPE_CONST_OFFSET_OK(info->spe_gp_save_offset + sp_offset | |
16387 | + (32 - info->first_gp_reg_save - 1) * reg_size) | |
16388 | && saving_GPRs_inline); | |
16389 | int spe_offset; | |
16390 | ||
16391 | if (spe_regs_addressable_via_sp) | |
16392 | { | |
16393 | spe_save_area_ptr = frame_reg_rtx; | |
16394 | spe_offset = info->spe_gp_save_offset + sp_offset; | |
16395 | } | |
16396 | else | |
16397 | { | |
16398 | /* Make r11 point to the start of the SPE save area. We need | |
16399 | to be careful here if r11 is holding the static chain. If | |
16400 | it is, then temporarily save it in r0. We would use r0 as | |
16401 | our base register here, but using r0 as a base register in | |
16402 | loads and stores means something different from what we | |
16403 | would like. */ | |
16404 | int ool_adjust = (saving_GPRs_inline | |
16405 | ? 0 | |
16406 | : (info->first_gp_reg_save | |
16407 | - (FIRST_SAVRES_REGISTER+1))*8); | |
16408 | HOST_WIDE_INT offset = (info->spe_gp_save_offset | |
16409 | + sp_offset - ool_adjust); | |
16410 | ||
16411 | if (using_static_chain_p) | |
16412 | { | |
16413 | rtx r0 = gen_rtx_REG (Pmode, 0); | |
16414 | gcc_assert (info->first_gp_reg_save > 11); | |
16415 | ||
16416 | emit_move_insn (r0, gen_rtx_REG (Pmode, 11)); | |
16417 | } | |
16418 | ||
16419 | spe_save_area_ptr = gen_rtx_REG (Pmode, 11); | |
16420 | insn = emit_insn (gen_addsi3 (spe_save_area_ptr, | |
16421 | frame_reg_rtx, | |
16422 | GEN_INT (offset))); | |
16423 | /* We need to make sure the move to r11 gets noted for | |
16424 | properly outputting unwind information. */ | |
16425 | if (!saving_GPRs_inline) | |
16426 | rs6000_frame_related (insn, frame_reg_rtx, offset, | |
16427 | NULL_RTX, NULL_RTX); | |
16428 | spe_offset = 0; | |
16429 | } | |
16430 | ||
16431 | if (saving_GPRs_inline) | |
16432 | { | |
16433 | for (i = 0; i < 32 - info->first_gp_reg_save; i++) | |
16434 | if (rs6000_reg_live_or_pic_offset_p (info->first_gp_reg_save + i)) | |
16435 | { | |
16436 | rtx reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i); | |
16437 | rtx offset, addr, mem; | |
f676971a | 16438 | |
f78c3290 NF |
16439 | /* We're doing all this to ensure that the offset fits into |
16440 | the immediate offset of 'evstdd'. */ | |
16441 | gcc_assert (SPE_CONST_OFFSET_OK (reg_size * i + spe_offset)); | |
16442 | ||
16443 | offset = GEN_INT (reg_size * i + spe_offset); | |
16444 | addr = gen_rtx_PLUS (Pmode, spe_save_area_ptr, offset); | |
16445 | mem = gen_rtx_MEM (V2SImode, addr); | |
16446 | ||
16447 | insn = emit_move_insn (mem, reg); | |
16448 | ||
16449 | rs6000_frame_related (insn, spe_save_area_ptr, | |
16450 | info->spe_gp_save_offset | |
16451 | + sp_offset + reg_size * i, | |
16452 | offset, const0_rtx); | |
16453 | } | |
16454 | } | |
16455 | else | |
9ebbca7d | 16456 | { |
f78c3290 | 16457 | rtx par; |
9ebbca7d | 16458 | |
f78c3290 NF |
16459 | par = rs6000_make_savres_rtx (info, gen_rtx_REG (Pmode, 11), |
16460 | 0, reg_mode, | |
16461 | /*savep=*/true, /*gpr=*/true, | |
16462 | /*exitp=*/false); | |
16463 | insn = emit_insn (par); | |
16464 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, | |
16465 | NULL_RTX, NULL_RTX); | |
9ebbca7d | 16466 | } |
f78c3290 NF |
16467 | |
16468 | ||
16469 | /* Move the static chain pointer back. */ | |
16470 | if (using_static_chain_p && !spe_regs_addressable_via_sp) | |
16471 | emit_move_insn (gen_rtx_REG (Pmode, 11), gen_rtx_REG (Pmode, 0)); | |
16472 | } | |
16473 | else if (!WORLD_SAVE_P (info) && !saving_GPRs_inline) | |
16474 | { | |
16475 | rtx par; | |
16476 | ||
16477 | /* Need to adjust r11 if we saved any FPRs. */ | |
16478 | if (info->first_fp_reg_save != 64) | |
16479 | { | |
16480 | rtx r11 = gen_rtx_REG (reg_mode, 11); | |
16481 | rtx offset = GEN_INT (info->total_size | |
16482 | + (-8 * (64-info->first_fp_reg_save))); | |
16483 | rtx ptr_reg = (sp_reg_rtx == frame_reg_rtx | |
16484 | ? sp_reg_rtx : r11); | |
16485 | ||
16486 | emit_insn (TARGET_32BIT | |
16487 | ? gen_addsi3 (r11, ptr_reg, offset) | |
16488 | : gen_adddi3 (r11, ptr_reg, offset)); | |
16489 | } | |
16490 | ||
16491 | par = rs6000_make_savres_rtx (info, frame_reg_rtx, | |
16492 | info->gp_save_offset + sp_offset, | |
16493 | reg_mode, | |
16494 | /*savep=*/true, /*gpr=*/true, | |
16495 | /*exitp=*/false); | |
16496 | insn = emit_insn (par); | |
f676971a | 16497 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, |
9ebbca7d GK |
16498 | NULL_RTX, NULL_RTX); |
16499 | } | |
f78c3290 | 16500 | else if (!WORLD_SAVE_P (info) && using_store_multiple) |
b6c9286a | 16501 | { |
308c142a | 16502 | rtvec p; |
9ebbca7d GK |
16503 | int i; |
16504 | p = rtvec_alloc (32 - info->first_gp_reg_save); | |
9ebbca7d GK |
16505 | for (i = 0; i < 32 - info->first_gp_reg_save; i++) |
16506 | { | |
16507 | rtx addr, reg, mem; | |
16508 | reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i); | |
f676971a EC |
16509 | addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, |
16510 | GEN_INT (info->gp_save_offset | |
16511 | + sp_offset | |
9ebbca7d | 16512 | + reg_size * i)); |
0be76840 | 16513 | mem = gen_frame_mem (reg_mode, addr); |
9ebbca7d GK |
16514 | |
16515 | RTVEC_ELT (p, i) = gen_rtx_SET (VOIDmode, mem, reg); | |
16516 | } | |
16517 | insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p)); | |
f676971a | 16518 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, |
9ebbca7d | 16519 | NULL_RTX, NULL_RTX); |
b6c9286a | 16520 | } |
f57fe068 | 16521 | else if (!WORLD_SAVE_P (info)) |
b6c9286a | 16522 | { |
9ebbca7d GK |
16523 | int i; |
16524 | for (i = 0; i < 32 - info->first_gp_reg_save; i++) | |
52ff33d0 NF |
16525 | if (rs6000_reg_live_or_pic_offset_p (info->first_gp_reg_save + i)) |
16526 | { | |
16527 | rtx addr, reg, mem; | |
16528 | reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i); | |
a3170dc6 | 16529 | |
52ff33d0 NF |
16530 | addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, |
16531 | GEN_INT (info->gp_save_offset | |
16532 | + sp_offset | |
16533 | + reg_size * i)); | |
16534 | mem = gen_frame_mem (reg_mode, addr); | |
a3170dc6 | 16535 | |
52ff33d0 NF |
16536 | insn = emit_move_insn (mem, reg); |
16537 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, | |
16538 | NULL_RTX, NULL_RTX); | |
16539 | } | |
9ebbca7d GK |
16540 | } |
16541 | ||
83720594 RH |
16542 | /* ??? There's no need to emit actual instructions here, but it's the |
16543 | easiest way to get the frame unwind information emitted. */ | |
e3b5732b | 16544 | if (crtl->calls_eh_return) |
83720594 | 16545 | { |
78e1b90d DE |
16546 | unsigned int i, regno; |
16547 | ||
fc4767bb JJ |
16548 | /* In AIX ABI we need to pretend we save r2 here. */ |
16549 | if (TARGET_AIX) | |
16550 | { | |
16551 | rtx addr, reg, mem; | |
16552 | ||
16553 | reg = gen_rtx_REG (reg_mode, 2); | |
16554 | addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
16555 | GEN_INT (sp_offset + 5 * reg_size)); | |
0be76840 | 16556 | mem = gen_frame_mem (reg_mode, addr); |
fc4767bb JJ |
16557 | |
16558 | insn = emit_move_insn (mem, reg); | |
f676971a | 16559 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, |
fc4767bb JJ |
16560 | NULL_RTX, NULL_RTX); |
16561 | PATTERN (insn) = gen_blockage (); | |
16562 | } | |
16563 | ||
83720594 RH |
16564 | for (i = 0; ; ++i) |
16565 | { | |
83720594 RH |
16566 | regno = EH_RETURN_DATA_REGNO (i); |
16567 | if (regno == INVALID_REGNUM) | |
16568 | break; | |
16569 | ||
89e7058f AH |
16570 | emit_frame_save (frame_reg_rtx, frame_ptr_rtx, reg_mode, regno, |
16571 | info->ehrd_offset + sp_offset | |
16572 | + reg_size * (int) i, | |
16573 | info->total_size); | |
83720594 RH |
16574 | } |
16575 | } | |
16576 | ||
9ebbca7d | 16577 | /* Save CR if we use any that must be preserved. */ |
f57fe068 | 16578 | if (!WORLD_SAVE_P (info) && info->cr_save_p) |
9ebbca7d GK |
16579 | { |
16580 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
16581 | GEN_INT (info->cr_save_offset + sp_offset)); | |
0be76840 | 16582 | rtx mem = gen_frame_mem (SImode, addr); |
f8a57be8 GK |
16583 | /* See the large comment above about why CR2_REGNO is used. */ |
16584 | rtx magic_eh_cr_reg = gen_rtx_REG (SImode, CR2_REGNO); | |
ba4828e0 | 16585 | |
9ebbca7d GK |
16586 | /* If r12 was used to hold the original sp, copy cr into r0 now |
16587 | that it's free. */ | |
16588 | if (REGNO (frame_reg_rtx) == 12) | |
16589 | { | |
f8a57be8 GK |
16590 | rtx set; |
16591 | ||
9ebbca7d | 16592 | cr_save_rtx = gen_rtx_REG (SImode, 0); |
f8a57be8 GK |
16593 | insn = emit_insn (gen_movesi_from_cr (cr_save_rtx)); |
16594 | RTX_FRAME_RELATED_P (insn) = 1; | |
16595 | set = gen_rtx_SET (VOIDmode, cr_save_rtx, magic_eh_cr_reg); | |
bbbbb16a | 16596 | add_reg_note (insn, REG_FRAME_RELATED_EXPR, set); |
9ebbca7d GK |
16597 | } |
16598 | insn = emit_move_insn (mem, cr_save_rtx); | |
16599 | ||
f676971a | 16600 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, |
f8a57be8 | 16601 | NULL_RTX, NULL_RTX); |
9ebbca7d GK |
16602 | } |
16603 | ||
f676971a | 16604 | /* Update stack and set back pointer unless this is V.4, |
9ebbca7d | 16605 | for which it was done previously. */ |
f57fe068 | 16606 | if (!WORLD_SAVE_P (info) && info->push_p |
e3b5732b | 16607 | && !(DEFAULT_ABI == ABI_V4 || crtl->calls_eh_return)) |
2b2c2fe5 | 16608 | { |
bcb2d701 | 16609 | if (info->total_size < 32767) |
2b2c2fe5 | 16610 | sp_offset = info->total_size; |
bcb2d701 EC |
16611 | else |
16612 | frame_reg_rtx = frame_ptr_rtx; | |
16613 | rs6000_emit_allocate_stack (info->total_size, | |
16614 | (frame_reg_rtx != sp_reg_rtx | |
16615 | && ((info->altivec_size != 0) | |
16616 | || (info->vrsave_mask != 0) | |
f78c3290 NF |
16617 | )), |
16618 | FALSE); | |
bcb2d701 EC |
16619 | if (frame_reg_rtx != sp_reg_rtx) |
16620 | rs6000_emit_stack_tie (); | |
2b2c2fe5 | 16621 | } |
9ebbca7d GK |
16622 | |
16623 | /* Set frame pointer, if needed. */ | |
16624 | if (frame_pointer_needed) | |
16625 | { | |
7d5175e1 | 16626 | insn = emit_move_insn (gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM), |
9ebbca7d GK |
16627 | sp_reg_rtx); |
16628 | RTX_FRAME_RELATED_P (insn) = 1; | |
b6c9286a | 16629 | } |
9878760c | 16630 | |
2b2c2fe5 EC |
16631 | /* Save AltiVec registers if needed. Save here because the red zone does |
16632 | not include AltiVec registers. */ | |
16633 | if (!WORLD_SAVE_P (info) && TARGET_ALTIVEC_ABI && info->altivec_size != 0) | |
16634 | { | |
16635 | int i; | |
16636 | ||
16637 | /* There should be a non inline version of this, for when we | |
16638 | are saving lots of vector registers. */ | |
16639 | for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i) | |
16640 | if (info->vrsave_mask & ALTIVEC_REG_BIT (i)) | |
16641 | { | |
16642 | rtx areg, savereg, mem; | |
16643 | int offset; | |
16644 | ||
16645 | offset = info->altivec_save_offset + sp_offset | |
16646 | + 16 * (i - info->first_altivec_reg_save); | |
16647 | ||
16648 | savereg = gen_rtx_REG (V4SImode, i); | |
16649 | ||
16650 | areg = gen_rtx_REG (Pmode, 0); | |
16651 | emit_move_insn (areg, GEN_INT (offset)); | |
16652 | ||
16653 | /* AltiVec addressing mode is [reg+reg]. */ | |
16654 | mem = gen_frame_mem (V4SImode, | |
16655 | gen_rtx_PLUS (Pmode, frame_reg_rtx, areg)); | |
16656 | ||
16657 | insn = emit_move_insn (mem, savereg); | |
16658 | ||
16659 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, | |
16660 | areg, GEN_INT (offset)); | |
16661 | } | |
16662 | } | |
16663 | ||
16664 | /* VRSAVE is a bit vector representing which AltiVec registers | |
16665 | are used. The OS uses this to determine which vector | |
16666 | registers to save on a context switch. We need to save | |
16667 | VRSAVE on the stack frame, add whatever AltiVec registers we | |
16668 | used in this function, and do the corresponding magic in the | |
16669 | epilogue. */ | |
16670 | ||
16671 | if (TARGET_ALTIVEC && TARGET_ALTIVEC_VRSAVE | |
16672 | && info->vrsave_mask != 0) | |
16673 | { | |
16674 | rtx reg, mem, vrsave; | |
16675 | int offset; | |
16676 | ||
16677 | /* Get VRSAVE onto a GPR. Note that ABI_V4 might be using r12 | |
16678 | as frame_reg_rtx and r11 as the static chain pointer for | |
16679 | nested functions. */ | |
16680 | reg = gen_rtx_REG (SImode, 0); | |
16681 | vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO); | |
16682 | if (TARGET_MACHO) | |
16683 | emit_insn (gen_get_vrsave_internal (reg)); | |
16684 | else | |
16685 | emit_insn (gen_rtx_SET (VOIDmode, reg, vrsave)); | |
16686 | ||
16687 | if (!WORLD_SAVE_P (info)) | |
16688 | { | |
16689 | /* Save VRSAVE. */ | |
16690 | offset = info->vrsave_save_offset + sp_offset; | |
16691 | mem = gen_frame_mem (SImode, | |
16692 | gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
16693 | GEN_INT (offset))); | |
16694 | insn = emit_move_insn (mem, reg); | |
16695 | } | |
16696 | ||
16697 | /* Include the registers in the mask. */ | |
16698 | emit_insn (gen_iorsi3 (reg, reg, GEN_INT ((int) info->vrsave_mask))); | |
16699 | ||
16700 | insn = emit_insn (generate_set_vrsave (reg, info, 0)); | |
16701 | } | |
16702 | ||
1db02437 | 16703 | /* If we are using RS6000_PIC_OFFSET_TABLE_REGNUM, we need to set it up. */ |
9ebbca7d | 16704 | if ((TARGET_TOC && TARGET_MINIMAL_TOC && get_pool_size () != 0) |
7f970b70 AM |
16705 | || (DEFAULT_ABI == ABI_V4 |
16706 | && (flag_pic == 1 || (flag_pic && TARGET_SECURE_PLT)) | |
6fb5fa3c | 16707 | && df_regs_ever_live_p (RS6000_PIC_OFFSET_TABLE_REGNUM))) |
c4ad648e AM |
16708 | { |
16709 | /* If emit_load_toc_table will use the link register, we need to save | |
16710 | it. We use R12 for this purpose because emit_load_toc_table | |
16711 | can use register 0. This allows us to use a plain 'blr' to return | |
16712 | from the procedure more often. */ | |
16713 | int save_LR_around_toc_setup = (TARGET_ELF | |
16714 | && DEFAULT_ABI != ABI_AIX | |
16715 | && flag_pic | |
16716 | && ! info->lr_save_p | |
16717 | && EDGE_COUNT (EXIT_BLOCK_PTR->preds) > 0); | |
16718 | if (save_LR_around_toc_setup) | |
16719 | { | |
1de43f85 | 16720 | rtx lr = gen_rtx_REG (Pmode, LR_REGNO); |
f8a57be8 | 16721 | |
c4ad648e | 16722 | insn = emit_move_insn (frame_ptr_rtx, lr); |
c4ad648e | 16723 | RTX_FRAME_RELATED_P (insn) = 1; |
f8a57be8 | 16724 | |
c4ad648e | 16725 | rs6000_emit_load_toc_table (TRUE); |
f8a57be8 | 16726 | |
c4ad648e | 16727 | insn = emit_move_insn (lr, frame_ptr_rtx); |
c4ad648e AM |
16728 | RTX_FRAME_RELATED_P (insn) = 1; |
16729 | } | |
16730 | else | |
16731 | rs6000_emit_load_toc_table (TRUE); | |
16732 | } | |
ee890fe2 | 16733 | |
fcce224d | 16734 | #if TARGET_MACHO |
ee890fe2 | 16735 | if (DEFAULT_ABI == ABI_DARWIN |
e3b5732b | 16736 | && flag_pic && crtl->uses_pic_offset_table) |
ee890fe2 | 16737 | { |
1de43f85 | 16738 | rtx lr = gen_rtx_REG (Pmode, LR_REGNO); |
08a6a74b | 16739 | rtx src = gen_rtx_SYMBOL_REF (Pmode, MACHOPIC_FUNCTION_BASE_NAME); |
ee890fe2 | 16740 | |
6d0a8091 DJ |
16741 | /* Save and restore LR locally around this call (in R0). */ |
16742 | if (!info->lr_save_p) | |
6fb5fa3c | 16743 | emit_move_insn (gen_rtx_REG (Pmode, 0), lr); |
6d0a8091 | 16744 | |
6fb5fa3c | 16745 | emit_insn (gen_load_macho_picbase (src)); |
ee890fe2 | 16746 | |
6fb5fa3c DB |
16747 | emit_move_insn (gen_rtx_REG (Pmode, |
16748 | RS6000_PIC_OFFSET_TABLE_REGNUM), | |
16749 | lr); | |
6d0a8091 DJ |
16750 | |
16751 | if (!info->lr_save_p) | |
6fb5fa3c | 16752 | emit_move_insn (lr, gen_rtx_REG (Pmode, 0)); |
ee890fe2 | 16753 | } |
fcce224d | 16754 | #endif |
9ebbca7d GK |
16755 | } |
16756 | ||
9ebbca7d | 16757 | /* Write function prologue. */ |
a4f6c312 | 16758 | |
08c148a8 | 16759 | static void |
f676971a | 16760 | rs6000_output_function_prologue (FILE *file, |
a2369ed3 | 16761 | HOST_WIDE_INT size ATTRIBUTE_UNUSED) |
9ebbca7d GK |
16762 | { |
16763 | rs6000_stack_t *info = rs6000_stack_info (); | |
16764 | ||
4697a36c MM |
16765 | if (TARGET_DEBUG_STACK) |
16766 | debug_stack_info (info); | |
9878760c | 16767 | |
a4f6c312 SS |
16768 | /* Write .extern for any function we will call to save and restore |
16769 | fp values. */ | |
16770 | if (info->first_fp_reg_save < 64 | |
16771 | && !FP_SAVE_INLINE (info->first_fp_reg_save)) | |
4d30c363 | 16772 | fprintf (file, "\t.extern %s%d%s\n\t.extern %s%d%s\n", |
4697a36c | 16773 | SAVE_FP_PREFIX, info->first_fp_reg_save - 32, SAVE_FP_SUFFIX, |
f78c3290 | 16774 | RESTORE_FP_PREFIX, info->first_fp_reg_save - 32, RESTORE_FP_SUFFIX); |
9878760c | 16775 | |
c764f757 RK |
16776 | /* Write .extern for AIX common mode routines, if needed. */ |
16777 | if (! TARGET_POWER && ! TARGET_POWERPC && ! common_mode_defined) | |
16778 | { | |
f6709c70 JW |
16779 | fputs ("\t.extern __mulh\n", file); |
16780 | fputs ("\t.extern __mull\n", file); | |
16781 | fputs ("\t.extern __divss\n", file); | |
16782 | fputs ("\t.extern __divus\n", file); | |
16783 | fputs ("\t.extern __quoss\n", file); | |
16784 | fputs ("\t.extern __quous\n", file); | |
c764f757 RK |
16785 | common_mode_defined = 1; |
16786 | } | |
9878760c | 16787 | |
9ebbca7d | 16788 | if (! HAVE_prologue) |
979721f8 | 16789 | { |
9ebbca7d | 16790 | start_sequence (); |
9dda4cc8 | 16791 | |
a4f6c312 SS |
16792 | /* A NOTE_INSN_DELETED is supposed to be at the start and end of |
16793 | the "toplevel" insn chain. */ | |
2e040219 | 16794 | emit_note (NOTE_INSN_DELETED); |
9ebbca7d | 16795 | rs6000_emit_prologue (); |
2e040219 | 16796 | emit_note (NOTE_INSN_DELETED); |
178c3eff | 16797 | |
a3c9585f | 16798 | /* Expand INSN_ADDRESSES so final() doesn't crash. */ |
178c3eff DJ |
16799 | { |
16800 | rtx insn; | |
16801 | unsigned addr = 0; | |
16802 | for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn)) | |
16803 | { | |
16804 | INSN_ADDRESSES_NEW (insn, addr); | |
16805 | addr += 4; | |
16806 | } | |
16807 | } | |
9dda4cc8 | 16808 | |
9ebbca7d | 16809 | if (TARGET_DEBUG_STACK) |
a4f6c312 | 16810 | debug_rtx_list (get_insns (), 100); |
c9d691e9 | 16811 | final (get_insns (), file, FALSE); |
9ebbca7d | 16812 | end_sequence (); |
979721f8 MM |
16813 | } |
16814 | ||
9ebbca7d GK |
16815 | rs6000_pic_labelno++; |
16816 | } | |
f676971a | 16817 | |
1c9c5e43 AM |
16818 | /* Non-zero if vmx regs are restored before the frame pop, zero if |
16819 | we restore after the pop when possible. */ | |
16820 | #define ALWAYS_RESTORE_ALTIVEC_BEFORE_POP 0 | |
16821 | ||
f78c3290 NF |
16822 | /* Reload CR from REG. */ |
16823 | ||
16824 | static void | |
16825 | rs6000_restore_saved_cr (rtx reg, int using_mfcr_multiple) | |
16826 | { | |
16827 | int count = 0; | |
16828 | int i; | |
16829 | ||
16830 | if (using_mfcr_multiple) | |
16831 | { | |
16832 | for (i = 0; i < 8; i++) | |
16833 | if (df_regs_ever_live_p (CR0_REGNO+i) && ! call_used_regs[CR0_REGNO+i]) | |
16834 | count++; | |
16835 | gcc_assert (count); | |
16836 | } | |
16837 | ||
16838 | if (using_mfcr_multiple && count > 1) | |
16839 | { | |
16840 | rtvec p; | |
16841 | int ndx; | |
16842 | ||
16843 | p = rtvec_alloc (count); | |
16844 | ||
16845 | ndx = 0; | |
16846 | for (i = 0; i < 8; i++) | |
16847 | if (df_regs_ever_live_p (CR0_REGNO+i) && ! call_used_regs[CR0_REGNO+i]) | |
16848 | { | |
16849 | rtvec r = rtvec_alloc (2); | |
16850 | RTVEC_ELT (r, 0) = reg; | |
16851 | RTVEC_ELT (r, 1) = GEN_INT (1 << (7-i)); | |
16852 | RTVEC_ELT (p, ndx) = | |
16853 | gen_rtx_SET (VOIDmode, gen_rtx_REG (CCmode, CR0_REGNO+i), | |
16854 | gen_rtx_UNSPEC (CCmode, r, UNSPEC_MOVESI_TO_CR)); | |
16855 | ndx++; | |
16856 | } | |
16857 | emit_insn (gen_rtx_PARALLEL (VOIDmode, p)); | |
16858 | gcc_assert (ndx == count); | |
16859 | } | |
16860 | else | |
16861 | for (i = 0; i < 8; i++) | |
16862 | if (df_regs_ever_live_p (CR0_REGNO+i) && ! call_used_regs[CR0_REGNO+i]) | |
16863 | { | |
16864 | emit_insn (gen_movsi_to_cr_one (gen_rtx_REG (CCmode, | |
16865 | CR0_REGNO+i), | |
16866 | reg)); | |
16867 | } | |
16868 | } | |
16869 | ||
9ebbca7d | 16870 | /* Emit function epilogue as insns. |
9878760c | 16871 | |
9ebbca7d GK |
16872 | At present, dwarf2out_frame_debug_expr doesn't understand |
16873 | register restores, so we don't bother setting RTX_FRAME_RELATED_P | |
16874 | anywhere in the epilogue. Most of the insns below would in any case | |
16875 | need special notes to explain where r11 is in relation to the stack. */ | |
9878760c | 16876 | |
9ebbca7d | 16877 | void |
a2369ed3 | 16878 | rs6000_emit_epilogue (int sibcall) |
9ebbca7d GK |
16879 | { |
16880 | rs6000_stack_t *info; | |
f78c3290 | 16881 | int restoring_GPRs_inline; |
9ebbca7d GK |
16882 | int restoring_FPRs_inline; |
16883 | int using_load_multiple; | |
d296e02e | 16884 | int using_mtcr_multiple; |
9ebbca7d | 16885 | int use_backchain_to_restore_sp; |
f78c3290 NF |
16886 | int restore_lr; |
16887 | int strategy; | |
9ebbca7d GK |
16888 | int sp_offset = 0; |
16889 | rtx sp_reg_rtx = gen_rtx_REG (Pmode, 1); | |
16890 | rtx frame_reg_rtx = sp_reg_rtx; | |
0e67400a | 16891 | enum machine_mode reg_mode = Pmode; |
327e5343 | 16892 | int reg_size = TARGET_32BIT ? 4 : 8; |
9ebbca7d GK |
16893 | int i; |
16894 | ||
c19de7aa AH |
16895 | info = rs6000_stack_info (); |
16896 | ||
16897 | if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0) | |
a3170dc6 AH |
16898 | { |
16899 | reg_mode = V2SImode; | |
16900 | reg_size = 8; | |
16901 | } | |
16902 | ||
f78c3290 NF |
16903 | strategy = rs6000_savres_strategy (info, /*savep=*/false, |
16904 | /*static_chain_p=*/0, sibcall); | |
16905 | using_load_multiple = strategy & SAVRES_MULTIPLE; | |
16906 | restoring_FPRs_inline = strategy & SAVRES_INLINE_FPRS; | |
16907 | restoring_GPRs_inline = strategy & SAVRES_INLINE_GPRS; | |
d296e02e | 16908 | using_mtcr_multiple = (rs6000_cpu == PROCESSOR_PPC601 |
9ebbca7d GK |
16909 | || rs6000_cpu == PROCESSOR_PPC603 |
16910 | || rs6000_cpu == PROCESSOR_PPC750 | |
16911 | || optimize_size); | |
1c9c5e43 AM |
16912 | /* Restore via the backchain when we have a large frame, since this |
16913 | is more efficient than an addis, addi pair. The second condition | |
16914 | here will not trigger at the moment; We don't actually need a | |
16915 | frame pointer for alloca, but the generic parts of the compiler | |
16916 | give us one anyway. */ | |
16917 | use_backchain_to_restore_sp = (info->total_size > 32767 | |
d2492102 AP |
16918 | || info->total_size |
16919 | + (info->lr_save_p ? info->lr_save_offset : 0) | |
16920 | > 32767 | |
1c9c5e43 AM |
16921 | || (cfun->calls_alloca |
16922 | && !frame_pointer_needed)); | |
f78c3290 NF |
16923 | restore_lr = (info->lr_save_p |
16924 | && restoring_GPRs_inline | |
16925 | && restoring_FPRs_inline); | |
9ebbca7d | 16926 | |
f57fe068 | 16927 | if (WORLD_SAVE_P (info)) |
d62294f5 FJ |
16928 | { |
16929 | int i, j; | |
16930 | char rname[30]; | |
16931 | const char *alloc_rname; | |
16932 | rtvec p; | |
16933 | ||
16934 | /* eh_rest_world_r10 will return to the location saved in the LR | |
c4ad648e AM |
16935 | stack slot (which is not likely to be our caller.) |
16936 | Input: R10 -- stack adjustment. Clobbers R0, R11, R12, R7, R8. | |
16937 | rest_world is similar, except any R10 parameter is ignored. | |
16938 | The exception-handling stuff that was here in 2.95 is no | |
16939 | longer necessary. */ | |
d62294f5 FJ |
16940 | |
16941 | p = rtvec_alloc (9 | |
16942 | + 1 | |
f676971a | 16943 | + 32 - info->first_gp_reg_save |
c4ad648e AM |
16944 | + LAST_ALTIVEC_REGNO + 1 - info->first_altivec_reg_save |
16945 | + 63 + 1 - info->first_fp_reg_save); | |
d62294f5 | 16946 | |
e3b5732b | 16947 | strcpy (rname, ((crtl->calls_eh_return) ? |
c4ad648e | 16948 | "*eh_rest_world_r10" : "*rest_world")); |
d62294f5 FJ |
16949 | alloc_rname = ggc_strdup (rname); |
16950 | ||
16951 | j = 0; | |
16952 | RTVEC_ELT (p, j++) = gen_rtx_RETURN (VOIDmode); | |
16953 | RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode, | |
c4ad648e | 16954 | gen_rtx_REG (Pmode, |
1de43f85 | 16955 | LR_REGNO)); |
d62294f5 | 16956 | RTVEC_ELT (p, j++) |
c4ad648e | 16957 | = gen_rtx_USE (VOIDmode, gen_rtx_SYMBOL_REF (Pmode, alloc_rname)); |
d62294f5 | 16958 | /* The instruction pattern requires a clobber here; |
c4ad648e | 16959 | it is shared with the restVEC helper. */ |
d62294f5 | 16960 | RTVEC_ELT (p, j++) |
c4ad648e | 16961 | = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 11)); |
d62294f5 FJ |
16962 | |
16963 | { | |
c4ad648e AM |
16964 | /* CR register traditionally saved as CR2. */ |
16965 | rtx reg = gen_rtx_REG (reg_mode, CR2_REGNO); | |
16966 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
16967 | GEN_INT (info->cr_save_offset)); | |
0be76840 | 16968 | rtx mem = gen_frame_mem (reg_mode, addr); |
c4ad648e AM |
16969 | |
16970 | RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem); | |
d62294f5 FJ |
16971 | } |
16972 | ||
16973 | for (i = 0; i < 32 - info->first_gp_reg_save; i++) | |
c4ad648e AM |
16974 | { |
16975 | rtx reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i); | |
16976 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
16977 | GEN_INT (info->gp_save_offset | |
16978 | + reg_size * i)); | |
0be76840 | 16979 | rtx mem = gen_frame_mem (reg_mode, addr); |
c4ad648e AM |
16980 | |
16981 | RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem); | |
16982 | } | |
d62294f5 | 16983 | for (i = 0; info->first_altivec_reg_save + i <= LAST_ALTIVEC_REGNO; i++) |
c4ad648e AM |
16984 | { |
16985 | rtx reg = gen_rtx_REG (V4SImode, info->first_altivec_reg_save + i); | |
16986 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
16987 | GEN_INT (info->altivec_save_offset | |
16988 | + 16 * i)); | |
0be76840 | 16989 | rtx mem = gen_frame_mem (V4SImode, addr); |
c4ad648e AM |
16990 | |
16991 | RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem); | |
16992 | } | |
d62294f5 | 16993 | for (i = 0; info->first_fp_reg_save + i <= 63; i++) |
c4ad648e | 16994 | { |
696e45ba ME |
16995 | rtx reg = gen_rtx_REG (((TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT) |
16996 | ? DFmode : SFmode), | |
16997 | info->first_fp_reg_save + i); | |
c4ad648e AM |
16998 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, |
16999 | GEN_INT (info->fp_save_offset | |
17000 | + 8 * i)); | |
696e45ba ME |
17001 | rtx mem = gen_frame_mem (((TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT) |
17002 | ? DFmode : SFmode), addr); | |
c4ad648e AM |
17003 | |
17004 | RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem); | |
17005 | } | |
d62294f5 | 17006 | RTVEC_ELT (p, j++) |
c4ad648e | 17007 | = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 0)); |
d62294f5 | 17008 | RTVEC_ELT (p, j++) |
c4ad648e | 17009 | = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 12)); |
d62294f5 | 17010 | RTVEC_ELT (p, j++) |
c4ad648e | 17011 | = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 7)); |
d62294f5 | 17012 | RTVEC_ELT (p, j++) |
c4ad648e | 17013 | = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 8)); |
d62294f5 | 17014 | RTVEC_ELT (p, j++) |
c4ad648e | 17015 | = gen_rtx_USE (VOIDmode, gen_rtx_REG (SImode, 10)); |
d62294f5 FJ |
17016 | emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p)); |
17017 | ||
17018 | return; | |
17019 | } | |
17020 | ||
45b194f8 AM |
17021 | /* frame_reg_rtx + sp_offset points to the top of this stack frame. */ |
17022 | if (info->push_p) | |
2b2c2fe5 | 17023 | sp_offset = info->total_size; |
f676971a | 17024 | |
e6477eaa AM |
17025 | /* Restore AltiVec registers if we must do so before adjusting the |
17026 | stack. */ | |
17027 | if (TARGET_ALTIVEC_ABI | |
17028 | && info->altivec_size != 0 | |
1c9c5e43 AM |
17029 | && (ALWAYS_RESTORE_ALTIVEC_BEFORE_POP |
17030 | || (DEFAULT_ABI != ABI_V4 | |
17031 | && info->altivec_save_offset < (TARGET_32BIT ? -220 : -288)))) | |
9aa86737 AH |
17032 | { |
17033 | int i; | |
17034 | ||
e6477eaa AM |
17035 | if (use_backchain_to_restore_sp) |
17036 | { | |
17037 | frame_reg_rtx = gen_rtx_REG (Pmode, 11); | |
17038 | emit_move_insn (frame_reg_rtx, | |
17039 | gen_rtx_MEM (Pmode, sp_reg_rtx)); | |
17040 | sp_offset = 0; | |
17041 | } | |
1c9c5e43 AM |
17042 | else if (frame_pointer_needed) |
17043 | frame_reg_rtx = hard_frame_pointer_rtx; | |
e6477eaa | 17044 | |
9aa86737 AH |
17045 | for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i) |
17046 | if (info->vrsave_mask & ALTIVEC_REG_BIT (i)) | |
17047 | { | |
17048 | rtx addr, areg, mem; | |
17049 | ||
17050 | areg = gen_rtx_REG (Pmode, 0); | |
17051 | emit_move_insn | |
17052 | (areg, GEN_INT (info->altivec_save_offset | |
17053 | + sp_offset | |
17054 | + 16 * (i - info->first_altivec_reg_save))); | |
17055 | ||
17056 | /* AltiVec addressing mode is [reg+reg]. */ | |
17057 | addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, areg); | |
0be76840 | 17058 | mem = gen_frame_mem (V4SImode, addr); |
9aa86737 AH |
17059 | |
17060 | emit_move_insn (gen_rtx_REG (V4SImode, i), mem); | |
17061 | } | |
17062 | } | |
17063 | ||
e6477eaa AM |
17064 | /* Restore VRSAVE if we must do so before adjusting the stack. */ |
17065 | if (TARGET_ALTIVEC | |
17066 | && TARGET_ALTIVEC_VRSAVE | |
17067 | && info->vrsave_mask != 0 | |
1c9c5e43 AM |
17068 | && (ALWAYS_RESTORE_ALTIVEC_BEFORE_POP |
17069 | || (DEFAULT_ABI != ABI_V4 | |
17070 | && info->vrsave_save_offset < (TARGET_32BIT ? -220 : -288)))) | |
e6477eaa AM |
17071 | { |
17072 | rtx addr, mem, reg; | |
17073 | ||
1c9c5e43 | 17074 | if (frame_reg_rtx == sp_reg_rtx) |
e6477eaa | 17075 | { |
1c9c5e43 AM |
17076 | if (use_backchain_to_restore_sp) |
17077 | { | |
17078 | frame_reg_rtx = gen_rtx_REG (Pmode, 11); | |
17079 | emit_move_insn (frame_reg_rtx, | |
17080 | gen_rtx_MEM (Pmode, sp_reg_rtx)); | |
17081 | sp_offset = 0; | |
17082 | } | |
17083 | else if (frame_pointer_needed) | |
17084 | frame_reg_rtx = hard_frame_pointer_rtx; | |
e6477eaa AM |
17085 | } |
17086 | ||
17087 | addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
17088 | GEN_INT (info->vrsave_save_offset + sp_offset)); | |
17089 | mem = gen_frame_mem (SImode, addr); | |
17090 | reg = gen_rtx_REG (SImode, 12); | |
17091 | emit_move_insn (reg, mem); | |
17092 | ||
17093 | emit_insn (generate_set_vrsave (reg, info, 1)); | |
17094 | } | |
17095 | ||
1c9c5e43 AM |
17096 | /* If we have a large stack frame, restore the old stack pointer |
17097 | using the backchain. */ | |
2b2c2fe5 EC |
17098 | if (use_backchain_to_restore_sp) |
17099 | { | |
1c9c5e43 | 17100 | if (frame_reg_rtx == sp_reg_rtx) |
e6477eaa AM |
17101 | { |
17102 | /* Under V.4, don't reset the stack pointer until after we're done | |
17103 | loading the saved registers. */ | |
17104 | if (DEFAULT_ABI == ABI_V4) | |
17105 | frame_reg_rtx = gen_rtx_REG (Pmode, 11); | |
17106 | ||
17107 | emit_move_insn (frame_reg_rtx, | |
17108 | gen_rtx_MEM (Pmode, sp_reg_rtx)); | |
17109 | sp_offset = 0; | |
17110 | } | |
1c9c5e43 AM |
17111 | else if (ALWAYS_RESTORE_ALTIVEC_BEFORE_POP |
17112 | && DEFAULT_ABI == ABI_V4) | |
17113 | /* frame_reg_rtx has been set up by the altivec restore. */ | |
17114 | ; | |
17115 | else | |
17116 | { | |
17117 | emit_move_insn (sp_reg_rtx, frame_reg_rtx); | |
17118 | frame_reg_rtx = sp_reg_rtx; | |
17119 | } | |
17120 | } | |
17121 | /* If we have a frame pointer, we can restore the old stack pointer | |
17122 | from it. */ | |
17123 | else if (frame_pointer_needed) | |
17124 | { | |
17125 | frame_reg_rtx = sp_reg_rtx; | |
17126 | if (DEFAULT_ABI == ABI_V4) | |
17127 | frame_reg_rtx = gen_rtx_REG (Pmode, 11); | |
17128 | ||
17129 | emit_insn (TARGET_32BIT | |
17130 | ? gen_addsi3 (frame_reg_rtx, hard_frame_pointer_rtx, | |
17131 | GEN_INT (info->total_size)) | |
17132 | : gen_adddi3 (frame_reg_rtx, hard_frame_pointer_rtx, | |
17133 | GEN_INT (info->total_size))); | |
17134 | sp_offset = 0; | |
2b2c2fe5 | 17135 | } |
45b194f8 AM |
17136 | else if (info->push_p |
17137 | && DEFAULT_ABI != ABI_V4 | |
e3b5732b | 17138 | && !crtl->calls_eh_return) |
2b2c2fe5 | 17139 | { |
45b194f8 AM |
17140 | emit_insn (TARGET_32BIT |
17141 | ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx, | |
17142 | GEN_INT (info->total_size)) | |
17143 | : gen_adddi3 (sp_reg_rtx, sp_reg_rtx, | |
17144 | GEN_INT (info->total_size))); | |
17145 | sp_offset = 0; | |
2b2c2fe5 EC |
17146 | } |
17147 | ||
e6477eaa | 17148 | /* Restore AltiVec registers if we have not done so already. */ |
1c9c5e43 AM |
17149 | if (!ALWAYS_RESTORE_ALTIVEC_BEFORE_POP |
17150 | && TARGET_ALTIVEC_ABI | |
e6477eaa AM |
17151 | && info->altivec_size != 0 |
17152 | && (DEFAULT_ABI == ABI_V4 | |
17153 | || info->altivec_save_offset >= (TARGET_32BIT ? -220 : -288))) | |
17154 | { | |
17155 | int i; | |
17156 | ||
17157 | for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i) | |
17158 | if (info->vrsave_mask & ALTIVEC_REG_BIT (i)) | |
17159 | { | |
17160 | rtx addr, areg, mem; | |
17161 | ||
17162 | areg = gen_rtx_REG (Pmode, 0); | |
17163 | emit_move_insn | |
17164 | (areg, GEN_INT (info->altivec_save_offset | |
17165 | + sp_offset | |
17166 | + 16 * (i - info->first_altivec_reg_save))); | |
17167 | ||
17168 | /* AltiVec addressing mode is [reg+reg]. */ | |
17169 | addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, areg); | |
17170 | mem = gen_frame_mem (V4SImode, addr); | |
17171 | ||
17172 | emit_move_insn (gen_rtx_REG (V4SImode, i), mem); | |
17173 | } | |
17174 | } | |
17175 | ||
17176 | /* Restore VRSAVE if we have not done so already. */ | |
1c9c5e43 AM |
17177 | if (!ALWAYS_RESTORE_ALTIVEC_BEFORE_POP |
17178 | && TARGET_ALTIVEC | |
e6477eaa AM |
17179 | && TARGET_ALTIVEC_VRSAVE |
17180 | && info->vrsave_mask != 0 | |
17181 | && (DEFAULT_ABI == ABI_V4 | |
17182 | || info->vrsave_save_offset >= (TARGET_32BIT ? -220 : -288))) | |
554c2941 AM |
17183 | { |
17184 | rtx addr, mem, reg; | |
17185 | ||
17186 | addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
17187 | GEN_INT (info->vrsave_save_offset + sp_offset)); | |
17188 | mem = gen_frame_mem (SImode, addr); | |
17189 | reg = gen_rtx_REG (SImode, 12); | |
17190 | emit_move_insn (reg, mem); | |
17191 | ||
17192 | emit_insn (generate_set_vrsave (reg, info, 1)); | |
17193 | } | |
17194 | ||
f78c3290 NF |
17195 | /* Get the old lr if we saved it. If we are restoring registers |
17196 | out-of-line, then the out-of-line routines can do this for us. */ | |
17197 | if (restore_lr) | |
b6c9286a | 17198 | { |
a3170dc6 AH |
17199 | rtx mem = gen_frame_mem_offset (Pmode, frame_reg_rtx, |
17200 | info->lr_save_offset + sp_offset); | |
ba4828e0 | 17201 | |
9ebbca7d | 17202 | emit_move_insn (gen_rtx_REG (Pmode, 0), mem); |
b6c9286a | 17203 | } |
f676971a | 17204 | |
9ebbca7d GK |
17205 | /* Get the old cr if we saved it. */ |
17206 | if (info->cr_save_p) | |
17207 | { | |
17208 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
17209 | GEN_INT (info->cr_save_offset + sp_offset)); | |
0be76840 | 17210 | rtx mem = gen_frame_mem (SImode, addr); |
b6c9286a | 17211 | |
9ebbca7d GK |
17212 | emit_move_insn (gen_rtx_REG (SImode, 12), mem); |
17213 | } | |
f676971a | 17214 | |
9ebbca7d | 17215 | /* Set LR here to try to overlap restores below. */ |
f78c3290 | 17216 | if (restore_lr) |
1de43f85 | 17217 | emit_move_insn (gen_rtx_REG (Pmode, LR_REGNO), |
9ebbca7d | 17218 | gen_rtx_REG (Pmode, 0)); |
f676971a | 17219 | |
83720594 | 17220 | /* Load exception handler data registers, if needed. */ |
e3b5732b | 17221 | if (crtl->calls_eh_return) |
83720594 | 17222 | { |
78e1b90d DE |
17223 | unsigned int i, regno; |
17224 | ||
fc4767bb JJ |
17225 | if (TARGET_AIX) |
17226 | { | |
17227 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
17228 | GEN_INT (sp_offset + 5 * reg_size)); | |
0be76840 | 17229 | rtx mem = gen_frame_mem (reg_mode, addr); |
fc4767bb JJ |
17230 | |
17231 | emit_move_insn (gen_rtx_REG (reg_mode, 2), mem); | |
17232 | } | |
17233 | ||
83720594 RH |
17234 | for (i = 0; ; ++i) |
17235 | { | |
a3170dc6 | 17236 | rtx mem; |
83720594 RH |
17237 | |
17238 | regno = EH_RETURN_DATA_REGNO (i); | |
17239 | if (regno == INVALID_REGNUM) | |
17240 | break; | |
17241 | ||
a3170dc6 AH |
17242 | mem = gen_frame_mem_offset (reg_mode, frame_reg_rtx, |
17243 | info->ehrd_offset + sp_offset | |
17244 | + reg_size * (int) i); | |
83720594 RH |
17245 | |
17246 | emit_move_insn (gen_rtx_REG (reg_mode, regno), mem); | |
17247 | } | |
17248 | } | |
f676971a | 17249 | |
9ebbca7d GK |
17250 | /* Restore GPRs. This is done as a PARALLEL if we are using |
17251 | the load-multiple instructions. */ | |
f78c3290 NF |
17252 | if (TARGET_SPE_ABI |
17253 | && info->spe_64bit_regs_used != 0 | |
17254 | && info->first_gp_reg_save != 32) | |
52ff33d0 | 17255 | { |
52ff33d0 NF |
17256 | /* Determine whether we can address all of the registers that need |
17257 | to be saved with an offset from the stack pointer that fits in | |
17258 | the small const field for SPE memory instructions. */ | |
17259 | int spe_regs_addressable_via_sp | |
f78c3290 NF |
17260 | = (SPE_CONST_OFFSET_OK(info->spe_gp_save_offset + sp_offset |
17261 | + (32 - info->first_gp_reg_save - 1) * reg_size) | |
17262 | && restoring_GPRs_inline); | |
52ff33d0 NF |
17263 | int spe_offset; |
17264 | ||
17265 | if (spe_regs_addressable_via_sp) | |
45b194f8 | 17266 | spe_offset = info->spe_gp_save_offset + sp_offset; |
52ff33d0 NF |
17267 | else |
17268 | { | |
45b194f8 | 17269 | rtx old_frame_reg_rtx = frame_reg_rtx; |
52ff33d0 | 17270 | /* Make r11 point to the start of the SPE save area. We worried about |
6ed3da00 | 17271 | not clobbering it when we were saving registers in the prologue. |
52ff33d0 NF |
17272 | There's no need to worry here because the static chain is passed |
17273 | anew to every function. */ | |
f78c3290 NF |
17274 | int ool_adjust = (restoring_GPRs_inline |
17275 | ? 0 | |
17276 | : (info->first_gp_reg_save | |
17277 | - (FIRST_SAVRES_REGISTER+1))*8); | |
17278 | ||
45b194f8 AM |
17279 | if (frame_reg_rtx == sp_reg_rtx) |
17280 | frame_reg_rtx = gen_rtx_REG (Pmode, 11); | |
17281 | emit_insn (gen_addsi3 (frame_reg_rtx, old_frame_reg_rtx, | |
f78c3290 NF |
17282 | GEN_INT (info->spe_gp_save_offset |
17283 | + sp_offset | |
17284 | - ool_adjust))); | |
45b194f8 AM |
17285 | /* Keep the invariant that frame_reg_rtx + sp_offset points |
17286 | at the top of the stack frame. */ | |
17287 | sp_offset = -info->spe_gp_save_offset; | |
52ff33d0 NF |
17288 | |
17289 | spe_offset = 0; | |
17290 | } | |
17291 | ||
f78c3290 NF |
17292 | if (restoring_GPRs_inline) |
17293 | { | |
17294 | for (i = 0; i < 32 - info->first_gp_reg_save; i++) | |
17295 | if (rs6000_reg_live_or_pic_offset_p (info->first_gp_reg_save + i)) | |
17296 | { | |
17297 | rtx offset, addr, mem; | |
52ff33d0 | 17298 | |
f78c3290 NF |
17299 | /* We're doing all this to ensure that the immediate offset |
17300 | fits into the immediate field of 'evldd'. */ | |
17301 | gcc_assert (SPE_CONST_OFFSET_OK (spe_offset + reg_size * i)); | |
52ff33d0 | 17302 | |
f78c3290 NF |
17303 | offset = GEN_INT (spe_offset + reg_size * i); |
17304 | addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, offset); | |
17305 | mem = gen_rtx_MEM (V2SImode, addr); | |
52ff33d0 | 17306 | |
f78c3290 NF |
17307 | emit_move_insn (gen_rtx_REG (reg_mode, info->first_gp_reg_save + i), |
17308 | mem); | |
17309 | } | |
17310 | } | |
17311 | else | |
17312 | { | |
17313 | rtx par; | |
17314 | ||
17315 | par = rs6000_make_savres_rtx (info, gen_rtx_REG (Pmode, 11), | |
17316 | 0, reg_mode, | |
17317 | /*savep=*/false, /*gpr=*/true, | |
17318 | /*exitp=*/true); | |
17319 | emit_jump_insn (par); | |
17320 | ||
17321 | /* We don't want anybody else emitting things after we jumped | |
17322 | back. */ | |
17323 | return; | |
17324 | } | |
52ff33d0 | 17325 | } |
f78c3290 NF |
17326 | else if (!restoring_GPRs_inline) |
17327 | { | |
17328 | /* We are jumping to an out-of-line function. */ | |
17329 | bool can_use_exit = info->first_fp_reg_save == 64; | |
17330 | rtx par; | |
17331 | ||
17332 | /* Emit stack reset code if we need it. */ | |
17333 | if (can_use_exit) | |
17334 | rs6000_emit_stack_reset (info, sp_reg_rtx, frame_reg_rtx, | |
17335 | sp_offset, can_use_exit); | |
17336 | else | |
17337 | emit_insn (gen_addsi3 (gen_rtx_REG (Pmode, 11), | |
17338 | sp_reg_rtx, | |
17339 | GEN_INT (sp_offset - info->fp_size))); | |
17340 | ||
17341 | par = rs6000_make_savres_rtx (info, frame_reg_rtx, | |
17342 | info->gp_save_offset, reg_mode, | |
17343 | /*savep=*/false, /*gpr=*/true, | |
17344 | /*exitp=*/can_use_exit); | |
17345 | ||
17346 | if (can_use_exit) | |
17347 | { | |
17348 | if (info->cr_save_p) | |
17349 | rs6000_restore_saved_cr (gen_rtx_REG (SImode, 12), | |
17350 | using_mtcr_multiple); | |
17351 | ||
17352 | emit_jump_insn (par); | |
17353 | ||
17354 | /* We don't want anybody else emitting things after we jumped | |
17355 | back. */ | |
17356 | return; | |
17357 | } | |
17358 | else | |
17359 | emit_insn (par); | |
17360 | } | |
17361 | else if (using_load_multiple) | |
17362 | { | |
17363 | rtvec p; | |
17364 | p = rtvec_alloc (32 - info->first_gp_reg_save); | |
17365 | for (i = 0; i < 32 - info->first_gp_reg_save; i++) | |
9ebbca7d | 17366 | { |
f676971a EC |
17367 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, |
17368 | GEN_INT (info->gp_save_offset | |
17369 | + sp_offset | |
9ebbca7d | 17370 | + reg_size * i)); |
0be76840 | 17371 | rtx mem = gen_frame_mem (reg_mode, addr); |
ba4828e0 | 17372 | |
f78c3290 NF |
17373 | RTVEC_ELT (p, i) = |
17374 | gen_rtx_SET (VOIDmode, | |
17375 | gen_rtx_REG (reg_mode, info->first_gp_reg_save + i), | |
17376 | mem); | |
9ebbca7d | 17377 | } |
f78c3290 NF |
17378 | emit_insn (gen_rtx_PARALLEL (VOIDmode, p)); |
17379 | } | |
17380 | else | |
17381 | { | |
17382 | for (i = 0; i < 32 - info->first_gp_reg_save; i++) | |
17383 | if (rs6000_reg_live_or_pic_offset_p (info->first_gp_reg_save + i)) | |
17384 | { | |
17385 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
17386 | GEN_INT (info->gp_save_offset | |
17387 | + sp_offset | |
17388 | + reg_size * i)); | |
17389 | rtx mem = gen_frame_mem (reg_mode, addr); | |
17390 | ||
17391 | emit_move_insn (gen_rtx_REG (reg_mode, | |
17392 | info->first_gp_reg_save + i), mem); | |
17393 | } | |
17394 | } | |
9878760c | 17395 | |
9ebbca7d GK |
17396 | /* Restore fpr's if we need to do it without calling a function. */ |
17397 | if (restoring_FPRs_inline) | |
17398 | for (i = 0; i < 64 - info->first_fp_reg_save; i++) | |
6fb5fa3c | 17399 | if ((df_regs_ever_live_p (info->first_fp_reg_save+i) |
9ebbca7d GK |
17400 | && ! call_used_regs[info->first_fp_reg_save+i])) |
17401 | { | |
17402 | rtx addr, mem; | |
17403 | addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
f676971a EC |
17404 | GEN_INT (info->fp_save_offset |
17405 | + sp_offset | |
a4f6c312 | 17406 | + 8 * i)); |
696e45ba ME |
17407 | mem = gen_frame_mem (((TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT) |
17408 | ? DFmode : SFmode), addr); | |
9ebbca7d | 17409 | |
696e45ba ME |
17410 | emit_move_insn (gen_rtx_REG (((TARGET_HARD_FLOAT |
17411 | && TARGET_DOUBLE_FLOAT) | |
17412 | ? DFmode : SFmode), | |
9ebbca7d GK |
17413 | info->first_fp_reg_save + i), |
17414 | mem); | |
17415 | } | |
8d30c4ee | 17416 | |
9ebbca7d GK |
17417 | /* If we saved cr, restore it here. Just those that were used. */ |
17418 | if (info->cr_save_p) | |
f78c3290 | 17419 | rs6000_restore_saved_cr (gen_rtx_REG (SImode, 12), using_mtcr_multiple); |
979721f8 | 17420 | |
9ebbca7d | 17421 | /* If this is V.4, unwind the stack pointer after all of the loads |
022123e6 | 17422 | have been done. */ |
f78c3290 NF |
17423 | rs6000_emit_stack_reset (info, sp_reg_rtx, frame_reg_rtx, |
17424 | sp_offset, !restoring_FPRs_inline); | |
b6c9286a | 17425 | |
e3b5732b | 17426 | if (crtl->calls_eh_return) |
83720594 RH |
17427 | { |
17428 | rtx sa = EH_RETURN_STACKADJ_RTX; | |
5b71a4e7 | 17429 | emit_insn (TARGET_32BIT |
83720594 RH |
17430 | ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx, sa) |
17431 | : gen_adddi3 (sp_reg_rtx, sp_reg_rtx, sa)); | |
17432 | } | |
17433 | ||
9ebbca7d GK |
17434 | if (!sibcall) |
17435 | { | |
17436 | rtvec p; | |
17437 | if (! restoring_FPRs_inline) | |
f78c3290 | 17438 | p = rtvec_alloc (4 + 64 - info->first_fp_reg_save); |
9ebbca7d GK |
17439 | else |
17440 | p = rtvec_alloc (2); | |
b6c9286a | 17441 | |
e35b9579 | 17442 | RTVEC_ELT (p, 0) = gen_rtx_RETURN (VOIDmode); |
f78c3290 NF |
17443 | RTVEC_ELT (p, 1) = (restoring_FPRs_inline |
17444 | ? gen_rtx_USE (VOIDmode, gen_rtx_REG (Pmode, 65)) | |
17445 | : gen_rtx_CLOBBER (VOIDmode, | |
17446 | gen_rtx_REG (Pmode, 65))); | |
9ebbca7d GK |
17447 | |
17448 | /* If we have to restore more than two FP registers, branch to the | |
17449 | restore function. It will return to our caller. */ | |
17450 | if (! restoring_FPRs_inline) | |
17451 | { | |
17452 | int i; | |
f78c3290 NF |
17453 | rtx sym; |
17454 | ||
17455 | sym = rs6000_savres_routine_sym (info, | |
17456 | /*savep=*/false, | |
17457 | /*gpr=*/false, | |
17458 | /*exitp=*/true); | |
17459 | RTVEC_ELT (p, 2) = gen_rtx_USE (VOIDmode, sym); | |
17460 | RTVEC_ELT (p, 3) = gen_rtx_USE (VOIDmode, | |
17461 | gen_rtx_REG (Pmode, 11)); | |
9ebbca7d GK |
17462 | for (i = 0; i < 64 - info->first_fp_reg_save; i++) |
17463 | { | |
17464 | rtx addr, mem; | |
17465 | addr = gen_rtx_PLUS (Pmode, sp_reg_rtx, | |
17466 | GEN_INT (info->fp_save_offset + 8*i)); | |
0be76840 | 17467 | mem = gen_frame_mem (DFmode, addr); |
9ebbca7d | 17468 | |
f78c3290 | 17469 | RTVEC_ELT (p, i+4) = |
9ebbca7d GK |
17470 | gen_rtx_SET (VOIDmode, |
17471 | gen_rtx_REG (DFmode, info->first_fp_reg_save + i), | |
17472 | mem); | |
b6c9286a MM |
17473 | } |
17474 | } | |
f676971a | 17475 | |
9ebbca7d | 17476 | emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p)); |
3daf36a4 | 17477 | } |
9878760c RK |
17478 | } |
17479 | ||
17480 | /* Write function epilogue. */ | |
17481 | ||
08c148a8 | 17482 | static void |
f676971a | 17483 | rs6000_output_function_epilogue (FILE *file, |
a2369ed3 | 17484 | HOST_WIDE_INT size ATTRIBUTE_UNUSED) |
9878760c | 17485 | { |
9ebbca7d | 17486 | if (! HAVE_epilogue) |
9878760c | 17487 | { |
9ebbca7d GK |
17488 | rtx insn = get_last_insn (); |
17489 | /* If the last insn was a BARRIER, we don't have to write anything except | |
17490 | the trace table. */ | |
17491 | if (GET_CODE (insn) == NOTE) | |
17492 | insn = prev_nonnote_insn (insn); | |
17493 | if (insn == 0 || GET_CODE (insn) != BARRIER) | |
4697a36c | 17494 | { |
9ebbca7d GK |
17495 | /* This is slightly ugly, but at least we don't have two |
17496 | copies of the epilogue-emitting code. */ | |
17497 | start_sequence (); | |
17498 | ||
17499 | /* A NOTE_INSN_DELETED is supposed to be at the start | |
17500 | and end of the "toplevel" insn chain. */ | |
2e040219 | 17501 | emit_note (NOTE_INSN_DELETED); |
9ebbca7d | 17502 | rs6000_emit_epilogue (FALSE); |
2e040219 | 17503 | emit_note (NOTE_INSN_DELETED); |
9ebbca7d | 17504 | |
a3c9585f | 17505 | /* Expand INSN_ADDRESSES so final() doesn't crash. */ |
178c3eff DJ |
17506 | { |
17507 | rtx insn; | |
17508 | unsigned addr = 0; | |
17509 | for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn)) | |
17510 | { | |
17511 | INSN_ADDRESSES_NEW (insn, addr); | |
17512 | addr += 4; | |
17513 | } | |
17514 | } | |
17515 | ||
9ebbca7d | 17516 | if (TARGET_DEBUG_STACK) |
a4f6c312 | 17517 | debug_rtx_list (get_insns (), 100); |
c9d691e9 | 17518 | final (get_insns (), file, FALSE); |
9ebbca7d | 17519 | end_sequence (); |
4697a36c | 17520 | } |
9878760c | 17521 | } |
b4ac57ab | 17522 | |
efdba735 SH |
17523 | #if TARGET_MACHO |
17524 | macho_branch_islands (); | |
0e5da0be GK |
17525 | /* Mach-O doesn't support labels at the end of objects, so if |
17526 | it looks like we might want one, insert a NOP. */ | |
17527 | { | |
17528 | rtx insn = get_last_insn (); | |
17529 | while (insn | |
17530 | && NOTE_P (insn) | |
a38e7aa5 | 17531 | && NOTE_KIND (insn) != NOTE_INSN_DELETED_LABEL) |
0e5da0be | 17532 | insn = PREV_INSN (insn); |
f676971a EC |
17533 | if (insn |
17534 | && (LABEL_P (insn) | |
0e5da0be | 17535 | || (NOTE_P (insn) |
a38e7aa5 | 17536 | && NOTE_KIND (insn) == NOTE_INSN_DELETED_LABEL))) |
0e5da0be GK |
17537 | fputs ("\tnop\n", file); |
17538 | } | |
17539 | #endif | |
17540 | ||
9b30bae2 | 17541 | /* Output a traceback table here. See /usr/include/sys/debug.h for info |
314fc5a9 ILT |
17542 | on its format. |
17543 | ||
17544 | We don't output a traceback table if -finhibit-size-directive was | |
17545 | used. The documentation for -finhibit-size-directive reads | |
17546 | ``don't output a @code{.size} assembler directive, or anything | |
17547 | else that would cause trouble if the function is split in the | |
17548 | middle, and the two halves are placed at locations far apart in | |
17549 | memory.'' The traceback table has this property, since it | |
17550 | includes the offset from the start of the function to the | |
4d30c363 MM |
17551 | traceback table itself. |
17552 | ||
17553 | System V.4 Powerpc's (and the embedded ABI derived from it) use a | |
b6c9286a | 17554 | different traceback table. */ |
57ac7be9 | 17555 | if (DEFAULT_ABI == ABI_AIX && ! flag_inhibit_size_directive |
3c072c6b | 17556 | && rs6000_traceback != traceback_none && !cfun->is_thunk) |
9b30bae2 | 17557 | { |
69c75916 | 17558 | const char *fname = NULL; |
3ac88239 | 17559 | const char *language_string = lang_hooks.name; |
6041bf2f | 17560 | int fixed_parms = 0, float_parms = 0, parm_info = 0; |
314fc5a9 | 17561 | int i; |
57ac7be9 | 17562 | int optional_tbtab; |
8097c268 | 17563 | rs6000_stack_t *info = rs6000_stack_info (); |
57ac7be9 AM |
17564 | |
17565 | if (rs6000_traceback == traceback_full) | |
17566 | optional_tbtab = 1; | |
17567 | else if (rs6000_traceback == traceback_part) | |
17568 | optional_tbtab = 0; | |
17569 | else | |
17570 | optional_tbtab = !optimize_size && !TARGET_ELF; | |
314fc5a9 | 17571 | |
69c75916 AM |
17572 | if (optional_tbtab) |
17573 | { | |
17574 | fname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0); | |
17575 | while (*fname == '.') /* V.4 encodes . in the name */ | |
17576 | fname++; | |
17577 | ||
17578 | /* Need label immediately before tbtab, so we can compute | |
17579 | its offset from the function start. */ | |
17580 | ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT"); | |
17581 | ASM_OUTPUT_LABEL (file, fname); | |
17582 | } | |
314fc5a9 ILT |
17583 | |
17584 | /* The .tbtab pseudo-op can only be used for the first eight | |
17585 | expressions, since it can't handle the possibly variable | |
17586 | length fields that follow. However, if you omit the optional | |
17587 | fields, the assembler outputs zeros for all optional fields | |
17588 | anyways, giving each variable length field is minimum length | |
17589 | (as defined in sys/debug.h). Thus we can not use the .tbtab | |
17590 | pseudo-op at all. */ | |
17591 | ||
17592 | /* An all-zero word flags the start of the tbtab, for debuggers | |
17593 | that have to find it by searching forward from the entry | |
17594 | point or from the current pc. */ | |
19d2d16f | 17595 | fputs ("\t.long 0\n", file); |
314fc5a9 ILT |
17596 | |
17597 | /* Tbtab format type. Use format type 0. */ | |
19d2d16f | 17598 | fputs ("\t.byte 0,", file); |
314fc5a9 | 17599 | |
5fc921c1 DE |
17600 | /* Language type. Unfortunately, there does not seem to be any |
17601 | official way to discover the language being compiled, so we | |
17602 | use language_string. | |
17603 | C is 0. Fortran is 1. Pascal is 2. Ada is 3. C++ is 9. | |
56438901 AM |
17604 | Java is 13. Objective-C is 14. Objective-C++ isn't assigned |
17605 | a number, so for now use 9. */ | |
5fc921c1 | 17606 | if (! strcmp (language_string, "GNU C")) |
314fc5a9 | 17607 | i = 0; |
6de9cd9a | 17608 | else if (! strcmp (language_string, "GNU F77") |
7f62878c | 17609 | || ! strcmp (language_string, "GNU Fortran")) |
314fc5a9 | 17610 | i = 1; |
8b83775b | 17611 | else if (! strcmp (language_string, "GNU Pascal")) |
314fc5a9 | 17612 | i = 2; |
5fc921c1 DE |
17613 | else if (! strcmp (language_string, "GNU Ada")) |
17614 | i = 3; | |
56438901 AM |
17615 | else if (! strcmp (language_string, "GNU C++") |
17616 | || ! strcmp (language_string, "GNU Objective-C++")) | |
314fc5a9 | 17617 | i = 9; |
9517ead8 AG |
17618 | else if (! strcmp (language_string, "GNU Java")) |
17619 | i = 13; | |
5fc921c1 DE |
17620 | else if (! strcmp (language_string, "GNU Objective-C")) |
17621 | i = 14; | |
314fc5a9 | 17622 | else |
37409796 | 17623 | gcc_unreachable (); |
314fc5a9 ILT |
17624 | fprintf (file, "%d,", i); |
17625 | ||
17626 | /* 8 single bit fields: global linkage (not set for C extern linkage, | |
17627 | apparently a PL/I convention?), out-of-line epilogue/prologue, offset | |
17628 | from start of procedure stored in tbtab, internal function, function | |
17629 | has controlled storage, function has no toc, function uses fp, | |
17630 | function logs/aborts fp operations. */ | |
17631 | /* Assume that fp operations are used if any fp reg must be saved. */ | |
6041bf2f DE |
17632 | fprintf (file, "%d,", |
17633 | (optional_tbtab << 5) | ((info->first_fp_reg_save != 64) << 1)); | |
314fc5a9 ILT |
17634 | |
17635 | /* 6 bitfields: function is interrupt handler, name present in | |
17636 | proc table, function calls alloca, on condition directives | |
17637 | (controls stack walks, 3 bits), saves condition reg, saves | |
17638 | link reg. */ | |
17639 | /* The `function calls alloca' bit seems to be set whenever reg 31 is | |
17640 | set up as a frame pointer, even when there is no alloca call. */ | |
17641 | fprintf (file, "%d,", | |
6041bf2f DE |
17642 | ((optional_tbtab << 6) |
17643 | | ((optional_tbtab & frame_pointer_needed) << 5) | |
17644 | | (info->cr_save_p << 1) | |
17645 | | (info->lr_save_p))); | |
314fc5a9 | 17646 | |
6041bf2f | 17647 | /* 3 bitfields: saves backchain, fixup code, number of fpr saved |
314fc5a9 ILT |
17648 | (6 bits). */ |
17649 | fprintf (file, "%d,", | |
4697a36c | 17650 | (info->push_p << 7) | (64 - info->first_fp_reg_save)); |
314fc5a9 ILT |
17651 | |
17652 | /* 2 bitfields: spare bits (2 bits), number of gpr saved (6 bits). */ | |
17653 | fprintf (file, "%d,", (32 - first_reg_to_save ())); | |
17654 | ||
6041bf2f DE |
17655 | if (optional_tbtab) |
17656 | { | |
17657 | /* Compute the parameter info from the function decl argument | |
17658 | list. */ | |
17659 | tree decl; | |
17660 | int next_parm_info_bit = 31; | |
314fc5a9 | 17661 | |
6041bf2f DE |
17662 | for (decl = DECL_ARGUMENTS (current_function_decl); |
17663 | decl; decl = TREE_CHAIN (decl)) | |
17664 | { | |
17665 | rtx parameter = DECL_INCOMING_RTL (decl); | |
17666 | enum machine_mode mode = GET_MODE (parameter); | |
314fc5a9 | 17667 | |
6041bf2f DE |
17668 | if (GET_CODE (parameter) == REG) |
17669 | { | |
ebb109ad | 17670 | if (SCALAR_FLOAT_MODE_P (mode)) |
6041bf2f DE |
17671 | { |
17672 | int bits; | |
17673 | ||
17674 | float_parms++; | |
17675 | ||
37409796 NS |
17676 | switch (mode) |
17677 | { | |
17678 | case SFmode: | |
e41b2a33 | 17679 | case SDmode: |
37409796 NS |
17680 | bits = 0x2; |
17681 | break; | |
17682 | ||
17683 | case DFmode: | |
7393f7f8 | 17684 | case DDmode: |
37409796 | 17685 | case TFmode: |
7393f7f8 | 17686 | case TDmode: |
37409796 NS |
17687 | bits = 0x3; |
17688 | break; | |
17689 | ||
17690 | default: | |
17691 | gcc_unreachable (); | |
17692 | } | |
6041bf2f DE |
17693 | |
17694 | /* If only one bit will fit, don't or in this entry. */ | |
17695 | if (next_parm_info_bit > 0) | |
17696 | parm_info |= (bits << (next_parm_info_bit - 1)); | |
17697 | next_parm_info_bit -= 2; | |
17698 | } | |
17699 | else | |
17700 | { | |
17701 | fixed_parms += ((GET_MODE_SIZE (mode) | |
17702 | + (UNITS_PER_WORD - 1)) | |
17703 | / UNITS_PER_WORD); | |
17704 | next_parm_info_bit -= 1; | |
17705 | } | |
17706 | } | |
17707 | } | |
17708 | } | |
314fc5a9 ILT |
17709 | |
17710 | /* Number of fixed point parameters. */ | |
17711 | /* This is actually the number of words of fixed point parameters; thus | |
17712 | an 8 byte struct counts as 2; and thus the maximum value is 8. */ | |
17713 | fprintf (file, "%d,", fixed_parms); | |
17714 | ||
17715 | /* 2 bitfields: number of floating point parameters (7 bits), parameters | |
17716 | all on stack. */ | |
17717 | /* This is actually the number of fp registers that hold parameters; | |
17718 | and thus the maximum value is 13. */ | |
17719 | /* Set parameters on stack bit if parameters are not in their original | |
17720 | registers, regardless of whether they are on the stack? Xlc | |
17721 | seems to set the bit when not optimizing. */ | |
17722 | fprintf (file, "%d\n", ((float_parms << 1) | (! optimize))); | |
17723 | ||
6041bf2f DE |
17724 | if (! optional_tbtab) |
17725 | return; | |
17726 | ||
314fc5a9 ILT |
17727 | /* Optional fields follow. Some are variable length. */ |
17728 | ||
17729 | /* Parameter types, left adjusted bit fields: 0 fixed, 10 single float, | |
17730 | 11 double float. */ | |
17731 | /* There is an entry for each parameter in a register, in the order that | |
17732 | they occur in the parameter list. Any intervening arguments on the | |
17733 | stack are ignored. If the list overflows a long (max possible length | |
17734 | 34 bits) then completely leave off all elements that don't fit. */ | |
17735 | /* Only emit this long if there was at least one parameter. */ | |
17736 | if (fixed_parms || float_parms) | |
17737 | fprintf (file, "\t.long %d\n", parm_info); | |
17738 | ||
17739 | /* Offset from start of code to tb table. */ | |
19d2d16f | 17740 | fputs ("\t.long ", file); |
314fc5a9 | 17741 | ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT"); |
85b776df AM |
17742 | if (TARGET_AIX) |
17743 | RS6000_OUTPUT_BASENAME (file, fname); | |
17744 | else | |
17745 | assemble_name (file, fname); | |
17746 | putc ('-', file); | |
17747 | rs6000_output_function_entry (file, fname); | |
19d2d16f | 17748 | putc ('\n', file); |
314fc5a9 ILT |
17749 | |
17750 | /* Interrupt handler mask. */ | |
17751 | /* Omit this long, since we never set the interrupt handler bit | |
17752 | above. */ | |
17753 | ||
17754 | /* Number of CTL (controlled storage) anchors. */ | |
17755 | /* Omit this long, since the has_ctl bit is never set above. */ | |
17756 | ||
17757 | /* Displacement into stack of each CTL anchor. */ | |
17758 | /* Omit this list of longs, because there are no CTL anchors. */ | |
17759 | ||
17760 | /* Length of function name. */ | |
69c75916 AM |
17761 | if (*fname == '*') |
17762 | ++fname; | |
296b8152 | 17763 | fprintf (file, "\t.short %d\n", (int) strlen (fname)); |
314fc5a9 ILT |
17764 | |
17765 | /* Function name. */ | |
17766 | assemble_string (fname, strlen (fname)); | |
17767 | ||
17768 | /* Register for alloca automatic storage; this is always reg 31. | |
17769 | Only emit this if the alloca bit was set above. */ | |
17770 | if (frame_pointer_needed) | |
19d2d16f | 17771 | fputs ("\t.byte 31\n", file); |
b1765bde DE |
17772 | |
17773 | fputs ("\t.align 2\n", file); | |
9b30bae2 | 17774 | } |
9878760c | 17775 | } |
17167fd8 | 17776 | \f |
a4f6c312 SS |
17777 | /* A C compound statement that outputs the assembler code for a thunk |
17778 | function, used to implement C++ virtual function calls with | |
17779 | multiple inheritance. The thunk acts as a wrapper around a virtual | |
17780 | function, adjusting the implicit object parameter before handing | |
17781 | control off to the real function. | |
17782 | ||
17783 | First, emit code to add the integer DELTA to the location that | |
17784 | contains the incoming first argument. Assume that this argument | |
17785 | contains a pointer, and is the one used to pass the `this' pointer | |
17786 | in C++. This is the incoming argument *before* the function | |
17787 | prologue, e.g. `%o0' on a sparc. The addition must preserve the | |
17788 | values of all other incoming arguments. | |
17167fd8 MM |
17789 | |
17790 | After the addition, emit code to jump to FUNCTION, which is a | |
a4f6c312 SS |
17791 | `FUNCTION_DECL'. This is a direct pure jump, not a call, and does |
17792 | not touch the return address. Hence returning from FUNCTION will | |
17793 | return to whoever called the current `thunk'. | |
17167fd8 | 17794 | |
a4f6c312 SS |
17795 | The effect must be as if FUNCTION had been called directly with the |
17796 | adjusted first argument. This macro is responsible for emitting | |
17797 | all of the code for a thunk function; output_function_prologue() | |
17798 | and output_function_epilogue() are not invoked. | |
17167fd8 | 17799 | |
a4f6c312 SS |
17800 | The THUNK_FNDECL is redundant. (DELTA and FUNCTION have already |
17801 | been extracted from it.) It might possibly be useful on some | |
17802 | targets, but probably not. | |
17167fd8 | 17803 | |
a4f6c312 SS |
17804 | If you do not define this macro, the target-independent code in the |
17805 | C++ frontend will generate a less efficient heavyweight thunk that | |
17806 | calls FUNCTION instead of jumping to it. The generic approach does | |
17807 | not support varargs. */ | |
17167fd8 | 17808 | |
3961e8fe | 17809 | static void |
f676971a EC |
17810 | rs6000_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED, |
17811 | HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset, | |
a2369ed3 | 17812 | tree function) |
17167fd8 | 17813 | { |
0a2aaacc | 17814 | rtx this_rtx, insn, funexp; |
17167fd8 | 17815 | |
5b71a4e7 | 17816 | reload_completed = 1; |
fe3ad572 | 17817 | epilogue_completed = 1; |
56a7189a | 17818 | |
5b71a4e7 | 17819 | /* Mark the end of the (empty) prologue. */ |
2e040219 | 17820 | emit_note (NOTE_INSN_PROLOGUE_END); |
17167fd8 | 17821 | |
5b71a4e7 DE |
17822 | /* Find the "this" pointer. If the function returns a structure, |
17823 | the structure return pointer is in r3. */ | |
61f71b34 | 17824 | if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function)) |
0a2aaacc | 17825 | this_rtx = gen_rtx_REG (Pmode, 4); |
56a7189a | 17826 | else |
0a2aaacc | 17827 | this_rtx = gen_rtx_REG (Pmode, 3); |
17167fd8 | 17828 | |
5b71a4e7 DE |
17829 | /* Apply the constant offset, if required. */ |
17830 | if (delta) | |
17831 | { | |
17832 | rtx delta_rtx = GEN_INT (delta); | |
17833 | emit_insn (TARGET_32BIT | |
0a2aaacc KG |
17834 | ? gen_addsi3 (this_rtx, this_rtx, delta_rtx) |
17835 | : gen_adddi3 (this_rtx, this_rtx, delta_rtx)); | |
17167fd8 MM |
17836 | } |
17837 | ||
5b71a4e7 DE |
17838 | /* Apply the offset from the vtable, if required. */ |
17839 | if (vcall_offset) | |
17167fd8 | 17840 | { |
5b71a4e7 DE |
17841 | rtx vcall_offset_rtx = GEN_INT (vcall_offset); |
17842 | rtx tmp = gen_rtx_REG (Pmode, 12); | |
17167fd8 | 17843 | |
0a2aaacc | 17844 | emit_move_insn (tmp, gen_rtx_MEM (Pmode, this_rtx)); |
eeff9307 JJ |
17845 | if (((unsigned HOST_WIDE_INT) vcall_offset) + 0x8000 >= 0x10000) |
17846 | { | |
17847 | emit_insn (TARGET_32BIT | |
17848 | ? gen_addsi3 (tmp, tmp, vcall_offset_rtx) | |
17849 | : gen_adddi3 (tmp, tmp, vcall_offset_rtx)); | |
17850 | emit_move_insn (tmp, gen_rtx_MEM (Pmode, tmp)); | |
17851 | } | |
17852 | else | |
17853 | { | |
17854 | rtx loc = gen_rtx_PLUS (Pmode, tmp, vcall_offset_rtx); | |
17855 | ||
17856 | emit_move_insn (tmp, gen_rtx_MEM (Pmode, loc)); | |
17857 | } | |
5b71a4e7 | 17858 | emit_insn (TARGET_32BIT |
0a2aaacc KG |
17859 | ? gen_addsi3 (this_rtx, this_rtx, tmp) |
17860 | : gen_adddi3 (this_rtx, this_rtx, tmp)); | |
17167fd8 MM |
17861 | } |
17862 | ||
5b71a4e7 DE |
17863 | /* Generate a tail call to the target function. */ |
17864 | if (!TREE_USED (function)) | |
17865 | { | |
17866 | assemble_external (function); | |
17867 | TREE_USED (function) = 1; | |
17868 | } | |
17869 | funexp = XEXP (DECL_RTL (function), 0); | |
5b71a4e7 | 17870 | funexp = gen_rtx_MEM (FUNCTION_MODE, funexp); |
ee890fe2 SS |
17871 | |
17872 | #if TARGET_MACHO | |
ab82a49f | 17873 | if (MACHOPIC_INDIRECT) |
5b71a4e7 | 17874 | funexp = machopic_indirect_call_target (funexp); |
ee890fe2 | 17875 | #endif |
5b71a4e7 DE |
17876 | |
17877 | /* gen_sibcall expects reload to convert scratch pseudo to LR so we must | |
992d08b1 | 17878 | generate sibcall RTL explicitly. */ |
5b71a4e7 DE |
17879 | insn = emit_call_insn ( |
17880 | gen_rtx_PARALLEL (VOIDmode, | |
17881 | gen_rtvec (4, | |
17882 | gen_rtx_CALL (VOIDmode, | |
17883 | funexp, const0_rtx), | |
17884 | gen_rtx_USE (VOIDmode, const0_rtx), | |
17885 | gen_rtx_USE (VOIDmode, | |
17886 | gen_rtx_REG (SImode, | |
1de43f85 | 17887 | LR_REGNO)), |
5b71a4e7 DE |
17888 | gen_rtx_RETURN (VOIDmode)))); |
17889 | SIBLING_CALL_P (insn) = 1; | |
17890 | emit_barrier (); | |
17891 | ||
17892 | /* Run just enough of rest_of_compilation to get the insns emitted. | |
17893 | There's not really enough bulk here to make other passes such as | |
17894 | instruction scheduling worth while. Note that use_thunk calls | |
17895 | assemble_start_function and assemble_end_function. */ | |
17896 | insn = get_insns (); | |
55e092c4 | 17897 | insn_locators_alloc (); |
5b71a4e7 DE |
17898 | shorten_branches (insn); |
17899 | final_start_function (insn, file, 1); | |
c9d691e9 | 17900 | final (insn, file, 1); |
5b71a4e7 | 17901 | final_end_function (); |
d7087dd2 | 17902 | free_after_compilation (cfun); |
5b71a4e7 DE |
17903 | |
17904 | reload_completed = 0; | |
fe3ad572 | 17905 | epilogue_completed = 0; |
9ebbca7d | 17906 | } |
9ebbca7d GK |
17907 | \f |
17908 | /* A quick summary of the various types of 'constant-pool tables' | |
17909 | under PowerPC: | |
17910 | ||
f676971a | 17911 | Target Flags Name One table per |
9ebbca7d GK |
17912 | AIX (none) AIX TOC object file |
17913 | AIX -mfull-toc AIX TOC object file | |
17914 | AIX -mminimal-toc AIX minimal TOC translation unit | |
17915 | SVR4/EABI (none) SVR4 SDATA object file | |
17916 | SVR4/EABI -fpic SVR4 pic object file | |
17917 | SVR4/EABI -fPIC SVR4 PIC translation unit | |
17918 | SVR4/EABI -mrelocatable EABI TOC function | |
17919 | SVR4/EABI -maix AIX TOC object file | |
f676971a | 17920 | SVR4/EABI -maix -mminimal-toc |
9ebbca7d GK |
17921 | AIX minimal TOC translation unit |
17922 | ||
17923 | Name Reg. Set by entries contains: | |
17924 | made by addrs? fp? sum? | |
17925 | ||
17926 | AIX TOC 2 crt0 as Y option option | |
17927 | AIX minimal TOC 30 prolog gcc Y Y option | |
17928 | SVR4 SDATA 13 crt0 gcc N Y N | |
17929 | SVR4 pic 30 prolog ld Y not yet N | |
17930 | SVR4 PIC 30 prolog gcc Y option option | |
17931 | EABI TOC 30 prolog gcc Y option option | |
17932 | ||
17933 | */ | |
17934 | ||
9ebbca7d GK |
17935 | /* Hash functions for the hash table. */ |
17936 | ||
17937 | static unsigned | |
a2369ed3 | 17938 | rs6000_hash_constant (rtx k) |
9ebbca7d | 17939 | { |
46b33600 RH |
17940 | enum rtx_code code = GET_CODE (k); |
17941 | enum machine_mode mode = GET_MODE (k); | |
17942 | unsigned result = (code << 3) ^ mode; | |
17943 | const char *format; | |
17944 | int flen, fidx; | |
f676971a | 17945 | |
46b33600 RH |
17946 | format = GET_RTX_FORMAT (code); |
17947 | flen = strlen (format); | |
17948 | fidx = 0; | |
9ebbca7d | 17949 | |
46b33600 RH |
17950 | switch (code) |
17951 | { | |
17952 | case LABEL_REF: | |
17953 | return result * 1231 + (unsigned) INSN_UID (XEXP (k, 0)); | |
17954 | ||
17955 | case CONST_DOUBLE: | |
17956 | if (mode != VOIDmode) | |
17957 | return real_hash (CONST_DOUBLE_REAL_VALUE (k)) * result; | |
17958 | flen = 2; | |
17959 | break; | |
17960 | ||
17961 | case CODE_LABEL: | |
17962 | fidx = 3; | |
17963 | break; | |
17964 | ||
17965 | default: | |
17966 | break; | |
17967 | } | |
9ebbca7d GK |
17968 | |
17969 | for (; fidx < flen; fidx++) | |
17970 | switch (format[fidx]) | |
17971 | { | |
17972 | case 's': | |
17973 | { | |
17974 | unsigned i, len; | |
17975 | const char *str = XSTR (k, fidx); | |
17976 | len = strlen (str); | |
17977 | result = result * 613 + len; | |
17978 | for (i = 0; i < len; i++) | |
17979 | result = result * 613 + (unsigned) str[i]; | |
17167fd8 MM |
17980 | break; |
17981 | } | |
9ebbca7d GK |
17982 | case 'u': |
17983 | case 'e': | |
17984 | result = result * 1231 + rs6000_hash_constant (XEXP (k, fidx)); | |
17985 | break; | |
17986 | case 'i': | |
17987 | case 'n': | |
17988 | result = result * 613 + (unsigned) XINT (k, fidx); | |
17989 | break; | |
17990 | case 'w': | |
17991 | if (sizeof (unsigned) >= sizeof (HOST_WIDE_INT)) | |
17992 | result = result * 613 + (unsigned) XWINT (k, fidx); | |
17993 | else | |
17994 | { | |
17995 | size_t i; | |
9390387d | 17996 | for (i = 0; i < sizeof (HOST_WIDE_INT) / sizeof (unsigned); i++) |
9ebbca7d GK |
17997 | result = result * 613 + (unsigned) (XWINT (k, fidx) |
17998 | >> CHAR_BIT * i); | |
17999 | } | |
18000 | break; | |
09501938 DE |
18001 | case '0': |
18002 | break; | |
9ebbca7d | 18003 | default: |
37409796 | 18004 | gcc_unreachable (); |
9ebbca7d | 18005 | } |
46b33600 | 18006 | |
9ebbca7d GK |
18007 | return result; |
18008 | } | |
18009 | ||
18010 | static unsigned | |
a2369ed3 | 18011 | toc_hash_function (const void *hash_entry) |
9ebbca7d | 18012 | { |
f676971a | 18013 | const struct toc_hash_struct *thc = |
a9098fd0 GK |
18014 | (const struct toc_hash_struct *) hash_entry; |
18015 | return rs6000_hash_constant (thc->key) ^ thc->key_mode; | |
9ebbca7d GK |
18016 | } |
18017 | ||
18018 | /* Compare H1 and H2 for equivalence. */ | |
18019 | ||
18020 | static int | |
a2369ed3 | 18021 | toc_hash_eq (const void *h1, const void *h2) |
9ebbca7d GK |
18022 | { |
18023 | rtx r1 = ((const struct toc_hash_struct *) h1)->key; | |
18024 | rtx r2 = ((const struct toc_hash_struct *) h2)->key; | |
18025 | ||
a9098fd0 GK |
18026 | if (((const struct toc_hash_struct *) h1)->key_mode |
18027 | != ((const struct toc_hash_struct *) h2)->key_mode) | |
18028 | return 0; | |
18029 | ||
5692c7bc | 18030 | return rtx_equal_p (r1, r2); |
9ebbca7d GK |
18031 | } |
18032 | ||
28e510bd MM |
18033 | /* These are the names given by the C++ front-end to vtables, and |
18034 | vtable-like objects. Ideally, this logic should not be here; | |
18035 | instead, there should be some programmatic way of inquiring as | |
18036 | to whether or not an object is a vtable. */ | |
18037 | ||
18038 | #define VTABLE_NAME_P(NAME) \ | |
9390387d | 18039 | (strncmp ("_vt.", name, strlen ("_vt.")) == 0 \ |
28e510bd MM |
18040 | || strncmp ("_ZTV", name, strlen ("_ZTV")) == 0 \ |
18041 | || strncmp ("_ZTT", name, strlen ("_ZTT")) == 0 \ | |
26be75db | 18042 | || strncmp ("_ZTI", name, strlen ("_ZTI")) == 0 \ |
f676971a | 18043 | || strncmp ("_ZTC", name, strlen ("_ZTC")) == 0) |
28e510bd | 18044 | |
ee06c6a5 DE |
18045 | #ifdef NO_DOLLAR_IN_LABEL |
18046 | /* Return a GGC-allocated character string translating dollar signs in | |
18047 | input NAME to underscores. Used by XCOFF ASM_OUTPUT_LABELREF. */ | |
18048 | ||
18049 | const char * | |
18050 | rs6000_xcoff_strip_dollar (const char *name) | |
18051 | { | |
18052 | char *strip, *p; | |
18053 | int len; | |
18054 | ||
18055 | p = strchr (name, '$'); | |
18056 | ||
18057 | if (p == 0 || p == name) | |
18058 | return name; | |
18059 | ||
18060 | len = strlen (name); | |
18061 | strip = (char *) alloca (len + 1); | |
18062 | strcpy (strip, name); | |
18063 | p = strchr (strip, '$'); | |
18064 | while (p) | |
18065 | { | |
18066 | *p = '_'; | |
18067 | p = strchr (p + 1, '$'); | |
18068 | } | |
18069 | ||
18070 | return ggc_alloc_string (strip, len); | |
18071 | } | |
18072 | #endif | |
18073 | ||
28e510bd | 18074 | void |
a2369ed3 | 18075 | rs6000_output_symbol_ref (FILE *file, rtx x) |
28e510bd MM |
18076 | { |
18077 | /* Currently C++ toc references to vtables can be emitted before it | |
18078 | is decided whether the vtable is public or private. If this is | |
18079 | the case, then the linker will eventually complain that there is | |
f676971a | 18080 | a reference to an unknown section. Thus, for vtables only, |
28e510bd MM |
18081 | we emit the TOC reference to reference the symbol and not the |
18082 | section. */ | |
18083 | const char *name = XSTR (x, 0); | |
54ee9799 | 18084 | |
f676971a | 18085 | if (VTABLE_NAME_P (name)) |
54ee9799 DE |
18086 | { |
18087 | RS6000_OUTPUT_BASENAME (file, name); | |
18088 | } | |
18089 | else | |
18090 | assemble_name (file, name); | |
28e510bd MM |
18091 | } |
18092 | ||
a4f6c312 SS |
18093 | /* Output a TOC entry. We derive the entry name from what is being |
18094 | written. */ | |
9878760c RK |
18095 | |
18096 | void | |
a2369ed3 | 18097 | output_toc (FILE *file, rtx x, int labelno, enum machine_mode mode) |
9878760c RK |
18098 | { |
18099 | char buf[256]; | |
3cce094d | 18100 | const char *name = buf; |
9878760c | 18101 | rtx base = x; |
16fdeb48 | 18102 | HOST_WIDE_INT offset = 0; |
9878760c | 18103 | |
37409796 | 18104 | gcc_assert (!TARGET_NO_TOC); |
4697a36c | 18105 | |
9ebbca7d GK |
18106 | /* When the linker won't eliminate them, don't output duplicate |
18107 | TOC entries (this happens on AIX if there is any kind of TOC, | |
17211ab5 GK |
18108 | and on SVR4 under -fPIC or -mrelocatable). Don't do this for |
18109 | CODE_LABELs. */ | |
18110 | if (TARGET_TOC && GET_CODE (x) != LABEL_REF) | |
9ebbca7d GK |
18111 | { |
18112 | struct toc_hash_struct *h; | |
18113 | void * * found; | |
f676971a | 18114 | |
17211ab5 | 18115 | /* Create toc_hash_table. This can't be done at OVERRIDE_OPTIONS |
c4ad648e | 18116 | time because GGC is not initialized at that point. */ |
17211ab5 | 18117 | if (toc_hash_table == NULL) |
f676971a | 18118 | toc_hash_table = htab_create_ggc (1021, toc_hash_function, |
17211ab5 GK |
18119 | toc_hash_eq, NULL); |
18120 | ||
5ead67f6 | 18121 | h = GGC_NEW (struct toc_hash_struct); |
9ebbca7d | 18122 | h->key = x; |
a9098fd0 | 18123 | h->key_mode = mode; |
9ebbca7d | 18124 | h->labelno = labelno; |
f676971a | 18125 | |
bbbbb16a | 18126 | found = htab_find_slot (toc_hash_table, h, INSERT); |
9ebbca7d GK |
18127 | if (*found == NULL) |
18128 | *found = h; | |
f676971a | 18129 | else /* This is indeed a duplicate. |
9ebbca7d GK |
18130 | Set this label equal to that label. */ |
18131 | { | |
18132 | fputs ("\t.set ", file); | |
18133 | ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC"); | |
18134 | fprintf (file, "%d,", labelno); | |
18135 | ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC"); | |
f676971a | 18136 | fprintf (file, "%d\n", ((*(const struct toc_hash_struct **) |
9ebbca7d GK |
18137 | found)->labelno)); |
18138 | return; | |
18139 | } | |
18140 | } | |
18141 | ||
18142 | /* If we're going to put a double constant in the TOC, make sure it's | |
18143 | aligned properly when strict alignment is on. */ | |
ff1720ed RK |
18144 | if (GET_CODE (x) == CONST_DOUBLE |
18145 | && STRICT_ALIGNMENT | |
a9098fd0 | 18146 | && GET_MODE_BITSIZE (mode) >= 64 |
ff1720ed RK |
18147 | && ! (TARGET_NO_FP_IN_TOC && ! TARGET_MINIMAL_TOC)) { |
18148 | ASM_OUTPUT_ALIGN (file, 3); | |
18149 | } | |
18150 | ||
4977bab6 | 18151 | (*targetm.asm_out.internal_label) (file, "LC", labelno); |
9878760c | 18152 | |
37c37a57 RK |
18153 | /* Handle FP constants specially. Note that if we have a minimal |
18154 | TOC, things we put here aren't actually in the TOC, so we can allow | |
18155 | FP constants. */ | |
00b79d54 BE |
18156 | if (GET_CODE (x) == CONST_DOUBLE && |
18157 | (GET_MODE (x) == TFmode || GET_MODE (x) == TDmode)) | |
fcce224d DE |
18158 | { |
18159 | REAL_VALUE_TYPE rv; | |
18160 | long k[4]; | |
18161 | ||
18162 | REAL_VALUE_FROM_CONST_DOUBLE (rv, x); | |
00b79d54 BE |
18163 | if (DECIMAL_FLOAT_MODE_P (GET_MODE (x))) |
18164 | REAL_VALUE_TO_TARGET_DECIMAL128 (rv, k); | |
18165 | else | |
18166 | REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv, k); | |
fcce224d DE |
18167 | |
18168 | if (TARGET_64BIT) | |
18169 | { | |
18170 | if (TARGET_MINIMAL_TOC) | |
18171 | fputs (DOUBLE_INT_ASM_OP, file); | |
18172 | else | |
18173 | fprintf (file, "\t.tc FT_%lx_%lx_%lx_%lx[TC],", | |
18174 | k[0] & 0xffffffff, k[1] & 0xffffffff, | |
18175 | k[2] & 0xffffffff, k[3] & 0xffffffff); | |
18176 | fprintf (file, "0x%lx%08lx,0x%lx%08lx\n", | |
18177 | k[0] & 0xffffffff, k[1] & 0xffffffff, | |
18178 | k[2] & 0xffffffff, k[3] & 0xffffffff); | |
18179 | return; | |
18180 | } | |
18181 | else | |
18182 | { | |
18183 | if (TARGET_MINIMAL_TOC) | |
18184 | fputs ("\t.long ", file); | |
18185 | else | |
18186 | fprintf (file, "\t.tc FT_%lx_%lx_%lx_%lx[TC],", | |
18187 | k[0] & 0xffffffff, k[1] & 0xffffffff, | |
18188 | k[2] & 0xffffffff, k[3] & 0xffffffff); | |
18189 | fprintf (file, "0x%lx,0x%lx,0x%lx,0x%lx\n", | |
18190 | k[0] & 0xffffffff, k[1] & 0xffffffff, | |
18191 | k[2] & 0xffffffff, k[3] & 0xffffffff); | |
18192 | return; | |
18193 | } | |
18194 | } | |
00b79d54 BE |
18195 | else if (GET_CODE (x) == CONST_DOUBLE && |
18196 | (GET_MODE (x) == DFmode || GET_MODE (x) == DDmode)) | |
9878760c | 18197 | { |
042259f2 DE |
18198 | REAL_VALUE_TYPE rv; |
18199 | long k[2]; | |
0adc764e | 18200 | |
042259f2 | 18201 | REAL_VALUE_FROM_CONST_DOUBLE (rv, x); |
00b79d54 BE |
18202 | |
18203 | if (DECIMAL_FLOAT_MODE_P (GET_MODE (x))) | |
18204 | REAL_VALUE_TO_TARGET_DECIMAL64 (rv, k); | |
18205 | else | |
18206 | REAL_VALUE_TO_TARGET_DOUBLE (rv, k); | |
31bfaa0b | 18207 | |
13ded975 DE |
18208 | if (TARGET_64BIT) |
18209 | { | |
18210 | if (TARGET_MINIMAL_TOC) | |
2bfcf297 | 18211 | fputs (DOUBLE_INT_ASM_OP, file); |
13ded975 | 18212 | else |
2f0552b6 AM |
18213 | fprintf (file, "\t.tc FD_%lx_%lx[TC],", |
18214 | k[0] & 0xffffffff, k[1] & 0xffffffff); | |
18215 | fprintf (file, "0x%lx%08lx\n", | |
18216 | k[0] & 0xffffffff, k[1] & 0xffffffff); | |
13ded975 DE |
18217 | return; |
18218 | } | |
1875cc88 | 18219 | else |
13ded975 DE |
18220 | { |
18221 | if (TARGET_MINIMAL_TOC) | |
2bfcf297 | 18222 | fputs ("\t.long ", file); |
13ded975 | 18223 | else |
2f0552b6 AM |
18224 | fprintf (file, "\t.tc FD_%lx_%lx[TC],", |
18225 | k[0] & 0xffffffff, k[1] & 0xffffffff); | |
18226 | fprintf (file, "0x%lx,0x%lx\n", | |
18227 | k[0] & 0xffffffff, k[1] & 0xffffffff); | |
13ded975 DE |
18228 | return; |
18229 | } | |
9878760c | 18230 | } |
00b79d54 BE |
18231 | else if (GET_CODE (x) == CONST_DOUBLE && |
18232 | (GET_MODE (x) == SFmode || GET_MODE (x) == SDmode)) | |
9878760c | 18233 | { |
042259f2 DE |
18234 | REAL_VALUE_TYPE rv; |
18235 | long l; | |
9878760c | 18236 | |
042259f2 | 18237 | REAL_VALUE_FROM_CONST_DOUBLE (rv, x); |
00b79d54 BE |
18238 | if (DECIMAL_FLOAT_MODE_P (GET_MODE (x))) |
18239 | REAL_VALUE_TO_TARGET_DECIMAL32 (rv, l); | |
18240 | else | |
18241 | REAL_VALUE_TO_TARGET_SINGLE (rv, l); | |
042259f2 | 18242 | |
31bfaa0b DE |
18243 | if (TARGET_64BIT) |
18244 | { | |
18245 | if (TARGET_MINIMAL_TOC) | |
2bfcf297 | 18246 | fputs (DOUBLE_INT_ASM_OP, file); |
31bfaa0b | 18247 | else |
2f0552b6 AM |
18248 | fprintf (file, "\t.tc FS_%lx[TC],", l & 0xffffffff); |
18249 | fprintf (file, "0x%lx00000000\n", l & 0xffffffff); | |
31bfaa0b DE |
18250 | return; |
18251 | } | |
042259f2 | 18252 | else |
31bfaa0b DE |
18253 | { |
18254 | if (TARGET_MINIMAL_TOC) | |
2bfcf297 | 18255 | fputs ("\t.long ", file); |
31bfaa0b | 18256 | else |
2f0552b6 AM |
18257 | fprintf (file, "\t.tc FS_%lx[TC],", l & 0xffffffff); |
18258 | fprintf (file, "0x%lx\n", l & 0xffffffff); | |
31bfaa0b DE |
18259 | return; |
18260 | } | |
042259f2 | 18261 | } |
f176e826 | 18262 | else if (GET_MODE (x) == VOIDmode |
a9098fd0 | 18263 | && (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE)) |
042259f2 | 18264 | { |
e2c953b6 | 18265 | unsigned HOST_WIDE_INT low; |
042259f2 DE |
18266 | HOST_WIDE_INT high; |
18267 | ||
18268 | if (GET_CODE (x) == CONST_DOUBLE) | |
18269 | { | |
18270 | low = CONST_DOUBLE_LOW (x); | |
18271 | high = CONST_DOUBLE_HIGH (x); | |
18272 | } | |
18273 | else | |
18274 | #if HOST_BITS_PER_WIDE_INT == 32 | |
18275 | { | |
18276 | low = INTVAL (x); | |
0858c623 | 18277 | high = (low & 0x80000000) ? ~0 : 0; |
042259f2 DE |
18278 | } |
18279 | #else | |
18280 | { | |
c4ad648e AM |
18281 | low = INTVAL (x) & 0xffffffff; |
18282 | high = (HOST_WIDE_INT) INTVAL (x) >> 32; | |
042259f2 DE |
18283 | } |
18284 | #endif | |
9878760c | 18285 | |
a9098fd0 GK |
18286 | /* TOC entries are always Pmode-sized, but since this |
18287 | is a bigendian machine then if we're putting smaller | |
18288 | integer constants in the TOC we have to pad them. | |
18289 | (This is still a win over putting the constants in | |
18290 | a separate constant pool, because then we'd have | |
02a4ec28 FS |
18291 | to have both a TOC entry _and_ the actual constant.) |
18292 | ||
18293 | For a 32-bit target, CONST_INT values are loaded and shifted | |
18294 | entirely within `low' and can be stored in one TOC entry. */ | |
18295 | ||
37409796 NS |
18296 | /* It would be easy to make this work, but it doesn't now. */ |
18297 | gcc_assert (!TARGET_64BIT || POINTER_SIZE >= GET_MODE_BITSIZE (mode)); | |
02a4ec28 FS |
18298 | |
18299 | if (POINTER_SIZE > GET_MODE_BITSIZE (mode)) | |
fb52d8de AM |
18300 | { |
18301 | #if HOST_BITS_PER_WIDE_INT == 32 | |
18302 | lshift_double (low, high, POINTER_SIZE - GET_MODE_BITSIZE (mode), | |
18303 | POINTER_SIZE, &low, &high, 0); | |
18304 | #else | |
18305 | low |= high << 32; | |
18306 | low <<= POINTER_SIZE - GET_MODE_BITSIZE (mode); | |
18307 | high = (HOST_WIDE_INT) low >> 32; | |
18308 | low &= 0xffffffff; | |
18309 | #endif | |
18310 | } | |
a9098fd0 | 18311 | |
13ded975 DE |
18312 | if (TARGET_64BIT) |
18313 | { | |
18314 | if (TARGET_MINIMAL_TOC) | |
2bfcf297 | 18315 | fputs (DOUBLE_INT_ASM_OP, file); |
13ded975 | 18316 | else |
2f0552b6 AM |
18317 | fprintf (file, "\t.tc ID_%lx_%lx[TC],", |
18318 | (long) high & 0xffffffff, (long) low & 0xffffffff); | |
18319 | fprintf (file, "0x%lx%08lx\n", | |
18320 | (long) high & 0xffffffff, (long) low & 0xffffffff); | |
13ded975 DE |
18321 | return; |
18322 | } | |
1875cc88 | 18323 | else |
13ded975 | 18324 | { |
02a4ec28 FS |
18325 | if (POINTER_SIZE < GET_MODE_BITSIZE (mode)) |
18326 | { | |
18327 | if (TARGET_MINIMAL_TOC) | |
2bfcf297 | 18328 | fputs ("\t.long ", file); |
02a4ec28 | 18329 | else |
2bfcf297 | 18330 | fprintf (file, "\t.tc ID_%lx_%lx[TC],", |
2f0552b6 AM |
18331 | (long) high & 0xffffffff, (long) low & 0xffffffff); |
18332 | fprintf (file, "0x%lx,0x%lx\n", | |
18333 | (long) high & 0xffffffff, (long) low & 0xffffffff); | |
02a4ec28 | 18334 | } |
13ded975 | 18335 | else |
02a4ec28 FS |
18336 | { |
18337 | if (TARGET_MINIMAL_TOC) | |
2bfcf297 | 18338 | fputs ("\t.long ", file); |
02a4ec28 | 18339 | else |
2f0552b6 AM |
18340 | fprintf (file, "\t.tc IS_%lx[TC],", (long) low & 0xffffffff); |
18341 | fprintf (file, "0x%lx\n", (long) low & 0xffffffff); | |
02a4ec28 | 18342 | } |
13ded975 DE |
18343 | return; |
18344 | } | |
9878760c RK |
18345 | } |
18346 | ||
18347 | if (GET_CODE (x) == CONST) | |
18348 | { | |
37409796 | 18349 | gcc_assert (GET_CODE (XEXP (x, 0)) == PLUS); |
2bfcf297 | 18350 | |
9878760c RK |
18351 | base = XEXP (XEXP (x, 0), 0); |
18352 | offset = INTVAL (XEXP (XEXP (x, 0), 1)); | |
18353 | } | |
f676971a | 18354 | |
37409796 NS |
18355 | switch (GET_CODE (base)) |
18356 | { | |
18357 | case SYMBOL_REF: | |
18358 | name = XSTR (base, 0); | |
18359 | break; | |
18360 | ||
18361 | case LABEL_REF: | |
18362 | ASM_GENERATE_INTERNAL_LABEL (buf, "L", | |
18363 | CODE_LABEL_NUMBER (XEXP (base, 0))); | |
18364 | break; | |
18365 | ||
18366 | case CODE_LABEL: | |
18367 | ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (base)); | |
18368 | break; | |
18369 | ||
18370 | default: | |
18371 | gcc_unreachable (); | |
18372 | } | |
9878760c | 18373 | |
1875cc88 | 18374 | if (TARGET_MINIMAL_TOC) |
2bfcf297 | 18375 | fputs (TARGET_32BIT ? "\t.long " : DOUBLE_INT_ASM_OP, file); |
1875cc88 JW |
18376 | else |
18377 | { | |
5773a50f DE |
18378 | fputs ("\t.tc ", file); |
18379 | RS6000_OUTPUT_BASENAME (file, name); | |
9878760c | 18380 | |
1875cc88 | 18381 | if (offset < 0) |
16fdeb48 | 18382 | fprintf (file, ".N" HOST_WIDE_INT_PRINT_UNSIGNED, - offset); |
1875cc88 | 18383 | else if (offset) |
16fdeb48 | 18384 | fprintf (file, ".P" HOST_WIDE_INT_PRINT_UNSIGNED, offset); |
9878760c | 18385 | |
19d2d16f | 18386 | fputs ("[TC],", file); |
1875cc88 | 18387 | } |
581bc4de MM |
18388 | |
18389 | /* Currently C++ toc references to vtables can be emitted before it | |
18390 | is decided whether the vtable is public or private. If this is | |
18391 | the case, then the linker will eventually complain that there is | |
18392 | a TOC reference to an unknown section. Thus, for vtables only, | |
18393 | we emit the TOC reference to reference the symbol and not the | |
18394 | section. */ | |
28e510bd | 18395 | if (VTABLE_NAME_P (name)) |
581bc4de | 18396 | { |
54ee9799 | 18397 | RS6000_OUTPUT_BASENAME (file, name); |
581bc4de | 18398 | if (offset < 0) |
16fdeb48 | 18399 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, offset); |
581bc4de | 18400 | else if (offset > 0) |
16fdeb48 | 18401 | fprintf (file, "+" HOST_WIDE_INT_PRINT_DEC, offset); |
581bc4de MM |
18402 | } |
18403 | else | |
18404 | output_addr_const (file, x); | |
19d2d16f | 18405 | putc ('\n', file); |
9878760c RK |
18406 | } |
18407 | \f | |
18408 | /* Output an assembler pseudo-op to write an ASCII string of N characters | |
18409 | starting at P to FILE. | |
18410 | ||
18411 | On the RS/6000, we have to do this using the .byte operation and | |
18412 | write out special characters outside the quoted string. | |
18413 | Also, the assembler is broken; very long strings are truncated, | |
a4f6c312 | 18414 | so we must artificially break them up early. */ |
9878760c RK |
18415 | |
18416 | void | |
a2369ed3 | 18417 | output_ascii (FILE *file, const char *p, int n) |
9878760c RK |
18418 | { |
18419 | char c; | |
18420 | int i, count_string; | |
d330fd93 KG |
18421 | const char *for_string = "\t.byte \""; |
18422 | const char *for_decimal = "\t.byte "; | |
18423 | const char *to_close = NULL; | |
9878760c RK |
18424 | |
18425 | count_string = 0; | |
18426 | for (i = 0; i < n; i++) | |
18427 | { | |
18428 | c = *p++; | |
18429 | if (c >= ' ' && c < 0177) | |
18430 | { | |
18431 | if (for_string) | |
18432 | fputs (for_string, file); | |
18433 | putc (c, file); | |
18434 | ||
18435 | /* Write two quotes to get one. */ | |
18436 | if (c == '"') | |
18437 | { | |
18438 | putc (c, file); | |
18439 | ++count_string; | |
18440 | } | |
18441 | ||
18442 | for_string = NULL; | |
18443 | for_decimal = "\"\n\t.byte "; | |
18444 | to_close = "\"\n"; | |
18445 | ++count_string; | |
18446 | ||
18447 | if (count_string >= 512) | |
18448 | { | |
18449 | fputs (to_close, file); | |
18450 | ||
18451 | for_string = "\t.byte \""; | |
18452 | for_decimal = "\t.byte "; | |
18453 | to_close = NULL; | |
18454 | count_string = 0; | |
18455 | } | |
18456 | } | |
18457 | else | |
18458 | { | |
18459 | if (for_decimal) | |
18460 | fputs (for_decimal, file); | |
18461 | fprintf (file, "%d", c); | |
18462 | ||
18463 | for_string = "\n\t.byte \""; | |
18464 | for_decimal = ", "; | |
18465 | to_close = "\n"; | |
18466 | count_string = 0; | |
18467 | } | |
18468 | } | |
18469 | ||
18470 | /* Now close the string if we have written one. Then end the line. */ | |
18471 | if (to_close) | |
9ebbca7d | 18472 | fputs (to_close, file); |
9878760c RK |
18473 | } |
18474 | \f | |
18475 | /* Generate a unique section name for FILENAME for a section type | |
18476 | represented by SECTION_DESC. Output goes into BUF. | |
18477 | ||
18478 | SECTION_DESC can be any string, as long as it is different for each | |
18479 | possible section type. | |
18480 | ||
18481 | We name the section in the same manner as xlc. The name begins with an | |
18482 | underscore followed by the filename (after stripping any leading directory | |
11e5fe42 RK |
18483 | names) with the last period replaced by the string SECTION_DESC. If |
18484 | FILENAME does not contain a period, SECTION_DESC is appended to the end of | |
18485 | the name. */ | |
9878760c RK |
18486 | |
18487 | void | |
f676971a | 18488 | rs6000_gen_section_name (char **buf, const char *filename, |
c4ad648e | 18489 | const char *section_desc) |
9878760c | 18490 | { |
9ebbca7d | 18491 | const char *q, *after_last_slash, *last_period = 0; |
9878760c RK |
18492 | char *p; |
18493 | int len; | |
9878760c RK |
18494 | |
18495 | after_last_slash = filename; | |
18496 | for (q = filename; *q; q++) | |
11e5fe42 RK |
18497 | { |
18498 | if (*q == '/') | |
18499 | after_last_slash = q + 1; | |
18500 | else if (*q == '.') | |
18501 | last_period = q; | |
18502 | } | |
9878760c | 18503 | |
11e5fe42 | 18504 | len = strlen (after_last_slash) + strlen (section_desc) + 2; |
6d9f628e | 18505 | *buf = (char *) xmalloc (len); |
9878760c RK |
18506 | |
18507 | p = *buf; | |
18508 | *p++ = '_'; | |
18509 | ||
18510 | for (q = after_last_slash; *q; q++) | |
18511 | { | |
11e5fe42 | 18512 | if (q == last_period) |
c4ad648e | 18513 | { |
9878760c RK |
18514 | strcpy (p, section_desc); |
18515 | p += strlen (section_desc); | |
e3981aab | 18516 | break; |
c4ad648e | 18517 | } |
9878760c | 18518 | |
e9a780ec | 18519 | else if (ISALNUM (*q)) |
c4ad648e | 18520 | *p++ = *q; |
9878760c RK |
18521 | } |
18522 | ||
11e5fe42 | 18523 | if (last_period == 0) |
9878760c RK |
18524 | strcpy (p, section_desc); |
18525 | else | |
18526 | *p = '\0'; | |
18527 | } | |
e165f3f0 | 18528 | \f |
a4f6c312 | 18529 | /* Emit profile function. */ |
411707f4 | 18530 | |
411707f4 | 18531 | void |
a2369ed3 | 18532 | output_profile_hook (int labelno ATTRIBUTE_UNUSED) |
411707f4 | 18533 | { |
858081ad AH |
18534 | /* Non-standard profiling for kernels, which just saves LR then calls |
18535 | _mcount without worrying about arg saves. The idea is to change | |
18536 | the function prologue as little as possible as it isn't easy to | |
18537 | account for arg save/restore code added just for _mcount. */ | |
ffcfcb5f AM |
18538 | if (TARGET_PROFILE_KERNEL) |
18539 | return; | |
18540 | ||
8480e480 CC |
18541 | if (DEFAULT_ABI == ABI_AIX) |
18542 | { | |
9739c90c JJ |
18543 | #ifndef NO_PROFILE_COUNTERS |
18544 | # define NO_PROFILE_COUNTERS 0 | |
18545 | #endif | |
f676971a | 18546 | if (NO_PROFILE_COUNTERS) |
bbbbb16a ILT |
18547 | emit_library_call (init_one_libfunc (RS6000_MCOUNT), |
18548 | LCT_NORMAL, VOIDmode, 0); | |
9739c90c JJ |
18549 | else |
18550 | { | |
18551 | char buf[30]; | |
18552 | const char *label_name; | |
18553 | rtx fun; | |
411707f4 | 18554 | |
9739c90c JJ |
18555 | ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno); |
18556 | label_name = (*targetm.strip_name_encoding) (ggc_strdup (buf)); | |
18557 | fun = gen_rtx_SYMBOL_REF (Pmode, label_name); | |
411707f4 | 18558 | |
bbbbb16a ILT |
18559 | emit_library_call (init_one_libfunc (RS6000_MCOUNT), |
18560 | LCT_NORMAL, VOIDmode, 1, fun, Pmode); | |
9739c90c | 18561 | } |
8480e480 | 18562 | } |
ee890fe2 SS |
18563 | else if (DEFAULT_ABI == ABI_DARWIN) |
18564 | { | |
d5fa86ba | 18565 | const char *mcount_name = RS6000_MCOUNT; |
1de43f85 | 18566 | int caller_addr_regno = LR_REGNO; |
ee890fe2 SS |
18567 | |
18568 | /* Be conservative and always set this, at least for now. */ | |
e3b5732b | 18569 | crtl->uses_pic_offset_table = 1; |
ee890fe2 SS |
18570 | |
18571 | #if TARGET_MACHO | |
18572 | /* For PIC code, set up a stub and collect the caller's address | |
18573 | from r0, which is where the prologue puts it. */ | |
11abc112 | 18574 | if (MACHOPIC_INDIRECT |
e3b5732b | 18575 | && crtl->uses_pic_offset_table) |
11abc112 | 18576 | caller_addr_regno = 0; |
ee890fe2 SS |
18577 | #endif |
18578 | emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mcount_name), | |
bbbbb16a | 18579 | LCT_NORMAL, VOIDmode, 1, |
ee890fe2 SS |
18580 | gen_rtx_REG (Pmode, caller_addr_regno), Pmode); |
18581 | } | |
411707f4 CC |
18582 | } |
18583 | ||
a4f6c312 | 18584 | /* Write function profiler code. */ |
e165f3f0 RK |
18585 | |
18586 | void | |
a2369ed3 | 18587 | output_function_profiler (FILE *file, int labelno) |
e165f3f0 | 18588 | { |
3daf36a4 | 18589 | char buf[100]; |
e165f3f0 | 18590 | |
38c1f2d7 | 18591 | switch (DEFAULT_ABI) |
3daf36a4 | 18592 | { |
38c1f2d7 | 18593 | default: |
37409796 | 18594 | gcc_unreachable (); |
38c1f2d7 MM |
18595 | |
18596 | case ABI_V4: | |
09eeeacb AM |
18597 | if (!TARGET_32BIT) |
18598 | { | |
d4ee4d25 | 18599 | warning (0, "no profiling of 64-bit code for this ABI"); |
09eeeacb AM |
18600 | return; |
18601 | } | |
ffcfcb5f | 18602 | ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno); |
38c1f2d7 | 18603 | fprintf (file, "\tmflr %s\n", reg_names[0]); |
71625f3d AM |
18604 | if (NO_PROFILE_COUNTERS) |
18605 | { | |
18606 | asm_fprintf (file, "\t{st|stw} %s,4(%s)\n", | |
18607 | reg_names[0], reg_names[1]); | |
18608 | } | |
18609 | else if (TARGET_SECURE_PLT && flag_pic) | |
18610 | { | |
18611 | asm_fprintf (file, "\tbcl 20,31,1f\n1:\n\t{st|stw} %s,4(%s)\n", | |
18612 | reg_names[0], reg_names[1]); | |
18613 | asm_fprintf (file, "\tmflr %s\n", reg_names[12]); | |
18614 | asm_fprintf (file, "\t{cau|addis} %s,%s,", | |
18615 | reg_names[12], reg_names[12]); | |
18616 | assemble_name (file, buf); | |
18617 | asm_fprintf (file, "-1b@ha\n\t{cal|la} %s,", reg_names[0]); | |
18618 | assemble_name (file, buf); | |
18619 | asm_fprintf (file, "-1b@l(%s)\n", reg_names[12]); | |
18620 | } | |
18621 | else if (flag_pic == 1) | |
38c1f2d7 | 18622 | { |
dfdfa60f | 18623 | fputs ("\tbl _GLOBAL_OFFSET_TABLE_@local-4\n", file); |
71625f3d AM |
18624 | asm_fprintf (file, "\t{st|stw} %s,4(%s)\n", |
18625 | reg_names[0], reg_names[1]); | |
17167fd8 | 18626 | asm_fprintf (file, "\tmflr %s\n", reg_names[12]); |
dfdfa60f | 18627 | asm_fprintf (file, "\t{l|lwz} %s,", reg_names[0]); |
38c1f2d7 | 18628 | assemble_name (file, buf); |
17167fd8 | 18629 | asm_fprintf (file, "@got(%s)\n", reg_names[12]); |
38c1f2d7 | 18630 | } |
9ebbca7d | 18631 | else if (flag_pic > 1) |
38c1f2d7 | 18632 | { |
71625f3d AM |
18633 | asm_fprintf (file, "\t{st|stw} %s,4(%s)\n", |
18634 | reg_names[0], reg_names[1]); | |
9ebbca7d | 18635 | /* Now, we need to get the address of the label. */ |
71625f3d | 18636 | fputs ("\tbcl 20,31,1f\n\t.long ", file); |
034e84c4 | 18637 | assemble_name (file, buf); |
9ebbca7d GK |
18638 | fputs ("-.\n1:", file); |
18639 | asm_fprintf (file, "\tmflr %s\n", reg_names[11]); | |
f676971a | 18640 | asm_fprintf (file, "\t{l|lwz} %s,0(%s)\n", |
9ebbca7d GK |
18641 | reg_names[0], reg_names[11]); |
18642 | asm_fprintf (file, "\t{cax|add} %s,%s,%s\n", | |
18643 | reg_names[0], reg_names[0], reg_names[11]); | |
38c1f2d7 | 18644 | } |
38c1f2d7 MM |
18645 | else |
18646 | { | |
17167fd8 | 18647 | asm_fprintf (file, "\t{liu|lis} %s,", reg_names[12]); |
38c1f2d7 | 18648 | assemble_name (file, buf); |
dfdfa60f | 18649 | fputs ("@ha\n", file); |
71625f3d AM |
18650 | asm_fprintf (file, "\t{st|stw} %s,4(%s)\n", |
18651 | reg_names[0], reg_names[1]); | |
a260abc9 | 18652 | asm_fprintf (file, "\t{cal|la} %s,", reg_names[0]); |
38c1f2d7 | 18653 | assemble_name (file, buf); |
17167fd8 | 18654 | asm_fprintf (file, "@l(%s)\n", reg_names[12]); |
38c1f2d7 MM |
18655 | } |
18656 | ||
50d440bc | 18657 | /* ABI_V4 saves the static chain reg with ASM_OUTPUT_REG_PUSH. */ |
3b6ce0af DE |
18658 | fprintf (file, "\tbl %s%s\n", |
18659 | RS6000_MCOUNT, flag_pic ? "@plt" : ""); | |
38c1f2d7 MM |
18660 | break; |
18661 | ||
18662 | case ABI_AIX: | |
ee890fe2 | 18663 | case ABI_DARWIN: |
ffcfcb5f AM |
18664 | if (!TARGET_PROFILE_KERNEL) |
18665 | { | |
a3c9585f | 18666 | /* Don't do anything, done in output_profile_hook (). */ |
ffcfcb5f AM |
18667 | } |
18668 | else | |
18669 | { | |
37409796 | 18670 | gcc_assert (!TARGET_32BIT); |
ffcfcb5f AM |
18671 | |
18672 | asm_fprintf (file, "\tmflr %s\n", reg_names[0]); | |
18673 | asm_fprintf (file, "\tstd %s,16(%s)\n", reg_names[0], reg_names[1]); | |
18674 | ||
6de9cd9a | 18675 | if (cfun->static_chain_decl != NULL) |
ffcfcb5f AM |
18676 | { |
18677 | asm_fprintf (file, "\tstd %s,24(%s)\n", | |
18678 | reg_names[STATIC_CHAIN_REGNUM], reg_names[1]); | |
18679 | fprintf (file, "\tbl %s\n", RS6000_MCOUNT); | |
18680 | asm_fprintf (file, "\tld %s,24(%s)\n", | |
18681 | reg_names[STATIC_CHAIN_REGNUM], reg_names[1]); | |
18682 | } | |
18683 | else | |
18684 | fprintf (file, "\tbl %s\n", RS6000_MCOUNT); | |
18685 | } | |
38c1f2d7 MM |
18686 | break; |
18687 | } | |
e165f3f0 | 18688 | } |
a251ffd0 | 18689 | |
b54cf83a | 18690 | \f |
44cd321e PS |
18691 | |
18692 | /* The following variable value is the last issued insn. */ | |
18693 | ||
18694 | static rtx last_scheduled_insn; | |
18695 | ||
18696 | /* The following variable helps to balance issuing of load and | |
18697 | store instructions */ | |
18698 | ||
18699 | static int load_store_pendulum; | |
18700 | ||
b54cf83a DE |
18701 | /* Power4 load update and store update instructions are cracked into a |
18702 | load or store and an integer insn which are executed in the same cycle. | |
18703 | Branches have their own dispatch slot which does not count against the | |
18704 | GCC issue rate, but it changes the program flow so there are no other | |
18705 | instructions to issue in this cycle. */ | |
18706 | ||
18707 | static int | |
f676971a EC |
18708 | rs6000_variable_issue (FILE *stream ATTRIBUTE_UNUSED, |
18709 | int verbose ATTRIBUTE_UNUSED, | |
a2369ed3 | 18710 | rtx insn, int more) |
b54cf83a | 18711 | { |
44cd321e | 18712 | last_scheduled_insn = insn; |
b54cf83a DE |
18713 | if (GET_CODE (PATTERN (insn)) == USE |
18714 | || GET_CODE (PATTERN (insn)) == CLOBBER) | |
44cd321e PS |
18715 | { |
18716 | cached_can_issue_more = more; | |
18717 | return cached_can_issue_more; | |
18718 | } | |
18719 | ||
18720 | if (insn_terminates_group_p (insn, current_group)) | |
18721 | { | |
18722 | cached_can_issue_more = 0; | |
18723 | return cached_can_issue_more; | |
18724 | } | |
b54cf83a | 18725 | |
d296e02e AP |
18726 | /* If no reservation, but reach here */ |
18727 | if (recog_memoized (insn) < 0) | |
18728 | return more; | |
18729 | ||
ec507f2d | 18730 | if (rs6000_sched_groups) |
b54cf83a | 18731 | { |
cbe26ab8 | 18732 | if (is_microcoded_insn (insn)) |
44cd321e | 18733 | cached_can_issue_more = 0; |
cbe26ab8 | 18734 | else if (is_cracked_insn (insn)) |
44cd321e PS |
18735 | cached_can_issue_more = more > 2 ? more - 2 : 0; |
18736 | else | |
18737 | cached_can_issue_more = more - 1; | |
18738 | ||
18739 | return cached_can_issue_more; | |
b54cf83a | 18740 | } |
165b263e | 18741 | |
d296e02e AP |
18742 | if (rs6000_cpu_attr == CPU_CELL && is_nonpipeline_insn (insn)) |
18743 | return 0; | |
18744 | ||
44cd321e PS |
18745 | cached_can_issue_more = more - 1; |
18746 | return cached_can_issue_more; | |
b54cf83a DE |
18747 | } |
18748 | ||
a251ffd0 TG |
18749 | /* Adjust the cost of a scheduling dependency. Return the new cost of |
18750 | a dependency LINK or INSN on DEP_INSN. COST is the current cost. */ | |
18751 | ||
c237e94a | 18752 | static int |
0a4f0294 | 18753 | rs6000_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost) |
a251ffd0 | 18754 | { |
44cd321e | 18755 | enum attr_type attr_type; |
a251ffd0 | 18756 | |
44cd321e | 18757 | if (! recog_memoized (insn)) |
a251ffd0 TG |
18758 | return 0; |
18759 | ||
44cd321e | 18760 | switch (REG_NOTE_KIND (link)) |
a251ffd0 | 18761 | { |
44cd321e PS |
18762 | case REG_DEP_TRUE: |
18763 | { | |
18764 | /* Data dependency; DEP_INSN writes a register that INSN reads | |
18765 | some cycles later. */ | |
18766 | ||
18767 | /* Separate a load from a narrower, dependent store. */ | |
18768 | if (rs6000_sched_groups | |
18769 | && GET_CODE (PATTERN (insn)) == SET | |
18770 | && GET_CODE (PATTERN (dep_insn)) == SET | |
18771 | && GET_CODE (XEXP (PATTERN (insn), 1)) == MEM | |
18772 | && GET_CODE (XEXP (PATTERN (dep_insn), 0)) == MEM | |
18773 | && (GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (insn), 1))) | |
18774 | > GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (dep_insn), 0))))) | |
18775 | return cost + 14; | |
18776 | ||
18777 | attr_type = get_attr_type (insn); | |
18778 | ||
18779 | switch (attr_type) | |
18780 | { | |
18781 | case TYPE_JMPREG: | |
18782 | /* Tell the first scheduling pass about the latency between | |
18783 | a mtctr and bctr (and mtlr and br/blr). The first | |
18784 | scheduling pass will not know about this latency since | |
18785 | the mtctr instruction, which has the latency associated | |
18786 | to it, will be generated by reload. */ | |
18787 | return TARGET_POWER ? 5 : 4; | |
18788 | case TYPE_BRANCH: | |
18789 | /* Leave some extra cycles between a compare and its | |
18790 | dependent branch, to inhibit expensive mispredicts. */ | |
18791 | if ((rs6000_cpu_attr == CPU_PPC603 | |
18792 | || rs6000_cpu_attr == CPU_PPC604 | |
18793 | || rs6000_cpu_attr == CPU_PPC604E | |
18794 | || rs6000_cpu_attr == CPU_PPC620 | |
18795 | || rs6000_cpu_attr == CPU_PPC630 | |
18796 | || rs6000_cpu_attr == CPU_PPC750 | |
18797 | || rs6000_cpu_attr == CPU_PPC7400 | |
18798 | || rs6000_cpu_attr == CPU_PPC7450 | |
18799 | || rs6000_cpu_attr == CPU_POWER4 | |
d296e02e AP |
18800 | || rs6000_cpu_attr == CPU_POWER5 |
18801 | || rs6000_cpu_attr == CPU_CELL) | |
44cd321e PS |
18802 | && recog_memoized (dep_insn) |
18803 | && (INSN_CODE (dep_insn) >= 0)) | |
982afe02 | 18804 | |
44cd321e PS |
18805 | switch (get_attr_type (dep_insn)) |
18806 | { | |
18807 | case TYPE_CMP: | |
18808 | case TYPE_COMPARE: | |
18809 | case TYPE_DELAYED_COMPARE: | |
18810 | case TYPE_IMUL_COMPARE: | |
18811 | case TYPE_LMUL_COMPARE: | |
18812 | case TYPE_FPCOMPARE: | |
18813 | case TYPE_CR_LOGICAL: | |
18814 | case TYPE_DELAYED_CR: | |
18815 | return cost + 2; | |
18816 | default: | |
18817 | break; | |
18818 | } | |
18819 | break; | |
18820 | ||
18821 | case TYPE_STORE: | |
18822 | case TYPE_STORE_U: | |
18823 | case TYPE_STORE_UX: | |
18824 | case TYPE_FPSTORE: | |
18825 | case TYPE_FPSTORE_U: | |
18826 | case TYPE_FPSTORE_UX: | |
18827 | if ((rs6000_cpu == PROCESSOR_POWER6) | |
18828 | && recog_memoized (dep_insn) | |
18829 | && (INSN_CODE (dep_insn) >= 0)) | |
18830 | { | |
18831 | ||
18832 | if (GET_CODE (PATTERN (insn)) != SET) | |
18833 | /* If this happens, we have to extend this to schedule | |
18834 | optimally. Return default for now. */ | |
18835 | return cost; | |
18836 | ||
18837 | /* Adjust the cost for the case where the value written | |
18838 | by a fixed point operation is used as the address | |
18839 | gen value on a store. */ | |
18840 | switch (get_attr_type (dep_insn)) | |
18841 | { | |
18842 | case TYPE_LOAD: | |
18843 | case TYPE_LOAD_U: | |
18844 | case TYPE_LOAD_UX: | |
18845 | case TYPE_CNTLZ: | |
18846 | { | |
18847 | if (! store_data_bypass_p (dep_insn, insn)) | |
18848 | return 4; | |
18849 | break; | |
18850 | } | |
18851 | case TYPE_LOAD_EXT: | |
18852 | case TYPE_LOAD_EXT_U: | |
18853 | case TYPE_LOAD_EXT_UX: | |
18854 | case TYPE_VAR_SHIFT_ROTATE: | |
18855 | case TYPE_VAR_DELAYED_COMPARE: | |
18856 | { | |
18857 | if (! store_data_bypass_p (dep_insn, insn)) | |
18858 | return 6; | |
18859 | break; | |
18860 | } | |
18861 | case TYPE_INTEGER: | |
18862 | case TYPE_COMPARE: | |
18863 | case TYPE_FAST_COMPARE: | |
18864 | case TYPE_EXTS: | |
18865 | case TYPE_SHIFT: | |
18866 | case TYPE_INSERT_WORD: | |
18867 | case TYPE_INSERT_DWORD: | |
18868 | case TYPE_FPLOAD_U: | |
18869 | case TYPE_FPLOAD_UX: | |
18870 | case TYPE_STORE_U: | |
18871 | case TYPE_STORE_UX: | |
18872 | case TYPE_FPSTORE_U: | |
18873 | case TYPE_FPSTORE_UX: | |
18874 | { | |
18875 | if (! store_data_bypass_p (dep_insn, insn)) | |
18876 | return 3; | |
18877 | break; | |
18878 | } | |
18879 | case TYPE_IMUL: | |
18880 | case TYPE_IMUL2: | |
18881 | case TYPE_IMUL3: | |
18882 | case TYPE_LMUL: | |
18883 | case TYPE_IMUL_COMPARE: | |
18884 | case TYPE_LMUL_COMPARE: | |
18885 | { | |
18886 | if (! store_data_bypass_p (dep_insn, insn)) | |
18887 | return 17; | |
18888 | break; | |
18889 | } | |
18890 | case TYPE_IDIV: | |
18891 | { | |
18892 | if (! store_data_bypass_p (dep_insn, insn)) | |
18893 | return 45; | |
18894 | break; | |
18895 | } | |
18896 | case TYPE_LDIV: | |
18897 | { | |
18898 | if (! store_data_bypass_p (dep_insn, insn)) | |
18899 | return 57; | |
18900 | break; | |
18901 | } | |
18902 | default: | |
18903 | break; | |
18904 | } | |
18905 | } | |
18906 | break; | |
18907 | ||
18908 | case TYPE_LOAD: | |
18909 | case TYPE_LOAD_U: | |
18910 | case TYPE_LOAD_UX: | |
18911 | case TYPE_LOAD_EXT: | |
18912 | case TYPE_LOAD_EXT_U: | |
18913 | case TYPE_LOAD_EXT_UX: | |
18914 | if ((rs6000_cpu == PROCESSOR_POWER6) | |
18915 | && recog_memoized (dep_insn) | |
18916 | && (INSN_CODE (dep_insn) >= 0)) | |
18917 | { | |
18918 | ||
18919 | /* Adjust the cost for the case where the value written | |
18920 | by a fixed point instruction is used within the address | |
18921 | gen portion of a subsequent load(u)(x) */ | |
18922 | switch (get_attr_type (dep_insn)) | |
18923 | { | |
18924 | case TYPE_LOAD: | |
18925 | case TYPE_LOAD_U: | |
18926 | case TYPE_LOAD_UX: | |
18927 | case TYPE_CNTLZ: | |
18928 | { | |
18929 | if (set_to_load_agen (dep_insn, insn)) | |
18930 | return 4; | |
18931 | break; | |
18932 | } | |
18933 | case TYPE_LOAD_EXT: | |
18934 | case TYPE_LOAD_EXT_U: | |
18935 | case TYPE_LOAD_EXT_UX: | |
18936 | case TYPE_VAR_SHIFT_ROTATE: | |
18937 | case TYPE_VAR_DELAYED_COMPARE: | |
18938 | { | |
18939 | if (set_to_load_agen (dep_insn, insn)) | |
18940 | return 6; | |
18941 | break; | |
18942 | } | |
18943 | case TYPE_INTEGER: | |
18944 | case TYPE_COMPARE: | |
18945 | case TYPE_FAST_COMPARE: | |
18946 | case TYPE_EXTS: | |
18947 | case TYPE_SHIFT: | |
18948 | case TYPE_INSERT_WORD: | |
18949 | case TYPE_INSERT_DWORD: | |
18950 | case TYPE_FPLOAD_U: | |
18951 | case TYPE_FPLOAD_UX: | |
18952 | case TYPE_STORE_U: | |
18953 | case TYPE_STORE_UX: | |
18954 | case TYPE_FPSTORE_U: | |
18955 | case TYPE_FPSTORE_UX: | |
18956 | { | |
18957 | if (set_to_load_agen (dep_insn, insn)) | |
18958 | return 3; | |
18959 | break; | |
18960 | } | |
18961 | case TYPE_IMUL: | |
18962 | case TYPE_IMUL2: | |
18963 | case TYPE_IMUL3: | |
18964 | case TYPE_LMUL: | |
18965 | case TYPE_IMUL_COMPARE: | |
18966 | case TYPE_LMUL_COMPARE: | |
18967 | { | |
18968 | if (set_to_load_agen (dep_insn, insn)) | |
18969 | return 17; | |
18970 | break; | |
18971 | } | |
18972 | case TYPE_IDIV: | |
18973 | { | |
18974 | if (set_to_load_agen (dep_insn, insn)) | |
18975 | return 45; | |
18976 | break; | |
18977 | } | |
18978 | case TYPE_LDIV: | |
18979 | { | |
18980 | if (set_to_load_agen (dep_insn, insn)) | |
18981 | return 57; | |
18982 | break; | |
18983 | } | |
18984 | default: | |
18985 | break; | |
18986 | } | |
18987 | } | |
18988 | break; | |
18989 | ||
18990 | case TYPE_FPLOAD: | |
18991 | if ((rs6000_cpu == PROCESSOR_POWER6) | |
18992 | && recog_memoized (dep_insn) | |
18993 | && (INSN_CODE (dep_insn) >= 0) | |
18994 | && (get_attr_type (dep_insn) == TYPE_MFFGPR)) | |
18995 | return 2; | |
18996 | ||
18997 | default: | |
18998 | break; | |
18999 | } | |
c9dbf840 | 19000 | |
a251ffd0 | 19001 | /* Fall out to return default cost. */ |
44cd321e PS |
19002 | } |
19003 | break; | |
19004 | ||
19005 | case REG_DEP_OUTPUT: | |
19006 | /* Output dependency; DEP_INSN writes a register that INSN writes some | |
19007 | cycles later. */ | |
19008 | if ((rs6000_cpu == PROCESSOR_POWER6) | |
19009 | && recog_memoized (dep_insn) | |
19010 | && (INSN_CODE (dep_insn) >= 0)) | |
19011 | { | |
19012 | attr_type = get_attr_type (insn); | |
19013 | ||
19014 | switch (attr_type) | |
19015 | { | |
19016 | case TYPE_FP: | |
19017 | if (get_attr_type (dep_insn) == TYPE_FP) | |
19018 | return 1; | |
19019 | break; | |
19020 | case TYPE_FPLOAD: | |
19021 | if (get_attr_type (dep_insn) == TYPE_MFFGPR) | |
19022 | return 2; | |
19023 | break; | |
19024 | default: | |
19025 | break; | |
19026 | } | |
19027 | } | |
19028 | case REG_DEP_ANTI: | |
19029 | /* Anti dependency; DEP_INSN reads a register that INSN writes some | |
19030 | cycles later. */ | |
19031 | return 0; | |
19032 | ||
19033 | default: | |
19034 | gcc_unreachable (); | |
a251ffd0 TG |
19035 | } |
19036 | ||
19037 | return cost; | |
19038 | } | |
b6c9286a | 19039 | |
cbe26ab8 | 19040 | /* The function returns a true if INSN is microcoded. |
839a4992 | 19041 | Return false otherwise. */ |
cbe26ab8 DN |
19042 | |
19043 | static bool | |
19044 | is_microcoded_insn (rtx insn) | |
19045 | { | |
19046 | if (!insn || !INSN_P (insn) | |
19047 | || GET_CODE (PATTERN (insn)) == USE | |
19048 | || GET_CODE (PATTERN (insn)) == CLOBBER) | |
19049 | return false; | |
19050 | ||
d296e02e AP |
19051 | if (rs6000_cpu_attr == CPU_CELL) |
19052 | return get_attr_cell_micro (insn) == CELL_MICRO_ALWAYS; | |
19053 | ||
ec507f2d | 19054 | if (rs6000_sched_groups) |
cbe26ab8 DN |
19055 | { |
19056 | enum attr_type type = get_attr_type (insn); | |
19057 | if (type == TYPE_LOAD_EXT_U | |
19058 | || type == TYPE_LOAD_EXT_UX | |
19059 | || type == TYPE_LOAD_UX | |
19060 | || type == TYPE_STORE_UX | |
19061 | || type == TYPE_MFCR) | |
c4ad648e | 19062 | return true; |
cbe26ab8 DN |
19063 | } |
19064 | ||
19065 | return false; | |
19066 | } | |
19067 | ||
cbe26ab8 DN |
19068 | /* The function returns true if INSN is cracked into 2 instructions |
19069 | by the processor (and therefore occupies 2 issue slots). */ | |
19070 | ||
19071 | static bool | |
19072 | is_cracked_insn (rtx insn) | |
19073 | { | |
19074 | if (!insn || !INSN_P (insn) | |
19075 | || GET_CODE (PATTERN (insn)) == USE | |
19076 | || GET_CODE (PATTERN (insn)) == CLOBBER) | |
19077 | return false; | |
19078 | ||
ec507f2d | 19079 | if (rs6000_sched_groups) |
cbe26ab8 DN |
19080 | { |
19081 | enum attr_type type = get_attr_type (insn); | |
19082 | if (type == TYPE_LOAD_U || type == TYPE_STORE_U | |
c4ad648e AM |
19083 | || type == TYPE_FPLOAD_U || type == TYPE_FPSTORE_U |
19084 | || type == TYPE_FPLOAD_UX || type == TYPE_FPSTORE_UX | |
19085 | || type == TYPE_LOAD_EXT || type == TYPE_DELAYED_CR | |
19086 | || type == TYPE_COMPARE || type == TYPE_DELAYED_COMPARE | |
19087 | || type == TYPE_IMUL_COMPARE || type == TYPE_LMUL_COMPARE | |
19088 | || type == TYPE_IDIV || type == TYPE_LDIV | |
19089 | || type == TYPE_INSERT_WORD) | |
19090 | return true; | |
cbe26ab8 DN |
19091 | } |
19092 | ||
19093 | return false; | |
19094 | } | |
19095 | ||
19096 | /* The function returns true if INSN can be issued only from | |
a3c9585f | 19097 | the branch slot. */ |
cbe26ab8 DN |
19098 | |
19099 | static bool | |
19100 | is_branch_slot_insn (rtx insn) | |
19101 | { | |
19102 | if (!insn || !INSN_P (insn) | |
19103 | || GET_CODE (PATTERN (insn)) == USE | |
19104 | || GET_CODE (PATTERN (insn)) == CLOBBER) | |
19105 | return false; | |
19106 | ||
ec507f2d | 19107 | if (rs6000_sched_groups) |
cbe26ab8 DN |
19108 | { |
19109 | enum attr_type type = get_attr_type (insn); | |
19110 | if (type == TYPE_BRANCH || type == TYPE_JMPREG) | |
f676971a | 19111 | return true; |
cbe26ab8 DN |
19112 | return false; |
19113 | } | |
19114 | ||
19115 | return false; | |
19116 | } | |
79ae11c4 | 19117 | |
44cd321e PS |
19118 | /* The function returns true if out_inst sets a value that is |
19119 | used in the address generation computation of in_insn */ | |
19120 | static bool | |
19121 | set_to_load_agen (rtx out_insn, rtx in_insn) | |
19122 | { | |
19123 | rtx out_set, in_set; | |
19124 | ||
19125 | /* For performance reasons, only handle the simple case where | |
19126 | both loads are a single_set. */ | |
19127 | out_set = single_set (out_insn); | |
19128 | if (out_set) | |
19129 | { | |
19130 | in_set = single_set (in_insn); | |
19131 | if (in_set) | |
19132 | return reg_mentioned_p (SET_DEST (out_set), SET_SRC (in_set)); | |
19133 | } | |
19134 | ||
19135 | return false; | |
19136 | } | |
19137 | ||
19138 | /* The function returns true if the target storage location of | |
19139 | out_insn is adjacent to the target storage location of in_insn */ | |
19140 | /* Return 1 if memory locations are adjacent. */ | |
19141 | ||
19142 | static bool | |
19143 | adjacent_mem_locations (rtx insn1, rtx insn2) | |
19144 | { | |
19145 | ||
e3a0e200 PB |
19146 | rtx a = get_store_dest (PATTERN (insn1)); |
19147 | rtx b = get_store_dest (PATTERN (insn2)); | |
19148 | ||
44cd321e PS |
19149 | if ((GET_CODE (XEXP (a, 0)) == REG |
19150 | || (GET_CODE (XEXP (a, 0)) == PLUS | |
19151 | && GET_CODE (XEXP (XEXP (a, 0), 1)) == CONST_INT)) | |
19152 | && (GET_CODE (XEXP (b, 0)) == REG | |
19153 | || (GET_CODE (XEXP (b, 0)) == PLUS | |
19154 | && GET_CODE (XEXP (XEXP (b, 0), 1)) == CONST_INT))) | |
19155 | { | |
f98e8938 | 19156 | HOST_WIDE_INT val0 = 0, val1 = 0, val_diff; |
44cd321e | 19157 | rtx reg0, reg1; |
44cd321e PS |
19158 | |
19159 | if (GET_CODE (XEXP (a, 0)) == PLUS) | |
19160 | { | |
19161 | reg0 = XEXP (XEXP (a, 0), 0); | |
19162 | val0 = INTVAL (XEXP (XEXP (a, 0), 1)); | |
19163 | } | |
19164 | else | |
19165 | reg0 = XEXP (a, 0); | |
19166 | ||
19167 | if (GET_CODE (XEXP (b, 0)) == PLUS) | |
19168 | { | |
19169 | reg1 = XEXP (XEXP (b, 0), 0); | |
19170 | val1 = INTVAL (XEXP (XEXP (b, 0), 1)); | |
19171 | } | |
19172 | else | |
19173 | reg1 = XEXP (b, 0); | |
19174 | ||
19175 | val_diff = val1 - val0; | |
19176 | ||
19177 | return ((REGNO (reg0) == REGNO (reg1)) | |
f98e8938 JJ |
19178 | && ((MEM_SIZE (a) && val_diff == INTVAL (MEM_SIZE (a))) |
19179 | || (MEM_SIZE (b) && val_diff == -INTVAL (MEM_SIZE (b))))); | |
44cd321e PS |
19180 | } |
19181 | ||
19182 | return false; | |
19183 | } | |
19184 | ||
a4f6c312 | 19185 | /* A C statement (sans semicolon) to update the integer scheduling |
79ae11c4 DN |
19186 | priority INSN_PRIORITY (INSN). Increase the priority to execute the |
19187 | INSN earlier, reduce the priority to execute INSN later. Do not | |
a4f6c312 SS |
19188 | define this macro if you do not need to adjust the scheduling |
19189 | priorities of insns. */ | |
bef84347 | 19190 | |
c237e94a | 19191 | static int |
a2369ed3 | 19192 | rs6000_adjust_priority (rtx insn ATTRIBUTE_UNUSED, int priority) |
bef84347 | 19193 | { |
a4f6c312 SS |
19194 | /* On machines (like the 750) which have asymmetric integer units, |
19195 | where one integer unit can do multiply and divides and the other | |
19196 | can't, reduce the priority of multiply/divide so it is scheduled | |
19197 | before other integer operations. */ | |
bef84347 VM |
19198 | |
19199 | #if 0 | |
2c3c49de | 19200 | if (! INSN_P (insn)) |
bef84347 VM |
19201 | return priority; |
19202 | ||
19203 | if (GET_CODE (PATTERN (insn)) == USE) | |
19204 | return priority; | |
19205 | ||
19206 | switch (rs6000_cpu_attr) { | |
19207 | case CPU_PPC750: | |
19208 | switch (get_attr_type (insn)) | |
19209 | { | |
19210 | default: | |
19211 | break; | |
19212 | ||
19213 | case TYPE_IMUL: | |
19214 | case TYPE_IDIV: | |
3cb999d8 DE |
19215 | fprintf (stderr, "priority was %#x (%d) before adjustment\n", |
19216 | priority, priority); | |
bef84347 VM |
19217 | if (priority >= 0 && priority < 0x01000000) |
19218 | priority >>= 3; | |
19219 | break; | |
19220 | } | |
19221 | } | |
19222 | #endif | |
19223 | ||
44cd321e | 19224 | if (insn_must_be_first_in_group (insn) |
79ae11c4 | 19225 | && reload_completed |
f676971a | 19226 | && current_sched_info->sched_max_insns_priority |
79ae11c4 DN |
19227 | && rs6000_sched_restricted_insns_priority) |
19228 | { | |
19229 | ||
c4ad648e AM |
19230 | /* Prioritize insns that can be dispatched only in the first |
19231 | dispatch slot. */ | |
79ae11c4 | 19232 | if (rs6000_sched_restricted_insns_priority == 1) |
f676971a EC |
19233 | /* Attach highest priority to insn. This means that in |
19234 | haifa-sched.c:ready_sort(), dispatch-slot restriction considerations | |
79ae11c4 | 19235 | precede 'priority' (critical path) considerations. */ |
f676971a | 19236 | return current_sched_info->sched_max_insns_priority; |
79ae11c4 | 19237 | else if (rs6000_sched_restricted_insns_priority == 2) |
f676971a | 19238 | /* Increase priority of insn by a minimal amount. This means that in |
c4ad648e AM |
19239 | haifa-sched.c:ready_sort(), only 'priority' (critical path) |
19240 | considerations precede dispatch-slot restriction considerations. */ | |
f676971a EC |
19241 | return (priority + 1); |
19242 | } | |
79ae11c4 | 19243 | |
44cd321e PS |
19244 | if (rs6000_cpu == PROCESSOR_POWER6 |
19245 | && ((load_store_pendulum == -2 && is_load_insn (insn)) | |
19246 | || (load_store_pendulum == 2 && is_store_insn (insn)))) | |
19247 | /* Attach highest priority to insn if the scheduler has just issued two | |
19248 | stores and this instruction is a load, or two loads and this instruction | |
19249 | is a store. Power6 wants loads and stores scheduled alternately | |
19250 | when possible */ | |
19251 | return current_sched_info->sched_max_insns_priority; | |
19252 | ||
bef84347 VM |
19253 | return priority; |
19254 | } | |
19255 | ||
d296e02e AP |
19256 | /* Return true if the instruction is nonpipelined on the Cell. */ |
19257 | static bool | |
19258 | is_nonpipeline_insn (rtx insn) | |
19259 | { | |
19260 | enum attr_type type; | |
19261 | if (!insn || !INSN_P (insn) | |
19262 | || GET_CODE (PATTERN (insn)) == USE | |
19263 | || GET_CODE (PATTERN (insn)) == CLOBBER) | |
19264 | return false; | |
19265 | ||
19266 | type = get_attr_type (insn); | |
19267 | if (type == TYPE_IMUL | |
19268 | || type == TYPE_IMUL2 | |
19269 | || type == TYPE_IMUL3 | |
19270 | || type == TYPE_LMUL | |
19271 | || type == TYPE_IDIV | |
19272 | || type == TYPE_LDIV | |
19273 | || type == TYPE_SDIV | |
19274 | || type == TYPE_DDIV | |
19275 | || type == TYPE_SSQRT | |
19276 | || type == TYPE_DSQRT | |
19277 | || type == TYPE_MFCR | |
19278 | || type == TYPE_MFCRF | |
19279 | || type == TYPE_MFJMPR) | |
19280 | { | |
19281 | return true; | |
19282 | } | |
19283 | return false; | |
19284 | } | |
19285 | ||
19286 | ||
a4f6c312 SS |
19287 | /* Return how many instructions the machine can issue per cycle. */ |
19288 | ||
c237e94a | 19289 | static int |
863d938c | 19290 | rs6000_issue_rate (void) |
b6c9286a | 19291 | { |
3317bab1 DE |
19292 | /* Use issue rate of 1 for first scheduling pass to decrease degradation. */ |
19293 | if (!reload_completed) | |
19294 | return 1; | |
19295 | ||
b6c9286a | 19296 | switch (rs6000_cpu_attr) { |
3cb999d8 DE |
19297 | case CPU_RIOS1: /* ? */ |
19298 | case CPU_RS64A: | |
19299 | case CPU_PPC601: /* ? */ | |
ed947a96 | 19300 | case CPU_PPC7450: |
3cb999d8 | 19301 | return 3; |
b54cf83a | 19302 | case CPU_PPC440: |
b6c9286a | 19303 | case CPU_PPC603: |
bef84347 | 19304 | case CPU_PPC750: |
ed947a96 | 19305 | case CPU_PPC7400: |
be12c2b0 | 19306 | case CPU_PPC8540: |
d296e02e | 19307 | case CPU_CELL: |
fa41c305 EW |
19308 | case CPU_PPCE300C2: |
19309 | case CPU_PPCE300C3: | |
edae5fe3 | 19310 | case CPU_PPCE500MC: |
f676971a | 19311 | return 2; |
3cb999d8 | 19312 | case CPU_RIOS2: |
b6c9286a | 19313 | case CPU_PPC604: |
19684119 | 19314 | case CPU_PPC604E: |
b6c9286a | 19315 | case CPU_PPC620: |
3cb999d8 | 19316 | case CPU_PPC630: |
b6c9286a | 19317 | return 4; |
cbe26ab8 | 19318 | case CPU_POWER4: |
ec507f2d | 19319 | case CPU_POWER5: |
44cd321e | 19320 | case CPU_POWER6: |
cbe26ab8 | 19321 | return 5; |
b6c9286a MM |
19322 | default: |
19323 | return 1; | |
19324 | } | |
19325 | } | |
19326 | ||
be12c2b0 VM |
19327 | /* Return how many instructions to look ahead for better insn |
19328 | scheduling. */ | |
19329 | ||
19330 | static int | |
863d938c | 19331 | rs6000_use_sched_lookahead (void) |
be12c2b0 VM |
19332 | { |
19333 | if (rs6000_cpu_attr == CPU_PPC8540) | |
19334 | return 4; | |
d296e02e AP |
19335 | if (rs6000_cpu_attr == CPU_CELL) |
19336 | return (reload_completed ? 8 : 0); | |
be12c2b0 VM |
19337 | return 0; |
19338 | } | |
19339 | ||
d296e02e AP |
19340 | /* We are choosing insn from the ready queue. Return nonzero if INSN can be chosen. */ |
19341 | static int | |
19342 | rs6000_use_sched_lookahead_guard (rtx insn) | |
19343 | { | |
19344 | if (rs6000_cpu_attr != CPU_CELL) | |
19345 | return 1; | |
19346 | ||
19347 | if (insn == NULL_RTX || !INSN_P (insn)) | |
19348 | abort (); | |
982afe02 | 19349 | |
d296e02e AP |
19350 | if (!reload_completed |
19351 | || is_nonpipeline_insn (insn) | |
19352 | || is_microcoded_insn (insn)) | |
19353 | return 0; | |
19354 | ||
19355 | return 1; | |
19356 | } | |
19357 | ||
569fa502 DN |
19358 | /* Determine is PAT refers to memory. */ |
19359 | ||
19360 | static bool | |
19361 | is_mem_ref (rtx pat) | |
19362 | { | |
19363 | const char * fmt; | |
19364 | int i, j; | |
19365 | bool ret = false; | |
19366 | ||
1de59bbd DE |
19367 | /* stack_tie does not produce any real memory traffic. */ |
19368 | if (GET_CODE (pat) == UNSPEC | |
19369 | && XINT (pat, 1) == UNSPEC_TIE) | |
19370 | return false; | |
19371 | ||
569fa502 DN |
19372 | if (GET_CODE (pat) == MEM) |
19373 | return true; | |
19374 | ||
19375 | /* Recursively process the pattern. */ | |
19376 | fmt = GET_RTX_FORMAT (GET_CODE (pat)); | |
19377 | ||
19378 | for (i = GET_RTX_LENGTH (GET_CODE (pat)) - 1; i >= 0 && !ret; i--) | |
19379 | { | |
19380 | if (fmt[i] == 'e') | |
19381 | ret |= is_mem_ref (XEXP (pat, i)); | |
19382 | else if (fmt[i] == 'E') | |
19383 | for (j = XVECLEN (pat, i) - 1; j >= 0; j--) | |
19384 | ret |= is_mem_ref (XVECEXP (pat, i, j)); | |
19385 | } | |
19386 | ||
19387 | return ret; | |
19388 | } | |
19389 | ||
19390 | /* Determine if PAT is a PATTERN of a load insn. */ | |
f676971a | 19391 | |
569fa502 DN |
19392 | static bool |
19393 | is_load_insn1 (rtx pat) | |
19394 | { | |
19395 | if (!pat || pat == NULL_RTX) | |
19396 | return false; | |
19397 | ||
19398 | if (GET_CODE (pat) == SET) | |
19399 | return is_mem_ref (SET_SRC (pat)); | |
19400 | ||
19401 | if (GET_CODE (pat) == PARALLEL) | |
19402 | { | |
19403 | int i; | |
19404 | ||
19405 | for (i = 0; i < XVECLEN (pat, 0); i++) | |
19406 | if (is_load_insn1 (XVECEXP (pat, 0, i))) | |
19407 | return true; | |
19408 | } | |
19409 | ||
19410 | return false; | |
19411 | } | |
19412 | ||
19413 | /* Determine if INSN loads from memory. */ | |
19414 | ||
19415 | static bool | |
19416 | is_load_insn (rtx insn) | |
19417 | { | |
19418 | if (!insn || !INSN_P (insn)) | |
19419 | return false; | |
19420 | ||
19421 | if (GET_CODE (insn) == CALL_INSN) | |
19422 | return false; | |
19423 | ||
19424 | return is_load_insn1 (PATTERN (insn)); | |
19425 | } | |
19426 | ||
19427 | /* Determine if PAT is a PATTERN of a store insn. */ | |
19428 | ||
19429 | static bool | |
19430 | is_store_insn1 (rtx pat) | |
19431 | { | |
19432 | if (!pat || pat == NULL_RTX) | |
19433 | return false; | |
19434 | ||
19435 | if (GET_CODE (pat) == SET) | |
19436 | return is_mem_ref (SET_DEST (pat)); | |
19437 | ||
19438 | if (GET_CODE (pat) == PARALLEL) | |
19439 | { | |
19440 | int i; | |
19441 | ||
19442 | for (i = 0; i < XVECLEN (pat, 0); i++) | |
19443 | if (is_store_insn1 (XVECEXP (pat, 0, i))) | |
19444 | return true; | |
19445 | } | |
19446 | ||
19447 | return false; | |
19448 | } | |
19449 | ||
19450 | /* Determine if INSN stores to memory. */ | |
19451 | ||
19452 | static bool | |
19453 | is_store_insn (rtx insn) | |
19454 | { | |
19455 | if (!insn || !INSN_P (insn)) | |
19456 | return false; | |
19457 | ||
19458 | return is_store_insn1 (PATTERN (insn)); | |
19459 | } | |
19460 | ||
e3a0e200 PB |
19461 | /* Return the dest of a store insn. */ |
19462 | ||
19463 | static rtx | |
19464 | get_store_dest (rtx pat) | |
19465 | { | |
19466 | gcc_assert (is_store_insn1 (pat)); | |
19467 | ||
19468 | if (GET_CODE (pat) == SET) | |
19469 | return SET_DEST (pat); | |
19470 | else if (GET_CODE (pat) == PARALLEL) | |
19471 | { | |
19472 | int i; | |
19473 | ||
19474 | for (i = 0; i < XVECLEN (pat, 0); i++) | |
19475 | { | |
19476 | rtx inner_pat = XVECEXP (pat, 0, i); | |
19477 | if (GET_CODE (inner_pat) == SET | |
19478 | && is_mem_ref (SET_DEST (inner_pat))) | |
19479 | return inner_pat; | |
19480 | } | |
19481 | } | |
19482 | /* We shouldn't get here, because we should have either a simple | |
19483 | store insn or a store with update which are covered above. */ | |
19484 | gcc_unreachable(); | |
19485 | } | |
19486 | ||
569fa502 DN |
19487 | /* Returns whether the dependence between INSN and NEXT is considered |
19488 | costly by the given target. */ | |
19489 | ||
19490 | static bool | |
b198261f | 19491 | rs6000_is_costly_dependence (dep_t dep, int cost, int distance) |
f676971a | 19492 | { |
b198261f MK |
19493 | rtx insn; |
19494 | rtx next; | |
19495 | ||
aabcd309 | 19496 | /* If the flag is not enabled - no dependence is considered costly; |
f676971a | 19497 | allow all dependent insns in the same group. |
569fa502 DN |
19498 | This is the most aggressive option. */ |
19499 | if (rs6000_sched_costly_dep == no_dep_costly) | |
19500 | return false; | |
19501 | ||
f676971a | 19502 | /* If the flag is set to 1 - a dependence is always considered costly; |
569fa502 DN |
19503 | do not allow dependent instructions in the same group. |
19504 | This is the most conservative option. */ | |
19505 | if (rs6000_sched_costly_dep == all_deps_costly) | |
f676971a | 19506 | return true; |
569fa502 | 19507 | |
b198261f MK |
19508 | insn = DEP_PRO (dep); |
19509 | next = DEP_CON (dep); | |
19510 | ||
f676971a EC |
19511 | if (rs6000_sched_costly_dep == store_to_load_dep_costly |
19512 | && is_load_insn (next) | |
569fa502 DN |
19513 | && is_store_insn (insn)) |
19514 | /* Prevent load after store in the same group. */ | |
19515 | return true; | |
19516 | ||
19517 | if (rs6000_sched_costly_dep == true_store_to_load_dep_costly | |
f676971a | 19518 | && is_load_insn (next) |
569fa502 | 19519 | && is_store_insn (insn) |
e2f6ff94 | 19520 | && DEP_TYPE (dep) == REG_DEP_TRUE) |
c4ad648e AM |
19521 | /* Prevent load after store in the same group if it is a true |
19522 | dependence. */ | |
569fa502 | 19523 | return true; |
f676971a EC |
19524 | |
19525 | /* The flag is set to X; dependences with latency >= X are considered costly, | |
569fa502 DN |
19526 | and will not be scheduled in the same group. */ |
19527 | if (rs6000_sched_costly_dep <= max_dep_latency | |
19528 | && ((cost - distance) >= (int)rs6000_sched_costly_dep)) | |
19529 | return true; | |
19530 | ||
19531 | return false; | |
19532 | } | |
19533 | ||
f676971a | 19534 | /* Return the next insn after INSN that is found before TAIL is reached, |
cbe26ab8 DN |
19535 | skipping any "non-active" insns - insns that will not actually occupy |
19536 | an issue slot. Return NULL_RTX if such an insn is not found. */ | |
19537 | ||
19538 | static rtx | |
19539 | get_next_active_insn (rtx insn, rtx tail) | |
19540 | { | |
f489aff8 | 19541 | if (insn == NULL_RTX || insn == tail) |
cbe26ab8 DN |
19542 | return NULL_RTX; |
19543 | ||
f489aff8 | 19544 | while (1) |
cbe26ab8 | 19545 | { |
f489aff8 AM |
19546 | insn = NEXT_INSN (insn); |
19547 | if (insn == NULL_RTX || insn == tail) | |
19548 | return NULL_RTX; | |
cbe26ab8 | 19549 | |
f489aff8 AM |
19550 | if (CALL_P (insn) |
19551 | || JUMP_P (insn) | |
19552 | || (NONJUMP_INSN_P (insn) | |
19553 | && GET_CODE (PATTERN (insn)) != USE | |
19554 | && GET_CODE (PATTERN (insn)) != CLOBBER | |
309ebcd0 | 19555 | && INSN_CODE (insn) != CODE_FOR_stack_tie)) |
f489aff8 AM |
19556 | break; |
19557 | } | |
19558 | return insn; | |
cbe26ab8 DN |
19559 | } |
19560 | ||
44cd321e PS |
19561 | /* We are about to begin issuing insns for this clock cycle. */ |
19562 | ||
19563 | static int | |
19564 | rs6000_sched_reorder (FILE *dump ATTRIBUTE_UNUSED, int sched_verbose, | |
19565 | rtx *ready ATTRIBUTE_UNUSED, | |
19566 | int *pn_ready ATTRIBUTE_UNUSED, | |
19567 | int clock_var ATTRIBUTE_UNUSED) | |
19568 | { | |
d296e02e AP |
19569 | int n_ready = *pn_ready; |
19570 | ||
44cd321e PS |
19571 | if (sched_verbose) |
19572 | fprintf (dump, "// rs6000_sched_reorder :\n"); | |
19573 | ||
d296e02e AP |
19574 | /* Reorder the ready list, if the second to last ready insn |
19575 | is a nonepipeline insn. */ | |
19576 | if (rs6000_cpu_attr == CPU_CELL && n_ready > 1) | |
19577 | { | |
19578 | if (is_nonpipeline_insn (ready[n_ready - 1]) | |
19579 | && (recog_memoized (ready[n_ready - 2]) > 0)) | |
19580 | /* Simply swap first two insns. */ | |
19581 | { | |
19582 | rtx tmp = ready[n_ready - 1]; | |
19583 | ready[n_ready - 1] = ready[n_ready - 2]; | |
19584 | ready[n_ready - 2] = tmp; | |
19585 | } | |
19586 | } | |
19587 | ||
44cd321e PS |
19588 | if (rs6000_cpu == PROCESSOR_POWER6) |
19589 | load_store_pendulum = 0; | |
19590 | ||
19591 | return rs6000_issue_rate (); | |
19592 | } | |
19593 | ||
19594 | /* Like rs6000_sched_reorder, but called after issuing each insn. */ | |
19595 | ||
19596 | static int | |
19597 | rs6000_sched_reorder2 (FILE *dump, int sched_verbose, rtx *ready, | |
19598 | int *pn_ready, int clock_var ATTRIBUTE_UNUSED) | |
19599 | { | |
19600 | if (sched_verbose) | |
19601 | fprintf (dump, "// rs6000_sched_reorder2 :\n"); | |
19602 | ||
19603 | /* For Power6, we need to handle some special cases to try and keep the | |
19604 | store queue from overflowing and triggering expensive flushes. | |
19605 | ||
19606 | This code monitors how load and store instructions are being issued | |
19607 | and skews the ready list one way or the other to increase the likelihood | |
19608 | that a desired instruction is issued at the proper time. | |
19609 | ||
19610 | A couple of things are done. First, we maintain a "load_store_pendulum" | |
19611 | to track the current state of load/store issue. | |
19612 | ||
19613 | - If the pendulum is at zero, then no loads or stores have been | |
19614 | issued in the current cycle so we do nothing. | |
19615 | ||
19616 | - If the pendulum is 1, then a single load has been issued in this | |
19617 | cycle and we attempt to locate another load in the ready list to | |
19618 | issue with it. | |
19619 | ||
2f8e468b | 19620 | - If the pendulum is -2, then two stores have already been |
44cd321e PS |
19621 | issued in this cycle, so we increase the priority of the first load |
19622 | in the ready list to increase it's likelihood of being chosen first | |
19623 | in the next cycle. | |
19624 | ||
19625 | - If the pendulum is -1, then a single store has been issued in this | |
19626 | cycle and we attempt to locate another store in the ready list to | |
19627 | issue with it, preferring a store to an adjacent memory location to | |
19628 | facilitate store pairing in the store queue. | |
19629 | ||
19630 | - If the pendulum is 2, then two loads have already been | |
19631 | issued in this cycle, so we increase the priority of the first store | |
19632 | in the ready list to increase it's likelihood of being chosen first | |
19633 | in the next cycle. | |
19634 | ||
19635 | - If the pendulum < -2 or > 2, then do nothing. | |
19636 | ||
19637 | Note: This code covers the most common scenarios. There exist non | |
19638 | load/store instructions which make use of the LSU and which | |
19639 | would need to be accounted for to strictly model the behavior | |
19640 | of the machine. Those instructions are currently unaccounted | |
19641 | for to help minimize compile time overhead of this code. | |
19642 | */ | |
19643 | if (rs6000_cpu == PROCESSOR_POWER6 && last_scheduled_insn) | |
19644 | { | |
19645 | int pos; | |
19646 | int i; | |
19647 | rtx tmp; | |
19648 | ||
19649 | if (is_store_insn (last_scheduled_insn)) | |
19650 | /* Issuing a store, swing the load_store_pendulum to the left */ | |
19651 | load_store_pendulum--; | |
19652 | else if (is_load_insn (last_scheduled_insn)) | |
19653 | /* Issuing a load, swing the load_store_pendulum to the right */ | |
19654 | load_store_pendulum++; | |
19655 | else | |
19656 | return cached_can_issue_more; | |
19657 | ||
19658 | /* If the pendulum is balanced, or there is only one instruction on | |
19659 | the ready list, then all is well, so return. */ | |
19660 | if ((load_store_pendulum == 0) || (*pn_ready <= 1)) | |
19661 | return cached_can_issue_more; | |
19662 | ||
19663 | if (load_store_pendulum == 1) | |
19664 | { | |
19665 | /* A load has been issued in this cycle. Scan the ready list | |
19666 | for another load to issue with it */ | |
19667 | pos = *pn_ready-1; | |
19668 | ||
19669 | while (pos >= 0) | |
19670 | { | |
19671 | if (is_load_insn (ready[pos])) | |
19672 | { | |
19673 | /* Found a load. Move it to the head of the ready list, | |
19674 | and adjust it's priority so that it is more likely to | |
19675 | stay there */ | |
19676 | tmp = ready[pos]; | |
19677 | for (i=pos; i<*pn_ready-1; i++) | |
19678 | ready[i] = ready[i + 1]; | |
19679 | ready[*pn_ready-1] = tmp; | |
e855c69d AB |
19680 | |
19681 | if (!sel_sched_p () && INSN_PRIORITY_KNOWN (tmp)) | |
44cd321e PS |
19682 | INSN_PRIORITY (tmp)++; |
19683 | break; | |
19684 | } | |
19685 | pos--; | |
19686 | } | |
19687 | } | |
19688 | else if (load_store_pendulum == -2) | |
19689 | { | |
19690 | /* Two stores have been issued in this cycle. Increase the | |
19691 | priority of the first load in the ready list to favor it for | |
19692 | issuing in the next cycle. */ | |
19693 | pos = *pn_ready-1; | |
19694 | ||
19695 | while (pos >= 0) | |
19696 | { | |
19697 | if (is_load_insn (ready[pos]) | |
e855c69d AB |
19698 | && !sel_sched_p () |
19699 | && INSN_PRIORITY_KNOWN (ready[pos])) | |
44cd321e PS |
19700 | { |
19701 | INSN_PRIORITY (ready[pos])++; | |
19702 | ||
19703 | /* Adjust the pendulum to account for the fact that a load | |
19704 | was found and increased in priority. This is to prevent | |
19705 | increasing the priority of multiple loads */ | |
19706 | load_store_pendulum--; | |
19707 | ||
19708 | break; | |
19709 | } | |
19710 | pos--; | |
19711 | } | |
19712 | } | |
19713 | else if (load_store_pendulum == -1) | |
19714 | { | |
19715 | /* A store has been issued in this cycle. Scan the ready list for | |
19716 | another store to issue with it, preferring a store to an adjacent | |
19717 | memory location */ | |
19718 | int first_store_pos = -1; | |
19719 | ||
19720 | pos = *pn_ready-1; | |
19721 | ||
19722 | while (pos >= 0) | |
19723 | { | |
19724 | if (is_store_insn (ready[pos])) | |
19725 | { | |
19726 | /* Maintain the index of the first store found on the | |
19727 | list */ | |
19728 | if (first_store_pos == -1) | |
19729 | first_store_pos = pos; | |
19730 | ||
19731 | if (is_store_insn (last_scheduled_insn) | |
19732 | && adjacent_mem_locations (last_scheduled_insn,ready[pos])) | |
19733 | { | |
19734 | /* Found an adjacent store. Move it to the head of the | |
19735 | ready list, and adjust it's priority so that it is | |
19736 | more likely to stay there */ | |
19737 | tmp = ready[pos]; | |
19738 | for (i=pos; i<*pn_ready-1; i++) | |
19739 | ready[i] = ready[i + 1]; | |
19740 | ready[*pn_ready-1] = tmp; | |
e855c69d AB |
19741 | |
19742 | if (!sel_sched_p () && INSN_PRIORITY_KNOWN (tmp)) | |
44cd321e | 19743 | INSN_PRIORITY (tmp)++; |
e855c69d | 19744 | |
44cd321e PS |
19745 | first_store_pos = -1; |
19746 | ||
19747 | break; | |
19748 | }; | |
19749 | } | |
19750 | pos--; | |
19751 | } | |
19752 | ||
19753 | if (first_store_pos >= 0) | |
19754 | { | |
19755 | /* An adjacent store wasn't found, but a non-adjacent store was, | |
19756 | so move the non-adjacent store to the front of the ready | |
19757 | list, and adjust its priority so that it is more likely to | |
19758 | stay there. */ | |
19759 | tmp = ready[first_store_pos]; | |
19760 | for (i=first_store_pos; i<*pn_ready-1; i++) | |
19761 | ready[i] = ready[i + 1]; | |
19762 | ready[*pn_ready-1] = tmp; | |
e855c69d | 19763 | if (!sel_sched_p () && INSN_PRIORITY_KNOWN (tmp)) |
44cd321e PS |
19764 | INSN_PRIORITY (tmp)++; |
19765 | } | |
19766 | } | |
19767 | else if (load_store_pendulum == 2) | |
19768 | { | |
19769 | /* Two loads have been issued in this cycle. Increase the priority | |
19770 | of the first store in the ready list to favor it for issuing in | |
19771 | the next cycle. */ | |
19772 | pos = *pn_ready-1; | |
19773 | ||
19774 | while (pos >= 0) | |
19775 | { | |
19776 | if (is_store_insn (ready[pos]) | |
e855c69d AB |
19777 | && !sel_sched_p () |
19778 | && INSN_PRIORITY_KNOWN (ready[pos])) | |
44cd321e PS |
19779 | { |
19780 | INSN_PRIORITY (ready[pos])++; | |
19781 | ||
19782 | /* Adjust the pendulum to account for the fact that a store | |
19783 | was found and increased in priority. This is to prevent | |
19784 | increasing the priority of multiple stores */ | |
19785 | load_store_pendulum++; | |
19786 | ||
19787 | break; | |
19788 | } | |
19789 | pos--; | |
19790 | } | |
19791 | } | |
19792 | } | |
19793 | ||
19794 | return cached_can_issue_more; | |
19795 | } | |
19796 | ||
839a4992 | 19797 | /* Return whether the presence of INSN causes a dispatch group termination |
cbe26ab8 DN |
19798 | of group WHICH_GROUP. |
19799 | ||
19800 | If WHICH_GROUP == current_group, this function will return true if INSN | |
19801 | causes the termination of the current group (i.e, the dispatch group to | |
19802 | which INSN belongs). This means that INSN will be the last insn in the | |
19803 | group it belongs to. | |
19804 | ||
19805 | If WHICH_GROUP == previous_group, this function will return true if INSN | |
19806 | causes the termination of the previous group (i.e, the dispatch group that | |
19807 | precedes the group to which INSN belongs). This means that INSN will be | |
19808 | the first insn in the group it belongs to). */ | |
19809 | ||
19810 | static bool | |
19811 | insn_terminates_group_p (rtx insn, enum group_termination which_group) | |
19812 | { | |
44cd321e | 19813 | bool first, last; |
cbe26ab8 DN |
19814 | |
19815 | if (! insn) | |
19816 | return false; | |
569fa502 | 19817 | |
44cd321e PS |
19818 | first = insn_must_be_first_in_group (insn); |
19819 | last = insn_must_be_last_in_group (insn); | |
cbe26ab8 | 19820 | |
44cd321e | 19821 | if (first && last) |
cbe26ab8 DN |
19822 | return true; |
19823 | ||
19824 | if (which_group == current_group) | |
44cd321e | 19825 | return last; |
cbe26ab8 | 19826 | else if (which_group == previous_group) |
44cd321e PS |
19827 | return first; |
19828 | ||
19829 | return false; | |
19830 | } | |
19831 | ||
19832 | ||
19833 | static bool | |
19834 | insn_must_be_first_in_group (rtx insn) | |
19835 | { | |
19836 | enum attr_type type; | |
19837 | ||
19838 | if (!insn | |
19839 | || insn == NULL_RTX | |
19840 | || GET_CODE (insn) == NOTE | |
19841 | || GET_CODE (PATTERN (insn)) == USE | |
19842 | || GET_CODE (PATTERN (insn)) == CLOBBER) | |
19843 | return false; | |
19844 | ||
19845 | switch (rs6000_cpu) | |
cbe26ab8 | 19846 | { |
44cd321e PS |
19847 | case PROCESSOR_POWER5: |
19848 | if (is_cracked_insn (insn)) | |
19849 | return true; | |
19850 | case PROCESSOR_POWER4: | |
19851 | if (is_microcoded_insn (insn)) | |
19852 | return true; | |
19853 | ||
19854 | if (!rs6000_sched_groups) | |
19855 | return false; | |
19856 | ||
19857 | type = get_attr_type (insn); | |
19858 | ||
19859 | switch (type) | |
19860 | { | |
19861 | case TYPE_MFCR: | |
19862 | case TYPE_MFCRF: | |
19863 | case TYPE_MTCR: | |
19864 | case TYPE_DELAYED_CR: | |
19865 | case TYPE_CR_LOGICAL: | |
19866 | case TYPE_MTJMPR: | |
19867 | case TYPE_MFJMPR: | |
19868 | case TYPE_IDIV: | |
19869 | case TYPE_LDIV: | |
19870 | case TYPE_LOAD_L: | |
19871 | case TYPE_STORE_C: | |
19872 | case TYPE_ISYNC: | |
19873 | case TYPE_SYNC: | |
19874 | return true; | |
19875 | default: | |
19876 | break; | |
19877 | } | |
19878 | break; | |
19879 | case PROCESSOR_POWER6: | |
19880 | type = get_attr_type (insn); | |
19881 | ||
19882 | switch (type) | |
19883 | { | |
19884 | case TYPE_INSERT_DWORD: | |
19885 | case TYPE_EXTS: | |
19886 | case TYPE_CNTLZ: | |
19887 | case TYPE_SHIFT: | |
19888 | case TYPE_VAR_SHIFT_ROTATE: | |
19889 | case TYPE_TRAP: | |
19890 | case TYPE_IMUL: | |
19891 | case TYPE_IMUL2: | |
19892 | case TYPE_IMUL3: | |
19893 | case TYPE_LMUL: | |
19894 | case TYPE_IDIV: | |
19895 | case TYPE_INSERT_WORD: | |
19896 | case TYPE_DELAYED_COMPARE: | |
19897 | case TYPE_IMUL_COMPARE: | |
19898 | case TYPE_LMUL_COMPARE: | |
19899 | case TYPE_FPCOMPARE: | |
19900 | case TYPE_MFCR: | |
19901 | case TYPE_MTCR: | |
19902 | case TYPE_MFJMPR: | |
19903 | case TYPE_MTJMPR: | |
19904 | case TYPE_ISYNC: | |
19905 | case TYPE_SYNC: | |
19906 | case TYPE_LOAD_L: | |
19907 | case TYPE_STORE_C: | |
19908 | case TYPE_LOAD_U: | |
19909 | case TYPE_LOAD_UX: | |
19910 | case TYPE_LOAD_EXT_UX: | |
19911 | case TYPE_STORE_U: | |
19912 | case TYPE_STORE_UX: | |
19913 | case TYPE_FPLOAD_U: | |
19914 | case TYPE_FPLOAD_UX: | |
19915 | case TYPE_FPSTORE_U: | |
19916 | case TYPE_FPSTORE_UX: | |
19917 | return true; | |
19918 | default: | |
19919 | break; | |
19920 | } | |
19921 | break; | |
19922 | default: | |
19923 | break; | |
19924 | } | |
19925 | ||
19926 | return false; | |
19927 | } | |
19928 | ||
19929 | static bool | |
19930 | insn_must_be_last_in_group (rtx insn) | |
19931 | { | |
19932 | enum attr_type type; | |
19933 | ||
19934 | if (!insn | |
19935 | || insn == NULL_RTX | |
19936 | || GET_CODE (insn) == NOTE | |
19937 | || GET_CODE (PATTERN (insn)) == USE | |
19938 | || GET_CODE (PATTERN (insn)) == CLOBBER) | |
19939 | return false; | |
19940 | ||
19941 | switch (rs6000_cpu) { | |
19942 | case PROCESSOR_POWER4: | |
19943 | case PROCESSOR_POWER5: | |
19944 | if (is_microcoded_insn (insn)) | |
19945 | return true; | |
19946 | ||
19947 | if (is_branch_slot_insn (insn)) | |
19948 | return true; | |
19949 | ||
19950 | break; | |
19951 | case PROCESSOR_POWER6: | |
19952 | type = get_attr_type (insn); | |
19953 | ||
19954 | switch (type) | |
19955 | { | |
19956 | case TYPE_EXTS: | |
19957 | case TYPE_CNTLZ: | |
19958 | case TYPE_SHIFT: | |
19959 | case TYPE_VAR_SHIFT_ROTATE: | |
19960 | case TYPE_TRAP: | |
19961 | case TYPE_IMUL: | |
19962 | case TYPE_IMUL2: | |
19963 | case TYPE_IMUL3: | |
19964 | case TYPE_LMUL: | |
19965 | case TYPE_IDIV: | |
19966 | case TYPE_DELAYED_COMPARE: | |
19967 | case TYPE_IMUL_COMPARE: | |
19968 | case TYPE_LMUL_COMPARE: | |
19969 | case TYPE_FPCOMPARE: | |
19970 | case TYPE_MFCR: | |
19971 | case TYPE_MTCR: | |
19972 | case TYPE_MFJMPR: | |
19973 | case TYPE_MTJMPR: | |
19974 | case TYPE_ISYNC: | |
19975 | case TYPE_SYNC: | |
19976 | case TYPE_LOAD_L: | |
19977 | case TYPE_STORE_C: | |
19978 | return true; | |
19979 | default: | |
19980 | break; | |
cbe26ab8 | 19981 | } |
44cd321e PS |
19982 | break; |
19983 | default: | |
19984 | break; | |
19985 | } | |
cbe26ab8 DN |
19986 | |
19987 | return false; | |
19988 | } | |
19989 | ||
839a4992 | 19990 | /* Return true if it is recommended to keep NEXT_INSN "far" (in a separate |
cbe26ab8 DN |
19991 | dispatch group) from the insns in GROUP_INSNS. Return false otherwise. */ |
19992 | ||
19993 | static bool | |
19994 | is_costly_group (rtx *group_insns, rtx next_insn) | |
19995 | { | |
19996 | int i; | |
cbe26ab8 DN |
19997 | int issue_rate = rs6000_issue_rate (); |
19998 | ||
19999 | for (i = 0; i < issue_rate; i++) | |
20000 | { | |
e2f6ff94 MK |
20001 | sd_iterator_def sd_it; |
20002 | dep_t dep; | |
cbe26ab8 | 20003 | rtx insn = group_insns[i]; |
b198261f | 20004 | |
cbe26ab8 | 20005 | if (!insn) |
c4ad648e | 20006 | continue; |
b198261f | 20007 | |
e2f6ff94 | 20008 | FOR_EACH_DEP (insn, SD_LIST_FORW, sd_it, dep) |
c4ad648e | 20009 | { |
b198261f MK |
20010 | rtx next = DEP_CON (dep); |
20011 | ||
20012 | if (next == next_insn | |
20013 | && rs6000_is_costly_dependence (dep, dep_cost (dep), 0)) | |
20014 | return true; | |
c4ad648e | 20015 | } |
cbe26ab8 DN |
20016 | } |
20017 | ||
20018 | return false; | |
20019 | } | |
20020 | ||
f676971a | 20021 | /* Utility of the function redefine_groups. |
cbe26ab8 DN |
20022 | Check if it is too costly to schedule NEXT_INSN together with GROUP_INSNS |
20023 | in the same dispatch group. If so, insert nops before NEXT_INSN, in order | |
20024 | to keep it "far" (in a separate group) from GROUP_INSNS, following | |
20025 | one of the following schemes, depending on the value of the flag | |
20026 | -minsert_sched_nops = X: | |
20027 | (1) X == sched_finish_regroup_exact: insert exactly as many nops as needed | |
839a4992 | 20028 | in order to force NEXT_INSN into a separate group. |
f676971a EC |
20029 | (2) X < sched_finish_regroup_exact: insert exactly X nops. |
20030 | GROUP_END, CAN_ISSUE_MORE and GROUP_COUNT record the state after nop | |
cbe26ab8 DN |
20031 | insertion (has a group just ended, how many vacant issue slots remain in the |
20032 | last group, and how many dispatch groups were encountered so far). */ | |
20033 | ||
f676971a | 20034 | static int |
c4ad648e AM |
20035 | force_new_group (int sched_verbose, FILE *dump, rtx *group_insns, |
20036 | rtx next_insn, bool *group_end, int can_issue_more, | |
20037 | int *group_count) | |
cbe26ab8 DN |
20038 | { |
20039 | rtx nop; | |
20040 | bool force; | |
20041 | int issue_rate = rs6000_issue_rate (); | |
20042 | bool end = *group_end; | |
20043 | int i; | |
20044 | ||
20045 | if (next_insn == NULL_RTX) | |
20046 | return can_issue_more; | |
20047 | ||
20048 | if (rs6000_sched_insert_nops > sched_finish_regroup_exact) | |
20049 | return can_issue_more; | |
20050 | ||
20051 | force = is_costly_group (group_insns, next_insn); | |
20052 | if (!force) | |
20053 | return can_issue_more; | |
20054 | ||
20055 | if (sched_verbose > 6) | |
20056 | fprintf (dump,"force: group count = %d, can_issue_more = %d\n", | |
c4ad648e | 20057 | *group_count ,can_issue_more); |
cbe26ab8 DN |
20058 | |
20059 | if (rs6000_sched_insert_nops == sched_finish_regroup_exact) | |
20060 | { | |
20061 | if (*group_end) | |
c4ad648e | 20062 | can_issue_more = 0; |
cbe26ab8 DN |
20063 | |
20064 | /* Since only a branch can be issued in the last issue_slot, it is | |
20065 | sufficient to insert 'can_issue_more - 1' nops if next_insn is not | |
20066 | a branch. If next_insn is a branch, we insert 'can_issue_more' nops; | |
c4ad648e AM |
20067 | in this case the last nop will start a new group and the branch |
20068 | will be forced to the new group. */ | |
cbe26ab8 | 20069 | if (can_issue_more && !is_branch_slot_insn (next_insn)) |
c4ad648e | 20070 | can_issue_more--; |
cbe26ab8 DN |
20071 | |
20072 | while (can_issue_more > 0) | |
c4ad648e | 20073 | { |
9390387d | 20074 | nop = gen_nop (); |
c4ad648e AM |
20075 | emit_insn_before (nop, next_insn); |
20076 | can_issue_more--; | |
20077 | } | |
cbe26ab8 DN |
20078 | |
20079 | *group_end = true; | |
20080 | return 0; | |
f676971a | 20081 | } |
cbe26ab8 DN |
20082 | |
20083 | if (rs6000_sched_insert_nops < sched_finish_regroup_exact) | |
20084 | { | |
20085 | int n_nops = rs6000_sched_insert_nops; | |
20086 | ||
f676971a | 20087 | /* Nops can't be issued from the branch slot, so the effective |
c4ad648e | 20088 | issue_rate for nops is 'issue_rate - 1'. */ |
cbe26ab8 | 20089 | if (can_issue_more == 0) |
c4ad648e | 20090 | can_issue_more = issue_rate; |
cbe26ab8 DN |
20091 | can_issue_more--; |
20092 | if (can_issue_more == 0) | |
c4ad648e AM |
20093 | { |
20094 | can_issue_more = issue_rate - 1; | |
20095 | (*group_count)++; | |
20096 | end = true; | |
20097 | for (i = 0; i < issue_rate; i++) | |
20098 | { | |
20099 | group_insns[i] = 0; | |
20100 | } | |
20101 | } | |
cbe26ab8 DN |
20102 | |
20103 | while (n_nops > 0) | |
c4ad648e AM |
20104 | { |
20105 | nop = gen_nop (); | |
20106 | emit_insn_before (nop, next_insn); | |
20107 | if (can_issue_more == issue_rate - 1) /* new group begins */ | |
20108 | end = false; | |
20109 | can_issue_more--; | |
20110 | if (can_issue_more == 0) | |
20111 | { | |
20112 | can_issue_more = issue_rate - 1; | |
20113 | (*group_count)++; | |
20114 | end = true; | |
20115 | for (i = 0; i < issue_rate; i++) | |
20116 | { | |
20117 | group_insns[i] = 0; | |
20118 | } | |
20119 | } | |
20120 | n_nops--; | |
20121 | } | |
cbe26ab8 DN |
20122 | |
20123 | /* Scale back relative to 'issue_rate' (instead of 'issue_rate - 1'). */ | |
f676971a | 20124 | can_issue_more++; |
cbe26ab8 | 20125 | |
c4ad648e AM |
20126 | /* Is next_insn going to start a new group? */ |
20127 | *group_end | |
20128 | = (end | |
cbe26ab8 DN |
20129 | || (can_issue_more == 1 && !is_branch_slot_insn (next_insn)) |
20130 | || (can_issue_more <= 2 && is_cracked_insn (next_insn)) | |
20131 | || (can_issue_more < issue_rate && | |
c4ad648e | 20132 | insn_terminates_group_p (next_insn, previous_group))); |
cbe26ab8 | 20133 | if (*group_end && end) |
c4ad648e | 20134 | (*group_count)--; |
cbe26ab8 DN |
20135 | |
20136 | if (sched_verbose > 6) | |
c4ad648e AM |
20137 | fprintf (dump, "done force: group count = %d, can_issue_more = %d\n", |
20138 | *group_count, can_issue_more); | |
f676971a EC |
20139 | return can_issue_more; |
20140 | } | |
cbe26ab8 DN |
20141 | |
20142 | return can_issue_more; | |
20143 | } | |
20144 | ||
20145 | /* This function tries to synch the dispatch groups that the compiler "sees" | |
f676971a | 20146 | with the dispatch groups that the processor dispatcher is expected to |
cbe26ab8 DN |
20147 | form in practice. It tries to achieve this synchronization by forcing the |
20148 | estimated processor grouping on the compiler (as opposed to the function | |
20149 | 'pad_goups' which tries to force the scheduler's grouping on the processor). | |
20150 | ||
20151 | The function scans the insn sequence between PREV_HEAD_INSN and TAIL and | |
20152 | examines the (estimated) dispatch groups that will be formed by the processor | |
20153 | dispatcher. It marks these group boundaries to reflect the estimated | |
20154 | processor grouping, overriding the grouping that the scheduler had marked. | |
20155 | Depending on the value of the flag '-minsert-sched-nops' this function can | |
20156 | force certain insns into separate groups or force a certain distance between | |
20157 | them by inserting nops, for example, if there exists a "costly dependence" | |
20158 | between the insns. | |
20159 | ||
20160 | The function estimates the group boundaries that the processor will form as | |
0fa2e4df | 20161 | follows: It keeps track of how many vacant issue slots are available after |
cbe26ab8 DN |
20162 | each insn. A subsequent insn will start a new group if one of the following |
20163 | 4 cases applies: | |
20164 | - no more vacant issue slots remain in the current dispatch group. | |
20165 | - only the last issue slot, which is the branch slot, is vacant, but the next | |
20166 | insn is not a branch. | |
20167 | - only the last 2 or less issue slots, including the branch slot, are vacant, | |
20168 | which means that a cracked insn (which occupies two issue slots) can't be | |
20169 | issued in this group. | |
f676971a | 20170 | - less than 'issue_rate' slots are vacant, and the next insn always needs to |
cbe26ab8 DN |
20171 | start a new group. */ |
20172 | ||
20173 | static int | |
20174 | redefine_groups (FILE *dump, int sched_verbose, rtx prev_head_insn, rtx tail) | |
20175 | { | |
20176 | rtx insn, next_insn; | |
20177 | int issue_rate; | |
20178 | int can_issue_more; | |
20179 | int slot, i; | |
20180 | bool group_end; | |
20181 | int group_count = 0; | |
20182 | rtx *group_insns; | |
20183 | ||
20184 | /* Initialize. */ | |
20185 | issue_rate = rs6000_issue_rate (); | |
5ead67f6 | 20186 | group_insns = XALLOCAVEC (rtx, issue_rate); |
f676971a | 20187 | for (i = 0; i < issue_rate; i++) |
cbe26ab8 DN |
20188 | { |
20189 | group_insns[i] = 0; | |
20190 | } | |
20191 | can_issue_more = issue_rate; | |
20192 | slot = 0; | |
20193 | insn = get_next_active_insn (prev_head_insn, tail); | |
20194 | group_end = false; | |
20195 | ||
20196 | while (insn != NULL_RTX) | |
20197 | { | |
20198 | slot = (issue_rate - can_issue_more); | |
20199 | group_insns[slot] = insn; | |
20200 | can_issue_more = | |
c4ad648e | 20201 | rs6000_variable_issue (dump, sched_verbose, insn, can_issue_more); |
cbe26ab8 | 20202 | if (insn_terminates_group_p (insn, current_group)) |
c4ad648e | 20203 | can_issue_more = 0; |
cbe26ab8 DN |
20204 | |
20205 | next_insn = get_next_active_insn (insn, tail); | |
20206 | if (next_insn == NULL_RTX) | |
c4ad648e | 20207 | return group_count + 1; |
cbe26ab8 | 20208 | |
c4ad648e AM |
20209 | /* Is next_insn going to start a new group? */ |
20210 | group_end | |
20211 | = (can_issue_more == 0 | |
20212 | || (can_issue_more == 1 && !is_branch_slot_insn (next_insn)) | |
20213 | || (can_issue_more <= 2 && is_cracked_insn (next_insn)) | |
20214 | || (can_issue_more < issue_rate && | |
20215 | insn_terminates_group_p (next_insn, previous_group))); | |
cbe26ab8 | 20216 | |
f676971a | 20217 | can_issue_more = force_new_group (sched_verbose, dump, group_insns, |
c4ad648e AM |
20218 | next_insn, &group_end, can_issue_more, |
20219 | &group_count); | |
cbe26ab8 DN |
20220 | |
20221 | if (group_end) | |
c4ad648e AM |
20222 | { |
20223 | group_count++; | |
20224 | can_issue_more = 0; | |
20225 | for (i = 0; i < issue_rate; i++) | |
20226 | { | |
20227 | group_insns[i] = 0; | |
20228 | } | |
20229 | } | |
cbe26ab8 DN |
20230 | |
20231 | if (GET_MODE (next_insn) == TImode && can_issue_more) | |
9390387d | 20232 | PUT_MODE (next_insn, VOIDmode); |
cbe26ab8 | 20233 | else if (!can_issue_more && GET_MODE (next_insn) != TImode) |
c4ad648e | 20234 | PUT_MODE (next_insn, TImode); |
cbe26ab8 DN |
20235 | |
20236 | insn = next_insn; | |
20237 | if (can_issue_more == 0) | |
c4ad648e AM |
20238 | can_issue_more = issue_rate; |
20239 | } /* while */ | |
cbe26ab8 DN |
20240 | |
20241 | return group_count; | |
20242 | } | |
20243 | ||
20244 | /* Scan the insn sequence between PREV_HEAD_INSN and TAIL and examine the | |
20245 | dispatch group boundaries that the scheduler had marked. Pad with nops | |
20246 | any dispatch groups which have vacant issue slots, in order to force the | |
20247 | scheduler's grouping on the processor dispatcher. The function | |
20248 | returns the number of dispatch groups found. */ | |
20249 | ||
20250 | static int | |
20251 | pad_groups (FILE *dump, int sched_verbose, rtx prev_head_insn, rtx tail) | |
20252 | { | |
20253 | rtx insn, next_insn; | |
20254 | rtx nop; | |
20255 | int issue_rate; | |
20256 | int can_issue_more; | |
20257 | int group_end; | |
20258 | int group_count = 0; | |
20259 | ||
20260 | /* Initialize issue_rate. */ | |
20261 | issue_rate = rs6000_issue_rate (); | |
20262 | can_issue_more = issue_rate; | |
20263 | ||
20264 | insn = get_next_active_insn (prev_head_insn, tail); | |
20265 | next_insn = get_next_active_insn (insn, tail); | |
20266 | ||
20267 | while (insn != NULL_RTX) | |
20268 | { | |
20269 | can_issue_more = | |
20270 | rs6000_variable_issue (dump, sched_verbose, insn, can_issue_more); | |
20271 | ||
20272 | group_end = (next_insn == NULL_RTX || GET_MODE (next_insn) == TImode); | |
20273 | ||
20274 | if (next_insn == NULL_RTX) | |
c4ad648e | 20275 | break; |
cbe26ab8 DN |
20276 | |
20277 | if (group_end) | |
c4ad648e AM |
20278 | { |
20279 | /* If the scheduler had marked group termination at this location | |
e855c69d | 20280 | (between insn and next_insn), and neither insn nor next_insn will |
c4ad648e AM |
20281 | force group termination, pad the group with nops to force group |
20282 | termination. */ | |
20283 | if (can_issue_more | |
20284 | && (rs6000_sched_insert_nops == sched_finish_pad_groups) | |
20285 | && !insn_terminates_group_p (insn, current_group) | |
20286 | && !insn_terminates_group_p (next_insn, previous_group)) | |
20287 | { | |
9390387d | 20288 | if (!is_branch_slot_insn (next_insn)) |
c4ad648e AM |
20289 | can_issue_more--; |
20290 | ||
20291 | while (can_issue_more) | |
20292 | { | |
20293 | nop = gen_nop (); | |
20294 | emit_insn_before (nop, next_insn); | |
20295 | can_issue_more--; | |
20296 | } | |
20297 | } | |
20298 | ||
20299 | can_issue_more = issue_rate; | |
20300 | group_count++; | |
20301 | } | |
cbe26ab8 DN |
20302 | |
20303 | insn = next_insn; | |
20304 | next_insn = get_next_active_insn (insn, tail); | |
20305 | } | |
20306 | ||
20307 | return group_count; | |
20308 | } | |
20309 | ||
44cd321e PS |
20310 | /* We're beginning a new block. Initialize data structures as necessary. */ |
20311 | ||
20312 | static void | |
20313 | rs6000_sched_init (FILE *dump ATTRIBUTE_UNUSED, | |
20314 | int sched_verbose ATTRIBUTE_UNUSED, | |
20315 | int max_ready ATTRIBUTE_UNUSED) | |
982afe02 | 20316 | { |
44cd321e PS |
20317 | last_scheduled_insn = NULL_RTX; |
20318 | load_store_pendulum = 0; | |
20319 | } | |
20320 | ||
cbe26ab8 DN |
20321 | /* The following function is called at the end of scheduling BB. |
20322 | After reload, it inserts nops at insn group bundling. */ | |
20323 | ||
20324 | static void | |
38f391a5 | 20325 | rs6000_sched_finish (FILE *dump, int sched_verbose) |
cbe26ab8 DN |
20326 | { |
20327 | int n_groups; | |
20328 | ||
20329 | if (sched_verbose) | |
20330 | fprintf (dump, "=== Finishing schedule.\n"); | |
20331 | ||
ec507f2d | 20332 | if (reload_completed && rs6000_sched_groups) |
cbe26ab8 | 20333 | { |
e855c69d AB |
20334 | /* Do not run sched_finish hook when selective scheduling enabled. */ |
20335 | if (sel_sched_p ()) | |
20336 | return; | |
20337 | ||
cbe26ab8 | 20338 | if (rs6000_sched_insert_nops == sched_finish_none) |
c4ad648e | 20339 | return; |
cbe26ab8 DN |
20340 | |
20341 | if (rs6000_sched_insert_nops == sched_finish_pad_groups) | |
c4ad648e AM |
20342 | n_groups = pad_groups (dump, sched_verbose, |
20343 | current_sched_info->prev_head, | |
20344 | current_sched_info->next_tail); | |
cbe26ab8 | 20345 | else |
c4ad648e AM |
20346 | n_groups = redefine_groups (dump, sched_verbose, |
20347 | current_sched_info->prev_head, | |
20348 | current_sched_info->next_tail); | |
cbe26ab8 DN |
20349 | |
20350 | if (sched_verbose >= 6) | |
20351 | { | |
20352 | fprintf (dump, "ngroups = %d\n", n_groups); | |
20353 | print_rtl (dump, current_sched_info->prev_head); | |
20354 | fprintf (dump, "Done finish_sched\n"); | |
20355 | } | |
20356 | } | |
20357 | } | |
e855c69d AB |
20358 | |
20359 | struct _rs6000_sched_context | |
20360 | { | |
20361 | short cached_can_issue_more; | |
20362 | rtx last_scheduled_insn; | |
20363 | int load_store_pendulum; | |
20364 | }; | |
20365 | ||
20366 | typedef struct _rs6000_sched_context rs6000_sched_context_def; | |
20367 | typedef rs6000_sched_context_def *rs6000_sched_context_t; | |
20368 | ||
20369 | /* Allocate store for new scheduling context. */ | |
20370 | static void * | |
20371 | rs6000_alloc_sched_context (void) | |
20372 | { | |
20373 | return xmalloc (sizeof (rs6000_sched_context_def)); | |
20374 | } | |
20375 | ||
20376 | /* If CLEAN_P is true then initializes _SC with clean data, | |
20377 | and from the global context otherwise. */ | |
20378 | static void | |
20379 | rs6000_init_sched_context (void *_sc, bool clean_p) | |
20380 | { | |
20381 | rs6000_sched_context_t sc = (rs6000_sched_context_t) _sc; | |
20382 | ||
20383 | if (clean_p) | |
20384 | { | |
20385 | sc->cached_can_issue_more = 0; | |
20386 | sc->last_scheduled_insn = NULL_RTX; | |
20387 | sc->load_store_pendulum = 0; | |
20388 | } | |
20389 | else | |
20390 | { | |
20391 | sc->cached_can_issue_more = cached_can_issue_more; | |
20392 | sc->last_scheduled_insn = last_scheduled_insn; | |
20393 | sc->load_store_pendulum = load_store_pendulum; | |
20394 | } | |
20395 | } | |
20396 | ||
20397 | /* Sets the global scheduling context to the one pointed to by _SC. */ | |
20398 | static void | |
20399 | rs6000_set_sched_context (void *_sc) | |
20400 | { | |
20401 | rs6000_sched_context_t sc = (rs6000_sched_context_t) _sc; | |
20402 | ||
20403 | gcc_assert (sc != NULL); | |
20404 | ||
20405 | cached_can_issue_more = sc->cached_can_issue_more; | |
20406 | last_scheduled_insn = sc->last_scheduled_insn; | |
20407 | load_store_pendulum = sc->load_store_pendulum; | |
20408 | } | |
20409 | ||
20410 | /* Free _SC. */ | |
20411 | static void | |
20412 | rs6000_free_sched_context (void *_sc) | |
20413 | { | |
20414 | gcc_assert (_sc != NULL); | |
20415 | ||
20416 | free (_sc); | |
20417 | } | |
20418 | ||
b6c9286a | 20419 | \f |
b6c9286a MM |
20420 | /* Length in units of the trampoline for entering a nested function. */ |
20421 | ||
20422 | int | |
863d938c | 20423 | rs6000_trampoline_size (void) |
b6c9286a MM |
20424 | { |
20425 | int ret = 0; | |
20426 | ||
20427 | switch (DEFAULT_ABI) | |
20428 | { | |
20429 | default: | |
37409796 | 20430 | gcc_unreachable (); |
b6c9286a MM |
20431 | |
20432 | case ABI_AIX: | |
8f802bfb | 20433 | ret = (TARGET_32BIT) ? 12 : 24; |
b6c9286a MM |
20434 | break; |
20435 | ||
4dabc42d | 20436 | case ABI_DARWIN: |
b6c9286a | 20437 | case ABI_V4: |
03a7e1a5 | 20438 | ret = (TARGET_32BIT) ? 40 : 48; |
b6c9286a | 20439 | break; |
b6c9286a MM |
20440 | } |
20441 | ||
20442 | return ret; | |
20443 | } | |
20444 | ||
20445 | /* Emit RTL insns to initialize the variable parts of a trampoline. | |
20446 | FNADDR is an RTX for the address of the function's pure code. | |
20447 | CXT is an RTX for the static chain value for the function. */ | |
20448 | ||
20449 | void | |
a2369ed3 | 20450 | rs6000_initialize_trampoline (rtx addr, rtx fnaddr, rtx cxt) |
b6c9286a | 20451 | { |
8bd04c56 | 20452 | int regsize = (TARGET_32BIT) ? 4 : 8; |
9613eaff | 20453 | rtx ctx_reg = force_reg (Pmode, cxt); |
b6c9286a MM |
20454 | |
20455 | switch (DEFAULT_ABI) | |
20456 | { | |
20457 | default: | |
37409796 | 20458 | gcc_unreachable (); |
b6c9286a | 20459 | |
8bd04c56 | 20460 | /* Macros to shorten the code expansions below. */ |
9613eaff | 20461 | #define MEM_DEREF(addr) gen_rtx_MEM (Pmode, memory_address (Pmode, addr)) |
c5c76735 | 20462 | #define MEM_PLUS(addr,offset) \ |
9613eaff | 20463 | gen_rtx_MEM (Pmode, memory_address (Pmode, plus_constant (addr, offset))) |
7c59dc5d | 20464 | |
b6c9286a MM |
20465 | /* Under AIX, just build the 3 word function descriptor */ |
20466 | case ABI_AIX: | |
8bd04c56 | 20467 | { |
9613eaff SH |
20468 | rtx fn_reg = gen_reg_rtx (Pmode); |
20469 | rtx toc_reg = gen_reg_rtx (Pmode); | |
8bd04c56 | 20470 | emit_move_insn (fn_reg, MEM_DEREF (fnaddr)); |
1cb18e3c | 20471 | emit_move_insn (toc_reg, MEM_PLUS (fnaddr, regsize)); |
8bd04c56 MM |
20472 | emit_move_insn (MEM_DEREF (addr), fn_reg); |
20473 | emit_move_insn (MEM_PLUS (addr, regsize), toc_reg); | |
20474 | emit_move_insn (MEM_PLUS (addr, 2*regsize), ctx_reg); | |
20475 | } | |
b6c9286a MM |
20476 | break; |
20477 | ||
4dabc42d TC |
20478 | /* Under V.4/eabi/darwin, __trampoline_setup does the real work. */ |
20479 | case ABI_DARWIN: | |
b6c9286a | 20480 | case ABI_V4: |
9613eaff | 20481 | emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__trampoline_setup"), |
bbbbb16a | 20482 | LCT_NORMAL, VOIDmode, 4, |
9613eaff | 20483 | addr, Pmode, |
eaf1bcf1 | 20484 | GEN_INT (rs6000_trampoline_size ()), SImode, |
9613eaff SH |
20485 | fnaddr, Pmode, |
20486 | ctx_reg, Pmode); | |
b6c9286a | 20487 | break; |
b6c9286a MM |
20488 | } |
20489 | ||
20490 | return; | |
20491 | } | |
7509c759 MM |
20492 | |
20493 | \f | |
91d231cb | 20494 | /* Table of valid machine attributes. */ |
a4f6c312 | 20495 | |
91d231cb | 20496 | const struct attribute_spec rs6000_attribute_table[] = |
7509c759 | 20497 | { |
91d231cb | 20498 | /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */ |
8bb418a3 | 20499 | { "altivec", 1, 1, false, true, false, rs6000_handle_altivec_attribute }, |
a5c76ee6 ZW |
20500 | { "longcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute }, |
20501 | { "shortcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute }, | |
77ccdfed EC |
20502 | { "ms_struct", 0, 0, false, false, false, rs6000_handle_struct_attribute }, |
20503 | { "gcc_struct", 0, 0, false, false, false, rs6000_handle_struct_attribute }, | |
005c1a13 GK |
20504 | #ifdef SUBTARGET_ATTRIBUTE_TABLE |
20505 | SUBTARGET_ATTRIBUTE_TABLE, | |
20506 | #endif | |
a5c76ee6 | 20507 | { NULL, 0, 0, false, false, false, NULL } |
91d231cb | 20508 | }; |
7509c759 | 20509 | |
8bb418a3 ZL |
20510 | /* Handle the "altivec" attribute. The attribute may have |
20511 | arguments as follows: | |
f676971a | 20512 | |
8bb418a3 ZL |
20513 | __attribute__((altivec(vector__))) |
20514 | __attribute__((altivec(pixel__))) (always followed by 'unsigned short') | |
20515 | __attribute__((altivec(bool__))) (always followed by 'unsigned') | |
20516 | ||
20517 | and may appear more than once (e.g., 'vector bool char') in a | |
20518 | given declaration. */ | |
20519 | ||
20520 | static tree | |
f90ac3f0 UP |
20521 | rs6000_handle_altivec_attribute (tree *node, |
20522 | tree name ATTRIBUTE_UNUSED, | |
20523 | tree args, | |
8bb418a3 ZL |
20524 | int flags ATTRIBUTE_UNUSED, |
20525 | bool *no_add_attrs) | |
20526 | { | |
20527 | tree type = *node, result = NULL_TREE; | |
20528 | enum machine_mode mode; | |
20529 | int unsigned_p; | |
20530 | char altivec_type | |
20531 | = ((args && TREE_CODE (args) == TREE_LIST && TREE_VALUE (args) | |
20532 | && TREE_CODE (TREE_VALUE (args)) == IDENTIFIER_NODE) | |
20533 | ? *IDENTIFIER_POINTER (TREE_VALUE (args)) | |
f676971a | 20534 | : '?'); |
8bb418a3 ZL |
20535 | |
20536 | while (POINTER_TYPE_P (type) | |
20537 | || TREE_CODE (type) == FUNCTION_TYPE | |
20538 | || TREE_CODE (type) == METHOD_TYPE | |
20539 | || TREE_CODE (type) == ARRAY_TYPE) | |
20540 | type = TREE_TYPE (type); | |
20541 | ||
20542 | mode = TYPE_MODE (type); | |
20543 | ||
f90ac3f0 UP |
20544 | /* Check for invalid AltiVec type qualifiers. */ |
20545 | if (type == long_unsigned_type_node || type == long_integer_type_node) | |
20546 | { | |
20547 | if (TARGET_64BIT) | |
20548 | error ("use of %<long%> in AltiVec types is invalid for 64-bit code"); | |
20549 | else if (rs6000_warn_altivec_long) | |
d4ee4d25 | 20550 | warning (0, "use of %<long%> in AltiVec types is deprecated; use %<int%>"); |
f90ac3f0 UP |
20551 | } |
20552 | else if (type == long_long_unsigned_type_node | |
20553 | || type == long_long_integer_type_node) | |
20554 | error ("use of %<long long%> in AltiVec types is invalid"); | |
20555 | else if (type == double_type_node) | |
20556 | error ("use of %<double%> in AltiVec types is invalid"); | |
20557 | else if (type == long_double_type_node) | |
20558 | error ("use of %<long double%> in AltiVec types is invalid"); | |
20559 | else if (type == boolean_type_node) | |
20560 | error ("use of boolean types in AltiVec types is invalid"); | |
20561 | else if (TREE_CODE (type) == COMPLEX_TYPE) | |
20562 | error ("use of %<complex%> in AltiVec types is invalid"); | |
00b79d54 BE |
20563 | else if (DECIMAL_FLOAT_MODE_P (mode)) |
20564 | error ("use of decimal floating point types in AltiVec types is invalid"); | |
8bb418a3 ZL |
20565 | |
20566 | switch (altivec_type) | |
20567 | { | |
20568 | case 'v': | |
8df83eae | 20569 | unsigned_p = TYPE_UNSIGNED (type); |
8bb418a3 ZL |
20570 | switch (mode) |
20571 | { | |
c4ad648e AM |
20572 | case SImode: |
20573 | result = (unsigned_p ? unsigned_V4SI_type_node : V4SI_type_node); | |
20574 | break; | |
20575 | case HImode: | |
20576 | result = (unsigned_p ? unsigned_V8HI_type_node : V8HI_type_node); | |
20577 | break; | |
20578 | case QImode: | |
20579 | result = (unsigned_p ? unsigned_V16QI_type_node : V16QI_type_node); | |
20580 | break; | |
20581 | case SFmode: result = V4SF_type_node; break; | |
20582 | /* If the user says 'vector int bool', we may be handed the 'bool' | |
20583 | attribute _before_ the 'vector' attribute, and so select the | |
20584 | proper type in the 'b' case below. */ | |
20585 | case V4SImode: case V8HImode: case V16QImode: case V4SFmode: | |
20586 | result = type; | |
20587 | default: break; | |
8bb418a3 ZL |
20588 | } |
20589 | break; | |
20590 | case 'b': | |
20591 | switch (mode) | |
20592 | { | |
c4ad648e AM |
20593 | case SImode: case V4SImode: result = bool_V4SI_type_node; break; |
20594 | case HImode: case V8HImode: result = bool_V8HI_type_node; break; | |
20595 | case QImode: case V16QImode: result = bool_V16QI_type_node; | |
20596 | default: break; | |
8bb418a3 ZL |
20597 | } |
20598 | break; | |
20599 | case 'p': | |
20600 | switch (mode) | |
20601 | { | |
c4ad648e AM |
20602 | case V8HImode: result = pixel_V8HI_type_node; |
20603 | default: break; | |
8bb418a3 ZL |
20604 | } |
20605 | default: break; | |
20606 | } | |
20607 | ||
4f538d42 UW |
20608 | /* Propagate qualifiers attached to the element type |
20609 | onto the vector type. */ | |
20610 | if (result && result != type && TYPE_QUALS (type)) | |
20611 | result = build_qualified_type (result, TYPE_QUALS (type)); | |
7958a2a6 | 20612 | |
8bb418a3 ZL |
20613 | *no_add_attrs = true; /* No need to hang on to the attribute. */ |
20614 | ||
f90ac3f0 | 20615 | if (result) |
5dc11954 | 20616 | *node = lang_hooks.types.reconstruct_complex_type (*node, result); |
8bb418a3 ZL |
20617 | |
20618 | return NULL_TREE; | |
20619 | } | |
20620 | ||
f18eca82 ZL |
20621 | /* AltiVec defines four built-in scalar types that serve as vector |
20622 | elements; we must teach the compiler how to mangle them. */ | |
20623 | ||
20624 | static const char * | |
3101faab | 20625 | rs6000_mangle_type (const_tree type) |
f18eca82 | 20626 | { |
608063c3 JB |
20627 | type = TYPE_MAIN_VARIANT (type); |
20628 | ||
20629 | if (TREE_CODE (type) != VOID_TYPE && TREE_CODE (type) != BOOLEAN_TYPE | |
20630 | && TREE_CODE (type) != INTEGER_TYPE && TREE_CODE (type) != REAL_TYPE) | |
20631 | return NULL; | |
20632 | ||
f18eca82 ZL |
20633 | if (type == bool_char_type_node) return "U6__boolc"; |
20634 | if (type == bool_short_type_node) return "U6__bools"; | |
20635 | if (type == pixel_type_node) return "u7__pixel"; | |
20636 | if (type == bool_int_type_node) return "U6__booli"; | |
20637 | ||
337bde91 DE |
20638 | /* Mangle IBM extended float long double as `g' (__float128) on |
20639 | powerpc*-linux where long-double-64 previously was the default. */ | |
20640 | if (TYPE_MAIN_VARIANT (type) == long_double_type_node | |
20641 | && TARGET_ELF | |
20642 | && TARGET_LONG_DOUBLE_128 | |
20643 | && !TARGET_IEEEQUAD) | |
20644 | return "g"; | |
20645 | ||
f18eca82 ZL |
20646 | /* For all other types, use normal C++ mangling. */ |
20647 | return NULL; | |
20648 | } | |
20649 | ||
a5c76ee6 ZW |
20650 | /* Handle a "longcall" or "shortcall" attribute; arguments as in |
20651 | struct attribute_spec.handler. */ | |
a4f6c312 | 20652 | |
91d231cb | 20653 | static tree |
f676971a EC |
20654 | rs6000_handle_longcall_attribute (tree *node, tree name, |
20655 | tree args ATTRIBUTE_UNUSED, | |
20656 | int flags ATTRIBUTE_UNUSED, | |
a2369ed3 | 20657 | bool *no_add_attrs) |
91d231cb JM |
20658 | { |
20659 | if (TREE_CODE (*node) != FUNCTION_TYPE | |
20660 | && TREE_CODE (*node) != FIELD_DECL | |
20661 | && TREE_CODE (*node) != TYPE_DECL) | |
20662 | { | |
5c498b10 | 20663 | warning (OPT_Wattributes, "%qs attribute only applies to functions", |
91d231cb JM |
20664 | IDENTIFIER_POINTER (name)); |
20665 | *no_add_attrs = true; | |
20666 | } | |
6a4cee5f | 20667 | |
91d231cb | 20668 | return NULL_TREE; |
7509c759 MM |
20669 | } |
20670 | ||
a5c76ee6 ZW |
20671 | /* Set longcall attributes on all functions declared when |
20672 | rs6000_default_long_calls is true. */ | |
20673 | static void | |
a2369ed3 | 20674 | rs6000_set_default_type_attributes (tree type) |
a5c76ee6 ZW |
20675 | { |
20676 | if (rs6000_default_long_calls | |
20677 | && (TREE_CODE (type) == FUNCTION_TYPE | |
20678 | || TREE_CODE (type) == METHOD_TYPE)) | |
20679 | TYPE_ATTRIBUTES (type) = tree_cons (get_identifier ("longcall"), | |
20680 | NULL_TREE, | |
20681 | TYPE_ATTRIBUTES (type)); | |
16d6f994 EC |
20682 | |
20683 | #if TARGET_MACHO | |
20684 | darwin_set_default_type_attributes (type); | |
20685 | #endif | |
a5c76ee6 ZW |
20686 | } |
20687 | ||
3cb999d8 DE |
20688 | /* Return a reference suitable for calling a function with the |
20689 | longcall attribute. */ | |
a4f6c312 | 20690 | |
9390387d | 20691 | rtx |
a2369ed3 | 20692 | rs6000_longcall_ref (rtx call_ref) |
6a4cee5f | 20693 | { |
d330fd93 | 20694 | const char *call_name; |
6a4cee5f MM |
20695 | tree node; |
20696 | ||
20697 | if (GET_CODE (call_ref) != SYMBOL_REF) | |
20698 | return call_ref; | |
20699 | ||
20700 | /* System V adds '.' to the internal name, so skip them. */ | |
20701 | call_name = XSTR (call_ref, 0); | |
20702 | if (*call_name == '.') | |
20703 | { | |
20704 | while (*call_name == '.') | |
20705 | call_name++; | |
20706 | ||
20707 | node = get_identifier (call_name); | |
39403d82 | 20708 | call_ref = gen_rtx_SYMBOL_REF (VOIDmode, IDENTIFIER_POINTER (node)); |
6a4cee5f MM |
20709 | } |
20710 | ||
20711 | return force_reg (Pmode, call_ref); | |
20712 | } | |
7509c759 | 20713 | \f |
77ccdfed EC |
20714 | #ifndef TARGET_USE_MS_BITFIELD_LAYOUT |
20715 | #define TARGET_USE_MS_BITFIELD_LAYOUT 0 | |
20716 | #endif | |
20717 | ||
20718 | /* Handle a "ms_struct" or "gcc_struct" attribute; arguments as in | |
20719 | struct attribute_spec.handler. */ | |
20720 | static tree | |
20721 | rs6000_handle_struct_attribute (tree *node, tree name, | |
20722 | tree args ATTRIBUTE_UNUSED, | |
20723 | int flags ATTRIBUTE_UNUSED, bool *no_add_attrs) | |
20724 | { | |
20725 | tree *type = NULL; | |
20726 | if (DECL_P (*node)) | |
20727 | { | |
20728 | if (TREE_CODE (*node) == TYPE_DECL) | |
20729 | type = &TREE_TYPE (*node); | |
20730 | } | |
20731 | else | |
20732 | type = node; | |
20733 | ||
20734 | if (!(type && (TREE_CODE (*type) == RECORD_TYPE | |
20735 | || TREE_CODE (*type) == UNION_TYPE))) | |
20736 | { | |
20737 | warning (OPT_Wattributes, "%qs attribute ignored", IDENTIFIER_POINTER (name)); | |
20738 | *no_add_attrs = true; | |
20739 | } | |
20740 | ||
20741 | else if ((is_attribute_p ("ms_struct", name) | |
20742 | && lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (*type))) | |
20743 | || ((is_attribute_p ("gcc_struct", name) | |
20744 | && lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (*type))))) | |
20745 | { | |
20746 | warning (OPT_Wattributes, "%qs incompatible attribute ignored", | |
20747 | IDENTIFIER_POINTER (name)); | |
20748 | *no_add_attrs = true; | |
20749 | } | |
20750 | ||
20751 | return NULL_TREE; | |
20752 | } | |
20753 | ||
20754 | static bool | |
3101faab | 20755 | rs6000_ms_bitfield_layout_p (const_tree record_type) |
77ccdfed EC |
20756 | { |
20757 | return (TARGET_USE_MS_BITFIELD_LAYOUT && | |
20758 | !lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (record_type))) | |
20759 | || lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (record_type)); | |
20760 | } | |
20761 | \f | |
b64a1b53 RH |
20762 | #ifdef USING_ELFOS_H |
20763 | ||
d6b5193b | 20764 | /* A get_unnamed_section callback, used for switching to toc_section. */ |
7509c759 | 20765 | |
d6b5193b RS |
20766 | static void |
20767 | rs6000_elf_output_toc_section_asm_op (const void *data ATTRIBUTE_UNUSED) | |
20768 | { | |
20769 | if (DEFAULT_ABI == ABI_AIX | |
20770 | && TARGET_MINIMAL_TOC | |
20771 | && !TARGET_RELOCATABLE) | |
20772 | { | |
20773 | if (!toc_initialized) | |
20774 | { | |
20775 | toc_initialized = 1; | |
20776 | fprintf (asm_out_file, "%s\n", TOC_SECTION_ASM_OP); | |
20777 | (*targetm.asm_out.internal_label) (asm_out_file, "LCTOC", 0); | |
20778 | fprintf (asm_out_file, "\t.tc "); | |
20779 | ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1[TC],"); | |
20780 | ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1"); | |
20781 | fprintf (asm_out_file, "\n"); | |
20782 | ||
20783 | fprintf (asm_out_file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP); | |
20784 | ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1"); | |
20785 | fprintf (asm_out_file, " = .+32768\n"); | |
20786 | } | |
20787 | else | |
20788 | fprintf (asm_out_file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP); | |
20789 | } | |
20790 | else if (DEFAULT_ABI == ABI_AIX && !TARGET_RELOCATABLE) | |
20791 | fprintf (asm_out_file, "%s\n", TOC_SECTION_ASM_OP); | |
20792 | else | |
20793 | { | |
20794 | fprintf (asm_out_file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP); | |
20795 | if (!toc_initialized) | |
20796 | { | |
20797 | ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1"); | |
20798 | fprintf (asm_out_file, " = .+32768\n"); | |
20799 | toc_initialized = 1; | |
20800 | } | |
20801 | } | |
20802 | } | |
20803 | ||
20804 | /* Implement TARGET_ASM_INIT_SECTIONS. */ | |
7509c759 | 20805 | |
b64a1b53 | 20806 | static void |
d6b5193b RS |
20807 | rs6000_elf_asm_init_sections (void) |
20808 | { | |
20809 | toc_section | |
20810 | = get_unnamed_section (0, rs6000_elf_output_toc_section_asm_op, NULL); | |
20811 | ||
20812 | sdata2_section | |
20813 | = get_unnamed_section (SECTION_WRITE, output_section_asm_op, | |
20814 | SDATA2_SECTION_ASM_OP); | |
20815 | } | |
20816 | ||
20817 | /* Implement TARGET_SELECT_RTX_SECTION. */ | |
20818 | ||
20819 | static section * | |
f676971a | 20820 | rs6000_elf_select_rtx_section (enum machine_mode mode, rtx x, |
a2369ed3 | 20821 | unsigned HOST_WIDE_INT align) |
7509c759 | 20822 | { |
a9098fd0 | 20823 | if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode)) |
d6b5193b | 20824 | return toc_section; |
7509c759 | 20825 | else |
d6b5193b | 20826 | return default_elf_select_rtx_section (mode, x, align); |
7509c759 | 20827 | } |
d9407988 | 20828 | \f |
d1908feb JJ |
20829 | /* For a SYMBOL_REF, set generic flags and then perform some |
20830 | target-specific processing. | |
20831 | ||
d1908feb JJ |
20832 | When the AIX ABI is requested on a non-AIX system, replace the |
20833 | function name with the real name (with a leading .) rather than the | |
20834 | function descriptor name. This saves a lot of overriding code to | |
20835 | read the prefixes. */ | |
d9407988 | 20836 | |
fb49053f | 20837 | static void |
a2369ed3 | 20838 | rs6000_elf_encode_section_info (tree decl, rtx rtl, int first) |
d9407988 | 20839 | { |
d1908feb | 20840 | default_encode_section_info (decl, rtl, first); |
b2003250 | 20841 | |
d1908feb JJ |
20842 | if (first |
20843 | && TREE_CODE (decl) == FUNCTION_DECL | |
20844 | && !TARGET_AIX | |
20845 | && DEFAULT_ABI == ABI_AIX) | |
d9407988 | 20846 | { |
c6a2438a | 20847 | rtx sym_ref = XEXP (rtl, 0); |
d1908feb | 20848 | size_t len = strlen (XSTR (sym_ref, 0)); |
5ead67f6 | 20849 | char *str = XALLOCAVEC (char, len + 2); |
d1908feb JJ |
20850 | str[0] = '.'; |
20851 | memcpy (str + 1, XSTR (sym_ref, 0), len + 1); | |
20852 | XSTR (sym_ref, 0) = ggc_alloc_string (str, len + 1); | |
d9407988 | 20853 | } |
d9407988 MM |
20854 | } |
20855 | ||
21d9bb3f | 20856 | static inline bool |
0a2aaacc | 20857 | compare_section_name (const char *section, const char *templ) |
21d9bb3f PB |
20858 | { |
20859 | int len; | |
20860 | ||
0a2aaacc KG |
20861 | len = strlen (templ); |
20862 | return (strncmp (section, templ, len) == 0 | |
21d9bb3f PB |
20863 | && (section[len] == 0 || section[len] == '.')); |
20864 | } | |
20865 | ||
c1b7d95a | 20866 | bool |
3101faab | 20867 | rs6000_elf_in_small_data_p (const_tree decl) |
0e5dbd9b DE |
20868 | { |
20869 | if (rs6000_sdata == SDATA_NONE) | |
20870 | return false; | |
20871 | ||
7482ad25 AF |
20872 | /* We want to merge strings, so we never consider them small data. */ |
20873 | if (TREE_CODE (decl) == STRING_CST) | |
20874 | return false; | |
20875 | ||
20876 | /* Functions are never in the small data area. */ | |
20877 | if (TREE_CODE (decl) == FUNCTION_DECL) | |
20878 | return false; | |
20879 | ||
0e5dbd9b DE |
20880 | if (TREE_CODE (decl) == VAR_DECL && DECL_SECTION_NAME (decl)) |
20881 | { | |
20882 | const char *section = TREE_STRING_POINTER (DECL_SECTION_NAME (decl)); | |
ca2ba153 JJ |
20883 | if (compare_section_name (section, ".sdata") |
20884 | || compare_section_name (section, ".sdata2") | |
20885 | || compare_section_name (section, ".gnu.linkonce.s") | |
20886 | || compare_section_name (section, ".sbss") | |
20887 | || compare_section_name (section, ".sbss2") | |
20888 | || compare_section_name (section, ".gnu.linkonce.sb") | |
20bfcd69 GK |
20889 | || strcmp (section, ".PPC.EMB.sdata0") == 0 |
20890 | || strcmp (section, ".PPC.EMB.sbss0") == 0) | |
0e5dbd9b DE |
20891 | return true; |
20892 | } | |
20893 | else | |
20894 | { | |
20895 | HOST_WIDE_INT size = int_size_in_bytes (TREE_TYPE (decl)); | |
20896 | ||
20897 | if (size > 0 | |
307b599c | 20898 | && (unsigned HOST_WIDE_INT) size <= g_switch_value |
20bfcd69 GK |
20899 | /* If it's not public, and we're not going to reference it there, |
20900 | there's no need to put it in the small data section. */ | |
0e5dbd9b DE |
20901 | && (rs6000_sdata != SDATA_DATA || TREE_PUBLIC (decl))) |
20902 | return true; | |
20903 | } | |
20904 | ||
20905 | return false; | |
20906 | } | |
20907 | ||
b91da81f | 20908 | #endif /* USING_ELFOS_H */ |
aacd3885 RS |
20909 | \f |
20910 | /* Implement TARGET_USE_BLOCKS_FOR_CONSTANT_P. */ | |
000034eb | 20911 | |
aacd3885 | 20912 | static bool |
3101faab | 20913 | rs6000_use_blocks_for_constant_p (enum machine_mode mode, const_rtx x) |
aacd3885 RS |
20914 | { |
20915 | return !ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode); | |
20916 | } | |
a6c2a102 | 20917 | \f |
000034eb | 20918 | /* Return a REG that occurs in ADDR with coefficient 1. |
02441cd6 JL |
20919 | ADDR can be effectively incremented by incrementing REG. |
20920 | ||
20921 | r0 is special and we must not select it as an address | |
20922 | register by this routine since our caller will try to | |
20923 | increment the returned register via an "la" instruction. */ | |
000034eb | 20924 | |
9390387d | 20925 | rtx |
a2369ed3 | 20926 | find_addr_reg (rtx addr) |
000034eb DE |
20927 | { |
20928 | while (GET_CODE (addr) == PLUS) | |
20929 | { | |
02441cd6 JL |
20930 | if (GET_CODE (XEXP (addr, 0)) == REG |
20931 | && REGNO (XEXP (addr, 0)) != 0) | |
000034eb | 20932 | addr = XEXP (addr, 0); |
02441cd6 JL |
20933 | else if (GET_CODE (XEXP (addr, 1)) == REG |
20934 | && REGNO (XEXP (addr, 1)) != 0) | |
000034eb DE |
20935 | addr = XEXP (addr, 1); |
20936 | else if (CONSTANT_P (XEXP (addr, 0))) | |
20937 | addr = XEXP (addr, 1); | |
20938 | else if (CONSTANT_P (XEXP (addr, 1))) | |
20939 | addr = XEXP (addr, 0); | |
20940 | else | |
37409796 | 20941 | gcc_unreachable (); |
000034eb | 20942 | } |
37409796 NS |
20943 | gcc_assert (GET_CODE (addr) == REG && REGNO (addr) != 0); |
20944 | return addr; | |
000034eb DE |
20945 | } |
20946 | ||
a6c2a102 | 20947 | void |
a2369ed3 | 20948 | rs6000_fatal_bad_address (rtx op) |
a6c2a102 DE |
20949 | { |
20950 | fatal_insn ("bad address", op); | |
20951 | } | |
c8023011 | 20952 | |
ee890fe2 SS |
20953 | #if TARGET_MACHO |
20954 | ||
efdba735 | 20955 | static tree branch_island_list = 0; |
ee890fe2 | 20956 | |
efdba735 SH |
20957 | /* Remember to generate a branch island for far calls to the given |
20958 | function. */ | |
ee890fe2 | 20959 | |
f676971a | 20960 | static void |
c4ad648e AM |
20961 | add_compiler_branch_island (tree label_name, tree function_name, |
20962 | int line_number) | |
ee890fe2 | 20963 | { |
efdba735 | 20964 | tree branch_island = build_tree_list (function_name, label_name); |
7d60be94 | 20965 | TREE_TYPE (branch_island) = build_int_cst (NULL_TREE, line_number); |
efdba735 SH |
20966 | TREE_CHAIN (branch_island) = branch_island_list; |
20967 | branch_island_list = branch_island; | |
ee890fe2 SS |
20968 | } |
20969 | ||
efdba735 SH |
20970 | #define BRANCH_ISLAND_LABEL_NAME(BRANCH_ISLAND) TREE_VALUE (BRANCH_ISLAND) |
20971 | #define BRANCH_ISLAND_FUNCTION_NAME(BRANCH_ISLAND) TREE_PURPOSE (BRANCH_ISLAND) | |
20972 | #define BRANCH_ISLAND_LINE_NUMBER(BRANCH_ISLAND) \ | |
20973 | TREE_INT_CST_LOW (TREE_TYPE (BRANCH_ISLAND)) | |
ee890fe2 | 20974 | |
efdba735 SH |
20975 | /* Generate far-jump branch islands for everything on the |
20976 | branch_island_list. Invoked immediately after the last instruction | |
20977 | of the epilogue has been emitted; the branch-islands must be | |
20978 | appended to, and contiguous with, the function body. Mach-O stubs | |
20979 | are generated in machopic_output_stub(). */ | |
ee890fe2 | 20980 | |
efdba735 SH |
20981 | static void |
20982 | macho_branch_islands (void) | |
20983 | { | |
20984 | char tmp_buf[512]; | |
20985 | tree branch_island; | |
20986 | ||
20987 | for (branch_island = branch_island_list; | |
20988 | branch_island; | |
20989 | branch_island = TREE_CHAIN (branch_island)) | |
20990 | { | |
20991 | const char *label = | |
20992 | IDENTIFIER_POINTER (BRANCH_ISLAND_LABEL_NAME (branch_island)); | |
20993 | const char *name = | |
11abc112 | 20994 | IDENTIFIER_POINTER (BRANCH_ISLAND_FUNCTION_NAME (branch_island)); |
efdba735 SH |
20995 | char name_buf[512]; |
20996 | /* Cheap copy of the details from the Darwin ASM_OUTPUT_LABELREF(). */ | |
20997 | if (name[0] == '*' || name[0] == '&') | |
20998 | strcpy (name_buf, name+1); | |
20999 | else | |
21000 | { | |
21001 | name_buf[0] = '_'; | |
21002 | strcpy (name_buf+1, name); | |
21003 | } | |
21004 | strcpy (tmp_buf, "\n"); | |
21005 | strcat (tmp_buf, label); | |
ee890fe2 | 21006 | #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO) |
efdba735 | 21007 | if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG) |
93a27b7b | 21008 | dbxout_stabd (N_SLINE, BRANCH_ISLAND_LINE_NUMBER (branch_island)); |
ee890fe2 | 21009 | #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */ |
efdba735 SH |
21010 | if (flag_pic) |
21011 | { | |
21012 | strcat (tmp_buf, ":\n\tmflr r0\n\tbcl 20,31,"); | |
21013 | strcat (tmp_buf, label); | |
21014 | strcat (tmp_buf, "_pic\n"); | |
21015 | strcat (tmp_buf, label); | |
21016 | strcat (tmp_buf, "_pic:\n\tmflr r11\n"); | |
f676971a | 21017 | |
efdba735 SH |
21018 | strcat (tmp_buf, "\taddis r11,r11,ha16("); |
21019 | strcat (tmp_buf, name_buf); | |
21020 | strcat (tmp_buf, " - "); | |
21021 | strcat (tmp_buf, label); | |
21022 | strcat (tmp_buf, "_pic)\n"); | |
f676971a | 21023 | |
efdba735 | 21024 | strcat (tmp_buf, "\tmtlr r0\n"); |
f676971a | 21025 | |
efdba735 SH |
21026 | strcat (tmp_buf, "\taddi r12,r11,lo16("); |
21027 | strcat (tmp_buf, name_buf); | |
21028 | strcat (tmp_buf, " - "); | |
21029 | strcat (tmp_buf, label); | |
21030 | strcat (tmp_buf, "_pic)\n"); | |
f676971a | 21031 | |
efdba735 SH |
21032 | strcat (tmp_buf, "\tmtctr r12\n\tbctr\n"); |
21033 | } | |
21034 | else | |
21035 | { | |
21036 | strcat (tmp_buf, ":\nlis r12,hi16("); | |
21037 | strcat (tmp_buf, name_buf); | |
21038 | strcat (tmp_buf, ")\n\tori r12,r12,lo16("); | |
21039 | strcat (tmp_buf, name_buf); | |
21040 | strcat (tmp_buf, ")\n\tmtctr r12\n\tbctr"); | |
21041 | } | |
21042 | output_asm_insn (tmp_buf, 0); | |
ee890fe2 | 21043 | #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO) |
efdba735 | 21044 | if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG) |
93a27b7b | 21045 | dbxout_stabd (N_SLINE, BRANCH_ISLAND_LINE_NUMBER (branch_island)); |
ee890fe2 | 21046 | #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */ |
efdba735 | 21047 | } |
ee890fe2 | 21048 | |
efdba735 | 21049 | branch_island_list = 0; |
ee890fe2 SS |
21050 | } |
21051 | ||
21052 | /* NO_PREVIOUS_DEF checks in the link list whether the function name is | |
21053 | already there or not. */ | |
21054 | ||
efdba735 | 21055 | static int |
a2369ed3 | 21056 | no_previous_def (tree function_name) |
ee890fe2 | 21057 | { |
efdba735 SH |
21058 | tree branch_island; |
21059 | for (branch_island = branch_island_list; | |
21060 | branch_island; | |
21061 | branch_island = TREE_CHAIN (branch_island)) | |
21062 | if (function_name == BRANCH_ISLAND_FUNCTION_NAME (branch_island)) | |
ee890fe2 SS |
21063 | return 0; |
21064 | return 1; | |
21065 | } | |
21066 | ||
21067 | /* GET_PREV_LABEL gets the label name from the previous definition of | |
21068 | the function. */ | |
21069 | ||
efdba735 | 21070 | static tree |
a2369ed3 | 21071 | get_prev_label (tree function_name) |
ee890fe2 | 21072 | { |
efdba735 SH |
21073 | tree branch_island; |
21074 | for (branch_island = branch_island_list; | |
21075 | branch_island; | |
21076 | branch_island = TREE_CHAIN (branch_island)) | |
21077 | if (function_name == BRANCH_ISLAND_FUNCTION_NAME (branch_island)) | |
21078 | return BRANCH_ISLAND_LABEL_NAME (branch_island); | |
ee890fe2 SS |
21079 | return 0; |
21080 | } | |
21081 | ||
75b1b789 MS |
21082 | #ifndef DARWIN_LINKER_GENERATES_ISLANDS |
21083 | #define DARWIN_LINKER_GENERATES_ISLANDS 0 | |
21084 | #endif | |
21085 | ||
21086 | /* KEXTs still need branch islands. */ | |
21087 | #define DARWIN_GENERATE_ISLANDS (!DARWIN_LINKER_GENERATES_ISLANDS \ | |
21088 | || flag_mkernel || flag_apple_kext) | |
21089 | ||
ee890fe2 | 21090 | /* INSN is either a function call or a millicode call. It may have an |
f676971a | 21091 | unconditional jump in its delay slot. |
ee890fe2 SS |
21092 | |
21093 | CALL_DEST is the routine we are calling. */ | |
21094 | ||
21095 | char * | |
c4ad648e AM |
21096 | output_call (rtx insn, rtx *operands, int dest_operand_number, |
21097 | int cookie_operand_number) | |
ee890fe2 SS |
21098 | { |
21099 | static char buf[256]; | |
75b1b789 MS |
21100 | if (DARWIN_GENERATE_ISLANDS |
21101 | && GET_CODE (operands[dest_operand_number]) == SYMBOL_REF | |
efdba735 | 21102 | && (INTVAL (operands[cookie_operand_number]) & CALL_LONG)) |
ee890fe2 SS |
21103 | { |
21104 | tree labelname; | |
efdba735 | 21105 | tree funname = get_identifier (XSTR (operands[dest_operand_number], 0)); |
f676971a | 21106 | |
ee890fe2 SS |
21107 | if (no_previous_def (funname)) |
21108 | { | |
ee890fe2 SS |
21109 | rtx label_rtx = gen_label_rtx (); |
21110 | char *label_buf, temp_buf[256]; | |
21111 | ASM_GENERATE_INTERNAL_LABEL (temp_buf, "L", | |
21112 | CODE_LABEL_NUMBER (label_rtx)); | |
21113 | label_buf = temp_buf[0] == '*' ? temp_buf + 1 : temp_buf; | |
21114 | labelname = get_identifier (label_buf); | |
a38e7aa5 | 21115 | add_compiler_branch_island (labelname, funname, insn_line (insn)); |
ee890fe2 SS |
21116 | } |
21117 | else | |
21118 | labelname = get_prev_label (funname); | |
21119 | ||
efdba735 SH |
21120 | /* "jbsr foo, L42" is Mach-O for "Link as 'bl foo' if a 'bl' |
21121 | instruction will reach 'foo', otherwise link as 'bl L42'". | |
21122 | "L42" should be a 'branch island', that will do a far jump to | |
21123 | 'foo'. Branch islands are generated in | |
21124 | macho_branch_islands(). */ | |
ee890fe2 | 21125 | sprintf (buf, "jbsr %%z%d,%.246s", |
efdba735 | 21126 | dest_operand_number, IDENTIFIER_POINTER (labelname)); |
ee890fe2 SS |
21127 | } |
21128 | else | |
efdba735 SH |
21129 | sprintf (buf, "bl %%z%d", dest_operand_number); |
21130 | return buf; | |
ee890fe2 SS |
21131 | } |
21132 | ||
ee890fe2 SS |
21133 | /* Generate PIC and indirect symbol stubs. */ |
21134 | ||
21135 | void | |
a2369ed3 | 21136 | machopic_output_stub (FILE *file, const char *symb, const char *stub) |
ee890fe2 SS |
21137 | { |
21138 | unsigned int length; | |
a4f6c312 SS |
21139 | char *symbol_name, *lazy_ptr_name; |
21140 | char *local_label_0; | |
ee890fe2 SS |
21141 | static int label = 0; |
21142 | ||
df56a27f | 21143 | /* Lose our funky encoding stuff so it doesn't contaminate the stub. */ |
772c5265 | 21144 | symb = (*targetm.strip_name_encoding) (symb); |
df56a27f | 21145 | |
ee890fe2 | 21146 | |
ee890fe2 | 21147 | length = strlen (symb); |
5ead67f6 | 21148 | symbol_name = XALLOCAVEC (char, length + 32); |
ee890fe2 SS |
21149 | GEN_SYMBOL_NAME_FOR_SYMBOL (symbol_name, symb, length); |
21150 | ||
5ead67f6 | 21151 | lazy_ptr_name = XALLOCAVEC (char, length + 32); |
ee890fe2 SS |
21152 | GEN_LAZY_PTR_NAME_FOR_SYMBOL (lazy_ptr_name, symb, length); |
21153 | ||
ee890fe2 | 21154 | if (flag_pic == 2) |
56c779bc | 21155 | switch_to_section (darwin_sections[machopic_picsymbol_stub1_section]); |
ee890fe2 | 21156 | else |
56c779bc | 21157 | switch_to_section (darwin_sections[machopic_symbol_stub1_section]); |
ee890fe2 SS |
21158 | |
21159 | if (flag_pic == 2) | |
21160 | { | |
d974312d DJ |
21161 | fprintf (file, "\t.align 5\n"); |
21162 | ||
21163 | fprintf (file, "%s:\n", stub); | |
21164 | fprintf (file, "\t.indirect_symbol %s\n", symbol_name); | |
21165 | ||
876455fa | 21166 | label++; |
5ead67f6 | 21167 | local_label_0 = XALLOCAVEC (char, sizeof ("\"L00000000000$spb\"")); |
876455fa | 21168 | sprintf (local_label_0, "\"L%011d$spb\"", label); |
f676971a | 21169 | |
ee890fe2 SS |
21170 | fprintf (file, "\tmflr r0\n"); |
21171 | fprintf (file, "\tbcl 20,31,%s\n", local_label_0); | |
21172 | fprintf (file, "%s:\n\tmflr r11\n", local_label_0); | |
21173 | fprintf (file, "\taddis r11,r11,ha16(%s-%s)\n", | |
21174 | lazy_ptr_name, local_label_0); | |
21175 | fprintf (file, "\tmtlr r0\n"); | |
3d0e2d58 SS |
21176 | fprintf (file, "\t%s r12,lo16(%s-%s)(r11)\n", |
21177 | (TARGET_64BIT ? "ldu" : "lwzu"), | |
ee890fe2 SS |
21178 | lazy_ptr_name, local_label_0); |
21179 | fprintf (file, "\tmtctr r12\n"); | |
ee890fe2 SS |
21180 | fprintf (file, "\tbctr\n"); |
21181 | } | |
21182 | else | |
d974312d DJ |
21183 | { |
21184 | fprintf (file, "\t.align 4\n"); | |
21185 | ||
21186 | fprintf (file, "%s:\n", stub); | |
21187 | fprintf (file, "\t.indirect_symbol %s\n", symbol_name); | |
21188 | ||
21189 | fprintf (file, "\tlis r11,ha16(%s)\n", lazy_ptr_name); | |
d9e4e4f5 SS |
21190 | fprintf (file, "\t%s r12,lo16(%s)(r11)\n", |
21191 | (TARGET_64BIT ? "ldu" : "lwzu"), | |
21192 | lazy_ptr_name); | |
d974312d DJ |
21193 | fprintf (file, "\tmtctr r12\n"); |
21194 | fprintf (file, "\tbctr\n"); | |
21195 | } | |
f676971a | 21196 | |
56c779bc | 21197 | switch_to_section (darwin_sections[machopic_lazy_symbol_ptr_section]); |
ee890fe2 SS |
21198 | fprintf (file, "%s:\n", lazy_ptr_name); |
21199 | fprintf (file, "\t.indirect_symbol %s\n", symbol_name); | |
49bd1d27 SS |
21200 | fprintf (file, "%sdyld_stub_binding_helper\n", |
21201 | (TARGET_64BIT ? DOUBLE_INT_ASM_OP : "\t.long\t")); | |
ee890fe2 SS |
21202 | } |
21203 | ||
21204 | /* Legitimize PIC addresses. If the address is already | |
21205 | position-independent, we return ORIG. Newly generated | |
21206 | position-independent addresses go into a reg. This is REG if non | |
21207 | zero, otherwise we allocate register(s) as necessary. */ | |
21208 | ||
4fbbe694 | 21209 | #define SMALL_INT(X) ((UINTVAL (X) + 0x8000) < 0x10000) |
ee890fe2 SS |
21210 | |
21211 | rtx | |
f676971a | 21212 | rs6000_machopic_legitimize_pic_address (rtx orig, enum machine_mode mode, |
a2369ed3 | 21213 | rtx reg) |
ee890fe2 SS |
21214 | { |
21215 | rtx base, offset; | |
21216 | ||
21217 | if (reg == NULL && ! reload_in_progress && ! reload_completed) | |
21218 | reg = gen_reg_rtx (Pmode); | |
21219 | ||
21220 | if (GET_CODE (orig) == CONST) | |
21221 | { | |
37409796 NS |
21222 | rtx reg_temp; |
21223 | ||
ee890fe2 SS |
21224 | if (GET_CODE (XEXP (orig, 0)) == PLUS |
21225 | && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx) | |
21226 | return orig; | |
21227 | ||
37409796 | 21228 | gcc_assert (GET_CODE (XEXP (orig, 0)) == PLUS); |
bb8df8a6 | 21229 | |
37409796 NS |
21230 | /* Use a different reg for the intermediate value, as |
21231 | it will be marked UNCHANGING. */ | |
b3a13419 | 21232 | reg_temp = !can_create_pseudo_p () ? reg : gen_reg_rtx (Pmode); |
37409796 NS |
21233 | base = rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 0), |
21234 | Pmode, reg_temp); | |
21235 | offset = | |
21236 | rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 1), | |
21237 | Pmode, reg); | |
bb8df8a6 | 21238 | |
ee890fe2 SS |
21239 | if (GET_CODE (offset) == CONST_INT) |
21240 | { | |
21241 | if (SMALL_INT (offset)) | |
ed8908e7 | 21242 | return plus_constant (base, INTVAL (offset)); |
ee890fe2 SS |
21243 | else if (! reload_in_progress && ! reload_completed) |
21244 | offset = force_reg (Pmode, offset); | |
21245 | else | |
c859cda6 DJ |
21246 | { |
21247 | rtx mem = force_const_mem (Pmode, orig); | |
21248 | return machopic_legitimize_pic_address (mem, Pmode, reg); | |
21249 | } | |
ee890fe2 | 21250 | } |
f1c25d3b | 21251 | return gen_rtx_PLUS (Pmode, base, offset); |
ee890fe2 SS |
21252 | } |
21253 | ||
21254 | /* Fall back on generic machopic code. */ | |
21255 | return machopic_legitimize_pic_address (orig, mode, reg); | |
21256 | } | |
21257 | ||
c4e18b1c GK |
21258 | /* Output a .machine directive for the Darwin assembler, and call |
21259 | the generic start_file routine. */ | |
21260 | ||
21261 | static void | |
21262 | rs6000_darwin_file_start (void) | |
21263 | { | |
94ff898d | 21264 | static const struct |
c4e18b1c GK |
21265 | { |
21266 | const char *arg; | |
21267 | const char *name; | |
21268 | int if_set; | |
21269 | } mapping[] = { | |
55dbfb48 | 21270 | { "ppc64", "ppc64", MASK_64BIT }, |
c4e18b1c GK |
21271 | { "970", "ppc970", MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64 }, |
21272 | { "power4", "ppc970", 0 }, | |
21273 | { "G5", "ppc970", 0 }, | |
21274 | { "7450", "ppc7450", 0 }, | |
21275 | { "7400", "ppc7400", MASK_ALTIVEC }, | |
21276 | { "G4", "ppc7400", 0 }, | |
21277 | { "750", "ppc750", 0 }, | |
21278 | { "740", "ppc750", 0 }, | |
21279 | { "G3", "ppc750", 0 }, | |
21280 | { "604e", "ppc604e", 0 }, | |
21281 | { "604", "ppc604", 0 }, | |
21282 | { "603e", "ppc603", 0 }, | |
21283 | { "603", "ppc603", 0 }, | |
21284 | { "601", "ppc601", 0 }, | |
21285 | { NULL, "ppc", 0 } }; | |
21286 | const char *cpu_id = ""; | |
21287 | size_t i; | |
94ff898d | 21288 | |
9390387d | 21289 | rs6000_file_start (); |
192d0f89 | 21290 | darwin_file_start (); |
c4e18b1c GK |
21291 | |
21292 | /* Determine the argument to -mcpu=. Default to G3 if not specified. */ | |
21293 | for (i = 0; i < ARRAY_SIZE (rs6000_select); i++) | |
21294 | if (rs6000_select[i].set_arch_p && rs6000_select[i].string | |
21295 | && rs6000_select[i].string[0] != '\0') | |
21296 | cpu_id = rs6000_select[i].string; | |
21297 | ||
21298 | /* Look through the mapping array. Pick the first name that either | |
21299 | matches the argument, has a bit set in IF_SET that is also set | |
21300 | in the target flags, or has a NULL name. */ | |
21301 | ||
21302 | i = 0; | |
21303 | while (mapping[i].arg != NULL | |
21304 | && strcmp (mapping[i].arg, cpu_id) != 0 | |
21305 | && (mapping[i].if_set & target_flags) == 0) | |
21306 | i++; | |
21307 | ||
21308 | fprintf (asm_out_file, "\t.machine %s\n", mapping[i].name); | |
21309 | } | |
21310 | ||
ee890fe2 | 21311 | #endif /* TARGET_MACHO */ |
7c262518 RH |
21312 | |
21313 | #if TARGET_ELF | |
9b580a0b RH |
21314 | static int |
21315 | rs6000_elf_reloc_rw_mask (void) | |
7c262518 | 21316 | { |
9b580a0b RH |
21317 | if (flag_pic) |
21318 | return 3; | |
21319 | else if (DEFAULT_ABI == ABI_AIX) | |
21320 | return 2; | |
21321 | else | |
21322 | return 0; | |
7c262518 | 21323 | } |
d9f6800d RH |
21324 | |
21325 | /* Record an element in the table of global constructors. SYMBOL is | |
21326 | a SYMBOL_REF of the function to be called; PRIORITY is a number | |
21327 | between 0 and MAX_INIT_PRIORITY. | |
21328 | ||
21329 | This differs from default_named_section_asm_out_constructor in | |
21330 | that we have special handling for -mrelocatable. */ | |
21331 | ||
21332 | static void | |
a2369ed3 | 21333 | rs6000_elf_asm_out_constructor (rtx symbol, int priority) |
d9f6800d RH |
21334 | { |
21335 | const char *section = ".ctors"; | |
21336 | char buf[16]; | |
21337 | ||
21338 | if (priority != DEFAULT_INIT_PRIORITY) | |
21339 | { | |
21340 | sprintf (buf, ".ctors.%.5u", | |
c4ad648e AM |
21341 | /* Invert the numbering so the linker puts us in the proper |
21342 | order; constructors are run from right to left, and the | |
21343 | linker sorts in increasing order. */ | |
21344 | MAX_INIT_PRIORITY - priority); | |
d9f6800d RH |
21345 | section = buf; |
21346 | } | |
21347 | ||
d6b5193b | 21348 | switch_to_section (get_section (section, SECTION_WRITE, NULL)); |
715bdd29 | 21349 | assemble_align (POINTER_SIZE); |
d9f6800d RH |
21350 | |
21351 | if (TARGET_RELOCATABLE) | |
21352 | { | |
21353 | fputs ("\t.long (", asm_out_file); | |
21354 | output_addr_const (asm_out_file, symbol); | |
21355 | fputs (")@fixup\n", asm_out_file); | |
21356 | } | |
21357 | else | |
c8af3574 | 21358 | assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1); |
d9f6800d RH |
21359 | } |
21360 | ||
21361 | static void | |
a2369ed3 | 21362 | rs6000_elf_asm_out_destructor (rtx symbol, int priority) |
d9f6800d RH |
21363 | { |
21364 | const char *section = ".dtors"; | |
21365 | char buf[16]; | |
21366 | ||
21367 | if (priority != DEFAULT_INIT_PRIORITY) | |
21368 | { | |
21369 | sprintf (buf, ".dtors.%.5u", | |
c4ad648e AM |
21370 | /* Invert the numbering so the linker puts us in the proper |
21371 | order; constructors are run from right to left, and the | |
21372 | linker sorts in increasing order. */ | |
21373 | MAX_INIT_PRIORITY - priority); | |
d9f6800d RH |
21374 | section = buf; |
21375 | } | |
21376 | ||
d6b5193b | 21377 | switch_to_section (get_section (section, SECTION_WRITE, NULL)); |
715bdd29 | 21378 | assemble_align (POINTER_SIZE); |
d9f6800d RH |
21379 | |
21380 | if (TARGET_RELOCATABLE) | |
21381 | { | |
21382 | fputs ("\t.long (", asm_out_file); | |
21383 | output_addr_const (asm_out_file, symbol); | |
21384 | fputs (")@fixup\n", asm_out_file); | |
21385 | } | |
21386 | else | |
c8af3574 | 21387 | assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1); |
d9f6800d | 21388 | } |
9739c90c JJ |
21389 | |
21390 | void | |
a2369ed3 | 21391 | rs6000_elf_declare_function_name (FILE *file, const char *name, tree decl) |
9739c90c JJ |
21392 | { |
21393 | if (TARGET_64BIT) | |
21394 | { | |
21395 | fputs ("\t.section\t\".opd\",\"aw\"\n\t.align 3\n", file); | |
21396 | ASM_OUTPUT_LABEL (file, name); | |
21397 | fputs (DOUBLE_INT_ASM_OP, file); | |
85b776df AM |
21398 | rs6000_output_function_entry (file, name); |
21399 | fputs (",.TOC.@tocbase,0\n\t.previous\n", file); | |
21400 | if (DOT_SYMBOLS) | |
9739c90c | 21401 | { |
85b776df | 21402 | fputs ("\t.size\t", file); |
9739c90c | 21403 | assemble_name (file, name); |
85b776df AM |
21404 | fputs (",24\n\t.type\t.", file); |
21405 | assemble_name (file, name); | |
21406 | fputs (",@function\n", file); | |
21407 | if (TREE_PUBLIC (decl) && ! DECL_WEAK (decl)) | |
21408 | { | |
21409 | fputs ("\t.globl\t.", file); | |
21410 | assemble_name (file, name); | |
21411 | putc ('\n', file); | |
21412 | } | |
9739c90c | 21413 | } |
85b776df AM |
21414 | else |
21415 | ASM_OUTPUT_TYPE_DIRECTIVE (file, name, "function"); | |
9739c90c | 21416 | ASM_DECLARE_RESULT (file, DECL_RESULT (decl)); |
85b776df AM |
21417 | rs6000_output_function_entry (file, name); |
21418 | fputs (":\n", file); | |
9739c90c JJ |
21419 | return; |
21420 | } | |
21421 | ||
21422 | if (TARGET_RELOCATABLE | |
7f970b70 | 21423 | && !TARGET_SECURE_PLT |
e3b5732b | 21424 | && (get_pool_size () != 0 || crtl->profile) |
3c9eb5f4 | 21425 | && uses_TOC ()) |
9739c90c JJ |
21426 | { |
21427 | char buf[256]; | |
21428 | ||
21429 | (*targetm.asm_out.internal_label) (file, "LCL", rs6000_pic_labelno); | |
21430 | ||
21431 | ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1); | |
21432 | fprintf (file, "\t.long "); | |
21433 | assemble_name (file, buf); | |
21434 | putc ('-', file); | |
21435 | ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno); | |
21436 | assemble_name (file, buf); | |
21437 | putc ('\n', file); | |
21438 | } | |
21439 | ||
21440 | ASM_OUTPUT_TYPE_DIRECTIVE (file, name, "function"); | |
21441 | ASM_DECLARE_RESULT (file, DECL_RESULT (decl)); | |
21442 | ||
21443 | if (DEFAULT_ABI == ABI_AIX) | |
21444 | { | |
21445 | const char *desc_name, *orig_name; | |
21446 | ||
21447 | orig_name = (*targetm.strip_name_encoding) (name); | |
21448 | desc_name = orig_name; | |
21449 | while (*desc_name == '.') | |
21450 | desc_name++; | |
21451 | ||
21452 | if (TREE_PUBLIC (decl)) | |
21453 | fprintf (file, "\t.globl %s\n", desc_name); | |
21454 | ||
21455 | fprintf (file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP); | |
21456 | fprintf (file, "%s:\n", desc_name); | |
21457 | fprintf (file, "\t.long %s\n", orig_name); | |
21458 | fputs ("\t.long _GLOBAL_OFFSET_TABLE_\n", file); | |
21459 | if (DEFAULT_ABI == ABI_AIX) | |
21460 | fputs ("\t.long 0\n", file); | |
21461 | fprintf (file, "\t.previous\n"); | |
21462 | } | |
21463 | ASM_OUTPUT_LABEL (file, name); | |
21464 | } | |
1334b570 AM |
21465 | |
21466 | static void | |
21467 | rs6000_elf_end_indicate_exec_stack (void) | |
21468 | { | |
21469 | if (TARGET_32BIT) | |
21470 | file_end_indicate_exec_stack (); | |
21471 | } | |
7c262518 RH |
21472 | #endif |
21473 | ||
cbaaba19 | 21474 | #if TARGET_XCOFF |
0d5817b2 DE |
21475 | static void |
21476 | rs6000_xcoff_asm_output_anchor (rtx symbol) | |
21477 | { | |
21478 | char buffer[100]; | |
21479 | ||
21480 | sprintf (buffer, "$ + " HOST_WIDE_INT_PRINT_DEC, | |
21481 | SYMBOL_REF_BLOCK_OFFSET (symbol)); | |
21482 | ASM_OUTPUT_DEF (asm_out_file, XSTR (symbol, 0), buffer); | |
21483 | } | |
21484 | ||
7c262518 | 21485 | static void |
a2369ed3 | 21486 | rs6000_xcoff_asm_globalize_label (FILE *stream, const char *name) |
b275d088 DE |
21487 | { |
21488 | fputs (GLOBAL_ASM_OP, stream); | |
21489 | RS6000_OUTPUT_BASENAME (stream, name); | |
21490 | putc ('\n', stream); | |
21491 | } | |
21492 | ||
d6b5193b RS |
21493 | /* A get_unnamed_decl callback, used for read-only sections. PTR |
21494 | points to the section string variable. */ | |
21495 | ||
21496 | static void | |
21497 | rs6000_xcoff_output_readonly_section_asm_op (const void *directive) | |
21498 | { | |
890f9edf OH |
21499 | fprintf (asm_out_file, "\t.csect %s[RO],%s\n", |
21500 | *(const char *const *) directive, | |
21501 | XCOFF_CSECT_DEFAULT_ALIGNMENT_STR); | |
d6b5193b RS |
21502 | } |
21503 | ||
21504 | /* Likewise for read-write sections. */ | |
21505 | ||
21506 | static void | |
21507 | rs6000_xcoff_output_readwrite_section_asm_op (const void *directive) | |
21508 | { | |
890f9edf OH |
21509 | fprintf (asm_out_file, "\t.csect %s[RW],%s\n", |
21510 | *(const char *const *) directive, | |
21511 | XCOFF_CSECT_DEFAULT_ALIGNMENT_STR); | |
d6b5193b RS |
21512 | } |
21513 | ||
21514 | /* A get_unnamed_section callback, used for switching to toc_section. */ | |
21515 | ||
21516 | static void | |
21517 | rs6000_xcoff_output_toc_section_asm_op (const void *data ATTRIBUTE_UNUSED) | |
21518 | { | |
21519 | if (TARGET_MINIMAL_TOC) | |
21520 | { | |
21521 | /* toc_section is always selected at least once from | |
21522 | rs6000_xcoff_file_start, so this is guaranteed to | |
21523 | always be defined once and only once in each file. */ | |
21524 | if (!toc_initialized) | |
21525 | { | |
21526 | fputs ("\t.toc\nLCTOC..1:\n", asm_out_file); | |
21527 | fputs ("\t.tc toc_table[TC],toc_table[RW]\n", asm_out_file); | |
21528 | toc_initialized = 1; | |
21529 | } | |
21530 | fprintf (asm_out_file, "\t.csect toc_table[RW]%s\n", | |
21531 | (TARGET_32BIT ? "" : ",3")); | |
21532 | } | |
21533 | else | |
21534 | fputs ("\t.toc\n", asm_out_file); | |
21535 | } | |
21536 | ||
21537 | /* Implement TARGET_ASM_INIT_SECTIONS. */ | |
21538 | ||
21539 | static void | |
21540 | rs6000_xcoff_asm_init_sections (void) | |
21541 | { | |
21542 | read_only_data_section | |
21543 | = get_unnamed_section (0, rs6000_xcoff_output_readonly_section_asm_op, | |
21544 | &xcoff_read_only_section_name); | |
21545 | ||
21546 | private_data_section | |
21547 | = get_unnamed_section (SECTION_WRITE, | |
21548 | rs6000_xcoff_output_readwrite_section_asm_op, | |
21549 | &xcoff_private_data_section_name); | |
21550 | ||
21551 | read_only_private_data_section | |
21552 | = get_unnamed_section (0, rs6000_xcoff_output_readonly_section_asm_op, | |
21553 | &xcoff_private_data_section_name); | |
21554 | ||
21555 | toc_section | |
21556 | = get_unnamed_section (0, rs6000_xcoff_output_toc_section_asm_op, NULL); | |
21557 | ||
21558 | readonly_data_section = read_only_data_section; | |
21559 | exception_section = data_section; | |
21560 | } | |
21561 | ||
9b580a0b RH |
21562 | static int |
21563 | rs6000_xcoff_reloc_rw_mask (void) | |
21564 | { | |
21565 | return 3; | |
21566 | } | |
21567 | ||
b275d088 | 21568 | static void |
c18a5b6c MM |
21569 | rs6000_xcoff_asm_named_section (const char *name, unsigned int flags, |
21570 | tree decl ATTRIBUTE_UNUSED) | |
7c262518 | 21571 | { |
0e5dbd9b DE |
21572 | int smclass; |
21573 | static const char * const suffix[3] = { "PR", "RO", "RW" }; | |
21574 | ||
21575 | if (flags & SECTION_CODE) | |
21576 | smclass = 0; | |
21577 | else if (flags & SECTION_WRITE) | |
21578 | smclass = 2; | |
21579 | else | |
21580 | smclass = 1; | |
21581 | ||
5b5198f7 | 21582 | fprintf (asm_out_file, "\t.csect %s%s[%s],%u\n", |
0e5dbd9b | 21583 | (flags & SECTION_CODE) ? "." : "", |
5b5198f7 | 21584 | name, suffix[smclass], flags & SECTION_ENTSIZE); |
7c262518 | 21585 | } |
ae46c4e0 | 21586 | |
d6b5193b | 21587 | static section * |
f676971a | 21588 | rs6000_xcoff_select_section (tree decl, int reloc, |
c4ad648e | 21589 | unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED) |
ae46c4e0 | 21590 | { |
9b580a0b | 21591 | if (decl_readonly_section (decl, reloc)) |
ae46c4e0 | 21592 | { |
0e5dbd9b | 21593 | if (TREE_PUBLIC (decl)) |
d6b5193b | 21594 | return read_only_data_section; |
ae46c4e0 | 21595 | else |
d6b5193b | 21596 | return read_only_private_data_section; |
ae46c4e0 RH |
21597 | } |
21598 | else | |
21599 | { | |
0e5dbd9b | 21600 | if (TREE_PUBLIC (decl)) |
d6b5193b | 21601 | return data_section; |
ae46c4e0 | 21602 | else |
d6b5193b | 21603 | return private_data_section; |
ae46c4e0 RH |
21604 | } |
21605 | } | |
21606 | ||
21607 | static void | |
a2369ed3 | 21608 | rs6000_xcoff_unique_section (tree decl, int reloc ATTRIBUTE_UNUSED) |
ae46c4e0 RH |
21609 | { |
21610 | const char *name; | |
ae46c4e0 | 21611 | |
5b5198f7 DE |
21612 | /* Use select_section for private and uninitialized data. */ |
21613 | if (!TREE_PUBLIC (decl) | |
21614 | || DECL_COMMON (decl) | |
0e5dbd9b DE |
21615 | || DECL_INITIAL (decl) == NULL_TREE |
21616 | || DECL_INITIAL (decl) == error_mark_node | |
21617 | || (flag_zero_initialized_in_bss | |
21618 | && initializer_zerop (DECL_INITIAL (decl)))) | |
21619 | return; | |
21620 | ||
21621 | name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl)); | |
21622 | name = (*targetm.strip_name_encoding) (name); | |
21623 | DECL_SECTION_NAME (decl) = build_string (strlen (name), name); | |
ae46c4e0 | 21624 | } |
b64a1b53 | 21625 | |
fb49053f RH |
21626 | /* Select section for constant in constant pool. |
21627 | ||
21628 | On RS/6000, all constants are in the private read-only data area. | |
21629 | However, if this is being placed in the TOC it must be output as a | |
21630 | toc entry. */ | |
21631 | ||
d6b5193b | 21632 | static section * |
f676971a | 21633 | rs6000_xcoff_select_rtx_section (enum machine_mode mode, rtx x, |
c4ad648e | 21634 | unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED) |
b64a1b53 RH |
21635 | { |
21636 | if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode)) | |
d6b5193b | 21637 | return toc_section; |
b64a1b53 | 21638 | else |
d6b5193b | 21639 | return read_only_private_data_section; |
b64a1b53 | 21640 | } |
772c5265 RH |
21641 | |
21642 | /* Remove any trailing [DS] or the like from the symbol name. */ | |
21643 | ||
21644 | static const char * | |
a2369ed3 | 21645 | rs6000_xcoff_strip_name_encoding (const char *name) |
772c5265 RH |
21646 | { |
21647 | size_t len; | |
21648 | if (*name == '*') | |
21649 | name++; | |
21650 | len = strlen (name); | |
21651 | if (name[len - 1] == ']') | |
21652 | return ggc_alloc_string (name, len - 4); | |
21653 | else | |
21654 | return name; | |
21655 | } | |
21656 | ||
5add3202 DE |
21657 | /* Section attributes. AIX is always PIC. */ |
21658 | ||
21659 | static unsigned int | |
a2369ed3 | 21660 | rs6000_xcoff_section_type_flags (tree decl, const char *name, int reloc) |
5add3202 | 21661 | { |
5b5198f7 | 21662 | unsigned int align; |
9b580a0b | 21663 | unsigned int flags = default_section_type_flags (decl, name, reloc); |
5b5198f7 DE |
21664 | |
21665 | /* Align to at least UNIT size. */ | |
21666 | if (flags & SECTION_CODE) | |
21667 | align = MIN_UNITS_PER_WORD; | |
21668 | else | |
21669 | /* Increase alignment of large objects if not already stricter. */ | |
21670 | align = MAX ((DECL_ALIGN (decl) / BITS_PER_UNIT), | |
21671 | int_size_in_bytes (TREE_TYPE (decl)) > MIN_UNITS_PER_WORD | |
21672 | ? UNITS_PER_FP_WORD : MIN_UNITS_PER_WORD); | |
21673 | ||
21674 | return flags | (exact_log2 (align) & SECTION_ENTSIZE); | |
5add3202 | 21675 | } |
a5fe455b | 21676 | |
1bc7c5b6 ZW |
21677 | /* Output at beginning of assembler file. |
21678 | ||
21679 | Initialize the section names for the RS/6000 at this point. | |
21680 | ||
21681 | Specify filename, including full path, to assembler. | |
21682 | ||
21683 | We want to go into the TOC section so at least one .toc will be emitted. | |
21684 | Also, in order to output proper .bs/.es pairs, we need at least one static | |
21685 | [RW] section emitted. | |
21686 | ||
21687 | Finally, declare mcount when profiling to make the assembler happy. */ | |
21688 | ||
21689 | static void | |
863d938c | 21690 | rs6000_xcoff_file_start (void) |
1bc7c5b6 ZW |
21691 | { |
21692 | rs6000_gen_section_name (&xcoff_bss_section_name, | |
21693 | main_input_filename, ".bss_"); | |
21694 | rs6000_gen_section_name (&xcoff_private_data_section_name, | |
21695 | main_input_filename, ".rw_"); | |
21696 | rs6000_gen_section_name (&xcoff_read_only_section_name, | |
21697 | main_input_filename, ".ro_"); | |
21698 | ||
21699 | fputs ("\t.file\t", asm_out_file); | |
21700 | output_quoted_string (asm_out_file, main_input_filename); | |
21701 | fputc ('\n', asm_out_file); | |
1bc7c5b6 | 21702 | if (write_symbols != NO_DEBUG) |
d6b5193b RS |
21703 | switch_to_section (private_data_section); |
21704 | switch_to_section (text_section); | |
1bc7c5b6 ZW |
21705 | if (profile_flag) |
21706 | fprintf (asm_out_file, "\t.extern %s\n", RS6000_MCOUNT); | |
21707 | rs6000_file_start (); | |
21708 | } | |
21709 | ||
a5fe455b ZW |
21710 | /* Output at end of assembler file. |
21711 | On the RS/6000, referencing data should automatically pull in text. */ | |
21712 | ||
21713 | static void | |
863d938c | 21714 | rs6000_xcoff_file_end (void) |
a5fe455b | 21715 | { |
d6b5193b | 21716 | switch_to_section (text_section); |
a5fe455b | 21717 | fputs ("_section_.text:\n", asm_out_file); |
d6b5193b | 21718 | switch_to_section (data_section); |
a5fe455b ZW |
21719 | fputs (TARGET_32BIT |
21720 | ? "\t.long _section_.text\n" : "\t.llong _section_.text\n", | |
21721 | asm_out_file); | |
21722 | } | |
f1384257 | 21723 | #endif /* TARGET_XCOFF */ |
0e5dbd9b | 21724 | |
3c50106f RH |
21725 | /* Compute a (partial) cost for rtx X. Return true if the complete |
21726 | cost has been computed, and false if subexpressions should be | |
21727 | scanned. In either case, *TOTAL contains the cost result. */ | |
21728 | ||
21729 | static bool | |
f40751dd JH |
21730 | rs6000_rtx_costs (rtx x, int code, int outer_code, int *total, |
21731 | bool speed) | |
3c50106f | 21732 | { |
f0517163 RS |
21733 | enum machine_mode mode = GET_MODE (x); |
21734 | ||
3c50106f RH |
21735 | switch (code) |
21736 | { | |
30a555d9 | 21737 | /* On the RS/6000, if it is valid in the insn, it is free. */ |
3c50106f | 21738 | case CONST_INT: |
066cd967 DE |
21739 | if (((outer_code == SET |
21740 | || outer_code == PLUS | |
21741 | || outer_code == MINUS) | |
279bb624 DE |
21742 | && (satisfies_constraint_I (x) |
21743 | || satisfies_constraint_L (x))) | |
066cd967 | 21744 | || (outer_code == AND |
279bb624 DE |
21745 | && (satisfies_constraint_K (x) |
21746 | || (mode == SImode | |
21747 | ? satisfies_constraint_L (x) | |
21748 | : satisfies_constraint_J (x)) | |
1990cd79 AM |
21749 | || mask_operand (x, mode) |
21750 | || (mode == DImode | |
21751 | && mask64_operand (x, DImode)))) | |
22e54023 | 21752 | || ((outer_code == IOR || outer_code == XOR) |
279bb624 DE |
21753 | && (satisfies_constraint_K (x) |
21754 | || (mode == SImode | |
21755 | ? satisfies_constraint_L (x) | |
21756 | : satisfies_constraint_J (x)))) | |
066cd967 DE |
21757 | || outer_code == ASHIFT |
21758 | || outer_code == ASHIFTRT | |
21759 | || outer_code == LSHIFTRT | |
21760 | || outer_code == ROTATE | |
21761 | || outer_code == ROTATERT | |
d5861a7a | 21762 | || outer_code == ZERO_EXTRACT |
066cd967 | 21763 | || (outer_code == MULT |
279bb624 | 21764 | && satisfies_constraint_I (x)) |
22e54023 DE |
21765 | || ((outer_code == DIV || outer_code == UDIV |
21766 | || outer_code == MOD || outer_code == UMOD) | |
21767 | && exact_log2 (INTVAL (x)) >= 0) | |
066cd967 | 21768 | || (outer_code == COMPARE |
279bb624 DE |
21769 | && (satisfies_constraint_I (x) |
21770 | || satisfies_constraint_K (x))) | |
22e54023 | 21771 | || (outer_code == EQ |
279bb624 DE |
21772 | && (satisfies_constraint_I (x) |
21773 | || satisfies_constraint_K (x) | |
21774 | || (mode == SImode | |
21775 | ? satisfies_constraint_L (x) | |
21776 | : satisfies_constraint_J (x)))) | |
22e54023 | 21777 | || (outer_code == GTU |
279bb624 | 21778 | && satisfies_constraint_I (x)) |
22e54023 | 21779 | || (outer_code == LTU |
279bb624 | 21780 | && satisfies_constraint_P (x))) |
066cd967 DE |
21781 | { |
21782 | *total = 0; | |
21783 | return true; | |
21784 | } | |
21785 | else if ((outer_code == PLUS | |
4ae234b0 | 21786 | && reg_or_add_cint_operand (x, VOIDmode)) |
066cd967 | 21787 | || (outer_code == MINUS |
4ae234b0 | 21788 | && reg_or_sub_cint_operand (x, VOIDmode)) |
066cd967 DE |
21789 | || ((outer_code == SET |
21790 | || outer_code == IOR | |
21791 | || outer_code == XOR) | |
21792 | && (INTVAL (x) | |
21793 | & ~ (unsigned HOST_WIDE_INT) 0xffffffff) == 0)) | |
21794 | { | |
21795 | *total = COSTS_N_INSNS (1); | |
21796 | return true; | |
21797 | } | |
21798 | /* FALLTHRU */ | |
21799 | ||
21800 | case CONST_DOUBLE: | |
f6fe3a22 | 21801 | if (mode == DImode && code == CONST_DOUBLE) |
066cd967 | 21802 | { |
f6fe3a22 DE |
21803 | if ((outer_code == IOR || outer_code == XOR) |
21804 | && CONST_DOUBLE_HIGH (x) == 0 | |
21805 | && (CONST_DOUBLE_LOW (x) | |
21806 | & ~ (unsigned HOST_WIDE_INT) 0xffff) == 0) | |
21807 | { | |
21808 | *total = 0; | |
21809 | return true; | |
21810 | } | |
21811 | else if ((outer_code == AND && and64_2_operand (x, DImode)) | |
21812 | || ((outer_code == SET | |
21813 | || outer_code == IOR | |
21814 | || outer_code == XOR) | |
21815 | && CONST_DOUBLE_HIGH (x) == 0)) | |
21816 | { | |
21817 | *total = COSTS_N_INSNS (1); | |
21818 | return true; | |
21819 | } | |
066cd967 DE |
21820 | } |
21821 | /* FALLTHRU */ | |
21822 | ||
3c50106f | 21823 | case CONST: |
066cd967 | 21824 | case HIGH: |
3c50106f | 21825 | case SYMBOL_REF: |
066cd967 DE |
21826 | case MEM: |
21827 | /* When optimizing for size, MEM should be slightly more expensive | |
21828 | than generating address, e.g., (plus (reg) (const)). | |
c112cf2b | 21829 | L1 cache latency is about two instructions. */ |
f40751dd | 21830 | *total = !speed ? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (2); |
3c50106f RH |
21831 | return true; |
21832 | ||
30a555d9 DE |
21833 | case LABEL_REF: |
21834 | *total = 0; | |
21835 | return true; | |
21836 | ||
3c50106f | 21837 | case PLUS: |
f0517163 | 21838 | if (mode == DFmode) |
066cd967 DE |
21839 | { |
21840 | if (GET_CODE (XEXP (x, 0)) == MULT) | |
21841 | { | |
21842 | /* FNMA accounted in outer NEG. */ | |
21843 | if (outer_code == NEG) | |
21844 | *total = rs6000_cost->dmul - rs6000_cost->fp; | |
21845 | else | |
21846 | *total = rs6000_cost->dmul; | |
21847 | } | |
21848 | else | |
21849 | *total = rs6000_cost->fp; | |
21850 | } | |
f0517163 | 21851 | else if (mode == SFmode) |
066cd967 DE |
21852 | { |
21853 | /* FNMA accounted in outer NEG. */ | |
21854 | if (outer_code == NEG && GET_CODE (XEXP (x, 0)) == MULT) | |
21855 | *total = 0; | |
21856 | else | |
21857 | *total = rs6000_cost->fp; | |
21858 | } | |
f0517163 | 21859 | else |
066cd967 DE |
21860 | *total = COSTS_N_INSNS (1); |
21861 | return false; | |
3c50106f | 21862 | |
52190329 | 21863 | case MINUS: |
f0517163 | 21864 | if (mode == DFmode) |
066cd967 | 21865 | { |
762c919f JM |
21866 | if (GET_CODE (XEXP (x, 0)) == MULT |
21867 | || GET_CODE (XEXP (x, 1)) == MULT) | |
066cd967 DE |
21868 | { |
21869 | /* FNMA accounted in outer NEG. */ | |
21870 | if (outer_code == NEG) | |
762c919f | 21871 | *total = rs6000_cost->dmul - rs6000_cost->fp; |
066cd967 DE |
21872 | else |
21873 | *total = rs6000_cost->dmul; | |
21874 | } | |
21875 | else | |
21876 | *total = rs6000_cost->fp; | |
21877 | } | |
f0517163 | 21878 | else if (mode == SFmode) |
066cd967 DE |
21879 | { |
21880 | /* FNMA accounted in outer NEG. */ | |
21881 | if (outer_code == NEG && GET_CODE (XEXP (x, 0)) == MULT) | |
21882 | *total = 0; | |
21883 | else | |
21884 | *total = rs6000_cost->fp; | |
21885 | } | |
f0517163 | 21886 | else |
c4ad648e | 21887 | *total = COSTS_N_INSNS (1); |
066cd967 | 21888 | return false; |
3c50106f RH |
21889 | |
21890 | case MULT: | |
c9dbf840 | 21891 | if (GET_CODE (XEXP (x, 1)) == CONST_INT |
279bb624 | 21892 | && satisfies_constraint_I (XEXP (x, 1))) |
3c50106f | 21893 | { |
8b897cfa RS |
21894 | if (INTVAL (XEXP (x, 1)) >= -256 |
21895 | && INTVAL (XEXP (x, 1)) <= 255) | |
06a67bdd | 21896 | *total = rs6000_cost->mulsi_const9; |
8b897cfa | 21897 | else |
06a67bdd | 21898 | *total = rs6000_cost->mulsi_const; |
3c50106f | 21899 | } |
066cd967 DE |
21900 | /* FMA accounted in outer PLUS/MINUS. */ |
21901 | else if ((mode == DFmode || mode == SFmode) | |
21902 | && (outer_code == PLUS || outer_code == MINUS)) | |
21903 | *total = 0; | |
f0517163 | 21904 | else if (mode == DFmode) |
06a67bdd | 21905 | *total = rs6000_cost->dmul; |
f0517163 | 21906 | else if (mode == SFmode) |
06a67bdd | 21907 | *total = rs6000_cost->fp; |
f0517163 | 21908 | else if (mode == DImode) |
06a67bdd | 21909 | *total = rs6000_cost->muldi; |
8b897cfa | 21910 | else |
06a67bdd | 21911 | *total = rs6000_cost->mulsi; |
066cd967 | 21912 | return false; |
3c50106f RH |
21913 | |
21914 | case DIV: | |
21915 | case MOD: | |
f0517163 RS |
21916 | if (FLOAT_MODE_P (mode)) |
21917 | { | |
06a67bdd RS |
21918 | *total = mode == DFmode ? rs6000_cost->ddiv |
21919 | : rs6000_cost->sdiv; | |
066cd967 | 21920 | return false; |
f0517163 | 21921 | } |
5efb1046 | 21922 | /* FALLTHRU */ |
3c50106f RH |
21923 | |
21924 | case UDIV: | |
21925 | case UMOD: | |
627b6fe2 DJ |
21926 | if (GET_CODE (XEXP (x, 1)) == CONST_INT |
21927 | && exact_log2 (INTVAL (XEXP (x, 1))) >= 0) | |
21928 | { | |
21929 | if (code == DIV || code == MOD) | |
21930 | /* Shift, addze */ | |
21931 | *total = COSTS_N_INSNS (2); | |
21932 | else | |
21933 | /* Shift */ | |
21934 | *total = COSTS_N_INSNS (1); | |
21935 | } | |
c4ad648e | 21936 | else |
627b6fe2 DJ |
21937 | { |
21938 | if (GET_MODE (XEXP (x, 1)) == DImode) | |
21939 | *total = rs6000_cost->divdi; | |
21940 | else | |
21941 | *total = rs6000_cost->divsi; | |
21942 | } | |
21943 | /* Add in shift and subtract for MOD. */ | |
21944 | if (code == MOD || code == UMOD) | |
21945 | *total += COSTS_N_INSNS (2); | |
066cd967 | 21946 | return false; |
3c50106f | 21947 | |
32f56aad | 21948 | case CTZ: |
3c50106f RH |
21949 | case FFS: |
21950 | *total = COSTS_N_INSNS (4); | |
066cd967 | 21951 | return false; |
3c50106f | 21952 | |
32f56aad DE |
21953 | case POPCOUNT: |
21954 | *total = COSTS_N_INSNS (6); | |
21955 | return false; | |
21956 | ||
06a67bdd | 21957 | case NOT: |
066cd967 DE |
21958 | if (outer_code == AND || outer_code == IOR || outer_code == XOR) |
21959 | { | |
21960 | *total = 0; | |
21961 | return false; | |
21962 | } | |
21963 | /* FALLTHRU */ | |
21964 | ||
21965 | case AND: | |
32f56aad | 21966 | case CLZ: |
066cd967 DE |
21967 | case IOR: |
21968 | case XOR: | |
d5861a7a DE |
21969 | case ZERO_EXTRACT: |
21970 | *total = COSTS_N_INSNS (1); | |
21971 | return false; | |
21972 | ||
066cd967 DE |
21973 | case ASHIFT: |
21974 | case ASHIFTRT: | |
21975 | case LSHIFTRT: | |
21976 | case ROTATE: | |
21977 | case ROTATERT: | |
d5861a7a | 21978 | /* Handle mul_highpart. */ |
066cd967 DE |
21979 | if (outer_code == TRUNCATE |
21980 | && GET_CODE (XEXP (x, 0)) == MULT) | |
21981 | { | |
21982 | if (mode == DImode) | |
21983 | *total = rs6000_cost->muldi; | |
21984 | else | |
21985 | *total = rs6000_cost->mulsi; | |
21986 | return true; | |
21987 | } | |
d5861a7a DE |
21988 | else if (outer_code == AND) |
21989 | *total = 0; | |
21990 | else | |
21991 | *total = COSTS_N_INSNS (1); | |
21992 | return false; | |
21993 | ||
21994 | case SIGN_EXTEND: | |
21995 | case ZERO_EXTEND: | |
21996 | if (GET_CODE (XEXP (x, 0)) == MEM) | |
21997 | *total = 0; | |
21998 | else | |
21999 | *total = COSTS_N_INSNS (1); | |
066cd967 | 22000 | return false; |
06a67bdd | 22001 | |
066cd967 DE |
22002 | case COMPARE: |
22003 | case NEG: | |
22004 | case ABS: | |
22005 | if (!FLOAT_MODE_P (mode)) | |
22006 | { | |
22007 | *total = COSTS_N_INSNS (1); | |
22008 | return false; | |
22009 | } | |
22010 | /* FALLTHRU */ | |
22011 | ||
22012 | case FLOAT: | |
22013 | case UNSIGNED_FLOAT: | |
22014 | case FIX: | |
22015 | case UNSIGNED_FIX: | |
06a67bdd RS |
22016 | case FLOAT_TRUNCATE: |
22017 | *total = rs6000_cost->fp; | |
066cd967 | 22018 | return false; |
06a67bdd | 22019 | |
a2af5043 DJ |
22020 | case FLOAT_EXTEND: |
22021 | if (mode == DFmode) | |
22022 | *total = 0; | |
22023 | else | |
22024 | *total = rs6000_cost->fp; | |
22025 | return false; | |
22026 | ||
06a67bdd RS |
22027 | case UNSPEC: |
22028 | switch (XINT (x, 1)) | |
22029 | { | |
22030 | case UNSPEC_FRSP: | |
22031 | *total = rs6000_cost->fp; | |
22032 | return true; | |
22033 | ||
22034 | default: | |
22035 | break; | |
22036 | } | |
22037 | break; | |
22038 | ||
22039 | case CALL: | |
22040 | case IF_THEN_ELSE: | |
f40751dd | 22041 | if (!speed) |
06a67bdd RS |
22042 | { |
22043 | *total = COSTS_N_INSNS (1); | |
22044 | return true; | |
22045 | } | |
066cd967 DE |
22046 | else if (FLOAT_MODE_P (mode) |
22047 | && TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS) | |
22048 | { | |
22049 | *total = rs6000_cost->fp; | |
22050 | return false; | |
22051 | } | |
06a67bdd RS |
22052 | break; |
22053 | ||
c0600ecd DE |
22054 | case EQ: |
22055 | case GTU: | |
22056 | case LTU: | |
22e54023 DE |
22057 | /* Carry bit requires mode == Pmode. |
22058 | NEG or PLUS already counted so only add one. */ | |
22059 | if (mode == Pmode | |
22060 | && (outer_code == NEG || outer_code == PLUS)) | |
c0600ecd | 22061 | { |
22e54023 DE |
22062 | *total = COSTS_N_INSNS (1); |
22063 | return true; | |
22064 | } | |
22065 | if (outer_code == SET) | |
22066 | { | |
22067 | if (XEXP (x, 1) == const0_rtx) | |
c0600ecd | 22068 | { |
22e54023 | 22069 | *total = COSTS_N_INSNS (2); |
c0600ecd | 22070 | return true; |
c0600ecd | 22071 | } |
22e54023 DE |
22072 | else if (mode == Pmode) |
22073 | { | |
22074 | *total = COSTS_N_INSNS (3); | |
22075 | return false; | |
22076 | } | |
22077 | } | |
22078 | /* FALLTHRU */ | |
22079 | ||
22080 | case GT: | |
22081 | case LT: | |
22082 | case UNORDERED: | |
22083 | if (outer_code == SET && (XEXP (x, 1) == const0_rtx)) | |
22084 | { | |
22085 | *total = COSTS_N_INSNS (2); | |
22086 | return true; | |
c0600ecd | 22087 | } |
22e54023 DE |
22088 | /* CC COMPARE. */ |
22089 | if (outer_code == COMPARE) | |
22090 | { | |
22091 | *total = 0; | |
22092 | return true; | |
22093 | } | |
22094 | break; | |
c0600ecd | 22095 | |
3c50106f | 22096 | default: |
06a67bdd | 22097 | break; |
3c50106f | 22098 | } |
06a67bdd RS |
22099 | |
22100 | return false; | |
3c50106f RH |
22101 | } |
22102 | ||
34bb030a DE |
22103 | /* A C expression returning the cost of moving data from a register of class |
22104 | CLASS1 to one of CLASS2. */ | |
22105 | ||
22106 | int | |
f676971a | 22107 | rs6000_register_move_cost (enum machine_mode mode, |
a2369ed3 | 22108 | enum reg_class from, enum reg_class to) |
34bb030a DE |
22109 | { |
22110 | /* Moves from/to GENERAL_REGS. */ | |
22111 | if (reg_classes_intersect_p (to, GENERAL_REGS) | |
22112 | || reg_classes_intersect_p (from, GENERAL_REGS)) | |
22113 | { | |
22114 | if (! reg_classes_intersect_p (to, GENERAL_REGS)) | |
22115 | from = to; | |
22116 | ||
22117 | if (from == FLOAT_REGS || from == ALTIVEC_REGS) | |
22118 | return (rs6000_memory_move_cost (mode, from, 0) | |
22119 | + rs6000_memory_move_cost (mode, GENERAL_REGS, 0)); | |
22120 | ||
c4ad648e AM |
22121 | /* It's more expensive to move CR_REGS than CR0_REGS because of the |
22122 | shift. */ | |
34bb030a DE |
22123 | else if (from == CR_REGS) |
22124 | return 4; | |
22125 | ||
aafc759a PH |
22126 | /* Power6 has slower LR/CTR moves so make them more expensive than |
22127 | memory in order to bias spills to memory .*/ | |
22128 | else if (rs6000_cpu == PROCESSOR_POWER6 | |
22129 | && reg_classes_intersect_p (from, LINK_OR_CTR_REGS)) | |
22130 | return 6 * hard_regno_nregs[0][mode]; | |
22131 | ||
34bb030a | 22132 | else |
c4ad648e | 22133 | /* A move will cost one instruction per GPR moved. */ |
c8b622ff | 22134 | return 2 * hard_regno_nregs[0][mode]; |
34bb030a DE |
22135 | } |
22136 | ||
c4ad648e | 22137 | /* Moving between two similar registers is just one instruction. */ |
34bb030a | 22138 | else if (reg_classes_intersect_p (to, from)) |
7393f7f8 | 22139 | return (mode == TFmode || mode == TDmode) ? 4 : 2; |
34bb030a | 22140 | |
c4ad648e | 22141 | /* Everything else has to go through GENERAL_REGS. */ |
34bb030a | 22142 | else |
f676971a | 22143 | return (rs6000_register_move_cost (mode, GENERAL_REGS, to) |
34bb030a DE |
22144 | + rs6000_register_move_cost (mode, from, GENERAL_REGS)); |
22145 | } | |
22146 | ||
22147 | /* A C expressions returning the cost of moving data of MODE from a register to | |
22148 | or from memory. */ | |
22149 | ||
22150 | int | |
0a2aaacc | 22151 | rs6000_memory_move_cost (enum machine_mode mode, enum reg_class rclass, |
a2369ed3 | 22152 | int in ATTRIBUTE_UNUSED) |
34bb030a | 22153 | { |
0a2aaacc | 22154 | if (reg_classes_intersect_p (rclass, GENERAL_REGS)) |
c8b622ff | 22155 | return 4 * hard_regno_nregs[0][mode]; |
0a2aaacc | 22156 | else if (reg_classes_intersect_p (rclass, FLOAT_REGS)) |
c8b622ff | 22157 | return 4 * hard_regno_nregs[32][mode]; |
0a2aaacc | 22158 | else if (reg_classes_intersect_p (rclass, ALTIVEC_REGS)) |
c8b622ff | 22159 | return 4 * hard_regno_nregs[FIRST_ALTIVEC_REGNO][mode]; |
34bb030a | 22160 | else |
0a2aaacc | 22161 | return 4 + rs6000_register_move_cost (mode, rclass, GENERAL_REGS); |
34bb030a DE |
22162 | } |
22163 | ||
9c78b944 DE |
22164 | /* Returns a code for a target-specific builtin that implements |
22165 | reciprocal of the function, or NULL_TREE if not available. */ | |
22166 | ||
22167 | static tree | |
22168 | rs6000_builtin_reciprocal (unsigned int fn, bool md_fn, | |
22169 | bool sqrt ATTRIBUTE_UNUSED) | |
22170 | { | |
22171 | if (! (TARGET_RECIP && TARGET_PPC_GFXOPT && !optimize_size | |
22172 | && flag_finite_math_only && !flag_trapping_math | |
22173 | && flag_unsafe_math_optimizations)) | |
22174 | return NULL_TREE; | |
22175 | ||
22176 | if (md_fn) | |
22177 | return NULL_TREE; | |
22178 | else | |
22179 | switch (fn) | |
22180 | { | |
22181 | case BUILT_IN_SQRTF: | |
22182 | return rs6000_builtin_decls[RS6000_BUILTIN_RSQRTF]; | |
22183 | ||
22184 | default: | |
22185 | return NULL_TREE; | |
22186 | } | |
22187 | } | |
22188 | ||
ef765ea9 DE |
22189 | /* Newton-Raphson approximation of single-precision floating point divide n/d. |
22190 | Assumes no trapping math and finite arguments. */ | |
22191 | ||
22192 | void | |
9c78b944 | 22193 | rs6000_emit_swdivsf (rtx dst, rtx n, rtx d) |
ef765ea9 DE |
22194 | { |
22195 | rtx x0, e0, e1, y1, u0, v0, one; | |
22196 | ||
22197 | x0 = gen_reg_rtx (SFmode); | |
22198 | e0 = gen_reg_rtx (SFmode); | |
22199 | e1 = gen_reg_rtx (SFmode); | |
22200 | y1 = gen_reg_rtx (SFmode); | |
22201 | u0 = gen_reg_rtx (SFmode); | |
22202 | v0 = gen_reg_rtx (SFmode); | |
22203 | one = force_reg (SFmode, CONST_DOUBLE_FROM_REAL_VALUE (dconst1, SFmode)); | |
22204 | ||
22205 | /* x0 = 1./d estimate */ | |
22206 | emit_insn (gen_rtx_SET (VOIDmode, x0, | |
22207 | gen_rtx_UNSPEC (SFmode, gen_rtvec (1, d), | |
22208 | UNSPEC_FRES))); | |
22209 | /* e0 = 1. - d * x0 */ | |
22210 | emit_insn (gen_rtx_SET (VOIDmode, e0, | |
22211 | gen_rtx_MINUS (SFmode, one, | |
22212 | gen_rtx_MULT (SFmode, d, x0)))); | |
22213 | /* e1 = e0 + e0 * e0 */ | |
22214 | emit_insn (gen_rtx_SET (VOIDmode, e1, | |
22215 | gen_rtx_PLUS (SFmode, | |
22216 | gen_rtx_MULT (SFmode, e0, e0), e0))); | |
22217 | /* y1 = x0 + e1 * x0 */ | |
22218 | emit_insn (gen_rtx_SET (VOIDmode, y1, | |
22219 | gen_rtx_PLUS (SFmode, | |
22220 | gen_rtx_MULT (SFmode, e1, x0), x0))); | |
22221 | /* u0 = n * y1 */ | |
22222 | emit_insn (gen_rtx_SET (VOIDmode, u0, | |
22223 | gen_rtx_MULT (SFmode, n, y1))); | |
22224 | /* v0 = n - d * u0 */ | |
22225 | emit_insn (gen_rtx_SET (VOIDmode, v0, | |
22226 | gen_rtx_MINUS (SFmode, n, | |
22227 | gen_rtx_MULT (SFmode, d, u0)))); | |
9c78b944 DE |
22228 | /* dst = u0 + v0 * y1 */ |
22229 | emit_insn (gen_rtx_SET (VOIDmode, dst, | |
ef765ea9 DE |
22230 | gen_rtx_PLUS (SFmode, |
22231 | gen_rtx_MULT (SFmode, v0, y1), u0))); | |
22232 | } | |
22233 | ||
22234 | /* Newton-Raphson approximation of double-precision floating point divide n/d. | |
22235 | Assumes no trapping math and finite arguments. */ | |
22236 | ||
22237 | void | |
9c78b944 | 22238 | rs6000_emit_swdivdf (rtx dst, rtx n, rtx d) |
ef765ea9 DE |
22239 | { |
22240 | rtx x0, e0, e1, e2, y1, y2, y3, u0, v0, one; | |
22241 | ||
22242 | x0 = gen_reg_rtx (DFmode); | |
22243 | e0 = gen_reg_rtx (DFmode); | |
22244 | e1 = gen_reg_rtx (DFmode); | |
22245 | e2 = gen_reg_rtx (DFmode); | |
22246 | y1 = gen_reg_rtx (DFmode); | |
22247 | y2 = gen_reg_rtx (DFmode); | |
22248 | y3 = gen_reg_rtx (DFmode); | |
22249 | u0 = gen_reg_rtx (DFmode); | |
22250 | v0 = gen_reg_rtx (DFmode); | |
22251 | one = force_reg (DFmode, CONST_DOUBLE_FROM_REAL_VALUE (dconst1, DFmode)); | |
22252 | ||
22253 | /* x0 = 1./d estimate */ | |
22254 | emit_insn (gen_rtx_SET (VOIDmode, x0, | |
22255 | gen_rtx_UNSPEC (DFmode, gen_rtvec (1, d), | |
22256 | UNSPEC_FRES))); | |
22257 | /* e0 = 1. - d * x0 */ | |
22258 | emit_insn (gen_rtx_SET (VOIDmode, e0, | |
22259 | gen_rtx_MINUS (DFmode, one, | |
22260 | gen_rtx_MULT (SFmode, d, x0)))); | |
22261 | /* y1 = x0 + e0 * x0 */ | |
22262 | emit_insn (gen_rtx_SET (VOIDmode, y1, | |
22263 | gen_rtx_PLUS (DFmode, | |
22264 | gen_rtx_MULT (DFmode, e0, x0), x0))); | |
22265 | /* e1 = e0 * e0 */ | |
22266 | emit_insn (gen_rtx_SET (VOIDmode, e1, | |
22267 | gen_rtx_MULT (DFmode, e0, e0))); | |
22268 | /* y2 = y1 + e1 * y1 */ | |
22269 | emit_insn (gen_rtx_SET (VOIDmode, y2, | |
22270 | gen_rtx_PLUS (DFmode, | |
22271 | gen_rtx_MULT (DFmode, e1, y1), y1))); | |
22272 | /* e2 = e1 * e1 */ | |
22273 | emit_insn (gen_rtx_SET (VOIDmode, e2, | |
22274 | gen_rtx_MULT (DFmode, e1, e1))); | |
22275 | /* y3 = y2 + e2 * y2 */ | |
22276 | emit_insn (gen_rtx_SET (VOIDmode, y3, | |
22277 | gen_rtx_PLUS (DFmode, | |
22278 | gen_rtx_MULT (DFmode, e2, y2), y2))); | |
22279 | /* u0 = n * y3 */ | |
22280 | emit_insn (gen_rtx_SET (VOIDmode, u0, | |
22281 | gen_rtx_MULT (DFmode, n, y3))); | |
22282 | /* v0 = n - d * u0 */ | |
22283 | emit_insn (gen_rtx_SET (VOIDmode, v0, | |
22284 | gen_rtx_MINUS (DFmode, n, | |
22285 | gen_rtx_MULT (DFmode, d, u0)))); | |
9c78b944 DE |
22286 | /* dst = u0 + v0 * y3 */ |
22287 | emit_insn (gen_rtx_SET (VOIDmode, dst, | |
ef765ea9 DE |
22288 | gen_rtx_PLUS (DFmode, |
22289 | gen_rtx_MULT (DFmode, v0, y3), u0))); | |
22290 | } | |
22291 | ||
565ef4ba | 22292 | |
9c78b944 DE |
22293 | /* Newton-Raphson approximation of single-precision floating point rsqrt. |
22294 | Assumes no trapping math and finite arguments. */ | |
22295 | ||
22296 | void | |
22297 | rs6000_emit_swrsqrtsf (rtx dst, rtx src) | |
22298 | { | |
22299 | rtx x0, x1, x2, y1, u0, u1, u2, v0, v1, v2, t0, | |
22300 | half, one, halfthree, c1, cond, label; | |
22301 | ||
22302 | x0 = gen_reg_rtx (SFmode); | |
22303 | x1 = gen_reg_rtx (SFmode); | |
22304 | x2 = gen_reg_rtx (SFmode); | |
22305 | y1 = gen_reg_rtx (SFmode); | |
22306 | u0 = gen_reg_rtx (SFmode); | |
22307 | u1 = gen_reg_rtx (SFmode); | |
22308 | u2 = gen_reg_rtx (SFmode); | |
22309 | v0 = gen_reg_rtx (SFmode); | |
22310 | v1 = gen_reg_rtx (SFmode); | |
22311 | v2 = gen_reg_rtx (SFmode); | |
22312 | t0 = gen_reg_rtx (SFmode); | |
22313 | halfthree = gen_reg_rtx (SFmode); | |
22314 | cond = gen_rtx_REG (CCFPmode, CR1_REGNO); | |
22315 | label = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ()); | |
22316 | ||
22317 | /* check 0.0, 1.0, NaN, Inf by testing src * src = src */ | |
22318 | emit_insn (gen_rtx_SET (VOIDmode, t0, | |
22319 | gen_rtx_MULT (SFmode, src, src))); | |
22320 | ||
22321 | emit_insn (gen_rtx_SET (VOIDmode, cond, | |
22322 | gen_rtx_COMPARE (CCFPmode, t0, src))); | |
22323 | c1 = gen_rtx_EQ (VOIDmode, cond, const0_rtx); | |
22324 | emit_unlikely_jump (c1, label); | |
22325 | ||
22326 | half = force_reg (SFmode, CONST_DOUBLE_FROM_REAL_VALUE (dconsthalf, SFmode)); | |
22327 | one = force_reg (SFmode, CONST_DOUBLE_FROM_REAL_VALUE (dconst1, SFmode)); | |
22328 | ||
22329 | /* halfthree = 1.5 = 1.0 + 0.5 */ | |
22330 | emit_insn (gen_rtx_SET (VOIDmode, halfthree, | |
22331 | gen_rtx_PLUS (SFmode, one, half))); | |
22332 | ||
22333 | /* x0 = rsqrt estimate */ | |
22334 | emit_insn (gen_rtx_SET (VOIDmode, x0, | |
22335 | gen_rtx_UNSPEC (SFmode, gen_rtvec (1, src), | |
22336 | UNSPEC_RSQRT))); | |
22337 | ||
22338 | /* y1 = 0.5 * src = 1.5 * src - src -> fewer constants */ | |
22339 | emit_insn (gen_rtx_SET (VOIDmode, y1, | |
22340 | gen_rtx_MINUS (SFmode, | |
22341 | gen_rtx_MULT (SFmode, src, halfthree), | |
22342 | src))); | |
22343 | ||
22344 | /* x1 = x0 * (1.5 - y1 * (x0 * x0)) */ | |
22345 | emit_insn (gen_rtx_SET (VOIDmode, u0, | |
22346 | gen_rtx_MULT (SFmode, x0, x0))); | |
22347 | emit_insn (gen_rtx_SET (VOIDmode, v0, | |
22348 | gen_rtx_MINUS (SFmode, | |
22349 | halfthree, | |
22350 | gen_rtx_MULT (SFmode, y1, u0)))); | |
22351 | emit_insn (gen_rtx_SET (VOIDmode, x1, | |
22352 | gen_rtx_MULT (SFmode, x0, v0))); | |
22353 | ||
22354 | /* x2 = x1 * (1.5 - y1 * (x1 * x1)) */ | |
22355 | emit_insn (gen_rtx_SET (VOIDmode, u1, | |
22356 | gen_rtx_MULT (SFmode, x1, x1))); | |
22357 | emit_insn (gen_rtx_SET (VOIDmode, v1, | |
22358 | gen_rtx_MINUS (SFmode, | |
22359 | halfthree, | |
22360 | gen_rtx_MULT (SFmode, y1, u1)))); | |
22361 | emit_insn (gen_rtx_SET (VOIDmode, x2, | |
22362 | gen_rtx_MULT (SFmode, x1, v1))); | |
22363 | ||
22364 | /* dst = x2 * (1.5 - y1 * (x2 * x2)) */ | |
22365 | emit_insn (gen_rtx_SET (VOIDmode, u2, | |
22366 | gen_rtx_MULT (SFmode, x2, x2))); | |
22367 | emit_insn (gen_rtx_SET (VOIDmode, v2, | |
22368 | gen_rtx_MINUS (SFmode, | |
22369 | halfthree, | |
22370 | gen_rtx_MULT (SFmode, y1, u2)))); | |
22371 | emit_insn (gen_rtx_SET (VOIDmode, dst, | |
22372 | gen_rtx_MULT (SFmode, x2, v2))); | |
22373 | ||
22374 | emit_label (XEXP (label, 0)); | |
22375 | } | |
22376 | ||
565ef4ba RS |
22377 | /* Emit popcount intrinsic on TARGET_POPCNTB targets. DST is the |
22378 | target, and SRC is the argument operand. */ | |
22379 | ||
22380 | void | |
22381 | rs6000_emit_popcount (rtx dst, rtx src) | |
22382 | { | |
22383 | enum machine_mode mode = GET_MODE (dst); | |
22384 | rtx tmp1, tmp2; | |
22385 | ||
22386 | tmp1 = gen_reg_rtx (mode); | |
22387 | ||
22388 | if (mode == SImode) | |
22389 | { | |
22390 | emit_insn (gen_popcntbsi2 (tmp1, src)); | |
22391 | tmp2 = expand_mult (SImode, tmp1, GEN_INT (0x01010101), | |
22392 | NULL_RTX, 0); | |
22393 | tmp2 = force_reg (SImode, tmp2); | |
22394 | emit_insn (gen_lshrsi3 (dst, tmp2, GEN_INT (24))); | |
22395 | } | |
22396 | else | |
22397 | { | |
22398 | emit_insn (gen_popcntbdi2 (tmp1, src)); | |
22399 | tmp2 = expand_mult (DImode, tmp1, | |
22400 | GEN_INT ((HOST_WIDE_INT) | |
22401 | 0x01010101 << 32 | 0x01010101), | |
22402 | NULL_RTX, 0); | |
22403 | tmp2 = force_reg (DImode, tmp2); | |
22404 | emit_insn (gen_lshrdi3 (dst, tmp2, GEN_INT (56))); | |
22405 | } | |
22406 | } | |
22407 | ||
22408 | ||
22409 | /* Emit parity intrinsic on TARGET_POPCNTB targets. DST is the | |
22410 | target, and SRC is the argument operand. */ | |
22411 | ||
22412 | void | |
22413 | rs6000_emit_parity (rtx dst, rtx src) | |
22414 | { | |
22415 | enum machine_mode mode = GET_MODE (dst); | |
22416 | rtx tmp; | |
22417 | ||
22418 | tmp = gen_reg_rtx (mode); | |
22419 | if (mode == SImode) | |
22420 | { | |
22421 | /* Is mult+shift >= shift+xor+shift+xor? */ | |
22422 | if (rs6000_cost->mulsi_const >= COSTS_N_INSNS (3)) | |
22423 | { | |
22424 | rtx tmp1, tmp2, tmp3, tmp4; | |
22425 | ||
22426 | tmp1 = gen_reg_rtx (SImode); | |
22427 | emit_insn (gen_popcntbsi2 (tmp1, src)); | |
22428 | ||
22429 | tmp2 = gen_reg_rtx (SImode); | |
22430 | emit_insn (gen_lshrsi3 (tmp2, tmp1, GEN_INT (16))); | |
22431 | tmp3 = gen_reg_rtx (SImode); | |
22432 | emit_insn (gen_xorsi3 (tmp3, tmp1, tmp2)); | |
22433 | ||
22434 | tmp4 = gen_reg_rtx (SImode); | |
22435 | emit_insn (gen_lshrsi3 (tmp4, tmp3, GEN_INT (8))); | |
22436 | emit_insn (gen_xorsi3 (tmp, tmp3, tmp4)); | |
22437 | } | |
22438 | else | |
22439 | rs6000_emit_popcount (tmp, src); | |
22440 | emit_insn (gen_andsi3 (dst, tmp, const1_rtx)); | |
22441 | } | |
22442 | else | |
22443 | { | |
22444 | /* Is mult+shift >= shift+xor+shift+xor+shift+xor? */ | |
22445 | if (rs6000_cost->muldi >= COSTS_N_INSNS (5)) | |
22446 | { | |
22447 | rtx tmp1, tmp2, tmp3, tmp4, tmp5, tmp6; | |
22448 | ||
22449 | tmp1 = gen_reg_rtx (DImode); | |
22450 | emit_insn (gen_popcntbdi2 (tmp1, src)); | |
22451 | ||
22452 | tmp2 = gen_reg_rtx (DImode); | |
22453 | emit_insn (gen_lshrdi3 (tmp2, tmp1, GEN_INT (32))); | |
22454 | tmp3 = gen_reg_rtx (DImode); | |
22455 | emit_insn (gen_xordi3 (tmp3, tmp1, tmp2)); | |
22456 | ||
22457 | tmp4 = gen_reg_rtx (DImode); | |
22458 | emit_insn (gen_lshrdi3 (tmp4, tmp3, GEN_INT (16))); | |
22459 | tmp5 = gen_reg_rtx (DImode); | |
22460 | emit_insn (gen_xordi3 (tmp5, tmp3, tmp4)); | |
22461 | ||
22462 | tmp6 = gen_reg_rtx (DImode); | |
22463 | emit_insn (gen_lshrdi3 (tmp6, tmp5, GEN_INT (8))); | |
22464 | emit_insn (gen_xordi3 (tmp, tmp5, tmp6)); | |
22465 | } | |
22466 | else | |
22467 | rs6000_emit_popcount (tmp, src); | |
22468 | emit_insn (gen_anddi3 (dst, tmp, const1_rtx)); | |
22469 | } | |
22470 | } | |
22471 | ||
ded9bf77 AH |
22472 | /* Return an RTX representing where to find the function value of a |
22473 | function returning MODE. */ | |
22474 | static rtx | |
22475 | rs6000_complex_function_value (enum machine_mode mode) | |
22476 | { | |
22477 | unsigned int regno; | |
22478 | rtx r1, r2; | |
22479 | enum machine_mode inner = GET_MODE_INNER (mode); | |
fb7e4164 | 22480 | unsigned int inner_bytes = GET_MODE_SIZE (inner); |
ded9bf77 | 22481 | |
18f63bfa AH |
22482 | if (FLOAT_MODE_P (mode) && TARGET_HARD_FLOAT && TARGET_FPRS) |
22483 | regno = FP_ARG_RETURN; | |
354ed18f AH |
22484 | else |
22485 | { | |
18f63bfa | 22486 | regno = GP_ARG_RETURN; |
ded9bf77 | 22487 | |
18f63bfa AH |
22488 | /* 32-bit is OK since it'll go in r3/r4. */ |
22489 | if (TARGET_32BIT && inner_bytes >= 4) | |
ded9bf77 AH |
22490 | return gen_rtx_REG (mode, regno); |
22491 | } | |
22492 | ||
18f63bfa AH |
22493 | if (inner_bytes >= 8) |
22494 | return gen_rtx_REG (mode, regno); | |
22495 | ||
ded9bf77 AH |
22496 | r1 = gen_rtx_EXPR_LIST (inner, gen_rtx_REG (inner, regno), |
22497 | const0_rtx); | |
22498 | r2 = gen_rtx_EXPR_LIST (inner, gen_rtx_REG (inner, regno + 1), | |
fb7e4164 | 22499 | GEN_INT (inner_bytes)); |
ded9bf77 AH |
22500 | return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r2)); |
22501 | } | |
22502 | ||
a6ebc39a AH |
22503 | /* Define how to find the value returned by a function. |
22504 | VALTYPE is the data type of the value (as a tree). | |
22505 | If the precise function being called is known, FUNC is its FUNCTION_DECL; | |
22506 | otherwise, FUNC is 0. | |
22507 | ||
22508 | On the SPE, both FPs and vectors are returned in r3. | |
22509 | ||
22510 | On RS/6000 an integer value is in r3 and a floating-point value is in | |
22511 | fp1, unless -msoft-float. */ | |
22512 | ||
22513 | rtx | |
586de218 | 22514 | rs6000_function_value (const_tree valtype, const_tree func ATTRIBUTE_UNUSED) |
a6ebc39a AH |
22515 | { |
22516 | enum machine_mode mode; | |
2a8fa26c | 22517 | unsigned int regno; |
a6ebc39a | 22518 | |
594a51fe SS |
22519 | /* Special handling for structs in darwin64. */ |
22520 | if (rs6000_darwin64_abi | |
22521 | && TYPE_MODE (valtype) == BLKmode | |
0b5383eb DJ |
22522 | && TREE_CODE (valtype) == RECORD_TYPE |
22523 | && int_size_in_bytes (valtype) > 0) | |
594a51fe SS |
22524 | { |
22525 | CUMULATIVE_ARGS valcum; | |
22526 | rtx valret; | |
22527 | ||
0b5383eb | 22528 | valcum.words = 0; |
594a51fe SS |
22529 | valcum.fregno = FP_ARG_MIN_REG; |
22530 | valcum.vregno = ALTIVEC_ARG_MIN_REG; | |
0b5383eb DJ |
22531 | /* Do a trial code generation as if this were going to be passed as |
22532 | an argument; if any part goes in memory, we return NULL. */ | |
22533 | valret = rs6000_darwin64_record_arg (&valcum, valtype, 1, true); | |
594a51fe SS |
22534 | if (valret) |
22535 | return valret; | |
22536 | /* Otherwise fall through to standard ABI rules. */ | |
22537 | } | |
22538 | ||
0e67400a FJ |
22539 | if (TARGET_32BIT && TARGET_POWERPC64 && TYPE_MODE (valtype) == DImode) |
22540 | { | |
22541 | /* Long long return value need be split in -mpowerpc64, 32bit ABI. */ | |
22542 | return gen_rtx_PARALLEL (DImode, | |
22543 | gen_rtvec (2, | |
22544 | gen_rtx_EXPR_LIST (VOIDmode, | |
22545 | gen_rtx_REG (SImode, GP_ARG_RETURN), | |
22546 | const0_rtx), | |
22547 | gen_rtx_EXPR_LIST (VOIDmode, | |
22548 | gen_rtx_REG (SImode, | |
22549 | GP_ARG_RETURN + 1), | |
22550 | GEN_INT (4)))); | |
22551 | } | |
0f086e42 FJ |
22552 | if (TARGET_32BIT && TARGET_POWERPC64 && TYPE_MODE (valtype) == DCmode) |
22553 | { | |
22554 | return gen_rtx_PARALLEL (DCmode, | |
22555 | gen_rtvec (4, | |
22556 | gen_rtx_EXPR_LIST (VOIDmode, | |
22557 | gen_rtx_REG (SImode, GP_ARG_RETURN), | |
22558 | const0_rtx), | |
22559 | gen_rtx_EXPR_LIST (VOIDmode, | |
22560 | gen_rtx_REG (SImode, | |
22561 | GP_ARG_RETURN + 1), | |
22562 | GEN_INT (4)), | |
22563 | gen_rtx_EXPR_LIST (VOIDmode, | |
22564 | gen_rtx_REG (SImode, | |
22565 | GP_ARG_RETURN + 2), | |
22566 | GEN_INT (8)), | |
22567 | gen_rtx_EXPR_LIST (VOIDmode, | |
22568 | gen_rtx_REG (SImode, | |
22569 | GP_ARG_RETURN + 3), | |
22570 | GEN_INT (12)))); | |
22571 | } | |
602ea4d3 | 22572 | |
7348aa7f FXC |
22573 | mode = TYPE_MODE (valtype); |
22574 | if ((INTEGRAL_TYPE_P (valtype) && GET_MODE_BITSIZE (mode) < BITS_PER_WORD) | |
a6ebc39a | 22575 | || POINTER_TYPE_P (valtype)) |
b78d48dd | 22576 | mode = TARGET_32BIT ? SImode : DImode; |
a6ebc39a | 22577 | |
e41b2a33 PB |
22578 | if (DECIMAL_FLOAT_MODE_P (mode) && TARGET_HARD_FLOAT && TARGET_FPRS) |
22579 | /* _Decimal128 must use an even/odd register pair. */ | |
22580 | regno = (mode == TDmode) ? FP_ARG_RETURN + 1 : FP_ARG_RETURN; | |
2c5cac98 ME |
22581 | else if (SCALAR_FLOAT_TYPE_P (valtype) && TARGET_HARD_FLOAT && TARGET_FPRS |
22582 | && ((TARGET_SINGLE_FLOAT && (mode == SFmode)) || TARGET_DOUBLE_FLOAT)) | |
2a8fa26c | 22583 | regno = FP_ARG_RETURN; |
ded9bf77 | 22584 | else if (TREE_CODE (valtype) == COMPLEX_TYPE |
42ba5130 | 22585 | && targetm.calls.split_complex_arg) |
ded9bf77 | 22586 | return rs6000_complex_function_value (mode); |
44688022 | 22587 | else if (TREE_CODE (valtype) == VECTOR_TYPE |
d0b2079e | 22588 | && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI |
23ba09f0 | 22589 | && ALTIVEC_VECTOR_MODE (mode)) |
a6ebc39a | 22590 | regno = ALTIVEC_ARG_RETURN; |
18f63bfa | 22591 | else if (TARGET_E500_DOUBLE && TARGET_HARD_FLOAT |
4f011e1e JM |
22592 | && (mode == DFmode || mode == DCmode |
22593 | || mode == TFmode || mode == TCmode)) | |
18f63bfa | 22594 | return spe_build_register_parallel (mode, GP_ARG_RETURN); |
a6ebc39a AH |
22595 | else |
22596 | regno = GP_ARG_RETURN; | |
22597 | ||
22598 | return gen_rtx_REG (mode, regno); | |
22599 | } | |
22600 | ||
ded9bf77 AH |
22601 | /* Define how to find the value returned by a library function |
22602 | assuming the value has mode MODE. */ | |
22603 | rtx | |
22604 | rs6000_libcall_value (enum machine_mode mode) | |
22605 | { | |
22606 | unsigned int regno; | |
22607 | ||
2e6c9641 FJ |
22608 | if (TARGET_32BIT && TARGET_POWERPC64 && mode == DImode) |
22609 | { | |
22610 | /* Long long return value need be split in -mpowerpc64, 32bit ABI. */ | |
22611 | return gen_rtx_PARALLEL (DImode, | |
22612 | gen_rtvec (2, | |
22613 | gen_rtx_EXPR_LIST (VOIDmode, | |
22614 | gen_rtx_REG (SImode, GP_ARG_RETURN), | |
22615 | const0_rtx), | |
22616 | gen_rtx_EXPR_LIST (VOIDmode, | |
22617 | gen_rtx_REG (SImode, | |
22618 | GP_ARG_RETURN + 1), | |
22619 | GEN_INT (4)))); | |
22620 | } | |
22621 | ||
e41b2a33 PB |
22622 | if (DECIMAL_FLOAT_MODE_P (mode) && TARGET_HARD_FLOAT && TARGET_FPRS) |
22623 | /* _Decimal128 must use an even/odd register pair. */ | |
22624 | regno = (mode == TDmode) ? FP_ARG_RETURN + 1 : FP_ARG_RETURN; | |
00b79d54 | 22625 | else if (SCALAR_FLOAT_MODE_P (mode) |
ded9bf77 AH |
22626 | && TARGET_HARD_FLOAT && TARGET_FPRS) |
22627 | regno = FP_ARG_RETURN; | |
44688022 AM |
22628 | else if (ALTIVEC_VECTOR_MODE (mode) |
22629 | && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI) | |
ded9bf77 | 22630 | regno = ALTIVEC_ARG_RETURN; |
42ba5130 | 22631 | else if (COMPLEX_MODE_P (mode) && targetm.calls.split_complex_arg) |
ded9bf77 | 22632 | return rs6000_complex_function_value (mode); |
18f63bfa | 22633 | else if (TARGET_E500_DOUBLE && TARGET_HARD_FLOAT |
4f011e1e JM |
22634 | && (mode == DFmode || mode == DCmode |
22635 | || mode == TFmode || mode == TCmode)) | |
18f63bfa | 22636 | return spe_build_register_parallel (mode, GP_ARG_RETURN); |
ded9bf77 AH |
22637 | else |
22638 | regno = GP_ARG_RETURN; | |
22639 | ||
22640 | return gen_rtx_REG (mode, regno); | |
22641 | } | |
22642 | ||
d1d0c603 JJ |
22643 | /* Define the offset between two registers, FROM to be eliminated and its |
22644 | replacement TO, at the start of a routine. */ | |
22645 | HOST_WIDE_INT | |
22646 | rs6000_initial_elimination_offset (int from, int to) | |
22647 | { | |
22648 | rs6000_stack_t *info = rs6000_stack_info (); | |
22649 | HOST_WIDE_INT offset; | |
22650 | ||
7d5175e1 | 22651 | if (from == HARD_FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM) |
d1d0c603 | 22652 | offset = info->push_p ? 0 : -info->total_size; |
7d5175e1 JJ |
22653 | else if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM) |
22654 | { | |
22655 | offset = info->push_p ? 0 : -info->total_size; | |
22656 | if (FRAME_GROWS_DOWNWARD) | |
5b667039 | 22657 | offset += info->fixed_size + info->vars_size + info->parm_size; |
7d5175e1 JJ |
22658 | } |
22659 | else if (from == FRAME_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM) | |
22660 | offset = FRAME_GROWS_DOWNWARD | |
5b667039 | 22661 | ? info->fixed_size + info->vars_size + info->parm_size |
7d5175e1 JJ |
22662 | : 0; |
22663 | else if (from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM) | |
d1d0c603 JJ |
22664 | offset = info->total_size; |
22665 | else if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM) | |
22666 | offset = info->push_p ? info->total_size : 0; | |
22667 | else if (from == RS6000_PIC_OFFSET_TABLE_REGNUM) | |
22668 | offset = 0; | |
22669 | else | |
37409796 | 22670 | gcc_unreachable (); |
d1d0c603 JJ |
22671 | |
22672 | return offset; | |
22673 | } | |
22674 | ||
96714395 | 22675 | static rtx |
a2369ed3 | 22676 | rs6000_dwarf_register_span (rtx reg) |
96714395 | 22677 | { |
6cd1d2e2 DJ |
22678 | rtx parts[8]; |
22679 | int i, words; | |
22680 | unsigned regno = REGNO (reg); | |
22681 | enum machine_mode mode = GET_MODE (reg); | |
96714395 | 22682 | |
4d4cbc0e | 22683 | if (TARGET_SPE |
6cd1d2e2 | 22684 | && regno < 32 |
4d4cbc0e | 22685 | && (SPE_VECTOR_MODE (GET_MODE (reg)) |
6cd1d2e2 DJ |
22686 | || (TARGET_E500_DOUBLE && FLOAT_MODE_P (mode) |
22687 | && mode != SFmode && mode != SDmode && mode != SCmode))) | |
4d4cbc0e AH |
22688 | ; |
22689 | else | |
96714395 AH |
22690 | return NULL_RTX; |
22691 | ||
22692 | regno = REGNO (reg); | |
22693 | ||
22694 | /* The duality of the SPE register size wreaks all kinds of havoc. | |
22695 | This is a way of distinguishing r0 in 32-bits from r0 in | |
22696 | 64-bits. */ | |
6cd1d2e2 DJ |
22697 | words = (GET_MODE_SIZE (mode) + UNITS_PER_FP_WORD - 1) / UNITS_PER_FP_WORD; |
22698 | gcc_assert (words <= 4); | |
22699 | for (i = 0; i < words; i++, regno++) | |
22700 | { | |
22701 | if (BYTES_BIG_ENDIAN) | |
22702 | { | |
22703 | parts[2 * i] = gen_rtx_REG (SImode, regno + 1200); | |
22704 | parts[2 * i + 1] = gen_rtx_REG (SImode, regno); | |
22705 | } | |
22706 | else | |
22707 | { | |
22708 | parts[2 * i] = gen_rtx_REG (SImode, regno); | |
22709 | parts[2 * i + 1] = gen_rtx_REG (SImode, regno + 1200); | |
22710 | } | |
22711 | } | |
22712 | ||
22713 | return gen_rtx_PARALLEL (VOIDmode, gen_rtvec_v (words * 2, parts)); | |
96714395 AH |
22714 | } |
22715 | ||
37ea0b7e JM |
22716 | /* Fill in sizes for SPE register high parts in table used by unwinder. */ |
22717 | ||
22718 | static void | |
22719 | rs6000_init_dwarf_reg_sizes_extra (tree address) | |
22720 | { | |
22721 | if (TARGET_SPE) | |
22722 | { | |
22723 | int i; | |
22724 | enum machine_mode mode = TYPE_MODE (char_type_node); | |
bbbbb16a | 22725 | rtx addr = expand_expr (address, NULL_RTX, VOIDmode, EXPAND_NORMAL); |
37ea0b7e JM |
22726 | rtx mem = gen_rtx_MEM (BLKmode, addr); |
22727 | rtx value = gen_int_mode (4, mode); | |
22728 | ||
22729 | for (i = 1201; i < 1232; i++) | |
22730 | { | |
22731 | int column = DWARF_REG_TO_UNWIND_COLUMN (i); | |
22732 | HOST_WIDE_INT offset | |
22733 | = DWARF_FRAME_REGNUM (column) * GET_MODE_SIZE (mode); | |
22734 | ||
22735 | emit_move_insn (adjust_address (mem, mode, offset), value); | |
22736 | } | |
22737 | } | |
22738 | } | |
22739 | ||
93c9d1ba AM |
22740 | /* Map internal gcc register numbers to DWARF2 register numbers. */ |
22741 | ||
22742 | unsigned int | |
22743 | rs6000_dbx_register_number (unsigned int regno) | |
22744 | { | |
22745 | if (regno <= 63 || write_symbols != DWARF2_DEBUG) | |
22746 | return regno; | |
22747 | if (regno == MQ_REGNO) | |
22748 | return 100; | |
1de43f85 | 22749 | if (regno == LR_REGNO) |
93c9d1ba | 22750 | return 108; |
1de43f85 | 22751 | if (regno == CTR_REGNO) |
93c9d1ba AM |
22752 | return 109; |
22753 | if (CR_REGNO_P (regno)) | |
22754 | return regno - CR0_REGNO + 86; | |
22755 | if (regno == XER_REGNO) | |
22756 | return 101; | |
22757 | if (ALTIVEC_REGNO_P (regno)) | |
22758 | return regno - FIRST_ALTIVEC_REGNO + 1124; | |
22759 | if (regno == VRSAVE_REGNO) | |
22760 | return 356; | |
22761 | if (regno == VSCR_REGNO) | |
22762 | return 67; | |
22763 | if (regno == SPE_ACC_REGNO) | |
22764 | return 99; | |
22765 | if (regno == SPEFSCR_REGNO) | |
22766 | return 612; | |
22767 | /* SPE high reg number. We get these values of regno from | |
22768 | rs6000_dwarf_register_span. */ | |
37409796 NS |
22769 | gcc_assert (regno >= 1200 && regno < 1232); |
22770 | return regno; | |
93c9d1ba AM |
22771 | } |
22772 | ||
93f90be6 | 22773 | /* target hook eh_return_filter_mode */ |
f676971a | 22774 | static enum machine_mode |
93f90be6 FJ |
22775 | rs6000_eh_return_filter_mode (void) |
22776 | { | |
22777 | return TARGET_32BIT ? SImode : word_mode; | |
22778 | } | |
22779 | ||
00b79d54 BE |
22780 | /* Target hook for scalar_mode_supported_p. */ |
22781 | static bool | |
22782 | rs6000_scalar_mode_supported_p (enum machine_mode mode) | |
22783 | { | |
22784 | if (DECIMAL_FLOAT_MODE_P (mode)) | |
22785 | return true; | |
22786 | else | |
22787 | return default_scalar_mode_supported_p (mode); | |
22788 | } | |
22789 | ||
f676971a EC |
22790 | /* Target hook for vector_mode_supported_p. */ |
22791 | static bool | |
22792 | rs6000_vector_mode_supported_p (enum machine_mode mode) | |
22793 | { | |
22794 | ||
96038623 DE |
22795 | if (TARGET_PAIRED_FLOAT && PAIRED_VECTOR_MODE (mode)) |
22796 | return true; | |
22797 | ||
f676971a EC |
22798 | if (TARGET_SPE && SPE_VECTOR_MODE (mode)) |
22799 | return true; | |
22800 | ||
22801 | else if (TARGET_ALTIVEC && ALTIVEC_VECTOR_MODE (mode)) | |
22802 | return true; | |
22803 | ||
22804 | else | |
22805 | return false; | |
22806 | } | |
22807 | ||
bb8df8a6 EC |
22808 | /* Target hook for invalid_arg_for_unprototyped_fn. */ |
22809 | static const char * | |
3101faab | 22810 | invalid_arg_for_unprototyped_fn (const_tree typelist, const_tree funcdecl, const_tree val) |
4d3e6fae FJ |
22811 | { |
22812 | return (!rs6000_darwin64_abi | |
22813 | && typelist == 0 | |
22814 | && TREE_CODE (TREE_TYPE (val)) == VECTOR_TYPE | |
22815 | && (funcdecl == NULL_TREE | |
22816 | || (TREE_CODE (funcdecl) == FUNCTION_DECL | |
22817 | && DECL_BUILT_IN_CLASS (funcdecl) != BUILT_IN_MD))) | |
22818 | ? N_("AltiVec argument passed to unprototyped function") | |
22819 | : NULL; | |
22820 | } | |
22821 | ||
3aebbe5f JJ |
22822 | /* For TARGET_SECURE_PLT 32-bit PIC code we can save PIC register |
22823 | setup by using __stack_chk_fail_local hidden function instead of | |
22824 | calling __stack_chk_fail directly. Otherwise it is better to call | |
22825 | __stack_chk_fail directly. */ | |
22826 | ||
22827 | static tree | |
22828 | rs6000_stack_protect_fail (void) | |
22829 | { | |
22830 | return (DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT && flag_pic) | |
22831 | ? default_hidden_stack_protect_fail () | |
22832 | : default_external_stack_protect_fail (); | |
22833 | } | |
22834 | ||
c921bad8 AP |
22835 | void |
22836 | rs6000_final_prescan_insn (rtx insn, rtx *operand ATTRIBUTE_UNUSED, | |
22837 | int num_operands ATTRIBUTE_UNUSED) | |
22838 | { | |
22839 | if (rs6000_warn_cell_microcode) | |
22840 | { | |
22841 | const char *temp; | |
22842 | int insn_code_number = recog_memoized (insn); | |
22843 | location_t location = locator_location (INSN_LOCATOR (insn)); | |
22844 | ||
22845 | /* Punt on insns we cannot recognize. */ | |
22846 | if (insn_code_number < 0) | |
22847 | return; | |
22848 | ||
22849 | temp = get_insn_template (insn_code_number, insn); | |
22850 | ||
22851 | if (get_attr_cell_micro (insn) == CELL_MICRO_ALWAYS) | |
22852 | warning_at (location, OPT_mwarn_cell_microcode, | |
22853 | "emitting microcode insn %s\t[%s] #%d", | |
22854 | temp, insn_data[INSN_CODE (insn)].name, INSN_UID (insn)); | |
22855 | else if (get_attr_cell_micro (insn) == CELL_MICRO_CONDITIONAL) | |
22856 | warning_at (location, OPT_mwarn_cell_microcode, | |
22857 | "emitting conditional microcode insn %s\t[%s] #%d", | |
22858 | temp, insn_data[INSN_CODE (insn)].name, INSN_UID (insn)); | |
22859 | } | |
22860 | } | |
22861 | ||
17211ab5 | 22862 | #include "gt-rs6000.h" |