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9878760c | 1 | /* Subroutines used for code generation on IBM RS/6000. |
9ebbca7d | 2 | Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, |
63b6e069 | 3 | 2000, 2001 Free Software Foundation, Inc. |
fab3bcc3 | 4 | Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu) |
9878760c RK |
5 | |
6 | This file is part of GNU CC. | |
7 | ||
8 | GNU CC is free software; you can redistribute it and/or modify | |
9 | it under the terms of the GNU General Public License as published by | |
10 | the Free Software Foundation; either version 2, or (at your option) | |
11 | any later version. | |
12 | ||
13 | GNU CC is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
19 | along with GNU CC; see the file COPYING. If not, write to | |
c15c9075 RK |
20 | the Free Software Foundation, 59 Temple Place - Suite 330, |
21 | Boston, MA 02111-1307, USA. */ | |
9878760c | 22 | |
956d6950 | 23 | #include "config.h" |
c4d38ccb | 24 | #include "system.h" |
9878760c RK |
25 | #include "rtl.h" |
26 | #include "regs.h" | |
27 | #include "hard-reg-set.h" | |
28 | #include "real.h" | |
29 | #include "insn-config.h" | |
30 | #include "conditions.h" | |
9878760c RK |
31 | #include "insn-attr.h" |
32 | #include "flags.h" | |
33 | #include "recog.h" | |
9878760c | 34 | #include "obstack.h" |
9b30bae2 | 35 | #include "tree.h" |
dfafc897 | 36 | #include "expr.h" |
2fc1c679 | 37 | #include "optabs.h" |
2a430ec1 | 38 | #include "except.h" |
a7df97e6 | 39 | #include "function.h" |
296b8152 | 40 | #include "output.h" |
d5fa86ba | 41 | #include "basic-block.h" |
d0101753 | 42 | #include "integrate.h" |
296b8152 | 43 | #include "toplev.h" |
c8023011 | 44 | #include "ggc.h" |
9ebbca7d GK |
45 | #include "hashtab.h" |
46 | #include "tm_p.h" | |
672a6f42 NB |
47 | #include "target.h" |
48 | #include "target-def.h" | |
3ac88239 | 49 | #include "langhooks.h" |
9b30bae2 | 50 | |
7509c759 MM |
51 | #ifndef TARGET_NO_PROTOTYPE |
52 | #define TARGET_NO_PROTOTYPE 0 | |
53 | #endif | |
54 | ||
5248c961 | 55 | extern int profile_block_flag; |
9878760c RK |
56 | |
57 | #define min(A,B) ((A) < (B) ? (A) : (B)) | |
58 | #define max(A,B) ((A) > (B) ? (A) : (B)) | |
59 | ||
5248c961 RK |
60 | /* Target cpu type */ |
61 | ||
62 | enum processor_type rs6000_cpu; | |
8e3f41e7 MM |
63 | struct rs6000_cpu_select rs6000_select[3] = |
64 | { | |
815cdc52 MM |
65 | /* switch name, tune arch */ |
66 | { (const char *)0, "--with-cpu=", 1, 1 }, | |
67 | { (const char *)0, "-mcpu=", 1, 1 }, | |
68 | { (const char *)0, "-mtune=", 1, 0 }, | |
8e3f41e7 | 69 | }; |
5248c961 | 70 | |
c764f757 RK |
71 | /* Set to non-zero once AIX common-mode calls have been defined. */ |
72 | static int common_mode_defined; | |
c81bebd7 | 73 | |
9878760c RK |
74 | /* Save information from a "cmpxx" operation until the branch or scc is |
75 | emitted. */ | |
9878760c RK |
76 | rtx rs6000_compare_op0, rs6000_compare_op1; |
77 | int rs6000_compare_fp_p; | |
874a0744 | 78 | |
874a0744 MM |
79 | /* Label number of label created for -mrelocatable, to call to so we can |
80 | get the address of the GOT section */ | |
81 | int rs6000_pic_labelno; | |
c81bebd7 | 82 | |
b91da81f | 83 | #ifdef USING_ELFOS_H |
c81bebd7 | 84 | /* Which abi to adhere to */ |
815cdc52 | 85 | const char *rs6000_abi_name = RS6000_ABI_NAME; |
d9407988 MM |
86 | |
87 | /* Semantics of the small data area */ | |
88 | enum rs6000_sdata_type rs6000_sdata = SDATA_DATA; | |
89 | ||
90 | /* Which small data model to use */ | |
815cdc52 | 91 | const char *rs6000_sdata_name = (char *)0; |
9ebbca7d GK |
92 | |
93 | /* Counter for labels which are to be placed in .fixup. */ | |
94 | int fixuplabelno = 0; | |
874a0744 | 95 | #endif |
4697a36c | 96 | |
b6c9286a MM |
97 | /* ABI enumeration available for subtarget to use. */ |
98 | enum rs6000_abi rs6000_current_abi; | |
99 | ||
0ac081f6 AH |
100 | /* ABI string from -mabi= option. */ |
101 | const char *rs6000_abi_string; | |
102 | ||
38c1f2d7 | 103 | /* Debug flags */ |
815cdc52 | 104 | const char *rs6000_debug_name; |
38c1f2d7 MM |
105 | int rs6000_debug_stack; /* debug stack applications */ |
106 | int rs6000_debug_arg; /* debug argument handling */ | |
107 | ||
108 | /* Flag to say the TOC is initialized */ | |
109 | int toc_initialized; | |
9ebbca7d | 110 | char toc_label_name[10]; |
38c1f2d7 | 111 | |
9ebbca7d GK |
112 | /* Alias set for saves and restores from the rs6000 stack. */ |
113 | static int rs6000_sr_alias_set; | |
c8023011 | 114 | |
9ebbca7d GK |
115 | static void rs6000_add_gc_roots PARAMS ((void)); |
116 | static int num_insns_constant_wide PARAMS ((HOST_WIDE_INT)); | |
117 | static rtx expand_block_move_mem PARAMS ((enum machine_mode, rtx, rtx)); | |
39a10a29 GK |
118 | static void validate_condition_mode |
119 | PARAMS ((enum rtx_code, enum machine_mode)); | |
120 | static rtx rs6000_generate_compare PARAMS ((enum rtx_code)); | |
e50f5f3d | 121 | static void rs6000_maybe_dead PARAMS ((rtx)); |
9ebbca7d GK |
122 | static void rs6000_emit_stack_tie PARAMS ((void)); |
123 | static void rs6000_frame_related PARAMS ((rtx, rtx, HOST_WIDE_INT, rtx, rtx)); | |
124 | static void rs6000_emit_allocate_stack PARAMS ((HOST_WIDE_INT, int)); | |
125 | static unsigned rs6000_hash_constant PARAMS ((rtx)); | |
126 | static unsigned toc_hash_function PARAMS ((const void *)); | |
127 | static int toc_hash_eq PARAMS ((const void *, const void *)); | |
2eba1afa | 128 | static int toc_hash_mark_entry PARAMS ((void **, void *)); |
9ebbca7d GK |
129 | static void toc_hash_mark_table PARAMS ((void *)); |
130 | static int constant_pool_expr_1 PARAMS ((rtx, int *, int *)); | |
6fee9e99 NC |
131 | static void rs6000_free_machine_status PARAMS ((struct function *)); |
132 | static void rs6000_init_machine_status PARAMS ((struct function *)); | |
71f123ca | 133 | static int rs6000_ra_ever_killed PARAMS ((void)); |
91d231cb JM |
134 | static tree rs6000_handle_longcall_attribute PARAMS ((tree *, tree, tree, int, bool *)); |
135 | const struct attribute_spec rs6000_attribute_table[]; | |
08c148a8 NB |
136 | static void rs6000_output_function_prologue PARAMS ((FILE *, HOST_WIDE_INT)); |
137 | static void rs6000_output_function_epilogue PARAMS ((FILE *, HOST_WIDE_INT)); | |
2bfcf297 DB |
138 | static rtx rs6000_emit_set_long_const PARAMS ((rtx, |
139 | HOST_WIDE_INT, HOST_WIDE_INT)); | |
7c262518 RH |
140 | #if TARGET_ELF |
141 | static unsigned int rs6000_elf_section_type_flags PARAMS ((tree, const char *, | |
142 | int)); | |
d9f6800d RH |
143 | static void rs6000_elf_asm_out_constructor PARAMS ((rtx, int)); |
144 | static void rs6000_elf_asm_out_destructor PARAMS ((rtx, int)); | |
7c262518 RH |
145 | #endif |
146 | #ifdef OBJECT_FORMAT_COFF | |
715bdd29 | 147 | static void xcoff_asm_named_section PARAMS ((const char *, unsigned int)); |
7c262518 | 148 | #endif |
c237e94a ZW |
149 | static int rs6000_adjust_cost PARAMS ((rtx, rtx, rtx, int)); |
150 | static int rs6000_adjust_priority PARAMS ((rtx, int)); | |
151 | static int rs6000_issue_rate PARAMS ((void)); | |
152 | ||
0ac081f6 AH |
153 | static void rs6000_init_builtins PARAMS ((tree)); |
154 | static void altivec_init_builtins PARAMS ((void)); | |
155 | static rtx rs6000_expand_builtin PARAMS ((tree, rtx, rtx, enum machine_mode, int)); | |
00b960c7 | 156 | static rtx altivec_expand_builtin PARAMS ((tree, rtx)); |
0ac081f6 AH |
157 | static rtx altivec_expand_binop_builtin PARAMS ((enum insn_code, tree, rtx)); |
158 | ||
159 | static void rs6000_parse_abi_options PARAMS ((void)); | |
00b960c7 AH |
160 | static int first_altivec_reg_to_save PARAMS ((void)); |
161 | static unsigned int compute_vrsave_mask PARAMS ((void)); | |
162 | static void is_altivec_return_reg PARAMS ((rtx, void *)); | |
163 | int vrsave_operation PARAMS ((rtx, enum machine_mode)); | |
164 | static rtx generate_set_vrsave PARAMS ((rtx, rs6000_stack_t *)); | |
c81bebd7 MM |
165 | \f |
166 | /* Default register names. */ | |
167 | char rs6000_reg_names[][8] = | |
168 | { | |
802a0058 MM |
169 | "0", "1", "2", "3", "4", "5", "6", "7", |
170 | "8", "9", "10", "11", "12", "13", "14", "15", | |
171 | "16", "17", "18", "19", "20", "21", "22", "23", | |
172 | "24", "25", "26", "27", "28", "29", "30", "31", | |
173 | "0", "1", "2", "3", "4", "5", "6", "7", | |
174 | "8", "9", "10", "11", "12", "13", "14", "15", | |
175 | "16", "17", "18", "19", "20", "21", "22", "23", | |
176 | "24", "25", "26", "27", "28", "29", "30", "31", | |
177 | "mq", "lr", "ctr","ap", | |
178 | "0", "1", "2", "3", "4", "5", "6", "7", | |
0ac081f6 AH |
179 | "xer", |
180 | /* AltiVec registers. */ | |
0cd5e3a1 AH |
181 | "0", "1", "2", "3", "4", "5", "6", "7", |
182 | "8", "9", "10", "11", "12", "13", "14", "15", | |
183 | "16", "17", "18", "19", "20", "21", "22", "23", | |
184 | "24", "25", "26", "27", "28", "29", "30", "31", | |
0ac081f6 | 185 | "vrsave" |
c81bebd7 MM |
186 | }; |
187 | ||
188 | #ifdef TARGET_REGNAMES | |
8b60264b | 189 | static const char alt_reg_names[][8] = |
c81bebd7 | 190 | { |
802a0058 MM |
191 | "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7", |
192 | "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15", | |
193 | "%r16", "%r17", "%r18", "%r19", "%r20", "%r21", "%r22", "%r23", | |
194 | "%r24", "%r25", "%r26", "%r27", "%r28", "%r29", "%r30", "%r31", | |
195 | "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7", | |
196 | "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15", | |
197 | "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23", | |
198 | "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31", | |
199 | "mq", "lr", "ctr", "ap", | |
200 | "%cr0", "%cr1", "%cr2", "%cr3", "%cr4", "%cr5", "%cr6", "%cr7", | |
0ac081f6 AH |
201 | "xer", |
202 | /* AltiVec registers. */ | |
203 | "%v0", "%v1", "%v2", "%v3", "%v4", "%v5", "%v6", "%v7", | |
204 | "%v8", "%v9", "%v10", "%v11", "%v12", "%v13", "%v14", "%v15", | |
205 | "%v16", "%v17", "%v18", "%v19", "%v20", "%v21", "%v22", "%v23", | |
206 | "%v24", "%v25", "%v26", "%v27", "%v28", "%v29", "%v30", "%v31", | |
207 | "%vrsave" | |
c81bebd7 MM |
208 | }; |
209 | #endif | |
9878760c | 210 | \f |
daf11973 MM |
211 | #ifndef MASK_STRICT_ALIGN |
212 | #define MASK_STRICT_ALIGN 0 | |
213 | #endif | |
672a6f42 NB |
214 | \f |
215 | /* Initialize the GCC target structure. */ | |
91d231cb JM |
216 | #undef TARGET_ATTRIBUTE_TABLE |
217 | #define TARGET_ATTRIBUTE_TABLE rs6000_attribute_table | |
daf11973 | 218 | |
08c148a8 NB |
219 | #undef TARGET_ASM_FUNCTION_PROLOGUE |
220 | #define TARGET_ASM_FUNCTION_PROLOGUE rs6000_output_function_prologue | |
221 | #undef TARGET_ASM_FUNCTION_EPILOGUE | |
222 | #define TARGET_ASM_FUNCTION_EPILOGUE rs6000_output_function_epilogue | |
223 | ||
7c262518 RH |
224 | #if TARGET_ELF |
225 | #undef TARGET_SECTION_TYPE_FLAGS | |
226 | #define TARGET_SECTION_TYPE_FLAGS rs6000_elf_section_type_flags | |
227 | #endif | |
228 | ||
c237e94a ZW |
229 | #undef TARGET_SCHED_ISSUE_RATE |
230 | #define TARGET_SCHED_ISSUE_RATE rs6000_issue_rate | |
231 | #undef TARGET_SCHED_ADJUST_COST | |
232 | #define TARGET_SCHED_ADJUST_COST rs6000_adjust_cost | |
233 | #undef TARGET_SCHED_ADJUST_PRIORITY | |
234 | #define TARGET_SCHED_ADJUST_PRIORITY rs6000_adjust_priority | |
235 | ||
0ac081f6 AH |
236 | #undef TARGET_INIT_BUILTINS |
237 | #define TARGET_INIT_BUILTINS rs6000_init_builtins | |
238 | ||
239 | #undef TARGET_EXPAND_BUILTIN | |
240 | #define TARGET_EXPAND_BUILTIN rs6000_expand_builtin | |
241 | ||
00b960c7 AH |
242 | /* The VRSAVE bitmask puts bit %v0 as the most significant bit. */ |
243 | #define ALTIVEC_REG_BIT(REGNO) (0x80000000 >> ((REGNO) - FIRST_ALTIVEC_REGNO)) | |
244 | ||
f6897b10 | 245 | struct gcc_target targetm = TARGET_INITIALIZER; |
672a6f42 | 246 | \f |
5248c961 RK |
247 | /* Override command line options. Mostly we process the processor |
248 | type and sometimes adjust other TARGET_ options. */ | |
249 | ||
250 | void | |
8e3f41e7 | 251 | rs6000_override_options (default_cpu) |
d330fd93 | 252 | const char *default_cpu; |
5248c961 | 253 | { |
c4d38ccb | 254 | size_t i, j; |
8e3f41e7 | 255 | struct rs6000_cpu_select *ptr; |
5248c961 | 256 | |
85638c0d RK |
257 | /* Simplify the entries below by making a mask for any POWER |
258 | variant and any PowerPC variant. */ | |
259 | ||
938937d8 | 260 | #define POWER_MASKS (MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING) |
68c49ffa RK |
261 | #define POWERPC_MASKS (MASK_POWERPC | MASK_PPC_GPOPT \ |
262 | | MASK_PPC_GFXOPT | MASK_POWERPC64) | |
263 | #define POWERPC_OPT_MASKS (MASK_PPC_GPOPT | MASK_PPC_GFXOPT) | |
85638c0d | 264 | |
5248c961 RK |
265 | static struct ptt |
266 | { | |
8b60264b KG |
267 | const char *const name; /* Canonical processor name. */ |
268 | const enum processor_type processor; /* Processor type enum value. */ | |
269 | const int target_enable; /* Target flags to enable. */ | |
270 | const int target_disable; /* Target flags to disable. */ | |
271 | } const processor_target_table[] | |
cf27b467 MM |
272 | = {{"common", PROCESSOR_COMMON, MASK_NEW_MNEMONICS, |
273 | POWER_MASKS | POWERPC_MASKS}, | |
db7f1e43 | 274 | {"power", PROCESSOR_POWER, |
938937d8 | 275 | MASK_POWER | MASK_MULTIPLE | MASK_STRING, |
db7f1e43 | 276 | MASK_POWER2 | POWERPC_MASKS | MASK_NEW_MNEMONICS}, |
8e3f41e7 MM |
277 | {"power2", PROCESSOR_POWER, |
278 | MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING, | |
279 | POWERPC_MASKS | MASK_NEW_MNEMONICS}, | |
c71791e0 DE |
280 | {"power3", PROCESSOR_PPC630, |
281 | MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS, | |
282 | POWER_MASKS | MASK_PPC_GPOPT}, | |
db7f1e43 RK |
283 | {"powerpc", PROCESSOR_POWERPC, |
284 | MASK_POWERPC | MASK_NEW_MNEMONICS, | |
68c49ffa | 285 | POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64}, |
3cb999d8 DE |
286 | {"powerpc64", PROCESSOR_POWERPC64, |
287 | MASK_POWERPC | MASK_POWERPC64 | MASK_NEW_MNEMONICS, | |
288 | POWER_MASKS | POWERPC_OPT_MASKS}, | |
db7f1e43 | 289 | {"rios", PROCESSOR_RIOS1, |
938937d8 | 290 | MASK_POWER | MASK_MULTIPLE | MASK_STRING, |
db7f1e43 RK |
291 | MASK_POWER2 | POWERPC_MASKS | MASK_NEW_MNEMONICS}, |
292 | {"rios1", PROCESSOR_RIOS1, | |
938937d8 | 293 | MASK_POWER | MASK_MULTIPLE | MASK_STRING, |
db7f1e43 RK |
294 | MASK_POWER2 | POWERPC_MASKS | MASK_NEW_MNEMONICS}, |
295 | {"rsc", PROCESSOR_PPC601, | |
938937d8 | 296 | MASK_POWER | MASK_MULTIPLE | MASK_STRING, |
db7f1e43 RK |
297 | MASK_POWER2 | POWERPC_MASKS | MASK_NEW_MNEMONICS}, |
298 | {"rsc1", PROCESSOR_PPC601, | |
938937d8 | 299 | MASK_POWER | MASK_MULTIPLE | MASK_STRING, |
db7f1e43 RK |
300 | MASK_POWER2 | POWERPC_MASKS | MASK_NEW_MNEMONICS}, |
301 | {"rios2", PROCESSOR_RIOS2, | |
938937d8 | 302 | MASK_POWER | MASK_MULTIPLE | MASK_STRING | MASK_POWER2, |
db7f1e43 | 303 | POWERPC_MASKS | MASK_NEW_MNEMONICS}, |
3cb999d8 DE |
304 | {"rs64a", PROCESSOR_RS64A, |
305 | MASK_POWERPC | MASK_NEW_MNEMONICS, | |
306 | POWER_MASKS | POWERPC_OPT_MASKS}, | |
a3a1dbf6 MM |
307 | {"401", PROCESSOR_PPC403, |
308 | MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS, | |
309 | POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64}, | |
49a0b204 | 310 | {"403", PROCESSOR_PPC403, |
daf11973 | 311 | MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS | MASK_STRICT_ALIGN, |
49a0b204 | 312 | POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64}, |
cf27b467 MM |
313 | {"505", PROCESSOR_MPCCORE, |
314 | MASK_POWERPC | MASK_NEW_MNEMONICS, | |
315 | POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64}, | |
5248c961 | 316 | {"601", PROCESSOR_PPC601, |
938937d8 | 317 | MASK_POWER | MASK_POWERPC | MASK_NEW_MNEMONICS | MASK_MULTIPLE | MASK_STRING, |
68c49ffa | 318 | MASK_POWER2 | POWERPC_OPT_MASKS | MASK_POWERPC64}, |
1ec26da6 | 319 | {"602", PROCESSOR_PPC603, |
cf27b467 MM |
320 | MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS, |
321 | POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64}, | |
5248c961 | 322 | {"603", PROCESSOR_PPC603, |
68c49ffa RK |
323 | MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS, |
324 | POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64}, | |
b6c9286a MM |
325 | {"603e", PROCESSOR_PPC603, |
326 | MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS, | |
327 | POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64}, | |
b5370a88 | 328 | {"ec603e", PROCESSOR_PPC603, |
a3a1dbf6 MM |
329 | MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS, |
330 | POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64}, | |
5248c961 | 331 | {"604", PROCESSOR_PPC604, |
b6c9286a MM |
332 | MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS, |
333 | POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64}, | |
cac8ce95 | 334 | {"604e", PROCESSOR_PPC604e, |
07e6159a MM |
335 | MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS, |
336 | POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64}, | |
b6c9286a | 337 | {"620", PROCESSOR_PPC620, |
68c49ffa | 338 | MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS, |
a260abc9 | 339 | POWER_MASKS | MASK_PPC_GPOPT}, |
3cb999d8 DE |
340 | {"630", PROCESSOR_PPC630, |
341 | MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS, | |
342 | POWER_MASKS | MASK_PPC_GPOPT}, | |
bef84347 VM |
343 | {"740", PROCESSOR_PPC750, |
344 | MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS, | |
345 | POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64}, | |
346 | {"750", PROCESSOR_PPC750, | |
347 | MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS, | |
348 | POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64}, | |
a4f6c312 SS |
349 | {"7400", PROCESSOR_PPC7400, |
350 | MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS, | |
351 | POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64}, | |
352 | {"7450", PROCESSOR_PPC7450, | |
353 | MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS, | |
354 | POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64}, | |
07e6159a MM |
355 | {"801", PROCESSOR_MPCCORE, |
356 | MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS, | |
357 | POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64}, | |
cf27b467 MM |
358 | {"821", PROCESSOR_MPCCORE, |
359 | MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS, | |
360 | POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64}, | |
07e6159a MM |
361 | {"823", PROCESSOR_MPCCORE, |
362 | MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS, | |
363 | POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64}, | |
cf27b467 MM |
364 | {"860", PROCESSOR_MPCCORE, |
365 | MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS, | |
366 | POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64}}; | |
5248c961 | 367 | |
c4d38ccb | 368 | size_t ptt_size = sizeof (processor_target_table) / sizeof (struct ptt); |
5248c961 | 369 | |
a4f6c312 SS |
370 | /* Save current -mmultiple/-mno-multiple status. */ |
371 | int multiple = TARGET_MULTIPLE; | |
372 | /* Save current -mstring/-mno-string status. */ | |
373 | int string = TARGET_STRING; | |
8a61d227 | 374 | |
5248c961 RK |
375 | profile_block_flag = 0; |
376 | ||
a4f6c312 | 377 | /* Identify the processor type. */ |
8e3f41e7 | 378 | rs6000_select[0].string = default_cpu; |
3cb999d8 | 379 | rs6000_cpu = TARGET_POWERPC64 ? PROCESSOR_DEFAULT64 : PROCESSOR_DEFAULT; |
8e3f41e7 | 380 | |
b6a1cbae | 381 | for (i = 0; i < ARRAY_SIZE (rs6000_select); i++) |
5248c961 | 382 | { |
8e3f41e7 MM |
383 | ptr = &rs6000_select[i]; |
384 | if (ptr->string != (char *)0 && ptr->string[0] != '\0') | |
5248c961 | 385 | { |
8e3f41e7 MM |
386 | for (j = 0; j < ptt_size; j++) |
387 | if (! strcmp (ptr->string, processor_target_table[j].name)) | |
388 | { | |
389 | if (ptr->set_tune_p) | |
390 | rs6000_cpu = processor_target_table[j].processor; | |
391 | ||
392 | if (ptr->set_arch_p) | |
393 | { | |
394 | target_flags |= processor_target_table[j].target_enable; | |
395 | target_flags &= ~processor_target_table[j].target_disable; | |
396 | } | |
397 | break; | |
398 | } | |
399 | ||
4406229e | 400 | if (j == ptt_size) |
8e3f41e7 | 401 | error ("bad value (%s) for %s switch", ptr->string, ptr->name); |
5248c961 RK |
402 | } |
403 | } | |
8a61d227 | 404 | |
a4f6c312 SS |
405 | /* If we are optimizing big endian systems for space, use the store |
406 | multiple instructions. */ | |
ef792183 MM |
407 | if (BYTES_BIG_ENDIAN && optimize_size) |
408 | target_flags |= MASK_MULTIPLE; | |
409 | ||
8a61d227 MM |
410 | /* If -mmultiple or -mno-multiple was explicitly used, don't |
411 | override with the processor default */ | |
412 | if (TARGET_MULTIPLE_SET) | |
413 | target_flags = (target_flags & ~MASK_MULTIPLE) | multiple; | |
7e69e155 | 414 | |
a4f6c312 SS |
415 | /* If -mstring or -mno-string was explicitly used, don't override |
416 | with the processor default. */ | |
938937d8 | 417 | if (TARGET_STRING_SET) |
1f5515bf | 418 | target_flags = (target_flags & ~MASK_STRING) | string; |
938937d8 | 419 | |
a4f6c312 SS |
420 | /* Don't allow -mmultiple or -mstring on little endian systems |
421 | unless the cpu is a 750, because the hardware doesn't support the | |
422 | instructions used in little endian mode, and causes an alignment | |
423 | trap. The 750 does not cause an alignment trap (except when the | |
424 | target is unaligned). */ | |
bef84347 | 425 | |
bfc79d3b | 426 | if (! BYTES_BIG_ENDIAN && rs6000_cpu != PROCESSOR_PPC750) |
7e69e155 MM |
427 | { |
428 | if (TARGET_MULTIPLE) | |
429 | { | |
430 | target_flags &= ~MASK_MULTIPLE; | |
431 | if (TARGET_MULTIPLE_SET) | |
432 | warning ("-mmultiple is not supported on little endian systems"); | |
433 | } | |
434 | ||
435 | if (TARGET_STRING) | |
436 | { | |
437 | target_flags &= ~MASK_STRING; | |
938937d8 MM |
438 | if (TARGET_STRING_SET) |
439 | warning ("-mstring is not supported on little endian systems"); | |
7e69e155 MM |
440 | } |
441 | } | |
3933e0e1 | 442 | |
2bfcf297 | 443 | if (flag_pic && DEFAULT_ABI == ABI_AIX) |
a260abc9 | 444 | { |
2bfcf297 | 445 | warning ("-f%s ignored (all code is position independent)", |
a260abc9 DE |
446 | (flag_pic > 1) ? "PIC" : "pic"); |
447 | flag_pic = 0; | |
448 | } | |
449 | ||
2bfcf297 | 450 | #ifdef XCOFF_DEBUGGING_INFO |
9861b0c9 | 451 | if (flag_function_sections && (write_symbols != NO_DEBUG) |
2bfcf297 | 452 | && DEFAULT_ABI == ABI_AIX) |
9861b0c9 DE |
453 | { |
454 | warning ("-ffunction-sections disabled on AIX when debugging"); | |
455 | flag_function_sections = 0; | |
456 | } | |
457 | ||
458 | if (flag_data_sections && (DEFAULT_ABI == ABI_AIX)) | |
459 | { | |
460 | warning ("-fdata-sections not supported on AIX"); | |
461 | flag_data_sections = 0; | |
462 | } | |
2bfcf297 | 463 | #endif |
9861b0c9 | 464 | |
38c1f2d7 MM |
465 | /* Set debug flags */ |
466 | if (rs6000_debug_name) | |
467 | { | |
bfc79d3b | 468 | if (! strcmp (rs6000_debug_name, "all")) |
38c1f2d7 | 469 | rs6000_debug_stack = rs6000_debug_arg = 1; |
bfc79d3b | 470 | else if (! strcmp (rs6000_debug_name, "stack")) |
38c1f2d7 | 471 | rs6000_debug_stack = 1; |
bfc79d3b | 472 | else if (! strcmp (rs6000_debug_name, "arg")) |
38c1f2d7 MM |
473 | rs6000_debug_arg = 1; |
474 | else | |
475 | error ("Unknown -mdebug-%s switch", rs6000_debug_name); | |
476 | } | |
477 | ||
0ac081f6 AH |
478 | /* Handle -mabi= options. */ |
479 | rs6000_parse_abi_options (); | |
480 | ||
c81bebd7 | 481 | #ifdef TARGET_REGNAMES |
a4f6c312 SS |
482 | /* If the user desires alternate register names, copy in the |
483 | alternate names now. */ | |
c81bebd7 | 484 | if (TARGET_REGNAMES) |
4e135bdd | 485 | memcpy (rs6000_reg_names, alt_reg_names, sizeof (rs6000_reg_names)); |
c81bebd7 MM |
486 | #endif |
487 | ||
3933e0e1 MM |
488 | #ifdef SUBTARGET_OVERRIDE_OPTIONS |
489 | SUBTARGET_OVERRIDE_OPTIONS; | |
490 | #endif | |
c8023011 MM |
491 | |
492 | /* Register global variables with the garbage collector. */ | |
493 | rs6000_add_gc_roots (); | |
9ebbca7d GK |
494 | |
495 | /* Allocate an alias set for register saves & restores from stack. */ | |
496 | rs6000_sr_alias_set = new_alias_set (); | |
497 | ||
498 | if (TARGET_TOC) | |
499 | ASM_GENERATE_INTERNAL_LABEL (toc_label_name, "LCTOC", 1); | |
71f123ca FS |
500 | |
501 | /* Arrange to save and restore machine status around nested functions. */ | |
502 | init_machine_status = rs6000_init_machine_status; | |
71f123ca | 503 | free_machine_status = rs6000_free_machine_status; |
5248c961 | 504 | } |
5accd822 | 505 | |
0ac081f6 | 506 | /* Handle -mabi= options. */ |
00b960c7 AH |
507 | static void |
508 | rs6000_parse_abi_options () | |
0ac081f6 AH |
509 | { |
510 | if (rs6000_abi_string == 0) | |
511 | return; | |
512 | else if (! strcmp (rs6000_abi_string, "altivec")) | |
513 | target_flags |= MASK_ALTIVEC_ABI; | |
514 | else | |
515 | error ("Unknown ABI specified: '%s'", rs6000_abi_string); | |
516 | } | |
517 | ||
5accd822 DE |
518 | void |
519 | optimization_options (level, size) | |
e2c953b6 | 520 | int level ATTRIBUTE_UNUSED; |
5accd822 DE |
521 | int size ATTRIBUTE_UNUSED; |
522 | { | |
5accd822 | 523 | } |
3cfa4909 MM |
524 | \f |
525 | /* Do anything needed at the start of the asm file. */ | |
526 | ||
527 | void | |
528 | rs6000_file_start (file, default_cpu) | |
529 | FILE *file; | |
d330fd93 | 530 | const char *default_cpu; |
3cfa4909 | 531 | { |
c4d38ccb | 532 | size_t i; |
3cfa4909 | 533 | char buffer[80]; |
d330fd93 | 534 | const char *start = buffer; |
3cfa4909 MM |
535 | struct rs6000_cpu_select *ptr; |
536 | ||
537 | if (flag_verbose_asm) | |
538 | { | |
539 | sprintf (buffer, "\n%s rs6000/powerpc options:", ASM_COMMENT_START); | |
540 | rs6000_select[0].string = default_cpu; | |
541 | ||
b6a1cbae | 542 | for (i = 0; i < ARRAY_SIZE (rs6000_select); i++) |
3cfa4909 MM |
543 | { |
544 | ptr = &rs6000_select[i]; | |
545 | if (ptr->string != (char *)0 && ptr->string[0] != '\0') | |
546 | { | |
547 | fprintf (file, "%s %s%s", start, ptr->name, ptr->string); | |
548 | start = ""; | |
549 | } | |
550 | } | |
551 | ||
b91da81f | 552 | #ifdef USING_ELFOS_H |
3cfa4909 MM |
553 | switch (rs6000_sdata) |
554 | { | |
555 | case SDATA_NONE: fprintf (file, "%s -msdata=none", start); start = ""; break; | |
556 | case SDATA_DATA: fprintf (file, "%s -msdata=data", start); start = ""; break; | |
557 | case SDATA_SYSV: fprintf (file, "%s -msdata=sysv", start); start = ""; break; | |
558 | case SDATA_EABI: fprintf (file, "%s -msdata=eabi", start); start = ""; break; | |
559 | } | |
560 | ||
561 | if (rs6000_sdata && g_switch_value) | |
562 | { | |
563 | fprintf (file, "%s -G %d", start, g_switch_value); | |
564 | start = ""; | |
565 | } | |
566 | #endif | |
567 | ||
568 | if (*start == '\0') | |
949ea356 | 569 | putc ('\n', file); |
3cfa4909 MM |
570 | } |
571 | } | |
572 | ||
24d304eb RK |
573 | \f |
574 | /* Create a CONST_DOUBLE from a string. */ | |
575 | ||
576 | struct rtx_def * | |
577 | rs6000_float_const (string, mode) | |
d330fd93 | 578 | const char *string; |
24d304eb RK |
579 | enum machine_mode mode; |
580 | { | |
ca5adc63 GK |
581 | REAL_VALUE_TYPE value; |
582 | value = REAL_VALUE_ATOF (string, mode); | |
24d304eb RK |
583 | return immed_real_const_1 (value, mode); |
584 | } | |
5248c961 | 585 | \f |
9878760c RK |
586 | /* Return non-zero if this function is known to have a null epilogue. */ |
587 | ||
588 | int | |
589 | direct_return () | |
590 | { | |
4697a36c MM |
591 | if (reload_completed) |
592 | { | |
593 | rs6000_stack_t *info = rs6000_stack_info (); | |
594 | ||
595 | if (info->first_gp_reg_save == 32 | |
596 | && info->first_fp_reg_save == 64 | |
00b960c7 | 597 | && info->first_altivec_reg_save == LAST_ALTIVEC_REGNO + 1 |
c81fc13e DE |
598 | && ! info->lr_save_p |
599 | && ! info->cr_save_p | |
00b960c7 | 600 | && info->vrsave_mask == 0 |
c81fc13e | 601 | && ! info->push_p) |
4697a36c MM |
602 | return 1; |
603 | } | |
604 | ||
605 | return 0; | |
9878760c RK |
606 | } |
607 | ||
608 | /* Returns 1 always. */ | |
609 | ||
610 | int | |
611 | any_operand (op, mode) | |
592696dd | 612 | rtx op ATTRIBUTE_UNUSED; |
296b8152 | 613 | enum machine_mode mode ATTRIBUTE_UNUSED; |
9878760c RK |
614 | { |
615 | return 1; | |
616 | } | |
617 | ||
a4f6c312 | 618 | /* Returns 1 if op is the count register. */ |
38c1f2d7 | 619 | int |
a4f6c312 | 620 | count_register_operand (op, mode) |
592696dd | 621 | rtx op; |
296b8152 | 622 | enum machine_mode mode ATTRIBUTE_UNUSED; |
b6c9286a MM |
623 | { |
624 | if (GET_CODE (op) != REG) | |
625 | return 0; | |
626 | ||
627 | if (REGNO (op) == COUNT_REGISTER_REGNUM) | |
628 | return 1; | |
629 | ||
630 | if (REGNO (op) > FIRST_PSEUDO_REGISTER) | |
631 | return 1; | |
632 | ||
633 | return 0; | |
634 | } | |
635 | ||
38c1f2d7 | 636 | int |
a4f6c312 | 637 | xer_operand (op, mode) |
592696dd | 638 | rtx op; |
296b8152 | 639 | enum machine_mode mode ATTRIBUTE_UNUSED; |
802a0058 MM |
640 | { |
641 | if (GET_CODE (op) != REG) | |
642 | return 0; | |
643 | ||
9ebbca7d | 644 | if (XER_REGNO_P (REGNO (op))) |
802a0058 MM |
645 | return 1; |
646 | ||
802a0058 MM |
647 | return 0; |
648 | } | |
649 | ||
9878760c RK |
650 | /* Return 1 if OP is a constant that can fit in a D field. */ |
651 | ||
652 | int | |
653 | short_cint_operand (op, mode) | |
592696dd | 654 | rtx op; |
296b8152 | 655 | enum machine_mode mode ATTRIBUTE_UNUSED; |
9878760c | 656 | { |
5f59ecb7 DE |
657 | return (GET_CODE (op) == CONST_INT |
658 | && CONST_OK_FOR_LETTER_P (INTVAL (op), 'I')); | |
9878760c RK |
659 | } |
660 | ||
5519a4f9 | 661 | /* Similar for an unsigned D field. */ |
9878760c RK |
662 | |
663 | int | |
664 | u_short_cint_operand (op, mode) | |
592696dd | 665 | rtx op; |
296b8152 | 666 | enum machine_mode mode ATTRIBUTE_UNUSED; |
9878760c | 667 | { |
19684119 | 668 | return (GET_CODE (op) == CONST_INT |
5f59ecb7 | 669 | && CONST_OK_FOR_LETTER_P (INTVAL (op), 'K')); |
9878760c RK |
670 | } |
671 | ||
dcfedcd0 RK |
672 | /* Return 1 if OP is a CONST_INT that cannot fit in a signed D field. */ |
673 | ||
674 | int | |
675 | non_short_cint_operand (op, mode) | |
592696dd | 676 | rtx op; |
296b8152 | 677 | enum machine_mode mode ATTRIBUTE_UNUSED; |
dcfedcd0 RK |
678 | { |
679 | return (GET_CODE (op) == CONST_INT | |
a7653a2c | 680 | && (unsigned HOST_WIDE_INT) (INTVAL (op) + 0x8000) >= 0x10000); |
dcfedcd0 RK |
681 | } |
682 | ||
2bfcf297 DB |
683 | /* Returns 1 if OP is a CONST_INT that is a positive value |
684 | and an exact power of 2. */ | |
685 | ||
686 | int | |
687 | exact_log2_cint_operand (op, mode) | |
592696dd | 688 | rtx op; |
2bfcf297 DB |
689 | enum machine_mode mode ATTRIBUTE_UNUSED; |
690 | { | |
691 | return (GET_CODE (op) == CONST_INT | |
692 | && INTVAL (op) > 0 | |
693 | && exact_log2 (INTVAL (op)) >= 0); | |
694 | } | |
695 | ||
9878760c RK |
696 | /* Returns 1 if OP is a register that is not special (i.e., not MQ, |
697 | ctr, or lr). */ | |
698 | ||
699 | int | |
cd2b37d9 | 700 | gpc_reg_operand (op, mode) |
592696dd | 701 | rtx op; |
9878760c RK |
702 | enum machine_mode mode; |
703 | { | |
704 | return (register_operand (op, mode) | |
802a0058 | 705 | && (GET_CODE (op) != REG |
9ebbca7d GK |
706 | || (REGNO (op) >= ARG_POINTER_REGNUM |
707 | && !XER_REGNO_P (REGNO (op))) | |
708 | || REGNO (op) < MQ_REGNO)); | |
9878760c RK |
709 | } |
710 | ||
711 | /* Returns 1 if OP is either a pseudo-register or a register denoting a | |
712 | CR field. */ | |
713 | ||
714 | int | |
715 | cc_reg_operand (op, mode) | |
592696dd | 716 | rtx op; |
9878760c RK |
717 | enum machine_mode mode; |
718 | { | |
719 | return (register_operand (op, mode) | |
720 | && (GET_CODE (op) != REG | |
721 | || REGNO (op) >= FIRST_PSEUDO_REGISTER | |
722 | || CR_REGNO_P (REGNO (op)))); | |
723 | } | |
724 | ||
815cdc52 MM |
725 | /* Returns 1 if OP is either a pseudo-register or a register denoting a |
726 | CR field that isn't CR0. */ | |
727 | ||
728 | int | |
729 | cc_reg_not_cr0_operand (op, mode) | |
592696dd | 730 | rtx op; |
815cdc52 MM |
731 | enum machine_mode mode; |
732 | { | |
733 | return (register_operand (op, mode) | |
734 | && (GET_CODE (op) != REG | |
735 | || REGNO (op) >= FIRST_PSEUDO_REGISTER | |
736 | || CR_REGNO_NOT_CR0_P (REGNO (op)))); | |
737 | } | |
738 | ||
a4f6c312 SS |
739 | /* Returns 1 if OP is either a constant integer valid for a D-field or |
740 | a non-special register. If a register, it must be in the proper | |
741 | mode unless MODE is VOIDmode. */ | |
9878760c RK |
742 | |
743 | int | |
744 | reg_or_short_operand (op, mode) | |
592696dd | 745 | rtx op; |
9878760c RK |
746 | enum machine_mode mode; |
747 | { | |
f5a28898 | 748 | return short_cint_operand (op, mode) || gpc_reg_operand (op, mode); |
9878760c RK |
749 | } |
750 | ||
a4f6c312 SS |
751 | /* Similar, except check if the negation of the constant would be |
752 | valid for a D-field. */ | |
9878760c RK |
753 | |
754 | int | |
755 | reg_or_neg_short_operand (op, mode) | |
592696dd | 756 | rtx op; |
9878760c RK |
757 | enum machine_mode mode; |
758 | { | |
759 | if (GET_CODE (op) == CONST_INT) | |
760 | return CONST_OK_FOR_LETTER_P (INTVAL (op), 'P'); | |
761 | ||
cd2b37d9 | 762 | return gpc_reg_operand (op, mode); |
9878760c RK |
763 | } |
764 | ||
a4f6c312 SS |
765 | /* Return 1 if the operand is either a register or an integer whose |
766 | high-order 16 bits are zero. */ | |
9878760c RK |
767 | |
768 | int | |
769 | reg_or_u_short_operand (op, mode) | |
592696dd | 770 | rtx op; |
9878760c RK |
771 | enum machine_mode mode; |
772 | { | |
e675f625 | 773 | return u_short_cint_operand (op, mode) || gpc_reg_operand (op, mode); |
9878760c RK |
774 | } |
775 | ||
776 | /* Return 1 is the operand is either a non-special register or ANY | |
777 | constant integer. */ | |
778 | ||
779 | int | |
780 | reg_or_cint_operand (op, mode) | |
592696dd | 781 | rtx op; |
9878760c RK |
782 | enum machine_mode mode; |
783 | { | |
a4f6c312 | 784 | return (GET_CODE (op) == CONST_INT || gpc_reg_operand (op, mode)); |
f6bf7de2 DE |
785 | } |
786 | ||
787 | /* Return 1 is the operand is either a non-special register or ANY | |
788 | 32-bit signed constant integer. */ | |
789 | ||
790 | int | |
791 | reg_or_arith_cint_operand (op, mode) | |
592696dd | 792 | rtx op; |
f6bf7de2 DE |
793 | enum machine_mode mode; |
794 | { | |
a4f6c312 SS |
795 | return (gpc_reg_operand (op, mode) |
796 | || (GET_CODE (op) == CONST_INT | |
f6bf7de2 | 797 | #if HOST_BITS_PER_WIDE_INT != 32 |
a4f6c312 SS |
798 | && ((unsigned HOST_WIDE_INT) (INTVAL (op) + 0x80000000) |
799 | < (unsigned HOST_WIDE_INT) 0x100000000ll) | |
f6bf7de2 | 800 | #endif |
a4f6c312 | 801 | )); |
9878760c RK |
802 | } |
803 | ||
2bfcf297 DB |
804 | /* Return 1 is the operand is either a non-special register or a 32-bit |
805 | signed constant integer valid for 64-bit addition. */ | |
806 | ||
807 | int | |
808 | reg_or_add_cint64_operand (op, mode) | |
592696dd | 809 | rtx op; |
2bfcf297 DB |
810 | enum machine_mode mode; |
811 | { | |
a4f6c312 SS |
812 | return (gpc_reg_operand (op, mode) |
813 | || (GET_CODE (op) == CONST_INT | |
814 | && INTVAL (op) < 0x7fff8000 | |
2bfcf297 | 815 | #if HOST_BITS_PER_WIDE_INT != 32 |
a4f6c312 SS |
816 | && ((unsigned HOST_WIDE_INT) (INTVAL (op) + 0x80008000) |
817 | < 0x100000000ll) | |
2bfcf297 | 818 | #endif |
a4f6c312 | 819 | )); |
2bfcf297 DB |
820 | } |
821 | ||
822 | /* Return 1 is the operand is either a non-special register or a 32-bit | |
823 | signed constant integer valid for 64-bit subtraction. */ | |
824 | ||
825 | int | |
826 | reg_or_sub_cint64_operand (op, mode) | |
592696dd | 827 | rtx op; |
2bfcf297 DB |
828 | enum machine_mode mode; |
829 | { | |
a4f6c312 SS |
830 | return (gpc_reg_operand (op, mode) |
831 | || (GET_CODE (op) == CONST_INT | |
832 | && (- INTVAL (op)) < 0x7fff8000 | |
2bfcf297 | 833 | #if HOST_BITS_PER_WIDE_INT != 32 |
a4f6c312 SS |
834 | && ((unsigned HOST_WIDE_INT) ((- INTVAL (op)) + 0x80008000) |
835 | < 0x100000000ll) | |
2bfcf297 | 836 | #endif |
a4f6c312 | 837 | )); |
2bfcf297 DB |
838 | } |
839 | ||
9ebbca7d GK |
840 | /* Return 1 is the operand is either a non-special register or ANY |
841 | 32-bit unsigned constant integer. */ | |
842 | ||
843 | int | |
1d328b19 | 844 | reg_or_logical_cint_operand (op, mode) |
592696dd | 845 | rtx op; |
9ebbca7d GK |
846 | enum machine_mode mode; |
847 | { | |
1d328b19 GK |
848 | if (GET_CODE (op) == CONST_INT) |
849 | { | |
850 | if (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT) | |
851 | { | |
852 | if (GET_MODE_BITSIZE (mode) <= 32) | |
a4f6c312 | 853 | abort (); |
1d328b19 GK |
854 | |
855 | if (INTVAL (op) < 0) | |
856 | return 0; | |
857 | } | |
858 | ||
859 | return ((INTVAL (op) & GET_MODE_MASK (mode) | |
0858c623 | 860 | & (~ (unsigned HOST_WIDE_INT) 0xffffffff)) == 0); |
1d328b19 GK |
861 | } |
862 | else if (GET_CODE (op) == CONST_DOUBLE) | |
863 | { | |
864 | if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT | |
865 | || mode != DImode) | |
a4f6c312 | 866 | abort (); |
1d328b19 GK |
867 | |
868 | return CONST_DOUBLE_HIGH (op) == 0; | |
869 | } | |
870 | else | |
871 | return gpc_reg_operand (op, mode); | |
9ebbca7d GK |
872 | } |
873 | ||
51d3e7d6 | 874 | /* Return 1 if the operand is an operand that can be loaded via the GOT. */ |
766a866c MM |
875 | |
876 | int | |
877 | got_operand (op, mode) | |
592696dd | 878 | rtx op; |
296b8152 | 879 | enum machine_mode mode ATTRIBUTE_UNUSED; |
766a866c MM |
880 | { |
881 | return (GET_CODE (op) == SYMBOL_REF | |
882 | || GET_CODE (op) == CONST | |
883 | || GET_CODE (op) == LABEL_REF); | |
884 | } | |
885 | ||
38c1f2d7 MM |
886 | /* Return 1 if the operand is a simple references that can be loaded via |
887 | the GOT (labels involving addition aren't allowed). */ | |
888 | ||
889 | int | |
890 | got_no_const_operand (op, mode) | |
592696dd | 891 | rtx op; |
296b8152 | 892 | enum machine_mode mode ATTRIBUTE_UNUSED; |
38c1f2d7 MM |
893 | { |
894 | return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF); | |
895 | } | |
896 | ||
4e74d8ec MM |
897 | /* Return the number of instructions it takes to form a constant in an |
898 | integer register. */ | |
899 | ||
900 | static int | |
901 | num_insns_constant_wide (value) | |
902 | HOST_WIDE_INT value; | |
903 | { | |
904 | /* signed constant loadable with {cal|addi} */ | |
5f59ecb7 | 905 | if (CONST_OK_FOR_LETTER_P (value, 'I')) |
0865c631 GK |
906 | return 1; |
907 | ||
4e74d8ec | 908 | /* constant loadable with {cau|addis} */ |
5f59ecb7 | 909 | else if (CONST_OK_FOR_LETTER_P (value, 'L')) |
4e74d8ec MM |
910 | return 1; |
911 | ||
5f59ecb7 | 912 | #if HOST_BITS_PER_WIDE_INT == 64 |
c81fc13e | 913 | else if (TARGET_POWERPC64) |
4e74d8ec | 914 | { |
0d30d435 | 915 | HOST_WIDE_INT low = value & 0xffffffff; |
4e74d8ec MM |
916 | HOST_WIDE_INT high = value >> 32; |
917 | ||
0d30d435 DE |
918 | low = (low ^ 0x80000000) - 0x80000000; /* sign extend */ |
919 | ||
0858c623 | 920 | if (high == 0 && (low & 0x80000000) == 0) |
4e74d8ec MM |
921 | return 2; |
922 | ||
0858c623 | 923 | else if (high == -1 && (low & 0x80000000) != 0) |
4e74d8ec MM |
924 | return 2; |
925 | ||
c81fc13e | 926 | else if (! low) |
4e74d8ec MM |
927 | return num_insns_constant_wide (high) + 1; |
928 | ||
929 | else | |
930 | return (num_insns_constant_wide (high) | |
e396202a | 931 | + num_insns_constant_wide (low) + 1); |
4e74d8ec MM |
932 | } |
933 | #endif | |
934 | ||
935 | else | |
936 | return 2; | |
937 | } | |
938 | ||
939 | int | |
940 | num_insns_constant (op, mode) | |
941 | rtx op; | |
942 | enum machine_mode mode; | |
943 | { | |
4e74d8ec | 944 | if (GET_CODE (op) == CONST_INT) |
0d30d435 DE |
945 | { |
946 | #if HOST_BITS_PER_WIDE_INT == 64 | |
4e2c1c44 DE |
947 | if ((INTVAL (op) >> 31) != 0 && (INTVAL (op) >> 31) != -1 |
948 | && mask64_operand (op, mode)) | |
0d30d435 DE |
949 | return 2; |
950 | else | |
951 | #endif | |
952 | return num_insns_constant_wide (INTVAL (op)); | |
953 | } | |
4e74d8ec | 954 | |
6fc48950 MM |
955 | else if (GET_CODE (op) == CONST_DOUBLE && mode == SFmode) |
956 | { | |
957 | long l; | |
958 | REAL_VALUE_TYPE rv; | |
959 | ||
960 | REAL_VALUE_FROM_CONST_DOUBLE (rv, op); | |
961 | REAL_VALUE_TO_TARGET_SINGLE (rv, l); | |
962 | return num_insns_constant_wide ((HOST_WIDE_INT)l); | |
963 | } | |
964 | ||
47ad8c61 | 965 | else if (GET_CODE (op) == CONST_DOUBLE) |
4e74d8ec | 966 | { |
47ad8c61 MM |
967 | HOST_WIDE_INT low; |
968 | HOST_WIDE_INT high; | |
969 | long l[2]; | |
970 | REAL_VALUE_TYPE rv; | |
971 | int endian = (WORDS_BIG_ENDIAN == 0); | |
4e74d8ec | 972 | |
47ad8c61 MM |
973 | if (mode == VOIDmode || mode == DImode) |
974 | { | |
975 | high = CONST_DOUBLE_HIGH (op); | |
976 | low = CONST_DOUBLE_LOW (op); | |
977 | } | |
978 | else | |
979 | { | |
980 | REAL_VALUE_FROM_CONST_DOUBLE (rv, op); | |
981 | REAL_VALUE_TO_TARGET_DOUBLE (rv, l); | |
982 | high = l[endian]; | |
983 | low = l[1 - endian]; | |
984 | } | |
4e74d8ec | 985 | |
47ad8c61 MM |
986 | if (TARGET_32BIT) |
987 | return (num_insns_constant_wide (low) | |
988 | + num_insns_constant_wide (high)); | |
4e74d8ec MM |
989 | |
990 | else | |
47ad8c61 | 991 | { |
0858c623 | 992 | if (high == 0 && (low & 0x80000000) == 0) |
47ad8c61 MM |
993 | return num_insns_constant_wide (low); |
994 | ||
0858c623 | 995 | else if (high == -1 && (low & 0x80000000) != 0) |
47ad8c61 MM |
996 | return num_insns_constant_wide (low); |
997 | ||
a260abc9 DE |
998 | else if (mask64_operand (op, mode)) |
999 | return 2; | |
1000 | ||
47ad8c61 MM |
1001 | else if (low == 0) |
1002 | return num_insns_constant_wide (high) + 1; | |
1003 | ||
1004 | else | |
1005 | return (num_insns_constant_wide (high) | |
1006 | + num_insns_constant_wide (low) + 1); | |
1007 | } | |
4e74d8ec MM |
1008 | } |
1009 | ||
1010 | else | |
1011 | abort (); | |
1012 | } | |
1013 | ||
a4f6c312 SS |
1014 | /* Return 1 if the operand is a CONST_DOUBLE and it can be put into a |
1015 | register with one instruction per word. We only do this if we can | |
1016 | safely read CONST_DOUBLE_{LOW,HIGH}. */ | |
9878760c RK |
1017 | |
1018 | int | |
1019 | easy_fp_constant (op, mode) | |
592696dd SS |
1020 | rtx op; |
1021 | enum machine_mode mode; | |
9878760c | 1022 | { |
9878760c RK |
1023 | if (GET_CODE (op) != CONST_DOUBLE |
1024 | || GET_MODE (op) != mode | |
4e74d8ec | 1025 | || (GET_MODE_CLASS (mode) != MODE_FLOAT && mode != DImode)) |
9878760c RK |
1026 | return 0; |
1027 | ||
a4f6c312 | 1028 | /* Consider all constants with -msoft-float to be easy. */ |
4e74d8ec | 1029 | if (TARGET_SOFT_FLOAT && mode != DImode) |
b6c9286a MM |
1030 | return 1; |
1031 | ||
a4f6c312 | 1032 | /* If we are using V.4 style PIC, consider all constants to be hard. */ |
f607bc57 | 1033 | if (flag_pic && DEFAULT_ABI == ABI_V4) |
a7273471 MM |
1034 | return 0; |
1035 | ||
5ae4759c | 1036 | #ifdef TARGET_RELOCATABLE |
a4f6c312 SS |
1037 | /* Similarly if we are using -mrelocatable, consider all constants |
1038 | to be hard. */ | |
5ae4759c MM |
1039 | if (TARGET_RELOCATABLE) |
1040 | return 0; | |
1041 | #endif | |
1042 | ||
042259f2 DE |
1043 | if (mode == DFmode) |
1044 | { | |
1045 | long k[2]; | |
1046 | REAL_VALUE_TYPE rv; | |
1047 | ||
1048 | REAL_VALUE_FROM_CONST_DOUBLE (rv, op); | |
1049 | REAL_VALUE_TO_TARGET_DOUBLE (rv, k); | |
9878760c | 1050 | |
4e74d8ec MM |
1051 | return (num_insns_constant_wide ((HOST_WIDE_INT)k[0]) == 1 |
1052 | && num_insns_constant_wide ((HOST_WIDE_INT)k[1]) == 1); | |
042259f2 | 1053 | } |
4e74d8ec MM |
1054 | |
1055 | else if (mode == SFmode) | |
042259f2 DE |
1056 | { |
1057 | long l; | |
1058 | REAL_VALUE_TYPE rv; | |
1059 | ||
1060 | REAL_VALUE_FROM_CONST_DOUBLE (rv, op); | |
1061 | REAL_VALUE_TO_TARGET_SINGLE (rv, l); | |
9878760c | 1062 | |
4e74d8ec | 1063 | return num_insns_constant_wide (l) == 1; |
042259f2 | 1064 | } |
4e74d8ec | 1065 | |
a260abc9 | 1066 | else if (mode == DImode) |
c81fc13e | 1067 | return ((TARGET_POWERPC64 |
a260abc9 DE |
1068 | && GET_CODE (op) == CONST_DOUBLE && CONST_DOUBLE_LOW (op) == 0) |
1069 | || (num_insns_constant (op, DImode) <= 2)); | |
4e74d8ec | 1070 | |
a9098fd0 GK |
1071 | else if (mode == SImode) |
1072 | return 1; | |
4e74d8ec MM |
1073 | else |
1074 | abort (); | |
9878760c | 1075 | } |
8f75773e | 1076 | |
50a0b056 GK |
1077 | /* Return 1 if the operand is 0.0. */ |
1078 | int | |
1079 | zero_fp_constant (op, mode) | |
592696dd SS |
1080 | rtx op; |
1081 | enum machine_mode mode; | |
50a0b056 GK |
1082 | { |
1083 | return GET_MODE_CLASS (mode) == MODE_FLOAT && op == CONST0_RTX (mode); | |
1084 | } | |
1085 | ||
a4f6c312 SS |
1086 | /* Return 1 if the operand is in volatile memory. Note that during |
1087 | the RTL generation phase, memory_operand does not return TRUE for | |
b6c9286a MM |
1088 | volatile memory references. So this function allows us to |
1089 | recognize volatile references where its safe. */ | |
1090 | ||
1091 | int | |
1092 | volatile_mem_operand (op, mode) | |
592696dd | 1093 | rtx op; |
b6c9286a MM |
1094 | enum machine_mode mode; |
1095 | { | |
1096 | if (GET_CODE (op) != MEM) | |
1097 | return 0; | |
1098 | ||
1099 | if (!MEM_VOLATILE_P (op)) | |
1100 | return 0; | |
1101 | ||
1102 | if (mode != GET_MODE (op)) | |
1103 | return 0; | |
1104 | ||
1105 | if (reload_completed) | |
1106 | return memory_operand (op, mode); | |
1107 | ||
1108 | if (reload_in_progress) | |
1109 | return strict_memory_address_p (mode, XEXP (op, 0)); | |
1110 | ||
1111 | return memory_address_p (mode, XEXP (op, 0)); | |
1112 | } | |
1113 | ||
97f6e72f | 1114 | /* Return 1 if the operand is an offsettable memory operand. */ |
914c2e77 RK |
1115 | |
1116 | int | |
97f6e72f | 1117 | offsettable_mem_operand (op, mode) |
592696dd | 1118 | rtx op; |
914c2e77 RK |
1119 | enum machine_mode mode; |
1120 | { | |
97f6e72f | 1121 | return ((GET_CODE (op) == MEM) |
677a9668 | 1122 | && offsettable_address_p (reload_completed || reload_in_progress, |
97f6e72f | 1123 | mode, XEXP (op, 0))); |
914c2e77 RK |
1124 | } |
1125 | ||
9878760c RK |
1126 | /* Return 1 if the operand is either an easy FP constant (see above) or |
1127 | memory. */ | |
1128 | ||
1129 | int | |
1130 | mem_or_easy_const_operand (op, mode) | |
592696dd | 1131 | rtx op; |
9878760c RK |
1132 | enum machine_mode mode; |
1133 | { | |
1134 | return memory_operand (op, mode) || easy_fp_constant (op, mode); | |
1135 | } | |
1136 | ||
1137 | /* Return 1 if the operand is either a non-special register or an item | |
5f59ecb7 | 1138 | that can be used as the operand of a `mode' add insn. */ |
9878760c RK |
1139 | |
1140 | int | |
1141 | add_operand (op, mode) | |
592696dd | 1142 | rtx op; |
9878760c RK |
1143 | enum machine_mode mode; |
1144 | { | |
2bfcf297 DB |
1145 | if (GET_CODE (op) == CONST_INT) |
1146 | return (CONST_OK_FOR_LETTER_P (INTVAL(op), 'I') | |
1147 | || CONST_OK_FOR_LETTER_P (INTVAL(op), 'L')); | |
1148 | ||
1149 | return gpc_reg_operand (op, mode); | |
9878760c RK |
1150 | } |
1151 | ||
dcfedcd0 RK |
1152 | /* Return 1 if OP is a constant but not a valid add_operand. */ |
1153 | ||
1154 | int | |
1155 | non_add_cint_operand (op, mode) | |
592696dd | 1156 | rtx op; |
296b8152 | 1157 | enum machine_mode mode ATTRIBUTE_UNUSED; |
dcfedcd0 RK |
1158 | { |
1159 | return (GET_CODE (op) == CONST_INT | |
a7653a2c | 1160 | && (unsigned HOST_WIDE_INT) (INTVAL (op) + 0x8000) >= 0x10000 |
38886f37 | 1161 | && ! CONST_OK_FOR_LETTER_P (INTVAL (op), 'L')); |
dcfedcd0 RK |
1162 | } |
1163 | ||
9878760c RK |
1164 | /* Return 1 if the operand is a non-special register or a constant that |
1165 | can be used as the operand of an OR or XOR insn on the RS/6000. */ | |
1166 | ||
1167 | int | |
1168 | logical_operand (op, mode) | |
592696dd | 1169 | rtx op; |
9878760c RK |
1170 | enum machine_mode mode; |
1171 | { | |
40501e5f | 1172 | HOST_WIDE_INT opl, oph; |
1d328b19 | 1173 | |
dfbdccdb GK |
1174 | if (gpc_reg_operand (op, mode)) |
1175 | return 1; | |
1d328b19 | 1176 | |
dfbdccdb | 1177 | if (GET_CODE (op) == CONST_INT) |
40501e5f AM |
1178 | { |
1179 | opl = INTVAL (op) & GET_MODE_MASK (mode); | |
1180 | ||
1181 | #if HOST_BITS_PER_WIDE_INT <= 32 | |
1182 | if (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT && opl < 0) | |
1183 | return 0; | |
1184 | #endif | |
1185 | } | |
dfbdccdb GK |
1186 | else if (GET_CODE (op) == CONST_DOUBLE) |
1187 | { | |
1d328b19 | 1188 | if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT) |
40501e5f | 1189 | abort (); |
1d328b19 GK |
1190 | |
1191 | opl = CONST_DOUBLE_LOW (op); | |
1192 | oph = CONST_DOUBLE_HIGH (op); | |
40501e5f | 1193 | if (oph != 0) |
38886f37 | 1194 | return 0; |
dfbdccdb GK |
1195 | } |
1196 | else | |
1197 | return 0; | |
1d328b19 | 1198 | |
40501e5f AM |
1199 | return ((opl & ~ (unsigned HOST_WIDE_INT) 0xffff) == 0 |
1200 | || (opl & ~ (unsigned HOST_WIDE_INT) 0xffff0000) == 0); | |
9878760c RK |
1201 | } |
1202 | ||
dcfedcd0 | 1203 | /* Return 1 if C is a constant that is not a logical operand (as |
1d328b19 | 1204 | above), but could be split into one. */ |
dcfedcd0 RK |
1205 | |
1206 | int | |
1207 | non_logical_cint_operand (op, mode) | |
592696dd | 1208 | rtx op; |
5f59ecb7 | 1209 | enum machine_mode mode; |
dcfedcd0 | 1210 | { |
dfbdccdb | 1211 | return ((GET_CODE (op) == CONST_INT || GET_CODE (op) == CONST_DOUBLE) |
1d328b19 GK |
1212 | && ! logical_operand (op, mode) |
1213 | && reg_or_logical_cint_operand (op, mode)); | |
dcfedcd0 RK |
1214 | } |
1215 | ||
19ba8161 | 1216 | /* Return 1 if C is a constant that can be encoded in a 32-bit mask on the |
9878760c RK |
1217 | RS/6000. It is if there are no more than two 1->0 or 0->1 transitions. |
1218 | Reject all ones and all zeros, since these should have been optimized | |
1219 | away and confuse the making of MB and ME. */ | |
1220 | ||
1221 | int | |
19ba8161 | 1222 | mask_operand (op, mode) |
592696dd | 1223 | rtx op; |
19ba8161 | 1224 | enum machine_mode mode ATTRIBUTE_UNUSED; |
9878760c | 1225 | { |
02071907 | 1226 | HOST_WIDE_INT c, lsb; |
9878760c | 1227 | |
19ba8161 DE |
1228 | if (GET_CODE (op) != CONST_INT) |
1229 | return 0; | |
1230 | ||
1231 | c = INTVAL (op); | |
1232 | ||
c5059423 AM |
1233 | /* We don't change the number of transitions by inverting, |
1234 | so make sure we start with the LS bit zero. */ | |
1235 | if (c & 1) | |
1236 | c = ~c; | |
1237 | ||
1238 | /* Reject all zeros or all ones. */ | |
1239 | if (c == 0) | |
9878760c RK |
1240 | return 0; |
1241 | ||
c5059423 AM |
1242 | /* Find the first transition. */ |
1243 | lsb = c & -c; | |
1244 | ||
1245 | /* Invert to look for a second transition. */ | |
1246 | c = ~c; | |
9878760c | 1247 | |
c5059423 AM |
1248 | /* Erase first transition. */ |
1249 | c &= -lsb; | |
9878760c | 1250 | |
c5059423 AM |
1251 | /* Find the second transition (if any). */ |
1252 | lsb = c & -c; | |
1253 | ||
1254 | /* Match if all the bits above are 1's (or c is zero). */ | |
1255 | return c == -lsb; | |
9878760c RK |
1256 | } |
1257 | ||
a260abc9 DE |
1258 | /* Return 1 if the operand is a constant that is a PowerPC64 mask. |
1259 | It is if there are no more than one 1->0 or 0->1 transitions. | |
1260 | Reject all ones and all zeros, since these should have been optimized | |
1261 | away and confuse the making of MB and ME. */ | |
9878760c RK |
1262 | |
1263 | int | |
a260abc9 | 1264 | mask64_operand (op, mode) |
592696dd | 1265 | rtx op; |
a260abc9 DE |
1266 | enum machine_mode mode; |
1267 | { | |
1268 | if (GET_CODE (op) == CONST_INT) | |
1269 | { | |
02071907 | 1270 | HOST_WIDE_INT c, lsb; |
a260abc9 | 1271 | |
c5059423 AM |
1272 | /* We don't change the number of transitions by inverting, |
1273 | so make sure we start with the LS bit zero. */ | |
1274 | c = INTVAL (op); | |
1275 | if (c & 1) | |
1276 | c = ~c; | |
a260abc9 | 1277 | |
c5059423 AM |
1278 | /* Reject all zeros or all ones. */ |
1279 | if (c == 0) | |
e2c953b6 DE |
1280 | return 0; |
1281 | ||
c5059423 AM |
1282 | /* Find the transition, and check that all bits above are 1's. */ |
1283 | lsb = c & -c; | |
1284 | return c == -lsb; | |
e2c953b6 | 1285 | } |
a260abc9 DE |
1286 | else if (GET_CODE (op) == CONST_DOUBLE |
1287 | && (mode == VOIDmode || mode == DImode)) | |
1288 | { | |
02071907 | 1289 | HOST_WIDE_INT low, high, lsb; |
a260abc9 | 1290 | |
c5059423 AM |
1291 | if (HOST_BITS_PER_WIDE_INT < 64) |
1292 | high = CONST_DOUBLE_HIGH (op); | |
a260abc9 | 1293 | |
c5059423 AM |
1294 | low = CONST_DOUBLE_LOW (op); |
1295 | if (low & 1) | |
1296 | { | |
1297 | if (HOST_BITS_PER_WIDE_INT < 64) | |
1298 | high = ~high; | |
1299 | low = ~low; | |
1300 | } | |
a260abc9 | 1301 | |
c5059423 AM |
1302 | if (low == 0) |
1303 | { | |
1304 | if (HOST_BITS_PER_WIDE_INT >= 64 || high == 0) | |
1305 | return 0; | |
a260abc9 | 1306 | |
c5059423 AM |
1307 | lsb = high & -high; |
1308 | return high == -lsb; | |
1309 | } | |
a260abc9 | 1310 | |
c5059423 AM |
1311 | lsb = low & -low; |
1312 | return low == -lsb && (HOST_BITS_PER_WIDE_INT >= 64 || high == ~0); | |
a260abc9 DE |
1313 | } |
1314 | else | |
1315 | return 0; | |
1316 | } | |
1317 | ||
1318 | /* Return 1 if the operand is either a non-special register or a constant | |
1319 | that can be used as the operand of a PowerPC64 logical AND insn. */ | |
1320 | ||
1321 | int | |
1322 | and64_operand (op, mode) | |
592696dd | 1323 | rtx op; |
9878760c RK |
1324 | enum machine_mode mode; |
1325 | { | |
a4f6c312 | 1326 | if (fixed_regs[CR0_REGNO]) /* CR0 not available, don't do andi./andis. */ |
52d3af72 DE |
1327 | return (gpc_reg_operand (op, mode) || mask64_operand (op, mode)); |
1328 | ||
1329 | return (logical_operand (op, mode) || mask64_operand (op, mode)); | |
9878760c RK |
1330 | } |
1331 | ||
a260abc9 DE |
1332 | /* Return 1 if the operand is either a non-special register or a |
1333 | constant that can be used as the operand of an RS/6000 logical AND insn. */ | |
dcfedcd0 RK |
1334 | |
1335 | int | |
a260abc9 | 1336 | and_operand (op, mode) |
592696dd | 1337 | rtx op; |
a260abc9 | 1338 | enum machine_mode mode; |
dcfedcd0 | 1339 | { |
a4f6c312 | 1340 | if (fixed_regs[CR0_REGNO]) /* CR0 not available, don't do andi./andis. */ |
52d3af72 DE |
1341 | return (gpc_reg_operand (op, mode) || mask_operand (op, mode)); |
1342 | ||
1343 | return (logical_operand (op, mode) || mask_operand (op, mode)); | |
dcfedcd0 RK |
1344 | } |
1345 | ||
9878760c RK |
1346 | /* Return 1 if the operand is a general register or memory operand. */ |
1347 | ||
1348 | int | |
1349 | reg_or_mem_operand (op, mode) | |
592696dd SS |
1350 | rtx op; |
1351 | enum machine_mode mode; | |
9878760c | 1352 | { |
b6c9286a MM |
1353 | return (gpc_reg_operand (op, mode) |
1354 | || memory_operand (op, mode) | |
1355 | || volatile_mem_operand (op, mode)); | |
9878760c RK |
1356 | } |
1357 | ||
a7a813f7 | 1358 | /* Return 1 if the operand is a general register or memory operand without |
3cb999d8 | 1359 | pre_inc or pre_dec which produces invalid form of PowerPC lwa |
a7a813f7 RK |
1360 | instruction. */ |
1361 | ||
1362 | int | |
1363 | lwa_operand (op, mode) | |
592696dd SS |
1364 | rtx op; |
1365 | enum machine_mode mode; | |
a7a813f7 RK |
1366 | { |
1367 | rtx inner = op; | |
1368 | ||
1369 | if (reload_completed && GET_CODE (inner) == SUBREG) | |
1370 | inner = SUBREG_REG (inner); | |
1371 | ||
1372 | return gpc_reg_operand (inner, mode) | |
1373 | || (memory_operand (inner, mode) | |
1374 | && GET_CODE (XEXP (inner, 0)) != PRE_INC | |
6a40a9d6 DE |
1375 | && GET_CODE (XEXP (inner, 0)) != PRE_DEC |
1376 | && (GET_CODE (XEXP (inner, 0)) != PLUS | |
e903c96a DE |
1377 | || GET_CODE (XEXP (XEXP (inner, 0), 1)) != CONST_INT |
1378 | || INTVAL (XEXP (XEXP (inner, 0), 1)) % 4 == 0)); | |
a7a813f7 RK |
1379 | } |
1380 | ||
9878760c RK |
1381 | /* Return 1 if the operand, used inside a MEM, is a valid first argument |
1382 | to CALL. This is a SYMBOL_REF or a pseudo-register, which will be | |
1383 | forced to lr. */ | |
1384 | ||
1385 | int | |
1386 | call_operand (op, mode) | |
592696dd | 1387 | rtx op; |
9878760c RK |
1388 | enum machine_mode mode; |
1389 | { | |
1390 | if (mode != VOIDmode && GET_MODE (op) != mode) | |
1391 | return 0; | |
1392 | ||
1393 | return (GET_CODE (op) == SYMBOL_REF | |
1394 | || (GET_CODE (op) == REG && REGNO (op) >= FIRST_PSEUDO_REGISTER)); | |
1395 | } | |
1396 | ||
2af3d377 | 1397 | /* Return 1 if the operand is a SYMBOL_REF for a function known to be in |
a4f6c312 | 1398 | this file and the function is not weakly defined. */ |
2af3d377 RK |
1399 | |
1400 | int | |
1401 | current_file_function_operand (op, mode) | |
592696dd | 1402 | rtx op; |
296b8152 | 1403 | enum machine_mode mode ATTRIBUTE_UNUSED; |
2af3d377 RK |
1404 | { |
1405 | return (GET_CODE (op) == SYMBOL_REF | |
1406 | && (SYMBOL_REF_FLAG (op) | |
8f1b829e | 1407 | || (op == XEXP (DECL_RTL (current_function_decl), 0) |
c81fc13e | 1408 | && ! DECL_WEAK (current_function_decl)))); |
2af3d377 RK |
1409 | } |
1410 | ||
9878760c RK |
1411 | /* Return 1 if this operand is a valid input for a move insn. */ |
1412 | ||
1413 | int | |
1414 | input_operand (op, mode) | |
592696dd | 1415 | rtx op; |
9878760c RK |
1416 | enum machine_mode mode; |
1417 | { | |
eb4e8003 | 1418 | /* Memory is always valid. */ |
9878760c RK |
1419 | if (memory_operand (op, mode)) |
1420 | return 1; | |
1421 | ||
34792e82 | 1422 | /* Only a tiny bit of handling for CONSTANT_P_RTX is necessary. */ |
01b4cf2b | 1423 | if (GET_CODE (op) == CONSTANT_P_RTX) |
34792e82 JL |
1424 | return 1; |
1425 | ||
eb4e8003 RK |
1426 | /* For floating-point, easy constants are valid. */ |
1427 | if (GET_MODE_CLASS (mode) == MODE_FLOAT | |
1428 | && CONSTANT_P (op) | |
1429 | && easy_fp_constant (op, mode)) | |
1430 | return 1; | |
1431 | ||
4e74d8ec MM |
1432 | /* Allow any integer constant. */ |
1433 | if (GET_MODE_CLASS (mode) == MODE_INT | |
e675f625 | 1434 | && (GET_CODE (op) == CONST_INT |
e675f625 | 1435 | || GET_CODE (op) == CONST_DOUBLE)) |
4e74d8ec MM |
1436 | return 1; |
1437 | ||
eb4e8003 RK |
1438 | /* For floating-point or multi-word mode, the only remaining valid type |
1439 | is a register. */ | |
9878760c RK |
1440 | if (GET_MODE_CLASS (mode) == MODE_FLOAT |
1441 | || GET_MODE_SIZE (mode) > UNITS_PER_WORD) | |
eb4e8003 | 1442 | return register_operand (op, mode); |
9878760c | 1443 | |
88fe15a1 RK |
1444 | /* The only cases left are integral modes one word or smaller (we |
1445 | do not get called for MODE_CC values). These can be in any | |
1446 | register. */ | |
1447 | if (register_operand (op, mode)) | |
a8b3aeda | 1448 | return 1; |
88fe15a1 | 1449 | |
84cf9dda | 1450 | /* A SYMBOL_REF referring to the TOC is valid. */ |
7fec4abd | 1451 | if (LEGITIMATE_CONSTANT_POOL_ADDRESS_P (op)) |
84cf9dda RK |
1452 | return 1; |
1453 | ||
9ebbca7d GK |
1454 | /* A constant pool expression (relative to the TOC) is valid */ |
1455 | if (TOC_RELATIVE_EXPR_P (op)) | |
b6c9286a MM |
1456 | return 1; |
1457 | ||
88228c4b MM |
1458 | /* V.4 allows SYMBOL_REFs and CONSTs that are in the small data region |
1459 | to be valid. */ | |
f607bc57 | 1460 | if (DEFAULT_ABI == ABI_V4 |
88228c4b MM |
1461 | && (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST) |
1462 | && small_data_operand (op, Pmode)) | |
1463 | return 1; | |
1464 | ||
042259f2 | 1465 | return 0; |
9878760c | 1466 | } |
7509c759 | 1467 | |
a4f6c312 | 1468 | /* Return 1 for an operand in small memory on V.4/eabi. */ |
7509c759 MM |
1469 | |
1470 | int | |
1471 | small_data_operand (op, mode) | |
296b8152 KG |
1472 | rtx op ATTRIBUTE_UNUSED; |
1473 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
7509c759 | 1474 | { |
38c1f2d7 | 1475 | #if TARGET_ELF |
5f59ecb7 | 1476 | rtx sym_ref; |
7509c759 | 1477 | |
d9407988 | 1478 | if (rs6000_sdata == SDATA_NONE || rs6000_sdata == SDATA_DATA) |
a54d04b7 | 1479 | return 0; |
a54d04b7 | 1480 | |
f607bc57 | 1481 | if (DEFAULT_ABI != ABI_V4) |
7509c759 MM |
1482 | return 0; |
1483 | ||
88228c4b MM |
1484 | if (GET_CODE (op) == SYMBOL_REF) |
1485 | sym_ref = op; | |
1486 | ||
1487 | else if (GET_CODE (op) != CONST | |
1488 | || GET_CODE (XEXP (op, 0)) != PLUS | |
1489 | || GET_CODE (XEXP (XEXP (op, 0), 0)) != SYMBOL_REF | |
1490 | || GET_CODE (XEXP (XEXP (op, 0), 1)) != CONST_INT) | |
7509c759 MM |
1491 | return 0; |
1492 | ||
88228c4b | 1493 | else |
dbf55e53 MM |
1494 | { |
1495 | rtx sum = XEXP (op, 0); | |
1496 | HOST_WIDE_INT summand; | |
1497 | ||
1498 | /* We have to be careful here, because it is the referenced address | |
1499 | that must be 32k from _SDA_BASE_, not just the symbol. */ | |
1500 | summand = INTVAL (XEXP (sum, 1)); | |
1501 | if (summand < 0 || summand > g_switch_value) | |
1502 | return 0; | |
1503 | ||
1504 | sym_ref = XEXP (sum, 0); | |
1505 | } | |
88228c4b MM |
1506 | |
1507 | if (*XSTR (sym_ref, 0) != '@') | |
7509c759 MM |
1508 | return 0; |
1509 | ||
1510 | return 1; | |
d9407988 MM |
1511 | |
1512 | #else | |
1513 | return 0; | |
1514 | #endif | |
7509c759 | 1515 | } |
9ebbca7d GK |
1516 | \f |
1517 | static int | |
1518 | constant_pool_expr_1 (op, have_sym, have_toc) | |
1519 | rtx op; | |
1520 | int *have_sym; | |
1521 | int *have_toc; | |
1522 | { | |
1523 | switch (GET_CODE(op)) | |
1524 | { | |
1525 | case SYMBOL_REF: | |
a4f6c312 SS |
1526 | if (CONSTANT_POOL_ADDRESS_P (op)) |
1527 | { | |
1528 | if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (op), Pmode)) | |
1529 | { | |
1530 | *have_sym = 1; | |
1531 | return 1; | |
1532 | } | |
1533 | else | |
1534 | return 0; | |
1535 | } | |
1536 | else if (! strcmp (XSTR (op, 0), toc_label_name)) | |
1537 | { | |
1538 | *have_toc = 1; | |
1539 | return 1; | |
1540 | } | |
1541 | else | |
1542 | return 0; | |
9ebbca7d GK |
1543 | case PLUS: |
1544 | case MINUS: | |
a4f6c312 SS |
1545 | return constant_pool_expr_1 (XEXP (op, 0), have_sym, have_toc) && |
1546 | constant_pool_expr_1 (XEXP (op, 1), have_sym, have_toc); | |
9ebbca7d | 1547 | case CONST: |
a4f6c312 | 1548 | return constant_pool_expr_1 (XEXP (op, 0), have_sym, have_toc); |
9ebbca7d | 1549 | case CONST_INT: |
a4f6c312 | 1550 | return 1; |
9ebbca7d | 1551 | default: |
a4f6c312 | 1552 | return 0; |
9ebbca7d GK |
1553 | } |
1554 | } | |
1555 | ||
1556 | int | |
1557 | constant_pool_expr_p (op) | |
1558 | rtx op; | |
1559 | { | |
1560 | int have_sym = 0; | |
1561 | int have_toc = 0; | |
1562 | return constant_pool_expr_1 (op, &have_sym, &have_toc) && have_sym; | |
1563 | } | |
1564 | ||
1565 | int | |
1566 | toc_relative_expr_p (op) | |
1567 | rtx op; | |
1568 | { | |
1569 | int have_sym = 0; | |
1570 | int have_toc = 0; | |
1571 | return constant_pool_expr_1 (op, &have_sym, &have_toc) && have_toc; | |
1572 | } | |
1573 | ||
1574 | /* Try machine-dependent ways of modifying an illegitimate address | |
1575 | to be legitimate. If we find one, return the new, valid address. | |
1576 | This is used from only one place: `memory_address' in explow.c. | |
1577 | ||
a4f6c312 SS |
1578 | OLDX is the address as it was before break_out_memory_refs was |
1579 | called. In some cases it is useful to look at this to decide what | |
1580 | needs to be done. | |
9ebbca7d | 1581 | |
a4f6c312 | 1582 | MODE is passed so that this function can use GO_IF_LEGITIMATE_ADDRESS. |
9ebbca7d | 1583 | |
a4f6c312 SS |
1584 | It is always safe for this function to do nothing. It exists to |
1585 | recognize opportunities to optimize the output. | |
9ebbca7d GK |
1586 | |
1587 | On RS/6000, first check for the sum of a register with a constant | |
1588 | integer that is out of range. If so, generate code to add the | |
1589 | constant with the low-order 16 bits masked to the register and force | |
1590 | this result into another register (this can be done with `cau'). | |
1591 | Then generate an address of REG+(CONST&0xffff), allowing for the | |
1592 | possibility of bit 16 being a one. | |
1593 | ||
1594 | Then check for the sum of a register and something not constant, try to | |
1595 | load the other things into a register and return the sum. */ | |
1596 | rtx | |
1597 | rs6000_legitimize_address (x, oldx, mode) | |
1598 | rtx x; | |
1599 | rtx oldx ATTRIBUTE_UNUSED; | |
1600 | enum machine_mode mode; | |
0ac081f6 | 1601 | { |
9ebbca7d GK |
1602 | if (GET_CODE (x) == PLUS |
1603 | && GET_CODE (XEXP (x, 0)) == REG | |
1604 | && GET_CODE (XEXP (x, 1)) == CONST_INT | |
1605 | && (unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 1)) + 0x8000) >= 0x10000) | |
1606 | { | |
1607 | HOST_WIDE_INT high_int, low_int; | |
1608 | rtx sum; | |
1609 | high_int = INTVAL (XEXP (x, 1)) & (~ (HOST_WIDE_INT) 0xffff); | |
1610 | low_int = INTVAL (XEXP (x, 1)) & 0xffff; | |
1611 | if (low_int & 0x8000) | |
1612 | high_int += 0x10000, low_int |= ((HOST_WIDE_INT) -1) << 16; | |
1613 | sum = force_operand (gen_rtx_PLUS (Pmode, XEXP (x, 0), | |
1614 | GEN_INT (high_int)), 0); | |
1615 | return gen_rtx_PLUS (Pmode, sum, GEN_INT (low_int)); | |
1616 | } | |
1617 | else if (GET_CODE (x) == PLUS | |
1618 | && GET_CODE (XEXP (x, 0)) == REG | |
1619 | && GET_CODE (XEXP (x, 1)) != CONST_INT | |
1620 | && (TARGET_HARD_FLOAT || TARGET_POWERPC64 || mode != DFmode) | |
1621 | && (TARGET_POWERPC64 || mode != DImode) | |
1622 | && mode != TImode) | |
1623 | { | |
1624 | return gen_rtx_PLUS (Pmode, XEXP (x, 0), | |
1625 | force_reg (Pmode, force_operand (XEXP (x, 1), 0))); | |
1626 | } | |
0ac081f6 AH |
1627 | else if (ALTIVEC_VECTOR_MODE (mode)) |
1628 | { | |
1629 | rtx reg; | |
1630 | ||
1631 | /* Make sure both operands are registers. */ | |
1632 | if (GET_CODE (x) == PLUS) | |
1633 | return gen_rtx_PLUS (Pmode, XEXP (x, 0), | |
1634 | force_reg (Pmode, XEXP (x, 1))); | |
1635 | ||
1636 | reg = force_reg (Pmode, x); | |
1637 | return reg; | |
1638 | } | |
9ebbca7d GK |
1639 | else if (TARGET_ELF && TARGET_32BIT && TARGET_NO_TOC && ! flag_pic |
1640 | && GET_CODE (x) != CONST_INT | |
1641 | && GET_CODE (x) != CONST_DOUBLE | |
1642 | && CONSTANT_P (x) | |
1643 | && (TARGET_HARD_FLOAT || mode != DFmode) | |
1644 | && mode != DImode | |
1645 | && mode != TImode) | |
1646 | { | |
1647 | rtx reg = gen_reg_rtx (Pmode); | |
1648 | emit_insn (gen_elf_high (reg, (x))); | |
1649 | return gen_rtx_LO_SUM (Pmode, reg, (x)); | |
1650 | } | |
ee890fe2 SS |
1651 | else if (TARGET_MACHO && TARGET_32BIT && TARGET_NO_TOC |
1652 | && ! flag_pic | |
1653 | && GET_CODE (x) != CONST_INT | |
1654 | && GET_CODE (x) != CONST_DOUBLE | |
1655 | && CONSTANT_P (x) | |
1656 | && (TARGET_HARD_FLOAT || mode != DFmode) | |
1657 | && mode != DImode | |
1658 | && mode != TImode) | |
1659 | { | |
1660 | rtx reg = gen_reg_rtx (Pmode); | |
1661 | emit_insn (gen_macho_high (reg, (x))); | |
1662 | return gen_rtx_LO_SUM (Pmode, reg, (x)); | |
1663 | } | |
9ebbca7d GK |
1664 | else if (TARGET_TOC |
1665 | && CONSTANT_POOL_EXPR_P (x) | |
a9098fd0 | 1666 | && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x), Pmode)) |
9ebbca7d GK |
1667 | { |
1668 | return create_TOC_reference (x); | |
1669 | } | |
1670 | else | |
1671 | return NULL_RTX; | |
1672 | } | |
258bfae2 FS |
1673 | |
1674 | /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression | |
1675 | that is a valid memory address for an instruction. | |
1676 | The MODE argument is the machine mode for the MEM expression | |
1677 | that wants to use this address. | |
1678 | ||
1679 | On the RS/6000, there are four valid address: a SYMBOL_REF that | |
1680 | refers to a constant pool entry of an address (or the sum of it | |
1681 | plus a constant), a short (16-bit signed) constant plus a register, | |
1682 | the sum of two registers, or a register indirect, possibly with an | |
1683 | auto-increment. For DFmode and DImode with an constant plus register, | |
1684 | we must ensure that both words are addressable or PowerPC64 with offset | |
1685 | word aligned. | |
1686 | ||
1687 | For modes spanning multiple registers (DFmode in 32-bit GPRs, | |
1688 | 32-bit DImode, TImode), indexed addressing cannot be used because | |
1689 | adjacent memory cells are accessed by adding word-sized offsets | |
1690 | during assembly output. */ | |
1691 | int | |
1692 | rs6000_legitimate_address (mode, x, reg_ok_strict) | |
1693 | enum machine_mode mode; | |
1694 | rtx x; | |
1695 | int reg_ok_strict; | |
1696 | { | |
1697 | if (LEGITIMATE_INDIRECT_ADDRESS_P (x, reg_ok_strict)) | |
1698 | return 1; | |
1699 | if ((GET_CODE (x) == PRE_INC || GET_CODE (x) == PRE_DEC) | |
1700 | && TARGET_UPDATE | |
1701 | && LEGITIMATE_INDIRECT_ADDRESS_P (XEXP (x, 0), reg_ok_strict)) | |
1702 | return 1; | |
1703 | if (LEGITIMATE_SMALL_DATA_P (mode, x)) | |
1704 | return 1; | |
1705 | if (LEGITIMATE_CONSTANT_POOL_ADDRESS_P (x)) | |
1706 | return 1; | |
1707 | /* If not REG_OK_STRICT (before reload) let pass any stack offset. */ | |
1708 | if (! reg_ok_strict | |
1709 | && GET_CODE (x) == PLUS | |
1710 | && GET_CODE (XEXP (x, 0)) == REG | |
1711 | && XEXP (x, 0) == virtual_stack_vars_rtx | |
1712 | && GET_CODE (XEXP (x, 1)) == CONST_INT) | |
1713 | return 1; | |
1714 | if (LEGITIMATE_OFFSET_ADDRESS_P (mode, x, reg_ok_strict)) | |
1715 | return 1; | |
1716 | if (mode != TImode | |
1717 | && (TARGET_HARD_FLOAT || TARGET_POWERPC64 || mode != DFmode) | |
1718 | && (TARGET_POWERPC64 || mode != DImode) | |
1719 | && LEGITIMATE_INDEXED_ADDRESS_P (x, reg_ok_strict)) | |
1720 | return 1; | |
1721 | if (LEGITIMATE_LO_SUM_ADDRESS_P (mode, x, reg_ok_strict)) | |
1722 | return 1; | |
1723 | return 0; | |
1724 | } | |
fb4d4348 | 1725 | \f |
a4f6c312 SS |
1726 | /* Try to output insns to set TARGET equal to the constant C if it can |
1727 | be done in less than N insns. Do all computations in MODE. | |
1728 | Returns the place where the output has been placed if it can be | |
1729 | done and the insns have been emitted. If it would take more than N | |
1730 | insns, zero is returned and no insns and emitted. */ | |
2bfcf297 DB |
1731 | |
1732 | rtx | |
1733 | rs6000_emit_set_const (dest, mode, source, n) | |
1734 | rtx dest, source; | |
1735 | enum machine_mode mode; | |
1736 | int n ATTRIBUTE_UNUSED; | |
1737 | { | |
1738 | HOST_WIDE_INT c0, c1; | |
1739 | ||
1740 | if (mode == QImode || mode == HImode || mode == SImode) | |
1741 | { | |
1742 | if (dest == NULL) | |
1743 | dest = gen_reg_rtx (mode); | |
1744 | emit_insn (gen_rtx_SET (VOIDmode, dest, source)); | |
1745 | return dest; | |
1746 | } | |
1747 | ||
1748 | if (GET_CODE (source) == CONST_INT) | |
1749 | { | |
1750 | c0 = INTVAL (source); | |
1751 | c1 = -(c0 < 0); | |
1752 | } | |
1753 | else if (GET_CODE (source) == CONST_DOUBLE) | |
1754 | { | |
1755 | #if HOST_BITS_PER_WIDE_INT >= 64 | |
1756 | c0 = CONST_DOUBLE_LOW (source); | |
1757 | c1 = -(c0 < 0); | |
1758 | #else | |
1759 | c0 = CONST_DOUBLE_LOW (source); | |
1760 | c1 = CONST_DOUBLE_HIGH (source); | |
1761 | #endif | |
1762 | } | |
1763 | else | |
a4f6c312 | 1764 | abort (); |
2bfcf297 DB |
1765 | |
1766 | return rs6000_emit_set_long_const (dest, c0, c1); | |
1767 | } | |
1768 | ||
1769 | /* Having failed to find a 3 insn sequence in rs6000_emit_set_const, | |
1770 | fall back to a straight forward decomposition. We do this to avoid | |
1771 | exponential run times encountered when looking for longer sequences | |
1772 | with rs6000_emit_set_const. */ | |
1773 | static rtx | |
1774 | rs6000_emit_set_long_const (dest, c1, c2) | |
1775 | rtx dest; | |
1776 | HOST_WIDE_INT c1, c2; | |
1777 | { | |
1778 | if (!TARGET_POWERPC64) | |
1779 | { | |
1780 | rtx operand1, operand2; | |
1781 | ||
1782 | operand1 = operand_subword_force (dest, WORDS_BIG_ENDIAN == 0, | |
1783 | DImode); | |
1784 | operand2 = operand_subword_force (dest, WORDS_BIG_ENDIAN != 0, | |
1785 | DImode); | |
1786 | emit_move_insn (operand1, GEN_INT (c1)); | |
1787 | emit_move_insn (operand2, GEN_INT (c2)); | |
1788 | } | |
1789 | else | |
1790 | { | |
1791 | HOST_WIDE_INT d1, d2, d3, d4; | |
1792 | ||
1793 | /* Decompose the entire word */ | |
1794 | #if HOST_BITS_PER_WIDE_INT >= 64 | |
1795 | if (c2 != -(c1 < 0)) | |
1796 | abort (); | |
1797 | d1 = ((c1 & 0xffff) ^ 0x8000) - 0x8000; | |
1798 | c1 -= d1; | |
1799 | d2 = ((c1 & 0xffffffff) ^ 0x80000000) - 0x80000000; | |
1800 | c1 = (c1 - d2) >> 32; | |
1801 | d3 = ((c1 & 0xffff) ^ 0x8000) - 0x8000; | |
1802 | c1 -= d3; | |
1803 | d4 = ((c1 & 0xffffffff) ^ 0x80000000) - 0x80000000; | |
1804 | if (c1 != d4) | |
1805 | abort (); | |
1806 | #else | |
1807 | d1 = ((c1 & 0xffff) ^ 0x8000) - 0x8000; | |
1808 | c1 -= d1; | |
1809 | d2 = ((c1 & 0xffffffff) ^ 0x80000000) - 0x80000000; | |
1810 | if (c1 != d2) | |
1811 | abort (); | |
1812 | c2 += (d2 < 0); | |
1813 | d3 = ((c2 & 0xffff) ^ 0x8000) - 0x8000; | |
1814 | c2 -= d3; | |
1815 | d4 = ((c2 & 0xffffffff) ^ 0x80000000) - 0x80000000; | |
1816 | if (c2 != d4) | |
1817 | abort (); | |
1818 | #endif | |
1819 | ||
1820 | /* Construct the high word */ | |
40501e5f | 1821 | if (d4 != 0) |
2bfcf297 DB |
1822 | { |
1823 | emit_move_insn (dest, GEN_INT (d4)); | |
40501e5f | 1824 | if (d3 != 0) |
2bfcf297 DB |
1825 | emit_move_insn (dest, |
1826 | gen_rtx_PLUS (DImode, dest, GEN_INT (d3))); | |
1827 | } | |
1828 | else | |
1829 | emit_move_insn (dest, GEN_INT (d3)); | |
1830 | ||
1831 | /* Shift it into place */ | |
40501e5f AM |
1832 | if (d3 != 0 || d4 != 0) |
1833 | emit_move_insn (dest, gen_rtx_ASHIFT (DImode, dest, GEN_INT (32))); | |
2bfcf297 DB |
1834 | |
1835 | /* Add in the low bits. */ | |
40501e5f | 1836 | if (d2 != 0) |
2bfcf297 | 1837 | emit_move_insn (dest, gen_rtx_PLUS (DImode, dest, GEN_INT (d2))); |
40501e5f | 1838 | if (d1 != 0) |
2bfcf297 DB |
1839 | emit_move_insn (dest, gen_rtx_PLUS (DImode, dest, GEN_INT (d1))); |
1840 | } | |
1841 | ||
1842 | return dest; | |
1843 | } | |
1844 | ||
fb4d4348 GK |
1845 | /* Emit a move from SOURCE to DEST in mode MODE. */ |
1846 | void | |
1847 | rs6000_emit_move (dest, source, mode) | |
1848 | rtx dest; | |
1849 | rtx source; | |
1850 | enum machine_mode mode; | |
1851 | { | |
1852 | rtx operands[2]; | |
1853 | operands[0] = dest; | |
1854 | operands[1] = source; | |
1855 | ||
1856 | /* Sanity checks. Check that we get CONST_DOUBLE only when we should. */ | |
1857 | if (GET_CODE (operands[1]) == CONST_DOUBLE | |
1858 | && ! FLOAT_MODE_P (mode) | |
1859 | && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT) | |
1860 | { | |
1861 | /* FIXME. This should never happen. */ | |
1862 | /* Since it seems that it does, do the safe thing and convert | |
1863 | to a CONST_INT. */ | |
1864 | operands[1] = | |
1865 | GEN_INT (trunc_int_for_mode (CONST_DOUBLE_LOW (operands[1]), mode)); | |
1866 | } | |
1867 | if (GET_CODE (operands[1]) == CONST_DOUBLE | |
1868 | && ! FLOAT_MODE_P (mode) | |
1869 | && ((CONST_DOUBLE_HIGH (operands[1]) == 0 | |
1870 | && CONST_DOUBLE_LOW (operands[1]) >= 0) | |
1871 | || (CONST_DOUBLE_HIGH (operands[1]) == -1 | |
1872 | && CONST_DOUBLE_LOW (operands[1]) < 0))) | |
1873 | abort (); | |
c9e8cb32 DD |
1874 | |
1875 | /* Check if GCC is setting up a block move that will end up using FP | |
1876 | registers as temporaries. We must make sure this is acceptable. */ | |
1877 | if (GET_CODE (operands[0]) == MEM | |
1878 | && GET_CODE (operands[1]) == MEM | |
1879 | && mode == DImode | |
c9e8cb32 DD |
1880 | && (SLOW_UNALIGNED_ACCESS(DImode, MEM_ALIGN(operands[0])) |
1881 | || SLOW_UNALIGNED_ACCESS(DImode, MEM_ALIGN(operands[1])))) | |
1882 | { | |
46aaf10d DE |
1883 | if (!TARGET_POWERPC64) |
1884 | { | |
1885 | emit_move_insn (simplify_subreg (SImode, operands[0], DImode, 0), | |
1886 | simplify_subreg (SImode, operands[1], DImode, 0)); | |
1887 | emit_move_insn (simplify_subreg (SImode, operands[0], DImode, 4), | |
1888 | simplify_subreg (SImode, operands[1], DImode, 4)); | |
1889 | } | |
1890 | else | |
1891 | { | |
1892 | emit_move_insn (gen_lowpart (SImode, operands[0]), | |
1893 | gen_lowpart (SImode, operands[1])); | |
1894 | emit_move_insn (gen_highpart (SImode, operands[0]), | |
1895 | gen_highpart (SImode, operands[1])); | |
1896 | } | |
c9e8cb32 DD |
1897 | return; |
1898 | } | |
fb4d4348 GK |
1899 | |
1900 | if (! no_new_pseudos && GET_CODE (operands[0]) != REG) | |
1901 | operands[1] = force_reg (mode, operands[1]); | |
a9098fd0 | 1902 | |
ffc14f31 GK |
1903 | if (mode == SFmode && ! TARGET_POWERPC && TARGET_HARD_FLOAT |
1904 | && GET_CODE (operands[0]) == MEM) | |
fb4d4348 | 1905 | { |
ffc14f31 GK |
1906 | int regnum; |
1907 | ||
1908 | if (reload_in_progress || reload_completed) | |
1909 | regnum = true_regnum (operands[1]); | |
1910 | else if (GET_CODE (operands[1]) == REG) | |
1911 | regnum = REGNO (operands[1]); | |
1912 | else | |
1913 | regnum = -1; | |
fb4d4348 GK |
1914 | |
1915 | /* If operands[1] is a register, on POWER it may have | |
1916 | double-precision data in it, so truncate it to single | |
1917 | precision. */ | |
1918 | if (FP_REGNO_P (regnum) || regnum >= FIRST_PSEUDO_REGISTER) | |
1919 | { | |
1920 | rtx newreg; | |
1921 | newreg = (no_new_pseudos ? operands[1] : gen_reg_rtx (mode)); | |
1922 | emit_insn (gen_aux_truncdfsf2 (newreg, operands[1])); | |
1923 | operands[1] = newreg; | |
1924 | } | |
1925 | } | |
1926 | ||
a9098fd0 GK |
1927 | /* Handle the case where reload calls us with an invalid address; |
1928 | and the case of CONSTANT_P_RTX. */ | |
1929 | if (! general_operand (operands[1], mode) | |
1930 | || ! nonimmediate_operand (operands[0], mode) | |
1931 | || GET_CODE (operands[1]) == CONSTANT_P_RTX) | |
fb4d4348 GK |
1932 | { |
1933 | emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1])); | |
1934 | return; | |
1935 | } | |
a9098fd0 | 1936 | |
fb4d4348 GK |
1937 | /* FIXME: In the long term, this switch statement should go away |
1938 | and be replaced by a sequence of tests based on things like | |
1939 | mode == Pmode. */ | |
1940 | switch (mode) | |
1941 | { | |
1942 | case HImode: | |
1943 | case QImode: | |
1944 | if (CONSTANT_P (operands[1]) | |
1945 | && GET_CODE (operands[1]) != CONST_INT) | |
a9098fd0 | 1946 | operands[1] = force_const_mem (mode, operands[1]); |
fb4d4348 GK |
1947 | break; |
1948 | ||
06f4e019 | 1949 | case TFmode: |
fb4d4348 GK |
1950 | case DFmode: |
1951 | case SFmode: | |
1952 | if (CONSTANT_P (operands[1]) | |
1953 | && ! easy_fp_constant (operands[1], mode)) | |
a9098fd0 | 1954 | operands[1] = force_const_mem (mode, operands[1]); |
fb4d4348 GK |
1955 | break; |
1956 | ||
0ac081f6 AH |
1957 | case V16QImode: |
1958 | case V8HImode: | |
1959 | case V4SFmode: | |
1960 | case V4SImode: | |
1961 | /* fixme: aldyh -- allow vector constants when they are implemented. */ | |
1962 | if (CONSTANT_P (operands[1])) | |
1963 | operands[1] = force_const_mem (mode, operands[1]); | |
1964 | break; | |
1965 | ||
fb4d4348 | 1966 | case SImode: |
a9098fd0 | 1967 | case DImode: |
fb4d4348 GK |
1968 | /* Use default pattern for address of ELF small data */ |
1969 | if (TARGET_ELF | |
a9098fd0 | 1970 | && mode == Pmode |
f607bc57 | 1971 | && DEFAULT_ABI == ABI_V4 |
a9098fd0 GK |
1972 | && (GET_CODE (operands[1]) == SYMBOL_REF |
1973 | || GET_CODE (operands[1]) == CONST) | |
1974 | && small_data_operand (operands[1], mode)) | |
fb4d4348 GK |
1975 | { |
1976 | emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1])); | |
1977 | return; | |
1978 | } | |
1979 | ||
f607bc57 | 1980 | if (DEFAULT_ABI == ABI_V4 |
a9098fd0 GK |
1981 | && mode == Pmode && mode == SImode |
1982 | && flag_pic == 1 && got_operand (operands[1], mode)) | |
fb4d4348 GK |
1983 | { |
1984 | emit_insn (gen_movsi_got (operands[0], operands[1])); | |
1985 | return; | |
1986 | } | |
1987 | ||
ee890fe2 SS |
1988 | if ((TARGET_ELF || DEFAULT_ABI == ABI_DARWIN) |
1989 | && TARGET_NO_TOC && ! flag_pic | |
a9098fd0 | 1990 | && mode == Pmode |
fb4d4348 GK |
1991 | && CONSTANT_P (operands[1]) |
1992 | && GET_CODE (operands[1]) != HIGH | |
1993 | && GET_CODE (operands[1]) != CONST_INT) | |
1994 | { | |
a9098fd0 | 1995 | rtx target = (no_new_pseudos ? operands[0] : gen_reg_rtx (mode)); |
fb4d4348 GK |
1996 | |
1997 | /* If this is a function address on -mcall-aixdesc, | |
1998 | convert it to the address of the descriptor. */ | |
1999 | if (DEFAULT_ABI == ABI_AIX | |
2000 | && GET_CODE (operands[1]) == SYMBOL_REF | |
2001 | && XSTR (operands[1], 0)[0] == '.') | |
2002 | { | |
2003 | const char *name = XSTR (operands[1], 0); | |
2004 | rtx new_ref; | |
2005 | while (*name == '.') | |
2006 | name++; | |
2007 | new_ref = gen_rtx_SYMBOL_REF (Pmode, name); | |
2008 | CONSTANT_POOL_ADDRESS_P (new_ref) | |
2009 | = CONSTANT_POOL_ADDRESS_P (operands[1]); | |
2010 | SYMBOL_REF_FLAG (new_ref) = SYMBOL_REF_FLAG (operands[1]); | |
2011 | SYMBOL_REF_USED (new_ref) = SYMBOL_REF_USED (operands[1]); | |
2012 | operands[1] = new_ref; | |
2013 | } | |
7509c759 | 2014 | |
ee890fe2 SS |
2015 | if (DEFAULT_ABI == ABI_DARWIN) |
2016 | { | |
2017 | emit_insn (gen_macho_high (target, operands[1])); | |
2018 | emit_insn (gen_macho_low (operands[0], target, operands[1])); | |
2019 | return; | |
2020 | } | |
2021 | ||
fb4d4348 GK |
2022 | emit_insn (gen_elf_high (target, operands[1])); |
2023 | emit_insn (gen_elf_low (operands[0], target, operands[1])); | |
2024 | return; | |
2025 | } | |
2026 | ||
a9098fd0 GK |
2027 | /* If this is a SYMBOL_REF that refers to a constant pool entry, |
2028 | and we have put it in the TOC, we just need to make a TOC-relative | |
2029 | reference to it. */ | |
2030 | if (TARGET_TOC | |
2031 | && GET_CODE (operands[1]) == SYMBOL_REF | |
2032 | && CONSTANT_POOL_EXPR_P (operands[1]) | |
2033 | && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (operands[1]), | |
2034 | get_pool_mode (operands[1]))) | |
fb4d4348 | 2035 | { |
a9098fd0 | 2036 | operands[1] = create_TOC_reference (operands[1]); |
fb4d4348 | 2037 | } |
a9098fd0 GK |
2038 | else if (mode == Pmode |
2039 | && CONSTANT_P (operands[1]) | |
38886f37 AO |
2040 | && ((GET_CODE (operands[1]) != CONST_INT |
2041 | && ! easy_fp_constant (operands[1], mode)) | |
2042 | || (GET_CODE (operands[1]) == CONST_INT | |
2043 | && num_insns_constant (operands[1], mode) > 2) | |
2044 | || (GET_CODE (operands[0]) == REG | |
2045 | && FP_REGNO_P (REGNO (operands[0])))) | |
a9098fd0 GK |
2046 | && GET_CODE (operands[1]) != HIGH |
2047 | && ! LEGITIMATE_CONSTANT_POOL_ADDRESS_P (operands[1]) | |
2048 | && ! TOC_RELATIVE_EXPR_P (operands[1])) | |
fb4d4348 GK |
2049 | { |
2050 | /* Emit a USE operation so that the constant isn't deleted if | |
2051 | expensive optimizations are turned on because nobody | |
2052 | references it. This should only be done for operands that | |
2053 | contain SYMBOL_REFs with CONSTANT_POOL_ADDRESS_P set. | |
2054 | This should not be done for operands that contain LABEL_REFs. | |
2055 | For now, we just handle the obvious case. */ | |
2056 | if (GET_CODE (operands[1]) != LABEL_REF) | |
2057 | emit_insn (gen_rtx_USE (VOIDmode, operands[1])); | |
2058 | ||
ee890fe2 SS |
2059 | /* Darwin uses a special PIC legitimizer. */ |
2060 | if (DEFAULT_ABI == ABI_DARWIN && flag_pic) | |
2061 | { | |
78e1b90d | 2062 | #if TARGET_MACHO |
ee890fe2 SS |
2063 | rtx temp_reg = ((reload_in_progress || reload_completed) |
2064 | ? operands[0] : NULL); | |
2065 | ||
ee890fe2 SS |
2066 | operands[1] = |
2067 | rs6000_machopic_legitimize_pic_address (operands[1], mode, | |
a4f6c312 | 2068 | temp_reg); |
ee890fe2 SS |
2069 | #endif |
2070 | emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1])); | |
2071 | return; | |
2072 | } | |
2073 | ||
fb4d4348 GK |
2074 | /* If we are to limit the number of things we put in the TOC and |
2075 | this is a symbol plus a constant we can add in one insn, | |
2076 | just put the symbol in the TOC and add the constant. Don't do | |
2077 | this if reload is in progress. */ | |
2078 | if (GET_CODE (operands[1]) == CONST | |
2079 | && TARGET_NO_SUM_IN_TOC && ! reload_in_progress | |
2080 | && GET_CODE (XEXP (operands[1], 0)) == PLUS | |
a9098fd0 | 2081 | && add_operand (XEXP (XEXP (operands[1], 0), 1), mode) |
fb4d4348 GK |
2082 | && (GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == LABEL_REF |
2083 | || GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == SYMBOL_REF) | |
2084 | && ! side_effects_p (operands[0])) | |
2085 | { | |
a4f6c312 SS |
2086 | rtx sym = |
2087 | force_const_mem (mode, XEXP (XEXP (operands[1], 0), 0)); | |
fb4d4348 GK |
2088 | rtx other = XEXP (XEXP (operands[1], 0), 1); |
2089 | ||
a9098fd0 GK |
2090 | sym = force_reg (mode, sym); |
2091 | if (mode == SImode) | |
2092 | emit_insn (gen_addsi3 (operands[0], sym, other)); | |
2093 | else | |
2094 | emit_insn (gen_adddi3 (operands[0], sym, other)); | |
fb4d4348 GK |
2095 | return; |
2096 | } | |
2097 | ||
a9098fd0 | 2098 | operands[1] = force_const_mem (mode, operands[1]); |
fb4d4348 GK |
2099 | |
2100 | if (TARGET_TOC | |
d34c5b80 DE |
2101 | && CONSTANT_POOL_EXPR_P (XEXP (operands[1], 0)) |
2102 | && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P ( | |
2103 | get_pool_constant (XEXP (operands[1], 0)), | |
2104 | get_pool_mode (XEXP (operands[1], 0)))) | |
a9098fd0 | 2105 | { |
ba4828e0 RK |
2106 | operands[1] |
2107 | = gen_rtx_MEM (mode, | |
2108 | create_TOC_reference (XEXP (operands[1], 0))); | |
2109 | set_mem_alias_set (operands[1], get_TOC_alias_set ()); | |
fb4d4348 | 2110 | RTX_UNCHANGING_P (operands[1]) = 1; |
a9098fd0 | 2111 | } |
fb4d4348 GK |
2112 | } |
2113 | break; | |
a9098fd0 | 2114 | |
fb4d4348 GK |
2115 | case TImode: |
2116 | if (GET_CODE (operands[0]) == MEM | |
2117 | && GET_CODE (XEXP (operands[0], 0)) != REG | |
2118 | && ! reload_in_progress) | |
792760b9 RK |
2119 | operands[0] |
2120 | = replace_equiv_address (operands[0], | |
2121 | copy_addr_to_reg (XEXP (operands[0], 0))); | |
fb4d4348 GK |
2122 | |
2123 | if (GET_CODE (operands[1]) == MEM | |
2124 | && GET_CODE (XEXP (operands[1], 0)) != REG | |
2125 | && ! reload_in_progress) | |
792760b9 RK |
2126 | operands[1] |
2127 | = replace_equiv_address (operands[1], | |
2128 | copy_addr_to_reg (XEXP (operands[1], 0))); | |
fb4d4348 GK |
2129 | break; |
2130 | ||
2131 | default: | |
2132 | abort (); | |
2133 | } | |
2134 | ||
a9098fd0 GK |
2135 | /* Above, we may have called force_const_mem which may have returned |
2136 | an invalid address. If we can, fix this up; otherwise, reload will | |
2137 | have to deal with it. */ | |
2138 | if (GET_CODE (operands[1]) == MEM | |
2139 | && ! memory_address_p (mode, XEXP (operands[1], 0)) | |
2140 | && ! reload_in_progress) | |
f4ef873c | 2141 | operands[1] = adjust_address (operands[1], mode, 0); |
a9098fd0 | 2142 | |
fb4d4348 | 2143 | emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1])); |
02a4ec28 | 2144 | return; |
fb4d4348 | 2145 | } |
4697a36c MM |
2146 | \f |
2147 | /* Initialize a variable CUM of type CUMULATIVE_ARGS | |
2148 | for a call to a function whose data type is FNTYPE. | |
2149 | For a library call, FNTYPE is 0. | |
2150 | ||
2151 | For incoming args we set the number of arguments in the prototype large | |
1c20ae99 | 2152 | so we never return a PARALLEL. */ |
4697a36c MM |
2153 | |
2154 | void | |
2155 | init_cumulative_args (cum, fntype, libname, incoming) | |
2156 | CUMULATIVE_ARGS *cum; | |
2157 | tree fntype; | |
296b8152 | 2158 | rtx libname ATTRIBUTE_UNUSED; |
4697a36c MM |
2159 | int incoming; |
2160 | { | |
2161 | static CUMULATIVE_ARGS zero_cumulative; | |
2162 | ||
2163 | *cum = zero_cumulative; | |
2164 | cum->words = 0; | |
2165 | cum->fregno = FP_ARG_MIN_REG; | |
0ac081f6 | 2166 | cum->vregno = ALTIVEC_ARG_MIN_REG; |
4697a36c | 2167 | cum->prototype = (fntype && TYPE_ARG_TYPES (fntype)); |
7509c759 | 2168 | cum->call_cookie = CALL_NORMAL; |
4cc833b7 | 2169 | cum->sysv_gregno = GP_ARG_MIN_REG; |
4697a36c MM |
2170 | |
2171 | if (incoming) | |
bd227acc | 2172 | cum->nargs_prototype = 1000; /* don't return a PARALLEL */ |
4697a36c MM |
2173 | |
2174 | else if (cum->prototype) | |
2175 | cum->nargs_prototype = (list_length (TYPE_ARG_TYPES (fntype)) - 1 | |
2176 | + (TYPE_MODE (TREE_TYPE (fntype)) == BLKmode | |
2177 | || RETURN_IN_MEMORY (TREE_TYPE (fntype)))); | |
2178 | ||
2179 | else | |
2180 | cum->nargs_prototype = 0; | |
2181 | ||
2182 | cum->orig_nargs = cum->nargs_prototype; | |
7509c759 | 2183 | |
9ebbca7d GK |
2184 | /* Check for longcall's */ |
2185 | if (fntype && lookup_attribute ("longcall", TYPE_ATTRIBUTES (fntype))) | |
6a4cee5f MM |
2186 | cum->call_cookie = CALL_LONG; |
2187 | ||
4697a36c MM |
2188 | if (TARGET_DEBUG_ARG) |
2189 | { | |
2190 | fprintf (stderr, "\ninit_cumulative_args:"); | |
2191 | if (fntype) | |
2192 | { | |
2193 | tree ret_type = TREE_TYPE (fntype); | |
2194 | fprintf (stderr, " ret code = %s,", | |
2195 | tree_code_name[ (int)TREE_CODE (ret_type) ]); | |
2196 | } | |
2197 | ||
6a4cee5f MM |
2198 | if (cum->call_cookie & CALL_LONG) |
2199 | fprintf (stderr, " longcall,"); | |
2200 | ||
4697a36c MM |
2201 | fprintf (stderr, " proto = %d, nargs = %d\n", |
2202 | cum->prototype, cum->nargs_prototype); | |
2203 | } | |
2204 | } | |
2205 | \f | |
c229cba9 DE |
2206 | /* If defined, a C expression which determines whether, and in which |
2207 | direction, to pad out an argument with extra space. The value | |
2208 | should be of type `enum direction': either `upward' to pad above | |
2209 | the argument, `downward' to pad below, or `none' to inhibit | |
2210 | padding. | |
2211 | ||
2212 | For the AIX ABI structs are always stored left shifted in their | |
2213 | argument slot. */ | |
2214 | ||
9ebbca7d | 2215 | enum direction |
c229cba9 DE |
2216 | function_arg_padding (mode, type) |
2217 | enum machine_mode mode; | |
2218 | tree type; | |
2219 | { | |
c85f7c16 | 2220 | if (type != 0 && AGGREGATE_TYPE_P (type)) |
9ebbca7d | 2221 | return upward; |
c229cba9 DE |
2222 | |
2223 | /* This is the default definition. */ | |
2224 | return (! BYTES_BIG_ENDIAN | |
9ebbca7d | 2225 | ? upward |
c229cba9 DE |
2226 | : ((mode == BLKmode |
2227 | ? (type && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST | |
2228 | && int_size_in_bytes (type) < (PARM_BOUNDARY / BITS_PER_UNIT)) | |
2229 | : GET_MODE_BITSIZE (mode) < PARM_BOUNDARY) | |
9ebbca7d | 2230 | ? downward : upward)); |
c229cba9 DE |
2231 | } |
2232 | ||
b6c9286a MM |
2233 | /* If defined, a C expression that gives the alignment boundary, in bits, |
2234 | of an argument with the specified mode and type. If it is not defined, | |
2235 | PARM_BOUNDARY is used for all arguments. | |
2236 | ||
2310f99a | 2237 | V.4 wants long longs to be double word aligned. */ |
b6c9286a MM |
2238 | |
2239 | int | |
2240 | function_arg_boundary (mode, type) | |
2241 | enum machine_mode mode; | |
9ebbca7d | 2242 | tree type ATTRIBUTE_UNUSED; |
b6c9286a | 2243 | { |
f607bc57 | 2244 | if (DEFAULT_ABI == ABI_V4 && (mode == DImode || mode == DFmode)) |
e1f83b4d | 2245 | return 64; |
0ac081f6 AH |
2246 | else if (TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode)) |
2247 | return 128; | |
9ebbca7d | 2248 | else |
b6c9286a | 2249 | return PARM_BOUNDARY; |
b6c9286a MM |
2250 | } |
2251 | \f | |
4697a36c MM |
2252 | /* Update the data in CUM to advance over an argument |
2253 | of mode MODE and data type TYPE. | |
2254 | (TYPE is null for libcalls where that information may not be available.) */ | |
2255 | ||
2256 | void | |
2257 | function_arg_advance (cum, mode, type, named) | |
2258 | CUMULATIVE_ARGS *cum; | |
2259 | enum machine_mode mode; | |
2260 | tree type; | |
2261 | int named; | |
2262 | { | |
2263 | cum->nargs_prototype--; | |
2264 | ||
0ac081f6 AH |
2265 | if (TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode)) |
2266 | { | |
2267 | if (cum->vregno <= ALTIVEC_ARG_MAX_REG && cum->nargs_prototype >= 0) | |
2268 | cum->vregno++; | |
2269 | else | |
2270 | cum->words += RS6000_ARG_SIZE (mode, type); | |
2271 | } | |
f607bc57 | 2272 | else if (DEFAULT_ABI == ABI_V4) |
4697a36c | 2273 | { |
4cc833b7 RH |
2274 | if (TARGET_HARD_FLOAT |
2275 | && (mode == SFmode || mode == DFmode)) | |
4697a36c | 2276 | { |
4cc833b7 RH |
2277 | if (cum->fregno <= FP_ARG_V4_MAX_REG) |
2278 | cum->fregno++; | |
2279 | else | |
2280 | { | |
2281 | if (mode == DFmode) | |
2282 | cum->words += cum->words & 1; | |
d34c5b80 | 2283 | cum->words += RS6000_ARG_SIZE (mode, type); |
4cc833b7 | 2284 | } |
4697a36c | 2285 | } |
4cc833b7 RH |
2286 | else |
2287 | { | |
2288 | int n_words; | |
2289 | int gregno = cum->sysv_gregno; | |
2290 | ||
2291 | /* Aggregates and IEEE quad get passed by reference. */ | |
2292 | if ((type && AGGREGATE_TYPE_P (type)) | |
2293 | || mode == TFmode) | |
2294 | n_words = 1; | |
2295 | else | |
d34c5b80 | 2296 | n_words = RS6000_ARG_SIZE (mode, type); |
4cc833b7 RH |
2297 | |
2298 | /* Long long is put in odd registers. */ | |
2299 | if (n_words == 2 && (gregno & 1) == 0) | |
2300 | gregno += 1; | |
2301 | ||
2302 | /* Long long is not split between registers and stack. */ | |
2303 | if (gregno + n_words - 1 > GP_ARG_MAX_REG) | |
2304 | { | |
2305 | /* Long long is aligned on the stack. */ | |
2306 | if (n_words == 2) | |
2307 | cum->words += cum->words & 1; | |
2308 | cum->words += n_words; | |
2309 | } | |
4697a36c | 2310 | |
4cc833b7 RH |
2311 | /* Note: continuing to accumulate gregno past when we've started |
2312 | spilling to the stack indicates the fact that we've started | |
2313 | spilling to the stack to expand_builtin_saveregs. */ | |
2314 | cum->sysv_gregno = gregno + n_words; | |
2315 | } | |
4697a36c | 2316 | |
4cc833b7 RH |
2317 | if (TARGET_DEBUG_ARG) |
2318 | { | |
2319 | fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ", | |
2320 | cum->words, cum->fregno); | |
2321 | fprintf (stderr, "gregno = %2d, nargs = %4d, proto = %d, ", | |
2322 | cum->sysv_gregno, cum->nargs_prototype, cum->prototype); | |
2323 | fprintf (stderr, "mode = %4s, named = %d\n", | |
2324 | GET_MODE_NAME (mode), named); | |
2325 | } | |
4697a36c MM |
2326 | } |
2327 | else | |
4cc833b7 RH |
2328 | { |
2329 | int align = (TARGET_32BIT && (cum->words & 1) != 0 | |
2330 | && function_arg_boundary (mode, type) == 64) ? 1 : 0; | |
a4f6c312 | 2331 | |
d34c5b80 | 2332 | cum->words += align + RS6000_ARG_SIZE (mode, type); |
4697a36c | 2333 | |
d34c5b80 DE |
2334 | if (GET_MODE_CLASS (mode) == MODE_FLOAT && TARGET_HARD_FLOAT) |
2335 | cum->fregno++; | |
4cc833b7 RH |
2336 | |
2337 | if (TARGET_DEBUG_ARG) | |
2338 | { | |
2339 | fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ", | |
2340 | cum->words, cum->fregno); | |
2341 | fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s, ", | |
2342 | cum->nargs_prototype, cum->prototype, GET_MODE_NAME (mode)); | |
2343 | fprintf (stderr, "named = %d, align = %d\n", named, align); | |
2344 | } | |
2345 | } | |
4697a36c MM |
2346 | } |
2347 | \f | |
2348 | /* Determine where to put an argument to a function. | |
2349 | Value is zero to push the argument on the stack, | |
2350 | or a hard register in which to store the argument. | |
2351 | ||
2352 | MODE is the argument's machine mode. | |
2353 | TYPE is the data type of the argument (as a tree). | |
2354 | This is null for libcalls where that information may | |
2355 | not be available. | |
2356 | CUM is a variable of type CUMULATIVE_ARGS which gives info about | |
2357 | the preceding args and about the function being called. | |
2358 | NAMED is nonzero if this argument is a named parameter | |
2359 | (otherwise it is an extra parameter matching an ellipsis). | |
2360 | ||
2361 | On RS/6000 the first eight words of non-FP are normally in registers | |
2362 | and the rest are pushed. Under AIX, the first 13 FP args are in registers. | |
2363 | Under V.4, the first 8 FP args are in registers. | |
2364 | ||
2365 | If this is floating-point and no prototype is specified, we use | |
2366 | both an FP and integer register (or possibly FP reg and stack). Library | |
2367 | functions (when TYPE is zero) always have the proper types for args, | |
2368 | so we can pass the FP value just in one register. emit_library_function | |
1c20ae99 | 2369 | doesn't support PARALLEL anyway. */ |
4697a36c MM |
2370 | |
2371 | struct rtx_def * | |
2372 | function_arg (cum, mode, type, named) | |
2373 | CUMULATIVE_ARGS *cum; | |
2374 | enum machine_mode mode; | |
2375 | tree type; | |
20c29ebe | 2376 | int named; |
4697a36c | 2377 | { |
4cc833b7 | 2378 | enum rs6000_abi abi = DEFAULT_ABI; |
4697a36c | 2379 | |
a4f6c312 SS |
2380 | /* Return a marker to indicate whether CR1 needs to set or clear the |
2381 | bit that V.4 uses to say fp args were passed in registers. | |
2382 | Assume that we don't need the marker for software floating point, | |
2383 | or compiler generated library calls. */ | |
4697a36c MM |
2384 | if (mode == VOIDmode) |
2385 | { | |
f607bc57 | 2386 | if (abi == ABI_V4 |
7509c759 MM |
2387 | && TARGET_HARD_FLOAT |
2388 | && cum->nargs_prototype < 0 | |
4697a36c | 2389 | && type && (cum->prototype || TARGET_NO_PROTOTYPE)) |
7509c759 | 2390 | { |
6a4cee5f MM |
2391 | return GEN_INT (cum->call_cookie |
2392 | | ((cum->fregno == FP_ARG_MIN_REG) | |
2393 | ? CALL_V4_SET_FP_ARGS | |
2394 | : CALL_V4_CLEAR_FP_ARGS)); | |
7509c759 | 2395 | } |
4697a36c | 2396 | |
7509c759 | 2397 | return GEN_INT (cum->call_cookie); |
4697a36c MM |
2398 | } |
2399 | ||
0ac081f6 AH |
2400 | if (TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode)) |
2401 | { | |
20c29ebe | 2402 | if (named && cum->vregno <= ALTIVEC_ARG_MAX_REG) |
0ac081f6 AH |
2403 | return gen_rtx_REG (mode, cum->vregno); |
2404 | else | |
2405 | return NULL; | |
2406 | } | |
f607bc57 | 2407 | else if (abi == ABI_V4) |
4697a36c | 2408 | { |
4cc833b7 RH |
2409 | if (TARGET_HARD_FLOAT |
2410 | && (mode == SFmode || mode == DFmode)) | |
2411 | { | |
2412 | if (cum->fregno <= FP_ARG_V4_MAX_REG) | |
2413 | return gen_rtx_REG (mode, cum->fregno); | |
2414 | else | |
2415 | return NULL; | |
2416 | } | |
2417 | else | |
2418 | { | |
2419 | int n_words; | |
2420 | int gregno = cum->sysv_gregno; | |
2421 | ||
2422 | /* Aggregates and IEEE quad get passed by reference. */ | |
2423 | if ((type && AGGREGATE_TYPE_P (type)) | |
2424 | || mode == TFmode) | |
2425 | n_words = 1; | |
2426 | else | |
d34c5b80 | 2427 | n_words = RS6000_ARG_SIZE (mode, type); |
4cc833b7 RH |
2428 | |
2429 | /* Long long is put in odd registers. */ | |
2430 | if (n_words == 2 && (gregno & 1) == 0) | |
2431 | gregno += 1; | |
2432 | ||
2433 | /* Long long is not split between registers and stack. */ | |
2434 | if (gregno + n_words - 1 <= GP_ARG_MAX_REG) | |
2435 | return gen_rtx_REG (mode, gregno); | |
2436 | else | |
2437 | return NULL; | |
2438 | } | |
4697a36c | 2439 | } |
4cc833b7 RH |
2440 | else |
2441 | { | |
2442 | int align = (TARGET_32BIT && (cum->words & 1) != 0 | |
2443 | && function_arg_boundary (mode, type) == 64) ? 1 : 0; | |
2444 | int align_words = cum->words + align; | |
4697a36c | 2445 | |
4cc833b7 RH |
2446 | if (type && TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST) |
2447 | return NULL_RTX; | |
2448 | ||
2449 | if (USE_FP_FOR_ARG_P (*cum, mode, type)) | |
2450 | { | |
2451 | if (! type | |
2452 | || ((cum->nargs_prototype > 0) | |
2453 | /* IBM AIX extended its linkage convention definition always | |
2454 | to require FP args after register save area hole on the | |
2455 | stack. */ | |
2456 | && (DEFAULT_ABI != ABI_AIX | |
2457 | || ! TARGET_XL_CALL | |
2458 | || (align_words < GP_ARG_NUM_REG)))) | |
2459 | return gen_rtx_REG (mode, cum->fregno); | |
2460 | ||
2461 | return gen_rtx_PARALLEL (mode, | |
2462 | gen_rtvec (2, | |
39403d82 | 2463 | gen_rtx_EXPR_LIST (VOIDmode, |
1c20ae99 JW |
2464 | ((align_words >= GP_ARG_NUM_REG) |
2465 | ? NULL_RTX | |
2466 | : (align_words | |
d34c5b80 | 2467 | + RS6000_ARG_SIZE (mode, type) |
1c20ae99 JW |
2468 | > GP_ARG_NUM_REG |
2469 | /* If this is partially on the stack, then | |
2470 | we only include the portion actually | |
2471 | in registers here. */ | |
39403d82 | 2472 | ? gen_rtx_REG (SImode, |
1c20ae99 | 2473 | GP_ARG_MIN_REG + align_words) |
39403d82 | 2474 | : gen_rtx_REG (mode, |
1c20ae99 JW |
2475 | GP_ARG_MIN_REG + align_words))), |
2476 | const0_rtx), | |
39403d82 DE |
2477 | gen_rtx_EXPR_LIST (VOIDmode, |
2478 | gen_rtx_REG (mode, cum->fregno), | |
1c20ae99 | 2479 | const0_rtx))); |
4cc833b7 RH |
2480 | } |
2481 | else if (align_words < GP_ARG_NUM_REG) | |
2482 | return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words); | |
2483 | else | |
2484 | return NULL_RTX; | |
4697a36c | 2485 | } |
4697a36c MM |
2486 | } |
2487 | \f | |
2488 | /* For an arg passed partly in registers and partly in memory, | |
2489 | this is the number of registers used. | |
2490 | For args passed entirely in registers or entirely in memory, zero. */ | |
2491 | ||
2492 | int | |
2493 | function_arg_partial_nregs (cum, mode, type, named) | |
2494 | CUMULATIVE_ARGS *cum; | |
2495 | enum machine_mode mode; | |
2496 | tree type; | |
d34c5b80 | 2497 | int named ATTRIBUTE_UNUSED; |
4697a36c | 2498 | { |
f607bc57 | 2499 | if (DEFAULT_ABI == ABI_V4) |
4697a36c | 2500 | return 0; |
4697a36c | 2501 | |
0ac081f6 AH |
2502 | if (USE_FP_FOR_ARG_P (*cum, mode, type) |
2503 | || USE_ALTIVEC_FOR_ARG_P (*cum, mode, type)) | |
4697a36c MM |
2504 | { |
2505 | if (cum->nargs_prototype >= 0) | |
2506 | return 0; | |
2507 | } | |
2508 | ||
2509 | if (cum->words < GP_ARG_NUM_REG | |
d34c5b80 | 2510 | && GP_ARG_NUM_REG < (cum->words + RS6000_ARG_SIZE (mode, type))) |
4697a36c MM |
2511 | { |
2512 | int ret = GP_ARG_NUM_REG - cum->words; | |
2513 | if (ret && TARGET_DEBUG_ARG) | |
2514 | fprintf (stderr, "function_arg_partial_nregs: %d\n", ret); | |
2515 | ||
2516 | return ret; | |
2517 | } | |
2518 | ||
2519 | return 0; | |
2520 | } | |
2521 | \f | |
2522 | /* A C expression that indicates when an argument must be passed by | |
2523 | reference. If nonzero for an argument, a copy of that argument is | |
2524 | made in memory and a pointer to the argument is passed instead of | |
2525 | the argument itself. The pointer is passed in whatever way is | |
2526 | appropriate for passing a pointer to that type. | |
2527 | ||
2528 | Under V.4, structures and unions are passed by reference. */ | |
2529 | ||
2530 | int | |
2531 | function_arg_pass_by_reference (cum, mode, type, named) | |
296b8152 KG |
2532 | CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED; |
2533 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
4697a36c | 2534 | tree type; |
296b8152 | 2535 | int named ATTRIBUTE_UNUSED; |
4697a36c | 2536 | { |
f607bc57 | 2537 | if (DEFAULT_ABI == ABI_V4 |
4cc833b7 RH |
2538 | && ((type && AGGREGATE_TYPE_P (type)) |
2539 | || mode == TFmode)) | |
4697a36c MM |
2540 | { |
2541 | if (TARGET_DEBUG_ARG) | |
2542 | fprintf (stderr, "function_arg_pass_by_reference: aggregate\n"); | |
2543 | ||
2544 | return 1; | |
2545 | } | |
4697a36c MM |
2546 | |
2547 | return 0; | |
2548 | } | |
4697a36c MM |
2549 | \f |
2550 | /* Perform any needed actions needed for a function that is receiving a | |
2551 | variable number of arguments. | |
2552 | ||
2553 | CUM is as above. | |
2554 | ||
2555 | MODE and TYPE are the mode and type of the current parameter. | |
2556 | ||
2557 | PRETEND_SIZE is a variable that should be set to the amount of stack | |
2558 | that must be pushed by the prolog to pretend that our caller pushed | |
2559 | it. | |
2560 | ||
2561 | Normally, this macro will push all remaining incoming registers on the | |
2562 | stack and set PRETEND_SIZE to the length of the registers pushed. */ | |
2563 | ||
2564 | void | |
2565 | setup_incoming_varargs (cum, mode, type, pretend_size, no_rtl) | |
2566 | CUMULATIVE_ARGS *cum; | |
2567 | enum machine_mode mode; | |
2568 | tree type; | |
2569 | int *pretend_size; | |
2570 | int no_rtl; | |
2571 | ||
2572 | { | |
4cc833b7 RH |
2573 | CUMULATIVE_ARGS next_cum; |
2574 | int reg_size = TARGET_32BIT ? 4 : 8; | |
ca5adc63 | 2575 | rtx save_area = NULL_RTX, mem; |
dfafc897 | 2576 | int first_reg_offset, set; |
d34c5b80 DE |
2577 | tree fntype; |
2578 | int stdarg_p; | |
4697a36c | 2579 | |
d34c5b80 DE |
2580 | fntype = TREE_TYPE (current_function_decl); |
2581 | stdarg_p = (TYPE_ARG_TYPES (fntype) != 0 | |
2582 | && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype))) | |
2583 | != void_type_node)); | |
4cc833b7 | 2584 | |
d34c5b80 DE |
2585 | /* For varargs, we do not want to skip the dummy va_dcl argument. |
2586 | For stdargs, we do want to skip the last named argument. */ | |
2587 | next_cum = *cum; | |
2588 | if (stdarg_p) | |
2589 | function_arg_advance (&next_cum, mode, type, 1); | |
4cc833b7 | 2590 | |
f607bc57 | 2591 | if (DEFAULT_ABI == ABI_V4) |
d34c5b80 | 2592 | { |
4cc833b7 RH |
2593 | /* Indicate to allocate space on the stack for varargs save area. */ |
2594 | /* ??? Does this really have to be located at a magic spot on the | |
2595 | stack, or can we allocate this with assign_stack_local instead. */ | |
00dba523 | 2596 | cfun->machine->sysv_varargs_p = 1; |
60e2d0ca | 2597 | if (! no_rtl) |
2c4974b7 | 2598 | save_area = plus_constant (virtual_stack_vars_rtx, |
bd227acc | 2599 | - RS6000_VARARGS_SIZE); |
4cc833b7 RH |
2600 | |
2601 | first_reg_offset = next_cum.sysv_gregno - GP_ARG_MIN_REG; | |
4697a36c | 2602 | } |
60e2d0ca | 2603 | else |
4697a36c | 2604 | { |
d34c5b80 | 2605 | first_reg_offset = next_cum.words; |
4cc833b7 | 2606 | save_area = virtual_incoming_args_rtx; |
00dba523 | 2607 | cfun->machine->sysv_varargs_p = 0; |
4697a36c MM |
2608 | |
2609 | if (MUST_PASS_IN_STACK (mode, type)) | |
d34c5b80 | 2610 | first_reg_offset += RS6000_ARG_SIZE (TYPE_MODE (type), type); |
4cc833b7 | 2611 | } |
4697a36c | 2612 | |
dfafc897 | 2613 | set = get_varargs_alias_set (); |
c81fc13e | 2614 | if (! no_rtl && first_reg_offset < GP_ARG_NUM_REG) |
4cc833b7 | 2615 | { |
dfafc897 FS |
2616 | mem = gen_rtx_MEM (BLKmode, |
2617 | plus_constant (save_area, | |
2618 | first_reg_offset * reg_size)), | |
ba4828e0 | 2619 | set_mem_alias_set (mem, set); |
8ac61af7 | 2620 | set_mem_align (mem, BITS_PER_WORD); |
dfafc897 | 2621 | |
4cc833b7 | 2622 | move_block_from_reg |
dfafc897 | 2623 | (GP_ARG_MIN_REG + first_reg_offset, mem, |
4cc833b7 RH |
2624 | GP_ARG_NUM_REG - first_reg_offset, |
2625 | (GP_ARG_NUM_REG - first_reg_offset) * UNITS_PER_WORD); | |
2626 | ||
2627 | /* ??? Does ABI_V4 need this at all? */ | |
4697a36c MM |
2628 | *pretend_size = (GP_ARG_NUM_REG - first_reg_offset) * UNITS_PER_WORD; |
2629 | } | |
2630 | ||
4697a36c | 2631 | /* Save FP registers if needed. */ |
f607bc57 | 2632 | if (DEFAULT_ABI == ABI_V4 |
c81fc13e | 2633 | && TARGET_HARD_FLOAT && ! no_rtl |
4cc833b7 | 2634 | && next_cum.fregno <= FP_ARG_V4_MAX_REG) |
4697a36c | 2635 | { |
4cc833b7 | 2636 | int fregno = next_cum.fregno; |
9ebbca7d | 2637 | rtx cr1 = gen_rtx_REG (CCmode, CR1_REGNO); |
4cc833b7 RH |
2638 | rtx lab = gen_label_rtx (); |
2639 | int off = (GP_ARG_NUM_REG * reg_size) + ((fregno - FP_ARG_MIN_REG) * 8); | |
4697a36c | 2640 | |
4cc833b7 | 2641 | emit_jump_insn (gen_rtx_SET (VOIDmode, |
4697a36c | 2642 | pc_rtx, |
39403d82 | 2643 | gen_rtx_IF_THEN_ELSE (VOIDmode, |
4cc833b7 RH |
2644 | gen_rtx_NE (VOIDmode, cr1, |
2645 | const0_rtx), | |
39403d82 | 2646 | gen_rtx_LABEL_REF (VOIDmode, lab), |
4697a36c MM |
2647 | pc_rtx))); |
2648 | ||
4cc833b7 RH |
2649 | while (fregno <= FP_ARG_V4_MAX_REG) |
2650 | { | |
dfafc897 | 2651 | mem = gen_rtx_MEM (DFmode, plus_constant (save_area, off)); |
ba4828e0 | 2652 | set_mem_alias_set (mem, set); |
dfafc897 | 2653 | emit_move_insn (mem, gen_rtx_REG (DFmode, fregno)); |
4cc833b7 RH |
2654 | fregno++; |
2655 | off += 8; | |
4697a36c | 2656 | } |
4cc833b7 RH |
2657 | |
2658 | emit_label (lab); | |
4697a36c | 2659 | } |
4697a36c | 2660 | } |
4697a36c | 2661 | |
dfafc897 | 2662 | /* Create the va_list data type. */ |
2c4974b7 | 2663 | |
dfafc897 FS |
2664 | tree |
2665 | rs6000_build_va_list () | |
2666 | { | |
bab45a51 | 2667 | tree f_gpr, f_fpr, f_ovf, f_sav, record, type_decl; |
4697a36c | 2668 | |
9ebbca7d GK |
2669 | /* For AIX, prefer 'char *' because that's what the system |
2670 | header files like. */ | |
f607bc57 | 2671 | if (DEFAULT_ABI != ABI_V4) |
9ebbca7d | 2672 | return build_pointer_type (char_type_node); |
dfafc897 | 2673 | |
0f4fd75d | 2674 | record = make_lang_type (RECORD_TYPE); |
bab45a51 | 2675 | type_decl = build_decl (TYPE_DECL, get_identifier ("__va_list_tag"), record); |
0f4fd75d | 2676 | |
9ebbca7d GK |
2677 | f_gpr = build_decl (FIELD_DECL, get_identifier ("gpr"), |
2678 | unsigned_char_type_node); | |
2679 | f_fpr = build_decl (FIELD_DECL, get_identifier ("fpr"), | |
2680 | unsigned_char_type_node); | |
dfafc897 FS |
2681 | f_ovf = build_decl (FIELD_DECL, get_identifier ("overflow_arg_area"), |
2682 | ptr_type_node); | |
2683 | f_sav = build_decl (FIELD_DECL, get_identifier ("reg_save_area"), | |
2684 | ptr_type_node); | |
2685 | ||
2686 | DECL_FIELD_CONTEXT (f_gpr) = record; | |
2687 | DECL_FIELD_CONTEXT (f_fpr) = record; | |
2688 | DECL_FIELD_CONTEXT (f_ovf) = record; | |
2689 | DECL_FIELD_CONTEXT (f_sav) = record; | |
2690 | ||
bab45a51 FS |
2691 | TREE_CHAIN (record) = type_decl; |
2692 | TYPE_NAME (record) = type_decl; | |
dfafc897 FS |
2693 | TYPE_FIELDS (record) = f_gpr; |
2694 | TREE_CHAIN (f_gpr) = f_fpr; | |
2695 | TREE_CHAIN (f_fpr) = f_ovf; | |
2696 | TREE_CHAIN (f_ovf) = f_sav; | |
2697 | ||
2698 | layout_type (record); | |
2699 | ||
2700 | /* The correct type is an array type of one element. */ | |
2701 | return build_array_type (record, build_index_type (size_zero_node)); | |
2702 | } | |
2703 | ||
2704 | /* Implement va_start. */ | |
2705 | ||
2706 | void | |
2707 | rs6000_va_start (stdarg_p, valist, nextarg) | |
2708 | int stdarg_p; | |
2709 | tree valist; | |
2710 | rtx nextarg; | |
4697a36c | 2711 | { |
dfafc897 FS |
2712 | HOST_WIDE_INT words, n_gpr, n_fpr; |
2713 | tree f_gpr, f_fpr, f_ovf, f_sav; | |
2714 | tree gpr, fpr, ovf, sav, t; | |
2c4974b7 | 2715 | |
dfafc897 | 2716 | /* Only SVR4 needs something special. */ |
f607bc57 | 2717 | if (DEFAULT_ABI != ABI_V4) |
dfafc897 FS |
2718 | { |
2719 | std_expand_builtin_va_start (stdarg_p, valist, nextarg); | |
2720 | return; | |
2721 | } | |
2722 | ||
973a648b | 2723 | f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node)); |
dfafc897 FS |
2724 | f_fpr = TREE_CHAIN (f_gpr); |
2725 | f_ovf = TREE_CHAIN (f_fpr); | |
2726 | f_sav = TREE_CHAIN (f_ovf); | |
2727 | ||
8ebecc3b | 2728 | valist = build1 (INDIRECT_REF, TREE_TYPE (TREE_TYPE (valist)), valist); |
dfafc897 FS |
2729 | gpr = build (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr); |
2730 | fpr = build (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr); | |
2731 | ovf = build (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf); | |
2732 | sav = build (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav); | |
2733 | ||
2734 | /* Count number of gp and fp argument registers used. */ | |
4cc833b7 | 2735 | words = current_function_args_info.words; |
dfafc897 FS |
2736 | n_gpr = current_function_args_info.sysv_gregno - GP_ARG_MIN_REG; |
2737 | n_fpr = current_function_args_info.fregno - FP_ARG_MIN_REG; | |
2738 | ||
2739 | if (TARGET_DEBUG_ARG) | |
78e1b90d DE |
2740 | { |
2741 | fputs ("va_start: words = ", stderr); | |
2742 | fprintf (stderr, HOST_WIDE_INT_PRINT_DEC, words); | |
2743 | fputs (", n_gpr = ", stderr); | |
2744 | fprintf (stderr, HOST_WIDE_INT_PRINT_DEC, n_gpr); | |
2745 | fputs (", n_fpr = ", stderr); | |
2746 | fprintf (stderr, HOST_WIDE_INT_PRINT_DEC, n_fpr); | |
2747 | putc ('\n', stderr); | |
2748 | } | |
dfafc897 FS |
2749 | |
2750 | t = build (MODIFY_EXPR, TREE_TYPE (gpr), gpr, build_int_2 (n_gpr, 0)); | |
2751 | TREE_SIDE_EFFECTS (t) = 1; | |
2752 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
2753 | ||
2754 | t = build (MODIFY_EXPR, TREE_TYPE (fpr), fpr, build_int_2 (n_fpr, 0)); | |
2755 | TREE_SIDE_EFFECTS (t) = 1; | |
2756 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
2757 | ||
2758 | /* Find the overflow area. */ | |
2759 | t = make_tree (TREE_TYPE (ovf), virtual_incoming_args_rtx); | |
2760 | if (words != 0) | |
2761 | t = build (PLUS_EXPR, TREE_TYPE (ovf), t, | |
2762 | build_int_2 (words * UNITS_PER_WORD, 0)); | |
2763 | t = build (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t); | |
2764 | TREE_SIDE_EFFECTS (t) = 1; | |
2765 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
2766 | ||
2767 | /* Find the register save area. */ | |
2768 | t = make_tree (TREE_TYPE (sav), virtual_stack_vars_rtx); | |
2769 | t = build (PLUS_EXPR, TREE_TYPE (sav), t, | |
2770 | build_int_2 (-RS6000_VARARGS_SIZE, -1)); | |
2771 | t = build (MODIFY_EXPR, TREE_TYPE (sav), sav, t); | |
2772 | TREE_SIDE_EFFECTS (t) = 1; | |
2773 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
2774 | } | |
2775 | ||
2776 | /* Implement va_arg. */ | |
2777 | ||
2778 | rtx | |
2779 | rs6000_va_arg (valist, type) | |
2780 | tree valist, type; | |
2781 | { | |
2782 | tree f_gpr, f_fpr, f_ovf, f_sav; | |
2783 | tree gpr, fpr, ovf, sav, reg, t, u; | |
2784 | int indirect_p, size, rsize, n_reg, sav_ofs, sav_scale; | |
2785 | rtx lab_false, lab_over, addr_rtx, r; | |
2786 | ||
9ebbca7d GK |
2787 | /* For AIX, the rule is that structures are passed left-aligned in |
2788 | their stack slot. However, GCC does not presently do this: | |
2789 | structures which are the same size as integer types are passed | |
2790 | right-aligned, as if they were in fact integers. This only | |
2791 | matters for structures of size 1 or 2, or 4 when TARGET_64BIT. */ | |
f607bc57 | 2792 | if (DEFAULT_ABI != ABI_V4) |
9ebbca7d GK |
2793 | { |
2794 | HOST_WIDE_INT align, rounded_size; | |
2795 | enum machine_mode mode; | |
2796 | tree addr_tree; | |
2797 | ||
2798 | /* Compute the rounded size of the type. */ | |
2799 | align = PARM_BOUNDARY / BITS_PER_UNIT; | |
2800 | rounded_size = (((int_size_in_bytes (type) + align - 1) / align) | |
2801 | * align); | |
2802 | ||
2803 | addr_tree = valist; | |
2804 | ||
2805 | mode = TYPE_MODE (type); | |
2806 | if (mode != BLKmode) | |
2807 | { | |
2808 | HOST_WIDE_INT adj; | |
2809 | adj = TREE_INT_CST_LOW (TYPE_SIZE (type)) / BITS_PER_UNIT; | |
2810 | if (rounded_size > align) | |
2811 | adj = rounded_size; | |
2812 | ||
2813 | addr_tree = build (PLUS_EXPR, TREE_TYPE (addr_tree), addr_tree, | |
2814 | build_int_2 (rounded_size - adj, 0)); | |
2815 | } | |
2816 | ||
2817 | addr_rtx = expand_expr (addr_tree, NULL_RTX, Pmode, EXPAND_NORMAL); | |
2818 | addr_rtx = copy_to_reg (addr_rtx); | |
2819 | ||
2820 | /* Compute new value for AP. */ | |
2821 | t = build (MODIFY_EXPR, TREE_TYPE (valist), valist, | |
2822 | build (PLUS_EXPR, TREE_TYPE (valist), valist, | |
2823 | build_int_2 (rounded_size, 0))); | |
2824 | TREE_SIDE_EFFECTS (t) = 1; | |
2825 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
2826 | ||
2827 | return addr_rtx; | |
2828 | } | |
dfafc897 | 2829 | |
973a648b | 2830 | f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node)); |
dfafc897 FS |
2831 | f_fpr = TREE_CHAIN (f_gpr); |
2832 | f_ovf = TREE_CHAIN (f_fpr); | |
2833 | f_sav = TREE_CHAIN (f_ovf); | |
2834 | ||
8ebecc3b | 2835 | valist = build1 (INDIRECT_REF, TREE_TYPE (TREE_TYPE (valist)), valist); |
dfafc897 FS |
2836 | gpr = build (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr); |
2837 | fpr = build (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr); | |
2838 | ovf = build (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf); | |
2839 | sav = build (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav); | |
2840 | ||
2841 | size = int_size_in_bytes (type); | |
2842 | rsize = (size + UNITS_PER_WORD - 1) / UNITS_PER_WORD; | |
4cc833b7 | 2843 | |
dfafc897 | 2844 | if (AGGREGATE_TYPE_P (type) || TYPE_MODE (type) == TFmode) |
4cc833b7 | 2845 | { |
dfafc897 FS |
2846 | /* Aggregates and long doubles are passed by reference. */ |
2847 | indirect_p = 1; | |
2848 | reg = gpr; | |
2849 | n_reg = 1; | |
2850 | sav_ofs = 0; | |
2851 | sav_scale = 4; | |
2852 | size = rsize = UNITS_PER_WORD; | |
2853 | } | |
2854 | else if (FLOAT_TYPE_P (type) && ! TARGET_SOFT_FLOAT) | |
2855 | { | |
2856 | /* FP args go in FP registers, if present. */ | |
2857 | indirect_p = 0; | |
2858 | reg = fpr; | |
2859 | n_reg = 1; | |
2860 | sav_ofs = 8*4; | |
2861 | sav_scale = 8; | |
4cc833b7 | 2862 | } |
dfafc897 FS |
2863 | else |
2864 | { | |
2865 | /* Otherwise into GP registers. */ | |
2866 | indirect_p = 0; | |
2867 | reg = gpr; | |
2868 | n_reg = rsize; | |
2869 | sav_ofs = 0; | |
2870 | sav_scale = 4; | |
2871 | } | |
2872 | ||
a4f6c312 | 2873 | /* Pull the value out of the saved registers ... */ |
dfafc897 FS |
2874 | |
2875 | lab_false = gen_label_rtx (); | |
2876 | lab_over = gen_label_rtx (); | |
2877 | addr_rtx = gen_reg_rtx (Pmode); | |
2878 | ||
2879 | emit_cmp_and_jump_insns (expand_expr (reg, NULL_RTX, QImode, EXPAND_NORMAL), | |
a06ef755 RK |
2880 | GEN_INT (8 - n_reg + 1), GE, const1_rtx, QImode, 1, |
2881 | lab_false); | |
2c4974b7 | 2882 | |
dfafc897 FS |
2883 | /* Long long is aligned in the registers. */ |
2884 | if (n_reg > 1) | |
2c4974b7 | 2885 | { |
dfafc897 FS |
2886 | u = build (BIT_AND_EXPR, TREE_TYPE (reg), reg, |
2887 | build_int_2 (n_reg - 1, 0)); | |
2888 | u = build (PLUS_EXPR, TREE_TYPE (reg), reg, u); | |
2889 | u = build (MODIFY_EXPR, TREE_TYPE (reg), reg, u); | |
2890 | TREE_SIDE_EFFECTS (u) = 1; | |
2891 | expand_expr (u, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
2c4974b7 | 2892 | } |
dfafc897 FS |
2893 | |
2894 | if (sav_ofs) | |
2895 | t = build (PLUS_EXPR, ptr_type_node, sav, build_int_2 (sav_ofs, 0)); | |
2c4974b7 | 2896 | else |
dfafc897 | 2897 | t = sav; |
2c4974b7 | 2898 | |
dfafc897 FS |
2899 | u = build (POSTINCREMENT_EXPR, TREE_TYPE (reg), reg, build_int_2 (n_reg, 0)); |
2900 | TREE_SIDE_EFFECTS (u) = 1; | |
2c4974b7 | 2901 | |
dfafc897 FS |
2902 | u = build1 (CONVERT_EXPR, integer_type_node, u); |
2903 | TREE_SIDE_EFFECTS (u) = 1; | |
2c4974b7 | 2904 | |
dfafc897 FS |
2905 | u = build (MULT_EXPR, integer_type_node, u, build_int_2 (sav_scale, 0)); |
2906 | TREE_SIDE_EFFECTS (u) = 1; | |
2907 | ||
2908 | t = build (PLUS_EXPR, ptr_type_node, t, u); | |
2909 | TREE_SIDE_EFFECTS (t) = 1; | |
2910 | ||
2911 | r = expand_expr (t, addr_rtx, Pmode, EXPAND_NORMAL); | |
2912 | if (r != addr_rtx) | |
2913 | emit_move_insn (addr_rtx, r); | |
2914 | ||
2915 | emit_jump_insn (gen_jump (lab_over)); | |
2916 | emit_barrier (); | |
2917 | emit_label (lab_false); | |
2918 | ||
a4f6c312 | 2919 | /* ... otherwise out of the overflow area. */ |
dfafc897 FS |
2920 | |
2921 | /* Make sure we don't find reg 7 for the next int arg. */ | |
2922 | if (n_reg > 1) | |
2923 | { | |
2924 | t = build (MODIFY_EXPR, TREE_TYPE (reg), reg, build_int_2 (8, 0)); | |
2925 | TREE_SIDE_EFFECTS (t) = 1; | |
2926 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
2927 | } | |
2928 | ||
2929 | /* Care for on-stack alignment if needed. */ | |
2930 | if (rsize <= 1) | |
2931 | t = ovf; | |
2932 | else | |
2933 | { | |
2934 | t = build (PLUS_EXPR, TREE_TYPE (ovf), ovf, build_int_2 (7, 0)); | |
2935 | t = build (BIT_AND_EXPR, TREE_TYPE (t), t, build_int_2 (-8, -1)); | |
2936 | } | |
2937 | t = save_expr (t); | |
2938 | ||
2939 | r = expand_expr (t, addr_rtx, Pmode, EXPAND_NORMAL); | |
2940 | if (r != addr_rtx) | |
2941 | emit_move_insn (addr_rtx, r); | |
2942 | ||
2943 | t = build (PLUS_EXPR, TREE_TYPE (t), t, build_int_2 (size, 0)); | |
2944 | t = build (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t); | |
2945 | TREE_SIDE_EFFECTS (t) = 1; | |
2946 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
2947 | ||
2948 | emit_label (lab_over); | |
2949 | ||
2950 | if (indirect_p) | |
2951 | { | |
2952 | r = gen_rtx_MEM (Pmode, addr_rtx); | |
ba4828e0 | 2953 | set_mem_alias_set (r, get_varargs_alias_set ()); |
dfafc897 FS |
2954 | emit_move_insn (addr_rtx, r); |
2955 | } | |
2956 | ||
2957 | return addr_rtx; | |
4697a36c | 2958 | } |
0ac081f6 AH |
2959 | |
2960 | /* Builtins. */ | |
2961 | ||
2962 | #define def_builtin(MASK, NAME, TYPE, CODE) \ | |
2963 | do { \ | |
2964 | if ((MASK) & target_flags) \ | |
2965 | builtin_function ((NAME), (TYPE), (CODE), BUILT_IN_MD, NULL); \ | |
2966 | } while (0) | |
2967 | ||
2968 | struct builtin_description | |
2969 | { | |
2970 | const unsigned int mask; | |
2971 | const enum insn_code icode; | |
2972 | const char *const name; | |
2973 | const enum rs6000_builtins code; | |
2974 | }; | |
2975 | ||
2976 | /* Simple binary operatiors: VECc = foo (VECa, VECb). */ | |
2977 | static const struct builtin_description bdesc_2arg[] = | |
2978 | { | |
f18c054f DB |
2979 | { MASK_ALTIVEC, CODE_FOR_addv16qi3, "__builtin_altivec_vaddubm", ALTIVEC_BUILTIN_VADDUBM }, |
2980 | { MASK_ALTIVEC, CODE_FOR_addv8hi3, "__builtin_altivec_vadduhm", ALTIVEC_BUILTIN_VADDUHM }, | |
2981 | { MASK_ALTIVEC, CODE_FOR_addv4si3, "__builtin_altivec_vadduwm", ALTIVEC_BUILTIN_VADDUWM }, | |
2982 | { MASK_ALTIVEC, CODE_FOR_addv4sf3, "__builtin_altivec_vaddfp", ALTIVEC_BUILTIN_VADDFP }, | |
0ac081f6 AH |
2983 | { MASK_ALTIVEC, CODE_FOR_altivec_vaddcuw, "__builtin_altivec_vaddcuw", ALTIVEC_BUILTIN_VADDCUW }, |
2984 | { MASK_ALTIVEC, CODE_FOR_altivec_vaddubs, "__builtin_altivec_vaddubs", ALTIVEC_BUILTIN_VADDUBS }, | |
2985 | { MASK_ALTIVEC, CODE_FOR_altivec_vaddsbs, "__builtin_altivec_vaddsbs", ALTIVEC_BUILTIN_VADDSBS }, | |
2986 | { MASK_ALTIVEC, CODE_FOR_altivec_vadduhs, "__builtin_altivec_vadduhs", ALTIVEC_BUILTIN_VADDUHS }, | |
2987 | { MASK_ALTIVEC, CODE_FOR_altivec_vaddshs, "__builtin_altivec_vaddshs", ALTIVEC_BUILTIN_VADDSHS }, | |
2988 | { MASK_ALTIVEC, CODE_FOR_altivec_vadduws, "__builtin_altivec_vadduws", ALTIVEC_BUILTIN_VADDUWS }, | |
2989 | { MASK_ALTIVEC, CODE_FOR_altivec_vaddsws, "__builtin_altivec_vaddsws", ALTIVEC_BUILTIN_VADDSWS }, | |
f18c054f | 2990 | { MASK_ALTIVEC, CODE_FOR_andv4si3, "__builtin_altivec_vand", ALTIVEC_BUILTIN_VAND }, |
0ac081f6 AH |
2991 | { MASK_ALTIVEC, CODE_FOR_altivec_vandc, "__builtin_altivec_vandc", ALTIVEC_BUILTIN_VANDC }, |
2992 | { MASK_ALTIVEC, CODE_FOR_altivec_vavgub, "__builtin_altivec_vavgub", ALTIVEC_BUILTIN_VAVGUB }, | |
2993 | { MASK_ALTIVEC, CODE_FOR_altivec_vavgsb, "__builtin_altivec_vavgsb", ALTIVEC_BUILTIN_VAVGSB }, | |
2994 | { MASK_ALTIVEC, CODE_FOR_altivec_vavguh, "__builtin_altivec_vavguh", ALTIVEC_BUILTIN_VAVGUH }, | |
2995 | { MASK_ALTIVEC, CODE_FOR_altivec_vavgsh, "__builtin_altivec_vavgsh", ALTIVEC_BUILTIN_VAVGSH }, | |
2996 | { MASK_ALTIVEC, CODE_FOR_altivec_vavguw, "__builtin_altivec_vavguw", ALTIVEC_BUILTIN_VAVGUW }, | |
2997 | { MASK_ALTIVEC, CODE_FOR_altivec_vavgsw, "__builtin_altivec_vavgsw", ALTIVEC_BUILTIN_VAVGSW }, | |
2998 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpbfp, "__builtin_altivec_vcmpbfp", ALTIVEC_BUILTIN_VCMPBFP }, | |
2999 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequb, "__builtin_altivec_vcmpequb", ALTIVEC_BUILTIN_VCMPEQUB }, | |
3000 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequh, "__builtin_altivec_vcmpequh", ALTIVEC_BUILTIN_VCMPEQUH }, | |
3001 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequw, "__builtin_altivec_vcmpequw", ALTIVEC_BUILTIN_VCMPEQUW }, | |
3002 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpeqfp, "__builtin_altivec_vcmpeqfp", ALTIVEC_BUILTIN_VCMPEQFP }, | |
3003 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgefp, "__builtin_altivec_vcmpgefp", ALTIVEC_BUILTIN_VCMPGEFP }, | |
3004 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtub, "__builtin_altivec_vcmpgtub", ALTIVEC_BUILTIN_VCMPGTUB }, | |
3005 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsb, "__builtin_altivec_vcmpgtsb", ALTIVEC_BUILTIN_VCMPGTSB }, | |
3006 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtuh, "__builtin_altivec_vcmpgtuh", ALTIVEC_BUILTIN_VCMPGTUH }, | |
3007 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsh, "__builtin_altivec_vcmpgtsh", ALTIVEC_BUILTIN_VCMPGTSH }, | |
3008 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtuw, "__builtin_altivec_vcmpgtuw", ALTIVEC_BUILTIN_VCMPGTUW }, | |
3009 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsw, "__builtin_altivec_vcmpgtsw", ALTIVEC_BUILTIN_VCMPGTSW }, | |
3010 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtfp, "__builtin_altivec_vcmpgtfp", ALTIVEC_BUILTIN_VCMPGTFP }, | |
f18c054f DB |
3011 | { MASK_ALTIVEC, CODE_FOR_umaxv16qi3, "__builtin_altivec_vmaxub", ALTIVEC_BUILTIN_VMAXUB }, |
3012 | { MASK_ALTIVEC, CODE_FOR_smaxv16qi3, "__builtin_altivec_vmaxsb", ALTIVEC_BUILTIN_VMAXSB }, | |
3013 | { MASK_ALTIVEC, CODE_FOR_uminv8hi3, "__builtin_altivec_vmaxuh", ALTIVEC_BUILTIN_VMAXUH }, | |
3014 | { MASK_ALTIVEC, CODE_FOR_sminv8hi3, "__builtin_altivec_vmaxsh", ALTIVEC_BUILTIN_VMAXSH }, | |
3015 | { MASK_ALTIVEC, CODE_FOR_uminv4si3, "__builtin_altivec_vmaxuw", ALTIVEC_BUILTIN_VMAXUW }, | |
3016 | { MASK_ALTIVEC, CODE_FOR_sminv4si3, "__builtin_altivec_vmaxsw", ALTIVEC_BUILTIN_VMAXSW }, | |
3017 | { MASK_ALTIVEC, CODE_FOR_sminv4sf3, "__builtin_altivec_vmaxfp", ALTIVEC_BUILTIN_VMAXFP }, | |
0ac081f6 AH |
3018 | { MASK_ALTIVEC, CODE_FOR_altivec_vmrghb, "__builtin_altivec_vmrghb", ALTIVEC_BUILTIN_VMRGHB }, |
3019 | { MASK_ALTIVEC, CODE_FOR_altivec_vmrghh, "__builtin_altivec_vmrghh", ALTIVEC_BUILTIN_VMRGHH }, | |
3020 | { MASK_ALTIVEC, CODE_FOR_altivec_vmrghw, "__builtin_altivec_vmrghw", ALTIVEC_BUILTIN_VMRGHW }, | |
3021 | { MASK_ALTIVEC, CODE_FOR_altivec_vmrglb, "__builtin_altivec_vmrglb", ALTIVEC_BUILTIN_VMRGLB }, | |
3022 | { MASK_ALTIVEC, CODE_FOR_altivec_vmrglh, "__builtin_altivec_vmrglh", ALTIVEC_BUILTIN_VMRGLH }, | |
3023 | { MASK_ALTIVEC, CODE_FOR_altivec_vmrglw, "__builtin_altivec_vmrglw", ALTIVEC_BUILTIN_VMRGLW }, | |
f18c054f DB |
3024 | { MASK_ALTIVEC, CODE_FOR_uminv16qi3, "__builtin_altivec_vminub", ALTIVEC_BUILTIN_VMINUB }, |
3025 | { MASK_ALTIVEC, CODE_FOR_sminv16qi3, "__builtin_altivec_vminsb", ALTIVEC_BUILTIN_VMINSB }, | |
3026 | { MASK_ALTIVEC, CODE_FOR_uminv8hi3, "__builtin_altivec_vminuh", ALTIVEC_BUILTIN_VMINUH }, | |
3027 | { MASK_ALTIVEC, CODE_FOR_sminv8hi3, "__builtin_altivec_vminsh", ALTIVEC_BUILTIN_VMINSH }, | |
3028 | { MASK_ALTIVEC, CODE_FOR_uminv4si3, "__builtin_altivec_vminuw", ALTIVEC_BUILTIN_VMINUW }, | |
3029 | { MASK_ALTIVEC, CODE_FOR_sminv4si3, "__builtin_altivec_vminsw", ALTIVEC_BUILTIN_VMINSW }, | |
3030 | { MASK_ALTIVEC, CODE_FOR_sminv4sf3, "__builtin_altivec_vminfp", ALTIVEC_BUILTIN_VMINFP }, | |
0ac081f6 AH |
3031 | { MASK_ALTIVEC, CODE_FOR_altivec_vmuleub, "__builtin_altivec_vmuleub", ALTIVEC_BUILTIN_VMULEUB }, |
3032 | { MASK_ALTIVEC, CODE_FOR_altivec_vmulesb, "__builtin_altivec_vmulesb", ALTIVEC_BUILTIN_VMULESB }, | |
3033 | { MASK_ALTIVEC, CODE_FOR_altivec_vmuleuh, "__builtin_altivec_vmuleuh", ALTIVEC_BUILTIN_VMULEUH }, | |
3034 | { MASK_ALTIVEC, CODE_FOR_altivec_vmulesh, "__builtin_altivec_vmulesh", ALTIVEC_BUILTIN_VMULESH }, | |
3035 | { MASK_ALTIVEC, CODE_FOR_altivec_vmuloub, "__builtin_altivec_vmuloub", ALTIVEC_BUILTIN_VMULOUB }, | |
3036 | { MASK_ALTIVEC, CODE_FOR_altivec_vmulosb, "__builtin_altivec_vmulosb", ALTIVEC_BUILTIN_VMULOSB }, | |
3037 | { MASK_ALTIVEC, CODE_FOR_altivec_vmulouh, "__builtin_altivec_vmulouh", ALTIVEC_BUILTIN_VMULOUH }, | |
3038 | { MASK_ALTIVEC, CODE_FOR_altivec_vmulosh, "__builtin_altivec_vmulosh", ALTIVEC_BUILTIN_VMULOSH }, | |
3039 | { MASK_ALTIVEC, CODE_FOR_altivec_vnor, "__builtin_altivec_vnor", ALTIVEC_BUILTIN_VNOR }, | |
f18c054f | 3040 | { MASK_ALTIVEC, CODE_FOR_iorv4si3, "__builtin_altivec_vor", ALTIVEC_BUILTIN_VOR }, |
0ac081f6 AH |
3041 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhum, "__builtin_altivec_vpkuhum", ALTIVEC_BUILTIN_VPKUHUM }, |
3042 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwum, "__builtin_altivec_vpkuwum", ALTIVEC_BUILTIN_VPKUWUM }, | |
3043 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkpx, "__builtin_altivec_vpkpx", ALTIVEC_BUILTIN_VPKPX }, | |
3044 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhss, "__builtin_altivec_vpkuhss", ALTIVEC_BUILTIN_VPKUHSS }, | |
3045 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkshss, "__builtin_altivec_vpkshss", ALTIVEC_BUILTIN_VPKSHSS }, | |
3046 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwss, "__builtin_altivec_vpkuwss", ALTIVEC_BUILTIN_VPKUWSS }, | |
3047 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkswss, "__builtin_altivec_vpkswss", ALTIVEC_BUILTIN_VPKSWSS }, | |
3048 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhus, "__builtin_altivec_vpkuhus", ALTIVEC_BUILTIN_VPKUHUS }, | |
3049 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkshus, "__builtin_altivec_vpkshus", ALTIVEC_BUILTIN_VPKSHUS }, | |
3050 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwus, "__builtin_altivec_vpkuwus", ALTIVEC_BUILTIN_VPKUWUS }, | |
3051 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkswus, "__builtin_altivec_vpkswus", ALTIVEC_BUILTIN_VPKSWUS }, | |
3052 | { MASK_ALTIVEC, CODE_FOR_altivec_vrlb, "__builtin_altivec_vrlb", ALTIVEC_BUILTIN_VRLB }, | |
3053 | { MASK_ALTIVEC, CODE_FOR_altivec_vrlh, "__builtin_altivec_vrlh", ALTIVEC_BUILTIN_VRLH }, | |
3054 | { MASK_ALTIVEC, CODE_FOR_altivec_vrlw, "__builtin_altivec_vrlw", ALTIVEC_BUILTIN_VRLW }, | |
3055 | { MASK_ALTIVEC, CODE_FOR_altivec_vslb, "__builtin_altivec_vslb", ALTIVEC_BUILTIN_VSLB }, | |
3056 | { MASK_ALTIVEC, CODE_FOR_altivec_vslh, "__builtin_altivec_vslh", ALTIVEC_BUILTIN_VSLH }, | |
3057 | { MASK_ALTIVEC, CODE_FOR_altivec_vslw, "__builtin_altivec_vslw", ALTIVEC_BUILTIN_VSLW }, | |
3058 | { MASK_ALTIVEC, CODE_FOR_altivec_vsl, "__builtin_altivec_vsl", ALTIVEC_BUILTIN_VSL }, | |
3059 | { MASK_ALTIVEC, CODE_FOR_altivec_vslo, "__builtin_altivec_vslo", ALTIVEC_BUILTIN_VSLO }, | |
3060 | { MASK_ALTIVEC, CODE_FOR_altivec_vsrb, "__builtin_altivec_vsrb", ALTIVEC_BUILTIN_VSRB }, | |
f18c054f DB |
3061 | { MASK_ALTIVEC, CODE_FOR_altivec_vsrh, "__builtin_altivec_vsrh", ALTIVEC_BUILTIN_VSRH }, |
3062 | { MASK_ALTIVEC, CODE_FOR_altivec_vsrw, "__builtin_altivec_vsrw", ALTIVEC_BUILTIN_VSRW }, | |
0ac081f6 AH |
3063 | { MASK_ALTIVEC, CODE_FOR_altivec_vsrab, "__builtin_altivec_vsrab", ALTIVEC_BUILTIN_VSRAB }, |
3064 | { MASK_ALTIVEC, CODE_FOR_altivec_vsrah, "__builtin_altivec_vsrah", ALTIVEC_BUILTIN_VSRAH }, | |
3065 | { MASK_ALTIVEC, CODE_FOR_altivec_vsraw, "__builtin_altivec_vsraw", ALTIVEC_BUILTIN_VSRAW }, | |
3066 | { MASK_ALTIVEC, CODE_FOR_altivec_vsr, "__builtin_altivec_vsr", ALTIVEC_BUILTIN_VSR }, | |
3067 | { MASK_ALTIVEC, CODE_FOR_altivec_vsro, "__builtin_altivec_vsro", ALTIVEC_BUILTIN_VSRO }, | |
f18c054f DB |
3068 | { MASK_ALTIVEC, CODE_FOR_subv16qi3, "__builtin_altivec_vsububm", ALTIVEC_BUILTIN_VSUBUBM }, |
3069 | { MASK_ALTIVEC, CODE_FOR_subv8hi3, "__builtin_altivec_vsubuhm", ALTIVEC_BUILTIN_VSUBUHM }, | |
3070 | { MASK_ALTIVEC, CODE_FOR_subv4si3, "__builtin_altivec_vsubuwm", ALTIVEC_BUILTIN_VSUBUWM }, | |
3071 | { MASK_ALTIVEC, CODE_FOR_subv4sf3, "__builtin_altivec_vsubfp", ALTIVEC_BUILTIN_VSUBFP }, | |
0ac081f6 AH |
3072 | { MASK_ALTIVEC, CODE_FOR_altivec_vsubcuw, "__builtin_altivec_vsubcuw", ALTIVEC_BUILTIN_VSUBCUW }, |
3073 | { MASK_ALTIVEC, CODE_FOR_altivec_vsububs, "__builtin_altivec_vsububs", ALTIVEC_BUILTIN_VSUBUBS }, | |
3074 | { MASK_ALTIVEC, CODE_FOR_altivec_vsubsbs, "__builtin_altivec_vsubsbs", ALTIVEC_BUILTIN_VSUBSBS }, | |
3075 | { MASK_ALTIVEC, CODE_FOR_altivec_vsubuhs, "__builtin_altivec_vsubuhs", ALTIVEC_BUILTIN_VSUBUHS }, | |
3076 | { MASK_ALTIVEC, CODE_FOR_altivec_vsubshs, "__builtin_altivec_vsubshs", ALTIVEC_BUILTIN_VSUBSHS }, | |
3077 | { MASK_ALTIVEC, CODE_FOR_altivec_vsubuws, "__builtin_altivec_vsubuws", ALTIVEC_BUILTIN_VSUBUWS }, | |
3078 | { MASK_ALTIVEC, CODE_FOR_altivec_vsubsws, "__builtin_altivec_vsubsws", ALTIVEC_BUILTIN_VSUBSWS }, | |
3079 | { MASK_ALTIVEC, CODE_FOR_altivec_vsum4ubs, "__builtin_altivec_vsum4ubs", ALTIVEC_BUILTIN_VSUM4UBS }, | |
3080 | { MASK_ALTIVEC, CODE_FOR_altivec_vsum4sbs, "__builtin_altivec_vsum4sbs", ALTIVEC_BUILTIN_VSUM4SBS }, | |
3081 | { MASK_ALTIVEC, CODE_FOR_altivec_vsum4shs, "__builtin_altivec_vsum4shs", ALTIVEC_BUILTIN_VSUM4SHS }, | |
3082 | { MASK_ALTIVEC, CODE_FOR_altivec_vsum2sws, "__builtin_altivec_vsum2sws", ALTIVEC_BUILTIN_VSUM2SWS }, | |
3083 | { MASK_ALTIVEC, CODE_FOR_altivec_vsumsws, "__builtin_altivec_vsumsws", ALTIVEC_BUILTIN_VSUMSWS }, | |
f18c054f | 3084 | { MASK_ALTIVEC, CODE_FOR_xorv4si3, "__builtin_altivec_vxor", ALTIVEC_BUILTIN_VXOR }, |
0ac081f6 AH |
3085 | }; |
3086 | ||
3087 | static rtx | |
3088 | altivec_expand_binop_builtin (icode, arglist, target) | |
3089 | enum insn_code icode; | |
3090 | tree arglist; | |
3091 | rtx target; | |
3092 | { | |
3093 | rtx pat; | |
3094 | tree arg0 = TREE_VALUE (arglist); | |
3095 | tree arg1 = TREE_VALUE (TREE_CHAIN (arglist)); | |
3096 | rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
3097 | rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); | |
3098 | enum machine_mode tmode = insn_data[icode].operand[0].mode; | |
3099 | enum machine_mode mode0 = insn_data[icode].operand[1].mode; | |
3100 | enum machine_mode mode1 = insn_data[icode].operand[2].mode; | |
3101 | ||
3102 | if (! target | |
3103 | || GET_MODE (target) != tmode | |
3104 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
3105 | target = gen_reg_rtx (tmode); | |
3106 | ||
3107 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) | |
3108 | op0 = copy_to_mode_reg (mode0, op0); | |
3109 | if (! (*insn_data[icode].operand[2].predicate) (op1, mode1)) | |
3110 | op1 = copy_to_mode_reg (mode1, op1); | |
3111 | ||
3112 | pat = GEN_FCN (icode) (target, op0, op1); | |
3113 | if (! pat) | |
3114 | return 0; | |
3115 | emit_insn (pat); | |
3116 | ||
3117 | return target; | |
3118 | } | |
3119 | ||
3120 | static rtx | |
00b960c7 | 3121 | altivec_expand_builtin (exp, target) |
0ac081f6 AH |
3122 | tree exp; |
3123 | rtx target; | |
0ac081f6 AH |
3124 | { |
3125 | struct builtin_description *d; | |
3126 | size_t i; | |
3127 | enum insn_code icode; | |
3128 | tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0); | |
3129 | tree arglist = TREE_OPERAND (exp, 1); | |
00b960c7 AH |
3130 | tree arg0, arg1; |
3131 | rtx op0, op1, pat; | |
3132 | enum machine_mode tmode, mode0, mode1; | |
0ac081f6 AH |
3133 | unsigned int fcode = DECL_FUNCTION_CODE (fndecl); |
3134 | ||
3135 | switch (fcode) | |
3136 | { | |
f18c054f DB |
3137 | case ALTIVEC_BUILTIN_LD_INTERNAL_16qi: |
3138 | icode = CODE_FOR_altivec_lvx_16qi; | |
0ac081f6 AH |
3139 | arg0 = TREE_VALUE (arglist); |
3140 | op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
3141 | tmode = insn_data[icode].operand[0].mode; | |
3142 | mode0 = insn_data[icode].operand[1].mode; | |
3143 | ||
3144 | if (! target | |
3145 | || GET_MODE (target) != tmode | |
3146 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
3147 | target = gen_reg_rtx (tmode); | |
3148 | ||
3149 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) | |
3150 | op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0)); | |
3151 | ||
3152 | pat = GEN_FCN (icode) (target, op0); | |
3153 | if (! pat) | |
3154 | return 0; | |
3155 | emit_insn (pat); | |
3156 | return target; | |
f18c054f DB |
3157 | case ALTIVEC_BUILTIN_LD_INTERNAL_8hi: |
3158 | icode = CODE_FOR_altivec_lvx_8hi; | |
3159 | arg0 = TREE_VALUE (arglist); | |
3160 | op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
3161 | tmode = insn_data[icode].operand[0].mode; | |
3162 | mode0 = insn_data[icode].operand[1].mode; | |
0ac081f6 | 3163 | |
f18c054f DB |
3164 | if (! target |
3165 | || GET_MODE (target) != tmode | |
3166 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
3167 | target = gen_reg_rtx (tmode); | |
3168 | ||
3169 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) | |
3170 | op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0)); | |
3171 | ||
3172 | pat = GEN_FCN (icode) (target, op0); | |
3173 | if (! pat) | |
3174 | return 0; | |
3175 | emit_insn (pat); | |
3176 | return target; | |
3177 | case ALTIVEC_BUILTIN_LD_INTERNAL_4si: | |
3178 | icode = CODE_FOR_altivec_lvx_4si; | |
3179 | arg0 = TREE_VALUE (arglist); | |
3180 | op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
3181 | tmode = insn_data[icode].operand[0].mode; | |
3182 | mode0 = insn_data[icode].operand[1].mode; | |
3183 | ||
3184 | if (! target | |
3185 | || GET_MODE (target) != tmode | |
3186 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
3187 | target = gen_reg_rtx (tmode); | |
3188 | ||
3189 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) | |
3190 | op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0)); | |
3191 | ||
3192 | pat = GEN_FCN (icode) (target, op0); | |
3193 | if (! pat) | |
3194 | return 0; | |
3195 | emit_insn (pat); | |
3196 | return target; | |
3197 | case ALTIVEC_BUILTIN_LD_INTERNAL_4sf: | |
3198 | icode = CODE_FOR_altivec_lvx_4sf; | |
3199 | arg0 = TREE_VALUE (arglist); | |
3200 | op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
3201 | tmode = insn_data[icode].operand[0].mode; | |
3202 | mode0 = insn_data[icode].operand[1].mode; | |
3203 | ||
3204 | if (! target | |
3205 | || GET_MODE (target) != tmode | |
3206 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
3207 | target = gen_reg_rtx (tmode); | |
3208 | ||
3209 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) | |
3210 | op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0)); | |
3211 | ||
3212 | pat = GEN_FCN (icode) (target, op0); | |
3213 | if (! pat) | |
3214 | return 0; | |
3215 | emit_insn (pat); | |
3216 | return target; | |
3217 | ||
3218 | case ALTIVEC_BUILTIN_ST_INTERNAL_16qi: | |
3219 | icode = CODE_FOR_altivec_stvx_16qi; | |
3220 | arg0 = TREE_VALUE (arglist); | |
3221 | arg1 = TREE_VALUE (TREE_CHAIN (arglist)); | |
3222 | op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
3223 | op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); | |
3224 | mode0 = insn_data[icode].operand[0].mode; | |
3225 | mode1 = insn_data[icode].operand[1].mode; | |
3226 | ||
3227 | if (! (*insn_data[icode].operand[0].predicate) (op0, mode0)) | |
3228 | op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0)); | |
3229 | if (! (*insn_data[icode].operand[1].predicate) (op1, mode1)) | |
3230 | op1 = copy_to_mode_reg (mode1, op1); | |
3231 | ||
3232 | pat = GEN_FCN (icode) (op0, op1); | |
3233 | if (! pat) | |
3234 | return 0; | |
3235 | emit_insn (pat); | |
3236 | return NULL_RTX; | |
3237 | case ALTIVEC_BUILTIN_ST_INTERNAL_8hi: | |
3238 | icode = CODE_FOR_altivec_stvx_8hi; | |
3239 | arg0 = TREE_VALUE (arglist); | |
3240 | arg1 = TREE_VALUE (TREE_CHAIN (arglist)); | |
3241 | op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
3242 | op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); | |
3243 | mode0 = insn_data[icode].operand[0].mode; | |
3244 | mode1 = insn_data[icode].operand[1].mode; | |
3245 | ||
3246 | if (! (*insn_data[icode].operand[0].predicate) (op0, mode0)) | |
3247 | op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0)); | |
3248 | if (! (*insn_data[icode].operand[1].predicate) (op1, mode1)) | |
3249 | op1 = copy_to_mode_reg (mode1, op1); | |
3250 | ||
3251 | pat = GEN_FCN (icode) (op0, op1); | |
3252 | if (! pat) | |
3253 | return 0; | |
3254 | emit_insn (pat); | |
3255 | return NULL_RTX; | |
3256 | case ALTIVEC_BUILTIN_ST_INTERNAL_4si: | |
3257 | icode = CODE_FOR_altivec_stvx_4si; | |
3258 | arg0 = TREE_VALUE (arglist); | |
3259 | arg1 = TREE_VALUE (TREE_CHAIN (arglist)); | |
3260 | op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
3261 | op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); | |
3262 | mode0 = insn_data[icode].operand[0].mode; | |
3263 | mode1 = insn_data[icode].operand[1].mode; | |
3264 | ||
3265 | if (! (*insn_data[icode].operand[0].predicate) (op0, mode0)) | |
3266 | op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0)); | |
3267 | if (! (*insn_data[icode].operand[1].predicate) (op1, mode1)) | |
3268 | op1 = copy_to_mode_reg (mode1, op1); | |
3269 | ||
3270 | pat = GEN_FCN (icode) (op0, op1); | |
3271 | if (! pat) | |
3272 | return 0; | |
3273 | emit_insn (pat); | |
3274 | return NULL_RTX; | |
3275 | case ALTIVEC_BUILTIN_ST_INTERNAL_4sf: | |
3276 | icode = CODE_FOR_altivec_stvx_4sf; | |
0ac081f6 AH |
3277 | arg0 = TREE_VALUE (arglist); |
3278 | arg1 = TREE_VALUE (TREE_CHAIN (arglist)); | |
3279 | op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
3280 | op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); | |
3281 | mode0 = insn_data[icode].operand[0].mode; | |
3282 | mode1 = insn_data[icode].operand[1].mode; | |
3283 | ||
3284 | if (! (*insn_data[icode].operand[0].predicate) (op0, mode0)) | |
3285 | op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0)); | |
3286 | if (! (*insn_data[icode].operand[1].predicate) (op1, mode1)) | |
3287 | op1 = copy_to_mode_reg (mode1, op1); | |
3288 | ||
3289 | pat = GEN_FCN (icode) (op0, op1); | |
3290 | if (! pat) | |
3291 | return 0; | |
3292 | emit_insn (pat); | |
3293 | return NULL_RTX; | |
3294 | } | |
3295 | ||
3296 | /* Handle simple binary operations. */ | |
00b960c7 AH |
3297 | d = (struct builtin_description *) bdesc_2arg; |
3298 | for (i = 0; i < sizeof (bdesc_2arg) / sizeof *d; i++, d++) | |
0ac081f6 AH |
3299 | if (d->code == fcode) |
3300 | return altivec_expand_binop_builtin (d->icode, arglist, target); | |
3301 | ||
3302 | abort (); | |
3303 | return NULL_RTX; | |
3304 | } | |
3305 | ||
3306 | /* Expand an expression EXP that calls a built-in function, | |
3307 | with result going to TARGET if that's convenient | |
3308 | (and in mode MODE if that's convenient). | |
3309 | SUBTARGET may be used as the target for computing one of EXP's operands. | |
3310 | IGNORE is nonzero if the value is to be ignored. */ | |
3311 | ||
3312 | static rtx | |
3313 | rs6000_expand_builtin (exp, target, subtarget, mode, ignore) | |
3314 | tree exp; | |
3315 | rtx target; | |
00b960c7 AH |
3316 | rtx subtarget ATTRIBUTE_UNUSED; |
3317 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
3318 | int ignore ATTRIBUTE_UNUSED; | |
0ac081f6 AH |
3319 | { |
3320 | if (TARGET_ALTIVEC) | |
00b960c7 | 3321 | return altivec_expand_builtin (exp, target); |
0ac081f6 AH |
3322 | |
3323 | abort (); | |
3324 | } | |
3325 | ||
3326 | static void | |
3327 | rs6000_init_builtins (list_node) | |
3328 | tree list_node ATTRIBUTE_UNUSED; | |
3329 | { | |
3330 | if (TARGET_ALTIVEC) | |
3331 | altivec_init_builtins (); | |
3332 | } | |
3333 | ||
3334 | static void | |
3335 | altivec_init_builtins (void) | |
3336 | { | |
3337 | struct builtin_description * d; | |
3338 | size_t i; | |
3339 | ||
3340 | tree endlink = void_list_node; | |
3341 | ||
3342 | tree pint_type_node = build_pointer_type (integer_type_node); | |
f18c054f DB |
3343 | tree pshort_type_node = build_pointer_type (short_integer_type_node); |
3344 | tree pchar_type_node = build_pointer_type (char_type_node); | |
3345 | tree pfloat_type_node = build_pointer_type (float_type_node); | |
0ac081f6 AH |
3346 | |
3347 | /* V4SI foo (int *). */ | |
3348 | tree v4si_ftype_pint | |
3349 | = build_function_type (V4SI_type_node, | |
3350 | tree_cons (NULL_TREE, pint_type_node, endlink)); | |
f18c054f DB |
3351 | /* V8HI foo (short *). */ |
3352 | tree v8hi_ftype_pshort | |
3353 | = build_function_type (V8HI_type_node, | |
3354 | tree_cons (NULL_TREE, pshort_type_node, endlink)); | |
3355 | /* V16QI foo (char *). */ | |
3356 | tree v16qi_ftype_pchar | |
3357 | = build_function_type (V16QI_type_node, | |
3358 | tree_cons (NULL_TREE, pchar_type_node, endlink)); | |
3359 | /* V4SF foo (float *). */ | |
3360 | tree v4sf_ftype_pfloat | |
3361 | = build_function_type (V4SF_type_node, | |
3362 | tree_cons (NULL_TREE, pfloat_type_node, endlink)); | |
0ac081f6 AH |
3363 | |
3364 | /* void foo (int *, V4SI). */ | |
3365 | tree void_ftype_pint_v4si | |
3366 | = build_function_type (void_type_node, | |
3367 | tree_cons (NULL_TREE, pint_type_node, | |
3368 | tree_cons (NULL_TREE, V4SI_type_node, | |
3369 | endlink))); | |
f18c054f DB |
3370 | /* void foo (short *, V8HI). */ |
3371 | tree void_ftype_pshort_v8hi | |
3372 | = build_function_type (void_type_node, | |
3373 | tree_cons (NULL_TREE, pshort_type_node, | |
3374 | tree_cons (NULL_TREE, V8HI_type_node, | |
3375 | endlink))); | |
3376 | /* void foo (char *, V16QI). */ | |
3377 | tree void_ftype_pchar_v16qi | |
3378 | = build_function_type (void_type_node, | |
3379 | tree_cons (NULL_TREE, pchar_type_node, | |
3380 | tree_cons (NULL_TREE, V16QI_type_node, | |
3381 | endlink))); | |
3382 | /* void foo (float *, V4SF). */ | |
3383 | tree void_ftype_pfloat_v4sf | |
3384 | = build_function_type (void_type_node, | |
3385 | tree_cons (NULL_TREE, pfloat_type_node, | |
3386 | tree_cons (NULL_TREE, V4SF_type_node, | |
3387 | endlink))); | |
0ac081f6 AH |
3388 | |
3389 | tree v4si_ftype_v4si_v4si | |
3390 | = build_function_type (V4SI_type_node, | |
3391 | tree_cons (NULL_TREE, V4SI_type_node, | |
3392 | tree_cons (NULL_TREE, V4SI_type_node, | |
3393 | endlink))); | |
3394 | ||
3395 | tree v4sf_ftype_v4sf_v4sf | |
3396 | = build_function_type (V4SF_type_node, | |
3397 | tree_cons (NULL_TREE, V4SF_type_node, | |
3398 | tree_cons (NULL_TREE, V4SF_type_node, | |
3399 | endlink))); | |
3400 | ||
3401 | tree v8hi_ftype_v8hi_v8hi | |
3402 | = build_function_type (V8HI_type_node, | |
3403 | tree_cons (NULL_TREE, V8HI_type_node, | |
3404 | tree_cons (NULL_TREE, V8HI_type_node, | |
3405 | endlink))); | |
3406 | ||
3407 | tree v16qi_ftype_v16qi_v16qi | |
3408 | = build_function_type (V16QI_type_node, | |
3409 | tree_cons (NULL_TREE, V16QI_type_node, | |
3410 | tree_cons (NULL_TREE, V16QI_type_node, | |
3411 | endlink))); | |
3412 | ||
3413 | tree v4si_ftype_v4sf_v4sf | |
3414 | = build_function_type (V4SI_type_node, | |
3415 | tree_cons (NULL_TREE, V4SF_type_node, | |
3416 | tree_cons (NULL_TREE, V4SF_type_node, | |
3417 | endlink))); | |
3418 | ||
3419 | tree v8hi_ftype_v16qi_v16qi | |
3420 | = build_function_type (V8HI_type_node, | |
3421 | tree_cons (NULL_TREE, V16QI_type_node, | |
3422 | tree_cons (NULL_TREE, V16QI_type_node, | |
3423 | endlink))); | |
3424 | ||
3425 | tree v4si_ftype_v8hi_v8hi | |
3426 | = build_function_type (V4SI_type_node, | |
3427 | tree_cons (NULL_TREE, V8HI_type_node, | |
3428 | tree_cons (NULL_TREE, V8HI_type_node, | |
3429 | endlink))); | |
3430 | ||
3431 | tree v8hi_ftype_v4si_v4si | |
3432 | = build_function_type (V8HI_type_node, | |
3433 | tree_cons (NULL_TREE, V4SI_type_node, | |
3434 | tree_cons (NULL_TREE, V4SI_type_node, | |
3435 | endlink))); | |
3436 | ||
3437 | tree v16qi_ftype_v8hi_v8hi | |
3438 | = build_function_type (V16QI_type_node, | |
3439 | tree_cons (NULL_TREE, V8HI_type_node, | |
3440 | tree_cons (NULL_TREE, V8HI_type_node, | |
3441 | endlink))); | |
3442 | ||
3443 | tree v4si_ftype_v16qi_v4si | |
3444 | = build_function_type (V4SI_type_node, | |
3445 | tree_cons (NULL_TREE, V16QI_type_node, | |
3446 | tree_cons (NULL_TREE, V4SI_type_node, | |
3447 | endlink))); | |
3448 | ||
3449 | tree v4si_ftype_v8hi_v4si | |
3450 | = build_function_type (V4SI_type_node, | |
3451 | tree_cons (NULL_TREE, V8HI_type_node, | |
3452 | tree_cons (NULL_TREE, V4SI_type_node, | |
3453 | endlink))); | |
3454 | ||
3455 | tree int_ftype_v4si_v4si | |
3456 | = build_function_type (integer_type_node, | |
3457 | tree_cons (NULL_TREE, V4SI_type_node, | |
3458 | tree_cons (NULL_TREE, V4SI_type_node, | |
3459 | endlink))); | |
3460 | ||
3461 | tree int_ftype_v4sf_v4sf | |
3462 | = build_function_type (integer_type_node, | |
3463 | tree_cons (NULL_TREE, V4SF_type_node, | |
3464 | tree_cons (NULL_TREE, V4SF_type_node, | |
3465 | endlink))); | |
3466 | ||
3467 | tree int_ftype_v16qi_v16qi | |
3468 | = build_function_type (integer_type_node, | |
3469 | tree_cons (NULL_TREE, V16QI_type_node, | |
3470 | tree_cons (NULL_TREE, V16QI_type_node, | |
3471 | endlink))); | |
3472 | ||
3473 | tree int_ftype_v8hi_v8hi | |
3474 | = build_function_type (integer_type_node, | |
3475 | tree_cons (NULL_TREE, V8HI_type_node, | |
3476 | tree_cons (NULL_TREE, V8HI_type_node, | |
3477 | endlink))); | |
3478 | ||
f18c054f DB |
3479 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_4sf", v4sf_ftype_pfloat, ALTIVEC_BUILTIN_LD_INTERNAL_4sf); |
3480 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_4sf", void_ftype_pfloat_v4sf, ALTIVEC_BUILTIN_ST_INTERNAL_4sf); | |
3481 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_4si", v4si_ftype_pint, ALTIVEC_BUILTIN_LD_INTERNAL_4si); | |
3482 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_4si", void_ftype_pint_v4si, ALTIVEC_BUILTIN_ST_INTERNAL_4si); | |
3483 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_8hi", v8hi_ftype_pshort, ALTIVEC_BUILTIN_LD_INTERNAL_8hi); | |
3484 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_8hi", void_ftype_pshort_v8hi, ALTIVEC_BUILTIN_ST_INTERNAL_8hi); | |
3485 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_16qi", v16qi_ftype_pchar, ALTIVEC_BUILTIN_LD_INTERNAL_16qi); | |
3486 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_16qi", void_ftype_pchar_v16qi, ALTIVEC_BUILTIN_ST_INTERNAL_16qi); | |
0ac081f6 AH |
3487 | |
3488 | /* Add the simple binary operators. */ | |
00b960c7 AH |
3489 | d = (struct builtin_description *) bdesc_2arg; |
3490 | for (i = 0; i < sizeof (bdesc_2arg) / sizeof *d; i++, d++) | |
0ac081f6 AH |
3491 | { |
3492 | enum machine_mode mode0, mode1, mode2; | |
3493 | tree type; | |
3494 | ||
3495 | if (d->name == 0) | |
3496 | continue; | |
3497 | ||
3498 | mode0 = insn_data[d->icode].operand[0].mode; | |
3499 | mode1 = insn_data[d->icode].operand[1].mode; | |
3500 | mode2 = insn_data[d->icode].operand[2].mode; | |
3501 | ||
3502 | /* When all three operands are of the same mode. */ | |
3503 | if (mode0 == mode1 && mode1 == mode2) | |
3504 | { | |
3505 | switch (mode0) | |
3506 | { | |
3507 | case V4SFmode: | |
3508 | type = v4sf_ftype_v4sf_v4sf; | |
3509 | break; | |
3510 | case V4SImode: | |
3511 | type = v4si_ftype_v4si_v4si; | |
3512 | break; | |
3513 | case V16QImode: | |
3514 | type = v16qi_ftype_v16qi_v16qi; | |
3515 | break; | |
3516 | case V8HImode: | |
3517 | type = v8hi_ftype_v8hi_v8hi; | |
3518 | break; | |
3519 | default: | |
3520 | abort (); | |
3521 | } | |
3522 | } | |
3523 | ||
3524 | /* A few other combos we really don't want to do manually. */ | |
3525 | ||
3526 | /* vint, vfloat, vfloat. */ | |
3527 | else if (mode0 == V4SImode && mode1 == V4SFmode && mode2 == V4SFmode) | |
3528 | type = v4si_ftype_v4sf_v4sf; | |
3529 | ||
3530 | /* vshort, vchar, vchar. */ | |
3531 | else if (mode0 == V8HImode && mode1 == V16QImode && mode2 == V16QImode) | |
3532 | type = v8hi_ftype_v16qi_v16qi; | |
3533 | ||
3534 | /* vint, vshort, vshort. */ | |
3535 | else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V8HImode) | |
3536 | type = v4si_ftype_v8hi_v8hi; | |
3537 | ||
3538 | /* vshort, vint, vint. */ | |
3539 | else if (mode0 == V8HImode && mode1 == V4SImode && mode2 == V4SImode) | |
3540 | type = v8hi_ftype_v4si_v4si; | |
3541 | ||
3542 | /* vchar, vshort, vshort. */ | |
3543 | else if (mode0 == V16QImode && mode1 == V8HImode && mode2 == V8HImode) | |
3544 | type = v16qi_ftype_v8hi_v8hi; | |
3545 | ||
3546 | /* vint, vchar, vint. */ | |
3547 | else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V4SImode) | |
3548 | type = v4si_ftype_v16qi_v4si; | |
3549 | ||
3550 | /* vint, vshort, vint. */ | |
3551 | else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V4SImode) | |
3552 | type = v4si_ftype_v8hi_v4si; | |
3553 | ||
3554 | /* fixme: aldyh */ | |
3555 | /* int, x, x. */ | |
3556 | else if (mode0 == SImode) | |
3557 | { | |
3558 | switch (mode1) | |
3559 | { | |
3560 | case V4SImode: | |
3561 | type = int_ftype_v4si_v4si; | |
3562 | break; | |
3563 | case V4SFmode: | |
3564 | type = int_ftype_v4sf_v4sf; | |
3565 | break; | |
3566 | case V16QImode: | |
3567 | type = int_ftype_v16qi_v16qi; | |
3568 | break; | |
3569 | case V8HImode: | |
3570 | type = int_ftype_v8hi_v8hi; | |
3571 | break; | |
3572 | default: | |
3573 | abort (); | |
3574 | } | |
3575 | } | |
3576 | ||
3577 | else | |
3578 | abort (); | |
3579 | ||
3580 | def_builtin (d->mask, d->name, type, d->code); | |
3581 | } | |
3582 | } | |
3583 | ||
5b5040b9 RK |
3584 | \f |
3585 | /* Generate a memory reference for expand_block_move, copying volatile, | |
3586 | and other bits from an original memory reference. */ | |
3587 | ||
3588 | static rtx | |
3589 | expand_block_move_mem (mode, addr, orig_mem) | |
3590 | enum machine_mode mode; | |
3591 | rtx addr; | |
3592 | rtx orig_mem; | |
3593 | { | |
39403d82 | 3594 | rtx mem = gen_rtx_MEM (mode, addr); |
b6c9286a | 3595 | |
c6df88cb | 3596 | MEM_COPY_ATTRIBUTES (mem, orig_mem); |
5b5040b9 RK |
3597 | return mem; |
3598 | } | |
3599 | ||
7e69e155 MM |
3600 | /* Expand a block move operation, and return 1 if successful. Return 0 |
3601 | if we should let the compiler generate normal code. | |
3602 | ||
3603 | operands[0] is the destination | |
3604 | operands[1] is the source | |
3605 | operands[2] is the length | |
3606 | operands[3] is the alignment */ | |
3607 | ||
3933e0e1 MM |
3608 | #define MAX_MOVE_REG 4 |
3609 | ||
7e69e155 MM |
3610 | int |
3611 | expand_block_move (operands) | |
3612 | rtx operands[]; | |
3613 | { | |
b6c9286a MM |
3614 | rtx orig_dest = operands[0]; |
3615 | rtx orig_src = operands[1]; | |
7e69e155 | 3616 | rtx bytes_rtx = operands[2]; |
7e69e155 | 3617 | rtx align_rtx = operands[3]; |
3933e0e1 | 3618 | int constp = (GET_CODE (bytes_rtx) == CONST_INT); |
5ee95df6 | 3619 | int align; |
3933e0e1 MM |
3620 | int bytes; |
3621 | int offset; | |
3622 | int num_reg; | |
3623 | int i; | |
7e69e155 MM |
3624 | rtx src_reg; |
3625 | rtx dest_reg; | |
3933e0e1 MM |
3626 | rtx src_addr; |
3627 | rtx dest_addr; | |
7e69e155 | 3628 | rtx tmp_reg; |
3933e0e1 | 3629 | rtx stores[MAX_MOVE_REG]; |
7e69e155 MM |
3630 | int move_bytes; |
3631 | ||
3933e0e1 | 3632 | /* If this is not a fixed size move, just call memcpy */ |
cc0d9ba8 | 3633 | if (! constp) |
3933e0e1 MM |
3634 | return 0; |
3635 | ||
5ee95df6 FS |
3636 | /* If this is not a fixed size alignment, abort */ |
3637 | if (GET_CODE (align_rtx) != CONST_INT) | |
3638 | abort (); | |
3639 | align = INTVAL (align_rtx); | |
3640 | ||
7e69e155 | 3641 | /* Anything to move? */ |
3933e0e1 MM |
3642 | bytes = INTVAL (bytes_rtx); |
3643 | if (bytes <= 0) | |
7e69e155 MM |
3644 | return 1; |
3645 | ||
3933e0e1 MM |
3646 | /* Don't support real large moves. If string instructions are not used, |
3647 | then don't generate more than 8 loads. */ | |
3648 | if (TARGET_STRING) | |
3649 | { | |
c81fc13e | 3650 | if (bytes > 8*4) |
3933e0e1 MM |
3651 | return 0; |
3652 | } | |
cc0d9ba8 | 3653 | else if (! STRICT_ALIGNMENT) |
3933e0e1 | 3654 | { |
c81fc13e DE |
3655 | if (TARGET_POWERPC64 && align >= 4) |
3656 | { | |
3657 | if (bytes > 8*8) | |
3658 | return 0; | |
3659 | } | |
3660 | else | |
3661 | if (bytes > 8*4) | |
3662 | return 0; | |
3933e0e1 MM |
3663 | } |
3664 | else if (bytes > 8*align) | |
7e69e155 MM |
3665 | return 0; |
3666 | ||
3667 | /* Move the address into scratch registers. */ | |
b6c9286a MM |
3668 | dest_reg = copy_addr_to_reg (XEXP (orig_dest, 0)); |
3669 | src_reg = copy_addr_to_reg (XEXP (orig_src, 0)); | |
7e69e155 | 3670 | |
3933e0e1 | 3671 | if (TARGET_STRING) /* string instructions are available */ |
7e69e155 | 3672 | { |
3933e0e1 | 3673 | for ( ; bytes > 0; bytes -= move_bytes) |
7e69e155 | 3674 | { |
3933e0e1 | 3675 | if (bytes > 24 /* move up to 32 bytes at a time */ |
cc0d9ba8 DE |
3676 | && ! fixed_regs[5] |
3677 | && ! fixed_regs[6] | |
3678 | && ! fixed_regs[7] | |
3679 | && ! fixed_regs[8] | |
3680 | && ! fixed_regs[9] | |
3681 | && ! fixed_regs[10] | |
3682 | && ! fixed_regs[11] | |
3683 | && ! fixed_regs[12]) | |
3933e0e1 MM |
3684 | { |
3685 | move_bytes = (bytes > 32) ? 32 : bytes; | |
cc0d9ba8 DE |
3686 | emit_insn (gen_movstrsi_8reg (expand_block_move_mem (BLKmode, |
3687 | dest_reg, | |
3688 | orig_dest), | |
3689 | expand_block_move_mem (BLKmode, | |
3690 | src_reg, | |
3691 | orig_src), | |
3692 | GEN_INT ((move_bytes == 32) | |
3693 | ? 0 : move_bytes), | |
4c64a852 | 3694 | align_rtx)); |
3933e0e1 MM |
3695 | } |
3696 | else if (bytes > 16 /* move up to 24 bytes at a time */ | |
f9562f27 DE |
3697 | && ! fixed_regs[5] |
3698 | && ! fixed_regs[6] | |
cc0d9ba8 DE |
3699 | && ! fixed_regs[7] |
3700 | && ! fixed_regs[8] | |
3701 | && ! fixed_regs[9] | |
f9562f27 | 3702 | && ! fixed_regs[10]) |
3933e0e1 MM |
3703 | { |
3704 | move_bytes = (bytes > 24) ? 24 : bytes; | |
cc0d9ba8 DE |
3705 | emit_insn (gen_movstrsi_6reg (expand_block_move_mem (BLKmode, |
3706 | dest_reg, | |
3707 | orig_dest), | |
3708 | expand_block_move_mem (BLKmode, | |
3709 | src_reg, | |
3710 | orig_src), | |
3933e0e1 | 3711 | GEN_INT (move_bytes), |
4c64a852 | 3712 | align_rtx)); |
3933e0e1 MM |
3713 | } |
3714 | else if (bytes > 8 /* move up to 16 bytes at a time */ | |
f9562f27 DE |
3715 | && ! fixed_regs[5] |
3716 | && ! fixed_regs[6] | |
3717 | && ! fixed_regs[7] | |
3718 | && ! fixed_regs[8]) | |
3933e0e1 MM |
3719 | { |
3720 | move_bytes = (bytes > 16) ? 16 : bytes; | |
cc0d9ba8 DE |
3721 | emit_insn (gen_movstrsi_4reg (expand_block_move_mem (BLKmode, |
3722 | dest_reg, | |
3723 | orig_dest), | |
3724 | expand_block_move_mem (BLKmode, | |
3725 | src_reg, | |
3726 | orig_src), | |
3933e0e1 | 3727 | GEN_INT (move_bytes), |
4c64a852 | 3728 | align_rtx)); |
3933e0e1 | 3729 | } |
acad7ed3 | 3730 | else if (bytes >= 8 && TARGET_POWERPC64 |
a4f6c312 | 3731 | /* 64-bit loads and stores require word-aligned |
82e41834 | 3732 | displacements. */ |
a4f6c312 | 3733 | && (align >= 8 || (! STRICT_ALIGNMENT && align >= 4))) |
acad7ed3 DE |
3734 | { |
3735 | move_bytes = 8; | |
3736 | tmp_reg = gen_reg_rtx (DImode); | |
3737 | emit_move_insn (tmp_reg, | |
3738 | expand_block_move_mem (DImode, | |
2eba1afa | 3739 | src_reg, orig_src)); |
acad7ed3 | 3740 | emit_move_insn (expand_block_move_mem (DImode, |
2eba1afa | 3741 | dest_reg, orig_dest), |
acad7ed3 DE |
3742 | tmp_reg); |
3743 | } | |
3744 | else if (bytes > 4) | |
3933e0e1 MM |
3745 | { /* move up to 8 bytes at a time */ |
3746 | move_bytes = (bytes > 8) ? 8 : bytes; | |
cc0d9ba8 DE |
3747 | emit_insn (gen_movstrsi_2reg (expand_block_move_mem (BLKmode, |
3748 | dest_reg, | |
3749 | orig_dest), | |
3750 | expand_block_move_mem (BLKmode, | |
3751 | src_reg, | |
3752 | orig_src), | |
3933e0e1 | 3753 | GEN_INT (move_bytes), |
4c64a852 | 3754 | align_rtx)); |
3933e0e1 | 3755 | } |
cc0d9ba8 | 3756 | else if (bytes >= 4 && (align >= 4 || ! STRICT_ALIGNMENT)) |
3933e0e1 MM |
3757 | { /* move 4 bytes */ |
3758 | move_bytes = 4; | |
3759 | tmp_reg = gen_reg_rtx (SImode); | |
cc0d9ba8 DE |
3760 | emit_move_insn (tmp_reg, |
3761 | expand_block_move_mem (SImode, | |
3762 | src_reg, orig_src)); | |
3763 | emit_move_insn (expand_block_move_mem (SImode, | |
3764 | dest_reg, orig_dest), | |
3765 | tmp_reg); | |
3933e0e1 | 3766 | } |
cc0d9ba8 | 3767 | else if (bytes == 2 && (align >= 2 || ! STRICT_ALIGNMENT)) |
3933e0e1 MM |
3768 | { /* move 2 bytes */ |
3769 | move_bytes = 2; | |
3770 | tmp_reg = gen_reg_rtx (HImode); | |
cc0d9ba8 DE |
3771 | emit_move_insn (tmp_reg, |
3772 | expand_block_move_mem (HImode, | |
3773 | src_reg, orig_src)); | |
3774 | emit_move_insn (expand_block_move_mem (HImode, | |
3775 | dest_reg, orig_dest), | |
3776 | tmp_reg); | |
3933e0e1 MM |
3777 | } |
3778 | else if (bytes == 1) /* move 1 byte */ | |
3779 | { | |
3780 | move_bytes = 1; | |
3781 | tmp_reg = gen_reg_rtx (QImode); | |
cc0d9ba8 DE |
3782 | emit_move_insn (tmp_reg, |
3783 | expand_block_move_mem (QImode, | |
3784 | src_reg, orig_src)); | |
3785 | emit_move_insn (expand_block_move_mem (QImode, | |
3786 | dest_reg, orig_dest), | |
3787 | tmp_reg); | |
3933e0e1 MM |
3788 | } |
3789 | else | |
3790 | { /* move up to 4 bytes at a time */ | |
3791 | move_bytes = (bytes > 4) ? 4 : bytes; | |
cc0d9ba8 DE |
3792 | emit_insn (gen_movstrsi_1reg (expand_block_move_mem (BLKmode, |
3793 | dest_reg, | |
3794 | orig_dest), | |
3795 | expand_block_move_mem (BLKmode, | |
3796 | src_reg, | |
3797 | orig_src), | |
3933e0e1 | 3798 | GEN_INT (move_bytes), |
4c64a852 | 3799 | align_rtx)); |
3933e0e1 | 3800 | } |
4c64a852 | 3801 | |
015892ee RK |
3802 | if (bytes > move_bytes) |
3803 | { | |
cc0d9ba8 DE |
3804 | if (! TARGET_POWERPC64) |
3805 | { | |
3806 | emit_insn (gen_addsi3 (src_reg, src_reg, | |
3807 | GEN_INT (move_bytes))); | |
3808 | emit_insn (gen_addsi3 (dest_reg, dest_reg, | |
3809 | GEN_INT (move_bytes))); | |
3810 | } | |
3811 | else | |
3812 | { | |
3813 | emit_insn (gen_adddi3 (src_reg, src_reg, | |
3814 | GEN_INT (move_bytes))); | |
3815 | emit_insn (gen_adddi3 (dest_reg, dest_reg, | |
3816 | GEN_INT (move_bytes))); | |
3817 | } | |
015892ee | 3818 | } |
4c64a852 | 3819 | } |
3933e0e1 MM |
3820 | } |
3821 | ||
3822 | else /* string instructions not available */ | |
3823 | { | |
3824 | num_reg = offset = 0; | |
3825 | for ( ; bytes > 0; (bytes -= move_bytes), (offset += move_bytes)) | |
7e69e155 | 3826 | { |
3933e0e1 MM |
3827 | /* Calculate the correct offset for src/dest */ |
3828 | if (offset == 0) | |
7e69e155 | 3829 | { |
3933e0e1 MM |
3830 | src_addr = src_reg; |
3831 | dest_addr = dest_reg; | |
3832 | } | |
3833 | else | |
3834 | { | |
c5c76735 JL |
3835 | src_addr = plus_constant (src_reg, offset); |
3836 | dest_addr = plus_constant (dest_reg, offset); | |
3933e0e1 MM |
3837 | } |
3838 | ||
cc0d9ba8 DE |
3839 | /* Generate the appropriate load and store, saving the stores |
3840 | for later. */ | |
3841 | if (bytes >= 8 && TARGET_POWERPC64 | |
a4f6c312 SS |
3842 | /* 64-bit loads and stores require word-aligned |
3843 | displacements. */ | |
cc0d9ba8 | 3844 | && (align >= 8 || (! STRICT_ALIGNMENT && align >= 4))) |
b6c9286a MM |
3845 | { |
3846 | move_bytes = 8; | |
3847 | tmp_reg = gen_reg_rtx (DImode); | |
cc0d9ba8 DE |
3848 | emit_insn (gen_movdi (tmp_reg, |
3849 | expand_block_move_mem (DImode, | |
3850 | src_addr, | |
3851 | orig_src))); | |
3852 | stores[num_reg++] = gen_movdi (expand_block_move_mem (DImode, | |
3853 | dest_addr, | |
3854 | orig_dest), | |
3855 | tmp_reg); | |
b6c9286a | 3856 | } |
cc0d9ba8 | 3857 | else if (bytes >= 4 && (align >= 4 || ! STRICT_ALIGNMENT)) |
3933e0e1 MM |
3858 | { |
3859 | move_bytes = 4; | |
3860 | tmp_reg = gen_reg_rtx (SImode); | |
cc0d9ba8 DE |
3861 | emit_insn (gen_movsi (tmp_reg, |
3862 | expand_block_move_mem (SImode, | |
3863 | src_addr, | |
3864 | orig_src))); | |
3865 | stores[num_reg++] = gen_movsi (expand_block_move_mem (SImode, | |
3866 | dest_addr, | |
3867 | orig_dest), | |
3868 | tmp_reg); | |
3933e0e1 | 3869 | } |
cc0d9ba8 | 3870 | else if (bytes >= 2 && (align >= 2 || ! STRICT_ALIGNMENT)) |
3933e0e1 MM |
3871 | { |
3872 | move_bytes = 2; | |
3873 | tmp_reg = gen_reg_rtx (HImode); | |
c81fc13e | 3874 | emit_insn (gen_movhi (tmp_reg, |
cc0d9ba8 DE |
3875 | expand_block_move_mem (HImode, |
3876 | src_addr, | |
3877 | orig_src))); | |
3878 | stores[num_reg++] = gen_movhi (expand_block_move_mem (HImode, | |
3879 | dest_addr, | |
3880 | orig_dest), | |
3881 | tmp_reg); | |
3933e0e1 MM |
3882 | } |
3883 | else | |
3884 | { | |
3885 | move_bytes = 1; | |
3886 | tmp_reg = gen_reg_rtx (QImode); | |
c81fc13e | 3887 | emit_insn (gen_movqi (tmp_reg, |
cc0d9ba8 DE |
3888 | expand_block_move_mem (QImode, |
3889 | src_addr, | |
3890 | orig_src))); | |
3891 | stores[num_reg++] = gen_movqi (expand_block_move_mem (QImode, | |
3892 | dest_addr, | |
3893 | orig_dest), | |
a4f6c312 | 3894 | tmp_reg); |
3933e0e1 MM |
3895 | } |
3896 | ||
3897 | if (num_reg >= MAX_MOVE_REG) | |
3898 | { | |
3899 | for (i = 0; i < num_reg; i++) | |
3900 | emit_insn (stores[i]); | |
3901 | num_reg = 0; | |
7e69e155 MM |
3902 | } |
3903 | } | |
3933e0e1 | 3904 | |
b6c9286a MM |
3905 | for (i = 0; i < num_reg; i++) |
3906 | emit_insn (stores[i]); | |
7e69e155 MM |
3907 | } |
3908 | ||
3909 | return 1; | |
3910 | } | |
3911 | ||
9878760c RK |
3912 | \f |
3913 | /* Return 1 if OP is a load multiple operation. It is known to be a | |
3914 | PARALLEL and the first section will be tested. */ | |
3915 | ||
3916 | int | |
3917 | load_multiple_operation (op, mode) | |
3918 | rtx op; | |
296b8152 | 3919 | enum machine_mode mode ATTRIBUTE_UNUSED; |
9878760c RK |
3920 | { |
3921 | int count = XVECLEN (op, 0); | |
e2c953b6 | 3922 | unsigned int dest_regno; |
9878760c RK |
3923 | rtx src_addr; |
3924 | int i; | |
3925 | ||
3926 | /* Perform a quick check so we don't blow up below. */ | |
3927 | if (count <= 1 | |
3928 | || GET_CODE (XVECEXP (op, 0, 0)) != SET | |
3929 | || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG | |
3930 | || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM) | |
3931 | return 0; | |
3932 | ||
3933 | dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0))); | |
3934 | src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0); | |
3935 | ||
3936 | for (i = 1; i < count; i++) | |
3937 | { | |
3938 | rtx elt = XVECEXP (op, 0, i); | |
3939 | ||
3940 | if (GET_CODE (elt) != SET | |
3941 | || GET_CODE (SET_DEST (elt)) != REG | |
3942 | || GET_MODE (SET_DEST (elt)) != SImode | |
3943 | || REGNO (SET_DEST (elt)) != dest_regno + i | |
3944 | || GET_CODE (SET_SRC (elt)) != MEM | |
3945 | || GET_MODE (SET_SRC (elt)) != SImode | |
3946 | || GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS | |
3947 | || ! rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr) | |
3948 | || GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT | |
3949 | || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != i * 4) | |
3950 | return 0; | |
3951 | } | |
3952 | ||
3953 | return 1; | |
3954 | } | |
3955 | ||
3956 | /* Similar, but tests for store multiple. Here, the second vector element | |
3957 | is a CLOBBER. It will be tested later. */ | |
3958 | ||
3959 | int | |
3960 | store_multiple_operation (op, mode) | |
3961 | rtx op; | |
296b8152 | 3962 | enum machine_mode mode ATTRIBUTE_UNUSED; |
9878760c RK |
3963 | { |
3964 | int count = XVECLEN (op, 0) - 1; | |
e2c953b6 | 3965 | unsigned int src_regno; |
9878760c RK |
3966 | rtx dest_addr; |
3967 | int i; | |
3968 | ||
3969 | /* Perform a quick check so we don't blow up below. */ | |
3970 | if (count <= 1 | |
3971 | || GET_CODE (XVECEXP (op, 0, 0)) != SET | |
3972 | || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM | |
3973 | || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG) | |
3974 | return 0; | |
3975 | ||
3976 | src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0))); | |
3977 | dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0); | |
3978 | ||
3979 | for (i = 1; i < count; i++) | |
3980 | { | |
3981 | rtx elt = XVECEXP (op, 0, i + 1); | |
3982 | ||
3983 | if (GET_CODE (elt) != SET | |
3984 | || GET_CODE (SET_SRC (elt)) != REG | |
3985 | || GET_MODE (SET_SRC (elt)) != SImode | |
3986 | || REGNO (SET_SRC (elt)) != src_regno + i | |
3987 | || GET_CODE (SET_DEST (elt)) != MEM | |
3988 | || GET_MODE (SET_DEST (elt)) != SImode | |
3989 | || GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS | |
3990 | || ! rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr) | |
3991 | || GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT | |
3992 | || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != i * 4) | |
3993 | return 0; | |
3994 | } | |
3995 | ||
3996 | return 1; | |
3997 | } | |
9ebbca7d | 3998 | |
00b960c7 AH |
3999 | /* Return 1 for a parallel vrsave operation. */ |
4000 | ||
4001 | int | |
4002 | vrsave_operation (op, mode) | |
4003 | rtx op; | |
4004 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
4005 | { | |
4006 | int count = XVECLEN (op, 0); | |
4007 | unsigned int dest_regno, src_regno; | |
4008 | int i; | |
4009 | ||
4010 | if (count <= 1 | |
4011 | || GET_CODE (XVECEXP (op, 0, 0)) != SET | |
4012 | || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG | |
4013 | || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC) | |
4014 | return 0; | |
4015 | ||
4016 | dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0))); | |
4017 | src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0))); | |
4018 | ||
4019 | if (dest_regno != VRSAVE_REGNO | |
4020 | && src_regno != VRSAVE_REGNO) | |
4021 | return 0; | |
4022 | ||
4023 | for (i = 1; i < count; i++) | |
4024 | { | |
4025 | rtx elt = XVECEXP (op, 0, i); | |
4026 | ||
4027 | if (GET_CODE (elt) != CLOBBER) | |
4028 | return 0; | |
4029 | } | |
4030 | ||
4031 | return 1; | |
4032 | } | |
4033 | ||
a4f6c312 | 4034 | /* Return 1 for an PARALLEL suitable for mtcrf. */ |
9ebbca7d GK |
4035 | |
4036 | int | |
4037 | mtcrf_operation (op, mode) | |
4038 | rtx op; | |
4039 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
4040 | { | |
4041 | int count = XVECLEN (op, 0); | |
4042 | int i; | |
9ebbca7d GK |
4043 | rtx src_reg; |
4044 | ||
4045 | /* Perform a quick check so we don't blow up below. */ | |
e35b9579 GK |
4046 | if (count < 1 |
4047 | || GET_CODE (XVECEXP (op, 0, 0)) != SET | |
4048 | || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC | |
4049 | || XVECLEN (SET_SRC (XVECEXP (op, 0, 0)), 0) != 2) | |
9ebbca7d | 4050 | return 0; |
e35b9579 | 4051 | src_reg = XVECEXP (SET_SRC (XVECEXP (op, 0, 0)), 0, 0); |
9ebbca7d GK |
4052 | |
4053 | if (GET_CODE (src_reg) != REG | |
4054 | || GET_MODE (src_reg) != SImode | |
4055 | || ! INT_REGNO_P (REGNO (src_reg))) | |
4056 | return 0; | |
4057 | ||
e35b9579 | 4058 | for (i = 0; i < count; i++) |
9ebbca7d GK |
4059 | { |
4060 | rtx exp = XVECEXP (op, 0, i); | |
4061 | rtx unspec; | |
4062 | int maskval; | |
4063 | ||
4064 | if (GET_CODE (exp) != SET | |
4065 | || GET_CODE (SET_DEST (exp)) != REG | |
4066 | || GET_MODE (SET_DEST (exp)) != CCmode | |
4067 | || ! CR_REGNO_P (REGNO (SET_DEST (exp)))) | |
4068 | return 0; | |
4069 | unspec = SET_SRC (exp); | |
4070 | maskval = 1 << (MAX_CR_REGNO - REGNO (SET_DEST (exp))); | |
9ebbca7d GK |
4071 | |
4072 | if (GET_CODE (unspec) != UNSPEC | |
4073 | || XINT (unspec, 1) != 20 | |
4074 | || XVECLEN (unspec, 0) != 2 | |
4075 | || XVECEXP (unspec, 0, 0) != src_reg | |
4076 | || GET_CODE (XVECEXP (unspec, 0, 1)) != CONST_INT | |
4077 | || INTVAL (XVECEXP (unspec, 0, 1)) != maskval) | |
4078 | return 0; | |
4079 | } | |
e35b9579 | 4080 | return 1; |
9ebbca7d GK |
4081 | } |
4082 | ||
a4f6c312 | 4083 | /* Return 1 for an PARALLEL suitable for lmw. */ |
9ebbca7d GK |
4084 | |
4085 | int | |
4086 | lmw_operation (op, mode) | |
4087 | rtx op; | |
4088 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
4089 | { | |
4090 | int count = XVECLEN (op, 0); | |
e2c953b6 | 4091 | unsigned int dest_regno; |
9ebbca7d | 4092 | rtx src_addr; |
e2c953b6 | 4093 | unsigned int base_regno; |
9ebbca7d GK |
4094 | HOST_WIDE_INT offset; |
4095 | int i; | |
4096 | ||
4097 | /* Perform a quick check so we don't blow up below. */ | |
4098 | if (count <= 1 | |
4099 | || GET_CODE (XVECEXP (op, 0, 0)) != SET | |
4100 | || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG | |
4101 | || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM) | |
4102 | return 0; | |
4103 | ||
4104 | dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0))); | |
4105 | src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0); | |
4106 | ||
4107 | if (dest_regno > 31 | |
e2c953b6 | 4108 | || count != 32 - (int) dest_regno) |
9ebbca7d GK |
4109 | return 0; |
4110 | ||
258bfae2 | 4111 | if (LEGITIMATE_INDIRECT_ADDRESS_P (src_addr, 0)) |
9ebbca7d GK |
4112 | { |
4113 | offset = 0; | |
4114 | base_regno = REGNO (src_addr); | |
4115 | if (base_regno == 0) | |
4116 | return 0; | |
4117 | } | |
258bfae2 | 4118 | else if (LEGITIMATE_OFFSET_ADDRESS_P (SImode, src_addr, 0)) |
9ebbca7d GK |
4119 | { |
4120 | offset = INTVAL (XEXP (src_addr, 1)); | |
4121 | base_regno = REGNO (XEXP (src_addr, 0)); | |
4122 | } | |
4123 | else | |
4124 | return 0; | |
4125 | ||
4126 | for (i = 0; i < count; i++) | |
4127 | { | |
4128 | rtx elt = XVECEXP (op, 0, i); | |
4129 | rtx newaddr; | |
4130 | rtx addr_reg; | |
4131 | HOST_WIDE_INT newoffset; | |
4132 | ||
4133 | if (GET_CODE (elt) != SET | |
4134 | || GET_CODE (SET_DEST (elt)) != REG | |
4135 | || GET_MODE (SET_DEST (elt)) != SImode | |
4136 | || REGNO (SET_DEST (elt)) != dest_regno + i | |
4137 | || GET_CODE (SET_SRC (elt)) != MEM | |
4138 | || GET_MODE (SET_SRC (elt)) != SImode) | |
4139 | return 0; | |
4140 | newaddr = XEXP (SET_SRC (elt), 0); | |
258bfae2 | 4141 | if (LEGITIMATE_INDIRECT_ADDRESS_P (newaddr, 0)) |
9ebbca7d GK |
4142 | { |
4143 | newoffset = 0; | |
4144 | addr_reg = newaddr; | |
4145 | } | |
258bfae2 | 4146 | else if (LEGITIMATE_OFFSET_ADDRESS_P (SImode, newaddr, 0)) |
9ebbca7d GK |
4147 | { |
4148 | addr_reg = XEXP (newaddr, 0); | |
4149 | newoffset = INTVAL (XEXP (newaddr, 1)); | |
4150 | } | |
4151 | else | |
4152 | return 0; | |
4153 | if (REGNO (addr_reg) != base_regno | |
4154 | || newoffset != offset + 4 * i) | |
4155 | return 0; | |
4156 | } | |
4157 | ||
4158 | return 1; | |
4159 | } | |
4160 | ||
a4f6c312 | 4161 | /* Return 1 for an PARALLEL suitable for stmw. */ |
9ebbca7d GK |
4162 | |
4163 | int | |
4164 | stmw_operation (op, mode) | |
4165 | rtx op; | |
4166 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
4167 | { | |
4168 | int count = XVECLEN (op, 0); | |
e2c953b6 | 4169 | unsigned int src_regno; |
9ebbca7d | 4170 | rtx dest_addr; |
e2c953b6 | 4171 | unsigned int base_regno; |
9ebbca7d GK |
4172 | HOST_WIDE_INT offset; |
4173 | int i; | |
4174 | ||
4175 | /* Perform a quick check so we don't blow up below. */ | |
4176 | if (count <= 1 | |
4177 | || GET_CODE (XVECEXP (op, 0, 0)) != SET | |
4178 | || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM | |
4179 | || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG) | |
4180 | return 0; | |
4181 | ||
4182 | src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0))); | |
4183 | dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0); | |
4184 | ||
4185 | if (src_regno > 31 | |
e2c953b6 | 4186 | || count != 32 - (int) src_regno) |
9ebbca7d GK |
4187 | return 0; |
4188 | ||
258bfae2 | 4189 | if (LEGITIMATE_INDIRECT_ADDRESS_P (dest_addr, 0)) |
9ebbca7d GK |
4190 | { |
4191 | offset = 0; | |
4192 | base_regno = REGNO (dest_addr); | |
4193 | if (base_regno == 0) | |
4194 | return 0; | |
4195 | } | |
258bfae2 | 4196 | else if (LEGITIMATE_OFFSET_ADDRESS_P (SImode, dest_addr, 0)) |
9ebbca7d GK |
4197 | { |
4198 | offset = INTVAL (XEXP (dest_addr, 1)); | |
4199 | base_regno = REGNO (XEXP (dest_addr, 0)); | |
4200 | } | |
4201 | else | |
4202 | return 0; | |
4203 | ||
4204 | for (i = 0; i < count; i++) | |
4205 | { | |
4206 | rtx elt = XVECEXP (op, 0, i); | |
4207 | rtx newaddr; | |
4208 | rtx addr_reg; | |
4209 | HOST_WIDE_INT newoffset; | |
4210 | ||
4211 | if (GET_CODE (elt) != SET | |
4212 | || GET_CODE (SET_SRC (elt)) != REG | |
4213 | || GET_MODE (SET_SRC (elt)) != SImode | |
4214 | || REGNO (SET_SRC (elt)) != src_regno + i | |
4215 | || GET_CODE (SET_DEST (elt)) != MEM | |
4216 | || GET_MODE (SET_DEST (elt)) != SImode) | |
4217 | return 0; | |
4218 | newaddr = XEXP (SET_DEST (elt), 0); | |
258bfae2 | 4219 | if (LEGITIMATE_INDIRECT_ADDRESS_P (newaddr, 0)) |
9ebbca7d GK |
4220 | { |
4221 | newoffset = 0; | |
4222 | addr_reg = newaddr; | |
4223 | } | |
258bfae2 | 4224 | else if (LEGITIMATE_OFFSET_ADDRESS_P (SImode, newaddr, 0)) |
9ebbca7d GK |
4225 | { |
4226 | addr_reg = XEXP (newaddr, 0); | |
4227 | newoffset = INTVAL (XEXP (newaddr, 1)); | |
4228 | } | |
4229 | else | |
4230 | return 0; | |
4231 | if (REGNO (addr_reg) != base_regno | |
4232 | || newoffset != offset + 4 * i) | |
4233 | return 0; | |
4234 | } | |
4235 | ||
4236 | return 1; | |
4237 | } | |
9878760c | 4238 | \f |
a4f6c312 SS |
4239 | /* A validation routine: say whether CODE, a condition code, and MODE |
4240 | match. The other alternatives either don't make sense or should | |
4241 | never be generated. */ | |
39a10a29 | 4242 | |
39a10a29 GK |
4243 | static void |
4244 | validate_condition_mode (code, mode) | |
4245 | enum rtx_code code; | |
4246 | enum machine_mode mode; | |
4247 | { | |
4248 | if (GET_RTX_CLASS (code) != '<' | |
4249 | || GET_MODE_CLASS (mode) != MODE_CC) | |
4250 | abort (); | |
4251 | ||
4252 | /* These don't make sense. */ | |
4253 | if ((code == GT || code == LT || code == GE || code == LE) | |
4254 | && mode == CCUNSmode) | |
4255 | abort (); | |
4256 | ||
4257 | if ((code == GTU || code == LTU || code == GEU || code == LEU) | |
4258 | && mode != CCUNSmode) | |
4259 | abort (); | |
4260 | ||
4261 | if (mode != CCFPmode | |
4262 | && (code == ORDERED || code == UNORDERED | |
4263 | || code == UNEQ || code == LTGT | |
4264 | || code == UNGT || code == UNLT | |
4265 | || code == UNGE || code == UNLE)) | |
a4f6c312 | 4266 | abort (); |
39a10a29 | 4267 | |
de6c5979 BL |
4268 | /* These should never be generated except for |
4269 | flag_unsafe_math_optimizations. */ | |
39a10a29 | 4270 | if (mode == CCFPmode |
de6c5979 | 4271 | && ! flag_unsafe_math_optimizations |
39a10a29 GK |
4272 | && (code == LE || code == GE |
4273 | || code == UNEQ || code == LTGT | |
4274 | || code == UNGT || code == UNLT)) | |
4275 | abort (); | |
4276 | ||
4277 | /* These are invalid; the information is not there. */ | |
4278 | if (mode == CCEQmode | |
4279 | && code != EQ && code != NE) | |
4280 | abort (); | |
4281 | } | |
4282 | ||
9878760c RK |
4283 | /* Return 1 if OP is a comparison operation that is valid for a branch insn. |
4284 | We only check the opcode against the mode of the CC value here. */ | |
4285 | ||
4286 | int | |
4287 | branch_comparison_operator (op, mode) | |
592696dd | 4288 | rtx op; |
296b8152 | 4289 | enum machine_mode mode ATTRIBUTE_UNUSED; |
9878760c RK |
4290 | { |
4291 | enum rtx_code code = GET_CODE (op); | |
4292 | enum machine_mode cc_mode; | |
4293 | ||
4294 | if (GET_RTX_CLASS (code) != '<') | |
4295 | return 0; | |
4296 | ||
4297 | cc_mode = GET_MODE (XEXP (op, 0)); | |
4298 | if (GET_MODE_CLASS (cc_mode) != MODE_CC) | |
4299 | return 0; | |
4300 | ||
39a10a29 | 4301 | validate_condition_mode (code, cc_mode); |
9878760c | 4302 | |
39a10a29 GK |
4303 | return 1; |
4304 | } | |
4305 | ||
4306 | /* Return 1 if OP is a comparison operation that is valid for a branch | |
4307 | insn and which is true if the corresponding bit in the CC register | |
4308 | is set. */ | |
4309 | ||
4310 | int | |
4311 | branch_positive_comparison_operator (op, mode) | |
592696dd | 4312 | rtx op; |
39a10a29 GK |
4313 | enum machine_mode mode; |
4314 | { | |
4315 | enum rtx_code code; | |
4316 | ||
4317 | if (! branch_comparison_operator (op, mode)) | |
9878760c RK |
4318 | return 0; |
4319 | ||
39a10a29 GK |
4320 | code = GET_CODE (op); |
4321 | return (code == EQ || code == LT || code == GT | |
4322 | || code == LTU || code == GTU | |
4323 | || code == UNORDERED); | |
9878760c RK |
4324 | } |
4325 | ||
4326 | /* Return 1 if OP is a comparison operation that is valid for an scc insn. | |
4327 | We check the opcode against the mode of the CC value and disallow EQ or | |
4328 | NE comparisons for integers. */ | |
4329 | ||
4330 | int | |
4331 | scc_comparison_operator (op, mode) | |
592696dd | 4332 | rtx op; |
9878760c RK |
4333 | enum machine_mode mode; |
4334 | { | |
4335 | enum rtx_code code = GET_CODE (op); | |
4336 | enum machine_mode cc_mode; | |
4337 | ||
4338 | if (GET_MODE (op) != mode && mode != VOIDmode) | |
4339 | return 0; | |
4340 | ||
4341 | if (GET_RTX_CLASS (code) != '<') | |
4342 | return 0; | |
4343 | ||
4344 | cc_mode = GET_MODE (XEXP (op, 0)); | |
4345 | if (GET_MODE_CLASS (cc_mode) != MODE_CC) | |
4346 | return 0; | |
4347 | ||
39a10a29 | 4348 | validate_condition_mode (code, cc_mode); |
9878760c | 4349 | |
39a10a29 | 4350 | if (code == NE && cc_mode != CCFPmode) |
c5defebb RK |
4351 | return 0; |
4352 | ||
9878760c RK |
4353 | return 1; |
4354 | } | |
e0cd0770 JC |
4355 | |
4356 | int | |
4357 | trap_comparison_operator (op, mode) | |
4358 | rtx op; | |
4359 | enum machine_mode mode; | |
4360 | { | |
4361 | if (mode != VOIDmode && mode != GET_MODE (op)) | |
4362 | return 0; | |
39a10a29 | 4363 | return GET_RTX_CLASS (GET_CODE (op)) == '<'; |
e0cd0770 | 4364 | } |
dfbdccdb GK |
4365 | |
4366 | int | |
4367 | boolean_operator (op, mode) | |
4368 | rtx op; | |
4369 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
4370 | { | |
4371 | enum rtx_code code = GET_CODE (op); | |
4372 | return (code == AND || code == IOR || code == XOR); | |
4373 | } | |
1d328b19 GK |
4374 | |
4375 | int | |
4376 | boolean_or_operator (op, mode) | |
4377 | rtx op; | |
4378 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
4379 | { | |
4380 | enum rtx_code code = GET_CODE (op); | |
4381 | return (code == IOR || code == XOR); | |
4382 | } | |
50a0b056 GK |
4383 | |
4384 | int | |
4385 | min_max_operator (op, mode) | |
4386 | rtx op; | |
4387 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
4388 | { | |
4389 | enum rtx_code code = GET_CODE (op); | |
4390 | return (code == SMIN || code == SMAX || code == UMIN || code == UMAX); | |
4391 | } | |
9878760c RK |
4392 | \f |
4393 | /* Return 1 if ANDOP is a mask that has no bits on that are not in the | |
4394 | mask required to convert the result of a rotate insn into a shift | |
4395 | left insn of SHIFTOP bits. Both are known to be CONST_INT. */ | |
4396 | ||
4397 | int | |
4398 | includes_lshift_p (shiftop, andop) | |
592696dd SS |
4399 | rtx shiftop; |
4400 | rtx andop; | |
9878760c | 4401 | { |
e2c953b6 DE |
4402 | unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0; |
4403 | ||
4404 | shift_mask <<= INTVAL (shiftop); | |
9878760c RK |
4405 | |
4406 | return (INTVAL (andop) & ~shift_mask) == 0; | |
4407 | } | |
4408 | ||
4409 | /* Similar, but for right shift. */ | |
4410 | ||
4411 | int | |
4412 | includes_rshift_p (shiftop, andop) | |
592696dd SS |
4413 | rtx shiftop; |
4414 | rtx andop; | |
9878760c | 4415 | { |
a7653a2c | 4416 | unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0; |
9878760c RK |
4417 | |
4418 | shift_mask >>= INTVAL (shiftop); | |
4419 | ||
e2c953b6 DE |
4420 | return (INTVAL (andop) & ~shift_mask) == 0; |
4421 | } | |
4422 | ||
c5059423 AM |
4423 | /* Return 1 if ANDOP is a mask suitable for use with an rldic insn |
4424 | to perform a left shift. It must have exactly SHIFTOP least | |
4425 | signifigant 0's, then one or more 1's, then zero or more 0's. */ | |
e2c953b6 DE |
4426 | |
4427 | int | |
c5059423 | 4428 | includes_rldic_lshift_p (shiftop, andop) |
592696dd SS |
4429 | rtx shiftop; |
4430 | rtx andop; | |
e2c953b6 | 4431 | { |
c5059423 AM |
4432 | if (GET_CODE (andop) == CONST_INT) |
4433 | { | |
02071907 | 4434 | HOST_WIDE_INT c, lsb, shift_mask; |
e2c953b6 | 4435 | |
c5059423 | 4436 | c = INTVAL (andop); |
02071907 | 4437 | if (c == 0 || c == ~0) |
c5059423 | 4438 | return 0; |
e2c953b6 | 4439 | |
02071907 | 4440 | shift_mask = ~0; |
c5059423 AM |
4441 | shift_mask <<= INTVAL (shiftop); |
4442 | ||
4443 | /* Find the least signifigant one bit. */ | |
4444 | lsb = c & -c; | |
4445 | ||
4446 | /* It must coincide with the LSB of the shift mask. */ | |
4447 | if (-lsb != shift_mask) | |
4448 | return 0; | |
e2c953b6 | 4449 | |
c5059423 AM |
4450 | /* Invert to look for the next transition (if any). */ |
4451 | c = ~c; | |
4452 | ||
4453 | /* Remove the low group of ones (originally low group of zeros). */ | |
4454 | c &= -lsb; | |
4455 | ||
4456 | /* Again find the lsb, and check we have all 1's above. */ | |
4457 | lsb = c & -c; | |
4458 | return c == -lsb; | |
4459 | } | |
4460 | else if (GET_CODE (andop) == CONST_DOUBLE | |
4461 | && (GET_MODE (andop) == VOIDmode || GET_MODE (andop) == DImode)) | |
4462 | { | |
02071907 AM |
4463 | HOST_WIDE_INT low, high, lsb; |
4464 | HOST_WIDE_INT shift_mask_low, shift_mask_high; | |
c5059423 AM |
4465 | |
4466 | low = CONST_DOUBLE_LOW (andop); | |
4467 | if (HOST_BITS_PER_WIDE_INT < 64) | |
4468 | high = CONST_DOUBLE_HIGH (andop); | |
4469 | ||
4470 | if ((low == 0 && (HOST_BITS_PER_WIDE_INT >= 64 || high == 0)) | |
02071907 | 4471 | || (low == ~0 && (HOST_BITS_PER_WIDE_INT >= 64 || high == ~0))) |
c5059423 AM |
4472 | return 0; |
4473 | ||
4474 | if (HOST_BITS_PER_WIDE_INT < 64 && low == 0) | |
4475 | { | |
02071907 | 4476 | shift_mask_high = ~0; |
c5059423 AM |
4477 | if (INTVAL (shiftop) > 32) |
4478 | shift_mask_high <<= INTVAL (shiftop) - 32; | |
4479 | ||
4480 | lsb = high & -high; | |
4481 | ||
4482 | if (-lsb != shift_mask_high || INTVAL (shiftop) < 32) | |
4483 | return 0; | |
4484 | ||
4485 | high = ~high; | |
4486 | high &= -lsb; | |
4487 | ||
4488 | lsb = high & -high; | |
4489 | return high == -lsb; | |
4490 | } | |
4491 | ||
02071907 | 4492 | shift_mask_low = ~0; |
c5059423 AM |
4493 | shift_mask_low <<= INTVAL (shiftop); |
4494 | ||
4495 | lsb = low & -low; | |
4496 | ||
4497 | if (-lsb != shift_mask_low) | |
4498 | return 0; | |
4499 | ||
4500 | if (HOST_BITS_PER_WIDE_INT < 64) | |
4501 | high = ~high; | |
4502 | low = ~low; | |
4503 | low &= -lsb; | |
4504 | ||
4505 | if (HOST_BITS_PER_WIDE_INT < 64 && low == 0) | |
4506 | { | |
4507 | lsb = high & -high; | |
4508 | return high == -lsb; | |
4509 | } | |
4510 | ||
4511 | lsb = low & -low; | |
4512 | return low == -lsb && (HOST_BITS_PER_WIDE_INT >= 64 || high == ~0); | |
4513 | } | |
4514 | else | |
4515 | return 0; | |
4516 | } | |
e2c953b6 | 4517 | |
c5059423 AM |
4518 | /* Return 1 if ANDOP is a mask suitable for use with an rldicr insn |
4519 | to perform a left shift. It must have SHIFTOP or more least | |
4520 | signifigant 0's, with the remainder of the word 1's. */ | |
e2c953b6 | 4521 | |
c5059423 AM |
4522 | int |
4523 | includes_rldicr_lshift_p (shiftop, andop) | |
592696dd SS |
4524 | rtx shiftop; |
4525 | rtx andop; | |
c5059423 | 4526 | { |
e2c953b6 | 4527 | if (GET_CODE (andop) == CONST_INT) |
c5059423 | 4528 | { |
02071907 | 4529 | HOST_WIDE_INT c, lsb, shift_mask; |
c5059423 | 4530 | |
02071907 | 4531 | shift_mask = ~0; |
c5059423 AM |
4532 | shift_mask <<= INTVAL (shiftop); |
4533 | c = INTVAL (andop); | |
4534 | ||
4535 | /* Find the least signifigant one bit. */ | |
4536 | lsb = c & -c; | |
4537 | ||
4538 | /* It must be covered by the shift mask. | |
a4f6c312 | 4539 | This test also rejects c == 0. */ |
c5059423 AM |
4540 | if ((lsb & shift_mask) == 0) |
4541 | return 0; | |
4542 | ||
4543 | /* Check we have all 1's above the transition, and reject all 1's. */ | |
4544 | return c == -lsb && lsb != 1; | |
4545 | } | |
4546 | else if (GET_CODE (andop) == CONST_DOUBLE | |
4547 | && (GET_MODE (andop) == VOIDmode || GET_MODE (andop) == DImode)) | |
4548 | { | |
02071907 | 4549 | HOST_WIDE_INT low, lsb, shift_mask_low; |
c5059423 AM |
4550 | |
4551 | low = CONST_DOUBLE_LOW (andop); | |
4552 | ||
4553 | if (HOST_BITS_PER_WIDE_INT < 64) | |
4554 | { | |
02071907 | 4555 | HOST_WIDE_INT high, shift_mask_high; |
c5059423 AM |
4556 | |
4557 | high = CONST_DOUBLE_HIGH (andop); | |
4558 | ||
4559 | if (low == 0) | |
4560 | { | |
02071907 | 4561 | shift_mask_high = ~0; |
c5059423 AM |
4562 | if (INTVAL (shiftop) > 32) |
4563 | shift_mask_high <<= INTVAL (shiftop) - 32; | |
4564 | ||
4565 | lsb = high & -high; | |
4566 | ||
4567 | if ((lsb & shift_mask_high) == 0) | |
4568 | return 0; | |
4569 | ||
4570 | return high == -lsb; | |
4571 | } | |
4572 | if (high != ~0) | |
4573 | return 0; | |
4574 | } | |
4575 | ||
02071907 | 4576 | shift_mask_low = ~0; |
c5059423 AM |
4577 | shift_mask_low <<= INTVAL (shiftop); |
4578 | ||
4579 | lsb = low & -low; | |
4580 | ||
4581 | if ((lsb & shift_mask_low) == 0) | |
4582 | return 0; | |
4583 | ||
4584 | return low == -lsb && lsb != 1; | |
4585 | } | |
e2c953b6 | 4586 | else |
c5059423 | 4587 | return 0; |
9878760c | 4588 | } |
35068b43 RK |
4589 | |
4590 | /* Return 1 if REGNO (reg1) == REGNO (reg2) - 1 making them candidates | |
4591 | for lfq and stfq insns. | |
4592 | ||
4593 | Note reg1 and reg2 *must* be hard registers. To be sure we will | |
4594 | abort if we are passed pseudo registers. */ | |
4595 | ||
4596 | int | |
4597 | registers_ok_for_quad_peep (reg1, reg2) | |
4598 | rtx reg1, reg2; | |
4599 | { | |
4600 | /* We might have been passed a SUBREG. */ | |
4601 | if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG) | |
4602 | return 0; | |
4603 | ||
4604 | return (REGNO (reg1) == REGNO (reg2) - 1); | |
4605 | } | |
4606 | ||
a4f6c312 SS |
4607 | /* Return 1 if addr1 and addr2 are suitable for lfq or stfq insn. |
4608 | addr1 and addr2 must be in consecutive memory locations | |
4609 | (addr2 == addr1 + 8). */ | |
35068b43 RK |
4610 | |
4611 | int | |
4612 | addrs_ok_for_quad_peep (addr1, addr2) | |
592696dd SS |
4613 | rtx addr1; |
4614 | rtx addr2; | |
35068b43 | 4615 | { |
e2c953b6 | 4616 | unsigned int reg1; |
35068b43 RK |
4617 | int offset1; |
4618 | ||
4619 | /* Extract an offset (if used) from the first addr. */ | |
4620 | if (GET_CODE (addr1) == PLUS) | |
4621 | { | |
4622 | /* If not a REG, return zero. */ | |
4623 | if (GET_CODE (XEXP (addr1, 0)) != REG) | |
4624 | return 0; | |
4625 | else | |
4626 | { | |
4627 | reg1 = REGNO (XEXP (addr1, 0)); | |
4628 | /* The offset must be constant! */ | |
4629 | if (GET_CODE (XEXP (addr1, 1)) != CONST_INT) | |
4630 | return 0; | |
4631 | offset1 = INTVAL (XEXP (addr1, 1)); | |
4632 | } | |
4633 | } | |
4634 | else if (GET_CODE (addr1) != REG) | |
4635 | return 0; | |
4636 | else | |
4637 | { | |
4638 | reg1 = REGNO (addr1); | |
4639 | /* This was a simple (mem (reg)) expression. Offset is 0. */ | |
4640 | offset1 = 0; | |
4641 | } | |
4642 | ||
acad7ed3 | 4643 | /* Make sure the second address is a (mem (plus (reg) (const_int))). */ |
35068b43 RK |
4644 | if (GET_CODE (addr2) != PLUS) |
4645 | return 0; | |
4646 | ||
4647 | if (GET_CODE (XEXP (addr2, 0)) != REG | |
4648 | || GET_CODE (XEXP (addr2, 1)) != CONST_INT) | |
4649 | return 0; | |
4650 | ||
4651 | if (reg1 != REGNO (XEXP (addr2, 0))) | |
4652 | return 0; | |
4653 | ||
4654 | /* The offset for the second addr must be 8 more than the first addr. */ | |
4655 | if (INTVAL (XEXP (addr2, 1)) != offset1 + 8) | |
4656 | return 0; | |
4657 | ||
4658 | /* All the tests passed. addr1 and addr2 are valid for lfq or stfq | |
4659 | instructions. */ | |
4660 | return 1; | |
4661 | } | |
9878760c RK |
4662 | \f |
4663 | /* Return the register class of a scratch register needed to copy IN into | |
4664 | or out of a register in CLASS in MODE. If it can be done directly, | |
4665 | NO_REGS is returned. */ | |
4666 | ||
4667 | enum reg_class | |
4668 | secondary_reload_class (class, mode, in) | |
4669 | enum reg_class class; | |
296b8152 | 4670 | enum machine_mode mode ATTRIBUTE_UNUSED; |
9878760c RK |
4671 | rtx in; |
4672 | { | |
5accd822 | 4673 | int regno; |
9878760c | 4674 | |
46fad5b7 DJ |
4675 | if (TARGET_ELF || (DEFAULT_ABI == ABI_DARWIN && flag_pic)) |
4676 | { | |
4677 | /* We cannot copy a symbolic operand directly into anything | |
4678 | other than BASE_REGS for TARGET_ELF. So indicate that a | |
4679 | register from BASE_REGS is needed as an intermediate | |
4680 | register. | |
4681 | ||
4682 | On Darwin, pic addresses require a load from memory, which | |
4683 | needs a base register. */ | |
4684 | if (class != BASE_REGS | |
4685 | && (GET_CODE (in) == SYMBOL_REF | |
4686 | || GET_CODE (in) == HIGH | |
4687 | || GET_CODE (in) == LABEL_REF | |
4688 | || GET_CODE (in) == CONST)) | |
4689 | return BASE_REGS; | |
4690 | } | |
e7b7998a | 4691 | |
5accd822 DE |
4692 | if (GET_CODE (in) == REG) |
4693 | { | |
4694 | regno = REGNO (in); | |
4695 | if (regno >= FIRST_PSEUDO_REGISTER) | |
4696 | { | |
4697 | regno = true_regnum (in); | |
4698 | if (regno >= FIRST_PSEUDO_REGISTER) | |
4699 | regno = -1; | |
4700 | } | |
4701 | } | |
4702 | else if (GET_CODE (in) == SUBREG) | |
4703 | { | |
4704 | regno = true_regnum (in); | |
4705 | if (regno >= FIRST_PSEUDO_REGISTER) | |
4706 | regno = -1; | |
4707 | } | |
4708 | else | |
4709 | regno = -1; | |
4710 | ||
9878760c RK |
4711 | /* We can place anything into GENERAL_REGS and can put GENERAL_REGS |
4712 | into anything. */ | |
4713 | if (class == GENERAL_REGS || class == BASE_REGS | |
4714 | || (regno >= 0 && INT_REGNO_P (regno))) | |
4715 | return NO_REGS; | |
4716 | ||
4717 | /* Constants, memory, and FP registers can go into FP registers. */ | |
4718 | if ((regno == -1 || FP_REGNO_P (regno)) | |
4719 | && (class == FLOAT_REGS || class == NON_SPECIAL_REGS)) | |
4720 | return NO_REGS; | |
4721 | ||
0ac081f6 AH |
4722 | /* Memory, and AltiVec registers can go into AltiVec registers. */ |
4723 | if ((regno == -1 || ALTIVEC_REGNO_P (regno)) | |
4724 | && class == ALTIVEC_REGS) | |
4725 | return NO_REGS; | |
4726 | ||
9878760c RK |
4727 | /* We can copy among the CR registers. */ |
4728 | if ((class == CR_REGS || class == CR0_REGS) | |
4729 | && regno >= 0 && CR_REGNO_P (regno)) | |
4730 | return NO_REGS; | |
4731 | ||
4732 | /* Otherwise, we need GENERAL_REGS. */ | |
4733 | return GENERAL_REGS; | |
4734 | } | |
4735 | \f | |
4736 | /* Given a comparison operation, return the bit number in CCR to test. We | |
4737 | know this is a valid comparison. | |
4738 | ||
4739 | SCC_P is 1 if this is for an scc. That means that %D will have been | |
4740 | used instead of %C, so the bits will be in different places. | |
4741 | ||
b4ac57ab | 4742 | Return -1 if OP isn't a valid comparison for some reason. */ |
9878760c RK |
4743 | |
4744 | int | |
4745 | ccr_bit (op, scc_p) | |
592696dd | 4746 | rtx op; |
9878760c RK |
4747 | int scc_p; |
4748 | { | |
4749 | enum rtx_code code = GET_CODE (op); | |
4750 | enum machine_mode cc_mode; | |
4751 | int cc_regnum; | |
4752 | int base_bit; | |
9ebbca7d | 4753 | rtx reg; |
9878760c RK |
4754 | |
4755 | if (GET_RTX_CLASS (code) != '<') | |
4756 | return -1; | |
4757 | ||
9ebbca7d GK |
4758 | reg = XEXP (op, 0); |
4759 | ||
4760 | if (GET_CODE (reg) != REG | |
4761 | || ! CR_REGNO_P (REGNO (reg))) | |
4762 | abort (); | |
4763 | ||
4764 | cc_mode = GET_MODE (reg); | |
4765 | cc_regnum = REGNO (reg); | |
4766 | base_bit = 4 * (cc_regnum - CR0_REGNO); | |
9878760c | 4767 | |
39a10a29 | 4768 | validate_condition_mode (code, cc_mode); |
c5defebb | 4769 | |
9878760c RK |
4770 | switch (code) |
4771 | { | |
4772 | case NE: | |
4773 | return scc_p ? base_bit + 3 : base_bit + 2; | |
4774 | case EQ: | |
4775 | return base_bit + 2; | |
1c882ea4 | 4776 | case GT: case GTU: case UNLE: |
9878760c | 4777 | return base_bit + 1; |
1c882ea4 | 4778 | case LT: case LTU: case UNGE: |
9878760c | 4779 | return base_bit; |
1c882ea4 GK |
4780 | case ORDERED: case UNORDERED: |
4781 | return base_bit + 3; | |
9878760c RK |
4782 | |
4783 | case GE: case GEU: | |
39a10a29 | 4784 | /* If scc, we will have done a cror to put the bit in the |
9878760c RK |
4785 | unordered position. So test that bit. For integer, this is ! LT |
4786 | unless this is an scc insn. */ | |
39a10a29 | 4787 | return scc_p ? base_bit + 3 : base_bit; |
9878760c RK |
4788 | |
4789 | case LE: case LEU: | |
39a10a29 | 4790 | return scc_p ? base_bit + 3 : base_bit + 1; |
1c882ea4 | 4791 | |
9878760c RK |
4792 | default: |
4793 | abort (); | |
4794 | } | |
4795 | } | |
1ff7789b | 4796 | \f |
8d30c4ee | 4797 | /* Return the GOT register. */ |
1ff7789b MM |
4798 | |
4799 | struct rtx_def * | |
4800 | rs6000_got_register (value) | |
5f59ecb7 | 4801 | rtx value ATTRIBUTE_UNUSED; |
1ff7789b | 4802 | { |
a4f6c312 SS |
4803 | /* The second flow pass currently (June 1999) can't update |
4804 | regs_ever_live without disturbing other parts of the compiler, so | |
4805 | update it here to make the prolog/epilogue code happy. */ | |
3cb999d8 | 4806 | if (no_new_pseudos && ! regs_ever_live[PIC_OFFSET_TABLE_REGNUM]) |
8d30c4ee | 4807 | regs_ever_live[PIC_OFFSET_TABLE_REGNUM] = 1; |
1ff7789b | 4808 | |
8d30c4ee | 4809 | current_function_uses_pic_offset_table = 1; |
3cb999d8 | 4810 | |
1ff7789b MM |
4811 | return pic_offset_table_rtx; |
4812 | } | |
a7df97e6 | 4813 | \f |
71f123ca | 4814 | /* Functions to init, mark and free struct machine_function. |
a7df97e6 MM |
4815 | These will be called, via pointer variables, |
4816 | from push_function_context and pop_function_context. */ | |
4817 | ||
00dba523 NC |
4818 | static void |
4819 | rs6000_init_machine_status (p) | |
a7df97e6 MM |
4820 | struct function *p; |
4821 | { | |
71f123ca FS |
4822 | p->machine = (machine_function *) xcalloc (1, sizeof (machine_function)); |
4823 | } | |
a7df97e6 | 4824 | |
00dba523 NC |
4825 | static void |
4826 | rs6000_free_machine_status (p) | |
a7df97e6 MM |
4827 | struct function *p; |
4828 | { | |
00dba523 NC |
4829 | if (p->machine == NULL) |
4830 | return; | |
a7df97e6 | 4831 | |
00dba523 NC |
4832 | free (p->machine); |
4833 | p->machine = NULL; | |
a7df97e6 MM |
4834 | } |
4835 | ||
9878760c RK |
4836 | \f |
4837 | /* Print an operand. Recognize special options, documented below. */ | |
4838 | ||
38c1f2d7 | 4839 | #if TARGET_ELF |
d9407988 | 4840 | #define SMALL_DATA_RELOC ((rs6000_sdata == SDATA_EABI) ? "sda21" : "sdarel") |
8fbd2dc7 | 4841 | #define SMALL_DATA_REG ((rs6000_sdata == SDATA_EABI) ? 0 : 13) |
ba5e43aa MM |
4842 | #else |
4843 | #define SMALL_DATA_RELOC "sda21" | |
8fbd2dc7 | 4844 | #define SMALL_DATA_REG 0 |
ba5e43aa MM |
4845 | #endif |
4846 | ||
9878760c RK |
4847 | void |
4848 | print_operand (file, x, code) | |
4849 | FILE *file; | |
4850 | rtx x; | |
9ebbca7d | 4851 | int code; |
9878760c RK |
4852 | { |
4853 | int i; | |
a260abc9 | 4854 | HOST_WIDE_INT val; |
9878760c RK |
4855 | |
4856 | /* These macros test for integers and extract the low-order bits. */ | |
4857 | #define INT_P(X) \ | |
4858 | ((GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST_DOUBLE) \ | |
4859 | && GET_MODE (X) == VOIDmode) | |
4860 | ||
4861 | #define INT_LOWPART(X) \ | |
4862 | (GET_CODE (X) == CONST_INT ? INTVAL (X) : CONST_DOUBLE_LOW (X)) | |
4863 | ||
4864 | switch (code) | |
4865 | { | |
a8b3aeda | 4866 | case '.': |
a85d226b RK |
4867 | /* Write out an instruction after the call which may be replaced |
4868 | with glue code by the loader. This depends on the AIX version. */ | |
4869 | asm_fprintf (file, RS6000_CALL_GLUE); | |
a8b3aeda RK |
4870 | return; |
4871 | ||
81eace42 GK |
4872 | /* %a is output_address. */ |
4873 | ||
9854d9ed RK |
4874 | case 'A': |
4875 | /* If X is a constant integer whose low-order 5 bits are zero, | |
4876 | write 'l'. Otherwise, write 'r'. This is a kludge to fix a bug | |
76229ac8 | 4877 | in the AIX assembler where "sri" with a zero shift count |
9854d9ed RK |
4878 | write a trash instruction. */ |
4879 | if (GET_CODE (x) == CONST_INT && (INTVAL (x) & 31) == 0) | |
76229ac8 | 4880 | putc ('l', file); |
9854d9ed | 4881 | else |
76229ac8 | 4882 | putc ('r', file); |
9854d9ed RK |
4883 | return; |
4884 | ||
4885 | case 'b': | |
e2c953b6 DE |
4886 | /* If constant, low-order 16 bits of constant, unsigned. |
4887 | Otherwise, write normally. */ | |
4888 | if (INT_P (x)) | |
4889 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 0xffff); | |
4890 | else | |
4891 | print_operand (file, x, 0); | |
cad12a8d RK |
4892 | return; |
4893 | ||
a260abc9 DE |
4894 | case 'B': |
4895 | /* If the low-order bit is zero, write 'r'; otherwise, write 'l' | |
4896 | for 64-bit mask direction. */ | |
296b8152 | 4897 | putc (((INT_LOWPART(x) & 1) == 0 ? 'r' : 'l'), file); |
a238cd8b | 4898 | return; |
a260abc9 | 4899 | |
81eace42 GK |
4900 | /* %c is output_addr_const if a CONSTANT_ADDRESS_P, otherwise |
4901 | output_operand. */ | |
4902 | ||
9854d9ed | 4903 | case 'D': |
39a10a29 GK |
4904 | /* There used to be a comment for 'C' reading "This is an |
4905 | optional cror needed for certain floating-point | |
4906 | comparisons. Otherwise write nothing." */ | |
4907 | ||
9854d9ed RK |
4908 | /* Similar, except that this is for an scc, so we must be able to |
4909 | encode the test in a single bit that is one. We do the above | |
4910 | for any LE, GE, GEU, or LEU and invert the bit for NE. */ | |
4911 | if (GET_CODE (x) == LE || GET_CODE (x) == GE | |
4912 | || GET_CODE (x) == LEU || GET_CODE (x) == GEU) | |
4913 | { | |
9ebbca7d | 4914 | int base_bit = 4 * (REGNO (XEXP (x, 0)) - CR0_REGNO); |
9854d9ed RK |
4915 | |
4916 | fprintf (file, "cror %d,%d,%d\n\t", base_bit + 3, | |
4917 | base_bit + 2, | |
4918 | base_bit + (GET_CODE (x) == GE || GET_CODE (x) == GEU)); | |
4919 | } | |
4920 | ||
4921 | else if (GET_CODE (x) == NE) | |
4922 | { | |
9ebbca7d | 4923 | int base_bit = 4 * (REGNO (XEXP (x, 0)) - CR0_REGNO); |
9854d9ed RK |
4924 | |
4925 | fprintf (file, "crnor %d,%d,%d\n\t", base_bit + 3, | |
4926 | base_bit + 2, base_bit + 2); | |
4927 | } | |
4928 | return; | |
4929 | ||
4930 | case 'E': | |
39a10a29 | 4931 | /* X is a CR register. Print the number of the EQ bit of the CR */ |
9854d9ed RK |
4932 | if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x))) |
4933 | output_operand_lossage ("invalid %%E value"); | |
78fbdbf7 | 4934 | else |
39a10a29 | 4935 | fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO) + 2); |
a85d226b | 4936 | return; |
9854d9ed RK |
4937 | |
4938 | case 'f': | |
4939 | /* X is a CR register. Print the shift count needed to move it | |
4940 | to the high-order four bits. */ | |
4941 | if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x))) | |
4942 | output_operand_lossage ("invalid %%f value"); | |
4943 | else | |
9ebbca7d | 4944 | fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO)); |
9854d9ed RK |
4945 | return; |
4946 | ||
4947 | case 'F': | |
4948 | /* Similar, but print the count for the rotate in the opposite | |
4949 | direction. */ | |
4950 | if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x))) | |
4951 | output_operand_lossage ("invalid %%F value"); | |
4952 | else | |
9ebbca7d | 4953 | fprintf (file, "%d", 32 - 4 * (REGNO (x) - CR0_REGNO)); |
9854d9ed RK |
4954 | return; |
4955 | ||
4956 | case 'G': | |
4957 | /* X is a constant integer. If it is negative, print "m", | |
4958 | otherwise print "z". This is to make a aze or ame insn. */ | |
4959 | if (GET_CODE (x) != CONST_INT) | |
4960 | output_operand_lossage ("invalid %%G value"); | |
4961 | else if (INTVAL (x) >= 0) | |
76229ac8 | 4962 | putc ('z', file); |
9854d9ed | 4963 | else |
76229ac8 | 4964 | putc ('m', file); |
9854d9ed | 4965 | return; |
e2c953b6 | 4966 | |
9878760c | 4967 | case 'h': |
a4f6c312 SS |
4968 | /* If constant, output low-order five bits. Otherwise, write |
4969 | normally. */ | |
9878760c | 4970 | if (INT_P (x)) |
5f59ecb7 | 4971 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 31); |
9878760c RK |
4972 | else |
4973 | print_operand (file, x, 0); | |
4974 | return; | |
4975 | ||
64305719 | 4976 | case 'H': |
a4f6c312 SS |
4977 | /* If constant, output low-order six bits. Otherwise, write |
4978 | normally. */ | |
64305719 | 4979 | if (INT_P (x)) |
5f59ecb7 | 4980 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 63); |
64305719 DE |
4981 | else |
4982 | print_operand (file, x, 0); | |
4983 | return; | |
4984 | ||
9854d9ed RK |
4985 | case 'I': |
4986 | /* Print `i' if this is a constant, else nothing. */ | |
9878760c | 4987 | if (INT_P (x)) |
76229ac8 | 4988 | putc ('i', file); |
9878760c RK |
4989 | return; |
4990 | ||
9854d9ed RK |
4991 | case 'j': |
4992 | /* Write the bit number in CCR for jump. */ | |
4993 | i = ccr_bit (x, 0); | |
4994 | if (i == -1) | |
4995 | output_operand_lossage ("invalid %%j code"); | |
9878760c | 4996 | else |
9854d9ed | 4997 | fprintf (file, "%d", i); |
9878760c RK |
4998 | return; |
4999 | ||
9854d9ed RK |
5000 | case 'J': |
5001 | /* Similar, but add one for shift count in rlinm for scc and pass | |
5002 | scc flag to `ccr_bit'. */ | |
5003 | i = ccr_bit (x, 1); | |
5004 | if (i == -1) | |
5005 | output_operand_lossage ("invalid %%J code"); | |
5006 | else | |
a0466a68 RK |
5007 | /* If we want bit 31, write a shift count of zero, not 32. */ |
5008 | fprintf (file, "%d", i == 31 ? 0 : i + 1); | |
9878760c RK |
5009 | return; |
5010 | ||
9854d9ed RK |
5011 | case 'k': |
5012 | /* X must be a constant. Write the 1's complement of the | |
5013 | constant. */ | |
9878760c | 5014 | if (! INT_P (x)) |
9854d9ed | 5015 | output_operand_lossage ("invalid %%k value"); |
e2c953b6 DE |
5016 | else |
5017 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, ~ INT_LOWPART (x)); | |
9878760c RK |
5018 | return; |
5019 | ||
81eace42 | 5020 | case 'K': |
9ebbca7d GK |
5021 | /* X must be a symbolic constant on ELF. Write an |
5022 | expression suitable for an 'addi' that adds in the low 16 | |
5023 | bits of the MEM. */ | |
5024 | if (GET_CODE (x) != CONST) | |
5025 | { | |
5026 | print_operand_address (file, x); | |
5027 | fputs ("@l", file); | |
5028 | } | |
5029 | else | |
5030 | { | |
5031 | if (GET_CODE (XEXP (x, 0)) != PLUS | |
5032 | || (GET_CODE (XEXP (XEXP (x, 0), 0)) != SYMBOL_REF | |
5033 | && GET_CODE (XEXP (XEXP (x, 0), 0)) != LABEL_REF) | |
5034 | || GET_CODE (XEXP (XEXP (x, 0), 1)) != CONST_INT) | |
53cd5d6c | 5035 | output_operand_lossage ("invalid %%K value"); |
9ebbca7d GK |
5036 | print_operand_address (file, XEXP (XEXP (x, 0), 0)); |
5037 | fputs ("@l", file); | |
5038 | print_operand (file, XEXP (XEXP (x, 0), 1), 0); | |
5039 | } | |
81eace42 GK |
5040 | return; |
5041 | ||
5042 | /* %l is output_asm_label. */ | |
9ebbca7d | 5043 | |
9854d9ed RK |
5044 | case 'L': |
5045 | /* Write second word of DImode or DFmode reference. Works on register | |
5046 | or non-indexed memory only. */ | |
5047 | if (GET_CODE (x) == REG) | |
5ebfb2ba | 5048 | fprintf (file, "%s", reg_names[REGNO (x) + 1]); |
9854d9ed RK |
5049 | else if (GET_CODE (x) == MEM) |
5050 | { | |
5051 | /* Handle possible auto-increment. Since it is pre-increment and | |
1427100a | 5052 | we have already done it, we can just use an offset of word. */ |
9854d9ed RK |
5053 | if (GET_CODE (XEXP (x, 0)) == PRE_INC |
5054 | || GET_CODE (XEXP (x, 0)) == PRE_DEC) | |
ed8908e7 RK |
5055 | output_address (plus_constant (XEXP (XEXP (x, 0), 0), |
5056 | UNITS_PER_WORD)); | |
9854d9ed | 5057 | else |
d7624dc0 RK |
5058 | output_address (XEXP (adjust_address_nv (x, SImode, |
5059 | UNITS_PER_WORD), | |
5060 | 0)); | |
ed8908e7 | 5061 | |
ba5e43aa | 5062 | if (small_data_operand (x, GET_MODE (x))) |
8fbd2dc7 MM |
5063 | fprintf (file, "@%s(%s)", SMALL_DATA_RELOC, |
5064 | reg_names[SMALL_DATA_REG]); | |
9854d9ed | 5065 | } |
9878760c | 5066 | return; |
9854d9ed | 5067 | |
9878760c RK |
5068 | case 'm': |
5069 | /* MB value for a mask operand. */ | |
5070 | if (! mask_operand (x, VOIDmode)) | |
5071 | output_operand_lossage ("invalid %%m value"); | |
5072 | ||
5073 | val = INT_LOWPART (x); | |
5074 | ||
5075 | /* If the high bit is set and the low bit is not, the value is zero. | |
5076 | If the high bit is zero, the value is the first 1 bit we find from | |
5077 | the left. */ | |
0858c623 | 5078 | if ((val & 0x80000000) && ((val & 1) == 0)) |
9878760c | 5079 | { |
19d2d16f | 5080 | putc ('0', file); |
9878760c RK |
5081 | return; |
5082 | } | |
0858c623 | 5083 | else if ((val & 0x80000000) == 0) |
9878760c RK |
5084 | { |
5085 | for (i = 1; i < 32; i++) | |
0858c623 | 5086 | if ((val <<= 1) & 0x80000000) |
9878760c RK |
5087 | break; |
5088 | fprintf (file, "%d", i); | |
5089 | return; | |
5090 | } | |
5091 | ||
5092 | /* Otherwise, look for the first 0 bit from the right. The result is its | |
5093 | number plus 1. We know the low-order bit is one. */ | |
5094 | for (i = 0; i < 32; i++) | |
5095 | if (((val >>= 1) & 1) == 0) | |
5096 | break; | |
5097 | ||
a260abc9 | 5098 | /* If we ended in ...01, i would be 0. The correct value is 31, so |
9878760c RK |
5099 | we want 31 - i. */ |
5100 | fprintf (file, "%d", 31 - i); | |
5101 | return; | |
5102 | ||
5103 | case 'M': | |
5104 | /* ME value for a mask operand. */ | |
5105 | if (! mask_operand (x, VOIDmode)) | |
a260abc9 | 5106 | output_operand_lossage ("invalid %%M value"); |
9878760c RK |
5107 | |
5108 | val = INT_LOWPART (x); | |
5109 | ||
5110 | /* If the low bit is set and the high bit is not, the value is 31. | |
5111 | If the low bit is zero, the value is the first 1 bit we find from | |
5112 | the right. */ | |
0858c623 | 5113 | if ((val & 1) && ((val & 0x80000000) == 0)) |
9878760c | 5114 | { |
76229ac8 | 5115 | fputs ("31", file); |
9878760c RK |
5116 | return; |
5117 | } | |
5118 | else if ((val & 1) == 0) | |
5119 | { | |
5120 | for (i = 0; i < 32; i++) | |
5121 | if ((val >>= 1) & 1) | |
5122 | break; | |
5123 | ||
a260abc9 | 5124 | /* If we had ....10, i would be 0. The result should be |
9878760c RK |
5125 | 30, so we need 30 - i. */ |
5126 | fprintf (file, "%d", 30 - i); | |
5127 | return; | |
5128 | } | |
5129 | ||
5130 | /* Otherwise, look for the first 0 bit from the left. The result is its | |
5131 | number minus 1. We know the high-order bit is one. */ | |
5132 | for (i = 0; i < 32; i++) | |
0858c623 | 5133 | if (((val <<= 1) & 0x80000000) == 0) |
9878760c RK |
5134 | break; |
5135 | ||
5136 | fprintf (file, "%d", i); | |
5137 | return; | |
5138 | ||
81eace42 GK |
5139 | /* %n outputs the negative of its operand. */ |
5140 | ||
9878760c RK |
5141 | case 'N': |
5142 | /* Write the number of elements in the vector times 4. */ | |
5143 | if (GET_CODE (x) != PARALLEL) | |
5144 | output_operand_lossage ("invalid %%N value"); | |
e2c953b6 DE |
5145 | else |
5146 | fprintf (file, "%d", XVECLEN (x, 0) * 4); | |
9878760c RK |
5147 | return; |
5148 | ||
5149 | case 'O': | |
5150 | /* Similar, but subtract 1 first. */ | |
5151 | if (GET_CODE (x) != PARALLEL) | |
1427100a | 5152 | output_operand_lossage ("invalid %%O value"); |
e2c953b6 DE |
5153 | else |
5154 | fprintf (file, "%d", (XVECLEN (x, 0) - 1) * 4); | |
9878760c RK |
5155 | return; |
5156 | ||
9854d9ed RK |
5157 | case 'p': |
5158 | /* X is a CONST_INT that is a power of two. Output the logarithm. */ | |
5159 | if (! INT_P (x) | |
2bfcf297 | 5160 | || INT_LOWPART (x) < 0 |
9854d9ed RK |
5161 | || (i = exact_log2 (INT_LOWPART (x))) < 0) |
5162 | output_operand_lossage ("invalid %%p value"); | |
e2c953b6 DE |
5163 | else |
5164 | fprintf (file, "%d", i); | |
9854d9ed RK |
5165 | return; |
5166 | ||
9878760c RK |
5167 | case 'P': |
5168 | /* The operand must be an indirect memory reference. The result | |
a4f6c312 | 5169 | is the register number. */ |
9878760c RK |
5170 | if (GET_CODE (x) != MEM || GET_CODE (XEXP (x, 0)) != REG |
5171 | || REGNO (XEXP (x, 0)) >= 32) | |
5172 | output_operand_lossage ("invalid %%P value"); | |
e2c953b6 DE |
5173 | else |
5174 | fprintf (file, "%d", REGNO (XEXP (x, 0))); | |
9878760c RK |
5175 | return; |
5176 | ||
dfbdccdb GK |
5177 | case 'q': |
5178 | /* This outputs the logical code corresponding to a boolean | |
5179 | expression. The expression may have one or both operands | |
39a10a29 GK |
5180 | negated (if one, only the first one). For condition register |
5181 | logical operations, it will also treat the negated | |
5182 | CR codes as NOTs, but not handle NOTs of them. */ | |
dfbdccdb | 5183 | { |
63bc1d05 | 5184 | const char *const *t = 0; |
dfbdccdb GK |
5185 | const char *s; |
5186 | enum rtx_code code = GET_CODE (x); | |
5187 | static const char * const tbl[3][3] = { | |
5188 | { "and", "andc", "nor" }, | |
5189 | { "or", "orc", "nand" }, | |
5190 | { "xor", "eqv", "xor" } }; | |
5191 | ||
5192 | if (code == AND) | |
5193 | t = tbl[0]; | |
5194 | else if (code == IOR) | |
5195 | t = tbl[1]; | |
5196 | else if (code == XOR) | |
5197 | t = tbl[2]; | |
5198 | else | |
5199 | output_operand_lossage ("invalid %%q value"); | |
5200 | ||
5201 | if (GET_CODE (XEXP (x, 0)) != NOT) | |
5202 | s = t[0]; | |
5203 | else | |
5204 | { | |
5205 | if (GET_CODE (XEXP (x, 1)) == NOT) | |
5206 | s = t[2]; | |
5207 | else | |
5208 | s = t[1]; | |
5209 | } | |
5210 | ||
5211 | fputs (s, file); | |
5212 | } | |
5213 | return; | |
5214 | ||
9854d9ed RK |
5215 | case 'R': |
5216 | /* X is a CR register. Print the mask for `mtcrf'. */ | |
5217 | if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x))) | |
5218 | output_operand_lossage ("invalid %%R value"); | |
5219 | else | |
9ebbca7d | 5220 | fprintf (file, "%d", 128 >> (REGNO (x) - CR0_REGNO)); |
9878760c | 5221 | return; |
9854d9ed RK |
5222 | |
5223 | case 's': | |
5224 | /* Low 5 bits of 32 - value */ | |
5225 | if (! INT_P (x)) | |
5226 | output_operand_lossage ("invalid %%s value"); | |
e2c953b6 DE |
5227 | else |
5228 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, (32 - INT_LOWPART (x)) & 31); | |
9878760c | 5229 | return; |
9854d9ed | 5230 | |
a260abc9 DE |
5231 | case 'S': |
5232 | /* PowerPC64 mask position. All 0's and all 1's are excluded. | |
5233 | CONST_INT 32-bit mask is considered sign-extended so any | |
5234 | transition must occur within the CONST_INT, not on the boundary. */ | |
5235 | if (! mask64_operand (x, VOIDmode)) | |
5236 | output_operand_lossage ("invalid %%S value"); | |
5237 | ||
5238 | val = INT_LOWPART (x); | |
5239 | ||
5240 | if (val & 1) /* Clear Left */ | |
5241 | { | |
a238cd8b DE |
5242 | for (i = 0; i < HOST_BITS_PER_WIDE_INT; i++) |
5243 | if (!((val >>= 1) & 1)) | |
5244 | break; | |
a260abc9 | 5245 | |
a238cd8b DE |
5246 | #if HOST_BITS_PER_WIDE_INT == 32 |
5247 | if (GET_CODE (x) == CONST_DOUBLE && i == 32) | |
5248 | { | |
5249 | val = CONST_DOUBLE_HIGH (x); | |
5250 | ||
5251 | if (val == 0) | |
5252 | --i; | |
5253 | else | |
5254 | for (i = 32; i < 64; i++) | |
5255 | if (!((val >>= 1) & 1)) | |
5256 | break; | |
5257 | } | |
a260abc9 | 5258 | #endif |
a238cd8b DE |
5259 | /* i = index of last set bit from right |
5260 | mask begins at 63 - i from left */ | |
5261 | if (i > 63) | |
5262 | output_operand_lossage ("%%S computed all 1's mask"); | |
cccf3bdc | 5263 | |
a260abc9 DE |
5264 | fprintf (file, "%d", 63 - i); |
5265 | return; | |
5266 | } | |
5267 | else /* Clear Right */ | |
5268 | { | |
a238cd8b DE |
5269 | for (i = 0; i < HOST_BITS_PER_WIDE_INT; i++) |
5270 | if ((val >>= 1) & 1) | |
5271 | break; | |
a260abc9 | 5272 | |
a238cd8b | 5273 | #if HOST_BITS_PER_WIDE_INT == 32 |
a260abc9 DE |
5274 | if (GET_CODE (x) == CONST_DOUBLE && i == 32) |
5275 | { | |
a238cd8b | 5276 | val = CONST_DOUBLE_HIGH (x); |
a260abc9 | 5277 | |
a238cd8b | 5278 | if (val == (HOST_WIDE_INT) -1) |
a260abc9 | 5279 | --i; |
a260abc9 | 5280 | else |
a238cd8b DE |
5281 | for (i = 32; i < 64; i++) |
5282 | if ((val >>= 1) & 1) | |
a260abc9 DE |
5283 | break; |
5284 | } | |
5285 | #endif | |
a238cd8b DE |
5286 | /* i = index of last clear bit from right |
5287 | mask ends at 62 - i from left */ | |
5288 | if (i > 62) | |
5289 | output_operand_lossage ("%%S computed all 0's mask"); | |
cccf3bdc | 5290 | |
a238cd8b | 5291 | fprintf (file, "%d", 62 - i); |
a260abc9 DE |
5292 | return; |
5293 | } | |
5294 | ||
cccf3bdc DE |
5295 | case 'T': |
5296 | /* Print the symbolic name of a branch target register. */ | |
5297 | if (GET_CODE (x) != REG || (REGNO (x) != LINK_REGISTER_REGNUM | |
5298 | && REGNO (x) != COUNT_REGISTER_REGNUM)) | |
5299 | output_operand_lossage ("invalid %%T value"); | |
e2c953b6 | 5300 | else if (REGNO (x) == LINK_REGISTER_REGNUM) |
cccf3bdc DE |
5301 | fputs (TARGET_NEW_MNEMONICS ? "lr" : "r", file); |
5302 | else | |
5303 | fputs ("ctr", file); | |
5304 | return; | |
5305 | ||
9854d9ed | 5306 | case 'u': |
802a0058 | 5307 | /* High-order 16 bits of constant for use in unsigned operand. */ |
9854d9ed RK |
5308 | if (! INT_P (x)) |
5309 | output_operand_lossage ("invalid %%u value"); | |
e2c953b6 DE |
5310 | else |
5311 | fprintf (file, HOST_WIDE_INT_PRINT_HEX, | |
5312 | (INT_LOWPART (x) >> 16) & 0xffff); | |
9878760c RK |
5313 | return; |
5314 | ||
802a0058 MM |
5315 | case 'v': |
5316 | /* High-order 16 bits of constant for use in signed operand. */ | |
5317 | if (! INT_P (x)) | |
5318 | output_operand_lossage ("invalid %%v value"); | |
e2c953b6 | 5319 | else |
134c32f6 DE |
5320 | fprintf (file, HOST_WIDE_INT_PRINT_HEX, |
5321 | (INT_LOWPART (x) >> 16) & 0xffff); | |
5322 | return; | |
802a0058 | 5323 | |
9854d9ed RK |
5324 | case 'U': |
5325 | /* Print `u' if this has an auto-increment or auto-decrement. */ | |
5326 | if (GET_CODE (x) == MEM | |
5327 | && (GET_CODE (XEXP (x, 0)) == PRE_INC | |
5328 | || GET_CODE (XEXP (x, 0)) == PRE_DEC)) | |
76229ac8 | 5329 | putc ('u', file); |
9854d9ed | 5330 | return; |
9878760c | 5331 | |
e0cd0770 JC |
5332 | case 'V': |
5333 | /* Print the trap code for this operand. */ | |
5334 | switch (GET_CODE (x)) | |
5335 | { | |
5336 | case EQ: | |
5337 | fputs ("eq", file); /* 4 */ | |
5338 | break; | |
5339 | case NE: | |
5340 | fputs ("ne", file); /* 24 */ | |
5341 | break; | |
5342 | case LT: | |
5343 | fputs ("lt", file); /* 16 */ | |
5344 | break; | |
5345 | case LE: | |
5346 | fputs ("le", file); /* 20 */ | |
5347 | break; | |
5348 | case GT: | |
5349 | fputs ("gt", file); /* 8 */ | |
5350 | break; | |
5351 | case GE: | |
5352 | fputs ("ge", file); /* 12 */ | |
5353 | break; | |
5354 | case LTU: | |
5355 | fputs ("llt", file); /* 2 */ | |
5356 | break; | |
5357 | case LEU: | |
5358 | fputs ("lle", file); /* 6 */ | |
5359 | break; | |
5360 | case GTU: | |
5361 | fputs ("lgt", file); /* 1 */ | |
5362 | break; | |
5363 | case GEU: | |
5364 | fputs ("lge", file); /* 5 */ | |
5365 | break; | |
5366 | default: | |
5367 | abort (); | |
5368 | } | |
5369 | break; | |
5370 | ||
9854d9ed RK |
5371 | case 'w': |
5372 | /* If constant, low-order 16 bits of constant, signed. Otherwise, write | |
5373 | normally. */ | |
5374 | if (INT_P (x)) | |
5f59ecb7 DE |
5375 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, |
5376 | ((INT_LOWPART (x) & 0xffff) ^ 0x8000) - 0x8000); | |
9854d9ed RK |
5377 | else |
5378 | print_operand (file, x, 0); | |
9878760c RK |
5379 | return; |
5380 | ||
9854d9ed | 5381 | case 'W': |
e2c953b6 | 5382 | /* MB value for a PowerPC64 rldic operand. */ |
e2c953b6 DE |
5383 | val = (GET_CODE (x) == CONST_INT |
5384 | ? INTVAL (x) : CONST_DOUBLE_HIGH (x)); | |
5385 | ||
5386 | if (val < 0) | |
5387 | i = -1; | |
9854d9ed | 5388 | else |
e2c953b6 DE |
5389 | for (i = 0; i < HOST_BITS_PER_WIDE_INT; i++) |
5390 | if ((val <<= 1) < 0) | |
5391 | break; | |
5392 | ||
5393 | #if HOST_BITS_PER_WIDE_INT == 32 | |
5394 | if (GET_CODE (x) == CONST_INT && i >= 0) | |
5395 | i += 32; /* zero-extend high-part was all 0's */ | |
5396 | else if (GET_CODE (x) == CONST_DOUBLE && i == 32) | |
5397 | { | |
5398 | val = CONST_DOUBLE_LOW (x); | |
5399 | ||
5400 | if (val == 0) | |
a4f6c312 | 5401 | abort (); |
e2c953b6 DE |
5402 | else if (val < 0) |
5403 | --i; | |
5404 | else | |
5405 | for ( ; i < 64; i++) | |
5406 | if ((val <<= 1) < 0) | |
5407 | break; | |
5408 | } | |
5409 | #endif | |
5410 | ||
5411 | fprintf (file, "%d", i + 1); | |
9854d9ed | 5412 | return; |
9878760c | 5413 | |
9854d9ed RK |
5414 | case 'X': |
5415 | if (GET_CODE (x) == MEM | |
258bfae2 | 5416 | && LEGITIMATE_INDEXED_ADDRESS_P (XEXP (x, 0), 0)) |
76229ac8 | 5417 | putc ('x', file); |
9854d9ed | 5418 | return; |
9878760c | 5419 | |
9854d9ed RK |
5420 | case 'Y': |
5421 | /* Like 'L', for third word of TImode */ | |
5422 | if (GET_CODE (x) == REG) | |
5ebfb2ba | 5423 | fprintf (file, "%s", reg_names[REGNO (x) + 2]); |
9854d9ed | 5424 | else if (GET_CODE (x) == MEM) |
9878760c | 5425 | { |
9854d9ed RK |
5426 | if (GET_CODE (XEXP (x, 0)) == PRE_INC |
5427 | || GET_CODE (XEXP (x, 0)) == PRE_DEC) | |
a54d04b7 | 5428 | output_address (plus_constant (XEXP (XEXP (x, 0), 0), 8)); |
9854d9ed | 5429 | else |
d7624dc0 | 5430 | output_address (XEXP (adjust_address_nv (x, SImode, 8), 0)); |
ba5e43aa | 5431 | if (small_data_operand (x, GET_MODE (x))) |
8fbd2dc7 MM |
5432 | fprintf (file, "@%s(%s)", SMALL_DATA_RELOC, |
5433 | reg_names[SMALL_DATA_REG]); | |
9878760c RK |
5434 | } |
5435 | return; | |
9854d9ed | 5436 | |
9878760c | 5437 | case 'z': |
b4ac57ab RS |
5438 | /* X is a SYMBOL_REF. Write out the name preceded by a |
5439 | period and without any trailing data in brackets. Used for function | |
4d30c363 MM |
5440 | names. If we are configured for System V (or the embedded ABI) on |
5441 | the PowerPC, do not emit the period, since those systems do not use | |
5442 | TOCs and the like. */ | |
9878760c RK |
5443 | if (GET_CODE (x) != SYMBOL_REF) |
5444 | abort (); | |
5445 | ||
b6c9286a MM |
5446 | if (XSTR (x, 0)[0] != '.') |
5447 | { | |
5448 | switch (DEFAULT_ABI) | |
5449 | { | |
5450 | default: | |
5451 | abort (); | |
5452 | ||
5453 | case ABI_AIX: | |
5454 | putc ('.', file); | |
5455 | break; | |
5456 | ||
5457 | case ABI_V4: | |
5458 | case ABI_AIX_NODESC: | |
ee890fe2 | 5459 | case ABI_DARWIN: |
b6c9286a | 5460 | break; |
b6c9286a MM |
5461 | } |
5462 | } | |
54ee9799 DE |
5463 | #if TARGET_AIX |
5464 | RS6000_OUTPUT_BASENAME (file, XSTR (x, 0)); | |
5465 | #else | |
9ebbca7d | 5466 | assemble_name (file, XSTR (x, 0)); |
54ee9799 | 5467 | #endif |
9878760c RK |
5468 | return; |
5469 | ||
9854d9ed RK |
5470 | case 'Z': |
5471 | /* Like 'L', for last word of TImode. */ | |
5472 | if (GET_CODE (x) == REG) | |
5ebfb2ba | 5473 | fprintf (file, "%s", reg_names[REGNO (x) + 3]); |
9854d9ed RK |
5474 | else if (GET_CODE (x) == MEM) |
5475 | { | |
5476 | if (GET_CODE (XEXP (x, 0)) == PRE_INC | |
5477 | || GET_CODE (XEXP (x, 0)) == PRE_DEC) | |
a54d04b7 | 5478 | output_address (plus_constant (XEXP (XEXP (x, 0), 0), 12)); |
9854d9ed | 5479 | else |
d7624dc0 | 5480 | output_address (XEXP (adjust_address_nv (x, SImode, 12), 0)); |
ba5e43aa | 5481 | if (small_data_operand (x, GET_MODE (x))) |
8fbd2dc7 MM |
5482 | fprintf (file, "@%s(%s)", SMALL_DATA_RELOC, |
5483 | reg_names[SMALL_DATA_REG]); | |
9854d9ed | 5484 | } |
5c23c401 | 5485 | return; |
0ac081f6 AH |
5486 | |
5487 | /* Print AltiVec memory operand. */ | |
5488 | case 'y': | |
5489 | { | |
5490 | rtx tmp; | |
5491 | ||
5492 | if (GET_CODE (x) != MEM) | |
5493 | abort (); | |
5494 | ||
5495 | tmp = XEXP (x, 0); | |
5496 | ||
5497 | if (GET_CODE (tmp) == REG) | |
5498 | fprintf (file, "0, %s", reg_names[REGNO (tmp)]); | |
5499 | else if (GET_CODE (tmp) == PLUS && GET_CODE (XEXP (tmp, 1)) == REG) | |
5500 | { | |
5501 | if (REGNO (XEXP (tmp, 0)) == 0) | |
5502 | fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 1)) ], | |
5503 | reg_names[ REGNO (XEXP (tmp, 0)) ]); | |
5504 | else | |
5505 | fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 0)) ], | |
5506 | reg_names[ REGNO (XEXP (tmp, 1)) ]); | |
5507 | } | |
5508 | else | |
5509 | abort (); | |
5510 | break; | |
5511 | } | |
9854d9ed | 5512 | |
9878760c RK |
5513 | case 0: |
5514 | if (GET_CODE (x) == REG) | |
5515 | fprintf (file, "%s", reg_names[REGNO (x)]); | |
5516 | else if (GET_CODE (x) == MEM) | |
5517 | { | |
5518 | /* We need to handle PRE_INC and PRE_DEC here, since we need to | |
5519 | know the width from the mode. */ | |
5520 | if (GET_CODE (XEXP (x, 0)) == PRE_INC) | |
79ba6d34 MM |
5521 | fprintf (file, "%d(%s)", GET_MODE_SIZE (GET_MODE (x)), |
5522 | reg_names[REGNO (XEXP (XEXP (x, 0), 0))]); | |
9878760c | 5523 | else if (GET_CODE (XEXP (x, 0)) == PRE_DEC) |
79ba6d34 MM |
5524 | fprintf (file, "%d(%s)", - GET_MODE_SIZE (GET_MODE (x)), |
5525 | reg_names[REGNO (XEXP (XEXP (x, 0), 0))]); | |
9878760c | 5526 | else |
a54d04b7 | 5527 | output_address (XEXP (x, 0)); |
9878760c RK |
5528 | } |
5529 | else | |
a54d04b7 | 5530 | output_addr_const (file, x); |
a85d226b | 5531 | return; |
9878760c RK |
5532 | |
5533 | default: | |
5534 | output_operand_lossage ("invalid %%xn code"); | |
5535 | } | |
5536 | } | |
5537 | \f | |
5538 | /* Print the address of an operand. */ | |
5539 | ||
5540 | void | |
5541 | print_operand_address (file, x) | |
5542 | FILE *file; | |
592696dd | 5543 | rtx x; |
9878760c RK |
5544 | { |
5545 | if (GET_CODE (x) == REG) | |
4697a36c | 5546 | fprintf (file, "0(%s)", reg_names[ REGNO (x) ]); |
9ebbca7d GK |
5547 | else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST |
5548 | || GET_CODE (x) == LABEL_REF) | |
9878760c RK |
5549 | { |
5550 | output_addr_const (file, x); | |
ba5e43aa | 5551 | if (small_data_operand (x, GET_MODE (x))) |
8fbd2dc7 MM |
5552 | fprintf (file, "@%s(%s)", SMALL_DATA_RELOC, |
5553 | reg_names[SMALL_DATA_REG]); | |
9ebbca7d | 5554 | else if (TARGET_TOC) |
a4f6c312 | 5555 | abort (); |
9878760c RK |
5556 | } |
5557 | else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == REG) | |
5558 | { | |
5559 | if (REGNO (XEXP (x, 0)) == 0) | |
4697a36c MM |
5560 | fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 1)) ], |
5561 | reg_names[ REGNO (XEXP (x, 0)) ]); | |
9878760c | 5562 | else |
4697a36c MM |
5563 | fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 0)) ], |
5564 | reg_names[ REGNO (XEXP (x, 1)) ]); | |
9878760c RK |
5565 | } |
5566 | else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT) | |
5f59ecb7 DE |
5567 | { |
5568 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (XEXP (x, 1))); | |
5569 | fprintf (file, "(%s)", reg_names[ REGNO (XEXP (x, 0)) ]); | |
5570 | } | |
3cb999d8 DE |
5571 | #if TARGET_ELF |
5572 | else if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 0)) == REG | |
5573 | && CONSTANT_P (XEXP (x, 1))) | |
4697a36c MM |
5574 | { |
5575 | output_addr_const (file, XEXP (x, 1)); | |
5576 | fprintf (file, "@l(%s)", reg_names[ REGNO (XEXP (x, 0)) ]); | |
5577 | } | |
3cb999d8 | 5578 | #endif |
9ebbca7d GK |
5579 | else if (LEGITIMATE_CONSTANT_POOL_ADDRESS_P (x)) |
5580 | { | |
2bfcf297 | 5581 | if (TARGET_AIX && (!TARGET_ELF || !TARGET_MINIMAL_TOC)) |
9ebbca7d | 5582 | { |
2bfcf297 DB |
5583 | rtx contains_minus = XEXP (x, 1); |
5584 | rtx minus, symref; | |
5585 | const char *name; | |
9ebbca7d GK |
5586 | |
5587 | /* Find the (minus (sym) (toc)) buried in X, and temporarily | |
a4f6c312 | 5588 | turn it into (sym) for output_addr_const. */ |
9ebbca7d GK |
5589 | while (GET_CODE (XEXP (contains_minus, 0)) != MINUS) |
5590 | contains_minus = XEXP (contains_minus, 0); | |
5591 | ||
2bfcf297 DB |
5592 | minus = XEXP (contains_minus, 0); |
5593 | symref = XEXP (minus, 0); | |
5594 | XEXP (contains_minus, 0) = symref; | |
5595 | if (TARGET_ELF) | |
5596 | { | |
5597 | char *newname; | |
5598 | ||
5599 | name = XSTR (symref, 0); | |
5600 | newname = alloca (strlen (name) + sizeof ("@toc")); | |
5601 | strcpy (newname, name); | |
5602 | strcat (newname, "@toc"); | |
5603 | XSTR (symref, 0) = newname; | |
5604 | } | |
5605 | output_addr_const (file, XEXP (x, 1)); | |
5606 | if (TARGET_ELF) | |
5607 | XSTR (symref, 0) = name; | |
9ebbca7d GK |
5608 | XEXP (contains_minus, 0) = minus; |
5609 | } | |
5610 | else | |
5611 | output_addr_const (file, XEXP (x, 1)); | |
5612 | ||
5613 | fprintf (file, "(%s)", reg_names[REGNO (XEXP (x, 0))]); | |
5614 | } | |
9878760c RK |
5615 | else |
5616 | abort (); | |
5617 | } | |
5618 | \f | |
39a10a29 GK |
5619 | enum rtx_code |
5620 | rs6000_reverse_condition (mode, code) | |
5621 | enum machine_mode mode; | |
5622 | enum rtx_code code; | |
5623 | { | |
5624 | /* Reversal of FP compares takes care -- an ordered compare | |
5625 | becomes an unordered compare and vice versa. */ | |
5626 | if (mode == CCFPmode) | |
bab6226b | 5627 | return reverse_condition_maybe_unordered (code); |
39a10a29 | 5628 | else |
bab6226b | 5629 | return reverse_condition (code); |
39a10a29 GK |
5630 | } |
5631 | ||
39a10a29 GK |
5632 | /* Generate a compare for CODE. Return a brand-new rtx that |
5633 | represents the result of the compare. */ | |
a4f6c312 | 5634 | |
39a10a29 GK |
5635 | static rtx |
5636 | rs6000_generate_compare (code) | |
5637 | enum rtx_code code; | |
5638 | { | |
5639 | enum machine_mode comp_mode; | |
5640 | rtx compare_result; | |
5641 | ||
5642 | if (rs6000_compare_fp_p) | |
5643 | comp_mode = CCFPmode; | |
5644 | else if (code == GTU || code == LTU | |
5645 | || code == GEU || code == LEU) | |
5646 | comp_mode = CCUNSmode; | |
5647 | else | |
5648 | comp_mode = CCmode; | |
5649 | ||
5650 | /* First, the compare. */ | |
5651 | compare_result = gen_reg_rtx (comp_mode); | |
5652 | emit_insn (gen_rtx_SET (VOIDmode, compare_result, | |
5653 | gen_rtx_COMPARE (comp_mode, | |
5654 | rs6000_compare_op0, | |
5655 | rs6000_compare_op1))); | |
5656 | ||
ca5adc63 | 5657 | /* Some kinds of FP comparisons need an OR operation; |
de6c5979 | 5658 | except for flag_unsafe_math_optimizations we don't bother. */ |
39a10a29 | 5659 | if (rs6000_compare_fp_p |
de6c5979 | 5660 | && ! flag_unsafe_math_optimizations |
39a10a29 GK |
5661 | && (code == LE || code == GE |
5662 | || code == UNEQ || code == LTGT | |
5663 | || code == UNGT || code == UNLT)) | |
5664 | { | |
5665 | enum rtx_code or1, or2; | |
5666 | rtx or1_rtx, or2_rtx, compare2_rtx; | |
5667 | rtx or_result = gen_reg_rtx (CCEQmode); | |
5668 | ||
5669 | switch (code) | |
5670 | { | |
5671 | case LE: or1 = LT; or2 = EQ; break; | |
5672 | case GE: or1 = GT; or2 = EQ; break; | |
5673 | case UNEQ: or1 = UNORDERED; or2 = EQ; break; | |
5674 | case LTGT: or1 = LT; or2 = GT; break; | |
5675 | case UNGT: or1 = UNORDERED; or2 = GT; break; | |
5676 | case UNLT: or1 = UNORDERED; or2 = LT; break; | |
5677 | default: abort (); | |
5678 | } | |
5679 | validate_condition_mode (or1, comp_mode); | |
5680 | validate_condition_mode (or2, comp_mode); | |
5681 | or1_rtx = gen_rtx (or1, SImode, compare_result, const0_rtx); | |
5682 | or2_rtx = gen_rtx (or2, SImode, compare_result, const0_rtx); | |
5683 | compare2_rtx = gen_rtx_COMPARE (CCEQmode, | |
5684 | gen_rtx_IOR (SImode, or1_rtx, or2_rtx), | |
5685 | const_true_rtx); | |
5686 | emit_insn (gen_rtx_SET (VOIDmode, or_result, compare2_rtx)); | |
5687 | ||
5688 | compare_result = or_result; | |
5689 | code = EQ; | |
5690 | } | |
5691 | ||
5692 | validate_condition_mode (code, GET_MODE (compare_result)); | |
5693 | ||
5694 | return gen_rtx (code, VOIDmode, compare_result, const0_rtx); | |
5695 | } | |
5696 | ||
5697 | ||
5698 | /* Emit the RTL for an sCOND pattern. */ | |
5699 | ||
5700 | void | |
5701 | rs6000_emit_sCOND (code, result) | |
5702 | enum rtx_code code; | |
5703 | rtx result; | |
5704 | { | |
5705 | rtx condition_rtx; | |
5706 | enum machine_mode op_mode; | |
5707 | ||
5708 | condition_rtx = rs6000_generate_compare (code); | |
5709 | ||
5710 | op_mode = GET_MODE (rs6000_compare_op0); | |
5711 | if (op_mode == VOIDmode) | |
5712 | op_mode = GET_MODE (rs6000_compare_op1); | |
5713 | ||
5714 | if (TARGET_POWERPC64 && (op_mode == DImode || rs6000_compare_fp_p)) | |
5715 | { | |
5716 | PUT_MODE (condition_rtx, DImode); | |
5717 | convert_move (result, condition_rtx, 0); | |
5718 | } | |
5719 | else | |
5720 | { | |
5721 | PUT_MODE (condition_rtx, SImode); | |
5722 | emit_insn (gen_rtx_SET (VOIDmode, result, condition_rtx)); | |
5723 | } | |
5724 | } | |
5725 | ||
39a10a29 GK |
5726 | /* Emit a branch of kind CODE to location LOC. */ |
5727 | ||
5728 | void | |
5729 | rs6000_emit_cbranch (code, loc) | |
5730 | enum rtx_code code; | |
5731 | rtx loc; | |
5732 | { | |
5733 | rtx condition_rtx, loc_ref; | |
5734 | ||
5735 | condition_rtx = rs6000_generate_compare (code); | |
5736 | loc_ref = gen_rtx_LABEL_REF (VOIDmode, loc); | |
5737 | emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, | |
5738 | gen_rtx_IF_THEN_ELSE (VOIDmode, condition_rtx, | |
5739 | loc_ref, pc_rtx))); | |
5740 | } | |
5741 | ||
12a4e8c5 GK |
5742 | /* Return the string to output a conditional branch to LABEL, which is |
5743 | the operand number of the label, or -1 if the branch is really a | |
5744 | conditional return. | |
5745 | ||
5746 | OP is the conditional expression. XEXP (OP, 0) is assumed to be a | |
5747 | condition code register and its mode specifies what kind of | |
5748 | comparison we made. | |
5749 | ||
5750 | REVERSED is non-zero if we should reverse the sense of the comparison. | |
5751 | ||
5752 | INSN is the insn. */ | |
5753 | ||
5754 | char * | |
5755 | output_cbranch (op, label, reversed, insn) | |
5756 | rtx op; | |
5757 | const char * label; | |
5758 | int reversed; | |
5759 | rtx insn; | |
5760 | { | |
5761 | static char string[64]; | |
5762 | enum rtx_code code = GET_CODE (op); | |
5763 | rtx cc_reg = XEXP (op, 0); | |
5764 | enum machine_mode mode = GET_MODE (cc_reg); | |
5765 | int cc_regno = REGNO (cc_reg) - CR0_REGNO; | |
39a10a29 | 5766 | int need_longbranch = label != NULL && get_attr_length (insn) == 8; |
12a4e8c5 GK |
5767 | int really_reversed = reversed ^ need_longbranch; |
5768 | char *s = string; | |
5769 | const char *ccode; | |
5770 | const char *pred; | |
5771 | rtx note; | |
5772 | ||
39a10a29 GK |
5773 | validate_condition_mode (code, mode); |
5774 | ||
5775 | /* Work out which way this really branches. We could use | |
5776 | reverse_condition_maybe_unordered here always but this | |
5777 | makes the resulting assembler clearer. */ | |
12a4e8c5 | 5778 | if (really_reversed) |
39a10a29 | 5779 | code = rs6000_reverse_condition (mode, code); |
12a4e8c5 | 5780 | |
39a10a29 | 5781 | switch (code) |
12a4e8c5 GK |
5782 | { |
5783 | /* Not all of these are actually distinct opcodes, but | |
5784 | we distinguish them for clarity of the resulting assembler. */ | |
50a0b056 GK |
5785 | case NE: case LTGT: |
5786 | ccode = "ne"; break; | |
5787 | case EQ: case UNEQ: | |
5788 | ccode = "eq"; break; | |
5789 | case GE: case GEU: | |
5790 | ccode = "ge"; break; | |
5791 | case GT: case GTU: case UNGT: | |
5792 | ccode = "gt"; break; | |
5793 | case LE: case LEU: | |
5794 | ccode = "le"; break; | |
5795 | case LT: case LTU: case UNLT: | |
5796 | ccode = "lt"; break; | |
12a4e8c5 GK |
5797 | case UNORDERED: ccode = "un"; break; |
5798 | case ORDERED: ccode = "nu"; break; | |
5799 | case UNGE: ccode = "nl"; break; | |
5800 | case UNLE: ccode = "ng"; break; | |
5801 | default: | |
a4f6c312 | 5802 | abort (); |
12a4e8c5 GK |
5803 | } |
5804 | ||
94a54f47 GK |
5805 | /* Maybe we have a guess as to how likely the branch is. |
5806 | The old mnemonics don't have a way to specify this information. */ | |
12a4e8c5 GK |
5807 | note = find_reg_note (insn, REG_BR_PROB, NULL_RTX); |
5808 | if (note != NULL_RTX) | |
5809 | { | |
5810 | /* PROB is the difference from 50%. */ | |
5811 | int prob = INTVAL (XEXP (note, 0)) - REG_BR_PROB_BASE / 2; | |
5812 | ||
5813 | /* For branches that are very close to 50%, assume not-taken. */ | |
5814 | if (abs (prob) > REG_BR_PROB_BASE / 20 | |
5815 | && ((prob > 0) ^ need_longbranch)) | |
5816 | pred = "+"; | |
5817 | else | |
5818 | pred = "-"; | |
5819 | } | |
5820 | else | |
5821 | pred = ""; | |
5822 | ||
5823 | if (label == NULL) | |
94a54f47 | 5824 | s += sprintf (s, "{b%sr|b%slr%s} ", ccode, ccode, pred); |
12a4e8c5 | 5825 | else |
94a54f47 | 5826 | s += sprintf (s, "{b%s|b%s%s} ", ccode, ccode, pred); |
12a4e8c5 | 5827 | |
37c67319 GK |
5828 | /* We need to escape any '%' characters in the reg_names string. |
5829 | Assume they'd only be the first character... */ | |
5830 | if (reg_names[cc_regno + CR0_REGNO][0] == '%') | |
5831 | *s++ = '%'; | |
94a54f47 | 5832 | s += sprintf (s, "%s", reg_names[cc_regno + CR0_REGNO]); |
12a4e8c5 GK |
5833 | |
5834 | if (label != NULL) | |
5835 | { | |
5836 | /* If the branch distance was too far, we may have to use an | |
5837 | unconditional branch to go the distance. */ | |
5838 | if (need_longbranch) | |
44518ddd | 5839 | s += sprintf (s, ",$+8\n\tb %s", label); |
12a4e8c5 GK |
5840 | else |
5841 | s += sprintf (s, ",%s", label); | |
5842 | } | |
5843 | ||
5844 | return string; | |
5845 | } | |
50a0b056 GK |
5846 | |
5847 | /* Emit a conditional move: move TRUE_COND to DEST if OP of the | |
5848 | operands of the last comparison is nonzero/true, FALSE_COND if it | |
5849 | is zero/false. Return 0 if the hardware has no such operation. */ | |
a4f6c312 | 5850 | |
50a0b056 GK |
5851 | int |
5852 | rs6000_emit_cmove (dest, op, true_cond, false_cond) | |
5853 | rtx dest; | |
5854 | rtx op; | |
5855 | rtx true_cond; | |
5856 | rtx false_cond; | |
5857 | { | |
5858 | enum rtx_code code = GET_CODE (op); | |
5859 | rtx op0 = rs6000_compare_op0; | |
5860 | rtx op1 = rs6000_compare_op1; | |
5861 | REAL_VALUE_TYPE c1; | |
5862 | enum machine_mode mode = GET_MODE (op0); | |
5863 | rtx temp; | |
5864 | ||
5865 | /* First, work out if the hardware can do this at all, or | |
5866 | if it's too slow... */ | |
5867 | /* If the comparison is an integer one, since we only have fsel | |
5868 | it'll be cheaper to use a branch. */ | |
5869 | if (! rs6000_compare_fp_p) | |
5870 | return 0; | |
5871 | ||
5872 | /* Eliminate half of the comparisons by switching operands, this | |
5873 | makes the remaining code simpler. */ | |
5874 | if (code == UNLT || code == UNGT || code == UNORDERED || code == NE | |
5875 | || code == LTGT || code == LT) | |
5876 | { | |
5877 | code = reverse_condition_maybe_unordered (code); | |
5878 | temp = true_cond; | |
5879 | true_cond = false_cond; | |
5880 | false_cond = temp; | |
5881 | } | |
5882 | ||
5883 | /* UNEQ and LTGT take four instructions for a comparison with zero, | |
5884 | it'll probably be faster to use a branch here too. */ | |
5885 | if (code == UNEQ) | |
5886 | return 0; | |
5887 | ||
5888 | if (GET_CODE (op1) == CONST_DOUBLE) | |
5889 | REAL_VALUE_FROM_CONST_DOUBLE (c1, op1); | |
5890 | ||
5891 | /* We're going to try to implement comparions by performing | |
5892 | a subtract, then comparing against zero. Unfortunately, | |
5893 | Inf - Inf is NaN which is not zero, and so if we don't | |
5894 | know that the the operand is finite and the comparison | |
5895 | would treat EQ different to UNORDERED, we can't do it. */ | |
5896 | if (! flag_unsafe_math_optimizations | |
5897 | && code != GT && code != UNGE | |
5898 | && (GET_CODE (op1) != CONST_DOUBLE || target_isinf (c1)) | |
5899 | /* Constructs of the form (a OP b ? a : b) are safe. */ | |
5900 | && ((! rtx_equal_p (op0, false_cond) && ! rtx_equal_p (op1, false_cond)) | |
5901 | || (! rtx_equal_p (op0, true_cond) | |
5902 | && ! rtx_equal_p (op1, true_cond)))) | |
5903 | return 0; | |
5904 | /* At this point we know we can use fsel. */ | |
5905 | ||
5906 | /* Reduce the comparison to a comparison against zero. */ | |
5907 | temp = gen_reg_rtx (mode); | |
5908 | emit_insn (gen_rtx_SET (VOIDmode, temp, | |
5909 | gen_rtx_MINUS (mode, op0, op1))); | |
5910 | op0 = temp; | |
5911 | op1 = CONST0_RTX (mode); | |
5912 | ||
5913 | /* If we don't care about NaNs we can reduce some of the comparisons | |
5914 | down to faster ones. */ | |
5915 | if (flag_unsafe_math_optimizations) | |
5916 | switch (code) | |
5917 | { | |
5918 | case GT: | |
5919 | code = LE; | |
5920 | temp = true_cond; | |
5921 | true_cond = false_cond; | |
5922 | false_cond = temp; | |
5923 | break; | |
5924 | case UNGE: | |
5925 | code = GE; | |
5926 | break; | |
5927 | case UNEQ: | |
5928 | code = EQ; | |
5929 | break; | |
5930 | default: | |
5931 | break; | |
5932 | } | |
5933 | ||
5934 | /* Now, reduce everything down to a GE. */ | |
5935 | switch (code) | |
5936 | { | |
5937 | case GE: | |
5938 | break; | |
5939 | ||
5940 | case LE: | |
5941 | temp = gen_reg_rtx (mode); | |
5942 | emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (mode, op0))); | |
5943 | op0 = temp; | |
5944 | break; | |
5945 | ||
5946 | case ORDERED: | |
5947 | temp = gen_reg_rtx (mode); | |
5948 | emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_ABS (mode, op0))); | |
5949 | op0 = temp; | |
5950 | break; | |
5951 | ||
5952 | case EQ: | |
5953 | temp = gen_reg_rtx (mode); | |
5954 | emit_insn (gen_rtx_SET (VOIDmode, temp, | |
5955 | gen_rtx_NEG (mode, | |
5956 | gen_rtx_ABS (mode, op0)))); | |
5957 | op0 = temp; | |
5958 | break; | |
5959 | ||
5960 | case UNGE: | |
5961 | temp = gen_reg_rtx (mode); | |
5962 | emit_insn (gen_rtx_SET (VOIDmode, temp, | |
5963 | gen_rtx_IF_THEN_ELSE (mode, | |
5964 | gen_rtx_GE (VOIDmode, | |
5965 | op0, op1), | |
5966 | true_cond, false_cond))); | |
5967 | false_cond = temp; | |
5968 | true_cond = false_cond; | |
5969 | ||
5970 | temp = gen_reg_rtx (mode); | |
5971 | emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (mode, op0))); | |
5972 | op0 = temp; | |
5973 | break; | |
5974 | ||
5975 | case GT: | |
5976 | temp = gen_reg_rtx (mode); | |
5977 | emit_insn (gen_rtx_SET (VOIDmode, temp, | |
5978 | gen_rtx_IF_THEN_ELSE (mode, | |
5979 | gen_rtx_GE (VOIDmode, | |
5980 | op0, op1), | |
5981 | true_cond, false_cond))); | |
5982 | true_cond = temp; | |
5983 | false_cond = true_cond; | |
5984 | ||
5985 | temp = gen_reg_rtx (mode); | |
5986 | emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (mode, op0))); | |
5987 | op0 = temp; | |
5988 | break; | |
5989 | ||
5990 | default: | |
5991 | abort (); | |
5992 | } | |
5993 | ||
5994 | emit_insn (gen_rtx_SET (VOIDmode, dest, | |
9f1a9740 | 5995 | gen_rtx_IF_THEN_ELSE (GET_MODE (dest), |
50a0b056 GK |
5996 | gen_rtx_GE (VOIDmode, |
5997 | op0, op1), | |
5998 | true_cond, false_cond))); | |
5999 | return 1; | |
6000 | } | |
6001 | ||
6002 | void | |
6003 | rs6000_emit_minmax (dest, code, op0, op1) | |
6004 | rtx dest; | |
6005 | enum rtx_code code; | |
6006 | rtx op0; | |
6007 | rtx op1; | |
6008 | { | |
6009 | enum machine_mode mode = GET_MODE (op0); | |
6010 | rtx target; | |
6011 | if (code == SMAX || code == UMAX) | |
6012 | target = emit_conditional_move (dest, GE, op0, op1, mode, | |
6013 | op0, op1, mode, 0); | |
6014 | else | |
6015 | target = emit_conditional_move (dest, GE, op0, op1, mode, | |
6016 | op1, op0, mode, 0); | |
6017 | if (target == NULL_RTX) | |
6018 | abort (); | |
6019 | if (target != dest) | |
6020 | emit_move_insn (dest, target); | |
6021 | } | |
12a4e8c5 | 6022 | \f |
a4f6c312 SS |
6023 | /* This page contains routines that are used to determine what the |
6024 | function prologue and epilogue code will do and write them out. */ | |
9878760c | 6025 | |
a4f6c312 SS |
6026 | /* Return the first fixed-point register that is required to be |
6027 | saved. 32 if none. */ | |
9878760c RK |
6028 | |
6029 | int | |
6030 | first_reg_to_save () | |
6031 | { | |
6032 | int first_reg; | |
6033 | ||
6034 | /* Find lowest numbered live register. */ | |
6035 | for (first_reg = 13; first_reg <= 31; first_reg++) | |
a38d360d GK |
6036 | if (regs_ever_live[first_reg] |
6037 | && (! call_used_regs[first_reg] | |
6038 | || (first_reg == PIC_OFFSET_TABLE_REGNUM | |
f607bc57 ZW |
6039 | && ((DEFAULT_ABI == ABI_V4 && flag_pic == 1) |
6040 | || (DEFAULT_ABI == ABI_DARWIN && flag_pic))))) | |
9878760c RK |
6041 | break; |
6042 | ||
b5253831 DE |
6043 | if (profile_flag) |
6044 | { | |
6045 | /* AIX must save/restore every register that contains a parameter | |
6046 | before/after the .__mcount call plus an additional register | |
6047 | for the static chain, if needed; use registers from 30 down to 22 | |
6048 | to do this. */ | |
ee890fe2 | 6049 | if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) |
b5253831 DE |
6050 | { |
6051 | int last_parm_reg, profile_first_reg; | |
6052 | ||
6053 | /* Figure out last used parameter register. The proper thing | |
6054 | to do is to walk incoming args of the function. A function | |
6055 | might have live parameter registers even if it has no | |
6056 | incoming args. */ | |
6057 | for (last_parm_reg = 10; | |
6058 | last_parm_reg > 2 && ! regs_ever_live [last_parm_reg]; | |
6059 | last_parm_reg--) | |
6060 | ; | |
6061 | ||
6062 | /* Calculate first reg for saving parameter registers | |
6063 | and static chain. | |
6064 | Skip reg 31 which may contain the frame pointer. */ | |
6065 | profile_first_reg = (33 - last_parm_reg | |
6066 | - (current_function_needs_context ? 1 : 0)); | |
ee890fe2 SS |
6067 | #if TARGET_MACHO |
6068 | /* Need to skip another reg to account for R31 being PICBASE | |
6069 | (when flag_pic is set) or R30 being used as the frame | |
6070 | pointer (when flag_pic is not set). */ | |
6071 | --profile_first_reg; | |
6072 | #endif | |
b5253831 DE |
6073 | /* Do not save frame pointer if no parameters needs to be saved. */ |
6074 | if (profile_first_reg == 31) | |
6075 | profile_first_reg = 32; | |
6076 | ||
6077 | if (first_reg > profile_first_reg) | |
6078 | first_reg = profile_first_reg; | |
6079 | } | |
e165f3f0 | 6080 | |
b5253831 DE |
6081 | /* SVR4 may need one register to preserve the static chain. */ |
6082 | else if (current_function_needs_context) | |
6083 | { | |
6084 | /* Skip reg 31 which may contain the frame pointer. */ | |
6085 | if (first_reg > 30) | |
6086 | first_reg = 30; | |
6087 | } | |
6088 | } | |
e165f3f0 | 6089 | |
ee890fe2 SS |
6090 | #if TARGET_MACHO |
6091 | if (flag_pic && current_function_uses_pic_offset_table && | |
6092 | (first_reg > PIC_OFFSET_TABLE_REGNUM)) | |
6093 | return PIC_OFFSET_TABLE_REGNUM; | |
6094 | #endif | |
6095 | ||
9878760c RK |
6096 | return first_reg; |
6097 | } | |
6098 | ||
6099 | /* Similar, for FP regs. */ | |
6100 | ||
6101 | int | |
6102 | first_fp_reg_to_save () | |
6103 | { | |
6104 | int first_reg; | |
6105 | ||
6106 | /* Find lowest numbered live register. */ | |
6107 | for (first_reg = 14 + 32; first_reg <= 63; first_reg++) | |
6108 | if (regs_ever_live[first_reg]) | |
6109 | break; | |
6110 | ||
6111 | return first_reg; | |
6112 | } | |
00b960c7 AH |
6113 | |
6114 | /* Similar, for AltiVec regs. */ | |
6115 | ||
6116 | static int | |
6117 | first_altivec_reg_to_save () | |
6118 | { | |
6119 | int i; | |
6120 | ||
6121 | /* Stack frame remains as is unless we are in AltiVec ABI. */ | |
6122 | if (! TARGET_ALTIVEC_ABI) | |
6123 | return LAST_ALTIVEC_REGNO + 1; | |
6124 | ||
6125 | /* Find lowest numbered live register. */ | |
6126 | for (i = FIRST_ALTIVEC_REGNO + 20; i <= LAST_ALTIVEC_REGNO; ++i) | |
6127 | if (regs_ever_live[i]) | |
6128 | break; | |
6129 | ||
6130 | return i; | |
6131 | } | |
6132 | ||
6133 | /* Return a 32-bit mask of the AltiVec registers we need to set in | |
6134 | VRSAVE. Bit n of the return value is 1 if Vn is live. The MSB in | |
6135 | the 32-bit word is 0. */ | |
6136 | ||
6137 | static unsigned int | |
6138 | compute_vrsave_mask () | |
6139 | { | |
6140 | unsigned int i, mask = 0; | |
6141 | ||
6142 | /* First, find out if we use _any_ altivec registers. */ | |
6143 | for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i) | |
6144 | if (regs_ever_live[i]) | |
6145 | mask |= ALTIVEC_REG_BIT (i); | |
6146 | ||
6147 | if (mask == 0) | |
6148 | return mask; | |
6149 | ||
6150 | /* Next, add all registers that are call-clobbered. We do this | |
6151 | because post-reload register optimizers such as regrename_optimize | |
6152 | may choose to use them. They never change the register class | |
6153 | chosen by reload, so cannot create new uses of altivec registers | |
6154 | if there were none before, so the early exit above is safe. */ | |
6155 | /* ??? Alternately, we could define HARD_REGNO_RENAME_OK to disallow | |
6156 | altivec registers not saved in the mask, which might well make the | |
6157 | adjustments below more effective in eliding the save/restore of | |
6158 | VRSAVE in small functions. */ | |
6159 | for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i) | |
6160 | if (call_used_regs[i]) | |
6161 | mask |= ALTIVEC_REG_BIT (i); | |
6162 | ||
6163 | /* Next, remove the argument registers from the set. These must | |
6164 | be in the VRSAVE mask set by the caller, so we don't need to add | |
6165 | them in again. More importantly, the mask we compute here is | |
6166 | used to generate CLOBBERs in the set_vrsave insn, and we do not | |
6167 | wish the argument registers to die. */ | |
6168 | for (i = cfun->args_info.vregno; i >= ALTIVEC_ARG_MIN_REG; --i) | |
6169 | mask &= ~ALTIVEC_REG_BIT (i); | |
6170 | ||
6171 | /* Similarly, remove the return value from the set. */ | |
6172 | { | |
6173 | bool yes = false; | |
6174 | diddle_return_value (is_altivec_return_reg, &yes); | |
6175 | if (yes) | |
6176 | mask &= ~ALTIVEC_REG_BIT (ALTIVEC_ARG_RETURN); | |
6177 | } | |
6178 | ||
6179 | return mask; | |
6180 | } | |
6181 | ||
6182 | static void | |
6183 | is_altivec_return_reg (reg, xyes) | |
6184 | rtx reg; | |
6185 | void *xyes; | |
6186 | { | |
6187 | bool *yes = (bool *) xyes; | |
6188 | if (REGNO (reg) == ALTIVEC_ARG_RETURN) | |
6189 | *yes = true; | |
6190 | } | |
6191 | ||
4697a36c MM |
6192 | \f |
6193 | /* Calculate the stack information for the current function. This is | |
6194 | complicated by having two separate calling sequences, the AIX calling | |
6195 | sequence and the V.4 calling sequence. | |
6196 | ||
592696dd | 6197 | AIX (and Darwin/Mac OS X) stack frames look like: |
a260abc9 | 6198 | 32-bit 64-bit |
4697a36c | 6199 | SP----> +---------------------------------------+ |
a260abc9 | 6200 | | back chain to caller | 0 0 |
4697a36c | 6201 | +---------------------------------------+ |
a260abc9 | 6202 | | saved CR | 4 8 (8-11) |
4697a36c | 6203 | +---------------------------------------+ |
a260abc9 | 6204 | | saved LR | 8 16 |
4697a36c | 6205 | +---------------------------------------+ |
a260abc9 | 6206 | | reserved for compilers | 12 24 |
4697a36c | 6207 | +---------------------------------------+ |
a260abc9 | 6208 | | reserved for binders | 16 32 |
4697a36c | 6209 | +---------------------------------------+ |
a260abc9 | 6210 | | saved TOC pointer | 20 40 |
4697a36c | 6211 | +---------------------------------------+ |
a260abc9 | 6212 | | Parameter save area (P) | 24 48 |
4697a36c | 6213 | +---------------------------------------+ |
a260abc9 | 6214 | | Alloca space (A) | 24+P etc. |
802a0058 | 6215 | +---------------------------------------+ |
a7df97e6 | 6216 | | Local variable space (L) | 24+P+A |
4697a36c | 6217 | +---------------------------------------+ |
a7df97e6 | 6218 | | Float/int conversion temporary (X) | 24+P+A+L |
4697a36c | 6219 | +---------------------------------------+ |
00b960c7 AH |
6220 | | Save area for AltiVec registers (W) | 24+P+A+L+X |
6221 | +---------------------------------------+ | |
6222 | | AltiVec alignment padding (Y) | 24+P+A+L+X+W | |
6223 | +---------------------------------------+ | |
6224 | | Save area for VRSAVE register (Z) | 24+P+A+L+X+W+Y | |
4697a36c | 6225 | +---------------------------------------+ |
00b960c7 AH |
6226 | | Save area for GP registers (G) | 24+P+A+X+L+X+W+Y+Z |
6227 | +---------------------------------------+ | |
6228 | | Save area for FP registers (F) | 24+P+A+X+L+X+W+Y+Z+G | |
4697a36c MM |
6229 | +---------------------------------------+ |
6230 | old SP->| back chain to caller's caller | | |
6231 | +---------------------------------------+ | |
6232 | ||
5376a30c KR |
6233 | The required alignment for AIX configurations is two words (i.e., 8 |
6234 | or 16 bytes). | |
6235 | ||
6236 | ||
4697a36c MM |
6237 | V.4 stack frames look like: |
6238 | ||
6239 | SP----> +---------------------------------------+ | |
6240 | | back chain to caller | 0 | |
6241 | +---------------------------------------+ | |
5eb387b8 | 6242 | | caller's saved LR | 4 |
4697a36c MM |
6243 | +---------------------------------------+ |
6244 | | Parameter save area (P) | 8 | |
6245 | +---------------------------------------+ | |
a7df97e6 MM |
6246 | | Alloca space (A) | 8+P |
6247 | +---------------------------------------+ | |
6248 | | Varargs save area (V) | 8+P+A | |
6249 | +---------------------------------------+ | |
6250 | | Local variable space (L) | 8+P+A+V | |
6251 | +---------------------------------------+ | |
6252 | | Float/int conversion temporary (X) | 8+P+A+V+L | |
4697a36c | 6253 | +---------------------------------------+ |
00b960c7 AH |
6254 | | Save area for AltiVec registers (W) | 8+P+A+V+L+X |
6255 | +---------------------------------------+ | |
6256 | | AltiVec alignment padding (Y) | 8+P+A+V+L+X+W | |
6257 | +---------------------------------------+ | |
6258 | | Save area for VRSAVE register (Z) | 8+P+A+V+L+X+W+Y | |
6259 | +---------------------------------------+ | |
6260 | | saved CR (C) | 8+P+A+V+L+X+W+Y+Z | |
a7df97e6 | 6261 | +---------------------------------------+ |
00b960c7 | 6262 | | Save area for GP registers (G) | 8+P+A+V+L+X+W+Y+Z+C |
a7df97e6 | 6263 | +---------------------------------------+ |
00b960c7 | 6264 | | Save area for FP registers (F) | 8+P+A+V+L+X+W+Y+Z+C+G |
4697a36c MM |
6265 | +---------------------------------------+ |
6266 | old SP->| back chain to caller's caller | | |
6267 | +---------------------------------------+ | |
b6c9286a | 6268 | |
5376a30c KR |
6269 | The required alignment for V.4 is 16 bytes, or 8 bytes if -meabi is |
6270 | given. (But note below and in sysv4.h that we require only 8 and | |
6271 | may round up the size of our stack frame anyways. The historical | |
6272 | reason is early versions of powerpc-linux which didn't properly | |
6273 | align the stack at program startup. A happy side-effect is that | |
6274 | -mno-eabi libraries can be used with -meabi programs.) | |
6275 | ||
5376a30c KR |
6276 | The EABI configuration defaults to the V.4 layout, unless |
6277 | -mcall-aix is used, in which case the AIX layout is used. However, | |
6278 | the stack alignment requirements may differ. If -mno-eabi is not | |
6279 | given, the required stack alignment is 8 bytes; if -mno-eabi is | |
6280 | given, the required alignment is 16 bytes. (But see V.4 comment | |
6281 | above.) */ | |
4697a36c | 6282 | |
61b2fbe7 MM |
6283 | #ifndef ABI_STACK_BOUNDARY |
6284 | #define ABI_STACK_BOUNDARY STACK_BOUNDARY | |
6285 | #endif | |
6286 | ||
4697a36c MM |
6287 | rs6000_stack_t * |
6288 | rs6000_stack_info () | |
6289 | { | |
6290 | static rs6000_stack_t info, zero_info; | |
6291 | rs6000_stack_t *info_ptr = &info; | |
9ebbca7d | 6292 | int reg_size = TARGET_POWERPC64 ? 8 : 4; |
24d304eb | 6293 | enum rs6000_abi abi; |
83720594 | 6294 | int ehrd_size; |
b6c9286a | 6295 | int total_raw_size; |
4697a36c | 6296 | |
a4f6c312 | 6297 | /* Zero all fields portably. */ |
4697a36c MM |
6298 | info = zero_info; |
6299 | ||
a4f6c312 | 6300 | /* Select which calling sequence. */ |
b6c9286a | 6301 | info_ptr->abi = abi = DEFAULT_ABI; |
9878760c | 6302 | |
a4f6c312 | 6303 | /* Calculate which registers need to be saved & save area size. */ |
4697a36c | 6304 | info_ptr->first_gp_reg_save = first_reg_to_save (); |
906fb125 GK |
6305 | /* Assume that we will have to save PIC_OFFSET_TABLE_REGNUM, |
6306 | even if it currently looks like we won't. */ | |
2bfcf297 | 6307 | if (((TARGET_TOC && TARGET_MINIMAL_TOC) |
f607bc57 ZW |
6308 | || (flag_pic == 1 && abi == ABI_V4) |
6309 | || (flag_pic && abi == ABI_DARWIN)) | |
906fb125 GK |
6310 | && info_ptr->first_gp_reg_save > PIC_OFFSET_TABLE_REGNUM) |
6311 | info_ptr->gp_size = reg_size * (32 - PIC_OFFSET_TABLE_REGNUM); | |
6312 | else | |
6313 | info_ptr->gp_size = reg_size * (32 - info_ptr->first_gp_reg_save); | |
4697a36c MM |
6314 | |
6315 | info_ptr->first_fp_reg_save = first_fp_reg_to_save (); | |
6316 | info_ptr->fp_size = 8 * (64 - info_ptr->first_fp_reg_save); | |
6317 | ||
00b960c7 AH |
6318 | info_ptr->first_altivec_reg_save = first_altivec_reg_to_save (); |
6319 | info_ptr->altivec_size = 16 * (LAST_ALTIVEC_REGNO + 1 | |
6320 | - info_ptr->first_altivec_reg_save); | |
6321 | ||
592696dd | 6322 | /* Does this function call anything? */ |
71f123ca FS |
6323 | info_ptr->calls_p = (! current_function_is_leaf |
6324 | || cfun->machine->ra_needs_full_frame); | |
b6c9286a | 6325 | |
a4f6c312 | 6326 | /* Determine if we need to save the link register. */ |
71f123ca | 6327 | if (rs6000_ra_ever_killed () |
38c1f2d7 | 6328 | || (DEFAULT_ABI == ABI_AIX && profile_flag) |
4697a36c MM |
6329 | #ifdef TARGET_RELOCATABLE |
6330 | || (TARGET_RELOCATABLE && (get_pool_size () != 0)) | |
6331 | #endif | |
6332 | || (info_ptr->first_fp_reg_save != 64 | |
6333 | && !FP_SAVE_INLINE (info_ptr->first_fp_reg_save)) | |
00b960c7 | 6334 | || info_ptr->first_altivec_reg_save <= LAST_ALTIVEC_REGNO |
24d304eb | 6335 | || (abi == ABI_V4 && current_function_calls_alloca) |
a4f6c312 SS |
6336 | || (DEFAULT_ABI == ABI_DARWIN |
6337 | && flag_pic | |
6338 | && current_function_uses_pic_offset_table) | |
4697a36c MM |
6339 | || info_ptr->calls_p) |
6340 | { | |
6341 | info_ptr->lr_save_p = 1; | |
9ebbca7d | 6342 | regs_ever_live[LINK_REGISTER_REGNUM] = 1; |
4697a36c MM |
6343 | } |
6344 | ||
9ebbca7d GK |
6345 | /* Determine if we need to save the condition code registers. */ |
6346 | if (regs_ever_live[CR2_REGNO] | |
6347 | || regs_ever_live[CR3_REGNO] | |
6348 | || regs_ever_live[CR4_REGNO]) | |
4697a36c MM |
6349 | { |
6350 | info_ptr->cr_save_p = 1; | |
f607bc57 | 6351 | if (abi == ABI_V4) |
4697a36c MM |
6352 | info_ptr->cr_size = reg_size; |
6353 | } | |
6354 | ||
83720594 RH |
6355 | /* If the current function calls __builtin_eh_return, then we need |
6356 | to allocate stack space for registers that will hold data for | |
6357 | the exception handler. */ | |
6358 | if (current_function_calls_eh_return) | |
6359 | { | |
6360 | unsigned int i; | |
6361 | for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; ++i) | |
6362 | continue; | |
6363 | ehrd_size = i * UNITS_PER_WORD; | |
6364 | } | |
6365 | else | |
6366 | ehrd_size = 0; | |
6367 | ||
592696dd | 6368 | /* Determine various sizes. */ |
4697a36c MM |
6369 | info_ptr->reg_size = reg_size; |
6370 | info_ptr->fixed_size = RS6000_SAVE_AREA; | |
6371 | info_ptr->varargs_size = RS6000_VARARGS_AREA; | |
189e03e3 | 6372 | info_ptr->vars_size = RS6000_ALIGN (get_frame_size (), 8); |
a4f6c312 SS |
6373 | info_ptr->parm_size = RS6000_ALIGN (current_function_outgoing_args_size, |
6374 | 8); | |
00b960c7 AH |
6375 | |
6376 | if (TARGET_ALTIVEC_ABI) | |
6377 | { | |
6378 | info_ptr->vrsave_mask = compute_vrsave_mask (); | |
6379 | info_ptr->vrsave_size = info_ptr->vrsave_mask ? 4 : 0; | |
6380 | } | |
6381 | else | |
6382 | { | |
6383 | info_ptr->vrsave_mask = 0; | |
6384 | info_ptr->vrsave_size = 0; | |
6385 | } | |
b6c9286a | 6386 | |
592696dd | 6387 | /* Calculate the offsets. */ |
24d304eb | 6388 | switch (abi) |
4697a36c | 6389 | { |
b6c9286a | 6390 | case ABI_NONE: |
24d304eb | 6391 | default: |
b6c9286a MM |
6392 | abort (); |
6393 | ||
6394 | case ABI_AIX: | |
6395 | case ABI_AIX_NODESC: | |
ee890fe2 | 6396 | case ABI_DARWIN: |
b6c9286a MM |
6397 | info_ptr->fp_save_offset = - info_ptr->fp_size; |
6398 | info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size; | |
00b960c7 AH |
6399 | |
6400 | if (TARGET_ALTIVEC_ABI) | |
6401 | { | |
6402 | info_ptr->vrsave_save_offset | |
6403 | = info_ptr->gp_save_offset - info_ptr->vrsave_size; | |
6404 | ||
6405 | /* Align stack so vector save area is on a quadword boundary. */ | |
6406 | if (info_ptr->altivec_size != 0) | |
6407 | info_ptr->altivec_padding_size | |
6408 | = 16 - (-info_ptr->vrsave_save_offset % 16); | |
6409 | else | |
6410 | info_ptr->altivec_padding_size = 0; | |
6411 | ||
6412 | info_ptr->altivec_save_offset | |
6413 | = info_ptr->vrsave_save_offset | |
6414 | - info_ptr->altivec_padding_size | |
6415 | - info_ptr->altivec_size; | |
6416 | ||
6417 | /* Adjust for AltiVec case. */ | |
6418 | info_ptr->ehrd_offset = info_ptr->altivec_save_offset - ehrd_size; | |
6419 | } | |
6420 | else | |
6421 | info_ptr->ehrd_offset = info_ptr->gp_save_offset - ehrd_size; | |
a260abc9 DE |
6422 | info_ptr->cr_save_offset = reg_size; /* first word when 64-bit. */ |
6423 | info_ptr->lr_save_offset = 2*reg_size; | |
24d304eb RK |
6424 | break; |
6425 | ||
6426 | case ABI_V4: | |
b6c9286a MM |
6427 | info_ptr->fp_save_offset = - info_ptr->fp_size; |
6428 | info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size; | |
a7df97e6 | 6429 | info_ptr->cr_save_offset = info_ptr->gp_save_offset - info_ptr->cr_size; |
00b960c7 AH |
6430 | |
6431 | if (TARGET_ALTIVEC_ABI) | |
6432 | { | |
6433 | info_ptr->vrsave_save_offset | |
6434 | = info_ptr->cr_save_offset - info_ptr->vrsave_size; | |
6435 | ||
6436 | /* Align stack so vector save area is on a quadword boundary. */ | |
6437 | if (info_ptr->altivec_size != 0) | |
6438 | info_ptr->altivec_padding_size | |
6439 | = 16 - (-info_ptr->vrsave_save_offset % 16); | |
6440 | else | |
6441 | info_ptr->altivec_padding_size = 0; | |
6442 | ||
6443 | info_ptr->altivec_save_offset | |
6444 | = info_ptr->vrsave_save_offset | |
6445 | - info_ptr->altivec_padding_size | |
6446 | - info_ptr->altivec_size; | |
6447 | ||
6448 | /* Adjust for AltiVec case. */ | |
6449 | info_ptr->toc_save_offset | |
6450 | = info_ptr->altivec_save_offset - info_ptr->toc_size; | |
6451 | } | |
6452 | else | |
6453 | info_ptr->toc_save_offset = info_ptr->cr_save_offset - info_ptr->toc_size; | |
83720594 | 6454 | info_ptr->ehrd_offset = info_ptr->toc_save_offset - ehrd_size; |
b6c9286a MM |
6455 | info_ptr->lr_save_offset = reg_size; |
6456 | break; | |
4697a36c MM |
6457 | } |
6458 | ||
00b960c7 AH |
6459 | info_ptr->save_size = RS6000_ALIGN (info_ptr->fp_size |
6460 | + info_ptr->gp_size | |
6461 | + info_ptr->altivec_size | |
6462 | + info_ptr->altivec_padding_size | |
6463 | + info_ptr->vrsave_size | |
6464 | + ehrd_size | |
6465 | + info_ptr->cr_size | |
6466 | + info_ptr->lr_size | |
6467 | + info_ptr->vrsave_size | |
6468 | + info_ptr->toc_size, | |
6469 | (TARGET_ALTIVEC_ABI || ABI_DARWIN) | |
6470 | ? 16 : 8); | |
6471 | ||
ff381587 MM |
6472 | total_raw_size = (info_ptr->vars_size |
6473 | + info_ptr->parm_size | |
ff381587 MM |
6474 | + info_ptr->save_size |
6475 | + info_ptr->varargs_size | |
6476 | + info_ptr->fixed_size); | |
6477 | ||
a4f6c312 SS |
6478 | info_ptr->total_size = |
6479 | RS6000_ALIGN (total_raw_size, ABI_STACK_BOUNDARY / BITS_PER_UNIT); | |
ff381587 MM |
6480 | |
6481 | /* Determine if we need to allocate any stack frame: | |
6482 | ||
a4f6c312 SS |
6483 | For AIX we need to push the stack if a frame pointer is needed |
6484 | (because the stack might be dynamically adjusted), if we are | |
6485 | debugging, if we make calls, or if the sum of fp_save, gp_save, | |
6486 | and local variables are more than the space needed to save all | |
6487 | non-volatile registers: 32-bit: 18*8 + 19*4 = 220 or 64-bit: 18*8 | |
6488 | + 18*8 = 288 (GPR13 reserved). | |
ff381587 | 6489 | |
a4f6c312 SS |
6490 | For V.4 we don't have the stack cushion that AIX uses, but assume |
6491 | that the debugger can handle stackless frames. */ | |
ff381587 MM |
6492 | |
6493 | if (info_ptr->calls_p) | |
6494 | info_ptr->push_p = 1; | |
6495 | ||
f607bc57 | 6496 | else if (abi == ABI_V4) |
ff381587 | 6497 | info_ptr->push_p = (total_raw_size > info_ptr->fixed_size |
9ebbca7d | 6498 | || info_ptr->calls_p); |
ff381587 MM |
6499 | |
6500 | else | |
6501 | info_ptr->push_p = (frame_pointer_needed | |
ee890fe2 | 6502 | || (abi != ABI_DARWIN && write_symbols != NO_DEBUG) |
ff381587 | 6503 | || ((total_raw_size - info_ptr->fixed_size) |
bfc79d3b | 6504 | > (TARGET_32BIT ? 220 : 288))); |
ff381587 | 6505 | |
a4f6c312 | 6506 | /* Zero offsets if we're not saving those registers. */ |
8dda1a21 | 6507 | if (info_ptr->fp_size == 0) |
4697a36c MM |
6508 | info_ptr->fp_save_offset = 0; |
6509 | ||
8dda1a21 | 6510 | if (info_ptr->gp_size == 0) |
4697a36c MM |
6511 | info_ptr->gp_save_offset = 0; |
6512 | ||
00b960c7 AH |
6513 | if (! TARGET_ALTIVEC_ABI || info_ptr->altivec_size == 0) |
6514 | info_ptr->altivec_save_offset = 0; | |
6515 | ||
6516 | if (! TARGET_ALTIVEC_ABI || info_ptr->vrsave_mask == 0) | |
6517 | info_ptr->vrsave_save_offset = 0; | |
6518 | ||
c81fc13e | 6519 | if (! info_ptr->lr_save_p) |
4697a36c MM |
6520 | info_ptr->lr_save_offset = 0; |
6521 | ||
c81fc13e | 6522 | if (! info_ptr->cr_save_p) |
4697a36c MM |
6523 | info_ptr->cr_save_offset = 0; |
6524 | ||
c81fc13e | 6525 | if (! info_ptr->toc_save_p) |
b6c9286a MM |
6526 | info_ptr->toc_save_offset = 0; |
6527 | ||
4697a36c MM |
6528 | return info_ptr; |
6529 | } | |
6530 | ||
6531 | void | |
6532 | debug_stack_info (info) | |
6533 | rs6000_stack_t *info; | |
9878760c | 6534 | { |
d330fd93 | 6535 | const char *abi_string; |
24d304eb | 6536 | |
c81fc13e | 6537 | if (! info) |
4697a36c MM |
6538 | info = rs6000_stack_info (); |
6539 | ||
6540 | fprintf (stderr, "\nStack information for function %s:\n", | |
6541 | ((current_function_decl && DECL_NAME (current_function_decl)) | |
6542 | ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl)) | |
6543 | : "<unknown>")); | |
6544 | ||
24d304eb RK |
6545 | switch (info->abi) |
6546 | { | |
b6c9286a MM |
6547 | default: abi_string = "Unknown"; break; |
6548 | case ABI_NONE: abi_string = "NONE"; break; | |
f607bc57 | 6549 | case ABI_AIX: |
b6c9286a | 6550 | case ABI_AIX_NODESC: abi_string = "AIX"; break; |
ee890fe2 | 6551 | case ABI_DARWIN: abi_string = "Darwin"; break; |
b6c9286a | 6552 | case ABI_V4: abi_string = "V.4"; break; |
24d304eb RK |
6553 | } |
6554 | ||
6555 | fprintf (stderr, "\tABI = %5s\n", abi_string); | |
6556 | ||
00b960c7 AH |
6557 | if (TARGET_ALTIVEC_ABI) |
6558 | fprintf (stderr, "\tALTIVEC ABI extensions enabled.\n"); | |
6559 | ||
4697a36c MM |
6560 | if (info->first_gp_reg_save != 32) |
6561 | fprintf (stderr, "\tfirst_gp_reg_save = %5d\n", info->first_gp_reg_save); | |
6562 | ||
6563 | if (info->first_fp_reg_save != 64) | |
6564 | fprintf (stderr, "\tfirst_fp_reg_save = %5d\n", info->first_fp_reg_save); | |
9878760c | 6565 | |
00b960c7 AH |
6566 | if (info->first_altivec_reg_save <= LAST_ALTIVEC_REGNO) |
6567 | fprintf (stderr, "\tfirst_altivec_reg_save = %5d\n", | |
6568 | info->first_altivec_reg_save); | |
6569 | ||
4697a36c MM |
6570 | if (info->lr_save_p) |
6571 | fprintf (stderr, "\tlr_save_p = %5d\n", info->lr_save_p); | |
9878760c | 6572 | |
4697a36c MM |
6573 | if (info->cr_save_p) |
6574 | fprintf (stderr, "\tcr_save_p = %5d\n", info->cr_save_p); | |
6575 | ||
b6c9286a MM |
6576 | if (info->toc_save_p) |
6577 | fprintf (stderr, "\ttoc_save_p = %5d\n", info->toc_save_p); | |
6578 | ||
00b960c7 AH |
6579 | if (info->vrsave_mask) |
6580 | fprintf (stderr, "\tvrsave_mask = 0x%x\n", info->vrsave_mask); | |
6581 | ||
4697a36c MM |
6582 | if (info->push_p) |
6583 | fprintf (stderr, "\tpush_p = %5d\n", info->push_p); | |
6584 | ||
6585 | if (info->calls_p) | |
6586 | fprintf (stderr, "\tcalls_p = %5d\n", info->calls_p); | |
6587 | ||
4697a36c MM |
6588 | if (info->gp_save_offset) |
6589 | fprintf (stderr, "\tgp_save_offset = %5d\n", info->gp_save_offset); | |
6590 | ||
6591 | if (info->fp_save_offset) | |
6592 | fprintf (stderr, "\tfp_save_offset = %5d\n", info->fp_save_offset); | |
6593 | ||
00b960c7 AH |
6594 | if (info->altivec_save_offset) |
6595 | fprintf (stderr, "\taltivec_save_offset = %5d\n", | |
6596 | info->altivec_save_offset); | |
6597 | ||
6598 | if (info->vrsave_save_offset) | |
6599 | fprintf (stderr, "\tvrsave_save_offset = %5d\n", | |
6600 | info->vrsave_save_offset); | |
6601 | ||
4697a36c MM |
6602 | if (info->lr_save_offset) |
6603 | fprintf (stderr, "\tlr_save_offset = %5d\n", info->lr_save_offset); | |
6604 | ||
6605 | if (info->cr_save_offset) | |
6606 | fprintf (stderr, "\tcr_save_offset = %5d\n", info->cr_save_offset); | |
6607 | ||
b6c9286a MM |
6608 | if (info->toc_save_offset) |
6609 | fprintf (stderr, "\ttoc_save_offset = %5d\n", info->toc_save_offset); | |
6610 | ||
4697a36c MM |
6611 | if (info->varargs_save_offset) |
6612 | fprintf (stderr, "\tvarargs_save_offset = %5d\n", info->varargs_save_offset); | |
6613 | ||
6614 | if (info->total_size) | |
6615 | fprintf (stderr, "\ttotal_size = %5d\n", info->total_size); | |
6616 | ||
6617 | if (info->varargs_size) | |
6618 | fprintf (stderr, "\tvarargs_size = %5d\n", info->varargs_size); | |
6619 | ||
6620 | if (info->vars_size) | |
6621 | fprintf (stderr, "\tvars_size = %5d\n", info->vars_size); | |
6622 | ||
6623 | if (info->parm_size) | |
6624 | fprintf (stderr, "\tparm_size = %5d\n", info->parm_size); | |
6625 | ||
6626 | if (info->fixed_size) | |
6627 | fprintf (stderr, "\tfixed_size = %5d\n", info->fixed_size); | |
6628 | ||
6629 | if (info->gp_size) | |
6630 | fprintf (stderr, "\tgp_size = %5d\n", info->gp_size); | |
6631 | ||
6632 | if (info->fp_size) | |
6633 | fprintf (stderr, "\tfp_size = %5d\n", info->fp_size); | |
6634 | ||
00b960c7 AH |
6635 | if (info->altivec_size) |
6636 | fprintf (stderr, "\taltivec_size = %5d\n", info->altivec_size); | |
6637 | ||
6638 | if (info->vrsave_size) | |
6639 | fprintf (stderr, "\tvrsave_size = %5d\n", info->vrsave_size); | |
6640 | ||
6641 | if (info->altivec_padding_size) | |
6642 | fprintf (stderr, "\taltivec_padding_size= %5d\n", | |
6643 | info->altivec_padding_size); | |
6644 | ||
a4f6c312 | 6645 | if (info->lr_size) |
ed947a96 | 6646 | fprintf (stderr, "\tlr_size = %5d\n", info->lr_size); |
b6c9286a | 6647 | |
4697a36c MM |
6648 | if (info->cr_size) |
6649 | fprintf (stderr, "\tcr_size = %5d\n", info->cr_size); | |
6650 | ||
a4f6c312 | 6651 | if (info->toc_size) |
b6c9286a MM |
6652 | fprintf (stderr, "\ttoc_size = %5d\n", info->toc_size); |
6653 | ||
4697a36c MM |
6654 | if (info->save_size) |
6655 | fprintf (stderr, "\tsave_size = %5d\n", info->save_size); | |
6656 | ||
6657 | if (info->reg_size != 4) | |
6658 | fprintf (stderr, "\treg_size = %5d\n", info->reg_size); | |
6659 | ||
6660 | fprintf (stderr, "\n"); | |
9878760c | 6661 | } |
71f123ca FS |
6662 | |
6663 | rtx | |
6664 | rs6000_return_addr (count, frame) | |
6665 | int count; | |
6666 | rtx frame; | |
6667 | { | |
a4f6c312 SS |
6668 | /* Currently we don't optimize very well between prolog and body |
6669 | code and for PIC code the code can be actually quite bad, so | |
6670 | don't try to be too clever here. */ | |
3418dd3a FS |
6671 | if (count != 0 |
6672 | || flag_pic != 0 | |
6673 | || DEFAULT_ABI == ABI_AIX | |
6674 | || DEFAULT_ABI == ABI_AIX_NODESC) | |
71f123ca FS |
6675 | { |
6676 | cfun->machine->ra_needs_full_frame = 1; | |
8ac61af7 RK |
6677 | |
6678 | return | |
6679 | gen_rtx_MEM | |
6680 | (Pmode, | |
6681 | memory_address | |
6682 | (Pmode, | |
6683 | plus_constant (copy_to_reg | |
6684 | (gen_rtx_MEM (Pmode, | |
6685 | memory_address (Pmode, frame))), | |
6686 | RETURN_ADDRESS_OFFSET))); | |
71f123ca FS |
6687 | } |
6688 | ||
9e2f7ec7 | 6689 | return get_hard_reg_initial_val (Pmode, LINK_REGISTER_REGNUM); |
71f123ca FS |
6690 | } |
6691 | ||
6692 | static int | |
6693 | rs6000_ra_ever_killed () | |
6694 | { | |
6695 | rtx top; | |
6696 | ||
6697 | #ifdef ASM_OUTPUT_MI_THUNK | |
6698 | if (current_function_is_thunk) | |
6699 | return 0; | |
6700 | #endif | |
9e2f7ec7 DD |
6701 | if (!has_hard_reg_initial_val (Pmode, LINK_REGISTER_REGNUM) |
6702 | || cfun->machine->ra_needs_full_frame) | |
71f123ca FS |
6703 | return regs_ever_live[LINK_REGISTER_REGNUM]; |
6704 | ||
6705 | push_topmost_sequence (); | |
6706 | top = get_insns (); | |
6707 | pop_topmost_sequence (); | |
6708 | ||
6709 | return reg_set_between_p (gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM), | |
6710 | top, NULL_RTX); | |
6711 | } | |
4697a36c | 6712 | \f |
8cd8f856 GK |
6713 | /* Add a REG_MAYBE_DEAD note to the insn. */ |
6714 | static void | |
6715 | rs6000_maybe_dead (insn) | |
6716 | rtx insn; | |
6717 | { | |
6718 | REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD, | |
6719 | const0_rtx, | |
6720 | REG_NOTES (insn)); | |
6721 | } | |
6722 | ||
9ebbca7d | 6723 | /* Emit instructions needed to load the TOC register. |
c7ca610e | 6724 | This is only needed when TARGET_TOC, TARGET_MINIMAL_TOC, and there is |
9ebbca7d | 6725 | a constant pool; or for SVR4 -fpic. */ |
c7ca610e RK |
6726 | |
6727 | void | |
9ebbca7d GK |
6728 | rs6000_emit_load_toc_table (fromprolog) |
6729 | int fromprolog; | |
c7ca610e | 6730 | { |
9ebbca7d GK |
6731 | rtx dest; |
6732 | dest = gen_rtx_REG (Pmode, PIC_OFFSET_TABLE_REGNUM); | |
c7ca610e | 6733 | |
2bfcf297 | 6734 | if (TARGET_ELF && DEFAULT_ABI != ABI_AIX) |
c7ca610e | 6735 | { |
f607bc57 | 6736 | if (DEFAULT_ABI == ABI_V4 && flag_pic == 1) |
38c1f2d7 | 6737 | { |
9ebbca7d GK |
6738 | rtx temp = (fromprolog |
6739 | ? gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM) | |
6740 | : gen_reg_rtx (Pmode)); | |
2bfcf297 | 6741 | rs6000_maybe_dead (emit_insn (gen_load_toc_v4_pic_si (temp))); |
8cd8f856 | 6742 | rs6000_maybe_dead (emit_move_insn (dest, temp)); |
38c1f2d7 | 6743 | } |
9ebbca7d GK |
6744 | else if (flag_pic == 2) |
6745 | { | |
6746 | char buf[30]; | |
6747 | rtx tempLR = (fromprolog | |
6748 | ? gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM) | |
6749 | : gen_reg_rtx (Pmode)); | |
6750 | rtx temp0 = (fromprolog | |
6751 | ? gen_rtx_REG (Pmode, 0) | |
6752 | : gen_reg_rtx (Pmode)); | |
6753 | rtx symF; | |
6754 | ||
6755 | /* possibly create the toc section */ | |
6756 | if (! toc_initialized) | |
6757 | { | |
6758 | toc_section (); | |
6759 | function_section (current_function_decl); | |
6760 | } | |
6761 | ||
6762 | if (fromprolog) | |
6763 | { | |
6764 | rtx symL; | |
6765 | ||
6766 | ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno); | |
a8a05998 | 6767 | symF = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); |
38c1f2d7 | 6768 | |
9ebbca7d | 6769 | ASM_GENERATE_INTERNAL_LABEL (buf, "LCL", rs6000_pic_labelno); |
a8a05998 | 6770 | symL = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); |
38c1f2d7 | 6771 | |
8cd8f856 GK |
6772 | rs6000_maybe_dead (emit_insn (gen_load_toc_v4_PIC_1 (tempLR, |
6773 | symF))); | |
6774 | rs6000_maybe_dead (emit_move_insn (dest, tempLR)); | |
6775 | rs6000_maybe_dead (emit_insn (gen_load_toc_v4_PIC_2 (temp0, dest, | |
6776 | symL, | |
6777 | symF))); | |
9ebbca7d GK |
6778 | } |
6779 | else | |
6780 | { | |
6781 | rtx tocsym; | |
6782 | static int reload_toc_labelno = 0; | |
6783 | ||
b999aaeb | 6784 | tocsym = gen_rtx_SYMBOL_REF (Pmode, toc_label_name); |
38c1f2d7 | 6785 | |
9ebbca7d | 6786 | ASM_GENERATE_INTERNAL_LABEL (buf, "LCG", reload_toc_labelno++); |
a8a05998 | 6787 | symF = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); |
9ebbca7d | 6788 | |
8cd8f856 GK |
6789 | rs6000_maybe_dead (emit_insn (gen_load_toc_v4_PIC_1b (tempLR, |
6790 | symF, | |
6791 | tocsym))); | |
6792 | rs6000_maybe_dead (emit_move_insn (dest, tempLR)); | |
6793 | rs6000_maybe_dead (emit_move_insn (temp0, | |
6794 | gen_rtx_MEM (Pmode, dest))); | |
9ebbca7d | 6795 | } |
8cd8f856 | 6796 | rs6000_maybe_dead (emit_insn (gen_addsi3 (dest, temp0, dest))); |
9ebbca7d GK |
6797 | } |
6798 | else if (flag_pic == 0 && TARGET_MINIMAL_TOC) | |
6799 | { | |
6800 | /* This is for AIX code running in non-PIC ELF. */ | |
6801 | char buf[30]; | |
6802 | rtx realsym; | |
38c1f2d7 | 6803 | ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1); |
a8a05998 | 6804 | realsym = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); |
9ebbca7d | 6805 | |
8cd8f856 GK |
6806 | rs6000_maybe_dead (emit_insn (gen_elf_high (dest, realsym))); |
6807 | rs6000_maybe_dead (emit_insn (gen_elf_low (dest, dest, realsym))); | |
9ebbca7d GK |
6808 | } |
6809 | else | |
a4f6c312 | 6810 | abort (); |
9ebbca7d GK |
6811 | } |
6812 | else | |
6813 | { | |
6814 | if (TARGET_32BIT) | |
8cd8f856 | 6815 | rs6000_maybe_dead (emit_insn (gen_load_toc_aix_si (dest))); |
9ebbca7d | 6816 | else |
8cd8f856 | 6817 | rs6000_maybe_dead (emit_insn (gen_load_toc_aix_di (dest))); |
9ebbca7d GK |
6818 | } |
6819 | } | |
6820 | ||
6821 | int | |
6822 | get_TOC_alias_set () | |
6823 | { | |
6824 | static int set = -1; | |
6825 | if (set == -1) | |
6826 | set = new_alias_set (); | |
6827 | return set; | |
6828 | } | |
6829 | ||
6830 | /* This retuns nonzero if the current function uses the TOC. This is | |
6831 | determined by the presence of (unspec ... 7), which is generated by | |
6832 | the various load_toc_* patterns. */ | |
a4f6c312 | 6833 | |
9ebbca7d GK |
6834 | int |
6835 | uses_TOC () | |
6836 | { | |
6837 | rtx insn; | |
38c1f2d7 | 6838 | |
9ebbca7d | 6839 | for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) |
2c3c49de | 6840 | if (INSN_P (insn)) |
9ebbca7d GK |
6841 | { |
6842 | rtx pat = PATTERN (insn); | |
6843 | int i; | |
6844 | ||
8cd8f856 | 6845 | if (GET_CODE (pat) == PARALLEL) |
9ebbca7d GK |
6846 | for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++) |
6847 | if (GET_CODE (XVECEXP (PATTERN (insn), 0, i)) == UNSPEC | |
6848 | && XINT (XVECEXP (PATTERN (insn), 0, i), 1) == 7) | |
6849 | return 1; | |
38c1f2d7 | 6850 | } |
9ebbca7d GK |
6851 | return 0; |
6852 | } | |
38c1f2d7 | 6853 | |
9ebbca7d | 6854 | rtx |
a4f6c312 | 6855 | create_TOC_reference (symbol) |
9ebbca7d GK |
6856 | rtx symbol; |
6857 | { | |
a8a05998 ZW |
6858 | return gen_rtx_PLUS (Pmode, |
6859 | gen_rtx_REG (Pmode, TOC_REGISTER), | |
6860 | gen_rtx_CONST (Pmode, | |
6861 | gen_rtx_MINUS (Pmode, symbol, | |
b999aaeb | 6862 | gen_rtx_SYMBOL_REF (Pmode, toc_label_name)))); |
9ebbca7d | 6863 | } |
38c1f2d7 | 6864 | |
9ebbca7d GK |
6865 | #if TARGET_AIX |
6866 | /* __throw will restore its own return address to be the same as the | |
6867 | return address of the function that the throw is being made to. | |
6868 | This is unfortunate, because we want to check the original | |
6869 | return address to see if we need to restore the TOC. | |
6870 | So we have to squirrel it away here. | |
6871 | This is used only in compiling __throw and __rethrow. | |
c7ca610e | 6872 | |
9ebbca7d GK |
6873 | Most of this code should be removed by CSE. */ |
6874 | static rtx insn_after_throw; | |
c7ca610e | 6875 | |
a4f6c312 | 6876 | /* This does the saving... */ |
9ebbca7d GK |
6877 | void |
6878 | rs6000_aix_emit_builtin_unwind_init () | |
6879 | { | |
6880 | rtx mem; | |
6881 | rtx stack_top = gen_reg_rtx (Pmode); | |
6882 | rtx opcode_addr = gen_reg_rtx (Pmode); | |
6883 | ||
6884 | insn_after_throw = gen_reg_rtx (SImode); | |
6885 | ||
6886 | mem = gen_rtx_MEM (Pmode, hard_frame_pointer_rtx); | |
6887 | emit_move_insn (stack_top, mem); | |
6888 | ||
6889 | mem = gen_rtx_MEM (Pmode, | |
6890 | gen_rtx_PLUS (Pmode, stack_top, | |
6891 | GEN_INT (2 * GET_MODE_SIZE (Pmode)))); | |
6892 | emit_move_insn (opcode_addr, mem); | |
6893 | emit_move_insn (insn_after_throw, gen_rtx_MEM (SImode, opcode_addr)); | |
c7ca610e RK |
6894 | } |
6895 | ||
a4f6c312 SS |
6896 | /* Emit insns to _restore_ the TOC register, at runtime (specifically |
6897 | in _eh.o). Only used on AIX. | |
9ebbca7d GK |
6898 | |
6899 | The idea is that on AIX, function calls look like this: | |
6900 | bl somefunction-trampoline | |
6901 | lwz r2,20(sp) | |
6902 | ||
a4f6c312 | 6903 | and later, |
9ebbca7d GK |
6904 | somefunction-trampoline: |
6905 | stw r2,20(sp) | |
6906 | ... load function address in the count register ... | |
6907 | bctr | |
6908 | or like this, if the linker determines that this is not a cross-module call | |
6909 | and so the TOC need not be restored: | |
6910 | bl somefunction | |
6911 | nop | |
6912 | or like this, if the compiler could determine that this is not a | |
6913 | cross-module call: | |
6914 | bl somefunction | |
6915 | now, the tricky bit here is that register 2 is saved and restored | |
6916 | by the _linker_, so we can't readily generate debugging information | |
6917 | for it. So we need to go back up the call chain looking at the | |
6918 | insns at return addresses to see which calls saved the TOC register | |
6919 | and so see where it gets restored from. | |
6920 | ||
6921 | Oh, and all this gets done in RTL inside the eh_epilogue pattern, | |
6922 | just before the actual epilogue. | |
6923 | ||
6924 | On the bright side, this incurs no space or time overhead unless an | |
6925 | exception is thrown, except for the extra code in libgcc.a. | |
6926 | ||
6927 | The parameter STACKSIZE is a register containing (at runtime) | |
6928 | the amount to be popped off the stack in addition to the stack frame | |
6929 | of this routine (which will be __throw or __rethrow, and so is | |
6930 | guaranteed to have a stack frame). */ | |
a4f6c312 | 6931 | |
9ebbca7d GK |
6932 | void |
6933 | rs6000_emit_eh_toc_restore (stacksize) | |
6934 | rtx stacksize; | |
6935 | { | |
6936 | rtx top_of_stack; | |
6937 | rtx bottom_of_stack = gen_reg_rtx (Pmode); | |
6938 | rtx tocompare = gen_reg_rtx (SImode); | |
6939 | rtx opcode = gen_reg_rtx (SImode); | |
6940 | rtx opcode_addr = gen_reg_rtx (Pmode); | |
6941 | rtx mem; | |
6942 | rtx loop_start = gen_label_rtx (); | |
6943 | rtx no_toc_restore_needed = gen_label_rtx (); | |
6944 | rtx loop_exit = gen_label_rtx (); | |
6945 | ||
6946 | mem = gen_rtx_MEM (Pmode, hard_frame_pointer_rtx); | |
ba4828e0 | 6947 | set_mem_alias_set (mem, rs6000_sr_alias_set); |
9ebbca7d GK |
6948 | emit_move_insn (bottom_of_stack, mem); |
6949 | ||
6950 | top_of_stack = expand_binop (Pmode, add_optab, | |
6951 | bottom_of_stack, stacksize, | |
6952 | NULL_RTX, 1, OPTAB_WIDEN); | |
6953 | ||
6954 | emit_move_insn (tocompare, | |
6955 | GEN_INT (trunc_int_for_mode (TARGET_32BIT | |
6956 | ? 0x80410014 | |
6957 | : 0xE8410028, SImode))); | |
6958 | ||
6959 | if (insn_after_throw == NULL_RTX) | |
a4f6c312 | 6960 | abort (); |
9ebbca7d GK |
6961 | emit_move_insn (opcode, insn_after_throw); |
6962 | ||
6496a589 | 6963 | emit_note (NULL, NOTE_INSN_LOOP_BEG); |
9ebbca7d GK |
6964 | emit_label (loop_start); |
6965 | ||
6966 | do_compare_rtx_and_jump (opcode, tocompare, NE, 1, | |
06f4e019 | 6967 | SImode, NULL_RTX, NULL_RTX, |
9ebbca7d GK |
6968 | no_toc_restore_needed); |
6969 | ||
6970 | mem = gen_rtx_MEM (Pmode, | |
6971 | gen_rtx_PLUS (Pmode, bottom_of_stack, | |
6972 | GEN_INT (5 * GET_MODE_SIZE (Pmode)))); | |
6973 | emit_move_insn (gen_rtx_REG (Pmode, 2), mem); | |
6974 | ||
6975 | emit_label (no_toc_restore_needed); | |
6976 | do_compare_rtx_and_jump (top_of_stack, bottom_of_stack, EQ, 1, | |
06f4e019 | 6977 | Pmode, NULL_RTX, NULL_RTX, |
9ebbca7d GK |
6978 | loop_exit); |
6979 | ||
6980 | mem = gen_rtx_MEM (Pmode, bottom_of_stack); | |
ba4828e0 | 6981 | set_mem_alias_set (mem, rs6000_sr_alias_set); |
9ebbca7d GK |
6982 | emit_move_insn (bottom_of_stack, mem); |
6983 | ||
6984 | mem = gen_rtx_MEM (Pmode, | |
6985 | gen_rtx_PLUS (Pmode, bottom_of_stack, | |
6986 | GEN_INT (2 * GET_MODE_SIZE (Pmode)))); | |
6987 | emit_move_insn (opcode_addr, mem); | |
6988 | emit_move_insn (opcode, gen_rtx_MEM (SImode, opcode_addr)); | |
6989 | ||
6496a589 | 6990 | emit_note (NULL, NOTE_INSN_LOOP_CONT); |
9ebbca7d | 6991 | emit_jump (loop_start); |
6496a589 | 6992 | emit_note (NULL, NOTE_INSN_LOOP_END); |
9ebbca7d GK |
6993 | emit_label (loop_exit); |
6994 | } | |
6995 | #endif /* TARGET_AIX */ | |
38c1f2d7 | 6996 | \f |
ba4828e0 RK |
6997 | /* This ties together stack memory (MEM with an alias set of |
6998 | rs6000_sr_alias_set) and the change to the stack pointer. */ | |
6999 | ||
9ebbca7d GK |
7000 | static void |
7001 | rs6000_emit_stack_tie () | |
7002 | { | |
ba4828e0 RK |
7003 | rtx mem = gen_rtx_MEM (BLKmode, gen_rtx_REG (Pmode, STACK_POINTER_REGNUM)); |
7004 | ||
7005 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
9ebbca7d GK |
7006 | emit_insn (gen_stack_tie (mem)); |
7007 | } | |
38c1f2d7 | 7008 | |
9ebbca7d GK |
7009 | /* Emit the correct code for allocating stack space, as insns. |
7010 | If COPY_R12, make sure a copy of the old frame is left in r12. | |
7011 | The generated code may use hard register 0 as a temporary. */ | |
7012 | ||
7013 | static void | |
7014 | rs6000_emit_allocate_stack (size, copy_r12) | |
7015 | HOST_WIDE_INT size; | |
38c1f2d7 MM |
7016 | int copy_r12; |
7017 | { | |
9ebbca7d GK |
7018 | rtx insn; |
7019 | rtx stack_reg = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM); | |
7020 | rtx tmp_reg = gen_rtx_REG (Pmode, 0); | |
7021 | rtx todec = GEN_INT (-size); | |
a157febd GK |
7022 | |
7023 | if (current_function_limit_stack) | |
7024 | { | |
7025 | if (REG_P (stack_limit_rtx) | |
7026 | && REGNO (stack_limit_rtx) > 1 | |
7027 | && REGNO (stack_limit_rtx) <= 31) | |
7028 | { | |
9ebbca7d GK |
7029 | emit_insn (Pmode == SImode |
7030 | ? gen_addsi3 (tmp_reg, | |
7031 | stack_limit_rtx, | |
7032 | GEN_INT (size)) | |
7033 | : gen_adddi3 (tmp_reg, | |
7034 | stack_limit_rtx, | |
7035 | GEN_INT (size))); | |
7036 | ||
7037 | emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg, | |
7038 | const0_rtx)); | |
a157febd GK |
7039 | } |
7040 | else if (GET_CODE (stack_limit_rtx) == SYMBOL_REF | |
9ebbca7d | 7041 | && TARGET_32BIT |
f607bc57 | 7042 | && DEFAULT_ABI == ABI_V4) |
a157febd | 7043 | { |
9ebbca7d GK |
7044 | rtx toload = gen_rtx_CONST (VOIDmode, |
7045 | gen_rtx_PLUS (Pmode, | |
7046 | stack_limit_rtx, | |
7047 | GEN_INT (size))); | |
7048 | ||
7049 | emit_insn (gen_elf_high (tmp_reg, toload)); | |
7050 | emit_insn (gen_elf_low (tmp_reg, tmp_reg, toload)); | |
7051 | emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg, | |
7052 | const0_rtx)); | |
a157febd GK |
7053 | } |
7054 | else | |
7055 | warning ("stack limit expression is not supported"); | |
7056 | } | |
7057 | ||
9ebbca7d GK |
7058 | if (copy_r12 || ! TARGET_UPDATE) |
7059 | emit_move_insn (gen_rtx_REG (Pmode, 12), stack_reg); | |
7060 | ||
38c1f2d7 MM |
7061 | if (TARGET_UPDATE) |
7062 | { | |
9ebbca7d | 7063 | if (size > 32767) |
38c1f2d7 | 7064 | { |
9ebbca7d GK |
7065 | /* Need a note here so that try_split doesn't get confused. */ |
7066 | if (get_last_insn() == NULL_RTX) | |
7067 | emit_note (0, NOTE_INSN_DELETED); | |
7068 | insn = emit_move_insn (tmp_reg, todec); | |
7069 | try_split (PATTERN (insn), insn, 0); | |
7070 | todec = tmp_reg; | |
38c1f2d7 | 7071 | } |
9ebbca7d GK |
7072 | |
7073 | if (Pmode == SImode) | |
7074 | insn = emit_insn (gen_movsi_update (stack_reg, stack_reg, | |
7075 | todec, stack_reg)); | |
7076 | else | |
7077 | insn = emit_insn (gen_movdi_update (stack_reg, stack_reg, | |
7078 | todec, stack_reg)); | |
38c1f2d7 MM |
7079 | } |
7080 | else | |
7081 | { | |
9ebbca7d GK |
7082 | if (Pmode == SImode) |
7083 | insn = emit_insn (gen_addsi3 (stack_reg, stack_reg, todec)); | |
38c1f2d7 | 7084 | else |
9ebbca7d GK |
7085 | insn = emit_insn (gen_adddi3 (stack_reg, stack_reg, todec)); |
7086 | emit_move_insn (gen_rtx_MEM (Pmode, stack_reg), | |
7087 | gen_rtx_REG (Pmode, 12)); | |
7088 | } | |
7089 | ||
7090 | RTX_FRAME_RELATED_P (insn) = 1; | |
7091 | REG_NOTES (insn) = | |
7092 | gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, | |
7093 | gen_rtx_SET (VOIDmode, stack_reg, | |
7094 | gen_rtx_PLUS (Pmode, stack_reg, | |
7095 | GEN_INT (-size))), | |
7096 | REG_NOTES (insn)); | |
7097 | } | |
7098 | ||
a4f6c312 SS |
7099 | /* Add to 'insn' a note which is PATTERN (INSN) but with REG replaced |
7100 | with (plus:P (reg 1) VAL), and with REG2 replaced with RREG if REG2 | |
7101 | is not NULL. It would be nice if dwarf2out_frame_debug_expr could | |
7102 | deduce these equivalences by itself so it wasn't necessary to hold | |
7103 | its hand so much. */ | |
9ebbca7d GK |
7104 | |
7105 | static void | |
7106 | rs6000_frame_related (insn, reg, val, reg2, rreg) | |
7107 | rtx insn; | |
7108 | rtx reg; | |
7109 | HOST_WIDE_INT val; | |
7110 | rtx reg2; | |
7111 | rtx rreg; | |
7112 | { | |
7113 | rtx real, temp; | |
7114 | ||
7115 | real = copy_rtx (PATTERN (insn)); | |
7116 | ||
7117 | real = replace_rtx (real, reg, | |
7118 | gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode, | |
7119 | STACK_POINTER_REGNUM), | |
7120 | GEN_INT (val))); | |
7121 | ||
7122 | /* We expect that 'real' is either a SET or a PARALLEL containing | |
7123 | SETs (and possibly other stuff). In a PARALLEL, all the SETs | |
7124 | are important so they all have to be marked RTX_FRAME_RELATED_P. */ | |
7125 | ||
7126 | if (GET_CODE (real) == SET) | |
7127 | { | |
7128 | rtx set = real; | |
7129 | ||
7130 | temp = simplify_rtx (SET_SRC (set)); | |
7131 | if (temp) | |
7132 | SET_SRC (set) = temp; | |
7133 | temp = simplify_rtx (SET_DEST (set)); | |
7134 | if (temp) | |
7135 | SET_DEST (set) = temp; | |
7136 | if (GET_CODE (SET_DEST (set)) == MEM) | |
38c1f2d7 | 7137 | { |
9ebbca7d GK |
7138 | temp = simplify_rtx (XEXP (SET_DEST (set), 0)); |
7139 | if (temp) | |
7140 | XEXP (SET_DEST (set), 0) = temp; | |
38c1f2d7 | 7141 | } |
38c1f2d7 | 7142 | } |
9ebbca7d GK |
7143 | else if (GET_CODE (real) == PARALLEL) |
7144 | { | |
7145 | int i; | |
7146 | for (i = 0; i < XVECLEN (real, 0); i++) | |
7147 | if (GET_CODE (XVECEXP (real, 0, i)) == SET) | |
7148 | { | |
7149 | rtx set = XVECEXP (real, 0, i); | |
7150 | ||
7151 | temp = simplify_rtx (SET_SRC (set)); | |
7152 | if (temp) | |
7153 | SET_SRC (set) = temp; | |
7154 | temp = simplify_rtx (SET_DEST (set)); | |
7155 | if (temp) | |
7156 | SET_DEST (set) = temp; | |
7157 | if (GET_CODE (SET_DEST (set)) == MEM) | |
7158 | { | |
7159 | temp = simplify_rtx (XEXP (SET_DEST (set), 0)); | |
7160 | if (temp) | |
7161 | XEXP (SET_DEST (set), 0) = temp; | |
7162 | } | |
7163 | RTX_FRAME_RELATED_P (set) = 1; | |
7164 | } | |
7165 | } | |
7166 | else | |
a4f6c312 | 7167 | abort (); |
9ebbca7d GK |
7168 | |
7169 | if (reg2 != NULL_RTX) | |
7170 | real = replace_rtx (real, reg2, rreg); | |
7171 | ||
7172 | RTX_FRAME_RELATED_P (insn) = 1; | |
7173 | REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, | |
7174 | real, | |
7175 | REG_NOTES (insn)); | |
38c1f2d7 MM |
7176 | } |
7177 | ||
00b960c7 AH |
7178 | /* Returns an insn that has a vrsave set operation with the |
7179 | appropriate CLOBBERs. */ | |
7180 | ||
7181 | static rtx | |
7182 | generate_set_vrsave (reg, info) | |
7183 | rtx reg; | |
7184 | rs6000_stack_t *info; | |
7185 | { | |
7186 | int nclobs, i; | |
7187 | rtx insn, clobs[TOTAL_ALTIVEC_REGS + 1]; | |
7188 | ||
7189 | clobs[0] = gen_set_vrsave (reg); | |
7190 | ||
7191 | nclobs = 1; | |
7192 | ||
7193 | /* CLOBBER the registers in the mask. */ | |
7194 | ||
7195 | for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i) | |
7196 | if (info->vrsave_mask != 0 && ALTIVEC_REG_BIT (i) != 0) | |
7197 | clobs[nclobs++] = gen_rtx_CLOBBER (VOIDmode, | |
7198 | gen_rtx_REG (V4SImode, i)); | |
7199 | ||
7200 | insn = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (nclobs)); | |
7201 | ||
7202 | for (i = 0; i < nclobs; ++i) | |
7203 | XVECEXP (insn, 0, i) = clobs[i]; | |
7204 | ||
7205 | return insn; | |
7206 | } | |
7207 | ||
9ebbca7d GK |
7208 | /* Emit function prologue as insns. */ |
7209 | ||
9878760c | 7210 | void |
83720594 | 7211 | rs6000_emit_prologue () |
9878760c | 7212 | { |
4697a36c | 7213 | rs6000_stack_t *info = rs6000_stack_info (); |
9ebbca7d GK |
7214 | enum machine_mode reg_mode = TARGET_POWERPC64 ? DImode : SImode; |
7215 | int reg_size = TARGET_POWERPC64 ? 8 : 4; | |
7216 | rtx sp_reg_rtx = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM); | |
7217 | rtx frame_ptr_rtx = gen_rtx_REG (Pmode, 12); | |
7218 | rtx frame_reg_rtx = sp_reg_rtx; | |
7219 | rtx cr_save_rtx = NULL; | |
7220 | rtx insn; | |
7221 | int saving_FPRs_inline; | |
7222 | int using_store_multiple; | |
7223 | HOST_WIDE_INT sp_offset = 0; | |
7224 | ||
7225 | using_store_multiple = (TARGET_MULTIPLE && ! TARGET_POWERPC64 | |
7226 | && info->first_gp_reg_save < 31); | |
7227 | saving_FPRs_inline = (info->first_fp_reg_save == 64 | |
7228 | || FP_SAVE_INLINE (info->first_fp_reg_save)); | |
7229 | ||
7230 | /* For V.4, update stack before we do any saving and set back pointer. */ | |
f607bc57 | 7231 | if (info->push_p && DEFAULT_ABI == ABI_V4) |
9ebbca7d GK |
7232 | { |
7233 | if (info->total_size < 32767) | |
7234 | sp_offset = info->total_size; | |
7235 | else | |
7236 | frame_reg_rtx = frame_ptr_rtx; | |
7237 | rs6000_emit_allocate_stack (info->total_size, | |
7238 | (frame_reg_rtx != sp_reg_rtx | |
7239 | && (info->cr_save_p | |
7240 | || info->lr_save_p | |
7241 | || info->first_fp_reg_save < 64 | |
7242 | || info->first_gp_reg_save < 32 | |
7243 | ))); | |
7244 | if (frame_reg_rtx != sp_reg_rtx) | |
7245 | rs6000_emit_stack_tie (); | |
7246 | } | |
7247 | ||
7248 | /* If we use the link register, get it into r0. */ | |
7249 | if (info->lr_save_p) | |
71f123ca | 7250 | emit_move_insn (gen_rtx_REG (Pmode, 0), |
9ebbca7d GK |
7251 | gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)); |
7252 | ||
7253 | /* If we need to save CR, put it into r12. */ | |
7254 | if (info->cr_save_p && frame_reg_rtx != frame_ptr_rtx) | |
7255 | { | |
7256 | cr_save_rtx = gen_rtx_REG (SImode, 12); | |
7257 | emit_insn (gen_movesi_from_cr (cr_save_rtx)); | |
7258 | } | |
7259 | ||
a4f6c312 SS |
7260 | /* Do any required saving of fpr's. If only one or two to save, do |
7261 | it ourselves. Otherwise, call function. */ | |
9ebbca7d GK |
7262 | if (saving_FPRs_inline) |
7263 | { | |
7264 | int i; | |
7265 | for (i = 0; i < 64 - info->first_fp_reg_save; i++) | |
7266 | if ((regs_ever_live[info->first_fp_reg_save+i] | |
7267 | && ! call_used_regs[info->first_fp_reg_save+i])) | |
7268 | { | |
7269 | rtx addr, reg, mem; | |
7270 | reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i); | |
7271 | addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
7272 | GEN_INT (info->fp_save_offset | |
7273 | + sp_offset | |
a4f6c312 | 7274 | + 8 * i)); |
9ebbca7d | 7275 | mem = gen_rtx_MEM (DFmode, addr); |
ba4828e0 | 7276 | set_mem_alias_set (mem, rs6000_sr_alias_set); |
9ebbca7d GK |
7277 | |
7278 | insn = emit_move_insn (mem, reg); | |
7279 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, | |
7280 | NULL_RTX, NULL_RTX); | |
7281 | } | |
7282 | } | |
7283 | else if (info->first_fp_reg_save != 64) | |
7284 | { | |
7285 | int i; | |
7286 | char rname[30]; | |
520a57c8 | 7287 | const char *alloc_rname; |
9ebbca7d GK |
7288 | rtvec p; |
7289 | p = rtvec_alloc (2 + 64 - info->first_fp_reg_save); | |
7290 | ||
7291 | RTVEC_ELT (p, 0) = gen_rtx_CLOBBER (VOIDmode, | |
7292 | gen_rtx_REG (Pmode, | |
7293 | LINK_REGISTER_REGNUM)); | |
7294 | sprintf (rname, "%s%d%s", SAVE_FP_PREFIX, | |
7295 | info->first_fp_reg_save - 32, SAVE_FP_SUFFIX); | |
a8a05998 | 7296 | alloc_rname = ggc_strdup (rname); |
9ebbca7d GK |
7297 | RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode, |
7298 | gen_rtx_SYMBOL_REF (Pmode, | |
7299 | alloc_rname)); | |
7300 | for (i = 0; i < 64 - info->first_fp_reg_save; i++) | |
7301 | { | |
7302 | rtx addr, reg, mem; | |
7303 | reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i); | |
7304 | addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
7305 | GEN_INT (info->fp_save_offset | |
7306 | + sp_offset + 8*i)); | |
7307 | mem = gen_rtx_MEM (DFmode, addr); | |
ba4828e0 | 7308 | set_mem_alias_set (mem, rs6000_sr_alias_set); |
9ebbca7d GK |
7309 | |
7310 | RTVEC_ELT (p, i + 2) = gen_rtx_SET (VOIDmode, mem, reg); | |
7311 | } | |
7312 | insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p)); | |
7313 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, | |
7314 | NULL_RTX, NULL_RTX); | |
7315 | } | |
b6c9286a | 7316 | |
9ebbca7d GK |
7317 | /* Save GPRs. This is done as a PARALLEL if we are using |
7318 | the store-multiple instructions. */ | |
7319 | if (using_store_multiple) | |
b6c9286a | 7320 | { |
9ebbca7d GK |
7321 | rtvec p, dwarfp; |
7322 | int i; | |
7323 | p = rtvec_alloc (32 - info->first_gp_reg_save); | |
7324 | dwarfp = rtvec_alloc (32 - info->first_gp_reg_save); | |
7325 | for (i = 0; i < 32 - info->first_gp_reg_save; i++) | |
7326 | { | |
7327 | rtx addr, reg, mem; | |
7328 | reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i); | |
7329 | addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
7330 | GEN_INT (info->gp_save_offset | |
7331 | + sp_offset | |
7332 | + reg_size * i)); | |
7333 | mem = gen_rtx_MEM (reg_mode, addr); | |
ba4828e0 | 7334 | set_mem_alias_set (mem, rs6000_sr_alias_set); |
9ebbca7d GK |
7335 | |
7336 | RTVEC_ELT (p, i) = gen_rtx_SET (VOIDmode, mem, reg); | |
7337 | } | |
7338 | insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p)); | |
7339 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, | |
7340 | NULL_RTX, NULL_RTX); | |
b6c9286a MM |
7341 | } |
7342 | else | |
7343 | { | |
9ebbca7d GK |
7344 | int i; |
7345 | for (i = 0; i < 32 - info->first_gp_reg_save; i++) | |
7346 | if ((regs_ever_live[info->first_gp_reg_save+i] | |
7347 | && ! call_used_regs[info->first_gp_reg_save+i]) | |
7348 | || (i+info->first_gp_reg_save == PIC_OFFSET_TABLE_REGNUM | |
f607bc57 ZW |
7349 | && ((DEFAULT_ABI == ABI_V4 && flag_pic == 1) |
7350 | || (DEFAULT_ABI == ABI_DARWIN && flag_pic)))) | |
9ebbca7d GK |
7351 | { |
7352 | rtx addr, reg, mem; | |
7353 | reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i); | |
7354 | addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
7355 | GEN_INT (info->gp_save_offset | |
7356 | + sp_offset | |
7357 | + reg_size * i)); | |
7358 | mem = gen_rtx_MEM (reg_mode, addr); | |
ba4828e0 | 7359 | set_mem_alias_set (mem, rs6000_sr_alias_set); |
9ebbca7d GK |
7360 | |
7361 | insn = emit_move_insn (mem, reg); | |
7362 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, | |
7363 | NULL_RTX, NULL_RTX); | |
7364 | } | |
7365 | } | |
7366 | ||
83720594 RH |
7367 | /* ??? There's no need to emit actual instructions here, but it's the |
7368 | easiest way to get the frame unwind information emitted. */ | |
7369 | if (current_function_calls_eh_return) | |
7370 | { | |
78e1b90d DE |
7371 | unsigned int i, regno; |
7372 | ||
83720594 RH |
7373 | for (i = 0; ; ++i) |
7374 | { | |
7375 | rtx addr, reg, mem; | |
7376 | ||
7377 | regno = EH_RETURN_DATA_REGNO (i); | |
7378 | if (regno == INVALID_REGNUM) | |
7379 | break; | |
7380 | ||
7381 | reg = gen_rtx_REG (reg_mode, regno); | |
7382 | addr = plus_constant (frame_reg_rtx, | |
78e1b90d DE |
7383 | info->ehrd_offset + sp_offset |
7384 | + reg_size * (int) i); | |
83720594 | 7385 | mem = gen_rtx_MEM (reg_mode, addr); |
ba4828e0 | 7386 | set_mem_alias_set (mem, rs6000_sr_alias_set); |
83720594 RH |
7387 | |
7388 | insn = emit_move_insn (mem, reg); | |
7389 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, | |
7390 | NULL_RTX, NULL_RTX); | |
7391 | } | |
7392 | } | |
7393 | ||
9ebbca7d GK |
7394 | /* Save lr if we used it. */ |
7395 | if (info->lr_save_p) | |
7396 | { | |
7397 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
7398 | GEN_INT (info->lr_save_offset + sp_offset)); | |
7399 | rtx reg = gen_rtx_REG (Pmode, 0); | |
7400 | rtx mem = gen_rtx_MEM (Pmode, addr); | |
7401 | /* This should not be of rs6000_sr_alias_set, because of | |
7402 | __builtin_return_address. */ | |
7403 | ||
7404 | insn = emit_move_insn (mem, reg); | |
7405 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, | |
7406 | reg, gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)); | |
7407 | } | |
7408 | ||
7409 | /* Save CR if we use any that must be preserved. */ | |
7410 | if (info->cr_save_p) | |
7411 | { | |
7412 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
7413 | GEN_INT (info->cr_save_offset + sp_offset)); | |
7414 | rtx mem = gen_rtx_MEM (SImode, addr); | |
ba4828e0 RK |
7415 | |
7416 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
9ebbca7d GK |
7417 | |
7418 | /* If r12 was used to hold the original sp, copy cr into r0 now | |
7419 | that it's free. */ | |
7420 | if (REGNO (frame_reg_rtx) == 12) | |
7421 | { | |
7422 | cr_save_rtx = gen_rtx_REG (SImode, 0); | |
7423 | emit_insn (gen_movesi_from_cr (cr_save_rtx)); | |
7424 | } | |
7425 | insn = emit_move_insn (mem, cr_save_rtx); | |
7426 | ||
7427 | /* Now, there's no way that dwarf2out_frame_debug_expr is going | |
7428 | to understand '(unspec:SI [(reg:CC 68) ...] 19)'. But that's | |
7429 | OK. All we have to do is specify that _one_ condition code | |
7430 | register is saved in this stack slot. The thrower's epilogue | |
a1dc9455 FS |
7431 | will then restore all the call-saved registers. |
7432 | We use CR2_REGNO (70) to be compatible with gcc-2.95 on Linux. */ | |
9ebbca7d | 7433 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, |
a1dc9455 | 7434 | cr_save_rtx, gen_rtx_REG (SImode, CR2_REGNO)); |
9ebbca7d GK |
7435 | } |
7436 | ||
7437 | /* Update stack and set back pointer unless this is V.4, | |
7438 | for which it was done previously. */ | |
f607bc57 | 7439 | if (info->push_p && DEFAULT_ABI != ABI_V4) |
9ebbca7d GK |
7440 | rs6000_emit_allocate_stack (info->total_size, FALSE); |
7441 | ||
00b960c7 AH |
7442 | /* Save AltiVec registers if needed. */ |
7443 | if (TARGET_ALTIVEC_ABI && info->altivec_size != 0) | |
7444 | { | |
7445 | int i; | |
7446 | ||
7447 | /* There should be a non inline version of this, for when we | |
7448 | are saving lots of vector registers. */ | |
7449 | for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i) | |
7450 | if (regs_ever_live[i] && ! call_used_regs[i]) | |
7451 | { | |
7452 | rtx addr, areg, savereg, mem; | |
7453 | ||
7454 | savereg = gen_rtx_REG (V4SImode, i); | |
7455 | ||
7456 | areg = gen_rtx_REG (Pmode, 0); | |
7457 | emit_move_insn | |
7458 | (areg, GEN_INT (info->altivec_save_offset | |
7459 | + sp_offset | |
7460 | + 16 * (i - info->first_altivec_reg_save))); | |
7461 | ||
7462 | /* AltiVec addressing mode is [reg+reg]. */ | |
7463 | addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, areg); | |
7464 | mem = gen_rtx_MEM (V4SImode, addr); | |
7465 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
7466 | ||
7467 | insn = emit_move_insn (mem, savereg); | |
7468 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, | |
7469 | NULL_RTX, NULL_RTX); | |
7470 | } | |
7471 | } | |
7472 | ||
7473 | /* VRSAVE is a bit vector representing which AltiVec registers | |
7474 | are used. The OS uses this to determine which vector | |
7475 | registers to save on a context switch. We need to save | |
7476 | VRSAVE on the stack frame, add whatever AltiVec registers we | |
7477 | used in this function, and do the corresponding magic in the | |
7478 | epilogue. */ | |
7479 | ||
7480 | if (TARGET_ALTIVEC && info->vrsave_mask != 0) | |
7481 | { | |
7482 | rtx reg, addr, mem; | |
7483 | ||
7484 | /* Get VRSAVE onto a GPR. */ | |
7485 | reg = gen_rtx_REG (SImode, 12); | |
7486 | emit_insn (gen_get_vrsave (reg)); | |
7487 | ||
7488 | /* Save VRSAVE. */ | |
7489 | addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
7490 | GEN_INT (info->vrsave_save_offset + sp_offset)); | |
7491 | mem = gen_rtx_MEM (SImode, addr); | |
7492 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
7493 | insn = emit_move_insn (mem, reg); | |
7494 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, | |
7495 | NULL_RTX, NULL_RTX); | |
7496 | ||
7497 | /* Include the registers in the mask. */ | |
7498 | emit_insn (gen_iorsi3 (reg, reg, GEN_INT ((int) info->vrsave_mask))); | |
7499 | ||
7500 | insn = emit_insn (generate_set_vrsave (reg, info)); | |
7501 | ||
7502 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, | |
7503 | NULL_RTX, NULL_RTX); | |
7504 | } | |
7505 | ||
9ebbca7d GK |
7506 | /* Set frame pointer, if needed. */ |
7507 | if (frame_pointer_needed) | |
7508 | { | |
7509 | insn = emit_move_insn (gen_rtx_REG (reg_mode, FRAME_POINTER_REGNUM), | |
7510 | sp_reg_rtx); | |
7511 | RTX_FRAME_RELATED_P (insn) = 1; | |
b6c9286a | 7512 | } |
9878760c | 7513 | |
9ebbca7d GK |
7514 | /* If we are using PIC_OFFSET_TABLE_REGNUM, we need to set it up. */ |
7515 | if ((TARGET_TOC && TARGET_MINIMAL_TOC && get_pool_size () != 0) | |
f607bc57 ZW |
7516 | || (DEFAULT_ABI == ABI_V4 && flag_pic == 1 |
7517 | && regs_ever_live[PIC_OFFSET_TABLE_REGNUM])) | |
9ebbca7d GK |
7518 | { |
7519 | /* If emit_load_toc_table will use the link register, we need to save | |
7520 | it. We use R11 for this purpose because emit_load_toc_table | |
7521 | can use register 0. This allows us to use a plain 'blr' to return | |
7522 | from the procedure more often. */ | |
d5fa86ba GK |
7523 | int save_LR_around_toc_setup = (TARGET_ELF && flag_pic != 0 |
7524 | && ! info->lr_save_p | |
7525 | && EXIT_BLOCK_PTR->pred != NULL); | |
9ebbca7d GK |
7526 | if (save_LR_around_toc_setup) |
7527 | emit_move_insn (gen_rtx_REG (Pmode, 11), | |
7528 | gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)); | |
7529 | ||
7530 | rs6000_emit_load_toc_table (TRUE); | |
7531 | ||
7532 | if (save_LR_around_toc_setup) | |
7533 | emit_move_insn (gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM), | |
7534 | gen_rtx_REG (Pmode, 11)); | |
7535 | } | |
ee890fe2 SS |
7536 | |
7537 | if (DEFAULT_ABI == ABI_DARWIN | |
7538 | && flag_pic && current_function_uses_pic_offset_table) | |
7539 | { | |
7540 | rtx dest = gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM); | |
7541 | ||
7542 | rs6000_maybe_dead (emit_insn (gen_load_macho_picbase (dest))); | |
7543 | ||
7544 | rs6000_maybe_dead ( | |
7545 | emit_move_insn (gen_rtx_REG (Pmode, PIC_OFFSET_TABLE_REGNUM), | |
7546 | gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM))); | |
7547 | } | |
9ebbca7d GK |
7548 | } |
7549 | ||
9ebbca7d | 7550 | /* Write function prologue. */ |
a4f6c312 | 7551 | |
08c148a8 NB |
7552 | static void |
7553 | rs6000_output_function_prologue (file, size) | |
9ebbca7d | 7554 | FILE *file; |
08c148a8 | 7555 | HOST_WIDE_INT size ATTRIBUTE_UNUSED; |
9ebbca7d GK |
7556 | { |
7557 | rs6000_stack_t *info = rs6000_stack_info (); | |
7558 | ||
4697a36c MM |
7559 | if (TARGET_DEBUG_STACK) |
7560 | debug_stack_info (info); | |
9878760c | 7561 | |
a4f6c312 SS |
7562 | /* Write .extern for any function we will call to save and restore |
7563 | fp values. */ | |
7564 | if (info->first_fp_reg_save < 64 | |
7565 | && !FP_SAVE_INLINE (info->first_fp_reg_save)) | |
4d30c363 | 7566 | fprintf (file, "\t.extern %s%d%s\n\t.extern %s%d%s\n", |
4697a36c | 7567 | SAVE_FP_PREFIX, info->first_fp_reg_save - 32, SAVE_FP_SUFFIX, |
a4f6c312 SS |
7568 | RESTORE_FP_PREFIX, info->first_fp_reg_save - 32, |
7569 | RESTORE_FP_SUFFIX); | |
9878760c | 7570 | |
c764f757 RK |
7571 | /* Write .extern for AIX common mode routines, if needed. */ |
7572 | if (! TARGET_POWER && ! TARGET_POWERPC && ! common_mode_defined) | |
7573 | { | |
f6709c70 JW |
7574 | fputs ("\t.extern __mulh\n", file); |
7575 | fputs ("\t.extern __mull\n", file); | |
7576 | fputs ("\t.extern __divss\n", file); | |
7577 | fputs ("\t.extern __divus\n", file); | |
7578 | fputs ("\t.extern __quoss\n", file); | |
7579 | fputs ("\t.extern __quous\n", file); | |
c764f757 RK |
7580 | common_mode_defined = 1; |
7581 | } | |
9878760c | 7582 | |
9ebbca7d | 7583 | if (! HAVE_prologue) |
979721f8 | 7584 | { |
9ebbca7d GK |
7585 | start_sequence (); |
7586 | ||
a4f6c312 SS |
7587 | /* A NOTE_INSN_DELETED is supposed to be at the start and end of |
7588 | the "toplevel" insn chain. */ | |
9ebbca7d GK |
7589 | emit_note (0, NOTE_INSN_DELETED); |
7590 | rs6000_emit_prologue (); | |
7591 | emit_note (0, NOTE_INSN_DELETED); | |
7592 | ||
7593 | if (TARGET_DEBUG_STACK) | |
a4f6c312 SS |
7594 | debug_rtx_list (get_insns (), 100); |
7595 | final (get_insns (), file, FALSE, FALSE); | |
9ebbca7d | 7596 | end_sequence (); |
979721f8 MM |
7597 | } |
7598 | ||
9ebbca7d GK |
7599 | rs6000_pic_labelno++; |
7600 | } | |
7601 | ||
7602 | /* Emit function epilogue as insns. | |
9878760c | 7603 | |
9ebbca7d GK |
7604 | At present, dwarf2out_frame_debug_expr doesn't understand |
7605 | register restores, so we don't bother setting RTX_FRAME_RELATED_P | |
7606 | anywhere in the epilogue. Most of the insns below would in any case | |
7607 | need special notes to explain where r11 is in relation to the stack. */ | |
9878760c | 7608 | |
9ebbca7d | 7609 | void |
83720594 | 7610 | rs6000_emit_epilogue (sibcall) |
9ebbca7d GK |
7611 | int sibcall; |
7612 | { | |
7613 | rs6000_stack_t *info; | |
7614 | int restoring_FPRs_inline; | |
7615 | int using_load_multiple; | |
7616 | int using_mfcr_multiple; | |
7617 | int use_backchain_to_restore_sp; | |
7618 | int sp_offset = 0; | |
7619 | rtx sp_reg_rtx = gen_rtx_REG (Pmode, 1); | |
7620 | rtx frame_reg_rtx = sp_reg_rtx; | |
7621 | enum machine_mode reg_mode = TARGET_POWERPC64 ? DImode : SImode; | |
7622 | int reg_size = TARGET_POWERPC64 ? 8 : 4; | |
7623 | int i; | |
7624 | ||
7625 | info = rs6000_stack_info (); | |
7626 | using_load_multiple = (TARGET_MULTIPLE && ! TARGET_POWERPC64 | |
7627 | && info->first_gp_reg_save < 31); | |
7628 | restoring_FPRs_inline = (sibcall | |
83720594 | 7629 | || current_function_calls_eh_return |
9ebbca7d GK |
7630 | || info->first_fp_reg_save == 64 |
7631 | || FP_SAVE_INLINE (info->first_fp_reg_save)); | |
7632 | use_backchain_to_restore_sp = (frame_pointer_needed | |
7633 | || current_function_calls_alloca | |
7634 | || info->total_size > 32767); | |
7635 | using_mfcr_multiple = (rs6000_cpu == PROCESSOR_PPC601 | |
7636 | || rs6000_cpu == PROCESSOR_PPC603 | |
7637 | || rs6000_cpu == PROCESSOR_PPC750 | |
7638 | || optimize_size); | |
7639 | ||
7640 | /* If we have a frame pointer, a call to alloca, or a large stack | |
7641 | frame, restore the old stack pointer using the backchain. Otherwise, | |
7642 | we know what size to update it with. */ | |
7643 | if (use_backchain_to_restore_sp) | |
bacbde18 | 7644 | { |
9ebbca7d GK |
7645 | /* Under V.4, don't reset the stack pointer until after we're done |
7646 | loading the saved registers. */ | |
f607bc57 | 7647 | if (DEFAULT_ABI == ABI_V4) |
9ebbca7d | 7648 | frame_reg_rtx = gen_rtx_REG (Pmode, 11); |
4697a36c | 7649 | |
9ebbca7d GK |
7650 | emit_move_insn (frame_reg_rtx, |
7651 | gen_rtx_MEM (Pmode, sp_reg_rtx)); | |
7652 | ||
bacbde18 | 7653 | } |
9ebbca7d | 7654 | else if (info->push_p) |
85638c0d | 7655 | { |
f607bc57 | 7656 | if (DEFAULT_ABI == ABI_V4) |
9ebbca7d GK |
7657 | sp_offset = info->total_size; |
7658 | else | |
7659 | { | |
7660 | emit_insn (TARGET_32BIT | |
7661 | ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx, | |
7662 | GEN_INT (info->total_size)) | |
7663 | : gen_adddi3 (sp_reg_rtx, sp_reg_rtx, | |
7664 | GEN_INT (info->total_size))); | |
7665 | } | |
85638c0d | 7666 | } |
9ebbca7d GK |
7667 | |
7668 | /* Get the old lr if we saved it. */ | |
7669 | if (info->lr_save_p) | |
b6c9286a | 7670 | { |
9ebbca7d GK |
7671 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, |
7672 | GEN_INT (info->lr_save_offset + sp_offset)); | |
7673 | rtx mem = gen_rtx_MEM (Pmode, addr); | |
ba4828e0 RK |
7674 | |
7675 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
b6c9286a | 7676 | |
9ebbca7d | 7677 | emit_move_insn (gen_rtx_REG (Pmode, 0), mem); |
b6c9286a | 7678 | } |
9ebbca7d GK |
7679 | |
7680 | /* Get the old cr if we saved it. */ | |
7681 | if (info->cr_save_p) | |
7682 | { | |
7683 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
7684 | GEN_INT (info->cr_save_offset + sp_offset)); | |
7685 | rtx mem = gen_rtx_MEM (SImode, addr); | |
ba4828e0 RK |
7686 | |
7687 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
b6c9286a | 7688 | |
9ebbca7d GK |
7689 | emit_move_insn (gen_rtx_REG (SImode, 12), mem); |
7690 | } | |
7691 | ||
7692 | /* Set LR here to try to overlap restores below. */ | |
4697a36c | 7693 | if (info->lr_save_p) |
9ebbca7d GK |
7694 | emit_move_insn (gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM), |
7695 | gen_rtx_REG (Pmode, 0)); | |
7696 | ||
83720594 RH |
7697 | /* Load exception handler data registers, if needed. */ |
7698 | if (current_function_calls_eh_return) | |
7699 | { | |
78e1b90d DE |
7700 | unsigned int i, regno; |
7701 | ||
83720594 RH |
7702 | for (i = 0; ; ++i) |
7703 | { | |
7704 | rtx addr, mem; | |
7705 | ||
7706 | regno = EH_RETURN_DATA_REGNO (i); | |
7707 | if (regno == INVALID_REGNUM) | |
7708 | break; | |
7709 | ||
7710 | addr = plus_constant (frame_reg_rtx, | |
78e1b90d DE |
7711 | info->ehrd_offset + sp_offset |
7712 | + reg_size * (int) i); | |
83720594 | 7713 | mem = gen_rtx_MEM (reg_mode, addr); |
ba4828e0 | 7714 | set_mem_alias_set (mem, rs6000_sr_alias_set); |
83720594 RH |
7715 | |
7716 | emit_move_insn (gen_rtx_REG (reg_mode, regno), mem); | |
7717 | } | |
7718 | } | |
9ebbca7d GK |
7719 | |
7720 | /* Restore GPRs. This is done as a PARALLEL if we are using | |
7721 | the load-multiple instructions. */ | |
7722 | if (using_load_multiple) | |
979721f8 | 7723 | { |
9ebbca7d GK |
7724 | rtvec p; |
7725 | p = rtvec_alloc (32 - info->first_gp_reg_save); | |
7726 | for (i = 0; i < 32 - info->first_gp_reg_save; i++) | |
979721f8 | 7727 | { |
9ebbca7d GK |
7728 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, |
7729 | GEN_INT (info->gp_save_offset | |
7730 | + sp_offset | |
7731 | + reg_size * i)); | |
7732 | rtx mem = gen_rtx_MEM (reg_mode, addr); | |
ba4828e0 RK |
7733 | |
7734 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
9ebbca7d GK |
7735 | |
7736 | RTVEC_ELT (p, i) = | |
7737 | gen_rtx_SET (VOIDmode, | |
7738 | gen_rtx_REG (reg_mode, info->first_gp_reg_save + i), | |
7739 | mem); | |
979721f8 | 7740 | } |
9ebbca7d | 7741 | emit_insn (gen_rtx_PARALLEL (VOIDmode, p)); |
979721f8 | 7742 | } |
9ebbca7d GK |
7743 | else |
7744 | for (i = 0; i < 32 - info->first_gp_reg_save; i++) | |
7745 | if ((regs_ever_live[info->first_gp_reg_save+i] | |
7746 | && ! call_used_regs[info->first_gp_reg_save+i]) | |
7747 | || (i+info->first_gp_reg_save == PIC_OFFSET_TABLE_REGNUM | |
f607bc57 ZW |
7748 | && ((DEFAULT_ABI == ABI_V4 && flag_pic == 1) |
7749 | || (DEFAULT_ABI == ABI_DARWIN && flag_pic)))) | |
9ebbca7d GK |
7750 | { |
7751 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
7752 | GEN_INT (info->gp_save_offset | |
7753 | + sp_offset | |
7754 | + reg_size * i)); | |
7755 | rtx mem = gen_rtx_MEM (reg_mode, addr); | |
ba4828e0 RK |
7756 | |
7757 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
9ebbca7d GK |
7758 | |
7759 | emit_move_insn (gen_rtx_REG (reg_mode, | |
7760 | info->first_gp_reg_save + i), | |
7761 | mem); | |
7762 | } | |
9878760c | 7763 | |
9ebbca7d GK |
7764 | /* Restore fpr's if we need to do it without calling a function. */ |
7765 | if (restoring_FPRs_inline) | |
7766 | for (i = 0; i < 64 - info->first_fp_reg_save; i++) | |
7767 | if ((regs_ever_live[info->first_fp_reg_save+i] | |
7768 | && ! call_used_regs[info->first_fp_reg_save+i])) | |
7769 | { | |
7770 | rtx addr, mem; | |
7771 | addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
7772 | GEN_INT (info->fp_save_offset | |
7773 | + sp_offset | |
a4f6c312 | 7774 | + 8 * i)); |
9ebbca7d | 7775 | mem = gen_rtx_MEM (DFmode, addr); |
ba4828e0 | 7776 | set_mem_alias_set (mem, rs6000_sr_alias_set); |
9ebbca7d GK |
7777 | |
7778 | emit_move_insn (gen_rtx_REG (DFmode, | |
7779 | info->first_fp_reg_save + i), | |
7780 | mem); | |
7781 | } | |
8d30c4ee | 7782 | |
00b960c7 AH |
7783 | /* Restore AltiVec registers if needed. */ |
7784 | if (TARGET_ALTIVEC_ABI && info->altivec_size != 0) | |
7785 | { | |
7786 | int i; | |
7787 | ||
7788 | for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i) | |
7789 | if (regs_ever_live[i] && ! call_used_regs[i]) | |
7790 | { | |
7791 | rtx addr, areg, mem; | |
7792 | ||
7793 | areg = gen_rtx_REG (Pmode, 0); | |
7794 | emit_move_insn | |
7795 | (areg, GEN_INT (info->altivec_save_offset | |
7796 | + sp_offset | |
7797 | + 16 * (i - info->first_altivec_reg_save))); | |
7798 | ||
7799 | /* AltiVec addressing mode is [reg+reg]. */ | |
7800 | addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, areg); | |
7801 | mem = gen_rtx_MEM (V4SImode, addr); | |
7802 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
7803 | ||
7804 | emit_move_insn (gen_rtx_REG (V4SImode, i), mem); | |
7805 | } | |
7806 | } | |
7807 | ||
7808 | /* Restore VRSAVE if needed. */ | |
7809 | if (TARGET_ALTIVEC_ABI && info->vrsave_mask != 0) | |
7810 | { | |
7811 | rtx addr, mem, reg; | |
7812 | ||
7813 | addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
7814 | GEN_INT (info->vrsave_save_offset + sp_offset)); | |
7815 | mem = gen_rtx_MEM (SImode, addr); | |
7816 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
7817 | reg = gen_rtx_REG (SImode, 12); | |
7818 | emit_move_insn (reg, mem); | |
7819 | ||
7820 | emit_insn (generate_set_vrsave (reg, info)); | |
7821 | } | |
7822 | ||
9ebbca7d GK |
7823 | /* If we saved cr, restore it here. Just those that were used. */ |
7824 | if (info->cr_save_p) | |
979721f8 | 7825 | { |
9ebbca7d | 7826 | rtx r12_rtx = gen_rtx_REG (SImode, 12); |
e35b9579 | 7827 | int count = 0; |
9ebbca7d GK |
7828 | |
7829 | if (using_mfcr_multiple) | |
979721f8 | 7830 | { |
9ebbca7d GK |
7831 | for (i = 0; i < 8; i++) |
7832 | if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i]) | |
e35b9579 | 7833 | count++; |
9ebbca7d | 7834 | if (count == 0) |
e35b9579 GK |
7835 | abort (); |
7836 | } | |
7837 | ||
7838 | if (using_mfcr_multiple && count > 1) | |
7839 | { | |
7840 | rtvec p; | |
7841 | int ndx; | |
9ebbca7d | 7842 | |
e35b9579 | 7843 | p = rtvec_alloc (count); |
9ebbca7d | 7844 | |
e35b9579 | 7845 | ndx = 0; |
9ebbca7d GK |
7846 | for (i = 0; i < 8; i++) |
7847 | if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i]) | |
7848 | { | |
7849 | rtvec r = rtvec_alloc (2); | |
7850 | RTVEC_ELT (r, 0) = r12_rtx; | |
7851 | RTVEC_ELT (r, 1) = GEN_INT (1 << (7-i)); | |
e35b9579 | 7852 | RTVEC_ELT (p, ndx) = |
9ebbca7d GK |
7853 | gen_rtx_SET (VOIDmode, gen_rtx_REG (CCmode, CR0_REGNO+i), |
7854 | gen_rtx_UNSPEC (CCmode, r, 20)); | |
e35b9579 | 7855 | ndx++; |
9ebbca7d GK |
7856 | } |
7857 | emit_insn (gen_rtx_PARALLEL (VOIDmode, p)); | |
e35b9579 GK |
7858 | if (ndx != count) |
7859 | abort (); | |
979721f8 MM |
7860 | } |
7861 | else | |
9ebbca7d GK |
7862 | for (i = 0; i < 8; i++) |
7863 | if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i]) | |
979721f8 | 7864 | { |
9ebbca7d GK |
7865 | emit_insn (gen_movsi_to_cr_one (gen_rtx_REG (CCmode, |
7866 | CR0_REGNO+i), | |
7867 | r12_rtx)); | |
979721f8 | 7868 | } |
979721f8 MM |
7869 | } |
7870 | ||
9ebbca7d GK |
7871 | /* If this is V.4, unwind the stack pointer after all of the loads |
7872 | have been done. We need to emit a block here so that sched | |
7873 | doesn't decide to move the sp change before the register restores | |
7874 | (which may not have any obvious dependency on the stack). This | |
7875 | doesn't hurt performance, because there is no scheduling that can | |
7876 | be done after this point. */ | |
f607bc57 | 7877 | if (DEFAULT_ABI == ABI_V4) |
b6c9286a | 7878 | { |
9ebbca7d GK |
7879 | if (frame_reg_rtx != sp_reg_rtx) |
7880 | rs6000_emit_stack_tie (); | |
b6c9286a | 7881 | |
9ebbca7d | 7882 | if (use_backchain_to_restore_sp) |
b6c9286a | 7883 | { |
9ebbca7d | 7884 | emit_move_insn (sp_reg_rtx, frame_reg_rtx); |
b6c9286a | 7885 | } |
9ebbca7d | 7886 | else if (sp_offset != 0) |
13f1623b | 7887 | { |
9ebbca7d GK |
7888 | emit_insn (Pmode == SImode |
7889 | ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx, | |
7890 | GEN_INT (sp_offset)) | |
7891 | : gen_adddi3 (sp_reg_rtx, sp_reg_rtx, | |
7892 | GEN_INT (sp_offset))); | |
13f1623b | 7893 | } |
9ebbca7d | 7894 | } |
b6c9286a | 7895 | |
83720594 RH |
7896 | if (current_function_calls_eh_return) |
7897 | { | |
7898 | rtx sa = EH_RETURN_STACKADJ_RTX; | |
7899 | emit_insn (Pmode == SImode | |
7900 | ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx, sa) | |
7901 | : gen_adddi3 (sp_reg_rtx, sp_reg_rtx, sa)); | |
7902 | } | |
7903 | ||
9ebbca7d GK |
7904 | if (!sibcall) |
7905 | { | |
7906 | rtvec p; | |
7907 | if (! restoring_FPRs_inline) | |
7908 | p = rtvec_alloc (3 + 64 - info->first_fp_reg_save); | |
7909 | else | |
7910 | p = rtvec_alloc (2); | |
b6c9286a | 7911 | |
e35b9579 GK |
7912 | RTVEC_ELT (p, 0) = gen_rtx_RETURN (VOIDmode); |
7913 | RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode, | |
9ebbca7d GK |
7914 | gen_rtx_REG (Pmode, |
7915 | LINK_REGISTER_REGNUM)); | |
9ebbca7d GK |
7916 | |
7917 | /* If we have to restore more than two FP registers, branch to the | |
7918 | restore function. It will return to our caller. */ | |
7919 | if (! restoring_FPRs_inline) | |
7920 | { | |
7921 | int i; | |
7922 | char rname[30]; | |
520a57c8 | 7923 | const char *alloc_rname; |
979721f8 | 7924 | |
9ebbca7d GK |
7925 | sprintf (rname, "%s%d%s", RESTORE_FP_PREFIX, |
7926 | info->first_fp_reg_save - 32, RESTORE_FP_SUFFIX); | |
a8a05998 | 7927 | alloc_rname = ggc_strdup (rname); |
9ebbca7d GK |
7928 | RTVEC_ELT (p, 2) = gen_rtx_USE (VOIDmode, |
7929 | gen_rtx_SYMBOL_REF (Pmode, | |
7930 | alloc_rname)); | |
b6c9286a | 7931 | |
9ebbca7d GK |
7932 | for (i = 0; i < 64 - info->first_fp_reg_save; i++) |
7933 | { | |
7934 | rtx addr, mem; | |
7935 | addr = gen_rtx_PLUS (Pmode, sp_reg_rtx, | |
7936 | GEN_INT (info->fp_save_offset + 8*i)); | |
7937 | mem = gen_rtx_MEM (DFmode, addr); | |
ba4828e0 | 7938 | set_mem_alias_set (mem, rs6000_sr_alias_set); |
9ebbca7d GK |
7939 | |
7940 | RTVEC_ELT (p, i+3) = | |
7941 | gen_rtx_SET (VOIDmode, | |
7942 | gen_rtx_REG (DFmode, info->first_fp_reg_save + i), | |
7943 | mem); | |
b6c9286a MM |
7944 | } |
7945 | } | |
9ebbca7d GK |
7946 | |
7947 | emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p)); | |
3daf36a4 | 7948 | } |
9878760c RK |
7949 | } |
7950 | ||
7951 | /* Write function epilogue. */ | |
7952 | ||
08c148a8 NB |
7953 | static void |
7954 | rs6000_output_function_epilogue (file, size) | |
9878760c | 7955 | FILE *file; |
08c148a8 | 7956 | HOST_WIDE_INT size ATTRIBUTE_UNUSED; |
9878760c | 7957 | { |
4697a36c | 7958 | rs6000_stack_t *info = rs6000_stack_info (); |
9878760c | 7959 | |
9ebbca7d | 7960 | if (! HAVE_epilogue) |
9878760c | 7961 | { |
9ebbca7d GK |
7962 | rtx insn = get_last_insn (); |
7963 | /* If the last insn was a BARRIER, we don't have to write anything except | |
7964 | the trace table. */ | |
7965 | if (GET_CODE (insn) == NOTE) | |
7966 | insn = prev_nonnote_insn (insn); | |
7967 | if (insn == 0 || GET_CODE (insn) != BARRIER) | |
4697a36c | 7968 | { |
9ebbca7d GK |
7969 | /* This is slightly ugly, but at least we don't have two |
7970 | copies of the epilogue-emitting code. */ | |
7971 | start_sequence (); | |
7972 | ||
7973 | /* A NOTE_INSN_DELETED is supposed to be at the start | |
7974 | and end of the "toplevel" insn chain. */ | |
7975 | emit_note (0, NOTE_INSN_DELETED); | |
7976 | rs6000_emit_epilogue (FALSE); | |
7977 | emit_note (0, NOTE_INSN_DELETED); | |
7978 | ||
7979 | if (TARGET_DEBUG_STACK) | |
a4f6c312 SS |
7980 | debug_rtx_list (get_insns (), 100); |
7981 | final (get_insns (), file, FALSE, FALSE); | |
9ebbca7d | 7982 | end_sequence (); |
4697a36c | 7983 | } |
9878760c | 7984 | } |
b4ac57ab | 7985 | |
9b30bae2 | 7986 | /* Output a traceback table here. See /usr/include/sys/debug.h for info |
314fc5a9 ILT |
7987 | on its format. |
7988 | ||
7989 | We don't output a traceback table if -finhibit-size-directive was | |
7990 | used. The documentation for -finhibit-size-directive reads | |
7991 | ``don't output a @code{.size} assembler directive, or anything | |
7992 | else that would cause trouble if the function is split in the | |
7993 | middle, and the two halves are placed at locations far apart in | |
7994 | memory.'' The traceback table has this property, since it | |
7995 | includes the offset from the start of the function to the | |
4d30c363 MM |
7996 | traceback table itself. |
7997 | ||
7998 | System V.4 Powerpc's (and the embedded ABI derived from it) use a | |
b6c9286a MM |
7999 | different traceback table. */ |
8000 | if (DEFAULT_ABI == ABI_AIX && ! flag_inhibit_size_directive) | |
9b30bae2 | 8001 | { |
3cce094d | 8002 | const char *fname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0); |
3ac88239 | 8003 | const char *language_string = lang_hooks.name; |
314fc5a9 ILT |
8004 | int fixed_parms, float_parms, parm_info; |
8005 | int i; | |
8006 | ||
b6c9286a MM |
8007 | while (*fname == '.') /* V.4 encodes . in the name */ |
8008 | fname++; | |
8009 | ||
314fc5a9 ILT |
8010 | /* Need label immediately before tbtab, so we can compute its offset |
8011 | from the function start. */ | |
8012 | if (*fname == '*') | |
8013 | ++fname; | |
8014 | ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT"); | |
8015 | ASM_OUTPUT_LABEL (file, fname); | |
8016 | ||
8017 | /* The .tbtab pseudo-op can only be used for the first eight | |
8018 | expressions, since it can't handle the possibly variable | |
8019 | length fields that follow. However, if you omit the optional | |
8020 | fields, the assembler outputs zeros for all optional fields | |
8021 | anyways, giving each variable length field is minimum length | |
8022 | (as defined in sys/debug.h). Thus we can not use the .tbtab | |
8023 | pseudo-op at all. */ | |
8024 | ||
8025 | /* An all-zero word flags the start of the tbtab, for debuggers | |
8026 | that have to find it by searching forward from the entry | |
8027 | point or from the current pc. */ | |
19d2d16f | 8028 | fputs ("\t.long 0\n", file); |
314fc5a9 ILT |
8029 | |
8030 | /* Tbtab format type. Use format type 0. */ | |
19d2d16f | 8031 | fputs ("\t.byte 0,", file); |
314fc5a9 ILT |
8032 | |
8033 | /* Language type. Unfortunately, there doesn't seem to be any | |
8034 | official way to get this info, so we use language_string. C | |
8035 | is 0. C++ is 9. No number defined for Obj-C, so use the | |
9517ead8 | 8036 | value for C for now. There is no official value for Java, |
6f573ff9 | 8037 | although IBM appears to be using 13. There is no official value |
f710504c | 8038 | for Chill, so we've chosen 44 pseudo-randomly. */ |
314fc5a9 | 8039 | if (! strcmp (language_string, "GNU C") |
e2c953b6 | 8040 | || ! strcmp (language_string, "GNU Objective-C")) |
314fc5a9 ILT |
8041 | i = 0; |
8042 | else if (! strcmp (language_string, "GNU F77")) | |
8043 | i = 1; | |
8044 | else if (! strcmp (language_string, "GNU Ada")) | |
8045 | i = 3; | |
8b83775b | 8046 | else if (! strcmp (language_string, "GNU Pascal")) |
314fc5a9 ILT |
8047 | i = 2; |
8048 | else if (! strcmp (language_string, "GNU C++")) | |
8049 | i = 9; | |
9517ead8 AG |
8050 | else if (! strcmp (language_string, "GNU Java")) |
8051 | i = 13; | |
6f573ff9 JL |
8052 | else if (! strcmp (language_string, "GNU CHILL")) |
8053 | i = 44; | |
314fc5a9 ILT |
8054 | else |
8055 | abort (); | |
8056 | fprintf (file, "%d,", i); | |
8057 | ||
8058 | /* 8 single bit fields: global linkage (not set for C extern linkage, | |
8059 | apparently a PL/I convention?), out-of-line epilogue/prologue, offset | |
8060 | from start of procedure stored in tbtab, internal function, function | |
8061 | has controlled storage, function has no toc, function uses fp, | |
8062 | function logs/aborts fp operations. */ | |
8063 | /* Assume that fp operations are used if any fp reg must be saved. */ | |
4697a36c | 8064 | fprintf (file, "%d,", (1 << 5) | ((info->first_fp_reg_save != 64) << 1)); |
314fc5a9 ILT |
8065 | |
8066 | /* 6 bitfields: function is interrupt handler, name present in | |
8067 | proc table, function calls alloca, on condition directives | |
8068 | (controls stack walks, 3 bits), saves condition reg, saves | |
8069 | link reg. */ | |
8070 | /* The `function calls alloca' bit seems to be set whenever reg 31 is | |
8071 | set up as a frame pointer, even when there is no alloca call. */ | |
8072 | fprintf (file, "%d,", | |
8073 | ((1 << 6) | (frame_pointer_needed << 5) | |
4697a36c | 8074 | | (info->cr_save_p << 1) | (info->lr_save_p))); |
314fc5a9 ILT |
8075 | |
8076 | /* 3 bitfields: saves backchain, spare bit, number of fpr saved | |
8077 | (6 bits). */ | |
8078 | fprintf (file, "%d,", | |
4697a36c | 8079 | (info->push_p << 7) | (64 - info->first_fp_reg_save)); |
314fc5a9 ILT |
8080 | |
8081 | /* 2 bitfields: spare bits (2 bits), number of gpr saved (6 bits). */ | |
8082 | fprintf (file, "%d,", (32 - first_reg_to_save ())); | |
8083 | ||
8084 | { | |
8085 | /* Compute the parameter info from the function decl argument | |
8086 | list. */ | |
8087 | tree decl; | |
8088 | int next_parm_info_bit; | |
8089 | ||
8090 | next_parm_info_bit = 31; | |
8091 | parm_info = 0; | |
8092 | fixed_parms = 0; | |
8093 | float_parms = 0; | |
8094 | ||
8095 | for (decl = DECL_ARGUMENTS (current_function_decl); | |
8096 | decl; decl = TREE_CHAIN (decl)) | |
8097 | { | |
8098 | rtx parameter = DECL_INCOMING_RTL (decl); | |
8099 | enum machine_mode mode = GET_MODE (parameter); | |
8100 | ||
8101 | if (GET_CODE (parameter) == REG) | |
8102 | { | |
8103 | if (GET_MODE_CLASS (mode) == MODE_FLOAT) | |
8104 | { | |
8105 | int bits; | |
8106 | ||
8107 | float_parms++; | |
8108 | ||
8109 | if (mode == SFmode) | |
8110 | bits = 0x2; | |
8111 | else if (mode == DFmode) | |
8112 | bits = 0x3; | |
8113 | else | |
8114 | abort (); | |
8115 | ||
8116 | /* If only one bit will fit, don't or in this entry. */ | |
8117 | if (next_parm_info_bit > 0) | |
8118 | parm_info |= (bits << (next_parm_info_bit - 1)); | |
8119 | next_parm_info_bit -= 2; | |
8120 | } | |
8121 | else | |
8122 | { | |
8123 | fixed_parms += ((GET_MODE_SIZE (mode) | |
8124 | + (UNITS_PER_WORD - 1)) | |
8125 | / UNITS_PER_WORD); | |
8126 | next_parm_info_bit -= 1; | |
8127 | } | |
8128 | } | |
8129 | } | |
8130 | } | |
8131 | ||
8132 | /* Number of fixed point parameters. */ | |
8133 | /* This is actually the number of words of fixed point parameters; thus | |
8134 | an 8 byte struct counts as 2; and thus the maximum value is 8. */ | |
8135 | fprintf (file, "%d,", fixed_parms); | |
8136 | ||
8137 | /* 2 bitfields: number of floating point parameters (7 bits), parameters | |
8138 | all on stack. */ | |
8139 | /* This is actually the number of fp registers that hold parameters; | |
8140 | and thus the maximum value is 13. */ | |
8141 | /* Set parameters on stack bit if parameters are not in their original | |
8142 | registers, regardless of whether they are on the stack? Xlc | |
8143 | seems to set the bit when not optimizing. */ | |
8144 | fprintf (file, "%d\n", ((float_parms << 1) | (! optimize))); | |
8145 | ||
8146 | /* Optional fields follow. Some are variable length. */ | |
8147 | ||
8148 | /* Parameter types, left adjusted bit fields: 0 fixed, 10 single float, | |
8149 | 11 double float. */ | |
8150 | /* There is an entry for each parameter in a register, in the order that | |
8151 | they occur in the parameter list. Any intervening arguments on the | |
8152 | stack are ignored. If the list overflows a long (max possible length | |
8153 | 34 bits) then completely leave off all elements that don't fit. */ | |
8154 | /* Only emit this long if there was at least one parameter. */ | |
8155 | if (fixed_parms || float_parms) | |
8156 | fprintf (file, "\t.long %d\n", parm_info); | |
8157 | ||
8158 | /* Offset from start of code to tb table. */ | |
19d2d16f | 8159 | fputs ("\t.long ", file); |
314fc5a9 | 8160 | ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT"); |
54ee9799 DE |
8161 | #if TARGET_AIX |
8162 | RS6000_OUTPUT_BASENAME (file, fname); | |
8163 | #else | |
9ebbca7d | 8164 | assemble_name (file, fname); |
54ee9799 | 8165 | #endif |
19d2d16f | 8166 | fputs ("-.", file); |
54ee9799 DE |
8167 | #if TARGET_AIX |
8168 | RS6000_OUTPUT_BASENAME (file, fname); | |
8169 | #else | |
9ebbca7d | 8170 | assemble_name (file, fname); |
54ee9799 | 8171 | #endif |
19d2d16f | 8172 | putc ('\n', file); |
314fc5a9 ILT |
8173 | |
8174 | /* Interrupt handler mask. */ | |
8175 | /* Omit this long, since we never set the interrupt handler bit | |
8176 | above. */ | |
8177 | ||
8178 | /* Number of CTL (controlled storage) anchors. */ | |
8179 | /* Omit this long, since the has_ctl bit is never set above. */ | |
8180 | ||
8181 | /* Displacement into stack of each CTL anchor. */ | |
8182 | /* Omit this list of longs, because there are no CTL anchors. */ | |
8183 | ||
8184 | /* Length of function name. */ | |
296b8152 | 8185 | fprintf (file, "\t.short %d\n", (int) strlen (fname)); |
314fc5a9 ILT |
8186 | |
8187 | /* Function name. */ | |
8188 | assemble_string (fname, strlen (fname)); | |
8189 | ||
8190 | /* Register for alloca automatic storage; this is always reg 31. | |
8191 | Only emit this if the alloca bit was set above. */ | |
8192 | if (frame_pointer_needed) | |
19d2d16f | 8193 | fputs ("\t.byte 31\n", file); |
9b30bae2 | 8194 | } |
9878760c | 8195 | } |
17167fd8 | 8196 | \f |
a4f6c312 SS |
8197 | /* A C compound statement that outputs the assembler code for a thunk |
8198 | function, used to implement C++ virtual function calls with | |
8199 | multiple inheritance. The thunk acts as a wrapper around a virtual | |
8200 | function, adjusting the implicit object parameter before handing | |
8201 | control off to the real function. | |
8202 | ||
8203 | First, emit code to add the integer DELTA to the location that | |
8204 | contains the incoming first argument. Assume that this argument | |
8205 | contains a pointer, and is the one used to pass the `this' pointer | |
8206 | in C++. This is the incoming argument *before* the function | |
8207 | prologue, e.g. `%o0' on a sparc. The addition must preserve the | |
8208 | values of all other incoming arguments. | |
17167fd8 MM |
8209 | |
8210 | After the addition, emit code to jump to FUNCTION, which is a | |
a4f6c312 SS |
8211 | `FUNCTION_DECL'. This is a direct pure jump, not a call, and does |
8212 | not touch the return address. Hence returning from FUNCTION will | |
8213 | return to whoever called the current `thunk'. | |
17167fd8 | 8214 | |
a4f6c312 SS |
8215 | The effect must be as if FUNCTION had been called directly with the |
8216 | adjusted first argument. This macro is responsible for emitting | |
8217 | all of the code for a thunk function; output_function_prologue() | |
8218 | and output_function_epilogue() are not invoked. | |
17167fd8 | 8219 | |
a4f6c312 SS |
8220 | The THUNK_FNDECL is redundant. (DELTA and FUNCTION have already |
8221 | been extracted from it.) It might possibly be useful on some | |
8222 | targets, but probably not. | |
17167fd8 | 8223 | |
a4f6c312 SS |
8224 | If you do not define this macro, the target-independent code in the |
8225 | C++ frontend will generate a less efficient heavyweight thunk that | |
8226 | calls FUNCTION instead of jumping to it. The generic approach does | |
8227 | not support varargs. */ | |
17167fd8 MM |
8228 | |
8229 | void | |
8230 | output_mi_thunk (file, thunk_fndecl, delta, function) | |
8231 | FILE *file; | |
d330fd93 | 8232 | tree thunk_fndecl ATTRIBUTE_UNUSED; |
17167fd8 MM |
8233 | int delta; |
8234 | tree function; | |
8235 | { | |
a4f6c312 SS |
8236 | const char *this_reg = |
8237 | reg_names[ aggregate_value_p (TREE_TYPE (TREE_TYPE (function))) ? 4 : 3 ]; | |
d330fd93 | 8238 | const char *prefix; |
3cce094d | 8239 | const char *fname; |
d330fd93 | 8240 | const char *r0 = reg_names[0]; |
d330fd93 KG |
8241 | const char *toc = reg_names[2]; |
8242 | const char *schain = reg_names[11]; | |
8243 | const char *r12 = reg_names[12]; | |
17167fd8 MM |
8244 | char buf[512]; |
8245 | static int labelno = 0; | |
8246 | ||
a4f6c312 | 8247 | /* Small constants that can be done by one add instruction. */ |
17167fd8 MM |
8248 | if (delta >= -32768 && delta <= 32767) |
8249 | { | |
22b4a3b0 | 8250 | if (! TARGET_NEW_MNEMONICS) |
17167fd8 MM |
8251 | fprintf (file, "\tcal %s,%d(%s)\n", this_reg, delta, this_reg); |
8252 | else | |
8253 | fprintf (file, "\taddi %s,%s,%d\n", this_reg, this_reg, delta); | |
8254 | } | |
8255 | ||
a4f6c312 | 8256 | /* Large constants that can be done by one addis instruction. */ |
17167fd8 MM |
8257 | else if ((delta & 0xffff) == 0 && num_insns_constant_wide (delta) == 1) |
8258 | asm_fprintf (file, "\t{cau|addis} %s,%s,%d\n", this_reg, this_reg, | |
8259 | delta >> 16); | |
8260 | ||
8261 | /* 32-bit constants that can be done by an add and addis instruction. */ | |
8262 | else if (TARGET_32BIT || num_insns_constant_wide (delta) == 1) | |
8263 | { | |
a4f6c312 SS |
8264 | /* Break into two pieces, propagating the sign bit from the low |
8265 | word to the upper word. */ | |
17167fd8 MM |
8266 | int delta_high = delta >> 16; |
8267 | int delta_low = delta & 0xffff; | |
8268 | if ((delta_low & 0x8000) != 0) | |
8269 | { | |
8270 | delta_high++; | |
8271 | delta_low = (delta_low ^ 0x8000) - 0x8000; /* sign extend */ | |
8272 | } | |
8273 | ||
8274 | asm_fprintf (file, "\t{cau|addis} %s,%s,%d\n", this_reg, this_reg, | |
8275 | delta_high); | |
8276 | ||
22b4a3b0 | 8277 | if (! TARGET_NEW_MNEMONICS) |
17167fd8 MM |
8278 | fprintf (file, "\tcal %s,%d(%s)\n", this_reg, delta_low, this_reg); |
8279 | else | |
8280 | fprintf (file, "\taddi %s,%s,%d\n", this_reg, this_reg, delta_low); | |
8281 | } | |
8282 | ||
8283 | /* 64-bit constants, fixme */ | |
8284 | else | |
8285 | abort (); | |
8286 | ||
8287 | /* Get the prefix in front of the names. */ | |
8288 | switch (DEFAULT_ABI) | |
8289 | { | |
8290 | default: | |
8291 | abort (); | |
8292 | ||
8293 | case ABI_AIX: | |
8294 | prefix = "."; | |
8295 | break; | |
8296 | ||
8297 | case ABI_V4: | |
8298 | case ABI_AIX_NODESC: | |
17167fd8 MM |
8299 | prefix = ""; |
8300 | break; | |
17167fd8 MM |
8301 | } |
8302 | ||
8303 | /* If the function is compiled in this module, jump to it directly. | |
8304 | Otherwise, load up its address and jump to it. */ | |
8305 | ||
8306 | fname = XSTR (XEXP (DECL_RTL (function), 0), 0); | |
42820a49 | 8307 | |
9ebbca7d | 8308 | if (current_file_function_operand (XEXP (DECL_RTL (function), 0), VOIDmode) |
22b4a3b0 FS |
8309 | && ! lookup_attribute ("longcall", |
8310 | TYPE_ATTRIBUTES (TREE_TYPE (function)))) | |
17167fd8 MM |
8311 | { |
8312 | fprintf (file, "\tb %s", prefix); | |
8313 | assemble_name (file, fname); | |
22b4a3b0 | 8314 | if (DEFAULT_ABI == ABI_V4 && flag_pic) fputs ("@local", file); |
949ea356 | 8315 | putc ('\n', file); |
17167fd8 MM |
8316 | } |
8317 | ||
8318 | else | |
8319 | { | |
8320 | switch (DEFAULT_ABI) | |
8321 | { | |
8322 | default: | |
17167fd8 MM |
8323 | abort (); |
8324 | ||
8325 | case ABI_AIX: | |
8326 | /* Set up a TOC entry for the function. */ | |
8327 | ASM_GENERATE_INTERNAL_LABEL (buf, "Lthunk", labelno); | |
8328 | toc_section (); | |
8329 | ASM_OUTPUT_INTERNAL_LABEL (file, "Lthunk", labelno); | |
8330 | labelno++; | |
8331 | ||
fa9b5c6b DE |
8332 | if (TARGET_MINIMAL_TOC) |
8333 | fputs (TARGET_32BIT ? "\t.long " : DOUBLE_INT_ASM_OP, file); | |
8334 | else | |
8335 | { | |
8336 | fputs ("\t.tc ", file); | |
8337 | assemble_name (file, fname); | |
8338 | fputs ("[TC],", file); | |
8339 | } | |
8340 | assemble_name (file, fname); | |
17167fd8 MM |
8341 | putc ('\n', file); |
8342 | text_section (); | |
468e8dba DE |
8343 | if (TARGET_MINIMAL_TOC) |
8344 | asm_fprintf (file, (TARGET_32BIT) | |
8345 | ? "\t{l|lwz} %s,%s(%s)\n" : "\tld %s,%s(%s)\n", r12, | |
8346 | TARGET_ELF ? ".LCTOC0@toc" : ".LCTOC..1", toc); | |
d2574c50 | 8347 | asm_fprintf (file, (TARGET_32BIT) ? "\t{l|lwz} %s," : "\tld %s,", r12); |
17167fd8 | 8348 | assemble_name (file, buf); |
468e8dba DE |
8349 | if (TARGET_ELF && TARGET_MINIMAL_TOC) |
8350 | fputs ("-(.LCTOC1)", file); | |
8351 | asm_fprintf (file, "(%s)\n", TARGET_MINIMAL_TOC ? r12 : toc); | |
17167fd8 MM |
8352 | asm_fprintf (file, |
8353 | (TARGET_32BIT) ? "\t{l|lwz} %s,0(%s)\n" : "\tld %s,0(%s)\n", | |
8354 | r0, r12); | |
8355 | ||
8356 | asm_fprintf (file, | |
8357 | (TARGET_32BIT) ? "\t{l|lwz} %s,4(%s)\n" : "\tld %s,8(%s)\n", | |
8358 | toc, r12); | |
8359 | ||
8360 | asm_fprintf (file, "\tmtctr %s\n", r0); | |
8361 | asm_fprintf (file, | |
8362 | (TARGET_32BIT) ? "\t{l|lwz} %s,8(%s)\n" : "\tld %s,16(%s)\n", | |
8363 | schain, r12); | |
8364 | ||
8365 | asm_fprintf (file, "\tbctr\n"); | |
8366 | break; | |
8367 | ||
9ebbca7d | 8368 | case ABI_AIX_NODESC: |
17167fd8 | 8369 | case ABI_V4: |
22b4a3b0 FS |
8370 | fprintf (file, "\tb %s", prefix); |
8371 | assemble_name (file, fname); | |
8372 | if (flag_pic) fputs ("@plt", file); | |
949ea356 | 8373 | putc ('\n', file); |
22b4a3b0 | 8374 | break; |
ee890fe2 SS |
8375 | |
8376 | #if TARGET_MACHO | |
8377 | case ABI_DARWIN: | |
8378 | fprintf (file, "\tb %s", prefix); | |
8379 | if (flag_pic && !machopic_name_defined_p (fname)) | |
8380 | assemble_name (file, machopic_stub_name (fname)); | |
8381 | else | |
8382 | assemble_name (file, fname); | |
8383 | putc ('\n', file); | |
8384 | break; | |
8385 | #endif | |
9ebbca7d GK |
8386 | } |
8387 | } | |
8388 | } | |
42820a49 | 8389 | |
9ebbca7d GK |
8390 | \f |
8391 | /* A quick summary of the various types of 'constant-pool tables' | |
8392 | under PowerPC: | |
8393 | ||
8394 | Target Flags Name One table per | |
8395 | AIX (none) AIX TOC object file | |
8396 | AIX -mfull-toc AIX TOC object file | |
8397 | AIX -mminimal-toc AIX minimal TOC translation unit | |
8398 | SVR4/EABI (none) SVR4 SDATA object file | |
8399 | SVR4/EABI -fpic SVR4 pic object file | |
8400 | SVR4/EABI -fPIC SVR4 PIC translation unit | |
8401 | SVR4/EABI -mrelocatable EABI TOC function | |
8402 | SVR4/EABI -maix AIX TOC object file | |
8403 | SVR4/EABI -maix -mminimal-toc | |
8404 | AIX minimal TOC translation unit | |
8405 | ||
8406 | Name Reg. Set by entries contains: | |
8407 | made by addrs? fp? sum? | |
8408 | ||
8409 | AIX TOC 2 crt0 as Y option option | |
8410 | AIX minimal TOC 30 prolog gcc Y Y option | |
8411 | SVR4 SDATA 13 crt0 gcc N Y N | |
8412 | SVR4 pic 30 prolog ld Y not yet N | |
8413 | SVR4 PIC 30 prolog gcc Y option option | |
8414 | EABI TOC 30 prolog gcc Y option option | |
8415 | ||
8416 | */ | |
8417 | ||
8418 | /* Hash table stuff for keeping track of TOC entries. */ | |
8419 | ||
8420 | struct toc_hash_struct | |
8421 | { | |
8422 | /* `key' will satisfy CONSTANT_P; in fact, it will satisfy | |
8423 | ASM_OUTPUT_SPECIAL_POOL_ENTRY_P. */ | |
8424 | rtx key; | |
a9098fd0 | 8425 | enum machine_mode key_mode; |
9ebbca7d GK |
8426 | int labelno; |
8427 | }; | |
17167fd8 | 8428 | |
9ebbca7d GK |
8429 | static htab_t toc_hash_table; |
8430 | ||
8431 | /* Hash functions for the hash table. */ | |
8432 | ||
8433 | static unsigned | |
8434 | rs6000_hash_constant (k) | |
8435 | rtx k; | |
8436 | { | |
a9098fd0 | 8437 | unsigned result = (GET_CODE (k) << 3) ^ GET_MODE (k); |
9ebbca7d GK |
8438 | const char *format = GET_RTX_FORMAT (GET_CODE (k)); |
8439 | int flen = strlen (format); | |
8440 | int fidx; | |
8441 | ||
8442 | if (GET_CODE (k) == LABEL_REF) | |
832ea3b3 | 8443 | return result * 1231 + X0INT (XEXP (k, 0), 3); |
9ebbca7d GK |
8444 | |
8445 | if (GET_CODE (k) == CONST_DOUBLE) | |
592bf28c | 8446 | fidx = 1; |
9ebbca7d GK |
8447 | else if (GET_CODE (k) == CODE_LABEL) |
8448 | fidx = 3; | |
8449 | else | |
8450 | fidx = 0; | |
8451 | ||
8452 | for (; fidx < flen; fidx++) | |
8453 | switch (format[fidx]) | |
8454 | { | |
8455 | case 's': | |
8456 | { | |
8457 | unsigned i, len; | |
8458 | const char *str = XSTR (k, fidx); | |
8459 | len = strlen (str); | |
8460 | result = result * 613 + len; | |
8461 | for (i = 0; i < len; i++) | |
8462 | result = result * 613 + (unsigned) str[i]; | |
17167fd8 MM |
8463 | break; |
8464 | } | |
9ebbca7d GK |
8465 | case 'u': |
8466 | case 'e': | |
8467 | result = result * 1231 + rs6000_hash_constant (XEXP (k, fidx)); | |
8468 | break; | |
8469 | case 'i': | |
8470 | case 'n': | |
8471 | result = result * 613 + (unsigned) XINT (k, fidx); | |
8472 | break; | |
8473 | case 'w': | |
8474 | if (sizeof (unsigned) >= sizeof (HOST_WIDE_INT)) | |
8475 | result = result * 613 + (unsigned) XWINT (k, fidx); | |
8476 | else | |
8477 | { | |
8478 | size_t i; | |
8479 | for (i = 0; i < sizeof(HOST_WIDE_INT)/sizeof(unsigned); i++) | |
8480 | result = result * 613 + (unsigned) (XWINT (k, fidx) | |
8481 | >> CHAR_BIT * i); | |
8482 | } | |
8483 | break; | |
8484 | default: | |
a4f6c312 | 8485 | abort (); |
9ebbca7d GK |
8486 | } |
8487 | return result; | |
8488 | } | |
8489 | ||
8490 | static unsigned | |
8491 | toc_hash_function (hash_entry) | |
8492 | const void * hash_entry; | |
8493 | { | |
a9098fd0 GK |
8494 | const struct toc_hash_struct *thc = |
8495 | (const struct toc_hash_struct *) hash_entry; | |
8496 | return rs6000_hash_constant (thc->key) ^ thc->key_mode; | |
9ebbca7d GK |
8497 | } |
8498 | ||
8499 | /* Compare H1 and H2 for equivalence. */ | |
8500 | ||
8501 | static int | |
8502 | toc_hash_eq (h1, h2) | |
8503 | const void * h1; | |
8504 | const void * h2; | |
8505 | { | |
8506 | rtx r1 = ((const struct toc_hash_struct *) h1)->key; | |
8507 | rtx r2 = ((const struct toc_hash_struct *) h2)->key; | |
8508 | ||
a9098fd0 GK |
8509 | if (((const struct toc_hash_struct *) h1)->key_mode |
8510 | != ((const struct toc_hash_struct *) h2)->key_mode) | |
8511 | return 0; | |
8512 | ||
9ebbca7d GK |
8513 | /* Gotcha: One of these const_doubles will be in memory. |
8514 | The other may be on the constant-pool chain. | |
a4f6c312 | 8515 | So rtx_equal_p will think they are different... */ |
9ebbca7d GK |
8516 | if (r1 == r2) |
8517 | return 1; | |
8518 | if (GET_CODE (r1) != GET_CODE (r2) | |
8519 | || GET_MODE (r1) != GET_MODE (r2)) | |
8520 | return 0; | |
8521 | if (GET_CODE (r1) == CONST_DOUBLE) | |
8522 | { | |
8523 | int format_len = strlen (GET_RTX_FORMAT (CONST_DOUBLE)); | |
8524 | int i; | |
592bf28c | 8525 | for (i = 1; i < format_len; i++) |
9ebbca7d GK |
8526 | if (XWINT (r1, i) != XWINT (r2, i)) |
8527 | return 0; | |
8528 | ||
8529 | return 1; | |
17167fd8 | 8530 | } |
9ebbca7d | 8531 | else if (GET_CODE (r1) == LABEL_REF) |
e4a0656f GK |
8532 | return (CODE_LABEL_NUMBER (XEXP (r1, 0)) |
8533 | == CODE_LABEL_NUMBER (XEXP (r2, 0))); | |
9ebbca7d GK |
8534 | else |
8535 | return rtx_equal_p (r1, r2); | |
8536 | } | |
8537 | ||
8538 | /* Mark the hash table-entry HASH_ENTRY. */ | |
8539 | ||
8540 | static int | |
8541 | toc_hash_mark_entry (hash_slot, unused) | |
2eba1afa | 8542 | void ** hash_slot; |
9ebbca7d GK |
8543 | void * unused ATTRIBUTE_UNUSED; |
8544 | { | |
8545 | const struct toc_hash_struct * hash_entry = | |
8546 | *(const struct toc_hash_struct **) hash_slot; | |
8547 | rtx r = hash_entry->key; | |
8548 | ggc_set_mark (hash_entry); | |
a4f6c312 | 8549 | /* For CODE_LABELS, we don't want to drag in the whole insn chain... */ |
9ebbca7d GK |
8550 | if (GET_CODE (r) == LABEL_REF) |
8551 | { | |
8552 | ggc_set_mark (r); | |
8553 | ggc_set_mark (XEXP (r, 0)); | |
8554 | } | |
8555 | else | |
8556 | ggc_mark_rtx (r); | |
8557 | return 1; | |
8558 | } | |
8559 | ||
8560 | /* Mark all the elements of the TOC hash-table *HT. */ | |
8561 | ||
8562 | static void | |
8563 | toc_hash_mark_table (vht) | |
8564 | void *vht; | |
8565 | { | |
8566 | htab_t *ht = vht; | |
8567 | ||
8568 | htab_traverse (*ht, toc_hash_mark_entry, (void *)0); | |
17167fd8 MM |
8569 | } |
8570 | ||
28e510bd MM |
8571 | /* These are the names given by the C++ front-end to vtables, and |
8572 | vtable-like objects. Ideally, this logic should not be here; | |
8573 | instead, there should be some programmatic way of inquiring as | |
8574 | to whether or not an object is a vtable. */ | |
8575 | ||
8576 | #define VTABLE_NAME_P(NAME) \ | |
8577 | (strncmp ("_vt.", name, strlen("_vt.")) == 0 \ | |
8578 | || strncmp ("_ZTV", name, strlen ("_ZTV")) == 0 \ | |
8579 | || strncmp ("_ZTT", name, strlen ("_ZTT")) == 0 \ | |
8580 | || strncmp ("_ZTC", name, strlen ("_ZTC")) == 0) | |
8581 | ||
8582 | void | |
8583 | rs6000_output_symbol_ref (file, x) | |
8584 | FILE *file; | |
8585 | rtx x; | |
8586 | { | |
8587 | /* Currently C++ toc references to vtables can be emitted before it | |
8588 | is decided whether the vtable is public or private. If this is | |
8589 | the case, then the linker will eventually complain that there is | |
8590 | a reference to an unknown section. Thus, for vtables only, | |
8591 | we emit the TOC reference to reference the symbol and not the | |
8592 | section. */ | |
8593 | const char *name = XSTR (x, 0); | |
54ee9799 DE |
8594 | |
8595 | if (VTABLE_NAME_P (name)) | |
8596 | { | |
8597 | RS6000_OUTPUT_BASENAME (file, name); | |
8598 | } | |
8599 | else | |
8600 | assemble_name (file, name); | |
28e510bd MM |
8601 | } |
8602 | ||
a4f6c312 SS |
8603 | /* Output a TOC entry. We derive the entry name from what is being |
8604 | written. */ | |
9878760c RK |
8605 | |
8606 | void | |
a9098fd0 | 8607 | output_toc (file, x, labelno, mode) |
9878760c RK |
8608 | FILE *file; |
8609 | rtx x; | |
8610 | int labelno; | |
a9098fd0 | 8611 | enum machine_mode mode; |
9878760c RK |
8612 | { |
8613 | char buf[256]; | |
3cce094d | 8614 | const char *name = buf; |
ec940faa | 8615 | const char *real_name; |
9878760c RK |
8616 | rtx base = x; |
8617 | int offset = 0; | |
8618 | ||
4697a36c MM |
8619 | if (TARGET_NO_TOC) |
8620 | abort (); | |
8621 | ||
9ebbca7d GK |
8622 | /* When the linker won't eliminate them, don't output duplicate |
8623 | TOC entries (this happens on AIX if there is any kind of TOC, | |
1f8f4a0b MM |
8624 | and on SVR4 under -fPIC or -mrelocatable). */ |
8625 | if (TARGET_TOC) | |
9ebbca7d GK |
8626 | { |
8627 | struct toc_hash_struct *h; | |
8628 | void * * found; | |
8629 | ||
8630 | h = ggc_alloc (sizeof (*h)); | |
8631 | h->key = x; | |
a9098fd0 | 8632 | h->key_mode = mode; |
9ebbca7d GK |
8633 | h->labelno = labelno; |
8634 | ||
8635 | found = htab_find_slot (toc_hash_table, h, 1); | |
8636 | if (*found == NULL) | |
8637 | *found = h; | |
8638 | else /* This is indeed a duplicate. | |
8639 | Set this label equal to that label. */ | |
8640 | { | |
8641 | fputs ("\t.set ", file); | |
8642 | ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC"); | |
8643 | fprintf (file, "%d,", labelno); | |
8644 | ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC"); | |
8645 | fprintf (file, "%d\n", ((*(const struct toc_hash_struct **) | |
8646 | found)->labelno)); | |
8647 | return; | |
8648 | } | |
8649 | } | |
8650 | ||
8651 | /* If we're going to put a double constant in the TOC, make sure it's | |
8652 | aligned properly when strict alignment is on. */ | |
ff1720ed RK |
8653 | if (GET_CODE (x) == CONST_DOUBLE |
8654 | && STRICT_ALIGNMENT | |
a9098fd0 | 8655 | && GET_MODE_BITSIZE (mode) >= 64 |
ff1720ed RK |
8656 | && ! (TARGET_NO_FP_IN_TOC && ! TARGET_MINIMAL_TOC)) { |
8657 | ASM_OUTPUT_ALIGN (file, 3); | |
8658 | } | |
8659 | ||
9ebbca7d | 8660 | ASM_OUTPUT_INTERNAL_LABEL (file, "LC", labelno); |
9878760c | 8661 | |
37c37a57 RK |
8662 | /* Handle FP constants specially. Note that if we have a minimal |
8663 | TOC, things we put here aren't actually in the TOC, so we can allow | |
8664 | FP constants. */ | |
a9098fd0 | 8665 | if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == DFmode) |
9878760c | 8666 | { |
042259f2 DE |
8667 | REAL_VALUE_TYPE rv; |
8668 | long k[2]; | |
0adc764e | 8669 | |
042259f2 DE |
8670 | REAL_VALUE_FROM_CONST_DOUBLE (rv, x); |
8671 | REAL_VALUE_TO_TARGET_DOUBLE (rv, k); | |
31bfaa0b | 8672 | |
13ded975 DE |
8673 | if (TARGET_64BIT) |
8674 | { | |
8675 | if (TARGET_MINIMAL_TOC) | |
2bfcf297 | 8676 | fputs (DOUBLE_INT_ASM_OP, file); |
13ded975 | 8677 | else |
2bfcf297 DB |
8678 | fprintf (file, "\t.tc FD_%lx_%lx[TC],", k[0], k[1]); |
8679 | fprintf (file, "0x%lx%08lx\n", k[0], k[1]); | |
13ded975 DE |
8680 | return; |
8681 | } | |
1875cc88 | 8682 | else |
13ded975 DE |
8683 | { |
8684 | if (TARGET_MINIMAL_TOC) | |
2bfcf297 | 8685 | fputs ("\t.long ", file); |
13ded975 | 8686 | else |
2bfcf297 DB |
8687 | fprintf (file, "\t.tc FD_%lx_%lx[TC],", k[0], k[1]); |
8688 | fprintf (file, "0x%lx,0x%lx\n", k[0], k[1]); | |
13ded975 DE |
8689 | return; |
8690 | } | |
9878760c | 8691 | } |
a9098fd0 | 8692 | else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == SFmode) |
9878760c | 8693 | { |
042259f2 DE |
8694 | REAL_VALUE_TYPE rv; |
8695 | long l; | |
9878760c | 8696 | |
042259f2 DE |
8697 | REAL_VALUE_FROM_CONST_DOUBLE (rv, x); |
8698 | REAL_VALUE_TO_TARGET_SINGLE (rv, l); | |
8699 | ||
31bfaa0b DE |
8700 | if (TARGET_64BIT) |
8701 | { | |
8702 | if (TARGET_MINIMAL_TOC) | |
2bfcf297 | 8703 | fputs (DOUBLE_INT_ASM_OP, file); |
31bfaa0b | 8704 | else |
2bfcf297 DB |
8705 | fprintf (file, "\t.tc FS_%lx[TC],", l); |
8706 | fprintf (file, "0x%lx00000000\n", l); | |
31bfaa0b DE |
8707 | return; |
8708 | } | |
042259f2 | 8709 | else |
31bfaa0b DE |
8710 | { |
8711 | if (TARGET_MINIMAL_TOC) | |
2bfcf297 | 8712 | fputs ("\t.long ", file); |
31bfaa0b | 8713 | else |
2bfcf297 DB |
8714 | fprintf (file, "\t.tc FS_%lx[TC],", l); |
8715 | fprintf (file, "0x%lx\n", l); | |
31bfaa0b DE |
8716 | return; |
8717 | } | |
042259f2 | 8718 | } |
f176e826 | 8719 | else if (GET_MODE (x) == VOIDmode |
a9098fd0 | 8720 | && (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE)) |
042259f2 | 8721 | { |
e2c953b6 | 8722 | unsigned HOST_WIDE_INT low; |
042259f2 DE |
8723 | HOST_WIDE_INT high; |
8724 | ||
8725 | if (GET_CODE (x) == CONST_DOUBLE) | |
8726 | { | |
8727 | low = CONST_DOUBLE_LOW (x); | |
8728 | high = CONST_DOUBLE_HIGH (x); | |
8729 | } | |
8730 | else | |
8731 | #if HOST_BITS_PER_WIDE_INT == 32 | |
8732 | { | |
8733 | low = INTVAL (x); | |
0858c623 | 8734 | high = (low & 0x80000000) ? ~0 : 0; |
042259f2 DE |
8735 | } |
8736 | #else | |
8737 | { | |
0858c623 | 8738 | low = INTVAL (x) & 0xffffffff; |
042259f2 DE |
8739 | high = (HOST_WIDE_INT) INTVAL (x) >> 32; |
8740 | } | |
8741 | #endif | |
9878760c | 8742 | |
a9098fd0 GK |
8743 | /* TOC entries are always Pmode-sized, but since this |
8744 | is a bigendian machine then if we're putting smaller | |
8745 | integer constants in the TOC we have to pad them. | |
8746 | (This is still a win over putting the constants in | |
8747 | a separate constant pool, because then we'd have | |
02a4ec28 FS |
8748 | to have both a TOC entry _and_ the actual constant.) |
8749 | ||
8750 | For a 32-bit target, CONST_INT values are loaded and shifted | |
8751 | entirely within `low' and can be stored in one TOC entry. */ | |
8752 | ||
8753 | if (TARGET_64BIT && POINTER_SIZE < GET_MODE_BITSIZE (mode)) | |
a9098fd0 | 8754 | abort ();/* It would be easy to make this work, but it doesn't now. */ |
02a4ec28 FS |
8755 | |
8756 | if (POINTER_SIZE > GET_MODE_BITSIZE (mode)) | |
a9098fd0 GK |
8757 | lshift_double (low, high, POINTER_SIZE - GET_MODE_BITSIZE (mode), |
8758 | POINTER_SIZE, &low, &high, 0); | |
8759 | ||
13ded975 DE |
8760 | if (TARGET_64BIT) |
8761 | { | |
8762 | if (TARGET_MINIMAL_TOC) | |
2bfcf297 | 8763 | fputs (DOUBLE_INT_ASM_OP, file); |
13ded975 | 8764 | else |
2bfcf297 DB |
8765 | fprintf (file, "\t.tc ID_%lx_%lx[TC],", (long)high, (long)low); |
8766 | fprintf (file, "0x%lx%08lx\n", (long) high, (long) low); | |
13ded975 DE |
8767 | return; |
8768 | } | |
1875cc88 | 8769 | else |
13ded975 | 8770 | { |
02a4ec28 FS |
8771 | if (POINTER_SIZE < GET_MODE_BITSIZE (mode)) |
8772 | { | |
8773 | if (TARGET_MINIMAL_TOC) | |
2bfcf297 | 8774 | fputs ("\t.long ", file); |
02a4ec28 | 8775 | else |
2bfcf297 DB |
8776 | fprintf (file, "\t.tc ID_%lx_%lx[TC],", |
8777 | (long)high, (long)low); | |
8778 | fprintf (file, "0x%lx,0x%lx\n", (long) high, (long) low); | |
02a4ec28 | 8779 | } |
13ded975 | 8780 | else |
02a4ec28 FS |
8781 | { |
8782 | if (TARGET_MINIMAL_TOC) | |
2bfcf297 | 8783 | fputs ("\t.long ", file); |
02a4ec28 | 8784 | else |
2bfcf297 DB |
8785 | fprintf (file, "\t.tc IS_%lx[TC],", (long) low); |
8786 | fprintf (file, "0x%lx\n", (long) low); | |
02a4ec28 | 8787 | } |
13ded975 DE |
8788 | return; |
8789 | } | |
9878760c RK |
8790 | } |
8791 | ||
8792 | if (GET_CODE (x) == CONST) | |
8793 | { | |
2bfcf297 DB |
8794 | if (GET_CODE (XEXP (x, 0)) != PLUS) |
8795 | abort (); | |
8796 | ||
9878760c RK |
8797 | base = XEXP (XEXP (x, 0), 0); |
8798 | offset = INTVAL (XEXP (XEXP (x, 0), 1)); | |
8799 | } | |
8800 | ||
8801 | if (GET_CODE (base) == SYMBOL_REF) | |
8802 | name = XSTR (base, 0); | |
8803 | else if (GET_CODE (base) == LABEL_REF) | |
8804 | ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (XEXP (base, 0))); | |
8805 | else if (GET_CODE (base) == CODE_LABEL) | |
8806 | ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (base)); | |
8807 | else | |
8808 | abort (); | |
8809 | ||
2e4eb9b0 | 8810 | STRIP_NAME_ENCODING (real_name, name); |
1875cc88 | 8811 | if (TARGET_MINIMAL_TOC) |
2bfcf297 | 8812 | fputs (TARGET_32BIT ? "\t.long " : DOUBLE_INT_ASM_OP, file); |
1875cc88 JW |
8813 | else |
8814 | { | |
b6c9286a | 8815 | fprintf (file, "\t.tc %s", real_name); |
9878760c | 8816 | |
1875cc88 JW |
8817 | if (offset < 0) |
8818 | fprintf (file, ".N%d", - offset); | |
8819 | else if (offset) | |
8820 | fprintf (file, ".P%d", offset); | |
9878760c | 8821 | |
19d2d16f | 8822 | fputs ("[TC],", file); |
1875cc88 | 8823 | } |
581bc4de MM |
8824 | |
8825 | /* Currently C++ toc references to vtables can be emitted before it | |
8826 | is decided whether the vtable is public or private. If this is | |
8827 | the case, then the linker will eventually complain that there is | |
8828 | a TOC reference to an unknown section. Thus, for vtables only, | |
8829 | we emit the TOC reference to reference the symbol and not the | |
8830 | section. */ | |
28e510bd | 8831 | if (VTABLE_NAME_P (name)) |
581bc4de | 8832 | { |
54ee9799 | 8833 | RS6000_OUTPUT_BASENAME (file, name); |
581bc4de MM |
8834 | if (offset < 0) |
8835 | fprintf (file, "%d", offset); | |
8836 | else if (offset > 0) | |
8837 | fprintf (file, "+%d", offset); | |
8838 | } | |
8839 | else | |
8840 | output_addr_const (file, x); | |
19d2d16f | 8841 | putc ('\n', file); |
9878760c RK |
8842 | } |
8843 | \f | |
8844 | /* Output an assembler pseudo-op to write an ASCII string of N characters | |
8845 | starting at P to FILE. | |
8846 | ||
8847 | On the RS/6000, we have to do this using the .byte operation and | |
8848 | write out special characters outside the quoted string. | |
8849 | Also, the assembler is broken; very long strings are truncated, | |
a4f6c312 | 8850 | so we must artificially break them up early. */ |
9878760c RK |
8851 | |
8852 | void | |
8853 | output_ascii (file, p, n) | |
8854 | FILE *file; | |
d330fd93 | 8855 | const char *p; |
9878760c RK |
8856 | int n; |
8857 | { | |
8858 | char c; | |
8859 | int i, count_string; | |
d330fd93 KG |
8860 | const char *for_string = "\t.byte \""; |
8861 | const char *for_decimal = "\t.byte "; | |
8862 | const char *to_close = NULL; | |
9878760c RK |
8863 | |
8864 | count_string = 0; | |
8865 | for (i = 0; i < n; i++) | |
8866 | { | |
8867 | c = *p++; | |
8868 | if (c >= ' ' && c < 0177) | |
8869 | { | |
8870 | if (for_string) | |
8871 | fputs (for_string, file); | |
8872 | putc (c, file); | |
8873 | ||
8874 | /* Write two quotes to get one. */ | |
8875 | if (c == '"') | |
8876 | { | |
8877 | putc (c, file); | |
8878 | ++count_string; | |
8879 | } | |
8880 | ||
8881 | for_string = NULL; | |
8882 | for_decimal = "\"\n\t.byte "; | |
8883 | to_close = "\"\n"; | |
8884 | ++count_string; | |
8885 | ||
8886 | if (count_string >= 512) | |
8887 | { | |
8888 | fputs (to_close, file); | |
8889 | ||
8890 | for_string = "\t.byte \""; | |
8891 | for_decimal = "\t.byte "; | |
8892 | to_close = NULL; | |
8893 | count_string = 0; | |
8894 | } | |
8895 | } | |
8896 | else | |
8897 | { | |
8898 | if (for_decimal) | |
8899 | fputs (for_decimal, file); | |
8900 | fprintf (file, "%d", c); | |
8901 | ||
8902 | for_string = "\n\t.byte \""; | |
8903 | for_decimal = ", "; | |
8904 | to_close = "\n"; | |
8905 | count_string = 0; | |
8906 | } | |
8907 | } | |
8908 | ||
8909 | /* Now close the string if we have written one. Then end the line. */ | |
8910 | if (to_close) | |
9ebbca7d | 8911 | fputs (to_close, file); |
9878760c RK |
8912 | } |
8913 | \f | |
8914 | /* Generate a unique section name for FILENAME for a section type | |
8915 | represented by SECTION_DESC. Output goes into BUF. | |
8916 | ||
8917 | SECTION_DESC can be any string, as long as it is different for each | |
8918 | possible section type. | |
8919 | ||
8920 | We name the section in the same manner as xlc. The name begins with an | |
8921 | underscore followed by the filename (after stripping any leading directory | |
11e5fe42 RK |
8922 | names) with the last period replaced by the string SECTION_DESC. If |
8923 | FILENAME does not contain a period, SECTION_DESC is appended to the end of | |
8924 | the name. */ | |
9878760c RK |
8925 | |
8926 | void | |
8927 | rs6000_gen_section_name (buf, filename, section_desc) | |
8928 | char **buf; | |
9ebbca7d GK |
8929 | const char *filename; |
8930 | const char *section_desc; | |
9878760c | 8931 | { |
9ebbca7d | 8932 | const char *q, *after_last_slash, *last_period = 0; |
9878760c RK |
8933 | char *p; |
8934 | int len; | |
9878760c RK |
8935 | |
8936 | after_last_slash = filename; | |
8937 | for (q = filename; *q; q++) | |
11e5fe42 RK |
8938 | { |
8939 | if (*q == '/') | |
8940 | after_last_slash = q + 1; | |
8941 | else if (*q == '.') | |
8942 | last_period = q; | |
8943 | } | |
9878760c | 8944 | |
11e5fe42 | 8945 | len = strlen (after_last_slash) + strlen (section_desc) + 2; |
9878760c RK |
8946 | *buf = (char *) permalloc (len); |
8947 | ||
8948 | p = *buf; | |
8949 | *p++ = '_'; | |
8950 | ||
8951 | for (q = after_last_slash; *q; q++) | |
8952 | { | |
11e5fe42 | 8953 | if (q == last_period) |
9878760c RK |
8954 | { |
8955 | strcpy (p, section_desc); | |
8956 | p += strlen (section_desc); | |
9878760c RK |
8957 | } |
8958 | ||
e9a780ec | 8959 | else if (ISALNUM (*q)) |
9878760c RK |
8960 | *p++ = *q; |
8961 | } | |
8962 | ||
11e5fe42 | 8963 | if (last_period == 0) |
9878760c RK |
8964 | strcpy (p, section_desc); |
8965 | else | |
8966 | *p = '\0'; | |
8967 | } | |
e165f3f0 | 8968 | \f |
a4f6c312 | 8969 | /* Emit profile function. */ |
411707f4 | 8970 | |
411707f4 CC |
8971 | void |
8972 | output_profile_hook (labelno) | |
8973 | int labelno; | |
8974 | { | |
8480e480 CC |
8975 | if (DEFAULT_ABI == ABI_AIX) |
8976 | { | |
8977 | char buf[30]; | |
40501e5f | 8978 | const char *label_name; |
8480e480 | 8979 | rtx fun; |
411707f4 | 8980 | |
8480e480 | 8981 | labelno += 1; |
411707f4 | 8982 | |
8480e480 CC |
8983 | ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno); |
8984 | STRIP_NAME_ENCODING (label_name, ggc_strdup (buf)); | |
8985 | fun = gen_rtx_SYMBOL_REF (Pmode, label_name); | |
411707f4 | 8986 | |
8480e480 CC |
8987 | emit_library_call (init_one_libfunc (RS6000_MCOUNT), 0, VOIDmode, 1, |
8988 | fun, Pmode); | |
8989 | } | |
ee890fe2 SS |
8990 | else if (DEFAULT_ABI == ABI_DARWIN) |
8991 | { | |
d5fa86ba | 8992 | const char *mcount_name = RS6000_MCOUNT; |
ee890fe2 SS |
8993 | int caller_addr_regno = LINK_REGISTER_REGNUM; |
8994 | ||
8995 | /* Be conservative and always set this, at least for now. */ | |
8996 | current_function_uses_pic_offset_table = 1; | |
8997 | ||
8998 | #if TARGET_MACHO | |
8999 | /* For PIC code, set up a stub and collect the caller's address | |
9000 | from r0, which is where the prologue puts it. */ | |
9001 | if (flag_pic) | |
9002 | { | |
9003 | mcount_name = machopic_stub_name (mcount_name); | |
9004 | if (current_function_uses_pic_offset_table) | |
9005 | caller_addr_regno = 0; | |
9006 | } | |
9007 | #endif | |
9008 | emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mcount_name), | |
9009 | 0, VOIDmode, 1, | |
9010 | gen_rtx_REG (Pmode, caller_addr_regno), Pmode); | |
9011 | } | |
411707f4 CC |
9012 | } |
9013 | ||
a4f6c312 | 9014 | /* Write function profiler code. */ |
e165f3f0 RK |
9015 | |
9016 | void | |
9017 | output_function_profiler (file, labelno) | |
9018 | FILE *file; | |
9019 | int labelno; | |
9020 | { | |
3daf36a4 | 9021 | char buf[100]; |
e165f3f0 | 9022 | |
3daf36a4 | 9023 | ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno); |
38c1f2d7 | 9024 | switch (DEFAULT_ABI) |
3daf36a4 | 9025 | { |
38c1f2d7 MM |
9026 | default: |
9027 | abort (); | |
9028 | ||
9029 | case ABI_V4: | |
38c1f2d7 MM |
9030 | case ABI_AIX_NODESC: |
9031 | fprintf (file, "\tmflr %s\n", reg_names[0]); | |
9032 | if (flag_pic == 1) | |
9033 | { | |
dfdfa60f DE |
9034 | fputs ("\tbl _GLOBAL_OFFSET_TABLE_@local-4\n", file); |
9035 | asm_fprintf (file, "\t{st|stw} %s,4(%s)\n", | |
9036 | reg_names[0], reg_names[1]); | |
17167fd8 | 9037 | asm_fprintf (file, "\tmflr %s\n", reg_names[12]); |
dfdfa60f | 9038 | asm_fprintf (file, "\t{l|lwz} %s,", reg_names[0]); |
38c1f2d7 | 9039 | assemble_name (file, buf); |
17167fd8 | 9040 | asm_fprintf (file, "@got(%s)\n", reg_names[12]); |
38c1f2d7 | 9041 | } |
9ebbca7d | 9042 | else if (flag_pic > 1) |
38c1f2d7 | 9043 | { |
dfdfa60f DE |
9044 | asm_fprintf (file, "\t{st|stw} %s,4(%s)\n", |
9045 | reg_names[0], reg_names[1]); | |
9ebbca7d GK |
9046 | /* Now, we need to get the address of the label. */ |
9047 | fputs ("\tbl 1f\n\t.long ", file); | |
034e84c4 | 9048 | assemble_name (file, buf); |
9ebbca7d GK |
9049 | fputs ("-.\n1:", file); |
9050 | asm_fprintf (file, "\tmflr %s\n", reg_names[11]); | |
9051 | asm_fprintf (file, "\t{l|lwz} %s,0(%s)\n", | |
9052 | reg_names[0], reg_names[11]); | |
9053 | asm_fprintf (file, "\t{cax|add} %s,%s,%s\n", | |
9054 | reg_names[0], reg_names[0], reg_names[11]); | |
38c1f2d7 | 9055 | } |
38c1f2d7 MM |
9056 | else |
9057 | { | |
17167fd8 | 9058 | asm_fprintf (file, "\t{liu|lis} %s,", reg_names[12]); |
38c1f2d7 | 9059 | assemble_name (file, buf); |
dfdfa60f | 9060 | fputs ("@ha\n", file); |
b5253831 DE |
9061 | asm_fprintf (file, "\t{st|stw} %s,4(%s)\n", |
9062 | reg_names[0], reg_names[1]); | |
a260abc9 | 9063 | asm_fprintf (file, "\t{cal|la} %s,", reg_names[0]); |
38c1f2d7 | 9064 | assemble_name (file, buf); |
17167fd8 | 9065 | asm_fprintf (file, "@l(%s)\n", reg_names[12]); |
38c1f2d7 MM |
9066 | } |
9067 | ||
b5253831 DE |
9068 | if (current_function_needs_context) |
9069 | asm_fprintf (file, "\tmr %s,%s\n", | |
9070 | reg_names[30], reg_names[STATIC_CHAIN_REGNUM]); | |
38c1f2d7 | 9071 | fprintf (file, "\tbl %s\n", RS6000_MCOUNT); |
b5253831 DE |
9072 | if (current_function_needs_context) |
9073 | asm_fprintf (file, "\tmr %s,%s\n", | |
9074 | reg_names[STATIC_CHAIN_REGNUM], reg_names[30]); | |
38c1f2d7 MM |
9075 | break; |
9076 | ||
9077 | case ABI_AIX: | |
ee890fe2 | 9078 | case ABI_DARWIN: |
a4f6c312 | 9079 | /* Don't do anything, done in output_profile_hook (). */ |
38c1f2d7 | 9080 | break; |
411707f4 | 9081 | |
38c1f2d7 | 9082 | } |
e165f3f0 | 9083 | } |
a251ffd0 TG |
9084 | |
9085 | /* Adjust the cost of a scheduling dependency. Return the new cost of | |
9086 | a dependency LINK or INSN on DEP_INSN. COST is the current cost. */ | |
9087 | ||
c237e94a | 9088 | static int |
a06faf84 | 9089 | rs6000_adjust_cost (insn, link, dep_insn, cost) |
a251ffd0 TG |
9090 | rtx insn; |
9091 | rtx link; | |
296b8152 | 9092 | rtx dep_insn ATTRIBUTE_UNUSED; |
a251ffd0 TG |
9093 | int cost; |
9094 | { | |
9095 | if (! recog_memoized (insn)) | |
9096 | return 0; | |
9097 | ||
9098 | if (REG_NOTE_KIND (link) != 0) | |
9099 | return 0; | |
9100 | ||
9101 | if (REG_NOTE_KIND (link) == 0) | |
9102 | { | |
ed947a96 DJ |
9103 | /* Data dependency; DEP_INSN writes a register that INSN reads |
9104 | some cycles later. */ | |
9105 | switch (get_attr_type (insn)) | |
9106 | { | |
9107 | case TYPE_JMPREG: | |
9108 | /* Tell the first scheduling pass about the latency between | |
9109 | a mtctr and bctr (and mtlr and br/blr). The first | |
9110 | scheduling pass will not know about this latency since | |
9111 | the mtctr instruction, which has the latency associated | |
9112 | to it, will be generated by reload. */ | |
9113 | return TARGET_POWER ? 5 : 4; | |
9114 | case TYPE_BRANCH: | |
9115 | /* Leave some extra cycles between a compare and its | |
9116 | dependent branch, to inhibit expensive mispredicts. */ | |
9117 | if ((rs6000_cpu_attr == CPU_PPC750 | |
9118 | || rs6000_cpu_attr == CPU_PPC7400 | |
9119 | || rs6000_cpu_attr == CPU_PPC7450) | |
9120 | && recog_memoized (dep_insn) | |
9121 | && (INSN_CODE (dep_insn) >= 0) | |
9122 | && (get_attr_type (dep_insn) == TYPE_COMPARE | |
9123 | || get_attr_type (dep_insn) == TYPE_DELAYED_COMPARE | |
9124 | || get_attr_type (dep_insn) == TYPE_FPCOMPARE | |
9125 | || get_attr_type (dep_insn) == TYPE_CR_LOGICAL)) | |
9126 | return cost + 2; | |
9127 | default: | |
9128 | break; | |
9129 | } | |
a251ffd0 TG |
9130 | /* Fall out to return default cost. */ |
9131 | } | |
9132 | ||
9133 | return cost; | |
9134 | } | |
b6c9286a | 9135 | |
a4f6c312 SS |
9136 | /* A C statement (sans semicolon) to update the integer scheduling |
9137 | priority INSN_PRIORITY (INSN). Reduce the priority to execute the | |
9138 | INSN earlier, increase the priority to execute INSN later. Do not | |
9139 | define this macro if you do not need to adjust the scheduling | |
9140 | priorities of insns. */ | |
bef84347 | 9141 | |
c237e94a | 9142 | static int |
bef84347 | 9143 | rs6000_adjust_priority (insn, priority) |
d330fd93 | 9144 | rtx insn ATTRIBUTE_UNUSED; |
bef84347 VM |
9145 | int priority; |
9146 | { | |
a4f6c312 SS |
9147 | /* On machines (like the 750) which have asymmetric integer units, |
9148 | where one integer unit can do multiply and divides and the other | |
9149 | can't, reduce the priority of multiply/divide so it is scheduled | |
9150 | before other integer operations. */ | |
bef84347 VM |
9151 | |
9152 | #if 0 | |
2c3c49de | 9153 | if (! INSN_P (insn)) |
bef84347 VM |
9154 | return priority; |
9155 | ||
9156 | if (GET_CODE (PATTERN (insn)) == USE) | |
9157 | return priority; | |
9158 | ||
9159 | switch (rs6000_cpu_attr) { | |
9160 | case CPU_PPC750: | |
9161 | switch (get_attr_type (insn)) | |
9162 | { | |
9163 | default: | |
9164 | break; | |
9165 | ||
9166 | case TYPE_IMUL: | |
9167 | case TYPE_IDIV: | |
3cb999d8 DE |
9168 | fprintf (stderr, "priority was %#x (%d) before adjustment\n", |
9169 | priority, priority); | |
bef84347 VM |
9170 | if (priority >= 0 && priority < 0x01000000) |
9171 | priority >>= 3; | |
9172 | break; | |
9173 | } | |
9174 | } | |
9175 | #endif | |
9176 | ||
9177 | return priority; | |
9178 | } | |
9179 | ||
a4f6c312 SS |
9180 | /* Return how many instructions the machine can issue per cycle. */ |
9181 | ||
c237e94a ZW |
9182 | static int |
9183 | rs6000_issue_rate () | |
b6c9286a MM |
9184 | { |
9185 | switch (rs6000_cpu_attr) { | |
3cb999d8 DE |
9186 | case CPU_RIOS1: /* ? */ |
9187 | case CPU_RS64A: | |
9188 | case CPU_PPC601: /* ? */ | |
ed947a96 | 9189 | case CPU_PPC7450: |
3cb999d8 | 9190 | return 3; |
b6c9286a | 9191 | case CPU_PPC603: |
bef84347 | 9192 | case CPU_PPC750: |
ed947a96 | 9193 | case CPU_PPC7400: |
bef84347 | 9194 | return 2; |
3cb999d8 | 9195 | case CPU_RIOS2: |
b6c9286a | 9196 | case CPU_PPC604: |
19684119 | 9197 | case CPU_PPC604E: |
b6c9286a | 9198 | case CPU_PPC620: |
3cb999d8 | 9199 | case CPU_PPC630: |
b6c9286a MM |
9200 | return 4; |
9201 | default: | |
9202 | return 1; | |
9203 | } | |
9204 | } | |
9205 | ||
b6c9286a | 9206 | \f |
b6c9286a MM |
9207 | /* Length in units of the trampoline for entering a nested function. */ |
9208 | ||
9209 | int | |
9210 | rs6000_trampoline_size () | |
9211 | { | |
9212 | int ret = 0; | |
9213 | ||
9214 | switch (DEFAULT_ABI) | |
9215 | { | |
9216 | default: | |
9217 | abort (); | |
9218 | ||
9219 | case ABI_AIX: | |
8f802bfb | 9220 | ret = (TARGET_32BIT) ? 12 : 24; |
b6c9286a MM |
9221 | break; |
9222 | ||
9223 | case ABI_V4: | |
9224 | case ABI_AIX_NODESC: | |
03a7e1a5 | 9225 | ret = (TARGET_32BIT) ? 40 : 48; |
b6c9286a | 9226 | break; |
b6c9286a MM |
9227 | } |
9228 | ||
9229 | return ret; | |
9230 | } | |
9231 | ||
9232 | /* Emit RTL insns to initialize the variable parts of a trampoline. | |
9233 | FNADDR is an RTX for the address of the function's pure code. | |
9234 | CXT is an RTX for the static chain value for the function. */ | |
9235 | ||
9236 | void | |
9237 | rs6000_initialize_trampoline (addr, fnaddr, cxt) | |
9238 | rtx addr; | |
9239 | rtx fnaddr; | |
9240 | rtx cxt; | |
9241 | { | |
ac2a93a1 | 9242 | enum machine_mode pmode = Pmode; |
8bd04c56 MM |
9243 | int regsize = (TARGET_32BIT) ? 4 : 8; |
9244 | rtx ctx_reg = force_reg (pmode, cxt); | |
b6c9286a MM |
9245 | |
9246 | switch (DEFAULT_ABI) | |
9247 | { | |
9248 | default: | |
9249 | abort (); | |
9250 | ||
8bd04c56 | 9251 | /* Macros to shorten the code expansions below. */ |
39403d82 | 9252 | #define MEM_DEREF(addr) gen_rtx_MEM (pmode, memory_address (pmode, addr)) |
c5c76735 JL |
9253 | #define MEM_PLUS(addr,offset) \ |
9254 | gen_rtx_MEM (pmode, memory_address (pmode, plus_constant (addr, offset))) | |
7c59dc5d | 9255 | |
b6c9286a MM |
9256 | /* Under AIX, just build the 3 word function descriptor */ |
9257 | case ABI_AIX: | |
8bd04c56 MM |
9258 | { |
9259 | rtx fn_reg = gen_reg_rtx (pmode); | |
9260 | rtx toc_reg = gen_reg_rtx (pmode); | |
9261 | emit_move_insn (fn_reg, MEM_DEREF (fnaddr)); | |
1cb18e3c | 9262 | emit_move_insn (toc_reg, MEM_PLUS (fnaddr, regsize)); |
8bd04c56 MM |
9263 | emit_move_insn (MEM_DEREF (addr), fn_reg); |
9264 | emit_move_insn (MEM_PLUS (addr, regsize), toc_reg); | |
9265 | emit_move_insn (MEM_PLUS (addr, 2*regsize), ctx_reg); | |
9266 | } | |
b6c9286a MM |
9267 | break; |
9268 | ||
eaf1bcf1 | 9269 | /* Under V.4/eabi, call __trampoline_setup to do the real work. */ |
b6c9286a MM |
9270 | case ABI_V4: |
9271 | case ABI_AIX_NODESC: | |
39403d82 | 9272 | emit_library_call (gen_rtx_SYMBOL_REF (SImode, "__trampoline_setup"), |
eaf1bcf1 MM |
9273 | FALSE, VOIDmode, 4, |
9274 | addr, pmode, | |
9275 | GEN_INT (rs6000_trampoline_size ()), SImode, | |
9276 | fnaddr, pmode, | |
9277 | ctx_reg, pmode); | |
b6c9286a | 9278 | break; |
b6c9286a MM |
9279 | } |
9280 | ||
9281 | return; | |
9282 | } | |
7509c759 MM |
9283 | |
9284 | \f | |
91d231cb | 9285 | /* Table of valid machine attributes. */ |
a4f6c312 | 9286 | |
91d231cb | 9287 | const struct attribute_spec rs6000_attribute_table[] = |
7509c759 | 9288 | { |
91d231cb JM |
9289 | /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */ |
9290 | { "longcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute }, | |
9291 | { NULL, 0, 0, false, false, false, NULL } | |
9292 | }; | |
7509c759 | 9293 | |
a4f6c312 SS |
9294 | /* Handle a "longcall" attribute; arguments as in struct |
9295 | attribute_spec.handler. */ | |
9296 | ||
91d231cb JM |
9297 | static tree |
9298 | rs6000_handle_longcall_attribute (node, name, args, flags, no_add_attrs) | |
9299 | tree *node; | |
9300 | tree name; | |
9301 | tree args ATTRIBUTE_UNUSED; | |
9302 | int flags ATTRIBUTE_UNUSED; | |
9303 | bool *no_add_attrs; | |
9304 | { | |
9305 | if (TREE_CODE (*node) != FUNCTION_TYPE | |
9306 | && TREE_CODE (*node) != FIELD_DECL | |
9307 | && TREE_CODE (*node) != TYPE_DECL) | |
9308 | { | |
9309 | warning ("`%s' attribute only applies to functions", | |
9310 | IDENTIFIER_POINTER (name)); | |
9311 | *no_add_attrs = true; | |
9312 | } | |
6a4cee5f | 9313 | |
91d231cb | 9314 | return NULL_TREE; |
7509c759 MM |
9315 | } |
9316 | ||
3cb999d8 DE |
9317 | /* Return a reference suitable for calling a function with the |
9318 | longcall attribute. */ | |
a4f6c312 | 9319 | |
6a4cee5f MM |
9320 | struct rtx_def * |
9321 | rs6000_longcall_ref (call_ref) | |
9322 | rtx call_ref; | |
9323 | { | |
d330fd93 | 9324 | const char *call_name; |
6a4cee5f MM |
9325 | tree node; |
9326 | ||
9327 | if (GET_CODE (call_ref) != SYMBOL_REF) | |
9328 | return call_ref; | |
9329 | ||
9330 | /* System V adds '.' to the internal name, so skip them. */ | |
9331 | call_name = XSTR (call_ref, 0); | |
9332 | if (*call_name == '.') | |
9333 | { | |
9334 | while (*call_name == '.') | |
9335 | call_name++; | |
9336 | ||
9337 | node = get_identifier (call_name); | |
39403d82 | 9338 | call_ref = gen_rtx_SYMBOL_REF (VOIDmode, IDENTIFIER_POINTER (node)); |
6a4cee5f MM |
9339 | } |
9340 | ||
9341 | return force_reg (Pmode, call_ref); | |
9342 | } | |
9343 | ||
7509c759 MM |
9344 | \f |
9345 | /* A C statement or statements to switch to the appropriate section | |
9346 | for output of RTX in mode MODE. You can assume that RTX is some | |
9347 | kind of constant in RTL. The argument MODE is redundant except in | |
9348 | the case of a `const_int' rtx. Select the section by calling | |
9349 | `text_section' or one of the alternatives for other sections. | |
9350 | ||
9351 | Do not define this macro if you put all constants in the read-only | |
9352 | data section. */ | |
9353 | ||
b91da81f | 9354 | #ifdef USING_ELFOS_H |
7509c759 MM |
9355 | |
9356 | void | |
9357 | rs6000_select_rtx_section (mode, x) | |
a9098fd0 | 9358 | enum machine_mode mode; |
7509c759 MM |
9359 | rtx x; |
9360 | { | |
a9098fd0 | 9361 | if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode)) |
7509c759 | 9362 | toc_section (); |
7509c759 MM |
9363 | else |
9364 | const_section (); | |
9365 | } | |
9366 | ||
9367 | /* A C statement or statements to switch to the appropriate | |
9368 | section for output of DECL. DECL is either a `VAR_DECL' node | |
9369 | or a constant of some sort. RELOC indicates whether forming | |
9370 | the initial value of DECL requires link-time relocations. */ | |
9371 | ||
9372 | void | |
9373 | rs6000_select_section (decl, reloc) | |
9374 | tree decl; | |
9375 | int reloc; | |
9376 | { | |
9377 | int size = int_size_in_bytes (TREE_TYPE (decl)); | |
63019373 GK |
9378 | int needs_sdata; |
9379 | int readonly; | |
9380 | static void (* const sec_funcs[4]) PARAMS ((void)) = { | |
9381 | &const_section, | |
9382 | &sdata2_section, | |
9383 | &data_section, | |
9384 | &sdata_section | |
9385 | }; | |
9386 | ||
9387 | needs_sdata = (size > 0 | |
9388 | && size <= g_switch_value | |
9389 | && rs6000_sdata != SDATA_NONE | |
9390 | && (rs6000_sdata != SDATA_DATA || TREE_PUBLIC (decl))); | |
7509c759 MM |
9391 | |
9392 | if (TREE_CODE (decl) == STRING_CST) | |
63019373 | 9393 | readonly = ! flag_writable_strings; |
a9098fd0 | 9394 | else if (TREE_CODE (decl) == VAR_DECL) |
63019373 GK |
9395 | readonly = (! (flag_pic && reloc) |
9396 | && TREE_READONLY (decl) | |
9397 | && ! TREE_SIDE_EFFECTS (decl) | |
9398 | && DECL_INITIAL (decl) | |
9399 | && DECL_INITIAL (decl) != error_mark_node | |
9400 | && TREE_CONSTANT (DECL_INITIAL (decl))); | |
ac4f7ad9 GK |
9401 | else if (TREE_CODE (decl) == CONSTRUCTOR) |
9402 | readonly = (! (flag_pic && reloc) | |
ac4f7ad9 | 9403 | && ! TREE_SIDE_EFFECTS (decl) |
f3afc192 | 9404 | && TREE_CONSTANT (decl)); |
7509c759 | 9405 | else |
63019373 GK |
9406 | readonly = 1; |
9407 | if (needs_sdata && rs6000_sdata != SDATA_EABI) | |
9408 | readonly = 0; | |
9409 | ||
9410 | (*sec_funcs[(readonly ? 0 : 2) + (needs_sdata ? 1 : 0)])(); | |
9411 | } | |
9412 | ||
9413 | /* A C statement to build up a unique section name, expressed as a | |
9414 | STRING_CST node, and assign it to DECL_SECTION_NAME (decl). | |
9415 | RELOC indicates whether the initial value of EXP requires | |
9416 | link-time relocations. If you do not define this macro, GCC will use | |
9417 | the symbol name prefixed by `.' as the section name. Note - this | |
f5143c46 | 9418 | macro can now be called for uninitialized data items as well as |
63019373 GK |
9419 | initialised data and functions. */ |
9420 | ||
9421 | void | |
9422 | rs6000_unique_section (decl, reloc) | |
9423 | tree decl; | |
9424 | int reloc; | |
9425 | { | |
9426 | int size = int_size_in_bytes (TREE_TYPE (decl)); | |
9427 | int needs_sdata; | |
9428 | int readonly; | |
9429 | int len; | |
9430 | int sec; | |
9431 | const char *name; | |
9432 | char *string; | |
9433 | const char *prefix; | |
9434 | ||
9435 | static const char *const prefixes[7][2] = | |
9436 | { | |
9437 | { ".text.", ".gnu.linkonce.t." }, | |
9438 | { ".rodata.", ".gnu.linkonce.r." }, | |
9439 | { ".sdata2.", ".gnu.linkonce.s2." }, | |
9440 | { ".data.", ".gnu.linkonce.d." }, | |
9441 | { ".sdata.", ".gnu.linkonce.s." }, | |
9442 | { ".bss.", ".gnu.linkonce.b." }, | |
9443 | { ".sbss.", ".gnu.linkonce.sb." } | |
9444 | }; | |
9445 | ||
9446 | needs_sdata = (TREE_CODE (decl) != FUNCTION_DECL | |
9447 | && size > 0 | |
9448 | && size <= g_switch_value | |
9449 | && rs6000_sdata != SDATA_NONE | |
9450 | && (rs6000_sdata != SDATA_DATA || TREE_PUBLIC (decl))); | |
9451 | ||
9452 | if (TREE_CODE (decl) == STRING_CST) | |
9453 | readonly = ! flag_writable_strings; | |
9454 | else if (TREE_CODE (decl) == VAR_DECL) | |
9455 | readonly = (! (flag_pic && reloc) | |
9456 | && TREE_READONLY (decl) | |
9457 | && ! TREE_SIDE_EFFECTS (decl) | |
9458 | && DECL_INITIAL (decl) | |
9459 | && DECL_INITIAL (decl) != error_mark_node | |
9460 | && TREE_CONSTANT (DECL_INITIAL (decl))); | |
9461 | else | |
9462 | readonly = 1; | |
9463 | if (needs_sdata && rs6000_sdata != SDATA_EABI) | |
9464 | readonly = 0; | |
9465 | ||
9466 | sec = ((TREE_CODE (decl) == FUNCTION_DECL ? 0 : 1) | |
9467 | + (readonly ? 0 : 2) | |
9468 | + (needs_sdata ? 1 : 0) | |
9469 | + (DECL_INITIAL (decl) == 0 | |
9470 | || DECL_INITIAL (decl) == error_mark_node) ? 4 : 0); | |
9471 | ||
e6978109 | 9472 | STRIP_NAME_ENCODING (name, IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl))); |
63019373 GK |
9473 | prefix = prefixes[sec][DECL_ONE_ONLY (decl)]; |
9474 | len = strlen (name) + strlen (prefix); | |
9475 | string = alloca (len + 1); | |
9476 | ||
9477 | sprintf (string, "%s%s", prefix, name); | |
9478 | ||
9479 | DECL_SECTION_NAME (decl) = build_string (len, string); | |
7509c759 | 9480 | } |
d9407988 MM |
9481 | |
9482 | \f | |
d9407988 MM |
9483 | /* If we are referencing a function that is static or is known to be |
9484 | in this file, make the SYMBOL_REF special. We can use this to indicate | |
9485 | that we can branch to this function without emitting a no-op after the | |
9ebbca7d | 9486 | call. For real AIX calling sequences, we also replace the |
d9407988 MM |
9487 | function name with the real name (1 or 2 leading .'s), rather than |
9488 | the function descriptor name. This saves a lot of overriding code | |
a260abc9 | 9489 | to read the prefixes. */ |
d9407988 MM |
9490 | |
9491 | void | |
9492 | rs6000_encode_section_info (decl) | |
9493 | tree decl; | |
9494 | { | |
9495 | if (TREE_CODE (decl) == FUNCTION_DECL) | |
9496 | { | |
9497 | rtx sym_ref = XEXP (DECL_RTL (decl), 0); | |
8f1b829e | 9498 | if ((TREE_ASM_WRITTEN (decl) || ! TREE_PUBLIC (decl)) |
c81fc13e | 9499 | && ! DECL_WEAK (decl)) |
d9407988 MM |
9500 | SYMBOL_REF_FLAG (sym_ref) = 1; |
9501 | ||
9ebbca7d | 9502 | if (DEFAULT_ABI == ABI_AIX) |
d9407988 | 9503 | { |
ff669a6c RH |
9504 | size_t len1 = (DEFAULT_ABI == ABI_AIX) ? 1 : 2; |
9505 | size_t len2 = strlen (XSTR (sym_ref, 0)); | |
520a57c8 | 9506 | char *str = alloca (len1 + len2 + 1); |
ff669a6c RH |
9507 | str[0] = '.'; |
9508 | str[1] = '.'; | |
9509 | memcpy (str + len1, XSTR (sym_ref, 0), len2 + 1); | |
9510 | ||
520a57c8 | 9511 | XSTR (sym_ref, 0) = ggc_alloc_string (str, len1 + len2); |
d9407988 MM |
9512 | } |
9513 | } | |
9514 | else if (rs6000_sdata != SDATA_NONE | |
f607bc57 | 9515 | && DEFAULT_ABI == ABI_V4 |
d9407988 MM |
9516 | && TREE_CODE (decl) == VAR_DECL) |
9517 | { | |
9518 | int size = int_size_in_bytes (TREE_TYPE (decl)); | |
9519 | tree section_name = DECL_SECTION_NAME (decl); | |
d330fd93 | 9520 | const char *name = (char *)0; |
d9407988 MM |
9521 | int len = 0; |
9522 | ||
9523 | if (section_name) | |
9524 | { | |
9525 | if (TREE_CODE (section_name) == STRING_CST) | |
9526 | { | |
9527 | name = TREE_STRING_POINTER (section_name); | |
9528 | len = TREE_STRING_LENGTH (section_name); | |
9529 | } | |
9530 | else | |
9531 | abort (); | |
9532 | } | |
9533 | ||
9534 | if ((size > 0 && size <= g_switch_value) | |
9535 | || (name | |
5f59ecb7 | 9536 | && ((len == sizeof (".sdata") - 1 |
3cb999d8 | 9537 | && strcmp (name, ".sdata") == 0) |
5f59ecb7 | 9538 | || (len == sizeof (".sdata2") - 1 |
3cb999d8 | 9539 | && strcmp (name, ".sdata2") == 0) |
5f59ecb7 | 9540 | || (len == sizeof (".sbss") - 1 |
3cb999d8 | 9541 | && strcmp (name, ".sbss") == 0) |
5f59ecb7 | 9542 | || (len == sizeof (".sbss2") - 1 |
3cb999d8 | 9543 | && strcmp (name, ".sbss2") == 0) |
5f59ecb7 | 9544 | || (len == sizeof (".PPC.EMB.sdata0") - 1 |
3cb999d8 | 9545 | && strcmp (name, ".PPC.EMB.sdata0") == 0) |
5f59ecb7 | 9546 | || (len == sizeof (".PPC.EMB.sbss0") - 1 |
3cb999d8 | 9547 | && strcmp (name, ".PPC.EMB.sbss0") == 0)))) |
d9407988 MM |
9548 | { |
9549 | rtx sym_ref = XEXP (DECL_RTL (decl), 0); | |
ff669a6c | 9550 | size_t len = strlen (XSTR (sym_ref, 0)); |
88c1e412 | 9551 | char *str = alloca (len + 2); |
ff669a6c | 9552 | |
ff669a6c RH |
9553 | str[0] = '@'; |
9554 | memcpy (str + 1, XSTR (sym_ref, 0), len + 1); | |
88c1e412 | 9555 | XSTR (sym_ref, 0) = ggc_alloc_string (str, len + 1); |
d9407988 MM |
9556 | } |
9557 | } | |
9558 | } | |
9559 | ||
b91da81f | 9560 | #endif /* USING_ELFOS_H */ |
000034eb | 9561 | |
a6c2a102 | 9562 | \f |
000034eb | 9563 | /* Return a REG that occurs in ADDR with coefficient 1. |
02441cd6 JL |
9564 | ADDR can be effectively incremented by incrementing REG. |
9565 | ||
9566 | r0 is special and we must not select it as an address | |
9567 | register by this routine since our caller will try to | |
9568 | increment the returned register via an "la" instruction. */ | |
000034eb DE |
9569 | |
9570 | struct rtx_def * | |
9571 | find_addr_reg (addr) | |
9572 | rtx addr; | |
9573 | { | |
9574 | while (GET_CODE (addr) == PLUS) | |
9575 | { | |
02441cd6 JL |
9576 | if (GET_CODE (XEXP (addr, 0)) == REG |
9577 | && REGNO (XEXP (addr, 0)) != 0) | |
000034eb | 9578 | addr = XEXP (addr, 0); |
02441cd6 JL |
9579 | else if (GET_CODE (XEXP (addr, 1)) == REG |
9580 | && REGNO (XEXP (addr, 1)) != 0) | |
000034eb DE |
9581 | addr = XEXP (addr, 1); |
9582 | else if (CONSTANT_P (XEXP (addr, 0))) | |
9583 | addr = XEXP (addr, 1); | |
9584 | else if (CONSTANT_P (XEXP (addr, 1))) | |
9585 | addr = XEXP (addr, 0); | |
9586 | else | |
9587 | abort (); | |
9588 | } | |
02441cd6 | 9589 | if (GET_CODE (addr) == REG && REGNO (addr) != 0) |
000034eb DE |
9590 | return addr; |
9591 | abort (); | |
9592 | } | |
9593 | ||
a6c2a102 DE |
9594 | void |
9595 | rs6000_fatal_bad_address (op) | |
9596 | rtx op; | |
9597 | { | |
9598 | fatal_insn ("bad address", op); | |
9599 | } | |
c8023011 MM |
9600 | |
9601 | /* Called to register all of our global variables with the garbage | |
9602 | collector. */ | |
9603 | ||
9604 | static void | |
9605 | rs6000_add_gc_roots () | |
9606 | { | |
9607 | ggc_add_rtx_root (&rs6000_compare_op0, 1); | |
9608 | ggc_add_rtx_root (&rs6000_compare_op1, 1); | |
9ebbca7d GK |
9609 | |
9610 | toc_hash_table = htab_create (1021, toc_hash_function, toc_hash_eq, NULL); | |
9611 | ggc_add_root (&toc_hash_table, 1, sizeof (toc_hash_table), | |
9612 | toc_hash_mark_table); | |
ee890fe2 SS |
9613 | |
9614 | #if TARGET_MACHO | |
9615 | machopic_add_gc_roots (); | |
9616 | #endif | |
9617 | } | |
9618 | ||
9619 | #if TARGET_MACHO | |
9620 | ||
9621 | #if 0 | |
9622 | /* Returns 1 if OP is either a symbol reference or a sum of a symbol | |
9623 | reference and a constant. */ | |
9624 | ||
9625 | int | |
9626 | symbolic_operand (op) | |
592696dd | 9627 | rtx op; |
ee890fe2 SS |
9628 | { |
9629 | switch (GET_CODE (op)) | |
9630 | { | |
9631 | case SYMBOL_REF: | |
9632 | case LABEL_REF: | |
9633 | return 1; | |
9634 | case CONST: | |
9635 | op = XEXP (op, 0); | |
9636 | return (GET_CODE (op) == SYMBOL_REF || | |
9637 | (GET_CODE (XEXP (op, 0)) == SYMBOL_REF | |
9638 | || GET_CODE (XEXP (op, 0)) == LABEL_REF) | |
9639 | && GET_CODE (XEXP (op, 1)) == CONST_INT); | |
9640 | default: | |
9641 | return 0; | |
9642 | } | |
c8023011 | 9643 | } |
ee890fe2 SS |
9644 | #endif |
9645 | ||
9646 | #ifdef RS6000_LONG_BRANCH | |
9647 | ||
9648 | static tree stub_list = 0; | |
9649 | ||
9650 | /* ADD_COMPILER_STUB adds the compiler generated stub for handling | |
9651 | procedure calls to the linked list. */ | |
9652 | ||
9653 | void | |
9654 | add_compiler_stub (label_name, function_name, line_number) | |
9655 | tree label_name; | |
9656 | tree function_name; | |
9657 | int line_number; | |
9658 | { | |
9659 | tree stub = build_tree_list (function_name, label_name); | |
9660 | TREE_TYPE (stub) = build_int_2 (line_number, 0); | |
9661 | TREE_CHAIN (stub) = stub_list; | |
9662 | stub_list = stub; | |
9663 | } | |
9664 | ||
9665 | #define STUB_LABEL_NAME(STUB) TREE_VALUE (STUB) | |
9666 | #define STUB_FUNCTION_NAME(STUB) TREE_PURPOSE (STUB) | |
9667 | #define STUB_LINE_NUMBER(STUB) TREE_INT_CST_LOW (TREE_TYPE (STUB)) | |
9668 | ||
a4f6c312 SS |
9669 | /* OUTPUT_COMPILER_STUB outputs the compiler generated stub for |
9670 | handling procedure calls from the linked list and initializes the | |
9671 | linked list. */ | |
ee890fe2 | 9672 | |
a4f6c312 SS |
9673 | void |
9674 | output_compiler_stub () | |
ee890fe2 SS |
9675 | { |
9676 | char tmp_buf[256]; | |
9677 | char label_buf[256]; | |
9678 | char *label; | |
9679 | tree tmp_stub, stub; | |
9680 | ||
9681 | if (!flag_pic) | |
9682 | for (stub = stub_list; stub; stub = TREE_CHAIN (stub)) | |
9683 | { | |
9684 | fprintf (asm_out_file, | |
9685 | "%s:\n", IDENTIFIER_POINTER(STUB_LABEL_NAME(stub))); | |
9686 | ||
9687 | #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO) | |
9688 | if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG) | |
9689 | fprintf (asm_out_file, "\t.stabd 68,0,%d\n", STUB_LINE_NUMBER(stub)); | |
9690 | #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */ | |
9691 | ||
9692 | if (IDENTIFIER_POINTER (STUB_FUNCTION_NAME (stub))[0] == '*') | |
9693 | strcpy (label_buf, | |
9694 | IDENTIFIER_POINTER (STUB_FUNCTION_NAME (stub))+1); | |
9695 | else | |
9696 | { | |
9697 | label_buf[0] = '_'; | |
9698 | strcpy (label_buf+1, | |
9699 | IDENTIFIER_POINTER (STUB_FUNCTION_NAME (stub))); | |
9700 | } | |
9701 | ||
9702 | strcpy (tmp_buf, "lis r12,hi16("); | |
9703 | strcat (tmp_buf, label_buf); | |
9704 | strcat (tmp_buf, ")\n\tori r12,r12,lo16("); | |
9705 | strcat (tmp_buf, label_buf); | |
9706 | strcat (tmp_buf, ")\n\tmtctr r12\n\tbctr"); | |
9707 | output_asm_insn (tmp_buf, 0); | |
9708 | ||
9709 | #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO) | |
9710 | if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG) | |
9711 | fprintf(asm_out_file, "\t.stabd 68,0,%d\n", STUB_LINE_NUMBER (stub)); | |
9712 | #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */ | |
9713 | } | |
9714 | ||
9715 | stub_list = 0; | |
9716 | } | |
9717 | ||
9718 | /* NO_PREVIOUS_DEF checks in the link list whether the function name is | |
9719 | already there or not. */ | |
9720 | ||
a4f6c312 SS |
9721 | int |
9722 | no_previous_def (function_name) | |
ee890fe2 SS |
9723 | tree function_name; |
9724 | { | |
9725 | tree stub; | |
9726 | for (stub = stub_list; stub; stub = TREE_CHAIN (stub)) | |
9727 | if (function_name == STUB_FUNCTION_NAME (stub)) | |
9728 | return 0; | |
9729 | return 1; | |
9730 | } | |
9731 | ||
9732 | /* GET_PREV_LABEL gets the label name from the previous definition of | |
9733 | the function. */ | |
9734 | ||
a4f6c312 SS |
9735 | tree |
9736 | get_prev_label (function_name) | |
ee890fe2 SS |
9737 | tree function_name; |
9738 | { | |
9739 | tree stub; | |
9740 | for (stub = stub_list; stub; stub = TREE_CHAIN (stub)) | |
9741 | if (function_name == STUB_FUNCTION_NAME (stub)) | |
9742 | return STUB_LABEL_NAME (stub); | |
9743 | return 0; | |
9744 | } | |
9745 | ||
9746 | /* INSN is either a function call or a millicode call. It may have an | |
9747 | unconditional jump in its delay slot. | |
9748 | ||
9749 | CALL_DEST is the routine we are calling. */ | |
9750 | ||
9751 | char * | |
9752 | output_call (insn, call_dest, operand_number) | |
9753 | rtx insn; | |
9754 | rtx call_dest; | |
9755 | int operand_number; | |
9756 | { | |
9757 | static char buf[256]; | |
9758 | if (GET_CODE (call_dest) == SYMBOL_REF && TARGET_LONG_BRANCH && !flag_pic) | |
9759 | { | |
9760 | tree labelname; | |
9761 | tree funname = get_identifier (XSTR (call_dest, 0)); | |
9762 | ||
9763 | if (no_previous_def (funname)) | |
9764 | { | |
9765 | int line_number; | |
9766 | rtx label_rtx = gen_label_rtx (); | |
9767 | char *label_buf, temp_buf[256]; | |
9768 | ASM_GENERATE_INTERNAL_LABEL (temp_buf, "L", | |
9769 | CODE_LABEL_NUMBER (label_rtx)); | |
9770 | label_buf = temp_buf[0] == '*' ? temp_buf + 1 : temp_buf; | |
9771 | labelname = get_identifier (label_buf); | |
9772 | for (; insn && GET_CODE (insn) != NOTE; insn = PREV_INSN (insn)); | |
9773 | if (insn) | |
9774 | line_number = NOTE_LINE_NUMBER (insn); | |
9775 | add_compiler_stub (labelname, funname, line_number); | |
9776 | } | |
9777 | else | |
9778 | labelname = get_prev_label (funname); | |
9779 | ||
9780 | sprintf (buf, "jbsr %%z%d,%.246s", | |
9781 | operand_number, IDENTIFIER_POINTER (labelname)); | |
9782 | return buf; | |
9783 | } | |
9784 | else | |
9785 | { | |
9786 | sprintf (buf, "bl %%z%d", operand_number); | |
9787 | return buf; | |
9788 | } | |
9789 | } | |
9790 | ||
9791 | #endif /* RS6000_LONG_BRANCH */ | |
9792 | ||
9793 | #define GEN_LOCAL_LABEL_FOR_SYMBOL(BUF,SYMBOL,LENGTH,N) \ | |
9794 | do { \ | |
83182544 | 9795 | const char *const symbol_ = (SYMBOL); \ |
ee890fe2 SS |
9796 | char *buffer_ = (BUF); \ |
9797 | if (symbol_[0] == '"') \ | |
9798 | { \ | |
9799 | sprintf(buffer_, "\"L%d$%s", (N), symbol_+1); \ | |
9800 | } \ | |
9801 | else if (name_needs_quotes(symbol_)) \ | |
9802 | { \ | |
9803 | sprintf(buffer_, "\"L%d$%s\"", (N), symbol_); \ | |
9804 | } \ | |
9805 | else \ | |
9806 | { \ | |
9807 | sprintf(buffer_, "L%d$%s", (N), symbol_); \ | |
9808 | } \ | |
9809 | } while (0) | |
9810 | ||
9811 | ||
9812 | /* Generate PIC and indirect symbol stubs. */ | |
9813 | ||
9814 | void | |
9815 | machopic_output_stub (file, symb, stub) | |
9816 | FILE *file; | |
9817 | const char *symb, *stub; | |
9818 | { | |
9819 | unsigned int length; | |
a4f6c312 SS |
9820 | char *symbol_name, *lazy_ptr_name; |
9821 | char *local_label_0; | |
ee890fe2 SS |
9822 | static int label = 0; |
9823 | ||
df56a27f SS |
9824 | /* Lose our funky encoding stuff so it doesn't contaminate the stub. */ |
9825 | STRIP_NAME_ENCODING (symb, symb); | |
9826 | ||
ee890fe2 SS |
9827 | label += 1; |
9828 | ||
ee890fe2 SS |
9829 | length = strlen (symb); |
9830 | symbol_name = alloca (length + 32); | |
9831 | GEN_SYMBOL_NAME_FOR_SYMBOL (symbol_name, symb, length); | |
9832 | ||
9833 | lazy_ptr_name = alloca (length + 32); | |
9834 | GEN_LAZY_PTR_NAME_FOR_SYMBOL (lazy_ptr_name, symb, length); | |
9835 | ||
9836 | local_label_0 = alloca (length + 32); | |
9837 | GEN_LOCAL_LABEL_FOR_SYMBOL (local_label_0, symb, length, 0); | |
9838 | ||
ee890fe2 SS |
9839 | if (flag_pic == 2) |
9840 | machopic_picsymbol_stub_section (); | |
9841 | else | |
9842 | machopic_symbol_stub_section (); | |
9843 | ||
9844 | fprintf (file, "%s:\n", stub); | |
9845 | fprintf (file, "\t.indirect_symbol %s\n", symbol_name); | |
9846 | ||
9847 | if (flag_pic == 2) | |
9848 | { | |
9849 | fprintf (file, "\tmflr r0\n"); | |
9850 | fprintf (file, "\tbcl 20,31,%s\n", local_label_0); | |
9851 | fprintf (file, "%s:\n\tmflr r11\n", local_label_0); | |
9852 | fprintf (file, "\taddis r11,r11,ha16(%s-%s)\n", | |
9853 | lazy_ptr_name, local_label_0); | |
9854 | fprintf (file, "\tmtlr r0\n"); | |
9855 | fprintf (file, "\tlwz r12,lo16(%s-%s)(r11)\n", | |
9856 | lazy_ptr_name, local_label_0); | |
9857 | fprintf (file, "\tmtctr r12\n"); | |
9858 | fprintf (file, "\taddi r11,r11,lo16(%s-%s)\n", | |
9859 | lazy_ptr_name, local_label_0); | |
9860 | fprintf (file, "\tbctr\n"); | |
9861 | } | |
9862 | else | |
9863 | fprintf (file, "non-pure not supported\n"); | |
9864 | ||
9865 | machopic_lazy_symbol_ptr_section (); | |
9866 | fprintf (file, "%s:\n", lazy_ptr_name); | |
9867 | fprintf (file, "\t.indirect_symbol %s\n", symbol_name); | |
9868 | fprintf (file, "\t.long dyld_stub_binding_helper\n"); | |
9869 | } | |
9870 | ||
9871 | /* Legitimize PIC addresses. If the address is already | |
9872 | position-independent, we return ORIG. Newly generated | |
9873 | position-independent addresses go into a reg. This is REG if non | |
9874 | zero, otherwise we allocate register(s) as necessary. */ | |
9875 | ||
9876 | #define SMALL_INT(X) ((unsigned) (INTVAL(X) + 0x4000) < 0x8000) | |
9877 | ||
9878 | rtx | |
9879 | rs6000_machopic_legitimize_pic_address (orig, mode, reg) | |
9880 | rtx orig; | |
9881 | enum machine_mode mode; | |
9882 | rtx reg; | |
9883 | { | |
9884 | rtx base, offset; | |
9885 | ||
9886 | if (reg == NULL && ! reload_in_progress && ! reload_completed) | |
9887 | reg = gen_reg_rtx (Pmode); | |
9888 | ||
9889 | if (GET_CODE (orig) == CONST) | |
9890 | { | |
9891 | if (GET_CODE (XEXP (orig, 0)) == PLUS | |
9892 | && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx) | |
9893 | return orig; | |
9894 | ||
9895 | if (GET_CODE (XEXP (orig, 0)) == PLUS) | |
9896 | { | |
a4f6c312 SS |
9897 | base = |
9898 | rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 0), | |
9899 | Pmode, reg); | |
9900 | offset = | |
9901 | rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 1), | |
9902 | Pmode, reg); | |
ee890fe2 SS |
9903 | } |
9904 | else | |
9905 | abort (); | |
9906 | ||
9907 | if (GET_CODE (offset) == CONST_INT) | |
9908 | { | |
9909 | if (SMALL_INT (offset)) | |
ed8908e7 | 9910 | return plus_constant (base, INTVAL (offset)); |
ee890fe2 SS |
9911 | else if (! reload_in_progress && ! reload_completed) |
9912 | offset = force_reg (Pmode, offset); | |
9913 | else | |
9914 | abort (); | |
9915 | } | |
9916 | return gen_rtx (PLUS, Pmode, base, offset); | |
9917 | } | |
9918 | ||
9919 | /* Fall back on generic machopic code. */ | |
9920 | return machopic_legitimize_pic_address (orig, mode, reg); | |
9921 | } | |
9922 | ||
9923 | /* This is just a placeholder to make linking work without having to | |
9924 | add this to the generic Darwin EXTRA_SECTIONS. If -mcall-aix is | |
9925 | ever needed for Darwin (not too likely!) this would have to get a | |
9926 | real definition. */ | |
9927 | ||
9928 | void | |
9929 | toc_section () | |
9930 | { | |
9931 | } | |
9932 | ||
9933 | #endif /* TARGET_MACHO */ | |
7c262518 RH |
9934 | |
9935 | #if TARGET_ELF | |
9936 | static unsigned int | |
9937 | rs6000_elf_section_type_flags (decl, name, reloc) | |
9938 | tree decl; | |
9939 | const char *name; | |
9940 | int reloc; | |
9941 | { | |
9942 | unsigned int flags = default_section_type_flags (decl, name, reloc); | |
9943 | ||
270fc29b RH |
9944 | if (TARGET_RELOCATABLE) |
9945 | flags |= SECTION_WRITE; | |
7c262518 | 9946 | |
d0101753 | 9947 | return flags; |
7c262518 | 9948 | } |
d9f6800d RH |
9949 | |
9950 | /* Record an element in the table of global constructors. SYMBOL is | |
9951 | a SYMBOL_REF of the function to be called; PRIORITY is a number | |
9952 | between 0 and MAX_INIT_PRIORITY. | |
9953 | ||
9954 | This differs from default_named_section_asm_out_constructor in | |
9955 | that we have special handling for -mrelocatable. */ | |
9956 | ||
9957 | static void | |
9958 | rs6000_elf_asm_out_constructor (symbol, priority) | |
9959 | rtx symbol; | |
9960 | int priority; | |
9961 | { | |
9962 | const char *section = ".ctors"; | |
9963 | char buf[16]; | |
9964 | ||
9965 | if (priority != DEFAULT_INIT_PRIORITY) | |
9966 | { | |
9967 | sprintf (buf, ".ctors.%.5u", | |
9968 | /* Invert the numbering so the linker puts us in the proper | |
9969 | order; constructors are run from right to left, and the | |
9970 | linker sorts in increasing order. */ | |
9971 | MAX_INIT_PRIORITY - priority); | |
9972 | section = buf; | |
9973 | } | |
9974 | ||
715bdd29 RH |
9975 | named_section_flags (section, SECTION_WRITE); |
9976 | assemble_align (POINTER_SIZE); | |
d9f6800d RH |
9977 | |
9978 | if (TARGET_RELOCATABLE) | |
9979 | { | |
9980 | fputs ("\t.long (", asm_out_file); | |
9981 | output_addr_const (asm_out_file, symbol); | |
9982 | fputs (")@fixup\n", asm_out_file); | |
9983 | } | |
9984 | else | |
c8af3574 | 9985 | assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1); |
d9f6800d RH |
9986 | } |
9987 | ||
9988 | static void | |
9989 | rs6000_elf_asm_out_destructor (symbol, priority) | |
9990 | rtx symbol; | |
9991 | int priority; | |
9992 | { | |
9993 | const char *section = ".dtors"; | |
9994 | char buf[16]; | |
9995 | ||
9996 | if (priority != DEFAULT_INIT_PRIORITY) | |
9997 | { | |
9998 | sprintf (buf, ".dtors.%.5u", | |
9999 | /* Invert the numbering so the linker puts us in the proper | |
10000 | order; constructors are run from right to left, and the | |
10001 | linker sorts in increasing order. */ | |
10002 | MAX_INIT_PRIORITY - priority); | |
10003 | section = buf; | |
10004 | } | |
10005 | ||
715bdd29 RH |
10006 | named_section_flags (section, SECTION_WRITE); |
10007 | assemble_align (POINTER_SIZE); | |
d9f6800d RH |
10008 | |
10009 | if (TARGET_RELOCATABLE) | |
10010 | { | |
10011 | fputs ("\t.long (", asm_out_file); | |
10012 | output_addr_const (asm_out_file, symbol); | |
10013 | fputs (")@fixup\n", asm_out_file); | |
10014 | } | |
10015 | else | |
c8af3574 | 10016 | assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1); |
d9f6800d | 10017 | } |
7c262518 RH |
10018 | #endif |
10019 | ||
10020 | #ifdef OBJECT_FORMAT_COFF | |
10021 | static void | |
715bdd29 | 10022 | xcoff_asm_named_section (name, flags) |
7c262518 RH |
10023 | const char *name; |
10024 | unsigned int flags ATTRIBUTE_UNUSED; | |
7c262518 RH |
10025 | { |
10026 | fprintf (asm_out_file, "\t.csect %s\n", name); | |
10027 | } | |
10028 | #endif |