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Commit | Line | Data |
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9878760c | 1 | /* Subroutines used for code generation on IBM RS/6000. |
9ebbca7d | 2 | Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, |
d3c300d2 | 3 | 2000, 2001, 2002, 2003 Free Software Foundation, Inc. |
fab3bcc3 | 4 | Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu) |
9878760c | 5 | |
5de601cf | 6 | This file is part of GCC. |
9878760c | 7 | |
5de601cf NC |
8 | GCC is free software; you can redistribute it and/or modify it |
9 | under the terms of the GNU General Public License as published | |
10 | by the Free Software Foundation; either version 2, or (at your | |
11 | option) any later version. | |
9878760c | 12 | |
5de601cf NC |
13 | GCC is distributed in the hope that it will be useful, but WITHOUT |
14 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
15 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
16 | License for more details. | |
9878760c | 17 | |
5de601cf NC |
18 | You should have received a copy of the GNU General Public License |
19 | along with GCC; see the file COPYING. If not, write to the | |
20 | Free Software Foundation, 59 Temple Place - Suite 330, Boston, | |
21 | MA 02111-1307, USA. */ | |
9878760c | 22 | |
956d6950 | 23 | #include "config.h" |
c4d38ccb | 24 | #include "system.h" |
4977bab6 ZW |
25 | #include "coretypes.h" |
26 | #include "tm.h" | |
9878760c RK |
27 | #include "rtl.h" |
28 | #include "regs.h" | |
29 | #include "hard-reg-set.h" | |
30 | #include "real.h" | |
31 | #include "insn-config.h" | |
32 | #include "conditions.h" | |
9878760c RK |
33 | #include "insn-attr.h" |
34 | #include "flags.h" | |
35 | #include "recog.h" | |
9878760c | 36 | #include "obstack.h" |
9b30bae2 | 37 | #include "tree.h" |
dfafc897 | 38 | #include "expr.h" |
2fc1c679 | 39 | #include "optabs.h" |
2a430ec1 | 40 | #include "except.h" |
a7df97e6 | 41 | #include "function.h" |
296b8152 | 42 | #include "output.h" |
d5fa86ba | 43 | #include "basic-block.h" |
d0101753 | 44 | #include "integrate.h" |
296b8152 | 45 | #include "toplev.h" |
c8023011 | 46 | #include "ggc.h" |
9ebbca7d GK |
47 | #include "hashtab.h" |
48 | #include "tm_p.h" | |
672a6f42 NB |
49 | #include "target.h" |
50 | #include "target-def.h" | |
3ac88239 | 51 | #include "langhooks.h" |
24ea750e | 52 | #include "reload.h" |
117dca74 | 53 | #include "cfglayout.h" |
1bc7c5b6 ZW |
54 | #if TARGET_XCOFF |
55 | #include "xcoffout.h" /* get declarations of xcoff_*_section_name */ | |
56 | #endif | |
9b30bae2 | 57 | |
7509c759 MM |
58 | #ifndef TARGET_NO_PROTOTYPE |
59 | #define TARGET_NO_PROTOTYPE 0 | |
60 | #endif | |
61 | ||
d744e06e AH |
62 | #define EASY_VECTOR_15(n, x, y) ((n) >= -16 && (n) <= 15 \ |
63 | && easy_vector_same (x, y)) | |
64 | ||
65 | #define EASY_VECTOR_15_ADD_SELF(n, x, y) ((n) >= 0x10 && (n) <= 0x1e \ | |
66 | && !((n) & 1) \ | |
67 | && easy_vector_same (x, y)) | |
68 | ||
9878760c RK |
69 | #define min(A,B) ((A) < (B) ? (A) : (B)) |
70 | #define max(A,B) ((A) > (B) ? (A) : (B)) | |
71 | ||
5248c961 RK |
72 | /* Target cpu type */ |
73 | ||
74 | enum processor_type rs6000_cpu; | |
8e3f41e7 MM |
75 | struct rs6000_cpu_select rs6000_select[3] = |
76 | { | |
815cdc52 MM |
77 | /* switch name, tune arch */ |
78 | { (const char *)0, "--with-cpu=", 1, 1 }, | |
79 | { (const char *)0, "-mcpu=", 1, 1 }, | |
80 | { (const char *)0, "-mtune=", 1, 0 }, | |
8e3f41e7 | 81 | }; |
5248c961 | 82 | |
6fa3f289 ZW |
83 | /* Size of long double */ |
84 | const char *rs6000_long_double_size_string; | |
85 | int rs6000_long_double_type_size; | |
86 | ||
87 | /* Whether -mabi=altivec has appeared */ | |
88 | int rs6000_altivec_abi; | |
89 | ||
08b57fb3 AH |
90 | /* Whether VRSAVE instructions should be generated. */ |
91 | int rs6000_altivec_vrsave; | |
92 | ||
93 | /* String from -mvrsave= option. */ | |
94 | const char *rs6000_altivec_vrsave_string; | |
95 | ||
a3170dc6 AH |
96 | /* Nonzero if we want SPE ABI extensions. */ |
97 | int rs6000_spe_abi; | |
98 | ||
99 | /* Whether isel instructions should be generated. */ | |
100 | int rs6000_isel; | |
101 | ||
993f19a8 AH |
102 | /* Whether SPE simd instructions should be generated. */ |
103 | int rs6000_spe; | |
104 | ||
5da702b1 AH |
105 | /* Nonzero if floating point operations are done in the GPRs. */ |
106 | int rs6000_float_gprs = 0; | |
107 | ||
108 | /* String from -mfloat-gprs=. */ | |
109 | const char *rs6000_float_gprs_string; | |
a3170dc6 AH |
110 | |
111 | /* String from -misel=. */ | |
112 | const char *rs6000_isel_string; | |
113 | ||
993f19a8 AH |
114 | /* String from -mspe=. */ |
115 | const char *rs6000_spe_string; | |
116 | ||
a0ab749a | 117 | /* Set to nonzero once AIX common-mode calls have been defined. */ |
bbfb86aa | 118 | static GTY(()) int common_mode_defined; |
c81bebd7 | 119 | |
9878760c RK |
120 | /* Save information from a "cmpxx" operation until the branch or scc is |
121 | emitted. */ | |
9878760c RK |
122 | rtx rs6000_compare_op0, rs6000_compare_op1; |
123 | int rs6000_compare_fp_p; | |
874a0744 | 124 | |
874a0744 MM |
125 | /* Label number of label created for -mrelocatable, to call to so we can |
126 | get the address of the GOT section */ | |
127 | int rs6000_pic_labelno; | |
c81bebd7 | 128 | |
b91da81f | 129 | #ifdef USING_ELFOS_H |
c81bebd7 | 130 | /* Which abi to adhere to */ |
9739c90c | 131 | const char *rs6000_abi_name; |
d9407988 MM |
132 | |
133 | /* Semantics of the small data area */ | |
134 | enum rs6000_sdata_type rs6000_sdata = SDATA_DATA; | |
135 | ||
136 | /* Which small data model to use */ | |
815cdc52 | 137 | const char *rs6000_sdata_name = (char *)0; |
9ebbca7d GK |
138 | |
139 | /* Counter for labels which are to be placed in .fixup. */ | |
140 | int fixuplabelno = 0; | |
874a0744 | 141 | #endif |
4697a36c | 142 | |
c4501e62 JJ |
143 | /* Bit size of immediate TLS offsets and string from which it is decoded. */ |
144 | int rs6000_tls_size = 32; | |
145 | const char *rs6000_tls_size_string; | |
146 | ||
b6c9286a MM |
147 | /* ABI enumeration available for subtarget to use. */ |
148 | enum rs6000_abi rs6000_current_abi; | |
149 | ||
0ac081f6 AH |
150 | /* ABI string from -mabi= option. */ |
151 | const char *rs6000_abi_string; | |
152 | ||
38c1f2d7 | 153 | /* Debug flags */ |
815cdc52 | 154 | const char *rs6000_debug_name; |
38c1f2d7 MM |
155 | int rs6000_debug_stack; /* debug stack applications */ |
156 | int rs6000_debug_arg; /* debug argument handling */ | |
157 | ||
6035d635 | 158 | /* Opaque types. */ |
2abe3e28 | 159 | static GTY(()) tree opaque_V2SI_type_node; |
2abe3e28 | 160 | static GTY(()) tree opaque_V2SF_type_node; |
6035d635 | 161 | static GTY(()) tree opaque_p_V2SI_type_node; |
2abe3e28 | 162 | |
57ac7be9 AM |
163 | const char *rs6000_traceback_name; |
164 | static enum { | |
165 | traceback_default = 0, | |
166 | traceback_none, | |
167 | traceback_part, | |
168 | traceback_full | |
169 | } rs6000_traceback; | |
170 | ||
38c1f2d7 MM |
171 | /* Flag to say the TOC is initialized */ |
172 | int toc_initialized; | |
9ebbca7d | 173 | char toc_label_name[10]; |
38c1f2d7 | 174 | |
9ebbca7d GK |
175 | /* Alias set for saves and restores from the rs6000 stack. */ |
176 | static int rs6000_sr_alias_set; | |
c8023011 | 177 | |
a5c76ee6 ZW |
178 | /* Call distance, overridden by -mlongcall and #pragma longcall(1). |
179 | The only place that looks at this is rs6000_set_default_type_attributes; | |
180 | everywhere else should rely on the presence or absence of a longcall | |
181 | attribute on the function declaration. */ | |
182 | int rs6000_default_long_calls; | |
183 | const char *rs6000_longcall_switch; | |
184 | ||
025d9908 KH |
185 | /* Control alignment for fields within structures. */ |
186 | /* String from -malign-XXXXX. */ | |
187 | const char *rs6000_alignment_string; | |
188 | int rs6000_alignment_flags; | |
189 | ||
a3170dc6 AH |
190 | struct builtin_description |
191 | { | |
192 | /* mask is not const because we're going to alter it below. This | |
193 | nonsense will go away when we rewrite the -march infrastructure | |
194 | to give us more target flag bits. */ | |
195 | unsigned int mask; | |
196 | const enum insn_code icode; | |
197 | const char *const name; | |
198 | const enum rs6000_builtins code; | |
199 | }; | |
200 | ||
4977bab6 | 201 | static bool rs6000_function_ok_for_sibcall PARAMS ((tree, tree)); |
9ebbca7d | 202 | static int num_insns_constant_wide PARAMS ((HOST_WIDE_INT)); |
39a10a29 GK |
203 | static void validate_condition_mode |
204 | PARAMS ((enum rtx_code, enum machine_mode)); | |
205 | static rtx rs6000_generate_compare PARAMS ((enum rtx_code)); | |
e50f5f3d | 206 | static void rs6000_maybe_dead PARAMS ((rtx)); |
9ebbca7d GK |
207 | static void rs6000_emit_stack_tie PARAMS ((void)); |
208 | static void rs6000_frame_related PARAMS ((rtx, rtx, HOST_WIDE_INT, rtx, rtx)); | |
c19de7aa AH |
209 | static rtx spe_synthesize_frame_save PARAMS ((rtx)); |
210 | static bool spe_func_has_64bit_regs_p PARAMS ((void)); | |
89e7058f AH |
211 | static void emit_frame_save PARAMS ((rtx, rtx, enum machine_mode, |
212 | unsigned int, int, int)); | |
a3170dc6 | 213 | static rtx gen_frame_mem_offset PARAMS ((enum machine_mode, rtx, int)); |
9ebbca7d GK |
214 | static void rs6000_emit_allocate_stack PARAMS ((HOST_WIDE_INT, int)); |
215 | static unsigned rs6000_hash_constant PARAMS ((rtx)); | |
216 | static unsigned toc_hash_function PARAMS ((const void *)); | |
217 | static int toc_hash_eq PARAMS ((const void *, const void *)); | |
9ebbca7d | 218 | static int constant_pool_expr_1 PARAMS ((rtx, int *, int *)); |
4d588c14 RH |
219 | static bool constant_pool_expr_p PARAMS ((rtx)); |
220 | static bool toc_relative_expr_p PARAMS ((rtx)); | |
221 | static bool legitimate_small_data_p PARAMS ((enum machine_mode, rtx)); | |
222 | static bool legitimate_offset_address_p PARAMS ((enum machine_mode, rtx, int)); | |
223 | static bool legitimate_indexed_address_p PARAMS ((rtx, int)); | |
224 | static bool legitimate_indirect_address_p PARAMS ((rtx, int)); | |
225 | static bool legitimate_lo_sum_address_p PARAMS ((enum machine_mode, rtx, int)); | |
e2500fed | 226 | static struct machine_function * rs6000_init_machine_status PARAMS ((void)); |
301d03af | 227 | static bool rs6000_assemble_integer PARAMS ((rtx, unsigned int, int)); |
5add3202 | 228 | #ifdef HAVE_GAS_HIDDEN |
25fdb4dc | 229 | static void rs6000_assemble_visibility PARAMS ((tree, int)); |
5add3202 | 230 | #endif |
71f123ca | 231 | static int rs6000_ra_ever_killed PARAMS ((void)); |
91d231cb | 232 | static tree rs6000_handle_longcall_attribute PARAMS ((tree *, tree, tree, int, bool *)); |
b86fe7b4 | 233 | extern const struct attribute_spec rs6000_attribute_table[]; |
a5c76ee6 | 234 | static void rs6000_set_default_type_attributes PARAMS ((tree)); |
08c148a8 NB |
235 | static void rs6000_output_function_prologue PARAMS ((FILE *, HOST_WIDE_INT)); |
236 | static void rs6000_output_function_epilogue PARAMS ((FILE *, HOST_WIDE_INT)); | |
3961e8fe RH |
237 | static void rs6000_output_mi_thunk PARAMS ((FILE *, tree, HOST_WIDE_INT, |
238 | HOST_WIDE_INT, tree)); | |
2bfcf297 DB |
239 | static rtx rs6000_emit_set_long_const PARAMS ((rtx, |
240 | HOST_WIDE_INT, HOST_WIDE_INT)); | |
1bc7c5b6 | 241 | static void rs6000_file_start PARAMS ((void)); |
7c262518 RH |
242 | #if TARGET_ELF |
243 | static unsigned int rs6000_elf_section_type_flags PARAMS ((tree, const char *, | |
244 | int)); | |
d9f6800d RH |
245 | static void rs6000_elf_asm_out_constructor PARAMS ((rtx, int)); |
246 | static void rs6000_elf_asm_out_destructor PARAMS ((rtx, int)); | |
ae46c4e0 | 247 | static void rs6000_elf_select_section PARAMS ((tree, int, |
5b71a4e7 | 248 | unsigned HOST_WIDE_INT)); |
ae46c4e0 | 249 | static void rs6000_elf_unique_section PARAMS ((tree, int)); |
b64a1b53 RH |
250 | static void rs6000_elf_select_rtx_section PARAMS ((enum machine_mode, rtx, |
251 | unsigned HOST_WIDE_INT)); | |
c6a2438a | 252 | static void rs6000_elf_encode_section_info PARAMS ((tree, rtx, int)) |
0e5dbd9b | 253 | ATTRIBUTE_UNUSED; |
0e5dbd9b | 254 | static bool rs6000_elf_in_small_data_p PARAMS ((tree)); |
7c262518 | 255 | #endif |
cbaaba19 | 256 | #if TARGET_XCOFF |
b275d088 DE |
257 | static void rs6000_xcoff_asm_globalize_label PARAMS ((FILE *, const char *)); |
258 | static void rs6000_xcoff_asm_named_section PARAMS ((const char *, unsigned int)); | |
ae46c4e0 RH |
259 | static void rs6000_xcoff_select_section PARAMS ((tree, int, |
260 | unsigned HOST_WIDE_INT)); | |
261 | static void rs6000_xcoff_unique_section PARAMS ((tree, int)); | |
b64a1b53 RH |
262 | static void rs6000_xcoff_select_rtx_section PARAMS ((enum machine_mode, rtx, |
263 | unsigned HOST_WIDE_INT)); | |
772c5265 | 264 | static const char * rs6000_xcoff_strip_name_encoding PARAMS ((const char *)); |
5add3202 | 265 | static unsigned int rs6000_xcoff_section_type_flags PARAMS ((tree, const char *, int)); |
1bc7c5b6 | 266 | static void rs6000_xcoff_file_start PARAMS ((void)); |
a5fe455b | 267 | static void rs6000_xcoff_file_end PARAMS ((void)); |
f1384257 AM |
268 | #endif |
269 | #if TARGET_MACHO | |
2bcc50d0 | 270 | static bool rs6000_binds_local_p PARAMS ((tree)); |
f1384257 | 271 | #endif |
b54cf83a | 272 | static int rs6000_use_dfa_pipeline_interface PARAMS ((void)); |
b54cf83a | 273 | static int rs6000_variable_issue PARAMS ((FILE *, int, rtx, int)); |
3c50106f | 274 | static bool rs6000_rtx_costs PARAMS ((rtx, int, int, int *)); |
c237e94a ZW |
275 | static int rs6000_adjust_cost PARAMS ((rtx, rtx, rtx, int)); |
276 | static int rs6000_adjust_priority PARAMS ((rtx, int)); | |
277 | static int rs6000_issue_rate PARAMS ((void)); | |
be12c2b0 | 278 | static int rs6000_use_sched_lookahead PARAMS ((void)); |
c237e94a | 279 | |
6fa3f289 | 280 | static void rs6000_init_builtins PARAMS ((void)); |
92898235 AH |
281 | static rtx rs6000_expand_unop_builtin PARAMS ((enum insn_code, tree, rtx)); |
282 | static rtx rs6000_expand_binop_builtin PARAMS ((enum insn_code, tree, rtx)); | |
283 | static rtx rs6000_expand_ternop_builtin PARAMS ((enum insn_code, tree, rtx)); | |
0ac081f6 | 284 | static rtx rs6000_expand_builtin PARAMS ((tree, rtx, rtx, enum machine_mode, int)); |
92898235 | 285 | static void altivec_init_builtins PARAMS ((void)); |
a3170dc6 AH |
286 | static void rs6000_common_init_builtins PARAMS ((void)); |
287 | ||
288 | static void enable_mask_for_builtins PARAMS ((struct builtin_description *, | |
289 | int, enum rs6000_builtins, | |
290 | enum rs6000_builtins)); | |
291 | static void spe_init_builtins PARAMS ((void)); | |
292 | static rtx spe_expand_builtin PARAMS ((tree, rtx, bool *)); | |
293 | static rtx spe_expand_predicate_builtin PARAMS ((enum insn_code, tree, rtx)); | |
294 | static rtx spe_expand_evsel_builtin PARAMS ((enum insn_code, tree, rtx)); | |
295 | static int rs6000_emit_int_cmove PARAMS ((rtx, rtx, rtx, rtx)); | |
296 | ||
92898235 | 297 | static rtx altivec_expand_builtin PARAMS ((tree, rtx, bool *)); |
3a9b8c7e AH |
298 | static rtx altivec_expand_ld_builtin PARAMS ((tree, rtx, bool *)); |
299 | static rtx altivec_expand_st_builtin PARAMS ((tree, rtx, bool *)); | |
300 | static rtx altivec_expand_dst_builtin PARAMS ((tree, rtx, bool *)); | |
100c4561 | 301 | static rtx altivec_expand_abs_builtin PARAMS ((enum insn_code, tree, rtx)); |
ae4b4a02 | 302 | static rtx altivec_expand_predicate_builtin PARAMS ((enum insn_code, const char *, tree, rtx)); |
6525c0e7 | 303 | static rtx altivec_expand_stv_builtin PARAMS ((enum insn_code, tree)); |
0ac081f6 | 304 | static void rs6000_parse_abi_options PARAMS ((void)); |
025d9908 | 305 | static void rs6000_parse_alignment_option PARAMS ((void)); |
c4501e62 | 306 | static void rs6000_parse_tls_size_option PARAMS ((void)); |
5da702b1 | 307 | static void rs6000_parse_yes_no_option (const char *, const char *, int *); |
00b960c7 AH |
308 | static int first_altivec_reg_to_save PARAMS ((void)); |
309 | static unsigned int compute_vrsave_mask PARAMS ((void)); | |
310 | static void is_altivec_return_reg PARAMS ((rtx, void *)); | |
9aa86737 | 311 | static rtx generate_set_vrsave PARAMS ((rtx, rs6000_stack_t *, int)); |
d744e06e AH |
312 | int easy_vector_constant PARAMS ((rtx, enum machine_mode)); |
313 | static int easy_vector_same PARAMS ((rtx, enum machine_mode)); | |
c8e4f0e9 | 314 | static bool is_ev64_opaque_type PARAMS ((tree)); |
96714395 | 315 | static rtx rs6000_dwarf_register_span PARAMS ((rtx)); |
c4501e62 JJ |
316 | static rtx rs6000_legitimize_tls_address PARAMS ((rtx, enum tls_model)); |
317 | static rtx rs6000_tls_get_addr PARAMS ((void)); | |
318 | static rtx rs6000_got_sym PARAMS ((void)); | |
319 | static inline int rs6000_tls_symbol_ref_1 PARAMS ((rtx *, void *)); | |
320 | static const char *rs6000_get_some_local_dynamic_name PARAMS ((void)); | |
321 | static int rs6000_get_some_local_dynamic_name_1 PARAMS ((rtx *, void *)); | |
ded9bf77 | 322 | static rtx rs6000_complex_function_value (enum machine_mode); |
a6c9bed4 | 323 | static rtx rs6000_spe_function_arg (CUMULATIVE_ARGS *, enum machine_mode, tree); |
17211ab5 GK |
324 | |
325 | /* Hash table stuff for keeping track of TOC entries. */ | |
326 | ||
327 | struct toc_hash_struct GTY(()) | |
328 | { | |
329 | /* `key' will satisfy CONSTANT_P; in fact, it will satisfy | |
330 | ASM_OUTPUT_SPECIAL_POOL_ENTRY_P. */ | |
331 | rtx key; | |
332 | enum machine_mode key_mode; | |
333 | int labelno; | |
334 | }; | |
335 | ||
336 | static GTY ((param_is (struct toc_hash_struct))) htab_t toc_hash_table; | |
c81bebd7 MM |
337 | \f |
338 | /* Default register names. */ | |
339 | char rs6000_reg_names[][8] = | |
340 | { | |
802a0058 MM |
341 | "0", "1", "2", "3", "4", "5", "6", "7", |
342 | "8", "9", "10", "11", "12", "13", "14", "15", | |
343 | "16", "17", "18", "19", "20", "21", "22", "23", | |
344 | "24", "25", "26", "27", "28", "29", "30", "31", | |
345 | "0", "1", "2", "3", "4", "5", "6", "7", | |
346 | "8", "9", "10", "11", "12", "13", "14", "15", | |
347 | "16", "17", "18", "19", "20", "21", "22", "23", | |
348 | "24", "25", "26", "27", "28", "29", "30", "31", | |
349 | "mq", "lr", "ctr","ap", | |
350 | "0", "1", "2", "3", "4", "5", "6", "7", | |
0ac081f6 AH |
351 | "xer", |
352 | /* AltiVec registers. */ | |
0cd5e3a1 AH |
353 | "0", "1", "2", "3", "4", "5", "6", "7", |
354 | "8", "9", "10", "11", "12", "13", "14", "15", | |
355 | "16", "17", "18", "19", "20", "21", "22", "23", | |
356 | "24", "25", "26", "27", "28", "29", "30", "31", | |
59a4c851 AH |
357 | "vrsave", "vscr", |
358 | /* SPE registers. */ | |
359 | "spe_acc", "spefscr" | |
c81bebd7 MM |
360 | }; |
361 | ||
362 | #ifdef TARGET_REGNAMES | |
8b60264b | 363 | static const char alt_reg_names[][8] = |
c81bebd7 | 364 | { |
802a0058 MM |
365 | "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7", |
366 | "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15", | |
367 | "%r16", "%r17", "%r18", "%r19", "%r20", "%r21", "%r22", "%r23", | |
368 | "%r24", "%r25", "%r26", "%r27", "%r28", "%r29", "%r30", "%r31", | |
369 | "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7", | |
370 | "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15", | |
371 | "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23", | |
372 | "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31", | |
373 | "mq", "lr", "ctr", "ap", | |
374 | "%cr0", "%cr1", "%cr2", "%cr3", "%cr4", "%cr5", "%cr6", "%cr7", | |
0ac081f6 | 375 | "xer", |
59a4c851 | 376 | /* AltiVec registers. */ |
0ac081f6 | 377 | "%v0", "%v1", "%v2", "%v3", "%v4", "%v5", "%v6", "%v7", |
59a4c851 AH |
378 | "%v8", "%v9", "%v10", "%v11", "%v12", "%v13", "%v14", "%v15", |
379 | "%v16", "%v17", "%v18", "%v19", "%v20", "%v21", "%v22", "%v23", | |
380 | "%v24", "%v25", "%v26", "%v27", "%v28", "%v29", "%v30", "%v31", | |
381 | "vrsave", "vscr", | |
382 | /* SPE registers. */ | |
383 | "spe_acc", "spefscr" | |
c81bebd7 MM |
384 | }; |
385 | #endif | |
9878760c | 386 | \f |
daf11973 MM |
387 | #ifndef MASK_STRICT_ALIGN |
388 | #define MASK_STRICT_ALIGN 0 | |
389 | #endif | |
ffcfcb5f AM |
390 | #ifndef TARGET_PROFILE_KERNEL |
391 | #define TARGET_PROFILE_KERNEL 0 | |
392 | #endif | |
3961e8fe RH |
393 | |
394 | /* The VRSAVE bitmask puts bit %v0 as the most significant bit. */ | |
395 | #define ALTIVEC_REG_BIT(REGNO) (0x80000000 >> ((REGNO) - FIRST_ALTIVEC_REGNO)) | |
c4501e62 JJ |
396 | |
397 | /* Return 1 for a symbol ref for a thread-local storage symbol. */ | |
398 | #define RS6000_SYMBOL_REF_TLS_P(RTX) \ | |
399 | (GET_CODE (RTX) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (RTX) != 0) | |
672a6f42 NB |
400 | \f |
401 | /* Initialize the GCC target structure. */ | |
91d231cb JM |
402 | #undef TARGET_ATTRIBUTE_TABLE |
403 | #define TARGET_ATTRIBUTE_TABLE rs6000_attribute_table | |
a5c76ee6 ZW |
404 | #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES |
405 | #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES rs6000_set_default_type_attributes | |
daf11973 | 406 | |
301d03af RS |
407 | #undef TARGET_ASM_ALIGNED_DI_OP |
408 | #define TARGET_ASM_ALIGNED_DI_OP DOUBLE_INT_ASM_OP | |
409 | ||
410 | /* Default unaligned ops are only provided for ELF. Find the ops needed | |
411 | for non-ELF systems. */ | |
412 | #ifndef OBJECT_FORMAT_ELF | |
cbaaba19 | 413 | #if TARGET_XCOFF |
ae6c1efd | 414 | /* For XCOFF. rs6000_assemble_integer will handle unaligned DIs on |
301d03af RS |
415 | 64-bit targets. */ |
416 | #undef TARGET_ASM_UNALIGNED_HI_OP | |
417 | #define TARGET_ASM_UNALIGNED_HI_OP "\t.vbyte\t2," | |
418 | #undef TARGET_ASM_UNALIGNED_SI_OP | |
419 | #define TARGET_ASM_UNALIGNED_SI_OP "\t.vbyte\t4," | |
420 | #undef TARGET_ASM_UNALIGNED_DI_OP | |
421 | #define TARGET_ASM_UNALIGNED_DI_OP "\t.vbyte\t8," | |
422 | #else | |
423 | /* For Darwin. */ | |
424 | #undef TARGET_ASM_UNALIGNED_HI_OP | |
425 | #define TARGET_ASM_UNALIGNED_HI_OP "\t.short\t" | |
426 | #undef TARGET_ASM_UNALIGNED_SI_OP | |
427 | #define TARGET_ASM_UNALIGNED_SI_OP "\t.long\t" | |
428 | #endif | |
429 | #endif | |
430 | ||
431 | /* This hook deals with fixups for relocatable code and DI-mode objects | |
432 | in 64-bit code. */ | |
433 | #undef TARGET_ASM_INTEGER | |
434 | #define TARGET_ASM_INTEGER rs6000_assemble_integer | |
435 | ||
93638d7a AM |
436 | #ifdef HAVE_GAS_HIDDEN |
437 | #undef TARGET_ASM_ASSEMBLE_VISIBILITY | |
438 | #define TARGET_ASM_ASSEMBLE_VISIBILITY rs6000_assemble_visibility | |
439 | #endif | |
440 | ||
c4501e62 JJ |
441 | #undef TARGET_HAVE_TLS |
442 | #define TARGET_HAVE_TLS HAVE_AS_TLS | |
443 | ||
444 | #undef TARGET_CANNOT_FORCE_CONST_MEM | |
445 | #define TARGET_CANNOT_FORCE_CONST_MEM rs6000_tls_referenced_p | |
446 | ||
08c148a8 NB |
447 | #undef TARGET_ASM_FUNCTION_PROLOGUE |
448 | #define TARGET_ASM_FUNCTION_PROLOGUE rs6000_output_function_prologue | |
449 | #undef TARGET_ASM_FUNCTION_EPILOGUE | |
450 | #define TARGET_ASM_FUNCTION_EPILOGUE rs6000_output_function_epilogue | |
451 | ||
b54cf83a DE |
452 | #undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE |
453 | #define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE rs6000_use_dfa_pipeline_interface | |
b54cf83a DE |
454 | #undef TARGET_SCHED_VARIABLE_ISSUE |
455 | #define TARGET_SCHED_VARIABLE_ISSUE rs6000_variable_issue | |
456 | ||
c237e94a ZW |
457 | #undef TARGET_SCHED_ISSUE_RATE |
458 | #define TARGET_SCHED_ISSUE_RATE rs6000_issue_rate | |
459 | #undef TARGET_SCHED_ADJUST_COST | |
460 | #define TARGET_SCHED_ADJUST_COST rs6000_adjust_cost | |
461 | #undef TARGET_SCHED_ADJUST_PRIORITY | |
462 | #define TARGET_SCHED_ADJUST_PRIORITY rs6000_adjust_priority | |
463 | ||
be12c2b0 VM |
464 | #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD |
465 | #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD rs6000_use_sched_lookahead | |
466 | ||
0ac081f6 AH |
467 | #undef TARGET_INIT_BUILTINS |
468 | #define TARGET_INIT_BUILTINS rs6000_init_builtins | |
469 | ||
470 | #undef TARGET_EXPAND_BUILTIN | |
471 | #define TARGET_EXPAND_BUILTIN rs6000_expand_builtin | |
472 | ||
f1384257 | 473 | #if TARGET_MACHO |
0e5dbd9b DE |
474 | #undef TARGET_BINDS_LOCAL_P |
475 | #define TARGET_BINDS_LOCAL_P rs6000_binds_local_p | |
f1384257 | 476 | #endif |
0e5dbd9b | 477 | |
3961e8fe RH |
478 | #undef TARGET_ASM_OUTPUT_MI_THUNK |
479 | #define TARGET_ASM_OUTPUT_MI_THUNK rs6000_output_mi_thunk | |
480 | ||
3961e8fe | 481 | #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK |
5b71a4e7 | 482 | #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_tree_hwi_hwi_tree_true |
00b960c7 | 483 | |
4977bab6 ZW |
484 | #undef TARGET_FUNCTION_OK_FOR_SIBCALL |
485 | #define TARGET_FUNCTION_OK_FOR_SIBCALL rs6000_function_ok_for_sibcall | |
486 | ||
3c50106f RH |
487 | #undef TARGET_RTX_COSTS |
488 | #define TARGET_RTX_COSTS rs6000_rtx_costs | |
dcefdf67 RH |
489 | #undef TARGET_ADDRESS_COST |
490 | #define TARGET_ADDRESS_COST hook_int_rtx_0 | |
3c50106f | 491 | |
c8e4f0e9 AH |
492 | #undef TARGET_VECTOR_OPAQUE_P |
493 | #define TARGET_VECTOR_OPAQUE_P is_ev64_opaque_type | |
62e1dfcf | 494 | |
96714395 AH |
495 | #undef TARGET_DWARF_REGISTER_SPAN |
496 | #define TARGET_DWARF_REGISTER_SPAN rs6000_dwarf_register_span | |
497 | ||
f6897b10 | 498 | struct gcc_target targetm = TARGET_INITIALIZER; |
672a6f42 | 499 | \f |
5248c961 RK |
500 | /* Override command line options. Mostly we process the processor |
501 | type and sometimes adjust other TARGET_ options. */ | |
502 | ||
503 | void | |
8e3f41e7 | 504 | rs6000_override_options (default_cpu) |
d330fd93 | 505 | const char *default_cpu; |
5248c961 | 506 | { |
c4d38ccb | 507 | size_t i, j; |
8e3f41e7 | 508 | struct rs6000_cpu_select *ptr; |
5248c961 | 509 | |
85638c0d RK |
510 | /* Simplify the entries below by making a mask for any POWER |
511 | variant and any PowerPC variant. */ | |
512 | ||
938937d8 | 513 | #define POWER_MASKS (MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING) |
68c49ffa RK |
514 | #define POWERPC_MASKS (MASK_POWERPC | MASK_PPC_GPOPT \ |
515 | | MASK_PPC_GFXOPT | MASK_POWERPC64) | |
516 | #define POWERPC_OPT_MASKS (MASK_PPC_GPOPT | MASK_PPC_GFXOPT) | |
85638c0d | 517 | |
5248c961 RK |
518 | static struct ptt |
519 | { | |
8b60264b KG |
520 | const char *const name; /* Canonical processor name. */ |
521 | const enum processor_type processor; /* Processor type enum value. */ | |
522 | const int target_enable; /* Target flags to enable. */ | |
523 | const int target_disable; /* Target flags to disable. */ | |
524 | } const processor_target_table[] | |
cf27b467 MM |
525 | = {{"common", PROCESSOR_COMMON, MASK_NEW_MNEMONICS, |
526 | POWER_MASKS | POWERPC_MASKS}, | |
db7f1e43 | 527 | {"power", PROCESSOR_POWER, |
938937d8 | 528 | MASK_POWER | MASK_MULTIPLE | MASK_STRING, |
db7f1e43 | 529 | MASK_POWER2 | POWERPC_MASKS | MASK_NEW_MNEMONICS}, |
8e3f41e7 MM |
530 | {"power2", PROCESSOR_POWER, |
531 | MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING, | |
532 | POWERPC_MASKS | MASK_NEW_MNEMONICS}, | |
c71791e0 DE |
533 | {"power3", PROCESSOR_PPC630, |
534 | MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS, | |
d7b53ca4 | 535 | POWER_MASKS}, |
309323c2 | 536 | {"power4", PROCESSOR_POWER4, |
7f3d8013 | 537 | MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS, |
a12f8290 | 538 | POWER_MASKS}, |
db7f1e43 RK |
539 | {"powerpc", PROCESSOR_POWERPC, |
540 | MASK_POWERPC | MASK_NEW_MNEMONICS, | |
68c49ffa | 541 | POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64}, |
3cb999d8 DE |
542 | {"powerpc64", PROCESSOR_POWERPC64, |
543 | MASK_POWERPC | MASK_POWERPC64 | MASK_NEW_MNEMONICS, | |
544 | POWER_MASKS | POWERPC_OPT_MASKS}, | |
db7f1e43 | 545 | {"rios", PROCESSOR_RIOS1, |
938937d8 | 546 | MASK_POWER | MASK_MULTIPLE | MASK_STRING, |
db7f1e43 RK |
547 | MASK_POWER2 | POWERPC_MASKS | MASK_NEW_MNEMONICS}, |
548 | {"rios1", PROCESSOR_RIOS1, | |
938937d8 | 549 | MASK_POWER | MASK_MULTIPLE | MASK_STRING, |
db7f1e43 RK |
550 | MASK_POWER2 | POWERPC_MASKS | MASK_NEW_MNEMONICS}, |
551 | {"rsc", PROCESSOR_PPC601, | |
938937d8 | 552 | MASK_POWER | MASK_MULTIPLE | MASK_STRING, |
db7f1e43 RK |
553 | MASK_POWER2 | POWERPC_MASKS | MASK_NEW_MNEMONICS}, |
554 | {"rsc1", PROCESSOR_PPC601, | |
938937d8 | 555 | MASK_POWER | MASK_MULTIPLE | MASK_STRING, |
db7f1e43 RK |
556 | MASK_POWER2 | POWERPC_MASKS | MASK_NEW_MNEMONICS}, |
557 | {"rios2", PROCESSOR_RIOS2, | |
938937d8 | 558 | MASK_POWER | MASK_MULTIPLE | MASK_STRING | MASK_POWER2, |
db7f1e43 | 559 | POWERPC_MASKS | MASK_NEW_MNEMONICS}, |
3cb999d8 DE |
560 | {"rs64a", PROCESSOR_RS64A, |
561 | MASK_POWERPC | MASK_NEW_MNEMONICS, | |
562 | POWER_MASKS | POWERPC_OPT_MASKS}, | |
a3a1dbf6 MM |
563 | {"401", PROCESSOR_PPC403, |
564 | MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS, | |
565 | POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64}, | |
49a0b204 | 566 | {"403", PROCESSOR_PPC403, |
daf11973 | 567 | MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS | MASK_STRICT_ALIGN, |
49a0b204 | 568 | POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64}, |
d7a5e253 DE |
569 | {"405", PROCESSOR_PPC405, |
570 | MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS, | |
571 | POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64}, | |
02ca7595 DE |
572 | {"405fp", PROCESSOR_PPC405, |
573 | MASK_POWERPC | MASK_NEW_MNEMONICS, | |
574 | POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64}, | |
575 | {"440", PROCESSOR_PPC440, | |
576 | MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS, | |
577 | POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64}, | |
578 | {"440fp", PROCESSOR_PPC440, | |
4977bab6 ZW |
579 | MASK_POWERPC | MASK_NEW_MNEMONICS, |
580 | POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64}, | |
cf27b467 MM |
581 | {"505", PROCESSOR_MPCCORE, |
582 | MASK_POWERPC | MASK_NEW_MNEMONICS, | |
583 | POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64}, | |
5248c961 | 584 | {"601", PROCESSOR_PPC601, |
938937d8 | 585 | MASK_POWER | MASK_POWERPC | MASK_NEW_MNEMONICS | MASK_MULTIPLE | MASK_STRING, |
68c49ffa | 586 | MASK_POWER2 | POWERPC_OPT_MASKS | MASK_POWERPC64}, |
1ec26da6 | 587 | {"602", PROCESSOR_PPC603, |
cf27b467 MM |
588 | MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS, |
589 | POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64}, | |
5248c961 | 590 | {"603", PROCESSOR_PPC603, |
68c49ffa RK |
591 | MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS, |
592 | POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64}, | |
b6c9286a MM |
593 | {"603e", PROCESSOR_PPC603, |
594 | MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS, | |
595 | POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64}, | |
b5370a88 | 596 | {"ec603e", PROCESSOR_PPC603, |
a3a1dbf6 MM |
597 | MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS, |
598 | POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64}, | |
5248c961 | 599 | {"604", PROCESSOR_PPC604, |
b6c9286a MM |
600 | MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS, |
601 | POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64}, | |
cac8ce95 | 602 | {"604e", PROCESSOR_PPC604e, |
07e6159a MM |
603 | MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS, |
604 | POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64}, | |
b6c9286a | 605 | {"620", PROCESSOR_PPC620, |
68c49ffa | 606 | MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS, |
d7b53ca4 | 607 | POWER_MASKS}, |
3cb999d8 DE |
608 | {"630", PROCESSOR_PPC630, |
609 | MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS, | |
d7b53ca4 | 610 | POWER_MASKS}, |
bef84347 VM |
611 | {"740", PROCESSOR_PPC750, |
612 | MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS, | |
613 | POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64}, | |
614 | {"750", PROCESSOR_PPC750, | |
615 | MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS, | |
616 | POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64}, | |
a4f6c312 SS |
617 | {"7400", PROCESSOR_PPC7400, |
618 | MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS, | |
619 | POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64}, | |
620 | {"7450", PROCESSOR_PPC7450, | |
621 | MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS, | |
622 | POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64}, | |
a3170dc6 AH |
623 | {"8540", PROCESSOR_PPC8540, |
624 | MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS, | |
625 | POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64}, | |
07e6159a MM |
626 | {"801", PROCESSOR_MPCCORE, |
627 | MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS, | |
628 | POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64}, | |
cf27b467 MM |
629 | {"821", PROCESSOR_MPCCORE, |
630 | MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS, | |
631 | POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64}, | |
07e6159a MM |
632 | {"823", PROCESSOR_MPCCORE, |
633 | MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS, | |
634 | POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64}, | |
cf27b467 MM |
635 | {"860", PROCESSOR_MPCCORE, |
636 | MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS, | |
637 | POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64}}; | |
5248c961 | 638 | |
ca7558fc | 639 | const size_t ptt_size = ARRAY_SIZE (processor_target_table); |
5248c961 | 640 | |
a4f6c312 SS |
641 | /* Save current -mmultiple/-mno-multiple status. */ |
642 | int multiple = TARGET_MULTIPLE; | |
643 | /* Save current -mstring/-mno-string status. */ | |
644 | int string = TARGET_STRING; | |
8a61d227 | 645 | |
a4f6c312 | 646 | /* Identify the processor type. */ |
8e3f41e7 | 647 | rs6000_select[0].string = default_cpu; |
3cb999d8 | 648 | rs6000_cpu = TARGET_POWERPC64 ? PROCESSOR_DEFAULT64 : PROCESSOR_DEFAULT; |
8e3f41e7 | 649 | |
b6a1cbae | 650 | for (i = 0; i < ARRAY_SIZE (rs6000_select); i++) |
5248c961 | 651 | { |
8e3f41e7 MM |
652 | ptr = &rs6000_select[i]; |
653 | if (ptr->string != (char *)0 && ptr->string[0] != '\0') | |
5248c961 | 654 | { |
8e3f41e7 MM |
655 | for (j = 0; j < ptt_size; j++) |
656 | if (! strcmp (ptr->string, processor_target_table[j].name)) | |
657 | { | |
658 | if (ptr->set_tune_p) | |
659 | rs6000_cpu = processor_target_table[j].processor; | |
660 | ||
661 | if (ptr->set_arch_p) | |
662 | { | |
663 | target_flags |= processor_target_table[j].target_enable; | |
664 | target_flags &= ~processor_target_table[j].target_disable; | |
665 | } | |
666 | break; | |
667 | } | |
668 | ||
4406229e | 669 | if (j == ptt_size) |
8e3f41e7 | 670 | error ("bad value (%s) for %s switch", ptr->string, ptr->name); |
5248c961 RK |
671 | } |
672 | } | |
8a61d227 | 673 | |
993f19a8 | 674 | if (TARGET_E500) |
a3170dc6 AH |
675 | rs6000_isel = 1; |
676 | ||
dff9f1b6 DE |
677 | /* If we are optimizing big endian systems for space, use the load/store |
678 | multiple and string instructions. */ | |
ef792183 | 679 | if (BYTES_BIG_ENDIAN && optimize_size) |
dff9f1b6 | 680 | target_flags |= MASK_MULTIPLE | MASK_STRING; |
ef792183 | 681 | |
8a61d227 MM |
682 | /* If -mmultiple or -mno-multiple was explicitly used, don't |
683 | override with the processor default */ | |
b21fb038 | 684 | if ((target_flags_explicit & MASK_MULTIPLE) != 0) |
8a61d227 | 685 | target_flags = (target_flags & ~MASK_MULTIPLE) | multiple; |
7e69e155 | 686 | |
a4f6c312 SS |
687 | /* If -mstring or -mno-string was explicitly used, don't override |
688 | with the processor default. */ | |
b21fb038 | 689 | if ((target_flags_explicit & MASK_STRING) != 0) |
1f5515bf | 690 | target_flags = (target_flags & ~MASK_STRING) | string; |
938937d8 | 691 | |
a4f6c312 SS |
692 | /* Don't allow -mmultiple or -mstring on little endian systems |
693 | unless the cpu is a 750, because the hardware doesn't support the | |
694 | instructions used in little endian mode, and causes an alignment | |
695 | trap. The 750 does not cause an alignment trap (except when the | |
696 | target is unaligned). */ | |
bef84347 | 697 | |
b21fb038 | 698 | if (!BYTES_BIG_ENDIAN && rs6000_cpu != PROCESSOR_PPC750) |
7e69e155 MM |
699 | { |
700 | if (TARGET_MULTIPLE) | |
701 | { | |
702 | target_flags &= ~MASK_MULTIPLE; | |
b21fb038 | 703 | if ((target_flags_explicit & MASK_MULTIPLE) != 0) |
7e69e155 MM |
704 | warning ("-mmultiple is not supported on little endian systems"); |
705 | } | |
706 | ||
707 | if (TARGET_STRING) | |
708 | { | |
709 | target_flags &= ~MASK_STRING; | |
b21fb038 | 710 | if ((target_flags_explicit & MASK_STRING) != 0) |
938937d8 | 711 | warning ("-mstring is not supported on little endian systems"); |
7e69e155 MM |
712 | } |
713 | } | |
3933e0e1 | 714 | |
38c1f2d7 MM |
715 | /* Set debug flags */ |
716 | if (rs6000_debug_name) | |
717 | { | |
bfc79d3b | 718 | if (! strcmp (rs6000_debug_name, "all")) |
38c1f2d7 | 719 | rs6000_debug_stack = rs6000_debug_arg = 1; |
bfc79d3b | 720 | else if (! strcmp (rs6000_debug_name, "stack")) |
38c1f2d7 | 721 | rs6000_debug_stack = 1; |
bfc79d3b | 722 | else if (! strcmp (rs6000_debug_name, "arg")) |
38c1f2d7 MM |
723 | rs6000_debug_arg = 1; |
724 | else | |
c725bd79 | 725 | error ("unknown -mdebug-%s switch", rs6000_debug_name); |
38c1f2d7 MM |
726 | } |
727 | ||
57ac7be9 AM |
728 | if (rs6000_traceback_name) |
729 | { | |
730 | if (! strncmp (rs6000_traceback_name, "full", 4)) | |
731 | rs6000_traceback = traceback_full; | |
732 | else if (! strncmp (rs6000_traceback_name, "part", 4)) | |
733 | rs6000_traceback = traceback_part; | |
734 | else if (! strncmp (rs6000_traceback_name, "no", 2)) | |
735 | rs6000_traceback = traceback_none; | |
736 | else | |
737 | error ("unknown -mtraceback arg `%s'; expecting `full', `partial' or `none'", | |
738 | rs6000_traceback_name); | |
739 | } | |
740 | ||
6fa3f289 ZW |
741 | /* Set size of long double */ |
742 | rs6000_long_double_type_size = 64; | |
743 | if (rs6000_long_double_size_string) | |
744 | { | |
745 | char *tail; | |
746 | int size = strtol (rs6000_long_double_size_string, &tail, 10); | |
747 | if (*tail != '\0' || (size != 64 && size != 128)) | |
748 | error ("Unknown switch -mlong-double-%s", | |
749 | rs6000_long_double_size_string); | |
750 | else | |
751 | rs6000_long_double_type_size = size; | |
752 | } | |
753 | ||
0ac081f6 AH |
754 | /* Handle -mabi= options. */ |
755 | rs6000_parse_abi_options (); | |
756 | ||
025d9908 KH |
757 | /* Handle -malign-XXXXX option. */ |
758 | rs6000_parse_alignment_option (); | |
759 | ||
5da702b1 AH |
760 | /* Handle generic -mFOO=YES/NO options. */ |
761 | rs6000_parse_yes_no_option ("vrsave", rs6000_altivec_vrsave_string, | |
762 | &rs6000_altivec_vrsave); | |
763 | rs6000_parse_yes_no_option ("isel", rs6000_isel_string, | |
764 | &rs6000_isel); | |
765 | rs6000_parse_yes_no_option ("spe", rs6000_spe_string, &rs6000_spe); | |
766 | rs6000_parse_yes_no_option ("float-gprs", rs6000_float_gprs_string, | |
767 | &rs6000_float_gprs); | |
993f19a8 | 768 | |
c4501e62 JJ |
769 | /* Handle -mtls-size option. */ |
770 | rs6000_parse_tls_size_option (); | |
771 | ||
a7ae18e2 AH |
772 | #ifdef SUBTARGET_OVERRIDE_OPTIONS |
773 | SUBTARGET_OVERRIDE_OPTIONS; | |
774 | #endif | |
775 | #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS | |
776 | SUBSUBTARGET_OVERRIDE_OPTIONS; | |
777 | #endif | |
778 | ||
5da702b1 AH |
779 | if (TARGET_E500) |
780 | { | |
781 | /* The e500 does not have string instructions, and we set | |
782 | MASK_STRING above when optimizing for size. */ | |
783 | if ((target_flags & MASK_STRING) != 0) | |
784 | target_flags = target_flags & ~MASK_STRING; | |
b6e59a3a AH |
785 | |
786 | /* No SPE means 64-bit long doubles, even if an E500. */ | |
787 | if (rs6000_spe_string != 0 | |
788 | && !strcmp (rs6000_spe_string, "no")) | |
789 | rs6000_long_double_type_size = 64; | |
5da702b1 AH |
790 | } |
791 | else if (rs6000_select[1].string != NULL) | |
792 | { | |
793 | /* For the powerpc-eabispe configuration, we set all these by | |
794 | default, so let's unset them if we manually set another | |
795 | CPU that is not the E500. */ | |
796 | if (rs6000_abi_string == 0) | |
797 | rs6000_spe_abi = 0; | |
798 | if (rs6000_spe_string == 0) | |
799 | rs6000_spe = 0; | |
800 | if (rs6000_float_gprs_string == 0) | |
801 | rs6000_float_gprs = 0; | |
802 | if (rs6000_isel_string == 0) | |
803 | rs6000_isel = 0; | |
b6e59a3a AH |
804 | if (rs6000_long_double_size_string == 0) |
805 | rs6000_long_double_type_size = 64; | |
5da702b1 | 806 | } |
b5044283 | 807 | |
a5c76ee6 ZW |
808 | /* Handle -m(no-)longcall option. This is a bit of a cheap hack, |
809 | using TARGET_OPTIONS to handle a toggle switch, but we're out of | |
810 | bits in target_flags so TARGET_SWITCHES cannot be used. | |
811 | Assumption here is that rs6000_longcall_switch points into the | |
812 | text of the complete option, rather than being a copy, so we can | |
813 | scan back for the presence or absence of the no- modifier. */ | |
814 | if (rs6000_longcall_switch) | |
815 | { | |
816 | const char *base = rs6000_longcall_switch; | |
817 | while (base[-1] != 'm') base--; | |
818 | ||
819 | if (*rs6000_longcall_switch != '\0') | |
820 | error ("invalid option `%s'", base); | |
821 | rs6000_default_long_calls = (base[0] != 'n'); | |
822 | } | |
823 | ||
c81bebd7 | 824 | #ifdef TARGET_REGNAMES |
a4f6c312 SS |
825 | /* If the user desires alternate register names, copy in the |
826 | alternate names now. */ | |
c81bebd7 | 827 | if (TARGET_REGNAMES) |
4e135bdd | 828 | memcpy (rs6000_reg_names, alt_reg_names, sizeof (rs6000_reg_names)); |
c81bebd7 MM |
829 | #endif |
830 | ||
6fa3f289 ZW |
831 | /* Set TARGET_AIX_STRUCT_RET last, after the ABI is determined. |
832 | If -maix-struct-return or -msvr4-struct-return was explicitly | |
833 | used, don't override with the ABI default. */ | |
b21fb038 | 834 | if ((target_flags_explicit & MASK_AIX_STRUCT_RET) == 0) |
6fa3f289 ZW |
835 | { |
836 | if (DEFAULT_ABI == ABI_V4 && !DRAFT_V4_STRUCT_RET) | |
837 | target_flags = (target_flags & ~MASK_AIX_STRUCT_RET); | |
838 | else | |
839 | target_flags |= MASK_AIX_STRUCT_RET; | |
840 | } | |
841 | ||
fcce224d DE |
842 | if (TARGET_LONG_DOUBLE_128 |
843 | && (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)) | |
844 | real_format_for_mode[TFmode - QFmode] = &ibm_extended_format; | |
845 | ||
9ebbca7d GK |
846 | /* Allocate an alias set for register saves & restores from stack. */ |
847 | rs6000_sr_alias_set = new_alias_set (); | |
848 | ||
849 | if (TARGET_TOC) | |
850 | ASM_GENERATE_INTERNAL_LABEL (toc_label_name, "LCTOC", 1); | |
71f123ca | 851 | |
301d03af RS |
852 | /* We can only guarantee the availability of DI pseudo-ops when |
853 | assembling for 64-bit targets. */ | |
ae6c1efd | 854 | if (!TARGET_64BIT) |
301d03af RS |
855 | { |
856 | targetm.asm_out.aligned_op.di = NULL; | |
857 | targetm.asm_out.unaligned_op.di = NULL; | |
858 | } | |
859 | ||
2792d578 DE |
860 | /* Set maximum branch target alignment at two instructions, eight bytes. */ |
861 | align_jumps_max_skip = 8; | |
862 | align_loops_max_skip = 8; | |
863 | ||
71f123ca FS |
864 | /* Arrange to save and restore machine status around nested functions. */ |
865 | init_machine_status = rs6000_init_machine_status; | |
5248c961 | 866 | } |
5accd822 | 867 | |
5da702b1 AH |
868 | /* Handle generic options of the form -mfoo=yes/no. |
869 | NAME is the option name. | |
870 | VALUE is the option value. | |
871 | FLAG is the pointer to the flag where to store a 1 or 0, depending on | |
872 | whether the option value is 'yes' or 'no' respectively. */ | |
993f19a8 | 873 | static void |
5da702b1 | 874 | rs6000_parse_yes_no_option (const char *name, const char *value, int *flag) |
993f19a8 | 875 | { |
5da702b1 | 876 | if (value == 0) |
993f19a8 | 877 | return; |
5da702b1 AH |
878 | else if (!strcmp (value, "yes")) |
879 | *flag = 1; | |
880 | else if (!strcmp (value, "no")) | |
881 | *flag = 0; | |
08b57fb3 | 882 | else |
5da702b1 | 883 | error ("unknown -m%s= option specified: '%s'", name, value); |
08b57fb3 AH |
884 | } |
885 | ||
0ac081f6 | 886 | /* Handle -mabi= options. */ |
00b960c7 AH |
887 | static void |
888 | rs6000_parse_abi_options () | |
0ac081f6 AH |
889 | { |
890 | if (rs6000_abi_string == 0) | |
891 | return; | |
892 | else if (! strcmp (rs6000_abi_string, "altivec")) | |
6fa3f289 | 893 | rs6000_altivec_abi = 1; |
76a773f3 AH |
894 | else if (! strcmp (rs6000_abi_string, "no-altivec")) |
895 | rs6000_altivec_abi = 0; | |
a3170dc6 | 896 | else if (! strcmp (rs6000_abi_string, "spe")) |
01f4962d NS |
897 | { |
898 | rs6000_spe_abi = 1; | |
899 | if (!TARGET_SPE_ABI) | |
900 | error ("not configured for ABI: '%s'", rs6000_abi_string); | |
901 | } | |
902 | ||
a3170dc6 AH |
903 | else if (! strcmp (rs6000_abi_string, "no-spe")) |
904 | rs6000_spe_abi = 0; | |
0ac081f6 | 905 | else |
c725bd79 | 906 | error ("unknown ABI specified: '%s'", rs6000_abi_string); |
0ac081f6 AH |
907 | } |
908 | ||
025d9908 KH |
909 | /* Handle -malign-XXXXXX options. */ |
910 | static void | |
911 | rs6000_parse_alignment_option () | |
912 | { | |
913 | if (rs6000_alignment_string == 0 | |
914 | || ! strcmp (rs6000_alignment_string, "power")) | |
915 | rs6000_alignment_flags = MASK_ALIGN_POWER; | |
916 | else if (! strcmp (rs6000_alignment_string, "natural")) | |
917 | rs6000_alignment_flags = MASK_ALIGN_NATURAL; | |
918 | else | |
919 | error ("unknown -malign-XXXXX option specified: '%s'", | |
920 | rs6000_alignment_string); | |
921 | } | |
922 | ||
c4501e62 JJ |
923 | /* Validate and record the size specified with the -mtls-size option. */ |
924 | ||
925 | static void | |
926 | rs6000_parse_tls_size_option () | |
927 | { | |
928 | if (rs6000_tls_size_string == 0) | |
929 | return; | |
930 | else if (strcmp (rs6000_tls_size_string, "16") == 0) | |
931 | rs6000_tls_size = 16; | |
932 | else if (strcmp (rs6000_tls_size_string, "32") == 0) | |
933 | rs6000_tls_size = 32; | |
934 | else if (strcmp (rs6000_tls_size_string, "64") == 0) | |
935 | rs6000_tls_size = 64; | |
936 | else | |
937 | error ("bad value `%s' for -mtls-size switch", rs6000_tls_size_string); | |
938 | } | |
939 | ||
5accd822 DE |
940 | void |
941 | optimization_options (level, size) | |
e2c953b6 | 942 | int level ATTRIBUTE_UNUSED; |
5accd822 DE |
943 | int size ATTRIBUTE_UNUSED; |
944 | { | |
5accd822 | 945 | } |
3cfa4909 MM |
946 | \f |
947 | /* Do anything needed at the start of the asm file. */ | |
948 | ||
1bc7c5b6 ZW |
949 | static void |
950 | rs6000_file_start () | |
3cfa4909 | 951 | { |
c4d38ccb | 952 | size_t i; |
3cfa4909 | 953 | char buffer[80]; |
d330fd93 | 954 | const char *start = buffer; |
3cfa4909 | 955 | struct rs6000_cpu_select *ptr; |
1bc7c5b6 ZW |
956 | const char *default_cpu = TARGET_CPU_DEFAULT; |
957 | FILE *file = asm_out_file; | |
958 | ||
959 | default_file_start (); | |
960 | ||
961 | #ifdef TARGET_BI_ARCH | |
962 | if ((TARGET_DEFAULT ^ target_flags) & MASK_64BIT) | |
963 | default_cpu = 0; | |
964 | #endif | |
3cfa4909 MM |
965 | |
966 | if (flag_verbose_asm) | |
967 | { | |
968 | sprintf (buffer, "\n%s rs6000/powerpc options:", ASM_COMMENT_START); | |
969 | rs6000_select[0].string = default_cpu; | |
970 | ||
b6a1cbae | 971 | for (i = 0; i < ARRAY_SIZE (rs6000_select); i++) |
3cfa4909 MM |
972 | { |
973 | ptr = &rs6000_select[i]; | |
974 | if (ptr->string != (char *)0 && ptr->string[0] != '\0') | |
975 | { | |
976 | fprintf (file, "%s %s%s", start, ptr->name, ptr->string); | |
977 | start = ""; | |
978 | } | |
979 | } | |
980 | ||
b91da81f | 981 | #ifdef USING_ELFOS_H |
3cfa4909 MM |
982 | switch (rs6000_sdata) |
983 | { | |
984 | case SDATA_NONE: fprintf (file, "%s -msdata=none", start); start = ""; break; | |
985 | case SDATA_DATA: fprintf (file, "%s -msdata=data", start); start = ""; break; | |
986 | case SDATA_SYSV: fprintf (file, "%s -msdata=sysv", start); start = ""; break; | |
987 | case SDATA_EABI: fprintf (file, "%s -msdata=eabi", start); start = ""; break; | |
988 | } | |
989 | ||
990 | if (rs6000_sdata && g_switch_value) | |
991 | { | |
307b599c MK |
992 | fprintf (file, "%s -G " HOST_WIDE_INT_PRINT_UNSIGNED, start, |
993 | g_switch_value); | |
3cfa4909 MM |
994 | start = ""; |
995 | } | |
996 | #endif | |
997 | ||
998 | if (*start == '\0') | |
949ea356 | 999 | putc ('\n', file); |
3cfa4909 MM |
1000 | } |
1001 | } | |
5248c961 | 1002 | \f |
a0ab749a | 1003 | /* Return nonzero if this function is known to have a null epilogue. */ |
9878760c RK |
1004 | |
1005 | int | |
1006 | direct_return () | |
1007 | { | |
4697a36c MM |
1008 | if (reload_completed) |
1009 | { | |
1010 | rs6000_stack_t *info = rs6000_stack_info (); | |
1011 | ||
1012 | if (info->first_gp_reg_save == 32 | |
1013 | && info->first_fp_reg_save == 64 | |
00b960c7 | 1014 | && info->first_altivec_reg_save == LAST_ALTIVEC_REGNO + 1 |
c81fc13e DE |
1015 | && ! info->lr_save_p |
1016 | && ! info->cr_save_p | |
00b960c7 | 1017 | && info->vrsave_mask == 0 |
c81fc13e | 1018 | && ! info->push_p) |
4697a36c MM |
1019 | return 1; |
1020 | } | |
1021 | ||
1022 | return 0; | |
9878760c RK |
1023 | } |
1024 | ||
1025 | /* Returns 1 always. */ | |
1026 | ||
1027 | int | |
1028 | any_operand (op, mode) | |
592696dd | 1029 | rtx op ATTRIBUTE_UNUSED; |
296b8152 | 1030 | enum machine_mode mode ATTRIBUTE_UNUSED; |
9878760c RK |
1031 | { |
1032 | return 1; | |
1033 | } | |
1034 | ||
a4f6c312 | 1035 | /* Returns 1 if op is the count register. */ |
38c1f2d7 | 1036 | int |
a4f6c312 | 1037 | count_register_operand (op, mode) |
592696dd | 1038 | rtx op; |
296b8152 | 1039 | enum machine_mode mode ATTRIBUTE_UNUSED; |
b6c9286a MM |
1040 | { |
1041 | if (GET_CODE (op) != REG) | |
1042 | return 0; | |
1043 | ||
1044 | if (REGNO (op) == COUNT_REGISTER_REGNUM) | |
1045 | return 1; | |
1046 | ||
1047 | if (REGNO (op) > FIRST_PSEUDO_REGISTER) | |
1048 | return 1; | |
1049 | ||
1050 | return 0; | |
1051 | } | |
1052 | ||
0ec4e2a8 AH |
1053 | /* Returns 1 if op is an altivec register. */ |
1054 | int | |
1055 | altivec_register_operand (op, mode) | |
1056 | rtx op; | |
1057 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
1058 | { | |
1059 | ||
1060 | return (register_operand (op, mode) | |
1061 | && (GET_CODE (op) != REG | |
1062 | || REGNO (op) > FIRST_PSEUDO_REGISTER | |
1063 | || ALTIVEC_REGNO_P (REGNO (op)))); | |
1064 | } | |
1065 | ||
38c1f2d7 | 1066 | int |
a4f6c312 | 1067 | xer_operand (op, mode) |
592696dd | 1068 | rtx op; |
296b8152 | 1069 | enum machine_mode mode ATTRIBUTE_UNUSED; |
802a0058 MM |
1070 | { |
1071 | if (GET_CODE (op) != REG) | |
1072 | return 0; | |
1073 | ||
9ebbca7d | 1074 | if (XER_REGNO_P (REGNO (op))) |
802a0058 MM |
1075 | return 1; |
1076 | ||
802a0058 MM |
1077 | return 0; |
1078 | } | |
1079 | ||
c859cda6 | 1080 | /* Return 1 if OP is a signed 8-bit constant. Int multiplication |
6f317ef3 | 1081 | by such constants completes more quickly. */ |
c859cda6 DJ |
1082 | |
1083 | int | |
1084 | s8bit_cint_operand (op, mode) | |
1085 | rtx op; | |
1086 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
1087 | { | |
1088 | return ( GET_CODE (op) == CONST_INT | |
1089 | && (INTVAL (op) >= -128 && INTVAL (op) <= 127)); | |
1090 | } | |
1091 | ||
9878760c RK |
1092 | /* Return 1 if OP is a constant that can fit in a D field. */ |
1093 | ||
1094 | int | |
1095 | short_cint_operand (op, mode) | |
592696dd | 1096 | rtx op; |
296b8152 | 1097 | enum machine_mode mode ATTRIBUTE_UNUSED; |
9878760c | 1098 | { |
5f59ecb7 DE |
1099 | return (GET_CODE (op) == CONST_INT |
1100 | && CONST_OK_FOR_LETTER_P (INTVAL (op), 'I')); | |
9878760c RK |
1101 | } |
1102 | ||
5519a4f9 | 1103 | /* Similar for an unsigned D field. */ |
9878760c RK |
1104 | |
1105 | int | |
1106 | u_short_cint_operand (op, mode) | |
592696dd | 1107 | rtx op; |
296b8152 | 1108 | enum machine_mode mode ATTRIBUTE_UNUSED; |
9878760c | 1109 | { |
19684119 | 1110 | return (GET_CODE (op) == CONST_INT |
c1f11548 | 1111 | && CONST_OK_FOR_LETTER_P (INTVAL (op) & GET_MODE_MASK (mode), 'K')); |
9878760c RK |
1112 | } |
1113 | ||
dcfedcd0 RK |
1114 | /* Return 1 if OP is a CONST_INT that cannot fit in a signed D field. */ |
1115 | ||
1116 | int | |
1117 | non_short_cint_operand (op, mode) | |
592696dd | 1118 | rtx op; |
296b8152 | 1119 | enum machine_mode mode ATTRIBUTE_UNUSED; |
dcfedcd0 RK |
1120 | { |
1121 | return (GET_CODE (op) == CONST_INT | |
a7653a2c | 1122 | && (unsigned HOST_WIDE_INT) (INTVAL (op) + 0x8000) >= 0x10000); |
dcfedcd0 RK |
1123 | } |
1124 | ||
2bfcf297 DB |
1125 | /* Returns 1 if OP is a CONST_INT that is a positive value |
1126 | and an exact power of 2. */ | |
1127 | ||
1128 | int | |
1129 | exact_log2_cint_operand (op, mode) | |
592696dd | 1130 | rtx op; |
2bfcf297 DB |
1131 | enum machine_mode mode ATTRIBUTE_UNUSED; |
1132 | { | |
1133 | return (GET_CODE (op) == CONST_INT | |
1134 | && INTVAL (op) > 0 | |
1135 | && exact_log2 (INTVAL (op)) >= 0); | |
1136 | } | |
1137 | ||
9878760c RK |
1138 | /* Returns 1 if OP is a register that is not special (i.e., not MQ, |
1139 | ctr, or lr). */ | |
1140 | ||
1141 | int | |
cd2b37d9 | 1142 | gpc_reg_operand (op, mode) |
592696dd | 1143 | rtx op; |
9878760c RK |
1144 | enum machine_mode mode; |
1145 | { | |
1146 | return (register_operand (op, mode) | |
802a0058 | 1147 | && (GET_CODE (op) != REG |
9ebbca7d GK |
1148 | || (REGNO (op) >= ARG_POINTER_REGNUM |
1149 | && !XER_REGNO_P (REGNO (op))) | |
1150 | || REGNO (op) < MQ_REGNO)); | |
9878760c RK |
1151 | } |
1152 | ||
1153 | /* Returns 1 if OP is either a pseudo-register or a register denoting a | |
1154 | CR field. */ | |
1155 | ||
1156 | int | |
1157 | cc_reg_operand (op, mode) | |
592696dd | 1158 | rtx op; |
9878760c RK |
1159 | enum machine_mode mode; |
1160 | { | |
1161 | return (register_operand (op, mode) | |
1162 | && (GET_CODE (op) != REG | |
1163 | || REGNO (op) >= FIRST_PSEUDO_REGISTER | |
1164 | || CR_REGNO_P (REGNO (op)))); | |
1165 | } | |
1166 | ||
815cdc52 MM |
1167 | /* Returns 1 if OP is either a pseudo-register or a register denoting a |
1168 | CR field that isn't CR0. */ | |
1169 | ||
1170 | int | |
1171 | cc_reg_not_cr0_operand (op, mode) | |
592696dd | 1172 | rtx op; |
815cdc52 MM |
1173 | enum machine_mode mode; |
1174 | { | |
1175 | return (register_operand (op, mode) | |
1176 | && (GET_CODE (op) != REG | |
1177 | || REGNO (op) >= FIRST_PSEUDO_REGISTER | |
1178 | || CR_REGNO_NOT_CR0_P (REGNO (op)))); | |
1179 | } | |
1180 | ||
a4f6c312 SS |
1181 | /* Returns 1 if OP is either a constant integer valid for a D-field or |
1182 | a non-special register. If a register, it must be in the proper | |
1183 | mode unless MODE is VOIDmode. */ | |
9878760c RK |
1184 | |
1185 | int | |
1186 | reg_or_short_operand (op, mode) | |
592696dd | 1187 | rtx op; |
9878760c RK |
1188 | enum machine_mode mode; |
1189 | { | |
f5a28898 | 1190 | return short_cint_operand (op, mode) || gpc_reg_operand (op, mode); |
9878760c RK |
1191 | } |
1192 | ||
a4f6c312 SS |
1193 | /* Similar, except check if the negation of the constant would be |
1194 | valid for a D-field. */ | |
9878760c RK |
1195 | |
1196 | int | |
1197 | reg_or_neg_short_operand (op, mode) | |
592696dd | 1198 | rtx op; |
9878760c RK |
1199 | enum machine_mode mode; |
1200 | { | |
1201 | if (GET_CODE (op) == CONST_INT) | |
1202 | return CONST_OK_FOR_LETTER_P (INTVAL (op), 'P'); | |
1203 | ||
cd2b37d9 | 1204 | return gpc_reg_operand (op, mode); |
9878760c RK |
1205 | } |
1206 | ||
768070a0 TR |
1207 | /* Returns 1 if OP is either a constant integer valid for a DS-field or |
1208 | a non-special register. If a register, it must be in the proper | |
1209 | mode unless MODE is VOIDmode. */ | |
1210 | ||
1211 | int | |
1212 | reg_or_aligned_short_operand (op, mode) | |
1213 | rtx op; | |
1214 | enum machine_mode mode; | |
1215 | { | |
1216 | if (gpc_reg_operand (op, mode)) | |
1217 | return 1; | |
1218 | else if (short_cint_operand (op, mode) && !(INTVAL (op) & 3)) | |
1219 | return 1; | |
1220 | ||
1221 | return 0; | |
1222 | } | |
1223 | ||
1224 | ||
a4f6c312 SS |
1225 | /* Return 1 if the operand is either a register or an integer whose |
1226 | high-order 16 bits are zero. */ | |
9878760c RK |
1227 | |
1228 | int | |
1229 | reg_or_u_short_operand (op, mode) | |
592696dd | 1230 | rtx op; |
9878760c RK |
1231 | enum machine_mode mode; |
1232 | { | |
e675f625 | 1233 | return u_short_cint_operand (op, mode) || gpc_reg_operand (op, mode); |
9878760c RK |
1234 | } |
1235 | ||
1236 | /* Return 1 is the operand is either a non-special register or ANY | |
1237 | constant integer. */ | |
1238 | ||
1239 | int | |
1240 | reg_or_cint_operand (op, mode) | |
592696dd | 1241 | rtx op; |
9878760c RK |
1242 | enum machine_mode mode; |
1243 | { | |
a4f6c312 | 1244 | return (GET_CODE (op) == CONST_INT || gpc_reg_operand (op, mode)); |
f6bf7de2 DE |
1245 | } |
1246 | ||
1247 | /* Return 1 is the operand is either a non-special register or ANY | |
1248 | 32-bit signed constant integer. */ | |
1249 | ||
1250 | int | |
1251 | reg_or_arith_cint_operand (op, mode) | |
592696dd | 1252 | rtx op; |
f6bf7de2 DE |
1253 | enum machine_mode mode; |
1254 | { | |
a4f6c312 SS |
1255 | return (gpc_reg_operand (op, mode) |
1256 | || (GET_CODE (op) == CONST_INT | |
f6bf7de2 | 1257 | #if HOST_BITS_PER_WIDE_INT != 32 |
a4f6c312 SS |
1258 | && ((unsigned HOST_WIDE_INT) (INTVAL (op) + 0x80000000) |
1259 | < (unsigned HOST_WIDE_INT) 0x100000000ll) | |
f6bf7de2 | 1260 | #endif |
a4f6c312 | 1261 | )); |
9878760c RK |
1262 | } |
1263 | ||
2bfcf297 DB |
1264 | /* Return 1 is the operand is either a non-special register or a 32-bit |
1265 | signed constant integer valid for 64-bit addition. */ | |
1266 | ||
1267 | int | |
1268 | reg_or_add_cint64_operand (op, mode) | |
592696dd | 1269 | rtx op; |
2bfcf297 DB |
1270 | enum machine_mode mode; |
1271 | { | |
a4f6c312 SS |
1272 | return (gpc_reg_operand (op, mode) |
1273 | || (GET_CODE (op) == CONST_INT | |
a65c591c | 1274 | #if HOST_BITS_PER_WIDE_INT == 32 |
a4f6c312 | 1275 | && INTVAL (op) < 0x7fff8000 |
a65c591c | 1276 | #else |
a4f6c312 SS |
1277 | && ((unsigned HOST_WIDE_INT) (INTVAL (op) + 0x80008000) |
1278 | < 0x100000000ll) | |
2bfcf297 | 1279 | #endif |
a4f6c312 | 1280 | )); |
2bfcf297 DB |
1281 | } |
1282 | ||
1283 | /* Return 1 is the operand is either a non-special register or a 32-bit | |
1284 | signed constant integer valid for 64-bit subtraction. */ | |
1285 | ||
1286 | int | |
1287 | reg_or_sub_cint64_operand (op, mode) | |
592696dd | 1288 | rtx op; |
2bfcf297 DB |
1289 | enum machine_mode mode; |
1290 | { | |
a4f6c312 SS |
1291 | return (gpc_reg_operand (op, mode) |
1292 | || (GET_CODE (op) == CONST_INT | |
a65c591c | 1293 | #if HOST_BITS_PER_WIDE_INT == 32 |
a4f6c312 | 1294 | && (- INTVAL (op)) < 0x7fff8000 |
a65c591c | 1295 | #else |
a4f6c312 SS |
1296 | && ((unsigned HOST_WIDE_INT) ((- INTVAL (op)) + 0x80008000) |
1297 | < 0x100000000ll) | |
2bfcf297 | 1298 | #endif |
a4f6c312 | 1299 | )); |
2bfcf297 DB |
1300 | } |
1301 | ||
9ebbca7d GK |
1302 | /* Return 1 is the operand is either a non-special register or ANY |
1303 | 32-bit unsigned constant integer. */ | |
1304 | ||
1305 | int | |
1d328b19 | 1306 | reg_or_logical_cint_operand (op, mode) |
592696dd | 1307 | rtx op; |
9ebbca7d GK |
1308 | enum machine_mode mode; |
1309 | { | |
1d328b19 GK |
1310 | if (GET_CODE (op) == CONST_INT) |
1311 | { | |
1312 | if (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT) | |
1313 | { | |
1314 | if (GET_MODE_BITSIZE (mode) <= 32) | |
a4f6c312 | 1315 | abort (); |
1d328b19 GK |
1316 | |
1317 | if (INTVAL (op) < 0) | |
1318 | return 0; | |
1319 | } | |
1320 | ||
1321 | return ((INTVAL (op) & GET_MODE_MASK (mode) | |
0858c623 | 1322 | & (~ (unsigned HOST_WIDE_INT) 0xffffffff)) == 0); |
1d328b19 GK |
1323 | } |
1324 | else if (GET_CODE (op) == CONST_DOUBLE) | |
1325 | { | |
1326 | if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT | |
1327 | || mode != DImode) | |
a4f6c312 | 1328 | abort (); |
1d328b19 GK |
1329 | |
1330 | return CONST_DOUBLE_HIGH (op) == 0; | |
1331 | } | |
1332 | else | |
1333 | return gpc_reg_operand (op, mode); | |
9ebbca7d GK |
1334 | } |
1335 | ||
51d3e7d6 | 1336 | /* Return 1 if the operand is an operand that can be loaded via the GOT. */ |
766a866c MM |
1337 | |
1338 | int | |
1339 | got_operand (op, mode) | |
592696dd | 1340 | rtx op; |
296b8152 | 1341 | enum machine_mode mode ATTRIBUTE_UNUSED; |
766a866c MM |
1342 | { |
1343 | return (GET_CODE (op) == SYMBOL_REF | |
1344 | || GET_CODE (op) == CONST | |
1345 | || GET_CODE (op) == LABEL_REF); | |
1346 | } | |
1347 | ||
38c1f2d7 MM |
1348 | /* Return 1 if the operand is a simple references that can be loaded via |
1349 | the GOT (labels involving addition aren't allowed). */ | |
1350 | ||
1351 | int | |
1352 | got_no_const_operand (op, mode) | |
592696dd | 1353 | rtx op; |
296b8152 | 1354 | enum machine_mode mode ATTRIBUTE_UNUSED; |
38c1f2d7 MM |
1355 | { |
1356 | return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF); | |
1357 | } | |
1358 | ||
4e74d8ec MM |
1359 | /* Return the number of instructions it takes to form a constant in an |
1360 | integer register. */ | |
1361 | ||
1362 | static int | |
1363 | num_insns_constant_wide (value) | |
1364 | HOST_WIDE_INT value; | |
1365 | { | |
1366 | /* signed constant loadable with {cal|addi} */ | |
5f59ecb7 | 1367 | if (CONST_OK_FOR_LETTER_P (value, 'I')) |
0865c631 GK |
1368 | return 1; |
1369 | ||
4e74d8ec | 1370 | /* constant loadable with {cau|addis} */ |
5f59ecb7 | 1371 | else if (CONST_OK_FOR_LETTER_P (value, 'L')) |
4e74d8ec MM |
1372 | return 1; |
1373 | ||
5f59ecb7 | 1374 | #if HOST_BITS_PER_WIDE_INT == 64 |
c81fc13e | 1375 | else if (TARGET_POWERPC64) |
4e74d8ec | 1376 | { |
a65c591c DE |
1377 | HOST_WIDE_INT low = ((value & 0xffffffff) ^ 0x80000000) - 0x80000000; |
1378 | HOST_WIDE_INT high = value >> 31; | |
4e74d8ec | 1379 | |
a65c591c | 1380 | if (high == 0 || high == -1) |
4e74d8ec MM |
1381 | return 2; |
1382 | ||
a65c591c | 1383 | high >>= 1; |
4e74d8ec | 1384 | |
a65c591c | 1385 | if (low == 0) |
4e74d8ec | 1386 | return num_insns_constant_wide (high) + 1; |
4e74d8ec MM |
1387 | else |
1388 | return (num_insns_constant_wide (high) | |
e396202a | 1389 | + num_insns_constant_wide (low) + 1); |
4e74d8ec MM |
1390 | } |
1391 | #endif | |
1392 | ||
1393 | else | |
1394 | return 2; | |
1395 | } | |
1396 | ||
1397 | int | |
1398 | num_insns_constant (op, mode) | |
1399 | rtx op; | |
1400 | enum machine_mode mode; | |
1401 | { | |
4e74d8ec | 1402 | if (GET_CODE (op) == CONST_INT) |
0d30d435 DE |
1403 | { |
1404 | #if HOST_BITS_PER_WIDE_INT == 64 | |
4e2c1c44 DE |
1405 | if ((INTVAL (op) >> 31) != 0 && (INTVAL (op) >> 31) != -1 |
1406 | && mask64_operand (op, mode)) | |
0d30d435 DE |
1407 | return 2; |
1408 | else | |
1409 | #endif | |
1410 | return num_insns_constant_wide (INTVAL (op)); | |
1411 | } | |
4e74d8ec | 1412 | |
6fc48950 MM |
1413 | else if (GET_CODE (op) == CONST_DOUBLE && mode == SFmode) |
1414 | { | |
1415 | long l; | |
1416 | REAL_VALUE_TYPE rv; | |
1417 | ||
1418 | REAL_VALUE_FROM_CONST_DOUBLE (rv, op); | |
1419 | REAL_VALUE_TO_TARGET_SINGLE (rv, l); | |
e72247f4 | 1420 | return num_insns_constant_wide ((HOST_WIDE_INT) l); |
6fc48950 MM |
1421 | } |
1422 | ||
47ad8c61 | 1423 | else if (GET_CODE (op) == CONST_DOUBLE) |
4e74d8ec | 1424 | { |
47ad8c61 MM |
1425 | HOST_WIDE_INT low; |
1426 | HOST_WIDE_INT high; | |
1427 | long l[2]; | |
1428 | REAL_VALUE_TYPE rv; | |
1429 | int endian = (WORDS_BIG_ENDIAN == 0); | |
4e74d8ec | 1430 | |
47ad8c61 MM |
1431 | if (mode == VOIDmode || mode == DImode) |
1432 | { | |
1433 | high = CONST_DOUBLE_HIGH (op); | |
1434 | low = CONST_DOUBLE_LOW (op); | |
1435 | } | |
1436 | else | |
1437 | { | |
1438 | REAL_VALUE_FROM_CONST_DOUBLE (rv, op); | |
1439 | REAL_VALUE_TO_TARGET_DOUBLE (rv, l); | |
1440 | high = l[endian]; | |
1441 | low = l[1 - endian]; | |
1442 | } | |
4e74d8ec | 1443 | |
47ad8c61 MM |
1444 | if (TARGET_32BIT) |
1445 | return (num_insns_constant_wide (low) | |
1446 | + num_insns_constant_wide (high)); | |
4e74d8ec MM |
1447 | |
1448 | else | |
47ad8c61 | 1449 | { |
e72247f4 | 1450 | if (high == 0 && low >= 0) |
47ad8c61 MM |
1451 | return num_insns_constant_wide (low); |
1452 | ||
e72247f4 | 1453 | else if (high == -1 && low < 0) |
47ad8c61 MM |
1454 | return num_insns_constant_wide (low); |
1455 | ||
a260abc9 DE |
1456 | else if (mask64_operand (op, mode)) |
1457 | return 2; | |
1458 | ||
47ad8c61 MM |
1459 | else if (low == 0) |
1460 | return num_insns_constant_wide (high) + 1; | |
1461 | ||
1462 | else | |
1463 | return (num_insns_constant_wide (high) | |
1464 | + num_insns_constant_wide (low) + 1); | |
1465 | } | |
4e74d8ec MM |
1466 | } |
1467 | ||
1468 | else | |
1469 | abort (); | |
1470 | } | |
1471 | ||
a4f6c312 SS |
1472 | /* Return 1 if the operand is a CONST_DOUBLE and it can be put into a |
1473 | register with one instruction per word. We only do this if we can | |
1474 | safely read CONST_DOUBLE_{LOW,HIGH}. */ | |
9878760c RK |
1475 | |
1476 | int | |
1477 | easy_fp_constant (op, mode) | |
592696dd SS |
1478 | rtx op; |
1479 | enum machine_mode mode; | |
9878760c | 1480 | { |
9878760c RK |
1481 | if (GET_CODE (op) != CONST_DOUBLE |
1482 | || GET_MODE (op) != mode | |
4e74d8ec | 1483 | || (GET_MODE_CLASS (mode) != MODE_FLOAT && mode != DImode)) |
9878760c RK |
1484 | return 0; |
1485 | ||
a4f6c312 | 1486 | /* Consider all constants with -msoft-float to be easy. */ |
a3170dc6 AH |
1487 | if ((TARGET_SOFT_FLOAT || !TARGET_FPRS) |
1488 | && mode != DImode) | |
b6c9286a MM |
1489 | return 1; |
1490 | ||
a4f6c312 | 1491 | /* If we are using V.4 style PIC, consider all constants to be hard. */ |
f607bc57 | 1492 | if (flag_pic && DEFAULT_ABI == ABI_V4) |
a7273471 MM |
1493 | return 0; |
1494 | ||
5ae4759c | 1495 | #ifdef TARGET_RELOCATABLE |
a4f6c312 SS |
1496 | /* Similarly if we are using -mrelocatable, consider all constants |
1497 | to be hard. */ | |
5ae4759c MM |
1498 | if (TARGET_RELOCATABLE) |
1499 | return 0; | |
1500 | #endif | |
1501 | ||
fcce224d DE |
1502 | if (mode == TFmode) |
1503 | { | |
1504 | long k[4]; | |
1505 | REAL_VALUE_TYPE rv; | |
1506 | ||
1507 | REAL_VALUE_FROM_CONST_DOUBLE (rv, op); | |
1508 | REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv, k); | |
1509 | ||
1510 | return (num_insns_constant_wide ((HOST_WIDE_INT) k[0]) == 1 | |
1511 | && num_insns_constant_wide ((HOST_WIDE_INT) k[1]) == 1 | |
1512 | && num_insns_constant_wide ((HOST_WIDE_INT) k[2]) == 1 | |
1513 | && num_insns_constant_wide ((HOST_WIDE_INT) k[3]) == 1); | |
1514 | } | |
1515 | ||
1516 | else if (mode == DFmode) | |
042259f2 DE |
1517 | { |
1518 | long k[2]; | |
1519 | REAL_VALUE_TYPE rv; | |
1520 | ||
1521 | REAL_VALUE_FROM_CONST_DOUBLE (rv, op); | |
1522 | REAL_VALUE_TO_TARGET_DOUBLE (rv, k); | |
9878760c | 1523 | |
a65c591c DE |
1524 | return (num_insns_constant_wide ((HOST_WIDE_INT) k[0]) == 1 |
1525 | && num_insns_constant_wide ((HOST_WIDE_INT) k[1]) == 1); | |
042259f2 | 1526 | } |
4e74d8ec MM |
1527 | |
1528 | else if (mode == SFmode) | |
042259f2 DE |
1529 | { |
1530 | long l; | |
1531 | REAL_VALUE_TYPE rv; | |
1532 | ||
1533 | REAL_VALUE_FROM_CONST_DOUBLE (rv, op); | |
1534 | REAL_VALUE_TO_TARGET_SINGLE (rv, l); | |
9878760c | 1535 | |
4e74d8ec | 1536 | return num_insns_constant_wide (l) == 1; |
042259f2 | 1537 | } |
4e74d8ec | 1538 | |
a260abc9 | 1539 | else if (mode == DImode) |
c81fc13e | 1540 | return ((TARGET_POWERPC64 |
a260abc9 DE |
1541 | && GET_CODE (op) == CONST_DOUBLE && CONST_DOUBLE_LOW (op) == 0) |
1542 | || (num_insns_constant (op, DImode) <= 2)); | |
4e74d8ec | 1543 | |
a9098fd0 GK |
1544 | else if (mode == SImode) |
1545 | return 1; | |
4e74d8ec MM |
1546 | else |
1547 | abort (); | |
9878760c | 1548 | } |
8f75773e | 1549 | |
72ac76be | 1550 | /* Return nonzero if all elements of a vector have the same value. */ |
69ef87e2 AH |
1551 | |
1552 | static int | |
d744e06e AH |
1553 | easy_vector_same (op, mode) |
1554 | rtx op; | |
1555 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
1556 | { | |
1557 | int units, i, cst; | |
1558 | ||
1559 | units = CONST_VECTOR_NUNITS (op); | |
1560 | ||
1561 | cst = INTVAL (CONST_VECTOR_ELT (op, 0)); | |
1562 | for (i = 1; i < units; ++i) | |
1563 | if (INTVAL (CONST_VECTOR_ELT (op, i)) != cst) | |
1564 | break; | |
1565 | if (i == units) | |
1566 | return 1; | |
1567 | return 0; | |
1568 | } | |
1569 | ||
1570 | /* Return 1 if the operand is a CONST_INT and can be put into a | |
1571 | register without using memory. */ | |
1572 | ||
1573 | int | |
1574 | easy_vector_constant (op, mode) | |
69ef87e2 | 1575 | rtx op; |
d744e06e | 1576 | enum machine_mode mode; |
69ef87e2 | 1577 | { |
d744e06e | 1578 | int cst, cst2; |
69ef87e2 | 1579 | |
d744e06e AH |
1580 | if (GET_CODE (op) != CONST_VECTOR |
1581 | || (!TARGET_ALTIVEC | |
1582 | && !TARGET_SPE)) | |
69ef87e2 AH |
1583 | return 0; |
1584 | ||
d744e06e AH |
1585 | if (zero_constant (op, mode) |
1586 | && ((TARGET_ALTIVEC && ALTIVEC_VECTOR_MODE (mode)) | |
1587 | || (TARGET_SPE && SPE_VECTOR_MODE (mode)))) | |
1588 | return 1; | |
69ef87e2 | 1589 | |
d744e06e AH |
1590 | if (GET_MODE_CLASS (mode) != MODE_VECTOR_INT) |
1591 | return 0; | |
1592 | ||
f5119d10 AH |
1593 | if (TARGET_SPE && mode == V1DImode) |
1594 | return 0; | |
1595 | ||
d744e06e AH |
1596 | cst = INTVAL (CONST_VECTOR_ELT (op, 0)); |
1597 | cst2 = INTVAL (CONST_VECTOR_ELT (op, 1)); | |
1598 | ||
1599 | /* Limit SPE vectors to 15 bits signed. These we can generate with: | |
1600 | li r0, CONSTANT1 | |
1601 | evmergelo r0, r0, r0 | |
1602 | li r0, CONSTANT2 | |
1603 | ||
1604 | I don't know how efficient it would be to allow bigger constants, | |
1605 | considering we'll have an extra 'ori' for every 'li'. I doubt 5 | |
1606 | instructions is better than a 64-bit memory load, but I don't | |
1607 | have the e500 timing specs. */ | |
1608 | if (TARGET_SPE && mode == V2SImode | |
1609 | && cst >= -0x7fff && cst <= 0x7fff | |
f5119d10 | 1610 | && cst2 >= -0x7fff && cst2 <= 0x7fff) |
d744e06e AH |
1611 | return 1; |
1612 | ||
1613 | if (TARGET_ALTIVEC && EASY_VECTOR_15 (cst, op, mode)) | |
1614 | return 1; | |
1615 | ||
1616 | if (TARGET_ALTIVEC && EASY_VECTOR_15_ADD_SELF (cst, op, mode)) | |
1617 | return 1; | |
1618 | ||
1619 | return 0; | |
1620 | } | |
1621 | ||
1622 | /* Same as easy_vector_constant but only for EASY_VECTOR_15_ADD_SELF. */ | |
1623 | ||
1624 | int | |
1625 | easy_vector_constant_add_self (op, mode) | |
1626 | rtx op; | |
1627 | enum machine_mode mode; | |
1628 | { | |
1629 | int cst; | |
1630 | ||
1631 | if (!easy_vector_constant (op, mode)) | |
1632 | return 0; | |
1633 | ||
1634 | cst = INTVAL (CONST_VECTOR_ELT (op, 0)); | |
1635 | ||
1636 | return TARGET_ALTIVEC && EASY_VECTOR_15_ADD_SELF (cst, op, mode); | |
1637 | } | |
1638 | ||
1639 | const char * | |
1640 | output_vec_const_move (operands) | |
1641 | rtx *operands; | |
1642 | { | |
1643 | int cst, cst2; | |
1644 | enum machine_mode mode; | |
1645 | rtx dest, vec; | |
1646 | ||
1647 | dest = operands[0]; | |
1648 | vec = operands[1]; | |
69ef87e2 | 1649 | |
d744e06e AH |
1650 | cst = INTVAL (CONST_VECTOR_ELT (vec, 0)); |
1651 | cst2 = INTVAL (CONST_VECTOR_ELT (vec, 1)); | |
1652 | mode = GET_MODE (dest); | |
69ef87e2 | 1653 | |
d744e06e AH |
1654 | if (TARGET_ALTIVEC) |
1655 | { | |
1656 | if (zero_constant (vec, mode)) | |
1657 | return "vxor %0,%0,%0"; | |
1658 | else if (EASY_VECTOR_15 (cst, vec, mode)) | |
98ef3137 | 1659 | { |
d744e06e AH |
1660 | operands[1] = GEN_INT (cst); |
1661 | switch (mode) | |
1662 | { | |
1663 | case V4SImode: | |
1664 | return "vspltisw %0,%1"; | |
1665 | case V8HImode: | |
1666 | return "vspltish %0,%1"; | |
1667 | case V16QImode: | |
1668 | return "vspltisb %0,%1"; | |
1669 | default: | |
1670 | abort (); | |
1671 | } | |
98ef3137 | 1672 | } |
d744e06e AH |
1673 | else if (EASY_VECTOR_15_ADD_SELF (cst, vec, mode)) |
1674 | return "#"; | |
1675 | else | |
1676 | abort (); | |
69ef87e2 AH |
1677 | } |
1678 | ||
d744e06e AH |
1679 | if (TARGET_SPE) |
1680 | { | |
1681 | /* Vector constant 0 is handled as a splitter of V2SI, and in the | |
1682 | pattern of V1DI, V4HI, and V2SF. | |
1683 | ||
1684 | FIXME: We should probabl return # and add post reload | |
1685 | splitters for these, but this way is so easy ;-). | |
1686 | */ | |
1687 | operands[1] = GEN_INT (cst); | |
1688 | operands[2] = GEN_INT (cst2); | |
1689 | if (cst == cst2) | |
1690 | return "li %0,%1\n\tevmergelo %0,%0,%0"; | |
1691 | else | |
1692 | return "li %0,%1\n\tevmergelo %0,%0,%0\n\tli %0,%2"; | |
1693 | } | |
1694 | ||
1695 | abort (); | |
69ef87e2 AH |
1696 | } |
1697 | ||
1698 | /* Return 1 if the operand is the constant 0. This works for scalars | |
1699 | as well as vectors. */ | |
1700 | int | |
1701 | zero_constant (op, mode) | |
1702 | rtx op; | |
1703 | enum machine_mode mode; | |
1704 | { | |
1705 | return op == CONST0_RTX (mode); | |
1706 | } | |
1707 | ||
50a0b056 GK |
1708 | /* Return 1 if the operand is 0.0. */ |
1709 | int | |
1710 | zero_fp_constant (op, mode) | |
592696dd SS |
1711 | rtx op; |
1712 | enum machine_mode mode; | |
50a0b056 GK |
1713 | { |
1714 | return GET_MODE_CLASS (mode) == MODE_FLOAT && op == CONST0_RTX (mode); | |
1715 | } | |
1716 | ||
a4f6c312 SS |
1717 | /* Return 1 if the operand is in volatile memory. Note that during |
1718 | the RTL generation phase, memory_operand does not return TRUE for | |
b6c9286a MM |
1719 | volatile memory references. So this function allows us to |
1720 | recognize volatile references where its safe. */ | |
1721 | ||
1722 | int | |
1723 | volatile_mem_operand (op, mode) | |
592696dd | 1724 | rtx op; |
b6c9286a MM |
1725 | enum machine_mode mode; |
1726 | { | |
1727 | if (GET_CODE (op) != MEM) | |
1728 | return 0; | |
1729 | ||
1730 | if (!MEM_VOLATILE_P (op)) | |
1731 | return 0; | |
1732 | ||
1733 | if (mode != GET_MODE (op)) | |
1734 | return 0; | |
1735 | ||
1736 | if (reload_completed) | |
1737 | return memory_operand (op, mode); | |
1738 | ||
1739 | if (reload_in_progress) | |
1740 | return strict_memory_address_p (mode, XEXP (op, 0)); | |
1741 | ||
1742 | return memory_address_p (mode, XEXP (op, 0)); | |
1743 | } | |
1744 | ||
97f6e72f | 1745 | /* Return 1 if the operand is an offsettable memory operand. */ |
914c2e77 RK |
1746 | |
1747 | int | |
97f6e72f | 1748 | offsettable_mem_operand (op, mode) |
592696dd | 1749 | rtx op; |
914c2e77 RK |
1750 | enum machine_mode mode; |
1751 | { | |
97f6e72f | 1752 | return ((GET_CODE (op) == MEM) |
677a9668 | 1753 | && offsettable_address_p (reload_completed || reload_in_progress, |
97f6e72f | 1754 | mode, XEXP (op, 0))); |
914c2e77 RK |
1755 | } |
1756 | ||
9878760c RK |
1757 | /* Return 1 if the operand is either an easy FP constant (see above) or |
1758 | memory. */ | |
1759 | ||
1760 | int | |
1761 | mem_or_easy_const_operand (op, mode) | |
592696dd | 1762 | rtx op; |
9878760c RK |
1763 | enum machine_mode mode; |
1764 | { | |
1765 | return memory_operand (op, mode) || easy_fp_constant (op, mode); | |
1766 | } | |
1767 | ||
1768 | /* Return 1 if the operand is either a non-special register or an item | |
5f59ecb7 | 1769 | that can be used as the operand of a `mode' add insn. */ |
9878760c RK |
1770 | |
1771 | int | |
1772 | add_operand (op, mode) | |
592696dd | 1773 | rtx op; |
9878760c RK |
1774 | enum machine_mode mode; |
1775 | { | |
2bfcf297 | 1776 | if (GET_CODE (op) == CONST_INT) |
e72247f4 DE |
1777 | return (CONST_OK_FOR_LETTER_P (INTVAL (op), 'I') |
1778 | || CONST_OK_FOR_LETTER_P (INTVAL (op), 'L')); | |
2bfcf297 DB |
1779 | |
1780 | return gpc_reg_operand (op, mode); | |
9878760c RK |
1781 | } |
1782 | ||
dcfedcd0 RK |
1783 | /* Return 1 if OP is a constant but not a valid add_operand. */ |
1784 | ||
1785 | int | |
1786 | non_add_cint_operand (op, mode) | |
592696dd | 1787 | rtx op; |
296b8152 | 1788 | enum machine_mode mode ATTRIBUTE_UNUSED; |
dcfedcd0 RK |
1789 | { |
1790 | return (GET_CODE (op) == CONST_INT | |
e72247f4 DE |
1791 | && !CONST_OK_FOR_LETTER_P (INTVAL (op), 'I') |
1792 | && !CONST_OK_FOR_LETTER_P (INTVAL (op), 'L')); | |
dcfedcd0 RK |
1793 | } |
1794 | ||
9878760c RK |
1795 | /* Return 1 if the operand is a non-special register or a constant that |
1796 | can be used as the operand of an OR or XOR insn on the RS/6000. */ | |
1797 | ||
1798 | int | |
1799 | logical_operand (op, mode) | |
592696dd | 1800 | rtx op; |
9878760c RK |
1801 | enum machine_mode mode; |
1802 | { | |
40501e5f | 1803 | HOST_WIDE_INT opl, oph; |
1d328b19 | 1804 | |
dfbdccdb GK |
1805 | if (gpc_reg_operand (op, mode)) |
1806 | return 1; | |
1d328b19 | 1807 | |
dfbdccdb | 1808 | if (GET_CODE (op) == CONST_INT) |
40501e5f AM |
1809 | { |
1810 | opl = INTVAL (op) & GET_MODE_MASK (mode); | |
1811 | ||
1812 | #if HOST_BITS_PER_WIDE_INT <= 32 | |
1813 | if (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT && opl < 0) | |
1814 | return 0; | |
1815 | #endif | |
1816 | } | |
dfbdccdb GK |
1817 | else if (GET_CODE (op) == CONST_DOUBLE) |
1818 | { | |
1d328b19 | 1819 | if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT) |
40501e5f | 1820 | abort (); |
1d328b19 GK |
1821 | |
1822 | opl = CONST_DOUBLE_LOW (op); | |
1823 | oph = CONST_DOUBLE_HIGH (op); | |
40501e5f | 1824 | if (oph != 0) |
38886f37 | 1825 | return 0; |
dfbdccdb GK |
1826 | } |
1827 | else | |
1828 | return 0; | |
1d328b19 | 1829 | |
40501e5f AM |
1830 | return ((opl & ~ (unsigned HOST_WIDE_INT) 0xffff) == 0 |
1831 | || (opl & ~ (unsigned HOST_WIDE_INT) 0xffff0000) == 0); | |
9878760c RK |
1832 | } |
1833 | ||
dcfedcd0 | 1834 | /* Return 1 if C is a constant that is not a logical operand (as |
1d328b19 | 1835 | above), but could be split into one. */ |
dcfedcd0 RK |
1836 | |
1837 | int | |
1838 | non_logical_cint_operand (op, mode) | |
592696dd | 1839 | rtx op; |
5f59ecb7 | 1840 | enum machine_mode mode; |
dcfedcd0 | 1841 | { |
dfbdccdb | 1842 | return ((GET_CODE (op) == CONST_INT || GET_CODE (op) == CONST_DOUBLE) |
1d328b19 GK |
1843 | && ! logical_operand (op, mode) |
1844 | && reg_or_logical_cint_operand (op, mode)); | |
dcfedcd0 RK |
1845 | } |
1846 | ||
19ba8161 | 1847 | /* Return 1 if C is a constant that can be encoded in a 32-bit mask on the |
9878760c RK |
1848 | RS/6000. It is if there are no more than two 1->0 or 0->1 transitions. |
1849 | Reject all ones and all zeros, since these should have been optimized | |
1850 | away and confuse the making of MB and ME. */ | |
1851 | ||
1852 | int | |
19ba8161 | 1853 | mask_operand (op, mode) |
592696dd | 1854 | rtx op; |
19ba8161 | 1855 | enum machine_mode mode ATTRIBUTE_UNUSED; |
9878760c | 1856 | { |
02071907 | 1857 | HOST_WIDE_INT c, lsb; |
9878760c | 1858 | |
19ba8161 DE |
1859 | if (GET_CODE (op) != CONST_INT) |
1860 | return 0; | |
1861 | ||
1862 | c = INTVAL (op); | |
1863 | ||
57deb3a1 AM |
1864 | /* Fail in 64-bit mode if the mask wraps around because the upper |
1865 | 32-bits of the mask will all be 1s, contrary to GCC's internal view. */ | |
1866 | if (TARGET_POWERPC64 && (c & 0x80000001) == 0x80000001) | |
1867 | return 0; | |
1868 | ||
c5059423 AM |
1869 | /* We don't change the number of transitions by inverting, |
1870 | so make sure we start with the LS bit zero. */ | |
1871 | if (c & 1) | |
1872 | c = ~c; | |
1873 | ||
1874 | /* Reject all zeros or all ones. */ | |
1875 | if (c == 0) | |
9878760c RK |
1876 | return 0; |
1877 | ||
c5059423 AM |
1878 | /* Find the first transition. */ |
1879 | lsb = c & -c; | |
1880 | ||
1881 | /* Invert to look for a second transition. */ | |
1882 | c = ~c; | |
9878760c | 1883 | |
c5059423 AM |
1884 | /* Erase first transition. */ |
1885 | c &= -lsb; | |
9878760c | 1886 | |
c5059423 AM |
1887 | /* Find the second transition (if any). */ |
1888 | lsb = c & -c; | |
1889 | ||
1890 | /* Match if all the bits above are 1's (or c is zero). */ | |
1891 | return c == -lsb; | |
9878760c RK |
1892 | } |
1893 | ||
0ba1b2ff AM |
1894 | /* Return 1 for the PowerPC64 rlwinm corner case. */ |
1895 | ||
1896 | int | |
1897 | mask_operand_wrap (op, mode) | |
1898 | rtx op; | |
1899 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
1900 | { | |
1901 | HOST_WIDE_INT c, lsb; | |
1902 | ||
1903 | if (GET_CODE (op) != CONST_INT) | |
1904 | return 0; | |
1905 | ||
1906 | c = INTVAL (op); | |
1907 | ||
1908 | if ((c & 0x80000001) != 0x80000001) | |
1909 | return 0; | |
1910 | ||
1911 | c = ~c; | |
1912 | if (c == 0) | |
1913 | return 0; | |
1914 | ||
1915 | lsb = c & -c; | |
1916 | c = ~c; | |
1917 | c &= -lsb; | |
1918 | lsb = c & -c; | |
1919 | return c == -lsb; | |
1920 | } | |
1921 | ||
a260abc9 DE |
1922 | /* Return 1 if the operand is a constant that is a PowerPC64 mask. |
1923 | It is if there are no more than one 1->0 or 0->1 transitions. | |
0ba1b2ff AM |
1924 | Reject all zeros, since zero should have been optimized away and |
1925 | confuses the making of MB and ME. */ | |
9878760c RK |
1926 | |
1927 | int | |
a260abc9 | 1928 | mask64_operand (op, mode) |
592696dd | 1929 | rtx op; |
0ba1b2ff | 1930 | enum machine_mode mode ATTRIBUTE_UNUSED; |
a260abc9 DE |
1931 | { |
1932 | if (GET_CODE (op) == CONST_INT) | |
1933 | { | |
02071907 | 1934 | HOST_WIDE_INT c, lsb; |
a260abc9 | 1935 | |
c5059423 | 1936 | c = INTVAL (op); |
a260abc9 | 1937 | |
0ba1b2ff | 1938 | /* Reject all zeros. */ |
c5059423 | 1939 | if (c == 0) |
e2c953b6 DE |
1940 | return 0; |
1941 | ||
0ba1b2ff AM |
1942 | /* We don't change the number of transitions by inverting, |
1943 | so make sure we start with the LS bit zero. */ | |
1944 | if (c & 1) | |
1945 | c = ~c; | |
1946 | ||
c5059423 AM |
1947 | /* Find the transition, and check that all bits above are 1's. */ |
1948 | lsb = c & -c; | |
e3981aab DE |
1949 | |
1950 | /* Match if all the bits above are 1's (or c is zero). */ | |
c5059423 | 1951 | return c == -lsb; |
e2c953b6 | 1952 | } |
0ba1b2ff AM |
1953 | return 0; |
1954 | } | |
1955 | ||
1956 | /* Like mask64_operand, but allow up to three transitions. This | |
1957 | predicate is used by insn patterns that generate two rldicl or | |
1958 | rldicr machine insns. */ | |
1959 | ||
1960 | int | |
1961 | mask64_2_operand (op, mode) | |
1962 | rtx op; | |
1963 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
1964 | { | |
1965 | if (GET_CODE (op) == CONST_INT) | |
a260abc9 | 1966 | { |
0ba1b2ff | 1967 | HOST_WIDE_INT c, lsb; |
a260abc9 | 1968 | |
0ba1b2ff | 1969 | c = INTVAL (op); |
a260abc9 | 1970 | |
0ba1b2ff AM |
1971 | /* Disallow all zeros. */ |
1972 | if (c == 0) | |
1973 | return 0; | |
a260abc9 | 1974 | |
0ba1b2ff AM |
1975 | /* We don't change the number of transitions by inverting, |
1976 | so make sure we start with the LS bit zero. */ | |
1977 | if (c & 1) | |
1978 | c = ~c; | |
a260abc9 | 1979 | |
0ba1b2ff AM |
1980 | /* Find the first transition. */ |
1981 | lsb = c & -c; | |
a260abc9 | 1982 | |
0ba1b2ff AM |
1983 | /* Invert to look for a second transition. */ |
1984 | c = ~c; | |
1985 | ||
1986 | /* Erase first transition. */ | |
1987 | c &= -lsb; | |
1988 | ||
1989 | /* Find the second transition. */ | |
1990 | lsb = c & -c; | |
1991 | ||
1992 | /* Invert to look for a third transition. */ | |
1993 | c = ~c; | |
1994 | ||
1995 | /* Erase second transition. */ | |
1996 | c &= -lsb; | |
1997 | ||
1998 | /* Find the third transition (if any). */ | |
1999 | lsb = c & -c; | |
2000 | ||
2001 | /* Match if all the bits above are 1's (or c is zero). */ | |
2002 | return c == -lsb; | |
2003 | } | |
2004 | return 0; | |
2005 | } | |
2006 | ||
2007 | /* Generates shifts and masks for a pair of rldicl or rldicr insns to | |
2008 | implement ANDing by the mask IN. */ | |
2009 | void | |
2010 | build_mask64_2_operands (in, out) | |
2011 | rtx in; | |
2012 | rtx *out; | |
2013 | { | |
2014 | #if HOST_BITS_PER_WIDE_INT >= 64 | |
2015 | unsigned HOST_WIDE_INT c, lsb, m1, m2; | |
2016 | int shift; | |
2017 | ||
2018 | if (GET_CODE (in) != CONST_INT) | |
2019 | abort (); | |
2020 | ||
2021 | c = INTVAL (in); | |
2022 | if (c & 1) | |
2023 | { | |
2024 | /* Assume c initially something like 0x00fff000000fffff. The idea | |
2025 | is to rotate the word so that the middle ^^^^^^ group of zeros | |
2026 | is at the MS end and can be cleared with an rldicl mask. We then | |
2027 | rotate back and clear off the MS ^^ group of zeros with a | |
2028 | second rldicl. */ | |
2029 | c = ~c; /* c == 0xff000ffffff00000 */ | |
2030 | lsb = c & -c; /* lsb == 0x0000000000100000 */ | |
2031 | m1 = -lsb; /* m1 == 0xfffffffffff00000 */ | |
2032 | c = ~c; /* c == 0x00fff000000fffff */ | |
2033 | c &= -lsb; /* c == 0x00fff00000000000 */ | |
2034 | lsb = c & -c; /* lsb == 0x0000100000000000 */ | |
2035 | c = ~c; /* c == 0xff000fffffffffff */ | |
2036 | c &= -lsb; /* c == 0xff00000000000000 */ | |
2037 | shift = 0; | |
2038 | while ((lsb >>= 1) != 0) | |
2039 | shift++; /* shift == 44 on exit from loop */ | |
2040 | m1 <<= 64 - shift; /* m1 == 0xffffff0000000000 */ | |
2041 | m1 = ~m1; /* m1 == 0x000000ffffffffff */ | |
2042 | m2 = ~c; /* m2 == 0x00ffffffffffffff */ | |
a260abc9 DE |
2043 | } |
2044 | else | |
0ba1b2ff AM |
2045 | { |
2046 | /* Assume c initially something like 0xff000f0000000000. The idea | |
2047 | is to rotate the word so that the ^^^ middle group of zeros | |
2048 | is at the LS end and can be cleared with an rldicr mask. We then | |
2049 | rotate back and clear off the LS group of ^^^^^^^^^^ zeros with | |
2050 | a second rldicr. */ | |
2051 | lsb = c & -c; /* lsb == 0x0000010000000000 */ | |
2052 | m2 = -lsb; /* m2 == 0xffffff0000000000 */ | |
2053 | c = ~c; /* c == 0x00fff0ffffffffff */ | |
2054 | c &= -lsb; /* c == 0x00fff00000000000 */ | |
2055 | lsb = c & -c; /* lsb == 0x0000100000000000 */ | |
2056 | c = ~c; /* c == 0xff000fffffffffff */ | |
2057 | c &= -lsb; /* c == 0xff00000000000000 */ | |
2058 | shift = 0; | |
2059 | while ((lsb >>= 1) != 0) | |
2060 | shift++; /* shift == 44 on exit from loop */ | |
2061 | m1 = ~c; /* m1 == 0x00ffffffffffffff */ | |
2062 | m1 >>= shift; /* m1 == 0x0000000000000fff */ | |
2063 | m1 = ~m1; /* m1 == 0xfffffffffffff000 */ | |
2064 | } | |
2065 | ||
2066 | /* Note that when we only have two 0->1 and 1->0 transitions, one of the | |
2067 | masks will be all 1's. We are guaranteed more than one transition. */ | |
2068 | out[0] = GEN_INT (64 - shift); | |
2069 | out[1] = GEN_INT (m1); | |
2070 | out[2] = GEN_INT (shift); | |
2071 | out[3] = GEN_INT (m2); | |
2072 | #else | |
045572c7 GK |
2073 | (void)in; |
2074 | (void)out; | |
0ba1b2ff AM |
2075 | abort (); |
2076 | #endif | |
a260abc9 DE |
2077 | } |
2078 | ||
2079 | /* Return 1 if the operand is either a non-special register or a constant | |
2080 | that can be used as the operand of a PowerPC64 logical AND insn. */ | |
2081 | ||
2082 | int | |
2083 | and64_operand (op, mode) | |
592696dd | 2084 | rtx op; |
9878760c RK |
2085 | enum machine_mode mode; |
2086 | { | |
a4f6c312 | 2087 | if (fixed_regs[CR0_REGNO]) /* CR0 not available, don't do andi./andis. */ |
52d3af72 DE |
2088 | return (gpc_reg_operand (op, mode) || mask64_operand (op, mode)); |
2089 | ||
2090 | return (logical_operand (op, mode) || mask64_operand (op, mode)); | |
9878760c RK |
2091 | } |
2092 | ||
0ba1b2ff AM |
2093 | /* Like the above, but also match constants that can be implemented |
2094 | with two rldicl or rldicr insns. */ | |
2095 | ||
2096 | int | |
2097 | and64_2_operand (op, mode) | |
2098 | rtx op; | |
2099 | enum machine_mode mode; | |
2100 | { | |
2101 | if (fixed_regs[CR0_REGNO]) /* CR0 not available, don't do andi./andis. */ | |
2102 | return gpc_reg_operand (op, mode) || mask64_2_operand (op, mode); | |
2103 | ||
2104 | return logical_operand (op, mode) || mask64_2_operand (op, mode); | |
2105 | } | |
2106 | ||
a260abc9 DE |
2107 | /* Return 1 if the operand is either a non-special register or a |
2108 | constant that can be used as the operand of an RS/6000 logical AND insn. */ | |
dcfedcd0 RK |
2109 | |
2110 | int | |
a260abc9 | 2111 | and_operand (op, mode) |
592696dd | 2112 | rtx op; |
a260abc9 | 2113 | enum machine_mode mode; |
dcfedcd0 | 2114 | { |
a4f6c312 | 2115 | if (fixed_regs[CR0_REGNO]) /* CR0 not available, don't do andi./andis. */ |
52d3af72 DE |
2116 | return (gpc_reg_operand (op, mode) || mask_operand (op, mode)); |
2117 | ||
2118 | return (logical_operand (op, mode) || mask_operand (op, mode)); | |
dcfedcd0 RK |
2119 | } |
2120 | ||
9878760c RK |
2121 | /* Return 1 if the operand is a general register or memory operand. */ |
2122 | ||
2123 | int | |
2124 | reg_or_mem_operand (op, mode) | |
592696dd SS |
2125 | rtx op; |
2126 | enum machine_mode mode; | |
9878760c | 2127 | { |
b6c9286a MM |
2128 | return (gpc_reg_operand (op, mode) |
2129 | || memory_operand (op, mode) | |
2130 | || volatile_mem_operand (op, mode)); | |
9878760c RK |
2131 | } |
2132 | ||
a7a813f7 | 2133 | /* Return 1 if the operand is a general register or memory operand without |
3cb999d8 | 2134 | pre_inc or pre_dec which produces invalid form of PowerPC lwa |
a7a813f7 RK |
2135 | instruction. */ |
2136 | ||
2137 | int | |
2138 | lwa_operand (op, mode) | |
592696dd SS |
2139 | rtx op; |
2140 | enum machine_mode mode; | |
a7a813f7 RK |
2141 | { |
2142 | rtx inner = op; | |
2143 | ||
2144 | if (reload_completed && GET_CODE (inner) == SUBREG) | |
2145 | inner = SUBREG_REG (inner); | |
2146 | ||
2147 | return gpc_reg_operand (inner, mode) | |
2148 | || (memory_operand (inner, mode) | |
2149 | && GET_CODE (XEXP (inner, 0)) != PRE_INC | |
6a40a9d6 DE |
2150 | && GET_CODE (XEXP (inner, 0)) != PRE_DEC |
2151 | && (GET_CODE (XEXP (inner, 0)) != PLUS | |
e903c96a DE |
2152 | || GET_CODE (XEXP (XEXP (inner, 0), 1)) != CONST_INT |
2153 | || INTVAL (XEXP (XEXP (inner, 0), 1)) % 4 == 0)); | |
a7a813f7 RK |
2154 | } |
2155 | ||
cc4d5fec JH |
2156 | /* Return 1 if the operand, used inside a MEM, is a SYMBOL_REF. */ |
2157 | ||
2158 | int | |
2159 | symbol_ref_operand (op, mode) | |
2160 | rtx op; | |
2161 | enum machine_mode mode; | |
2162 | { | |
2163 | if (mode != VOIDmode && GET_MODE (op) != mode) | |
2164 | return 0; | |
2165 | ||
473f51b6 DE |
2166 | return (GET_CODE (op) == SYMBOL_REF |
2167 | && (DEFAULT_ABI != ABI_AIX || SYMBOL_REF_FUNCTION_P (op))); | |
cc4d5fec JH |
2168 | } |
2169 | ||
9878760c | 2170 | /* Return 1 if the operand, used inside a MEM, is a valid first argument |
cc4d5fec | 2171 | to CALL. This is a SYMBOL_REF, a pseudo-register, LR or CTR. */ |
9878760c RK |
2172 | |
2173 | int | |
2174 | call_operand (op, mode) | |
592696dd | 2175 | rtx op; |
9878760c RK |
2176 | enum machine_mode mode; |
2177 | { | |
2178 | if (mode != VOIDmode && GET_MODE (op) != mode) | |
2179 | return 0; | |
2180 | ||
2181 | return (GET_CODE (op) == SYMBOL_REF | |
cc4d5fec JH |
2182 | || (GET_CODE (op) == REG |
2183 | && (REGNO (op) == LINK_REGISTER_REGNUM | |
2184 | || REGNO (op) == COUNT_REGISTER_REGNUM | |
2185 | || REGNO (op) >= FIRST_PSEUDO_REGISTER))); | |
9878760c RK |
2186 | } |
2187 | ||
2af3d377 | 2188 | /* Return 1 if the operand is a SYMBOL_REF for a function known to be in |
d1908feb | 2189 | this file. */ |
2af3d377 RK |
2190 | |
2191 | int | |
2192 | current_file_function_operand (op, mode) | |
592696dd | 2193 | rtx op; |
296b8152 | 2194 | enum machine_mode mode ATTRIBUTE_UNUSED; |
2af3d377 | 2195 | { |
473f51b6 DE |
2196 | return (GET_CODE (op) == SYMBOL_REF |
2197 | && (DEFAULT_ABI != ABI_AIX || SYMBOL_REF_FUNCTION_P (op)) | |
2198 | && (SYMBOL_REF_LOCAL_P (op) | |
2199 | || (op == XEXP (DECL_RTL (current_function_decl), 0)))); | |
2af3d377 RK |
2200 | } |
2201 | ||
9878760c RK |
2202 | /* Return 1 if this operand is a valid input for a move insn. */ |
2203 | ||
2204 | int | |
2205 | input_operand (op, mode) | |
592696dd | 2206 | rtx op; |
9878760c RK |
2207 | enum machine_mode mode; |
2208 | { | |
eb4e8003 | 2209 | /* Memory is always valid. */ |
9878760c RK |
2210 | if (memory_operand (op, mode)) |
2211 | return 1; | |
2212 | ||
34792e82 | 2213 | /* Only a tiny bit of handling for CONSTANT_P_RTX is necessary. */ |
01b4cf2b | 2214 | if (GET_CODE (op) == CONSTANT_P_RTX) |
34792e82 JL |
2215 | return 1; |
2216 | ||
eb4e8003 RK |
2217 | /* For floating-point, easy constants are valid. */ |
2218 | if (GET_MODE_CLASS (mode) == MODE_FLOAT | |
2219 | && CONSTANT_P (op) | |
2220 | && easy_fp_constant (op, mode)) | |
2221 | return 1; | |
2222 | ||
4e74d8ec MM |
2223 | /* Allow any integer constant. */ |
2224 | if (GET_MODE_CLASS (mode) == MODE_INT | |
e675f625 | 2225 | && (GET_CODE (op) == CONST_INT |
e675f625 | 2226 | || GET_CODE (op) == CONST_DOUBLE)) |
4e74d8ec MM |
2227 | return 1; |
2228 | ||
d744e06e AH |
2229 | /* Allow easy vector constants. */ |
2230 | if (GET_CODE (op) == CONST_VECTOR | |
2231 | && easy_vector_constant (op, mode)) | |
2232 | return 1; | |
2233 | ||
eb4e8003 RK |
2234 | /* For floating-point or multi-word mode, the only remaining valid type |
2235 | is a register. */ | |
9878760c RK |
2236 | if (GET_MODE_CLASS (mode) == MODE_FLOAT |
2237 | || GET_MODE_SIZE (mode) > UNITS_PER_WORD) | |
eb4e8003 | 2238 | return register_operand (op, mode); |
9878760c | 2239 | |
88fe15a1 RK |
2240 | /* The only cases left are integral modes one word or smaller (we |
2241 | do not get called for MODE_CC values). These can be in any | |
2242 | register. */ | |
2243 | if (register_operand (op, mode)) | |
a8b3aeda | 2244 | return 1; |
88fe15a1 | 2245 | |
84cf9dda | 2246 | /* A SYMBOL_REF referring to the TOC is valid. */ |
4d588c14 | 2247 | if (legitimate_constant_pool_address_p (op)) |
84cf9dda RK |
2248 | return 1; |
2249 | ||
9ebbca7d | 2250 | /* A constant pool expression (relative to the TOC) is valid */ |
4d588c14 | 2251 | if (toc_relative_expr_p (op)) |
b6c9286a MM |
2252 | return 1; |
2253 | ||
88228c4b MM |
2254 | /* V.4 allows SYMBOL_REFs and CONSTs that are in the small data region |
2255 | to be valid. */ | |
f607bc57 | 2256 | if (DEFAULT_ABI == ABI_V4 |
88228c4b MM |
2257 | && (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST) |
2258 | && small_data_operand (op, Pmode)) | |
2259 | return 1; | |
2260 | ||
042259f2 | 2261 | return 0; |
9878760c | 2262 | } |
7509c759 | 2263 | |
a4f6c312 | 2264 | /* Return 1 for an operand in small memory on V.4/eabi. */ |
7509c759 MM |
2265 | |
2266 | int | |
2267 | small_data_operand (op, mode) | |
296b8152 KG |
2268 | rtx op ATTRIBUTE_UNUSED; |
2269 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
7509c759 | 2270 | { |
38c1f2d7 | 2271 | #if TARGET_ELF |
5f59ecb7 | 2272 | rtx sym_ref; |
7509c759 | 2273 | |
d9407988 | 2274 | if (rs6000_sdata == SDATA_NONE || rs6000_sdata == SDATA_DATA) |
a54d04b7 | 2275 | return 0; |
a54d04b7 | 2276 | |
f607bc57 | 2277 | if (DEFAULT_ABI != ABI_V4) |
7509c759 MM |
2278 | return 0; |
2279 | ||
88228c4b MM |
2280 | if (GET_CODE (op) == SYMBOL_REF) |
2281 | sym_ref = op; | |
2282 | ||
2283 | else if (GET_CODE (op) != CONST | |
2284 | || GET_CODE (XEXP (op, 0)) != PLUS | |
2285 | || GET_CODE (XEXP (XEXP (op, 0), 0)) != SYMBOL_REF | |
2286 | || GET_CODE (XEXP (XEXP (op, 0), 1)) != CONST_INT) | |
7509c759 MM |
2287 | return 0; |
2288 | ||
88228c4b | 2289 | else |
dbf55e53 MM |
2290 | { |
2291 | rtx sum = XEXP (op, 0); | |
2292 | HOST_WIDE_INT summand; | |
2293 | ||
2294 | /* We have to be careful here, because it is the referenced address | |
2295 | that must be 32k from _SDA_BASE_, not just the symbol. */ | |
2296 | summand = INTVAL (XEXP (sum, 1)); | |
307b599c | 2297 | if (summand < 0 || (unsigned HOST_WIDE_INT) summand > g_switch_value) |
dbf55e53 MM |
2298 | return 0; |
2299 | ||
2300 | sym_ref = XEXP (sum, 0); | |
2301 | } | |
88228c4b | 2302 | |
20bfcd69 | 2303 | return SYMBOL_REF_SMALL_P (sym_ref); |
d9407988 MM |
2304 | #else |
2305 | return 0; | |
2306 | #endif | |
7509c759 | 2307 | } |
9ebbca7d | 2308 | \f |
4d588c14 RH |
2309 | /* Subroutines of rs6000_legitimize_address and rs6000_legitimate_address. */ |
2310 | ||
9ebbca7d GK |
2311 | static int |
2312 | constant_pool_expr_1 (op, have_sym, have_toc) | |
2313 | rtx op; | |
2314 | int *have_sym; | |
2315 | int *have_toc; | |
2316 | { | |
2317 | switch (GET_CODE(op)) | |
2318 | { | |
2319 | case SYMBOL_REF: | |
c4501e62 JJ |
2320 | if (RS6000_SYMBOL_REF_TLS_P (op)) |
2321 | return 0; | |
2322 | else if (CONSTANT_POOL_ADDRESS_P (op)) | |
a4f6c312 SS |
2323 | { |
2324 | if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (op), Pmode)) | |
2325 | { | |
2326 | *have_sym = 1; | |
2327 | return 1; | |
2328 | } | |
2329 | else | |
2330 | return 0; | |
2331 | } | |
2332 | else if (! strcmp (XSTR (op, 0), toc_label_name)) | |
2333 | { | |
2334 | *have_toc = 1; | |
2335 | return 1; | |
2336 | } | |
2337 | else | |
2338 | return 0; | |
9ebbca7d GK |
2339 | case PLUS: |
2340 | case MINUS: | |
c1f11548 DE |
2341 | return (constant_pool_expr_1 (XEXP (op, 0), have_sym, have_toc) |
2342 | && constant_pool_expr_1 (XEXP (op, 1), have_sym, have_toc)); | |
9ebbca7d | 2343 | case CONST: |
a4f6c312 | 2344 | return constant_pool_expr_1 (XEXP (op, 0), have_sym, have_toc); |
9ebbca7d | 2345 | case CONST_INT: |
a4f6c312 | 2346 | return 1; |
9ebbca7d | 2347 | default: |
a4f6c312 | 2348 | return 0; |
9ebbca7d GK |
2349 | } |
2350 | } | |
2351 | ||
4d588c14 | 2352 | static bool |
9ebbca7d GK |
2353 | constant_pool_expr_p (op) |
2354 | rtx op; | |
2355 | { | |
2356 | int have_sym = 0; | |
2357 | int have_toc = 0; | |
2358 | return constant_pool_expr_1 (op, &have_sym, &have_toc) && have_sym; | |
2359 | } | |
2360 | ||
4d588c14 | 2361 | static bool |
9ebbca7d GK |
2362 | toc_relative_expr_p (op) |
2363 | rtx op; | |
2364 | { | |
4d588c14 RH |
2365 | int have_sym = 0; |
2366 | int have_toc = 0; | |
2367 | return constant_pool_expr_1 (op, &have_sym, &have_toc) && have_toc; | |
2368 | } | |
2369 | ||
2370 | /* SPE offset addressing is limited to 5-bits worth of double words. */ | |
2371 | #define SPE_CONST_OFFSET_OK(x) (((x) & ~0xf8) == 0) | |
2372 | ||
2373 | bool | |
2374 | legitimate_constant_pool_address_p (x) | |
2375 | rtx x; | |
2376 | { | |
2377 | return (TARGET_TOC | |
2378 | && GET_CODE (x) == PLUS | |
2379 | && GET_CODE (XEXP (x, 0)) == REG | |
2380 | && (TARGET_MINIMAL_TOC || REGNO (XEXP (x, 0)) == TOC_REGISTER) | |
2381 | && constant_pool_expr_p (XEXP (x, 1))); | |
2382 | } | |
2383 | ||
2384 | static bool | |
2385 | legitimate_small_data_p (mode, x) | |
2386 | enum machine_mode mode; | |
2387 | rtx x; | |
2388 | { | |
2389 | return (DEFAULT_ABI == ABI_V4 | |
2390 | && !flag_pic && !TARGET_TOC | |
2391 | && (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST) | |
2392 | && small_data_operand (x, mode)); | |
2393 | } | |
2394 | ||
2395 | static bool | |
2396 | legitimate_offset_address_p (mode, x, strict) | |
2397 | enum machine_mode mode; | |
2398 | rtx x; | |
2399 | int strict; | |
2400 | { | |
2401 | unsigned HOST_WIDE_INT offset, extra; | |
2402 | ||
2403 | if (GET_CODE (x) != PLUS) | |
2404 | return false; | |
2405 | if (GET_CODE (XEXP (x, 0)) != REG) | |
2406 | return false; | |
2407 | if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict)) | |
2408 | return false; | |
2409 | if (GET_CODE (XEXP (x, 1)) != CONST_INT) | |
2410 | return false; | |
2411 | ||
2412 | offset = INTVAL (XEXP (x, 1)); | |
2413 | extra = 0; | |
2414 | switch (mode) | |
2415 | { | |
2416 | case V16QImode: | |
2417 | case V8HImode: | |
2418 | case V4SFmode: | |
2419 | case V4SImode: | |
2420 | /* AltiVec vector modes. Only reg+reg addressing is valid here, | |
2421 | which leaves the only valid constant offset of zero, which by | |
2422 | canonicalization rules is also invalid. */ | |
2423 | return false; | |
2424 | ||
2425 | case V4HImode: | |
2426 | case V2SImode: | |
2427 | case V1DImode: | |
2428 | case V2SFmode: | |
2429 | /* SPE vector modes. */ | |
2430 | return SPE_CONST_OFFSET_OK (offset); | |
2431 | ||
2432 | case DFmode: | |
2433 | case DImode: | |
2434 | if (TARGET_32BIT) | |
2435 | extra = 4; | |
2436 | else if (offset & 3) | |
2437 | return false; | |
2438 | break; | |
2439 | ||
2440 | case TFmode: | |
2441 | case TImode: | |
2442 | if (TARGET_32BIT) | |
2443 | extra = 12; | |
2444 | else if (offset & 3) | |
2445 | return false; | |
2446 | else | |
2447 | extra = 8; | |
2448 | break; | |
2449 | ||
2450 | default: | |
2451 | break; | |
2452 | } | |
2453 | ||
2454 | return (offset + extra >= offset) && (offset + extra + 0x8000 < 0x10000); | |
2455 | } | |
2456 | ||
2457 | static bool | |
2458 | legitimate_indexed_address_p (x, strict) | |
2459 | rtx x; | |
2460 | int strict; | |
2461 | { | |
2462 | rtx op0, op1; | |
2463 | ||
2464 | if (GET_CODE (x) != PLUS) | |
2465 | return false; | |
2466 | op0 = XEXP (x, 0); | |
2467 | op1 = XEXP (x, 1); | |
2468 | ||
2469 | if (!REG_P (op0) || !REG_P (op1)) | |
2470 | return false; | |
2471 | ||
2472 | return ((INT_REG_OK_FOR_BASE_P (op0, strict) | |
2473 | && INT_REG_OK_FOR_INDEX_P (op1, strict)) | |
2474 | || (INT_REG_OK_FOR_BASE_P (op1, strict) | |
2475 | && INT_REG_OK_FOR_INDEX_P (op0, strict))); | |
9ebbca7d GK |
2476 | } |
2477 | ||
4d588c14 RH |
2478 | static inline bool |
2479 | legitimate_indirect_address_p (x, strict) | |
2480 | rtx x; | |
2481 | int strict; | |
2482 | { | |
2483 | return GET_CODE (x) == REG && INT_REG_OK_FOR_BASE_P (x, strict); | |
2484 | } | |
2485 | ||
2486 | static bool | |
2487 | legitimate_lo_sum_address_p (mode, x, strict) | |
2488 | enum machine_mode mode; | |
2489 | rtx x; | |
2490 | int strict; | |
2491 | { | |
2492 | if (GET_CODE (x) != LO_SUM) | |
2493 | return false; | |
2494 | if (GET_CODE (XEXP (x, 0)) != REG) | |
2495 | return false; | |
2496 | if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict)) | |
2497 | return false; | |
2498 | x = XEXP (x, 1); | |
2499 | ||
2500 | if (TARGET_ELF) | |
2501 | { | |
2502 | if (DEFAULT_ABI != ABI_AIX && flag_pic) | |
2503 | return false; | |
2504 | if (TARGET_TOC) | |
2505 | return false; | |
2506 | if (GET_MODE_NUNITS (mode) != 1) | |
2507 | return false; | |
2508 | if (GET_MODE_BITSIZE (mode) > 32 | |
2509 | && !(TARGET_HARD_FLOAT && TARGET_FPRS && mode == DFmode)) | |
2510 | return false; | |
2511 | ||
2512 | return CONSTANT_P (x); | |
2513 | } | |
2514 | ||
2515 | return false; | |
2516 | } | |
2517 | ||
2518 | ||
9ebbca7d GK |
2519 | /* Try machine-dependent ways of modifying an illegitimate address |
2520 | to be legitimate. If we find one, return the new, valid address. | |
2521 | This is used from only one place: `memory_address' in explow.c. | |
2522 | ||
a4f6c312 SS |
2523 | OLDX is the address as it was before break_out_memory_refs was |
2524 | called. In some cases it is useful to look at this to decide what | |
2525 | needs to be done. | |
9ebbca7d | 2526 | |
a4f6c312 | 2527 | MODE is passed so that this function can use GO_IF_LEGITIMATE_ADDRESS. |
9ebbca7d | 2528 | |
a4f6c312 SS |
2529 | It is always safe for this function to do nothing. It exists to |
2530 | recognize opportunities to optimize the output. | |
9ebbca7d GK |
2531 | |
2532 | On RS/6000, first check for the sum of a register with a constant | |
2533 | integer that is out of range. If so, generate code to add the | |
2534 | constant with the low-order 16 bits masked to the register and force | |
2535 | this result into another register (this can be done with `cau'). | |
2536 | Then generate an address of REG+(CONST&0xffff), allowing for the | |
2537 | possibility of bit 16 being a one. | |
2538 | ||
2539 | Then check for the sum of a register and something not constant, try to | |
2540 | load the other things into a register and return the sum. */ | |
4d588c14 | 2541 | |
9ebbca7d GK |
2542 | rtx |
2543 | rs6000_legitimize_address (x, oldx, mode) | |
2544 | rtx x; | |
2545 | rtx oldx ATTRIBUTE_UNUSED; | |
2546 | enum machine_mode mode; | |
0ac081f6 | 2547 | { |
c4501e62 JJ |
2548 | if (GET_CODE (x) == SYMBOL_REF) |
2549 | { | |
2550 | enum tls_model model = SYMBOL_REF_TLS_MODEL (x); | |
2551 | if (model != 0) | |
2552 | return rs6000_legitimize_tls_address (x, model); | |
2553 | } | |
2554 | ||
9ebbca7d GK |
2555 | if (GET_CODE (x) == PLUS |
2556 | && GET_CODE (XEXP (x, 0)) == REG | |
2557 | && GET_CODE (XEXP (x, 1)) == CONST_INT | |
2558 | && (unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 1)) + 0x8000) >= 0x10000) | |
2559 | { | |
2560 | HOST_WIDE_INT high_int, low_int; | |
2561 | rtx sum; | |
a65c591c DE |
2562 | low_int = ((INTVAL (XEXP (x, 1)) & 0xffff) ^ 0x8000) - 0x8000; |
2563 | high_int = INTVAL (XEXP (x, 1)) - low_int; | |
9ebbca7d GK |
2564 | sum = force_operand (gen_rtx_PLUS (Pmode, XEXP (x, 0), |
2565 | GEN_INT (high_int)), 0); | |
2566 | return gen_rtx_PLUS (Pmode, sum, GEN_INT (low_int)); | |
2567 | } | |
2568 | else if (GET_CODE (x) == PLUS | |
2569 | && GET_CODE (XEXP (x, 0)) == REG | |
2570 | && GET_CODE (XEXP (x, 1)) != CONST_INT | |
6ac7bf2c | 2571 | && GET_MODE_NUNITS (mode) == 1 |
a3170dc6 AH |
2572 | && ((TARGET_HARD_FLOAT && TARGET_FPRS) |
2573 | || TARGET_POWERPC64 | |
fcce224d | 2574 | || (mode != DFmode && mode != TFmode)) |
9ebbca7d GK |
2575 | && (TARGET_POWERPC64 || mode != DImode) |
2576 | && mode != TImode) | |
2577 | { | |
2578 | return gen_rtx_PLUS (Pmode, XEXP (x, 0), | |
2579 | force_reg (Pmode, force_operand (XEXP (x, 1), 0))); | |
2580 | } | |
0ac081f6 AH |
2581 | else if (ALTIVEC_VECTOR_MODE (mode)) |
2582 | { | |
2583 | rtx reg; | |
2584 | ||
2585 | /* Make sure both operands are registers. */ | |
2586 | if (GET_CODE (x) == PLUS) | |
9f85ed45 | 2587 | return gen_rtx_PLUS (Pmode, force_reg (Pmode, XEXP (x, 0)), |
0ac081f6 AH |
2588 | force_reg (Pmode, XEXP (x, 1))); |
2589 | ||
2590 | reg = force_reg (Pmode, x); | |
2591 | return reg; | |
2592 | } | |
a3170dc6 AH |
2593 | else if (SPE_VECTOR_MODE (mode)) |
2594 | { | |
2595 | /* We accept [reg + reg] and [reg + OFFSET]. */ | |
2596 | ||
2597 | if (GET_CODE (x) == PLUS) | |
2598 | { | |
2599 | rtx op1 = XEXP (x, 0); | |
2600 | rtx op2 = XEXP (x, 1); | |
2601 | ||
2602 | op1 = force_reg (Pmode, op1); | |
2603 | ||
2604 | if (GET_CODE (op2) != REG | |
2605 | && (GET_CODE (op2) != CONST_INT | |
2606 | || !SPE_CONST_OFFSET_OK (INTVAL (op2)))) | |
2607 | op2 = force_reg (Pmode, op2); | |
2608 | ||
2609 | return gen_rtx_PLUS (Pmode, op1, op2); | |
2610 | } | |
2611 | ||
2612 | return force_reg (Pmode, x); | |
2613 | } | |
f1384257 AM |
2614 | else if (TARGET_ELF |
2615 | && TARGET_32BIT | |
2616 | && TARGET_NO_TOC | |
2617 | && ! flag_pic | |
9ebbca7d GK |
2618 | && GET_CODE (x) != CONST_INT |
2619 | && GET_CODE (x) != CONST_DOUBLE | |
2620 | && CONSTANT_P (x) | |
6ac7bf2c GK |
2621 | && GET_MODE_NUNITS (mode) == 1 |
2622 | && (GET_MODE_BITSIZE (mode) <= 32 | |
a3170dc6 | 2623 | || ((TARGET_HARD_FLOAT && TARGET_FPRS) && mode == DFmode))) |
9ebbca7d GK |
2624 | { |
2625 | rtx reg = gen_reg_rtx (Pmode); | |
2626 | emit_insn (gen_elf_high (reg, (x))); | |
2627 | return gen_rtx_LO_SUM (Pmode, reg, (x)); | |
2628 | } | |
ee890fe2 SS |
2629 | else if (TARGET_MACHO && TARGET_32BIT && TARGET_NO_TOC |
2630 | && ! flag_pic | |
ab82a49f AP |
2631 | #if TARGET_MACHO |
2632 | && ! MACHO_DYNAMIC_NO_PIC_P | |
2633 | #endif | |
ee890fe2 SS |
2634 | && GET_CODE (x) != CONST_INT |
2635 | && GET_CODE (x) != CONST_DOUBLE | |
2636 | && CONSTANT_P (x) | |
a3170dc6 | 2637 | && ((TARGET_HARD_FLOAT && TARGET_FPRS) || mode != DFmode) |
ee890fe2 SS |
2638 | && mode != DImode |
2639 | && mode != TImode) | |
2640 | { | |
2641 | rtx reg = gen_reg_rtx (Pmode); | |
2642 | emit_insn (gen_macho_high (reg, (x))); | |
2643 | return gen_rtx_LO_SUM (Pmode, reg, (x)); | |
2644 | } | |
9ebbca7d | 2645 | else if (TARGET_TOC |
4d588c14 | 2646 | && constant_pool_expr_p (x) |
a9098fd0 | 2647 | && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x), Pmode)) |
9ebbca7d GK |
2648 | { |
2649 | return create_TOC_reference (x); | |
2650 | } | |
2651 | else | |
2652 | return NULL_RTX; | |
2653 | } | |
258bfae2 | 2654 | |
c4501e62 JJ |
2655 | /* Construct the SYMBOL_REF for the tls_get_addr function. */ |
2656 | ||
2657 | static GTY(()) rtx rs6000_tls_symbol; | |
2658 | static rtx | |
2659 | rs6000_tls_get_addr () | |
2660 | { | |
2661 | if (!rs6000_tls_symbol) | |
2662 | rs6000_tls_symbol = init_one_libfunc ("__tls_get_addr"); | |
2663 | ||
2664 | return rs6000_tls_symbol; | |
2665 | } | |
2666 | ||
2667 | /* Construct the SYMBOL_REF for TLS GOT references. */ | |
2668 | ||
2669 | static GTY(()) rtx rs6000_got_symbol; | |
2670 | static rtx | |
2671 | rs6000_got_sym () | |
2672 | { | |
2673 | if (!rs6000_got_symbol) | |
2674 | { | |
2675 | rs6000_got_symbol = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_"); | |
2676 | SYMBOL_REF_FLAGS (rs6000_got_symbol) |= SYMBOL_FLAG_LOCAL; | |
2677 | SYMBOL_REF_FLAGS (rs6000_got_symbol) |= SYMBOL_FLAG_EXTERNAL; | |
2678 | } | |
2679 | ||
2680 | return rs6000_got_symbol; | |
2681 | } | |
2682 | ||
2683 | /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute | |
2684 | this (thread-local) address. */ | |
2685 | ||
2686 | static rtx | |
2687 | rs6000_legitimize_tls_address (addr, model) | |
2688 | rtx addr; | |
2689 | enum tls_model model; | |
2690 | { | |
2691 | rtx dest, insn; | |
2692 | ||
2693 | dest = gen_reg_rtx (Pmode); | |
2694 | if (model == TLS_MODEL_LOCAL_EXEC && rs6000_tls_size == 16) | |
2695 | { | |
2696 | rtx tlsreg; | |
2697 | ||
2698 | if (TARGET_64BIT) | |
2699 | { | |
2700 | tlsreg = gen_rtx_REG (Pmode, 13); | |
2701 | insn = gen_tls_tprel_64 (dest, tlsreg, addr); | |
2702 | } | |
2703 | else | |
2704 | { | |
2705 | tlsreg = gen_rtx_REG (Pmode, 2); | |
2706 | insn = gen_tls_tprel_32 (dest, tlsreg, addr); | |
2707 | } | |
2708 | emit_insn (insn); | |
2709 | } | |
2710 | else if (model == TLS_MODEL_LOCAL_EXEC && rs6000_tls_size == 32) | |
2711 | { | |
2712 | rtx tlsreg, tmp; | |
2713 | ||
2714 | tmp = gen_reg_rtx (Pmode); | |
2715 | if (TARGET_64BIT) | |
2716 | { | |
2717 | tlsreg = gen_rtx_REG (Pmode, 13); | |
2718 | insn = gen_tls_tprel_ha_64 (tmp, tlsreg, addr); | |
2719 | } | |
2720 | else | |
2721 | { | |
2722 | tlsreg = gen_rtx_REG (Pmode, 2); | |
2723 | insn = gen_tls_tprel_ha_32 (tmp, tlsreg, addr); | |
2724 | } | |
2725 | emit_insn (insn); | |
2726 | if (TARGET_64BIT) | |
2727 | insn = gen_tls_tprel_lo_64 (dest, tmp, addr); | |
2728 | else | |
2729 | insn = gen_tls_tprel_lo_32 (dest, tmp, addr); | |
2730 | emit_insn (insn); | |
2731 | } | |
2732 | else | |
2733 | { | |
2734 | rtx r3, got, tga, tmp1, tmp2, eqv; | |
2735 | ||
2736 | if (TARGET_64BIT) | |
2737 | got = gen_rtx_REG (Pmode, TOC_REGISTER); | |
2738 | else | |
2739 | { | |
2740 | if (flag_pic == 1) | |
2741 | got = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM); | |
2742 | else | |
2743 | { | |
2744 | rtx gsym = rs6000_got_sym (); | |
2745 | got = gen_reg_rtx (Pmode); | |
2746 | if (flag_pic == 0) | |
2747 | rs6000_emit_move (got, gsym, Pmode); | |
2748 | else | |
2749 | { | |
2750 | char buf[30]; | |
2751 | static int tls_got_labelno = 0; | |
2752 | rtx tempLR, lab, tmp3, mem; | |
2753 | rtx first, last; | |
2754 | ||
2755 | ASM_GENERATE_INTERNAL_LABEL (buf, "LTLS", tls_got_labelno++); | |
2756 | lab = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); | |
2757 | tempLR = gen_reg_rtx (Pmode); | |
2758 | tmp1 = gen_reg_rtx (Pmode); | |
2759 | tmp2 = gen_reg_rtx (Pmode); | |
2760 | tmp3 = gen_reg_rtx (Pmode); | |
2761 | mem = gen_rtx_MEM (Pmode, tmp1); | |
2762 | RTX_UNCHANGING_P (mem) = 1; | |
2763 | ||
2764 | first = emit_insn (gen_load_toc_v4_PIC_1b (tempLR, lab, | |
2765 | gsym)); | |
2766 | emit_move_insn (tmp1, tempLR); | |
2767 | emit_move_insn (tmp2, mem); | |
2768 | emit_insn (gen_addsi3 (tmp3, tmp1, tmp2)); | |
2769 | last = emit_move_insn (got, tmp3); | |
2770 | REG_NOTES (last) = gen_rtx_EXPR_LIST (REG_EQUAL, gsym, | |
2771 | REG_NOTES (last)); | |
2772 | REG_NOTES (first) = gen_rtx_INSN_LIST (REG_LIBCALL, last, | |
2773 | REG_NOTES (first)); | |
2774 | REG_NOTES (last) = gen_rtx_INSN_LIST (REG_RETVAL, first, | |
2775 | REG_NOTES (last)); | |
2776 | } | |
2777 | } | |
2778 | } | |
2779 | ||
2780 | if (model == TLS_MODEL_GLOBAL_DYNAMIC) | |
2781 | { | |
2782 | r3 = gen_rtx_REG (Pmode, 3); | |
2783 | if (TARGET_64BIT) | |
2784 | insn = gen_tls_gd_64 (r3, got, addr); | |
2785 | else | |
2786 | insn = gen_tls_gd_32 (r3, got, addr); | |
2787 | start_sequence (); | |
2788 | emit_insn (insn); | |
2789 | tga = gen_rtx_MEM (Pmode, rs6000_tls_get_addr ()); | |
2790 | insn = gen_call_value (r3, tga, const0_rtx, const0_rtx); | |
2791 | insn = emit_call_insn (insn); | |
2792 | CONST_OR_PURE_CALL_P (insn) = 1; | |
2793 | use_reg (&CALL_INSN_FUNCTION_USAGE (insn), r3); | |
2794 | insn = get_insns (); | |
2795 | end_sequence (); | |
2796 | emit_libcall_block (insn, dest, r3, addr); | |
2797 | } | |
2798 | else if (model == TLS_MODEL_LOCAL_DYNAMIC) | |
2799 | { | |
2800 | r3 = gen_rtx_REG (Pmode, 3); | |
2801 | if (TARGET_64BIT) | |
2802 | insn = gen_tls_ld_64 (r3, got); | |
2803 | else | |
2804 | insn = gen_tls_ld_32 (r3, got); | |
2805 | start_sequence (); | |
2806 | emit_insn (insn); | |
2807 | tga = gen_rtx_MEM (Pmode, rs6000_tls_get_addr ()); | |
2808 | insn = gen_call_value (r3, tga, const0_rtx, const0_rtx); | |
2809 | insn = emit_call_insn (insn); | |
2810 | CONST_OR_PURE_CALL_P (insn) = 1; | |
2811 | use_reg (&CALL_INSN_FUNCTION_USAGE (insn), r3); | |
2812 | insn = get_insns (); | |
2813 | end_sequence (); | |
2814 | tmp1 = gen_reg_rtx (Pmode); | |
2815 | eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), | |
2816 | UNSPEC_TLSLD); | |
2817 | emit_libcall_block (insn, tmp1, r3, eqv); | |
2818 | if (rs6000_tls_size == 16) | |
2819 | { | |
2820 | if (TARGET_64BIT) | |
2821 | insn = gen_tls_dtprel_64 (dest, tmp1, addr); | |
2822 | else | |
2823 | insn = gen_tls_dtprel_32 (dest, tmp1, addr); | |
2824 | } | |
2825 | else if (rs6000_tls_size == 32) | |
2826 | { | |
2827 | tmp2 = gen_reg_rtx (Pmode); | |
2828 | if (TARGET_64BIT) | |
2829 | insn = gen_tls_dtprel_ha_64 (tmp2, tmp1, addr); | |
2830 | else | |
2831 | insn = gen_tls_dtprel_ha_32 (tmp2, tmp1, addr); | |
2832 | emit_insn (insn); | |
2833 | if (TARGET_64BIT) | |
2834 | insn = gen_tls_dtprel_lo_64 (dest, tmp2, addr); | |
2835 | else | |
2836 | insn = gen_tls_dtprel_lo_32 (dest, tmp2, addr); | |
2837 | } | |
2838 | else | |
2839 | { | |
2840 | tmp2 = gen_reg_rtx (Pmode); | |
2841 | if (TARGET_64BIT) | |
2842 | insn = gen_tls_got_dtprel_64 (tmp2, got, addr); | |
2843 | else | |
2844 | insn = gen_tls_got_dtprel_32 (tmp2, got, addr); | |
2845 | emit_insn (insn); | |
2846 | insn = gen_rtx_SET (Pmode, dest, | |
2847 | gen_rtx_PLUS (Pmode, tmp2, tmp1)); | |
2848 | } | |
2849 | emit_insn (insn); | |
2850 | } | |
2851 | else | |
2852 | { | |
2853 | /* IE, or 64 bit offset LE. */ | |
2854 | tmp2 = gen_reg_rtx (Pmode); | |
2855 | if (TARGET_64BIT) | |
2856 | insn = gen_tls_got_tprel_64 (tmp2, got, addr); | |
2857 | else | |
2858 | insn = gen_tls_got_tprel_32 (tmp2, got, addr); | |
2859 | emit_insn (insn); | |
2860 | if (TARGET_64BIT) | |
2861 | insn = gen_tls_tls_64 (dest, tmp2, addr); | |
2862 | else | |
2863 | insn = gen_tls_tls_32 (dest, tmp2, addr); | |
2864 | emit_insn (insn); | |
2865 | } | |
2866 | } | |
2867 | ||
2868 | return dest; | |
2869 | } | |
2870 | ||
2871 | /* Return 1 if X is a SYMBOL_REF for a TLS symbol. This is used in | |
2872 | instruction definitions. */ | |
2873 | ||
2874 | int | |
2875 | rs6000_tls_symbol_ref (x, mode) | |
2876 | rtx x; | |
2877 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
2878 | { | |
2879 | return RS6000_SYMBOL_REF_TLS_P (x); | |
2880 | } | |
2881 | ||
2882 | /* Return 1 if X contains a thread-local symbol. */ | |
2883 | ||
2884 | bool | |
2885 | rs6000_tls_referenced_p (x) | |
2886 | rtx x; | |
2887 | { | |
2888 | return for_each_rtx (&x, &rs6000_tls_symbol_ref_1, 0); | |
2889 | } | |
2890 | ||
2891 | /* Return 1 if *X is a thread-local symbol. This is the same as | |
2892 | rs6000_tls_symbol_ref except for the type of the unused argument. */ | |
2893 | ||
2894 | static inline int | |
2895 | rs6000_tls_symbol_ref_1 (x, data) | |
2896 | rtx *x; | |
2897 | void *data ATTRIBUTE_UNUSED; | |
2898 | { | |
2899 | return RS6000_SYMBOL_REF_TLS_P (*x); | |
2900 | } | |
2901 | ||
24ea750e DJ |
2902 | /* The convention appears to be to define this wherever it is used. |
2903 | With legitimize_reload_address now defined here, REG_MODE_OK_FOR_BASE_P | |
2904 | is now used here. */ | |
2905 | #ifndef REG_MODE_OK_FOR_BASE_P | |
2906 | #define REG_MODE_OK_FOR_BASE_P(REGNO, MODE) REG_OK_FOR_BASE_P (REGNO) | |
2907 | #endif | |
2908 | ||
2909 | /* Our implementation of LEGITIMIZE_RELOAD_ADDRESS. Returns a value to | |
2910 | replace the input X, or the original X if no replacement is called for. | |
2911 | The output parameter *WIN is 1 if the calling macro should goto WIN, | |
2912 | 0 if it should not. | |
2913 | ||
2914 | For RS/6000, we wish to handle large displacements off a base | |
2915 | register by splitting the addend across an addiu/addis and the mem insn. | |
2916 | This cuts number of extra insns needed from 3 to 1. | |
2917 | ||
2918 | On Darwin, we use this to generate code for floating point constants. | |
2919 | A movsf_low is generated so we wind up with 2 instructions rather than 3. | |
2920 | The Darwin code is inside #if TARGET_MACHO because only then is | |
2921 | machopic_function_base_name() defined. */ | |
2922 | rtx | |
2923 | rs6000_legitimize_reload_address (x, mode, opnum, type, ind_levels, win) | |
2924 | rtx x; | |
2925 | enum machine_mode mode; | |
2926 | int opnum; | |
2927 | int type; | |
2928 | int ind_levels ATTRIBUTE_UNUSED; | |
2929 | int *win; | |
2930 | { | |
2931 | /* We must recognize output that we have already generated ourselves. */ | |
2932 | if (GET_CODE (x) == PLUS | |
2933 | && GET_CODE (XEXP (x, 0)) == PLUS | |
2934 | && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG | |
2935 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT | |
2936 | && GET_CODE (XEXP (x, 1)) == CONST_INT) | |
2937 | { | |
2938 | push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL, | |
2939 | BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0, | |
2940 | opnum, (enum reload_type)type); | |
2941 | *win = 1; | |
2942 | return x; | |
2943 | } | |
3deb2758 | 2944 | |
24ea750e DJ |
2945 | #if TARGET_MACHO |
2946 | if (DEFAULT_ABI == ABI_DARWIN && flag_pic | |
2947 | && GET_CODE (x) == LO_SUM | |
2948 | && GET_CODE (XEXP (x, 0)) == PLUS | |
2949 | && XEXP (XEXP (x, 0), 0) == pic_offset_table_rtx | |
2950 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == HIGH | |
2951 | && GET_CODE (XEXP (XEXP (XEXP (x, 0), 1), 0)) == CONST | |
2952 | && XEXP (XEXP (XEXP (x, 0), 1), 0) == XEXP (x, 1) | |
2953 | && GET_CODE (XEXP (XEXP (x, 1), 0)) == MINUS | |
2954 | && GET_CODE (XEXP (XEXP (XEXP (x, 1), 0), 0)) == SYMBOL_REF | |
2955 | && GET_CODE (XEXP (XEXP (XEXP (x, 1), 0), 1)) == SYMBOL_REF) | |
2956 | { | |
2957 | /* Result of previous invocation of this function on Darwin | |
6f317ef3 | 2958 | floating point constant. */ |
24ea750e DJ |
2959 | push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL, |
2960 | BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, | |
2961 | opnum, (enum reload_type)type); | |
2962 | *win = 1; | |
2963 | return x; | |
2964 | } | |
2965 | #endif | |
2966 | if (GET_CODE (x) == PLUS | |
2967 | && GET_CODE (XEXP (x, 0)) == REG | |
2968 | && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER | |
2969 | && REG_MODE_OK_FOR_BASE_P (XEXP (x, 0), mode) | |
78c875e8 | 2970 | && GET_CODE (XEXP (x, 1)) == CONST_INT |
93638d7a | 2971 | && !SPE_VECTOR_MODE (mode) |
78c875e8 | 2972 | && !ALTIVEC_VECTOR_MODE (mode)) |
24ea750e DJ |
2973 | { |
2974 | HOST_WIDE_INT val = INTVAL (XEXP (x, 1)); | |
2975 | HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000; | |
2976 | HOST_WIDE_INT high | |
2977 | = (((val - low) & 0xffffffff) ^ 0x80000000) - 0x80000000; | |
2978 | ||
2979 | /* Check for 32-bit overflow. */ | |
2980 | if (high + low != val) | |
2981 | { | |
2982 | *win = 0; | |
2983 | return x; | |
2984 | } | |
2985 | ||
2986 | /* Reload the high part into a base reg; leave the low part | |
2987 | in the mem directly. */ | |
2988 | ||
2989 | x = gen_rtx_PLUS (GET_MODE (x), | |
2990 | gen_rtx_PLUS (GET_MODE (x), XEXP (x, 0), | |
2991 | GEN_INT (high)), | |
2992 | GEN_INT (low)); | |
2993 | ||
2994 | push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL, | |
2995 | BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0, | |
2996 | opnum, (enum reload_type)type); | |
2997 | *win = 1; | |
2998 | return x; | |
2999 | } | |
3000 | #if TARGET_MACHO | |
3001 | if (GET_CODE (x) == SYMBOL_REF | |
3002 | && DEFAULT_ABI == ABI_DARWIN | |
69ef87e2 | 3003 | && !ALTIVEC_VECTOR_MODE (mode) |
24ea750e DJ |
3004 | && flag_pic) |
3005 | { | |
3006 | /* Darwin load of floating point constant. */ | |
3007 | rtx offset = gen_rtx (CONST, Pmode, | |
3008 | gen_rtx (MINUS, Pmode, x, | |
3009 | gen_rtx (SYMBOL_REF, Pmode, | |
3010 | machopic_function_base_name ()))); | |
3011 | x = gen_rtx (LO_SUM, GET_MODE (x), | |
3012 | gen_rtx (PLUS, Pmode, pic_offset_table_rtx, | |
3013 | gen_rtx (HIGH, Pmode, offset)), offset); | |
3014 | push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL, | |
3015 | BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, | |
3016 | opnum, (enum reload_type)type); | |
3017 | *win = 1; | |
3018 | return x; | |
3019 | } | |
ab82a49f AP |
3020 | if (GET_CODE (x) == SYMBOL_REF |
3021 | && DEFAULT_ABI == ABI_DARWIN | |
3022 | && !ALTIVEC_VECTOR_MODE (mode) | |
3023 | && MACHO_DYNAMIC_NO_PIC_P) | |
3024 | { | |
3025 | /* Darwin load of floating point constant. */ | |
3026 | x = gen_rtx (LO_SUM, GET_MODE (x), | |
3027 | gen_rtx (HIGH, Pmode, x), x); | |
3028 | push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL, | |
3029 | BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, | |
3030 | opnum, (enum reload_type)type); | |
3031 | *win = 1; | |
3032 | return x; | |
3033 | } | |
24ea750e DJ |
3034 | #endif |
3035 | if (TARGET_TOC | |
4d588c14 | 3036 | && constant_pool_expr_p (x) |
c1f11548 | 3037 | && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x), mode)) |
24ea750e DJ |
3038 | { |
3039 | (x) = create_TOC_reference (x); | |
3040 | *win = 1; | |
3041 | return x; | |
3042 | } | |
3043 | *win = 0; | |
3044 | return x; | |
3045 | } | |
3046 | ||
258bfae2 FS |
3047 | /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression |
3048 | that is a valid memory address for an instruction. | |
3049 | The MODE argument is the machine mode for the MEM expression | |
3050 | that wants to use this address. | |
3051 | ||
3052 | On the RS/6000, there are four valid address: a SYMBOL_REF that | |
3053 | refers to a constant pool entry of an address (or the sum of it | |
3054 | plus a constant), a short (16-bit signed) constant plus a register, | |
3055 | the sum of two registers, or a register indirect, possibly with an | |
5bdc5878 | 3056 | auto-increment. For DFmode and DImode with a constant plus register, |
258bfae2 FS |
3057 | we must ensure that both words are addressable or PowerPC64 with offset |
3058 | word aligned. | |
3059 | ||
3060 | For modes spanning multiple registers (DFmode in 32-bit GPRs, | |
3061 | 32-bit DImode, TImode), indexed addressing cannot be used because | |
3062 | adjacent memory cells are accessed by adding word-sized offsets | |
3063 | during assembly output. */ | |
3064 | int | |
3065 | rs6000_legitimate_address (mode, x, reg_ok_strict) | |
3066 | enum machine_mode mode; | |
3067 | rtx x; | |
3068 | int reg_ok_strict; | |
3069 | { | |
c4501e62 JJ |
3070 | if (RS6000_SYMBOL_REF_TLS_P (x)) |
3071 | return 0; | |
4d588c14 | 3072 | if (legitimate_indirect_address_p (x, reg_ok_strict)) |
258bfae2 FS |
3073 | return 1; |
3074 | if ((GET_CODE (x) == PRE_INC || GET_CODE (x) == PRE_DEC) | |
0d6d6892 | 3075 | && !ALTIVEC_VECTOR_MODE (mode) |
a3170dc6 | 3076 | && !SPE_VECTOR_MODE (mode) |
258bfae2 | 3077 | && TARGET_UPDATE |
4d588c14 | 3078 | && legitimate_indirect_address_p (XEXP (x, 0), reg_ok_strict)) |
258bfae2 | 3079 | return 1; |
4d588c14 | 3080 | if (legitimate_small_data_p (mode, x)) |
258bfae2 | 3081 | return 1; |
4d588c14 | 3082 | if (legitimate_constant_pool_address_p (x)) |
258bfae2 FS |
3083 | return 1; |
3084 | /* If not REG_OK_STRICT (before reload) let pass any stack offset. */ | |
3085 | if (! reg_ok_strict | |
3086 | && GET_CODE (x) == PLUS | |
3087 | && GET_CODE (XEXP (x, 0)) == REG | |
3088 | && XEXP (x, 0) == virtual_stack_vars_rtx | |
3089 | && GET_CODE (XEXP (x, 1)) == CONST_INT) | |
3090 | return 1; | |
4d588c14 | 3091 | if (legitimate_offset_address_p (mode, x, reg_ok_strict)) |
258bfae2 FS |
3092 | return 1; |
3093 | if (mode != TImode | |
a3170dc6 AH |
3094 | && ((TARGET_HARD_FLOAT && TARGET_FPRS) |
3095 | || TARGET_POWERPC64 | |
fcce224d | 3096 | || (mode != DFmode && mode != TFmode)) |
258bfae2 | 3097 | && (TARGET_POWERPC64 || mode != DImode) |
4d588c14 | 3098 | && legitimate_indexed_address_p (x, reg_ok_strict)) |
258bfae2 | 3099 | return 1; |
4d588c14 | 3100 | if (legitimate_lo_sum_address_p (mode, x, reg_ok_strict)) |
258bfae2 FS |
3101 | return 1; |
3102 | return 0; | |
3103 | } | |
4d588c14 RH |
3104 | |
3105 | /* Go to LABEL if ADDR (a legitimate address expression) | |
3106 | has an effect that depends on the machine mode it is used for. | |
3107 | ||
3108 | On the RS/6000 this is true of all integral offsets (since AltiVec | |
3109 | modes don't allow them) or is a pre-increment or decrement. | |
3110 | ||
3111 | ??? Except that due to conceptual problems in offsettable_address_p | |
3112 | we can't really report the problems of integral offsets. So leave | |
3113 | this assuming that the adjustable offset must be valid for the | |
3114 | sub-words of a TFmode operand, which is what we had before. */ | |
3115 | ||
3116 | bool | |
3117 | rs6000_mode_dependent_address (addr) | |
3118 | rtx addr; | |
3119 | { | |
3120 | switch (GET_CODE (addr)) | |
3121 | { | |
3122 | case PLUS: | |
3123 | if (GET_CODE (XEXP (addr, 1)) == CONST_INT) | |
3124 | { | |
3125 | unsigned HOST_WIDE_INT val = INTVAL (XEXP (addr, 1)); | |
3126 | return val + 12 + 0x8000 >= 0x10000; | |
3127 | } | |
3128 | break; | |
3129 | ||
3130 | case LO_SUM: | |
3131 | return true; | |
3132 | ||
3133 | case PRE_INC: | |
3134 | case PRE_DEC: | |
3135 | return TARGET_UPDATE; | |
3136 | ||
3137 | default: | |
3138 | break; | |
3139 | } | |
3140 | ||
3141 | return false; | |
3142 | } | |
fb4d4348 | 3143 | \f |
a4f6c312 SS |
3144 | /* Try to output insns to set TARGET equal to the constant C if it can |
3145 | be done in less than N insns. Do all computations in MODE. | |
3146 | Returns the place where the output has been placed if it can be | |
3147 | done and the insns have been emitted. If it would take more than N | |
3148 | insns, zero is returned and no insns and emitted. */ | |
2bfcf297 DB |
3149 | |
3150 | rtx | |
3151 | rs6000_emit_set_const (dest, mode, source, n) | |
3152 | rtx dest, source; | |
3153 | enum machine_mode mode; | |
3154 | int n ATTRIBUTE_UNUSED; | |
3155 | { | |
af8cb5c5 | 3156 | rtx result, insn, set; |
2bfcf297 DB |
3157 | HOST_WIDE_INT c0, c1; |
3158 | ||
af8cb5c5 | 3159 | if (mode == QImode || mode == HImode) |
2bfcf297 DB |
3160 | { |
3161 | if (dest == NULL) | |
3162 | dest = gen_reg_rtx (mode); | |
3163 | emit_insn (gen_rtx_SET (VOIDmode, dest, source)); | |
3164 | return dest; | |
3165 | } | |
af8cb5c5 | 3166 | else if (mode == SImode) |
2bfcf297 | 3167 | { |
af8cb5c5 DE |
3168 | result = no_new_pseudos ? dest : gen_reg_rtx (SImode); |
3169 | ||
3170 | emit_insn (gen_rtx_SET (VOIDmode, result, | |
3171 | GEN_INT (INTVAL (source) | |
3172 | & (~ (HOST_WIDE_INT) 0xffff)))); | |
3173 | emit_insn (gen_rtx_SET (VOIDmode, dest, | |
3174 | gen_rtx_IOR (SImode, result, | |
3175 | GEN_INT (INTVAL (source) & 0xffff)))); | |
3176 | result = dest; | |
2bfcf297 | 3177 | } |
af8cb5c5 | 3178 | else if (mode == DImode) |
2bfcf297 | 3179 | { |
af8cb5c5 DE |
3180 | if (GET_CODE (source) == CONST_INT) |
3181 | { | |
3182 | c0 = INTVAL (source); | |
3183 | c1 = -(c0 < 0); | |
3184 | } | |
3185 | else if (GET_CODE (source) == CONST_DOUBLE) | |
3186 | { | |
2bfcf297 | 3187 | #if HOST_BITS_PER_WIDE_INT >= 64 |
af8cb5c5 DE |
3188 | c0 = CONST_DOUBLE_LOW (source); |
3189 | c1 = -(c0 < 0); | |
2bfcf297 | 3190 | #else |
af8cb5c5 DE |
3191 | c0 = CONST_DOUBLE_LOW (source); |
3192 | c1 = CONST_DOUBLE_HIGH (source); | |
2bfcf297 | 3193 | #endif |
af8cb5c5 DE |
3194 | } |
3195 | else | |
3196 | abort (); | |
3197 | ||
3198 | result = rs6000_emit_set_long_const (dest, c0, c1); | |
2bfcf297 DB |
3199 | } |
3200 | else | |
a4f6c312 | 3201 | abort (); |
2bfcf297 | 3202 | |
af8cb5c5 DE |
3203 | insn = get_last_insn (); |
3204 | set = single_set (insn); | |
3205 | if (! CONSTANT_P (SET_SRC (set))) | |
3206 | set_unique_reg_note (insn, REG_EQUAL, source); | |
3207 | ||
3208 | return result; | |
2bfcf297 DB |
3209 | } |
3210 | ||
3211 | /* Having failed to find a 3 insn sequence in rs6000_emit_set_const, | |
3212 | fall back to a straight forward decomposition. We do this to avoid | |
3213 | exponential run times encountered when looking for longer sequences | |
3214 | with rs6000_emit_set_const. */ | |
3215 | static rtx | |
3216 | rs6000_emit_set_long_const (dest, c1, c2) | |
3217 | rtx dest; | |
3218 | HOST_WIDE_INT c1, c2; | |
3219 | { | |
3220 | if (!TARGET_POWERPC64) | |
3221 | { | |
3222 | rtx operand1, operand2; | |
3223 | ||
3224 | operand1 = operand_subword_force (dest, WORDS_BIG_ENDIAN == 0, | |
3225 | DImode); | |
3226 | operand2 = operand_subword_force (dest, WORDS_BIG_ENDIAN != 0, | |
3227 | DImode); | |
3228 | emit_move_insn (operand1, GEN_INT (c1)); | |
3229 | emit_move_insn (operand2, GEN_INT (c2)); | |
3230 | } | |
3231 | else | |
3232 | { | |
bc06712d | 3233 | HOST_WIDE_INT ud1, ud2, ud3, ud4; |
252b88f7 | 3234 | |
bc06712d TR |
3235 | ud1 = c1 & 0xffff; |
3236 | ud2 = (c1 & 0xffff0000) >> 16; | |
2bfcf297 | 3237 | #if HOST_BITS_PER_WIDE_INT >= 64 |
bc06712d | 3238 | c2 = c1 >> 32; |
2bfcf297 | 3239 | #endif |
bc06712d TR |
3240 | ud3 = c2 & 0xffff; |
3241 | ud4 = (c2 & 0xffff0000) >> 16; | |
2bfcf297 | 3242 | |
bc06712d TR |
3243 | if ((ud4 == 0xffff && ud3 == 0xffff && ud2 == 0xffff && (ud1 & 0x8000)) |
3244 | || (ud4 == 0 && ud3 == 0 && ud2 == 0 && ! (ud1 & 0x8000))) | |
2bfcf297 | 3245 | { |
bc06712d TR |
3246 | if (ud1 & 0x8000) |
3247 | emit_move_insn (dest, GEN_INT (((ud1 ^ 0x8000) - 0x8000))); | |
3248 | else | |
3249 | emit_move_insn (dest, GEN_INT (ud1)); | |
2bfcf297 | 3250 | } |
2bfcf297 | 3251 | |
bc06712d TR |
3252 | else if ((ud4 == 0xffff && ud3 == 0xffff && (ud2 & 0x8000)) |
3253 | || (ud4 == 0 && ud3 == 0 && ! (ud2 & 0x8000))) | |
252b88f7 | 3254 | { |
bc06712d TR |
3255 | if (ud2 & 0x8000) |
3256 | emit_move_insn (dest, GEN_INT (((ud2 << 16) ^ 0x80000000) | |
3257 | - 0x80000000)); | |
252b88f7 | 3258 | else |
bc06712d TR |
3259 | emit_move_insn (dest, GEN_INT (ud2 << 16)); |
3260 | if (ud1 != 0) | |
3261 | emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud1))); | |
252b88f7 | 3262 | } |
bc06712d TR |
3263 | else if ((ud4 == 0xffff && (ud3 & 0x8000)) |
3264 | || (ud4 == 0 && ! (ud3 & 0x8000))) | |
3265 | { | |
3266 | if (ud3 & 0x8000) | |
3267 | emit_move_insn (dest, GEN_INT (((ud3 << 16) ^ 0x80000000) | |
3268 | - 0x80000000)); | |
3269 | else | |
3270 | emit_move_insn (dest, GEN_INT (ud3 << 16)); | |
3271 | ||
3272 | if (ud2 != 0) | |
3273 | emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud2))); | |
3274 | emit_move_insn (dest, gen_rtx_ASHIFT (DImode, dest, GEN_INT (16))); | |
3275 | if (ud1 != 0) | |
3276 | emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud1))); | |
3277 | } | |
3278 | else | |
3279 | { | |
3280 | if (ud4 & 0x8000) | |
3281 | emit_move_insn (dest, GEN_INT (((ud4 << 16) ^ 0x80000000) | |
3282 | - 0x80000000)); | |
3283 | else | |
3284 | emit_move_insn (dest, GEN_INT (ud4 << 16)); | |
3285 | ||
3286 | if (ud3 != 0) | |
3287 | emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud3))); | |
2bfcf297 | 3288 | |
bc06712d TR |
3289 | emit_move_insn (dest, gen_rtx_ASHIFT (DImode, dest, GEN_INT (32))); |
3290 | if (ud2 != 0) | |
3291 | emit_move_insn (dest, gen_rtx_IOR (DImode, dest, | |
3292 | GEN_INT (ud2 << 16))); | |
3293 | if (ud1 != 0) | |
3294 | emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud1))); | |
3295 | } | |
3296 | } | |
2bfcf297 DB |
3297 | return dest; |
3298 | } | |
3299 | ||
fb4d4348 GK |
3300 | /* Emit a move from SOURCE to DEST in mode MODE. */ |
3301 | void | |
3302 | rs6000_emit_move (dest, source, mode) | |
3303 | rtx dest; | |
3304 | rtx source; | |
3305 | enum machine_mode mode; | |
3306 | { | |
3307 | rtx operands[2]; | |
3308 | operands[0] = dest; | |
3309 | operands[1] = source; | |
3310 | ||
3311 | /* Sanity checks. Check that we get CONST_DOUBLE only when we should. */ | |
3312 | if (GET_CODE (operands[1]) == CONST_DOUBLE | |
3313 | && ! FLOAT_MODE_P (mode) | |
3314 | && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT) | |
3315 | { | |
3316 | /* FIXME. This should never happen. */ | |
3317 | /* Since it seems that it does, do the safe thing and convert | |
3318 | to a CONST_INT. */ | |
2496c7bd | 3319 | operands[1] = gen_int_mode (CONST_DOUBLE_LOW (operands[1]), mode); |
fb4d4348 GK |
3320 | } |
3321 | if (GET_CODE (operands[1]) == CONST_DOUBLE | |
3322 | && ! FLOAT_MODE_P (mode) | |
3323 | && ((CONST_DOUBLE_HIGH (operands[1]) == 0 | |
3324 | && CONST_DOUBLE_LOW (operands[1]) >= 0) | |
3325 | || (CONST_DOUBLE_HIGH (operands[1]) == -1 | |
3326 | && CONST_DOUBLE_LOW (operands[1]) < 0))) | |
3327 | abort (); | |
c9e8cb32 DD |
3328 | |
3329 | /* Check if GCC is setting up a block move that will end up using FP | |
3330 | registers as temporaries. We must make sure this is acceptable. */ | |
3331 | if (GET_CODE (operands[0]) == MEM | |
3332 | && GET_CODE (operands[1]) == MEM | |
3333 | && mode == DImode | |
41543739 GK |
3334 | && (SLOW_UNALIGNED_ACCESS (DImode, MEM_ALIGN (operands[0])) |
3335 | || SLOW_UNALIGNED_ACCESS (DImode, MEM_ALIGN (operands[1]))) | |
3336 | && ! (SLOW_UNALIGNED_ACCESS (SImode, (MEM_ALIGN (operands[0]) > 32 | |
3337 | ? 32 : MEM_ALIGN (operands[0]))) | |
3338 | || SLOW_UNALIGNED_ACCESS (SImode, (MEM_ALIGN (operands[1]) > 32 | |
3339 | ? 32 | |
3340 | : MEM_ALIGN (operands[1])))) | |
3341 | && ! MEM_VOLATILE_P (operands [0]) | |
3342 | && ! MEM_VOLATILE_P (operands [1])) | |
c9e8cb32 | 3343 | { |
41543739 GK |
3344 | emit_move_insn (adjust_address (operands[0], SImode, 0), |
3345 | adjust_address (operands[1], SImode, 0)); | |
3346 | emit_move_insn (adjust_address (operands[0], SImode, 4), | |
3347 | adjust_address (operands[1], SImode, 4)); | |
c9e8cb32 DD |
3348 | return; |
3349 | } | |
fb4d4348 | 3350 | |
67cef334 DE |
3351 | if (!no_new_pseudos) |
3352 | { | |
3353 | if (GET_CODE (operands[1]) == MEM && optimize > 0 | |
3354 | && (mode == QImode || mode == HImode || mode == SImode) | |
3355 | && GET_MODE_SIZE (mode) < GET_MODE_SIZE (word_mode)) | |
3356 | { | |
3357 | rtx reg = gen_reg_rtx (word_mode); | |
3358 | ||
3359 | emit_insn (gen_rtx_SET (word_mode, reg, | |
3360 | gen_rtx_ZERO_EXTEND (word_mode, | |
3361 | operands[1]))); | |
3362 | operands[1] = gen_lowpart (mode, reg); | |
3363 | } | |
3364 | if (GET_CODE (operands[0]) != REG) | |
3365 | operands[1] = force_reg (mode, operands[1]); | |
3366 | } | |
a9098fd0 | 3367 | |
a3170dc6 AH |
3368 | if (mode == SFmode && ! TARGET_POWERPC |
3369 | && TARGET_HARD_FLOAT && TARGET_FPRS | |
ffc14f31 | 3370 | && GET_CODE (operands[0]) == MEM) |
fb4d4348 | 3371 | { |
ffc14f31 GK |
3372 | int regnum; |
3373 | ||
3374 | if (reload_in_progress || reload_completed) | |
3375 | regnum = true_regnum (operands[1]); | |
3376 | else if (GET_CODE (operands[1]) == REG) | |
3377 | regnum = REGNO (operands[1]); | |
3378 | else | |
3379 | regnum = -1; | |
fb4d4348 GK |
3380 | |
3381 | /* If operands[1] is a register, on POWER it may have | |
3382 | double-precision data in it, so truncate it to single | |
3383 | precision. */ | |
3384 | if (FP_REGNO_P (regnum) || regnum >= FIRST_PSEUDO_REGISTER) | |
3385 | { | |
3386 | rtx newreg; | |
3387 | newreg = (no_new_pseudos ? operands[1] : gen_reg_rtx (mode)); | |
3388 | emit_insn (gen_aux_truncdfsf2 (newreg, operands[1])); | |
3389 | operands[1] = newreg; | |
3390 | } | |
3391 | } | |
3392 | ||
c4501e62 JJ |
3393 | /* Recognize the case where operand[1] is a reference to thread-local |
3394 | data and load its address to a register. */ | |
3395 | if (GET_CODE (operands[1]) == SYMBOL_REF) | |
3396 | { | |
3397 | enum tls_model model = SYMBOL_REF_TLS_MODEL (operands[1]); | |
3398 | if (model != 0) | |
3399 | operands[1] = rs6000_legitimize_tls_address (operands[1], model); | |
3400 | } | |
3401 | ||
8f4e6caf RH |
3402 | /* Handle the case where reload calls us with an invalid address. */ |
3403 | if (reload_in_progress && mode == Pmode | |
69ef87e2 | 3404 | && (! general_operand (operands[1], mode) |
8f4e6caf RH |
3405 | || ! nonimmediate_operand (operands[0], mode))) |
3406 | goto emit_set; | |
3407 | ||
3408 | /* Handle the case of CONSTANT_P_RTX. */ | |
3409 | if (GET_CODE (operands[1]) == CONSTANT_P_RTX) | |
3410 | goto emit_set; | |
a9098fd0 | 3411 | |
fb4d4348 GK |
3412 | /* FIXME: In the long term, this switch statement should go away |
3413 | and be replaced by a sequence of tests based on things like | |
3414 | mode == Pmode. */ | |
3415 | switch (mode) | |
3416 | { | |
3417 | case HImode: | |
3418 | case QImode: | |
3419 | if (CONSTANT_P (operands[1]) | |
3420 | && GET_CODE (operands[1]) != CONST_INT) | |
a9098fd0 | 3421 | operands[1] = force_const_mem (mode, operands[1]); |
fb4d4348 GK |
3422 | break; |
3423 | ||
06f4e019 | 3424 | case TFmode: |
fb4d4348 GK |
3425 | case DFmode: |
3426 | case SFmode: | |
3427 | if (CONSTANT_P (operands[1]) | |
3428 | && ! easy_fp_constant (operands[1], mode)) | |
a9098fd0 | 3429 | operands[1] = force_const_mem (mode, operands[1]); |
fb4d4348 GK |
3430 | break; |
3431 | ||
0ac081f6 AH |
3432 | case V16QImode: |
3433 | case V8HImode: | |
3434 | case V4SFmode: | |
3435 | case V4SImode: | |
a3170dc6 AH |
3436 | case V4HImode: |
3437 | case V2SFmode: | |
3438 | case V2SImode: | |
00a892b8 | 3439 | case V1DImode: |
69ef87e2 | 3440 | if (CONSTANT_P (operands[1]) |
d744e06e | 3441 | && !easy_vector_constant (operands[1], mode)) |
0ac081f6 AH |
3442 | operands[1] = force_const_mem (mode, operands[1]); |
3443 | break; | |
3444 | ||
fb4d4348 | 3445 | case SImode: |
a9098fd0 | 3446 | case DImode: |
fb4d4348 GK |
3447 | /* Use default pattern for address of ELF small data */ |
3448 | if (TARGET_ELF | |
a9098fd0 | 3449 | && mode == Pmode |
f607bc57 | 3450 | && DEFAULT_ABI == ABI_V4 |
a9098fd0 GK |
3451 | && (GET_CODE (operands[1]) == SYMBOL_REF |
3452 | || GET_CODE (operands[1]) == CONST) | |
3453 | && small_data_operand (operands[1], mode)) | |
fb4d4348 GK |
3454 | { |
3455 | emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1])); | |
3456 | return; | |
3457 | } | |
3458 | ||
f607bc57 | 3459 | if (DEFAULT_ABI == ABI_V4 |
a9098fd0 GK |
3460 | && mode == Pmode && mode == SImode |
3461 | && flag_pic == 1 && got_operand (operands[1], mode)) | |
fb4d4348 GK |
3462 | { |
3463 | emit_insn (gen_movsi_got (operands[0], operands[1])); | |
3464 | return; | |
3465 | } | |
3466 | ||
ee890fe2 | 3467 | if ((TARGET_ELF || DEFAULT_ABI == ABI_DARWIN) |
f1384257 AM |
3468 | && TARGET_NO_TOC |
3469 | && ! flag_pic | |
a9098fd0 | 3470 | && mode == Pmode |
fb4d4348 GK |
3471 | && CONSTANT_P (operands[1]) |
3472 | && GET_CODE (operands[1]) != HIGH | |
3473 | && GET_CODE (operands[1]) != CONST_INT) | |
3474 | { | |
a9098fd0 | 3475 | rtx target = (no_new_pseudos ? operands[0] : gen_reg_rtx (mode)); |
fb4d4348 GK |
3476 | |
3477 | /* If this is a function address on -mcall-aixdesc, | |
3478 | convert it to the address of the descriptor. */ | |
3479 | if (DEFAULT_ABI == ABI_AIX | |
3480 | && GET_CODE (operands[1]) == SYMBOL_REF | |
3481 | && XSTR (operands[1], 0)[0] == '.') | |
3482 | { | |
3483 | const char *name = XSTR (operands[1], 0); | |
3484 | rtx new_ref; | |
3485 | while (*name == '.') | |
3486 | name++; | |
3487 | new_ref = gen_rtx_SYMBOL_REF (Pmode, name); | |
3488 | CONSTANT_POOL_ADDRESS_P (new_ref) | |
3489 | = CONSTANT_POOL_ADDRESS_P (operands[1]); | |
d1908feb | 3490 | SYMBOL_REF_FLAGS (new_ref) = SYMBOL_REF_FLAGS (operands[1]); |
fb4d4348 | 3491 | SYMBOL_REF_USED (new_ref) = SYMBOL_REF_USED (operands[1]); |
d1908feb | 3492 | SYMBOL_REF_DECL (new_ref) = SYMBOL_REF_DECL (operands[1]); |
fb4d4348 GK |
3493 | operands[1] = new_ref; |
3494 | } | |
7509c759 | 3495 | |
ee890fe2 SS |
3496 | if (DEFAULT_ABI == ABI_DARWIN) |
3497 | { | |
ab82a49f AP |
3498 | #if TARGET_MACHO |
3499 | if (MACHO_DYNAMIC_NO_PIC_P) | |
3500 | { | |
3501 | /* Take care of any required data indirection. */ | |
3502 | operands[1] = rs6000_machopic_legitimize_pic_address ( | |
3503 | operands[1], mode, operands[0]); | |
3504 | if (operands[0] != operands[1]) | |
3505 | emit_insn (gen_rtx_SET (VOIDmode, | |
3506 | operands[0], operands[1])); | |
3507 | return; | |
3508 | } | |
3509 | #endif | |
ee890fe2 SS |
3510 | emit_insn (gen_macho_high (target, operands[1])); |
3511 | emit_insn (gen_macho_low (operands[0], target, operands[1])); | |
3512 | return; | |
3513 | } | |
3514 | ||
fb4d4348 GK |
3515 | emit_insn (gen_elf_high (target, operands[1])); |
3516 | emit_insn (gen_elf_low (operands[0], target, operands[1])); | |
3517 | return; | |
3518 | } | |
3519 | ||
a9098fd0 GK |
3520 | /* If this is a SYMBOL_REF that refers to a constant pool entry, |
3521 | and we have put it in the TOC, we just need to make a TOC-relative | |
3522 | reference to it. */ | |
3523 | if (TARGET_TOC | |
3524 | && GET_CODE (operands[1]) == SYMBOL_REF | |
4d588c14 | 3525 | && constant_pool_expr_p (operands[1]) |
a9098fd0 GK |
3526 | && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (operands[1]), |
3527 | get_pool_mode (operands[1]))) | |
fb4d4348 | 3528 | { |
a9098fd0 | 3529 | operands[1] = create_TOC_reference (operands[1]); |
fb4d4348 | 3530 | } |
a9098fd0 GK |
3531 | else if (mode == Pmode |
3532 | && CONSTANT_P (operands[1]) | |
38886f37 AO |
3533 | && ((GET_CODE (operands[1]) != CONST_INT |
3534 | && ! easy_fp_constant (operands[1], mode)) | |
3535 | || (GET_CODE (operands[1]) == CONST_INT | |
3536 | && num_insns_constant (operands[1], mode) > 2) | |
3537 | || (GET_CODE (operands[0]) == REG | |
3538 | && FP_REGNO_P (REGNO (operands[0])))) | |
a9098fd0 | 3539 | && GET_CODE (operands[1]) != HIGH |
4d588c14 RH |
3540 | && ! legitimate_constant_pool_address_p (operands[1]) |
3541 | && ! toc_relative_expr_p (operands[1])) | |
fb4d4348 GK |
3542 | { |
3543 | /* Emit a USE operation so that the constant isn't deleted if | |
3544 | expensive optimizations are turned on because nobody | |
3545 | references it. This should only be done for operands that | |
3546 | contain SYMBOL_REFs with CONSTANT_POOL_ADDRESS_P set. | |
3547 | This should not be done for operands that contain LABEL_REFs. | |
3548 | For now, we just handle the obvious case. */ | |
3549 | if (GET_CODE (operands[1]) != LABEL_REF) | |
3550 | emit_insn (gen_rtx_USE (VOIDmode, operands[1])); | |
3551 | ||
c859cda6 | 3552 | #if TARGET_MACHO |
ee890fe2 | 3553 | /* Darwin uses a special PIC legitimizer. */ |
ab82a49f | 3554 | if (DEFAULT_ABI == ABI_DARWIN && MACHOPIC_INDIRECT) |
ee890fe2 | 3555 | { |
ee890fe2 SS |
3556 | operands[1] = |
3557 | rs6000_machopic_legitimize_pic_address (operands[1], mode, | |
c859cda6 DJ |
3558 | operands[0]); |
3559 | if (operands[0] != operands[1]) | |
3560 | emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1])); | |
ee890fe2 SS |
3561 | return; |
3562 | } | |
c859cda6 | 3563 | #endif |
ee890fe2 | 3564 | |
fb4d4348 GK |
3565 | /* If we are to limit the number of things we put in the TOC and |
3566 | this is a symbol plus a constant we can add in one insn, | |
3567 | just put the symbol in the TOC and add the constant. Don't do | |
3568 | this if reload is in progress. */ | |
3569 | if (GET_CODE (operands[1]) == CONST | |
3570 | && TARGET_NO_SUM_IN_TOC && ! reload_in_progress | |
3571 | && GET_CODE (XEXP (operands[1], 0)) == PLUS | |
a9098fd0 | 3572 | && add_operand (XEXP (XEXP (operands[1], 0), 1), mode) |
fb4d4348 GK |
3573 | && (GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == LABEL_REF |
3574 | || GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == SYMBOL_REF) | |
3575 | && ! side_effects_p (operands[0])) | |
3576 | { | |
a4f6c312 SS |
3577 | rtx sym = |
3578 | force_const_mem (mode, XEXP (XEXP (operands[1], 0), 0)); | |
fb4d4348 GK |
3579 | rtx other = XEXP (XEXP (operands[1], 0), 1); |
3580 | ||
a9098fd0 GK |
3581 | sym = force_reg (mode, sym); |
3582 | if (mode == SImode) | |
3583 | emit_insn (gen_addsi3 (operands[0], sym, other)); | |
3584 | else | |
3585 | emit_insn (gen_adddi3 (operands[0], sym, other)); | |
fb4d4348 GK |
3586 | return; |
3587 | } | |
3588 | ||
a9098fd0 | 3589 | operands[1] = force_const_mem (mode, operands[1]); |
fb4d4348 GK |
3590 | |
3591 | if (TARGET_TOC | |
4d588c14 | 3592 | && constant_pool_expr_p (XEXP (operands[1], 0)) |
d34c5b80 DE |
3593 | && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P ( |
3594 | get_pool_constant (XEXP (operands[1], 0)), | |
3595 | get_pool_mode (XEXP (operands[1], 0)))) | |
a9098fd0 | 3596 | { |
ba4828e0 RK |
3597 | operands[1] |
3598 | = gen_rtx_MEM (mode, | |
3599 | create_TOC_reference (XEXP (operands[1], 0))); | |
3600 | set_mem_alias_set (operands[1], get_TOC_alias_set ()); | |
fb4d4348 | 3601 | RTX_UNCHANGING_P (operands[1]) = 1; |
a9098fd0 | 3602 | } |
fb4d4348 GK |
3603 | } |
3604 | break; | |
a9098fd0 | 3605 | |
fb4d4348 GK |
3606 | case TImode: |
3607 | if (GET_CODE (operands[0]) == MEM | |
3608 | && GET_CODE (XEXP (operands[0], 0)) != REG | |
3609 | && ! reload_in_progress) | |
792760b9 RK |
3610 | operands[0] |
3611 | = replace_equiv_address (operands[0], | |
3612 | copy_addr_to_reg (XEXP (operands[0], 0))); | |
fb4d4348 GK |
3613 | |
3614 | if (GET_CODE (operands[1]) == MEM | |
3615 | && GET_CODE (XEXP (operands[1], 0)) != REG | |
3616 | && ! reload_in_progress) | |
792760b9 RK |
3617 | operands[1] |
3618 | = replace_equiv_address (operands[1], | |
3619 | copy_addr_to_reg (XEXP (operands[1], 0))); | |
27dc0551 DE |
3620 | if (TARGET_POWER) |
3621 | { | |
3622 | emit_insn (gen_rtx_PARALLEL (VOIDmode, | |
3623 | gen_rtvec (2, | |
3624 | gen_rtx_SET (VOIDmode, | |
3625 | operands[0], operands[1]), | |
3626 | gen_rtx_CLOBBER (VOIDmode, | |
3627 | gen_rtx_SCRATCH (SImode))))); | |
3628 | return; | |
3629 | } | |
fb4d4348 GK |
3630 | break; |
3631 | ||
3632 | default: | |
3633 | abort (); | |
3634 | } | |
3635 | ||
a9098fd0 GK |
3636 | /* Above, we may have called force_const_mem which may have returned |
3637 | an invalid address. If we can, fix this up; otherwise, reload will | |
3638 | have to deal with it. */ | |
8f4e6caf RH |
3639 | if (GET_CODE (operands[1]) == MEM && ! reload_in_progress) |
3640 | operands[1] = validize_mem (operands[1]); | |
a9098fd0 | 3641 | |
8f4e6caf | 3642 | emit_set: |
fb4d4348 GK |
3643 | emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1])); |
3644 | } | |
4697a36c MM |
3645 | \f |
3646 | /* Initialize a variable CUM of type CUMULATIVE_ARGS | |
3647 | for a call to a function whose data type is FNTYPE. | |
3648 | For a library call, FNTYPE is 0. | |
3649 | ||
3650 | For incoming args we set the number of arguments in the prototype large | |
1c20ae99 | 3651 | so we never return a PARALLEL. */ |
4697a36c MM |
3652 | |
3653 | void | |
b9599e46 | 3654 | init_cumulative_args (cum, fntype, libname, incoming, libcall) |
4697a36c MM |
3655 | CUMULATIVE_ARGS *cum; |
3656 | tree fntype; | |
296b8152 | 3657 | rtx libname ATTRIBUTE_UNUSED; |
4697a36c | 3658 | int incoming; |
b9599e46 | 3659 | int libcall; |
4697a36c MM |
3660 | { |
3661 | static CUMULATIVE_ARGS zero_cumulative; | |
3662 | ||
3663 | *cum = zero_cumulative; | |
3664 | cum->words = 0; | |
3665 | cum->fregno = FP_ARG_MIN_REG; | |
0ac081f6 | 3666 | cum->vregno = ALTIVEC_ARG_MIN_REG; |
4697a36c | 3667 | cum->prototype = (fntype && TYPE_ARG_TYPES (fntype)); |
ddcc8263 DE |
3668 | cum->call_cookie = ((DEFAULT_ABI == ABI_V4 && libcall) |
3669 | ? CALL_LIBCALL : CALL_NORMAL); | |
4cc833b7 | 3670 | cum->sysv_gregno = GP_ARG_MIN_REG; |
a6c9bed4 AH |
3671 | cum->stdarg = fntype |
3672 | && (TYPE_ARG_TYPES (fntype) != 0 | |
3673 | && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype))) | |
3674 | != void_type_node)); | |
4697a36c MM |
3675 | |
3676 | if (incoming) | |
bd227acc | 3677 | cum->nargs_prototype = 1000; /* don't return a PARALLEL */ |
4697a36c MM |
3678 | |
3679 | else if (cum->prototype) | |
3680 | cum->nargs_prototype = (list_length (TYPE_ARG_TYPES (fntype)) - 1 | |
3681 | + (TYPE_MODE (TREE_TYPE (fntype)) == BLKmode | |
3682 | || RETURN_IN_MEMORY (TREE_TYPE (fntype)))); | |
3683 | ||
3684 | else | |
3685 | cum->nargs_prototype = 0; | |
3686 | ||
3687 | cum->orig_nargs = cum->nargs_prototype; | |
7509c759 | 3688 | |
a5c76ee6 ZW |
3689 | /* Check for a longcall attribute. */ |
3690 | if (fntype | |
3691 | && lookup_attribute ("longcall", TYPE_ATTRIBUTES (fntype)) | |
3692 | && !lookup_attribute ("shortcall", TYPE_ATTRIBUTES (fntype))) | |
6a4cee5f MM |
3693 | cum->call_cookie = CALL_LONG; |
3694 | ||
4697a36c MM |
3695 | if (TARGET_DEBUG_ARG) |
3696 | { | |
3697 | fprintf (stderr, "\ninit_cumulative_args:"); | |
3698 | if (fntype) | |
3699 | { | |
3700 | tree ret_type = TREE_TYPE (fntype); | |
3701 | fprintf (stderr, " ret code = %s,", | |
3702 | tree_code_name[ (int)TREE_CODE (ret_type) ]); | |
3703 | } | |
3704 | ||
6a4cee5f MM |
3705 | if (cum->call_cookie & CALL_LONG) |
3706 | fprintf (stderr, " longcall,"); | |
3707 | ||
4697a36c MM |
3708 | fprintf (stderr, " proto = %d, nargs = %d\n", |
3709 | cum->prototype, cum->nargs_prototype); | |
3710 | } | |
3711 | } | |
3712 | \f | |
c229cba9 DE |
3713 | /* If defined, a C expression which determines whether, and in which |
3714 | direction, to pad out an argument with extra space. The value | |
3715 | should be of type `enum direction': either `upward' to pad above | |
3716 | the argument, `downward' to pad below, or `none' to inhibit | |
3717 | padding. | |
3718 | ||
3719 | For the AIX ABI structs are always stored left shifted in their | |
3720 | argument slot. */ | |
3721 | ||
9ebbca7d | 3722 | enum direction |
c229cba9 DE |
3723 | function_arg_padding (mode, type) |
3724 | enum machine_mode mode; | |
3725 | tree type; | |
3726 | { | |
c85f7c16 | 3727 | if (type != 0 && AGGREGATE_TYPE_P (type)) |
9ebbca7d | 3728 | return upward; |
c229cba9 DE |
3729 | |
3730 | /* This is the default definition. */ | |
3731 | return (! BYTES_BIG_ENDIAN | |
02ca7595 DE |
3732 | ? upward |
3733 | : ((mode == BLKmode | |
3734 | ? (type && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST | |
3735 | && int_size_in_bytes (type) < (PARM_BOUNDARY / BITS_PER_UNIT)) | |
3736 | : GET_MODE_BITSIZE (mode) < PARM_BOUNDARY) | |
3737 | ? downward : upward)); | |
c229cba9 DE |
3738 | } |
3739 | ||
b6c9286a MM |
3740 | /* If defined, a C expression that gives the alignment boundary, in bits, |
3741 | of an argument with the specified mode and type. If it is not defined, | |
3742 | PARM_BOUNDARY is used for all arguments. | |
3743 | ||
2310f99a | 3744 | V.4 wants long longs to be double word aligned. */ |
b6c9286a MM |
3745 | |
3746 | int | |
3747 | function_arg_boundary (mode, type) | |
3748 | enum machine_mode mode; | |
9ebbca7d | 3749 | tree type ATTRIBUTE_UNUSED; |
b6c9286a | 3750 | { |
f607bc57 | 3751 | if (DEFAULT_ABI == ABI_V4 && (mode == DImode || mode == DFmode)) |
e1f83b4d | 3752 | return 64; |
a3170dc6 AH |
3753 | else if (SPE_VECTOR_MODE (mode)) |
3754 | return 64; | |
0ac081f6 AH |
3755 | else if (TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode)) |
3756 | return 128; | |
9ebbca7d | 3757 | else |
b6c9286a | 3758 | return PARM_BOUNDARY; |
b6c9286a MM |
3759 | } |
3760 | \f | |
4697a36c MM |
3761 | /* Update the data in CUM to advance over an argument |
3762 | of mode MODE and data type TYPE. | |
3763 | (TYPE is null for libcalls where that information may not be available.) */ | |
3764 | ||
3765 | void | |
3766 | function_arg_advance (cum, mode, type, named) | |
3767 | CUMULATIVE_ARGS *cum; | |
3768 | enum machine_mode mode; | |
3769 | tree type; | |
3770 | int named; | |
3771 | { | |
3772 | cum->nargs_prototype--; | |
3773 | ||
0ac081f6 AH |
3774 | if (TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode)) |
3775 | { | |
3776 | if (cum->vregno <= ALTIVEC_ARG_MAX_REG && cum->nargs_prototype >= 0) | |
3777 | cum->vregno++; | |
3778 | else | |
3779 | cum->words += RS6000_ARG_SIZE (mode, type); | |
3780 | } | |
a4b0320c | 3781 | else if (TARGET_SPE_ABI && TARGET_SPE && SPE_VECTOR_MODE (mode) |
a6c9bed4 AH |
3782 | && !cum->stdarg |
3783 | && cum->sysv_gregno <= GP_ARG_MAX_REG) | |
a4b0320c | 3784 | cum->sysv_gregno++; |
f607bc57 | 3785 | else if (DEFAULT_ABI == ABI_V4) |
4697a36c | 3786 | { |
a3170dc6 | 3787 | if (TARGET_HARD_FLOAT && TARGET_FPRS |
4cc833b7 | 3788 | && (mode == SFmode || mode == DFmode)) |
4697a36c | 3789 | { |
4cc833b7 RH |
3790 | if (cum->fregno <= FP_ARG_V4_MAX_REG) |
3791 | cum->fregno++; | |
3792 | else | |
3793 | { | |
3794 | if (mode == DFmode) | |
3795 | cum->words += cum->words & 1; | |
d34c5b80 | 3796 | cum->words += RS6000_ARG_SIZE (mode, type); |
4cc833b7 | 3797 | } |
4697a36c | 3798 | } |
4cc833b7 RH |
3799 | else |
3800 | { | |
3801 | int n_words; | |
3802 | int gregno = cum->sysv_gregno; | |
3803 | ||
3804 | /* Aggregates and IEEE quad get passed by reference. */ | |
3805 | if ((type && AGGREGATE_TYPE_P (type)) | |
3806 | || mode == TFmode) | |
3807 | n_words = 1; | |
3808 | else | |
d34c5b80 | 3809 | n_words = RS6000_ARG_SIZE (mode, type); |
4cc833b7 | 3810 | |
a4b0320c | 3811 | /* Long long and SPE vectors are put in odd registers. */ |
4cc833b7 RH |
3812 | if (n_words == 2 && (gregno & 1) == 0) |
3813 | gregno += 1; | |
3814 | ||
a4b0320c AH |
3815 | /* Long long and SPE vectors are not split between registers |
3816 | and stack. */ | |
4cc833b7 RH |
3817 | if (gregno + n_words - 1 > GP_ARG_MAX_REG) |
3818 | { | |
3819 | /* Long long is aligned on the stack. */ | |
3820 | if (n_words == 2) | |
3821 | cum->words += cum->words & 1; | |
3822 | cum->words += n_words; | |
3823 | } | |
4697a36c | 3824 | |
4cc833b7 RH |
3825 | /* Note: continuing to accumulate gregno past when we've started |
3826 | spilling to the stack indicates the fact that we've started | |
3827 | spilling to the stack to expand_builtin_saveregs. */ | |
3828 | cum->sysv_gregno = gregno + n_words; | |
3829 | } | |
4697a36c | 3830 | |
4cc833b7 RH |
3831 | if (TARGET_DEBUG_ARG) |
3832 | { | |
3833 | fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ", | |
3834 | cum->words, cum->fregno); | |
3835 | fprintf (stderr, "gregno = %2d, nargs = %4d, proto = %d, ", | |
3836 | cum->sysv_gregno, cum->nargs_prototype, cum->prototype); | |
3837 | fprintf (stderr, "mode = %4s, named = %d\n", | |
3838 | GET_MODE_NAME (mode), named); | |
3839 | } | |
4697a36c MM |
3840 | } |
3841 | else | |
4cc833b7 RH |
3842 | { |
3843 | int align = (TARGET_32BIT && (cum->words & 1) != 0 | |
3844 | && function_arg_boundary (mode, type) == 64) ? 1 : 0; | |
a4f6c312 | 3845 | |
d34c5b80 | 3846 | cum->words += align + RS6000_ARG_SIZE (mode, type); |
4697a36c | 3847 | |
a3170dc6 AH |
3848 | if (GET_MODE_CLASS (mode) == MODE_FLOAT |
3849 | && TARGET_HARD_FLOAT && TARGET_FPRS) | |
fcce224d | 3850 | cum->fregno += (mode == TFmode ? 2 : 1); |
4cc833b7 RH |
3851 | |
3852 | if (TARGET_DEBUG_ARG) | |
3853 | { | |
3854 | fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ", | |
3855 | cum->words, cum->fregno); | |
3856 | fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s, ", | |
3857 | cum->nargs_prototype, cum->prototype, GET_MODE_NAME (mode)); | |
3858 | fprintf (stderr, "named = %d, align = %d\n", named, align); | |
3859 | } | |
3860 | } | |
4697a36c | 3861 | } |
a6c9bed4 AH |
3862 | |
3863 | /* Determine where to put a SIMD argument on the SPE. */ | |
3864 | static rtx | |
3865 | rs6000_spe_function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode, tree type) | |
3866 | { | |
3867 | if (cum->stdarg) | |
3868 | { | |
3869 | int gregno = cum->sysv_gregno; | |
3870 | int n_words = RS6000_ARG_SIZE (mode, type); | |
3871 | ||
3872 | /* SPE vectors are put in odd registers. */ | |
3873 | if (n_words == 2 && (gregno & 1) == 0) | |
3874 | gregno += 1; | |
3875 | ||
3876 | if (gregno + n_words - 1 <= GP_ARG_MAX_REG) | |
3877 | { | |
3878 | rtx r1, r2; | |
3879 | enum machine_mode m = SImode; | |
3880 | ||
3881 | r1 = gen_rtx_REG (m, gregno); | |
3882 | r1 = gen_rtx_EXPR_LIST (m, r1, const0_rtx); | |
3883 | r2 = gen_rtx_REG (m, gregno + 1); | |
3884 | r2 = gen_rtx_EXPR_LIST (m, r2, GEN_INT (4)); | |
3885 | return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r2)); | |
3886 | } | |
3887 | else | |
3888 | return NULL; | |
3889 | } | |
3890 | else | |
3891 | { | |
3892 | if (cum->sysv_gregno <= GP_ARG_MAX_REG) | |
3893 | return gen_rtx_REG (mode, cum->sysv_gregno); | |
3894 | else | |
3895 | return NULL; | |
3896 | } | |
3897 | } | |
3898 | ||
4697a36c MM |
3899 | /* Determine where to put an argument to a function. |
3900 | Value is zero to push the argument on the stack, | |
3901 | or a hard register in which to store the argument. | |
3902 | ||
3903 | MODE is the argument's machine mode. | |
3904 | TYPE is the data type of the argument (as a tree). | |
3905 | This is null for libcalls where that information may | |
3906 | not be available. | |
3907 | CUM is a variable of type CUMULATIVE_ARGS which gives info about | |
3908 | the preceding args and about the function being called. | |
3909 | NAMED is nonzero if this argument is a named parameter | |
3910 | (otherwise it is an extra parameter matching an ellipsis). | |
3911 | ||
3912 | On RS/6000 the first eight words of non-FP are normally in registers | |
3913 | and the rest are pushed. Under AIX, the first 13 FP args are in registers. | |
3914 | Under V.4, the first 8 FP args are in registers. | |
3915 | ||
3916 | If this is floating-point and no prototype is specified, we use | |
3917 | both an FP and integer register (or possibly FP reg and stack). Library | |
b9599e46 | 3918 | functions (when CALL_LIBCALL is set) always have the proper types for args, |
4697a36c | 3919 | so we can pass the FP value just in one register. emit_library_function |
1c20ae99 | 3920 | doesn't support PARALLEL anyway. */ |
4697a36c MM |
3921 | |
3922 | struct rtx_def * | |
3923 | function_arg (cum, mode, type, named) | |
3924 | CUMULATIVE_ARGS *cum; | |
3925 | enum machine_mode mode; | |
3926 | tree type; | |
20c29ebe | 3927 | int named; |
4697a36c | 3928 | { |
4cc833b7 | 3929 | enum rs6000_abi abi = DEFAULT_ABI; |
4697a36c | 3930 | |
a4f6c312 SS |
3931 | /* Return a marker to indicate whether CR1 needs to set or clear the |
3932 | bit that V.4 uses to say fp args were passed in registers. | |
3933 | Assume that we don't need the marker for software floating point, | |
3934 | or compiler generated library calls. */ | |
4697a36c MM |
3935 | if (mode == VOIDmode) |
3936 | { | |
f607bc57 | 3937 | if (abi == ABI_V4 |
7509c759 | 3938 | && cum->nargs_prototype < 0 |
b9599e46 FS |
3939 | && (cum->call_cookie & CALL_LIBCALL) == 0 |
3940 | && (cum->prototype || TARGET_NO_PROTOTYPE)) | |
7509c759 | 3941 | { |
a3170dc6 AH |
3942 | /* For the SPE, we need to crxor CR6 always. */ |
3943 | if (TARGET_SPE_ABI) | |
3944 | return GEN_INT (cum->call_cookie | CALL_V4_SET_FP_ARGS); | |
3945 | else if (TARGET_HARD_FLOAT && TARGET_FPRS) | |
3946 | return GEN_INT (cum->call_cookie | |
3947 | | ((cum->fregno == FP_ARG_MIN_REG) | |
3948 | ? CALL_V4_SET_FP_ARGS | |
3949 | : CALL_V4_CLEAR_FP_ARGS)); | |
7509c759 | 3950 | } |
4697a36c | 3951 | |
7509c759 | 3952 | return GEN_INT (cum->call_cookie); |
4697a36c MM |
3953 | } |
3954 | ||
0ac081f6 AH |
3955 | if (TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode)) |
3956 | { | |
20c29ebe | 3957 | if (named && cum->vregno <= ALTIVEC_ARG_MAX_REG) |
0ac081f6 AH |
3958 | return gen_rtx_REG (mode, cum->vregno); |
3959 | else | |
3960 | return NULL; | |
3961 | } | |
a6c9bed4 AH |
3962 | else if (TARGET_SPE_ABI && TARGET_SPE && SPE_VECTOR_MODE (mode)) |
3963 | return rs6000_spe_function_arg (cum, mode, type); | |
f607bc57 | 3964 | else if (abi == ABI_V4) |
4697a36c | 3965 | { |
a3170dc6 | 3966 | if (TARGET_HARD_FLOAT && TARGET_FPRS |
4cc833b7 RH |
3967 | && (mode == SFmode || mode == DFmode)) |
3968 | { | |
3969 | if (cum->fregno <= FP_ARG_V4_MAX_REG) | |
3970 | return gen_rtx_REG (mode, cum->fregno); | |
3971 | else | |
3972 | return NULL; | |
3973 | } | |
3974 | else | |
3975 | { | |
3976 | int n_words; | |
3977 | int gregno = cum->sysv_gregno; | |
3978 | ||
3979 | /* Aggregates and IEEE quad get passed by reference. */ | |
3980 | if ((type && AGGREGATE_TYPE_P (type)) | |
3981 | || mode == TFmode) | |
3982 | n_words = 1; | |
3983 | else | |
d34c5b80 | 3984 | n_words = RS6000_ARG_SIZE (mode, type); |
4cc833b7 | 3985 | |
a4b0320c | 3986 | /* Long long and SPE vectors are put in odd registers. */ |
4cc833b7 RH |
3987 | if (n_words == 2 && (gregno & 1) == 0) |
3988 | gregno += 1; | |
3989 | ||
a6c9bed4 | 3990 | /* Long long do not split between registers and stack. */ |
4cc833b7 | 3991 | if (gregno + n_words - 1 <= GP_ARG_MAX_REG) |
a6c9bed4 | 3992 | return gen_rtx_REG (mode, gregno); |
4cc833b7 RH |
3993 | else |
3994 | return NULL; | |
3995 | } | |
4697a36c | 3996 | } |
4cc833b7 RH |
3997 | else |
3998 | { | |
3999 | int align = (TARGET_32BIT && (cum->words & 1) != 0 | |
4000 | && function_arg_boundary (mode, type) == 64) ? 1 : 0; | |
4001 | int align_words = cum->words + align; | |
4697a36c | 4002 | |
4cc833b7 RH |
4003 | if (type && TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST) |
4004 | return NULL_RTX; | |
4005 | ||
4006 | if (USE_FP_FOR_ARG_P (*cum, mode, type)) | |
4007 | { | |
4008 | if (! type | |
4009 | || ((cum->nargs_prototype > 0) | |
4010 | /* IBM AIX extended its linkage convention definition always | |
4011 | to require FP args after register save area hole on the | |
4012 | stack. */ | |
4013 | && (DEFAULT_ABI != ABI_AIX | |
4014 | || ! TARGET_XL_CALL | |
4015 | || (align_words < GP_ARG_NUM_REG)))) | |
4016 | return gen_rtx_REG (mode, cum->fregno); | |
4017 | ||
4018 | return gen_rtx_PARALLEL (mode, | |
4019 | gen_rtvec (2, | |
39403d82 | 4020 | gen_rtx_EXPR_LIST (VOIDmode, |
1c20ae99 JW |
4021 | ((align_words >= GP_ARG_NUM_REG) |
4022 | ? NULL_RTX | |
4023 | : (align_words | |
d34c5b80 | 4024 | + RS6000_ARG_SIZE (mode, type) |
1c20ae99 JW |
4025 | > GP_ARG_NUM_REG |
4026 | /* If this is partially on the stack, then | |
4027 | we only include the portion actually | |
4028 | in registers here. */ | |
39403d82 | 4029 | ? gen_rtx_REG (SImode, |
1c20ae99 | 4030 | GP_ARG_MIN_REG + align_words) |
39403d82 | 4031 | : gen_rtx_REG (mode, |
1c20ae99 JW |
4032 | GP_ARG_MIN_REG + align_words))), |
4033 | const0_rtx), | |
39403d82 DE |
4034 | gen_rtx_EXPR_LIST (VOIDmode, |
4035 | gen_rtx_REG (mode, cum->fregno), | |
1c20ae99 | 4036 | const0_rtx))); |
4cc833b7 RH |
4037 | } |
4038 | else if (align_words < GP_ARG_NUM_REG) | |
4039 | return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words); | |
4040 | else | |
4041 | return NULL_RTX; | |
4697a36c | 4042 | } |
4697a36c MM |
4043 | } |
4044 | \f | |
4045 | /* For an arg passed partly in registers and partly in memory, | |
4046 | this is the number of registers used. | |
4047 | For args passed entirely in registers or entirely in memory, zero. */ | |
4048 | ||
4049 | int | |
4050 | function_arg_partial_nregs (cum, mode, type, named) | |
4051 | CUMULATIVE_ARGS *cum; | |
4052 | enum machine_mode mode; | |
4053 | tree type; | |
d34c5b80 | 4054 | int named ATTRIBUTE_UNUSED; |
4697a36c | 4055 | { |
f607bc57 | 4056 | if (DEFAULT_ABI == ABI_V4) |
4697a36c | 4057 | return 0; |
4697a36c | 4058 | |
0ac081f6 AH |
4059 | if (USE_FP_FOR_ARG_P (*cum, mode, type) |
4060 | || USE_ALTIVEC_FOR_ARG_P (*cum, mode, type)) | |
4697a36c MM |
4061 | { |
4062 | if (cum->nargs_prototype >= 0) | |
4063 | return 0; | |
4064 | } | |
4065 | ||
4066 | if (cum->words < GP_ARG_NUM_REG | |
d34c5b80 | 4067 | && GP_ARG_NUM_REG < (cum->words + RS6000_ARG_SIZE (mode, type))) |
4697a36c MM |
4068 | { |
4069 | int ret = GP_ARG_NUM_REG - cum->words; | |
4070 | if (ret && TARGET_DEBUG_ARG) | |
4071 | fprintf (stderr, "function_arg_partial_nregs: %d\n", ret); | |
4072 | ||
4073 | return ret; | |
4074 | } | |
4075 | ||
4076 | return 0; | |
4077 | } | |
4078 | \f | |
4079 | /* A C expression that indicates when an argument must be passed by | |
4080 | reference. If nonzero for an argument, a copy of that argument is | |
4081 | made in memory and a pointer to the argument is passed instead of | |
4082 | the argument itself. The pointer is passed in whatever way is | |
4083 | appropriate for passing a pointer to that type. | |
4084 | ||
c8c99a68 DE |
4085 | Under V.4, structures and unions are passed by reference. |
4086 | ||
4087 | As an extension to all ABIs, variable sized types are passed by | |
4088 | reference. */ | |
4697a36c MM |
4089 | |
4090 | int | |
4091 | function_arg_pass_by_reference (cum, mode, type, named) | |
296b8152 KG |
4092 | CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED; |
4093 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
4697a36c | 4094 | tree type; |
296b8152 | 4095 | int named ATTRIBUTE_UNUSED; |
4697a36c | 4096 | { |
f607bc57 | 4097 | if (DEFAULT_ABI == ABI_V4 |
4cc833b7 RH |
4098 | && ((type && AGGREGATE_TYPE_P (type)) |
4099 | || mode == TFmode)) | |
4697a36c MM |
4100 | { |
4101 | if (TARGET_DEBUG_ARG) | |
4102 | fprintf (stderr, "function_arg_pass_by_reference: aggregate\n"); | |
4103 | ||
4104 | return 1; | |
4105 | } | |
c8c99a68 | 4106 | return type && int_size_in_bytes (type) <= 0; |
4697a36c | 4107 | } |
4697a36c MM |
4108 | \f |
4109 | /* Perform any needed actions needed for a function that is receiving a | |
4110 | variable number of arguments. | |
4111 | ||
4112 | CUM is as above. | |
4113 | ||
4114 | MODE and TYPE are the mode and type of the current parameter. | |
4115 | ||
4116 | PRETEND_SIZE is a variable that should be set to the amount of stack | |
4117 | that must be pushed by the prolog to pretend that our caller pushed | |
4118 | it. | |
4119 | ||
4120 | Normally, this macro will push all remaining incoming registers on the | |
4121 | stack and set PRETEND_SIZE to the length of the registers pushed. */ | |
4122 | ||
4123 | void | |
4124 | setup_incoming_varargs (cum, mode, type, pretend_size, no_rtl) | |
4125 | CUMULATIVE_ARGS *cum; | |
4126 | enum machine_mode mode; | |
4127 | tree type; | |
de62b72c | 4128 | int *pretend_size ATTRIBUTE_UNUSED; |
4697a36c MM |
4129 | int no_rtl; |
4130 | ||
4131 | { | |
4cc833b7 RH |
4132 | CUMULATIVE_ARGS next_cum; |
4133 | int reg_size = TARGET_32BIT ? 4 : 8; | |
ca5adc63 | 4134 | rtx save_area = NULL_RTX, mem; |
dfafc897 | 4135 | int first_reg_offset, set; |
d34c5b80 DE |
4136 | tree fntype; |
4137 | int stdarg_p; | |
4697a36c | 4138 | |
d34c5b80 DE |
4139 | fntype = TREE_TYPE (current_function_decl); |
4140 | stdarg_p = (TYPE_ARG_TYPES (fntype) != 0 | |
4141 | && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype))) | |
4142 | != void_type_node)); | |
4cc833b7 | 4143 | |
d34c5b80 DE |
4144 | /* For varargs, we do not want to skip the dummy va_dcl argument. |
4145 | For stdargs, we do want to skip the last named argument. */ | |
4146 | next_cum = *cum; | |
4147 | if (stdarg_p) | |
4148 | function_arg_advance (&next_cum, mode, type, 1); | |
4cc833b7 | 4149 | |
f607bc57 | 4150 | if (DEFAULT_ABI == ABI_V4) |
d34c5b80 | 4151 | { |
4cc833b7 | 4152 | /* Indicate to allocate space on the stack for varargs save area. */ |
00dba523 | 4153 | cfun->machine->sysv_varargs_p = 1; |
60e2d0ca | 4154 | if (! no_rtl) |
2c4974b7 | 4155 | save_area = plus_constant (virtual_stack_vars_rtx, |
bd227acc | 4156 | - RS6000_VARARGS_SIZE); |
4cc833b7 RH |
4157 | |
4158 | first_reg_offset = next_cum.sysv_gregno - GP_ARG_MIN_REG; | |
4697a36c | 4159 | } |
60e2d0ca | 4160 | else |
4697a36c | 4161 | { |
d34c5b80 | 4162 | first_reg_offset = next_cum.words; |
4cc833b7 | 4163 | save_area = virtual_incoming_args_rtx; |
00dba523 | 4164 | cfun->machine->sysv_varargs_p = 0; |
4697a36c MM |
4165 | |
4166 | if (MUST_PASS_IN_STACK (mode, type)) | |
d34c5b80 | 4167 | first_reg_offset += RS6000_ARG_SIZE (TYPE_MODE (type), type); |
4cc833b7 | 4168 | } |
4697a36c | 4169 | |
dfafc897 | 4170 | set = get_varargs_alias_set (); |
c81fc13e | 4171 | if (! no_rtl && first_reg_offset < GP_ARG_NUM_REG) |
4cc833b7 | 4172 | { |
dfafc897 FS |
4173 | mem = gen_rtx_MEM (BLKmode, |
4174 | plus_constant (save_area, | |
4175 | first_reg_offset * reg_size)), | |
ba4828e0 | 4176 | set_mem_alias_set (mem, set); |
8ac61af7 | 4177 | set_mem_align (mem, BITS_PER_WORD); |
dfafc897 | 4178 | |
c6b97fac AM |
4179 | move_block_from_reg (GP_ARG_MIN_REG + first_reg_offset, mem, |
4180 | GP_ARG_NUM_REG - first_reg_offset); | |
4697a36c MM |
4181 | } |
4182 | ||
4697a36c | 4183 | /* Save FP registers if needed. */ |
f607bc57 | 4184 | if (DEFAULT_ABI == ABI_V4 |
a3170dc6 AH |
4185 | && TARGET_HARD_FLOAT && TARGET_FPRS |
4186 | && ! no_rtl | |
4cc833b7 | 4187 | && next_cum.fregno <= FP_ARG_V4_MAX_REG) |
4697a36c | 4188 | { |
4cc833b7 | 4189 | int fregno = next_cum.fregno; |
9ebbca7d | 4190 | rtx cr1 = gen_rtx_REG (CCmode, CR1_REGNO); |
4cc833b7 RH |
4191 | rtx lab = gen_label_rtx (); |
4192 | int off = (GP_ARG_NUM_REG * reg_size) + ((fregno - FP_ARG_MIN_REG) * 8); | |
4697a36c | 4193 | |
4cc833b7 | 4194 | emit_jump_insn (gen_rtx_SET (VOIDmode, |
4697a36c | 4195 | pc_rtx, |
39403d82 | 4196 | gen_rtx_IF_THEN_ELSE (VOIDmode, |
4cc833b7 RH |
4197 | gen_rtx_NE (VOIDmode, cr1, |
4198 | const0_rtx), | |
39403d82 | 4199 | gen_rtx_LABEL_REF (VOIDmode, lab), |
4697a36c MM |
4200 | pc_rtx))); |
4201 | ||
4cc833b7 RH |
4202 | while (fregno <= FP_ARG_V4_MAX_REG) |
4203 | { | |
dfafc897 | 4204 | mem = gen_rtx_MEM (DFmode, plus_constant (save_area, off)); |
ba4828e0 | 4205 | set_mem_alias_set (mem, set); |
dfafc897 | 4206 | emit_move_insn (mem, gen_rtx_REG (DFmode, fregno)); |
4cc833b7 RH |
4207 | fregno++; |
4208 | off += 8; | |
4697a36c | 4209 | } |
4cc833b7 RH |
4210 | |
4211 | emit_label (lab); | |
4697a36c | 4212 | } |
4697a36c | 4213 | } |
4697a36c | 4214 | |
dfafc897 | 4215 | /* Create the va_list data type. */ |
2c4974b7 | 4216 | |
dfafc897 FS |
4217 | tree |
4218 | rs6000_build_va_list () | |
4219 | { | |
64c2816f | 4220 | tree f_gpr, f_fpr, f_res, f_ovf, f_sav, record, type_decl; |
4697a36c | 4221 | |
9ebbca7d GK |
4222 | /* For AIX, prefer 'char *' because that's what the system |
4223 | header files like. */ | |
f607bc57 | 4224 | if (DEFAULT_ABI != ABI_V4) |
9ebbca7d | 4225 | return build_pointer_type (char_type_node); |
dfafc897 | 4226 | |
f1e639b1 | 4227 | record = (*lang_hooks.types.make_type) (RECORD_TYPE); |
bab45a51 | 4228 | type_decl = build_decl (TYPE_DECL, get_identifier ("__va_list_tag"), record); |
0f4fd75d | 4229 | |
9ebbca7d GK |
4230 | f_gpr = build_decl (FIELD_DECL, get_identifier ("gpr"), |
4231 | unsigned_char_type_node); | |
4232 | f_fpr = build_decl (FIELD_DECL, get_identifier ("fpr"), | |
4233 | unsigned_char_type_node); | |
64c2816f DT |
4234 | /* Give the two bytes of padding a name, so that -Wpadded won't warn on |
4235 | every user file. */ | |
4236 | f_res = build_decl (FIELD_DECL, get_identifier ("reserved"), | |
4237 | short_unsigned_type_node); | |
dfafc897 FS |
4238 | f_ovf = build_decl (FIELD_DECL, get_identifier ("overflow_arg_area"), |
4239 | ptr_type_node); | |
4240 | f_sav = build_decl (FIELD_DECL, get_identifier ("reg_save_area"), | |
4241 | ptr_type_node); | |
4242 | ||
4243 | DECL_FIELD_CONTEXT (f_gpr) = record; | |
4244 | DECL_FIELD_CONTEXT (f_fpr) = record; | |
64c2816f | 4245 | DECL_FIELD_CONTEXT (f_res) = record; |
dfafc897 FS |
4246 | DECL_FIELD_CONTEXT (f_ovf) = record; |
4247 | DECL_FIELD_CONTEXT (f_sav) = record; | |
4248 | ||
bab45a51 FS |
4249 | TREE_CHAIN (record) = type_decl; |
4250 | TYPE_NAME (record) = type_decl; | |
dfafc897 FS |
4251 | TYPE_FIELDS (record) = f_gpr; |
4252 | TREE_CHAIN (f_gpr) = f_fpr; | |
64c2816f DT |
4253 | TREE_CHAIN (f_fpr) = f_res; |
4254 | TREE_CHAIN (f_res) = f_ovf; | |
dfafc897 FS |
4255 | TREE_CHAIN (f_ovf) = f_sav; |
4256 | ||
4257 | layout_type (record); | |
4258 | ||
4259 | /* The correct type is an array type of one element. */ | |
4260 | return build_array_type (record, build_index_type (size_zero_node)); | |
4261 | } | |
4262 | ||
4263 | /* Implement va_start. */ | |
4264 | ||
4265 | void | |
e5faf155 | 4266 | rs6000_va_start (valist, nextarg) |
dfafc897 FS |
4267 | tree valist; |
4268 | rtx nextarg; | |
4697a36c | 4269 | { |
dfafc897 | 4270 | HOST_WIDE_INT words, n_gpr, n_fpr; |
c566f9bd | 4271 | tree f_gpr, f_fpr, f_res, f_ovf, f_sav; |
dfafc897 | 4272 | tree gpr, fpr, ovf, sav, t; |
2c4974b7 | 4273 | |
dfafc897 | 4274 | /* Only SVR4 needs something special. */ |
f607bc57 | 4275 | if (DEFAULT_ABI != ABI_V4) |
dfafc897 | 4276 | { |
e5faf155 | 4277 | std_expand_builtin_va_start (valist, nextarg); |
dfafc897 FS |
4278 | return; |
4279 | } | |
4280 | ||
973a648b | 4281 | f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node)); |
dfafc897 | 4282 | f_fpr = TREE_CHAIN (f_gpr); |
c566f9bd DT |
4283 | f_res = TREE_CHAIN (f_fpr); |
4284 | f_ovf = TREE_CHAIN (f_res); | |
dfafc897 FS |
4285 | f_sav = TREE_CHAIN (f_ovf); |
4286 | ||
8ebecc3b | 4287 | valist = build1 (INDIRECT_REF, TREE_TYPE (TREE_TYPE (valist)), valist); |
dfafc897 FS |
4288 | gpr = build (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr); |
4289 | fpr = build (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr); | |
4290 | ovf = build (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf); | |
4291 | sav = build (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav); | |
4292 | ||
4293 | /* Count number of gp and fp argument registers used. */ | |
4cc833b7 | 4294 | words = current_function_args_info.words; |
dfafc897 FS |
4295 | n_gpr = current_function_args_info.sysv_gregno - GP_ARG_MIN_REG; |
4296 | n_fpr = current_function_args_info.fregno - FP_ARG_MIN_REG; | |
4297 | ||
4298 | if (TARGET_DEBUG_ARG) | |
4a0a75dd KG |
4299 | fprintf (stderr, "va_start: words = "HOST_WIDE_INT_PRINT_DEC", n_gpr = " |
4300 | HOST_WIDE_INT_PRINT_DEC", n_fpr = "HOST_WIDE_INT_PRINT_DEC"\n", | |
4301 | words, n_gpr, n_fpr); | |
dfafc897 FS |
4302 | |
4303 | t = build (MODIFY_EXPR, TREE_TYPE (gpr), gpr, build_int_2 (n_gpr, 0)); | |
4304 | TREE_SIDE_EFFECTS (t) = 1; | |
4305 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
4306 | ||
4307 | t = build (MODIFY_EXPR, TREE_TYPE (fpr), fpr, build_int_2 (n_fpr, 0)); | |
4308 | TREE_SIDE_EFFECTS (t) = 1; | |
4309 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
4310 | ||
4311 | /* Find the overflow area. */ | |
4312 | t = make_tree (TREE_TYPE (ovf), virtual_incoming_args_rtx); | |
4313 | if (words != 0) | |
4314 | t = build (PLUS_EXPR, TREE_TYPE (ovf), t, | |
4315 | build_int_2 (words * UNITS_PER_WORD, 0)); | |
4316 | t = build (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t); | |
4317 | TREE_SIDE_EFFECTS (t) = 1; | |
4318 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
4319 | ||
4320 | /* Find the register save area. */ | |
4321 | t = make_tree (TREE_TYPE (sav), virtual_stack_vars_rtx); | |
4322 | t = build (PLUS_EXPR, TREE_TYPE (sav), t, | |
4323 | build_int_2 (-RS6000_VARARGS_SIZE, -1)); | |
4324 | t = build (MODIFY_EXPR, TREE_TYPE (sav), sav, t); | |
4325 | TREE_SIDE_EFFECTS (t) = 1; | |
4326 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
4327 | } | |
4328 | ||
4329 | /* Implement va_arg. */ | |
4330 | ||
4331 | rtx | |
4332 | rs6000_va_arg (valist, type) | |
4333 | tree valist, type; | |
4334 | { | |
c566f9bd | 4335 | tree f_gpr, f_fpr, f_res, f_ovf, f_sav; |
dfafc897 FS |
4336 | tree gpr, fpr, ovf, sav, reg, t, u; |
4337 | int indirect_p, size, rsize, n_reg, sav_ofs, sav_scale; | |
4338 | rtx lab_false, lab_over, addr_rtx, r; | |
4339 | ||
f607bc57 | 4340 | if (DEFAULT_ABI != ABI_V4) |
c8c99a68 DE |
4341 | { |
4342 | /* Variable sized types are passed by reference. */ | |
4343 | if (int_size_in_bytes (type) <= 0) | |
4344 | { | |
4345 | u = build_pointer_type (type); | |
4346 | ||
4347 | /* Args grow upward. */ | |
4348 | t = build (POSTINCREMENT_EXPR, TREE_TYPE (valist), valist, | |
4349 | build_int_2 (POINTER_SIZE / BITS_PER_UNIT, 0)); | |
4350 | TREE_SIDE_EFFECTS (t) = 1; | |
4351 | ||
4352 | t = build1 (NOP_EXPR, build_pointer_type (u), t); | |
4353 | TREE_SIDE_EFFECTS (t) = 1; | |
4354 | ||
4355 | t = build1 (INDIRECT_REF, u, t); | |
4356 | TREE_SIDE_EFFECTS (t) = 1; | |
4357 | ||
4358 | return expand_expr (t, NULL_RTX, VOIDmode, EXPAND_NORMAL); | |
4359 | } | |
4360 | else | |
4361 | return std_expand_builtin_va_arg (valist, type); | |
4362 | } | |
dfafc897 | 4363 | |
973a648b | 4364 | f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node)); |
dfafc897 | 4365 | f_fpr = TREE_CHAIN (f_gpr); |
c566f9bd DT |
4366 | f_res = TREE_CHAIN (f_fpr); |
4367 | f_ovf = TREE_CHAIN (f_res); | |
dfafc897 FS |
4368 | f_sav = TREE_CHAIN (f_ovf); |
4369 | ||
8ebecc3b | 4370 | valist = build1 (INDIRECT_REF, TREE_TYPE (TREE_TYPE (valist)), valist); |
dfafc897 FS |
4371 | gpr = build (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr); |
4372 | fpr = build (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr); | |
4373 | ovf = build (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf); | |
4374 | sav = build (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav); | |
4375 | ||
4376 | size = int_size_in_bytes (type); | |
4377 | rsize = (size + UNITS_PER_WORD - 1) / UNITS_PER_WORD; | |
4cc833b7 | 4378 | |
dfafc897 | 4379 | if (AGGREGATE_TYPE_P (type) || TYPE_MODE (type) == TFmode) |
4cc833b7 | 4380 | { |
dfafc897 FS |
4381 | /* Aggregates and long doubles are passed by reference. */ |
4382 | indirect_p = 1; | |
4383 | reg = gpr; | |
4384 | n_reg = 1; | |
4385 | sav_ofs = 0; | |
4386 | sav_scale = 4; | |
d3294cd9 FS |
4387 | size = UNITS_PER_WORD; |
4388 | rsize = 1; | |
dfafc897 | 4389 | } |
a3170dc6 | 4390 | else if (FLOAT_TYPE_P (type) && TARGET_HARD_FLOAT && TARGET_FPRS) |
dfafc897 FS |
4391 | { |
4392 | /* FP args go in FP registers, if present. */ | |
4393 | indirect_p = 0; | |
4394 | reg = fpr; | |
4395 | n_reg = 1; | |
4396 | sav_ofs = 8*4; | |
4397 | sav_scale = 8; | |
4cc833b7 | 4398 | } |
dfafc897 FS |
4399 | else |
4400 | { | |
4401 | /* Otherwise into GP registers. */ | |
4402 | indirect_p = 0; | |
4403 | reg = gpr; | |
4404 | n_reg = rsize; | |
4405 | sav_ofs = 0; | |
4406 | sav_scale = 4; | |
4407 | } | |
4408 | ||
a4f6c312 | 4409 | /* Pull the value out of the saved registers ... */ |
dfafc897 FS |
4410 | |
4411 | lab_false = gen_label_rtx (); | |
4412 | lab_over = gen_label_rtx (); | |
4413 | addr_rtx = gen_reg_rtx (Pmode); | |
4414 | ||
16861f33 AH |
4415 | /* AltiVec vectors never go in registers. */ |
4416 | if (!TARGET_ALTIVEC || TREE_CODE (type) != VECTOR_TYPE) | |
2c4974b7 | 4417 | { |
41daaf0e AH |
4418 | TREE_THIS_VOLATILE (reg) = 1; |
4419 | emit_cmp_and_jump_insns | |
4420 | (expand_expr (reg, NULL_RTX, QImode, EXPAND_NORMAL), | |
4421 | GEN_INT (8 - n_reg + 1), GE, const1_rtx, QImode, 1, | |
4422 | lab_false); | |
dfafc897 | 4423 | |
41daaf0e AH |
4424 | /* Long long is aligned in the registers. */ |
4425 | if (n_reg > 1) | |
4426 | { | |
4427 | u = build (BIT_AND_EXPR, TREE_TYPE (reg), reg, | |
4428 | build_int_2 (n_reg - 1, 0)); | |
4429 | u = build (PLUS_EXPR, TREE_TYPE (reg), reg, u); | |
4430 | u = build (MODIFY_EXPR, TREE_TYPE (reg), reg, u); | |
4431 | TREE_SIDE_EFFECTS (u) = 1; | |
4432 | expand_expr (u, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
4433 | } | |
2c4974b7 | 4434 | |
41daaf0e AH |
4435 | if (sav_ofs) |
4436 | t = build (PLUS_EXPR, ptr_type_node, sav, build_int_2 (sav_ofs, 0)); | |
4437 | else | |
4438 | t = sav; | |
2c4974b7 | 4439 | |
41daaf0e AH |
4440 | u = build (POSTINCREMENT_EXPR, TREE_TYPE (reg), reg, |
4441 | build_int_2 (n_reg, 0)); | |
4442 | TREE_SIDE_EFFECTS (u) = 1; | |
2c4974b7 | 4443 | |
41daaf0e AH |
4444 | u = build1 (CONVERT_EXPR, integer_type_node, u); |
4445 | TREE_SIDE_EFFECTS (u) = 1; | |
dfafc897 | 4446 | |
41daaf0e AH |
4447 | u = build (MULT_EXPR, integer_type_node, u, build_int_2 (sav_scale, 0)); |
4448 | TREE_SIDE_EFFECTS (u) = 1; | |
dfafc897 | 4449 | |
41daaf0e AH |
4450 | t = build (PLUS_EXPR, ptr_type_node, t, u); |
4451 | TREE_SIDE_EFFECTS (t) = 1; | |
4452 | ||
4453 | r = expand_expr (t, addr_rtx, Pmode, EXPAND_NORMAL); | |
4454 | if (r != addr_rtx) | |
4455 | emit_move_insn (addr_rtx, r); | |
4456 | ||
4457 | emit_jump_insn (gen_jump (lab_over)); | |
4458 | emit_barrier (); | |
4459 | } | |
dfafc897 | 4460 | |
dfafc897 FS |
4461 | emit_label (lab_false); |
4462 | ||
a4f6c312 | 4463 | /* ... otherwise out of the overflow area. */ |
dfafc897 | 4464 | |
41daaf0e AH |
4465 | /* Make sure we don't find reg 7 for the next int arg. |
4466 | ||
4467 | All AltiVec vectors go in the overflow area. So in the AltiVec | |
4468 | case we need to get the vectors from the overflow area, but | |
4469 | remember where the GPRs and FPRs are. */ | |
16861f33 AH |
4470 | if (n_reg > 1 && (TREE_CODE (type) != VECTOR_TYPE |
4471 | || !TARGET_ALTIVEC)) | |
dfafc897 FS |
4472 | { |
4473 | t = build (MODIFY_EXPR, TREE_TYPE (reg), reg, build_int_2 (8, 0)); | |
4474 | TREE_SIDE_EFFECTS (t) = 1; | |
4475 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
4476 | } | |
4477 | ||
4478 | /* Care for on-stack alignment if needed. */ | |
4479 | if (rsize <= 1) | |
4480 | t = ovf; | |
4481 | else | |
4482 | { | |
41daaf0e AH |
4483 | int align; |
4484 | ||
16861f33 AH |
4485 | /* AltiVec vectors are 16 byte aligned. */ |
4486 | if (TARGET_ALTIVEC && TREE_CODE (type) == VECTOR_TYPE) | |
41daaf0e AH |
4487 | align = 15; |
4488 | else | |
4489 | align = 7; | |
4490 | ||
4491 | t = build (PLUS_EXPR, TREE_TYPE (ovf), ovf, build_int_2 (align, 0)); | |
4492 | t = build (BIT_AND_EXPR, TREE_TYPE (t), t, build_int_2 (-align-1, -1)); | |
dfafc897 FS |
4493 | } |
4494 | t = save_expr (t); | |
4495 | ||
4496 | r = expand_expr (t, addr_rtx, Pmode, EXPAND_NORMAL); | |
4497 | if (r != addr_rtx) | |
4498 | emit_move_insn (addr_rtx, r); | |
4499 | ||
4500 | t = build (PLUS_EXPR, TREE_TYPE (t), t, build_int_2 (size, 0)); | |
4501 | t = build (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t); | |
4502 | TREE_SIDE_EFFECTS (t) = 1; | |
4503 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
4504 | ||
4505 | emit_label (lab_over); | |
4506 | ||
4507 | if (indirect_p) | |
4508 | { | |
4509 | r = gen_rtx_MEM (Pmode, addr_rtx); | |
ba4828e0 | 4510 | set_mem_alias_set (r, get_varargs_alias_set ()); |
dfafc897 FS |
4511 | emit_move_insn (addr_rtx, r); |
4512 | } | |
4513 | ||
4514 | return addr_rtx; | |
4697a36c | 4515 | } |
0ac081f6 AH |
4516 | |
4517 | /* Builtins. */ | |
4518 | ||
6a2dd09a RS |
4519 | #define def_builtin(MASK, NAME, TYPE, CODE) \ |
4520 | do { \ | |
4521 | if ((MASK) & target_flags) \ | |
4522 | builtin_function ((NAME), (TYPE), (CODE), BUILT_IN_MD, \ | |
4523 | NULL, NULL_TREE); \ | |
0ac081f6 AH |
4524 | } while (0) |
4525 | ||
24408032 AH |
4526 | /* Simple ternary operations: VECd = foo (VECa, VECb, VECc). */ |
4527 | ||
2212663f | 4528 | static const struct builtin_description bdesc_3arg[] = |
24408032 AH |
4529 | { |
4530 | { MASK_ALTIVEC, CODE_FOR_altivec_vmaddfp, "__builtin_altivec_vmaddfp", ALTIVEC_BUILTIN_VMADDFP }, | |
4531 | { MASK_ALTIVEC, CODE_FOR_altivec_vmhaddshs, "__builtin_altivec_vmhaddshs", ALTIVEC_BUILTIN_VMHADDSHS }, | |
4532 | { MASK_ALTIVEC, CODE_FOR_altivec_vmhraddshs, "__builtin_altivec_vmhraddshs", ALTIVEC_BUILTIN_VMHRADDSHS }, | |
4533 | { MASK_ALTIVEC, CODE_FOR_altivec_vmladduhm, "__builtin_altivec_vmladduhm", ALTIVEC_BUILTIN_VMLADDUHM}, | |
4534 | { MASK_ALTIVEC, CODE_FOR_altivec_vmsumubm, "__builtin_altivec_vmsumubm", ALTIVEC_BUILTIN_VMSUMUBM }, | |
4535 | { MASK_ALTIVEC, CODE_FOR_altivec_vmsummbm, "__builtin_altivec_vmsummbm", ALTIVEC_BUILTIN_VMSUMMBM }, | |
4536 | { MASK_ALTIVEC, CODE_FOR_altivec_vmsumuhm, "__builtin_altivec_vmsumuhm", ALTIVEC_BUILTIN_VMSUMUHM }, | |
4537 | { MASK_ALTIVEC, CODE_FOR_altivec_vmsumshm, "__builtin_altivec_vmsumshm", ALTIVEC_BUILTIN_VMSUMSHM }, | |
4538 | { MASK_ALTIVEC, CODE_FOR_altivec_vmsumuhs, "__builtin_altivec_vmsumuhs", ALTIVEC_BUILTIN_VMSUMUHS }, | |
4539 | { MASK_ALTIVEC, CODE_FOR_altivec_vmsumshs, "__builtin_altivec_vmsumshs", ALTIVEC_BUILTIN_VMSUMSHS }, | |
4540 | { MASK_ALTIVEC, CODE_FOR_altivec_vnmsubfp, "__builtin_altivec_vnmsubfp", ALTIVEC_BUILTIN_VNMSUBFP }, | |
4541 | { MASK_ALTIVEC, CODE_FOR_altivec_vperm_4sf, "__builtin_altivec_vperm_4sf", ALTIVEC_BUILTIN_VPERM_4SF }, | |
4542 | { MASK_ALTIVEC, CODE_FOR_altivec_vperm_4si, "__builtin_altivec_vperm_4si", ALTIVEC_BUILTIN_VPERM_4SI }, | |
4543 | { MASK_ALTIVEC, CODE_FOR_altivec_vperm_8hi, "__builtin_altivec_vperm_8hi", ALTIVEC_BUILTIN_VPERM_8HI }, | |
4544 | { MASK_ALTIVEC, CODE_FOR_altivec_vperm_16qi, "__builtin_altivec_vperm_16qi", ALTIVEC_BUILTIN_VPERM_16QI }, | |
4545 | { MASK_ALTIVEC, CODE_FOR_altivec_vsel_4sf, "__builtin_altivec_vsel_4sf", ALTIVEC_BUILTIN_VSEL_4SF }, | |
4546 | { MASK_ALTIVEC, CODE_FOR_altivec_vsel_4si, "__builtin_altivec_vsel_4si", ALTIVEC_BUILTIN_VSEL_4SI }, | |
4547 | { MASK_ALTIVEC, CODE_FOR_altivec_vsel_8hi, "__builtin_altivec_vsel_8hi", ALTIVEC_BUILTIN_VSEL_8HI }, | |
4548 | { MASK_ALTIVEC, CODE_FOR_altivec_vsel_16qi, "__builtin_altivec_vsel_16qi", ALTIVEC_BUILTIN_VSEL_16QI }, | |
4549 | { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_16qi, "__builtin_altivec_vsldoi_16qi", ALTIVEC_BUILTIN_VSLDOI_16QI }, | |
4550 | { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_8hi, "__builtin_altivec_vsldoi_8hi", ALTIVEC_BUILTIN_VSLDOI_8HI }, | |
4551 | { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_4si, "__builtin_altivec_vsldoi_4si", ALTIVEC_BUILTIN_VSLDOI_4SI }, | |
4552 | { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_4sf, "__builtin_altivec_vsldoi_4sf", ALTIVEC_BUILTIN_VSLDOI_4SF }, | |
4553 | }; | |
2212663f | 4554 | |
95385cbb AH |
4555 | /* DST operations: void foo (void *, const int, const char). */ |
4556 | ||
4557 | static const struct builtin_description bdesc_dst[] = | |
4558 | { | |
4559 | { MASK_ALTIVEC, CODE_FOR_altivec_dst, "__builtin_altivec_dst", ALTIVEC_BUILTIN_DST }, | |
4560 | { MASK_ALTIVEC, CODE_FOR_altivec_dstt, "__builtin_altivec_dstt", ALTIVEC_BUILTIN_DSTT }, | |
4561 | { MASK_ALTIVEC, CODE_FOR_altivec_dstst, "__builtin_altivec_dstst", ALTIVEC_BUILTIN_DSTST }, | |
4562 | { MASK_ALTIVEC, CODE_FOR_altivec_dststt, "__builtin_altivec_dststt", ALTIVEC_BUILTIN_DSTSTT } | |
4563 | }; | |
4564 | ||
2212663f | 4565 | /* Simple binary operations: VECc = foo (VECa, VECb). */ |
24408032 | 4566 | |
a3170dc6 | 4567 | static struct builtin_description bdesc_2arg[] = |
0ac081f6 | 4568 | { |
f18c054f DB |
4569 | { MASK_ALTIVEC, CODE_FOR_addv16qi3, "__builtin_altivec_vaddubm", ALTIVEC_BUILTIN_VADDUBM }, |
4570 | { MASK_ALTIVEC, CODE_FOR_addv8hi3, "__builtin_altivec_vadduhm", ALTIVEC_BUILTIN_VADDUHM }, | |
4571 | { MASK_ALTIVEC, CODE_FOR_addv4si3, "__builtin_altivec_vadduwm", ALTIVEC_BUILTIN_VADDUWM }, | |
4572 | { MASK_ALTIVEC, CODE_FOR_addv4sf3, "__builtin_altivec_vaddfp", ALTIVEC_BUILTIN_VADDFP }, | |
0ac081f6 AH |
4573 | { MASK_ALTIVEC, CODE_FOR_altivec_vaddcuw, "__builtin_altivec_vaddcuw", ALTIVEC_BUILTIN_VADDCUW }, |
4574 | { MASK_ALTIVEC, CODE_FOR_altivec_vaddubs, "__builtin_altivec_vaddubs", ALTIVEC_BUILTIN_VADDUBS }, | |
4575 | { MASK_ALTIVEC, CODE_FOR_altivec_vaddsbs, "__builtin_altivec_vaddsbs", ALTIVEC_BUILTIN_VADDSBS }, | |
4576 | { MASK_ALTIVEC, CODE_FOR_altivec_vadduhs, "__builtin_altivec_vadduhs", ALTIVEC_BUILTIN_VADDUHS }, | |
4577 | { MASK_ALTIVEC, CODE_FOR_altivec_vaddshs, "__builtin_altivec_vaddshs", ALTIVEC_BUILTIN_VADDSHS }, | |
4578 | { MASK_ALTIVEC, CODE_FOR_altivec_vadduws, "__builtin_altivec_vadduws", ALTIVEC_BUILTIN_VADDUWS }, | |
4579 | { MASK_ALTIVEC, CODE_FOR_altivec_vaddsws, "__builtin_altivec_vaddsws", ALTIVEC_BUILTIN_VADDSWS }, | |
f18c054f | 4580 | { MASK_ALTIVEC, CODE_FOR_andv4si3, "__builtin_altivec_vand", ALTIVEC_BUILTIN_VAND }, |
0ac081f6 AH |
4581 | { MASK_ALTIVEC, CODE_FOR_altivec_vandc, "__builtin_altivec_vandc", ALTIVEC_BUILTIN_VANDC }, |
4582 | { MASK_ALTIVEC, CODE_FOR_altivec_vavgub, "__builtin_altivec_vavgub", ALTIVEC_BUILTIN_VAVGUB }, | |
4583 | { MASK_ALTIVEC, CODE_FOR_altivec_vavgsb, "__builtin_altivec_vavgsb", ALTIVEC_BUILTIN_VAVGSB }, | |
4584 | { MASK_ALTIVEC, CODE_FOR_altivec_vavguh, "__builtin_altivec_vavguh", ALTIVEC_BUILTIN_VAVGUH }, | |
4585 | { MASK_ALTIVEC, CODE_FOR_altivec_vavgsh, "__builtin_altivec_vavgsh", ALTIVEC_BUILTIN_VAVGSH }, | |
4586 | { MASK_ALTIVEC, CODE_FOR_altivec_vavguw, "__builtin_altivec_vavguw", ALTIVEC_BUILTIN_VAVGUW }, | |
4587 | { MASK_ALTIVEC, CODE_FOR_altivec_vavgsw, "__builtin_altivec_vavgsw", ALTIVEC_BUILTIN_VAVGSW }, | |
617e0e1d DB |
4588 | { MASK_ALTIVEC, CODE_FOR_altivec_vcfux, "__builtin_altivec_vcfux", ALTIVEC_BUILTIN_VCFUX }, |
4589 | { MASK_ALTIVEC, CODE_FOR_altivec_vcfsx, "__builtin_altivec_vcfsx", ALTIVEC_BUILTIN_VCFSX }, | |
0ac081f6 AH |
4590 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpbfp, "__builtin_altivec_vcmpbfp", ALTIVEC_BUILTIN_VCMPBFP }, |
4591 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequb, "__builtin_altivec_vcmpequb", ALTIVEC_BUILTIN_VCMPEQUB }, | |
4592 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequh, "__builtin_altivec_vcmpequh", ALTIVEC_BUILTIN_VCMPEQUH }, | |
4593 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequw, "__builtin_altivec_vcmpequw", ALTIVEC_BUILTIN_VCMPEQUW }, | |
4594 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpeqfp, "__builtin_altivec_vcmpeqfp", ALTIVEC_BUILTIN_VCMPEQFP }, | |
4595 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgefp, "__builtin_altivec_vcmpgefp", ALTIVEC_BUILTIN_VCMPGEFP }, | |
4596 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtub, "__builtin_altivec_vcmpgtub", ALTIVEC_BUILTIN_VCMPGTUB }, | |
4597 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsb, "__builtin_altivec_vcmpgtsb", ALTIVEC_BUILTIN_VCMPGTSB }, | |
4598 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtuh, "__builtin_altivec_vcmpgtuh", ALTIVEC_BUILTIN_VCMPGTUH }, | |
4599 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsh, "__builtin_altivec_vcmpgtsh", ALTIVEC_BUILTIN_VCMPGTSH }, | |
4600 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtuw, "__builtin_altivec_vcmpgtuw", ALTIVEC_BUILTIN_VCMPGTUW }, | |
4601 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsw, "__builtin_altivec_vcmpgtsw", ALTIVEC_BUILTIN_VCMPGTSW }, | |
4602 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtfp, "__builtin_altivec_vcmpgtfp", ALTIVEC_BUILTIN_VCMPGTFP }, | |
617e0e1d DB |
4603 | { MASK_ALTIVEC, CODE_FOR_altivec_vctsxs, "__builtin_altivec_vctsxs", ALTIVEC_BUILTIN_VCTSXS }, |
4604 | { MASK_ALTIVEC, CODE_FOR_altivec_vctuxs, "__builtin_altivec_vctuxs", ALTIVEC_BUILTIN_VCTUXS }, | |
f18c054f DB |
4605 | { MASK_ALTIVEC, CODE_FOR_umaxv16qi3, "__builtin_altivec_vmaxub", ALTIVEC_BUILTIN_VMAXUB }, |
4606 | { MASK_ALTIVEC, CODE_FOR_smaxv16qi3, "__builtin_altivec_vmaxsb", ALTIVEC_BUILTIN_VMAXSB }, | |
df966bff AH |
4607 | { MASK_ALTIVEC, CODE_FOR_umaxv8hi3, "__builtin_altivec_vmaxuh", ALTIVEC_BUILTIN_VMAXUH }, |
4608 | { MASK_ALTIVEC, CODE_FOR_smaxv8hi3, "__builtin_altivec_vmaxsh", ALTIVEC_BUILTIN_VMAXSH }, | |
4609 | { MASK_ALTIVEC, CODE_FOR_umaxv4si3, "__builtin_altivec_vmaxuw", ALTIVEC_BUILTIN_VMAXUW }, | |
4610 | { MASK_ALTIVEC, CODE_FOR_smaxv4si3, "__builtin_altivec_vmaxsw", ALTIVEC_BUILTIN_VMAXSW }, | |
4611 | { MASK_ALTIVEC, CODE_FOR_smaxv4sf3, "__builtin_altivec_vmaxfp", ALTIVEC_BUILTIN_VMAXFP }, | |
0ac081f6 AH |
4612 | { MASK_ALTIVEC, CODE_FOR_altivec_vmrghb, "__builtin_altivec_vmrghb", ALTIVEC_BUILTIN_VMRGHB }, |
4613 | { MASK_ALTIVEC, CODE_FOR_altivec_vmrghh, "__builtin_altivec_vmrghh", ALTIVEC_BUILTIN_VMRGHH }, | |
4614 | { MASK_ALTIVEC, CODE_FOR_altivec_vmrghw, "__builtin_altivec_vmrghw", ALTIVEC_BUILTIN_VMRGHW }, | |
4615 | { MASK_ALTIVEC, CODE_FOR_altivec_vmrglb, "__builtin_altivec_vmrglb", ALTIVEC_BUILTIN_VMRGLB }, | |
4616 | { MASK_ALTIVEC, CODE_FOR_altivec_vmrglh, "__builtin_altivec_vmrglh", ALTIVEC_BUILTIN_VMRGLH }, | |
4617 | { MASK_ALTIVEC, CODE_FOR_altivec_vmrglw, "__builtin_altivec_vmrglw", ALTIVEC_BUILTIN_VMRGLW }, | |
f18c054f DB |
4618 | { MASK_ALTIVEC, CODE_FOR_uminv16qi3, "__builtin_altivec_vminub", ALTIVEC_BUILTIN_VMINUB }, |
4619 | { MASK_ALTIVEC, CODE_FOR_sminv16qi3, "__builtin_altivec_vminsb", ALTIVEC_BUILTIN_VMINSB }, | |
4620 | { MASK_ALTIVEC, CODE_FOR_uminv8hi3, "__builtin_altivec_vminuh", ALTIVEC_BUILTIN_VMINUH }, | |
4621 | { MASK_ALTIVEC, CODE_FOR_sminv8hi3, "__builtin_altivec_vminsh", ALTIVEC_BUILTIN_VMINSH }, | |
4622 | { MASK_ALTIVEC, CODE_FOR_uminv4si3, "__builtin_altivec_vminuw", ALTIVEC_BUILTIN_VMINUW }, | |
4623 | { MASK_ALTIVEC, CODE_FOR_sminv4si3, "__builtin_altivec_vminsw", ALTIVEC_BUILTIN_VMINSW }, | |
4624 | { MASK_ALTIVEC, CODE_FOR_sminv4sf3, "__builtin_altivec_vminfp", ALTIVEC_BUILTIN_VMINFP }, | |
0ac081f6 AH |
4625 | { MASK_ALTIVEC, CODE_FOR_altivec_vmuleub, "__builtin_altivec_vmuleub", ALTIVEC_BUILTIN_VMULEUB }, |
4626 | { MASK_ALTIVEC, CODE_FOR_altivec_vmulesb, "__builtin_altivec_vmulesb", ALTIVEC_BUILTIN_VMULESB }, | |
4627 | { MASK_ALTIVEC, CODE_FOR_altivec_vmuleuh, "__builtin_altivec_vmuleuh", ALTIVEC_BUILTIN_VMULEUH }, | |
4628 | { MASK_ALTIVEC, CODE_FOR_altivec_vmulesh, "__builtin_altivec_vmulesh", ALTIVEC_BUILTIN_VMULESH }, | |
4629 | { MASK_ALTIVEC, CODE_FOR_altivec_vmuloub, "__builtin_altivec_vmuloub", ALTIVEC_BUILTIN_VMULOUB }, | |
4630 | { MASK_ALTIVEC, CODE_FOR_altivec_vmulosb, "__builtin_altivec_vmulosb", ALTIVEC_BUILTIN_VMULOSB }, | |
4631 | { MASK_ALTIVEC, CODE_FOR_altivec_vmulouh, "__builtin_altivec_vmulouh", ALTIVEC_BUILTIN_VMULOUH }, | |
4632 | { MASK_ALTIVEC, CODE_FOR_altivec_vmulosh, "__builtin_altivec_vmulosh", ALTIVEC_BUILTIN_VMULOSH }, | |
4633 | { MASK_ALTIVEC, CODE_FOR_altivec_vnor, "__builtin_altivec_vnor", ALTIVEC_BUILTIN_VNOR }, | |
f18c054f | 4634 | { MASK_ALTIVEC, CODE_FOR_iorv4si3, "__builtin_altivec_vor", ALTIVEC_BUILTIN_VOR }, |
0ac081f6 AH |
4635 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhum, "__builtin_altivec_vpkuhum", ALTIVEC_BUILTIN_VPKUHUM }, |
4636 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwum, "__builtin_altivec_vpkuwum", ALTIVEC_BUILTIN_VPKUWUM }, | |
4637 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkpx, "__builtin_altivec_vpkpx", ALTIVEC_BUILTIN_VPKPX }, | |
4638 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhss, "__builtin_altivec_vpkuhss", ALTIVEC_BUILTIN_VPKUHSS }, | |
4639 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkshss, "__builtin_altivec_vpkshss", ALTIVEC_BUILTIN_VPKSHSS }, | |
4640 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwss, "__builtin_altivec_vpkuwss", ALTIVEC_BUILTIN_VPKUWSS }, | |
4641 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkswss, "__builtin_altivec_vpkswss", ALTIVEC_BUILTIN_VPKSWSS }, | |
4642 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhus, "__builtin_altivec_vpkuhus", ALTIVEC_BUILTIN_VPKUHUS }, | |
4643 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkshus, "__builtin_altivec_vpkshus", ALTIVEC_BUILTIN_VPKSHUS }, | |
4644 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwus, "__builtin_altivec_vpkuwus", ALTIVEC_BUILTIN_VPKUWUS }, | |
4645 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkswus, "__builtin_altivec_vpkswus", ALTIVEC_BUILTIN_VPKSWUS }, | |
4646 | { MASK_ALTIVEC, CODE_FOR_altivec_vrlb, "__builtin_altivec_vrlb", ALTIVEC_BUILTIN_VRLB }, | |
4647 | { MASK_ALTIVEC, CODE_FOR_altivec_vrlh, "__builtin_altivec_vrlh", ALTIVEC_BUILTIN_VRLH }, | |
4648 | { MASK_ALTIVEC, CODE_FOR_altivec_vrlw, "__builtin_altivec_vrlw", ALTIVEC_BUILTIN_VRLW }, | |
4649 | { MASK_ALTIVEC, CODE_FOR_altivec_vslb, "__builtin_altivec_vslb", ALTIVEC_BUILTIN_VSLB }, | |
4650 | { MASK_ALTIVEC, CODE_FOR_altivec_vslh, "__builtin_altivec_vslh", ALTIVEC_BUILTIN_VSLH }, | |
4651 | { MASK_ALTIVEC, CODE_FOR_altivec_vslw, "__builtin_altivec_vslw", ALTIVEC_BUILTIN_VSLW }, | |
4652 | { MASK_ALTIVEC, CODE_FOR_altivec_vsl, "__builtin_altivec_vsl", ALTIVEC_BUILTIN_VSL }, | |
4653 | { MASK_ALTIVEC, CODE_FOR_altivec_vslo, "__builtin_altivec_vslo", ALTIVEC_BUILTIN_VSLO }, | |
2212663f DB |
4654 | { MASK_ALTIVEC, CODE_FOR_altivec_vspltb, "__builtin_altivec_vspltb", ALTIVEC_BUILTIN_VSPLTB }, |
4655 | { MASK_ALTIVEC, CODE_FOR_altivec_vsplth, "__builtin_altivec_vsplth", ALTIVEC_BUILTIN_VSPLTH }, | |
4656 | { MASK_ALTIVEC, CODE_FOR_altivec_vspltw, "__builtin_altivec_vspltw", ALTIVEC_BUILTIN_VSPLTW }, | |
0ac081f6 | 4657 | { MASK_ALTIVEC, CODE_FOR_altivec_vsrb, "__builtin_altivec_vsrb", ALTIVEC_BUILTIN_VSRB }, |
f18c054f DB |
4658 | { MASK_ALTIVEC, CODE_FOR_altivec_vsrh, "__builtin_altivec_vsrh", ALTIVEC_BUILTIN_VSRH }, |
4659 | { MASK_ALTIVEC, CODE_FOR_altivec_vsrw, "__builtin_altivec_vsrw", ALTIVEC_BUILTIN_VSRW }, | |
0ac081f6 AH |
4660 | { MASK_ALTIVEC, CODE_FOR_altivec_vsrab, "__builtin_altivec_vsrab", ALTIVEC_BUILTIN_VSRAB }, |
4661 | { MASK_ALTIVEC, CODE_FOR_altivec_vsrah, "__builtin_altivec_vsrah", ALTIVEC_BUILTIN_VSRAH }, | |
4662 | { MASK_ALTIVEC, CODE_FOR_altivec_vsraw, "__builtin_altivec_vsraw", ALTIVEC_BUILTIN_VSRAW }, | |
4663 | { MASK_ALTIVEC, CODE_FOR_altivec_vsr, "__builtin_altivec_vsr", ALTIVEC_BUILTIN_VSR }, | |
4664 | { MASK_ALTIVEC, CODE_FOR_altivec_vsro, "__builtin_altivec_vsro", ALTIVEC_BUILTIN_VSRO }, | |
f18c054f DB |
4665 | { MASK_ALTIVEC, CODE_FOR_subv16qi3, "__builtin_altivec_vsububm", ALTIVEC_BUILTIN_VSUBUBM }, |
4666 | { MASK_ALTIVEC, CODE_FOR_subv8hi3, "__builtin_altivec_vsubuhm", ALTIVEC_BUILTIN_VSUBUHM }, | |
4667 | { MASK_ALTIVEC, CODE_FOR_subv4si3, "__builtin_altivec_vsubuwm", ALTIVEC_BUILTIN_VSUBUWM }, | |
4668 | { MASK_ALTIVEC, CODE_FOR_subv4sf3, "__builtin_altivec_vsubfp", ALTIVEC_BUILTIN_VSUBFP }, | |
0ac081f6 AH |
4669 | { MASK_ALTIVEC, CODE_FOR_altivec_vsubcuw, "__builtin_altivec_vsubcuw", ALTIVEC_BUILTIN_VSUBCUW }, |
4670 | { MASK_ALTIVEC, CODE_FOR_altivec_vsububs, "__builtin_altivec_vsububs", ALTIVEC_BUILTIN_VSUBUBS }, | |
4671 | { MASK_ALTIVEC, CODE_FOR_altivec_vsubsbs, "__builtin_altivec_vsubsbs", ALTIVEC_BUILTIN_VSUBSBS }, | |
4672 | { MASK_ALTIVEC, CODE_FOR_altivec_vsubuhs, "__builtin_altivec_vsubuhs", ALTIVEC_BUILTIN_VSUBUHS }, | |
4673 | { MASK_ALTIVEC, CODE_FOR_altivec_vsubshs, "__builtin_altivec_vsubshs", ALTIVEC_BUILTIN_VSUBSHS }, | |
4674 | { MASK_ALTIVEC, CODE_FOR_altivec_vsubuws, "__builtin_altivec_vsubuws", ALTIVEC_BUILTIN_VSUBUWS }, | |
4675 | { MASK_ALTIVEC, CODE_FOR_altivec_vsubsws, "__builtin_altivec_vsubsws", ALTIVEC_BUILTIN_VSUBSWS }, | |
4676 | { MASK_ALTIVEC, CODE_FOR_altivec_vsum4ubs, "__builtin_altivec_vsum4ubs", ALTIVEC_BUILTIN_VSUM4UBS }, | |
4677 | { MASK_ALTIVEC, CODE_FOR_altivec_vsum4sbs, "__builtin_altivec_vsum4sbs", ALTIVEC_BUILTIN_VSUM4SBS }, | |
4678 | { MASK_ALTIVEC, CODE_FOR_altivec_vsum4shs, "__builtin_altivec_vsum4shs", ALTIVEC_BUILTIN_VSUM4SHS }, | |
4679 | { MASK_ALTIVEC, CODE_FOR_altivec_vsum2sws, "__builtin_altivec_vsum2sws", ALTIVEC_BUILTIN_VSUM2SWS }, | |
4680 | { MASK_ALTIVEC, CODE_FOR_altivec_vsumsws, "__builtin_altivec_vsumsws", ALTIVEC_BUILTIN_VSUMSWS }, | |
f18c054f | 4681 | { MASK_ALTIVEC, CODE_FOR_xorv4si3, "__builtin_altivec_vxor", ALTIVEC_BUILTIN_VXOR }, |
a3170dc6 AH |
4682 | |
4683 | /* Place holder, leave as first spe builtin. */ | |
4684 | { 0, CODE_FOR_spe_evaddw, "__builtin_spe_evaddw", SPE_BUILTIN_EVADDW }, | |
4685 | { 0, CODE_FOR_spe_evand, "__builtin_spe_evand", SPE_BUILTIN_EVAND }, | |
4686 | { 0, CODE_FOR_spe_evandc, "__builtin_spe_evandc", SPE_BUILTIN_EVANDC }, | |
4687 | { 0, CODE_FOR_spe_evdivws, "__builtin_spe_evdivws", SPE_BUILTIN_EVDIVWS }, | |
4688 | { 0, CODE_FOR_spe_evdivwu, "__builtin_spe_evdivwu", SPE_BUILTIN_EVDIVWU }, | |
4689 | { 0, CODE_FOR_spe_eveqv, "__builtin_spe_eveqv", SPE_BUILTIN_EVEQV }, | |
4690 | { 0, CODE_FOR_spe_evfsadd, "__builtin_spe_evfsadd", SPE_BUILTIN_EVFSADD }, | |
4691 | { 0, CODE_FOR_spe_evfsdiv, "__builtin_spe_evfsdiv", SPE_BUILTIN_EVFSDIV }, | |
4692 | { 0, CODE_FOR_spe_evfsmul, "__builtin_spe_evfsmul", SPE_BUILTIN_EVFSMUL }, | |
4693 | { 0, CODE_FOR_spe_evfssub, "__builtin_spe_evfssub", SPE_BUILTIN_EVFSSUB }, | |
4694 | { 0, CODE_FOR_spe_evmergehi, "__builtin_spe_evmergehi", SPE_BUILTIN_EVMERGEHI }, | |
4695 | { 0, CODE_FOR_spe_evmergehilo, "__builtin_spe_evmergehilo", SPE_BUILTIN_EVMERGEHILO }, | |
4696 | { 0, CODE_FOR_spe_evmergelo, "__builtin_spe_evmergelo", SPE_BUILTIN_EVMERGELO }, | |
4697 | { 0, CODE_FOR_spe_evmergelohi, "__builtin_spe_evmergelohi", SPE_BUILTIN_EVMERGELOHI }, | |
4698 | { 0, CODE_FOR_spe_evmhegsmfaa, "__builtin_spe_evmhegsmfaa", SPE_BUILTIN_EVMHEGSMFAA }, | |
4699 | { 0, CODE_FOR_spe_evmhegsmfan, "__builtin_spe_evmhegsmfan", SPE_BUILTIN_EVMHEGSMFAN }, | |
4700 | { 0, CODE_FOR_spe_evmhegsmiaa, "__builtin_spe_evmhegsmiaa", SPE_BUILTIN_EVMHEGSMIAA }, | |
4701 | { 0, CODE_FOR_spe_evmhegsmian, "__builtin_spe_evmhegsmian", SPE_BUILTIN_EVMHEGSMIAN }, | |
4702 | { 0, CODE_FOR_spe_evmhegumiaa, "__builtin_spe_evmhegumiaa", SPE_BUILTIN_EVMHEGUMIAA }, | |
4703 | { 0, CODE_FOR_spe_evmhegumian, "__builtin_spe_evmhegumian", SPE_BUILTIN_EVMHEGUMIAN }, | |
4704 | { 0, CODE_FOR_spe_evmhesmf, "__builtin_spe_evmhesmf", SPE_BUILTIN_EVMHESMF }, | |
4705 | { 0, CODE_FOR_spe_evmhesmfa, "__builtin_spe_evmhesmfa", SPE_BUILTIN_EVMHESMFA }, | |
4706 | { 0, CODE_FOR_spe_evmhesmfaaw, "__builtin_spe_evmhesmfaaw", SPE_BUILTIN_EVMHESMFAAW }, | |
4707 | { 0, CODE_FOR_spe_evmhesmfanw, "__builtin_spe_evmhesmfanw", SPE_BUILTIN_EVMHESMFANW }, | |
4708 | { 0, CODE_FOR_spe_evmhesmi, "__builtin_spe_evmhesmi", SPE_BUILTIN_EVMHESMI }, | |
4709 | { 0, CODE_FOR_spe_evmhesmia, "__builtin_spe_evmhesmia", SPE_BUILTIN_EVMHESMIA }, | |
4710 | { 0, CODE_FOR_spe_evmhesmiaaw, "__builtin_spe_evmhesmiaaw", SPE_BUILTIN_EVMHESMIAAW }, | |
4711 | { 0, CODE_FOR_spe_evmhesmianw, "__builtin_spe_evmhesmianw", SPE_BUILTIN_EVMHESMIANW }, | |
4712 | { 0, CODE_FOR_spe_evmhessf, "__builtin_spe_evmhessf", SPE_BUILTIN_EVMHESSF }, | |
4713 | { 0, CODE_FOR_spe_evmhessfa, "__builtin_spe_evmhessfa", SPE_BUILTIN_EVMHESSFA }, | |
4714 | { 0, CODE_FOR_spe_evmhessfaaw, "__builtin_spe_evmhessfaaw", SPE_BUILTIN_EVMHESSFAAW }, | |
4715 | { 0, CODE_FOR_spe_evmhessfanw, "__builtin_spe_evmhessfanw", SPE_BUILTIN_EVMHESSFANW }, | |
4716 | { 0, CODE_FOR_spe_evmhessiaaw, "__builtin_spe_evmhessiaaw", SPE_BUILTIN_EVMHESSIAAW }, | |
4717 | { 0, CODE_FOR_spe_evmhessianw, "__builtin_spe_evmhessianw", SPE_BUILTIN_EVMHESSIANW }, | |
4718 | { 0, CODE_FOR_spe_evmheumi, "__builtin_spe_evmheumi", SPE_BUILTIN_EVMHEUMI }, | |
4719 | { 0, CODE_FOR_spe_evmheumia, "__builtin_spe_evmheumia", SPE_BUILTIN_EVMHEUMIA }, | |
4720 | { 0, CODE_FOR_spe_evmheumiaaw, "__builtin_spe_evmheumiaaw", SPE_BUILTIN_EVMHEUMIAAW }, | |
4721 | { 0, CODE_FOR_spe_evmheumianw, "__builtin_spe_evmheumianw", SPE_BUILTIN_EVMHEUMIANW }, | |
4722 | { 0, CODE_FOR_spe_evmheusiaaw, "__builtin_spe_evmheusiaaw", SPE_BUILTIN_EVMHEUSIAAW }, | |
4723 | { 0, CODE_FOR_spe_evmheusianw, "__builtin_spe_evmheusianw", SPE_BUILTIN_EVMHEUSIANW }, | |
4724 | { 0, CODE_FOR_spe_evmhogsmfaa, "__builtin_spe_evmhogsmfaa", SPE_BUILTIN_EVMHOGSMFAA }, | |
4725 | { 0, CODE_FOR_spe_evmhogsmfan, "__builtin_spe_evmhogsmfan", SPE_BUILTIN_EVMHOGSMFAN }, | |
4726 | { 0, CODE_FOR_spe_evmhogsmiaa, "__builtin_spe_evmhogsmiaa", SPE_BUILTIN_EVMHOGSMIAA }, | |
4727 | { 0, CODE_FOR_spe_evmhogsmian, "__builtin_spe_evmhogsmian", SPE_BUILTIN_EVMHOGSMIAN }, | |
4728 | { 0, CODE_FOR_spe_evmhogumiaa, "__builtin_spe_evmhogumiaa", SPE_BUILTIN_EVMHOGUMIAA }, | |
4729 | { 0, CODE_FOR_spe_evmhogumian, "__builtin_spe_evmhogumian", SPE_BUILTIN_EVMHOGUMIAN }, | |
4730 | { 0, CODE_FOR_spe_evmhosmf, "__builtin_spe_evmhosmf", SPE_BUILTIN_EVMHOSMF }, | |
4731 | { 0, CODE_FOR_spe_evmhosmfa, "__builtin_spe_evmhosmfa", SPE_BUILTIN_EVMHOSMFA }, | |
4732 | { 0, CODE_FOR_spe_evmhosmfaaw, "__builtin_spe_evmhosmfaaw", SPE_BUILTIN_EVMHOSMFAAW }, | |
4733 | { 0, CODE_FOR_spe_evmhosmfanw, "__builtin_spe_evmhosmfanw", SPE_BUILTIN_EVMHOSMFANW }, | |
4734 | { 0, CODE_FOR_spe_evmhosmi, "__builtin_spe_evmhosmi", SPE_BUILTIN_EVMHOSMI }, | |
4735 | { 0, CODE_FOR_spe_evmhosmia, "__builtin_spe_evmhosmia", SPE_BUILTIN_EVMHOSMIA }, | |
4736 | { 0, CODE_FOR_spe_evmhosmiaaw, "__builtin_spe_evmhosmiaaw", SPE_BUILTIN_EVMHOSMIAAW }, | |
4737 | { 0, CODE_FOR_spe_evmhosmianw, "__builtin_spe_evmhosmianw", SPE_BUILTIN_EVMHOSMIANW }, | |
4738 | { 0, CODE_FOR_spe_evmhossf, "__builtin_spe_evmhossf", SPE_BUILTIN_EVMHOSSF }, | |
4739 | { 0, CODE_FOR_spe_evmhossfa, "__builtin_spe_evmhossfa", SPE_BUILTIN_EVMHOSSFA }, | |
4740 | { 0, CODE_FOR_spe_evmhossfaaw, "__builtin_spe_evmhossfaaw", SPE_BUILTIN_EVMHOSSFAAW }, | |
4741 | { 0, CODE_FOR_spe_evmhossfanw, "__builtin_spe_evmhossfanw", SPE_BUILTIN_EVMHOSSFANW }, | |
4742 | { 0, CODE_FOR_spe_evmhossiaaw, "__builtin_spe_evmhossiaaw", SPE_BUILTIN_EVMHOSSIAAW }, | |
4743 | { 0, CODE_FOR_spe_evmhossianw, "__builtin_spe_evmhossianw", SPE_BUILTIN_EVMHOSSIANW }, | |
4744 | { 0, CODE_FOR_spe_evmhoumi, "__builtin_spe_evmhoumi", SPE_BUILTIN_EVMHOUMI }, | |
4745 | { 0, CODE_FOR_spe_evmhoumia, "__builtin_spe_evmhoumia", SPE_BUILTIN_EVMHOUMIA }, | |
4746 | { 0, CODE_FOR_spe_evmhoumiaaw, "__builtin_spe_evmhoumiaaw", SPE_BUILTIN_EVMHOUMIAAW }, | |
4747 | { 0, CODE_FOR_spe_evmhoumianw, "__builtin_spe_evmhoumianw", SPE_BUILTIN_EVMHOUMIANW }, | |
4748 | { 0, CODE_FOR_spe_evmhousiaaw, "__builtin_spe_evmhousiaaw", SPE_BUILTIN_EVMHOUSIAAW }, | |
4749 | { 0, CODE_FOR_spe_evmhousianw, "__builtin_spe_evmhousianw", SPE_BUILTIN_EVMHOUSIANW }, | |
4750 | { 0, CODE_FOR_spe_evmwhsmf, "__builtin_spe_evmwhsmf", SPE_BUILTIN_EVMWHSMF }, | |
4751 | { 0, CODE_FOR_spe_evmwhsmfa, "__builtin_spe_evmwhsmfa", SPE_BUILTIN_EVMWHSMFA }, | |
4752 | { 0, CODE_FOR_spe_evmwhsmi, "__builtin_spe_evmwhsmi", SPE_BUILTIN_EVMWHSMI }, | |
4753 | { 0, CODE_FOR_spe_evmwhsmia, "__builtin_spe_evmwhsmia", SPE_BUILTIN_EVMWHSMIA }, | |
4754 | { 0, CODE_FOR_spe_evmwhssf, "__builtin_spe_evmwhssf", SPE_BUILTIN_EVMWHSSF }, | |
4755 | { 0, CODE_FOR_spe_evmwhssfa, "__builtin_spe_evmwhssfa", SPE_BUILTIN_EVMWHSSFA }, | |
4756 | { 0, CODE_FOR_spe_evmwhumi, "__builtin_spe_evmwhumi", SPE_BUILTIN_EVMWHUMI }, | |
4757 | { 0, CODE_FOR_spe_evmwhumia, "__builtin_spe_evmwhumia", SPE_BUILTIN_EVMWHUMIA }, | |
a3170dc6 AH |
4758 | { 0, CODE_FOR_spe_evmwlsmiaaw, "__builtin_spe_evmwlsmiaaw", SPE_BUILTIN_EVMWLSMIAAW }, |
4759 | { 0, CODE_FOR_spe_evmwlsmianw, "__builtin_spe_evmwlsmianw", SPE_BUILTIN_EVMWLSMIANW }, | |
a3170dc6 AH |
4760 | { 0, CODE_FOR_spe_evmwlssiaaw, "__builtin_spe_evmwlssiaaw", SPE_BUILTIN_EVMWLSSIAAW }, |
4761 | { 0, CODE_FOR_spe_evmwlssianw, "__builtin_spe_evmwlssianw", SPE_BUILTIN_EVMWLSSIANW }, | |
4762 | { 0, CODE_FOR_spe_evmwlumi, "__builtin_spe_evmwlumi", SPE_BUILTIN_EVMWLUMI }, | |
4763 | { 0, CODE_FOR_spe_evmwlumia, "__builtin_spe_evmwlumia", SPE_BUILTIN_EVMWLUMIA }, | |
4764 | { 0, CODE_FOR_spe_evmwlumiaaw, "__builtin_spe_evmwlumiaaw", SPE_BUILTIN_EVMWLUMIAAW }, | |
4765 | { 0, CODE_FOR_spe_evmwlumianw, "__builtin_spe_evmwlumianw", SPE_BUILTIN_EVMWLUMIANW }, | |
4766 | { 0, CODE_FOR_spe_evmwlusiaaw, "__builtin_spe_evmwlusiaaw", SPE_BUILTIN_EVMWLUSIAAW }, | |
4767 | { 0, CODE_FOR_spe_evmwlusianw, "__builtin_spe_evmwlusianw", SPE_BUILTIN_EVMWLUSIANW }, | |
4768 | { 0, CODE_FOR_spe_evmwsmf, "__builtin_spe_evmwsmf", SPE_BUILTIN_EVMWSMF }, | |
4769 | { 0, CODE_FOR_spe_evmwsmfa, "__builtin_spe_evmwsmfa", SPE_BUILTIN_EVMWSMFA }, | |
4770 | { 0, CODE_FOR_spe_evmwsmfaa, "__builtin_spe_evmwsmfaa", SPE_BUILTIN_EVMWSMFAA }, | |
4771 | { 0, CODE_FOR_spe_evmwsmfan, "__builtin_spe_evmwsmfan", SPE_BUILTIN_EVMWSMFAN }, | |
4772 | { 0, CODE_FOR_spe_evmwsmi, "__builtin_spe_evmwsmi", SPE_BUILTIN_EVMWSMI }, | |
4773 | { 0, CODE_FOR_spe_evmwsmia, "__builtin_spe_evmwsmia", SPE_BUILTIN_EVMWSMIA }, | |
4774 | { 0, CODE_FOR_spe_evmwsmiaa, "__builtin_spe_evmwsmiaa", SPE_BUILTIN_EVMWSMIAA }, | |
4775 | { 0, CODE_FOR_spe_evmwsmian, "__builtin_spe_evmwsmian", SPE_BUILTIN_EVMWSMIAN }, | |
4776 | { 0, CODE_FOR_spe_evmwssf, "__builtin_spe_evmwssf", SPE_BUILTIN_EVMWSSF }, | |
4777 | { 0, CODE_FOR_spe_evmwssfa, "__builtin_spe_evmwssfa", SPE_BUILTIN_EVMWSSFA }, | |
4778 | { 0, CODE_FOR_spe_evmwssfaa, "__builtin_spe_evmwssfaa", SPE_BUILTIN_EVMWSSFAA }, | |
4779 | { 0, CODE_FOR_spe_evmwssfan, "__builtin_spe_evmwssfan", SPE_BUILTIN_EVMWSSFAN }, | |
4780 | { 0, CODE_FOR_spe_evmwumi, "__builtin_spe_evmwumi", SPE_BUILTIN_EVMWUMI }, | |
4781 | { 0, CODE_FOR_spe_evmwumia, "__builtin_spe_evmwumia", SPE_BUILTIN_EVMWUMIA }, | |
4782 | { 0, CODE_FOR_spe_evmwumiaa, "__builtin_spe_evmwumiaa", SPE_BUILTIN_EVMWUMIAA }, | |
4783 | { 0, CODE_FOR_spe_evmwumian, "__builtin_spe_evmwumian", SPE_BUILTIN_EVMWUMIAN }, | |
4784 | { 0, CODE_FOR_spe_evnand, "__builtin_spe_evnand", SPE_BUILTIN_EVNAND }, | |
4785 | { 0, CODE_FOR_spe_evnor, "__builtin_spe_evnor", SPE_BUILTIN_EVNOR }, | |
4786 | { 0, CODE_FOR_spe_evor, "__builtin_spe_evor", SPE_BUILTIN_EVOR }, | |
4787 | { 0, CODE_FOR_spe_evorc, "__builtin_spe_evorc", SPE_BUILTIN_EVORC }, | |
4788 | { 0, CODE_FOR_spe_evrlw, "__builtin_spe_evrlw", SPE_BUILTIN_EVRLW }, | |
4789 | { 0, CODE_FOR_spe_evslw, "__builtin_spe_evslw", SPE_BUILTIN_EVSLW }, | |
4790 | { 0, CODE_FOR_spe_evsrws, "__builtin_spe_evsrws", SPE_BUILTIN_EVSRWS }, | |
4791 | { 0, CODE_FOR_spe_evsrwu, "__builtin_spe_evsrwu", SPE_BUILTIN_EVSRWU }, | |
4792 | { 0, CODE_FOR_spe_evsubfw, "__builtin_spe_evsubfw", SPE_BUILTIN_EVSUBFW }, | |
4793 | ||
4794 | /* SPE binary operations expecting a 5-bit unsigned literal. */ | |
4795 | { 0, CODE_FOR_spe_evaddiw, "__builtin_spe_evaddiw", SPE_BUILTIN_EVADDIW }, | |
4796 | ||
4797 | { 0, CODE_FOR_spe_evrlwi, "__builtin_spe_evrlwi", SPE_BUILTIN_EVRLWI }, | |
4798 | { 0, CODE_FOR_spe_evslwi, "__builtin_spe_evslwi", SPE_BUILTIN_EVSLWI }, | |
4799 | { 0, CODE_FOR_spe_evsrwis, "__builtin_spe_evsrwis", SPE_BUILTIN_EVSRWIS }, | |
4800 | { 0, CODE_FOR_spe_evsrwiu, "__builtin_spe_evsrwiu", SPE_BUILTIN_EVSRWIU }, | |
4801 | { 0, CODE_FOR_spe_evsubifw, "__builtin_spe_evsubifw", SPE_BUILTIN_EVSUBIFW }, | |
4802 | { 0, CODE_FOR_spe_evmwhssfaa, "__builtin_spe_evmwhssfaa", SPE_BUILTIN_EVMWHSSFAA }, | |
4803 | { 0, CODE_FOR_spe_evmwhssmaa, "__builtin_spe_evmwhssmaa", SPE_BUILTIN_EVMWHSSMAA }, | |
4804 | { 0, CODE_FOR_spe_evmwhsmfaa, "__builtin_spe_evmwhsmfaa", SPE_BUILTIN_EVMWHSMFAA }, | |
4805 | { 0, CODE_FOR_spe_evmwhsmiaa, "__builtin_spe_evmwhsmiaa", SPE_BUILTIN_EVMWHSMIAA }, | |
4806 | { 0, CODE_FOR_spe_evmwhusiaa, "__builtin_spe_evmwhusiaa", SPE_BUILTIN_EVMWHUSIAA }, | |
4807 | { 0, CODE_FOR_spe_evmwhumiaa, "__builtin_spe_evmwhumiaa", SPE_BUILTIN_EVMWHUMIAA }, | |
4808 | { 0, CODE_FOR_spe_evmwhssfan, "__builtin_spe_evmwhssfan", SPE_BUILTIN_EVMWHSSFAN }, | |
4809 | { 0, CODE_FOR_spe_evmwhssian, "__builtin_spe_evmwhssian", SPE_BUILTIN_EVMWHSSIAN }, | |
4810 | { 0, CODE_FOR_spe_evmwhsmfan, "__builtin_spe_evmwhsmfan", SPE_BUILTIN_EVMWHSMFAN }, | |
4811 | { 0, CODE_FOR_spe_evmwhsmian, "__builtin_spe_evmwhsmian", SPE_BUILTIN_EVMWHSMIAN }, | |
4812 | { 0, CODE_FOR_spe_evmwhusian, "__builtin_spe_evmwhusian", SPE_BUILTIN_EVMWHUSIAN }, | |
4813 | { 0, CODE_FOR_spe_evmwhumian, "__builtin_spe_evmwhumian", SPE_BUILTIN_EVMWHUMIAN }, | |
4814 | { 0, CODE_FOR_spe_evmwhgssfaa, "__builtin_spe_evmwhgssfaa", SPE_BUILTIN_EVMWHGSSFAA }, | |
4815 | { 0, CODE_FOR_spe_evmwhgsmfaa, "__builtin_spe_evmwhgsmfaa", SPE_BUILTIN_EVMWHGSMFAA }, | |
4816 | { 0, CODE_FOR_spe_evmwhgsmiaa, "__builtin_spe_evmwhgsmiaa", SPE_BUILTIN_EVMWHGSMIAA }, | |
4817 | { 0, CODE_FOR_spe_evmwhgumiaa, "__builtin_spe_evmwhgumiaa", SPE_BUILTIN_EVMWHGUMIAA }, | |
4818 | { 0, CODE_FOR_spe_evmwhgssfan, "__builtin_spe_evmwhgssfan", SPE_BUILTIN_EVMWHGSSFAN }, | |
4819 | { 0, CODE_FOR_spe_evmwhgsmfan, "__builtin_spe_evmwhgsmfan", SPE_BUILTIN_EVMWHGSMFAN }, | |
4820 | { 0, CODE_FOR_spe_evmwhgsmian, "__builtin_spe_evmwhgsmian", SPE_BUILTIN_EVMWHGSMIAN }, | |
4821 | { 0, CODE_FOR_spe_evmwhgumian, "__builtin_spe_evmwhgumian", SPE_BUILTIN_EVMWHGUMIAN }, | |
4822 | { 0, CODE_FOR_spe_brinc, "__builtin_spe_brinc", SPE_BUILTIN_BRINC }, | |
4823 | ||
4824 | /* Place-holder. Leave as last binary SPE builtin. */ | |
17edbda5 | 4825 | { 0, CODE_FOR_xorv2si3, "__builtin_spe_evxor", SPE_BUILTIN_EVXOR }, |
ae4b4a02 AH |
4826 | }; |
4827 | ||
4828 | /* AltiVec predicates. */ | |
4829 | ||
4830 | struct builtin_description_predicates | |
4831 | { | |
4832 | const unsigned int mask; | |
4833 | const enum insn_code icode; | |
4834 | const char *opcode; | |
4835 | const char *const name; | |
4836 | const enum rs6000_builtins code; | |
4837 | }; | |
4838 | ||
4839 | static const struct builtin_description_predicates bdesc_altivec_preds[] = | |
4840 | { | |
4841 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpbfp.", "__builtin_altivec_vcmpbfp_p", ALTIVEC_BUILTIN_VCMPBFP_P }, | |
4842 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpeqfp.", "__builtin_altivec_vcmpeqfp_p", ALTIVEC_BUILTIN_VCMPEQFP_P }, | |
4843 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpgefp.", "__builtin_altivec_vcmpgefp_p", ALTIVEC_BUILTIN_VCMPGEFP_P }, | |
4844 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpgtfp.", "__builtin_altivec_vcmpgtfp_p", ALTIVEC_BUILTIN_VCMPGTFP_P }, | |
4845 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpequw.", "__builtin_altivec_vcmpequw_p", ALTIVEC_BUILTIN_VCMPEQUW_P }, | |
4846 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpgtsw.", "__builtin_altivec_vcmpgtsw_p", ALTIVEC_BUILTIN_VCMPGTSW_P }, | |
4847 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpgtuw.", "__builtin_altivec_vcmpgtuw_p", ALTIVEC_BUILTIN_VCMPGTUW_P }, | |
4848 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpgtuh.", "__builtin_altivec_vcmpgtuh_p", ALTIVEC_BUILTIN_VCMPGTUH_P }, | |
4849 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpgtsh.", "__builtin_altivec_vcmpgtsh_p", ALTIVEC_BUILTIN_VCMPGTSH_P }, | |
4850 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpequh.", "__builtin_altivec_vcmpequh_p", ALTIVEC_BUILTIN_VCMPEQUH_P }, | |
4851 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpequb.", "__builtin_altivec_vcmpequb_p", ALTIVEC_BUILTIN_VCMPEQUB_P }, | |
4852 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpgtsb.", "__builtin_altivec_vcmpgtsb_p", ALTIVEC_BUILTIN_VCMPGTSB_P }, | |
4853 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpgtub.", "__builtin_altivec_vcmpgtub_p", ALTIVEC_BUILTIN_VCMPGTUB_P } | |
0ac081f6 | 4854 | }; |
24408032 | 4855 | |
a3170dc6 AH |
4856 | /* SPE predicates. */ |
4857 | static struct builtin_description bdesc_spe_predicates[] = | |
4858 | { | |
4859 | /* Place-holder. Leave as first. */ | |
4860 | { 0, CODE_FOR_spe_evcmpeq, "__builtin_spe_evcmpeq", SPE_BUILTIN_EVCMPEQ }, | |
4861 | { 0, CODE_FOR_spe_evcmpgts, "__builtin_spe_evcmpgts", SPE_BUILTIN_EVCMPGTS }, | |
4862 | { 0, CODE_FOR_spe_evcmpgtu, "__builtin_spe_evcmpgtu", SPE_BUILTIN_EVCMPGTU }, | |
4863 | { 0, CODE_FOR_spe_evcmplts, "__builtin_spe_evcmplts", SPE_BUILTIN_EVCMPLTS }, | |
4864 | { 0, CODE_FOR_spe_evcmpltu, "__builtin_spe_evcmpltu", SPE_BUILTIN_EVCMPLTU }, | |
4865 | { 0, CODE_FOR_spe_evfscmpeq, "__builtin_spe_evfscmpeq", SPE_BUILTIN_EVFSCMPEQ }, | |
4866 | { 0, CODE_FOR_spe_evfscmpgt, "__builtin_spe_evfscmpgt", SPE_BUILTIN_EVFSCMPGT }, | |
4867 | { 0, CODE_FOR_spe_evfscmplt, "__builtin_spe_evfscmplt", SPE_BUILTIN_EVFSCMPLT }, | |
4868 | { 0, CODE_FOR_spe_evfststeq, "__builtin_spe_evfststeq", SPE_BUILTIN_EVFSTSTEQ }, | |
4869 | { 0, CODE_FOR_spe_evfststgt, "__builtin_spe_evfststgt", SPE_BUILTIN_EVFSTSTGT }, | |
4870 | /* Place-holder. Leave as last. */ | |
4871 | { 0, CODE_FOR_spe_evfststlt, "__builtin_spe_evfststlt", SPE_BUILTIN_EVFSTSTLT }, | |
4872 | }; | |
4873 | ||
4874 | /* SPE evsel predicates. */ | |
4875 | static struct builtin_description bdesc_spe_evsel[] = | |
4876 | { | |
4877 | /* Place-holder. Leave as first. */ | |
4878 | { 0, CODE_FOR_spe_evcmpgts, "__builtin_spe_evsel_gts", SPE_BUILTIN_EVSEL_CMPGTS }, | |
4879 | { 0, CODE_FOR_spe_evcmpgtu, "__builtin_spe_evsel_gtu", SPE_BUILTIN_EVSEL_CMPGTU }, | |
4880 | { 0, CODE_FOR_spe_evcmplts, "__builtin_spe_evsel_lts", SPE_BUILTIN_EVSEL_CMPLTS }, | |
4881 | { 0, CODE_FOR_spe_evcmpltu, "__builtin_spe_evsel_ltu", SPE_BUILTIN_EVSEL_CMPLTU }, | |
4882 | { 0, CODE_FOR_spe_evcmpeq, "__builtin_spe_evsel_eq", SPE_BUILTIN_EVSEL_CMPEQ }, | |
4883 | { 0, CODE_FOR_spe_evfscmpgt, "__builtin_spe_evsel_fsgt", SPE_BUILTIN_EVSEL_FSCMPGT }, | |
4884 | { 0, CODE_FOR_spe_evfscmplt, "__builtin_spe_evsel_fslt", SPE_BUILTIN_EVSEL_FSCMPLT }, | |
4885 | { 0, CODE_FOR_spe_evfscmpeq, "__builtin_spe_evsel_fseq", SPE_BUILTIN_EVSEL_FSCMPEQ }, | |
4886 | { 0, CODE_FOR_spe_evfststgt, "__builtin_spe_evsel_fststgt", SPE_BUILTIN_EVSEL_FSTSTGT }, | |
4887 | { 0, CODE_FOR_spe_evfststlt, "__builtin_spe_evsel_fststlt", SPE_BUILTIN_EVSEL_FSTSTLT }, | |
4888 | /* Place-holder. Leave as last. */ | |
4889 | { 0, CODE_FOR_spe_evfststeq, "__builtin_spe_evsel_fststeq", SPE_BUILTIN_EVSEL_FSTSTEQ }, | |
4890 | }; | |
4891 | ||
b6d08ca1 | 4892 | /* ABS* operations. */ |
100c4561 AH |
4893 | |
4894 | static const struct builtin_description bdesc_abs[] = | |
4895 | { | |
4896 | { MASK_ALTIVEC, CODE_FOR_absv4si2, "__builtin_altivec_abs_v4si", ALTIVEC_BUILTIN_ABS_V4SI }, | |
4897 | { MASK_ALTIVEC, CODE_FOR_absv8hi2, "__builtin_altivec_abs_v8hi", ALTIVEC_BUILTIN_ABS_V8HI }, | |
4898 | { MASK_ALTIVEC, CODE_FOR_absv4sf2, "__builtin_altivec_abs_v4sf", ALTIVEC_BUILTIN_ABS_V4SF }, | |
4899 | { MASK_ALTIVEC, CODE_FOR_absv16qi2, "__builtin_altivec_abs_v16qi", ALTIVEC_BUILTIN_ABS_V16QI }, | |
4900 | { MASK_ALTIVEC, CODE_FOR_altivec_abss_v4si, "__builtin_altivec_abss_v4si", ALTIVEC_BUILTIN_ABSS_V4SI }, | |
4901 | { MASK_ALTIVEC, CODE_FOR_altivec_abss_v8hi, "__builtin_altivec_abss_v8hi", ALTIVEC_BUILTIN_ABSS_V8HI }, | |
4902 | { MASK_ALTIVEC, CODE_FOR_altivec_abss_v16qi, "__builtin_altivec_abss_v16qi", ALTIVEC_BUILTIN_ABSS_V16QI } | |
4903 | }; | |
4904 | ||
617e0e1d DB |
4905 | /* Simple unary operations: VECb = foo (unsigned literal) or VECb = |
4906 | foo (VECa). */ | |
24408032 | 4907 | |
a3170dc6 | 4908 | static struct builtin_description bdesc_1arg[] = |
2212663f | 4909 | { |
617e0e1d DB |
4910 | { MASK_ALTIVEC, CODE_FOR_altivec_vexptefp, "__builtin_altivec_vexptefp", ALTIVEC_BUILTIN_VEXPTEFP }, |
4911 | { MASK_ALTIVEC, CODE_FOR_altivec_vlogefp, "__builtin_altivec_vlogefp", ALTIVEC_BUILTIN_VLOGEFP }, | |
4912 | { MASK_ALTIVEC, CODE_FOR_altivec_vrefp, "__builtin_altivec_vrefp", ALTIVEC_BUILTIN_VREFP }, | |
4913 | { MASK_ALTIVEC, CODE_FOR_altivec_vrfim, "__builtin_altivec_vrfim", ALTIVEC_BUILTIN_VRFIM }, | |
4914 | { MASK_ALTIVEC, CODE_FOR_altivec_vrfin, "__builtin_altivec_vrfin", ALTIVEC_BUILTIN_VRFIN }, | |
4915 | { MASK_ALTIVEC, CODE_FOR_altivec_vrfip, "__builtin_altivec_vrfip", ALTIVEC_BUILTIN_VRFIP }, | |
4916 | { MASK_ALTIVEC, CODE_FOR_ftruncv4sf2, "__builtin_altivec_vrfiz", ALTIVEC_BUILTIN_VRFIZ }, | |
4917 | { MASK_ALTIVEC, CODE_FOR_altivec_vrsqrtefp, "__builtin_altivec_vrsqrtefp", ALTIVEC_BUILTIN_VRSQRTEFP }, | |
2212663f DB |
4918 | { MASK_ALTIVEC, CODE_FOR_altivec_vspltisb, "__builtin_altivec_vspltisb", ALTIVEC_BUILTIN_VSPLTISB }, |
4919 | { MASK_ALTIVEC, CODE_FOR_altivec_vspltish, "__builtin_altivec_vspltish", ALTIVEC_BUILTIN_VSPLTISH }, | |
4920 | { MASK_ALTIVEC, CODE_FOR_altivec_vspltisw, "__builtin_altivec_vspltisw", ALTIVEC_BUILTIN_VSPLTISW }, | |
20e26713 AH |
4921 | { MASK_ALTIVEC, CODE_FOR_altivec_vupkhsb, "__builtin_altivec_vupkhsb", ALTIVEC_BUILTIN_VUPKHSB }, |
4922 | { MASK_ALTIVEC, CODE_FOR_altivec_vupkhpx, "__builtin_altivec_vupkhpx", ALTIVEC_BUILTIN_VUPKHPX }, | |
4923 | { MASK_ALTIVEC, CODE_FOR_altivec_vupkhsh, "__builtin_altivec_vupkhsh", ALTIVEC_BUILTIN_VUPKHSH }, | |
4924 | { MASK_ALTIVEC, CODE_FOR_altivec_vupklsb, "__builtin_altivec_vupklsb", ALTIVEC_BUILTIN_VUPKLSB }, | |
4925 | { MASK_ALTIVEC, CODE_FOR_altivec_vupklpx, "__builtin_altivec_vupklpx", ALTIVEC_BUILTIN_VUPKLPX }, | |
4926 | { MASK_ALTIVEC, CODE_FOR_altivec_vupklsh, "__builtin_altivec_vupklsh", ALTIVEC_BUILTIN_VUPKLSH }, | |
a3170dc6 AH |
4927 | |
4928 | /* The SPE unary builtins must start with SPE_BUILTIN_EVABS and | |
4929 | end with SPE_BUILTIN_EVSUBFUSIAAW. */ | |
4930 | { 0, CODE_FOR_spe_evabs, "__builtin_spe_evabs", SPE_BUILTIN_EVABS }, | |
4931 | { 0, CODE_FOR_spe_evaddsmiaaw, "__builtin_spe_evaddsmiaaw", SPE_BUILTIN_EVADDSMIAAW }, | |
4932 | { 0, CODE_FOR_spe_evaddssiaaw, "__builtin_spe_evaddssiaaw", SPE_BUILTIN_EVADDSSIAAW }, | |
4933 | { 0, CODE_FOR_spe_evaddumiaaw, "__builtin_spe_evaddumiaaw", SPE_BUILTIN_EVADDUMIAAW }, | |
4934 | { 0, CODE_FOR_spe_evaddusiaaw, "__builtin_spe_evaddusiaaw", SPE_BUILTIN_EVADDUSIAAW }, | |
4935 | { 0, CODE_FOR_spe_evcntlsw, "__builtin_spe_evcntlsw", SPE_BUILTIN_EVCNTLSW }, | |
4936 | { 0, CODE_FOR_spe_evcntlzw, "__builtin_spe_evcntlzw", SPE_BUILTIN_EVCNTLZW }, | |
4937 | { 0, CODE_FOR_spe_evextsb, "__builtin_spe_evextsb", SPE_BUILTIN_EVEXTSB }, | |
4938 | { 0, CODE_FOR_spe_evextsh, "__builtin_spe_evextsh", SPE_BUILTIN_EVEXTSH }, | |
4939 | { 0, CODE_FOR_spe_evfsabs, "__builtin_spe_evfsabs", SPE_BUILTIN_EVFSABS }, | |
4940 | { 0, CODE_FOR_spe_evfscfsf, "__builtin_spe_evfscfsf", SPE_BUILTIN_EVFSCFSF }, | |
4941 | { 0, CODE_FOR_spe_evfscfsi, "__builtin_spe_evfscfsi", SPE_BUILTIN_EVFSCFSI }, | |
4942 | { 0, CODE_FOR_spe_evfscfuf, "__builtin_spe_evfscfuf", SPE_BUILTIN_EVFSCFUF }, | |
4943 | { 0, CODE_FOR_spe_evfscfui, "__builtin_spe_evfscfui", SPE_BUILTIN_EVFSCFUI }, | |
4944 | { 0, CODE_FOR_spe_evfsctsf, "__builtin_spe_evfsctsf", SPE_BUILTIN_EVFSCTSF }, | |
4945 | { 0, CODE_FOR_spe_evfsctsi, "__builtin_spe_evfsctsi", SPE_BUILTIN_EVFSCTSI }, | |
4946 | { 0, CODE_FOR_spe_evfsctsiz, "__builtin_spe_evfsctsiz", SPE_BUILTIN_EVFSCTSIZ }, | |
4947 | { 0, CODE_FOR_spe_evfsctuf, "__builtin_spe_evfsctuf", SPE_BUILTIN_EVFSCTUF }, | |
4948 | { 0, CODE_FOR_spe_evfsctui, "__builtin_spe_evfsctui", SPE_BUILTIN_EVFSCTUI }, | |
4949 | { 0, CODE_FOR_spe_evfsctuiz, "__builtin_spe_evfsctuiz", SPE_BUILTIN_EVFSCTUIZ }, | |
4950 | { 0, CODE_FOR_spe_evfsnabs, "__builtin_spe_evfsnabs", SPE_BUILTIN_EVFSNABS }, | |
4951 | { 0, CODE_FOR_spe_evfsneg, "__builtin_spe_evfsneg", SPE_BUILTIN_EVFSNEG }, | |
4952 | { 0, CODE_FOR_spe_evmra, "__builtin_spe_evmra", SPE_BUILTIN_EVMRA }, | |
4953 | { 0, CODE_FOR_spe_evneg, "__builtin_spe_evneg", SPE_BUILTIN_EVNEG }, | |
4954 | { 0, CODE_FOR_spe_evrndw, "__builtin_spe_evrndw", SPE_BUILTIN_EVRNDW }, | |
4955 | { 0, CODE_FOR_spe_evsubfsmiaaw, "__builtin_spe_evsubfsmiaaw", SPE_BUILTIN_EVSUBFSMIAAW }, | |
4956 | { 0, CODE_FOR_spe_evsubfssiaaw, "__builtin_spe_evsubfssiaaw", SPE_BUILTIN_EVSUBFSSIAAW }, | |
4957 | { 0, CODE_FOR_spe_evsubfumiaaw, "__builtin_spe_evsubfumiaaw", SPE_BUILTIN_EVSUBFUMIAAW }, | |
4958 | { 0, CODE_FOR_spe_evsplatfi, "__builtin_spe_evsplatfi", SPE_BUILTIN_EVSPLATFI }, | |
4959 | { 0, CODE_FOR_spe_evsplati, "__builtin_spe_evsplati", SPE_BUILTIN_EVSPLATI }, | |
4960 | ||
4961 | /* Place-holder. Leave as last unary SPE builtin. */ | |
4962 | { 0, CODE_FOR_spe_evsubfusiaaw, "__builtin_spe_evsubfusiaaw", SPE_BUILTIN_EVSUBFUSIAAW }, | |
2212663f DB |
4963 | }; |
4964 | ||
4965 | static rtx | |
92898235 | 4966 | rs6000_expand_unop_builtin (icode, arglist, target) |
2212663f DB |
4967 | enum insn_code icode; |
4968 | tree arglist; | |
4969 | rtx target; | |
4970 | { | |
4971 | rtx pat; | |
4972 | tree arg0 = TREE_VALUE (arglist); | |
4973 | rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
4974 | enum machine_mode tmode = insn_data[icode].operand[0].mode; | |
4975 | enum machine_mode mode0 = insn_data[icode].operand[1].mode; | |
4976 | ||
0559cc77 DE |
4977 | if (icode == CODE_FOR_nothing) |
4978 | /* Builtin not supported on this processor. */ | |
4979 | return 0; | |
4980 | ||
20e26713 AH |
4981 | /* If we got invalid arguments bail out before generating bad rtl. */ |
4982 | if (arg0 == error_mark_node) | |
9a171fcd | 4983 | return const0_rtx; |
20e26713 | 4984 | |
0559cc77 DE |
4985 | if (icode == CODE_FOR_altivec_vspltisb |
4986 | || icode == CODE_FOR_altivec_vspltish | |
4987 | || icode == CODE_FOR_altivec_vspltisw | |
4988 | || icode == CODE_FOR_spe_evsplatfi | |
4989 | || icode == CODE_FOR_spe_evsplati) | |
b44140e7 AH |
4990 | { |
4991 | /* Only allow 5-bit *signed* literals. */ | |
b44140e7 AH |
4992 | if (GET_CODE (op0) != CONST_INT |
4993 | || INTVAL (op0) > 0x1f | |
4994 | || INTVAL (op0) < -0x1f) | |
4995 | { | |
4996 | error ("argument 1 must be a 5-bit signed literal"); | |
9a171fcd | 4997 | return const0_rtx; |
b44140e7 | 4998 | } |
b44140e7 AH |
4999 | } |
5000 | ||
c62f2db5 | 5001 | if (target == 0 |
2212663f DB |
5002 | || GET_MODE (target) != tmode |
5003 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
5004 | target = gen_reg_rtx (tmode); | |
5005 | ||
5006 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) | |
5007 | op0 = copy_to_mode_reg (mode0, op0); | |
5008 | ||
5009 | pat = GEN_FCN (icode) (target, op0); | |
5010 | if (! pat) | |
5011 | return 0; | |
5012 | emit_insn (pat); | |
0ac081f6 | 5013 | |
2212663f DB |
5014 | return target; |
5015 | } | |
ae4b4a02 | 5016 | |
100c4561 AH |
5017 | static rtx |
5018 | altivec_expand_abs_builtin (icode, arglist, target) | |
5019 | enum insn_code icode; | |
5020 | tree arglist; | |
5021 | rtx target; | |
5022 | { | |
5023 | rtx pat, scratch1, scratch2; | |
5024 | tree arg0 = TREE_VALUE (arglist); | |
5025 | rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
5026 | enum machine_mode tmode = insn_data[icode].operand[0].mode; | |
5027 | enum machine_mode mode0 = insn_data[icode].operand[1].mode; | |
5028 | ||
5029 | /* If we have invalid arguments, bail out before generating bad rtl. */ | |
5030 | if (arg0 == error_mark_node) | |
9a171fcd | 5031 | return const0_rtx; |
100c4561 AH |
5032 | |
5033 | if (target == 0 | |
5034 | || GET_MODE (target) != tmode | |
5035 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
5036 | target = gen_reg_rtx (tmode); | |
5037 | ||
5038 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) | |
5039 | op0 = copy_to_mode_reg (mode0, op0); | |
5040 | ||
5041 | scratch1 = gen_reg_rtx (mode0); | |
5042 | scratch2 = gen_reg_rtx (mode0); | |
5043 | ||
5044 | pat = GEN_FCN (icode) (target, op0, scratch1, scratch2); | |
5045 | if (! pat) | |
5046 | return 0; | |
5047 | emit_insn (pat); | |
5048 | ||
5049 | return target; | |
5050 | } | |
5051 | ||
0ac081f6 | 5052 | static rtx |
92898235 | 5053 | rs6000_expand_binop_builtin (icode, arglist, target) |
0ac081f6 AH |
5054 | enum insn_code icode; |
5055 | tree arglist; | |
5056 | rtx target; | |
5057 | { | |
5058 | rtx pat; | |
5059 | tree arg0 = TREE_VALUE (arglist); | |
5060 | tree arg1 = TREE_VALUE (TREE_CHAIN (arglist)); | |
5061 | rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
5062 | rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); | |
5063 | enum machine_mode tmode = insn_data[icode].operand[0].mode; | |
5064 | enum machine_mode mode0 = insn_data[icode].operand[1].mode; | |
5065 | enum machine_mode mode1 = insn_data[icode].operand[2].mode; | |
5066 | ||
0559cc77 DE |
5067 | if (icode == CODE_FOR_nothing) |
5068 | /* Builtin not supported on this processor. */ | |
5069 | return 0; | |
5070 | ||
20e26713 AH |
5071 | /* If we got invalid arguments bail out before generating bad rtl. */ |
5072 | if (arg0 == error_mark_node || arg1 == error_mark_node) | |
9a171fcd | 5073 | return const0_rtx; |
20e26713 | 5074 | |
0559cc77 DE |
5075 | if (icode == CODE_FOR_altivec_vcfux |
5076 | || icode == CODE_FOR_altivec_vcfsx | |
5077 | || icode == CODE_FOR_altivec_vctsxs | |
5078 | || icode == CODE_FOR_altivec_vctuxs | |
5079 | || icode == CODE_FOR_altivec_vspltb | |
5080 | || icode == CODE_FOR_altivec_vsplth | |
5081 | || icode == CODE_FOR_altivec_vspltw | |
5082 | || icode == CODE_FOR_spe_evaddiw | |
5083 | || icode == CODE_FOR_spe_evldd | |
5084 | || icode == CODE_FOR_spe_evldh | |
5085 | || icode == CODE_FOR_spe_evldw | |
5086 | || icode == CODE_FOR_spe_evlhhesplat | |
5087 | || icode == CODE_FOR_spe_evlhhossplat | |
5088 | || icode == CODE_FOR_spe_evlhhousplat | |
5089 | || icode == CODE_FOR_spe_evlwhe | |
5090 | || icode == CODE_FOR_spe_evlwhos | |
5091 | || icode == CODE_FOR_spe_evlwhou | |
5092 | || icode == CODE_FOR_spe_evlwhsplat | |
5093 | || icode == CODE_FOR_spe_evlwwsplat | |
5094 | || icode == CODE_FOR_spe_evrlwi | |
5095 | || icode == CODE_FOR_spe_evslwi | |
5096 | || icode == CODE_FOR_spe_evsrwis | |
f5119d10 | 5097 | || icode == CODE_FOR_spe_evsubifw |
0559cc77 | 5098 | || icode == CODE_FOR_spe_evsrwiu) |
b44140e7 AH |
5099 | { |
5100 | /* Only allow 5-bit unsigned literals. */ | |
b44140e7 AH |
5101 | if (TREE_CODE (arg1) != INTEGER_CST |
5102 | || TREE_INT_CST_LOW (arg1) & ~0x1f) | |
5103 | { | |
5104 | error ("argument 2 must be a 5-bit unsigned literal"); | |
9a171fcd | 5105 | return const0_rtx; |
b44140e7 | 5106 | } |
b44140e7 AH |
5107 | } |
5108 | ||
c62f2db5 | 5109 | if (target == 0 |
0ac081f6 AH |
5110 | || GET_MODE (target) != tmode |
5111 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
5112 | target = gen_reg_rtx (tmode); | |
5113 | ||
5114 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) | |
5115 | op0 = copy_to_mode_reg (mode0, op0); | |
5116 | if (! (*insn_data[icode].operand[2].predicate) (op1, mode1)) | |
5117 | op1 = copy_to_mode_reg (mode1, op1); | |
5118 | ||
5119 | pat = GEN_FCN (icode) (target, op0, op1); | |
5120 | if (! pat) | |
5121 | return 0; | |
5122 | emit_insn (pat); | |
5123 | ||
5124 | return target; | |
5125 | } | |
6525c0e7 | 5126 | |
ae4b4a02 AH |
5127 | static rtx |
5128 | altivec_expand_predicate_builtin (icode, opcode, arglist, target) | |
5129 | enum insn_code icode; | |
5130 | const char *opcode; | |
5131 | tree arglist; | |
5132 | rtx target; | |
5133 | { | |
5134 | rtx pat, scratch; | |
5135 | tree cr6_form = TREE_VALUE (arglist); | |
5136 | tree arg0 = TREE_VALUE (TREE_CHAIN (arglist)); | |
5137 | tree arg1 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist))); | |
5138 | rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
5139 | rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); | |
5140 | enum machine_mode tmode = SImode; | |
5141 | enum machine_mode mode0 = insn_data[icode].operand[1].mode; | |
5142 | enum machine_mode mode1 = insn_data[icode].operand[2].mode; | |
5143 | int cr6_form_int; | |
5144 | ||
5145 | if (TREE_CODE (cr6_form) != INTEGER_CST) | |
5146 | { | |
5147 | error ("argument 1 of __builtin_altivec_predicate must be a constant"); | |
9a171fcd | 5148 | return const0_rtx; |
ae4b4a02 AH |
5149 | } |
5150 | else | |
5151 | cr6_form_int = TREE_INT_CST_LOW (cr6_form); | |
5152 | ||
5153 | if (mode0 != mode1) | |
5154 | abort (); | |
5155 | ||
5156 | /* If we have invalid arguments, bail out before generating bad rtl. */ | |
5157 | if (arg0 == error_mark_node || arg1 == error_mark_node) | |
9a171fcd | 5158 | return const0_rtx; |
ae4b4a02 AH |
5159 | |
5160 | if (target == 0 | |
5161 | || GET_MODE (target) != tmode | |
5162 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
5163 | target = gen_reg_rtx (tmode); | |
5164 | ||
5165 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) | |
5166 | op0 = copy_to_mode_reg (mode0, op0); | |
5167 | if (! (*insn_data[icode].operand[2].predicate) (op1, mode1)) | |
5168 | op1 = copy_to_mode_reg (mode1, op1); | |
5169 | ||
5170 | scratch = gen_reg_rtx (mode0); | |
5171 | ||
5172 | pat = GEN_FCN (icode) (scratch, op0, op1, | |
5173 | gen_rtx (SYMBOL_REF, Pmode, opcode)); | |
5174 | if (! pat) | |
5175 | return 0; | |
5176 | emit_insn (pat); | |
5177 | ||
5178 | /* The vec_any* and vec_all* predicates use the same opcodes for two | |
5179 | different operations, but the bits in CR6 will be different | |
5180 | depending on what information we want. So we have to play tricks | |
5181 | with CR6 to get the right bits out. | |
5182 | ||
5183 | If you think this is disgusting, look at the specs for the | |
5184 | AltiVec predicates. */ | |
5185 | ||
5186 | switch (cr6_form_int) | |
5187 | { | |
5188 | case 0: | |
5189 | emit_insn (gen_cr6_test_for_zero (target)); | |
5190 | break; | |
5191 | case 1: | |
5192 | emit_insn (gen_cr6_test_for_zero_reverse (target)); | |
5193 | break; | |
5194 | case 2: | |
5195 | emit_insn (gen_cr6_test_for_lt (target)); | |
5196 | break; | |
5197 | case 3: | |
5198 | emit_insn (gen_cr6_test_for_lt_reverse (target)); | |
5199 | break; | |
5200 | default: | |
5201 | error ("argument 1 of __builtin_altivec_predicate is out of range"); | |
5202 | break; | |
5203 | } | |
5204 | ||
5205 | return target; | |
5206 | } | |
5207 | ||
6525c0e7 AH |
5208 | static rtx |
5209 | altivec_expand_stv_builtin (icode, arglist) | |
5210 | enum insn_code icode; | |
5211 | tree arglist; | |
5212 | { | |
5213 | tree arg0 = TREE_VALUE (arglist); | |
5214 | tree arg1 = TREE_VALUE (TREE_CHAIN (arglist)); | |
5215 | tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist))); | |
5216 | rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
5217 | rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); | |
5218 | rtx op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0); | |
5219 | rtx pat; | |
5220 | enum machine_mode mode0 = insn_data[icode].operand[0].mode; | |
5221 | enum machine_mode mode1 = insn_data[icode].operand[1].mode; | |
5222 | enum machine_mode mode2 = insn_data[icode].operand[2].mode; | |
5223 | ||
5224 | /* Invalid arguments. Bail before doing anything stoopid! */ | |
5225 | if (arg0 == error_mark_node | |
5226 | || arg1 == error_mark_node | |
5227 | || arg2 == error_mark_node) | |
9a171fcd | 5228 | return const0_rtx; |
6525c0e7 AH |
5229 | |
5230 | if (! (*insn_data[icode].operand[2].predicate) (op0, mode2)) | |
5231 | op0 = copy_to_mode_reg (mode2, op0); | |
5232 | if (! (*insn_data[icode].operand[0].predicate) (op1, mode0)) | |
5233 | op1 = copy_to_mode_reg (mode0, op1); | |
5234 | if (! (*insn_data[icode].operand[1].predicate) (op2, mode1)) | |
5235 | op2 = copy_to_mode_reg (mode1, op2); | |
5236 | ||
5237 | pat = GEN_FCN (icode) (op1, op2, op0); | |
5238 | if (pat) | |
5239 | emit_insn (pat); | |
5240 | return NULL_RTX; | |
5241 | } | |
5242 | ||
2212663f | 5243 | static rtx |
92898235 | 5244 | rs6000_expand_ternop_builtin (icode, arglist, target) |
2212663f DB |
5245 | enum insn_code icode; |
5246 | tree arglist; | |
5247 | rtx target; | |
5248 | { | |
5249 | rtx pat; | |
5250 | tree arg0 = TREE_VALUE (arglist); | |
5251 | tree arg1 = TREE_VALUE (TREE_CHAIN (arglist)); | |
5252 | tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist))); | |
5253 | rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
5254 | rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); | |
5255 | rtx op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0); | |
5256 | enum machine_mode tmode = insn_data[icode].operand[0].mode; | |
5257 | enum machine_mode mode0 = insn_data[icode].operand[1].mode; | |
5258 | enum machine_mode mode1 = insn_data[icode].operand[2].mode; | |
5259 | enum machine_mode mode2 = insn_data[icode].operand[3].mode; | |
0ac081f6 | 5260 | |
774b5662 DE |
5261 | if (icode == CODE_FOR_nothing) |
5262 | /* Builtin not supported on this processor. */ | |
5263 | return 0; | |
5264 | ||
20e26713 AH |
5265 | /* If we got invalid arguments bail out before generating bad rtl. */ |
5266 | if (arg0 == error_mark_node | |
5267 | || arg1 == error_mark_node | |
5268 | || arg2 == error_mark_node) | |
9a171fcd | 5269 | return const0_rtx; |
20e26713 | 5270 | |
774b5662 DE |
5271 | if (icode == CODE_FOR_altivec_vsldoi_4sf |
5272 | || icode == CODE_FOR_altivec_vsldoi_4si | |
5273 | || icode == CODE_FOR_altivec_vsldoi_8hi | |
5274 | || icode == CODE_FOR_altivec_vsldoi_16qi) | |
b44140e7 AH |
5275 | { |
5276 | /* Only allow 4-bit unsigned literals. */ | |
b44140e7 AH |
5277 | if (TREE_CODE (arg2) != INTEGER_CST |
5278 | || TREE_INT_CST_LOW (arg2) & ~0xf) | |
5279 | { | |
5280 | error ("argument 3 must be a 4-bit unsigned literal"); | |
e3277ffb | 5281 | return const0_rtx; |
b44140e7 | 5282 | } |
b44140e7 AH |
5283 | } |
5284 | ||
c62f2db5 | 5285 | if (target == 0 |
2212663f DB |
5286 | || GET_MODE (target) != tmode |
5287 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
5288 | target = gen_reg_rtx (tmode); | |
5289 | ||
5290 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) | |
5291 | op0 = copy_to_mode_reg (mode0, op0); | |
5292 | if (! (*insn_data[icode].operand[2].predicate) (op1, mode1)) | |
5293 | op1 = copy_to_mode_reg (mode1, op1); | |
5294 | if (! (*insn_data[icode].operand[3].predicate) (op2, mode2)) | |
5295 | op2 = copy_to_mode_reg (mode2, op2); | |
5296 | ||
5297 | pat = GEN_FCN (icode) (target, op0, op1, op2); | |
5298 | if (! pat) | |
5299 | return 0; | |
5300 | emit_insn (pat); | |
5301 | ||
5302 | return target; | |
5303 | } | |
92898235 | 5304 | |
3a9b8c7e | 5305 | /* Expand the lvx builtins. */ |
0ac081f6 | 5306 | static rtx |
3a9b8c7e | 5307 | altivec_expand_ld_builtin (exp, target, expandedp) |
0ac081f6 AH |
5308 | tree exp; |
5309 | rtx target; | |
92898235 | 5310 | bool *expandedp; |
0ac081f6 | 5311 | { |
0ac081f6 AH |
5312 | tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0); |
5313 | tree arglist = TREE_OPERAND (exp, 1); | |
0ac081f6 | 5314 | unsigned int fcode = DECL_FUNCTION_CODE (fndecl); |
3a9b8c7e AH |
5315 | tree arg0; |
5316 | enum machine_mode tmode, mode0; | |
7c3abc73 | 5317 | rtx pat, op0; |
3a9b8c7e | 5318 | enum insn_code icode; |
92898235 | 5319 | |
0ac081f6 AH |
5320 | switch (fcode) |
5321 | { | |
f18c054f DB |
5322 | case ALTIVEC_BUILTIN_LD_INTERNAL_16qi: |
5323 | icode = CODE_FOR_altivec_lvx_16qi; | |
3a9b8c7e | 5324 | break; |
f18c054f DB |
5325 | case ALTIVEC_BUILTIN_LD_INTERNAL_8hi: |
5326 | icode = CODE_FOR_altivec_lvx_8hi; | |
3a9b8c7e AH |
5327 | break; |
5328 | case ALTIVEC_BUILTIN_LD_INTERNAL_4si: | |
5329 | icode = CODE_FOR_altivec_lvx_4si; | |
5330 | break; | |
5331 | case ALTIVEC_BUILTIN_LD_INTERNAL_4sf: | |
5332 | icode = CODE_FOR_altivec_lvx_4sf; | |
5333 | break; | |
5334 | default: | |
5335 | *expandedp = false; | |
5336 | return NULL_RTX; | |
5337 | } | |
0ac081f6 | 5338 | |
3a9b8c7e | 5339 | *expandedp = true; |
f18c054f | 5340 | |
3a9b8c7e AH |
5341 | arg0 = TREE_VALUE (arglist); |
5342 | op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
5343 | tmode = insn_data[icode].operand[0].mode; | |
5344 | mode0 = insn_data[icode].operand[1].mode; | |
f18c054f | 5345 | |
3a9b8c7e AH |
5346 | if (target == 0 |
5347 | || GET_MODE (target) != tmode | |
5348 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
5349 | target = gen_reg_rtx (tmode); | |
24408032 | 5350 | |
3a9b8c7e AH |
5351 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) |
5352 | op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0)); | |
f18c054f | 5353 | |
3a9b8c7e AH |
5354 | pat = GEN_FCN (icode) (target, op0); |
5355 | if (! pat) | |
5356 | return 0; | |
5357 | emit_insn (pat); | |
5358 | return target; | |
5359 | } | |
f18c054f | 5360 | |
3a9b8c7e AH |
5361 | /* Expand the stvx builtins. */ |
5362 | static rtx | |
5363 | altivec_expand_st_builtin (exp, target, expandedp) | |
5364 | tree exp; | |
7c3abc73 | 5365 | rtx target ATTRIBUTE_UNUSED; |
3a9b8c7e AH |
5366 | bool *expandedp; |
5367 | { | |
5368 | tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0); | |
5369 | tree arglist = TREE_OPERAND (exp, 1); | |
5370 | unsigned int fcode = DECL_FUNCTION_CODE (fndecl); | |
5371 | tree arg0, arg1; | |
5372 | enum machine_mode mode0, mode1; | |
7c3abc73 | 5373 | rtx pat, op0, op1; |
3a9b8c7e | 5374 | enum insn_code icode; |
f18c054f | 5375 | |
3a9b8c7e AH |
5376 | switch (fcode) |
5377 | { | |
5378 | case ALTIVEC_BUILTIN_ST_INTERNAL_16qi: | |
5379 | icode = CODE_FOR_altivec_stvx_16qi; | |
5380 | break; | |
5381 | case ALTIVEC_BUILTIN_ST_INTERNAL_8hi: | |
5382 | icode = CODE_FOR_altivec_stvx_8hi; | |
5383 | break; | |
5384 | case ALTIVEC_BUILTIN_ST_INTERNAL_4si: | |
5385 | icode = CODE_FOR_altivec_stvx_4si; | |
5386 | break; | |
5387 | case ALTIVEC_BUILTIN_ST_INTERNAL_4sf: | |
5388 | icode = CODE_FOR_altivec_stvx_4sf; | |
5389 | break; | |
5390 | default: | |
5391 | *expandedp = false; | |
5392 | return NULL_RTX; | |
5393 | } | |
24408032 | 5394 | |
3a9b8c7e AH |
5395 | arg0 = TREE_VALUE (arglist); |
5396 | arg1 = TREE_VALUE (TREE_CHAIN (arglist)); | |
5397 | op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
5398 | op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); | |
5399 | mode0 = insn_data[icode].operand[0].mode; | |
5400 | mode1 = insn_data[icode].operand[1].mode; | |
f18c054f | 5401 | |
3a9b8c7e AH |
5402 | if (! (*insn_data[icode].operand[0].predicate) (op0, mode0)) |
5403 | op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0)); | |
5404 | if (! (*insn_data[icode].operand[1].predicate) (op1, mode1)) | |
5405 | op1 = copy_to_mode_reg (mode1, op1); | |
f18c054f | 5406 | |
3a9b8c7e AH |
5407 | pat = GEN_FCN (icode) (op0, op1); |
5408 | if (pat) | |
5409 | emit_insn (pat); | |
f18c054f | 5410 | |
3a9b8c7e AH |
5411 | *expandedp = true; |
5412 | return NULL_RTX; | |
5413 | } | |
f18c054f | 5414 | |
3a9b8c7e AH |
5415 | /* Expand the dst builtins. */ |
5416 | static rtx | |
5417 | altivec_expand_dst_builtin (exp, target, expandedp) | |
5418 | tree exp; | |
7c3abc73 | 5419 | rtx target ATTRIBUTE_UNUSED; |
3a9b8c7e AH |
5420 | bool *expandedp; |
5421 | { | |
5422 | tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0); | |
5423 | tree arglist = TREE_OPERAND (exp, 1); | |
5424 | unsigned int fcode = DECL_FUNCTION_CODE (fndecl); | |
5425 | tree arg0, arg1, arg2; | |
5426 | enum machine_mode mode0, mode1, mode2; | |
7c3abc73 | 5427 | rtx pat, op0, op1, op2; |
3a9b8c7e | 5428 | struct builtin_description *d; |
a3170dc6 | 5429 | size_t i; |
f18c054f | 5430 | |
3a9b8c7e | 5431 | *expandedp = false; |
f18c054f | 5432 | |
3a9b8c7e AH |
5433 | /* Handle DST variants. */ |
5434 | d = (struct builtin_description *) bdesc_dst; | |
5435 | for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++) | |
5436 | if (d->code == fcode) | |
5437 | { | |
5438 | arg0 = TREE_VALUE (arglist); | |
5439 | arg1 = TREE_VALUE (TREE_CHAIN (arglist)); | |
5440 | arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist))); | |
5441 | op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
5442 | op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); | |
5443 | op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0); | |
5444 | mode0 = insn_data[d->icode].operand[0].mode; | |
5445 | mode1 = insn_data[d->icode].operand[1].mode; | |
5446 | mode2 = insn_data[d->icode].operand[2].mode; | |
24408032 | 5447 | |
3a9b8c7e AH |
5448 | /* Invalid arguments, bail out before generating bad rtl. */ |
5449 | if (arg0 == error_mark_node | |
5450 | || arg1 == error_mark_node | |
5451 | || arg2 == error_mark_node) | |
5452 | return const0_rtx; | |
f18c054f | 5453 | |
3a9b8c7e AH |
5454 | if (TREE_CODE (arg2) != INTEGER_CST |
5455 | || TREE_INT_CST_LOW (arg2) & ~0x3) | |
5456 | { | |
5457 | error ("argument to `%s' must be a 2-bit unsigned literal", d->name); | |
5458 | return const0_rtx; | |
5459 | } | |
f18c054f | 5460 | |
3a9b8c7e AH |
5461 | if (! (*insn_data[d->icode].operand[0].predicate) (op0, mode0)) |
5462 | op0 = copy_to_mode_reg (mode0, op0); | |
5463 | if (! (*insn_data[d->icode].operand[1].predicate) (op1, mode1)) | |
5464 | op1 = copy_to_mode_reg (mode1, op1); | |
24408032 | 5465 | |
3a9b8c7e AH |
5466 | pat = GEN_FCN (d->icode) (op0, op1, op2); |
5467 | if (pat != 0) | |
5468 | emit_insn (pat); | |
f18c054f | 5469 | |
3a9b8c7e AH |
5470 | *expandedp = true; |
5471 | return NULL_RTX; | |
5472 | } | |
f18c054f | 5473 | |
3a9b8c7e AH |
5474 | return NULL_RTX; |
5475 | } | |
24408032 | 5476 | |
3a9b8c7e AH |
5477 | /* Expand the builtin in EXP and store the result in TARGET. Store |
5478 | true in *EXPANDEDP if we found a builtin to expand. */ | |
5479 | static rtx | |
5480 | altivec_expand_builtin (exp, target, expandedp) | |
5481 | tree exp; | |
5482 | rtx target; | |
5483 | bool *expandedp; | |
5484 | { | |
5485 | struct builtin_description *d; | |
5486 | struct builtin_description_predicates *dp; | |
5487 | size_t i; | |
5488 | enum insn_code icode; | |
5489 | tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0); | |
5490 | tree arglist = TREE_OPERAND (exp, 1); | |
7c3abc73 AH |
5491 | tree arg0; |
5492 | rtx op0, pat; | |
5493 | enum machine_mode tmode, mode0; | |
3a9b8c7e | 5494 | unsigned int fcode = DECL_FUNCTION_CODE (fndecl); |
0ac081f6 | 5495 | |
3a9b8c7e AH |
5496 | target = altivec_expand_ld_builtin (exp, target, expandedp); |
5497 | if (*expandedp) | |
5498 | return target; | |
0ac081f6 | 5499 | |
3a9b8c7e AH |
5500 | target = altivec_expand_st_builtin (exp, target, expandedp); |
5501 | if (*expandedp) | |
5502 | return target; | |
5503 | ||
5504 | target = altivec_expand_dst_builtin (exp, target, expandedp); | |
5505 | if (*expandedp) | |
5506 | return target; | |
5507 | ||
5508 | *expandedp = true; | |
95385cbb | 5509 | |
3a9b8c7e AH |
5510 | switch (fcode) |
5511 | { | |
6525c0e7 AH |
5512 | case ALTIVEC_BUILTIN_STVX: |
5513 | return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx, arglist); | |
5514 | case ALTIVEC_BUILTIN_STVEBX: | |
5515 | return altivec_expand_stv_builtin (CODE_FOR_altivec_stvebx, arglist); | |
5516 | case ALTIVEC_BUILTIN_STVEHX: | |
5517 | return altivec_expand_stv_builtin (CODE_FOR_altivec_stvehx, arglist); | |
5518 | case ALTIVEC_BUILTIN_STVEWX: | |
5519 | return altivec_expand_stv_builtin (CODE_FOR_altivec_stvewx, arglist); | |
5520 | case ALTIVEC_BUILTIN_STVXL: | |
5521 | return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl, arglist); | |
3a9b8c7e | 5522 | |
95385cbb AH |
5523 | case ALTIVEC_BUILTIN_MFVSCR: |
5524 | icode = CODE_FOR_altivec_mfvscr; | |
5525 | tmode = insn_data[icode].operand[0].mode; | |
5526 | ||
5527 | if (target == 0 | |
5528 | || GET_MODE (target) != tmode | |
5529 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
5530 | target = gen_reg_rtx (tmode); | |
5531 | ||
5532 | pat = GEN_FCN (icode) (target); | |
0ac081f6 AH |
5533 | if (! pat) |
5534 | return 0; | |
5535 | emit_insn (pat); | |
95385cbb AH |
5536 | return target; |
5537 | ||
5538 | case ALTIVEC_BUILTIN_MTVSCR: | |
5539 | icode = CODE_FOR_altivec_mtvscr; | |
5540 | arg0 = TREE_VALUE (arglist); | |
5541 | op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
5542 | mode0 = insn_data[icode].operand[0].mode; | |
5543 | ||
5544 | /* If we got invalid arguments bail out before generating bad rtl. */ | |
5545 | if (arg0 == error_mark_node) | |
9a171fcd | 5546 | return const0_rtx; |
95385cbb AH |
5547 | |
5548 | if (! (*insn_data[icode].operand[0].predicate) (op0, mode0)) | |
5549 | op0 = copy_to_mode_reg (mode0, op0); | |
5550 | ||
5551 | pat = GEN_FCN (icode) (op0); | |
5552 | if (pat) | |
5553 | emit_insn (pat); | |
5554 | return NULL_RTX; | |
3a9b8c7e | 5555 | |
95385cbb AH |
5556 | case ALTIVEC_BUILTIN_DSSALL: |
5557 | emit_insn (gen_altivec_dssall ()); | |
5558 | return NULL_RTX; | |
5559 | ||
5560 | case ALTIVEC_BUILTIN_DSS: | |
5561 | icode = CODE_FOR_altivec_dss; | |
5562 | arg0 = TREE_VALUE (arglist); | |
5563 | op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
5564 | mode0 = insn_data[icode].operand[0].mode; | |
5565 | ||
5566 | /* If we got invalid arguments bail out before generating bad rtl. */ | |
5567 | if (arg0 == error_mark_node) | |
9a171fcd | 5568 | return const0_rtx; |
95385cbb | 5569 | |
b44140e7 AH |
5570 | if (TREE_CODE (arg0) != INTEGER_CST |
5571 | || TREE_INT_CST_LOW (arg0) & ~0x3) | |
5572 | { | |
5573 | error ("argument to dss must be a 2-bit unsigned literal"); | |
9a171fcd | 5574 | return const0_rtx; |
b44140e7 AH |
5575 | } |
5576 | ||
95385cbb AH |
5577 | if (! (*insn_data[icode].operand[0].predicate) (op0, mode0)) |
5578 | op0 = copy_to_mode_reg (mode0, op0); | |
5579 | ||
5580 | emit_insn (gen_altivec_dss (op0)); | |
0ac081f6 AH |
5581 | return NULL_RTX; |
5582 | } | |
24408032 | 5583 | |
100c4561 AH |
5584 | /* Expand abs* operations. */ |
5585 | d = (struct builtin_description *) bdesc_abs; | |
ca7558fc | 5586 | for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++) |
100c4561 AH |
5587 | if (d->code == fcode) |
5588 | return altivec_expand_abs_builtin (d->icode, arglist, target); | |
5589 | ||
ae4b4a02 AH |
5590 | /* Expand the AltiVec predicates. */ |
5591 | dp = (struct builtin_description_predicates *) bdesc_altivec_preds; | |
ca7558fc | 5592 | for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, dp++) |
ae4b4a02 AH |
5593 | if (dp->code == fcode) |
5594 | return altivec_expand_predicate_builtin (dp->icode, dp->opcode, arglist, target); | |
5595 | ||
6525c0e7 AH |
5596 | /* LV* are funky. We initialized them differently. */ |
5597 | switch (fcode) | |
5598 | { | |
5599 | case ALTIVEC_BUILTIN_LVSL: | |
92898235 | 5600 | return rs6000_expand_binop_builtin (CODE_FOR_altivec_lvsl, |
6525c0e7 AH |
5601 | arglist, target); |
5602 | case ALTIVEC_BUILTIN_LVSR: | |
92898235 AH |
5603 | return rs6000_expand_binop_builtin (CODE_FOR_altivec_lvsr, |
5604 | arglist, target); | |
6525c0e7 | 5605 | case ALTIVEC_BUILTIN_LVEBX: |
92898235 AH |
5606 | return rs6000_expand_binop_builtin (CODE_FOR_altivec_lvebx, |
5607 | arglist, target); | |
6525c0e7 | 5608 | case ALTIVEC_BUILTIN_LVEHX: |
92898235 AH |
5609 | return rs6000_expand_binop_builtin (CODE_FOR_altivec_lvehx, |
5610 | arglist, target); | |
6525c0e7 | 5611 | case ALTIVEC_BUILTIN_LVEWX: |
92898235 AH |
5612 | return rs6000_expand_binop_builtin (CODE_FOR_altivec_lvewx, |
5613 | arglist, target); | |
6525c0e7 | 5614 | case ALTIVEC_BUILTIN_LVXL: |
92898235 AH |
5615 | return rs6000_expand_binop_builtin (CODE_FOR_altivec_lvxl, |
5616 | arglist, target); | |
6525c0e7 | 5617 | case ALTIVEC_BUILTIN_LVX: |
92898235 AH |
5618 | return rs6000_expand_binop_builtin (CODE_FOR_altivec_lvx, |
5619 | arglist, target); | |
6525c0e7 AH |
5620 | default: |
5621 | break; | |
5622 | /* Fall through. */ | |
5623 | } | |
95385cbb | 5624 | |
92898235 | 5625 | *expandedp = false; |
0ac081f6 AH |
5626 | return NULL_RTX; |
5627 | } | |
5628 | ||
a3170dc6 AH |
5629 | /* Binops that need to be initialized manually, but can be expanded |
5630 | automagically by rs6000_expand_binop_builtin. */ | |
5631 | static struct builtin_description bdesc_2arg_spe[] = | |
5632 | { | |
5633 | { 0, CODE_FOR_spe_evlddx, "__builtin_spe_evlddx", SPE_BUILTIN_EVLDDX }, | |
5634 | { 0, CODE_FOR_spe_evldwx, "__builtin_spe_evldwx", SPE_BUILTIN_EVLDWX }, | |
5635 | { 0, CODE_FOR_spe_evldhx, "__builtin_spe_evldhx", SPE_BUILTIN_EVLDHX }, | |
5636 | { 0, CODE_FOR_spe_evlwhex, "__builtin_spe_evlwhex", SPE_BUILTIN_EVLWHEX }, | |
5637 | { 0, CODE_FOR_spe_evlwhoux, "__builtin_spe_evlwhoux", SPE_BUILTIN_EVLWHOUX }, | |
5638 | { 0, CODE_FOR_spe_evlwhosx, "__builtin_spe_evlwhosx", SPE_BUILTIN_EVLWHOSX }, | |
5639 | { 0, CODE_FOR_spe_evlwwsplatx, "__builtin_spe_evlwwsplatx", SPE_BUILTIN_EVLWWSPLATX }, | |
5640 | { 0, CODE_FOR_spe_evlwhsplatx, "__builtin_spe_evlwhsplatx", SPE_BUILTIN_EVLWHSPLATX }, | |
5641 | { 0, CODE_FOR_spe_evlhhesplatx, "__builtin_spe_evlhhesplatx", SPE_BUILTIN_EVLHHESPLATX }, | |
5642 | { 0, CODE_FOR_spe_evlhhousplatx, "__builtin_spe_evlhhousplatx", SPE_BUILTIN_EVLHHOUSPLATX }, | |
5643 | { 0, CODE_FOR_spe_evlhhossplatx, "__builtin_spe_evlhhossplatx", SPE_BUILTIN_EVLHHOSSPLATX }, | |
5644 | { 0, CODE_FOR_spe_evldd, "__builtin_spe_evldd", SPE_BUILTIN_EVLDD }, | |
5645 | { 0, CODE_FOR_spe_evldw, "__builtin_spe_evldw", SPE_BUILTIN_EVLDW }, | |
5646 | { 0, CODE_FOR_spe_evldh, "__builtin_spe_evldh", SPE_BUILTIN_EVLDH }, | |
5647 | { 0, CODE_FOR_spe_evlwhe, "__builtin_spe_evlwhe", SPE_BUILTIN_EVLWHE }, | |
5648 | { 0, CODE_FOR_spe_evlwhou, "__builtin_spe_evlwhou", SPE_BUILTIN_EVLWHOU }, | |
5649 | { 0, CODE_FOR_spe_evlwhos, "__builtin_spe_evlwhos", SPE_BUILTIN_EVLWHOS }, | |
5650 | { 0, CODE_FOR_spe_evlwwsplat, "__builtin_spe_evlwwsplat", SPE_BUILTIN_EVLWWSPLAT }, | |
5651 | { 0, CODE_FOR_spe_evlwhsplat, "__builtin_spe_evlwhsplat", SPE_BUILTIN_EVLWHSPLAT }, | |
5652 | { 0, CODE_FOR_spe_evlhhesplat, "__builtin_spe_evlhhesplat", SPE_BUILTIN_EVLHHESPLAT }, | |
5653 | { 0, CODE_FOR_spe_evlhhousplat, "__builtin_spe_evlhhousplat", SPE_BUILTIN_EVLHHOUSPLAT }, | |
5654 | { 0, CODE_FOR_spe_evlhhossplat, "__builtin_spe_evlhhossplat", SPE_BUILTIN_EVLHHOSSPLAT } | |
5655 | }; | |
5656 | ||
5657 | /* Expand the builtin in EXP and store the result in TARGET. Store | |
5658 | true in *EXPANDEDP if we found a builtin to expand. | |
5659 | ||
5660 | This expands the SPE builtins that are not simple unary and binary | |
5661 | operations. */ | |
5662 | static rtx | |
5663 | spe_expand_builtin (exp, target, expandedp) | |
5664 | tree exp; | |
5665 | rtx target; | |
5666 | bool *expandedp; | |
5667 | { | |
5668 | tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0); | |
5669 | tree arglist = TREE_OPERAND (exp, 1); | |
5670 | tree arg1, arg0; | |
5671 | unsigned int fcode = DECL_FUNCTION_CODE (fndecl); | |
5672 | enum insn_code icode; | |
5673 | enum machine_mode tmode, mode0; | |
5674 | rtx pat, op0; | |
5675 | struct builtin_description *d; | |
5676 | size_t i; | |
5677 | ||
5678 | *expandedp = true; | |
5679 | ||
5680 | /* Syntax check for a 5-bit unsigned immediate. */ | |
5681 | switch (fcode) | |
5682 | { | |
5683 | case SPE_BUILTIN_EVSTDD: | |
5684 | case SPE_BUILTIN_EVSTDH: | |
5685 | case SPE_BUILTIN_EVSTDW: | |
5686 | case SPE_BUILTIN_EVSTWHE: | |
5687 | case SPE_BUILTIN_EVSTWHO: | |
5688 | case SPE_BUILTIN_EVSTWWE: | |
5689 | case SPE_BUILTIN_EVSTWWO: | |
5690 | arg1 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist))); | |
5691 | if (TREE_CODE (arg1) != INTEGER_CST | |
5692 | || TREE_INT_CST_LOW (arg1) & ~0x1f) | |
5693 | { | |
5694 | error ("argument 2 must be a 5-bit unsigned literal"); | |
5695 | return const0_rtx; | |
5696 | } | |
5697 | break; | |
5698 | default: | |
5699 | break; | |
5700 | } | |
5701 | ||
5702 | d = (struct builtin_description *) bdesc_2arg_spe; | |
5703 | for (i = 0; i < ARRAY_SIZE (bdesc_2arg_spe); ++i, ++d) | |
5704 | if (d->code == fcode) | |
5705 | return rs6000_expand_binop_builtin (d->icode, arglist, target); | |
5706 | ||
5707 | d = (struct builtin_description *) bdesc_spe_predicates; | |
5708 | for (i = 0; i < ARRAY_SIZE (bdesc_spe_predicates); ++i, ++d) | |
5709 | if (d->code == fcode) | |
5710 | return spe_expand_predicate_builtin (d->icode, arglist, target); | |
5711 | ||
5712 | d = (struct builtin_description *) bdesc_spe_evsel; | |
5713 | for (i = 0; i < ARRAY_SIZE (bdesc_spe_evsel); ++i, ++d) | |
5714 | if (d->code == fcode) | |
5715 | return spe_expand_evsel_builtin (d->icode, arglist, target); | |
5716 | ||
5717 | switch (fcode) | |
5718 | { | |
5719 | case SPE_BUILTIN_EVSTDDX: | |
5720 | return altivec_expand_stv_builtin (CODE_FOR_spe_evstddx, arglist); | |
5721 | case SPE_BUILTIN_EVSTDHX: | |
5722 | return altivec_expand_stv_builtin (CODE_FOR_spe_evstdhx, arglist); | |
5723 | case SPE_BUILTIN_EVSTDWX: | |
5724 | return altivec_expand_stv_builtin (CODE_FOR_spe_evstdwx, arglist); | |
5725 | case SPE_BUILTIN_EVSTWHEX: | |
5726 | return altivec_expand_stv_builtin (CODE_FOR_spe_evstwhex, arglist); | |
5727 | case SPE_BUILTIN_EVSTWHOX: | |
5728 | return altivec_expand_stv_builtin (CODE_FOR_spe_evstwhox, arglist); | |
5729 | case SPE_BUILTIN_EVSTWWEX: | |
5730 | return altivec_expand_stv_builtin (CODE_FOR_spe_evstwwex, arglist); | |
5731 | case SPE_BUILTIN_EVSTWWOX: | |
5732 | return altivec_expand_stv_builtin (CODE_FOR_spe_evstwwox, arglist); | |
5733 | case SPE_BUILTIN_EVSTDD: | |
5734 | return altivec_expand_stv_builtin (CODE_FOR_spe_evstdd, arglist); | |
5735 | case SPE_BUILTIN_EVSTDH: | |
5736 | return altivec_expand_stv_builtin (CODE_FOR_spe_evstdh, arglist); | |
5737 | case SPE_BUILTIN_EVSTDW: | |
5738 | return altivec_expand_stv_builtin (CODE_FOR_spe_evstdw, arglist); | |
5739 | case SPE_BUILTIN_EVSTWHE: | |
5740 | return altivec_expand_stv_builtin (CODE_FOR_spe_evstwhe, arglist); | |
5741 | case SPE_BUILTIN_EVSTWHO: | |
5742 | return altivec_expand_stv_builtin (CODE_FOR_spe_evstwho, arglist); | |
5743 | case SPE_BUILTIN_EVSTWWE: | |
5744 | return altivec_expand_stv_builtin (CODE_FOR_spe_evstwwe, arglist); | |
5745 | case SPE_BUILTIN_EVSTWWO: | |
5746 | return altivec_expand_stv_builtin (CODE_FOR_spe_evstwwo, arglist); | |
5747 | case SPE_BUILTIN_MFSPEFSCR: | |
5748 | icode = CODE_FOR_spe_mfspefscr; | |
5749 | tmode = insn_data[icode].operand[0].mode; | |
5750 | ||
5751 | if (target == 0 | |
5752 | || GET_MODE (target) != tmode | |
5753 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
5754 | target = gen_reg_rtx (tmode); | |
5755 | ||
5756 | pat = GEN_FCN (icode) (target); | |
5757 | if (! pat) | |
5758 | return 0; | |
5759 | emit_insn (pat); | |
5760 | return target; | |
5761 | case SPE_BUILTIN_MTSPEFSCR: | |
5762 | icode = CODE_FOR_spe_mtspefscr; | |
5763 | arg0 = TREE_VALUE (arglist); | |
5764 | op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
5765 | mode0 = insn_data[icode].operand[0].mode; | |
5766 | ||
5767 | if (arg0 == error_mark_node) | |
5768 | return const0_rtx; | |
5769 | ||
5770 | if (! (*insn_data[icode].operand[0].predicate) (op0, mode0)) | |
5771 | op0 = copy_to_mode_reg (mode0, op0); | |
5772 | ||
5773 | pat = GEN_FCN (icode) (op0); | |
5774 | if (pat) | |
5775 | emit_insn (pat); | |
5776 | return NULL_RTX; | |
5777 | default: | |
5778 | break; | |
5779 | } | |
5780 | ||
5781 | *expandedp = false; | |
5782 | return NULL_RTX; | |
5783 | } | |
5784 | ||
5785 | static rtx | |
5786 | spe_expand_predicate_builtin (icode, arglist, target) | |
5787 | enum insn_code icode; | |
5788 | tree arglist; | |
5789 | rtx target; | |
5790 | { | |
5791 | rtx pat, scratch, tmp; | |
5792 | tree form = TREE_VALUE (arglist); | |
5793 | tree arg0 = TREE_VALUE (TREE_CHAIN (arglist)); | |
5794 | tree arg1 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist))); | |
5795 | rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
5796 | rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); | |
5797 | enum machine_mode mode0 = insn_data[icode].operand[1].mode; | |
5798 | enum machine_mode mode1 = insn_data[icode].operand[2].mode; | |
5799 | int form_int; | |
5800 | enum rtx_code code; | |
5801 | ||
5802 | if (TREE_CODE (form) != INTEGER_CST) | |
5803 | { | |
5804 | error ("argument 1 of __builtin_spe_predicate must be a constant"); | |
5805 | return const0_rtx; | |
5806 | } | |
5807 | else | |
5808 | form_int = TREE_INT_CST_LOW (form); | |
5809 | ||
5810 | if (mode0 != mode1) | |
5811 | abort (); | |
5812 | ||
5813 | if (arg0 == error_mark_node || arg1 == error_mark_node) | |
5814 | return const0_rtx; | |
5815 | ||
5816 | if (target == 0 | |
5817 | || GET_MODE (target) != SImode | |
5818 | || ! (*insn_data[icode].operand[0].predicate) (target, SImode)) | |
5819 | target = gen_reg_rtx (SImode); | |
5820 | ||
5821 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) | |
5822 | op0 = copy_to_mode_reg (mode0, op0); | |
5823 | if (! (*insn_data[icode].operand[2].predicate) (op1, mode1)) | |
5824 | op1 = copy_to_mode_reg (mode1, op1); | |
5825 | ||
5826 | scratch = gen_reg_rtx (CCmode); | |
5827 | ||
5828 | pat = GEN_FCN (icode) (scratch, op0, op1); | |
5829 | if (! pat) | |
5830 | return const0_rtx; | |
5831 | emit_insn (pat); | |
5832 | ||
5833 | /* There are 4 variants for each predicate: _any_, _all_, _upper_, | |
5834 | _lower_. We use one compare, but look in different bits of the | |
5835 | CR for each variant. | |
5836 | ||
5837 | There are 2 elements in each SPE simd type (upper/lower). The CR | |
5838 | bits are set as follows: | |
5839 | ||
5840 | BIT0 | BIT 1 | BIT 2 | BIT 3 | |
5841 | U | L | (U | L) | (U & L) | |
5842 | ||
5843 | So, for an "all" relationship, BIT 3 would be set. | |
5844 | For an "any" relationship, BIT 2 would be set. Etc. | |
5845 | ||
5846 | Following traditional nomenclature, these bits map to: | |
5847 | ||
5848 | BIT0 | BIT 1 | BIT 2 | BIT 3 | |
5849 | LT | GT | EQ | OV | |
5850 | ||
5851 | Later, we will generate rtl to look in the LT/EQ/EQ/OV bits. | |
5852 | */ | |
5853 | ||
5854 | switch (form_int) | |
5855 | { | |
5856 | /* All variant. OV bit. */ | |
5857 | case 0: | |
5858 | /* We need to get to the OV bit, which is the ORDERED bit. We | |
5859 | could generate (ordered:SI (reg:CC xx) (const_int 0)), but | |
5860 | that's ugly and will trigger a validate_condition_mode abort. | |
5861 | So let's just use another pattern. */ | |
5862 | emit_insn (gen_move_from_CR_ov_bit (target, scratch)); | |
5863 | return target; | |
5864 | /* Any variant. EQ bit. */ | |
5865 | case 1: | |
5866 | code = EQ; | |
5867 | break; | |
5868 | /* Upper variant. LT bit. */ | |
5869 | case 2: | |
5870 | code = LT; | |
5871 | break; | |
5872 | /* Lower variant. GT bit. */ | |
5873 | case 3: | |
5874 | code = GT; | |
5875 | break; | |
5876 | default: | |
5877 | error ("argument 1 of __builtin_spe_predicate is out of range"); | |
5878 | return const0_rtx; | |
5879 | } | |
5880 | ||
5881 | tmp = gen_rtx_fmt_ee (code, SImode, scratch, const0_rtx); | |
5882 | emit_move_insn (target, tmp); | |
5883 | ||
5884 | return target; | |
5885 | } | |
5886 | ||
5887 | /* The evsel builtins look like this: | |
5888 | ||
5889 | e = __builtin_spe_evsel_OP (a, b, c, d); | |
5890 | ||
5891 | and work like this: | |
5892 | ||
5893 | e[upper] = a[upper] *OP* b[upper] ? c[upper] : d[upper]; | |
5894 | e[lower] = a[lower] *OP* b[lower] ? c[lower] : d[lower]; | |
5895 | */ | |
5896 | ||
5897 | static rtx | |
5898 | spe_expand_evsel_builtin (icode, arglist, target) | |
5899 | enum insn_code icode; | |
5900 | tree arglist; | |
5901 | rtx target; | |
5902 | { | |
5903 | rtx pat, scratch; | |
5904 | tree arg0 = TREE_VALUE (arglist); | |
5905 | tree arg1 = TREE_VALUE (TREE_CHAIN (arglist)); | |
5906 | tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist))); | |
5907 | tree arg3 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (TREE_CHAIN (arglist)))); | |
5908 | rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
5909 | rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); | |
5910 | rtx op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0); | |
5911 | rtx op3 = expand_expr (arg3, NULL_RTX, VOIDmode, 0); | |
5912 | enum machine_mode mode0 = insn_data[icode].operand[1].mode; | |
5913 | enum machine_mode mode1 = insn_data[icode].operand[2].mode; | |
5914 | ||
5915 | if (mode0 != mode1) | |
5916 | abort (); | |
5917 | ||
5918 | if (arg0 == error_mark_node || arg1 == error_mark_node | |
5919 | || arg2 == error_mark_node || arg3 == error_mark_node) | |
5920 | return const0_rtx; | |
5921 | ||
5922 | if (target == 0 | |
5923 | || GET_MODE (target) != mode0 | |
5924 | || ! (*insn_data[icode].operand[0].predicate) (target, mode0)) | |
5925 | target = gen_reg_rtx (mode0); | |
5926 | ||
5927 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) | |
5928 | op0 = copy_to_mode_reg (mode0, op0); | |
5929 | if (! (*insn_data[icode].operand[1].predicate) (op1, mode1)) | |
5930 | op1 = copy_to_mode_reg (mode0, op1); | |
5931 | if (! (*insn_data[icode].operand[1].predicate) (op2, mode1)) | |
5932 | op2 = copy_to_mode_reg (mode0, op2); | |
5933 | if (! (*insn_data[icode].operand[1].predicate) (op3, mode1)) | |
5934 | op3 = copy_to_mode_reg (mode0, op3); | |
5935 | ||
5936 | /* Generate the compare. */ | |
5937 | scratch = gen_reg_rtx (CCmode); | |
5938 | pat = GEN_FCN (icode) (scratch, op0, op1); | |
5939 | if (! pat) | |
5940 | return const0_rtx; | |
5941 | emit_insn (pat); | |
5942 | ||
5943 | if (mode0 == V2SImode) | |
5944 | emit_insn (gen_spe_evsel (target, op2, op3, scratch)); | |
5945 | else | |
5946 | emit_insn (gen_spe_evsel_fs (target, op2, op3, scratch)); | |
5947 | ||
5948 | return target; | |
5949 | } | |
5950 | ||
0ac081f6 AH |
5951 | /* Expand an expression EXP that calls a built-in function, |
5952 | with result going to TARGET if that's convenient | |
5953 | (and in mode MODE if that's convenient). | |
5954 | SUBTARGET may be used as the target for computing one of EXP's operands. | |
5955 | IGNORE is nonzero if the value is to be ignored. */ | |
5956 | ||
5957 | static rtx | |
5958 | rs6000_expand_builtin (exp, target, subtarget, mode, ignore) | |
5959 | tree exp; | |
5960 | rtx target; | |
00b960c7 AH |
5961 | rtx subtarget ATTRIBUTE_UNUSED; |
5962 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
5963 | int ignore ATTRIBUTE_UNUSED; | |
0ac081f6 | 5964 | { |
92898235 AH |
5965 | tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0); |
5966 | tree arglist = TREE_OPERAND (exp, 1); | |
5967 | unsigned int fcode = DECL_FUNCTION_CODE (fndecl); | |
5968 | struct builtin_description *d; | |
5969 | size_t i; | |
5970 | rtx ret; | |
5971 | bool success; | |
5972 | ||
0ac081f6 | 5973 | if (TARGET_ALTIVEC) |
92898235 AH |
5974 | { |
5975 | ret = altivec_expand_builtin (exp, target, &success); | |
5976 | ||
a3170dc6 AH |
5977 | if (success) |
5978 | return ret; | |
5979 | } | |
5980 | if (TARGET_SPE) | |
5981 | { | |
5982 | ret = spe_expand_builtin (exp, target, &success); | |
5983 | ||
92898235 AH |
5984 | if (success) |
5985 | return ret; | |
5986 | } | |
5987 | ||
0559cc77 DE |
5988 | if (TARGET_ALTIVEC || TARGET_SPE) |
5989 | { | |
5990 | /* Handle simple unary operations. */ | |
5991 | d = (struct builtin_description *) bdesc_1arg; | |
5992 | for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++) | |
5993 | if (d->code == fcode) | |
5994 | return rs6000_expand_unop_builtin (d->icode, arglist, target); | |
5995 | ||
5996 | /* Handle simple binary operations. */ | |
5997 | d = (struct builtin_description *) bdesc_2arg; | |
5998 | for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++) | |
5999 | if (d->code == fcode) | |
6000 | return rs6000_expand_binop_builtin (d->icode, arglist, target); | |
6001 | ||
6002 | /* Handle simple ternary operations. */ | |
6003 | d = (struct builtin_description *) bdesc_3arg; | |
6004 | for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++) | |
6005 | if (d->code == fcode) | |
6006 | return rs6000_expand_ternop_builtin (d->icode, arglist, target); | |
6007 | } | |
0ac081f6 AH |
6008 | |
6009 | abort (); | |
92898235 | 6010 | return NULL_RTX; |
0ac081f6 AH |
6011 | } |
6012 | ||
6013 | static void | |
6fa3f289 | 6014 | rs6000_init_builtins () |
0ac081f6 | 6015 | { |
3fdaa45a AH |
6016 | opaque_V2SI_type_node = copy_node (V2SI_type_node); |
6017 | opaque_V2SF_type_node = copy_node (V2SF_type_node); | |
6035d635 | 6018 | opaque_p_V2SI_type_node = build_pointer_type (opaque_V2SI_type_node); |
3fdaa45a | 6019 | |
a3170dc6 | 6020 | if (TARGET_SPE) |
3fdaa45a | 6021 | spe_init_builtins (); |
0ac081f6 AH |
6022 | if (TARGET_ALTIVEC) |
6023 | altivec_init_builtins (); | |
0559cc77 DE |
6024 | if (TARGET_ALTIVEC || TARGET_SPE) |
6025 | rs6000_common_init_builtins (); | |
0ac081f6 AH |
6026 | } |
6027 | ||
a3170dc6 AH |
6028 | /* Search through a set of builtins and enable the mask bits. |
6029 | DESC is an array of builtins. | |
b6d08ca1 | 6030 | SIZE is the total number of builtins. |
a3170dc6 AH |
6031 | START is the builtin enum at which to start. |
6032 | END is the builtin enum at which to end. */ | |
0ac081f6 | 6033 | static void |
a3170dc6 AH |
6034 | enable_mask_for_builtins (desc, size, start, end) |
6035 | struct builtin_description *desc; | |
6036 | int size; | |
6037 | enum rs6000_builtins start, end; | |
6038 | { | |
6039 | int i; | |
6040 | ||
6041 | for (i = 0; i < size; ++i) | |
6042 | if (desc[i].code == start) | |
6043 | break; | |
6044 | ||
6045 | if (i == size) | |
6046 | return; | |
6047 | ||
6048 | for (; i < size; ++i) | |
6049 | { | |
6050 | /* Flip all the bits on. */ | |
6051 | desc[i].mask = target_flags; | |
6052 | if (desc[i].code == end) | |
6053 | break; | |
6054 | } | |
6055 | } | |
6056 | ||
6057 | static void | |
b24c9d35 | 6058 | spe_init_builtins () |
0ac081f6 | 6059 | { |
a3170dc6 AH |
6060 | tree endlink = void_list_node; |
6061 | tree puint_type_node = build_pointer_type (unsigned_type_node); | |
6062 | tree pushort_type_node = build_pointer_type (short_unsigned_type_node); | |
ae4b4a02 | 6063 | struct builtin_description *d; |
0ac081f6 AH |
6064 | size_t i; |
6065 | ||
a3170dc6 AH |
6066 | tree v2si_ftype_4_v2si |
6067 | = build_function_type | |
3fdaa45a AH |
6068 | (opaque_V2SI_type_node, |
6069 | tree_cons (NULL_TREE, opaque_V2SI_type_node, | |
6070 | tree_cons (NULL_TREE, opaque_V2SI_type_node, | |
6071 | tree_cons (NULL_TREE, opaque_V2SI_type_node, | |
6072 | tree_cons (NULL_TREE, opaque_V2SI_type_node, | |
a3170dc6 AH |
6073 | endlink))))); |
6074 | ||
6075 | tree v2sf_ftype_4_v2sf | |
6076 | = build_function_type | |
3fdaa45a AH |
6077 | (opaque_V2SF_type_node, |
6078 | tree_cons (NULL_TREE, opaque_V2SF_type_node, | |
6079 | tree_cons (NULL_TREE, opaque_V2SF_type_node, | |
6080 | tree_cons (NULL_TREE, opaque_V2SF_type_node, | |
6081 | tree_cons (NULL_TREE, opaque_V2SF_type_node, | |
a3170dc6 AH |
6082 | endlink))))); |
6083 | ||
6084 | tree int_ftype_int_v2si_v2si | |
6085 | = build_function_type | |
6086 | (integer_type_node, | |
6087 | tree_cons (NULL_TREE, integer_type_node, | |
3fdaa45a AH |
6088 | tree_cons (NULL_TREE, opaque_V2SI_type_node, |
6089 | tree_cons (NULL_TREE, opaque_V2SI_type_node, | |
a3170dc6 AH |
6090 | endlink)))); |
6091 | ||
6092 | tree int_ftype_int_v2sf_v2sf | |
6093 | = build_function_type | |
6094 | (integer_type_node, | |
6095 | tree_cons (NULL_TREE, integer_type_node, | |
3fdaa45a AH |
6096 | tree_cons (NULL_TREE, opaque_V2SF_type_node, |
6097 | tree_cons (NULL_TREE, opaque_V2SF_type_node, | |
a3170dc6 AH |
6098 | endlink)))); |
6099 | ||
6100 | tree void_ftype_v2si_puint_int | |
6101 | = build_function_type (void_type_node, | |
3fdaa45a | 6102 | tree_cons (NULL_TREE, opaque_V2SI_type_node, |
a3170dc6 AH |
6103 | tree_cons (NULL_TREE, puint_type_node, |
6104 | tree_cons (NULL_TREE, | |
6105 | integer_type_node, | |
6106 | endlink)))); | |
6107 | ||
6108 | tree void_ftype_v2si_puint_char | |
6109 | = build_function_type (void_type_node, | |
3fdaa45a | 6110 | tree_cons (NULL_TREE, opaque_V2SI_type_node, |
a3170dc6 AH |
6111 | tree_cons (NULL_TREE, puint_type_node, |
6112 | tree_cons (NULL_TREE, | |
6113 | char_type_node, | |
6114 | endlink)))); | |
6115 | ||
6116 | tree void_ftype_v2si_pv2si_int | |
6117 | = build_function_type (void_type_node, | |
3fdaa45a | 6118 | tree_cons (NULL_TREE, opaque_V2SI_type_node, |
6035d635 | 6119 | tree_cons (NULL_TREE, opaque_p_V2SI_type_node, |
a3170dc6 AH |
6120 | tree_cons (NULL_TREE, |
6121 | integer_type_node, | |
6122 | endlink)))); | |
6123 | ||
6124 | tree void_ftype_v2si_pv2si_char | |
6125 | = build_function_type (void_type_node, | |
3fdaa45a | 6126 | tree_cons (NULL_TREE, opaque_V2SI_type_node, |
6035d635 | 6127 | tree_cons (NULL_TREE, opaque_p_V2SI_type_node, |
a3170dc6 AH |
6128 | tree_cons (NULL_TREE, |
6129 | char_type_node, | |
6130 | endlink)))); | |
6131 | ||
6132 | tree void_ftype_int | |
6133 | = build_function_type (void_type_node, | |
6134 | tree_cons (NULL_TREE, integer_type_node, endlink)); | |
6135 | ||
6136 | tree int_ftype_void | |
36e8d515 | 6137 | = build_function_type (integer_type_node, endlink); |
a3170dc6 AH |
6138 | |
6139 | tree v2si_ftype_pv2si_int | |
3fdaa45a | 6140 | = build_function_type (opaque_V2SI_type_node, |
6035d635 | 6141 | tree_cons (NULL_TREE, opaque_p_V2SI_type_node, |
a3170dc6 AH |
6142 | tree_cons (NULL_TREE, integer_type_node, |
6143 | endlink))); | |
6144 | ||
6145 | tree v2si_ftype_puint_int | |
3fdaa45a | 6146 | = build_function_type (opaque_V2SI_type_node, |
a3170dc6 AH |
6147 | tree_cons (NULL_TREE, puint_type_node, |
6148 | tree_cons (NULL_TREE, integer_type_node, | |
6149 | endlink))); | |
6150 | ||
6151 | tree v2si_ftype_pushort_int | |
3fdaa45a | 6152 | = build_function_type (opaque_V2SI_type_node, |
a3170dc6 AH |
6153 | tree_cons (NULL_TREE, pushort_type_node, |
6154 | tree_cons (NULL_TREE, integer_type_node, | |
6155 | endlink))); | |
6156 | ||
6157 | /* The initialization of the simple binary and unary builtins is | |
6158 | done in rs6000_common_init_builtins, but we have to enable the | |
6159 | mask bits here manually because we have run out of `target_flags' | |
6160 | bits. We really need to redesign this mask business. */ | |
6161 | ||
6162 | enable_mask_for_builtins ((struct builtin_description *) bdesc_2arg, | |
6163 | ARRAY_SIZE (bdesc_2arg), | |
6164 | SPE_BUILTIN_EVADDW, | |
6165 | SPE_BUILTIN_EVXOR); | |
6166 | enable_mask_for_builtins ((struct builtin_description *) bdesc_1arg, | |
6167 | ARRAY_SIZE (bdesc_1arg), | |
6168 | SPE_BUILTIN_EVABS, | |
6169 | SPE_BUILTIN_EVSUBFUSIAAW); | |
6170 | enable_mask_for_builtins ((struct builtin_description *) bdesc_spe_predicates, | |
6171 | ARRAY_SIZE (bdesc_spe_predicates), | |
6172 | SPE_BUILTIN_EVCMPEQ, | |
6173 | SPE_BUILTIN_EVFSTSTLT); | |
6174 | enable_mask_for_builtins ((struct builtin_description *) bdesc_spe_evsel, | |
6175 | ARRAY_SIZE (bdesc_spe_evsel), | |
6176 | SPE_BUILTIN_EVSEL_CMPGTS, | |
6177 | SPE_BUILTIN_EVSEL_FSTSTEQ); | |
6178 | ||
6179 | /* Initialize irregular SPE builtins. */ | |
6180 | ||
6181 | def_builtin (target_flags, "__builtin_spe_mtspefscr", void_ftype_int, SPE_BUILTIN_MTSPEFSCR); | |
6182 | def_builtin (target_flags, "__builtin_spe_mfspefscr", int_ftype_void, SPE_BUILTIN_MFSPEFSCR); | |
6183 | def_builtin (target_flags, "__builtin_spe_evstddx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDDX); | |
6184 | def_builtin (target_flags, "__builtin_spe_evstdhx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDHX); | |
6185 | def_builtin (target_flags, "__builtin_spe_evstdwx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDWX); | |
6186 | def_builtin (target_flags, "__builtin_spe_evstwhex", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWHEX); | |
6187 | def_builtin (target_flags, "__builtin_spe_evstwhox", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWHOX); | |
6188 | def_builtin (target_flags, "__builtin_spe_evstwwex", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWWEX); | |
6189 | def_builtin (target_flags, "__builtin_spe_evstwwox", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWWOX); | |
6190 | def_builtin (target_flags, "__builtin_spe_evstdd", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDD); | |
6191 | def_builtin (target_flags, "__builtin_spe_evstdh", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDH); | |
6192 | def_builtin (target_flags, "__builtin_spe_evstdw", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDW); | |
6193 | def_builtin (target_flags, "__builtin_spe_evstwhe", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWHE); | |
6194 | def_builtin (target_flags, "__builtin_spe_evstwho", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWHO); | |
6195 | def_builtin (target_flags, "__builtin_spe_evstwwe", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWWE); | |
6196 | def_builtin (target_flags, "__builtin_spe_evstwwo", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWWO); | |
6197 | ||
6198 | /* Loads. */ | |
6199 | def_builtin (target_flags, "__builtin_spe_evlddx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDDX); | |
6200 | def_builtin (target_flags, "__builtin_spe_evldwx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDWX); | |
6201 | def_builtin (target_flags, "__builtin_spe_evldhx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDHX); | |
6202 | def_builtin (target_flags, "__builtin_spe_evlwhex", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHEX); | |
6203 | def_builtin (target_flags, "__builtin_spe_evlwhoux", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOUX); | |
6204 | def_builtin (target_flags, "__builtin_spe_evlwhosx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOSX); | |
6205 | def_builtin (target_flags, "__builtin_spe_evlwwsplatx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWWSPLATX); | |
6206 | def_builtin (target_flags, "__builtin_spe_evlwhsplatx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHSPLATX); | |
6207 | def_builtin (target_flags, "__builtin_spe_evlhhesplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHESPLATX); | |
6208 | def_builtin (target_flags, "__builtin_spe_evlhhousplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOUSPLATX); | |
6209 | def_builtin (target_flags, "__builtin_spe_evlhhossplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOSSPLATX); | |
6210 | def_builtin (target_flags, "__builtin_spe_evldd", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDD); | |
6211 | def_builtin (target_flags, "__builtin_spe_evldw", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDW); | |
6212 | def_builtin (target_flags, "__builtin_spe_evldh", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDH); | |
6213 | def_builtin (target_flags, "__builtin_spe_evlhhesplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHESPLAT); | |
6214 | def_builtin (target_flags, "__builtin_spe_evlhhossplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOSSPLAT); | |
6215 | def_builtin (target_flags, "__builtin_spe_evlhhousplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOUSPLAT); | |
6216 | def_builtin (target_flags, "__builtin_spe_evlwhe", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHE); | |
6217 | def_builtin (target_flags, "__builtin_spe_evlwhos", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOS); | |
6218 | def_builtin (target_flags, "__builtin_spe_evlwhou", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOU); | |
6219 | def_builtin (target_flags, "__builtin_spe_evlwhsplat", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHSPLAT); | |
6220 | def_builtin (target_flags, "__builtin_spe_evlwwsplat", v2si_ftype_puint_int, SPE_BUILTIN_EVLWWSPLAT); | |
6221 | ||
6222 | /* Predicates. */ | |
6223 | d = (struct builtin_description *) bdesc_spe_predicates; | |
6224 | for (i = 0; i < ARRAY_SIZE (bdesc_spe_predicates); ++i, d++) | |
6225 | { | |
6226 | tree type; | |
6227 | ||
6228 | switch (insn_data[d->icode].operand[1].mode) | |
6229 | { | |
6230 | case V2SImode: | |
6231 | type = int_ftype_int_v2si_v2si; | |
6232 | break; | |
6233 | case V2SFmode: | |
6234 | type = int_ftype_int_v2sf_v2sf; | |
6235 | break; | |
6236 | default: | |
6237 | abort (); | |
6238 | } | |
6239 | ||
6240 | def_builtin (d->mask, d->name, type, d->code); | |
6241 | } | |
6242 | ||
6243 | /* Evsel predicates. */ | |
6244 | d = (struct builtin_description *) bdesc_spe_evsel; | |
6245 | for (i = 0; i < ARRAY_SIZE (bdesc_spe_evsel); ++i, d++) | |
6246 | { | |
6247 | tree type; | |
6248 | ||
6249 | switch (insn_data[d->icode].operand[1].mode) | |
6250 | { | |
6251 | case V2SImode: | |
6252 | type = v2si_ftype_4_v2si; | |
6253 | break; | |
6254 | case V2SFmode: | |
6255 | type = v2sf_ftype_4_v2sf; | |
6256 | break; | |
6257 | default: | |
6258 | abort (); | |
6259 | } | |
6260 | ||
6261 | def_builtin (d->mask, d->name, type, d->code); | |
6262 | } | |
6263 | } | |
6264 | ||
6265 | static void | |
b24c9d35 | 6266 | altivec_init_builtins () |
a3170dc6 AH |
6267 | { |
6268 | struct builtin_description *d; | |
6269 | struct builtin_description_predicates *dp; | |
6270 | size_t i; | |
6271 | tree pfloat_type_node = build_pointer_type (float_type_node); | |
6272 | tree pint_type_node = build_pointer_type (integer_type_node); | |
6273 | tree pshort_type_node = build_pointer_type (short_integer_type_node); | |
6274 | tree pchar_type_node = build_pointer_type (char_type_node); | |
6275 | ||
6276 | tree pvoid_type_node = build_pointer_type (void_type_node); | |
6277 | ||
0dbc3651 ZW |
6278 | tree pcfloat_type_node = build_pointer_type (build_qualified_type (float_type_node, TYPE_QUAL_CONST)); |
6279 | tree pcint_type_node = build_pointer_type (build_qualified_type (integer_type_node, TYPE_QUAL_CONST)); | |
6280 | tree pcshort_type_node = build_pointer_type (build_qualified_type (short_integer_type_node, TYPE_QUAL_CONST)); | |
6281 | tree pcchar_type_node = build_pointer_type (build_qualified_type (char_type_node, TYPE_QUAL_CONST)); | |
6282 | ||
6283 | tree pcvoid_type_node = build_pointer_type (build_qualified_type (void_type_node, TYPE_QUAL_CONST)); | |
6284 | ||
a3170dc6 AH |
6285 | tree int_ftype_int_v4si_v4si |
6286 | = build_function_type_list (integer_type_node, | |
6287 | integer_type_node, V4SI_type_node, | |
6288 | V4SI_type_node, NULL_TREE); | |
0dbc3651 ZW |
6289 | tree v4sf_ftype_pcfloat |
6290 | = build_function_type_list (V4SF_type_node, pcfloat_type_node, NULL_TREE); | |
a3170dc6 | 6291 | tree void_ftype_pfloat_v4sf |
b4de2f7d | 6292 | = build_function_type_list (void_type_node, |
a3170dc6 | 6293 | pfloat_type_node, V4SF_type_node, NULL_TREE); |
0dbc3651 ZW |
6294 | tree v4si_ftype_pcint |
6295 | = build_function_type_list (V4SI_type_node, pcint_type_node, NULL_TREE); | |
6296 | tree void_ftype_pint_v4si | |
b4de2f7d AH |
6297 | = build_function_type_list (void_type_node, |
6298 | pint_type_node, V4SI_type_node, NULL_TREE); | |
0dbc3651 ZW |
6299 | tree v8hi_ftype_pcshort |
6300 | = build_function_type_list (V8HI_type_node, pcshort_type_node, NULL_TREE); | |
f18c054f | 6301 | tree void_ftype_pshort_v8hi |
b4de2f7d AH |
6302 | = build_function_type_list (void_type_node, |
6303 | pshort_type_node, V8HI_type_node, NULL_TREE); | |
0dbc3651 ZW |
6304 | tree v16qi_ftype_pcchar |
6305 | = build_function_type_list (V16QI_type_node, pcchar_type_node, NULL_TREE); | |
f18c054f | 6306 | tree void_ftype_pchar_v16qi |
b4de2f7d AH |
6307 | = build_function_type_list (void_type_node, |
6308 | pchar_type_node, V16QI_type_node, NULL_TREE); | |
95385cbb | 6309 | tree void_ftype_v4si |
b4de2f7d | 6310 | = build_function_type_list (void_type_node, V4SI_type_node, NULL_TREE); |
a3170dc6 AH |
6311 | tree v8hi_ftype_void |
6312 | = build_function_type (V8HI_type_node, void_list_node); | |
6313 | tree void_ftype_void | |
6314 | = build_function_type (void_type_node, void_list_node); | |
6315 | tree void_ftype_qi | |
6316 | = build_function_type_list (void_type_node, char_type_node, NULL_TREE); | |
0dbc3651 ZW |
6317 | |
6318 | tree v16qi_ftype_int_pcvoid | |
a3170dc6 | 6319 | = build_function_type_list (V16QI_type_node, |
0dbc3651 ZW |
6320 | integer_type_node, pcvoid_type_node, NULL_TREE); |
6321 | tree v8hi_ftype_int_pcvoid | |
a3170dc6 | 6322 | = build_function_type_list (V8HI_type_node, |
0dbc3651 ZW |
6323 | integer_type_node, pcvoid_type_node, NULL_TREE); |
6324 | tree v4si_ftype_int_pcvoid | |
a3170dc6 | 6325 | = build_function_type_list (V4SI_type_node, |
0dbc3651 ZW |
6326 | integer_type_node, pcvoid_type_node, NULL_TREE); |
6327 | ||
14b32f4e | 6328 | tree void_ftype_v4si_int_pvoid |
b4de2f7d AH |
6329 | = build_function_type_list (void_type_node, |
6330 | V4SI_type_node, integer_type_node, | |
6331 | pvoid_type_node, NULL_TREE); | |
6525c0e7 | 6332 | tree void_ftype_v16qi_int_pvoid |
b4de2f7d AH |
6333 | = build_function_type_list (void_type_node, |
6334 | V16QI_type_node, integer_type_node, | |
6335 | pvoid_type_node, NULL_TREE); | |
6525c0e7 | 6336 | tree void_ftype_v8hi_int_pvoid |
b4de2f7d AH |
6337 | = build_function_type_list (void_type_node, |
6338 | V8HI_type_node, integer_type_node, | |
6339 | pvoid_type_node, NULL_TREE); | |
a3170dc6 AH |
6340 | tree int_ftype_int_v8hi_v8hi |
6341 | = build_function_type_list (integer_type_node, | |
6342 | integer_type_node, V8HI_type_node, | |
6343 | V8HI_type_node, NULL_TREE); | |
6344 | tree int_ftype_int_v16qi_v16qi | |
6345 | = build_function_type_list (integer_type_node, | |
6346 | integer_type_node, V16QI_type_node, | |
6347 | V16QI_type_node, NULL_TREE); | |
6348 | tree int_ftype_int_v4sf_v4sf | |
6349 | = build_function_type_list (integer_type_node, | |
6350 | integer_type_node, V4SF_type_node, | |
6351 | V4SF_type_node, NULL_TREE); | |
6352 | tree v4si_ftype_v4si | |
6353 | = build_function_type_list (V4SI_type_node, V4SI_type_node, NULL_TREE); | |
6354 | tree v8hi_ftype_v8hi | |
6355 | = build_function_type_list (V8HI_type_node, V8HI_type_node, NULL_TREE); | |
6356 | tree v16qi_ftype_v16qi | |
6357 | = build_function_type_list (V16QI_type_node, V16QI_type_node, NULL_TREE); | |
6358 | tree v4sf_ftype_v4sf | |
6359 | = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE); | |
0dbc3651 | 6360 | tree void_ftype_pcvoid_int_char |
a3170dc6 | 6361 | = build_function_type_list (void_type_node, |
0dbc3651 | 6362 | pcvoid_type_node, integer_type_node, |
a3170dc6 | 6363 | char_type_node, NULL_TREE); |
0dbc3651 ZW |
6364 | |
6365 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_4sf", v4sf_ftype_pcfloat, | |
6366 | ALTIVEC_BUILTIN_LD_INTERNAL_4sf); | |
6367 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_4sf", void_ftype_pfloat_v4sf, | |
6368 | ALTIVEC_BUILTIN_ST_INTERNAL_4sf); | |
6369 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_4si", v4si_ftype_pcint, | |
6370 | ALTIVEC_BUILTIN_LD_INTERNAL_4si); | |
6371 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_4si", void_ftype_pint_v4si, | |
6372 | ALTIVEC_BUILTIN_ST_INTERNAL_4si); | |
6373 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_8hi", v8hi_ftype_pcshort, | |
6374 | ALTIVEC_BUILTIN_LD_INTERNAL_8hi); | |
6375 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_8hi", void_ftype_pshort_v8hi, | |
6376 | ALTIVEC_BUILTIN_ST_INTERNAL_8hi); | |
6377 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_16qi", v16qi_ftype_pcchar, | |
6378 | ALTIVEC_BUILTIN_LD_INTERNAL_16qi); | |
6379 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_16qi", void_ftype_pchar_v16qi, | |
6380 | ALTIVEC_BUILTIN_ST_INTERNAL_16qi); | |
a3170dc6 AH |
6381 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_mtvscr", void_ftype_v4si, ALTIVEC_BUILTIN_MTVSCR); |
6382 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_mfvscr", v8hi_ftype_void, ALTIVEC_BUILTIN_MFVSCR); | |
6383 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_dssall", void_ftype_void, ALTIVEC_BUILTIN_DSSALL); | |
6384 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_dss", void_ftype_qi, ALTIVEC_BUILTIN_DSS); | |
0dbc3651 ZW |
6385 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvsl", v16qi_ftype_int_pcvoid, ALTIVEC_BUILTIN_LVSL); |
6386 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvsr", v16qi_ftype_int_pcvoid, ALTIVEC_BUILTIN_LVSR); | |
6387 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvebx", v16qi_ftype_int_pcvoid, ALTIVEC_BUILTIN_LVEBX); | |
6388 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvehx", v8hi_ftype_int_pcvoid, ALTIVEC_BUILTIN_LVEHX); | |
6389 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvewx", v4si_ftype_int_pcvoid, ALTIVEC_BUILTIN_LVEWX); | |
6390 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvxl", v4si_ftype_int_pcvoid, ALTIVEC_BUILTIN_LVXL); | |
6391 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvx", v4si_ftype_int_pcvoid, ALTIVEC_BUILTIN_LVX); | |
a3170dc6 AH |
6392 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvx", void_ftype_v4si_int_pvoid, ALTIVEC_BUILTIN_STVX); |
6393 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvewx", void_ftype_v4si_int_pvoid, ALTIVEC_BUILTIN_STVEWX); | |
6394 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvxl", void_ftype_v4si_int_pvoid, ALTIVEC_BUILTIN_STVXL); | |
6395 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvebx", void_ftype_v16qi_int_pvoid, ALTIVEC_BUILTIN_STVEBX); | |
6396 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvehx", void_ftype_v8hi_int_pvoid, ALTIVEC_BUILTIN_STVEHX); | |
6397 | ||
6398 | /* Add the DST variants. */ | |
6399 | d = (struct builtin_description *) bdesc_dst; | |
6400 | for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++) | |
0dbc3651 | 6401 | def_builtin (d->mask, d->name, void_ftype_pcvoid_int_char, d->code); |
a3170dc6 AH |
6402 | |
6403 | /* Initialize the predicates. */ | |
6404 | dp = (struct builtin_description_predicates *) bdesc_altivec_preds; | |
6405 | for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, dp++) | |
6406 | { | |
6407 | enum machine_mode mode1; | |
6408 | tree type; | |
6409 | ||
6410 | mode1 = insn_data[dp->icode].operand[1].mode; | |
6411 | ||
6412 | switch (mode1) | |
6413 | { | |
6414 | case V4SImode: | |
6415 | type = int_ftype_int_v4si_v4si; | |
6416 | break; | |
6417 | case V8HImode: | |
6418 | type = int_ftype_int_v8hi_v8hi; | |
6419 | break; | |
6420 | case V16QImode: | |
6421 | type = int_ftype_int_v16qi_v16qi; | |
6422 | break; | |
6423 | case V4SFmode: | |
6424 | type = int_ftype_int_v4sf_v4sf; | |
6425 | break; | |
6426 | default: | |
6427 | abort (); | |
6428 | } | |
6429 | ||
6430 | def_builtin (dp->mask, dp->name, type, dp->code); | |
6431 | } | |
6432 | ||
6433 | /* Initialize the abs* operators. */ | |
6434 | d = (struct builtin_description *) bdesc_abs; | |
6435 | for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++) | |
6436 | { | |
6437 | enum machine_mode mode0; | |
6438 | tree type; | |
6439 | ||
6440 | mode0 = insn_data[d->icode].operand[0].mode; | |
6441 | ||
6442 | switch (mode0) | |
6443 | { | |
6444 | case V4SImode: | |
6445 | type = v4si_ftype_v4si; | |
6446 | break; | |
6447 | case V8HImode: | |
6448 | type = v8hi_ftype_v8hi; | |
6449 | break; | |
6450 | case V16QImode: | |
6451 | type = v16qi_ftype_v16qi; | |
6452 | break; | |
6453 | case V4SFmode: | |
6454 | type = v4sf_ftype_v4sf; | |
6455 | break; | |
6456 | default: | |
6457 | abort (); | |
6458 | } | |
6459 | ||
6460 | def_builtin (d->mask, d->name, type, d->code); | |
6461 | } | |
6462 | } | |
6463 | ||
6464 | static void | |
b24c9d35 | 6465 | rs6000_common_init_builtins () |
a3170dc6 AH |
6466 | { |
6467 | struct builtin_description *d; | |
6468 | size_t i; | |
6469 | ||
6470 | tree v4sf_ftype_v4sf_v4sf_v16qi | |
6471 | = build_function_type_list (V4SF_type_node, | |
6472 | V4SF_type_node, V4SF_type_node, | |
6473 | V16QI_type_node, NULL_TREE); | |
6474 | tree v4si_ftype_v4si_v4si_v16qi | |
6475 | = build_function_type_list (V4SI_type_node, | |
6476 | V4SI_type_node, V4SI_type_node, | |
6477 | V16QI_type_node, NULL_TREE); | |
6478 | tree v8hi_ftype_v8hi_v8hi_v16qi | |
6479 | = build_function_type_list (V8HI_type_node, | |
6480 | V8HI_type_node, V8HI_type_node, | |
6481 | V16QI_type_node, NULL_TREE); | |
6482 | tree v16qi_ftype_v16qi_v16qi_v16qi | |
6483 | = build_function_type_list (V16QI_type_node, | |
6484 | V16QI_type_node, V16QI_type_node, | |
6485 | V16QI_type_node, NULL_TREE); | |
6486 | tree v4si_ftype_char | |
6487 | = build_function_type_list (V4SI_type_node, char_type_node, NULL_TREE); | |
6488 | tree v8hi_ftype_char | |
6489 | = build_function_type_list (V8HI_type_node, char_type_node, NULL_TREE); | |
6490 | tree v16qi_ftype_char | |
6491 | = build_function_type_list (V16QI_type_node, char_type_node, NULL_TREE); | |
6492 | tree v8hi_ftype_v16qi | |
6493 | = build_function_type_list (V8HI_type_node, V16QI_type_node, NULL_TREE); | |
6494 | tree v4sf_ftype_v4sf | |
6495 | = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE); | |
6496 | ||
6497 | tree v2si_ftype_v2si_v2si | |
2abe3e28 AH |
6498 | = build_function_type_list (opaque_V2SI_type_node, |
6499 | opaque_V2SI_type_node, | |
6500 | opaque_V2SI_type_node, NULL_TREE); | |
a3170dc6 AH |
6501 | |
6502 | tree v2sf_ftype_v2sf_v2sf | |
2abe3e28 AH |
6503 | = build_function_type_list (opaque_V2SF_type_node, |
6504 | opaque_V2SF_type_node, | |
6505 | opaque_V2SF_type_node, NULL_TREE); | |
a3170dc6 AH |
6506 | |
6507 | tree v2si_ftype_int_int | |
2abe3e28 | 6508 | = build_function_type_list (opaque_V2SI_type_node, |
a3170dc6 AH |
6509 | integer_type_node, integer_type_node, |
6510 | NULL_TREE); | |
6511 | ||
6512 | tree v2si_ftype_v2si | |
2abe3e28 AH |
6513 | = build_function_type_list (opaque_V2SI_type_node, |
6514 | opaque_V2SI_type_node, NULL_TREE); | |
a3170dc6 AH |
6515 | |
6516 | tree v2sf_ftype_v2sf | |
2abe3e28 AH |
6517 | = build_function_type_list (opaque_V2SF_type_node, |
6518 | opaque_V2SF_type_node, NULL_TREE); | |
a3170dc6 AH |
6519 | |
6520 | tree v2sf_ftype_v2si | |
2abe3e28 AH |
6521 | = build_function_type_list (opaque_V2SF_type_node, |
6522 | opaque_V2SI_type_node, NULL_TREE); | |
a3170dc6 AH |
6523 | |
6524 | tree v2si_ftype_v2sf | |
2abe3e28 AH |
6525 | = build_function_type_list (opaque_V2SI_type_node, |
6526 | opaque_V2SF_type_node, NULL_TREE); | |
a3170dc6 AH |
6527 | |
6528 | tree v2si_ftype_v2si_char | |
2abe3e28 AH |
6529 | = build_function_type_list (opaque_V2SI_type_node, |
6530 | opaque_V2SI_type_node, | |
6531 | char_type_node, NULL_TREE); | |
a3170dc6 AH |
6532 | |
6533 | tree v2si_ftype_int_char | |
2abe3e28 | 6534 | = build_function_type_list (opaque_V2SI_type_node, |
a3170dc6 AH |
6535 | integer_type_node, char_type_node, NULL_TREE); |
6536 | ||
6537 | tree v2si_ftype_char | |
2abe3e28 AH |
6538 | = build_function_type_list (opaque_V2SI_type_node, |
6539 | char_type_node, NULL_TREE); | |
a3170dc6 AH |
6540 | |
6541 | tree int_ftype_int_int | |
6542 | = build_function_type_list (integer_type_node, | |
6543 | integer_type_node, integer_type_node, | |
6544 | NULL_TREE); | |
95385cbb | 6545 | |
0ac081f6 | 6546 | tree v4si_ftype_v4si_v4si |
b4de2f7d AH |
6547 | = build_function_type_list (V4SI_type_node, |
6548 | V4SI_type_node, V4SI_type_node, NULL_TREE); | |
617e0e1d | 6549 | tree v4sf_ftype_v4si_char |
b4de2f7d AH |
6550 | = build_function_type_list (V4SF_type_node, |
6551 | V4SI_type_node, char_type_node, NULL_TREE); | |
617e0e1d | 6552 | tree v4si_ftype_v4sf_char |
b4de2f7d AH |
6553 | = build_function_type_list (V4SI_type_node, |
6554 | V4SF_type_node, char_type_node, NULL_TREE); | |
2212663f | 6555 | tree v4si_ftype_v4si_char |
b4de2f7d AH |
6556 | = build_function_type_list (V4SI_type_node, |
6557 | V4SI_type_node, char_type_node, NULL_TREE); | |
2212663f | 6558 | tree v8hi_ftype_v8hi_char |
b4de2f7d AH |
6559 | = build_function_type_list (V8HI_type_node, |
6560 | V8HI_type_node, char_type_node, NULL_TREE); | |
2212663f | 6561 | tree v16qi_ftype_v16qi_char |
b4de2f7d AH |
6562 | = build_function_type_list (V16QI_type_node, |
6563 | V16QI_type_node, char_type_node, NULL_TREE); | |
24408032 | 6564 | tree v16qi_ftype_v16qi_v16qi_char |
b4de2f7d AH |
6565 | = build_function_type_list (V16QI_type_node, |
6566 | V16QI_type_node, V16QI_type_node, | |
6567 | char_type_node, NULL_TREE); | |
24408032 | 6568 | tree v8hi_ftype_v8hi_v8hi_char |
b4de2f7d AH |
6569 | = build_function_type_list (V8HI_type_node, |
6570 | V8HI_type_node, V8HI_type_node, | |
6571 | char_type_node, NULL_TREE); | |
24408032 | 6572 | tree v4si_ftype_v4si_v4si_char |
b4de2f7d AH |
6573 | = build_function_type_list (V4SI_type_node, |
6574 | V4SI_type_node, V4SI_type_node, | |
6575 | char_type_node, NULL_TREE); | |
24408032 | 6576 | tree v4sf_ftype_v4sf_v4sf_char |
b4de2f7d AH |
6577 | = build_function_type_list (V4SF_type_node, |
6578 | V4SF_type_node, V4SF_type_node, | |
6579 | char_type_node, NULL_TREE); | |
0ac081f6 | 6580 | tree v4sf_ftype_v4sf_v4sf |
b4de2f7d AH |
6581 | = build_function_type_list (V4SF_type_node, |
6582 | V4SF_type_node, V4SF_type_node, NULL_TREE); | |
617e0e1d | 6583 | tree v4sf_ftype_v4sf_v4sf_v4si |
b4de2f7d AH |
6584 | = build_function_type_list (V4SF_type_node, |
6585 | V4SF_type_node, V4SF_type_node, | |
6586 | V4SI_type_node, NULL_TREE); | |
2212663f | 6587 | tree v4sf_ftype_v4sf_v4sf_v4sf |
b4de2f7d AH |
6588 | = build_function_type_list (V4SF_type_node, |
6589 | V4SF_type_node, V4SF_type_node, | |
6590 | V4SF_type_node, NULL_TREE); | |
617e0e1d | 6591 | tree v4si_ftype_v4si_v4si_v4si |
b4de2f7d AH |
6592 | = build_function_type_list (V4SI_type_node, |
6593 | V4SI_type_node, V4SI_type_node, | |
6594 | V4SI_type_node, NULL_TREE); | |
0ac081f6 | 6595 | tree v8hi_ftype_v8hi_v8hi |
b4de2f7d AH |
6596 | = build_function_type_list (V8HI_type_node, |
6597 | V8HI_type_node, V8HI_type_node, NULL_TREE); | |
2212663f | 6598 | tree v8hi_ftype_v8hi_v8hi_v8hi |
b4de2f7d AH |
6599 | = build_function_type_list (V8HI_type_node, |
6600 | V8HI_type_node, V8HI_type_node, | |
6601 | V8HI_type_node, NULL_TREE); | |
2212663f | 6602 | tree v4si_ftype_v8hi_v8hi_v4si |
b4de2f7d AH |
6603 | = build_function_type_list (V4SI_type_node, |
6604 | V8HI_type_node, V8HI_type_node, | |
6605 | V4SI_type_node, NULL_TREE); | |
2212663f | 6606 | tree v4si_ftype_v16qi_v16qi_v4si |
b4de2f7d AH |
6607 | = build_function_type_list (V4SI_type_node, |
6608 | V16QI_type_node, V16QI_type_node, | |
6609 | V4SI_type_node, NULL_TREE); | |
0ac081f6 | 6610 | tree v16qi_ftype_v16qi_v16qi |
b4de2f7d AH |
6611 | = build_function_type_list (V16QI_type_node, |
6612 | V16QI_type_node, V16QI_type_node, NULL_TREE); | |
0ac081f6 | 6613 | tree v4si_ftype_v4sf_v4sf |
b4de2f7d AH |
6614 | = build_function_type_list (V4SI_type_node, |
6615 | V4SF_type_node, V4SF_type_node, NULL_TREE); | |
0ac081f6 | 6616 | tree v8hi_ftype_v16qi_v16qi |
b4de2f7d AH |
6617 | = build_function_type_list (V8HI_type_node, |
6618 | V16QI_type_node, V16QI_type_node, NULL_TREE); | |
0ac081f6 | 6619 | tree v4si_ftype_v8hi_v8hi |
b4de2f7d AH |
6620 | = build_function_type_list (V4SI_type_node, |
6621 | V8HI_type_node, V8HI_type_node, NULL_TREE); | |
0ac081f6 | 6622 | tree v8hi_ftype_v4si_v4si |
b4de2f7d AH |
6623 | = build_function_type_list (V8HI_type_node, |
6624 | V4SI_type_node, V4SI_type_node, NULL_TREE); | |
0ac081f6 | 6625 | tree v16qi_ftype_v8hi_v8hi |
b4de2f7d AH |
6626 | = build_function_type_list (V16QI_type_node, |
6627 | V8HI_type_node, V8HI_type_node, NULL_TREE); | |
0ac081f6 | 6628 | tree v4si_ftype_v16qi_v4si |
b4de2f7d AH |
6629 | = build_function_type_list (V4SI_type_node, |
6630 | V16QI_type_node, V4SI_type_node, NULL_TREE); | |
fa066a23 | 6631 | tree v4si_ftype_v16qi_v16qi |
b4de2f7d AH |
6632 | = build_function_type_list (V4SI_type_node, |
6633 | V16QI_type_node, V16QI_type_node, NULL_TREE); | |
0ac081f6 | 6634 | tree v4si_ftype_v8hi_v4si |
b4de2f7d AH |
6635 | = build_function_type_list (V4SI_type_node, |
6636 | V8HI_type_node, V4SI_type_node, NULL_TREE); | |
a3170dc6 AH |
6637 | tree v4si_ftype_v8hi |
6638 | = build_function_type_list (V4SI_type_node, V8HI_type_node, NULL_TREE); | |
6639 | tree int_ftype_v4si_v4si | |
6640 | = build_function_type_list (integer_type_node, | |
6641 | V4SI_type_node, V4SI_type_node, NULL_TREE); | |
6642 | tree int_ftype_v4sf_v4sf | |
6643 | = build_function_type_list (integer_type_node, | |
6644 | V4SF_type_node, V4SF_type_node, NULL_TREE); | |
6645 | tree int_ftype_v16qi_v16qi | |
6646 | = build_function_type_list (integer_type_node, | |
6647 | V16QI_type_node, V16QI_type_node, NULL_TREE); | |
0ac081f6 | 6648 | tree int_ftype_v8hi_v8hi |
b4de2f7d AH |
6649 | = build_function_type_list (integer_type_node, |
6650 | V8HI_type_node, V8HI_type_node, NULL_TREE); | |
0ac081f6 | 6651 | |
6f317ef3 | 6652 | /* Add the simple ternary operators. */ |
2212663f | 6653 | d = (struct builtin_description *) bdesc_3arg; |
ca7558fc | 6654 | for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++) |
2212663f DB |
6655 | { |
6656 | ||
6657 | enum machine_mode mode0, mode1, mode2, mode3; | |
6658 | tree type; | |
6659 | ||
0559cc77 | 6660 | if (d->name == 0 || d->icode == CODE_FOR_nothing) |
2212663f DB |
6661 | continue; |
6662 | ||
6663 | mode0 = insn_data[d->icode].operand[0].mode; | |
6664 | mode1 = insn_data[d->icode].operand[1].mode; | |
6665 | mode2 = insn_data[d->icode].operand[2].mode; | |
6666 | mode3 = insn_data[d->icode].operand[3].mode; | |
6667 | ||
6668 | /* When all four are of the same mode. */ | |
6669 | if (mode0 == mode1 && mode1 == mode2 && mode2 == mode3) | |
6670 | { | |
6671 | switch (mode0) | |
6672 | { | |
617e0e1d DB |
6673 | case V4SImode: |
6674 | type = v4si_ftype_v4si_v4si_v4si; | |
6675 | break; | |
2212663f DB |
6676 | case V4SFmode: |
6677 | type = v4sf_ftype_v4sf_v4sf_v4sf; | |
6678 | break; | |
6679 | case V8HImode: | |
6680 | type = v8hi_ftype_v8hi_v8hi_v8hi; | |
6681 | break; | |
6682 | case V16QImode: | |
6683 | type = v16qi_ftype_v16qi_v16qi_v16qi; | |
6684 | break; | |
6685 | default: | |
6686 | abort(); | |
6687 | } | |
6688 | } | |
6689 | else if (mode0 == mode1 && mode1 == mode2 && mode3 == V16QImode) | |
6690 | { | |
6691 | switch (mode0) | |
6692 | { | |
6693 | case V4SImode: | |
6694 | type = v4si_ftype_v4si_v4si_v16qi; | |
6695 | break; | |
6696 | case V4SFmode: | |
6697 | type = v4sf_ftype_v4sf_v4sf_v16qi; | |
6698 | break; | |
6699 | case V8HImode: | |
6700 | type = v8hi_ftype_v8hi_v8hi_v16qi; | |
6701 | break; | |
6702 | case V16QImode: | |
6703 | type = v16qi_ftype_v16qi_v16qi_v16qi; | |
6704 | break; | |
6705 | default: | |
6706 | abort(); | |
6707 | } | |
6708 | } | |
6709 | else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V16QImode | |
6710 | && mode3 == V4SImode) | |
24408032 | 6711 | type = v4si_ftype_v16qi_v16qi_v4si; |
2212663f DB |
6712 | else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V8HImode |
6713 | && mode3 == V4SImode) | |
24408032 | 6714 | type = v4si_ftype_v8hi_v8hi_v4si; |
617e0e1d DB |
6715 | else if (mode0 == V4SFmode && mode1 == V4SFmode && mode2 == V4SFmode |
6716 | && mode3 == V4SImode) | |
24408032 AH |
6717 | type = v4sf_ftype_v4sf_v4sf_v4si; |
6718 | ||
6719 | /* vchar, vchar, vchar, 4 bit literal. */ | |
6720 | else if (mode0 == V16QImode && mode1 == mode0 && mode2 == mode0 | |
6721 | && mode3 == QImode) | |
6722 | type = v16qi_ftype_v16qi_v16qi_char; | |
6723 | ||
6724 | /* vshort, vshort, vshort, 4 bit literal. */ | |
6725 | else if (mode0 == V8HImode && mode1 == mode0 && mode2 == mode0 | |
6726 | && mode3 == QImode) | |
6727 | type = v8hi_ftype_v8hi_v8hi_char; | |
6728 | ||
6729 | /* vint, vint, vint, 4 bit literal. */ | |
6730 | else if (mode0 == V4SImode && mode1 == mode0 && mode2 == mode0 | |
6731 | && mode3 == QImode) | |
6732 | type = v4si_ftype_v4si_v4si_char; | |
6733 | ||
6734 | /* vfloat, vfloat, vfloat, 4 bit literal. */ | |
6735 | else if (mode0 == V4SFmode && mode1 == mode0 && mode2 == mode0 | |
6736 | && mode3 == QImode) | |
6737 | type = v4sf_ftype_v4sf_v4sf_char; | |
6738 | ||
2212663f DB |
6739 | else |
6740 | abort (); | |
6741 | ||
6742 | def_builtin (d->mask, d->name, type, d->code); | |
6743 | } | |
6744 | ||
0ac081f6 | 6745 | /* Add the simple binary operators. */ |
00b960c7 | 6746 | d = (struct builtin_description *) bdesc_2arg; |
ca7558fc | 6747 | for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++) |
0ac081f6 AH |
6748 | { |
6749 | enum machine_mode mode0, mode1, mode2; | |
6750 | tree type; | |
6751 | ||
0559cc77 | 6752 | if (d->name == 0 || d->icode == CODE_FOR_nothing) |
0ac081f6 AH |
6753 | continue; |
6754 | ||
6755 | mode0 = insn_data[d->icode].operand[0].mode; | |
6756 | mode1 = insn_data[d->icode].operand[1].mode; | |
6757 | mode2 = insn_data[d->icode].operand[2].mode; | |
6758 | ||
6759 | /* When all three operands are of the same mode. */ | |
6760 | if (mode0 == mode1 && mode1 == mode2) | |
6761 | { | |
6762 | switch (mode0) | |
6763 | { | |
6764 | case V4SFmode: | |
6765 | type = v4sf_ftype_v4sf_v4sf; | |
6766 | break; | |
6767 | case V4SImode: | |
6768 | type = v4si_ftype_v4si_v4si; | |
6769 | break; | |
6770 | case V16QImode: | |
6771 | type = v16qi_ftype_v16qi_v16qi; | |
6772 | break; | |
6773 | case V8HImode: | |
6774 | type = v8hi_ftype_v8hi_v8hi; | |
6775 | break; | |
a3170dc6 AH |
6776 | case V2SImode: |
6777 | type = v2si_ftype_v2si_v2si; | |
6778 | break; | |
6779 | case V2SFmode: | |
6780 | type = v2sf_ftype_v2sf_v2sf; | |
6781 | break; | |
6782 | case SImode: | |
6783 | type = int_ftype_int_int; | |
6784 | break; | |
0ac081f6 AH |
6785 | default: |
6786 | abort (); | |
6787 | } | |
6788 | } | |
6789 | ||
6790 | /* A few other combos we really don't want to do manually. */ | |
6791 | ||
6792 | /* vint, vfloat, vfloat. */ | |
6793 | else if (mode0 == V4SImode && mode1 == V4SFmode && mode2 == V4SFmode) | |
6794 | type = v4si_ftype_v4sf_v4sf; | |
6795 | ||
6796 | /* vshort, vchar, vchar. */ | |
6797 | else if (mode0 == V8HImode && mode1 == V16QImode && mode2 == V16QImode) | |
6798 | type = v8hi_ftype_v16qi_v16qi; | |
6799 | ||
6800 | /* vint, vshort, vshort. */ | |
6801 | else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V8HImode) | |
6802 | type = v4si_ftype_v8hi_v8hi; | |
6803 | ||
6804 | /* vshort, vint, vint. */ | |
6805 | else if (mode0 == V8HImode && mode1 == V4SImode && mode2 == V4SImode) | |
6806 | type = v8hi_ftype_v4si_v4si; | |
6807 | ||
6808 | /* vchar, vshort, vshort. */ | |
6809 | else if (mode0 == V16QImode && mode1 == V8HImode && mode2 == V8HImode) | |
6810 | type = v16qi_ftype_v8hi_v8hi; | |
6811 | ||
6812 | /* vint, vchar, vint. */ | |
6813 | else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V4SImode) | |
6814 | type = v4si_ftype_v16qi_v4si; | |
6815 | ||
fa066a23 AH |
6816 | /* vint, vchar, vchar. */ |
6817 | else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V16QImode) | |
6818 | type = v4si_ftype_v16qi_v16qi; | |
6819 | ||
0ac081f6 AH |
6820 | /* vint, vshort, vint. */ |
6821 | else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V4SImode) | |
6822 | type = v4si_ftype_v8hi_v4si; | |
2212663f DB |
6823 | |
6824 | /* vint, vint, 5 bit literal. */ | |
6825 | else if (mode0 == V4SImode && mode1 == V4SImode && mode2 == QImode) | |
6826 | type = v4si_ftype_v4si_char; | |
6827 | ||
6828 | /* vshort, vshort, 5 bit literal. */ | |
6829 | else if (mode0 == V8HImode && mode1 == V8HImode && mode2 == QImode) | |
6830 | type = v8hi_ftype_v8hi_char; | |
6831 | ||
6832 | /* vchar, vchar, 5 bit literal. */ | |
6833 | else if (mode0 == V16QImode && mode1 == V16QImode && mode2 == QImode) | |
6834 | type = v16qi_ftype_v16qi_char; | |
0ac081f6 | 6835 | |
617e0e1d DB |
6836 | /* vfloat, vint, 5 bit literal. */ |
6837 | else if (mode0 == V4SFmode && mode1 == V4SImode && mode2 == QImode) | |
6838 | type = v4sf_ftype_v4si_char; | |
6839 | ||
6840 | /* vint, vfloat, 5 bit literal. */ | |
6841 | else if (mode0 == V4SImode && mode1 == V4SFmode && mode2 == QImode) | |
6842 | type = v4si_ftype_v4sf_char; | |
6843 | ||
a3170dc6 AH |
6844 | else if (mode0 == V2SImode && mode1 == SImode && mode2 == SImode) |
6845 | type = v2si_ftype_int_int; | |
6846 | ||
6847 | else if (mode0 == V2SImode && mode1 == V2SImode && mode2 == QImode) | |
6848 | type = v2si_ftype_v2si_char; | |
6849 | ||
6850 | else if (mode0 == V2SImode && mode1 == SImode && mode2 == QImode) | |
6851 | type = v2si_ftype_int_char; | |
6852 | ||
0ac081f6 AH |
6853 | /* int, x, x. */ |
6854 | else if (mode0 == SImode) | |
6855 | { | |
6856 | switch (mode1) | |
6857 | { | |
6858 | case V4SImode: | |
6859 | type = int_ftype_v4si_v4si; | |
6860 | break; | |
6861 | case V4SFmode: | |
6862 | type = int_ftype_v4sf_v4sf; | |
6863 | break; | |
6864 | case V16QImode: | |
6865 | type = int_ftype_v16qi_v16qi; | |
6866 | break; | |
6867 | case V8HImode: | |
6868 | type = int_ftype_v8hi_v8hi; | |
6869 | break; | |
6870 | default: | |
6871 | abort (); | |
6872 | } | |
6873 | } | |
6874 | ||
6875 | else | |
6876 | abort (); | |
6877 | ||
2212663f DB |
6878 | def_builtin (d->mask, d->name, type, d->code); |
6879 | } | |
24408032 | 6880 | |
2212663f DB |
6881 | /* Add the simple unary operators. */ |
6882 | d = (struct builtin_description *) bdesc_1arg; | |
ca7558fc | 6883 | for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++) |
2212663f DB |
6884 | { |
6885 | enum machine_mode mode0, mode1; | |
6886 | tree type; | |
6887 | ||
0559cc77 | 6888 | if (d->name == 0 || d->icode == CODE_FOR_nothing) |
2212663f DB |
6889 | continue; |
6890 | ||
6891 | mode0 = insn_data[d->icode].operand[0].mode; | |
6892 | mode1 = insn_data[d->icode].operand[1].mode; | |
6893 | ||
6894 | if (mode0 == V4SImode && mode1 == QImode) | |
6895 | type = v4si_ftype_char; | |
6896 | else if (mode0 == V8HImode && mode1 == QImode) | |
6897 | type = v8hi_ftype_char; | |
6898 | else if (mode0 == V16QImode && mode1 == QImode) | |
6899 | type = v16qi_ftype_char; | |
617e0e1d DB |
6900 | else if (mode0 == V4SFmode && mode1 == V4SFmode) |
6901 | type = v4sf_ftype_v4sf; | |
20e26713 AH |
6902 | else if (mode0 == V8HImode && mode1 == V16QImode) |
6903 | type = v8hi_ftype_v16qi; | |
6904 | else if (mode0 == V4SImode && mode1 == V8HImode) | |
6905 | type = v4si_ftype_v8hi; | |
a3170dc6 AH |
6906 | else if (mode0 == V2SImode && mode1 == V2SImode) |
6907 | type = v2si_ftype_v2si; | |
6908 | else if (mode0 == V2SFmode && mode1 == V2SFmode) | |
6909 | type = v2sf_ftype_v2sf; | |
6910 | else if (mode0 == V2SFmode && mode1 == V2SImode) | |
6911 | type = v2sf_ftype_v2si; | |
6912 | else if (mode0 == V2SImode && mode1 == V2SFmode) | |
6913 | type = v2si_ftype_v2sf; | |
6914 | else if (mode0 == V2SImode && mode1 == QImode) | |
6915 | type = v2si_ftype_char; | |
2212663f DB |
6916 | else |
6917 | abort (); | |
6918 | ||
0ac081f6 AH |
6919 | def_builtin (d->mask, d->name, type, d->code); |
6920 | } | |
6921 | } | |
6922 | ||
35aff10b | 6923 | \f |
7e69e155 MM |
6924 | /* Expand a block move operation, and return 1 if successful. Return 0 |
6925 | if we should let the compiler generate normal code. | |
6926 | ||
6927 | operands[0] is the destination | |
6928 | operands[1] is the source | |
6929 | operands[2] is the length | |
6930 | operands[3] is the alignment */ | |
6931 | ||
3933e0e1 MM |
6932 | #define MAX_MOVE_REG 4 |
6933 | ||
7e69e155 MM |
6934 | int |
6935 | expand_block_move (operands) | |
6936 | rtx operands[]; | |
6937 | { | |
b6c9286a MM |
6938 | rtx orig_dest = operands[0]; |
6939 | rtx orig_src = operands[1]; | |
7e69e155 | 6940 | rtx bytes_rtx = operands[2]; |
7e69e155 | 6941 | rtx align_rtx = operands[3]; |
3933e0e1 | 6942 | int constp = (GET_CODE (bytes_rtx) == CONST_INT); |
5ee95df6 | 6943 | int align; |
3933e0e1 MM |
6944 | int bytes; |
6945 | int offset; | |
7e69e155 | 6946 | int move_bytes; |
cabfd258 GK |
6947 | rtx stores[MAX_MOVE_REG]; |
6948 | int num_reg = 0; | |
7e69e155 | 6949 | |
3933e0e1 | 6950 | /* If this is not a fixed size move, just call memcpy */ |
cc0d9ba8 | 6951 | if (! constp) |
3933e0e1 MM |
6952 | return 0; |
6953 | ||
5ee95df6 FS |
6954 | /* If this is not a fixed size alignment, abort */ |
6955 | if (GET_CODE (align_rtx) != CONST_INT) | |
6956 | abort (); | |
6957 | align = INTVAL (align_rtx); | |
6958 | ||
7e69e155 | 6959 | /* Anything to move? */ |
3933e0e1 MM |
6960 | bytes = INTVAL (bytes_rtx); |
6961 | if (bytes <= 0) | |
7e69e155 MM |
6962 | return 1; |
6963 | ||
ea9982a8 | 6964 | /* store_one_arg depends on expand_block_move to handle at least the size of |
6f317ef3 | 6965 | reg_parm_stack_space. */ |
ea9982a8 | 6966 | if (bytes > (TARGET_POWERPC64 ? 64 : 32)) |
7e69e155 MM |
6967 | return 0; |
6968 | ||
cabfd258 | 6969 | for (offset = 0; bytes > 0; offset += move_bytes, bytes -= move_bytes) |
7e69e155 | 6970 | { |
cabfd258 GK |
6971 | union { |
6972 | rtx (*movstrsi) PARAMS ((rtx, rtx, rtx, rtx)); | |
6973 | rtx (*mov) PARAMS ((rtx, rtx)); | |
6974 | } gen_func; | |
6975 | enum machine_mode mode = BLKmode; | |
6976 | rtx src, dest; | |
6977 | ||
6978 | if (TARGET_STRING | |
6979 | && bytes > 24 /* move up to 32 bytes at a time */ | |
6980 | && ! fixed_regs[5] | |
6981 | && ! fixed_regs[6] | |
6982 | && ! fixed_regs[7] | |
6983 | && ! fixed_regs[8] | |
6984 | && ! fixed_regs[9] | |
6985 | && ! fixed_regs[10] | |
6986 | && ! fixed_regs[11] | |
6987 | && ! fixed_regs[12]) | |
7e69e155 | 6988 | { |
cabfd258 GK |
6989 | move_bytes = (bytes > 32) ? 32 : bytes; |
6990 | gen_func.movstrsi = gen_movstrsi_8reg; | |
6991 | } | |
6992 | else if (TARGET_STRING | |
6993 | && bytes > 16 /* move up to 24 bytes at a time */ | |
6994 | && ! fixed_regs[5] | |
6995 | && ! fixed_regs[6] | |
6996 | && ! fixed_regs[7] | |
6997 | && ! fixed_regs[8] | |
6998 | && ! fixed_regs[9] | |
6999 | && ! fixed_regs[10]) | |
7000 | { | |
7001 | move_bytes = (bytes > 24) ? 24 : bytes; | |
7002 | gen_func.movstrsi = gen_movstrsi_6reg; | |
7003 | } | |
7004 | else if (TARGET_STRING | |
7005 | && bytes > 8 /* move up to 16 bytes at a time */ | |
7006 | && ! fixed_regs[5] | |
7007 | && ! fixed_regs[6] | |
7008 | && ! fixed_regs[7] | |
7009 | && ! fixed_regs[8]) | |
7010 | { | |
7011 | move_bytes = (bytes > 16) ? 16 : bytes; | |
7012 | gen_func.movstrsi = gen_movstrsi_4reg; | |
7013 | } | |
7014 | else if (bytes >= 8 && TARGET_POWERPC64 | |
7015 | /* 64-bit loads and stores require word-aligned | |
7016 | displacements. */ | |
7017 | && (align >= 8 || (! STRICT_ALIGNMENT && align >= 4))) | |
7018 | { | |
7019 | move_bytes = 8; | |
7020 | mode = DImode; | |
7021 | gen_func.mov = gen_movdi; | |
7022 | } | |
7023 | else if (TARGET_STRING && bytes > 4 && !TARGET_POWERPC64) | |
7024 | { /* move up to 8 bytes at a time */ | |
7025 | move_bytes = (bytes > 8) ? 8 : bytes; | |
7026 | gen_func.movstrsi = gen_movstrsi_2reg; | |
7027 | } | |
7028 | else if (bytes >= 4 && (align >= 4 || ! STRICT_ALIGNMENT)) | |
7029 | { /* move 4 bytes */ | |
7030 | move_bytes = 4; | |
7031 | mode = SImode; | |
7032 | gen_func.mov = gen_movsi; | |
7033 | } | |
7034 | else if (bytes == 2 && (align >= 2 || ! STRICT_ALIGNMENT)) | |
7035 | { /* move 2 bytes */ | |
7036 | move_bytes = 2; | |
7037 | mode = HImode; | |
7038 | gen_func.mov = gen_movhi; | |
7039 | } | |
7040 | else if (TARGET_STRING && bytes > 1) | |
7041 | { /* move up to 4 bytes at a time */ | |
7042 | move_bytes = (bytes > 4) ? 4 : bytes; | |
7043 | gen_func.movstrsi = gen_movstrsi_1reg; | |
7044 | } | |
7045 | else /* move 1 byte at a time */ | |
7046 | { | |
7047 | move_bytes = 1; | |
7048 | mode = QImode; | |
7049 | gen_func.mov = gen_movqi; | |
7050 | } | |
7051 | ||
7052 | src = adjust_address (orig_src, mode, offset); | |
7053 | dest = adjust_address (orig_dest, mode, offset); | |
7054 | ||
7055 | if (mode != BLKmode) | |
7056 | { | |
7057 | rtx tmp_reg = gen_reg_rtx (mode); | |
7058 | ||
7059 | emit_insn ((*gen_func.mov) (tmp_reg, src)); | |
7060 | stores[num_reg++] = (*gen_func.mov) (dest, tmp_reg); | |
4c64a852 | 7061 | } |
3933e0e1 | 7062 | |
cabfd258 GK |
7063 | if (mode == BLKmode || num_reg >= MAX_MOVE_REG || bytes == move_bytes) |
7064 | { | |
7065 | int i; | |
7066 | for (i = 0; i < num_reg; i++) | |
7067 | emit_insn (stores[i]); | |
7068 | num_reg = 0; | |
7069 | } | |
35aff10b | 7070 | |
cabfd258 | 7071 | if (mode == BLKmode) |
7e69e155 | 7072 | { |
cabfd258 GK |
7073 | /* Move the address into scratch registers. The movstrsi |
7074 | patterns require zero offset. */ | |
7075 | if (!REG_P (XEXP (src, 0))) | |
b6c9286a | 7076 | { |
cabfd258 GK |
7077 | rtx src_reg = copy_addr_to_reg (XEXP (src, 0)); |
7078 | src = replace_equiv_address (src, src_reg); | |
b6c9286a | 7079 | } |
cabfd258 GK |
7080 | set_mem_size (src, GEN_INT (move_bytes)); |
7081 | ||
7082 | if (!REG_P (XEXP (dest, 0))) | |
3933e0e1 | 7083 | { |
cabfd258 GK |
7084 | rtx dest_reg = copy_addr_to_reg (XEXP (dest, 0)); |
7085 | dest = replace_equiv_address (dest, dest_reg); | |
7e69e155 | 7086 | } |
cabfd258 GK |
7087 | set_mem_size (dest, GEN_INT (move_bytes)); |
7088 | ||
7089 | emit_insn ((*gen_func.movstrsi) (dest, src, | |
7090 | GEN_INT (move_bytes & 31), | |
7091 | align_rtx)); | |
7e69e155 | 7092 | } |
7e69e155 MM |
7093 | } |
7094 | ||
7095 | return 1; | |
7096 | } | |
7097 | ||
9878760c RK |
7098 | \f |
7099 | /* Return 1 if OP is a load multiple operation. It is known to be a | |
7100 | PARALLEL and the first section will be tested. */ | |
7101 | ||
7102 | int | |
7103 | load_multiple_operation (op, mode) | |
7104 | rtx op; | |
296b8152 | 7105 | enum machine_mode mode ATTRIBUTE_UNUSED; |
9878760c RK |
7106 | { |
7107 | int count = XVECLEN (op, 0); | |
e2c953b6 | 7108 | unsigned int dest_regno; |
9878760c RK |
7109 | rtx src_addr; |
7110 | int i; | |
7111 | ||
7112 | /* Perform a quick check so we don't blow up below. */ | |
7113 | if (count <= 1 | |
7114 | || GET_CODE (XVECEXP (op, 0, 0)) != SET | |
7115 | || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG | |
7116 | || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM) | |
7117 | return 0; | |
7118 | ||
7119 | dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0))); | |
7120 | src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0); | |
7121 | ||
7122 | for (i = 1; i < count; i++) | |
7123 | { | |
7124 | rtx elt = XVECEXP (op, 0, i); | |
7125 | ||
7126 | if (GET_CODE (elt) != SET | |
7127 | || GET_CODE (SET_DEST (elt)) != REG | |
7128 | || GET_MODE (SET_DEST (elt)) != SImode | |
7129 | || REGNO (SET_DEST (elt)) != dest_regno + i | |
7130 | || GET_CODE (SET_SRC (elt)) != MEM | |
7131 | || GET_MODE (SET_SRC (elt)) != SImode | |
7132 | || GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS | |
7133 | || ! rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr) | |
7134 | || GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT | |
7135 | || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != i * 4) | |
7136 | return 0; | |
7137 | } | |
7138 | ||
7139 | return 1; | |
7140 | } | |
7141 | ||
7142 | /* Similar, but tests for store multiple. Here, the second vector element | |
7143 | is a CLOBBER. It will be tested later. */ | |
7144 | ||
7145 | int | |
7146 | store_multiple_operation (op, mode) | |
7147 | rtx op; | |
296b8152 | 7148 | enum machine_mode mode ATTRIBUTE_UNUSED; |
9878760c RK |
7149 | { |
7150 | int count = XVECLEN (op, 0) - 1; | |
e2c953b6 | 7151 | unsigned int src_regno; |
9878760c RK |
7152 | rtx dest_addr; |
7153 | int i; | |
7154 | ||
7155 | /* Perform a quick check so we don't blow up below. */ | |
7156 | if (count <= 1 | |
7157 | || GET_CODE (XVECEXP (op, 0, 0)) != SET | |
7158 | || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM | |
7159 | || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG) | |
7160 | return 0; | |
7161 | ||
7162 | src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0))); | |
7163 | dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0); | |
7164 | ||
7165 | for (i = 1; i < count; i++) | |
7166 | { | |
7167 | rtx elt = XVECEXP (op, 0, i + 1); | |
7168 | ||
7169 | if (GET_CODE (elt) != SET | |
7170 | || GET_CODE (SET_SRC (elt)) != REG | |
7171 | || GET_MODE (SET_SRC (elt)) != SImode | |
7172 | || REGNO (SET_SRC (elt)) != src_regno + i | |
7173 | || GET_CODE (SET_DEST (elt)) != MEM | |
7174 | || GET_MODE (SET_DEST (elt)) != SImode | |
7175 | || GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS | |
7176 | || ! rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr) | |
7177 | || GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT | |
7178 | || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != i * 4) | |
7179 | return 0; | |
7180 | } | |
7181 | ||
7182 | return 1; | |
7183 | } | |
9ebbca7d | 7184 | |
9caa3eb2 DE |
7185 | /* Return a string to perform a load_multiple operation. |
7186 | operands[0] is the vector. | |
7187 | operands[1] is the source address. | |
7188 | operands[2] is the first destination register. */ | |
7189 | ||
7190 | const char * | |
7191 | rs6000_output_load_multiple (operands) | |
ebe637e3 | 7192 | rtx operands[3]; |
9caa3eb2 DE |
7193 | { |
7194 | /* We have to handle the case where the pseudo used to contain the address | |
7195 | is assigned to one of the output registers. */ | |
7196 | int i, j; | |
7197 | int words = XVECLEN (operands[0], 0); | |
7198 | rtx xop[10]; | |
7199 | ||
7200 | if (XVECLEN (operands[0], 0) == 1) | |
7201 | return "{l|lwz} %2,0(%1)"; | |
7202 | ||
7203 | for (i = 0; i < words; i++) | |
7204 | if (refers_to_regno_p (REGNO (operands[2]) + i, | |
7205 | REGNO (operands[2]) + i + 1, operands[1], 0)) | |
7206 | { | |
7207 | if (i == words-1) | |
7208 | { | |
7209 | xop[0] = GEN_INT (4 * (words-1)); | |
7210 | xop[1] = operands[1]; | |
7211 | xop[2] = operands[2]; | |
7212 | output_asm_insn ("{lsi|lswi} %2,%1,%0\n\t{l|lwz} %1,%0(%1)", xop); | |
7213 | return ""; | |
7214 | } | |
7215 | else if (i == 0) | |
7216 | { | |
7217 | xop[0] = GEN_INT (4 * (words-1)); | |
7218 | xop[1] = operands[1]; | |
7219 | xop[2] = gen_rtx_REG (SImode, REGNO (operands[2]) + 1); | |
7220 | output_asm_insn ("{cal %1,4(%1)|addi %1,%1,4}\n\t{lsi|lswi} %2,%1,%0\n\t{l|lwz} %1,-4(%1)", xop); | |
7221 | return ""; | |
7222 | } | |
7223 | else | |
7224 | { | |
7225 | for (j = 0; j < words; j++) | |
7226 | if (j != i) | |
7227 | { | |
7228 | xop[0] = GEN_INT (j * 4); | |
7229 | xop[1] = operands[1]; | |
7230 | xop[2] = gen_rtx_REG (SImode, REGNO (operands[2]) + j); | |
7231 | output_asm_insn ("{l|lwz} %2,%0(%1)", xop); | |
7232 | } | |
7233 | xop[0] = GEN_INT (i * 4); | |
7234 | xop[1] = operands[1]; | |
7235 | output_asm_insn ("{l|lwz} %1,%0(%1)", xop); | |
7236 | return ""; | |
7237 | } | |
7238 | } | |
7239 | ||
7240 | return "{lsi|lswi} %2,%1,%N0"; | |
7241 | } | |
7242 | ||
00b960c7 AH |
7243 | /* Return 1 for a parallel vrsave operation. */ |
7244 | ||
7245 | int | |
7246 | vrsave_operation (op, mode) | |
7247 | rtx op; | |
7248 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
7249 | { | |
7250 | int count = XVECLEN (op, 0); | |
7251 | unsigned int dest_regno, src_regno; | |
7252 | int i; | |
7253 | ||
7254 | if (count <= 1 | |
7255 | || GET_CODE (XVECEXP (op, 0, 0)) != SET | |
7256 | || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG | |
a004eb82 | 7257 | || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC_VOLATILE) |
00b960c7 AH |
7258 | return 0; |
7259 | ||
7260 | dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0))); | |
7261 | src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0))); | |
7262 | ||
7263 | if (dest_regno != VRSAVE_REGNO | |
7264 | && src_regno != VRSAVE_REGNO) | |
7265 | return 0; | |
7266 | ||
7267 | for (i = 1; i < count; i++) | |
7268 | { | |
7269 | rtx elt = XVECEXP (op, 0, i); | |
7270 | ||
9aa86737 AH |
7271 | if (GET_CODE (elt) != CLOBBER |
7272 | && GET_CODE (elt) != SET) | |
00b960c7 AH |
7273 | return 0; |
7274 | } | |
7275 | ||
7276 | return 1; | |
7277 | } | |
7278 | ||
a4f6c312 | 7279 | /* Return 1 for an PARALLEL suitable for mtcrf. */ |
9ebbca7d GK |
7280 | |
7281 | int | |
7282 | mtcrf_operation (op, mode) | |
7283 | rtx op; | |
7284 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
7285 | { | |
7286 | int count = XVECLEN (op, 0); | |
7287 | int i; | |
9ebbca7d GK |
7288 | rtx src_reg; |
7289 | ||
7290 | /* Perform a quick check so we don't blow up below. */ | |
e35b9579 GK |
7291 | if (count < 1 |
7292 | || GET_CODE (XVECEXP (op, 0, 0)) != SET | |
7293 | || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC | |
7294 | || XVECLEN (SET_SRC (XVECEXP (op, 0, 0)), 0) != 2) | |
9ebbca7d | 7295 | return 0; |
e35b9579 | 7296 | src_reg = XVECEXP (SET_SRC (XVECEXP (op, 0, 0)), 0, 0); |
9ebbca7d GK |
7297 | |
7298 | if (GET_CODE (src_reg) != REG | |
7299 | || GET_MODE (src_reg) != SImode | |
7300 | || ! INT_REGNO_P (REGNO (src_reg))) | |
7301 | return 0; | |
7302 | ||
e35b9579 | 7303 | for (i = 0; i < count; i++) |
9ebbca7d GK |
7304 | { |
7305 | rtx exp = XVECEXP (op, 0, i); | |
7306 | rtx unspec; | |
7307 | int maskval; | |
7308 | ||
7309 | if (GET_CODE (exp) != SET | |
7310 | || GET_CODE (SET_DEST (exp)) != REG | |
7311 | || GET_MODE (SET_DEST (exp)) != CCmode | |
7312 | || ! CR_REGNO_P (REGNO (SET_DEST (exp)))) | |
7313 | return 0; | |
7314 | unspec = SET_SRC (exp); | |
7315 | maskval = 1 << (MAX_CR_REGNO - REGNO (SET_DEST (exp))); | |
9ebbca7d GK |
7316 | |
7317 | if (GET_CODE (unspec) != UNSPEC | |
615158e2 | 7318 | || XINT (unspec, 1) != UNSPEC_MOVESI_TO_CR |
9ebbca7d GK |
7319 | || XVECLEN (unspec, 0) != 2 |
7320 | || XVECEXP (unspec, 0, 0) != src_reg | |
7321 | || GET_CODE (XVECEXP (unspec, 0, 1)) != CONST_INT | |
7322 | || INTVAL (XVECEXP (unspec, 0, 1)) != maskval) | |
7323 | return 0; | |
7324 | } | |
e35b9579 | 7325 | return 1; |
9ebbca7d GK |
7326 | } |
7327 | ||
a4f6c312 | 7328 | /* Return 1 for an PARALLEL suitable for lmw. */ |
9ebbca7d GK |
7329 | |
7330 | int | |
7331 | lmw_operation (op, mode) | |
7332 | rtx op; | |
7333 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
7334 | { | |
7335 | int count = XVECLEN (op, 0); | |
e2c953b6 | 7336 | unsigned int dest_regno; |
9ebbca7d | 7337 | rtx src_addr; |
e2c953b6 | 7338 | unsigned int base_regno; |
9ebbca7d GK |
7339 | HOST_WIDE_INT offset; |
7340 | int i; | |
7341 | ||
7342 | /* Perform a quick check so we don't blow up below. */ | |
7343 | if (count <= 1 | |
7344 | || GET_CODE (XVECEXP (op, 0, 0)) != SET | |
7345 | || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG | |
7346 | || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM) | |
7347 | return 0; | |
7348 | ||
7349 | dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0))); | |
7350 | src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0); | |
7351 | ||
7352 | if (dest_regno > 31 | |
e2c953b6 | 7353 | || count != 32 - (int) dest_regno) |
9ebbca7d GK |
7354 | return 0; |
7355 | ||
4d588c14 | 7356 | if (legitimate_indirect_address_p (src_addr, 0)) |
9ebbca7d GK |
7357 | { |
7358 | offset = 0; | |
7359 | base_regno = REGNO (src_addr); | |
7360 | if (base_regno == 0) | |
7361 | return 0; | |
7362 | } | |
4d588c14 | 7363 | else if (legitimate_offset_address_p (SImode, src_addr, 0)) |
9ebbca7d GK |
7364 | { |
7365 | offset = INTVAL (XEXP (src_addr, 1)); | |
7366 | base_regno = REGNO (XEXP (src_addr, 0)); | |
7367 | } | |
7368 | else | |
7369 | return 0; | |
7370 | ||
7371 | for (i = 0; i < count; i++) | |
7372 | { | |
7373 | rtx elt = XVECEXP (op, 0, i); | |
7374 | rtx newaddr; | |
7375 | rtx addr_reg; | |
7376 | HOST_WIDE_INT newoffset; | |
7377 | ||
7378 | if (GET_CODE (elt) != SET | |
7379 | || GET_CODE (SET_DEST (elt)) != REG | |
7380 | || GET_MODE (SET_DEST (elt)) != SImode | |
7381 | || REGNO (SET_DEST (elt)) != dest_regno + i | |
7382 | || GET_CODE (SET_SRC (elt)) != MEM | |
7383 | || GET_MODE (SET_SRC (elt)) != SImode) | |
7384 | return 0; | |
7385 | newaddr = XEXP (SET_SRC (elt), 0); | |
4d588c14 | 7386 | if (legitimate_indirect_address_p (newaddr, 0)) |
9ebbca7d GK |
7387 | { |
7388 | newoffset = 0; | |
7389 | addr_reg = newaddr; | |
7390 | } | |
4d588c14 | 7391 | else if (legitimate_offset_address_p (SImode, newaddr, 0)) |
9ebbca7d GK |
7392 | { |
7393 | addr_reg = XEXP (newaddr, 0); | |
7394 | newoffset = INTVAL (XEXP (newaddr, 1)); | |
7395 | } | |
7396 | else | |
7397 | return 0; | |
7398 | if (REGNO (addr_reg) != base_regno | |
7399 | || newoffset != offset + 4 * i) | |
7400 | return 0; | |
7401 | } | |
7402 | ||
7403 | return 1; | |
7404 | } | |
7405 | ||
a4f6c312 | 7406 | /* Return 1 for an PARALLEL suitable for stmw. */ |
9ebbca7d GK |
7407 | |
7408 | int | |
7409 | stmw_operation (op, mode) | |
7410 | rtx op; | |
7411 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
7412 | { | |
7413 | int count = XVECLEN (op, 0); | |
e2c953b6 | 7414 | unsigned int src_regno; |
9ebbca7d | 7415 | rtx dest_addr; |
e2c953b6 | 7416 | unsigned int base_regno; |
9ebbca7d GK |
7417 | HOST_WIDE_INT offset; |
7418 | int i; | |
7419 | ||
7420 | /* Perform a quick check so we don't blow up below. */ | |
7421 | if (count <= 1 | |
7422 | || GET_CODE (XVECEXP (op, 0, 0)) != SET | |
7423 | || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM | |
7424 | || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG) | |
7425 | return 0; | |
7426 | ||
7427 | src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0))); | |
7428 | dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0); | |
7429 | ||
7430 | if (src_regno > 31 | |
e2c953b6 | 7431 | || count != 32 - (int) src_regno) |
9ebbca7d GK |
7432 | return 0; |
7433 | ||
4d588c14 | 7434 | if (legitimate_indirect_address_p (dest_addr, 0)) |
9ebbca7d GK |
7435 | { |
7436 | offset = 0; | |
7437 | base_regno = REGNO (dest_addr); | |
7438 | if (base_regno == 0) | |
7439 | return 0; | |
7440 | } | |
4d588c14 | 7441 | else if (legitimate_offset_address_p (SImode, dest_addr, 0)) |
9ebbca7d GK |
7442 | { |
7443 | offset = INTVAL (XEXP (dest_addr, 1)); | |
7444 | base_regno = REGNO (XEXP (dest_addr, 0)); | |
7445 | } | |
7446 | else | |
7447 | return 0; | |
7448 | ||
7449 | for (i = 0; i < count; i++) | |
7450 | { | |
7451 | rtx elt = XVECEXP (op, 0, i); | |
7452 | rtx newaddr; | |
7453 | rtx addr_reg; | |
7454 | HOST_WIDE_INT newoffset; | |
7455 | ||
7456 | if (GET_CODE (elt) != SET | |
7457 | || GET_CODE (SET_SRC (elt)) != REG | |
7458 | || GET_MODE (SET_SRC (elt)) != SImode | |
7459 | || REGNO (SET_SRC (elt)) != src_regno + i | |
7460 | || GET_CODE (SET_DEST (elt)) != MEM | |
7461 | || GET_MODE (SET_DEST (elt)) != SImode) | |
7462 | return 0; | |
7463 | newaddr = XEXP (SET_DEST (elt), 0); | |
4d588c14 | 7464 | if (legitimate_indirect_address_p (newaddr, 0)) |
9ebbca7d GK |
7465 | { |
7466 | newoffset = 0; | |
7467 | addr_reg = newaddr; | |
7468 | } | |
4d588c14 | 7469 | else if (legitimate_offset_address_p (SImode, newaddr, 0)) |
9ebbca7d GK |
7470 | { |
7471 | addr_reg = XEXP (newaddr, 0); | |
7472 | newoffset = INTVAL (XEXP (newaddr, 1)); | |
7473 | } | |
7474 | else | |
7475 | return 0; | |
7476 | if (REGNO (addr_reg) != base_regno | |
7477 | || newoffset != offset + 4 * i) | |
7478 | return 0; | |
7479 | } | |
7480 | ||
7481 | return 1; | |
7482 | } | |
9878760c | 7483 | \f |
a4f6c312 SS |
7484 | /* A validation routine: say whether CODE, a condition code, and MODE |
7485 | match. The other alternatives either don't make sense or should | |
7486 | never be generated. */ | |
39a10a29 | 7487 | |
39a10a29 GK |
7488 | static void |
7489 | validate_condition_mode (code, mode) | |
7490 | enum rtx_code code; | |
7491 | enum machine_mode mode; | |
7492 | { | |
7493 | if (GET_RTX_CLASS (code) != '<' | |
7494 | || GET_MODE_CLASS (mode) != MODE_CC) | |
7495 | abort (); | |
7496 | ||
7497 | /* These don't make sense. */ | |
7498 | if ((code == GT || code == LT || code == GE || code == LE) | |
7499 | && mode == CCUNSmode) | |
7500 | abort (); | |
7501 | ||
7502 | if ((code == GTU || code == LTU || code == GEU || code == LEU) | |
7503 | && mode != CCUNSmode) | |
7504 | abort (); | |
7505 | ||
7506 | if (mode != CCFPmode | |
7507 | && (code == ORDERED || code == UNORDERED | |
7508 | || code == UNEQ || code == LTGT | |
7509 | || code == UNGT || code == UNLT | |
7510 | || code == UNGE || code == UNLE)) | |
a4f6c312 | 7511 | abort (); |
39a10a29 | 7512 | |
de6c5979 | 7513 | /* These should never be generated except for |
bc9ec0e0 | 7514 | flag_finite_math_only. */ |
39a10a29 | 7515 | if (mode == CCFPmode |
ad72b533 | 7516 | && ! flag_finite_math_only |
39a10a29 GK |
7517 | && (code == LE || code == GE |
7518 | || code == UNEQ || code == LTGT | |
7519 | || code == UNGT || code == UNLT)) | |
7520 | abort (); | |
7521 | ||
7522 | /* These are invalid; the information is not there. */ | |
7523 | if (mode == CCEQmode | |
7524 | && code != EQ && code != NE) | |
7525 | abort (); | |
7526 | } | |
7527 | ||
9878760c RK |
7528 | /* Return 1 if OP is a comparison operation that is valid for a branch insn. |
7529 | We only check the opcode against the mode of the CC value here. */ | |
7530 | ||
7531 | int | |
7532 | branch_comparison_operator (op, mode) | |
592696dd | 7533 | rtx op; |
296b8152 | 7534 | enum machine_mode mode ATTRIBUTE_UNUSED; |
9878760c RK |
7535 | { |
7536 | enum rtx_code code = GET_CODE (op); | |
7537 | enum machine_mode cc_mode; | |
7538 | ||
7539 | if (GET_RTX_CLASS (code) != '<') | |
7540 | return 0; | |
7541 | ||
7542 | cc_mode = GET_MODE (XEXP (op, 0)); | |
7543 | if (GET_MODE_CLASS (cc_mode) != MODE_CC) | |
7544 | return 0; | |
7545 | ||
39a10a29 | 7546 | validate_condition_mode (code, cc_mode); |
9878760c | 7547 | |
39a10a29 GK |
7548 | return 1; |
7549 | } | |
7550 | ||
7551 | /* Return 1 if OP is a comparison operation that is valid for a branch | |
7552 | insn and which is true if the corresponding bit in the CC register | |
7553 | is set. */ | |
7554 | ||
7555 | int | |
7556 | branch_positive_comparison_operator (op, mode) | |
592696dd | 7557 | rtx op; |
39a10a29 GK |
7558 | enum machine_mode mode; |
7559 | { | |
7560 | enum rtx_code code; | |
7561 | ||
7562 | if (! branch_comparison_operator (op, mode)) | |
9878760c RK |
7563 | return 0; |
7564 | ||
39a10a29 GK |
7565 | code = GET_CODE (op); |
7566 | return (code == EQ || code == LT || code == GT | |
993f19a8 | 7567 | || (TARGET_E500 && TARGET_HARD_FLOAT && !TARGET_FPRS && code == NE) |
39a10a29 GK |
7568 | || code == LTU || code == GTU |
7569 | || code == UNORDERED); | |
9878760c RK |
7570 | } |
7571 | ||
b7053a3f GK |
7572 | /* Return 1 if OP is a comparison operation that is valid for an scc |
7573 | insn: it must be a positive comparison. */ | |
9878760c RK |
7574 | |
7575 | int | |
7576 | scc_comparison_operator (op, mode) | |
592696dd | 7577 | rtx op; |
9878760c RK |
7578 | enum machine_mode mode; |
7579 | { | |
b7053a3f | 7580 | return branch_positive_comparison_operator (op, mode); |
9878760c | 7581 | } |
e0cd0770 JC |
7582 | |
7583 | int | |
7584 | trap_comparison_operator (op, mode) | |
7585 | rtx op; | |
7586 | enum machine_mode mode; | |
7587 | { | |
7588 | if (mode != VOIDmode && mode != GET_MODE (op)) | |
7589 | return 0; | |
39a10a29 | 7590 | return GET_RTX_CLASS (GET_CODE (op)) == '<'; |
e0cd0770 | 7591 | } |
dfbdccdb GK |
7592 | |
7593 | int | |
7594 | boolean_operator (op, mode) | |
7595 | rtx op; | |
7596 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
7597 | { | |
7598 | enum rtx_code code = GET_CODE (op); | |
7599 | return (code == AND || code == IOR || code == XOR); | |
7600 | } | |
1d328b19 GK |
7601 | |
7602 | int | |
7603 | boolean_or_operator (op, mode) | |
7604 | rtx op; | |
7605 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
7606 | { | |
7607 | enum rtx_code code = GET_CODE (op); | |
7608 | return (code == IOR || code == XOR); | |
7609 | } | |
50a0b056 GK |
7610 | |
7611 | int | |
7612 | min_max_operator (op, mode) | |
7613 | rtx op; | |
7614 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
7615 | { | |
7616 | enum rtx_code code = GET_CODE (op); | |
7617 | return (code == SMIN || code == SMAX || code == UMIN || code == UMAX); | |
7618 | } | |
9878760c RK |
7619 | \f |
7620 | /* Return 1 if ANDOP is a mask that has no bits on that are not in the | |
7621 | mask required to convert the result of a rotate insn into a shift | |
b1765bde | 7622 | left insn of SHIFTOP bits. Both are known to be SImode CONST_INT. */ |
9878760c RK |
7623 | |
7624 | int | |
7625 | includes_lshift_p (shiftop, andop) | |
592696dd SS |
7626 | rtx shiftop; |
7627 | rtx andop; | |
9878760c | 7628 | { |
e2c953b6 DE |
7629 | unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0; |
7630 | ||
7631 | shift_mask <<= INTVAL (shiftop); | |
9878760c | 7632 | |
b1765bde | 7633 | return (INTVAL (andop) & 0xffffffff & ~shift_mask) == 0; |
9878760c RK |
7634 | } |
7635 | ||
7636 | /* Similar, but for right shift. */ | |
7637 | ||
7638 | int | |
7639 | includes_rshift_p (shiftop, andop) | |
592696dd SS |
7640 | rtx shiftop; |
7641 | rtx andop; | |
9878760c | 7642 | { |
a7653a2c | 7643 | unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0; |
9878760c RK |
7644 | |
7645 | shift_mask >>= INTVAL (shiftop); | |
7646 | ||
b1765bde | 7647 | return (INTVAL (andop) & 0xffffffff & ~shift_mask) == 0; |
e2c953b6 DE |
7648 | } |
7649 | ||
c5059423 AM |
7650 | /* Return 1 if ANDOP is a mask suitable for use with an rldic insn |
7651 | to perform a left shift. It must have exactly SHIFTOP least | |
b6d08ca1 | 7652 | significant 0's, then one or more 1's, then zero or more 0's. */ |
e2c953b6 DE |
7653 | |
7654 | int | |
c5059423 | 7655 | includes_rldic_lshift_p (shiftop, andop) |
592696dd SS |
7656 | rtx shiftop; |
7657 | rtx andop; | |
e2c953b6 | 7658 | { |
c5059423 AM |
7659 | if (GET_CODE (andop) == CONST_INT) |
7660 | { | |
02071907 | 7661 | HOST_WIDE_INT c, lsb, shift_mask; |
e2c953b6 | 7662 | |
c5059423 | 7663 | c = INTVAL (andop); |
02071907 | 7664 | if (c == 0 || c == ~0) |
c5059423 | 7665 | return 0; |
e2c953b6 | 7666 | |
02071907 | 7667 | shift_mask = ~0; |
c5059423 AM |
7668 | shift_mask <<= INTVAL (shiftop); |
7669 | ||
b6d08ca1 | 7670 | /* Find the least significant one bit. */ |
c5059423 AM |
7671 | lsb = c & -c; |
7672 | ||
7673 | /* It must coincide with the LSB of the shift mask. */ | |
7674 | if (-lsb != shift_mask) | |
7675 | return 0; | |
e2c953b6 | 7676 | |
c5059423 AM |
7677 | /* Invert to look for the next transition (if any). */ |
7678 | c = ~c; | |
7679 | ||
7680 | /* Remove the low group of ones (originally low group of zeros). */ | |
7681 | c &= -lsb; | |
7682 | ||
7683 | /* Again find the lsb, and check we have all 1's above. */ | |
7684 | lsb = c & -c; | |
7685 | return c == -lsb; | |
7686 | } | |
7687 | else if (GET_CODE (andop) == CONST_DOUBLE | |
7688 | && (GET_MODE (andop) == VOIDmode || GET_MODE (andop) == DImode)) | |
7689 | { | |
02071907 AM |
7690 | HOST_WIDE_INT low, high, lsb; |
7691 | HOST_WIDE_INT shift_mask_low, shift_mask_high; | |
c5059423 AM |
7692 | |
7693 | low = CONST_DOUBLE_LOW (andop); | |
7694 | if (HOST_BITS_PER_WIDE_INT < 64) | |
7695 | high = CONST_DOUBLE_HIGH (andop); | |
7696 | ||
7697 | if ((low == 0 && (HOST_BITS_PER_WIDE_INT >= 64 || high == 0)) | |
02071907 | 7698 | || (low == ~0 && (HOST_BITS_PER_WIDE_INT >= 64 || high == ~0))) |
c5059423 AM |
7699 | return 0; |
7700 | ||
7701 | if (HOST_BITS_PER_WIDE_INT < 64 && low == 0) | |
7702 | { | |
02071907 | 7703 | shift_mask_high = ~0; |
c5059423 AM |
7704 | if (INTVAL (shiftop) > 32) |
7705 | shift_mask_high <<= INTVAL (shiftop) - 32; | |
7706 | ||
7707 | lsb = high & -high; | |
7708 | ||
7709 | if (-lsb != shift_mask_high || INTVAL (shiftop) < 32) | |
7710 | return 0; | |
7711 | ||
7712 | high = ~high; | |
7713 | high &= -lsb; | |
7714 | ||
7715 | lsb = high & -high; | |
7716 | return high == -lsb; | |
7717 | } | |
7718 | ||
02071907 | 7719 | shift_mask_low = ~0; |
c5059423 AM |
7720 | shift_mask_low <<= INTVAL (shiftop); |
7721 | ||
7722 | lsb = low & -low; | |
7723 | ||
7724 | if (-lsb != shift_mask_low) | |
7725 | return 0; | |
7726 | ||
7727 | if (HOST_BITS_PER_WIDE_INT < 64) | |
7728 | high = ~high; | |
7729 | low = ~low; | |
7730 | low &= -lsb; | |
7731 | ||
7732 | if (HOST_BITS_PER_WIDE_INT < 64 && low == 0) | |
7733 | { | |
7734 | lsb = high & -high; | |
7735 | return high == -lsb; | |
7736 | } | |
7737 | ||
7738 | lsb = low & -low; | |
7739 | return low == -lsb && (HOST_BITS_PER_WIDE_INT >= 64 || high == ~0); | |
7740 | } | |
7741 | else | |
7742 | return 0; | |
7743 | } | |
e2c953b6 | 7744 | |
c5059423 AM |
7745 | /* Return 1 if ANDOP is a mask suitable for use with an rldicr insn |
7746 | to perform a left shift. It must have SHIFTOP or more least | |
7747 | signifigant 0's, with the remainder of the word 1's. */ | |
e2c953b6 | 7748 | |
c5059423 AM |
7749 | int |
7750 | includes_rldicr_lshift_p (shiftop, andop) | |
592696dd SS |
7751 | rtx shiftop; |
7752 | rtx andop; | |
c5059423 | 7753 | { |
e2c953b6 | 7754 | if (GET_CODE (andop) == CONST_INT) |
c5059423 | 7755 | { |
02071907 | 7756 | HOST_WIDE_INT c, lsb, shift_mask; |
c5059423 | 7757 | |
02071907 | 7758 | shift_mask = ~0; |
c5059423 AM |
7759 | shift_mask <<= INTVAL (shiftop); |
7760 | c = INTVAL (andop); | |
7761 | ||
7762 | /* Find the least signifigant one bit. */ | |
7763 | lsb = c & -c; | |
7764 | ||
7765 | /* It must be covered by the shift mask. | |
a4f6c312 | 7766 | This test also rejects c == 0. */ |
c5059423 AM |
7767 | if ((lsb & shift_mask) == 0) |
7768 | return 0; | |
7769 | ||
7770 | /* Check we have all 1's above the transition, and reject all 1's. */ | |
7771 | return c == -lsb && lsb != 1; | |
7772 | } | |
7773 | else if (GET_CODE (andop) == CONST_DOUBLE | |
7774 | && (GET_MODE (andop) == VOIDmode || GET_MODE (andop) == DImode)) | |
7775 | { | |
02071907 | 7776 | HOST_WIDE_INT low, lsb, shift_mask_low; |
c5059423 AM |
7777 | |
7778 | low = CONST_DOUBLE_LOW (andop); | |
7779 | ||
7780 | if (HOST_BITS_PER_WIDE_INT < 64) | |
7781 | { | |
02071907 | 7782 | HOST_WIDE_INT high, shift_mask_high; |
c5059423 AM |
7783 | |
7784 | high = CONST_DOUBLE_HIGH (andop); | |
7785 | ||
7786 | if (low == 0) | |
7787 | { | |
02071907 | 7788 | shift_mask_high = ~0; |
c5059423 AM |
7789 | if (INTVAL (shiftop) > 32) |
7790 | shift_mask_high <<= INTVAL (shiftop) - 32; | |
7791 | ||
7792 | lsb = high & -high; | |
7793 | ||
7794 | if ((lsb & shift_mask_high) == 0) | |
7795 | return 0; | |
7796 | ||
7797 | return high == -lsb; | |
7798 | } | |
7799 | if (high != ~0) | |
7800 | return 0; | |
7801 | } | |
7802 | ||
02071907 | 7803 | shift_mask_low = ~0; |
c5059423 AM |
7804 | shift_mask_low <<= INTVAL (shiftop); |
7805 | ||
7806 | lsb = low & -low; | |
7807 | ||
7808 | if ((lsb & shift_mask_low) == 0) | |
7809 | return 0; | |
7810 | ||
7811 | return low == -lsb && lsb != 1; | |
7812 | } | |
e2c953b6 | 7813 | else |
c5059423 | 7814 | return 0; |
9878760c | 7815 | } |
35068b43 RK |
7816 | |
7817 | /* Return 1 if REGNO (reg1) == REGNO (reg2) - 1 making them candidates | |
7818 | for lfq and stfq insns. | |
7819 | ||
7820 | Note reg1 and reg2 *must* be hard registers. To be sure we will | |
7821 | abort if we are passed pseudo registers. */ | |
7822 | ||
7823 | int | |
7824 | registers_ok_for_quad_peep (reg1, reg2) | |
7825 | rtx reg1, reg2; | |
7826 | { | |
7827 | /* We might have been passed a SUBREG. */ | |
7828 | if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG) | |
7829 | return 0; | |
7830 | ||
7831 | return (REGNO (reg1) == REGNO (reg2) - 1); | |
7832 | } | |
7833 | ||
a4f6c312 SS |
7834 | /* Return 1 if addr1 and addr2 are suitable for lfq or stfq insn. |
7835 | addr1 and addr2 must be in consecutive memory locations | |
7836 | (addr2 == addr1 + 8). */ | |
35068b43 RK |
7837 | |
7838 | int | |
7839 | addrs_ok_for_quad_peep (addr1, addr2) | |
592696dd SS |
7840 | rtx addr1; |
7841 | rtx addr2; | |
35068b43 | 7842 | { |
e2c953b6 | 7843 | unsigned int reg1; |
35068b43 RK |
7844 | int offset1; |
7845 | ||
7846 | /* Extract an offset (if used) from the first addr. */ | |
7847 | if (GET_CODE (addr1) == PLUS) | |
7848 | { | |
7849 | /* If not a REG, return zero. */ | |
7850 | if (GET_CODE (XEXP (addr1, 0)) != REG) | |
7851 | return 0; | |
7852 | else | |
7853 | { | |
7854 | reg1 = REGNO (XEXP (addr1, 0)); | |
7855 | /* The offset must be constant! */ | |
7856 | if (GET_CODE (XEXP (addr1, 1)) != CONST_INT) | |
7857 | return 0; | |
7858 | offset1 = INTVAL (XEXP (addr1, 1)); | |
7859 | } | |
7860 | } | |
7861 | else if (GET_CODE (addr1) != REG) | |
7862 | return 0; | |
7863 | else | |
7864 | { | |
7865 | reg1 = REGNO (addr1); | |
7866 | /* This was a simple (mem (reg)) expression. Offset is 0. */ | |
7867 | offset1 = 0; | |
7868 | } | |
7869 | ||
984e25ac DE |
7870 | /* Make sure the second address is a (mem (plus (reg) (const_int))) |
7871 | or if it is (mem (reg)) then make sure that offset1 is -8 and the same | |
7872 | register as addr1. */ | |
7873 | if (offset1 == -8 && GET_CODE (addr2) == REG && reg1 == REGNO (addr2)) | |
7874 | return 1; | |
35068b43 RK |
7875 | if (GET_CODE (addr2) != PLUS) |
7876 | return 0; | |
7877 | ||
7878 | if (GET_CODE (XEXP (addr2, 0)) != REG | |
7879 | || GET_CODE (XEXP (addr2, 1)) != CONST_INT) | |
7880 | return 0; | |
7881 | ||
7882 | if (reg1 != REGNO (XEXP (addr2, 0))) | |
7883 | return 0; | |
7884 | ||
7885 | /* The offset for the second addr must be 8 more than the first addr. */ | |
7886 | if (INTVAL (XEXP (addr2, 1)) != offset1 + 8) | |
7887 | return 0; | |
7888 | ||
7889 | /* All the tests passed. addr1 and addr2 are valid for lfq or stfq | |
7890 | instructions. */ | |
7891 | return 1; | |
7892 | } | |
9878760c RK |
7893 | \f |
7894 | /* Return the register class of a scratch register needed to copy IN into | |
7895 | or out of a register in CLASS in MODE. If it can be done directly, | |
7896 | NO_REGS is returned. */ | |
7897 | ||
7898 | enum reg_class | |
7899 | secondary_reload_class (class, mode, in) | |
7900 | enum reg_class class; | |
296b8152 | 7901 | enum machine_mode mode ATTRIBUTE_UNUSED; |
9878760c RK |
7902 | rtx in; |
7903 | { | |
5accd822 | 7904 | int regno; |
9878760c | 7905 | |
ab82a49f AP |
7906 | if (TARGET_ELF || (DEFAULT_ABI == ABI_DARWIN |
7907 | #if TARGET_MACHO | |
7908 | && MACHOPIC_INDIRECT | |
7909 | #endif | |
7910 | )) | |
46fad5b7 DJ |
7911 | { |
7912 | /* We cannot copy a symbolic operand directly into anything | |
7913 | other than BASE_REGS for TARGET_ELF. So indicate that a | |
7914 | register from BASE_REGS is needed as an intermediate | |
7915 | register. | |
7916 | ||
7917 | On Darwin, pic addresses require a load from memory, which | |
7918 | needs a base register. */ | |
7919 | if (class != BASE_REGS | |
7920 | && (GET_CODE (in) == SYMBOL_REF | |
7921 | || GET_CODE (in) == HIGH | |
7922 | || GET_CODE (in) == LABEL_REF | |
7923 | || GET_CODE (in) == CONST)) | |
7924 | return BASE_REGS; | |
7925 | } | |
e7b7998a | 7926 | |
5accd822 DE |
7927 | if (GET_CODE (in) == REG) |
7928 | { | |
7929 | regno = REGNO (in); | |
7930 | if (regno >= FIRST_PSEUDO_REGISTER) | |
7931 | { | |
7932 | regno = true_regnum (in); | |
7933 | if (regno >= FIRST_PSEUDO_REGISTER) | |
7934 | regno = -1; | |
7935 | } | |
7936 | } | |
7937 | else if (GET_CODE (in) == SUBREG) | |
7938 | { | |
7939 | regno = true_regnum (in); | |
7940 | if (regno >= FIRST_PSEUDO_REGISTER) | |
7941 | regno = -1; | |
7942 | } | |
7943 | else | |
7944 | regno = -1; | |
7945 | ||
9878760c RK |
7946 | /* We can place anything into GENERAL_REGS and can put GENERAL_REGS |
7947 | into anything. */ | |
7948 | if (class == GENERAL_REGS || class == BASE_REGS | |
7949 | || (regno >= 0 && INT_REGNO_P (regno))) | |
7950 | return NO_REGS; | |
7951 | ||
7952 | /* Constants, memory, and FP registers can go into FP registers. */ | |
7953 | if ((regno == -1 || FP_REGNO_P (regno)) | |
7954 | && (class == FLOAT_REGS || class == NON_SPECIAL_REGS)) | |
7955 | return NO_REGS; | |
7956 | ||
0ac081f6 AH |
7957 | /* Memory, and AltiVec registers can go into AltiVec registers. */ |
7958 | if ((regno == -1 || ALTIVEC_REGNO_P (regno)) | |
7959 | && class == ALTIVEC_REGS) | |
7960 | return NO_REGS; | |
7961 | ||
9878760c RK |
7962 | /* We can copy among the CR registers. */ |
7963 | if ((class == CR_REGS || class == CR0_REGS) | |
7964 | && regno >= 0 && CR_REGNO_P (regno)) | |
7965 | return NO_REGS; | |
7966 | ||
7967 | /* Otherwise, we need GENERAL_REGS. */ | |
7968 | return GENERAL_REGS; | |
7969 | } | |
7970 | \f | |
7971 | /* Given a comparison operation, return the bit number in CCR to test. We | |
7972 | know this is a valid comparison. | |
7973 | ||
7974 | SCC_P is 1 if this is for an scc. That means that %D will have been | |
7975 | used instead of %C, so the bits will be in different places. | |
7976 | ||
b4ac57ab | 7977 | Return -1 if OP isn't a valid comparison for some reason. */ |
9878760c RK |
7978 | |
7979 | int | |
7980 | ccr_bit (op, scc_p) | |
592696dd | 7981 | rtx op; |
9878760c RK |
7982 | int scc_p; |
7983 | { | |
7984 | enum rtx_code code = GET_CODE (op); | |
7985 | enum machine_mode cc_mode; | |
7986 | int cc_regnum; | |
7987 | int base_bit; | |
9ebbca7d | 7988 | rtx reg; |
9878760c RK |
7989 | |
7990 | if (GET_RTX_CLASS (code) != '<') | |
7991 | return -1; | |
7992 | ||
9ebbca7d GK |
7993 | reg = XEXP (op, 0); |
7994 | ||
7995 | if (GET_CODE (reg) != REG | |
7996 | || ! CR_REGNO_P (REGNO (reg))) | |
7997 | abort (); | |
7998 | ||
7999 | cc_mode = GET_MODE (reg); | |
8000 | cc_regnum = REGNO (reg); | |
8001 | base_bit = 4 * (cc_regnum - CR0_REGNO); | |
9878760c | 8002 | |
39a10a29 | 8003 | validate_condition_mode (code, cc_mode); |
c5defebb | 8004 | |
b7053a3f GK |
8005 | /* When generating a sCOND operation, only positive conditions are |
8006 | allowed. */ | |
8007 | if (scc_p && code != EQ && code != GT && code != LT && code != UNORDERED | |
8008 | && code != GTU && code != LTU) | |
8009 | abort (); | |
8010 | ||
9878760c RK |
8011 | switch (code) |
8012 | { | |
8013 | case NE: | |
993f19a8 AH |
8014 | if (TARGET_E500 && !TARGET_FPRS |
8015 | && TARGET_HARD_FLOAT && cc_mode == CCFPmode) | |
a3170dc6 | 8016 | return base_bit + 1; |
9878760c RK |
8017 | return scc_p ? base_bit + 3 : base_bit + 2; |
8018 | case EQ: | |
993f19a8 AH |
8019 | if (TARGET_E500 && !TARGET_FPRS |
8020 | && TARGET_HARD_FLOAT && cc_mode == CCFPmode) | |
a3170dc6 | 8021 | return base_bit + 1; |
9878760c | 8022 | return base_bit + 2; |
1c882ea4 | 8023 | case GT: case GTU: case UNLE: |
9878760c | 8024 | return base_bit + 1; |
1c882ea4 | 8025 | case LT: case LTU: case UNGE: |
9878760c | 8026 | return base_bit; |
1c882ea4 GK |
8027 | case ORDERED: case UNORDERED: |
8028 | return base_bit + 3; | |
9878760c RK |
8029 | |
8030 | case GE: case GEU: | |
39a10a29 | 8031 | /* If scc, we will have done a cror to put the bit in the |
9878760c RK |
8032 | unordered position. So test that bit. For integer, this is ! LT |
8033 | unless this is an scc insn. */ | |
39a10a29 | 8034 | return scc_p ? base_bit + 3 : base_bit; |
9878760c RK |
8035 | |
8036 | case LE: case LEU: | |
39a10a29 | 8037 | return scc_p ? base_bit + 3 : base_bit + 1; |
1c882ea4 | 8038 | |
9878760c RK |
8039 | default: |
8040 | abort (); | |
8041 | } | |
8042 | } | |
1ff7789b | 8043 | \f |
8d30c4ee | 8044 | /* Return the GOT register. */ |
1ff7789b MM |
8045 | |
8046 | struct rtx_def * | |
8047 | rs6000_got_register (value) | |
5f59ecb7 | 8048 | rtx value ATTRIBUTE_UNUSED; |
1ff7789b | 8049 | { |
a4f6c312 SS |
8050 | /* The second flow pass currently (June 1999) can't update |
8051 | regs_ever_live without disturbing other parts of the compiler, so | |
8052 | update it here to make the prolog/epilogue code happy. */ | |
1db02437 FS |
8053 | if (no_new_pseudos && ! regs_ever_live[RS6000_PIC_OFFSET_TABLE_REGNUM]) |
8054 | regs_ever_live[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1; | |
1ff7789b | 8055 | |
8d30c4ee | 8056 | current_function_uses_pic_offset_table = 1; |
3cb999d8 | 8057 | |
1ff7789b MM |
8058 | return pic_offset_table_rtx; |
8059 | } | |
a7df97e6 | 8060 | \f |
e2500fed GK |
8061 | /* Function to init struct machine_function. |
8062 | This will be called, via a pointer variable, | |
8063 | from push_function_context. */ | |
a7df97e6 | 8064 | |
e2500fed GK |
8065 | static struct machine_function * |
8066 | rs6000_init_machine_status () | |
a7df97e6 | 8067 | { |
e2500fed | 8068 | return ggc_alloc_cleared (sizeof (machine_function)); |
a7df97e6 | 8069 | } |
9878760c | 8070 | \f |
0ba1b2ff AM |
8071 | /* These macros test for integers and extract the low-order bits. */ |
8072 | #define INT_P(X) \ | |
8073 | ((GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST_DOUBLE) \ | |
8074 | && GET_MODE (X) == VOIDmode) | |
8075 | ||
8076 | #define INT_LOWPART(X) \ | |
8077 | (GET_CODE (X) == CONST_INT ? INTVAL (X) : CONST_DOUBLE_LOW (X)) | |
8078 | ||
8079 | int | |
8080 | extract_MB (op) | |
8081 | rtx op; | |
8082 | { | |
8083 | int i; | |
8084 | unsigned long val = INT_LOWPART (op); | |
8085 | ||
8086 | /* If the high bit is zero, the value is the first 1 bit we find | |
8087 | from the left. */ | |
8088 | if ((val & 0x80000000) == 0) | |
8089 | { | |
8090 | if ((val & 0xffffffff) == 0) | |
8091 | abort (); | |
8092 | ||
8093 | i = 1; | |
8094 | while (((val <<= 1) & 0x80000000) == 0) | |
8095 | ++i; | |
8096 | return i; | |
8097 | } | |
8098 | ||
8099 | /* If the high bit is set and the low bit is not, or the mask is all | |
8100 | 1's, the value is zero. */ | |
8101 | if ((val & 1) == 0 || (val & 0xffffffff) == 0xffffffff) | |
8102 | return 0; | |
8103 | ||
8104 | /* Otherwise we have a wrap-around mask. Look for the first 0 bit | |
8105 | from the right. */ | |
8106 | i = 31; | |
8107 | while (((val >>= 1) & 1) != 0) | |
8108 | --i; | |
8109 | ||
8110 | return i; | |
8111 | } | |
8112 | ||
8113 | int | |
8114 | extract_ME (op) | |
8115 | rtx op; | |
8116 | { | |
8117 | int i; | |
8118 | unsigned long val = INT_LOWPART (op); | |
8119 | ||
8120 | /* If the low bit is zero, the value is the first 1 bit we find from | |
8121 | the right. */ | |
8122 | if ((val & 1) == 0) | |
8123 | { | |
8124 | if ((val & 0xffffffff) == 0) | |
8125 | abort (); | |
8126 | ||
8127 | i = 30; | |
8128 | while (((val >>= 1) & 1) == 0) | |
8129 | --i; | |
8130 | ||
8131 | return i; | |
8132 | } | |
8133 | ||
8134 | /* If the low bit is set and the high bit is not, or the mask is all | |
8135 | 1's, the value is 31. */ | |
8136 | if ((val & 0x80000000) == 0 || (val & 0xffffffff) == 0xffffffff) | |
8137 | return 31; | |
8138 | ||
8139 | /* Otherwise we have a wrap-around mask. Look for the first 0 bit | |
8140 | from the left. */ | |
8141 | i = 0; | |
8142 | while (((val <<= 1) & 0x80000000) != 0) | |
8143 | ++i; | |
8144 | ||
8145 | return i; | |
8146 | } | |
8147 | ||
c4501e62 JJ |
8148 | /* Locate some local-dynamic symbol still in use by this function |
8149 | so that we can print its name in some tls_ld pattern. */ | |
8150 | ||
8151 | static const char * | |
8152 | rs6000_get_some_local_dynamic_name () | |
8153 | { | |
8154 | rtx insn; | |
8155 | ||
8156 | if (cfun->machine->some_ld_name) | |
8157 | return cfun->machine->some_ld_name; | |
8158 | ||
8159 | for (insn = get_insns (); insn ; insn = NEXT_INSN (insn)) | |
8160 | if (INSN_P (insn) | |
8161 | && for_each_rtx (&PATTERN (insn), | |
8162 | rs6000_get_some_local_dynamic_name_1, 0)) | |
8163 | return cfun->machine->some_ld_name; | |
8164 | ||
8165 | abort (); | |
8166 | } | |
8167 | ||
8168 | /* Helper function for rs6000_get_some_local_dynamic_name. */ | |
8169 | ||
8170 | static int | |
8171 | rs6000_get_some_local_dynamic_name_1 (px, data) | |
8172 | rtx *px; | |
8173 | void *data ATTRIBUTE_UNUSED; | |
8174 | { | |
8175 | rtx x = *px; | |
8176 | ||
8177 | if (GET_CODE (x) == SYMBOL_REF) | |
8178 | { | |
8179 | const char *str = XSTR (x, 0); | |
8180 | if (SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC) | |
8181 | { | |
8182 | cfun->machine->some_ld_name = str; | |
8183 | return 1; | |
8184 | } | |
8185 | } | |
8186 | ||
8187 | return 0; | |
8188 | } | |
8189 | ||
9878760c RK |
8190 | /* Print an operand. Recognize special options, documented below. */ |
8191 | ||
38c1f2d7 | 8192 | #if TARGET_ELF |
d9407988 | 8193 | #define SMALL_DATA_RELOC ((rs6000_sdata == SDATA_EABI) ? "sda21" : "sdarel") |
8fbd2dc7 | 8194 | #define SMALL_DATA_REG ((rs6000_sdata == SDATA_EABI) ? 0 : 13) |
ba5e43aa MM |
8195 | #else |
8196 | #define SMALL_DATA_RELOC "sda21" | |
8fbd2dc7 | 8197 | #define SMALL_DATA_REG 0 |
ba5e43aa MM |
8198 | #endif |
8199 | ||
9878760c RK |
8200 | void |
8201 | print_operand (file, x, code) | |
8202 | FILE *file; | |
8203 | rtx x; | |
9ebbca7d | 8204 | int code; |
9878760c RK |
8205 | { |
8206 | int i; | |
a260abc9 | 8207 | HOST_WIDE_INT val; |
0ba1b2ff | 8208 | unsigned HOST_WIDE_INT uval; |
9878760c RK |
8209 | |
8210 | switch (code) | |
8211 | { | |
a8b3aeda | 8212 | case '.': |
a85d226b RK |
8213 | /* Write out an instruction after the call which may be replaced |
8214 | with glue code by the loader. This depends on the AIX version. */ | |
8215 | asm_fprintf (file, RS6000_CALL_GLUE); | |
a8b3aeda RK |
8216 | return; |
8217 | ||
81eace42 GK |
8218 | /* %a is output_address. */ |
8219 | ||
9854d9ed RK |
8220 | case 'A': |
8221 | /* If X is a constant integer whose low-order 5 bits are zero, | |
8222 | write 'l'. Otherwise, write 'r'. This is a kludge to fix a bug | |
76229ac8 | 8223 | in the AIX assembler where "sri" with a zero shift count |
20e26713 | 8224 | writes a trash instruction. */ |
9854d9ed | 8225 | if (GET_CODE (x) == CONST_INT && (INTVAL (x) & 31) == 0) |
76229ac8 | 8226 | putc ('l', file); |
9854d9ed | 8227 | else |
76229ac8 | 8228 | putc ('r', file); |
9854d9ed RK |
8229 | return; |
8230 | ||
8231 | case 'b': | |
e2c953b6 DE |
8232 | /* If constant, low-order 16 bits of constant, unsigned. |
8233 | Otherwise, write normally. */ | |
8234 | if (INT_P (x)) | |
8235 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 0xffff); | |
8236 | else | |
8237 | print_operand (file, x, 0); | |
cad12a8d RK |
8238 | return; |
8239 | ||
a260abc9 DE |
8240 | case 'B': |
8241 | /* If the low-order bit is zero, write 'r'; otherwise, write 'l' | |
8242 | for 64-bit mask direction. */ | |
296b8152 | 8243 | putc (((INT_LOWPART(x) & 1) == 0 ? 'r' : 'l'), file); |
a238cd8b | 8244 | return; |
a260abc9 | 8245 | |
81eace42 GK |
8246 | /* %c is output_addr_const if a CONSTANT_ADDRESS_P, otherwise |
8247 | output_operand. */ | |
8248 | ||
9854d9ed | 8249 | case 'E': |
39a10a29 | 8250 | /* X is a CR register. Print the number of the EQ bit of the CR */ |
9854d9ed RK |
8251 | if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x))) |
8252 | output_operand_lossage ("invalid %%E value"); | |
78fbdbf7 | 8253 | else |
39a10a29 | 8254 | fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO) + 2); |
a85d226b | 8255 | return; |
9854d9ed RK |
8256 | |
8257 | case 'f': | |
8258 | /* X is a CR register. Print the shift count needed to move it | |
8259 | to the high-order four bits. */ | |
8260 | if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x))) | |
8261 | output_operand_lossage ("invalid %%f value"); | |
8262 | else | |
9ebbca7d | 8263 | fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO)); |
9854d9ed RK |
8264 | return; |
8265 | ||
8266 | case 'F': | |
8267 | /* Similar, but print the count for the rotate in the opposite | |
8268 | direction. */ | |
8269 | if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x))) | |
8270 | output_operand_lossage ("invalid %%F value"); | |
8271 | else | |
9ebbca7d | 8272 | fprintf (file, "%d", 32 - 4 * (REGNO (x) - CR0_REGNO)); |
9854d9ed RK |
8273 | return; |
8274 | ||
8275 | case 'G': | |
8276 | /* X is a constant integer. If it is negative, print "m", | |
43aa4e05 | 8277 | otherwise print "z". This is to make an aze or ame insn. */ |
9854d9ed RK |
8278 | if (GET_CODE (x) != CONST_INT) |
8279 | output_operand_lossage ("invalid %%G value"); | |
8280 | else if (INTVAL (x) >= 0) | |
76229ac8 | 8281 | putc ('z', file); |
9854d9ed | 8282 | else |
76229ac8 | 8283 | putc ('m', file); |
9854d9ed | 8284 | return; |
e2c953b6 | 8285 | |
9878760c | 8286 | case 'h': |
a4f6c312 SS |
8287 | /* If constant, output low-order five bits. Otherwise, write |
8288 | normally. */ | |
9878760c | 8289 | if (INT_P (x)) |
5f59ecb7 | 8290 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 31); |
9878760c RK |
8291 | else |
8292 | print_operand (file, x, 0); | |
8293 | return; | |
8294 | ||
64305719 | 8295 | case 'H': |
a4f6c312 SS |
8296 | /* If constant, output low-order six bits. Otherwise, write |
8297 | normally. */ | |
64305719 | 8298 | if (INT_P (x)) |
5f59ecb7 | 8299 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 63); |
64305719 DE |
8300 | else |
8301 | print_operand (file, x, 0); | |
8302 | return; | |
8303 | ||
9854d9ed RK |
8304 | case 'I': |
8305 | /* Print `i' if this is a constant, else nothing. */ | |
9878760c | 8306 | if (INT_P (x)) |
76229ac8 | 8307 | putc ('i', file); |
9878760c RK |
8308 | return; |
8309 | ||
9854d9ed RK |
8310 | case 'j': |
8311 | /* Write the bit number in CCR for jump. */ | |
8312 | i = ccr_bit (x, 0); | |
8313 | if (i == -1) | |
8314 | output_operand_lossage ("invalid %%j code"); | |
9878760c | 8315 | else |
9854d9ed | 8316 | fprintf (file, "%d", i); |
9878760c RK |
8317 | return; |
8318 | ||
9854d9ed RK |
8319 | case 'J': |
8320 | /* Similar, but add one for shift count in rlinm for scc and pass | |
8321 | scc flag to `ccr_bit'. */ | |
8322 | i = ccr_bit (x, 1); | |
8323 | if (i == -1) | |
8324 | output_operand_lossage ("invalid %%J code"); | |
8325 | else | |
a0466a68 RK |
8326 | /* If we want bit 31, write a shift count of zero, not 32. */ |
8327 | fprintf (file, "%d", i == 31 ? 0 : i + 1); | |
9878760c RK |
8328 | return; |
8329 | ||
9854d9ed RK |
8330 | case 'k': |
8331 | /* X must be a constant. Write the 1's complement of the | |
8332 | constant. */ | |
9878760c | 8333 | if (! INT_P (x)) |
9854d9ed | 8334 | output_operand_lossage ("invalid %%k value"); |
e2c953b6 DE |
8335 | else |
8336 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, ~ INT_LOWPART (x)); | |
9878760c RK |
8337 | return; |
8338 | ||
81eace42 | 8339 | case 'K': |
9ebbca7d GK |
8340 | /* X must be a symbolic constant on ELF. Write an |
8341 | expression suitable for an 'addi' that adds in the low 16 | |
8342 | bits of the MEM. */ | |
8343 | if (GET_CODE (x) != CONST) | |
8344 | { | |
8345 | print_operand_address (file, x); | |
8346 | fputs ("@l", file); | |
8347 | } | |
8348 | else | |
8349 | { | |
8350 | if (GET_CODE (XEXP (x, 0)) != PLUS | |
8351 | || (GET_CODE (XEXP (XEXP (x, 0), 0)) != SYMBOL_REF | |
8352 | && GET_CODE (XEXP (XEXP (x, 0), 0)) != LABEL_REF) | |
8353 | || GET_CODE (XEXP (XEXP (x, 0), 1)) != CONST_INT) | |
53cd5d6c | 8354 | output_operand_lossage ("invalid %%K value"); |
9ebbca7d GK |
8355 | print_operand_address (file, XEXP (XEXP (x, 0), 0)); |
8356 | fputs ("@l", file); | |
ed8d2920 MM |
8357 | /* For GNU as, there must be a non-alphanumeric character |
8358 | between 'l' and the number. The '-' is added by | |
8359 | print_operand() already. */ | |
8360 | if (INTVAL (XEXP (XEXP (x, 0), 1)) >= 0) | |
8361 | fputs ("+", file); | |
9ebbca7d GK |
8362 | print_operand (file, XEXP (XEXP (x, 0), 1), 0); |
8363 | } | |
81eace42 GK |
8364 | return; |
8365 | ||
8366 | /* %l is output_asm_label. */ | |
9ebbca7d | 8367 | |
9854d9ed RK |
8368 | case 'L': |
8369 | /* Write second word of DImode or DFmode reference. Works on register | |
8370 | or non-indexed memory only. */ | |
8371 | if (GET_CODE (x) == REG) | |
5ebfb2ba | 8372 | fprintf (file, "%s", reg_names[REGNO (x) + 1]); |
9854d9ed RK |
8373 | else if (GET_CODE (x) == MEM) |
8374 | { | |
8375 | /* Handle possible auto-increment. Since it is pre-increment and | |
1427100a | 8376 | we have already done it, we can just use an offset of word. */ |
9854d9ed RK |
8377 | if (GET_CODE (XEXP (x, 0)) == PRE_INC |
8378 | || GET_CODE (XEXP (x, 0)) == PRE_DEC) | |
ed8908e7 RK |
8379 | output_address (plus_constant (XEXP (XEXP (x, 0), 0), |
8380 | UNITS_PER_WORD)); | |
9854d9ed | 8381 | else |
d7624dc0 RK |
8382 | output_address (XEXP (adjust_address_nv (x, SImode, |
8383 | UNITS_PER_WORD), | |
8384 | 0)); | |
ed8908e7 | 8385 | |
ba5e43aa | 8386 | if (small_data_operand (x, GET_MODE (x))) |
8fbd2dc7 MM |
8387 | fprintf (file, "@%s(%s)", SMALL_DATA_RELOC, |
8388 | reg_names[SMALL_DATA_REG]); | |
9854d9ed | 8389 | } |
9878760c | 8390 | return; |
9854d9ed | 8391 | |
9878760c RK |
8392 | case 'm': |
8393 | /* MB value for a mask operand. */ | |
b1765bde | 8394 | if (! mask_operand (x, SImode)) |
9878760c RK |
8395 | output_operand_lossage ("invalid %%m value"); |
8396 | ||
0ba1b2ff | 8397 | fprintf (file, "%d", extract_MB (x)); |
9878760c RK |
8398 | return; |
8399 | ||
8400 | case 'M': | |
8401 | /* ME value for a mask operand. */ | |
b1765bde | 8402 | if (! mask_operand (x, SImode)) |
a260abc9 | 8403 | output_operand_lossage ("invalid %%M value"); |
9878760c | 8404 | |
0ba1b2ff | 8405 | fprintf (file, "%d", extract_ME (x)); |
9878760c RK |
8406 | return; |
8407 | ||
81eace42 GK |
8408 | /* %n outputs the negative of its operand. */ |
8409 | ||
9878760c RK |
8410 | case 'N': |
8411 | /* Write the number of elements in the vector times 4. */ | |
8412 | if (GET_CODE (x) != PARALLEL) | |
8413 | output_operand_lossage ("invalid %%N value"); | |
e2c953b6 DE |
8414 | else |
8415 | fprintf (file, "%d", XVECLEN (x, 0) * 4); | |
9878760c RK |
8416 | return; |
8417 | ||
8418 | case 'O': | |
8419 | /* Similar, but subtract 1 first. */ | |
8420 | if (GET_CODE (x) != PARALLEL) | |
1427100a | 8421 | output_operand_lossage ("invalid %%O value"); |
e2c953b6 DE |
8422 | else |
8423 | fprintf (file, "%d", (XVECLEN (x, 0) - 1) * 4); | |
9878760c RK |
8424 | return; |
8425 | ||
9854d9ed RK |
8426 | case 'p': |
8427 | /* X is a CONST_INT that is a power of two. Output the logarithm. */ | |
8428 | if (! INT_P (x) | |
2bfcf297 | 8429 | || INT_LOWPART (x) < 0 |
9854d9ed RK |
8430 | || (i = exact_log2 (INT_LOWPART (x))) < 0) |
8431 | output_operand_lossage ("invalid %%p value"); | |
e2c953b6 DE |
8432 | else |
8433 | fprintf (file, "%d", i); | |
9854d9ed RK |
8434 | return; |
8435 | ||
9878760c RK |
8436 | case 'P': |
8437 | /* The operand must be an indirect memory reference. The result | |
a4f6c312 | 8438 | is the register number. */ |
9878760c RK |
8439 | if (GET_CODE (x) != MEM || GET_CODE (XEXP (x, 0)) != REG |
8440 | || REGNO (XEXP (x, 0)) >= 32) | |
8441 | output_operand_lossage ("invalid %%P value"); | |
e2c953b6 DE |
8442 | else |
8443 | fprintf (file, "%d", REGNO (XEXP (x, 0))); | |
9878760c RK |
8444 | return; |
8445 | ||
dfbdccdb GK |
8446 | case 'q': |
8447 | /* This outputs the logical code corresponding to a boolean | |
8448 | expression. The expression may have one or both operands | |
39a10a29 GK |
8449 | negated (if one, only the first one). For condition register |
8450 | logical operations, it will also treat the negated | |
8451 | CR codes as NOTs, but not handle NOTs of them. */ | |
dfbdccdb | 8452 | { |
63bc1d05 | 8453 | const char *const *t = 0; |
dfbdccdb GK |
8454 | const char *s; |
8455 | enum rtx_code code = GET_CODE (x); | |
8456 | static const char * const tbl[3][3] = { | |
8457 | { "and", "andc", "nor" }, | |
8458 | { "or", "orc", "nand" }, | |
8459 | { "xor", "eqv", "xor" } }; | |
8460 | ||
8461 | if (code == AND) | |
8462 | t = tbl[0]; | |
8463 | else if (code == IOR) | |
8464 | t = tbl[1]; | |
8465 | else if (code == XOR) | |
8466 | t = tbl[2]; | |
8467 | else | |
8468 | output_operand_lossage ("invalid %%q value"); | |
8469 | ||
8470 | if (GET_CODE (XEXP (x, 0)) != NOT) | |
8471 | s = t[0]; | |
8472 | else | |
8473 | { | |
8474 | if (GET_CODE (XEXP (x, 1)) == NOT) | |
8475 | s = t[2]; | |
8476 | else | |
8477 | s = t[1]; | |
8478 | } | |
8479 | ||
8480 | fputs (s, file); | |
8481 | } | |
8482 | return; | |
8483 | ||
9854d9ed RK |
8484 | case 'R': |
8485 | /* X is a CR register. Print the mask for `mtcrf'. */ | |
8486 | if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x))) | |
8487 | output_operand_lossage ("invalid %%R value"); | |
8488 | else | |
9ebbca7d | 8489 | fprintf (file, "%d", 128 >> (REGNO (x) - CR0_REGNO)); |
9878760c | 8490 | return; |
9854d9ed RK |
8491 | |
8492 | case 's': | |
8493 | /* Low 5 bits of 32 - value */ | |
8494 | if (! INT_P (x)) | |
8495 | output_operand_lossage ("invalid %%s value"); | |
e2c953b6 DE |
8496 | else |
8497 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, (32 - INT_LOWPART (x)) & 31); | |
9878760c | 8498 | return; |
9854d9ed | 8499 | |
a260abc9 | 8500 | case 'S': |
0ba1b2ff | 8501 | /* PowerPC64 mask position. All 0's is excluded. |
a260abc9 DE |
8502 | CONST_INT 32-bit mask is considered sign-extended so any |
8503 | transition must occur within the CONST_INT, not on the boundary. */ | |
b1765bde | 8504 | if (! mask64_operand (x, DImode)) |
a260abc9 DE |
8505 | output_operand_lossage ("invalid %%S value"); |
8506 | ||
0ba1b2ff | 8507 | uval = INT_LOWPART (x); |
a260abc9 | 8508 | |
0ba1b2ff | 8509 | if (uval & 1) /* Clear Left */ |
a260abc9 | 8510 | { |
f099d360 GK |
8511 | #if HOST_BITS_PER_WIDE_INT > 64 |
8512 | uval &= ((unsigned HOST_WIDE_INT) 1 << 64) - 1; | |
8513 | #endif | |
0ba1b2ff | 8514 | i = 64; |
a260abc9 | 8515 | } |
0ba1b2ff | 8516 | else /* Clear Right */ |
a260abc9 | 8517 | { |
0ba1b2ff | 8518 | uval = ~uval; |
f099d360 GK |
8519 | #if HOST_BITS_PER_WIDE_INT > 64 |
8520 | uval &= ((unsigned HOST_WIDE_INT) 1 << 64) - 1; | |
8521 | #endif | |
0ba1b2ff | 8522 | i = 63; |
a260abc9 | 8523 | } |
0ba1b2ff AM |
8524 | while (uval != 0) |
8525 | --i, uval >>= 1; | |
8526 | if (i < 0) | |
8527 | abort (); | |
8528 | fprintf (file, "%d", i); | |
8529 | return; | |
a260abc9 | 8530 | |
a3170dc6 AH |
8531 | case 't': |
8532 | /* Like 'J' but get to the OVERFLOW/UNORDERED bit. */ | |
8533 | if (GET_CODE (x) != REG || GET_MODE (x) != CCmode) | |
8534 | abort (); | |
8535 | ||
8536 | /* Bit 3 is OV bit. */ | |
8537 | i = 4 * (REGNO (x) - CR0_REGNO) + 3; | |
8538 | ||
8539 | /* If we want bit 31, write a shift count of zero, not 32. */ | |
8540 | fprintf (file, "%d", i == 31 ? 0 : i + 1); | |
8541 | return; | |
8542 | ||
cccf3bdc DE |
8543 | case 'T': |
8544 | /* Print the symbolic name of a branch target register. */ | |
8545 | if (GET_CODE (x) != REG || (REGNO (x) != LINK_REGISTER_REGNUM | |
8546 | && REGNO (x) != COUNT_REGISTER_REGNUM)) | |
8547 | output_operand_lossage ("invalid %%T value"); | |
e2c953b6 | 8548 | else if (REGNO (x) == LINK_REGISTER_REGNUM) |
cccf3bdc DE |
8549 | fputs (TARGET_NEW_MNEMONICS ? "lr" : "r", file); |
8550 | else | |
8551 | fputs ("ctr", file); | |
8552 | return; | |
8553 | ||
9854d9ed | 8554 | case 'u': |
802a0058 | 8555 | /* High-order 16 bits of constant for use in unsigned operand. */ |
9854d9ed RK |
8556 | if (! INT_P (x)) |
8557 | output_operand_lossage ("invalid %%u value"); | |
e2c953b6 DE |
8558 | else |
8559 | fprintf (file, HOST_WIDE_INT_PRINT_HEX, | |
8560 | (INT_LOWPART (x) >> 16) & 0xffff); | |
9878760c RK |
8561 | return; |
8562 | ||
802a0058 MM |
8563 | case 'v': |
8564 | /* High-order 16 bits of constant for use in signed operand. */ | |
8565 | if (! INT_P (x)) | |
8566 | output_operand_lossage ("invalid %%v value"); | |
e2c953b6 | 8567 | else |
134c32f6 DE |
8568 | fprintf (file, HOST_WIDE_INT_PRINT_HEX, |
8569 | (INT_LOWPART (x) >> 16) & 0xffff); | |
8570 | return; | |
802a0058 | 8571 | |
9854d9ed RK |
8572 | case 'U': |
8573 | /* Print `u' if this has an auto-increment or auto-decrement. */ | |
8574 | if (GET_CODE (x) == MEM | |
8575 | && (GET_CODE (XEXP (x, 0)) == PRE_INC | |
8576 | || GET_CODE (XEXP (x, 0)) == PRE_DEC)) | |
76229ac8 | 8577 | putc ('u', file); |
9854d9ed | 8578 | return; |
9878760c | 8579 | |
e0cd0770 JC |
8580 | case 'V': |
8581 | /* Print the trap code for this operand. */ | |
8582 | switch (GET_CODE (x)) | |
8583 | { | |
8584 | case EQ: | |
8585 | fputs ("eq", file); /* 4 */ | |
8586 | break; | |
8587 | case NE: | |
8588 | fputs ("ne", file); /* 24 */ | |
8589 | break; | |
8590 | case LT: | |
8591 | fputs ("lt", file); /* 16 */ | |
8592 | break; | |
8593 | case LE: | |
8594 | fputs ("le", file); /* 20 */ | |
8595 | break; | |
8596 | case GT: | |
8597 | fputs ("gt", file); /* 8 */ | |
8598 | break; | |
8599 | case GE: | |
8600 | fputs ("ge", file); /* 12 */ | |
8601 | break; | |
8602 | case LTU: | |
8603 | fputs ("llt", file); /* 2 */ | |
8604 | break; | |
8605 | case LEU: | |
8606 | fputs ("lle", file); /* 6 */ | |
8607 | break; | |
8608 | case GTU: | |
8609 | fputs ("lgt", file); /* 1 */ | |
8610 | break; | |
8611 | case GEU: | |
8612 | fputs ("lge", file); /* 5 */ | |
8613 | break; | |
8614 | default: | |
8615 | abort (); | |
8616 | } | |
8617 | break; | |
8618 | ||
9854d9ed RK |
8619 | case 'w': |
8620 | /* If constant, low-order 16 bits of constant, signed. Otherwise, write | |
8621 | normally. */ | |
8622 | if (INT_P (x)) | |
5f59ecb7 DE |
8623 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, |
8624 | ((INT_LOWPART (x) & 0xffff) ^ 0x8000) - 0x8000); | |
9854d9ed RK |
8625 | else |
8626 | print_operand (file, x, 0); | |
9878760c RK |
8627 | return; |
8628 | ||
9854d9ed | 8629 | case 'W': |
e2c953b6 | 8630 | /* MB value for a PowerPC64 rldic operand. */ |
e2c953b6 DE |
8631 | val = (GET_CODE (x) == CONST_INT |
8632 | ? INTVAL (x) : CONST_DOUBLE_HIGH (x)); | |
8633 | ||
8634 | if (val < 0) | |
8635 | i = -1; | |
9854d9ed | 8636 | else |
e2c953b6 DE |
8637 | for (i = 0; i < HOST_BITS_PER_WIDE_INT; i++) |
8638 | if ((val <<= 1) < 0) | |
8639 | break; | |
8640 | ||
8641 | #if HOST_BITS_PER_WIDE_INT == 32 | |
8642 | if (GET_CODE (x) == CONST_INT && i >= 0) | |
8643 | i += 32; /* zero-extend high-part was all 0's */ | |
8644 | else if (GET_CODE (x) == CONST_DOUBLE && i == 32) | |
8645 | { | |
8646 | val = CONST_DOUBLE_LOW (x); | |
8647 | ||
8648 | if (val == 0) | |
a4f6c312 | 8649 | abort (); |
e2c953b6 DE |
8650 | else if (val < 0) |
8651 | --i; | |
8652 | else | |
8653 | for ( ; i < 64; i++) | |
8654 | if ((val <<= 1) < 0) | |
8655 | break; | |
8656 | } | |
8657 | #endif | |
8658 | ||
8659 | fprintf (file, "%d", i + 1); | |
9854d9ed | 8660 | return; |
9878760c | 8661 | |
9854d9ed RK |
8662 | case 'X': |
8663 | if (GET_CODE (x) == MEM | |
4d588c14 | 8664 | && legitimate_indexed_address_p (XEXP (x, 0), 0)) |
76229ac8 | 8665 | putc ('x', file); |
9854d9ed | 8666 | return; |
9878760c | 8667 | |
9854d9ed RK |
8668 | case 'Y': |
8669 | /* Like 'L', for third word of TImode */ | |
8670 | if (GET_CODE (x) == REG) | |
5ebfb2ba | 8671 | fprintf (file, "%s", reg_names[REGNO (x) + 2]); |
9854d9ed | 8672 | else if (GET_CODE (x) == MEM) |
9878760c | 8673 | { |
9854d9ed RK |
8674 | if (GET_CODE (XEXP (x, 0)) == PRE_INC |
8675 | || GET_CODE (XEXP (x, 0)) == PRE_DEC) | |
a54d04b7 | 8676 | output_address (plus_constant (XEXP (XEXP (x, 0), 0), 8)); |
9854d9ed | 8677 | else |
d7624dc0 | 8678 | output_address (XEXP (adjust_address_nv (x, SImode, 8), 0)); |
ba5e43aa | 8679 | if (small_data_operand (x, GET_MODE (x))) |
8fbd2dc7 MM |
8680 | fprintf (file, "@%s(%s)", SMALL_DATA_RELOC, |
8681 | reg_names[SMALL_DATA_REG]); | |
9878760c RK |
8682 | } |
8683 | return; | |
9854d9ed | 8684 | |
9878760c | 8685 | case 'z': |
b4ac57ab RS |
8686 | /* X is a SYMBOL_REF. Write out the name preceded by a |
8687 | period and without any trailing data in brackets. Used for function | |
4d30c363 MM |
8688 | names. If we are configured for System V (or the embedded ABI) on |
8689 | the PowerPC, do not emit the period, since those systems do not use | |
8690 | TOCs and the like. */ | |
9878760c RK |
8691 | if (GET_CODE (x) != SYMBOL_REF) |
8692 | abort (); | |
8693 | ||
b6c9286a MM |
8694 | if (XSTR (x, 0)[0] != '.') |
8695 | { | |
8696 | switch (DEFAULT_ABI) | |
8697 | { | |
8698 | default: | |
8699 | abort (); | |
8700 | ||
8701 | case ABI_AIX: | |
8702 | putc ('.', file); | |
8703 | break; | |
8704 | ||
8705 | case ABI_V4: | |
ee890fe2 | 8706 | case ABI_DARWIN: |
b6c9286a | 8707 | break; |
b6c9286a MM |
8708 | } |
8709 | } | |
9739c90c JJ |
8710 | if (TARGET_AIX) |
8711 | RS6000_OUTPUT_BASENAME (file, XSTR (x, 0)); | |
8712 | else | |
8713 | assemble_name (file, XSTR (x, 0)); | |
9878760c RK |
8714 | return; |
8715 | ||
9854d9ed RK |
8716 | case 'Z': |
8717 | /* Like 'L', for last word of TImode. */ | |
8718 | if (GET_CODE (x) == REG) | |
5ebfb2ba | 8719 | fprintf (file, "%s", reg_names[REGNO (x) + 3]); |
9854d9ed RK |
8720 | else if (GET_CODE (x) == MEM) |
8721 | { | |
8722 | if (GET_CODE (XEXP (x, 0)) == PRE_INC | |
8723 | || GET_CODE (XEXP (x, 0)) == PRE_DEC) | |
a54d04b7 | 8724 | output_address (plus_constant (XEXP (XEXP (x, 0), 0), 12)); |
9854d9ed | 8725 | else |
d7624dc0 | 8726 | output_address (XEXP (adjust_address_nv (x, SImode, 12), 0)); |
ba5e43aa | 8727 | if (small_data_operand (x, GET_MODE (x))) |
8fbd2dc7 MM |
8728 | fprintf (file, "@%s(%s)", SMALL_DATA_RELOC, |
8729 | reg_names[SMALL_DATA_REG]); | |
9854d9ed | 8730 | } |
5c23c401 | 8731 | return; |
0ac081f6 | 8732 | |
a3170dc6 | 8733 | /* Print AltiVec or SPE memory operand. */ |
0ac081f6 AH |
8734 | case 'y': |
8735 | { | |
8736 | rtx tmp; | |
8737 | ||
8738 | if (GET_CODE (x) != MEM) | |
8739 | abort (); | |
8740 | ||
8741 | tmp = XEXP (x, 0); | |
8742 | ||
993f19a8 | 8743 | if (TARGET_E500) |
a3170dc6 AH |
8744 | { |
8745 | /* Handle [reg]. */ | |
8746 | if (GET_CODE (tmp) == REG) | |
8747 | { | |
8748 | fprintf (file, "0(%s)", reg_names[REGNO (tmp)]); | |
8749 | break; | |
8750 | } | |
8751 | /* Handle [reg+UIMM]. */ | |
8752 | else if (GET_CODE (tmp) == PLUS && | |
8753 | GET_CODE (XEXP (tmp, 1)) == CONST_INT) | |
8754 | { | |
8755 | int x; | |
8756 | ||
8757 | if (GET_CODE (XEXP (tmp, 0)) != REG) | |
8758 | abort (); | |
8759 | ||
8760 | x = INTVAL (XEXP (tmp, 1)); | |
8761 | fprintf (file, "%d(%s)", x, reg_names[REGNO (XEXP (tmp, 0))]); | |
8762 | break; | |
8763 | } | |
8764 | ||
8765 | /* Fall through. Must be [reg+reg]. */ | |
8766 | } | |
0ac081f6 | 8767 | if (GET_CODE (tmp) == REG) |
c62f2db5 | 8768 | fprintf (file, "0,%s", reg_names[REGNO (tmp)]); |
0ac081f6 AH |
8769 | else if (GET_CODE (tmp) == PLUS && GET_CODE (XEXP (tmp, 1)) == REG) |
8770 | { | |
8771 | if (REGNO (XEXP (tmp, 0)) == 0) | |
8772 | fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 1)) ], | |
8773 | reg_names[ REGNO (XEXP (tmp, 0)) ]); | |
8774 | else | |
8775 | fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 0)) ], | |
8776 | reg_names[ REGNO (XEXP (tmp, 1)) ]); | |
8777 | } | |
8778 | else | |
8779 | abort (); | |
8780 | break; | |
8781 | } | |
9854d9ed | 8782 | |
9878760c RK |
8783 | case 0: |
8784 | if (GET_CODE (x) == REG) | |
8785 | fprintf (file, "%s", reg_names[REGNO (x)]); | |
8786 | else if (GET_CODE (x) == MEM) | |
8787 | { | |
8788 | /* We need to handle PRE_INC and PRE_DEC here, since we need to | |
8789 | know the width from the mode. */ | |
8790 | if (GET_CODE (XEXP (x, 0)) == PRE_INC) | |
79ba6d34 MM |
8791 | fprintf (file, "%d(%s)", GET_MODE_SIZE (GET_MODE (x)), |
8792 | reg_names[REGNO (XEXP (XEXP (x, 0), 0))]); | |
9878760c | 8793 | else if (GET_CODE (XEXP (x, 0)) == PRE_DEC) |
79ba6d34 MM |
8794 | fprintf (file, "%d(%s)", - GET_MODE_SIZE (GET_MODE (x)), |
8795 | reg_names[REGNO (XEXP (XEXP (x, 0), 0))]); | |
9878760c | 8796 | else |
a54d04b7 | 8797 | output_address (XEXP (x, 0)); |
9878760c RK |
8798 | } |
8799 | else | |
a54d04b7 | 8800 | output_addr_const (file, x); |
a85d226b | 8801 | return; |
9878760c | 8802 | |
c4501e62 JJ |
8803 | case '&': |
8804 | assemble_name (file, rs6000_get_some_local_dynamic_name ()); | |
8805 | return; | |
8806 | ||
9878760c RK |
8807 | default: |
8808 | output_operand_lossage ("invalid %%xn code"); | |
8809 | } | |
8810 | } | |
8811 | \f | |
8812 | /* Print the address of an operand. */ | |
8813 | ||
8814 | void | |
8815 | print_operand_address (file, x) | |
8816 | FILE *file; | |
592696dd | 8817 | rtx x; |
9878760c RK |
8818 | { |
8819 | if (GET_CODE (x) == REG) | |
4697a36c | 8820 | fprintf (file, "0(%s)", reg_names[ REGNO (x) ]); |
9ebbca7d GK |
8821 | else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST |
8822 | || GET_CODE (x) == LABEL_REF) | |
9878760c RK |
8823 | { |
8824 | output_addr_const (file, x); | |
ba5e43aa | 8825 | if (small_data_operand (x, GET_MODE (x))) |
8fbd2dc7 MM |
8826 | fprintf (file, "@%s(%s)", SMALL_DATA_RELOC, |
8827 | reg_names[SMALL_DATA_REG]); | |
9ebbca7d | 8828 | else if (TARGET_TOC) |
a4f6c312 | 8829 | abort (); |
9878760c RK |
8830 | } |
8831 | else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == REG) | |
8832 | { | |
8833 | if (REGNO (XEXP (x, 0)) == 0) | |
4697a36c MM |
8834 | fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 1)) ], |
8835 | reg_names[ REGNO (XEXP (x, 0)) ]); | |
9878760c | 8836 | else |
4697a36c MM |
8837 | fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 0)) ], |
8838 | reg_names[ REGNO (XEXP (x, 1)) ]); | |
9878760c RK |
8839 | } |
8840 | else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT) | |
4a0a75dd KG |
8841 | fprintf (file, HOST_WIDE_INT_PRINT_DEC "(%s)", |
8842 | INTVAL (XEXP (x, 1)), reg_names[ REGNO (XEXP (x, 0)) ]); | |
3cb999d8 DE |
8843 | #if TARGET_ELF |
8844 | else if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 0)) == REG | |
8845 | && CONSTANT_P (XEXP (x, 1))) | |
4697a36c MM |
8846 | { |
8847 | output_addr_const (file, XEXP (x, 1)); | |
8848 | fprintf (file, "@l(%s)", reg_names[ REGNO (XEXP (x, 0)) ]); | |
8849 | } | |
c859cda6 DJ |
8850 | #endif |
8851 | #if TARGET_MACHO | |
8852 | else if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 0)) == REG | |
8853 | && CONSTANT_P (XEXP (x, 1))) | |
8854 | { | |
8855 | fprintf (file, "lo16("); | |
8856 | output_addr_const (file, XEXP (x, 1)); | |
8857 | fprintf (file, ")(%s)", reg_names[ REGNO (XEXP (x, 0)) ]); | |
8858 | } | |
3cb999d8 | 8859 | #endif |
4d588c14 | 8860 | else if (legitimate_constant_pool_address_p (x)) |
9ebbca7d | 8861 | { |
2bfcf297 | 8862 | if (TARGET_AIX && (!TARGET_ELF || !TARGET_MINIMAL_TOC)) |
9ebbca7d | 8863 | { |
2bfcf297 DB |
8864 | rtx contains_minus = XEXP (x, 1); |
8865 | rtx minus, symref; | |
8866 | const char *name; | |
9ebbca7d GK |
8867 | |
8868 | /* Find the (minus (sym) (toc)) buried in X, and temporarily | |
a4f6c312 | 8869 | turn it into (sym) for output_addr_const. */ |
9ebbca7d GK |
8870 | while (GET_CODE (XEXP (contains_minus, 0)) != MINUS) |
8871 | contains_minus = XEXP (contains_minus, 0); | |
8872 | ||
2bfcf297 DB |
8873 | minus = XEXP (contains_minus, 0); |
8874 | symref = XEXP (minus, 0); | |
8875 | XEXP (contains_minus, 0) = symref; | |
8876 | if (TARGET_ELF) | |
8877 | { | |
8878 | char *newname; | |
8879 | ||
8880 | name = XSTR (symref, 0); | |
8881 | newname = alloca (strlen (name) + sizeof ("@toc")); | |
8882 | strcpy (newname, name); | |
8883 | strcat (newname, "@toc"); | |
8884 | XSTR (symref, 0) = newname; | |
8885 | } | |
8886 | output_addr_const (file, XEXP (x, 1)); | |
8887 | if (TARGET_ELF) | |
8888 | XSTR (symref, 0) = name; | |
9ebbca7d GK |
8889 | XEXP (contains_minus, 0) = minus; |
8890 | } | |
8891 | else | |
8892 | output_addr_const (file, XEXP (x, 1)); | |
8893 | ||
8894 | fprintf (file, "(%s)", reg_names[REGNO (XEXP (x, 0))]); | |
8895 | } | |
9878760c RK |
8896 | else |
8897 | abort (); | |
8898 | } | |
8899 | \f | |
88cad84b | 8900 | /* Target hook for assembling integer objects. The PowerPC version has |
301d03af RS |
8901 | to handle fixup entries for relocatable code if RELOCATABLE_NEEDS_FIXUP |
8902 | is defined. It also needs to handle DI-mode objects on 64-bit | |
8903 | targets. */ | |
8904 | ||
8905 | static bool | |
8906 | rs6000_assemble_integer (x, size, aligned_p) | |
8907 | rtx x; | |
8908 | unsigned int size; | |
8909 | int aligned_p; | |
8910 | { | |
8911 | #ifdef RELOCATABLE_NEEDS_FIXUP | |
8912 | /* Special handling for SI values. */ | |
8913 | if (size == 4 && aligned_p) | |
8914 | { | |
8915 | extern int in_toc_section PARAMS ((void)); | |
8916 | static int recurse = 0; | |
8917 | ||
8918 | /* For -mrelocatable, we mark all addresses that need to be fixed up | |
8919 | in the .fixup section. */ | |
8920 | if (TARGET_RELOCATABLE | |
8921 | && !in_toc_section () | |
8922 | && !in_text_section () | |
8923 | && !recurse | |
8924 | && GET_CODE (x) != CONST_INT | |
8925 | && GET_CODE (x) != CONST_DOUBLE | |
8926 | && CONSTANT_P (x)) | |
8927 | { | |
8928 | char buf[256]; | |
8929 | ||
8930 | recurse = 1; | |
8931 | ASM_GENERATE_INTERNAL_LABEL (buf, "LCP", fixuplabelno); | |
8932 | fixuplabelno++; | |
8933 | ASM_OUTPUT_LABEL (asm_out_file, buf); | |
8934 | fprintf (asm_out_file, "\t.long\t("); | |
8935 | output_addr_const (asm_out_file, x); | |
8936 | fprintf (asm_out_file, ")@fixup\n"); | |
8937 | fprintf (asm_out_file, "\t.section\t\".fixup\",\"aw\"\n"); | |
8938 | ASM_OUTPUT_ALIGN (asm_out_file, 2); | |
8939 | fprintf (asm_out_file, "\t.long\t"); | |
8940 | assemble_name (asm_out_file, buf); | |
8941 | fprintf (asm_out_file, "\n\t.previous\n"); | |
8942 | recurse = 0; | |
8943 | return true; | |
8944 | } | |
8945 | /* Remove initial .'s to turn a -mcall-aixdesc function | |
8946 | address into the address of the descriptor, not the function | |
8947 | itself. */ | |
8948 | else if (GET_CODE (x) == SYMBOL_REF | |
8949 | && XSTR (x, 0)[0] == '.' | |
8950 | && DEFAULT_ABI == ABI_AIX) | |
8951 | { | |
8952 | const char *name = XSTR (x, 0); | |
8953 | while (*name == '.') | |
8954 | name++; | |
8955 | ||
8956 | fprintf (asm_out_file, "\t.long\t%s\n", name); | |
8957 | return true; | |
8958 | } | |
8959 | } | |
8960 | #endif /* RELOCATABLE_NEEDS_FIXUP */ | |
8961 | return default_assemble_integer (x, size, aligned_p); | |
8962 | } | |
93638d7a AM |
8963 | |
8964 | #ifdef HAVE_GAS_HIDDEN | |
8965 | /* Emit an assembler directive to set symbol visibility for DECL to | |
8966 | VISIBILITY_TYPE. */ | |
8967 | ||
5add3202 | 8968 | static void |
25fdb4dc | 8969 | rs6000_assemble_visibility (decl, vis) |
93638d7a | 8970 | tree decl; |
25fdb4dc | 8971 | int vis; |
93638d7a | 8972 | { |
93638d7a AM |
8973 | /* Functions need to have their entry point symbol visibility set as |
8974 | well as their descriptor symbol visibility. */ | |
8975 | if (DEFAULT_ABI == ABI_AIX && TREE_CODE (decl) == FUNCTION_DECL) | |
8976 | { | |
25fdb4dc RH |
8977 | static const char * const visibility_types[] = { |
8978 | NULL, "internal", "hidden", "protected" | |
8979 | }; | |
8980 | ||
8981 | const char *name, *type; | |
93638d7a AM |
8982 | |
8983 | name = ((* targetm.strip_name_encoding) | |
8984 | (IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl)))); | |
25fdb4dc | 8985 | type = visibility_types[vis]; |
93638d7a | 8986 | |
25fdb4dc RH |
8987 | fprintf (asm_out_file, "\t.%s\t%s\n", type, name); |
8988 | fprintf (asm_out_file, "\t.%s\t.%s\n", type, name); | |
93638d7a | 8989 | } |
25fdb4dc RH |
8990 | else |
8991 | default_assemble_visibility (decl, vis); | |
93638d7a AM |
8992 | } |
8993 | #endif | |
301d03af | 8994 | \f |
39a10a29 GK |
8995 | enum rtx_code |
8996 | rs6000_reverse_condition (mode, code) | |
8997 | enum machine_mode mode; | |
8998 | enum rtx_code code; | |
8999 | { | |
9000 | /* Reversal of FP compares takes care -- an ordered compare | |
9001 | becomes an unordered compare and vice versa. */ | |
bc9ec0e0 GK |
9002 | if (mode == CCFPmode |
9003 | && (!flag_finite_math_only | |
9004 | || code == UNLT || code == UNLE || code == UNGT || code == UNGE | |
9005 | || code == UNEQ || code == LTGT)) | |
bab6226b | 9006 | return reverse_condition_maybe_unordered (code); |
39a10a29 | 9007 | else |
bab6226b | 9008 | return reverse_condition (code); |
39a10a29 GK |
9009 | } |
9010 | ||
39a10a29 GK |
9011 | /* Generate a compare for CODE. Return a brand-new rtx that |
9012 | represents the result of the compare. */ | |
a4f6c312 | 9013 | |
39a10a29 GK |
9014 | static rtx |
9015 | rs6000_generate_compare (code) | |
9016 | enum rtx_code code; | |
9017 | { | |
9018 | enum machine_mode comp_mode; | |
9019 | rtx compare_result; | |
9020 | ||
9021 | if (rs6000_compare_fp_p) | |
9022 | comp_mode = CCFPmode; | |
9023 | else if (code == GTU || code == LTU | |
9024 | || code == GEU || code == LEU) | |
9025 | comp_mode = CCUNSmode; | |
9026 | else | |
9027 | comp_mode = CCmode; | |
9028 | ||
9029 | /* First, the compare. */ | |
9030 | compare_result = gen_reg_rtx (comp_mode); | |
a3170dc6 AH |
9031 | |
9032 | /* SPE FP compare instructions on the GPRs. Yuck! */ | |
993f19a8 AH |
9033 | if ((TARGET_E500 && !TARGET_FPRS && TARGET_HARD_FLOAT) |
9034 | && rs6000_compare_fp_p) | |
a3170dc6 AH |
9035 | { |
9036 | rtx cmp, or1, or2, or_result, compare_result2; | |
9037 | ||
9038 | switch (code) | |
9039 | { | |
9040 | case EQ: | |
9041 | case UNEQ: | |
9042 | case NE: | |
9043 | case LTGT: | |
bc9ec0e0 | 9044 | cmp = flag_finite_math_only |
a3170dc6 AH |
9045 | ? gen_tstsfeq_gpr (compare_result, rs6000_compare_op0, |
9046 | rs6000_compare_op1) | |
9047 | : gen_cmpsfeq_gpr (compare_result, rs6000_compare_op0, | |
9048 | rs6000_compare_op1); | |
9049 | break; | |
9050 | case GT: | |
9051 | case GTU: | |
9052 | case UNGT: | |
9053 | case UNGE: | |
9054 | case GE: | |
9055 | case GEU: | |
bc9ec0e0 | 9056 | cmp = flag_finite_math_only |
a3170dc6 AH |
9057 | ? gen_tstsfgt_gpr (compare_result, rs6000_compare_op0, |
9058 | rs6000_compare_op1) | |
9059 | : gen_cmpsfgt_gpr (compare_result, rs6000_compare_op0, | |
9060 | rs6000_compare_op1); | |
9061 | break; | |
9062 | case LT: | |
9063 | case LTU: | |
9064 | case UNLT: | |
9065 | case UNLE: | |
9066 | case LE: | |
9067 | case LEU: | |
bc9ec0e0 | 9068 | cmp = flag_finite_math_only |
a3170dc6 AH |
9069 | ? gen_tstsflt_gpr (compare_result, rs6000_compare_op0, |
9070 | rs6000_compare_op1) | |
9071 | : gen_cmpsflt_gpr (compare_result, rs6000_compare_op0, | |
9072 | rs6000_compare_op1); | |
9073 | break; | |
9074 | default: | |
9075 | abort (); | |
9076 | } | |
9077 | ||
9078 | /* Synthesize LE and GE from LT/GT || EQ. */ | |
9079 | if (code == LE || code == GE || code == LEU || code == GEU) | |
9080 | { | |
9081 | /* Synthesize GE/LE frome GT/LT || EQ. */ | |
9082 | ||
9083 | emit_insn (cmp); | |
9084 | ||
9085 | switch (code) | |
9086 | { | |
9087 | case LE: code = LT; break; | |
9088 | case GE: code = GT; break; | |
9089 | case LEU: code = LT; break; | |
9090 | case GEU: code = GT; break; | |
9091 | default: abort (); | |
9092 | } | |
9093 | ||
9094 | or1 = gen_reg_rtx (SImode); | |
9095 | or2 = gen_reg_rtx (SImode); | |
9096 | or_result = gen_reg_rtx (CCEQmode); | |
9097 | compare_result2 = gen_reg_rtx (CCFPmode); | |
9098 | ||
9099 | /* Do the EQ. */ | |
bc9ec0e0 | 9100 | cmp = flag_finite_math_only |
a3170dc6 AH |
9101 | ? gen_tstsfeq_gpr (compare_result2, rs6000_compare_op0, |
9102 | rs6000_compare_op1) | |
9103 | : gen_cmpsfeq_gpr (compare_result2, rs6000_compare_op0, | |
9104 | rs6000_compare_op1); | |
9105 | emit_insn (cmp); | |
9106 | ||
9107 | /* The MC8540 FP compare instructions set the CR bits | |
9108 | differently than other PPC compare instructions. For | |
9109 | that matter, there is no generic test instruction, but a | |
9110 | testgt, testlt, and testeq. For a true condition, bit 2 | |
9111 | is set (x1xx) in the CR. Following the traditional CR | |
9112 | values: | |
9113 | ||
9114 | LT GT EQ OV | |
9115 | bit3 bit2 bit1 bit0 | |
9116 | ||
9117 | ... bit 2 would be a GT CR alias, so later on we | |
b6d08ca1 | 9118 | look in the GT bits for the branch instructions. |
a3170dc6 AH |
9119 | However, we must be careful to emit correct RTL in |
9120 | the meantime, so optimizations don't get confused. */ | |
9121 | ||
9122 | or1 = gen_rtx (NE, SImode, compare_result, const0_rtx); | |
9123 | or2 = gen_rtx (NE, SImode, compare_result2, const0_rtx); | |
9124 | ||
9125 | /* OR them together. */ | |
9126 | cmp = gen_rtx_SET (VOIDmode, or_result, | |
9127 | gen_rtx_COMPARE (CCEQmode, | |
9128 | gen_rtx_IOR (SImode, or1, or2), | |
9129 | const_true_rtx)); | |
9130 | compare_result = or_result; | |
9131 | code = EQ; | |
9132 | } | |
9133 | else | |
9134 | { | |
9135 | /* We only care about 1 bit (x1xx), so map everything to NE to | |
9136 | maintain rtl sanity. We'll get to the right bit (x1xx) at | |
9137 | code output time. */ | |
9138 | if (code == NE || code == LTGT) | |
9139 | /* Do the inverse here because we have no cmpne | |
9140 | instruction. We use the cmpeq instruction and expect | |
9141 | to get a 0 instead. */ | |
9142 | code = EQ; | |
9143 | else | |
9144 | code = NE; | |
9145 | } | |
9146 | ||
9147 | emit_insn (cmp); | |
9148 | } | |
9149 | else | |
9150 | emit_insn (gen_rtx_SET (VOIDmode, compare_result, | |
9151 | gen_rtx_COMPARE (comp_mode, | |
9152 | rs6000_compare_op0, | |
9153 | rs6000_compare_op1))); | |
39a10a29 | 9154 | |
ca5adc63 | 9155 | /* Some kinds of FP comparisons need an OR operation; |
bc9ec0e0 | 9156 | under flag_finite_math_only we don't bother. */ |
39a10a29 | 9157 | if (rs6000_compare_fp_p |
bc9ec0e0 | 9158 | && ! flag_finite_math_only |
993f19a8 | 9159 | && ! (TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS) |
39a10a29 GK |
9160 | && (code == LE || code == GE |
9161 | || code == UNEQ || code == LTGT | |
9162 | || code == UNGT || code == UNLT)) | |
9163 | { | |
9164 | enum rtx_code or1, or2; | |
9165 | rtx or1_rtx, or2_rtx, compare2_rtx; | |
9166 | rtx or_result = gen_reg_rtx (CCEQmode); | |
9167 | ||
9168 | switch (code) | |
9169 | { | |
9170 | case LE: or1 = LT; or2 = EQ; break; | |
9171 | case GE: or1 = GT; or2 = EQ; break; | |
9172 | case UNEQ: or1 = UNORDERED; or2 = EQ; break; | |
9173 | case LTGT: or1 = LT; or2 = GT; break; | |
9174 | case UNGT: or1 = UNORDERED; or2 = GT; break; | |
9175 | case UNLT: or1 = UNORDERED; or2 = LT; break; | |
9176 | default: abort (); | |
9177 | } | |
9178 | validate_condition_mode (or1, comp_mode); | |
9179 | validate_condition_mode (or2, comp_mode); | |
9180 | or1_rtx = gen_rtx (or1, SImode, compare_result, const0_rtx); | |
9181 | or2_rtx = gen_rtx (or2, SImode, compare_result, const0_rtx); | |
9182 | compare2_rtx = gen_rtx_COMPARE (CCEQmode, | |
9183 | gen_rtx_IOR (SImode, or1_rtx, or2_rtx), | |
9184 | const_true_rtx); | |
9185 | emit_insn (gen_rtx_SET (VOIDmode, or_result, compare2_rtx)); | |
9186 | ||
9187 | compare_result = or_result; | |
9188 | code = EQ; | |
9189 | } | |
9190 | ||
9191 | validate_condition_mode (code, GET_MODE (compare_result)); | |
9192 | ||
9193 | return gen_rtx (code, VOIDmode, compare_result, const0_rtx); | |
9194 | } | |
9195 | ||
9196 | ||
9197 | /* Emit the RTL for an sCOND pattern. */ | |
9198 | ||
9199 | void | |
9200 | rs6000_emit_sCOND (code, result) | |
9201 | enum rtx_code code; | |
9202 | rtx result; | |
9203 | { | |
9204 | rtx condition_rtx; | |
9205 | enum machine_mode op_mode; | |
b7053a3f | 9206 | enum rtx_code cond_code; |
39a10a29 GK |
9207 | |
9208 | condition_rtx = rs6000_generate_compare (code); | |
b7053a3f GK |
9209 | cond_code = GET_CODE (condition_rtx); |
9210 | ||
9211 | if (cond_code == NE | |
9212 | || cond_code == GE || cond_code == LE | |
9213 | || cond_code == GEU || cond_code == LEU | |
9214 | || cond_code == ORDERED || cond_code == UNGE || cond_code == UNLE) | |
9215 | { | |
9216 | rtx not_result = gen_reg_rtx (CCEQmode); | |
9217 | rtx not_op, rev_cond_rtx; | |
9218 | enum machine_mode cc_mode; | |
9219 | ||
9220 | cc_mode = GET_MODE (XEXP (condition_rtx, 0)); | |
9221 | ||
9222 | rev_cond_rtx = gen_rtx (rs6000_reverse_condition (cc_mode, cond_code), | |
9223 | SImode, XEXP (condition_rtx, 0), const0_rtx); | |
9224 | not_op = gen_rtx_COMPARE (CCEQmode, rev_cond_rtx, const0_rtx); | |
9225 | emit_insn (gen_rtx_SET (VOIDmode, not_result, not_op)); | |
9226 | condition_rtx = gen_rtx_EQ (VOIDmode, not_result, const0_rtx); | |
9227 | } | |
39a10a29 GK |
9228 | |
9229 | op_mode = GET_MODE (rs6000_compare_op0); | |
9230 | if (op_mode == VOIDmode) | |
9231 | op_mode = GET_MODE (rs6000_compare_op1); | |
9232 | ||
9233 | if (TARGET_POWERPC64 && (op_mode == DImode || rs6000_compare_fp_p)) | |
9234 | { | |
9235 | PUT_MODE (condition_rtx, DImode); | |
9236 | convert_move (result, condition_rtx, 0); | |
9237 | } | |
9238 | else | |
9239 | { | |
9240 | PUT_MODE (condition_rtx, SImode); | |
9241 | emit_insn (gen_rtx_SET (VOIDmode, result, condition_rtx)); | |
9242 | } | |
9243 | } | |
9244 | ||
39a10a29 GK |
9245 | /* Emit a branch of kind CODE to location LOC. */ |
9246 | ||
9247 | void | |
9248 | rs6000_emit_cbranch (code, loc) | |
9249 | enum rtx_code code; | |
9250 | rtx loc; | |
9251 | { | |
9252 | rtx condition_rtx, loc_ref; | |
9253 | ||
9254 | condition_rtx = rs6000_generate_compare (code); | |
9255 | loc_ref = gen_rtx_LABEL_REF (VOIDmode, loc); | |
9256 | emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, | |
9257 | gen_rtx_IF_THEN_ELSE (VOIDmode, condition_rtx, | |
9258 | loc_ref, pc_rtx))); | |
9259 | } | |
9260 | ||
12a4e8c5 GK |
9261 | /* Return the string to output a conditional branch to LABEL, which is |
9262 | the operand number of the label, or -1 if the branch is really a | |
9263 | conditional return. | |
9264 | ||
9265 | OP is the conditional expression. XEXP (OP, 0) is assumed to be a | |
9266 | condition code register and its mode specifies what kind of | |
9267 | comparison we made. | |
9268 | ||
a0ab749a | 9269 | REVERSED is nonzero if we should reverse the sense of the comparison. |
12a4e8c5 GK |
9270 | |
9271 | INSN is the insn. */ | |
9272 | ||
9273 | char * | |
9274 | output_cbranch (op, label, reversed, insn) | |
9275 | rtx op; | |
9276 | const char * label; | |
9277 | int reversed; | |
9278 | rtx insn; | |
9279 | { | |
9280 | static char string[64]; | |
9281 | enum rtx_code code = GET_CODE (op); | |
9282 | rtx cc_reg = XEXP (op, 0); | |
9283 | enum machine_mode mode = GET_MODE (cc_reg); | |
9284 | int cc_regno = REGNO (cc_reg) - CR0_REGNO; | |
39a10a29 | 9285 | int need_longbranch = label != NULL && get_attr_length (insn) == 8; |
12a4e8c5 GK |
9286 | int really_reversed = reversed ^ need_longbranch; |
9287 | char *s = string; | |
9288 | const char *ccode; | |
9289 | const char *pred; | |
9290 | rtx note; | |
9291 | ||
39a10a29 GK |
9292 | validate_condition_mode (code, mode); |
9293 | ||
9294 | /* Work out which way this really branches. We could use | |
9295 | reverse_condition_maybe_unordered here always but this | |
9296 | makes the resulting assembler clearer. */ | |
12a4e8c5 | 9297 | if (really_reversed) |
de40e1df DJ |
9298 | { |
9299 | /* Reversal of FP compares takes care -- an ordered compare | |
9300 | becomes an unordered compare and vice versa. */ | |
9301 | if (mode == CCFPmode) | |
9302 | code = reverse_condition_maybe_unordered (code); | |
9303 | else | |
9304 | code = reverse_condition (code); | |
9305 | } | |
12a4e8c5 | 9306 | |
993f19a8 | 9307 | if ((TARGET_E500 && !TARGET_FPRS && TARGET_HARD_FLOAT) && mode == CCFPmode) |
a3170dc6 AH |
9308 | { |
9309 | /* The efscmp/tst* instructions twiddle bit 2, which maps nicely | |
9310 | to the GT bit. */ | |
9311 | if (code == EQ) | |
9312 | /* Opposite of GT. */ | |
9313 | code = UNLE; | |
9314 | else if (code == NE) | |
9315 | code = GT; | |
9316 | else | |
9317 | abort (); | |
9318 | } | |
9319 | ||
39a10a29 | 9320 | switch (code) |
12a4e8c5 GK |
9321 | { |
9322 | /* Not all of these are actually distinct opcodes, but | |
9323 | we distinguish them for clarity of the resulting assembler. */ | |
50a0b056 GK |
9324 | case NE: case LTGT: |
9325 | ccode = "ne"; break; | |
9326 | case EQ: case UNEQ: | |
9327 | ccode = "eq"; break; | |
9328 | case GE: case GEU: | |
9329 | ccode = "ge"; break; | |
9330 | case GT: case GTU: case UNGT: | |
9331 | ccode = "gt"; break; | |
9332 | case LE: case LEU: | |
9333 | ccode = "le"; break; | |
9334 | case LT: case LTU: case UNLT: | |
9335 | ccode = "lt"; break; | |
12a4e8c5 GK |
9336 | case UNORDERED: ccode = "un"; break; |
9337 | case ORDERED: ccode = "nu"; break; | |
9338 | case UNGE: ccode = "nl"; break; | |
9339 | case UNLE: ccode = "ng"; break; | |
9340 | default: | |
a4f6c312 | 9341 | abort (); |
12a4e8c5 GK |
9342 | } |
9343 | ||
94a54f47 GK |
9344 | /* Maybe we have a guess as to how likely the branch is. |
9345 | The old mnemonics don't have a way to specify this information. */ | |
f4857b9b | 9346 | pred = ""; |
12a4e8c5 GK |
9347 | note = find_reg_note (insn, REG_BR_PROB, NULL_RTX); |
9348 | if (note != NULL_RTX) | |
9349 | { | |
9350 | /* PROB is the difference from 50%. */ | |
9351 | int prob = INTVAL (XEXP (note, 0)) - REG_BR_PROB_BASE / 2; | |
f4857b9b AM |
9352 | bool always_hint = rs6000_cpu != PROCESSOR_POWER4; |
9353 | ||
9354 | /* Only hint for highly probable/improbable branches on newer | |
9355 | cpus as static prediction overrides processor dynamic | |
9356 | prediction. For older cpus we may as well always hint, but | |
9357 | assume not taken for branches that are very close to 50% as a | |
9358 | mispredicted taken branch is more expensive than a | |
9359 | mispredicted not-taken branch. */ | |
9360 | if (always_hint | |
9361 | || abs (prob) > REG_BR_PROB_BASE / 100 * 48) | |
9362 | { | |
9363 | if (abs (prob) > REG_BR_PROB_BASE / 20 | |
9364 | && ((prob > 0) ^ need_longbranch)) | |
7f3d8013 | 9365 | pred = "+"; |
f4857b9b AM |
9366 | else |
9367 | pred = "-"; | |
9368 | } | |
12a4e8c5 | 9369 | } |
12a4e8c5 GK |
9370 | |
9371 | if (label == NULL) | |
94a54f47 | 9372 | s += sprintf (s, "{b%sr|b%slr%s} ", ccode, ccode, pred); |
12a4e8c5 | 9373 | else |
94a54f47 | 9374 | s += sprintf (s, "{b%s|b%s%s} ", ccode, ccode, pred); |
12a4e8c5 | 9375 | |
37c67319 GK |
9376 | /* We need to escape any '%' characters in the reg_names string. |
9377 | Assume they'd only be the first character... */ | |
9378 | if (reg_names[cc_regno + CR0_REGNO][0] == '%') | |
9379 | *s++ = '%'; | |
94a54f47 | 9380 | s += sprintf (s, "%s", reg_names[cc_regno + CR0_REGNO]); |
12a4e8c5 GK |
9381 | |
9382 | if (label != NULL) | |
9383 | { | |
9384 | /* If the branch distance was too far, we may have to use an | |
9385 | unconditional branch to go the distance. */ | |
9386 | if (need_longbranch) | |
44518ddd | 9387 | s += sprintf (s, ",$+8\n\tb %s", label); |
12a4e8c5 GK |
9388 | else |
9389 | s += sprintf (s, ",%s", label); | |
9390 | } | |
9391 | ||
9392 | return string; | |
9393 | } | |
50a0b056 GK |
9394 | |
9395 | /* Emit a conditional move: move TRUE_COND to DEST if OP of the | |
9396 | operands of the last comparison is nonzero/true, FALSE_COND if it | |
9397 | is zero/false. Return 0 if the hardware has no such operation. */ | |
a4f6c312 | 9398 | |
50a0b056 GK |
9399 | int |
9400 | rs6000_emit_cmove (dest, op, true_cond, false_cond) | |
9401 | rtx dest; | |
9402 | rtx op; | |
9403 | rtx true_cond; | |
9404 | rtx false_cond; | |
9405 | { | |
9406 | enum rtx_code code = GET_CODE (op); | |
9407 | rtx op0 = rs6000_compare_op0; | |
9408 | rtx op1 = rs6000_compare_op1; | |
9409 | REAL_VALUE_TYPE c1; | |
3148ad6d DJ |
9410 | enum machine_mode compare_mode = GET_MODE (op0); |
9411 | enum machine_mode result_mode = GET_MODE (dest); | |
50a0b056 GK |
9412 | rtx temp; |
9413 | ||
3148ad6d | 9414 | /* These modes should always match. */ |
a3170dc6 AH |
9415 | if (GET_MODE (op1) != compare_mode |
9416 | /* In the isel case however, we can use a compare immediate, so | |
9417 | op1 may be a small constant. */ | |
9418 | && (!TARGET_ISEL || !short_cint_operand (op1, VOIDmode))) | |
3148ad6d | 9419 | return 0; |
178c3eff | 9420 | if (GET_MODE (true_cond) != result_mode) |
3148ad6d | 9421 | return 0; |
178c3eff | 9422 | if (GET_MODE (false_cond) != result_mode) |
3148ad6d DJ |
9423 | return 0; |
9424 | ||
50a0b056 GK |
9425 | /* First, work out if the hardware can do this at all, or |
9426 | if it's too slow... */ | |
50a0b056 | 9427 | if (! rs6000_compare_fp_p) |
a3170dc6 AH |
9428 | { |
9429 | if (TARGET_ISEL) | |
9430 | return rs6000_emit_int_cmove (dest, op, true_cond, false_cond); | |
9431 | return 0; | |
9432 | } | |
50a0b056 GK |
9433 | |
9434 | /* Eliminate half of the comparisons by switching operands, this | |
9435 | makes the remaining code simpler. */ | |
9436 | if (code == UNLT || code == UNGT || code == UNORDERED || code == NE | |
bc9ec0e0 | 9437 | || code == LTGT || code == LT || code == UNLE) |
50a0b056 GK |
9438 | { |
9439 | code = reverse_condition_maybe_unordered (code); | |
9440 | temp = true_cond; | |
9441 | true_cond = false_cond; | |
9442 | false_cond = temp; | |
9443 | } | |
9444 | ||
9445 | /* UNEQ and LTGT take four instructions for a comparison with zero, | |
9446 | it'll probably be faster to use a branch here too. */ | |
bc9ec0e0 | 9447 | if (code == UNEQ && HONOR_NANS (compare_mode)) |
50a0b056 GK |
9448 | return 0; |
9449 | ||
9450 | if (GET_CODE (op1) == CONST_DOUBLE) | |
9451 | REAL_VALUE_FROM_CONST_DOUBLE (c1, op1); | |
9452 | ||
b6d08ca1 | 9453 | /* We're going to try to implement comparisons by performing |
50a0b056 GK |
9454 | a subtract, then comparing against zero. Unfortunately, |
9455 | Inf - Inf is NaN which is not zero, and so if we don't | |
27d30956 | 9456 | know that the operand is finite and the comparison |
50a0b056 | 9457 | would treat EQ different to UNORDERED, we can't do it. */ |
bc9ec0e0 | 9458 | if (HONOR_INFINITIES (compare_mode) |
50a0b056 | 9459 | && code != GT && code != UNGE |
045572c7 | 9460 | && (GET_CODE (op1) != CONST_DOUBLE || real_isinf (&c1)) |
50a0b056 GK |
9461 | /* Constructs of the form (a OP b ? a : b) are safe. */ |
9462 | && ((! rtx_equal_p (op0, false_cond) && ! rtx_equal_p (op1, false_cond)) | |
9463 | || (! rtx_equal_p (op0, true_cond) | |
9464 | && ! rtx_equal_p (op1, true_cond)))) | |
9465 | return 0; | |
9466 | /* At this point we know we can use fsel. */ | |
9467 | ||
9468 | /* Reduce the comparison to a comparison against zero. */ | |
3148ad6d | 9469 | temp = gen_reg_rtx (compare_mode); |
50a0b056 | 9470 | emit_insn (gen_rtx_SET (VOIDmode, temp, |
3148ad6d | 9471 | gen_rtx_MINUS (compare_mode, op0, op1))); |
50a0b056 | 9472 | op0 = temp; |
3148ad6d | 9473 | op1 = CONST0_RTX (compare_mode); |
50a0b056 GK |
9474 | |
9475 | /* If we don't care about NaNs we can reduce some of the comparisons | |
9476 | down to faster ones. */ | |
bc9ec0e0 | 9477 | if (! HONOR_NANS (compare_mode)) |
50a0b056 GK |
9478 | switch (code) |
9479 | { | |
9480 | case GT: | |
9481 | code = LE; | |
9482 | temp = true_cond; | |
9483 | true_cond = false_cond; | |
9484 | false_cond = temp; | |
9485 | break; | |
9486 | case UNGE: | |
9487 | code = GE; | |
9488 | break; | |
9489 | case UNEQ: | |
9490 | code = EQ; | |
9491 | break; | |
9492 | default: | |
9493 | break; | |
9494 | } | |
9495 | ||
9496 | /* Now, reduce everything down to a GE. */ | |
9497 | switch (code) | |
9498 | { | |
9499 | case GE: | |
9500 | break; | |
9501 | ||
9502 | case LE: | |
3148ad6d DJ |
9503 | temp = gen_reg_rtx (compare_mode); |
9504 | emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0))); | |
50a0b056 GK |
9505 | op0 = temp; |
9506 | break; | |
9507 | ||
9508 | case ORDERED: | |
3148ad6d DJ |
9509 | temp = gen_reg_rtx (compare_mode); |
9510 | emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_ABS (compare_mode, op0))); | |
50a0b056 GK |
9511 | op0 = temp; |
9512 | break; | |
9513 | ||
9514 | case EQ: | |
3148ad6d | 9515 | temp = gen_reg_rtx (compare_mode); |
50a0b056 | 9516 | emit_insn (gen_rtx_SET (VOIDmode, temp, |
3148ad6d DJ |
9517 | gen_rtx_NEG (compare_mode, |
9518 | gen_rtx_ABS (compare_mode, op0)))); | |
50a0b056 GK |
9519 | op0 = temp; |
9520 | break; | |
9521 | ||
9522 | case UNGE: | |
bc9ec0e0 | 9523 | /* a UNGE 0 <-> (a GE 0 || -a UNLT 0) */ |
3148ad6d | 9524 | temp = gen_reg_rtx (result_mode); |
50a0b056 | 9525 | emit_insn (gen_rtx_SET (VOIDmode, temp, |
3148ad6d | 9526 | gen_rtx_IF_THEN_ELSE (result_mode, |
50a0b056 GK |
9527 | gen_rtx_GE (VOIDmode, |
9528 | op0, op1), | |
9529 | true_cond, false_cond))); | |
bc9ec0e0 GK |
9530 | false_cond = true_cond; |
9531 | true_cond = temp; | |
50a0b056 | 9532 | |
3148ad6d DJ |
9533 | temp = gen_reg_rtx (compare_mode); |
9534 | emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0))); | |
50a0b056 GK |
9535 | op0 = temp; |
9536 | break; | |
9537 | ||
9538 | case GT: | |
bc9ec0e0 | 9539 | /* a GT 0 <-> (a GE 0 && -a UNLT 0) */ |
3148ad6d | 9540 | temp = gen_reg_rtx (result_mode); |
50a0b056 | 9541 | emit_insn (gen_rtx_SET (VOIDmode, temp, |
3148ad6d | 9542 | gen_rtx_IF_THEN_ELSE (result_mode, |
50a0b056 GK |
9543 | gen_rtx_GE (VOIDmode, |
9544 | op0, op1), | |
9545 | true_cond, false_cond))); | |
bc9ec0e0 GK |
9546 | true_cond = false_cond; |
9547 | false_cond = temp; | |
50a0b056 | 9548 | |
3148ad6d DJ |
9549 | temp = gen_reg_rtx (compare_mode); |
9550 | emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0))); | |
50a0b056 GK |
9551 | op0 = temp; |
9552 | break; | |
9553 | ||
9554 | default: | |
9555 | abort (); | |
9556 | } | |
9557 | ||
9558 | emit_insn (gen_rtx_SET (VOIDmode, dest, | |
3148ad6d | 9559 | gen_rtx_IF_THEN_ELSE (result_mode, |
50a0b056 GK |
9560 | gen_rtx_GE (VOIDmode, |
9561 | op0, op1), | |
9562 | true_cond, false_cond))); | |
9563 | return 1; | |
9564 | } | |
9565 | ||
a3170dc6 AH |
9566 | /* Same as above, but for ints (isel). */ |
9567 | ||
9568 | static int | |
9569 | rs6000_emit_int_cmove (dest, op, true_cond, false_cond) | |
9570 | rtx dest; | |
9571 | rtx op; | |
9572 | rtx true_cond; | |
9573 | rtx false_cond; | |
9574 | { | |
9575 | rtx condition_rtx, cr; | |
9576 | ||
9577 | /* All isel implementations thus far are 32-bits. */ | |
9578 | if (GET_MODE (rs6000_compare_op0) != SImode) | |
9579 | return 0; | |
9580 | ||
9581 | /* We still have to do the compare, because isel doesn't do a | |
9582 | compare, it just looks at the CRx bits set by a previous compare | |
9583 | instruction. */ | |
9584 | condition_rtx = rs6000_generate_compare (GET_CODE (op)); | |
9585 | cr = XEXP (condition_rtx, 0); | |
9586 | ||
9587 | if (GET_MODE (cr) == CCmode) | |
9588 | emit_insn (gen_isel_signed (dest, condition_rtx, | |
9589 | true_cond, false_cond, cr)); | |
9590 | else | |
9591 | emit_insn (gen_isel_unsigned (dest, condition_rtx, | |
9592 | true_cond, false_cond, cr)); | |
9593 | ||
9594 | return 1; | |
9595 | } | |
9596 | ||
9597 | const char * | |
9598 | output_isel (operands) | |
9599 | rtx *operands; | |
9600 | { | |
9601 | enum rtx_code code; | |
9602 | ||
9603 | code = GET_CODE (operands[1]); | |
9604 | if (code == GE || code == GEU || code == LE || code == LEU || code == NE) | |
9605 | { | |
9606 | PUT_CODE (operands[1], reverse_condition (code)); | |
9607 | return "isel %0,%3,%2,%j1"; | |
9608 | } | |
9609 | else | |
9610 | return "isel %0,%2,%3,%j1"; | |
9611 | } | |
9612 | ||
50a0b056 GK |
9613 | void |
9614 | rs6000_emit_minmax (dest, code, op0, op1) | |
9615 | rtx dest; | |
9616 | enum rtx_code code; | |
9617 | rtx op0; | |
9618 | rtx op1; | |
9619 | { | |
9620 | enum machine_mode mode = GET_MODE (op0); | |
5dc8d536 | 9621 | enum rtx_code c; |
50a0b056 | 9622 | rtx target; |
5dc8d536 AH |
9623 | |
9624 | if (code == SMAX || code == SMIN) | |
9625 | c = GE; | |
9626 | else | |
9627 | c = GEU; | |
9628 | ||
50a0b056 | 9629 | if (code == SMAX || code == UMAX) |
5dc8d536 | 9630 | target = emit_conditional_move (dest, c, op0, op1, mode, |
50a0b056 GK |
9631 | op0, op1, mode, 0); |
9632 | else | |
5dc8d536 | 9633 | target = emit_conditional_move (dest, c, op0, op1, mode, |
50a0b056 GK |
9634 | op1, op0, mode, 0); |
9635 | if (target == NULL_RTX) | |
9636 | abort (); | |
9637 | if (target != dest) | |
9638 | emit_move_insn (dest, target); | |
9639 | } | |
12a4e8c5 | 9640 | \f |
a4f6c312 SS |
9641 | /* This page contains routines that are used to determine what the |
9642 | function prologue and epilogue code will do and write them out. */ | |
9878760c | 9643 | |
a4f6c312 SS |
9644 | /* Return the first fixed-point register that is required to be |
9645 | saved. 32 if none. */ | |
9878760c RK |
9646 | |
9647 | int | |
9648 | first_reg_to_save () | |
9649 | { | |
9650 | int first_reg; | |
9651 | ||
9652 | /* Find lowest numbered live register. */ | |
9653 | for (first_reg = 13; first_reg <= 31; first_reg++) | |
a38d360d GK |
9654 | if (regs_ever_live[first_reg] |
9655 | && (! call_used_regs[first_reg] | |
1db02437 | 9656 | || (first_reg == RS6000_PIC_OFFSET_TABLE_REGNUM |
14f00213 | 9657 | && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0) |
f607bc57 | 9658 | || (DEFAULT_ABI == ABI_DARWIN && flag_pic))))) |
9878760c RK |
9659 | break; |
9660 | ||
ee890fe2 | 9661 | #if TARGET_MACHO |
93638d7a AM |
9662 | if (flag_pic |
9663 | && current_function_uses_pic_offset_table | |
9664 | && first_reg > RS6000_PIC_OFFSET_TABLE_REGNUM) | |
1db02437 | 9665 | return RS6000_PIC_OFFSET_TABLE_REGNUM; |
ee890fe2 SS |
9666 | #endif |
9667 | ||
9878760c RK |
9668 | return first_reg; |
9669 | } | |
9670 | ||
9671 | /* Similar, for FP regs. */ | |
9672 | ||
9673 | int | |
9674 | first_fp_reg_to_save () | |
9675 | { | |
9676 | int first_reg; | |
9677 | ||
9678 | /* Find lowest numbered live register. */ | |
9679 | for (first_reg = 14 + 32; first_reg <= 63; first_reg++) | |
9680 | if (regs_ever_live[first_reg]) | |
9681 | break; | |
9682 | ||
9683 | return first_reg; | |
9684 | } | |
00b960c7 AH |
9685 | |
9686 | /* Similar, for AltiVec regs. */ | |
9687 | ||
9688 | static int | |
9689 | first_altivec_reg_to_save () | |
9690 | { | |
9691 | int i; | |
9692 | ||
9693 | /* Stack frame remains as is unless we are in AltiVec ABI. */ | |
9694 | if (! TARGET_ALTIVEC_ABI) | |
9695 | return LAST_ALTIVEC_REGNO + 1; | |
9696 | ||
9697 | /* Find lowest numbered live register. */ | |
9698 | for (i = FIRST_ALTIVEC_REGNO + 20; i <= LAST_ALTIVEC_REGNO; ++i) | |
9699 | if (regs_ever_live[i]) | |
9700 | break; | |
9701 | ||
9702 | return i; | |
9703 | } | |
9704 | ||
9705 | /* Return a 32-bit mask of the AltiVec registers we need to set in | |
9706 | VRSAVE. Bit n of the return value is 1 if Vn is live. The MSB in | |
9707 | the 32-bit word is 0. */ | |
9708 | ||
9709 | static unsigned int | |
9710 | compute_vrsave_mask () | |
9711 | { | |
9712 | unsigned int i, mask = 0; | |
9713 | ||
9714 | /* First, find out if we use _any_ altivec registers. */ | |
9715 | for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i) | |
9716 | if (regs_ever_live[i]) | |
9717 | mask |= ALTIVEC_REG_BIT (i); | |
9718 | ||
9719 | if (mask == 0) | |
9720 | return mask; | |
9721 | ||
00b960c7 AH |
9722 | /* Next, remove the argument registers from the set. These must |
9723 | be in the VRSAVE mask set by the caller, so we don't need to add | |
9724 | them in again. More importantly, the mask we compute here is | |
9725 | used to generate CLOBBERs in the set_vrsave insn, and we do not | |
9726 | wish the argument registers to die. */ | |
9727 | for (i = cfun->args_info.vregno; i >= ALTIVEC_ARG_MIN_REG; --i) | |
9728 | mask &= ~ALTIVEC_REG_BIT (i); | |
9729 | ||
9730 | /* Similarly, remove the return value from the set. */ | |
9731 | { | |
9732 | bool yes = false; | |
9733 | diddle_return_value (is_altivec_return_reg, &yes); | |
9734 | if (yes) | |
9735 | mask &= ~ALTIVEC_REG_BIT (ALTIVEC_ARG_RETURN); | |
9736 | } | |
9737 | ||
9738 | return mask; | |
9739 | } | |
9740 | ||
9741 | static void | |
9742 | is_altivec_return_reg (reg, xyes) | |
9743 | rtx reg; | |
9744 | void *xyes; | |
9745 | { | |
9746 | bool *yes = (bool *) xyes; | |
9747 | if (REGNO (reg) == ALTIVEC_ARG_RETURN) | |
9748 | *yes = true; | |
9749 | } | |
9750 | ||
4697a36c MM |
9751 | \f |
9752 | /* Calculate the stack information for the current function. This is | |
9753 | complicated by having two separate calling sequences, the AIX calling | |
9754 | sequence and the V.4 calling sequence. | |
9755 | ||
592696dd | 9756 | AIX (and Darwin/Mac OS X) stack frames look like: |
a260abc9 | 9757 | 32-bit 64-bit |
4697a36c | 9758 | SP----> +---------------------------------------+ |
a260abc9 | 9759 | | back chain to caller | 0 0 |
4697a36c | 9760 | +---------------------------------------+ |
a260abc9 | 9761 | | saved CR | 4 8 (8-11) |
4697a36c | 9762 | +---------------------------------------+ |
a260abc9 | 9763 | | saved LR | 8 16 |
4697a36c | 9764 | +---------------------------------------+ |
a260abc9 | 9765 | | reserved for compilers | 12 24 |
4697a36c | 9766 | +---------------------------------------+ |
a260abc9 | 9767 | | reserved for binders | 16 32 |
4697a36c | 9768 | +---------------------------------------+ |
a260abc9 | 9769 | | saved TOC pointer | 20 40 |
4697a36c | 9770 | +---------------------------------------+ |
a260abc9 | 9771 | | Parameter save area (P) | 24 48 |
4697a36c | 9772 | +---------------------------------------+ |
a260abc9 | 9773 | | Alloca space (A) | 24+P etc. |
802a0058 | 9774 | +---------------------------------------+ |
a7df97e6 | 9775 | | Local variable space (L) | 24+P+A |
4697a36c | 9776 | +---------------------------------------+ |
a7df97e6 | 9777 | | Float/int conversion temporary (X) | 24+P+A+L |
4697a36c | 9778 | +---------------------------------------+ |
00b960c7 AH |
9779 | | Save area for AltiVec registers (W) | 24+P+A+L+X |
9780 | +---------------------------------------+ | |
9781 | | AltiVec alignment padding (Y) | 24+P+A+L+X+W | |
9782 | +---------------------------------------+ | |
9783 | | Save area for VRSAVE register (Z) | 24+P+A+L+X+W+Y | |
4697a36c | 9784 | +---------------------------------------+ |
00b960c7 AH |
9785 | | Save area for GP registers (G) | 24+P+A+X+L+X+W+Y+Z |
9786 | +---------------------------------------+ | |
9787 | | Save area for FP registers (F) | 24+P+A+X+L+X+W+Y+Z+G | |
4697a36c MM |
9788 | +---------------------------------------+ |
9789 | old SP->| back chain to caller's caller | | |
9790 | +---------------------------------------+ | |
9791 | ||
5376a30c KR |
9792 | The required alignment for AIX configurations is two words (i.e., 8 |
9793 | or 16 bytes). | |
9794 | ||
9795 | ||
4697a36c MM |
9796 | V.4 stack frames look like: |
9797 | ||
9798 | SP----> +---------------------------------------+ | |
9799 | | back chain to caller | 0 | |
9800 | +---------------------------------------+ | |
5eb387b8 | 9801 | | caller's saved LR | 4 |
4697a36c MM |
9802 | +---------------------------------------+ |
9803 | | Parameter save area (P) | 8 | |
9804 | +---------------------------------------+ | |
a7df97e6 MM |
9805 | | Alloca space (A) | 8+P |
9806 | +---------------------------------------+ | |
9807 | | Varargs save area (V) | 8+P+A | |
9808 | +---------------------------------------+ | |
9809 | | Local variable space (L) | 8+P+A+V | |
9810 | +---------------------------------------+ | |
9811 | | Float/int conversion temporary (X) | 8+P+A+V+L | |
4697a36c | 9812 | +---------------------------------------+ |
00b960c7 AH |
9813 | | Save area for AltiVec registers (W) | 8+P+A+V+L+X |
9814 | +---------------------------------------+ | |
9815 | | AltiVec alignment padding (Y) | 8+P+A+V+L+X+W | |
9816 | +---------------------------------------+ | |
9817 | | Save area for VRSAVE register (Z) | 8+P+A+V+L+X+W+Y | |
9818 | +---------------------------------------+ | |
a3170dc6 AH |
9819 | | SPE: area for 64-bit GP registers | |
9820 | +---------------------------------------+ | |
9821 | | SPE alignment padding | | |
9822 | +---------------------------------------+ | |
00b960c7 | 9823 | | saved CR (C) | 8+P+A+V+L+X+W+Y+Z |
a7df97e6 | 9824 | +---------------------------------------+ |
00b960c7 | 9825 | | Save area for GP registers (G) | 8+P+A+V+L+X+W+Y+Z+C |
a7df97e6 | 9826 | +---------------------------------------+ |
00b960c7 | 9827 | | Save area for FP registers (F) | 8+P+A+V+L+X+W+Y+Z+C+G |
4697a36c MM |
9828 | +---------------------------------------+ |
9829 | old SP->| back chain to caller's caller | | |
9830 | +---------------------------------------+ | |
b6c9286a | 9831 | |
5376a30c KR |
9832 | The required alignment for V.4 is 16 bytes, or 8 bytes if -meabi is |
9833 | given. (But note below and in sysv4.h that we require only 8 and | |
9834 | may round up the size of our stack frame anyways. The historical | |
9835 | reason is early versions of powerpc-linux which didn't properly | |
9836 | align the stack at program startup. A happy side-effect is that | |
9837 | -mno-eabi libraries can be used with -meabi programs.) | |
9838 | ||
50d440bc | 9839 | The EABI configuration defaults to the V.4 layout. However, |
5376a30c KR |
9840 | the stack alignment requirements may differ. If -mno-eabi is not |
9841 | given, the required stack alignment is 8 bytes; if -mno-eabi is | |
9842 | given, the required alignment is 16 bytes. (But see V.4 comment | |
9843 | above.) */ | |
4697a36c | 9844 | |
61b2fbe7 MM |
9845 | #ifndef ABI_STACK_BOUNDARY |
9846 | #define ABI_STACK_BOUNDARY STACK_BOUNDARY | |
9847 | #endif | |
9848 | ||
4697a36c MM |
9849 | rs6000_stack_t * |
9850 | rs6000_stack_info () | |
9851 | { | |
9852 | static rs6000_stack_t info, zero_info; | |
9853 | rs6000_stack_t *info_ptr = &info; | |
9ebbca7d | 9854 | int reg_size = TARGET_POWERPC64 ? 8 : 4; |
83720594 | 9855 | int ehrd_size; |
b6c9286a | 9856 | int total_raw_size; |
4697a36c | 9857 | |
a4f6c312 | 9858 | /* Zero all fields portably. */ |
4697a36c MM |
9859 | info = zero_info; |
9860 | ||
c19de7aa AH |
9861 | if (TARGET_SPE) |
9862 | { | |
9863 | /* Cache value so we don't rescan instruction chain over and over. */ | |
9b7b447f AH |
9864 | if (cfun->machine->insn_chain_scanned_p == 0) |
9865 | { | |
9866 | cfun->machine->insn_chain_scanned_p = 1; | |
9867 | info_ptr->spe_64bit_regs_used = (int) spe_func_has_64bit_regs_p (); | |
9868 | } | |
c19de7aa AH |
9869 | } |
9870 | ||
a4f6c312 | 9871 | /* Select which calling sequence. */ |
178274da | 9872 | info_ptr->abi = DEFAULT_ABI; |
9878760c | 9873 | |
a4f6c312 | 9874 | /* Calculate which registers need to be saved & save area size. */ |
4697a36c | 9875 | info_ptr->first_gp_reg_save = first_reg_to_save (); |
1db02437 | 9876 | /* Assume that we will have to save RS6000_PIC_OFFSET_TABLE_REGNUM, |
906fb125 | 9877 | even if it currently looks like we won't. */ |
2bfcf297 | 9878 | if (((TARGET_TOC && TARGET_MINIMAL_TOC) |
178274da AM |
9879 | || (flag_pic == 1 && DEFAULT_ABI == ABI_V4) |
9880 | || (flag_pic && DEFAULT_ABI == ABI_DARWIN)) | |
1db02437 FS |
9881 | && info_ptr->first_gp_reg_save > RS6000_PIC_OFFSET_TABLE_REGNUM) |
9882 | info_ptr->gp_size = reg_size * (32 - RS6000_PIC_OFFSET_TABLE_REGNUM); | |
906fb125 GK |
9883 | else |
9884 | info_ptr->gp_size = reg_size * (32 - info_ptr->first_gp_reg_save); | |
4697a36c | 9885 | |
a3170dc6 AH |
9886 | /* For the SPE, we have an additional upper 32-bits on each GPR. |
9887 | Ideally we should save the entire 64-bits only when the upper | |
9888 | half is used in SIMD instructions. Since we only record | |
9889 | registers live (not the size they are used in), this proves | |
9890 | difficult because we'd have to traverse the instruction chain at | |
9891 | the right time, taking reload into account. This is a real pain, | |
c19de7aa AH |
9892 | so we opt to save the GPRs in 64-bits always if but one register |
9893 | gets used in 64-bits. Otherwise, all the registers in the frame | |
9894 | get saved in 32-bits. | |
a3170dc6 | 9895 | |
c19de7aa | 9896 | So... since when we save all GPRs (except the SP) in 64-bits, the |
a3170dc6 | 9897 | traditional GP save area will be empty. */ |
c19de7aa | 9898 | if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0) |
a3170dc6 AH |
9899 | info_ptr->gp_size = 0; |
9900 | ||
4697a36c MM |
9901 | info_ptr->first_fp_reg_save = first_fp_reg_to_save (); |
9902 | info_ptr->fp_size = 8 * (64 - info_ptr->first_fp_reg_save); | |
9903 | ||
00b960c7 AH |
9904 | info_ptr->first_altivec_reg_save = first_altivec_reg_to_save (); |
9905 | info_ptr->altivec_size = 16 * (LAST_ALTIVEC_REGNO + 1 | |
9906 | - info_ptr->first_altivec_reg_save); | |
9907 | ||
592696dd | 9908 | /* Does this function call anything? */ |
71f123ca FS |
9909 | info_ptr->calls_p = (! current_function_is_leaf |
9910 | || cfun->machine->ra_needs_full_frame); | |
b6c9286a | 9911 | |
a4f6c312 | 9912 | /* Determine if we need to save the link register. */ |
71f123ca | 9913 | if (rs6000_ra_ever_killed () |
ffcfcb5f AM |
9914 | || (DEFAULT_ABI == ABI_AIX |
9915 | && current_function_profile | |
9916 | && !TARGET_PROFILE_KERNEL) | |
4697a36c MM |
9917 | #ifdef TARGET_RELOCATABLE |
9918 | || (TARGET_RELOCATABLE && (get_pool_size () != 0)) | |
9919 | #endif | |
9920 | || (info_ptr->first_fp_reg_save != 64 | |
9921 | && !FP_SAVE_INLINE (info_ptr->first_fp_reg_save)) | |
00b960c7 | 9922 | || info_ptr->first_altivec_reg_save <= LAST_ALTIVEC_REGNO |
178274da | 9923 | || (DEFAULT_ABI == ABI_V4 && current_function_calls_alloca) |
a4f6c312 SS |
9924 | || (DEFAULT_ABI == ABI_DARWIN |
9925 | && flag_pic | |
9926 | && current_function_uses_pic_offset_table) | |
4697a36c MM |
9927 | || info_ptr->calls_p) |
9928 | { | |
9929 | info_ptr->lr_save_p = 1; | |
9ebbca7d | 9930 | regs_ever_live[LINK_REGISTER_REGNUM] = 1; |
4697a36c MM |
9931 | } |
9932 | ||
9ebbca7d GK |
9933 | /* Determine if we need to save the condition code registers. */ |
9934 | if (regs_ever_live[CR2_REGNO] | |
9935 | || regs_ever_live[CR3_REGNO] | |
9936 | || regs_ever_live[CR4_REGNO]) | |
4697a36c MM |
9937 | { |
9938 | info_ptr->cr_save_p = 1; | |
178274da | 9939 | if (DEFAULT_ABI == ABI_V4) |
4697a36c MM |
9940 | info_ptr->cr_size = reg_size; |
9941 | } | |
9942 | ||
83720594 RH |
9943 | /* If the current function calls __builtin_eh_return, then we need |
9944 | to allocate stack space for registers that will hold data for | |
9945 | the exception handler. */ | |
9946 | if (current_function_calls_eh_return) | |
9947 | { | |
9948 | unsigned int i; | |
9949 | for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; ++i) | |
9950 | continue; | |
a3170dc6 AH |
9951 | |
9952 | /* SPE saves EH registers in 64-bits. */ | |
c19de7aa AH |
9953 | ehrd_size = i * (TARGET_SPE_ABI |
9954 | && info_ptr->spe_64bit_regs_used != 0 | |
9955 | ? UNITS_PER_SPE_WORD : UNITS_PER_WORD); | |
83720594 RH |
9956 | } |
9957 | else | |
9958 | ehrd_size = 0; | |
9959 | ||
592696dd | 9960 | /* Determine various sizes. */ |
4697a36c MM |
9961 | info_ptr->reg_size = reg_size; |
9962 | info_ptr->fixed_size = RS6000_SAVE_AREA; | |
9963 | info_ptr->varargs_size = RS6000_VARARGS_AREA; | |
189e03e3 | 9964 | info_ptr->vars_size = RS6000_ALIGN (get_frame_size (), 8); |
a4f6c312 SS |
9965 | info_ptr->parm_size = RS6000_ALIGN (current_function_outgoing_args_size, |
9966 | 8); | |
00b960c7 | 9967 | |
c19de7aa | 9968 | if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0) |
a3170dc6 AH |
9969 | info_ptr->spe_gp_size = 8 * (32 - info_ptr->first_gp_reg_save); |
9970 | else | |
9971 | info_ptr->spe_gp_size = 0; | |
9972 | ||
08b57fb3 | 9973 | if (TARGET_ALTIVEC_ABI && TARGET_ALTIVEC_VRSAVE) |
00b960c7 AH |
9974 | { |
9975 | info_ptr->vrsave_mask = compute_vrsave_mask (); | |
9976 | info_ptr->vrsave_size = info_ptr->vrsave_mask ? 4 : 0; | |
9977 | } | |
9978 | else | |
9979 | { | |
9980 | info_ptr->vrsave_mask = 0; | |
9981 | info_ptr->vrsave_size = 0; | |
9982 | } | |
b6c9286a | 9983 | |
592696dd | 9984 | /* Calculate the offsets. */ |
178274da | 9985 | switch (DEFAULT_ABI) |
4697a36c | 9986 | { |
b6c9286a | 9987 | case ABI_NONE: |
24d304eb | 9988 | default: |
b6c9286a MM |
9989 | abort (); |
9990 | ||
9991 | case ABI_AIX: | |
ee890fe2 | 9992 | case ABI_DARWIN: |
b6c9286a MM |
9993 | info_ptr->fp_save_offset = - info_ptr->fp_size; |
9994 | info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size; | |
00b960c7 AH |
9995 | |
9996 | if (TARGET_ALTIVEC_ABI) | |
9997 | { | |
9998 | info_ptr->vrsave_save_offset | |
9999 | = info_ptr->gp_save_offset - info_ptr->vrsave_size; | |
10000 | ||
10001 | /* Align stack so vector save area is on a quadword boundary. */ | |
10002 | if (info_ptr->altivec_size != 0) | |
10003 | info_ptr->altivec_padding_size | |
10004 | = 16 - (-info_ptr->vrsave_save_offset % 16); | |
10005 | else | |
10006 | info_ptr->altivec_padding_size = 0; | |
10007 | ||
10008 | info_ptr->altivec_save_offset | |
10009 | = info_ptr->vrsave_save_offset | |
10010 | - info_ptr->altivec_padding_size | |
10011 | - info_ptr->altivec_size; | |
10012 | ||
10013 | /* Adjust for AltiVec case. */ | |
10014 | info_ptr->ehrd_offset = info_ptr->altivec_save_offset - ehrd_size; | |
10015 | } | |
10016 | else | |
10017 | info_ptr->ehrd_offset = info_ptr->gp_save_offset - ehrd_size; | |
a260abc9 DE |
10018 | info_ptr->cr_save_offset = reg_size; /* first word when 64-bit. */ |
10019 | info_ptr->lr_save_offset = 2*reg_size; | |
24d304eb RK |
10020 | break; |
10021 | ||
10022 | case ABI_V4: | |
b6c9286a MM |
10023 | info_ptr->fp_save_offset = - info_ptr->fp_size; |
10024 | info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size; | |
a7df97e6 | 10025 | info_ptr->cr_save_offset = info_ptr->gp_save_offset - info_ptr->cr_size; |
00b960c7 | 10026 | |
c19de7aa | 10027 | if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0) |
a3170dc6 AH |
10028 | { |
10029 | /* Align stack so SPE GPR save area is aligned on a | |
10030 | double-word boundary. */ | |
10031 | if (info_ptr->spe_gp_size != 0) | |
10032 | info_ptr->spe_padding_size | |
10033 | = 8 - (-info_ptr->cr_save_offset % 8); | |
10034 | else | |
10035 | info_ptr->spe_padding_size = 0; | |
10036 | ||
10037 | info_ptr->spe_gp_save_offset | |
10038 | = info_ptr->cr_save_offset | |
10039 | - info_ptr->spe_padding_size | |
10040 | - info_ptr->spe_gp_size; | |
10041 | ||
10042 | /* Adjust for SPE case. */ | |
10043 | info_ptr->toc_save_offset | |
10044 | = info_ptr->spe_gp_save_offset - info_ptr->toc_size; | |
10045 | } | |
10046 | else if (TARGET_ALTIVEC_ABI) | |
00b960c7 AH |
10047 | { |
10048 | info_ptr->vrsave_save_offset | |
10049 | = info_ptr->cr_save_offset - info_ptr->vrsave_size; | |
10050 | ||
10051 | /* Align stack so vector save area is on a quadword boundary. */ | |
10052 | if (info_ptr->altivec_size != 0) | |
10053 | info_ptr->altivec_padding_size | |
10054 | = 16 - (-info_ptr->vrsave_save_offset % 16); | |
10055 | else | |
10056 | info_ptr->altivec_padding_size = 0; | |
10057 | ||
10058 | info_ptr->altivec_save_offset | |
10059 | = info_ptr->vrsave_save_offset | |
10060 | - info_ptr->altivec_padding_size | |
10061 | - info_ptr->altivec_size; | |
10062 | ||
10063 | /* Adjust for AltiVec case. */ | |
10064 | info_ptr->toc_save_offset | |
10065 | = info_ptr->altivec_save_offset - info_ptr->toc_size; | |
10066 | } | |
10067 | else | |
10068 | info_ptr->toc_save_offset = info_ptr->cr_save_offset - info_ptr->toc_size; | |
83720594 | 10069 | info_ptr->ehrd_offset = info_ptr->toc_save_offset - ehrd_size; |
b6c9286a MM |
10070 | info_ptr->lr_save_offset = reg_size; |
10071 | break; | |
4697a36c MM |
10072 | } |
10073 | ||
00b960c7 AH |
10074 | info_ptr->save_size = RS6000_ALIGN (info_ptr->fp_size |
10075 | + info_ptr->gp_size | |
10076 | + info_ptr->altivec_size | |
10077 | + info_ptr->altivec_padding_size | |
a3170dc6 AH |
10078 | + info_ptr->spe_gp_size |
10079 | + info_ptr->spe_padding_size | |
00b960c7 AH |
10080 | + ehrd_size |
10081 | + info_ptr->cr_size | |
10082 | + info_ptr->lr_size | |
10083 | + info_ptr->vrsave_size | |
10084 | + info_ptr->toc_size, | |
10085 | (TARGET_ALTIVEC_ABI || ABI_DARWIN) | |
10086 | ? 16 : 8); | |
10087 | ||
ff381587 MM |
10088 | total_raw_size = (info_ptr->vars_size |
10089 | + info_ptr->parm_size | |
ff381587 MM |
10090 | + info_ptr->save_size |
10091 | + info_ptr->varargs_size | |
10092 | + info_ptr->fixed_size); | |
10093 | ||
a4f6c312 SS |
10094 | info_ptr->total_size = |
10095 | RS6000_ALIGN (total_raw_size, ABI_STACK_BOUNDARY / BITS_PER_UNIT); | |
ff381587 MM |
10096 | |
10097 | /* Determine if we need to allocate any stack frame: | |
10098 | ||
a4f6c312 SS |
10099 | For AIX we need to push the stack if a frame pointer is needed |
10100 | (because the stack might be dynamically adjusted), if we are | |
10101 | debugging, if we make calls, or if the sum of fp_save, gp_save, | |
10102 | and local variables are more than the space needed to save all | |
10103 | non-volatile registers: 32-bit: 18*8 + 19*4 = 220 or 64-bit: 18*8 | |
10104 | + 18*8 = 288 (GPR13 reserved). | |
ff381587 | 10105 | |
a4f6c312 SS |
10106 | For V.4 we don't have the stack cushion that AIX uses, but assume |
10107 | that the debugger can handle stackless frames. */ | |
ff381587 MM |
10108 | |
10109 | if (info_ptr->calls_p) | |
10110 | info_ptr->push_p = 1; | |
10111 | ||
178274da | 10112 | else if (DEFAULT_ABI == ABI_V4) |
e72247f4 | 10113 | info_ptr->push_p = total_raw_size > info_ptr->fixed_size; |
ff381587 | 10114 | |
178274da AM |
10115 | else if (frame_pointer_needed) |
10116 | info_ptr->push_p = 1; | |
10117 | ||
10118 | else if (TARGET_XCOFF && write_symbols != NO_DEBUG) | |
10119 | info_ptr->push_p = 1; | |
10120 | ||
ff381587 | 10121 | else |
178274da AM |
10122 | info_ptr->push_p |
10123 | = total_raw_size - info_ptr->fixed_size > (TARGET_32BIT ? 220 : 288); | |
ff381587 | 10124 | |
a4f6c312 | 10125 | /* Zero offsets if we're not saving those registers. */ |
8dda1a21 | 10126 | if (info_ptr->fp_size == 0) |
4697a36c MM |
10127 | info_ptr->fp_save_offset = 0; |
10128 | ||
8dda1a21 | 10129 | if (info_ptr->gp_size == 0) |
4697a36c MM |
10130 | info_ptr->gp_save_offset = 0; |
10131 | ||
00b960c7 AH |
10132 | if (! TARGET_ALTIVEC_ABI || info_ptr->altivec_size == 0) |
10133 | info_ptr->altivec_save_offset = 0; | |
10134 | ||
10135 | if (! TARGET_ALTIVEC_ABI || info_ptr->vrsave_mask == 0) | |
10136 | info_ptr->vrsave_save_offset = 0; | |
10137 | ||
c19de7aa AH |
10138 | if (! TARGET_SPE_ABI |
10139 | || info_ptr->spe_64bit_regs_used == 0 | |
10140 | || info_ptr->spe_gp_size == 0) | |
a3170dc6 AH |
10141 | info_ptr->spe_gp_save_offset = 0; |
10142 | ||
c81fc13e | 10143 | if (! info_ptr->lr_save_p) |
4697a36c MM |
10144 | info_ptr->lr_save_offset = 0; |
10145 | ||
c81fc13e | 10146 | if (! info_ptr->cr_save_p) |
4697a36c MM |
10147 | info_ptr->cr_save_offset = 0; |
10148 | ||
c81fc13e | 10149 | if (! info_ptr->toc_save_p) |
b6c9286a MM |
10150 | info_ptr->toc_save_offset = 0; |
10151 | ||
4697a36c MM |
10152 | return info_ptr; |
10153 | } | |
10154 | ||
c19de7aa AH |
10155 | /* Return true if the current function uses any GPRs in 64-bit SIMD |
10156 | mode. */ | |
10157 | ||
10158 | static bool | |
10159 | spe_func_has_64bit_regs_p () | |
10160 | { | |
10161 | rtx insns, insn; | |
10162 | ||
10163 | /* Functions that save and restore all the call-saved registers will | |
10164 | need to save/restore the registers in 64-bits. */ | |
10165 | if (current_function_calls_eh_return | |
10166 | || current_function_calls_setjmp | |
10167 | || current_function_has_nonlocal_goto) | |
10168 | return true; | |
10169 | ||
10170 | insns = get_insns (); | |
10171 | ||
10172 | for (insn = NEXT_INSN (insns); insn != NULL_RTX; insn = NEXT_INSN (insn)) | |
10173 | { | |
10174 | if (INSN_P (insn)) | |
10175 | { | |
10176 | rtx i; | |
10177 | ||
10178 | i = PATTERN (insn); | |
10179 | if (GET_CODE (i) == SET | |
10180 | && SPE_VECTOR_MODE (GET_MODE (SET_SRC (i)))) | |
10181 | return true; | |
10182 | } | |
10183 | } | |
10184 | ||
10185 | return false; | |
10186 | } | |
10187 | ||
4697a36c MM |
10188 | void |
10189 | debug_stack_info (info) | |
10190 | rs6000_stack_t *info; | |
9878760c | 10191 | { |
d330fd93 | 10192 | const char *abi_string; |
24d304eb | 10193 | |
c81fc13e | 10194 | if (! info) |
4697a36c MM |
10195 | info = rs6000_stack_info (); |
10196 | ||
10197 | fprintf (stderr, "\nStack information for function %s:\n", | |
10198 | ((current_function_decl && DECL_NAME (current_function_decl)) | |
10199 | ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl)) | |
10200 | : "<unknown>")); | |
10201 | ||
24d304eb RK |
10202 | switch (info->abi) |
10203 | { | |
b6c9286a MM |
10204 | default: abi_string = "Unknown"; break; |
10205 | case ABI_NONE: abi_string = "NONE"; break; | |
50d440bc | 10206 | case ABI_AIX: abi_string = "AIX"; break; |
ee890fe2 | 10207 | case ABI_DARWIN: abi_string = "Darwin"; break; |
b6c9286a | 10208 | case ABI_V4: abi_string = "V.4"; break; |
24d304eb RK |
10209 | } |
10210 | ||
10211 | fprintf (stderr, "\tABI = %5s\n", abi_string); | |
10212 | ||
00b960c7 AH |
10213 | if (TARGET_ALTIVEC_ABI) |
10214 | fprintf (stderr, "\tALTIVEC ABI extensions enabled.\n"); | |
10215 | ||
a3170dc6 AH |
10216 | if (TARGET_SPE_ABI) |
10217 | fprintf (stderr, "\tSPE ABI extensions enabled.\n"); | |
10218 | ||
4697a36c MM |
10219 | if (info->first_gp_reg_save != 32) |
10220 | fprintf (stderr, "\tfirst_gp_reg_save = %5d\n", info->first_gp_reg_save); | |
10221 | ||
10222 | if (info->first_fp_reg_save != 64) | |
10223 | fprintf (stderr, "\tfirst_fp_reg_save = %5d\n", info->first_fp_reg_save); | |
9878760c | 10224 | |
00b960c7 AH |
10225 | if (info->first_altivec_reg_save <= LAST_ALTIVEC_REGNO) |
10226 | fprintf (stderr, "\tfirst_altivec_reg_save = %5d\n", | |
10227 | info->first_altivec_reg_save); | |
10228 | ||
4697a36c MM |
10229 | if (info->lr_save_p) |
10230 | fprintf (stderr, "\tlr_save_p = %5d\n", info->lr_save_p); | |
9878760c | 10231 | |
4697a36c MM |
10232 | if (info->cr_save_p) |
10233 | fprintf (stderr, "\tcr_save_p = %5d\n", info->cr_save_p); | |
10234 | ||
b6c9286a MM |
10235 | if (info->toc_save_p) |
10236 | fprintf (stderr, "\ttoc_save_p = %5d\n", info->toc_save_p); | |
10237 | ||
00b960c7 AH |
10238 | if (info->vrsave_mask) |
10239 | fprintf (stderr, "\tvrsave_mask = 0x%x\n", info->vrsave_mask); | |
10240 | ||
4697a36c MM |
10241 | if (info->push_p) |
10242 | fprintf (stderr, "\tpush_p = %5d\n", info->push_p); | |
10243 | ||
10244 | if (info->calls_p) | |
10245 | fprintf (stderr, "\tcalls_p = %5d\n", info->calls_p); | |
10246 | ||
4697a36c MM |
10247 | if (info->gp_save_offset) |
10248 | fprintf (stderr, "\tgp_save_offset = %5d\n", info->gp_save_offset); | |
10249 | ||
10250 | if (info->fp_save_offset) | |
10251 | fprintf (stderr, "\tfp_save_offset = %5d\n", info->fp_save_offset); | |
10252 | ||
00b960c7 AH |
10253 | if (info->altivec_save_offset) |
10254 | fprintf (stderr, "\taltivec_save_offset = %5d\n", | |
10255 | info->altivec_save_offset); | |
10256 | ||
a3170dc6 AH |
10257 | if (info->spe_gp_save_offset) |
10258 | fprintf (stderr, "\tspe_gp_save_offset = %5d\n", | |
10259 | info->spe_gp_save_offset); | |
10260 | ||
00b960c7 AH |
10261 | if (info->vrsave_save_offset) |
10262 | fprintf (stderr, "\tvrsave_save_offset = %5d\n", | |
10263 | info->vrsave_save_offset); | |
10264 | ||
4697a36c MM |
10265 | if (info->lr_save_offset) |
10266 | fprintf (stderr, "\tlr_save_offset = %5d\n", info->lr_save_offset); | |
10267 | ||
10268 | if (info->cr_save_offset) | |
10269 | fprintf (stderr, "\tcr_save_offset = %5d\n", info->cr_save_offset); | |
10270 | ||
b6c9286a MM |
10271 | if (info->toc_save_offset) |
10272 | fprintf (stderr, "\ttoc_save_offset = %5d\n", info->toc_save_offset); | |
10273 | ||
4697a36c MM |
10274 | if (info->varargs_save_offset) |
10275 | fprintf (stderr, "\tvarargs_save_offset = %5d\n", info->varargs_save_offset); | |
10276 | ||
10277 | if (info->total_size) | |
10278 | fprintf (stderr, "\ttotal_size = %5d\n", info->total_size); | |
10279 | ||
10280 | if (info->varargs_size) | |
10281 | fprintf (stderr, "\tvarargs_size = %5d\n", info->varargs_size); | |
10282 | ||
10283 | if (info->vars_size) | |
10284 | fprintf (stderr, "\tvars_size = %5d\n", info->vars_size); | |
10285 | ||
10286 | if (info->parm_size) | |
10287 | fprintf (stderr, "\tparm_size = %5d\n", info->parm_size); | |
10288 | ||
10289 | if (info->fixed_size) | |
10290 | fprintf (stderr, "\tfixed_size = %5d\n", info->fixed_size); | |
10291 | ||
10292 | if (info->gp_size) | |
10293 | fprintf (stderr, "\tgp_size = %5d\n", info->gp_size); | |
10294 | ||
a3170dc6 AH |
10295 | if (info->spe_gp_size) |
10296 | fprintf (stderr, "\tspe_gp_size = %5d\n", info->spe_gp_size); | |
10297 | ||
4697a36c MM |
10298 | if (info->fp_size) |
10299 | fprintf (stderr, "\tfp_size = %5d\n", info->fp_size); | |
10300 | ||
00b960c7 AH |
10301 | if (info->altivec_size) |
10302 | fprintf (stderr, "\taltivec_size = %5d\n", info->altivec_size); | |
10303 | ||
10304 | if (info->vrsave_size) | |
10305 | fprintf (stderr, "\tvrsave_size = %5d\n", info->vrsave_size); | |
10306 | ||
10307 | if (info->altivec_padding_size) | |
10308 | fprintf (stderr, "\taltivec_padding_size= %5d\n", | |
10309 | info->altivec_padding_size); | |
10310 | ||
a3170dc6 AH |
10311 | if (info->spe_padding_size) |
10312 | fprintf (stderr, "\tspe_padding_size = %5d\n", | |
10313 | info->spe_padding_size); | |
10314 | ||
a4f6c312 | 10315 | if (info->lr_size) |
ed947a96 | 10316 | fprintf (stderr, "\tlr_size = %5d\n", info->lr_size); |
b6c9286a | 10317 | |
4697a36c MM |
10318 | if (info->cr_size) |
10319 | fprintf (stderr, "\tcr_size = %5d\n", info->cr_size); | |
10320 | ||
a4f6c312 | 10321 | if (info->toc_size) |
b6c9286a MM |
10322 | fprintf (stderr, "\ttoc_size = %5d\n", info->toc_size); |
10323 | ||
4697a36c MM |
10324 | if (info->save_size) |
10325 | fprintf (stderr, "\tsave_size = %5d\n", info->save_size); | |
10326 | ||
10327 | if (info->reg_size != 4) | |
10328 | fprintf (stderr, "\treg_size = %5d\n", info->reg_size); | |
10329 | ||
10330 | fprintf (stderr, "\n"); | |
9878760c | 10331 | } |
71f123ca FS |
10332 | |
10333 | rtx | |
10334 | rs6000_return_addr (count, frame) | |
10335 | int count; | |
10336 | rtx frame; | |
10337 | { | |
a4f6c312 SS |
10338 | /* Currently we don't optimize very well between prolog and body |
10339 | code and for PIC code the code can be actually quite bad, so | |
10340 | don't try to be too clever here. */ | |
f1384257 | 10341 | if (count != 0 || (DEFAULT_ABI != ABI_AIX && flag_pic)) |
71f123ca FS |
10342 | { |
10343 | cfun->machine->ra_needs_full_frame = 1; | |
8ac61af7 RK |
10344 | |
10345 | return | |
10346 | gen_rtx_MEM | |
10347 | (Pmode, | |
10348 | memory_address | |
10349 | (Pmode, | |
10350 | plus_constant (copy_to_reg | |
10351 | (gen_rtx_MEM (Pmode, | |
10352 | memory_address (Pmode, frame))), | |
10353 | RETURN_ADDRESS_OFFSET))); | |
71f123ca FS |
10354 | } |
10355 | ||
9e2f7ec7 | 10356 | return get_hard_reg_initial_val (Pmode, LINK_REGISTER_REGNUM); |
71f123ca FS |
10357 | } |
10358 | ||
5e1bf043 DJ |
10359 | /* Say whether a function is a candidate for sibcall handling or not. |
10360 | We do not allow indirect calls to be optimized into sibling calls. | |
10361 | Also, we can't do it if there are any vector parameters; there's | |
10362 | nowhere to put the VRsave code so it works; note that functions with | |
10363 | vector parameters are required to have a prototype, so the argument | |
10364 | type info must be available here. (The tail recursion case can work | |
10365 | with vector parameters, but there's no way to distinguish here.) */ | |
4977bab6 ZW |
10366 | static bool |
10367 | rs6000_function_ok_for_sibcall (decl, exp) | |
10368 | tree decl; | |
10369 | tree exp ATTRIBUTE_UNUSED; | |
5e1bf043 DJ |
10370 | { |
10371 | tree type; | |
4977bab6 | 10372 | if (decl) |
5e1bf043 DJ |
10373 | { |
10374 | if (TARGET_ALTIVEC_VRSAVE) | |
10375 | { | |
4977bab6 | 10376 | for (type = TYPE_ARG_TYPES (TREE_TYPE (decl)); |
5e1bf043 DJ |
10377 | type; type = TREE_CHAIN (type)) |
10378 | { | |
c15b529f | 10379 | if (TREE_CODE (TREE_VALUE (type)) == VECTOR_TYPE) |
4977bab6 | 10380 | return false; |
5e1bf043 DJ |
10381 | } |
10382 | } | |
10383 | if (DEFAULT_ABI == ABI_DARWIN | |
4977bab6 | 10384 | || (*targetm.binds_local_p) (decl)) |
2bcc50d0 | 10385 | { |
4977bab6 | 10386 | tree attr_list = TYPE_ATTRIBUTES (TREE_TYPE (decl)); |
2bcc50d0 AM |
10387 | |
10388 | if (!lookup_attribute ("longcall", attr_list) | |
10389 | || lookup_attribute ("shortcall", attr_list)) | |
4977bab6 | 10390 | return true; |
2bcc50d0 | 10391 | } |
5e1bf043 | 10392 | } |
4977bab6 | 10393 | return false; |
5e1bf043 DJ |
10394 | } |
10395 | ||
71f123ca FS |
10396 | static int |
10397 | rs6000_ra_ever_killed () | |
10398 | { | |
10399 | rtx top; | |
5e1bf043 DJ |
10400 | rtx reg; |
10401 | rtx insn; | |
71f123ca | 10402 | |
3961e8fe RH |
10403 | /* Irritatingly, there are two kinds of thunks -- those created with |
10404 | TARGET_ASM_OUTPUT_MI_THUNK and those with DECL_THUNK_P that go | |
10405 | through the regular part of the compiler. This is a very hacky | |
10406 | way to tell them apart. */ | |
10407 | if (current_function_is_thunk && !no_new_pseudos) | |
71f123ca | 10408 | return 0; |
eb0424da | 10409 | |
36f7e964 AH |
10410 | /* regs_ever_live has LR marked as used if any sibcalls are present, |
10411 | but this should not force saving and restoring in the | |
10412 | pro/epilogue. Likewise, reg_set_between_p thinks a sibcall | |
10413 | clobbers LR, so that is inappropriate. */ | |
10414 | ||
5e1bf043 DJ |
10415 | /* Also, the prologue can generate a store into LR that |
10416 | doesn't really count, like this: | |
36f7e964 | 10417 | |
5e1bf043 DJ |
10418 | move LR->R0 |
10419 | bcl to set PIC register | |
10420 | move LR->R31 | |
10421 | move R0->LR | |
36f7e964 AH |
10422 | |
10423 | When we're called from the epilogue, we need to avoid counting | |
10424 | this as a store. */ | |
5e1bf043 | 10425 | |
71f123ca FS |
10426 | push_topmost_sequence (); |
10427 | top = get_insns (); | |
10428 | pop_topmost_sequence (); | |
5e1bf043 | 10429 | reg = gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM); |
71f123ca | 10430 | |
5e1bf043 DJ |
10431 | for (insn = NEXT_INSN (top); insn != NULL_RTX; insn = NEXT_INSN (insn)) |
10432 | { | |
10433 | if (INSN_P (insn)) | |
10434 | { | |
10435 | if (FIND_REG_INC_NOTE (insn, reg)) | |
10436 | return 1; | |
10437 | else if (GET_CODE (insn) == CALL_INSN | |
c15b529f | 10438 | && !SIBLING_CALL_P (insn)) |
5e1bf043 | 10439 | return 1; |
36f7e964 AH |
10440 | else if (set_of (reg, insn) != NULL_RTX |
10441 | && !prologue_epilogue_contains (insn)) | |
5e1bf043 DJ |
10442 | return 1; |
10443 | } | |
10444 | } | |
10445 | return 0; | |
71f123ca | 10446 | } |
4697a36c | 10447 | \f |
8cd8f856 GK |
10448 | /* Add a REG_MAYBE_DEAD note to the insn. */ |
10449 | static void | |
10450 | rs6000_maybe_dead (insn) | |
10451 | rtx insn; | |
10452 | { | |
10453 | REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD, | |
10454 | const0_rtx, | |
10455 | REG_NOTES (insn)); | |
10456 | } | |
10457 | ||
9ebbca7d | 10458 | /* Emit instructions needed to load the TOC register. |
c7ca610e | 10459 | This is only needed when TARGET_TOC, TARGET_MINIMAL_TOC, and there is |
9ebbca7d | 10460 | a constant pool; or for SVR4 -fpic. */ |
c7ca610e RK |
10461 | |
10462 | void | |
9ebbca7d GK |
10463 | rs6000_emit_load_toc_table (fromprolog) |
10464 | int fromprolog; | |
c7ca610e | 10465 | { |
027fbf43 | 10466 | rtx dest, insn; |
1db02437 | 10467 | dest = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM); |
c7ca610e | 10468 | |
20b71b17 AM |
10469 | if (TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 1) |
10470 | { | |
10471 | rtx temp = (fromprolog | |
10472 | ? gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM) | |
10473 | : gen_reg_rtx (Pmode)); | |
027fbf43 JJ |
10474 | insn = emit_insn (gen_load_toc_v4_pic_si (temp)); |
10475 | if (fromprolog) | |
10476 | rs6000_maybe_dead (insn); | |
10477 | insn = emit_move_insn (dest, temp); | |
10478 | if (fromprolog) | |
10479 | rs6000_maybe_dead (insn); | |
20b71b17 AM |
10480 | } |
10481 | else if (TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2) | |
10482 | { | |
10483 | char buf[30]; | |
10484 | rtx tempLR = (fromprolog | |
10485 | ? gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM) | |
10486 | : gen_reg_rtx (Pmode)); | |
10487 | rtx temp0 = (fromprolog | |
10488 | ? gen_rtx_REG (Pmode, 0) | |
10489 | : gen_reg_rtx (Pmode)); | |
10490 | rtx symF; | |
10491 | ||
10492 | /* possibly create the toc section */ | |
10493 | if (! toc_initialized) | |
38c1f2d7 | 10494 | { |
20b71b17 AM |
10495 | toc_section (); |
10496 | function_section (current_function_decl); | |
38c1f2d7 | 10497 | } |
9ebbca7d | 10498 | |
20b71b17 AM |
10499 | if (fromprolog) |
10500 | { | |
10501 | rtx symL; | |
38c1f2d7 | 10502 | |
20b71b17 AM |
10503 | ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno); |
10504 | symF = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); | |
9ebbca7d | 10505 | |
20b71b17 AM |
10506 | ASM_GENERATE_INTERNAL_LABEL (buf, "LCL", rs6000_pic_labelno); |
10507 | symL = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); | |
10508 | ||
10509 | rs6000_maybe_dead (emit_insn (gen_load_toc_v4_PIC_1 (tempLR, | |
10510 | symF))); | |
10511 | rs6000_maybe_dead (emit_move_insn (dest, tempLR)); | |
10512 | rs6000_maybe_dead (emit_insn (gen_load_toc_v4_PIC_2 (temp0, dest, | |
10513 | symL, | |
10514 | symF))); | |
9ebbca7d GK |
10515 | } |
10516 | else | |
20b71b17 AM |
10517 | { |
10518 | rtx tocsym; | |
10519 | static int reload_toc_labelno = 0; | |
10520 | ||
10521 | tocsym = gen_rtx_SYMBOL_REF (Pmode, toc_label_name); | |
10522 | ||
10523 | ASM_GENERATE_INTERNAL_LABEL (buf, "LCG", reload_toc_labelno++); | |
10524 | symF = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); | |
10525 | ||
027fbf43 JJ |
10526 | emit_insn (gen_load_toc_v4_PIC_1b (tempLR, symF, tocsym)); |
10527 | emit_move_insn (dest, tempLR); | |
10528 | emit_move_insn (temp0, gen_rtx_MEM (Pmode, dest)); | |
20b71b17 | 10529 | } |
027fbf43 JJ |
10530 | insn = emit_insn (gen_addsi3 (dest, temp0, dest)); |
10531 | if (fromprolog) | |
10532 | rs6000_maybe_dead (insn); | |
9ebbca7d | 10533 | } |
20b71b17 AM |
10534 | else if (TARGET_ELF && !TARGET_AIX && flag_pic == 0 && TARGET_MINIMAL_TOC) |
10535 | { | |
10536 | /* This is for AIX code running in non-PIC ELF32. */ | |
10537 | char buf[30]; | |
10538 | rtx realsym; | |
10539 | ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1); | |
10540 | realsym = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); | |
10541 | ||
027fbf43 JJ |
10542 | insn = emit_insn (gen_elf_high (dest, realsym)); |
10543 | if (fromprolog) | |
10544 | rs6000_maybe_dead (insn); | |
10545 | insn = emit_insn (gen_elf_low (dest, dest, realsym)); | |
10546 | if (fromprolog) | |
10547 | rs6000_maybe_dead (insn); | |
20b71b17 AM |
10548 | } |
10549 | else if (DEFAULT_ABI == ABI_AIX) | |
9ebbca7d GK |
10550 | { |
10551 | if (TARGET_32BIT) | |
027fbf43 | 10552 | insn = emit_insn (gen_load_toc_aix_si (dest)); |
9ebbca7d | 10553 | else |
027fbf43 JJ |
10554 | insn = emit_insn (gen_load_toc_aix_di (dest)); |
10555 | if (fromprolog) | |
10556 | rs6000_maybe_dead (insn); | |
9ebbca7d | 10557 | } |
20b71b17 AM |
10558 | else |
10559 | abort (); | |
9ebbca7d GK |
10560 | } |
10561 | ||
10562 | int | |
10563 | get_TOC_alias_set () | |
10564 | { | |
10565 | static int set = -1; | |
10566 | if (set == -1) | |
10567 | set = new_alias_set (); | |
10568 | return set; | |
10569 | } | |
10570 | ||
10571 | /* This retuns nonzero if the current function uses the TOC. This is | |
c4501e62 JJ |
10572 | determined by the presence of (unspec ... UNSPEC_TOC) or |
10573 | use (unspec ... UNSPEC_TOC), which are generated by the various | |
10574 | load_toc_* patterns. */ | |
a4f6c312 | 10575 | |
9ebbca7d GK |
10576 | int |
10577 | uses_TOC () | |
10578 | { | |
c4501e62 | 10579 | rtx insn; |
38c1f2d7 | 10580 | |
c4501e62 JJ |
10581 | for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) |
10582 | if (INSN_P (insn)) | |
10583 | { | |
10584 | rtx pat = PATTERN (insn); | |
10585 | int i; | |
9ebbca7d | 10586 | |
c4501e62 JJ |
10587 | if (GET_CODE (pat) == PARALLEL) |
10588 | for (i = 0; i < XVECLEN (pat, 0); i++) | |
10589 | { | |
10590 | rtx sub = XVECEXP (pat, 0, i); | |
10591 | if (GET_CODE (sub) == USE) | |
10592 | { | |
10593 | sub = XEXP (sub, 0); | |
10594 | if (GET_CODE (sub) == UNSPEC | |
10595 | && XINT (sub, 1) == UNSPEC_TOC) | |
10596 | return 1; | |
10597 | } | |
10598 | } | |
10599 | } | |
10600 | return 0; | |
9ebbca7d | 10601 | } |
38c1f2d7 | 10602 | |
9ebbca7d | 10603 | rtx |
a4f6c312 | 10604 | create_TOC_reference (symbol) |
9ebbca7d GK |
10605 | rtx symbol; |
10606 | { | |
a8a05998 ZW |
10607 | return gen_rtx_PLUS (Pmode, |
10608 | gen_rtx_REG (Pmode, TOC_REGISTER), | |
10609 | gen_rtx_CONST (Pmode, | |
10610 | gen_rtx_MINUS (Pmode, symbol, | |
b999aaeb | 10611 | gen_rtx_SYMBOL_REF (Pmode, toc_label_name)))); |
9ebbca7d | 10612 | } |
38c1f2d7 | 10613 | |
9ebbca7d GK |
10614 | /* __throw will restore its own return address to be the same as the |
10615 | return address of the function that the throw is being made to. | |
10616 | This is unfortunate, because we want to check the original | |
10617 | return address to see if we need to restore the TOC. | |
10618 | So we have to squirrel it away here. | |
10619 | This is used only in compiling __throw and __rethrow. | |
c7ca610e | 10620 | |
9ebbca7d GK |
10621 | Most of this code should be removed by CSE. */ |
10622 | static rtx insn_after_throw; | |
c7ca610e | 10623 | |
a4f6c312 | 10624 | /* This does the saving... */ |
9ebbca7d GK |
10625 | void |
10626 | rs6000_aix_emit_builtin_unwind_init () | |
10627 | { | |
10628 | rtx mem; | |
10629 | rtx stack_top = gen_reg_rtx (Pmode); | |
10630 | rtx opcode_addr = gen_reg_rtx (Pmode); | |
10631 | ||
10632 | insn_after_throw = gen_reg_rtx (SImode); | |
10633 | ||
10634 | mem = gen_rtx_MEM (Pmode, hard_frame_pointer_rtx); | |
10635 | emit_move_insn (stack_top, mem); | |
10636 | ||
10637 | mem = gen_rtx_MEM (Pmode, | |
10638 | gen_rtx_PLUS (Pmode, stack_top, | |
10639 | GEN_INT (2 * GET_MODE_SIZE (Pmode)))); | |
10640 | emit_move_insn (opcode_addr, mem); | |
10641 | emit_move_insn (insn_after_throw, gen_rtx_MEM (SImode, opcode_addr)); | |
c7ca610e RK |
10642 | } |
10643 | ||
a4f6c312 SS |
10644 | /* Emit insns to _restore_ the TOC register, at runtime (specifically |
10645 | in _eh.o). Only used on AIX. | |
9ebbca7d GK |
10646 | |
10647 | The idea is that on AIX, function calls look like this: | |
10648 | bl somefunction-trampoline | |
10649 | lwz r2,20(sp) | |
10650 | ||
a4f6c312 | 10651 | and later, |
9ebbca7d GK |
10652 | somefunction-trampoline: |
10653 | stw r2,20(sp) | |
10654 | ... load function address in the count register ... | |
10655 | bctr | |
10656 | or like this, if the linker determines that this is not a cross-module call | |
10657 | and so the TOC need not be restored: | |
10658 | bl somefunction | |
10659 | nop | |
10660 | or like this, if the compiler could determine that this is not a | |
10661 | cross-module call: | |
10662 | bl somefunction | |
10663 | now, the tricky bit here is that register 2 is saved and restored | |
10664 | by the _linker_, so we can't readily generate debugging information | |
10665 | for it. So we need to go back up the call chain looking at the | |
10666 | insns at return addresses to see which calls saved the TOC register | |
10667 | and so see where it gets restored from. | |
10668 | ||
10669 | Oh, and all this gets done in RTL inside the eh_epilogue pattern, | |
10670 | just before the actual epilogue. | |
10671 | ||
10672 | On the bright side, this incurs no space or time overhead unless an | |
10673 | exception is thrown, except for the extra code in libgcc.a. | |
10674 | ||
10675 | The parameter STACKSIZE is a register containing (at runtime) | |
10676 | the amount to be popped off the stack in addition to the stack frame | |
10677 | of this routine (which will be __throw or __rethrow, and so is | |
10678 | guaranteed to have a stack frame). */ | |
a4f6c312 | 10679 | |
9ebbca7d GK |
10680 | void |
10681 | rs6000_emit_eh_toc_restore (stacksize) | |
10682 | rtx stacksize; | |
10683 | { | |
10684 | rtx top_of_stack; | |
10685 | rtx bottom_of_stack = gen_reg_rtx (Pmode); | |
10686 | rtx tocompare = gen_reg_rtx (SImode); | |
10687 | rtx opcode = gen_reg_rtx (SImode); | |
10688 | rtx opcode_addr = gen_reg_rtx (Pmode); | |
10689 | rtx mem; | |
10690 | rtx loop_start = gen_label_rtx (); | |
10691 | rtx no_toc_restore_needed = gen_label_rtx (); | |
10692 | rtx loop_exit = gen_label_rtx (); | |
10693 | ||
10694 | mem = gen_rtx_MEM (Pmode, hard_frame_pointer_rtx); | |
ba4828e0 | 10695 | set_mem_alias_set (mem, rs6000_sr_alias_set); |
9ebbca7d GK |
10696 | emit_move_insn (bottom_of_stack, mem); |
10697 | ||
10698 | top_of_stack = expand_binop (Pmode, add_optab, | |
10699 | bottom_of_stack, stacksize, | |
10700 | NULL_RTX, 1, OPTAB_WIDEN); | |
10701 | ||
2496c7bd LB |
10702 | emit_move_insn (tocompare, gen_int_mode (TARGET_32BIT ? 0x80410014 |
10703 | : 0xE8410028, SImode)); | |
9ebbca7d GK |
10704 | |
10705 | if (insn_after_throw == NULL_RTX) | |
a4f6c312 | 10706 | abort (); |
9ebbca7d GK |
10707 | emit_move_insn (opcode, insn_after_throw); |
10708 | ||
6496a589 | 10709 | emit_note (NULL, NOTE_INSN_LOOP_BEG); |
9ebbca7d GK |
10710 | emit_label (loop_start); |
10711 | ||
10712 | do_compare_rtx_and_jump (opcode, tocompare, NE, 1, | |
06f4e019 | 10713 | SImode, NULL_RTX, NULL_RTX, |
9ebbca7d GK |
10714 | no_toc_restore_needed); |
10715 | ||
10716 | mem = gen_rtx_MEM (Pmode, | |
10717 | gen_rtx_PLUS (Pmode, bottom_of_stack, | |
10718 | GEN_INT (5 * GET_MODE_SIZE (Pmode)))); | |
10719 | emit_move_insn (gen_rtx_REG (Pmode, 2), mem); | |
10720 | ||
10721 | emit_label (no_toc_restore_needed); | |
10722 | do_compare_rtx_and_jump (top_of_stack, bottom_of_stack, EQ, 1, | |
06f4e019 | 10723 | Pmode, NULL_RTX, NULL_RTX, |
9ebbca7d GK |
10724 | loop_exit); |
10725 | ||
10726 | mem = gen_rtx_MEM (Pmode, bottom_of_stack); | |
ba4828e0 | 10727 | set_mem_alias_set (mem, rs6000_sr_alias_set); |
9ebbca7d GK |
10728 | emit_move_insn (bottom_of_stack, mem); |
10729 | ||
10730 | mem = gen_rtx_MEM (Pmode, | |
10731 | gen_rtx_PLUS (Pmode, bottom_of_stack, | |
10732 | GEN_INT (2 * GET_MODE_SIZE (Pmode)))); | |
10733 | emit_move_insn (opcode_addr, mem); | |
10734 | emit_move_insn (opcode, gen_rtx_MEM (SImode, opcode_addr)); | |
10735 | ||
6496a589 | 10736 | emit_note (NULL, NOTE_INSN_LOOP_CONT); |
9ebbca7d | 10737 | emit_jump (loop_start); |
6496a589 | 10738 | emit_note (NULL, NOTE_INSN_LOOP_END); |
9ebbca7d GK |
10739 | emit_label (loop_exit); |
10740 | } | |
38c1f2d7 | 10741 | \f |
ba4828e0 RK |
10742 | /* This ties together stack memory (MEM with an alias set of |
10743 | rs6000_sr_alias_set) and the change to the stack pointer. */ | |
10744 | ||
9ebbca7d GK |
10745 | static void |
10746 | rs6000_emit_stack_tie () | |
10747 | { | |
ba4828e0 RK |
10748 | rtx mem = gen_rtx_MEM (BLKmode, gen_rtx_REG (Pmode, STACK_POINTER_REGNUM)); |
10749 | ||
10750 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
9ebbca7d GK |
10751 | emit_insn (gen_stack_tie (mem)); |
10752 | } | |
38c1f2d7 | 10753 | |
9ebbca7d GK |
10754 | /* Emit the correct code for allocating stack space, as insns. |
10755 | If COPY_R12, make sure a copy of the old frame is left in r12. | |
10756 | The generated code may use hard register 0 as a temporary. */ | |
10757 | ||
10758 | static void | |
10759 | rs6000_emit_allocate_stack (size, copy_r12) | |
10760 | HOST_WIDE_INT size; | |
38c1f2d7 MM |
10761 | int copy_r12; |
10762 | { | |
9ebbca7d GK |
10763 | rtx insn; |
10764 | rtx stack_reg = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM); | |
10765 | rtx tmp_reg = gen_rtx_REG (Pmode, 0); | |
10766 | rtx todec = GEN_INT (-size); | |
a157febd GK |
10767 | |
10768 | if (current_function_limit_stack) | |
10769 | { | |
10770 | if (REG_P (stack_limit_rtx) | |
10771 | && REGNO (stack_limit_rtx) > 1 | |
10772 | && REGNO (stack_limit_rtx) <= 31) | |
10773 | { | |
5b71a4e7 | 10774 | emit_insn (TARGET_32BIT |
9ebbca7d GK |
10775 | ? gen_addsi3 (tmp_reg, |
10776 | stack_limit_rtx, | |
10777 | GEN_INT (size)) | |
10778 | : gen_adddi3 (tmp_reg, | |
10779 | stack_limit_rtx, | |
10780 | GEN_INT (size))); | |
5b71a4e7 | 10781 | |
9ebbca7d GK |
10782 | emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg, |
10783 | const0_rtx)); | |
a157febd GK |
10784 | } |
10785 | else if (GET_CODE (stack_limit_rtx) == SYMBOL_REF | |
9ebbca7d | 10786 | && TARGET_32BIT |
f607bc57 | 10787 | && DEFAULT_ABI == ABI_V4) |
a157febd | 10788 | { |
9ebbca7d GK |
10789 | rtx toload = gen_rtx_CONST (VOIDmode, |
10790 | gen_rtx_PLUS (Pmode, | |
10791 | stack_limit_rtx, | |
10792 | GEN_INT (size))); | |
5b71a4e7 | 10793 | |
9ebbca7d GK |
10794 | emit_insn (gen_elf_high (tmp_reg, toload)); |
10795 | emit_insn (gen_elf_low (tmp_reg, tmp_reg, toload)); | |
10796 | emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg, | |
10797 | const0_rtx)); | |
a157febd GK |
10798 | } |
10799 | else | |
10800 | warning ("stack limit expression is not supported"); | |
10801 | } | |
10802 | ||
9ebbca7d GK |
10803 | if (copy_r12 || ! TARGET_UPDATE) |
10804 | emit_move_insn (gen_rtx_REG (Pmode, 12), stack_reg); | |
10805 | ||
38c1f2d7 MM |
10806 | if (TARGET_UPDATE) |
10807 | { | |
9ebbca7d | 10808 | if (size > 32767) |
38c1f2d7 | 10809 | { |
9ebbca7d GK |
10810 | /* Need a note here so that try_split doesn't get confused. */ |
10811 | if (get_last_insn() == NULL_RTX) | |
10812 | emit_note (0, NOTE_INSN_DELETED); | |
10813 | insn = emit_move_insn (tmp_reg, todec); | |
10814 | try_split (PATTERN (insn), insn, 0); | |
10815 | todec = tmp_reg; | |
38c1f2d7 | 10816 | } |
5b71a4e7 DE |
10817 | |
10818 | insn = emit_insn (TARGET_32BIT | |
10819 | ? gen_movsi_update (stack_reg, stack_reg, | |
10820 | todec, stack_reg) | |
10821 | : gen_movdi_update (stack_reg, stack_reg, | |
9ebbca7d | 10822 | todec, stack_reg)); |
38c1f2d7 MM |
10823 | } |
10824 | else | |
10825 | { | |
5b71a4e7 DE |
10826 | insn = emit_insn (TARGET_32BIT |
10827 | ? gen_addsi3 (stack_reg, stack_reg, todec) | |
10828 | : gen_adddi3 (stack_reg, stack_reg, todec)); | |
9ebbca7d GK |
10829 | emit_move_insn (gen_rtx_MEM (Pmode, stack_reg), |
10830 | gen_rtx_REG (Pmode, 12)); | |
10831 | } | |
5b71a4e7 | 10832 | |
9ebbca7d GK |
10833 | RTX_FRAME_RELATED_P (insn) = 1; |
10834 | REG_NOTES (insn) = | |
10835 | gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, | |
10836 | gen_rtx_SET (VOIDmode, stack_reg, | |
10837 | gen_rtx_PLUS (Pmode, stack_reg, | |
10838 | GEN_INT (-size))), | |
10839 | REG_NOTES (insn)); | |
10840 | } | |
10841 | ||
a4f6c312 SS |
10842 | /* Add to 'insn' a note which is PATTERN (INSN) but with REG replaced |
10843 | with (plus:P (reg 1) VAL), and with REG2 replaced with RREG if REG2 | |
10844 | is not NULL. It would be nice if dwarf2out_frame_debug_expr could | |
10845 | deduce these equivalences by itself so it wasn't necessary to hold | |
10846 | its hand so much. */ | |
9ebbca7d GK |
10847 | |
10848 | static void | |
10849 | rs6000_frame_related (insn, reg, val, reg2, rreg) | |
10850 | rtx insn; | |
10851 | rtx reg; | |
10852 | HOST_WIDE_INT val; | |
10853 | rtx reg2; | |
10854 | rtx rreg; | |
10855 | { | |
10856 | rtx real, temp; | |
10857 | ||
e56c4463 JL |
10858 | /* copy_rtx will not make unique copies of registers, so we need to |
10859 | ensure we don't have unwanted sharing here. */ | |
10860 | if (reg == reg2) | |
10861 | reg = gen_raw_REG (GET_MODE (reg), REGNO (reg)); | |
10862 | ||
10863 | if (reg == rreg) | |
10864 | reg = gen_raw_REG (GET_MODE (reg), REGNO (reg)); | |
10865 | ||
9ebbca7d GK |
10866 | real = copy_rtx (PATTERN (insn)); |
10867 | ||
89e7058f AH |
10868 | if (reg2 != NULL_RTX) |
10869 | real = replace_rtx (real, reg2, rreg); | |
10870 | ||
9ebbca7d GK |
10871 | real = replace_rtx (real, reg, |
10872 | gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode, | |
10873 | STACK_POINTER_REGNUM), | |
10874 | GEN_INT (val))); | |
10875 | ||
10876 | /* We expect that 'real' is either a SET or a PARALLEL containing | |
10877 | SETs (and possibly other stuff). In a PARALLEL, all the SETs | |
10878 | are important so they all have to be marked RTX_FRAME_RELATED_P. */ | |
10879 | ||
10880 | if (GET_CODE (real) == SET) | |
10881 | { | |
10882 | rtx set = real; | |
10883 | ||
10884 | temp = simplify_rtx (SET_SRC (set)); | |
10885 | if (temp) | |
10886 | SET_SRC (set) = temp; | |
10887 | temp = simplify_rtx (SET_DEST (set)); | |
10888 | if (temp) | |
10889 | SET_DEST (set) = temp; | |
10890 | if (GET_CODE (SET_DEST (set)) == MEM) | |
38c1f2d7 | 10891 | { |
9ebbca7d GK |
10892 | temp = simplify_rtx (XEXP (SET_DEST (set), 0)); |
10893 | if (temp) | |
10894 | XEXP (SET_DEST (set), 0) = temp; | |
38c1f2d7 | 10895 | } |
38c1f2d7 | 10896 | } |
9ebbca7d GK |
10897 | else if (GET_CODE (real) == PARALLEL) |
10898 | { | |
10899 | int i; | |
10900 | for (i = 0; i < XVECLEN (real, 0); i++) | |
10901 | if (GET_CODE (XVECEXP (real, 0, i)) == SET) | |
10902 | { | |
10903 | rtx set = XVECEXP (real, 0, i); | |
10904 | ||
10905 | temp = simplify_rtx (SET_SRC (set)); | |
10906 | if (temp) | |
10907 | SET_SRC (set) = temp; | |
10908 | temp = simplify_rtx (SET_DEST (set)); | |
10909 | if (temp) | |
10910 | SET_DEST (set) = temp; | |
10911 | if (GET_CODE (SET_DEST (set)) == MEM) | |
10912 | { | |
10913 | temp = simplify_rtx (XEXP (SET_DEST (set), 0)); | |
10914 | if (temp) | |
10915 | XEXP (SET_DEST (set), 0) = temp; | |
10916 | } | |
10917 | RTX_FRAME_RELATED_P (set) = 1; | |
10918 | } | |
10919 | } | |
10920 | else | |
a4f6c312 | 10921 | abort (); |
c19de7aa AH |
10922 | |
10923 | if (TARGET_SPE) | |
10924 | real = spe_synthesize_frame_save (real); | |
10925 | ||
9ebbca7d GK |
10926 | RTX_FRAME_RELATED_P (insn) = 1; |
10927 | REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, | |
10928 | real, | |
10929 | REG_NOTES (insn)); | |
38c1f2d7 MM |
10930 | } |
10931 | ||
c19de7aa AH |
10932 | /* Given an SPE frame note, return a PARALLEL of SETs with the |
10933 | original note, plus a synthetic register save. */ | |
10934 | ||
10935 | static rtx | |
10936 | spe_synthesize_frame_save (real) | |
10937 | rtx real; | |
10938 | { | |
10939 | rtx synth, offset, reg, real2; | |
10940 | ||
10941 | if (GET_CODE (real) != SET | |
10942 | || GET_MODE (SET_SRC (real)) != V2SImode) | |
10943 | return real; | |
10944 | ||
10945 | /* For the SPE, registers saved in 64-bits, get a PARALLEL for their | |
10946 | frame related note. The parallel contains a set of the register | |
41f3a930 | 10947 | being saved, and another set to a synthetic register (n+1200). |
c19de7aa AH |
10948 | This is so we can differentiate between 64-bit and 32-bit saves. |
10949 | Words cannot describe this nastiness. */ | |
10950 | ||
10951 | if (GET_CODE (SET_DEST (real)) != MEM | |
10952 | || GET_CODE (XEXP (SET_DEST (real), 0)) != PLUS | |
10953 | || GET_CODE (SET_SRC (real)) != REG) | |
10954 | abort (); | |
10955 | ||
10956 | /* Transform: | |
10957 | (set (mem (plus (reg x) (const y))) | |
10958 | (reg z)) | |
10959 | into: | |
10960 | (set (mem (plus (reg x) (const y+4))) | |
41f3a930 | 10961 | (reg z+1200)) |
c19de7aa AH |
10962 | */ |
10963 | ||
10964 | real2 = copy_rtx (real); | |
10965 | PUT_MODE (SET_DEST (real2), SImode); | |
10966 | reg = SET_SRC (real2); | |
10967 | real2 = replace_rtx (real2, reg, gen_rtx_REG (SImode, REGNO (reg))); | |
10968 | synth = copy_rtx (real2); | |
10969 | ||
10970 | if (BYTES_BIG_ENDIAN) | |
10971 | { | |
10972 | offset = XEXP (XEXP (SET_DEST (real2), 0), 1); | |
10973 | real2 = replace_rtx (real2, offset, GEN_INT (INTVAL (offset) + 4)); | |
10974 | } | |
10975 | ||
10976 | reg = SET_SRC (synth); | |
41f3a930 | 10977 | |
c19de7aa | 10978 | synth = replace_rtx (synth, reg, |
41f3a930 | 10979 | gen_rtx_REG (SImode, REGNO (reg) + 1200)); |
c19de7aa AH |
10980 | |
10981 | offset = XEXP (XEXP (SET_DEST (synth), 0), 1); | |
10982 | synth = replace_rtx (synth, offset, | |
10983 | GEN_INT (INTVAL (offset) | |
10984 | + (BYTES_BIG_ENDIAN ? 0 : 4))); | |
10985 | ||
10986 | RTX_FRAME_RELATED_P (synth) = 1; | |
10987 | RTX_FRAME_RELATED_P (real2) = 1; | |
10988 | if (BYTES_BIG_ENDIAN) | |
10989 | real = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, synth, real2)); | |
10990 | else | |
10991 | real = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, real2, synth)); | |
10992 | ||
10993 | return real; | |
10994 | } | |
10995 | ||
00b960c7 AH |
10996 | /* Returns an insn that has a vrsave set operation with the |
10997 | appropriate CLOBBERs. */ | |
10998 | ||
10999 | static rtx | |
9aa86737 | 11000 | generate_set_vrsave (reg, info, epiloguep) |
00b960c7 AH |
11001 | rtx reg; |
11002 | rs6000_stack_t *info; | |
9aa86737 | 11003 | int epiloguep; |
00b960c7 AH |
11004 | { |
11005 | int nclobs, i; | |
11006 | rtx insn, clobs[TOTAL_ALTIVEC_REGS + 1]; | |
a004eb82 | 11007 | rtx vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO); |
00b960c7 | 11008 | |
a004eb82 AH |
11009 | clobs[0] |
11010 | = gen_rtx_SET (VOIDmode, | |
11011 | vrsave, | |
11012 | gen_rtx_UNSPEC_VOLATILE (SImode, | |
11013 | gen_rtvec (2, reg, vrsave), | |
11014 | 30)); | |
00b960c7 AH |
11015 | |
11016 | nclobs = 1; | |
11017 | ||
9aa86737 AH |
11018 | /* We need to clobber the registers in the mask so the scheduler |
11019 | does not move sets to VRSAVE before sets of AltiVec registers. | |
11020 | ||
11021 | However, if the function receives nonlocal gotos, reload will set | |
11022 | all call saved registers live. We will end up with: | |
11023 | ||
11024 | (set (reg 999) (mem)) | |
11025 | (parallel [ (set (reg vrsave) (unspec blah)) | |
11026 | (clobber (reg 999))]) | |
11027 | ||
11028 | The clobber will cause the store into reg 999 to be dead, and | |
11029 | flow will attempt to delete an epilogue insn. In this case, we | |
11030 | need an unspec use/set of the register. */ | |
00b960c7 AH |
11031 | |
11032 | for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i) | |
11033 | if (info->vrsave_mask != 0 && ALTIVEC_REG_BIT (i) != 0) | |
9aa86737 AH |
11034 | { |
11035 | if (!epiloguep || call_used_regs [i]) | |
11036 | clobs[nclobs++] = gen_rtx_CLOBBER (VOIDmode, | |
11037 | gen_rtx_REG (V4SImode, i)); | |
11038 | else | |
11039 | { | |
11040 | rtx reg = gen_rtx_REG (V4SImode, i); | |
9aa86737 AH |
11041 | |
11042 | clobs[nclobs++] | |
a004eb82 AH |
11043 | = gen_rtx_SET (VOIDmode, |
11044 | reg, | |
11045 | gen_rtx_UNSPEC (V4SImode, | |
11046 | gen_rtvec (1, reg), 27)); | |
9aa86737 AH |
11047 | } |
11048 | } | |
00b960c7 AH |
11049 | |
11050 | insn = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (nclobs)); | |
11051 | ||
11052 | for (i = 0; i < nclobs; ++i) | |
11053 | XVECEXP (insn, 0, i) = clobs[i]; | |
11054 | ||
11055 | return insn; | |
11056 | } | |
11057 | ||
89e7058f AH |
11058 | /* Save a register into the frame, and emit RTX_FRAME_RELATED_P notes. |
11059 | Save REGNO into [FRAME_REG + OFFSET] in mode MODE. */ | |
11060 | ||
11061 | static void | |
11062 | emit_frame_save (frame_reg, frame_ptr, mode, regno, offset, total_size) | |
11063 | rtx frame_reg; | |
11064 | rtx frame_ptr; | |
11065 | enum machine_mode mode; | |
11066 | unsigned int regno; | |
11067 | int offset; | |
11068 | int total_size; | |
11069 | { | |
11070 | rtx reg, offset_rtx, insn, mem, addr, int_rtx; | |
11071 | rtx replacea, replaceb; | |
11072 | ||
11073 | int_rtx = GEN_INT (offset); | |
11074 | ||
11075 | /* Some cases that need register indexed addressing. */ | |
11076 | if ((TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode)) | |
a3170dc6 AH |
11077 | || (TARGET_SPE_ABI |
11078 | && SPE_VECTOR_MODE (mode) | |
11079 | && !SPE_CONST_OFFSET_OK (offset))) | |
89e7058f AH |
11080 | { |
11081 | /* Whomever calls us must make sure r11 is available in the | |
11082 | flow path of instructions in the prologue. */ | |
11083 | offset_rtx = gen_rtx_REG (Pmode, 11); | |
11084 | emit_move_insn (offset_rtx, int_rtx); | |
11085 | ||
11086 | replacea = offset_rtx; | |
11087 | replaceb = int_rtx; | |
11088 | } | |
11089 | else | |
11090 | { | |
11091 | offset_rtx = int_rtx; | |
11092 | replacea = NULL_RTX; | |
11093 | replaceb = NULL_RTX; | |
11094 | } | |
11095 | ||
11096 | reg = gen_rtx_REG (mode, regno); | |
11097 | addr = gen_rtx_PLUS (Pmode, frame_reg, offset_rtx); | |
11098 | mem = gen_rtx_MEM (mode, addr); | |
11099 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
11100 | ||
11101 | insn = emit_move_insn (mem, reg); | |
11102 | ||
11103 | rs6000_frame_related (insn, frame_ptr, total_size, replacea, replaceb); | |
11104 | } | |
11105 | ||
a3170dc6 AH |
11106 | /* Emit an offset memory reference suitable for a frame store, while |
11107 | converting to a valid addressing mode. */ | |
11108 | ||
11109 | static rtx | |
11110 | gen_frame_mem_offset (mode, reg, offset) | |
11111 | enum machine_mode mode; | |
11112 | rtx reg; | |
11113 | int offset; | |
11114 | { | |
11115 | rtx int_rtx, offset_rtx; | |
11116 | ||
11117 | int_rtx = GEN_INT (offset); | |
11118 | ||
11119 | if (TARGET_SPE_ABI && SPE_VECTOR_MODE (mode)) | |
11120 | { | |
11121 | offset_rtx = gen_rtx_REG (Pmode, FIXED_SCRATCH); | |
11122 | emit_move_insn (offset_rtx, int_rtx); | |
11123 | } | |
11124 | else | |
11125 | offset_rtx = int_rtx; | |
11126 | ||
11127 | return gen_rtx_MEM (mode, gen_rtx_PLUS (Pmode, reg, offset_rtx)); | |
11128 | } | |
11129 | ||
9ebbca7d GK |
11130 | /* Emit function prologue as insns. */ |
11131 | ||
9878760c | 11132 | void |
83720594 | 11133 | rs6000_emit_prologue () |
9878760c | 11134 | { |
4697a36c | 11135 | rs6000_stack_t *info = rs6000_stack_info (); |
9ebbca7d GK |
11136 | enum machine_mode reg_mode = TARGET_POWERPC64 ? DImode : SImode; |
11137 | int reg_size = TARGET_POWERPC64 ? 8 : 4; | |
11138 | rtx sp_reg_rtx = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM); | |
11139 | rtx frame_ptr_rtx = gen_rtx_REG (Pmode, 12); | |
11140 | rtx frame_reg_rtx = sp_reg_rtx; | |
11141 | rtx cr_save_rtx = NULL; | |
11142 | rtx insn; | |
11143 | int saving_FPRs_inline; | |
11144 | int using_store_multiple; | |
11145 | HOST_WIDE_INT sp_offset = 0; | |
11146 | ||
c19de7aa | 11147 | if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0) |
a3170dc6 AH |
11148 | { |
11149 | reg_mode = V2SImode; | |
11150 | reg_size = 8; | |
11151 | } | |
11152 | ||
9ebbca7d | 11153 | using_store_multiple = (TARGET_MULTIPLE && ! TARGET_POWERPC64 |
c19de7aa AH |
11154 | && (!TARGET_SPE_ABI |
11155 | || info->spe_64bit_regs_used == 0) | |
9ebbca7d GK |
11156 | && info->first_gp_reg_save < 31); |
11157 | saving_FPRs_inline = (info->first_fp_reg_save == 64 | |
11158 | || FP_SAVE_INLINE (info->first_fp_reg_save)); | |
11159 | ||
11160 | /* For V.4, update stack before we do any saving and set back pointer. */ | |
f607bc57 | 11161 | if (info->push_p && DEFAULT_ABI == ABI_V4) |
9ebbca7d GK |
11162 | { |
11163 | if (info->total_size < 32767) | |
11164 | sp_offset = info->total_size; | |
11165 | else | |
11166 | frame_reg_rtx = frame_ptr_rtx; | |
11167 | rs6000_emit_allocate_stack (info->total_size, | |
11168 | (frame_reg_rtx != sp_reg_rtx | |
11169 | && (info->cr_save_p | |
11170 | || info->lr_save_p | |
11171 | || info->first_fp_reg_save < 64 | |
11172 | || info->first_gp_reg_save < 32 | |
11173 | ))); | |
11174 | if (frame_reg_rtx != sp_reg_rtx) | |
11175 | rs6000_emit_stack_tie (); | |
11176 | } | |
11177 | ||
9aa86737 AH |
11178 | /* Save AltiVec registers if needed. */ |
11179 | if (TARGET_ALTIVEC_ABI && info->altivec_size != 0) | |
11180 | { | |
11181 | int i; | |
11182 | ||
11183 | /* There should be a non inline version of this, for when we | |
11184 | are saving lots of vector registers. */ | |
11185 | for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i) | |
11186 | if (info->vrsave_mask & ALTIVEC_REG_BIT (i)) | |
11187 | { | |
11188 | rtx areg, savereg, mem; | |
11189 | int offset; | |
11190 | ||
11191 | offset = info->altivec_save_offset + sp_offset | |
11192 | + 16 * (i - info->first_altivec_reg_save); | |
11193 | ||
11194 | savereg = gen_rtx_REG (V4SImode, i); | |
11195 | ||
11196 | areg = gen_rtx_REG (Pmode, 0); | |
11197 | emit_move_insn (areg, GEN_INT (offset)); | |
11198 | ||
11199 | /* AltiVec addressing mode is [reg+reg]. */ | |
11200 | mem = gen_rtx_MEM (V4SImode, | |
11201 | gen_rtx_PLUS (Pmode, frame_reg_rtx, areg)); | |
11202 | ||
11203 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
11204 | ||
11205 | insn = emit_move_insn (mem, savereg); | |
11206 | ||
5c242421 SB |
11207 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, |
11208 | areg, GEN_INT (offset)); | |
9aa86737 AH |
11209 | } |
11210 | } | |
11211 | ||
11212 | /* VRSAVE is a bit vector representing which AltiVec registers | |
11213 | are used. The OS uses this to determine which vector | |
11214 | registers to save on a context switch. We need to save | |
11215 | VRSAVE on the stack frame, add whatever AltiVec registers we | |
11216 | used in this function, and do the corresponding magic in the | |
11217 | epilogue. */ | |
11218 | ||
11219 | if (TARGET_ALTIVEC && info->vrsave_mask != 0) | |
11220 | { | |
a004eb82 | 11221 | rtx reg, mem, vrsave; |
9aa86737 AH |
11222 | int offset; |
11223 | ||
11224 | /* Get VRSAVE onto a GPR. */ | |
11225 | reg = gen_rtx_REG (SImode, 12); | |
a004eb82 | 11226 | vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO); |
b188f760 AH |
11227 | if (TARGET_MACHO) |
11228 | emit_insn (gen_get_vrsave_internal (reg)); | |
11229 | else | |
11230 | emit_insn (gen_rtx_SET (VOIDmode, reg, vrsave)); | |
9aa86737 AH |
11231 | |
11232 | /* Save VRSAVE. */ | |
11233 | offset = info->vrsave_save_offset + sp_offset; | |
11234 | mem | |
11235 | = gen_rtx_MEM (SImode, | |
11236 | gen_rtx_PLUS (Pmode, frame_reg_rtx, GEN_INT (offset))); | |
11237 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
11238 | insn = emit_move_insn (mem, reg); | |
11239 | ||
11240 | /* Include the registers in the mask. */ | |
11241 | emit_insn (gen_iorsi3 (reg, reg, GEN_INT ((int) info->vrsave_mask))); | |
11242 | ||
11243 | insn = emit_insn (generate_set_vrsave (reg, info, 0)); | |
11244 | } | |
11245 | ||
9ebbca7d GK |
11246 | /* If we use the link register, get it into r0. */ |
11247 | if (info->lr_save_p) | |
71f123ca | 11248 | emit_move_insn (gen_rtx_REG (Pmode, 0), |
9ebbca7d GK |
11249 | gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)); |
11250 | ||
11251 | /* If we need to save CR, put it into r12. */ | |
11252 | if (info->cr_save_p && frame_reg_rtx != frame_ptr_rtx) | |
11253 | { | |
11254 | cr_save_rtx = gen_rtx_REG (SImode, 12); | |
11255 | emit_insn (gen_movesi_from_cr (cr_save_rtx)); | |
11256 | } | |
11257 | ||
a4f6c312 SS |
11258 | /* Do any required saving of fpr's. If only one or two to save, do |
11259 | it ourselves. Otherwise, call function. */ | |
9ebbca7d GK |
11260 | if (saving_FPRs_inline) |
11261 | { | |
11262 | int i; | |
11263 | for (i = 0; i < 64 - info->first_fp_reg_save; i++) | |
11264 | if ((regs_ever_live[info->first_fp_reg_save+i] | |
11265 | && ! call_used_regs[info->first_fp_reg_save+i])) | |
89e7058f AH |
11266 | emit_frame_save (frame_reg_rtx, frame_ptr_rtx, DFmode, |
11267 | info->first_fp_reg_save + i, | |
11268 | info->fp_save_offset + sp_offset + 8 * i, | |
11269 | info->total_size); | |
9ebbca7d GK |
11270 | } |
11271 | else if (info->first_fp_reg_save != 64) | |
11272 | { | |
11273 | int i; | |
11274 | char rname[30]; | |
520a57c8 | 11275 | const char *alloc_rname; |
9ebbca7d GK |
11276 | rtvec p; |
11277 | p = rtvec_alloc (2 + 64 - info->first_fp_reg_save); | |
11278 | ||
11279 | RTVEC_ELT (p, 0) = gen_rtx_CLOBBER (VOIDmode, | |
11280 | gen_rtx_REG (Pmode, | |
11281 | LINK_REGISTER_REGNUM)); | |
11282 | sprintf (rname, "%s%d%s", SAVE_FP_PREFIX, | |
11283 | info->first_fp_reg_save - 32, SAVE_FP_SUFFIX); | |
a8a05998 | 11284 | alloc_rname = ggc_strdup (rname); |
9ebbca7d GK |
11285 | RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode, |
11286 | gen_rtx_SYMBOL_REF (Pmode, | |
11287 | alloc_rname)); | |
11288 | for (i = 0; i < 64 - info->first_fp_reg_save; i++) | |
11289 | { | |
11290 | rtx addr, reg, mem; | |
11291 | reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i); | |
11292 | addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
11293 | GEN_INT (info->fp_save_offset | |
11294 | + sp_offset + 8*i)); | |
11295 | mem = gen_rtx_MEM (DFmode, addr); | |
ba4828e0 | 11296 | set_mem_alias_set (mem, rs6000_sr_alias_set); |
9ebbca7d GK |
11297 | |
11298 | RTVEC_ELT (p, i + 2) = gen_rtx_SET (VOIDmode, mem, reg); | |
11299 | } | |
11300 | insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p)); | |
11301 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, | |
11302 | NULL_RTX, NULL_RTX); | |
11303 | } | |
b6c9286a | 11304 | |
9ebbca7d GK |
11305 | /* Save GPRs. This is done as a PARALLEL if we are using |
11306 | the store-multiple instructions. */ | |
11307 | if (using_store_multiple) | |
b6c9286a | 11308 | { |
308c142a | 11309 | rtvec p; |
9ebbca7d GK |
11310 | int i; |
11311 | p = rtvec_alloc (32 - info->first_gp_reg_save); | |
9ebbca7d GK |
11312 | for (i = 0; i < 32 - info->first_gp_reg_save; i++) |
11313 | { | |
11314 | rtx addr, reg, mem; | |
11315 | reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i); | |
11316 | addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
11317 | GEN_INT (info->gp_save_offset | |
11318 | + sp_offset | |
11319 | + reg_size * i)); | |
11320 | mem = gen_rtx_MEM (reg_mode, addr); | |
ba4828e0 | 11321 | set_mem_alias_set (mem, rs6000_sr_alias_set); |
9ebbca7d GK |
11322 | |
11323 | RTVEC_ELT (p, i) = gen_rtx_SET (VOIDmode, mem, reg); | |
11324 | } | |
11325 | insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p)); | |
11326 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, | |
11327 | NULL_RTX, NULL_RTX); | |
b6c9286a MM |
11328 | } |
11329 | else | |
11330 | { | |
9ebbca7d GK |
11331 | int i; |
11332 | for (i = 0; i < 32 - info->first_gp_reg_save; i++) | |
11333 | if ((regs_ever_live[info->first_gp_reg_save+i] | |
11334 | && ! call_used_regs[info->first_gp_reg_save+i]) | |
1db02437 | 11335 | || (i+info->first_gp_reg_save == RS6000_PIC_OFFSET_TABLE_REGNUM |
14f00213 | 11336 | && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0) |
f607bc57 | 11337 | || (DEFAULT_ABI == ABI_DARWIN && flag_pic)))) |
a3170dc6 AH |
11338 | { |
11339 | rtx addr, reg, mem; | |
11340 | reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i); | |
11341 | ||
c19de7aa | 11342 | if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0) |
a3170dc6 AH |
11343 | { |
11344 | int offset = info->spe_gp_save_offset + sp_offset + 8 * i; | |
11345 | rtx b; | |
11346 | ||
11347 | if (!SPE_CONST_OFFSET_OK (offset)) | |
11348 | { | |
11349 | b = gen_rtx_REG (Pmode, FIXED_SCRATCH); | |
11350 | emit_move_insn (b, GEN_INT (offset)); | |
11351 | } | |
11352 | else | |
11353 | b = GEN_INT (offset); | |
11354 | ||
11355 | addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, b); | |
11356 | mem = gen_rtx_MEM (V2SImode, addr); | |
11357 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
11358 | insn = emit_move_insn (mem, reg); | |
11359 | ||
11360 | if (GET_CODE (b) == CONST_INT) | |
11361 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, | |
11362 | NULL_RTX, NULL_RTX); | |
11363 | else | |
11364 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, | |
11365 | b, GEN_INT (offset)); | |
11366 | } | |
11367 | else | |
11368 | { | |
11369 | addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
11370 | GEN_INT (info->gp_save_offset | |
11371 | + sp_offset | |
11372 | + reg_size * i)); | |
11373 | mem = gen_rtx_MEM (reg_mode, addr); | |
11374 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
11375 | ||
11376 | insn = emit_move_insn (mem, reg); | |
11377 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, | |
11378 | NULL_RTX, NULL_RTX); | |
11379 | } | |
11380 | } | |
9ebbca7d GK |
11381 | } |
11382 | ||
83720594 RH |
11383 | /* ??? There's no need to emit actual instructions here, but it's the |
11384 | easiest way to get the frame unwind information emitted. */ | |
11385 | if (current_function_calls_eh_return) | |
11386 | { | |
78e1b90d DE |
11387 | unsigned int i, regno; |
11388 | ||
83720594 RH |
11389 | for (i = 0; ; ++i) |
11390 | { | |
83720594 RH |
11391 | regno = EH_RETURN_DATA_REGNO (i); |
11392 | if (regno == INVALID_REGNUM) | |
11393 | break; | |
11394 | ||
89e7058f AH |
11395 | emit_frame_save (frame_reg_rtx, frame_ptr_rtx, reg_mode, regno, |
11396 | info->ehrd_offset + sp_offset | |
11397 | + reg_size * (int) i, | |
11398 | info->total_size); | |
83720594 RH |
11399 | } |
11400 | } | |
11401 | ||
9ebbca7d GK |
11402 | /* Save lr if we used it. */ |
11403 | if (info->lr_save_p) | |
11404 | { | |
11405 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
11406 | GEN_INT (info->lr_save_offset + sp_offset)); | |
11407 | rtx reg = gen_rtx_REG (Pmode, 0); | |
11408 | rtx mem = gen_rtx_MEM (Pmode, addr); | |
11409 | /* This should not be of rs6000_sr_alias_set, because of | |
11410 | __builtin_return_address. */ | |
11411 | ||
11412 | insn = emit_move_insn (mem, reg); | |
11413 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, | |
11414 | reg, gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)); | |
11415 | } | |
11416 | ||
11417 | /* Save CR if we use any that must be preserved. */ | |
11418 | if (info->cr_save_p) | |
11419 | { | |
11420 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
11421 | GEN_INT (info->cr_save_offset + sp_offset)); | |
11422 | rtx mem = gen_rtx_MEM (SImode, addr); | |
ba4828e0 RK |
11423 | |
11424 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
9ebbca7d GK |
11425 | |
11426 | /* If r12 was used to hold the original sp, copy cr into r0 now | |
11427 | that it's free. */ | |
11428 | if (REGNO (frame_reg_rtx) == 12) | |
11429 | { | |
11430 | cr_save_rtx = gen_rtx_REG (SImode, 0); | |
11431 | emit_insn (gen_movesi_from_cr (cr_save_rtx)); | |
11432 | } | |
11433 | insn = emit_move_insn (mem, cr_save_rtx); | |
11434 | ||
11435 | /* Now, there's no way that dwarf2out_frame_debug_expr is going | |
615158e2 JJ |
11436 | to understand '(unspec:SI [(reg:CC 68) ...] UNSPEC_MOVESI_FROM_CR)'. |
11437 | But that's OK. All we have to do is specify that _one_ condition | |
11438 | code register is saved in this stack slot. The thrower's epilogue | |
a1dc9455 FS |
11439 | will then restore all the call-saved registers. |
11440 | We use CR2_REGNO (70) to be compatible with gcc-2.95 on Linux. */ | |
9ebbca7d | 11441 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, |
a1dc9455 | 11442 | cr_save_rtx, gen_rtx_REG (SImode, CR2_REGNO)); |
9ebbca7d GK |
11443 | } |
11444 | ||
11445 | /* Update stack and set back pointer unless this is V.4, | |
11446 | for which it was done previously. */ | |
f607bc57 | 11447 | if (info->push_p && DEFAULT_ABI != ABI_V4) |
9ebbca7d GK |
11448 | rs6000_emit_allocate_stack (info->total_size, FALSE); |
11449 | ||
11450 | /* Set frame pointer, if needed. */ | |
11451 | if (frame_pointer_needed) | |
11452 | { | |
a3170dc6 | 11453 | insn = emit_move_insn (gen_rtx_REG (Pmode, FRAME_POINTER_REGNUM), |
9ebbca7d GK |
11454 | sp_reg_rtx); |
11455 | RTX_FRAME_RELATED_P (insn) = 1; | |
b6c9286a | 11456 | } |
9878760c | 11457 | |
1db02437 | 11458 | /* If we are using RS6000_PIC_OFFSET_TABLE_REGNUM, we need to set it up. */ |
9ebbca7d | 11459 | if ((TARGET_TOC && TARGET_MINIMAL_TOC && get_pool_size () != 0) |
f607bc57 | 11460 | || (DEFAULT_ABI == ABI_V4 && flag_pic == 1 |
1db02437 | 11461 | && regs_ever_live[RS6000_PIC_OFFSET_TABLE_REGNUM])) |
9ebbca7d GK |
11462 | { |
11463 | /* If emit_load_toc_table will use the link register, we need to save | |
c4501e62 | 11464 | it. We use R12 for this purpose because emit_load_toc_table |
9ebbca7d GK |
11465 | can use register 0. This allows us to use a plain 'blr' to return |
11466 | from the procedure more often. */ | |
f1384257 AM |
11467 | int save_LR_around_toc_setup = (TARGET_ELF |
11468 | && DEFAULT_ABI != ABI_AIX | |
11469 | && flag_pic | |
d5fa86ba GK |
11470 | && ! info->lr_save_p |
11471 | && EXIT_BLOCK_PTR->pred != NULL); | |
9ebbca7d | 11472 | if (save_LR_around_toc_setup) |
c4501e62 JJ |
11473 | { |
11474 | rtx lr = gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM); | |
11475 | rs6000_maybe_dead (emit_move_insn (frame_ptr_rtx, lr)); | |
11476 | rs6000_emit_load_toc_table (TRUE); | |
11477 | rs6000_maybe_dead (emit_move_insn (lr, frame_ptr_rtx)); | |
11478 | } | |
11479 | else | |
11480 | rs6000_emit_load_toc_table (TRUE); | |
9ebbca7d | 11481 | } |
ee890fe2 | 11482 | |
fcce224d | 11483 | #if TARGET_MACHO |
ee890fe2 SS |
11484 | if (DEFAULT_ABI == ABI_DARWIN |
11485 | && flag_pic && current_function_uses_pic_offset_table) | |
11486 | { | |
11487 | rtx dest = gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM); | |
f099d360 | 11488 | const char *picbase = machopic_function_base_name (); |
6788f5ca | 11489 | rtx src = gen_rtx_SYMBOL_REF (Pmode, picbase); |
ee890fe2 | 11490 | |
f51eee6a | 11491 | rs6000_maybe_dead (emit_insn (gen_load_macho_picbase (dest, src))); |
ee890fe2 SS |
11492 | |
11493 | rs6000_maybe_dead ( | |
1db02437 | 11494 | emit_move_insn (gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM), |
ee890fe2 SS |
11495 | gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM))); |
11496 | } | |
fcce224d | 11497 | #endif |
9ebbca7d GK |
11498 | } |
11499 | ||
9ebbca7d | 11500 | /* Write function prologue. */ |
a4f6c312 | 11501 | |
08c148a8 NB |
11502 | static void |
11503 | rs6000_output_function_prologue (file, size) | |
9ebbca7d | 11504 | FILE *file; |
08c148a8 | 11505 | HOST_WIDE_INT size ATTRIBUTE_UNUSED; |
9ebbca7d GK |
11506 | { |
11507 | rs6000_stack_t *info = rs6000_stack_info (); | |
11508 | ||
4697a36c MM |
11509 | if (TARGET_DEBUG_STACK) |
11510 | debug_stack_info (info); | |
9878760c | 11511 | |
a4f6c312 SS |
11512 | /* Write .extern for any function we will call to save and restore |
11513 | fp values. */ | |
11514 | if (info->first_fp_reg_save < 64 | |
11515 | && !FP_SAVE_INLINE (info->first_fp_reg_save)) | |
4d30c363 | 11516 | fprintf (file, "\t.extern %s%d%s\n\t.extern %s%d%s\n", |
4697a36c | 11517 | SAVE_FP_PREFIX, info->first_fp_reg_save - 32, SAVE_FP_SUFFIX, |
a4f6c312 SS |
11518 | RESTORE_FP_PREFIX, info->first_fp_reg_save - 32, |
11519 | RESTORE_FP_SUFFIX); | |
9878760c | 11520 | |
c764f757 RK |
11521 | /* Write .extern for AIX common mode routines, if needed. */ |
11522 | if (! TARGET_POWER && ! TARGET_POWERPC && ! common_mode_defined) | |
11523 | { | |
f6709c70 JW |
11524 | fputs ("\t.extern __mulh\n", file); |
11525 | fputs ("\t.extern __mull\n", file); | |
11526 | fputs ("\t.extern __divss\n", file); | |
11527 | fputs ("\t.extern __divus\n", file); | |
11528 | fputs ("\t.extern __quoss\n", file); | |
11529 | fputs ("\t.extern __quous\n", file); | |
c764f757 RK |
11530 | common_mode_defined = 1; |
11531 | } | |
9878760c | 11532 | |
9ebbca7d | 11533 | if (! HAVE_prologue) |
979721f8 | 11534 | { |
9ebbca7d | 11535 | start_sequence (); |
9dda4cc8 | 11536 | |
a4f6c312 SS |
11537 | /* A NOTE_INSN_DELETED is supposed to be at the start and end of |
11538 | the "toplevel" insn chain. */ | |
9ebbca7d GK |
11539 | emit_note (0, NOTE_INSN_DELETED); |
11540 | rs6000_emit_prologue (); | |
11541 | emit_note (0, NOTE_INSN_DELETED); | |
178c3eff DJ |
11542 | |
11543 | /* Expand INSN_ADDRESSES so final() doesn't crash. */ | |
11544 | { | |
11545 | rtx insn; | |
11546 | unsigned addr = 0; | |
11547 | for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn)) | |
11548 | { | |
11549 | INSN_ADDRESSES_NEW (insn, addr); | |
11550 | addr += 4; | |
11551 | } | |
11552 | } | |
9dda4cc8 | 11553 | |
9ebbca7d | 11554 | if (TARGET_DEBUG_STACK) |
a4f6c312 SS |
11555 | debug_rtx_list (get_insns (), 100); |
11556 | final (get_insns (), file, FALSE, FALSE); | |
9ebbca7d | 11557 | end_sequence (); |
979721f8 MM |
11558 | } |
11559 | ||
9ebbca7d GK |
11560 | rs6000_pic_labelno++; |
11561 | } | |
11562 | ||
11563 | /* Emit function epilogue as insns. | |
9878760c | 11564 | |
9ebbca7d GK |
11565 | At present, dwarf2out_frame_debug_expr doesn't understand |
11566 | register restores, so we don't bother setting RTX_FRAME_RELATED_P | |
11567 | anywhere in the epilogue. Most of the insns below would in any case | |
11568 | need special notes to explain where r11 is in relation to the stack. */ | |
9878760c | 11569 | |
9ebbca7d | 11570 | void |
83720594 | 11571 | rs6000_emit_epilogue (sibcall) |
9ebbca7d GK |
11572 | int sibcall; |
11573 | { | |
11574 | rs6000_stack_t *info; | |
11575 | int restoring_FPRs_inline; | |
11576 | int using_load_multiple; | |
11577 | int using_mfcr_multiple; | |
11578 | int use_backchain_to_restore_sp; | |
11579 | int sp_offset = 0; | |
11580 | rtx sp_reg_rtx = gen_rtx_REG (Pmode, 1); | |
11581 | rtx frame_reg_rtx = sp_reg_rtx; | |
11582 | enum machine_mode reg_mode = TARGET_POWERPC64 ? DImode : SImode; | |
11583 | int reg_size = TARGET_POWERPC64 ? 8 : 4; | |
11584 | int i; | |
11585 | ||
c19de7aa AH |
11586 | info = rs6000_stack_info (); |
11587 | ||
11588 | if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0) | |
a3170dc6 AH |
11589 | { |
11590 | reg_mode = V2SImode; | |
11591 | reg_size = 8; | |
11592 | } | |
11593 | ||
9ebbca7d | 11594 | using_load_multiple = (TARGET_MULTIPLE && ! TARGET_POWERPC64 |
c19de7aa AH |
11595 | && (!TARGET_SPE_ABI |
11596 | || info->spe_64bit_regs_used == 0) | |
9ebbca7d GK |
11597 | && info->first_gp_reg_save < 31); |
11598 | restoring_FPRs_inline = (sibcall | |
83720594 | 11599 | || current_function_calls_eh_return |
9ebbca7d GK |
11600 | || info->first_fp_reg_save == 64 |
11601 | || FP_SAVE_INLINE (info->first_fp_reg_save)); | |
11602 | use_backchain_to_restore_sp = (frame_pointer_needed | |
11603 | || current_function_calls_alloca | |
11604 | || info->total_size > 32767); | |
11605 | using_mfcr_multiple = (rs6000_cpu == PROCESSOR_PPC601 | |
11606 | || rs6000_cpu == PROCESSOR_PPC603 | |
11607 | || rs6000_cpu == PROCESSOR_PPC750 | |
11608 | || optimize_size); | |
11609 | ||
11610 | /* If we have a frame pointer, a call to alloca, or a large stack | |
11611 | frame, restore the old stack pointer using the backchain. Otherwise, | |
11612 | we know what size to update it with. */ | |
11613 | if (use_backchain_to_restore_sp) | |
bacbde18 | 11614 | { |
9ebbca7d GK |
11615 | /* Under V.4, don't reset the stack pointer until after we're done |
11616 | loading the saved registers. */ | |
f607bc57 | 11617 | if (DEFAULT_ABI == ABI_V4) |
9ebbca7d | 11618 | frame_reg_rtx = gen_rtx_REG (Pmode, 11); |
4697a36c | 11619 | |
9ebbca7d GK |
11620 | emit_move_insn (frame_reg_rtx, |
11621 | gen_rtx_MEM (Pmode, sp_reg_rtx)); | |
11622 | ||
bacbde18 | 11623 | } |
9ebbca7d | 11624 | else if (info->push_p) |
85638c0d | 11625 | { |
f607bc57 | 11626 | if (DEFAULT_ABI == ABI_V4) |
9ebbca7d GK |
11627 | sp_offset = info->total_size; |
11628 | else | |
11629 | { | |
11630 | emit_insn (TARGET_32BIT | |
11631 | ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx, | |
11632 | GEN_INT (info->total_size)) | |
11633 | : gen_adddi3 (sp_reg_rtx, sp_reg_rtx, | |
11634 | GEN_INT (info->total_size))); | |
11635 | } | |
85638c0d | 11636 | } |
9ebbca7d | 11637 | |
9aa86737 AH |
11638 | /* Restore AltiVec registers if needed. */ |
11639 | if (TARGET_ALTIVEC_ABI && info->altivec_size != 0) | |
11640 | { | |
11641 | int i; | |
11642 | ||
11643 | for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i) | |
11644 | if (info->vrsave_mask & ALTIVEC_REG_BIT (i)) | |
11645 | { | |
11646 | rtx addr, areg, mem; | |
11647 | ||
11648 | areg = gen_rtx_REG (Pmode, 0); | |
11649 | emit_move_insn | |
11650 | (areg, GEN_INT (info->altivec_save_offset | |
11651 | + sp_offset | |
11652 | + 16 * (i - info->first_altivec_reg_save))); | |
11653 | ||
11654 | /* AltiVec addressing mode is [reg+reg]. */ | |
11655 | addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, areg); | |
11656 | mem = gen_rtx_MEM (V4SImode, addr); | |
11657 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
11658 | ||
11659 | emit_move_insn (gen_rtx_REG (V4SImode, i), mem); | |
11660 | } | |
11661 | } | |
11662 | ||
11663 | /* Restore VRSAVE if needed. */ | |
11664 | if (TARGET_ALTIVEC_ABI && info->vrsave_mask != 0) | |
11665 | { | |
11666 | rtx addr, mem, reg; | |
11667 | ||
11668 | addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
11669 | GEN_INT (info->vrsave_save_offset + sp_offset)); | |
11670 | mem = gen_rtx_MEM (SImode, addr); | |
11671 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
11672 | reg = gen_rtx_REG (SImode, 12); | |
11673 | emit_move_insn (reg, mem); | |
11674 | ||
11675 | emit_insn (generate_set_vrsave (reg, info, 1)); | |
11676 | } | |
11677 | ||
9ebbca7d GK |
11678 | /* Get the old lr if we saved it. */ |
11679 | if (info->lr_save_p) | |
b6c9286a | 11680 | { |
a3170dc6 AH |
11681 | rtx mem = gen_frame_mem_offset (Pmode, frame_reg_rtx, |
11682 | info->lr_save_offset + sp_offset); | |
ba4828e0 RK |
11683 | |
11684 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
b6c9286a | 11685 | |
9ebbca7d | 11686 | emit_move_insn (gen_rtx_REG (Pmode, 0), mem); |
b6c9286a | 11687 | } |
9ebbca7d GK |
11688 | |
11689 | /* Get the old cr if we saved it. */ | |
11690 | if (info->cr_save_p) | |
11691 | { | |
11692 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
11693 | GEN_INT (info->cr_save_offset + sp_offset)); | |
11694 | rtx mem = gen_rtx_MEM (SImode, addr); | |
ba4828e0 RK |
11695 | |
11696 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
b6c9286a | 11697 | |
9ebbca7d GK |
11698 | emit_move_insn (gen_rtx_REG (SImode, 12), mem); |
11699 | } | |
11700 | ||
11701 | /* Set LR here to try to overlap restores below. */ | |
4697a36c | 11702 | if (info->lr_save_p) |
9ebbca7d GK |
11703 | emit_move_insn (gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM), |
11704 | gen_rtx_REG (Pmode, 0)); | |
11705 | ||
83720594 RH |
11706 | /* Load exception handler data registers, if needed. */ |
11707 | if (current_function_calls_eh_return) | |
11708 | { | |
78e1b90d DE |
11709 | unsigned int i, regno; |
11710 | ||
83720594 RH |
11711 | for (i = 0; ; ++i) |
11712 | { | |
a3170dc6 | 11713 | rtx mem; |
83720594 RH |
11714 | |
11715 | regno = EH_RETURN_DATA_REGNO (i); | |
11716 | if (regno == INVALID_REGNUM) | |
11717 | break; | |
11718 | ||
a3170dc6 AH |
11719 | mem = gen_frame_mem_offset (reg_mode, frame_reg_rtx, |
11720 | info->ehrd_offset + sp_offset | |
11721 | + reg_size * (int) i); | |
ba4828e0 | 11722 | set_mem_alias_set (mem, rs6000_sr_alias_set); |
83720594 RH |
11723 | |
11724 | emit_move_insn (gen_rtx_REG (reg_mode, regno), mem); | |
11725 | } | |
11726 | } | |
9ebbca7d GK |
11727 | |
11728 | /* Restore GPRs. This is done as a PARALLEL if we are using | |
11729 | the load-multiple instructions. */ | |
11730 | if (using_load_multiple) | |
979721f8 | 11731 | { |
9ebbca7d GK |
11732 | rtvec p; |
11733 | p = rtvec_alloc (32 - info->first_gp_reg_save); | |
11734 | for (i = 0; i < 32 - info->first_gp_reg_save; i++) | |
979721f8 | 11735 | { |
9ebbca7d GK |
11736 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, |
11737 | GEN_INT (info->gp_save_offset | |
11738 | + sp_offset | |
11739 | + reg_size * i)); | |
11740 | rtx mem = gen_rtx_MEM (reg_mode, addr); | |
ba4828e0 RK |
11741 | |
11742 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
9ebbca7d GK |
11743 | |
11744 | RTVEC_ELT (p, i) = | |
11745 | gen_rtx_SET (VOIDmode, | |
11746 | gen_rtx_REG (reg_mode, info->first_gp_reg_save + i), | |
11747 | mem); | |
979721f8 | 11748 | } |
9ebbca7d | 11749 | emit_insn (gen_rtx_PARALLEL (VOIDmode, p)); |
979721f8 | 11750 | } |
9ebbca7d GK |
11751 | else |
11752 | for (i = 0; i < 32 - info->first_gp_reg_save; i++) | |
11753 | if ((regs_ever_live[info->first_gp_reg_save+i] | |
11754 | && ! call_used_regs[info->first_gp_reg_save+i]) | |
1db02437 | 11755 | || (i+info->first_gp_reg_save == RS6000_PIC_OFFSET_TABLE_REGNUM |
14f00213 | 11756 | && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0) |
f607bc57 | 11757 | || (DEFAULT_ABI == ABI_DARWIN && flag_pic)))) |
9ebbca7d GK |
11758 | { |
11759 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
11760 | GEN_INT (info->gp_save_offset | |
11761 | + sp_offset | |
11762 | + reg_size * i)); | |
11763 | rtx mem = gen_rtx_MEM (reg_mode, addr); | |
ba4828e0 | 11764 | |
a3170dc6 | 11765 | /* Restore 64-bit quantities for SPE. */ |
c19de7aa | 11766 | if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0) |
a3170dc6 AH |
11767 | { |
11768 | int offset = info->spe_gp_save_offset + sp_offset + 8 * i; | |
11769 | rtx b; | |
11770 | ||
11771 | if (!SPE_CONST_OFFSET_OK (offset)) | |
11772 | { | |
11773 | b = gen_rtx_REG (Pmode, FIXED_SCRATCH); | |
11774 | emit_move_insn (b, GEN_INT (offset)); | |
11775 | } | |
11776 | else | |
11777 | b = GEN_INT (offset); | |
11778 | ||
11779 | addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, b); | |
11780 | mem = gen_rtx_MEM (V2SImode, addr); | |
11781 | } | |
11782 | ||
ba4828e0 | 11783 | set_mem_alias_set (mem, rs6000_sr_alias_set); |
9ebbca7d GK |
11784 | |
11785 | emit_move_insn (gen_rtx_REG (reg_mode, | |
a3170dc6 | 11786 | info->first_gp_reg_save + i), mem); |
9ebbca7d | 11787 | } |
9878760c | 11788 | |
9ebbca7d GK |
11789 | /* Restore fpr's if we need to do it without calling a function. */ |
11790 | if (restoring_FPRs_inline) | |
11791 | for (i = 0; i < 64 - info->first_fp_reg_save; i++) | |
11792 | if ((regs_ever_live[info->first_fp_reg_save+i] | |
11793 | && ! call_used_regs[info->first_fp_reg_save+i])) | |
11794 | { | |
11795 | rtx addr, mem; | |
11796 | addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
11797 | GEN_INT (info->fp_save_offset | |
11798 | + sp_offset | |
a4f6c312 | 11799 | + 8 * i)); |
9ebbca7d | 11800 | mem = gen_rtx_MEM (DFmode, addr); |
ba4828e0 | 11801 | set_mem_alias_set (mem, rs6000_sr_alias_set); |
9ebbca7d GK |
11802 | |
11803 | emit_move_insn (gen_rtx_REG (DFmode, | |
11804 | info->first_fp_reg_save + i), | |
11805 | mem); | |
11806 | } | |
8d30c4ee | 11807 | |
9ebbca7d GK |
11808 | /* If we saved cr, restore it here. Just those that were used. */ |
11809 | if (info->cr_save_p) | |
979721f8 | 11810 | { |
9ebbca7d | 11811 | rtx r12_rtx = gen_rtx_REG (SImode, 12); |
e35b9579 | 11812 | int count = 0; |
9ebbca7d GK |
11813 | |
11814 | if (using_mfcr_multiple) | |
979721f8 | 11815 | { |
9ebbca7d GK |
11816 | for (i = 0; i < 8; i++) |
11817 | if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i]) | |
e35b9579 | 11818 | count++; |
9ebbca7d | 11819 | if (count == 0) |
e35b9579 GK |
11820 | abort (); |
11821 | } | |
11822 | ||
11823 | if (using_mfcr_multiple && count > 1) | |
11824 | { | |
11825 | rtvec p; | |
11826 | int ndx; | |
9ebbca7d | 11827 | |
e35b9579 | 11828 | p = rtvec_alloc (count); |
9ebbca7d | 11829 | |
e35b9579 | 11830 | ndx = 0; |
9ebbca7d GK |
11831 | for (i = 0; i < 8; i++) |
11832 | if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i]) | |
11833 | { | |
11834 | rtvec r = rtvec_alloc (2); | |
11835 | RTVEC_ELT (r, 0) = r12_rtx; | |
11836 | RTVEC_ELT (r, 1) = GEN_INT (1 << (7-i)); | |
e35b9579 | 11837 | RTVEC_ELT (p, ndx) = |
9ebbca7d | 11838 | gen_rtx_SET (VOIDmode, gen_rtx_REG (CCmode, CR0_REGNO+i), |
615158e2 | 11839 | gen_rtx_UNSPEC (CCmode, r, UNSPEC_MOVESI_TO_CR)); |
e35b9579 | 11840 | ndx++; |
9ebbca7d GK |
11841 | } |
11842 | emit_insn (gen_rtx_PARALLEL (VOIDmode, p)); | |
e35b9579 GK |
11843 | if (ndx != count) |
11844 | abort (); | |
979721f8 MM |
11845 | } |
11846 | else | |
9ebbca7d GK |
11847 | for (i = 0; i < 8; i++) |
11848 | if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i]) | |
979721f8 | 11849 | { |
9ebbca7d GK |
11850 | emit_insn (gen_movsi_to_cr_one (gen_rtx_REG (CCmode, |
11851 | CR0_REGNO+i), | |
11852 | r12_rtx)); | |
979721f8 | 11853 | } |
979721f8 MM |
11854 | } |
11855 | ||
9ebbca7d GK |
11856 | /* If this is V.4, unwind the stack pointer after all of the loads |
11857 | have been done. We need to emit a block here so that sched | |
11858 | doesn't decide to move the sp change before the register restores | |
11859 | (which may not have any obvious dependency on the stack). This | |
11860 | doesn't hurt performance, because there is no scheduling that can | |
11861 | be done after this point. */ | |
f607bc57 | 11862 | if (DEFAULT_ABI == ABI_V4) |
b6c9286a | 11863 | { |
9ebbca7d GK |
11864 | if (frame_reg_rtx != sp_reg_rtx) |
11865 | rs6000_emit_stack_tie (); | |
b6c9286a | 11866 | |
9ebbca7d | 11867 | if (use_backchain_to_restore_sp) |
b6c9286a | 11868 | { |
9ebbca7d | 11869 | emit_move_insn (sp_reg_rtx, frame_reg_rtx); |
b6c9286a | 11870 | } |
9ebbca7d | 11871 | else if (sp_offset != 0) |
13f1623b | 11872 | { |
5b71a4e7 | 11873 | emit_insn (TARGET_32BIT |
9ebbca7d GK |
11874 | ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx, |
11875 | GEN_INT (sp_offset)) | |
11876 | : gen_adddi3 (sp_reg_rtx, sp_reg_rtx, | |
11877 | GEN_INT (sp_offset))); | |
13f1623b | 11878 | } |
9ebbca7d | 11879 | } |
b6c9286a | 11880 | |
83720594 RH |
11881 | if (current_function_calls_eh_return) |
11882 | { | |
11883 | rtx sa = EH_RETURN_STACKADJ_RTX; | |
5b71a4e7 | 11884 | emit_insn (TARGET_32BIT |
83720594 RH |
11885 | ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx, sa) |
11886 | : gen_adddi3 (sp_reg_rtx, sp_reg_rtx, sa)); | |
11887 | } | |
11888 | ||
9ebbca7d GK |
11889 | if (!sibcall) |
11890 | { | |
11891 | rtvec p; | |
11892 | if (! restoring_FPRs_inline) | |
11893 | p = rtvec_alloc (3 + 64 - info->first_fp_reg_save); | |
11894 | else | |
11895 | p = rtvec_alloc (2); | |
b6c9286a | 11896 | |
e35b9579 GK |
11897 | RTVEC_ELT (p, 0) = gen_rtx_RETURN (VOIDmode); |
11898 | RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode, | |
9ebbca7d GK |
11899 | gen_rtx_REG (Pmode, |
11900 | LINK_REGISTER_REGNUM)); | |
9ebbca7d GK |
11901 | |
11902 | /* If we have to restore more than two FP registers, branch to the | |
11903 | restore function. It will return to our caller. */ | |
11904 | if (! restoring_FPRs_inline) | |
11905 | { | |
11906 | int i; | |
11907 | char rname[30]; | |
520a57c8 | 11908 | const char *alloc_rname; |
979721f8 | 11909 | |
9ebbca7d GK |
11910 | sprintf (rname, "%s%d%s", RESTORE_FP_PREFIX, |
11911 | info->first_fp_reg_save - 32, RESTORE_FP_SUFFIX); | |
a8a05998 | 11912 | alloc_rname = ggc_strdup (rname); |
9ebbca7d GK |
11913 | RTVEC_ELT (p, 2) = gen_rtx_USE (VOIDmode, |
11914 | gen_rtx_SYMBOL_REF (Pmode, | |
11915 | alloc_rname)); | |
b6c9286a | 11916 | |
9ebbca7d GK |
11917 | for (i = 0; i < 64 - info->first_fp_reg_save; i++) |
11918 | { | |
11919 | rtx addr, mem; | |
11920 | addr = gen_rtx_PLUS (Pmode, sp_reg_rtx, | |
11921 | GEN_INT (info->fp_save_offset + 8*i)); | |
11922 | mem = gen_rtx_MEM (DFmode, addr); | |
ba4828e0 | 11923 | set_mem_alias_set (mem, rs6000_sr_alias_set); |
9ebbca7d GK |
11924 | |
11925 | RTVEC_ELT (p, i+3) = | |
11926 | gen_rtx_SET (VOIDmode, | |
11927 | gen_rtx_REG (DFmode, info->first_fp_reg_save + i), | |
11928 | mem); | |
b6c9286a MM |
11929 | } |
11930 | } | |
9ebbca7d GK |
11931 | |
11932 | emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p)); | |
3daf36a4 | 11933 | } |
9878760c RK |
11934 | } |
11935 | ||
11936 | /* Write function epilogue. */ | |
11937 | ||
08c148a8 NB |
11938 | static void |
11939 | rs6000_output_function_epilogue (file, size) | |
9878760c | 11940 | FILE *file; |
08c148a8 | 11941 | HOST_WIDE_INT size ATTRIBUTE_UNUSED; |
9878760c | 11942 | { |
4697a36c | 11943 | rs6000_stack_t *info = rs6000_stack_info (); |
9878760c | 11944 | |
9ebbca7d | 11945 | if (! HAVE_epilogue) |
9878760c | 11946 | { |
9ebbca7d GK |
11947 | rtx insn = get_last_insn (); |
11948 | /* If the last insn was a BARRIER, we don't have to write anything except | |
11949 | the trace table. */ | |
11950 | if (GET_CODE (insn) == NOTE) | |
11951 | insn = prev_nonnote_insn (insn); | |
11952 | if (insn == 0 || GET_CODE (insn) != BARRIER) | |
4697a36c | 11953 | { |
9ebbca7d GK |
11954 | /* This is slightly ugly, but at least we don't have two |
11955 | copies of the epilogue-emitting code. */ | |
11956 | start_sequence (); | |
11957 | ||
11958 | /* A NOTE_INSN_DELETED is supposed to be at the start | |
11959 | and end of the "toplevel" insn chain. */ | |
11960 | emit_note (0, NOTE_INSN_DELETED); | |
11961 | rs6000_emit_epilogue (FALSE); | |
11962 | emit_note (0, NOTE_INSN_DELETED); | |
11963 | ||
178c3eff DJ |
11964 | /* Expand INSN_ADDRESSES so final() doesn't crash. */ |
11965 | { | |
11966 | rtx insn; | |
11967 | unsigned addr = 0; | |
11968 | for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn)) | |
11969 | { | |
11970 | INSN_ADDRESSES_NEW (insn, addr); | |
11971 | addr += 4; | |
11972 | } | |
11973 | } | |
11974 | ||
9ebbca7d | 11975 | if (TARGET_DEBUG_STACK) |
a4f6c312 SS |
11976 | debug_rtx_list (get_insns (), 100); |
11977 | final (get_insns (), file, FALSE, FALSE); | |
9ebbca7d | 11978 | end_sequence (); |
4697a36c | 11979 | } |
9878760c | 11980 | } |
b4ac57ab | 11981 | |
9b30bae2 | 11982 | /* Output a traceback table here. See /usr/include/sys/debug.h for info |
314fc5a9 ILT |
11983 | on its format. |
11984 | ||
11985 | We don't output a traceback table if -finhibit-size-directive was | |
11986 | used. The documentation for -finhibit-size-directive reads | |
11987 | ``don't output a @code{.size} assembler directive, or anything | |
11988 | else that would cause trouble if the function is split in the | |
11989 | middle, and the two halves are placed at locations far apart in | |
11990 | memory.'' The traceback table has this property, since it | |
11991 | includes the offset from the start of the function to the | |
4d30c363 MM |
11992 | traceback table itself. |
11993 | ||
11994 | System V.4 Powerpc's (and the embedded ABI derived from it) use a | |
b6c9286a | 11995 | different traceback table. */ |
57ac7be9 AM |
11996 | if (DEFAULT_ABI == ABI_AIX && ! flag_inhibit_size_directive |
11997 | && rs6000_traceback != traceback_none) | |
9b30bae2 | 11998 | { |
69c75916 | 11999 | const char *fname = NULL; |
3ac88239 | 12000 | const char *language_string = lang_hooks.name; |
6041bf2f | 12001 | int fixed_parms = 0, float_parms = 0, parm_info = 0; |
314fc5a9 | 12002 | int i; |
57ac7be9 AM |
12003 | int optional_tbtab; |
12004 | ||
12005 | if (rs6000_traceback == traceback_full) | |
12006 | optional_tbtab = 1; | |
12007 | else if (rs6000_traceback == traceback_part) | |
12008 | optional_tbtab = 0; | |
12009 | else | |
12010 | optional_tbtab = !optimize_size && !TARGET_ELF; | |
314fc5a9 | 12011 | |
69c75916 AM |
12012 | if (optional_tbtab) |
12013 | { | |
12014 | fname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0); | |
12015 | while (*fname == '.') /* V.4 encodes . in the name */ | |
12016 | fname++; | |
12017 | ||
12018 | /* Need label immediately before tbtab, so we can compute | |
12019 | its offset from the function start. */ | |
12020 | ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT"); | |
12021 | ASM_OUTPUT_LABEL (file, fname); | |
12022 | } | |
314fc5a9 ILT |
12023 | |
12024 | /* The .tbtab pseudo-op can only be used for the first eight | |
12025 | expressions, since it can't handle the possibly variable | |
12026 | length fields that follow. However, if you omit the optional | |
12027 | fields, the assembler outputs zeros for all optional fields | |
12028 | anyways, giving each variable length field is minimum length | |
12029 | (as defined in sys/debug.h). Thus we can not use the .tbtab | |
12030 | pseudo-op at all. */ | |
12031 | ||
12032 | /* An all-zero word flags the start of the tbtab, for debuggers | |
12033 | that have to find it by searching forward from the entry | |
12034 | point or from the current pc. */ | |
19d2d16f | 12035 | fputs ("\t.long 0\n", file); |
314fc5a9 ILT |
12036 | |
12037 | /* Tbtab format type. Use format type 0. */ | |
19d2d16f | 12038 | fputs ("\t.byte 0,", file); |
314fc5a9 ILT |
12039 | |
12040 | /* Language type. Unfortunately, there doesn't seem to be any | |
12041 | official way to get this info, so we use language_string. C | |
12042 | is 0. C++ is 9. No number defined for Obj-C, so use the | |
9517ead8 | 12043 | value for C for now. There is no official value for Java, |
6f573ff9 | 12044 | although IBM appears to be using 13. There is no official value |
f710504c | 12045 | for Chill, so we've chosen 44 pseudo-randomly. */ |
314fc5a9 | 12046 | if (! strcmp (language_string, "GNU C") |
e2c953b6 | 12047 | || ! strcmp (language_string, "GNU Objective-C")) |
314fc5a9 ILT |
12048 | i = 0; |
12049 | else if (! strcmp (language_string, "GNU F77")) | |
12050 | i = 1; | |
12051 | else if (! strcmp (language_string, "GNU Ada")) | |
12052 | i = 3; | |
8b83775b | 12053 | else if (! strcmp (language_string, "GNU Pascal")) |
314fc5a9 ILT |
12054 | i = 2; |
12055 | else if (! strcmp (language_string, "GNU C++")) | |
12056 | i = 9; | |
9517ead8 AG |
12057 | else if (! strcmp (language_string, "GNU Java")) |
12058 | i = 13; | |
6f573ff9 JL |
12059 | else if (! strcmp (language_string, "GNU CHILL")) |
12060 | i = 44; | |
314fc5a9 ILT |
12061 | else |
12062 | abort (); | |
12063 | fprintf (file, "%d,", i); | |
12064 | ||
12065 | /* 8 single bit fields: global linkage (not set for C extern linkage, | |
12066 | apparently a PL/I convention?), out-of-line epilogue/prologue, offset | |
12067 | from start of procedure stored in tbtab, internal function, function | |
12068 | has controlled storage, function has no toc, function uses fp, | |
12069 | function logs/aborts fp operations. */ | |
12070 | /* Assume that fp operations are used if any fp reg must be saved. */ | |
6041bf2f DE |
12071 | fprintf (file, "%d,", |
12072 | (optional_tbtab << 5) | ((info->first_fp_reg_save != 64) << 1)); | |
314fc5a9 ILT |
12073 | |
12074 | /* 6 bitfields: function is interrupt handler, name present in | |
12075 | proc table, function calls alloca, on condition directives | |
12076 | (controls stack walks, 3 bits), saves condition reg, saves | |
12077 | link reg. */ | |
12078 | /* The `function calls alloca' bit seems to be set whenever reg 31 is | |
12079 | set up as a frame pointer, even when there is no alloca call. */ | |
12080 | fprintf (file, "%d,", | |
6041bf2f DE |
12081 | ((optional_tbtab << 6) |
12082 | | ((optional_tbtab & frame_pointer_needed) << 5) | |
12083 | | (info->cr_save_p << 1) | |
12084 | | (info->lr_save_p))); | |
314fc5a9 | 12085 | |
6041bf2f | 12086 | /* 3 bitfields: saves backchain, fixup code, number of fpr saved |
314fc5a9 ILT |
12087 | (6 bits). */ |
12088 | fprintf (file, "%d,", | |
4697a36c | 12089 | (info->push_p << 7) | (64 - info->first_fp_reg_save)); |
314fc5a9 ILT |
12090 | |
12091 | /* 2 bitfields: spare bits (2 bits), number of gpr saved (6 bits). */ | |
12092 | fprintf (file, "%d,", (32 - first_reg_to_save ())); | |
12093 | ||
6041bf2f DE |
12094 | if (optional_tbtab) |
12095 | { | |
12096 | /* Compute the parameter info from the function decl argument | |
12097 | list. */ | |
12098 | tree decl; | |
12099 | int next_parm_info_bit = 31; | |
314fc5a9 | 12100 | |
6041bf2f DE |
12101 | for (decl = DECL_ARGUMENTS (current_function_decl); |
12102 | decl; decl = TREE_CHAIN (decl)) | |
12103 | { | |
12104 | rtx parameter = DECL_INCOMING_RTL (decl); | |
12105 | enum machine_mode mode = GET_MODE (parameter); | |
314fc5a9 | 12106 | |
6041bf2f DE |
12107 | if (GET_CODE (parameter) == REG) |
12108 | { | |
12109 | if (GET_MODE_CLASS (mode) == MODE_FLOAT) | |
12110 | { | |
12111 | int bits; | |
12112 | ||
12113 | float_parms++; | |
12114 | ||
12115 | if (mode == SFmode) | |
12116 | bits = 0x2; | |
fcce224d | 12117 | else if (mode == DFmode || mode == TFmode) |
6041bf2f DE |
12118 | bits = 0x3; |
12119 | else | |
12120 | abort (); | |
12121 | ||
12122 | /* If only one bit will fit, don't or in this entry. */ | |
12123 | if (next_parm_info_bit > 0) | |
12124 | parm_info |= (bits << (next_parm_info_bit - 1)); | |
12125 | next_parm_info_bit -= 2; | |
12126 | } | |
12127 | else | |
12128 | { | |
12129 | fixed_parms += ((GET_MODE_SIZE (mode) | |
12130 | + (UNITS_PER_WORD - 1)) | |
12131 | / UNITS_PER_WORD); | |
12132 | next_parm_info_bit -= 1; | |
12133 | } | |
12134 | } | |
12135 | } | |
12136 | } | |
314fc5a9 ILT |
12137 | |
12138 | /* Number of fixed point parameters. */ | |
12139 | /* This is actually the number of words of fixed point parameters; thus | |
12140 | an 8 byte struct counts as 2; and thus the maximum value is 8. */ | |
12141 | fprintf (file, "%d,", fixed_parms); | |
12142 | ||
12143 | /* 2 bitfields: number of floating point parameters (7 bits), parameters | |
12144 | all on stack. */ | |
12145 | /* This is actually the number of fp registers that hold parameters; | |
12146 | and thus the maximum value is 13. */ | |
12147 | /* Set parameters on stack bit if parameters are not in their original | |
12148 | registers, regardless of whether they are on the stack? Xlc | |
12149 | seems to set the bit when not optimizing. */ | |
12150 | fprintf (file, "%d\n", ((float_parms << 1) | (! optimize))); | |
12151 | ||
6041bf2f DE |
12152 | if (! optional_tbtab) |
12153 | return; | |
12154 | ||
314fc5a9 ILT |
12155 | /* Optional fields follow. Some are variable length. */ |
12156 | ||
12157 | /* Parameter types, left adjusted bit fields: 0 fixed, 10 single float, | |
12158 | 11 double float. */ | |
12159 | /* There is an entry for each parameter in a register, in the order that | |
12160 | they occur in the parameter list. Any intervening arguments on the | |
12161 | stack are ignored. If the list overflows a long (max possible length | |
12162 | 34 bits) then completely leave off all elements that don't fit. */ | |
12163 | /* Only emit this long if there was at least one parameter. */ | |
12164 | if (fixed_parms || float_parms) | |
12165 | fprintf (file, "\t.long %d\n", parm_info); | |
12166 | ||
12167 | /* Offset from start of code to tb table. */ | |
19d2d16f | 12168 | fputs ("\t.long ", file); |
314fc5a9 | 12169 | ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT"); |
54ee9799 DE |
12170 | #if TARGET_AIX |
12171 | RS6000_OUTPUT_BASENAME (file, fname); | |
12172 | #else | |
9ebbca7d | 12173 | assemble_name (file, fname); |
54ee9799 | 12174 | #endif |
19d2d16f | 12175 | fputs ("-.", file); |
54ee9799 DE |
12176 | #if TARGET_AIX |
12177 | RS6000_OUTPUT_BASENAME (file, fname); | |
12178 | #else | |
9ebbca7d | 12179 | assemble_name (file, fname); |
54ee9799 | 12180 | #endif |
19d2d16f | 12181 | putc ('\n', file); |
314fc5a9 ILT |
12182 | |
12183 | /* Interrupt handler mask. */ | |
12184 | /* Omit this long, since we never set the interrupt handler bit | |
12185 | above. */ | |
12186 | ||
12187 | /* Number of CTL (controlled storage) anchors. */ | |
12188 | /* Omit this long, since the has_ctl bit is never set above. */ | |
12189 | ||
12190 | /* Displacement into stack of each CTL anchor. */ | |
12191 | /* Omit this list of longs, because there are no CTL anchors. */ | |
12192 | ||
12193 | /* Length of function name. */ | |
69c75916 AM |
12194 | if (*fname == '*') |
12195 | ++fname; | |
296b8152 | 12196 | fprintf (file, "\t.short %d\n", (int) strlen (fname)); |
314fc5a9 ILT |
12197 | |
12198 | /* Function name. */ | |
12199 | assemble_string (fname, strlen (fname)); | |
12200 | ||
12201 | /* Register for alloca automatic storage; this is always reg 31. | |
12202 | Only emit this if the alloca bit was set above. */ | |
12203 | if (frame_pointer_needed) | |
19d2d16f | 12204 | fputs ("\t.byte 31\n", file); |
b1765bde DE |
12205 | |
12206 | fputs ("\t.align 2\n", file); | |
9b30bae2 | 12207 | } |
9878760c | 12208 | } |
17167fd8 | 12209 | \f |
a4f6c312 SS |
12210 | /* A C compound statement that outputs the assembler code for a thunk |
12211 | function, used to implement C++ virtual function calls with | |
12212 | multiple inheritance. The thunk acts as a wrapper around a virtual | |
12213 | function, adjusting the implicit object parameter before handing | |
12214 | control off to the real function. | |
12215 | ||
12216 | First, emit code to add the integer DELTA to the location that | |
12217 | contains the incoming first argument. Assume that this argument | |
12218 | contains a pointer, and is the one used to pass the `this' pointer | |
12219 | in C++. This is the incoming argument *before* the function | |
12220 | prologue, e.g. `%o0' on a sparc. The addition must preserve the | |
12221 | values of all other incoming arguments. | |
17167fd8 MM |
12222 | |
12223 | After the addition, emit code to jump to FUNCTION, which is a | |
a4f6c312 SS |
12224 | `FUNCTION_DECL'. This is a direct pure jump, not a call, and does |
12225 | not touch the return address. Hence returning from FUNCTION will | |
12226 | return to whoever called the current `thunk'. | |
17167fd8 | 12227 | |
a4f6c312 SS |
12228 | The effect must be as if FUNCTION had been called directly with the |
12229 | adjusted first argument. This macro is responsible for emitting | |
12230 | all of the code for a thunk function; output_function_prologue() | |
12231 | and output_function_epilogue() are not invoked. | |
17167fd8 | 12232 | |
a4f6c312 SS |
12233 | The THUNK_FNDECL is redundant. (DELTA and FUNCTION have already |
12234 | been extracted from it.) It might possibly be useful on some | |
12235 | targets, but probably not. | |
17167fd8 | 12236 | |
a4f6c312 SS |
12237 | If you do not define this macro, the target-independent code in the |
12238 | C++ frontend will generate a less efficient heavyweight thunk that | |
12239 | calls FUNCTION instead of jumping to it. The generic approach does | |
12240 | not support varargs. */ | |
17167fd8 | 12241 | |
3961e8fe RH |
12242 | static void |
12243 | rs6000_output_mi_thunk (file, thunk_fndecl, delta, vcall_offset, function) | |
17167fd8 | 12244 | FILE *file; |
d330fd93 | 12245 | tree thunk_fndecl ATTRIBUTE_UNUSED; |
eb0424da | 12246 | HOST_WIDE_INT delta; |
5b71a4e7 | 12247 | HOST_WIDE_INT vcall_offset; |
17167fd8 MM |
12248 | tree function; |
12249 | { | |
5b71a4e7 | 12250 | rtx this, insn, funexp; |
17167fd8 | 12251 | |
5b71a4e7 | 12252 | reload_completed = 1; |
fe3ad572 | 12253 | epilogue_completed = 1; |
5b71a4e7 | 12254 | no_new_pseudos = 1; |
56a7189a | 12255 | |
5b71a4e7 DE |
12256 | /* Mark the end of the (empty) prologue. */ |
12257 | emit_note (NULL, NOTE_INSN_PROLOGUE_END); | |
17167fd8 | 12258 | |
5b71a4e7 DE |
12259 | /* Find the "this" pointer. If the function returns a structure, |
12260 | the structure return pointer is in r3. */ | |
12261 | if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)))) | |
12262 | this = gen_rtx_REG (Pmode, 4); | |
56a7189a | 12263 | else |
5b71a4e7 | 12264 | this = gen_rtx_REG (Pmode, 3); |
17167fd8 | 12265 | |
5b71a4e7 DE |
12266 | /* Apply the constant offset, if required. */ |
12267 | if (delta) | |
12268 | { | |
12269 | rtx delta_rtx = GEN_INT (delta); | |
12270 | emit_insn (TARGET_32BIT | |
12271 | ? gen_addsi3 (this, this, delta_rtx) | |
12272 | : gen_adddi3 (this, this, delta_rtx)); | |
17167fd8 MM |
12273 | } |
12274 | ||
5b71a4e7 DE |
12275 | /* Apply the offset from the vtable, if required. */ |
12276 | if (vcall_offset) | |
17167fd8 | 12277 | { |
5b71a4e7 DE |
12278 | rtx vcall_offset_rtx = GEN_INT (vcall_offset); |
12279 | rtx tmp = gen_rtx_REG (Pmode, 12); | |
17167fd8 | 12280 | |
5b71a4e7 DE |
12281 | emit_move_insn (tmp, gen_rtx_MEM (Pmode, this)); |
12282 | emit_insn (TARGET_32BIT | |
12283 | ? gen_addsi3 (tmp, tmp, vcall_offset_rtx) | |
12284 | : gen_adddi3 (tmp, tmp, vcall_offset_rtx)); | |
12285 | emit_move_insn (tmp, gen_rtx_MEM (Pmode, tmp)); | |
12286 | emit_insn (TARGET_32BIT | |
12287 | ? gen_addsi3 (this, this, tmp) | |
12288 | : gen_adddi3 (this, this, tmp)); | |
17167fd8 MM |
12289 | } |
12290 | ||
5b71a4e7 DE |
12291 | /* Generate a tail call to the target function. */ |
12292 | if (!TREE_USED (function)) | |
12293 | { | |
12294 | assemble_external (function); | |
12295 | TREE_USED (function) = 1; | |
12296 | } | |
12297 | funexp = XEXP (DECL_RTL (function), 0); | |
d1908feb | 12298 | SYMBOL_REF_FLAGS (funexp) &= ~SYMBOL_FLAG_LOCAL; |
5b71a4e7 | 12299 | funexp = gen_rtx_MEM (FUNCTION_MODE, funexp); |
ee890fe2 SS |
12300 | |
12301 | #if TARGET_MACHO | |
ab82a49f | 12302 | if (MACHOPIC_INDIRECT) |
5b71a4e7 | 12303 | funexp = machopic_indirect_call_target (funexp); |
ee890fe2 | 12304 | #endif |
5b71a4e7 DE |
12305 | |
12306 | /* gen_sibcall expects reload to convert scratch pseudo to LR so we must | |
12307 | generate sibcall RTL explicitly to avoid constraint abort. */ | |
12308 | insn = emit_call_insn ( | |
12309 | gen_rtx_PARALLEL (VOIDmode, | |
12310 | gen_rtvec (4, | |
12311 | gen_rtx_CALL (VOIDmode, | |
12312 | funexp, const0_rtx), | |
12313 | gen_rtx_USE (VOIDmode, const0_rtx), | |
12314 | gen_rtx_USE (VOIDmode, | |
12315 | gen_rtx_REG (SImode, | |
12316 | LINK_REGISTER_REGNUM)), | |
12317 | gen_rtx_RETURN (VOIDmode)))); | |
12318 | SIBLING_CALL_P (insn) = 1; | |
12319 | emit_barrier (); | |
12320 | ||
12321 | /* Run just enough of rest_of_compilation to get the insns emitted. | |
12322 | There's not really enough bulk here to make other passes such as | |
12323 | instruction scheduling worth while. Note that use_thunk calls | |
12324 | assemble_start_function and assemble_end_function. */ | |
12325 | insn = get_insns (); | |
a2855205 | 12326 | insn_locators_initialize (); |
5b71a4e7 DE |
12327 | shorten_branches (insn); |
12328 | final_start_function (insn, file, 1); | |
12329 | final (insn, file, 1, 0); | |
12330 | final_end_function (); | |
12331 | ||
12332 | reload_completed = 0; | |
fe3ad572 | 12333 | epilogue_completed = 0; |
5b71a4e7 | 12334 | no_new_pseudos = 0; |
9ebbca7d | 12335 | } |
9ebbca7d GK |
12336 | \f |
12337 | /* A quick summary of the various types of 'constant-pool tables' | |
12338 | under PowerPC: | |
12339 | ||
12340 | Target Flags Name One table per | |
12341 | AIX (none) AIX TOC object file | |
12342 | AIX -mfull-toc AIX TOC object file | |
12343 | AIX -mminimal-toc AIX minimal TOC translation unit | |
12344 | SVR4/EABI (none) SVR4 SDATA object file | |
12345 | SVR4/EABI -fpic SVR4 pic object file | |
12346 | SVR4/EABI -fPIC SVR4 PIC translation unit | |
12347 | SVR4/EABI -mrelocatable EABI TOC function | |
12348 | SVR4/EABI -maix AIX TOC object file | |
12349 | SVR4/EABI -maix -mminimal-toc | |
12350 | AIX minimal TOC translation unit | |
12351 | ||
12352 | Name Reg. Set by entries contains: | |
12353 | made by addrs? fp? sum? | |
12354 | ||
12355 | AIX TOC 2 crt0 as Y option option | |
12356 | AIX minimal TOC 30 prolog gcc Y Y option | |
12357 | SVR4 SDATA 13 crt0 gcc N Y N | |
12358 | SVR4 pic 30 prolog ld Y not yet N | |
12359 | SVR4 PIC 30 prolog gcc Y option option | |
12360 | EABI TOC 30 prolog gcc Y option option | |
12361 | ||
12362 | */ | |
12363 | ||
9ebbca7d GK |
12364 | /* Hash functions for the hash table. */ |
12365 | ||
12366 | static unsigned | |
12367 | rs6000_hash_constant (k) | |
12368 | rtx k; | |
12369 | { | |
46b33600 RH |
12370 | enum rtx_code code = GET_CODE (k); |
12371 | enum machine_mode mode = GET_MODE (k); | |
12372 | unsigned result = (code << 3) ^ mode; | |
12373 | const char *format; | |
12374 | int flen, fidx; | |
9ebbca7d | 12375 | |
46b33600 RH |
12376 | format = GET_RTX_FORMAT (code); |
12377 | flen = strlen (format); | |
12378 | fidx = 0; | |
9ebbca7d | 12379 | |
46b33600 RH |
12380 | switch (code) |
12381 | { | |
12382 | case LABEL_REF: | |
12383 | return result * 1231 + (unsigned) INSN_UID (XEXP (k, 0)); | |
12384 | ||
12385 | case CONST_DOUBLE: | |
12386 | if (mode != VOIDmode) | |
12387 | return real_hash (CONST_DOUBLE_REAL_VALUE (k)) * result; | |
12388 | flen = 2; | |
12389 | break; | |
12390 | ||
12391 | case CODE_LABEL: | |
12392 | fidx = 3; | |
12393 | break; | |
12394 | ||
12395 | default: | |
12396 | break; | |
12397 | } | |
9ebbca7d GK |
12398 | |
12399 | for (; fidx < flen; fidx++) | |
12400 | switch (format[fidx]) | |
12401 | { | |
12402 | case 's': | |
12403 | { | |
12404 | unsigned i, len; | |
12405 | const char *str = XSTR (k, fidx); | |
12406 | len = strlen (str); | |
12407 | result = result * 613 + len; | |
12408 | for (i = 0; i < len; i++) | |
12409 | result = result * 613 + (unsigned) str[i]; | |
17167fd8 MM |
12410 | break; |
12411 | } | |
9ebbca7d GK |
12412 | case 'u': |
12413 | case 'e': | |
12414 | result = result * 1231 + rs6000_hash_constant (XEXP (k, fidx)); | |
12415 | break; | |
12416 | case 'i': | |
12417 | case 'n': | |
12418 | result = result * 613 + (unsigned) XINT (k, fidx); | |
12419 | break; | |
12420 | case 'w': | |
12421 | if (sizeof (unsigned) >= sizeof (HOST_WIDE_INT)) | |
12422 | result = result * 613 + (unsigned) XWINT (k, fidx); | |
12423 | else | |
12424 | { | |
12425 | size_t i; | |
12426 | for (i = 0; i < sizeof(HOST_WIDE_INT)/sizeof(unsigned); i++) | |
12427 | result = result * 613 + (unsigned) (XWINT (k, fidx) | |
12428 | >> CHAR_BIT * i); | |
12429 | } | |
12430 | break; | |
09501938 DE |
12431 | case '0': |
12432 | break; | |
9ebbca7d | 12433 | default: |
a4f6c312 | 12434 | abort (); |
9ebbca7d | 12435 | } |
46b33600 | 12436 | |
9ebbca7d GK |
12437 | return result; |
12438 | } | |
12439 | ||
12440 | static unsigned | |
12441 | toc_hash_function (hash_entry) | |
12442 | const void * hash_entry; | |
12443 | { | |
a9098fd0 GK |
12444 | const struct toc_hash_struct *thc = |
12445 | (const struct toc_hash_struct *) hash_entry; | |
12446 | return rs6000_hash_constant (thc->key) ^ thc->key_mode; | |
9ebbca7d GK |
12447 | } |
12448 | ||
12449 | /* Compare H1 and H2 for equivalence. */ | |
12450 | ||
12451 | static int | |
12452 | toc_hash_eq (h1, h2) | |
12453 | const void * h1; | |
12454 | const void * h2; | |
12455 | { | |
12456 | rtx r1 = ((const struct toc_hash_struct *) h1)->key; | |
12457 | rtx r2 = ((const struct toc_hash_struct *) h2)->key; | |
12458 | ||
a9098fd0 GK |
12459 | if (((const struct toc_hash_struct *) h1)->key_mode |
12460 | != ((const struct toc_hash_struct *) h2)->key_mode) | |
12461 | return 0; | |
12462 | ||
5692c7bc | 12463 | return rtx_equal_p (r1, r2); |
9ebbca7d GK |
12464 | } |
12465 | ||
28e510bd MM |
12466 | /* These are the names given by the C++ front-end to vtables, and |
12467 | vtable-like objects. Ideally, this logic should not be here; | |
12468 | instead, there should be some programmatic way of inquiring as | |
12469 | to whether or not an object is a vtable. */ | |
12470 | ||
12471 | #define VTABLE_NAME_P(NAME) \ | |
12472 | (strncmp ("_vt.", name, strlen("_vt.")) == 0 \ | |
12473 | || strncmp ("_ZTV", name, strlen ("_ZTV")) == 0 \ | |
12474 | || strncmp ("_ZTT", name, strlen ("_ZTT")) == 0 \ | |
12475 | || strncmp ("_ZTC", name, strlen ("_ZTC")) == 0) | |
12476 | ||
12477 | void | |
12478 | rs6000_output_symbol_ref (file, x) | |
12479 | FILE *file; | |
12480 | rtx x; | |
12481 | { | |
12482 | /* Currently C++ toc references to vtables can be emitted before it | |
12483 | is decided whether the vtable is public or private. If this is | |
12484 | the case, then the linker will eventually complain that there is | |
12485 | a reference to an unknown section. Thus, for vtables only, | |
12486 | we emit the TOC reference to reference the symbol and not the | |
12487 | section. */ | |
12488 | const char *name = XSTR (x, 0); | |
54ee9799 DE |
12489 | |
12490 | if (VTABLE_NAME_P (name)) | |
12491 | { | |
12492 | RS6000_OUTPUT_BASENAME (file, name); | |
12493 | } | |
12494 | else | |
12495 | assemble_name (file, name); | |
28e510bd MM |
12496 | } |
12497 | ||
a4f6c312 SS |
12498 | /* Output a TOC entry. We derive the entry name from what is being |
12499 | written. */ | |
9878760c RK |
12500 | |
12501 | void | |
a9098fd0 | 12502 | output_toc (file, x, labelno, mode) |
9878760c RK |
12503 | FILE *file; |
12504 | rtx x; | |
12505 | int labelno; | |
a9098fd0 | 12506 | enum machine_mode mode; |
9878760c RK |
12507 | { |
12508 | char buf[256]; | |
3cce094d | 12509 | const char *name = buf; |
ec940faa | 12510 | const char *real_name; |
9878760c RK |
12511 | rtx base = x; |
12512 | int offset = 0; | |
12513 | ||
4697a36c MM |
12514 | if (TARGET_NO_TOC) |
12515 | abort (); | |
12516 | ||
9ebbca7d GK |
12517 | /* When the linker won't eliminate them, don't output duplicate |
12518 | TOC entries (this happens on AIX if there is any kind of TOC, | |
17211ab5 GK |
12519 | and on SVR4 under -fPIC or -mrelocatable). Don't do this for |
12520 | CODE_LABELs. */ | |
12521 | if (TARGET_TOC && GET_CODE (x) != LABEL_REF) | |
9ebbca7d GK |
12522 | { |
12523 | struct toc_hash_struct *h; | |
12524 | void * * found; | |
12525 | ||
17211ab5 GK |
12526 | /* Create toc_hash_table. This can't be done at OVERRIDE_OPTIONS |
12527 | time because GGC is not initialised at that point. */ | |
12528 | if (toc_hash_table == NULL) | |
12529 | toc_hash_table = htab_create_ggc (1021, toc_hash_function, | |
12530 | toc_hash_eq, NULL); | |
12531 | ||
9ebbca7d GK |
12532 | h = ggc_alloc (sizeof (*h)); |
12533 | h->key = x; | |
a9098fd0 | 12534 | h->key_mode = mode; |
9ebbca7d GK |
12535 | h->labelno = labelno; |
12536 | ||
12537 | found = htab_find_slot (toc_hash_table, h, 1); | |
12538 | if (*found == NULL) | |
12539 | *found = h; | |
12540 | else /* This is indeed a duplicate. | |
12541 | Set this label equal to that label. */ | |
12542 | { | |
12543 | fputs ("\t.set ", file); | |
12544 | ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC"); | |
12545 | fprintf (file, "%d,", labelno); | |
12546 | ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC"); | |
12547 | fprintf (file, "%d\n", ((*(const struct toc_hash_struct **) | |
12548 | found)->labelno)); | |
12549 | return; | |
12550 | } | |
12551 | } | |
12552 | ||
12553 | /* If we're going to put a double constant in the TOC, make sure it's | |
12554 | aligned properly when strict alignment is on. */ | |
ff1720ed RK |
12555 | if (GET_CODE (x) == CONST_DOUBLE |
12556 | && STRICT_ALIGNMENT | |
a9098fd0 | 12557 | && GET_MODE_BITSIZE (mode) >= 64 |
ff1720ed RK |
12558 | && ! (TARGET_NO_FP_IN_TOC && ! TARGET_MINIMAL_TOC)) { |
12559 | ASM_OUTPUT_ALIGN (file, 3); | |
12560 | } | |
12561 | ||
4977bab6 | 12562 | (*targetm.asm_out.internal_label) (file, "LC", labelno); |
9878760c | 12563 | |
37c37a57 RK |
12564 | /* Handle FP constants specially. Note that if we have a minimal |
12565 | TOC, things we put here aren't actually in the TOC, so we can allow | |
12566 | FP constants. */ | |
fcce224d DE |
12567 | if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == TFmode) |
12568 | { | |
12569 | REAL_VALUE_TYPE rv; | |
12570 | long k[4]; | |
12571 | ||
12572 | REAL_VALUE_FROM_CONST_DOUBLE (rv, x); | |
12573 | REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv, k); | |
12574 | ||
12575 | if (TARGET_64BIT) | |
12576 | { | |
12577 | if (TARGET_MINIMAL_TOC) | |
12578 | fputs (DOUBLE_INT_ASM_OP, file); | |
12579 | else | |
12580 | fprintf (file, "\t.tc FT_%lx_%lx_%lx_%lx[TC],", | |
12581 | k[0] & 0xffffffff, k[1] & 0xffffffff, | |
12582 | k[2] & 0xffffffff, k[3] & 0xffffffff); | |
12583 | fprintf (file, "0x%lx%08lx,0x%lx%08lx\n", | |
12584 | k[0] & 0xffffffff, k[1] & 0xffffffff, | |
12585 | k[2] & 0xffffffff, k[3] & 0xffffffff); | |
12586 | return; | |
12587 | } | |
12588 | else | |
12589 | { | |
12590 | if (TARGET_MINIMAL_TOC) | |
12591 | fputs ("\t.long ", file); | |
12592 | else | |
12593 | fprintf (file, "\t.tc FT_%lx_%lx_%lx_%lx[TC],", | |
12594 | k[0] & 0xffffffff, k[1] & 0xffffffff, | |
12595 | k[2] & 0xffffffff, k[3] & 0xffffffff); | |
12596 | fprintf (file, "0x%lx,0x%lx,0x%lx,0x%lx\n", | |
12597 | k[0] & 0xffffffff, k[1] & 0xffffffff, | |
12598 | k[2] & 0xffffffff, k[3] & 0xffffffff); | |
12599 | return; | |
12600 | } | |
12601 | } | |
12602 | else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == DFmode) | |
9878760c | 12603 | { |
042259f2 DE |
12604 | REAL_VALUE_TYPE rv; |
12605 | long k[2]; | |
0adc764e | 12606 | |
042259f2 DE |
12607 | REAL_VALUE_FROM_CONST_DOUBLE (rv, x); |
12608 | REAL_VALUE_TO_TARGET_DOUBLE (rv, k); | |
31bfaa0b | 12609 | |
13ded975 DE |
12610 | if (TARGET_64BIT) |
12611 | { | |
12612 | if (TARGET_MINIMAL_TOC) | |
2bfcf297 | 12613 | fputs (DOUBLE_INT_ASM_OP, file); |
13ded975 | 12614 | else |
2f0552b6 AM |
12615 | fprintf (file, "\t.tc FD_%lx_%lx[TC],", |
12616 | k[0] & 0xffffffff, k[1] & 0xffffffff); | |
12617 | fprintf (file, "0x%lx%08lx\n", | |
12618 | k[0] & 0xffffffff, k[1] & 0xffffffff); | |
13ded975 DE |
12619 | return; |
12620 | } | |
1875cc88 | 12621 | else |
13ded975 DE |
12622 | { |
12623 | if (TARGET_MINIMAL_TOC) | |
2bfcf297 | 12624 | fputs ("\t.long ", file); |
13ded975 | 12625 | else |
2f0552b6 AM |
12626 | fprintf (file, "\t.tc FD_%lx_%lx[TC],", |
12627 | k[0] & 0xffffffff, k[1] & 0xffffffff); | |
12628 | fprintf (file, "0x%lx,0x%lx\n", | |
12629 | k[0] & 0xffffffff, k[1] & 0xffffffff); | |
13ded975 DE |
12630 | return; |
12631 | } | |
9878760c | 12632 | } |
a9098fd0 | 12633 | else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == SFmode) |
9878760c | 12634 | { |
042259f2 DE |
12635 | REAL_VALUE_TYPE rv; |
12636 | long l; | |
9878760c | 12637 | |
042259f2 DE |
12638 | REAL_VALUE_FROM_CONST_DOUBLE (rv, x); |
12639 | REAL_VALUE_TO_TARGET_SINGLE (rv, l); | |
12640 | ||
31bfaa0b DE |
12641 | if (TARGET_64BIT) |
12642 | { | |
12643 | if (TARGET_MINIMAL_TOC) | |
2bfcf297 | 12644 | fputs (DOUBLE_INT_ASM_OP, file); |
31bfaa0b | 12645 | else |
2f0552b6 AM |
12646 | fprintf (file, "\t.tc FS_%lx[TC],", l & 0xffffffff); |
12647 | fprintf (file, "0x%lx00000000\n", l & 0xffffffff); | |
31bfaa0b DE |
12648 | return; |
12649 | } | |
042259f2 | 12650 | else |
31bfaa0b DE |
12651 | { |
12652 | if (TARGET_MINIMAL_TOC) | |
2bfcf297 | 12653 | fputs ("\t.long ", file); |
31bfaa0b | 12654 | else |
2f0552b6 AM |
12655 | fprintf (file, "\t.tc FS_%lx[TC],", l & 0xffffffff); |
12656 | fprintf (file, "0x%lx\n", l & 0xffffffff); | |
31bfaa0b DE |
12657 | return; |
12658 | } | |
042259f2 | 12659 | } |
f176e826 | 12660 | else if (GET_MODE (x) == VOIDmode |
a9098fd0 | 12661 | && (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE)) |
042259f2 | 12662 | { |
e2c953b6 | 12663 | unsigned HOST_WIDE_INT low; |
042259f2 DE |
12664 | HOST_WIDE_INT high; |
12665 | ||
12666 | if (GET_CODE (x) == CONST_DOUBLE) | |
12667 | { | |
12668 | low = CONST_DOUBLE_LOW (x); | |
12669 | high = CONST_DOUBLE_HIGH (x); | |
12670 | } | |
12671 | else | |
12672 | #if HOST_BITS_PER_WIDE_INT == 32 | |
12673 | { | |
12674 | low = INTVAL (x); | |
0858c623 | 12675 | high = (low & 0x80000000) ? ~0 : 0; |
042259f2 DE |
12676 | } |
12677 | #else | |
12678 | { | |
0858c623 | 12679 | low = INTVAL (x) & 0xffffffff; |
042259f2 DE |
12680 | high = (HOST_WIDE_INT) INTVAL (x) >> 32; |
12681 | } | |
12682 | #endif | |
9878760c | 12683 | |
a9098fd0 GK |
12684 | /* TOC entries are always Pmode-sized, but since this |
12685 | is a bigendian machine then if we're putting smaller | |
12686 | integer constants in the TOC we have to pad them. | |
12687 | (This is still a win over putting the constants in | |
12688 | a separate constant pool, because then we'd have | |
02a4ec28 FS |
12689 | to have both a TOC entry _and_ the actual constant.) |
12690 | ||
12691 | For a 32-bit target, CONST_INT values are loaded and shifted | |
12692 | entirely within `low' and can be stored in one TOC entry. */ | |
12693 | ||
12694 | if (TARGET_64BIT && POINTER_SIZE < GET_MODE_BITSIZE (mode)) | |
a9098fd0 | 12695 | abort ();/* It would be easy to make this work, but it doesn't now. */ |
02a4ec28 FS |
12696 | |
12697 | if (POINTER_SIZE > GET_MODE_BITSIZE (mode)) | |
fb52d8de AM |
12698 | { |
12699 | #if HOST_BITS_PER_WIDE_INT == 32 | |
12700 | lshift_double (low, high, POINTER_SIZE - GET_MODE_BITSIZE (mode), | |
12701 | POINTER_SIZE, &low, &high, 0); | |
12702 | #else | |
12703 | low |= high << 32; | |
12704 | low <<= POINTER_SIZE - GET_MODE_BITSIZE (mode); | |
12705 | high = (HOST_WIDE_INT) low >> 32; | |
12706 | low &= 0xffffffff; | |
12707 | #endif | |
12708 | } | |
a9098fd0 | 12709 | |
13ded975 DE |
12710 | if (TARGET_64BIT) |
12711 | { | |
12712 | if (TARGET_MINIMAL_TOC) | |
2bfcf297 | 12713 | fputs (DOUBLE_INT_ASM_OP, file); |
13ded975 | 12714 | else |
2f0552b6 AM |
12715 | fprintf (file, "\t.tc ID_%lx_%lx[TC],", |
12716 | (long) high & 0xffffffff, (long) low & 0xffffffff); | |
12717 | fprintf (file, "0x%lx%08lx\n", | |
12718 | (long) high & 0xffffffff, (long) low & 0xffffffff); | |
13ded975 DE |
12719 | return; |
12720 | } | |
1875cc88 | 12721 | else |
13ded975 | 12722 | { |
02a4ec28 FS |
12723 | if (POINTER_SIZE < GET_MODE_BITSIZE (mode)) |
12724 | { | |
12725 | if (TARGET_MINIMAL_TOC) | |
2bfcf297 | 12726 | fputs ("\t.long ", file); |
02a4ec28 | 12727 | else |
2bfcf297 | 12728 | fprintf (file, "\t.tc ID_%lx_%lx[TC],", |
2f0552b6 AM |
12729 | (long) high & 0xffffffff, (long) low & 0xffffffff); |
12730 | fprintf (file, "0x%lx,0x%lx\n", | |
12731 | (long) high & 0xffffffff, (long) low & 0xffffffff); | |
02a4ec28 | 12732 | } |
13ded975 | 12733 | else |
02a4ec28 FS |
12734 | { |
12735 | if (TARGET_MINIMAL_TOC) | |
2bfcf297 | 12736 | fputs ("\t.long ", file); |
02a4ec28 | 12737 | else |
2f0552b6 AM |
12738 | fprintf (file, "\t.tc IS_%lx[TC],", (long) low & 0xffffffff); |
12739 | fprintf (file, "0x%lx\n", (long) low & 0xffffffff); | |
02a4ec28 | 12740 | } |
13ded975 DE |
12741 | return; |
12742 | } | |
9878760c RK |
12743 | } |
12744 | ||
12745 | if (GET_CODE (x) == CONST) | |
12746 | { | |
2bfcf297 DB |
12747 | if (GET_CODE (XEXP (x, 0)) != PLUS) |
12748 | abort (); | |
12749 | ||
9878760c RK |
12750 | base = XEXP (XEXP (x, 0), 0); |
12751 | offset = INTVAL (XEXP (XEXP (x, 0), 1)); | |
12752 | } | |
12753 | ||
12754 | if (GET_CODE (base) == SYMBOL_REF) | |
12755 | name = XSTR (base, 0); | |
12756 | else if (GET_CODE (base) == LABEL_REF) | |
12757 | ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (XEXP (base, 0))); | |
12758 | else if (GET_CODE (base) == CODE_LABEL) | |
12759 | ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (base)); | |
12760 | else | |
12761 | abort (); | |
12762 | ||
772c5265 | 12763 | real_name = (*targetm.strip_name_encoding) (name); |
1875cc88 | 12764 | if (TARGET_MINIMAL_TOC) |
2bfcf297 | 12765 | fputs (TARGET_32BIT ? "\t.long " : DOUBLE_INT_ASM_OP, file); |
1875cc88 JW |
12766 | else |
12767 | { | |
b6c9286a | 12768 | fprintf (file, "\t.tc %s", real_name); |
9878760c | 12769 | |
1875cc88 JW |
12770 | if (offset < 0) |
12771 | fprintf (file, ".N%d", - offset); | |
12772 | else if (offset) | |
12773 | fprintf (file, ".P%d", offset); | |
9878760c | 12774 | |
19d2d16f | 12775 | fputs ("[TC],", file); |
1875cc88 | 12776 | } |
581bc4de MM |
12777 | |
12778 | /* Currently C++ toc references to vtables can be emitted before it | |
12779 | is decided whether the vtable is public or private. If this is | |
12780 | the case, then the linker will eventually complain that there is | |
12781 | a TOC reference to an unknown section. Thus, for vtables only, | |
12782 | we emit the TOC reference to reference the symbol and not the | |
12783 | section. */ | |
28e510bd | 12784 | if (VTABLE_NAME_P (name)) |
581bc4de | 12785 | { |
54ee9799 | 12786 | RS6000_OUTPUT_BASENAME (file, name); |
581bc4de MM |
12787 | if (offset < 0) |
12788 | fprintf (file, "%d", offset); | |
12789 | else if (offset > 0) | |
12790 | fprintf (file, "+%d", offset); | |
12791 | } | |
12792 | else | |
12793 | output_addr_const (file, x); | |
19d2d16f | 12794 | putc ('\n', file); |
9878760c RK |
12795 | } |
12796 | \f | |
12797 | /* Output an assembler pseudo-op to write an ASCII string of N characters | |
12798 | starting at P to FILE. | |
12799 | ||
12800 | On the RS/6000, we have to do this using the .byte operation and | |
12801 | write out special characters outside the quoted string. | |
12802 | Also, the assembler is broken; very long strings are truncated, | |
a4f6c312 | 12803 | so we must artificially break them up early. */ |
9878760c RK |
12804 | |
12805 | void | |
12806 | output_ascii (file, p, n) | |
12807 | FILE *file; | |
d330fd93 | 12808 | const char *p; |
9878760c RK |
12809 | int n; |
12810 | { | |
12811 | char c; | |
12812 | int i, count_string; | |
d330fd93 KG |
12813 | const char *for_string = "\t.byte \""; |
12814 | const char *for_decimal = "\t.byte "; | |
12815 | const char *to_close = NULL; | |
9878760c RK |
12816 | |
12817 | count_string = 0; | |
12818 | for (i = 0; i < n; i++) | |
12819 | { | |
12820 | c = *p++; | |
12821 | if (c >= ' ' && c < 0177) | |
12822 | { | |
12823 | if (for_string) | |
12824 | fputs (for_string, file); | |
12825 | putc (c, file); | |
12826 | ||
12827 | /* Write two quotes to get one. */ | |
12828 | if (c == '"') | |
12829 | { | |
12830 | putc (c, file); | |
12831 | ++count_string; | |
12832 | } | |
12833 | ||
12834 | for_string = NULL; | |
12835 | for_decimal = "\"\n\t.byte "; | |
12836 | to_close = "\"\n"; | |
12837 | ++count_string; | |
12838 | ||
12839 | if (count_string >= 512) | |
12840 | { | |
12841 | fputs (to_close, file); | |
12842 | ||
12843 | for_string = "\t.byte \""; | |
12844 | for_decimal = "\t.byte "; | |
12845 | to_close = NULL; | |
12846 | count_string = 0; | |
12847 | } | |
12848 | } | |
12849 | else | |
12850 | { | |
12851 | if (for_decimal) | |
12852 | fputs (for_decimal, file); | |
12853 | fprintf (file, "%d", c); | |
12854 | ||
12855 | for_string = "\n\t.byte \""; | |
12856 | for_decimal = ", "; | |
12857 | to_close = "\n"; | |
12858 | count_string = 0; | |
12859 | } | |
12860 | } | |
12861 | ||
12862 | /* Now close the string if we have written one. Then end the line. */ | |
12863 | if (to_close) | |
9ebbca7d | 12864 | fputs (to_close, file); |
9878760c RK |
12865 | } |
12866 | \f | |
12867 | /* Generate a unique section name for FILENAME for a section type | |
12868 | represented by SECTION_DESC. Output goes into BUF. | |
12869 | ||
12870 | SECTION_DESC can be any string, as long as it is different for each | |
12871 | possible section type. | |
12872 | ||
12873 | We name the section in the same manner as xlc. The name begins with an | |
12874 | underscore followed by the filename (after stripping any leading directory | |
11e5fe42 RK |
12875 | names) with the last period replaced by the string SECTION_DESC. If |
12876 | FILENAME does not contain a period, SECTION_DESC is appended to the end of | |
12877 | the name. */ | |
9878760c RK |
12878 | |
12879 | void | |
12880 | rs6000_gen_section_name (buf, filename, section_desc) | |
12881 | char **buf; | |
9ebbca7d GK |
12882 | const char *filename; |
12883 | const char *section_desc; | |
9878760c | 12884 | { |
9ebbca7d | 12885 | const char *q, *after_last_slash, *last_period = 0; |
9878760c RK |
12886 | char *p; |
12887 | int len; | |
9878760c RK |
12888 | |
12889 | after_last_slash = filename; | |
12890 | for (q = filename; *q; q++) | |
11e5fe42 RK |
12891 | { |
12892 | if (*q == '/') | |
12893 | after_last_slash = q + 1; | |
12894 | else if (*q == '.') | |
12895 | last_period = q; | |
12896 | } | |
9878760c | 12897 | |
11e5fe42 | 12898 | len = strlen (after_last_slash) + strlen (section_desc) + 2; |
6d9f628e | 12899 | *buf = (char *) xmalloc (len); |
9878760c RK |
12900 | |
12901 | p = *buf; | |
12902 | *p++ = '_'; | |
12903 | ||
12904 | for (q = after_last_slash; *q; q++) | |
12905 | { | |
11e5fe42 | 12906 | if (q == last_period) |
9878760c RK |
12907 | { |
12908 | strcpy (p, section_desc); | |
12909 | p += strlen (section_desc); | |
e3981aab | 12910 | break; |
9878760c RK |
12911 | } |
12912 | ||
e9a780ec | 12913 | else if (ISALNUM (*q)) |
9878760c RK |
12914 | *p++ = *q; |
12915 | } | |
12916 | ||
11e5fe42 | 12917 | if (last_period == 0) |
9878760c RK |
12918 | strcpy (p, section_desc); |
12919 | else | |
12920 | *p = '\0'; | |
12921 | } | |
e165f3f0 | 12922 | \f |
a4f6c312 | 12923 | /* Emit profile function. */ |
411707f4 | 12924 | |
411707f4 CC |
12925 | void |
12926 | output_profile_hook (labelno) | |
57ac7be9 | 12927 | int labelno ATTRIBUTE_UNUSED; |
411707f4 | 12928 | { |
ffcfcb5f AM |
12929 | if (TARGET_PROFILE_KERNEL) |
12930 | return; | |
12931 | ||
8480e480 CC |
12932 | if (DEFAULT_ABI == ABI_AIX) |
12933 | { | |
9739c90c JJ |
12934 | #ifndef NO_PROFILE_COUNTERS |
12935 | # define NO_PROFILE_COUNTERS 0 | |
12936 | #endif | |
12937 | if (NO_PROFILE_COUNTERS) | |
12938 | emit_library_call (init_one_libfunc (RS6000_MCOUNT), 0, VOIDmode, 0); | |
12939 | else | |
12940 | { | |
12941 | char buf[30]; | |
12942 | const char *label_name; | |
12943 | rtx fun; | |
411707f4 | 12944 | |
9739c90c JJ |
12945 | ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno); |
12946 | label_name = (*targetm.strip_name_encoding) (ggc_strdup (buf)); | |
12947 | fun = gen_rtx_SYMBOL_REF (Pmode, label_name); | |
411707f4 | 12948 | |
9739c90c JJ |
12949 | emit_library_call (init_one_libfunc (RS6000_MCOUNT), 0, VOIDmode, 1, |
12950 | fun, Pmode); | |
12951 | } | |
8480e480 | 12952 | } |
ee890fe2 SS |
12953 | else if (DEFAULT_ABI == ABI_DARWIN) |
12954 | { | |
d5fa86ba | 12955 | const char *mcount_name = RS6000_MCOUNT; |
ee890fe2 SS |
12956 | int caller_addr_regno = LINK_REGISTER_REGNUM; |
12957 | ||
12958 | /* Be conservative and always set this, at least for now. */ | |
12959 | current_function_uses_pic_offset_table = 1; | |
12960 | ||
12961 | #if TARGET_MACHO | |
12962 | /* For PIC code, set up a stub and collect the caller's address | |
12963 | from r0, which is where the prologue puts it. */ | |
ab82a49f | 12964 | if (MACHOPIC_INDIRECT) |
ee890fe2 SS |
12965 | { |
12966 | mcount_name = machopic_stub_name (mcount_name); | |
12967 | if (current_function_uses_pic_offset_table) | |
12968 | caller_addr_regno = 0; | |
12969 | } | |
12970 | #endif | |
12971 | emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mcount_name), | |
12972 | 0, VOIDmode, 1, | |
12973 | gen_rtx_REG (Pmode, caller_addr_regno), Pmode); | |
12974 | } | |
411707f4 CC |
12975 | } |
12976 | ||
a4f6c312 | 12977 | /* Write function profiler code. */ |
e165f3f0 RK |
12978 | |
12979 | void | |
12980 | output_function_profiler (file, labelno) | |
12981 | FILE *file; | |
12982 | int labelno; | |
12983 | { | |
3daf36a4 | 12984 | char buf[100]; |
09eeeacb | 12985 | int save_lr = 8; |
e165f3f0 | 12986 | |
38c1f2d7 | 12987 | switch (DEFAULT_ABI) |
3daf36a4 | 12988 | { |
38c1f2d7 MM |
12989 | default: |
12990 | abort (); | |
12991 | ||
12992 | case ABI_V4: | |
09eeeacb | 12993 | save_lr = 4; |
09eeeacb AM |
12994 | if (!TARGET_32BIT) |
12995 | { | |
12996 | warning ("no profiling of 64-bit code for this ABI"); | |
12997 | return; | |
12998 | } | |
ffcfcb5f | 12999 | ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno); |
38c1f2d7 MM |
13000 | fprintf (file, "\tmflr %s\n", reg_names[0]); |
13001 | if (flag_pic == 1) | |
13002 | { | |
dfdfa60f | 13003 | fputs ("\tbl _GLOBAL_OFFSET_TABLE_@local-4\n", file); |
09eeeacb AM |
13004 | asm_fprintf (file, "\t{st|stw} %s,%d(%s)\n", |
13005 | reg_names[0], save_lr, reg_names[1]); | |
17167fd8 | 13006 | asm_fprintf (file, "\tmflr %s\n", reg_names[12]); |
dfdfa60f | 13007 | asm_fprintf (file, "\t{l|lwz} %s,", reg_names[0]); |
38c1f2d7 | 13008 | assemble_name (file, buf); |
17167fd8 | 13009 | asm_fprintf (file, "@got(%s)\n", reg_names[12]); |
38c1f2d7 | 13010 | } |
9ebbca7d | 13011 | else if (flag_pic > 1) |
38c1f2d7 | 13012 | { |
09eeeacb AM |
13013 | asm_fprintf (file, "\t{st|stw} %s,%d(%s)\n", |
13014 | reg_names[0], save_lr, reg_names[1]); | |
9ebbca7d GK |
13015 | /* Now, we need to get the address of the label. */ |
13016 | fputs ("\tbl 1f\n\t.long ", file); | |
034e84c4 | 13017 | assemble_name (file, buf); |
9ebbca7d GK |
13018 | fputs ("-.\n1:", file); |
13019 | asm_fprintf (file, "\tmflr %s\n", reg_names[11]); | |
13020 | asm_fprintf (file, "\t{l|lwz} %s,0(%s)\n", | |
13021 | reg_names[0], reg_names[11]); | |
13022 | asm_fprintf (file, "\t{cax|add} %s,%s,%s\n", | |
13023 | reg_names[0], reg_names[0], reg_names[11]); | |
38c1f2d7 | 13024 | } |
38c1f2d7 MM |
13025 | else |
13026 | { | |
17167fd8 | 13027 | asm_fprintf (file, "\t{liu|lis} %s,", reg_names[12]); |
38c1f2d7 | 13028 | assemble_name (file, buf); |
dfdfa60f | 13029 | fputs ("@ha\n", file); |
09eeeacb AM |
13030 | asm_fprintf (file, "\t{st|stw} %s,%d(%s)\n", |
13031 | reg_names[0], save_lr, reg_names[1]); | |
a260abc9 | 13032 | asm_fprintf (file, "\t{cal|la} %s,", reg_names[0]); |
38c1f2d7 | 13033 | assemble_name (file, buf); |
17167fd8 | 13034 | asm_fprintf (file, "@l(%s)\n", reg_names[12]); |
38c1f2d7 MM |
13035 | } |
13036 | ||
50d440bc NC |
13037 | /* ABI_V4 saves the static chain reg with ASM_OUTPUT_REG_PUSH. */ |
13038 | fprintf (file, "\tbl %s\n", RS6000_MCOUNT); | |
38c1f2d7 MM |
13039 | break; |
13040 | ||
13041 | case ABI_AIX: | |
ee890fe2 | 13042 | case ABI_DARWIN: |
ffcfcb5f AM |
13043 | if (!TARGET_PROFILE_KERNEL) |
13044 | { | |
13045 | /* Don't do anything, done in output_profile_hook (). */ | |
13046 | } | |
13047 | else | |
13048 | { | |
13049 | if (TARGET_32BIT) | |
13050 | abort (); | |
13051 | ||
13052 | asm_fprintf (file, "\tmflr %s\n", reg_names[0]); | |
13053 | asm_fprintf (file, "\tstd %s,16(%s)\n", reg_names[0], reg_names[1]); | |
13054 | ||
13055 | if (current_function_needs_context) | |
13056 | { | |
13057 | asm_fprintf (file, "\tstd %s,24(%s)\n", | |
13058 | reg_names[STATIC_CHAIN_REGNUM], reg_names[1]); | |
13059 | fprintf (file, "\tbl %s\n", RS6000_MCOUNT); | |
13060 | asm_fprintf (file, "\tld %s,24(%s)\n", | |
13061 | reg_names[STATIC_CHAIN_REGNUM], reg_names[1]); | |
13062 | } | |
13063 | else | |
13064 | fprintf (file, "\tbl %s\n", RS6000_MCOUNT); | |
13065 | } | |
38c1f2d7 MM |
13066 | break; |
13067 | } | |
e165f3f0 | 13068 | } |
a251ffd0 | 13069 | |
b54cf83a DE |
13070 | \f |
13071 | static int | |
13072 | rs6000_use_dfa_pipeline_interface () | |
13073 | { | |
13074 | return 1; | |
13075 | } | |
13076 | ||
b54cf83a DE |
13077 | /* Power4 load update and store update instructions are cracked into a |
13078 | load or store and an integer insn which are executed in the same cycle. | |
13079 | Branches have their own dispatch slot which does not count against the | |
13080 | GCC issue rate, but it changes the program flow so there are no other | |
13081 | instructions to issue in this cycle. */ | |
13082 | ||
13083 | static int | |
13084 | rs6000_variable_issue (stream, verbose, insn, more) | |
13085 | FILE *stream ATTRIBUTE_UNUSED; | |
13086 | int verbose ATTRIBUTE_UNUSED; | |
13087 | rtx insn; | |
13088 | int more; | |
13089 | { | |
13090 | if (GET_CODE (PATTERN (insn)) == USE | |
13091 | || GET_CODE (PATTERN (insn)) == CLOBBER) | |
13092 | return more; | |
13093 | ||
13094 | if (rs6000_cpu == PROCESSOR_POWER4) | |
13095 | { | |
13096 | enum attr_type type = get_attr_type (insn); | |
13097 | if (type == TYPE_LOAD_EXT_U || type == TYPE_LOAD_EXT_UX | |
9259f3b0 | 13098 | || type == TYPE_LOAD_UX || type == TYPE_STORE_UX) |
b54cf83a DE |
13099 | return 0; |
13100 | else if (type == TYPE_LOAD_U || type == TYPE_STORE_U | |
13101 | || type == TYPE_FPLOAD_U || type == TYPE_FPSTORE_U | |
9259f3b0 DE |
13102 | || type == TYPE_FPLOAD_UX || type == TYPE_FPSTORE_UX |
13103 | || type == TYPE_LOAD_EXT || type == TYPE_DELAYED_CR | |
13104 | || type == TYPE_COMPARE || type == TYPE_DELAYED_COMPARE | |
13105 | || type == TYPE_IMUL_COMPARE || type == TYPE_LMUL_COMPARE | |
8e8238f1 DE |
13106 | || type == TYPE_IDIV || type == TYPE_LDIV |
13107 | || type == TYPE_INSERT_WORD) | |
3317bab1 | 13108 | return more > 2 ? more - 2 : 0; |
b54cf83a | 13109 | } |
165b263e DE |
13110 | |
13111 | return more - 1; | |
b54cf83a DE |
13112 | } |
13113 | ||
a251ffd0 TG |
13114 | /* Adjust the cost of a scheduling dependency. Return the new cost of |
13115 | a dependency LINK or INSN on DEP_INSN. COST is the current cost. */ | |
13116 | ||
c237e94a | 13117 | static int |
a06faf84 | 13118 | rs6000_adjust_cost (insn, link, dep_insn, cost) |
a251ffd0 TG |
13119 | rtx insn; |
13120 | rtx link; | |
296b8152 | 13121 | rtx dep_insn ATTRIBUTE_UNUSED; |
a251ffd0 TG |
13122 | int cost; |
13123 | { | |
13124 | if (! recog_memoized (insn)) | |
13125 | return 0; | |
13126 | ||
13127 | if (REG_NOTE_KIND (link) != 0) | |
13128 | return 0; | |
13129 | ||
13130 | if (REG_NOTE_KIND (link) == 0) | |
13131 | { | |
ed947a96 DJ |
13132 | /* Data dependency; DEP_INSN writes a register that INSN reads |
13133 | some cycles later. */ | |
13134 | switch (get_attr_type (insn)) | |
13135 | { | |
13136 | case TYPE_JMPREG: | |
309323c2 | 13137 | /* Tell the first scheduling pass about the latency between |
ed947a96 DJ |
13138 | a mtctr and bctr (and mtlr and br/blr). The first |
13139 | scheduling pass will not know about this latency since | |
13140 | the mtctr instruction, which has the latency associated | |
13141 | to it, will be generated by reload. */ | |
309323c2 | 13142 | return TARGET_POWER ? 5 : 4; |
ed947a96 DJ |
13143 | case TYPE_BRANCH: |
13144 | /* Leave some extra cycles between a compare and its | |
13145 | dependent branch, to inhibit expensive mispredicts. */ | |
309323c2 DE |
13146 | if ((rs6000_cpu_attr == CPU_PPC603 |
13147 | || rs6000_cpu_attr == CPU_PPC604 | |
13148 | || rs6000_cpu_attr == CPU_PPC604E | |
13149 | || rs6000_cpu_attr == CPU_PPC620 | |
13150 | || rs6000_cpu_attr == CPU_PPC630 | |
13151 | || rs6000_cpu_attr == CPU_PPC750 | |
13152 | || rs6000_cpu_attr == CPU_PPC7400 | |
13153 | || rs6000_cpu_attr == CPU_PPC7450 | |
13154 | || rs6000_cpu_attr == CPU_POWER4) | |
ed947a96 DJ |
13155 | && recog_memoized (dep_insn) |
13156 | && (INSN_CODE (dep_insn) >= 0) | |
b54cf83a DE |
13157 | && (get_attr_type (dep_insn) == TYPE_CMP |
13158 | || get_attr_type (dep_insn) == TYPE_COMPARE | |
ed947a96 | 13159 | || get_attr_type (dep_insn) == TYPE_DELAYED_COMPARE |
9259f3b0 DE |
13160 | || get_attr_type (dep_insn) == TYPE_IMUL_COMPARE |
13161 | || get_attr_type (dep_insn) == TYPE_LMUL_COMPARE | |
ed947a96 | 13162 | || get_attr_type (dep_insn) == TYPE_FPCOMPARE |
b54cf83a DE |
13163 | || get_attr_type (dep_insn) == TYPE_CR_LOGICAL |
13164 | || get_attr_type (dep_insn) == TYPE_DELAYED_CR)) | |
ed947a96 DJ |
13165 | return cost + 2; |
13166 | default: | |
13167 | break; | |
13168 | } | |
a251ffd0 TG |
13169 | /* Fall out to return default cost. */ |
13170 | } | |
13171 | ||
13172 | return cost; | |
13173 | } | |
b6c9286a | 13174 | |
a4f6c312 SS |
13175 | /* A C statement (sans semicolon) to update the integer scheduling |
13176 | priority INSN_PRIORITY (INSN). Reduce the priority to execute the | |
13177 | INSN earlier, increase the priority to execute INSN later. Do not | |
13178 | define this macro if you do not need to adjust the scheduling | |
13179 | priorities of insns. */ | |
bef84347 | 13180 | |
c237e94a | 13181 | static int |
bef84347 | 13182 | rs6000_adjust_priority (insn, priority) |
d330fd93 | 13183 | rtx insn ATTRIBUTE_UNUSED; |
bef84347 VM |
13184 | int priority; |
13185 | { | |
a4f6c312 SS |
13186 | /* On machines (like the 750) which have asymmetric integer units, |
13187 | where one integer unit can do multiply and divides and the other | |
13188 | can't, reduce the priority of multiply/divide so it is scheduled | |
13189 | before other integer operations. */ | |
bef84347 VM |
13190 | |
13191 | #if 0 | |
2c3c49de | 13192 | if (! INSN_P (insn)) |
bef84347 VM |
13193 | return priority; |
13194 | ||
13195 | if (GET_CODE (PATTERN (insn)) == USE) | |
13196 | return priority; | |
13197 | ||
13198 | switch (rs6000_cpu_attr) { | |
13199 | case CPU_PPC750: | |
13200 | switch (get_attr_type (insn)) | |
13201 | { | |
13202 | default: | |
13203 | break; | |
13204 | ||
13205 | case TYPE_IMUL: | |
13206 | case TYPE_IDIV: | |
3cb999d8 DE |
13207 | fprintf (stderr, "priority was %#x (%d) before adjustment\n", |
13208 | priority, priority); | |
bef84347 VM |
13209 | if (priority >= 0 && priority < 0x01000000) |
13210 | priority >>= 3; | |
13211 | break; | |
13212 | } | |
13213 | } | |
13214 | #endif | |
13215 | ||
13216 | return priority; | |
13217 | } | |
13218 | ||
a4f6c312 SS |
13219 | /* Return how many instructions the machine can issue per cycle. */ |
13220 | ||
c237e94a ZW |
13221 | static int |
13222 | rs6000_issue_rate () | |
b6c9286a | 13223 | { |
3317bab1 DE |
13224 | /* Use issue rate of 1 for first scheduling pass to decrease degradation. */ |
13225 | if (!reload_completed) | |
13226 | return 1; | |
13227 | ||
b6c9286a | 13228 | switch (rs6000_cpu_attr) { |
3cb999d8 DE |
13229 | case CPU_RIOS1: /* ? */ |
13230 | case CPU_RS64A: | |
13231 | case CPU_PPC601: /* ? */ | |
ed947a96 | 13232 | case CPU_PPC7450: |
3cb999d8 | 13233 | return 3; |
b54cf83a | 13234 | case CPU_PPC440: |
b6c9286a | 13235 | case CPU_PPC603: |
bef84347 | 13236 | case CPU_PPC750: |
ed947a96 | 13237 | case CPU_PPC7400: |
be12c2b0 | 13238 | case CPU_PPC8540: |
bef84347 | 13239 | return 2; |
3cb999d8 | 13240 | case CPU_RIOS2: |
b6c9286a | 13241 | case CPU_PPC604: |
19684119 | 13242 | case CPU_PPC604E: |
b6c9286a | 13243 | case CPU_PPC620: |
3cb999d8 | 13244 | case CPU_PPC630: |
309323c2 | 13245 | case CPU_POWER4: |
b6c9286a MM |
13246 | return 4; |
13247 | default: | |
13248 | return 1; | |
13249 | } | |
13250 | } | |
13251 | ||
be12c2b0 VM |
13252 | /* Return how many instructions to look ahead for better insn |
13253 | scheduling. */ | |
13254 | ||
13255 | static int | |
13256 | rs6000_use_sched_lookahead () | |
13257 | { | |
13258 | if (rs6000_cpu_attr == CPU_PPC8540) | |
13259 | return 4; | |
13260 | return 0; | |
13261 | } | |
13262 | ||
b6c9286a | 13263 | \f |
b6c9286a MM |
13264 | /* Length in units of the trampoline for entering a nested function. */ |
13265 | ||
13266 | int | |
13267 | rs6000_trampoline_size () | |
13268 | { | |
13269 | int ret = 0; | |
13270 | ||
13271 | switch (DEFAULT_ABI) | |
13272 | { | |
13273 | default: | |
13274 | abort (); | |
13275 | ||
13276 | case ABI_AIX: | |
8f802bfb | 13277 | ret = (TARGET_32BIT) ? 12 : 24; |
b6c9286a MM |
13278 | break; |
13279 | ||
4dabc42d | 13280 | case ABI_DARWIN: |
b6c9286a | 13281 | case ABI_V4: |
03a7e1a5 | 13282 | ret = (TARGET_32BIT) ? 40 : 48; |
b6c9286a | 13283 | break; |
b6c9286a MM |
13284 | } |
13285 | ||
13286 | return ret; | |
13287 | } | |
13288 | ||
13289 | /* Emit RTL insns to initialize the variable parts of a trampoline. | |
13290 | FNADDR is an RTX for the address of the function's pure code. | |
13291 | CXT is an RTX for the static chain value for the function. */ | |
13292 | ||
13293 | void | |
13294 | rs6000_initialize_trampoline (addr, fnaddr, cxt) | |
13295 | rtx addr; | |
13296 | rtx fnaddr; | |
13297 | rtx cxt; | |
13298 | { | |
ac2a93a1 | 13299 | enum machine_mode pmode = Pmode; |
8bd04c56 MM |
13300 | int regsize = (TARGET_32BIT) ? 4 : 8; |
13301 | rtx ctx_reg = force_reg (pmode, cxt); | |
b6c9286a MM |
13302 | |
13303 | switch (DEFAULT_ABI) | |
13304 | { | |
13305 | default: | |
13306 | abort (); | |
13307 | ||
8bd04c56 | 13308 | /* Macros to shorten the code expansions below. */ |
39403d82 | 13309 | #define MEM_DEREF(addr) gen_rtx_MEM (pmode, memory_address (pmode, addr)) |
c5c76735 JL |
13310 | #define MEM_PLUS(addr,offset) \ |
13311 | gen_rtx_MEM (pmode, memory_address (pmode, plus_constant (addr, offset))) | |
7c59dc5d | 13312 | |
b6c9286a MM |
13313 | /* Under AIX, just build the 3 word function descriptor */ |
13314 | case ABI_AIX: | |
8bd04c56 MM |
13315 | { |
13316 | rtx fn_reg = gen_reg_rtx (pmode); | |
13317 | rtx toc_reg = gen_reg_rtx (pmode); | |
13318 | emit_move_insn (fn_reg, MEM_DEREF (fnaddr)); | |
1cb18e3c | 13319 | emit_move_insn (toc_reg, MEM_PLUS (fnaddr, regsize)); |
8bd04c56 MM |
13320 | emit_move_insn (MEM_DEREF (addr), fn_reg); |
13321 | emit_move_insn (MEM_PLUS (addr, regsize), toc_reg); | |
13322 | emit_move_insn (MEM_PLUS (addr, 2*regsize), ctx_reg); | |
13323 | } | |
b6c9286a MM |
13324 | break; |
13325 | ||
4dabc42d TC |
13326 | /* Under V.4/eabi/darwin, __trampoline_setup does the real work. */ |
13327 | case ABI_DARWIN: | |
b6c9286a | 13328 | case ABI_V4: |
39403d82 | 13329 | emit_library_call (gen_rtx_SYMBOL_REF (SImode, "__trampoline_setup"), |
eaf1bcf1 MM |
13330 | FALSE, VOIDmode, 4, |
13331 | addr, pmode, | |
13332 | GEN_INT (rs6000_trampoline_size ()), SImode, | |
13333 | fnaddr, pmode, | |
13334 | ctx_reg, pmode); | |
b6c9286a | 13335 | break; |
b6c9286a MM |
13336 | } |
13337 | ||
13338 | return; | |
13339 | } | |
7509c759 MM |
13340 | |
13341 | \f | |
91d231cb | 13342 | /* Table of valid machine attributes. */ |
a4f6c312 | 13343 | |
91d231cb | 13344 | const struct attribute_spec rs6000_attribute_table[] = |
7509c759 | 13345 | { |
91d231cb | 13346 | /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */ |
a5c76ee6 ZW |
13347 | { "longcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute }, |
13348 | { "shortcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute }, | |
13349 | { NULL, 0, 0, false, false, false, NULL } | |
91d231cb | 13350 | }; |
7509c759 | 13351 | |
a5c76ee6 ZW |
13352 | /* Handle a "longcall" or "shortcall" attribute; arguments as in |
13353 | struct attribute_spec.handler. */ | |
a4f6c312 | 13354 | |
91d231cb JM |
13355 | static tree |
13356 | rs6000_handle_longcall_attribute (node, name, args, flags, no_add_attrs) | |
13357 | tree *node; | |
13358 | tree name; | |
13359 | tree args ATTRIBUTE_UNUSED; | |
13360 | int flags ATTRIBUTE_UNUSED; | |
13361 | bool *no_add_attrs; | |
13362 | { | |
13363 | if (TREE_CODE (*node) != FUNCTION_TYPE | |
13364 | && TREE_CODE (*node) != FIELD_DECL | |
13365 | && TREE_CODE (*node) != TYPE_DECL) | |
13366 | { | |
13367 | warning ("`%s' attribute only applies to functions", | |
13368 | IDENTIFIER_POINTER (name)); | |
13369 | *no_add_attrs = true; | |
13370 | } | |
6a4cee5f | 13371 | |
91d231cb | 13372 | return NULL_TREE; |
7509c759 MM |
13373 | } |
13374 | ||
a5c76ee6 ZW |
13375 | /* Set longcall attributes on all functions declared when |
13376 | rs6000_default_long_calls is true. */ | |
13377 | static void | |
13378 | rs6000_set_default_type_attributes (type) | |
13379 | tree type; | |
13380 | { | |
13381 | if (rs6000_default_long_calls | |
13382 | && (TREE_CODE (type) == FUNCTION_TYPE | |
13383 | || TREE_CODE (type) == METHOD_TYPE)) | |
13384 | TYPE_ATTRIBUTES (type) = tree_cons (get_identifier ("longcall"), | |
13385 | NULL_TREE, | |
13386 | TYPE_ATTRIBUTES (type)); | |
13387 | } | |
13388 | ||
3cb999d8 DE |
13389 | /* Return a reference suitable for calling a function with the |
13390 | longcall attribute. */ | |
a4f6c312 | 13391 | |
6a4cee5f MM |
13392 | struct rtx_def * |
13393 | rs6000_longcall_ref (call_ref) | |
13394 | rtx call_ref; | |
13395 | { | |
d330fd93 | 13396 | const char *call_name; |
6a4cee5f MM |
13397 | tree node; |
13398 | ||
13399 | if (GET_CODE (call_ref) != SYMBOL_REF) | |
13400 | return call_ref; | |
13401 | ||
13402 | /* System V adds '.' to the internal name, so skip them. */ | |
13403 | call_name = XSTR (call_ref, 0); | |
13404 | if (*call_name == '.') | |
13405 | { | |
13406 | while (*call_name == '.') | |
13407 | call_name++; | |
13408 | ||
13409 | node = get_identifier (call_name); | |
39403d82 | 13410 | call_ref = gen_rtx_SYMBOL_REF (VOIDmode, IDENTIFIER_POINTER (node)); |
6a4cee5f MM |
13411 | } |
13412 | ||
13413 | return force_reg (Pmode, call_ref); | |
13414 | } | |
7509c759 | 13415 | \f |
b64a1b53 RH |
13416 | #ifdef USING_ELFOS_H |
13417 | ||
7509c759 MM |
13418 | /* A C statement or statements to switch to the appropriate section |
13419 | for output of RTX in mode MODE. You can assume that RTX is some | |
13420 | kind of constant in RTL. The argument MODE is redundant except in | |
13421 | the case of a `const_int' rtx. Select the section by calling | |
13422 | `text_section' or one of the alternatives for other sections. | |
13423 | ||
13424 | Do not define this macro if you put all constants in the read-only | |
13425 | data section. */ | |
13426 | ||
b64a1b53 RH |
13427 | static void |
13428 | rs6000_elf_select_rtx_section (mode, x, align) | |
a9098fd0 | 13429 | enum machine_mode mode; |
7509c759 | 13430 | rtx x; |
b64a1b53 | 13431 | unsigned HOST_WIDE_INT align; |
7509c759 | 13432 | { |
a9098fd0 | 13433 | if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode)) |
7509c759 | 13434 | toc_section (); |
7509c759 | 13435 | else |
b64a1b53 | 13436 | default_elf_select_rtx_section (mode, x, align); |
7509c759 MM |
13437 | } |
13438 | ||
13439 | /* A C statement or statements to switch to the appropriate | |
13440 | section for output of DECL. DECL is either a `VAR_DECL' node | |
13441 | or a constant of some sort. RELOC indicates whether forming | |
13442 | the initial value of DECL requires link-time relocations. */ | |
13443 | ||
ae46c4e0 RH |
13444 | static void |
13445 | rs6000_elf_select_section (decl, reloc, align) | |
7509c759 MM |
13446 | tree decl; |
13447 | int reloc; | |
0e5dbd9b | 13448 | unsigned HOST_WIDE_INT align; |
7509c759 | 13449 | { |
f1384257 AM |
13450 | /* Pretend that we're always building for a shared library when |
13451 | ABI_AIX, because otherwise we end up with dynamic relocations | |
13452 | in read-only sections. This happens for function pointers, | |
13453 | references to vtables in typeinfo, and probably other cases. */ | |
0e5dbd9b DE |
13454 | default_elf_select_section_1 (decl, reloc, align, |
13455 | flag_pic || DEFAULT_ABI == ABI_AIX); | |
63019373 GK |
13456 | } |
13457 | ||
13458 | /* A C statement to build up a unique section name, expressed as a | |
13459 | STRING_CST node, and assign it to DECL_SECTION_NAME (decl). | |
13460 | RELOC indicates whether the initial value of EXP requires | |
13461 | link-time relocations. If you do not define this macro, GCC will use | |
13462 | the symbol name prefixed by `.' as the section name. Note - this | |
f5143c46 | 13463 | macro can now be called for uninitialized data items as well as |
4912a07c | 13464 | initialized data and functions. */ |
63019373 | 13465 | |
ae46c4e0 RH |
13466 | static void |
13467 | rs6000_elf_unique_section (decl, reloc) | |
63019373 GK |
13468 | tree decl; |
13469 | int reloc; | |
13470 | { | |
f1384257 AM |
13471 | /* As above, pretend that we're always building for a shared library |
13472 | when ABI_AIX, to avoid dynamic relocations in read-only sections. */ | |
0e5dbd9b DE |
13473 | default_unique_section_1 (decl, reloc, |
13474 | flag_pic || DEFAULT_ABI == ABI_AIX); | |
7509c759 | 13475 | } |
d9407988 | 13476 | \f |
d1908feb JJ |
13477 | /* For a SYMBOL_REF, set generic flags and then perform some |
13478 | target-specific processing. | |
13479 | ||
d1908feb JJ |
13480 | When the AIX ABI is requested on a non-AIX system, replace the |
13481 | function name with the real name (with a leading .) rather than the | |
13482 | function descriptor name. This saves a lot of overriding code to | |
13483 | read the prefixes. */ | |
d9407988 | 13484 | |
fb49053f | 13485 | static void |
c6a2438a | 13486 | rs6000_elf_encode_section_info (decl, rtl, first) |
d9407988 | 13487 | tree decl; |
c6a2438a | 13488 | rtx rtl; |
b2003250 | 13489 | int first; |
d9407988 | 13490 | { |
d1908feb | 13491 | default_encode_section_info (decl, rtl, first); |
b2003250 | 13492 | |
d1908feb JJ |
13493 | if (first |
13494 | && TREE_CODE (decl) == FUNCTION_DECL | |
13495 | && !TARGET_AIX | |
13496 | && DEFAULT_ABI == ABI_AIX) | |
d9407988 | 13497 | { |
c6a2438a | 13498 | rtx sym_ref = XEXP (rtl, 0); |
d1908feb JJ |
13499 | size_t len = strlen (XSTR (sym_ref, 0)); |
13500 | char *str = alloca (len + 2); | |
13501 | str[0] = '.'; | |
13502 | memcpy (str + 1, XSTR (sym_ref, 0), len + 1); | |
13503 | XSTR (sym_ref, 0) = ggc_alloc_string (str, len + 1); | |
d9407988 | 13504 | } |
d9407988 MM |
13505 | } |
13506 | ||
0e5dbd9b DE |
13507 | static bool |
13508 | rs6000_elf_in_small_data_p (decl) | |
13509 | tree decl; | |
13510 | { | |
13511 | if (rs6000_sdata == SDATA_NONE) | |
13512 | return false; | |
13513 | ||
13514 | if (TREE_CODE (decl) == VAR_DECL && DECL_SECTION_NAME (decl)) | |
13515 | { | |
13516 | const char *section = TREE_STRING_POINTER (DECL_SECTION_NAME (decl)); | |
13517 | if (strcmp (section, ".sdata") == 0 | |
13518 | || strcmp (section, ".sdata2") == 0 | |
20bfcd69 GK |
13519 | || strcmp (section, ".sbss") == 0 |
13520 | || strcmp (section, ".sbss2") == 0 | |
13521 | || strcmp (section, ".PPC.EMB.sdata0") == 0 | |
13522 | || strcmp (section, ".PPC.EMB.sbss0") == 0) | |
0e5dbd9b DE |
13523 | return true; |
13524 | } | |
13525 | else | |
13526 | { | |
13527 | HOST_WIDE_INT size = int_size_in_bytes (TREE_TYPE (decl)); | |
13528 | ||
13529 | if (size > 0 | |
307b599c | 13530 | && (unsigned HOST_WIDE_INT) size <= g_switch_value |
20bfcd69 GK |
13531 | /* If it's not public, and we're not going to reference it there, |
13532 | there's no need to put it in the small data section. */ | |
0e5dbd9b DE |
13533 | && (rs6000_sdata != SDATA_DATA || TREE_PUBLIC (decl))) |
13534 | return true; | |
13535 | } | |
13536 | ||
13537 | return false; | |
13538 | } | |
13539 | ||
b91da81f | 13540 | #endif /* USING_ELFOS_H */ |
000034eb | 13541 | |
a6c2a102 | 13542 | \f |
000034eb | 13543 | /* Return a REG that occurs in ADDR with coefficient 1. |
02441cd6 JL |
13544 | ADDR can be effectively incremented by incrementing REG. |
13545 | ||
13546 | r0 is special and we must not select it as an address | |
13547 | register by this routine since our caller will try to | |
13548 | increment the returned register via an "la" instruction. */ | |
000034eb DE |
13549 | |
13550 | struct rtx_def * | |
13551 | find_addr_reg (addr) | |
13552 | rtx addr; | |
13553 | { | |
13554 | while (GET_CODE (addr) == PLUS) | |
13555 | { | |
02441cd6 JL |
13556 | if (GET_CODE (XEXP (addr, 0)) == REG |
13557 | && REGNO (XEXP (addr, 0)) != 0) | |
000034eb | 13558 | addr = XEXP (addr, 0); |
02441cd6 JL |
13559 | else if (GET_CODE (XEXP (addr, 1)) == REG |
13560 | && REGNO (XEXP (addr, 1)) != 0) | |
000034eb DE |
13561 | addr = XEXP (addr, 1); |
13562 | else if (CONSTANT_P (XEXP (addr, 0))) | |
13563 | addr = XEXP (addr, 1); | |
13564 | else if (CONSTANT_P (XEXP (addr, 1))) | |
13565 | addr = XEXP (addr, 0); | |
13566 | else | |
13567 | abort (); | |
13568 | } | |
02441cd6 | 13569 | if (GET_CODE (addr) == REG && REGNO (addr) != 0) |
000034eb DE |
13570 | return addr; |
13571 | abort (); | |
13572 | } | |
13573 | ||
a6c2a102 DE |
13574 | void |
13575 | rs6000_fatal_bad_address (op) | |
13576 | rtx op; | |
13577 | { | |
13578 | fatal_insn ("bad address", op); | |
13579 | } | |
c8023011 | 13580 | |
ee890fe2 SS |
13581 | #if TARGET_MACHO |
13582 | ||
13583 | #if 0 | |
13584 | /* Returns 1 if OP is either a symbol reference or a sum of a symbol | |
13585 | reference and a constant. */ | |
13586 | ||
13587 | int | |
13588 | symbolic_operand (op) | |
592696dd | 13589 | rtx op; |
ee890fe2 SS |
13590 | { |
13591 | switch (GET_CODE (op)) | |
13592 | { | |
13593 | case SYMBOL_REF: | |
13594 | case LABEL_REF: | |
13595 | return 1; | |
13596 | case CONST: | |
13597 | op = XEXP (op, 0); | |
13598 | return (GET_CODE (op) == SYMBOL_REF || | |
13599 | (GET_CODE (XEXP (op, 0)) == SYMBOL_REF | |
13600 | || GET_CODE (XEXP (op, 0)) == LABEL_REF) | |
13601 | && GET_CODE (XEXP (op, 1)) == CONST_INT); | |
13602 | default: | |
13603 | return 0; | |
13604 | } | |
c8023011 | 13605 | } |
ee890fe2 SS |
13606 | #endif |
13607 | ||
13608 | #ifdef RS6000_LONG_BRANCH | |
13609 | ||
13610 | static tree stub_list = 0; | |
13611 | ||
13612 | /* ADD_COMPILER_STUB adds the compiler generated stub for handling | |
13613 | procedure calls to the linked list. */ | |
13614 | ||
13615 | void | |
13616 | add_compiler_stub (label_name, function_name, line_number) | |
13617 | tree label_name; | |
13618 | tree function_name; | |
13619 | int line_number; | |
13620 | { | |
13621 | tree stub = build_tree_list (function_name, label_name); | |
13622 | TREE_TYPE (stub) = build_int_2 (line_number, 0); | |
13623 | TREE_CHAIN (stub) = stub_list; | |
13624 | stub_list = stub; | |
13625 | } | |
13626 | ||
13627 | #define STUB_LABEL_NAME(STUB) TREE_VALUE (STUB) | |
13628 | #define STUB_FUNCTION_NAME(STUB) TREE_PURPOSE (STUB) | |
13629 | #define STUB_LINE_NUMBER(STUB) TREE_INT_CST_LOW (TREE_TYPE (STUB)) | |
13630 | ||
a4f6c312 SS |
13631 | /* OUTPUT_COMPILER_STUB outputs the compiler generated stub for |
13632 | handling procedure calls from the linked list and initializes the | |
13633 | linked list. */ | |
ee890fe2 | 13634 | |
a4f6c312 SS |
13635 | void |
13636 | output_compiler_stub () | |
ee890fe2 SS |
13637 | { |
13638 | char tmp_buf[256]; | |
13639 | char label_buf[256]; | |
308c142a | 13640 | tree stub; |
ee890fe2 SS |
13641 | |
13642 | if (!flag_pic) | |
13643 | for (stub = stub_list; stub; stub = TREE_CHAIN (stub)) | |
13644 | { | |
13645 | fprintf (asm_out_file, | |
13646 | "%s:\n", IDENTIFIER_POINTER(STUB_LABEL_NAME(stub))); | |
13647 | ||
13648 | #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO) | |
13649 | if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG) | |
13650 | fprintf (asm_out_file, "\t.stabd 68,0,%d\n", STUB_LINE_NUMBER(stub)); | |
13651 | #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */ | |
13652 | ||
13653 | if (IDENTIFIER_POINTER (STUB_FUNCTION_NAME (stub))[0] == '*') | |
13654 | strcpy (label_buf, | |
13655 | IDENTIFIER_POINTER (STUB_FUNCTION_NAME (stub))+1); | |
13656 | else | |
13657 | { | |
13658 | label_buf[0] = '_'; | |
13659 | strcpy (label_buf+1, | |
13660 | IDENTIFIER_POINTER (STUB_FUNCTION_NAME (stub))); | |
13661 | } | |
13662 | ||
13663 | strcpy (tmp_buf, "lis r12,hi16("); | |
13664 | strcat (tmp_buf, label_buf); | |
13665 | strcat (tmp_buf, ")\n\tori r12,r12,lo16("); | |
13666 | strcat (tmp_buf, label_buf); | |
13667 | strcat (tmp_buf, ")\n\tmtctr r12\n\tbctr"); | |
13668 | output_asm_insn (tmp_buf, 0); | |
13669 | ||
13670 | #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO) | |
13671 | if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG) | |
13672 | fprintf(asm_out_file, "\t.stabd 68,0,%d\n", STUB_LINE_NUMBER (stub)); | |
13673 | #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */ | |
13674 | } | |
13675 | ||
13676 | stub_list = 0; | |
13677 | } | |
13678 | ||
13679 | /* NO_PREVIOUS_DEF checks in the link list whether the function name is | |
13680 | already there or not. */ | |
13681 | ||
a4f6c312 SS |
13682 | int |
13683 | no_previous_def (function_name) | |
ee890fe2 SS |
13684 | tree function_name; |
13685 | { | |
13686 | tree stub; | |
13687 | for (stub = stub_list; stub; stub = TREE_CHAIN (stub)) | |
13688 | if (function_name == STUB_FUNCTION_NAME (stub)) | |
13689 | return 0; | |
13690 | return 1; | |
13691 | } | |
13692 | ||
13693 | /* GET_PREV_LABEL gets the label name from the previous definition of | |
13694 | the function. */ | |
13695 | ||
a4f6c312 SS |
13696 | tree |
13697 | get_prev_label (function_name) | |
ee890fe2 SS |
13698 | tree function_name; |
13699 | { | |
13700 | tree stub; | |
13701 | for (stub = stub_list; stub; stub = TREE_CHAIN (stub)) | |
13702 | if (function_name == STUB_FUNCTION_NAME (stub)) | |
13703 | return STUB_LABEL_NAME (stub); | |
13704 | return 0; | |
13705 | } | |
13706 | ||
13707 | /* INSN is either a function call or a millicode call. It may have an | |
13708 | unconditional jump in its delay slot. | |
13709 | ||
13710 | CALL_DEST is the routine we are calling. */ | |
13711 | ||
13712 | char * | |
13713 | output_call (insn, call_dest, operand_number) | |
13714 | rtx insn; | |
13715 | rtx call_dest; | |
13716 | int operand_number; | |
13717 | { | |
13718 | static char buf[256]; | |
13719 | if (GET_CODE (call_dest) == SYMBOL_REF && TARGET_LONG_BRANCH && !flag_pic) | |
13720 | { | |
13721 | tree labelname; | |
13722 | tree funname = get_identifier (XSTR (call_dest, 0)); | |
13723 | ||
13724 | if (no_previous_def (funname)) | |
13725 | { | |
308c142a | 13726 | int line_number = 0; |
ee890fe2 SS |
13727 | rtx label_rtx = gen_label_rtx (); |
13728 | char *label_buf, temp_buf[256]; | |
13729 | ASM_GENERATE_INTERNAL_LABEL (temp_buf, "L", | |
13730 | CODE_LABEL_NUMBER (label_rtx)); | |
13731 | label_buf = temp_buf[0] == '*' ? temp_buf + 1 : temp_buf; | |
13732 | labelname = get_identifier (label_buf); | |
13733 | for (; insn && GET_CODE (insn) != NOTE; insn = PREV_INSN (insn)); | |
13734 | if (insn) | |
13735 | line_number = NOTE_LINE_NUMBER (insn); | |
13736 | add_compiler_stub (labelname, funname, line_number); | |
13737 | } | |
13738 | else | |
13739 | labelname = get_prev_label (funname); | |
13740 | ||
13741 | sprintf (buf, "jbsr %%z%d,%.246s", | |
13742 | operand_number, IDENTIFIER_POINTER (labelname)); | |
13743 | return buf; | |
13744 | } | |
13745 | else | |
13746 | { | |
13747 | sprintf (buf, "bl %%z%d", operand_number); | |
13748 | return buf; | |
13749 | } | |
13750 | } | |
13751 | ||
13752 | #endif /* RS6000_LONG_BRANCH */ | |
13753 | ||
13754 | #define GEN_LOCAL_LABEL_FOR_SYMBOL(BUF,SYMBOL,LENGTH,N) \ | |
13755 | do { \ | |
83182544 | 13756 | const char *const symbol_ = (SYMBOL); \ |
ee890fe2 SS |
13757 | char *buffer_ = (BUF); \ |
13758 | if (symbol_[0] == '"') \ | |
13759 | { \ | |
13760 | sprintf(buffer_, "\"L%d$%s", (N), symbol_+1); \ | |
13761 | } \ | |
13762 | else if (name_needs_quotes(symbol_)) \ | |
13763 | { \ | |
13764 | sprintf(buffer_, "\"L%d$%s\"", (N), symbol_); \ | |
13765 | } \ | |
13766 | else \ | |
13767 | { \ | |
13768 | sprintf(buffer_, "L%d$%s", (N), symbol_); \ | |
13769 | } \ | |
13770 | } while (0) | |
13771 | ||
13772 | ||
13773 | /* Generate PIC and indirect symbol stubs. */ | |
13774 | ||
13775 | void | |
13776 | machopic_output_stub (file, symb, stub) | |
13777 | FILE *file; | |
13778 | const char *symb, *stub; | |
13779 | { | |
13780 | unsigned int length; | |
a4f6c312 SS |
13781 | char *symbol_name, *lazy_ptr_name; |
13782 | char *local_label_0; | |
ee890fe2 SS |
13783 | static int label = 0; |
13784 | ||
df56a27f | 13785 | /* Lose our funky encoding stuff so it doesn't contaminate the stub. */ |
772c5265 | 13786 | symb = (*targetm.strip_name_encoding) (symb); |
df56a27f | 13787 | |
ee890fe2 SS |
13788 | label += 1; |
13789 | ||
ee890fe2 SS |
13790 | length = strlen (symb); |
13791 | symbol_name = alloca (length + 32); | |
13792 | GEN_SYMBOL_NAME_FOR_SYMBOL (symbol_name, symb, length); | |
13793 | ||
13794 | lazy_ptr_name = alloca (length + 32); | |
13795 | GEN_LAZY_PTR_NAME_FOR_SYMBOL (lazy_ptr_name, symb, length); | |
13796 | ||
13797 | local_label_0 = alloca (length + 32); | |
13798 | GEN_LOCAL_LABEL_FOR_SYMBOL (local_label_0, symb, length, 0); | |
13799 | ||
ee890fe2 | 13800 | if (flag_pic == 2) |
d3c300d2 | 13801 | machopic_picsymbol_stub1_section (); |
ee890fe2 | 13802 | else |
d3c300d2 DJ |
13803 | machopic_symbol_stub1_section (); |
13804 | fprintf (file, "\t.align 2\n"); | |
ee890fe2 SS |
13805 | |
13806 | fprintf (file, "%s:\n", stub); | |
13807 | fprintf (file, "\t.indirect_symbol %s\n", symbol_name); | |
13808 | ||
13809 | if (flag_pic == 2) | |
13810 | { | |
13811 | fprintf (file, "\tmflr r0\n"); | |
13812 | fprintf (file, "\tbcl 20,31,%s\n", local_label_0); | |
13813 | fprintf (file, "%s:\n\tmflr r11\n", local_label_0); | |
13814 | fprintf (file, "\taddis r11,r11,ha16(%s-%s)\n", | |
13815 | lazy_ptr_name, local_label_0); | |
13816 | fprintf (file, "\tmtlr r0\n"); | |
d3c300d2 | 13817 | fprintf (file, "\tlwzu r12,lo16(%s-%s)(r11)\n", |
ee890fe2 SS |
13818 | lazy_ptr_name, local_label_0); |
13819 | fprintf (file, "\tmtctr r12\n"); | |
ee890fe2 SS |
13820 | fprintf (file, "\tbctr\n"); |
13821 | } | |
13822 | else | |
ab82a49f AP |
13823 | { |
13824 | fprintf (file, "\tlis r11,ha16(%s)\n", lazy_ptr_name); | |
13825 | fprintf (file, "\tlwzu r12,lo16(%s)(r11)\n", lazy_ptr_name); | |
13826 | fprintf (file, "\tmtctr r12\n"); | |
13827 | fprintf (file, "\tbctr\n"); | |
13828 | } | |
ee890fe2 SS |
13829 | |
13830 | machopic_lazy_symbol_ptr_section (); | |
13831 | fprintf (file, "%s:\n", lazy_ptr_name); | |
13832 | fprintf (file, "\t.indirect_symbol %s\n", symbol_name); | |
13833 | fprintf (file, "\t.long dyld_stub_binding_helper\n"); | |
13834 | } | |
13835 | ||
13836 | /* Legitimize PIC addresses. If the address is already | |
13837 | position-independent, we return ORIG. Newly generated | |
13838 | position-independent addresses go into a reg. This is REG if non | |
13839 | zero, otherwise we allocate register(s) as necessary. */ | |
13840 | ||
c859cda6 | 13841 | #define SMALL_INT(X) ((unsigned) (INTVAL(X) + 0x8000) < 0x10000) |
ee890fe2 SS |
13842 | |
13843 | rtx | |
13844 | rs6000_machopic_legitimize_pic_address (orig, mode, reg) | |
13845 | rtx orig; | |
13846 | enum machine_mode mode; | |
13847 | rtx reg; | |
13848 | { | |
13849 | rtx base, offset; | |
13850 | ||
13851 | if (reg == NULL && ! reload_in_progress && ! reload_completed) | |
13852 | reg = gen_reg_rtx (Pmode); | |
13853 | ||
13854 | if (GET_CODE (orig) == CONST) | |
13855 | { | |
13856 | if (GET_CODE (XEXP (orig, 0)) == PLUS | |
13857 | && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx) | |
13858 | return orig; | |
13859 | ||
13860 | if (GET_CODE (XEXP (orig, 0)) == PLUS) | |
13861 | { | |
a4f6c312 SS |
13862 | base = |
13863 | rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 0), | |
13864 | Pmode, reg); | |
13865 | offset = | |
13866 | rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 1), | |
13867 | Pmode, reg); | |
ee890fe2 SS |
13868 | } |
13869 | else | |
13870 | abort (); | |
13871 | ||
13872 | if (GET_CODE (offset) == CONST_INT) | |
13873 | { | |
13874 | if (SMALL_INT (offset)) | |
ed8908e7 | 13875 | return plus_constant (base, INTVAL (offset)); |
ee890fe2 SS |
13876 | else if (! reload_in_progress && ! reload_completed) |
13877 | offset = force_reg (Pmode, offset); | |
13878 | else | |
c859cda6 DJ |
13879 | { |
13880 | rtx mem = force_const_mem (Pmode, orig); | |
13881 | return machopic_legitimize_pic_address (mem, Pmode, reg); | |
13882 | } | |
ee890fe2 SS |
13883 | } |
13884 | return gen_rtx (PLUS, Pmode, base, offset); | |
13885 | } | |
13886 | ||
13887 | /* Fall back on generic machopic code. */ | |
13888 | return machopic_legitimize_pic_address (orig, mode, reg); | |
13889 | } | |
13890 | ||
13891 | /* This is just a placeholder to make linking work without having to | |
13892 | add this to the generic Darwin EXTRA_SECTIONS. If -mcall-aix is | |
13893 | ever needed for Darwin (not too likely!) this would have to get a | |
13894 | real definition. */ | |
13895 | ||
13896 | void | |
13897 | toc_section () | |
13898 | { | |
13899 | } | |
13900 | ||
13901 | #endif /* TARGET_MACHO */ | |
7c262518 RH |
13902 | |
13903 | #if TARGET_ELF | |
13904 | static unsigned int | |
13905 | rs6000_elf_section_type_flags (decl, name, reloc) | |
13906 | tree decl; | |
13907 | const char *name; | |
13908 | int reloc; | |
13909 | { | |
5add3202 DE |
13910 | unsigned int flags |
13911 | = default_section_type_flags_1 (decl, name, reloc, | |
13912 | flag_pic || DEFAULT_ABI == ABI_AIX); | |
7c262518 | 13913 | |
270fc29b RH |
13914 | if (TARGET_RELOCATABLE) |
13915 | flags |= SECTION_WRITE; | |
7c262518 | 13916 | |
d0101753 | 13917 | return flags; |
7c262518 | 13918 | } |
d9f6800d RH |
13919 | |
13920 | /* Record an element in the table of global constructors. SYMBOL is | |
13921 | a SYMBOL_REF of the function to be called; PRIORITY is a number | |
13922 | between 0 and MAX_INIT_PRIORITY. | |
13923 | ||
13924 | This differs from default_named_section_asm_out_constructor in | |
13925 | that we have special handling for -mrelocatable. */ | |
13926 | ||
13927 | static void | |
13928 | rs6000_elf_asm_out_constructor (symbol, priority) | |
13929 | rtx symbol; | |
13930 | int priority; | |
13931 | { | |
13932 | const char *section = ".ctors"; | |
13933 | char buf[16]; | |
13934 | ||
13935 | if (priority != DEFAULT_INIT_PRIORITY) | |
13936 | { | |
13937 | sprintf (buf, ".ctors.%.5u", | |
13938 | /* Invert the numbering so the linker puts us in the proper | |
13939 | order; constructors are run from right to left, and the | |
13940 | linker sorts in increasing order. */ | |
13941 | MAX_INIT_PRIORITY - priority); | |
13942 | section = buf; | |
13943 | } | |
13944 | ||
715bdd29 RH |
13945 | named_section_flags (section, SECTION_WRITE); |
13946 | assemble_align (POINTER_SIZE); | |
d9f6800d RH |
13947 | |
13948 | if (TARGET_RELOCATABLE) | |
13949 | { | |
13950 | fputs ("\t.long (", asm_out_file); | |
13951 | output_addr_const (asm_out_file, symbol); | |
13952 | fputs (")@fixup\n", asm_out_file); | |
13953 | } | |
13954 | else | |
c8af3574 | 13955 | assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1); |
d9f6800d RH |
13956 | } |
13957 | ||
13958 | static void | |
13959 | rs6000_elf_asm_out_destructor (symbol, priority) | |
13960 | rtx symbol; | |
13961 | int priority; | |
13962 | { | |
13963 | const char *section = ".dtors"; | |
13964 | char buf[16]; | |
13965 | ||
13966 | if (priority != DEFAULT_INIT_PRIORITY) | |
13967 | { | |
13968 | sprintf (buf, ".dtors.%.5u", | |
13969 | /* Invert the numbering so the linker puts us in the proper | |
13970 | order; constructors are run from right to left, and the | |
13971 | linker sorts in increasing order. */ | |
13972 | MAX_INIT_PRIORITY - priority); | |
13973 | section = buf; | |
13974 | } | |
13975 | ||
715bdd29 RH |
13976 | named_section_flags (section, SECTION_WRITE); |
13977 | assemble_align (POINTER_SIZE); | |
d9f6800d RH |
13978 | |
13979 | if (TARGET_RELOCATABLE) | |
13980 | { | |
13981 | fputs ("\t.long (", asm_out_file); | |
13982 | output_addr_const (asm_out_file, symbol); | |
13983 | fputs (")@fixup\n", asm_out_file); | |
13984 | } | |
13985 | else | |
c8af3574 | 13986 | assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1); |
d9f6800d | 13987 | } |
9739c90c JJ |
13988 | |
13989 | void | |
13990 | rs6000_elf_declare_function_name (file, name, decl) | |
13991 | FILE *file; | |
13992 | const char *name; | |
13993 | tree decl; | |
13994 | { | |
13995 | if (TARGET_64BIT) | |
13996 | { | |
13997 | fputs ("\t.section\t\".opd\",\"aw\"\n\t.align 3\n", file); | |
13998 | ASM_OUTPUT_LABEL (file, name); | |
13999 | fputs (DOUBLE_INT_ASM_OP, file); | |
14000 | putc ('.', file); | |
14001 | assemble_name (file, name); | |
14002 | fputs (",.TOC.@tocbase,0\n\t.previous\n\t.size\t", file); | |
14003 | assemble_name (file, name); | |
14004 | fputs (",24\n\t.type\t.", file); | |
14005 | assemble_name (file, name); | |
14006 | fputs (",@function\n", file); | |
14007 | if (TREE_PUBLIC (decl) && ! DECL_WEAK (decl)) | |
14008 | { | |
14009 | fputs ("\t.globl\t.", file); | |
14010 | assemble_name (file, name); | |
14011 | putc ('\n', file); | |
14012 | } | |
14013 | ASM_DECLARE_RESULT (file, DECL_RESULT (decl)); | |
14014 | putc ('.', file); | |
14015 | ASM_OUTPUT_LABEL (file, name); | |
14016 | return; | |
14017 | } | |
14018 | ||
14019 | if (TARGET_RELOCATABLE | |
14020 | && (get_pool_size () != 0 || current_function_profile) | |
14021 | && uses_TOC()) | |
14022 | { | |
14023 | char buf[256]; | |
14024 | ||
14025 | (*targetm.asm_out.internal_label) (file, "LCL", rs6000_pic_labelno); | |
14026 | ||
14027 | ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1); | |
14028 | fprintf (file, "\t.long "); | |
14029 | assemble_name (file, buf); | |
14030 | putc ('-', file); | |
14031 | ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno); | |
14032 | assemble_name (file, buf); | |
14033 | putc ('\n', file); | |
14034 | } | |
14035 | ||
14036 | ASM_OUTPUT_TYPE_DIRECTIVE (file, name, "function"); | |
14037 | ASM_DECLARE_RESULT (file, DECL_RESULT (decl)); | |
14038 | ||
14039 | if (DEFAULT_ABI == ABI_AIX) | |
14040 | { | |
14041 | const char *desc_name, *orig_name; | |
14042 | ||
14043 | orig_name = (*targetm.strip_name_encoding) (name); | |
14044 | desc_name = orig_name; | |
14045 | while (*desc_name == '.') | |
14046 | desc_name++; | |
14047 | ||
14048 | if (TREE_PUBLIC (decl)) | |
14049 | fprintf (file, "\t.globl %s\n", desc_name); | |
14050 | ||
14051 | fprintf (file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP); | |
14052 | fprintf (file, "%s:\n", desc_name); | |
14053 | fprintf (file, "\t.long %s\n", orig_name); | |
14054 | fputs ("\t.long _GLOBAL_OFFSET_TABLE_\n", file); | |
14055 | if (DEFAULT_ABI == ABI_AIX) | |
14056 | fputs ("\t.long 0\n", file); | |
14057 | fprintf (file, "\t.previous\n"); | |
14058 | } | |
14059 | ASM_OUTPUT_LABEL (file, name); | |
14060 | } | |
7c262518 RH |
14061 | #endif |
14062 | ||
cbaaba19 | 14063 | #if TARGET_XCOFF |
7c262518 | 14064 | static void |
b275d088 DE |
14065 | rs6000_xcoff_asm_globalize_label (stream, name) |
14066 | FILE *stream; | |
14067 | const char *name; | |
14068 | { | |
14069 | fputs (GLOBAL_ASM_OP, stream); | |
14070 | RS6000_OUTPUT_BASENAME (stream, name); | |
14071 | putc ('\n', stream); | |
14072 | } | |
14073 | ||
14074 | static void | |
14075 | rs6000_xcoff_asm_named_section (name, flags) | |
7c262518 | 14076 | const char *name; |
0e5dbd9b | 14077 | unsigned int flags; |
7c262518 | 14078 | { |
0e5dbd9b DE |
14079 | int smclass; |
14080 | static const char * const suffix[3] = { "PR", "RO", "RW" }; | |
14081 | ||
14082 | if (flags & SECTION_CODE) | |
14083 | smclass = 0; | |
14084 | else if (flags & SECTION_WRITE) | |
14085 | smclass = 2; | |
14086 | else | |
14087 | smclass = 1; | |
14088 | ||
5b5198f7 | 14089 | fprintf (asm_out_file, "\t.csect %s%s[%s],%u\n", |
0e5dbd9b | 14090 | (flags & SECTION_CODE) ? "." : "", |
5b5198f7 | 14091 | name, suffix[smclass], flags & SECTION_ENTSIZE); |
7c262518 | 14092 | } |
ae46c4e0 RH |
14093 | |
14094 | static void | |
0e5dbd9b DE |
14095 | rs6000_xcoff_select_section (decl, reloc, align) |
14096 | tree decl; | |
ae46c4e0 RH |
14097 | int reloc; |
14098 | unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED; | |
14099 | { | |
5add3202 | 14100 | if (decl_readonly_section_1 (decl, reloc, 1)) |
ae46c4e0 | 14101 | { |
0e5dbd9b | 14102 | if (TREE_PUBLIC (decl)) |
ae46c4e0 RH |
14103 | read_only_data_section (); |
14104 | else | |
14105 | read_only_private_data_section (); | |
14106 | } | |
14107 | else | |
14108 | { | |
0e5dbd9b | 14109 | if (TREE_PUBLIC (decl)) |
ae46c4e0 RH |
14110 | data_section (); |
14111 | else | |
14112 | private_data_section (); | |
14113 | } | |
14114 | } | |
14115 | ||
14116 | static void | |
14117 | rs6000_xcoff_unique_section (decl, reloc) | |
14118 | tree decl; | |
772c5265 | 14119 | int reloc ATTRIBUTE_UNUSED; |
ae46c4e0 RH |
14120 | { |
14121 | const char *name; | |
ae46c4e0 | 14122 | |
5b5198f7 DE |
14123 | /* Use select_section for private and uninitialized data. */ |
14124 | if (!TREE_PUBLIC (decl) | |
14125 | || DECL_COMMON (decl) | |
0e5dbd9b DE |
14126 | || DECL_INITIAL (decl) == NULL_TREE |
14127 | || DECL_INITIAL (decl) == error_mark_node | |
14128 | || (flag_zero_initialized_in_bss | |
14129 | && initializer_zerop (DECL_INITIAL (decl)))) | |
14130 | return; | |
14131 | ||
14132 | name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl)); | |
14133 | name = (*targetm.strip_name_encoding) (name); | |
14134 | DECL_SECTION_NAME (decl) = build_string (strlen (name), name); | |
ae46c4e0 | 14135 | } |
b64a1b53 | 14136 | |
fb49053f RH |
14137 | /* Select section for constant in constant pool. |
14138 | ||
14139 | On RS/6000, all constants are in the private read-only data area. | |
14140 | However, if this is being placed in the TOC it must be output as a | |
14141 | toc entry. */ | |
14142 | ||
b64a1b53 RH |
14143 | static void |
14144 | rs6000_xcoff_select_rtx_section (mode, x, align) | |
14145 | enum machine_mode mode; | |
14146 | rtx x; | |
14147 | unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED; | |
14148 | { | |
14149 | if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode)) | |
14150 | toc_section (); | |
14151 | else | |
14152 | read_only_private_data_section (); | |
14153 | } | |
772c5265 RH |
14154 | |
14155 | /* Remove any trailing [DS] or the like from the symbol name. */ | |
14156 | ||
14157 | static const char * | |
14158 | rs6000_xcoff_strip_name_encoding (name) | |
14159 | const char *name; | |
14160 | { | |
14161 | size_t len; | |
14162 | if (*name == '*') | |
14163 | name++; | |
14164 | len = strlen (name); | |
14165 | if (name[len - 1] == ']') | |
14166 | return ggc_alloc_string (name, len - 4); | |
14167 | else | |
14168 | return name; | |
14169 | } | |
14170 | ||
5add3202 DE |
14171 | /* Section attributes. AIX is always PIC. */ |
14172 | ||
14173 | static unsigned int | |
14174 | rs6000_xcoff_section_type_flags (decl, name, reloc) | |
14175 | tree decl; | |
14176 | const char *name; | |
14177 | int reloc; | |
14178 | { | |
5b5198f7 DE |
14179 | unsigned int align; |
14180 | unsigned int flags = default_section_type_flags_1 (decl, name, reloc, 1); | |
14181 | ||
14182 | /* Align to at least UNIT size. */ | |
14183 | if (flags & SECTION_CODE) | |
14184 | align = MIN_UNITS_PER_WORD; | |
14185 | else | |
14186 | /* Increase alignment of large objects if not already stricter. */ | |
14187 | align = MAX ((DECL_ALIGN (decl) / BITS_PER_UNIT), | |
14188 | int_size_in_bytes (TREE_TYPE (decl)) > MIN_UNITS_PER_WORD | |
14189 | ? UNITS_PER_FP_WORD : MIN_UNITS_PER_WORD); | |
14190 | ||
14191 | return flags | (exact_log2 (align) & SECTION_ENTSIZE); | |
5add3202 | 14192 | } |
a5fe455b | 14193 | |
1bc7c5b6 ZW |
14194 | /* Output at beginning of assembler file. |
14195 | ||
14196 | Initialize the section names for the RS/6000 at this point. | |
14197 | ||
14198 | Specify filename, including full path, to assembler. | |
14199 | ||
14200 | We want to go into the TOC section so at least one .toc will be emitted. | |
14201 | Also, in order to output proper .bs/.es pairs, we need at least one static | |
14202 | [RW] section emitted. | |
14203 | ||
14204 | Finally, declare mcount when profiling to make the assembler happy. */ | |
14205 | ||
14206 | static void | |
14207 | rs6000_xcoff_file_start () | |
14208 | { | |
14209 | rs6000_gen_section_name (&xcoff_bss_section_name, | |
14210 | main_input_filename, ".bss_"); | |
14211 | rs6000_gen_section_name (&xcoff_private_data_section_name, | |
14212 | main_input_filename, ".rw_"); | |
14213 | rs6000_gen_section_name (&xcoff_read_only_section_name, | |
14214 | main_input_filename, ".ro_"); | |
14215 | ||
14216 | fputs ("\t.file\t", asm_out_file); | |
14217 | output_quoted_string (asm_out_file, main_input_filename); | |
14218 | fputc ('\n', asm_out_file); | |
14219 | toc_section (); | |
14220 | if (write_symbols != NO_DEBUG) | |
14221 | private_data_section (); | |
14222 | text_section (); | |
14223 | if (profile_flag) | |
14224 | fprintf (asm_out_file, "\t.extern %s\n", RS6000_MCOUNT); | |
14225 | rs6000_file_start (); | |
14226 | } | |
14227 | ||
a5fe455b ZW |
14228 | /* Output at end of assembler file. |
14229 | On the RS/6000, referencing data should automatically pull in text. */ | |
14230 | ||
14231 | static void | |
14232 | rs6000_xcoff_file_end () | |
14233 | { | |
14234 | text_section (); | |
14235 | fputs ("_section_.text:\n", asm_out_file); | |
14236 | data_section (); | |
14237 | fputs (TARGET_32BIT | |
14238 | ? "\t.long _section_.text\n" : "\t.llong _section_.text\n", | |
14239 | asm_out_file); | |
14240 | } | |
f1384257 | 14241 | #endif /* TARGET_XCOFF */ |
0e5dbd9b | 14242 | |
f1384257 AM |
14243 | #if TARGET_MACHO |
14244 | /* Cross-module name binding. Darwin does not support overriding | |
7f3d8013 | 14245 | functions at dynamic-link time. */ |
0e5dbd9b | 14246 | |
2bcc50d0 | 14247 | static bool |
0e5dbd9b DE |
14248 | rs6000_binds_local_p (decl) |
14249 | tree decl; | |
14250 | { | |
f1384257 | 14251 | return default_binds_local_p_1 (decl, 0); |
0e5dbd9b | 14252 | } |
f1384257 | 14253 | #endif |
34bb030a | 14254 | |
3c50106f RH |
14255 | /* Compute a (partial) cost for rtx X. Return true if the complete |
14256 | cost has been computed, and false if subexpressions should be | |
14257 | scanned. In either case, *TOTAL contains the cost result. */ | |
14258 | ||
14259 | static bool | |
14260 | rs6000_rtx_costs (x, code, outer_code, total) | |
14261 | rtx x; | |
14262 | int code, outer_code ATTRIBUTE_UNUSED; | |
14263 | int *total; | |
14264 | { | |
14265 | switch (code) | |
14266 | { | |
14267 | /* On the RS/6000, if it is valid in the insn, it is free. | |
14268 | So this always returns 0. */ | |
14269 | case CONST_INT: | |
14270 | case CONST: | |
14271 | case LABEL_REF: | |
14272 | case SYMBOL_REF: | |
14273 | case CONST_DOUBLE: | |
14274 | case HIGH: | |
14275 | *total = 0; | |
14276 | return true; | |
14277 | ||
14278 | case PLUS: | |
14279 | *total = ((GET_CODE (XEXP (x, 1)) == CONST_INT | |
14280 | && ((unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 1)) | |
14281 | + 0x8000) >= 0x10000) | |
14282 | && ((INTVAL (XEXP (x, 1)) & 0xffff) != 0)) | |
14283 | ? COSTS_N_INSNS (2) | |
14284 | : COSTS_N_INSNS (1)); | |
14285 | return true; | |
14286 | ||
14287 | case AND: | |
14288 | case IOR: | |
14289 | case XOR: | |
14290 | *total = ((GET_CODE (XEXP (x, 1)) == CONST_INT | |
14291 | && (INTVAL (XEXP (x, 1)) & (~ (HOST_WIDE_INT) 0xffff)) != 0 | |
14292 | && ((INTVAL (XEXP (x, 1)) & 0xffff) != 0)) | |
14293 | ? COSTS_N_INSNS (2) | |
14294 | : COSTS_N_INSNS (1)); | |
14295 | return true; | |
14296 | ||
14297 | case MULT: | |
14298 | if (optimize_size) | |
14299 | { | |
14300 | *total = COSTS_N_INSNS (2); | |
14301 | return true; | |
14302 | } | |
14303 | switch (rs6000_cpu) | |
14304 | { | |
14305 | case PROCESSOR_RIOS1: | |
14306 | case PROCESSOR_PPC405: | |
14307 | *total = (GET_CODE (XEXP (x, 1)) != CONST_INT | |
14308 | ? COSTS_N_INSNS (5) | |
14309 | : (INTVAL (XEXP (x, 1)) >= -256 | |
14310 | && INTVAL (XEXP (x, 1)) <= 255) | |
14311 | ? COSTS_N_INSNS (3) : COSTS_N_INSNS (4)); | |
14312 | return true; | |
14313 | ||
02ca7595 DE |
14314 | case PROCESSOR_PPC440: |
14315 | *total = (GET_CODE (XEXP (x, 1)) != CONST_INT | |
14316 | ? COSTS_N_INSNS (3) | |
14317 | : COSTS_N_INSNS (2)); | |
14318 | return true; | |
14319 | ||
3c50106f RH |
14320 | case PROCESSOR_RS64A: |
14321 | *total = (GET_CODE (XEXP (x, 1)) != CONST_INT | |
14322 | ? GET_MODE (XEXP (x, 1)) != DImode | |
14323 | ? COSTS_N_INSNS (20) : COSTS_N_INSNS (34) | |
14324 | : (INTVAL (XEXP (x, 1)) >= -256 | |
14325 | && INTVAL (XEXP (x, 1)) <= 255) | |
14326 | ? COSTS_N_INSNS (8) : COSTS_N_INSNS (12)); | |
14327 | return true; | |
14328 | ||
14329 | case PROCESSOR_RIOS2: | |
14330 | case PROCESSOR_MPCCORE: | |
14331 | case PROCESSOR_PPC604e: | |
14332 | *total = COSTS_N_INSNS (2); | |
14333 | return true; | |
14334 | ||
14335 | case PROCESSOR_PPC601: | |
14336 | *total = COSTS_N_INSNS (5); | |
14337 | return true; | |
14338 | ||
14339 | case PROCESSOR_PPC603: | |
14340 | case PROCESSOR_PPC7400: | |
14341 | case PROCESSOR_PPC750: | |
14342 | *total = (GET_CODE (XEXP (x, 1)) != CONST_INT | |
14343 | ? COSTS_N_INSNS (5) | |
14344 | : (INTVAL (XEXP (x, 1)) >= -256 | |
14345 | && INTVAL (XEXP (x, 1)) <= 255) | |
14346 | ? COSTS_N_INSNS (2) : COSTS_N_INSNS (3)); | |
14347 | return true; | |
14348 | ||
14349 | case PROCESSOR_PPC7450: | |
14350 | *total = (GET_CODE (XEXP (x, 1)) != CONST_INT | |
14351 | ? COSTS_N_INSNS (4) | |
14352 | : COSTS_N_INSNS (3)); | |
14353 | return true; | |
14354 | ||
14355 | case PROCESSOR_PPC403: | |
14356 | case PROCESSOR_PPC604: | |
14357 | case PROCESSOR_PPC8540: | |
14358 | *total = COSTS_N_INSNS (4); | |
14359 | return true; | |
14360 | ||
14361 | case PROCESSOR_PPC620: | |
14362 | case PROCESSOR_PPC630: | |
3c50106f RH |
14363 | *total = (GET_CODE (XEXP (x, 1)) != CONST_INT |
14364 | ? GET_MODE (XEXP (x, 1)) != DImode | |
14365 | ? COSTS_N_INSNS (5) : COSTS_N_INSNS (7) | |
14366 | : (INTVAL (XEXP (x, 1)) >= -256 | |
14367 | && INTVAL (XEXP (x, 1)) <= 255) | |
14368 | ? COSTS_N_INSNS (3) : COSTS_N_INSNS (4)); | |
14369 | return true; | |
14370 | ||
9259f3b0 DE |
14371 | case PROCESSOR_POWER4: |
14372 | *total = (GET_CODE (XEXP (x, 1)) != CONST_INT | |
14373 | ? GET_MODE (XEXP (x, 1)) != DImode | |
984e25ac DE |
14374 | ? COSTS_N_INSNS (3) : COSTS_N_INSNS (4) |
14375 | : COSTS_N_INSNS (2)); | |
9259f3b0 DE |
14376 | return true; |
14377 | ||
3c50106f RH |
14378 | default: |
14379 | abort (); | |
14380 | } | |
14381 | ||
14382 | case DIV: | |
14383 | case MOD: | |
14384 | if (GET_CODE (XEXP (x, 1)) == CONST_INT | |
14385 | && exact_log2 (INTVAL (XEXP (x, 1))) >= 0) | |
14386 | { | |
14387 | *total = COSTS_N_INSNS (2); | |
14388 | return true; | |
14389 | } | |
14390 | /* FALLTHRU */ | |
14391 | ||
14392 | case UDIV: | |
14393 | case UMOD: | |
14394 | switch (rs6000_cpu) | |
14395 | { | |
14396 | case PROCESSOR_RIOS1: | |
14397 | *total = COSTS_N_INSNS (19); | |
14398 | return true; | |
14399 | ||
14400 | case PROCESSOR_RIOS2: | |
14401 | *total = COSTS_N_INSNS (13); | |
14402 | return true; | |
14403 | ||
14404 | case PROCESSOR_RS64A: | |
14405 | *total = (GET_MODE (XEXP (x, 1)) != DImode | |
14406 | ? COSTS_N_INSNS (65) | |
14407 | : COSTS_N_INSNS (67)); | |
14408 | return true; | |
14409 | ||
14410 | case PROCESSOR_MPCCORE: | |
14411 | *total = COSTS_N_INSNS (6); | |
14412 | return true; | |
14413 | ||
14414 | case PROCESSOR_PPC403: | |
14415 | *total = COSTS_N_INSNS (33); | |
14416 | return true; | |
14417 | ||
14418 | case PROCESSOR_PPC405: | |
14419 | *total = COSTS_N_INSNS (35); | |
14420 | return true; | |
14421 | ||
02ca7595 DE |
14422 | case PROCESSOR_PPC440: |
14423 | *total = COSTS_N_INSNS (34); | |
14424 | return true; | |
14425 | ||
3c50106f RH |
14426 | case PROCESSOR_PPC601: |
14427 | *total = COSTS_N_INSNS (36); | |
14428 | return true; | |
14429 | ||
14430 | case PROCESSOR_PPC603: | |
14431 | *total = COSTS_N_INSNS (37); | |
14432 | return true; | |
14433 | ||
14434 | case PROCESSOR_PPC604: | |
14435 | case PROCESSOR_PPC604e: | |
14436 | *total = COSTS_N_INSNS (20); | |
14437 | return true; | |
14438 | ||
14439 | case PROCESSOR_PPC620: | |
14440 | case PROCESSOR_PPC630: | |
3c50106f RH |
14441 | *total = (GET_MODE (XEXP (x, 1)) != DImode |
14442 | ? COSTS_N_INSNS (21) | |
14443 | : COSTS_N_INSNS (37)); | |
14444 | return true; | |
14445 | ||
14446 | case PROCESSOR_PPC750: | |
14447 | case PROCESSOR_PPC8540: | |
14448 | case PROCESSOR_PPC7400: | |
14449 | *total = COSTS_N_INSNS (19); | |
14450 | return true; | |
14451 | ||
14452 | case PROCESSOR_PPC7450: | |
14453 | *total = COSTS_N_INSNS (23); | |
14454 | return true; | |
984e25ac DE |
14455 | |
14456 | case PROCESSOR_POWER4: | |
14457 | *total = (GET_MODE (XEXP (x, 1)) != DImode | |
14458 | ? COSTS_N_INSNS (18) | |
14459 | : COSTS_N_INSNS (34)); | |
14460 | return true; | |
3c50106f RH |
14461 | |
14462 | default: | |
14463 | abort (); | |
14464 | } | |
14465 | ||
14466 | case FFS: | |
14467 | *total = COSTS_N_INSNS (4); | |
14468 | return true; | |
14469 | ||
14470 | case MEM: | |
14471 | /* MEM should be slightly more expensive than (plus (reg) (const)) */ | |
14472 | *total = 5; | |
14473 | return true; | |
14474 | ||
14475 | default: | |
14476 | return false; | |
14477 | } | |
14478 | } | |
14479 | ||
34bb030a DE |
14480 | /* A C expression returning the cost of moving data from a register of class |
14481 | CLASS1 to one of CLASS2. */ | |
14482 | ||
14483 | int | |
14484 | rs6000_register_move_cost (mode, from, to) | |
14485 | enum machine_mode mode; | |
14486 | enum reg_class from, to; | |
14487 | { | |
14488 | /* Moves from/to GENERAL_REGS. */ | |
14489 | if (reg_classes_intersect_p (to, GENERAL_REGS) | |
14490 | || reg_classes_intersect_p (from, GENERAL_REGS)) | |
14491 | { | |
14492 | if (! reg_classes_intersect_p (to, GENERAL_REGS)) | |
14493 | from = to; | |
14494 | ||
14495 | if (from == FLOAT_REGS || from == ALTIVEC_REGS) | |
14496 | return (rs6000_memory_move_cost (mode, from, 0) | |
14497 | + rs6000_memory_move_cost (mode, GENERAL_REGS, 0)); | |
14498 | ||
14499 | /* It's more expensive to move CR_REGS than CR0_REGS because of the shift...*/ | |
14500 | else if (from == CR_REGS) | |
14501 | return 4; | |
14502 | ||
14503 | else | |
14504 | /* A move will cost one instruction per GPR moved. */ | |
14505 | return 2 * HARD_REGNO_NREGS (0, mode); | |
14506 | } | |
14507 | ||
14508 | /* Moving between two similar registers is just one instruction. */ | |
14509 | else if (reg_classes_intersect_p (to, from)) | |
14510 | return mode == TFmode ? 4 : 2; | |
14511 | ||
14512 | /* Everything else has to go through GENERAL_REGS. */ | |
14513 | else | |
14514 | return (rs6000_register_move_cost (mode, GENERAL_REGS, to) | |
14515 | + rs6000_register_move_cost (mode, from, GENERAL_REGS)); | |
14516 | } | |
14517 | ||
14518 | /* A C expressions returning the cost of moving data of MODE from a register to | |
14519 | or from memory. */ | |
14520 | ||
14521 | int | |
14522 | rs6000_memory_move_cost (mode, class, in) | |
14523 | enum machine_mode mode; | |
14524 | enum reg_class class; | |
14525 | int in ATTRIBUTE_UNUSED; | |
14526 | { | |
14527 | if (reg_classes_intersect_p (class, GENERAL_REGS)) | |
14528 | return 4 * HARD_REGNO_NREGS (0, mode); | |
14529 | else if (reg_classes_intersect_p (class, FLOAT_REGS)) | |
14530 | return 4 * HARD_REGNO_NREGS (32, mode); | |
14531 | else if (reg_classes_intersect_p (class, ALTIVEC_REGS)) | |
14532 | return 4 * HARD_REGNO_NREGS (FIRST_ALTIVEC_REGNO, mode); | |
14533 | else | |
14534 | return 4 + rs6000_register_move_cost (mode, class, GENERAL_REGS); | |
14535 | } | |
14536 | ||
ded9bf77 AH |
14537 | /* Return an RTX representing where to find the function value of a |
14538 | function returning MODE. */ | |
14539 | static rtx | |
14540 | rs6000_complex_function_value (enum machine_mode mode) | |
14541 | { | |
14542 | unsigned int regno; | |
14543 | rtx r1, r2; | |
14544 | enum machine_mode inner = GET_MODE_INNER (mode); | |
14545 | ||
14546 | if (FLOAT_MODE_P (mode)) | |
14547 | regno = FP_ARG_RETURN; | |
14548 | else | |
14549 | { | |
14550 | regno = GP_ARG_RETURN; | |
14551 | ||
14552 | /* 32-bit is OK since it'll go in r3/r4. */ | |
165848da AH |
14553 | if (TARGET_32BIT |
14554 | && GET_MODE_BITSIZE (inner) >= 32) | |
ded9bf77 AH |
14555 | return gen_rtx_REG (mode, regno); |
14556 | } | |
14557 | ||
14558 | r1 = gen_rtx_EXPR_LIST (inner, gen_rtx_REG (inner, regno), | |
14559 | const0_rtx); | |
14560 | r2 = gen_rtx_EXPR_LIST (inner, gen_rtx_REG (inner, regno + 1), | |
14561 | GEN_INT (GET_MODE_UNIT_SIZE (inner))); | |
14562 | return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r2)); | |
14563 | } | |
14564 | ||
a6ebc39a AH |
14565 | /* Define how to find the value returned by a function. |
14566 | VALTYPE is the data type of the value (as a tree). | |
14567 | If the precise function being called is known, FUNC is its FUNCTION_DECL; | |
14568 | otherwise, FUNC is 0. | |
14569 | ||
14570 | On the SPE, both FPs and vectors are returned in r3. | |
14571 | ||
14572 | On RS/6000 an integer value is in r3 and a floating-point value is in | |
14573 | fp1, unless -msoft-float. */ | |
14574 | ||
14575 | rtx | |
14576 | rs6000_function_value (tree valtype, tree func ATTRIBUTE_UNUSED) | |
14577 | { | |
14578 | enum machine_mode mode; | |
2a8fa26c | 14579 | unsigned int regno; |
a6ebc39a AH |
14580 | |
14581 | if ((INTEGRAL_TYPE_P (valtype) | |
14582 | && TYPE_PRECISION (valtype) < BITS_PER_WORD) | |
14583 | || POINTER_TYPE_P (valtype)) | |
14584 | mode = word_mode; | |
14585 | else | |
14586 | mode = TYPE_MODE (valtype); | |
14587 | ||
2a8fa26c DE |
14588 | if (TREE_CODE (valtype) == REAL_TYPE && TARGET_HARD_FLOAT && TARGET_FPRS) |
14589 | regno = FP_ARG_RETURN; | |
ded9bf77 AH |
14590 | else if (TREE_CODE (valtype) == COMPLEX_TYPE |
14591 | && TARGET_HARD_FLOAT | |
14592 | && SPLIT_COMPLEX_ARGS) | |
14593 | return rs6000_complex_function_value (mode); | |
2a8fa26c | 14594 | else if (TREE_CODE (valtype) == VECTOR_TYPE && TARGET_ALTIVEC) |
a6ebc39a AH |
14595 | regno = ALTIVEC_ARG_RETURN; |
14596 | else | |
14597 | regno = GP_ARG_RETURN; | |
14598 | ||
14599 | return gen_rtx_REG (mode, regno); | |
14600 | } | |
14601 | ||
ded9bf77 AH |
14602 | /* Define how to find the value returned by a library function |
14603 | assuming the value has mode MODE. */ | |
14604 | rtx | |
14605 | rs6000_libcall_value (enum machine_mode mode) | |
14606 | { | |
14607 | unsigned int regno; | |
14608 | ||
14609 | if (GET_MODE_CLASS (mode) == MODE_FLOAT | |
14610 | && TARGET_HARD_FLOAT && TARGET_FPRS) | |
14611 | regno = FP_ARG_RETURN; | |
14612 | else if (ALTIVEC_VECTOR_MODE (mode)) | |
14613 | regno = ALTIVEC_ARG_RETURN; | |
14614 | else if (COMPLEX_MODE_P (mode) && SPLIT_COMPLEX_ARGS) | |
14615 | return rs6000_complex_function_value (mode); | |
14616 | else | |
14617 | regno = GP_ARG_RETURN; | |
14618 | ||
14619 | return gen_rtx_REG (mode, regno); | |
14620 | } | |
14621 | ||
62e1dfcf NC |
14622 | /* Return true if TYPE is of type __ev64_opaque__. */ |
14623 | ||
c8e4f0e9 | 14624 | static bool |
62e1dfcf NC |
14625 | is_ev64_opaque_type (type) |
14626 | tree type; | |
14627 | { | |
c8e4f0e9 | 14628 | return (TARGET_SPE |
2abe3e28 AH |
14629 | && (type == opaque_V2SI_type_node |
14630 | || type == opaque_V2SF_type_node | |
6035d635 | 14631 | || type == opaque_p_V2SI_type_node |
2abe3e28 AH |
14632 | || (TREE_CODE (type) == VECTOR_TYPE |
14633 | && TYPE_NAME (type) | |
14634 | && TREE_CODE (TYPE_NAME (type)) == TYPE_DECL | |
14635 | && DECL_NAME (TYPE_NAME (type)) | |
14636 | && strcmp (IDENTIFIER_POINTER (DECL_NAME (TYPE_NAME (type))), | |
14637 | "__ev64_opaque__") == 0))); | |
62e1dfcf NC |
14638 | } |
14639 | ||
96714395 AH |
14640 | static rtx |
14641 | rs6000_dwarf_register_span (reg) | |
14642 | rtx reg; | |
14643 | { | |
14644 | unsigned regno; | |
14645 | ||
14646 | if (!TARGET_SPE || !SPE_VECTOR_MODE (GET_MODE (reg))) | |
14647 | return NULL_RTX; | |
14648 | ||
14649 | regno = REGNO (reg); | |
14650 | ||
14651 | /* The duality of the SPE register size wreaks all kinds of havoc. | |
14652 | This is a way of distinguishing r0 in 32-bits from r0 in | |
14653 | 64-bits. */ | |
14654 | return | |
14655 | gen_rtx_PARALLEL (VOIDmode, | |
3bd104d1 AH |
14656 | BYTES_BIG_ENDIAN |
14657 | ? gen_rtvec (2, | |
14658 | gen_rtx_REG (SImode, regno + 1200), | |
14659 | gen_rtx_REG (SImode, regno)) | |
14660 | : gen_rtvec (2, | |
14661 | gen_rtx_REG (SImode, regno), | |
14662 | gen_rtx_REG (SImode, regno + 1200))); | |
96714395 AH |
14663 | } |
14664 | ||
17211ab5 | 14665 | #include "gt-rs6000.h" |