]>
Commit | Line | Data |
---|---|---|
9878760c | 1 | /* Subroutines used for code generation on IBM RS/6000. |
cf27b467 | 2 | Copyright (C) 1991, 1993, 1994, 1995, 1996 Free Software Foundation, Inc. |
fab3bcc3 | 3 | Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu) |
9878760c RK |
4 | |
5 | This file is part of GNU CC. | |
6 | ||
7 | GNU CC is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 2, or (at your option) | |
10 | any later version. | |
11 | ||
12 | GNU CC is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with GNU CC; see the file COPYING. If not, write to | |
c15c9075 RK |
19 | the Free Software Foundation, 59 Temple Place - Suite 330, |
20 | Boston, MA 02111-1307, USA. */ | |
9878760c RK |
21 | |
22 | #include <stdio.h> | |
127b0efc | 23 | #include <ctype.h> |
9878760c RK |
24 | #include "config.h" |
25 | #include "rtl.h" | |
26 | #include "regs.h" | |
27 | #include "hard-reg-set.h" | |
28 | #include "real.h" | |
29 | #include "insn-config.h" | |
30 | #include "conditions.h" | |
31 | #include "insn-flags.h" | |
32 | #include "output.h" | |
33 | #include "insn-attr.h" | |
34 | #include "flags.h" | |
35 | #include "recog.h" | |
36 | #include "expr.h" | |
37 | #include "obstack.h" | |
9b30bae2 JW |
38 | #include "tree.h" |
39 | ||
7509c759 MM |
40 | #ifndef TARGET_NO_PROTOTYPE |
41 | #define TARGET_NO_PROTOTYPE 0 | |
42 | #endif | |
43 | ||
9b30bae2 | 44 | extern char *language_string; |
5248c961 | 45 | extern int profile_block_flag; |
9878760c RK |
46 | |
47 | #define min(A,B) ((A) < (B) ? (A) : (B)) | |
48 | #define max(A,B) ((A) > (B) ? (A) : (B)) | |
49 | ||
5248c961 RK |
50 | /* Target cpu type */ |
51 | ||
52 | enum processor_type rs6000_cpu; | |
8e3f41e7 MM |
53 | struct rs6000_cpu_select rs6000_select[3] = |
54 | { | |
55 | /* switch name, tune arch */ | |
5d6426e0 | 56 | { (char *)0, "--with-cpu=", 1, 1 }, |
8e3f41e7 MM |
57 | { (char *)0, "-mcpu=", 1, 1 }, |
58 | { (char *)0, "-mtune=", 1, 0 }, | |
59 | }; | |
5248c961 | 60 | |
9878760c RK |
61 | /* Set to non-zero by "fix" operation to indicate that itrunc and |
62 | uitrunc must be defined. */ | |
63 | ||
64 | int rs6000_trunc_used; | |
65 | ||
66 | /* Set to non-zero once they have been defined. */ | |
67 | ||
68 | static int trunc_defined; | |
69 | ||
c764f757 RK |
70 | /* Set to non-zero once AIX common-mode calls have been defined. */ |
71 | static int common_mode_defined; | |
c81bebd7 | 72 | |
9878760c RK |
73 | /* Save information from a "cmpxx" operation until the branch or scc is |
74 | emitted. */ | |
9878760c RK |
75 | rtx rs6000_compare_op0, rs6000_compare_op1; |
76 | int rs6000_compare_fp_p; | |
874a0744 MM |
77 | |
78 | #ifdef USING_SVR4_H | |
79 | /* Label number of label created for -mrelocatable, to call to so we can | |
80 | get the address of the GOT section */ | |
81 | int rs6000_pic_labelno; | |
c81bebd7 MM |
82 | |
83 | /* Which abi to adhere to */ | |
84 | char *rs6000_abi_name = RS6000_ABI_NAME; | |
d9407988 MM |
85 | |
86 | /* Semantics of the small data area */ | |
87 | enum rs6000_sdata_type rs6000_sdata = SDATA_DATA; | |
88 | ||
89 | /* Which small data model to use */ | |
90 | char *rs6000_sdata_name = (char *)0; | |
874a0744 | 91 | #endif |
4697a36c MM |
92 | |
93 | /* Whether a System V.4 varargs area was created. */ | |
94 | int rs6000_sysv_varargs_p; | |
8f75773e | 95 | |
b6c9286a MM |
96 | /* Whether we need to save the TOC register. */ |
97 | int rs6000_save_toc_p; | |
98 | ||
99 | /* ABI enumeration available for subtarget to use. */ | |
100 | enum rs6000_abi rs6000_current_abi; | |
101 | ||
802a0058 MM |
102 | /* Offset & size for fpmem stack locations used for converting between |
103 | float and integral types. */ | |
104 | int rs6000_fpmem_offset; | |
105 | int rs6000_fpmem_size; | |
106 | ||
c81bebd7 MM |
107 | \f |
108 | /* Default register names. */ | |
109 | char rs6000_reg_names[][8] = | |
110 | { | |
802a0058 MM |
111 | "0", "1", "2", "3", "4", "5", "6", "7", |
112 | "8", "9", "10", "11", "12", "13", "14", "15", | |
113 | "16", "17", "18", "19", "20", "21", "22", "23", | |
114 | "24", "25", "26", "27", "28", "29", "30", "31", | |
115 | "0", "1", "2", "3", "4", "5", "6", "7", | |
116 | "8", "9", "10", "11", "12", "13", "14", "15", | |
117 | "16", "17", "18", "19", "20", "21", "22", "23", | |
118 | "24", "25", "26", "27", "28", "29", "30", "31", | |
119 | "mq", "lr", "ctr","ap", | |
120 | "0", "1", "2", "3", "4", "5", "6", "7", | |
121 | "fpmem" | |
c81bebd7 MM |
122 | }; |
123 | ||
124 | #ifdef TARGET_REGNAMES | |
125 | static char alt_reg_names[][8] = | |
126 | { | |
802a0058 MM |
127 | "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7", |
128 | "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15", | |
129 | "%r16", "%r17", "%r18", "%r19", "%r20", "%r21", "%r22", "%r23", | |
130 | "%r24", "%r25", "%r26", "%r27", "%r28", "%r29", "%r30", "%r31", | |
131 | "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7", | |
132 | "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15", | |
133 | "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23", | |
134 | "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31", | |
135 | "mq", "lr", "ctr", "ap", | |
136 | "%cr0", "%cr1", "%cr2", "%cr3", "%cr4", "%cr5", "%cr6", "%cr7", | |
137 | "fpmem" | |
c81bebd7 MM |
138 | }; |
139 | #endif | |
9878760c | 140 | \f |
5248c961 RK |
141 | /* Override command line options. Mostly we process the processor |
142 | type and sometimes adjust other TARGET_ options. */ | |
143 | ||
144 | void | |
8e3f41e7 MM |
145 | rs6000_override_options (default_cpu) |
146 | char *default_cpu; | |
5248c961 | 147 | { |
8e3f41e7 MM |
148 | int i, j; |
149 | struct rs6000_cpu_select *ptr; | |
5248c961 | 150 | |
85638c0d RK |
151 | /* Simplify the entries below by making a mask for any POWER |
152 | variant and any PowerPC variant. */ | |
153 | ||
938937d8 | 154 | #define POWER_MASKS (MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING) |
68c49ffa RK |
155 | #define POWERPC_MASKS (MASK_POWERPC | MASK_PPC_GPOPT \ |
156 | | MASK_PPC_GFXOPT | MASK_POWERPC64) | |
157 | #define POWERPC_OPT_MASKS (MASK_PPC_GPOPT | MASK_PPC_GFXOPT) | |
85638c0d | 158 | |
5248c961 RK |
159 | static struct ptt |
160 | { | |
161 | char *name; /* Canonical processor name. */ | |
162 | enum processor_type processor; /* Processor type enum value. */ | |
163 | int target_enable; /* Target flags to enable. */ | |
164 | int target_disable; /* Target flags to disable. */ | |
165 | } processor_target_table[] | |
cf27b467 MM |
166 | = {{"common", PROCESSOR_COMMON, MASK_NEW_MNEMONICS, |
167 | POWER_MASKS | POWERPC_MASKS}, | |
db7f1e43 | 168 | {"power", PROCESSOR_POWER, |
938937d8 | 169 | MASK_POWER | MASK_MULTIPLE | MASK_STRING, |
db7f1e43 | 170 | MASK_POWER2 | POWERPC_MASKS | MASK_NEW_MNEMONICS}, |
8e3f41e7 MM |
171 | {"power2", PROCESSOR_POWER, |
172 | MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING, | |
173 | POWERPC_MASKS | MASK_NEW_MNEMONICS}, | |
db7f1e43 RK |
174 | {"powerpc", PROCESSOR_POWERPC, |
175 | MASK_POWERPC | MASK_NEW_MNEMONICS, | |
68c49ffa | 176 | POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64}, |
db7f1e43 | 177 | {"rios", PROCESSOR_RIOS1, |
938937d8 | 178 | MASK_POWER | MASK_MULTIPLE | MASK_STRING, |
db7f1e43 RK |
179 | MASK_POWER2 | POWERPC_MASKS | MASK_NEW_MNEMONICS}, |
180 | {"rios1", PROCESSOR_RIOS1, | |
938937d8 | 181 | MASK_POWER | MASK_MULTIPLE | MASK_STRING, |
db7f1e43 RK |
182 | MASK_POWER2 | POWERPC_MASKS | MASK_NEW_MNEMONICS}, |
183 | {"rsc", PROCESSOR_PPC601, | |
938937d8 | 184 | MASK_POWER | MASK_MULTIPLE | MASK_STRING, |
db7f1e43 RK |
185 | MASK_POWER2 | POWERPC_MASKS | MASK_NEW_MNEMONICS}, |
186 | {"rsc1", PROCESSOR_PPC601, | |
938937d8 | 187 | MASK_POWER | MASK_MULTIPLE | MASK_STRING, |
db7f1e43 RK |
188 | MASK_POWER2 | POWERPC_MASKS | MASK_NEW_MNEMONICS}, |
189 | {"rios2", PROCESSOR_RIOS2, | |
938937d8 | 190 | MASK_POWER | MASK_MULTIPLE | MASK_STRING | MASK_POWER2, |
db7f1e43 | 191 | POWERPC_MASKS | MASK_NEW_MNEMONICS}, |
49a0b204 MM |
192 | {"403", PROCESSOR_PPC403, |
193 | MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS, | |
194 | POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64}, | |
cf27b467 MM |
195 | {"505", PROCESSOR_MPCCORE, |
196 | MASK_POWERPC | MASK_NEW_MNEMONICS, | |
197 | POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64}, | |
5248c961 | 198 | {"601", PROCESSOR_PPC601, |
938937d8 | 199 | MASK_POWER | MASK_POWERPC | MASK_NEW_MNEMONICS | MASK_MULTIPLE | MASK_STRING, |
68c49ffa | 200 | MASK_POWER2 | POWERPC_OPT_MASKS | MASK_POWERPC64}, |
1ec26da6 | 201 | {"602", PROCESSOR_PPC603, |
cf27b467 MM |
202 | MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS, |
203 | POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64}, | |
5248c961 | 204 | {"603", PROCESSOR_PPC603, |
68c49ffa RK |
205 | MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS, |
206 | POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64}, | |
b6c9286a MM |
207 | {"603e", PROCESSOR_PPC603, |
208 | MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS, | |
209 | POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64}, | |
5248c961 | 210 | {"604", PROCESSOR_PPC604, |
b6c9286a MM |
211 | MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS, |
212 | POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64}, | |
213 | {"620", PROCESSOR_PPC620, | |
68c49ffa | 214 | MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS, |
cf27b467 MM |
215 | POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64}, |
216 | {"821", PROCESSOR_MPCCORE, | |
217 | MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS, | |
218 | POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64}, | |
219 | {"860", PROCESSOR_MPCCORE, | |
220 | MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS, | |
221 | POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64}}; | |
5248c961 RK |
222 | |
223 | int ptt_size = sizeof (processor_target_table) / sizeof (struct ptt); | |
224 | ||
8a61d227 | 225 | int multiple = TARGET_MULTIPLE; /* save current -mmultiple/-mno-multiple status */ |
938937d8 | 226 | int string = TARGET_STRING; /* save current -mstring/-mno-string status */ |
8a61d227 | 227 | |
5248c961 RK |
228 | profile_block_flag = 0; |
229 | ||
230 | /* Identify the processor type */ | |
8e3f41e7 MM |
231 | rs6000_select[0].string = default_cpu; |
232 | rs6000_cpu = PROCESSOR_DEFAULT; | |
8e3f41e7 MM |
233 | |
234 | for (i = 0; i < sizeof (rs6000_select) / sizeof (rs6000_select[0]); i++) | |
5248c961 | 235 | { |
8e3f41e7 MM |
236 | ptr = &rs6000_select[i]; |
237 | if (ptr->string != (char *)0 && ptr->string[0] != '\0') | |
5248c961 | 238 | { |
8e3f41e7 MM |
239 | for (j = 0; j < ptt_size; j++) |
240 | if (! strcmp (ptr->string, processor_target_table[j].name)) | |
241 | { | |
242 | if (ptr->set_tune_p) | |
243 | rs6000_cpu = processor_target_table[j].processor; | |
244 | ||
245 | if (ptr->set_arch_p) | |
246 | { | |
247 | target_flags |= processor_target_table[j].target_enable; | |
248 | target_flags &= ~processor_target_table[j].target_disable; | |
249 | } | |
250 | break; | |
251 | } | |
252 | ||
253 | if (i == ptt_size) | |
254 | error ("bad value (%s) for %s switch", ptr->string, ptr->name); | |
5248c961 RK |
255 | } |
256 | } | |
8a61d227 MM |
257 | |
258 | /* If -mmultiple or -mno-multiple was explicitly used, don't | |
259 | override with the processor default */ | |
260 | if (TARGET_MULTIPLE_SET) | |
261 | target_flags = (target_flags & ~MASK_MULTIPLE) | multiple; | |
7e69e155 | 262 | |
938937d8 MM |
263 | /* If -mstring or -mno-string was explicitly used, don't |
264 | override with the processor default */ | |
265 | if (TARGET_STRING_SET) | |
1f5515bf | 266 | target_flags = (target_flags & ~MASK_STRING) | string; |
938937d8 | 267 | |
7e69e155 MM |
268 | /* Don't allow -mmultiple or -mstring on little endian systems, because the |
269 | hardware doesn't support the instructions used in little endian mode */ | |
270 | if (!BYTES_BIG_ENDIAN) | |
271 | { | |
272 | if (TARGET_MULTIPLE) | |
273 | { | |
274 | target_flags &= ~MASK_MULTIPLE; | |
275 | if (TARGET_MULTIPLE_SET) | |
276 | warning ("-mmultiple is not supported on little endian systems"); | |
277 | } | |
278 | ||
279 | if (TARGET_STRING) | |
280 | { | |
281 | target_flags &= ~MASK_STRING; | |
938937d8 MM |
282 | if (TARGET_STRING_SET) |
283 | warning ("-mstring is not supported on little endian systems"); | |
7e69e155 MM |
284 | } |
285 | } | |
3933e0e1 | 286 | |
c81bebd7 MM |
287 | #ifdef TARGET_REGNAMES |
288 | /* If the user desires alternate register names, copy in the alternate names | |
289 | now. */ | |
290 | if (TARGET_REGNAMES) | |
291 | bcopy ((char *)alt_reg_names, (char *)rs6000_reg_names, sizeof (rs6000_reg_names)); | |
292 | #endif | |
293 | ||
3933e0e1 MM |
294 | #ifdef SUBTARGET_OVERRIDE_OPTIONS |
295 | SUBTARGET_OVERRIDE_OPTIONS; | |
296 | #endif | |
5248c961 | 297 | } |
3cfa4909 MM |
298 | \f |
299 | /* Do anything needed at the start of the asm file. */ | |
300 | ||
301 | void | |
302 | rs6000_file_start (file, default_cpu) | |
303 | FILE *file; | |
304 | char *default_cpu; | |
305 | { | |
306 | int i; | |
307 | char buffer[80]; | |
308 | char *start = buffer; | |
309 | struct rs6000_cpu_select *ptr; | |
310 | ||
311 | if (flag_verbose_asm) | |
312 | { | |
313 | sprintf (buffer, "\n%s rs6000/powerpc options:", ASM_COMMENT_START); | |
314 | rs6000_select[0].string = default_cpu; | |
315 | ||
316 | for (i = 0; i < sizeof (rs6000_select) / sizeof (rs6000_select[0]); i++) | |
317 | { | |
318 | ptr = &rs6000_select[i]; | |
319 | if (ptr->string != (char *)0 && ptr->string[0] != '\0') | |
320 | { | |
321 | fprintf (file, "%s %s%s", start, ptr->name, ptr->string); | |
322 | start = ""; | |
323 | } | |
324 | } | |
325 | ||
326 | #ifdef USING_SVR4_H | |
327 | switch (rs6000_sdata) | |
328 | { | |
329 | case SDATA_NONE: fprintf (file, "%s -msdata=none", start); start = ""; break; | |
330 | case SDATA_DATA: fprintf (file, "%s -msdata=data", start); start = ""; break; | |
331 | case SDATA_SYSV: fprintf (file, "%s -msdata=sysv", start); start = ""; break; | |
332 | case SDATA_EABI: fprintf (file, "%s -msdata=eabi", start); start = ""; break; | |
333 | } | |
334 | ||
335 | if (rs6000_sdata && g_switch_value) | |
336 | { | |
337 | fprintf (file, "%s -G %d", start, g_switch_value); | |
338 | start = ""; | |
339 | } | |
340 | #endif | |
341 | ||
342 | if (*start == '\0') | |
343 | fputs ("\n", file); | |
344 | } | |
345 | } | |
346 | ||
24d304eb RK |
347 | \f |
348 | /* Create a CONST_DOUBLE from a string. */ | |
349 | ||
350 | struct rtx_def * | |
351 | rs6000_float_const (string, mode) | |
352 | char *string; | |
353 | enum machine_mode mode; | |
354 | { | |
355 | REAL_VALUE_TYPE value = REAL_VALUE_ATOF (string, mode); | |
356 | return immed_real_const_1 (value, mode); | |
357 | } | |
358 | ||
75814ad4 MM |
359 | \f |
360 | /* Create a CONST_DOUBLE like immed_double_const, except reverse the | |
361 | two parts of the constant if the target is little endian. */ | |
362 | ||
d679bebf RK |
363 | struct rtx_def * |
364 | rs6000_immed_double_const (i0, i1, mode) | |
75814ad4 MM |
365 | HOST_WIDE_INT i0, i1; |
366 | enum machine_mode mode; | |
367 | { | |
368 | if (! WORDS_BIG_ENDIAN) | |
369 | return immed_double_const (i1, i0, mode); | |
370 | ||
371 | return immed_double_const (i0, i1, mode); | |
372 | } | |
373 | ||
5248c961 | 374 | \f |
9878760c RK |
375 | /* Return non-zero if this function is known to have a null epilogue. */ |
376 | ||
377 | int | |
378 | direct_return () | |
379 | { | |
4697a36c MM |
380 | if (reload_completed) |
381 | { | |
382 | rs6000_stack_t *info = rs6000_stack_info (); | |
383 | ||
384 | if (info->first_gp_reg_save == 32 | |
385 | && info->first_fp_reg_save == 64 | |
386 | && !info->lr_save_p | |
1b4a2731 | 387 | && !info->cr_save_p |
4697a36c MM |
388 | && !info->push_p) |
389 | return 1; | |
390 | } | |
391 | ||
392 | return 0; | |
9878760c RK |
393 | } |
394 | ||
395 | /* Returns 1 always. */ | |
396 | ||
397 | int | |
398 | any_operand (op, mode) | |
399 | register rtx op; | |
400 | enum machine_mode mode; | |
401 | { | |
402 | return 1; | |
403 | } | |
404 | ||
b6c9286a MM |
405 | /* Returns 1 if op is the count register */ |
406 | int count_register_operand(op, mode) | |
407 | register rtx op; | |
408 | enum machine_mode mode; | |
409 | { | |
410 | if (GET_CODE (op) != REG) | |
411 | return 0; | |
412 | ||
413 | if (REGNO (op) == COUNT_REGISTER_REGNUM) | |
414 | return 1; | |
415 | ||
416 | if (REGNO (op) > FIRST_PSEUDO_REGISTER) | |
417 | return 1; | |
418 | ||
419 | return 0; | |
420 | } | |
421 | ||
802a0058 MM |
422 | /* Returns 1 if op is memory location for float/int conversions that masquerades |
423 | as a register. */ | |
424 | int fpmem_operand(op, mode) | |
425 | register rtx op; | |
426 | enum machine_mode mode; | |
427 | { | |
428 | if (GET_CODE (op) != REG) | |
429 | return 0; | |
430 | ||
431 | if (FPMEM_REGNO_P (REGNO (op))) | |
432 | return 1; | |
433 | ||
434 | #if 0 | |
435 | if (REGNO (op) > FIRST_PSEUDO_REGISTER) | |
436 | return 1; | |
437 | #endif | |
438 | ||
439 | return 0; | |
440 | } | |
441 | ||
9878760c RK |
442 | /* Return 1 if OP is a constant that can fit in a D field. */ |
443 | ||
444 | int | |
445 | short_cint_operand (op, mode) | |
446 | register rtx op; | |
447 | enum machine_mode mode; | |
448 | { | |
449 | return (GET_CODE (op) == CONST_INT | |
450 | && (unsigned) (INTVAL (op) + 0x8000) < 0x10000); | |
451 | } | |
452 | ||
453 | /* Similar for a unsigned D field. */ | |
454 | ||
455 | int | |
456 | u_short_cint_operand (op, mode) | |
457 | register rtx op; | |
458 | enum machine_mode mode; | |
459 | { | |
460 | return (GET_CODE (op) == CONST_INT && (INTVAL (op) & 0xffff0000) == 0); | |
461 | } | |
462 | ||
dcfedcd0 RK |
463 | /* Return 1 if OP is a CONST_INT that cannot fit in a signed D field. */ |
464 | ||
465 | int | |
466 | non_short_cint_operand (op, mode) | |
467 | register rtx op; | |
468 | enum machine_mode mode; | |
469 | { | |
470 | return (GET_CODE (op) == CONST_INT | |
471 | && (unsigned) (INTVAL (op) + 0x8000) >= 0x10000); | |
472 | } | |
473 | ||
9878760c RK |
474 | /* Returns 1 if OP is a register that is not special (i.e., not MQ, |
475 | ctr, or lr). */ | |
476 | ||
477 | int | |
cd2b37d9 | 478 | gpc_reg_operand (op, mode) |
9878760c RK |
479 | register rtx op; |
480 | enum machine_mode mode; | |
481 | { | |
482 | return (register_operand (op, mode) | |
802a0058 MM |
483 | && (GET_CODE (op) != REG |
484 | || (REGNO (op) >= 67 && !FPMEM_REGNO_P (REGNO (op))) | |
485 | || REGNO (op) < 64)); | |
9878760c RK |
486 | } |
487 | ||
488 | /* Returns 1 if OP is either a pseudo-register or a register denoting a | |
489 | CR field. */ | |
490 | ||
491 | int | |
492 | cc_reg_operand (op, mode) | |
493 | register rtx op; | |
494 | enum machine_mode mode; | |
495 | { | |
496 | return (register_operand (op, mode) | |
497 | && (GET_CODE (op) != REG | |
498 | || REGNO (op) >= FIRST_PSEUDO_REGISTER | |
499 | || CR_REGNO_P (REGNO (op)))); | |
500 | } | |
501 | ||
502 | /* Returns 1 if OP is either a constant integer valid for a D-field or a | |
503 | non-special register. If a register, it must be in the proper mode unless | |
504 | MODE is VOIDmode. */ | |
505 | ||
506 | int | |
507 | reg_or_short_operand (op, mode) | |
508 | register rtx op; | |
509 | enum machine_mode mode; | |
510 | { | |
f5a28898 | 511 | return short_cint_operand (op, mode) || gpc_reg_operand (op, mode); |
9878760c RK |
512 | } |
513 | ||
514 | /* Similar, except check if the negation of the constant would be valid for | |
515 | a D-field. */ | |
516 | ||
517 | int | |
518 | reg_or_neg_short_operand (op, mode) | |
519 | register rtx op; | |
520 | enum machine_mode mode; | |
521 | { | |
522 | if (GET_CODE (op) == CONST_INT) | |
523 | return CONST_OK_FOR_LETTER_P (INTVAL (op), 'P'); | |
524 | ||
cd2b37d9 | 525 | return gpc_reg_operand (op, mode); |
9878760c RK |
526 | } |
527 | ||
528 | /* Return 1 if the operand is either a register or an integer whose high-order | |
529 | 16 bits are zero. */ | |
530 | ||
531 | int | |
532 | reg_or_u_short_operand (op, mode) | |
533 | register rtx op; | |
534 | enum machine_mode mode; | |
535 | { | |
536 | if (GET_CODE (op) == CONST_INT | |
537 | && (INTVAL (op) & 0xffff0000) == 0) | |
538 | return 1; | |
539 | ||
cd2b37d9 | 540 | return gpc_reg_operand (op, mode); |
9878760c RK |
541 | } |
542 | ||
543 | /* Return 1 is the operand is either a non-special register or ANY | |
544 | constant integer. */ | |
545 | ||
546 | int | |
547 | reg_or_cint_operand (op, mode) | |
548 | register rtx op; | |
549 | enum machine_mode mode; | |
550 | { | |
cd2b37d9 | 551 | return GET_CODE (op) == CONST_INT || gpc_reg_operand (op, mode); |
9878760c RK |
552 | } |
553 | ||
766a866c MM |
554 | /* Return 1 if the operand is an operand that can be loaded via the GOT */ |
555 | ||
556 | int | |
557 | got_operand (op, mode) | |
558 | register rtx op; | |
559 | enum machine_mode mode; | |
560 | { | |
561 | return (GET_CODE (op) == SYMBOL_REF | |
562 | || GET_CODE (op) == CONST | |
563 | || GET_CODE (op) == LABEL_REF); | |
564 | } | |
565 | ||
4e74d8ec MM |
566 | /* Return the number of instructions it takes to form a constant in an |
567 | integer register. */ | |
568 | ||
569 | static int | |
570 | num_insns_constant_wide (value) | |
571 | HOST_WIDE_INT value; | |
572 | { | |
573 | /* signed constant loadable with {cal|addi} */ | |
574 | if (((unsigned HOST_WIDE_INT)value + 0x8000) < 0x10000) | |
575 | return 1; | |
576 | ||
577 | #if HOST_BITS_PER_WIDE_INT == 32 | |
578 | /* constant loadable with {cau|addis} */ | |
579 | else if ((value & 0xffff) == 0) | |
580 | return 1; | |
581 | ||
582 | #else | |
583 | /* constant loadable with {cau|addis} */ | |
584 | else if ((value & 0xffff) == 0 && (value & ~0xffffffff) == 0) | |
585 | return 1; | |
586 | ||
587 | else if (TARGET_64BIT) | |
588 | { | |
589 | HOST_WIDE_INT low = value & 0xffffffff; | |
590 | HOST_WIDE_INT high = value >> 32; | |
591 | ||
592 | if (high == 0 && (low & 0x80000000) == 0) | |
593 | return 2; | |
594 | ||
595 | else if (high == 0xffffffff && (low & 0x80000000) != 0) | |
596 | return 2; | |
597 | ||
598 | else if (!low) | |
599 | return num_insns_constant_wide (high) + 1; | |
600 | ||
601 | else | |
602 | return (num_insns_constant_wide (high) | |
603 | + num_insns_constant_low (low) + 1); | |
604 | } | |
605 | #endif | |
606 | ||
607 | else | |
608 | return 2; | |
609 | } | |
610 | ||
611 | int | |
612 | num_insns_constant (op, mode) | |
613 | rtx op; | |
614 | enum machine_mode mode; | |
615 | { | |
616 | if (mode != SImode && mode != DImode) | |
617 | abort (); | |
618 | ||
619 | if (GET_CODE (op) == CONST_INT) | |
620 | return num_insns_constant_wide (INTVAL (op)); | |
621 | ||
622 | else if (GET_CODE (op) == CONST_DOUBLE && TARGET_32BIT) | |
623 | return (num_insns_constant_wide (CONST_DOUBLE_LOW (op)) | |
624 | + num_insns_constant_wide (CONST_DOUBLE_HIGH (op))); | |
625 | ||
626 | else if (GET_CODE (op) == CONST_DOUBLE && TARGET_64BIT) | |
627 | { | |
628 | HOST_WIDE_INT low = CONST_DOUBLE_LOW (op); | |
629 | HOST_WIDE_INT high = CONST_DOUBLE_HIGH (op); | |
630 | ||
631 | if (high == 0 && (low & 0x80000000) == 0) | |
632 | return num_insns_constant_wide (low); | |
633 | ||
634 | else if (((high & 0xffffffff) == 0xffffffff) | |
635 | && ((low & 0x80000000) != 0)) | |
636 | return num_insns_constant_wide (low); | |
637 | ||
638 | else if (low == 0) | |
639 | return num_insns_constant_wide (high) + 1; | |
640 | ||
641 | else | |
642 | return (num_insns_constant_wide (high) | |
643 | + num_insns_constant_wide (low) + 1); | |
644 | } | |
645 | ||
646 | else | |
647 | abort (); | |
648 | } | |
649 | ||
6f2f8311 RK |
650 | /* Return 1 if the operand is a CONST_DOUBLE and it can be put into a register |
651 | with one instruction per word. We only do this if we can safely read | |
652 | CONST_DOUBLE_{LOW,HIGH}. */ | |
9878760c RK |
653 | |
654 | int | |
655 | easy_fp_constant (op, mode) | |
656 | register rtx op; | |
657 | register enum machine_mode mode; | |
658 | { | |
9878760c RK |
659 | if (GET_CODE (op) != CONST_DOUBLE |
660 | || GET_MODE (op) != mode | |
4e74d8ec | 661 | || (GET_MODE_CLASS (mode) != MODE_FLOAT && mode != DImode)) |
9878760c RK |
662 | return 0; |
663 | ||
b6c9286a | 664 | /* Consider all constants with -msoft-float to be easy */ |
4e74d8ec | 665 | if (TARGET_SOFT_FLOAT && mode != DImode) |
b6c9286a MM |
666 | return 1; |
667 | ||
042259f2 DE |
668 | if (mode == DFmode) |
669 | { | |
670 | long k[2]; | |
671 | REAL_VALUE_TYPE rv; | |
672 | ||
673 | REAL_VALUE_FROM_CONST_DOUBLE (rv, op); | |
674 | REAL_VALUE_TO_TARGET_DOUBLE (rv, k); | |
9878760c | 675 | |
4e74d8ec MM |
676 | return (num_insns_constant_wide ((HOST_WIDE_INT)k[0]) == 1 |
677 | && num_insns_constant_wide ((HOST_WIDE_INT)k[1]) == 1); | |
042259f2 | 678 | } |
4e74d8ec MM |
679 | |
680 | else if (mode == SFmode) | |
042259f2 DE |
681 | { |
682 | long l; | |
683 | REAL_VALUE_TYPE rv; | |
684 | ||
685 | REAL_VALUE_FROM_CONST_DOUBLE (rv, op); | |
686 | REAL_VALUE_TO_TARGET_SINGLE (rv, l); | |
9878760c | 687 | |
4e74d8ec | 688 | return num_insns_constant_wide (l) == 1; |
042259f2 | 689 | } |
4e74d8ec MM |
690 | |
691 | else if (mode == DImode && TARGET_32BIT) | |
692 | return num_insns_constant (op, DImode) == 2; | |
693 | ||
694 | else | |
695 | abort (); | |
9878760c | 696 | } |
8f75773e | 697 | |
b6c9286a MM |
698 | /* Return 1 if the operand is in volatile memory. Note that during the |
699 | RTL generation phase, memory_operand does not return TRUE for | |
700 | volatile memory references. So this function allows us to | |
701 | recognize volatile references where its safe. */ | |
702 | ||
703 | int | |
704 | volatile_mem_operand (op, mode) | |
705 | register rtx op; | |
706 | enum machine_mode mode; | |
707 | { | |
708 | if (GET_CODE (op) != MEM) | |
709 | return 0; | |
710 | ||
711 | if (!MEM_VOLATILE_P (op)) | |
712 | return 0; | |
713 | ||
714 | if (mode != GET_MODE (op)) | |
715 | return 0; | |
716 | ||
717 | if (reload_completed) | |
718 | return memory_operand (op, mode); | |
719 | ||
720 | if (reload_in_progress) | |
721 | return strict_memory_address_p (mode, XEXP (op, 0)); | |
722 | ||
723 | return memory_address_p (mode, XEXP (op, 0)); | |
724 | } | |
725 | ||
5b5040b9 | 726 | /* Return 1 if the operand is an offsettable memory address. */ |
914c2e77 RK |
727 | |
728 | int | |
5b5040b9 | 729 | offsettable_addr_operand (op, mode) |
914c2e77 RK |
730 | register rtx op; |
731 | enum machine_mode mode; | |
732 | { | |
8f75773e | 733 | return offsettable_address_p (reload_completed | reload_in_progress, |
5b5040b9 | 734 | mode, op); |
914c2e77 RK |
735 | } |
736 | ||
9878760c RK |
737 | /* Return 1 if the operand is either a floating-point register, a pseudo |
738 | register, or memory. */ | |
739 | ||
740 | int | |
741 | fp_reg_or_mem_operand (op, mode) | |
742 | register rtx op; | |
743 | enum machine_mode mode; | |
744 | { | |
745 | return (memory_operand (op, mode) | |
b6c9286a | 746 | || volatile_mem_operand (op, mode) |
9878760c RK |
747 | || (register_operand (op, mode) |
748 | && (GET_CODE (op) != REG | |
749 | || REGNO (op) >= FIRST_PSEUDO_REGISTER | |
750 | || FP_REGNO_P (REGNO (op))))); | |
751 | } | |
752 | ||
753 | /* Return 1 if the operand is either an easy FP constant (see above) or | |
754 | memory. */ | |
755 | ||
756 | int | |
757 | mem_or_easy_const_operand (op, mode) | |
758 | register rtx op; | |
759 | enum machine_mode mode; | |
760 | { | |
761 | return memory_operand (op, mode) || easy_fp_constant (op, mode); | |
762 | } | |
763 | ||
764 | /* Return 1 if the operand is either a non-special register or an item | |
765 | that can be used as the operand of an SI add insn. */ | |
766 | ||
767 | int | |
768 | add_operand (op, mode) | |
769 | register rtx op; | |
770 | enum machine_mode mode; | |
771 | { | |
772 | return (reg_or_short_operand (op, mode) | |
773 | || (GET_CODE (op) == CONST_INT && (INTVAL (op) & 0xffff) == 0)); | |
774 | } | |
775 | ||
dcfedcd0 RK |
776 | /* Return 1 if OP is a constant but not a valid add_operand. */ |
777 | ||
778 | int | |
779 | non_add_cint_operand (op, mode) | |
780 | register rtx op; | |
781 | enum machine_mode mode; | |
782 | { | |
783 | return (GET_CODE (op) == CONST_INT | |
784 | && (unsigned) (INTVAL (op) + 0x8000) >= 0x10000 | |
785 | && (INTVAL (op) & 0xffff) != 0); | |
786 | } | |
787 | ||
9878760c RK |
788 | /* Return 1 if the operand is a non-special register or a constant that |
789 | can be used as the operand of an OR or XOR insn on the RS/6000. */ | |
790 | ||
791 | int | |
792 | logical_operand (op, mode) | |
793 | register rtx op; | |
794 | enum machine_mode mode; | |
795 | { | |
cd2b37d9 | 796 | return (gpc_reg_operand (op, mode) |
9878760c RK |
797 | || (GET_CODE (op) == CONST_INT |
798 | && ((INTVAL (op) & 0xffff0000) == 0 | |
799 | || (INTVAL (op) & 0xffff) == 0))); | |
800 | } | |
801 | ||
dcfedcd0 RK |
802 | /* Return 1 if C is a constant that is not a logical operand (as |
803 | above). */ | |
804 | ||
805 | int | |
806 | non_logical_cint_operand (op, mode) | |
807 | register rtx op; | |
808 | enum machine_mode mode; | |
809 | { | |
810 | return (GET_CODE (op) == CONST_INT | |
811 | && (INTVAL (op) & 0xffff0000) != 0 | |
812 | && (INTVAL (op) & 0xffff) != 0); | |
813 | } | |
814 | ||
9878760c RK |
815 | /* Return 1 if C is a constant that can be encoded in a mask on the |
816 | RS/6000. It is if there are no more than two 1->0 or 0->1 transitions. | |
817 | Reject all ones and all zeros, since these should have been optimized | |
818 | away and confuse the making of MB and ME. */ | |
819 | ||
820 | int | |
821 | mask_constant (c) | |
822 | register int c; | |
823 | { | |
824 | int i; | |
825 | int last_bit_value; | |
826 | int transitions = 0; | |
827 | ||
828 | if (c == 0 || c == ~0) | |
829 | return 0; | |
830 | ||
831 | last_bit_value = c & 1; | |
832 | ||
833 | for (i = 1; i < 32; i++) | |
834 | if (((c >>= 1) & 1) != last_bit_value) | |
835 | last_bit_value ^= 1, transitions++; | |
836 | ||
837 | return transitions <= 2; | |
838 | } | |
839 | ||
840 | /* Return 1 if the operand is a constant that is a mask on the RS/6000. */ | |
841 | ||
842 | int | |
843 | mask_operand (op, mode) | |
844 | register rtx op; | |
845 | enum machine_mode mode; | |
846 | { | |
847 | return GET_CODE (op) == CONST_INT && mask_constant (INTVAL (op)); | |
848 | } | |
849 | ||
850 | /* Return 1 if the operand is either a non-special register or a | |
851 | constant that can be used as the operand of an RS/6000 logical AND insn. */ | |
852 | ||
853 | int | |
854 | and_operand (op, mode) | |
855 | register rtx op; | |
856 | enum machine_mode mode; | |
857 | { | |
858 | return (reg_or_short_operand (op, mode) | |
859 | || logical_operand (op, mode) | |
860 | || mask_operand (op, mode)); | |
861 | } | |
862 | ||
dcfedcd0 RK |
863 | /* Return 1 if the operand is a constant but not a valid operand for an AND |
864 | insn. */ | |
865 | ||
866 | int | |
867 | non_and_cint_operand (op, mode) | |
868 | register rtx op; | |
869 | enum machine_mode mode; | |
870 | { | |
871 | return GET_CODE (op) == CONST_INT && ! and_operand (op, mode); | |
872 | } | |
873 | ||
9878760c RK |
874 | /* Return 1 if the operand is a general register or memory operand. */ |
875 | ||
876 | int | |
877 | reg_or_mem_operand (op, mode) | |
878 | register rtx op; | |
879 | register enum machine_mode mode; | |
880 | { | |
b6c9286a MM |
881 | return (gpc_reg_operand (op, mode) |
882 | || memory_operand (op, mode) | |
883 | || volatile_mem_operand (op, mode)); | |
9878760c RK |
884 | } |
885 | ||
a7a813f7 RK |
886 | /* Return 1 if the operand is a general register or memory operand without |
887 | pre-inc or pre_dec which produces invalid form of PowerPC lwa | |
888 | instruction. */ | |
889 | ||
890 | int | |
891 | lwa_operand (op, mode) | |
892 | register rtx op; | |
893 | register enum machine_mode mode; | |
894 | { | |
895 | rtx inner = op; | |
896 | ||
897 | if (reload_completed && GET_CODE (inner) == SUBREG) | |
898 | inner = SUBREG_REG (inner); | |
899 | ||
900 | return gpc_reg_operand (inner, mode) | |
901 | || (memory_operand (inner, mode) | |
902 | && GET_CODE (XEXP (inner, 0)) != PRE_INC | |
903 | && GET_CODE (XEXP (inner, 0)) != PRE_DEC); | |
904 | } | |
905 | ||
9878760c RK |
906 | /* Return 1 if the operand, used inside a MEM, is a valid first argument |
907 | to CALL. This is a SYMBOL_REF or a pseudo-register, which will be | |
908 | forced to lr. */ | |
909 | ||
910 | int | |
911 | call_operand (op, mode) | |
912 | register rtx op; | |
913 | enum machine_mode mode; | |
914 | { | |
915 | if (mode != VOIDmode && GET_MODE (op) != mode) | |
916 | return 0; | |
917 | ||
918 | return (GET_CODE (op) == SYMBOL_REF | |
919 | || (GET_CODE (op) == REG && REGNO (op) >= FIRST_PSEUDO_REGISTER)); | |
920 | } | |
921 | ||
2af3d377 RK |
922 | |
923 | /* Return 1 if the operand is a SYMBOL_REF for a function known to be in | |
924 | this file. */ | |
925 | ||
926 | int | |
927 | current_file_function_operand (op, mode) | |
928 | register rtx op; | |
929 | enum machine_mode mode; | |
930 | { | |
931 | return (GET_CODE (op) == SYMBOL_REF | |
932 | && (SYMBOL_REF_FLAG (op) | |
933 | || op == XEXP (DECL_RTL (current_function_decl), 0))); | |
934 | } | |
935 | ||
936 | ||
9878760c RK |
937 | /* Return 1 if this operand is a valid input for a move insn. */ |
938 | ||
939 | int | |
940 | input_operand (op, mode) | |
941 | register rtx op; | |
942 | enum machine_mode mode; | |
943 | { | |
eb4e8003 | 944 | /* Memory is always valid. */ |
9878760c RK |
945 | if (memory_operand (op, mode)) |
946 | return 1; | |
947 | ||
eb4e8003 RK |
948 | /* For floating-point, easy constants are valid. */ |
949 | if (GET_MODE_CLASS (mode) == MODE_FLOAT | |
950 | && CONSTANT_P (op) | |
951 | && easy_fp_constant (op, mode)) | |
952 | return 1; | |
953 | ||
4e74d8ec MM |
954 | /* Allow any integer constant. */ |
955 | if (GET_MODE_CLASS (mode) == MODE_INT | |
956 | && (GET_CODE (op) == CONST_INT || GET_CODE (op) == CONST_DOUBLE)) | |
957 | return 1; | |
958 | ||
eb4e8003 RK |
959 | /* For floating-point or multi-word mode, the only remaining valid type |
960 | is a register. */ | |
9878760c RK |
961 | if (GET_MODE_CLASS (mode) == MODE_FLOAT |
962 | || GET_MODE_SIZE (mode) > UNITS_PER_WORD) | |
eb4e8003 | 963 | return register_operand (op, mode); |
9878760c | 964 | |
88fe15a1 RK |
965 | /* The only cases left are integral modes one word or smaller (we |
966 | do not get called for MODE_CC values). These can be in any | |
967 | register. */ | |
968 | if (register_operand (op, mode)) | |
a8b3aeda | 969 | return 1; |
88fe15a1 | 970 | |
84cf9dda | 971 | /* A SYMBOL_REF referring to the TOC is valid. */ |
7fec4abd | 972 | if (LEGITIMATE_CONSTANT_POOL_ADDRESS_P (op)) |
84cf9dda RK |
973 | return 1; |
974 | ||
b6c9286a MM |
975 | /* Windows NT allows SYMBOL_REFs and LABEL_REFs against the TOC |
976 | directly in the instruction stream */ | |
977 | if (DEFAULT_ABI == ABI_NT | |
978 | && (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF)) | |
979 | return 1; | |
980 | ||
88228c4b MM |
981 | /* V.4 allows SYMBOL_REFs and CONSTs that are in the small data region |
982 | to be valid. */ | |
c81bebd7 | 983 | if ((DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) |
88228c4b MM |
984 | && (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST) |
985 | && small_data_operand (op, Pmode)) | |
986 | return 1; | |
987 | ||
042259f2 | 988 | return 0; |
9878760c | 989 | } |
7509c759 MM |
990 | |
991 | /* Return 1 for an operand in small memory on V.4/eabi */ | |
992 | ||
993 | int | |
994 | small_data_operand (op, mode) | |
995 | rtx op; | |
996 | enum machine_mode mode; | |
997 | { | |
d9407988 | 998 | #ifdef TARGET_SDATA |
7509c759 MM |
999 | rtx sym_ref, const_part; |
1000 | ||
d9407988 | 1001 | if (rs6000_sdata == SDATA_NONE || rs6000_sdata == SDATA_DATA) |
a54d04b7 | 1002 | return 0; |
a54d04b7 | 1003 | |
c81bebd7 | 1004 | if (DEFAULT_ABI != ABI_V4 /* && DEFAULT_ABI != ABI_SOLARIS */) |
7509c759 MM |
1005 | return 0; |
1006 | ||
88228c4b MM |
1007 | if (GET_CODE (op) == SYMBOL_REF) |
1008 | sym_ref = op; | |
1009 | ||
1010 | else if (GET_CODE (op) != CONST | |
1011 | || GET_CODE (XEXP (op, 0)) != PLUS | |
1012 | || GET_CODE (XEXP (XEXP (op, 0), 0)) != SYMBOL_REF | |
1013 | || GET_CODE (XEXP (XEXP (op, 0), 1)) != CONST_INT) | |
7509c759 MM |
1014 | return 0; |
1015 | ||
88228c4b MM |
1016 | else |
1017 | sym_ref = XEXP (XEXP (op, 0), 0); | |
1018 | ||
1019 | if (*XSTR (sym_ref, 0) != '@') | |
7509c759 MM |
1020 | return 0; |
1021 | ||
1022 | return 1; | |
d9407988 MM |
1023 | |
1024 | #else | |
1025 | return 0; | |
1026 | #endif | |
7509c759 MM |
1027 | } |
1028 | ||
4697a36c MM |
1029 | \f |
1030 | /* Initialize a variable CUM of type CUMULATIVE_ARGS | |
1031 | for a call to a function whose data type is FNTYPE. | |
1032 | For a library call, FNTYPE is 0. | |
1033 | ||
1034 | For incoming args we set the number of arguments in the prototype large | |
1035 | so we never return an EXPR_LIST. */ | |
1036 | ||
1037 | void | |
1038 | init_cumulative_args (cum, fntype, libname, incoming) | |
1039 | CUMULATIVE_ARGS *cum; | |
1040 | tree fntype; | |
1041 | rtx libname; | |
1042 | int incoming; | |
1043 | { | |
1044 | static CUMULATIVE_ARGS zero_cumulative; | |
7509c759 | 1045 | enum rs6000_abi abi = DEFAULT_ABI; |
4697a36c MM |
1046 | |
1047 | *cum = zero_cumulative; | |
1048 | cum->words = 0; | |
1049 | cum->fregno = FP_ARG_MIN_REG; | |
1050 | cum->prototype = (fntype && TYPE_ARG_TYPES (fntype)); | |
7509c759 | 1051 | cum->call_cookie = CALL_NORMAL; |
4697a36c MM |
1052 | |
1053 | if (incoming) | |
1054 | { | |
1055 | cum->nargs_prototype = 1000; /* don't return an EXPR_LIST */ | |
c81bebd7 | 1056 | if (abi == ABI_V4 || abi == ABI_SOLARIS) |
4697a36c | 1057 | cum->varargs_offset = RS6000_VARARGS_OFFSET; |
4697a36c MM |
1058 | } |
1059 | ||
1060 | else if (cum->prototype) | |
1061 | cum->nargs_prototype = (list_length (TYPE_ARG_TYPES (fntype)) - 1 | |
1062 | + (TYPE_MODE (TREE_TYPE (fntype)) == BLKmode | |
1063 | || RETURN_IN_MEMORY (TREE_TYPE (fntype)))); | |
1064 | ||
1065 | else | |
1066 | cum->nargs_prototype = 0; | |
1067 | ||
1068 | cum->orig_nargs = cum->nargs_prototype; | |
7509c759 MM |
1069 | |
1070 | /* Check for DLL import functions */ | |
1071 | if (abi == ABI_NT | |
1072 | && fntype | |
1073 | && lookup_attribute ("dllimport", TYPE_ATTRIBUTES (fntype))) | |
1074 | cum->call_cookie = CALL_NT_DLLIMPORT; | |
1075 | ||
6a4cee5f MM |
1076 | /* Also check for longcall's */ |
1077 | else if (fntype && lookup_attribute ("longcall", TYPE_ATTRIBUTES (fntype))) | |
1078 | cum->call_cookie = CALL_LONG; | |
1079 | ||
4697a36c MM |
1080 | if (TARGET_DEBUG_ARG) |
1081 | { | |
1082 | fprintf (stderr, "\ninit_cumulative_args:"); | |
1083 | if (fntype) | |
1084 | { | |
1085 | tree ret_type = TREE_TYPE (fntype); | |
1086 | fprintf (stderr, " ret code = %s,", | |
1087 | tree_code_name[ (int)TREE_CODE (ret_type) ]); | |
1088 | } | |
1089 | ||
c81bebd7 | 1090 | if ((abi == ABI_V4 || abi == ABI_SOLARIS) && incoming) |
4697a36c | 1091 | fprintf (stderr, " varargs = %d, ", cum->varargs_offset); |
7509c759 | 1092 | |
6a4cee5f | 1093 | if (cum->call_cookie & CALL_NT_DLLIMPORT) |
7509c759 | 1094 | fprintf (stderr, " dllimport,"); |
4697a36c | 1095 | |
6a4cee5f MM |
1096 | if (cum->call_cookie & CALL_LONG) |
1097 | fprintf (stderr, " longcall,"); | |
1098 | ||
4697a36c MM |
1099 | fprintf (stderr, " proto = %d, nargs = %d\n", |
1100 | cum->prototype, cum->nargs_prototype); | |
1101 | } | |
1102 | } | |
1103 | \f | |
b6c9286a MM |
1104 | /* If defined, a C expression that gives the alignment boundary, in bits, |
1105 | of an argument with the specified mode and type. If it is not defined, | |
1106 | PARM_BOUNDARY is used for all arguments. | |
1107 | ||
e1f83b4d MM |
1108 | Windows NT wants anything >= 8 bytes to be double word aligned. |
1109 | ||
1110 | V.4 wants long longs to be double word aligned. */ | |
b6c9286a MM |
1111 | |
1112 | int | |
1113 | function_arg_boundary (mode, type) | |
1114 | enum machine_mode mode; | |
1115 | tree type; | |
1116 | { | |
c81bebd7 | 1117 | if ((DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) && mode == DImode) |
e1f83b4d MM |
1118 | return 64; |
1119 | ||
b6c9286a MM |
1120 | if (DEFAULT_ABI != ABI_NT || TARGET_64BIT) |
1121 | return PARM_BOUNDARY; | |
1122 | ||
1123 | if (mode != BLKmode) | |
1124 | return (GET_MODE_SIZE (mode)) >= 8 ? 64 : 32; | |
1125 | ||
1126 | return (int_size_in_bytes (type) >= 8) ? 64 : 32; | |
1127 | } | |
1128 | \f | |
4697a36c MM |
1129 | /* Update the data in CUM to advance over an argument |
1130 | of mode MODE and data type TYPE. | |
1131 | (TYPE is null for libcalls where that information may not be available.) */ | |
1132 | ||
1133 | void | |
1134 | function_arg_advance (cum, mode, type, named) | |
1135 | CUMULATIVE_ARGS *cum; | |
1136 | enum machine_mode mode; | |
1137 | tree type; | |
1138 | int named; | |
1139 | { | |
b6c9286a MM |
1140 | int align = ((cum->words & 1) != 0 && function_arg_boundary (mode, type) == 64) ? 1 : 0; |
1141 | cum->words += align; | |
4697a36c MM |
1142 | cum->nargs_prototype--; |
1143 | ||
c81bebd7 | 1144 | if (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) |
4697a36c MM |
1145 | { |
1146 | /* Long longs must not be split between registers and stack */ | |
1147 | if ((GET_MODE_CLASS (mode) != MODE_FLOAT || TARGET_SOFT_FLOAT) | |
1148 | && type && !AGGREGATE_TYPE_P (type) | |
1149 | && cum->words < GP_ARG_NUM_REG | |
1150 | && cum->words + RS6000_ARG_SIZE (mode, type, named) > GP_ARG_NUM_REG) | |
1151 | { | |
1152 | cum->words = GP_ARG_NUM_REG; | |
1153 | } | |
1154 | ||
1155 | /* Aggregates get passed as pointers */ | |
1156 | if (type && AGGREGATE_TYPE_P (type)) | |
1157 | cum->words++; | |
1158 | ||
1159 | /* Floats go in registers, & don't occupy space in the GP registers | |
1160 | like they do for AIX unless software floating point. */ | |
1161 | else if (GET_MODE_CLASS (mode) == MODE_FLOAT | |
1162 | && TARGET_HARD_FLOAT | |
1163 | && cum->fregno <= FP_ARG_V4_MAX_REG) | |
1164 | cum->fregno++; | |
1165 | ||
1166 | else | |
1167 | cum->words += RS6000_ARG_SIZE (mode, type, 1); | |
1168 | } | |
1169 | else | |
4697a36c MM |
1170 | if (named) |
1171 | { | |
1172 | cum->words += RS6000_ARG_SIZE (mode, type, named); | |
1173 | if (GET_MODE_CLASS (mode) == MODE_FLOAT && TARGET_HARD_FLOAT) | |
1174 | cum->fregno++; | |
1175 | } | |
1176 | ||
1177 | if (TARGET_DEBUG_ARG) | |
1178 | fprintf (stderr, | |
b6c9286a MM |
1179 | "function_adv: words = %2d, fregno = %2d, nargs = %4d, proto = %d, mode = %4s, named = %d, align = %d\n", |
1180 | cum->words, cum->fregno, cum->nargs_prototype, cum->prototype, GET_MODE_NAME (mode), named, align); | |
4697a36c MM |
1181 | } |
1182 | \f | |
1183 | /* Determine where to put an argument to a function. | |
1184 | Value is zero to push the argument on the stack, | |
1185 | or a hard register in which to store the argument. | |
1186 | ||
1187 | MODE is the argument's machine mode. | |
1188 | TYPE is the data type of the argument (as a tree). | |
1189 | This is null for libcalls where that information may | |
1190 | not be available. | |
1191 | CUM is a variable of type CUMULATIVE_ARGS which gives info about | |
1192 | the preceding args and about the function being called. | |
1193 | NAMED is nonzero if this argument is a named parameter | |
1194 | (otherwise it is an extra parameter matching an ellipsis). | |
1195 | ||
1196 | On RS/6000 the first eight words of non-FP are normally in registers | |
1197 | and the rest are pushed. Under AIX, the first 13 FP args are in registers. | |
1198 | Under V.4, the first 8 FP args are in registers. | |
1199 | ||
1200 | If this is floating-point and no prototype is specified, we use | |
1201 | both an FP and integer register (or possibly FP reg and stack). Library | |
1202 | functions (when TYPE is zero) always have the proper types for args, | |
1203 | so we can pass the FP value just in one register. emit_library_function | |
1204 | doesn't support EXPR_LIST anyway. */ | |
1205 | ||
1206 | struct rtx_def * | |
1207 | function_arg (cum, mode, type, named) | |
1208 | CUMULATIVE_ARGS *cum; | |
1209 | enum machine_mode mode; | |
1210 | tree type; | |
1211 | int named; | |
1212 | { | |
b6c9286a MM |
1213 | int align = ((cum->words & 1) != 0 && function_arg_boundary (mode, type) == 64) ? 1 : 0; |
1214 | int align_words = cum->words + align; | |
1215 | ||
4697a36c MM |
1216 | if (TARGET_DEBUG_ARG) |
1217 | fprintf (stderr, | |
b6c9286a MM |
1218 | "function_arg: words = %2d, fregno = %2d, nargs = %4d, proto = %d, mode = %4s, named = %d, align = %d\n", |
1219 | cum->words, cum->fregno, cum->nargs_prototype, cum->prototype, GET_MODE_NAME (mode), named, align); | |
4697a36c MM |
1220 | |
1221 | /* Return a marker to indicate whether CR1 needs to set or clear the bit that V.4 | |
1222 | uses to say fp args were passed in registers. Assume that we don't need the | |
1223 | marker for software floating point, or compiler generated library calls. */ | |
1224 | if (mode == VOIDmode) | |
1225 | { | |
7509c759 MM |
1226 | enum rs6000_abi abi = DEFAULT_ABI; |
1227 | ||
c81bebd7 | 1228 | if ((abi == ABI_V4 || abi == ABI_SOLARIS) |
7509c759 MM |
1229 | && TARGET_HARD_FLOAT |
1230 | && cum->nargs_prototype < 0 | |
4697a36c | 1231 | && type && (cum->prototype || TARGET_NO_PROTOTYPE)) |
7509c759 | 1232 | { |
6a4cee5f MM |
1233 | return GEN_INT (cum->call_cookie |
1234 | | ((cum->fregno == FP_ARG_MIN_REG) | |
1235 | ? CALL_V4_SET_FP_ARGS | |
1236 | : CALL_V4_CLEAR_FP_ARGS)); | |
7509c759 | 1237 | } |
4697a36c | 1238 | |
7509c759 | 1239 | return GEN_INT (cum->call_cookie); |
4697a36c MM |
1240 | } |
1241 | ||
1242 | if (!named) | |
1243 | { | |
c81bebd7 | 1244 | if (DEFAULT_ABI != ABI_V4 && DEFAULT_ABI != ABI_SOLARIS) |
4697a36c MM |
1245 | return NULL_RTX; |
1246 | } | |
1247 | ||
1248 | if (type && TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST) | |
1249 | return NULL_RTX; | |
1250 | ||
1251 | if (USE_FP_FOR_ARG_P (*cum, mode, type)) | |
1252 | { | |
1253 | if ((cum->nargs_prototype > 0) | |
c81bebd7 MM |
1254 | || DEFAULT_ABI == ABI_V4 /* V.4 never passes FP values in GP registers */ |
1255 | || DEFAULT_ABI == ABI_SOLARIS | |
4697a36c MM |
1256 | || !type) |
1257 | return gen_rtx (REG, mode, cum->fregno); | |
1258 | ||
1259 | return gen_rtx (EXPR_LIST, VOIDmode, | |
b6c9286a MM |
1260 | ((align_words < GP_ARG_NUM_REG) |
1261 | ? gen_rtx (REG, mode, GP_ARG_MIN_REG + align_words) | |
4697a36c MM |
1262 | : NULL_RTX), |
1263 | gen_rtx (REG, mode, cum->fregno)); | |
1264 | } | |
1265 | ||
4697a36c | 1266 | /* Long longs won't be split between register and stack */ |
c81bebd7 | 1267 | else if ((DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) && |
b6c9286a | 1268 | align_words + RS6000_ARG_SIZE (mode, type, named) > GP_ARG_NUM_REG) |
4697a36c MM |
1269 | { |
1270 | return NULL_RTX; | |
1271 | } | |
4697a36c | 1272 | |
b6c9286a MM |
1273 | else if (align_words < GP_ARG_NUM_REG) |
1274 | return gen_rtx (REG, mode, GP_ARG_MIN_REG + align_words); | |
4697a36c MM |
1275 | |
1276 | return NULL_RTX; | |
1277 | } | |
1278 | \f | |
1279 | /* For an arg passed partly in registers and partly in memory, | |
1280 | this is the number of registers used. | |
1281 | For args passed entirely in registers or entirely in memory, zero. */ | |
1282 | ||
1283 | int | |
1284 | function_arg_partial_nregs (cum, mode, type, named) | |
1285 | CUMULATIVE_ARGS *cum; | |
1286 | enum machine_mode mode; | |
1287 | tree type; | |
1288 | int named; | |
1289 | { | |
1290 | if (! named) | |
1291 | return 0; | |
1292 | ||
c81bebd7 | 1293 | if (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) |
4697a36c | 1294 | return 0; |
4697a36c MM |
1295 | |
1296 | if (USE_FP_FOR_ARG_P (*cum, mode, type)) | |
1297 | { | |
1298 | if (cum->nargs_prototype >= 0) | |
1299 | return 0; | |
1300 | } | |
1301 | ||
1302 | if (cum->words < GP_ARG_NUM_REG | |
1303 | && GP_ARG_NUM_REG < (cum->words + RS6000_ARG_SIZE (mode, type, named))) | |
1304 | { | |
1305 | int ret = GP_ARG_NUM_REG - cum->words; | |
1306 | if (ret && TARGET_DEBUG_ARG) | |
1307 | fprintf (stderr, "function_arg_partial_nregs: %d\n", ret); | |
1308 | ||
1309 | return ret; | |
1310 | } | |
1311 | ||
1312 | return 0; | |
1313 | } | |
1314 | \f | |
1315 | /* A C expression that indicates when an argument must be passed by | |
1316 | reference. If nonzero for an argument, a copy of that argument is | |
1317 | made in memory and a pointer to the argument is passed instead of | |
1318 | the argument itself. The pointer is passed in whatever way is | |
1319 | appropriate for passing a pointer to that type. | |
1320 | ||
1321 | Under V.4, structures and unions are passed by reference. */ | |
1322 | ||
1323 | int | |
1324 | function_arg_pass_by_reference (cum, mode, type, named) | |
1325 | CUMULATIVE_ARGS *cum; | |
1326 | enum machine_mode mode; | |
1327 | tree type; | |
1328 | int named; | |
1329 | { | |
c81bebd7 MM |
1330 | if ((DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) |
1331 | && type && AGGREGATE_TYPE_P (type)) | |
4697a36c MM |
1332 | { |
1333 | if (TARGET_DEBUG_ARG) | |
1334 | fprintf (stderr, "function_arg_pass_by_reference: aggregate\n"); | |
1335 | ||
1336 | return 1; | |
1337 | } | |
4697a36c MM |
1338 | |
1339 | return 0; | |
1340 | } | |
1341 | ||
1342 | \f | |
1343 | /* Perform any needed actions needed for a function that is receiving a | |
1344 | variable number of arguments. | |
1345 | ||
1346 | CUM is as above. | |
1347 | ||
1348 | MODE and TYPE are the mode and type of the current parameter. | |
1349 | ||
1350 | PRETEND_SIZE is a variable that should be set to the amount of stack | |
1351 | that must be pushed by the prolog to pretend that our caller pushed | |
1352 | it. | |
1353 | ||
1354 | Normally, this macro will push all remaining incoming registers on the | |
1355 | stack and set PRETEND_SIZE to the length of the registers pushed. */ | |
1356 | ||
1357 | void | |
1358 | setup_incoming_varargs (cum, mode, type, pretend_size, no_rtl) | |
1359 | CUMULATIVE_ARGS *cum; | |
1360 | enum machine_mode mode; | |
1361 | tree type; | |
1362 | int *pretend_size; | |
1363 | int no_rtl; | |
1364 | ||
1365 | { | |
1366 | rtx save_area = virtual_incoming_args_rtx; | |
1367 | int reg_size = (TARGET_64BIT) ? 8 : 4; | |
1368 | ||
1369 | if (TARGET_DEBUG_ARG) | |
1370 | fprintf (stderr, | |
1371 | "setup_vararg: words = %2d, fregno = %2d, nargs = %4d, proto = %d, mode = %4s, no_rtl= %d\n", | |
1372 | cum->words, cum->fregno, cum->nargs_prototype, cum->prototype, GET_MODE_NAME (mode), no_rtl); | |
1373 | ||
c81bebd7 | 1374 | if ((DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) && !no_rtl) |
4697a36c MM |
1375 | { |
1376 | rs6000_sysv_varargs_p = 1; | |
1377 | save_area = plus_constant (frame_pointer_rtx, RS6000_VARARGS_OFFSET); | |
1378 | } | |
4697a36c MM |
1379 | |
1380 | if (cum->words < 8) | |
1381 | { | |
1382 | int first_reg_offset = cum->words; | |
1383 | ||
1384 | if (MUST_PASS_IN_STACK (mode, type)) | |
1385 | first_reg_offset += RS6000_ARG_SIZE (TYPE_MODE (type), type, 1); | |
1386 | ||
1387 | if (first_reg_offset > GP_ARG_NUM_REG) | |
1388 | first_reg_offset = GP_ARG_NUM_REG; | |
1389 | ||
1390 | if (!no_rtl && first_reg_offset != GP_ARG_NUM_REG) | |
1391 | move_block_from_reg | |
1392 | (GP_ARG_MIN_REG + first_reg_offset, | |
1393 | gen_rtx (MEM, BLKmode, | |
1394 | plus_constant (save_area, first_reg_offset * reg_size)), | |
1395 | GP_ARG_NUM_REG - first_reg_offset, | |
1396 | (GP_ARG_NUM_REG - first_reg_offset) * UNITS_PER_WORD); | |
1397 | ||
1398 | *pretend_size = (GP_ARG_NUM_REG - first_reg_offset) * UNITS_PER_WORD; | |
1399 | } | |
1400 | ||
4697a36c | 1401 | /* Save FP registers if needed. */ |
c81bebd7 | 1402 | if ((DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) && TARGET_HARD_FLOAT && !no_rtl) |
4697a36c MM |
1403 | { |
1404 | int fregno = cum->fregno; | |
1405 | int num_fp_reg = FP_ARG_V4_MAX_REG + 1 - fregno; | |
1406 | ||
1407 | if (num_fp_reg >= 0) | |
1408 | { | |
1409 | rtx cr1 = gen_rtx (REG, CCmode, 69); | |
1410 | rtx lab = gen_label_rtx (); | |
1411 | int off = (GP_ARG_NUM_REG * reg_size) + ((fregno - FP_ARG_MIN_REG) * 8); | |
1412 | ||
1413 | emit_jump_insn (gen_rtx (SET, VOIDmode, | |
1414 | pc_rtx, | |
1415 | gen_rtx (IF_THEN_ELSE, VOIDmode, | |
1416 | gen_rtx (NE, VOIDmode, cr1, const0_rtx), | |
1417 | gen_rtx (LABEL_REF, VOIDmode, lab), | |
1418 | pc_rtx))); | |
1419 | ||
1420 | while ( num_fp_reg-- >= 0) | |
1421 | { | |
1422 | emit_move_insn (gen_rtx (MEM, DFmode, plus_constant (save_area, off)), | |
1423 | gen_rtx (REG, DFmode, fregno++)); | |
1424 | off += 8; | |
1425 | } | |
1426 | ||
1427 | emit_label (lab); | |
1428 | } | |
1429 | } | |
4697a36c MM |
1430 | } |
1431 | \f | |
1432 | /* If defined, is a C expression that produces the machine-specific | |
1433 | code for a call to `__builtin_saveregs'. This code will be moved | |
1434 | to the very beginning of the function, before any parameter access | |
1435 | are made. The return value of this function should be an RTX that | |
1436 | contains the value to use as the return of `__builtin_saveregs'. | |
1437 | ||
1438 | The argument ARGS is a `tree_list' containing the arguments that | |
1439 | were passed to `__builtin_saveregs'. | |
1440 | ||
1441 | If this macro is not defined, the compiler will output an ordinary | |
1442 | call to the library function `__builtin_saveregs'. | |
1443 | ||
1444 | On the Power/PowerPC return the address of the area on the stack | |
1445 | used to hold arguments. Under AIX, this includes the 8 word register | |
1446 | save area. Under V.4 this does not. */ | |
1447 | ||
1448 | struct rtx_def * | |
1449 | expand_builtin_saveregs (args) | |
1450 | tree args; | |
1451 | { | |
1452 | return virtual_incoming_args_rtx; | |
1453 | } | |
1454 | ||
5b5040b9 RK |
1455 | \f |
1456 | /* Generate a memory reference for expand_block_move, copying volatile, | |
1457 | and other bits from an original memory reference. */ | |
1458 | ||
1459 | static rtx | |
1460 | expand_block_move_mem (mode, addr, orig_mem) | |
1461 | enum machine_mode mode; | |
1462 | rtx addr; | |
1463 | rtx orig_mem; | |
1464 | { | |
1465 | rtx mem = gen_rtx (MEM, mode, addr); | |
b6c9286a MM |
1466 | |
1467 | RTX_UNCHANGING_P (mem) = RTX_UNCHANGING_P (orig_mem); | |
5b5040b9 RK |
1468 | MEM_VOLATILE_P (mem) = MEM_VOLATILE_P (orig_mem); |
1469 | MEM_IN_STRUCT_P (mem) = MEM_IN_STRUCT_P (orig_mem); | |
b6c9286a MM |
1470 | #ifdef MEM_UNALIGNED_P |
1471 | MEM_UNALIGNED_P (mem) = MEM_UNALIGNED_P (orig_mem); | |
1472 | #endif | |
5b5040b9 RK |
1473 | return mem; |
1474 | } | |
1475 | ||
7e69e155 MM |
1476 | /* Expand a block move operation, and return 1 if successful. Return 0 |
1477 | if we should let the compiler generate normal code. | |
1478 | ||
1479 | operands[0] is the destination | |
1480 | operands[1] is the source | |
1481 | operands[2] is the length | |
1482 | operands[3] is the alignment */ | |
1483 | ||
3933e0e1 MM |
1484 | #define MAX_MOVE_REG 4 |
1485 | ||
7e69e155 MM |
1486 | int |
1487 | expand_block_move (operands) | |
1488 | rtx operands[]; | |
1489 | { | |
b6c9286a MM |
1490 | rtx orig_dest = operands[0]; |
1491 | rtx orig_src = operands[1]; | |
7e69e155 | 1492 | rtx bytes_rtx = operands[2]; |
7e69e155 | 1493 | rtx align_rtx = operands[3]; |
3933e0e1 | 1494 | int constp = (GET_CODE (bytes_rtx) == CONST_INT); |
7e69e155 | 1495 | int align = XINT (align_rtx, 0); |
3933e0e1 MM |
1496 | int bytes; |
1497 | int offset; | |
1498 | int num_reg; | |
1499 | int i; | |
7e69e155 MM |
1500 | rtx src_reg; |
1501 | rtx dest_reg; | |
3933e0e1 MM |
1502 | rtx src_addr; |
1503 | rtx dest_addr; | |
7e69e155 | 1504 | rtx tmp_reg; |
3933e0e1 | 1505 | rtx stores[MAX_MOVE_REG]; |
7e69e155 MM |
1506 | int move_bytes; |
1507 | ||
3933e0e1 MM |
1508 | /* If this is not a fixed size move, just call memcpy */ |
1509 | if (!constp) | |
1510 | return 0; | |
1511 | ||
7e69e155 | 1512 | /* Anything to move? */ |
3933e0e1 MM |
1513 | bytes = INTVAL (bytes_rtx); |
1514 | if (bytes <= 0) | |
7e69e155 MM |
1515 | return 1; |
1516 | ||
3933e0e1 MM |
1517 | /* Don't support real large moves. If string instructions are not used, |
1518 | then don't generate more than 8 loads. */ | |
1519 | if (TARGET_STRING) | |
1520 | { | |
1cab3be1 | 1521 | if (bytes > 4*8) |
3933e0e1 MM |
1522 | return 0; |
1523 | } | |
1524 | else if (!STRICT_ALIGNMENT) | |
1525 | { | |
1526 | if (bytes > 4*8) | |
1527 | return 0; | |
1528 | } | |
1529 | else if (bytes > 8*align) | |
7e69e155 MM |
1530 | return 0; |
1531 | ||
1532 | /* Move the address into scratch registers. */ | |
b6c9286a MM |
1533 | dest_reg = copy_addr_to_reg (XEXP (orig_dest, 0)); |
1534 | src_reg = copy_addr_to_reg (XEXP (orig_src, 0)); | |
7e69e155 | 1535 | |
3933e0e1 | 1536 | if (TARGET_STRING) /* string instructions are available */ |
7e69e155 | 1537 | { |
3933e0e1 | 1538 | for ( ; bytes > 0; bytes -= move_bytes) |
7e69e155 | 1539 | { |
3933e0e1 MM |
1540 | if (bytes > 24 /* move up to 32 bytes at a time */ |
1541 | && !fixed_regs[5] | |
1542 | && !fixed_regs[6] | |
1543 | && !fixed_regs[7] | |
1544 | && !fixed_regs[8] | |
1545 | && !fixed_regs[9] | |
1546 | && !fixed_regs[10] | |
1547 | && !fixed_regs[11] | |
1548 | && !fixed_regs[12]) | |
1549 | { | |
1550 | move_bytes = (bytes > 32) ? 32 : bytes; | |
b6c9286a MM |
1551 | emit_insn (gen_movstrsi_8reg (expand_block_move_mem (BLKmode, dest_reg, orig_dest), |
1552 | expand_block_move_mem (BLKmode, src_reg, orig_src), | |
3933e0e1 | 1553 | GEN_INT ((move_bytes == 32) ? 0 : move_bytes), |
4c64a852 | 1554 | align_rtx)); |
3933e0e1 MM |
1555 | } |
1556 | else if (bytes > 16 /* move up to 24 bytes at a time */ | |
1557 | && !fixed_regs[7] | |
1558 | && !fixed_regs[8] | |
1559 | && !fixed_regs[9] | |
1560 | && !fixed_regs[10] | |
1561 | && !fixed_regs[11] | |
1562 | && !fixed_regs[12]) | |
1563 | { | |
1564 | move_bytes = (bytes > 24) ? 24 : bytes; | |
b6c9286a MM |
1565 | emit_insn (gen_movstrsi_6reg (expand_block_move_mem (BLKmode, dest_reg, orig_dest), |
1566 | expand_block_move_mem (BLKmode, src_reg, orig_src), | |
3933e0e1 | 1567 | GEN_INT (move_bytes), |
4c64a852 | 1568 | align_rtx)); |
3933e0e1 MM |
1569 | } |
1570 | else if (bytes > 8 /* move up to 16 bytes at a time */ | |
1571 | && !fixed_regs[9] | |
1572 | && !fixed_regs[10] | |
1573 | && !fixed_regs[11] | |
1574 | && !fixed_regs[12]) | |
1575 | { | |
1576 | move_bytes = (bytes > 16) ? 16 : bytes; | |
b6c9286a MM |
1577 | emit_insn (gen_movstrsi_4reg (expand_block_move_mem (BLKmode, dest_reg, orig_dest), |
1578 | expand_block_move_mem (BLKmode, src_reg, orig_src), | |
3933e0e1 | 1579 | GEN_INT (move_bytes), |
4c64a852 | 1580 | align_rtx)); |
3933e0e1 | 1581 | } |
d679bebf | 1582 | else if (bytes > 4 && !TARGET_64BIT) |
3933e0e1 MM |
1583 | { /* move up to 8 bytes at a time */ |
1584 | move_bytes = (bytes > 8) ? 8 : bytes; | |
b6c9286a MM |
1585 | emit_insn (gen_movstrsi_2reg (expand_block_move_mem (BLKmode, dest_reg, orig_dest), |
1586 | expand_block_move_mem (BLKmode, src_reg, orig_src), | |
3933e0e1 | 1587 | GEN_INT (move_bytes), |
4c64a852 | 1588 | align_rtx)); |
3933e0e1 MM |
1589 | } |
1590 | else if (bytes >= 4 && (align >= 4 || !STRICT_ALIGNMENT)) | |
1591 | { /* move 4 bytes */ | |
1592 | move_bytes = 4; | |
1593 | tmp_reg = gen_reg_rtx (SImode); | |
b6c9286a MM |
1594 | emit_move_insn (tmp_reg, expand_block_move_mem (SImode, src_reg, orig_src)); |
1595 | emit_move_insn (expand_block_move_mem (SImode, dest_reg, orig_dest), tmp_reg); | |
3933e0e1 MM |
1596 | } |
1597 | else if (bytes == 2 && (align >= 2 || !STRICT_ALIGNMENT)) | |
1598 | { /* move 2 bytes */ | |
1599 | move_bytes = 2; | |
1600 | tmp_reg = gen_reg_rtx (HImode); | |
b6c9286a MM |
1601 | emit_move_insn (tmp_reg, expand_block_move_mem (HImode, src_reg, orig_src)); |
1602 | emit_move_insn (expand_block_move_mem (HImode, dest_reg, orig_dest), tmp_reg); | |
3933e0e1 MM |
1603 | } |
1604 | else if (bytes == 1) /* move 1 byte */ | |
1605 | { | |
1606 | move_bytes = 1; | |
1607 | tmp_reg = gen_reg_rtx (QImode); | |
b6c9286a MM |
1608 | emit_move_insn (tmp_reg, expand_block_move_mem (QImode, src_reg, orig_src)); |
1609 | emit_move_insn (expand_block_move_mem (QImode, dest_reg, orig_dest), tmp_reg); | |
3933e0e1 MM |
1610 | } |
1611 | else | |
1612 | { /* move up to 4 bytes at a time */ | |
1613 | move_bytes = (bytes > 4) ? 4 : bytes; | |
b6c9286a MM |
1614 | emit_insn (gen_movstrsi_1reg (expand_block_move_mem (BLKmode, dest_reg, orig_dest), |
1615 | expand_block_move_mem (BLKmode, src_reg, orig_src), | |
3933e0e1 | 1616 | GEN_INT (move_bytes), |
4c64a852 | 1617 | align_rtx)); |
3933e0e1 | 1618 | } |
4c64a852 | 1619 | |
015892ee RK |
1620 | if (bytes > move_bytes) |
1621 | { | |
1622 | emit_insn (gen_addsi3 (src_reg, src_reg, GEN_INT (move_bytes))); | |
1623 | emit_insn (gen_addsi3 (dest_reg, dest_reg, GEN_INT (move_bytes))); | |
1624 | } | |
4c64a852 | 1625 | } |
3933e0e1 MM |
1626 | } |
1627 | ||
1628 | else /* string instructions not available */ | |
1629 | { | |
1630 | num_reg = offset = 0; | |
1631 | for ( ; bytes > 0; (bytes -= move_bytes), (offset += move_bytes)) | |
7e69e155 | 1632 | { |
3933e0e1 MM |
1633 | /* Calculate the correct offset for src/dest */ |
1634 | if (offset == 0) | |
7e69e155 | 1635 | { |
3933e0e1 MM |
1636 | src_addr = src_reg; |
1637 | dest_addr = dest_reg; | |
1638 | } | |
1639 | else | |
1640 | { | |
1641 | src_addr = gen_rtx (PLUS, Pmode, src_reg, GEN_INT (offset)); | |
1642 | dest_addr = gen_rtx (PLUS, Pmode, dest_reg, GEN_INT (offset)); | |
1643 | } | |
1644 | ||
1645 | /* Generate the appropriate load and store, saving the stores for later */ | |
b6c9286a MM |
1646 | if (bytes >= 8 && TARGET_64BIT && (align >= 8 || !STRICT_ALIGNMENT)) |
1647 | { | |
1648 | move_bytes = 8; | |
1649 | tmp_reg = gen_reg_rtx (DImode); | |
1650 | emit_insn (gen_movdi (tmp_reg, expand_block_move_mem (DImode, src_addr, orig_src))); | |
1651 | stores[ num_reg++ ] = gen_movdi (expand_block_move_mem (DImode, dest_addr, orig_dest), tmp_reg); | |
1652 | } | |
1653 | else if (bytes >= 4 && (align >= 4 || !STRICT_ALIGNMENT)) | |
3933e0e1 MM |
1654 | { |
1655 | move_bytes = 4; | |
1656 | tmp_reg = gen_reg_rtx (SImode); | |
b6c9286a MM |
1657 | emit_insn (gen_movsi (tmp_reg, expand_block_move_mem (SImode, src_addr, orig_src))); |
1658 | stores[ num_reg++ ] = gen_movsi (expand_block_move_mem (SImode, dest_addr, orig_dest), tmp_reg); | |
3933e0e1 MM |
1659 | } |
1660 | else if (bytes >= 2 && (align >= 2 || !STRICT_ALIGNMENT)) | |
1661 | { | |
1662 | move_bytes = 2; | |
1663 | tmp_reg = gen_reg_rtx (HImode); | |
b6c9286a MM |
1664 | emit_insn (gen_movsi (tmp_reg, expand_block_move_mem (HImode, src_addr, orig_src))); |
1665 | stores[ num_reg++ ] = gen_movhi (expand_block_move_mem (HImode, dest_addr, orig_dest), tmp_reg); | |
3933e0e1 MM |
1666 | } |
1667 | else | |
1668 | { | |
1669 | move_bytes = 1; | |
1670 | tmp_reg = gen_reg_rtx (QImode); | |
b6c9286a MM |
1671 | emit_insn (gen_movsi (tmp_reg, expand_block_move_mem (QImode, src_addr, orig_src))); |
1672 | stores[ num_reg++ ] = gen_movqi (expand_block_move_mem (QImode, dest_addr, orig_dest), tmp_reg); | |
3933e0e1 MM |
1673 | } |
1674 | ||
1675 | if (num_reg >= MAX_MOVE_REG) | |
1676 | { | |
1677 | for (i = 0; i < num_reg; i++) | |
1678 | emit_insn (stores[i]); | |
1679 | num_reg = 0; | |
7e69e155 MM |
1680 | } |
1681 | } | |
3933e0e1 | 1682 | |
b6c9286a MM |
1683 | for (i = 0; i < num_reg; i++) |
1684 | emit_insn (stores[i]); | |
7e69e155 MM |
1685 | } |
1686 | ||
1687 | return 1; | |
1688 | } | |
1689 | ||
9878760c RK |
1690 | \f |
1691 | /* Return 1 if OP is a load multiple operation. It is known to be a | |
1692 | PARALLEL and the first section will be tested. */ | |
1693 | ||
1694 | int | |
1695 | load_multiple_operation (op, mode) | |
1696 | rtx op; | |
1697 | enum machine_mode mode; | |
1698 | { | |
1699 | int count = XVECLEN (op, 0); | |
1700 | int dest_regno; | |
1701 | rtx src_addr; | |
1702 | int i; | |
1703 | ||
1704 | /* Perform a quick check so we don't blow up below. */ | |
1705 | if (count <= 1 | |
1706 | || GET_CODE (XVECEXP (op, 0, 0)) != SET | |
1707 | || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG | |
1708 | || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM) | |
1709 | return 0; | |
1710 | ||
1711 | dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0))); | |
1712 | src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0); | |
1713 | ||
1714 | for (i = 1; i < count; i++) | |
1715 | { | |
1716 | rtx elt = XVECEXP (op, 0, i); | |
1717 | ||
1718 | if (GET_CODE (elt) != SET | |
1719 | || GET_CODE (SET_DEST (elt)) != REG | |
1720 | || GET_MODE (SET_DEST (elt)) != SImode | |
1721 | || REGNO (SET_DEST (elt)) != dest_regno + i | |
1722 | || GET_CODE (SET_SRC (elt)) != MEM | |
1723 | || GET_MODE (SET_SRC (elt)) != SImode | |
1724 | || GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS | |
1725 | || ! rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr) | |
1726 | || GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT | |
1727 | || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != i * 4) | |
1728 | return 0; | |
1729 | } | |
1730 | ||
1731 | return 1; | |
1732 | } | |
1733 | ||
1734 | /* Similar, but tests for store multiple. Here, the second vector element | |
1735 | is a CLOBBER. It will be tested later. */ | |
1736 | ||
1737 | int | |
1738 | store_multiple_operation (op, mode) | |
1739 | rtx op; | |
1740 | enum machine_mode mode; | |
1741 | { | |
1742 | int count = XVECLEN (op, 0) - 1; | |
1743 | int src_regno; | |
1744 | rtx dest_addr; | |
1745 | int i; | |
1746 | ||
1747 | /* Perform a quick check so we don't blow up below. */ | |
1748 | if (count <= 1 | |
1749 | || GET_CODE (XVECEXP (op, 0, 0)) != SET | |
1750 | || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM | |
1751 | || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG) | |
1752 | return 0; | |
1753 | ||
1754 | src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0))); | |
1755 | dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0); | |
1756 | ||
1757 | for (i = 1; i < count; i++) | |
1758 | { | |
1759 | rtx elt = XVECEXP (op, 0, i + 1); | |
1760 | ||
1761 | if (GET_CODE (elt) != SET | |
1762 | || GET_CODE (SET_SRC (elt)) != REG | |
1763 | || GET_MODE (SET_SRC (elt)) != SImode | |
1764 | || REGNO (SET_SRC (elt)) != src_regno + i | |
1765 | || GET_CODE (SET_DEST (elt)) != MEM | |
1766 | || GET_MODE (SET_DEST (elt)) != SImode | |
1767 | || GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS | |
1768 | || ! rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr) | |
1769 | || GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT | |
1770 | || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != i * 4) | |
1771 | return 0; | |
1772 | } | |
1773 | ||
1774 | return 1; | |
1775 | } | |
1776 | \f | |
1777 | /* Return 1 if OP is a comparison operation that is valid for a branch insn. | |
1778 | We only check the opcode against the mode of the CC value here. */ | |
1779 | ||
1780 | int | |
1781 | branch_comparison_operator (op, mode) | |
1782 | register rtx op; | |
1783 | enum machine_mode mode; | |
1784 | { | |
1785 | enum rtx_code code = GET_CODE (op); | |
1786 | enum machine_mode cc_mode; | |
1787 | ||
1788 | if (GET_RTX_CLASS (code) != '<') | |
1789 | return 0; | |
1790 | ||
1791 | cc_mode = GET_MODE (XEXP (op, 0)); | |
1792 | if (GET_MODE_CLASS (cc_mode) != MODE_CC) | |
1793 | return 0; | |
1794 | ||
1795 | if ((code == GT || code == LT || code == GE || code == LE) | |
1796 | && cc_mode == CCUNSmode) | |
1797 | return 0; | |
1798 | ||
1799 | if ((code == GTU || code == LTU || code == GEU || code == LEU) | |
1800 | && (cc_mode != CCUNSmode)) | |
1801 | return 0; | |
1802 | ||
1803 | return 1; | |
1804 | } | |
1805 | ||
1806 | /* Return 1 if OP is a comparison operation that is valid for an scc insn. | |
1807 | We check the opcode against the mode of the CC value and disallow EQ or | |
1808 | NE comparisons for integers. */ | |
1809 | ||
1810 | int | |
1811 | scc_comparison_operator (op, mode) | |
1812 | register rtx op; | |
1813 | enum machine_mode mode; | |
1814 | { | |
1815 | enum rtx_code code = GET_CODE (op); | |
1816 | enum machine_mode cc_mode; | |
1817 | ||
1818 | if (GET_MODE (op) != mode && mode != VOIDmode) | |
1819 | return 0; | |
1820 | ||
1821 | if (GET_RTX_CLASS (code) != '<') | |
1822 | return 0; | |
1823 | ||
1824 | cc_mode = GET_MODE (XEXP (op, 0)); | |
1825 | if (GET_MODE_CLASS (cc_mode) != MODE_CC) | |
1826 | return 0; | |
1827 | ||
1828 | if (code == NE && cc_mode != CCFPmode) | |
1829 | return 0; | |
1830 | ||
1831 | if ((code == GT || code == LT || code == GE || code == LE) | |
1832 | && cc_mode == CCUNSmode) | |
1833 | return 0; | |
1834 | ||
1835 | if ((code == GTU || code == LTU || code == GEU || code == LEU) | |
1836 | && (cc_mode != CCUNSmode)) | |
1837 | return 0; | |
1838 | ||
c5defebb RK |
1839 | if (cc_mode == CCEQmode && code != EQ && code != NE) |
1840 | return 0; | |
1841 | ||
9878760c RK |
1842 | return 1; |
1843 | } | |
1844 | \f | |
1845 | /* Return 1 if ANDOP is a mask that has no bits on that are not in the | |
1846 | mask required to convert the result of a rotate insn into a shift | |
1847 | left insn of SHIFTOP bits. Both are known to be CONST_INT. */ | |
1848 | ||
1849 | int | |
1850 | includes_lshift_p (shiftop, andop) | |
1851 | register rtx shiftop; | |
1852 | register rtx andop; | |
1853 | { | |
1854 | int shift_mask = (~0 << INTVAL (shiftop)); | |
1855 | ||
1856 | return (INTVAL (andop) & ~shift_mask) == 0; | |
1857 | } | |
1858 | ||
1859 | /* Similar, but for right shift. */ | |
1860 | ||
1861 | int | |
1862 | includes_rshift_p (shiftop, andop) | |
1863 | register rtx shiftop; | |
1864 | register rtx andop; | |
1865 | { | |
802a0058 | 1866 | unsigned shift_mask = ~(unsigned)0; |
9878760c RK |
1867 | |
1868 | shift_mask >>= INTVAL (shiftop); | |
1869 | ||
1870 | return (INTVAL (andop) & ~ shift_mask) == 0; | |
1871 | } | |
35068b43 RK |
1872 | |
1873 | /* Return 1 if REGNO (reg1) == REGNO (reg2) - 1 making them candidates | |
1874 | for lfq and stfq insns. | |
1875 | ||
1876 | Note reg1 and reg2 *must* be hard registers. To be sure we will | |
1877 | abort if we are passed pseudo registers. */ | |
1878 | ||
1879 | int | |
1880 | registers_ok_for_quad_peep (reg1, reg2) | |
1881 | rtx reg1, reg2; | |
1882 | { | |
1883 | /* We might have been passed a SUBREG. */ | |
1884 | if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG) | |
1885 | return 0; | |
1886 | ||
1887 | return (REGNO (reg1) == REGNO (reg2) - 1); | |
1888 | } | |
1889 | ||
1890 | /* Return 1 if addr1 and addr2 are suitable for lfq or stfq insn. addr1 and | |
1891 | addr2 must be in consecutive memory locations (addr2 == addr1 + 8). */ | |
1892 | ||
1893 | int | |
1894 | addrs_ok_for_quad_peep (addr1, addr2) | |
1895 | register rtx addr1; | |
1896 | register rtx addr2; | |
1897 | { | |
1898 | int reg1; | |
1899 | int offset1; | |
1900 | ||
1901 | /* Extract an offset (if used) from the first addr. */ | |
1902 | if (GET_CODE (addr1) == PLUS) | |
1903 | { | |
1904 | /* If not a REG, return zero. */ | |
1905 | if (GET_CODE (XEXP (addr1, 0)) != REG) | |
1906 | return 0; | |
1907 | else | |
1908 | { | |
1909 | reg1 = REGNO (XEXP (addr1, 0)); | |
1910 | /* The offset must be constant! */ | |
1911 | if (GET_CODE (XEXP (addr1, 1)) != CONST_INT) | |
1912 | return 0; | |
1913 | offset1 = INTVAL (XEXP (addr1, 1)); | |
1914 | } | |
1915 | } | |
1916 | else if (GET_CODE (addr1) != REG) | |
1917 | return 0; | |
1918 | else | |
1919 | { | |
1920 | reg1 = REGNO (addr1); | |
1921 | /* This was a simple (mem (reg)) expression. Offset is 0. */ | |
1922 | offset1 = 0; | |
1923 | } | |
1924 | ||
1925 | /* Make sure the second address is a (mem (plus (reg) (const_int). */ | |
1926 | if (GET_CODE (addr2) != PLUS) | |
1927 | return 0; | |
1928 | ||
1929 | if (GET_CODE (XEXP (addr2, 0)) != REG | |
1930 | || GET_CODE (XEXP (addr2, 1)) != CONST_INT) | |
1931 | return 0; | |
1932 | ||
1933 | if (reg1 != REGNO (XEXP (addr2, 0))) | |
1934 | return 0; | |
1935 | ||
1936 | /* The offset for the second addr must be 8 more than the first addr. */ | |
1937 | if (INTVAL (XEXP (addr2, 1)) != offset1 + 8) | |
1938 | return 0; | |
1939 | ||
1940 | /* All the tests passed. addr1 and addr2 are valid for lfq or stfq | |
1941 | instructions. */ | |
1942 | return 1; | |
1943 | } | |
9878760c RK |
1944 | \f |
1945 | /* Return the register class of a scratch register needed to copy IN into | |
1946 | or out of a register in CLASS in MODE. If it can be done directly, | |
1947 | NO_REGS is returned. */ | |
1948 | ||
1949 | enum reg_class | |
1950 | secondary_reload_class (class, mode, in) | |
1951 | enum reg_class class; | |
1952 | enum machine_mode mode; | |
1953 | rtx in; | |
1954 | { | |
1955 | int regno = true_regnum (in); | |
1956 | ||
1957 | if (regno >= FIRST_PSEUDO_REGISTER) | |
1958 | regno = -1; | |
1959 | ||
1960 | /* We can place anything into GENERAL_REGS and can put GENERAL_REGS | |
1961 | into anything. */ | |
1962 | if (class == GENERAL_REGS || class == BASE_REGS | |
1963 | || (regno >= 0 && INT_REGNO_P (regno))) | |
1964 | return NO_REGS; | |
1965 | ||
1966 | /* Constants, memory, and FP registers can go into FP registers. */ | |
1967 | if ((regno == -1 || FP_REGNO_P (regno)) | |
1968 | && (class == FLOAT_REGS || class == NON_SPECIAL_REGS)) | |
1969 | return NO_REGS; | |
1970 | ||
1971 | /* We can copy among the CR registers. */ | |
1972 | if ((class == CR_REGS || class == CR0_REGS) | |
1973 | && regno >= 0 && CR_REGNO_P (regno)) | |
1974 | return NO_REGS; | |
1975 | ||
1976 | /* Otherwise, we need GENERAL_REGS. */ | |
1977 | return GENERAL_REGS; | |
1978 | } | |
1979 | \f | |
1980 | /* Given a comparison operation, return the bit number in CCR to test. We | |
1981 | know this is a valid comparison. | |
1982 | ||
1983 | SCC_P is 1 if this is for an scc. That means that %D will have been | |
1984 | used instead of %C, so the bits will be in different places. | |
1985 | ||
b4ac57ab | 1986 | Return -1 if OP isn't a valid comparison for some reason. */ |
9878760c RK |
1987 | |
1988 | int | |
1989 | ccr_bit (op, scc_p) | |
1990 | register rtx op; | |
1991 | int scc_p; | |
1992 | { | |
1993 | enum rtx_code code = GET_CODE (op); | |
1994 | enum machine_mode cc_mode; | |
1995 | int cc_regnum; | |
1996 | int base_bit; | |
1997 | ||
1998 | if (GET_RTX_CLASS (code) != '<') | |
1999 | return -1; | |
2000 | ||
2001 | cc_mode = GET_MODE (XEXP (op, 0)); | |
2002 | cc_regnum = REGNO (XEXP (op, 0)); | |
2003 | base_bit = 4 * (cc_regnum - 68); | |
2004 | ||
c5defebb RK |
2005 | /* In CCEQmode cases we have made sure that the result is always in the |
2006 | third bit of the CR field. */ | |
2007 | ||
2008 | if (cc_mode == CCEQmode) | |
2009 | return base_bit + 3; | |
2010 | ||
9878760c RK |
2011 | switch (code) |
2012 | { | |
2013 | case NE: | |
2014 | return scc_p ? base_bit + 3 : base_bit + 2; | |
2015 | case EQ: | |
2016 | return base_bit + 2; | |
2017 | case GT: case GTU: | |
2018 | return base_bit + 1; | |
2019 | case LT: case LTU: | |
2020 | return base_bit; | |
2021 | ||
2022 | case GE: case GEU: | |
2023 | /* If floating-point, we will have done a cror to put the bit in the | |
2024 | unordered position. So test that bit. For integer, this is ! LT | |
2025 | unless this is an scc insn. */ | |
2026 | return cc_mode == CCFPmode || scc_p ? base_bit + 3 : base_bit; | |
2027 | ||
2028 | case LE: case LEU: | |
2029 | return cc_mode == CCFPmode || scc_p ? base_bit + 3 : base_bit + 1; | |
2030 | ||
2031 | default: | |
2032 | abort (); | |
2033 | } | |
2034 | } | |
2035 | \f | |
2036 | /* Print an operand. Recognize special options, documented below. */ | |
2037 | ||
d9407988 MM |
2038 | #ifdef TARGET_SDATA |
2039 | #define SMALL_DATA_RELOC ((rs6000_sdata == SDATA_EABI) ? "sda21" : "sdarel") | |
ba5e43aa MM |
2040 | #else |
2041 | #define SMALL_DATA_RELOC "sda21" | |
2042 | #endif | |
2043 | ||
9878760c RK |
2044 | void |
2045 | print_operand (file, x, code) | |
2046 | FILE *file; | |
2047 | rtx x; | |
2048 | char code; | |
2049 | { | |
2050 | int i; | |
2051 | int val; | |
2052 | ||
2053 | /* These macros test for integers and extract the low-order bits. */ | |
2054 | #define INT_P(X) \ | |
2055 | ((GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST_DOUBLE) \ | |
2056 | && GET_MODE (X) == VOIDmode) | |
2057 | ||
2058 | #define INT_LOWPART(X) \ | |
2059 | (GET_CODE (X) == CONST_INT ? INTVAL (X) : CONST_DOUBLE_LOW (X)) | |
2060 | ||
2061 | switch (code) | |
2062 | { | |
a8b3aeda | 2063 | case '.': |
a85d226b RK |
2064 | /* Write out an instruction after the call which may be replaced |
2065 | with glue code by the loader. This depends on the AIX version. */ | |
2066 | asm_fprintf (file, RS6000_CALL_GLUE); | |
a8b3aeda RK |
2067 | return; |
2068 | ||
cfaaaf2e RK |
2069 | case '*': |
2070 | /* Write the register number of the TOC register. */ | |
4697a36c | 2071 | fputs (TARGET_MINIMAL_TOC ? reg_names[30] : reg_names[2], file); |
cfaaaf2e RK |
2072 | return; |
2073 | ||
c81bebd7 MM |
2074 | case '$': |
2075 | /* Write out either a '.' or '$' for the current location, depending | |
2076 | on whether this is Solaris or not. */ | |
2077 | putc ((DEFAULT_ABI == ABI_SOLARIS) ? '.' : '$', file); | |
2078 | return; | |
2079 | ||
9854d9ed RK |
2080 | case 'A': |
2081 | /* If X is a constant integer whose low-order 5 bits are zero, | |
2082 | write 'l'. Otherwise, write 'r'. This is a kludge to fix a bug | |
76229ac8 | 2083 | in the AIX assembler where "sri" with a zero shift count |
9854d9ed RK |
2084 | write a trash instruction. */ |
2085 | if (GET_CODE (x) == CONST_INT && (INTVAL (x) & 31) == 0) | |
76229ac8 | 2086 | putc ('l', file); |
9854d9ed | 2087 | else |
76229ac8 | 2088 | putc ('r', file); |
9854d9ed RK |
2089 | return; |
2090 | ||
2091 | case 'b': | |
2092 | /* Low-order 16 bits of constant, unsigned. */ | |
cad12a8d | 2093 | if (! INT_P (x)) |
9854d9ed | 2094 | output_operand_lossage ("invalid %%b value"); |
cad12a8d | 2095 | |
9854d9ed | 2096 | fprintf (file, "%d", INT_LOWPART (x) & 0xffff); |
cad12a8d RK |
2097 | return; |
2098 | ||
9854d9ed RK |
2099 | case 'C': |
2100 | /* This is an optional cror needed for LE or GE floating-point | |
2101 | comparisons. Otherwise write nothing. */ | |
2102 | if ((GET_CODE (x) == LE || GET_CODE (x) == GE) | |
2103 | && GET_MODE (XEXP (x, 0)) == CCFPmode) | |
2104 | { | |
2105 | int base_bit = 4 * (REGNO (XEXP (x, 0)) - 68); | |
2106 | ||
2107 | fprintf (file, "cror %d,%d,%d\n\t", base_bit + 3, | |
2108 | base_bit + 2, base_bit + (GET_CODE (x) == GE)); | |
2109 | } | |
2110 | return; | |
2111 | ||
2112 | case 'D': | |
2113 | /* Similar, except that this is for an scc, so we must be able to | |
2114 | encode the test in a single bit that is one. We do the above | |
2115 | for any LE, GE, GEU, or LEU and invert the bit for NE. */ | |
2116 | if (GET_CODE (x) == LE || GET_CODE (x) == GE | |
2117 | || GET_CODE (x) == LEU || GET_CODE (x) == GEU) | |
2118 | { | |
2119 | int base_bit = 4 * (REGNO (XEXP (x, 0)) - 68); | |
2120 | ||
2121 | fprintf (file, "cror %d,%d,%d\n\t", base_bit + 3, | |
2122 | base_bit + 2, | |
2123 | base_bit + (GET_CODE (x) == GE || GET_CODE (x) == GEU)); | |
2124 | } | |
2125 | ||
2126 | else if (GET_CODE (x) == NE) | |
2127 | { | |
2128 | int base_bit = 4 * (REGNO (XEXP (x, 0)) - 68); | |
2129 | ||
2130 | fprintf (file, "crnor %d,%d,%d\n\t", base_bit + 3, | |
2131 | base_bit + 2, base_bit + 2); | |
2132 | } | |
2133 | return; | |
2134 | ||
2135 | case 'E': | |
2136 | /* X is a CR register. Print the number of the third bit of the CR */ | |
2137 | if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x))) | |
2138 | output_operand_lossage ("invalid %%E value"); | |
2139 | ||
2140 | fprintf(file, "%d", 4 * (REGNO (x) - 68) + 3); | |
a85d226b | 2141 | return; |
9854d9ed RK |
2142 | |
2143 | case 'f': | |
2144 | /* X is a CR register. Print the shift count needed to move it | |
2145 | to the high-order four bits. */ | |
2146 | if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x))) | |
2147 | output_operand_lossage ("invalid %%f value"); | |
2148 | else | |
2149 | fprintf (file, "%d", 4 * (REGNO (x) - 68)); | |
2150 | return; | |
2151 | ||
2152 | case 'F': | |
2153 | /* Similar, but print the count for the rotate in the opposite | |
2154 | direction. */ | |
2155 | if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x))) | |
2156 | output_operand_lossage ("invalid %%F value"); | |
2157 | else | |
2158 | fprintf (file, "%d", 32 - 4 * (REGNO (x) - 68)); | |
2159 | return; | |
2160 | ||
2161 | case 'G': | |
2162 | /* X is a constant integer. If it is negative, print "m", | |
2163 | otherwise print "z". This is to make a aze or ame insn. */ | |
2164 | if (GET_CODE (x) != CONST_INT) | |
2165 | output_operand_lossage ("invalid %%G value"); | |
2166 | else if (INTVAL (x) >= 0) | |
76229ac8 | 2167 | putc ('z', file); |
9854d9ed | 2168 | else |
76229ac8 | 2169 | putc ('m', file); |
9854d9ed RK |
2170 | return; |
2171 | ||
9878760c | 2172 | case 'h': |
df3d94ed RK |
2173 | /* If constant, output low-order five bits. Otherwise, |
2174 | write normally. */ | |
9878760c RK |
2175 | if (INT_P (x)) |
2176 | fprintf (file, "%d", INT_LOWPART (x) & 31); | |
2177 | else | |
2178 | print_operand (file, x, 0); | |
2179 | return; | |
2180 | ||
64305719 DE |
2181 | case 'H': |
2182 | /* If constant, output low-order six bits. Otherwise, | |
2183 | write normally. */ | |
2184 | if (INT_P (x)) | |
2185 | fprintf (file, "%d", INT_LOWPART (x) & 63); | |
2186 | else | |
2187 | print_operand (file, x, 0); | |
2188 | return; | |
2189 | ||
9854d9ed RK |
2190 | case 'I': |
2191 | /* Print `i' if this is a constant, else nothing. */ | |
9878760c | 2192 | if (INT_P (x)) |
76229ac8 | 2193 | putc ('i', file); |
9878760c RK |
2194 | return; |
2195 | ||
9854d9ed RK |
2196 | case 'j': |
2197 | /* Write the bit number in CCR for jump. */ | |
2198 | i = ccr_bit (x, 0); | |
2199 | if (i == -1) | |
2200 | output_operand_lossage ("invalid %%j code"); | |
9878760c | 2201 | else |
9854d9ed | 2202 | fprintf (file, "%d", i); |
9878760c RK |
2203 | return; |
2204 | ||
9854d9ed RK |
2205 | case 'J': |
2206 | /* Similar, but add one for shift count in rlinm for scc and pass | |
2207 | scc flag to `ccr_bit'. */ | |
2208 | i = ccr_bit (x, 1); | |
2209 | if (i == -1) | |
2210 | output_operand_lossage ("invalid %%J code"); | |
2211 | else | |
a0466a68 RK |
2212 | /* If we want bit 31, write a shift count of zero, not 32. */ |
2213 | fprintf (file, "%d", i == 31 ? 0 : i + 1); | |
9878760c RK |
2214 | return; |
2215 | ||
9854d9ed RK |
2216 | case 'k': |
2217 | /* X must be a constant. Write the 1's complement of the | |
2218 | constant. */ | |
9878760c | 2219 | if (! INT_P (x)) |
9854d9ed | 2220 | output_operand_lossage ("invalid %%k value"); |
9878760c | 2221 | |
9854d9ed | 2222 | fprintf (file, "%d", ~ INT_LOWPART (x)); |
9878760c RK |
2223 | return; |
2224 | ||
9854d9ed RK |
2225 | case 'L': |
2226 | /* Write second word of DImode or DFmode reference. Works on register | |
2227 | or non-indexed memory only. */ | |
2228 | if (GET_CODE (x) == REG) | |
5ebfb2ba | 2229 | fprintf (file, "%s", reg_names[REGNO (x) + 1]); |
9854d9ed RK |
2230 | else if (GET_CODE (x) == MEM) |
2231 | { | |
2232 | /* Handle possible auto-increment. Since it is pre-increment and | |
2233 | we have already done it, we can just use an offset of four. */ | |
2234 | if (GET_CODE (XEXP (x, 0)) == PRE_INC | |
2235 | || GET_CODE (XEXP (x, 0)) == PRE_DEC) | |
a54d04b7 | 2236 | output_address (plus_constant (XEXP (XEXP (x, 0), 0), 4)); |
9854d9ed | 2237 | else |
a54d04b7 | 2238 | output_address (plus_constant (XEXP (x, 0), 4)); |
ba5e43aa MM |
2239 | if (small_data_operand (x, GET_MODE (x))) |
2240 | fprintf (file, "@%s(%s)", SMALL_DATA_RELOC, reg_names[0]); | |
9854d9ed | 2241 | } |
9878760c | 2242 | return; |
9854d9ed | 2243 | |
9878760c RK |
2244 | case 'm': |
2245 | /* MB value for a mask operand. */ | |
2246 | if (! mask_operand (x, VOIDmode)) | |
2247 | output_operand_lossage ("invalid %%m value"); | |
2248 | ||
2249 | val = INT_LOWPART (x); | |
2250 | ||
2251 | /* If the high bit is set and the low bit is not, the value is zero. | |
2252 | If the high bit is zero, the value is the first 1 bit we find from | |
2253 | the left. */ | |
2254 | if (val < 0 && (val & 1) == 0) | |
2255 | { | |
19d2d16f | 2256 | putc ('0', file); |
9878760c RK |
2257 | return; |
2258 | } | |
2259 | else if (val >= 0) | |
2260 | { | |
2261 | for (i = 1; i < 32; i++) | |
2262 | if ((val <<= 1) < 0) | |
2263 | break; | |
2264 | fprintf (file, "%d", i); | |
2265 | return; | |
2266 | } | |
2267 | ||
2268 | /* Otherwise, look for the first 0 bit from the right. The result is its | |
2269 | number plus 1. We know the low-order bit is one. */ | |
2270 | for (i = 0; i < 32; i++) | |
2271 | if (((val >>= 1) & 1) == 0) | |
2272 | break; | |
2273 | ||
2274 | /* If we ended in ...01, I would be 0. The correct value is 31, so | |
2275 | we want 31 - i. */ | |
2276 | fprintf (file, "%d", 31 - i); | |
2277 | return; | |
2278 | ||
2279 | case 'M': | |
2280 | /* ME value for a mask operand. */ | |
2281 | if (! mask_operand (x, VOIDmode)) | |
2282 | output_operand_lossage ("invalid %%m value"); | |
2283 | ||
2284 | val = INT_LOWPART (x); | |
2285 | ||
2286 | /* If the low bit is set and the high bit is not, the value is 31. | |
2287 | If the low bit is zero, the value is the first 1 bit we find from | |
2288 | the right. */ | |
2289 | if ((val & 1) && val >= 0) | |
2290 | { | |
76229ac8 | 2291 | fputs ("31", file); |
9878760c RK |
2292 | return; |
2293 | } | |
2294 | else if ((val & 1) == 0) | |
2295 | { | |
2296 | for (i = 0; i < 32; i++) | |
2297 | if ((val >>= 1) & 1) | |
2298 | break; | |
2299 | ||
2300 | /* If we had ....10, I would be 0. The result should be | |
2301 | 30, so we need 30 - i. */ | |
2302 | fprintf (file, "%d", 30 - i); | |
2303 | return; | |
2304 | } | |
2305 | ||
2306 | /* Otherwise, look for the first 0 bit from the left. The result is its | |
2307 | number minus 1. We know the high-order bit is one. */ | |
2308 | for (i = 0; i < 32; i++) | |
2309 | if ((val <<= 1) >= 0) | |
2310 | break; | |
2311 | ||
2312 | fprintf (file, "%d", i); | |
2313 | return; | |
2314 | ||
9878760c RK |
2315 | case 'N': |
2316 | /* Write the number of elements in the vector times 4. */ | |
2317 | if (GET_CODE (x) != PARALLEL) | |
2318 | output_operand_lossage ("invalid %%N value"); | |
2319 | ||
2320 | fprintf (file, "%d", XVECLEN (x, 0) * 4); | |
2321 | return; | |
2322 | ||
2323 | case 'O': | |
2324 | /* Similar, but subtract 1 first. */ | |
2325 | if (GET_CODE (x) != PARALLEL) | |
2326 | output_operand_lossage ("invalid %%N value"); | |
2327 | ||
2328 | fprintf (file, "%d", (XVECLEN (x, 0) - 1) * 4); | |
2329 | return; | |
2330 | ||
9854d9ed RK |
2331 | case 'p': |
2332 | /* X is a CONST_INT that is a power of two. Output the logarithm. */ | |
2333 | if (! INT_P (x) | |
2334 | || (i = exact_log2 (INT_LOWPART (x))) < 0) | |
2335 | output_operand_lossage ("invalid %%p value"); | |
2336 | ||
2337 | fprintf (file, "%d", i); | |
2338 | return; | |
2339 | ||
9878760c RK |
2340 | case 'P': |
2341 | /* The operand must be an indirect memory reference. The result | |
2342 | is the register number. */ | |
2343 | if (GET_CODE (x) != MEM || GET_CODE (XEXP (x, 0)) != REG | |
2344 | || REGNO (XEXP (x, 0)) >= 32) | |
2345 | output_operand_lossage ("invalid %%P value"); | |
2346 | ||
2347 | fprintf (file, "%d", REGNO (XEXP (x, 0))); | |
2348 | return; | |
2349 | ||
9854d9ed RK |
2350 | case 'R': |
2351 | /* X is a CR register. Print the mask for `mtcrf'. */ | |
2352 | if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x))) | |
2353 | output_operand_lossage ("invalid %%R value"); | |
2354 | else | |
2355 | fprintf (file, "%d", 128 >> (REGNO (x) - 68)); | |
9878760c | 2356 | return; |
9854d9ed RK |
2357 | |
2358 | case 's': | |
2359 | /* Low 5 bits of 32 - value */ | |
2360 | if (! INT_P (x)) | |
2361 | output_operand_lossage ("invalid %%s value"); | |
2362 | ||
2363 | fprintf (file, "%d", (32 - INT_LOWPART (x)) & 31); | |
9878760c | 2364 | return; |
9854d9ed | 2365 | |
9878760c RK |
2366 | case 't': |
2367 | /* Write 12 if this jump operation will branch if true, 4 otherwise. | |
2368 | All floating-point operations except NE branch true and integer | |
2369 | EQ, LT, GT, LTU and GTU also branch true. */ | |
2370 | if (GET_RTX_CLASS (GET_CODE (x)) != '<') | |
2371 | output_operand_lossage ("invalid %%t value"); | |
2372 | ||
2373 | else if ((GET_MODE (XEXP (x, 0)) == CCFPmode | |
2374 | && GET_CODE (x) != NE) | |
2375 | || GET_CODE (x) == EQ | |
2376 | || GET_CODE (x) == LT || GET_CODE (x) == GT | |
2377 | || GET_CODE (x) == LTU || GET_CODE (x) == GTU) | |
76229ac8 | 2378 | fputs ("12", file); |
9878760c | 2379 | else |
76229ac8 | 2380 | putc ('4', file); |
9878760c RK |
2381 | return; |
2382 | ||
2383 | case 'T': | |
2384 | /* Opposite of 't': write 4 if this jump operation will branch if true, | |
2385 | 12 otherwise. */ | |
2386 | if (GET_RTX_CLASS (GET_CODE (x)) != '<') | |
2387 | output_operand_lossage ("invalid %%t value"); | |
2388 | ||
2389 | else if ((GET_MODE (XEXP (x, 0)) == CCFPmode | |
2390 | && GET_CODE (x) != NE) | |
2391 | || GET_CODE (x) == EQ | |
2392 | || GET_CODE (x) == LT || GET_CODE (x) == GT | |
2393 | || GET_CODE (x) == LTU || GET_CODE (x) == GTU) | |
76229ac8 | 2394 | putc ('4', file); |
9878760c | 2395 | else |
76229ac8 | 2396 | fputs ("12", file); |
9878760c RK |
2397 | return; |
2398 | ||
9854d9ed | 2399 | case 'u': |
802a0058 | 2400 | /* High-order 16 bits of constant for use in unsigned operand. */ |
9854d9ed RK |
2401 | if (! INT_P (x)) |
2402 | output_operand_lossage ("invalid %%u value"); | |
9878760c | 2403 | |
76229ac8 | 2404 | fprintf (file, "0x%x", (INT_LOWPART (x) >> 16) & 0xffff); |
9878760c RK |
2405 | return; |
2406 | ||
802a0058 MM |
2407 | case 'v': |
2408 | /* High-order 16 bits of constant for use in signed operand. */ | |
2409 | if (! INT_P (x)) | |
2410 | output_operand_lossage ("invalid %%v value"); | |
2411 | ||
2412 | { | |
2413 | int value = (INT_LOWPART (x) >> 16) & 0xffff; | |
2414 | ||
2415 | /* Solaris assembler doesn't like lis 0,0x80000 */ | |
2416 | if (DEFAULT_ABI == ABI_SOLARIS && (value & 0x8000) != 0) | |
2417 | fprintf (file, "%d", value | (~0 << 16)); | |
2418 | else | |
2419 | fprintf (file, "0x%x", value); | |
2420 | return; | |
2421 | } | |
2422 | ||
9854d9ed RK |
2423 | case 'U': |
2424 | /* Print `u' if this has an auto-increment or auto-decrement. */ | |
2425 | if (GET_CODE (x) == MEM | |
2426 | && (GET_CODE (XEXP (x, 0)) == PRE_INC | |
2427 | || GET_CODE (XEXP (x, 0)) == PRE_DEC)) | |
76229ac8 | 2428 | putc ('u', file); |
9854d9ed | 2429 | return; |
9878760c | 2430 | |
9854d9ed RK |
2431 | case 'w': |
2432 | /* If constant, low-order 16 bits of constant, signed. Otherwise, write | |
2433 | normally. */ | |
2434 | if (INT_P (x)) | |
2435 | fprintf (file, "%d", | |
2436 | (INT_LOWPART (x) & 0xffff) - 2 * (INT_LOWPART (x) & 0x8000)); | |
2437 | else | |
2438 | print_operand (file, x, 0); | |
9878760c RK |
2439 | return; |
2440 | ||
9854d9ed RK |
2441 | case 'W': |
2442 | /* If constant, low-order 16 bits of constant, unsigned. | |
2443 | Otherwise, write normally. */ | |
2444 | if (INT_P (x)) | |
2445 | fprintf (file, "%d", INT_LOWPART (x) & 0xffff); | |
2446 | else | |
2447 | print_operand (file, x, 0); | |
2448 | return; | |
9878760c | 2449 | |
9854d9ed RK |
2450 | case 'X': |
2451 | if (GET_CODE (x) == MEM | |
2452 | && LEGITIMATE_INDEXED_ADDRESS_P (XEXP (x, 0))) | |
76229ac8 | 2453 | putc ('x', file); |
9854d9ed | 2454 | return; |
9878760c | 2455 | |
9854d9ed RK |
2456 | case 'Y': |
2457 | /* Like 'L', for third word of TImode */ | |
2458 | if (GET_CODE (x) == REG) | |
5ebfb2ba | 2459 | fprintf (file, "%s", reg_names[REGNO (x) + 2]); |
9854d9ed | 2460 | else if (GET_CODE (x) == MEM) |
9878760c | 2461 | { |
9854d9ed RK |
2462 | if (GET_CODE (XEXP (x, 0)) == PRE_INC |
2463 | || GET_CODE (XEXP (x, 0)) == PRE_DEC) | |
a54d04b7 | 2464 | output_address (plus_constant (XEXP (XEXP (x, 0), 0), 8)); |
9854d9ed | 2465 | else |
a54d04b7 | 2466 | output_address (plus_constant (XEXP (x, 0), 8)); |
ba5e43aa MM |
2467 | if (small_data_operand (x, GET_MODE (x))) |
2468 | fprintf (file, "@%s(%s)", SMALL_DATA_RELOC, reg_names[0]); | |
9878760c RK |
2469 | } |
2470 | return; | |
9854d9ed | 2471 | |
9878760c | 2472 | case 'z': |
b4ac57ab RS |
2473 | /* X is a SYMBOL_REF. Write out the name preceded by a |
2474 | period and without any trailing data in brackets. Used for function | |
4d30c363 MM |
2475 | names. If we are configured for System V (or the embedded ABI) on |
2476 | the PowerPC, do not emit the period, since those systems do not use | |
2477 | TOCs and the like. */ | |
9878760c RK |
2478 | if (GET_CODE (x) != SYMBOL_REF) |
2479 | abort (); | |
2480 | ||
b6c9286a MM |
2481 | if (XSTR (x, 0)[0] != '.') |
2482 | { | |
2483 | switch (DEFAULT_ABI) | |
2484 | { | |
2485 | default: | |
2486 | abort (); | |
2487 | ||
2488 | case ABI_AIX: | |
2489 | putc ('.', file); | |
2490 | break; | |
2491 | ||
2492 | case ABI_V4: | |
2493 | case ABI_AIX_NODESC: | |
c81bebd7 | 2494 | case ABI_SOLARIS: |
b6c9286a MM |
2495 | break; |
2496 | ||
2497 | case ABI_NT: | |
2498 | fputs ("..", file); | |
2499 | break; | |
2500 | } | |
2501 | } | |
9878760c RK |
2502 | RS6000_OUTPUT_BASENAME (file, XSTR (x, 0)); |
2503 | return; | |
2504 | ||
9854d9ed RK |
2505 | case 'Z': |
2506 | /* Like 'L', for last word of TImode. */ | |
2507 | if (GET_CODE (x) == REG) | |
5ebfb2ba | 2508 | fprintf (file, "%s", reg_names[REGNO (x) + 3]); |
9854d9ed RK |
2509 | else if (GET_CODE (x) == MEM) |
2510 | { | |
2511 | if (GET_CODE (XEXP (x, 0)) == PRE_INC | |
2512 | || GET_CODE (XEXP (x, 0)) == PRE_DEC) | |
a54d04b7 | 2513 | output_address (plus_constant (XEXP (XEXP (x, 0), 0), 12)); |
9854d9ed | 2514 | else |
a54d04b7 | 2515 | output_address (plus_constant (XEXP (x, 0), 12)); |
ba5e43aa MM |
2516 | if (small_data_operand (x, GET_MODE (x))) |
2517 | fprintf (file, "@%s(%s)", SMALL_DATA_RELOC, reg_names[0]); | |
9854d9ed | 2518 | } |
5c23c401 | 2519 | return; |
9854d9ed | 2520 | |
9878760c RK |
2521 | case 0: |
2522 | if (GET_CODE (x) == REG) | |
2523 | fprintf (file, "%s", reg_names[REGNO (x)]); | |
2524 | else if (GET_CODE (x) == MEM) | |
2525 | { | |
2526 | /* We need to handle PRE_INC and PRE_DEC here, since we need to | |
2527 | know the width from the mode. */ | |
2528 | if (GET_CODE (XEXP (x, 0)) == PRE_INC) | |
2529 | fprintf (file, "%d(%d)", GET_MODE_SIZE (GET_MODE (x)), | |
2530 | REGNO (XEXP (XEXP (x, 0), 0))); | |
2531 | else if (GET_CODE (XEXP (x, 0)) == PRE_DEC) | |
2532 | fprintf (file, "%d(%d)", - GET_MODE_SIZE (GET_MODE (x)), | |
2533 | REGNO (XEXP (XEXP (x, 0), 0))); | |
2534 | else | |
a54d04b7 | 2535 | output_address (XEXP (x, 0)); |
9878760c RK |
2536 | } |
2537 | else | |
a54d04b7 | 2538 | output_addr_const (file, x); |
a85d226b | 2539 | return; |
9878760c RK |
2540 | |
2541 | default: | |
2542 | output_operand_lossage ("invalid %%xn code"); | |
2543 | } | |
2544 | } | |
2545 | \f | |
2546 | /* Print the address of an operand. */ | |
2547 | ||
2548 | void | |
2549 | print_operand_address (file, x) | |
2550 | FILE *file; | |
2551 | register rtx x; | |
2552 | { | |
2553 | if (GET_CODE (x) == REG) | |
4697a36c | 2554 | fprintf (file, "0(%s)", reg_names[ REGNO (x) ]); |
9878760c RK |
2555 | else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST) |
2556 | { | |
2557 | output_addr_const (file, x); | |
ba5e43aa MM |
2558 | if (small_data_operand (x, GET_MODE (x))) |
2559 | fprintf (file, "@%s(%s)", SMALL_DATA_RELOC, reg_names[0]); | |
7509c759 | 2560 | |
4697a36c | 2561 | #ifdef TARGET_NO_TOC |
7509c759 | 2562 | else if (TARGET_NO_TOC) |
4697a36c | 2563 | ; |
4697a36c | 2564 | #endif |
7509c759 | 2565 | else |
4697a36c | 2566 | fprintf (file, "(%s)", reg_names[ TARGET_MINIMAL_TOC ? 30 : 2 ]); |
9878760c RK |
2567 | } |
2568 | else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == REG) | |
2569 | { | |
2570 | if (REGNO (XEXP (x, 0)) == 0) | |
4697a36c MM |
2571 | fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 1)) ], |
2572 | reg_names[ REGNO (XEXP (x, 0)) ]); | |
9878760c | 2573 | else |
4697a36c MM |
2574 | fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 0)) ], |
2575 | reg_names[ REGNO (XEXP (x, 1)) ]); | |
9878760c RK |
2576 | } |
2577 | else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT) | |
4697a36c MM |
2578 | fprintf (file, "%d(%s)", INTVAL (XEXP (x, 1)), reg_names[ REGNO (XEXP (x, 0)) ]); |
2579 | else if (TARGET_ELF && !TARGET_64BIT && GET_CODE (x) == LO_SUM | |
2580 | && GET_CODE (XEXP (x, 0)) == REG && CONSTANT_P (XEXP (x, 1))) | |
2581 | { | |
2582 | output_addr_const (file, XEXP (x, 1)); | |
2583 | fprintf (file, "@l(%s)", reg_names[ REGNO (XEXP (x, 0)) ]); | |
2584 | } | |
9878760c RK |
2585 | else |
2586 | abort (); | |
2587 | } | |
2588 | \f | |
2589 | /* This page contains routines that are used to determine what the function | |
2590 | prologue and epilogue code will do and write them out. */ | |
2591 | ||
2592 | /* Return the first fixed-point register that is required to be saved. 32 if | |
2593 | none. */ | |
2594 | ||
2595 | int | |
2596 | first_reg_to_save () | |
2597 | { | |
2598 | int first_reg; | |
2599 | ||
2600 | /* Find lowest numbered live register. */ | |
2601 | for (first_reg = 13; first_reg <= 31; first_reg++) | |
2602 | if (regs_ever_live[first_reg]) | |
2603 | break; | |
2604 | ||
e165f3f0 RK |
2605 | /* If profiling, then we must save/restore every register that contains |
2606 | a parameter before/after the .mcount call. Use registers from 30 down | |
2607 | to 23 to do this. Don't use the frame pointer in reg 31. | |
2608 | ||
2609 | For now, save enough room for all of the parameter registers. */ | |
b6c9286a | 2610 | if (DEFAULT_ABI == ABI_AIX && profile_flag) |
e165f3f0 RK |
2611 | if (first_reg > 23) |
2612 | first_reg = 23; | |
2613 | ||
9878760c RK |
2614 | return first_reg; |
2615 | } | |
2616 | ||
2617 | /* Similar, for FP regs. */ | |
2618 | ||
2619 | int | |
2620 | first_fp_reg_to_save () | |
2621 | { | |
2622 | int first_reg; | |
2623 | ||
2624 | /* Find lowest numbered live register. */ | |
2625 | for (first_reg = 14 + 32; first_reg <= 63; first_reg++) | |
2626 | if (regs_ever_live[first_reg]) | |
2627 | break; | |
2628 | ||
2629 | return first_reg; | |
2630 | } | |
2631 | ||
9878760c RK |
2632 | /* Return non-zero if this function makes calls. */ |
2633 | ||
2634 | int | |
2635 | rs6000_makes_calls () | |
2636 | { | |
2637 | rtx insn; | |
2638 | ||
0c61c946 RK |
2639 | /* If we are profiling, we will be making a call to mcount. */ |
2640 | if (profile_flag) | |
2641 | return 1; | |
2642 | ||
9878760c RK |
2643 | for (insn = get_insns (); insn; insn = next_insn (insn)) |
2644 | if (GET_CODE (insn) == CALL_INSN) | |
2645 | return 1; | |
2646 | ||
2647 | return 0; | |
2648 | } | |
2649 | ||
4697a36c MM |
2650 | \f |
2651 | /* Calculate the stack information for the current function. This is | |
2652 | complicated by having two separate calling sequences, the AIX calling | |
2653 | sequence and the V.4 calling sequence. | |
2654 | ||
2655 | AIX stack frames look like: | |
2656 | ||
2657 | SP----> +---------------------------------------+ | |
2658 | | back chain to caller | 0 | |
2659 | +---------------------------------------+ | |
2660 | | saved CR | 4 | |
2661 | +---------------------------------------+ | |
2662 | | saved LR | 8 | |
2663 | +---------------------------------------+ | |
2664 | | reserved for compilers | 12 | |
2665 | +---------------------------------------+ | |
2666 | | reserved for binders | 16 | |
2667 | +---------------------------------------+ | |
2668 | | saved TOC pointer | 20 | |
2669 | +---------------------------------------+ | |
2670 | | Parameter save area (P) | 24 | |
2671 | +---------------------------------------+ | |
802a0058 MM |
2672 | | Float/int conversion temporary (X) | 24+P |
2673 | +---------------------------------------+ | |
2674 | | Alloca space (A) | 24+P+X | |
4697a36c | 2675 | +---------------------------------------+ |
802a0058 | 2676 | | Local variable space (L) | 24+P+X+A |
4697a36c | 2677 | +---------------------------------------+ |
802a0058 | 2678 | | Save area for GP registers (G) | 24+P+X+A+L |
4697a36c | 2679 | +---------------------------------------+ |
802a0058 | 2680 | | Save area for FP registers (F) | 24+P+X+A+L+G |
4697a36c MM |
2681 | +---------------------------------------+ |
2682 | old SP->| back chain to caller's caller | | |
2683 | +---------------------------------------+ | |
2684 | ||
2685 | V.4 stack frames look like: | |
2686 | ||
2687 | SP----> +---------------------------------------+ | |
2688 | | back chain to caller | 0 | |
2689 | +---------------------------------------+ | |
5eb387b8 | 2690 | | caller's saved LR | 4 |
4697a36c MM |
2691 | +---------------------------------------+ |
2692 | | Parameter save area (P) | 8 | |
2693 | +---------------------------------------+ | |
802a0058 | 2694 | | Float/int conversion temporary (X) | 8+P |
4697a36c | 2695 | +---------------------------------------+ |
802a0058 | 2696 | | Alloca space (A) | 8+P+X |
4697a36c | 2697 | +---------------------------------------+ |
802a0058 | 2698 | | Varargs save area (V) | 8+P+X+A |
4697a36c | 2699 | +---------------------------------------+ |
802a0058 | 2700 | | Local variable space (L) | 8+P+X+A+V |
4697a36c | 2701 | +---------------------------------------+ |
802a0058 | 2702 | | saved CR (C) | 8+P+X+A+V+L |
4697a36c | 2703 | +---------------------------------------+ |
802a0058 MM |
2704 | | Save area for GP registers (G) | 8+P+X+A+V+L+C |
2705 | +---------------------------------------+ | |
2706 | | Save area for FP registers (F) | 8+P+X+A+V+L+C+G | |
4697a36c MM |
2707 | +---------------------------------------+ |
2708 | old SP->| back chain to caller's caller | | |
2709 | +---------------------------------------+ | |
b6c9286a MM |
2710 | |
2711 | ||
2712 | A PowerPC Windows/NT frame looks like: | |
2713 | ||
2714 | SP----> +---------------------------------------+ | |
2715 | | back chain to caller | 0 | |
2716 | +---------------------------------------+ | |
2717 | | reserved | 4 | |
2718 | +---------------------------------------+ | |
2719 | | reserved | 8 | |
2720 | +---------------------------------------+ | |
2721 | | reserved | 12 | |
2722 | +---------------------------------------+ | |
2723 | | reserved | 16 | |
2724 | +---------------------------------------+ | |
2725 | | reserved | 20 | |
2726 | +---------------------------------------+ | |
2727 | | Parameter save area (P) | 24 | |
2728 | +---------------------------------------+ | |
802a0058 MM |
2729 | | Float/int conversion temporary (X) | 24+P |
2730 | +---------------------------------------+ | |
2731 | | Alloca space (A) | 24+P+X | |
b6c9286a | 2732 | +---------------------------------------+ |
802a0058 | 2733 | | Local variable space (L) | 24+P+X+A |
b6c9286a | 2734 | +---------------------------------------+ |
802a0058 | 2735 | | Save area for FP registers (F) | 24+P+X+A+L |
b6c9286a | 2736 | +---------------------------------------+ |
802a0058 | 2737 | | Possible alignment area (X) | 24+P+X+A+L+F |
b6c9286a | 2738 | +---------------------------------------+ |
802a0058 | 2739 | | Save area for GP registers (G) | 24+P+X+A+L+F+X |
b6c9286a | 2740 | +---------------------------------------+ |
802a0058 | 2741 | | Save area for CR (C) | 24+P+X+A+L+F+X+G |
b6c9286a | 2742 | +---------------------------------------+ |
802a0058 | 2743 | | Save area for TOC (T) | 24+P+X+A+L+F+X+G+C |
b6c9286a | 2744 | +---------------------------------------+ |
802a0058 | 2745 | | Save area for LR (R) | 24+P+X+A+L+F+X+G+C+T |
b6c9286a MM |
2746 | +---------------------------------------+ |
2747 | old SP->| back chain to caller's caller | | |
2748 | +---------------------------------------+ | |
2749 | ||
2750 | For NT, there is no specific order to save the registers, but in | |
2751 | order to support __builtin_return_address, the save area for the | |
2752 | link register needs to be in a known place, so we use -4 off of the | |
2753 | old SP. To support calls through pointers, we also allocate a | |
2754 | fixed slot to store the TOC, -8 off the old SP. */ | |
4697a36c MM |
2755 | |
2756 | rs6000_stack_t * | |
2757 | rs6000_stack_info () | |
2758 | { | |
2759 | static rs6000_stack_t info, zero_info; | |
2760 | rs6000_stack_t *info_ptr = &info; | |
2761 | int reg_size = TARGET_64BIT ? 8 : 4; | |
24d304eb | 2762 | enum rs6000_abi abi; |
b6c9286a | 2763 | int total_raw_size; |
4697a36c MM |
2764 | |
2765 | /* Zero all fields portably */ | |
2766 | info = zero_info; | |
2767 | ||
2768 | /* Select which calling sequence */ | |
b6c9286a | 2769 | info_ptr->abi = abi = DEFAULT_ABI; |
9878760c | 2770 | |
4697a36c MM |
2771 | /* Calculate which registers need to be saved & save area size */ |
2772 | info_ptr->first_gp_reg_save = first_reg_to_save (); | |
2773 | info_ptr->gp_size = reg_size * (32 - info_ptr->first_gp_reg_save); | |
2774 | ||
2775 | info_ptr->first_fp_reg_save = first_fp_reg_to_save (); | |
2776 | info_ptr->fp_size = 8 * (64 - info_ptr->first_fp_reg_save); | |
2777 | ||
2778 | /* Does this function call anything? */ | |
2779 | info_ptr->calls_p = rs6000_makes_calls (); | |
2780 | ||
b6c9286a MM |
2781 | /* Do we need to allocate space to save the toc? */ |
2782 | if (rs6000_save_toc_p) | |
2783 | { | |
2784 | info_ptr->toc_save_p = 1; | |
2785 | info_ptr->toc_size = reg_size; | |
2786 | } | |
2787 | ||
802a0058 MM |
2788 | /* Does this machine need the float/int conversion area? */ |
2789 | info_ptr->fpmem_p = regs_ever_live[FPMEM_REGNUM]; | |
2790 | ||
b6c9286a MM |
2791 | /* If this is main and we need to call a function to set things up, |
2792 | save main's arguments around the call. */ | |
c81bebd7 MM |
2793 | #ifdef TARGET_EABI |
2794 | if (TARGET_EABI) | |
2795 | #endif | |
b6c9286a | 2796 | { |
c81bebd7 | 2797 | if (strcmp (IDENTIFIER_POINTER (DECL_NAME (current_function_decl)), "main") == 0) |
b6c9286a | 2798 | { |
c81bebd7 | 2799 | info_ptr->main_p = 1; |
b6c9286a | 2800 | |
c81bebd7 MM |
2801 | #ifdef NAME__MAIN |
2802 | info_ptr->calls_p = 1; | |
b6c9286a | 2803 | |
c81bebd7 | 2804 | if (DECL_ARGUMENTS (current_function_decl)) |
b6c9286a | 2805 | { |
c81bebd7 MM |
2806 | int i; |
2807 | tree arg; | |
2808 | ||
2809 | info_ptr->main_save_p = 1; | |
2810 | info_ptr->main_size = 0; | |
2811 | ||
2812 | for ((i = 0), (arg = DECL_ARGUMENTS (current_function_decl)); | |
2813 | arg != NULL_TREE && i < 8; | |
2814 | (arg = TREE_CHAIN (arg)), i++) | |
2815 | { | |
2816 | info_ptr->main_size += reg_size; | |
2817 | } | |
b6c9286a | 2818 | } |
b6c9286a | 2819 | #endif |
c81bebd7 | 2820 | } |
b6c9286a MM |
2821 | } |
2822 | ||
c81bebd7 | 2823 | |
4697a36c MM |
2824 | /* Determine if we need to save the link register */ |
2825 | if (regs_ever_live[65] || profile_flag | |
2826 | #ifdef TARGET_RELOCATABLE | |
2827 | || (TARGET_RELOCATABLE && (get_pool_size () != 0)) | |
2828 | #endif | |
2829 | || (info_ptr->first_fp_reg_save != 64 | |
2830 | && !FP_SAVE_INLINE (info_ptr->first_fp_reg_save)) | |
24d304eb | 2831 | || (abi == ABI_V4 && current_function_calls_alloca) |
c81bebd7 | 2832 | || (abi == ABI_SOLARIS && current_function_calls_alloca) |
4697a36c MM |
2833 | || info_ptr->calls_p) |
2834 | { | |
2835 | info_ptr->lr_save_p = 1; | |
2836 | regs_ever_live[65] = 1; | |
b6c9286a MM |
2837 | if (abi == ABI_NT) |
2838 | info_ptr->lr_size = reg_size; | |
4697a36c MM |
2839 | } |
2840 | ||
2841 | /* Determine if we need to save the condition code registers */ | |
2842 | if (regs_ever_live[70] || regs_ever_live[71] || regs_ever_live[72]) | |
2843 | { | |
2844 | info_ptr->cr_save_p = 1; | |
c81bebd7 | 2845 | if (abi == ABI_V4 || abi == ABI_NT || abi == ABI_SOLARIS) |
4697a36c MM |
2846 | info_ptr->cr_size = reg_size; |
2847 | } | |
2848 | ||
2849 | /* Determine various sizes */ | |
2850 | info_ptr->reg_size = reg_size; | |
2851 | info_ptr->fixed_size = RS6000_SAVE_AREA; | |
2852 | info_ptr->varargs_size = RS6000_VARARGS_AREA; | |
2853 | info_ptr->vars_size = ALIGN (get_frame_size (), 8); | |
2854 | info_ptr->parm_size = ALIGN (current_function_outgoing_args_size, 8); | |
802a0058 | 2855 | info_ptr->fpmem_size = (info_ptr->fpmem_p) ? 8 : 0; |
b6c9286a MM |
2856 | info_ptr->save_size = ALIGN (info_ptr->fp_size |
2857 | + info_ptr->gp_size | |
2858 | + info_ptr->cr_size | |
2859 | + info_ptr->lr_size | |
2860 | + info_ptr->toc_size | |
2861 | + info_ptr->main_size, 8); | |
2862 | ||
2863 | total_raw_size = (info_ptr->vars_size | |
2864 | + info_ptr->parm_size | |
802a0058 | 2865 | + info_ptr->fpmem_size |
b6c9286a MM |
2866 | + info_ptr->save_size |
2867 | + info_ptr->varargs_size | |
2868 | + info_ptr->fixed_size); | |
2869 | ||
2870 | info_ptr->total_size = ALIGN (total_raw_size, STACK_BOUNDARY / BITS_PER_UNIT); | |
4697a36c MM |
2871 | |
2872 | /* Determine if we need to allocate any stack frame. | |
2873 | For AIX We need to push the stack if a frame pointer is needed (because | |
2874 | the stack might be dynamically adjusted), if we are debugging, if the | |
2875 | total stack size is more than 220 bytes, or if we make calls. | |
2876 | ||
2877 | For V.4 we don't have the stack cushion that AIX uses, but assume that | |
2878 | the debugger can handle stackless frames. */ | |
2879 | ||
2880 | if (info_ptr->calls_p) | |
2881 | info_ptr->push_p = 1; | |
2882 | ||
c81bebd7 | 2883 | else if (abi == ABI_V4 || abi == ABI_NT || abi == ABI_SOLARIS) |
b6c9286a | 2884 | info_ptr->push_p = (total_raw_size > info_ptr->fixed_size |
4697a36c MM |
2885 | || info_ptr->lr_save_p); |
2886 | ||
2887 | else | |
2888 | info_ptr->push_p = (frame_pointer_needed | |
2889 | || write_symbols != NO_DEBUG | |
2890 | || info_ptr->total_size > 220); | |
2891 | ||
2892 | /* Calculate the offsets */ | |
802a0058 | 2893 | info_ptr->fpmem_offset = info_ptr->total_size - info_ptr->parm_size; |
24d304eb | 2894 | switch (abi) |
4697a36c | 2895 | { |
b6c9286a | 2896 | case ABI_NONE: |
24d304eb | 2897 | default: |
b6c9286a MM |
2898 | abort (); |
2899 | ||
2900 | case ABI_AIX: | |
2901 | case ABI_AIX_NODESC: | |
2902 | info_ptr->fp_save_offset = - info_ptr->fp_size; | |
2903 | info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size; | |
2904 | info_ptr->main_save_offset = info_ptr->gp_save_offset - info_ptr->main_size; | |
2905 | info_ptr->cr_save_offset = 4; | |
2906 | info_ptr->lr_save_offset = 8; | |
24d304eb RK |
2907 | break; |
2908 | ||
2909 | case ABI_V4: | |
c81bebd7 | 2910 | case ABI_SOLARIS: |
b6c9286a MM |
2911 | info_ptr->fp_save_offset = - info_ptr->fp_size; |
2912 | info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size; | |
2913 | info_ptr->cr_save_offset = info_ptr->gp_save_offset - reg_size; | |
2914 | info_ptr->toc_save_offset = info_ptr->cr_save_offset - info_ptr->cr_size; | |
2915 | info_ptr->main_save_offset = info_ptr->toc_save_offset - info_ptr->toc_size; | |
2916 | info_ptr->lr_save_offset = reg_size; | |
2917 | break; | |
2918 | ||
2919 | case ABI_NT: | |
2920 | info_ptr->lr_save_offset = -4; | |
2921 | info_ptr->toc_save_offset = info_ptr->lr_save_offset - info_ptr->lr_size; | |
2922 | info_ptr->cr_save_offset = info_ptr->toc_save_offset - info_ptr->toc_size; | |
2923 | info_ptr->gp_save_offset = info_ptr->cr_save_offset - info_ptr->cr_size - info_ptr->gp_size + reg_size; | |
2924 | info_ptr->fp_save_offset = info_ptr->gp_save_offset - info_ptr->fp_size; | |
2925 | if (info_ptr->fp_size && ((- info_ptr->fp_save_offset) % 8) != 0) | |
2926 | info_ptr->fp_save_offset -= 4; | |
2927 | ||
2928 | info_ptr->main_save_offset = info_ptr->fp_save_offset - info_ptr->main_size; | |
24d304eb | 2929 | break; |
4697a36c MM |
2930 | } |
2931 | ||
2932 | /* Zero offsets if we're not saving those registers */ | |
2933 | if (!info_ptr->fp_size) | |
2934 | info_ptr->fp_save_offset = 0; | |
2935 | ||
2936 | if (!info_ptr->gp_size) | |
2937 | info_ptr->gp_save_offset = 0; | |
2938 | ||
2939 | if (!info_ptr->lr_save_p) | |
2940 | info_ptr->lr_save_offset = 0; | |
2941 | ||
2942 | if (!info_ptr->cr_save_p) | |
2943 | info_ptr->cr_save_offset = 0; | |
2944 | ||
b6c9286a MM |
2945 | if (!info_ptr->toc_save_p) |
2946 | info_ptr->toc_save_offset = 0; | |
2947 | ||
2948 | if (!info_ptr->main_save_p) | |
2949 | info_ptr->main_save_offset = 0; | |
2950 | ||
802a0058 MM |
2951 | if (!info_ptr->fpmem_p) |
2952 | info_ptr->fpmem_offset = 0; | |
2953 | else | |
2954 | { | |
2955 | rs6000_fpmem_size = info_ptr->fpmem_size; | |
2956 | rs6000_fpmem_offset = STACK_DYNAMIC_OFFSET (current_function_decl) - info_ptr->fpmem_size; | |
2957 | if (rs6000_fpmem_offset > 32767) | |
2958 | abort (); | |
2959 | } | |
2960 | ||
4697a36c MM |
2961 | return info_ptr; |
2962 | } | |
2963 | ||
2964 | void | |
2965 | debug_stack_info (info) | |
2966 | rs6000_stack_t *info; | |
9878760c | 2967 | { |
24d304eb RK |
2968 | char *abi_string; |
2969 | ||
4697a36c MM |
2970 | if (!info) |
2971 | info = rs6000_stack_info (); | |
2972 | ||
2973 | fprintf (stderr, "\nStack information for function %s:\n", | |
2974 | ((current_function_decl && DECL_NAME (current_function_decl)) | |
2975 | ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl)) | |
2976 | : "<unknown>")); | |
2977 | ||
24d304eb RK |
2978 | switch (info->abi) |
2979 | { | |
b6c9286a MM |
2980 | default: abi_string = "Unknown"; break; |
2981 | case ABI_NONE: abi_string = "NONE"; break; | |
2982 | case ABI_AIX: abi_string = "AIX"; break; | |
2983 | case ABI_AIX_NODESC: abi_string = "AIX"; break; | |
2984 | case ABI_V4: abi_string = "V.4"; break; | |
c81bebd7 | 2985 | case ABI_SOLARIS: abi_string = "Solaris"; break; |
b6c9286a | 2986 | case ABI_NT: abi_string = "NT"; break; |
24d304eb RK |
2987 | } |
2988 | ||
2989 | fprintf (stderr, "\tABI = %5s\n", abi_string); | |
2990 | ||
4697a36c MM |
2991 | if (info->first_gp_reg_save != 32) |
2992 | fprintf (stderr, "\tfirst_gp_reg_save = %5d\n", info->first_gp_reg_save); | |
2993 | ||
2994 | if (info->first_fp_reg_save != 64) | |
2995 | fprintf (stderr, "\tfirst_fp_reg_save = %5d\n", info->first_fp_reg_save); | |
9878760c | 2996 | |
4697a36c MM |
2997 | if (info->lr_save_p) |
2998 | fprintf (stderr, "\tlr_save_p = %5d\n", info->lr_save_p); | |
9878760c | 2999 | |
4697a36c MM |
3000 | if (info->cr_save_p) |
3001 | fprintf (stderr, "\tcr_save_p = %5d\n", info->cr_save_p); | |
3002 | ||
b6c9286a MM |
3003 | if (info->toc_save_p) |
3004 | fprintf (stderr, "\ttoc_save_p = %5d\n", info->toc_save_p); | |
3005 | ||
4697a36c MM |
3006 | if (info->push_p) |
3007 | fprintf (stderr, "\tpush_p = %5d\n", info->push_p); | |
3008 | ||
3009 | if (info->calls_p) | |
3010 | fprintf (stderr, "\tcalls_p = %5d\n", info->calls_p); | |
3011 | ||
b6c9286a MM |
3012 | if (info->main_p) |
3013 | fprintf (stderr, "\tmain_p = %5d\n", info->main_p); | |
3014 | ||
3015 | if (info->main_save_p) | |
3016 | fprintf (stderr, "\tmain_save_p = %5d\n", info->main_save_p); | |
3017 | ||
802a0058 MM |
3018 | if (info->fpmem_p) |
3019 | fprintf (stderr, "\tfpmem_p = %5d\n", info->fpmem_p); | |
3020 | ||
4697a36c MM |
3021 | if (info->gp_save_offset) |
3022 | fprintf (stderr, "\tgp_save_offset = %5d\n", info->gp_save_offset); | |
3023 | ||
3024 | if (info->fp_save_offset) | |
3025 | fprintf (stderr, "\tfp_save_offset = %5d\n", info->fp_save_offset); | |
3026 | ||
3027 | if (info->lr_save_offset) | |
3028 | fprintf (stderr, "\tlr_save_offset = %5d\n", info->lr_save_offset); | |
3029 | ||
3030 | if (info->cr_save_offset) | |
3031 | fprintf (stderr, "\tcr_save_offset = %5d\n", info->cr_save_offset); | |
3032 | ||
b6c9286a MM |
3033 | if (info->toc_save_offset) |
3034 | fprintf (stderr, "\ttoc_save_offset = %5d\n", info->toc_save_offset); | |
3035 | ||
4697a36c MM |
3036 | if (info->varargs_save_offset) |
3037 | fprintf (stderr, "\tvarargs_save_offset = %5d\n", info->varargs_save_offset); | |
3038 | ||
b6c9286a MM |
3039 | if (info->main_save_offset) |
3040 | fprintf (stderr, "\tmain_save_offset = %5d\n", info->main_save_offset); | |
3041 | ||
802a0058 MM |
3042 | if (info->fpmem_offset) |
3043 | fprintf (stderr, "\tfpmem_offset = %5d\n", info->fpmem_offset); | |
3044 | ||
4697a36c MM |
3045 | if (info->total_size) |
3046 | fprintf (stderr, "\ttotal_size = %5d\n", info->total_size); | |
3047 | ||
3048 | if (info->varargs_size) | |
3049 | fprintf (stderr, "\tvarargs_size = %5d\n", info->varargs_size); | |
3050 | ||
3051 | if (info->vars_size) | |
3052 | fprintf (stderr, "\tvars_size = %5d\n", info->vars_size); | |
3053 | ||
3054 | if (info->parm_size) | |
3055 | fprintf (stderr, "\tparm_size = %5d\n", info->parm_size); | |
3056 | ||
802a0058 MM |
3057 | if (info->fpmem_size) |
3058 | fprintf (stderr, "\tfpmem_size = %5d\n", info->fpmem_size); | |
3059 | ||
4697a36c MM |
3060 | if (info->fixed_size) |
3061 | fprintf (stderr, "\tfixed_size = %5d\n", info->fixed_size); | |
3062 | ||
3063 | if (info->gp_size) | |
3064 | fprintf (stderr, "\tgp_size = %5d\n", info->gp_size); | |
3065 | ||
3066 | if (info->fp_size) | |
3067 | fprintf (stderr, "\tfp_size = %5d\n", info->fp_size); | |
3068 | ||
b6c9286a MM |
3069 | if (info->lr_size) |
3070 | fprintf (stderr, "\tlr_size = %5d\n", info->cr_size); | |
3071 | ||
4697a36c MM |
3072 | if (info->cr_size) |
3073 | fprintf (stderr, "\tcr_size = %5d\n", info->cr_size); | |
3074 | ||
b6c9286a MM |
3075 | if (info->toc_size) |
3076 | fprintf (stderr, "\ttoc_size = %5d\n", info->toc_size); | |
3077 | ||
3078 | if (info->main_size) | |
3079 | fprintf (stderr, "\tmain_size = %5d\n", info->main_size); | |
3080 | ||
4697a36c MM |
3081 | if (info->save_size) |
3082 | fprintf (stderr, "\tsave_size = %5d\n", info->save_size); | |
3083 | ||
3084 | if (info->reg_size != 4) | |
3085 | fprintf (stderr, "\treg_size = %5d\n", info->reg_size); | |
3086 | ||
3087 | fprintf (stderr, "\n"); | |
9878760c RK |
3088 | } |
3089 | ||
4697a36c | 3090 | \f |
9878760c | 3091 | /* Write function prologue. */ |
9878760c RK |
3092 | void |
3093 | output_prolog (file, size) | |
3094 | FILE *file; | |
3095 | int size; | |
3096 | { | |
4697a36c | 3097 | rs6000_stack_t *info = rs6000_stack_info (); |
b6c9286a MM |
3098 | int reg_size = info->reg_size; |
3099 | char *store_reg; | |
3100 | char *load_reg; | |
979721f8 MM |
3101 | int sp_reg = 1; |
3102 | int sp_offset = 0; | |
b6c9286a | 3103 | |
8f802bfb | 3104 | if (TARGET_32BIT) |
b6c9286a | 3105 | { |
8f802bfb DE |
3106 | store_reg = "\t{st|stw} %s,%d(%s)\n"; |
3107 | load_reg = "\t{l|lwz} %s,%d(%s)\n"; | |
b6c9286a MM |
3108 | } |
3109 | else | |
3110 | { | |
8f802bfb DE |
3111 | store_reg = "\tstd %s,%d(%s)\n"; |
3112 | load_reg = "\tlld %s,%d(%s)\n"; | |
b6c9286a | 3113 | } |
9878760c | 3114 | |
4697a36c MM |
3115 | if (TARGET_DEBUG_STACK) |
3116 | debug_stack_info (info); | |
9878760c RK |
3117 | |
3118 | /* Write .extern for any function we will call to save and restore fp | |
3119 | values. */ | |
b6c9286a | 3120 | if (info->first_fp_reg_save < 64 && !FP_SAVE_INLINE (info->first_fp_reg_save)) |
4d30c363 | 3121 | fprintf (file, "\t.extern %s%d%s\n\t.extern %s%d%s\n", |
4697a36c MM |
3122 | SAVE_FP_PREFIX, info->first_fp_reg_save - 32, SAVE_FP_SUFFIX, |
3123 | RESTORE_FP_PREFIX, info->first_fp_reg_save - 32, RESTORE_FP_SUFFIX); | |
9878760c RK |
3124 | |
3125 | /* Write .extern for truncation routines, if needed. */ | |
3126 | if (rs6000_trunc_used && ! trunc_defined) | |
3127 | { | |
e138174b ILT |
3128 | fprintf (file, "\t.extern .%s\n\t.extern .%s\n", |
3129 | RS6000_ITRUNC, RS6000_UITRUNC); | |
9878760c RK |
3130 | trunc_defined = 1; |
3131 | } | |
4697a36c | 3132 | |
c764f757 RK |
3133 | /* Write .extern for AIX common mode routines, if needed. */ |
3134 | if (! TARGET_POWER && ! TARGET_POWERPC && ! common_mode_defined) | |
3135 | { | |
f6709c70 JW |
3136 | fputs ("\t.extern __mulh\n", file); |
3137 | fputs ("\t.extern __mull\n", file); | |
3138 | fputs ("\t.extern __divss\n", file); | |
3139 | fputs ("\t.extern __divus\n", file); | |
3140 | fputs ("\t.extern __quoss\n", file); | |
3141 | fputs ("\t.extern __quous\n", file); | |
c764f757 RK |
3142 | common_mode_defined = 1; |
3143 | } | |
9878760c | 3144 | |
979721f8 | 3145 | /* For V.4, update stack before we do any saving and set back pointer. */ |
c81bebd7 | 3146 | if (info->push_p && (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS)) |
979721f8 MM |
3147 | { |
3148 | if (info->total_size < 32767) | |
3149 | { | |
3150 | asm_fprintf (file, | |
3151 | (TARGET_32BIT) ? "\t{stu|stwu} %s,%d(%s)\n" : "\tstdu %s,%d(%s)\n", | |
3152 | reg_names[1], - info->total_size, reg_names[1]); | |
3153 | sp_offset = info->total_size; | |
3154 | } | |
3155 | else | |
3156 | { | |
3157 | int neg_size = - info->total_size; | |
3158 | sp_reg = 12; | |
3159 | asm_fprintf (file, "\tmr %s,%s\n", reg_names[12], reg_names[1]); | |
3160 | asm_fprintf (file, "\t{liu|lis} %s,%d\n\t{oril|ori} %s,%s,%d\n", | |
3161 | reg_names[0], (neg_size >> 16) & 0xffff, | |
3162 | reg_names[0], reg_names[0], neg_size & 0xffff); | |
3163 | asm_fprintf (file, | |
3164 | (TARGET_32BIT) ? "\t{stux|stwux} %s,%s,%s\n" : "\tstdux %s,%s,%s\n", | |
3165 | reg_names[1], reg_names[1], reg_names[0]); | |
3166 | } | |
3167 | } | |
3168 | ||
9878760c | 3169 | /* If we use the link register, get it into r0. */ |
4697a36c MM |
3170 | if (info->lr_save_p) |
3171 | asm_fprintf (file, "\tmflr %s\n", reg_names[0]); | |
9878760c RK |
3172 | |
3173 | /* If we need to save CR, put it into r12. */ | |
979721f8 | 3174 | if (info->cr_save_p && sp_reg != 12) |
4697a36c | 3175 | asm_fprintf (file, "\tmfcr %s\n", reg_names[12]); |
9878760c RK |
3176 | |
3177 | /* Do any required saving of fpr's. If only one or two to save, do it | |
53322b0c RK |
3178 | ourself. Otherwise, call function. Note that since they are statically |
3179 | linked, we do not need a nop following them. */ | |
4697a36c | 3180 | if (FP_SAVE_INLINE (info->first_fp_reg_save)) |
bacbde18 | 3181 | { |
4697a36c | 3182 | int regno = info->first_fp_reg_save; |
979721f8 | 3183 | int loc = info->fp_save_offset + sp_offset; |
4697a36c MM |
3184 | |
3185 | for ( ; regno < 64; regno++, loc += 8) | |
979721f8 | 3186 | asm_fprintf (file, "\tstfd %s,%d(%s)\n", reg_names[regno], loc, reg_names[sp_reg]); |
bacbde18 | 3187 | } |
4697a36c MM |
3188 | else if (info->first_fp_reg_save != 64) |
3189 | asm_fprintf (file, "\tbl %s%d%s\n", SAVE_FP_PREFIX, | |
3190 | info->first_fp_reg_save - 32, SAVE_FP_SUFFIX); | |
9878760c RK |
3191 | |
3192 | /* Now save gpr's. */ | |
4697a36c | 3193 | if (! TARGET_MULTIPLE || info->first_gp_reg_save == 31 || TARGET_64BIT) |
85638c0d | 3194 | { |
4697a36c | 3195 | int regno = info->first_gp_reg_save; |
979721f8 | 3196 | int loc = info->gp_save_offset + sp_offset; |
85638c0d | 3197 | |
4697a36c | 3198 | for ( ; regno < 32; regno++, loc += reg_size) |
979721f8 | 3199 | asm_fprintf (file, store_reg, reg_names[regno], loc, reg_names[sp_reg]); |
85638c0d RK |
3200 | } |
3201 | ||
4697a36c MM |
3202 | else if (info->first_gp_reg_save != 32) |
3203 | asm_fprintf (file, "\t{stm|stmw} %s,%d(%s)\n", | |
3204 | reg_names[info->first_gp_reg_save], | |
979721f8 MM |
3205 | info->gp_save_offset + sp_offset, |
3206 | reg_names[sp_reg]); | |
9878760c | 3207 | |
b6c9286a MM |
3208 | /* Save main's arguments if we need to call a function */ |
3209 | #ifdef NAME__MAIN | |
3210 | if (info->main_save_p) | |
3211 | { | |
3212 | int regno; | |
5ebfb2ba | 3213 | int loc = info->main_save_offset + sp_offset; |
b6c9286a MM |
3214 | int size = info->main_size; |
3215 | ||
3216 | for (regno = 3; size > 0; regno++, loc -= reg_size, size -= reg_size) | |
979721f8 | 3217 | asm_fprintf (file, store_reg, reg_names[regno], loc, reg_names[sp_reg]); |
b6c9286a MM |
3218 | } |
3219 | #endif | |
3220 | ||
9878760c | 3221 | /* Save lr if we used it. */ |
4697a36c | 3222 | if (info->lr_save_p) |
979721f8 MM |
3223 | asm_fprintf (file, store_reg, reg_names[0], info->lr_save_offset + sp_offset, |
3224 | reg_names[sp_reg]); | |
9878760c RK |
3225 | |
3226 | /* Save CR if we use any that must be preserved. */ | |
4697a36c | 3227 | if (info->cr_save_p) |
979721f8 MM |
3228 | { |
3229 | if (sp_reg == 12) /* If r12 is used to hold the original sp, copy cr now */ | |
3230 | { | |
3231 | asm_fprintf (file, "\tmfcr %s\n", reg_names[0]); | |
3232 | asm_fprintf (file, store_reg, reg_names[0], | |
3233 | info->cr_save_offset + sp_offset, | |
3234 | reg_names[sp_reg]); | |
3235 | } | |
3236 | else | |
3237 | asm_fprintf (file, store_reg, reg_names[12], info->cr_save_offset + sp_offset, | |
3238 | reg_names[sp_reg]); | |
3239 | } | |
9878760c | 3240 | |
b6c9286a | 3241 | if (info->toc_save_p) |
979721f8 MM |
3242 | asm_fprintf (file, store_reg, reg_names[2], info->toc_save_offset + sp_offset, |
3243 | reg_names[sp_reg]); | |
b6c9286a | 3244 | |
979721f8 MM |
3245 | /* NT needs us to probe the stack frame every 4k pages for large frames, so |
3246 | do it here. */ | |
3247 | if (DEFAULT_ABI == ABI_NT && info->total_size > 4096) | |
3248 | { | |
3249 | if (info->total_size < 32768) | |
3250 | { | |
3251 | int probe_offset = 4096; | |
3252 | while (probe_offset < info->total_size) | |
3253 | { | |
3254 | asm_fprintf (file, "\t{l|lwz} %s,%d(%s)\n", reg_names[0], -probe_offset, reg_names[1]); | |
3255 | probe_offset += 4096; | |
3256 | } | |
3257 | } | |
3258 | else | |
3259 | { | |
3260 | int probe_iterations = info->total_size / 4096; | |
3261 | static int probe_labelno = 0; | |
3262 | char buf[256]; | |
3263 | ||
3264 | if (probe_iterations < 32768) | |
3265 | asm_fprintf (file, "\tli %s,%d\n", reg_names[12], probe_iterations); | |
3266 | else | |
3267 | { | |
3268 | asm_fprintf (file, "\tlis %s,%d\n", reg_names[12], probe_iterations >> 16); | |
3269 | if (probe_iterations & 0xffff) | |
3270 | asm_fprintf (file, "\tori %s,%s,%d\n", reg_names[12], reg_names[12], | |
3271 | probe_iterations & 0xffff); | |
3272 | } | |
3273 | asm_fprintf (file, "\tmtctr %s\n", reg_names[12]); | |
3274 | asm_fprintf (file, "\tmr %s,%s\n", reg_names[12], reg_names[1]); | |
3275 | ASM_OUTPUT_INTERNAL_LABEL (file, "LCprobe", probe_labelno); | |
3276 | asm_fprintf (file, "\t{lu|lwzu} %s,-4096(%s)\n", reg_names[0], reg_names[12]); | |
3277 | ASM_GENERATE_INTERNAL_LABEL (buf, "LCprobe", probe_labelno); | |
3278 | fputs ("\tbdnz ", file); | |
3279 | assemble_name (file, buf); | |
3280 | fputs ("\n", file); | |
3281 | } | |
3282 | } | |
3283 | ||
3284 | /* Update stack and set back pointer and we have already done so for V.4. */ | |
c81bebd7 | 3285 | if (info->push_p && DEFAULT_ABI != ABI_V4 && DEFAULT_ABI != ABI_SOLARIS) |
9878760c | 3286 | { |
4697a36c MM |
3287 | if (info->total_size < 32767) |
3288 | asm_fprintf (file, | |
8f802bfb | 3289 | (TARGET_32BIT) ? "\t{stu|stwu} %s,%d(%s)\n" : "\tstdu %s,%d(%s)\n", |
4697a36c | 3290 | reg_names[1], - info->total_size, reg_names[1]); |
9878760c RK |
3291 | else |
3292 | { | |
ef7a1424 | 3293 | int neg_size = - info->total_size; |
4697a36c | 3294 | asm_fprintf (file, "\t{liu|lis} %s,%d\n\t{oril|ori} %s,%s,%d\n", |
ef7a1424 RK |
3295 | reg_names[0], (neg_size >> 16) & 0xffff, |
3296 | reg_names[0], reg_names[0], neg_size & 0xffff); | |
4697a36c | 3297 | asm_fprintf (file, |
8f802bfb | 3298 | (TARGET_32BIT) ? "\t{stux|stwux} %s,%s,%s\n" : "\tstdux %s,%s,%s\n", |
4697a36c | 3299 | reg_names[1], reg_names[1], reg_names[0]); |
9878760c RK |
3300 | } |
3301 | } | |
3302 | ||
3303 | /* Set frame pointer, if needed. */ | |
3304 | if (frame_pointer_needed) | |
4697a36c | 3305 | asm_fprintf (file, "\tmr %s,%s\n", reg_names[31], reg_names[1]); |
1875cc88 | 3306 | |
b6c9286a MM |
3307 | #ifdef NAME__MAIN |
3308 | /* If we need to call a function to set things up for main, do so now | |
3309 | before dealing with the TOC. */ | |
3310 | if (info->main_p) | |
3311 | { | |
3312 | char *prefix = ""; | |
3313 | ||
3314 | switch (DEFAULT_ABI) | |
3315 | { | |
3316 | case ABI_AIX: prefix = "."; break; | |
3317 | case ABI_NT: prefix = ".."; break; | |
3318 | } | |
3319 | ||
3320 | fprintf (file, "\tbl %s%s\n", prefix, NAME__MAIN); | |
3321 | #ifdef RS6000_CALL_GLUE2 | |
3322 | fprintf (file, "\t%s%s%s\n", RS6000_CALL_GLUE2, prefix, NAME_MAIN); | |
3323 | #else | |
3324 | #ifdef RS6000_CALL_GLUE | |
3325 | if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_NT) | |
3326 | fprintf (file, "\t%s\n", RS6000_CALL_GLUE); | |
3327 | #endif | |
3328 | #endif | |
3329 | ||
3330 | if (info->main_save_p) | |
3331 | { | |
3332 | int regno; | |
3333 | int loc; | |
3334 | int size = info->main_size; | |
3335 | ||
3336 | if (info->total_size < 32767) | |
3337 | { | |
3338 | loc = info->total_size + info->main_save_offset; | |
3339 | for (regno = 3; size > 0; regno++, size -= reg_size, loc -= reg_size) | |
3340 | asm_fprintf (file, load_reg, reg_names[regno], loc, reg_names[1]); | |
3341 | } | |
3342 | else | |
5ebfb2ba MM |
3343 | { |
3344 | int neg_size = info->main_save_offset - info->total_size; | |
3345 | loc = 0; | |
3346 | asm_fprintf (file, "\t{liu|lis} %s,%d\n\t{oril|ori} %s,%s,%d\n", | |
3347 | reg_names[0], (neg_size >> 16) & 0xffff, | |
3348 | reg_names[0], reg_names[0], neg_size & 0xffff); | |
979721f8 | 3349 | |
b6c9286a MM |
3350 | asm_fprintf (file, "\t{sf|subf} %s,%s,%s\n", reg_names[0], reg_names[0], |
3351 | reg_names[1]); | |
3352 | ||
3353 | for (regno = 3; size > 0; regno++, size -= reg_size, loc -= reg_size) | |
3354 | asm_fprintf (file, load_reg, reg_names[regno], loc, reg_names[0]); | |
3355 | } | |
3356 | } | |
3357 | } | |
3358 | #endif | |
3359 | ||
3360 | ||
1875cc88 JW |
3361 | /* If TARGET_MINIMAL_TOC, and the constant pool is needed, then load the |
3362 | TOC_TABLE address into register 30. */ | |
4697a36c | 3363 | if (TARGET_TOC && TARGET_MINIMAL_TOC && get_pool_size () != 0) |
3daf36a4 | 3364 | { |
d14a6d05 MM |
3365 | char buf[256]; |
3366 | ||
b6c9286a | 3367 | #ifdef TARGET_RELOCATABLE |
d14a6d05 MM |
3368 | if (TARGET_RELOCATABLE) |
3369 | { | |
874a0744 | 3370 | ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno); |
19d2d16f | 3371 | fputs ("\tbl ", file); |
d14a6d05 | 3372 | assemble_name (file, buf); |
19d2d16f | 3373 | putc ('\n', file); |
d14a6d05 | 3374 | |
874a0744 | 3375 | ASM_OUTPUT_INTERNAL_LABEL (file, "LCF", rs6000_pic_labelno); |
4697a36c | 3376 | fprintf (file, "\tmflr %s\n", reg_names[30]); |
3daf36a4 | 3377 | |
03a7e1a5 | 3378 | asm_fprintf (file, (TARGET_32BIT) ? "\t{l|lwz}" : "\tld"); |
4697a36c | 3379 | fprintf (file, " %s,(", reg_names[0]); |
874a0744 MM |
3380 | ASM_GENERATE_INTERNAL_LABEL (buf, "LCL", rs6000_pic_labelno); |
3381 | assemble_name (file, buf); | |
19d2d16f | 3382 | putc ('-', file); |
874a0744 MM |
3383 | ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno); |
3384 | assemble_name (file, buf); | |
4697a36c MM |
3385 | fprintf (file, ")(%s)\n", reg_names[30]); |
3386 | asm_fprintf (file, "\t{cax|add} %s,%s,%s\n", | |
3387 | reg_names[30], reg_names[0], reg_names[30]); | |
874a0744 | 3388 | rs6000_pic_labelno++; |
d14a6d05 | 3389 | } |
b6c9286a MM |
3390 | else |
3391 | #endif | |
3392 | ||
3393 | switch (DEFAULT_ABI) | |
3394 | { | |
3395 | case ABI_V4: | |
c81bebd7 | 3396 | case ABI_SOLARIS: |
b6c9286a | 3397 | case ABI_AIX_NODESC: |
8f802bfb | 3398 | if (TARGET_32BIT) |
b6c9286a MM |
3399 | { |
3400 | ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1); | |
3401 | asm_fprintf (file, "\t{cau|addis} %s,%s,", reg_names[30], reg_names[0]); | |
3402 | assemble_name (file, buf); | |
3403 | asm_fprintf (file, "@ha\n"); | |
3404 | if (TARGET_NEW_MNEMONICS) | |
3405 | { | |
3406 | asm_fprintf (file, "\taddi %s,%s,", reg_names[30], reg_names[30]); | |
3407 | assemble_name (file, buf); | |
3408 | asm_fprintf (file, "@l\n"); | |
3409 | } | |
3410 | else | |
3411 | { | |
3412 | asm_fprintf (file, "\tcal %s,", reg_names[30]); | |
3413 | assemble_name (file, buf); | |
3414 | asm_fprintf (file, "@l(%s)\n", reg_names[30]); | |
3415 | } | |
3416 | } | |
3417 | else | |
3418 | abort (); | |
3419 | ||
3420 | break; | |
3421 | ||
3422 | case ABI_NT: | |
3423 | case ABI_AIX: | |
3424 | ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 0); | |
3425 | asm_fprintf (file, "\t{l|lwz} %s,", reg_names[30]); | |
3933e0e1 | 3426 | assemble_name (file, buf); |
b6c9286a MM |
3427 | asm_fprintf (file, "(%s)\n", reg_names[2]); |
3428 | break; | |
3933e0e1 | 3429 | } |
b6c9286a | 3430 | } |
4697a36c | 3431 | |
b6c9286a MM |
3432 | if (DEFAULT_ABI == ABI_NT) |
3433 | { | |
3434 | assemble_name (file, XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0)); | |
3435 | fputs (".b:\n", file); | |
3daf36a4 | 3436 | } |
9878760c RK |
3437 | } |
3438 | ||
3439 | /* Write function epilogue. */ | |
3440 | ||
3441 | void | |
3442 | output_epilog (file, size) | |
3443 | FILE *file; | |
3444 | int size; | |
3445 | { | |
4697a36c | 3446 | rs6000_stack_t *info = rs6000_stack_info (); |
8f802bfb | 3447 | char *load_reg = (TARGET_32BIT) ? "\t{l|lwz} %s,%d(%s)\n" : "\tld %s,%d(%s)\n"; |
9878760c | 3448 | rtx insn = get_last_insn (); |
979721f8 MM |
3449 | int sp_reg = 1; |
3450 | int sp_offset = 0; | |
5b5040b9 | 3451 | int i; |
9878760c | 3452 | |
9878760c RK |
3453 | /* If the last insn was a BARRIER, we don't have to write anything except |
3454 | the trace table. */ | |
3455 | if (GET_CODE (insn) == NOTE) | |
3456 | insn = prev_nonnote_insn (insn); | |
3457 | if (insn == 0 || GET_CODE (insn) != BARRIER) | |
3458 | { | |
3459 | /* If we have a frame pointer, a call to alloca, or a large stack | |
3460 | frame, restore the old stack pointer using the backchain. Otherwise, | |
3461 | we know what size to update it with. */ | |
3462 | if (frame_pointer_needed || current_function_calls_alloca | |
4697a36c | 3463 | || info->total_size > 32767) |
979721f8 MM |
3464 | { |
3465 | /* Under V.4, don't reset the stack pointer until after we're done | |
3466 | loading the saved registers. */ | |
c81bebd7 | 3467 | if (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) |
979721f8 MM |
3468 | sp_reg = 11; |
3469 | ||
3470 | asm_fprintf (file, load_reg, reg_names[sp_reg], 0, reg_names[1]); | |
3471 | } | |
4697a36c MM |
3472 | else if (info->push_p) |
3473 | { | |
c81bebd7 | 3474 | if (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) |
979721f8 MM |
3475 | sp_offset = info->total_size; |
3476 | else if (TARGET_NEW_MNEMONICS) | |
4697a36c MM |
3477 | asm_fprintf (file, "\taddi %s,%s,%d\n", reg_names[1], reg_names[1], info->total_size); |
3478 | else | |
3479 | asm_fprintf (file, "\tcal %s,%d(%s)\n", reg_names[1], info->total_size, reg_names[1]); | |
3480 | } | |
9878760c | 3481 | |
b4ac57ab | 3482 | /* Get the old lr if we saved it. */ |
4697a36c | 3483 | if (info->lr_save_p) |
979721f8 | 3484 | asm_fprintf (file, load_reg, reg_names[0], info->lr_save_offset + sp_offset, reg_names[sp_reg]); |
9878760c RK |
3485 | |
3486 | /* Get the old cr if we saved it. */ | |
4697a36c | 3487 | if (info->cr_save_p) |
979721f8 | 3488 | asm_fprintf (file, load_reg, reg_names[12], info->cr_save_offset + sp_offset, reg_names[sp_reg]); |
9878760c | 3489 | |
b4ac57ab | 3490 | /* Set LR here to try to overlap restores below. */ |
4697a36c MM |
3491 | if (info->lr_save_p) |
3492 | asm_fprintf (file, "\tmtlr %s\n", reg_names[0]); | |
b4ac57ab | 3493 | |
9878760c | 3494 | /* Restore gpr's. */ |
4697a36c | 3495 | if (! TARGET_MULTIPLE || info->first_gp_reg_save == 31 || TARGET_64BIT) |
85638c0d | 3496 | { |
4697a36c | 3497 | int regno = info->first_gp_reg_save; |
979721f8 | 3498 | int loc = info->gp_save_offset + sp_offset; |
8f802bfb | 3499 | int reg_size = (TARGET_32BIT) ? 4 : 8; |
85638c0d | 3500 | |
4697a36c | 3501 | for ( ; regno < 32; regno++, loc += reg_size) |
979721f8 | 3502 | asm_fprintf (file, load_reg, reg_names[regno], loc, reg_names[sp_reg]); |
85638c0d RK |
3503 | } |
3504 | ||
4697a36c MM |
3505 | else if (info->first_gp_reg_save != 32) |
3506 | asm_fprintf (file, "\t{lm|lmw} %s,%d(%s)\n", | |
3507 | reg_names[info->first_gp_reg_save], | |
979721f8 MM |
3508 | info->gp_save_offset + sp_offset, |
3509 | reg_names[sp_reg]); | |
9878760c | 3510 | |
b4ac57ab | 3511 | /* Restore fpr's if we can do it without calling a function. */ |
4697a36c MM |
3512 | if (FP_SAVE_INLINE (info->first_fp_reg_save)) |
3513 | { | |
3514 | int regno = info->first_fp_reg_save; | |
979721f8 | 3515 | int loc = info->fp_save_offset + sp_offset; |
4697a36c MM |
3516 | |
3517 | for ( ; regno < 64; regno++, loc += 8) | |
979721f8 | 3518 | asm_fprintf (file, "\tlfd %s,%d(%s)\n", reg_names[regno], loc, reg_names[sp_reg]); |
4697a36c | 3519 | } |
9878760c | 3520 | |
28edebac RK |
3521 | /* If we saved cr, restore it here. Just those of cr2, cr3, and cr4 |
3522 | that were used. */ | |
4697a36c MM |
3523 | if (info->cr_save_p) |
3524 | asm_fprintf (file, "\tmtcrf %d,%s\n", | |
85638c0d RK |
3525 | (regs_ever_live[70] != 0) * 0x20 |
3526 | + (regs_ever_live[71] != 0) * 0x10 | |
4697a36c | 3527 | + (regs_ever_live[72] != 0) * 0x8, reg_names[12]); |
9878760c | 3528 | |
979721f8 MM |
3529 | /* If this is V.4, unwind the stack pointer after all of the loads have been done */ |
3530 | if (sp_offset) | |
3531 | { | |
3532 | if (TARGET_NEW_MNEMONICS) | |
3533 | asm_fprintf (file, "\taddi %s,%s,%d\n", reg_names[1], reg_names[1], sp_offset); | |
3534 | else | |
3535 | asm_fprintf (file, "\tcal %s,%d(%s)\n", reg_names[1], sp_offset, reg_names[1]); | |
3536 | } | |
3537 | else if (sp_reg != 1) | |
3538 | asm_fprintf (file, "\tmr %s,%s\n", reg_names[1], reg_names[sp_reg]); | |
3539 | ||
b4ac57ab RS |
3540 | /* If we have to restore more than two FP registers, branch to the |
3541 | restore function. It will return to our caller. */ | |
4697a36c MM |
3542 | if (info->first_fp_reg_save != 64 && !FP_SAVE_INLINE (info->first_fp_reg_save)) |
3543 | asm_fprintf (file, "\tb %s%d%s\n", RESTORE_FP_PREFIX, | |
3544 | info->first_fp_reg_save - 32, RESTORE_FP_SUFFIX); | |
b4ac57ab | 3545 | else |
85638c0d | 3546 | asm_fprintf (file, "\t{br|blr}\n"); |
9878760c | 3547 | } |
b4ac57ab | 3548 | |
9b30bae2 | 3549 | /* Output a traceback table here. See /usr/include/sys/debug.h for info |
314fc5a9 ILT |
3550 | on its format. |
3551 | ||
3552 | We don't output a traceback table if -finhibit-size-directive was | |
3553 | used. The documentation for -finhibit-size-directive reads | |
3554 | ``don't output a @code{.size} assembler directive, or anything | |
3555 | else that would cause trouble if the function is split in the | |
3556 | middle, and the two halves are placed at locations far apart in | |
3557 | memory.'' The traceback table has this property, since it | |
3558 | includes the offset from the start of the function to the | |
4d30c363 MM |
3559 | traceback table itself. |
3560 | ||
3561 | System V.4 Powerpc's (and the embedded ABI derived from it) use a | |
b6c9286a MM |
3562 | different traceback table. */ |
3563 | if (DEFAULT_ABI == ABI_AIX && ! flag_inhibit_size_directive) | |
9b30bae2 | 3564 | { |
314fc5a9 ILT |
3565 | char *fname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0); |
3566 | int fixed_parms, float_parms, parm_info; | |
3567 | int i; | |
3568 | ||
b6c9286a MM |
3569 | while (*fname == '.') /* V.4 encodes . in the name */ |
3570 | fname++; | |
3571 | ||
314fc5a9 ILT |
3572 | /* Need label immediately before tbtab, so we can compute its offset |
3573 | from the function start. */ | |
3574 | if (*fname == '*') | |
3575 | ++fname; | |
3576 | ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT"); | |
3577 | ASM_OUTPUT_LABEL (file, fname); | |
3578 | ||
3579 | /* The .tbtab pseudo-op can only be used for the first eight | |
3580 | expressions, since it can't handle the possibly variable | |
3581 | length fields that follow. However, if you omit the optional | |
3582 | fields, the assembler outputs zeros for all optional fields | |
3583 | anyways, giving each variable length field is minimum length | |
3584 | (as defined in sys/debug.h). Thus we can not use the .tbtab | |
3585 | pseudo-op at all. */ | |
3586 | ||
3587 | /* An all-zero word flags the start of the tbtab, for debuggers | |
3588 | that have to find it by searching forward from the entry | |
3589 | point or from the current pc. */ | |
19d2d16f | 3590 | fputs ("\t.long 0\n", file); |
314fc5a9 ILT |
3591 | |
3592 | /* Tbtab format type. Use format type 0. */ | |
19d2d16f | 3593 | fputs ("\t.byte 0,", file); |
314fc5a9 ILT |
3594 | |
3595 | /* Language type. Unfortunately, there doesn't seem to be any | |
3596 | official way to get this info, so we use language_string. C | |
3597 | is 0. C++ is 9. No number defined for Obj-C, so use the | |
3598 | value for C for now. */ | |
3599 | if (! strcmp (language_string, "GNU C") | |
3600 | || ! strcmp (language_string, "GNU Obj-C")) | |
3601 | i = 0; | |
3602 | else if (! strcmp (language_string, "GNU F77")) | |
3603 | i = 1; | |
3604 | else if (! strcmp (language_string, "GNU Ada")) | |
3605 | i = 3; | |
3606 | else if (! strcmp (language_string, "GNU PASCAL")) | |
3607 | i = 2; | |
3608 | else if (! strcmp (language_string, "GNU C++")) | |
3609 | i = 9; | |
3610 | else | |
3611 | abort (); | |
3612 | fprintf (file, "%d,", i); | |
3613 | ||
3614 | /* 8 single bit fields: global linkage (not set for C extern linkage, | |
3615 | apparently a PL/I convention?), out-of-line epilogue/prologue, offset | |
3616 | from start of procedure stored in tbtab, internal function, function | |
3617 | has controlled storage, function has no toc, function uses fp, | |
3618 | function logs/aborts fp operations. */ | |
3619 | /* Assume that fp operations are used if any fp reg must be saved. */ | |
4697a36c | 3620 | fprintf (file, "%d,", (1 << 5) | ((info->first_fp_reg_save != 64) << 1)); |
314fc5a9 ILT |
3621 | |
3622 | /* 6 bitfields: function is interrupt handler, name present in | |
3623 | proc table, function calls alloca, on condition directives | |
3624 | (controls stack walks, 3 bits), saves condition reg, saves | |
3625 | link reg. */ | |
3626 | /* The `function calls alloca' bit seems to be set whenever reg 31 is | |
3627 | set up as a frame pointer, even when there is no alloca call. */ | |
3628 | fprintf (file, "%d,", | |
3629 | ((1 << 6) | (frame_pointer_needed << 5) | |
4697a36c | 3630 | | (info->cr_save_p << 1) | (info->lr_save_p))); |
314fc5a9 ILT |
3631 | |
3632 | /* 3 bitfields: saves backchain, spare bit, number of fpr saved | |
3633 | (6 bits). */ | |
3634 | fprintf (file, "%d,", | |
4697a36c | 3635 | (info->push_p << 7) | (64 - info->first_fp_reg_save)); |
314fc5a9 ILT |
3636 | |
3637 | /* 2 bitfields: spare bits (2 bits), number of gpr saved (6 bits). */ | |
3638 | fprintf (file, "%d,", (32 - first_reg_to_save ())); | |
3639 | ||
3640 | { | |
3641 | /* Compute the parameter info from the function decl argument | |
3642 | list. */ | |
3643 | tree decl; | |
3644 | int next_parm_info_bit; | |
3645 | ||
3646 | next_parm_info_bit = 31; | |
3647 | parm_info = 0; | |
3648 | fixed_parms = 0; | |
3649 | float_parms = 0; | |
3650 | ||
3651 | for (decl = DECL_ARGUMENTS (current_function_decl); | |
3652 | decl; decl = TREE_CHAIN (decl)) | |
3653 | { | |
3654 | rtx parameter = DECL_INCOMING_RTL (decl); | |
3655 | enum machine_mode mode = GET_MODE (parameter); | |
3656 | ||
3657 | if (GET_CODE (parameter) == REG) | |
3658 | { | |
3659 | if (GET_MODE_CLASS (mode) == MODE_FLOAT) | |
3660 | { | |
3661 | int bits; | |
3662 | ||
3663 | float_parms++; | |
3664 | ||
3665 | if (mode == SFmode) | |
3666 | bits = 0x2; | |
3667 | else if (mode == DFmode) | |
3668 | bits = 0x3; | |
3669 | else | |
3670 | abort (); | |
3671 | ||
3672 | /* If only one bit will fit, don't or in this entry. */ | |
3673 | if (next_parm_info_bit > 0) | |
3674 | parm_info |= (bits << (next_parm_info_bit - 1)); | |
3675 | next_parm_info_bit -= 2; | |
3676 | } | |
3677 | else | |
3678 | { | |
3679 | fixed_parms += ((GET_MODE_SIZE (mode) | |
3680 | + (UNITS_PER_WORD - 1)) | |
3681 | / UNITS_PER_WORD); | |
3682 | next_parm_info_bit -= 1; | |
3683 | } | |
3684 | } | |
3685 | } | |
3686 | } | |
3687 | ||
3688 | /* Number of fixed point parameters. */ | |
3689 | /* This is actually the number of words of fixed point parameters; thus | |
3690 | an 8 byte struct counts as 2; and thus the maximum value is 8. */ | |
3691 | fprintf (file, "%d,", fixed_parms); | |
3692 | ||
3693 | /* 2 bitfields: number of floating point parameters (7 bits), parameters | |
3694 | all on stack. */ | |
3695 | /* This is actually the number of fp registers that hold parameters; | |
3696 | and thus the maximum value is 13. */ | |
3697 | /* Set parameters on stack bit if parameters are not in their original | |
3698 | registers, regardless of whether they are on the stack? Xlc | |
3699 | seems to set the bit when not optimizing. */ | |
3700 | fprintf (file, "%d\n", ((float_parms << 1) | (! optimize))); | |
3701 | ||
3702 | /* Optional fields follow. Some are variable length. */ | |
3703 | ||
3704 | /* Parameter types, left adjusted bit fields: 0 fixed, 10 single float, | |
3705 | 11 double float. */ | |
3706 | /* There is an entry for each parameter in a register, in the order that | |
3707 | they occur in the parameter list. Any intervening arguments on the | |
3708 | stack are ignored. If the list overflows a long (max possible length | |
3709 | 34 bits) then completely leave off all elements that don't fit. */ | |
3710 | /* Only emit this long if there was at least one parameter. */ | |
3711 | if (fixed_parms || float_parms) | |
3712 | fprintf (file, "\t.long %d\n", parm_info); | |
3713 | ||
3714 | /* Offset from start of code to tb table. */ | |
19d2d16f | 3715 | fputs ("\t.long ", file); |
314fc5a9 ILT |
3716 | ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT"); |
3717 | RS6000_OUTPUT_BASENAME (file, fname); | |
19d2d16f | 3718 | fputs ("-.", file); |
314fc5a9 | 3719 | RS6000_OUTPUT_BASENAME (file, fname); |
19d2d16f | 3720 | putc ('\n', file); |
314fc5a9 ILT |
3721 | |
3722 | /* Interrupt handler mask. */ | |
3723 | /* Omit this long, since we never set the interrupt handler bit | |
3724 | above. */ | |
3725 | ||
3726 | /* Number of CTL (controlled storage) anchors. */ | |
3727 | /* Omit this long, since the has_ctl bit is never set above. */ | |
3728 | ||
3729 | /* Displacement into stack of each CTL anchor. */ | |
3730 | /* Omit this list of longs, because there are no CTL anchors. */ | |
3731 | ||
3732 | /* Length of function name. */ | |
3733 | fprintf (file, "\t.short %d\n", strlen (fname)); | |
3734 | ||
3735 | /* Function name. */ | |
3736 | assemble_string (fname, strlen (fname)); | |
3737 | ||
3738 | /* Register for alloca automatic storage; this is always reg 31. | |
3739 | Only emit this if the alloca bit was set above. */ | |
3740 | if (frame_pointer_needed) | |
19d2d16f | 3741 | fputs ("\t.byte 31\n", file); |
9b30bae2 | 3742 | } |
4697a36c | 3743 | |
b6c9286a | 3744 | /* Reset varargs and save TOC indicator */ |
4697a36c | 3745 | rs6000_sysv_varargs_p = 0; |
b6c9286a | 3746 | rs6000_save_toc_p = 0; |
802a0058 MM |
3747 | rs6000_fpmem_size = 0; |
3748 | rs6000_fpmem_offset = 0; | |
62cb0901 | 3749 | pic_offset_table_rtx = (rtx)0; |
b6c9286a MM |
3750 | |
3751 | if (DEFAULT_ABI == ABI_NT) | |
3752 | { | |
3753 | RS6000_OUTPUT_BASENAME (file, XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0)); | |
3754 | fputs (".e:\nFE_MOT_RESVD..", file); | |
3755 | RS6000_OUTPUT_BASENAME (file, XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0)); | |
3756 | fputs (":\n", file); | |
3757 | } | |
9878760c RK |
3758 | } |
3759 | \f | |
3760 | /* Output a TOC entry. We derive the entry name from what is | |
3761 | being written. */ | |
3762 | ||
3763 | void | |
3764 | output_toc (file, x, labelno) | |
3765 | FILE *file; | |
3766 | rtx x; | |
3767 | int labelno; | |
3768 | { | |
3769 | char buf[256]; | |
3770 | char *name = buf; | |
b6c9286a | 3771 | char *real_name; |
9878760c RK |
3772 | rtx base = x; |
3773 | int offset = 0; | |
3774 | ||
4697a36c MM |
3775 | if (TARGET_NO_TOC) |
3776 | abort (); | |
3777 | ||
ff1720ed RK |
3778 | /* if we're going to put a double constant in the TOC, make sure it's |
3779 | aligned properly when strict alignment is on. */ | |
3780 | if (GET_CODE (x) == CONST_DOUBLE | |
3781 | && STRICT_ALIGNMENT | |
3782 | && GET_MODE (x) == DFmode | |
3783 | && ! (TARGET_NO_FP_IN_TOC && ! TARGET_MINIMAL_TOC)) { | |
3784 | ASM_OUTPUT_ALIGN (file, 3); | |
3785 | } | |
3786 | ||
3787 | ||
b6c9286a | 3788 | if (TARGET_ELF && TARGET_MINIMAL_TOC) |
d14a6d05 MM |
3789 | { |
3790 | ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC"); | |
3791 | fprintf (file, "%d = .-", labelno); | |
3792 | ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LCTOC"); | |
19d2d16f | 3793 | fputs ("1\n", file); |
d14a6d05 MM |
3794 | } |
3795 | else | |
d14a6d05 | 3796 | ASM_OUTPUT_INTERNAL_LABEL (file, "LC", labelno); |
9878760c | 3797 | |
37c37a57 RK |
3798 | /* Handle FP constants specially. Note that if we have a minimal |
3799 | TOC, things we put here aren't actually in the TOC, so we can allow | |
3800 | FP constants. */ | |
042259f2 | 3801 | if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == DFmode |
37c37a57 | 3802 | && ! (TARGET_NO_FP_IN_TOC && ! TARGET_MINIMAL_TOC)) |
9878760c | 3803 | { |
042259f2 DE |
3804 | REAL_VALUE_TYPE rv; |
3805 | long k[2]; | |
0adc764e | 3806 | |
042259f2 DE |
3807 | REAL_VALUE_FROM_CONST_DOUBLE (rv, x); |
3808 | REAL_VALUE_TO_TARGET_DOUBLE (rv, k); | |
1875cc88 | 3809 | if (TARGET_MINIMAL_TOC) |
042259f2 | 3810 | fprintf (file, "\t.long %ld\n\t.long %ld\n", k[0], k[1]); |
1875cc88 | 3811 | else |
0adc764e | 3812 | fprintf (file, "\t.tc FD_%lx_%lx[TC],%ld,%ld\n", |
042259f2 | 3813 | k[0], k[1], k[0], k[1]); |
9878760c RK |
3814 | return; |
3815 | } | |
3816 | else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == SFmode | |
37c37a57 | 3817 | && ! (TARGET_NO_FP_IN_TOC && ! TARGET_MINIMAL_TOC)) |
9878760c | 3818 | { |
042259f2 DE |
3819 | REAL_VALUE_TYPE rv; |
3820 | long l; | |
9878760c | 3821 | |
042259f2 DE |
3822 | REAL_VALUE_FROM_CONST_DOUBLE (rv, x); |
3823 | REAL_VALUE_TO_TARGET_SINGLE (rv, l); | |
3824 | ||
3825 | if (TARGET_MINIMAL_TOC) | |
3826 | fprintf (file, "\t.long %d\n", l); | |
3827 | else | |
3828 | fprintf (file, "\t.tc FS_%x[TC],%d\n", l, l); | |
3829 | return; | |
3830 | } | |
3831 | else if (GET_MODE (x) == DImode | |
3832 | && (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE) | |
3833 | && ! (TARGET_NO_FP_IN_TOC && ! TARGET_MINIMAL_TOC)) | |
3834 | { | |
3835 | HOST_WIDE_INT low; | |
3836 | HOST_WIDE_INT high; | |
3837 | ||
3838 | if (GET_CODE (x) == CONST_DOUBLE) | |
3839 | { | |
3840 | low = CONST_DOUBLE_LOW (x); | |
3841 | high = CONST_DOUBLE_HIGH (x); | |
3842 | } | |
3843 | else | |
3844 | #if HOST_BITS_PER_WIDE_INT == 32 | |
3845 | { | |
3846 | low = INTVAL (x); | |
3847 | high = (low < 0) ? ~0 : 0; | |
3848 | } | |
3849 | #else | |
3850 | { | |
3851 | low = INTVAL (x) & 0xffffffff; | |
3852 | high = (HOST_WIDE_INT) INTVAL (x) >> 32; | |
3853 | } | |
3854 | #endif | |
9878760c | 3855 | |
1875cc88 | 3856 | if (TARGET_MINIMAL_TOC) |
042259f2 | 3857 | fprintf (file, "\t.long %ld\n\t.long %ld\n", high, low); |
1875cc88 | 3858 | else |
042259f2 DE |
3859 | fprintf (file, "\t.tc ID_%lx_%lx[TC],%ld,%ld\n", |
3860 | high, low, high, low); | |
9878760c RK |
3861 | return; |
3862 | } | |
3863 | ||
3864 | if (GET_CODE (x) == CONST) | |
3865 | { | |
3866 | base = XEXP (XEXP (x, 0), 0); | |
3867 | offset = INTVAL (XEXP (XEXP (x, 0), 1)); | |
3868 | } | |
3869 | ||
3870 | if (GET_CODE (base) == SYMBOL_REF) | |
3871 | name = XSTR (base, 0); | |
3872 | else if (GET_CODE (base) == LABEL_REF) | |
3873 | ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (XEXP (base, 0))); | |
3874 | else if (GET_CODE (base) == CODE_LABEL) | |
3875 | ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (base)); | |
3876 | else | |
3877 | abort (); | |
3878 | ||
1875cc88 | 3879 | if (TARGET_MINIMAL_TOC) |
19d2d16f | 3880 | fputs ("\t.long ", file); |
1875cc88 JW |
3881 | else |
3882 | { | |
b6c9286a MM |
3883 | STRIP_NAME_ENCODING (real_name, name); |
3884 | fprintf (file, "\t.tc %s", real_name); | |
9878760c | 3885 | |
1875cc88 JW |
3886 | if (offset < 0) |
3887 | fprintf (file, ".N%d", - offset); | |
3888 | else if (offset) | |
3889 | fprintf (file, ".P%d", offset); | |
9878760c | 3890 | |
19d2d16f | 3891 | fputs ("[TC],", file); |
1875cc88 | 3892 | } |
9878760c | 3893 | output_addr_const (file, x); |
19d2d16f | 3894 | putc ('\n', file); |
9878760c RK |
3895 | } |
3896 | \f | |
3897 | /* Output an assembler pseudo-op to write an ASCII string of N characters | |
3898 | starting at P to FILE. | |
3899 | ||
3900 | On the RS/6000, we have to do this using the .byte operation and | |
3901 | write out special characters outside the quoted string. | |
3902 | Also, the assembler is broken; very long strings are truncated, | |
3903 | so we must artificially break them up early. */ | |
3904 | ||
3905 | void | |
3906 | output_ascii (file, p, n) | |
3907 | FILE *file; | |
3908 | char *p; | |
3909 | int n; | |
3910 | { | |
3911 | char c; | |
3912 | int i, count_string; | |
3913 | char *for_string = "\t.byte \""; | |
3914 | char *for_decimal = "\t.byte "; | |
3915 | char *to_close = NULL; | |
3916 | ||
3917 | count_string = 0; | |
3918 | for (i = 0; i < n; i++) | |
3919 | { | |
3920 | c = *p++; | |
3921 | if (c >= ' ' && c < 0177) | |
3922 | { | |
3923 | if (for_string) | |
3924 | fputs (for_string, file); | |
3925 | putc (c, file); | |
3926 | ||
3927 | /* Write two quotes to get one. */ | |
3928 | if (c == '"') | |
3929 | { | |
3930 | putc (c, file); | |
3931 | ++count_string; | |
3932 | } | |
3933 | ||
3934 | for_string = NULL; | |
3935 | for_decimal = "\"\n\t.byte "; | |
3936 | to_close = "\"\n"; | |
3937 | ++count_string; | |
3938 | ||
3939 | if (count_string >= 512) | |
3940 | { | |
3941 | fputs (to_close, file); | |
3942 | ||
3943 | for_string = "\t.byte \""; | |
3944 | for_decimal = "\t.byte "; | |
3945 | to_close = NULL; | |
3946 | count_string = 0; | |
3947 | } | |
3948 | } | |
3949 | else | |
3950 | { | |
3951 | if (for_decimal) | |
3952 | fputs (for_decimal, file); | |
3953 | fprintf (file, "%d", c); | |
3954 | ||
3955 | for_string = "\n\t.byte \""; | |
3956 | for_decimal = ", "; | |
3957 | to_close = "\n"; | |
3958 | count_string = 0; | |
3959 | } | |
3960 | } | |
3961 | ||
3962 | /* Now close the string if we have written one. Then end the line. */ | |
3963 | if (to_close) | |
3964 | fprintf (file, to_close); | |
3965 | } | |
3966 | \f | |
3967 | /* Generate a unique section name for FILENAME for a section type | |
3968 | represented by SECTION_DESC. Output goes into BUF. | |
3969 | ||
3970 | SECTION_DESC can be any string, as long as it is different for each | |
3971 | possible section type. | |
3972 | ||
3973 | We name the section in the same manner as xlc. The name begins with an | |
3974 | underscore followed by the filename (after stripping any leading directory | |
11e5fe42 RK |
3975 | names) with the last period replaced by the string SECTION_DESC. If |
3976 | FILENAME does not contain a period, SECTION_DESC is appended to the end of | |
3977 | the name. */ | |
9878760c RK |
3978 | |
3979 | void | |
3980 | rs6000_gen_section_name (buf, filename, section_desc) | |
3981 | char **buf; | |
3982 | char *filename; | |
3983 | char *section_desc; | |
3984 | { | |
11e5fe42 | 3985 | char *q, *after_last_slash, *last_period; |
9878760c RK |
3986 | char *p; |
3987 | int len; | |
9878760c RK |
3988 | |
3989 | after_last_slash = filename; | |
3990 | for (q = filename; *q; q++) | |
11e5fe42 RK |
3991 | { |
3992 | if (*q == '/') | |
3993 | after_last_slash = q + 1; | |
3994 | else if (*q == '.') | |
3995 | last_period = q; | |
3996 | } | |
9878760c | 3997 | |
11e5fe42 | 3998 | len = strlen (after_last_slash) + strlen (section_desc) + 2; |
9878760c RK |
3999 | *buf = (char *) permalloc (len); |
4000 | ||
4001 | p = *buf; | |
4002 | *p++ = '_'; | |
4003 | ||
4004 | for (q = after_last_slash; *q; q++) | |
4005 | { | |
11e5fe42 | 4006 | if (q == last_period) |
9878760c RK |
4007 | { |
4008 | strcpy (p, section_desc); | |
4009 | p += strlen (section_desc); | |
9878760c RK |
4010 | } |
4011 | ||
4012 | else if (isalnum (*q)) | |
4013 | *p++ = *q; | |
4014 | } | |
4015 | ||
11e5fe42 | 4016 | if (last_period == 0) |
9878760c RK |
4017 | strcpy (p, section_desc); |
4018 | else | |
4019 | *p = '\0'; | |
4020 | } | |
e165f3f0 RK |
4021 | \f |
4022 | /* Write function profiler code. */ | |
4023 | ||
4024 | void | |
4025 | output_function_profiler (file, labelno) | |
4026 | FILE *file; | |
4027 | int labelno; | |
4028 | { | |
4029 | /* The last used parameter register. */ | |
4030 | int last_parm_reg; | |
4031 | int i, j; | |
3daf36a4 | 4032 | char buf[100]; |
e165f3f0 | 4033 | |
b6c9286a MM |
4034 | if (DEFAULT_ABI != ABI_AIX) |
4035 | abort (); | |
4036 | ||
e165f3f0 RK |
4037 | /* Set up a TOC entry for the profiler label. */ |
4038 | toc_section (); | |
3daf36a4 ILT |
4039 | ASM_OUTPUT_INTERNAL_LABEL (file, "LPC", labelno); |
4040 | ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno); | |
35fc1624 | 4041 | if (TARGET_MINIMAL_TOC) |
3daf36a4 | 4042 | { |
19d2d16f | 4043 | fputs ("\t.long ", file); |
3daf36a4 | 4044 | assemble_name (file, buf); |
19d2d16f | 4045 | putc ('\n', file); |
3daf36a4 | 4046 | } |
35fc1624 | 4047 | else |
3daf36a4 | 4048 | { |
19d2d16f | 4049 | fputs ("\t.tc\t", file); |
3daf36a4 | 4050 | assemble_name (file, buf); |
19d2d16f | 4051 | fputs ("[TC],", file); |
3daf36a4 | 4052 | assemble_name (file, buf); |
19d2d16f | 4053 | putc ('\n', file); |
3daf36a4 | 4054 | } |
e165f3f0 RK |
4055 | text_section (); |
4056 | ||
4057 | /* Figure out last used parameter register. The proper thing to do is | |
4058 | to walk incoming args of the function. A function might have live | |
4059 | parameter registers even if it has no incoming args. */ | |
4060 | ||
4061 | for (last_parm_reg = 10; | |
4062 | last_parm_reg > 2 && ! regs_ever_live [last_parm_reg]; | |
4063 | last_parm_reg--) | |
4064 | ; | |
4065 | ||
4066 | /* Save parameter registers in regs 23-30. Don't overwrite reg 31, since | |
4067 | it might be set up as the frame pointer. */ | |
4068 | ||
4069 | for (i = 3, j = 30; i <= last_parm_reg; i++, j--) | |
19d2d16f | 4070 | asm_fprintf (file, "\tmr %d,%d\n", j, i); |
e165f3f0 RK |
4071 | |
4072 | /* Load location address into r3, and call mcount. */ | |
4073 | ||
3daf36a4 | 4074 | ASM_GENERATE_INTERNAL_LABEL (buf, "LPC", labelno); |
19d2d16f | 4075 | asm_fprintf (file, "\t{l|lwz} %s,", reg_names[3]); |
3daf36a4 | 4076 | assemble_name (file, buf); |
19d2d16f | 4077 | asm_fprintf (file, "(%s)\n\tbl .mcount\n", reg_names[2]); |
e165f3f0 RK |
4078 | |
4079 | /* Restore parameter registers. */ | |
4080 | ||
4081 | for (i = 3, j = 30; i <= last_parm_reg; i++, j--) | |
19d2d16f | 4082 | asm_fprintf (file, "\tmr %d,%d\n", i, j); |
e165f3f0 | 4083 | } |
a251ffd0 TG |
4084 | |
4085 | /* Adjust the cost of a scheduling dependency. Return the new cost of | |
4086 | a dependency LINK or INSN on DEP_INSN. COST is the current cost. */ | |
4087 | ||
4088 | int | |
a06faf84 | 4089 | rs6000_adjust_cost (insn, link, dep_insn, cost) |
a251ffd0 TG |
4090 | rtx insn; |
4091 | rtx link; | |
4092 | rtx dep_insn; | |
4093 | int cost; | |
4094 | { | |
4095 | if (! recog_memoized (insn)) | |
4096 | return 0; | |
4097 | ||
4098 | if (REG_NOTE_KIND (link) != 0) | |
4099 | return 0; | |
4100 | ||
4101 | if (REG_NOTE_KIND (link) == 0) | |
4102 | { | |
4103 | /* Data dependency; DEP_INSN writes a register that INSN reads some | |
4104 | cycles later. */ | |
4105 | ||
4106 | /* Tell the first scheduling pass about the latency between a mtctr | |
4107 | and bctr (and mtlr and br/blr). The first scheduling pass will not | |
4108 | know about this latency since the mtctr instruction, which has the | |
4109 | latency associated to it, will be generated by reload. */ | |
4110 | if (get_attr_type (insn) == TYPE_JMPREG) | |
4111 | return TARGET_POWER ? 5 : 4; | |
4112 | ||
4113 | /* Fall out to return default cost. */ | |
4114 | } | |
4115 | ||
4116 | return cost; | |
4117 | } | |
b6c9286a MM |
4118 | |
4119 | /* Return how many instructions the machine can issue per cycle */ | |
4120 | int get_issue_rate() | |
4121 | { | |
4122 | switch (rs6000_cpu_attr) { | |
4123 | case CPU_RIOS1: | |
4124 | return 3; /* ? */ | |
4125 | case CPU_RIOS2: | |
4126 | return 4; | |
4127 | case CPU_PPC601: | |
4128 | return 3; /* ? */ | |
b6c9286a MM |
4129 | case CPU_PPC603: |
4130 | return 2; | |
4131 | case CPU_PPC604: | |
4132 | return 4; | |
4133 | case CPU_PPC620: | |
4134 | return 4; | |
4135 | default: | |
4136 | return 1; | |
4137 | } | |
4138 | } | |
4139 | ||
4140 | \f | |
4141 | /* Output insns to flush the {data|instruction} caches after building a | |
4142 | trampoline. */ | |
4143 | ||
4144 | static void | |
4145 | rs6000_sync_trampoline (addr) | |
4146 | rtx addr; | |
4147 | { | |
4148 | enum machine_mode pmode = Pmode; | |
4149 | rtx reg = gen_reg_rtx (pmode); | |
4150 | rtx mem2; | |
4151 | rtx mem1; | |
4152 | int size = rs6000_trampoline_size (); | |
4153 | rtx (*sub_fcn) PROTO ((rtx, rtx, rtx)); | |
4154 | rtx (*cmp_fcn) PROTO ((rtx, rtx)); | |
4155 | rtx label; | |
4156 | ||
ac2a93a1 | 4157 | if (TARGET_32BIT) |
b6c9286a | 4158 | { |
ac2a93a1 DE |
4159 | sub_fcn = gen_subsi3; |
4160 | cmp_fcn = gen_cmpsi; | |
b6c9286a MM |
4161 | } |
4162 | else | |
4163 | { | |
ac2a93a1 DE |
4164 | sub_fcn = gen_subdi3; |
4165 | cmp_fcn = gen_cmpdi; | |
b6c9286a MM |
4166 | } |
4167 | ||
4168 | addr = force_reg (pmode, addr); | |
4169 | mem2 = gen_rtx (MEM, pmode, gen_rtx (PLUS, pmode, addr, reg)); | |
4170 | mem1 = gen_rtx (MEM, pmode, addr); | |
4171 | ||
4172 | /* Issue a loop of dcbst's to flush the data cache */ | |
4173 | emit_move_insn (reg, GEN_INT (size-4)); | |
4174 | label = gen_label_rtx (); | |
4175 | emit_label (label); | |
4176 | emit_insn (gen_dcbst (mem2, addr, reg)); | |
4177 | emit_insn ((*sub_fcn) (reg, reg, GEN_INT (4))); | |
4178 | emit_insn ((*cmp_fcn) (reg, const0_rtx)); | |
4179 | emit_jump_insn (gen_bgt (label)); | |
4180 | ||
4181 | /* Issue a sync after the dcbst's to let things settle down */ | |
4182 | emit_insn (gen_sync (mem1)); | |
4183 | ||
4184 | /* Issue a loop of icbi's to flush the instruction cache */ | |
4185 | emit_move_insn (reg, GEN_INT (size-4)); | |
4186 | label = gen_label_rtx (); | |
4187 | emit_label (label); | |
4188 | emit_insn (gen_icbi (mem2, addr, reg)); | |
4189 | emit_insn ((*sub_fcn) (reg, reg, GEN_INT (4))); | |
4190 | emit_insn ((*cmp_fcn) (reg, const0_rtx)); | |
4191 | emit_jump_insn (gen_bgt (label)); | |
4192 | ||
4193 | /* Issue a sync after the icbi's to let things settle down */ | |
4194 | emit_insn (gen_sync (mem1)); | |
4195 | ||
4196 | /* Finally issue an isync to synchronize the icache */ | |
4197 | emit_insn (gen_isync (mem1)); | |
4198 | } | |
4199 | ||
4200 | \f | |
4201 | /* Output assembler code for a block containing the constant parts | |
4202 | of a trampoline, leaving space for the variable parts. | |
4203 | ||
4204 | The trampoline should set the static chain pointer to value placed | |
4205 | into the trampoline and should branch to the specified routine. */ | |
4206 | ||
4207 | void | |
4208 | rs6000_trampoline_template (file) | |
4209 | FILE *file; | |
4210 | { | |
4211 | char *sc = reg_names[STATIC_CHAIN_REGNUM]; | |
4212 | char *r0 = reg_names[0]; | |
7c59dc5d | 4213 | char *r2 = reg_names[2]; |
b6c9286a MM |
4214 | |
4215 | switch (DEFAULT_ABI) | |
4216 | { | |
4217 | default: | |
4218 | abort (); | |
4219 | ||
4220 | /* Under AIX, this is not code at all, but merely a data area, | |
4221 | since that is the way all functions are called. The first word is | |
4222 | the address of the function, the second word is the TOC pointer (r2), | |
4223 | and the third word is the static chain value. */ | |
4224 | case ABI_AIX: | |
8f802bfb | 4225 | fprintf (file, "\t.long %s\n", (TARGET_32BIT) ? "0,0,0" : "0,0,0,0,0,0"); |
b6c9286a MM |
4226 | break; |
4227 | ||
4228 | ||
4229 | /* V.4/eabi function pointers are just a single pointer, so we need to | |
4230 | do the full gory code to load up the static chain. */ | |
4231 | case ABI_V4: | |
c81bebd7 | 4232 | case ABI_SOLARIS: |
b6c9286a MM |
4233 | case ABI_AIX_NODESC: |
4234 | if (STATIC_CHAIN_REGNUM == 0 || !TARGET_NEW_MNEMONICS) | |
4235 | abort (); | |
4236 | ||
8f802bfb | 4237 | if (TARGET_32BIT) |
b6c9286a MM |
4238 | { |
4239 | fprintf (file, "\tmflr %s\n", r0); /* offset 0 */ | |
4240 | fprintf (file, "\tbl .LTRAMP1\n"); /* offset 4 */ | |
4241 | fprintf (file, "\t.long 0,0\n"); /* offset 8 */ | |
4242 | fprintf (file, ".LTRAMP1:\n"); | |
4243 | fprintf (file, "\tmflr %s\n", sc); /* offset 20 */ | |
4244 | fprintf (file, "\tmtlr %s\n", r0); /* offset 24 */ | |
4245 | fprintf (file, "\tlwz %s,0(%s)\n", r0, sc); /* offset 28 */ | |
4246 | fprintf (file, "\tlwz %s,4(%s)\n", sc, sc); /* offset 32 */ | |
4247 | fprintf (file, "\tmtctr %s\n", r0); /* offset 36 */ | |
4248 | fprintf (file, "\tbctr\n"); /* offset 40 */ | |
4249 | } | |
8f802bfb DE |
4250 | else |
4251 | { | |
4252 | fprintf (file, "\tmflr %s\n", r0); /* offset 0 */ | |
4253 | fprintf (file, "\tbl .LTRAMP1\n"); /* offset 4 */ | |
4254 | fprintf (file, "\t.long 0,0,0,0\n"); /* offset 8 */ | |
4255 | fprintf (file, ".LTRAMP1:\n"); | |
4256 | fprintf (file, "\tmflr %s\n", sc); /* offset 28 */ | |
4257 | fprintf (file, "\tmtlr %s\n", r0); /* offset 32 */ | |
4258 | fprintf (file, "\tld %s,0(%s)\n", r0, sc); /* offset 36 */ | |
4259 | fprintf (file, "\tld %s,8(%s)\n", sc, sc); /* offset 40 */ | |
4260 | fprintf (file, "\tmtctr %s\n", r0); /* offset 44 */ | |
4261 | fprintf (file, "\tbctr\n"); /* offset 48 */ | |
4262 | } | |
b6c9286a MM |
4263 | break; |
4264 | ||
4265 | /* NT function pointers point to a two word area (real address, TOC) | |
4266 | which unfortunately does not include a static chain field. So we | |
7c59dc5d MM |
4267 | use the function field to point to ..LTRAMP1 and the toc field |
4268 | to point to the whole table. */ | |
b6c9286a | 4269 | case ABI_NT: |
7c59dc5d MM |
4270 | if (STATIC_CHAIN_REGNUM == 0 |
4271 | || STATIC_CHAIN_REGNUM == 2 | |
4272 | || TARGET_64BIT | |
4273 | || !TARGET_NEW_MNEMONICS) | |
b6c9286a MM |
4274 | abort (); |
4275 | ||
7c59dc5d MM |
4276 | fprintf (file, "\t.ualong 0\n"); /* offset 0 */ |
4277 | fprintf (file, "\t.ualong 0\n"); /* offset 4 */ | |
4278 | fprintf (file, "\t.ualong 0\n"); /* offset 8 */ | |
4279 | fprintf (file, "\t.ualong 0\n"); /* offset 12 */ | |
4280 | fprintf (file, "\t.ualong 0\n"); /* offset 16 */ | |
8bd04c56 | 4281 | fprintf (file, "..LTRAMP1..0:\n"); /* offset 20 */ |
7c59dc5d MM |
4282 | fprintf (file, "\tlwz %s,8(%s)\n", r0, r2); /* offset 24 */ |
4283 | fprintf (file, "\tlwz %s,12(%s)\n", sc, r2); /* offset 28 */ | |
4284 | fprintf (file, "\tmtctr %s\n", r0); /* offset 32 */ | |
4285 | fprintf (file, "\tlwz %s,16(%s)\n", r2, r2); /* offset 36 */ | |
4286 | fprintf (file, "\tbctr\n"); /* offset 40 */ | |
b6c9286a MM |
4287 | break; |
4288 | } | |
4289 | ||
4290 | return; | |
4291 | } | |
4292 | ||
4293 | /* Length in units of the trampoline for entering a nested function. */ | |
4294 | ||
4295 | int | |
4296 | rs6000_trampoline_size () | |
4297 | { | |
4298 | int ret = 0; | |
4299 | ||
4300 | switch (DEFAULT_ABI) | |
4301 | { | |
4302 | default: | |
4303 | abort (); | |
4304 | ||
4305 | case ABI_AIX: | |
8f802bfb | 4306 | ret = (TARGET_32BIT) ? 12 : 24; |
b6c9286a MM |
4307 | break; |
4308 | ||
4309 | case ABI_V4: | |
c81bebd7 | 4310 | case ABI_SOLARIS: |
b6c9286a | 4311 | case ABI_AIX_NODESC: |
03a7e1a5 | 4312 | ret = (TARGET_32BIT) ? 40 : 48; |
b6c9286a MM |
4313 | break; |
4314 | ||
4315 | case ABI_NT: | |
7c59dc5d | 4316 | ret = 20; |
b6c9286a MM |
4317 | break; |
4318 | } | |
4319 | ||
4320 | return ret; | |
4321 | } | |
4322 | ||
4323 | /* Emit RTL insns to initialize the variable parts of a trampoline. | |
4324 | FNADDR is an RTX for the address of the function's pure code. | |
4325 | CXT is an RTX for the static chain value for the function. */ | |
4326 | ||
4327 | void | |
4328 | rs6000_initialize_trampoline (addr, fnaddr, cxt) | |
4329 | rtx addr; | |
4330 | rtx fnaddr; | |
4331 | rtx cxt; | |
4332 | { | |
ac2a93a1 | 4333 | enum machine_mode pmode = Pmode; |
8bd04c56 MM |
4334 | int regsize = (TARGET_32BIT) ? 4 : 8; |
4335 | rtx ctx_reg = force_reg (pmode, cxt); | |
b6c9286a MM |
4336 | |
4337 | switch (DEFAULT_ABI) | |
4338 | { | |
4339 | default: | |
4340 | abort (); | |
4341 | ||
8bd04c56 MM |
4342 | /* Macros to shorten the code expansions below. */ |
4343 | #define MEM_DEREF(addr) gen_rtx (MEM, pmode, memory_address (pmode, addr)) | |
7c59dc5d MM |
4344 | #define MEM_PLUS(addr,offset) gen_rtx (MEM, pmode, memory_address (pmode, plus_constant (addr, offset))) |
4345 | ||
b6c9286a MM |
4346 | /* Under AIX, just build the 3 word function descriptor */ |
4347 | case ABI_AIX: | |
8bd04c56 MM |
4348 | { |
4349 | rtx fn_reg = gen_reg_rtx (pmode); | |
4350 | rtx toc_reg = gen_reg_rtx (pmode); | |
4351 | emit_move_insn (fn_reg, MEM_DEREF (fnaddr)); | |
4352 | emit_move_insn (toc_reg, MEM_PLUS (fnaddr, 4)); | |
4353 | emit_move_insn (MEM_DEREF (addr), fn_reg); | |
4354 | emit_move_insn (MEM_PLUS (addr, regsize), toc_reg); | |
4355 | emit_move_insn (MEM_PLUS (addr, 2*regsize), ctx_reg); | |
4356 | } | |
b6c9286a MM |
4357 | break; |
4358 | ||
4359 | /* Under V.4/eabi, update the two words after the bl to have the real | |
4360 | function address and the static chain. */ | |
4361 | case ABI_V4: | |
c81bebd7 | 4362 | case ABI_SOLARIS: |
b6c9286a | 4363 | case ABI_AIX_NODESC: |
8bd04c56 MM |
4364 | { |
4365 | rtx reg = gen_reg_rtx (pmode); | |
4366 | emit_move_insn (reg, fnaddr); | |
4367 | emit_move_insn (MEM_PLUS (addr, 8), reg); | |
4368 | emit_move_insn (MEM_PLUS (addr, 8 + regsize), ctx_reg); | |
4369 | rs6000_sync_trampoline (addr); | |
4370 | } | |
b6c9286a MM |
4371 | break; |
4372 | ||
8bd04c56 MM |
4373 | /* Under NT, update the first word to point to the ..LTRAMP1..0 header, |
4374 | the second word will point to the whole trampoline, third-fifth words | |
7c59dc5d | 4375 | will then have the real address, static chain, and toc value. */ |
b6c9286a | 4376 | case ABI_NT: |
8bd04c56 MM |
4377 | { |
4378 | rtx tramp_reg = gen_reg_rtx (pmode); | |
4379 | rtx fn_reg = gen_reg_rtx (pmode); | |
4380 | rtx toc_reg = gen_reg_rtx (pmode); | |
4381 | ||
4382 | emit_move_insn (tramp_reg, gen_rtx (SYMBOL_REF, pmode, "..LTRAMP1..0")); | |
4383 | addr = force_reg (pmode, addr); | |
4384 | emit_move_insn (fn_reg, MEM_DEREF (fnaddr)); | |
4385 | emit_move_insn (toc_reg, MEM_PLUS (fnaddr, regsize)); | |
4386 | emit_move_insn (MEM_DEREF (addr), tramp_reg); | |
4387 | emit_move_insn (MEM_PLUS (addr, regsize), addr); | |
4388 | emit_move_insn (MEM_PLUS (addr, 2*regsize), fn_reg); | |
4389 | emit_move_insn (MEM_PLUS (addr, 3*regsize), ctx_reg); | |
4390 | emit_move_insn (MEM_PLUS (addr, 4*regsize), gen_rtx (REG, pmode, 2)); | |
4391 | } | |
b6c9286a MM |
4392 | break; |
4393 | } | |
4394 | ||
4395 | return; | |
4396 | } | |
7509c759 MM |
4397 | |
4398 | \f | |
4399 | /* If defined, a C expression whose value is nonzero if IDENTIFIER | |
4400 | with arguments ARGS is a valid machine specific attribute for DECL. | |
4401 | The attributes in ATTRIBUTES have previously been assigned to DECL. */ | |
4402 | ||
4403 | int | |
4404 | rs6000_valid_decl_attribute_p (decl, attributes, identifier, args) | |
4405 | tree decl; | |
4406 | tree attributes; | |
4407 | tree identifier; | |
4408 | tree args; | |
4409 | { | |
4410 | return 0; | |
4411 | } | |
4412 | ||
4413 | /* If defined, a C expression whose value is nonzero if IDENTIFIER | |
4414 | with arguments ARGS is a valid machine specific attribute for TYPE. | |
4415 | The attributes in ATTRIBUTES have previously been assigned to TYPE. */ | |
4416 | ||
4417 | int | |
4418 | rs6000_valid_type_attribute_p (type, attributes, identifier, args) | |
4419 | tree type; | |
4420 | tree attributes; | |
4421 | tree identifier; | |
4422 | tree args; | |
4423 | { | |
4424 | if (TREE_CODE (type) != FUNCTION_TYPE | |
4425 | && TREE_CODE (type) != FIELD_DECL | |
4426 | && TREE_CODE (type) != TYPE_DECL) | |
4427 | return 0; | |
4428 | ||
6a4cee5f MM |
4429 | /* Longcall attribute says that the function is not within 2**26 bytes |
4430 | of the current function, and to do an indirect call. */ | |
4431 | if (is_attribute_p ("longcall", identifier)) | |
4432 | return (args == NULL_TREE); | |
4433 | ||
7509c759 MM |
4434 | if (DEFAULT_ABI == ABI_NT) |
4435 | { | |
4436 | /* Stdcall attribute says callee is responsible for popping arguments | |
4437 | if they are not variable. */ | |
4438 | if (is_attribute_p ("stdcall", identifier)) | |
4439 | return (args == NULL_TREE); | |
4440 | ||
4441 | /* Cdecl attribute says the callee is a normal C declaration */ | |
4442 | if (is_attribute_p ("cdecl", identifier)) | |
4443 | return (args == NULL_TREE); | |
4444 | ||
4445 | /* Dllimport attribute says says the caller is to call the function | |
4446 | indirectly through a __imp_<name> pointer. */ | |
4447 | if (is_attribute_p ("dllimport", identifier)) | |
4448 | return (args == NULL_TREE); | |
4449 | ||
4450 | /* Dllexport attribute says says the callee is to create a __imp_<name> | |
4451 | pointer. */ | |
4452 | if (is_attribute_p ("dllexport", identifier)) | |
4453 | return (args == NULL_TREE); | |
e56bb9ed MM |
4454 | |
4455 | /* Exception attribute allows the user to specify 1-2 strings or identifiers | |
4456 | that will fill in the 3rd and 4th fields of the structured exception | |
4457 | table. */ | |
4458 | if (is_attribute_p ("exception", identifier)) | |
4459 | { | |
4460 | int i; | |
4461 | ||
4462 | if (args == NULL_TREE) | |
4463 | return 0; | |
4464 | ||
4465 | for (i = 0; i < 2 && args != NULL_TREE; i++) | |
4466 | { | |
4467 | tree this_arg = TREE_VALUE (args); | |
4468 | args = TREE_PURPOSE (args); | |
4469 | ||
4470 | if (TREE_CODE (this_arg) != STRING_CST | |
4471 | && TREE_CODE (this_arg) != IDENTIFIER_NODE) | |
4472 | return 0; | |
4473 | } | |
4474 | ||
4475 | return (args == NULL_TREE); | |
4476 | } | |
7509c759 MM |
4477 | } |
4478 | ||
4479 | return 0; | |
4480 | } | |
4481 | ||
4482 | /* If defined, a C expression whose value is zero if the attributes on | |
4483 | TYPE1 and TYPE2 are incompatible, one if they are compatible, and | |
4484 | two if they are nearly compatible (which causes a warning to be | |
4485 | generated). */ | |
4486 | ||
4487 | int | |
4488 | rs6000_comp_type_attributes (type1, type2) | |
4489 | tree type1; | |
4490 | tree type2; | |
4491 | { | |
4492 | return 1; | |
4493 | } | |
4494 | ||
4495 | /* If defined, a C statement that assigns default attributes to newly | |
4496 | defined TYPE. */ | |
4497 | ||
4498 | void | |
4499 | rs6000_set_default_type_attributes (type) | |
4500 | tree type; | |
4501 | { | |
4502 | } | |
4503 | ||
4504 | /* Return a dll import reference corresponding to to a call's SYMBOL_REF */ | |
4505 | struct rtx_def * | |
4506 | rs6000_dll_import_ref (call_ref) | |
4507 | rtx call_ref; | |
4508 | { | |
4509 | char *call_name; | |
4510 | int len; | |
4511 | char *p; | |
4512 | rtx reg1, reg2; | |
4513 | tree node; | |
4514 | ||
4515 | if (GET_CODE (call_ref) != SYMBOL_REF) | |
4516 | abort (); | |
4517 | ||
4518 | call_name = XSTR (call_ref, 0); | |
4519 | len = sizeof ("__imp_") + strlen (call_name); | |
4520 | p = alloca (len); | |
4521 | reg2 = gen_reg_rtx (Pmode); | |
4522 | ||
4523 | strcpy (p, "__imp_"); | |
4524 | strcat (p, call_name); | |
4525 | node = get_identifier (p); | |
4526 | ||
4527 | reg1 = force_reg (Pmode, gen_rtx (SYMBOL_REF, VOIDmode, IDENTIFIER_POINTER (node))); | |
4528 | emit_move_insn (reg2, gen_rtx (MEM, Pmode, reg1)); | |
4529 | ||
4530 | return reg2; | |
4531 | } | |
4532 | ||
6a4cee5f MM |
4533 | /* Return a reference suitable for calling a function with the longcall attribute. */ |
4534 | struct rtx_def * | |
4535 | rs6000_longcall_ref (call_ref) | |
4536 | rtx call_ref; | |
4537 | { | |
4538 | char *call_name; | |
4539 | int len; | |
4540 | char *p; | |
4541 | rtx reg1, reg2; | |
4542 | tree node; | |
4543 | ||
4544 | if (GET_CODE (call_ref) != SYMBOL_REF) | |
4545 | return call_ref; | |
4546 | ||
4547 | /* System V adds '.' to the internal name, so skip them. */ | |
4548 | call_name = XSTR (call_ref, 0); | |
4549 | if (*call_name == '.') | |
4550 | { | |
4551 | while (*call_name == '.') | |
4552 | call_name++; | |
4553 | ||
4554 | node = get_identifier (call_name); | |
4555 | call_ref = gen_rtx (SYMBOL_REF, VOIDmode, IDENTIFIER_POINTER (node)); | |
4556 | } | |
4557 | ||
4558 | return force_reg (Pmode, call_ref); | |
4559 | } | |
4560 | ||
7509c759 MM |
4561 | \f |
4562 | /* A C statement or statements to switch to the appropriate section | |
4563 | for output of RTX in mode MODE. You can assume that RTX is some | |
4564 | kind of constant in RTL. The argument MODE is redundant except in | |
4565 | the case of a `const_int' rtx. Select the section by calling | |
4566 | `text_section' or one of the alternatives for other sections. | |
4567 | ||
4568 | Do not define this macro if you put all constants in the read-only | |
4569 | data section. */ | |
4570 | ||
4571 | #ifdef USING_SVR4_H | |
4572 | ||
4573 | void | |
4574 | rs6000_select_rtx_section (mode, x) | |
4575 | enum machine_mode mode; | |
4576 | rtx x; | |
4577 | { | |
4578 | if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x)) | |
4579 | toc_section (); | |
7509c759 MM |
4580 | else |
4581 | const_section (); | |
4582 | } | |
4583 | ||
4584 | /* A C statement or statements to switch to the appropriate | |
4585 | section for output of DECL. DECL is either a `VAR_DECL' node | |
4586 | or a constant of some sort. RELOC indicates whether forming | |
4587 | the initial value of DECL requires link-time relocations. */ | |
4588 | ||
4589 | void | |
4590 | rs6000_select_section (decl, reloc) | |
4591 | tree decl; | |
4592 | int reloc; | |
4593 | { | |
4594 | int size = int_size_in_bytes (TREE_TYPE (decl)); | |
4595 | ||
4596 | if (TREE_CODE (decl) == STRING_CST) | |
4597 | { | |
88228c4b | 4598 | if (! flag_writable_strings) |
7509c759 | 4599 | const_section (); |
7509c759 MM |
4600 | else |
4601 | data_section (); | |
4602 | } | |
4603 | else if (TREE_CODE (decl) == VAR_DECL) | |
4604 | { | |
4605 | if ((flag_pic && reloc) | |
4606 | || !TREE_READONLY (decl) | |
4607 | || TREE_SIDE_EFFECTS (decl) | |
4608 | || !DECL_INITIAL (decl) | |
4609 | || (DECL_INITIAL (decl) != error_mark_node | |
4610 | && !TREE_CONSTANT (DECL_INITIAL (decl)))) | |
4611 | { | |
d9407988 | 4612 | if (rs6000_sdata != SDATA_NONE && (size > 0) && (size <= g_switch_value)) |
7509c759 MM |
4613 | sdata_section (); |
4614 | else | |
4615 | data_section (); | |
4616 | } | |
4617 | else | |
4618 | { | |
d9407988 | 4619 | if (rs6000_sdata != SDATA_NONE && (size > 0) && (size <= g_switch_value)) |
c81bebd7 | 4620 | { |
d9407988 | 4621 | if (rs6000_sdata == SDATA_EABI) |
c81bebd7 MM |
4622 | sdata2_section (); |
4623 | else | |
4624 | sdata_section (); /* System V doesn't have .sdata2/.sbss2 */ | |
4625 | } | |
7509c759 MM |
4626 | else |
4627 | const_section (); | |
4628 | } | |
4629 | } | |
4630 | else | |
4631 | const_section (); | |
4632 | } | |
d9407988 MM |
4633 | |
4634 | \f | |
4635 | ||
4636 | /* If we are referencing a function that is static or is known to be | |
4637 | in this file, make the SYMBOL_REF special. We can use this to indicate | |
4638 | that we can branch to this function without emitting a no-op after the | |
4639 | call. For real AIX and NT calling sequences, we also replace the | |
4640 | function name with the real name (1 or 2 leading .'s), rather than | |
4641 | the function descriptor name. This saves a lot of overriding code | |
4642 | to readd the prefixes. */ | |
4643 | ||
4644 | void | |
4645 | rs6000_encode_section_info (decl) | |
4646 | tree decl; | |
4647 | { | |
4648 | if (TREE_CODE (decl) == FUNCTION_DECL) | |
4649 | { | |
4650 | rtx sym_ref = XEXP (DECL_RTL (decl), 0); | |
4651 | if (TREE_ASM_WRITTEN (decl) || ! TREE_PUBLIC (decl)) | |
4652 | SYMBOL_REF_FLAG (sym_ref) = 1; | |
4653 | ||
4654 | if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_NT) | |
4655 | { | |
4656 | char *prefix = (DEFAULT_ABI == ABI_AIX) ? "." : ".."; | |
4657 | char *str = permalloc (strlen (prefix) + 1 | |
4658 | + strlen (XSTR (sym_ref, 0))); | |
4659 | strcpy (str, prefix); | |
4660 | strcat (str, XSTR (sym_ref, 0)); | |
4661 | XSTR (sym_ref, 0) = str; | |
4662 | } | |
4663 | } | |
4664 | else if (rs6000_sdata != SDATA_NONE | |
4665 | && (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) | |
4666 | && TREE_CODE (decl) == VAR_DECL) | |
4667 | { | |
4668 | int size = int_size_in_bytes (TREE_TYPE (decl)); | |
4669 | tree section_name = DECL_SECTION_NAME (decl); | |
4670 | char *name = (char *)0; | |
4671 | int len = 0; | |
4672 | ||
4673 | if (section_name) | |
4674 | { | |
4675 | if (TREE_CODE (section_name) == STRING_CST) | |
4676 | { | |
4677 | name = TREE_STRING_POINTER (section_name); | |
4678 | len = TREE_STRING_LENGTH (section_name); | |
4679 | } | |
4680 | else | |
4681 | abort (); | |
4682 | } | |
4683 | ||
4684 | if ((size > 0 && size <= g_switch_value) | |
4685 | || (name | |
4686 | && ((len == sizeof (".sdata")-1 && strcmp (name, ".sdata") == 0) | |
4687 | || (len == sizeof (".sdata2")-1 && strcmp (name, ".sdata2") == 0) | |
4688 | || (len == sizeof (".sbss")-1 && strcmp (name, ".sbss") == 0) | |
4689 | || (len == sizeof (".sbss2")-1 && strcmp (name, ".sbss2") == 0) | |
4690 | || (len == sizeof (".PPC.EMB.sdata0")-1 && strcmp (name, ".PPC.EMB.sdata0") == 0) | |
4691 | || (len == sizeof (".PPC.EMB.sbss0")-1 && strcmp (name, ".PPC.EMB.sbss0") == 0)))) | |
4692 | { | |
4693 | rtx sym_ref = XEXP (DECL_RTL (decl), 0); | |
4694 | char *str = permalloc (2 + strlen (XSTR (sym_ref, 0))); | |
4695 | strcpy (str, "@"); | |
4696 | strcat (str, XSTR (sym_ref, 0)); | |
4697 | XSTR (sym_ref, 0) = str; | |
4698 | } | |
4699 | } | |
4700 | } | |
4701 | ||
7509c759 | 4702 | #endif /* USING_SVR4_H */ |
ba5e43aa MM |
4703 | |
4704 | \f | |
4705 | /* CYGNUS LOCAL mac */ | |
4706 | ||
4707 | /* Whether we are using m68k-compatible alignment. */ | |
4708 | ||
4709 | int mac68k_aligned; | |
4710 | ||
4711 | /* Most Mac compiler pragmas are unimportant, but we must recognize | |
4712 | the m68k alignment pragma, because that is crucial to transitions | |
4713 | to and from the m68k emulator on PowerMacs. */ | |
4714 | ||
4715 | int | |
4716 | handle_mac_pragma (finput, t) | |
4717 | FILE *finput; | |
4718 | tree t; | |
4719 | { | |
4720 | int retval = 0; | |
4721 | register char *pname; | |
4722 | char pbuf[200]; | |
4723 | int c, psize; | |
4724 | ||
4725 | if (TREE_CODE (t) != IDENTIFIER_NODE) | |
4726 | return 0; | |
4727 | ||
4728 | pname = IDENTIFIER_POINTER (t); | |
4729 | if (strcmp (pname, "segment") == 0) | |
4730 | { | |
ba5e43aa MM |
4731 | /* (should collect pbuf + 8 into a segment name) */ |
4732 | } | |
4733 | else if (strcmp (pname, "options") == 0) | |
4734 | { | |
4735 | c = getc (finput); | |
4736 | /* Skip over initial whitespace. */ | |
4737 | while (c == ' ' || c == '\t') | |
4738 | c = getc (finput); | |
4739 | ||
4740 | /* Return without doing anything if no content. */ | |
4741 | if (c == '\n' || c == EOF) | |
802a0058 MM |
4742 | { |
4743 | ungetc (c, finput); | |
4744 | return 0; | |
4745 | } | |
ba5e43aa MM |
4746 | |
4747 | /* Collect the rest of the line. */ | |
4748 | while (psize < sizeof (pbuf) - 1 && c != '\n') | |
4749 | { | |
4750 | pbuf[psize++] = c; | |
4751 | c = getc (finput); | |
4752 | } | |
4753 | ||
4754 | if (strncmp (pbuf, "align=mac68k", 12) == 0) | |
4755 | { | |
802a0058 MM |
4756 | mac68k_aligned = 1; |
4757 | retval = 1; | |
4758 | } | |
4759 | else if (strncmp (pbuf, "align=power", 11) == 0) | |
4760 | { | |
4761 | mac68k_aligned = 0; | |
4762 | retval = 1; | |
ba5e43aa MM |
4763 | } |
4764 | else if (strncmp (pbuf, "align=reset", 11) == 0) | |
4765 | { | |
802a0058 MM |
4766 | mac68k_aligned = 0; |
4767 | retval = 1; | |
ba5e43aa MM |
4768 | } |
4769 | } | |
4770 | ||
802a0058 | 4771 | return retval; |
ba5e43aa MM |
4772 | } |
4773 | /* END CYGNUS LOCAL mac */ |