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9878760c | 1 | /* Subroutines used for code generation on IBM RS/6000. |
9ebbca7d | 2 | Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, |
63b6e069 | 3 | 2000, 2001 Free Software Foundation, Inc. |
fab3bcc3 | 4 | Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu) |
9878760c RK |
5 | |
6 | This file is part of GNU CC. | |
7 | ||
8 | GNU CC is free software; you can redistribute it and/or modify | |
9 | it under the terms of the GNU General Public License as published by | |
10 | the Free Software Foundation; either version 2, or (at your option) | |
11 | any later version. | |
12 | ||
13 | GNU CC is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
19 | along with GNU CC; see the file COPYING. If not, write to | |
c15c9075 RK |
20 | the Free Software Foundation, 59 Temple Place - Suite 330, |
21 | Boston, MA 02111-1307, USA. */ | |
9878760c | 22 | |
956d6950 | 23 | #include "config.h" |
c4d38ccb | 24 | #include "system.h" |
9878760c RK |
25 | #include "rtl.h" |
26 | #include "regs.h" | |
27 | #include "hard-reg-set.h" | |
28 | #include "real.h" | |
29 | #include "insn-config.h" | |
30 | #include "conditions.h" | |
9878760c RK |
31 | #include "insn-attr.h" |
32 | #include "flags.h" | |
33 | #include "recog.h" | |
9878760c | 34 | #include "obstack.h" |
9b30bae2 | 35 | #include "tree.h" |
dfafc897 | 36 | #include "expr.h" |
2fc1c679 | 37 | #include "optabs.h" |
2a430ec1 | 38 | #include "except.h" |
a7df97e6 | 39 | #include "function.h" |
296b8152 | 40 | #include "output.h" |
d5fa86ba | 41 | #include "basic-block.h" |
d0101753 | 42 | #include "integrate.h" |
296b8152 | 43 | #include "toplev.h" |
c8023011 | 44 | #include "ggc.h" |
9ebbca7d GK |
45 | #include "hashtab.h" |
46 | #include "tm_p.h" | |
672a6f42 NB |
47 | #include "target.h" |
48 | #include "target-def.h" | |
9b30bae2 | 49 | |
7509c759 MM |
50 | #ifndef TARGET_NO_PROTOTYPE |
51 | #define TARGET_NO_PROTOTYPE 0 | |
52 | #endif | |
53 | ||
5248c961 | 54 | extern int profile_block_flag; |
9878760c RK |
55 | |
56 | #define min(A,B) ((A) < (B) ? (A) : (B)) | |
57 | #define max(A,B) ((A) > (B) ? (A) : (B)) | |
58 | ||
5248c961 RK |
59 | /* Target cpu type */ |
60 | ||
61 | enum processor_type rs6000_cpu; | |
8e3f41e7 MM |
62 | struct rs6000_cpu_select rs6000_select[3] = |
63 | { | |
815cdc52 MM |
64 | /* switch name, tune arch */ |
65 | { (const char *)0, "--with-cpu=", 1, 1 }, | |
66 | { (const char *)0, "-mcpu=", 1, 1 }, | |
67 | { (const char *)0, "-mtune=", 1, 0 }, | |
8e3f41e7 | 68 | }; |
5248c961 | 69 | |
c764f757 RK |
70 | /* Set to non-zero once AIX common-mode calls have been defined. */ |
71 | static int common_mode_defined; | |
c81bebd7 | 72 | |
9878760c RK |
73 | /* Save information from a "cmpxx" operation until the branch or scc is |
74 | emitted. */ | |
9878760c RK |
75 | rtx rs6000_compare_op0, rs6000_compare_op1; |
76 | int rs6000_compare_fp_p; | |
874a0744 | 77 | |
874a0744 MM |
78 | /* Label number of label created for -mrelocatable, to call to so we can |
79 | get the address of the GOT section */ | |
80 | int rs6000_pic_labelno; | |
c81bebd7 | 81 | |
9ebbca7d | 82 | #ifdef USING_SVR4_H |
c81bebd7 | 83 | /* Which abi to adhere to */ |
815cdc52 | 84 | const char *rs6000_abi_name = RS6000_ABI_NAME; |
d9407988 MM |
85 | |
86 | /* Semantics of the small data area */ | |
87 | enum rs6000_sdata_type rs6000_sdata = SDATA_DATA; | |
88 | ||
89 | /* Which small data model to use */ | |
815cdc52 | 90 | const char *rs6000_sdata_name = (char *)0; |
9ebbca7d GK |
91 | |
92 | /* Counter for labels which are to be placed in .fixup. */ | |
93 | int fixuplabelno = 0; | |
874a0744 | 94 | #endif |
4697a36c | 95 | |
b6c9286a MM |
96 | /* ABI enumeration available for subtarget to use. */ |
97 | enum rs6000_abi rs6000_current_abi; | |
98 | ||
38c1f2d7 | 99 | /* Debug flags */ |
815cdc52 | 100 | const char *rs6000_debug_name; |
38c1f2d7 MM |
101 | int rs6000_debug_stack; /* debug stack applications */ |
102 | int rs6000_debug_arg; /* debug argument handling */ | |
103 | ||
104 | /* Flag to say the TOC is initialized */ | |
105 | int toc_initialized; | |
9ebbca7d | 106 | char toc_label_name[10]; |
38c1f2d7 | 107 | |
9ebbca7d GK |
108 | /* Alias set for saves and restores from the rs6000 stack. */ |
109 | static int rs6000_sr_alias_set; | |
c8023011 | 110 | |
9ebbca7d GK |
111 | static void rs6000_add_gc_roots PARAMS ((void)); |
112 | static int num_insns_constant_wide PARAMS ((HOST_WIDE_INT)); | |
113 | static rtx expand_block_move_mem PARAMS ((enum machine_mode, rtx, rtx)); | |
39a10a29 GK |
114 | static void validate_condition_mode |
115 | PARAMS ((enum rtx_code, enum machine_mode)); | |
116 | static rtx rs6000_generate_compare PARAMS ((enum rtx_code)); | |
e50f5f3d | 117 | static void rs6000_maybe_dead PARAMS ((rtx)); |
9ebbca7d GK |
118 | static void rs6000_emit_stack_tie PARAMS ((void)); |
119 | static void rs6000_frame_related PARAMS ((rtx, rtx, HOST_WIDE_INT, rtx, rtx)); | |
120 | static void rs6000_emit_allocate_stack PARAMS ((HOST_WIDE_INT, int)); | |
121 | static unsigned rs6000_hash_constant PARAMS ((rtx)); | |
122 | static unsigned toc_hash_function PARAMS ((const void *)); | |
123 | static int toc_hash_eq PARAMS ((const void *, const void *)); | |
2eba1afa | 124 | static int toc_hash_mark_entry PARAMS ((void **, void *)); |
9ebbca7d GK |
125 | static void toc_hash_mark_table PARAMS ((void *)); |
126 | static int constant_pool_expr_1 PARAMS ((rtx, int *, int *)); | |
6fee9e99 NC |
127 | static void rs6000_free_machine_status PARAMS ((struct function *)); |
128 | static void rs6000_init_machine_status PARAMS ((struct function *)); | |
71f123ca | 129 | static int rs6000_ra_ever_killed PARAMS ((void)); |
672a6f42 | 130 | static int rs6000_valid_type_attribute_p PARAMS ((tree, tree, tree, tree)); |
08c148a8 NB |
131 | static void rs6000_output_function_prologue PARAMS ((FILE *, HOST_WIDE_INT)); |
132 | static void rs6000_output_function_epilogue PARAMS ((FILE *, HOST_WIDE_INT)); | |
2bfcf297 DB |
133 | static rtx rs6000_emit_set_long_const PARAMS ((rtx, |
134 | HOST_WIDE_INT, HOST_WIDE_INT)); | |
7c262518 RH |
135 | #if TARGET_ELF |
136 | static unsigned int rs6000_elf_section_type_flags PARAMS ((tree, const char *, | |
137 | int)); | |
d9f6800d RH |
138 | static void rs6000_elf_asm_out_constructor PARAMS ((rtx, int)); |
139 | static void rs6000_elf_asm_out_destructor PARAMS ((rtx, int)); | |
7c262518 RH |
140 | #endif |
141 | #ifdef OBJECT_FORMAT_COFF | |
715bdd29 | 142 | static void xcoff_asm_named_section PARAMS ((const char *, unsigned int)); |
7c262518 | 143 | #endif |
c237e94a ZW |
144 | static int rs6000_adjust_cost PARAMS ((rtx, rtx, rtx, int)); |
145 | static int rs6000_adjust_priority PARAMS ((rtx, int)); | |
146 | static int rs6000_issue_rate PARAMS ((void)); | |
147 | ||
c81bebd7 MM |
148 | \f |
149 | /* Default register names. */ | |
150 | char rs6000_reg_names[][8] = | |
151 | { | |
802a0058 MM |
152 | "0", "1", "2", "3", "4", "5", "6", "7", |
153 | "8", "9", "10", "11", "12", "13", "14", "15", | |
154 | "16", "17", "18", "19", "20", "21", "22", "23", | |
155 | "24", "25", "26", "27", "28", "29", "30", "31", | |
156 | "0", "1", "2", "3", "4", "5", "6", "7", | |
157 | "8", "9", "10", "11", "12", "13", "14", "15", | |
158 | "16", "17", "18", "19", "20", "21", "22", "23", | |
159 | "24", "25", "26", "27", "28", "29", "30", "31", | |
160 | "mq", "lr", "ctr","ap", | |
161 | "0", "1", "2", "3", "4", "5", "6", "7", | |
9ebbca7d | 162 | "xer" |
c81bebd7 MM |
163 | }; |
164 | ||
165 | #ifdef TARGET_REGNAMES | |
166 | static char alt_reg_names[][8] = | |
167 | { | |
802a0058 MM |
168 | "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7", |
169 | "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15", | |
170 | "%r16", "%r17", "%r18", "%r19", "%r20", "%r21", "%r22", "%r23", | |
171 | "%r24", "%r25", "%r26", "%r27", "%r28", "%r29", "%r30", "%r31", | |
172 | "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7", | |
173 | "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15", | |
174 | "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23", | |
175 | "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31", | |
176 | "mq", "lr", "ctr", "ap", | |
177 | "%cr0", "%cr1", "%cr2", "%cr3", "%cr4", "%cr5", "%cr6", "%cr7", | |
9ebbca7d | 178 | "xer" |
c81bebd7 MM |
179 | }; |
180 | #endif | |
9878760c | 181 | \f |
daf11973 MM |
182 | #ifndef MASK_STRICT_ALIGN |
183 | #define MASK_STRICT_ALIGN 0 | |
184 | #endif | |
672a6f42 NB |
185 | \f |
186 | /* Initialize the GCC target structure. */ | |
187 | #undef TARGET_VALID_TYPE_ATTRIBUTE | |
188 | #define TARGET_VALID_TYPE_ATTRIBUTE rs6000_valid_type_attribute_p | |
daf11973 | 189 | |
08c148a8 NB |
190 | #undef TARGET_ASM_FUNCTION_PROLOGUE |
191 | #define TARGET_ASM_FUNCTION_PROLOGUE rs6000_output_function_prologue | |
192 | #undef TARGET_ASM_FUNCTION_EPILOGUE | |
193 | #define TARGET_ASM_FUNCTION_EPILOGUE rs6000_output_function_epilogue | |
194 | ||
7c262518 RH |
195 | #if TARGET_ELF |
196 | #undef TARGET_SECTION_TYPE_FLAGS | |
197 | #define TARGET_SECTION_TYPE_FLAGS rs6000_elf_section_type_flags | |
198 | #endif | |
199 | ||
c237e94a ZW |
200 | #undef TARGET_SCHED_ISSUE_RATE |
201 | #define TARGET_SCHED_ISSUE_RATE rs6000_issue_rate | |
202 | #undef TARGET_SCHED_ADJUST_COST | |
203 | #define TARGET_SCHED_ADJUST_COST rs6000_adjust_cost | |
204 | #undef TARGET_SCHED_ADJUST_PRIORITY | |
205 | #define TARGET_SCHED_ADJUST_PRIORITY rs6000_adjust_priority | |
206 | ||
f6897b10 | 207 | struct gcc_target targetm = TARGET_INITIALIZER; |
672a6f42 | 208 | \f |
5248c961 RK |
209 | /* Override command line options. Mostly we process the processor |
210 | type and sometimes adjust other TARGET_ options. */ | |
211 | ||
212 | void | |
8e3f41e7 | 213 | rs6000_override_options (default_cpu) |
d330fd93 | 214 | const char *default_cpu; |
5248c961 | 215 | { |
c4d38ccb | 216 | size_t i, j; |
8e3f41e7 | 217 | struct rs6000_cpu_select *ptr; |
5248c961 | 218 | |
85638c0d RK |
219 | /* Simplify the entries below by making a mask for any POWER |
220 | variant and any PowerPC variant. */ | |
221 | ||
938937d8 | 222 | #define POWER_MASKS (MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING) |
68c49ffa RK |
223 | #define POWERPC_MASKS (MASK_POWERPC | MASK_PPC_GPOPT \ |
224 | | MASK_PPC_GFXOPT | MASK_POWERPC64) | |
225 | #define POWERPC_OPT_MASKS (MASK_PPC_GPOPT | MASK_PPC_GFXOPT) | |
85638c0d | 226 | |
5248c961 RK |
227 | static struct ptt |
228 | { | |
d330fd93 | 229 | const char *name; /* Canonical processor name. */ |
5248c961 RK |
230 | enum processor_type processor; /* Processor type enum value. */ |
231 | int target_enable; /* Target flags to enable. */ | |
232 | int target_disable; /* Target flags to disable. */ | |
233 | } processor_target_table[] | |
cf27b467 MM |
234 | = {{"common", PROCESSOR_COMMON, MASK_NEW_MNEMONICS, |
235 | POWER_MASKS | POWERPC_MASKS}, | |
db7f1e43 | 236 | {"power", PROCESSOR_POWER, |
938937d8 | 237 | MASK_POWER | MASK_MULTIPLE | MASK_STRING, |
db7f1e43 | 238 | MASK_POWER2 | POWERPC_MASKS | MASK_NEW_MNEMONICS}, |
8e3f41e7 MM |
239 | {"power2", PROCESSOR_POWER, |
240 | MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING, | |
241 | POWERPC_MASKS | MASK_NEW_MNEMONICS}, | |
c71791e0 DE |
242 | {"power3", PROCESSOR_PPC630, |
243 | MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS, | |
244 | POWER_MASKS | MASK_PPC_GPOPT}, | |
db7f1e43 RK |
245 | {"powerpc", PROCESSOR_POWERPC, |
246 | MASK_POWERPC | MASK_NEW_MNEMONICS, | |
68c49ffa | 247 | POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64}, |
3cb999d8 DE |
248 | {"powerpc64", PROCESSOR_POWERPC64, |
249 | MASK_POWERPC | MASK_POWERPC64 | MASK_NEW_MNEMONICS, | |
250 | POWER_MASKS | POWERPC_OPT_MASKS}, | |
db7f1e43 | 251 | {"rios", PROCESSOR_RIOS1, |
938937d8 | 252 | MASK_POWER | MASK_MULTIPLE | MASK_STRING, |
db7f1e43 RK |
253 | MASK_POWER2 | POWERPC_MASKS | MASK_NEW_MNEMONICS}, |
254 | {"rios1", PROCESSOR_RIOS1, | |
938937d8 | 255 | MASK_POWER | MASK_MULTIPLE | MASK_STRING, |
db7f1e43 RK |
256 | MASK_POWER2 | POWERPC_MASKS | MASK_NEW_MNEMONICS}, |
257 | {"rsc", PROCESSOR_PPC601, | |
938937d8 | 258 | MASK_POWER | MASK_MULTIPLE | MASK_STRING, |
db7f1e43 RK |
259 | MASK_POWER2 | POWERPC_MASKS | MASK_NEW_MNEMONICS}, |
260 | {"rsc1", PROCESSOR_PPC601, | |
938937d8 | 261 | MASK_POWER | MASK_MULTIPLE | MASK_STRING, |
db7f1e43 RK |
262 | MASK_POWER2 | POWERPC_MASKS | MASK_NEW_MNEMONICS}, |
263 | {"rios2", PROCESSOR_RIOS2, | |
938937d8 | 264 | MASK_POWER | MASK_MULTIPLE | MASK_STRING | MASK_POWER2, |
db7f1e43 | 265 | POWERPC_MASKS | MASK_NEW_MNEMONICS}, |
3cb999d8 DE |
266 | {"rs64a", PROCESSOR_RS64A, |
267 | MASK_POWERPC | MASK_NEW_MNEMONICS, | |
268 | POWER_MASKS | POWERPC_OPT_MASKS}, | |
a3a1dbf6 MM |
269 | {"401", PROCESSOR_PPC403, |
270 | MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS, | |
271 | POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64}, | |
49a0b204 | 272 | {"403", PROCESSOR_PPC403, |
daf11973 | 273 | MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS | MASK_STRICT_ALIGN, |
49a0b204 | 274 | POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64}, |
cf27b467 MM |
275 | {"505", PROCESSOR_MPCCORE, |
276 | MASK_POWERPC | MASK_NEW_MNEMONICS, | |
277 | POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64}, | |
5248c961 | 278 | {"601", PROCESSOR_PPC601, |
938937d8 | 279 | MASK_POWER | MASK_POWERPC | MASK_NEW_MNEMONICS | MASK_MULTIPLE | MASK_STRING, |
68c49ffa | 280 | MASK_POWER2 | POWERPC_OPT_MASKS | MASK_POWERPC64}, |
1ec26da6 | 281 | {"602", PROCESSOR_PPC603, |
cf27b467 MM |
282 | MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS, |
283 | POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64}, | |
5248c961 | 284 | {"603", PROCESSOR_PPC603, |
68c49ffa RK |
285 | MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS, |
286 | POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64}, | |
b6c9286a MM |
287 | {"603e", PROCESSOR_PPC603, |
288 | MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS, | |
289 | POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64}, | |
b5370a88 | 290 | {"ec603e", PROCESSOR_PPC603, |
a3a1dbf6 MM |
291 | MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS, |
292 | POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64}, | |
5248c961 | 293 | {"604", PROCESSOR_PPC604, |
b6c9286a MM |
294 | MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS, |
295 | POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64}, | |
cac8ce95 | 296 | {"604e", PROCESSOR_PPC604e, |
07e6159a MM |
297 | MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS, |
298 | POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64}, | |
b6c9286a | 299 | {"620", PROCESSOR_PPC620, |
68c49ffa | 300 | MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS, |
a260abc9 | 301 | POWER_MASKS | MASK_PPC_GPOPT}, |
3cb999d8 DE |
302 | {"630", PROCESSOR_PPC630, |
303 | MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS, | |
304 | POWER_MASKS | MASK_PPC_GPOPT}, | |
bef84347 VM |
305 | {"740", PROCESSOR_PPC750, |
306 | MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS, | |
307 | POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64}, | |
308 | {"750", PROCESSOR_PPC750, | |
309 | MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS, | |
310 | POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64}, | |
07e6159a MM |
311 | {"801", PROCESSOR_MPCCORE, |
312 | MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS, | |
313 | POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64}, | |
cf27b467 MM |
314 | {"821", PROCESSOR_MPCCORE, |
315 | MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS, | |
316 | POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64}, | |
07e6159a MM |
317 | {"823", PROCESSOR_MPCCORE, |
318 | MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS, | |
319 | POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64}, | |
cf27b467 MM |
320 | {"860", PROCESSOR_MPCCORE, |
321 | MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS, | |
322 | POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64}}; | |
5248c961 | 323 | |
c4d38ccb | 324 | size_t ptt_size = sizeof (processor_target_table) / sizeof (struct ptt); |
5248c961 | 325 | |
8a61d227 | 326 | int multiple = TARGET_MULTIPLE; /* save current -mmultiple/-mno-multiple status */ |
938937d8 | 327 | int string = TARGET_STRING; /* save current -mstring/-mno-string status */ |
8a61d227 | 328 | |
5248c961 RK |
329 | profile_block_flag = 0; |
330 | ||
331 | /* Identify the processor type */ | |
8e3f41e7 | 332 | rs6000_select[0].string = default_cpu; |
3cb999d8 | 333 | rs6000_cpu = TARGET_POWERPC64 ? PROCESSOR_DEFAULT64 : PROCESSOR_DEFAULT; |
8e3f41e7 | 334 | |
b6a1cbae | 335 | for (i = 0; i < ARRAY_SIZE (rs6000_select); i++) |
5248c961 | 336 | { |
8e3f41e7 MM |
337 | ptr = &rs6000_select[i]; |
338 | if (ptr->string != (char *)0 && ptr->string[0] != '\0') | |
5248c961 | 339 | { |
8e3f41e7 MM |
340 | for (j = 0; j < ptt_size; j++) |
341 | if (! strcmp (ptr->string, processor_target_table[j].name)) | |
342 | { | |
343 | if (ptr->set_tune_p) | |
344 | rs6000_cpu = processor_target_table[j].processor; | |
345 | ||
346 | if (ptr->set_arch_p) | |
347 | { | |
348 | target_flags |= processor_target_table[j].target_enable; | |
349 | target_flags &= ~processor_target_table[j].target_disable; | |
350 | } | |
351 | break; | |
352 | } | |
353 | ||
4406229e | 354 | if (j == ptt_size) |
8e3f41e7 | 355 | error ("bad value (%s) for %s switch", ptr->string, ptr->name); |
5248c961 RK |
356 | } |
357 | } | |
8a61d227 | 358 | |
ef792183 MM |
359 | /* If we are optimizing big endian systems for space, use the |
360 | store multiple instructions. */ | |
361 | if (BYTES_BIG_ENDIAN && optimize_size) | |
362 | target_flags |= MASK_MULTIPLE; | |
363 | ||
8a61d227 MM |
364 | /* If -mmultiple or -mno-multiple was explicitly used, don't |
365 | override with the processor default */ | |
366 | if (TARGET_MULTIPLE_SET) | |
367 | target_flags = (target_flags & ~MASK_MULTIPLE) | multiple; | |
7e69e155 | 368 | |
938937d8 MM |
369 | /* If -mstring or -mno-string was explicitly used, don't |
370 | override with the processor default */ | |
371 | if (TARGET_STRING_SET) | |
1f5515bf | 372 | target_flags = (target_flags & ~MASK_STRING) | string; |
938937d8 | 373 | |
bef84347 VM |
374 | /* Don't allow -mmultiple or -mstring on little endian systems unless the cpu |
375 | is a 750, because the hardware doesn't support the instructions used in | |
376 | little endian mode, and causes an alignment trap. The 750 does not cause | |
377 | an alignment trap (except when the target is unaligned). */ | |
378 | ||
bfc79d3b | 379 | if (! BYTES_BIG_ENDIAN && rs6000_cpu != PROCESSOR_PPC750) |
7e69e155 MM |
380 | { |
381 | if (TARGET_MULTIPLE) | |
382 | { | |
383 | target_flags &= ~MASK_MULTIPLE; | |
384 | if (TARGET_MULTIPLE_SET) | |
385 | warning ("-mmultiple is not supported on little endian systems"); | |
386 | } | |
387 | ||
388 | if (TARGET_STRING) | |
389 | { | |
390 | target_flags &= ~MASK_STRING; | |
938937d8 MM |
391 | if (TARGET_STRING_SET) |
392 | warning ("-mstring is not supported on little endian systems"); | |
7e69e155 MM |
393 | } |
394 | } | |
3933e0e1 | 395 | |
2bfcf297 | 396 | if (flag_pic && DEFAULT_ABI == ABI_AIX) |
a260abc9 | 397 | { |
2bfcf297 | 398 | warning ("-f%s ignored (all code is position independent)", |
a260abc9 DE |
399 | (flag_pic > 1) ? "PIC" : "pic"); |
400 | flag_pic = 0; | |
401 | } | |
402 | ||
2bfcf297 | 403 | #ifdef XCOFF_DEBUGGING_INFO |
9861b0c9 | 404 | if (flag_function_sections && (write_symbols != NO_DEBUG) |
2bfcf297 | 405 | && DEFAULT_ABI == ABI_AIX) |
9861b0c9 DE |
406 | { |
407 | warning ("-ffunction-sections disabled on AIX when debugging"); | |
408 | flag_function_sections = 0; | |
409 | } | |
410 | ||
411 | if (flag_data_sections && (DEFAULT_ABI == ABI_AIX)) | |
412 | { | |
413 | warning ("-fdata-sections not supported on AIX"); | |
414 | flag_data_sections = 0; | |
415 | } | |
2bfcf297 | 416 | #endif |
9861b0c9 | 417 | |
38c1f2d7 MM |
418 | /* Set debug flags */ |
419 | if (rs6000_debug_name) | |
420 | { | |
bfc79d3b | 421 | if (! strcmp (rs6000_debug_name, "all")) |
38c1f2d7 | 422 | rs6000_debug_stack = rs6000_debug_arg = 1; |
bfc79d3b | 423 | else if (! strcmp (rs6000_debug_name, "stack")) |
38c1f2d7 | 424 | rs6000_debug_stack = 1; |
bfc79d3b | 425 | else if (! strcmp (rs6000_debug_name, "arg")) |
38c1f2d7 MM |
426 | rs6000_debug_arg = 1; |
427 | else | |
428 | error ("Unknown -mdebug-%s switch", rs6000_debug_name); | |
429 | } | |
430 | ||
c81bebd7 MM |
431 | #ifdef TARGET_REGNAMES |
432 | /* If the user desires alternate register names, copy in the alternate names | |
433 | now. */ | |
434 | if (TARGET_REGNAMES) | |
4e135bdd | 435 | memcpy (rs6000_reg_names, alt_reg_names, sizeof (rs6000_reg_names)); |
c81bebd7 MM |
436 | #endif |
437 | ||
3933e0e1 MM |
438 | #ifdef SUBTARGET_OVERRIDE_OPTIONS |
439 | SUBTARGET_OVERRIDE_OPTIONS; | |
440 | #endif | |
c8023011 MM |
441 | |
442 | /* Register global variables with the garbage collector. */ | |
443 | rs6000_add_gc_roots (); | |
9ebbca7d GK |
444 | |
445 | /* Allocate an alias set for register saves & restores from stack. */ | |
446 | rs6000_sr_alias_set = new_alias_set (); | |
447 | ||
448 | if (TARGET_TOC) | |
449 | ASM_GENERATE_INTERNAL_LABEL (toc_label_name, "LCTOC", 1); | |
71f123ca FS |
450 | |
451 | /* Arrange to save and restore machine status around nested functions. */ | |
452 | init_machine_status = rs6000_init_machine_status; | |
71f123ca | 453 | free_machine_status = rs6000_free_machine_status; |
5248c961 | 454 | } |
5accd822 DE |
455 | |
456 | void | |
457 | optimization_options (level, size) | |
e2c953b6 | 458 | int level ATTRIBUTE_UNUSED; |
5accd822 DE |
459 | int size ATTRIBUTE_UNUSED; |
460 | { | |
5accd822 | 461 | } |
3cfa4909 MM |
462 | \f |
463 | /* Do anything needed at the start of the asm file. */ | |
464 | ||
465 | void | |
466 | rs6000_file_start (file, default_cpu) | |
467 | FILE *file; | |
d330fd93 | 468 | const char *default_cpu; |
3cfa4909 | 469 | { |
c4d38ccb | 470 | size_t i; |
3cfa4909 | 471 | char buffer[80]; |
d330fd93 | 472 | const char *start = buffer; |
3cfa4909 MM |
473 | struct rs6000_cpu_select *ptr; |
474 | ||
475 | if (flag_verbose_asm) | |
476 | { | |
477 | sprintf (buffer, "\n%s rs6000/powerpc options:", ASM_COMMENT_START); | |
478 | rs6000_select[0].string = default_cpu; | |
479 | ||
b6a1cbae | 480 | for (i = 0; i < ARRAY_SIZE (rs6000_select); i++) |
3cfa4909 MM |
481 | { |
482 | ptr = &rs6000_select[i]; | |
483 | if (ptr->string != (char *)0 && ptr->string[0] != '\0') | |
484 | { | |
485 | fprintf (file, "%s %s%s", start, ptr->name, ptr->string); | |
486 | start = ""; | |
487 | } | |
488 | } | |
489 | ||
490 | #ifdef USING_SVR4_H | |
491 | switch (rs6000_sdata) | |
492 | { | |
493 | case SDATA_NONE: fprintf (file, "%s -msdata=none", start); start = ""; break; | |
494 | case SDATA_DATA: fprintf (file, "%s -msdata=data", start); start = ""; break; | |
495 | case SDATA_SYSV: fprintf (file, "%s -msdata=sysv", start); start = ""; break; | |
496 | case SDATA_EABI: fprintf (file, "%s -msdata=eabi", start); start = ""; break; | |
497 | } | |
498 | ||
499 | if (rs6000_sdata && g_switch_value) | |
500 | { | |
501 | fprintf (file, "%s -G %d", start, g_switch_value); | |
502 | start = ""; | |
503 | } | |
504 | #endif | |
505 | ||
506 | if (*start == '\0') | |
949ea356 | 507 | putc ('\n', file); |
3cfa4909 MM |
508 | } |
509 | } | |
510 | ||
24d304eb RK |
511 | \f |
512 | /* Create a CONST_DOUBLE from a string. */ | |
513 | ||
514 | struct rtx_def * | |
515 | rs6000_float_const (string, mode) | |
d330fd93 | 516 | const char *string; |
24d304eb RK |
517 | enum machine_mode mode; |
518 | { | |
ca5adc63 GK |
519 | REAL_VALUE_TYPE value; |
520 | value = REAL_VALUE_ATOF (string, mode); | |
24d304eb RK |
521 | return immed_real_const_1 (value, mode); |
522 | } | |
5248c961 | 523 | \f |
9878760c RK |
524 | /* Return non-zero if this function is known to have a null epilogue. */ |
525 | ||
526 | int | |
527 | direct_return () | |
528 | { | |
4697a36c MM |
529 | if (reload_completed) |
530 | { | |
531 | rs6000_stack_t *info = rs6000_stack_info (); | |
532 | ||
533 | if (info->first_gp_reg_save == 32 | |
534 | && info->first_fp_reg_save == 64 | |
c81fc13e DE |
535 | && ! info->lr_save_p |
536 | && ! info->cr_save_p | |
537 | && ! info->push_p) | |
4697a36c MM |
538 | return 1; |
539 | } | |
540 | ||
541 | return 0; | |
9878760c RK |
542 | } |
543 | ||
544 | /* Returns 1 always. */ | |
545 | ||
546 | int | |
547 | any_operand (op, mode) | |
296b8152 KG |
548 | register rtx op ATTRIBUTE_UNUSED; |
549 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
9878760c RK |
550 | { |
551 | return 1; | |
552 | } | |
553 | ||
b6c9286a | 554 | /* Returns 1 if op is the count register */ |
38c1f2d7 MM |
555 | int |
556 | count_register_operand(op, mode) | |
b6c9286a | 557 | register rtx op; |
296b8152 | 558 | enum machine_mode mode ATTRIBUTE_UNUSED; |
b6c9286a MM |
559 | { |
560 | if (GET_CODE (op) != REG) | |
561 | return 0; | |
562 | ||
563 | if (REGNO (op) == COUNT_REGISTER_REGNUM) | |
564 | return 1; | |
565 | ||
566 | if (REGNO (op) > FIRST_PSEUDO_REGISTER) | |
567 | return 1; | |
568 | ||
569 | return 0; | |
570 | } | |
571 | ||
38c1f2d7 | 572 | int |
9ebbca7d | 573 | xer_operand(op, mode) |
802a0058 | 574 | register rtx op; |
296b8152 | 575 | enum machine_mode mode ATTRIBUTE_UNUSED; |
802a0058 MM |
576 | { |
577 | if (GET_CODE (op) != REG) | |
578 | return 0; | |
579 | ||
9ebbca7d | 580 | if (XER_REGNO_P (REGNO (op))) |
802a0058 MM |
581 | return 1; |
582 | ||
802a0058 MM |
583 | return 0; |
584 | } | |
585 | ||
9878760c RK |
586 | /* Return 1 if OP is a constant that can fit in a D field. */ |
587 | ||
588 | int | |
589 | short_cint_operand (op, mode) | |
590 | register rtx op; | |
296b8152 | 591 | enum machine_mode mode ATTRIBUTE_UNUSED; |
9878760c | 592 | { |
5f59ecb7 DE |
593 | return (GET_CODE (op) == CONST_INT |
594 | && CONST_OK_FOR_LETTER_P (INTVAL (op), 'I')); | |
9878760c RK |
595 | } |
596 | ||
597 | /* Similar for a unsigned D field. */ | |
598 | ||
599 | int | |
600 | u_short_cint_operand (op, mode) | |
601 | register rtx op; | |
296b8152 | 602 | enum machine_mode mode ATTRIBUTE_UNUSED; |
9878760c | 603 | { |
19684119 | 604 | return (GET_CODE (op) == CONST_INT |
5f59ecb7 | 605 | && CONST_OK_FOR_LETTER_P (INTVAL (op), 'K')); |
9878760c RK |
606 | } |
607 | ||
dcfedcd0 RK |
608 | /* Return 1 if OP is a CONST_INT that cannot fit in a signed D field. */ |
609 | ||
610 | int | |
611 | non_short_cint_operand (op, mode) | |
612 | register rtx op; | |
296b8152 | 613 | enum machine_mode mode ATTRIBUTE_UNUSED; |
dcfedcd0 RK |
614 | { |
615 | return (GET_CODE (op) == CONST_INT | |
a7653a2c | 616 | && (unsigned HOST_WIDE_INT) (INTVAL (op) + 0x8000) >= 0x10000); |
dcfedcd0 RK |
617 | } |
618 | ||
2bfcf297 DB |
619 | /* Returns 1 if OP is a CONST_INT that is a positive value |
620 | and an exact power of 2. */ | |
621 | ||
622 | int | |
623 | exact_log2_cint_operand (op, mode) | |
624 | register rtx op; | |
625 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
626 | { | |
627 | return (GET_CODE (op) == CONST_INT | |
628 | && INTVAL (op) > 0 | |
629 | && exact_log2 (INTVAL (op)) >= 0); | |
630 | } | |
631 | ||
9878760c RK |
632 | /* Returns 1 if OP is a register that is not special (i.e., not MQ, |
633 | ctr, or lr). */ | |
634 | ||
635 | int | |
cd2b37d9 | 636 | gpc_reg_operand (op, mode) |
9878760c RK |
637 | register rtx op; |
638 | enum machine_mode mode; | |
639 | { | |
640 | return (register_operand (op, mode) | |
802a0058 | 641 | && (GET_CODE (op) != REG |
9ebbca7d GK |
642 | || (REGNO (op) >= ARG_POINTER_REGNUM |
643 | && !XER_REGNO_P (REGNO (op))) | |
644 | || REGNO (op) < MQ_REGNO)); | |
9878760c RK |
645 | } |
646 | ||
647 | /* Returns 1 if OP is either a pseudo-register or a register denoting a | |
648 | CR field. */ | |
649 | ||
650 | int | |
651 | cc_reg_operand (op, mode) | |
652 | register rtx op; | |
653 | enum machine_mode mode; | |
654 | { | |
655 | return (register_operand (op, mode) | |
656 | && (GET_CODE (op) != REG | |
657 | || REGNO (op) >= FIRST_PSEUDO_REGISTER | |
658 | || CR_REGNO_P (REGNO (op)))); | |
659 | } | |
660 | ||
815cdc52 MM |
661 | /* Returns 1 if OP is either a pseudo-register or a register denoting a |
662 | CR field that isn't CR0. */ | |
663 | ||
664 | int | |
665 | cc_reg_not_cr0_operand (op, mode) | |
666 | register rtx op; | |
667 | enum machine_mode mode; | |
668 | { | |
669 | return (register_operand (op, mode) | |
670 | && (GET_CODE (op) != REG | |
671 | || REGNO (op) >= FIRST_PSEUDO_REGISTER | |
672 | || CR_REGNO_NOT_CR0_P (REGNO (op)))); | |
673 | } | |
674 | ||
9878760c RK |
675 | /* Returns 1 if OP is either a constant integer valid for a D-field or a |
676 | non-special register. If a register, it must be in the proper mode unless | |
677 | MODE is VOIDmode. */ | |
678 | ||
679 | int | |
680 | reg_or_short_operand (op, mode) | |
681 | register rtx op; | |
682 | enum machine_mode mode; | |
683 | { | |
f5a28898 | 684 | return short_cint_operand (op, mode) || gpc_reg_operand (op, mode); |
9878760c RK |
685 | } |
686 | ||
687 | /* Similar, except check if the negation of the constant would be valid for | |
688 | a D-field. */ | |
689 | ||
690 | int | |
691 | reg_or_neg_short_operand (op, mode) | |
692 | register rtx op; | |
693 | enum machine_mode mode; | |
694 | { | |
695 | if (GET_CODE (op) == CONST_INT) | |
696 | return CONST_OK_FOR_LETTER_P (INTVAL (op), 'P'); | |
697 | ||
cd2b37d9 | 698 | return gpc_reg_operand (op, mode); |
9878760c RK |
699 | } |
700 | ||
701 | /* Return 1 if the operand is either a register or an integer whose high-order | |
702 | 16 bits are zero. */ | |
703 | ||
704 | int | |
705 | reg_or_u_short_operand (op, mode) | |
706 | register rtx op; | |
707 | enum machine_mode mode; | |
708 | { | |
e675f625 | 709 | return u_short_cint_operand (op, mode) || gpc_reg_operand (op, mode); |
9878760c RK |
710 | } |
711 | ||
712 | /* Return 1 is the operand is either a non-special register or ANY | |
713 | constant integer. */ | |
714 | ||
715 | int | |
716 | reg_or_cint_operand (op, mode) | |
717 | register rtx op; | |
718 | enum machine_mode mode; | |
719 | { | |
f6bf7de2 DE |
720 | return (GET_CODE (op) == CONST_INT || gpc_reg_operand (op, mode)); |
721 | } | |
722 | ||
723 | /* Return 1 is the operand is either a non-special register or ANY | |
724 | 32-bit signed constant integer. */ | |
725 | ||
726 | int | |
727 | reg_or_arith_cint_operand (op, mode) | |
728 | register rtx op; | |
729 | enum machine_mode mode; | |
730 | { | |
731 | return (gpc_reg_operand (op, mode) | |
732 | || (GET_CODE (op) == CONST_INT | |
733 | #if HOST_BITS_PER_WIDE_INT != 32 | |
734 | && ((unsigned HOST_WIDE_INT) (INTVAL (op) + 0x80000000) | |
78e1b90d | 735 | < (unsigned HOST_WIDE_INT) 0x100000000ll) |
f6bf7de2 DE |
736 | #endif |
737 | )); | |
9878760c RK |
738 | } |
739 | ||
2bfcf297 DB |
740 | /* Return 1 is the operand is either a non-special register or a 32-bit |
741 | signed constant integer valid for 64-bit addition. */ | |
742 | ||
743 | int | |
744 | reg_or_add_cint64_operand (op, mode) | |
745 | register rtx op; | |
746 | enum machine_mode mode; | |
747 | { | |
748 | return (gpc_reg_operand (op, mode) | |
749 | || (GET_CODE (op) == CONST_INT | |
750 | && INTVAL (op) < 0x7fff8000 | |
751 | #if HOST_BITS_PER_WIDE_INT != 32 | |
752 | && ((unsigned HOST_WIDE_INT) (INTVAL (op) + 0x80008000) | |
753 | < 0x100000000ll) | |
754 | #endif | |
755 | )); | |
756 | } | |
757 | ||
758 | /* Return 1 is the operand is either a non-special register or a 32-bit | |
759 | signed constant integer valid for 64-bit subtraction. */ | |
760 | ||
761 | int | |
762 | reg_or_sub_cint64_operand (op, mode) | |
763 | register rtx op; | |
764 | enum machine_mode mode; | |
765 | { | |
766 | return (gpc_reg_operand (op, mode) | |
767 | || (GET_CODE (op) == CONST_INT | |
768 | && (- INTVAL (op)) < 0x7fff8000 | |
769 | #if HOST_BITS_PER_WIDE_INT != 32 | |
770 | && ((unsigned HOST_WIDE_INT) ((- INTVAL (op)) + 0x80008000) | |
771 | < 0x100000000ll) | |
772 | #endif | |
773 | )); | |
774 | } | |
775 | ||
9ebbca7d GK |
776 | /* Return 1 is the operand is either a non-special register or ANY |
777 | 32-bit unsigned constant integer. */ | |
778 | ||
779 | int | |
1d328b19 | 780 | reg_or_logical_cint_operand (op, mode) |
9ebbca7d GK |
781 | register rtx op; |
782 | enum machine_mode mode; | |
783 | { | |
1d328b19 GK |
784 | if (GET_CODE (op) == CONST_INT) |
785 | { | |
786 | if (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT) | |
787 | { | |
788 | if (GET_MODE_BITSIZE (mode) <= 32) | |
789 | abort(); | |
790 | ||
791 | if (INTVAL (op) < 0) | |
792 | return 0; | |
793 | } | |
794 | ||
795 | return ((INTVAL (op) & GET_MODE_MASK (mode) | |
0858c623 | 796 | & (~ (unsigned HOST_WIDE_INT) 0xffffffff)) == 0); |
1d328b19 GK |
797 | } |
798 | else if (GET_CODE (op) == CONST_DOUBLE) | |
799 | { | |
800 | if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT | |
801 | || mode != DImode) | |
802 | abort(); | |
803 | ||
804 | return CONST_DOUBLE_HIGH (op) == 0; | |
805 | } | |
806 | else | |
807 | return gpc_reg_operand (op, mode); | |
9ebbca7d GK |
808 | } |
809 | ||
766a866c MM |
810 | /* Return 1 if the operand is an operand that can be loaded via the GOT */ |
811 | ||
812 | int | |
813 | got_operand (op, mode) | |
814 | register rtx op; | |
296b8152 | 815 | enum machine_mode mode ATTRIBUTE_UNUSED; |
766a866c MM |
816 | { |
817 | return (GET_CODE (op) == SYMBOL_REF | |
818 | || GET_CODE (op) == CONST | |
819 | || GET_CODE (op) == LABEL_REF); | |
820 | } | |
821 | ||
38c1f2d7 MM |
822 | /* Return 1 if the operand is a simple references that can be loaded via |
823 | the GOT (labels involving addition aren't allowed). */ | |
824 | ||
825 | int | |
826 | got_no_const_operand (op, mode) | |
827 | register rtx op; | |
296b8152 | 828 | enum machine_mode mode ATTRIBUTE_UNUSED; |
38c1f2d7 MM |
829 | { |
830 | return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF); | |
831 | } | |
832 | ||
4e74d8ec MM |
833 | /* Return the number of instructions it takes to form a constant in an |
834 | integer register. */ | |
835 | ||
836 | static int | |
837 | num_insns_constant_wide (value) | |
838 | HOST_WIDE_INT value; | |
839 | { | |
840 | /* signed constant loadable with {cal|addi} */ | |
5f59ecb7 | 841 | if (CONST_OK_FOR_LETTER_P (value, 'I')) |
0865c631 GK |
842 | return 1; |
843 | ||
4e74d8ec | 844 | /* constant loadable with {cau|addis} */ |
5f59ecb7 | 845 | else if (CONST_OK_FOR_LETTER_P (value, 'L')) |
4e74d8ec MM |
846 | return 1; |
847 | ||
5f59ecb7 | 848 | #if HOST_BITS_PER_WIDE_INT == 64 |
c81fc13e | 849 | else if (TARGET_POWERPC64) |
4e74d8ec | 850 | { |
0d30d435 | 851 | HOST_WIDE_INT low = value & 0xffffffff; |
4e74d8ec MM |
852 | HOST_WIDE_INT high = value >> 32; |
853 | ||
0d30d435 DE |
854 | low = (low ^ 0x80000000) - 0x80000000; /* sign extend */ |
855 | ||
0858c623 | 856 | if (high == 0 && (low & 0x80000000) == 0) |
4e74d8ec MM |
857 | return 2; |
858 | ||
0858c623 | 859 | else if (high == -1 && (low & 0x80000000) != 0) |
4e74d8ec MM |
860 | return 2; |
861 | ||
c81fc13e | 862 | else if (! low) |
4e74d8ec MM |
863 | return num_insns_constant_wide (high) + 1; |
864 | ||
865 | else | |
866 | return (num_insns_constant_wide (high) | |
e396202a | 867 | + num_insns_constant_wide (low) + 1); |
4e74d8ec MM |
868 | } |
869 | #endif | |
870 | ||
871 | else | |
872 | return 2; | |
873 | } | |
874 | ||
875 | int | |
876 | num_insns_constant (op, mode) | |
877 | rtx op; | |
878 | enum machine_mode mode; | |
879 | { | |
4e74d8ec | 880 | if (GET_CODE (op) == CONST_INT) |
0d30d435 DE |
881 | { |
882 | #if HOST_BITS_PER_WIDE_INT == 64 | |
883 | if (mask64_operand (op, mode)) | |
884 | return 2; | |
885 | else | |
886 | #endif | |
887 | return num_insns_constant_wide (INTVAL (op)); | |
888 | } | |
4e74d8ec | 889 | |
6fc48950 MM |
890 | else if (GET_CODE (op) == CONST_DOUBLE && mode == SFmode) |
891 | { | |
892 | long l; | |
893 | REAL_VALUE_TYPE rv; | |
894 | ||
895 | REAL_VALUE_FROM_CONST_DOUBLE (rv, op); | |
896 | REAL_VALUE_TO_TARGET_SINGLE (rv, l); | |
897 | return num_insns_constant_wide ((HOST_WIDE_INT)l); | |
898 | } | |
899 | ||
47ad8c61 | 900 | else if (GET_CODE (op) == CONST_DOUBLE) |
4e74d8ec | 901 | { |
47ad8c61 MM |
902 | HOST_WIDE_INT low; |
903 | HOST_WIDE_INT high; | |
904 | long l[2]; | |
905 | REAL_VALUE_TYPE rv; | |
906 | int endian = (WORDS_BIG_ENDIAN == 0); | |
4e74d8ec | 907 | |
47ad8c61 MM |
908 | if (mode == VOIDmode || mode == DImode) |
909 | { | |
910 | high = CONST_DOUBLE_HIGH (op); | |
911 | low = CONST_DOUBLE_LOW (op); | |
912 | } | |
913 | else | |
914 | { | |
915 | REAL_VALUE_FROM_CONST_DOUBLE (rv, op); | |
916 | REAL_VALUE_TO_TARGET_DOUBLE (rv, l); | |
917 | high = l[endian]; | |
918 | low = l[1 - endian]; | |
919 | } | |
4e74d8ec | 920 | |
47ad8c61 MM |
921 | if (TARGET_32BIT) |
922 | return (num_insns_constant_wide (low) | |
923 | + num_insns_constant_wide (high)); | |
4e74d8ec MM |
924 | |
925 | else | |
47ad8c61 | 926 | { |
0858c623 | 927 | if (high == 0 && (low & 0x80000000) == 0) |
47ad8c61 MM |
928 | return num_insns_constant_wide (low); |
929 | ||
0858c623 | 930 | else if (high == -1 && (low & 0x80000000) != 0) |
47ad8c61 MM |
931 | return num_insns_constant_wide (low); |
932 | ||
a260abc9 DE |
933 | else if (mask64_operand (op, mode)) |
934 | return 2; | |
935 | ||
47ad8c61 MM |
936 | else if (low == 0) |
937 | return num_insns_constant_wide (high) + 1; | |
938 | ||
939 | else | |
940 | return (num_insns_constant_wide (high) | |
941 | + num_insns_constant_wide (low) + 1); | |
942 | } | |
4e74d8ec MM |
943 | } |
944 | ||
945 | else | |
946 | abort (); | |
947 | } | |
948 | ||
6f2f8311 RK |
949 | /* Return 1 if the operand is a CONST_DOUBLE and it can be put into a register |
950 | with one instruction per word. We only do this if we can safely read | |
951 | CONST_DOUBLE_{LOW,HIGH}. */ | |
9878760c RK |
952 | |
953 | int | |
954 | easy_fp_constant (op, mode) | |
955 | register rtx op; | |
956 | register enum machine_mode mode; | |
957 | { | |
9878760c RK |
958 | if (GET_CODE (op) != CONST_DOUBLE |
959 | || GET_MODE (op) != mode | |
4e74d8ec | 960 | || (GET_MODE_CLASS (mode) != MODE_FLOAT && mode != DImode)) |
9878760c RK |
961 | return 0; |
962 | ||
b6c9286a | 963 | /* Consider all constants with -msoft-float to be easy */ |
4e74d8ec | 964 | if (TARGET_SOFT_FLOAT && mode != DImode) |
b6c9286a MM |
965 | return 1; |
966 | ||
a7273471 MM |
967 | /* If we are using V.4 style PIC, consider all constants to be hard */ |
968 | if (flag_pic && (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS)) | |
969 | return 0; | |
970 | ||
5ae4759c MM |
971 | #ifdef TARGET_RELOCATABLE |
972 | /* Similarly if we are using -mrelocatable, consider all constants to be hard */ | |
973 | if (TARGET_RELOCATABLE) | |
974 | return 0; | |
975 | #endif | |
976 | ||
042259f2 DE |
977 | if (mode == DFmode) |
978 | { | |
979 | long k[2]; | |
980 | REAL_VALUE_TYPE rv; | |
981 | ||
982 | REAL_VALUE_FROM_CONST_DOUBLE (rv, op); | |
983 | REAL_VALUE_TO_TARGET_DOUBLE (rv, k); | |
9878760c | 984 | |
4e74d8ec MM |
985 | return (num_insns_constant_wide ((HOST_WIDE_INT)k[0]) == 1 |
986 | && num_insns_constant_wide ((HOST_WIDE_INT)k[1]) == 1); | |
042259f2 | 987 | } |
4e74d8ec MM |
988 | |
989 | else if (mode == SFmode) | |
042259f2 DE |
990 | { |
991 | long l; | |
992 | REAL_VALUE_TYPE rv; | |
993 | ||
994 | REAL_VALUE_FROM_CONST_DOUBLE (rv, op); | |
995 | REAL_VALUE_TO_TARGET_SINGLE (rv, l); | |
9878760c | 996 | |
4e74d8ec | 997 | return num_insns_constant_wide (l) == 1; |
042259f2 | 998 | } |
4e74d8ec | 999 | |
a260abc9 | 1000 | else if (mode == DImode) |
c81fc13e | 1001 | return ((TARGET_POWERPC64 |
a260abc9 DE |
1002 | && GET_CODE (op) == CONST_DOUBLE && CONST_DOUBLE_LOW (op) == 0) |
1003 | || (num_insns_constant (op, DImode) <= 2)); | |
4e74d8ec | 1004 | |
a9098fd0 GK |
1005 | else if (mode == SImode) |
1006 | return 1; | |
4e74d8ec MM |
1007 | else |
1008 | abort (); | |
9878760c | 1009 | } |
8f75773e | 1010 | |
50a0b056 GK |
1011 | /* Return 1 if the operand is 0.0. */ |
1012 | int | |
1013 | zero_fp_constant (op, mode) | |
1014 | register rtx op; | |
1015 | register enum machine_mode mode; | |
1016 | { | |
1017 | return GET_MODE_CLASS (mode) == MODE_FLOAT && op == CONST0_RTX (mode); | |
1018 | } | |
1019 | ||
b6c9286a MM |
1020 | /* Return 1 if the operand is in volatile memory. Note that during the |
1021 | RTL generation phase, memory_operand does not return TRUE for | |
1022 | volatile memory references. So this function allows us to | |
1023 | recognize volatile references where its safe. */ | |
1024 | ||
1025 | int | |
1026 | volatile_mem_operand (op, mode) | |
1027 | register rtx op; | |
1028 | enum machine_mode mode; | |
1029 | { | |
1030 | if (GET_CODE (op) != MEM) | |
1031 | return 0; | |
1032 | ||
1033 | if (!MEM_VOLATILE_P (op)) | |
1034 | return 0; | |
1035 | ||
1036 | if (mode != GET_MODE (op)) | |
1037 | return 0; | |
1038 | ||
1039 | if (reload_completed) | |
1040 | return memory_operand (op, mode); | |
1041 | ||
1042 | if (reload_in_progress) | |
1043 | return strict_memory_address_p (mode, XEXP (op, 0)); | |
1044 | ||
1045 | return memory_address_p (mode, XEXP (op, 0)); | |
1046 | } | |
1047 | ||
97f6e72f | 1048 | /* Return 1 if the operand is an offsettable memory operand. */ |
914c2e77 RK |
1049 | |
1050 | int | |
97f6e72f | 1051 | offsettable_mem_operand (op, mode) |
914c2e77 RK |
1052 | register rtx op; |
1053 | enum machine_mode mode; | |
1054 | { | |
97f6e72f | 1055 | return ((GET_CODE (op) == MEM) |
677a9668 | 1056 | && offsettable_address_p (reload_completed || reload_in_progress, |
97f6e72f | 1057 | mode, XEXP (op, 0))); |
914c2e77 RK |
1058 | } |
1059 | ||
9878760c RK |
1060 | /* Return 1 if the operand is either an easy FP constant (see above) or |
1061 | memory. */ | |
1062 | ||
1063 | int | |
1064 | mem_or_easy_const_operand (op, mode) | |
1065 | register rtx op; | |
1066 | enum machine_mode mode; | |
1067 | { | |
1068 | return memory_operand (op, mode) || easy_fp_constant (op, mode); | |
1069 | } | |
1070 | ||
1071 | /* Return 1 if the operand is either a non-special register or an item | |
5f59ecb7 | 1072 | that can be used as the operand of a `mode' add insn. */ |
9878760c RK |
1073 | |
1074 | int | |
1075 | add_operand (op, mode) | |
1076 | register rtx op; | |
1077 | enum machine_mode mode; | |
1078 | { | |
2bfcf297 DB |
1079 | if (GET_CODE (op) == CONST_INT) |
1080 | return (CONST_OK_FOR_LETTER_P (INTVAL(op), 'I') | |
1081 | || CONST_OK_FOR_LETTER_P (INTVAL(op), 'L')); | |
1082 | ||
1083 | return gpc_reg_operand (op, mode); | |
9878760c RK |
1084 | } |
1085 | ||
dcfedcd0 RK |
1086 | /* Return 1 if OP is a constant but not a valid add_operand. */ |
1087 | ||
1088 | int | |
1089 | non_add_cint_operand (op, mode) | |
1090 | register rtx op; | |
296b8152 | 1091 | enum machine_mode mode ATTRIBUTE_UNUSED; |
dcfedcd0 RK |
1092 | { |
1093 | return (GET_CODE (op) == CONST_INT | |
a7653a2c | 1094 | && (unsigned HOST_WIDE_INT) (INTVAL (op) + 0x8000) >= 0x10000 |
38886f37 | 1095 | && ! CONST_OK_FOR_LETTER_P (INTVAL (op), 'L')); |
dcfedcd0 RK |
1096 | } |
1097 | ||
9878760c RK |
1098 | /* Return 1 if the operand is a non-special register or a constant that |
1099 | can be used as the operand of an OR or XOR insn on the RS/6000. */ | |
1100 | ||
1101 | int | |
1102 | logical_operand (op, mode) | |
1103 | register rtx op; | |
1104 | enum machine_mode mode; | |
1105 | { | |
1d328b19 GK |
1106 | /* an unsigned representation of 'op'. */ |
1107 | unsigned HOST_WIDE_INT opl, oph; | |
1108 | ||
dfbdccdb GK |
1109 | if (gpc_reg_operand (op, mode)) |
1110 | return 1; | |
1d328b19 | 1111 | |
dfbdccdb | 1112 | if (GET_CODE (op) == CONST_INT) |
38886f37 | 1113 | opl = INTVAL (op); |
dfbdccdb GK |
1114 | else if (GET_CODE (op) == CONST_DOUBLE) |
1115 | { | |
1d328b19 GK |
1116 | if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT) |
1117 | abort(); | |
1118 | ||
1119 | opl = CONST_DOUBLE_LOW (op); | |
1120 | oph = CONST_DOUBLE_HIGH (op); | |
38886f37 AO |
1121 | |
1122 | if (oph != ((unsigned HOST_WIDE_INT)0 | |
1123 | - ((opl & ((unsigned HOST_WIDE_INT)1 | |
1124 | << (HOST_BITS_PER_WIDE_INT - 1))) != 0))) | |
1125 | return 0; | |
dfbdccdb GK |
1126 | } |
1127 | else | |
1128 | return 0; | |
1d328b19 | 1129 | |
38886f37 | 1130 | /* This must really be SImode, not MODE. */ |
78e1b90d | 1131 | if (opl != (unsigned HOST_WIDE_INT) trunc_int_for_mode (opl, SImode)) |
38886f37 AO |
1132 | return 0; |
1133 | ||
1134 | return ((opl & 0xffff) == 0 | |
1135 | || (opl & ~ (unsigned HOST_WIDE_INT) 0xffff) == 0); | |
9878760c RK |
1136 | } |
1137 | ||
dcfedcd0 | 1138 | /* Return 1 if C is a constant that is not a logical operand (as |
1d328b19 | 1139 | above), but could be split into one. */ |
dcfedcd0 RK |
1140 | |
1141 | int | |
1142 | non_logical_cint_operand (op, mode) | |
1143 | register rtx op; | |
5f59ecb7 | 1144 | enum machine_mode mode; |
dcfedcd0 | 1145 | { |
dfbdccdb | 1146 | return ((GET_CODE (op) == CONST_INT || GET_CODE (op) == CONST_DOUBLE) |
1d328b19 GK |
1147 | && ! logical_operand (op, mode) |
1148 | && reg_or_logical_cint_operand (op, mode)); | |
dcfedcd0 RK |
1149 | } |
1150 | ||
19ba8161 | 1151 | /* Return 1 if C is a constant that can be encoded in a 32-bit mask on the |
9878760c RK |
1152 | RS/6000. It is if there are no more than two 1->0 or 0->1 transitions. |
1153 | Reject all ones and all zeros, since these should have been optimized | |
1154 | away and confuse the making of MB and ME. */ | |
1155 | ||
1156 | int | |
19ba8161 DE |
1157 | mask_operand (op, mode) |
1158 | register rtx op; | |
1159 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
9878760c | 1160 | { |
19ba8161 | 1161 | HOST_WIDE_INT c; |
9878760c RK |
1162 | int i; |
1163 | int last_bit_value; | |
1164 | int transitions = 0; | |
1165 | ||
19ba8161 DE |
1166 | if (GET_CODE (op) != CONST_INT) |
1167 | return 0; | |
1168 | ||
1169 | c = INTVAL (op); | |
1170 | ||
9878760c RK |
1171 | if (c == 0 || c == ~0) |
1172 | return 0; | |
1173 | ||
1174 | last_bit_value = c & 1; | |
1175 | ||
1176 | for (i = 1; i < 32; i++) | |
1177 | if (((c >>= 1) & 1) != last_bit_value) | |
1178 | last_bit_value ^= 1, transitions++; | |
1179 | ||
1180 | return transitions <= 2; | |
1181 | } | |
1182 | ||
a260abc9 DE |
1183 | /* Return 1 if the operand is a constant that is a PowerPC64 mask. |
1184 | It is if there are no more than one 1->0 or 0->1 transitions. | |
1185 | Reject all ones and all zeros, since these should have been optimized | |
1186 | away and confuse the making of MB and ME. */ | |
9878760c RK |
1187 | |
1188 | int | |
a260abc9 DE |
1189 | mask64_operand (op, mode) |
1190 | register rtx op; | |
1191 | enum machine_mode mode; | |
1192 | { | |
1193 | if (GET_CODE (op) == CONST_INT) | |
1194 | { | |
1195 | HOST_WIDE_INT c = INTVAL (op); | |
1196 | int i; | |
1197 | int last_bit_value; | |
1198 | int transitions = 0; | |
1199 | ||
1200 | if (c == 0 || c == ~0) | |
1201 | return 0; | |
1202 | ||
1203 | last_bit_value = c & 1; | |
1204 | ||
1205 | for (i = 1; i < HOST_BITS_PER_WIDE_INT; i++) | |
1206 | if (((c >>= 1) & 1) != last_bit_value) | |
1207 | last_bit_value ^= 1, transitions++; | |
1208 | ||
e2c953b6 DE |
1209 | return transitions <= 1; |
1210 | } | |
1211 | else if (GET_CODE (op) == CONST_DOUBLE | |
1212 | && (mode == VOIDmode || mode == DImode)) | |
1213 | { | |
1214 | HOST_WIDE_INT low = CONST_DOUBLE_LOW (op); | |
1215 | #if HOST_BITS_PER_WIDE_INT == 32 | |
1216 | HOST_WIDE_INT high = CONST_DOUBLE_HIGH (op); | |
1217 | #endif | |
1218 | int i; | |
1219 | int last_bit_value; | |
1220 | int transitions = 0; | |
1221 | ||
1222 | if ((low == 0 | |
1223 | #if HOST_BITS_PER_WIDE_INT == 32 | |
1224 | && high == 0 | |
1225 | #endif | |
1226 | ) | |
1227 | || (low == ~0 | |
1228 | #if HOST_BITS_PER_WIDE_INT == 32 | |
1229 | && high == ~0 | |
1230 | #endif | |
1231 | )) | |
1232 | return 0; | |
1233 | ||
1234 | last_bit_value = low & 1; | |
1235 | ||
1236 | for (i = 1; i < HOST_BITS_PER_WIDE_INT; i++) | |
1237 | if (((low >>= 1) & 1) != last_bit_value) | |
1238 | last_bit_value ^= 1, transitions++; | |
1239 | ||
a238cd8b | 1240 | #if HOST_BITS_PER_WIDE_INT == 32 |
e2c953b6 DE |
1241 | if ((high & 1) != last_bit_value) |
1242 | last_bit_value ^= 1, transitions++; | |
1243 | ||
1244 | for (i = 1; i < HOST_BITS_PER_WIDE_INT; i++) | |
1245 | if (((high >>= 1) & 1) != last_bit_value) | |
1246 | last_bit_value ^= 1, transitions++; | |
a260abc9 DE |
1247 | #endif |
1248 | ||
1249 | return transitions <= 1; | |
1250 | } | |
e2c953b6 DE |
1251 | else |
1252 | return 0; | |
1253 | } | |
1254 | ||
1255 | /* Return 1 if the operand is a constant that is a PowerPC64 mask. | |
1256 | It is if there are no more than two 1->0 or 0->1 transitions. | |
1257 | Reject all ones and all zeros, since these should have been optimized | |
1258 | away and confuse the making of MB and ME. */ | |
1259 | ||
1260 | int | |
1261 | rldic_operand (op, mode) | |
1262 | register rtx op; | |
1263 | enum machine_mode mode; | |
1264 | { | |
1265 | if (GET_CODE (op) == CONST_INT) | |
1266 | { | |
1267 | HOST_WIDE_INT c = INTVAL (op); | |
1268 | int i; | |
1269 | int last_bit_value; | |
1270 | int transitions = 0; | |
1271 | ||
1272 | if (c == 0 || c == ~0) | |
1273 | return 0; | |
1274 | ||
1275 | last_bit_value = c & 1; | |
1276 | ||
1277 | for (i = 1; i < HOST_BITS_PER_WIDE_INT; i++) | |
1278 | if (((c >>= 1) & 1) != last_bit_value) | |
1279 | last_bit_value ^= 1, transitions++; | |
1280 | ||
1281 | return transitions <= 2; | |
1282 | } | |
a260abc9 DE |
1283 | else if (GET_CODE (op) == CONST_DOUBLE |
1284 | && (mode == VOIDmode || mode == DImode)) | |
1285 | { | |
1286 | HOST_WIDE_INT low = CONST_DOUBLE_LOW (op); | |
a238cd8b | 1287 | #if HOST_BITS_PER_WIDE_INT == 32 |
a260abc9 DE |
1288 | HOST_WIDE_INT high = CONST_DOUBLE_HIGH (op); |
1289 | #endif | |
1290 | int i; | |
1291 | int last_bit_value; | |
1292 | int transitions = 0; | |
1293 | ||
1294 | if ((low == 0 | |
a238cd8b | 1295 | #if HOST_BITS_PER_WIDE_INT == 32 |
a260abc9 DE |
1296 | && high == 0 |
1297 | #endif | |
1298 | ) | |
1299 | || (low == ~0 | |
a238cd8b | 1300 | #if HOST_BITS_PER_WIDE_INT == 32 |
a260abc9 DE |
1301 | && high == ~0 |
1302 | #endif | |
1303 | )) | |
1304 | return 0; | |
1305 | ||
1306 | last_bit_value = low & 1; | |
1307 | ||
1308 | for (i = 1; i < HOST_BITS_PER_WIDE_INT; i++) | |
1309 | if (((low >>= 1) & 1) != last_bit_value) | |
1310 | last_bit_value ^= 1, transitions++; | |
1311 | ||
a238cd8b | 1312 | #if HOST_BITS_PER_WIDE_INT == 32 |
a260abc9 DE |
1313 | if ((high & 1) != last_bit_value) |
1314 | last_bit_value ^= 1, transitions++; | |
1315 | ||
1316 | for (i = 1; i < HOST_BITS_PER_WIDE_INT; i++) | |
1317 | if (((high >>= 1) & 1) != last_bit_value) | |
1318 | last_bit_value ^= 1, transitions++; | |
1319 | #endif | |
1320 | ||
e2c953b6 | 1321 | return transitions <= 2; |
a260abc9 DE |
1322 | } |
1323 | else | |
1324 | return 0; | |
1325 | } | |
1326 | ||
1327 | /* Return 1 if the operand is either a non-special register or a constant | |
1328 | that can be used as the operand of a PowerPC64 logical AND insn. */ | |
1329 | ||
1330 | int | |
1331 | and64_operand (op, mode) | |
9878760c RK |
1332 | register rtx op; |
1333 | enum machine_mode mode; | |
1334 | { | |
9ebbca7d | 1335 | if (fixed_regs[CR0_REGNO]) /* CR0 not available, don't do andi./andis. */ |
52d3af72 DE |
1336 | return (gpc_reg_operand (op, mode) || mask64_operand (op, mode)); |
1337 | ||
1338 | return (logical_operand (op, mode) || mask64_operand (op, mode)); | |
9878760c RK |
1339 | } |
1340 | ||
a260abc9 DE |
1341 | /* Return 1 if the operand is either a non-special register or a |
1342 | constant that can be used as the operand of an RS/6000 logical AND insn. */ | |
dcfedcd0 RK |
1343 | |
1344 | int | |
a260abc9 DE |
1345 | and_operand (op, mode) |
1346 | register rtx op; | |
1347 | enum machine_mode mode; | |
dcfedcd0 | 1348 | { |
9ebbca7d | 1349 | if (fixed_regs[CR0_REGNO]) /* CR0 not available, don't do andi./andis. */ |
52d3af72 DE |
1350 | return (gpc_reg_operand (op, mode) || mask_operand (op, mode)); |
1351 | ||
1352 | return (logical_operand (op, mode) || mask_operand (op, mode)); | |
dcfedcd0 RK |
1353 | } |
1354 | ||
9878760c RK |
1355 | /* Return 1 if the operand is a general register or memory operand. */ |
1356 | ||
1357 | int | |
1358 | reg_or_mem_operand (op, mode) | |
1359 | register rtx op; | |
1360 | register enum machine_mode mode; | |
1361 | { | |
b6c9286a MM |
1362 | return (gpc_reg_operand (op, mode) |
1363 | || memory_operand (op, mode) | |
1364 | || volatile_mem_operand (op, mode)); | |
9878760c RK |
1365 | } |
1366 | ||
a7a813f7 | 1367 | /* Return 1 if the operand is a general register or memory operand without |
3cb999d8 | 1368 | pre_inc or pre_dec which produces invalid form of PowerPC lwa |
a7a813f7 RK |
1369 | instruction. */ |
1370 | ||
1371 | int | |
1372 | lwa_operand (op, mode) | |
1373 | register rtx op; | |
1374 | register enum machine_mode mode; | |
1375 | { | |
1376 | rtx inner = op; | |
1377 | ||
1378 | if (reload_completed && GET_CODE (inner) == SUBREG) | |
1379 | inner = SUBREG_REG (inner); | |
1380 | ||
1381 | return gpc_reg_operand (inner, mode) | |
1382 | || (memory_operand (inner, mode) | |
1383 | && GET_CODE (XEXP (inner, 0)) != PRE_INC | |
1384 | && GET_CODE (XEXP (inner, 0)) != PRE_DEC); | |
1385 | } | |
1386 | ||
9878760c RK |
1387 | /* Return 1 if the operand, used inside a MEM, is a valid first argument |
1388 | to CALL. This is a SYMBOL_REF or a pseudo-register, which will be | |
1389 | forced to lr. */ | |
1390 | ||
1391 | int | |
1392 | call_operand (op, mode) | |
1393 | register rtx op; | |
1394 | enum machine_mode mode; | |
1395 | { | |
1396 | if (mode != VOIDmode && GET_MODE (op) != mode) | |
1397 | return 0; | |
1398 | ||
1399 | return (GET_CODE (op) == SYMBOL_REF | |
1400 | || (GET_CODE (op) == REG && REGNO (op) >= FIRST_PSEUDO_REGISTER)); | |
1401 | } | |
1402 | ||
2af3d377 RK |
1403 | |
1404 | /* Return 1 if the operand is a SYMBOL_REF for a function known to be in | |
8f1b829e | 1405 | this file and the function is not weakly defined. */ |
2af3d377 RK |
1406 | |
1407 | int | |
1408 | current_file_function_operand (op, mode) | |
1409 | register rtx op; | |
296b8152 | 1410 | enum machine_mode mode ATTRIBUTE_UNUSED; |
2af3d377 RK |
1411 | { |
1412 | return (GET_CODE (op) == SYMBOL_REF | |
1413 | && (SYMBOL_REF_FLAG (op) | |
8f1b829e | 1414 | || (op == XEXP (DECL_RTL (current_function_decl), 0) |
c81fc13e | 1415 | && ! DECL_WEAK (current_function_decl)))); |
2af3d377 RK |
1416 | } |
1417 | ||
1418 | ||
9878760c RK |
1419 | /* Return 1 if this operand is a valid input for a move insn. */ |
1420 | ||
1421 | int | |
1422 | input_operand (op, mode) | |
1423 | register rtx op; | |
1424 | enum machine_mode mode; | |
1425 | { | |
eb4e8003 | 1426 | /* Memory is always valid. */ |
9878760c RK |
1427 | if (memory_operand (op, mode)) |
1428 | return 1; | |
1429 | ||
34792e82 | 1430 | /* Only a tiny bit of handling for CONSTANT_P_RTX is necessary. */ |
01b4cf2b | 1431 | if (GET_CODE (op) == CONSTANT_P_RTX) |
34792e82 JL |
1432 | return 1; |
1433 | ||
eb4e8003 RK |
1434 | /* For floating-point, easy constants are valid. */ |
1435 | if (GET_MODE_CLASS (mode) == MODE_FLOAT | |
1436 | && CONSTANT_P (op) | |
1437 | && easy_fp_constant (op, mode)) | |
1438 | return 1; | |
1439 | ||
4e74d8ec MM |
1440 | /* Allow any integer constant. */ |
1441 | if (GET_MODE_CLASS (mode) == MODE_INT | |
e675f625 | 1442 | && (GET_CODE (op) == CONST_INT |
e675f625 | 1443 | || GET_CODE (op) == CONST_DOUBLE)) |
4e74d8ec MM |
1444 | return 1; |
1445 | ||
eb4e8003 RK |
1446 | /* For floating-point or multi-word mode, the only remaining valid type |
1447 | is a register. */ | |
9878760c RK |
1448 | if (GET_MODE_CLASS (mode) == MODE_FLOAT |
1449 | || GET_MODE_SIZE (mode) > UNITS_PER_WORD) | |
eb4e8003 | 1450 | return register_operand (op, mode); |
9878760c | 1451 | |
88fe15a1 RK |
1452 | /* The only cases left are integral modes one word or smaller (we |
1453 | do not get called for MODE_CC values). These can be in any | |
1454 | register. */ | |
1455 | if (register_operand (op, mode)) | |
a8b3aeda | 1456 | return 1; |
88fe15a1 | 1457 | |
84cf9dda | 1458 | /* A SYMBOL_REF referring to the TOC is valid. */ |
7fec4abd | 1459 | if (LEGITIMATE_CONSTANT_POOL_ADDRESS_P (op)) |
84cf9dda RK |
1460 | return 1; |
1461 | ||
9ebbca7d GK |
1462 | /* A constant pool expression (relative to the TOC) is valid */ |
1463 | if (TOC_RELATIVE_EXPR_P (op)) | |
b6c9286a MM |
1464 | return 1; |
1465 | ||
88228c4b MM |
1466 | /* V.4 allows SYMBOL_REFs and CONSTs that are in the small data region |
1467 | to be valid. */ | |
c81bebd7 | 1468 | if ((DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) |
88228c4b MM |
1469 | && (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST) |
1470 | && small_data_operand (op, Pmode)) | |
1471 | return 1; | |
1472 | ||
042259f2 | 1473 | return 0; |
9878760c | 1474 | } |
7509c759 MM |
1475 | |
1476 | /* Return 1 for an operand in small memory on V.4/eabi */ | |
1477 | ||
1478 | int | |
1479 | small_data_operand (op, mode) | |
296b8152 KG |
1480 | rtx op ATTRIBUTE_UNUSED; |
1481 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
7509c759 | 1482 | { |
38c1f2d7 | 1483 | #if TARGET_ELF |
5f59ecb7 | 1484 | rtx sym_ref; |
7509c759 | 1485 | |
d9407988 | 1486 | if (rs6000_sdata == SDATA_NONE || rs6000_sdata == SDATA_DATA) |
a54d04b7 | 1487 | return 0; |
a54d04b7 | 1488 | |
5b9d9a0c | 1489 | if (DEFAULT_ABI != ABI_V4 && DEFAULT_ABI != ABI_SOLARIS) |
7509c759 MM |
1490 | return 0; |
1491 | ||
88228c4b MM |
1492 | if (GET_CODE (op) == SYMBOL_REF) |
1493 | sym_ref = op; | |
1494 | ||
1495 | else if (GET_CODE (op) != CONST | |
1496 | || GET_CODE (XEXP (op, 0)) != PLUS | |
1497 | || GET_CODE (XEXP (XEXP (op, 0), 0)) != SYMBOL_REF | |
1498 | || GET_CODE (XEXP (XEXP (op, 0), 1)) != CONST_INT) | |
7509c759 MM |
1499 | return 0; |
1500 | ||
88228c4b | 1501 | else |
dbf55e53 MM |
1502 | { |
1503 | rtx sum = XEXP (op, 0); | |
1504 | HOST_WIDE_INT summand; | |
1505 | ||
1506 | /* We have to be careful here, because it is the referenced address | |
1507 | that must be 32k from _SDA_BASE_, not just the symbol. */ | |
1508 | summand = INTVAL (XEXP (sum, 1)); | |
1509 | if (summand < 0 || summand > g_switch_value) | |
1510 | return 0; | |
1511 | ||
1512 | sym_ref = XEXP (sum, 0); | |
1513 | } | |
88228c4b MM |
1514 | |
1515 | if (*XSTR (sym_ref, 0) != '@') | |
7509c759 MM |
1516 | return 0; |
1517 | ||
1518 | return 1; | |
d9407988 MM |
1519 | |
1520 | #else | |
1521 | return 0; | |
1522 | #endif | |
7509c759 | 1523 | } |
9ebbca7d GK |
1524 | \f |
1525 | static int | |
1526 | constant_pool_expr_1 (op, have_sym, have_toc) | |
1527 | rtx op; | |
1528 | int *have_sym; | |
1529 | int *have_toc; | |
1530 | { | |
1531 | switch (GET_CODE(op)) | |
1532 | { | |
1533 | case SYMBOL_REF: | |
1534 | if (CONSTANT_POOL_ADDRESS_P (op)) | |
1535 | { | |
a9098fd0 | 1536 | if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (op), Pmode)) |
9ebbca7d GK |
1537 | { |
1538 | *have_sym = 1; | |
1539 | return 1; | |
1540 | } | |
1541 | else | |
1542 | return 0; | |
1543 | } | |
1544 | else if (! strcmp (XSTR (op, 0), toc_label_name)) | |
1545 | { | |
1546 | *have_toc = 1; | |
1547 | return 1; | |
1548 | } | |
1549 | else | |
1550 | return 0; | |
1551 | case PLUS: | |
1552 | case MINUS: | |
1553 | return constant_pool_expr_1 (XEXP (op, 0), have_sym, have_toc) && | |
1554 | constant_pool_expr_1 (XEXP (op, 1), have_sym, have_toc); | |
1555 | case CONST: | |
1556 | return constant_pool_expr_1 (XEXP (op, 0), have_sym, have_toc); | |
1557 | case CONST_INT: | |
1558 | return 1; | |
1559 | default: | |
1560 | return 0; | |
1561 | } | |
1562 | } | |
1563 | ||
1564 | int | |
1565 | constant_pool_expr_p (op) | |
1566 | rtx op; | |
1567 | { | |
1568 | int have_sym = 0; | |
1569 | int have_toc = 0; | |
1570 | return constant_pool_expr_1 (op, &have_sym, &have_toc) && have_sym; | |
1571 | } | |
1572 | ||
1573 | int | |
1574 | toc_relative_expr_p (op) | |
1575 | rtx op; | |
1576 | { | |
1577 | int have_sym = 0; | |
1578 | int have_toc = 0; | |
1579 | return constant_pool_expr_1 (op, &have_sym, &have_toc) && have_toc; | |
1580 | } | |
1581 | ||
1582 | /* Try machine-dependent ways of modifying an illegitimate address | |
1583 | to be legitimate. If we find one, return the new, valid address. | |
1584 | This is used from only one place: `memory_address' in explow.c. | |
1585 | ||
1586 | OLDX is the address as it was before break_out_memory_refs was called. | |
1587 | In some cases it is useful to look at this to decide what needs to be done. | |
1588 | ||
1589 | MODE is passed so that this macro can use GO_IF_LEGITIMATE_ADDRESS. | |
1590 | ||
1591 | It is always safe for this macro to do nothing. It exists to recognize | |
1592 | opportunities to optimize the output. | |
1593 | ||
1594 | On RS/6000, first check for the sum of a register with a constant | |
1595 | integer that is out of range. If so, generate code to add the | |
1596 | constant with the low-order 16 bits masked to the register and force | |
1597 | this result into another register (this can be done with `cau'). | |
1598 | Then generate an address of REG+(CONST&0xffff), allowing for the | |
1599 | possibility of bit 16 being a one. | |
1600 | ||
1601 | Then check for the sum of a register and something not constant, try to | |
1602 | load the other things into a register and return the sum. */ | |
1603 | rtx | |
1604 | rs6000_legitimize_address (x, oldx, mode) | |
1605 | rtx x; | |
1606 | rtx oldx ATTRIBUTE_UNUSED; | |
1607 | enum machine_mode mode; | |
1608 | { | |
1609 | if (GET_CODE (x) == PLUS | |
1610 | && GET_CODE (XEXP (x, 0)) == REG | |
1611 | && GET_CODE (XEXP (x, 1)) == CONST_INT | |
1612 | && (unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 1)) + 0x8000) >= 0x10000) | |
1613 | { | |
1614 | HOST_WIDE_INT high_int, low_int; | |
1615 | rtx sum; | |
1616 | high_int = INTVAL (XEXP (x, 1)) & (~ (HOST_WIDE_INT) 0xffff); | |
1617 | low_int = INTVAL (XEXP (x, 1)) & 0xffff; | |
1618 | if (low_int & 0x8000) | |
1619 | high_int += 0x10000, low_int |= ((HOST_WIDE_INT) -1) << 16; | |
1620 | sum = force_operand (gen_rtx_PLUS (Pmode, XEXP (x, 0), | |
1621 | GEN_INT (high_int)), 0); | |
1622 | return gen_rtx_PLUS (Pmode, sum, GEN_INT (low_int)); | |
1623 | } | |
1624 | else if (GET_CODE (x) == PLUS | |
1625 | && GET_CODE (XEXP (x, 0)) == REG | |
1626 | && GET_CODE (XEXP (x, 1)) != CONST_INT | |
1627 | && (TARGET_HARD_FLOAT || TARGET_POWERPC64 || mode != DFmode) | |
1628 | && (TARGET_POWERPC64 || mode != DImode) | |
1629 | && mode != TImode) | |
1630 | { | |
1631 | return gen_rtx_PLUS (Pmode, XEXP (x, 0), | |
1632 | force_reg (Pmode, force_operand (XEXP (x, 1), 0))); | |
1633 | } | |
1634 | else if (TARGET_ELF && TARGET_32BIT && TARGET_NO_TOC && ! flag_pic | |
1635 | && GET_CODE (x) != CONST_INT | |
1636 | && GET_CODE (x) != CONST_DOUBLE | |
1637 | && CONSTANT_P (x) | |
1638 | && (TARGET_HARD_FLOAT || mode != DFmode) | |
1639 | && mode != DImode | |
1640 | && mode != TImode) | |
1641 | { | |
1642 | rtx reg = gen_reg_rtx (Pmode); | |
1643 | emit_insn (gen_elf_high (reg, (x))); | |
1644 | return gen_rtx_LO_SUM (Pmode, reg, (x)); | |
1645 | } | |
ee890fe2 SS |
1646 | else if (TARGET_MACHO && TARGET_32BIT && TARGET_NO_TOC |
1647 | && ! flag_pic | |
1648 | && GET_CODE (x) != CONST_INT | |
1649 | && GET_CODE (x) != CONST_DOUBLE | |
1650 | && CONSTANT_P (x) | |
1651 | && (TARGET_HARD_FLOAT || mode != DFmode) | |
1652 | && mode != DImode | |
1653 | && mode != TImode) | |
1654 | { | |
1655 | rtx reg = gen_reg_rtx (Pmode); | |
1656 | emit_insn (gen_macho_high (reg, (x))); | |
1657 | return gen_rtx_LO_SUM (Pmode, reg, (x)); | |
1658 | } | |
9ebbca7d GK |
1659 | else if (TARGET_TOC |
1660 | && CONSTANT_POOL_EXPR_P (x) | |
a9098fd0 | 1661 | && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x), Pmode)) |
9ebbca7d GK |
1662 | { |
1663 | return create_TOC_reference (x); | |
1664 | } | |
1665 | else | |
1666 | return NULL_RTX; | |
1667 | } | |
258bfae2 FS |
1668 | |
1669 | /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression | |
1670 | that is a valid memory address for an instruction. | |
1671 | The MODE argument is the machine mode for the MEM expression | |
1672 | that wants to use this address. | |
1673 | ||
1674 | On the RS/6000, there are four valid address: a SYMBOL_REF that | |
1675 | refers to a constant pool entry of an address (or the sum of it | |
1676 | plus a constant), a short (16-bit signed) constant plus a register, | |
1677 | the sum of two registers, or a register indirect, possibly with an | |
1678 | auto-increment. For DFmode and DImode with an constant plus register, | |
1679 | we must ensure that both words are addressable or PowerPC64 with offset | |
1680 | word aligned. | |
1681 | ||
1682 | For modes spanning multiple registers (DFmode in 32-bit GPRs, | |
1683 | 32-bit DImode, TImode), indexed addressing cannot be used because | |
1684 | adjacent memory cells are accessed by adding word-sized offsets | |
1685 | during assembly output. */ | |
1686 | int | |
1687 | rs6000_legitimate_address (mode, x, reg_ok_strict) | |
1688 | enum machine_mode mode; | |
1689 | rtx x; | |
1690 | int reg_ok_strict; | |
1691 | { | |
1692 | if (LEGITIMATE_INDIRECT_ADDRESS_P (x, reg_ok_strict)) | |
1693 | return 1; | |
1694 | if ((GET_CODE (x) == PRE_INC || GET_CODE (x) == PRE_DEC) | |
1695 | && TARGET_UPDATE | |
1696 | && LEGITIMATE_INDIRECT_ADDRESS_P (XEXP (x, 0), reg_ok_strict)) | |
1697 | return 1; | |
1698 | if (LEGITIMATE_SMALL_DATA_P (mode, x)) | |
1699 | return 1; | |
1700 | if (LEGITIMATE_CONSTANT_POOL_ADDRESS_P (x)) | |
1701 | return 1; | |
1702 | /* If not REG_OK_STRICT (before reload) let pass any stack offset. */ | |
1703 | if (! reg_ok_strict | |
1704 | && GET_CODE (x) == PLUS | |
1705 | && GET_CODE (XEXP (x, 0)) == REG | |
1706 | && XEXP (x, 0) == virtual_stack_vars_rtx | |
1707 | && GET_CODE (XEXP (x, 1)) == CONST_INT) | |
1708 | return 1; | |
1709 | if (LEGITIMATE_OFFSET_ADDRESS_P (mode, x, reg_ok_strict)) | |
1710 | return 1; | |
1711 | if (mode != TImode | |
1712 | && (TARGET_HARD_FLOAT || TARGET_POWERPC64 || mode != DFmode) | |
1713 | && (TARGET_POWERPC64 || mode != DImode) | |
1714 | && LEGITIMATE_INDEXED_ADDRESS_P (x, reg_ok_strict)) | |
1715 | return 1; | |
1716 | if (LEGITIMATE_LO_SUM_ADDRESS_P (mode, x, reg_ok_strict)) | |
1717 | return 1; | |
1718 | return 0; | |
1719 | } | |
fb4d4348 | 1720 | \f |
2bfcf297 DB |
1721 | /* Try to output insns to set TARGET equal to the constant C if it can be |
1722 | done in less than N insns. Do all computations in MODE. Returns the place | |
1723 | where the output has been placed if it can be done and the insns have been | |
1724 | emitted. If it would take more than N insns, zero is returned and no | |
1725 | insns and emitted. */ | |
1726 | ||
1727 | rtx | |
1728 | rs6000_emit_set_const (dest, mode, source, n) | |
1729 | rtx dest, source; | |
1730 | enum machine_mode mode; | |
1731 | int n ATTRIBUTE_UNUSED; | |
1732 | { | |
1733 | HOST_WIDE_INT c0, c1; | |
1734 | ||
1735 | if (mode == QImode || mode == HImode || mode == SImode) | |
1736 | { | |
1737 | if (dest == NULL) | |
1738 | dest = gen_reg_rtx (mode); | |
1739 | emit_insn (gen_rtx_SET (VOIDmode, dest, source)); | |
1740 | return dest; | |
1741 | } | |
1742 | ||
1743 | if (GET_CODE (source) == CONST_INT) | |
1744 | { | |
1745 | c0 = INTVAL (source); | |
1746 | c1 = -(c0 < 0); | |
1747 | } | |
1748 | else if (GET_CODE (source) == CONST_DOUBLE) | |
1749 | { | |
1750 | #if HOST_BITS_PER_WIDE_INT >= 64 | |
1751 | c0 = CONST_DOUBLE_LOW (source); | |
1752 | c1 = -(c0 < 0); | |
1753 | #else | |
1754 | c0 = CONST_DOUBLE_LOW (source); | |
1755 | c1 = CONST_DOUBLE_HIGH (source); | |
1756 | #endif | |
1757 | } | |
1758 | else | |
1759 | abort(); | |
1760 | ||
1761 | return rs6000_emit_set_long_const (dest, c0, c1); | |
1762 | } | |
1763 | ||
1764 | /* Having failed to find a 3 insn sequence in rs6000_emit_set_const, | |
1765 | fall back to a straight forward decomposition. We do this to avoid | |
1766 | exponential run times encountered when looking for longer sequences | |
1767 | with rs6000_emit_set_const. */ | |
1768 | static rtx | |
1769 | rs6000_emit_set_long_const (dest, c1, c2) | |
1770 | rtx dest; | |
1771 | HOST_WIDE_INT c1, c2; | |
1772 | { | |
1773 | if (!TARGET_POWERPC64) | |
1774 | { | |
1775 | rtx operand1, operand2; | |
1776 | ||
1777 | operand1 = operand_subword_force (dest, WORDS_BIG_ENDIAN == 0, | |
1778 | DImode); | |
1779 | operand2 = operand_subword_force (dest, WORDS_BIG_ENDIAN != 0, | |
1780 | DImode); | |
1781 | emit_move_insn (operand1, GEN_INT (c1)); | |
1782 | emit_move_insn (operand2, GEN_INT (c2)); | |
1783 | } | |
1784 | else | |
1785 | { | |
1786 | HOST_WIDE_INT d1, d2, d3, d4; | |
1787 | ||
1788 | /* Decompose the entire word */ | |
1789 | #if HOST_BITS_PER_WIDE_INT >= 64 | |
1790 | if (c2 != -(c1 < 0)) | |
1791 | abort (); | |
1792 | d1 = ((c1 & 0xffff) ^ 0x8000) - 0x8000; | |
1793 | c1 -= d1; | |
1794 | d2 = ((c1 & 0xffffffff) ^ 0x80000000) - 0x80000000; | |
1795 | c1 = (c1 - d2) >> 32; | |
1796 | d3 = ((c1 & 0xffff) ^ 0x8000) - 0x8000; | |
1797 | c1 -= d3; | |
1798 | d4 = ((c1 & 0xffffffff) ^ 0x80000000) - 0x80000000; | |
1799 | if (c1 != d4) | |
1800 | abort (); | |
1801 | #else | |
1802 | d1 = ((c1 & 0xffff) ^ 0x8000) - 0x8000; | |
1803 | c1 -= d1; | |
1804 | d2 = ((c1 & 0xffffffff) ^ 0x80000000) - 0x80000000; | |
1805 | if (c1 != d2) | |
1806 | abort (); | |
1807 | c2 += (d2 < 0); | |
1808 | d3 = ((c2 & 0xffff) ^ 0x8000) - 0x8000; | |
1809 | c2 -= d3; | |
1810 | d4 = ((c2 & 0xffffffff) ^ 0x80000000) - 0x80000000; | |
1811 | if (c2 != d4) | |
1812 | abort (); | |
1813 | #endif | |
1814 | ||
1815 | /* Construct the high word */ | |
1816 | if (d4) | |
1817 | { | |
1818 | emit_move_insn (dest, GEN_INT (d4)); | |
1819 | if (d3) | |
1820 | emit_move_insn (dest, | |
1821 | gen_rtx_PLUS (DImode, dest, GEN_INT (d3))); | |
1822 | } | |
1823 | else | |
1824 | emit_move_insn (dest, GEN_INT (d3)); | |
1825 | ||
1826 | /* Shift it into place */ | |
1827 | emit_move_insn (dest, gen_rtx_ASHIFT (DImode, dest, GEN_INT (32))); | |
1828 | ||
1829 | /* Add in the low bits. */ | |
1830 | if (d2) | |
1831 | emit_move_insn (dest, gen_rtx_PLUS (DImode, dest, GEN_INT (d2))); | |
1832 | if (d1) | |
1833 | emit_move_insn (dest, gen_rtx_PLUS (DImode, dest, GEN_INT (d1))); | |
1834 | } | |
1835 | ||
1836 | return dest; | |
1837 | } | |
1838 | ||
fb4d4348 GK |
1839 | /* Emit a move from SOURCE to DEST in mode MODE. */ |
1840 | void | |
1841 | rs6000_emit_move (dest, source, mode) | |
1842 | rtx dest; | |
1843 | rtx source; | |
1844 | enum machine_mode mode; | |
1845 | { | |
1846 | rtx operands[2]; | |
1847 | operands[0] = dest; | |
1848 | operands[1] = source; | |
1849 | ||
1850 | /* Sanity checks. Check that we get CONST_DOUBLE only when we should. */ | |
1851 | if (GET_CODE (operands[1]) == CONST_DOUBLE | |
1852 | && ! FLOAT_MODE_P (mode) | |
1853 | && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT) | |
1854 | { | |
1855 | /* FIXME. This should never happen. */ | |
1856 | /* Since it seems that it does, do the safe thing and convert | |
1857 | to a CONST_INT. */ | |
1858 | operands[1] = | |
1859 | GEN_INT (trunc_int_for_mode (CONST_DOUBLE_LOW (operands[1]), mode)); | |
1860 | } | |
1861 | if (GET_CODE (operands[1]) == CONST_DOUBLE | |
1862 | && ! FLOAT_MODE_P (mode) | |
1863 | && ((CONST_DOUBLE_HIGH (operands[1]) == 0 | |
1864 | && CONST_DOUBLE_LOW (operands[1]) >= 0) | |
1865 | || (CONST_DOUBLE_HIGH (operands[1]) == -1 | |
1866 | && CONST_DOUBLE_LOW (operands[1]) < 0))) | |
1867 | abort (); | |
1868 | ||
1869 | if (! no_new_pseudos && GET_CODE (operands[0]) != REG) | |
1870 | operands[1] = force_reg (mode, operands[1]); | |
a9098fd0 | 1871 | |
ffc14f31 GK |
1872 | if (mode == SFmode && ! TARGET_POWERPC && TARGET_HARD_FLOAT |
1873 | && GET_CODE (operands[0]) == MEM) | |
fb4d4348 | 1874 | { |
ffc14f31 GK |
1875 | int regnum; |
1876 | ||
1877 | if (reload_in_progress || reload_completed) | |
1878 | regnum = true_regnum (operands[1]); | |
1879 | else if (GET_CODE (operands[1]) == REG) | |
1880 | regnum = REGNO (operands[1]); | |
1881 | else | |
1882 | regnum = -1; | |
fb4d4348 GK |
1883 | |
1884 | /* If operands[1] is a register, on POWER it may have | |
1885 | double-precision data in it, so truncate it to single | |
1886 | precision. */ | |
1887 | if (FP_REGNO_P (regnum) || regnum >= FIRST_PSEUDO_REGISTER) | |
1888 | { | |
1889 | rtx newreg; | |
1890 | newreg = (no_new_pseudos ? operands[1] : gen_reg_rtx (mode)); | |
1891 | emit_insn (gen_aux_truncdfsf2 (newreg, operands[1])); | |
1892 | operands[1] = newreg; | |
1893 | } | |
1894 | } | |
1895 | ||
a9098fd0 GK |
1896 | /* Handle the case where reload calls us with an invalid address; |
1897 | and the case of CONSTANT_P_RTX. */ | |
1898 | if (! general_operand (operands[1], mode) | |
1899 | || ! nonimmediate_operand (operands[0], mode) | |
1900 | || GET_CODE (operands[1]) == CONSTANT_P_RTX) | |
fb4d4348 GK |
1901 | { |
1902 | emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1])); | |
1903 | return; | |
1904 | } | |
a9098fd0 | 1905 | |
fb4d4348 GK |
1906 | /* FIXME: In the long term, this switch statement should go away |
1907 | and be replaced by a sequence of tests based on things like | |
1908 | mode == Pmode. */ | |
1909 | switch (mode) | |
1910 | { | |
1911 | case HImode: | |
1912 | case QImode: | |
1913 | if (CONSTANT_P (operands[1]) | |
1914 | && GET_CODE (operands[1]) != CONST_INT) | |
a9098fd0 | 1915 | operands[1] = force_const_mem (mode, operands[1]); |
fb4d4348 GK |
1916 | break; |
1917 | ||
1918 | case DFmode: | |
1919 | case SFmode: | |
1920 | if (CONSTANT_P (operands[1]) | |
1921 | && ! easy_fp_constant (operands[1], mode)) | |
a9098fd0 | 1922 | operands[1] = force_const_mem (mode, operands[1]); |
fb4d4348 GK |
1923 | break; |
1924 | ||
1925 | case SImode: | |
a9098fd0 | 1926 | case DImode: |
fb4d4348 GK |
1927 | /* Use default pattern for address of ELF small data */ |
1928 | if (TARGET_ELF | |
a9098fd0 | 1929 | && mode == Pmode |
fb4d4348 | 1930 | && (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) |
a9098fd0 GK |
1931 | && (GET_CODE (operands[1]) == SYMBOL_REF |
1932 | || GET_CODE (operands[1]) == CONST) | |
1933 | && small_data_operand (operands[1], mode)) | |
fb4d4348 GK |
1934 | { |
1935 | emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1])); | |
1936 | return; | |
1937 | } | |
1938 | ||
1939 | if ((DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) | |
a9098fd0 GK |
1940 | && mode == Pmode && mode == SImode |
1941 | && flag_pic == 1 && got_operand (operands[1], mode)) | |
fb4d4348 GK |
1942 | { |
1943 | emit_insn (gen_movsi_got (operands[0], operands[1])); | |
1944 | return; | |
1945 | } | |
1946 | ||
ee890fe2 SS |
1947 | if ((TARGET_ELF || DEFAULT_ABI == ABI_DARWIN) |
1948 | && TARGET_NO_TOC && ! flag_pic | |
a9098fd0 | 1949 | && mode == Pmode |
fb4d4348 GK |
1950 | && CONSTANT_P (operands[1]) |
1951 | && GET_CODE (operands[1]) != HIGH | |
1952 | && GET_CODE (operands[1]) != CONST_INT) | |
1953 | { | |
a9098fd0 | 1954 | rtx target = (no_new_pseudos ? operands[0] : gen_reg_rtx (mode)); |
fb4d4348 GK |
1955 | |
1956 | /* If this is a function address on -mcall-aixdesc, | |
1957 | convert it to the address of the descriptor. */ | |
1958 | if (DEFAULT_ABI == ABI_AIX | |
1959 | && GET_CODE (operands[1]) == SYMBOL_REF | |
1960 | && XSTR (operands[1], 0)[0] == '.') | |
1961 | { | |
1962 | const char *name = XSTR (operands[1], 0); | |
1963 | rtx new_ref; | |
1964 | while (*name == '.') | |
1965 | name++; | |
1966 | new_ref = gen_rtx_SYMBOL_REF (Pmode, name); | |
1967 | CONSTANT_POOL_ADDRESS_P (new_ref) | |
1968 | = CONSTANT_POOL_ADDRESS_P (operands[1]); | |
1969 | SYMBOL_REF_FLAG (new_ref) = SYMBOL_REF_FLAG (operands[1]); | |
1970 | SYMBOL_REF_USED (new_ref) = SYMBOL_REF_USED (operands[1]); | |
1971 | operands[1] = new_ref; | |
1972 | } | |
7509c759 | 1973 | |
ee890fe2 SS |
1974 | if (DEFAULT_ABI == ABI_DARWIN) |
1975 | { | |
1976 | emit_insn (gen_macho_high (target, operands[1])); | |
1977 | emit_insn (gen_macho_low (operands[0], target, operands[1])); | |
1978 | return; | |
1979 | } | |
1980 | ||
fb4d4348 GK |
1981 | emit_insn (gen_elf_high (target, operands[1])); |
1982 | emit_insn (gen_elf_low (operands[0], target, operands[1])); | |
1983 | return; | |
1984 | } | |
1985 | ||
a9098fd0 GK |
1986 | /* If this is a SYMBOL_REF that refers to a constant pool entry, |
1987 | and we have put it in the TOC, we just need to make a TOC-relative | |
1988 | reference to it. */ | |
1989 | if (TARGET_TOC | |
1990 | && GET_CODE (operands[1]) == SYMBOL_REF | |
1991 | && CONSTANT_POOL_EXPR_P (operands[1]) | |
1992 | && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (operands[1]), | |
1993 | get_pool_mode (operands[1]))) | |
fb4d4348 | 1994 | { |
a9098fd0 | 1995 | operands[1] = create_TOC_reference (operands[1]); |
fb4d4348 | 1996 | } |
a9098fd0 GK |
1997 | else if (mode == Pmode |
1998 | && CONSTANT_P (operands[1]) | |
38886f37 AO |
1999 | && ((GET_CODE (operands[1]) != CONST_INT |
2000 | && ! easy_fp_constant (operands[1], mode)) | |
2001 | || (GET_CODE (operands[1]) == CONST_INT | |
2002 | && num_insns_constant (operands[1], mode) > 2) | |
2003 | || (GET_CODE (operands[0]) == REG | |
2004 | && FP_REGNO_P (REGNO (operands[0])))) | |
a9098fd0 GK |
2005 | && GET_CODE (operands[1]) != HIGH |
2006 | && ! LEGITIMATE_CONSTANT_POOL_ADDRESS_P (operands[1]) | |
2007 | && ! TOC_RELATIVE_EXPR_P (operands[1])) | |
fb4d4348 GK |
2008 | { |
2009 | /* Emit a USE operation so that the constant isn't deleted if | |
2010 | expensive optimizations are turned on because nobody | |
2011 | references it. This should only be done for operands that | |
2012 | contain SYMBOL_REFs with CONSTANT_POOL_ADDRESS_P set. | |
2013 | This should not be done for operands that contain LABEL_REFs. | |
2014 | For now, we just handle the obvious case. */ | |
2015 | if (GET_CODE (operands[1]) != LABEL_REF) | |
2016 | emit_insn (gen_rtx_USE (VOIDmode, operands[1])); | |
2017 | ||
ee890fe2 SS |
2018 | /* Darwin uses a special PIC legitimizer. */ |
2019 | if (DEFAULT_ABI == ABI_DARWIN && flag_pic) | |
2020 | { | |
78e1b90d | 2021 | #if TARGET_MACHO |
ee890fe2 SS |
2022 | rtx temp_reg = ((reload_in_progress || reload_completed) |
2023 | ? operands[0] : NULL); | |
2024 | ||
ee890fe2 SS |
2025 | operands[1] = |
2026 | rs6000_machopic_legitimize_pic_address (operands[1], mode, | |
2027 | temp_reg); | |
2028 | #endif | |
2029 | emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1])); | |
2030 | return; | |
2031 | } | |
2032 | ||
fb4d4348 GK |
2033 | /* If we are to limit the number of things we put in the TOC and |
2034 | this is a symbol plus a constant we can add in one insn, | |
2035 | just put the symbol in the TOC and add the constant. Don't do | |
2036 | this if reload is in progress. */ | |
2037 | if (GET_CODE (operands[1]) == CONST | |
2038 | && TARGET_NO_SUM_IN_TOC && ! reload_in_progress | |
2039 | && GET_CODE (XEXP (operands[1], 0)) == PLUS | |
a9098fd0 | 2040 | && add_operand (XEXP (XEXP (operands[1], 0), 1), mode) |
fb4d4348 GK |
2041 | && (GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == LABEL_REF |
2042 | || GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == SYMBOL_REF) | |
2043 | && ! side_effects_p (operands[0])) | |
2044 | { | |
a9098fd0 | 2045 | rtx sym = force_const_mem (mode, XEXP (XEXP (operands[1], 0), 0)); |
fb4d4348 GK |
2046 | rtx other = XEXP (XEXP (operands[1], 0), 1); |
2047 | ||
a9098fd0 GK |
2048 | sym = force_reg (mode, sym); |
2049 | if (mode == SImode) | |
2050 | emit_insn (gen_addsi3 (operands[0], sym, other)); | |
2051 | else | |
2052 | emit_insn (gen_adddi3 (operands[0], sym, other)); | |
fb4d4348 GK |
2053 | return; |
2054 | } | |
2055 | ||
a9098fd0 | 2056 | operands[1] = force_const_mem (mode, operands[1]); |
fb4d4348 GK |
2057 | |
2058 | if (TARGET_TOC | |
d34c5b80 DE |
2059 | && CONSTANT_POOL_EXPR_P (XEXP (operands[1], 0)) |
2060 | && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P ( | |
2061 | get_pool_constant (XEXP (operands[1], 0)), | |
2062 | get_pool_mode (XEXP (operands[1], 0)))) | |
a9098fd0 | 2063 | { |
ba4828e0 RK |
2064 | operands[1] |
2065 | = gen_rtx_MEM (mode, | |
2066 | create_TOC_reference (XEXP (operands[1], 0))); | |
2067 | set_mem_alias_set (operands[1], get_TOC_alias_set ()); | |
fb4d4348 | 2068 | RTX_UNCHANGING_P (operands[1]) = 1; |
a9098fd0 | 2069 | } |
fb4d4348 GK |
2070 | } |
2071 | break; | |
a9098fd0 | 2072 | |
fb4d4348 GK |
2073 | case TImode: |
2074 | if (GET_CODE (operands[0]) == MEM | |
2075 | && GET_CODE (XEXP (operands[0], 0)) != REG | |
2076 | && ! reload_in_progress) | |
792760b9 RK |
2077 | operands[0] |
2078 | = replace_equiv_address (operands[0], | |
2079 | copy_addr_to_reg (XEXP (operands[0], 0))); | |
fb4d4348 GK |
2080 | |
2081 | if (GET_CODE (operands[1]) == MEM | |
2082 | && GET_CODE (XEXP (operands[1], 0)) != REG | |
2083 | && ! reload_in_progress) | |
792760b9 RK |
2084 | operands[1] |
2085 | = replace_equiv_address (operands[1], | |
2086 | copy_addr_to_reg (XEXP (operands[1], 0))); | |
fb4d4348 GK |
2087 | break; |
2088 | ||
2089 | default: | |
2090 | abort (); | |
2091 | } | |
2092 | ||
a9098fd0 GK |
2093 | /* Above, we may have called force_const_mem which may have returned |
2094 | an invalid address. If we can, fix this up; otherwise, reload will | |
2095 | have to deal with it. */ | |
2096 | if (GET_CODE (operands[1]) == MEM | |
2097 | && ! memory_address_p (mode, XEXP (operands[1], 0)) | |
2098 | && ! reload_in_progress) | |
f4ef873c | 2099 | operands[1] = adjust_address (operands[1], mode, 0); |
a9098fd0 | 2100 | |
fb4d4348 | 2101 | emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1])); |
02a4ec28 | 2102 | return; |
fb4d4348 | 2103 | } |
4697a36c MM |
2104 | \f |
2105 | /* Initialize a variable CUM of type CUMULATIVE_ARGS | |
2106 | for a call to a function whose data type is FNTYPE. | |
2107 | For a library call, FNTYPE is 0. | |
2108 | ||
2109 | For incoming args we set the number of arguments in the prototype large | |
1c20ae99 | 2110 | so we never return a PARALLEL. */ |
4697a36c MM |
2111 | |
2112 | void | |
2113 | init_cumulative_args (cum, fntype, libname, incoming) | |
2114 | CUMULATIVE_ARGS *cum; | |
2115 | tree fntype; | |
296b8152 | 2116 | rtx libname ATTRIBUTE_UNUSED; |
4697a36c MM |
2117 | int incoming; |
2118 | { | |
2119 | static CUMULATIVE_ARGS zero_cumulative; | |
2120 | ||
2121 | *cum = zero_cumulative; | |
2122 | cum->words = 0; | |
2123 | cum->fregno = FP_ARG_MIN_REG; | |
2124 | cum->prototype = (fntype && TYPE_ARG_TYPES (fntype)); | |
7509c759 | 2125 | cum->call_cookie = CALL_NORMAL; |
4cc833b7 | 2126 | cum->sysv_gregno = GP_ARG_MIN_REG; |
4697a36c MM |
2127 | |
2128 | if (incoming) | |
bd227acc | 2129 | cum->nargs_prototype = 1000; /* don't return a PARALLEL */ |
4697a36c MM |
2130 | |
2131 | else if (cum->prototype) | |
2132 | cum->nargs_prototype = (list_length (TYPE_ARG_TYPES (fntype)) - 1 | |
2133 | + (TYPE_MODE (TREE_TYPE (fntype)) == BLKmode | |
2134 | || RETURN_IN_MEMORY (TREE_TYPE (fntype)))); | |
2135 | ||
2136 | else | |
2137 | cum->nargs_prototype = 0; | |
2138 | ||
2139 | cum->orig_nargs = cum->nargs_prototype; | |
7509c759 | 2140 | |
9ebbca7d GK |
2141 | /* Check for longcall's */ |
2142 | if (fntype && lookup_attribute ("longcall", TYPE_ATTRIBUTES (fntype))) | |
6a4cee5f MM |
2143 | cum->call_cookie = CALL_LONG; |
2144 | ||
4697a36c MM |
2145 | if (TARGET_DEBUG_ARG) |
2146 | { | |
2147 | fprintf (stderr, "\ninit_cumulative_args:"); | |
2148 | if (fntype) | |
2149 | { | |
2150 | tree ret_type = TREE_TYPE (fntype); | |
2151 | fprintf (stderr, " ret code = %s,", | |
2152 | tree_code_name[ (int)TREE_CODE (ret_type) ]); | |
2153 | } | |
2154 | ||
6a4cee5f MM |
2155 | if (cum->call_cookie & CALL_LONG) |
2156 | fprintf (stderr, " longcall,"); | |
2157 | ||
4697a36c MM |
2158 | fprintf (stderr, " proto = %d, nargs = %d\n", |
2159 | cum->prototype, cum->nargs_prototype); | |
2160 | } | |
2161 | } | |
2162 | \f | |
c229cba9 DE |
2163 | /* If defined, a C expression which determines whether, and in which |
2164 | direction, to pad out an argument with extra space. The value | |
2165 | should be of type `enum direction': either `upward' to pad above | |
2166 | the argument, `downward' to pad below, or `none' to inhibit | |
2167 | padding. | |
2168 | ||
2169 | For the AIX ABI structs are always stored left shifted in their | |
2170 | argument slot. */ | |
2171 | ||
9ebbca7d | 2172 | enum direction |
c229cba9 DE |
2173 | function_arg_padding (mode, type) |
2174 | enum machine_mode mode; | |
2175 | tree type; | |
2176 | { | |
c85f7c16 | 2177 | if (type != 0 && AGGREGATE_TYPE_P (type)) |
9ebbca7d | 2178 | return upward; |
c229cba9 DE |
2179 | |
2180 | /* This is the default definition. */ | |
2181 | return (! BYTES_BIG_ENDIAN | |
9ebbca7d | 2182 | ? upward |
c229cba9 DE |
2183 | : ((mode == BLKmode |
2184 | ? (type && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST | |
2185 | && int_size_in_bytes (type) < (PARM_BOUNDARY / BITS_PER_UNIT)) | |
2186 | : GET_MODE_BITSIZE (mode) < PARM_BOUNDARY) | |
9ebbca7d | 2187 | ? downward : upward)); |
c229cba9 DE |
2188 | } |
2189 | ||
b6c9286a MM |
2190 | /* If defined, a C expression that gives the alignment boundary, in bits, |
2191 | of an argument with the specified mode and type. If it is not defined, | |
2192 | PARM_BOUNDARY is used for all arguments. | |
2193 | ||
2310f99a | 2194 | V.4 wants long longs to be double word aligned. */ |
b6c9286a MM |
2195 | |
2196 | int | |
2197 | function_arg_boundary (mode, type) | |
2198 | enum machine_mode mode; | |
9ebbca7d | 2199 | tree type ATTRIBUTE_UNUSED; |
b6c9286a | 2200 | { |
4cc833b7 RH |
2201 | if ((DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) |
2202 | && (mode == DImode || mode == DFmode)) | |
e1f83b4d | 2203 | return 64; |
9ebbca7d | 2204 | else |
b6c9286a | 2205 | return PARM_BOUNDARY; |
b6c9286a MM |
2206 | } |
2207 | \f | |
4697a36c MM |
2208 | /* Update the data in CUM to advance over an argument |
2209 | of mode MODE and data type TYPE. | |
2210 | (TYPE is null for libcalls where that information may not be available.) */ | |
2211 | ||
2212 | void | |
2213 | function_arg_advance (cum, mode, type, named) | |
2214 | CUMULATIVE_ARGS *cum; | |
2215 | enum machine_mode mode; | |
2216 | tree type; | |
2217 | int named; | |
2218 | { | |
2219 | cum->nargs_prototype--; | |
2220 | ||
c81bebd7 | 2221 | if (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) |
4697a36c | 2222 | { |
4cc833b7 RH |
2223 | if (TARGET_HARD_FLOAT |
2224 | && (mode == SFmode || mode == DFmode)) | |
4697a36c | 2225 | { |
4cc833b7 RH |
2226 | if (cum->fregno <= FP_ARG_V4_MAX_REG) |
2227 | cum->fregno++; | |
2228 | else | |
2229 | { | |
2230 | if (mode == DFmode) | |
2231 | cum->words += cum->words & 1; | |
d34c5b80 | 2232 | cum->words += RS6000_ARG_SIZE (mode, type); |
4cc833b7 | 2233 | } |
4697a36c | 2234 | } |
4cc833b7 RH |
2235 | else |
2236 | { | |
2237 | int n_words; | |
2238 | int gregno = cum->sysv_gregno; | |
2239 | ||
2240 | /* Aggregates and IEEE quad get passed by reference. */ | |
2241 | if ((type && AGGREGATE_TYPE_P (type)) | |
2242 | || mode == TFmode) | |
2243 | n_words = 1; | |
2244 | else | |
d34c5b80 | 2245 | n_words = RS6000_ARG_SIZE (mode, type); |
4cc833b7 RH |
2246 | |
2247 | /* Long long is put in odd registers. */ | |
2248 | if (n_words == 2 && (gregno & 1) == 0) | |
2249 | gregno += 1; | |
2250 | ||
2251 | /* Long long is not split between registers and stack. */ | |
2252 | if (gregno + n_words - 1 > GP_ARG_MAX_REG) | |
2253 | { | |
2254 | /* Long long is aligned on the stack. */ | |
2255 | if (n_words == 2) | |
2256 | cum->words += cum->words & 1; | |
2257 | cum->words += n_words; | |
2258 | } | |
4697a36c | 2259 | |
4cc833b7 RH |
2260 | /* Note: continuing to accumulate gregno past when we've started |
2261 | spilling to the stack indicates the fact that we've started | |
2262 | spilling to the stack to expand_builtin_saveregs. */ | |
2263 | cum->sysv_gregno = gregno + n_words; | |
2264 | } | |
4697a36c | 2265 | |
4cc833b7 RH |
2266 | if (TARGET_DEBUG_ARG) |
2267 | { | |
2268 | fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ", | |
2269 | cum->words, cum->fregno); | |
2270 | fprintf (stderr, "gregno = %2d, nargs = %4d, proto = %d, ", | |
2271 | cum->sysv_gregno, cum->nargs_prototype, cum->prototype); | |
2272 | fprintf (stderr, "mode = %4s, named = %d\n", | |
2273 | GET_MODE_NAME (mode), named); | |
2274 | } | |
4697a36c MM |
2275 | } |
2276 | else | |
4cc833b7 RH |
2277 | { |
2278 | int align = (TARGET_32BIT && (cum->words & 1) != 0 | |
2279 | && function_arg_boundary (mode, type) == 64) ? 1 : 0; | |
d34c5b80 | 2280 | cum->words += align + RS6000_ARG_SIZE (mode, type); |
4697a36c | 2281 | |
d34c5b80 DE |
2282 | if (GET_MODE_CLASS (mode) == MODE_FLOAT && TARGET_HARD_FLOAT) |
2283 | cum->fregno++; | |
4cc833b7 RH |
2284 | |
2285 | if (TARGET_DEBUG_ARG) | |
2286 | { | |
2287 | fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ", | |
2288 | cum->words, cum->fregno); | |
2289 | fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s, ", | |
2290 | cum->nargs_prototype, cum->prototype, GET_MODE_NAME (mode)); | |
2291 | fprintf (stderr, "named = %d, align = %d\n", named, align); | |
2292 | } | |
2293 | } | |
4697a36c MM |
2294 | } |
2295 | \f | |
2296 | /* Determine where to put an argument to a function. | |
2297 | Value is zero to push the argument on the stack, | |
2298 | or a hard register in which to store the argument. | |
2299 | ||
2300 | MODE is the argument's machine mode. | |
2301 | TYPE is the data type of the argument (as a tree). | |
2302 | This is null for libcalls where that information may | |
2303 | not be available. | |
2304 | CUM is a variable of type CUMULATIVE_ARGS which gives info about | |
2305 | the preceding args and about the function being called. | |
2306 | NAMED is nonzero if this argument is a named parameter | |
2307 | (otherwise it is an extra parameter matching an ellipsis). | |
2308 | ||
2309 | On RS/6000 the first eight words of non-FP are normally in registers | |
2310 | and the rest are pushed. Under AIX, the first 13 FP args are in registers. | |
2311 | Under V.4, the first 8 FP args are in registers. | |
2312 | ||
2313 | If this is floating-point and no prototype is specified, we use | |
2314 | both an FP and integer register (or possibly FP reg and stack). Library | |
2315 | functions (when TYPE is zero) always have the proper types for args, | |
2316 | so we can pass the FP value just in one register. emit_library_function | |
1c20ae99 | 2317 | doesn't support PARALLEL anyway. */ |
4697a36c MM |
2318 | |
2319 | struct rtx_def * | |
2320 | function_arg (cum, mode, type, named) | |
2321 | CUMULATIVE_ARGS *cum; | |
2322 | enum machine_mode mode; | |
2323 | tree type; | |
d34c5b80 | 2324 | int named ATTRIBUTE_UNUSED; |
4697a36c | 2325 | { |
4cc833b7 | 2326 | enum rs6000_abi abi = DEFAULT_ABI; |
4697a36c | 2327 | |
4cc833b7 RH |
2328 | /* Return a marker to indicate whether CR1 needs to set or clear the bit |
2329 | that V.4 uses to say fp args were passed in registers. Assume that we | |
2330 | don't need the marker for software floating point, or compiler generated | |
2331 | library calls. */ | |
4697a36c MM |
2332 | if (mode == VOIDmode) |
2333 | { | |
c81bebd7 | 2334 | if ((abi == ABI_V4 || abi == ABI_SOLARIS) |
7509c759 MM |
2335 | && TARGET_HARD_FLOAT |
2336 | && cum->nargs_prototype < 0 | |
4697a36c | 2337 | && type && (cum->prototype || TARGET_NO_PROTOTYPE)) |
7509c759 | 2338 | { |
6a4cee5f MM |
2339 | return GEN_INT (cum->call_cookie |
2340 | | ((cum->fregno == FP_ARG_MIN_REG) | |
2341 | ? CALL_V4_SET_FP_ARGS | |
2342 | : CALL_V4_CLEAR_FP_ARGS)); | |
7509c759 | 2343 | } |
4697a36c | 2344 | |
7509c759 | 2345 | return GEN_INT (cum->call_cookie); |
4697a36c MM |
2346 | } |
2347 | ||
4cc833b7 | 2348 | if (abi == ABI_V4 || abi == ABI_SOLARIS) |
4697a36c | 2349 | { |
4cc833b7 RH |
2350 | if (TARGET_HARD_FLOAT |
2351 | && (mode == SFmode || mode == DFmode)) | |
2352 | { | |
2353 | if (cum->fregno <= FP_ARG_V4_MAX_REG) | |
2354 | return gen_rtx_REG (mode, cum->fregno); | |
2355 | else | |
2356 | return NULL; | |
2357 | } | |
2358 | else | |
2359 | { | |
2360 | int n_words; | |
2361 | int gregno = cum->sysv_gregno; | |
2362 | ||
2363 | /* Aggregates and IEEE quad get passed by reference. */ | |
2364 | if ((type && AGGREGATE_TYPE_P (type)) | |
2365 | || mode == TFmode) | |
2366 | n_words = 1; | |
2367 | else | |
d34c5b80 | 2368 | n_words = RS6000_ARG_SIZE (mode, type); |
4cc833b7 RH |
2369 | |
2370 | /* Long long is put in odd registers. */ | |
2371 | if (n_words == 2 && (gregno & 1) == 0) | |
2372 | gregno += 1; | |
2373 | ||
2374 | /* Long long is not split between registers and stack. */ | |
2375 | if (gregno + n_words - 1 <= GP_ARG_MAX_REG) | |
2376 | return gen_rtx_REG (mode, gregno); | |
2377 | else | |
2378 | return NULL; | |
2379 | } | |
4697a36c | 2380 | } |
4cc833b7 RH |
2381 | else |
2382 | { | |
2383 | int align = (TARGET_32BIT && (cum->words & 1) != 0 | |
2384 | && function_arg_boundary (mode, type) == 64) ? 1 : 0; | |
2385 | int align_words = cum->words + align; | |
4697a36c | 2386 | |
4cc833b7 RH |
2387 | if (type && TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST) |
2388 | return NULL_RTX; | |
2389 | ||
2390 | if (USE_FP_FOR_ARG_P (*cum, mode, type)) | |
2391 | { | |
2392 | if (! type | |
2393 | || ((cum->nargs_prototype > 0) | |
2394 | /* IBM AIX extended its linkage convention definition always | |
2395 | to require FP args after register save area hole on the | |
2396 | stack. */ | |
2397 | && (DEFAULT_ABI != ABI_AIX | |
2398 | || ! TARGET_XL_CALL | |
2399 | || (align_words < GP_ARG_NUM_REG)))) | |
2400 | return gen_rtx_REG (mode, cum->fregno); | |
2401 | ||
2402 | return gen_rtx_PARALLEL (mode, | |
2403 | gen_rtvec (2, | |
39403d82 | 2404 | gen_rtx_EXPR_LIST (VOIDmode, |
1c20ae99 JW |
2405 | ((align_words >= GP_ARG_NUM_REG) |
2406 | ? NULL_RTX | |
2407 | : (align_words | |
d34c5b80 | 2408 | + RS6000_ARG_SIZE (mode, type) |
1c20ae99 JW |
2409 | > GP_ARG_NUM_REG |
2410 | /* If this is partially on the stack, then | |
2411 | we only include the portion actually | |
2412 | in registers here. */ | |
39403d82 | 2413 | ? gen_rtx_REG (SImode, |
1c20ae99 | 2414 | GP_ARG_MIN_REG + align_words) |
39403d82 | 2415 | : gen_rtx_REG (mode, |
1c20ae99 JW |
2416 | GP_ARG_MIN_REG + align_words))), |
2417 | const0_rtx), | |
39403d82 DE |
2418 | gen_rtx_EXPR_LIST (VOIDmode, |
2419 | gen_rtx_REG (mode, cum->fregno), | |
1c20ae99 | 2420 | const0_rtx))); |
4cc833b7 RH |
2421 | } |
2422 | else if (align_words < GP_ARG_NUM_REG) | |
2423 | return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words); | |
2424 | else | |
2425 | return NULL_RTX; | |
4697a36c | 2426 | } |
4697a36c MM |
2427 | } |
2428 | \f | |
2429 | /* For an arg passed partly in registers and partly in memory, | |
2430 | this is the number of registers used. | |
2431 | For args passed entirely in registers or entirely in memory, zero. */ | |
2432 | ||
2433 | int | |
2434 | function_arg_partial_nregs (cum, mode, type, named) | |
2435 | CUMULATIVE_ARGS *cum; | |
2436 | enum machine_mode mode; | |
2437 | tree type; | |
d34c5b80 | 2438 | int named ATTRIBUTE_UNUSED; |
4697a36c | 2439 | { |
c81bebd7 | 2440 | if (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) |
4697a36c | 2441 | return 0; |
4697a36c MM |
2442 | |
2443 | if (USE_FP_FOR_ARG_P (*cum, mode, type)) | |
2444 | { | |
2445 | if (cum->nargs_prototype >= 0) | |
2446 | return 0; | |
2447 | } | |
2448 | ||
2449 | if (cum->words < GP_ARG_NUM_REG | |
d34c5b80 | 2450 | && GP_ARG_NUM_REG < (cum->words + RS6000_ARG_SIZE (mode, type))) |
4697a36c MM |
2451 | { |
2452 | int ret = GP_ARG_NUM_REG - cum->words; | |
2453 | if (ret && TARGET_DEBUG_ARG) | |
2454 | fprintf (stderr, "function_arg_partial_nregs: %d\n", ret); | |
2455 | ||
2456 | return ret; | |
2457 | } | |
2458 | ||
2459 | return 0; | |
2460 | } | |
2461 | \f | |
2462 | /* A C expression that indicates when an argument must be passed by | |
2463 | reference. If nonzero for an argument, a copy of that argument is | |
2464 | made in memory and a pointer to the argument is passed instead of | |
2465 | the argument itself. The pointer is passed in whatever way is | |
2466 | appropriate for passing a pointer to that type. | |
2467 | ||
2468 | Under V.4, structures and unions are passed by reference. */ | |
2469 | ||
2470 | int | |
2471 | function_arg_pass_by_reference (cum, mode, type, named) | |
296b8152 KG |
2472 | CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED; |
2473 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
4697a36c | 2474 | tree type; |
296b8152 | 2475 | int named ATTRIBUTE_UNUSED; |
4697a36c | 2476 | { |
c81bebd7 | 2477 | if ((DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) |
4cc833b7 RH |
2478 | && ((type && AGGREGATE_TYPE_P (type)) |
2479 | || mode == TFmode)) | |
4697a36c MM |
2480 | { |
2481 | if (TARGET_DEBUG_ARG) | |
2482 | fprintf (stderr, "function_arg_pass_by_reference: aggregate\n"); | |
2483 | ||
2484 | return 1; | |
2485 | } | |
4697a36c MM |
2486 | |
2487 | return 0; | |
2488 | } | |
4697a36c MM |
2489 | \f |
2490 | /* Perform any needed actions needed for a function that is receiving a | |
2491 | variable number of arguments. | |
2492 | ||
2493 | CUM is as above. | |
2494 | ||
2495 | MODE and TYPE are the mode and type of the current parameter. | |
2496 | ||
2497 | PRETEND_SIZE is a variable that should be set to the amount of stack | |
2498 | that must be pushed by the prolog to pretend that our caller pushed | |
2499 | it. | |
2500 | ||
2501 | Normally, this macro will push all remaining incoming registers on the | |
2502 | stack and set PRETEND_SIZE to the length of the registers pushed. */ | |
2503 | ||
2504 | void | |
2505 | setup_incoming_varargs (cum, mode, type, pretend_size, no_rtl) | |
2506 | CUMULATIVE_ARGS *cum; | |
2507 | enum machine_mode mode; | |
2508 | tree type; | |
2509 | int *pretend_size; | |
2510 | int no_rtl; | |
2511 | ||
2512 | { | |
4cc833b7 RH |
2513 | CUMULATIVE_ARGS next_cum; |
2514 | int reg_size = TARGET_32BIT ? 4 : 8; | |
ca5adc63 | 2515 | rtx save_area = NULL_RTX, mem; |
dfafc897 | 2516 | int first_reg_offset, set; |
d34c5b80 DE |
2517 | tree fntype; |
2518 | int stdarg_p; | |
4697a36c | 2519 | |
d34c5b80 DE |
2520 | fntype = TREE_TYPE (current_function_decl); |
2521 | stdarg_p = (TYPE_ARG_TYPES (fntype) != 0 | |
2522 | && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype))) | |
2523 | != void_type_node)); | |
4cc833b7 | 2524 | |
d34c5b80 DE |
2525 | /* For varargs, we do not want to skip the dummy va_dcl argument. |
2526 | For stdargs, we do want to skip the last named argument. */ | |
2527 | next_cum = *cum; | |
2528 | if (stdarg_p) | |
2529 | function_arg_advance (&next_cum, mode, type, 1); | |
4cc833b7 | 2530 | |
d34c5b80 DE |
2531 | if (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) |
2532 | { | |
4cc833b7 RH |
2533 | /* Indicate to allocate space on the stack for varargs save area. */ |
2534 | /* ??? Does this really have to be located at a magic spot on the | |
2535 | stack, or can we allocate this with assign_stack_local instead. */ | |
00dba523 | 2536 | cfun->machine->sysv_varargs_p = 1; |
60e2d0ca | 2537 | if (! no_rtl) |
2c4974b7 | 2538 | save_area = plus_constant (virtual_stack_vars_rtx, |
bd227acc | 2539 | - RS6000_VARARGS_SIZE); |
4cc833b7 RH |
2540 | |
2541 | first_reg_offset = next_cum.sysv_gregno - GP_ARG_MIN_REG; | |
4697a36c | 2542 | } |
60e2d0ca | 2543 | else |
4697a36c | 2544 | { |
d34c5b80 | 2545 | first_reg_offset = next_cum.words; |
4cc833b7 | 2546 | save_area = virtual_incoming_args_rtx; |
00dba523 | 2547 | cfun->machine->sysv_varargs_p = 0; |
4697a36c MM |
2548 | |
2549 | if (MUST_PASS_IN_STACK (mode, type)) | |
d34c5b80 | 2550 | first_reg_offset += RS6000_ARG_SIZE (TYPE_MODE (type), type); |
4cc833b7 | 2551 | } |
4697a36c | 2552 | |
dfafc897 | 2553 | set = get_varargs_alias_set (); |
c81fc13e | 2554 | if (! no_rtl && first_reg_offset < GP_ARG_NUM_REG) |
4cc833b7 | 2555 | { |
dfafc897 FS |
2556 | mem = gen_rtx_MEM (BLKmode, |
2557 | plus_constant (save_area, | |
2558 | first_reg_offset * reg_size)), | |
ba4828e0 | 2559 | set_mem_alias_set (mem, set); |
dfafc897 | 2560 | |
4cc833b7 | 2561 | move_block_from_reg |
dfafc897 | 2562 | (GP_ARG_MIN_REG + first_reg_offset, mem, |
4cc833b7 RH |
2563 | GP_ARG_NUM_REG - first_reg_offset, |
2564 | (GP_ARG_NUM_REG - first_reg_offset) * UNITS_PER_WORD); | |
2565 | ||
2566 | /* ??? Does ABI_V4 need this at all? */ | |
4697a36c MM |
2567 | *pretend_size = (GP_ARG_NUM_REG - first_reg_offset) * UNITS_PER_WORD; |
2568 | } | |
2569 | ||
4697a36c | 2570 | /* Save FP registers if needed. */ |
4cc833b7 | 2571 | if ((DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) |
c81fc13e | 2572 | && TARGET_HARD_FLOAT && ! no_rtl |
4cc833b7 | 2573 | && next_cum.fregno <= FP_ARG_V4_MAX_REG) |
4697a36c | 2574 | { |
4cc833b7 | 2575 | int fregno = next_cum.fregno; |
9ebbca7d | 2576 | rtx cr1 = gen_rtx_REG (CCmode, CR1_REGNO); |
4cc833b7 RH |
2577 | rtx lab = gen_label_rtx (); |
2578 | int off = (GP_ARG_NUM_REG * reg_size) + ((fregno - FP_ARG_MIN_REG) * 8); | |
4697a36c | 2579 | |
4cc833b7 | 2580 | emit_jump_insn (gen_rtx_SET (VOIDmode, |
4697a36c | 2581 | pc_rtx, |
39403d82 | 2582 | gen_rtx_IF_THEN_ELSE (VOIDmode, |
4cc833b7 RH |
2583 | gen_rtx_NE (VOIDmode, cr1, |
2584 | const0_rtx), | |
39403d82 | 2585 | gen_rtx_LABEL_REF (VOIDmode, lab), |
4697a36c MM |
2586 | pc_rtx))); |
2587 | ||
4cc833b7 RH |
2588 | while (fregno <= FP_ARG_V4_MAX_REG) |
2589 | { | |
dfafc897 | 2590 | mem = gen_rtx_MEM (DFmode, plus_constant (save_area, off)); |
ba4828e0 | 2591 | set_mem_alias_set (mem, set); |
dfafc897 | 2592 | emit_move_insn (mem, gen_rtx_REG (DFmode, fregno)); |
4cc833b7 RH |
2593 | fregno++; |
2594 | off += 8; | |
4697a36c | 2595 | } |
4cc833b7 RH |
2596 | |
2597 | emit_label (lab); | |
4697a36c | 2598 | } |
4697a36c | 2599 | } |
4697a36c | 2600 | |
dfafc897 | 2601 | /* Create the va_list data type. */ |
2c4974b7 | 2602 | |
dfafc897 FS |
2603 | tree |
2604 | rs6000_build_va_list () | |
2605 | { | |
bab45a51 | 2606 | tree f_gpr, f_fpr, f_ovf, f_sav, record, type_decl; |
4697a36c | 2607 | |
9ebbca7d GK |
2608 | /* For AIX, prefer 'char *' because that's what the system |
2609 | header files like. */ | |
dfafc897 | 2610 | if (DEFAULT_ABI != ABI_V4 && DEFAULT_ABI != ABI_SOLARIS) |
9ebbca7d | 2611 | return build_pointer_type (char_type_node); |
dfafc897 | 2612 | |
0f4fd75d | 2613 | record = make_lang_type (RECORD_TYPE); |
bab45a51 | 2614 | type_decl = build_decl (TYPE_DECL, get_identifier ("__va_list_tag"), record); |
0f4fd75d | 2615 | |
9ebbca7d GK |
2616 | f_gpr = build_decl (FIELD_DECL, get_identifier ("gpr"), |
2617 | unsigned_char_type_node); | |
2618 | f_fpr = build_decl (FIELD_DECL, get_identifier ("fpr"), | |
2619 | unsigned_char_type_node); | |
dfafc897 FS |
2620 | f_ovf = build_decl (FIELD_DECL, get_identifier ("overflow_arg_area"), |
2621 | ptr_type_node); | |
2622 | f_sav = build_decl (FIELD_DECL, get_identifier ("reg_save_area"), | |
2623 | ptr_type_node); | |
2624 | ||
2625 | DECL_FIELD_CONTEXT (f_gpr) = record; | |
2626 | DECL_FIELD_CONTEXT (f_fpr) = record; | |
2627 | DECL_FIELD_CONTEXT (f_ovf) = record; | |
2628 | DECL_FIELD_CONTEXT (f_sav) = record; | |
2629 | ||
bab45a51 FS |
2630 | TREE_CHAIN (record) = type_decl; |
2631 | TYPE_NAME (record) = type_decl; | |
dfafc897 FS |
2632 | TYPE_FIELDS (record) = f_gpr; |
2633 | TREE_CHAIN (f_gpr) = f_fpr; | |
2634 | TREE_CHAIN (f_fpr) = f_ovf; | |
2635 | TREE_CHAIN (f_ovf) = f_sav; | |
2636 | ||
2637 | layout_type (record); | |
2638 | ||
2639 | /* The correct type is an array type of one element. */ | |
2640 | return build_array_type (record, build_index_type (size_zero_node)); | |
2641 | } | |
2642 | ||
2643 | /* Implement va_start. */ | |
2644 | ||
2645 | void | |
2646 | rs6000_va_start (stdarg_p, valist, nextarg) | |
2647 | int stdarg_p; | |
2648 | tree valist; | |
2649 | rtx nextarg; | |
4697a36c | 2650 | { |
dfafc897 FS |
2651 | HOST_WIDE_INT words, n_gpr, n_fpr; |
2652 | tree f_gpr, f_fpr, f_ovf, f_sav; | |
2653 | tree gpr, fpr, ovf, sav, t; | |
2c4974b7 | 2654 | |
dfafc897 | 2655 | /* Only SVR4 needs something special. */ |
2c4974b7 | 2656 | if (DEFAULT_ABI != ABI_V4 && DEFAULT_ABI != ABI_SOLARIS) |
dfafc897 FS |
2657 | { |
2658 | std_expand_builtin_va_start (stdarg_p, valist, nextarg); | |
2659 | return; | |
2660 | } | |
2661 | ||
973a648b | 2662 | f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node)); |
dfafc897 FS |
2663 | f_fpr = TREE_CHAIN (f_gpr); |
2664 | f_ovf = TREE_CHAIN (f_fpr); | |
2665 | f_sav = TREE_CHAIN (f_ovf); | |
2666 | ||
8ebecc3b | 2667 | valist = build1 (INDIRECT_REF, TREE_TYPE (TREE_TYPE (valist)), valist); |
dfafc897 FS |
2668 | gpr = build (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr); |
2669 | fpr = build (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr); | |
2670 | ovf = build (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf); | |
2671 | sav = build (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav); | |
2672 | ||
2673 | /* Count number of gp and fp argument registers used. */ | |
4cc833b7 | 2674 | words = current_function_args_info.words; |
dfafc897 FS |
2675 | n_gpr = current_function_args_info.sysv_gregno - GP_ARG_MIN_REG; |
2676 | n_fpr = current_function_args_info.fregno - FP_ARG_MIN_REG; | |
2677 | ||
2678 | if (TARGET_DEBUG_ARG) | |
78e1b90d DE |
2679 | { |
2680 | fputs ("va_start: words = ", stderr); | |
2681 | fprintf (stderr, HOST_WIDE_INT_PRINT_DEC, words); | |
2682 | fputs (", n_gpr = ", stderr); | |
2683 | fprintf (stderr, HOST_WIDE_INT_PRINT_DEC, n_gpr); | |
2684 | fputs (", n_fpr = ", stderr); | |
2685 | fprintf (stderr, HOST_WIDE_INT_PRINT_DEC, n_fpr); | |
2686 | putc ('\n', stderr); | |
2687 | } | |
dfafc897 FS |
2688 | |
2689 | t = build (MODIFY_EXPR, TREE_TYPE (gpr), gpr, build_int_2 (n_gpr, 0)); | |
2690 | TREE_SIDE_EFFECTS (t) = 1; | |
2691 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
2692 | ||
2693 | t = build (MODIFY_EXPR, TREE_TYPE (fpr), fpr, build_int_2 (n_fpr, 0)); | |
2694 | TREE_SIDE_EFFECTS (t) = 1; | |
2695 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
2696 | ||
2697 | /* Find the overflow area. */ | |
2698 | t = make_tree (TREE_TYPE (ovf), virtual_incoming_args_rtx); | |
2699 | if (words != 0) | |
2700 | t = build (PLUS_EXPR, TREE_TYPE (ovf), t, | |
2701 | build_int_2 (words * UNITS_PER_WORD, 0)); | |
2702 | t = build (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t); | |
2703 | TREE_SIDE_EFFECTS (t) = 1; | |
2704 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
2705 | ||
2706 | /* Find the register save area. */ | |
2707 | t = make_tree (TREE_TYPE (sav), virtual_stack_vars_rtx); | |
2708 | t = build (PLUS_EXPR, TREE_TYPE (sav), t, | |
2709 | build_int_2 (-RS6000_VARARGS_SIZE, -1)); | |
2710 | t = build (MODIFY_EXPR, TREE_TYPE (sav), sav, t); | |
2711 | TREE_SIDE_EFFECTS (t) = 1; | |
2712 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
2713 | } | |
2714 | ||
2715 | /* Implement va_arg. */ | |
2716 | ||
2717 | rtx | |
2718 | rs6000_va_arg (valist, type) | |
2719 | tree valist, type; | |
2720 | { | |
2721 | tree f_gpr, f_fpr, f_ovf, f_sav; | |
2722 | tree gpr, fpr, ovf, sav, reg, t, u; | |
2723 | int indirect_p, size, rsize, n_reg, sav_ofs, sav_scale; | |
2724 | rtx lab_false, lab_over, addr_rtx, r; | |
2725 | ||
9ebbca7d GK |
2726 | /* For AIX, the rule is that structures are passed left-aligned in |
2727 | their stack slot. However, GCC does not presently do this: | |
2728 | structures which are the same size as integer types are passed | |
2729 | right-aligned, as if they were in fact integers. This only | |
2730 | matters for structures of size 1 or 2, or 4 when TARGET_64BIT. */ | |
dfafc897 | 2731 | if (DEFAULT_ABI != ABI_V4 && DEFAULT_ABI != ABI_SOLARIS) |
9ebbca7d GK |
2732 | { |
2733 | HOST_WIDE_INT align, rounded_size; | |
2734 | enum machine_mode mode; | |
2735 | tree addr_tree; | |
2736 | ||
2737 | /* Compute the rounded size of the type. */ | |
2738 | align = PARM_BOUNDARY / BITS_PER_UNIT; | |
2739 | rounded_size = (((int_size_in_bytes (type) + align - 1) / align) | |
2740 | * align); | |
2741 | ||
2742 | addr_tree = valist; | |
2743 | ||
2744 | mode = TYPE_MODE (type); | |
2745 | if (mode != BLKmode) | |
2746 | { | |
2747 | HOST_WIDE_INT adj; | |
2748 | adj = TREE_INT_CST_LOW (TYPE_SIZE (type)) / BITS_PER_UNIT; | |
2749 | if (rounded_size > align) | |
2750 | adj = rounded_size; | |
2751 | ||
2752 | addr_tree = build (PLUS_EXPR, TREE_TYPE (addr_tree), addr_tree, | |
2753 | build_int_2 (rounded_size - adj, 0)); | |
2754 | } | |
2755 | ||
2756 | addr_rtx = expand_expr (addr_tree, NULL_RTX, Pmode, EXPAND_NORMAL); | |
2757 | addr_rtx = copy_to_reg (addr_rtx); | |
2758 | ||
2759 | /* Compute new value for AP. */ | |
2760 | t = build (MODIFY_EXPR, TREE_TYPE (valist), valist, | |
2761 | build (PLUS_EXPR, TREE_TYPE (valist), valist, | |
2762 | build_int_2 (rounded_size, 0))); | |
2763 | TREE_SIDE_EFFECTS (t) = 1; | |
2764 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
2765 | ||
2766 | return addr_rtx; | |
2767 | } | |
dfafc897 | 2768 | |
973a648b | 2769 | f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node)); |
dfafc897 FS |
2770 | f_fpr = TREE_CHAIN (f_gpr); |
2771 | f_ovf = TREE_CHAIN (f_fpr); | |
2772 | f_sav = TREE_CHAIN (f_ovf); | |
2773 | ||
8ebecc3b | 2774 | valist = build1 (INDIRECT_REF, TREE_TYPE (TREE_TYPE (valist)), valist); |
dfafc897 FS |
2775 | gpr = build (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr); |
2776 | fpr = build (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr); | |
2777 | ovf = build (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf); | |
2778 | sav = build (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav); | |
2779 | ||
2780 | size = int_size_in_bytes (type); | |
2781 | rsize = (size + UNITS_PER_WORD - 1) / UNITS_PER_WORD; | |
4cc833b7 | 2782 | |
dfafc897 | 2783 | if (AGGREGATE_TYPE_P (type) || TYPE_MODE (type) == TFmode) |
4cc833b7 | 2784 | { |
dfafc897 FS |
2785 | /* Aggregates and long doubles are passed by reference. */ |
2786 | indirect_p = 1; | |
2787 | reg = gpr; | |
2788 | n_reg = 1; | |
2789 | sav_ofs = 0; | |
2790 | sav_scale = 4; | |
2791 | size = rsize = UNITS_PER_WORD; | |
2792 | } | |
2793 | else if (FLOAT_TYPE_P (type) && ! TARGET_SOFT_FLOAT) | |
2794 | { | |
2795 | /* FP args go in FP registers, if present. */ | |
2796 | indirect_p = 0; | |
2797 | reg = fpr; | |
2798 | n_reg = 1; | |
2799 | sav_ofs = 8*4; | |
2800 | sav_scale = 8; | |
4cc833b7 | 2801 | } |
dfafc897 FS |
2802 | else |
2803 | { | |
2804 | /* Otherwise into GP registers. */ | |
2805 | indirect_p = 0; | |
2806 | reg = gpr; | |
2807 | n_reg = rsize; | |
2808 | sav_ofs = 0; | |
2809 | sav_scale = 4; | |
2810 | } | |
2811 | ||
2812 | /* | |
2813 | * Pull the value out of the saved registers ... | |
2814 | */ | |
2815 | ||
2816 | lab_false = gen_label_rtx (); | |
2817 | lab_over = gen_label_rtx (); | |
2818 | addr_rtx = gen_reg_rtx (Pmode); | |
2819 | ||
2820 | emit_cmp_and_jump_insns (expand_expr (reg, NULL_RTX, QImode, EXPAND_NORMAL), | |
2821 | GEN_INT (8 - n_reg + 1), | |
2822 | GE, const1_rtx, QImode, 1, 1, lab_false); | |
2c4974b7 | 2823 | |
dfafc897 FS |
2824 | /* Long long is aligned in the registers. */ |
2825 | if (n_reg > 1) | |
2c4974b7 | 2826 | { |
dfafc897 FS |
2827 | u = build (BIT_AND_EXPR, TREE_TYPE (reg), reg, |
2828 | build_int_2 (n_reg - 1, 0)); | |
2829 | u = build (PLUS_EXPR, TREE_TYPE (reg), reg, u); | |
2830 | u = build (MODIFY_EXPR, TREE_TYPE (reg), reg, u); | |
2831 | TREE_SIDE_EFFECTS (u) = 1; | |
2832 | expand_expr (u, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
2c4974b7 | 2833 | } |
dfafc897 FS |
2834 | |
2835 | if (sav_ofs) | |
2836 | t = build (PLUS_EXPR, ptr_type_node, sav, build_int_2 (sav_ofs, 0)); | |
2c4974b7 | 2837 | else |
dfafc897 | 2838 | t = sav; |
2c4974b7 | 2839 | |
dfafc897 FS |
2840 | u = build (POSTINCREMENT_EXPR, TREE_TYPE (reg), reg, build_int_2 (n_reg, 0)); |
2841 | TREE_SIDE_EFFECTS (u) = 1; | |
2c4974b7 | 2842 | |
dfafc897 FS |
2843 | u = build1 (CONVERT_EXPR, integer_type_node, u); |
2844 | TREE_SIDE_EFFECTS (u) = 1; | |
2c4974b7 | 2845 | |
dfafc897 FS |
2846 | u = build (MULT_EXPR, integer_type_node, u, build_int_2 (sav_scale, 0)); |
2847 | TREE_SIDE_EFFECTS (u) = 1; | |
2848 | ||
2849 | t = build (PLUS_EXPR, ptr_type_node, t, u); | |
2850 | TREE_SIDE_EFFECTS (t) = 1; | |
2851 | ||
2852 | r = expand_expr (t, addr_rtx, Pmode, EXPAND_NORMAL); | |
2853 | if (r != addr_rtx) | |
2854 | emit_move_insn (addr_rtx, r); | |
2855 | ||
2856 | emit_jump_insn (gen_jump (lab_over)); | |
2857 | emit_barrier (); | |
2858 | emit_label (lab_false); | |
2859 | ||
2860 | /* | |
2861 | * ... otherwise out of the overflow area. | |
2862 | */ | |
2863 | ||
2864 | /* Make sure we don't find reg 7 for the next int arg. */ | |
2865 | if (n_reg > 1) | |
2866 | { | |
2867 | t = build (MODIFY_EXPR, TREE_TYPE (reg), reg, build_int_2 (8, 0)); | |
2868 | TREE_SIDE_EFFECTS (t) = 1; | |
2869 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
2870 | } | |
2871 | ||
2872 | /* Care for on-stack alignment if needed. */ | |
2873 | if (rsize <= 1) | |
2874 | t = ovf; | |
2875 | else | |
2876 | { | |
2877 | t = build (PLUS_EXPR, TREE_TYPE (ovf), ovf, build_int_2 (7, 0)); | |
2878 | t = build (BIT_AND_EXPR, TREE_TYPE (t), t, build_int_2 (-8, -1)); | |
2879 | } | |
2880 | t = save_expr (t); | |
2881 | ||
2882 | r = expand_expr (t, addr_rtx, Pmode, EXPAND_NORMAL); | |
2883 | if (r != addr_rtx) | |
2884 | emit_move_insn (addr_rtx, r); | |
2885 | ||
2886 | t = build (PLUS_EXPR, TREE_TYPE (t), t, build_int_2 (size, 0)); | |
2887 | t = build (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t); | |
2888 | TREE_SIDE_EFFECTS (t) = 1; | |
2889 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
2890 | ||
2891 | emit_label (lab_over); | |
2892 | ||
2893 | if (indirect_p) | |
2894 | { | |
2895 | r = gen_rtx_MEM (Pmode, addr_rtx); | |
ba4828e0 | 2896 | set_mem_alias_set (r, get_varargs_alias_set ()); |
dfafc897 FS |
2897 | emit_move_insn (addr_rtx, r); |
2898 | } | |
2899 | ||
2900 | return addr_rtx; | |
4697a36c | 2901 | } |
5b5040b9 RK |
2902 | \f |
2903 | /* Generate a memory reference for expand_block_move, copying volatile, | |
2904 | and other bits from an original memory reference. */ | |
2905 | ||
2906 | static rtx | |
2907 | expand_block_move_mem (mode, addr, orig_mem) | |
2908 | enum machine_mode mode; | |
2909 | rtx addr; | |
2910 | rtx orig_mem; | |
2911 | { | |
39403d82 | 2912 | rtx mem = gen_rtx_MEM (mode, addr); |
b6c9286a | 2913 | |
c6df88cb | 2914 | MEM_COPY_ATTRIBUTES (mem, orig_mem); |
b6c9286a MM |
2915 | #ifdef MEM_UNALIGNED_P |
2916 | MEM_UNALIGNED_P (mem) = MEM_UNALIGNED_P (orig_mem); | |
2917 | #endif | |
5b5040b9 RK |
2918 | return mem; |
2919 | } | |
2920 | ||
7e69e155 MM |
2921 | /* Expand a block move operation, and return 1 if successful. Return 0 |
2922 | if we should let the compiler generate normal code. | |
2923 | ||
2924 | operands[0] is the destination | |
2925 | operands[1] is the source | |
2926 | operands[2] is the length | |
2927 | operands[3] is the alignment */ | |
2928 | ||
3933e0e1 MM |
2929 | #define MAX_MOVE_REG 4 |
2930 | ||
7e69e155 MM |
2931 | int |
2932 | expand_block_move (operands) | |
2933 | rtx operands[]; | |
2934 | { | |
b6c9286a MM |
2935 | rtx orig_dest = operands[0]; |
2936 | rtx orig_src = operands[1]; | |
7e69e155 | 2937 | rtx bytes_rtx = operands[2]; |
7e69e155 | 2938 | rtx align_rtx = operands[3]; |
3933e0e1 | 2939 | int constp = (GET_CODE (bytes_rtx) == CONST_INT); |
5ee95df6 | 2940 | int align; |
3933e0e1 MM |
2941 | int bytes; |
2942 | int offset; | |
2943 | int num_reg; | |
2944 | int i; | |
7e69e155 MM |
2945 | rtx src_reg; |
2946 | rtx dest_reg; | |
3933e0e1 MM |
2947 | rtx src_addr; |
2948 | rtx dest_addr; | |
7e69e155 | 2949 | rtx tmp_reg; |
3933e0e1 | 2950 | rtx stores[MAX_MOVE_REG]; |
7e69e155 MM |
2951 | int move_bytes; |
2952 | ||
3933e0e1 | 2953 | /* If this is not a fixed size move, just call memcpy */ |
cc0d9ba8 | 2954 | if (! constp) |
3933e0e1 MM |
2955 | return 0; |
2956 | ||
5ee95df6 FS |
2957 | /* If this is not a fixed size alignment, abort */ |
2958 | if (GET_CODE (align_rtx) != CONST_INT) | |
2959 | abort (); | |
2960 | align = INTVAL (align_rtx); | |
2961 | ||
7e69e155 | 2962 | /* Anything to move? */ |
3933e0e1 MM |
2963 | bytes = INTVAL (bytes_rtx); |
2964 | if (bytes <= 0) | |
7e69e155 MM |
2965 | return 1; |
2966 | ||
3933e0e1 MM |
2967 | /* Don't support real large moves. If string instructions are not used, |
2968 | then don't generate more than 8 loads. */ | |
2969 | if (TARGET_STRING) | |
2970 | { | |
c81fc13e | 2971 | if (bytes > 8*4) |
3933e0e1 MM |
2972 | return 0; |
2973 | } | |
cc0d9ba8 | 2974 | else if (! STRICT_ALIGNMENT) |
3933e0e1 | 2975 | { |
c81fc13e DE |
2976 | if (TARGET_POWERPC64 && align >= 4) |
2977 | { | |
2978 | if (bytes > 8*8) | |
2979 | return 0; | |
2980 | } | |
2981 | else | |
2982 | if (bytes > 8*4) | |
2983 | return 0; | |
3933e0e1 MM |
2984 | } |
2985 | else if (bytes > 8*align) | |
7e69e155 MM |
2986 | return 0; |
2987 | ||
2988 | /* Move the address into scratch registers. */ | |
b6c9286a MM |
2989 | dest_reg = copy_addr_to_reg (XEXP (orig_dest, 0)); |
2990 | src_reg = copy_addr_to_reg (XEXP (orig_src, 0)); | |
7e69e155 | 2991 | |
3933e0e1 | 2992 | if (TARGET_STRING) /* string instructions are available */ |
7e69e155 | 2993 | { |
3933e0e1 | 2994 | for ( ; bytes > 0; bytes -= move_bytes) |
7e69e155 | 2995 | { |
3933e0e1 | 2996 | if (bytes > 24 /* move up to 32 bytes at a time */ |
cc0d9ba8 DE |
2997 | && ! fixed_regs[5] |
2998 | && ! fixed_regs[6] | |
2999 | && ! fixed_regs[7] | |
3000 | && ! fixed_regs[8] | |
3001 | && ! fixed_regs[9] | |
3002 | && ! fixed_regs[10] | |
3003 | && ! fixed_regs[11] | |
3004 | && ! fixed_regs[12]) | |
3933e0e1 MM |
3005 | { |
3006 | move_bytes = (bytes > 32) ? 32 : bytes; | |
cc0d9ba8 DE |
3007 | emit_insn (gen_movstrsi_8reg (expand_block_move_mem (BLKmode, |
3008 | dest_reg, | |
3009 | orig_dest), | |
3010 | expand_block_move_mem (BLKmode, | |
3011 | src_reg, | |
3012 | orig_src), | |
3013 | GEN_INT ((move_bytes == 32) | |
3014 | ? 0 : move_bytes), | |
4c64a852 | 3015 | align_rtx)); |
3933e0e1 MM |
3016 | } |
3017 | else if (bytes > 16 /* move up to 24 bytes at a time */ | |
f9562f27 DE |
3018 | && ! fixed_regs[5] |
3019 | && ! fixed_regs[6] | |
cc0d9ba8 DE |
3020 | && ! fixed_regs[7] |
3021 | && ! fixed_regs[8] | |
3022 | && ! fixed_regs[9] | |
f9562f27 | 3023 | && ! fixed_regs[10]) |
3933e0e1 MM |
3024 | { |
3025 | move_bytes = (bytes > 24) ? 24 : bytes; | |
cc0d9ba8 DE |
3026 | emit_insn (gen_movstrsi_6reg (expand_block_move_mem (BLKmode, |
3027 | dest_reg, | |
3028 | orig_dest), | |
3029 | expand_block_move_mem (BLKmode, | |
3030 | src_reg, | |
3031 | orig_src), | |
3933e0e1 | 3032 | GEN_INT (move_bytes), |
4c64a852 | 3033 | align_rtx)); |
3933e0e1 MM |
3034 | } |
3035 | else if (bytes > 8 /* move up to 16 bytes at a time */ | |
f9562f27 DE |
3036 | && ! fixed_regs[5] |
3037 | && ! fixed_regs[6] | |
3038 | && ! fixed_regs[7] | |
3039 | && ! fixed_regs[8]) | |
3933e0e1 MM |
3040 | { |
3041 | move_bytes = (bytes > 16) ? 16 : bytes; | |
cc0d9ba8 DE |
3042 | emit_insn (gen_movstrsi_4reg (expand_block_move_mem (BLKmode, |
3043 | dest_reg, | |
3044 | orig_dest), | |
3045 | expand_block_move_mem (BLKmode, | |
3046 | src_reg, | |
3047 | orig_src), | |
3933e0e1 | 3048 | GEN_INT (move_bytes), |
4c64a852 | 3049 | align_rtx)); |
3933e0e1 | 3050 | } |
acad7ed3 DE |
3051 | else if (bytes >= 8 && TARGET_POWERPC64 |
3052 | /* 64-bit loads and stores require word-aligned displacements. */ | |
3053 | && (align >= 8 || (! STRICT_ALIGNMENT && align >= 4))) | |
3054 | { | |
3055 | move_bytes = 8; | |
3056 | tmp_reg = gen_reg_rtx (DImode); | |
3057 | emit_move_insn (tmp_reg, | |
3058 | expand_block_move_mem (DImode, | |
2eba1afa | 3059 | src_reg, orig_src)); |
acad7ed3 | 3060 | emit_move_insn (expand_block_move_mem (DImode, |
2eba1afa | 3061 | dest_reg, orig_dest), |
acad7ed3 DE |
3062 | tmp_reg); |
3063 | } | |
3064 | else if (bytes > 4) | |
3933e0e1 MM |
3065 | { /* move up to 8 bytes at a time */ |
3066 | move_bytes = (bytes > 8) ? 8 : bytes; | |
cc0d9ba8 DE |
3067 | emit_insn (gen_movstrsi_2reg (expand_block_move_mem (BLKmode, |
3068 | dest_reg, | |
3069 | orig_dest), | |
3070 | expand_block_move_mem (BLKmode, | |
3071 | src_reg, | |
3072 | orig_src), | |
3933e0e1 | 3073 | GEN_INT (move_bytes), |
4c64a852 | 3074 | align_rtx)); |
3933e0e1 | 3075 | } |
cc0d9ba8 | 3076 | else if (bytes >= 4 && (align >= 4 || ! STRICT_ALIGNMENT)) |
3933e0e1 MM |
3077 | { /* move 4 bytes */ |
3078 | move_bytes = 4; | |
3079 | tmp_reg = gen_reg_rtx (SImode); | |
cc0d9ba8 DE |
3080 | emit_move_insn (tmp_reg, |
3081 | expand_block_move_mem (SImode, | |
3082 | src_reg, orig_src)); | |
3083 | emit_move_insn (expand_block_move_mem (SImode, | |
3084 | dest_reg, orig_dest), | |
3085 | tmp_reg); | |
3933e0e1 | 3086 | } |
cc0d9ba8 | 3087 | else if (bytes == 2 && (align >= 2 || ! STRICT_ALIGNMENT)) |
3933e0e1 MM |
3088 | { /* move 2 bytes */ |
3089 | move_bytes = 2; | |
3090 | tmp_reg = gen_reg_rtx (HImode); | |
cc0d9ba8 DE |
3091 | emit_move_insn (tmp_reg, |
3092 | expand_block_move_mem (HImode, | |
3093 | src_reg, orig_src)); | |
3094 | emit_move_insn (expand_block_move_mem (HImode, | |
3095 | dest_reg, orig_dest), | |
3096 | tmp_reg); | |
3933e0e1 MM |
3097 | } |
3098 | else if (bytes == 1) /* move 1 byte */ | |
3099 | { | |
3100 | move_bytes = 1; | |
3101 | tmp_reg = gen_reg_rtx (QImode); | |
cc0d9ba8 DE |
3102 | emit_move_insn (tmp_reg, |
3103 | expand_block_move_mem (QImode, | |
3104 | src_reg, orig_src)); | |
3105 | emit_move_insn (expand_block_move_mem (QImode, | |
3106 | dest_reg, orig_dest), | |
3107 | tmp_reg); | |
3933e0e1 MM |
3108 | } |
3109 | else | |
3110 | { /* move up to 4 bytes at a time */ | |
3111 | move_bytes = (bytes > 4) ? 4 : bytes; | |
cc0d9ba8 DE |
3112 | emit_insn (gen_movstrsi_1reg (expand_block_move_mem (BLKmode, |
3113 | dest_reg, | |
3114 | orig_dest), | |
3115 | expand_block_move_mem (BLKmode, | |
3116 | src_reg, | |
3117 | orig_src), | |
3933e0e1 | 3118 | GEN_INT (move_bytes), |
4c64a852 | 3119 | align_rtx)); |
3933e0e1 | 3120 | } |
4c64a852 | 3121 | |
015892ee RK |
3122 | if (bytes > move_bytes) |
3123 | { | |
cc0d9ba8 DE |
3124 | if (! TARGET_POWERPC64) |
3125 | { | |
3126 | emit_insn (gen_addsi3 (src_reg, src_reg, | |
3127 | GEN_INT (move_bytes))); | |
3128 | emit_insn (gen_addsi3 (dest_reg, dest_reg, | |
3129 | GEN_INT (move_bytes))); | |
3130 | } | |
3131 | else | |
3132 | { | |
3133 | emit_insn (gen_adddi3 (src_reg, src_reg, | |
3134 | GEN_INT (move_bytes))); | |
3135 | emit_insn (gen_adddi3 (dest_reg, dest_reg, | |
3136 | GEN_INT (move_bytes))); | |
3137 | } | |
015892ee | 3138 | } |
4c64a852 | 3139 | } |
3933e0e1 MM |
3140 | } |
3141 | ||
3142 | else /* string instructions not available */ | |
3143 | { | |
3144 | num_reg = offset = 0; | |
3145 | for ( ; bytes > 0; (bytes -= move_bytes), (offset += move_bytes)) | |
7e69e155 | 3146 | { |
3933e0e1 MM |
3147 | /* Calculate the correct offset for src/dest */ |
3148 | if (offset == 0) | |
7e69e155 | 3149 | { |
3933e0e1 MM |
3150 | src_addr = src_reg; |
3151 | dest_addr = dest_reg; | |
3152 | } | |
3153 | else | |
3154 | { | |
c5c76735 JL |
3155 | src_addr = plus_constant (src_reg, offset); |
3156 | dest_addr = plus_constant (dest_reg, offset); | |
3933e0e1 MM |
3157 | } |
3158 | ||
cc0d9ba8 DE |
3159 | /* Generate the appropriate load and store, saving the stores |
3160 | for later. */ | |
3161 | if (bytes >= 8 && TARGET_POWERPC64 | |
3162 | /* 64-bit loads and stores require word-aligned displacements. */ | |
3163 | && (align >= 8 || (! STRICT_ALIGNMENT && align >= 4))) | |
b6c9286a MM |
3164 | { |
3165 | move_bytes = 8; | |
3166 | tmp_reg = gen_reg_rtx (DImode); | |
cc0d9ba8 DE |
3167 | emit_insn (gen_movdi (tmp_reg, |
3168 | expand_block_move_mem (DImode, | |
3169 | src_addr, | |
3170 | orig_src))); | |
3171 | stores[num_reg++] = gen_movdi (expand_block_move_mem (DImode, | |
3172 | dest_addr, | |
3173 | orig_dest), | |
3174 | tmp_reg); | |
b6c9286a | 3175 | } |
cc0d9ba8 | 3176 | else if (bytes >= 4 && (align >= 4 || ! STRICT_ALIGNMENT)) |
3933e0e1 MM |
3177 | { |
3178 | move_bytes = 4; | |
3179 | tmp_reg = gen_reg_rtx (SImode); | |
cc0d9ba8 DE |
3180 | emit_insn (gen_movsi (tmp_reg, |
3181 | expand_block_move_mem (SImode, | |
3182 | src_addr, | |
3183 | orig_src))); | |
3184 | stores[num_reg++] = gen_movsi (expand_block_move_mem (SImode, | |
3185 | dest_addr, | |
3186 | orig_dest), | |
3187 | tmp_reg); | |
3933e0e1 | 3188 | } |
cc0d9ba8 | 3189 | else if (bytes >= 2 && (align >= 2 || ! STRICT_ALIGNMENT)) |
3933e0e1 MM |
3190 | { |
3191 | move_bytes = 2; | |
3192 | tmp_reg = gen_reg_rtx (HImode); | |
c81fc13e | 3193 | emit_insn (gen_movhi (tmp_reg, |
cc0d9ba8 DE |
3194 | expand_block_move_mem (HImode, |
3195 | src_addr, | |
3196 | orig_src))); | |
3197 | stores[num_reg++] = gen_movhi (expand_block_move_mem (HImode, | |
3198 | dest_addr, | |
3199 | orig_dest), | |
3200 | tmp_reg); | |
3933e0e1 MM |
3201 | } |
3202 | else | |
3203 | { | |
3204 | move_bytes = 1; | |
3205 | tmp_reg = gen_reg_rtx (QImode); | |
c81fc13e | 3206 | emit_insn (gen_movqi (tmp_reg, |
cc0d9ba8 DE |
3207 | expand_block_move_mem (QImode, |
3208 | src_addr, | |
3209 | orig_src))); | |
3210 | stores[num_reg++] = gen_movqi (expand_block_move_mem (QImode, | |
3211 | dest_addr, | |
3212 | orig_dest), | |
3213 | tmp_reg); | |
3933e0e1 MM |
3214 | } |
3215 | ||
3216 | if (num_reg >= MAX_MOVE_REG) | |
3217 | { | |
3218 | for (i = 0; i < num_reg; i++) | |
3219 | emit_insn (stores[i]); | |
3220 | num_reg = 0; | |
7e69e155 MM |
3221 | } |
3222 | } | |
3933e0e1 | 3223 | |
b6c9286a MM |
3224 | for (i = 0; i < num_reg; i++) |
3225 | emit_insn (stores[i]); | |
7e69e155 MM |
3226 | } |
3227 | ||
3228 | return 1; | |
3229 | } | |
3230 | ||
9878760c RK |
3231 | \f |
3232 | /* Return 1 if OP is a load multiple operation. It is known to be a | |
3233 | PARALLEL and the first section will be tested. */ | |
3234 | ||
3235 | int | |
3236 | load_multiple_operation (op, mode) | |
3237 | rtx op; | |
296b8152 | 3238 | enum machine_mode mode ATTRIBUTE_UNUSED; |
9878760c RK |
3239 | { |
3240 | int count = XVECLEN (op, 0); | |
e2c953b6 | 3241 | unsigned int dest_regno; |
9878760c RK |
3242 | rtx src_addr; |
3243 | int i; | |
3244 | ||
3245 | /* Perform a quick check so we don't blow up below. */ | |
3246 | if (count <= 1 | |
3247 | || GET_CODE (XVECEXP (op, 0, 0)) != SET | |
3248 | || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG | |
3249 | || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM) | |
3250 | return 0; | |
3251 | ||
3252 | dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0))); | |
3253 | src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0); | |
3254 | ||
3255 | for (i = 1; i < count; i++) | |
3256 | { | |
3257 | rtx elt = XVECEXP (op, 0, i); | |
3258 | ||
3259 | if (GET_CODE (elt) != SET | |
3260 | || GET_CODE (SET_DEST (elt)) != REG | |
3261 | || GET_MODE (SET_DEST (elt)) != SImode | |
3262 | || REGNO (SET_DEST (elt)) != dest_regno + i | |
3263 | || GET_CODE (SET_SRC (elt)) != MEM | |
3264 | || GET_MODE (SET_SRC (elt)) != SImode | |
3265 | || GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS | |
3266 | || ! rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr) | |
3267 | || GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT | |
3268 | || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != i * 4) | |
3269 | return 0; | |
3270 | } | |
3271 | ||
3272 | return 1; | |
3273 | } | |
3274 | ||
3275 | /* Similar, but tests for store multiple. Here, the second vector element | |
3276 | is a CLOBBER. It will be tested later. */ | |
3277 | ||
3278 | int | |
3279 | store_multiple_operation (op, mode) | |
3280 | rtx op; | |
296b8152 | 3281 | enum machine_mode mode ATTRIBUTE_UNUSED; |
9878760c RK |
3282 | { |
3283 | int count = XVECLEN (op, 0) - 1; | |
e2c953b6 | 3284 | unsigned int src_regno; |
9878760c RK |
3285 | rtx dest_addr; |
3286 | int i; | |
3287 | ||
3288 | /* Perform a quick check so we don't blow up below. */ | |
3289 | if (count <= 1 | |
3290 | || GET_CODE (XVECEXP (op, 0, 0)) != SET | |
3291 | || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM | |
3292 | || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG) | |
3293 | return 0; | |
3294 | ||
3295 | src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0))); | |
3296 | dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0); | |
3297 | ||
3298 | for (i = 1; i < count; i++) | |
3299 | { | |
3300 | rtx elt = XVECEXP (op, 0, i + 1); | |
3301 | ||
3302 | if (GET_CODE (elt) != SET | |
3303 | || GET_CODE (SET_SRC (elt)) != REG | |
3304 | || GET_MODE (SET_SRC (elt)) != SImode | |
3305 | || REGNO (SET_SRC (elt)) != src_regno + i | |
3306 | || GET_CODE (SET_DEST (elt)) != MEM | |
3307 | || GET_MODE (SET_DEST (elt)) != SImode | |
3308 | || GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS | |
3309 | || ! rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr) | |
3310 | || GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT | |
3311 | || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != i * 4) | |
3312 | return 0; | |
3313 | } | |
3314 | ||
3315 | return 1; | |
3316 | } | |
9ebbca7d GK |
3317 | |
3318 | /* Return 1 for an PARALLEL suitable for mtcrf. */ | |
3319 | ||
3320 | int | |
3321 | mtcrf_operation (op, mode) | |
3322 | rtx op; | |
3323 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
3324 | { | |
3325 | int count = XVECLEN (op, 0); | |
3326 | int i; | |
9ebbca7d GK |
3327 | rtx src_reg; |
3328 | ||
3329 | /* Perform a quick check so we don't blow up below. */ | |
e35b9579 GK |
3330 | if (count < 1 |
3331 | || GET_CODE (XVECEXP (op, 0, 0)) != SET | |
3332 | || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC | |
3333 | || XVECLEN (SET_SRC (XVECEXP (op, 0, 0)), 0) != 2) | |
9ebbca7d | 3334 | return 0; |
e35b9579 | 3335 | src_reg = XVECEXP (SET_SRC (XVECEXP (op, 0, 0)), 0, 0); |
9ebbca7d GK |
3336 | |
3337 | if (GET_CODE (src_reg) != REG | |
3338 | || GET_MODE (src_reg) != SImode | |
3339 | || ! INT_REGNO_P (REGNO (src_reg))) | |
3340 | return 0; | |
3341 | ||
e35b9579 | 3342 | for (i = 0; i < count; i++) |
9ebbca7d GK |
3343 | { |
3344 | rtx exp = XVECEXP (op, 0, i); | |
3345 | rtx unspec; | |
3346 | int maskval; | |
3347 | ||
3348 | if (GET_CODE (exp) != SET | |
3349 | || GET_CODE (SET_DEST (exp)) != REG | |
3350 | || GET_MODE (SET_DEST (exp)) != CCmode | |
3351 | || ! CR_REGNO_P (REGNO (SET_DEST (exp)))) | |
3352 | return 0; | |
3353 | unspec = SET_SRC (exp); | |
3354 | maskval = 1 << (MAX_CR_REGNO - REGNO (SET_DEST (exp))); | |
9ebbca7d GK |
3355 | |
3356 | if (GET_CODE (unspec) != UNSPEC | |
3357 | || XINT (unspec, 1) != 20 | |
3358 | || XVECLEN (unspec, 0) != 2 | |
3359 | || XVECEXP (unspec, 0, 0) != src_reg | |
3360 | || GET_CODE (XVECEXP (unspec, 0, 1)) != CONST_INT | |
3361 | || INTVAL (XVECEXP (unspec, 0, 1)) != maskval) | |
3362 | return 0; | |
3363 | } | |
e35b9579 | 3364 | return 1; |
9ebbca7d GK |
3365 | } |
3366 | ||
3367 | /* Return 1 for an PARALLEL suitable for lmw. */ | |
3368 | ||
3369 | int | |
3370 | lmw_operation (op, mode) | |
3371 | rtx op; | |
3372 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
3373 | { | |
3374 | int count = XVECLEN (op, 0); | |
e2c953b6 | 3375 | unsigned int dest_regno; |
9ebbca7d | 3376 | rtx src_addr; |
e2c953b6 | 3377 | unsigned int base_regno; |
9ebbca7d GK |
3378 | HOST_WIDE_INT offset; |
3379 | int i; | |
3380 | ||
3381 | /* Perform a quick check so we don't blow up below. */ | |
3382 | if (count <= 1 | |
3383 | || GET_CODE (XVECEXP (op, 0, 0)) != SET | |
3384 | || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG | |
3385 | || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM) | |
3386 | return 0; | |
3387 | ||
3388 | dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0))); | |
3389 | src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0); | |
3390 | ||
3391 | if (dest_regno > 31 | |
e2c953b6 | 3392 | || count != 32 - (int) dest_regno) |
9ebbca7d GK |
3393 | return 0; |
3394 | ||
258bfae2 | 3395 | if (LEGITIMATE_INDIRECT_ADDRESS_P (src_addr, 0)) |
9ebbca7d GK |
3396 | { |
3397 | offset = 0; | |
3398 | base_regno = REGNO (src_addr); | |
3399 | if (base_regno == 0) | |
3400 | return 0; | |
3401 | } | |
258bfae2 | 3402 | else if (LEGITIMATE_OFFSET_ADDRESS_P (SImode, src_addr, 0)) |
9ebbca7d GK |
3403 | { |
3404 | offset = INTVAL (XEXP (src_addr, 1)); | |
3405 | base_regno = REGNO (XEXP (src_addr, 0)); | |
3406 | } | |
3407 | else | |
3408 | return 0; | |
3409 | ||
3410 | for (i = 0; i < count; i++) | |
3411 | { | |
3412 | rtx elt = XVECEXP (op, 0, i); | |
3413 | rtx newaddr; | |
3414 | rtx addr_reg; | |
3415 | HOST_WIDE_INT newoffset; | |
3416 | ||
3417 | if (GET_CODE (elt) != SET | |
3418 | || GET_CODE (SET_DEST (elt)) != REG | |
3419 | || GET_MODE (SET_DEST (elt)) != SImode | |
3420 | || REGNO (SET_DEST (elt)) != dest_regno + i | |
3421 | || GET_CODE (SET_SRC (elt)) != MEM | |
3422 | || GET_MODE (SET_SRC (elt)) != SImode) | |
3423 | return 0; | |
3424 | newaddr = XEXP (SET_SRC (elt), 0); | |
258bfae2 | 3425 | if (LEGITIMATE_INDIRECT_ADDRESS_P (newaddr, 0)) |
9ebbca7d GK |
3426 | { |
3427 | newoffset = 0; | |
3428 | addr_reg = newaddr; | |
3429 | } | |
258bfae2 | 3430 | else if (LEGITIMATE_OFFSET_ADDRESS_P (SImode, newaddr, 0)) |
9ebbca7d GK |
3431 | { |
3432 | addr_reg = XEXP (newaddr, 0); | |
3433 | newoffset = INTVAL (XEXP (newaddr, 1)); | |
3434 | } | |
3435 | else | |
3436 | return 0; | |
3437 | if (REGNO (addr_reg) != base_regno | |
3438 | || newoffset != offset + 4 * i) | |
3439 | return 0; | |
3440 | } | |
3441 | ||
3442 | return 1; | |
3443 | } | |
3444 | ||
3445 | /* Return 1 for an PARALLEL suitable for stmw. */ | |
3446 | ||
3447 | int | |
3448 | stmw_operation (op, mode) | |
3449 | rtx op; | |
3450 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
3451 | { | |
3452 | int count = XVECLEN (op, 0); | |
e2c953b6 | 3453 | unsigned int src_regno; |
9ebbca7d | 3454 | rtx dest_addr; |
e2c953b6 | 3455 | unsigned int base_regno; |
9ebbca7d GK |
3456 | HOST_WIDE_INT offset; |
3457 | int i; | |
3458 | ||
3459 | /* Perform a quick check so we don't blow up below. */ | |
3460 | if (count <= 1 | |
3461 | || GET_CODE (XVECEXP (op, 0, 0)) != SET | |
3462 | || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM | |
3463 | || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG) | |
3464 | return 0; | |
3465 | ||
3466 | src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0))); | |
3467 | dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0); | |
3468 | ||
3469 | if (src_regno > 31 | |
e2c953b6 | 3470 | || count != 32 - (int) src_regno) |
9ebbca7d GK |
3471 | return 0; |
3472 | ||
258bfae2 | 3473 | if (LEGITIMATE_INDIRECT_ADDRESS_P (dest_addr, 0)) |
9ebbca7d GK |
3474 | { |
3475 | offset = 0; | |
3476 | base_regno = REGNO (dest_addr); | |
3477 | if (base_regno == 0) | |
3478 | return 0; | |
3479 | } | |
258bfae2 | 3480 | else if (LEGITIMATE_OFFSET_ADDRESS_P (SImode, dest_addr, 0)) |
9ebbca7d GK |
3481 | { |
3482 | offset = INTVAL (XEXP (dest_addr, 1)); | |
3483 | base_regno = REGNO (XEXP (dest_addr, 0)); | |
3484 | } | |
3485 | else | |
3486 | return 0; | |
3487 | ||
3488 | for (i = 0; i < count; i++) | |
3489 | { | |
3490 | rtx elt = XVECEXP (op, 0, i); | |
3491 | rtx newaddr; | |
3492 | rtx addr_reg; | |
3493 | HOST_WIDE_INT newoffset; | |
3494 | ||
3495 | if (GET_CODE (elt) != SET | |
3496 | || GET_CODE (SET_SRC (elt)) != REG | |
3497 | || GET_MODE (SET_SRC (elt)) != SImode | |
3498 | || REGNO (SET_SRC (elt)) != src_regno + i | |
3499 | || GET_CODE (SET_DEST (elt)) != MEM | |
3500 | || GET_MODE (SET_DEST (elt)) != SImode) | |
3501 | return 0; | |
3502 | newaddr = XEXP (SET_DEST (elt), 0); | |
258bfae2 | 3503 | if (LEGITIMATE_INDIRECT_ADDRESS_P (newaddr, 0)) |
9ebbca7d GK |
3504 | { |
3505 | newoffset = 0; | |
3506 | addr_reg = newaddr; | |
3507 | } | |
258bfae2 | 3508 | else if (LEGITIMATE_OFFSET_ADDRESS_P (SImode, newaddr, 0)) |
9ebbca7d GK |
3509 | { |
3510 | addr_reg = XEXP (newaddr, 0); | |
3511 | newoffset = INTVAL (XEXP (newaddr, 1)); | |
3512 | } | |
3513 | else | |
3514 | return 0; | |
3515 | if (REGNO (addr_reg) != base_regno | |
3516 | || newoffset != offset + 4 * i) | |
3517 | return 0; | |
3518 | } | |
3519 | ||
3520 | return 1; | |
3521 | } | |
9878760c | 3522 | \f |
39a10a29 GK |
3523 | |
3524 | /* A validation routine: say whether CODE, a condition code, | |
3525 | and MODE match. The other alternatives either don't make | |
3526 | sense or should never be generated. */ | |
3527 | static void | |
3528 | validate_condition_mode (code, mode) | |
3529 | enum rtx_code code; | |
3530 | enum machine_mode mode; | |
3531 | { | |
3532 | if (GET_RTX_CLASS (code) != '<' | |
3533 | || GET_MODE_CLASS (mode) != MODE_CC) | |
3534 | abort (); | |
3535 | ||
3536 | /* These don't make sense. */ | |
3537 | if ((code == GT || code == LT || code == GE || code == LE) | |
3538 | && mode == CCUNSmode) | |
3539 | abort (); | |
3540 | ||
3541 | if ((code == GTU || code == LTU || code == GEU || code == LEU) | |
3542 | && mode != CCUNSmode) | |
3543 | abort (); | |
3544 | ||
3545 | if (mode != CCFPmode | |
3546 | && (code == ORDERED || code == UNORDERED | |
3547 | || code == UNEQ || code == LTGT | |
3548 | || code == UNGT || code == UNLT | |
3549 | || code == UNGE || code == UNLE)) | |
3550 | abort(); | |
3551 | ||
de6c5979 BL |
3552 | /* These should never be generated except for |
3553 | flag_unsafe_math_optimizations. */ | |
39a10a29 | 3554 | if (mode == CCFPmode |
de6c5979 | 3555 | && ! flag_unsafe_math_optimizations |
39a10a29 GK |
3556 | && (code == LE || code == GE |
3557 | || code == UNEQ || code == LTGT | |
3558 | || code == UNGT || code == UNLT)) | |
3559 | abort (); | |
3560 | ||
3561 | /* These are invalid; the information is not there. */ | |
3562 | if (mode == CCEQmode | |
3563 | && code != EQ && code != NE) | |
3564 | abort (); | |
3565 | } | |
3566 | ||
9878760c RK |
3567 | /* Return 1 if OP is a comparison operation that is valid for a branch insn. |
3568 | We only check the opcode against the mode of the CC value here. */ | |
3569 | ||
3570 | int | |
3571 | branch_comparison_operator (op, mode) | |
3572 | register rtx op; | |
296b8152 | 3573 | enum machine_mode mode ATTRIBUTE_UNUSED; |
9878760c RK |
3574 | { |
3575 | enum rtx_code code = GET_CODE (op); | |
3576 | enum machine_mode cc_mode; | |
3577 | ||
3578 | if (GET_RTX_CLASS (code) != '<') | |
3579 | return 0; | |
3580 | ||
3581 | cc_mode = GET_MODE (XEXP (op, 0)); | |
3582 | if (GET_MODE_CLASS (cc_mode) != MODE_CC) | |
3583 | return 0; | |
3584 | ||
39a10a29 | 3585 | validate_condition_mode (code, cc_mode); |
9878760c | 3586 | |
39a10a29 GK |
3587 | return 1; |
3588 | } | |
3589 | ||
3590 | /* Return 1 if OP is a comparison operation that is valid for a branch | |
3591 | insn and which is true if the corresponding bit in the CC register | |
3592 | is set. */ | |
3593 | ||
3594 | int | |
3595 | branch_positive_comparison_operator (op, mode) | |
3596 | register rtx op; | |
3597 | enum machine_mode mode; | |
3598 | { | |
3599 | enum rtx_code code; | |
3600 | ||
3601 | if (! branch_comparison_operator (op, mode)) | |
9878760c RK |
3602 | return 0; |
3603 | ||
39a10a29 GK |
3604 | code = GET_CODE (op); |
3605 | return (code == EQ || code == LT || code == GT | |
3606 | || code == LTU || code == GTU | |
3607 | || code == UNORDERED); | |
9878760c RK |
3608 | } |
3609 | ||
39a10a29 | 3610 | |
9878760c RK |
3611 | /* Return 1 if OP is a comparison operation that is valid for an scc insn. |
3612 | We check the opcode against the mode of the CC value and disallow EQ or | |
3613 | NE comparisons for integers. */ | |
3614 | ||
3615 | int | |
3616 | scc_comparison_operator (op, mode) | |
3617 | register rtx op; | |
3618 | enum machine_mode mode; | |
3619 | { | |
3620 | enum rtx_code code = GET_CODE (op); | |
3621 | enum machine_mode cc_mode; | |
3622 | ||
3623 | if (GET_MODE (op) != mode && mode != VOIDmode) | |
3624 | return 0; | |
3625 | ||
3626 | if (GET_RTX_CLASS (code) != '<') | |
3627 | return 0; | |
3628 | ||
3629 | cc_mode = GET_MODE (XEXP (op, 0)); | |
3630 | if (GET_MODE_CLASS (cc_mode) != MODE_CC) | |
3631 | return 0; | |
3632 | ||
39a10a29 | 3633 | validate_condition_mode (code, cc_mode); |
9878760c | 3634 | |
39a10a29 | 3635 | if (code == NE && cc_mode != CCFPmode) |
c5defebb RK |
3636 | return 0; |
3637 | ||
9878760c RK |
3638 | return 1; |
3639 | } | |
e0cd0770 JC |
3640 | |
3641 | int | |
3642 | trap_comparison_operator (op, mode) | |
3643 | rtx op; | |
3644 | enum machine_mode mode; | |
3645 | { | |
3646 | if (mode != VOIDmode && mode != GET_MODE (op)) | |
3647 | return 0; | |
39a10a29 | 3648 | return GET_RTX_CLASS (GET_CODE (op)) == '<'; |
e0cd0770 | 3649 | } |
dfbdccdb GK |
3650 | |
3651 | int | |
3652 | boolean_operator (op, mode) | |
3653 | rtx op; | |
3654 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
3655 | { | |
3656 | enum rtx_code code = GET_CODE (op); | |
3657 | return (code == AND || code == IOR || code == XOR); | |
3658 | } | |
1d328b19 GK |
3659 | |
3660 | int | |
3661 | boolean_or_operator (op, mode) | |
3662 | rtx op; | |
3663 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
3664 | { | |
3665 | enum rtx_code code = GET_CODE (op); | |
3666 | return (code == IOR || code == XOR); | |
3667 | } | |
50a0b056 GK |
3668 | |
3669 | int | |
3670 | min_max_operator (op, mode) | |
3671 | rtx op; | |
3672 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
3673 | { | |
3674 | enum rtx_code code = GET_CODE (op); | |
3675 | return (code == SMIN || code == SMAX || code == UMIN || code == UMAX); | |
3676 | } | |
9878760c RK |
3677 | \f |
3678 | /* Return 1 if ANDOP is a mask that has no bits on that are not in the | |
3679 | mask required to convert the result of a rotate insn into a shift | |
3680 | left insn of SHIFTOP bits. Both are known to be CONST_INT. */ | |
3681 | ||
3682 | int | |
3683 | includes_lshift_p (shiftop, andop) | |
3684 | register rtx shiftop; | |
3685 | register rtx andop; | |
3686 | { | |
e2c953b6 DE |
3687 | unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0; |
3688 | ||
3689 | shift_mask <<= INTVAL (shiftop); | |
9878760c RK |
3690 | |
3691 | return (INTVAL (andop) & ~shift_mask) == 0; | |
3692 | } | |
3693 | ||
3694 | /* Similar, but for right shift. */ | |
3695 | ||
3696 | int | |
3697 | includes_rshift_p (shiftop, andop) | |
3698 | register rtx shiftop; | |
3699 | register rtx andop; | |
3700 | { | |
a7653a2c | 3701 | unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0; |
9878760c RK |
3702 | |
3703 | shift_mask >>= INTVAL (shiftop); | |
3704 | ||
e2c953b6 DE |
3705 | return (INTVAL (andop) & ~shift_mask) == 0; |
3706 | } | |
3707 | ||
3708 | /* Return 1 if ANDOP is a mask that has no bits on that are not in the | |
3709 | mask required to convert the result of a rotate insn into a shift | |
3710 | left insn of SHIFTOP bits. */ | |
3711 | ||
3712 | int | |
3713 | includes_lshift64_p (shiftop, andop) | |
3714 | register rtx shiftop; | |
3715 | register rtx andop; | |
3716 | { | |
3717 | #if HOST_BITS_PER_WIDE_INT == 64 | |
3718 | unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0; | |
3719 | ||
3720 | shift_mask <<= INTVAL (shiftop); | |
3721 | ||
3722 | return (INTVAL (andop) & ~shift_mask) == 0; | |
3723 | #else | |
3724 | unsigned HOST_WIDE_INT shift_mask_low = ~(unsigned HOST_WIDE_INT) 0; | |
3725 | unsigned HOST_WIDE_INT shift_mask_high = ~(unsigned HOST_WIDE_INT) 0; | |
3726 | ||
3727 | shift_mask_low <<= INTVAL (shiftop); | |
3728 | ||
3729 | if (INTVAL (shiftop) > 32) | |
3730 | shift_mask_high <<= (INTVAL (shiftop) - 32); | |
3731 | ||
3732 | if (GET_CODE (andop) == CONST_INT) | |
3733 | return (INTVAL (andop) & ~shift_mask_low) == 0; | |
3734 | else | |
3735 | return ((CONST_DOUBLE_HIGH (andop) & ~shift_mask_high) == 0 | |
3736 | && (CONST_DOUBLE_LOW (andop) & ~shift_mask_low) == 0); | |
3737 | #endif | |
9878760c | 3738 | } |
35068b43 RK |
3739 | |
3740 | /* Return 1 if REGNO (reg1) == REGNO (reg2) - 1 making them candidates | |
3741 | for lfq and stfq insns. | |
3742 | ||
3743 | Note reg1 and reg2 *must* be hard registers. To be sure we will | |
3744 | abort if we are passed pseudo registers. */ | |
3745 | ||
3746 | int | |
3747 | registers_ok_for_quad_peep (reg1, reg2) | |
3748 | rtx reg1, reg2; | |
3749 | { | |
3750 | /* We might have been passed a SUBREG. */ | |
3751 | if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG) | |
3752 | return 0; | |
3753 | ||
3754 | return (REGNO (reg1) == REGNO (reg2) - 1); | |
3755 | } | |
3756 | ||
3757 | /* Return 1 if addr1 and addr2 are suitable for lfq or stfq insn. addr1 and | |
3758 | addr2 must be in consecutive memory locations (addr2 == addr1 + 8). */ | |
3759 | ||
3760 | int | |
3761 | addrs_ok_for_quad_peep (addr1, addr2) | |
3762 | register rtx addr1; | |
3763 | register rtx addr2; | |
3764 | { | |
e2c953b6 | 3765 | unsigned int reg1; |
35068b43 RK |
3766 | int offset1; |
3767 | ||
3768 | /* Extract an offset (if used) from the first addr. */ | |
3769 | if (GET_CODE (addr1) == PLUS) | |
3770 | { | |
3771 | /* If not a REG, return zero. */ | |
3772 | if (GET_CODE (XEXP (addr1, 0)) != REG) | |
3773 | return 0; | |
3774 | else | |
3775 | { | |
3776 | reg1 = REGNO (XEXP (addr1, 0)); | |
3777 | /* The offset must be constant! */ | |
3778 | if (GET_CODE (XEXP (addr1, 1)) != CONST_INT) | |
3779 | return 0; | |
3780 | offset1 = INTVAL (XEXP (addr1, 1)); | |
3781 | } | |
3782 | } | |
3783 | else if (GET_CODE (addr1) != REG) | |
3784 | return 0; | |
3785 | else | |
3786 | { | |
3787 | reg1 = REGNO (addr1); | |
3788 | /* This was a simple (mem (reg)) expression. Offset is 0. */ | |
3789 | offset1 = 0; | |
3790 | } | |
3791 | ||
acad7ed3 | 3792 | /* Make sure the second address is a (mem (plus (reg) (const_int))). */ |
35068b43 RK |
3793 | if (GET_CODE (addr2) != PLUS) |
3794 | return 0; | |
3795 | ||
3796 | if (GET_CODE (XEXP (addr2, 0)) != REG | |
3797 | || GET_CODE (XEXP (addr2, 1)) != CONST_INT) | |
3798 | return 0; | |
3799 | ||
3800 | if (reg1 != REGNO (XEXP (addr2, 0))) | |
3801 | return 0; | |
3802 | ||
3803 | /* The offset for the second addr must be 8 more than the first addr. */ | |
3804 | if (INTVAL (XEXP (addr2, 1)) != offset1 + 8) | |
3805 | return 0; | |
3806 | ||
3807 | /* All the tests passed. addr1 and addr2 are valid for lfq or stfq | |
3808 | instructions. */ | |
3809 | return 1; | |
3810 | } | |
9878760c RK |
3811 | \f |
3812 | /* Return the register class of a scratch register needed to copy IN into | |
3813 | or out of a register in CLASS in MODE. If it can be done directly, | |
3814 | NO_REGS is returned. */ | |
3815 | ||
3816 | enum reg_class | |
3817 | secondary_reload_class (class, mode, in) | |
3818 | enum reg_class class; | |
296b8152 | 3819 | enum machine_mode mode ATTRIBUTE_UNUSED; |
9878760c RK |
3820 | rtx in; |
3821 | { | |
5accd822 | 3822 | int regno; |
9878760c | 3823 | |
46fad5b7 DJ |
3824 | if (TARGET_ELF || (DEFAULT_ABI == ABI_DARWIN && flag_pic)) |
3825 | { | |
3826 | /* We cannot copy a symbolic operand directly into anything | |
3827 | other than BASE_REGS for TARGET_ELF. So indicate that a | |
3828 | register from BASE_REGS is needed as an intermediate | |
3829 | register. | |
3830 | ||
3831 | On Darwin, pic addresses require a load from memory, which | |
3832 | needs a base register. */ | |
3833 | if (class != BASE_REGS | |
3834 | && (GET_CODE (in) == SYMBOL_REF | |
3835 | || GET_CODE (in) == HIGH | |
3836 | || GET_CODE (in) == LABEL_REF | |
3837 | || GET_CODE (in) == CONST)) | |
3838 | return BASE_REGS; | |
3839 | } | |
e7b7998a | 3840 | |
5accd822 DE |
3841 | if (GET_CODE (in) == REG) |
3842 | { | |
3843 | regno = REGNO (in); | |
3844 | if (regno >= FIRST_PSEUDO_REGISTER) | |
3845 | { | |
3846 | regno = true_regnum (in); | |
3847 | if (regno >= FIRST_PSEUDO_REGISTER) | |
3848 | regno = -1; | |
3849 | } | |
3850 | } | |
3851 | else if (GET_CODE (in) == SUBREG) | |
3852 | { | |
3853 | regno = true_regnum (in); | |
3854 | if (regno >= FIRST_PSEUDO_REGISTER) | |
3855 | regno = -1; | |
3856 | } | |
3857 | else | |
3858 | regno = -1; | |
3859 | ||
9878760c RK |
3860 | /* We can place anything into GENERAL_REGS and can put GENERAL_REGS |
3861 | into anything. */ | |
3862 | if (class == GENERAL_REGS || class == BASE_REGS | |
3863 | || (regno >= 0 && INT_REGNO_P (regno))) | |
3864 | return NO_REGS; | |
3865 | ||
3866 | /* Constants, memory, and FP registers can go into FP registers. */ | |
3867 | if ((regno == -1 || FP_REGNO_P (regno)) | |
3868 | && (class == FLOAT_REGS || class == NON_SPECIAL_REGS)) | |
3869 | return NO_REGS; | |
3870 | ||
3871 | /* We can copy among the CR registers. */ | |
3872 | if ((class == CR_REGS || class == CR0_REGS) | |
3873 | && regno >= 0 && CR_REGNO_P (regno)) | |
3874 | return NO_REGS; | |
3875 | ||
3876 | /* Otherwise, we need GENERAL_REGS. */ | |
3877 | return GENERAL_REGS; | |
3878 | } | |
3879 | \f | |
3880 | /* Given a comparison operation, return the bit number in CCR to test. We | |
3881 | know this is a valid comparison. | |
3882 | ||
3883 | SCC_P is 1 if this is for an scc. That means that %D will have been | |
3884 | used instead of %C, so the bits will be in different places. | |
3885 | ||
b4ac57ab | 3886 | Return -1 if OP isn't a valid comparison for some reason. */ |
9878760c RK |
3887 | |
3888 | int | |
3889 | ccr_bit (op, scc_p) | |
3890 | register rtx op; | |
3891 | int scc_p; | |
3892 | { | |
3893 | enum rtx_code code = GET_CODE (op); | |
3894 | enum machine_mode cc_mode; | |
3895 | int cc_regnum; | |
3896 | int base_bit; | |
9ebbca7d | 3897 | rtx reg; |
9878760c RK |
3898 | |
3899 | if (GET_RTX_CLASS (code) != '<') | |
3900 | return -1; | |
3901 | ||
9ebbca7d GK |
3902 | reg = XEXP (op, 0); |
3903 | ||
3904 | if (GET_CODE (reg) != REG | |
3905 | || ! CR_REGNO_P (REGNO (reg))) | |
3906 | abort (); | |
3907 | ||
3908 | cc_mode = GET_MODE (reg); | |
3909 | cc_regnum = REGNO (reg); | |
3910 | base_bit = 4 * (cc_regnum - CR0_REGNO); | |
9878760c | 3911 | |
39a10a29 | 3912 | validate_condition_mode (code, cc_mode); |
c5defebb | 3913 | |
9878760c RK |
3914 | switch (code) |
3915 | { | |
3916 | case NE: | |
3917 | return scc_p ? base_bit + 3 : base_bit + 2; | |
3918 | case EQ: | |
3919 | return base_bit + 2; | |
1c882ea4 | 3920 | case GT: case GTU: case UNLE: |
9878760c | 3921 | return base_bit + 1; |
1c882ea4 | 3922 | case LT: case LTU: case UNGE: |
9878760c | 3923 | return base_bit; |
1c882ea4 GK |
3924 | case ORDERED: case UNORDERED: |
3925 | return base_bit + 3; | |
9878760c RK |
3926 | |
3927 | case GE: case GEU: | |
39a10a29 | 3928 | /* If scc, we will have done a cror to put the bit in the |
9878760c RK |
3929 | unordered position. So test that bit. For integer, this is ! LT |
3930 | unless this is an scc insn. */ | |
39a10a29 | 3931 | return scc_p ? base_bit + 3 : base_bit; |
9878760c RK |
3932 | |
3933 | case LE: case LEU: | |
39a10a29 | 3934 | return scc_p ? base_bit + 3 : base_bit + 1; |
1c882ea4 | 3935 | |
9878760c RK |
3936 | default: |
3937 | abort (); | |
3938 | } | |
3939 | } | |
1ff7789b | 3940 | \f |
8d30c4ee | 3941 | /* Return the GOT register. */ |
1ff7789b MM |
3942 | |
3943 | struct rtx_def * | |
3944 | rs6000_got_register (value) | |
5f59ecb7 | 3945 | rtx value ATTRIBUTE_UNUSED; |
1ff7789b | 3946 | { |
8d30c4ee FS |
3947 | /* The second flow pass currently (June 1999) can't update regs_ever_live |
3948 | without disturbing other parts of the compiler, so update it here to | |
3949 | make the prolog/epilogue code happy. */ | |
3cb999d8 | 3950 | if (no_new_pseudos && ! regs_ever_live[PIC_OFFSET_TABLE_REGNUM]) |
8d30c4ee | 3951 | regs_ever_live[PIC_OFFSET_TABLE_REGNUM] = 1; |
1ff7789b | 3952 | |
8d30c4ee | 3953 | current_function_uses_pic_offset_table = 1; |
3cb999d8 | 3954 | |
1ff7789b MM |
3955 | return pic_offset_table_rtx; |
3956 | } | |
a7df97e6 | 3957 | \f |
71f123ca | 3958 | /* Functions to init, mark and free struct machine_function. |
a7df97e6 MM |
3959 | These will be called, via pointer variables, |
3960 | from push_function_context and pop_function_context. */ | |
3961 | ||
00dba523 NC |
3962 | static void |
3963 | rs6000_init_machine_status (p) | |
a7df97e6 MM |
3964 | struct function *p; |
3965 | { | |
71f123ca FS |
3966 | p->machine = (machine_function *) xcalloc (1, sizeof (machine_function)); |
3967 | } | |
a7df97e6 | 3968 | |
00dba523 NC |
3969 | static void |
3970 | rs6000_free_machine_status (p) | |
a7df97e6 MM |
3971 | struct function *p; |
3972 | { | |
00dba523 NC |
3973 | if (p->machine == NULL) |
3974 | return; | |
a7df97e6 | 3975 | |
00dba523 NC |
3976 | free (p->machine); |
3977 | p->machine = NULL; | |
a7df97e6 MM |
3978 | } |
3979 | ||
9878760c RK |
3980 | \f |
3981 | /* Print an operand. Recognize special options, documented below. */ | |
3982 | ||
38c1f2d7 | 3983 | #if TARGET_ELF |
d9407988 | 3984 | #define SMALL_DATA_RELOC ((rs6000_sdata == SDATA_EABI) ? "sda21" : "sdarel") |
8fbd2dc7 | 3985 | #define SMALL_DATA_REG ((rs6000_sdata == SDATA_EABI) ? 0 : 13) |
ba5e43aa MM |
3986 | #else |
3987 | #define SMALL_DATA_RELOC "sda21" | |
8fbd2dc7 | 3988 | #define SMALL_DATA_REG 0 |
ba5e43aa MM |
3989 | #endif |
3990 | ||
9878760c RK |
3991 | void |
3992 | print_operand (file, x, code) | |
3993 | FILE *file; | |
3994 | rtx x; | |
9ebbca7d | 3995 | int code; |
9878760c RK |
3996 | { |
3997 | int i; | |
a260abc9 | 3998 | HOST_WIDE_INT val; |
9878760c RK |
3999 | |
4000 | /* These macros test for integers and extract the low-order bits. */ | |
4001 | #define INT_P(X) \ | |
4002 | ((GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST_DOUBLE) \ | |
4003 | && GET_MODE (X) == VOIDmode) | |
4004 | ||
4005 | #define INT_LOWPART(X) \ | |
4006 | (GET_CODE (X) == CONST_INT ? INTVAL (X) : CONST_DOUBLE_LOW (X)) | |
4007 | ||
4008 | switch (code) | |
4009 | { | |
a8b3aeda | 4010 | case '.': |
a85d226b RK |
4011 | /* Write out an instruction after the call which may be replaced |
4012 | with glue code by the loader. This depends on the AIX version. */ | |
4013 | asm_fprintf (file, RS6000_CALL_GLUE); | |
a8b3aeda RK |
4014 | return; |
4015 | ||
c81bebd7 MM |
4016 | case '$': |
4017 | /* Write out either a '.' or '$' for the current location, depending | |
4018 | on whether this is Solaris or not. */ | |
4019 | putc ((DEFAULT_ABI == ABI_SOLARIS) ? '.' : '$', file); | |
4020 | return; | |
4021 | ||
81eace42 GK |
4022 | /* %a is output_address. */ |
4023 | ||
9854d9ed RK |
4024 | case 'A': |
4025 | /* If X is a constant integer whose low-order 5 bits are zero, | |
4026 | write 'l'. Otherwise, write 'r'. This is a kludge to fix a bug | |
76229ac8 | 4027 | in the AIX assembler where "sri" with a zero shift count |
9854d9ed RK |
4028 | write a trash instruction. */ |
4029 | if (GET_CODE (x) == CONST_INT && (INTVAL (x) & 31) == 0) | |
76229ac8 | 4030 | putc ('l', file); |
9854d9ed | 4031 | else |
76229ac8 | 4032 | putc ('r', file); |
9854d9ed RK |
4033 | return; |
4034 | ||
4035 | case 'b': | |
e2c953b6 DE |
4036 | /* If constant, low-order 16 bits of constant, unsigned. |
4037 | Otherwise, write normally. */ | |
4038 | if (INT_P (x)) | |
4039 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 0xffff); | |
4040 | else | |
4041 | print_operand (file, x, 0); | |
cad12a8d RK |
4042 | return; |
4043 | ||
a260abc9 DE |
4044 | case 'B': |
4045 | /* If the low-order bit is zero, write 'r'; otherwise, write 'l' | |
4046 | for 64-bit mask direction. */ | |
296b8152 | 4047 | putc (((INT_LOWPART(x) & 1) == 0 ? 'r' : 'l'), file); |
a238cd8b | 4048 | return; |
a260abc9 | 4049 | |
81eace42 GK |
4050 | /* %c is output_addr_const if a CONSTANT_ADDRESS_P, otherwise |
4051 | output_operand. */ | |
4052 | ||
9854d9ed | 4053 | case 'D': |
39a10a29 GK |
4054 | /* There used to be a comment for 'C' reading "This is an |
4055 | optional cror needed for certain floating-point | |
4056 | comparisons. Otherwise write nothing." */ | |
4057 | ||
9854d9ed RK |
4058 | /* Similar, except that this is for an scc, so we must be able to |
4059 | encode the test in a single bit that is one. We do the above | |
4060 | for any LE, GE, GEU, or LEU and invert the bit for NE. */ | |
4061 | if (GET_CODE (x) == LE || GET_CODE (x) == GE | |
4062 | || GET_CODE (x) == LEU || GET_CODE (x) == GEU) | |
4063 | { | |
9ebbca7d | 4064 | int base_bit = 4 * (REGNO (XEXP (x, 0)) - CR0_REGNO); |
9854d9ed RK |
4065 | |
4066 | fprintf (file, "cror %d,%d,%d\n\t", base_bit + 3, | |
4067 | base_bit + 2, | |
4068 | base_bit + (GET_CODE (x) == GE || GET_CODE (x) == GEU)); | |
4069 | } | |
4070 | ||
4071 | else if (GET_CODE (x) == NE) | |
4072 | { | |
9ebbca7d | 4073 | int base_bit = 4 * (REGNO (XEXP (x, 0)) - CR0_REGNO); |
9854d9ed RK |
4074 | |
4075 | fprintf (file, "crnor %d,%d,%d\n\t", base_bit + 3, | |
4076 | base_bit + 2, base_bit + 2); | |
4077 | } | |
4078 | return; | |
4079 | ||
4080 | case 'E': | |
39a10a29 | 4081 | /* X is a CR register. Print the number of the EQ bit of the CR */ |
9854d9ed RK |
4082 | if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x))) |
4083 | output_operand_lossage ("invalid %%E value"); | |
78fbdbf7 | 4084 | else |
39a10a29 | 4085 | fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO) + 2); |
a85d226b | 4086 | return; |
9854d9ed RK |
4087 | |
4088 | case 'f': | |
4089 | /* X is a CR register. Print the shift count needed to move it | |
4090 | to the high-order four bits. */ | |
4091 | if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x))) | |
4092 | output_operand_lossage ("invalid %%f value"); | |
4093 | else | |
9ebbca7d | 4094 | fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO)); |
9854d9ed RK |
4095 | return; |
4096 | ||
4097 | case 'F': | |
4098 | /* Similar, but print the count for the rotate in the opposite | |
4099 | direction. */ | |
4100 | if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x))) | |
4101 | output_operand_lossage ("invalid %%F value"); | |
4102 | else | |
9ebbca7d | 4103 | fprintf (file, "%d", 32 - 4 * (REGNO (x) - CR0_REGNO)); |
9854d9ed RK |
4104 | return; |
4105 | ||
4106 | case 'G': | |
4107 | /* X is a constant integer. If it is negative, print "m", | |
4108 | otherwise print "z". This is to make a aze or ame insn. */ | |
4109 | if (GET_CODE (x) != CONST_INT) | |
4110 | output_operand_lossage ("invalid %%G value"); | |
4111 | else if (INTVAL (x) >= 0) | |
76229ac8 | 4112 | putc ('z', file); |
9854d9ed | 4113 | else |
76229ac8 | 4114 | putc ('m', file); |
9854d9ed | 4115 | return; |
e2c953b6 | 4116 | |
9878760c | 4117 | case 'h': |
df3d94ed RK |
4118 | /* If constant, output low-order five bits. Otherwise, |
4119 | write normally. */ | |
9878760c | 4120 | if (INT_P (x)) |
5f59ecb7 | 4121 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 31); |
9878760c RK |
4122 | else |
4123 | print_operand (file, x, 0); | |
4124 | return; | |
4125 | ||
64305719 DE |
4126 | case 'H': |
4127 | /* If constant, output low-order six bits. Otherwise, | |
4128 | write normally. */ | |
4129 | if (INT_P (x)) | |
5f59ecb7 | 4130 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 63); |
64305719 DE |
4131 | else |
4132 | print_operand (file, x, 0); | |
4133 | return; | |
4134 | ||
9854d9ed RK |
4135 | case 'I': |
4136 | /* Print `i' if this is a constant, else nothing. */ | |
9878760c | 4137 | if (INT_P (x)) |
76229ac8 | 4138 | putc ('i', file); |
9878760c RK |
4139 | return; |
4140 | ||
9854d9ed RK |
4141 | case 'j': |
4142 | /* Write the bit number in CCR for jump. */ | |
4143 | i = ccr_bit (x, 0); | |
4144 | if (i == -1) | |
4145 | output_operand_lossage ("invalid %%j code"); | |
9878760c | 4146 | else |
9854d9ed | 4147 | fprintf (file, "%d", i); |
9878760c RK |
4148 | return; |
4149 | ||
9854d9ed RK |
4150 | case 'J': |
4151 | /* Similar, but add one for shift count in rlinm for scc and pass | |
4152 | scc flag to `ccr_bit'. */ | |
4153 | i = ccr_bit (x, 1); | |
4154 | if (i == -1) | |
4155 | output_operand_lossage ("invalid %%J code"); | |
4156 | else | |
a0466a68 RK |
4157 | /* If we want bit 31, write a shift count of zero, not 32. */ |
4158 | fprintf (file, "%d", i == 31 ? 0 : i + 1); | |
9878760c RK |
4159 | return; |
4160 | ||
9854d9ed RK |
4161 | case 'k': |
4162 | /* X must be a constant. Write the 1's complement of the | |
4163 | constant. */ | |
9878760c | 4164 | if (! INT_P (x)) |
9854d9ed | 4165 | output_operand_lossage ("invalid %%k value"); |
e2c953b6 DE |
4166 | else |
4167 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, ~ INT_LOWPART (x)); | |
9878760c RK |
4168 | return; |
4169 | ||
81eace42 | 4170 | case 'K': |
9ebbca7d GK |
4171 | /* X must be a symbolic constant on ELF. Write an |
4172 | expression suitable for an 'addi' that adds in the low 16 | |
4173 | bits of the MEM. */ | |
4174 | if (GET_CODE (x) != CONST) | |
4175 | { | |
4176 | print_operand_address (file, x); | |
4177 | fputs ("@l", file); | |
4178 | } | |
4179 | else | |
4180 | { | |
4181 | if (GET_CODE (XEXP (x, 0)) != PLUS | |
4182 | || (GET_CODE (XEXP (XEXP (x, 0), 0)) != SYMBOL_REF | |
4183 | && GET_CODE (XEXP (XEXP (x, 0), 0)) != LABEL_REF) | |
4184 | || GET_CODE (XEXP (XEXP (x, 0), 1)) != CONST_INT) | |
53cd5d6c | 4185 | output_operand_lossage ("invalid %%K value"); |
9ebbca7d GK |
4186 | print_operand_address (file, XEXP (XEXP (x, 0), 0)); |
4187 | fputs ("@l", file); | |
4188 | print_operand (file, XEXP (XEXP (x, 0), 1), 0); | |
4189 | } | |
81eace42 GK |
4190 | return; |
4191 | ||
4192 | /* %l is output_asm_label. */ | |
9ebbca7d | 4193 | |
9854d9ed RK |
4194 | case 'L': |
4195 | /* Write second word of DImode or DFmode reference. Works on register | |
4196 | or non-indexed memory only. */ | |
4197 | if (GET_CODE (x) == REG) | |
5ebfb2ba | 4198 | fprintf (file, "%s", reg_names[REGNO (x) + 1]); |
9854d9ed RK |
4199 | else if (GET_CODE (x) == MEM) |
4200 | { | |
4201 | /* Handle possible auto-increment. Since it is pre-increment and | |
1427100a | 4202 | we have already done it, we can just use an offset of word. */ |
9854d9ed RK |
4203 | if (GET_CODE (XEXP (x, 0)) == PRE_INC |
4204 | || GET_CODE (XEXP (x, 0)) == PRE_DEC) | |
ed8908e7 RK |
4205 | output_address (plus_constant (XEXP (XEXP (x, 0), 0), |
4206 | UNITS_PER_WORD)); | |
9854d9ed | 4207 | else |
d7624dc0 RK |
4208 | output_address (XEXP (adjust_address_nv (x, SImode, |
4209 | UNITS_PER_WORD), | |
4210 | 0)); | |
ed8908e7 | 4211 | |
ba5e43aa | 4212 | if (small_data_operand (x, GET_MODE (x))) |
8fbd2dc7 MM |
4213 | fprintf (file, "@%s(%s)", SMALL_DATA_RELOC, |
4214 | reg_names[SMALL_DATA_REG]); | |
9854d9ed | 4215 | } |
9878760c | 4216 | return; |
9854d9ed | 4217 | |
9878760c RK |
4218 | case 'm': |
4219 | /* MB value for a mask operand. */ | |
4220 | if (! mask_operand (x, VOIDmode)) | |
4221 | output_operand_lossage ("invalid %%m value"); | |
4222 | ||
4223 | val = INT_LOWPART (x); | |
4224 | ||
4225 | /* If the high bit is set and the low bit is not, the value is zero. | |
4226 | If the high bit is zero, the value is the first 1 bit we find from | |
4227 | the left. */ | |
0858c623 | 4228 | if ((val & 0x80000000) && ((val & 1) == 0)) |
9878760c | 4229 | { |
19d2d16f | 4230 | putc ('0', file); |
9878760c RK |
4231 | return; |
4232 | } | |
0858c623 | 4233 | else if ((val & 0x80000000) == 0) |
9878760c RK |
4234 | { |
4235 | for (i = 1; i < 32; i++) | |
0858c623 | 4236 | if ((val <<= 1) & 0x80000000) |
9878760c RK |
4237 | break; |
4238 | fprintf (file, "%d", i); | |
4239 | return; | |
4240 | } | |
4241 | ||
4242 | /* Otherwise, look for the first 0 bit from the right. The result is its | |
4243 | number plus 1. We know the low-order bit is one. */ | |
4244 | for (i = 0; i < 32; i++) | |
4245 | if (((val >>= 1) & 1) == 0) | |
4246 | break; | |
4247 | ||
a260abc9 | 4248 | /* If we ended in ...01, i would be 0. The correct value is 31, so |
9878760c RK |
4249 | we want 31 - i. */ |
4250 | fprintf (file, "%d", 31 - i); | |
4251 | return; | |
4252 | ||
4253 | case 'M': | |
4254 | /* ME value for a mask operand. */ | |
4255 | if (! mask_operand (x, VOIDmode)) | |
a260abc9 | 4256 | output_operand_lossage ("invalid %%M value"); |
9878760c RK |
4257 | |
4258 | val = INT_LOWPART (x); | |
4259 | ||
4260 | /* If the low bit is set and the high bit is not, the value is 31. | |
4261 | If the low bit is zero, the value is the first 1 bit we find from | |
4262 | the right. */ | |
0858c623 | 4263 | if ((val & 1) && ((val & 0x80000000) == 0)) |
9878760c | 4264 | { |
76229ac8 | 4265 | fputs ("31", file); |
9878760c RK |
4266 | return; |
4267 | } | |
4268 | else if ((val & 1) == 0) | |
4269 | { | |
4270 | for (i = 0; i < 32; i++) | |
4271 | if ((val >>= 1) & 1) | |
4272 | break; | |
4273 | ||
a260abc9 | 4274 | /* If we had ....10, i would be 0. The result should be |
9878760c RK |
4275 | 30, so we need 30 - i. */ |
4276 | fprintf (file, "%d", 30 - i); | |
4277 | return; | |
4278 | } | |
4279 | ||
4280 | /* Otherwise, look for the first 0 bit from the left. The result is its | |
4281 | number minus 1. We know the high-order bit is one. */ | |
4282 | for (i = 0; i < 32; i++) | |
0858c623 | 4283 | if (((val <<= 1) & 0x80000000) == 0) |
9878760c RK |
4284 | break; |
4285 | ||
4286 | fprintf (file, "%d", i); | |
4287 | return; | |
4288 | ||
81eace42 GK |
4289 | /* %n outputs the negative of its operand. */ |
4290 | ||
9878760c RK |
4291 | case 'N': |
4292 | /* Write the number of elements in the vector times 4. */ | |
4293 | if (GET_CODE (x) != PARALLEL) | |
4294 | output_operand_lossage ("invalid %%N value"); | |
e2c953b6 DE |
4295 | else |
4296 | fprintf (file, "%d", XVECLEN (x, 0) * 4); | |
9878760c RK |
4297 | return; |
4298 | ||
4299 | case 'O': | |
4300 | /* Similar, but subtract 1 first. */ | |
4301 | if (GET_CODE (x) != PARALLEL) | |
1427100a | 4302 | output_operand_lossage ("invalid %%O value"); |
e2c953b6 DE |
4303 | else |
4304 | fprintf (file, "%d", (XVECLEN (x, 0) - 1) * 4); | |
9878760c RK |
4305 | return; |
4306 | ||
9854d9ed RK |
4307 | case 'p': |
4308 | /* X is a CONST_INT that is a power of two. Output the logarithm. */ | |
4309 | if (! INT_P (x) | |
2bfcf297 | 4310 | || INT_LOWPART (x) < 0 |
9854d9ed RK |
4311 | || (i = exact_log2 (INT_LOWPART (x))) < 0) |
4312 | output_operand_lossage ("invalid %%p value"); | |
e2c953b6 DE |
4313 | else |
4314 | fprintf (file, "%d", i); | |
9854d9ed RK |
4315 | return; |
4316 | ||
9878760c RK |
4317 | case 'P': |
4318 | /* The operand must be an indirect memory reference. The result | |
4319 | is the register number. */ | |
4320 | if (GET_CODE (x) != MEM || GET_CODE (XEXP (x, 0)) != REG | |
4321 | || REGNO (XEXP (x, 0)) >= 32) | |
4322 | output_operand_lossage ("invalid %%P value"); | |
e2c953b6 DE |
4323 | else |
4324 | fprintf (file, "%d", REGNO (XEXP (x, 0))); | |
9878760c RK |
4325 | return; |
4326 | ||
dfbdccdb GK |
4327 | case 'q': |
4328 | /* This outputs the logical code corresponding to a boolean | |
4329 | expression. The expression may have one or both operands | |
39a10a29 GK |
4330 | negated (if one, only the first one). For condition register |
4331 | logical operations, it will also treat the negated | |
4332 | CR codes as NOTs, but not handle NOTs of them. */ | |
dfbdccdb | 4333 | { |
63bc1d05 | 4334 | const char *const *t = 0; |
dfbdccdb GK |
4335 | const char *s; |
4336 | enum rtx_code code = GET_CODE (x); | |
4337 | static const char * const tbl[3][3] = { | |
4338 | { "and", "andc", "nor" }, | |
4339 | { "or", "orc", "nand" }, | |
4340 | { "xor", "eqv", "xor" } }; | |
4341 | ||
4342 | if (code == AND) | |
4343 | t = tbl[0]; | |
4344 | else if (code == IOR) | |
4345 | t = tbl[1]; | |
4346 | else if (code == XOR) | |
4347 | t = tbl[2]; | |
4348 | else | |
4349 | output_operand_lossage ("invalid %%q value"); | |
4350 | ||
4351 | if (GET_CODE (XEXP (x, 0)) != NOT) | |
4352 | s = t[0]; | |
4353 | else | |
4354 | { | |
4355 | if (GET_CODE (XEXP (x, 1)) == NOT) | |
4356 | s = t[2]; | |
4357 | else | |
4358 | s = t[1]; | |
4359 | } | |
4360 | ||
4361 | fputs (s, file); | |
4362 | } | |
4363 | return; | |
4364 | ||
9854d9ed RK |
4365 | case 'R': |
4366 | /* X is a CR register. Print the mask for `mtcrf'. */ | |
4367 | if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x))) | |
4368 | output_operand_lossage ("invalid %%R value"); | |
4369 | else | |
9ebbca7d | 4370 | fprintf (file, "%d", 128 >> (REGNO (x) - CR0_REGNO)); |
9878760c | 4371 | return; |
9854d9ed RK |
4372 | |
4373 | case 's': | |
4374 | /* Low 5 bits of 32 - value */ | |
4375 | if (! INT_P (x)) | |
4376 | output_operand_lossage ("invalid %%s value"); | |
e2c953b6 DE |
4377 | else |
4378 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, (32 - INT_LOWPART (x)) & 31); | |
9878760c | 4379 | return; |
9854d9ed | 4380 | |
a260abc9 DE |
4381 | case 'S': |
4382 | /* PowerPC64 mask position. All 0's and all 1's are excluded. | |
4383 | CONST_INT 32-bit mask is considered sign-extended so any | |
4384 | transition must occur within the CONST_INT, not on the boundary. */ | |
4385 | if (! mask64_operand (x, VOIDmode)) | |
4386 | output_operand_lossage ("invalid %%S value"); | |
4387 | ||
4388 | val = INT_LOWPART (x); | |
4389 | ||
4390 | if (val & 1) /* Clear Left */ | |
4391 | { | |
a238cd8b DE |
4392 | for (i = 0; i < HOST_BITS_PER_WIDE_INT; i++) |
4393 | if (!((val >>= 1) & 1)) | |
4394 | break; | |
a260abc9 | 4395 | |
a238cd8b DE |
4396 | #if HOST_BITS_PER_WIDE_INT == 32 |
4397 | if (GET_CODE (x) == CONST_DOUBLE && i == 32) | |
4398 | { | |
4399 | val = CONST_DOUBLE_HIGH (x); | |
4400 | ||
4401 | if (val == 0) | |
4402 | --i; | |
4403 | else | |
4404 | for (i = 32; i < 64; i++) | |
4405 | if (!((val >>= 1) & 1)) | |
4406 | break; | |
4407 | } | |
a260abc9 | 4408 | #endif |
a238cd8b DE |
4409 | /* i = index of last set bit from right |
4410 | mask begins at 63 - i from left */ | |
4411 | if (i > 63) | |
4412 | output_operand_lossage ("%%S computed all 1's mask"); | |
cccf3bdc | 4413 | |
a260abc9 DE |
4414 | fprintf (file, "%d", 63 - i); |
4415 | return; | |
4416 | } | |
4417 | else /* Clear Right */ | |
4418 | { | |
a238cd8b DE |
4419 | for (i = 0; i < HOST_BITS_PER_WIDE_INT; i++) |
4420 | if ((val >>= 1) & 1) | |
4421 | break; | |
a260abc9 | 4422 | |
a238cd8b | 4423 | #if HOST_BITS_PER_WIDE_INT == 32 |
a260abc9 DE |
4424 | if (GET_CODE (x) == CONST_DOUBLE && i == 32) |
4425 | { | |
a238cd8b | 4426 | val = CONST_DOUBLE_HIGH (x); |
a260abc9 | 4427 | |
a238cd8b | 4428 | if (val == (HOST_WIDE_INT) -1) |
a260abc9 | 4429 | --i; |
a260abc9 | 4430 | else |
a238cd8b DE |
4431 | for (i = 32; i < 64; i++) |
4432 | if ((val >>= 1) & 1) | |
a260abc9 DE |
4433 | break; |
4434 | } | |
4435 | #endif | |
a238cd8b DE |
4436 | /* i = index of last clear bit from right |
4437 | mask ends at 62 - i from left */ | |
4438 | if (i > 62) | |
4439 | output_operand_lossage ("%%S computed all 0's mask"); | |
cccf3bdc | 4440 | |
a238cd8b | 4441 | fprintf (file, "%d", 62 - i); |
a260abc9 DE |
4442 | return; |
4443 | } | |
4444 | ||
cccf3bdc DE |
4445 | case 'T': |
4446 | /* Print the symbolic name of a branch target register. */ | |
4447 | if (GET_CODE (x) != REG || (REGNO (x) != LINK_REGISTER_REGNUM | |
4448 | && REGNO (x) != COUNT_REGISTER_REGNUM)) | |
4449 | output_operand_lossage ("invalid %%T value"); | |
e2c953b6 | 4450 | else if (REGNO (x) == LINK_REGISTER_REGNUM) |
cccf3bdc DE |
4451 | fputs (TARGET_NEW_MNEMONICS ? "lr" : "r", file); |
4452 | else | |
4453 | fputs ("ctr", file); | |
4454 | return; | |
4455 | ||
9854d9ed | 4456 | case 'u': |
802a0058 | 4457 | /* High-order 16 bits of constant for use in unsigned operand. */ |
9854d9ed RK |
4458 | if (! INT_P (x)) |
4459 | output_operand_lossage ("invalid %%u value"); | |
e2c953b6 DE |
4460 | else |
4461 | fprintf (file, HOST_WIDE_INT_PRINT_HEX, | |
4462 | (INT_LOWPART (x) >> 16) & 0xffff); | |
9878760c RK |
4463 | return; |
4464 | ||
802a0058 MM |
4465 | case 'v': |
4466 | /* High-order 16 bits of constant for use in signed operand. */ | |
4467 | if (! INT_P (x)) | |
4468 | output_operand_lossage ("invalid %%v value"); | |
e2c953b6 DE |
4469 | else |
4470 | { | |
4471 | int value = (INT_LOWPART (x) >> 16) & 0xffff; | |
802a0058 | 4472 | |
e2c953b6 DE |
4473 | /* Solaris assembler doesn't like lis 0,0x8000 */ |
4474 | if (DEFAULT_ABI == ABI_SOLARIS && (value & 0x8000) != 0) | |
4475 | fprintf (file, "%d", value | (~0 << 16)); | |
4476 | else | |
4477 | fprintf (file, "0x%x", value); | |
4478 | return; | |
4479 | } | |
802a0058 | 4480 | |
9854d9ed RK |
4481 | case 'U': |
4482 | /* Print `u' if this has an auto-increment or auto-decrement. */ | |
4483 | if (GET_CODE (x) == MEM | |
4484 | && (GET_CODE (XEXP (x, 0)) == PRE_INC | |
4485 | || GET_CODE (XEXP (x, 0)) == PRE_DEC)) | |
76229ac8 | 4486 | putc ('u', file); |
9854d9ed | 4487 | return; |
9878760c | 4488 | |
e0cd0770 JC |
4489 | case 'V': |
4490 | /* Print the trap code for this operand. */ | |
4491 | switch (GET_CODE (x)) | |
4492 | { | |
4493 | case EQ: | |
4494 | fputs ("eq", file); /* 4 */ | |
4495 | break; | |
4496 | case NE: | |
4497 | fputs ("ne", file); /* 24 */ | |
4498 | break; | |
4499 | case LT: | |
4500 | fputs ("lt", file); /* 16 */ | |
4501 | break; | |
4502 | case LE: | |
4503 | fputs ("le", file); /* 20 */ | |
4504 | break; | |
4505 | case GT: | |
4506 | fputs ("gt", file); /* 8 */ | |
4507 | break; | |
4508 | case GE: | |
4509 | fputs ("ge", file); /* 12 */ | |
4510 | break; | |
4511 | case LTU: | |
4512 | fputs ("llt", file); /* 2 */ | |
4513 | break; | |
4514 | case LEU: | |
4515 | fputs ("lle", file); /* 6 */ | |
4516 | break; | |
4517 | case GTU: | |
4518 | fputs ("lgt", file); /* 1 */ | |
4519 | break; | |
4520 | case GEU: | |
4521 | fputs ("lge", file); /* 5 */ | |
4522 | break; | |
4523 | default: | |
4524 | abort (); | |
4525 | } | |
4526 | break; | |
4527 | ||
9854d9ed RK |
4528 | case 'w': |
4529 | /* If constant, low-order 16 bits of constant, signed. Otherwise, write | |
4530 | normally. */ | |
4531 | if (INT_P (x)) | |
5f59ecb7 DE |
4532 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, |
4533 | ((INT_LOWPART (x) & 0xffff) ^ 0x8000) - 0x8000); | |
9854d9ed RK |
4534 | else |
4535 | print_operand (file, x, 0); | |
9878760c RK |
4536 | return; |
4537 | ||
9854d9ed | 4538 | case 'W': |
e2c953b6 DE |
4539 | /* MB value for a PowerPC64 rldic operand. */ |
4540 | if (! rldic_operand (x, VOIDmode)) | |
4541 | output_operand_lossage ("invalid %%W value"); | |
4542 | ||
4543 | val = (GET_CODE (x) == CONST_INT | |
4544 | ? INTVAL (x) : CONST_DOUBLE_HIGH (x)); | |
4545 | ||
4546 | if (val < 0) | |
4547 | i = -1; | |
9854d9ed | 4548 | else |
e2c953b6 DE |
4549 | for (i = 0; i < HOST_BITS_PER_WIDE_INT; i++) |
4550 | if ((val <<= 1) < 0) | |
4551 | break; | |
4552 | ||
4553 | #if HOST_BITS_PER_WIDE_INT == 32 | |
4554 | if (GET_CODE (x) == CONST_INT && i >= 0) | |
4555 | i += 32; /* zero-extend high-part was all 0's */ | |
4556 | else if (GET_CODE (x) == CONST_DOUBLE && i == 32) | |
4557 | { | |
4558 | val = CONST_DOUBLE_LOW (x); | |
4559 | ||
4560 | if (val == 0) | |
4561 | abort(); | |
4562 | else if (val < 0) | |
4563 | --i; | |
4564 | else | |
4565 | for ( ; i < 64; i++) | |
4566 | if ((val <<= 1) < 0) | |
4567 | break; | |
4568 | } | |
4569 | #endif | |
4570 | ||
4571 | fprintf (file, "%d", i + 1); | |
9854d9ed | 4572 | return; |
9878760c | 4573 | |
9854d9ed RK |
4574 | case 'X': |
4575 | if (GET_CODE (x) == MEM | |
258bfae2 | 4576 | && LEGITIMATE_INDEXED_ADDRESS_P (XEXP (x, 0), 0)) |
76229ac8 | 4577 | putc ('x', file); |
9854d9ed | 4578 | return; |
9878760c | 4579 | |
9854d9ed RK |
4580 | case 'Y': |
4581 | /* Like 'L', for third word of TImode */ | |
4582 | if (GET_CODE (x) == REG) | |
5ebfb2ba | 4583 | fprintf (file, "%s", reg_names[REGNO (x) + 2]); |
9854d9ed | 4584 | else if (GET_CODE (x) == MEM) |
9878760c | 4585 | { |
9854d9ed RK |
4586 | if (GET_CODE (XEXP (x, 0)) == PRE_INC |
4587 | || GET_CODE (XEXP (x, 0)) == PRE_DEC) | |
a54d04b7 | 4588 | output_address (plus_constant (XEXP (XEXP (x, 0), 0), 8)); |
9854d9ed | 4589 | else |
d7624dc0 | 4590 | output_address (XEXP (adjust_address_nv (x, SImode, 8), 0)); |
ba5e43aa | 4591 | if (small_data_operand (x, GET_MODE (x))) |
8fbd2dc7 MM |
4592 | fprintf (file, "@%s(%s)", SMALL_DATA_RELOC, |
4593 | reg_names[SMALL_DATA_REG]); | |
9878760c RK |
4594 | } |
4595 | return; | |
9854d9ed | 4596 | |
9878760c | 4597 | case 'z': |
b4ac57ab RS |
4598 | /* X is a SYMBOL_REF. Write out the name preceded by a |
4599 | period and without any trailing data in brackets. Used for function | |
4d30c363 MM |
4600 | names. If we are configured for System V (or the embedded ABI) on |
4601 | the PowerPC, do not emit the period, since those systems do not use | |
4602 | TOCs and the like. */ | |
9878760c RK |
4603 | if (GET_CODE (x) != SYMBOL_REF) |
4604 | abort (); | |
4605 | ||
b6c9286a MM |
4606 | if (XSTR (x, 0)[0] != '.') |
4607 | { | |
4608 | switch (DEFAULT_ABI) | |
4609 | { | |
4610 | default: | |
4611 | abort (); | |
4612 | ||
4613 | case ABI_AIX: | |
4614 | putc ('.', file); | |
4615 | break; | |
4616 | ||
4617 | case ABI_V4: | |
4618 | case ABI_AIX_NODESC: | |
c81bebd7 | 4619 | case ABI_SOLARIS: |
ee890fe2 | 4620 | case ABI_DARWIN: |
b6c9286a | 4621 | break; |
b6c9286a MM |
4622 | } |
4623 | } | |
9ebbca7d | 4624 | #if TARGET_AIX |
9878760c | 4625 | RS6000_OUTPUT_BASENAME (file, XSTR (x, 0)); |
9ebbca7d GK |
4626 | #else |
4627 | assemble_name (file, XSTR (x, 0)); | |
4628 | #endif | |
9878760c RK |
4629 | return; |
4630 | ||
9854d9ed RK |
4631 | case 'Z': |
4632 | /* Like 'L', for last word of TImode. */ | |
4633 | if (GET_CODE (x) == REG) | |
5ebfb2ba | 4634 | fprintf (file, "%s", reg_names[REGNO (x) + 3]); |
9854d9ed RK |
4635 | else if (GET_CODE (x) == MEM) |
4636 | { | |
4637 | if (GET_CODE (XEXP (x, 0)) == PRE_INC | |
4638 | || GET_CODE (XEXP (x, 0)) == PRE_DEC) | |
a54d04b7 | 4639 | output_address (plus_constant (XEXP (XEXP (x, 0), 0), 12)); |
9854d9ed | 4640 | else |
d7624dc0 | 4641 | output_address (XEXP (adjust_address_nv (x, SImode, 12), 0)); |
ba5e43aa | 4642 | if (small_data_operand (x, GET_MODE (x))) |
8fbd2dc7 MM |
4643 | fprintf (file, "@%s(%s)", SMALL_DATA_RELOC, |
4644 | reg_names[SMALL_DATA_REG]); | |
9854d9ed | 4645 | } |
5c23c401 | 4646 | return; |
9854d9ed | 4647 | |
9878760c RK |
4648 | case 0: |
4649 | if (GET_CODE (x) == REG) | |
4650 | fprintf (file, "%s", reg_names[REGNO (x)]); | |
4651 | else if (GET_CODE (x) == MEM) | |
4652 | { | |
4653 | /* We need to handle PRE_INC and PRE_DEC here, since we need to | |
4654 | know the width from the mode. */ | |
4655 | if (GET_CODE (XEXP (x, 0)) == PRE_INC) | |
79ba6d34 MM |
4656 | fprintf (file, "%d(%s)", GET_MODE_SIZE (GET_MODE (x)), |
4657 | reg_names[REGNO (XEXP (XEXP (x, 0), 0))]); | |
9878760c | 4658 | else if (GET_CODE (XEXP (x, 0)) == PRE_DEC) |
79ba6d34 MM |
4659 | fprintf (file, "%d(%s)", - GET_MODE_SIZE (GET_MODE (x)), |
4660 | reg_names[REGNO (XEXP (XEXP (x, 0), 0))]); | |
9878760c | 4661 | else |
a54d04b7 | 4662 | output_address (XEXP (x, 0)); |
9878760c RK |
4663 | } |
4664 | else | |
a54d04b7 | 4665 | output_addr_const (file, x); |
a85d226b | 4666 | return; |
9878760c RK |
4667 | |
4668 | default: | |
4669 | output_operand_lossage ("invalid %%xn code"); | |
4670 | } | |
4671 | } | |
4672 | \f | |
4673 | /* Print the address of an operand. */ | |
4674 | ||
4675 | void | |
4676 | print_operand_address (file, x) | |
4677 | FILE *file; | |
4678 | register rtx x; | |
4679 | { | |
4680 | if (GET_CODE (x) == REG) | |
4697a36c | 4681 | fprintf (file, "0(%s)", reg_names[ REGNO (x) ]); |
9ebbca7d GK |
4682 | else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST |
4683 | || GET_CODE (x) == LABEL_REF) | |
9878760c RK |
4684 | { |
4685 | output_addr_const (file, x); | |
ba5e43aa | 4686 | if (small_data_operand (x, GET_MODE (x))) |
8fbd2dc7 MM |
4687 | fprintf (file, "@%s(%s)", SMALL_DATA_RELOC, |
4688 | reg_names[SMALL_DATA_REG]); | |
9ebbca7d GK |
4689 | else if (TARGET_TOC) |
4690 | abort(); | |
9878760c RK |
4691 | } |
4692 | else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == REG) | |
4693 | { | |
4694 | if (REGNO (XEXP (x, 0)) == 0) | |
4697a36c MM |
4695 | fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 1)) ], |
4696 | reg_names[ REGNO (XEXP (x, 0)) ]); | |
9878760c | 4697 | else |
4697a36c MM |
4698 | fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 0)) ], |
4699 | reg_names[ REGNO (XEXP (x, 1)) ]); | |
9878760c RK |
4700 | } |
4701 | else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT) | |
5f59ecb7 DE |
4702 | { |
4703 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (XEXP (x, 1))); | |
4704 | fprintf (file, "(%s)", reg_names[ REGNO (XEXP (x, 0)) ]); | |
4705 | } | |
3cb999d8 DE |
4706 | #if TARGET_ELF |
4707 | else if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 0)) == REG | |
4708 | && CONSTANT_P (XEXP (x, 1))) | |
4697a36c MM |
4709 | { |
4710 | output_addr_const (file, XEXP (x, 1)); | |
4711 | fprintf (file, "@l(%s)", reg_names[ REGNO (XEXP (x, 0)) ]); | |
4712 | } | |
3cb999d8 | 4713 | #endif |
9ebbca7d GK |
4714 | else if (LEGITIMATE_CONSTANT_POOL_ADDRESS_P (x)) |
4715 | { | |
2bfcf297 | 4716 | if (TARGET_AIX && (!TARGET_ELF || !TARGET_MINIMAL_TOC)) |
9ebbca7d | 4717 | { |
2bfcf297 DB |
4718 | rtx contains_minus = XEXP (x, 1); |
4719 | rtx minus, symref; | |
4720 | const char *name; | |
9ebbca7d GK |
4721 | |
4722 | /* Find the (minus (sym) (toc)) buried in X, and temporarily | |
4723 | turn it into (sym) for output_addr_const. */ | |
4724 | while (GET_CODE (XEXP (contains_minus, 0)) != MINUS) | |
4725 | contains_minus = XEXP (contains_minus, 0); | |
4726 | ||
2bfcf297 DB |
4727 | minus = XEXP (contains_minus, 0); |
4728 | symref = XEXP (minus, 0); | |
4729 | XEXP (contains_minus, 0) = symref; | |
4730 | if (TARGET_ELF) | |
4731 | { | |
4732 | char *newname; | |
4733 | ||
4734 | name = XSTR (symref, 0); | |
4735 | newname = alloca (strlen (name) + sizeof ("@toc")); | |
4736 | strcpy (newname, name); | |
4737 | strcat (newname, "@toc"); | |
4738 | XSTR (symref, 0) = newname; | |
4739 | } | |
4740 | output_addr_const (file, XEXP (x, 1)); | |
4741 | if (TARGET_ELF) | |
4742 | XSTR (symref, 0) = name; | |
9ebbca7d GK |
4743 | XEXP (contains_minus, 0) = minus; |
4744 | } | |
4745 | else | |
4746 | output_addr_const (file, XEXP (x, 1)); | |
4747 | ||
4748 | fprintf (file, "(%s)", reg_names[REGNO (XEXP (x, 0))]); | |
4749 | } | |
9878760c RK |
4750 | else |
4751 | abort (); | |
4752 | } | |
4753 | \f | |
39a10a29 GK |
4754 | enum rtx_code |
4755 | rs6000_reverse_condition (mode, code) | |
4756 | enum machine_mode mode; | |
4757 | enum rtx_code code; | |
4758 | { | |
4759 | /* Reversal of FP compares takes care -- an ordered compare | |
4760 | becomes an unordered compare and vice versa. */ | |
4761 | if (mode == CCFPmode) | |
bab6226b | 4762 | return reverse_condition_maybe_unordered (code); |
39a10a29 | 4763 | else |
bab6226b | 4764 | return reverse_condition (code); |
39a10a29 GK |
4765 | } |
4766 | ||
4767 | ||
4768 | /* Generate a compare for CODE. Return a brand-new rtx that | |
4769 | represents the result of the compare. */ | |
4770 | static rtx | |
4771 | rs6000_generate_compare (code) | |
4772 | enum rtx_code code; | |
4773 | { | |
4774 | enum machine_mode comp_mode; | |
4775 | rtx compare_result; | |
4776 | ||
4777 | if (rs6000_compare_fp_p) | |
4778 | comp_mode = CCFPmode; | |
4779 | else if (code == GTU || code == LTU | |
4780 | || code == GEU || code == LEU) | |
4781 | comp_mode = CCUNSmode; | |
4782 | else | |
4783 | comp_mode = CCmode; | |
4784 | ||
4785 | /* First, the compare. */ | |
4786 | compare_result = gen_reg_rtx (comp_mode); | |
4787 | emit_insn (gen_rtx_SET (VOIDmode, compare_result, | |
4788 | gen_rtx_COMPARE (comp_mode, | |
4789 | rs6000_compare_op0, | |
4790 | rs6000_compare_op1))); | |
4791 | ||
ca5adc63 | 4792 | /* Some kinds of FP comparisons need an OR operation; |
de6c5979 | 4793 | except for flag_unsafe_math_optimizations we don't bother. */ |
39a10a29 | 4794 | if (rs6000_compare_fp_p |
de6c5979 | 4795 | && ! flag_unsafe_math_optimizations |
39a10a29 GK |
4796 | && (code == LE || code == GE |
4797 | || code == UNEQ || code == LTGT | |
4798 | || code == UNGT || code == UNLT)) | |
4799 | { | |
4800 | enum rtx_code or1, or2; | |
4801 | rtx or1_rtx, or2_rtx, compare2_rtx; | |
4802 | rtx or_result = gen_reg_rtx (CCEQmode); | |
4803 | ||
4804 | switch (code) | |
4805 | { | |
4806 | case LE: or1 = LT; or2 = EQ; break; | |
4807 | case GE: or1 = GT; or2 = EQ; break; | |
4808 | case UNEQ: or1 = UNORDERED; or2 = EQ; break; | |
4809 | case LTGT: or1 = LT; or2 = GT; break; | |
4810 | case UNGT: or1 = UNORDERED; or2 = GT; break; | |
4811 | case UNLT: or1 = UNORDERED; or2 = LT; break; | |
4812 | default: abort (); | |
4813 | } | |
4814 | validate_condition_mode (or1, comp_mode); | |
4815 | validate_condition_mode (or2, comp_mode); | |
4816 | or1_rtx = gen_rtx (or1, SImode, compare_result, const0_rtx); | |
4817 | or2_rtx = gen_rtx (or2, SImode, compare_result, const0_rtx); | |
4818 | compare2_rtx = gen_rtx_COMPARE (CCEQmode, | |
4819 | gen_rtx_IOR (SImode, or1_rtx, or2_rtx), | |
4820 | const_true_rtx); | |
4821 | emit_insn (gen_rtx_SET (VOIDmode, or_result, compare2_rtx)); | |
4822 | ||
4823 | compare_result = or_result; | |
4824 | code = EQ; | |
4825 | } | |
4826 | ||
4827 | validate_condition_mode (code, GET_MODE (compare_result)); | |
4828 | ||
4829 | return gen_rtx (code, VOIDmode, compare_result, const0_rtx); | |
4830 | } | |
4831 | ||
4832 | ||
4833 | /* Emit the RTL for an sCOND pattern. */ | |
4834 | ||
4835 | void | |
4836 | rs6000_emit_sCOND (code, result) | |
4837 | enum rtx_code code; | |
4838 | rtx result; | |
4839 | { | |
4840 | rtx condition_rtx; | |
4841 | enum machine_mode op_mode; | |
4842 | ||
4843 | condition_rtx = rs6000_generate_compare (code); | |
4844 | ||
4845 | op_mode = GET_MODE (rs6000_compare_op0); | |
4846 | if (op_mode == VOIDmode) | |
4847 | op_mode = GET_MODE (rs6000_compare_op1); | |
4848 | ||
4849 | if (TARGET_POWERPC64 && (op_mode == DImode || rs6000_compare_fp_p)) | |
4850 | { | |
4851 | PUT_MODE (condition_rtx, DImode); | |
4852 | convert_move (result, condition_rtx, 0); | |
4853 | } | |
4854 | else | |
4855 | { | |
4856 | PUT_MODE (condition_rtx, SImode); | |
4857 | emit_insn (gen_rtx_SET (VOIDmode, result, condition_rtx)); | |
4858 | } | |
4859 | } | |
4860 | ||
4861 | ||
4862 | /* Emit a branch of kind CODE to location LOC. */ | |
4863 | ||
4864 | void | |
4865 | rs6000_emit_cbranch (code, loc) | |
4866 | enum rtx_code code; | |
4867 | rtx loc; | |
4868 | { | |
4869 | rtx condition_rtx, loc_ref; | |
4870 | ||
4871 | condition_rtx = rs6000_generate_compare (code); | |
4872 | loc_ref = gen_rtx_LABEL_REF (VOIDmode, loc); | |
4873 | emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, | |
4874 | gen_rtx_IF_THEN_ELSE (VOIDmode, condition_rtx, | |
4875 | loc_ref, pc_rtx))); | |
4876 | } | |
4877 | ||
4878 | ||
12a4e8c5 GK |
4879 | /* Return the string to output a conditional branch to LABEL, which is |
4880 | the operand number of the label, or -1 if the branch is really a | |
4881 | conditional return. | |
4882 | ||
4883 | OP is the conditional expression. XEXP (OP, 0) is assumed to be a | |
4884 | condition code register and its mode specifies what kind of | |
4885 | comparison we made. | |
4886 | ||
4887 | REVERSED is non-zero if we should reverse the sense of the comparison. | |
4888 | ||
4889 | INSN is the insn. */ | |
4890 | ||
4891 | char * | |
4892 | output_cbranch (op, label, reversed, insn) | |
4893 | rtx op; | |
4894 | const char * label; | |
4895 | int reversed; | |
4896 | rtx insn; | |
4897 | { | |
4898 | static char string[64]; | |
4899 | enum rtx_code code = GET_CODE (op); | |
4900 | rtx cc_reg = XEXP (op, 0); | |
4901 | enum machine_mode mode = GET_MODE (cc_reg); | |
4902 | int cc_regno = REGNO (cc_reg) - CR0_REGNO; | |
39a10a29 | 4903 | int need_longbranch = label != NULL && get_attr_length (insn) == 8; |
12a4e8c5 GK |
4904 | int really_reversed = reversed ^ need_longbranch; |
4905 | char *s = string; | |
4906 | const char *ccode; | |
4907 | const char *pred; | |
4908 | rtx note; | |
4909 | ||
39a10a29 GK |
4910 | validate_condition_mode (code, mode); |
4911 | ||
4912 | /* Work out which way this really branches. We could use | |
4913 | reverse_condition_maybe_unordered here always but this | |
4914 | makes the resulting assembler clearer. */ | |
12a4e8c5 | 4915 | if (really_reversed) |
39a10a29 | 4916 | code = rs6000_reverse_condition (mode, code); |
12a4e8c5 | 4917 | |
39a10a29 | 4918 | switch (code) |
12a4e8c5 GK |
4919 | { |
4920 | /* Not all of these are actually distinct opcodes, but | |
4921 | we distinguish them for clarity of the resulting assembler. */ | |
50a0b056 GK |
4922 | case NE: case LTGT: |
4923 | ccode = "ne"; break; | |
4924 | case EQ: case UNEQ: | |
4925 | ccode = "eq"; break; | |
4926 | case GE: case GEU: | |
4927 | ccode = "ge"; break; | |
4928 | case GT: case GTU: case UNGT: | |
4929 | ccode = "gt"; break; | |
4930 | case LE: case LEU: | |
4931 | ccode = "le"; break; | |
4932 | case LT: case LTU: case UNLT: | |
4933 | ccode = "lt"; break; | |
12a4e8c5 GK |
4934 | case UNORDERED: ccode = "un"; break; |
4935 | case ORDERED: ccode = "nu"; break; | |
4936 | case UNGE: ccode = "nl"; break; | |
4937 | case UNLE: ccode = "ng"; break; | |
4938 | default: | |
4939 | abort(); | |
4940 | } | |
4941 | ||
94a54f47 GK |
4942 | /* Maybe we have a guess as to how likely the branch is. |
4943 | The old mnemonics don't have a way to specify this information. */ | |
12a4e8c5 GK |
4944 | note = find_reg_note (insn, REG_BR_PROB, NULL_RTX); |
4945 | if (note != NULL_RTX) | |
4946 | { | |
4947 | /* PROB is the difference from 50%. */ | |
4948 | int prob = INTVAL (XEXP (note, 0)) - REG_BR_PROB_BASE / 2; | |
4949 | ||
4950 | /* For branches that are very close to 50%, assume not-taken. */ | |
4951 | if (abs (prob) > REG_BR_PROB_BASE / 20 | |
4952 | && ((prob > 0) ^ need_longbranch)) | |
4953 | pred = "+"; | |
4954 | else | |
4955 | pred = "-"; | |
4956 | } | |
4957 | else | |
4958 | pred = ""; | |
4959 | ||
4960 | if (label == NULL) | |
94a54f47 | 4961 | s += sprintf (s, "{b%sr|b%slr%s} ", ccode, ccode, pred); |
12a4e8c5 | 4962 | else |
94a54f47 | 4963 | s += sprintf (s, "{b%s|b%s%s} ", ccode, ccode, pred); |
12a4e8c5 | 4964 | |
37c67319 GK |
4965 | /* We need to escape any '%' characters in the reg_names string. |
4966 | Assume they'd only be the first character... */ | |
4967 | if (reg_names[cc_regno + CR0_REGNO][0] == '%') | |
4968 | *s++ = '%'; | |
94a54f47 | 4969 | s += sprintf (s, "%s", reg_names[cc_regno + CR0_REGNO]); |
12a4e8c5 GK |
4970 | |
4971 | if (label != NULL) | |
4972 | { | |
4973 | /* If the branch distance was too far, we may have to use an | |
4974 | unconditional branch to go the distance. */ | |
4975 | if (need_longbranch) | |
33011c35 | 4976 | s += sprintf (s, ",%c$+8\n\tb %s", '%', label); |
12a4e8c5 GK |
4977 | else |
4978 | s += sprintf (s, ",%s", label); | |
4979 | } | |
4980 | ||
4981 | return string; | |
4982 | } | |
50a0b056 GK |
4983 | |
4984 | /* Emit a conditional move: move TRUE_COND to DEST if OP of the | |
4985 | operands of the last comparison is nonzero/true, FALSE_COND if it | |
4986 | is zero/false. Return 0 if the hardware has no such operation. */ | |
4987 | int | |
4988 | rs6000_emit_cmove (dest, op, true_cond, false_cond) | |
4989 | rtx dest; | |
4990 | rtx op; | |
4991 | rtx true_cond; | |
4992 | rtx false_cond; | |
4993 | { | |
4994 | enum rtx_code code = GET_CODE (op); | |
4995 | rtx op0 = rs6000_compare_op0; | |
4996 | rtx op1 = rs6000_compare_op1; | |
4997 | REAL_VALUE_TYPE c1; | |
4998 | enum machine_mode mode = GET_MODE (op0); | |
4999 | rtx temp; | |
5000 | ||
5001 | /* First, work out if the hardware can do this at all, or | |
5002 | if it's too slow... */ | |
5003 | /* If the comparison is an integer one, since we only have fsel | |
5004 | it'll be cheaper to use a branch. */ | |
5005 | if (! rs6000_compare_fp_p) | |
5006 | return 0; | |
5007 | ||
5008 | /* Eliminate half of the comparisons by switching operands, this | |
5009 | makes the remaining code simpler. */ | |
5010 | if (code == UNLT || code == UNGT || code == UNORDERED || code == NE | |
5011 | || code == LTGT || code == LT) | |
5012 | { | |
5013 | code = reverse_condition_maybe_unordered (code); | |
5014 | temp = true_cond; | |
5015 | true_cond = false_cond; | |
5016 | false_cond = temp; | |
5017 | } | |
5018 | ||
5019 | /* UNEQ and LTGT take four instructions for a comparison with zero, | |
5020 | it'll probably be faster to use a branch here too. */ | |
5021 | if (code == UNEQ) | |
5022 | return 0; | |
5023 | ||
5024 | if (GET_CODE (op1) == CONST_DOUBLE) | |
5025 | REAL_VALUE_FROM_CONST_DOUBLE (c1, op1); | |
5026 | ||
5027 | /* We're going to try to implement comparions by performing | |
5028 | a subtract, then comparing against zero. Unfortunately, | |
5029 | Inf - Inf is NaN which is not zero, and so if we don't | |
5030 | know that the the operand is finite and the comparison | |
5031 | would treat EQ different to UNORDERED, we can't do it. */ | |
5032 | if (! flag_unsafe_math_optimizations | |
5033 | && code != GT && code != UNGE | |
5034 | && (GET_CODE (op1) != CONST_DOUBLE || target_isinf (c1)) | |
5035 | /* Constructs of the form (a OP b ? a : b) are safe. */ | |
5036 | && ((! rtx_equal_p (op0, false_cond) && ! rtx_equal_p (op1, false_cond)) | |
5037 | || (! rtx_equal_p (op0, true_cond) | |
5038 | && ! rtx_equal_p (op1, true_cond)))) | |
5039 | return 0; | |
5040 | /* At this point we know we can use fsel. */ | |
5041 | ||
5042 | /* Reduce the comparison to a comparison against zero. */ | |
5043 | temp = gen_reg_rtx (mode); | |
5044 | emit_insn (gen_rtx_SET (VOIDmode, temp, | |
5045 | gen_rtx_MINUS (mode, op0, op1))); | |
5046 | op0 = temp; | |
5047 | op1 = CONST0_RTX (mode); | |
5048 | ||
5049 | /* If we don't care about NaNs we can reduce some of the comparisons | |
5050 | down to faster ones. */ | |
5051 | if (flag_unsafe_math_optimizations) | |
5052 | switch (code) | |
5053 | { | |
5054 | case GT: | |
5055 | code = LE; | |
5056 | temp = true_cond; | |
5057 | true_cond = false_cond; | |
5058 | false_cond = temp; | |
5059 | break; | |
5060 | case UNGE: | |
5061 | code = GE; | |
5062 | break; | |
5063 | case UNEQ: | |
5064 | code = EQ; | |
5065 | break; | |
5066 | default: | |
5067 | break; | |
5068 | } | |
5069 | ||
5070 | /* Now, reduce everything down to a GE. */ | |
5071 | switch (code) | |
5072 | { | |
5073 | case GE: | |
5074 | break; | |
5075 | ||
5076 | case LE: | |
5077 | temp = gen_reg_rtx (mode); | |
5078 | emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (mode, op0))); | |
5079 | op0 = temp; | |
5080 | break; | |
5081 | ||
5082 | case ORDERED: | |
5083 | temp = gen_reg_rtx (mode); | |
5084 | emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_ABS (mode, op0))); | |
5085 | op0 = temp; | |
5086 | break; | |
5087 | ||
5088 | case EQ: | |
5089 | temp = gen_reg_rtx (mode); | |
5090 | emit_insn (gen_rtx_SET (VOIDmode, temp, | |
5091 | gen_rtx_NEG (mode, | |
5092 | gen_rtx_ABS (mode, op0)))); | |
5093 | op0 = temp; | |
5094 | break; | |
5095 | ||
5096 | case UNGE: | |
5097 | temp = gen_reg_rtx (mode); | |
5098 | emit_insn (gen_rtx_SET (VOIDmode, temp, | |
5099 | gen_rtx_IF_THEN_ELSE (mode, | |
5100 | gen_rtx_GE (VOIDmode, | |
5101 | op0, op1), | |
5102 | true_cond, false_cond))); | |
5103 | false_cond = temp; | |
5104 | true_cond = false_cond; | |
5105 | ||
5106 | temp = gen_reg_rtx (mode); | |
5107 | emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (mode, op0))); | |
5108 | op0 = temp; | |
5109 | break; | |
5110 | ||
5111 | case GT: | |
5112 | temp = gen_reg_rtx (mode); | |
5113 | emit_insn (gen_rtx_SET (VOIDmode, temp, | |
5114 | gen_rtx_IF_THEN_ELSE (mode, | |
5115 | gen_rtx_GE (VOIDmode, | |
5116 | op0, op1), | |
5117 | true_cond, false_cond))); | |
5118 | true_cond = temp; | |
5119 | false_cond = true_cond; | |
5120 | ||
5121 | temp = gen_reg_rtx (mode); | |
5122 | emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (mode, op0))); | |
5123 | op0 = temp; | |
5124 | break; | |
5125 | ||
5126 | default: | |
5127 | abort (); | |
5128 | } | |
5129 | ||
5130 | emit_insn (gen_rtx_SET (VOIDmode, dest, | |
5131 | gen_rtx_IF_THEN_ELSE (mode, | |
5132 | gen_rtx_GE (VOIDmode, | |
5133 | op0, op1), | |
5134 | true_cond, false_cond))); | |
5135 | return 1; | |
5136 | } | |
5137 | ||
5138 | void | |
5139 | rs6000_emit_minmax (dest, code, op0, op1) | |
5140 | rtx dest; | |
5141 | enum rtx_code code; | |
5142 | rtx op0; | |
5143 | rtx op1; | |
5144 | { | |
5145 | enum machine_mode mode = GET_MODE (op0); | |
5146 | rtx target; | |
5147 | if (code == SMAX || code == UMAX) | |
5148 | target = emit_conditional_move (dest, GE, op0, op1, mode, | |
5149 | op0, op1, mode, 0); | |
5150 | else | |
5151 | target = emit_conditional_move (dest, GE, op0, op1, mode, | |
5152 | op1, op0, mode, 0); | |
5153 | if (target == NULL_RTX) | |
5154 | abort (); | |
5155 | if (target != dest) | |
5156 | emit_move_insn (dest, target); | |
5157 | } | |
12a4e8c5 | 5158 | \f |
9878760c RK |
5159 | /* This page contains routines that are used to determine what the function |
5160 | prologue and epilogue code will do and write them out. */ | |
5161 | ||
5162 | /* Return the first fixed-point register that is required to be saved. 32 if | |
5163 | none. */ | |
5164 | ||
5165 | int | |
5166 | first_reg_to_save () | |
5167 | { | |
5168 | int first_reg; | |
5169 | ||
5170 | /* Find lowest numbered live register. */ | |
5171 | for (first_reg = 13; first_reg <= 31; first_reg++) | |
a38d360d GK |
5172 | if (regs_ever_live[first_reg] |
5173 | && (! call_used_regs[first_reg] | |
5174 | || (first_reg == PIC_OFFSET_TABLE_REGNUM | |
ee890fe2 SS |
5175 | && (((DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) |
5176 | && flag_pic == 1) | |
5177 | || (DEFAULT_ABI == ABI_DARWIN | |
5178 | && flag_pic))))) | |
9878760c RK |
5179 | break; |
5180 | ||
b5253831 DE |
5181 | if (profile_flag) |
5182 | { | |
5183 | /* AIX must save/restore every register that contains a parameter | |
5184 | before/after the .__mcount call plus an additional register | |
5185 | for the static chain, if needed; use registers from 30 down to 22 | |
5186 | to do this. */ | |
ee890fe2 | 5187 | if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) |
b5253831 DE |
5188 | { |
5189 | int last_parm_reg, profile_first_reg; | |
5190 | ||
5191 | /* Figure out last used parameter register. The proper thing | |
5192 | to do is to walk incoming args of the function. A function | |
5193 | might have live parameter registers even if it has no | |
5194 | incoming args. */ | |
5195 | for (last_parm_reg = 10; | |
5196 | last_parm_reg > 2 && ! regs_ever_live [last_parm_reg]; | |
5197 | last_parm_reg--) | |
5198 | ; | |
5199 | ||
5200 | /* Calculate first reg for saving parameter registers | |
5201 | and static chain. | |
5202 | Skip reg 31 which may contain the frame pointer. */ | |
5203 | profile_first_reg = (33 - last_parm_reg | |
5204 | - (current_function_needs_context ? 1 : 0)); | |
ee890fe2 SS |
5205 | #if TARGET_MACHO |
5206 | /* Need to skip another reg to account for R31 being PICBASE | |
5207 | (when flag_pic is set) or R30 being used as the frame | |
5208 | pointer (when flag_pic is not set). */ | |
5209 | --profile_first_reg; | |
5210 | #endif | |
b5253831 DE |
5211 | /* Do not save frame pointer if no parameters needs to be saved. */ |
5212 | if (profile_first_reg == 31) | |
5213 | profile_first_reg = 32; | |
5214 | ||
5215 | if (first_reg > profile_first_reg) | |
5216 | first_reg = profile_first_reg; | |
5217 | } | |
e165f3f0 | 5218 | |
b5253831 DE |
5219 | /* SVR4 may need one register to preserve the static chain. */ |
5220 | else if (current_function_needs_context) | |
5221 | { | |
5222 | /* Skip reg 31 which may contain the frame pointer. */ | |
5223 | if (first_reg > 30) | |
5224 | first_reg = 30; | |
5225 | } | |
5226 | } | |
e165f3f0 | 5227 | |
ee890fe2 SS |
5228 | #if TARGET_MACHO |
5229 | if (flag_pic && current_function_uses_pic_offset_table && | |
5230 | (first_reg > PIC_OFFSET_TABLE_REGNUM)) | |
5231 | return PIC_OFFSET_TABLE_REGNUM; | |
5232 | #endif | |
5233 | ||
9878760c RK |
5234 | return first_reg; |
5235 | } | |
5236 | ||
5237 | /* Similar, for FP regs. */ | |
5238 | ||
5239 | int | |
5240 | first_fp_reg_to_save () | |
5241 | { | |
5242 | int first_reg; | |
5243 | ||
5244 | /* Find lowest numbered live register. */ | |
5245 | for (first_reg = 14 + 32; first_reg <= 63; first_reg++) | |
5246 | if (regs_ever_live[first_reg]) | |
5247 | break; | |
5248 | ||
5249 | return first_reg; | |
5250 | } | |
4697a36c MM |
5251 | \f |
5252 | /* Calculate the stack information for the current function. This is | |
5253 | complicated by having two separate calling sequences, the AIX calling | |
5254 | sequence and the V.4 calling sequence. | |
5255 | ||
ee890fe2 | 5256 | AIX (and Darwin/Mac OS) stack frames look like: |
a260abc9 | 5257 | 32-bit 64-bit |
4697a36c | 5258 | SP----> +---------------------------------------+ |
a260abc9 | 5259 | | back chain to caller | 0 0 |
4697a36c | 5260 | +---------------------------------------+ |
a260abc9 | 5261 | | saved CR | 4 8 (8-11) |
4697a36c | 5262 | +---------------------------------------+ |
a260abc9 | 5263 | | saved LR | 8 16 |
4697a36c | 5264 | +---------------------------------------+ |
a260abc9 | 5265 | | reserved for compilers | 12 24 |
4697a36c | 5266 | +---------------------------------------+ |
a260abc9 | 5267 | | reserved for binders | 16 32 |
4697a36c | 5268 | +---------------------------------------+ |
a260abc9 | 5269 | | saved TOC pointer | 20 40 |
4697a36c | 5270 | +---------------------------------------+ |
a260abc9 | 5271 | | Parameter save area (P) | 24 48 |
4697a36c | 5272 | +---------------------------------------+ |
a260abc9 | 5273 | | Alloca space (A) | 24+P etc. |
802a0058 | 5274 | +---------------------------------------+ |
a7df97e6 | 5275 | | Local variable space (L) | 24+P+A |
4697a36c | 5276 | +---------------------------------------+ |
a7df97e6 | 5277 | | Float/int conversion temporary (X) | 24+P+A+L |
4697a36c | 5278 | +---------------------------------------+ |
a7df97e6 | 5279 | | Save area for GP registers (G) | 24+P+A+X+L |
4697a36c | 5280 | +---------------------------------------+ |
a7df97e6 | 5281 | | Save area for FP registers (F) | 24+P+A+X+L+G |
4697a36c MM |
5282 | +---------------------------------------+ |
5283 | old SP->| back chain to caller's caller | | |
5284 | +---------------------------------------+ | |
5285 | ||
5376a30c KR |
5286 | The required alignment for AIX configurations is two words (i.e., 8 |
5287 | or 16 bytes). | |
5288 | ||
5289 | ||
4697a36c MM |
5290 | V.4 stack frames look like: |
5291 | ||
5292 | SP----> +---------------------------------------+ | |
5293 | | back chain to caller | 0 | |
5294 | +---------------------------------------+ | |
5eb387b8 | 5295 | | caller's saved LR | 4 |
4697a36c MM |
5296 | +---------------------------------------+ |
5297 | | Parameter save area (P) | 8 | |
5298 | +---------------------------------------+ | |
a7df97e6 MM |
5299 | | Alloca space (A) | 8+P |
5300 | +---------------------------------------+ | |
5301 | | Varargs save area (V) | 8+P+A | |
5302 | +---------------------------------------+ | |
5303 | | Local variable space (L) | 8+P+A+V | |
5304 | +---------------------------------------+ | |
5305 | | Float/int conversion temporary (X) | 8+P+A+V+L | |
4697a36c | 5306 | +---------------------------------------+ |
a7df97e6 MM |
5307 | | saved CR (C) | 8+P+A+V+L+X |
5308 | +---------------------------------------+ | |
5309 | | Save area for GP registers (G) | 8+P+A+V+L+X+C | |
5310 | +---------------------------------------+ | |
5311 | | Save area for FP registers (F) | 8+P+A+V+L+X+C+G | |
4697a36c MM |
5312 | +---------------------------------------+ |
5313 | old SP->| back chain to caller's caller | | |
5314 | +---------------------------------------+ | |
b6c9286a | 5315 | |
5376a30c KR |
5316 | The required alignment for V.4 is 16 bytes, or 8 bytes if -meabi is |
5317 | given. (But note below and in sysv4.h that we require only 8 and | |
5318 | may round up the size of our stack frame anyways. The historical | |
5319 | reason is early versions of powerpc-linux which didn't properly | |
5320 | align the stack at program startup. A happy side-effect is that | |
5321 | -mno-eabi libraries can be used with -meabi programs.) | |
5322 | ||
b6c9286a | 5323 | |
5376a30c KR |
5324 | The EABI configuration defaults to the V.4 layout, unless |
5325 | -mcall-aix is used, in which case the AIX layout is used. However, | |
5326 | the stack alignment requirements may differ. If -mno-eabi is not | |
5327 | given, the required stack alignment is 8 bytes; if -mno-eabi is | |
5328 | given, the required alignment is 16 bytes. (But see V.4 comment | |
5329 | above.) */ | |
4697a36c | 5330 | |
61b2fbe7 MM |
5331 | #ifndef ABI_STACK_BOUNDARY |
5332 | #define ABI_STACK_BOUNDARY STACK_BOUNDARY | |
5333 | #endif | |
5334 | ||
4697a36c MM |
5335 | rs6000_stack_t * |
5336 | rs6000_stack_info () | |
5337 | { | |
5338 | static rs6000_stack_t info, zero_info; | |
5339 | rs6000_stack_t *info_ptr = &info; | |
9ebbca7d | 5340 | int reg_size = TARGET_POWERPC64 ? 8 : 4; |
24d304eb | 5341 | enum rs6000_abi abi; |
83720594 | 5342 | int ehrd_size; |
b6c9286a | 5343 | int total_raw_size; |
4697a36c MM |
5344 | |
5345 | /* Zero all fields portably */ | |
5346 | info = zero_info; | |
5347 | ||
5348 | /* Select which calling sequence */ | |
b6c9286a | 5349 | info_ptr->abi = abi = DEFAULT_ABI; |
9878760c | 5350 | |
4697a36c MM |
5351 | /* Calculate which registers need to be saved & save area size */ |
5352 | info_ptr->first_gp_reg_save = first_reg_to_save (); | |
906fb125 GK |
5353 | /* Assume that we will have to save PIC_OFFSET_TABLE_REGNUM, |
5354 | even if it currently looks like we won't. */ | |
2bfcf297 DB |
5355 | if (((TARGET_TOC && TARGET_MINIMAL_TOC) |
5356 | || (flag_pic == 1 | |
5357 | && (abi == ABI_V4 || abi == ABI_SOLARIS)) | |
ee890fe2 SS |
5358 | || (flag_pic && |
5359 | abi == ABI_DARWIN)) | |
906fb125 GK |
5360 | && info_ptr->first_gp_reg_save > PIC_OFFSET_TABLE_REGNUM) |
5361 | info_ptr->gp_size = reg_size * (32 - PIC_OFFSET_TABLE_REGNUM); | |
5362 | else | |
5363 | info_ptr->gp_size = reg_size * (32 - info_ptr->first_gp_reg_save); | |
4697a36c MM |
5364 | |
5365 | info_ptr->first_fp_reg_save = first_fp_reg_to_save (); | |
5366 | info_ptr->fp_size = 8 * (64 - info_ptr->first_fp_reg_save); | |
5367 | ||
5368 | /* Does this function call anything? */ | |
71f123ca FS |
5369 | info_ptr->calls_p = (! current_function_is_leaf |
5370 | || cfun->machine->ra_needs_full_frame); | |
b6c9286a | 5371 | |
4697a36c | 5372 | /* Determine if we need to save the link register */ |
71f123ca | 5373 | if (rs6000_ra_ever_killed () |
38c1f2d7 | 5374 | || (DEFAULT_ABI == ABI_AIX && profile_flag) |
4697a36c MM |
5375 | #ifdef TARGET_RELOCATABLE |
5376 | || (TARGET_RELOCATABLE && (get_pool_size () != 0)) | |
5377 | #endif | |
5378 | || (info_ptr->first_fp_reg_save != 64 | |
5379 | && !FP_SAVE_INLINE (info_ptr->first_fp_reg_save)) | |
24d304eb | 5380 | || (abi == ABI_V4 && current_function_calls_alloca) |
c81bebd7 | 5381 | || (abi == ABI_SOLARIS && current_function_calls_alloca) |
ee890fe2 | 5382 | || (DEFAULT_ABI == ABI_DARWIN && flag_pic && current_function_uses_pic_offset_table) |
4697a36c MM |
5383 | || info_ptr->calls_p) |
5384 | { | |
5385 | info_ptr->lr_save_p = 1; | |
9ebbca7d | 5386 | regs_ever_live[LINK_REGISTER_REGNUM] = 1; |
4697a36c MM |
5387 | } |
5388 | ||
9ebbca7d GK |
5389 | /* Determine if we need to save the condition code registers. */ |
5390 | if (regs_ever_live[CR2_REGNO] | |
5391 | || regs_ever_live[CR3_REGNO] | |
5392 | || regs_ever_live[CR4_REGNO]) | |
4697a36c MM |
5393 | { |
5394 | info_ptr->cr_save_p = 1; | |
9ebbca7d | 5395 | if (abi == ABI_V4 || abi == ABI_SOLARIS) |
4697a36c MM |
5396 | info_ptr->cr_size = reg_size; |
5397 | } | |
5398 | ||
83720594 RH |
5399 | /* If the current function calls __builtin_eh_return, then we need |
5400 | to allocate stack space for registers that will hold data for | |
5401 | the exception handler. */ | |
5402 | if (current_function_calls_eh_return) | |
5403 | { | |
5404 | unsigned int i; | |
5405 | for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; ++i) | |
5406 | continue; | |
5407 | ehrd_size = i * UNITS_PER_WORD; | |
5408 | } | |
5409 | else | |
5410 | ehrd_size = 0; | |
5411 | ||
4697a36c MM |
5412 | /* Determine various sizes */ |
5413 | info_ptr->reg_size = reg_size; | |
5414 | info_ptr->fixed_size = RS6000_SAVE_AREA; | |
5415 | info_ptr->varargs_size = RS6000_VARARGS_AREA; | |
189e03e3 DE |
5416 | info_ptr->vars_size = RS6000_ALIGN (get_frame_size (), 8); |
5417 | info_ptr->parm_size = RS6000_ALIGN (current_function_outgoing_args_size, 8); | |
189e03e3 | 5418 | info_ptr->save_size = RS6000_ALIGN (info_ptr->fp_size |
b6c9286a | 5419 | + info_ptr->gp_size |
83720594 | 5420 | + ehrd_size |
b6c9286a MM |
5421 | + info_ptr->cr_size |
5422 | + info_ptr->lr_size | |
9ebbca7d | 5423 | + info_ptr->toc_size, 8); |
ee890fe2 SS |
5424 | if (DEFAULT_ABI == ABI_DARWIN) |
5425 | info_ptr->save_size = RS6000_ALIGN (info_ptr->save_size, 16); | |
b6c9286a | 5426 | |
4697a36c | 5427 | /* Calculate the offsets */ |
24d304eb | 5428 | switch (abi) |
4697a36c | 5429 | { |
b6c9286a | 5430 | case ABI_NONE: |
24d304eb | 5431 | default: |
b6c9286a MM |
5432 | abort (); |
5433 | ||
5434 | case ABI_AIX: | |
5435 | case ABI_AIX_NODESC: | |
ee890fe2 | 5436 | case ABI_DARWIN: |
b6c9286a MM |
5437 | info_ptr->fp_save_offset = - info_ptr->fp_size; |
5438 | info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size; | |
83720594 | 5439 | info_ptr->ehrd_offset = info_ptr->gp_save_offset - ehrd_size; |
a260abc9 DE |
5440 | info_ptr->cr_save_offset = reg_size; /* first word when 64-bit. */ |
5441 | info_ptr->lr_save_offset = 2*reg_size; | |
24d304eb RK |
5442 | break; |
5443 | ||
5444 | case ABI_V4: | |
c81bebd7 | 5445 | case ABI_SOLARIS: |
b6c9286a MM |
5446 | info_ptr->fp_save_offset = - info_ptr->fp_size; |
5447 | info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size; | |
a7df97e6 MM |
5448 | info_ptr->cr_save_offset = info_ptr->gp_save_offset - info_ptr->cr_size; |
5449 | info_ptr->toc_save_offset = info_ptr->cr_save_offset - info_ptr->toc_size; | |
83720594 | 5450 | info_ptr->ehrd_offset = info_ptr->toc_save_offset - ehrd_size; |
b6c9286a MM |
5451 | info_ptr->lr_save_offset = reg_size; |
5452 | break; | |
4697a36c MM |
5453 | } |
5454 | ||
ff381587 MM |
5455 | total_raw_size = (info_ptr->vars_size |
5456 | + info_ptr->parm_size | |
ff381587 MM |
5457 | + info_ptr->save_size |
5458 | + info_ptr->varargs_size | |
5459 | + info_ptr->fixed_size); | |
5460 | ||
5461 | info_ptr->total_size = RS6000_ALIGN (total_raw_size, ABI_STACK_BOUNDARY / BITS_PER_UNIT); | |
5462 | ||
5463 | /* Determine if we need to allocate any stack frame: | |
5464 | ||
5465 | For AIX we need to push the stack if a frame pointer is needed (because | |
5466 | the stack might be dynamically adjusted), if we are debugging, if we | |
9ebbca7d | 5467 | make calls, or if the sum of fp_save, gp_save, and local variables |
ff381587 | 5468 | are more than the space needed to save all non-volatile registers: |
bfc79d3b | 5469 | 32-bit: 18*8 + 19*4 = 220 or 64-bit: 18*8 + 18*8 = 288 (GPR13 reserved). |
ff381587 MM |
5470 | |
5471 | For V.4 we don't have the stack cushion that AIX uses, but assume that | |
5472 | the debugger can handle stackless frames. */ | |
5473 | ||
5474 | if (info_ptr->calls_p) | |
5475 | info_ptr->push_p = 1; | |
5476 | ||
9ebbca7d | 5477 | else if (abi == ABI_V4 || abi == ABI_SOLARIS) |
ff381587 | 5478 | info_ptr->push_p = (total_raw_size > info_ptr->fixed_size |
9ebbca7d | 5479 | || info_ptr->calls_p); |
ff381587 MM |
5480 | |
5481 | else | |
5482 | info_ptr->push_p = (frame_pointer_needed | |
ee890fe2 | 5483 | || (abi != ABI_DARWIN && write_symbols != NO_DEBUG) |
ff381587 | 5484 | || ((total_raw_size - info_ptr->fixed_size) |
bfc79d3b | 5485 | > (TARGET_32BIT ? 220 : 288))); |
ff381587 | 5486 | |
4697a36c | 5487 | /* Zero offsets if we're not saving those registers */ |
8dda1a21 | 5488 | if (info_ptr->fp_size == 0) |
4697a36c MM |
5489 | info_ptr->fp_save_offset = 0; |
5490 | ||
8dda1a21 | 5491 | if (info_ptr->gp_size == 0) |
4697a36c MM |
5492 | info_ptr->gp_save_offset = 0; |
5493 | ||
c81fc13e | 5494 | if (! info_ptr->lr_save_p) |
4697a36c MM |
5495 | info_ptr->lr_save_offset = 0; |
5496 | ||
c81fc13e | 5497 | if (! info_ptr->cr_save_p) |
4697a36c MM |
5498 | info_ptr->cr_save_offset = 0; |
5499 | ||
c81fc13e | 5500 | if (! info_ptr->toc_save_p) |
b6c9286a MM |
5501 | info_ptr->toc_save_offset = 0; |
5502 | ||
4697a36c MM |
5503 | return info_ptr; |
5504 | } | |
5505 | ||
5506 | void | |
5507 | debug_stack_info (info) | |
5508 | rs6000_stack_t *info; | |
9878760c | 5509 | { |
d330fd93 | 5510 | const char *abi_string; |
24d304eb | 5511 | |
c81fc13e | 5512 | if (! info) |
4697a36c MM |
5513 | info = rs6000_stack_info (); |
5514 | ||
5515 | fprintf (stderr, "\nStack information for function %s:\n", | |
5516 | ((current_function_decl && DECL_NAME (current_function_decl)) | |
5517 | ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl)) | |
5518 | : "<unknown>")); | |
5519 | ||
24d304eb RK |
5520 | switch (info->abi) |
5521 | { | |
b6c9286a MM |
5522 | default: abi_string = "Unknown"; break; |
5523 | case ABI_NONE: abi_string = "NONE"; break; | |
5524 | case ABI_AIX: abi_string = "AIX"; break; | |
5525 | case ABI_AIX_NODESC: abi_string = "AIX"; break; | |
ee890fe2 | 5526 | case ABI_DARWIN: abi_string = "Darwin"; break; |
b6c9286a | 5527 | case ABI_V4: abi_string = "V.4"; break; |
c81bebd7 | 5528 | case ABI_SOLARIS: abi_string = "Solaris"; break; |
24d304eb RK |
5529 | } |
5530 | ||
5531 | fprintf (stderr, "\tABI = %5s\n", abi_string); | |
5532 | ||
4697a36c MM |
5533 | if (info->first_gp_reg_save != 32) |
5534 | fprintf (stderr, "\tfirst_gp_reg_save = %5d\n", info->first_gp_reg_save); | |
5535 | ||
5536 | if (info->first_fp_reg_save != 64) | |
5537 | fprintf (stderr, "\tfirst_fp_reg_save = %5d\n", info->first_fp_reg_save); | |
9878760c | 5538 | |
4697a36c MM |
5539 | if (info->lr_save_p) |
5540 | fprintf (stderr, "\tlr_save_p = %5d\n", info->lr_save_p); | |
9878760c | 5541 | |
4697a36c MM |
5542 | if (info->cr_save_p) |
5543 | fprintf (stderr, "\tcr_save_p = %5d\n", info->cr_save_p); | |
5544 | ||
b6c9286a MM |
5545 | if (info->toc_save_p) |
5546 | fprintf (stderr, "\ttoc_save_p = %5d\n", info->toc_save_p); | |
5547 | ||
4697a36c MM |
5548 | if (info->push_p) |
5549 | fprintf (stderr, "\tpush_p = %5d\n", info->push_p); | |
5550 | ||
5551 | if (info->calls_p) | |
5552 | fprintf (stderr, "\tcalls_p = %5d\n", info->calls_p); | |
5553 | ||
4697a36c MM |
5554 | if (info->gp_save_offset) |
5555 | fprintf (stderr, "\tgp_save_offset = %5d\n", info->gp_save_offset); | |
5556 | ||
5557 | if (info->fp_save_offset) | |
5558 | fprintf (stderr, "\tfp_save_offset = %5d\n", info->fp_save_offset); | |
5559 | ||
5560 | if (info->lr_save_offset) | |
5561 | fprintf (stderr, "\tlr_save_offset = %5d\n", info->lr_save_offset); | |
5562 | ||
5563 | if (info->cr_save_offset) | |
5564 | fprintf (stderr, "\tcr_save_offset = %5d\n", info->cr_save_offset); | |
5565 | ||
b6c9286a MM |
5566 | if (info->toc_save_offset) |
5567 | fprintf (stderr, "\ttoc_save_offset = %5d\n", info->toc_save_offset); | |
5568 | ||
4697a36c MM |
5569 | if (info->varargs_save_offset) |
5570 | fprintf (stderr, "\tvarargs_save_offset = %5d\n", info->varargs_save_offset); | |
5571 | ||
5572 | if (info->total_size) | |
5573 | fprintf (stderr, "\ttotal_size = %5d\n", info->total_size); | |
5574 | ||
5575 | if (info->varargs_size) | |
5576 | fprintf (stderr, "\tvarargs_size = %5d\n", info->varargs_size); | |
5577 | ||
5578 | if (info->vars_size) | |
5579 | fprintf (stderr, "\tvars_size = %5d\n", info->vars_size); | |
5580 | ||
5581 | if (info->parm_size) | |
5582 | fprintf (stderr, "\tparm_size = %5d\n", info->parm_size); | |
5583 | ||
5584 | if (info->fixed_size) | |
5585 | fprintf (stderr, "\tfixed_size = %5d\n", info->fixed_size); | |
5586 | ||
5587 | if (info->gp_size) | |
5588 | fprintf (stderr, "\tgp_size = %5d\n", info->gp_size); | |
5589 | ||
5590 | if (info->fp_size) | |
5591 | fprintf (stderr, "\tfp_size = %5d\n", info->fp_size); | |
5592 | ||
b6c9286a MM |
5593 | if (info->lr_size) |
5594 | fprintf (stderr, "\tlr_size = %5d\n", info->cr_size); | |
5595 | ||
4697a36c MM |
5596 | if (info->cr_size) |
5597 | fprintf (stderr, "\tcr_size = %5d\n", info->cr_size); | |
5598 | ||
b6c9286a MM |
5599 | if (info->toc_size) |
5600 | fprintf (stderr, "\ttoc_size = %5d\n", info->toc_size); | |
5601 | ||
4697a36c MM |
5602 | if (info->save_size) |
5603 | fprintf (stderr, "\tsave_size = %5d\n", info->save_size); | |
5604 | ||
5605 | if (info->reg_size != 4) | |
5606 | fprintf (stderr, "\treg_size = %5d\n", info->reg_size); | |
5607 | ||
5608 | fprintf (stderr, "\n"); | |
9878760c | 5609 | } |
71f123ca FS |
5610 | |
5611 | rtx | |
5612 | rs6000_return_addr (count, frame) | |
5613 | int count; | |
5614 | rtx frame; | |
5615 | { | |
71f123ca FS |
5616 | /* Currently we don't optimize very well between prolog and body code and |
5617 | for PIC code the code can be actually quite bad, so don't try to be | |
5618 | too clever here. */ | |
3418dd3a FS |
5619 | if (count != 0 |
5620 | || flag_pic != 0 | |
5621 | || DEFAULT_ABI == ABI_AIX | |
5622 | || DEFAULT_ABI == ABI_AIX_NODESC) | |
71f123ca FS |
5623 | { |
5624 | cfun->machine->ra_needs_full_frame = 1; | |
5625 | return | |
5626 | gen_rtx_MEM (Pmode, | |
3418dd3a | 5627 | memory_address (Pmode, |
71f123ca FS |
5628 | plus_constant (copy_to_reg (gen_rtx_MEM (Pmode, |
5629 | memory_address (Pmode, frame))), | |
5630 | RETURN_ADDRESS_OFFSET))); | |
5631 | } | |
5632 | ||
9e2f7ec7 | 5633 | return get_hard_reg_initial_val (Pmode, LINK_REGISTER_REGNUM); |
71f123ca FS |
5634 | } |
5635 | ||
5636 | static int | |
5637 | rs6000_ra_ever_killed () | |
5638 | { | |
5639 | rtx top; | |
5640 | ||
5641 | #ifdef ASM_OUTPUT_MI_THUNK | |
5642 | if (current_function_is_thunk) | |
5643 | return 0; | |
5644 | #endif | |
9e2f7ec7 DD |
5645 | if (!has_hard_reg_initial_val (Pmode, LINK_REGISTER_REGNUM) |
5646 | || cfun->machine->ra_needs_full_frame) | |
71f123ca FS |
5647 | return regs_ever_live[LINK_REGISTER_REGNUM]; |
5648 | ||
5649 | push_topmost_sequence (); | |
5650 | top = get_insns (); | |
5651 | pop_topmost_sequence (); | |
5652 | ||
5653 | return reg_set_between_p (gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM), | |
5654 | top, NULL_RTX); | |
5655 | } | |
4697a36c | 5656 | \f |
8cd8f856 GK |
5657 | /* Add a REG_MAYBE_DEAD note to the insn. */ |
5658 | static void | |
5659 | rs6000_maybe_dead (insn) | |
5660 | rtx insn; | |
5661 | { | |
5662 | REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD, | |
5663 | const0_rtx, | |
5664 | REG_NOTES (insn)); | |
5665 | } | |
5666 | ||
9ebbca7d | 5667 | /* Emit instructions needed to load the TOC register. |
c7ca610e | 5668 | This is only needed when TARGET_TOC, TARGET_MINIMAL_TOC, and there is |
9ebbca7d | 5669 | a constant pool; or for SVR4 -fpic. */ |
c7ca610e RK |
5670 | |
5671 | void | |
9ebbca7d GK |
5672 | rs6000_emit_load_toc_table (fromprolog) |
5673 | int fromprolog; | |
c7ca610e | 5674 | { |
9ebbca7d GK |
5675 | rtx dest; |
5676 | dest = gen_rtx_REG (Pmode, PIC_OFFSET_TABLE_REGNUM); | |
c7ca610e | 5677 | |
2bfcf297 | 5678 | if (TARGET_ELF && DEFAULT_ABI != ABI_AIX) |
c7ca610e | 5679 | { |
9ebbca7d GK |
5680 | if ((DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) |
5681 | && flag_pic == 1) | |
38c1f2d7 | 5682 | { |
9ebbca7d GK |
5683 | rtx temp = (fromprolog |
5684 | ? gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM) | |
5685 | : gen_reg_rtx (Pmode)); | |
2bfcf297 | 5686 | rs6000_maybe_dead (emit_insn (gen_load_toc_v4_pic_si (temp))); |
8cd8f856 | 5687 | rs6000_maybe_dead (emit_move_insn (dest, temp)); |
38c1f2d7 | 5688 | } |
9ebbca7d GK |
5689 | else if (flag_pic == 2) |
5690 | { | |
5691 | char buf[30]; | |
5692 | rtx tempLR = (fromprolog | |
5693 | ? gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM) | |
5694 | : gen_reg_rtx (Pmode)); | |
5695 | rtx temp0 = (fromprolog | |
5696 | ? gen_rtx_REG (Pmode, 0) | |
5697 | : gen_reg_rtx (Pmode)); | |
5698 | rtx symF; | |
5699 | ||
5700 | /* possibly create the toc section */ | |
5701 | if (! toc_initialized) | |
5702 | { | |
5703 | toc_section (); | |
5704 | function_section (current_function_decl); | |
5705 | } | |
5706 | ||
5707 | if (fromprolog) | |
5708 | { | |
5709 | rtx symL; | |
5710 | ||
5711 | ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno); | |
a8a05998 | 5712 | symF = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); |
38c1f2d7 | 5713 | |
9ebbca7d | 5714 | ASM_GENERATE_INTERNAL_LABEL (buf, "LCL", rs6000_pic_labelno); |
a8a05998 | 5715 | symL = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); |
38c1f2d7 | 5716 | |
8cd8f856 GK |
5717 | rs6000_maybe_dead (emit_insn (gen_load_toc_v4_PIC_1 (tempLR, |
5718 | symF))); | |
5719 | rs6000_maybe_dead (emit_move_insn (dest, tempLR)); | |
5720 | rs6000_maybe_dead (emit_insn (gen_load_toc_v4_PIC_2 (temp0, dest, | |
5721 | symL, | |
5722 | symF))); | |
9ebbca7d GK |
5723 | } |
5724 | else | |
5725 | { | |
5726 | rtx tocsym; | |
5727 | static int reload_toc_labelno = 0; | |
5728 | ||
a8a05998 | 5729 | tocsym = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (toc_label_name)); |
38c1f2d7 | 5730 | |
9ebbca7d | 5731 | ASM_GENERATE_INTERNAL_LABEL (buf, "LCG", reload_toc_labelno++); |
a8a05998 | 5732 | symF = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); |
9ebbca7d | 5733 | |
8cd8f856 GK |
5734 | rs6000_maybe_dead (emit_insn (gen_load_toc_v4_PIC_1b (tempLR, |
5735 | symF, | |
5736 | tocsym))); | |
5737 | rs6000_maybe_dead (emit_move_insn (dest, tempLR)); | |
5738 | rs6000_maybe_dead (emit_move_insn (temp0, | |
5739 | gen_rtx_MEM (Pmode, dest))); | |
9ebbca7d | 5740 | } |
8cd8f856 | 5741 | rs6000_maybe_dead (emit_insn (gen_addsi3 (dest, temp0, dest))); |
9ebbca7d GK |
5742 | } |
5743 | else if (flag_pic == 0 && TARGET_MINIMAL_TOC) | |
5744 | { | |
5745 | /* This is for AIX code running in non-PIC ELF. */ | |
5746 | char buf[30]; | |
5747 | rtx realsym; | |
38c1f2d7 | 5748 | ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1); |
a8a05998 | 5749 | realsym = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); |
9ebbca7d | 5750 | |
8cd8f856 GK |
5751 | rs6000_maybe_dead (emit_insn (gen_elf_high (dest, realsym))); |
5752 | rs6000_maybe_dead (emit_insn (gen_elf_low (dest, dest, realsym))); | |
9ebbca7d GK |
5753 | } |
5754 | else | |
5755 | abort(); | |
5756 | } | |
5757 | else | |
5758 | { | |
5759 | if (TARGET_32BIT) | |
8cd8f856 | 5760 | rs6000_maybe_dead (emit_insn (gen_load_toc_aix_si (dest))); |
9ebbca7d | 5761 | else |
8cd8f856 | 5762 | rs6000_maybe_dead (emit_insn (gen_load_toc_aix_di (dest))); |
9ebbca7d GK |
5763 | } |
5764 | } | |
5765 | ||
5766 | int | |
5767 | get_TOC_alias_set () | |
5768 | { | |
5769 | static int set = -1; | |
5770 | if (set == -1) | |
5771 | set = new_alias_set (); | |
5772 | return set; | |
5773 | } | |
5774 | ||
5775 | /* This retuns nonzero if the current function uses the TOC. This is | |
5776 | determined by the presence of (unspec ... 7), which is generated by | |
5777 | the various load_toc_* patterns. */ | |
5778 | int | |
5779 | uses_TOC () | |
5780 | { | |
5781 | rtx insn; | |
38c1f2d7 | 5782 | |
9ebbca7d | 5783 | for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) |
2c3c49de | 5784 | if (INSN_P (insn)) |
9ebbca7d GK |
5785 | { |
5786 | rtx pat = PATTERN (insn); | |
5787 | int i; | |
5788 | ||
8cd8f856 | 5789 | if (GET_CODE (pat) == PARALLEL) |
9ebbca7d GK |
5790 | for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++) |
5791 | if (GET_CODE (XVECEXP (PATTERN (insn), 0, i)) == UNSPEC | |
5792 | && XINT (XVECEXP (PATTERN (insn), 0, i), 1) == 7) | |
5793 | return 1; | |
38c1f2d7 | 5794 | } |
9ebbca7d GK |
5795 | return 0; |
5796 | } | |
38c1f2d7 | 5797 | |
9ebbca7d GK |
5798 | rtx |
5799 | create_TOC_reference(symbol) | |
5800 | rtx symbol; | |
5801 | { | |
a8a05998 ZW |
5802 | return gen_rtx_PLUS (Pmode, |
5803 | gen_rtx_REG (Pmode, TOC_REGISTER), | |
5804 | gen_rtx_CONST (Pmode, | |
5805 | gen_rtx_MINUS (Pmode, symbol, | |
5806 | gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (toc_label_name))))); | |
9ebbca7d | 5807 | } |
38c1f2d7 | 5808 | |
9ebbca7d GK |
5809 | #if TARGET_AIX |
5810 | /* __throw will restore its own return address to be the same as the | |
5811 | return address of the function that the throw is being made to. | |
5812 | This is unfortunate, because we want to check the original | |
5813 | return address to see if we need to restore the TOC. | |
5814 | So we have to squirrel it away here. | |
5815 | This is used only in compiling __throw and __rethrow. | |
c7ca610e | 5816 | |
9ebbca7d GK |
5817 | Most of this code should be removed by CSE. */ |
5818 | static rtx insn_after_throw; | |
c7ca610e | 5819 | |
9ebbca7d GK |
5820 | /* This does the saving... */ |
5821 | void | |
5822 | rs6000_aix_emit_builtin_unwind_init () | |
5823 | { | |
5824 | rtx mem; | |
5825 | rtx stack_top = gen_reg_rtx (Pmode); | |
5826 | rtx opcode_addr = gen_reg_rtx (Pmode); | |
5827 | ||
5828 | insn_after_throw = gen_reg_rtx (SImode); | |
5829 | ||
5830 | mem = gen_rtx_MEM (Pmode, hard_frame_pointer_rtx); | |
5831 | emit_move_insn (stack_top, mem); | |
5832 | ||
5833 | mem = gen_rtx_MEM (Pmode, | |
5834 | gen_rtx_PLUS (Pmode, stack_top, | |
5835 | GEN_INT (2 * GET_MODE_SIZE (Pmode)))); | |
5836 | emit_move_insn (opcode_addr, mem); | |
5837 | emit_move_insn (insn_after_throw, gen_rtx_MEM (SImode, opcode_addr)); | |
c7ca610e RK |
5838 | } |
5839 | ||
9ebbca7d GK |
5840 | /* Emit insns to _restore_ the TOC register, at runtime (specifically in _eh.o). |
5841 | Only used on AIX. | |
5842 | ||
5843 | The idea is that on AIX, function calls look like this: | |
5844 | bl somefunction-trampoline | |
5845 | lwz r2,20(sp) | |
5846 | ||
5847 | and later, | |
5848 | somefunction-trampoline: | |
5849 | stw r2,20(sp) | |
5850 | ... load function address in the count register ... | |
5851 | bctr | |
5852 | or like this, if the linker determines that this is not a cross-module call | |
5853 | and so the TOC need not be restored: | |
5854 | bl somefunction | |
5855 | nop | |
5856 | or like this, if the compiler could determine that this is not a | |
5857 | cross-module call: | |
5858 | bl somefunction | |
5859 | now, the tricky bit here is that register 2 is saved and restored | |
5860 | by the _linker_, so we can't readily generate debugging information | |
5861 | for it. So we need to go back up the call chain looking at the | |
5862 | insns at return addresses to see which calls saved the TOC register | |
5863 | and so see where it gets restored from. | |
5864 | ||
5865 | Oh, and all this gets done in RTL inside the eh_epilogue pattern, | |
5866 | just before the actual epilogue. | |
5867 | ||
5868 | On the bright side, this incurs no space or time overhead unless an | |
5869 | exception is thrown, except for the extra code in libgcc.a. | |
5870 | ||
5871 | The parameter STACKSIZE is a register containing (at runtime) | |
5872 | the amount to be popped off the stack in addition to the stack frame | |
5873 | of this routine (which will be __throw or __rethrow, and so is | |
5874 | guaranteed to have a stack frame). */ | |
5875 | void | |
5876 | rs6000_emit_eh_toc_restore (stacksize) | |
5877 | rtx stacksize; | |
5878 | { | |
5879 | rtx top_of_stack; | |
5880 | rtx bottom_of_stack = gen_reg_rtx (Pmode); | |
5881 | rtx tocompare = gen_reg_rtx (SImode); | |
5882 | rtx opcode = gen_reg_rtx (SImode); | |
5883 | rtx opcode_addr = gen_reg_rtx (Pmode); | |
5884 | rtx mem; | |
5885 | rtx loop_start = gen_label_rtx (); | |
5886 | rtx no_toc_restore_needed = gen_label_rtx (); | |
5887 | rtx loop_exit = gen_label_rtx (); | |
5888 | ||
5889 | mem = gen_rtx_MEM (Pmode, hard_frame_pointer_rtx); | |
ba4828e0 | 5890 | set_mem_alias_set (mem, rs6000_sr_alias_set); |
9ebbca7d GK |
5891 | emit_move_insn (bottom_of_stack, mem); |
5892 | ||
5893 | top_of_stack = expand_binop (Pmode, add_optab, | |
5894 | bottom_of_stack, stacksize, | |
5895 | NULL_RTX, 1, OPTAB_WIDEN); | |
5896 | ||
5897 | emit_move_insn (tocompare, | |
5898 | GEN_INT (trunc_int_for_mode (TARGET_32BIT | |
5899 | ? 0x80410014 | |
5900 | : 0xE8410028, SImode))); | |
5901 | ||
5902 | if (insn_after_throw == NULL_RTX) | |
5903 | abort(); | |
5904 | emit_move_insn (opcode, insn_after_throw); | |
5905 | ||
6496a589 | 5906 | emit_note (NULL, NOTE_INSN_LOOP_BEG); |
9ebbca7d GK |
5907 | emit_label (loop_start); |
5908 | ||
5909 | do_compare_rtx_and_jump (opcode, tocompare, NE, 1, | |
5910 | SImode, NULL_RTX, 0, NULL_RTX, | |
5911 | no_toc_restore_needed); | |
5912 | ||
5913 | mem = gen_rtx_MEM (Pmode, | |
5914 | gen_rtx_PLUS (Pmode, bottom_of_stack, | |
5915 | GEN_INT (5 * GET_MODE_SIZE (Pmode)))); | |
5916 | emit_move_insn (gen_rtx_REG (Pmode, 2), mem); | |
5917 | ||
5918 | emit_label (no_toc_restore_needed); | |
5919 | do_compare_rtx_and_jump (top_of_stack, bottom_of_stack, EQ, 1, | |
5920 | Pmode, NULL_RTX, 0, NULL_RTX, | |
5921 | loop_exit); | |
5922 | ||
5923 | mem = gen_rtx_MEM (Pmode, bottom_of_stack); | |
ba4828e0 | 5924 | set_mem_alias_set (mem, rs6000_sr_alias_set); |
9ebbca7d GK |
5925 | emit_move_insn (bottom_of_stack, mem); |
5926 | ||
5927 | mem = gen_rtx_MEM (Pmode, | |
5928 | gen_rtx_PLUS (Pmode, bottom_of_stack, | |
5929 | GEN_INT (2 * GET_MODE_SIZE (Pmode)))); | |
5930 | emit_move_insn (opcode_addr, mem); | |
5931 | emit_move_insn (opcode, gen_rtx_MEM (SImode, opcode_addr)); | |
5932 | ||
6496a589 | 5933 | emit_note (NULL, NOTE_INSN_LOOP_CONT); |
9ebbca7d | 5934 | emit_jump (loop_start); |
6496a589 | 5935 | emit_note (NULL, NOTE_INSN_LOOP_END); |
9ebbca7d GK |
5936 | emit_label (loop_exit); |
5937 | } | |
5938 | #endif /* TARGET_AIX */ | |
38c1f2d7 | 5939 | \f |
ba4828e0 RK |
5940 | /* This ties together stack memory (MEM with an alias set of |
5941 | rs6000_sr_alias_set) and the change to the stack pointer. */ | |
5942 | ||
9ebbca7d GK |
5943 | static void |
5944 | rs6000_emit_stack_tie () | |
5945 | { | |
ba4828e0 RK |
5946 | rtx mem = gen_rtx_MEM (BLKmode, gen_rtx_REG (Pmode, STACK_POINTER_REGNUM)); |
5947 | ||
5948 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
9ebbca7d GK |
5949 | emit_insn (gen_stack_tie (mem)); |
5950 | } | |
38c1f2d7 | 5951 | |
9ebbca7d GK |
5952 | /* Emit the correct code for allocating stack space, as insns. |
5953 | If COPY_R12, make sure a copy of the old frame is left in r12. | |
5954 | The generated code may use hard register 0 as a temporary. */ | |
5955 | ||
5956 | static void | |
5957 | rs6000_emit_allocate_stack (size, copy_r12) | |
5958 | HOST_WIDE_INT size; | |
38c1f2d7 MM |
5959 | int copy_r12; |
5960 | { | |
9ebbca7d GK |
5961 | rtx insn; |
5962 | rtx stack_reg = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM); | |
5963 | rtx tmp_reg = gen_rtx_REG (Pmode, 0); | |
5964 | rtx todec = GEN_INT (-size); | |
a157febd GK |
5965 | |
5966 | if (current_function_limit_stack) | |
5967 | { | |
5968 | if (REG_P (stack_limit_rtx) | |
5969 | && REGNO (stack_limit_rtx) > 1 | |
5970 | && REGNO (stack_limit_rtx) <= 31) | |
5971 | { | |
9ebbca7d GK |
5972 | emit_insn (Pmode == SImode |
5973 | ? gen_addsi3 (tmp_reg, | |
5974 | stack_limit_rtx, | |
5975 | GEN_INT (size)) | |
5976 | : gen_adddi3 (tmp_reg, | |
5977 | stack_limit_rtx, | |
5978 | GEN_INT (size))); | |
5979 | ||
5980 | emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg, | |
5981 | const0_rtx)); | |
a157febd GK |
5982 | } |
5983 | else if (GET_CODE (stack_limit_rtx) == SYMBOL_REF | |
9ebbca7d | 5984 | && TARGET_32BIT |
a157febd GK |
5985 | && (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS)) |
5986 | { | |
9ebbca7d GK |
5987 | rtx toload = gen_rtx_CONST (VOIDmode, |
5988 | gen_rtx_PLUS (Pmode, | |
5989 | stack_limit_rtx, | |
5990 | GEN_INT (size))); | |
5991 | ||
5992 | emit_insn (gen_elf_high (tmp_reg, toload)); | |
5993 | emit_insn (gen_elf_low (tmp_reg, tmp_reg, toload)); | |
5994 | emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg, | |
5995 | const0_rtx)); | |
a157febd GK |
5996 | } |
5997 | else | |
5998 | warning ("stack limit expression is not supported"); | |
5999 | } | |
6000 | ||
9ebbca7d GK |
6001 | if (copy_r12 || ! TARGET_UPDATE) |
6002 | emit_move_insn (gen_rtx_REG (Pmode, 12), stack_reg); | |
6003 | ||
38c1f2d7 MM |
6004 | if (TARGET_UPDATE) |
6005 | { | |
9ebbca7d | 6006 | if (size > 32767) |
38c1f2d7 | 6007 | { |
9ebbca7d GK |
6008 | /* Need a note here so that try_split doesn't get confused. */ |
6009 | if (get_last_insn() == NULL_RTX) | |
6010 | emit_note (0, NOTE_INSN_DELETED); | |
6011 | insn = emit_move_insn (tmp_reg, todec); | |
6012 | try_split (PATTERN (insn), insn, 0); | |
6013 | todec = tmp_reg; | |
38c1f2d7 | 6014 | } |
9ebbca7d GK |
6015 | |
6016 | if (Pmode == SImode) | |
6017 | insn = emit_insn (gen_movsi_update (stack_reg, stack_reg, | |
6018 | todec, stack_reg)); | |
6019 | else | |
6020 | insn = emit_insn (gen_movdi_update (stack_reg, stack_reg, | |
6021 | todec, stack_reg)); | |
38c1f2d7 MM |
6022 | } |
6023 | else | |
6024 | { | |
9ebbca7d GK |
6025 | if (Pmode == SImode) |
6026 | insn = emit_insn (gen_addsi3 (stack_reg, stack_reg, todec)); | |
38c1f2d7 | 6027 | else |
9ebbca7d GK |
6028 | insn = emit_insn (gen_adddi3 (stack_reg, stack_reg, todec)); |
6029 | emit_move_insn (gen_rtx_MEM (Pmode, stack_reg), | |
6030 | gen_rtx_REG (Pmode, 12)); | |
6031 | } | |
6032 | ||
6033 | RTX_FRAME_RELATED_P (insn) = 1; | |
6034 | REG_NOTES (insn) = | |
6035 | gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, | |
6036 | gen_rtx_SET (VOIDmode, stack_reg, | |
6037 | gen_rtx_PLUS (Pmode, stack_reg, | |
6038 | GEN_INT (-size))), | |
6039 | REG_NOTES (insn)); | |
6040 | } | |
6041 | ||
6042 | /* Add to 'insn' a note which is PATTERN (INSN) but with REG replaced with | |
6043 | (plus:P (reg 1) VAL), and with REG2 replaced with RREG if REG2 is not | |
6044 | NULL. | |
6045 | It would be nice if dwarf2out_frame_debug_expr could deduce these | |
6046 | equivalences by itself so it wasn't necessary to hold its hand so much. */ | |
6047 | ||
6048 | static void | |
6049 | rs6000_frame_related (insn, reg, val, reg2, rreg) | |
6050 | rtx insn; | |
6051 | rtx reg; | |
6052 | HOST_WIDE_INT val; | |
6053 | rtx reg2; | |
6054 | rtx rreg; | |
6055 | { | |
6056 | rtx real, temp; | |
6057 | ||
6058 | real = copy_rtx (PATTERN (insn)); | |
6059 | ||
6060 | real = replace_rtx (real, reg, | |
6061 | gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode, | |
6062 | STACK_POINTER_REGNUM), | |
6063 | GEN_INT (val))); | |
6064 | ||
6065 | /* We expect that 'real' is either a SET or a PARALLEL containing | |
6066 | SETs (and possibly other stuff). In a PARALLEL, all the SETs | |
6067 | are important so they all have to be marked RTX_FRAME_RELATED_P. */ | |
6068 | ||
6069 | if (GET_CODE (real) == SET) | |
6070 | { | |
6071 | rtx set = real; | |
6072 | ||
6073 | temp = simplify_rtx (SET_SRC (set)); | |
6074 | if (temp) | |
6075 | SET_SRC (set) = temp; | |
6076 | temp = simplify_rtx (SET_DEST (set)); | |
6077 | if (temp) | |
6078 | SET_DEST (set) = temp; | |
6079 | if (GET_CODE (SET_DEST (set)) == MEM) | |
38c1f2d7 | 6080 | { |
9ebbca7d GK |
6081 | temp = simplify_rtx (XEXP (SET_DEST (set), 0)); |
6082 | if (temp) | |
6083 | XEXP (SET_DEST (set), 0) = temp; | |
38c1f2d7 | 6084 | } |
38c1f2d7 | 6085 | } |
9ebbca7d GK |
6086 | else if (GET_CODE (real) == PARALLEL) |
6087 | { | |
6088 | int i; | |
6089 | for (i = 0; i < XVECLEN (real, 0); i++) | |
6090 | if (GET_CODE (XVECEXP (real, 0, i)) == SET) | |
6091 | { | |
6092 | rtx set = XVECEXP (real, 0, i); | |
6093 | ||
6094 | temp = simplify_rtx (SET_SRC (set)); | |
6095 | if (temp) | |
6096 | SET_SRC (set) = temp; | |
6097 | temp = simplify_rtx (SET_DEST (set)); | |
6098 | if (temp) | |
6099 | SET_DEST (set) = temp; | |
6100 | if (GET_CODE (SET_DEST (set)) == MEM) | |
6101 | { | |
6102 | temp = simplify_rtx (XEXP (SET_DEST (set), 0)); | |
6103 | if (temp) | |
6104 | XEXP (SET_DEST (set), 0) = temp; | |
6105 | } | |
6106 | RTX_FRAME_RELATED_P (set) = 1; | |
6107 | } | |
6108 | } | |
6109 | else | |
6110 | abort(); | |
6111 | ||
6112 | if (reg2 != NULL_RTX) | |
6113 | real = replace_rtx (real, reg2, rreg); | |
6114 | ||
6115 | RTX_FRAME_RELATED_P (insn) = 1; | |
6116 | REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, | |
6117 | real, | |
6118 | REG_NOTES (insn)); | |
38c1f2d7 MM |
6119 | } |
6120 | ||
9ebbca7d GK |
6121 | /* Emit function prologue as insns. */ |
6122 | ||
9878760c | 6123 | void |
83720594 | 6124 | rs6000_emit_prologue () |
9878760c | 6125 | { |
4697a36c | 6126 | rs6000_stack_t *info = rs6000_stack_info (); |
9ebbca7d GK |
6127 | enum machine_mode reg_mode = TARGET_POWERPC64 ? DImode : SImode; |
6128 | int reg_size = TARGET_POWERPC64 ? 8 : 4; | |
6129 | rtx sp_reg_rtx = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM); | |
6130 | rtx frame_ptr_rtx = gen_rtx_REG (Pmode, 12); | |
6131 | rtx frame_reg_rtx = sp_reg_rtx; | |
6132 | rtx cr_save_rtx = NULL; | |
6133 | rtx insn; | |
6134 | int saving_FPRs_inline; | |
6135 | int using_store_multiple; | |
6136 | HOST_WIDE_INT sp_offset = 0; | |
6137 | ||
6138 | using_store_multiple = (TARGET_MULTIPLE && ! TARGET_POWERPC64 | |
6139 | && info->first_gp_reg_save < 31); | |
6140 | saving_FPRs_inline = (info->first_fp_reg_save == 64 | |
6141 | || FP_SAVE_INLINE (info->first_fp_reg_save)); | |
6142 | ||
6143 | /* For V.4, update stack before we do any saving and set back pointer. */ | |
6144 | if (info->push_p && (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS)) | |
6145 | { | |
6146 | if (info->total_size < 32767) | |
6147 | sp_offset = info->total_size; | |
6148 | else | |
6149 | frame_reg_rtx = frame_ptr_rtx; | |
6150 | rs6000_emit_allocate_stack (info->total_size, | |
6151 | (frame_reg_rtx != sp_reg_rtx | |
6152 | && (info->cr_save_p | |
6153 | || info->lr_save_p | |
6154 | || info->first_fp_reg_save < 64 | |
6155 | || info->first_gp_reg_save < 32 | |
6156 | ))); | |
6157 | if (frame_reg_rtx != sp_reg_rtx) | |
6158 | rs6000_emit_stack_tie (); | |
6159 | } | |
6160 | ||
6161 | /* If we use the link register, get it into r0. */ | |
6162 | if (info->lr_save_p) | |
71f123ca | 6163 | emit_move_insn (gen_rtx_REG (Pmode, 0), |
9ebbca7d GK |
6164 | gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)); |
6165 | ||
6166 | /* If we need to save CR, put it into r12. */ | |
6167 | if (info->cr_save_p && frame_reg_rtx != frame_ptr_rtx) | |
6168 | { | |
6169 | cr_save_rtx = gen_rtx_REG (SImode, 12); | |
6170 | emit_insn (gen_movesi_from_cr (cr_save_rtx)); | |
6171 | } | |
6172 | ||
6173 | /* Do any required saving of fpr's. If only one or two to save, do it | |
6174 | ourself. Otherwise, call function. */ | |
6175 | if (saving_FPRs_inline) | |
6176 | { | |
6177 | int i; | |
6178 | for (i = 0; i < 64 - info->first_fp_reg_save; i++) | |
6179 | if ((regs_ever_live[info->first_fp_reg_save+i] | |
6180 | && ! call_used_regs[info->first_fp_reg_save+i])) | |
6181 | { | |
6182 | rtx addr, reg, mem; | |
6183 | reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i); | |
6184 | addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
6185 | GEN_INT (info->fp_save_offset | |
6186 | + sp_offset | |
6187 | + 8*i)); | |
6188 | mem = gen_rtx_MEM (DFmode, addr); | |
ba4828e0 | 6189 | set_mem_alias_set (mem, rs6000_sr_alias_set); |
9ebbca7d GK |
6190 | |
6191 | insn = emit_move_insn (mem, reg); | |
6192 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, | |
6193 | NULL_RTX, NULL_RTX); | |
6194 | } | |
6195 | } | |
6196 | else if (info->first_fp_reg_save != 64) | |
6197 | { | |
6198 | int i; | |
6199 | char rname[30]; | |
520a57c8 | 6200 | const char *alloc_rname; |
9ebbca7d GK |
6201 | rtvec p; |
6202 | p = rtvec_alloc (2 + 64 - info->first_fp_reg_save); | |
6203 | ||
6204 | RTVEC_ELT (p, 0) = gen_rtx_CLOBBER (VOIDmode, | |
6205 | gen_rtx_REG (Pmode, | |
6206 | LINK_REGISTER_REGNUM)); | |
6207 | sprintf (rname, "%s%d%s", SAVE_FP_PREFIX, | |
6208 | info->first_fp_reg_save - 32, SAVE_FP_SUFFIX); | |
a8a05998 | 6209 | alloc_rname = ggc_strdup (rname); |
9ebbca7d GK |
6210 | RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode, |
6211 | gen_rtx_SYMBOL_REF (Pmode, | |
6212 | alloc_rname)); | |
6213 | for (i = 0; i < 64 - info->first_fp_reg_save; i++) | |
6214 | { | |
6215 | rtx addr, reg, mem; | |
6216 | reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i); | |
6217 | addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
6218 | GEN_INT (info->fp_save_offset | |
6219 | + sp_offset + 8*i)); | |
6220 | mem = gen_rtx_MEM (DFmode, addr); | |
ba4828e0 | 6221 | set_mem_alias_set (mem, rs6000_sr_alias_set); |
9ebbca7d GK |
6222 | |
6223 | RTVEC_ELT (p, i + 2) = gen_rtx_SET (VOIDmode, mem, reg); | |
6224 | } | |
6225 | insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p)); | |
6226 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, | |
6227 | NULL_RTX, NULL_RTX); | |
6228 | } | |
b6c9286a | 6229 | |
9ebbca7d GK |
6230 | /* Save GPRs. This is done as a PARALLEL if we are using |
6231 | the store-multiple instructions. */ | |
6232 | if (using_store_multiple) | |
b6c9286a | 6233 | { |
9ebbca7d GK |
6234 | rtvec p, dwarfp; |
6235 | int i; | |
6236 | p = rtvec_alloc (32 - info->first_gp_reg_save); | |
6237 | dwarfp = rtvec_alloc (32 - info->first_gp_reg_save); | |
6238 | for (i = 0; i < 32 - info->first_gp_reg_save; i++) | |
6239 | { | |
6240 | rtx addr, reg, mem; | |
6241 | reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i); | |
6242 | addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
6243 | GEN_INT (info->gp_save_offset | |
6244 | + sp_offset | |
6245 | + reg_size * i)); | |
6246 | mem = gen_rtx_MEM (reg_mode, addr); | |
ba4828e0 | 6247 | set_mem_alias_set (mem, rs6000_sr_alias_set); |
9ebbca7d GK |
6248 | |
6249 | RTVEC_ELT (p, i) = gen_rtx_SET (VOIDmode, mem, reg); | |
6250 | } | |
6251 | insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p)); | |
6252 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, | |
6253 | NULL_RTX, NULL_RTX); | |
b6c9286a MM |
6254 | } |
6255 | else | |
6256 | { | |
9ebbca7d GK |
6257 | int i; |
6258 | for (i = 0; i < 32 - info->first_gp_reg_save; i++) | |
6259 | if ((regs_ever_live[info->first_gp_reg_save+i] | |
6260 | && ! call_used_regs[info->first_gp_reg_save+i]) | |
6261 | || (i+info->first_gp_reg_save == PIC_OFFSET_TABLE_REGNUM | |
ee890fe2 SS |
6262 | && (((DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) |
6263 | && flag_pic == 1) | |
6264 | || (DEFAULT_ABI == ABI_DARWIN | |
6265 | && flag_pic)))) | |
9ebbca7d GK |
6266 | { |
6267 | rtx addr, reg, mem; | |
6268 | reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i); | |
6269 | addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
6270 | GEN_INT (info->gp_save_offset | |
6271 | + sp_offset | |
6272 | + reg_size * i)); | |
6273 | mem = gen_rtx_MEM (reg_mode, addr); | |
ba4828e0 | 6274 | set_mem_alias_set (mem, rs6000_sr_alias_set); |
9ebbca7d GK |
6275 | |
6276 | insn = emit_move_insn (mem, reg); | |
6277 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, | |
6278 | NULL_RTX, NULL_RTX); | |
6279 | } | |
6280 | } | |
6281 | ||
83720594 RH |
6282 | /* ??? There's no need to emit actual instructions here, but it's the |
6283 | easiest way to get the frame unwind information emitted. */ | |
6284 | if (current_function_calls_eh_return) | |
6285 | { | |
78e1b90d DE |
6286 | unsigned int i, regno; |
6287 | ||
83720594 RH |
6288 | for (i = 0; ; ++i) |
6289 | { | |
6290 | rtx addr, reg, mem; | |
6291 | ||
6292 | regno = EH_RETURN_DATA_REGNO (i); | |
6293 | if (regno == INVALID_REGNUM) | |
6294 | break; | |
6295 | ||
6296 | reg = gen_rtx_REG (reg_mode, regno); | |
6297 | addr = plus_constant (frame_reg_rtx, | |
78e1b90d DE |
6298 | info->ehrd_offset + sp_offset |
6299 | + reg_size * (int) i); | |
83720594 | 6300 | mem = gen_rtx_MEM (reg_mode, addr); |
ba4828e0 | 6301 | set_mem_alias_set (mem, rs6000_sr_alias_set); |
83720594 RH |
6302 | |
6303 | insn = emit_move_insn (mem, reg); | |
6304 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, | |
6305 | NULL_RTX, NULL_RTX); | |
6306 | } | |
6307 | } | |
6308 | ||
9ebbca7d GK |
6309 | /* Save lr if we used it. */ |
6310 | if (info->lr_save_p) | |
6311 | { | |
6312 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
6313 | GEN_INT (info->lr_save_offset + sp_offset)); | |
6314 | rtx reg = gen_rtx_REG (Pmode, 0); | |
6315 | rtx mem = gen_rtx_MEM (Pmode, addr); | |
6316 | /* This should not be of rs6000_sr_alias_set, because of | |
6317 | __builtin_return_address. */ | |
6318 | ||
6319 | insn = emit_move_insn (mem, reg); | |
6320 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, | |
6321 | reg, gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)); | |
6322 | } | |
6323 | ||
6324 | /* Save CR if we use any that must be preserved. */ | |
6325 | if (info->cr_save_p) | |
6326 | { | |
6327 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
6328 | GEN_INT (info->cr_save_offset + sp_offset)); | |
6329 | rtx mem = gen_rtx_MEM (SImode, addr); | |
ba4828e0 RK |
6330 | |
6331 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
9ebbca7d GK |
6332 | |
6333 | /* If r12 was used to hold the original sp, copy cr into r0 now | |
6334 | that it's free. */ | |
6335 | if (REGNO (frame_reg_rtx) == 12) | |
6336 | { | |
6337 | cr_save_rtx = gen_rtx_REG (SImode, 0); | |
6338 | emit_insn (gen_movesi_from_cr (cr_save_rtx)); | |
6339 | } | |
6340 | insn = emit_move_insn (mem, cr_save_rtx); | |
6341 | ||
6342 | /* Now, there's no way that dwarf2out_frame_debug_expr is going | |
6343 | to understand '(unspec:SI [(reg:CC 68) ...] 19)'. But that's | |
6344 | OK. All we have to do is specify that _one_ condition code | |
6345 | register is saved in this stack slot. The thrower's epilogue | |
6346 | will then restore all the call-saved registers. */ | |
6347 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, | |
6348 | cr_save_rtx, gen_rtx_REG (SImode, CR0_REGNO)); | |
6349 | } | |
6350 | ||
6351 | /* Update stack and set back pointer unless this is V.4, | |
6352 | for which it was done previously. */ | |
6353 | if (info->push_p && DEFAULT_ABI != ABI_V4 && DEFAULT_ABI != ABI_SOLARIS) | |
6354 | rs6000_emit_allocate_stack (info->total_size, FALSE); | |
6355 | ||
6356 | /* Set frame pointer, if needed. */ | |
6357 | if (frame_pointer_needed) | |
6358 | { | |
6359 | insn = emit_move_insn (gen_rtx_REG (reg_mode, FRAME_POINTER_REGNUM), | |
6360 | sp_reg_rtx); | |
6361 | RTX_FRAME_RELATED_P (insn) = 1; | |
b6c9286a | 6362 | } |
9878760c | 6363 | |
9ebbca7d GK |
6364 | /* If we are using PIC_OFFSET_TABLE_REGNUM, we need to set it up. */ |
6365 | if ((TARGET_TOC && TARGET_MINIMAL_TOC && get_pool_size () != 0) | |
6366 | || ((DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) | |
6367 | && flag_pic == 1 && regs_ever_live[PIC_OFFSET_TABLE_REGNUM])) | |
6368 | { | |
6369 | /* If emit_load_toc_table will use the link register, we need to save | |
6370 | it. We use R11 for this purpose because emit_load_toc_table | |
6371 | can use register 0. This allows us to use a plain 'blr' to return | |
6372 | from the procedure more often. */ | |
d5fa86ba GK |
6373 | int save_LR_around_toc_setup = (TARGET_ELF && flag_pic != 0 |
6374 | && ! info->lr_save_p | |
6375 | && EXIT_BLOCK_PTR->pred != NULL); | |
9ebbca7d GK |
6376 | if (save_LR_around_toc_setup) |
6377 | emit_move_insn (gen_rtx_REG (Pmode, 11), | |
6378 | gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)); | |
6379 | ||
6380 | rs6000_emit_load_toc_table (TRUE); | |
6381 | ||
6382 | if (save_LR_around_toc_setup) | |
6383 | emit_move_insn (gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM), | |
6384 | gen_rtx_REG (Pmode, 11)); | |
6385 | } | |
ee890fe2 SS |
6386 | |
6387 | if (DEFAULT_ABI == ABI_DARWIN | |
6388 | && flag_pic && current_function_uses_pic_offset_table) | |
6389 | { | |
6390 | rtx dest = gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM); | |
6391 | ||
6392 | rs6000_maybe_dead (emit_insn (gen_load_macho_picbase (dest))); | |
6393 | ||
6394 | rs6000_maybe_dead ( | |
6395 | emit_move_insn (gen_rtx_REG (Pmode, PIC_OFFSET_TABLE_REGNUM), | |
6396 | gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM))); | |
6397 | } | |
9ebbca7d GK |
6398 | } |
6399 | ||
6400 | ||
6401 | /* Write function prologue. */ | |
08c148a8 NB |
6402 | static void |
6403 | rs6000_output_function_prologue (file, size) | |
9ebbca7d | 6404 | FILE *file; |
08c148a8 | 6405 | HOST_WIDE_INT size ATTRIBUTE_UNUSED; |
9ebbca7d GK |
6406 | { |
6407 | rs6000_stack_t *info = rs6000_stack_info (); | |
6408 | ||
4697a36c MM |
6409 | if (TARGET_DEBUG_STACK) |
6410 | debug_stack_info (info); | |
9878760c RK |
6411 | |
6412 | /* Write .extern for any function we will call to save and restore fp | |
6413 | values. */ | |
b6c9286a | 6414 | if (info->first_fp_reg_save < 64 && !FP_SAVE_INLINE (info->first_fp_reg_save)) |
4d30c363 | 6415 | fprintf (file, "\t.extern %s%d%s\n\t.extern %s%d%s\n", |
4697a36c MM |
6416 | SAVE_FP_PREFIX, info->first_fp_reg_save - 32, SAVE_FP_SUFFIX, |
6417 | RESTORE_FP_PREFIX, info->first_fp_reg_save - 32, RESTORE_FP_SUFFIX); | |
9878760c | 6418 | |
c764f757 RK |
6419 | /* Write .extern for AIX common mode routines, if needed. */ |
6420 | if (! TARGET_POWER && ! TARGET_POWERPC && ! common_mode_defined) | |
6421 | { | |
f6709c70 JW |
6422 | fputs ("\t.extern __mulh\n", file); |
6423 | fputs ("\t.extern __mull\n", file); | |
6424 | fputs ("\t.extern __divss\n", file); | |
6425 | fputs ("\t.extern __divus\n", file); | |
6426 | fputs ("\t.extern __quoss\n", file); | |
6427 | fputs ("\t.extern __quous\n", file); | |
c764f757 RK |
6428 | common_mode_defined = 1; |
6429 | } | |
9878760c | 6430 | |
9ebbca7d | 6431 | if (! HAVE_prologue) |
979721f8 | 6432 | { |
9ebbca7d GK |
6433 | start_sequence (); |
6434 | ||
6435 | /* A NOTE_INSN_DELETED is supposed to be at the start | |
6436 | and end of the "toplevel" insn chain. */ | |
6437 | emit_note (0, NOTE_INSN_DELETED); | |
6438 | rs6000_emit_prologue (); | |
6439 | emit_note (0, NOTE_INSN_DELETED); | |
6440 | ||
6441 | if (TARGET_DEBUG_STACK) | |
6442 | debug_rtx_list (get_insns(), 100); | |
6443 | final (get_insns(), file, FALSE, FALSE); | |
6444 | end_sequence (); | |
979721f8 MM |
6445 | } |
6446 | ||
9ebbca7d GK |
6447 | rs6000_pic_labelno++; |
6448 | } | |
6449 | ||
6450 | /* Emit function epilogue as insns. | |
9878760c | 6451 | |
9ebbca7d GK |
6452 | At present, dwarf2out_frame_debug_expr doesn't understand |
6453 | register restores, so we don't bother setting RTX_FRAME_RELATED_P | |
6454 | anywhere in the epilogue. Most of the insns below would in any case | |
6455 | need special notes to explain where r11 is in relation to the stack. */ | |
9878760c | 6456 | |
9ebbca7d | 6457 | void |
83720594 | 6458 | rs6000_emit_epilogue (sibcall) |
9ebbca7d GK |
6459 | int sibcall; |
6460 | { | |
6461 | rs6000_stack_t *info; | |
6462 | int restoring_FPRs_inline; | |
6463 | int using_load_multiple; | |
6464 | int using_mfcr_multiple; | |
6465 | int use_backchain_to_restore_sp; | |
6466 | int sp_offset = 0; | |
6467 | rtx sp_reg_rtx = gen_rtx_REG (Pmode, 1); | |
6468 | rtx frame_reg_rtx = sp_reg_rtx; | |
6469 | enum machine_mode reg_mode = TARGET_POWERPC64 ? DImode : SImode; | |
6470 | int reg_size = TARGET_POWERPC64 ? 8 : 4; | |
6471 | int i; | |
6472 | ||
6473 | info = rs6000_stack_info (); | |
6474 | using_load_multiple = (TARGET_MULTIPLE && ! TARGET_POWERPC64 | |
6475 | && info->first_gp_reg_save < 31); | |
6476 | restoring_FPRs_inline = (sibcall | |
83720594 | 6477 | || current_function_calls_eh_return |
9ebbca7d GK |
6478 | || info->first_fp_reg_save == 64 |
6479 | || FP_SAVE_INLINE (info->first_fp_reg_save)); | |
6480 | use_backchain_to_restore_sp = (frame_pointer_needed | |
6481 | || current_function_calls_alloca | |
6482 | || info->total_size > 32767); | |
6483 | using_mfcr_multiple = (rs6000_cpu == PROCESSOR_PPC601 | |
6484 | || rs6000_cpu == PROCESSOR_PPC603 | |
6485 | || rs6000_cpu == PROCESSOR_PPC750 | |
6486 | || optimize_size); | |
6487 | ||
6488 | /* If we have a frame pointer, a call to alloca, or a large stack | |
6489 | frame, restore the old stack pointer using the backchain. Otherwise, | |
6490 | we know what size to update it with. */ | |
6491 | if (use_backchain_to_restore_sp) | |
bacbde18 | 6492 | { |
9ebbca7d GK |
6493 | /* Under V.4, don't reset the stack pointer until after we're done |
6494 | loading the saved registers. */ | |
6495 | if (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) | |
6496 | frame_reg_rtx = gen_rtx_REG (Pmode, 11); | |
4697a36c | 6497 | |
9ebbca7d GK |
6498 | emit_move_insn (frame_reg_rtx, |
6499 | gen_rtx_MEM (Pmode, sp_reg_rtx)); | |
6500 | ||
bacbde18 | 6501 | } |
9ebbca7d | 6502 | else if (info->push_p) |
85638c0d | 6503 | { |
9ebbca7d GK |
6504 | if (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) |
6505 | sp_offset = info->total_size; | |
6506 | else | |
6507 | { | |
6508 | emit_insn (TARGET_32BIT | |
6509 | ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx, | |
6510 | GEN_INT (info->total_size)) | |
6511 | : gen_adddi3 (sp_reg_rtx, sp_reg_rtx, | |
6512 | GEN_INT (info->total_size))); | |
6513 | } | |
85638c0d | 6514 | } |
9ebbca7d GK |
6515 | |
6516 | /* Get the old lr if we saved it. */ | |
6517 | if (info->lr_save_p) | |
b6c9286a | 6518 | { |
9ebbca7d GK |
6519 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, |
6520 | GEN_INT (info->lr_save_offset + sp_offset)); | |
6521 | rtx mem = gen_rtx_MEM (Pmode, addr); | |
ba4828e0 RK |
6522 | |
6523 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
b6c9286a | 6524 | |
9ebbca7d | 6525 | emit_move_insn (gen_rtx_REG (Pmode, 0), mem); |
b6c9286a | 6526 | } |
9ebbca7d GK |
6527 | |
6528 | /* Get the old cr if we saved it. */ | |
6529 | if (info->cr_save_p) | |
6530 | { | |
6531 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
6532 | GEN_INT (info->cr_save_offset + sp_offset)); | |
6533 | rtx mem = gen_rtx_MEM (SImode, addr); | |
ba4828e0 RK |
6534 | |
6535 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
b6c9286a | 6536 | |
9ebbca7d GK |
6537 | emit_move_insn (gen_rtx_REG (SImode, 12), mem); |
6538 | } | |
6539 | ||
6540 | /* Set LR here to try to overlap restores below. */ | |
4697a36c | 6541 | if (info->lr_save_p) |
9ebbca7d GK |
6542 | emit_move_insn (gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM), |
6543 | gen_rtx_REG (Pmode, 0)); | |
6544 | ||
83720594 RH |
6545 | /* Load exception handler data registers, if needed. */ |
6546 | if (current_function_calls_eh_return) | |
6547 | { | |
78e1b90d DE |
6548 | unsigned int i, regno; |
6549 | ||
83720594 RH |
6550 | for (i = 0; ; ++i) |
6551 | { | |
6552 | rtx addr, mem; | |
6553 | ||
6554 | regno = EH_RETURN_DATA_REGNO (i); | |
6555 | if (regno == INVALID_REGNUM) | |
6556 | break; | |
6557 | ||
6558 | addr = plus_constant (frame_reg_rtx, | |
78e1b90d DE |
6559 | info->ehrd_offset + sp_offset |
6560 | + reg_size * (int) i); | |
83720594 | 6561 | mem = gen_rtx_MEM (reg_mode, addr); |
ba4828e0 | 6562 | set_mem_alias_set (mem, rs6000_sr_alias_set); |
83720594 RH |
6563 | |
6564 | emit_move_insn (gen_rtx_REG (reg_mode, regno), mem); | |
6565 | } | |
6566 | } | |
9ebbca7d GK |
6567 | |
6568 | /* Restore GPRs. This is done as a PARALLEL if we are using | |
6569 | the load-multiple instructions. */ | |
6570 | if (using_load_multiple) | |
979721f8 | 6571 | { |
9ebbca7d GK |
6572 | rtvec p; |
6573 | p = rtvec_alloc (32 - info->first_gp_reg_save); | |
6574 | for (i = 0; i < 32 - info->first_gp_reg_save; i++) | |
979721f8 | 6575 | { |
9ebbca7d GK |
6576 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, |
6577 | GEN_INT (info->gp_save_offset | |
6578 | + sp_offset | |
6579 | + reg_size * i)); | |
6580 | rtx mem = gen_rtx_MEM (reg_mode, addr); | |
ba4828e0 RK |
6581 | |
6582 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
9ebbca7d GK |
6583 | |
6584 | RTVEC_ELT (p, i) = | |
6585 | gen_rtx_SET (VOIDmode, | |
6586 | gen_rtx_REG (reg_mode, info->first_gp_reg_save + i), | |
6587 | mem); | |
979721f8 | 6588 | } |
9ebbca7d | 6589 | emit_insn (gen_rtx_PARALLEL (VOIDmode, p)); |
979721f8 | 6590 | } |
9ebbca7d GK |
6591 | else |
6592 | for (i = 0; i < 32 - info->first_gp_reg_save; i++) | |
6593 | if ((regs_ever_live[info->first_gp_reg_save+i] | |
6594 | && ! call_used_regs[info->first_gp_reg_save+i]) | |
6595 | || (i+info->first_gp_reg_save == PIC_OFFSET_TABLE_REGNUM | |
ee890fe2 SS |
6596 | && (((DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) |
6597 | && flag_pic == 1) | |
6598 | || (DEFAULT_ABI == ABI_DARWIN | |
6599 | && flag_pic)))) | |
9ebbca7d GK |
6600 | { |
6601 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
6602 | GEN_INT (info->gp_save_offset | |
6603 | + sp_offset | |
6604 | + reg_size * i)); | |
6605 | rtx mem = gen_rtx_MEM (reg_mode, addr); | |
ba4828e0 RK |
6606 | |
6607 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
9ebbca7d GK |
6608 | |
6609 | emit_move_insn (gen_rtx_REG (reg_mode, | |
6610 | info->first_gp_reg_save + i), | |
6611 | mem); | |
6612 | } | |
9878760c | 6613 | |
9ebbca7d GK |
6614 | /* Restore fpr's if we need to do it without calling a function. */ |
6615 | if (restoring_FPRs_inline) | |
6616 | for (i = 0; i < 64 - info->first_fp_reg_save; i++) | |
6617 | if ((regs_ever_live[info->first_fp_reg_save+i] | |
6618 | && ! call_used_regs[info->first_fp_reg_save+i])) | |
6619 | { | |
6620 | rtx addr, mem; | |
6621 | addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
6622 | GEN_INT (info->fp_save_offset | |
6623 | + sp_offset | |
6624 | + 8*i)); | |
6625 | mem = gen_rtx_MEM (DFmode, addr); | |
ba4828e0 | 6626 | set_mem_alias_set (mem, rs6000_sr_alias_set); |
9ebbca7d GK |
6627 | |
6628 | emit_move_insn (gen_rtx_REG (DFmode, | |
6629 | info->first_fp_reg_save + i), | |
6630 | mem); | |
6631 | } | |
8d30c4ee | 6632 | |
9ebbca7d GK |
6633 | /* If we saved cr, restore it here. Just those that were used. */ |
6634 | if (info->cr_save_p) | |
979721f8 | 6635 | { |
9ebbca7d | 6636 | rtx r12_rtx = gen_rtx_REG (SImode, 12); |
e35b9579 | 6637 | int count = 0; |
9ebbca7d GK |
6638 | |
6639 | if (using_mfcr_multiple) | |
979721f8 | 6640 | { |
9ebbca7d GK |
6641 | for (i = 0; i < 8; i++) |
6642 | if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i]) | |
e35b9579 | 6643 | count++; |
9ebbca7d | 6644 | if (count == 0) |
e35b9579 GK |
6645 | abort (); |
6646 | } | |
6647 | ||
6648 | if (using_mfcr_multiple && count > 1) | |
6649 | { | |
6650 | rtvec p; | |
6651 | int ndx; | |
9ebbca7d | 6652 | |
e35b9579 | 6653 | p = rtvec_alloc (count); |
9ebbca7d | 6654 | |
e35b9579 | 6655 | ndx = 0; |
9ebbca7d GK |
6656 | for (i = 0; i < 8; i++) |
6657 | if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i]) | |
6658 | { | |
6659 | rtvec r = rtvec_alloc (2); | |
6660 | RTVEC_ELT (r, 0) = r12_rtx; | |
6661 | RTVEC_ELT (r, 1) = GEN_INT (1 << (7-i)); | |
e35b9579 | 6662 | RTVEC_ELT (p, ndx) = |
9ebbca7d GK |
6663 | gen_rtx_SET (VOIDmode, gen_rtx_REG (CCmode, CR0_REGNO+i), |
6664 | gen_rtx_UNSPEC (CCmode, r, 20)); | |
e35b9579 | 6665 | ndx++; |
9ebbca7d GK |
6666 | } |
6667 | emit_insn (gen_rtx_PARALLEL (VOIDmode, p)); | |
e35b9579 GK |
6668 | if (ndx != count) |
6669 | abort (); | |
979721f8 MM |
6670 | } |
6671 | else | |
9ebbca7d GK |
6672 | for (i = 0; i < 8; i++) |
6673 | if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i]) | |
979721f8 | 6674 | { |
9ebbca7d GK |
6675 | emit_insn (gen_movsi_to_cr_one (gen_rtx_REG (CCmode, |
6676 | CR0_REGNO+i), | |
6677 | r12_rtx)); | |
979721f8 | 6678 | } |
979721f8 MM |
6679 | } |
6680 | ||
9ebbca7d GK |
6681 | /* If this is V.4, unwind the stack pointer after all of the loads |
6682 | have been done. We need to emit a block here so that sched | |
6683 | doesn't decide to move the sp change before the register restores | |
6684 | (which may not have any obvious dependency on the stack). This | |
6685 | doesn't hurt performance, because there is no scheduling that can | |
6686 | be done after this point. */ | |
6687 | if (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) | |
b6c9286a | 6688 | { |
9ebbca7d GK |
6689 | if (frame_reg_rtx != sp_reg_rtx) |
6690 | rs6000_emit_stack_tie (); | |
b6c9286a | 6691 | |
9ebbca7d | 6692 | if (use_backchain_to_restore_sp) |
b6c9286a | 6693 | { |
9ebbca7d | 6694 | emit_move_insn (sp_reg_rtx, frame_reg_rtx); |
b6c9286a | 6695 | } |
9ebbca7d | 6696 | else if (sp_offset != 0) |
13f1623b | 6697 | { |
9ebbca7d GK |
6698 | emit_insn (Pmode == SImode |
6699 | ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx, | |
6700 | GEN_INT (sp_offset)) | |
6701 | : gen_adddi3 (sp_reg_rtx, sp_reg_rtx, | |
6702 | GEN_INT (sp_offset))); | |
13f1623b | 6703 | } |
9ebbca7d | 6704 | } |
b6c9286a | 6705 | |
83720594 RH |
6706 | if (current_function_calls_eh_return) |
6707 | { | |
6708 | rtx sa = EH_RETURN_STACKADJ_RTX; | |
6709 | emit_insn (Pmode == SImode | |
6710 | ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx, sa) | |
6711 | : gen_adddi3 (sp_reg_rtx, sp_reg_rtx, sa)); | |
6712 | } | |
6713 | ||
9ebbca7d GK |
6714 | if (!sibcall) |
6715 | { | |
6716 | rtvec p; | |
6717 | if (! restoring_FPRs_inline) | |
6718 | p = rtvec_alloc (3 + 64 - info->first_fp_reg_save); | |
6719 | else | |
6720 | p = rtvec_alloc (2); | |
b6c9286a | 6721 | |
e35b9579 GK |
6722 | RTVEC_ELT (p, 0) = gen_rtx_RETURN (VOIDmode); |
6723 | RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode, | |
9ebbca7d GK |
6724 | gen_rtx_REG (Pmode, |
6725 | LINK_REGISTER_REGNUM)); | |
9ebbca7d GK |
6726 | |
6727 | /* If we have to restore more than two FP registers, branch to the | |
6728 | restore function. It will return to our caller. */ | |
6729 | if (! restoring_FPRs_inline) | |
6730 | { | |
6731 | int i; | |
6732 | char rname[30]; | |
520a57c8 | 6733 | const char *alloc_rname; |
979721f8 | 6734 | |
9ebbca7d GK |
6735 | sprintf (rname, "%s%d%s", RESTORE_FP_PREFIX, |
6736 | info->first_fp_reg_save - 32, RESTORE_FP_SUFFIX); | |
a8a05998 | 6737 | alloc_rname = ggc_strdup (rname); |
9ebbca7d GK |
6738 | RTVEC_ELT (p, 2) = gen_rtx_USE (VOIDmode, |
6739 | gen_rtx_SYMBOL_REF (Pmode, | |
6740 | alloc_rname)); | |
b6c9286a | 6741 | |
9ebbca7d GK |
6742 | for (i = 0; i < 64 - info->first_fp_reg_save; i++) |
6743 | { | |
6744 | rtx addr, mem; | |
6745 | addr = gen_rtx_PLUS (Pmode, sp_reg_rtx, | |
6746 | GEN_INT (info->fp_save_offset + 8*i)); | |
6747 | mem = gen_rtx_MEM (DFmode, addr); | |
ba4828e0 | 6748 | set_mem_alias_set (mem, rs6000_sr_alias_set); |
9ebbca7d GK |
6749 | |
6750 | RTVEC_ELT (p, i+3) = | |
6751 | gen_rtx_SET (VOIDmode, | |
6752 | gen_rtx_REG (DFmode, info->first_fp_reg_save + i), | |
6753 | mem); | |
b6c9286a MM |
6754 | } |
6755 | } | |
9ebbca7d GK |
6756 | |
6757 | emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p)); | |
3daf36a4 | 6758 | } |
9878760c RK |
6759 | } |
6760 | ||
6761 | /* Write function epilogue. */ | |
6762 | ||
08c148a8 NB |
6763 | static void |
6764 | rs6000_output_function_epilogue (file, size) | |
9878760c | 6765 | FILE *file; |
08c148a8 | 6766 | HOST_WIDE_INT size ATTRIBUTE_UNUSED; |
9878760c | 6767 | { |
4697a36c | 6768 | rs6000_stack_t *info = rs6000_stack_info (); |
9878760c | 6769 | |
9ebbca7d | 6770 | if (! HAVE_epilogue) |
9878760c | 6771 | { |
9ebbca7d GK |
6772 | rtx insn = get_last_insn (); |
6773 | /* If the last insn was a BARRIER, we don't have to write anything except | |
6774 | the trace table. */ | |
6775 | if (GET_CODE (insn) == NOTE) | |
6776 | insn = prev_nonnote_insn (insn); | |
6777 | if (insn == 0 || GET_CODE (insn) != BARRIER) | |
4697a36c | 6778 | { |
9ebbca7d GK |
6779 | /* This is slightly ugly, but at least we don't have two |
6780 | copies of the epilogue-emitting code. */ | |
6781 | start_sequence (); | |
6782 | ||
6783 | /* A NOTE_INSN_DELETED is supposed to be at the start | |
6784 | and end of the "toplevel" insn chain. */ | |
6785 | emit_note (0, NOTE_INSN_DELETED); | |
6786 | rs6000_emit_epilogue (FALSE); | |
6787 | emit_note (0, NOTE_INSN_DELETED); | |
6788 | ||
6789 | if (TARGET_DEBUG_STACK) | |
6790 | debug_rtx_list (get_insns(), 100); | |
6791 | final (get_insns(), file, FALSE, FALSE); | |
6792 | end_sequence (); | |
4697a36c | 6793 | } |
9878760c | 6794 | } |
b4ac57ab | 6795 | |
9b30bae2 | 6796 | /* Output a traceback table here. See /usr/include/sys/debug.h for info |
314fc5a9 ILT |
6797 | on its format. |
6798 | ||
6799 | We don't output a traceback table if -finhibit-size-directive was | |
6800 | used. The documentation for -finhibit-size-directive reads | |
6801 | ``don't output a @code{.size} assembler directive, or anything | |
6802 | else that would cause trouble if the function is split in the | |
6803 | middle, and the two halves are placed at locations far apart in | |
6804 | memory.'' The traceback table has this property, since it | |
6805 | includes the offset from the start of the function to the | |
4d30c363 MM |
6806 | traceback table itself. |
6807 | ||
6808 | System V.4 Powerpc's (and the embedded ABI derived from it) use a | |
b6c9286a MM |
6809 | different traceback table. */ |
6810 | if (DEFAULT_ABI == ABI_AIX && ! flag_inhibit_size_directive) | |
9b30bae2 | 6811 | { |
3cce094d | 6812 | const char *fname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0); |
314fc5a9 ILT |
6813 | int fixed_parms, float_parms, parm_info; |
6814 | int i; | |
6815 | ||
b6c9286a MM |
6816 | while (*fname == '.') /* V.4 encodes . in the name */ |
6817 | fname++; | |
6818 | ||
314fc5a9 ILT |
6819 | /* Need label immediately before tbtab, so we can compute its offset |
6820 | from the function start. */ | |
6821 | if (*fname == '*') | |
6822 | ++fname; | |
6823 | ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT"); | |
6824 | ASM_OUTPUT_LABEL (file, fname); | |
6825 | ||
6826 | /* The .tbtab pseudo-op can only be used for the first eight | |
6827 | expressions, since it can't handle the possibly variable | |
6828 | length fields that follow. However, if you omit the optional | |
6829 | fields, the assembler outputs zeros for all optional fields | |
6830 | anyways, giving each variable length field is minimum length | |
6831 | (as defined in sys/debug.h). Thus we can not use the .tbtab | |
6832 | pseudo-op at all. */ | |
6833 | ||
6834 | /* An all-zero word flags the start of the tbtab, for debuggers | |
6835 | that have to find it by searching forward from the entry | |
6836 | point or from the current pc. */ | |
19d2d16f | 6837 | fputs ("\t.long 0\n", file); |
314fc5a9 ILT |
6838 | |
6839 | /* Tbtab format type. Use format type 0. */ | |
19d2d16f | 6840 | fputs ("\t.byte 0,", file); |
314fc5a9 ILT |
6841 | |
6842 | /* Language type. Unfortunately, there doesn't seem to be any | |
6843 | official way to get this info, so we use language_string. C | |
6844 | is 0. C++ is 9. No number defined for Obj-C, so use the | |
9517ead8 | 6845 | value for C for now. There is no official value for Java, |
6f573ff9 JL |
6846 | although IBM appears to be using 13. There is no official value |
6847 | for Chill, so we've choosen 44 pseudo-randomly. */ | |
314fc5a9 | 6848 | if (! strcmp (language_string, "GNU C") |
e2c953b6 | 6849 | || ! strcmp (language_string, "GNU Objective-C")) |
314fc5a9 ILT |
6850 | i = 0; |
6851 | else if (! strcmp (language_string, "GNU F77")) | |
6852 | i = 1; | |
6853 | else if (! strcmp (language_string, "GNU Ada")) | |
6854 | i = 3; | |
8b83775b | 6855 | else if (! strcmp (language_string, "GNU Pascal")) |
314fc5a9 ILT |
6856 | i = 2; |
6857 | else if (! strcmp (language_string, "GNU C++")) | |
6858 | i = 9; | |
9517ead8 AG |
6859 | else if (! strcmp (language_string, "GNU Java")) |
6860 | i = 13; | |
6f573ff9 JL |
6861 | else if (! strcmp (language_string, "GNU CHILL")) |
6862 | i = 44; | |
314fc5a9 ILT |
6863 | else |
6864 | abort (); | |
6865 | fprintf (file, "%d,", i); | |
6866 | ||
6867 | /* 8 single bit fields: global linkage (not set for C extern linkage, | |
6868 | apparently a PL/I convention?), out-of-line epilogue/prologue, offset | |
6869 | from start of procedure stored in tbtab, internal function, function | |
6870 | has controlled storage, function has no toc, function uses fp, | |
6871 | function logs/aborts fp operations. */ | |
6872 | /* Assume that fp operations are used if any fp reg must be saved. */ | |
4697a36c | 6873 | fprintf (file, "%d,", (1 << 5) | ((info->first_fp_reg_save != 64) << 1)); |
314fc5a9 ILT |
6874 | |
6875 | /* 6 bitfields: function is interrupt handler, name present in | |
6876 | proc table, function calls alloca, on condition directives | |
6877 | (controls stack walks, 3 bits), saves condition reg, saves | |
6878 | link reg. */ | |
6879 | /* The `function calls alloca' bit seems to be set whenever reg 31 is | |
6880 | set up as a frame pointer, even when there is no alloca call. */ | |
6881 | fprintf (file, "%d,", | |
6882 | ((1 << 6) | (frame_pointer_needed << 5) | |
4697a36c | 6883 | | (info->cr_save_p << 1) | (info->lr_save_p))); |
314fc5a9 ILT |
6884 | |
6885 | /* 3 bitfields: saves backchain, spare bit, number of fpr saved | |
6886 | (6 bits). */ | |
6887 | fprintf (file, "%d,", | |
4697a36c | 6888 | (info->push_p << 7) | (64 - info->first_fp_reg_save)); |
314fc5a9 ILT |
6889 | |
6890 | /* 2 bitfields: spare bits (2 bits), number of gpr saved (6 bits). */ | |
6891 | fprintf (file, "%d,", (32 - first_reg_to_save ())); | |
6892 | ||
6893 | { | |
6894 | /* Compute the parameter info from the function decl argument | |
6895 | list. */ | |
6896 | tree decl; | |
6897 | int next_parm_info_bit; | |
6898 | ||
6899 | next_parm_info_bit = 31; | |
6900 | parm_info = 0; | |
6901 | fixed_parms = 0; | |
6902 | float_parms = 0; | |
6903 | ||
6904 | for (decl = DECL_ARGUMENTS (current_function_decl); | |
6905 | decl; decl = TREE_CHAIN (decl)) | |
6906 | { | |
6907 | rtx parameter = DECL_INCOMING_RTL (decl); | |
6908 | enum machine_mode mode = GET_MODE (parameter); | |
6909 | ||
6910 | if (GET_CODE (parameter) == REG) | |
6911 | { | |
6912 | if (GET_MODE_CLASS (mode) == MODE_FLOAT) | |
6913 | { | |
6914 | int bits; | |
6915 | ||
6916 | float_parms++; | |
6917 | ||
6918 | if (mode == SFmode) | |
6919 | bits = 0x2; | |
6920 | else if (mode == DFmode) | |
6921 | bits = 0x3; | |
6922 | else | |
6923 | abort (); | |
6924 | ||
6925 | /* If only one bit will fit, don't or in this entry. */ | |
6926 | if (next_parm_info_bit > 0) | |
6927 | parm_info |= (bits << (next_parm_info_bit - 1)); | |
6928 | next_parm_info_bit -= 2; | |
6929 | } | |
6930 | else | |
6931 | { | |
6932 | fixed_parms += ((GET_MODE_SIZE (mode) | |
6933 | + (UNITS_PER_WORD - 1)) | |
6934 | / UNITS_PER_WORD); | |
6935 | next_parm_info_bit -= 1; | |
6936 | } | |
6937 | } | |
6938 | } | |
6939 | } | |
6940 | ||
6941 | /* Number of fixed point parameters. */ | |
6942 | /* This is actually the number of words of fixed point parameters; thus | |
6943 | an 8 byte struct counts as 2; and thus the maximum value is 8. */ | |
6944 | fprintf (file, "%d,", fixed_parms); | |
6945 | ||
6946 | /* 2 bitfields: number of floating point parameters (7 bits), parameters | |
6947 | all on stack. */ | |
6948 | /* This is actually the number of fp registers that hold parameters; | |
6949 | and thus the maximum value is 13. */ | |
6950 | /* Set parameters on stack bit if parameters are not in their original | |
6951 | registers, regardless of whether they are on the stack? Xlc | |
6952 | seems to set the bit when not optimizing. */ | |
6953 | fprintf (file, "%d\n", ((float_parms << 1) | (! optimize))); | |
6954 | ||
6955 | /* Optional fields follow. Some are variable length. */ | |
6956 | ||
6957 | /* Parameter types, left adjusted bit fields: 0 fixed, 10 single float, | |
6958 | 11 double float. */ | |
6959 | /* There is an entry for each parameter in a register, in the order that | |
6960 | they occur in the parameter list. Any intervening arguments on the | |
6961 | stack are ignored. If the list overflows a long (max possible length | |
6962 | 34 bits) then completely leave off all elements that don't fit. */ | |
6963 | /* Only emit this long if there was at least one parameter. */ | |
6964 | if (fixed_parms || float_parms) | |
6965 | fprintf (file, "\t.long %d\n", parm_info); | |
6966 | ||
6967 | /* Offset from start of code to tb table. */ | |
19d2d16f | 6968 | fputs ("\t.long ", file); |
314fc5a9 | 6969 | ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT"); |
9ebbca7d | 6970 | #if TARGET_AIX |
314fc5a9 | 6971 | RS6000_OUTPUT_BASENAME (file, fname); |
9ebbca7d GK |
6972 | #else |
6973 | assemble_name (file, fname); | |
6974 | #endif | |
19d2d16f | 6975 | fputs ("-.", file); |
9ebbca7d | 6976 | #if TARGET_AIX |
314fc5a9 | 6977 | RS6000_OUTPUT_BASENAME (file, fname); |
9ebbca7d GK |
6978 | #else |
6979 | assemble_name (file, fname); | |
6980 | #endif | |
19d2d16f | 6981 | putc ('\n', file); |
314fc5a9 ILT |
6982 | |
6983 | /* Interrupt handler mask. */ | |
6984 | /* Omit this long, since we never set the interrupt handler bit | |
6985 | above. */ | |
6986 | ||
6987 | /* Number of CTL (controlled storage) anchors. */ | |
6988 | /* Omit this long, since the has_ctl bit is never set above. */ | |
6989 | ||
6990 | /* Displacement into stack of each CTL anchor. */ | |
6991 | /* Omit this list of longs, because there are no CTL anchors. */ | |
6992 | ||
6993 | /* Length of function name. */ | |
296b8152 | 6994 | fprintf (file, "\t.short %d\n", (int) strlen (fname)); |
314fc5a9 ILT |
6995 | |
6996 | /* Function name. */ | |
6997 | assemble_string (fname, strlen (fname)); | |
6998 | ||
6999 | /* Register for alloca automatic storage; this is always reg 31. | |
7000 | Only emit this if the alloca bit was set above. */ | |
7001 | if (frame_pointer_needed) | |
19d2d16f | 7002 | fputs ("\t.byte 31\n", file); |
9b30bae2 | 7003 | } |
9878760c | 7004 | } |
17167fd8 MM |
7005 | \f |
7006 | /* A C compound statement that outputs the assembler code for a thunk function, | |
7007 | used to implement C++ virtual function calls with multiple inheritance. The | |
7008 | thunk acts as a wrapper around a virtual function, adjusting the implicit | |
7009 | object parameter before handing control off to the real function. | |
7010 | ||
7011 | First, emit code to add the integer DELTA to the location that contains the | |
7012 | incoming first argument. Assume that this argument contains a pointer, and | |
7013 | is the one used to pass the `this' pointer in C++. This is the incoming | |
7014 | argument *before* the function prologue, e.g. `%o0' on a sparc. The | |
7015 | addition must preserve the values of all other incoming arguments. | |
7016 | ||
7017 | After the addition, emit code to jump to FUNCTION, which is a | |
7018 | `FUNCTION_DECL'. This is a direct pure jump, not a call, and does not touch | |
7019 | the return address. Hence returning from FUNCTION will return to whoever | |
7020 | called the current `thunk'. | |
7021 | ||
7022 | The effect must be as if FUNCTION had been called directly with the adjusted | |
7023 | first argument. This macro is responsible for emitting all of the code for | |
08c148a8 NB |
7024 | a thunk function; output_function_prologue() and output_function_epilogue() |
7025 | are not invoked. | |
17167fd8 MM |
7026 | |
7027 | The THUNK_FNDECL is redundant. (DELTA and FUNCTION have already been | |
7028 | extracted from it.) It might possibly be useful on some targets, but | |
7029 | probably not. | |
7030 | ||
7031 | If you do not define this macro, the target-independent code in the C++ | |
7032 | frontend will generate a less efficient heavyweight thunk that calls | |
7033 | FUNCTION instead of jumping to it. The generic approach does not support | |
7034 | varargs. */ | |
7035 | ||
7036 | void | |
7037 | output_mi_thunk (file, thunk_fndecl, delta, function) | |
7038 | FILE *file; | |
d330fd93 | 7039 | tree thunk_fndecl ATTRIBUTE_UNUSED; |
17167fd8 MM |
7040 | int delta; |
7041 | tree function; | |
7042 | { | |
d330fd93 KG |
7043 | const char *this_reg = reg_names[ aggregate_value_p (TREE_TYPE (TREE_TYPE (function))) ? 4 : 3 ]; |
7044 | const char *prefix; | |
3cce094d | 7045 | const char *fname; |
d330fd93 | 7046 | const char *r0 = reg_names[0]; |
d330fd93 KG |
7047 | const char *toc = reg_names[2]; |
7048 | const char *schain = reg_names[11]; | |
7049 | const char *r12 = reg_names[12]; | |
17167fd8 MM |
7050 | char buf[512]; |
7051 | static int labelno = 0; | |
7052 | ||
7053 | /* Small constants that can be done by one add instruction */ | |
7054 | if (delta >= -32768 && delta <= 32767) | |
7055 | { | |
22b4a3b0 | 7056 | if (! TARGET_NEW_MNEMONICS) |
17167fd8 MM |
7057 | fprintf (file, "\tcal %s,%d(%s)\n", this_reg, delta, this_reg); |
7058 | else | |
7059 | fprintf (file, "\taddi %s,%s,%d\n", this_reg, this_reg, delta); | |
7060 | } | |
7061 | ||
7062 | /* Large constants that can be done by one addis instruction */ | |
7063 | else if ((delta & 0xffff) == 0 && num_insns_constant_wide (delta) == 1) | |
7064 | asm_fprintf (file, "\t{cau|addis} %s,%s,%d\n", this_reg, this_reg, | |
7065 | delta >> 16); | |
7066 | ||
7067 | /* 32-bit constants that can be done by an add and addis instruction. */ | |
7068 | else if (TARGET_32BIT || num_insns_constant_wide (delta) == 1) | |
7069 | { | |
22b4a3b0 | 7070 | /* Break into two pieces, propagating the sign bit from the low word to |
17167fd8 MM |
7071 | the upper word. */ |
7072 | int delta_high = delta >> 16; | |
7073 | int delta_low = delta & 0xffff; | |
7074 | if ((delta_low & 0x8000) != 0) | |
7075 | { | |
7076 | delta_high++; | |
7077 | delta_low = (delta_low ^ 0x8000) - 0x8000; /* sign extend */ | |
7078 | } | |
7079 | ||
7080 | asm_fprintf (file, "\t{cau|addis} %s,%s,%d\n", this_reg, this_reg, | |
7081 | delta_high); | |
7082 | ||
22b4a3b0 | 7083 | if (! TARGET_NEW_MNEMONICS) |
17167fd8 MM |
7084 | fprintf (file, "\tcal %s,%d(%s)\n", this_reg, delta_low, this_reg); |
7085 | else | |
7086 | fprintf (file, "\taddi %s,%s,%d\n", this_reg, this_reg, delta_low); | |
7087 | } | |
7088 | ||
7089 | /* 64-bit constants, fixme */ | |
7090 | else | |
7091 | abort (); | |
7092 | ||
7093 | /* Get the prefix in front of the names. */ | |
7094 | switch (DEFAULT_ABI) | |
7095 | { | |
7096 | default: | |
7097 | abort (); | |
7098 | ||
7099 | case ABI_AIX: | |
7100 | prefix = "."; | |
7101 | break; | |
7102 | ||
7103 | case ABI_V4: | |
7104 | case ABI_AIX_NODESC: | |
7105 | case ABI_SOLARIS: | |
7106 | prefix = ""; | |
7107 | break; | |
17167fd8 MM |
7108 | } |
7109 | ||
7110 | /* If the function is compiled in this module, jump to it directly. | |
7111 | Otherwise, load up its address and jump to it. */ | |
7112 | ||
7113 | fname = XSTR (XEXP (DECL_RTL (function), 0), 0); | |
42820a49 | 7114 | |
9ebbca7d | 7115 | if (current_file_function_operand (XEXP (DECL_RTL (function), 0), VOIDmode) |
22b4a3b0 FS |
7116 | && ! lookup_attribute ("longcall", |
7117 | TYPE_ATTRIBUTES (TREE_TYPE (function)))) | |
17167fd8 MM |
7118 | { |
7119 | fprintf (file, "\tb %s", prefix); | |
7120 | assemble_name (file, fname); | |
22b4a3b0 | 7121 | if (DEFAULT_ABI == ABI_V4 && flag_pic) fputs ("@local", file); |
949ea356 | 7122 | putc ('\n', file); |
17167fd8 MM |
7123 | } |
7124 | ||
7125 | else | |
7126 | { | |
7127 | switch (DEFAULT_ABI) | |
7128 | { | |
7129 | default: | |
17167fd8 MM |
7130 | abort (); |
7131 | ||
7132 | case ABI_AIX: | |
7133 | /* Set up a TOC entry for the function. */ | |
7134 | ASM_GENERATE_INTERNAL_LABEL (buf, "Lthunk", labelno); | |
7135 | toc_section (); | |
7136 | ASM_OUTPUT_INTERNAL_LABEL (file, "Lthunk", labelno); | |
7137 | labelno++; | |
7138 | ||
7139 | /* Note, MINIMAL_TOC doesn't make sense in the case of a thunk, since | |
7140 | there will be only one TOC entry for this function. */ | |
7141 | fputs ("\t.tc\t", file); | |
7142 | assemble_name (file, buf); | |
7143 | fputs ("[TC],", file); | |
7144 | assemble_name (file, buf); | |
7145 | putc ('\n', file); | |
7146 | text_section (); | |
7147 | asm_fprintf (file, (TARGET_32BIT) ? "\t{l|lwz} %s," : "\tld %s", r12); | |
7148 | assemble_name (file, buf); | |
7149 | asm_fprintf (file, "(%s)\n", reg_names[2]); | |
7150 | asm_fprintf (file, | |
7151 | (TARGET_32BIT) ? "\t{l|lwz} %s,0(%s)\n" : "\tld %s,0(%s)\n", | |
7152 | r0, r12); | |
7153 | ||
7154 | asm_fprintf (file, | |
7155 | (TARGET_32BIT) ? "\t{l|lwz} %s,4(%s)\n" : "\tld %s,8(%s)\n", | |
7156 | toc, r12); | |
7157 | ||
7158 | asm_fprintf (file, "\tmtctr %s\n", r0); | |
7159 | asm_fprintf (file, | |
7160 | (TARGET_32BIT) ? "\t{l|lwz} %s,8(%s)\n" : "\tld %s,16(%s)\n", | |
7161 | schain, r12); | |
7162 | ||
7163 | asm_fprintf (file, "\tbctr\n"); | |
7164 | break; | |
7165 | ||
9ebbca7d GK |
7166 | case ABI_AIX_NODESC: |
7167 | case ABI_SOLARIS: | |
17167fd8 | 7168 | case ABI_V4: |
22b4a3b0 FS |
7169 | fprintf (file, "\tb %s", prefix); |
7170 | assemble_name (file, fname); | |
7171 | if (flag_pic) fputs ("@plt", file); | |
949ea356 | 7172 | putc ('\n', file); |
22b4a3b0 | 7173 | break; |
ee890fe2 SS |
7174 | |
7175 | #if TARGET_MACHO | |
7176 | case ABI_DARWIN: | |
7177 | fprintf (file, "\tb %s", prefix); | |
7178 | if (flag_pic && !machopic_name_defined_p (fname)) | |
7179 | assemble_name (file, machopic_stub_name (fname)); | |
7180 | else | |
7181 | assemble_name (file, fname); | |
7182 | putc ('\n', file); | |
7183 | break; | |
7184 | #endif | |
9ebbca7d GK |
7185 | } |
7186 | } | |
7187 | } | |
42820a49 | 7188 | |
9ebbca7d GK |
7189 | \f |
7190 | /* A quick summary of the various types of 'constant-pool tables' | |
7191 | under PowerPC: | |
7192 | ||
7193 | Target Flags Name One table per | |
7194 | AIX (none) AIX TOC object file | |
7195 | AIX -mfull-toc AIX TOC object file | |
7196 | AIX -mminimal-toc AIX minimal TOC translation unit | |
7197 | SVR4/EABI (none) SVR4 SDATA object file | |
7198 | SVR4/EABI -fpic SVR4 pic object file | |
7199 | SVR4/EABI -fPIC SVR4 PIC translation unit | |
7200 | SVR4/EABI -mrelocatable EABI TOC function | |
7201 | SVR4/EABI -maix AIX TOC object file | |
7202 | SVR4/EABI -maix -mminimal-toc | |
7203 | AIX minimal TOC translation unit | |
7204 | ||
7205 | Name Reg. Set by entries contains: | |
7206 | made by addrs? fp? sum? | |
7207 | ||
7208 | AIX TOC 2 crt0 as Y option option | |
7209 | AIX minimal TOC 30 prolog gcc Y Y option | |
7210 | SVR4 SDATA 13 crt0 gcc N Y N | |
7211 | SVR4 pic 30 prolog ld Y not yet N | |
7212 | SVR4 PIC 30 prolog gcc Y option option | |
7213 | EABI TOC 30 prolog gcc Y option option | |
7214 | ||
7215 | */ | |
7216 | ||
7217 | /* Hash table stuff for keeping track of TOC entries. */ | |
7218 | ||
7219 | struct toc_hash_struct | |
7220 | { | |
7221 | /* `key' will satisfy CONSTANT_P; in fact, it will satisfy | |
7222 | ASM_OUTPUT_SPECIAL_POOL_ENTRY_P. */ | |
7223 | rtx key; | |
a9098fd0 | 7224 | enum machine_mode key_mode; |
9ebbca7d GK |
7225 | int labelno; |
7226 | }; | |
17167fd8 | 7227 | |
9ebbca7d GK |
7228 | static htab_t toc_hash_table; |
7229 | ||
7230 | /* Hash functions for the hash table. */ | |
7231 | ||
7232 | static unsigned | |
7233 | rs6000_hash_constant (k) | |
7234 | rtx k; | |
7235 | { | |
a9098fd0 | 7236 | unsigned result = (GET_CODE (k) << 3) ^ GET_MODE (k); |
9ebbca7d GK |
7237 | const char *format = GET_RTX_FORMAT (GET_CODE (k)); |
7238 | int flen = strlen (format); | |
7239 | int fidx; | |
7240 | ||
7241 | if (GET_CODE (k) == LABEL_REF) | |
832ea3b3 | 7242 | return result * 1231 + X0INT (XEXP (k, 0), 3); |
9ebbca7d GK |
7243 | |
7244 | if (GET_CODE (k) == CONST_DOUBLE) | |
7245 | fidx = 2; | |
7246 | else if (GET_CODE (k) == CODE_LABEL) | |
7247 | fidx = 3; | |
7248 | else | |
7249 | fidx = 0; | |
7250 | ||
7251 | for (; fidx < flen; fidx++) | |
7252 | switch (format[fidx]) | |
7253 | { | |
7254 | case 's': | |
7255 | { | |
7256 | unsigned i, len; | |
7257 | const char *str = XSTR (k, fidx); | |
7258 | len = strlen (str); | |
7259 | result = result * 613 + len; | |
7260 | for (i = 0; i < len; i++) | |
7261 | result = result * 613 + (unsigned) str[i]; | |
17167fd8 MM |
7262 | break; |
7263 | } | |
9ebbca7d GK |
7264 | case 'u': |
7265 | case 'e': | |
7266 | result = result * 1231 + rs6000_hash_constant (XEXP (k, fidx)); | |
7267 | break; | |
7268 | case 'i': | |
7269 | case 'n': | |
7270 | result = result * 613 + (unsigned) XINT (k, fidx); | |
7271 | break; | |
7272 | case 'w': | |
7273 | if (sizeof (unsigned) >= sizeof (HOST_WIDE_INT)) | |
7274 | result = result * 613 + (unsigned) XWINT (k, fidx); | |
7275 | else | |
7276 | { | |
7277 | size_t i; | |
7278 | for (i = 0; i < sizeof(HOST_WIDE_INT)/sizeof(unsigned); i++) | |
7279 | result = result * 613 + (unsigned) (XWINT (k, fidx) | |
7280 | >> CHAR_BIT * i); | |
7281 | } | |
7282 | break; | |
7283 | default: | |
7284 | abort(); | |
7285 | } | |
7286 | return result; | |
7287 | } | |
7288 | ||
7289 | static unsigned | |
7290 | toc_hash_function (hash_entry) | |
7291 | const void * hash_entry; | |
7292 | { | |
a9098fd0 GK |
7293 | const struct toc_hash_struct *thc = |
7294 | (const struct toc_hash_struct *) hash_entry; | |
7295 | return rs6000_hash_constant (thc->key) ^ thc->key_mode; | |
9ebbca7d GK |
7296 | } |
7297 | ||
7298 | /* Compare H1 and H2 for equivalence. */ | |
7299 | ||
7300 | static int | |
7301 | toc_hash_eq (h1, h2) | |
7302 | const void * h1; | |
7303 | const void * h2; | |
7304 | { | |
7305 | rtx r1 = ((const struct toc_hash_struct *) h1)->key; | |
7306 | rtx r2 = ((const struct toc_hash_struct *) h2)->key; | |
7307 | ||
a9098fd0 GK |
7308 | if (((const struct toc_hash_struct *) h1)->key_mode |
7309 | != ((const struct toc_hash_struct *) h2)->key_mode) | |
7310 | return 0; | |
7311 | ||
9ebbca7d GK |
7312 | /* Gotcha: One of these const_doubles will be in memory. |
7313 | The other may be on the constant-pool chain. | |
7314 | So rtx_equal_p will think they are different... */ | |
7315 | if (r1 == r2) | |
7316 | return 1; | |
7317 | if (GET_CODE (r1) != GET_CODE (r2) | |
7318 | || GET_MODE (r1) != GET_MODE (r2)) | |
7319 | return 0; | |
7320 | if (GET_CODE (r1) == CONST_DOUBLE) | |
7321 | { | |
7322 | int format_len = strlen (GET_RTX_FORMAT (CONST_DOUBLE)); | |
7323 | int i; | |
7324 | for (i = 2; i < format_len; i++) | |
7325 | if (XWINT (r1, i) != XWINT (r2, i)) | |
7326 | return 0; | |
7327 | ||
7328 | return 1; | |
17167fd8 | 7329 | } |
9ebbca7d | 7330 | else if (GET_CODE (r1) == LABEL_REF) |
e4a0656f GK |
7331 | return (CODE_LABEL_NUMBER (XEXP (r1, 0)) |
7332 | == CODE_LABEL_NUMBER (XEXP (r2, 0))); | |
9ebbca7d GK |
7333 | else |
7334 | return rtx_equal_p (r1, r2); | |
7335 | } | |
7336 | ||
7337 | /* Mark the hash table-entry HASH_ENTRY. */ | |
7338 | ||
7339 | static int | |
7340 | toc_hash_mark_entry (hash_slot, unused) | |
2eba1afa | 7341 | void ** hash_slot; |
9ebbca7d GK |
7342 | void * unused ATTRIBUTE_UNUSED; |
7343 | { | |
7344 | const struct toc_hash_struct * hash_entry = | |
7345 | *(const struct toc_hash_struct **) hash_slot; | |
7346 | rtx r = hash_entry->key; | |
7347 | ggc_set_mark (hash_entry); | |
7348 | /* For CODE_LABELS, we don't want to drag in the whole insn chain... */ | |
7349 | if (GET_CODE (r) == LABEL_REF) | |
7350 | { | |
7351 | ggc_set_mark (r); | |
7352 | ggc_set_mark (XEXP (r, 0)); | |
7353 | } | |
7354 | else | |
7355 | ggc_mark_rtx (r); | |
7356 | return 1; | |
7357 | } | |
7358 | ||
7359 | /* Mark all the elements of the TOC hash-table *HT. */ | |
7360 | ||
7361 | static void | |
7362 | toc_hash_mark_table (vht) | |
7363 | void *vht; | |
7364 | { | |
7365 | htab_t *ht = vht; | |
7366 | ||
7367 | htab_traverse (*ht, toc_hash_mark_entry, (void *)0); | |
17167fd8 MM |
7368 | } |
7369 | ||
28e510bd MM |
7370 | /* These are the names given by the C++ front-end to vtables, and |
7371 | vtable-like objects. Ideally, this logic should not be here; | |
7372 | instead, there should be some programmatic way of inquiring as | |
7373 | to whether or not an object is a vtable. */ | |
7374 | ||
7375 | #define VTABLE_NAME_P(NAME) \ | |
7376 | (strncmp ("_vt.", name, strlen("_vt.")) == 0 \ | |
7377 | || strncmp ("_ZTV", name, strlen ("_ZTV")) == 0 \ | |
7378 | || strncmp ("_ZTT", name, strlen ("_ZTT")) == 0 \ | |
7379 | || strncmp ("_ZTC", name, strlen ("_ZTC")) == 0) | |
7380 | ||
7381 | void | |
7382 | rs6000_output_symbol_ref (file, x) | |
7383 | FILE *file; | |
7384 | rtx x; | |
7385 | { | |
7386 | /* Currently C++ toc references to vtables can be emitted before it | |
7387 | is decided whether the vtable is public or private. If this is | |
7388 | the case, then the linker will eventually complain that there is | |
7389 | a reference to an unknown section. Thus, for vtables only, | |
7390 | we emit the TOC reference to reference the symbol and not the | |
7391 | section. */ | |
7392 | const char *name = XSTR (x, 0); | |
7393 | ||
7394 | if (VTABLE_NAME_P (name)) | |
7395 | { | |
7396 | RS6000_OUTPUT_BASENAME (file, name); | |
7397 | } | |
7398 | else | |
7399 | assemble_name (file, name); | |
7400 | } | |
7401 | ||
9878760c RK |
7402 | /* Output a TOC entry. We derive the entry name from what is |
7403 | being written. */ | |
7404 | ||
7405 | void | |
a9098fd0 | 7406 | output_toc (file, x, labelno, mode) |
9878760c RK |
7407 | FILE *file; |
7408 | rtx x; | |
7409 | int labelno; | |
a9098fd0 | 7410 | enum machine_mode mode; |
9878760c RK |
7411 | { |
7412 | char buf[256]; | |
3cce094d | 7413 | const char *name = buf; |
ec940faa | 7414 | const char *real_name; |
9878760c RK |
7415 | rtx base = x; |
7416 | int offset = 0; | |
7417 | ||
4697a36c MM |
7418 | if (TARGET_NO_TOC) |
7419 | abort (); | |
7420 | ||
9ebbca7d GK |
7421 | /* When the linker won't eliminate them, don't output duplicate |
7422 | TOC entries (this happens on AIX if there is any kind of TOC, | |
1f8f4a0b MM |
7423 | and on SVR4 under -fPIC or -mrelocatable). */ |
7424 | if (TARGET_TOC) | |
9ebbca7d GK |
7425 | { |
7426 | struct toc_hash_struct *h; | |
7427 | void * * found; | |
7428 | ||
7429 | h = ggc_alloc (sizeof (*h)); | |
7430 | h->key = x; | |
a9098fd0 | 7431 | h->key_mode = mode; |
9ebbca7d GK |
7432 | h->labelno = labelno; |
7433 | ||
7434 | found = htab_find_slot (toc_hash_table, h, 1); | |
7435 | if (*found == NULL) | |
7436 | *found = h; | |
7437 | else /* This is indeed a duplicate. | |
7438 | Set this label equal to that label. */ | |
7439 | { | |
7440 | fputs ("\t.set ", file); | |
7441 | ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC"); | |
7442 | fprintf (file, "%d,", labelno); | |
7443 | ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC"); | |
7444 | fprintf (file, "%d\n", ((*(const struct toc_hash_struct **) | |
7445 | found)->labelno)); | |
7446 | return; | |
7447 | } | |
7448 | } | |
7449 | ||
7450 | /* If we're going to put a double constant in the TOC, make sure it's | |
7451 | aligned properly when strict alignment is on. */ | |
ff1720ed RK |
7452 | if (GET_CODE (x) == CONST_DOUBLE |
7453 | && STRICT_ALIGNMENT | |
a9098fd0 | 7454 | && GET_MODE_BITSIZE (mode) >= 64 |
ff1720ed RK |
7455 | && ! (TARGET_NO_FP_IN_TOC && ! TARGET_MINIMAL_TOC)) { |
7456 | ASM_OUTPUT_ALIGN (file, 3); | |
7457 | } | |
7458 | ||
9ebbca7d | 7459 | ASM_OUTPUT_INTERNAL_LABEL (file, "LC", labelno); |
9878760c | 7460 | |
37c37a57 RK |
7461 | /* Handle FP constants specially. Note that if we have a minimal |
7462 | TOC, things we put here aren't actually in the TOC, so we can allow | |
7463 | FP constants. */ | |
a9098fd0 | 7464 | if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == DFmode) |
9878760c | 7465 | { |
042259f2 DE |
7466 | REAL_VALUE_TYPE rv; |
7467 | long k[2]; | |
0adc764e | 7468 | |
042259f2 DE |
7469 | REAL_VALUE_FROM_CONST_DOUBLE (rv, x); |
7470 | REAL_VALUE_TO_TARGET_DOUBLE (rv, k); | |
31bfaa0b | 7471 | |
13ded975 DE |
7472 | if (TARGET_64BIT) |
7473 | { | |
7474 | if (TARGET_MINIMAL_TOC) | |
2bfcf297 | 7475 | fputs (DOUBLE_INT_ASM_OP, file); |
13ded975 | 7476 | else |
2bfcf297 DB |
7477 | fprintf (file, "\t.tc FD_%lx_%lx[TC],", k[0], k[1]); |
7478 | fprintf (file, "0x%lx%08lx\n", k[0], k[1]); | |
13ded975 DE |
7479 | return; |
7480 | } | |
1875cc88 | 7481 | else |
13ded975 DE |
7482 | { |
7483 | if (TARGET_MINIMAL_TOC) | |
2bfcf297 | 7484 | fputs ("\t.long ", file); |
13ded975 | 7485 | else |
2bfcf297 DB |
7486 | fprintf (file, "\t.tc FD_%lx_%lx[TC],", k[0], k[1]); |
7487 | fprintf (file, "0x%lx,0x%lx\n", k[0], k[1]); | |
13ded975 DE |
7488 | return; |
7489 | } | |
9878760c | 7490 | } |
a9098fd0 | 7491 | else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == SFmode) |
9878760c | 7492 | { |
042259f2 DE |
7493 | REAL_VALUE_TYPE rv; |
7494 | long l; | |
9878760c | 7495 | |
042259f2 DE |
7496 | REAL_VALUE_FROM_CONST_DOUBLE (rv, x); |
7497 | REAL_VALUE_TO_TARGET_SINGLE (rv, l); | |
7498 | ||
31bfaa0b DE |
7499 | if (TARGET_64BIT) |
7500 | { | |
7501 | if (TARGET_MINIMAL_TOC) | |
2bfcf297 | 7502 | fputs (DOUBLE_INT_ASM_OP, file); |
31bfaa0b | 7503 | else |
2bfcf297 DB |
7504 | fprintf (file, "\t.tc FS_%lx[TC],", l); |
7505 | fprintf (file, "0x%lx00000000\n", l); | |
31bfaa0b DE |
7506 | return; |
7507 | } | |
042259f2 | 7508 | else |
31bfaa0b DE |
7509 | { |
7510 | if (TARGET_MINIMAL_TOC) | |
2bfcf297 | 7511 | fputs ("\t.long ", file); |
31bfaa0b | 7512 | else |
2bfcf297 DB |
7513 | fprintf (file, "\t.tc FS_%lx[TC],", l); |
7514 | fprintf (file, "0x%lx\n", l); | |
31bfaa0b DE |
7515 | return; |
7516 | } | |
042259f2 | 7517 | } |
f176e826 | 7518 | else if (GET_MODE (x) == VOIDmode |
a9098fd0 | 7519 | && (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE)) |
042259f2 | 7520 | { |
e2c953b6 | 7521 | unsigned HOST_WIDE_INT low; |
042259f2 DE |
7522 | HOST_WIDE_INT high; |
7523 | ||
7524 | if (GET_CODE (x) == CONST_DOUBLE) | |
7525 | { | |
7526 | low = CONST_DOUBLE_LOW (x); | |
7527 | high = CONST_DOUBLE_HIGH (x); | |
7528 | } | |
7529 | else | |
7530 | #if HOST_BITS_PER_WIDE_INT == 32 | |
7531 | { | |
7532 | low = INTVAL (x); | |
0858c623 | 7533 | high = (low & 0x80000000) ? ~0 : 0; |
042259f2 DE |
7534 | } |
7535 | #else | |
7536 | { | |
0858c623 | 7537 | low = INTVAL (x) & 0xffffffff; |
042259f2 DE |
7538 | high = (HOST_WIDE_INT) INTVAL (x) >> 32; |
7539 | } | |
7540 | #endif | |
9878760c | 7541 | |
a9098fd0 GK |
7542 | /* TOC entries are always Pmode-sized, but since this |
7543 | is a bigendian machine then if we're putting smaller | |
7544 | integer constants in the TOC we have to pad them. | |
7545 | (This is still a win over putting the constants in | |
7546 | a separate constant pool, because then we'd have | |
02a4ec28 FS |
7547 | to have both a TOC entry _and_ the actual constant.) |
7548 | ||
7549 | For a 32-bit target, CONST_INT values are loaded and shifted | |
7550 | entirely within `low' and can be stored in one TOC entry. */ | |
7551 | ||
7552 | if (TARGET_64BIT && POINTER_SIZE < GET_MODE_BITSIZE (mode)) | |
a9098fd0 | 7553 | abort ();/* It would be easy to make this work, but it doesn't now. */ |
02a4ec28 FS |
7554 | |
7555 | if (POINTER_SIZE > GET_MODE_BITSIZE (mode)) | |
a9098fd0 GK |
7556 | lshift_double (low, high, POINTER_SIZE - GET_MODE_BITSIZE (mode), |
7557 | POINTER_SIZE, &low, &high, 0); | |
7558 | ||
13ded975 DE |
7559 | if (TARGET_64BIT) |
7560 | { | |
7561 | if (TARGET_MINIMAL_TOC) | |
2bfcf297 | 7562 | fputs (DOUBLE_INT_ASM_OP, file); |
13ded975 | 7563 | else |
2bfcf297 DB |
7564 | fprintf (file, "\t.tc ID_%lx_%lx[TC],", (long)high, (long)low); |
7565 | fprintf (file, "0x%lx%08lx\n", (long) high, (long) low); | |
13ded975 DE |
7566 | return; |
7567 | } | |
1875cc88 | 7568 | else |
13ded975 | 7569 | { |
02a4ec28 FS |
7570 | if (POINTER_SIZE < GET_MODE_BITSIZE (mode)) |
7571 | { | |
7572 | if (TARGET_MINIMAL_TOC) | |
2bfcf297 | 7573 | fputs ("\t.long ", file); |
02a4ec28 | 7574 | else |
2bfcf297 DB |
7575 | fprintf (file, "\t.tc ID_%lx_%lx[TC],", |
7576 | (long)high, (long)low); | |
7577 | fprintf (file, "0x%lx,0x%lx\n", (long) high, (long) low); | |
02a4ec28 | 7578 | } |
13ded975 | 7579 | else |
02a4ec28 FS |
7580 | { |
7581 | if (TARGET_MINIMAL_TOC) | |
2bfcf297 | 7582 | fputs ("\t.long ", file); |
02a4ec28 | 7583 | else |
2bfcf297 DB |
7584 | fprintf (file, "\t.tc IS_%lx[TC],", (long) low); |
7585 | fprintf (file, "0x%lx\n", (long) low); | |
02a4ec28 | 7586 | } |
13ded975 DE |
7587 | return; |
7588 | } | |
9878760c RK |
7589 | } |
7590 | ||
7591 | if (GET_CODE (x) == CONST) | |
7592 | { | |
2bfcf297 DB |
7593 | if (GET_CODE (XEXP (x, 0)) != PLUS) |
7594 | abort (); | |
7595 | ||
9878760c RK |
7596 | base = XEXP (XEXP (x, 0), 0); |
7597 | offset = INTVAL (XEXP (XEXP (x, 0), 1)); | |
7598 | } | |
7599 | ||
7600 | if (GET_CODE (base) == SYMBOL_REF) | |
7601 | name = XSTR (base, 0); | |
7602 | else if (GET_CODE (base) == LABEL_REF) | |
7603 | ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (XEXP (base, 0))); | |
7604 | else if (GET_CODE (base) == CODE_LABEL) | |
7605 | ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (base)); | |
7606 | else | |
7607 | abort (); | |
7608 | ||
2e4eb9b0 | 7609 | STRIP_NAME_ENCODING (real_name, name); |
1875cc88 | 7610 | if (TARGET_MINIMAL_TOC) |
2bfcf297 | 7611 | fputs (TARGET_32BIT ? "\t.long " : DOUBLE_INT_ASM_OP, file); |
1875cc88 JW |
7612 | else |
7613 | { | |
b6c9286a | 7614 | fprintf (file, "\t.tc %s", real_name); |
9878760c | 7615 | |
1875cc88 JW |
7616 | if (offset < 0) |
7617 | fprintf (file, ".N%d", - offset); | |
7618 | else if (offset) | |
7619 | fprintf (file, ".P%d", offset); | |
9878760c | 7620 | |
19d2d16f | 7621 | fputs ("[TC],", file); |
1875cc88 | 7622 | } |
581bc4de MM |
7623 | |
7624 | /* Currently C++ toc references to vtables can be emitted before it | |
7625 | is decided whether the vtable is public or private. If this is | |
7626 | the case, then the linker will eventually complain that there is | |
7627 | a TOC reference to an unknown section. Thus, for vtables only, | |
7628 | we emit the TOC reference to reference the symbol and not the | |
7629 | section. */ | |
28e510bd | 7630 | if (VTABLE_NAME_P (name)) |
581bc4de | 7631 | { |
89c01f0e | 7632 | RS6000_OUTPUT_BASENAME (file, name); |
581bc4de MM |
7633 | if (offset < 0) |
7634 | fprintf (file, "%d", offset); | |
7635 | else if (offset > 0) | |
7636 | fprintf (file, "+%d", offset); | |
7637 | } | |
7638 | else | |
7639 | output_addr_const (file, x); | |
19d2d16f | 7640 | putc ('\n', file); |
9878760c RK |
7641 | } |
7642 | \f | |
7643 | /* Output an assembler pseudo-op to write an ASCII string of N characters | |
7644 | starting at P to FILE. | |
7645 | ||
7646 | On the RS/6000, we have to do this using the .byte operation and | |
7647 | write out special characters outside the quoted string. | |
7648 | Also, the assembler is broken; very long strings are truncated, | |
7649 | so we must artificially break them up early. */ | |
7650 | ||
7651 | void | |
7652 | output_ascii (file, p, n) | |
7653 | FILE *file; | |
d330fd93 | 7654 | const char *p; |
9878760c RK |
7655 | int n; |
7656 | { | |
7657 | char c; | |
7658 | int i, count_string; | |
d330fd93 KG |
7659 | const char *for_string = "\t.byte \""; |
7660 | const char *for_decimal = "\t.byte "; | |
7661 | const char *to_close = NULL; | |
9878760c RK |
7662 | |
7663 | count_string = 0; | |
7664 | for (i = 0; i < n; i++) | |
7665 | { | |
7666 | c = *p++; | |
7667 | if (c >= ' ' && c < 0177) | |
7668 | { | |
7669 | if (for_string) | |
7670 | fputs (for_string, file); | |
7671 | putc (c, file); | |
7672 | ||
7673 | /* Write two quotes to get one. */ | |
7674 | if (c == '"') | |
7675 | { | |
7676 | putc (c, file); | |
7677 | ++count_string; | |
7678 | } | |
7679 | ||
7680 | for_string = NULL; | |
7681 | for_decimal = "\"\n\t.byte "; | |
7682 | to_close = "\"\n"; | |
7683 | ++count_string; | |
7684 | ||
7685 | if (count_string >= 512) | |
7686 | { | |
7687 | fputs (to_close, file); | |
7688 | ||
7689 | for_string = "\t.byte \""; | |
7690 | for_decimal = "\t.byte "; | |
7691 | to_close = NULL; | |
7692 | count_string = 0; | |
7693 | } | |
7694 | } | |
7695 | else | |
7696 | { | |
7697 | if (for_decimal) | |
7698 | fputs (for_decimal, file); | |
7699 | fprintf (file, "%d", c); | |
7700 | ||
7701 | for_string = "\n\t.byte \""; | |
7702 | for_decimal = ", "; | |
7703 | to_close = "\n"; | |
7704 | count_string = 0; | |
7705 | } | |
7706 | } | |
7707 | ||
7708 | /* Now close the string if we have written one. Then end the line. */ | |
7709 | if (to_close) | |
9ebbca7d | 7710 | fputs (to_close, file); |
9878760c RK |
7711 | } |
7712 | \f | |
7713 | /* Generate a unique section name for FILENAME for a section type | |
7714 | represented by SECTION_DESC. Output goes into BUF. | |
7715 | ||
7716 | SECTION_DESC can be any string, as long as it is different for each | |
7717 | possible section type. | |
7718 | ||
7719 | We name the section in the same manner as xlc. The name begins with an | |
7720 | underscore followed by the filename (after stripping any leading directory | |
11e5fe42 RK |
7721 | names) with the last period replaced by the string SECTION_DESC. If |
7722 | FILENAME does not contain a period, SECTION_DESC is appended to the end of | |
7723 | the name. */ | |
9878760c RK |
7724 | |
7725 | void | |
7726 | rs6000_gen_section_name (buf, filename, section_desc) | |
7727 | char **buf; | |
9ebbca7d GK |
7728 | const char *filename; |
7729 | const char *section_desc; | |
9878760c | 7730 | { |
9ebbca7d | 7731 | const char *q, *after_last_slash, *last_period = 0; |
9878760c RK |
7732 | char *p; |
7733 | int len; | |
9878760c RK |
7734 | |
7735 | after_last_slash = filename; | |
7736 | for (q = filename; *q; q++) | |
11e5fe42 RK |
7737 | { |
7738 | if (*q == '/') | |
7739 | after_last_slash = q + 1; | |
7740 | else if (*q == '.') | |
7741 | last_period = q; | |
7742 | } | |
9878760c | 7743 | |
11e5fe42 | 7744 | len = strlen (after_last_slash) + strlen (section_desc) + 2; |
9878760c RK |
7745 | *buf = (char *) permalloc (len); |
7746 | ||
7747 | p = *buf; | |
7748 | *p++ = '_'; | |
7749 | ||
7750 | for (q = after_last_slash; *q; q++) | |
7751 | { | |
11e5fe42 | 7752 | if (q == last_period) |
9878760c RK |
7753 | { |
7754 | strcpy (p, section_desc); | |
7755 | p += strlen (section_desc); | |
9878760c RK |
7756 | } |
7757 | ||
e9a780ec | 7758 | else if (ISALNUM (*q)) |
9878760c RK |
7759 | *p++ = *q; |
7760 | } | |
7761 | ||
11e5fe42 | 7762 | if (last_period == 0) |
9878760c RK |
7763 | strcpy (p, section_desc); |
7764 | else | |
7765 | *p = '\0'; | |
7766 | } | |
e165f3f0 | 7767 | \f |
411707f4 CC |
7768 | |
7769 | /* Emit profile function. */ | |
7770 | void | |
7771 | output_profile_hook (labelno) | |
7772 | int labelno; | |
7773 | { | |
8480e480 CC |
7774 | if (DEFAULT_ABI == ABI_AIX) |
7775 | { | |
7776 | char buf[30]; | |
7777 | char *label_name; | |
7778 | rtx fun; | |
411707f4 | 7779 | |
8480e480 | 7780 | labelno += 1; |
411707f4 | 7781 | |
8480e480 CC |
7782 | ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno); |
7783 | STRIP_NAME_ENCODING (label_name, ggc_strdup (buf)); | |
7784 | fun = gen_rtx_SYMBOL_REF (Pmode, label_name); | |
411707f4 | 7785 | |
8480e480 CC |
7786 | emit_library_call (init_one_libfunc (RS6000_MCOUNT), 0, VOIDmode, 1, |
7787 | fun, Pmode); | |
7788 | } | |
ee890fe2 SS |
7789 | else if (DEFAULT_ABI == ABI_DARWIN) |
7790 | { | |
d5fa86ba | 7791 | const char *mcount_name = RS6000_MCOUNT; |
ee890fe2 SS |
7792 | int caller_addr_regno = LINK_REGISTER_REGNUM; |
7793 | ||
7794 | /* Be conservative and always set this, at least for now. */ | |
7795 | current_function_uses_pic_offset_table = 1; | |
7796 | ||
7797 | #if TARGET_MACHO | |
7798 | /* For PIC code, set up a stub and collect the caller's address | |
7799 | from r0, which is where the prologue puts it. */ | |
7800 | if (flag_pic) | |
7801 | { | |
7802 | mcount_name = machopic_stub_name (mcount_name); | |
7803 | if (current_function_uses_pic_offset_table) | |
7804 | caller_addr_regno = 0; | |
7805 | } | |
7806 | #endif | |
7807 | emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mcount_name), | |
7808 | 0, VOIDmode, 1, | |
7809 | gen_rtx_REG (Pmode, caller_addr_regno), Pmode); | |
7810 | } | |
411707f4 CC |
7811 | } |
7812 | ||
e165f3f0 RK |
7813 | /* Write function profiler code. */ |
7814 | ||
7815 | void | |
7816 | output_function_profiler (file, labelno) | |
7817 | FILE *file; | |
7818 | int labelno; | |
7819 | { | |
3daf36a4 | 7820 | char buf[100]; |
e165f3f0 | 7821 | |
3daf36a4 | 7822 | ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno); |
38c1f2d7 | 7823 | switch (DEFAULT_ABI) |
3daf36a4 | 7824 | { |
38c1f2d7 MM |
7825 | default: |
7826 | abort (); | |
7827 | ||
7828 | case ABI_V4: | |
7829 | case ABI_SOLARIS: | |
7830 | case ABI_AIX_NODESC: | |
7831 | fprintf (file, "\tmflr %s\n", reg_names[0]); | |
7832 | if (flag_pic == 1) | |
7833 | { | |
dfdfa60f DE |
7834 | fputs ("\tbl _GLOBAL_OFFSET_TABLE_@local-4\n", file); |
7835 | asm_fprintf (file, "\t{st|stw} %s,4(%s)\n", | |
7836 | reg_names[0], reg_names[1]); | |
17167fd8 | 7837 | asm_fprintf (file, "\tmflr %s\n", reg_names[12]); |
dfdfa60f | 7838 | asm_fprintf (file, "\t{l|lwz} %s,", reg_names[0]); |
38c1f2d7 | 7839 | assemble_name (file, buf); |
17167fd8 | 7840 | asm_fprintf (file, "@got(%s)\n", reg_names[12]); |
38c1f2d7 | 7841 | } |
9ebbca7d | 7842 | else if (flag_pic > 1) |
38c1f2d7 | 7843 | { |
dfdfa60f DE |
7844 | asm_fprintf (file, "\t{st|stw} %s,4(%s)\n", |
7845 | reg_names[0], reg_names[1]); | |
9ebbca7d GK |
7846 | /* Now, we need to get the address of the label. */ |
7847 | fputs ("\tbl 1f\n\t.long ", file); | |
034e84c4 | 7848 | assemble_name (file, buf); |
9ebbca7d GK |
7849 | fputs ("-.\n1:", file); |
7850 | asm_fprintf (file, "\tmflr %s\n", reg_names[11]); | |
7851 | asm_fprintf (file, "\t{l|lwz} %s,0(%s)\n", | |
7852 | reg_names[0], reg_names[11]); | |
7853 | asm_fprintf (file, "\t{cax|add} %s,%s,%s\n", | |
7854 | reg_names[0], reg_names[0], reg_names[11]); | |
38c1f2d7 | 7855 | } |
38c1f2d7 MM |
7856 | else |
7857 | { | |
17167fd8 | 7858 | asm_fprintf (file, "\t{liu|lis} %s,", reg_names[12]); |
38c1f2d7 | 7859 | assemble_name (file, buf); |
dfdfa60f | 7860 | fputs ("@ha\n", file); |
b5253831 DE |
7861 | asm_fprintf (file, "\t{st|stw} %s,4(%s)\n", |
7862 | reg_names[0], reg_names[1]); | |
a260abc9 | 7863 | asm_fprintf (file, "\t{cal|la} %s,", reg_names[0]); |
38c1f2d7 | 7864 | assemble_name (file, buf); |
17167fd8 | 7865 | asm_fprintf (file, "@l(%s)\n", reg_names[12]); |
38c1f2d7 MM |
7866 | } |
7867 | ||
b5253831 DE |
7868 | if (current_function_needs_context) |
7869 | asm_fprintf (file, "\tmr %s,%s\n", | |
7870 | reg_names[30], reg_names[STATIC_CHAIN_REGNUM]); | |
38c1f2d7 | 7871 | fprintf (file, "\tbl %s\n", RS6000_MCOUNT); |
b5253831 DE |
7872 | if (current_function_needs_context) |
7873 | asm_fprintf (file, "\tmr %s,%s\n", | |
7874 | reg_names[STATIC_CHAIN_REGNUM], reg_names[30]); | |
38c1f2d7 MM |
7875 | break; |
7876 | ||
7877 | case ABI_AIX: | |
ee890fe2 | 7878 | case ABI_DARWIN: |
411707f4 | 7879 | /* Don't do anything, done in output_profile_hook (). */ |
38c1f2d7 | 7880 | break; |
411707f4 | 7881 | |
38c1f2d7 | 7882 | } |
e165f3f0 | 7883 | } |
a251ffd0 TG |
7884 | |
7885 | /* Adjust the cost of a scheduling dependency. Return the new cost of | |
7886 | a dependency LINK or INSN on DEP_INSN. COST is the current cost. */ | |
7887 | ||
c237e94a | 7888 | static int |
a06faf84 | 7889 | rs6000_adjust_cost (insn, link, dep_insn, cost) |
a251ffd0 TG |
7890 | rtx insn; |
7891 | rtx link; | |
296b8152 | 7892 | rtx dep_insn ATTRIBUTE_UNUSED; |
a251ffd0 TG |
7893 | int cost; |
7894 | { | |
7895 | if (! recog_memoized (insn)) | |
7896 | return 0; | |
7897 | ||
7898 | if (REG_NOTE_KIND (link) != 0) | |
7899 | return 0; | |
7900 | ||
7901 | if (REG_NOTE_KIND (link) == 0) | |
7902 | { | |
7903 | /* Data dependency; DEP_INSN writes a register that INSN reads some | |
7904 | cycles later. */ | |
7905 | ||
7906 | /* Tell the first scheduling pass about the latency between a mtctr | |
7907 | and bctr (and mtlr and br/blr). The first scheduling pass will not | |
7908 | know about this latency since the mtctr instruction, which has the | |
7909 | latency associated to it, will be generated by reload. */ | |
7910 | if (get_attr_type (insn) == TYPE_JMPREG) | |
7911 | return TARGET_POWER ? 5 : 4; | |
7912 | ||
7913 | /* Fall out to return default cost. */ | |
7914 | } | |
7915 | ||
7916 | return cost; | |
7917 | } | |
b6c9286a | 7918 | |
bef84347 VM |
7919 | /* A C statement (sans semicolon) to update the integer scheduling priority |
7920 | INSN_PRIORITY (INSN). Reduce the priority to execute the INSN earlier, | |
7921 | increase the priority to execute INSN later. Do not define this macro if | |
7922 | you do not need to adjust the scheduling priorities of insns. */ | |
7923 | ||
c237e94a | 7924 | static int |
bef84347 | 7925 | rs6000_adjust_priority (insn, priority) |
d330fd93 | 7926 | rtx insn ATTRIBUTE_UNUSED; |
bef84347 VM |
7927 | int priority; |
7928 | { | |
7929 | /* On machines (like the 750) which have asymetric integer units, where one | |
7930 | integer unit can do multiply and divides and the other can't, reduce the | |
7931 | priority of multiply/divide so it is scheduled before other integer | |
7932 | operationss. */ | |
7933 | ||
7934 | #if 0 | |
2c3c49de | 7935 | if (! INSN_P (insn)) |
bef84347 VM |
7936 | return priority; |
7937 | ||
7938 | if (GET_CODE (PATTERN (insn)) == USE) | |
7939 | return priority; | |
7940 | ||
7941 | switch (rs6000_cpu_attr) { | |
7942 | case CPU_PPC750: | |
7943 | switch (get_attr_type (insn)) | |
7944 | { | |
7945 | default: | |
7946 | break; | |
7947 | ||
7948 | case TYPE_IMUL: | |
7949 | case TYPE_IDIV: | |
3cb999d8 DE |
7950 | fprintf (stderr, "priority was %#x (%d) before adjustment\n", |
7951 | priority, priority); | |
bef84347 VM |
7952 | if (priority >= 0 && priority < 0x01000000) |
7953 | priority >>= 3; | |
7954 | break; | |
7955 | } | |
7956 | } | |
7957 | #endif | |
7958 | ||
7959 | return priority; | |
7960 | } | |
7961 | ||
b6c9286a | 7962 | /* Return how many instructions the machine can issue per cycle */ |
c237e94a ZW |
7963 | static int |
7964 | rs6000_issue_rate () | |
b6c9286a MM |
7965 | { |
7966 | switch (rs6000_cpu_attr) { | |
3cb999d8 DE |
7967 | case CPU_RIOS1: /* ? */ |
7968 | case CPU_RS64A: | |
7969 | case CPU_PPC601: /* ? */ | |
7970 | return 3; | |
b6c9286a | 7971 | case CPU_PPC603: |
bef84347 VM |
7972 | case CPU_PPC750: |
7973 | return 2; | |
3cb999d8 | 7974 | case CPU_RIOS2: |
b6c9286a | 7975 | case CPU_PPC604: |
19684119 | 7976 | case CPU_PPC604E: |
b6c9286a | 7977 | case CPU_PPC620: |
3cb999d8 | 7978 | case CPU_PPC630: |
b6c9286a MM |
7979 | return 4; |
7980 | default: | |
7981 | return 1; | |
7982 | } | |
7983 | } | |
7984 | ||
b6c9286a | 7985 | \f |
b6c9286a MM |
7986 | /* Length in units of the trampoline for entering a nested function. */ |
7987 | ||
7988 | int | |
7989 | rs6000_trampoline_size () | |
7990 | { | |
7991 | int ret = 0; | |
7992 | ||
7993 | switch (DEFAULT_ABI) | |
7994 | { | |
7995 | default: | |
7996 | abort (); | |
7997 | ||
7998 | case ABI_AIX: | |
8f802bfb | 7999 | ret = (TARGET_32BIT) ? 12 : 24; |
b6c9286a MM |
8000 | break; |
8001 | ||
8002 | case ABI_V4: | |
c81bebd7 | 8003 | case ABI_SOLARIS: |
b6c9286a | 8004 | case ABI_AIX_NODESC: |
03a7e1a5 | 8005 | ret = (TARGET_32BIT) ? 40 : 48; |
b6c9286a | 8006 | break; |
b6c9286a MM |
8007 | } |
8008 | ||
8009 | return ret; | |
8010 | } | |
8011 | ||
8012 | /* Emit RTL insns to initialize the variable parts of a trampoline. | |
8013 | FNADDR is an RTX for the address of the function's pure code. | |
8014 | CXT is an RTX for the static chain value for the function. */ | |
8015 | ||
8016 | void | |
8017 | rs6000_initialize_trampoline (addr, fnaddr, cxt) | |
8018 | rtx addr; | |
8019 | rtx fnaddr; | |
8020 | rtx cxt; | |
8021 | { | |
ac2a93a1 | 8022 | enum machine_mode pmode = Pmode; |
8bd04c56 MM |
8023 | int regsize = (TARGET_32BIT) ? 4 : 8; |
8024 | rtx ctx_reg = force_reg (pmode, cxt); | |
b6c9286a MM |
8025 | |
8026 | switch (DEFAULT_ABI) | |
8027 | { | |
8028 | default: | |
8029 | abort (); | |
8030 | ||
8bd04c56 | 8031 | /* Macros to shorten the code expansions below. */ |
39403d82 | 8032 | #define MEM_DEREF(addr) gen_rtx_MEM (pmode, memory_address (pmode, addr)) |
c5c76735 JL |
8033 | #define MEM_PLUS(addr,offset) \ |
8034 | gen_rtx_MEM (pmode, memory_address (pmode, plus_constant (addr, offset))) | |
7c59dc5d | 8035 | |
b6c9286a MM |
8036 | /* Under AIX, just build the 3 word function descriptor */ |
8037 | case ABI_AIX: | |
8bd04c56 MM |
8038 | { |
8039 | rtx fn_reg = gen_reg_rtx (pmode); | |
8040 | rtx toc_reg = gen_reg_rtx (pmode); | |
8041 | emit_move_insn (fn_reg, MEM_DEREF (fnaddr)); | |
1cb18e3c | 8042 | emit_move_insn (toc_reg, MEM_PLUS (fnaddr, regsize)); |
8bd04c56 MM |
8043 | emit_move_insn (MEM_DEREF (addr), fn_reg); |
8044 | emit_move_insn (MEM_PLUS (addr, regsize), toc_reg); | |
8045 | emit_move_insn (MEM_PLUS (addr, 2*regsize), ctx_reg); | |
8046 | } | |
b6c9286a MM |
8047 | break; |
8048 | ||
eaf1bcf1 | 8049 | /* Under V.4/eabi, call __trampoline_setup to do the real work. */ |
b6c9286a | 8050 | case ABI_V4: |
c81bebd7 | 8051 | case ABI_SOLARIS: |
b6c9286a | 8052 | case ABI_AIX_NODESC: |
39403d82 | 8053 | emit_library_call (gen_rtx_SYMBOL_REF (SImode, "__trampoline_setup"), |
eaf1bcf1 MM |
8054 | FALSE, VOIDmode, 4, |
8055 | addr, pmode, | |
8056 | GEN_INT (rs6000_trampoline_size ()), SImode, | |
8057 | fnaddr, pmode, | |
8058 | ctx_reg, pmode); | |
b6c9286a | 8059 | break; |
b6c9286a MM |
8060 | } |
8061 | ||
8062 | return; | |
8063 | } | |
7509c759 MM |
8064 | |
8065 | \f | |
7509c759 MM |
8066 | /* If defined, a C expression whose value is nonzero if IDENTIFIER |
8067 | with arguments ARGS is a valid machine specific attribute for TYPE. | |
8068 | The attributes in ATTRIBUTES have previously been assigned to TYPE. */ | |
8069 | ||
672a6f42 | 8070 | static int |
7509c759 MM |
8071 | rs6000_valid_type_attribute_p (type, attributes, identifier, args) |
8072 | tree type; | |
296b8152 | 8073 | tree attributes ATTRIBUTE_UNUSED; |
7509c759 MM |
8074 | tree identifier; |
8075 | tree args; | |
8076 | { | |
8077 | if (TREE_CODE (type) != FUNCTION_TYPE | |
8078 | && TREE_CODE (type) != FIELD_DECL | |
8079 | && TREE_CODE (type) != TYPE_DECL) | |
8080 | return 0; | |
8081 | ||
6a4cee5f MM |
8082 | /* Longcall attribute says that the function is not within 2**26 bytes |
8083 | of the current function, and to do an indirect call. */ | |
8084 | if (is_attribute_p ("longcall", identifier)) | |
8085 | return (args == NULL_TREE); | |
8086 | ||
7509c759 MM |
8087 | return 0; |
8088 | } | |
8089 | ||
3cb999d8 DE |
8090 | /* Return a reference suitable for calling a function with the |
8091 | longcall attribute. */ | |
6a4cee5f MM |
8092 | struct rtx_def * |
8093 | rs6000_longcall_ref (call_ref) | |
8094 | rtx call_ref; | |
8095 | { | |
d330fd93 | 8096 | const char *call_name; |
6a4cee5f MM |
8097 | tree node; |
8098 | ||
8099 | if (GET_CODE (call_ref) != SYMBOL_REF) | |
8100 | return call_ref; | |
8101 | ||
8102 | /* System V adds '.' to the internal name, so skip them. */ | |
8103 | call_name = XSTR (call_ref, 0); | |
8104 | if (*call_name == '.') | |
8105 | { | |
8106 | while (*call_name == '.') | |
8107 | call_name++; | |
8108 | ||
8109 | node = get_identifier (call_name); | |
39403d82 | 8110 | call_ref = gen_rtx_SYMBOL_REF (VOIDmode, IDENTIFIER_POINTER (node)); |
6a4cee5f MM |
8111 | } |
8112 | ||
8113 | return force_reg (Pmode, call_ref); | |
8114 | } | |
8115 | ||
7509c759 MM |
8116 | \f |
8117 | /* A C statement or statements to switch to the appropriate section | |
8118 | for output of RTX in mode MODE. You can assume that RTX is some | |
8119 | kind of constant in RTL. The argument MODE is redundant except in | |
8120 | the case of a `const_int' rtx. Select the section by calling | |
8121 | `text_section' or one of the alternatives for other sections. | |
8122 | ||
8123 | Do not define this macro if you put all constants in the read-only | |
8124 | data section. */ | |
8125 | ||
8126 | #ifdef USING_SVR4_H | |
8127 | ||
8128 | void | |
8129 | rs6000_select_rtx_section (mode, x) | |
a9098fd0 | 8130 | enum machine_mode mode; |
7509c759 MM |
8131 | rtx x; |
8132 | { | |
a9098fd0 | 8133 | if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode)) |
7509c759 | 8134 | toc_section (); |
7509c759 MM |
8135 | else |
8136 | const_section (); | |
8137 | } | |
8138 | ||
8139 | /* A C statement or statements to switch to the appropriate | |
8140 | section for output of DECL. DECL is either a `VAR_DECL' node | |
8141 | or a constant of some sort. RELOC indicates whether forming | |
8142 | the initial value of DECL requires link-time relocations. */ | |
8143 | ||
8144 | void | |
8145 | rs6000_select_section (decl, reloc) | |
8146 | tree decl; | |
8147 | int reloc; | |
8148 | { | |
8149 | int size = int_size_in_bytes (TREE_TYPE (decl)); | |
63019373 GK |
8150 | int needs_sdata; |
8151 | int readonly; | |
8152 | static void (* const sec_funcs[4]) PARAMS ((void)) = { | |
8153 | &const_section, | |
8154 | &sdata2_section, | |
8155 | &data_section, | |
8156 | &sdata_section | |
8157 | }; | |
8158 | ||
8159 | needs_sdata = (size > 0 | |
8160 | && size <= g_switch_value | |
8161 | && rs6000_sdata != SDATA_NONE | |
8162 | && (rs6000_sdata != SDATA_DATA || TREE_PUBLIC (decl))); | |
7509c759 MM |
8163 | |
8164 | if (TREE_CODE (decl) == STRING_CST) | |
63019373 | 8165 | readonly = ! flag_writable_strings; |
a9098fd0 | 8166 | else if (TREE_CODE (decl) == VAR_DECL) |
63019373 GK |
8167 | readonly = (! (flag_pic && reloc) |
8168 | && TREE_READONLY (decl) | |
8169 | && ! TREE_SIDE_EFFECTS (decl) | |
8170 | && DECL_INITIAL (decl) | |
8171 | && DECL_INITIAL (decl) != error_mark_node | |
8172 | && TREE_CONSTANT (DECL_INITIAL (decl))); | |
7509c759 | 8173 | else |
63019373 GK |
8174 | readonly = 1; |
8175 | if (needs_sdata && rs6000_sdata != SDATA_EABI) | |
8176 | readonly = 0; | |
8177 | ||
8178 | (*sec_funcs[(readonly ? 0 : 2) + (needs_sdata ? 1 : 0)])(); | |
8179 | } | |
8180 | ||
8181 | /* A C statement to build up a unique section name, expressed as a | |
8182 | STRING_CST node, and assign it to DECL_SECTION_NAME (decl). | |
8183 | RELOC indicates whether the initial value of EXP requires | |
8184 | link-time relocations. If you do not define this macro, GCC will use | |
8185 | the symbol name prefixed by `.' as the section name. Note - this | |
8186 | macro can now be called for unitialised data items as well as | |
8187 | initialised data and functions. */ | |
8188 | ||
8189 | void | |
8190 | rs6000_unique_section (decl, reloc) | |
8191 | tree decl; | |
8192 | int reloc; | |
8193 | { | |
8194 | int size = int_size_in_bytes (TREE_TYPE (decl)); | |
8195 | int needs_sdata; | |
8196 | int readonly; | |
8197 | int len; | |
8198 | int sec; | |
8199 | const char *name; | |
8200 | char *string; | |
8201 | const char *prefix; | |
8202 | ||
8203 | static const char *const prefixes[7][2] = | |
8204 | { | |
8205 | { ".text.", ".gnu.linkonce.t." }, | |
8206 | { ".rodata.", ".gnu.linkonce.r." }, | |
8207 | { ".sdata2.", ".gnu.linkonce.s2." }, | |
8208 | { ".data.", ".gnu.linkonce.d." }, | |
8209 | { ".sdata.", ".gnu.linkonce.s." }, | |
8210 | { ".bss.", ".gnu.linkonce.b." }, | |
8211 | { ".sbss.", ".gnu.linkonce.sb." } | |
8212 | }; | |
8213 | ||
8214 | needs_sdata = (TREE_CODE (decl) != FUNCTION_DECL | |
8215 | && size > 0 | |
8216 | && size <= g_switch_value | |
8217 | && rs6000_sdata != SDATA_NONE | |
8218 | && (rs6000_sdata != SDATA_DATA || TREE_PUBLIC (decl))); | |
8219 | ||
8220 | if (TREE_CODE (decl) == STRING_CST) | |
8221 | readonly = ! flag_writable_strings; | |
8222 | else if (TREE_CODE (decl) == VAR_DECL) | |
8223 | readonly = (! (flag_pic && reloc) | |
8224 | && TREE_READONLY (decl) | |
8225 | && ! TREE_SIDE_EFFECTS (decl) | |
8226 | && DECL_INITIAL (decl) | |
8227 | && DECL_INITIAL (decl) != error_mark_node | |
8228 | && TREE_CONSTANT (DECL_INITIAL (decl))); | |
8229 | else | |
8230 | readonly = 1; | |
8231 | if (needs_sdata && rs6000_sdata != SDATA_EABI) | |
8232 | readonly = 0; | |
8233 | ||
8234 | sec = ((TREE_CODE (decl) == FUNCTION_DECL ? 0 : 1) | |
8235 | + (readonly ? 0 : 2) | |
8236 | + (needs_sdata ? 1 : 0) | |
8237 | + (DECL_INITIAL (decl) == 0 | |
8238 | || DECL_INITIAL (decl) == error_mark_node) ? 4 : 0); | |
8239 | ||
e6978109 | 8240 | STRIP_NAME_ENCODING (name, IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl))); |
63019373 GK |
8241 | prefix = prefixes[sec][DECL_ONE_ONLY (decl)]; |
8242 | len = strlen (name) + strlen (prefix); | |
8243 | string = alloca (len + 1); | |
8244 | ||
8245 | sprintf (string, "%s%s", prefix, name); | |
8246 | ||
8247 | DECL_SECTION_NAME (decl) = build_string (len, string); | |
7509c759 | 8248 | } |
d9407988 MM |
8249 | |
8250 | \f | |
d9407988 MM |
8251 | /* If we are referencing a function that is static or is known to be |
8252 | in this file, make the SYMBOL_REF special. We can use this to indicate | |
8253 | that we can branch to this function without emitting a no-op after the | |
9ebbca7d | 8254 | call. For real AIX calling sequences, we also replace the |
d9407988 MM |
8255 | function name with the real name (1 or 2 leading .'s), rather than |
8256 | the function descriptor name. This saves a lot of overriding code | |
a260abc9 | 8257 | to read the prefixes. */ |
d9407988 MM |
8258 | |
8259 | void | |
8260 | rs6000_encode_section_info (decl) | |
8261 | tree decl; | |
8262 | { | |
8263 | if (TREE_CODE (decl) == FUNCTION_DECL) | |
8264 | { | |
8265 | rtx sym_ref = XEXP (DECL_RTL (decl), 0); | |
8f1b829e | 8266 | if ((TREE_ASM_WRITTEN (decl) || ! TREE_PUBLIC (decl)) |
c81fc13e | 8267 | && ! DECL_WEAK (decl)) |
d9407988 MM |
8268 | SYMBOL_REF_FLAG (sym_ref) = 1; |
8269 | ||
9ebbca7d | 8270 | if (DEFAULT_ABI == ABI_AIX) |
d9407988 | 8271 | { |
ff669a6c RH |
8272 | size_t len1 = (DEFAULT_ABI == ABI_AIX) ? 1 : 2; |
8273 | size_t len2 = strlen (XSTR (sym_ref, 0)); | |
520a57c8 | 8274 | char *str = alloca (len1 + len2 + 1); |
ff669a6c RH |
8275 | str[0] = '.'; |
8276 | str[1] = '.'; | |
8277 | memcpy (str + len1, XSTR (sym_ref, 0), len2 + 1); | |
8278 | ||
520a57c8 | 8279 | XSTR (sym_ref, 0) = ggc_alloc_string (str, len1 + len2); |
d9407988 MM |
8280 | } |
8281 | } | |
8282 | else if (rs6000_sdata != SDATA_NONE | |
8283 | && (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) | |
8284 | && TREE_CODE (decl) == VAR_DECL) | |
8285 | { | |
8286 | int size = int_size_in_bytes (TREE_TYPE (decl)); | |
8287 | tree section_name = DECL_SECTION_NAME (decl); | |
d330fd93 | 8288 | const char *name = (char *)0; |
d9407988 MM |
8289 | int len = 0; |
8290 | ||
8291 | if (section_name) | |
8292 | { | |
8293 | if (TREE_CODE (section_name) == STRING_CST) | |
8294 | { | |
8295 | name = TREE_STRING_POINTER (section_name); | |
8296 | len = TREE_STRING_LENGTH (section_name); | |
8297 | } | |
8298 | else | |
8299 | abort (); | |
8300 | } | |
8301 | ||
8302 | if ((size > 0 && size <= g_switch_value) | |
8303 | || (name | |
5f59ecb7 | 8304 | && ((len == sizeof (".sdata") - 1 |
3cb999d8 | 8305 | && strcmp (name, ".sdata") == 0) |
5f59ecb7 | 8306 | || (len == sizeof (".sdata2") - 1 |
3cb999d8 | 8307 | && strcmp (name, ".sdata2") == 0) |
5f59ecb7 | 8308 | || (len == sizeof (".sbss") - 1 |
3cb999d8 | 8309 | && strcmp (name, ".sbss") == 0) |
5f59ecb7 | 8310 | || (len == sizeof (".sbss2") - 1 |
3cb999d8 | 8311 | && strcmp (name, ".sbss2") == 0) |
5f59ecb7 | 8312 | || (len == sizeof (".PPC.EMB.sdata0") - 1 |
3cb999d8 | 8313 | && strcmp (name, ".PPC.EMB.sdata0") == 0) |
5f59ecb7 | 8314 | || (len == sizeof (".PPC.EMB.sbss0") - 1 |
3cb999d8 | 8315 | && strcmp (name, ".PPC.EMB.sbss0") == 0)))) |
d9407988 MM |
8316 | { |
8317 | rtx sym_ref = XEXP (DECL_RTL (decl), 0); | |
ff669a6c | 8318 | size_t len = strlen (XSTR (sym_ref, 0)); |
88c1e412 | 8319 | char *str = alloca (len + 2); |
ff669a6c | 8320 | |
ff669a6c RH |
8321 | str[0] = '@'; |
8322 | memcpy (str + 1, XSTR (sym_ref, 0), len + 1); | |
88c1e412 | 8323 | XSTR (sym_ref, 0) = ggc_alloc_string (str, len + 1); |
d9407988 MM |
8324 | } |
8325 | } | |
8326 | } | |
8327 | ||
7509c759 | 8328 | #endif /* USING_SVR4_H */ |
000034eb | 8329 | |
a6c2a102 | 8330 | \f |
000034eb | 8331 | /* Return a REG that occurs in ADDR with coefficient 1. |
02441cd6 JL |
8332 | ADDR can be effectively incremented by incrementing REG. |
8333 | ||
8334 | r0 is special and we must not select it as an address | |
8335 | register by this routine since our caller will try to | |
8336 | increment the returned register via an "la" instruction. */ | |
000034eb DE |
8337 | |
8338 | struct rtx_def * | |
8339 | find_addr_reg (addr) | |
8340 | rtx addr; | |
8341 | { | |
8342 | while (GET_CODE (addr) == PLUS) | |
8343 | { | |
02441cd6 JL |
8344 | if (GET_CODE (XEXP (addr, 0)) == REG |
8345 | && REGNO (XEXP (addr, 0)) != 0) | |
000034eb | 8346 | addr = XEXP (addr, 0); |
02441cd6 JL |
8347 | else if (GET_CODE (XEXP (addr, 1)) == REG |
8348 | && REGNO (XEXP (addr, 1)) != 0) | |
000034eb DE |
8349 | addr = XEXP (addr, 1); |
8350 | else if (CONSTANT_P (XEXP (addr, 0))) | |
8351 | addr = XEXP (addr, 1); | |
8352 | else if (CONSTANT_P (XEXP (addr, 1))) | |
8353 | addr = XEXP (addr, 0); | |
8354 | else | |
8355 | abort (); | |
8356 | } | |
02441cd6 | 8357 | if (GET_CODE (addr) == REG && REGNO (addr) != 0) |
000034eb DE |
8358 | return addr; |
8359 | abort (); | |
8360 | } | |
8361 | ||
a6c2a102 DE |
8362 | void |
8363 | rs6000_fatal_bad_address (op) | |
8364 | rtx op; | |
8365 | { | |
8366 | fatal_insn ("bad address", op); | |
8367 | } | |
c8023011 MM |
8368 | |
8369 | /* Called to register all of our global variables with the garbage | |
8370 | collector. */ | |
8371 | ||
8372 | static void | |
8373 | rs6000_add_gc_roots () | |
8374 | { | |
8375 | ggc_add_rtx_root (&rs6000_compare_op0, 1); | |
8376 | ggc_add_rtx_root (&rs6000_compare_op1, 1); | |
9ebbca7d GK |
8377 | |
8378 | toc_hash_table = htab_create (1021, toc_hash_function, toc_hash_eq, NULL); | |
8379 | ggc_add_root (&toc_hash_table, 1, sizeof (toc_hash_table), | |
8380 | toc_hash_mark_table); | |
ee890fe2 SS |
8381 | |
8382 | #if TARGET_MACHO | |
8383 | machopic_add_gc_roots (); | |
8384 | #endif | |
8385 | } | |
8386 | ||
8387 | #if TARGET_MACHO | |
8388 | ||
8389 | #if 0 | |
8390 | /* Returns 1 if OP is either a symbol reference or a sum of a symbol | |
8391 | reference and a constant. */ | |
8392 | ||
8393 | int | |
8394 | symbolic_operand (op) | |
8395 | register rtx op; | |
8396 | { | |
8397 | switch (GET_CODE (op)) | |
8398 | { | |
8399 | case SYMBOL_REF: | |
8400 | case LABEL_REF: | |
8401 | return 1; | |
8402 | case CONST: | |
8403 | op = XEXP (op, 0); | |
8404 | return (GET_CODE (op) == SYMBOL_REF || | |
8405 | (GET_CODE (XEXP (op, 0)) == SYMBOL_REF | |
8406 | || GET_CODE (XEXP (op, 0)) == LABEL_REF) | |
8407 | && GET_CODE (XEXP (op, 1)) == CONST_INT); | |
8408 | default: | |
8409 | return 0; | |
8410 | } | |
c8023011 | 8411 | } |
ee890fe2 SS |
8412 | #endif |
8413 | ||
8414 | #ifdef RS6000_LONG_BRANCH | |
8415 | ||
8416 | static tree stub_list = 0; | |
8417 | ||
8418 | /* ADD_COMPILER_STUB adds the compiler generated stub for handling | |
8419 | procedure calls to the linked list. */ | |
8420 | ||
8421 | void | |
8422 | add_compiler_stub (label_name, function_name, line_number) | |
8423 | tree label_name; | |
8424 | tree function_name; | |
8425 | int line_number; | |
8426 | { | |
8427 | tree stub = build_tree_list (function_name, label_name); | |
8428 | TREE_TYPE (stub) = build_int_2 (line_number, 0); | |
8429 | TREE_CHAIN (stub) = stub_list; | |
8430 | stub_list = stub; | |
8431 | } | |
8432 | ||
8433 | #define STUB_LABEL_NAME(STUB) TREE_VALUE (STUB) | |
8434 | #define STUB_FUNCTION_NAME(STUB) TREE_PURPOSE (STUB) | |
8435 | #define STUB_LINE_NUMBER(STUB) TREE_INT_CST_LOW (TREE_TYPE (STUB)) | |
8436 | ||
8437 | /* OUTPUT_COMPILER_STUB outputs the compiler generated stub for handling | |
8438 | procedure calls from the linked list and initializes the linked list. */ | |
8439 | ||
8440 | void output_compiler_stub () | |
8441 | { | |
8442 | char tmp_buf[256]; | |
8443 | char label_buf[256]; | |
8444 | char *label; | |
8445 | tree tmp_stub, stub; | |
8446 | ||
8447 | if (!flag_pic) | |
8448 | for (stub = stub_list; stub; stub = TREE_CHAIN (stub)) | |
8449 | { | |
8450 | fprintf (asm_out_file, | |
8451 | "%s:\n", IDENTIFIER_POINTER(STUB_LABEL_NAME(stub))); | |
8452 | ||
8453 | #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO) | |
8454 | if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG) | |
8455 | fprintf (asm_out_file, "\t.stabd 68,0,%d\n", STUB_LINE_NUMBER(stub)); | |
8456 | #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */ | |
8457 | ||
8458 | if (IDENTIFIER_POINTER (STUB_FUNCTION_NAME (stub))[0] == '*') | |
8459 | strcpy (label_buf, | |
8460 | IDENTIFIER_POINTER (STUB_FUNCTION_NAME (stub))+1); | |
8461 | else | |
8462 | { | |
8463 | label_buf[0] = '_'; | |
8464 | strcpy (label_buf+1, | |
8465 | IDENTIFIER_POINTER (STUB_FUNCTION_NAME (stub))); | |
8466 | } | |
8467 | ||
8468 | strcpy (tmp_buf, "lis r12,hi16("); | |
8469 | strcat (tmp_buf, label_buf); | |
8470 | strcat (tmp_buf, ")\n\tori r12,r12,lo16("); | |
8471 | strcat (tmp_buf, label_buf); | |
8472 | strcat (tmp_buf, ")\n\tmtctr r12\n\tbctr"); | |
8473 | output_asm_insn (tmp_buf, 0); | |
8474 | ||
8475 | #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO) | |
8476 | if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG) | |
8477 | fprintf(asm_out_file, "\t.stabd 68,0,%d\n", STUB_LINE_NUMBER (stub)); | |
8478 | #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */ | |
8479 | } | |
8480 | ||
8481 | stub_list = 0; | |
8482 | } | |
8483 | ||
8484 | /* NO_PREVIOUS_DEF checks in the link list whether the function name is | |
8485 | already there or not. */ | |
8486 | ||
8487 | int no_previous_def (function_name) | |
8488 | tree function_name; | |
8489 | { | |
8490 | tree stub; | |
8491 | for (stub = stub_list; stub; stub = TREE_CHAIN (stub)) | |
8492 | if (function_name == STUB_FUNCTION_NAME (stub)) | |
8493 | return 0; | |
8494 | return 1; | |
8495 | } | |
8496 | ||
8497 | /* GET_PREV_LABEL gets the label name from the previous definition of | |
8498 | the function. */ | |
8499 | ||
8500 | tree get_prev_label (function_name) | |
8501 | tree function_name; | |
8502 | { | |
8503 | tree stub; | |
8504 | for (stub = stub_list; stub; stub = TREE_CHAIN (stub)) | |
8505 | if (function_name == STUB_FUNCTION_NAME (stub)) | |
8506 | return STUB_LABEL_NAME (stub); | |
8507 | return 0; | |
8508 | } | |
8509 | ||
8510 | /* INSN is either a function call or a millicode call. It may have an | |
8511 | unconditional jump in its delay slot. | |
8512 | ||
8513 | CALL_DEST is the routine we are calling. */ | |
8514 | ||
8515 | char * | |
8516 | output_call (insn, call_dest, operand_number) | |
8517 | rtx insn; | |
8518 | rtx call_dest; | |
8519 | int operand_number; | |
8520 | { | |
8521 | static char buf[256]; | |
8522 | if (GET_CODE (call_dest) == SYMBOL_REF && TARGET_LONG_BRANCH && !flag_pic) | |
8523 | { | |
8524 | tree labelname; | |
8525 | tree funname = get_identifier (XSTR (call_dest, 0)); | |
8526 | ||
8527 | if (no_previous_def (funname)) | |
8528 | { | |
8529 | int line_number; | |
8530 | rtx label_rtx = gen_label_rtx (); | |
8531 | char *label_buf, temp_buf[256]; | |
8532 | ASM_GENERATE_INTERNAL_LABEL (temp_buf, "L", | |
8533 | CODE_LABEL_NUMBER (label_rtx)); | |
8534 | label_buf = temp_buf[0] == '*' ? temp_buf + 1 : temp_buf; | |
8535 | labelname = get_identifier (label_buf); | |
8536 | for (; insn && GET_CODE (insn) != NOTE; insn = PREV_INSN (insn)); | |
8537 | if (insn) | |
8538 | line_number = NOTE_LINE_NUMBER (insn); | |
8539 | add_compiler_stub (labelname, funname, line_number); | |
8540 | } | |
8541 | else | |
8542 | labelname = get_prev_label (funname); | |
8543 | ||
8544 | sprintf (buf, "jbsr %%z%d,%.246s", | |
8545 | operand_number, IDENTIFIER_POINTER (labelname)); | |
8546 | return buf; | |
8547 | } | |
8548 | else | |
8549 | { | |
8550 | sprintf (buf, "bl %%z%d", operand_number); | |
8551 | return buf; | |
8552 | } | |
8553 | } | |
8554 | ||
8555 | #endif /* RS6000_LONG_BRANCH */ | |
8556 | ||
8557 | #define GEN_LOCAL_LABEL_FOR_SYMBOL(BUF,SYMBOL,LENGTH,N) \ | |
8558 | do { \ | |
8559 | const char *symbol_ = (SYMBOL); \ | |
8560 | char *buffer_ = (BUF); \ | |
8561 | if (symbol_[0] == '"') \ | |
8562 | { \ | |
8563 | sprintf(buffer_, "\"L%d$%s", (N), symbol_+1); \ | |
8564 | } \ | |
8565 | else if (name_needs_quotes(symbol_)) \ | |
8566 | { \ | |
8567 | sprintf(buffer_, "\"L%d$%s\"", (N), symbol_); \ | |
8568 | } \ | |
8569 | else \ | |
8570 | { \ | |
8571 | sprintf(buffer_, "L%d$%s", (N), symbol_); \ | |
8572 | } \ | |
8573 | } while (0) | |
8574 | ||
8575 | ||
8576 | /* Generate PIC and indirect symbol stubs. */ | |
8577 | ||
8578 | void | |
8579 | machopic_output_stub (file, symb, stub) | |
8580 | FILE *file; | |
8581 | const char *symb, *stub; | |
8582 | { | |
8583 | unsigned int length; | |
8584 | char *binder_name, *symbol_name, *lazy_ptr_name; | |
8585 | char *local_label_0, *local_label_1, *local_label_2; | |
8586 | static int label = 0; | |
8587 | ||
df56a27f SS |
8588 | /* Lose our funky encoding stuff so it doesn't contaminate the stub. */ |
8589 | STRIP_NAME_ENCODING (symb, symb); | |
8590 | ||
ee890fe2 SS |
8591 | label += 1; |
8592 | ||
8593 | length = strlen (stub); | |
8594 | binder_name = alloca (length + 32); | |
8595 | GEN_BINDER_NAME_FOR_STUB (binder_name, stub, length); | |
8596 | ||
8597 | length = strlen (symb); | |
8598 | symbol_name = alloca (length + 32); | |
8599 | GEN_SYMBOL_NAME_FOR_SYMBOL (symbol_name, symb, length); | |
8600 | ||
8601 | lazy_ptr_name = alloca (length + 32); | |
8602 | GEN_LAZY_PTR_NAME_FOR_SYMBOL (lazy_ptr_name, symb, length); | |
8603 | ||
8604 | local_label_0 = alloca (length + 32); | |
8605 | GEN_LOCAL_LABEL_FOR_SYMBOL (local_label_0, symb, length, 0); | |
8606 | ||
8607 | local_label_1 = alloca (length + 32); | |
8608 | GEN_LOCAL_LABEL_FOR_SYMBOL (local_label_1, symb, length, 1); | |
8609 | ||
8610 | local_label_2 = alloca (length + 32); | |
8611 | GEN_LOCAL_LABEL_FOR_SYMBOL (local_label_2, symb, length, 2); | |
8612 | ||
8613 | if (flag_pic == 2) | |
8614 | machopic_picsymbol_stub_section (); | |
8615 | else | |
8616 | machopic_symbol_stub_section (); | |
8617 | ||
8618 | fprintf (file, "%s:\n", stub); | |
8619 | fprintf (file, "\t.indirect_symbol %s\n", symbol_name); | |
8620 | ||
8621 | if (flag_pic == 2) | |
8622 | { | |
8623 | fprintf (file, "\tmflr r0\n"); | |
8624 | fprintf (file, "\tbcl 20,31,%s\n", local_label_0); | |
8625 | fprintf (file, "%s:\n\tmflr r11\n", local_label_0); | |
8626 | fprintf (file, "\taddis r11,r11,ha16(%s-%s)\n", | |
8627 | lazy_ptr_name, local_label_0); | |
8628 | fprintf (file, "\tmtlr r0\n"); | |
8629 | fprintf (file, "\tlwz r12,lo16(%s-%s)(r11)\n", | |
8630 | lazy_ptr_name, local_label_0); | |
8631 | fprintf (file, "\tmtctr r12\n"); | |
8632 | fprintf (file, "\taddi r11,r11,lo16(%s-%s)\n", | |
8633 | lazy_ptr_name, local_label_0); | |
8634 | fprintf (file, "\tbctr\n"); | |
8635 | } | |
8636 | else | |
8637 | fprintf (file, "non-pure not supported\n"); | |
8638 | ||
8639 | machopic_lazy_symbol_ptr_section (); | |
8640 | fprintf (file, "%s:\n", lazy_ptr_name); | |
8641 | fprintf (file, "\t.indirect_symbol %s\n", symbol_name); | |
8642 | fprintf (file, "\t.long dyld_stub_binding_helper\n"); | |
8643 | } | |
8644 | ||
8645 | /* Legitimize PIC addresses. If the address is already | |
8646 | position-independent, we return ORIG. Newly generated | |
8647 | position-independent addresses go into a reg. This is REG if non | |
8648 | zero, otherwise we allocate register(s) as necessary. */ | |
8649 | ||
8650 | #define SMALL_INT(X) ((unsigned) (INTVAL(X) + 0x4000) < 0x8000) | |
8651 | ||
8652 | rtx | |
8653 | rs6000_machopic_legitimize_pic_address (orig, mode, reg) | |
8654 | rtx orig; | |
8655 | enum machine_mode mode; | |
8656 | rtx reg; | |
8657 | { | |
8658 | rtx base, offset; | |
8659 | ||
8660 | if (reg == NULL && ! reload_in_progress && ! reload_completed) | |
8661 | reg = gen_reg_rtx (Pmode); | |
8662 | ||
8663 | if (GET_CODE (orig) == CONST) | |
8664 | { | |
8665 | if (GET_CODE (XEXP (orig, 0)) == PLUS | |
8666 | && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx) | |
8667 | return orig; | |
8668 | ||
8669 | if (GET_CODE (XEXP (orig, 0)) == PLUS) | |
8670 | { | |
8671 | base = rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 0), | |
8672 | Pmode, reg); | |
8673 | offset = rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 1), | |
8674 | Pmode, reg); | |
8675 | } | |
8676 | else | |
8677 | abort (); | |
8678 | ||
8679 | if (GET_CODE (offset) == CONST_INT) | |
8680 | { | |
8681 | if (SMALL_INT (offset)) | |
ed8908e7 | 8682 | return plus_constant (base, INTVAL (offset)); |
ee890fe2 SS |
8683 | else if (! reload_in_progress && ! reload_completed) |
8684 | offset = force_reg (Pmode, offset); | |
8685 | else | |
8686 | abort (); | |
8687 | } | |
8688 | return gen_rtx (PLUS, Pmode, base, offset); | |
8689 | } | |
8690 | ||
8691 | /* Fall back on generic machopic code. */ | |
8692 | return machopic_legitimize_pic_address (orig, mode, reg); | |
8693 | } | |
8694 | ||
8695 | /* This is just a placeholder to make linking work without having to | |
8696 | add this to the generic Darwin EXTRA_SECTIONS. If -mcall-aix is | |
8697 | ever needed for Darwin (not too likely!) this would have to get a | |
8698 | real definition. */ | |
8699 | ||
8700 | void | |
8701 | toc_section () | |
8702 | { | |
8703 | } | |
8704 | ||
8705 | #endif /* TARGET_MACHO */ | |
7c262518 RH |
8706 | |
8707 | #if TARGET_ELF | |
8708 | static unsigned int | |
8709 | rs6000_elf_section_type_flags (decl, name, reloc) | |
8710 | tree decl; | |
8711 | const char *name; | |
8712 | int reloc; | |
8713 | { | |
8714 | unsigned int flags = default_section_type_flags (decl, name, reloc); | |
8715 | ||
270fc29b RH |
8716 | if (TARGET_RELOCATABLE) |
8717 | flags |= SECTION_WRITE; | |
7c262518 RH |
8718 | |
8719 | /* Solaris doesn't like @nobits, and gas can handle .sbss without it. */ | |
8720 | flags &= ~SECTION_BSS; | |
d0101753 FS |
8721 | |
8722 | return flags; | |
7c262518 | 8723 | } |
d9f6800d RH |
8724 | |
8725 | /* Record an element in the table of global constructors. SYMBOL is | |
8726 | a SYMBOL_REF of the function to be called; PRIORITY is a number | |
8727 | between 0 and MAX_INIT_PRIORITY. | |
8728 | ||
8729 | This differs from default_named_section_asm_out_constructor in | |
8730 | that we have special handling for -mrelocatable. */ | |
8731 | ||
8732 | static void | |
8733 | rs6000_elf_asm_out_constructor (symbol, priority) | |
8734 | rtx symbol; | |
8735 | int priority; | |
8736 | { | |
8737 | const char *section = ".ctors"; | |
8738 | char buf[16]; | |
8739 | ||
8740 | if (priority != DEFAULT_INIT_PRIORITY) | |
8741 | { | |
8742 | sprintf (buf, ".ctors.%.5u", | |
8743 | /* Invert the numbering so the linker puts us in the proper | |
8744 | order; constructors are run from right to left, and the | |
8745 | linker sorts in increasing order. */ | |
8746 | MAX_INIT_PRIORITY - priority); | |
8747 | section = buf; | |
8748 | } | |
8749 | ||
715bdd29 RH |
8750 | named_section_flags (section, SECTION_WRITE); |
8751 | assemble_align (POINTER_SIZE); | |
d9f6800d RH |
8752 | |
8753 | if (TARGET_RELOCATABLE) | |
8754 | { | |
8755 | fputs ("\t.long (", asm_out_file); | |
8756 | output_addr_const (asm_out_file, symbol); | |
8757 | fputs (")@fixup\n", asm_out_file); | |
8758 | } | |
8759 | else | |
c8af3574 | 8760 | assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1); |
d9f6800d RH |
8761 | } |
8762 | ||
8763 | static void | |
8764 | rs6000_elf_asm_out_destructor (symbol, priority) | |
8765 | rtx symbol; | |
8766 | int priority; | |
8767 | { | |
8768 | const char *section = ".dtors"; | |
8769 | char buf[16]; | |
8770 | ||
8771 | if (priority != DEFAULT_INIT_PRIORITY) | |
8772 | { | |
8773 | sprintf (buf, ".dtors.%.5u", | |
8774 | /* Invert the numbering so the linker puts us in the proper | |
8775 | order; constructors are run from right to left, and the | |
8776 | linker sorts in increasing order. */ | |
8777 | MAX_INIT_PRIORITY - priority); | |
8778 | section = buf; | |
8779 | } | |
8780 | ||
715bdd29 RH |
8781 | named_section_flags (section, SECTION_WRITE); |
8782 | assemble_align (POINTER_SIZE); | |
d9f6800d RH |
8783 | |
8784 | if (TARGET_RELOCATABLE) | |
8785 | { | |
8786 | fputs ("\t.long (", asm_out_file); | |
8787 | output_addr_const (asm_out_file, symbol); | |
8788 | fputs (")@fixup\n", asm_out_file); | |
8789 | } | |
8790 | else | |
c8af3574 | 8791 | assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1); |
d9f6800d | 8792 | } |
7c262518 RH |
8793 | #endif |
8794 | ||
8795 | #ifdef OBJECT_FORMAT_COFF | |
8796 | static void | |
715bdd29 | 8797 | xcoff_asm_named_section (name, flags) |
7c262518 RH |
8798 | const char *name; |
8799 | unsigned int flags ATTRIBUTE_UNUSED; | |
7c262518 RH |
8800 | { |
8801 | fprintf (asm_out_file, "\t.csect %s\n", name); | |
8802 | } | |
8803 | #endif |