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9878760c | 1 | /* Subroutines used for code generation on IBM RS/6000. |
9ebbca7d | 2 | Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, |
95385cbb | 3 | 2000, 2001, 2002 Free Software Foundation, Inc. |
fab3bcc3 | 4 | Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu) |
9878760c RK |
5 | |
6 | This file is part of GNU CC. | |
7 | ||
8 | GNU CC is free software; you can redistribute it and/or modify | |
9 | it under the terms of the GNU General Public License as published by | |
10 | the Free Software Foundation; either version 2, or (at your option) | |
11 | any later version. | |
12 | ||
13 | GNU CC is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
19 | along with GNU CC; see the file COPYING. If not, write to | |
c15c9075 RK |
20 | the Free Software Foundation, 59 Temple Place - Suite 330, |
21 | Boston, MA 02111-1307, USA. */ | |
9878760c | 22 | |
956d6950 | 23 | #include "config.h" |
c4d38ccb | 24 | #include "system.h" |
9878760c RK |
25 | #include "rtl.h" |
26 | #include "regs.h" | |
27 | #include "hard-reg-set.h" | |
28 | #include "real.h" | |
29 | #include "insn-config.h" | |
30 | #include "conditions.h" | |
9878760c RK |
31 | #include "insn-attr.h" |
32 | #include "flags.h" | |
33 | #include "recog.h" | |
9878760c | 34 | #include "obstack.h" |
9b30bae2 | 35 | #include "tree.h" |
dfafc897 | 36 | #include "expr.h" |
2fc1c679 | 37 | #include "optabs.h" |
2a430ec1 | 38 | #include "except.h" |
a7df97e6 | 39 | #include "function.h" |
296b8152 | 40 | #include "output.h" |
d5fa86ba | 41 | #include "basic-block.h" |
d0101753 | 42 | #include "integrate.h" |
296b8152 | 43 | #include "toplev.h" |
c8023011 | 44 | #include "ggc.h" |
9ebbca7d GK |
45 | #include "hashtab.h" |
46 | #include "tm_p.h" | |
672a6f42 NB |
47 | #include "target.h" |
48 | #include "target-def.h" | |
3ac88239 | 49 | #include "langhooks.h" |
24ea750e | 50 | #include "reload.h" |
9b30bae2 | 51 | |
7509c759 MM |
52 | #ifndef TARGET_NO_PROTOTYPE |
53 | #define TARGET_NO_PROTOTYPE 0 | |
54 | #endif | |
55 | ||
9878760c RK |
56 | #define min(A,B) ((A) < (B) ? (A) : (B)) |
57 | #define max(A,B) ((A) > (B) ? (A) : (B)) | |
58 | ||
5248c961 RK |
59 | /* Target cpu type */ |
60 | ||
61 | enum processor_type rs6000_cpu; | |
8e3f41e7 MM |
62 | struct rs6000_cpu_select rs6000_select[3] = |
63 | { | |
815cdc52 MM |
64 | /* switch name, tune arch */ |
65 | { (const char *)0, "--with-cpu=", 1, 1 }, | |
66 | { (const char *)0, "-mcpu=", 1, 1 }, | |
67 | { (const char *)0, "-mtune=", 1, 0 }, | |
8e3f41e7 | 68 | }; |
5248c961 | 69 | |
6fa3f289 ZW |
70 | /* Size of long double */ |
71 | const char *rs6000_long_double_size_string; | |
72 | int rs6000_long_double_type_size; | |
73 | ||
74 | /* Whether -mabi=altivec has appeared */ | |
75 | int rs6000_altivec_abi; | |
76 | ||
c764f757 RK |
77 | /* Set to non-zero once AIX common-mode calls have been defined. */ |
78 | static int common_mode_defined; | |
c81bebd7 | 79 | |
9878760c RK |
80 | /* Save information from a "cmpxx" operation until the branch or scc is |
81 | emitted. */ | |
9878760c RK |
82 | rtx rs6000_compare_op0, rs6000_compare_op1; |
83 | int rs6000_compare_fp_p; | |
874a0744 | 84 | |
874a0744 MM |
85 | /* Label number of label created for -mrelocatable, to call to so we can |
86 | get the address of the GOT section */ | |
87 | int rs6000_pic_labelno; | |
c81bebd7 | 88 | |
b91da81f | 89 | #ifdef USING_ELFOS_H |
c81bebd7 | 90 | /* Which abi to adhere to */ |
815cdc52 | 91 | const char *rs6000_abi_name = RS6000_ABI_NAME; |
d9407988 MM |
92 | |
93 | /* Semantics of the small data area */ | |
94 | enum rs6000_sdata_type rs6000_sdata = SDATA_DATA; | |
95 | ||
96 | /* Which small data model to use */ | |
815cdc52 | 97 | const char *rs6000_sdata_name = (char *)0; |
9ebbca7d GK |
98 | |
99 | /* Counter for labels which are to be placed in .fixup. */ | |
100 | int fixuplabelno = 0; | |
874a0744 | 101 | #endif |
4697a36c | 102 | |
b6c9286a MM |
103 | /* ABI enumeration available for subtarget to use. */ |
104 | enum rs6000_abi rs6000_current_abi; | |
105 | ||
0ac081f6 AH |
106 | /* ABI string from -mabi= option. */ |
107 | const char *rs6000_abi_string; | |
108 | ||
38c1f2d7 | 109 | /* Debug flags */ |
815cdc52 | 110 | const char *rs6000_debug_name; |
38c1f2d7 MM |
111 | int rs6000_debug_stack; /* debug stack applications */ |
112 | int rs6000_debug_arg; /* debug argument handling */ | |
113 | ||
114 | /* Flag to say the TOC is initialized */ | |
115 | int toc_initialized; | |
9ebbca7d | 116 | char toc_label_name[10]; |
38c1f2d7 | 117 | |
9ebbca7d GK |
118 | /* Alias set for saves and restores from the rs6000 stack. */ |
119 | static int rs6000_sr_alias_set; | |
c8023011 | 120 | |
9ebbca7d GK |
121 | static void rs6000_add_gc_roots PARAMS ((void)); |
122 | static int num_insns_constant_wide PARAMS ((HOST_WIDE_INT)); | |
123 | static rtx expand_block_move_mem PARAMS ((enum machine_mode, rtx, rtx)); | |
39a10a29 GK |
124 | static void validate_condition_mode |
125 | PARAMS ((enum rtx_code, enum machine_mode)); | |
126 | static rtx rs6000_generate_compare PARAMS ((enum rtx_code)); | |
e50f5f3d | 127 | static void rs6000_maybe_dead PARAMS ((rtx)); |
9ebbca7d GK |
128 | static void rs6000_emit_stack_tie PARAMS ((void)); |
129 | static void rs6000_frame_related PARAMS ((rtx, rtx, HOST_WIDE_INT, rtx, rtx)); | |
130 | static void rs6000_emit_allocate_stack PARAMS ((HOST_WIDE_INT, int)); | |
131 | static unsigned rs6000_hash_constant PARAMS ((rtx)); | |
132 | static unsigned toc_hash_function PARAMS ((const void *)); | |
133 | static int toc_hash_eq PARAMS ((const void *, const void *)); | |
2eba1afa | 134 | static int toc_hash_mark_entry PARAMS ((void **, void *)); |
9ebbca7d GK |
135 | static void toc_hash_mark_table PARAMS ((void *)); |
136 | static int constant_pool_expr_1 PARAMS ((rtx, int *, int *)); | |
6fee9e99 NC |
137 | static void rs6000_free_machine_status PARAMS ((struct function *)); |
138 | static void rs6000_init_machine_status PARAMS ((struct function *)); | |
301d03af | 139 | static bool rs6000_assemble_integer PARAMS ((rtx, unsigned int, int)); |
71f123ca | 140 | static int rs6000_ra_ever_killed PARAMS ((void)); |
91d231cb JM |
141 | static tree rs6000_handle_longcall_attribute PARAMS ((tree *, tree, tree, int, bool *)); |
142 | const struct attribute_spec rs6000_attribute_table[]; | |
08c148a8 NB |
143 | static void rs6000_output_function_prologue PARAMS ((FILE *, HOST_WIDE_INT)); |
144 | static void rs6000_output_function_epilogue PARAMS ((FILE *, HOST_WIDE_INT)); | |
2bfcf297 DB |
145 | static rtx rs6000_emit_set_long_const PARAMS ((rtx, |
146 | HOST_WIDE_INT, HOST_WIDE_INT)); | |
7c262518 RH |
147 | #if TARGET_ELF |
148 | static unsigned int rs6000_elf_section_type_flags PARAMS ((tree, const char *, | |
149 | int)); | |
d9f6800d RH |
150 | static void rs6000_elf_asm_out_constructor PARAMS ((rtx, int)); |
151 | static void rs6000_elf_asm_out_destructor PARAMS ((rtx, int)); | |
7c262518 RH |
152 | #endif |
153 | #ifdef OBJECT_FORMAT_COFF | |
715bdd29 | 154 | static void xcoff_asm_named_section PARAMS ((const char *, unsigned int)); |
7c262518 | 155 | #endif |
c237e94a ZW |
156 | static int rs6000_adjust_cost PARAMS ((rtx, rtx, rtx, int)); |
157 | static int rs6000_adjust_priority PARAMS ((rtx, int)); | |
158 | static int rs6000_issue_rate PARAMS ((void)); | |
159 | ||
6fa3f289 | 160 | static void rs6000_init_builtins PARAMS ((void)); |
0ac081f6 AH |
161 | static void altivec_init_builtins PARAMS ((void)); |
162 | static rtx rs6000_expand_builtin PARAMS ((tree, rtx, rtx, enum machine_mode, int)); | |
00b960c7 | 163 | static rtx altivec_expand_builtin PARAMS ((tree, rtx)); |
2212663f | 164 | static rtx altivec_expand_unop_builtin PARAMS ((enum insn_code, tree, rtx)); |
0ac081f6 | 165 | static rtx altivec_expand_binop_builtin PARAMS ((enum insn_code, tree, rtx)); |
2212663f | 166 | static rtx altivec_expand_ternop_builtin PARAMS ((enum insn_code, tree, rtx)); |
0ac081f6 | 167 | static void rs6000_parse_abi_options PARAMS ((void)); |
00b960c7 AH |
168 | static int first_altivec_reg_to_save PARAMS ((void)); |
169 | static unsigned int compute_vrsave_mask PARAMS ((void)); | |
170 | static void is_altivec_return_reg PARAMS ((rtx, void *)); | |
171 | int vrsave_operation PARAMS ((rtx, enum machine_mode)); | |
9aa86737 AH |
172 | static rtx generate_set_vrsave PARAMS ((rtx, rs6000_stack_t *, int)); |
173 | static void altivec_frame_fixup PARAMS ((rtx, rtx, HOST_WIDE_INT)); | |
c81bebd7 MM |
174 | \f |
175 | /* Default register names. */ | |
176 | char rs6000_reg_names[][8] = | |
177 | { | |
802a0058 MM |
178 | "0", "1", "2", "3", "4", "5", "6", "7", |
179 | "8", "9", "10", "11", "12", "13", "14", "15", | |
180 | "16", "17", "18", "19", "20", "21", "22", "23", | |
181 | "24", "25", "26", "27", "28", "29", "30", "31", | |
182 | "0", "1", "2", "3", "4", "5", "6", "7", | |
183 | "8", "9", "10", "11", "12", "13", "14", "15", | |
184 | "16", "17", "18", "19", "20", "21", "22", "23", | |
185 | "24", "25", "26", "27", "28", "29", "30", "31", | |
186 | "mq", "lr", "ctr","ap", | |
187 | "0", "1", "2", "3", "4", "5", "6", "7", | |
0ac081f6 AH |
188 | "xer", |
189 | /* AltiVec registers. */ | |
0cd5e3a1 AH |
190 | "0", "1", "2", "3", "4", "5", "6", "7", |
191 | "8", "9", "10", "11", "12", "13", "14", "15", | |
192 | "16", "17", "18", "19", "20", "21", "22", "23", | |
193 | "24", "25", "26", "27", "28", "29", "30", "31", | |
0ac081f6 | 194 | "vrsave" |
c81bebd7 MM |
195 | }; |
196 | ||
197 | #ifdef TARGET_REGNAMES | |
8b60264b | 198 | static const char alt_reg_names[][8] = |
c81bebd7 | 199 | { |
802a0058 MM |
200 | "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7", |
201 | "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15", | |
202 | "%r16", "%r17", "%r18", "%r19", "%r20", "%r21", "%r22", "%r23", | |
203 | "%r24", "%r25", "%r26", "%r27", "%r28", "%r29", "%r30", "%r31", | |
204 | "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7", | |
205 | "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15", | |
206 | "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23", | |
207 | "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31", | |
208 | "mq", "lr", "ctr", "ap", | |
209 | "%cr0", "%cr1", "%cr2", "%cr3", "%cr4", "%cr5", "%cr6", "%cr7", | |
0ac081f6 AH |
210 | "xer", |
211 | /* AltiVec registers. */ | |
212 | "%v0", "%v1", "%v2", "%v3", "%v4", "%v5", "%v6", "%v7", | |
213 | "%v8", "%v9", "%v10", "%v11", "%v12", "%v13", "%v14", "%v15", | |
214 | "%v16", "%v17", "%v18", "%v19", "%v20", "%v21", "%v22", "%v23", | |
215 | "%v24", "%v25", "%v26", "%v27", "%v28", "%v29", "%v30", "%v31", | |
216 | "%vrsave" | |
c81bebd7 MM |
217 | }; |
218 | #endif | |
9878760c | 219 | \f |
daf11973 MM |
220 | #ifndef MASK_STRICT_ALIGN |
221 | #define MASK_STRICT_ALIGN 0 | |
222 | #endif | |
672a6f42 NB |
223 | \f |
224 | /* Initialize the GCC target structure. */ | |
91d231cb JM |
225 | #undef TARGET_ATTRIBUTE_TABLE |
226 | #define TARGET_ATTRIBUTE_TABLE rs6000_attribute_table | |
daf11973 | 227 | |
301d03af RS |
228 | #undef TARGET_ASM_ALIGNED_DI_OP |
229 | #define TARGET_ASM_ALIGNED_DI_OP DOUBLE_INT_ASM_OP | |
230 | ||
231 | /* Default unaligned ops are only provided for ELF. Find the ops needed | |
232 | for non-ELF systems. */ | |
233 | #ifndef OBJECT_FORMAT_ELF | |
234 | #ifdef OBJECT_FORMAT_COFF | |
ae6c1efd | 235 | /* For XCOFF. rs6000_assemble_integer will handle unaligned DIs on |
301d03af RS |
236 | 64-bit targets. */ |
237 | #undef TARGET_ASM_UNALIGNED_HI_OP | |
238 | #define TARGET_ASM_UNALIGNED_HI_OP "\t.vbyte\t2," | |
239 | #undef TARGET_ASM_UNALIGNED_SI_OP | |
240 | #define TARGET_ASM_UNALIGNED_SI_OP "\t.vbyte\t4," | |
241 | #undef TARGET_ASM_UNALIGNED_DI_OP | |
242 | #define TARGET_ASM_UNALIGNED_DI_OP "\t.vbyte\t8," | |
243 | #else | |
244 | /* For Darwin. */ | |
245 | #undef TARGET_ASM_UNALIGNED_HI_OP | |
246 | #define TARGET_ASM_UNALIGNED_HI_OP "\t.short\t" | |
247 | #undef TARGET_ASM_UNALIGNED_SI_OP | |
248 | #define TARGET_ASM_UNALIGNED_SI_OP "\t.long\t" | |
249 | #endif | |
250 | #endif | |
251 | ||
252 | /* This hook deals with fixups for relocatable code and DI-mode objects | |
253 | in 64-bit code. */ | |
254 | #undef TARGET_ASM_INTEGER | |
255 | #define TARGET_ASM_INTEGER rs6000_assemble_integer | |
256 | ||
08c148a8 NB |
257 | #undef TARGET_ASM_FUNCTION_PROLOGUE |
258 | #define TARGET_ASM_FUNCTION_PROLOGUE rs6000_output_function_prologue | |
259 | #undef TARGET_ASM_FUNCTION_EPILOGUE | |
260 | #define TARGET_ASM_FUNCTION_EPILOGUE rs6000_output_function_epilogue | |
261 | ||
7c262518 RH |
262 | #if TARGET_ELF |
263 | #undef TARGET_SECTION_TYPE_FLAGS | |
264 | #define TARGET_SECTION_TYPE_FLAGS rs6000_elf_section_type_flags | |
265 | #endif | |
266 | ||
c237e94a ZW |
267 | #undef TARGET_SCHED_ISSUE_RATE |
268 | #define TARGET_SCHED_ISSUE_RATE rs6000_issue_rate | |
269 | #undef TARGET_SCHED_ADJUST_COST | |
270 | #define TARGET_SCHED_ADJUST_COST rs6000_adjust_cost | |
271 | #undef TARGET_SCHED_ADJUST_PRIORITY | |
272 | #define TARGET_SCHED_ADJUST_PRIORITY rs6000_adjust_priority | |
273 | ||
0ac081f6 AH |
274 | #undef TARGET_INIT_BUILTINS |
275 | #define TARGET_INIT_BUILTINS rs6000_init_builtins | |
276 | ||
277 | #undef TARGET_EXPAND_BUILTIN | |
278 | #define TARGET_EXPAND_BUILTIN rs6000_expand_builtin | |
279 | ||
00b960c7 AH |
280 | /* The VRSAVE bitmask puts bit %v0 as the most significant bit. */ |
281 | #define ALTIVEC_REG_BIT(REGNO) (0x80000000 >> ((REGNO) - FIRST_ALTIVEC_REGNO)) | |
282 | ||
f6897b10 | 283 | struct gcc_target targetm = TARGET_INITIALIZER; |
672a6f42 | 284 | \f |
5248c961 RK |
285 | /* Override command line options. Mostly we process the processor |
286 | type and sometimes adjust other TARGET_ options. */ | |
287 | ||
288 | void | |
8e3f41e7 | 289 | rs6000_override_options (default_cpu) |
d330fd93 | 290 | const char *default_cpu; |
5248c961 | 291 | { |
c4d38ccb | 292 | size_t i, j; |
8e3f41e7 | 293 | struct rs6000_cpu_select *ptr; |
5248c961 | 294 | |
85638c0d RK |
295 | /* Simplify the entries below by making a mask for any POWER |
296 | variant and any PowerPC variant. */ | |
297 | ||
938937d8 | 298 | #define POWER_MASKS (MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING) |
68c49ffa RK |
299 | #define POWERPC_MASKS (MASK_POWERPC | MASK_PPC_GPOPT \ |
300 | | MASK_PPC_GFXOPT | MASK_POWERPC64) | |
301 | #define POWERPC_OPT_MASKS (MASK_PPC_GPOPT | MASK_PPC_GFXOPT) | |
85638c0d | 302 | |
5248c961 RK |
303 | static struct ptt |
304 | { | |
8b60264b KG |
305 | const char *const name; /* Canonical processor name. */ |
306 | const enum processor_type processor; /* Processor type enum value. */ | |
307 | const int target_enable; /* Target flags to enable. */ | |
308 | const int target_disable; /* Target flags to disable. */ | |
309 | } const processor_target_table[] | |
cf27b467 MM |
310 | = {{"common", PROCESSOR_COMMON, MASK_NEW_MNEMONICS, |
311 | POWER_MASKS | POWERPC_MASKS}, | |
db7f1e43 | 312 | {"power", PROCESSOR_POWER, |
938937d8 | 313 | MASK_POWER | MASK_MULTIPLE | MASK_STRING, |
db7f1e43 | 314 | MASK_POWER2 | POWERPC_MASKS | MASK_NEW_MNEMONICS}, |
8e3f41e7 MM |
315 | {"power2", PROCESSOR_POWER, |
316 | MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING, | |
317 | POWERPC_MASKS | MASK_NEW_MNEMONICS}, | |
c71791e0 DE |
318 | {"power3", PROCESSOR_PPC630, |
319 | MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS, | |
320 | POWER_MASKS | MASK_PPC_GPOPT}, | |
db7f1e43 RK |
321 | {"powerpc", PROCESSOR_POWERPC, |
322 | MASK_POWERPC | MASK_NEW_MNEMONICS, | |
68c49ffa | 323 | POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64}, |
3cb999d8 DE |
324 | {"powerpc64", PROCESSOR_POWERPC64, |
325 | MASK_POWERPC | MASK_POWERPC64 | MASK_NEW_MNEMONICS, | |
326 | POWER_MASKS | POWERPC_OPT_MASKS}, | |
db7f1e43 | 327 | {"rios", PROCESSOR_RIOS1, |
938937d8 | 328 | MASK_POWER | MASK_MULTIPLE | MASK_STRING, |
db7f1e43 RK |
329 | MASK_POWER2 | POWERPC_MASKS | MASK_NEW_MNEMONICS}, |
330 | {"rios1", PROCESSOR_RIOS1, | |
938937d8 | 331 | MASK_POWER | MASK_MULTIPLE | MASK_STRING, |
db7f1e43 RK |
332 | MASK_POWER2 | POWERPC_MASKS | MASK_NEW_MNEMONICS}, |
333 | {"rsc", PROCESSOR_PPC601, | |
938937d8 | 334 | MASK_POWER | MASK_MULTIPLE | MASK_STRING, |
db7f1e43 RK |
335 | MASK_POWER2 | POWERPC_MASKS | MASK_NEW_MNEMONICS}, |
336 | {"rsc1", PROCESSOR_PPC601, | |
938937d8 | 337 | MASK_POWER | MASK_MULTIPLE | MASK_STRING, |
db7f1e43 RK |
338 | MASK_POWER2 | POWERPC_MASKS | MASK_NEW_MNEMONICS}, |
339 | {"rios2", PROCESSOR_RIOS2, | |
938937d8 | 340 | MASK_POWER | MASK_MULTIPLE | MASK_STRING | MASK_POWER2, |
db7f1e43 | 341 | POWERPC_MASKS | MASK_NEW_MNEMONICS}, |
3cb999d8 DE |
342 | {"rs64a", PROCESSOR_RS64A, |
343 | MASK_POWERPC | MASK_NEW_MNEMONICS, | |
344 | POWER_MASKS | POWERPC_OPT_MASKS}, | |
a3a1dbf6 MM |
345 | {"401", PROCESSOR_PPC403, |
346 | MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS, | |
347 | POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64}, | |
49a0b204 | 348 | {"403", PROCESSOR_PPC403, |
daf11973 | 349 | MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS | MASK_STRICT_ALIGN, |
49a0b204 | 350 | POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64}, |
d7a5e253 DE |
351 | {"405", PROCESSOR_PPC405, |
352 | MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS, | |
353 | POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64}, | |
cf27b467 MM |
354 | {"505", PROCESSOR_MPCCORE, |
355 | MASK_POWERPC | MASK_NEW_MNEMONICS, | |
356 | POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64}, | |
5248c961 | 357 | {"601", PROCESSOR_PPC601, |
938937d8 | 358 | MASK_POWER | MASK_POWERPC | MASK_NEW_MNEMONICS | MASK_MULTIPLE | MASK_STRING, |
68c49ffa | 359 | MASK_POWER2 | POWERPC_OPT_MASKS | MASK_POWERPC64}, |
1ec26da6 | 360 | {"602", PROCESSOR_PPC603, |
cf27b467 MM |
361 | MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS, |
362 | POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64}, | |
5248c961 | 363 | {"603", PROCESSOR_PPC603, |
68c49ffa RK |
364 | MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS, |
365 | POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64}, | |
b6c9286a MM |
366 | {"603e", PROCESSOR_PPC603, |
367 | MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS, | |
368 | POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64}, | |
b5370a88 | 369 | {"ec603e", PROCESSOR_PPC603, |
a3a1dbf6 MM |
370 | MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS, |
371 | POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64}, | |
5248c961 | 372 | {"604", PROCESSOR_PPC604, |
b6c9286a MM |
373 | MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS, |
374 | POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64}, | |
cac8ce95 | 375 | {"604e", PROCESSOR_PPC604e, |
07e6159a MM |
376 | MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS, |
377 | POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64}, | |
b6c9286a | 378 | {"620", PROCESSOR_PPC620, |
68c49ffa | 379 | MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS, |
a260abc9 | 380 | POWER_MASKS | MASK_PPC_GPOPT}, |
3cb999d8 DE |
381 | {"630", PROCESSOR_PPC630, |
382 | MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS, | |
383 | POWER_MASKS | MASK_PPC_GPOPT}, | |
bef84347 VM |
384 | {"740", PROCESSOR_PPC750, |
385 | MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS, | |
386 | POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64}, | |
387 | {"750", PROCESSOR_PPC750, | |
388 | MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS, | |
389 | POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64}, | |
a4f6c312 SS |
390 | {"7400", PROCESSOR_PPC7400, |
391 | MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS, | |
392 | POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64}, | |
393 | {"7450", PROCESSOR_PPC7450, | |
394 | MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS, | |
395 | POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64}, | |
07e6159a MM |
396 | {"801", PROCESSOR_MPCCORE, |
397 | MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS, | |
398 | POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64}, | |
cf27b467 MM |
399 | {"821", PROCESSOR_MPCCORE, |
400 | MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS, | |
401 | POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64}, | |
07e6159a MM |
402 | {"823", PROCESSOR_MPCCORE, |
403 | MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS, | |
404 | POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64}, | |
cf27b467 MM |
405 | {"860", PROCESSOR_MPCCORE, |
406 | MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS, | |
407 | POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64}}; | |
5248c961 | 408 | |
c4d38ccb | 409 | size_t ptt_size = sizeof (processor_target_table) / sizeof (struct ptt); |
5248c961 | 410 | |
a4f6c312 SS |
411 | /* Save current -mmultiple/-mno-multiple status. */ |
412 | int multiple = TARGET_MULTIPLE; | |
413 | /* Save current -mstring/-mno-string status. */ | |
414 | int string = TARGET_STRING; | |
8a61d227 | 415 | |
a4f6c312 | 416 | /* Identify the processor type. */ |
8e3f41e7 | 417 | rs6000_select[0].string = default_cpu; |
3cb999d8 | 418 | rs6000_cpu = TARGET_POWERPC64 ? PROCESSOR_DEFAULT64 : PROCESSOR_DEFAULT; |
8e3f41e7 | 419 | |
b6a1cbae | 420 | for (i = 0; i < ARRAY_SIZE (rs6000_select); i++) |
5248c961 | 421 | { |
8e3f41e7 MM |
422 | ptr = &rs6000_select[i]; |
423 | if (ptr->string != (char *)0 && ptr->string[0] != '\0') | |
5248c961 | 424 | { |
8e3f41e7 MM |
425 | for (j = 0; j < ptt_size; j++) |
426 | if (! strcmp (ptr->string, processor_target_table[j].name)) | |
427 | { | |
428 | if (ptr->set_tune_p) | |
429 | rs6000_cpu = processor_target_table[j].processor; | |
430 | ||
431 | if (ptr->set_arch_p) | |
432 | { | |
433 | target_flags |= processor_target_table[j].target_enable; | |
434 | target_flags &= ~processor_target_table[j].target_disable; | |
435 | } | |
436 | break; | |
437 | } | |
438 | ||
4406229e | 439 | if (j == ptt_size) |
8e3f41e7 | 440 | error ("bad value (%s) for %s switch", ptr->string, ptr->name); |
5248c961 RK |
441 | } |
442 | } | |
8a61d227 | 443 | |
a4f6c312 SS |
444 | /* If we are optimizing big endian systems for space, use the store |
445 | multiple instructions. */ | |
ef792183 MM |
446 | if (BYTES_BIG_ENDIAN && optimize_size) |
447 | target_flags |= MASK_MULTIPLE; | |
448 | ||
8a61d227 MM |
449 | /* If -mmultiple or -mno-multiple was explicitly used, don't |
450 | override with the processor default */ | |
451 | if (TARGET_MULTIPLE_SET) | |
452 | target_flags = (target_flags & ~MASK_MULTIPLE) | multiple; | |
7e69e155 | 453 | |
a4f6c312 SS |
454 | /* If -mstring or -mno-string was explicitly used, don't override |
455 | with the processor default. */ | |
938937d8 | 456 | if (TARGET_STRING_SET) |
1f5515bf | 457 | target_flags = (target_flags & ~MASK_STRING) | string; |
938937d8 | 458 | |
a4f6c312 SS |
459 | /* Don't allow -mmultiple or -mstring on little endian systems |
460 | unless the cpu is a 750, because the hardware doesn't support the | |
461 | instructions used in little endian mode, and causes an alignment | |
462 | trap. The 750 does not cause an alignment trap (except when the | |
463 | target is unaligned). */ | |
bef84347 | 464 | |
bfc79d3b | 465 | if (! BYTES_BIG_ENDIAN && rs6000_cpu != PROCESSOR_PPC750) |
7e69e155 MM |
466 | { |
467 | if (TARGET_MULTIPLE) | |
468 | { | |
469 | target_flags &= ~MASK_MULTIPLE; | |
470 | if (TARGET_MULTIPLE_SET) | |
471 | warning ("-mmultiple is not supported on little endian systems"); | |
472 | } | |
473 | ||
474 | if (TARGET_STRING) | |
475 | { | |
476 | target_flags &= ~MASK_STRING; | |
938937d8 MM |
477 | if (TARGET_STRING_SET) |
478 | warning ("-mstring is not supported on little endian systems"); | |
7e69e155 MM |
479 | } |
480 | } | |
3933e0e1 | 481 | |
2bfcf297 | 482 | if (flag_pic && DEFAULT_ABI == ABI_AIX) |
a260abc9 | 483 | { |
2bfcf297 | 484 | warning ("-f%s ignored (all code is position independent)", |
a260abc9 DE |
485 | (flag_pic > 1) ? "PIC" : "pic"); |
486 | flag_pic = 0; | |
487 | } | |
488 | ||
2bfcf297 | 489 | #ifdef XCOFF_DEBUGGING_INFO |
9861b0c9 | 490 | if (flag_function_sections && (write_symbols != NO_DEBUG) |
2bfcf297 | 491 | && DEFAULT_ABI == ABI_AIX) |
9861b0c9 DE |
492 | { |
493 | warning ("-ffunction-sections disabled on AIX when debugging"); | |
494 | flag_function_sections = 0; | |
495 | } | |
496 | ||
497 | if (flag_data_sections && (DEFAULT_ABI == ABI_AIX)) | |
498 | { | |
499 | warning ("-fdata-sections not supported on AIX"); | |
500 | flag_data_sections = 0; | |
501 | } | |
2bfcf297 | 502 | #endif |
9861b0c9 | 503 | |
38c1f2d7 MM |
504 | /* Set debug flags */ |
505 | if (rs6000_debug_name) | |
506 | { | |
bfc79d3b | 507 | if (! strcmp (rs6000_debug_name, "all")) |
38c1f2d7 | 508 | rs6000_debug_stack = rs6000_debug_arg = 1; |
bfc79d3b | 509 | else if (! strcmp (rs6000_debug_name, "stack")) |
38c1f2d7 | 510 | rs6000_debug_stack = 1; |
bfc79d3b | 511 | else if (! strcmp (rs6000_debug_name, "arg")) |
38c1f2d7 MM |
512 | rs6000_debug_arg = 1; |
513 | else | |
c725bd79 | 514 | error ("unknown -mdebug-%s switch", rs6000_debug_name); |
38c1f2d7 MM |
515 | } |
516 | ||
6fa3f289 ZW |
517 | /* Set size of long double */ |
518 | rs6000_long_double_type_size = 64; | |
519 | if (rs6000_long_double_size_string) | |
520 | { | |
521 | char *tail; | |
522 | int size = strtol (rs6000_long_double_size_string, &tail, 10); | |
523 | if (*tail != '\0' || (size != 64 && size != 128)) | |
524 | error ("Unknown switch -mlong-double-%s", | |
525 | rs6000_long_double_size_string); | |
526 | else | |
527 | rs6000_long_double_type_size = size; | |
528 | } | |
529 | ||
0ac081f6 AH |
530 | /* Handle -mabi= options. */ |
531 | rs6000_parse_abi_options (); | |
532 | ||
c81bebd7 | 533 | #ifdef TARGET_REGNAMES |
a4f6c312 SS |
534 | /* If the user desires alternate register names, copy in the |
535 | alternate names now. */ | |
c81bebd7 | 536 | if (TARGET_REGNAMES) |
4e135bdd | 537 | memcpy (rs6000_reg_names, alt_reg_names, sizeof (rs6000_reg_names)); |
c81bebd7 MM |
538 | #endif |
539 | ||
3933e0e1 MM |
540 | #ifdef SUBTARGET_OVERRIDE_OPTIONS |
541 | SUBTARGET_OVERRIDE_OPTIONS; | |
542 | #endif | |
10baca6b AH |
543 | #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS |
544 | SUBSUBTARGET_OVERRIDE_OPTIONS; | |
545 | #endif | |
c8023011 | 546 | |
6fa3f289 ZW |
547 | /* Set TARGET_AIX_STRUCT_RET last, after the ABI is determined. |
548 | If -maix-struct-return or -msvr4-struct-return was explicitly | |
549 | used, don't override with the ABI default. */ | |
550 | if (!(target_flags & MASK_AIX_STRUCT_RET_SET)) | |
551 | { | |
552 | if (DEFAULT_ABI == ABI_V4 && !DRAFT_V4_STRUCT_RET) | |
553 | target_flags = (target_flags & ~MASK_AIX_STRUCT_RET); | |
554 | else | |
555 | target_flags |= MASK_AIX_STRUCT_RET; | |
556 | } | |
557 | ||
c8023011 MM |
558 | /* Register global variables with the garbage collector. */ |
559 | rs6000_add_gc_roots (); | |
9ebbca7d GK |
560 | |
561 | /* Allocate an alias set for register saves & restores from stack. */ | |
562 | rs6000_sr_alias_set = new_alias_set (); | |
563 | ||
564 | if (TARGET_TOC) | |
565 | ASM_GENERATE_INTERNAL_LABEL (toc_label_name, "LCTOC", 1); | |
71f123ca | 566 | |
301d03af RS |
567 | /* We can only guarantee the availability of DI pseudo-ops when |
568 | assembling for 64-bit targets. */ | |
ae6c1efd | 569 | if (!TARGET_64BIT) |
301d03af RS |
570 | { |
571 | targetm.asm_out.aligned_op.di = NULL; | |
572 | targetm.asm_out.unaligned_op.di = NULL; | |
573 | } | |
574 | ||
71f123ca FS |
575 | /* Arrange to save and restore machine status around nested functions. */ |
576 | init_machine_status = rs6000_init_machine_status; | |
71f123ca | 577 | free_machine_status = rs6000_free_machine_status; |
5248c961 | 578 | } |
5accd822 | 579 | |
0ac081f6 | 580 | /* Handle -mabi= options. */ |
00b960c7 AH |
581 | static void |
582 | rs6000_parse_abi_options () | |
0ac081f6 AH |
583 | { |
584 | if (rs6000_abi_string == 0) | |
585 | return; | |
586 | else if (! strcmp (rs6000_abi_string, "altivec")) | |
6fa3f289 | 587 | rs6000_altivec_abi = 1; |
0ac081f6 | 588 | else |
c725bd79 | 589 | error ("unknown ABI specified: '%s'", rs6000_abi_string); |
0ac081f6 AH |
590 | } |
591 | ||
5accd822 DE |
592 | void |
593 | optimization_options (level, size) | |
e2c953b6 | 594 | int level ATTRIBUTE_UNUSED; |
5accd822 DE |
595 | int size ATTRIBUTE_UNUSED; |
596 | { | |
5accd822 | 597 | } |
3cfa4909 MM |
598 | \f |
599 | /* Do anything needed at the start of the asm file. */ | |
600 | ||
601 | void | |
602 | rs6000_file_start (file, default_cpu) | |
603 | FILE *file; | |
d330fd93 | 604 | const char *default_cpu; |
3cfa4909 | 605 | { |
c4d38ccb | 606 | size_t i; |
3cfa4909 | 607 | char buffer[80]; |
d330fd93 | 608 | const char *start = buffer; |
3cfa4909 MM |
609 | struct rs6000_cpu_select *ptr; |
610 | ||
611 | if (flag_verbose_asm) | |
612 | { | |
613 | sprintf (buffer, "\n%s rs6000/powerpc options:", ASM_COMMENT_START); | |
614 | rs6000_select[0].string = default_cpu; | |
615 | ||
b6a1cbae | 616 | for (i = 0; i < ARRAY_SIZE (rs6000_select); i++) |
3cfa4909 MM |
617 | { |
618 | ptr = &rs6000_select[i]; | |
619 | if (ptr->string != (char *)0 && ptr->string[0] != '\0') | |
620 | { | |
621 | fprintf (file, "%s %s%s", start, ptr->name, ptr->string); | |
622 | start = ""; | |
623 | } | |
624 | } | |
625 | ||
b91da81f | 626 | #ifdef USING_ELFOS_H |
3cfa4909 MM |
627 | switch (rs6000_sdata) |
628 | { | |
629 | case SDATA_NONE: fprintf (file, "%s -msdata=none", start); start = ""; break; | |
630 | case SDATA_DATA: fprintf (file, "%s -msdata=data", start); start = ""; break; | |
631 | case SDATA_SYSV: fprintf (file, "%s -msdata=sysv", start); start = ""; break; | |
632 | case SDATA_EABI: fprintf (file, "%s -msdata=eabi", start); start = ""; break; | |
633 | } | |
634 | ||
635 | if (rs6000_sdata && g_switch_value) | |
636 | { | |
637 | fprintf (file, "%s -G %d", start, g_switch_value); | |
638 | start = ""; | |
639 | } | |
640 | #endif | |
641 | ||
642 | if (*start == '\0') | |
949ea356 | 643 | putc ('\n', file); |
3cfa4909 MM |
644 | } |
645 | } | |
646 | ||
24d304eb RK |
647 | \f |
648 | /* Create a CONST_DOUBLE from a string. */ | |
649 | ||
650 | struct rtx_def * | |
651 | rs6000_float_const (string, mode) | |
d330fd93 | 652 | const char *string; |
24d304eb RK |
653 | enum machine_mode mode; |
654 | { | |
ca5adc63 GK |
655 | REAL_VALUE_TYPE value; |
656 | value = REAL_VALUE_ATOF (string, mode); | |
24d304eb RK |
657 | return immed_real_const_1 (value, mode); |
658 | } | |
5248c961 | 659 | \f |
9878760c RK |
660 | /* Return non-zero if this function is known to have a null epilogue. */ |
661 | ||
662 | int | |
663 | direct_return () | |
664 | { | |
4697a36c MM |
665 | if (reload_completed) |
666 | { | |
667 | rs6000_stack_t *info = rs6000_stack_info (); | |
668 | ||
669 | if (info->first_gp_reg_save == 32 | |
670 | && info->first_fp_reg_save == 64 | |
00b960c7 | 671 | && info->first_altivec_reg_save == LAST_ALTIVEC_REGNO + 1 |
c81fc13e DE |
672 | && ! info->lr_save_p |
673 | && ! info->cr_save_p | |
00b960c7 | 674 | && info->vrsave_mask == 0 |
c81fc13e | 675 | && ! info->push_p) |
4697a36c MM |
676 | return 1; |
677 | } | |
678 | ||
679 | return 0; | |
9878760c RK |
680 | } |
681 | ||
682 | /* Returns 1 always. */ | |
683 | ||
684 | int | |
685 | any_operand (op, mode) | |
592696dd | 686 | rtx op ATTRIBUTE_UNUSED; |
296b8152 | 687 | enum machine_mode mode ATTRIBUTE_UNUSED; |
9878760c RK |
688 | { |
689 | return 1; | |
690 | } | |
691 | ||
a4f6c312 | 692 | /* Returns 1 if op is the count register. */ |
38c1f2d7 | 693 | int |
a4f6c312 | 694 | count_register_operand (op, mode) |
592696dd | 695 | rtx op; |
296b8152 | 696 | enum machine_mode mode ATTRIBUTE_UNUSED; |
b6c9286a MM |
697 | { |
698 | if (GET_CODE (op) != REG) | |
699 | return 0; | |
700 | ||
701 | if (REGNO (op) == COUNT_REGISTER_REGNUM) | |
702 | return 1; | |
703 | ||
704 | if (REGNO (op) > FIRST_PSEUDO_REGISTER) | |
705 | return 1; | |
706 | ||
707 | return 0; | |
708 | } | |
709 | ||
38c1f2d7 | 710 | int |
a4f6c312 | 711 | xer_operand (op, mode) |
592696dd | 712 | rtx op; |
296b8152 | 713 | enum machine_mode mode ATTRIBUTE_UNUSED; |
802a0058 MM |
714 | { |
715 | if (GET_CODE (op) != REG) | |
716 | return 0; | |
717 | ||
9ebbca7d | 718 | if (XER_REGNO_P (REGNO (op))) |
802a0058 MM |
719 | return 1; |
720 | ||
802a0058 MM |
721 | return 0; |
722 | } | |
723 | ||
c859cda6 | 724 | /* Return 1 if OP is a signed 8-bit constant. Int multiplication |
6f317ef3 | 725 | by such constants completes more quickly. */ |
c859cda6 DJ |
726 | |
727 | int | |
728 | s8bit_cint_operand (op, mode) | |
729 | rtx op; | |
730 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
731 | { | |
732 | return ( GET_CODE (op) == CONST_INT | |
733 | && (INTVAL (op) >= -128 && INTVAL (op) <= 127)); | |
734 | } | |
735 | ||
9878760c RK |
736 | /* Return 1 if OP is a constant that can fit in a D field. */ |
737 | ||
738 | int | |
739 | short_cint_operand (op, mode) | |
592696dd | 740 | rtx op; |
296b8152 | 741 | enum machine_mode mode ATTRIBUTE_UNUSED; |
9878760c | 742 | { |
5f59ecb7 DE |
743 | return (GET_CODE (op) == CONST_INT |
744 | && CONST_OK_FOR_LETTER_P (INTVAL (op), 'I')); | |
9878760c RK |
745 | } |
746 | ||
5519a4f9 | 747 | /* Similar for an unsigned D field. */ |
9878760c RK |
748 | |
749 | int | |
750 | u_short_cint_operand (op, mode) | |
592696dd | 751 | rtx op; |
296b8152 | 752 | enum machine_mode mode ATTRIBUTE_UNUSED; |
9878760c | 753 | { |
19684119 | 754 | return (GET_CODE (op) == CONST_INT |
5f59ecb7 | 755 | && CONST_OK_FOR_LETTER_P (INTVAL (op), 'K')); |
9878760c RK |
756 | } |
757 | ||
dcfedcd0 RK |
758 | /* Return 1 if OP is a CONST_INT that cannot fit in a signed D field. */ |
759 | ||
760 | int | |
761 | non_short_cint_operand (op, mode) | |
592696dd | 762 | rtx op; |
296b8152 | 763 | enum machine_mode mode ATTRIBUTE_UNUSED; |
dcfedcd0 RK |
764 | { |
765 | return (GET_CODE (op) == CONST_INT | |
a7653a2c | 766 | && (unsigned HOST_WIDE_INT) (INTVAL (op) + 0x8000) >= 0x10000); |
dcfedcd0 RK |
767 | } |
768 | ||
2bfcf297 DB |
769 | /* Returns 1 if OP is a CONST_INT that is a positive value |
770 | and an exact power of 2. */ | |
771 | ||
772 | int | |
773 | exact_log2_cint_operand (op, mode) | |
592696dd | 774 | rtx op; |
2bfcf297 DB |
775 | enum machine_mode mode ATTRIBUTE_UNUSED; |
776 | { | |
777 | return (GET_CODE (op) == CONST_INT | |
778 | && INTVAL (op) > 0 | |
779 | && exact_log2 (INTVAL (op)) >= 0); | |
780 | } | |
781 | ||
9878760c RK |
782 | /* Returns 1 if OP is a register that is not special (i.e., not MQ, |
783 | ctr, or lr). */ | |
784 | ||
785 | int | |
cd2b37d9 | 786 | gpc_reg_operand (op, mode) |
592696dd | 787 | rtx op; |
9878760c RK |
788 | enum machine_mode mode; |
789 | { | |
790 | return (register_operand (op, mode) | |
802a0058 | 791 | && (GET_CODE (op) != REG |
9ebbca7d GK |
792 | || (REGNO (op) >= ARG_POINTER_REGNUM |
793 | && !XER_REGNO_P (REGNO (op))) | |
794 | || REGNO (op) < MQ_REGNO)); | |
9878760c RK |
795 | } |
796 | ||
797 | /* Returns 1 if OP is either a pseudo-register or a register denoting a | |
798 | CR field. */ | |
799 | ||
800 | int | |
801 | cc_reg_operand (op, mode) | |
592696dd | 802 | rtx op; |
9878760c RK |
803 | enum machine_mode mode; |
804 | { | |
805 | return (register_operand (op, mode) | |
806 | && (GET_CODE (op) != REG | |
807 | || REGNO (op) >= FIRST_PSEUDO_REGISTER | |
808 | || CR_REGNO_P (REGNO (op)))); | |
809 | } | |
810 | ||
815cdc52 MM |
811 | /* Returns 1 if OP is either a pseudo-register or a register denoting a |
812 | CR field that isn't CR0. */ | |
813 | ||
814 | int | |
815 | cc_reg_not_cr0_operand (op, mode) | |
592696dd | 816 | rtx op; |
815cdc52 MM |
817 | enum machine_mode mode; |
818 | { | |
819 | return (register_operand (op, mode) | |
820 | && (GET_CODE (op) != REG | |
821 | || REGNO (op) >= FIRST_PSEUDO_REGISTER | |
822 | || CR_REGNO_NOT_CR0_P (REGNO (op)))); | |
823 | } | |
824 | ||
a4f6c312 SS |
825 | /* Returns 1 if OP is either a constant integer valid for a D-field or |
826 | a non-special register. If a register, it must be in the proper | |
827 | mode unless MODE is VOIDmode. */ | |
9878760c RK |
828 | |
829 | int | |
830 | reg_or_short_operand (op, mode) | |
592696dd | 831 | rtx op; |
9878760c RK |
832 | enum machine_mode mode; |
833 | { | |
f5a28898 | 834 | return short_cint_operand (op, mode) || gpc_reg_operand (op, mode); |
9878760c RK |
835 | } |
836 | ||
a4f6c312 SS |
837 | /* Similar, except check if the negation of the constant would be |
838 | valid for a D-field. */ | |
9878760c RK |
839 | |
840 | int | |
841 | reg_or_neg_short_operand (op, mode) | |
592696dd | 842 | rtx op; |
9878760c RK |
843 | enum machine_mode mode; |
844 | { | |
845 | if (GET_CODE (op) == CONST_INT) | |
846 | return CONST_OK_FOR_LETTER_P (INTVAL (op), 'P'); | |
847 | ||
cd2b37d9 | 848 | return gpc_reg_operand (op, mode); |
9878760c RK |
849 | } |
850 | ||
a4f6c312 SS |
851 | /* Return 1 if the operand is either a register or an integer whose |
852 | high-order 16 bits are zero. */ | |
9878760c RK |
853 | |
854 | int | |
855 | reg_or_u_short_operand (op, mode) | |
592696dd | 856 | rtx op; |
9878760c RK |
857 | enum machine_mode mode; |
858 | { | |
e675f625 | 859 | return u_short_cint_operand (op, mode) || gpc_reg_operand (op, mode); |
9878760c RK |
860 | } |
861 | ||
862 | /* Return 1 is the operand is either a non-special register or ANY | |
863 | constant integer. */ | |
864 | ||
865 | int | |
866 | reg_or_cint_operand (op, mode) | |
592696dd | 867 | rtx op; |
9878760c RK |
868 | enum machine_mode mode; |
869 | { | |
a4f6c312 | 870 | return (GET_CODE (op) == CONST_INT || gpc_reg_operand (op, mode)); |
f6bf7de2 DE |
871 | } |
872 | ||
873 | /* Return 1 is the operand is either a non-special register or ANY | |
874 | 32-bit signed constant integer. */ | |
875 | ||
876 | int | |
877 | reg_or_arith_cint_operand (op, mode) | |
592696dd | 878 | rtx op; |
f6bf7de2 DE |
879 | enum machine_mode mode; |
880 | { | |
a4f6c312 SS |
881 | return (gpc_reg_operand (op, mode) |
882 | || (GET_CODE (op) == CONST_INT | |
f6bf7de2 | 883 | #if HOST_BITS_PER_WIDE_INT != 32 |
a4f6c312 SS |
884 | && ((unsigned HOST_WIDE_INT) (INTVAL (op) + 0x80000000) |
885 | < (unsigned HOST_WIDE_INT) 0x100000000ll) | |
f6bf7de2 | 886 | #endif |
a4f6c312 | 887 | )); |
9878760c RK |
888 | } |
889 | ||
2bfcf297 DB |
890 | /* Return 1 is the operand is either a non-special register or a 32-bit |
891 | signed constant integer valid for 64-bit addition. */ | |
892 | ||
893 | int | |
894 | reg_or_add_cint64_operand (op, mode) | |
592696dd | 895 | rtx op; |
2bfcf297 DB |
896 | enum machine_mode mode; |
897 | { | |
a4f6c312 SS |
898 | return (gpc_reg_operand (op, mode) |
899 | || (GET_CODE (op) == CONST_INT | |
900 | && INTVAL (op) < 0x7fff8000 | |
2bfcf297 | 901 | #if HOST_BITS_PER_WIDE_INT != 32 |
a4f6c312 SS |
902 | && ((unsigned HOST_WIDE_INT) (INTVAL (op) + 0x80008000) |
903 | < 0x100000000ll) | |
2bfcf297 | 904 | #endif |
a4f6c312 | 905 | )); |
2bfcf297 DB |
906 | } |
907 | ||
908 | /* Return 1 is the operand is either a non-special register or a 32-bit | |
909 | signed constant integer valid for 64-bit subtraction. */ | |
910 | ||
911 | int | |
912 | reg_or_sub_cint64_operand (op, mode) | |
592696dd | 913 | rtx op; |
2bfcf297 DB |
914 | enum machine_mode mode; |
915 | { | |
a4f6c312 SS |
916 | return (gpc_reg_operand (op, mode) |
917 | || (GET_CODE (op) == CONST_INT | |
918 | && (- INTVAL (op)) < 0x7fff8000 | |
2bfcf297 | 919 | #if HOST_BITS_PER_WIDE_INT != 32 |
a4f6c312 SS |
920 | && ((unsigned HOST_WIDE_INT) ((- INTVAL (op)) + 0x80008000) |
921 | < 0x100000000ll) | |
2bfcf297 | 922 | #endif |
a4f6c312 | 923 | )); |
2bfcf297 DB |
924 | } |
925 | ||
9ebbca7d GK |
926 | /* Return 1 is the operand is either a non-special register or ANY |
927 | 32-bit unsigned constant integer. */ | |
928 | ||
929 | int | |
1d328b19 | 930 | reg_or_logical_cint_operand (op, mode) |
592696dd | 931 | rtx op; |
9ebbca7d GK |
932 | enum machine_mode mode; |
933 | { | |
1d328b19 GK |
934 | if (GET_CODE (op) == CONST_INT) |
935 | { | |
936 | if (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT) | |
937 | { | |
938 | if (GET_MODE_BITSIZE (mode) <= 32) | |
a4f6c312 | 939 | abort (); |
1d328b19 GK |
940 | |
941 | if (INTVAL (op) < 0) | |
942 | return 0; | |
943 | } | |
944 | ||
945 | return ((INTVAL (op) & GET_MODE_MASK (mode) | |
0858c623 | 946 | & (~ (unsigned HOST_WIDE_INT) 0xffffffff)) == 0); |
1d328b19 GK |
947 | } |
948 | else if (GET_CODE (op) == CONST_DOUBLE) | |
949 | { | |
950 | if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT | |
951 | || mode != DImode) | |
a4f6c312 | 952 | abort (); |
1d328b19 GK |
953 | |
954 | return CONST_DOUBLE_HIGH (op) == 0; | |
955 | } | |
956 | else | |
957 | return gpc_reg_operand (op, mode); | |
9ebbca7d GK |
958 | } |
959 | ||
51d3e7d6 | 960 | /* Return 1 if the operand is an operand that can be loaded via the GOT. */ |
766a866c MM |
961 | |
962 | int | |
963 | got_operand (op, mode) | |
592696dd | 964 | rtx op; |
296b8152 | 965 | enum machine_mode mode ATTRIBUTE_UNUSED; |
766a866c MM |
966 | { |
967 | return (GET_CODE (op) == SYMBOL_REF | |
968 | || GET_CODE (op) == CONST | |
969 | || GET_CODE (op) == LABEL_REF); | |
970 | } | |
971 | ||
38c1f2d7 MM |
972 | /* Return 1 if the operand is a simple references that can be loaded via |
973 | the GOT (labels involving addition aren't allowed). */ | |
974 | ||
975 | int | |
976 | got_no_const_operand (op, mode) | |
592696dd | 977 | rtx op; |
296b8152 | 978 | enum machine_mode mode ATTRIBUTE_UNUSED; |
38c1f2d7 MM |
979 | { |
980 | return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF); | |
981 | } | |
982 | ||
4e74d8ec MM |
983 | /* Return the number of instructions it takes to form a constant in an |
984 | integer register. */ | |
985 | ||
986 | static int | |
987 | num_insns_constant_wide (value) | |
988 | HOST_WIDE_INT value; | |
989 | { | |
990 | /* signed constant loadable with {cal|addi} */ | |
5f59ecb7 | 991 | if (CONST_OK_FOR_LETTER_P (value, 'I')) |
0865c631 GK |
992 | return 1; |
993 | ||
4e74d8ec | 994 | /* constant loadable with {cau|addis} */ |
5f59ecb7 | 995 | else if (CONST_OK_FOR_LETTER_P (value, 'L')) |
4e74d8ec MM |
996 | return 1; |
997 | ||
5f59ecb7 | 998 | #if HOST_BITS_PER_WIDE_INT == 64 |
c81fc13e | 999 | else if (TARGET_POWERPC64) |
4e74d8ec | 1000 | { |
0d30d435 | 1001 | HOST_WIDE_INT low = value & 0xffffffff; |
4e74d8ec MM |
1002 | HOST_WIDE_INT high = value >> 32; |
1003 | ||
0d30d435 DE |
1004 | low = (low ^ 0x80000000) - 0x80000000; /* sign extend */ |
1005 | ||
0858c623 | 1006 | if (high == 0 && (low & 0x80000000) == 0) |
4e74d8ec MM |
1007 | return 2; |
1008 | ||
0858c623 | 1009 | else if (high == -1 && (low & 0x80000000) != 0) |
4e74d8ec MM |
1010 | return 2; |
1011 | ||
c81fc13e | 1012 | else if (! low) |
4e74d8ec MM |
1013 | return num_insns_constant_wide (high) + 1; |
1014 | ||
1015 | else | |
1016 | return (num_insns_constant_wide (high) | |
e396202a | 1017 | + num_insns_constant_wide (low) + 1); |
4e74d8ec MM |
1018 | } |
1019 | #endif | |
1020 | ||
1021 | else | |
1022 | return 2; | |
1023 | } | |
1024 | ||
1025 | int | |
1026 | num_insns_constant (op, mode) | |
1027 | rtx op; | |
1028 | enum machine_mode mode; | |
1029 | { | |
4e74d8ec | 1030 | if (GET_CODE (op) == CONST_INT) |
0d30d435 DE |
1031 | { |
1032 | #if HOST_BITS_PER_WIDE_INT == 64 | |
4e2c1c44 DE |
1033 | if ((INTVAL (op) >> 31) != 0 && (INTVAL (op) >> 31) != -1 |
1034 | && mask64_operand (op, mode)) | |
0d30d435 DE |
1035 | return 2; |
1036 | else | |
1037 | #endif | |
1038 | return num_insns_constant_wide (INTVAL (op)); | |
1039 | } | |
4e74d8ec | 1040 | |
6fc48950 MM |
1041 | else if (GET_CODE (op) == CONST_DOUBLE && mode == SFmode) |
1042 | { | |
1043 | long l; | |
1044 | REAL_VALUE_TYPE rv; | |
1045 | ||
1046 | REAL_VALUE_FROM_CONST_DOUBLE (rv, op); | |
1047 | REAL_VALUE_TO_TARGET_SINGLE (rv, l); | |
1048 | return num_insns_constant_wide ((HOST_WIDE_INT)l); | |
1049 | } | |
1050 | ||
47ad8c61 | 1051 | else if (GET_CODE (op) == CONST_DOUBLE) |
4e74d8ec | 1052 | { |
47ad8c61 MM |
1053 | HOST_WIDE_INT low; |
1054 | HOST_WIDE_INT high; | |
1055 | long l[2]; | |
1056 | REAL_VALUE_TYPE rv; | |
1057 | int endian = (WORDS_BIG_ENDIAN == 0); | |
4e74d8ec | 1058 | |
47ad8c61 MM |
1059 | if (mode == VOIDmode || mode == DImode) |
1060 | { | |
1061 | high = CONST_DOUBLE_HIGH (op); | |
1062 | low = CONST_DOUBLE_LOW (op); | |
1063 | } | |
1064 | else | |
1065 | { | |
1066 | REAL_VALUE_FROM_CONST_DOUBLE (rv, op); | |
1067 | REAL_VALUE_TO_TARGET_DOUBLE (rv, l); | |
1068 | high = l[endian]; | |
1069 | low = l[1 - endian]; | |
1070 | } | |
4e74d8ec | 1071 | |
47ad8c61 MM |
1072 | if (TARGET_32BIT) |
1073 | return (num_insns_constant_wide (low) | |
1074 | + num_insns_constant_wide (high)); | |
4e74d8ec MM |
1075 | |
1076 | else | |
47ad8c61 | 1077 | { |
0858c623 | 1078 | if (high == 0 && (low & 0x80000000) == 0) |
47ad8c61 MM |
1079 | return num_insns_constant_wide (low); |
1080 | ||
0858c623 | 1081 | else if (high == -1 && (low & 0x80000000) != 0) |
47ad8c61 MM |
1082 | return num_insns_constant_wide (low); |
1083 | ||
a260abc9 DE |
1084 | else if (mask64_operand (op, mode)) |
1085 | return 2; | |
1086 | ||
47ad8c61 MM |
1087 | else if (low == 0) |
1088 | return num_insns_constant_wide (high) + 1; | |
1089 | ||
1090 | else | |
1091 | return (num_insns_constant_wide (high) | |
1092 | + num_insns_constant_wide (low) + 1); | |
1093 | } | |
4e74d8ec MM |
1094 | } |
1095 | ||
1096 | else | |
1097 | abort (); | |
1098 | } | |
1099 | ||
a4f6c312 SS |
1100 | /* Return 1 if the operand is a CONST_DOUBLE and it can be put into a |
1101 | register with one instruction per word. We only do this if we can | |
1102 | safely read CONST_DOUBLE_{LOW,HIGH}. */ | |
9878760c RK |
1103 | |
1104 | int | |
1105 | easy_fp_constant (op, mode) | |
592696dd SS |
1106 | rtx op; |
1107 | enum machine_mode mode; | |
9878760c | 1108 | { |
9878760c RK |
1109 | if (GET_CODE (op) != CONST_DOUBLE |
1110 | || GET_MODE (op) != mode | |
4e74d8ec | 1111 | || (GET_MODE_CLASS (mode) != MODE_FLOAT && mode != DImode)) |
9878760c RK |
1112 | return 0; |
1113 | ||
a4f6c312 | 1114 | /* Consider all constants with -msoft-float to be easy. */ |
4e74d8ec | 1115 | if (TARGET_SOFT_FLOAT && mode != DImode) |
b6c9286a MM |
1116 | return 1; |
1117 | ||
a4f6c312 | 1118 | /* If we are using V.4 style PIC, consider all constants to be hard. */ |
f607bc57 | 1119 | if (flag_pic && DEFAULT_ABI == ABI_V4) |
a7273471 MM |
1120 | return 0; |
1121 | ||
5ae4759c | 1122 | #ifdef TARGET_RELOCATABLE |
a4f6c312 SS |
1123 | /* Similarly if we are using -mrelocatable, consider all constants |
1124 | to be hard. */ | |
5ae4759c MM |
1125 | if (TARGET_RELOCATABLE) |
1126 | return 0; | |
1127 | #endif | |
1128 | ||
042259f2 DE |
1129 | if (mode == DFmode) |
1130 | { | |
1131 | long k[2]; | |
1132 | REAL_VALUE_TYPE rv; | |
1133 | ||
1134 | REAL_VALUE_FROM_CONST_DOUBLE (rv, op); | |
1135 | REAL_VALUE_TO_TARGET_DOUBLE (rv, k); | |
9878760c | 1136 | |
4e74d8ec MM |
1137 | return (num_insns_constant_wide ((HOST_WIDE_INT)k[0]) == 1 |
1138 | && num_insns_constant_wide ((HOST_WIDE_INT)k[1]) == 1); | |
042259f2 | 1139 | } |
4e74d8ec MM |
1140 | |
1141 | else if (mode == SFmode) | |
042259f2 DE |
1142 | { |
1143 | long l; | |
1144 | REAL_VALUE_TYPE rv; | |
1145 | ||
1146 | REAL_VALUE_FROM_CONST_DOUBLE (rv, op); | |
1147 | REAL_VALUE_TO_TARGET_SINGLE (rv, l); | |
9878760c | 1148 | |
4e74d8ec | 1149 | return num_insns_constant_wide (l) == 1; |
042259f2 | 1150 | } |
4e74d8ec | 1151 | |
a260abc9 | 1152 | else if (mode == DImode) |
c81fc13e | 1153 | return ((TARGET_POWERPC64 |
a260abc9 DE |
1154 | && GET_CODE (op) == CONST_DOUBLE && CONST_DOUBLE_LOW (op) == 0) |
1155 | || (num_insns_constant (op, DImode) <= 2)); | |
4e74d8ec | 1156 | |
a9098fd0 GK |
1157 | else if (mode == SImode) |
1158 | return 1; | |
4e74d8ec MM |
1159 | else |
1160 | abort (); | |
9878760c | 1161 | } |
8f75773e | 1162 | |
50a0b056 GK |
1163 | /* Return 1 if the operand is 0.0. */ |
1164 | int | |
1165 | zero_fp_constant (op, mode) | |
592696dd SS |
1166 | rtx op; |
1167 | enum machine_mode mode; | |
50a0b056 GK |
1168 | { |
1169 | return GET_MODE_CLASS (mode) == MODE_FLOAT && op == CONST0_RTX (mode); | |
1170 | } | |
1171 | ||
a4f6c312 SS |
1172 | /* Return 1 if the operand is in volatile memory. Note that during |
1173 | the RTL generation phase, memory_operand does not return TRUE for | |
b6c9286a MM |
1174 | volatile memory references. So this function allows us to |
1175 | recognize volatile references where its safe. */ | |
1176 | ||
1177 | int | |
1178 | volatile_mem_operand (op, mode) | |
592696dd | 1179 | rtx op; |
b6c9286a MM |
1180 | enum machine_mode mode; |
1181 | { | |
1182 | if (GET_CODE (op) != MEM) | |
1183 | return 0; | |
1184 | ||
1185 | if (!MEM_VOLATILE_P (op)) | |
1186 | return 0; | |
1187 | ||
1188 | if (mode != GET_MODE (op)) | |
1189 | return 0; | |
1190 | ||
1191 | if (reload_completed) | |
1192 | return memory_operand (op, mode); | |
1193 | ||
1194 | if (reload_in_progress) | |
1195 | return strict_memory_address_p (mode, XEXP (op, 0)); | |
1196 | ||
1197 | return memory_address_p (mode, XEXP (op, 0)); | |
1198 | } | |
1199 | ||
97f6e72f | 1200 | /* Return 1 if the operand is an offsettable memory operand. */ |
914c2e77 RK |
1201 | |
1202 | int | |
97f6e72f | 1203 | offsettable_mem_operand (op, mode) |
592696dd | 1204 | rtx op; |
914c2e77 RK |
1205 | enum machine_mode mode; |
1206 | { | |
97f6e72f | 1207 | return ((GET_CODE (op) == MEM) |
677a9668 | 1208 | && offsettable_address_p (reload_completed || reload_in_progress, |
97f6e72f | 1209 | mode, XEXP (op, 0))); |
914c2e77 RK |
1210 | } |
1211 | ||
9878760c RK |
1212 | /* Return 1 if the operand is either an easy FP constant (see above) or |
1213 | memory. */ | |
1214 | ||
1215 | int | |
1216 | mem_or_easy_const_operand (op, mode) | |
592696dd | 1217 | rtx op; |
9878760c RK |
1218 | enum machine_mode mode; |
1219 | { | |
1220 | return memory_operand (op, mode) || easy_fp_constant (op, mode); | |
1221 | } | |
1222 | ||
1223 | /* Return 1 if the operand is either a non-special register or an item | |
5f59ecb7 | 1224 | that can be used as the operand of a `mode' add insn. */ |
9878760c RK |
1225 | |
1226 | int | |
1227 | add_operand (op, mode) | |
592696dd | 1228 | rtx op; |
9878760c RK |
1229 | enum machine_mode mode; |
1230 | { | |
2bfcf297 DB |
1231 | if (GET_CODE (op) == CONST_INT) |
1232 | return (CONST_OK_FOR_LETTER_P (INTVAL(op), 'I') | |
1233 | || CONST_OK_FOR_LETTER_P (INTVAL(op), 'L')); | |
1234 | ||
1235 | return gpc_reg_operand (op, mode); | |
9878760c RK |
1236 | } |
1237 | ||
dcfedcd0 RK |
1238 | /* Return 1 if OP is a constant but not a valid add_operand. */ |
1239 | ||
1240 | int | |
1241 | non_add_cint_operand (op, mode) | |
592696dd | 1242 | rtx op; |
296b8152 | 1243 | enum machine_mode mode ATTRIBUTE_UNUSED; |
dcfedcd0 RK |
1244 | { |
1245 | return (GET_CODE (op) == CONST_INT | |
a7653a2c | 1246 | && (unsigned HOST_WIDE_INT) (INTVAL (op) + 0x8000) >= 0x10000 |
38886f37 | 1247 | && ! CONST_OK_FOR_LETTER_P (INTVAL (op), 'L')); |
dcfedcd0 RK |
1248 | } |
1249 | ||
9878760c RK |
1250 | /* Return 1 if the operand is a non-special register or a constant that |
1251 | can be used as the operand of an OR or XOR insn on the RS/6000. */ | |
1252 | ||
1253 | int | |
1254 | logical_operand (op, mode) | |
592696dd | 1255 | rtx op; |
9878760c RK |
1256 | enum machine_mode mode; |
1257 | { | |
40501e5f | 1258 | HOST_WIDE_INT opl, oph; |
1d328b19 | 1259 | |
dfbdccdb GK |
1260 | if (gpc_reg_operand (op, mode)) |
1261 | return 1; | |
1d328b19 | 1262 | |
dfbdccdb | 1263 | if (GET_CODE (op) == CONST_INT) |
40501e5f AM |
1264 | { |
1265 | opl = INTVAL (op) & GET_MODE_MASK (mode); | |
1266 | ||
1267 | #if HOST_BITS_PER_WIDE_INT <= 32 | |
1268 | if (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT && opl < 0) | |
1269 | return 0; | |
1270 | #endif | |
1271 | } | |
dfbdccdb GK |
1272 | else if (GET_CODE (op) == CONST_DOUBLE) |
1273 | { | |
1d328b19 | 1274 | if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT) |
40501e5f | 1275 | abort (); |
1d328b19 GK |
1276 | |
1277 | opl = CONST_DOUBLE_LOW (op); | |
1278 | oph = CONST_DOUBLE_HIGH (op); | |
40501e5f | 1279 | if (oph != 0) |
38886f37 | 1280 | return 0; |
dfbdccdb GK |
1281 | } |
1282 | else | |
1283 | return 0; | |
1d328b19 | 1284 | |
40501e5f AM |
1285 | return ((opl & ~ (unsigned HOST_WIDE_INT) 0xffff) == 0 |
1286 | || (opl & ~ (unsigned HOST_WIDE_INT) 0xffff0000) == 0); | |
9878760c RK |
1287 | } |
1288 | ||
dcfedcd0 | 1289 | /* Return 1 if C is a constant that is not a logical operand (as |
1d328b19 | 1290 | above), but could be split into one. */ |
dcfedcd0 RK |
1291 | |
1292 | int | |
1293 | non_logical_cint_operand (op, mode) | |
592696dd | 1294 | rtx op; |
5f59ecb7 | 1295 | enum machine_mode mode; |
dcfedcd0 | 1296 | { |
dfbdccdb | 1297 | return ((GET_CODE (op) == CONST_INT || GET_CODE (op) == CONST_DOUBLE) |
1d328b19 GK |
1298 | && ! logical_operand (op, mode) |
1299 | && reg_or_logical_cint_operand (op, mode)); | |
dcfedcd0 RK |
1300 | } |
1301 | ||
19ba8161 | 1302 | /* Return 1 if C is a constant that can be encoded in a 32-bit mask on the |
9878760c RK |
1303 | RS/6000. It is if there are no more than two 1->0 or 0->1 transitions. |
1304 | Reject all ones and all zeros, since these should have been optimized | |
1305 | away and confuse the making of MB and ME. */ | |
1306 | ||
1307 | int | |
19ba8161 | 1308 | mask_operand (op, mode) |
592696dd | 1309 | rtx op; |
19ba8161 | 1310 | enum machine_mode mode ATTRIBUTE_UNUSED; |
9878760c | 1311 | { |
02071907 | 1312 | HOST_WIDE_INT c, lsb; |
9878760c | 1313 | |
19ba8161 DE |
1314 | if (GET_CODE (op) != CONST_INT) |
1315 | return 0; | |
1316 | ||
1317 | c = INTVAL (op); | |
1318 | ||
c5059423 AM |
1319 | /* We don't change the number of transitions by inverting, |
1320 | so make sure we start with the LS bit zero. */ | |
1321 | if (c & 1) | |
1322 | c = ~c; | |
1323 | ||
1324 | /* Reject all zeros or all ones. */ | |
1325 | if (c == 0) | |
9878760c RK |
1326 | return 0; |
1327 | ||
c5059423 AM |
1328 | /* Find the first transition. */ |
1329 | lsb = c & -c; | |
1330 | ||
1331 | /* Invert to look for a second transition. */ | |
1332 | c = ~c; | |
9878760c | 1333 | |
c5059423 AM |
1334 | /* Erase first transition. */ |
1335 | c &= -lsb; | |
9878760c | 1336 | |
c5059423 AM |
1337 | /* Find the second transition (if any). */ |
1338 | lsb = c & -c; | |
1339 | ||
1340 | /* Match if all the bits above are 1's (or c is zero). */ | |
1341 | return c == -lsb; | |
9878760c RK |
1342 | } |
1343 | ||
a260abc9 DE |
1344 | /* Return 1 if the operand is a constant that is a PowerPC64 mask. |
1345 | It is if there are no more than one 1->0 or 0->1 transitions. | |
1346 | Reject all ones and all zeros, since these should have been optimized | |
1347 | away and confuse the making of MB and ME. */ | |
9878760c RK |
1348 | |
1349 | int | |
a260abc9 | 1350 | mask64_operand (op, mode) |
592696dd | 1351 | rtx op; |
a260abc9 DE |
1352 | enum machine_mode mode; |
1353 | { | |
1354 | if (GET_CODE (op) == CONST_INT) | |
1355 | { | |
02071907 | 1356 | HOST_WIDE_INT c, lsb; |
a260abc9 | 1357 | |
c5059423 AM |
1358 | /* We don't change the number of transitions by inverting, |
1359 | so make sure we start with the LS bit zero. */ | |
1360 | c = INTVAL (op); | |
1361 | if (c & 1) | |
1362 | c = ~c; | |
a260abc9 | 1363 | |
c5059423 AM |
1364 | /* Reject all zeros or all ones. */ |
1365 | if (c == 0) | |
e2c953b6 DE |
1366 | return 0; |
1367 | ||
c5059423 AM |
1368 | /* Find the transition, and check that all bits above are 1's. */ |
1369 | lsb = c & -c; | |
1370 | return c == -lsb; | |
e2c953b6 | 1371 | } |
a260abc9 DE |
1372 | else if (GET_CODE (op) == CONST_DOUBLE |
1373 | && (mode == VOIDmode || mode == DImode)) | |
1374 | { | |
02071907 | 1375 | HOST_WIDE_INT low, high, lsb; |
a260abc9 | 1376 | |
c5059423 AM |
1377 | if (HOST_BITS_PER_WIDE_INT < 64) |
1378 | high = CONST_DOUBLE_HIGH (op); | |
a260abc9 | 1379 | |
c5059423 AM |
1380 | low = CONST_DOUBLE_LOW (op); |
1381 | if (low & 1) | |
1382 | { | |
1383 | if (HOST_BITS_PER_WIDE_INT < 64) | |
1384 | high = ~high; | |
1385 | low = ~low; | |
1386 | } | |
a260abc9 | 1387 | |
c5059423 AM |
1388 | if (low == 0) |
1389 | { | |
1390 | if (HOST_BITS_PER_WIDE_INT >= 64 || high == 0) | |
1391 | return 0; | |
a260abc9 | 1392 | |
c5059423 AM |
1393 | lsb = high & -high; |
1394 | return high == -lsb; | |
1395 | } | |
a260abc9 | 1396 | |
c5059423 AM |
1397 | lsb = low & -low; |
1398 | return low == -lsb && (HOST_BITS_PER_WIDE_INT >= 64 || high == ~0); | |
a260abc9 DE |
1399 | } |
1400 | else | |
1401 | return 0; | |
1402 | } | |
1403 | ||
1404 | /* Return 1 if the operand is either a non-special register or a constant | |
1405 | that can be used as the operand of a PowerPC64 logical AND insn. */ | |
1406 | ||
1407 | int | |
1408 | and64_operand (op, mode) | |
592696dd | 1409 | rtx op; |
9878760c RK |
1410 | enum machine_mode mode; |
1411 | { | |
a4f6c312 | 1412 | if (fixed_regs[CR0_REGNO]) /* CR0 not available, don't do andi./andis. */ |
52d3af72 DE |
1413 | return (gpc_reg_operand (op, mode) || mask64_operand (op, mode)); |
1414 | ||
1415 | return (logical_operand (op, mode) || mask64_operand (op, mode)); | |
9878760c RK |
1416 | } |
1417 | ||
a260abc9 DE |
1418 | /* Return 1 if the operand is either a non-special register or a |
1419 | constant that can be used as the operand of an RS/6000 logical AND insn. */ | |
dcfedcd0 RK |
1420 | |
1421 | int | |
a260abc9 | 1422 | and_operand (op, mode) |
592696dd | 1423 | rtx op; |
a260abc9 | 1424 | enum machine_mode mode; |
dcfedcd0 | 1425 | { |
a4f6c312 | 1426 | if (fixed_regs[CR0_REGNO]) /* CR0 not available, don't do andi./andis. */ |
52d3af72 DE |
1427 | return (gpc_reg_operand (op, mode) || mask_operand (op, mode)); |
1428 | ||
1429 | return (logical_operand (op, mode) || mask_operand (op, mode)); | |
dcfedcd0 RK |
1430 | } |
1431 | ||
9878760c RK |
1432 | /* Return 1 if the operand is a general register or memory operand. */ |
1433 | ||
1434 | int | |
1435 | reg_or_mem_operand (op, mode) | |
592696dd SS |
1436 | rtx op; |
1437 | enum machine_mode mode; | |
9878760c | 1438 | { |
b6c9286a MM |
1439 | return (gpc_reg_operand (op, mode) |
1440 | || memory_operand (op, mode) | |
1441 | || volatile_mem_operand (op, mode)); | |
9878760c RK |
1442 | } |
1443 | ||
a7a813f7 | 1444 | /* Return 1 if the operand is a general register or memory operand without |
3cb999d8 | 1445 | pre_inc or pre_dec which produces invalid form of PowerPC lwa |
a7a813f7 RK |
1446 | instruction. */ |
1447 | ||
1448 | int | |
1449 | lwa_operand (op, mode) | |
592696dd SS |
1450 | rtx op; |
1451 | enum machine_mode mode; | |
a7a813f7 RK |
1452 | { |
1453 | rtx inner = op; | |
1454 | ||
1455 | if (reload_completed && GET_CODE (inner) == SUBREG) | |
1456 | inner = SUBREG_REG (inner); | |
1457 | ||
1458 | return gpc_reg_operand (inner, mode) | |
1459 | || (memory_operand (inner, mode) | |
1460 | && GET_CODE (XEXP (inner, 0)) != PRE_INC | |
6a40a9d6 DE |
1461 | && GET_CODE (XEXP (inner, 0)) != PRE_DEC |
1462 | && (GET_CODE (XEXP (inner, 0)) != PLUS | |
e903c96a DE |
1463 | || GET_CODE (XEXP (XEXP (inner, 0), 1)) != CONST_INT |
1464 | || INTVAL (XEXP (XEXP (inner, 0), 1)) % 4 == 0)); | |
a7a813f7 RK |
1465 | } |
1466 | ||
9878760c RK |
1467 | /* Return 1 if the operand, used inside a MEM, is a valid first argument |
1468 | to CALL. This is a SYMBOL_REF or a pseudo-register, which will be | |
1469 | forced to lr. */ | |
1470 | ||
1471 | int | |
1472 | call_operand (op, mode) | |
592696dd | 1473 | rtx op; |
9878760c RK |
1474 | enum machine_mode mode; |
1475 | { | |
1476 | if (mode != VOIDmode && GET_MODE (op) != mode) | |
1477 | return 0; | |
1478 | ||
1479 | return (GET_CODE (op) == SYMBOL_REF | |
1480 | || (GET_CODE (op) == REG && REGNO (op) >= FIRST_PSEUDO_REGISTER)); | |
1481 | } | |
1482 | ||
2af3d377 | 1483 | /* Return 1 if the operand is a SYMBOL_REF for a function known to be in |
a4f6c312 | 1484 | this file and the function is not weakly defined. */ |
2af3d377 RK |
1485 | |
1486 | int | |
1487 | current_file_function_operand (op, mode) | |
592696dd | 1488 | rtx op; |
296b8152 | 1489 | enum machine_mode mode ATTRIBUTE_UNUSED; |
2af3d377 RK |
1490 | { |
1491 | return (GET_CODE (op) == SYMBOL_REF | |
1492 | && (SYMBOL_REF_FLAG (op) | |
8f1b829e | 1493 | || (op == XEXP (DECL_RTL (current_function_decl), 0) |
c81fc13e | 1494 | && ! DECL_WEAK (current_function_decl)))); |
2af3d377 RK |
1495 | } |
1496 | ||
9878760c RK |
1497 | /* Return 1 if this operand is a valid input for a move insn. */ |
1498 | ||
1499 | int | |
1500 | input_operand (op, mode) | |
592696dd | 1501 | rtx op; |
9878760c RK |
1502 | enum machine_mode mode; |
1503 | { | |
eb4e8003 | 1504 | /* Memory is always valid. */ |
9878760c RK |
1505 | if (memory_operand (op, mode)) |
1506 | return 1; | |
1507 | ||
34792e82 | 1508 | /* Only a tiny bit of handling for CONSTANT_P_RTX is necessary. */ |
01b4cf2b | 1509 | if (GET_CODE (op) == CONSTANT_P_RTX) |
34792e82 JL |
1510 | return 1; |
1511 | ||
eb4e8003 RK |
1512 | /* For floating-point, easy constants are valid. */ |
1513 | if (GET_MODE_CLASS (mode) == MODE_FLOAT | |
1514 | && CONSTANT_P (op) | |
1515 | && easy_fp_constant (op, mode)) | |
1516 | return 1; | |
1517 | ||
4e74d8ec MM |
1518 | /* Allow any integer constant. */ |
1519 | if (GET_MODE_CLASS (mode) == MODE_INT | |
e675f625 | 1520 | && (GET_CODE (op) == CONST_INT |
e675f625 | 1521 | || GET_CODE (op) == CONST_DOUBLE)) |
4e74d8ec MM |
1522 | return 1; |
1523 | ||
eb4e8003 RK |
1524 | /* For floating-point or multi-word mode, the only remaining valid type |
1525 | is a register. */ | |
9878760c RK |
1526 | if (GET_MODE_CLASS (mode) == MODE_FLOAT |
1527 | || GET_MODE_SIZE (mode) > UNITS_PER_WORD) | |
eb4e8003 | 1528 | return register_operand (op, mode); |
9878760c | 1529 | |
88fe15a1 RK |
1530 | /* The only cases left are integral modes one word or smaller (we |
1531 | do not get called for MODE_CC values). These can be in any | |
1532 | register. */ | |
1533 | if (register_operand (op, mode)) | |
a8b3aeda | 1534 | return 1; |
88fe15a1 | 1535 | |
84cf9dda | 1536 | /* A SYMBOL_REF referring to the TOC is valid. */ |
7fec4abd | 1537 | if (LEGITIMATE_CONSTANT_POOL_ADDRESS_P (op)) |
84cf9dda RK |
1538 | return 1; |
1539 | ||
9ebbca7d GK |
1540 | /* A constant pool expression (relative to the TOC) is valid */ |
1541 | if (TOC_RELATIVE_EXPR_P (op)) | |
b6c9286a MM |
1542 | return 1; |
1543 | ||
88228c4b MM |
1544 | /* V.4 allows SYMBOL_REFs and CONSTs that are in the small data region |
1545 | to be valid. */ | |
f607bc57 | 1546 | if (DEFAULT_ABI == ABI_V4 |
88228c4b MM |
1547 | && (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST) |
1548 | && small_data_operand (op, Pmode)) | |
1549 | return 1; | |
1550 | ||
042259f2 | 1551 | return 0; |
9878760c | 1552 | } |
7509c759 | 1553 | |
a4f6c312 | 1554 | /* Return 1 for an operand in small memory on V.4/eabi. */ |
7509c759 MM |
1555 | |
1556 | int | |
1557 | small_data_operand (op, mode) | |
296b8152 KG |
1558 | rtx op ATTRIBUTE_UNUSED; |
1559 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
7509c759 | 1560 | { |
38c1f2d7 | 1561 | #if TARGET_ELF |
5f59ecb7 | 1562 | rtx sym_ref; |
7509c759 | 1563 | |
d9407988 | 1564 | if (rs6000_sdata == SDATA_NONE || rs6000_sdata == SDATA_DATA) |
a54d04b7 | 1565 | return 0; |
a54d04b7 | 1566 | |
f607bc57 | 1567 | if (DEFAULT_ABI != ABI_V4) |
7509c759 MM |
1568 | return 0; |
1569 | ||
88228c4b MM |
1570 | if (GET_CODE (op) == SYMBOL_REF) |
1571 | sym_ref = op; | |
1572 | ||
1573 | else if (GET_CODE (op) != CONST | |
1574 | || GET_CODE (XEXP (op, 0)) != PLUS | |
1575 | || GET_CODE (XEXP (XEXP (op, 0), 0)) != SYMBOL_REF | |
1576 | || GET_CODE (XEXP (XEXP (op, 0), 1)) != CONST_INT) | |
7509c759 MM |
1577 | return 0; |
1578 | ||
88228c4b | 1579 | else |
dbf55e53 MM |
1580 | { |
1581 | rtx sum = XEXP (op, 0); | |
1582 | HOST_WIDE_INT summand; | |
1583 | ||
1584 | /* We have to be careful here, because it is the referenced address | |
1585 | that must be 32k from _SDA_BASE_, not just the symbol. */ | |
1586 | summand = INTVAL (XEXP (sum, 1)); | |
1587 | if (summand < 0 || summand > g_switch_value) | |
1588 | return 0; | |
1589 | ||
1590 | sym_ref = XEXP (sum, 0); | |
1591 | } | |
88228c4b MM |
1592 | |
1593 | if (*XSTR (sym_ref, 0) != '@') | |
7509c759 MM |
1594 | return 0; |
1595 | ||
1596 | return 1; | |
d9407988 MM |
1597 | |
1598 | #else | |
1599 | return 0; | |
1600 | #endif | |
7509c759 | 1601 | } |
9ebbca7d GK |
1602 | \f |
1603 | static int | |
1604 | constant_pool_expr_1 (op, have_sym, have_toc) | |
1605 | rtx op; | |
1606 | int *have_sym; | |
1607 | int *have_toc; | |
1608 | { | |
1609 | switch (GET_CODE(op)) | |
1610 | { | |
1611 | case SYMBOL_REF: | |
a4f6c312 SS |
1612 | if (CONSTANT_POOL_ADDRESS_P (op)) |
1613 | { | |
1614 | if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (op), Pmode)) | |
1615 | { | |
1616 | *have_sym = 1; | |
1617 | return 1; | |
1618 | } | |
1619 | else | |
1620 | return 0; | |
1621 | } | |
1622 | else if (! strcmp (XSTR (op, 0), toc_label_name)) | |
1623 | { | |
1624 | *have_toc = 1; | |
1625 | return 1; | |
1626 | } | |
1627 | else | |
1628 | return 0; | |
9ebbca7d GK |
1629 | case PLUS: |
1630 | case MINUS: | |
a4f6c312 SS |
1631 | return constant_pool_expr_1 (XEXP (op, 0), have_sym, have_toc) && |
1632 | constant_pool_expr_1 (XEXP (op, 1), have_sym, have_toc); | |
9ebbca7d | 1633 | case CONST: |
a4f6c312 | 1634 | return constant_pool_expr_1 (XEXP (op, 0), have_sym, have_toc); |
9ebbca7d | 1635 | case CONST_INT: |
a4f6c312 | 1636 | return 1; |
9ebbca7d | 1637 | default: |
a4f6c312 | 1638 | return 0; |
9ebbca7d GK |
1639 | } |
1640 | } | |
1641 | ||
1642 | int | |
1643 | constant_pool_expr_p (op) | |
1644 | rtx op; | |
1645 | { | |
1646 | int have_sym = 0; | |
1647 | int have_toc = 0; | |
1648 | return constant_pool_expr_1 (op, &have_sym, &have_toc) && have_sym; | |
1649 | } | |
1650 | ||
1651 | int | |
1652 | toc_relative_expr_p (op) | |
1653 | rtx op; | |
1654 | { | |
1655 | int have_sym = 0; | |
1656 | int have_toc = 0; | |
1657 | return constant_pool_expr_1 (op, &have_sym, &have_toc) && have_toc; | |
1658 | } | |
1659 | ||
1660 | /* Try machine-dependent ways of modifying an illegitimate address | |
1661 | to be legitimate. If we find one, return the new, valid address. | |
1662 | This is used from only one place: `memory_address' in explow.c. | |
1663 | ||
a4f6c312 SS |
1664 | OLDX is the address as it was before break_out_memory_refs was |
1665 | called. In some cases it is useful to look at this to decide what | |
1666 | needs to be done. | |
9ebbca7d | 1667 | |
a4f6c312 | 1668 | MODE is passed so that this function can use GO_IF_LEGITIMATE_ADDRESS. |
9ebbca7d | 1669 | |
a4f6c312 SS |
1670 | It is always safe for this function to do nothing. It exists to |
1671 | recognize opportunities to optimize the output. | |
9ebbca7d GK |
1672 | |
1673 | On RS/6000, first check for the sum of a register with a constant | |
1674 | integer that is out of range. If so, generate code to add the | |
1675 | constant with the low-order 16 bits masked to the register and force | |
1676 | this result into another register (this can be done with `cau'). | |
1677 | Then generate an address of REG+(CONST&0xffff), allowing for the | |
1678 | possibility of bit 16 being a one. | |
1679 | ||
1680 | Then check for the sum of a register and something not constant, try to | |
1681 | load the other things into a register and return the sum. */ | |
1682 | rtx | |
1683 | rs6000_legitimize_address (x, oldx, mode) | |
1684 | rtx x; | |
1685 | rtx oldx ATTRIBUTE_UNUSED; | |
1686 | enum machine_mode mode; | |
0ac081f6 | 1687 | { |
9ebbca7d GK |
1688 | if (GET_CODE (x) == PLUS |
1689 | && GET_CODE (XEXP (x, 0)) == REG | |
1690 | && GET_CODE (XEXP (x, 1)) == CONST_INT | |
1691 | && (unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 1)) + 0x8000) >= 0x10000) | |
1692 | { | |
1693 | HOST_WIDE_INT high_int, low_int; | |
1694 | rtx sum; | |
1695 | high_int = INTVAL (XEXP (x, 1)) & (~ (HOST_WIDE_INT) 0xffff); | |
1696 | low_int = INTVAL (XEXP (x, 1)) & 0xffff; | |
1697 | if (low_int & 0x8000) | |
1698 | high_int += 0x10000, low_int |= ((HOST_WIDE_INT) -1) << 16; | |
1699 | sum = force_operand (gen_rtx_PLUS (Pmode, XEXP (x, 0), | |
1700 | GEN_INT (high_int)), 0); | |
1701 | return gen_rtx_PLUS (Pmode, sum, GEN_INT (low_int)); | |
1702 | } | |
1703 | else if (GET_CODE (x) == PLUS | |
1704 | && GET_CODE (XEXP (x, 0)) == REG | |
1705 | && GET_CODE (XEXP (x, 1)) != CONST_INT | |
6ac7bf2c | 1706 | && GET_MODE_NUNITS (mode) == 1 |
9ebbca7d GK |
1707 | && (TARGET_HARD_FLOAT || TARGET_POWERPC64 || mode != DFmode) |
1708 | && (TARGET_POWERPC64 || mode != DImode) | |
1709 | && mode != TImode) | |
1710 | { | |
1711 | return gen_rtx_PLUS (Pmode, XEXP (x, 0), | |
1712 | force_reg (Pmode, force_operand (XEXP (x, 1), 0))); | |
1713 | } | |
0ac081f6 AH |
1714 | else if (ALTIVEC_VECTOR_MODE (mode)) |
1715 | { | |
1716 | rtx reg; | |
1717 | ||
1718 | /* Make sure both operands are registers. */ | |
1719 | if (GET_CODE (x) == PLUS) | |
9f85ed45 | 1720 | return gen_rtx_PLUS (Pmode, force_reg (Pmode, XEXP (x, 0)), |
0ac081f6 AH |
1721 | force_reg (Pmode, XEXP (x, 1))); |
1722 | ||
1723 | reg = force_reg (Pmode, x); | |
1724 | return reg; | |
1725 | } | |
9ebbca7d GK |
1726 | else if (TARGET_ELF && TARGET_32BIT && TARGET_NO_TOC && ! flag_pic |
1727 | && GET_CODE (x) != CONST_INT | |
1728 | && GET_CODE (x) != CONST_DOUBLE | |
1729 | && CONSTANT_P (x) | |
6ac7bf2c GK |
1730 | && GET_MODE_NUNITS (mode) == 1 |
1731 | && (GET_MODE_BITSIZE (mode) <= 32 | |
c3bb62b9 | 1732 | || (TARGET_HARD_FLOAT && mode == DFmode))) |
9ebbca7d GK |
1733 | { |
1734 | rtx reg = gen_reg_rtx (Pmode); | |
1735 | emit_insn (gen_elf_high (reg, (x))); | |
1736 | return gen_rtx_LO_SUM (Pmode, reg, (x)); | |
1737 | } | |
ee890fe2 SS |
1738 | else if (TARGET_MACHO && TARGET_32BIT && TARGET_NO_TOC |
1739 | && ! flag_pic | |
1740 | && GET_CODE (x) != CONST_INT | |
1741 | && GET_CODE (x) != CONST_DOUBLE | |
1742 | && CONSTANT_P (x) | |
1743 | && (TARGET_HARD_FLOAT || mode != DFmode) | |
1744 | && mode != DImode | |
1745 | && mode != TImode) | |
1746 | { | |
1747 | rtx reg = gen_reg_rtx (Pmode); | |
1748 | emit_insn (gen_macho_high (reg, (x))); | |
1749 | return gen_rtx_LO_SUM (Pmode, reg, (x)); | |
1750 | } | |
9ebbca7d GK |
1751 | else if (TARGET_TOC |
1752 | && CONSTANT_POOL_EXPR_P (x) | |
a9098fd0 | 1753 | && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x), Pmode)) |
9ebbca7d GK |
1754 | { |
1755 | return create_TOC_reference (x); | |
1756 | } | |
1757 | else | |
1758 | return NULL_RTX; | |
1759 | } | |
258bfae2 | 1760 | |
24ea750e DJ |
1761 | /* The convention appears to be to define this wherever it is used. |
1762 | With legitimize_reload_address now defined here, REG_MODE_OK_FOR_BASE_P | |
1763 | is now used here. */ | |
1764 | #ifndef REG_MODE_OK_FOR_BASE_P | |
1765 | #define REG_MODE_OK_FOR_BASE_P(REGNO, MODE) REG_OK_FOR_BASE_P (REGNO) | |
1766 | #endif | |
1767 | ||
1768 | /* Our implementation of LEGITIMIZE_RELOAD_ADDRESS. Returns a value to | |
1769 | replace the input X, or the original X if no replacement is called for. | |
1770 | The output parameter *WIN is 1 if the calling macro should goto WIN, | |
1771 | 0 if it should not. | |
1772 | ||
1773 | For RS/6000, we wish to handle large displacements off a base | |
1774 | register by splitting the addend across an addiu/addis and the mem insn. | |
1775 | This cuts number of extra insns needed from 3 to 1. | |
1776 | ||
1777 | On Darwin, we use this to generate code for floating point constants. | |
1778 | A movsf_low is generated so we wind up with 2 instructions rather than 3. | |
1779 | The Darwin code is inside #if TARGET_MACHO because only then is | |
1780 | machopic_function_base_name() defined. */ | |
1781 | rtx | |
1782 | rs6000_legitimize_reload_address (x, mode, opnum, type, ind_levels, win) | |
1783 | rtx x; | |
1784 | enum machine_mode mode; | |
1785 | int opnum; | |
1786 | int type; | |
1787 | int ind_levels ATTRIBUTE_UNUSED; | |
1788 | int *win; | |
1789 | { | |
1790 | /* We must recognize output that we have already generated ourselves. */ | |
1791 | if (GET_CODE (x) == PLUS | |
1792 | && GET_CODE (XEXP (x, 0)) == PLUS | |
1793 | && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG | |
1794 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT | |
1795 | && GET_CODE (XEXP (x, 1)) == CONST_INT) | |
1796 | { | |
1797 | push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL, | |
1798 | BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0, | |
1799 | opnum, (enum reload_type)type); | |
1800 | *win = 1; | |
1801 | return x; | |
1802 | } | |
1803 | #if TARGET_MACHO | |
1804 | if (DEFAULT_ABI == ABI_DARWIN && flag_pic | |
1805 | && GET_CODE (x) == LO_SUM | |
1806 | && GET_CODE (XEXP (x, 0)) == PLUS | |
1807 | && XEXP (XEXP (x, 0), 0) == pic_offset_table_rtx | |
1808 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == HIGH | |
1809 | && GET_CODE (XEXP (XEXP (XEXP (x, 0), 1), 0)) == CONST | |
1810 | && XEXP (XEXP (XEXP (x, 0), 1), 0) == XEXP (x, 1) | |
1811 | && GET_CODE (XEXP (XEXP (x, 1), 0)) == MINUS | |
1812 | && GET_CODE (XEXP (XEXP (XEXP (x, 1), 0), 0)) == SYMBOL_REF | |
1813 | && GET_CODE (XEXP (XEXP (XEXP (x, 1), 0), 1)) == SYMBOL_REF) | |
1814 | { | |
1815 | /* Result of previous invocation of this function on Darwin | |
6f317ef3 | 1816 | floating point constant. */ |
24ea750e DJ |
1817 | push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL, |
1818 | BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, | |
1819 | opnum, (enum reload_type)type); | |
1820 | *win = 1; | |
1821 | return x; | |
1822 | } | |
1823 | #endif | |
1824 | if (GET_CODE (x) == PLUS | |
1825 | && GET_CODE (XEXP (x, 0)) == REG | |
1826 | && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER | |
1827 | && REG_MODE_OK_FOR_BASE_P (XEXP (x, 0), mode) | |
1828 | && GET_CODE (XEXP (x, 1)) == CONST_INT) | |
1829 | { | |
1830 | HOST_WIDE_INT val = INTVAL (XEXP (x, 1)); | |
1831 | HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000; | |
1832 | HOST_WIDE_INT high | |
1833 | = (((val - low) & 0xffffffff) ^ 0x80000000) - 0x80000000; | |
1834 | ||
1835 | /* Check for 32-bit overflow. */ | |
1836 | if (high + low != val) | |
1837 | { | |
1838 | *win = 0; | |
1839 | return x; | |
1840 | } | |
1841 | ||
1842 | /* Reload the high part into a base reg; leave the low part | |
1843 | in the mem directly. */ | |
1844 | ||
1845 | x = gen_rtx_PLUS (GET_MODE (x), | |
1846 | gen_rtx_PLUS (GET_MODE (x), XEXP (x, 0), | |
1847 | GEN_INT (high)), | |
1848 | GEN_INT (low)); | |
1849 | ||
1850 | push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL, | |
1851 | BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0, | |
1852 | opnum, (enum reload_type)type); | |
1853 | *win = 1; | |
1854 | return x; | |
1855 | } | |
1856 | #if TARGET_MACHO | |
1857 | if (GET_CODE (x) == SYMBOL_REF | |
1858 | && DEFAULT_ABI == ABI_DARWIN | |
1859 | && flag_pic) | |
1860 | { | |
1861 | /* Darwin load of floating point constant. */ | |
1862 | rtx offset = gen_rtx (CONST, Pmode, | |
1863 | gen_rtx (MINUS, Pmode, x, | |
1864 | gen_rtx (SYMBOL_REF, Pmode, | |
1865 | machopic_function_base_name ()))); | |
1866 | x = gen_rtx (LO_SUM, GET_MODE (x), | |
1867 | gen_rtx (PLUS, Pmode, pic_offset_table_rtx, | |
1868 | gen_rtx (HIGH, Pmode, offset)), offset); | |
1869 | push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL, | |
1870 | BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, | |
1871 | opnum, (enum reload_type)type); | |
1872 | *win = 1; | |
1873 | return x; | |
1874 | } | |
1875 | #endif | |
1876 | if (TARGET_TOC | |
1877 | && CONSTANT_POOL_EXPR_P (x) | |
1878 | && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x), mode)) | |
1879 | { | |
1880 | (x) = create_TOC_reference (x); | |
1881 | *win = 1; | |
1882 | return x; | |
1883 | } | |
1884 | *win = 0; | |
1885 | return x; | |
1886 | } | |
1887 | ||
258bfae2 FS |
1888 | /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression |
1889 | that is a valid memory address for an instruction. | |
1890 | The MODE argument is the machine mode for the MEM expression | |
1891 | that wants to use this address. | |
1892 | ||
1893 | On the RS/6000, there are four valid address: a SYMBOL_REF that | |
1894 | refers to a constant pool entry of an address (or the sum of it | |
1895 | plus a constant), a short (16-bit signed) constant plus a register, | |
1896 | the sum of two registers, or a register indirect, possibly with an | |
1897 | auto-increment. For DFmode and DImode with an constant plus register, | |
1898 | we must ensure that both words are addressable or PowerPC64 with offset | |
1899 | word aligned. | |
1900 | ||
1901 | For modes spanning multiple registers (DFmode in 32-bit GPRs, | |
1902 | 32-bit DImode, TImode), indexed addressing cannot be used because | |
1903 | adjacent memory cells are accessed by adding word-sized offsets | |
1904 | during assembly output. */ | |
1905 | int | |
1906 | rs6000_legitimate_address (mode, x, reg_ok_strict) | |
1907 | enum machine_mode mode; | |
1908 | rtx x; | |
1909 | int reg_ok_strict; | |
1910 | { | |
1911 | if (LEGITIMATE_INDIRECT_ADDRESS_P (x, reg_ok_strict)) | |
1912 | return 1; | |
1913 | if ((GET_CODE (x) == PRE_INC || GET_CODE (x) == PRE_DEC) | |
1914 | && TARGET_UPDATE | |
1915 | && LEGITIMATE_INDIRECT_ADDRESS_P (XEXP (x, 0), reg_ok_strict)) | |
1916 | return 1; | |
1917 | if (LEGITIMATE_SMALL_DATA_P (mode, x)) | |
1918 | return 1; | |
1919 | if (LEGITIMATE_CONSTANT_POOL_ADDRESS_P (x)) | |
1920 | return 1; | |
1921 | /* If not REG_OK_STRICT (before reload) let pass any stack offset. */ | |
1922 | if (! reg_ok_strict | |
1923 | && GET_CODE (x) == PLUS | |
1924 | && GET_CODE (XEXP (x, 0)) == REG | |
1925 | && XEXP (x, 0) == virtual_stack_vars_rtx | |
1926 | && GET_CODE (XEXP (x, 1)) == CONST_INT) | |
1927 | return 1; | |
1928 | if (LEGITIMATE_OFFSET_ADDRESS_P (mode, x, reg_ok_strict)) | |
1929 | return 1; | |
1930 | if (mode != TImode | |
1931 | && (TARGET_HARD_FLOAT || TARGET_POWERPC64 || mode != DFmode) | |
1932 | && (TARGET_POWERPC64 || mode != DImode) | |
1933 | && LEGITIMATE_INDEXED_ADDRESS_P (x, reg_ok_strict)) | |
1934 | return 1; | |
1935 | if (LEGITIMATE_LO_SUM_ADDRESS_P (mode, x, reg_ok_strict)) | |
1936 | return 1; | |
1937 | return 0; | |
1938 | } | |
fb4d4348 | 1939 | \f |
a4f6c312 SS |
1940 | /* Try to output insns to set TARGET equal to the constant C if it can |
1941 | be done in less than N insns. Do all computations in MODE. | |
1942 | Returns the place where the output has been placed if it can be | |
1943 | done and the insns have been emitted. If it would take more than N | |
1944 | insns, zero is returned and no insns and emitted. */ | |
2bfcf297 DB |
1945 | |
1946 | rtx | |
1947 | rs6000_emit_set_const (dest, mode, source, n) | |
1948 | rtx dest, source; | |
1949 | enum machine_mode mode; | |
1950 | int n ATTRIBUTE_UNUSED; | |
1951 | { | |
1952 | HOST_WIDE_INT c0, c1; | |
1953 | ||
1954 | if (mode == QImode || mode == HImode || mode == SImode) | |
1955 | { | |
1956 | if (dest == NULL) | |
1957 | dest = gen_reg_rtx (mode); | |
1958 | emit_insn (gen_rtx_SET (VOIDmode, dest, source)); | |
1959 | return dest; | |
1960 | } | |
1961 | ||
1962 | if (GET_CODE (source) == CONST_INT) | |
1963 | { | |
1964 | c0 = INTVAL (source); | |
1965 | c1 = -(c0 < 0); | |
1966 | } | |
1967 | else if (GET_CODE (source) == CONST_DOUBLE) | |
1968 | { | |
1969 | #if HOST_BITS_PER_WIDE_INT >= 64 | |
1970 | c0 = CONST_DOUBLE_LOW (source); | |
1971 | c1 = -(c0 < 0); | |
1972 | #else | |
1973 | c0 = CONST_DOUBLE_LOW (source); | |
1974 | c1 = CONST_DOUBLE_HIGH (source); | |
1975 | #endif | |
1976 | } | |
1977 | else | |
a4f6c312 | 1978 | abort (); |
2bfcf297 DB |
1979 | |
1980 | return rs6000_emit_set_long_const (dest, c0, c1); | |
1981 | } | |
1982 | ||
1983 | /* Having failed to find a 3 insn sequence in rs6000_emit_set_const, | |
1984 | fall back to a straight forward decomposition. We do this to avoid | |
1985 | exponential run times encountered when looking for longer sequences | |
1986 | with rs6000_emit_set_const. */ | |
1987 | static rtx | |
1988 | rs6000_emit_set_long_const (dest, c1, c2) | |
1989 | rtx dest; | |
1990 | HOST_WIDE_INT c1, c2; | |
1991 | { | |
1992 | if (!TARGET_POWERPC64) | |
1993 | { | |
1994 | rtx operand1, operand2; | |
1995 | ||
1996 | operand1 = operand_subword_force (dest, WORDS_BIG_ENDIAN == 0, | |
1997 | DImode); | |
1998 | operand2 = operand_subword_force (dest, WORDS_BIG_ENDIAN != 0, | |
1999 | DImode); | |
2000 | emit_move_insn (operand1, GEN_INT (c1)); | |
2001 | emit_move_insn (operand2, GEN_INT (c2)); | |
2002 | } | |
2003 | else | |
2004 | { | |
252b88f7 TR |
2005 | HOST_WIDE_INT d1, d2, d2_s, d3, d4; |
2006 | ||
2007 | /* This function is called by rs6000_emit_allocate_stack after reload | |
2008 | with a dest of r0. r0 is an invalid register for addsi. Use an addi | |
2009 | and a shift instead. */ | |
2010 | int regnum = REGNO (dest); | |
2bfcf297 DB |
2011 | |
2012 | /* Decompose the entire word */ | |
2013 | #if HOST_BITS_PER_WIDE_INT >= 64 | |
2014 | if (c2 != -(c1 < 0)) | |
2015 | abort (); | |
2016 | d1 = ((c1 & 0xffff) ^ 0x8000) - 0x8000; | |
2017 | c1 -= d1; | |
2018 | d2 = ((c1 & 0xffffffff) ^ 0x80000000) - 0x80000000; | |
252b88f7 | 2019 | d2_s = d2 >> 16; |
2bfcf297 DB |
2020 | c1 = (c1 - d2) >> 32; |
2021 | d3 = ((c1 & 0xffff) ^ 0x8000) - 0x8000; | |
2022 | c1 -= d3; | |
2023 | d4 = ((c1 & 0xffffffff) ^ 0x80000000) - 0x80000000; | |
2024 | if (c1 != d4) | |
2025 | abort (); | |
2026 | #else | |
2027 | d1 = ((c1 & 0xffff) ^ 0x8000) - 0x8000; | |
2028 | c1 -= d1; | |
2029 | d2 = ((c1 & 0xffffffff) ^ 0x80000000) - 0x80000000; | |
252b88f7 | 2030 | d2_s = d2 >> 16; |
2bfcf297 DB |
2031 | if (c1 != d2) |
2032 | abort (); | |
2033 | c2 += (d2 < 0); | |
2034 | d3 = ((c2 & 0xffff) ^ 0x8000) - 0x8000; | |
2035 | c2 -= d3; | |
2036 | d4 = ((c2 & 0xffffffff) ^ 0x80000000) - 0x80000000; | |
2037 | if (c2 != d4) | |
2038 | abort (); | |
2039 | #endif | |
2040 | ||
2041 | /* Construct the high word */ | |
40501e5f | 2042 | if (d4 != 0) |
2bfcf297 DB |
2043 | { |
2044 | emit_move_insn (dest, GEN_INT (d4)); | |
40501e5f | 2045 | if (d3 != 0) |
2bfcf297 DB |
2046 | emit_move_insn (dest, |
2047 | gen_rtx_PLUS (DImode, dest, GEN_INT (d3))); | |
2048 | } | |
252b88f7 | 2049 | else if (d3 != 0) |
2bfcf297 DB |
2050 | emit_move_insn (dest, GEN_INT (d3)); |
2051 | ||
2052 | /* Shift it into place */ | |
40501e5f | 2053 | if (d3 != 0 || d4 != 0) |
252b88f7 TR |
2054 | if (regnum == 0 && d2 != 0) |
2055 | emit_move_insn (dest, gen_rtx_ASHIFT (DImode, dest, GEN_INT (16))); | |
2056 | else | |
2057 | emit_move_insn (dest, gen_rtx_ASHIFT (DImode, dest, GEN_INT (32))); | |
2bfcf297 DB |
2058 | |
2059 | /* Add in the low bits. */ | |
40501e5f | 2060 | if (d2 != 0) |
252b88f7 TR |
2061 | { |
2062 | if (d3 != 0 || d4 != 0) | |
2063 | { | |
2064 | if (regnum == 0) | |
2065 | { | |
2066 | emit_move_insn (dest, gen_rtx_PLUS (DImode, dest, | |
2067 | GEN_INT (d2_s))); | |
2068 | emit_move_insn (dest, gen_rtx_ASHIFT (DImode, dest, | |
2069 | GEN_INT (16))); | |
2070 | } | |
2071 | else | |
2072 | emit_move_insn (dest, gen_rtx_PLUS (DImode, dest, | |
2073 | GEN_INT (d2))); | |
2074 | } | |
2075 | else | |
2076 | emit_move_insn (dest, GEN_INT (d2)); | |
2077 | } | |
40501e5f | 2078 | if (d1 != 0) |
252b88f7 TR |
2079 | if (d2 != 0 || d3 != 0 || d4 != 0) |
2080 | emit_move_insn (dest, gen_rtx_PLUS (DImode, dest, GEN_INT (d1))); | |
2081 | else | |
2082 | emit_move_insn (dest, GEN_INT (d1)); | |
2bfcf297 DB |
2083 | } |
2084 | ||
2085 | return dest; | |
2086 | } | |
2087 | ||
fb4d4348 GK |
2088 | /* Emit a move from SOURCE to DEST in mode MODE. */ |
2089 | void | |
2090 | rs6000_emit_move (dest, source, mode) | |
2091 | rtx dest; | |
2092 | rtx source; | |
2093 | enum machine_mode mode; | |
2094 | { | |
2095 | rtx operands[2]; | |
2096 | operands[0] = dest; | |
2097 | operands[1] = source; | |
2098 | ||
2099 | /* Sanity checks. Check that we get CONST_DOUBLE only when we should. */ | |
2100 | if (GET_CODE (operands[1]) == CONST_DOUBLE | |
2101 | && ! FLOAT_MODE_P (mode) | |
2102 | && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT) | |
2103 | { | |
2104 | /* FIXME. This should never happen. */ | |
2105 | /* Since it seems that it does, do the safe thing and convert | |
2106 | to a CONST_INT. */ | |
2107 | operands[1] = | |
2108 | GEN_INT (trunc_int_for_mode (CONST_DOUBLE_LOW (operands[1]), mode)); | |
2109 | } | |
2110 | if (GET_CODE (operands[1]) == CONST_DOUBLE | |
2111 | && ! FLOAT_MODE_P (mode) | |
2112 | && ((CONST_DOUBLE_HIGH (operands[1]) == 0 | |
2113 | && CONST_DOUBLE_LOW (operands[1]) >= 0) | |
2114 | || (CONST_DOUBLE_HIGH (operands[1]) == -1 | |
2115 | && CONST_DOUBLE_LOW (operands[1]) < 0))) | |
2116 | abort (); | |
c9e8cb32 DD |
2117 | |
2118 | /* Check if GCC is setting up a block move that will end up using FP | |
2119 | registers as temporaries. We must make sure this is acceptable. */ | |
2120 | if (GET_CODE (operands[0]) == MEM | |
2121 | && GET_CODE (operands[1]) == MEM | |
2122 | && mode == DImode | |
41543739 GK |
2123 | && (SLOW_UNALIGNED_ACCESS (DImode, MEM_ALIGN (operands[0])) |
2124 | || SLOW_UNALIGNED_ACCESS (DImode, MEM_ALIGN (operands[1]))) | |
2125 | && ! (SLOW_UNALIGNED_ACCESS (SImode, (MEM_ALIGN (operands[0]) > 32 | |
2126 | ? 32 : MEM_ALIGN (operands[0]))) | |
2127 | || SLOW_UNALIGNED_ACCESS (SImode, (MEM_ALIGN (operands[1]) > 32 | |
2128 | ? 32 | |
2129 | : MEM_ALIGN (operands[1])))) | |
2130 | && ! MEM_VOLATILE_P (operands [0]) | |
2131 | && ! MEM_VOLATILE_P (operands [1])) | |
c9e8cb32 | 2132 | { |
41543739 GK |
2133 | emit_move_insn (adjust_address (operands[0], SImode, 0), |
2134 | adjust_address (operands[1], SImode, 0)); | |
2135 | emit_move_insn (adjust_address (operands[0], SImode, 4), | |
2136 | adjust_address (operands[1], SImode, 4)); | |
c9e8cb32 DD |
2137 | return; |
2138 | } | |
fb4d4348 GK |
2139 | |
2140 | if (! no_new_pseudos && GET_CODE (operands[0]) != REG) | |
2141 | operands[1] = force_reg (mode, operands[1]); | |
a9098fd0 | 2142 | |
ffc14f31 GK |
2143 | if (mode == SFmode && ! TARGET_POWERPC && TARGET_HARD_FLOAT |
2144 | && GET_CODE (operands[0]) == MEM) | |
fb4d4348 | 2145 | { |
ffc14f31 GK |
2146 | int regnum; |
2147 | ||
2148 | if (reload_in_progress || reload_completed) | |
2149 | regnum = true_regnum (operands[1]); | |
2150 | else if (GET_CODE (operands[1]) == REG) | |
2151 | regnum = REGNO (operands[1]); | |
2152 | else | |
2153 | regnum = -1; | |
fb4d4348 GK |
2154 | |
2155 | /* If operands[1] is a register, on POWER it may have | |
2156 | double-precision data in it, so truncate it to single | |
2157 | precision. */ | |
2158 | if (FP_REGNO_P (regnum) || regnum >= FIRST_PSEUDO_REGISTER) | |
2159 | { | |
2160 | rtx newreg; | |
2161 | newreg = (no_new_pseudos ? operands[1] : gen_reg_rtx (mode)); | |
2162 | emit_insn (gen_aux_truncdfsf2 (newreg, operands[1])); | |
2163 | operands[1] = newreg; | |
2164 | } | |
2165 | } | |
2166 | ||
a9098fd0 GK |
2167 | /* Handle the case where reload calls us with an invalid address; |
2168 | and the case of CONSTANT_P_RTX. */ | |
2169 | if (! general_operand (operands[1], mode) | |
2170 | || ! nonimmediate_operand (operands[0], mode) | |
2171 | || GET_CODE (operands[1]) == CONSTANT_P_RTX) | |
fb4d4348 GK |
2172 | { |
2173 | emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1])); | |
2174 | return; | |
2175 | } | |
a9098fd0 | 2176 | |
fb4d4348 GK |
2177 | /* FIXME: In the long term, this switch statement should go away |
2178 | and be replaced by a sequence of tests based on things like | |
2179 | mode == Pmode. */ | |
2180 | switch (mode) | |
2181 | { | |
2182 | case HImode: | |
2183 | case QImode: | |
2184 | if (CONSTANT_P (operands[1]) | |
2185 | && GET_CODE (operands[1]) != CONST_INT) | |
a9098fd0 | 2186 | operands[1] = force_const_mem (mode, operands[1]); |
fb4d4348 GK |
2187 | break; |
2188 | ||
06f4e019 | 2189 | case TFmode: |
fb4d4348 GK |
2190 | case DFmode: |
2191 | case SFmode: | |
2192 | if (CONSTANT_P (operands[1]) | |
2193 | && ! easy_fp_constant (operands[1], mode)) | |
a9098fd0 | 2194 | operands[1] = force_const_mem (mode, operands[1]); |
fb4d4348 GK |
2195 | break; |
2196 | ||
0ac081f6 AH |
2197 | case V16QImode: |
2198 | case V8HImode: | |
2199 | case V4SFmode: | |
2200 | case V4SImode: | |
2201 | /* fixme: aldyh -- allow vector constants when they are implemented. */ | |
2202 | if (CONSTANT_P (operands[1])) | |
2203 | operands[1] = force_const_mem (mode, operands[1]); | |
2204 | break; | |
2205 | ||
fb4d4348 | 2206 | case SImode: |
a9098fd0 | 2207 | case DImode: |
fb4d4348 GK |
2208 | /* Use default pattern for address of ELF small data */ |
2209 | if (TARGET_ELF | |
a9098fd0 | 2210 | && mode == Pmode |
f607bc57 | 2211 | && DEFAULT_ABI == ABI_V4 |
a9098fd0 GK |
2212 | && (GET_CODE (operands[1]) == SYMBOL_REF |
2213 | || GET_CODE (operands[1]) == CONST) | |
2214 | && small_data_operand (operands[1], mode)) | |
fb4d4348 GK |
2215 | { |
2216 | emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1])); | |
2217 | return; | |
2218 | } | |
2219 | ||
f607bc57 | 2220 | if (DEFAULT_ABI == ABI_V4 |
a9098fd0 GK |
2221 | && mode == Pmode && mode == SImode |
2222 | && flag_pic == 1 && got_operand (operands[1], mode)) | |
fb4d4348 GK |
2223 | { |
2224 | emit_insn (gen_movsi_got (operands[0], operands[1])); | |
2225 | return; | |
2226 | } | |
2227 | ||
ee890fe2 SS |
2228 | if ((TARGET_ELF || DEFAULT_ABI == ABI_DARWIN) |
2229 | && TARGET_NO_TOC && ! flag_pic | |
a9098fd0 | 2230 | && mode == Pmode |
fb4d4348 GK |
2231 | && CONSTANT_P (operands[1]) |
2232 | && GET_CODE (operands[1]) != HIGH | |
2233 | && GET_CODE (operands[1]) != CONST_INT) | |
2234 | { | |
a9098fd0 | 2235 | rtx target = (no_new_pseudos ? operands[0] : gen_reg_rtx (mode)); |
fb4d4348 GK |
2236 | |
2237 | /* If this is a function address on -mcall-aixdesc, | |
2238 | convert it to the address of the descriptor. */ | |
2239 | if (DEFAULT_ABI == ABI_AIX | |
2240 | && GET_CODE (operands[1]) == SYMBOL_REF | |
2241 | && XSTR (operands[1], 0)[0] == '.') | |
2242 | { | |
2243 | const char *name = XSTR (operands[1], 0); | |
2244 | rtx new_ref; | |
2245 | while (*name == '.') | |
2246 | name++; | |
2247 | new_ref = gen_rtx_SYMBOL_REF (Pmode, name); | |
2248 | CONSTANT_POOL_ADDRESS_P (new_ref) | |
2249 | = CONSTANT_POOL_ADDRESS_P (operands[1]); | |
2250 | SYMBOL_REF_FLAG (new_ref) = SYMBOL_REF_FLAG (operands[1]); | |
2251 | SYMBOL_REF_USED (new_ref) = SYMBOL_REF_USED (operands[1]); | |
2252 | operands[1] = new_ref; | |
2253 | } | |
7509c759 | 2254 | |
ee890fe2 SS |
2255 | if (DEFAULT_ABI == ABI_DARWIN) |
2256 | { | |
2257 | emit_insn (gen_macho_high (target, operands[1])); | |
2258 | emit_insn (gen_macho_low (operands[0], target, operands[1])); | |
2259 | return; | |
2260 | } | |
2261 | ||
fb4d4348 GK |
2262 | emit_insn (gen_elf_high (target, operands[1])); |
2263 | emit_insn (gen_elf_low (operands[0], target, operands[1])); | |
2264 | return; | |
2265 | } | |
2266 | ||
a9098fd0 GK |
2267 | /* If this is a SYMBOL_REF that refers to a constant pool entry, |
2268 | and we have put it in the TOC, we just need to make a TOC-relative | |
2269 | reference to it. */ | |
2270 | if (TARGET_TOC | |
2271 | && GET_CODE (operands[1]) == SYMBOL_REF | |
2272 | && CONSTANT_POOL_EXPR_P (operands[1]) | |
2273 | && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (operands[1]), | |
2274 | get_pool_mode (operands[1]))) | |
fb4d4348 | 2275 | { |
a9098fd0 | 2276 | operands[1] = create_TOC_reference (operands[1]); |
fb4d4348 | 2277 | } |
a9098fd0 GK |
2278 | else if (mode == Pmode |
2279 | && CONSTANT_P (operands[1]) | |
38886f37 AO |
2280 | && ((GET_CODE (operands[1]) != CONST_INT |
2281 | && ! easy_fp_constant (operands[1], mode)) | |
2282 | || (GET_CODE (operands[1]) == CONST_INT | |
2283 | && num_insns_constant (operands[1], mode) > 2) | |
2284 | || (GET_CODE (operands[0]) == REG | |
2285 | && FP_REGNO_P (REGNO (operands[0])))) | |
a9098fd0 GK |
2286 | && GET_CODE (operands[1]) != HIGH |
2287 | && ! LEGITIMATE_CONSTANT_POOL_ADDRESS_P (operands[1]) | |
2288 | && ! TOC_RELATIVE_EXPR_P (operands[1])) | |
fb4d4348 GK |
2289 | { |
2290 | /* Emit a USE operation so that the constant isn't deleted if | |
2291 | expensive optimizations are turned on because nobody | |
2292 | references it. This should only be done for operands that | |
2293 | contain SYMBOL_REFs with CONSTANT_POOL_ADDRESS_P set. | |
2294 | This should not be done for operands that contain LABEL_REFs. | |
2295 | For now, we just handle the obvious case. */ | |
2296 | if (GET_CODE (operands[1]) != LABEL_REF) | |
2297 | emit_insn (gen_rtx_USE (VOIDmode, operands[1])); | |
2298 | ||
c859cda6 | 2299 | #if TARGET_MACHO |
ee890fe2 SS |
2300 | /* Darwin uses a special PIC legitimizer. */ |
2301 | if (DEFAULT_ABI == ABI_DARWIN && flag_pic) | |
2302 | { | |
ee890fe2 SS |
2303 | operands[1] = |
2304 | rs6000_machopic_legitimize_pic_address (operands[1], mode, | |
c859cda6 DJ |
2305 | operands[0]); |
2306 | if (operands[0] != operands[1]) | |
2307 | emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1])); | |
ee890fe2 SS |
2308 | return; |
2309 | } | |
c859cda6 | 2310 | #endif |
ee890fe2 | 2311 | |
fb4d4348 GK |
2312 | /* If we are to limit the number of things we put in the TOC and |
2313 | this is a symbol plus a constant we can add in one insn, | |
2314 | just put the symbol in the TOC and add the constant. Don't do | |
2315 | this if reload is in progress. */ | |
2316 | if (GET_CODE (operands[1]) == CONST | |
2317 | && TARGET_NO_SUM_IN_TOC && ! reload_in_progress | |
2318 | && GET_CODE (XEXP (operands[1], 0)) == PLUS | |
a9098fd0 | 2319 | && add_operand (XEXP (XEXP (operands[1], 0), 1), mode) |
fb4d4348 GK |
2320 | && (GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == LABEL_REF |
2321 | || GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == SYMBOL_REF) | |
2322 | && ! side_effects_p (operands[0])) | |
2323 | { | |
a4f6c312 SS |
2324 | rtx sym = |
2325 | force_const_mem (mode, XEXP (XEXP (operands[1], 0), 0)); | |
fb4d4348 GK |
2326 | rtx other = XEXP (XEXP (operands[1], 0), 1); |
2327 | ||
a9098fd0 GK |
2328 | sym = force_reg (mode, sym); |
2329 | if (mode == SImode) | |
2330 | emit_insn (gen_addsi3 (operands[0], sym, other)); | |
2331 | else | |
2332 | emit_insn (gen_adddi3 (operands[0], sym, other)); | |
fb4d4348 GK |
2333 | return; |
2334 | } | |
2335 | ||
a9098fd0 | 2336 | operands[1] = force_const_mem (mode, operands[1]); |
fb4d4348 GK |
2337 | |
2338 | if (TARGET_TOC | |
d34c5b80 DE |
2339 | && CONSTANT_POOL_EXPR_P (XEXP (operands[1], 0)) |
2340 | && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P ( | |
2341 | get_pool_constant (XEXP (operands[1], 0)), | |
2342 | get_pool_mode (XEXP (operands[1], 0)))) | |
a9098fd0 | 2343 | { |
ba4828e0 RK |
2344 | operands[1] |
2345 | = gen_rtx_MEM (mode, | |
2346 | create_TOC_reference (XEXP (operands[1], 0))); | |
2347 | set_mem_alias_set (operands[1], get_TOC_alias_set ()); | |
fb4d4348 | 2348 | RTX_UNCHANGING_P (operands[1]) = 1; |
a9098fd0 | 2349 | } |
fb4d4348 GK |
2350 | } |
2351 | break; | |
a9098fd0 | 2352 | |
fb4d4348 GK |
2353 | case TImode: |
2354 | if (GET_CODE (operands[0]) == MEM | |
2355 | && GET_CODE (XEXP (operands[0], 0)) != REG | |
2356 | && ! reload_in_progress) | |
792760b9 RK |
2357 | operands[0] |
2358 | = replace_equiv_address (operands[0], | |
2359 | copy_addr_to_reg (XEXP (operands[0], 0))); | |
fb4d4348 GK |
2360 | |
2361 | if (GET_CODE (operands[1]) == MEM | |
2362 | && GET_CODE (XEXP (operands[1], 0)) != REG | |
2363 | && ! reload_in_progress) | |
792760b9 RK |
2364 | operands[1] |
2365 | = replace_equiv_address (operands[1], | |
2366 | copy_addr_to_reg (XEXP (operands[1], 0))); | |
fb4d4348 GK |
2367 | break; |
2368 | ||
2369 | default: | |
2370 | abort (); | |
2371 | } | |
2372 | ||
a9098fd0 GK |
2373 | /* Above, we may have called force_const_mem which may have returned |
2374 | an invalid address. If we can, fix this up; otherwise, reload will | |
2375 | have to deal with it. */ | |
2376 | if (GET_CODE (operands[1]) == MEM | |
2377 | && ! memory_address_p (mode, XEXP (operands[1], 0)) | |
2378 | && ! reload_in_progress) | |
f4ef873c | 2379 | operands[1] = adjust_address (operands[1], mode, 0); |
a9098fd0 | 2380 | |
fb4d4348 | 2381 | emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1])); |
02a4ec28 | 2382 | return; |
fb4d4348 | 2383 | } |
4697a36c MM |
2384 | \f |
2385 | /* Initialize a variable CUM of type CUMULATIVE_ARGS | |
2386 | for a call to a function whose data type is FNTYPE. | |
2387 | For a library call, FNTYPE is 0. | |
2388 | ||
2389 | For incoming args we set the number of arguments in the prototype large | |
1c20ae99 | 2390 | so we never return a PARALLEL. */ |
4697a36c MM |
2391 | |
2392 | void | |
2393 | init_cumulative_args (cum, fntype, libname, incoming) | |
2394 | CUMULATIVE_ARGS *cum; | |
2395 | tree fntype; | |
296b8152 | 2396 | rtx libname ATTRIBUTE_UNUSED; |
4697a36c MM |
2397 | int incoming; |
2398 | { | |
2399 | static CUMULATIVE_ARGS zero_cumulative; | |
2400 | ||
2401 | *cum = zero_cumulative; | |
2402 | cum->words = 0; | |
2403 | cum->fregno = FP_ARG_MIN_REG; | |
0ac081f6 | 2404 | cum->vregno = ALTIVEC_ARG_MIN_REG; |
4697a36c | 2405 | cum->prototype = (fntype && TYPE_ARG_TYPES (fntype)); |
7509c759 | 2406 | cum->call_cookie = CALL_NORMAL; |
4cc833b7 | 2407 | cum->sysv_gregno = GP_ARG_MIN_REG; |
4697a36c MM |
2408 | |
2409 | if (incoming) | |
bd227acc | 2410 | cum->nargs_prototype = 1000; /* don't return a PARALLEL */ |
4697a36c MM |
2411 | |
2412 | else if (cum->prototype) | |
2413 | cum->nargs_prototype = (list_length (TYPE_ARG_TYPES (fntype)) - 1 | |
2414 | + (TYPE_MODE (TREE_TYPE (fntype)) == BLKmode | |
2415 | || RETURN_IN_MEMORY (TREE_TYPE (fntype)))); | |
2416 | ||
2417 | else | |
2418 | cum->nargs_prototype = 0; | |
2419 | ||
2420 | cum->orig_nargs = cum->nargs_prototype; | |
7509c759 | 2421 | |
9ebbca7d GK |
2422 | /* Check for longcall's */ |
2423 | if (fntype && lookup_attribute ("longcall", TYPE_ATTRIBUTES (fntype))) | |
6a4cee5f MM |
2424 | cum->call_cookie = CALL_LONG; |
2425 | ||
4697a36c MM |
2426 | if (TARGET_DEBUG_ARG) |
2427 | { | |
2428 | fprintf (stderr, "\ninit_cumulative_args:"); | |
2429 | if (fntype) | |
2430 | { | |
2431 | tree ret_type = TREE_TYPE (fntype); | |
2432 | fprintf (stderr, " ret code = %s,", | |
2433 | tree_code_name[ (int)TREE_CODE (ret_type) ]); | |
2434 | } | |
2435 | ||
6a4cee5f MM |
2436 | if (cum->call_cookie & CALL_LONG) |
2437 | fprintf (stderr, " longcall,"); | |
2438 | ||
4697a36c MM |
2439 | fprintf (stderr, " proto = %d, nargs = %d\n", |
2440 | cum->prototype, cum->nargs_prototype); | |
2441 | } | |
2442 | } | |
2443 | \f | |
c229cba9 DE |
2444 | /* If defined, a C expression which determines whether, and in which |
2445 | direction, to pad out an argument with extra space. The value | |
2446 | should be of type `enum direction': either `upward' to pad above | |
2447 | the argument, `downward' to pad below, or `none' to inhibit | |
2448 | padding. | |
2449 | ||
2450 | For the AIX ABI structs are always stored left shifted in their | |
2451 | argument slot. */ | |
2452 | ||
9ebbca7d | 2453 | enum direction |
c229cba9 DE |
2454 | function_arg_padding (mode, type) |
2455 | enum machine_mode mode; | |
2456 | tree type; | |
2457 | { | |
c85f7c16 | 2458 | if (type != 0 && AGGREGATE_TYPE_P (type)) |
9ebbca7d | 2459 | return upward; |
c229cba9 DE |
2460 | |
2461 | /* This is the default definition. */ | |
2462 | return (! BYTES_BIG_ENDIAN | |
9ebbca7d | 2463 | ? upward |
c229cba9 DE |
2464 | : ((mode == BLKmode |
2465 | ? (type && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST | |
2466 | && int_size_in_bytes (type) < (PARM_BOUNDARY / BITS_PER_UNIT)) | |
2467 | : GET_MODE_BITSIZE (mode) < PARM_BOUNDARY) | |
9ebbca7d | 2468 | ? downward : upward)); |
c229cba9 DE |
2469 | } |
2470 | ||
b6c9286a MM |
2471 | /* If defined, a C expression that gives the alignment boundary, in bits, |
2472 | of an argument with the specified mode and type. If it is not defined, | |
2473 | PARM_BOUNDARY is used for all arguments. | |
2474 | ||
2310f99a | 2475 | V.4 wants long longs to be double word aligned. */ |
b6c9286a MM |
2476 | |
2477 | int | |
2478 | function_arg_boundary (mode, type) | |
2479 | enum machine_mode mode; | |
9ebbca7d | 2480 | tree type ATTRIBUTE_UNUSED; |
b6c9286a | 2481 | { |
f607bc57 | 2482 | if (DEFAULT_ABI == ABI_V4 && (mode == DImode || mode == DFmode)) |
e1f83b4d | 2483 | return 64; |
0ac081f6 AH |
2484 | else if (TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode)) |
2485 | return 128; | |
9ebbca7d | 2486 | else |
b6c9286a | 2487 | return PARM_BOUNDARY; |
b6c9286a MM |
2488 | } |
2489 | \f | |
4697a36c MM |
2490 | /* Update the data in CUM to advance over an argument |
2491 | of mode MODE and data type TYPE. | |
2492 | (TYPE is null for libcalls where that information may not be available.) */ | |
2493 | ||
2494 | void | |
2495 | function_arg_advance (cum, mode, type, named) | |
2496 | CUMULATIVE_ARGS *cum; | |
2497 | enum machine_mode mode; | |
2498 | tree type; | |
2499 | int named; | |
2500 | { | |
2501 | cum->nargs_prototype--; | |
2502 | ||
0ac081f6 AH |
2503 | if (TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode)) |
2504 | { | |
2505 | if (cum->vregno <= ALTIVEC_ARG_MAX_REG && cum->nargs_prototype >= 0) | |
2506 | cum->vregno++; | |
2507 | else | |
2508 | cum->words += RS6000_ARG_SIZE (mode, type); | |
2509 | } | |
f607bc57 | 2510 | else if (DEFAULT_ABI == ABI_V4) |
4697a36c | 2511 | { |
4cc833b7 RH |
2512 | if (TARGET_HARD_FLOAT |
2513 | && (mode == SFmode || mode == DFmode)) | |
4697a36c | 2514 | { |
4cc833b7 RH |
2515 | if (cum->fregno <= FP_ARG_V4_MAX_REG) |
2516 | cum->fregno++; | |
2517 | else | |
2518 | { | |
2519 | if (mode == DFmode) | |
2520 | cum->words += cum->words & 1; | |
d34c5b80 | 2521 | cum->words += RS6000_ARG_SIZE (mode, type); |
4cc833b7 | 2522 | } |
4697a36c | 2523 | } |
4cc833b7 RH |
2524 | else |
2525 | { | |
2526 | int n_words; | |
2527 | int gregno = cum->sysv_gregno; | |
2528 | ||
2529 | /* Aggregates and IEEE quad get passed by reference. */ | |
2530 | if ((type && AGGREGATE_TYPE_P (type)) | |
2531 | || mode == TFmode) | |
2532 | n_words = 1; | |
2533 | else | |
d34c5b80 | 2534 | n_words = RS6000_ARG_SIZE (mode, type); |
4cc833b7 RH |
2535 | |
2536 | /* Long long is put in odd registers. */ | |
2537 | if (n_words == 2 && (gregno & 1) == 0) | |
2538 | gregno += 1; | |
2539 | ||
2540 | /* Long long is not split between registers and stack. */ | |
2541 | if (gregno + n_words - 1 > GP_ARG_MAX_REG) | |
2542 | { | |
2543 | /* Long long is aligned on the stack. */ | |
2544 | if (n_words == 2) | |
2545 | cum->words += cum->words & 1; | |
2546 | cum->words += n_words; | |
2547 | } | |
4697a36c | 2548 | |
4cc833b7 RH |
2549 | /* Note: continuing to accumulate gregno past when we've started |
2550 | spilling to the stack indicates the fact that we've started | |
2551 | spilling to the stack to expand_builtin_saveregs. */ | |
2552 | cum->sysv_gregno = gregno + n_words; | |
2553 | } | |
4697a36c | 2554 | |
4cc833b7 RH |
2555 | if (TARGET_DEBUG_ARG) |
2556 | { | |
2557 | fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ", | |
2558 | cum->words, cum->fregno); | |
2559 | fprintf (stderr, "gregno = %2d, nargs = %4d, proto = %d, ", | |
2560 | cum->sysv_gregno, cum->nargs_prototype, cum->prototype); | |
2561 | fprintf (stderr, "mode = %4s, named = %d\n", | |
2562 | GET_MODE_NAME (mode), named); | |
2563 | } | |
4697a36c MM |
2564 | } |
2565 | else | |
4cc833b7 RH |
2566 | { |
2567 | int align = (TARGET_32BIT && (cum->words & 1) != 0 | |
2568 | && function_arg_boundary (mode, type) == 64) ? 1 : 0; | |
a4f6c312 | 2569 | |
d34c5b80 | 2570 | cum->words += align + RS6000_ARG_SIZE (mode, type); |
4697a36c | 2571 | |
d34c5b80 DE |
2572 | if (GET_MODE_CLASS (mode) == MODE_FLOAT && TARGET_HARD_FLOAT) |
2573 | cum->fregno++; | |
4cc833b7 RH |
2574 | |
2575 | if (TARGET_DEBUG_ARG) | |
2576 | { | |
2577 | fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ", | |
2578 | cum->words, cum->fregno); | |
2579 | fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s, ", | |
2580 | cum->nargs_prototype, cum->prototype, GET_MODE_NAME (mode)); | |
2581 | fprintf (stderr, "named = %d, align = %d\n", named, align); | |
2582 | } | |
2583 | } | |
4697a36c MM |
2584 | } |
2585 | \f | |
2586 | /* Determine where to put an argument to a function. | |
2587 | Value is zero to push the argument on the stack, | |
2588 | or a hard register in which to store the argument. | |
2589 | ||
2590 | MODE is the argument's machine mode. | |
2591 | TYPE is the data type of the argument (as a tree). | |
2592 | This is null for libcalls where that information may | |
2593 | not be available. | |
2594 | CUM is a variable of type CUMULATIVE_ARGS which gives info about | |
2595 | the preceding args and about the function being called. | |
2596 | NAMED is nonzero if this argument is a named parameter | |
2597 | (otherwise it is an extra parameter matching an ellipsis). | |
2598 | ||
2599 | On RS/6000 the first eight words of non-FP are normally in registers | |
2600 | and the rest are pushed. Under AIX, the first 13 FP args are in registers. | |
2601 | Under V.4, the first 8 FP args are in registers. | |
2602 | ||
2603 | If this is floating-point and no prototype is specified, we use | |
2604 | both an FP and integer register (or possibly FP reg and stack). Library | |
2605 | functions (when TYPE is zero) always have the proper types for args, | |
2606 | so we can pass the FP value just in one register. emit_library_function | |
1c20ae99 | 2607 | doesn't support PARALLEL anyway. */ |
4697a36c MM |
2608 | |
2609 | struct rtx_def * | |
2610 | function_arg (cum, mode, type, named) | |
2611 | CUMULATIVE_ARGS *cum; | |
2612 | enum machine_mode mode; | |
2613 | tree type; | |
20c29ebe | 2614 | int named; |
4697a36c | 2615 | { |
4cc833b7 | 2616 | enum rs6000_abi abi = DEFAULT_ABI; |
4697a36c | 2617 | |
a4f6c312 SS |
2618 | /* Return a marker to indicate whether CR1 needs to set or clear the |
2619 | bit that V.4 uses to say fp args were passed in registers. | |
2620 | Assume that we don't need the marker for software floating point, | |
2621 | or compiler generated library calls. */ | |
4697a36c MM |
2622 | if (mode == VOIDmode) |
2623 | { | |
f607bc57 | 2624 | if (abi == ABI_V4 |
7509c759 MM |
2625 | && TARGET_HARD_FLOAT |
2626 | && cum->nargs_prototype < 0 | |
4697a36c | 2627 | && type && (cum->prototype || TARGET_NO_PROTOTYPE)) |
7509c759 | 2628 | { |
6a4cee5f MM |
2629 | return GEN_INT (cum->call_cookie |
2630 | | ((cum->fregno == FP_ARG_MIN_REG) | |
2631 | ? CALL_V4_SET_FP_ARGS | |
2632 | : CALL_V4_CLEAR_FP_ARGS)); | |
7509c759 | 2633 | } |
4697a36c | 2634 | |
7509c759 | 2635 | return GEN_INT (cum->call_cookie); |
4697a36c MM |
2636 | } |
2637 | ||
0ac081f6 AH |
2638 | if (TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode)) |
2639 | { | |
20c29ebe | 2640 | if (named && cum->vregno <= ALTIVEC_ARG_MAX_REG) |
0ac081f6 AH |
2641 | return gen_rtx_REG (mode, cum->vregno); |
2642 | else | |
2643 | return NULL; | |
2644 | } | |
f607bc57 | 2645 | else if (abi == ABI_V4) |
4697a36c | 2646 | { |
4cc833b7 RH |
2647 | if (TARGET_HARD_FLOAT |
2648 | && (mode == SFmode || mode == DFmode)) | |
2649 | { | |
2650 | if (cum->fregno <= FP_ARG_V4_MAX_REG) | |
2651 | return gen_rtx_REG (mode, cum->fregno); | |
2652 | else | |
2653 | return NULL; | |
2654 | } | |
2655 | else | |
2656 | { | |
2657 | int n_words; | |
2658 | int gregno = cum->sysv_gregno; | |
2659 | ||
2660 | /* Aggregates and IEEE quad get passed by reference. */ | |
2661 | if ((type && AGGREGATE_TYPE_P (type)) | |
2662 | || mode == TFmode) | |
2663 | n_words = 1; | |
2664 | else | |
d34c5b80 | 2665 | n_words = RS6000_ARG_SIZE (mode, type); |
4cc833b7 RH |
2666 | |
2667 | /* Long long is put in odd registers. */ | |
2668 | if (n_words == 2 && (gregno & 1) == 0) | |
2669 | gregno += 1; | |
2670 | ||
2671 | /* Long long is not split between registers and stack. */ | |
2672 | if (gregno + n_words - 1 <= GP_ARG_MAX_REG) | |
2673 | return gen_rtx_REG (mode, gregno); | |
2674 | else | |
2675 | return NULL; | |
2676 | } | |
4697a36c | 2677 | } |
4cc833b7 RH |
2678 | else |
2679 | { | |
2680 | int align = (TARGET_32BIT && (cum->words & 1) != 0 | |
2681 | && function_arg_boundary (mode, type) == 64) ? 1 : 0; | |
2682 | int align_words = cum->words + align; | |
4697a36c | 2683 | |
4cc833b7 RH |
2684 | if (type && TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST) |
2685 | return NULL_RTX; | |
2686 | ||
2687 | if (USE_FP_FOR_ARG_P (*cum, mode, type)) | |
2688 | { | |
2689 | if (! type | |
2690 | || ((cum->nargs_prototype > 0) | |
2691 | /* IBM AIX extended its linkage convention definition always | |
2692 | to require FP args after register save area hole on the | |
2693 | stack. */ | |
2694 | && (DEFAULT_ABI != ABI_AIX | |
2695 | || ! TARGET_XL_CALL | |
2696 | || (align_words < GP_ARG_NUM_REG)))) | |
2697 | return gen_rtx_REG (mode, cum->fregno); | |
2698 | ||
2699 | return gen_rtx_PARALLEL (mode, | |
2700 | gen_rtvec (2, | |
39403d82 | 2701 | gen_rtx_EXPR_LIST (VOIDmode, |
1c20ae99 JW |
2702 | ((align_words >= GP_ARG_NUM_REG) |
2703 | ? NULL_RTX | |
2704 | : (align_words | |
d34c5b80 | 2705 | + RS6000_ARG_SIZE (mode, type) |
1c20ae99 JW |
2706 | > GP_ARG_NUM_REG |
2707 | /* If this is partially on the stack, then | |
2708 | we only include the portion actually | |
2709 | in registers here. */ | |
39403d82 | 2710 | ? gen_rtx_REG (SImode, |
1c20ae99 | 2711 | GP_ARG_MIN_REG + align_words) |
39403d82 | 2712 | : gen_rtx_REG (mode, |
1c20ae99 JW |
2713 | GP_ARG_MIN_REG + align_words))), |
2714 | const0_rtx), | |
39403d82 DE |
2715 | gen_rtx_EXPR_LIST (VOIDmode, |
2716 | gen_rtx_REG (mode, cum->fregno), | |
1c20ae99 | 2717 | const0_rtx))); |
4cc833b7 RH |
2718 | } |
2719 | else if (align_words < GP_ARG_NUM_REG) | |
2720 | return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words); | |
2721 | else | |
2722 | return NULL_RTX; | |
4697a36c | 2723 | } |
4697a36c MM |
2724 | } |
2725 | \f | |
2726 | /* For an arg passed partly in registers and partly in memory, | |
2727 | this is the number of registers used. | |
2728 | For args passed entirely in registers or entirely in memory, zero. */ | |
2729 | ||
2730 | int | |
2731 | function_arg_partial_nregs (cum, mode, type, named) | |
2732 | CUMULATIVE_ARGS *cum; | |
2733 | enum machine_mode mode; | |
2734 | tree type; | |
d34c5b80 | 2735 | int named ATTRIBUTE_UNUSED; |
4697a36c | 2736 | { |
f607bc57 | 2737 | if (DEFAULT_ABI == ABI_V4) |
4697a36c | 2738 | return 0; |
4697a36c | 2739 | |
0ac081f6 AH |
2740 | if (USE_FP_FOR_ARG_P (*cum, mode, type) |
2741 | || USE_ALTIVEC_FOR_ARG_P (*cum, mode, type)) | |
4697a36c MM |
2742 | { |
2743 | if (cum->nargs_prototype >= 0) | |
2744 | return 0; | |
2745 | } | |
2746 | ||
2747 | if (cum->words < GP_ARG_NUM_REG | |
d34c5b80 | 2748 | && GP_ARG_NUM_REG < (cum->words + RS6000_ARG_SIZE (mode, type))) |
4697a36c MM |
2749 | { |
2750 | int ret = GP_ARG_NUM_REG - cum->words; | |
2751 | if (ret && TARGET_DEBUG_ARG) | |
2752 | fprintf (stderr, "function_arg_partial_nregs: %d\n", ret); | |
2753 | ||
2754 | return ret; | |
2755 | } | |
2756 | ||
2757 | return 0; | |
2758 | } | |
2759 | \f | |
2760 | /* A C expression that indicates when an argument must be passed by | |
2761 | reference. If nonzero for an argument, a copy of that argument is | |
2762 | made in memory and a pointer to the argument is passed instead of | |
2763 | the argument itself. The pointer is passed in whatever way is | |
2764 | appropriate for passing a pointer to that type. | |
2765 | ||
2766 | Under V.4, structures and unions are passed by reference. */ | |
2767 | ||
2768 | int | |
2769 | function_arg_pass_by_reference (cum, mode, type, named) | |
296b8152 KG |
2770 | CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED; |
2771 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
4697a36c | 2772 | tree type; |
296b8152 | 2773 | int named ATTRIBUTE_UNUSED; |
4697a36c | 2774 | { |
f607bc57 | 2775 | if (DEFAULT_ABI == ABI_V4 |
4cc833b7 RH |
2776 | && ((type && AGGREGATE_TYPE_P (type)) |
2777 | || mode == TFmode)) | |
4697a36c MM |
2778 | { |
2779 | if (TARGET_DEBUG_ARG) | |
2780 | fprintf (stderr, "function_arg_pass_by_reference: aggregate\n"); | |
2781 | ||
2782 | return 1; | |
2783 | } | |
4697a36c MM |
2784 | |
2785 | return 0; | |
2786 | } | |
4697a36c MM |
2787 | \f |
2788 | /* Perform any needed actions needed for a function that is receiving a | |
2789 | variable number of arguments. | |
2790 | ||
2791 | CUM is as above. | |
2792 | ||
2793 | MODE and TYPE are the mode and type of the current parameter. | |
2794 | ||
2795 | PRETEND_SIZE is a variable that should be set to the amount of stack | |
2796 | that must be pushed by the prolog to pretend that our caller pushed | |
2797 | it. | |
2798 | ||
2799 | Normally, this macro will push all remaining incoming registers on the | |
2800 | stack and set PRETEND_SIZE to the length of the registers pushed. */ | |
2801 | ||
2802 | void | |
2803 | setup_incoming_varargs (cum, mode, type, pretend_size, no_rtl) | |
2804 | CUMULATIVE_ARGS *cum; | |
2805 | enum machine_mode mode; | |
2806 | tree type; | |
2807 | int *pretend_size; | |
2808 | int no_rtl; | |
2809 | ||
2810 | { | |
4cc833b7 RH |
2811 | CUMULATIVE_ARGS next_cum; |
2812 | int reg_size = TARGET_32BIT ? 4 : 8; | |
ca5adc63 | 2813 | rtx save_area = NULL_RTX, mem; |
dfafc897 | 2814 | int first_reg_offset, set; |
d34c5b80 DE |
2815 | tree fntype; |
2816 | int stdarg_p; | |
4697a36c | 2817 | |
d34c5b80 DE |
2818 | fntype = TREE_TYPE (current_function_decl); |
2819 | stdarg_p = (TYPE_ARG_TYPES (fntype) != 0 | |
2820 | && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype))) | |
2821 | != void_type_node)); | |
4cc833b7 | 2822 | |
d34c5b80 DE |
2823 | /* For varargs, we do not want to skip the dummy va_dcl argument. |
2824 | For stdargs, we do want to skip the last named argument. */ | |
2825 | next_cum = *cum; | |
2826 | if (stdarg_p) | |
2827 | function_arg_advance (&next_cum, mode, type, 1); | |
4cc833b7 | 2828 | |
f607bc57 | 2829 | if (DEFAULT_ABI == ABI_V4) |
d34c5b80 | 2830 | { |
4cc833b7 RH |
2831 | /* Indicate to allocate space on the stack for varargs save area. */ |
2832 | /* ??? Does this really have to be located at a magic spot on the | |
2833 | stack, or can we allocate this with assign_stack_local instead. */ | |
00dba523 | 2834 | cfun->machine->sysv_varargs_p = 1; |
60e2d0ca | 2835 | if (! no_rtl) |
2c4974b7 | 2836 | save_area = plus_constant (virtual_stack_vars_rtx, |
bd227acc | 2837 | - RS6000_VARARGS_SIZE); |
4cc833b7 RH |
2838 | |
2839 | first_reg_offset = next_cum.sysv_gregno - GP_ARG_MIN_REG; | |
4697a36c | 2840 | } |
60e2d0ca | 2841 | else |
4697a36c | 2842 | { |
d34c5b80 | 2843 | first_reg_offset = next_cum.words; |
4cc833b7 | 2844 | save_area = virtual_incoming_args_rtx; |
00dba523 | 2845 | cfun->machine->sysv_varargs_p = 0; |
4697a36c MM |
2846 | |
2847 | if (MUST_PASS_IN_STACK (mode, type)) | |
d34c5b80 | 2848 | first_reg_offset += RS6000_ARG_SIZE (TYPE_MODE (type), type); |
4cc833b7 | 2849 | } |
4697a36c | 2850 | |
dfafc897 | 2851 | set = get_varargs_alias_set (); |
c81fc13e | 2852 | if (! no_rtl && first_reg_offset < GP_ARG_NUM_REG) |
4cc833b7 | 2853 | { |
dfafc897 FS |
2854 | mem = gen_rtx_MEM (BLKmode, |
2855 | plus_constant (save_area, | |
2856 | first_reg_offset * reg_size)), | |
ba4828e0 | 2857 | set_mem_alias_set (mem, set); |
8ac61af7 | 2858 | set_mem_align (mem, BITS_PER_WORD); |
dfafc897 | 2859 | |
4cc833b7 | 2860 | move_block_from_reg |
dfafc897 | 2861 | (GP_ARG_MIN_REG + first_reg_offset, mem, |
4cc833b7 RH |
2862 | GP_ARG_NUM_REG - first_reg_offset, |
2863 | (GP_ARG_NUM_REG - first_reg_offset) * UNITS_PER_WORD); | |
2864 | ||
2865 | /* ??? Does ABI_V4 need this at all? */ | |
4697a36c MM |
2866 | *pretend_size = (GP_ARG_NUM_REG - first_reg_offset) * UNITS_PER_WORD; |
2867 | } | |
2868 | ||
4697a36c | 2869 | /* Save FP registers if needed. */ |
f607bc57 | 2870 | if (DEFAULT_ABI == ABI_V4 |
c81fc13e | 2871 | && TARGET_HARD_FLOAT && ! no_rtl |
4cc833b7 | 2872 | && next_cum.fregno <= FP_ARG_V4_MAX_REG) |
4697a36c | 2873 | { |
4cc833b7 | 2874 | int fregno = next_cum.fregno; |
9ebbca7d | 2875 | rtx cr1 = gen_rtx_REG (CCmode, CR1_REGNO); |
4cc833b7 RH |
2876 | rtx lab = gen_label_rtx (); |
2877 | int off = (GP_ARG_NUM_REG * reg_size) + ((fregno - FP_ARG_MIN_REG) * 8); | |
4697a36c | 2878 | |
4cc833b7 | 2879 | emit_jump_insn (gen_rtx_SET (VOIDmode, |
4697a36c | 2880 | pc_rtx, |
39403d82 | 2881 | gen_rtx_IF_THEN_ELSE (VOIDmode, |
4cc833b7 RH |
2882 | gen_rtx_NE (VOIDmode, cr1, |
2883 | const0_rtx), | |
39403d82 | 2884 | gen_rtx_LABEL_REF (VOIDmode, lab), |
4697a36c MM |
2885 | pc_rtx))); |
2886 | ||
4cc833b7 RH |
2887 | while (fregno <= FP_ARG_V4_MAX_REG) |
2888 | { | |
dfafc897 | 2889 | mem = gen_rtx_MEM (DFmode, plus_constant (save_area, off)); |
ba4828e0 | 2890 | set_mem_alias_set (mem, set); |
dfafc897 | 2891 | emit_move_insn (mem, gen_rtx_REG (DFmode, fregno)); |
4cc833b7 RH |
2892 | fregno++; |
2893 | off += 8; | |
4697a36c | 2894 | } |
4cc833b7 RH |
2895 | |
2896 | emit_label (lab); | |
4697a36c | 2897 | } |
4697a36c | 2898 | } |
4697a36c | 2899 | |
dfafc897 | 2900 | /* Create the va_list data type. */ |
2c4974b7 | 2901 | |
dfafc897 FS |
2902 | tree |
2903 | rs6000_build_va_list () | |
2904 | { | |
bab45a51 | 2905 | tree f_gpr, f_fpr, f_ovf, f_sav, record, type_decl; |
4697a36c | 2906 | |
9ebbca7d GK |
2907 | /* For AIX, prefer 'char *' because that's what the system |
2908 | header files like. */ | |
f607bc57 | 2909 | if (DEFAULT_ABI != ABI_V4) |
9ebbca7d | 2910 | return build_pointer_type (char_type_node); |
dfafc897 | 2911 | |
0f4fd75d | 2912 | record = make_lang_type (RECORD_TYPE); |
bab45a51 | 2913 | type_decl = build_decl (TYPE_DECL, get_identifier ("__va_list_tag"), record); |
0f4fd75d | 2914 | |
9ebbca7d GK |
2915 | f_gpr = build_decl (FIELD_DECL, get_identifier ("gpr"), |
2916 | unsigned_char_type_node); | |
2917 | f_fpr = build_decl (FIELD_DECL, get_identifier ("fpr"), | |
2918 | unsigned_char_type_node); | |
dfafc897 FS |
2919 | f_ovf = build_decl (FIELD_DECL, get_identifier ("overflow_arg_area"), |
2920 | ptr_type_node); | |
2921 | f_sav = build_decl (FIELD_DECL, get_identifier ("reg_save_area"), | |
2922 | ptr_type_node); | |
2923 | ||
2924 | DECL_FIELD_CONTEXT (f_gpr) = record; | |
2925 | DECL_FIELD_CONTEXT (f_fpr) = record; | |
2926 | DECL_FIELD_CONTEXT (f_ovf) = record; | |
2927 | DECL_FIELD_CONTEXT (f_sav) = record; | |
2928 | ||
bab45a51 FS |
2929 | TREE_CHAIN (record) = type_decl; |
2930 | TYPE_NAME (record) = type_decl; | |
dfafc897 FS |
2931 | TYPE_FIELDS (record) = f_gpr; |
2932 | TREE_CHAIN (f_gpr) = f_fpr; | |
2933 | TREE_CHAIN (f_fpr) = f_ovf; | |
2934 | TREE_CHAIN (f_ovf) = f_sav; | |
2935 | ||
2936 | layout_type (record); | |
2937 | ||
2938 | /* The correct type is an array type of one element. */ | |
2939 | return build_array_type (record, build_index_type (size_zero_node)); | |
2940 | } | |
2941 | ||
2942 | /* Implement va_start. */ | |
2943 | ||
2944 | void | |
2945 | rs6000_va_start (stdarg_p, valist, nextarg) | |
2946 | int stdarg_p; | |
2947 | tree valist; | |
2948 | rtx nextarg; | |
4697a36c | 2949 | { |
dfafc897 FS |
2950 | HOST_WIDE_INT words, n_gpr, n_fpr; |
2951 | tree f_gpr, f_fpr, f_ovf, f_sav; | |
2952 | tree gpr, fpr, ovf, sav, t; | |
2c4974b7 | 2953 | |
dfafc897 | 2954 | /* Only SVR4 needs something special. */ |
f607bc57 | 2955 | if (DEFAULT_ABI != ABI_V4) |
dfafc897 FS |
2956 | { |
2957 | std_expand_builtin_va_start (stdarg_p, valist, nextarg); | |
2958 | return; | |
2959 | } | |
2960 | ||
973a648b | 2961 | f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node)); |
dfafc897 FS |
2962 | f_fpr = TREE_CHAIN (f_gpr); |
2963 | f_ovf = TREE_CHAIN (f_fpr); | |
2964 | f_sav = TREE_CHAIN (f_ovf); | |
2965 | ||
8ebecc3b | 2966 | valist = build1 (INDIRECT_REF, TREE_TYPE (TREE_TYPE (valist)), valist); |
dfafc897 FS |
2967 | gpr = build (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr); |
2968 | fpr = build (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr); | |
2969 | ovf = build (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf); | |
2970 | sav = build (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav); | |
2971 | ||
2972 | /* Count number of gp and fp argument registers used. */ | |
4cc833b7 | 2973 | words = current_function_args_info.words; |
dfafc897 FS |
2974 | n_gpr = current_function_args_info.sysv_gregno - GP_ARG_MIN_REG; |
2975 | n_fpr = current_function_args_info.fregno - FP_ARG_MIN_REG; | |
2976 | ||
2977 | if (TARGET_DEBUG_ARG) | |
78e1b90d DE |
2978 | { |
2979 | fputs ("va_start: words = ", stderr); | |
2980 | fprintf (stderr, HOST_WIDE_INT_PRINT_DEC, words); | |
2981 | fputs (", n_gpr = ", stderr); | |
2982 | fprintf (stderr, HOST_WIDE_INT_PRINT_DEC, n_gpr); | |
2983 | fputs (", n_fpr = ", stderr); | |
2984 | fprintf (stderr, HOST_WIDE_INT_PRINT_DEC, n_fpr); | |
2985 | putc ('\n', stderr); | |
2986 | } | |
dfafc897 FS |
2987 | |
2988 | t = build (MODIFY_EXPR, TREE_TYPE (gpr), gpr, build_int_2 (n_gpr, 0)); | |
2989 | TREE_SIDE_EFFECTS (t) = 1; | |
2990 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
2991 | ||
2992 | t = build (MODIFY_EXPR, TREE_TYPE (fpr), fpr, build_int_2 (n_fpr, 0)); | |
2993 | TREE_SIDE_EFFECTS (t) = 1; | |
2994 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
2995 | ||
2996 | /* Find the overflow area. */ | |
2997 | t = make_tree (TREE_TYPE (ovf), virtual_incoming_args_rtx); | |
2998 | if (words != 0) | |
2999 | t = build (PLUS_EXPR, TREE_TYPE (ovf), t, | |
3000 | build_int_2 (words * UNITS_PER_WORD, 0)); | |
3001 | t = build (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t); | |
3002 | TREE_SIDE_EFFECTS (t) = 1; | |
3003 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
3004 | ||
3005 | /* Find the register save area. */ | |
3006 | t = make_tree (TREE_TYPE (sav), virtual_stack_vars_rtx); | |
3007 | t = build (PLUS_EXPR, TREE_TYPE (sav), t, | |
3008 | build_int_2 (-RS6000_VARARGS_SIZE, -1)); | |
3009 | t = build (MODIFY_EXPR, TREE_TYPE (sav), sav, t); | |
3010 | TREE_SIDE_EFFECTS (t) = 1; | |
3011 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
3012 | } | |
3013 | ||
3014 | /* Implement va_arg. */ | |
3015 | ||
3016 | rtx | |
3017 | rs6000_va_arg (valist, type) | |
3018 | tree valist, type; | |
3019 | { | |
3020 | tree f_gpr, f_fpr, f_ovf, f_sav; | |
3021 | tree gpr, fpr, ovf, sav, reg, t, u; | |
3022 | int indirect_p, size, rsize, n_reg, sav_ofs, sav_scale; | |
3023 | rtx lab_false, lab_over, addr_rtx, r; | |
3024 | ||
9ebbca7d GK |
3025 | /* For AIX, the rule is that structures are passed left-aligned in |
3026 | their stack slot. However, GCC does not presently do this: | |
3027 | structures which are the same size as integer types are passed | |
3028 | right-aligned, as if they were in fact integers. This only | |
3029 | matters for structures of size 1 or 2, or 4 when TARGET_64BIT. */ | |
f607bc57 | 3030 | if (DEFAULT_ABI != ABI_V4) |
9ebbca7d GK |
3031 | { |
3032 | HOST_WIDE_INT align, rounded_size; | |
3033 | enum machine_mode mode; | |
3034 | tree addr_tree; | |
3035 | ||
3036 | /* Compute the rounded size of the type. */ | |
3037 | align = PARM_BOUNDARY / BITS_PER_UNIT; | |
3038 | rounded_size = (((int_size_in_bytes (type) + align - 1) / align) | |
3039 | * align); | |
3040 | ||
3041 | addr_tree = valist; | |
3042 | ||
3043 | mode = TYPE_MODE (type); | |
3044 | if (mode != BLKmode) | |
3045 | { | |
3046 | HOST_WIDE_INT adj; | |
3047 | adj = TREE_INT_CST_LOW (TYPE_SIZE (type)) / BITS_PER_UNIT; | |
3048 | if (rounded_size > align) | |
3049 | adj = rounded_size; | |
3050 | ||
3051 | addr_tree = build (PLUS_EXPR, TREE_TYPE (addr_tree), addr_tree, | |
3052 | build_int_2 (rounded_size - adj, 0)); | |
3053 | } | |
3054 | ||
3055 | addr_rtx = expand_expr (addr_tree, NULL_RTX, Pmode, EXPAND_NORMAL); | |
3056 | addr_rtx = copy_to_reg (addr_rtx); | |
3057 | ||
3058 | /* Compute new value for AP. */ | |
3059 | t = build (MODIFY_EXPR, TREE_TYPE (valist), valist, | |
3060 | build (PLUS_EXPR, TREE_TYPE (valist), valist, | |
3061 | build_int_2 (rounded_size, 0))); | |
3062 | TREE_SIDE_EFFECTS (t) = 1; | |
3063 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
3064 | ||
3065 | return addr_rtx; | |
3066 | } | |
dfafc897 | 3067 | |
973a648b | 3068 | f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node)); |
dfafc897 FS |
3069 | f_fpr = TREE_CHAIN (f_gpr); |
3070 | f_ovf = TREE_CHAIN (f_fpr); | |
3071 | f_sav = TREE_CHAIN (f_ovf); | |
3072 | ||
8ebecc3b | 3073 | valist = build1 (INDIRECT_REF, TREE_TYPE (TREE_TYPE (valist)), valist); |
dfafc897 FS |
3074 | gpr = build (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr); |
3075 | fpr = build (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr); | |
3076 | ovf = build (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf); | |
3077 | sav = build (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav); | |
3078 | ||
3079 | size = int_size_in_bytes (type); | |
3080 | rsize = (size + UNITS_PER_WORD - 1) / UNITS_PER_WORD; | |
4cc833b7 | 3081 | |
dfafc897 | 3082 | if (AGGREGATE_TYPE_P (type) || TYPE_MODE (type) == TFmode) |
4cc833b7 | 3083 | { |
dfafc897 FS |
3084 | /* Aggregates and long doubles are passed by reference. */ |
3085 | indirect_p = 1; | |
3086 | reg = gpr; | |
3087 | n_reg = 1; | |
3088 | sav_ofs = 0; | |
3089 | sav_scale = 4; | |
3090 | size = rsize = UNITS_PER_WORD; | |
3091 | } | |
3092 | else if (FLOAT_TYPE_P (type) && ! TARGET_SOFT_FLOAT) | |
3093 | { | |
3094 | /* FP args go in FP registers, if present. */ | |
3095 | indirect_p = 0; | |
3096 | reg = fpr; | |
3097 | n_reg = 1; | |
3098 | sav_ofs = 8*4; | |
3099 | sav_scale = 8; | |
4cc833b7 | 3100 | } |
dfafc897 FS |
3101 | else |
3102 | { | |
3103 | /* Otherwise into GP registers. */ | |
3104 | indirect_p = 0; | |
3105 | reg = gpr; | |
3106 | n_reg = rsize; | |
3107 | sav_ofs = 0; | |
3108 | sav_scale = 4; | |
3109 | } | |
3110 | ||
a4f6c312 | 3111 | /* Pull the value out of the saved registers ... */ |
dfafc897 FS |
3112 | |
3113 | lab_false = gen_label_rtx (); | |
3114 | lab_over = gen_label_rtx (); | |
3115 | addr_rtx = gen_reg_rtx (Pmode); | |
3116 | ||
3117 | emit_cmp_and_jump_insns (expand_expr (reg, NULL_RTX, QImode, EXPAND_NORMAL), | |
a06ef755 RK |
3118 | GEN_INT (8 - n_reg + 1), GE, const1_rtx, QImode, 1, |
3119 | lab_false); | |
2c4974b7 | 3120 | |
dfafc897 FS |
3121 | /* Long long is aligned in the registers. */ |
3122 | if (n_reg > 1) | |
2c4974b7 | 3123 | { |
dfafc897 FS |
3124 | u = build (BIT_AND_EXPR, TREE_TYPE (reg), reg, |
3125 | build_int_2 (n_reg - 1, 0)); | |
3126 | u = build (PLUS_EXPR, TREE_TYPE (reg), reg, u); | |
3127 | u = build (MODIFY_EXPR, TREE_TYPE (reg), reg, u); | |
3128 | TREE_SIDE_EFFECTS (u) = 1; | |
3129 | expand_expr (u, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
2c4974b7 | 3130 | } |
dfafc897 FS |
3131 | |
3132 | if (sav_ofs) | |
3133 | t = build (PLUS_EXPR, ptr_type_node, sav, build_int_2 (sav_ofs, 0)); | |
2c4974b7 | 3134 | else |
dfafc897 | 3135 | t = sav; |
2c4974b7 | 3136 | |
dfafc897 FS |
3137 | u = build (POSTINCREMENT_EXPR, TREE_TYPE (reg), reg, build_int_2 (n_reg, 0)); |
3138 | TREE_SIDE_EFFECTS (u) = 1; | |
2c4974b7 | 3139 | |
dfafc897 FS |
3140 | u = build1 (CONVERT_EXPR, integer_type_node, u); |
3141 | TREE_SIDE_EFFECTS (u) = 1; | |
2c4974b7 | 3142 | |
dfafc897 FS |
3143 | u = build (MULT_EXPR, integer_type_node, u, build_int_2 (sav_scale, 0)); |
3144 | TREE_SIDE_EFFECTS (u) = 1; | |
3145 | ||
3146 | t = build (PLUS_EXPR, ptr_type_node, t, u); | |
3147 | TREE_SIDE_EFFECTS (t) = 1; | |
3148 | ||
3149 | r = expand_expr (t, addr_rtx, Pmode, EXPAND_NORMAL); | |
3150 | if (r != addr_rtx) | |
3151 | emit_move_insn (addr_rtx, r); | |
3152 | ||
3153 | emit_jump_insn (gen_jump (lab_over)); | |
3154 | emit_barrier (); | |
3155 | emit_label (lab_false); | |
3156 | ||
a4f6c312 | 3157 | /* ... otherwise out of the overflow area. */ |
dfafc897 FS |
3158 | |
3159 | /* Make sure we don't find reg 7 for the next int arg. */ | |
3160 | if (n_reg > 1) | |
3161 | { | |
3162 | t = build (MODIFY_EXPR, TREE_TYPE (reg), reg, build_int_2 (8, 0)); | |
3163 | TREE_SIDE_EFFECTS (t) = 1; | |
3164 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
3165 | } | |
3166 | ||
3167 | /* Care for on-stack alignment if needed. */ | |
3168 | if (rsize <= 1) | |
3169 | t = ovf; | |
3170 | else | |
3171 | { | |
3172 | t = build (PLUS_EXPR, TREE_TYPE (ovf), ovf, build_int_2 (7, 0)); | |
3173 | t = build (BIT_AND_EXPR, TREE_TYPE (t), t, build_int_2 (-8, -1)); | |
3174 | } | |
3175 | t = save_expr (t); | |
3176 | ||
3177 | r = expand_expr (t, addr_rtx, Pmode, EXPAND_NORMAL); | |
3178 | if (r != addr_rtx) | |
3179 | emit_move_insn (addr_rtx, r); | |
3180 | ||
3181 | t = build (PLUS_EXPR, TREE_TYPE (t), t, build_int_2 (size, 0)); | |
3182 | t = build (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t); | |
3183 | TREE_SIDE_EFFECTS (t) = 1; | |
3184 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
3185 | ||
3186 | emit_label (lab_over); | |
3187 | ||
3188 | if (indirect_p) | |
3189 | { | |
3190 | r = gen_rtx_MEM (Pmode, addr_rtx); | |
ba4828e0 | 3191 | set_mem_alias_set (r, get_varargs_alias_set ()); |
dfafc897 FS |
3192 | emit_move_insn (addr_rtx, r); |
3193 | } | |
3194 | ||
3195 | return addr_rtx; | |
4697a36c | 3196 | } |
0ac081f6 AH |
3197 | |
3198 | /* Builtins. */ | |
3199 | ||
3200 | #define def_builtin(MASK, NAME, TYPE, CODE) \ | |
3201 | do { \ | |
3202 | if ((MASK) & target_flags) \ | |
3203 | builtin_function ((NAME), (TYPE), (CODE), BUILT_IN_MD, NULL); \ | |
3204 | } while (0) | |
3205 | ||
3206 | struct builtin_description | |
3207 | { | |
3208 | const unsigned int mask; | |
3209 | const enum insn_code icode; | |
3210 | const char *const name; | |
3211 | const enum rs6000_builtins code; | |
3212 | }; | |
24408032 AH |
3213 | |
3214 | /* Simple ternary operations: VECd = foo (VECa, VECb, VECc). */ | |
3215 | ||
2212663f | 3216 | static const struct builtin_description bdesc_3arg[] = |
24408032 AH |
3217 | { |
3218 | { MASK_ALTIVEC, CODE_FOR_altivec_vmaddfp, "__builtin_altivec_vmaddfp", ALTIVEC_BUILTIN_VMADDFP }, | |
3219 | { MASK_ALTIVEC, CODE_FOR_altivec_vmhaddshs, "__builtin_altivec_vmhaddshs", ALTIVEC_BUILTIN_VMHADDSHS }, | |
3220 | { MASK_ALTIVEC, CODE_FOR_altivec_vmhraddshs, "__builtin_altivec_vmhraddshs", ALTIVEC_BUILTIN_VMHRADDSHS }, | |
3221 | { MASK_ALTIVEC, CODE_FOR_altivec_vmladduhm, "__builtin_altivec_vmladduhm", ALTIVEC_BUILTIN_VMLADDUHM}, | |
3222 | { MASK_ALTIVEC, CODE_FOR_altivec_vmsumubm, "__builtin_altivec_vmsumubm", ALTIVEC_BUILTIN_VMSUMUBM }, | |
3223 | { MASK_ALTIVEC, CODE_FOR_altivec_vmsummbm, "__builtin_altivec_vmsummbm", ALTIVEC_BUILTIN_VMSUMMBM }, | |
3224 | { MASK_ALTIVEC, CODE_FOR_altivec_vmsumuhm, "__builtin_altivec_vmsumuhm", ALTIVEC_BUILTIN_VMSUMUHM }, | |
3225 | { MASK_ALTIVEC, CODE_FOR_altivec_vmsumshm, "__builtin_altivec_vmsumshm", ALTIVEC_BUILTIN_VMSUMSHM }, | |
3226 | { MASK_ALTIVEC, CODE_FOR_altivec_vmsumuhs, "__builtin_altivec_vmsumuhs", ALTIVEC_BUILTIN_VMSUMUHS }, | |
3227 | { MASK_ALTIVEC, CODE_FOR_altivec_vmsumshs, "__builtin_altivec_vmsumshs", ALTIVEC_BUILTIN_VMSUMSHS }, | |
3228 | { MASK_ALTIVEC, CODE_FOR_altivec_vnmsubfp, "__builtin_altivec_vnmsubfp", ALTIVEC_BUILTIN_VNMSUBFP }, | |
3229 | { MASK_ALTIVEC, CODE_FOR_altivec_vperm_4sf, "__builtin_altivec_vperm_4sf", ALTIVEC_BUILTIN_VPERM_4SF }, | |
3230 | { MASK_ALTIVEC, CODE_FOR_altivec_vperm_4si, "__builtin_altivec_vperm_4si", ALTIVEC_BUILTIN_VPERM_4SI }, | |
3231 | { MASK_ALTIVEC, CODE_FOR_altivec_vperm_8hi, "__builtin_altivec_vperm_8hi", ALTIVEC_BUILTIN_VPERM_8HI }, | |
3232 | { MASK_ALTIVEC, CODE_FOR_altivec_vperm_16qi, "__builtin_altivec_vperm_16qi", ALTIVEC_BUILTIN_VPERM_16QI }, | |
3233 | { MASK_ALTIVEC, CODE_FOR_altivec_vsel_4sf, "__builtin_altivec_vsel_4sf", ALTIVEC_BUILTIN_VSEL_4SF }, | |
3234 | { MASK_ALTIVEC, CODE_FOR_altivec_vsel_4si, "__builtin_altivec_vsel_4si", ALTIVEC_BUILTIN_VSEL_4SI }, | |
3235 | { MASK_ALTIVEC, CODE_FOR_altivec_vsel_8hi, "__builtin_altivec_vsel_8hi", ALTIVEC_BUILTIN_VSEL_8HI }, | |
3236 | { MASK_ALTIVEC, CODE_FOR_altivec_vsel_16qi, "__builtin_altivec_vsel_16qi", ALTIVEC_BUILTIN_VSEL_16QI }, | |
3237 | { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_16qi, "__builtin_altivec_vsldoi_16qi", ALTIVEC_BUILTIN_VSLDOI_16QI }, | |
3238 | { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_8hi, "__builtin_altivec_vsldoi_8hi", ALTIVEC_BUILTIN_VSLDOI_8HI }, | |
3239 | { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_4si, "__builtin_altivec_vsldoi_4si", ALTIVEC_BUILTIN_VSLDOI_4SI }, | |
3240 | { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_4sf, "__builtin_altivec_vsldoi_4sf", ALTIVEC_BUILTIN_VSLDOI_4SF }, | |
3241 | }; | |
2212663f | 3242 | |
95385cbb AH |
3243 | /* DST operations: void foo (void *, const int, const char). */ |
3244 | ||
3245 | static const struct builtin_description bdesc_dst[] = | |
3246 | { | |
3247 | { MASK_ALTIVEC, CODE_FOR_altivec_dst, "__builtin_altivec_dst", ALTIVEC_BUILTIN_DST }, | |
3248 | { MASK_ALTIVEC, CODE_FOR_altivec_dstt, "__builtin_altivec_dstt", ALTIVEC_BUILTIN_DSTT }, | |
3249 | { MASK_ALTIVEC, CODE_FOR_altivec_dstst, "__builtin_altivec_dstst", ALTIVEC_BUILTIN_DSTST }, | |
3250 | { MASK_ALTIVEC, CODE_FOR_altivec_dststt, "__builtin_altivec_dststt", ALTIVEC_BUILTIN_DSTSTT } | |
3251 | }; | |
3252 | ||
2212663f | 3253 | /* Simple binary operations: VECc = foo (VECa, VECb). */ |
24408032 | 3254 | |
0ac081f6 AH |
3255 | static const struct builtin_description bdesc_2arg[] = |
3256 | { | |
f18c054f DB |
3257 | { MASK_ALTIVEC, CODE_FOR_addv16qi3, "__builtin_altivec_vaddubm", ALTIVEC_BUILTIN_VADDUBM }, |
3258 | { MASK_ALTIVEC, CODE_FOR_addv8hi3, "__builtin_altivec_vadduhm", ALTIVEC_BUILTIN_VADDUHM }, | |
3259 | { MASK_ALTIVEC, CODE_FOR_addv4si3, "__builtin_altivec_vadduwm", ALTIVEC_BUILTIN_VADDUWM }, | |
3260 | { MASK_ALTIVEC, CODE_FOR_addv4sf3, "__builtin_altivec_vaddfp", ALTIVEC_BUILTIN_VADDFP }, | |
0ac081f6 AH |
3261 | { MASK_ALTIVEC, CODE_FOR_altivec_vaddcuw, "__builtin_altivec_vaddcuw", ALTIVEC_BUILTIN_VADDCUW }, |
3262 | { MASK_ALTIVEC, CODE_FOR_altivec_vaddubs, "__builtin_altivec_vaddubs", ALTIVEC_BUILTIN_VADDUBS }, | |
3263 | { MASK_ALTIVEC, CODE_FOR_altivec_vaddsbs, "__builtin_altivec_vaddsbs", ALTIVEC_BUILTIN_VADDSBS }, | |
3264 | { MASK_ALTIVEC, CODE_FOR_altivec_vadduhs, "__builtin_altivec_vadduhs", ALTIVEC_BUILTIN_VADDUHS }, | |
3265 | { MASK_ALTIVEC, CODE_FOR_altivec_vaddshs, "__builtin_altivec_vaddshs", ALTIVEC_BUILTIN_VADDSHS }, | |
3266 | { MASK_ALTIVEC, CODE_FOR_altivec_vadduws, "__builtin_altivec_vadduws", ALTIVEC_BUILTIN_VADDUWS }, | |
3267 | { MASK_ALTIVEC, CODE_FOR_altivec_vaddsws, "__builtin_altivec_vaddsws", ALTIVEC_BUILTIN_VADDSWS }, | |
f18c054f | 3268 | { MASK_ALTIVEC, CODE_FOR_andv4si3, "__builtin_altivec_vand", ALTIVEC_BUILTIN_VAND }, |
0ac081f6 AH |
3269 | { MASK_ALTIVEC, CODE_FOR_altivec_vandc, "__builtin_altivec_vandc", ALTIVEC_BUILTIN_VANDC }, |
3270 | { MASK_ALTIVEC, CODE_FOR_altivec_vavgub, "__builtin_altivec_vavgub", ALTIVEC_BUILTIN_VAVGUB }, | |
3271 | { MASK_ALTIVEC, CODE_FOR_altivec_vavgsb, "__builtin_altivec_vavgsb", ALTIVEC_BUILTIN_VAVGSB }, | |
3272 | { MASK_ALTIVEC, CODE_FOR_altivec_vavguh, "__builtin_altivec_vavguh", ALTIVEC_BUILTIN_VAVGUH }, | |
3273 | { MASK_ALTIVEC, CODE_FOR_altivec_vavgsh, "__builtin_altivec_vavgsh", ALTIVEC_BUILTIN_VAVGSH }, | |
3274 | { MASK_ALTIVEC, CODE_FOR_altivec_vavguw, "__builtin_altivec_vavguw", ALTIVEC_BUILTIN_VAVGUW }, | |
3275 | { MASK_ALTIVEC, CODE_FOR_altivec_vavgsw, "__builtin_altivec_vavgsw", ALTIVEC_BUILTIN_VAVGSW }, | |
617e0e1d DB |
3276 | { MASK_ALTIVEC, CODE_FOR_altivec_vcfux, "__builtin_altivec_vcfux", ALTIVEC_BUILTIN_VCFUX }, |
3277 | { MASK_ALTIVEC, CODE_FOR_altivec_vcfsx, "__builtin_altivec_vcfsx", ALTIVEC_BUILTIN_VCFSX }, | |
0ac081f6 AH |
3278 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpbfp, "__builtin_altivec_vcmpbfp", ALTIVEC_BUILTIN_VCMPBFP }, |
3279 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequb, "__builtin_altivec_vcmpequb", ALTIVEC_BUILTIN_VCMPEQUB }, | |
3280 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequh, "__builtin_altivec_vcmpequh", ALTIVEC_BUILTIN_VCMPEQUH }, | |
3281 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequw, "__builtin_altivec_vcmpequw", ALTIVEC_BUILTIN_VCMPEQUW }, | |
3282 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpeqfp, "__builtin_altivec_vcmpeqfp", ALTIVEC_BUILTIN_VCMPEQFP }, | |
3283 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgefp, "__builtin_altivec_vcmpgefp", ALTIVEC_BUILTIN_VCMPGEFP }, | |
3284 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtub, "__builtin_altivec_vcmpgtub", ALTIVEC_BUILTIN_VCMPGTUB }, | |
3285 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsb, "__builtin_altivec_vcmpgtsb", ALTIVEC_BUILTIN_VCMPGTSB }, | |
3286 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtuh, "__builtin_altivec_vcmpgtuh", ALTIVEC_BUILTIN_VCMPGTUH }, | |
3287 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsh, "__builtin_altivec_vcmpgtsh", ALTIVEC_BUILTIN_VCMPGTSH }, | |
3288 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtuw, "__builtin_altivec_vcmpgtuw", ALTIVEC_BUILTIN_VCMPGTUW }, | |
3289 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsw, "__builtin_altivec_vcmpgtsw", ALTIVEC_BUILTIN_VCMPGTSW }, | |
3290 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtfp, "__builtin_altivec_vcmpgtfp", ALTIVEC_BUILTIN_VCMPGTFP }, | |
617e0e1d DB |
3291 | { MASK_ALTIVEC, CODE_FOR_altivec_vctsxs, "__builtin_altivec_vctsxs", ALTIVEC_BUILTIN_VCTSXS }, |
3292 | { MASK_ALTIVEC, CODE_FOR_altivec_vctuxs, "__builtin_altivec_vctuxs", ALTIVEC_BUILTIN_VCTUXS }, | |
f18c054f DB |
3293 | { MASK_ALTIVEC, CODE_FOR_umaxv16qi3, "__builtin_altivec_vmaxub", ALTIVEC_BUILTIN_VMAXUB }, |
3294 | { MASK_ALTIVEC, CODE_FOR_smaxv16qi3, "__builtin_altivec_vmaxsb", ALTIVEC_BUILTIN_VMAXSB }, | |
3295 | { MASK_ALTIVEC, CODE_FOR_uminv8hi3, "__builtin_altivec_vmaxuh", ALTIVEC_BUILTIN_VMAXUH }, | |
3296 | { MASK_ALTIVEC, CODE_FOR_sminv8hi3, "__builtin_altivec_vmaxsh", ALTIVEC_BUILTIN_VMAXSH }, | |
3297 | { MASK_ALTIVEC, CODE_FOR_uminv4si3, "__builtin_altivec_vmaxuw", ALTIVEC_BUILTIN_VMAXUW }, | |
3298 | { MASK_ALTIVEC, CODE_FOR_sminv4si3, "__builtin_altivec_vmaxsw", ALTIVEC_BUILTIN_VMAXSW }, | |
3299 | { MASK_ALTIVEC, CODE_FOR_sminv4sf3, "__builtin_altivec_vmaxfp", ALTIVEC_BUILTIN_VMAXFP }, | |
0ac081f6 AH |
3300 | { MASK_ALTIVEC, CODE_FOR_altivec_vmrghb, "__builtin_altivec_vmrghb", ALTIVEC_BUILTIN_VMRGHB }, |
3301 | { MASK_ALTIVEC, CODE_FOR_altivec_vmrghh, "__builtin_altivec_vmrghh", ALTIVEC_BUILTIN_VMRGHH }, | |
3302 | { MASK_ALTIVEC, CODE_FOR_altivec_vmrghw, "__builtin_altivec_vmrghw", ALTIVEC_BUILTIN_VMRGHW }, | |
3303 | { MASK_ALTIVEC, CODE_FOR_altivec_vmrglb, "__builtin_altivec_vmrglb", ALTIVEC_BUILTIN_VMRGLB }, | |
3304 | { MASK_ALTIVEC, CODE_FOR_altivec_vmrglh, "__builtin_altivec_vmrglh", ALTIVEC_BUILTIN_VMRGLH }, | |
3305 | { MASK_ALTIVEC, CODE_FOR_altivec_vmrglw, "__builtin_altivec_vmrglw", ALTIVEC_BUILTIN_VMRGLW }, | |
f18c054f DB |
3306 | { MASK_ALTIVEC, CODE_FOR_uminv16qi3, "__builtin_altivec_vminub", ALTIVEC_BUILTIN_VMINUB }, |
3307 | { MASK_ALTIVEC, CODE_FOR_sminv16qi3, "__builtin_altivec_vminsb", ALTIVEC_BUILTIN_VMINSB }, | |
3308 | { MASK_ALTIVEC, CODE_FOR_uminv8hi3, "__builtin_altivec_vminuh", ALTIVEC_BUILTIN_VMINUH }, | |
3309 | { MASK_ALTIVEC, CODE_FOR_sminv8hi3, "__builtin_altivec_vminsh", ALTIVEC_BUILTIN_VMINSH }, | |
3310 | { MASK_ALTIVEC, CODE_FOR_uminv4si3, "__builtin_altivec_vminuw", ALTIVEC_BUILTIN_VMINUW }, | |
3311 | { MASK_ALTIVEC, CODE_FOR_sminv4si3, "__builtin_altivec_vminsw", ALTIVEC_BUILTIN_VMINSW }, | |
3312 | { MASK_ALTIVEC, CODE_FOR_sminv4sf3, "__builtin_altivec_vminfp", ALTIVEC_BUILTIN_VMINFP }, | |
0ac081f6 AH |
3313 | { MASK_ALTIVEC, CODE_FOR_altivec_vmuleub, "__builtin_altivec_vmuleub", ALTIVEC_BUILTIN_VMULEUB }, |
3314 | { MASK_ALTIVEC, CODE_FOR_altivec_vmulesb, "__builtin_altivec_vmulesb", ALTIVEC_BUILTIN_VMULESB }, | |
3315 | { MASK_ALTIVEC, CODE_FOR_altivec_vmuleuh, "__builtin_altivec_vmuleuh", ALTIVEC_BUILTIN_VMULEUH }, | |
3316 | { MASK_ALTIVEC, CODE_FOR_altivec_vmulesh, "__builtin_altivec_vmulesh", ALTIVEC_BUILTIN_VMULESH }, | |
3317 | { MASK_ALTIVEC, CODE_FOR_altivec_vmuloub, "__builtin_altivec_vmuloub", ALTIVEC_BUILTIN_VMULOUB }, | |
3318 | { MASK_ALTIVEC, CODE_FOR_altivec_vmulosb, "__builtin_altivec_vmulosb", ALTIVEC_BUILTIN_VMULOSB }, | |
3319 | { MASK_ALTIVEC, CODE_FOR_altivec_vmulouh, "__builtin_altivec_vmulouh", ALTIVEC_BUILTIN_VMULOUH }, | |
3320 | { MASK_ALTIVEC, CODE_FOR_altivec_vmulosh, "__builtin_altivec_vmulosh", ALTIVEC_BUILTIN_VMULOSH }, | |
3321 | { MASK_ALTIVEC, CODE_FOR_altivec_vnor, "__builtin_altivec_vnor", ALTIVEC_BUILTIN_VNOR }, | |
f18c054f | 3322 | { MASK_ALTIVEC, CODE_FOR_iorv4si3, "__builtin_altivec_vor", ALTIVEC_BUILTIN_VOR }, |
0ac081f6 AH |
3323 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhum, "__builtin_altivec_vpkuhum", ALTIVEC_BUILTIN_VPKUHUM }, |
3324 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwum, "__builtin_altivec_vpkuwum", ALTIVEC_BUILTIN_VPKUWUM }, | |
3325 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkpx, "__builtin_altivec_vpkpx", ALTIVEC_BUILTIN_VPKPX }, | |
3326 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhss, "__builtin_altivec_vpkuhss", ALTIVEC_BUILTIN_VPKUHSS }, | |
3327 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkshss, "__builtin_altivec_vpkshss", ALTIVEC_BUILTIN_VPKSHSS }, | |
3328 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwss, "__builtin_altivec_vpkuwss", ALTIVEC_BUILTIN_VPKUWSS }, | |
3329 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkswss, "__builtin_altivec_vpkswss", ALTIVEC_BUILTIN_VPKSWSS }, | |
3330 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhus, "__builtin_altivec_vpkuhus", ALTIVEC_BUILTIN_VPKUHUS }, | |
3331 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkshus, "__builtin_altivec_vpkshus", ALTIVEC_BUILTIN_VPKSHUS }, | |
3332 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwus, "__builtin_altivec_vpkuwus", ALTIVEC_BUILTIN_VPKUWUS }, | |
3333 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkswus, "__builtin_altivec_vpkswus", ALTIVEC_BUILTIN_VPKSWUS }, | |
3334 | { MASK_ALTIVEC, CODE_FOR_altivec_vrlb, "__builtin_altivec_vrlb", ALTIVEC_BUILTIN_VRLB }, | |
3335 | { MASK_ALTIVEC, CODE_FOR_altivec_vrlh, "__builtin_altivec_vrlh", ALTIVEC_BUILTIN_VRLH }, | |
3336 | { MASK_ALTIVEC, CODE_FOR_altivec_vrlw, "__builtin_altivec_vrlw", ALTIVEC_BUILTIN_VRLW }, | |
3337 | { MASK_ALTIVEC, CODE_FOR_altivec_vslb, "__builtin_altivec_vslb", ALTIVEC_BUILTIN_VSLB }, | |
3338 | { MASK_ALTIVEC, CODE_FOR_altivec_vslh, "__builtin_altivec_vslh", ALTIVEC_BUILTIN_VSLH }, | |
3339 | { MASK_ALTIVEC, CODE_FOR_altivec_vslw, "__builtin_altivec_vslw", ALTIVEC_BUILTIN_VSLW }, | |
3340 | { MASK_ALTIVEC, CODE_FOR_altivec_vsl, "__builtin_altivec_vsl", ALTIVEC_BUILTIN_VSL }, | |
3341 | { MASK_ALTIVEC, CODE_FOR_altivec_vslo, "__builtin_altivec_vslo", ALTIVEC_BUILTIN_VSLO }, | |
2212663f DB |
3342 | { MASK_ALTIVEC, CODE_FOR_altivec_vspltb, "__builtin_altivec_vspltb", ALTIVEC_BUILTIN_VSPLTB }, |
3343 | { MASK_ALTIVEC, CODE_FOR_altivec_vsplth, "__builtin_altivec_vsplth", ALTIVEC_BUILTIN_VSPLTH }, | |
3344 | { MASK_ALTIVEC, CODE_FOR_altivec_vspltw, "__builtin_altivec_vspltw", ALTIVEC_BUILTIN_VSPLTW }, | |
0ac081f6 | 3345 | { MASK_ALTIVEC, CODE_FOR_altivec_vsrb, "__builtin_altivec_vsrb", ALTIVEC_BUILTIN_VSRB }, |
f18c054f DB |
3346 | { MASK_ALTIVEC, CODE_FOR_altivec_vsrh, "__builtin_altivec_vsrh", ALTIVEC_BUILTIN_VSRH }, |
3347 | { MASK_ALTIVEC, CODE_FOR_altivec_vsrw, "__builtin_altivec_vsrw", ALTIVEC_BUILTIN_VSRW }, | |
0ac081f6 AH |
3348 | { MASK_ALTIVEC, CODE_FOR_altivec_vsrab, "__builtin_altivec_vsrab", ALTIVEC_BUILTIN_VSRAB }, |
3349 | { MASK_ALTIVEC, CODE_FOR_altivec_vsrah, "__builtin_altivec_vsrah", ALTIVEC_BUILTIN_VSRAH }, | |
3350 | { MASK_ALTIVEC, CODE_FOR_altivec_vsraw, "__builtin_altivec_vsraw", ALTIVEC_BUILTIN_VSRAW }, | |
3351 | { MASK_ALTIVEC, CODE_FOR_altivec_vsr, "__builtin_altivec_vsr", ALTIVEC_BUILTIN_VSR }, | |
3352 | { MASK_ALTIVEC, CODE_FOR_altivec_vsro, "__builtin_altivec_vsro", ALTIVEC_BUILTIN_VSRO }, | |
f18c054f DB |
3353 | { MASK_ALTIVEC, CODE_FOR_subv16qi3, "__builtin_altivec_vsububm", ALTIVEC_BUILTIN_VSUBUBM }, |
3354 | { MASK_ALTIVEC, CODE_FOR_subv8hi3, "__builtin_altivec_vsubuhm", ALTIVEC_BUILTIN_VSUBUHM }, | |
3355 | { MASK_ALTIVEC, CODE_FOR_subv4si3, "__builtin_altivec_vsubuwm", ALTIVEC_BUILTIN_VSUBUWM }, | |
3356 | { MASK_ALTIVEC, CODE_FOR_subv4sf3, "__builtin_altivec_vsubfp", ALTIVEC_BUILTIN_VSUBFP }, | |
0ac081f6 AH |
3357 | { MASK_ALTIVEC, CODE_FOR_altivec_vsubcuw, "__builtin_altivec_vsubcuw", ALTIVEC_BUILTIN_VSUBCUW }, |
3358 | { MASK_ALTIVEC, CODE_FOR_altivec_vsububs, "__builtin_altivec_vsububs", ALTIVEC_BUILTIN_VSUBUBS }, | |
3359 | { MASK_ALTIVEC, CODE_FOR_altivec_vsubsbs, "__builtin_altivec_vsubsbs", ALTIVEC_BUILTIN_VSUBSBS }, | |
3360 | { MASK_ALTIVEC, CODE_FOR_altivec_vsubuhs, "__builtin_altivec_vsubuhs", ALTIVEC_BUILTIN_VSUBUHS }, | |
3361 | { MASK_ALTIVEC, CODE_FOR_altivec_vsubshs, "__builtin_altivec_vsubshs", ALTIVEC_BUILTIN_VSUBSHS }, | |
3362 | { MASK_ALTIVEC, CODE_FOR_altivec_vsubuws, "__builtin_altivec_vsubuws", ALTIVEC_BUILTIN_VSUBUWS }, | |
3363 | { MASK_ALTIVEC, CODE_FOR_altivec_vsubsws, "__builtin_altivec_vsubsws", ALTIVEC_BUILTIN_VSUBSWS }, | |
3364 | { MASK_ALTIVEC, CODE_FOR_altivec_vsum4ubs, "__builtin_altivec_vsum4ubs", ALTIVEC_BUILTIN_VSUM4UBS }, | |
3365 | { MASK_ALTIVEC, CODE_FOR_altivec_vsum4sbs, "__builtin_altivec_vsum4sbs", ALTIVEC_BUILTIN_VSUM4SBS }, | |
3366 | { MASK_ALTIVEC, CODE_FOR_altivec_vsum4shs, "__builtin_altivec_vsum4shs", ALTIVEC_BUILTIN_VSUM4SHS }, | |
3367 | { MASK_ALTIVEC, CODE_FOR_altivec_vsum2sws, "__builtin_altivec_vsum2sws", ALTIVEC_BUILTIN_VSUM2SWS }, | |
3368 | { MASK_ALTIVEC, CODE_FOR_altivec_vsumsws, "__builtin_altivec_vsumsws", ALTIVEC_BUILTIN_VSUMSWS }, | |
f18c054f | 3369 | { MASK_ALTIVEC, CODE_FOR_xorv4si3, "__builtin_altivec_vxor", ALTIVEC_BUILTIN_VXOR }, |
fa066a23 AH |
3370 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpbfp_p, "__builtin_altivec_vcmpbfp_p", ALTIVEC_BUILTIN_VCMPBFP_P }, |
3371 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpeqfp_p, "__builtin_altivec_vcmpeqfp_p", ALTIVEC_BUILTIN_VCMPEQFP_P }, | |
3372 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequb_p, "__builtin_altivec_vcmpequb_p", ALTIVEC_BUILTIN_VCMPEQUB_P }, | |
3373 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequh_p, "__builtin_altivec_vcmpequh_p", ALTIVEC_BUILTIN_VCMPEQUH_P }, | |
3374 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequw_p, "__builtin_altivec_vcmpequw_p", ALTIVEC_BUILTIN_VCMPEQUW_P }, | |
3375 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgefp_p, "__builtin_altivec_vcmpgefp_p", ALTIVEC_BUILTIN_VCMPGEFP_P }, | |
3376 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtfp_p, "__builtin_altivec_vcmpgtfp_p", ALTIVEC_BUILTIN_VCMPGTFP_P }, | |
3377 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsb_p, "__builtin_altivec_vcmpgtsb_p", ALTIVEC_BUILTIN_VCMPGTSB_P }, | |
3378 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsh_p, "__builtin_altivec_vcmpgtsh_p", ALTIVEC_BUILTIN_VCMPGTSH_P }, | |
3379 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsw_p, "__builtin_altivec_vcmpgtsw_p", ALTIVEC_BUILTIN_VCMPGTSW_P }, | |
3380 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtub_p, "__builtin_altivec_vcmpgtub_p", ALTIVEC_BUILTIN_VCMPGTUB_P }, | |
3381 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtuh_p, "__builtin_altivec_vcmpgtuh_p", ALTIVEC_BUILTIN_VCMPGTUH_P }, | |
3382 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtuw_p, "__builtin_altivec_vcmpgtuw_p", ALTIVEC_BUILTIN_VCMPGTUW_P }, | |
0ac081f6 | 3383 | }; |
24408032 | 3384 | |
617e0e1d DB |
3385 | /* Simple unary operations: VECb = foo (unsigned literal) or VECb = |
3386 | foo (VECa). */ | |
24408032 | 3387 | |
2212663f DB |
3388 | static const struct builtin_description bdesc_1arg[] = |
3389 | { | |
617e0e1d DB |
3390 | { MASK_ALTIVEC, CODE_FOR_altivec_vexptefp, "__builtin_altivec_vexptefp", ALTIVEC_BUILTIN_VEXPTEFP }, |
3391 | { MASK_ALTIVEC, CODE_FOR_altivec_vlogefp, "__builtin_altivec_vlogefp", ALTIVEC_BUILTIN_VLOGEFP }, | |
3392 | { MASK_ALTIVEC, CODE_FOR_altivec_vrefp, "__builtin_altivec_vrefp", ALTIVEC_BUILTIN_VREFP }, | |
3393 | { MASK_ALTIVEC, CODE_FOR_altivec_vrfim, "__builtin_altivec_vrfim", ALTIVEC_BUILTIN_VRFIM }, | |
3394 | { MASK_ALTIVEC, CODE_FOR_altivec_vrfin, "__builtin_altivec_vrfin", ALTIVEC_BUILTIN_VRFIN }, | |
3395 | { MASK_ALTIVEC, CODE_FOR_altivec_vrfip, "__builtin_altivec_vrfip", ALTIVEC_BUILTIN_VRFIP }, | |
3396 | { MASK_ALTIVEC, CODE_FOR_ftruncv4sf2, "__builtin_altivec_vrfiz", ALTIVEC_BUILTIN_VRFIZ }, | |
3397 | { MASK_ALTIVEC, CODE_FOR_altivec_vrsqrtefp, "__builtin_altivec_vrsqrtefp", ALTIVEC_BUILTIN_VRSQRTEFP }, | |
2212663f DB |
3398 | { MASK_ALTIVEC, CODE_FOR_altivec_vspltisb, "__builtin_altivec_vspltisb", ALTIVEC_BUILTIN_VSPLTISB }, |
3399 | { MASK_ALTIVEC, CODE_FOR_altivec_vspltish, "__builtin_altivec_vspltish", ALTIVEC_BUILTIN_VSPLTISH }, | |
3400 | { MASK_ALTIVEC, CODE_FOR_altivec_vspltisw, "__builtin_altivec_vspltisw", ALTIVEC_BUILTIN_VSPLTISW }, | |
20e26713 AH |
3401 | { MASK_ALTIVEC, CODE_FOR_altivec_vupkhsb, "__builtin_altivec_vupkhsb", ALTIVEC_BUILTIN_VUPKHSB }, |
3402 | { MASK_ALTIVEC, CODE_FOR_altivec_vupkhpx, "__builtin_altivec_vupkhpx", ALTIVEC_BUILTIN_VUPKHPX }, | |
3403 | { MASK_ALTIVEC, CODE_FOR_altivec_vupkhsh, "__builtin_altivec_vupkhsh", ALTIVEC_BUILTIN_VUPKHSH }, | |
3404 | { MASK_ALTIVEC, CODE_FOR_altivec_vupklsb, "__builtin_altivec_vupklsb", ALTIVEC_BUILTIN_VUPKLSB }, | |
3405 | { MASK_ALTIVEC, CODE_FOR_altivec_vupklpx, "__builtin_altivec_vupklpx", ALTIVEC_BUILTIN_VUPKLPX }, | |
3406 | { MASK_ALTIVEC, CODE_FOR_altivec_vupklsh, "__builtin_altivec_vupklsh", ALTIVEC_BUILTIN_VUPKLSH }, | |
2212663f DB |
3407 | }; |
3408 | ||
3409 | static rtx | |
3410 | altivec_expand_unop_builtin (icode, arglist, target) | |
3411 | enum insn_code icode; | |
3412 | tree arglist; | |
3413 | rtx target; | |
3414 | { | |
3415 | rtx pat; | |
3416 | tree arg0 = TREE_VALUE (arglist); | |
3417 | rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
3418 | enum machine_mode tmode = insn_data[icode].operand[0].mode; | |
3419 | enum machine_mode mode0 = insn_data[icode].operand[1].mode; | |
3420 | ||
20e26713 AH |
3421 | /* If we got invalid arguments bail out before generating bad rtl. */ |
3422 | if (arg0 == error_mark_node) | |
95385cbb | 3423 | return NULL_RTX; |
20e26713 | 3424 | |
c62f2db5 | 3425 | if (target == 0 |
2212663f DB |
3426 | || GET_MODE (target) != tmode |
3427 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
3428 | target = gen_reg_rtx (tmode); | |
3429 | ||
3430 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) | |
3431 | op0 = copy_to_mode_reg (mode0, op0); | |
3432 | ||
3433 | pat = GEN_FCN (icode) (target, op0); | |
3434 | if (! pat) | |
3435 | return 0; | |
3436 | emit_insn (pat); | |
0ac081f6 | 3437 | |
2212663f DB |
3438 | return target; |
3439 | } | |
0ac081f6 AH |
3440 | static rtx |
3441 | altivec_expand_binop_builtin (icode, arglist, target) | |
3442 | enum insn_code icode; | |
3443 | tree arglist; | |
3444 | rtx target; | |
3445 | { | |
3446 | rtx pat; | |
3447 | tree arg0 = TREE_VALUE (arglist); | |
3448 | tree arg1 = TREE_VALUE (TREE_CHAIN (arglist)); | |
3449 | rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
3450 | rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); | |
3451 | enum machine_mode tmode = insn_data[icode].operand[0].mode; | |
3452 | enum machine_mode mode0 = insn_data[icode].operand[1].mode; | |
3453 | enum machine_mode mode1 = insn_data[icode].operand[2].mode; | |
3454 | ||
20e26713 AH |
3455 | /* If we got invalid arguments bail out before generating bad rtl. */ |
3456 | if (arg0 == error_mark_node || arg1 == error_mark_node) | |
95385cbb | 3457 | return NULL_RTX; |
20e26713 | 3458 | |
c62f2db5 | 3459 | if (target == 0 |
0ac081f6 AH |
3460 | || GET_MODE (target) != tmode |
3461 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
3462 | target = gen_reg_rtx (tmode); | |
3463 | ||
3464 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) | |
3465 | op0 = copy_to_mode_reg (mode0, op0); | |
3466 | if (! (*insn_data[icode].operand[2].predicate) (op1, mode1)) | |
3467 | op1 = copy_to_mode_reg (mode1, op1); | |
3468 | ||
3469 | pat = GEN_FCN (icode) (target, op0, op1); | |
3470 | if (! pat) | |
3471 | return 0; | |
3472 | emit_insn (pat); | |
3473 | ||
3474 | return target; | |
3475 | } | |
2212663f DB |
3476 | static rtx |
3477 | altivec_expand_ternop_builtin (icode, arglist, target) | |
3478 | enum insn_code icode; | |
3479 | tree arglist; | |
3480 | rtx target; | |
3481 | { | |
3482 | rtx pat; | |
3483 | tree arg0 = TREE_VALUE (arglist); | |
3484 | tree arg1 = TREE_VALUE (TREE_CHAIN (arglist)); | |
3485 | tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist))); | |
3486 | rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
3487 | rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); | |
3488 | rtx op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0); | |
3489 | enum machine_mode tmode = insn_data[icode].operand[0].mode; | |
3490 | enum machine_mode mode0 = insn_data[icode].operand[1].mode; | |
3491 | enum machine_mode mode1 = insn_data[icode].operand[2].mode; | |
3492 | enum machine_mode mode2 = insn_data[icode].operand[3].mode; | |
0ac081f6 | 3493 | |
20e26713 AH |
3494 | /* If we got invalid arguments bail out before generating bad rtl. */ |
3495 | if (arg0 == error_mark_node | |
3496 | || arg1 == error_mark_node | |
3497 | || arg2 == error_mark_node) | |
95385cbb | 3498 | return NULL_RTX; |
20e26713 | 3499 | |
c62f2db5 | 3500 | if (target == 0 |
2212663f DB |
3501 | || GET_MODE (target) != tmode |
3502 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
3503 | target = gen_reg_rtx (tmode); | |
3504 | ||
3505 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) | |
3506 | op0 = copy_to_mode_reg (mode0, op0); | |
3507 | if (! (*insn_data[icode].operand[2].predicate) (op1, mode1)) | |
3508 | op1 = copy_to_mode_reg (mode1, op1); | |
3509 | if (! (*insn_data[icode].operand[3].predicate) (op2, mode2)) | |
3510 | op2 = copy_to_mode_reg (mode2, op2); | |
3511 | ||
3512 | pat = GEN_FCN (icode) (target, op0, op1, op2); | |
3513 | if (! pat) | |
3514 | return 0; | |
3515 | emit_insn (pat); | |
3516 | ||
3517 | return target; | |
3518 | } | |
0ac081f6 | 3519 | static rtx |
00b960c7 | 3520 | altivec_expand_builtin (exp, target) |
0ac081f6 AH |
3521 | tree exp; |
3522 | rtx target; | |
0ac081f6 AH |
3523 | { |
3524 | struct builtin_description *d; | |
3525 | size_t i; | |
3526 | enum insn_code icode; | |
3527 | tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0); | |
3528 | tree arglist = TREE_OPERAND (exp, 1); | |
95385cbb AH |
3529 | tree arg0, arg1, arg2; |
3530 | rtx op0, op1, op2, pat; | |
3531 | enum machine_mode tmode, mode0, mode1, mode2; | |
0ac081f6 AH |
3532 | unsigned int fcode = DECL_FUNCTION_CODE (fndecl); |
3533 | ||
3534 | switch (fcode) | |
3535 | { | |
f18c054f DB |
3536 | case ALTIVEC_BUILTIN_LD_INTERNAL_16qi: |
3537 | icode = CODE_FOR_altivec_lvx_16qi; | |
0ac081f6 AH |
3538 | arg0 = TREE_VALUE (arglist); |
3539 | op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
3540 | tmode = insn_data[icode].operand[0].mode; | |
3541 | mode0 = insn_data[icode].operand[1].mode; | |
3542 | ||
c62f2db5 | 3543 | if (target == 0 |
0ac081f6 AH |
3544 | || GET_MODE (target) != tmode |
3545 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
3546 | target = gen_reg_rtx (tmode); | |
3547 | ||
3548 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) | |
3549 | op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0)); | |
3550 | ||
3551 | pat = GEN_FCN (icode) (target, op0); | |
3552 | if (! pat) | |
3553 | return 0; | |
3554 | emit_insn (pat); | |
3555 | return target; | |
24408032 | 3556 | |
f18c054f DB |
3557 | case ALTIVEC_BUILTIN_LD_INTERNAL_8hi: |
3558 | icode = CODE_FOR_altivec_lvx_8hi; | |
3559 | arg0 = TREE_VALUE (arglist); | |
3560 | op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
3561 | tmode = insn_data[icode].operand[0].mode; | |
3562 | mode0 = insn_data[icode].operand[1].mode; | |
0ac081f6 | 3563 | |
c62f2db5 | 3564 | if (target == 0 |
f18c054f DB |
3565 | || GET_MODE (target) != tmode |
3566 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
3567 | target = gen_reg_rtx (tmode); | |
3568 | ||
3569 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) | |
3570 | op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0)); | |
3571 | ||
3572 | pat = GEN_FCN (icode) (target, op0); | |
3573 | if (! pat) | |
3574 | return 0; | |
3575 | emit_insn (pat); | |
3576 | return target; | |
24408032 | 3577 | |
f18c054f DB |
3578 | case ALTIVEC_BUILTIN_LD_INTERNAL_4si: |
3579 | icode = CODE_FOR_altivec_lvx_4si; | |
3580 | arg0 = TREE_VALUE (arglist); | |
3581 | op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
3582 | tmode = insn_data[icode].operand[0].mode; | |
3583 | mode0 = insn_data[icode].operand[1].mode; | |
3584 | ||
c62f2db5 | 3585 | if (target == 0 |
f18c054f DB |
3586 | || GET_MODE (target) != tmode |
3587 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
3588 | target = gen_reg_rtx (tmode); | |
3589 | ||
3590 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) | |
3591 | op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0)); | |
3592 | ||
3593 | pat = GEN_FCN (icode) (target, op0); | |
3594 | if (! pat) | |
3595 | return 0; | |
3596 | emit_insn (pat); | |
3597 | return target; | |
24408032 | 3598 | |
f18c054f DB |
3599 | case ALTIVEC_BUILTIN_LD_INTERNAL_4sf: |
3600 | icode = CODE_FOR_altivec_lvx_4sf; | |
3601 | arg0 = TREE_VALUE (arglist); | |
3602 | op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
3603 | tmode = insn_data[icode].operand[0].mode; | |
3604 | mode0 = insn_data[icode].operand[1].mode; | |
3605 | ||
c62f2db5 | 3606 | if (target == 0 |
f18c054f DB |
3607 | || GET_MODE (target) != tmode |
3608 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
3609 | target = gen_reg_rtx (tmode); | |
3610 | ||
3611 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) | |
3612 | op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0)); | |
3613 | ||
3614 | pat = GEN_FCN (icode) (target, op0); | |
3615 | if (! pat) | |
3616 | return 0; | |
3617 | emit_insn (pat); | |
3618 | return target; | |
3619 | ||
3620 | case ALTIVEC_BUILTIN_ST_INTERNAL_16qi: | |
3621 | icode = CODE_FOR_altivec_stvx_16qi; | |
3622 | arg0 = TREE_VALUE (arglist); | |
3623 | arg1 = TREE_VALUE (TREE_CHAIN (arglist)); | |
3624 | op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
3625 | op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); | |
3626 | mode0 = insn_data[icode].operand[0].mode; | |
3627 | mode1 = insn_data[icode].operand[1].mode; | |
3628 | ||
3629 | if (! (*insn_data[icode].operand[0].predicate) (op0, mode0)) | |
3630 | op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0)); | |
3631 | if (! (*insn_data[icode].operand[1].predicate) (op1, mode1)) | |
3632 | op1 = copy_to_mode_reg (mode1, op1); | |
3633 | ||
3634 | pat = GEN_FCN (icode) (op0, op1); | |
95385cbb AH |
3635 | if (pat) |
3636 | emit_insn (pat); | |
f18c054f | 3637 | return NULL_RTX; |
24408032 | 3638 | |
f18c054f DB |
3639 | case ALTIVEC_BUILTIN_ST_INTERNAL_8hi: |
3640 | icode = CODE_FOR_altivec_stvx_8hi; | |
3641 | arg0 = TREE_VALUE (arglist); | |
3642 | arg1 = TREE_VALUE (TREE_CHAIN (arglist)); | |
3643 | op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
3644 | op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); | |
3645 | mode0 = insn_data[icode].operand[0].mode; | |
3646 | mode1 = insn_data[icode].operand[1].mode; | |
3647 | ||
3648 | if (! (*insn_data[icode].operand[0].predicate) (op0, mode0)) | |
3649 | op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0)); | |
3650 | if (! (*insn_data[icode].operand[1].predicate) (op1, mode1)) | |
3651 | op1 = copy_to_mode_reg (mode1, op1); | |
3652 | ||
3653 | pat = GEN_FCN (icode) (op0, op1); | |
95385cbb AH |
3654 | if (pat) |
3655 | emit_insn (pat); | |
f18c054f | 3656 | return NULL_RTX; |
24408032 | 3657 | |
f18c054f DB |
3658 | case ALTIVEC_BUILTIN_ST_INTERNAL_4si: |
3659 | icode = CODE_FOR_altivec_stvx_4si; | |
3660 | arg0 = TREE_VALUE (arglist); | |
3661 | arg1 = TREE_VALUE (TREE_CHAIN (arglist)); | |
3662 | op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
3663 | op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); | |
3664 | mode0 = insn_data[icode].operand[0].mode; | |
3665 | mode1 = insn_data[icode].operand[1].mode; | |
3666 | ||
3667 | if (! (*insn_data[icode].operand[0].predicate) (op0, mode0)) | |
3668 | op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0)); | |
3669 | if (! (*insn_data[icode].operand[1].predicate) (op1, mode1)) | |
3670 | op1 = copy_to_mode_reg (mode1, op1); | |
3671 | ||
3672 | pat = GEN_FCN (icode) (op0, op1); | |
95385cbb AH |
3673 | if (pat) |
3674 | emit_insn (pat); | |
f18c054f | 3675 | return NULL_RTX; |
24408032 | 3676 | |
f18c054f DB |
3677 | case ALTIVEC_BUILTIN_ST_INTERNAL_4sf: |
3678 | icode = CODE_FOR_altivec_stvx_4sf; | |
0ac081f6 AH |
3679 | arg0 = TREE_VALUE (arglist); |
3680 | arg1 = TREE_VALUE (TREE_CHAIN (arglist)); | |
3681 | op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
3682 | op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); | |
3683 | mode0 = insn_data[icode].operand[0].mode; | |
3684 | mode1 = insn_data[icode].operand[1].mode; | |
3685 | ||
3686 | if (! (*insn_data[icode].operand[0].predicate) (op0, mode0)) | |
3687 | op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0)); | |
3688 | if (! (*insn_data[icode].operand[1].predicate) (op1, mode1)) | |
3689 | op1 = copy_to_mode_reg (mode1, op1); | |
3690 | ||
3691 | pat = GEN_FCN (icode) (op0, op1); | |
95385cbb AH |
3692 | if (pat) |
3693 | emit_insn (pat); | |
3694 | return NULL_RTX; | |
3695 | ||
3696 | case ALTIVEC_BUILTIN_MFVSCR: | |
3697 | icode = CODE_FOR_altivec_mfvscr; | |
3698 | tmode = insn_data[icode].operand[0].mode; | |
3699 | ||
3700 | if (target == 0 | |
3701 | || GET_MODE (target) != tmode | |
3702 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
3703 | target = gen_reg_rtx (tmode); | |
3704 | ||
3705 | pat = GEN_FCN (icode) (target); | |
0ac081f6 AH |
3706 | if (! pat) |
3707 | return 0; | |
3708 | emit_insn (pat); | |
95385cbb AH |
3709 | return target; |
3710 | ||
3711 | case ALTIVEC_BUILTIN_MTVSCR: | |
3712 | icode = CODE_FOR_altivec_mtvscr; | |
3713 | arg0 = TREE_VALUE (arglist); | |
3714 | op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
3715 | mode0 = insn_data[icode].operand[0].mode; | |
3716 | ||
3717 | /* If we got invalid arguments bail out before generating bad rtl. */ | |
3718 | if (arg0 == error_mark_node) | |
3719 | return NULL_RTX; | |
3720 | ||
3721 | if (! (*insn_data[icode].operand[0].predicate) (op0, mode0)) | |
3722 | op0 = copy_to_mode_reg (mode0, op0); | |
3723 | ||
3724 | pat = GEN_FCN (icode) (op0); | |
3725 | if (pat) | |
3726 | emit_insn (pat); | |
3727 | return NULL_RTX; | |
3728 | ||
3729 | case ALTIVEC_BUILTIN_DSSALL: | |
3730 | emit_insn (gen_altivec_dssall ()); | |
3731 | return NULL_RTX; | |
3732 | ||
3733 | case ALTIVEC_BUILTIN_DSS: | |
3734 | icode = CODE_FOR_altivec_dss; | |
3735 | arg0 = TREE_VALUE (arglist); | |
3736 | op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
3737 | mode0 = insn_data[icode].operand[0].mode; | |
3738 | ||
3739 | /* If we got invalid arguments bail out before generating bad rtl. */ | |
3740 | if (arg0 == error_mark_node) | |
3741 | return NULL_RTX; | |
3742 | ||
3743 | if (! (*insn_data[icode].operand[0].predicate) (op0, mode0)) | |
3744 | op0 = copy_to_mode_reg (mode0, op0); | |
3745 | ||
3746 | emit_insn (gen_altivec_dss (op0)); | |
0ac081f6 AH |
3747 | return NULL_RTX; |
3748 | } | |
24408032 | 3749 | |
95385cbb AH |
3750 | /* Handle DST variants. */ |
3751 | d = (struct builtin_description *) bdesc_dst; | |
3752 | for (i = 0; i < sizeof (bdesc_dst) / sizeof *d; i++, d++) | |
3753 | if (d->code == fcode) | |
3754 | { | |
3755 | arg0 = TREE_VALUE (arglist); | |
3756 | arg1 = TREE_VALUE (TREE_CHAIN (arglist)); | |
3757 | arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist))); | |
3758 | op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
3759 | op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); | |
3760 | op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0); | |
3761 | mode0 = insn_data[d->icode].operand[0].mode; | |
3762 | mode1 = insn_data[d->icode].operand[1].mode; | |
3763 | mode2 = insn_data[d->icode].operand[2].mode; | |
3764 | ||
3765 | /* Invalid arguments, bail out before generating bad rtl. */ | |
3766 | if (arg0 == error_mark_node | |
3767 | || arg1 == error_mark_node | |
3768 | || arg2 == error_mark_node) | |
3769 | return NULL_RTX; | |
3770 | ||
3771 | if (! (*insn_data[d->icode].operand[0].predicate) (op0, mode0)) | |
3772 | op0 = copy_to_mode_reg (mode0, op0); | |
3773 | if (! (*insn_data[d->icode].operand[1].predicate) (op1, mode1)) | |
3774 | op1 = copy_to_mode_reg (mode1, op1); | |
3775 | ||
3776 | if (GET_CODE (op2) != CONST_INT || INTVAL (op2) > 3) | |
3777 | { | |
3778 | error ("argument 3 of `%s' must be a 2-bit literal", d->name); | |
3779 | return NULL_RTX; | |
3780 | } | |
3781 | ||
3782 | pat = GEN_FCN (d->icode) (op0, op1, op2); | |
3783 | if (pat != 0) | |
3784 | emit_insn (pat); | |
3785 | ||
3786 | return NULL_RTX; | |
3787 | } | |
3788 | ||
2212663f DB |
3789 | /* Handle simple unary operations. */ |
3790 | d = (struct builtin_description *) bdesc_1arg; | |
3791 | for (i = 0; i < sizeof (bdesc_1arg) / sizeof *d; i++, d++) | |
3792 | if (d->code == fcode) | |
3793 | return altivec_expand_unop_builtin (d->icode, arglist, target); | |
0ac081f6 AH |
3794 | |
3795 | /* Handle simple binary operations. */ | |
00b960c7 AH |
3796 | d = (struct builtin_description *) bdesc_2arg; |
3797 | for (i = 0; i < sizeof (bdesc_2arg) / sizeof *d; i++, d++) | |
0ac081f6 AH |
3798 | if (d->code == fcode) |
3799 | return altivec_expand_binop_builtin (d->icode, arglist, target); | |
3800 | ||
95385cbb AH |
3801 | /* LVS* are funky. We initialized them differently. */ |
3802 | if (fcode == ALTIVEC_BUILTIN_LVSL) | |
3803 | return altivec_expand_binop_builtin (CODE_FOR_altivec_lvsl, | |
3804 | arglist, target); | |
3805 | if (fcode == ALTIVEC_BUILTIN_LVSR) | |
3806 | return altivec_expand_binop_builtin (CODE_FOR_altivec_lvsr, | |
3807 | arglist, target); | |
3808 | ||
2212663f DB |
3809 | /* Handle simple ternary operations. */ |
3810 | d = (struct builtin_description *) bdesc_3arg; | |
3811 | for (i = 0; i < sizeof (bdesc_3arg) / sizeof *d; i++, d++) | |
3812 | if (d->code == fcode) | |
3813 | return altivec_expand_ternop_builtin (d->icode, arglist, target); | |
3814 | ||
0ac081f6 AH |
3815 | abort (); |
3816 | return NULL_RTX; | |
3817 | } | |
3818 | ||
3819 | /* Expand an expression EXP that calls a built-in function, | |
3820 | with result going to TARGET if that's convenient | |
3821 | (and in mode MODE if that's convenient). | |
3822 | SUBTARGET may be used as the target for computing one of EXP's operands. | |
3823 | IGNORE is nonzero if the value is to be ignored. */ | |
3824 | ||
3825 | static rtx | |
3826 | rs6000_expand_builtin (exp, target, subtarget, mode, ignore) | |
3827 | tree exp; | |
3828 | rtx target; | |
00b960c7 AH |
3829 | rtx subtarget ATTRIBUTE_UNUSED; |
3830 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
3831 | int ignore ATTRIBUTE_UNUSED; | |
0ac081f6 AH |
3832 | { |
3833 | if (TARGET_ALTIVEC) | |
00b960c7 | 3834 | return altivec_expand_builtin (exp, target); |
0ac081f6 AH |
3835 | |
3836 | abort (); | |
3837 | } | |
3838 | ||
3839 | static void | |
6fa3f289 | 3840 | rs6000_init_builtins () |
0ac081f6 AH |
3841 | { |
3842 | if (TARGET_ALTIVEC) | |
3843 | altivec_init_builtins (); | |
3844 | } | |
3845 | ||
3846 | static void | |
3847 | altivec_init_builtins (void) | |
3848 | { | |
3849 | struct builtin_description * d; | |
3850 | size_t i; | |
3851 | ||
3852 | tree endlink = void_list_node; | |
3853 | ||
3854 | tree pint_type_node = build_pointer_type (integer_type_node); | |
95385cbb | 3855 | tree pvoid_type_node = build_pointer_type (void_type_node); |
f18c054f DB |
3856 | tree pshort_type_node = build_pointer_type (short_integer_type_node); |
3857 | tree pchar_type_node = build_pointer_type (char_type_node); | |
3858 | tree pfloat_type_node = build_pointer_type (float_type_node); | |
20e26713 | 3859 | |
2212663f DB |
3860 | tree v4sf_ftype_v4sf_v4sf_v16qi |
3861 | = build_function_type (V4SF_type_node, | |
3862 | tree_cons (NULL_TREE, V4SF_type_node, | |
3863 | tree_cons (NULL_TREE, V4SF_type_node, | |
3864 | tree_cons (NULL_TREE, | |
3865 | V16QI_type_node, | |
3866 | endlink)))); | |
3867 | tree v4si_ftype_v4si_v4si_v16qi | |
3868 | = build_function_type (V4SI_type_node, | |
3869 | tree_cons (NULL_TREE, V4SI_type_node, | |
3870 | tree_cons (NULL_TREE, V4SI_type_node, | |
3871 | tree_cons (NULL_TREE, | |
3872 | V16QI_type_node, | |
3873 | endlink)))); | |
3874 | tree v8hi_ftype_v8hi_v8hi_v16qi | |
3875 | = build_function_type (V8HI_type_node, | |
3876 | tree_cons (NULL_TREE, V8HI_type_node, | |
3877 | tree_cons (NULL_TREE, V8HI_type_node, | |
3878 | tree_cons (NULL_TREE, | |
3879 | V16QI_type_node, | |
3880 | endlink)))); | |
3881 | tree v16qi_ftype_v16qi_v16qi_v16qi | |
3882 | = build_function_type (V16QI_type_node, | |
3883 | tree_cons (NULL_TREE, V16QI_type_node, | |
3884 | tree_cons (NULL_TREE, V16QI_type_node, | |
3885 | tree_cons (NULL_TREE, | |
3886 | V16QI_type_node, | |
3887 | endlink)))); | |
3888 | ||
24408032 | 3889 | /* V4SI foo (char). */ |
2212663f DB |
3890 | tree v4si_ftype_char |
3891 | = build_function_type (V4SI_type_node, | |
3892 | tree_cons (NULL_TREE, char_type_node, endlink)); | |
3893 | ||
24408032 | 3894 | /* V8HI foo (char). */ |
2212663f DB |
3895 | tree v8hi_ftype_char |
3896 | = build_function_type (V8HI_type_node, | |
3897 | tree_cons (NULL_TREE, char_type_node, endlink)); | |
3898 | ||
24408032 | 3899 | /* V16QI foo (char). */ |
2212663f DB |
3900 | tree v16qi_ftype_char |
3901 | = build_function_type (V16QI_type_node, | |
3902 | tree_cons (NULL_TREE, char_type_node, endlink)); | |
24408032 | 3903 | /* V4SF foo (V4SF). */ |
617e0e1d DB |
3904 | tree v4sf_ftype_v4sf |
3905 | = build_function_type (V4SF_type_node, | |
3906 | tree_cons (NULL_TREE, V4SF_type_node, endlink)); | |
0ac081f6 AH |
3907 | |
3908 | /* V4SI foo (int *). */ | |
3909 | tree v4si_ftype_pint | |
3910 | = build_function_type (V4SI_type_node, | |
3911 | tree_cons (NULL_TREE, pint_type_node, endlink)); | |
f18c054f DB |
3912 | /* V8HI foo (short *). */ |
3913 | tree v8hi_ftype_pshort | |
3914 | = build_function_type (V8HI_type_node, | |
3915 | tree_cons (NULL_TREE, pshort_type_node, endlink)); | |
3916 | /* V16QI foo (char *). */ | |
3917 | tree v16qi_ftype_pchar | |
3918 | = build_function_type (V16QI_type_node, | |
3919 | tree_cons (NULL_TREE, pchar_type_node, endlink)); | |
3920 | /* V4SF foo (float *). */ | |
3921 | tree v4sf_ftype_pfloat | |
3922 | = build_function_type (V4SF_type_node, | |
3923 | tree_cons (NULL_TREE, pfloat_type_node, endlink)); | |
0ac081f6 | 3924 | |
20e26713 AH |
3925 | /* V8HI foo (V16QI). */ |
3926 | tree v8hi_ftype_v16qi | |
3927 | = build_function_type (V8HI_type_node, | |
3928 | tree_cons (NULL_TREE, V16QI_type_node, endlink)); | |
3929 | ||
95385cbb AH |
3930 | /* void foo (void *, int, char/literal). */ |
3931 | tree void_ftype_pvoid_int_char | |
3932 | = build_function_type (void_type_node, | |
3933 | tree_cons (NULL_TREE, pvoid_type_node, | |
3934 | tree_cons (NULL_TREE, integer_type_node, | |
3935 | tree_cons (NULL_TREE, | |
3936 | char_type_node, | |
3937 | endlink)))); | |
3938 | ||
0ac081f6 AH |
3939 | /* void foo (int *, V4SI). */ |
3940 | tree void_ftype_pint_v4si | |
3941 | = build_function_type (void_type_node, | |
3942 | tree_cons (NULL_TREE, pint_type_node, | |
3943 | tree_cons (NULL_TREE, V4SI_type_node, | |
3944 | endlink))); | |
f18c054f DB |
3945 | /* void foo (short *, V8HI). */ |
3946 | tree void_ftype_pshort_v8hi | |
3947 | = build_function_type (void_type_node, | |
3948 | tree_cons (NULL_TREE, pshort_type_node, | |
3949 | tree_cons (NULL_TREE, V8HI_type_node, | |
3950 | endlink))); | |
3951 | /* void foo (char *, V16QI). */ | |
3952 | tree void_ftype_pchar_v16qi | |
3953 | = build_function_type (void_type_node, | |
3954 | tree_cons (NULL_TREE, pchar_type_node, | |
3955 | tree_cons (NULL_TREE, V16QI_type_node, | |
3956 | endlink))); | |
3957 | /* void foo (float *, V4SF). */ | |
3958 | tree void_ftype_pfloat_v4sf | |
3959 | = build_function_type (void_type_node, | |
3960 | tree_cons (NULL_TREE, pfloat_type_node, | |
3961 | tree_cons (NULL_TREE, V4SF_type_node, | |
3962 | endlink))); | |
0ac081f6 | 3963 | |
95385cbb AH |
3964 | /* void foo (V4SI). */ |
3965 | tree void_ftype_v4si | |
3966 | = build_function_type (void_type_node, | |
3967 | tree_cons (NULL_TREE, V4SI_type_node, | |
3968 | endlink)); | |
3969 | ||
3970 | /* void foo (char). */ | |
3971 | tree void_ftype_qi | |
3972 | = build_function_type (void_type_node, | |
3973 | tree_cons (NULL_TREE, char_type_node, | |
3974 | endlink)); | |
3975 | ||
3976 | /* void foo (void). */ | |
3977 | tree void_ftype_void | |
3978 | = build_function_type (void_type_node, | |
3979 | tree_cons (NULL_TREE, void_type_node, | |
3980 | endlink)); | |
3981 | ||
3982 | /* vshort foo (void). */ | |
3983 | tree v8hi_ftype_void | |
3984 | = build_function_type (V8HI_type_node, | |
3985 | tree_cons (NULL_TREE, void_type_node, | |
3986 | endlink)); | |
3987 | ||
0ac081f6 AH |
3988 | tree v4si_ftype_v4si_v4si |
3989 | = build_function_type (V4SI_type_node, | |
3990 | tree_cons (NULL_TREE, V4SI_type_node, | |
3991 | tree_cons (NULL_TREE, V4SI_type_node, | |
3992 | endlink))); | |
24408032 AH |
3993 | |
3994 | /* These are for the unsigned 5 bit literals. */ | |
3995 | ||
617e0e1d DB |
3996 | tree v4sf_ftype_v4si_char |
3997 | = build_function_type (V4SF_type_node, | |
3998 | tree_cons (NULL_TREE, V4SI_type_node, | |
3999 | tree_cons (NULL_TREE, char_type_node, | |
4000 | endlink))); | |
4001 | tree v4si_ftype_v4sf_char | |
4002 | = build_function_type (V4SI_type_node, | |
4003 | tree_cons (NULL_TREE, V4SF_type_node, | |
4004 | tree_cons (NULL_TREE, char_type_node, | |
4005 | endlink))); | |
2212663f DB |
4006 | tree v4si_ftype_v4si_char |
4007 | = build_function_type (V4SI_type_node, | |
4008 | tree_cons (NULL_TREE, V4SI_type_node, | |
4009 | tree_cons (NULL_TREE, char_type_node, | |
4010 | endlink))); | |
4011 | tree v8hi_ftype_v8hi_char | |
4012 | = build_function_type (V8HI_type_node, | |
4013 | tree_cons (NULL_TREE, V8HI_type_node, | |
4014 | tree_cons (NULL_TREE, char_type_node, | |
4015 | endlink))); | |
4016 | tree v16qi_ftype_v16qi_char | |
4017 | = build_function_type (V16QI_type_node, | |
4018 | tree_cons (NULL_TREE, V16QI_type_node, | |
4019 | tree_cons (NULL_TREE, char_type_node, | |
4020 | endlink))); | |
0ac081f6 | 4021 | |
24408032 AH |
4022 | /* These are for the unsigned 4 bit literals. */ |
4023 | ||
4024 | tree v16qi_ftype_v16qi_v16qi_char | |
4025 | = build_function_type (V16QI_type_node, | |
4026 | tree_cons (NULL_TREE, V16QI_type_node, | |
4027 | tree_cons (NULL_TREE, V16QI_type_node, | |
4028 | tree_cons (NULL_TREE, | |
4029 | char_type_node, | |
4030 | endlink)))); | |
4031 | ||
4032 | tree v8hi_ftype_v8hi_v8hi_char | |
4033 | = build_function_type (V8HI_type_node, | |
4034 | tree_cons (NULL_TREE, V8HI_type_node, | |
4035 | tree_cons (NULL_TREE, V8HI_type_node, | |
4036 | tree_cons (NULL_TREE, | |
4037 | char_type_node, | |
4038 | endlink)))); | |
4039 | ||
4040 | tree v4si_ftype_v4si_v4si_char | |
4041 | = build_function_type (V4SI_type_node, | |
4042 | tree_cons (NULL_TREE, V4SI_type_node, | |
4043 | tree_cons (NULL_TREE, V4SI_type_node, | |
4044 | tree_cons (NULL_TREE, | |
4045 | char_type_node, | |
4046 | endlink)))); | |
4047 | ||
4048 | tree v4sf_ftype_v4sf_v4sf_char | |
4049 | = build_function_type (V4SF_type_node, | |
4050 | tree_cons (NULL_TREE, V4SF_type_node, | |
4051 | tree_cons (NULL_TREE, V4SF_type_node, | |
4052 | tree_cons (NULL_TREE, | |
4053 | char_type_node, | |
4054 | endlink)))); | |
4055 | ||
4056 | /* End of 4 bit literals. */ | |
4057 | ||
0ac081f6 AH |
4058 | tree v4sf_ftype_v4sf_v4sf |
4059 | = build_function_type (V4SF_type_node, | |
4060 | tree_cons (NULL_TREE, V4SF_type_node, | |
4061 | tree_cons (NULL_TREE, V4SF_type_node, | |
4062 | endlink))); | |
617e0e1d DB |
4063 | tree v4sf_ftype_v4sf_v4sf_v4si |
4064 | = build_function_type (V4SF_type_node, | |
4065 | tree_cons (NULL_TREE, V4SF_type_node, | |
4066 | tree_cons (NULL_TREE, V4SF_type_node, | |
4067 | tree_cons (NULL_TREE, | |
4068 | V4SI_type_node, | |
4069 | endlink)))); | |
2212663f DB |
4070 | tree v4sf_ftype_v4sf_v4sf_v4sf |
4071 | = build_function_type (V4SF_type_node, | |
4072 | tree_cons (NULL_TREE, V4SF_type_node, | |
4073 | tree_cons (NULL_TREE, V4SF_type_node, | |
4074 | tree_cons (NULL_TREE, | |
4075 | V4SF_type_node, | |
4076 | endlink)))); | |
617e0e1d DB |
4077 | tree v4si_ftype_v4si_v4si_v4si |
4078 | = build_function_type (V4SI_type_node, | |
4079 | tree_cons (NULL_TREE, V4SI_type_node, | |
4080 | tree_cons (NULL_TREE, V4SI_type_node, | |
4081 | tree_cons (NULL_TREE, | |
4082 | V4SI_type_node, | |
4083 | endlink)))); | |
2212663f | 4084 | |
0ac081f6 AH |
4085 | tree v8hi_ftype_v8hi_v8hi |
4086 | = build_function_type (V8HI_type_node, | |
4087 | tree_cons (NULL_TREE, V8HI_type_node, | |
4088 | tree_cons (NULL_TREE, V8HI_type_node, | |
4089 | endlink))); | |
2212663f DB |
4090 | tree v8hi_ftype_v8hi_v8hi_v8hi |
4091 | = build_function_type (V8HI_type_node, | |
4092 | tree_cons (NULL_TREE, V8HI_type_node, | |
4093 | tree_cons (NULL_TREE, V8HI_type_node, | |
4094 | tree_cons (NULL_TREE, | |
4095 | V8HI_type_node, | |
4096 | endlink)))); | |
4097 | tree v4si_ftype_v8hi_v8hi_v4si | |
4098 | = build_function_type (V4SI_type_node, | |
4099 | tree_cons (NULL_TREE, V8HI_type_node, | |
4100 | tree_cons (NULL_TREE, V8HI_type_node, | |
4101 | tree_cons (NULL_TREE, | |
4102 | V4SI_type_node, | |
4103 | endlink)))); | |
4104 | tree v4si_ftype_v16qi_v16qi_v4si | |
4105 | = build_function_type (V4SI_type_node, | |
4106 | tree_cons (NULL_TREE, V16QI_type_node, | |
4107 | tree_cons (NULL_TREE, V16QI_type_node, | |
4108 | tree_cons (NULL_TREE, | |
4109 | V4SI_type_node, | |
4110 | endlink)))); | |
4111 | ||
0ac081f6 AH |
4112 | tree v16qi_ftype_v16qi_v16qi |
4113 | = build_function_type (V16QI_type_node, | |
4114 | tree_cons (NULL_TREE, V16QI_type_node, | |
4115 | tree_cons (NULL_TREE, V16QI_type_node, | |
4116 | endlink))); | |
2212663f | 4117 | |
0ac081f6 AH |
4118 | tree v4si_ftype_v4sf_v4sf |
4119 | = build_function_type (V4SI_type_node, | |
4120 | tree_cons (NULL_TREE, V4SF_type_node, | |
4121 | tree_cons (NULL_TREE, V4SF_type_node, | |
4122 | endlink))); | |
4123 | ||
4124 | tree v8hi_ftype_v16qi_v16qi | |
4125 | = build_function_type (V8HI_type_node, | |
4126 | tree_cons (NULL_TREE, V16QI_type_node, | |
4127 | tree_cons (NULL_TREE, V16QI_type_node, | |
4128 | endlink))); | |
4129 | ||
4130 | tree v4si_ftype_v8hi_v8hi | |
4131 | = build_function_type (V4SI_type_node, | |
4132 | tree_cons (NULL_TREE, V8HI_type_node, | |
4133 | tree_cons (NULL_TREE, V8HI_type_node, | |
4134 | endlink))); | |
4135 | ||
4136 | tree v8hi_ftype_v4si_v4si | |
4137 | = build_function_type (V8HI_type_node, | |
4138 | tree_cons (NULL_TREE, V4SI_type_node, | |
4139 | tree_cons (NULL_TREE, V4SI_type_node, | |
4140 | endlink))); | |
4141 | ||
4142 | tree v16qi_ftype_v8hi_v8hi | |
4143 | = build_function_type (V16QI_type_node, | |
4144 | tree_cons (NULL_TREE, V8HI_type_node, | |
4145 | tree_cons (NULL_TREE, V8HI_type_node, | |
4146 | endlink))); | |
4147 | ||
4148 | tree v4si_ftype_v16qi_v4si | |
4149 | = build_function_type (V4SI_type_node, | |
4150 | tree_cons (NULL_TREE, V16QI_type_node, | |
4151 | tree_cons (NULL_TREE, V4SI_type_node, | |
4152 | endlink))); | |
4153 | ||
fa066a23 AH |
4154 | tree v4si_ftype_v16qi_v16qi |
4155 | = build_function_type (V4SI_type_node, | |
4156 | tree_cons (NULL_TREE, V16QI_type_node, | |
4157 | tree_cons (NULL_TREE, V16QI_type_node, | |
4158 | endlink))); | |
4159 | ||
0ac081f6 AH |
4160 | tree v4si_ftype_v8hi_v4si |
4161 | = build_function_type (V4SI_type_node, | |
4162 | tree_cons (NULL_TREE, V8HI_type_node, | |
4163 | tree_cons (NULL_TREE, V4SI_type_node, | |
4164 | endlink))); | |
4165 | ||
20e26713 AH |
4166 | tree v4si_ftype_v8hi |
4167 | = build_function_type (V4SI_type_node, | |
4168 | tree_cons (NULL_TREE, V8HI_type_node, endlink)); | |
4169 | ||
0ac081f6 AH |
4170 | tree int_ftype_v4si_v4si |
4171 | = build_function_type (integer_type_node, | |
4172 | tree_cons (NULL_TREE, V4SI_type_node, | |
4173 | tree_cons (NULL_TREE, V4SI_type_node, | |
4174 | endlink))); | |
4175 | ||
4176 | tree int_ftype_v4sf_v4sf | |
4177 | = build_function_type (integer_type_node, | |
4178 | tree_cons (NULL_TREE, V4SF_type_node, | |
4179 | tree_cons (NULL_TREE, V4SF_type_node, | |
4180 | endlink))); | |
4181 | ||
4182 | tree int_ftype_v16qi_v16qi | |
4183 | = build_function_type (integer_type_node, | |
4184 | tree_cons (NULL_TREE, V16QI_type_node, | |
4185 | tree_cons (NULL_TREE, V16QI_type_node, | |
4186 | endlink))); | |
4187 | ||
95385cbb AH |
4188 | tree v16qi_ftype_int_pvoid |
4189 | = build_function_type (V16QI_type_node, | |
4190 | tree_cons (NULL_TREE, integer_type_node, | |
4191 | tree_cons (NULL_TREE, pvoid_type_node, | |
4192 | endlink))); | |
4193 | ||
0ac081f6 AH |
4194 | tree int_ftype_v8hi_v8hi |
4195 | = build_function_type (integer_type_node, | |
4196 | tree_cons (NULL_TREE, V8HI_type_node, | |
4197 | tree_cons (NULL_TREE, V8HI_type_node, | |
4198 | endlink))); | |
4199 | ||
f18c054f DB |
4200 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_4sf", v4sf_ftype_pfloat, ALTIVEC_BUILTIN_LD_INTERNAL_4sf); |
4201 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_4sf", void_ftype_pfloat_v4sf, ALTIVEC_BUILTIN_ST_INTERNAL_4sf); | |
4202 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_4si", v4si_ftype_pint, ALTIVEC_BUILTIN_LD_INTERNAL_4si); | |
4203 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_4si", void_ftype_pint_v4si, ALTIVEC_BUILTIN_ST_INTERNAL_4si); | |
4204 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_8hi", v8hi_ftype_pshort, ALTIVEC_BUILTIN_LD_INTERNAL_8hi); | |
4205 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_8hi", void_ftype_pshort_v8hi, ALTIVEC_BUILTIN_ST_INTERNAL_8hi); | |
4206 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_16qi", v16qi_ftype_pchar, ALTIVEC_BUILTIN_LD_INTERNAL_16qi); | |
4207 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_16qi", void_ftype_pchar_v16qi, ALTIVEC_BUILTIN_ST_INTERNAL_16qi); | |
95385cbb AH |
4208 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_mtvscr", void_ftype_v4si, ALTIVEC_BUILTIN_MTVSCR); |
4209 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_mfvscr", v8hi_ftype_void, ALTIVEC_BUILTIN_MFVSCR); | |
4210 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_dssall", void_ftype_void, ALTIVEC_BUILTIN_DSSALL); | |
4211 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_dss", void_ftype_qi, ALTIVEC_BUILTIN_DSS); | |
4212 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvsl", v16qi_ftype_int_pvoid, ALTIVEC_BUILTIN_LVSL); | |
4213 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvsr", v16qi_ftype_int_pvoid, ALTIVEC_BUILTIN_LVSR); | |
0ac081f6 | 4214 | |
6f317ef3 | 4215 | /* Add the simple ternary operators. */ |
2212663f DB |
4216 | d = (struct builtin_description *) bdesc_3arg; |
4217 | for (i = 0; i < sizeof (bdesc_3arg) / sizeof *d; i++, d++) | |
4218 | { | |
4219 | ||
4220 | enum machine_mode mode0, mode1, mode2, mode3; | |
4221 | tree type; | |
4222 | ||
4223 | if (d->name == 0) | |
4224 | continue; | |
4225 | ||
4226 | mode0 = insn_data[d->icode].operand[0].mode; | |
4227 | mode1 = insn_data[d->icode].operand[1].mode; | |
4228 | mode2 = insn_data[d->icode].operand[2].mode; | |
4229 | mode3 = insn_data[d->icode].operand[3].mode; | |
4230 | ||
4231 | /* When all four are of the same mode. */ | |
4232 | if (mode0 == mode1 && mode1 == mode2 && mode2 == mode3) | |
4233 | { | |
4234 | switch (mode0) | |
4235 | { | |
617e0e1d DB |
4236 | case V4SImode: |
4237 | type = v4si_ftype_v4si_v4si_v4si; | |
4238 | break; | |
2212663f DB |
4239 | case V4SFmode: |
4240 | type = v4sf_ftype_v4sf_v4sf_v4sf; | |
4241 | break; | |
4242 | case V8HImode: | |
4243 | type = v8hi_ftype_v8hi_v8hi_v8hi; | |
4244 | break; | |
4245 | case V16QImode: | |
4246 | type = v16qi_ftype_v16qi_v16qi_v16qi; | |
4247 | break; | |
4248 | default: | |
4249 | abort(); | |
4250 | } | |
4251 | } | |
4252 | else if (mode0 == mode1 && mode1 == mode2 && mode3 == V16QImode) | |
4253 | { | |
4254 | switch (mode0) | |
4255 | { | |
4256 | case V4SImode: | |
4257 | type = v4si_ftype_v4si_v4si_v16qi; | |
4258 | break; | |
4259 | case V4SFmode: | |
4260 | type = v4sf_ftype_v4sf_v4sf_v16qi; | |
4261 | break; | |
4262 | case V8HImode: | |
4263 | type = v8hi_ftype_v8hi_v8hi_v16qi; | |
4264 | break; | |
4265 | case V16QImode: | |
4266 | type = v16qi_ftype_v16qi_v16qi_v16qi; | |
4267 | break; | |
4268 | default: | |
4269 | abort(); | |
4270 | } | |
4271 | } | |
4272 | else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V16QImode | |
4273 | && mode3 == V4SImode) | |
24408032 | 4274 | type = v4si_ftype_v16qi_v16qi_v4si; |
2212663f DB |
4275 | else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V8HImode |
4276 | && mode3 == V4SImode) | |
24408032 | 4277 | type = v4si_ftype_v8hi_v8hi_v4si; |
617e0e1d DB |
4278 | else if (mode0 == V4SFmode && mode1 == V4SFmode && mode2 == V4SFmode |
4279 | && mode3 == V4SImode) | |
24408032 AH |
4280 | type = v4sf_ftype_v4sf_v4sf_v4si; |
4281 | ||
4282 | /* vchar, vchar, vchar, 4 bit literal. */ | |
4283 | else if (mode0 == V16QImode && mode1 == mode0 && mode2 == mode0 | |
4284 | && mode3 == QImode) | |
4285 | type = v16qi_ftype_v16qi_v16qi_char; | |
4286 | ||
4287 | /* vshort, vshort, vshort, 4 bit literal. */ | |
4288 | else if (mode0 == V8HImode && mode1 == mode0 && mode2 == mode0 | |
4289 | && mode3 == QImode) | |
4290 | type = v8hi_ftype_v8hi_v8hi_char; | |
4291 | ||
4292 | /* vint, vint, vint, 4 bit literal. */ | |
4293 | else if (mode0 == V4SImode && mode1 == mode0 && mode2 == mode0 | |
4294 | && mode3 == QImode) | |
4295 | type = v4si_ftype_v4si_v4si_char; | |
4296 | ||
4297 | /* vfloat, vfloat, vfloat, 4 bit literal. */ | |
4298 | else if (mode0 == V4SFmode && mode1 == mode0 && mode2 == mode0 | |
4299 | && mode3 == QImode) | |
4300 | type = v4sf_ftype_v4sf_v4sf_char; | |
4301 | ||
2212663f DB |
4302 | else |
4303 | abort (); | |
4304 | ||
4305 | def_builtin (d->mask, d->name, type, d->code); | |
4306 | } | |
4307 | ||
95385cbb AH |
4308 | /* Add the DST variants. */ |
4309 | d = (struct builtin_description *) bdesc_dst; | |
4310 | for (i = 0; i < sizeof (bdesc_dst) / sizeof *d; i++, d++) | |
4311 | def_builtin (d->mask, d->name, void_ftype_pvoid_int_char, d->code); | |
4312 | ||
0ac081f6 | 4313 | /* Add the simple binary operators. */ |
00b960c7 AH |
4314 | d = (struct builtin_description *) bdesc_2arg; |
4315 | for (i = 0; i < sizeof (bdesc_2arg) / sizeof *d; i++, d++) | |
0ac081f6 AH |
4316 | { |
4317 | enum machine_mode mode0, mode1, mode2; | |
4318 | tree type; | |
4319 | ||
4320 | if (d->name == 0) | |
4321 | continue; | |
4322 | ||
4323 | mode0 = insn_data[d->icode].operand[0].mode; | |
4324 | mode1 = insn_data[d->icode].operand[1].mode; | |
4325 | mode2 = insn_data[d->icode].operand[2].mode; | |
4326 | ||
4327 | /* When all three operands are of the same mode. */ | |
4328 | if (mode0 == mode1 && mode1 == mode2) | |
4329 | { | |
4330 | switch (mode0) | |
4331 | { | |
4332 | case V4SFmode: | |
4333 | type = v4sf_ftype_v4sf_v4sf; | |
4334 | break; | |
4335 | case V4SImode: | |
4336 | type = v4si_ftype_v4si_v4si; | |
4337 | break; | |
4338 | case V16QImode: | |
4339 | type = v16qi_ftype_v16qi_v16qi; | |
4340 | break; | |
4341 | case V8HImode: | |
4342 | type = v8hi_ftype_v8hi_v8hi; | |
4343 | break; | |
4344 | default: | |
4345 | abort (); | |
4346 | } | |
4347 | } | |
4348 | ||
4349 | /* A few other combos we really don't want to do manually. */ | |
4350 | ||
4351 | /* vint, vfloat, vfloat. */ | |
4352 | else if (mode0 == V4SImode && mode1 == V4SFmode && mode2 == V4SFmode) | |
4353 | type = v4si_ftype_v4sf_v4sf; | |
4354 | ||
4355 | /* vshort, vchar, vchar. */ | |
4356 | else if (mode0 == V8HImode && mode1 == V16QImode && mode2 == V16QImode) | |
4357 | type = v8hi_ftype_v16qi_v16qi; | |
4358 | ||
4359 | /* vint, vshort, vshort. */ | |
4360 | else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V8HImode) | |
4361 | type = v4si_ftype_v8hi_v8hi; | |
4362 | ||
4363 | /* vshort, vint, vint. */ | |
4364 | else if (mode0 == V8HImode && mode1 == V4SImode && mode2 == V4SImode) | |
4365 | type = v8hi_ftype_v4si_v4si; | |
4366 | ||
4367 | /* vchar, vshort, vshort. */ | |
4368 | else if (mode0 == V16QImode && mode1 == V8HImode && mode2 == V8HImode) | |
4369 | type = v16qi_ftype_v8hi_v8hi; | |
4370 | ||
4371 | /* vint, vchar, vint. */ | |
4372 | else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V4SImode) | |
4373 | type = v4si_ftype_v16qi_v4si; | |
4374 | ||
fa066a23 AH |
4375 | /* vint, vchar, vchar. */ |
4376 | else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V16QImode) | |
4377 | type = v4si_ftype_v16qi_v16qi; | |
4378 | ||
0ac081f6 AH |
4379 | /* vint, vshort, vint. */ |
4380 | else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V4SImode) | |
4381 | type = v4si_ftype_v8hi_v4si; | |
2212663f DB |
4382 | |
4383 | /* vint, vint, 5 bit literal. */ | |
4384 | else if (mode0 == V4SImode && mode1 == V4SImode && mode2 == QImode) | |
4385 | type = v4si_ftype_v4si_char; | |
4386 | ||
4387 | /* vshort, vshort, 5 bit literal. */ | |
4388 | else if (mode0 == V8HImode && mode1 == V8HImode && mode2 == QImode) | |
4389 | type = v8hi_ftype_v8hi_char; | |
4390 | ||
4391 | /* vchar, vchar, 5 bit literal. */ | |
4392 | else if (mode0 == V16QImode && mode1 == V16QImode && mode2 == QImode) | |
4393 | type = v16qi_ftype_v16qi_char; | |
0ac081f6 | 4394 | |
617e0e1d DB |
4395 | /* vfloat, vint, 5 bit literal. */ |
4396 | else if (mode0 == V4SFmode && mode1 == V4SImode && mode2 == QImode) | |
4397 | type = v4sf_ftype_v4si_char; | |
4398 | ||
4399 | /* vint, vfloat, 5 bit literal. */ | |
4400 | else if (mode0 == V4SImode && mode1 == V4SFmode && mode2 == QImode) | |
4401 | type = v4si_ftype_v4sf_char; | |
4402 | ||
0ac081f6 AH |
4403 | /* int, x, x. */ |
4404 | else if (mode0 == SImode) | |
4405 | { | |
4406 | switch (mode1) | |
4407 | { | |
4408 | case V4SImode: | |
4409 | type = int_ftype_v4si_v4si; | |
4410 | break; | |
4411 | case V4SFmode: | |
4412 | type = int_ftype_v4sf_v4sf; | |
4413 | break; | |
4414 | case V16QImode: | |
4415 | type = int_ftype_v16qi_v16qi; | |
4416 | break; | |
4417 | case V8HImode: | |
4418 | type = int_ftype_v8hi_v8hi; | |
4419 | break; | |
4420 | default: | |
4421 | abort (); | |
4422 | } | |
4423 | } | |
4424 | ||
4425 | else | |
4426 | abort (); | |
4427 | ||
2212663f DB |
4428 | def_builtin (d->mask, d->name, type, d->code); |
4429 | } | |
24408032 | 4430 | |
2212663f DB |
4431 | /* Add the simple unary operators. */ |
4432 | d = (struct builtin_description *) bdesc_1arg; | |
4433 | for (i = 0; i < sizeof (bdesc_1arg) / sizeof *d; i++, d++) | |
4434 | { | |
4435 | enum machine_mode mode0, mode1; | |
4436 | tree type; | |
4437 | ||
4438 | if (d->name == 0) | |
4439 | continue; | |
4440 | ||
4441 | mode0 = insn_data[d->icode].operand[0].mode; | |
4442 | mode1 = insn_data[d->icode].operand[1].mode; | |
4443 | ||
4444 | if (mode0 == V4SImode && mode1 == QImode) | |
4445 | type = v4si_ftype_char; | |
4446 | else if (mode0 == V8HImode && mode1 == QImode) | |
4447 | type = v8hi_ftype_char; | |
4448 | else if (mode0 == V16QImode && mode1 == QImode) | |
4449 | type = v16qi_ftype_char; | |
617e0e1d DB |
4450 | else if (mode0 == V4SFmode && mode1 == V4SFmode) |
4451 | type = v4sf_ftype_v4sf; | |
20e26713 AH |
4452 | else if (mode0 == V8HImode && mode1 == V16QImode) |
4453 | type = v8hi_ftype_v16qi; | |
4454 | else if (mode0 == V4SImode && mode1 == V8HImode) | |
4455 | type = v4si_ftype_v8hi; | |
2212663f DB |
4456 | else |
4457 | abort (); | |
4458 | ||
0ac081f6 AH |
4459 | def_builtin (d->mask, d->name, type, d->code); |
4460 | } | |
4461 | } | |
4462 | ||
5b5040b9 RK |
4463 | \f |
4464 | /* Generate a memory reference for expand_block_move, copying volatile, | |
4465 | and other bits from an original memory reference. */ | |
4466 | ||
4467 | static rtx | |
4468 | expand_block_move_mem (mode, addr, orig_mem) | |
4469 | enum machine_mode mode; | |
4470 | rtx addr; | |
4471 | rtx orig_mem; | |
4472 | { | |
39403d82 | 4473 | rtx mem = gen_rtx_MEM (mode, addr); |
b6c9286a | 4474 | |
c6df88cb | 4475 | MEM_COPY_ATTRIBUTES (mem, orig_mem); |
5b5040b9 RK |
4476 | return mem; |
4477 | } | |
4478 | ||
7e69e155 MM |
4479 | /* Expand a block move operation, and return 1 if successful. Return 0 |
4480 | if we should let the compiler generate normal code. | |
4481 | ||
4482 | operands[0] is the destination | |
4483 | operands[1] is the source | |
4484 | operands[2] is the length | |
4485 | operands[3] is the alignment */ | |
4486 | ||
3933e0e1 MM |
4487 | #define MAX_MOVE_REG 4 |
4488 | ||
7e69e155 MM |
4489 | int |
4490 | expand_block_move (operands) | |
4491 | rtx operands[]; | |
4492 | { | |
b6c9286a MM |
4493 | rtx orig_dest = operands[0]; |
4494 | rtx orig_src = operands[1]; | |
7e69e155 | 4495 | rtx bytes_rtx = operands[2]; |
7e69e155 | 4496 | rtx align_rtx = operands[3]; |
3933e0e1 | 4497 | int constp = (GET_CODE (bytes_rtx) == CONST_INT); |
5ee95df6 | 4498 | int align; |
3933e0e1 MM |
4499 | int bytes; |
4500 | int offset; | |
4501 | int num_reg; | |
4502 | int i; | |
7e69e155 MM |
4503 | rtx src_reg; |
4504 | rtx dest_reg; | |
3933e0e1 MM |
4505 | rtx src_addr; |
4506 | rtx dest_addr; | |
7e69e155 | 4507 | rtx tmp_reg; |
3933e0e1 | 4508 | rtx stores[MAX_MOVE_REG]; |
7e69e155 MM |
4509 | int move_bytes; |
4510 | ||
3933e0e1 | 4511 | /* If this is not a fixed size move, just call memcpy */ |
cc0d9ba8 | 4512 | if (! constp) |
3933e0e1 MM |
4513 | return 0; |
4514 | ||
5ee95df6 FS |
4515 | /* If this is not a fixed size alignment, abort */ |
4516 | if (GET_CODE (align_rtx) != CONST_INT) | |
4517 | abort (); | |
4518 | align = INTVAL (align_rtx); | |
4519 | ||
7e69e155 | 4520 | /* Anything to move? */ |
3933e0e1 MM |
4521 | bytes = INTVAL (bytes_rtx); |
4522 | if (bytes <= 0) | |
7e69e155 MM |
4523 | return 1; |
4524 | ||
ea9982a8 | 4525 | /* store_one_arg depends on expand_block_move to handle at least the size of |
6f317ef3 | 4526 | reg_parm_stack_space. */ |
ea9982a8 | 4527 | if (bytes > (TARGET_POWERPC64 ? 64 : 32)) |
7e69e155 MM |
4528 | return 0; |
4529 | ||
4530 | /* Move the address into scratch registers. */ | |
b6c9286a MM |
4531 | dest_reg = copy_addr_to_reg (XEXP (orig_dest, 0)); |
4532 | src_reg = copy_addr_to_reg (XEXP (orig_src, 0)); | |
7e69e155 | 4533 | |
3933e0e1 | 4534 | if (TARGET_STRING) /* string instructions are available */ |
7e69e155 | 4535 | { |
3933e0e1 | 4536 | for ( ; bytes > 0; bytes -= move_bytes) |
7e69e155 | 4537 | { |
3933e0e1 | 4538 | if (bytes > 24 /* move up to 32 bytes at a time */ |
cc0d9ba8 DE |
4539 | && ! fixed_regs[5] |
4540 | && ! fixed_regs[6] | |
4541 | && ! fixed_regs[7] | |
4542 | && ! fixed_regs[8] | |
4543 | && ! fixed_regs[9] | |
4544 | && ! fixed_regs[10] | |
4545 | && ! fixed_regs[11] | |
4546 | && ! fixed_regs[12]) | |
3933e0e1 MM |
4547 | { |
4548 | move_bytes = (bytes > 32) ? 32 : bytes; | |
cc0d9ba8 DE |
4549 | emit_insn (gen_movstrsi_8reg (expand_block_move_mem (BLKmode, |
4550 | dest_reg, | |
4551 | orig_dest), | |
4552 | expand_block_move_mem (BLKmode, | |
4553 | src_reg, | |
4554 | orig_src), | |
4555 | GEN_INT ((move_bytes == 32) | |
4556 | ? 0 : move_bytes), | |
4c64a852 | 4557 | align_rtx)); |
3933e0e1 MM |
4558 | } |
4559 | else if (bytes > 16 /* move up to 24 bytes at a time */ | |
f9562f27 DE |
4560 | && ! fixed_regs[5] |
4561 | && ! fixed_regs[6] | |
cc0d9ba8 DE |
4562 | && ! fixed_regs[7] |
4563 | && ! fixed_regs[8] | |
4564 | && ! fixed_regs[9] | |
f9562f27 | 4565 | && ! fixed_regs[10]) |
3933e0e1 MM |
4566 | { |
4567 | move_bytes = (bytes > 24) ? 24 : bytes; | |
cc0d9ba8 DE |
4568 | emit_insn (gen_movstrsi_6reg (expand_block_move_mem (BLKmode, |
4569 | dest_reg, | |
4570 | orig_dest), | |
4571 | expand_block_move_mem (BLKmode, | |
4572 | src_reg, | |
4573 | orig_src), | |
3933e0e1 | 4574 | GEN_INT (move_bytes), |
4c64a852 | 4575 | align_rtx)); |
3933e0e1 MM |
4576 | } |
4577 | else if (bytes > 8 /* move up to 16 bytes at a time */ | |
f9562f27 DE |
4578 | && ! fixed_regs[5] |
4579 | && ! fixed_regs[6] | |
4580 | && ! fixed_regs[7] | |
4581 | && ! fixed_regs[8]) | |
3933e0e1 MM |
4582 | { |
4583 | move_bytes = (bytes > 16) ? 16 : bytes; | |
cc0d9ba8 DE |
4584 | emit_insn (gen_movstrsi_4reg (expand_block_move_mem (BLKmode, |
4585 | dest_reg, | |
4586 | orig_dest), | |
4587 | expand_block_move_mem (BLKmode, | |
4588 | src_reg, | |
4589 | orig_src), | |
3933e0e1 | 4590 | GEN_INT (move_bytes), |
4c64a852 | 4591 | align_rtx)); |
3933e0e1 | 4592 | } |
acad7ed3 | 4593 | else if (bytes >= 8 && TARGET_POWERPC64 |
a4f6c312 | 4594 | /* 64-bit loads and stores require word-aligned |
82e41834 | 4595 | displacements. */ |
a4f6c312 | 4596 | && (align >= 8 || (! STRICT_ALIGNMENT && align >= 4))) |
acad7ed3 DE |
4597 | { |
4598 | move_bytes = 8; | |
4599 | tmp_reg = gen_reg_rtx (DImode); | |
4600 | emit_move_insn (tmp_reg, | |
4601 | expand_block_move_mem (DImode, | |
2eba1afa | 4602 | src_reg, orig_src)); |
acad7ed3 | 4603 | emit_move_insn (expand_block_move_mem (DImode, |
2eba1afa | 4604 | dest_reg, orig_dest), |
acad7ed3 DE |
4605 | tmp_reg); |
4606 | } | |
09a625f7 | 4607 | else if (bytes > 4 && !TARGET_POWERPC64) |
3933e0e1 MM |
4608 | { /* move up to 8 bytes at a time */ |
4609 | move_bytes = (bytes > 8) ? 8 : bytes; | |
cc0d9ba8 DE |
4610 | emit_insn (gen_movstrsi_2reg (expand_block_move_mem (BLKmode, |
4611 | dest_reg, | |
4612 | orig_dest), | |
4613 | expand_block_move_mem (BLKmode, | |
4614 | src_reg, | |
4615 | orig_src), | |
3933e0e1 | 4616 | GEN_INT (move_bytes), |
4c64a852 | 4617 | align_rtx)); |
3933e0e1 | 4618 | } |
cc0d9ba8 | 4619 | else if (bytes >= 4 && (align >= 4 || ! STRICT_ALIGNMENT)) |
3933e0e1 MM |
4620 | { /* move 4 bytes */ |
4621 | move_bytes = 4; | |
4622 | tmp_reg = gen_reg_rtx (SImode); | |
cc0d9ba8 DE |
4623 | emit_move_insn (tmp_reg, |
4624 | expand_block_move_mem (SImode, | |
4625 | src_reg, orig_src)); | |
4626 | emit_move_insn (expand_block_move_mem (SImode, | |
4627 | dest_reg, orig_dest), | |
4628 | tmp_reg); | |
3933e0e1 | 4629 | } |
cc0d9ba8 | 4630 | else if (bytes == 2 && (align >= 2 || ! STRICT_ALIGNMENT)) |
3933e0e1 MM |
4631 | { /* move 2 bytes */ |
4632 | move_bytes = 2; | |
4633 | tmp_reg = gen_reg_rtx (HImode); | |
cc0d9ba8 DE |
4634 | emit_move_insn (tmp_reg, |
4635 | expand_block_move_mem (HImode, | |
4636 | src_reg, orig_src)); | |
4637 | emit_move_insn (expand_block_move_mem (HImode, | |
4638 | dest_reg, orig_dest), | |
4639 | tmp_reg); | |
3933e0e1 MM |
4640 | } |
4641 | else if (bytes == 1) /* move 1 byte */ | |
4642 | { | |
4643 | move_bytes = 1; | |
4644 | tmp_reg = gen_reg_rtx (QImode); | |
cc0d9ba8 DE |
4645 | emit_move_insn (tmp_reg, |
4646 | expand_block_move_mem (QImode, | |
4647 | src_reg, orig_src)); | |
4648 | emit_move_insn (expand_block_move_mem (QImode, | |
4649 | dest_reg, orig_dest), | |
4650 | tmp_reg); | |
3933e0e1 MM |
4651 | } |
4652 | else | |
4653 | { /* move up to 4 bytes at a time */ | |
4654 | move_bytes = (bytes > 4) ? 4 : bytes; | |
cc0d9ba8 DE |
4655 | emit_insn (gen_movstrsi_1reg (expand_block_move_mem (BLKmode, |
4656 | dest_reg, | |
4657 | orig_dest), | |
4658 | expand_block_move_mem (BLKmode, | |
4659 | src_reg, | |
4660 | orig_src), | |
3933e0e1 | 4661 | GEN_INT (move_bytes), |
4c64a852 | 4662 | align_rtx)); |
3933e0e1 | 4663 | } |
4c64a852 | 4664 | |
015892ee RK |
4665 | if (bytes > move_bytes) |
4666 | { | |
cc0d9ba8 DE |
4667 | if (! TARGET_POWERPC64) |
4668 | { | |
4669 | emit_insn (gen_addsi3 (src_reg, src_reg, | |
4670 | GEN_INT (move_bytes))); | |
4671 | emit_insn (gen_addsi3 (dest_reg, dest_reg, | |
4672 | GEN_INT (move_bytes))); | |
4673 | } | |
4674 | else | |
4675 | { | |
4676 | emit_insn (gen_adddi3 (src_reg, src_reg, | |
4677 | GEN_INT (move_bytes))); | |
4678 | emit_insn (gen_adddi3 (dest_reg, dest_reg, | |
4679 | GEN_INT (move_bytes))); | |
4680 | } | |
015892ee | 4681 | } |
4c64a852 | 4682 | } |
3933e0e1 MM |
4683 | } |
4684 | ||
4685 | else /* string instructions not available */ | |
4686 | { | |
4687 | num_reg = offset = 0; | |
4688 | for ( ; bytes > 0; (bytes -= move_bytes), (offset += move_bytes)) | |
7e69e155 | 4689 | { |
3933e0e1 MM |
4690 | /* Calculate the correct offset for src/dest */ |
4691 | if (offset == 0) | |
7e69e155 | 4692 | { |
3933e0e1 MM |
4693 | src_addr = src_reg; |
4694 | dest_addr = dest_reg; | |
4695 | } | |
4696 | else | |
4697 | { | |
c5c76735 JL |
4698 | src_addr = plus_constant (src_reg, offset); |
4699 | dest_addr = plus_constant (dest_reg, offset); | |
3933e0e1 MM |
4700 | } |
4701 | ||
cc0d9ba8 DE |
4702 | /* Generate the appropriate load and store, saving the stores |
4703 | for later. */ | |
4704 | if (bytes >= 8 && TARGET_POWERPC64 | |
a4f6c312 SS |
4705 | /* 64-bit loads and stores require word-aligned |
4706 | displacements. */ | |
cc0d9ba8 | 4707 | && (align >= 8 || (! STRICT_ALIGNMENT && align >= 4))) |
b6c9286a MM |
4708 | { |
4709 | move_bytes = 8; | |
4710 | tmp_reg = gen_reg_rtx (DImode); | |
cc0d9ba8 DE |
4711 | emit_insn (gen_movdi (tmp_reg, |
4712 | expand_block_move_mem (DImode, | |
4713 | src_addr, | |
4714 | orig_src))); | |
4715 | stores[num_reg++] = gen_movdi (expand_block_move_mem (DImode, | |
4716 | dest_addr, | |
4717 | orig_dest), | |
4718 | tmp_reg); | |
b6c9286a | 4719 | } |
cc0d9ba8 | 4720 | else if (bytes >= 4 && (align >= 4 || ! STRICT_ALIGNMENT)) |
3933e0e1 MM |
4721 | { |
4722 | move_bytes = 4; | |
4723 | tmp_reg = gen_reg_rtx (SImode); | |
cc0d9ba8 DE |
4724 | emit_insn (gen_movsi (tmp_reg, |
4725 | expand_block_move_mem (SImode, | |
4726 | src_addr, | |
4727 | orig_src))); | |
4728 | stores[num_reg++] = gen_movsi (expand_block_move_mem (SImode, | |
4729 | dest_addr, | |
4730 | orig_dest), | |
4731 | tmp_reg); | |
3933e0e1 | 4732 | } |
cc0d9ba8 | 4733 | else if (bytes >= 2 && (align >= 2 || ! STRICT_ALIGNMENT)) |
3933e0e1 MM |
4734 | { |
4735 | move_bytes = 2; | |
4736 | tmp_reg = gen_reg_rtx (HImode); | |
c81fc13e | 4737 | emit_insn (gen_movhi (tmp_reg, |
cc0d9ba8 DE |
4738 | expand_block_move_mem (HImode, |
4739 | src_addr, | |
4740 | orig_src))); | |
4741 | stores[num_reg++] = gen_movhi (expand_block_move_mem (HImode, | |
4742 | dest_addr, | |
4743 | orig_dest), | |
4744 | tmp_reg); | |
3933e0e1 MM |
4745 | } |
4746 | else | |
4747 | { | |
4748 | move_bytes = 1; | |
4749 | tmp_reg = gen_reg_rtx (QImode); | |
c81fc13e | 4750 | emit_insn (gen_movqi (tmp_reg, |
cc0d9ba8 DE |
4751 | expand_block_move_mem (QImode, |
4752 | src_addr, | |
4753 | orig_src))); | |
4754 | stores[num_reg++] = gen_movqi (expand_block_move_mem (QImode, | |
4755 | dest_addr, | |
4756 | orig_dest), | |
a4f6c312 | 4757 | tmp_reg); |
3933e0e1 MM |
4758 | } |
4759 | ||
4760 | if (num_reg >= MAX_MOVE_REG) | |
4761 | { | |
4762 | for (i = 0; i < num_reg; i++) | |
4763 | emit_insn (stores[i]); | |
4764 | num_reg = 0; | |
7e69e155 MM |
4765 | } |
4766 | } | |
3933e0e1 | 4767 | |
b6c9286a MM |
4768 | for (i = 0; i < num_reg; i++) |
4769 | emit_insn (stores[i]); | |
7e69e155 MM |
4770 | } |
4771 | ||
4772 | return 1; | |
4773 | } | |
4774 | ||
9878760c RK |
4775 | \f |
4776 | /* Return 1 if OP is a load multiple operation. It is known to be a | |
4777 | PARALLEL and the first section will be tested. */ | |
4778 | ||
4779 | int | |
4780 | load_multiple_operation (op, mode) | |
4781 | rtx op; | |
296b8152 | 4782 | enum machine_mode mode ATTRIBUTE_UNUSED; |
9878760c RK |
4783 | { |
4784 | int count = XVECLEN (op, 0); | |
e2c953b6 | 4785 | unsigned int dest_regno; |
9878760c RK |
4786 | rtx src_addr; |
4787 | int i; | |
4788 | ||
4789 | /* Perform a quick check so we don't blow up below. */ | |
4790 | if (count <= 1 | |
4791 | || GET_CODE (XVECEXP (op, 0, 0)) != SET | |
4792 | || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG | |
4793 | || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM) | |
4794 | return 0; | |
4795 | ||
4796 | dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0))); | |
4797 | src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0); | |
4798 | ||
4799 | for (i = 1; i < count; i++) | |
4800 | { | |
4801 | rtx elt = XVECEXP (op, 0, i); | |
4802 | ||
4803 | if (GET_CODE (elt) != SET | |
4804 | || GET_CODE (SET_DEST (elt)) != REG | |
4805 | || GET_MODE (SET_DEST (elt)) != SImode | |
4806 | || REGNO (SET_DEST (elt)) != dest_regno + i | |
4807 | || GET_CODE (SET_SRC (elt)) != MEM | |
4808 | || GET_MODE (SET_SRC (elt)) != SImode | |
4809 | || GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS | |
4810 | || ! rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr) | |
4811 | || GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT | |
4812 | || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != i * 4) | |
4813 | return 0; | |
4814 | } | |
4815 | ||
4816 | return 1; | |
4817 | } | |
4818 | ||
4819 | /* Similar, but tests for store multiple. Here, the second vector element | |
4820 | is a CLOBBER. It will be tested later. */ | |
4821 | ||
4822 | int | |
4823 | store_multiple_operation (op, mode) | |
4824 | rtx op; | |
296b8152 | 4825 | enum machine_mode mode ATTRIBUTE_UNUSED; |
9878760c RK |
4826 | { |
4827 | int count = XVECLEN (op, 0) - 1; | |
e2c953b6 | 4828 | unsigned int src_regno; |
9878760c RK |
4829 | rtx dest_addr; |
4830 | int i; | |
4831 | ||
4832 | /* Perform a quick check so we don't blow up below. */ | |
4833 | if (count <= 1 | |
4834 | || GET_CODE (XVECEXP (op, 0, 0)) != SET | |
4835 | || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM | |
4836 | || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG) | |
4837 | return 0; | |
4838 | ||
4839 | src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0))); | |
4840 | dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0); | |
4841 | ||
4842 | for (i = 1; i < count; i++) | |
4843 | { | |
4844 | rtx elt = XVECEXP (op, 0, i + 1); | |
4845 | ||
4846 | if (GET_CODE (elt) != SET | |
4847 | || GET_CODE (SET_SRC (elt)) != REG | |
4848 | || GET_MODE (SET_SRC (elt)) != SImode | |
4849 | || REGNO (SET_SRC (elt)) != src_regno + i | |
4850 | || GET_CODE (SET_DEST (elt)) != MEM | |
4851 | || GET_MODE (SET_DEST (elt)) != SImode | |
4852 | || GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS | |
4853 | || ! rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr) | |
4854 | || GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT | |
4855 | || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != i * 4) | |
4856 | return 0; | |
4857 | } | |
4858 | ||
4859 | return 1; | |
4860 | } | |
9ebbca7d | 4861 | |
00b960c7 AH |
4862 | /* Return 1 for a parallel vrsave operation. */ |
4863 | ||
4864 | int | |
4865 | vrsave_operation (op, mode) | |
4866 | rtx op; | |
4867 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
4868 | { | |
4869 | int count = XVECLEN (op, 0); | |
4870 | unsigned int dest_regno, src_regno; | |
4871 | int i; | |
4872 | ||
4873 | if (count <= 1 | |
4874 | || GET_CODE (XVECEXP (op, 0, 0)) != SET | |
4875 | || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG | |
a004eb82 | 4876 | || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC_VOLATILE) |
00b960c7 AH |
4877 | return 0; |
4878 | ||
4879 | dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0))); | |
4880 | src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0))); | |
4881 | ||
4882 | if (dest_regno != VRSAVE_REGNO | |
4883 | && src_regno != VRSAVE_REGNO) | |
4884 | return 0; | |
4885 | ||
4886 | for (i = 1; i < count; i++) | |
4887 | { | |
4888 | rtx elt = XVECEXP (op, 0, i); | |
4889 | ||
9aa86737 AH |
4890 | if (GET_CODE (elt) != CLOBBER |
4891 | && GET_CODE (elt) != SET) | |
00b960c7 AH |
4892 | return 0; |
4893 | } | |
4894 | ||
4895 | return 1; | |
4896 | } | |
4897 | ||
a4f6c312 | 4898 | /* Return 1 for an PARALLEL suitable for mtcrf. */ |
9ebbca7d GK |
4899 | |
4900 | int | |
4901 | mtcrf_operation (op, mode) | |
4902 | rtx op; | |
4903 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
4904 | { | |
4905 | int count = XVECLEN (op, 0); | |
4906 | int i; | |
9ebbca7d GK |
4907 | rtx src_reg; |
4908 | ||
4909 | /* Perform a quick check so we don't blow up below. */ | |
e35b9579 GK |
4910 | if (count < 1 |
4911 | || GET_CODE (XVECEXP (op, 0, 0)) != SET | |
4912 | || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC | |
4913 | || XVECLEN (SET_SRC (XVECEXP (op, 0, 0)), 0) != 2) | |
9ebbca7d | 4914 | return 0; |
e35b9579 | 4915 | src_reg = XVECEXP (SET_SRC (XVECEXP (op, 0, 0)), 0, 0); |
9ebbca7d GK |
4916 | |
4917 | if (GET_CODE (src_reg) != REG | |
4918 | || GET_MODE (src_reg) != SImode | |
4919 | || ! INT_REGNO_P (REGNO (src_reg))) | |
4920 | return 0; | |
4921 | ||
e35b9579 | 4922 | for (i = 0; i < count; i++) |
9ebbca7d GK |
4923 | { |
4924 | rtx exp = XVECEXP (op, 0, i); | |
4925 | rtx unspec; | |
4926 | int maskval; | |
4927 | ||
4928 | if (GET_CODE (exp) != SET | |
4929 | || GET_CODE (SET_DEST (exp)) != REG | |
4930 | || GET_MODE (SET_DEST (exp)) != CCmode | |
4931 | || ! CR_REGNO_P (REGNO (SET_DEST (exp)))) | |
4932 | return 0; | |
4933 | unspec = SET_SRC (exp); | |
4934 | maskval = 1 << (MAX_CR_REGNO - REGNO (SET_DEST (exp))); | |
9ebbca7d GK |
4935 | |
4936 | if (GET_CODE (unspec) != UNSPEC | |
4937 | || XINT (unspec, 1) != 20 | |
4938 | || XVECLEN (unspec, 0) != 2 | |
4939 | || XVECEXP (unspec, 0, 0) != src_reg | |
4940 | || GET_CODE (XVECEXP (unspec, 0, 1)) != CONST_INT | |
4941 | || INTVAL (XVECEXP (unspec, 0, 1)) != maskval) | |
4942 | return 0; | |
4943 | } | |
e35b9579 | 4944 | return 1; |
9ebbca7d GK |
4945 | } |
4946 | ||
a4f6c312 | 4947 | /* Return 1 for an PARALLEL suitable for lmw. */ |
9ebbca7d GK |
4948 | |
4949 | int | |
4950 | lmw_operation (op, mode) | |
4951 | rtx op; | |
4952 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
4953 | { | |
4954 | int count = XVECLEN (op, 0); | |
e2c953b6 | 4955 | unsigned int dest_regno; |
9ebbca7d | 4956 | rtx src_addr; |
e2c953b6 | 4957 | unsigned int base_regno; |
9ebbca7d GK |
4958 | HOST_WIDE_INT offset; |
4959 | int i; | |
4960 | ||
4961 | /* Perform a quick check so we don't blow up below. */ | |
4962 | if (count <= 1 | |
4963 | || GET_CODE (XVECEXP (op, 0, 0)) != SET | |
4964 | || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG | |
4965 | || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM) | |
4966 | return 0; | |
4967 | ||
4968 | dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0))); | |
4969 | src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0); | |
4970 | ||
4971 | if (dest_regno > 31 | |
e2c953b6 | 4972 | || count != 32 - (int) dest_regno) |
9ebbca7d GK |
4973 | return 0; |
4974 | ||
258bfae2 | 4975 | if (LEGITIMATE_INDIRECT_ADDRESS_P (src_addr, 0)) |
9ebbca7d GK |
4976 | { |
4977 | offset = 0; | |
4978 | base_regno = REGNO (src_addr); | |
4979 | if (base_regno == 0) | |
4980 | return 0; | |
4981 | } | |
258bfae2 | 4982 | else if (LEGITIMATE_OFFSET_ADDRESS_P (SImode, src_addr, 0)) |
9ebbca7d GK |
4983 | { |
4984 | offset = INTVAL (XEXP (src_addr, 1)); | |
4985 | base_regno = REGNO (XEXP (src_addr, 0)); | |
4986 | } | |
4987 | else | |
4988 | return 0; | |
4989 | ||
4990 | for (i = 0; i < count; i++) | |
4991 | { | |
4992 | rtx elt = XVECEXP (op, 0, i); | |
4993 | rtx newaddr; | |
4994 | rtx addr_reg; | |
4995 | HOST_WIDE_INT newoffset; | |
4996 | ||
4997 | if (GET_CODE (elt) != SET | |
4998 | || GET_CODE (SET_DEST (elt)) != REG | |
4999 | || GET_MODE (SET_DEST (elt)) != SImode | |
5000 | || REGNO (SET_DEST (elt)) != dest_regno + i | |
5001 | || GET_CODE (SET_SRC (elt)) != MEM | |
5002 | || GET_MODE (SET_SRC (elt)) != SImode) | |
5003 | return 0; | |
5004 | newaddr = XEXP (SET_SRC (elt), 0); | |
258bfae2 | 5005 | if (LEGITIMATE_INDIRECT_ADDRESS_P (newaddr, 0)) |
9ebbca7d GK |
5006 | { |
5007 | newoffset = 0; | |
5008 | addr_reg = newaddr; | |
5009 | } | |
258bfae2 | 5010 | else if (LEGITIMATE_OFFSET_ADDRESS_P (SImode, newaddr, 0)) |
9ebbca7d GK |
5011 | { |
5012 | addr_reg = XEXP (newaddr, 0); | |
5013 | newoffset = INTVAL (XEXP (newaddr, 1)); | |
5014 | } | |
5015 | else | |
5016 | return 0; | |
5017 | if (REGNO (addr_reg) != base_regno | |
5018 | || newoffset != offset + 4 * i) | |
5019 | return 0; | |
5020 | } | |
5021 | ||
5022 | return 1; | |
5023 | } | |
5024 | ||
a4f6c312 | 5025 | /* Return 1 for an PARALLEL suitable for stmw. */ |
9ebbca7d GK |
5026 | |
5027 | int | |
5028 | stmw_operation (op, mode) | |
5029 | rtx op; | |
5030 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
5031 | { | |
5032 | int count = XVECLEN (op, 0); | |
e2c953b6 | 5033 | unsigned int src_regno; |
9ebbca7d | 5034 | rtx dest_addr; |
e2c953b6 | 5035 | unsigned int base_regno; |
9ebbca7d GK |
5036 | HOST_WIDE_INT offset; |
5037 | int i; | |
5038 | ||
5039 | /* Perform a quick check so we don't blow up below. */ | |
5040 | if (count <= 1 | |
5041 | || GET_CODE (XVECEXP (op, 0, 0)) != SET | |
5042 | || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM | |
5043 | || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG) | |
5044 | return 0; | |
5045 | ||
5046 | src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0))); | |
5047 | dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0); | |
5048 | ||
5049 | if (src_regno > 31 | |
e2c953b6 | 5050 | || count != 32 - (int) src_regno) |
9ebbca7d GK |
5051 | return 0; |
5052 | ||
258bfae2 | 5053 | if (LEGITIMATE_INDIRECT_ADDRESS_P (dest_addr, 0)) |
9ebbca7d GK |
5054 | { |
5055 | offset = 0; | |
5056 | base_regno = REGNO (dest_addr); | |
5057 | if (base_regno == 0) | |
5058 | return 0; | |
5059 | } | |
258bfae2 | 5060 | else if (LEGITIMATE_OFFSET_ADDRESS_P (SImode, dest_addr, 0)) |
9ebbca7d GK |
5061 | { |
5062 | offset = INTVAL (XEXP (dest_addr, 1)); | |
5063 | base_regno = REGNO (XEXP (dest_addr, 0)); | |
5064 | } | |
5065 | else | |
5066 | return 0; | |
5067 | ||
5068 | for (i = 0; i < count; i++) | |
5069 | { | |
5070 | rtx elt = XVECEXP (op, 0, i); | |
5071 | rtx newaddr; | |
5072 | rtx addr_reg; | |
5073 | HOST_WIDE_INT newoffset; | |
5074 | ||
5075 | if (GET_CODE (elt) != SET | |
5076 | || GET_CODE (SET_SRC (elt)) != REG | |
5077 | || GET_MODE (SET_SRC (elt)) != SImode | |
5078 | || REGNO (SET_SRC (elt)) != src_regno + i | |
5079 | || GET_CODE (SET_DEST (elt)) != MEM | |
5080 | || GET_MODE (SET_DEST (elt)) != SImode) | |
5081 | return 0; | |
5082 | newaddr = XEXP (SET_DEST (elt), 0); | |
258bfae2 | 5083 | if (LEGITIMATE_INDIRECT_ADDRESS_P (newaddr, 0)) |
9ebbca7d GK |
5084 | { |
5085 | newoffset = 0; | |
5086 | addr_reg = newaddr; | |
5087 | } | |
258bfae2 | 5088 | else if (LEGITIMATE_OFFSET_ADDRESS_P (SImode, newaddr, 0)) |
9ebbca7d GK |
5089 | { |
5090 | addr_reg = XEXP (newaddr, 0); | |
5091 | newoffset = INTVAL (XEXP (newaddr, 1)); | |
5092 | } | |
5093 | else | |
5094 | return 0; | |
5095 | if (REGNO (addr_reg) != base_regno | |
5096 | || newoffset != offset + 4 * i) | |
5097 | return 0; | |
5098 | } | |
5099 | ||
5100 | return 1; | |
5101 | } | |
9878760c | 5102 | \f |
a4f6c312 SS |
5103 | /* A validation routine: say whether CODE, a condition code, and MODE |
5104 | match. The other alternatives either don't make sense or should | |
5105 | never be generated. */ | |
39a10a29 | 5106 | |
39a10a29 GK |
5107 | static void |
5108 | validate_condition_mode (code, mode) | |
5109 | enum rtx_code code; | |
5110 | enum machine_mode mode; | |
5111 | { | |
5112 | if (GET_RTX_CLASS (code) != '<' | |
5113 | || GET_MODE_CLASS (mode) != MODE_CC) | |
5114 | abort (); | |
5115 | ||
5116 | /* These don't make sense. */ | |
5117 | if ((code == GT || code == LT || code == GE || code == LE) | |
5118 | && mode == CCUNSmode) | |
5119 | abort (); | |
5120 | ||
5121 | if ((code == GTU || code == LTU || code == GEU || code == LEU) | |
5122 | && mode != CCUNSmode) | |
5123 | abort (); | |
5124 | ||
5125 | if (mode != CCFPmode | |
5126 | && (code == ORDERED || code == UNORDERED | |
5127 | || code == UNEQ || code == LTGT | |
5128 | || code == UNGT || code == UNLT | |
5129 | || code == UNGE || code == UNLE)) | |
a4f6c312 | 5130 | abort (); |
39a10a29 | 5131 | |
de6c5979 BL |
5132 | /* These should never be generated except for |
5133 | flag_unsafe_math_optimizations. */ | |
39a10a29 | 5134 | if (mode == CCFPmode |
de6c5979 | 5135 | && ! flag_unsafe_math_optimizations |
39a10a29 GK |
5136 | && (code == LE || code == GE |
5137 | || code == UNEQ || code == LTGT | |
5138 | || code == UNGT || code == UNLT)) | |
5139 | abort (); | |
5140 | ||
5141 | /* These are invalid; the information is not there. */ | |
5142 | if (mode == CCEQmode | |
5143 | && code != EQ && code != NE) | |
5144 | abort (); | |
5145 | } | |
5146 | ||
9878760c RK |
5147 | /* Return 1 if OP is a comparison operation that is valid for a branch insn. |
5148 | We only check the opcode against the mode of the CC value here. */ | |
5149 | ||
5150 | int | |
5151 | branch_comparison_operator (op, mode) | |
592696dd | 5152 | rtx op; |
296b8152 | 5153 | enum machine_mode mode ATTRIBUTE_UNUSED; |
9878760c RK |
5154 | { |
5155 | enum rtx_code code = GET_CODE (op); | |
5156 | enum machine_mode cc_mode; | |
5157 | ||
5158 | if (GET_RTX_CLASS (code) != '<') | |
5159 | return 0; | |
5160 | ||
5161 | cc_mode = GET_MODE (XEXP (op, 0)); | |
5162 | if (GET_MODE_CLASS (cc_mode) != MODE_CC) | |
5163 | return 0; | |
5164 | ||
39a10a29 | 5165 | validate_condition_mode (code, cc_mode); |
9878760c | 5166 | |
39a10a29 GK |
5167 | return 1; |
5168 | } | |
5169 | ||
5170 | /* Return 1 if OP is a comparison operation that is valid for a branch | |
5171 | insn and which is true if the corresponding bit in the CC register | |
5172 | is set. */ | |
5173 | ||
5174 | int | |
5175 | branch_positive_comparison_operator (op, mode) | |
592696dd | 5176 | rtx op; |
39a10a29 GK |
5177 | enum machine_mode mode; |
5178 | { | |
5179 | enum rtx_code code; | |
5180 | ||
5181 | if (! branch_comparison_operator (op, mode)) | |
9878760c RK |
5182 | return 0; |
5183 | ||
39a10a29 GK |
5184 | code = GET_CODE (op); |
5185 | return (code == EQ || code == LT || code == GT | |
5186 | || code == LTU || code == GTU | |
5187 | || code == UNORDERED); | |
9878760c RK |
5188 | } |
5189 | ||
5190 | /* Return 1 if OP is a comparison operation that is valid for an scc insn. | |
5191 | We check the opcode against the mode of the CC value and disallow EQ or | |
5192 | NE comparisons for integers. */ | |
5193 | ||
5194 | int | |
5195 | scc_comparison_operator (op, mode) | |
592696dd | 5196 | rtx op; |
9878760c RK |
5197 | enum machine_mode mode; |
5198 | { | |
5199 | enum rtx_code code = GET_CODE (op); | |
5200 | enum machine_mode cc_mode; | |
5201 | ||
5202 | if (GET_MODE (op) != mode && mode != VOIDmode) | |
5203 | return 0; | |
5204 | ||
5205 | if (GET_RTX_CLASS (code) != '<') | |
5206 | return 0; | |
5207 | ||
5208 | cc_mode = GET_MODE (XEXP (op, 0)); | |
5209 | if (GET_MODE_CLASS (cc_mode) != MODE_CC) | |
5210 | return 0; | |
5211 | ||
39a10a29 | 5212 | validate_condition_mode (code, cc_mode); |
9878760c | 5213 | |
39a10a29 | 5214 | if (code == NE && cc_mode != CCFPmode) |
c5defebb RK |
5215 | return 0; |
5216 | ||
9878760c RK |
5217 | return 1; |
5218 | } | |
e0cd0770 JC |
5219 | |
5220 | int | |
5221 | trap_comparison_operator (op, mode) | |
5222 | rtx op; | |
5223 | enum machine_mode mode; | |
5224 | { | |
5225 | if (mode != VOIDmode && mode != GET_MODE (op)) | |
5226 | return 0; | |
39a10a29 | 5227 | return GET_RTX_CLASS (GET_CODE (op)) == '<'; |
e0cd0770 | 5228 | } |
dfbdccdb GK |
5229 | |
5230 | int | |
5231 | boolean_operator (op, mode) | |
5232 | rtx op; | |
5233 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
5234 | { | |
5235 | enum rtx_code code = GET_CODE (op); | |
5236 | return (code == AND || code == IOR || code == XOR); | |
5237 | } | |
1d328b19 GK |
5238 | |
5239 | int | |
5240 | boolean_or_operator (op, mode) | |
5241 | rtx op; | |
5242 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
5243 | { | |
5244 | enum rtx_code code = GET_CODE (op); | |
5245 | return (code == IOR || code == XOR); | |
5246 | } | |
50a0b056 GK |
5247 | |
5248 | int | |
5249 | min_max_operator (op, mode) | |
5250 | rtx op; | |
5251 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
5252 | { | |
5253 | enum rtx_code code = GET_CODE (op); | |
5254 | return (code == SMIN || code == SMAX || code == UMIN || code == UMAX); | |
5255 | } | |
9878760c RK |
5256 | \f |
5257 | /* Return 1 if ANDOP is a mask that has no bits on that are not in the | |
5258 | mask required to convert the result of a rotate insn into a shift | |
5259 | left insn of SHIFTOP bits. Both are known to be CONST_INT. */ | |
5260 | ||
5261 | int | |
5262 | includes_lshift_p (shiftop, andop) | |
592696dd SS |
5263 | rtx shiftop; |
5264 | rtx andop; | |
9878760c | 5265 | { |
e2c953b6 DE |
5266 | unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0; |
5267 | ||
5268 | shift_mask <<= INTVAL (shiftop); | |
9878760c RK |
5269 | |
5270 | return (INTVAL (andop) & ~shift_mask) == 0; | |
5271 | } | |
5272 | ||
5273 | /* Similar, but for right shift. */ | |
5274 | ||
5275 | int | |
5276 | includes_rshift_p (shiftop, andop) | |
592696dd SS |
5277 | rtx shiftop; |
5278 | rtx andop; | |
9878760c | 5279 | { |
a7653a2c | 5280 | unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0; |
9878760c RK |
5281 | |
5282 | shift_mask >>= INTVAL (shiftop); | |
5283 | ||
e2c953b6 DE |
5284 | return (INTVAL (andop) & ~shift_mask) == 0; |
5285 | } | |
5286 | ||
c5059423 AM |
5287 | /* Return 1 if ANDOP is a mask suitable for use with an rldic insn |
5288 | to perform a left shift. It must have exactly SHIFTOP least | |
5289 | signifigant 0's, then one or more 1's, then zero or more 0's. */ | |
e2c953b6 DE |
5290 | |
5291 | int | |
c5059423 | 5292 | includes_rldic_lshift_p (shiftop, andop) |
592696dd SS |
5293 | rtx shiftop; |
5294 | rtx andop; | |
e2c953b6 | 5295 | { |
c5059423 AM |
5296 | if (GET_CODE (andop) == CONST_INT) |
5297 | { | |
02071907 | 5298 | HOST_WIDE_INT c, lsb, shift_mask; |
e2c953b6 | 5299 | |
c5059423 | 5300 | c = INTVAL (andop); |
02071907 | 5301 | if (c == 0 || c == ~0) |
c5059423 | 5302 | return 0; |
e2c953b6 | 5303 | |
02071907 | 5304 | shift_mask = ~0; |
c5059423 AM |
5305 | shift_mask <<= INTVAL (shiftop); |
5306 | ||
5307 | /* Find the least signifigant one bit. */ | |
5308 | lsb = c & -c; | |
5309 | ||
5310 | /* It must coincide with the LSB of the shift mask. */ | |
5311 | if (-lsb != shift_mask) | |
5312 | return 0; | |
e2c953b6 | 5313 | |
c5059423 AM |
5314 | /* Invert to look for the next transition (if any). */ |
5315 | c = ~c; | |
5316 | ||
5317 | /* Remove the low group of ones (originally low group of zeros). */ | |
5318 | c &= -lsb; | |
5319 | ||
5320 | /* Again find the lsb, and check we have all 1's above. */ | |
5321 | lsb = c & -c; | |
5322 | return c == -lsb; | |
5323 | } | |
5324 | else if (GET_CODE (andop) == CONST_DOUBLE | |
5325 | && (GET_MODE (andop) == VOIDmode || GET_MODE (andop) == DImode)) | |
5326 | { | |
02071907 AM |
5327 | HOST_WIDE_INT low, high, lsb; |
5328 | HOST_WIDE_INT shift_mask_low, shift_mask_high; | |
c5059423 AM |
5329 | |
5330 | low = CONST_DOUBLE_LOW (andop); | |
5331 | if (HOST_BITS_PER_WIDE_INT < 64) | |
5332 | high = CONST_DOUBLE_HIGH (andop); | |
5333 | ||
5334 | if ((low == 0 && (HOST_BITS_PER_WIDE_INT >= 64 || high == 0)) | |
02071907 | 5335 | || (low == ~0 && (HOST_BITS_PER_WIDE_INT >= 64 || high == ~0))) |
c5059423 AM |
5336 | return 0; |
5337 | ||
5338 | if (HOST_BITS_PER_WIDE_INT < 64 && low == 0) | |
5339 | { | |
02071907 | 5340 | shift_mask_high = ~0; |
c5059423 AM |
5341 | if (INTVAL (shiftop) > 32) |
5342 | shift_mask_high <<= INTVAL (shiftop) - 32; | |
5343 | ||
5344 | lsb = high & -high; | |
5345 | ||
5346 | if (-lsb != shift_mask_high || INTVAL (shiftop) < 32) | |
5347 | return 0; | |
5348 | ||
5349 | high = ~high; | |
5350 | high &= -lsb; | |
5351 | ||
5352 | lsb = high & -high; | |
5353 | return high == -lsb; | |
5354 | } | |
5355 | ||
02071907 | 5356 | shift_mask_low = ~0; |
c5059423 AM |
5357 | shift_mask_low <<= INTVAL (shiftop); |
5358 | ||
5359 | lsb = low & -low; | |
5360 | ||
5361 | if (-lsb != shift_mask_low) | |
5362 | return 0; | |
5363 | ||
5364 | if (HOST_BITS_PER_WIDE_INT < 64) | |
5365 | high = ~high; | |
5366 | low = ~low; | |
5367 | low &= -lsb; | |
5368 | ||
5369 | if (HOST_BITS_PER_WIDE_INT < 64 && low == 0) | |
5370 | { | |
5371 | lsb = high & -high; | |
5372 | return high == -lsb; | |
5373 | } | |
5374 | ||
5375 | lsb = low & -low; | |
5376 | return low == -lsb && (HOST_BITS_PER_WIDE_INT >= 64 || high == ~0); | |
5377 | } | |
5378 | else | |
5379 | return 0; | |
5380 | } | |
e2c953b6 | 5381 | |
c5059423 AM |
5382 | /* Return 1 if ANDOP is a mask suitable for use with an rldicr insn |
5383 | to perform a left shift. It must have SHIFTOP or more least | |
5384 | signifigant 0's, with the remainder of the word 1's. */ | |
e2c953b6 | 5385 | |
c5059423 AM |
5386 | int |
5387 | includes_rldicr_lshift_p (shiftop, andop) | |
592696dd SS |
5388 | rtx shiftop; |
5389 | rtx andop; | |
c5059423 | 5390 | { |
e2c953b6 | 5391 | if (GET_CODE (andop) == CONST_INT) |
c5059423 | 5392 | { |
02071907 | 5393 | HOST_WIDE_INT c, lsb, shift_mask; |
c5059423 | 5394 | |
02071907 | 5395 | shift_mask = ~0; |
c5059423 AM |
5396 | shift_mask <<= INTVAL (shiftop); |
5397 | c = INTVAL (andop); | |
5398 | ||
5399 | /* Find the least signifigant one bit. */ | |
5400 | lsb = c & -c; | |
5401 | ||
5402 | /* It must be covered by the shift mask. | |
a4f6c312 | 5403 | This test also rejects c == 0. */ |
c5059423 AM |
5404 | if ((lsb & shift_mask) == 0) |
5405 | return 0; | |
5406 | ||
5407 | /* Check we have all 1's above the transition, and reject all 1's. */ | |
5408 | return c == -lsb && lsb != 1; | |
5409 | } | |
5410 | else if (GET_CODE (andop) == CONST_DOUBLE | |
5411 | && (GET_MODE (andop) == VOIDmode || GET_MODE (andop) == DImode)) | |
5412 | { | |
02071907 | 5413 | HOST_WIDE_INT low, lsb, shift_mask_low; |
c5059423 AM |
5414 | |
5415 | low = CONST_DOUBLE_LOW (andop); | |
5416 | ||
5417 | if (HOST_BITS_PER_WIDE_INT < 64) | |
5418 | { | |
02071907 | 5419 | HOST_WIDE_INT high, shift_mask_high; |
c5059423 AM |
5420 | |
5421 | high = CONST_DOUBLE_HIGH (andop); | |
5422 | ||
5423 | if (low == 0) | |
5424 | { | |
02071907 | 5425 | shift_mask_high = ~0; |
c5059423 AM |
5426 | if (INTVAL (shiftop) > 32) |
5427 | shift_mask_high <<= INTVAL (shiftop) - 32; | |
5428 | ||
5429 | lsb = high & -high; | |
5430 | ||
5431 | if ((lsb & shift_mask_high) == 0) | |
5432 | return 0; | |
5433 | ||
5434 | return high == -lsb; | |
5435 | } | |
5436 | if (high != ~0) | |
5437 | return 0; | |
5438 | } | |
5439 | ||
02071907 | 5440 | shift_mask_low = ~0; |
c5059423 AM |
5441 | shift_mask_low <<= INTVAL (shiftop); |
5442 | ||
5443 | lsb = low & -low; | |
5444 | ||
5445 | if ((lsb & shift_mask_low) == 0) | |
5446 | return 0; | |
5447 | ||
5448 | return low == -lsb && lsb != 1; | |
5449 | } | |
e2c953b6 | 5450 | else |
c5059423 | 5451 | return 0; |
9878760c | 5452 | } |
35068b43 RK |
5453 | |
5454 | /* Return 1 if REGNO (reg1) == REGNO (reg2) - 1 making them candidates | |
5455 | for lfq and stfq insns. | |
5456 | ||
5457 | Note reg1 and reg2 *must* be hard registers. To be sure we will | |
5458 | abort if we are passed pseudo registers. */ | |
5459 | ||
5460 | int | |
5461 | registers_ok_for_quad_peep (reg1, reg2) | |
5462 | rtx reg1, reg2; | |
5463 | { | |
5464 | /* We might have been passed a SUBREG. */ | |
5465 | if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG) | |
5466 | return 0; | |
5467 | ||
5468 | return (REGNO (reg1) == REGNO (reg2) - 1); | |
5469 | } | |
5470 | ||
a4f6c312 SS |
5471 | /* Return 1 if addr1 and addr2 are suitable for lfq or stfq insn. |
5472 | addr1 and addr2 must be in consecutive memory locations | |
5473 | (addr2 == addr1 + 8). */ | |
35068b43 RK |
5474 | |
5475 | int | |
5476 | addrs_ok_for_quad_peep (addr1, addr2) | |
592696dd SS |
5477 | rtx addr1; |
5478 | rtx addr2; | |
35068b43 | 5479 | { |
e2c953b6 | 5480 | unsigned int reg1; |
35068b43 RK |
5481 | int offset1; |
5482 | ||
5483 | /* Extract an offset (if used) from the first addr. */ | |
5484 | if (GET_CODE (addr1) == PLUS) | |
5485 | { | |
5486 | /* If not a REG, return zero. */ | |
5487 | if (GET_CODE (XEXP (addr1, 0)) != REG) | |
5488 | return 0; | |
5489 | else | |
5490 | { | |
5491 | reg1 = REGNO (XEXP (addr1, 0)); | |
5492 | /* The offset must be constant! */ | |
5493 | if (GET_CODE (XEXP (addr1, 1)) != CONST_INT) | |
5494 | return 0; | |
5495 | offset1 = INTVAL (XEXP (addr1, 1)); | |
5496 | } | |
5497 | } | |
5498 | else if (GET_CODE (addr1) != REG) | |
5499 | return 0; | |
5500 | else | |
5501 | { | |
5502 | reg1 = REGNO (addr1); | |
5503 | /* This was a simple (mem (reg)) expression. Offset is 0. */ | |
5504 | offset1 = 0; | |
5505 | } | |
5506 | ||
acad7ed3 | 5507 | /* Make sure the second address is a (mem (plus (reg) (const_int))). */ |
35068b43 RK |
5508 | if (GET_CODE (addr2) != PLUS) |
5509 | return 0; | |
5510 | ||
5511 | if (GET_CODE (XEXP (addr2, 0)) != REG | |
5512 | || GET_CODE (XEXP (addr2, 1)) != CONST_INT) | |
5513 | return 0; | |
5514 | ||
5515 | if (reg1 != REGNO (XEXP (addr2, 0))) | |
5516 | return 0; | |
5517 | ||
5518 | /* The offset for the second addr must be 8 more than the first addr. */ | |
5519 | if (INTVAL (XEXP (addr2, 1)) != offset1 + 8) | |
5520 | return 0; | |
5521 | ||
5522 | /* All the tests passed. addr1 and addr2 are valid for lfq or stfq | |
5523 | instructions. */ | |
5524 | return 1; | |
5525 | } | |
9878760c RK |
5526 | \f |
5527 | /* Return the register class of a scratch register needed to copy IN into | |
5528 | or out of a register in CLASS in MODE. If it can be done directly, | |
5529 | NO_REGS is returned. */ | |
5530 | ||
5531 | enum reg_class | |
5532 | secondary_reload_class (class, mode, in) | |
5533 | enum reg_class class; | |
296b8152 | 5534 | enum machine_mode mode ATTRIBUTE_UNUSED; |
9878760c RK |
5535 | rtx in; |
5536 | { | |
5accd822 | 5537 | int regno; |
9878760c | 5538 | |
46fad5b7 DJ |
5539 | if (TARGET_ELF || (DEFAULT_ABI == ABI_DARWIN && flag_pic)) |
5540 | { | |
5541 | /* We cannot copy a symbolic operand directly into anything | |
5542 | other than BASE_REGS for TARGET_ELF. So indicate that a | |
5543 | register from BASE_REGS is needed as an intermediate | |
5544 | register. | |
5545 | ||
5546 | On Darwin, pic addresses require a load from memory, which | |
5547 | needs a base register. */ | |
5548 | if (class != BASE_REGS | |
5549 | && (GET_CODE (in) == SYMBOL_REF | |
5550 | || GET_CODE (in) == HIGH | |
5551 | || GET_CODE (in) == LABEL_REF | |
5552 | || GET_CODE (in) == CONST)) | |
5553 | return BASE_REGS; | |
5554 | } | |
e7b7998a | 5555 | |
5accd822 DE |
5556 | if (GET_CODE (in) == REG) |
5557 | { | |
5558 | regno = REGNO (in); | |
5559 | if (regno >= FIRST_PSEUDO_REGISTER) | |
5560 | { | |
5561 | regno = true_regnum (in); | |
5562 | if (regno >= FIRST_PSEUDO_REGISTER) | |
5563 | regno = -1; | |
5564 | } | |
5565 | } | |
5566 | else if (GET_CODE (in) == SUBREG) | |
5567 | { | |
5568 | regno = true_regnum (in); | |
5569 | if (regno >= FIRST_PSEUDO_REGISTER) | |
5570 | regno = -1; | |
5571 | } | |
5572 | else | |
5573 | regno = -1; | |
5574 | ||
9878760c RK |
5575 | /* We can place anything into GENERAL_REGS and can put GENERAL_REGS |
5576 | into anything. */ | |
5577 | if (class == GENERAL_REGS || class == BASE_REGS | |
5578 | || (regno >= 0 && INT_REGNO_P (regno))) | |
5579 | return NO_REGS; | |
5580 | ||
5581 | /* Constants, memory, and FP registers can go into FP registers. */ | |
5582 | if ((regno == -1 || FP_REGNO_P (regno)) | |
5583 | && (class == FLOAT_REGS || class == NON_SPECIAL_REGS)) | |
5584 | return NO_REGS; | |
5585 | ||
0ac081f6 AH |
5586 | /* Memory, and AltiVec registers can go into AltiVec registers. */ |
5587 | if ((regno == -1 || ALTIVEC_REGNO_P (regno)) | |
5588 | && class == ALTIVEC_REGS) | |
5589 | return NO_REGS; | |
5590 | ||
9878760c RK |
5591 | /* We can copy among the CR registers. */ |
5592 | if ((class == CR_REGS || class == CR0_REGS) | |
5593 | && regno >= 0 && CR_REGNO_P (regno)) | |
5594 | return NO_REGS; | |
5595 | ||
5596 | /* Otherwise, we need GENERAL_REGS. */ | |
5597 | return GENERAL_REGS; | |
5598 | } | |
5599 | \f | |
5600 | /* Given a comparison operation, return the bit number in CCR to test. We | |
5601 | know this is a valid comparison. | |
5602 | ||
5603 | SCC_P is 1 if this is for an scc. That means that %D will have been | |
5604 | used instead of %C, so the bits will be in different places. | |
5605 | ||
b4ac57ab | 5606 | Return -1 if OP isn't a valid comparison for some reason. */ |
9878760c RK |
5607 | |
5608 | int | |
5609 | ccr_bit (op, scc_p) | |
592696dd | 5610 | rtx op; |
9878760c RK |
5611 | int scc_p; |
5612 | { | |
5613 | enum rtx_code code = GET_CODE (op); | |
5614 | enum machine_mode cc_mode; | |
5615 | int cc_regnum; | |
5616 | int base_bit; | |
9ebbca7d | 5617 | rtx reg; |
9878760c RK |
5618 | |
5619 | if (GET_RTX_CLASS (code) != '<') | |
5620 | return -1; | |
5621 | ||
9ebbca7d GK |
5622 | reg = XEXP (op, 0); |
5623 | ||
5624 | if (GET_CODE (reg) != REG | |
5625 | || ! CR_REGNO_P (REGNO (reg))) | |
5626 | abort (); | |
5627 | ||
5628 | cc_mode = GET_MODE (reg); | |
5629 | cc_regnum = REGNO (reg); | |
5630 | base_bit = 4 * (cc_regnum - CR0_REGNO); | |
9878760c | 5631 | |
39a10a29 | 5632 | validate_condition_mode (code, cc_mode); |
c5defebb | 5633 | |
9878760c RK |
5634 | switch (code) |
5635 | { | |
5636 | case NE: | |
5637 | return scc_p ? base_bit + 3 : base_bit + 2; | |
5638 | case EQ: | |
5639 | return base_bit + 2; | |
1c882ea4 | 5640 | case GT: case GTU: case UNLE: |
9878760c | 5641 | return base_bit + 1; |
1c882ea4 | 5642 | case LT: case LTU: case UNGE: |
9878760c | 5643 | return base_bit; |
1c882ea4 GK |
5644 | case ORDERED: case UNORDERED: |
5645 | return base_bit + 3; | |
9878760c RK |
5646 | |
5647 | case GE: case GEU: | |
39a10a29 | 5648 | /* If scc, we will have done a cror to put the bit in the |
9878760c RK |
5649 | unordered position. So test that bit. For integer, this is ! LT |
5650 | unless this is an scc insn. */ | |
39a10a29 | 5651 | return scc_p ? base_bit + 3 : base_bit; |
9878760c RK |
5652 | |
5653 | case LE: case LEU: | |
39a10a29 | 5654 | return scc_p ? base_bit + 3 : base_bit + 1; |
1c882ea4 | 5655 | |
9878760c RK |
5656 | default: |
5657 | abort (); | |
5658 | } | |
5659 | } | |
1ff7789b | 5660 | \f |
8d30c4ee | 5661 | /* Return the GOT register. */ |
1ff7789b MM |
5662 | |
5663 | struct rtx_def * | |
5664 | rs6000_got_register (value) | |
5f59ecb7 | 5665 | rtx value ATTRIBUTE_UNUSED; |
1ff7789b | 5666 | { |
a4f6c312 SS |
5667 | /* The second flow pass currently (June 1999) can't update |
5668 | regs_ever_live without disturbing other parts of the compiler, so | |
5669 | update it here to make the prolog/epilogue code happy. */ | |
3cb999d8 | 5670 | if (no_new_pseudos && ! regs_ever_live[PIC_OFFSET_TABLE_REGNUM]) |
8d30c4ee | 5671 | regs_ever_live[PIC_OFFSET_TABLE_REGNUM] = 1; |
1ff7789b | 5672 | |
8d30c4ee | 5673 | current_function_uses_pic_offset_table = 1; |
3cb999d8 | 5674 | |
1ff7789b MM |
5675 | return pic_offset_table_rtx; |
5676 | } | |
a7df97e6 | 5677 | \f |
71f123ca | 5678 | /* Functions to init, mark and free struct machine_function. |
a7df97e6 MM |
5679 | These will be called, via pointer variables, |
5680 | from push_function_context and pop_function_context. */ | |
5681 | ||
00dba523 NC |
5682 | static void |
5683 | rs6000_init_machine_status (p) | |
a7df97e6 MM |
5684 | struct function *p; |
5685 | { | |
71f123ca FS |
5686 | p->machine = (machine_function *) xcalloc (1, sizeof (machine_function)); |
5687 | } | |
a7df97e6 | 5688 | |
00dba523 NC |
5689 | static void |
5690 | rs6000_free_machine_status (p) | |
a7df97e6 MM |
5691 | struct function *p; |
5692 | { | |
00dba523 NC |
5693 | if (p->machine == NULL) |
5694 | return; | |
a7df97e6 | 5695 | |
00dba523 NC |
5696 | free (p->machine); |
5697 | p->machine = NULL; | |
a7df97e6 MM |
5698 | } |
5699 | ||
9878760c RK |
5700 | \f |
5701 | /* Print an operand. Recognize special options, documented below. */ | |
5702 | ||
38c1f2d7 | 5703 | #if TARGET_ELF |
d9407988 | 5704 | #define SMALL_DATA_RELOC ((rs6000_sdata == SDATA_EABI) ? "sda21" : "sdarel") |
8fbd2dc7 | 5705 | #define SMALL_DATA_REG ((rs6000_sdata == SDATA_EABI) ? 0 : 13) |
ba5e43aa MM |
5706 | #else |
5707 | #define SMALL_DATA_RELOC "sda21" | |
8fbd2dc7 | 5708 | #define SMALL_DATA_REG 0 |
ba5e43aa MM |
5709 | #endif |
5710 | ||
9878760c RK |
5711 | void |
5712 | print_operand (file, x, code) | |
5713 | FILE *file; | |
5714 | rtx x; | |
9ebbca7d | 5715 | int code; |
9878760c RK |
5716 | { |
5717 | int i; | |
a260abc9 | 5718 | HOST_WIDE_INT val; |
9878760c RK |
5719 | |
5720 | /* These macros test for integers and extract the low-order bits. */ | |
5721 | #define INT_P(X) \ | |
5722 | ((GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST_DOUBLE) \ | |
5723 | && GET_MODE (X) == VOIDmode) | |
5724 | ||
5725 | #define INT_LOWPART(X) \ | |
5726 | (GET_CODE (X) == CONST_INT ? INTVAL (X) : CONST_DOUBLE_LOW (X)) | |
5727 | ||
5728 | switch (code) | |
5729 | { | |
a8b3aeda | 5730 | case '.': |
a85d226b RK |
5731 | /* Write out an instruction after the call which may be replaced |
5732 | with glue code by the loader. This depends on the AIX version. */ | |
5733 | asm_fprintf (file, RS6000_CALL_GLUE); | |
a8b3aeda RK |
5734 | return; |
5735 | ||
81eace42 GK |
5736 | /* %a is output_address. */ |
5737 | ||
9854d9ed RK |
5738 | case 'A': |
5739 | /* If X is a constant integer whose low-order 5 bits are zero, | |
5740 | write 'l'. Otherwise, write 'r'. This is a kludge to fix a bug | |
76229ac8 | 5741 | in the AIX assembler where "sri" with a zero shift count |
20e26713 | 5742 | writes a trash instruction. */ |
9854d9ed | 5743 | if (GET_CODE (x) == CONST_INT && (INTVAL (x) & 31) == 0) |
76229ac8 | 5744 | putc ('l', file); |
9854d9ed | 5745 | else |
76229ac8 | 5746 | putc ('r', file); |
9854d9ed RK |
5747 | return; |
5748 | ||
5749 | case 'b': | |
e2c953b6 DE |
5750 | /* If constant, low-order 16 bits of constant, unsigned. |
5751 | Otherwise, write normally. */ | |
5752 | if (INT_P (x)) | |
5753 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 0xffff); | |
5754 | else | |
5755 | print_operand (file, x, 0); | |
cad12a8d RK |
5756 | return; |
5757 | ||
a260abc9 DE |
5758 | case 'B': |
5759 | /* If the low-order bit is zero, write 'r'; otherwise, write 'l' | |
5760 | for 64-bit mask direction. */ | |
296b8152 | 5761 | putc (((INT_LOWPART(x) & 1) == 0 ? 'r' : 'l'), file); |
a238cd8b | 5762 | return; |
a260abc9 | 5763 | |
81eace42 GK |
5764 | /* %c is output_addr_const if a CONSTANT_ADDRESS_P, otherwise |
5765 | output_operand. */ | |
5766 | ||
9854d9ed | 5767 | case 'D': |
39a10a29 GK |
5768 | /* There used to be a comment for 'C' reading "This is an |
5769 | optional cror needed for certain floating-point | |
5770 | comparisons. Otherwise write nothing." */ | |
5771 | ||
9854d9ed RK |
5772 | /* Similar, except that this is for an scc, so we must be able to |
5773 | encode the test in a single bit that is one. We do the above | |
5774 | for any LE, GE, GEU, or LEU and invert the bit for NE. */ | |
5775 | if (GET_CODE (x) == LE || GET_CODE (x) == GE | |
5776 | || GET_CODE (x) == LEU || GET_CODE (x) == GEU) | |
5777 | { | |
9ebbca7d | 5778 | int base_bit = 4 * (REGNO (XEXP (x, 0)) - CR0_REGNO); |
9854d9ed RK |
5779 | |
5780 | fprintf (file, "cror %d,%d,%d\n\t", base_bit + 3, | |
5781 | base_bit + 2, | |
5782 | base_bit + (GET_CODE (x) == GE || GET_CODE (x) == GEU)); | |
5783 | } | |
5784 | ||
5785 | else if (GET_CODE (x) == NE) | |
5786 | { | |
9ebbca7d | 5787 | int base_bit = 4 * (REGNO (XEXP (x, 0)) - CR0_REGNO); |
9854d9ed RK |
5788 | |
5789 | fprintf (file, "crnor %d,%d,%d\n\t", base_bit + 3, | |
5790 | base_bit + 2, base_bit + 2); | |
5791 | } | |
5792 | return; | |
5793 | ||
5794 | case 'E': | |
39a10a29 | 5795 | /* X is a CR register. Print the number of the EQ bit of the CR */ |
9854d9ed RK |
5796 | if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x))) |
5797 | output_operand_lossage ("invalid %%E value"); | |
78fbdbf7 | 5798 | else |
39a10a29 | 5799 | fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO) + 2); |
a85d226b | 5800 | return; |
9854d9ed RK |
5801 | |
5802 | case 'f': | |
5803 | /* X is a CR register. Print the shift count needed to move it | |
5804 | to the high-order four bits. */ | |
5805 | if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x))) | |
5806 | output_operand_lossage ("invalid %%f value"); | |
5807 | else | |
9ebbca7d | 5808 | fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO)); |
9854d9ed RK |
5809 | return; |
5810 | ||
5811 | case 'F': | |
5812 | /* Similar, but print the count for the rotate in the opposite | |
5813 | direction. */ | |
5814 | if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x))) | |
5815 | output_operand_lossage ("invalid %%F value"); | |
5816 | else | |
9ebbca7d | 5817 | fprintf (file, "%d", 32 - 4 * (REGNO (x) - CR0_REGNO)); |
9854d9ed RK |
5818 | return; |
5819 | ||
5820 | case 'G': | |
5821 | /* X is a constant integer. If it is negative, print "m", | |
5822 | otherwise print "z". This is to make a aze or ame insn. */ | |
5823 | if (GET_CODE (x) != CONST_INT) | |
5824 | output_operand_lossage ("invalid %%G value"); | |
5825 | else if (INTVAL (x) >= 0) | |
76229ac8 | 5826 | putc ('z', file); |
9854d9ed | 5827 | else |
76229ac8 | 5828 | putc ('m', file); |
9854d9ed | 5829 | return; |
e2c953b6 | 5830 | |
9878760c | 5831 | case 'h': |
a4f6c312 SS |
5832 | /* If constant, output low-order five bits. Otherwise, write |
5833 | normally. */ | |
9878760c | 5834 | if (INT_P (x)) |
5f59ecb7 | 5835 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 31); |
9878760c RK |
5836 | else |
5837 | print_operand (file, x, 0); | |
5838 | return; | |
5839 | ||
64305719 | 5840 | case 'H': |
a4f6c312 SS |
5841 | /* If constant, output low-order six bits. Otherwise, write |
5842 | normally. */ | |
64305719 | 5843 | if (INT_P (x)) |
5f59ecb7 | 5844 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 63); |
64305719 DE |
5845 | else |
5846 | print_operand (file, x, 0); | |
5847 | return; | |
5848 | ||
9854d9ed RK |
5849 | case 'I': |
5850 | /* Print `i' if this is a constant, else nothing. */ | |
9878760c | 5851 | if (INT_P (x)) |
76229ac8 | 5852 | putc ('i', file); |
9878760c RK |
5853 | return; |
5854 | ||
9854d9ed RK |
5855 | case 'j': |
5856 | /* Write the bit number in CCR for jump. */ | |
5857 | i = ccr_bit (x, 0); | |
5858 | if (i == -1) | |
5859 | output_operand_lossage ("invalid %%j code"); | |
9878760c | 5860 | else |
9854d9ed | 5861 | fprintf (file, "%d", i); |
9878760c RK |
5862 | return; |
5863 | ||
9854d9ed RK |
5864 | case 'J': |
5865 | /* Similar, but add one for shift count in rlinm for scc and pass | |
5866 | scc flag to `ccr_bit'. */ | |
5867 | i = ccr_bit (x, 1); | |
5868 | if (i == -1) | |
5869 | output_operand_lossage ("invalid %%J code"); | |
5870 | else | |
a0466a68 RK |
5871 | /* If we want bit 31, write a shift count of zero, not 32. */ |
5872 | fprintf (file, "%d", i == 31 ? 0 : i + 1); | |
9878760c RK |
5873 | return; |
5874 | ||
9854d9ed RK |
5875 | case 'k': |
5876 | /* X must be a constant. Write the 1's complement of the | |
5877 | constant. */ | |
9878760c | 5878 | if (! INT_P (x)) |
9854d9ed | 5879 | output_operand_lossage ("invalid %%k value"); |
e2c953b6 DE |
5880 | else |
5881 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, ~ INT_LOWPART (x)); | |
9878760c RK |
5882 | return; |
5883 | ||
81eace42 | 5884 | case 'K': |
9ebbca7d GK |
5885 | /* X must be a symbolic constant on ELF. Write an |
5886 | expression suitable for an 'addi' that adds in the low 16 | |
5887 | bits of the MEM. */ | |
5888 | if (GET_CODE (x) != CONST) | |
5889 | { | |
5890 | print_operand_address (file, x); | |
5891 | fputs ("@l", file); | |
5892 | } | |
5893 | else | |
5894 | { | |
5895 | if (GET_CODE (XEXP (x, 0)) != PLUS | |
5896 | || (GET_CODE (XEXP (XEXP (x, 0), 0)) != SYMBOL_REF | |
5897 | && GET_CODE (XEXP (XEXP (x, 0), 0)) != LABEL_REF) | |
5898 | || GET_CODE (XEXP (XEXP (x, 0), 1)) != CONST_INT) | |
53cd5d6c | 5899 | output_operand_lossage ("invalid %%K value"); |
9ebbca7d GK |
5900 | print_operand_address (file, XEXP (XEXP (x, 0), 0)); |
5901 | fputs ("@l", file); | |
5902 | print_operand (file, XEXP (XEXP (x, 0), 1), 0); | |
5903 | } | |
81eace42 GK |
5904 | return; |
5905 | ||
5906 | /* %l is output_asm_label. */ | |
9ebbca7d | 5907 | |
9854d9ed RK |
5908 | case 'L': |
5909 | /* Write second word of DImode or DFmode reference. Works on register | |
5910 | or non-indexed memory only. */ | |
5911 | if (GET_CODE (x) == REG) | |
5ebfb2ba | 5912 | fprintf (file, "%s", reg_names[REGNO (x) + 1]); |
9854d9ed RK |
5913 | else if (GET_CODE (x) == MEM) |
5914 | { | |
5915 | /* Handle possible auto-increment. Since it is pre-increment and | |
1427100a | 5916 | we have already done it, we can just use an offset of word. */ |
9854d9ed RK |
5917 | if (GET_CODE (XEXP (x, 0)) == PRE_INC |
5918 | || GET_CODE (XEXP (x, 0)) == PRE_DEC) | |
ed8908e7 RK |
5919 | output_address (plus_constant (XEXP (XEXP (x, 0), 0), |
5920 | UNITS_PER_WORD)); | |
9854d9ed | 5921 | else |
d7624dc0 RK |
5922 | output_address (XEXP (adjust_address_nv (x, SImode, |
5923 | UNITS_PER_WORD), | |
5924 | 0)); | |
ed8908e7 | 5925 | |
ba5e43aa | 5926 | if (small_data_operand (x, GET_MODE (x))) |
8fbd2dc7 MM |
5927 | fprintf (file, "@%s(%s)", SMALL_DATA_RELOC, |
5928 | reg_names[SMALL_DATA_REG]); | |
9854d9ed | 5929 | } |
9878760c | 5930 | return; |
9854d9ed | 5931 | |
9878760c RK |
5932 | case 'm': |
5933 | /* MB value for a mask operand. */ | |
5934 | if (! mask_operand (x, VOIDmode)) | |
5935 | output_operand_lossage ("invalid %%m value"); | |
5936 | ||
5937 | val = INT_LOWPART (x); | |
5938 | ||
5939 | /* If the high bit is set and the low bit is not, the value is zero. | |
5940 | If the high bit is zero, the value is the first 1 bit we find from | |
5941 | the left. */ | |
0858c623 | 5942 | if ((val & 0x80000000) && ((val & 1) == 0)) |
9878760c | 5943 | { |
19d2d16f | 5944 | putc ('0', file); |
9878760c RK |
5945 | return; |
5946 | } | |
0858c623 | 5947 | else if ((val & 0x80000000) == 0) |
9878760c RK |
5948 | { |
5949 | for (i = 1; i < 32; i++) | |
0858c623 | 5950 | if ((val <<= 1) & 0x80000000) |
9878760c RK |
5951 | break; |
5952 | fprintf (file, "%d", i); | |
5953 | return; | |
5954 | } | |
5955 | ||
5956 | /* Otherwise, look for the first 0 bit from the right. The result is its | |
5957 | number plus 1. We know the low-order bit is one. */ | |
5958 | for (i = 0; i < 32; i++) | |
5959 | if (((val >>= 1) & 1) == 0) | |
5960 | break; | |
5961 | ||
a260abc9 | 5962 | /* If we ended in ...01, i would be 0. The correct value is 31, so |
9878760c RK |
5963 | we want 31 - i. */ |
5964 | fprintf (file, "%d", 31 - i); | |
5965 | return; | |
5966 | ||
5967 | case 'M': | |
5968 | /* ME value for a mask operand. */ | |
5969 | if (! mask_operand (x, VOIDmode)) | |
a260abc9 | 5970 | output_operand_lossage ("invalid %%M value"); |
9878760c RK |
5971 | |
5972 | val = INT_LOWPART (x); | |
5973 | ||
5974 | /* If the low bit is set and the high bit is not, the value is 31. | |
5975 | If the low bit is zero, the value is the first 1 bit we find from | |
5976 | the right. */ | |
0858c623 | 5977 | if ((val & 1) && ((val & 0x80000000) == 0)) |
9878760c | 5978 | { |
76229ac8 | 5979 | fputs ("31", file); |
9878760c RK |
5980 | return; |
5981 | } | |
5982 | else if ((val & 1) == 0) | |
5983 | { | |
5984 | for (i = 0; i < 32; i++) | |
5985 | if ((val >>= 1) & 1) | |
5986 | break; | |
5987 | ||
a260abc9 | 5988 | /* If we had ....10, i would be 0. The result should be |
9878760c RK |
5989 | 30, so we need 30 - i. */ |
5990 | fprintf (file, "%d", 30 - i); | |
5991 | return; | |
5992 | } | |
5993 | ||
5994 | /* Otherwise, look for the first 0 bit from the left. The result is its | |
5995 | number minus 1. We know the high-order bit is one. */ | |
5996 | for (i = 0; i < 32; i++) | |
0858c623 | 5997 | if (((val <<= 1) & 0x80000000) == 0) |
9878760c RK |
5998 | break; |
5999 | ||
6000 | fprintf (file, "%d", i); | |
6001 | return; | |
6002 | ||
81eace42 GK |
6003 | /* %n outputs the negative of its operand. */ |
6004 | ||
9878760c RK |
6005 | case 'N': |
6006 | /* Write the number of elements in the vector times 4. */ | |
6007 | if (GET_CODE (x) != PARALLEL) | |
6008 | output_operand_lossage ("invalid %%N value"); | |
e2c953b6 DE |
6009 | else |
6010 | fprintf (file, "%d", XVECLEN (x, 0) * 4); | |
9878760c RK |
6011 | return; |
6012 | ||
6013 | case 'O': | |
6014 | /* Similar, but subtract 1 first. */ | |
6015 | if (GET_CODE (x) != PARALLEL) | |
1427100a | 6016 | output_operand_lossage ("invalid %%O value"); |
e2c953b6 DE |
6017 | else |
6018 | fprintf (file, "%d", (XVECLEN (x, 0) - 1) * 4); | |
9878760c RK |
6019 | return; |
6020 | ||
9854d9ed RK |
6021 | case 'p': |
6022 | /* X is a CONST_INT that is a power of two. Output the logarithm. */ | |
6023 | if (! INT_P (x) | |
2bfcf297 | 6024 | || INT_LOWPART (x) < 0 |
9854d9ed RK |
6025 | || (i = exact_log2 (INT_LOWPART (x))) < 0) |
6026 | output_operand_lossage ("invalid %%p value"); | |
e2c953b6 DE |
6027 | else |
6028 | fprintf (file, "%d", i); | |
9854d9ed RK |
6029 | return; |
6030 | ||
9878760c RK |
6031 | case 'P': |
6032 | /* The operand must be an indirect memory reference. The result | |
a4f6c312 | 6033 | is the register number. */ |
9878760c RK |
6034 | if (GET_CODE (x) != MEM || GET_CODE (XEXP (x, 0)) != REG |
6035 | || REGNO (XEXP (x, 0)) >= 32) | |
6036 | output_operand_lossage ("invalid %%P value"); | |
e2c953b6 DE |
6037 | else |
6038 | fprintf (file, "%d", REGNO (XEXP (x, 0))); | |
9878760c RK |
6039 | return; |
6040 | ||
dfbdccdb GK |
6041 | case 'q': |
6042 | /* This outputs the logical code corresponding to a boolean | |
6043 | expression. The expression may have one or both operands | |
39a10a29 GK |
6044 | negated (if one, only the first one). For condition register |
6045 | logical operations, it will also treat the negated | |
6046 | CR codes as NOTs, but not handle NOTs of them. */ | |
dfbdccdb | 6047 | { |
63bc1d05 | 6048 | const char *const *t = 0; |
dfbdccdb GK |
6049 | const char *s; |
6050 | enum rtx_code code = GET_CODE (x); | |
6051 | static const char * const tbl[3][3] = { | |
6052 | { "and", "andc", "nor" }, | |
6053 | { "or", "orc", "nand" }, | |
6054 | { "xor", "eqv", "xor" } }; | |
6055 | ||
6056 | if (code == AND) | |
6057 | t = tbl[0]; | |
6058 | else if (code == IOR) | |
6059 | t = tbl[1]; | |
6060 | else if (code == XOR) | |
6061 | t = tbl[2]; | |
6062 | else | |
6063 | output_operand_lossage ("invalid %%q value"); | |
6064 | ||
6065 | if (GET_CODE (XEXP (x, 0)) != NOT) | |
6066 | s = t[0]; | |
6067 | else | |
6068 | { | |
6069 | if (GET_CODE (XEXP (x, 1)) == NOT) | |
6070 | s = t[2]; | |
6071 | else | |
6072 | s = t[1]; | |
6073 | } | |
6074 | ||
6075 | fputs (s, file); | |
6076 | } | |
6077 | return; | |
6078 | ||
9854d9ed RK |
6079 | case 'R': |
6080 | /* X is a CR register. Print the mask for `mtcrf'. */ | |
6081 | if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x))) | |
6082 | output_operand_lossage ("invalid %%R value"); | |
6083 | else | |
9ebbca7d | 6084 | fprintf (file, "%d", 128 >> (REGNO (x) - CR0_REGNO)); |
9878760c | 6085 | return; |
9854d9ed RK |
6086 | |
6087 | case 's': | |
6088 | /* Low 5 bits of 32 - value */ | |
6089 | if (! INT_P (x)) | |
6090 | output_operand_lossage ("invalid %%s value"); | |
e2c953b6 DE |
6091 | else |
6092 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, (32 - INT_LOWPART (x)) & 31); | |
9878760c | 6093 | return; |
9854d9ed | 6094 | |
a260abc9 DE |
6095 | case 'S': |
6096 | /* PowerPC64 mask position. All 0's and all 1's are excluded. | |
6097 | CONST_INT 32-bit mask is considered sign-extended so any | |
6098 | transition must occur within the CONST_INT, not on the boundary. */ | |
6099 | if (! mask64_operand (x, VOIDmode)) | |
6100 | output_operand_lossage ("invalid %%S value"); | |
6101 | ||
6102 | val = INT_LOWPART (x); | |
6103 | ||
6104 | if (val & 1) /* Clear Left */ | |
6105 | { | |
a238cd8b DE |
6106 | for (i = 0; i < HOST_BITS_PER_WIDE_INT; i++) |
6107 | if (!((val >>= 1) & 1)) | |
6108 | break; | |
a260abc9 | 6109 | |
a238cd8b DE |
6110 | #if HOST_BITS_PER_WIDE_INT == 32 |
6111 | if (GET_CODE (x) == CONST_DOUBLE && i == 32) | |
6112 | { | |
6113 | val = CONST_DOUBLE_HIGH (x); | |
6114 | ||
6115 | if (val == 0) | |
6116 | --i; | |
6117 | else | |
6118 | for (i = 32; i < 64; i++) | |
6119 | if (!((val >>= 1) & 1)) | |
6120 | break; | |
6121 | } | |
a260abc9 | 6122 | #endif |
a238cd8b DE |
6123 | /* i = index of last set bit from right |
6124 | mask begins at 63 - i from left */ | |
6125 | if (i > 63) | |
6126 | output_operand_lossage ("%%S computed all 1's mask"); | |
cccf3bdc | 6127 | |
a260abc9 DE |
6128 | fprintf (file, "%d", 63 - i); |
6129 | return; | |
6130 | } | |
6131 | else /* Clear Right */ | |
6132 | { | |
a238cd8b DE |
6133 | for (i = 0; i < HOST_BITS_PER_WIDE_INT; i++) |
6134 | if ((val >>= 1) & 1) | |
6135 | break; | |
a260abc9 | 6136 | |
a238cd8b | 6137 | #if HOST_BITS_PER_WIDE_INT == 32 |
a260abc9 DE |
6138 | if (GET_CODE (x) == CONST_DOUBLE && i == 32) |
6139 | { | |
a238cd8b | 6140 | val = CONST_DOUBLE_HIGH (x); |
a260abc9 | 6141 | |
a238cd8b | 6142 | if (val == (HOST_WIDE_INT) -1) |
a260abc9 | 6143 | --i; |
a260abc9 | 6144 | else |
a238cd8b DE |
6145 | for (i = 32; i < 64; i++) |
6146 | if ((val >>= 1) & 1) | |
a260abc9 DE |
6147 | break; |
6148 | } | |
6149 | #endif | |
a238cd8b DE |
6150 | /* i = index of last clear bit from right |
6151 | mask ends at 62 - i from left */ | |
6152 | if (i > 62) | |
6153 | output_operand_lossage ("%%S computed all 0's mask"); | |
cccf3bdc | 6154 | |
a238cd8b | 6155 | fprintf (file, "%d", 62 - i); |
a260abc9 DE |
6156 | return; |
6157 | } | |
6158 | ||
cccf3bdc DE |
6159 | case 'T': |
6160 | /* Print the symbolic name of a branch target register. */ | |
6161 | if (GET_CODE (x) != REG || (REGNO (x) != LINK_REGISTER_REGNUM | |
6162 | && REGNO (x) != COUNT_REGISTER_REGNUM)) | |
6163 | output_operand_lossage ("invalid %%T value"); | |
e2c953b6 | 6164 | else if (REGNO (x) == LINK_REGISTER_REGNUM) |
cccf3bdc DE |
6165 | fputs (TARGET_NEW_MNEMONICS ? "lr" : "r", file); |
6166 | else | |
6167 | fputs ("ctr", file); | |
6168 | return; | |
6169 | ||
9854d9ed | 6170 | case 'u': |
802a0058 | 6171 | /* High-order 16 bits of constant for use in unsigned operand. */ |
9854d9ed RK |
6172 | if (! INT_P (x)) |
6173 | output_operand_lossage ("invalid %%u value"); | |
e2c953b6 DE |
6174 | else |
6175 | fprintf (file, HOST_WIDE_INT_PRINT_HEX, | |
6176 | (INT_LOWPART (x) >> 16) & 0xffff); | |
9878760c RK |
6177 | return; |
6178 | ||
802a0058 MM |
6179 | case 'v': |
6180 | /* High-order 16 bits of constant for use in signed operand. */ | |
6181 | if (! INT_P (x)) | |
6182 | output_operand_lossage ("invalid %%v value"); | |
e2c953b6 | 6183 | else |
134c32f6 DE |
6184 | fprintf (file, HOST_WIDE_INT_PRINT_HEX, |
6185 | (INT_LOWPART (x) >> 16) & 0xffff); | |
6186 | return; | |
802a0058 | 6187 | |
9854d9ed RK |
6188 | case 'U': |
6189 | /* Print `u' if this has an auto-increment or auto-decrement. */ | |
6190 | if (GET_CODE (x) == MEM | |
6191 | && (GET_CODE (XEXP (x, 0)) == PRE_INC | |
6192 | || GET_CODE (XEXP (x, 0)) == PRE_DEC)) | |
76229ac8 | 6193 | putc ('u', file); |
9854d9ed | 6194 | return; |
9878760c | 6195 | |
e0cd0770 JC |
6196 | case 'V': |
6197 | /* Print the trap code for this operand. */ | |
6198 | switch (GET_CODE (x)) | |
6199 | { | |
6200 | case EQ: | |
6201 | fputs ("eq", file); /* 4 */ | |
6202 | break; | |
6203 | case NE: | |
6204 | fputs ("ne", file); /* 24 */ | |
6205 | break; | |
6206 | case LT: | |
6207 | fputs ("lt", file); /* 16 */ | |
6208 | break; | |
6209 | case LE: | |
6210 | fputs ("le", file); /* 20 */ | |
6211 | break; | |
6212 | case GT: | |
6213 | fputs ("gt", file); /* 8 */ | |
6214 | break; | |
6215 | case GE: | |
6216 | fputs ("ge", file); /* 12 */ | |
6217 | break; | |
6218 | case LTU: | |
6219 | fputs ("llt", file); /* 2 */ | |
6220 | break; | |
6221 | case LEU: | |
6222 | fputs ("lle", file); /* 6 */ | |
6223 | break; | |
6224 | case GTU: | |
6225 | fputs ("lgt", file); /* 1 */ | |
6226 | break; | |
6227 | case GEU: | |
6228 | fputs ("lge", file); /* 5 */ | |
6229 | break; | |
6230 | default: | |
6231 | abort (); | |
6232 | } | |
6233 | break; | |
6234 | ||
9854d9ed RK |
6235 | case 'w': |
6236 | /* If constant, low-order 16 bits of constant, signed. Otherwise, write | |
6237 | normally. */ | |
6238 | if (INT_P (x)) | |
5f59ecb7 DE |
6239 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, |
6240 | ((INT_LOWPART (x) & 0xffff) ^ 0x8000) - 0x8000); | |
9854d9ed RK |
6241 | else |
6242 | print_operand (file, x, 0); | |
9878760c RK |
6243 | return; |
6244 | ||
9854d9ed | 6245 | case 'W': |
e2c953b6 | 6246 | /* MB value for a PowerPC64 rldic operand. */ |
e2c953b6 DE |
6247 | val = (GET_CODE (x) == CONST_INT |
6248 | ? INTVAL (x) : CONST_DOUBLE_HIGH (x)); | |
6249 | ||
6250 | if (val < 0) | |
6251 | i = -1; | |
9854d9ed | 6252 | else |
e2c953b6 DE |
6253 | for (i = 0; i < HOST_BITS_PER_WIDE_INT; i++) |
6254 | if ((val <<= 1) < 0) | |
6255 | break; | |
6256 | ||
6257 | #if HOST_BITS_PER_WIDE_INT == 32 | |
6258 | if (GET_CODE (x) == CONST_INT && i >= 0) | |
6259 | i += 32; /* zero-extend high-part was all 0's */ | |
6260 | else if (GET_CODE (x) == CONST_DOUBLE && i == 32) | |
6261 | { | |
6262 | val = CONST_DOUBLE_LOW (x); | |
6263 | ||
6264 | if (val == 0) | |
a4f6c312 | 6265 | abort (); |
e2c953b6 DE |
6266 | else if (val < 0) |
6267 | --i; | |
6268 | else | |
6269 | for ( ; i < 64; i++) | |
6270 | if ((val <<= 1) < 0) | |
6271 | break; | |
6272 | } | |
6273 | #endif | |
6274 | ||
6275 | fprintf (file, "%d", i + 1); | |
9854d9ed | 6276 | return; |
9878760c | 6277 | |
9854d9ed RK |
6278 | case 'X': |
6279 | if (GET_CODE (x) == MEM | |
258bfae2 | 6280 | && LEGITIMATE_INDEXED_ADDRESS_P (XEXP (x, 0), 0)) |
76229ac8 | 6281 | putc ('x', file); |
9854d9ed | 6282 | return; |
9878760c | 6283 | |
9854d9ed RK |
6284 | case 'Y': |
6285 | /* Like 'L', for third word of TImode */ | |
6286 | if (GET_CODE (x) == REG) | |
5ebfb2ba | 6287 | fprintf (file, "%s", reg_names[REGNO (x) + 2]); |
9854d9ed | 6288 | else if (GET_CODE (x) == MEM) |
9878760c | 6289 | { |
9854d9ed RK |
6290 | if (GET_CODE (XEXP (x, 0)) == PRE_INC |
6291 | || GET_CODE (XEXP (x, 0)) == PRE_DEC) | |
a54d04b7 | 6292 | output_address (plus_constant (XEXP (XEXP (x, 0), 0), 8)); |
9854d9ed | 6293 | else |
d7624dc0 | 6294 | output_address (XEXP (adjust_address_nv (x, SImode, 8), 0)); |
ba5e43aa | 6295 | if (small_data_operand (x, GET_MODE (x))) |
8fbd2dc7 MM |
6296 | fprintf (file, "@%s(%s)", SMALL_DATA_RELOC, |
6297 | reg_names[SMALL_DATA_REG]); | |
9878760c RK |
6298 | } |
6299 | return; | |
9854d9ed | 6300 | |
9878760c | 6301 | case 'z': |
b4ac57ab RS |
6302 | /* X is a SYMBOL_REF. Write out the name preceded by a |
6303 | period and without any trailing data in brackets. Used for function | |
4d30c363 MM |
6304 | names. If we are configured for System V (or the embedded ABI) on |
6305 | the PowerPC, do not emit the period, since those systems do not use | |
6306 | TOCs and the like. */ | |
9878760c RK |
6307 | if (GET_CODE (x) != SYMBOL_REF) |
6308 | abort (); | |
6309 | ||
b6c9286a MM |
6310 | if (XSTR (x, 0)[0] != '.') |
6311 | { | |
6312 | switch (DEFAULT_ABI) | |
6313 | { | |
6314 | default: | |
6315 | abort (); | |
6316 | ||
6317 | case ABI_AIX: | |
6318 | putc ('.', file); | |
6319 | break; | |
6320 | ||
6321 | case ABI_V4: | |
6322 | case ABI_AIX_NODESC: | |
ee890fe2 | 6323 | case ABI_DARWIN: |
b6c9286a | 6324 | break; |
b6c9286a MM |
6325 | } |
6326 | } | |
54ee9799 DE |
6327 | #if TARGET_AIX |
6328 | RS6000_OUTPUT_BASENAME (file, XSTR (x, 0)); | |
6329 | #else | |
9ebbca7d | 6330 | assemble_name (file, XSTR (x, 0)); |
54ee9799 | 6331 | #endif |
9878760c RK |
6332 | return; |
6333 | ||
9854d9ed RK |
6334 | case 'Z': |
6335 | /* Like 'L', for last word of TImode. */ | |
6336 | if (GET_CODE (x) == REG) | |
5ebfb2ba | 6337 | fprintf (file, "%s", reg_names[REGNO (x) + 3]); |
9854d9ed RK |
6338 | else if (GET_CODE (x) == MEM) |
6339 | { | |
6340 | if (GET_CODE (XEXP (x, 0)) == PRE_INC | |
6341 | || GET_CODE (XEXP (x, 0)) == PRE_DEC) | |
a54d04b7 | 6342 | output_address (plus_constant (XEXP (XEXP (x, 0), 0), 12)); |
9854d9ed | 6343 | else |
d7624dc0 | 6344 | output_address (XEXP (adjust_address_nv (x, SImode, 12), 0)); |
ba5e43aa | 6345 | if (small_data_operand (x, GET_MODE (x))) |
8fbd2dc7 MM |
6346 | fprintf (file, "@%s(%s)", SMALL_DATA_RELOC, |
6347 | reg_names[SMALL_DATA_REG]); | |
9854d9ed | 6348 | } |
5c23c401 | 6349 | return; |
0ac081f6 AH |
6350 | |
6351 | /* Print AltiVec memory operand. */ | |
6352 | case 'y': | |
6353 | { | |
6354 | rtx tmp; | |
6355 | ||
6356 | if (GET_CODE (x) != MEM) | |
6357 | abort (); | |
6358 | ||
6359 | tmp = XEXP (x, 0); | |
6360 | ||
6361 | if (GET_CODE (tmp) == REG) | |
c62f2db5 | 6362 | fprintf (file, "0,%s", reg_names[REGNO (tmp)]); |
0ac081f6 AH |
6363 | else if (GET_CODE (tmp) == PLUS && GET_CODE (XEXP (tmp, 1)) == REG) |
6364 | { | |
6365 | if (REGNO (XEXP (tmp, 0)) == 0) | |
6366 | fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 1)) ], | |
6367 | reg_names[ REGNO (XEXP (tmp, 0)) ]); | |
6368 | else | |
6369 | fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 0)) ], | |
6370 | reg_names[ REGNO (XEXP (tmp, 1)) ]); | |
6371 | } | |
6372 | else | |
6373 | abort (); | |
6374 | break; | |
6375 | } | |
9854d9ed | 6376 | |
9878760c RK |
6377 | case 0: |
6378 | if (GET_CODE (x) == REG) | |
6379 | fprintf (file, "%s", reg_names[REGNO (x)]); | |
6380 | else if (GET_CODE (x) == MEM) | |
6381 | { | |
6382 | /* We need to handle PRE_INC and PRE_DEC here, since we need to | |
6383 | know the width from the mode. */ | |
6384 | if (GET_CODE (XEXP (x, 0)) == PRE_INC) | |
79ba6d34 MM |
6385 | fprintf (file, "%d(%s)", GET_MODE_SIZE (GET_MODE (x)), |
6386 | reg_names[REGNO (XEXP (XEXP (x, 0), 0))]); | |
9878760c | 6387 | else if (GET_CODE (XEXP (x, 0)) == PRE_DEC) |
79ba6d34 MM |
6388 | fprintf (file, "%d(%s)", - GET_MODE_SIZE (GET_MODE (x)), |
6389 | reg_names[REGNO (XEXP (XEXP (x, 0), 0))]); | |
9878760c | 6390 | else |
a54d04b7 | 6391 | output_address (XEXP (x, 0)); |
9878760c RK |
6392 | } |
6393 | else | |
a54d04b7 | 6394 | output_addr_const (file, x); |
a85d226b | 6395 | return; |
9878760c RK |
6396 | |
6397 | default: | |
6398 | output_operand_lossage ("invalid %%xn code"); | |
6399 | } | |
6400 | } | |
6401 | \f | |
6402 | /* Print the address of an operand. */ | |
6403 | ||
6404 | void | |
6405 | print_operand_address (file, x) | |
6406 | FILE *file; | |
592696dd | 6407 | rtx x; |
9878760c RK |
6408 | { |
6409 | if (GET_CODE (x) == REG) | |
4697a36c | 6410 | fprintf (file, "0(%s)", reg_names[ REGNO (x) ]); |
9ebbca7d GK |
6411 | else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST |
6412 | || GET_CODE (x) == LABEL_REF) | |
9878760c RK |
6413 | { |
6414 | output_addr_const (file, x); | |
ba5e43aa | 6415 | if (small_data_operand (x, GET_MODE (x))) |
8fbd2dc7 MM |
6416 | fprintf (file, "@%s(%s)", SMALL_DATA_RELOC, |
6417 | reg_names[SMALL_DATA_REG]); | |
9ebbca7d | 6418 | else if (TARGET_TOC) |
a4f6c312 | 6419 | abort (); |
9878760c RK |
6420 | } |
6421 | else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == REG) | |
6422 | { | |
6423 | if (REGNO (XEXP (x, 0)) == 0) | |
4697a36c MM |
6424 | fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 1)) ], |
6425 | reg_names[ REGNO (XEXP (x, 0)) ]); | |
9878760c | 6426 | else |
4697a36c MM |
6427 | fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 0)) ], |
6428 | reg_names[ REGNO (XEXP (x, 1)) ]); | |
9878760c RK |
6429 | } |
6430 | else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT) | |
5f59ecb7 DE |
6431 | { |
6432 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (XEXP (x, 1))); | |
6433 | fprintf (file, "(%s)", reg_names[ REGNO (XEXP (x, 0)) ]); | |
6434 | } | |
3cb999d8 DE |
6435 | #if TARGET_ELF |
6436 | else if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 0)) == REG | |
6437 | && CONSTANT_P (XEXP (x, 1))) | |
4697a36c MM |
6438 | { |
6439 | output_addr_const (file, XEXP (x, 1)); | |
6440 | fprintf (file, "@l(%s)", reg_names[ REGNO (XEXP (x, 0)) ]); | |
6441 | } | |
c859cda6 DJ |
6442 | #endif |
6443 | #if TARGET_MACHO | |
6444 | else if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 0)) == REG | |
6445 | && CONSTANT_P (XEXP (x, 1))) | |
6446 | { | |
6447 | fprintf (file, "lo16("); | |
6448 | output_addr_const (file, XEXP (x, 1)); | |
6449 | fprintf (file, ")(%s)", reg_names[ REGNO (XEXP (x, 0)) ]); | |
6450 | } | |
3cb999d8 | 6451 | #endif |
9ebbca7d GK |
6452 | else if (LEGITIMATE_CONSTANT_POOL_ADDRESS_P (x)) |
6453 | { | |
2bfcf297 | 6454 | if (TARGET_AIX && (!TARGET_ELF || !TARGET_MINIMAL_TOC)) |
9ebbca7d | 6455 | { |
2bfcf297 DB |
6456 | rtx contains_minus = XEXP (x, 1); |
6457 | rtx minus, symref; | |
6458 | const char *name; | |
9ebbca7d GK |
6459 | |
6460 | /* Find the (minus (sym) (toc)) buried in X, and temporarily | |
a4f6c312 | 6461 | turn it into (sym) for output_addr_const. */ |
9ebbca7d GK |
6462 | while (GET_CODE (XEXP (contains_minus, 0)) != MINUS) |
6463 | contains_minus = XEXP (contains_minus, 0); | |
6464 | ||
2bfcf297 DB |
6465 | minus = XEXP (contains_minus, 0); |
6466 | symref = XEXP (minus, 0); | |
6467 | XEXP (contains_minus, 0) = symref; | |
6468 | if (TARGET_ELF) | |
6469 | { | |
6470 | char *newname; | |
6471 | ||
6472 | name = XSTR (symref, 0); | |
6473 | newname = alloca (strlen (name) + sizeof ("@toc")); | |
6474 | strcpy (newname, name); | |
6475 | strcat (newname, "@toc"); | |
6476 | XSTR (symref, 0) = newname; | |
6477 | } | |
6478 | output_addr_const (file, XEXP (x, 1)); | |
6479 | if (TARGET_ELF) | |
6480 | XSTR (symref, 0) = name; | |
9ebbca7d GK |
6481 | XEXP (contains_minus, 0) = minus; |
6482 | } | |
6483 | else | |
6484 | output_addr_const (file, XEXP (x, 1)); | |
6485 | ||
6486 | fprintf (file, "(%s)", reg_names[REGNO (XEXP (x, 0))]); | |
6487 | } | |
9878760c RK |
6488 | else |
6489 | abort (); | |
6490 | } | |
6491 | \f | |
301d03af RS |
6492 | /* Target hook for assembling integer objects. The powerpc version has |
6493 | to handle fixup entries for relocatable code if RELOCATABLE_NEEDS_FIXUP | |
6494 | is defined. It also needs to handle DI-mode objects on 64-bit | |
6495 | targets. */ | |
6496 | ||
6497 | static bool | |
6498 | rs6000_assemble_integer (x, size, aligned_p) | |
6499 | rtx x; | |
6500 | unsigned int size; | |
6501 | int aligned_p; | |
6502 | { | |
6503 | #ifdef RELOCATABLE_NEEDS_FIXUP | |
6504 | /* Special handling for SI values. */ | |
6505 | if (size == 4 && aligned_p) | |
6506 | { | |
6507 | extern int in_toc_section PARAMS ((void)); | |
6508 | static int recurse = 0; | |
6509 | ||
6510 | /* For -mrelocatable, we mark all addresses that need to be fixed up | |
6511 | in the .fixup section. */ | |
6512 | if (TARGET_RELOCATABLE | |
6513 | && !in_toc_section () | |
6514 | && !in_text_section () | |
6515 | && !recurse | |
6516 | && GET_CODE (x) != CONST_INT | |
6517 | && GET_CODE (x) != CONST_DOUBLE | |
6518 | && CONSTANT_P (x)) | |
6519 | { | |
6520 | char buf[256]; | |
6521 | ||
6522 | recurse = 1; | |
6523 | ASM_GENERATE_INTERNAL_LABEL (buf, "LCP", fixuplabelno); | |
6524 | fixuplabelno++; | |
6525 | ASM_OUTPUT_LABEL (asm_out_file, buf); | |
6526 | fprintf (asm_out_file, "\t.long\t("); | |
6527 | output_addr_const (asm_out_file, x); | |
6528 | fprintf (asm_out_file, ")@fixup\n"); | |
6529 | fprintf (asm_out_file, "\t.section\t\".fixup\",\"aw\"\n"); | |
6530 | ASM_OUTPUT_ALIGN (asm_out_file, 2); | |
6531 | fprintf (asm_out_file, "\t.long\t"); | |
6532 | assemble_name (asm_out_file, buf); | |
6533 | fprintf (asm_out_file, "\n\t.previous\n"); | |
6534 | recurse = 0; | |
6535 | return true; | |
6536 | } | |
6537 | /* Remove initial .'s to turn a -mcall-aixdesc function | |
6538 | address into the address of the descriptor, not the function | |
6539 | itself. */ | |
6540 | else if (GET_CODE (x) == SYMBOL_REF | |
6541 | && XSTR (x, 0)[0] == '.' | |
6542 | && DEFAULT_ABI == ABI_AIX) | |
6543 | { | |
6544 | const char *name = XSTR (x, 0); | |
6545 | while (*name == '.') | |
6546 | name++; | |
6547 | ||
6548 | fprintf (asm_out_file, "\t.long\t%s\n", name); | |
6549 | return true; | |
6550 | } | |
6551 | } | |
6552 | #endif /* RELOCATABLE_NEEDS_FIXUP */ | |
6553 | return default_assemble_integer (x, size, aligned_p); | |
6554 | } | |
6555 | \f | |
39a10a29 GK |
6556 | enum rtx_code |
6557 | rs6000_reverse_condition (mode, code) | |
6558 | enum machine_mode mode; | |
6559 | enum rtx_code code; | |
6560 | { | |
6561 | /* Reversal of FP compares takes care -- an ordered compare | |
6562 | becomes an unordered compare and vice versa. */ | |
6563 | if (mode == CCFPmode) | |
bab6226b | 6564 | return reverse_condition_maybe_unordered (code); |
39a10a29 | 6565 | else |
bab6226b | 6566 | return reverse_condition (code); |
39a10a29 GK |
6567 | } |
6568 | ||
39a10a29 GK |
6569 | /* Generate a compare for CODE. Return a brand-new rtx that |
6570 | represents the result of the compare. */ | |
a4f6c312 | 6571 | |
39a10a29 GK |
6572 | static rtx |
6573 | rs6000_generate_compare (code) | |
6574 | enum rtx_code code; | |
6575 | { | |
6576 | enum machine_mode comp_mode; | |
6577 | rtx compare_result; | |
6578 | ||
6579 | if (rs6000_compare_fp_p) | |
6580 | comp_mode = CCFPmode; | |
6581 | else if (code == GTU || code == LTU | |
6582 | || code == GEU || code == LEU) | |
6583 | comp_mode = CCUNSmode; | |
6584 | else | |
6585 | comp_mode = CCmode; | |
6586 | ||
6587 | /* First, the compare. */ | |
6588 | compare_result = gen_reg_rtx (comp_mode); | |
6589 | emit_insn (gen_rtx_SET (VOIDmode, compare_result, | |
6590 | gen_rtx_COMPARE (comp_mode, | |
6591 | rs6000_compare_op0, | |
6592 | rs6000_compare_op1))); | |
6593 | ||
ca5adc63 | 6594 | /* Some kinds of FP comparisons need an OR operation; |
de6c5979 | 6595 | except for flag_unsafe_math_optimizations we don't bother. */ |
39a10a29 | 6596 | if (rs6000_compare_fp_p |
de6c5979 | 6597 | && ! flag_unsafe_math_optimizations |
39a10a29 GK |
6598 | && (code == LE || code == GE |
6599 | || code == UNEQ || code == LTGT | |
6600 | || code == UNGT || code == UNLT)) | |
6601 | { | |
6602 | enum rtx_code or1, or2; | |
6603 | rtx or1_rtx, or2_rtx, compare2_rtx; | |
6604 | rtx or_result = gen_reg_rtx (CCEQmode); | |
6605 | ||
6606 | switch (code) | |
6607 | { | |
6608 | case LE: or1 = LT; or2 = EQ; break; | |
6609 | case GE: or1 = GT; or2 = EQ; break; | |
6610 | case UNEQ: or1 = UNORDERED; or2 = EQ; break; | |
6611 | case LTGT: or1 = LT; or2 = GT; break; | |
6612 | case UNGT: or1 = UNORDERED; or2 = GT; break; | |
6613 | case UNLT: or1 = UNORDERED; or2 = LT; break; | |
6614 | default: abort (); | |
6615 | } | |
6616 | validate_condition_mode (or1, comp_mode); | |
6617 | validate_condition_mode (or2, comp_mode); | |
6618 | or1_rtx = gen_rtx (or1, SImode, compare_result, const0_rtx); | |
6619 | or2_rtx = gen_rtx (or2, SImode, compare_result, const0_rtx); | |
6620 | compare2_rtx = gen_rtx_COMPARE (CCEQmode, | |
6621 | gen_rtx_IOR (SImode, or1_rtx, or2_rtx), | |
6622 | const_true_rtx); | |
6623 | emit_insn (gen_rtx_SET (VOIDmode, or_result, compare2_rtx)); | |
6624 | ||
6625 | compare_result = or_result; | |
6626 | code = EQ; | |
6627 | } | |
6628 | ||
6629 | validate_condition_mode (code, GET_MODE (compare_result)); | |
6630 | ||
6631 | return gen_rtx (code, VOIDmode, compare_result, const0_rtx); | |
6632 | } | |
6633 | ||
6634 | ||
6635 | /* Emit the RTL for an sCOND pattern. */ | |
6636 | ||
6637 | void | |
6638 | rs6000_emit_sCOND (code, result) | |
6639 | enum rtx_code code; | |
6640 | rtx result; | |
6641 | { | |
6642 | rtx condition_rtx; | |
6643 | enum machine_mode op_mode; | |
6644 | ||
6645 | condition_rtx = rs6000_generate_compare (code); | |
6646 | ||
6647 | op_mode = GET_MODE (rs6000_compare_op0); | |
6648 | if (op_mode == VOIDmode) | |
6649 | op_mode = GET_MODE (rs6000_compare_op1); | |
6650 | ||
6651 | if (TARGET_POWERPC64 && (op_mode == DImode || rs6000_compare_fp_p)) | |
6652 | { | |
6653 | PUT_MODE (condition_rtx, DImode); | |
6654 | convert_move (result, condition_rtx, 0); | |
6655 | } | |
6656 | else | |
6657 | { | |
6658 | PUT_MODE (condition_rtx, SImode); | |
6659 | emit_insn (gen_rtx_SET (VOIDmode, result, condition_rtx)); | |
6660 | } | |
6661 | } | |
6662 | ||
39a10a29 GK |
6663 | /* Emit a branch of kind CODE to location LOC. */ |
6664 | ||
6665 | void | |
6666 | rs6000_emit_cbranch (code, loc) | |
6667 | enum rtx_code code; | |
6668 | rtx loc; | |
6669 | { | |
6670 | rtx condition_rtx, loc_ref; | |
6671 | ||
6672 | condition_rtx = rs6000_generate_compare (code); | |
6673 | loc_ref = gen_rtx_LABEL_REF (VOIDmode, loc); | |
6674 | emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, | |
6675 | gen_rtx_IF_THEN_ELSE (VOIDmode, condition_rtx, | |
6676 | loc_ref, pc_rtx))); | |
6677 | } | |
6678 | ||
12a4e8c5 GK |
6679 | /* Return the string to output a conditional branch to LABEL, which is |
6680 | the operand number of the label, or -1 if the branch is really a | |
6681 | conditional return. | |
6682 | ||
6683 | OP is the conditional expression. XEXP (OP, 0) is assumed to be a | |
6684 | condition code register and its mode specifies what kind of | |
6685 | comparison we made. | |
6686 | ||
6687 | REVERSED is non-zero if we should reverse the sense of the comparison. | |
6688 | ||
6689 | INSN is the insn. */ | |
6690 | ||
6691 | char * | |
6692 | output_cbranch (op, label, reversed, insn) | |
6693 | rtx op; | |
6694 | const char * label; | |
6695 | int reversed; | |
6696 | rtx insn; | |
6697 | { | |
6698 | static char string[64]; | |
6699 | enum rtx_code code = GET_CODE (op); | |
6700 | rtx cc_reg = XEXP (op, 0); | |
6701 | enum machine_mode mode = GET_MODE (cc_reg); | |
6702 | int cc_regno = REGNO (cc_reg) - CR0_REGNO; | |
39a10a29 | 6703 | int need_longbranch = label != NULL && get_attr_length (insn) == 8; |
12a4e8c5 GK |
6704 | int really_reversed = reversed ^ need_longbranch; |
6705 | char *s = string; | |
6706 | const char *ccode; | |
6707 | const char *pred; | |
6708 | rtx note; | |
6709 | ||
39a10a29 GK |
6710 | validate_condition_mode (code, mode); |
6711 | ||
6712 | /* Work out which way this really branches. We could use | |
6713 | reverse_condition_maybe_unordered here always but this | |
6714 | makes the resulting assembler clearer. */ | |
12a4e8c5 | 6715 | if (really_reversed) |
39a10a29 | 6716 | code = rs6000_reverse_condition (mode, code); |
12a4e8c5 | 6717 | |
39a10a29 | 6718 | switch (code) |
12a4e8c5 GK |
6719 | { |
6720 | /* Not all of these are actually distinct opcodes, but | |
6721 | we distinguish them for clarity of the resulting assembler. */ | |
50a0b056 GK |
6722 | case NE: case LTGT: |
6723 | ccode = "ne"; break; | |
6724 | case EQ: case UNEQ: | |
6725 | ccode = "eq"; break; | |
6726 | case GE: case GEU: | |
6727 | ccode = "ge"; break; | |
6728 | case GT: case GTU: case UNGT: | |
6729 | ccode = "gt"; break; | |
6730 | case LE: case LEU: | |
6731 | ccode = "le"; break; | |
6732 | case LT: case LTU: case UNLT: | |
6733 | ccode = "lt"; break; | |
12a4e8c5 GK |
6734 | case UNORDERED: ccode = "un"; break; |
6735 | case ORDERED: ccode = "nu"; break; | |
6736 | case UNGE: ccode = "nl"; break; | |
6737 | case UNLE: ccode = "ng"; break; | |
6738 | default: | |
a4f6c312 | 6739 | abort (); |
12a4e8c5 GK |
6740 | } |
6741 | ||
94a54f47 GK |
6742 | /* Maybe we have a guess as to how likely the branch is. |
6743 | The old mnemonics don't have a way to specify this information. */ | |
12a4e8c5 GK |
6744 | note = find_reg_note (insn, REG_BR_PROB, NULL_RTX); |
6745 | if (note != NULL_RTX) | |
6746 | { | |
6747 | /* PROB is the difference from 50%. */ | |
6748 | int prob = INTVAL (XEXP (note, 0)) - REG_BR_PROB_BASE / 2; | |
6749 | ||
6750 | /* For branches that are very close to 50%, assume not-taken. */ | |
6751 | if (abs (prob) > REG_BR_PROB_BASE / 20 | |
6752 | && ((prob > 0) ^ need_longbranch)) | |
6753 | pred = "+"; | |
6754 | else | |
6755 | pred = "-"; | |
6756 | } | |
6757 | else | |
6758 | pred = ""; | |
6759 | ||
6760 | if (label == NULL) | |
94a54f47 | 6761 | s += sprintf (s, "{b%sr|b%slr%s} ", ccode, ccode, pred); |
12a4e8c5 | 6762 | else |
94a54f47 | 6763 | s += sprintf (s, "{b%s|b%s%s} ", ccode, ccode, pred); |
12a4e8c5 | 6764 | |
37c67319 GK |
6765 | /* We need to escape any '%' characters in the reg_names string. |
6766 | Assume they'd only be the first character... */ | |
6767 | if (reg_names[cc_regno + CR0_REGNO][0] == '%') | |
6768 | *s++ = '%'; | |
94a54f47 | 6769 | s += sprintf (s, "%s", reg_names[cc_regno + CR0_REGNO]); |
12a4e8c5 GK |
6770 | |
6771 | if (label != NULL) | |
6772 | { | |
6773 | /* If the branch distance was too far, we may have to use an | |
6774 | unconditional branch to go the distance. */ | |
6775 | if (need_longbranch) | |
44518ddd | 6776 | s += sprintf (s, ",$+8\n\tb %s", label); |
12a4e8c5 GK |
6777 | else |
6778 | s += sprintf (s, ",%s", label); | |
6779 | } | |
6780 | ||
6781 | return string; | |
6782 | } | |
50a0b056 GK |
6783 | |
6784 | /* Emit a conditional move: move TRUE_COND to DEST if OP of the | |
6785 | operands of the last comparison is nonzero/true, FALSE_COND if it | |
6786 | is zero/false. Return 0 if the hardware has no such operation. */ | |
a4f6c312 | 6787 | |
50a0b056 GK |
6788 | int |
6789 | rs6000_emit_cmove (dest, op, true_cond, false_cond) | |
6790 | rtx dest; | |
6791 | rtx op; | |
6792 | rtx true_cond; | |
6793 | rtx false_cond; | |
6794 | { | |
6795 | enum rtx_code code = GET_CODE (op); | |
6796 | rtx op0 = rs6000_compare_op0; | |
6797 | rtx op1 = rs6000_compare_op1; | |
6798 | REAL_VALUE_TYPE c1; | |
6799 | enum machine_mode mode = GET_MODE (op0); | |
6800 | rtx temp; | |
6801 | ||
6802 | /* First, work out if the hardware can do this at all, or | |
6803 | if it's too slow... */ | |
6804 | /* If the comparison is an integer one, since we only have fsel | |
6805 | it'll be cheaper to use a branch. */ | |
6806 | if (! rs6000_compare_fp_p) | |
6807 | return 0; | |
6808 | ||
6809 | /* Eliminate half of the comparisons by switching operands, this | |
6810 | makes the remaining code simpler. */ | |
6811 | if (code == UNLT || code == UNGT || code == UNORDERED || code == NE | |
6812 | || code == LTGT || code == LT) | |
6813 | { | |
6814 | code = reverse_condition_maybe_unordered (code); | |
6815 | temp = true_cond; | |
6816 | true_cond = false_cond; | |
6817 | false_cond = temp; | |
6818 | } | |
6819 | ||
6820 | /* UNEQ and LTGT take four instructions for a comparison with zero, | |
6821 | it'll probably be faster to use a branch here too. */ | |
6822 | if (code == UNEQ) | |
6823 | return 0; | |
6824 | ||
6825 | if (GET_CODE (op1) == CONST_DOUBLE) | |
6826 | REAL_VALUE_FROM_CONST_DOUBLE (c1, op1); | |
6827 | ||
6828 | /* We're going to try to implement comparions by performing | |
6829 | a subtract, then comparing against zero. Unfortunately, | |
6830 | Inf - Inf is NaN which is not zero, and so if we don't | |
6831 | know that the the operand is finite and the comparison | |
6832 | would treat EQ different to UNORDERED, we can't do it. */ | |
6833 | if (! flag_unsafe_math_optimizations | |
6834 | && code != GT && code != UNGE | |
6835 | && (GET_CODE (op1) != CONST_DOUBLE || target_isinf (c1)) | |
6836 | /* Constructs of the form (a OP b ? a : b) are safe. */ | |
6837 | && ((! rtx_equal_p (op0, false_cond) && ! rtx_equal_p (op1, false_cond)) | |
6838 | || (! rtx_equal_p (op0, true_cond) | |
6839 | && ! rtx_equal_p (op1, true_cond)))) | |
6840 | return 0; | |
6841 | /* At this point we know we can use fsel. */ | |
6842 | ||
6843 | /* Reduce the comparison to a comparison against zero. */ | |
6844 | temp = gen_reg_rtx (mode); | |
6845 | emit_insn (gen_rtx_SET (VOIDmode, temp, | |
6846 | gen_rtx_MINUS (mode, op0, op1))); | |
6847 | op0 = temp; | |
6848 | op1 = CONST0_RTX (mode); | |
6849 | ||
6850 | /* If we don't care about NaNs we can reduce some of the comparisons | |
6851 | down to faster ones. */ | |
6852 | if (flag_unsafe_math_optimizations) | |
6853 | switch (code) | |
6854 | { | |
6855 | case GT: | |
6856 | code = LE; | |
6857 | temp = true_cond; | |
6858 | true_cond = false_cond; | |
6859 | false_cond = temp; | |
6860 | break; | |
6861 | case UNGE: | |
6862 | code = GE; | |
6863 | break; | |
6864 | case UNEQ: | |
6865 | code = EQ; | |
6866 | break; | |
6867 | default: | |
6868 | break; | |
6869 | } | |
6870 | ||
6871 | /* Now, reduce everything down to a GE. */ | |
6872 | switch (code) | |
6873 | { | |
6874 | case GE: | |
6875 | break; | |
6876 | ||
6877 | case LE: | |
6878 | temp = gen_reg_rtx (mode); | |
6879 | emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (mode, op0))); | |
6880 | op0 = temp; | |
6881 | break; | |
6882 | ||
6883 | case ORDERED: | |
6884 | temp = gen_reg_rtx (mode); | |
6885 | emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_ABS (mode, op0))); | |
6886 | op0 = temp; | |
6887 | break; | |
6888 | ||
6889 | case EQ: | |
6890 | temp = gen_reg_rtx (mode); | |
6891 | emit_insn (gen_rtx_SET (VOIDmode, temp, | |
6892 | gen_rtx_NEG (mode, | |
6893 | gen_rtx_ABS (mode, op0)))); | |
6894 | op0 = temp; | |
6895 | break; | |
6896 | ||
6897 | case UNGE: | |
6898 | temp = gen_reg_rtx (mode); | |
6899 | emit_insn (gen_rtx_SET (VOIDmode, temp, | |
6900 | gen_rtx_IF_THEN_ELSE (mode, | |
6901 | gen_rtx_GE (VOIDmode, | |
6902 | op0, op1), | |
6903 | true_cond, false_cond))); | |
6904 | false_cond = temp; | |
6905 | true_cond = false_cond; | |
6906 | ||
6907 | temp = gen_reg_rtx (mode); | |
6908 | emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (mode, op0))); | |
6909 | op0 = temp; | |
6910 | break; | |
6911 | ||
6912 | case GT: | |
6913 | temp = gen_reg_rtx (mode); | |
6914 | emit_insn (gen_rtx_SET (VOIDmode, temp, | |
6915 | gen_rtx_IF_THEN_ELSE (mode, | |
6916 | gen_rtx_GE (VOIDmode, | |
6917 | op0, op1), | |
6918 | true_cond, false_cond))); | |
6919 | true_cond = temp; | |
6920 | false_cond = true_cond; | |
6921 | ||
6922 | temp = gen_reg_rtx (mode); | |
6923 | emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (mode, op0))); | |
6924 | op0 = temp; | |
6925 | break; | |
6926 | ||
6927 | default: | |
6928 | abort (); | |
6929 | } | |
6930 | ||
6931 | emit_insn (gen_rtx_SET (VOIDmode, dest, | |
9f1a9740 | 6932 | gen_rtx_IF_THEN_ELSE (GET_MODE (dest), |
50a0b056 GK |
6933 | gen_rtx_GE (VOIDmode, |
6934 | op0, op1), | |
6935 | true_cond, false_cond))); | |
6936 | return 1; | |
6937 | } | |
6938 | ||
6939 | void | |
6940 | rs6000_emit_minmax (dest, code, op0, op1) | |
6941 | rtx dest; | |
6942 | enum rtx_code code; | |
6943 | rtx op0; | |
6944 | rtx op1; | |
6945 | { | |
6946 | enum machine_mode mode = GET_MODE (op0); | |
6947 | rtx target; | |
6948 | if (code == SMAX || code == UMAX) | |
6949 | target = emit_conditional_move (dest, GE, op0, op1, mode, | |
6950 | op0, op1, mode, 0); | |
6951 | else | |
6952 | target = emit_conditional_move (dest, GE, op0, op1, mode, | |
6953 | op1, op0, mode, 0); | |
6954 | if (target == NULL_RTX) | |
6955 | abort (); | |
6956 | if (target != dest) | |
6957 | emit_move_insn (dest, target); | |
6958 | } | |
12a4e8c5 | 6959 | \f |
a4f6c312 SS |
6960 | /* This page contains routines that are used to determine what the |
6961 | function prologue and epilogue code will do and write them out. */ | |
9878760c | 6962 | |
a4f6c312 SS |
6963 | /* Return the first fixed-point register that is required to be |
6964 | saved. 32 if none. */ | |
9878760c RK |
6965 | |
6966 | int | |
6967 | first_reg_to_save () | |
6968 | { | |
6969 | int first_reg; | |
6970 | ||
6971 | /* Find lowest numbered live register. */ | |
6972 | for (first_reg = 13; first_reg <= 31; first_reg++) | |
a38d360d GK |
6973 | if (regs_ever_live[first_reg] |
6974 | && (! call_used_regs[first_reg] | |
6975 | || (first_reg == PIC_OFFSET_TABLE_REGNUM | |
f607bc57 ZW |
6976 | && ((DEFAULT_ABI == ABI_V4 && flag_pic == 1) |
6977 | || (DEFAULT_ABI == ABI_DARWIN && flag_pic))))) | |
9878760c RK |
6978 | break; |
6979 | ||
70f4f91c | 6980 | if (current_function_profile) |
b5253831 DE |
6981 | { |
6982 | /* AIX must save/restore every register that contains a parameter | |
6983 | before/after the .__mcount call plus an additional register | |
6984 | for the static chain, if needed; use registers from 30 down to 22 | |
6985 | to do this. */ | |
ee890fe2 | 6986 | if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) |
b5253831 DE |
6987 | { |
6988 | int last_parm_reg, profile_first_reg; | |
6989 | ||
6990 | /* Figure out last used parameter register. The proper thing | |
6991 | to do is to walk incoming args of the function. A function | |
6992 | might have live parameter registers even if it has no | |
6993 | incoming args. */ | |
6994 | for (last_parm_reg = 10; | |
6995 | last_parm_reg > 2 && ! regs_ever_live [last_parm_reg]; | |
6996 | last_parm_reg--) | |
6997 | ; | |
6998 | ||
6999 | /* Calculate first reg for saving parameter registers | |
7000 | and static chain. | |
7001 | Skip reg 31 which may contain the frame pointer. */ | |
7002 | profile_first_reg = (33 - last_parm_reg | |
7003 | - (current_function_needs_context ? 1 : 0)); | |
ee890fe2 SS |
7004 | #if TARGET_MACHO |
7005 | /* Need to skip another reg to account for R31 being PICBASE | |
7006 | (when flag_pic is set) or R30 being used as the frame | |
7007 | pointer (when flag_pic is not set). */ | |
7008 | --profile_first_reg; | |
7009 | #endif | |
b5253831 DE |
7010 | /* Do not save frame pointer if no parameters needs to be saved. */ |
7011 | if (profile_first_reg == 31) | |
7012 | profile_first_reg = 32; | |
7013 | ||
7014 | if (first_reg > profile_first_reg) | |
7015 | first_reg = profile_first_reg; | |
7016 | } | |
e165f3f0 | 7017 | |
b5253831 DE |
7018 | /* SVR4 may need one register to preserve the static chain. */ |
7019 | else if (current_function_needs_context) | |
7020 | { | |
7021 | /* Skip reg 31 which may contain the frame pointer. */ | |
7022 | if (first_reg > 30) | |
7023 | first_reg = 30; | |
7024 | } | |
7025 | } | |
e165f3f0 | 7026 | |
ee890fe2 SS |
7027 | #if TARGET_MACHO |
7028 | if (flag_pic && current_function_uses_pic_offset_table && | |
7029 | (first_reg > PIC_OFFSET_TABLE_REGNUM)) | |
7030 | return PIC_OFFSET_TABLE_REGNUM; | |
7031 | #endif | |
7032 | ||
9878760c RK |
7033 | return first_reg; |
7034 | } | |
7035 | ||
7036 | /* Similar, for FP regs. */ | |
7037 | ||
7038 | int | |
7039 | first_fp_reg_to_save () | |
7040 | { | |
7041 | int first_reg; | |
7042 | ||
7043 | /* Find lowest numbered live register. */ | |
7044 | for (first_reg = 14 + 32; first_reg <= 63; first_reg++) | |
7045 | if (regs_ever_live[first_reg]) | |
7046 | break; | |
7047 | ||
7048 | return first_reg; | |
7049 | } | |
00b960c7 AH |
7050 | |
7051 | /* Similar, for AltiVec regs. */ | |
7052 | ||
7053 | static int | |
7054 | first_altivec_reg_to_save () | |
7055 | { | |
7056 | int i; | |
7057 | ||
7058 | /* Stack frame remains as is unless we are in AltiVec ABI. */ | |
7059 | if (! TARGET_ALTIVEC_ABI) | |
7060 | return LAST_ALTIVEC_REGNO + 1; | |
7061 | ||
7062 | /* Find lowest numbered live register. */ | |
7063 | for (i = FIRST_ALTIVEC_REGNO + 20; i <= LAST_ALTIVEC_REGNO; ++i) | |
7064 | if (regs_ever_live[i]) | |
7065 | break; | |
7066 | ||
7067 | return i; | |
7068 | } | |
7069 | ||
7070 | /* Return a 32-bit mask of the AltiVec registers we need to set in | |
7071 | VRSAVE. Bit n of the return value is 1 if Vn is live. The MSB in | |
7072 | the 32-bit word is 0. */ | |
7073 | ||
7074 | static unsigned int | |
7075 | compute_vrsave_mask () | |
7076 | { | |
7077 | unsigned int i, mask = 0; | |
7078 | ||
7079 | /* First, find out if we use _any_ altivec registers. */ | |
7080 | for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i) | |
7081 | if (regs_ever_live[i]) | |
7082 | mask |= ALTIVEC_REG_BIT (i); | |
7083 | ||
7084 | if (mask == 0) | |
7085 | return mask; | |
7086 | ||
7087 | /* Next, add all registers that are call-clobbered. We do this | |
7088 | because post-reload register optimizers such as regrename_optimize | |
7089 | may choose to use them. They never change the register class | |
7090 | chosen by reload, so cannot create new uses of altivec registers | |
7091 | if there were none before, so the early exit above is safe. */ | |
7092 | /* ??? Alternately, we could define HARD_REGNO_RENAME_OK to disallow | |
7093 | altivec registers not saved in the mask, which might well make the | |
7094 | adjustments below more effective in eliding the save/restore of | |
7095 | VRSAVE in small functions. */ | |
7096 | for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i) | |
7097 | if (call_used_regs[i]) | |
7098 | mask |= ALTIVEC_REG_BIT (i); | |
7099 | ||
7100 | /* Next, remove the argument registers from the set. These must | |
7101 | be in the VRSAVE mask set by the caller, so we don't need to add | |
7102 | them in again. More importantly, the mask we compute here is | |
7103 | used to generate CLOBBERs in the set_vrsave insn, and we do not | |
7104 | wish the argument registers to die. */ | |
7105 | for (i = cfun->args_info.vregno; i >= ALTIVEC_ARG_MIN_REG; --i) | |
7106 | mask &= ~ALTIVEC_REG_BIT (i); | |
7107 | ||
7108 | /* Similarly, remove the return value from the set. */ | |
7109 | { | |
7110 | bool yes = false; | |
7111 | diddle_return_value (is_altivec_return_reg, &yes); | |
7112 | if (yes) | |
7113 | mask &= ~ALTIVEC_REG_BIT (ALTIVEC_ARG_RETURN); | |
7114 | } | |
7115 | ||
7116 | return mask; | |
7117 | } | |
7118 | ||
7119 | static void | |
7120 | is_altivec_return_reg (reg, xyes) | |
7121 | rtx reg; | |
7122 | void *xyes; | |
7123 | { | |
7124 | bool *yes = (bool *) xyes; | |
7125 | if (REGNO (reg) == ALTIVEC_ARG_RETURN) | |
7126 | *yes = true; | |
7127 | } | |
7128 | ||
4697a36c MM |
7129 | \f |
7130 | /* Calculate the stack information for the current function. This is | |
7131 | complicated by having two separate calling sequences, the AIX calling | |
7132 | sequence and the V.4 calling sequence. | |
7133 | ||
592696dd | 7134 | AIX (and Darwin/Mac OS X) stack frames look like: |
a260abc9 | 7135 | 32-bit 64-bit |
4697a36c | 7136 | SP----> +---------------------------------------+ |
a260abc9 | 7137 | | back chain to caller | 0 0 |
4697a36c | 7138 | +---------------------------------------+ |
a260abc9 | 7139 | | saved CR | 4 8 (8-11) |
4697a36c | 7140 | +---------------------------------------+ |
a260abc9 | 7141 | | saved LR | 8 16 |
4697a36c | 7142 | +---------------------------------------+ |
a260abc9 | 7143 | | reserved for compilers | 12 24 |
4697a36c | 7144 | +---------------------------------------+ |
a260abc9 | 7145 | | reserved for binders | 16 32 |
4697a36c | 7146 | +---------------------------------------+ |
a260abc9 | 7147 | | saved TOC pointer | 20 40 |
4697a36c | 7148 | +---------------------------------------+ |
a260abc9 | 7149 | | Parameter save area (P) | 24 48 |
4697a36c | 7150 | +---------------------------------------+ |
a260abc9 | 7151 | | Alloca space (A) | 24+P etc. |
802a0058 | 7152 | +---------------------------------------+ |
a7df97e6 | 7153 | | Local variable space (L) | 24+P+A |
4697a36c | 7154 | +---------------------------------------+ |
a7df97e6 | 7155 | | Float/int conversion temporary (X) | 24+P+A+L |
4697a36c | 7156 | +---------------------------------------+ |
00b960c7 AH |
7157 | | Save area for AltiVec registers (W) | 24+P+A+L+X |
7158 | +---------------------------------------+ | |
7159 | | AltiVec alignment padding (Y) | 24+P+A+L+X+W | |
7160 | +---------------------------------------+ | |
7161 | | Save area for VRSAVE register (Z) | 24+P+A+L+X+W+Y | |
4697a36c | 7162 | +---------------------------------------+ |
00b960c7 AH |
7163 | | Save area for GP registers (G) | 24+P+A+X+L+X+W+Y+Z |
7164 | +---------------------------------------+ | |
7165 | | Save area for FP registers (F) | 24+P+A+X+L+X+W+Y+Z+G | |
4697a36c MM |
7166 | +---------------------------------------+ |
7167 | old SP->| back chain to caller's caller | | |
7168 | +---------------------------------------+ | |
7169 | ||
5376a30c KR |
7170 | The required alignment for AIX configurations is two words (i.e., 8 |
7171 | or 16 bytes). | |
7172 | ||
7173 | ||
4697a36c MM |
7174 | V.4 stack frames look like: |
7175 | ||
7176 | SP----> +---------------------------------------+ | |
7177 | | back chain to caller | 0 | |
7178 | +---------------------------------------+ | |
5eb387b8 | 7179 | | caller's saved LR | 4 |
4697a36c MM |
7180 | +---------------------------------------+ |
7181 | | Parameter save area (P) | 8 | |
7182 | +---------------------------------------+ | |
a7df97e6 MM |
7183 | | Alloca space (A) | 8+P |
7184 | +---------------------------------------+ | |
7185 | | Varargs save area (V) | 8+P+A | |
7186 | +---------------------------------------+ | |
7187 | | Local variable space (L) | 8+P+A+V | |
7188 | +---------------------------------------+ | |
7189 | | Float/int conversion temporary (X) | 8+P+A+V+L | |
4697a36c | 7190 | +---------------------------------------+ |
00b960c7 AH |
7191 | | Save area for AltiVec registers (W) | 8+P+A+V+L+X |
7192 | +---------------------------------------+ | |
7193 | | AltiVec alignment padding (Y) | 8+P+A+V+L+X+W | |
7194 | +---------------------------------------+ | |
7195 | | Save area for VRSAVE register (Z) | 8+P+A+V+L+X+W+Y | |
7196 | +---------------------------------------+ | |
7197 | | saved CR (C) | 8+P+A+V+L+X+W+Y+Z | |
a7df97e6 | 7198 | +---------------------------------------+ |
00b960c7 | 7199 | | Save area for GP registers (G) | 8+P+A+V+L+X+W+Y+Z+C |
a7df97e6 | 7200 | +---------------------------------------+ |
00b960c7 | 7201 | | Save area for FP registers (F) | 8+P+A+V+L+X+W+Y+Z+C+G |
4697a36c MM |
7202 | +---------------------------------------+ |
7203 | old SP->| back chain to caller's caller | | |
7204 | +---------------------------------------+ | |
b6c9286a | 7205 | |
5376a30c KR |
7206 | The required alignment for V.4 is 16 bytes, or 8 bytes if -meabi is |
7207 | given. (But note below and in sysv4.h that we require only 8 and | |
7208 | may round up the size of our stack frame anyways. The historical | |
7209 | reason is early versions of powerpc-linux which didn't properly | |
7210 | align the stack at program startup. A happy side-effect is that | |
7211 | -mno-eabi libraries can be used with -meabi programs.) | |
7212 | ||
5376a30c KR |
7213 | The EABI configuration defaults to the V.4 layout, unless |
7214 | -mcall-aix is used, in which case the AIX layout is used. However, | |
7215 | the stack alignment requirements may differ. If -mno-eabi is not | |
7216 | given, the required stack alignment is 8 bytes; if -mno-eabi is | |
7217 | given, the required alignment is 16 bytes. (But see V.4 comment | |
7218 | above.) */ | |
4697a36c | 7219 | |
61b2fbe7 MM |
7220 | #ifndef ABI_STACK_BOUNDARY |
7221 | #define ABI_STACK_BOUNDARY STACK_BOUNDARY | |
7222 | #endif | |
7223 | ||
4697a36c MM |
7224 | rs6000_stack_t * |
7225 | rs6000_stack_info () | |
7226 | { | |
7227 | static rs6000_stack_t info, zero_info; | |
7228 | rs6000_stack_t *info_ptr = &info; | |
9ebbca7d | 7229 | int reg_size = TARGET_POWERPC64 ? 8 : 4; |
24d304eb | 7230 | enum rs6000_abi abi; |
83720594 | 7231 | int ehrd_size; |
b6c9286a | 7232 | int total_raw_size; |
4697a36c | 7233 | |
a4f6c312 | 7234 | /* Zero all fields portably. */ |
4697a36c MM |
7235 | info = zero_info; |
7236 | ||
a4f6c312 | 7237 | /* Select which calling sequence. */ |
b6c9286a | 7238 | info_ptr->abi = abi = DEFAULT_ABI; |
9878760c | 7239 | |
a4f6c312 | 7240 | /* Calculate which registers need to be saved & save area size. */ |
4697a36c | 7241 | info_ptr->first_gp_reg_save = first_reg_to_save (); |
906fb125 GK |
7242 | /* Assume that we will have to save PIC_OFFSET_TABLE_REGNUM, |
7243 | even if it currently looks like we won't. */ | |
2bfcf297 | 7244 | if (((TARGET_TOC && TARGET_MINIMAL_TOC) |
f607bc57 ZW |
7245 | || (flag_pic == 1 && abi == ABI_V4) |
7246 | || (flag_pic && abi == ABI_DARWIN)) | |
906fb125 GK |
7247 | && info_ptr->first_gp_reg_save > PIC_OFFSET_TABLE_REGNUM) |
7248 | info_ptr->gp_size = reg_size * (32 - PIC_OFFSET_TABLE_REGNUM); | |
7249 | else | |
7250 | info_ptr->gp_size = reg_size * (32 - info_ptr->first_gp_reg_save); | |
4697a36c MM |
7251 | |
7252 | info_ptr->first_fp_reg_save = first_fp_reg_to_save (); | |
7253 | info_ptr->fp_size = 8 * (64 - info_ptr->first_fp_reg_save); | |
7254 | ||
00b960c7 AH |
7255 | info_ptr->first_altivec_reg_save = first_altivec_reg_to_save (); |
7256 | info_ptr->altivec_size = 16 * (LAST_ALTIVEC_REGNO + 1 | |
7257 | - info_ptr->first_altivec_reg_save); | |
7258 | ||
592696dd | 7259 | /* Does this function call anything? */ |
71f123ca FS |
7260 | info_ptr->calls_p = (! current_function_is_leaf |
7261 | || cfun->machine->ra_needs_full_frame); | |
b6c9286a | 7262 | |
a4f6c312 | 7263 | /* Determine if we need to save the link register. */ |
71f123ca | 7264 | if (rs6000_ra_ever_killed () |
70f4f91c | 7265 | || (DEFAULT_ABI == ABI_AIX && current_function_profile) |
4697a36c MM |
7266 | #ifdef TARGET_RELOCATABLE |
7267 | || (TARGET_RELOCATABLE && (get_pool_size () != 0)) | |
7268 | #endif | |
7269 | || (info_ptr->first_fp_reg_save != 64 | |
7270 | && !FP_SAVE_INLINE (info_ptr->first_fp_reg_save)) | |
00b960c7 | 7271 | || info_ptr->first_altivec_reg_save <= LAST_ALTIVEC_REGNO |
24d304eb | 7272 | || (abi == ABI_V4 && current_function_calls_alloca) |
a4f6c312 SS |
7273 | || (DEFAULT_ABI == ABI_DARWIN |
7274 | && flag_pic | |
7275 | && current_function_uses_pic_offset_table) | |
4697a36c MM |
7276 | || info_ptr->calls_p) |
7277 | { | |
7278 | info_ptr->lr_save_p = 1; | |
9ebbca7d | 7279 | regs_ever_live[LINK_REGISTER_REGNUM] = 1; |
4697a36c MM |
7280 | } |
7281 | ||
9ebbca7d GK |
7282 | /* Determine if we need to save the condition code registers. */ |
7283 | if (regs_ever_live[CR2_REGNO] | |
7284 | || regs_ever_live[CR3_REGNO] | |
7285 | || regs_ever_live[CR4_REGNO]) | |
4697a36c MM |
7286 | { |
7287 | info_ptr->cr_save_p = 1; | |
f607bc57 | 7288 | if (abi == ABI_V4) |
4697a36c MM |
7289 | info_ptr->cr_size = reg_size; |
7290 | } | |
7291 | ||
83720594 RH |
7292 | /* If the current function calls __builtin_eh_return, then we need |
7293 | to allocate stack space for registers that will hold data for | |
7294 | the exception handler. */ | |
7295 | if (current_function_calls_eh_return) | |
7296 | { | |
7297 | unsigned int i; | |
7298 | for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; ++i) | |
7299 | continue; | |
7300 | ehrd_size = i * UNITS_PER_WORD; | |
7301 | } | |
7302 | else | |
7303 | ehrd_size = 0; | |
7304 | ||
592696dd | 7305 | /* Determine various sizes. */ |
4697a36c MM |
7306 | info_ptr->reg_size = reg_size; |
7307 | info_ptr->fixed_size = RS6000_SAVE_AREA; | |
7308 | info_ptr->varargs_size = RS6000_VARARGS_AREA; | |
189e03e3 | 7309 | info_ptr->vars_size = RS6000_ALIGN (get_frame_size (), 8); |
a4f6c312 SS |
7310 | info_ptr->parm_size = RS6000_ALIGN (current_function_outgoing_args_size, |
7311 | 8); | |
00b960c7 AH |
7312 | |
7313 | if (TARGET_ALTIVEC_ABI) | |
7314 | { | |
7315 | info_ptr->vrsave_mask = compute_vrsave_mask (); | |
7316 | info_ptr->vrsave_size = info_ptr->vrsave_mask ? 4 : 0; | |
7317 | } | |
7318 | else | |
7319 | { | |
7320 | info_ptr->vrsave_mask = 0; | |
7321 | info_ptr->vrsave_size = 0; | |
7322 | } | |
b6c9286a | 7323 | |
592696dd | 7324 | /* Calculate the offsets. */ |
24d304eb | 7325 | switch (abi) |
4697a36c | 7326 | { |
b6c9286a | 7327 | case ABI_NONE: |
24d304eb | 7328 | default: |
b6c9286a MM |
7329 | abort (); |
7330 | ||
7331 | case ABI_AIX: | |
7332 | case ABI_AIX_NODESC: | |
ee890fe2 | 7333 | case ABI_DARWIN: |
b6c9286a MM |
7334 | info_ptr->fp_save_offset = - info_ptr->fp_size; |
7335 | info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size; | |
00b960c7 AH |
7336 | |
7337 | if (TARGET_ALTIVEC_ABI) | |
7338 | { | |
7339 | info_ptr->vrsave_save_offset | |
7340 | = info_ptr->gp_save_offset - info_ptr->vrsave_size; | |
7341 | ||
7342 | /* Align stack so vector save area is on a quadword boundary. */ | |
7343 | if (info_ptr->altivec_size != 0) | |
7344 | info_ptr->altivec_padding_size | |
7345 | = 16 - (-info_ptr->vrsave_save_offset % 16); | |
7346 | else | |
7347 | info_ptr->altivec_padding_size = 0; | |
7348 | ||
7349 | info_ptr->altivec_save_offset | |
7350 | = info_ptr->vrsave_save_offset | |
7351 | - info_ptr->altivec_padding_size | |
7352 | - info_ptr->altivec_size; | |
7353 | ||
7354 | /* Adjust for AltiVec case. */ | |
7355 | info_ptr->ehrd_offset = info_ptr->altivec_save_offset - ehrd_size; | |
7356 | } | |
7357 | else | |
7358 | info_ptr->ehrd_offset = info_ptr->gp_save_offset - ehrd_size; | |
a260abc9 DE |
7359 | info_ptr->cr_save_offset = reg_size; /* first word when 64-bit. */ |
7360 | info_ptr->lr_save_offset = 2*reg_size; | |
24d304eb RK |
7361 | break; |
7362 | ||
7363 | case ABI_V4: | |
b6c9286a MM |
7364 | info_ptr->fp_save_offset = - info_ptr->fp_size; |
7365 | info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size; | |
a7df97e6 | 7366 | info_ptr->cr_save_offset = info_ptr->gp_save_offset - info_ptr->cr_size; |
00b960c7 AH |
7367 | |
7368 | if (TARGET_ALTIVEC_ABI) | |
7369 | { | |
7370 | info_ptr->vrsave_save_offset | |
7371 | = info_ptr->cr_save_offset - info_ptr->vrsave_size; | |
7372 | ||
7373 | /* Align stack so vector save area is on a quadword boundary. */ | |
7374 | if (info_ptr->altivec_size != 0) | |
7375 | info_ptr->altivec_padding_size | |
7376 | = 16 - (-info_ptr->vrsave_save_offset % 16); | |
7377 | else | |
7378 | info_ptr->altivec_padding_size = 0; | |
7379 | ||
7380 | info_ptr->altivec_save_offset | |
7381 | = info_ptr->vrsave_save_offset | |
7382 | - info_ptr->altivec_padding_size | |
7383 | - info_ptr->altivec_size; | |
7384 | ||
7385 | /* Adjust for AltiVec case. */ | |
7386 | info_ptr->toc_save_offset | |
7387 | = info_ptr->altivec_save_offset - info_ptr->toc_size; | |
7388 | } | |
7389 | else | |
7390 | info_ptr->toc_save_offset = info_ptr->cr_save_offset - info_ptr->toc_size; | |
83720594 | 7391 | info_ptr->ehrd_offset = info_ptr->toc_save_offset - ehrd_size; |
b6c9286a MM |
7392 | info_ptr->lr_save_offset = reg_size; |
7393 | break; | |
4697a36c MM |
7394 | } |
7395 | ||
00b960c7 AH |
7396 | info_ptr->save_size = RS6000_ALIGN (info_ptr->fp_size |
7397 | + info_ptr->gp_size | |
7398 | + info_ptr->altivec_size | |
7399 | + info_ptr->altivec_padding_size | |
7400 | + info_ptr->vrsave_size | |
7401 | + ehrd_size | |
7402 | + info_ptr->cr_size | |
7403 | + info_ptr->lr_size | |
7404 | + info_ptr->vrsave_size | |
7405 | + info_ptr->toc_size, | |
7406 | (TARGET_ALTIVEC_ABI || ABI_DARWIN) | |
7407 | ? 16 : 8); | |
7408 | ||
ff381587 MM |
7409 | total_raw_size = (info_ptr->vars_size |
7410 | + info_ptr->parm_size | |
ff381587 MM |
7411 | + info_ptr->save_size |
7412 | + info_ptr->varargs_size | |
7413 | + info_ptr->fixed_size); | |
7414 | ||
a4f6c312 SS |
7415 | info_ptr->total_size = |
7416 | RS6000_ALIGN (total_raw_size, ABI_STACK_BOUNDARY / BITS_PER_UNIT); | |
ff381587 MM |
7417 | |
7418 | /* Determine if we need to allocate any stack frame: | |
7419 | ||
a4f6c312 SS |
7420 | For AIX we need to push the stack if a frame pointer is needed |
7421 | (because the stack might be dynamically adjusted), if we are | |
7422 | debugging, if we make calls, or if the sum of fp_save, gp_save, | |
7423 | and local variables are more than the space needed to save all | |
7424 | non-volatile registers: 32-bit: 18*8 + 19*4 = 220 or 64-bit: 18*8 | |
7425 | + 18*8 = 288 (GPR13 reserved). | |
ff381587 | 7426 | |
a4f6c312 SS |
7427 | For V.4 we don't have the stack cushion that AIX uses, but assume |
7428 | that the debugger can handle stackless frames. */ | |
ff381587 MM |
7429 | |
7430 | if (info_ptr->calls_p) | |
7431 | info_ptr->push_p = 1; | |
7432 | ||
f607bc57 | 7433 | else if (abi == ABI_V4) |
ff381587 | 7434 | info_ptr->push_p = (total_raw_size > info_ptr->fixed_size |
9ebbca7d | 7435 | || info_ptr->calls_p); |
ff381587 MM |
7436 | |
7437 | else | |
7438 | info_ptr->push_p = (frame_pointer_needed | |
ee890fe2 | 7439 | || (abi != ABI_DARWIN && write_symbols != NO_DEBUG) |
ff381587 | 7440 | || ((total_raw_size - info_ptr->fixed_size) |
bfc79d3b | 7441 | > (TARGET_32BIT ? 220 : 288))); |
ff381587 | 7442 | |
a4f6c312 | 7443 | /* Zero offsets if we're not saving those registers. */ |
8dda1a21 | 7444 | if (info_ptr->fp_size == 0) |
4697a36c MM |
7445 | info_ptr->fp_save_offset = 0; |
7446 | ||
8dda1a21 | 7447 | if (info_ptr->gp_size == 0) |
4697a36c MM |
7448 | info_ptr->gp_save_offset = 0; |
7449 | ||
00b960c7 AH |
7450 | if (! TARGET_ALTIVEC_ABI || info_ptr->altivec_size == 0) |
7451 | info_ptr->altivec_save_offset = 0; | |
7452 | ||
7453 | if (! TARGET_ALTIVEC_ABI || info_ptr->vrsave_mask == 0) | |
7454 | info_ptr->vrsave_save_offset = 0; | |
7455 | ||
c81fc13e | 7456 | if (! info_ptr->lr_save_p) |
4697a36c MM |
7457 | info_ptr->lr_save_offset = 0; |
7458 | ||
c81fc13e | 7459 | if (! info_ptr->cr_save_p) |
4697a36c MM |
7460 | info_ptr->cr_save_offset = 0; |
7461 | ||
c81fc13e | 7462 | if (! info_ptr->toc_save_p) |
b6c9286a MM |
7463 | info_ptr->toc_save_offset = 0; |
7464 | ||
4697a36c MM |
7465 | return info_ptr; |
7466 | } | |
7467 | ||
7468 | void | |
7469 | debug_stack_info (info) | |
7470 | rs6000_stack_t *info; | |
9878760c | 7471 | { |
d330fd93 | 7472 | const char *abi_string; |
24d304eb | 7473 | |
c81fc13e | 7474 | if (! info) |
4697a36c MM |
7475 | info = rs6000_stack_info (); |
7476 | ||
7477 | fprintf (stderr, "\nStack information for function %s:\n", | |
7478 | ((current_function_decl && DECL_NAME (current_function_decl)) | |
7479 | ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl)) | |
7480 | : "<unknown>")); | |
7481 | ||
24d304eb RK |
7482 | switch (info->abi) |
7483 | { | |
b6c9286a MM |
7484 | default: abi_string = "Unknown"; break; |
7485 | case ABI_NONE: abi_string = "NONE"; break; | |
f607bc57 | 7486 | case ABI_AIX: |
b6c9286a | 7487 | case ABI_AIX_NODESC: abi_string = "AIX"; break; |
ee890fe2 | 7488 | case ABI_DARWIN: abi_string = "Darwin"; break; |
b6c9286a | 7489 | case ABI_V4: abi_string = "V.4"; break; |
24d304eb RK |
7490 | } |
7491 | ||
7492 | fprintf (stderr, "\tABI = %5s\n", abi_string); | |
7493 | ||
00b960c7 AH |
7494 | if (TARGET_ALTIVEC_ABI) |
7495 | fprintf (stderr, "\tALTIVEC ABI extensions enabled.\n"); | |
7496 | ||
4697a36c MM |
7497 | if (info->first_gp_reg_save != 32) |
7498 | fprintf (stderr, "\tfirst_gp_reg_save = %5d\n", info->first_gp_reg_save); | |
7499 | ||
7500 | if (info->first_fp_reg_save != 64) | |
7501 | fprintf (stderr, "\tfirst_fp_reg_save = %5d\n", info->first_fp_reg_save); | |
9878760c | 7502 | |
00b960c7 AH |
7503 | if (info->first_altivec_reg_save <= LAST_ALTIVEC_REGNO) |
7504 | fprintf (stderr, "\tfirst_altivec_reg_save = %5d\n", | |
7505 | info->first_altivec_reg_save); | |
7506 | ||
4697a36c MM |
7507 | if (info->lr_save_p) |
7508 | fprintf (stderr, "\tlr_save_p = %5d\n", info->lr_save_p); | |
9878760c | 7509 | |
4697a36c MM |
7510 | if (info->cr_save_p) |
7511 | fprintf (stderr, "\tcr_save_p = %5d\n", info->cr_save_p); | |
7512 | ||
b6c9286a MM |
7513 | if (info->toc_save_p) |
7514 | fprintf (stderr, "\ttoc_save_p = %5d\n", info->toc_save_p); | |
7515 | ||
00b960c7 AH |
7516 | if (info->vrsave_mask) |
7517 | fprintf (stderr, "\tvrsave_mask = 0x%x\n", info->vrsave_mask); | |
7518 | ||
4697a36c MM |
7519 | if (info->push_p) |
7520 | fprintf (stderr, "\tpush_p = %5d\n", info->push_p); | |
7521 | ||
7522 | if (info->calls_p) | |
7523 | fprintf (stderr, "\tcalls_p = %5d\n", info->calls_p); | |
7524 | ||
4697a36c MM |
7525 | if (info->gp_save_offset) |
7526 | fprintf (stderr, "\tgp_save_offset = %5d\n", info->gp_save_offset); | |
7527 | ||
7528 | if (info->fp_save_offset) | |
7529 | fprintf (stderr, "\tfp_save_offset = %5d\n", info->fp_save_offset); | |
7530 | ||
00b960c7 AH |
7531 | if (info->altivec_save_offset) |
7532 | fprintf (stderr, "\taltivec_save_offset = %5d\n", | |
7533 | info->altivec_save_offset); | |
7534 | ||
7535 | if (info->vrsave_save_offset) | |
7536 | fprintf (stderr, "\tvrsave_save_offset = %5d\n", | |
7537 | info->vrsave_save_offset); | |
7538 | ||
4697a36c MM |
7539 | if (info->lr_save_offset) |
7540 | fprintf (stderr, "\tlr_save_offset = %5d\n", info->lr_save_offset); | |
7541 | ||
7542 | if (info->cr_save_offset) | |
7543 | fprintf (stderr, "\tcr_save_offset = %5d\n", info->cr_save_offset); | |
7544 | ||
b6c9286a MM |
7545 | if (info->toc_save_offset) |
7546 | fprintf (stderr, "\ttoc_save_offset = %5d\n", info->toc_save_offset); | |
7547 | ||
4697a36c MM |
7548 | if (info->varargs_save_offset) |
7549 | fprintf (stderr, "\tvarargs_save_offset = %5d\n", info->varargs_save_offset); | |
7550 | ||
7551 | if (info->total_size) | |
7552 | fprintf (stderr, "\ttotal_size = %5d\n", info->total_size); | |
7553 | ||
7554 | if (info->varargs_size) | |
7555 | fprintf (stderr, "\tvarargs_size = %5d\n", info->varargs_size); | |
7556 | ||
7557 | if (info->vars_size) | |
7558 | fprintf (stderr, "\tvars_size = %5d\n", info->vars_size); | |
7559 | ||
7560 | if (info->parm_size) | |
7561 | fprintf (stderr, "\tparm_size = %5d\n", info->parm_size); | |
7562 | ||
7563 | if (info->fixed_size) | |
7564 | fprintf (stderr, "\tfixed_size = %5d\n", info->fixed_size); | |
7565 | ||
7566 | if (info->gp_size) | |
7567 | fprintf (stderr, "\tgp_size = %5d\n", info->gp_size); | |
7568 | ||
7569 | if (info->fp_size) | |
7570 | fprintf (stderr, "\tfp_size = %5d\n", info->fp_size); | |
7571 | ||
00b960c7 AH |
7572 | if (info->altivec_size) |
7573 | fprintf (stderr, "\taltivec_size = %5d\n", info->altivec_size); | |
7574 | ||
7575 | if (info->vrsave_size) | |
7576 | fprintf (stderr, "\tvrsave_size = %5d\n", info->vrsave_size); | |
7577 | ||
7578 | if (info->altivec_padding_size) | |
7579 | fprintf (stderr, "\taltivec_padding_size= %5d\n", | |
7580 | info->altivec_padding_size); | |
7581 | ||
a4f6c312 | 7582 | if (info->lr_size) |
ed947a96 | 7583 | fprintf (stderr, "\tlr_size = %5d\n", info->lr_size); |
b6c9286a | 7584 | |
4697a36c MM |
7585 | if (info->cr_size) |
7586 | fprintf (stderr, "\tcr_size = %5d\n", info->cr_size); | |
7587 | ||
a4f6c312 | 7588 | if (info->toc_size) |
b6c9286a MM |
7589 | fprintf (stderr, "\ttoc_size = %5d\n", info->toc_size); |
7590 | ||
4697a36c MM |
7591 | if (info->save_size) |
7592 | fprintf (stderr, "\tsave_size = %5d\n", info->save_size); | |
7593 | ||
7594 | if (info->reg_size != 4) | |
7595 | fprintf (stderr, "\treg_size = %5d\n", info->reg_size); | |
7596 | ||
7597 | fprintf (stderr, "\n"); | |
9878760c | 7598 | } |
71f123ca FS |
7599 | |
7600 | rtx | |
7601 | rs6000_return_addr (count, frame) | |
7602 | int count; | |
7603 | rtx frame; | |
7604 | { | |
a4f6c312 SS |
7605 | /* Currently we don't optimize very well between prolog and body |
7606 | code and for PIC code the code can be actually quite bad, so | |
7607 | don't try to be too clever here. */ | |
3418dd3a FS |
7608 | if (count != 0 |
7609 | || flag_pic != 0 | |
7610 | || DEFAULT_ABI == ABI_AIX | |
7611 | || DEFAULT_ABI == ABI_AIX_NODESC) | |
71f123ca FS |
7612 | { |
7613 | cfun->machine->ra_needs_full_frame = 1; | |
8ac61af7 RK |
7614 | |
7615 | return | |
7616 | gen_rtx_MEM | |
7617 | (Pmode, | |
7618 | memory_address | |
7619 | (Pmode, | |
7620 | plus_constant (copy_to_reg | |
7621 | (gen_rtx_MEM (Pmode, | |
7622 | memory_address (Pmode, frame))), | |
7623 | RETURN_ADDRESS_OFFSET))); | |
71f123ca FS |
7624 | } |
7625 | ||
9e2f7ec7 | 7626 | return get_hard_reg_initial_val (Pmode, LINK_REGISTER_REGNUM); |
71f123ca FS |
7627 | } |
7628 | ||
7629 | static int | |
7630 | rs6000_ra_ever_killed () | |
7631 | { | |
7632 | rtx top; | |
7633 | ||
7634 | #ifdef ASM_OUTPUT_MI_THUNK | |
7635 | if (current_function_is_thunk) | |
7636 | return 0; | |
7637 | #endif | |
9e2f7ec7 DD |
7638 | if (!has_hard_reg_initial_val (Pmode, LINK_REGISTER_REGNUM) |
7639 | || cfun->machine->ra_needs_full_frame) | |
71f123ca FS |
7640 | return regs_ever_live[LINK_REGISTER_REGNUM]; |
7641 | ||
7642 | push_topmost_sequence (); | |
7643 | top = get_insns (); | |
7644 | pop_topmost_sequence (); | |
7645 | ||
7646 | return reg_set_between_p (gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM), | |
7647 | top, NULL_RTX); | |
7648 | } | |
4697a36c | 7649 | \f |
8cd8f856 GK |
7650 | /* Add a REG_MAYBE_DEAD note to the insn. */ |
7651 | static void | |
7652 | rs6000_maybe_dead (insn) | |
7653 | rtx insn; | |
7654 | { | |
7655 | REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD, | |
7656 | const0_rtx, | |
7657 | REG_NOTES (insn)); | |
7658 | } | |
7659 | ||
9ebbca7d | 7660 | /* Emit instructions needed to load the TOC register. |
c7ca610e | 7661 | This is only needed when TARGET_TOC, TARGET_MINIMAL_TOC, and there is |
9ebbca7d | 7662 | a constant pool; or for SVR4 -fpic. */ |
c7ca610e RK |
7663 | |
7664 | void | |
9ebbca7d GK |
7665 | rs6000_emit_load_toc_table (fromprolog) |
7666 | int fromprolog; | |
c7ca610e | 7667 | { |
9ebbca7d GK |
7668 | rtx dest; |
7669 | dest = gen_rtx_REG (Pmode, PIC_OFFSET_TABLE_REGNUM); | |
c7ca610e | 7670 | |
2bfcf297 | 7671 | if (TARGET_ELF && DEFAULT_ABI != ABI_AIX) |
c7ca610e | 7672 | { |
f607bc57 | 7673 | if (DEFAULT_ABI == ABI_V4 && flag_pic == 1) |
38c1f2d7 | 7674 | { |
9ebbca7d GK |
7675 | rtx temp = (fromprolog |
7676 | ? gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM) | |
7677 | : gen_reg_rtx (Pmode)); | |
2bfcf297 | 7678 | rs6000_maybe_dead (emit_insn (gen_load_toc_v4_pic_si (temp))); |
8cd8f856 | 7679 | rs6000_maybe_dead (emit_move_insn (dest, temp)); |
38c1f2d7 | 7680 | } |
9ebbca7d GK |
7681 | else if (flag_pic == 2) |
7682 | { | |
7683 | char buf[30]; | |
7684 | rtx tempLR = (fromprolog | |
7685 | ? gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM) | |
7686 | : gen_reg_rtx (Pmode)); | |
7687 | rtx temp0 = (fromprolog | |
7688 | ? gen_rtx_REG (Pmode, 0) | |
7689 | : gen_reg_rtx (Pmode)); | |
7690 | rtx symF; | |
7691 | ||
7692 | /* possibly create the toc section */ | |
7693 | if (! toc_initialized) | |
7694 | { | |
7695 | toc_section (); | |
7696 | function_section (current_function_decl); | |
7697 | } | |
7698 | ||
7699 | if (fromprolog) | |
7700 | { | |
7701 | rtx symL; | |
7702 | ||
7703 | ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno); | |
a8a05998 | 7704 | symF = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); |
38c1f2d7 | 7705 | |
9ebbca7d | 7706 | ASM_GENERATE_INTERNAL_LABEL (buf, "LCL", rs6000_pic_labelno); |
a8a05998 | 7707 | symL = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); |
38c1f2d7 | 7708 | |
8cd8f856 GK |
7709 | rs6000_maybe_dead (emit_insn (gen_load_toc_v4_PIC_1 (tempLR, |
7710 | symF))); | |
7711 | rs6000_maybe_dead (emit_move_insn (dest, tempLR)); | |
7712 | rs6000_maybe_dead (emit_insn (gen_load_toc_v4_PIC_2 (temp0, dest, | |
7713 | symL, | |
7714 | symF))); | |
9ebbca7d GK |
7715 | } |
7716 | else | |
7717 | { | |
7718 | rtx tocsym; | |
7719 | static int reload_toc_labelno = 0; | |
7720 | ||
b999aaeb | 7721 | tocsym = gen_rtx_SYMBOL_REF (Pmode, toc_label_name); |
38c1f2d7 | 7722 | |
9ebbca7d | 7723 | ASM_GENERATE_INTERNAL_LABEL (buf, "LCG", reload_toc_labelno++); |
a8a05998 | 7724 | symF = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); |
9ebbca7d | 7725 | |
8cd8f856 GK |
7726 | rs6000_maybe_dead (emit_insn (gen_load_toc_v4_PIC_1b (tempLR, |
7727 | symF, | |
7728 | tocsym))); | |
7729 | rs6000_maybe_dead (emit_move_insn (dest, tempLR)); | |
7730 | rs6000_maybe_dead (emit_move_insn (temp0, | |
7731 | gen_rtx_MEM (Pmode, dest))); | |
9ebbca7d | 7732 | } |
8cd8f856 | 7733 | rs6000_maybe_dead (emit_insn (gen_addsi3 (dest, temp0, dest))); |
9ebbca7d GK |
7734 | } |
7735 | else if (flag_pic == 0 && TARGET_MINIMAL_TOC) | |
7736 | { | |
7737 | /* This is for AIX code running in non-PIC ELF. */ | |
7738 | char buf[30]; | |
7739 | rtx realsym; | |
38c1f2d7 | 7740 | ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1); |
a8a05998 | 7741 | realsym = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); |
9ebbca7d | 7742 | |
8cd8f856 GK |
7743 | rs6000_maybe_dead (emit_insn (gen_elf_high (dest, realsym))); |
7744 | rs6000_maybe_dead (emit_insn (gen_elf_low (dest, dest, realsym))); | |
9ebbca7d GK |
7745 | } |
7746 | else | |
a4f6c312 | 7747 | abort (); |
9ebbca7d GK |
7748 | } |
7749 | else | |
7750 | { | |
7751 | if (TARGET_32BIT) | |
8cd8f856 | 7752 | rs6000_maybe_dead (emit_insn (gen_load_toc_aix_si (dest))); |
9ebbca7d | 7753 | else |
8cd8f856 | 7754 | rs6000_maybe_dead (emit_insn (gen_load_toc_aix_di (dest))); |
9ebbca7d GK |
7755 | } |
7756 | } | |
7757 | ||
7758 | int | |
7759 | get_TOC_alias_set () | |
7760 | { | |
7761 | static int set = -1; | |
7762 | if (set == -1) | |
7763 | set = new_alias_set (); | |
7764 | return set; | |
7765 | } | |
7766 | ||
7767 | /* This retuns nonzero if the current function uses the TOC. This is | |
7768 | determined by the presence of (unspec ... 7), which is generated by | |
7769 | the various load_toc_* patterns. */ | |
a4f6c312 | 7770 | |
9ebbca7d GK |
7771 | int |
7772 | uses_TOC () | |
7773 | { | |
7774 | rtx insn; | |
38c1f2d7 | 7775 | |
9ebbca7d | 7776 | for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) |
2c3c49de | 7777 | if (INSN_P (insn)) |
9ebbca7d GK |
7778 | { |
7779 | rtx pat = PATTERN (insn); | |
7780 | int i; | |
7781 | ||
8cd8f856 | 7782 | if (GET_CODE (pat) == PARALLEL) |
9ebbca7d GK |
7783 | for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++) |
7784 | if (GET_CODE (XVECEXP (PATTERN (insn), 0, i)) == UNSPEC | |
7785 | && XINT (XVECEXP (PATTERN (insn), 0, i), 1) == 7) | |
7786 | return 1; | |
38c1f2d7 | 7787 | } |
9ebbca7d GK |
7788 | return 0; |
7789 | } | |
38c1f2d7 | 7790 | |
9ebbca7d | 7791 | rtx |
a4f6c312 | 7792 | create_TOC_reference (symbol) |
9ebbca7d GK |
7793 | rtx symbol; |
7794 | { | |
a8a05998 ZW |
7795 | return gen_rtx_PLUS (Pmode, |
7796 | gen_rtx_REG (Pmode, TOC_REGISTER), | |
7797 | gen_rtx_CONST (Pmode, | |
7798 | gen_rtx_MINUS (Pmode, symbol, | |
b999aaeb | 7799 | gen_rtx_SYMBOL_REF (Pmode, toc_label_name)))); |
9ebbca7d | 7800 | } |
38c1f2d7 | 7801 | |
9ebbca7d GK |
7802 | #if TARGET_AIX |
7803 | /* __throw will restore its own return address to be the same as the | |
7804 | return address of the function that the throw is being made to. | |
7805 | This is unfortunate, because we want to check the original | |
7806 | return address to see if we need to restore the TOC. | |
7807 | So we have to squirrel it away here. | |
7808 | This is used only in compiling __throw and __rethrow. | |
c7ca610e | 7809 | |
9ebbca7d GK |
7810 | Most of this code should be removed by CSE. */ |
7811 | static rtx insn_after_throw; | |
c7ca610e | 7812 | |
a4f6c312 | 7813 | /* This does the saving... */ |
9ebbca7d GK |
7814 | void |
7815 | rs6000_aix_emit_builtin_unwind_init () | |
7816 | { | |
7817 | rtx mem; | |
7818 | rtx stack_top = gen_reg_rtx (Pmode); | |
7819 | rtx opcode_addr = gen_reg_rtx (Pmode); | |
7820 | ||
7821 | insn_after_throw = gen_reg_rtx (SImode); | |
7822 | ||
7823 | mem = gen_rtx_MEM (Pmode, hard_frame_pointer_rtx); | |
7824 | emit_move_insn (stack_top, mem); | |
7825 | ||
7826 | mem = gen_rtx_MEM (Pmode, | |
7827 | gen_rtx_PLUS (Pmode, stack_top, | |
7828 | GEN_INT (2 * GET_MODE_SIZE (Pmode)))); | |
7829 | emit_move_insn (opcode_addr, mem); | |
7830 | emit_move_insn (insn_after_throw, gen_rtx_MEM (SImode, opcode_addr)); | |
c7ca610e RK |
7831 | } |
7832 | ||
a4f6c312 SS |
7833 | /* Emit insns to _restore_ the TOC register, at runtime (specifically |
7834 | in _eh.o). Only used on AIX. | |
9ebbca7d GK |
7835 | |
7836 | The idea is that on AIX, function calls look like this: | |
7837 | bl somefunction-trampoline | |
7838 | lwz r2,20(sp) | |
7839 | ||
a4f6c312 | 7840 | and later, |
9ebbca7d GK |
7841 | somefunction-trampoline: |
7842 | stw r2,20(sp) | |
7843 | ... load function address in the count register ... | |
7844 | bctr | |
7845 | or like this, if the linker determines that this is not a cross-module call | |
7846 | and so the TOC need not be restored: | |
7847 | bl somefunction | |
7848 | nop | |
7849 | or like this, if the compiler could determine that this is not a | |
7850 | cross-module call: | |
7851 | bl somefunction | |
7852 | now, the tricky bit here is that register 2 is saved and restored | |
7853 | by the _linker_, so we can't readily generate debugging information | |
7854 | for it. So we need to go back up the call chain looking at the | |
7855 | insns at return addresses to see which calls saved the TOC register | |
7856 | and so see where it gets restored from. | |
7857 | ||
7858 | Oh, and all this gets done in RTL inside the eh_epilogue pattern, | |
7859 | just before the actual epilogue. | |
7860 | ||
7861 | On the bright side, this incurs no space or time overhead unless an | |
7862 | exception is thrown, except for the extra code in libgcc.a. | |
7863 | ||
7864 | The parameter STACKSIZE is a register containing (at runtime) | |
7865 | the amount to be popped off the stack in addition to the stack frame | |
7866 | of this routine (which will be __throw or __rethrow, and so is | |
7867 | guaranteed to have a stack frame). */ | |
a4f6c312 | 7868 | |
9ebbca7d GK |
7869 | void |
7870 | rs6000_emit_eh_toc_restore (stacksize) | |
7871 | rtx stacksize; | |
7872 | { | |
7873 | rtx top_of_stack; | |
7874 | rtx bottom_of_stack = gen_reg_rtx (Pmode); | |
7875 | rtx tocompare = gen_reg_rtx (SImode); | |
7876 | rtx opcode = gen_reg_rtx (SImode); | |
7877 | rtx opcode_addr = gen_reg_rtx (Pmode); | |
7878 | rtx mem; | |
7879 | rtx loop_start = gen_label_rtx (); | |
7880 | rtx no_toc_restore_needed = gen_label_rtx (); | |
7881 | rtx loop_exit = gen_label_rtx (); | |
7882 | ||
7883 | mem = gen_rtx_MEM (Pmode, hard_frame_pointer_rtx); | |
ba4828e0 | 7884 | set_mem_alias_set (mem, rs6000_sr_alias_set); |
9ebbca7d GK |
7885 | emit_move_insn (bottom_of_stack, mem); |
7886 | ||
7887 | top_of_stack = expand_binop (Pmode, add_optab, | |
7888 | bottom_of_stack, stacksize, | |
7889 | NULL_RTX, 1, OPTAB_WIDEN); | |
7890 | ||
7891 | emit_move_insn (tocompare, | |
7892 | GEN_INT (trunc_int_for_mode (TARGET_32BIT | |
7893 | ? 0x80410014 | |
7894 | : 0xE8410028, SImode))); | |
7895 | ||
7896 | if (insn_after_throw == NULL_RTX) | |
a4f6c312 | 7897 | abort (); |
9ebbca7d GK |
7898 | emit_move_insn (opcode, insn_after_throw); |
7899 | ||
6496a589 | 7900 | emit_note (NULL, NOTE_INSN_LOOP_BEG); |
9ebbca7d GK |
7901 | emit_label (loop_start); |
7902 | ||
7903 | do_compare_rtx_and_jump (opcode, tocompare, NE, 1, | |
06f4e019 | 7904 | SImode, NULL_RTX, NULL_RTX, |
9ebbca7d GK |
7905 | no_toc_restore_needed); |
7906 | ||
7907 | mem = gen_rtx_MEM (Pmode, | |
7908 | gen_rtx_PLUS (Pmode, bottom_of_stack, | |
7909 | GEN_INT (5 * GET_MODE_SIZE (Pmode)))); | |
7910 | emit_move_insn (gen_rtx_REG (Pmode, 2), mem); | |
7911 | ||
7912 | emit_label (no_toc_restore_needed); | |
7913 | do_compare_rtx_and_jump (top_of_stack, bottom_of_stack, EQ, 1, | |
06f4e019 | 7914 | Pmode, NULL_RTX, NULL_RTX, |
9ebbca7d GK |
7915 | loop_exit); |
7916 | ||
7917 | mem = gen_rtx_MEM (Pmode, bottom_of_stack); | |
ba4828e0 | 7918 | set_mem_alias_set (mem, rs6000_sr_alias_set); |
9ebbca7d GK |
7919 | emit_move_insn (bottom_of_stack, mem); |
7920 | ||
7921 | mem = gen_rtx_MEM (Pmode, | |
7922 | gen_rtx_PLUS (Pmode, bottom_of_stack, | |
7923 | GEN_INT (2 * GET_MODE_SIZE (Pmode)))); | |
7924 | emit_move_insn (opcode_addr, mem); | |
7925 | emit_move_insn (opcode, gen_rtx_MEM (SImode, opcode_addr)); | |
7926 | ||
6496a589 | 7927 | emit_note (NULL, NOTE_INSN_LOOP_CONT); |
9ebbca7d | 7928 | emit_jump (loop_start); |
6496a589 | 7929 | emit_note (NULL, NOTE_INSN_LOOP_END); |
9ebbca7d GK |
7930 | emit_label (loop_exit); |
7931 | } | |
7932 | #endif /* TARGET_AIX */ | |
38c1f2d7 | 7933 | \f |
ba4828e0 RK |
7934 | /* This ties together stack memory (MEM with an alias set of |
7935 | rs6000_sr_alias_set) and the change to the stack pointer. */ | |
7936 | ||
9ebbca7d GK |
7937 | static void |
7938 | rs6000_emit_stack_tie () | |
7939 | { | |
ba4828e0 RK |
7940 | rtx mem = gen_rtx_MEM (BLKmode, gen_rtx_REG (Pmode, STACK_POINTER_REGNUM)); |
7941 | ||
7942 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
9ebbca7d GK |
7943 | emit_insn (gen_stack_tie (mem)); |
7944 | } | |
38c1f2d7 | 7945 | |
9ebbca7d GK |
7946 | /* Emit the correct code for allocating stack space, as insns. |
7947 | If COPY_R12, make sure a copy of the old frame is left in r12. | |
7948 | The generated code may use hard register 0 as a temporary. */ | |
7949 | ||
7950 | static void | |
7951 | rs6000_emit_allocate_stack (size, copy_r12) | |
7952 | HOST_WIDE_INT size; | |
38c1f2d7 MM |
7953 | int copy_r12; |
7954 | { | |
9ebbca7d GK |
7955 | rtx insn; |
7956 | rtx stack_reg = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM); | |
7957 | rtx tmp_reg = gen_rtx_REG (Pmode, 0); | |
7958 | rtx todec = GEN_INT (-size); | |
a157febd GK |
7959 | |
7960 | if (current_function_limit_stack) | |
7961 | { | |
7962 | if (REG_P (stack_limit_rtx) | |
7963 | && REGNO (stack_limit_rtx) > 1 | |
7964 | && REGNO (stack_limit_rtx) <= 31) | |
7965 | { | |
9ebbca7d GK |
7966 | emit_insn (Pmode == SImode |
7967 | ? gen_addsi3 (tmp_reg, | |
7968 | stack_limit_rtx, | |
7969 | GEN_INT (size)) | |
7970 | : gen_adddi3 (tmp_reg, | |
7971 | stack_limit_rtx, | |
7972 | GEN_INT (size))); | |
7973 | ||
7974 | emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg, | |
7975 | const0_rtx)); | |
a157febd GK |
7976 | } |
7977 | else if (GET_CODE (stack_limit_rtx) == SYMBOL_REF | |
9ebbca7d | 7978 | && TARGET_32BIT |
f607bc57 | 7979 | && DEFAULT_ABI == ABI_V4) |
a157febd | 7980 | { |
9ebbca7d GK |
7981 | rtx toload = gen_rtx_CONST (VOIDmode, |
7982 | gen_rtx_PLUS (Pmode, | |
7983 | stack_limit_rtx, | |
7984 | GEN_INT (size))); | |
7985 | ||
7986 | emit_insn (gen_elf_high (tmp_reg, toload)); | |
7987 | emit_insn (gen_elf_low (tmp_reg, tmp_reg, toload)); | |
7988 | emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg, | |
7989 | const0_rtx)); | |
a157febd GK |
7990 | } |
7991 | else | |
7992 | warning ("stack limit expression is not supported"); | |
7993 | } | |
7994 | ||
9ebbca7d GK |
7995 | if (copy_r12 || ! TARGET_UPDATE) |
7996 | emit_move_insn (gen_rtx_REG (Pmode, 12), stack_reg); | |
7997 | ||
38c1f2d7 MM |
7998 | if (TARGET_UPDATE) |
7999 | { | |
9ebbca7d | 8000 | if (size > 32767) |
38c1f2d7 | 8001 | { |
9ebbca7d GK |
8002 | /* Need a note here so that try_split doesn't get confused. */ |
8003 | if (get_last_insn() == NULL_RTX) | |
8004 | emit_note (0, NOTE_INSN_DELETED); | |
8005 | insn = emit_move_insn (tmp_reg, todec); | |
8006 | try_split (PATTERN (insn), insn, 0); | |
8007 | todec = tmp_reg; | |
38c1f2d7 | 8008 | } |
9ebbca7d GK |
8009 | |
8010 | if (Pmode == SImode) | |
8011 | insn = emit_insn (gen_movsi_update (stack_reg, stack_reg, | |
8012 | todec, stack_reg)); | |
8013 | else | |
8014 | insn = emit_insn (gen_movdi_update (stack_reg, stack_reg, | |
8015 | todec, stack_reg)); | |
38c1f2d7 MM |
8016 | } |
8017 | else | |
8018 | { | |
9ebbca7d GK |
8019 | if (Pmode == SImode) |
8020 | insn = emit_insn (gen_addsi3 (stack_reg, stack_reg, todec)); | |
38c1f2d7 | 8021 | else |
9ebbca7d GK |
8022 | insn = emit_insn (gen_adddi3 (stack_reg, stack_reg, todec)); |
8023 | emit_move_insn (gen_rtx_MEM (Pmode, stack_reg), | |
8024 | gen_rtx_REG (Pmode, 12)); | |
8025 | } | |
8026 | ||
8027 | RTX_FRAME_RELATED_P (insn) = 1; | |
8028 | REG_NOTES (insn) = | |
8029 | gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, | |
8030 | gen_rtx_SET (VOIDmode, stack_reg, | |
8031 | gen_rtx_PLUS (Pmode, stack_reg, | |
8032 | GEN_INT (-size))), | |
8033 | REG_NOTES (insn)); | |
8034 | } | |
8035 | ||
9aa86737 AH |
8036 | /* Add a RTX_FRAME_RELATED note so that dwarf2out_frame_debug_expr |
8037 | knows that: | |
8038 | ||
8039 | (mem (plus (blah) (regXX))) | |
8040 | ||
8041 | is really: | |
8042 | ||
8043 | (mem (plus (blah) (const VALUE_OF_REGXX))). */ | |
8044 | ||
8045 | static void | |
8046 | altivec_frame_fixup (insn, reg, val) | |
8047 | rtx insn, reg; | |
8048 | HOST_WIDE_INT val; | |
8049 | { | |
8050 | rtx real; | |
8051 | ||
8052 | real = copy_rtx (PATTERN (insn)); | |
8053 | ||
8054 | real = replace_rtx (real, reg, GEN_INT (val)); | |
8055 | ||
8056 | RTX_FRAME_RELATED_P (insn) = 1; | |
8057 | REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, | |
8058 | real, | |
8059 | REG_NOTES (insn)); | |
8060 | } | |
8061 | ||
a4f6c312 SS |
8062 | /* Add to 'insn' a note which is PATTERN (INSN) but with REG replaced |
8063 | with (plus:P (reg 1) VAL), and with REG2 replaced with RREG if REG2 | |
8064 | is not NULL. It would be nice if dwarf2out_frame_debug_expr could | |
8065 | deduce these equivalences by itself so it wasn't necessary to hold | |
8066 | its hand so much. */ | |
9ebbca7d GK |
8067 | |
8068 | static void | |
8069 | rs6000_frame_related (insn, reg, val, reg2, rreg) | |
8070 | rtx insn; | |
8071 | rtx reg; | |
8072 | HOST_WIDE_INT val; | |
8073 | rtx reg2; | |
8074 | rtx rreg; | |
8075 | { | |
8076 | rtx real, temp; | |
8077 | ||
8078 | real = copy_rtx (PATTERN (insn)); | |
8079 | ||
8080 | real = replace_rtx (real, reg, | |
8081 | gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode, | |
8082 | STACK_POINTER_REGNUM), | |
8083 | GEN_INT (val))); | |
8084 | ||
8085 | /* We expect that 'real' is either a SET or a PARALLEL containing | |
8086 | SETs (and possibly other stuff). In a PARALLEL, all the SETs | |
8087 | are important so they all have to be marked RTX_FRAME_RELATED_P. */ | |
8088 | ||
8089 | if (GET_CODE (real) == SET) | |
8090 | { | |
8091 | rtx set = real; | |
8092 | ||
8093 | temp = simplify_rtx (SET_SRC (set)); | |
8094 | if (temp) | |
8095 | SET_SRC (set) = temp; | |
8096 | temp = simplify_rtx (SET_DEST (set)); | |
8097 | if (temp) | |
8098 | SET_DEST (set) = temp; | |
8099 | if (GET_CODE (SET_DEST (set)) == MEM) | |
38c1f2d7 | 8100 | { |
9ebbca7d GK |
8101 | temp = simplify_rtx (XEXP (SET_DEST (set), 0)); |
8102 | if (temp) | |
8103 | XEXP (SET_DEST (set), 0) = temp; | |
38c1f2d7 | 8104 | } |
38c1f2d7 | 8105 | } |
9ebbca7d GK |
8106 | else if (GET_CODE (real) == PARALLEL) |
8107 | { | |
8108 | int i; | |
8109 | for (i = 0; i < XVECLEN (real, 0); i++) | |
8110 | if (GET_CODE (XVECEXP (real, 0, i)) == SET) | |
8111 | { | |
8112 | rtx set = XVECEXP (real, 0, i); | |
8113 | ||
8114 | temp = simplify_rtx (SET_SRC (set)); | |
8115 | if (temp) | |
8116 | SET_SRC (set) = temp; | |
8117 | temp = simplify_rtx (SET_DEST (set)); | |
8118 | if (temp) | |
8119 | SET_DEST (set) = temp; | |
8120 | if (GET_CODE (SET_DEST (set)) == MEM) | |
8121 | { | |
8122 | temp = simplify_rtx (XEXP (SET_DEST (set), 0)); | |
8123 | if (temp) | |
8124 | XEXP (SET_DEST (set), 0) = temp; | |
8125 | } | |
8126 | RTX_FRAME_RELATED_P (set) = 1; | |
8127 | } | |
8128 | } | |
8129 | else | |
a4f6c312 | 8130 | abort (); |
9ebbca7d GK |
8131 | |
8132 | if (reg2 != NULL_RTX) | |
8133 | real = replace_rtx (real, reg2, rreg); | |
8134 | ||
8135 | RTX_FRAME_RELATED_P (insn) = 1; | |
8136 | REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, | |
8137 | real, | |
8138 | REG_NOTES (insn)); | |
38c1f2d7 MM |
8139 | } |
8140 | ||
00b960c7 AH |
8141 | /* Returns an insn that has a vrsave set operation with the |
8142 | appropriate CLOBBERs. */ | |
8143 | ||
8144 | static rtx | |
9aa86737 | 8145 | generate_set_vrsave (reg, info, epiloguep) |
00b960c7 AH |
8146 | rtx reg; |
8147 | rs6000_stack_t *info; | |
9aa86737 | 8148 | int epiloguep; |
00b960c7 AH |
8149 | { |
8150 | int nclobs, i; | |
8151 | rtx insn, clobs[TOTAL_ALTIVEC_REGS + 1]; | |
a004eb82 | 8152 | rtx vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO); |
00b960c7 | 8153 | |
a004eb82 AH |
8154 | clobs[0] |
8155 | = gen_rtx_SET (VOIDmode, | |
8156 | vrsave, | |
8157 | gen_rtx_UNSPEC_VOLATILE (SImode, | |
8158 | gen_rtvec (2, reg, vrsave), | |
8159 | 30)); | |
00b960c7 AH |
8160 | |
8161 | nclobs = 1; | |
8162 | ||
9aa86737 AH |
8163 | /* We need to clobber the registers in the mask so the scheduler |
8164 | does not move sets to VRSAVE before sets of AltiVec registers. | |
8165 | ||
8166 | However, if the function receives nonlocal gotos, reload will set | |
8167 | all call saved registers live. We will end up with: | |
8168 | ||
8169 | (set (reg 999) (mem)) | |
8170 | (parallel [ (set (reg vrsave) (unspec blah)) | |
8171 | (clobber (reg 999))]) | |
8172 | ||
8173 | The clobber will cause the store into reg 999 to be dead, and | |
8174 | flow will attempt to delete an epilogue insn. In this case, we | |
8175 | need an unspec use/set of the register. */ | |
00b960c7 AH |
8176 | |
8177 | for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i) | |
8178 | if (info->vrsave_mask != 0 && ALTIVEC_REG_BIT (i) != 0) | |
9aa86737 AH |
8179 | { |
8180 | if (!epiloguep || call_used_regs [i]) | |
8181 | clobs[nclobs++] = gen_rtx_CLOBBER (VOIDmode, | |
8182 | gen_rtx_REG (V4SImode, i)); | |
8183 | else | |
8184 | { | |
8185 | rtx reg = gen_rtx_REG (V4SImode, i); | |
9aa86737 AH |
8186 | |
8187 | clobs[nclobs++] | |
a004eb82 AH |
8188 | = gen_rtx_SET (VOIDmode, |
8189 | reg, | |
8190 | gen_rtx_UNSPEC (V4SImode, | |
8191 | gen_rtvec (1, reg), 27)); | |
9aa86737 AH |
8192 | } |
8193 | } | |
00b960c7 AH |
8194 | |
8195 | insn = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (nclobs)); | |
8196 | ||
8197 | for (i = 0; i < nclobs; ++i) | |
8198 | XVECEXP (insn, 0, i) = clobs[i]; | |
8199 | ||
8200 | return insn; | |
8201 | } | |
8202 | ||
9ebbca7d GK |
8203 | /* Emit function prologue as insns. */ |
8204 | ||
9878760c | 8205 | void |
83720594 | 8206 | rs6000_emit_prologue () |
9878760c | 8207 | { |
4697a36c | 8208 | rs6000_stack_t *info = rs6000_stack_info (); |
9ebbca7d GK |
8209 | enum machine_mode reg_mode = TARGET_POWERPC64 ? DImode : SImode; |
8210 | int reg_size = TARGET_POWERPC64 ? 8 : 4; | |
8211 | rtx sp_reg_rtx = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM); | |
8212 | rtx frame_ptr_rtx = gen_rtx_REG (Pmode, 12); | |
8213 | rtx frame_reg_rtx = sp_reg_rtx; | |
8214 | rtx cr_save_rtx = NULL; | |
8215 | rtx insn; | |
8216 | int saving_FPRs_inline; | |
8217 | int using_store_multiple; | |
8218 | HOST_WIDE_INT sp_offset = 0; | |
8219 | ||
8220 | using_store_multiple = (TARGET_MULTIPLE && ! TARGET_POWERPC64 | |
8221 | && info->first_gp_reg_save < 31); | |
8222 | saving_FPRs_inline = (info->first_fp_reg_save == 64 | |
8223 | || FP_SAVE_INLINE (info->first_fp_reg_save)); | |
8224 | ||
8225 | /* For V.4, update stack before we do any saving and set back pointer. */ | |
f607bc57 | 8226 | if (info->push_p && DEFAULT_ABI == ABI_V4) |
9ebbca7d GK |
8227 | { |
8228 | if (info->total_size < 32767) | |
8229 | sp_offset = info->total_size; | |
8230 | else | |
8231 | frame_reg_rtx = frame_ptr_rtx; | |
8232 | rs6000_emit_allocate_stack (info->total_size, | |
8233 | (frame_reg_rtx != sp_reg_rtx | |
8234 | && (info->cr_save_p | |
8235 | || info->lr_save_p | |
8236 | || info->first_fp_reg_save < 64 | |
8237 | || info->first_gp_reg_save < 32 | |
8238 | ))); | |
8239 | if (frame_reg_rtx != sp_reg_rtx) | |
8240 | rs6000_emit_stack_tie (); | |
8241 | } | |
8242 | ||
9aa86737 AH |
8243 | /* Save AltiVec registers if needed. */ |
8244 | if (TARGET_ALTIVEC_ABI && info->altivec_size != 0) | |
8245 | { | |
8246 | int i; | |
8247 | ||
8248 | /* There should be a non inline version of this, for when we | |
8249 | are saving lots of vector registers. */ | |
8250 | for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i) | |
8251 | if (info->vrsave_mask & ALTIVEC_REG_BIT (i)) | |
8252 | { | |
8253 | rtx areg, savereg, mem; | |
8254 | int offset; | |
8255 | ||
8256 | offset = info->altivec_save_offset + sp_offset | |
8257 | + 16 * (i - info->first_altivec_reg_save); | |
8258 | ||
8259 | savereg = gen_rtx_REG (V4SImode, i); | |
8260 | ||
8261 | areg = gen_rtx_REG (Pmode, 0); | |
8262 | emit_move_insn (areg, GEN_INT (offset)); | |
8263 | ||
8264 | /* AltiVec addressing mode is [reg+reg]. */ | |
8265 | mem = gen_rtx_MEM (V4SImode, | |
8266 | gen_rtx_PLUS (Pmode, frame_reg_rtx, areg)); | |
8267 | ||
8268 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
8269 | ||
8270 | insn = emit_move_insn (mem, savereg); | |
8271 | ||
8272 | altivec_frame_fixup (insn, areg, offset); | |
8273 | } | |
8274 | } | |
8275 | ||
8276 | /* VRSAVE is a bit vector representing which AltiVec registers | |
8277 | are used. The OS uses this to determine which vector | |
8278 | registers to save on a context switch. We need to save | |
8279 | VRSAVE on the stack frame, add whatever AltiVec registers we | |
8280 | used in this function, and do the corresponding magic in the | |
8281 | epilogue. */ | |
8282 | ||
8283 | if (TARGET_ALTIVEC && info->vrsave_mask != 0) | |
8284 | { | |
a004eb82 | 8285 | rtx reg, mem, vrsave; |
9aa86737 AH |
8286 | int offset; |
8287 | ||
8288 | /* Get VRSAVE onto a GPR. */ | |
8289 | reg = gen_rtx_REG (SImode, 12); | |
a004eb82 AH |
8290 | vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO); |
8291 | emit_insn (gen_rtx_SET (VOIDmode, reg, vrsave)); | |
9aa86737 AH |
8292 | |
8293 | /* Save VRSAVE. */ | |
8294 | offset = info->vrsave_save_offset + sp_offset; | |
8295 | mem | |
8296 | = gen_rtx_MEM (SImode, | |
8297 | gen_rtx_PLUS (Pmode, frame_reg_rtx, GEN_INT (offset))); | |
8298 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
8299 | insn = emit_move_insn (mem, reg); | |
8300 | ||
8301 | /* Include the registers in the mask. */ | |
8302 | emit_insn (gen_iorsi3 (reg, reg, GEN_INT ((int) info->vrsave_mask))); | |
8303 | ||
8304 | insn = emit_insn (generate_set_vrsave (reg, info, 0)); | |
8305 | } | |
8306 | ||
9ebbca7d GK |
8307 | /* If we use the link register, get it into r0. */ |
8308 | if (info->lr_save_p) | |
71f123ca | 8309 | emit_move_insn (gen_rtx_REG (Pmode, 0), |
9ebbca7d GK |
8310 | gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)); |
8311 | ||
8312 | /* If we need to save CR, put it into r12. */ | |
8313 | if (info->cr_save_p && frame_reg_rtx != frame_ptr_rtx) | |
8314 | { | |
8315 | cr_save_rtx = gen_rtx_REG (SImode, 12); | |
8316 | emit_insn (gen_movesi_from_cr (cr_save_rtx)); | |
8317 | } | |
8318 | ||
a4f6c312 SS |
8319 | /* Do any required saving of fpr's. If only one or two to save, do |
8320 | it ourselves. Otherwise, call function. */ | |
9ebbca7d GK |
8321 | if (saving_FPRs_inline) |
8322 | { | |
8323 | int i; | |
8324 | for (i = 0; i < 64 - info->first_fp_reg_save; i++) | |
8325 | if ((regs_ever_live[info->first_fp_reg_save+i] | |
8326 | && ! call_used_regs[info->first_fp_reg_save+i])) | |
8327 | { | |
8328 | rtx addr, reg, mem; | |
8329 | reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i); | |
8330 | addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
8331 | GEN_INT (info->fp_save_offset | |
8332 | + sp_offset | |
a4f6c312 | 8333 | + 8 * i)); |
9ebbca7d | 8334 | mem = gen_rtx_MEM (DFmode, addr); |
ba4828e0 | 8335 | set_mem_alias_set (mem, rs6000_sr_alias_set); |
9ebbca7d GK |
8336 | |
8337 | insn = emit_move_insn (mem, reg); | |
8338 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, | |
8339 | NULL_RTX, NULL_RTX); | |
8340 | } | |
8341 | } | |
8342 | else if (info->first_fp_reg_save != 64) | |
8343 | { | |
8344 | int i; | |
8345 | char rname[30]; | |
520a57c8 | 8346 | const char *alloc_rname; |
9ebbca7d GK |
8347 | rtvec p; |
8348 | p = rtvec_alloc (2 + 64 - info->first_fp_reg_save); | |
8349 | ||
8350 | RTVEC_ELT (p, 0) = gen_rtx_CLOBBER (VOIDmode, | |
8351 | gen_rtx_REG (Pmode, | |
8352 | LINK_REGISTER_REGNUM)); | |
8353 | sprintf (rname, "%s%d%s", SAVE_FP_PREFIX, | |
8354 | info->first_fp_reg_save - 32, SAVE_FP_SUFFIX); | |
a8a05998 | 8355 | alloc_rname = ggc_strdup (rname); |
9ebbca7d GK |
8356 | RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode, |
8357 | gen_rtx_SYMBOL_REF (Pmode, | |
8358 | alloc_rname)); | |
8359 | for (i = 0; i < 64 - info->first_fp_reg_save; i++) | |
8360 | { | |
8361 | rtx addr, reg, mem; | |
8362 | reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i); | |
8363 | addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
8364 | GEN_INT (info->fp_save_offset | |
8365 | + sp_offset + 8*i)); | |
8366 | mem = gen_rtx_MEM (DFmode, addr); | |
ba4828e0 | 8367 | set_mem_alias_set (mem, rs6000_sr_alias_set); |
9ebbca7d GK |
8368 | |
8369 | RTVEC_ELT (p, i + 2) = gen_rtx_SET (VOIDmode, mem, reg); | |
8370 | } | |
8371 | insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p)); | |
8372 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, | |
8373 | NULL_RTX, NULL_RTX); | |
8374 | } | |
b6c9286a | 8375 | |
9ebbca7d GK |
8376 | /* Save GPRs. This is done as a PARALLEL if we are using |
8377 | the store-multiple instructions. */ | |
8378 | if (using_store_multiple) | |
b6c9286a | 8379 | { |
9ebbca7d GK |
8380 | rtvec p, dwarfp; |
8381 | int i; | |
8382 | p = rtvec_alloc (32 - info->first_gp_reg_save); | |
8383 | dwarfp = rtvec_alloc (32 - info->first_gp_reg_save); | |
8384 | for (i = 0; i < 32 - info->first_gp_reg_save; i++) | |
8385 | { | |
8386 | rtx addr, reg, mem; | |
8387 | reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i); | |
8388 | addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
8389 | GEN_INT (info->gp_save_offset | |
8390 | + sp_offset | |
8391 | + reg_size * i)); | |
8392 | mem = gen_rtx_MEM (reg_mode, addr); | |
ba4828e0 | 8393 | set_mem_alias_set (mem, rs6000_sr_alias_set); |
9ebbca7d GK |
8394 | |
8395 | RTVEC_ELT (p, i) = gen_rtx_SET (VOIDmode, mem, reg); | |
8396 | } | |
8397 | insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p)); | |
8398 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, | |
8399 | NULL_RTX, NULL_RTX); | |
b6c9286a MM |
8400 | } |
8401 | else | |
8402 | { | |
9ebbca7d GK |
8403 | int i; |
8404 | for (i = 0; i < 32 - info->first_gp_reg_save; i++) | |
8405 | if ((regs_ever_live[info->first_gp_reg_save+i] | |
8406 | && ! call_used_regs[info->first_gp_reg_save+i]) | |
8407 | || (i+info->first_gp_reg_save == PIC_OFFSET_TABLE_REGNUM | |
f607bc57 ZW |
8408 | && ((DEFAULT_ABI == ABI_V4 && flag_pic == 1) |
8409 | || (DEFAULT_ABI == ABI_DARWIN && flag_pic)))) | |
9ebbca7d GK |
8410 | { |
8411 | rtx addr, reg, mem; | |
8412 | reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i); | |
8413 | addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
8414 | GEN_INT (info->gp_save_offset | |
8415 | + sp_offset | |
8416 | + reg_size * i)); | |
8417 | mem = gen_rtx_MEM (reg_mode, addr); | |
ba4828e0 | 8418 | set_mem_alias_set (mem, rs6000_sr_alias_set); |
9ebbca7d GK |
8419 | |
8420 | insn = emit_move_insn (mem, reg); | |
8421 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, | |
8422 | NULL_RTX, NULL_RTX); | |
8423 | } | |
8424 | } | |
8425 | ||
83720594 RH |
8426 | /* ??? There's no need to emit actual instructions here, but it's the |
8427 | easiest way to get the frame unwind information emitted. */ | |
8428 | if (current_function_calls_eh_return) | |
8429 | { | |
78e1b90d DE |
8430 | unsigned int i, regno; |
8431 | ||
83720594 RH |
8432 | for (i = 0; ; ++i) |
8433 | { | |
8434 | rtx addr, reg, mem; | |
8435 | ||
8436 | regno = EH_RETURN_DATA_REGNO (i); | |
8437 | if (regno == INVALID_REGNUM) | |
8438 | break; | |
8439 | ||
8440 | reg = gen_rtx_REG (reg_mode, regno); | |
8441 | addr = plus_constant (frame_reg_rtx, | |
78e1b90d DE |
8442 | info->ehrd_offset + sp_offset |
8443 | + reg_size * (int) i); | |
83720594 | 8444 | mem = gen_rtx_MEM (reg_mode, addr); |
ba4828e0 | 8445 | set_mem_alias_set (mem, rs6000_sr_alias_set); |
83720594 RH |
8446 | |
8447 | insn = emit_move_insn (mem, reg); | |
8448 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, | |
8449 | NULL_RTX, NULL_RTX); | |
8450 | } | |
8451 | } | |
8452 | ||
9ebbca7d GK |
8453 | /* Save lr if we used it. */ |
8454 | if (info->lr_save_p) | |
8455 | { | |
8456 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
8457 | GEN_INT (info->lr_save_offset + sp_offset)); | |
8458 | rtx reg = gen_rtx_REG (Pmode, 0); | |
8459 | rtx mem = gen_rtx_MEM (Pmode, addr); | |
8460 | /* This should not be of rs6000_sr_alias_set, because of | |
8461 | __builtin_return_address. */ | |
8462 | ||
8463 | insn = emit_move_insn (mem, reg); | |
8464 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, | |
8465 | reg, gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)); | |
8466 | } | |
8467 | ||
8468 | /* Save CR if we use any that must be preserved. */ | |
8469 | if (info->cr_save_p) | |
8470 | { | |
8471 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
8472 | GEN_INT (info->cr_save_offset + sp_offset)); | |
8473 | rtx mem = gen_rtx_MEM (SImode, addr); | |
ba4828e0 RK |
8474 | |
8475 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
9ebbca7d GK |
8476 | |
8477 | /* If r12 was used to hold the original sp, copy cr into r0 now | |
8478 | that it's free. */ | |
8479 | if (REGNO (frame_reg_rtx) == 12) | |
8480 | { | |
8481 | cr_save_rtx = gen_rtx_REG (SImode, 0); | |
8482 | emit_insn (gen_movesi_from_cr (cr_save_rtx)); | |
8483 | } | |
8484 | insn = emit_move_insn (mem, cr_save_rtx); | |
8485 | ||
8486 | /* Now, there's no way that dwarf2out_frame_debug_expr is going | |
8487 | to understand '(unspec:SI [(reg:CC 68) ...] 19)'. But that's | |
8488 | OK. All we have to do is specify that _one_ condition code | |
8489 | register is saved in this stack slot. The thrower's epilogue | |
a1dc9455 FS |
8490 | will then restore all the call-saved registers. |
8491 | We use CR2_REGNO (70) to be compatible with gcc-2.95 on Linux. */ | |
9ebbca7d | 8492 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, |
a1dc9455 | 8493 | cr_save_rtx, gen_rtx_REG (SImode, CR2_REGNO)); |
9ebbca7d GK |
8494 | } |
8495 | ||
8496 | /* Update stack and set back pointer unless this is V.4, | |
8497 | for which it was done previously. */ | |
f607bc57 | 8498 | if (info->push_p && DEFAULT_ABI != ABI_V4) |
9ebbca7d GK |
8499 | rs6000_emit_allocate_stack (info->total_size, FALSE); |
8500 | ||
8501 | /* Set frame pointer, if needed. */ | |
8502 | if (frame_pointer_needed) | |
8503 | { | |
8504 | insn = emit_move_insn (gen_rtx_REG (reg_mode, FRAME_POINTER_REGNUM), | |
8505 | sp_reg_rtx); | |
8506 | RTX_FRAME_RELATED_P (insn) = 1; | |
b6c9286a | 8507 | } |
9878760c | 8508 | |
9ebbca7d GK |
8509 | /* If we are using PIC_OFFSET_TABLE_REGNUM, we need to set it up. */ |
8510 | if ((TARGET_TOC && TARGET_MINIMAL_TOC && get_pool_size () != 0) | |
f607bc57 ZW |
8511 | || (DEFAULT_ABI == ABI_V4 && flag_pic == 1 |
8512 | && regs_ever_live[PIC_OFFSET_TABLE_REGNUM])) | |
9ebbca7d GK |
8513 | { |
8514 | /* If emit_load_toc_table will use the link register, we need to save | |
8515 | it. We use R11 for this purpose because emit_load_toc_table | |
8516 | can use register 0. This allows us to use a plain 'blr' to return | |
8517 | from the procedure more often. */ | |
d5fa86ba GK |
8518 | int save_LR_around_toc_setup = (TARGET_ELF && flag_pic != 0 |
8519 | && ! info->lr_save_p | |
8520 | && EXIT_BLOCK_PTR->pred != NULL); | |
9ebbca7d GK |
8521 | if (save_LR_around_toc_setup) |
8522 | emit_move_insn (gen_rtx_REG (Pmode, 11), | |
8523 | gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)); | |
8524 | ||
8525 | rs6000_emit_load_toc_table (TRUE); | |
8526 | ||
8527 | if (save_LR_around_toc_setup) | |
8528 | emit_move_insn (gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM), | |
8529 | gen_rtx_REG (Pmode, 11)); | |
8530 | } | |
ee890fe2 SS |
8531 | |
8532 | if (DEFAULT_ABI == ABI_DARWIN | |
8533 | && flag_pic && current_function_uses_pic_offset_table) | |
8534 | { | |
8535 | rtx dest = gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM); | |
8536 | ||
8537 | rs6000_maybe_dead (emit_insn (gen_load_macho_picbase (dest))); | |
8538 | ||
8539 | rs6000_maybe_dead ( | |
8540 | emit_move_insn (gen_rtx_REG (Pmode, PIC_OFFSET_TABLE_REGNUM), | |
8541 | gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM))); | |
8542 | } | |
9ebbca7d GK |
8543 | } |
8544 | ||
9ebbca7d | 8545 | /* Write function prologue. */ |
a4f6c312 | 8546 | |
08c148a8 NB |
8547 | static void |
8548 | rs6000_output_function_prologue (file, size) | |
9ebbca7d | 8549 | FILE *file; |
08c148a8 | 8550 | HOST_WIDE_INT size ATTRIBUTE_UNUSED; |
9ebbca7d GK |
8551 | { |
8552 | rs6000_stack_t *info = rs6000_stack_info (); | |
8553 | ||
4697a36c MM |
8554 | if (TARGET_DEBUG_STACK) |
8555 | debug_stack_info (info); | |
9878760c | 8556 | |
a4f6c312 SS |
8557 | /* Write .extern for any function we will call to save and restore |
8558 | fp values. */ | |
8559 | if (info->first_fp_reg_save < 64 | |
8560 | && !FP_SAVE_INLINE (info->first_fp_reg_save)) | |
4d30c363 | 8561 | fprintf (file, "\t.extern %s%d%s\n\t.extern %s%d%s\n", |
4697a36c | 8562 | SAVE_FP_PREFIX, info->first_fp_reg_save - 32, SAVE_FP_SUFFIX, |
a4f6c312 SS |
8563 | RESTORE_FP_PREFIX, info->first_fp_reg_save - 32, |
8564 | RESTORE_FP_SUFFIX); | |
9878760c | 8565 | |
c764f757 RK |
8566 | /* Write .extern for AIX common mode routines, if needed. */ |
8567 | if (! TARGET_POWER && ! TARGET_POWERPC && ! common_mode_defined) | |
8568 | { | |
f6709c70 JW |
8569 | fputs ("\t.extern __mulh\n", file); |
8570 | fputs ("\t.extern __mull\n", file); | |
8571 | fputs ("\t.extern __divss\n", file); | |
8572 | fputs ("\t.extern __divus\n", file); | |
8573 | fputs ("\t.extern __quoss\n", file); | |
8574 | fputs ("\t.extern __quous\n", file); | |
c764f757 RK |
8575 | common_mode_defined = 1; |
8576 | } | |
9878760c | 8577 | |
9ebbca7d | 8578 | if (! HAVE_prologue) |
979721f8 | 8579 | { |
9ebbca7d GK |
8580 | start_sequence (); |
8581 | ||
a4f6c312 SS |
8582 | /* A NOTE_INSN_DELETED is supposed to be at the start and end of |
8583 | the "toplevel" insn chain. */ | |
9ebbca7d GK |
8584 | emit_note (0, NOTE_INSN_DELETED); |
8585 | rs6000_emit_prologue (); | |
8586 | emit_note (0, NOTE_INSN_DELETED); | |
8587 | ||
8588 | if (TARGET_DEBUG_STACK) | |
a4f6c312 SS |
8589 | debug_rtx_list (get_insns (), 100); |
8590 | final (get_insns (), file, FALSE, FALSE); | |
9ebbca7d | 8591 | end_sequence (); |
979721f8 MM |
8592 | } |
8593 | ||
9ebbca7d GK |
8594 | rs6000_pic_labelno++; |
8595 | } | |
8596 | ||
8597 | /* Emit function epilogue as insns. | |
9878760c | 8598 | |
9ebbca7d GK |
8599 | At present, dwarf2out_frame_debug_expr doesn't understand |
8600 | register restores, so we don't bother setting RTX_FRAME_RELATED_P | |
8601 | anywhere in the epilogue. Most of the insns below would in any case | |
8602 | need special notes to explain where r11 is in relation to the stack. */ | |
9878760c | 8603 | |
9ebbca7d | 8604 | void |
83720594 | 8605 | rs6000_emit_epilogue (sibcall) |
9ebbca7d GK |
8606 | int sibcall; |
8607 | { | |
8608 | rs6000_stack_t *info; | |
8609 | int restoring_FPRs_inline; | |
8610 | int using_load_multiple; | |
8611 | int using_mfcr_multiple; | |
8612 | int use_backchain_to_restore_sp; | |
8613 | int sp_offset = 0; | |
8614 | rtx sp_reg_rtx = gen_rtx_REG (Pmode, 1); | |
8615 | rtx frame_reg_rtx = sp_reg_rtx; | |
8616 | enum machine_mode reg_mode = TARGET_POWERPC64 ? DImode : SImode; | |
8617 | int reg_size = TARGET_POWERPC64 ? 8 : 4; | |
8618 | int i; | |
8619 | ||
8620 | info = rs6000_stack_info (); | |
8621 | using_load_multiple = (TARGET_MULTIPLE && ! TARGET_POWERPC64 | |
8622 | && info->first_gp_reg_save < 31); | |
8623 | restoring_FPRs_inline = (sibcall | |
83720594 | 8624 | || current_function_calls_eh_return |
9ebbca7d GK |
8625 | || info->first_fp_reg_save == 64 |
8626 | || FP_SAVE_INLINE (info->first_fp_reg_save)); | |
8627 | use_backchain_to_restore_sp = (frame_pointer_needed | |
8628 | || current_function_calls_alloca | |
8629 | || info->total_size > 32767); | |
8630 | using_mfcr_multiple = (rs6000_cpu == PROCESSOR_PPC601 | |
8631 | || rs6000_cpu == PROCESSOR_PPC603 | |
8632 | || rs6000_cpu == PROCESSOR_PPC750 | |
8633 | || optimize_size); | |
8634 | ||
8635 | /* If we have a frame pointer, a call to alloca, or a large stack | |
8636 | frame, restore the old stack pointer using the backchain. Otherwise, | |
8637 | we know what size to update it with. */ | |
8638 | if (use_backchain_to_restore_sp) | |
bacbde18 | 8639 | { |
9ebbca7d GK |
8640 | /* Under V.4, don't reset the stack pointer until after we're done |
8641 | loading the saved registers. */ | |
f607bc57 | 8642 | if (DEFAULT_ABI == ABI_V4) |
9ebbca7d | 8643 | frame_reg_rtx = gen_rtx_REG (Pmode, 11); |
4697a36c | 8644 | |
9ebbca7d GK |
8645 | emit_move_insn (frame_reg_rtx, |
8646 | gen_rtx_MEM (Pmode, sp_reg_rtx)); | |
8647 | ||
bacbde18 | 8648 | } |
9ebbca7d | 8649 | else if (info->push_p) |
85638c0d | 8650 | { |
f607bc57 | 8651 | if (DEFAULT_ABI == ABI_V4) |
9ebbca7d GK |
8652 | sp_offset = info->total_size; |
8653 | else | |
8654 | { | |
8655 | emit_insn (TARGET_32BIT | |
8656 | ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx, | |
8657 | GEN_INT (info->total_size)) | |
8658 | : gen_adddi3 (sp_reg_rtx, sp_reg_rtx, | |
8659 | GEN_INT (info->total_size))); | |
8660 | } | |
85638c0d | 8661 | } |
9ebbca7d | 8662 | |
9aa86737 AH |
8663 | /* Restore AltiVec registers if needed. */ |
8664 | if (TARGET_ALTIVEC_ABI && info->altivec_size != 0) | |
8665 | { | |
8666 | int i; | |
8667 | ||
8668 | for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i) | |
8669 | if (info->vrsave_mask & ALTIVEC_REG_BIT (i)) | |
8670 | { | |
8671 | rtx addr, areg, mem; | |
8672 | ||
8673 | areg = gen_rtx_REG (Pmode, 0); | |
8674 | emit_move_insn | |
8675 | (areg, GEN_INT (info->altivec_save_offset | |
8676 | + sp_offset | |
8677 | + 16 * (i - info->first_altivec_reg_save))); | |
8678 | ||
8679 | /* AltiVec addressing mode is [reg+reg]. */ | |
8680 | addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, areg); | |
8681 | mem = gen_rtx_MEM (V4SImode, addr); | |
8682 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
8683 | ||
8684 | emit_move_insn (gen_rtx_REG (V4SImode, i), mem); | |
8685 | } | |
8686 | } | |
8687 | ||
8688 | /* Restore VRSAVE if needed. */ | |
8689 | if (TARGET_ALTIVEC_ABI && info->vrsave_mask != 0) | |
8690 | { | |
8691 | rtx addr, mem, reg; | |
8692 | ||
8693 | addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
8694 | GEN_INT (info->vrsave_save_offset + sp_offset)); | |
8695 | mem = gen_rtx_MEM (SImode, addr); | |
8696 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
8697 | reg = gen_rtx_REG (SImode, 12); | |
8698 | emit_move_insn (reg, mem); | |
8699 | ||
8700 | emit_insn (generate_set_vrsave (reg, info, 1)); | |
8701 | } | |
8702 | ||
9ebbca7d GK |
8703 | /* Get the old lr if we saved it. */ |
8704 | if (info->lr_save_p) | |
b6c9286a | 8705 | { |
9ebbca7d GK |
8706 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, |
8707 | GEN_INT (info->lr_save_offset + sp_offset)); | |
8708 | rtx mem = gen_rtx_MEM (Pmode, addr); | |
ba4828e0 RK |
8709 | |
8710 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
b6c9286a | 8711 | |
9ebbca7d | 8712 | emit_move_insn (gen_rtx_REG (Pmode, 0), mem); |
b6c9286a | 8713 | } |
9ebbca7d GK |
8714 | |
8715 | /* Get the old cr if we saved it. */ | |
8716 | if (info->cr_save_p) | |
8717 | { | |
8718 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
8719 | GEN_INT (info->cr_save_offset + sp_offset)); | |
8720 | rtx mem = gen_rtx_MEM (SImode, addr); | |
ba4828e0 RK |
8721 | |
8722 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
b6c9286a | 8723 | |
9ebbca7d GK |
8724 | emit_move_insn (gen_rtx_REG (SImode, 12), mem); |
8725 | } | |
8726 | ||
8727 | /* Set LR here to try to overlap restores below. */ | |
4697a36c | 8728 | if (info->lr_save_p) |
9ebbca7d GK |
8729 | emit_move_insn (gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM), |
8730 | gen_rtx_REG (Pmode, 0)); | |
8731 | ||
83720594 RH |
8732 | /* Load exception handler data registers, if needed. */ |
8733 | if (current_function_calls_eh_return) | |
8734 | { | |
78e1b90d DE |
8735 | unsigned int i, regno; |
8736 | ||
83720594 RH |
8737 | for (i = 0; ; ++i) |
8738 | { | |
8739 | rtx addr, mem; | |
8740 | ||
8741 | regno = EH_RETURN_DATA_REGNO (i); | |
8742 | if (regno == INVALID_REGNUM) | |
8743 | break; | |
8744 | ||
8745 | addr = plus_constant (frame_reg_rtx, | |
78e1b90d DE |
8746 | info->ehrd_offset + sp_offset |
8747 | + reg_size * (int) i); | |
83720594 | 8748 | mem = gen_rtx_MEM (reg_mode, addr); |
ba4828e0 | 8749 | set_mem_alias_set (mem, rs6000_sr_alias_set); |
83720594 RH |
8750 | |
8751 | emit_move_insn (gen_rtx_REG (reg_mode, regno), mem); | |
8752 | } | |
8753 | } | |
9ebbca7d GK |
8754 | |
8755 | /* Restore GPRs. This is done as a PARALLEL if we are using | |
8756 | the load-multiple instructions. */ | |
8757 | if (using_load_multiple) | |
979721f8 | 8758 | { |
9ebbca7d GK |
8759 | rtvec p; |
8760 | p = rtvec_alloc (32 - info->first_gp_reg_save); | |
8761 | for (i = 0; i < 32 - info->first_gp_reg_save; i++) | |
979721f8 | 8762 | { |
9ebbca7d GK |
8763 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, |
8764 | GEN_INT (info->gp_save_offset | |
8765 | + sp_offset | |
8766 | + reg_size * i)); | |
8767 | rtx mem = gen_rtx_MEM (reg_mode, addr); | |
ba4828e0 RK |
8768 | |
8769 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
9ebbca7d GK |
8770 | |
8771 | RTVEC_ELT (p, i) = | |
8772 | gen_rtx_SET (VOIDmode, | |
8773 | gen_rtx_REG (reg_mode, info->first_gp_reg_save + i), | |
8774 | mem); | |
979721f8 | 8775 | } |
9ebbca7d | 8776 | emit_insn (gen_rtx_PARALLEL (VOIDmode, p)); |
979721f8 | 8777 | } |
9ebbca7d GK |
8778 | else |
8779 | for (i = 0; i < 32 - info->first_gp_reg_save; i++) | |
8780 | if ((regs_ever_live[info->first_gp_reg_save+i] | |
8781 | && ! call_used_regs[info->first_gp_reg_save+i]) | |
8782 | || (i+info->first_gp_reg_save == PIC_OFFSET_TABLE_REGNUM | |
f607bc57 ZW |
8783 | && ((DEFAULT_ABI == ABI_V4 && flag_pic == 1) |
8784 | || (DEFAULT_ABI == ABI_DARWIN && flag_pic)))) | |
9ebbca7d GK |
8785 | { |
8786 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
8787 | GEN_INT (info->gp_save_offset | |
8788 | + sp_offset | |
8789 | + reg_size * i)); | |
8790 | rtx mem = gen_rtx_MEM (reg_mode, addr); | |
ba4828e0 RK |
8791 | |
8792 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
9ebbca7d GK |
8793 | |
8794 | emit_move_insn (gen_rtx_REG (reg_mode, | |
8795 | info->first_gp_reg_save + i), | |
8796 | mem); | |
8797 | } | |
9878760c | 8798 | |
9ebbca7d GK |
8799 | /* Restore fpr's if we need to do it without calling a function. */ |
8800 | if (restoring_FPRs_inline) | |
8801 | for (i = 0; i < 64 - info->first_fp_reg_save; i++) | |
8802 | if ((regs_ever_live[info->first_fp_reg_save+i] | |
8803 | && ! call_used_regs[info->first_fp_reg_save+i])) | |
8804 | { | |
8805 | rtx addr, mem; | |
8806 | addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
8807 | GEN_INT (info->fp_save_offset | |
8808 | + sp_offset | |
a4f6c312 | 8809 | + 8 * i)); |
9ebbca7d | 8810 | mem = gen_rtx_MEM (DFmode, addr); |
ba4828e0 | 8811 | set_mem_alias_set (mem, rs6000_sr_alias_set); |
9ebbca7d GK |
8812 | |
8813 | emit_move_insn (gen_rtx_REG (DFmode, | |
8814 | info->first_fp_reg_save + i), | |
8815 | mem); | |
8816 | } | |
8d30c4ee | 8817 | |
9ebbca7d GK |
8818 | /* If we saved cr, restore it here. Just those that were used. */ |
8819 | if (info->cr_save_p) | |
979721f8 | 8820 | { |
9ebbca7d | 8821 | rtx r12_rtx = gen_rtx_REG (SImode, 12); |
e35b9579 | 8822 | int count = 0; |
9ebbca7d GK |
8823 | |
8824 | if (using_mfcr_multiple) | |
979721f8 | 8825 | { |
9ebbca7d GK |
8826 | for (i = 0; i < 8; i++) |
8827 | if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i]) | |
e35b9579 | 8828 | count++; |
9ebbca7d | 8829 | if (count == 0) |
e35b9579 GK |
8830 | abort (); |
8831 | } | |
8832 | ||
8833 | if (using_mfcr_multiple && count > 1) | |
8834 | { | |
8835 | rtvec p; | |
8836 | int ndx; | |
9ebbca7d | 8837 | |
e35b9579 | 8838 | p = rtvec_alloc (count); |
9ebbca7d | 8839 | |
e35b9579 | 8840 | ndx = 0; |
9ebbca7d GK |
8841 | for (i = 0; i < 8; i++) |
8842 | if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i]) | |
8843 | { | |
8844 | rtvec r = rtvec_alloc (2); | |
8845 | RTVEC_ELT (r, 0) = r12_rtx; | |
8846 | RTVEC_ELT (r, 1) = GEN_INT (1 << (7-i)); | |
e35b9579 | 8847 | RTVEC_ELT (p, ndx) = |
9ebbca7d GK |
8848 | gen_rtx_SET (VOIDmode, gen_rtx_REG (CCmode, CR0_REGNO+i), |
8849 | gen_rtx_UNSPEC (CCmode, r, 20)); | |
e35b9579 | 8850 | ndx++; |
9ebbca7d GK |
8851 | } |
8852 | emit_insn (gen_rtx_PARALLEL (VOIDmode, p)); | |
e35b9579 GK |
8853 | if (ndx != count) |
8854 | abort (); | |
979721f8 MM |
8855 | } |
8856 | else | |
9ebbca7d GK |
8857 | for (i = 0; i < 8; i++) |
8858 | if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i]) | |
979721f8 | 8859 | { |
9ebbca7d GK |
8860 | emit_insn (gen_movsi_to_cr_one (gen_rtx_REG (CCmode, |
8861 | CR0_REGNO+i), | |
8862 | r12_rtx)); | |
979721f8 | 8863 | } |
979721f8 MM |
8864 | } |
8865 | ||
9ebbca7d GK |
8866 | /* If this is V.4, unwind the stack pointer after all of the loads |
8867 | have been done. We need to emit a block here so that sched | |
8868 | doesn't decide to move the sp change before the register restores | |
8869 | (which may not have any obvious dependency on the stack). This | |
8870 | doesn't hurt performance, because there is no scheduling that can | |
8871 | be done after this point. */ | |
f607bc57 | 8872 | if (DEFAULT_ABI == ABI_V4) |
b6c9286a | 8873 | { |
9ebbca7d GK |
8874 | if (frame_reg_rtx != sp_reg_rtx) |
8875 | rs6000_emit_stack_tie (); | |
b6c9286a | 8876 | |
9ebbca7d | 8877 | if (use_backchain_to_restore_sp) |
b6c9286a | 8878 | { |
9ebbca7d | 8879 | emit_move_insn (sp_reg_rtx, frame_reg_rtx); |
b6c9286a | 8880 | } |
9ebbca7d | 8881 | else if (sp_offset != 0) |
13f1623b | 8882 | { |
9ebbca7d GK |
8883 | emit_insn (Pmode == SImode |
8884 | ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx, | |
8885 | GEN_INT (sp_offset)) | |
8886 | : gen_adddi3 (sp_reg_rtx, sp_reg_rtx, | |
8887 | GEN_INT (sp_offset))); | |
13f1623b | 8888 | } |
9ebbca7d | 8889 | } |
b6c9286a | 8890 | |
83720594 RH |
8891 | if (current_function_calls_eh_return) |
8892 | { | |
8893 | rtx sa = EH_RETURN_STACKADJ_RTX; | |
8894 | emit_insn (Pmode == SImode | |
8895 | ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx, sa) | |
8896 | : gen_adddi3 (sp_reg_rtx, sp_reg_rtx, sa)); | |
8897 | } | |
8898 | ||
9ebbca7d GK |
8899 | if (!sibcall) |
8900 | { | |
8901 | rtvec p; | |
8902 | if (! restoring_FPRs_inline) | |
8903 | p = rtvec_alloc (3 + 64 - info->first_fp_reg_save); | |
8904 | else | |
8905 | p = rtvec_alloc (2); | |
b6c9286a | 8906 | |
e35b9579 GK |
8907 | RTVEC_ELT (p, 0) = gen_rtx_RETURN (VOIDmode); |
8908 | RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode, | |
9ebbca7d GK |
8909 | gen_rtx_REG (Pmode, |
8910 | LINK_REGISTER_REGNUM)); | |
9ebbca7d GK |
8911 | |
8912 | /* If we have to restore more than two FP registers, branch to the | |
8913 | restore function. It will return to our caller. */ | |
8914 | if (! restoring_FPRs_inline) | |
8915 | { | |
8916 | int i; | |
8917 | char rname[30]; | |
520a57c8 | 8918 | const char *alloc_rname; |
979721f8 | 8919 | |
9ebbca7d GK |
8920 | sprintf (rname, "%s%d%s", RESTORE_FP_PREFIX, |
8921 | info->first_fp_reg_save - 32, RESTORE_FP_SUFFIX); | |
a8a05998 | 8922 | alloc_rname = ggc_strdup (rname); |
9ebbca7d GK |
8923 | RTVEC_ELT (p, 2) = gen_rtx_USE (VOIDmode, |
8924 | gen_rtx_SYMBOL_REF (Pmode, | |
8925 | alloc_rname)); | |
b6c9286a | 8926 | |
9ebbca7d GK |
8927 | for (i = 0; i < 64 - info->first_fp_reg_save; i++) |
8928 | { | |
8929 | rtx addr, mem; | |
8930 | addr = gen_rtx_PLUS (Pmode, sp_reg_rtx, | |
8931 | GEN_INT (info->fp_save_offset + 8*i)); | |
8932 | mem = gen_rtx_MEM (DFmode, addr); | |
ba4828e0 | 8933 | set_mem_alias_set (mem, rs6000_sr_alias_set); |
9ebbca7d GK |
8934 | |
8935 | RTVEC_ELT (p, i+3) = | |
8936 | gen_rtx_SET (VOIDmode, | |
8937 | gen_rtx_REG (DFmode, info->first_fp_reg_save + i), | |
8938 | mem); | |
b6c9286a MM |
8939 | } |
8940 | } | |
9ebbca7d GK |
8941 | |
8942 | emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p)); | |
3daf36a4 | 8943 | } |
9878760c RK |
8944 | } |
8945 | ||
8946 | /* Write function epilogue. */ | |
8947 | ||
08c148a8 NB |
8948 | static void |
8949 | rs6000_output_function_epilogue (file, size) | |
9878760c | 8950 | FILE *file; |
08c148a8 | 8951 | HOST_WIDE_INT size ATTRIBUTE_UNUSED; |
9878760c | 8952 | { |
4697a36c | 8953 | rs6000_stack_t *info = rs6000_stack_info (); |
9878760c | 8954 | |
9ebbca7d | 8955 | if (! HAVE_epilogue) |
9878760c | 8956 | { |
9ebbca7d GK |
8957 | rtx insn = get_last_insn (); |
8958 | /* If the last insn was a BARRIER, we don't have to write anything except | |
8959 | the trace table. */ | |
8960 | if (GET_CODE (insn) == NOTE) | |
8961 | insn = prev_nonnote_insn (insn); | |
8962 | if (insn == 0 || GET_CODE (insn) != BARRIER) | |
4697a36c | 8963 | { |
9ebbca7d GK |
8964 | /* This is slightly ugly, but at least we don't have two |
8965 | copies of the epilogue-emitting code. */ | |
8966 | start_sequence (); | |
8967 | ||
8968 | /* A NOTE_INSN_DELETED is supposed to be at the start | |
8969 | and end of the "toplevel" insn chain. */ | |
8970 | emit_note (0, NOTE_INSN_DELETED); | |
8971 | rs6000_emit_epilogue (FALSE); | |
8972 | emit_note (0, NOTE_INSN_DELETED); | |
8973 | ||
8974 | if (TARGET_DEBUG_STACK) | |
a4f6c312 SS |
8975 | debug_rtx_list (get_insns (), 100); |
8976 | final (get_insns (), file, FALSE, FALSE); | |
9ebbca7d | 8977 | end_sequence (); |
4697a36c | 8978 | } |
9878760c | 8979 | } |
b4ac57ab | 8980 | |
9b30bae2 | 8981 | /* Output a traceback table here. See /usr/include/sys/debug.h for info |
314fc5a9 ILT |
8982 | on its format. |
8983 | ||
8984 | We don't output a traceback table if -finhibit-size-directive was | |
8985 | used. The documentation for -finhibit-size-directive reads | |
8986 | ``don't output a @code{.size} assembler directive, or anything | |
8987 | else that would cause trouble if the function is split in the | |
8988 | middle, and the two halves are placed at locations far apart in | |
8989 | memory.'' The traceback table has this property, since it | |
8990 | includes the offset from the start of the function to the | |
4d30c363 MM |
8991 | traceback table itself. |
8992 | ||
8993 | System V.4 Powerpc's (and the embedded ABI derived from it) use a | |
b6c9286a MM |
8994 | different traceback table. */ |
8995 | if (DEFAULT_ABI == ABI_AIX && ! flag_inhibit_size_directive) | |
9b30bae2 | 8996 | { |
3cce094d | 8997 | const char *fname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0); |
3ac88239 | 8998 | const char *language_string = lang_hooks.name; |
314fc5a9 ILT |
8999 | int fixed_parms, float_parms, parm_info; |
9000 | int i; | |
9001 | ||
b6c9286a MM |
9002 | while (*fname == '.') /* V.4 encodes . in the name */ |
9003 | fname++; | |
9004 | ||
314fc5a9 ILT |
9005 | /* Need label immediately before tbtab, so we can compute its offset |
9006 | from the function start. */ | |
9007 | if (*fname == '*') | |
9008 | ++fname; | |
9009 | ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT"); | |
9010 | ASM_OUTPUT_LABEL (file, fname); | |
9011 | ||
9012 | /* The .tbtab pseudo-op can only be used for the first eight | |
9013 | expressions, since it can't handle the possibly variable | |
9014 | length fields that follow. However, if you omit the optional | |
9015 | fields, the assembler outputs zeros for all optional fields | |
9016 | anyways, giving each variable length field is minimum length | |
9017 | (as defined in sys/debug.h). Thus we can not use the .tbtab | |
9018 | pseudo-op at all. */ | |
9019 | ||
9020 | /* An all-zero word flags the start of the tbtab, for debuggers | |
9021 | that have to find it by searching forward from the entry | |
9022 | point or from the current pc. */ | |
19d2d16f | 9023 | fputs ("\t.long 0\n", file); |
314fc5a9 ILT |
9024 | |
9025 | /* Tbtab format type. Use format type 0. */ | |
19d2d16f | 9026 | fputs ("\t.byte 0,", file); |
314fc5a9 ILT |
9027 | |
9028 | /* Language type. Unfortunately, there doesn't seem to be any | |
9029 | official way to get this info, so we use language_string. C | |
9030 | is 0. C++ is 9. No number defined for Obj-C, so use the | |
9517ead8 | 9031 | value for C for now. There is no official value for Java, |
6f573ff9 | 9032 | although IBM appears to be using 13. There is no official value |
f710504c | 9033 | for Chill, so we've chosen 44 pseudo-randomly. */ |
314fc5a9 | 9034 | if (! strcmp (language_string, "GNU C") |
e2c953b6 | 9035 | || ! strcmp (language_string, "GNU Objective-C")) |
314fc5a9 ILT |
9036 | i = 0; |
9037 | else if (! strcmp (language_string, "GNU F77")) | |
9038 | i = 1; | |
9039 | else if (! strcmp (language_string, "GNU Ada")) | |
9040 | i = 3; | |
8b83775b | 9041 | else if (! strcmp (language_string, "GNU Pascal")) |
314fc5a9 ILT |
9042 | i = 2; |
9043 | else if (! strcmp (language_string, "GNU C++")) | |
9044 | i = 9; | |
9517ead8 AG |
9045 | else if (! strcmp (language_string, "GNU Java")) |
9046 | i = 13; | |
6f573ff9 JL |
9047 | else if (! strcmp (language_string, "GNU CHILL")) |
9048 | i = 44; | |
314fc5a9 ILT |
9049 | else |
9050 | abort (); | |
9051 | fprintf (file, "%d,", i); | |
9052 | ||
9053 | /* 8 single bit fields: global linkage (not set for C extern linkage, | |
9054 | apparently a PL/I convention?), out-of-line epilogue/prologue, offset | |
9055 | from start of procedure stored in tbtab, internal function, function | |
9056 | has controlled storage, function has no toc, function uses fp, | |
9057 | function logs/aborts fp operations. */ | |
9058 | /* Assume that fp operations are used if any fp reg must be saved. */ | |
4697a36c | 9059 | fprintf (file, "%d,", (1 << 5) | ((info->first_fp_reg_save != 64) << 1)); |
314fc5a9 ILT |
9060 | |
9061 | /* 6 bitfields: function is interrupt handler, name present in | |
9062 | proc table, function calls alloca, on condition directives | |
9063 | (controls stack walks, 3 bits), saves condition reg, saves | |
9064 | link reg. */ | |
9065 | /* The `function calls alloca' bit seems to be set whenever reg 31 is | |
9066 | set up as a frame pointer, even when there is no alloca call. */ | |
9067 | fprintf (file, "%d,", | |
9068 | ((1 << 6) | (frame_pointer_needed << 5) | |
4697a36c | 9069 | | (info->cr_save_p << 1) | (info->lr_save_p))); |
314fc5a9 ILT |
9070 | |
9071 | /* 3 bitfields: saves backchain, spare bit, number of fpr saved | |
9072 | (6 bits). */ | |
9073 | fprintf (file, "%d,", | |
4697a36c | 9074 | (info->push_p << 7) | (64 - info->first_fp_reg_save)); |
314fc5a9 ILT |
9075 | |
9076 | /* 2 bitfields: spare bits (2 bits), number of gpr saved (6 bits). */ | |
9077 | fprintf (file, "%d,", (32 - first_reg_to_save ())); | |
9078 | ||
9079 | { | |
9080 | /* Compute the parameter info from the function decl argument | |
9081 | list. */ | |
9082 | tree decl; | |
9083 | int next_parm_info_bit; | |
9084 | ||
9085 | next_parm_info_bit = 31; | |
9086 | parm_info = 0; | |
9087 | fixed_parms = 0; | |
9088 | float_parms = 0; | |
9089 | ||
9090 | for (decl = DECL_ARGUMENTS (current_function_decl); | |
9091 | decl; decl = TREE_CHAIN (decl)) | |
9092 | { | |
9093 | rtx parameter = DECL_INCOMING_RTL (decl); | |
9094 | enum machine_mode mode = GET_MODE (parameter); | |
9095 | ||
9096 | if (GET_CODE (parameter) == REG) | |
9097 | { | |
9098 | if (GET_MODE_CLASS (mode) == MODE_FLOAT) | |
9099 | { | |
9100 | int bits; | |
9101 | ||
9102 | float_parms++; | |
9103 | ||
9104 | if (mode == SFmode) | |
9105 | bits = 0x2; | |
9106 | else if (mode == DFmode) | |
9107 | bits = 0x3; | |
9108 | else | |
9109 | abort (); | |
9110 | ||
9111 | /* If only one bit will fit, don't or in this entry. */ | |
9112 | if (next_parm_info_bit > 0) | |
9113 | parm_info |= (bits << (next_parm_info_bit - 1)); | |
9114 | next_parm_info_bit -= 2; | |
9115 | } | |
9116 | else | |
9117 | { | |
9118 | fixed_parms += ((GET_MODE_SIZE (mode) | |
9119 | + (UNITS_PER_WORD - 1)) | |
9120 | / UNITS_PER_WORD); | |
9121 | next_parm_info_bit -= 1; | |
9122 | } | |
9123 | } | |
9124 | } | |
9125 | } | |
9126 | ||
9127 | /* Number of fixed point parameters. */ | |
9128 | /* This is actually the number of words of fixed point parameters; thus | |
9129 | an 8 byte struct counts as 2; and thus the maximum value is 8. */ | |
9130 | fprintf (file, "%d,", fixed_parms); | |
9131 | ||
9132 | /* 2 bitfields: number of floating point parameters (7 bits), parameters | |
9133 | all on stack. */ | |
9134 | /* This is actually the number of fp registers that hold parameters; | |
9135 | and thus the maximum value is 13. */ | |
9136 | /* Set parameters on stack bit if parameters are not in their original | |
9137 | registers, regardless of whether they are on the stack? Xlc | |
9138 | seems to set the bit when not optimizing. */ | |
9139 | fprintf (file, "%d\n", ((float_parms << 1) | (! optimize))); | |
9140 | ||
9141 | /* Optional fields follow. Some are variable length. */ | |
9142 | ||
9143 | /* Parameter types, left adjusted bit fields: 0 fixed, 10 single float, | |
9144 | 11 double float. */ | |
9145 | /* There is an entry for each parameter in a register, in the order that | |
9146 | they occur in the parameter list. Any intervening arguments on the | |
9147 | stack are ignored. If the list overflows a long (max possible length | |
9148 | 34 bits) then completely leave off all elements that don't fit. */ | |
9149 | /* Only emit this long if there was at least one parameter. */ | |
9150 | if (fixed_parms || float_parms) | |
9151 | fprintf (file, "\t.long %d\n", parm_info); | |
9152 | ||
9153 | /* Offset from start of code to tb table. */ | |
19d2d16f | 9154 | fputs ("\t.long ", file); |
314fc5a9 | 9155 | ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT"); |
54ee9799 DE |
9156 | #if TARGET_AIX |
9157 | RS6000_OUTPUT_BASENAME (file, fname); | |
9158 | #else | |
9ebbca7d | 9159 | assemble_name (file, fname); |
54ee9799 | 9160 | #endif |
19d2d16f | 9161 | fputs ("-.", file); |
54ee9799 DE |
9162 | #if TARGET_AIX |
9163 | RS6000_OUTPUT_BASENAME (file, fname); | |
9164 | #else | |
9ebbca7d | 9165 | assemble_name (file, fname); |
54ee9799 | 9166 | #endif |
19d2d16f | 9167 | putc ('\n', file); |
314fc5a9 ILT |
9168 | |
9169 | /* Interrupt handler mask. */ | |
9170 | /* Omit this long, since we never set the interrupt handler bit | |
9171 | above. */ | |
9172 | ||
9173 | /* Number of CTL (controlled storage) anchors. */ | |
9174 | /* Omit this long, since the has_ctl bit is never set above. */ | |
9175 | ||
9176 | /* Displacement into stack of each CTL anchor. */ | |
9177 | /* Omit this list of longs, because there are no CTL anchors. */ | |
9178 | ||
9179 | /* Length of function name. */ | |
296b8152 | 9180 | fprintf (file, "\t.short %d\n", (int) strlen (fname)); |
314fc5a9 ILT |
9181 | |
9182 | /* Function name. */ | |
9183 | assemble_string (fname, strlen (fname)); | |
9184 | ||
9185 | /* Register for alloca automatic storage; this is always reg 31. | |
9186 | Only emit this if the alloca bit was set above. */ | |
9187 | if (frame_pointer_needed) | |
19d2d16f | 9188 | fputs ("\t.byte 31\n", file); |
9b30bae2 | 9189 | } |
9878760c | 9190 | } |
17167fd8 | 9191 | \f |
a4f6c312 SS |
9192 | /* A C compound statement that outputs the assembler code for a thunk |
9193 | function, used to implement C++ virtual function calls with | |
9194 | multiple inheritance. The thunk acts as a wrapper around a virtual | |
9195 | function, adjusting the implicit object parameter before handing | |
9196 | control off to the real function. | |
9197 | ||
9198 | First, emit code to add the integer DELTA to the location that | |
9199 | contains the incoming first argument. Assume that this argument | |
9200 | contains a pointer, and is the one used to pass the `this' pointer | |
9201 | in C++. This is the incoming argument *before* the function | |
9202 | prologue, e.g. `%o0' on a sparc. The addition must preserve the | |
9203 | values of all other incoming arguments. | |
17167fd8 MM |
9204 | |
9205 | After the addition, emit code to jump to FUNCTION, which is a | |
a4f6c312 SS |
9206 | `FUNCTION_DECL'. This is a direct pure jump, not a call, and does |
9207 | not touch the return address. Hence returning from FUNCTION will | |
9208 | return to whoever called the current `thunk'. | |
17167fd8 | 9209 | |
a4f6c312 SS |
9210 | The effect must be as if FUNCTION had been called directly with the |
9211 | adjusted first argument. This macro is responsible for emitting | |
9212 | all of the code for a thunk function; output_function_prologue() | |
9213 | and output_function_epilogue() are not invoked. | |
17167fd8 | 9214 | |
a4f6c312 SS |
9215 | The THUNK_FNDECL is redundant. (DELTA and FUNCTION have already |
9216 | been extracted from it.) It might possibly be useful on some | |
9217 | targets, but probably not. | |
17167fd8 | 9218 | |
a4f6c312 SS |
9219 | If you do not define this macro, the target-independent code in the |
9220 | C++ frontend will generate a less efficient heavyweight thunk that | |
9221 | calls FUNCTION instead of jumping to it. The generic approach does | |
9222 | not support varargs. */ | |
17167fd8 MM |
9223 | |
9224 | void | |
9225 | output_mi_thunk (file, thunk_fndecl, delta, function) | |
9226 | FILE *file; | |
d330fd93 | 9227 | tree thunk_fndecl ATTRIBUTE_UNUSED; |
17167fd8 MM |
9228 | int delta; |
9229 | tree function; | |
9230 | { | |
a4f6c312 SS |
9231 | const char *this_reg = |
9232 | reg_names[ aggregate_value_p (TREE_TYPE (TREE_TYPE (function))) ? 4 : 3 ]; | |
d330fd93 | 9233 | const char *prefix; |
3cce094d | 9234 | const char *fname; |
d330fd93 | 9235 | const char *r0 = reg_names[0]; |
d330fd93 KG |
9236 | const char *toc = reg_names[2]; |
9237 | const char *schain = reg_names[11]; | |
9238 | const char *r12 = reg_names[12]; | |
17167fd8 MM |
9239 | char buf[512]; |
9240 | static int labelno = 0; | |
9241 | ||
a4f6c312 | 9242 | /* Small constants that can be done by one add instruction. */ |
17167fd8 MM |
9243 | if (delta >= -32768 && delta <= 32767) |
9244 | { | |
22b4a3b0 | 9245 | if (! TARGET_NEW_MNEMONICS) |
17167fd8 MM |
9246 | fprintf (file, "\tcal %s,%d(%s)\n", this_reg, delta, this_reg); |
9247 | else | |
9248 | fprintf (file, "\taddi %s,%s,%d\n", this_reg, this_reg, delta); | |
9249 | } | |
9250 | ||
a4f6c312 | 9251 | /* Large constants that can be done by one addis instruction. */ |
17167fd8 MM |
9252 | else if ((delta & 0xffff) == 0 && num_insns_constant_wide (delta) == 1) |
9253 | asm_fprintf (file, "\t{cau|addis} %s,%s,%d\n", this_reg, this_reg, | |
9254 | delta >> 16); | |
9255 | ||
9256 | /* 32-bit constants that can be done by an add and addis instruction. */ | |
9257 | else if (TARGET_32BIT || num_insns_constant_wide (delta) == 1) | |
9258 | { | |
a4f6c312 SS |
9259 | /* Break into two pieces, propagating the sign bit from the low |
9260 | word to the upper word. */ | |
17167fd8 MM |
9261 | int delta_high = delta >> 16; |
9262 | int delta_low = delta & 0xffff; | |
9263 | if ((delta_low & 0x8000) != 0) | |
9264 | { | |
9265 | delta_high++; | |
9266 | delta_low = (delta_low ^ 0x8000) - 0x8000; /* sign extend */ | |
9267 | } | |
9268 | ||
9269 | asm_fprintf (file, "\t{cau|addis} %s,%s,%d\n", this_reg, this_reg, | |
9270 | delta_high); | |
9271 | ||
22b4a3b0 | 9272 | if (! TARGET_NEW_MNEMONICS) |
17167fd8 MM |
9273 | fprintf (file, "\tcal %s,%d(%s)\n", this_reg, delta_low, this_reg); |
9274 | else | |
9275 | fprintf (file, "\taddi %s,%s,%d\n", this_reg, this_reg, delta_low); | |
9276 | } | |
9277 | ||
9278 | /* 64-bit constants, fixme */ | |
9279 | else | |
9280 | abort (); | |
9281 | ||
9282 | /* Get the prefix in front of the names. */ | |
9283 | switch (DEFAULT_ABI) | |
9284 | { | |
9285 | default: | |
9286 | abort (); | |
9287 | ||
9288 | case ABI_AIX: | |
9289 | prefix = "."; | |
9290 | break; | |
9291 | ||
9292 | case ABI_V4: | |
9293 | case ABI_AIX_NODESC: | |
17167fd8 MM |
9294 | prefix = ""; |
9295 | break; | |
17167fd8 MM |
9296 | } |
9297 | ||
9298 | /* If the function is compiled in this module, jump to it directly. | |
9299 | Otherwise, load up its address and jump to it. */ | |
9300 | ||
9301 | fname = XSTR (XEXP (DECL_RTL (function), 0), 0); | |
42820a49 | 9302 | |
9ebbca7d | 9303 | if (current_file_function_operand (XEXP (DECL_RTL (function), 0), VOIDmode) |
22b4a3b0 FS |
9304 | && ! lookup_attribute ("longcall", |
9305 | TYPE_ATTRIBUTES (TREE_TYPE (function)))) | |
17167fd8 MM |
9306 | { |
9307 | fprintf (file, "\tb %s", prefix); | |
9308 | assemble_name (file, fname); | |
22b4a3b0 | 9309 | if (DEFAULT_ABI == ABI_V4 && flag_pic) fputs ("@local", file); |
949ea356 | 9310 | putc ('\n', file); |
17167fd8 MM |
9311 | } |
9312 | ||
9313 | else | |
9314 | { | |
9315 | switch (DEFAULT_ABI) | |
9316 | { | |
9317 | default: | |
17167fd8 MM |
9318 | abort (); |
9319 | ||
9320 | case ABI_AIX: | |
9321 | /* Set up a TOC entry for the function. */ | |
9322 | ASM_GENERATE_INTERNAL_LABEL (buf, "Lthunk", labelno); | |
9323 | toc_section (); | |
9324 | ASM_OUTPUT_INTERNAL_LABEL (file, "Lthunk", labelno); | |
9325 | labelno++; | |
9326 | ||
fa9b5c6b DE |
9327 | if (TARGET_MINIMAL_TOC) |
9328 | fputs (TARGET_32BIT ? "\t.long " : DOUBLE_INT_ASM_OP, file); | |
9329 | else | |
9330 | { | |
9331 | fputs ("\t.tc ", file); | |
9332 | assemble_name (file, fname); | |
9333 | fputs ("[TC],", file); | |
9334 | } | |
9335 | assemble_name (file, fname); | |
17167fd8 MM |
9336 | putc ('\n', file); |
9337 | text_section (); | |
468e8dba DE |
9338 | if (TARGET_MINIMAL_TOC) |
9339 | asm_fprintf (file, (TARGET_32BIT) | |
9340 | ? "\t{l|lwz} %s,%s(%s)\n" : "\tld %s,%s(%s)\n", r12, | |
9341 | TARGET_ELF ? ".LCTOC0@toc" : ".LCTOC..1", toc); | |
d2574c50 | 9342 | asm_fprintf (file, (TARGET_32BIT) ? "\t{l|lwz} %s," : "\tld %s,", r12); |
17167fd8 | 9343 | assemble_name (file, buf); |
468e8dba DE |
9344 | if (TARGET_ELF && TARGET_MINIMAL_TOC) |
9345 | fputs ("-(.LCTOC1)", file); | |
9346 | asm_fprintf (file, "(%s)\n", TARGET_MINIMAL_TOC ? r12 : toc); | |
17167fd8 MM |
9347 | asm_fprintf (file, |
9348 | (TARGET_32BIT) ? "\t{l|lwz} %s,0(%s)\n" : "\tld %s,0(%s)\n", | |
9349 | r0, r12); | |
9350 | ||
9351 | asm_fprintf (file, | |
9352 | (TARGET_32BIT) ? "\t{l|lwz} %s,4(%s)\n" : "\tld %s,8(%s)\n", | |
9353 | toc, r12); | |
9354 | ||
9355 | asm_fprintf (file, "\tmtctr %s\n", r0); | |
9356 | asm_fprintf (file, | |
9357 | (TARGET_32BIT) ? "\t{l|lwz} %s,8(%s)\n" : "\tld %s,16(%s)\n", | |
9358 | schain, r12); | |
9359 | ||
9360 | asm_fprintf (file, "\tbctr\n"); | |
9361 | break; | |
9362 | ||
9ebbca7d | 9363 | case ABI_AIX_NODESC: |
17167fd8 | 9364 | case ABI_V4: |
22b4a3b0 FS |
9365 | fprintf (file, "\tb %s", prefix); |
9366 | assemble_name (file, fname); | |
9367 | if (flag_pic) fputs ("@plt", file); | |
949ea356 | 9368 | putc ('\n', file); |
22b4a3b0 | 9369 | break; |
ee890fe2 SS |
9370 | |
9371 | #if TARGET_MACHO | |
9372 | case ABI_DARWIN: | |
9373 | fprintf (file, "\tb %s", prefix); | |
9374 | if (flag_pic && !machopic_name_defined_p (fname)) | |
9375 | assemble_name (file, machopic_stub_name (fname)); | |
9376 | else | |
9377 | assemble_name (file, fname); | |
9378 | putc ('\n', file); | |
9379 | break; | |
9380 | #endif | |
9ebbca7d GK |
9381 | } |
9382 | } | |
9383 | } | |
42820a49 | 9384 | |
9ebbca7d GK |
9385 | \f |
9386 | /* A quick summary of the various types of 'constant-pool tables' | |
9387 | under PowerPC: | |
9388 | ||
9389 | Target Flags Name One table per | |
9390 | AIX (none) AIX TOC object file | |
9391 | AIX -mfull-toc AIX TOC object file | |
9392 | AIX -mminimal-toc AIX minimal TOC translation unit | |
9393 | SVR4/EABI (none) SVR4 SDATA object file | |
9394 | SVR4/EABI -fpic SVR4 pic object file | |
9395 | SVR4/EABI -fPIC SVR4 PIC translation unit | |
9396 | SVR4/EABI -mrelocatable EABI TOC function | |
9397 | SVR4/EABI -maix AIX TOC object file | |
9398 | SVR4/EABI -maix -mminimal-toc | |
9399 | AIX minimal TOC translation unit | |
9400 | ||
9401 | Name Reg. Set by entries contains: | |
9402 | made by addrs? fp? sum? | |
9403 | ||
9404 | AIX TOC 2 crt0 as Y option option | |
9405 | AIX minimal TOC 30 prolog gcc Y Y option | |
9406 | SVR4 SDATA 13 crt0 gcc N Y N | |
9407 | SVR4 pic 30 prolog ld Y not yet N | |
9408 | SVR4 PIC 30 prolog gcc Y option option | |
9409 | EABI TOC 30 prolog gcc Y option option | |
9410 | ||
9411 | */ | |
9412 | ||
9413 | /* Hash table stuff for keeping track of TOC entries. */ | |
9414 | ||
9415 | struct toc_hash_struct | |
9416 | { | |
9417 | /* `key' will satisfy CONSTANT_P; in fact, it will satisfy | |
9418 | ASM_OUTPUT_SPECIAL_POOL_ENTRY_P. */ | |
9419 | rtx key; | |
a9098fd0 | 9420 | enum machine_mode key_mode; |
9ebbca7d GK |
9421 | int labelno; |
9422 | }; | |
17167fd8 | 9423 | |
9ebbca7d GK |
9424 | static htab_t toc_hash_table; |
9425 | ||
9426 | /* Hash functions for the hash table. */ | |
9427 | ||
9428 | static unsigned | |
9429 | rs6000_hash_constant (k) | |
9430 | rtx k; | |
9431 | { | |
a9098fd0 | 9432 | unsigned result = (GET_CODE (k) << 3) ^ GET_MODE (k); |
9ebbca7d GK |
9433 | const char *format = GET_RTX_FORMAT (GET_CODE (k)); |
9434 | int flen = strlen (format); | |
9435 | int fidx; | |
9436 | ||
9437 | if (GET_CODE (k) == LABEL_REF) | |
832ea3b3 | 9438 | return result * 1231 + X0INT (XEXP (k, 0), 3); |
9ebbca7d GK |
9439 | |
9440 | if (GET_CODE (k) == CONST_DOUBLE) | |
592bf28c | 9441 | fidx = 1; |
9ebbca7d GK |
9442 | else if (GET_CODE (k) == CODE_LABEL) |
9443 | fidx = 3; | |
9444 | else | |
9445 | fidx = 0; | |
9446 | ||
9447 | for (; fidx < flen; fidx++) | |
9448 | switch (format[fidx]) | |
9449 | { | |
9450 | case 's': | |
9451 | { | |
9452 | unsigned i, len; | |
9453 | const char *str = XSTR (k, fidx); | |
9454 | len = strlen (str); | |
9455 | result = result * 613 + len; | |
9456 | for (i = 0; i < len; i++) | |
9457 | result = result * 613 + (unsigned) str[i]; | |
17167fd8 MM |
9458 | break; |
9459 | } | |
9ebbca7d GK |
9460 | case 'u': |
9461 | case 'e': | |
9462 | result = result * 1231 + rs6000_hash_constant (XEXP (k, fidx)); | |
9463 | break; | |
9464 | case 'i': | |
9465 | case 'n': | |
9466 | result = result * 613 + (unsigned) XINT (k, fidx); | |
9467 | break; | |
9468 | case 'w': | |
9469 | if (sizeof (unsigned) >= sizeof (HOST_WIDE_INT)) | |
9470 | result = result * 613 + (unsigned) XWINT (k, fidx); | |
9471 | else | |
9472 | { | |
9473 | size_t i; | |
9474 | for (i = 0; i < sizeof(HOST_WIDE_INT)/sizeof(unsigned); i++) | |
9475 | result = result * 613 + (unsigned) (XWINT (k, fidx) | |
9476 | >> CHAR_BIT * i); | |
9477 | } | |
9478 | break; | |
9479 | default: | |
a4f6c312 | 9480 | abort (); |
9ebbca7d GK |
9481 | } |
9482 | return result; | |
9483 | } | |
9484 | ||
9485 | static unsigned | |
9486 | toc_hash_function (hash_entry) | |
9487 | const void * hash_entry; | |
9488 | { | |
a9098fd0 GK |
9489 | const struct toc_hash_struct *thc = |
9490 | (const struct toc_hash_struct *) hash_entry; | |
9491 | return rs6000_hash_constant (thc->key) ^ thc->key_mode; | |
9ebbca7d GK |
9492 | } |
9493 | ||
9494 | /* Compare H1 and H2 for equivalence. */ | |
9495 | ||
9496 | static int | |
9497 | toc_hash_eq (h1, h2) | |
9498 | const void * h1; | |
9499 | const void * h2; | |
9500 | { | |
9501 | rtx r1 = ((const struct toc_hash_struct *) h1)->key; | |
9502 | rtx r2 = ((const struct toc_hash_struct *) h2)->key; | |
9503 | ||
a9098fd0 GK |
9504 | if (((const struct toc_hash_struct *) h1)->key_mode |
9505 | != ((const struct toc_hash_struct *) h2)->key_mode) | |
9506 | return 0; | |
9507 | ||
9ebbca7d GK |
9508 | /* Gotcha: One of these const_doubles will be in memory. |
9509 | The other may be on the constant-pool chain. | |
a4f6c312 | 9510 | So rtx_equal_p will think they are different... */ |
9ebbca7d GK |
9511 | if (r1 == r2) |
9512 | return 1; | |
9513 | if (GET_CODE (r1) != GET_CODE (r2) | |
9514 | || GET_MODE (r1) != GET_MODE (r2)) | |
9515 | return 0; | |
9516 | if (GET_CODE (r1) == CONST_DOUBLE) | |
9517 | { | |
9518 | int format_len = strlen (GET_RTX_FORMAT (CONST_DOUBLE)); | |
9519 | int i; | |
592bf28c | 9520 | for (i = 1; i < format_len; i++) |
9ebbca7d GK |
9521 | if (XWINT (r1, i) != XWINT (r2, i)) |
9522 | return 0; | |
9523 | ||
9524 | return 1; | |
17167fd8 | 9525 | } |
9ebbca7d | 9526 | else if (GET_CODE (r1) == LABEL_REF) |
e4a0656f GK |
9527 | return (CODE_LABEL_NUMBER (XEXP (r1, 0)) |
9528 | == CODE_LABEL_NUMBER (XEXP (r2, 0))); | |
9ebbca7d GK |
9529 | else |
9530 | return rtx_equal_p (r1, r2); | |
9531 | } | |
9532 | ||
9533 | /* Mark the hash table-entry HASH_ENTRY. */ | |
9534 | ||
9535 | static int | |
9536 | toc_hash_mark_entry (hash_slot, unused) | |
2eba1afa | 9537 | void ** hash_slot; |
9ebbca7d GK |
9538 | void * unused ATTRIBUTE_UNUSED; |
9539 | { | |
9540 | const struct toc_hash_struct * hash_entry = | |
9541 | *(const struct toc_hash_struct **) hash_slot; | |
9542 | rtx r = hash_entry->key; | |
9543 | ggc_set_mark (hash_entry); | |
a4f6c312 | 9544 | /* For CODE_LABELS, we don't want to drag in the whole insn chain... */ |
9ebbca7d GK |
9545 | if (GET_CODE (r) == LABEL_REF) |
9546 | { | |
9547 | ggc_set_mark (r); | |
9548 | ggc_set_mark (XEXP (r, 0)); | |
9549 | } | |
9550 | else | |
9551 | ggc_mark_rtx (r); | |
9552 | return 1; | |
9553 | } | |
9554 | ||
9555 | /* Mark all the elements of the TOC hash-table *HT. */ | |
9556 | ||
9557 | static void | |
9558 | toc_hash_mark_table (vht) | |
9559 | void *vht; | |
9560 | { | |
9561 | htab_t *ht = vht; | |
9562 | ||
9563 | htab_traverse (*ht, toc_hash_mark_entry, (void *)0); | |
17167fd8 MM |
9564 | } |
9565 | ||
28e510bd MM |
9566 | /* These are the names given by the C++ front-end to vtables, and |
9567 | vtable-like objects. Ideally, this logic should not be here; | |
9568 | instead, there should be some programmatic way of inquiring as | |
9569 | to whether or not an object is a vtable. */ | |
9570 | ||
9571 | #define VTABLE_NAME_P(NAME) \ | |
9572 | (strncmp ("_vt.", name, strlen("_vt.")) == 0 \ | |
9573 | || strncmp ("_ZTV", name, strlen ("_ZTV")) == 0 \ | |
9574 | || strncmp ("_ZTT", name, strlen ("_ZTT")) == 0 \ | |
9575 | || strncmp ("_ZTC", name, strlen ("_ZTC")) == 0) | |
9576 | ||
9577 | void | |
9578 | rs6000_output_symbol_ref (file, x) | |
9579 | FILE *file; | |
9580 | rtx x; | |
9581 | { | |
9582 | /* Currently C++ toc references to vtables can be emitted before it | |
9583 | is decided whether the vtable is public or private. If this is | |
9584 | the case, then the linker will eventually complain that there is | |
9585 | a reference to an unknown section. Thus, for vtables only, | |
9586 | we emit the TOC reference to reference the symbol and not the | |
9587 | section. */ | |
9588 | const char *name = XSTR (x, 0); | |
54ee9799 DE |
9589 | |
9590 | if (VTABLE_NAME_P (name)) | |
9591 | { | |
9592 | RS6000_OUTPUT_BASENAME (file, name); | |
9593 | } | |
9594 | else | |
9595 | assemble_name (file, name); | |
28e510bd MM |
9596 | } |
9597 | ||
a4f6c312 SS |
9598 | /* Output a TOC entry. We derive the entry name from what is being |
9599 | written. */ | |
9878760c RK |
9600 | |
9601 | void | |
a9098fd0 | 9602 | output_toc (file, x, labelno, mode) |
9878760c RK |
9603 | FILE *file; |
9604 | rtx x; | |
9605 | int labelno; | |
a9098fd0 | 9606 | enum machine_mode mode; |
9878760c RK |
9607 | { |
9608 | char buf[256]; | |
3cce094d | 9609 | const char *name = buf; |
ec940faa | 9610 | const char *real_name; |
9878760c RK |
9611 | rtx base = x; |
9612 | int offset = 0; | |
9613 | ||
4697a36c MM |
9614 | if (TARGET_NO_TOC) |
9615 | abort (); | |
9616 | ||
9ebbca7d GK |
9617 | /* When the linker won't eliminate them, don't output duplicate |
9618 | TOC entries (this happens on AIX if there is any kind of TOC, | |
1f8f4a0b MM |
9619 | and on SVR4 under -fPIC or -mrelocatable). */ |
9620 | if (TARGET_TOC) | |
9ebbca7d GK |
9621 | { |
9622 | struct toc_hash_struct *h; | |
9623 | void * * found; | |
9624 | ||
9625 | h = ggc_alloc (sizeof (*h)); | |
9626 | h->key = x; | |
a9098fd0 | 9627 | h->key_mode = mode; |
9ebbca7d GK |
9628 | h->labelno = labelno; |
9629 | ||
9630 | found = htab_find_slot (toc_hash_table, h, 1); | |
9631 | if (*found == NULL) | |
9632 | *found = h; | |
9633 | else /* This is indeed a duplicate. | |
9634 | Set this label equal to that label. */ | |
9635 | { | |
9636 | fputs ("\t.set ", file); | |
9637 | ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC"); | |
9638 | fprintf (file, "%d,", labelno); | |
9639 | ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC"); | |
9640 | fprintf (file, "%d\n", ((*(const struct toc_hash_struct **) | |
9641 | found)->labelno)); | |
9642 | return; | |
9643 | } | |
9644 | } | |
9645 | ||
9646 | /* If we're going to put a double constant in the TOC, make sure it's | |
9647 | aligned properly when strict alignment is on. */ | |
ff1720ed RK |
9648 | if (GET_CODE (x) == CONST_DOUBLE |
9649 | && STRICT_ALIGNMENT | |
a9098fd0 | 9650 | && GET_MODE_BITSIZE (mode) >= 64 |
ff1720ed RK |
9651 | && ! (TARGET_NO_FP_IN_TOC && ! TARGET_MINIMAL_TOC)) { |
9652 | ASM_OUTPUT_ALIGN (file, 3); | |
9653 | } | |
9654 | ||
9ebbca7d | 9655 | ASM_OUTPUT_INTERNAL_LABEL (file, "LC", labelno); |
9878760c | 9656 | |
37c37a57 RK |
9657 | /* Handle FP constants specially. Note that if we have a minimal |
9658 | TOC, things we put here aren't actually in the TOC, so we can allow | |
9659 | FP constants. */ | |
a9098fd0 | 9660 | if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == DFmode) |
9878760c | 9661 | { |
042259f2 DE |
9662 | REAL_VALUE_TYPE rv; |
9663 | long k[2]; | |
0adc764e | 9664 | |
042259f2 DE |
9665 | REAL_VALUE_FROM_CONST_DOUBLE (rv, x); |
9666 | REAL_VALUE_TO_TARGET_DOUBLE (rv, k); | |
31bfaa0b | 9667 | |
13ded975 DE |
9668 | if (TARGET_64BIT) |
9669 | { | |
9670 | if (TARGET_MINIMAL_TOC) | |
2bfcf297 | 9671 | fputs (DOUBLE_INT_ASM_OP, file); |
13ded975 | 9672 | else |
2bfcf297 DB |
9673 | fprintf (file, "\t.tc FD_%lx_%lx[TC],", k[0], k[1]); |
9674 | fprintf (file, "0x%lx%08lx\n", k[0], k[1]); | |
13ded975 DE |
9675 | return; |
9676 | } | |
1875cc88 | 9677 | else |
13ded975 DE |
9678 | { |
9679 | if (TARGET_MINIMAL_TOC) | |
2bfcf297 | 9680 | fputs ("\t.long ", file); |
13ded975 | 9681 | else |
2bfcf297 DB |
9682 | fprintf (file, "\t.tc FD_%lx_%lx[TC],", k[0], k[1]); |
9683 | fprintf (file, "0x%lx,0x%lx\n", k[0], k[1]); | |
13ded975 DE |
9684 | return; |
9685 | } | |
9878760c | 9686 | } |
a9098fd0 | 9687 | else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == SFmode) |
9878760c | 9688 | { |
042259f2 DE |
9689 | REAL_VALUE_TYPE rv; |
9690 | long l; | |
9878760c | 9691 | |
042259f2 DE |
9692 | REAL_VALUE_FROM_CONST_DOUBLE (rv, x); |
9693 | REAL_VALUE_TO_TARGET_SINGLE (rv, l); | |
9694 | ||
31bfaa0b DE |
9695 | if (TARGET_64BIT) |
9696 | { | |
9697 | if (TARGET_MINIMAL_TOC) | |
2bfcf297 | 9698 | fputs (DOUBLE_INT_ASM_OP, file); |
31bfaa0b | 9699 | else |
2bfcf297 DB |
9700 | fprintf (file, "\t.tc FS_%lx[TC],", l); |
9701 | fprintf (file, "0x%lx00000000\n", l); | |
31bfaa0b DE |
9702 | return; |
9703 | } | |
042259f2 | 9704 | else |
31bfaa0b DE |
9705 | { |
9706 | if (TARGET_MINIMAL_TOC) | |
2bfcf297 | 9707 | fputs ("\t.long ", file); |
31bfaa0b | 9708 | else |
2bfcf297 DB |
9709 | fprintf (file, "\t.tc FS_%lx[TC],", l); |
9710 | fprintf (file, "0x%lx\n", l); | |
31bfaa0b DE |
9711 | return; |
9712 | } | |
042259f2 | 9713 | } |
f176e826 | 9714 | else if (GET_MODE (x) == VOIDmode |
a9098fd0 | 9715 | && (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE)) |
042259f2 | 9716 | { |
e2c953b6 | 9717 | unsigned HOST_WIDE_INT low; |
042259f2 DE |
9718 | HOST_WIDE_INT high; |
9719 | ||
9720 | if (GET_CODE (x) == CONST_DOUBLE) | |
9721 | { | |
9722 | low = CONST_DOUBLE_LOW (x); | |
9723 | high = CONST_DOUBLE_HIGH (x); | |
9724 | } | |
9725 | else | |
9726 | #if HOST_BITS_PER_WIDE_INT == 32 | |
9727 | { | |
9728 | low = INTVAL (x); | |
0858c623 | 9729 | high = (low & 0x80000000) ? ~0 : 0; |
042259f2 DE |
9730 | } |
9731 | #else | |
9732 | { | |
0858c623 | 9733 | low = INTVAL (x) & 0xffffffff; |
042259f2 DE |
9734 | high = (HOST_WIDE_INT) INTVAL (x) >> 32; |
9735 | } | |
9736 | #endif | |
9878760c | 9737 | |
a9098fd0 GK |
9738 | /* TOC entries are always Pmode-sized, but since this |
9739 | is a bigendian machine then if we're putting smaller | |
9740 | integer constants in the TOC we have to pad them. | |
9741 | (This is still a win over putting the constants in | |
9742 | a separate constant pool, because then we'd have | |
02a4ec28 FS |
9743 | to have both a TOC entry _and_ the actual constant.) |
9744 | ||
9745 | For a 32-bit target, CONST_INT values are loaded and shifted | |
9746 | entirely within `low' and can be stored in one TOC entry. */ | |
9747 | ||
9748 | if (TARGET_64BIT && POINTER_SIZE < GET_MODE_BITSIZE (mode)) | |
a9098fd0 | 9749 | abort ();/* It would be easy to make this work, but it doesn't now. */ |
02a4ec28 FS |
9750 | |
9751 | if (POINTER_SIZE > GET_MODE_BITSIZE (mode)) | |
a9098fd0 GK |
9752 | lshift_double (low, high, POINTER_SIZE - GET_MODE_BITSIZE (mode), |
9753 | POINTER_SIZE, &low, &high, 0); | |
9754 | ||
13ded975 DE |
9755 | if (TARGET_64BIT) |
9756 | { | |
9757 | if (TARGET_MINIMAL_TOC) | |
2bfcf297 | 9758 | fputs (DOUBLE_INT_ASM_OP, file); |
13ded975 | 9759 | else |
2bfcf297 DB |
9760 | fprintf (file, "\t.tc ID_%lx_%lx[TC],", (long)high, (long)low); |
9761 | fprintf (file, "0x%lx%08lx\n", (long) high, (long) low); | |
13ded975 DE |
9762 | return; |
9763 | } | |
1875cc88 | 9764 | else |
13ded975 | 9765 | { |
02a4ec28 FS |
9766 | if (POINTER_SIZE < GET_MODE_BITSIZE (mode)) |
9767 | { | |
9768 | if (TARGET_MINIMAL_TOC) | |
2bfcf297 | 9769 | fputs ("\t.long ", file); |
02a4ec28 | 9770 | else |
2bfcf297 DB |
9771 | fprintf (file, "\t.tc ID_%lx_%lx[TC],", |
9772 | (long)high, (long)low); | |
9773 | fprintf (file, "0x%lx,0x%lx\n", (long) high, (long) low); | |
02a4ec28 | 9774 | } |
13ded975 | 9775 | else |
02a4ec28 FS |
9776 | { |
9777 | if (TARGET_MINIMAL_TOC) | |
2bfcf297 | 9778 | fputs ("\t.long ", file); |
02a4ec28 | 9779 | else |
2bfcf297 DB |
9780 | fprintf (file, "\t.tc IS_%lx[TC],", (long) low); |
9781 | fprintf (file, "0x%lx\n", (long) low); | |
02a4ec28 | 9782 | } |
13ded975 DE |
9783 | return; |
9784 | } | |
9878760c RK |
9785 | } |
9786 | ||
9787 | if (GET_CODE (x) == CONST) | |
9788 | { | |
2bfcf297 DB |
9789 | if (GET_CODE (XEXP (x, 0)) != PLUS) |
9790 | abort (); | |
9791 | ||
9878760c RK |
9792 | base = XEXP (XEXP (x, 0), 0); |
9793 | offset = INTVAL (XEXP (XEXP (x, 0), 1)); | |
9794 | } | |
9795 | ||
9796 | if (GET_CODE (base) == SYMBOL_REF) | |
9797 | name = XSTR (base, 0); | |
9798 | else if (GET_CODE (base) == LABEL_REF) | |
9799 | ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (XEXP (base, 0))); | |
9800 | else if (GET_CODE (base) == CODE_LABEL) | |
9801 | ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (base)); | |
9802 | else | |
9803 | abort (); | |
9804 | ||
2e4eb9b0 | 9805 | STRIP_NAME_ENCODING (real_name, name); |
1875cc88 | 9806 | if (TARGET_MINIMAL_TOC) |
2bfcf297 | 9807 | fputs (TARGET_32BIT ? "\t.long " : DOUBLE_INT_ASM_OP, file); |
1875cc88 JW |
9808 | else |
9809 | { | |
b6c9286a | 9810 | fprintf (file, "\t.tc %s", real_name); |
9878760c | 9811 | |
1875cc88 JW |
9812 | if (offset < 0) |
9813 | fprintf (file, ".N%d", - offset); | |
9814 | else if (offset) | |
9815 | fprintf (file, ".P%d", offset); | |
9878760c | 9816 | |
19d2d16f | 9817 | fputs ("[TC],", file); |
1875cc88 | 9818 | } |
581bc4de MM |
9819 | |
9820 | /* Currently C++ toc references to vtables can be emitted before it | |
9821 | is decided whether the vtable is public or private. If this is | |
9822 | the case, then the linker will eventually complain that there is | |
9823 | a TOC reference to an unknown section. Thus, for vtables only, | |
9824 | we emit the TOC reference to reference the symbol and not the | |
9825 | section. */ | |
28e510bd | 9826 | if (VTABLE_NAME_P (name)) |
581bc4de | 9827 | { |
54ee9799 | 9828 | RS6000_OUTPUT_BASENAME (file, name); |
581bc4de MM |
9829 | if (offset < 0) |
9830 | fprintf (file, "%d", offset); | |
9831 | else if (offset > 0) | |
9832 | fprintf (file, "+%d", offset); | |
9833 | } | |
9834 | else | |
9835 | output_addr_const (file, x); | |
19d2d16f | 9836 | putc ('\n', file); |
9878760c RK |
9837 | } |
9838 | \f | |
9839 | /* Output an assembler pseudo-op to write an ASCII string of N characters | |
9840 | starting at P to FILE. | |
9841 | ||
9842 | On the RS/6000, we have to do this using the .byte operation and | |
9843 | write out special characters outside the quoted string. | |
9844 | Also, the assembler is broken; very long strings are truncated, | |
a4f6c312 | 9845 | so we must artificially break them up early. */ |
9878760c RK |
9846 | |
9847 | void | |
9848 | output_ascii (file, p, n) | |
9849 | FILE *file; | |
d330fd93 | 9850 | const char *p; |
9878760c RK |
9851 | int n; |
9852 | { | |
9853 | char c; | |
9854 | int i, count_string; | |
d330fd93 KG |
9855 | const char *for_string = "\t.byte \""; |
9856 | const char *for_decimal = "\t.byte "; | |
9857 | const char *to_close = NULL; | |
9878760c RK |
9858 | |
9859 | count_string = 0; | |
9860 | for (i = 0; i < n; i++) | |
9861 | { | |
9862 | c = *p++; | |
9863 | if (c >= ' ' && c < 0177) | |
9864 | { | |
9865 | if (for_string) | |
9866 | fputs (for_string, file); | |
9867 | putc (c, file); | |
9868 | ||
9869 | /* Write two quotes to get one. */ | |
9870 | if (c == '"') | |
9871 | { | |
9872 | putc (c, file); | |
9873 | ++count_string; | |
9874 | } | |
9875 | ||
9876 | for_string = NULL; | |
9877 | for_decimal = "\"\n\t.byte "; | |
9878 | to_close = "\"\n"; | |
9879 | ++count_string; | |
9880 | ||
9881 | if (count_string >= 512) | |
9882 | { | |
9883 | fputs (to_close, file); | |
9884 | ||
9885 | for_string = "\t.byte \""; | |
9886 | for_decimal = "\t.byte "; | |
9887 | to_close = NULL; | |
9888 | count_string = 0; | |
9889 | } | |
9890 | } | |
9891 | else | |
9892 | { | |
9893 | if (for_decimal) | |
9894 | fputs (for_decimal, file); | |
9895 | fprintf (file, "%d", c); | |
9896 | ||
9897 | for_string = "\n\t.byte \""; | |
9898 | for_decimal = ", "; | |
9899 | to_close = "\n"; | |
9900 | count_string = 0; | |
9901 | } | |
9902 | } | |
9903 | ||
9904 | /* Now close the string if we have written one. Then end the line. */ | |
9905 | if (to_close) | |
9ebbca7d | 9906 | fputs (to_close, file); |
9878760c RK |
9907 | } |
9908 | \f | |
9909 | /* Generate a unique section name for FILENAME for a section type | |
9910 | represented by SECTION_DESC. Output goes into BUF. | |
9911 | ||
9912 | SECTION_DESC can be any string, as long as it is different for each | |
9913 | possible section type. | |
9914 | ||
9915 | We name the section in the same manner as xlc. The name begins with an | |
9916 | underscore followed by the filename (after stripping any leading directory | |
11e5fe42 RK |
9917 | names) with the last period replaced by the string SECTION_DESC. If |
9918 | FILENAME does not contain a period, SECTION_DESC is appended to the end of | |
9919 | the name. */ | |
9878760c RK |
9920 | |
9921 | void | |
9922 | rs6000_gen_section_name (buf, filename, section_desc) | |
9923 | char **buf; | |
9ebbca7d GK |
9924 | const char *filename; |
9925 | const char *section_desc; | |
9878760c | 9926 | { |
9ebbca7d | 9927 | const char *q, *after_last_slash, *last_period = 0; |
9878760c RK |
9928 | char *p; |
9929 | int len; | |
9878760c RK |
9930 | |
9931 | after_last_slash = filename; | |
9932 | for (q = filename; *q; q++) | |
11e5fe42 RK |
9933 | { |
9934 | if (*q == '/') | |
9935 | after_last_slash = q + 1; | |
9936 | else if (*q == '.') | |
9937 | last_period = q; | |
9938 | } | |
9878760c | 9939 | |
11e5fe42 | 9940 | len = strlen (after_last_slash) + strlen (section_desc) + 2; |
9878760c RK |
9941 | *buf = (char *) permalloc (len); |
9942 | ||
9943 | p = *buf; | |
9944 | *p++ = '_'; | |
9945 | ||
9946 | for (q = after_last_slash; *q; q++) | |
9947 | { | |
11e5fe42 | 9948 | if (q == last_period) |
9878760c RK |
9949 | { |
9950 | strcpy (p, section_desc); | |
9951 | p += strlen (section_desc); | |
9878760c RK |
9952 | } |
9953 | ||
e9a780ec | 9954 | else if (ISALNUM (*q)) |
9878760c RK |
9955 | *p++ = *q; |
9956 | } | |
9957 | ||
11e5fe42 | 9958 | if (last_period == 0) |
9878760c RK |
9959 | strcpy (p, section_desc); |
9960 | else | |
9961 | *p = '\0'; | |
9962 | } | |
e165f3f0 | 9963 | \f |
a4f6c312 | 9964 | /* Emit profile function. */ |
411707f4 | 9965 | |
411707f4 CC |
9966 | void |
9967 | output_profile_hook (labelno) | |
9968 | int labelno; | |
9969 | { | |
8480e480 CC |
9970 | if (DEFAULT_ABI == ABI_AIX) |
9971 | { | |
9972 | char buf[30]; | |
40501e5f | 9973 | const char *label_name; |
8480e480 | 9974 | rtx fun; |
411707f4 | 9975 | |
8480e480 | 9976 | labelno += 1; |
411707f4 | 9977 | |
8480e480 CC |
9978 | ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno); |
9979 | STRIP_NAME_ENCODING (label_name, ggc_strdup (buf)); | |
9980 | fun = gen_rtx_SYMBOL_REF (Pmode, label_name); | |
411707f4 | 9981 | |
8480e480 CC |
9982 | emit_library_call (init_one_libfunc (RS6000_MCOUNT), 0, VOIDmode, 1, |
9983 | fun, Pmode); | |
9984 | } | |
ee890fe2 SS |
9985 | else if (DEFAULT_ABI == ABI_DARWIN) |
9986 | { | |
d5fa86ba | 9987 | const char *mcount_name = RS6000_MCOUNT; |
ee890fe2 SS |
9988 | int caller_addr_regno = LINK_REGISTER_REGNUM; |
9989 | ||
9990 | /* Be conservative and always set this, at least for now. */ | |
9991 | current_function_uses_pic_offset_table = 1; | |
9992 | ||
9993 | #if TARGET_MACHO | |
9994 | /* For PIC code, set up a stub and collect the caller's address | |
9995 | from r0, which is where the prologue puts it. */ | |
9996 | if (flag_pic) | |
9997 | { | |
9998 | mcount_name = machopic_stub_name (mcount_name); | |
9999 | if (current_function_uses_pic_offset_table) | |
10000 | caller_addr_regno = 0; | |
10001 | } | |
10002 | #endif | |
10003 | emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mcount_name), | |
10004 | 0, VOIDmode, 1, | |
10005 | gen_rtx_REG (Pmode, caller_addr_regno), Pmode); | |
10006 | } | |
411707f4 CC |
10007 | } |
10008 | ||
a4f6c312 | 10009 | /* Write function profiler code. */ |
e165f3f0 RK |
10010 | |
10011 | void | |
10012 | output_function_profiler (file, labelno) | |
10013 | FILE *file; | |
10014 | int labelno; | |
10015 | { | |
3daf36a4 | 10016 | char buf[100]; |
e165f3f0 | 10017 | |
3daf36a4 | 10018 | ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno); |
38c1f2d7 | 10019 | switch (DEFAULT_ABI) |
3daf36a4 | 10020 | { |
38c1f2d7 MM |
10021 | default: |
10022 | abort (); | |
10023 | ||
10024 | case ABI_V4: | |
38c1f2d7 MM |
10025 | case ABI_AIX_NODESC: |
10026 | fprintf (file, "\tmflr %s\n", reg_names[0]); | |
10027 | if (flag_pic == 1) | |
10028 | { | |
dfdfa60f DE |
10029 | fputs ("\tbl _GLOBAL_OFFSET_TABLE_@local-4\n", file); |
10030 | asm_fprintf (file, "\t{st|stw} %s,4(%s)\n", | |
10031 | reg_names[0], reg_names[1]); | |
17167fd8 | 10032 | asm_fprintf (file, "\tmflr %s\n", reg_names[12]); |
dfdfa60f | 10033 | asm_fprintf (file, "\t{l|lwz} %s,", reg_names[0]); |
38c1f2d7 | 10034 | assemble_name (file, buf); |
17167fd8 | 10035 | asm_fprintf (file, "@got(%s)\n", reg_names[12]); |
38c1f2d7 | 10036 | } |
9ebbca7d | 10037 | else if (flag_pic > 1) |
38c1f2d7 | 10038 | { |
dfdfa60f DE |
10039 | asm_fprintf (file, "\t{st|stw} %s,4(%s)\n", |
10040 | reg_names[0], reg_names[1]); | |
9ebbca7d GK |
10041 | /* Now, we need to get the address of the label. */ |
10042 | fputs ("\tbl 1f\n\t.long ", file); | |
034e84c4 | 10043 | assemble_name (file, buf); |
9ebbca7d GK |
10044 | fputs ("-.\n1:", file); |
10045 | asm_fprintf (file, "\tmflr %s\n", reg_names[11]); | |
10046 | asm_fprintf (file, "\t{l|lwz} %s,0(%s)\n", | |
10047 | reg_names[0], reg_names[11]); | |
10048 | asm_fprintf (file, "\t{cax|add} %s,%s,%s\n", | |
10049 | reg_names[0], reg_names[0], reg_names[11]); | |
38c1f2d7 | 10050 | } |
38c1f2d7 MM |
10051 | else |
10052 | { | |
17167fd8 | 10053 | asm_fprintf (file, "\t{liu|lis} %s,", reg_names[12]); |
38c1f2d7 | 10054 | assemble_name (file, buf); |
dfdfa60f | 10055 | fputs ("@ha\n", file); |
b5253831 DE |
10056 | asm_fprintf (file, "\t{st|stw} %s,4(%s)\n", |
10057 | reg_names[0], reg_names[1]); | |
a260abc9 | 10058 | asm_fprintf (file, "\t{cal|la} %s,", reg_names[0]); |
38c1f2d7 | 10059 | assemble_name (file, buf); |
17167fd8 | 10060 | asm_fprintf (file, "@l(%s)\n", reg_names[12]); |
38c1f2d7 MM |
10061 | } |
10062 | ||
b5253831 DE |
10063 | if (current_function_needs_context) |
10064 | asm_fprintf (file, "\tmr %s,%s\n", | |
10065 | reg_names[30], reg_names[STATIC_CHAIN_REGNUM]); | |
38c1f2d7 | 10066 | fprintf (file, "\tbl %s\n", RS6000_MCOUNT); |
b5253831 DE |
10067 | if (current_function_needs_context) |
10068 | asm_fprintf (file, "\tmr %s,%s\n", | |
10069 | reg_names[STATIC_CHAIN_REGNUM], reg_names[30]); | |
38c1f2d7 MM |
10070 | break; |
10071 | ||
10072 | case ABI_AIX: | |
ee890fe2 | 10073 | case ABI_DARWIN: |
a4f6c312 | 10074 | /* Don't do anything, done in output_profile_hook (). */ |
38c1f2d7 | 10075 | break; |
411707f4 | 10076 | |
38c1f2d7 | 10077 | } |
e165f3f0 | 10078 | } |
a251ffd0 TG |
10079 | |
10080 | /* Adjust the cost of a scheduling dependency. Return the new cost of | |
10081 | a dependency LINK or INSN on DEP_INSN. COST is the current cost. */ | |
10082 | ||
c237e94a | 10083 | static int |
a06faf84 | 10084 | rs6000_adjust_cost (insn, link, dep_insn, cost) |
a251ffd0 TG |
10085 | rtx insn; |
10086 | rtx link; | |
296b8152 | 10087 | rtx dep_insn ATTRIBUTE_UNUSED; |
a251ffd0 TG |
10088 | int cost; |
10089 | { | |
10090 | if (! recog_memoized (insn)) | |
10091 | return 0; | |
10092 | ||
10093 | if (REG_NOTE_KIND (link) != 0) | |
10094 | return 0; | |
10095 | ||
10096 | if (REG_NOTE_KIND (link) == 0) | |
10097 | { | |
ed947a96 DJ |
10098 | /* Data dependency; DEP_INSN writes a register that INSN reads |
10099 | some cycles later. */ | |
10100 | switch (get_attr_type (insn)) | |
10101 | { | |
10102 | case TYPE_JMPREG: | |
10103 | /* Tell the first scheduling pass about the latency between | |
10104 | a mtctr and bctr (and mtlr and br/blr). The first | |
10105 | scheduling pass will not know about this latency since | |
10106 | the mtctr instruction, which has the latency associated | |
10107 | to it, will be generated by reload. */ | |
10108 | return TARGET_POWER ? 5 : 4; | |
10109 | case TYPE_BRANCH: | |
10110 | /* Leave some extra cycles between a compare and its | |
10111 | dependent branch, to inhibit expensive mispredicts. */ | |
10112 | if ((rs6000_cpu_attr == CPU_PPC750 | |
10113 | || rs6000_cpu_attr == CPU_PPC7400 | |
10114 | || rs6000_cpu_attr == CPU_PPC7450) | |
10115 | && recog_memoized (dep_insn) | |
10116 | && (INSN_CODE (dep_insn) >= 0) | |
10117 | && (get_attr_type (dep_insn) == TYPE_COMPARE | |
10118 | || get_attr_type (dep_insn) == TYPE_DELAYED_COMPARE | |
10119 | || get_attr_type (dep_insn) == TYPE_FPCOMPARE | |
10120 | || get_attr_type (dep_insn) == TYPE_CR_LOGICAL)) | |
10121 | return cost + 2; | |
10122 | default: | |
10123 | break; | |
10124 | } | |
a251ffd0 TG |
10125 | /* Fall out to return default cost. */ |
10126 | } | |
10127 | ||
10128 | return cost; | |
10129 | } | |
b6c9286a | 10130 | |
a4f6c312 SS |
10131 | /* A C statement (sans semicolon) to update the integer scheduling |
10132 | priority INSN_PRIORITY (INSN). Reduce the priority to execute the | |
10133 | INSN earlier, increase the priority to execute INSN later. Do not | |
10134 | define this macro if you do not need to adjust the scheduling | |
10135 | priorities of insns. */ | |
bef84347 | 10136 | |
c237e94a | 10137 | static int |
bef84347 | 10138 | rs6000_adjust_priority (insn, priority) |
d330fd93 | 10139 | rtx insn ATTRIBUTE_UNUSED; |
bef84347 VM |
10140 | int priority; |
10141 | { | |
a4f6c312 SS |
10142 | /* On machines (like the 750) which have asymmetric integer units, |
10143 | where one integer unit can do multiply and divides and the other | |
10144 | can't, reduce the priority of multiply/divide so it is scheduled | |
10145 | before other integer operations. */ | |
bef84347 VM |
10146 | |
10147 | #if 0 | |
2c3c49de | 10148 | if (! INSN_P (insn)) |
bef84347 VM |
10149 | return priority; |
10150 | ||
10151 | if (GET_CODE (PATTERN (insn)) == USE) | |
10152 | return priority; | |
10153 | ||
10154 | switch (rs6000_cpu_attr) { | |
10155 | case CPU_PPC750: | |
10156 | switch (get_attr_type (insn)) | |
10157 | { | |
10158 | default: | |
10159 | break; | |
10160 | ||
10161 | case TYPE_IMUL: | |
10162 | case TYPE_IDIV: | |
3cb999d8 DE |
10163 | fprintf (stderr, "priority was %#x (%d) before adjustment\n", |
10164 | priority, priority); | |
bef84347 VM |
10165 | if (priority >= 0 && priority < 0x01000000) |
10166 | priority >>= 3; | |
10167 | break; | |
10168 | } | |
10169 | } | |
10170 | #endif | |
10171 | ||
10172 | return priority; | |
10173 | } | |
10174 | ||
a4f6c312 SS |
10175 | /* Return how many instructions the machine can issue per cycle. */ |
10176 | ||
c237e94a ZW |
10177 | static int |
10178 | rs6000_issue_rate () | |
b6c9286a MM |
10179 | { |
10180 | switch (rs6000_cpu_attr) { | |
3cb999d8 DE |
10181 | case CPU_RIOS1: /* ? */ |
10182 | case CPU_RS64A: | |
10183 | case CPU_PPC601: /* ? */ | |
ed947a96 | 10184 | case CPU_PPC7450: |
3cb999d8 | 10185 | return 3; |
b6c9286a | 10186 | case CPU_PPC603: |
bef84347 | 10187 | case CPU_PPC750: |
ed947a96 | 10188 | case CPU_PPC7400: |
bef84347 | 10189 | return 2; |
3cb999d8 | 10190 | case CPU_RIOS2: |
b6c9286a | 10191 | case CPU_PPC604: |
19684119 | 10192 | case CPU_PPC604E: |
b6c9286a | 10193 | case CPU_PPC620: |
3cb999d8 | 10194 | case CPU_PPC630: |
b6c9286a MM |
10195 | return 4; |
10196 | default: | |
10197 | return 1; | |
10198 | } | |
10199 | } | |
10200 | ||
b6c9286a | 10201 | \f |
b6c9286a MM |
10202 | /* Length in units of the trampoline for entering a nested function. */ |
10203 | ||
10204 | int | |
10205 | rs6000_trampoline_size () | |
10206 | { | |
10207 | int ret = 0; | |
10208 | ||
10209 | switch (DEFAULT_ABI) | |
10210 | { | |
10211 | default: | |
10212 | abort (); | |
10213 | ||
10214 | case ABI_AIX: | |
8f802bfb | 10215 | ret = (TARGET_32BIT) ? 12 : 24; |
b6c9286a MM |
10216 | break; |
10217 | ||
4dabc42d | 10218 | case ABI_DARWIN: |
b6c9286a MM |
10219 | case ABI_V4: |
10220 | case ABI_AIX_NODESC: | |
03a7e1a5 | 10221 | ret = (TARGET_32BIT) ? 40 : 48; |
b6c9286a | 10222 | break; |
b6c9286a MM |
10223 | } |
10224 | ||
10225 | return ret; | |
10226 | } | |
10227 | ||
10228 | /* Emit RTL insns to initialize the variable parts of a trampoline. | |
10229 | FNADDR is an RTX for the address of the function's pure code. | |
10230 | CXT is an RTX for the static chain value for the function. */ | |
10231 | ||
10232 | void | |
10233 | rs6000_initialize_trampoline (addr, fnaddr, cxt) | |
10234 | rtx addr; | |
10235 | rtx fnaddr; | |
10236 | rtx cxt; | |
10237 | { | |
ac2a93a1 | 10238 | enum machine_mode pmode = Pmode; |
8bd04c56 MM |
10239 | int regsize = (TARGET_32BIT) ? 4 : 8; |
10240 | rtx ctx_reg = force_reg (pmode, cxt); | |
b6c9286a MM |
10241 | |
10242 | switch (DEFAULT_ABI) | |
10243 | { | |
10244 | default: | |
10245 | abort (); | |
10246 | ||
8bd04c56 | 10247 | /* Macros to shorten the code expansions below. */ |
39403d82 | 10248 | #define MEM_DEREF(addr) gen_rtx_MEM (pmode, memory_address (pmode, addr)) |
c5c76735 JL |
10249 | #define MEM_PLUS(addr,offset) \ |
10250 | gen_rtx_MEM (pmode, memory_address (pmode, plus_constant (addr, offset))) | |
7c59dc5d | 10251 | |
b6c9286a MM |
10252 | /* Under AIX, just build the 3 word function descriptor */ |
10253 | case ABI_AIX: | |
8bd04c56 MM |
10254 | { |
10255 | rtx fn_reg = gen_reg_rtx (pmode); | |
10256 | rtx toc_reg = gen_reg_rtx (pmode); | |
10257 | emit_move_insn (fn_reg, MEM_DEREF (fnaddr)); | |
1cb18e3c | 10258 | emit_move_insn (toc_reg, MEM_PLUS (fnaddr, regsize)); |
8bd04c56 MM |
10259 | emit_move_insn (MEM_DEREF (addr), fn_reg); |
10260 | emit_move_insn (MEM_PLUS (addr, regsize), toc_reg); | |
10261 | emit_move_insn (MEM_PLUS (addr, 2*regsize), ctx_reg); | |
10262 | } | |
b6c9286a MM |
10263 | break; |
10264 | ||
4dabc42d TC |
10265 | /* Under V.4/eabi/darwin, __trampoline_setup does the real work. */ |
10266 | case ABI_DARWIN: | |
b6c9286a MM |
10267 | case ABI_V4: |
10268 | case ABI_AIX_NODESC: | |
39403d82 | 10269 | emit_library_call (gen_rtx_SYMBOL_REF (SImode, "__trampoline_setup"), |
eaf1bcf1 MM |
10270 | FALSE, VOIDmode, 4, |
10271 | addr, pmode, | |
10272 | GEN_INT (rs6000_trampoline_size ()), SImode, | |
10273 | fnaddr, pmode, | |
10274 | ctx_reg, pmode); | |
b6c9286a | 10275 | break; |
b6c9286a MM |
10276 | } |
10277 | ||
10278 | return; | |
10279 | } | |
7509c759 MM |
10280 | |
10281 | \f | |
91d231cb | 10282 | /* Table of valid machine attributes. */ |
a4f6c312 | 10283 | |
91d231cb | 10284 | const struct attribute_spec rs6000_attribute_table[] = |
7509c759 | 10285 | { |
91d231cb JM |
10286 | /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */ |
10287 | { "longcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute }, | |
10288 | { NULL, 0, 0, false, false, false, NULL } | |
10289 | }; | |
7509c759 | 10290 | |
a4f6c312 SS |
10291 | /* Handle a "longcall" attribute; arguments as in struct |
10292 | attribute_spec.handler. */ | |
10293 | ||
91d231cb JM |
10294 | static tree |
10295 | rs6000_handle_longcall_attribute (node, name, args, flags, no_add_attrs) | |
10296 | tree *node; | |
10297 | tree name; | |
10298 | tree args ATTRIBUTE_UNUSED; | |
10299 | int flags ATTRIBUTE_UNUSED; | |
10300 | bool *no_add_attrs; | |
10301 | { | |
10302 | if (TREE_CODE (*node) != FUNCTION_TYPE | |
10303 | && TREE_CODE (*node) != FIELD_DECL | |
10304 | && TREE_CODE (*node) != TYPE_DECL) | |
10305 | { | |
10306 | warning ("`%s' attribute only applies to functions", | |
10307 | IDENTIFIER_POINTER (name)); | |
10308 | *no_add_attrs = true; | |
10309 | } | |
6a4cee5f | 10310 | |
91d231cb | 10311 | return NULL_TREE; |
7509c759 MM |
10312 | } |
10313 | ||
3cb999d8 DE |
10314 | /* Return a reference suitable for calling a function with the |
10315 | longcall attribute. */ | |
a4f6c312 | 10316 | |
6a4cee5f MM |
10317 | struct rtx_def * |
10318 | rs6000_longcall_ref (call_ref) | |
10319 | rtx call_ref; | |
10320 | { | |
d330fd93 | 10321 | const char *call_name; |
6a4cee5f MM |
10322 | tree node; |
10323 | ||
10324 | if (GET_CODE (call_ref) != SYMBOL_REF) | |
10325 | return call_ref; | |
10326 | ||
10327 | /* System V adds '.' to the internal name, so skip them. */ | |
10328 | call_name = XSTR (call_ref, 0); | |
10329 | if (*call_name == '.') | |
10330 | { | |
10331 | while (*call_name == '.') | |
10332 | call_name++; | |
10333 | ||
10334 | node = get_identifier (call_name); | |
39403d82 | 10335 | call_ref = gen_rtx_SYMBOL_REF (VOIDmode, IDENTIFIER_POINTER (node)); |
6a4cee5f MM |
10336 | } |
10337 | ||
10338 | return force_reg (Pmode, call_ref); | |
10339 | } | |
10340 | ||
7509c759 MM |
10341 | \f |
10342 | /* A C statement or statements to switch to the appropriate section | |
10343 | for output of RTX in mode MODE. You can assume that RTX is some | |
10344 | kind of constant in RTL. The argument MODE is redundant except in | |
10345 | the case of a `const_int' rtx. Select the section by calling | |
10346 | `text_section' or one of the alternatives for other sections. | |
10347 | ||
10348 | Do not define this macro if you put all constants in the read-only | |
10349 | data section. */ | |
10350 | ||
b91da81f | 10351 | #ifdef USING_ELFOS_H |
7509c759 MM |
10352 | |
10353 | void | |
10354 | rs6000_select_rtx_section (mode, x) | |
a9098fd0 | 10355 | enum machine_mode mode; |
7509c759 MM |
10356 | rtx x; |
10357 | { | |
a9098fd0 | 10358 | if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode)) |
7509c759 | 10359 | toc_section (); |
7509c759 MM |
10360 | else |
10361 | const_section (); | |
10362 | } | |
10363 | ||
10364 | /* A C statement or statements to switch to the appropriate | |
10365 | section for output of DECL. DECL is either a `VAR_DECL' node | |
10366 | or a constant of some sort. RELOC indicates whether forming | |
10367 | the initial value of DECL requires link-time relocations. */ | |
10368 | ||
10369 | void | |
10370 | rs6000_select_section (decl, reloc) | |
10371 | tree decl; | |
10372 | int reloc; | |
10373 | { | |
10374 | int size = int_size_in_bytes (TREE_TYPE (decl)); | |
63019373 GK |
10375 | int needs_sdata; |
10376 | int readonly; | |
10377 | static void (* const sec_funcs[4]) PARAMS ((void)) = { | |
10378 | &const_section, | |
10379 | &sdata2_section, | |
10380 | &data_section, | |
10381 | &sdata_section | |
10382 | }; | |
10383 | ||
10384 | needs_sdata = (size > 0 | |
10385 | && size <= g_switch_value | |
10386 | && rs6000_sdata != SDATA_NONE | |
10387 | && (rs6000_sdata != SDATA_DATA || TREE_PUBLIC (decl))); | |
7509c759 MM |
10388 | |
10389 | if (TREE_CODE (decl) == STRING_CST) | |
63019373 | 10390 | readonly = ! flag_writable_strings; |
a9098fd0 | 10391 | else if (TREE_CODE (decl) == VAR_DECL) |
63019373 GK |
10392 | readonly = (! (flag_pic && reloc) |
10393 | && TREE_READONLY (decl) | |
10394 | && ! TREE_SIDE_EFFECTS (decl) | |
10395 | && DECL_INITIAL (decl) | |
10396 | && DECL_INITIAL (decl) != error_mark_node | |
10397 | && TREE_CONSTANT (DECL_INITIAL (decl))); | |
ac4f7ad9 GK |
10398 | else if (TREE_CODE (decl) == CONSTRUCTOR) |
10399 | readonly = (! (flag_pic && reloc) | |
ac4f7ad9 | 10400 | && ! TREE_SIDE_EFFECTS (decl) |
f3afc192 | 10401 | && TREE_CONSTANT (decl)); |
7509c759 | 10402 | else |
63019373 GK |
10403 | readonly = 1; |
10404 | if (needs_sdata && rs6000_sdata != SDATA_EABI) | |
10405 | readonly = 0; | |
10406 | ||
10407 | (*sec_funcs[(readonly ? 0 : 2) + (needs_sdata ? 1 : 0)])(); | |
10408 | } | |
10409 | ||
10410 | /* A C statement to build up a unique section name, expressed as a | |
10411 | STRING_CST node, and assign it to DECL_SECTION_NAME (decl). | |
10412 | RELOC indicates whether the initial value of EXP requires | |
10413 | link-time relocations. If you do not define this macro, GCC will use | |
10414 | the symbol name prefixed by `.' as the section name. Note - this | |
f5143c46 | 10415 | macro can now be called for uninitialized data items as well as |
63019373 GK |
10416 | initialised data and functions. */ |
10417 | ||
10418 | void | |
10419 | rs6000_unique_section (decl, reloc) | |
10420 | tree decl; | |
10421 | int reloc; | |
10422 | { | |
63019373 GK |
10423 | int len; |
10424 | int sec; | |
10425 | const char *name; | |
10426 | char *string; | |
10427 | const char *prefix; | |
10428 | ||
10429 | static const char *const prefixes[7][2] = | |
10430 | { | |
63019373 GK |
10431 | { ".rodata.", ".gnu.linkonce.r." }, |
10432 | { ".sdata2.", ".gnu.linkonce.s2." }, | |
10433 | { ".data.", ".gnu.linkonce.d." }, | |
10434 | { ".sdata.", ".gnu.linkonce.s." }, | |
10435 | { ".bss.", ".gnu.linkonce.b." }, | |
5b8c2356 AM |
10436 | { ".sbss.", ".gnu.linkonce.sb." }, |
10437 | { ".text.", ".gnu.linkonce.t." } | |
63019373 | 10438 | }; |
63019373 | 10439 | |
5b8c2356 AM |
10440 | if (TREE_CODE (decl) == FUNCTION_DECL) |
10441 | sec = 6; | |
63019373 | 10442 | else |
5b8c2356 AM |
10443 | { |
10444 | int readonly; | |
10445 | int needs_sdata; | |
10446 | int size; | |
10447 | ||
10448 | readonly = 1; | |
10449 | if (TREE_CODE (decl) == STRING_CST) | |
10450 | readonly = ! flag_writable_strings; | |
10451 | else if (TREE_CODE (decl) == VAR_DECL) | |
10452 | readonly = (! (flag_pic && reloc) | |
10453 | && TREE_READONLY (decl) | |
10454 | && ! TREE_SIDE_EFFECTS (decl) | |
10455 | && TREE_CONSTANT (DECL_INITIAL (decl))); | |
10456 | ||
10457 | size = int_size_in_bytes (TREE_TYPE (decl)); | |
10458 | needs_sdata = (size > 0 | |
10459 | && size <= g_switch_value | |
10460 | && rs6000_sdata != SDATA_NONE | |
10461 | && (rs6000_sdata != SDATA_DATA || TREE_PUBLIC (decl))); | |
10462 | ||
10463 | if (DECL_INITIAL (decl) == 0 | |
10464 | || DECL_INITIAL (decl) == error_mark_node) | |
10465 | sec = 4; | |
10466 | else if (! readonly) | |
10467 | sec = 2; | |
10468 | else | |
10469 | sec = 0; | |
63019373 | 10470 | |
5b8c2356 AM |
10471 | if (needs_sdata) |
10472 | { | |
10473 | /* .sdata2 is only for EABI. */ | |
10474 | if (sec == 0 && rs6000_sdata != SDATA_EABI) | |
10475 | sec = 2; | |
10476 | sec += 1; | |
10477 | } | |
10478 | } | |
63019373 | 10479 | |
e6978109 | 10480 | STRIP_NAME_ENCODING (name, IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl))); |
63019373 GK |
10481 | prefix = prefixes[sec][DECL_ONE_ONLY (decl)]; |
10482 | len = strlen (name) + strlen (prefix); | |
10483 | string = alloca (len + 1); | |
10484 | ||
10485 | sprintf (string, "%s%s", prefix, name); | |
10486 | ||
10487 | DECL_SECTION_NAME (decl) = build_string (len, string); | |
7509c759 | 10488 | } |
d9407988 MM |
10489 | |
10490 | \f | |
d9407988 MM |
10491 | /* If we are referencing a function that is static or is known to be |
10492 | in this file, make the SYMBOL_REF special. We can use this to indicate | |
10493 | that we can branch to this function without emitting a no-op after the | |
9ebbca7d | 10494 | call. For real AIX calling sequences, we also replace the |
d9407988 MM |
10495 | function name with the real name (1 or 2 leading .'s), rather than |
10496 | the function descriptor name. This saves a lot of overriding code | |
a260abc9 | 10497 | to read the prefixes. */ |
d9407988 MM |
10498 | |
10499 | void | |
10500 | rs6000_encode_section_info (decl) | |
10501 | tree decl; | |
10502 | { | |
10503 | if (TREE_CODE (decl) == FUNCTION_DECL) | |
10504 | { | |
10505 | rtx sym_ref = XEXP (DECL_RTL (decl), 0); | |
8f1b829e | 10506 | if ((TREE_ASM_WRITTEN (decl) || ! TREE_PUBLIC (decl)) |
c81fc13e | 10507 | && ! DECL_WEAK (decl)) |
d9407988 MM |
10508 | SYMBOL_REF_FLAG (sym_ref) = 1; |
10509 | ||
9ebbca7d | 10510 | if (DEFAULT_ABI == ABI_AIX) |
d9407988 | 10511 | { |
ff669a6c RH |
10512 | size_t len1 = (DEFAULT_ABI == ABI_AIX) ? 1 : 2; |
10513 | size_t len2 = strlen (XSTR (sym_ref, 0)); | |
520a57c8 | 10514 | char *str = alloca (len1 + len2 + 1); |
ff669a6c RH |
10515 | str[0] = '.'; |
10516 | str[1] = '.'; | |
10517 | memcpy (str + len1, XSTR (sym_ref, 0), len2 + 1); | |
10518 | ||
520a57c8 | 10519 | XSTR (sym_ref, 0) = ggc_alloc_string (str, len1 + len2); |
d9407988 MM |
10520 | } |
10521 | } | |
10522 | else if (rs6000_sdata != SDATA_NONE | |
f607bc57 | 10523 | && DEFAULT_ABI == ABI_V4 |
d9407988 MM |
10524 | && TREE_CODE (decl) == VAR_DECL) |
10525 | { | |
10526 | int size = int_size_in_bytes (TREE_TYPE (decl)); | |
10527 | tree section_name = DECL_SECTION_NAME (decl); | |
d330fd93 | 10528 | const char *name = (char *)0; |
d9407988 MM |
10529 | int len = 0; |
10530 | ||
10531 | if (section_name) | |
10532 | { | |
10533 | if (TREE_CODE (section_name) == STRING_CST) | |
10534 | { | |
10535 | name = TREE_STRING_POINTER (section_name); | |
10536 | len = TREE_STRING_LENGTH (section_name); | |
10537 | } | |
10538 | else | |
10539 | abort (); | |
10540 | } | |
10541 | ||
10542 | if ((size > 0 && size <= g_switch_value) | |
10543 | || (name | |
5f59ecb7 | 10544 | && ((len == sizeof (".sdata") - 1 |
3cb999d8 | 10545 | && strcmp (name, ".sdata") == 0) |
5f59ecb7 | 10546 | || (len == sizeof (".sdata2") - 1 |
3cb999d8 | 10547 | && strcmp (name, ".sdata2") == 0) |
5f59ecb7 | 10548 | || (len == sizeof (".sbss") - 1 |
3cb999d8 | 10549 | && strcmp (name, ".sbss") == 0) |
5f59ecb7 | 10550 | || (len == sizeof (".sbss2") - 1 |
3cb999d8 | 10551 | && strcmp (name, ".sbss2") == 0) |
5f59ecb7 | 10552 | || (len == sizeof (".PPC.EMB.sdata0") - 1 |
3cb999d8 | 10553 | && strcmp (name, ".PPC.EMB.sdata0") == 0) |
5f59ecb7 | 10554 | || (len == sizeof (".PPC.EMB.sbss0") - 1 |
3cb999d8 | 10555 | && strcmp (name, ".PPC.EMB.sbss0") == 0)))) |
d9407988 MM |
10556 | { |
10557 | rtx sym_ref = XEXP (DECL_RTL (decl), 0); | |
ff669a6c | 10558 | size_t len = strlen (XSTR (sym_ref, 0)); |
88c1e412 | 10559 | char *str = alloca (len + 2); |
ff669a6c | 10560 | |
ff669a6c RH |
10561 | str[0] = '@'; |
10562 | memcpy (str + 1, XSTR (sym_ref, 0), len + 1); | |
88c1e412 | 10563 | XSTR (sym_ref, 0) = ggc_alloc_string (str, len + 1); |
d9407988 MM |
10564 | } |
10565 | } | |
10566 | } | |
10567 | ||
b91da81f | 10568 | #endif /* USING_ELFOS_H */ |
000034eb | 10569 | |
a6c2a102 | 10570 | \f |
000034eb | 10571 | /* Return a REG that occurs in ADDR with coefficient 1. |
02441cd6 JL |
10572 | ADDR can be effectively incremented by incrementing REG. |
10573 | ||
10574 | r0 is special and we must not select it as an address | |
10575 | register by this routine since our caller will try to | |
10576 | increment the returned register via an "la" instruction. */ | |
000034eb DE |
10577 | |
10578 | struct rtx_def * | |
10579 | find_addr_reg (addr) | |
10580 | rtx addr; | |
10581 | { | |
10582 | while (GET_CODE (addr) == PLUS) | |
10583 | { | |
02441cd6 JL |
10584 | if (GET_CODE (XEXP (addr, 0)) == REG |
10585 | && REGNO (XEXP (addr, 0)) != 0) | |
000034eb | 10586 | addr = XEXP (addr, 0); |
02441cd6 JL |
10587 | else if (GET_CODE (XEXP (addr, 1)) == REG |
10588 | && REGNO (XEXP (addr, 1)) != 0) | |
000034eb DE |
10589 | addr = XEXP (addr, 1); |
10590 | else if (CONSTANT_P (XEXP (addr, 0))) | |
10591 | addr = XEXP (addr, 1); | |
10592 | else if (CONSTANT_P (XEXP (addr, 1))) | |
10593 | addr = XEXP (addr, 0); | |
10594 | else | |
10595 | abort (); | |
10596 | } | |
02441cd6 | 10597 | if (GET_CODE (addr) == REG && REGNO (addr) != 0) |
000034eb DE |
10598 | return addr; |
10599 | abort (); | |
10600 | } | |
10601 | ||
a6c2a102 DE |
10602 | void |
10603 | rs6000_fatal_bad_address (op) | |
10604 | rtx op; | |
10605 | { | |
10606 | fatal_insn ("bad address", op); | |
10607 | } | |
c8023011 MM |
10608 | |
10609 | /* Called to register all of our global variables with the garbage | |
10610 | collector. */ | |
10611 | ||
10612 | static void | |
10613 | rs6000_add_gc_roots () | |
10614 | { | |
10615 | ggc_add_rtx_root (&rs6000_compare_op0, 1); | |
10616 | ggc_add_rtx_root (&rs6000_compare_op1, 1); | |
9ebbca7d GK |
10617 | |
10618 | toc_hash_table = htab_create (1021, toc_hash_function, toc_hash_eq, NULL); | |
10619 | ggc_add_root (&toc_hash_table, 1, sizeof (toc_hash_table), | |
10620 | toc_hash_mark_table); | |
ee890fe2 SS |
10621 | |
10622 | #if TARGET_MACHO | |
10623 | machopic_add_gc_roots (); | |
10624 | #endif | |
10625 | } | |
10626 | ||
10627 | #if TARGET_MACHO | |
10628 | ||
10629 | #if 0 | |
10630 | /* Returns 1 if OP is either a symbol reference or a sum of a symbol | |
10631 | reference and a constant. */ | |
10632 | ||
10633 | int | |
10634 | symbolic_operand (op) | |
592696dd | 10635 | rtx op; |
ee890fe2 SS |
10636 | { |
10637 | switch (GET_CODE (op)) | |
10638 | { | |
10639 | case SYMBOL_REF: | |
10640 | case LABEL_REF: | |
10641 | return 1; | |
10642 | case CONST: | |
10643 | op = XEXP (op, 0); | |
10644 | return (GET_CODE (op) == SYMBOL_REF || | |
10645 | (GET_CODE (XEXP (op, 0)) == SYMBOL_REF | |
10646 | || GET_CODE (XEXP (op, 0)) == LABEL_REF) | |
10647 | && GET_CODE (XEXP (op, 1)) == CONST_INT); | |
10648 | default: | |
10649 | return 0; | |
10650 | } | |
c8023011 | 10651 | } |
ee890fe2 SS |
10652 | #endif |
10653 | ||
10654 | #ifdef RS6000_LONG_BRANCH | |
10655 | ||
10656 | static tree stub_list = 0; | |
10657 | ||
10658 | /* ADD_COMPILER_STUB adds the compiler generated stub for handling | |
10659 | procedure calls to the linked list. */ | |
10660 | ||
10661 | void | |
10662 | add_compiler_stub (label_name, function_name, line_number) | |
10663 | tree label_name; | |
10664 | tree function_name; | |
10665 | int line_number; | |
10666 | { | |
10667 | tree stub = build_tree_list (function_name, label_name); | |
10668 | TREE_TYPE (stub) = build_int_2 (line_number, 0); | |
10669 | TREE_CHAIN (stub) = stub_list; | |
10670 | stub_list = stub; | |
10671 | } | |
10672 | ||
10673 | #define STUB_LABEL_NAME(STUB) TREE_VALUE (STUB) | |
10674 | #define STUB_FUNCTION_NAME(STUB) TREE_PURPOSE (STUB) | |
10675 | #define STUB_LINE_NUMBER(STUB) TREE_INT_CST_LOW (TREE_TYPE (STUB)) | |
10676 | ||
a4f6c312 SS |
10677 | /* OUTPUT_COMPILER_STUB outputs the compiler generated stub for |
10678 | handling procedure calls from the linked list and initializes the | |
10679 | linked list. */ | |
ee890fe2 | 10680 | |
a4f6c312 SS |
10681 | void |
10682 | output_compiler_stub () | |
ee890fe2 SS |
10683 | { |
10684 | char tmp_buf[256]; | |
10685 | char label_buf[256]; | |
10686 | char *label; | |
10687 | tree tmp_stub, stub; | |
10688 | ||
10689 | if (!flag_pic) | |
10690 | for (stub = stub_list; stub; stub = TREE_CHAIN (stub)) | |
10691 | { | |
10692 | fprintf (asm_out_file, | |
10693 | "%s:\n", IDENTIFIER_POINTER(STUB_LABEL_NAME(stub))); | |
10694 | ||
10695 | #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO) | |
10696 | if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG) | |
10697 | fprintf (asm_out_file, "\t.stabd 68,0,%d\n", STUB_LINE_NUMBER(stub)); | |
10698 | #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */ | |
10699 | ||
10700 | if (IDENTIFIER_POINTER (STUB_FUNCTION_NAME (stub))[0] == '*') | |
10701 | strcpy (label_buf, | |
10702 | IDENTIFIER_POINTER (STUB_FUNCTION_NAME (stub))+1); | |
10703 | else | |
10704 | { | |
10705 | label_buf[0] = '_'; | |
10706 | strcpy (label_buf+1, | |
10707 | IDENTIFIER_POINTER (STUB_FUNCTION_NAME (stub))); | |
10708 | } | |
10709 | ||
10710 | strcpy (tmp_buf, "lis r12,hi16("); | |
10711 | strcat (tmp_buf, label_buf); | |
10712 | strcat (tmp_buf, ")\n\tori r12,r12,lo16("); | |
10713 | strcat (tmp_buf, label_buf); | |
10714 | strcat (tmp_buf, ")\n\tmtctr r12\n\tbctr"); | |
10715 | output_asm_insn (tmp_buf, 0); | |
10716 | ||
10717 | #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO) | |
10718 | if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG) | |
10719 | fprintf(asm_out_file, "\t.stabd 68,0,%d\n", STUB_LINE_NUMBER (stub)); | |
10720 | #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */ | |
10721 | } | |
10722 | ||
10723 | stub_list = 0; | |
10724 | } | |
10725 | ||
10726 | /* NO_PREVIOUS_DEF checks in the link list whether the function name is | |
10727 | already there or not. */ | |
10728 | ||
a4f6c312 SS |
10729 | int |
10730 | no_previous_def (function_name) | |
ee890fe2 SS |
10731 | tree function_name; |
10732 | { | |
10733 | tree stub; | |
10734 | for (stub = stub_list; stub; stub = TREE_CHAIN (stub)) | |
10735 | if (function_name == STUB_FUNCTION_NAME (stub)) | |
10736 | return 0; | |
10737 | return 1; | |
10738 | } | |
10739 | ||
10740 | /* GET_PREV_LABEL gets the label name from the previous definition of | |
10741 | the function. */ | |
10742 | ||
a4f6c312 SS |
10743 | tree |
10744 | get_prev_label (function_name) | |
ee890fe2 SS |
10745 | tree function_name; |
10746 | { | |
10747 | tree stub; | |
10748 | for (stub = stub_list; stub; stub = TREE_CHAIN (stub)) | |
10749 | if (function_name == STUB_FUNCTION_NAME (stub)) | |
10750 | return STUB_LABEL_NAME (stub); | |
10751 | return 0; | |
10752 | } | |
10753 | ||
10754 | /* INSN is either a function call or a millicode call. It may have an | |
10755 | unconditional jump in its delay slot. | |
10756 | ||
10757 | CALL_DEST is the routine we are calling. */ | |
10758 | ||
10759 | char * | |
10760 | output_call (insn, call_dest, operand_number) | |
10761 | rtx insn; | |
10762 | rtx call_dest; | |
10763 | int operand_number; | |
10764 | { | |
10765 | static char buf[256]; | |
10766 | if (GET_CODE (call_dest) == SYMBOL_REF && TARGET_LONG_BRANCH && !flag_pic) | |
10767 | { | |
10768 | tree labelname; | |
10769 | tree funname = get_identifier (XSTR (call_dest, 0)); | |
10770 | ||
10771 | if (no_previous_def (funname)) | |
10772 | { | |
10773 | int line_number; | |
10774 | rtx label_rtx = gen_label_rtx (); | |
10775 | char *label_buf, temp_buf[256]; | |
10776 | ASM_GENERATE_INTERNAL_LABEL (temp_buf, "L", | |
10777 | CODE_LABEL_NUMBER (label_rtx)); | |
10778 | label_buf = temp_buf[0] == '*' ? temp_buf + 1 : temp_buf; | |
10779 | labelname = get_identifier (label_buf); | |
10780 | for (; insn && GET_CODE (insn) != NOTE; insn = PREV_INSN (insn)); | |
10781 | if (insn) | |
10782 | line_number = NOTE_LINE_NUMBER (insn); | |
10783 | add_compiler_stub (labelname, funname, line_number); | |
10784 | } | |
10785 | else | |
10786 | labelname = get_prev_label (funname); | |
10787 | ||
10788 | sprintf (buf, "jbsr %%z%d,%.246s", | |
10789 | operand_number, IDENTIFIER_POINTER (labelname)); | |
10790 | return buf; | |
10791 | } | |
10792 | else | |
10793 | { | |
10794 | sprintf (buf, "bl %%z%d", operand_number); | |
10795 | return buf; | |
10796 | } | |
10797 | } | |
10798 | ||
10799 | #endif /* RS6000_LONG_BRANCH */ | |
10800 | ||
10801 | #define GEN_LOCAL_LABEL_FOR_SYMBOL(BUF,SYMBOL,LENGTH,N) \ | |
10802 | do { \ | |
83182544 | 10803 | const char *const symbol_ = (SYMBOL); \ |
ee890fe2 SS |
10804 | char *buffer_ = (BUF); \ |
10805 | if (symbol_[0] == '"') \ | |
10806 | { \ | |
10807 | sprintf(buffer_, "\"L%d$%s", (N), symbol_+1); \ | |
10808 | } \ | |
10809 | else if (name_needs_quotes(symbol_)) \ | |
10810 | { \ | |
10811 | sprintf(buffer_, "\"L%d$%s\"", (N), symbol_); \ | |
10812 | } \ | |
10813 | else \ | |
10814 | { \ | |
10815 | sprintf(buffer_, "L%d$%s", (N), symbol_); \ | |
10816 | } \ | |
10817 | } while (0) | |
10818 | ||
10819 | ||
10820 | /* Generate PIC and indirect symbol stubs. */ | |
10821 | ||
10822 | void | |
10823 | machopic_output_stub (file, symb, stub) | |
10824 | FILE *file; | |
10825 | const char *symb, *stub; | |
10826 | { | |
10827 | unsigned int length; | |
a4f6c312 SS |
10828 | char *symbol_name, *lazy_ptr_name; |
10829 | char *local_label_0; | |
ee890fe2 SS |
10830 | static int label = 0; |
10831 | ||
df56a27f SS |
10832 | /* Lose our funky encoding stuff so it doesn't contaminate the stub. */ |
10833 | STRIP_NAME_ENCODING (symb, symb); | |
10834 | ||
ee890fe2 SS |
10835 | label += 1; |
10836 | ||
ee890fe2 SS |
10837 | length = strlen (symb); |
10838 | symbol_name = alloca (length + 32); | |
10839 | GEN_SYMBOL_NAME_FOR_SYMBOL (symbol_name, symb, length); | |
10840 | ||
10841 | lazy_ptr_name = alloca (length + 32); | |
10842 | GEN_LAZY_PTR_NAME_FOR_SYMBOL (lazy_ptr_name, symb, length); | |
10843 | ||
10844 | local_label_0 = alloca (length + 32); | |
10845 | GEN_LOCAL_LABEL_FOR_SYMBOL (local_label_0, symb, length, 0); | |
10846 | ||
ee890fe2 SS |
10847 | if (flag_pic == 2) |
10848 | machopic_picsymbol_stub_section (); | |
10849 | else | |
10850 | machopic_symbol_stub_section (); | |
10851 | ||
10852 | fprintf (file, "%s:\n", stub); | |
10853 | fprintf (file, "\t.indirect_symbol %s\n", symbol_name); | |
10854 | ||
10855 | if (flag_pic == 2) | |
10856 | { | |
10857 | fprintf (file, "\tmflr r0\n"); | |
10858 | fprintf (file, "\tbcl 20,31,%s\n", local_label_0); | |
10859 | fprintf (file, "%s:\n\tmflr r11\n", local_label_0); | |
10860 | fprintf (file, "\taddis r11,r11,ha16(%s-%s)\n", | |
10861 | lazy_ptr_name, local_label_0); | |
10862 | fprintf (file, "\tmtlr r0\n"); | |
10863 | fprintf (file, "\tlwz r12,lo16(%s-%s)(r11)\n", | |
10864 | lazy_ptr_name, local_label_0); | |
10865 | fprintf (file, "\tmtctr r12\n"); | |
10866 | fprintf (file, "\taddi r11,r11,lo16(%s-%s)\n", | |
10867 | lazy_ptr_name, local_label_0); | |
10868 | fprintf (file, "\tbctr\n"); | |
10869 | } | |
10870 | else | |
10871 | fprintf (file, "non-pure not supported\n"); | |
10872 | ||
10873 | machopic_lazy_symbol_ptr_section (); | |
10874 | fprintf (file, "%s:\n", lazy_ptr_name); | |
10875 | fprintf (file, "\t.indirect_symbol %s\n", symbol_name); | |
10876 | fprintf (file, "\t.long dyld_stub_binding_helper\n"); | |
10877 | } | |
10878 | ||
10879 | /* Legitimize PIC addresses. If the address is already | |
10880 | position-independent, we return ORIG. Newly generated | |
10881 | position-independent addresses go into a reg. This is REG if non | |
10882 | zero, otherwise we allocate register(s) as necessary. */ | |
10883 | ||
c859cda6 | 10884 | #define SMALL_INT(X) ((unsigned) (INTVAL(X) + 0x8000) < 0x10000) |
ee890fe2 SS |
10885 | |
10886 | rtx | |
10887 | rs6000_machopic_legitimize_pic_address (orig, mode, reg) | |
10888 | rtx orig; | |
10889 | enum machine_mode mode; | |
10890 | rtx reg; | |
10891 | { | |
10892 | rtx base, offset; | |
10893 | ||
10894 | if (reg == NULL && ! reload_in_progress && ! reload_completed) | |
10895 | reg = gen_reg_rtx (Pmode); | |
10896 | ||
10897 | if (GET_CODE (orig) == CONST) | |
10898 | { | |
10899 | if (GET_CODE (XEXP (orig, 0)) == PLUS | |
10900 | && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx) | |
10901 | return orig; | |
10902 | ||
10903 | if (GET_CODE (XEXP (orig, 0)) == PLUS) | |
10904 | { | |
a4f6c312 SS |
10905 | base = |
10906 | rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 0), | |
10907 | Pmode, reg); | |
10908 | offset = | |
10909 | rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 1), | |
10910 | Pmode, reg); | |
ee890fe2 SS |
10911 | } |
10912 | else | |
10913 | abort (); | |
10914 | ||
10915 | if (GET_CODE (offset) == CONST_INT) | |
10916 | { | |
10917 | if (SMALL_INT (offset)) | |
ed8908e7 | 10918 | return plus_constant (base, INTVAL (offset)); |
ee890fe2 SS |
10919 | else if (! reload_in_progress && ! reload_completed) |
10920 | offset = force_reg (Pmode, offset); | |
10921 | else | |
c859cda6 DJ |
10922 | { |
10923 | rtx mem = force_const_mem (Pmode, orig); | |
10924 | return machopic_legitimize_pic_address (mem, Pmode, reg); | |
10925 | } | |
ee890fe2 SS |
10926 | } |
10927 | return gen_rtx (PLUS, Pmode, base, offset); | |
10928 | } | |
10929 | ||
10930 | /* Fall back on generic machopic code. */ | |
10931 | return machopic_legitimize_pic_address (orig, mode, reg); | |
10932 | } | |
10933 | ||
10934 | /* This is just a placeholder to make linking work without having to | |
10935 | add this to the generic Darwin EXTRA_SECTIONS. If -mcall-aix is | |
10936 | ever needed for Darwin (not too likely!) this would have to get a | |
10937 | real definition. */ | |
10938 | ||
10939 | void | |
10940 | toc_section () | |
10941 | { | |
10942 | } | |
10943 | ||
10944 | #endif /* TARGET_MACHO */ | |
7c262518 RH |
10945 | |
10946 | #if TARGET_ELF | |
10947 | static unsigned int | |
10948 | rs6000_elf_section_type_flags (decl, name, reloc) | |
10949 | tree decl; | |
10950 | const char *name; | |
10951 | int reloc; | |
10952 | { | |
10953 | unsigned int flags = default_section_type_flags (decl, name, reloc); | |
10954 | ||
270fc29b RH |
10955 | if (TARGET_RELOCATABLE) |
10956 | flags |= SECTION_WRITE; | |
7c262518 | 10957 | |
d0101753 | 10958 | return flags; |
7c262518 | 10959 | } |
d9f6800d RH |
10960 | |
10961 | /* Record an element in the table of global constructors. SYMBOL is | |
10962 | a SYMBOL_REF of the function to be called; PRIORITY is a number | |
10963 | between 0 and MAX_INIT_PRIORITY. | |
10964 | ||
10965 | This differs from default_named_section_asm_out_constructor in | |
10966 | that we have special handling for -mrelocatable. */ | |
10967 | ||
10968 | static void | |
10969 | rs6000_elf_asm_out_constructor (symbol, priority) | |
10970 | rtx symbol; | |
10971 | int priority; | |
10972 | { | |
10973 | const char *section = ".ctors"; | |
10974 | char buf[16]; | |
10975 | ||
10976 | if (priority != DEFAULT_INIT_PRIORITY) | |
10977 | { | |
10978 | sprintf (buf, ".ctors.%.5u", | |
10979 | /* Invert the numbering so the linker puts us in the proper | |
10980 | order; constructors are run from right to left, and the | |
10981 | linker sorts in increasing order. */ | |
10982 | MAX_INIT_PRIORITY - priority); | |
10983 | section = buf; | |
10984 | } | |
10985 | ||
715bdd29 RH |
10986 | named_section_flags (section, SECTION_WRITE); |
10987 | assemble_align (POINTER_SIZE); | |
d9f6800d RH |
10988 | |
10989 | if (TARGET_RELOCATABLE) | |
10990 | { | |
10991 | fputs ("\t.long (", asm_out_file); | |
10992 | output_addr_const (asm_out_file, symbol); | |
10993 | fputs (")@fixup\n", asm_out_file); | |
10994 | } | |
10995 | else | |
c8af3574 | 10996 | assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1); |
d9f6800d RH |
10997 | } |
10998 | ||
10999 | static void | |
11000 | rs6000_elf_asm_out_destructor (symbol, priority) | |
11001 | rtx symbol; | |
11002 | int priority; | |
11003 | { | |
11004 | const char *section = ".dtors"; | |
11005 | char buf[16]; | |
11006 | ||
11007 | if (priority != DEFAULT_INIT_PRIORITY) | |
11008 | { | |
11009 | sprintf (buf, ".dtors.%.5u", | |
11010 | /* Invert the numbering so the linker puts us in the proper | |
11011 | order; constructors are run from right to left, and the | |
11012 | linker sorts in increasing order. */ | |
11013 | MAX_INIT_PRIORITY - priority); | |
11014 | section = buf; | |
11015 | } | |
11016 | ||
715bdd29 RH |
11017 | named_section_flags (section, SECTION_WRITE); |
11018 | assemble_align (POINTER_SIZE); | |
d9f6800d RH |
11019 | |
11020 | if (TARGET_RELOCATABLE) | |
11021 | { | |
11022 | fputs ("\t.long (", asm_out_file); | |
11023 | output_addr_const (asm_out_file, symbol); | |
11024 | fputs (")@fixup\n", asm_out_file); | |
11025 | } | |
11026 | else | |
c8af3574 | 11027 | assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1); |
d9f6800d | 11028 | } |
7c262518 RH |
11029 | #endif |
11030 | ||
11031 | #ifdef OBJECT_FORMAT_COFF | |
11032 | static void | |
715bdd29 | 11033 | xcoff_asm_named_section (name, flags) |
7c262518 RH |
11034 | const char *name; |
11035 | unsigned int flags ATTRIBUTE_UNUSED; | |
7c262518 RH |
11036 | { |
11037 | fprintf (asm_out_file, "\t.csect %s\n", name); | |
11038 | } | |
11039 | #endif |