]>
Commit | Line | Data |
---|---|---|
9878760c | 1 | /* Subroutines used for code generation on IBM RS/6000. |
f676971a | 2 | Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, |
5b86a469 | 3 | 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc. |
fab3bcc3 | 4 | Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu) |
9878760c | 5 | |
5de601cf | 6 | This file is part of GCC. |
9878760c | 7 | |
5de601cf NC |
8 | GCC is free software; you can redistribute it and/or modify it |
9 | under the terms of the GNU General Public License as published | |
10 | by the Free Software Foundation; either version 2, or (at your | |
11 | option) any later version. | |
9878760c | 12 | |
5de601cf NC |
13 | GCC is distributed in the hope that it will be useful, but WITHOUT |
14 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
15 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
16 | License for more details. | |
9878760c | 17 | |
5de601cf NC |
18 | You should have received a copy of the GNU General Public License |
19 | along with GCC; see the file COPYING. If not, write to the | |
20 | Free Software Foundation, 59 Temple Place - Suite 330, Boston, | |
21 | MA 02111-1307, USA. */ | |
9878760c | 22 | |
956d6950 | 23 | #include "config.h" |
c4d38ccb | 24 | #include "system.h" |
4977bab6 ZW |
25 | #include "coretypes.h" |
26 | #include "tm.h" | |
9878760c RK |
27 | #include "rtl.h" |
28 | #include "regs.h" | |
29 | #include "hard-reg-set.h" | |
30 | #include "real.h" | |
31 | #include "insn-config.h" | |
32 | #include "conditions.h" | |
9878760c RK |
33 | #include "insn-attr.h" |
34 | #include "flags.h" | |
35 | #include "recog.h" | |
9878760c | 36 | #include "obstack.h" |
9b30bae2 | 37 | #include "tree.h" |
dfafc897 | 38 | #include "expr.h" |
2fc1c679 | 39 | #include "optabs.h" |
2a430ec1 | 40 | #include "except.h" |
a7df97e6 | 41 | #include "function.h" |
296b8152 | 42 | #include "output.h" |
d5fa86ba | 43 | #include "basic-block.h" |
d0101753 | 44 | #include "integrate.h" |
296b8152 | 45 | #include "toplev.h" |
c8023011 | 46 | #include "ggc.h" |
9ebbca7d GK |
47 | #include "hashtab.h" |
48 | #include "tm_p.h" | |
672a6f42 NB |
49 | #include "target.h" |
50 | #include "target-def.h" | |
3ac88239 | 51 | #include "langhooks.h" |
24ea750e | 52 | #include "reload.h" |
117dca74 | 53 | #include "cfglayout.h" |
79ae11c4 | 54 | #include "sched-int.h" |
cd3ce9b4 | 55 | #include "tree-gimple.h" |
1bc7c5b6 ZW |
56 | #if TARGET_XCOFF |
57 | #include "xcoffout.h" /* get declarations of xcoff_*_section_name */ | |
58 | #endif | |
93a27b7b ZW |
59 | #if TARGET_MACHO |
60 | #include "gstab.h" /* for N_SLINE */ | |
61 | #endif | |
9b30bae2 | 62 | |
7509c759 MM |
63 | #ifndef TARGET_NO_PROTOTYPE |
64 | #define TARGET_NO_PROTOTYPE 0 | |
65 | #endif | |
66 | ||
9878760c RK |
67 | #define min(A,B) ((A) < (B) ? (A) : (B)) |
68 | #define max(A,B) ((A) > (B) ? (A) : (B)) | |
69 | ||
d1d0c603 JJ |
70 | /* Structure used to define the rs6000 stack */ |
71 | typedef struct rs6000_stack { | |
72 | int first_gp_reg_save; /* first callee saved GP register used */ | |
73 | int first_fp_reg_save; /* first callee saved FP register used */ | |
74 | int first_altivec_reg_save; /* first callee saved AltiVec register used */ | |
75 | int lr_save_p; /* true if the link reg needs to be saved */ | |
76 | int cr_save_p; /* true if the CR reg needs to be saved */ | |
77 | unsigned int vrsave_mask; /* mask of vec registers to save */ | |
78 | int toc_save_p; /* true if the TOC needs to be saved */ | |
79 | int push_p; /* true if we need to allocate stack space */ | |
80 | int calls_p; /* true if the function makes any calls */ | |
c4ad648e | 81 | int world_save_p; /* true if we're saving *everything*: |
d62294f5 | 82 | r13-r31, cr, f14-f31, vrsave, v20-v31 */ |
d1d0c603 JJ |
83 | enum rs6000_abi abi; /* which ABI to use */ |
84 | int gp_save_offset; /* offset to save GP regs from initial SP */ | |
85 | int fp_save_offset; /* offset to save FP regs from initial SP */ | |
86 | int altivec_save_offset; /* offset to save AltiVec regs from initial SP */ | |
87 | int lr_save_offset; /* offset to save LR from initial SP */ | |
88 | int cr_save_offset; /* offset to save CR from initial SP */ | |
89 | int vrsave_save_offset; /* offset to save VRSAVE from initial SP */ | |
90 | int spe_gp_save_offset; /* offset to save spe 64-bit gprs */ | |
91 | int toc_save_offset; /* offset to save the TOC pointer */ | |
92 | int varargs_save_offset; /* offset to save the varargs registers */ | |
93 | int ehrd_offset; /* offset to EH return data */ | |
94 | int reg_size; /* register size (4 or 8) */ | |
95 | int varargs_size; /* size to hold V.4 args passed in regs */ | |
96 | HOST_WIDE_INT vars_size; /* variable save area size */ | |
97 | int parm_size; /* outgoing parameter size */ | |
98 | int save_size; /* save area size */ | |
99 | int fixed_size; /* fixed size of stack frame */ | |
100 | int gp_size; /* size of saved GP registers */ | |
101 | int fp_size; /* size of saved FP registers */ | |
102 | int altivec_size; /* size of saved AltiVec registers */ | |
103 | int cr_size; /* size to hold CR if not in save_size */ | |
104 | int lr_size; /* size to hold LR if not in save_size */ | |
105 | int vrsave_size; /* size to hold VRSAVE if not in save_size */ | |
106 | int altivec_padding_size; /* size of altivec alignment padding if | |
107 | not in save_size */ | |
108 | int spe_gp_size; /* size of 64-bit GPR save size for SPE */ | |
109 | int spe_padding_size; | |
110 | int toc_size; /* size to hold TOC if not in save_size */ | |
111 | HOST_WIDE_INT total_size; /* total bytes allocated for stack */ | |
112 | int spe_64bit_regs_used; | |
113 | } rs6000_stack_t; | |
114 | ||
5248c961 RK |
115 | /* Target cpu type */ |
116 | ||
117 | enum processor_type rs6000_cpu; | |
8e3f41e7 MM |
118 | struct rs6000_cpu_select rs6000_select[3] = |
119 | { | |
815cdc52 MM |
120 | /* switch name, tune arch */ |
121 | { (const char *)0, "--with-cpu=", 1, 1 }, | |
122 | { (const char *)0, "-mcpu=", 1, 1 }, | |
123 | { (const char *)0, "-mtune=", 1, 0 }, | |
8e3f41e7 | 124 | }; |
5248c961 | 125 | |
ec507f2d DE |
126 | /* Always emit branch hint bits. */ |
127 | static GTY(()) bool rs6000_always_hint; | |
128 | ||
129 | /* Schedule instructions for group formation. */ | |
130 | static GTY(()) bool rs6000_sched_groups; | |
131 | ||
f676971a | 132 | /* Support adjust_priority scheduler hook |
79ae11c4 DN |
133 | and -mprioritize-restricted-insns= option. */ |
134 | const char *rs6000_sched_restricted_insns_priority_str; | |
135 | int rs6000_sched_restricted_insns_priority; | |
136 | ||
569fa502 DN |
137 | /* Support for -msched-costly-dep option. */ |
138 | const char *rs6000_sched_costly_dep_str; | |
139 | enum rs6000_dependence_cost rs6000_sched_costly_dep; | |
140 | ||
cbe26ab8 DN |
141 | /* Support for -minsert-sched-nops option. */ |
142 | const char *rs6000_sched_insert_nops_str; | |
143 | enum rs6000_nop_insertion rs6000_sched_insert_nops; | |
144 | ||
7ccf35ed | 145 | /* Support targetm.vectorize.builtin_mask_for_load. */ |
13c62176 | 146 | static GTY(()) tree altivec_builtin_mask_for_load; |
7ccf35ed | 147 | |
6fa3f289 ZW |
148 | /* Size of long double */ |
149 | const char *rs6000_long_double_size_string; | |
150 | int rs6000_long_double_type_size; | |
151 | ||
152 | /* Whether -mabi=altivec has appeared */ | |
153 | int rs6000_altivec_abi; | |
154 | ||
08b57fb3 AH |
155 | /* Whether VRSAVE instructions should be generated. */ |
156 | int rs6000_altivec_vrsave; | |
157 | ||
158 | /* String from -mvrsave= option. */ | |
159 | const char *rs6000_altivec_vrsave_string; | |
160 | ||
a3170dc6 AH |
161 | /* Nonzero if we want SPE ABI extensions. */ |
162 | int rs6000_spe_abi; | |
163 | ||
164 | /* Whether isel instructions should be generated. */ | |
165 | int rs6000_isel; | |
166 | ||
993f19a8 AH |
167 | /* Whether SPE simd instructions should be generated. */ |
168 | int rs6000_spe; | |
169 | ||
5da702b1 AH |
170 | /* Nonzero if floating point operations are done in the GPRs. */ |
171 | int rs6000_float_gprs = 0; | |
172 | ||
594a51fe SS |
173 | /* Nonzero if we want Darwin's struct-by-value-in-regs ABI. */ |
174 | int rs6000_darwin64_abi; | |
175 | ||
5da702b1 AH |
176 | /* String from -mfloat-gprs=. */ |
177 | const char *rs6000_float_gprs_string; | |
a3170dc6 AH |
178 | |
179 | /* String from -misel=. */ | |
180 | const char *rs6000_isel_string; | |
181 | ||
993f19a8 AH |
182 | /* String from -mspe=. */ |
183 | const char *rs6000_spe_string; | |
184 | ||
a0ab749a | 185 | /* Set to nonzero once AIX common-mode calls have been defined. */ |
bbfb86aa | 186 | static GTY(()) int common_mode_defined; |
c81bebd7 | 187 | |
9878760c RK |
188 | /* Save information from a "cmpxx" operation until the branch or scc is |
189 | emitted. */ | |
9878760c RK |
190 | rtx rs6000_compare_op0, rs6000_compare_op1; |
191 | int rs6000_compare_fp_p; | |
874a0744 | 192 | |
874a0744 MM |
193 | /* Label number of label created for -mrelocatable, to call to so we can |
194 | get the address of the GOT section */ | |
195 | int rs6000_pic_labelno; | |
c81bebd7 | 196 | |
b91da81f | 197 | #ifdef USING_ELFOS_H |
c81bebd7 | 198 | /* Which abi to adhere to */ |
9739c90c | 199 | const char *rs6000_abi_name; |
d9407988 MM |
200 | |
201 | /* Semantics of the small data area */ | |
202 | enum rs6000_sdata_type rs6000_sdata = SDATA_DATA; | |
203 | ||
204 | /* Which small data model to use */ | |
815cdc52 | 205 | const char *rs6000_sdata_name = (char *)0; |
9ebbca7d GK |
206 | |
207 | /* Counter for labels which are to be placed in .fixup. */ | |
208 | int fixuplabelno = 0; | |
874a0744 | 209 | #endif |
4697a36c | 210 | |
c4501e62 JJ |
211 | /* Bit size of immediate TLS offsets and string from which it is decoded. */ |
212 | int rs6000_tls_size = 32; | |
213 | const char *rs6000_tls_size_string; | |
214 | ||
b6c9286a MM |
215 | /* ABI enumeration available for subtarget to use. */ |
216 | enum rs6000_abi rs6000_current_abi; | |
217 | ||
0ac081f6 AH |
218 | /* ABI string from -mabi= option. */ |
219 | const char *rs6000_abi_string; | |
220 | ||
85b776df AM |
221 | /* Whether to use variant of AIX ABI for PowerPC64 Linux. */ |
222 | int dot_symbols; | |
223 | ||
38c1f2d7 | 224 | /* Debug flags */ |
815cdc52 | 225 | const char *rs6000_debug_name; |
38c1f2d7 MM |
226 | int rs6000_debug_stack; /* debug stack applications */ |
227 | int rs6000_debug_arg; /* debug argument handling */ | |
228 | ||
0d1fbc8c AH |
229 | /* Value is TRUE if register/mode pair is accepatable. */ |
230 | bool rs6000_hard_regno_mode_ok_p[NUM_MACHINE_MODES][FIRST_PSEUDO_REGISTER]; | |
231 | ||
6035d635 | 232 | /* Opaque types. */ |
2abe3e28 | 233 | static GTY(()) tree opaque_V2SI_type_node; |
2abe3e28 | 234 | static GTY(()) tree opaque_V2SF_type_node; |
6035d635 | 235 | static GTY(()) tree opaque_p_V2SI_type_node; |
4a5eab38 PB |
236 | static GTY(()) tree V16QI_type_node; |
237 | static GTY(()) tree V2SI_type_node; | |
238 | static GTY(()) tree V2SF_type_node; | |
239 | static GTY(()) tree V4HI_type_node; | |
240 | static GTY(()) tree V4SI_type_node; | |
241 | static GTY(()) tree V4SF_type_node; | |
242 | static GTY(()) tree V8HI_type_node; | |
243 | static GTY(()) tree unsigned_V16QI_type_node; | |
244 | static GTY(()) tree unsigned_V8HI_type_node; | |
245 | static GTY(()) tree unsigned_V4SI_type_node; | |
8bb418a3 ZL |
246 | static GTY(()) tree bool_char_type_node; /* __bool char */ |
247 | static GTY(()) tree bool_short_type_node; /* __bool short */ | |
248 | static GTY(()) tree bool_int_type_node; /* __bool int */ | |
249 | static GTY(()) tree pixel_type_node; /* __pixel */ | |
250 | static GTY(()) tree bool_V16QI_type_node; /* __vector __bool char */ | |
251 | static GTY(()) tree bool_V8HI_type_node; /* __vector __bool short */ | |
252 | static GTY(()) tree bool_V4SI_type_node; /* __vector __bool int */ | |
253 | static GTY(()) tree pixel_V8HI_type_node; /* __vector __pixel */ | |
254 | ||
255 | int rs6000_warn_altivec_long = 1; /* On by default. */ | |
256 | const char *rs6000_warn_altivec_long_switch; | |
257 | ||
57ac7be9 AM |
258 | const char *rs6000_traceback_name; |
259 | static enum { | |
260 | traceback_default = 0, | |
261 | traceback_none, | |
262 | traceback_part, | |
263 | traceback_full | |
264 | } rs6000_traceback; | |
265 | ||
38c1f2d7 MM |
266 | /* Flag to say the TOC is initialized */ |
267 | int toc_initialized; | |
9ebbca7d | 268 | char toc_label_name[10]; |
38c1f2d7 | 269 | |
9ebbca7d | 270 | /* Alias set for saves and restores from the rs6000 stack. */ |
f103e34d | 271 | static GTY(()) int rs6000_sr_alias_set; |
c8023011 | 272 | |
a5c76ee6 ZW |
273 | /* Call distance, overridden by -mlongcall and #pragma longcall(1). |
274 | The only place that looks at this is rs6000_set_default_type_attributes; | |
275 | everywhere else should rely on the presence or absence of a longcall | |
3eb4e360 AM |
276 | attribute on the function declaration. Exception: init_cumulative_args |
277 | looks at it too, for libcalls. */ | |
a5c76ee6 ZW |
278 | int rs6000_default_long_calls; |
279 | const char *rs6000_longcall_switch; | |
280 | ||
a3c9585f KH |
281 | /* Control alignment for fields within structures. */ |
282 | /* String from -malign-XXXXX. */ | |
025d9908 KH |
283 | const char *rs6000_alignment_string; |
284 | int rs6000_alignment_flags; | |
285 | ||
a3170dc6 AH |
286 | struct builtin_description |
287 | { | |
288 | /* mask is not const because we're going to alter it below. This | |
289 | nonsense will go away when we rewrite the -march infrastructure | |
290 | to give us more target flag bits. */ | |
291 | unsigned int mask; | |
292 | const enum insn_code icode; | |
293 | const char *const name; | |
294 | const enum rs6000_builtins code; | |
295 | }; | |
8b897cfa RS |
296 | \f |
297 | /* Target cpu costs. */ | |
298 | ||
299 | struct processor_costs { | |
c4ad648e | 300 | const int mulsi; /* cost of SImode multiplication. */ |
8b897cfa RS |
301 | const int mulsi_const; /* cost of SImode multiplication by constant. */ |
302 | const int mulsi_const9; /* cost of SImode mult by short constant. */ | |
c4ad648e AM |
303 | const int muldi; /* cost of DImode multiplication. */ |
304 | const int divsi; /* cost of SImode division. */ | |
305 | const int divdi; /* cost of DImode division. */ | |
306 | const int fp; /* cost of simple SFmode and DFmode insns. */ | |
307 | const int dmul; /* cost of DFmode multiplication (and fmadd). */ | |
308 | const int sdiv; /* cost of SFmode division (fdivs). */ | |
309 | const int ddiv; /* cost of DFmode division (fdiv). */ | |
8b897cfa RS |
310 | }; |
311 | ||
312 | const struct processor_costs *rs6000_cost; | |
313 | ||
314 | /* Processor costs (relative to an add) */ | |
315 | ||
316 | /* Instruction size costs on 32bit processors. */ | |
317 | static const | |
318 | struct processor_costs size32_cost = { | |
06a67bdd RS |
319 | COSTS_N_INSNS (1), /* mulsi */ |
320 | COSTS_N_INSNS (1), /* mulsi_const */ | |
321 | COSTS_N_INSNS (1), /* mulsi_const9 */ | |
322 | COSTS_N_INSNS (1), /* muldi */ | |
323 | COSTS_N_INSNS (1), /* divsi */ | |
324 | COSTS_N_INSNS (1), /* divdi */ | |
325 | COSTS_N_INSNS (1), /* fp */ | |
326 | COSTS_N_INSNS (1), /* dmul */ | |
327 | COSTS_N_INSNS (1), /* sdiv */ | |
328 | COSTS_N_INSNS (1), /* ddiv */ | |
8b897cfa RS |
329 | }; |
330 | ||
331 | /* Instruction size costs on 64bit processors. */ | |
332 | static const | |
333 | struct processor_costs size64_cost = { | |
06a67bdd RS |
334 | COSTS_N_INSNS (1), /* mulsi */ |
335 | COSTS_N_INSNS (1), /* mulsi_const */ | |
336 | COSTS_N_INSNS (1), /* mulsi_const9 */ | |
337 | COSTS_N_INSNS (1), /* muldi */ | |
338 | COSTS_N_INSNS (1), /* divsi */ | |
339 | COSTS_N_INSNS (1), /* divdi */ | |
340 | COSTS_N_INSNS (1), /* fp */ | |
341 | COSTS_N_INSNS (1), /* dmul */ | |
342 | COSTS_N_INSNS (1), /* sdiv */ | |
343 | COSTS_N_INSNS (1), /* ddiv */ | |
8b897cfa RS |
344 | }; |
345 | ||
346 | /* Instruction costs on RIOS1 processors. */ | |
347 | static const | |
348 | struct processor_costs rios1_cost = { | |
06a67bdd RS |
349 | COSTS_N_INSNS (5), /* mulsi */ |
350 | COSTS_N_INSNS (4), /* mulsi_const */ | |
351 | COSTS_N_INSNS (3), /* mulsi_const9 */ | |
352 | COSTS_N_INSNS (5), /* muldi */ | |
353 | COSTS_N_INSNS (19), /* divsi */ | |
354 | COSTS_N_INSNS (19), /* divdi */ | |
355 | COSTS_N_INSNS (2), /* fp */ | |
356 | COSTS_N_INSNS (2), /* dmul */ | |
357 | COSTS_N_INSNS (19), /* sdiv */ | |
358 | COSTS_N_INSNS (19), /* ddiv */ | |
8b897cfa RS |
359 | }; |
360 | ||
361 | /* Instruction costs on RIOS2 processors. */ | |
362 | static const | |
363 | struct processor_costs rios2_cost = { | |
06a67bdd RS |
364 | COSTS_N_INSNS (2), /* mulsi */ |
365 | COSTS_N_INSNS (2), /* mulsi_const */ | |
366 | COSTS_N_INSNS (2), /* mulsi_const9 */ | |
367 | COSTS_N_INSNS (2), /* muldi */ | |
368 | COSTS_N_INSNS (13), /* divsi */ | |
369 | COSTS_N_INSNS (13), /* divdi */ | |
370 | COSTS_N_INSNS (2), /* fp */ | |
371 | COSTS_N_INSNS (2), /* dmul */ | |
372 | COSTS_N_INSNS (17), /* sdiv */ | |
373 | COSTS_N_INSNS (17), /* ddiv */ | |
8b897cfa RS |
374 | }; |
375 | ||
376 | /* Instruction costs on RS64A processors. */ | |
377 | static const | |
378 | struct processor_costs rs64a_cost = { | |
06a67bdd RS |
379 | COSTS_N_INSNS (20), /* mulsi */ |
380 | COSTS_N_INSNS (12), /* mulsi_const */ | |
381 | COSTS_N_INSNS (8), /* mulsi_const9 */ | |
382 | COSTS_N_INSNS (34), /* muldi */ | |
383 | COSTS_N_INSNS (65), /* divsi */ | |
384 | COSTS_N_INSNS (67), /* divdi */ | |
385 | COSTS_N_INSNS (4), /* fp */ | |
386 | COSTS_N_INSNS (4), /* dmul */ | |
387 | COSTS_N_INSNS (31), /* sdiv */ | |
388 | COSTS_N_INSNS (31), /* ddiv */ | |
8b897cfa RS |
389 | }; |
390 | ||
391 | /* Instruction costs on MPCCORE processors. */ | |
392 | static const | |
393 | struct processor_costs mpccore_cost = { | |
06a67bdd RS |
394 | COSTS_N_INSNS (2), /* mulsi */ |
395 | COSTS_N_INSNS (2), /* mulsi_const */ | |
396 | COSTS_N_INSNS (2), /* mulsi_const9 */ | |
397 | COSTS_N_INSNS (2), /* muldi */ | |
398 | COSTS_N_INSNS (6), /* divsi */ | |
399 | COSTS_N_INSNS (6), /* divdi */ | |
400 | COSTS_N_INSNS (4), /* fp */ | |
401 | COSTS_N_INSNS (5), /* dmul */ | |
402 | COSTS_N_INSNS (10), /* sdiv */ | |
403 | COSTS_N_INSNS (17), /* ddiv */ | |
8b897cfa RS |
404 | }; |
405 | ||
406 | /* Instruction costs on PPC403 processors. */ | |
407 | static const | |
408 | struct processor_costs ppc403_cost = { | |
06a67bdd RS |
409 | COSTS_N_INSNS (4), /* mulsi */ |
410 | COSTS_N_INSNS (4), /* mulsi_const */ | |
411 | COSTS_N_INSNS (4), /* mulsi_const9 */ | |
412 | COSTS_N_INSNS (4), /* muldi */ | |
413 | COSTS_N_INSNS (33), /* divsi */ | |
414 | COSTS_N_INSNS (33), /* divdi */ | |
415 | COSTS_N_INSNS (11), /* fp */ | |
416 | COSTS_N_INSNS (11), /* dmul */ | |
417 | COSTS_N_INSNS (11), /* sdiv */ | |
418 | COSTS_N_INSNS (11), /* ddiv */ | |
8b897cfa RS |
419 | }; |
420 | ||
421 | /* Instruction costs on PPC405 processors. */ | |
422 | static const | |
423 | struct processor_costs ppc405_cost = { | |
06a67bdd RS |
424 | COSTS_N_INSNS (5), /* mulsi */ |
425 | COSTS_N_INSNS (4), /* mulsi_const */ | |
426 | COSTS_N_INSNS (3), /* mulsi_const9 */ | |
427 | COSTS_N_INSNS (5), /* muldi */ | |
428 | COSTS_N_INSNS (35), /* divsi */ | |
429 | COSTS_N_INSNS (35), /* divdi */ | |
430 | COSTS_N_INSNS (11), /* fp */ | |
431 | COSTS_N_INSNS (11), /* dmul */ | |
432 | COSTS_N_INSNS (11), /* sdiv */ | |
433 | COSTS_N_INSNS (11), /* ddiv */ | |
8b897cfa RS |
434 | }; |
435 | ||
436 | /* Instruction costs on PPC440 processors. */ | |
437 | static const | |
438 | struct processor_costs ppc440_cost = { | |
06a67bdd RS |
439 | COSTS_N_INSNS (3), /* mulsi */ |
440 | COSTS_N_INSNS (2), /* mulsi_const */ | |
441 | COSTS_N_INSNS (2), /* mulsi_const9 */ | |
442 | COSTS_N_INSNS (3), /* muldi */ | |
443 | COSTS_N_INSNS (34), /* divsi */ | |
444 | COSTS_N_INSNS (34), /* divdi */ | |
445 | COSTS_N_INSNS (5), /* fp */ | |
446 | COSTS_N_INSNS (5), /* dmul */ | |
447 | COSTS_N_INSNS (19), /* sdiv */ | |
448 | COSTS_N_INSNS (33), /* ddiv */ | |
8b897cfa RS |
449 | }; |
450 | ||
451 | /* Instruction costs on PPC601 processors. */ | |
452 | static const | |
453 | struct processor_costs ppc601_cost = { | |
06a67bdd RS |
454 | COSTS_N_INSNS (5), /* mulsi */ |
455 | COSTS_N_INSNS (5), /* mulsi_const */ | |
456 | COSTS_N_INSNS (5), /* mulsi_const9 */ | |
457 | COSTS_N_INSNS (5), /* muldi */ | |
458 | COSTS_N_INSNS (36), /* divsi */ | |
459 | COSTS_N_INSNS (36), /* divdi */ | |
460 | COSTS_N_INSNS (4), /* fp */ | |
461 | COSTS_N_INSNS (5), /* dmul */ | |
462 | COSTS_N_INSNS (17), /* sdiv */ | |
463 | COSTS_N_INSNS (31), /* ddiv */ | |
8b897cfa RS |
464 | }; |
465 | ||
466 | /* Instruction costs on PPC603 processors. */ | |
467 | static const | |
468 | struct processor_costs ppc603_cost = { | |
06a67bdd RS |
469 | COSTS_N_INSNS (5), /* mulsi */ |
470 | COSTS_N_INSNS (3), /* mulsi_const */ | |
471 | COSTS_N_INSNS (2), /* mulsi_const9 */ | |
472 | COSTS_N_INSNS (5), /* muldi */ | |
473 | COSTS_N_INSNS (37), /* divsi */ | |
474 | COSTS_N_INSNS (37), /* divdi */ | |
475 | COSTS_N_INSNS (3), /* fp */ | |
476 | COSTS_N_INSNS (4), /* dmul */ | |
477 | COSTS_N_INSNS (18), /* sdiv */ | |
478 | COSTS_N_INSNS (33), /* ddiv */ | |
8b897cfa RS |
479 | }; |
480 | ||
481 | /* Instruction costs on PPC604 processors. */ | |
482 | static const | |
483 | struct processor_costs ppc604_cost = { | |
06a67bdd RS |
484 | COSTS_N_INSNS (4), /* mulsi */ |
485 | COSTS_N_INSNS (4), /* mulsi_const */ | |
486 | COSTS_N_INSNS (4), /* mulsi_const9 */ | |
487 | COSTS_N_INSNS (4), /* muldi */ | |
488 | COSTS_N_INSNS (20), /* divsi */ | |
489 | COSTS_N_INSNS (20), /* divdi */ | |
490 | COSTS_N_INSNS (3), /* fp */ | |
491 | COSTS_N_INSNS (3), /* dmul */ | |
492 | COSTS_N_INSNS (18), /* sdiv */ | |
493 | COSTS_N_INSNS (32), /* ddiv */ | |
8b897cfa RS |
494 | }; |
495 | ||
496 | /* Instruction costs on PPC604e processors. */ | |
497 | static const | |
498 | struct processor_costs ppc604e_cost = { | |
06a67bdd RS |
499 | COSTS_N_INSNS (2), /* mulsi */ |
500 | COSTS_N_INSNS (2), /* mulsi_const */ | |
501 | COSTS_N_INSNS (2), /* mulsi_const9 */ | |
502 | COSTS_N_INSNS (2), /* muldi */ | |
503 | COSTS_N_INSNS (20), /* divsi */ | |
504 | COSTS_N_INSNS (20), /* divdi */ | |
505 | COSTS_N_INSNS (3), /* fp */ | |
506 | COSTS_N_INSNS (3), /* dmul */ | |
507 | COSTS_N_INSNS (18), /* sdiv */ | |
508 | COSTS_N_INSNS (32), /* ddiv */ | |
8b897cfa RS |
509 | }; |
510 | ||
f0517163 | 511 | /* Instruction costs on PPC620 processors. */ |
8b897cfa RS |
512 | static const |
513 | struct processor_costs ppc620_cost = { | |
06a67bdd RS |
514 | COSTS_N_INSNS (5), /* mulsi */ |
515 | COSTS_N_INSNS (4), /* mulsi_const */ | |
516 | COSTS_N_INSNS (3), /* mulsi_const9 */ | |
517 | COSTS_N_INSNS (7), /* muldi */ | |
518 | COSTS_N_INSNS (21), /* divsi */ | |
519 | COSTS_N_INSNS (37), /* divdi */ | |
520 | COSTS_N_INSNS (3), /* fp */ | |
521 | COSTS_N_INSNS (3), /* dmul */ | |
522 | COSTS_N_INSNS (18), /* sdiv */ | |
523 | COSTS_N_INSNS (32), /* ddiv */ | |
f0517163 RS |
524 | }; |
525 | ||
526 | /* Instruction costs on PPC630 processors. */ | |
527 | static const | |
528 | struct processor_costs ppc630_cost = { | |
06a67bdd RS |
529 | COSTS_N_INSNS (5), /* mulsi */ |
530 | COSTS_N_INSNS (4), /* mulsi_const */ | |
531 | COSTS_N_INSNS (3), /* mulsi_const9 */ | |
532 | COSTS_N_INSNS (7), /* muldi */ | |
533 | COSTS_N_INSNS (21), /* divsi */ | |
534 | COSTS_N_INSNS (37), /* divdi */ | |
535 | COSTS_N_INSNS (3), /* fp */ | |
536 | COSTS_N_INSNS (3), /* dmul */ | |
537 | COSTS_N_INSNS (17), /* sdiv */ | |
538 | COSTS_N_INSNS (21), /* ddiv */ | |
8b897cfa RS |
539 | }; |
540 | ||
541 | /* Instruction costs on PPC750 and PPC7400 processors. */ | |
542 | static const | |
543 | struct processor_costs ppc750_cost = { | |
06a67bdd RS |
544 | COSTS_N_INSNS (5), /* mulsi */ |
545 | COSTS_N_INSNS (3), /* mulsi_const */ | |
546 | COSTS_N_INSNS (2), /* mulsi_const9 */ | |
547 | COSTS_N_INSNS (5), /* muldi */ | |
548 | COSTS_N_INSNS (17), /* divsi */ | |
549 | COSTS_N_INSNS (17), /* divdi */ | |
550 | COSTS_N_INSNS (3), /* fp */ | |
551 | COSTS_N_INSNS (3), /* dmul */ | |
552 | COSTS_N_INSNS (17), /* sdiv */ | |
553 | COSTS_N_INSNS (31), /* ddiv */ | |
8b897cfa RS |
554 | }; |
555 | ||
556 | /* Instruction costs on PPC7450 processors. */ | |
557 | static const | |
558 | struct processor_costs ppc7450_cost = { | |
06a67bdd RS |
559 | COSTS_N_INSNS (4), /* mulsi */ |
560 | COSTS_N_INSNS (3), /* mulsi_const */ | |
561 | COSTS_N_INSNS (3), /* mulsi_const9 */ | |
562 | COSTS_N_INSNS (4), /* muldi */ | |
563 | COSTS_N_INSNS (23), /* divsi */ | |
564 | COSTS_N_INSNS (23), /* divdi */ | |
565 | COSTS_N_INSNS (5), /* fp */ | |
566 | COSTS_N_INSNS (5), /* dmul */ | |
567 | COSTS_N_INSNS (21), /* sdiv */ | |
568 | COSTS_N_INSNS (35), /* ddiv */ | |
8b897cfa | 569 | }; |
a3170dc6 | 570 | |
8b897cfa RS |
571 | /* Instruction costs on PPC8540 processors. */ |
572 | static const | |
573 | struct processor_costs ppc8540_cost = { | |
06a67bdd RS |
574 | COSTS_N_INSNS (4), /* mulsi */ |
575 | COSTS_N_INSNS (4), /* mulsi_const */ | |
576 | COSTS_N_INSNS (4), /* mulsi_const9 */ | |
577 | COSTS_N_INSNS (4), /* muldi */ | |
578 | COSTS_N_INSNS (19), /* divsi */ | |
579 | COSTS_N_INSNS (19), /* divdi */ | |
580 | COSTS_N_INSNS (4), /* fp */ | |
581 | COSTS_N_INSNS (4), /* dmul */ | |
582 | COSTS_N_INSNS (29), /* sdiv */ | |
583 | COSTS_N_INSNS (29), /* ddiv */ | |
8b897cfa RS |
584 | }; |
585 | ||
586 | /* Instruction costs on POWER4 and POWER5 processors. */ | |
587 | static const | |
588 | struct processor_costs power4_cost = { | |
06a67bdd RS |
589 | COSTS_N_INSNS (3), /* mulsi */ |
590 | COSTS_N_INSNS (2), /* mulsi_const */ | |
591 | COSTS_N_INSNS (2), /* mulsi_const9 */ | |
592 | COSTS_N_INSNS (4), /* muldi */ | |
593 | COSTS_N_INSNS (18), /* divsi */ | |
594 | COSTS_N_INSNS (34), /* divdi */ | |
595 | COSTS_N_INSNS (3), /* fp */ | |
596 | COSTS_N_INSNS (3), /* dmul */ | |
597 | COSTS_N_INSNS (17), /* sdiv */ | |
598 | COSTS_N_INSNS (17), /* ddiv */ | |
8b897cfa RS |
599 | }; |
600 | ||
601 | \f | |
a2369ed3 | 602 | static bool rs6000_function_ok_for_sibcall (tree, tree); |
a2369ed3 DJ |
603 | static rtx rs6000_generate_compare (enum rtx_code); |
604 | static void rs6000_maybe_dead (rtx); | |
605 | static void rs6000_emit_stack_tie (void); | |
606 | static void rs6000_frame_related (rtx, rtx, HOST_WIDE_INT, rtx, rtx); | |
607 | static rtx spe_synthesize_frame_save (rtx); | |
608 | static bool spe_func_has_64bit_regs_p (void); | |
b20a9cca | 609 | static void emit_frame_save (rtx, rtx, enum machine_mode, unsigned int, |
d1d0c603 | 610 | int, HOST_WIDE_INT); |
a2369ed3 DJ |
611 | static rtx gen_frame_mem_offset (enum machine_mode, rtx, int); |
612 | static void rs6000_emit_allocate_stack (HOST_WIDE_INT, int); | |
613 | static unsigned rs6000_hash_constant (rtx); | |
614 | static unsigned toc_hash_function (const void *); | |
615 | static int toc_hash_eq (const void *, const void *); | |
616 | static int constant_pool_expr_1 (rtx, int *, int *); | |
617 | static bool constant_pool_expr_p (rtx); | |
a2369ed3 | 618 | static bool legitimate_small_data_p (enum machine_mode, rtx); |
a2369ed3 | 619 | static bool legitimate_indexed_address_p (rtx, int); |
a2369ed3 DJ |
620 | static bool legitimate_lo_sum_address_p (enum machine_mode, rtx, int); |
621 | static struct machine_function * rs6000_init_machine_status (void); | |
622 | static bool rs6000_assemble_integer (rtx, unsigned int, int); | |
5add3202 | 623 | #ifdef HAVE_GAS_HIDDEN |
a2369ed3 | 624 | static void rs6000_assemble_visibility (tree, int); |
5add3202 | 625 | #endif |
a2369ed3 DJ |
626 | static int rs6000_ra_ever_killed (void); |
627 | static tree rs6000_handle_longcall_attribute (tree *, tree, tree, int, bool *); | |
8bb418a3 | 628 | static tree rs6000_handle_altivec_attribute (tree *, tree, tree, int, bool *); |
76d2b81d | 629 | static void rs6000_eliminate_indexed_memrefs (rtx operands[2]); |
f18eca82 | 630 | static const char *rs6000_mangle_fundamental_type (tree); |
b86fe7b4 | 631 | extern const struct attribute_spec rs6000_attribute_table[]; |
a2369ed3 DJ |
632 | static void rs6000_set_default_type_attributes (tree); |
633 | static void rs6000_output_function_prologue (FILE *, HOST_WIDE_INT); | |
634 | static void rs6000_output_function_epilogue (FILE *, HOST_WIDE_INT); | |
b20a9cca AM |
635 | static void rs6000_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT, |
636 | tree); | |
a2369ed3 | 637 | static rtx rs6000_emit_set_long_const (rtx, HOST_WIDE_INT, HOST_WIDE_INT); |
c6e8c921 | 638 | static bool rs6000_return_in_memory (tree, tree); |
a2369ed3 | 639 | static void rs6000_file_start (void); |
7c262518 | 640 | #if TARGET_ELF |
a2369ed3 DJ |
641 | static unsigned int rs6000_elf_section_type_flags (tree, const char *, int); |
642 | static void rs6000_elf_asm_out_constructor (rtx, int); | |
643 | static void rs6000_elf_asm_out_destructor (rtx, int); | |
644 | static void rs6000_elf_select_section (tree, int, unsigned HOST_WIDE_INT); | |
645 | static void rs6000_elf_unique_section (tree, int); | |
646 | static void rs6000_elf_select_rtx_section (enum machine_mode, rtx, | |
b20a9cca | 647 | unsigned HOST_WIDE_INT); |
a56d7372 | 648 | static void rs6000_elf_encode_section_info (tree, rtx, int) |
0e5dbd9b | 649 | ATTRIBUTE_UNUSED; |
a2369ed3 | 650 | static bool rs6000_elf_in_small_data_p (tree); |
7c262518 | 651 | #endif |
cbaaba19 | 652 | #if TARGET_XCOFF |
a2369ed3 | 653 | static void rs6000_xcoff_asm_globalize_label (FILE *, const char *); |
8210e4c4 | 654 | static void rs6000_xcoff_asm_named_section (const char *, unsigned int, tree); |
a2369ed3 DJ |
655 | static void rs6000_xcoff_select_section (tree, int, unsigned HOST_WIDE_INT); |
656 | static void rs6000_xcoff_unique_section (tree, int); | |
657 | static void rs6000_xcoff_select_rtx_section (enum machine_mode, rtx, | |
b20a9cca | 658 | unsigned HOST_WIDE_INT); |
a2369ed3 DJ |
659 | static const char * rs6000_xcoff_strip_name_encoding (const char *); |
660 | static unsigned int rs6000_xcoff_section_type_flags (tree, const char *, int); | |
661 | static void rs6000_xcoff_file_start (void); | |
662 | static void rs6000_xcoff_file_end (void); | |
f1384257 AM |
663 | #endif |
664 | #if TARGET_MACHO | |
a2369ed3 | 665 | static bool rs6000_binds_local_p (tree); |
f1384257 | 666 | #endif |
a2369ed3 DJ |
667 | static int rs6000_variable_issue (FILE *, int, rtx, int); |
668 | static bool rs6000_rtx_costs (rtx, int, int, int *); | |
669 | static int rs6000_adjust_cost (rtx, rtx, rtx, int); | |
cbe26ab8 | 670 | static bool is_microcoded_insn (rtx); |
79ae11c4 | 671 | static int is_dispatch_slot_restricted (rtx); |
cbe26ab8 DN |
672 | static bool is_cracked_insn (rtx); |
673 | static bool is_branch_slot_insn (rtx); | |
a2369ed3 DJ |
674 | static int rs6000_adjust_priority (rtx, int); |
675 | static int rs6000_issue_rate (void); | |
569fa502 | 676 | static bool rs6000_is_costly_dependence (rtx, rtx, rtx, int, int); |
cbe26ab8 DN |
677 | static rtx get_next_active_insn (rtx, rtx); |
678 | static bool insn_terminates_group_p (rtx , enum group_termination); | |
679 | static bool is_costly_group (rtx *, rtx); | |
680 | static int force_new_group (int, FILE *, rtx *, rtx, bool *, int, int *); | |
681 | static int redefine_groups (FILE *, int, rtx, rtx); | |
682 | static int pad_groups (FILE *, int, rtx, rtx); | |
683 | static void rs6000_sched_finish (FILE *, int); | |
a2369ed3 | 684 | static int rs6000_use_sched_lookahead (void); |
7ccf35ed | 685 | static tree rs6000_builtin_mask_for_load (void); |
a2369ed3 DJ |
686 | |
687 | static void rs6000_init_builtins (void); | |
688 | static rtx rs6000_expand_unop_builtin (enum insn_code, tree, rtx); | |
689 | static rtx rs6000_expand_binop_builtin (enum insn_code, tree, rtx); | |
690 | static rtx rs6000_expand_ternop_builtin (enum insn_code, tree, rtx); | |
691 | static rtx rs6000_expand_builtin (tree, rtx, rtx, enum machine_mode, int); | |
692 | static void altivec_init_builtins (void); | |
693 | static void rs6000_common_init_builtins (void); | |
c15c90bb | 694 | static void rs6000_init_libfuncs (void); |
a2369ed3 | 695 | |
b20a9cca AM |
696 | static void enable_mask_for_builtins (struct builtin_description *, int, |
697 | enum rs6000_builtins, | |
698 | enum rs6000_builtins); | |
7c62e993 | 699 | static tree build_opaque_vector_type (tree, int); |
a2369ed3 DJ |
700 | static void spe_init_builtins (void); |
701 | static rtx spe_expand_builtin (tree, rtx, bool *); | |
61bea3b0 | 702 | static rtx spe_expand_stv_builtin (enum insn_code, tree); |
a2369ed3 DJ |
703 | static rtx spe_expand_predicate_builtin (enum insn_code, tree, rtx); |
704 | static rtx spe_expand_evsel_builtin (enum insn_code, tree, rtx); | |
705 | static int rs6000_emit_int_cmove (rtx, rtx, rtx, rtx); | |
d1d0c603 JJ |
706 | static rs6000_stack_t *rs6000_stack_info (void); |
707 | static void debug_stack_info (rs6000_stack_t *); | |
a2369ed3 DJ |
708 | |
709 | static rtx altivec_expand_builtin (tree, rtx, bool *); | |
710 | static rtx altivec_expand_ld_builtin (tree, rtx, bool *); | |
711 | static rtx altivec_expand_st_builtin (tree, rtx, bool *); | |
712 | static rtx altivec_expand_dst_builtin (tree, rtx, bool *); | |
713 | static rtx altivec_expand_abs_builtin (enum insn_code, tree, rtx); | |
f676971a | 714 | static rtx altivec_expand_predicate_builtin (enum insn_code, |
c4ad648e | 715 | const char *, tree, rtx); |
b4a62fa0 | 716 | static rtx altivec_expand_lv_builtin (enum insn_code, tree, rtx); |
a2369ed3 DJ |
717 | static rtx altivec_expand_stv_builtin (enum insn_code, tree); |
718 | static void rs6000_parse_abi_options (void); | |
719 | static void rs6000_parse_alignment_option (void); | |
720 | static void rs6000_parse_tls_size_option (void); | |
5da702b1 | 721 | static void rs6000_parse_yes_no_option (const char *, const char *, int *); |
4d4cbc0e | 722 | static void rs6000_parse_float_gprs_option (void); |
a2369ed3 DJ |
723 | static int first_altivec_reg_to_save (void); |
724 | static unsigned int compute_vrsave_mask (void); | |
d62294f5 | 725 | static void compute_save_world_info(rs6000_stack_t *info_ptr); |
a2369ed3 DJ |
726 | static void is_altivec_return_reg (rtx, void *); |
727 | static rtx generate_set_vrsave (rtx, rs6000_stack_t *, int); | |
728 | int easy_vector_constant (rtx, enum machine_mode); | |
a2369ed3 DJ |
729 | static bool is_ev64_opaque_type (tree); |
730 | static rtx rs6000_dwarf_register_span (rtx); | |
731 | static rtx rs6000_legitimize_tls_address (rtx, enum tls_model); | |
732 | static rtx rs6000_tls_get_addr (void); | |
733 | static rtx rs6000_got_sym (void); | |
734 | static inline int rs6000_tls_symbol_ref_1 (rtx *, void *); | |
735 | static const char *rs6000_get_some_local_dynamic_name (void); | |
736 | static int rs6000_get_some_local_dynamic_name_1 (rtx *, void *); | |
ded9bf77 | 737 | static rtx rs6000_complex_function_value (enum machine_mode); |
b20a9cca | 738 | static rtx rs6000_spe_function_arg (CUMULATIVE_ARGS *, |
a2369ed3 | 739 | enum machine_mode, tree); |
0b5383eb DJ |
740 | static void rs6000_darwin64_record_arg_advance_flush (CUMULATIVE_ARGS *, |
741 | HOST_WIDE_INT); | |
742 | static void rs6000_darwin64_record_arg_advance_recurse (CUMULATIVE_ARGS *, | |
743 | tree, HOST_WIDE_INT); | |
744 | static void rs6000_darwin64_record_arg_flush (CUMULATIVE_ARGS *, | |
745 | HOST_WIDE_INT, | |
746 | rtx[], int *); | |
747 | static void rs6000_darwin64_record_arg_recurse (CUMULATIVE_ARGS *, | |
748 | tree, HOST_WIDE_INT, | |
749 | rtx[], int *); | |
750 | static rtx rs6000_darwin64_record_arg (CUMULATIVE_ARGS *, tree, int, bool); | |
ec6376ab | 751 | static rtx rs6000_mixed_function_arg (enum machine_mode, tree, int); |
b1917422 | 752 | static void rs6000_move_block_from_reg (int regno, rtx x, int nregs); |
c6e8c921 GK |
753 | static void setup_incoming_varargs (CUMULATIVE_ARGS *, |
754 | enum machine_mode, tree, | |
755 | int *, int); | |
8cd5a4e0 RH |
756 | static bool rs6000_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode, |
757 | tree, bool); | |
78a52f11 RH |
758 | static int rs6000_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode, |
759 | tree, bool); | |
efdba735 SH |
760 | #if TARGET_MACHO |
761 | static void macho_branch_islands (void); | |
762 | static void add_compiler_branch_island (tree, tree, int); | |
763 | static int no_previous_def (tree function_name); | |
764 | static tree get_prev_label (tree function_name); | |
c4e18b1c | 765 | static void rs6000_darwin_file_start (void); |
efdba735 SH |
766 | #endif |
767 | ||
c35d187f | 768 | static tree rs6000_build_builtin_va_list (void); |
23a60a04 | 769 | static tree rs6000_gimplify_va_arg (tree, tree, tree *, tree *); |
fe984136 | 770 | static bool rs6000_must_pass_in_stack (enum machine_mode, tree); |
f676971a | 771 | static bool rs6000_vector_mode_supported_p (enum machine_mode); |
94ff898d | 772 | static int get_vec_cmp_insn (enum rtx_code, enum machine_mode, |
21213b4c | 773 | enum machine_mode); |
94ff898d | 774 | static rtx rs6000_emit_vector_compare (enum rtx_code, rtx, rtx, |
21213b4c DP |
775 | enum machine_mode); |
776 | static int get_vsel_insn (enum machine_mode); | |
777 | static void rs6000_emit_vector_select (rtx, rtx, rtx, rtx); | |
17211ab5 | 778 | |
21213b4c DP |
779 | |
780 | const int INSN_NOT_AVAILABLE = -1; | |
93f90be6 FJ |
781 | static enum machine_mode rs6000_eh_return_filter_mode (void); |
782 | ||
17211ab5 GK |
783 | /* Hash table stuff for keeping track of TOC entries. */ |
784 | ||
785 | struct toc_hash_struct GTY(()) | |
786 | { | |
787 | /* `key' will satisfy CONSTANT_P; in fact, it will satisfy | |
788 | ASM_OUTPUT_SPECIAL_POOL_ENTRY_P. */ | |
789 | rtx key; | |
790 | enum machine_mode key_mode; | |
791 | int labelno; | |
792 | }; | |
793 | ||
794 | static GTY ((param_is (struct toc_hash_struct))) htab_t toc_hash_table; | |
c81bebd7 MM |
795 | \f |
796 | /* Default register names. */ | |
797 | char rs6000_reg_names[][8] = | |
798 | { | |
802a0058 MM |
799 | "0", "1", "2", "3", "4", "5", "6", "7", |
800 | "8", "9", "10", "11", "12", "13", "14", "15", | |
801 | "16", "17", "18", "19", "20", "21", "22", "23", | |
802 | "24", "25", "26", "27", "28", "29", "30", "31", | |
803 | "0", "1", "2", "3", "4", "5", "6", "7", | |
804 | "8", "9", "10", "11", "12", "13", "14", "15", | |
805 | "16", "17", "18", "19", "20", "21", "22", "23", | |
806 | "24", "25", "26", "27", "28", "29", "30", "31", | |
807 | "mq", "lr", "ctr","ap", | |
808 | "0", "1", "2", "3", "4", "5", "6", "7", | |
0ac081f6 AH |
809 | "xer", |
810 | /* AltiVec registers. */ | |
0cd5e3a1 AH |
811 | "0", "1", "2", "3", "4", "5", "6", "7", |
812 | "8", "9", "10", "11", "12", "13", "14", "15", | |
813 | "16", "17", "18", "19", "20", "21", "22", "23", | |
814 | "24", "25", "26", "27", "28", "29", "30", "31", | |
59a4c851 AH |
815 | "vrsave", "vscr", |
816 | /* SPE registers. */ | |
817 | "spe_acc", "spefscr" | |
c81bebd7 MM |
818 | }; |
819 | ||
820 | #ifdef TARGET_REGNAMES | |
8b60264b | 821 | static const char alt_reg_names[][8] = |
c81bebd7 | 822 | { |
802a0058 MM |
823 | "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7", |
824 | "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15", | |
825 | "%r16", "%r17", "%r18", "%r19", "%r20", "%r21", "%r22", "%r23", | |
826 | "%r24", "%r25", "%r26", "%r27", "%r28", "%r29", "%r30", "%r31", | |
827 | "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7", | |
828 | "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15", | |
829 | "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23", | |
830 | "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31", | |
831 | "mq", "lr", "ctr", "ap", | |
832 | "%cr0", "%cr1", "%cr2", "%cr3", "%cr4", "%cr5", "%cr6", "%cr7", | |
0ac081f6 | 833 | "xer", |
59a4c851 | 834 | /* AltiVec registers. */ |
0ac081f6 | 835 | "%v0", "%v1", "%v2", "%v3", "%v4", "%v5", "%v6", "%v7", |
59a4c851 AH |
836 | "%v8", "%v9", "%v10", "%v11", "%v12", "%v13", "%v14", "%v15", |
837 | "%v16", "%v17", "%v18", "%v19", "%v20", "%v21", "%v22", "%v23", | |
838 | "%v24", "%v25", "%v26", "%v27", "%v28", "%v29", "%v30", "%v31", | |
839 | "vrsave", "vscr", | |
840 | /* SPE registers. */ | |
841 | "spe_acc", "spefscr" | |
c81bebd7 MM |
842 | }; |
843 | #endif | |
9878760c | 844 | \f |
daf11973 MM |
845 | #ifndef MASK_STRICT_ALIGN |
846 | #define MASK_STRICT_ALIGN 0 | |
847 | #endif | |
ffcfcb5f AM |
848 | #ifndef TARGET_PROFILE_KERNEL |
849 | #define TARGET_PROFILE_KERNEL 0 | |
850 | #endif | |
3961e8fe RH |
851 | |
852 | /* The VRSAVE bitmask puts bit %v0 as the most significant bit. */ | |
853 | #define ALTIVEC_REG_BIT(REGNO) (0x80000000 >> ((REGNO) - FIRST_ALTIVEC_REGNO)) | |
672a6f42 NB |
854 | \f |
855 | /* Initialize the GCC target structure. */ | |
91d231cb JM |
856 | #undef TARGET_ATTRIBUTE_TABLE |
857 | #define TARGET_ATTRIBUTE_TABLE rs6000_attribute_table | |
a5c76ee6 ZW |
858 | #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES |
859 | #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES rs6000_set_default_type_attributes | |
daf11973 | 860 | |
301d03af RS |
861 | #undef TARGET_ASM_ALIGNED_DI_OP |
862 | #define TARGET_ASM_ALIGNED_DI_OP DOUBLE_INT_ASM_OP | |
863 | ||
864 | /* Default unaligned ops are only provided for ELF. Find the ops needed | |
865 | for non-ELF systems. */ | |
866 | #ifndef OBJECT_FORMAT_ELF | |
cbaaba19 | 867 | #if TARGET_XCOFF |
ae6c1efd | 868 | /* For XCOFF. rs6000_assemble_integer will handle unaligned DIs on |
301d03af RS |
869 | 64-bit targets. */ |
870 | #undef TARGET_ASM_UNALIGNED_HI_OP | |
871 | #define TARGET_ASM_UNALIGNED_HI_OP "\t.vbyte\t2," | |
872 | #undef TARGET_ASM_UNALIGNED_SI_OP | |
873 | #define TARGET_ASM_UNALIGNED_SI_OP "\t.vbyte\t4," | |
874 | #undef TARGET_ASM_UNALIGNED_DI_OP | |
875 | #define TARGET_ASM_UNALIGNED_DI_OP "\t.vbyte\t8," | |
876 | #else | |
877 | /* For Darwin. */ | |
878 | #undef TARGET_ASM_UNALIGNED_HI_OP | |
879 | #define TARGET_ASM_UNALIGNED_HI_OP "\t.short\t" | |
880 | #undef TARGET_ASM_UNALIGNED_SI_OP | |
881 | #define TARGET_ASM_UNALIGNED_SI_OP "\t.long\t" | |
49bd1d27 SS |
882 | #undef TARGET_ASM_UNALIGNED_DI_OP |
883 | #define TARGET_ASM_UNALIGNED_DI_OP "\t.quad\t" | |
884 | #undef TARGET_ASM_ALIGNED_DI_OP | |
885 | #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t" | |
301d03af RS |
886 | #endif |
887 | #endif | |
888 | ||
889 | /* This hook deals with fixups for relocatable code and DI-mode objects | |
890 | in 64-bit code. */ | |
891 | #undef TARGET_ASM_INTEGER | |
892 | #define TARGET_ASM_INTEGER rs6000_assemble_integer | |
893 | ||
93638d7a AM |
894 | #ifdef HAVE_GAS_HIDDEN |
895 | #undef TARGET_ASM_ASSEMBLE_VISIBILITY | |
896 | #define TARGET_ASM_ASSEMBLE_VISIBILITY rs6000_assemble_visibility | |
897 | #endif | |
898 | ||
c4501e62 JJ |
899 | #undef TARGET_HAVE_TLS |
900 | #define TARGET_HAVE_TLS HAVE_AS_TLS | |
901 | ||
902 | #undef TARGET_CANNOT_FORCE_CONST_MEM | |
903 | #define TARGET_CANNOT_FORCE_CONST_MEM rs6000_tls_referenced_p | |
904 | ||
08c148a8 NB |
905 | #undef TARGET_ASM_FUNCTION_PROLOGUE |
906 | #define TARGET_ASM_FUNCTION_PROLOGUE rs6000_output_function_prologue | |
907 | #undef TARGET_ASM_FUNCTION_EPILOGUE | |
908 | #define TARGET_ASM_FUNCTION_EPILOGUE rs6000_output_function_epilogue | |
909 | ||
b54cf83a DE |
910 | #undef TARGET_SCHED_VARIABLE_ISSUE |
911 | #define TARGET_SCHED_VARIABLE_ISSUE rs6000_variable_issue | |
912 | ||
c237e94a ZW |
913 | #undef TARGET_SCHED_ISSUE_RATE |
914 | #define TARGET_SCHED_ISSUE_RATE rs6000_issue_rate | |
915 | #undef TARGET_SCHED_ADJUST_COST | |
916 | #define TARGET_SCHED_ADJUST_COST rs6000_adjust_cost | |
917 | #undef TARGET_SCHED_ADJUST_PRIORITY | |
918 | #define TARGET_SCHED_ADJUST_PRIORITY rs6000_adjust_priority | |
f676971a | 919 | #undef TARGET_SCHED_IS_COSTLY_DEPENDENCE |
569fa502 | 920 | #define TARGET_SCHED_IS_COSTLY_DEPENDENCE rs6000_is_costly_dependence |
cbe26ab8 DN |
921 | #undef TARGET_SCHED_FINISH |
922 | #define TARGET_SCHED_FINISH rs6000_sched_finish | |
c237e94a | 923 | |
be12c2b0 VM |
924 | #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD |
925 | #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD rs6000_use_sched_lookahead | |
926 | ||
7ccf35ed DN |
927 | #undef TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD |
928 | #define TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD rs6000_builtin_mask_for_load | |
929 | ||
0ac081f6 AH |
930 | #undef TARGET_INIT_BUILTINS |
931 | #define TARGET_INIT_BUILTINS rs6000_init_builtins | |
932 | ||
933 | #undef TARGET_EXPAND_BUILTIN | |
934 | #define TARGET_EXPAND_BUILTIN rs6000_expand_builtin | |
935 | ||
f18eca82 ZL |
936 | #undef TARGET_MANGLE_FUNDAMENTAL_TYPE |
937 | #define TARGET_MANGLE_FUNDAMENTAL_TYPE rs6000_mangle_fundamental_type | |
938 | ||
c15c90bb ZW |
939 | #undef TARGET_INIT_LIBFUNCS |
940 | #define TARGET_INIT_LIBFUNCS rs6000_init_libfuncs | |
941 | ||
f1384257 | 942 | #if TARGET_MACHO |
0e5dbd9b DE |
943 | #undef TARGET_BINDS_LOCAL_P |
944 | #define TARGET_BINDS_LOCAL_P rs6000_binds_local_p | |
f1384257 | 945 | #endif |
0e5dbd9b | 946 | |
3961e8fe RH |
947 | #undef TARGET_ASM_OUTPUT_MI_THUNK |
948 | #define TARGET_ASM_OUTPUT_MI_THUNK rs6000_output_mi_thunk | |
949 | ||
3961e8fe | 950 | #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK |
5b71a4e7 | 951 | #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_tree_hwi_hwi_tree_true |
00b960c7 | 952 | |
4977bab6 ZW |
953 | #undef TARGET_FUNCTION_OK_FOR_SIBCALL |
954 | #define TARGET_FUNCTION_OK_FOR_SIBCALL rs6000_function_ok_for_sibcall | |
955 | ||
3c50106f RH |
956 | #undef TARGET_RTX_COSTS |
957 | #define TARGET_RTX_COSTS rs6000_rtx_costs | |
dcefdf67 RH |
958 | #undef TARGET_ADDRESS_COST |
959 | #define TARGET_ADDRESS_COST hook_int_rtx_0 | |
3c50106f | 960 | |
c8e4f0e9 AH |
961 | #undef TARGET_VECTOR_OPAQUE_P |
962 | #define TARGET_VECTOR_OPAQUE_P is_ev64_opaque_type | |
62e1dfcf | 963 | |
96714395 AH |
964 | #undef TARGET_DWARF_REGISTER_SPAN |
965 | #define TARGET_DWARF_REGISTER_SPAN rs6000_dwarf_register_span | |
966 | ||
c6e8c921 GK |
967 | /* On rs6000, function arguments are promoted, as are function return |
968 | values. */ | |
969 | #undef TARGET_PROMOTE_FUNCTION_ARGS | |
970 | #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true | |
971 | #undef TARGET_PROMOTE_FUNCTION_RETURN | |
972 | #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true | |
973 | ||
c6e8c921 GK |
974 | #undef TARGET_RETURN_IN_MEMORY |
975 | #define TARGET_RETURN_IN_MEMORY rs6000_return_in_memory | |
976 | ||
977 | #undef TARGET_SETUP_INCOMING_VARARGS | |
978 | #define TARGET_SETUP_INCOMING_VARARGS setup_incoming_varargs | |
979 | ||
980 | /* Always strict argument naming on rs6000. */ | |
981 | #undef TARGET_STRICT_ARGUMENT_NAMING | |
982 | #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true | |
983 | #undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED | |
984 | #define TARGET_PRETEND_OUTGOING_VARARGS_NAMED hook_bool_CUMULATIVE_ARGS_true | |
42ba5130 RH |
985 | #undef TARGET_SPLIT_COMPLEX_ARG |
986 | #define TARGET_SPLIT_COMPLEX_ARG hook_bool_tree_true | |
fe984136 RH |
987 | #undef TARGET_MUST_PASS_IN_STACK |
988 | #define TARGET_MUST_PASS_IN_STACK rs6000_must_pass_in_stack | |
8cd5a4e0 RH |
989 | #undef TARGET_PASS_BY_REFERENCE |
990 | #define TARGET_PASS_BY_REFERENCE rs6000_pass_by_reference | |
78a52f11 RH |
991 | #undef TARGET_ARG_PARTIAL_BYTES |
992 | #define TARGET_ARG_PARTIAL_BYTES rs6000_arg_partial_bytes | |
c6e8c921 | 993 | |
c35d187f RH |
994 | #undef TARGET_BUILD_BUILTIN_VA_LIST |
995 | #define TARGET_BUILD_BUILTIN_VA_LIST rs6000_build_builtin_va_list | |
996 | ||
cd3ce9b4 JM |
997 | #undef TARGET_GIMPLIFY_VA_ARG_EXPR |
998 | #define TARGET_GIMPLIFY_VA_ARG_EXPR rs6000_gimplify_va_arg | |
999 | ||
93f90be6 FJ |
1000 | #undef TARGET_EH_RETURN_FILTER_MODE |
1001 | #define TARGET_EH_RETURN_FILTER_MODE rs6000_eh_return_filter_mode | |
1002 | ||
f676971a EC |
1003 | #undef TARGET_VECTOR_MODE_SUPPORTED_P |
1004 | #define TARGET_VECTOR_MODE_SUPPORTED_P rs6000_vector_mode_supported_p | |
1005 | ||
445cf5eb JM |
1006 | /* MPC604EUM 3.5.2 Weak Consistency between Multiple Processors |
1007 | The PowerPC architecture requires only weak consistency among | |
1008 | processors--that is, memory accesses between processors need not be | |
1009 | sequentially consistent and memory accesses among processors can occur | |
1010 | in any order. The ability to order memory accesses weakly provides | |
1011 | opportunities for more efficient use of the system bus. Unless a | |
1012 | dependency exists, the 604e allows read operations to precede store | |
1013 | operations. */ | |
1014 | #undef TARGET_RELAXED_ORDERING | |
1015 | #define TARGET_RELAXED_ORDERING true | |
1016 | ||
f6897b10 | 1017 | struct gcc_target targetm = TARGET_INITIALIZER; |
672a6f42 | 1018 | \f |
0d1fbc8c AH |
1019 | |
1020 | /* Value is 1 if hard register REGNO can hold a value of machine-mode | |
1021 | MODE. */ | |
1022 | static int | |
1023 | rs6000_hard_regno_mode_ok (int regno, enum machine_mode mode) | |
1024 | { | |
1025 | /* The GPRs can hold any mode, but values bigger than one register | |
1026 | cannot go past R31. */ | |
1027 | if (INT_REGNO_P (regno)) | |
1028 | return INT_REGNO_P (regno + HARD_REGNO_NREGS (regno, mode) - 1); | |
1029 | ||
1030 | /* The float registers can only hold floating modes and DImode. */ | |
1031 | if (FP_REGNO_P (regno)) | |
1032 | return | |
1033 | (GET_MODE_CLASS (mode) == MODE_FLOAT | |
1034 | && FP_REGNO_P (regno + HARD_REGNO_NREGS (regno, mode) - 1)) | |
1035 | || (GET_MODE_CLASS (mode) == MODE_INT | |
1036 | && GET_MODE_SIZE (mode) == UNITS_PER_FP_WORD); | |
1037 | ||
1038 | /* The CR register can only hold CC modes. */ | |
1039 | if (CR_REGNO_P (regno)) | |
1040 | return GET_MODE_CLASS (mode) == MODE_CC; | |
1041 | ||
1042 | if (XER_REGNO_P (regno)) | |
1043 | return mode == PSImode; | |
1044 | ||
1045 | /* AltiVec only in AldyVec registers. */ | |
1046 | if (ALTIVEC_REGNO_P (regno)) | |
1047 | return ALTIVEC_VECTOR_MODE (mode); | |
1048 | ||
1049 | /* ...but GPRs can hold SIMD data on the SPE in one register. */ | |
1050 | if (SPE_SIMD_REGNO_P (regno) && TARGET_SPE && SPE_VECTOR_MODE (mode)) | |
1051 | return 1; | |
1052 | ||
1053 | /* We cannot put TImode anywhere except general register and it must be | |
1054 | able to fit within the register set. */ | |
1055 | ||
1056 | return GET_MODE_SIZE (mode) <= UNITS_PER_WORD; | |
1057 | } | |
1058 | ||
1059 | /* Initialize rs6000_hard_regno_mode_ok_p table. */ | |
1060 | static void | |
1061 | rs6000_init_hard_regno_mode_ok (void) | |
1062 | { | |
1063 | int r, m; | |
1064 | ||
1065 | for (r = 0; r < FIRST_PSEUDO_REGISTER; ++r) | |
1066 | for (m = 0; m < NUM_MACHINE_MODES; ++m) | |
1067 | if (rs6000_hard_regno_mode_ok (r, m)) | |
1068 | rs6000_hard_regno_mode_ok_p[m][r] = true; | |
1069 | } | |
1070 | ||
c1e55850 GK |
1071 | /* If not otherwise specified by a target, make 'long double' equivalent to |
1072 | 'double'. */ | |
1073 | ||
1074 | #ifndef RS6000_DEFAULT_LONG_DOUBLE_SIZE | |
1075 | #define RS6000_DEFAULT_LONG_DOUBLE_SIZE 64 | |
1076 | #endif | |
1077 | ||
5248c961 RK |
1078 | /* Override command line options. Mostly we process the processor |
1079 | type and sometimes adjust other TARGET_ options. */ | |
1080 | ||
1081 | void | |
d779d0dc | 1082 | rs6000_override_options (const char *default_cpu) |
5248c961 | 1083 | { |
c4d38ccb | 1084 | size_t i, j; |
8e3f41e7 | 1085 | struct rs6000_cpu_select *ptr; |
66188a7e | 1086 | int set_masks; |
5248c961 | 1087 | |
66188a7e | 1088 | /* Simplifications for entries below. */ |
85638c0d | 1089 | |
66188a7e GK |
1090 | enum { |
1091 | POWERPC_BASE_MASK = MASK_POWERPC | MASK_NEW_MNEMONICS, | |
1092 | POWERPC_7400_MASK = POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_ALTIVEC | |
1093 | }; | |
85638c0d | 1094 | |
66188a7e GK |
1095 | /* This table occasionally claims that a processor does not support |
1096 | a particular feature even though it does, but the feature is slower | |
1097 | than the alternative. Thus, it shouldn't be relied on as a | |
f676971a | 1098 | complete description of the processor's support. |
66188a7e GK |
1099 | |
1100 | Please keep this list in order, and don't forget to update the | |
1101 | documentation in invoke.texi when adding a new processor or | |
1102 | flag. */ | |
5248c961 RK |
1103 | static struct ptt |
1104 | { | |
8b60264b KG |
1105 | const char *const name; /* Canonical processor name. */ |
1106 | const enum processor_type processor; /* Processor type enum value. */ | |
1107 | const int target_enable; /* Target flags to enable. */ | |
8b60264b | 1108 | } const processor_target_table[] |
66188a7e | 1109 | = {{"401", PROCESSOR_PPC403, POWERPC_BASE_MASK | MASK_SOFT_FLOAT}, |
49a0b204 | 1110 | {"403", PROCESSOR_PPC403, |
66188a7e GK |
1111 | POWERPC_BASE_MASK | MASK_SOFT_FLOAT | MASK_STRICT_ALIGN}, |
1112 | {"405", PROCESSOR_PPC405, POWERPC_BASE_MASK | MASK_SOFT_FLOAT}, | |
1113 | {"405fp", PROCESSOR_PPC405, POWERPC_BASE_MASK}, | |
1114 | {"440", PROCESSOR_PPC440, POWERPC_BASE_MASK | MASK_SOFT_FLOAT}, | |
1115 | {"440fp", PROCESSOR_PPC440, POWERPC_BASE_MASK}, | |
1116 | {"505", PROCESSOR_MPCCORE, POWERPC_BASE_MASK}, | |
5248c961 | 1117 | {"601", PROCESSOR_PPC601, |
66188a7e GK |
1118 | MASK_POWER | POWERPC_BASE_MASK | MASK_MULTIPLE | MASK_STRING}, |
1119 | {"602", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT}, | |
1120 | {"603", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT}, | |
1121 | {"603e", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT}, | |
1122 | {"604", PROCESSOR_PPC604, POWERPC_BASE_MASK | MASK_PPC_GFXOPT}, | |
1123 | {"604e", PROCESSOR_PPC604e, POWERPC_BASE_MASK | MASK_PPC_GFXOPT}, | |
7ddb6568 AM |
1124 | {"620", PROCESSOR_PPC620, |
1125 | POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64}, | |
1126 | {"630", PROCESSOR_PPC630, | |
1127 | POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64}, | |
66188a7e GK |
1128 | {"740", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT}, |
1129 | {"7400", PROCESSOR_PPC7400, POWERPC_7400_MASK}, | |
1130 | {"7450", PROCESSOR_PPC7450, POWERPC_7400_MASK}, | |
1131 | {"750", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT}, | |
1132 | {"801", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT}, | |
1133 | {"821", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT}, | |
1134 | {"823", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT}, | |
1135 | {"8540", PROCESSOR_PPC8540, POWERPC_BASE_MASK | MASK_PPC_GFXOPT}, | |
4d4cbc0e AH |
1136 | /* 8548 has a dummy entry for now. */ |
1137 | {"8548", PROCESSOR_PPC8540, POWERPC_BASE_MASK | MASK_PPC_GFXOPT}, | |
66188a7e | 1138 | {"860", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT}, |
7177e720 | 1139 | {"970", PROCESSOR_POWER4, |
66188a7e GK |
1140 | POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64}, |
1141 | {"common", PROCESSOR_COMMON, MASK_NEW_MNEMONICS}, | |
1142 | {"ec603e", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_SOFT_FLOAT}, | |
1143 | {"G3", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT}, | |
1144 | {"G4", PROCESSOR_PPC7450, POWERPC_7400_MASK}, | |
49ffe578 | 1145 | {"G5", PROCESSOR_POWER4, |
66188a7e GK |
1146 | POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64}, |
1147 | {"power", PROCESSOR_POWER, MASK_POWER | MASK_MULTIPLE | MASK_STRING}, | |
1148 | {"power2", PROCESSOR_POWER, | |
1149 | MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING}, | |
7ddb6568 AM |
1150 | {"power3", PROCESSOR_PPC630, |
1151 | POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64}, | |
1152 | {"power4", PROCESSOR_POWER4, | |
fc091c8e | 1153 | POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POWERPC64}, |
ec507f2d | 1154 | {"power5", PROCESSOR_POWER5, |
fc091c8e | 1155 | POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POWERPC64}, |
66188a7e GK |
1156 | {"powerpc", PROCESSOR_POWERPC, POWERPC_BASE_MASK}, |
1157 | {"powerpc64", PROCESSOR_POWERPC64, | |
1158 | POWERPC_BASE_MASK | MASK_POWERPC64}, | |
1159 | {"rios", PROCESSOR_RIOS1, MASK_POWER | MASK_MULTIPLE | MASK_STRING}, | |
1160 | {"rios1", PROCESSOR_RIOS1, MASK_POWER | MASK_MULTIPLE | MASK_STRING}, | |
1161 | {"rios2", PROCESSOR_RIOS2, | |
1162 | MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING}, | |
1163 | {"rsc", PROCESSOR_PPC601, MASK_POWER | MASK_MULTIPLE | MASK_STRING}, | |
1164 | {"rsc1", PROCESSOR_PPC601, MASK_POWER | MASK_MULTIPLE | MASK_STRING}, | |
7ddb6568 | 1165 | {"rs64a", PROCESSOR_RS64A, POWERPC_BASE_MASK | MASK_POWERPC64}, |
66188a7e | 1166 | }; |
5248c961 | 1167 | |
ca7558fc | 1168 | const size_t ptt_size = ARRAY_SIZE (processor_target_table); |
5248c961 | 1169 | |
66188a7e GK |
1170 | /* Some OSs don't support saving the high part of 64-bit registers on |
1171 | context switch. Other OSs don't support saving Altivec registers. | |
1172 | On those OSs, we don't touch the MASK_POWERPC64 or MASK_ALTIVEC | |
1173 | settings; if the user wants either, the user must explicitly specify | |
1174 | them and we won't interfere with the user's specification. */ | |
1175 | ||
1176 | enum { | |
1177 | POWER_MASKS = MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING, | |
f676971a | 1178 | POWERPC_MASKS = (POWERPC_BASE_MASK | MASK_PPC_GPOPT |
66188a7e GK |
1179 | | MASK_PPC_GFXOPT | MASK_POWERPC64 | MASK_ALTIVEC |
1180 | | MASK_MFCRF) | |
1181 | }; | |
0d1fbc8c AH |
1182 | |
1183 | rs6000_init_hard_regno_mode_ok (); | |
1184 | ||
c4ad648e | 1185 | set_masks = POWER_MASKS | POWERPC_MASKS | MASK_SOFT_FLOAT; |
66188a7e GK |
1186 | #ifdef OS_MISSING_POWERPC64 |
1187 | if (OS_MISSING_POWERPC64) | |
1188 | set_masks &= ~MASK_POWERPC64; | |
1189 | #endif | |
1190 | #ifdef OS_MISSING_ALTIVEC | |
1191 | if (OS_MISSING_ALTIVEC) | |
1192 | set_masks &= ~MASK_ALTIVEC; | |
1193 | #endif | |
1194 | ||
957211c3 AM |
1195 | /* Don't override these by the processor default if given explicitly. */ |
1196 | set_masks &= ~(target_flags_explicit | |
1197 | & (MASK_MULTIPLE | MASK_STRING | MASK_SOFT_FLOAT)); | |
1198 | ||
a4f6c312 | 1199 | /* Identify the processor type. */ |
8e3f41e7 | 1200 | rs6000_select[0].string = default_cpu; |
3cb999d8 | 1201 | rs6000_cpu = TARGET_POWERPC64 ? PROCESSOR_DEFAULT64 : PROCESSOR_DEFAULT; |
8e3f41e7 | 1202 | |
b6a1cbae | 1203 | for (i = 0; i < ARRAY_SIZE (rs6000_select); i++) |
5248c961 | 1204 | { |
8e3f41e7 MM |
1205 | ptr = &rs6000_select[i]; |
1206 | if (ptr->string != (char *)0 && ptr->string[0] != '\0') | |
5248c961 | 1207 | { |
8e3f41e7 MM |
1208 | for (j = 0; j < ptt_size; j++) |
1209 | if (! strcmp (ptr->string, processor_target_table[j].name)) | |
1210 | { | |
1211 | if (ptr->set_tune_p) | |
1212 | rs6000_cpu = processor_target_table[j].processor; | |
1213 | ||
1214 | if (ptr->set_arch_p) | |
1215 | { | |
66188a7e GK |
1216 | target_flags &= ~set_masks; |
1217 | target_flags |= (processor_target_table[j].target_enable | |
1218 | & set_masks); | |
8e3f41e7 MM |
1219 | } |
1220 | break; | |
1221 | } | |
1222 | ||
4406229e | 1223 | if (j == ptt_size) |
8e3f41e7 | 1224 | error ("bad value (%s) for %s switch", ptr->string, ptr->name); |
5248c961 RK |
1225 | } |
1226 | } | |
8a61d227 | 1227 | |
993f19a8 | 1228 | if (TARGET_E500) |
a3170dc6 AH |
1229 | rs6000_isel = 1; |
1230 | ||
dff9f1b6 DE |
1231 | /* If we are optimizing big endian systems for space, use the load/store |
1232 | multiple and string instructions. */ | |
ef792183 | 1233 | if (BYTES_BIG_ENDIAN && optimize_size) |
957211c3 | 1234 | target_flags |= ~target_flags_explicit & (MASK_MULTIPLE | MASK_STRING); |
938937d8 | 1235 | |
a4f6c312 SS |
1236 | /* Don't allow -mmultiple or -mstring on little endian systems |
1237 | unless the cpu is a 750, because the hardware doesn't support the | |
1238 | instructions used in little endian mode, and causes an alignment | |
1239 | trap. The 750 does not cause an alignment trap (except when the | |
1240 | target is unaligned). */ | |
bef84347 | 1241 | |
b21fb038 | 1242 | if (!BYTES_BIG_ENDIAN && rs6000_cpu != PROCESSOR_PPC750) |
7e69e155 MM |
1243 | { |
1244 | if (TARGET_MULTIPLE) | |
1245 | { | |
1246 | target_flags &= ~MASK_MULTIPLE; | |
b21fb038 | 1247 | if ((target_flags_explicit & MASK_MULTIPLE) != 0) |
7e69e155 MM |
1248 | warning ("-mmultiple is not supported on little endian systems"); |
1249 | } | |
1250 | ||
1251 | if (TARGET_STRING) | |
1252 | { | |
1253 | target_flags &= ~MASK_STRING; | |
b21fb038 | 1254 | if ((target_flags_explicit & MASK_STRING) != 0) |
938937d8 | 1255 | warning ("-mstring is not supported on little endian systems"); |
7e69e155 MM |
1256 | } |
1257 | } | |
3933e0e1 | 1258 | |
38c1f2d7 MM |
1259 | /* Set debug flags */ |
1260 | if (rs6000_debug_name) | |
1261 | { | |
bfc79d3b | 1262 | if (! strcmp (rs6000_debug_name, "all")) |
38c1f2d7 | 1263 | rs6000_debug_stack = rs6000_debug_arg = 1; |
bfc79d3b | 1264 | else if (! strcmp (rs6000_debug_name, "stack")) |
38c1f2d7 | 1265 | rs6000_debug_stack = 1; |
bfc79d3b | 1266 | else if (! strcmp (rs6000_debug_name, "arg")) |
38c1f2d7 MM |
1267 | rs6000_debug_arg = 1; |
1268 | else | |
c725bd79 | 1269 | error ("unknown -mdebug-%s switch", rs6000_debug_name); |
38c1f2d7 MM |
1270 | } |
1271 | ||
57ac7be9 AM |
1272 | if (rs6000_traceback_name) |
1273 | { | |
1274 | if (! strncmp (rs6000_traceback_name, "full", 4)) | |
1275 | rs6000_traceback = traceback_full; | |
1276 | else if (! strncmp (rs6000_traceback_name, "part", 4)) | |
1277 | rs6000_traceback = traceback_part; | |
1278 | else if (! strncmp (rs6000_traceback_name, "no", 2)) | |
1279 | rs6000_traceback = traceback_none; | |
1280 | else | |
9e637a26 | 1281 | error ("unknown -mtraceback arg %qs; expecting %<full%>, %<partial%> or %<none%>", |
57ac7be9 AM |
1282 | rs6000_traceback_name); |
1283 | } | |
1284 | ||
6fa3f289 | 1285 | /* Set size of long double */ |
c1e55850 | 1286 | rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE; |
6fa3f289 ZW |
1287 | if (rs6000_long_double_size_string) |
1288 | { | |
1289 | char *tail; | |
1290 | int size = strtol (rs6000_long_double_size_string, &tail, 10); | |
1291 | if (*tail != '\0' || (size != 64 && size != 128)) | |
1292 | error ("Unknown switch -mlong-double-%s", | |
1293 | rs6000_long_double_size_string); | |
1294 | else | |
1295 | rs6000_long_double_type_size = size; | |
1296 | } | |
1297 | ||
6d0ef01e HP |
1298 | /* Set Altivec ABI as default for powerpc64 linux. */ |
1299 | if (TARGET_ELF && TARGET_64BIT) | |
1300 | { | |
1301 | rs6000_altivec_abi = 1; | |
1302 | rs6000_altivec_vrsave = 1; | |
1303 | } | |
1304 | ||
594a51fe SS |
1305 | /* Set the Darwin64 ABI as default for 64-bit Darwin. */ |
1306 | if (DEFAULT_ABI == ABI_DARWIN && TARGET_64BIT) | |
1307 | { | |
1308 | rs6000_darwin64_abi = 1; | |
7bd3a493 | 1309 | /* Setting to empty string is same as "-mone-byte-bool". */ |
9c7956fd | 1310 | #if TARGET_MACHO |
7bd3a493 | 1311 | darwin_one_byte_bool = ""; |
9c7956fd | 1312 | #endif |
d9168963 SS |
1313 | /* Default to natural alignment, for better performance. */ |
1314 | rs6000_alignment_flags = MASK_ALIGN_NATURAL; | |
594a51fe SS |
1315 | } |
1316 | ||
0ac081f6 AH |
1317 | /* Handle -mabi= options. */ |
1318 | rs6000_parse_abi_options (); | |
1319 | ||
025d9908 KH |
1320 | /* Handle -malign-XXXXX option. */ |
1321 | rs6000_parse_alignment_option (); | |
1322 | ||
4d4cbc0e AH |
1323 | rs6000_parse_float_gprs_option (); |
1324 | ||
5da702b1 AH |
1325 | /* Handle generic -mFOO=YES/NO options. */ |
1326 | rs6000_parse_yes_no_option ("vrsave", rs6000_altivec_vrsave_string, | |
1327 | &rs6000_altivec_vrsave); | |
1328 | rs6000_parse_yes_no_option ("isel", rs6000_isel_string, | |
1329 | &rs6000_isel); | |
1330 | rs6000_parse_yes_no_option ("spe", rs6000_spe_string, &rs6000_spe); | |
993f19a8 | 1331 | |
c4501e62 JJ |
1332 | /* Handle -mtls-size option. */ |
1333 | rs6000_parse_tls_size_option (); | |
1334 | ||
a7ae18e2 AH |
1335 | #ifdef SUBTARGET_OVERRIDE_OPTIONS |
1336 | SUBTARGET_OVERRIDE_OPTIONS; | |
1337 | #endif | |
1338 | #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS | |
1339 | SUBSUBTARGET_OVERRIDE_OPTIONS; | |
1340 | #endif | |
4d4cbc0e AH |
1341 | #ifdef SUB3TARGET_OVERRIDE_OPTIONS |
1342 | SUB3TARGET_OVERRIDE_OPTIONS; | |
1343 | #endif | |
a7ae18e2 | 1344 | |
5da702b1 AH |
1345 | if (TARGET_E500) |
1346 | { | |
e4463bf1 AH |
1347 | if (TARGET_ALTIVEC) |
1348 | error ("AltiVec and E500 instructions cannot coexist"); | |
1349 | ||
5da702b1 AH |
1350 | /* The e500 does not have string instructions, and we set |
1351 | MASK_STRING above when optimizing for size. */ | |
1352 | if ((target_flags & MASK_STRING) != 0) | |
1353 | target_flags = target_flags & ~MASK_STRING; | |
b6e59a3a AH |
1354 | |
1355 | /* No SPE means 64-bit long doubles, even if an E500. */ | |
1356 | if (rs6000_spe_string != 0 | |
c4ad648e | 1357 | && !strcmp (rs6000_spe_string, "no")) |
b6e59a3a | 1358 | rs6000_long_double_type_size = 64; |
5da702b1 AH |
1359 | } |
1360 | else if (rs6000_select[1].string != NULL) | |
1361 | { | |
1362 | /* For the powerpc-eabispe configuration, we set all these by | |
1363 | default, so let's unset them if we manually set another | |
1364 | CPU that is not the E500. */ | |
1365 | if (rs6000_abi_string == 0) | |
1366 | rs6000_spe_abi = 0; | |
1367 | if (rs6000_spe_string == 0) | |
1368 | rs6000_spe = 0; | |
1369 | if (rs6000_float_gprs_string == 0) | |
1370 | rs6000_float_gprs = 0; | |
1371 | if (rs6000_isel_string == 0) | |
1372 | rs6000_isel = 0; | |
b6e59a3a | 1373 | if (rs6000_long_double_size_string == 0) |
c1e55850 | 1374 | rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE; |
5da702b1 | 1375 | } |
b5044283 | 1376 | |
ec507f2d DE |
1377 | rs6000_always_hint = (rs6000_cpu != PROCESSOR_POWER4 |
1378 | && rs6000_cpu != PROCESSOR_POWER5); | |
1379 | rs6000_sched_groups = (rs6000_cpu == PROCESSOR_POWER4 | |
1380 | || rs6000_cpu == PROCESSOR_POWER5); | |
1381 | ||
a5c76ee6 ZW |
1382 | /* Handle -m(no-)longcall option. This is a bit of a cheap hack, |
1383 | using TARGET_OPTIONS to handle a toggle switch, but we're out of | |
1384 | bits in target_flags so TARGET_SWITCHES cannot be used. | |
1385 | Assumption here is that rs6000_longcall_switch points into the | |
1386 | text of the complete option, rather than being a copy, so we can | |
1387 | scan back for the presence or absence of the no- modifier. */ | |
1388 | if (rs6000_longcall_switch) | |
1389 | { | |
1390 | const char *base = rs6000_longcall_switch; | |
1391 | while (base[-1] != 'm') base--; | |
1392 | ||
1393 | if (*rs6000_longcall_switch != '\0') | |
9e637a26 | 1394 | error ("invalid option %qs", base); |
a5c76ee6 ZW |
1395 | rs6000_default_long_calls = (base[0] != 'n'); |
1396 | } | |
1397 | ||
8bb418a3 ZL |
1398 | /* Handle -m(no-)warn-altivec-long similarly. */ |
1399 | if (rs6000_warn_altivec_long_switch) | |
1400 | { | |
1401 | const char *base = rs6000_warn_altivec_long_switch; | |
1402 | while (base[-1] != 'm') base--; | |
1403 | ||
1404 | if (*rs6000_warn_altivec_long_switch != '\0') | |
9e637a26 | 1405 | error ("invalid option %qs", base); |
8bb418a3 ZL |
1406 | rs6000_warn_altivec_long = (base[0] != 'n'); |
1407 | } | |
1408 | ||
cbe26ab8 | 1409 | /* Handle -mprioritize-restricted-insns option. */ |
ec507f2d DE |
1410 | rs6000_sched_restricted_insns_priority |
1411 | = (rs6000_sched_groups ? 1 : 0); | |
79ae11c4 DN |
1412 | if (rs6000_sched_restricted_insns_priority_str) |
1413 | rs6000_sched_restricted_insns_priority = | |
1414 | atoi (rs6000_sched_restricted_insns_priority_str); | |
1415 | ||
569fa502 | 1416 | /* Handle -msched-costly-dep option. */ |
ec507f2d DE |
1417 | rs6000_sched_costly_dep |
1418 | = (rs6000_sched_groups ? store_to_load_dep_costly : no_dep_costly); | |
569fa502 DN |
1419 | if (rs6000_sched_costly_dep_str) |
1420 | { | |
f676971a | 1421 | if (! strcmp (rs6000_sched_costly_dep_str, "no")) |
c4ad648e | 1422 | rs6000_sched_costly_dep = no_dep_costly; |
569fa502 | 1423 | else if (! strcmp (rs6000_sched_costly_dep_str, "all")) |
c4ad648e | 1424 | rs6000_sched_costly_dep = all_deps_costly; |
569fa502 | 1425 | else if (! strcmp (rs6000_sched_costly_dep_str, "true_store_to_load")) |
c4ad648e | 1426 | rs6000_sched_costly_dep = true_store_to_load_dep_costly; |
569fa502 | 1427 | else if (! strcmp (rs6000_sched_costly_dep_str, "store_to_load")) |
c4ad648e | 1428 | rs6000_sched_costly_dep = store_to_load_dep_costly; |
f676971a | 1429 | else |
c4ad648e | 1430 | rs6000_sched_costly_dep = atoi (rs6000_sched_costly_dep_str); |
cbe26ab8 DN |
1431 | } |
1432 | ||
1433 | /* Handle -minsert-sched-nops option. */ | |
ec507f2d DE |
1434 | rs6000_sched_insert_nops |
1435 | = (rs6000_sched_groups ? sched_finish_regroup_exact : sched_finish_none); | |
cbe26ab8 DN |
1436 | if (rs6000_sched_insert_nops_str) |
1437 | { | |
1438 | if (! strcmp (rs6000_sched_insert_nops_str, "no")) | |
c4ad648e | 1439 | rs6000_sched_insert_nops = sched_finish_none; |
cbe26ab8 | 1440 | else if (! strcmp (rs6000_sched_insert_nops_str, "pad")) |
c4ad648e | 1441 | rs6000_sched_insert_nops = sched_finish_pad_groups; |
cbe26ab8 | 1442 | else if (! strcmp (rs6000_sched_insert_nops_str, "regroup_exact")) |
c4ad648e | 1443 | rs6000_sched_insert_nops = sched_finish_regroup_exact; |
cbe26ab8 | 1444 | else |
c4ad648e | 1445 | rs6000_sched_insert_nops = atoi (rs6000_sched_insert_nops_str); |
569fa502 DN |
1446 | } |
1447 | ||
c81bebd7 | 1448 | #ifdef TARGET_REGNAMES |
a4f6c312 SS |
1449 | /* If the user desires alternate register names, copy in the |
1450 | alternate names now. */ | |
c81bebd7 | 1451 | if (TARGET_REGNAMES) |
4e135bdd | 1452 | memcpy (rs6000_reg_names, alt_reg_names, sizeof (rs6000_reg_names)); |
c81bebd7 MM |
1453 | #endif |
1454 | ||
6fa3f289 ZW |
1455 | /* Set TARGET_AIX_STRUCT_RET last, after the ABI is determined. |
1456 | If -maix-struct-return or -msvr4-struct-return was explicitly | |
1457 | used, don't override with the ABI default. */ | |
b21fb038 | 1458 | if ((target_flags_explicit & MASK_AIX_STRUCT_RET) == 0) |
6fa3f289 ZW |
1459 | { |
1460 | if (DEFAULT_ABI == ABI_V4 && !DRAFT_V4_STRUCT_RET) | |
1461 | target_flags = (target_flags & ~MASK_AIX_STRUCT_RET); | |
1462 | else | |
1463 | target_flags |= MASK_AIX_STRUCT_RET; | |
1464 | } | |
1465 | ||
fcce224d DE |
1466 | if (TARGET_LONG_DOUBLE_128 |
1467 | && (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)) | |
70a01792 | 1468 | REAL_MODE_FORMAT (TFmode) = &ibm_extended_format; |
fcce224d | 1469 | |
9ebbca7d GK |
1470 | /* Allocate an alias set for register saves & restores from stack. */ |
1471 | rs6000_sr_alias_set = new_alias_set (); | |
1472 | ||
f676971a | 1473 | if (TARGET_TOC) |
9ebbca7d | 1474 | ASM_GENERATE_INTERNAL_LABEL (toc_label_name, "LCTOC", 1); |
71f123ca | 1475 | |
301d03af RS |
1476 | /* We can only guarantee the availability of DI pseudo-ops when |
1477 | assembling for 64-bit targets. */ | |
ae6c1efd | 1478 | if (!TARGET_64BIT) |
301d03af RS |
1479 | { |
1480 | targetm.asm_out.aligned_op.di = NULL; | |
1481 | targetm.asm_out.unaligned_op.di = NULL; | |
1482 | } | |
1483 | ||
1494c534 DE |
1484 | /* Set branch target alignment, if not optimizing for size. */ |
1485 | if (!optimize_size) | |
1486 | { | |
1487 | if (rs6000_sched_groups) | |
1488 | { | |
1489 | if (align_functions <= 0) | |
1490 | align_functions = 16; | |
1491 | if (align_jumps <= 0) | |
1492 | align_jumps = 16; | |
1493 | if (align_loops <= 0) | |
1494 | align_loops = 16; | |
1495 | } | |
1496 | if (align_jumps_max_skip <= 0) | |
1497 | align_jumps_max_skip = 15; | |
1498 | if (align_loops_max_skip <= 0) | |
1499 | align_loops_max_skip = 15; | |
1500 | } | |
2792d578 | 1501 | |
71f123ca FS |
1502 | /* Arrange to save and restore machine status around nested functions. */ |
1503 | init_machine_status = rs6000_init_machine_status; | |
42ba5130 RH |
1504 | |
1505 | /* We should always be splitting complex arguments, but we can't break | |
1506 | Linux and Darwin ABIs at the moment. For now, only AIX is fixed. */ | |
18f63bfa | 1507 | if (DEFAULT_ABI != ABI_AIX) |
42ba5130 | 1508 | targetm.calls.split_complex_arg = NULL; |
8b897cfa RS |
1509 | |
1510 | /* Initialize rs6000_cost with the appropriate target costs. */ | |
1511 | if (optimize_size) | |
1512 | rs6000_cost = TARGET_POWERPC64 ? &size64_cost : &size32_cost; | |
1513 | else | |
1514 | switch (rs6000_cpu) | |
1515 | { | |
1516 | case PROCESSOR_RIOS1: | |
1517 | rs6000_cost = &rios1_cost; | |
1518 | break; | |
1519 | ||
1520 | case PROCESSOR_RIOS2: | |
1521 | rs6000_cost = &rios2_cost; | |
1522 | break; | |
1523 | ||
1524 | case PROCESSOR_RS64A: | |
1525 | rs6000_cost = &rs64a_cost; | |
1526 | break; | |
1527 | ||
1528 | case PROCESSOR_MPCCORE: | |
1529 | rs6000_cost = &mpccore_cost; | |
1530 | break; | |
1531 | ||
1532 | case PROCESSOR_PPC403: | |
1533 | rs6000_cost = &ppc403_cost; | |
1534 | break; | |
1535 | ||
1536 | case PROCESSOR_PPC405: | |
1537 | rs6000_cost = &ppc405_cost; | |
1538 | break; | |
1539 | ||
1540 | case PROCESSOR_PPC440: | |
1541 | rs6000_cost = &ppc440_cost; | |
1542 | break; | |
1543 | ||
1544 | case PROCESSOR_PPC601: | |
1545 | rs6000_cost = &ppc601_cost; | |
1546 | break; | |
1547 | ||
1548 | case PROCESSOR_PPC603: | |
1549 | rs6000_cost = &ppc603_cost; | |
1550 | break; | |
1551 | ||
1552 | case PROCESSOR_PPC604: | |
1553 | rs6000_cost = &ppc604_cost; | |
1554 | break; | |
1555 | ||
1556 | case PROCESSOR_PPC604e: | |
1557 | rs6000_cost = &ppc604e_cost; | |
1558 | break; | |
1559 | ||
1560 | case PROCESSOR_PPC620: | |
8b897cfa RS |
1561 | rs6000_cost = &ppc620_cost; |
1562 | break; | |
1563 | ||
f0517163 RS |
1564 | case PROCESSOR_PPC630: |
1565 | rs6000_cost = &ppc630_cost; | |
1566 | break; | |
1567 | ||
8b897cfa RS |
1568 | case PROCESSOR_PPC750: |
1569 | case PROCESSOR_PPC7400: | |
1570 | rs6000_cost = &ppc750_cost; | |
1571 | break; | |
1572 | ||
1573 | case PROCESSOR_PPC7450: | |
1574 | rs6000_cost = &ppc7450_cost; | |
1575 | break; | |
1576 | ||
1577 | case PROCESSOR_PPC8540: | |
1578 | rs6000_cost = &ppc8540_cost; | |
1579 | break; | |
1580 | ||
1581 | case PROCESSOR_POWER4: | |
1582 | case PROCESSOR_POWER5: | |
1583 | rs6000_cost = &power4_cost; | |
1584 | break; | |
1585 | ||
1586 | default: | |
1587 | abort (); | |
1588 | } | |
5248c961 | 1589 | } |
5accd822 | 1590 | |
7ccf35ed DN |
1591 | /* Implement targetm.vectorize.builtin_mask_for_load. */ |
1592 | static tree | |
1593 | rs6000_builtin_mask_for_load (void) | |
1594 | { | |
1595 | if (TARGET_ALTIVEC) | |
1596 | return altivec_builtin_mask_for_load; | |
1597 | else | |
1598 | return 0; | |
1599 | } | |
1600 | ||
5da702b1 AH |
1601 | /* Handle generic options of the form -mfoo=yes/no. |
1602 | NAME is the option name. | |
1603 | VALUE is the option value. | |
1604 | FLAG is the pointer to the flag where to store a 1 or 0, depending on | |
1605 | whether the option value is 'yes' or 'no' respectively. */ | |
993f19a8 | 1606 | static void |
5da702b1 | 1607 | rs6000_parse_yes_no_option (const char *name, const char *value, int *flag) |
993f19a8 | 1608 | { |
5da702b1 | 1609 | if (value == 0) |
993f19a8 | 1610 | return; |
5da702b1 AH |
1611 | else if (!strcmp (value, "yes")) |
1612 | *flag = 1; | |
1613 | else if (!strcmp (value, "no")) | |
1614 | *flag = 0; | |
08b57fb3 | 1615 | else |
5da702b1 | 1616 | error ("unknown -m%s= option specified: '%s'", name, value); |
08b57fb3 AH |
1617 | } |
1618 | ||
0ac081f6 | 1619 | /* Handle -mabi= options. */ |
00b960c7 | 1620 | static void |
863d938c | 1621 | rs6000_parse_abi_options (void) |
0ac081f6 AH |
1622 | { |
1623 | if (rs6000_abi_string == 0) | |
1624 | return; | |
1625 | else if (! strcmp (rs6000_abi_string, "altivec")) | |
5cc73f91 AH |
1626 | { |
1627 | rs6000_altivec_abi = 1; | |
1628 | rs6000_spe_abi = 0; | |
1629 | } | |
76a773f3 AH |
1630 | else if (! strcmp (rs6000_abi_string, "no-altivec")) |
1631 | rs6000_altivec_abi = 0; | |
a3170dc6 | 1632 | else if (! strcmp (rs6000_abi_string, "spe")) |
01f4962d NS |
1633 | { |
1634 | rs6000_spe_abi = 1; | |
5cc73f91 | 1635 | rs6000_altivec_abi = 0; |
01f4962d NS |
1636 | if (!TARGET_SPE_ABI) |
1637 | error ("not configured for ABI: '%s'", rs6000_abi_string); | |
1638 | } | |
f676971a | 1639 | |
594a51fe SS |
1640 | /* These are here for testing during development only, do not |
1641 | document in the manual please. */ | |
1642 | else if (! strcmp (rs6000_abi_string, "d64")) | |
1643 | { | |
1644 | rs6000_darwin64_abi = 1; | |
1645 | warning ("Using darwin64 ABI"); | |
1646 | } | |
1647 | else if (! strcmp (rs6000_abi_string, "d32")) | |
1648 | { | |
1649 | rs6000_darwin64_abi = 0; | |
1650 | warning ("Using old darwin ABI"); | |
1651 | } | |
1652 | ||
a3170dc6 AH |
1653 | else if (! strcmp (rs6000_abi_string, "no-spe")) |
1654 | rs6000_spe_abi = 0; | |
0ac081f6 | 1655 | else |
c725bd79 | 1656 | error ("unknown ABI specified: '%s'", rs6000_abi_string); |
0ac081f6 AH |
1657 | } |
1658 | ||
4d4cbc0e AH |
1659 | /* Handle -mfloat-gprs= options. */ |
1660 | static void | |
1661 | rs6000_parse_float_gprs_option (void) | |
1662 | { | |
1663 | if (rs6000_float_gprs_string == 0) | |
1664 | return; | |
1665 | else if (! strcmp (rs6000_float_gprs_string, "yes") | |
1666 | || ! strcmp (rs6000_float_gprs_string, "single")) | |
1667 | rs6000_float_gprs = 1; | |
1668 | else if (! strcmp (rs6000_float_gprs_string, "double")) | |
1669 | rs6000_float_gprs = 2; | |
1670 | else if (! strcmp (rs6000_float_gprs_string, "no")) | |
1671 | rs6000_float_gprs = 0; | |
1672 | else | |
1673 | error ("invalid option for -mfloat-gprs"); | |
1674 | } | |
1675 | ||
025d9908 KH |
1676 | /* Handle -malign-XXXXXX options. */ |
1677 | static void | |
863d938c | 1678 | rs6000_parse_alignment_option (void) |
025d9908 | 1679 | { |
b20a9cca AM |
1680 | if (rs6000_alignment_string == 0) |
1681 | return; | |
1682 | else if (! strcmp (rs6000_alignment_string, "power")) | |
d9168963 SS |
1683 | { |
1684 | /* On 64-bit Darwin, power alignment is ABI-incompatible with | |
1685 | some C library functions, so warn about it. The flag may be | |
1686 | useful for performance studies from time to time though, so | |
1687 | don't disable it entirely. */ | |
1688 | if (DEFAULT_ABI == ABI_DARWIN && TARGET_64BIT) | |
1689 | warning ("-malign-power is not supported for 64-bit Darwin;" | |
1690 | " it is incompatible with the installed C and C++ libraries"); | |
1691 | rs6000_alignment_flags = MASK_ALIGN_POWER; | |
1692 | } | |
025d9908 KH |
1693 | else if (! strcmp (rs6000_alignment_string, "natural")) |
1694 | rs6000_alignment_flags = MASK_ALIGN_NATURAL; | |
1695 | else | |
1696 | error ("unknown -malign-XXXXX option specified: '%s'", | |
1697 | rs6000_alignment_string); | |
1698 | } | |
1699 | ||
c4501e62 JJ |
1700 | /* Validate and record the size specified with the -mtls-size option. */ |
1701 | ||
1702 | static void | |
863d938c | 1703 | rs6000_parse_tls_size_option (void) |
c4501e62 JJ |
1704 | { |
1705 | if (rs6000_tls_size_string == 0) | |
1706 | return; | |
1707 | else if (strcmp (rs6000_tls_size_string, "16") == 0) | |
1708 | rs6000_tls_size = 16; | |
1709 | else if (strcmp (rs6000_tls_size_string, "32") == 0) | |
1710 | rs6000_tls_size = 32; | |
1711 | else if (strcmp (rs6000_tls_size_string, "64") == 0) | |
1712 | rs6000_tls_size = 64; | |
1713 | else | |
9e637a26 | 1714 | error ("bad value %qs for -mtls-size switch", rs6000_tls_size_string); |
c4501e62 JJ |
1715 | } |
1716 | ||
5accd822 | 1717 | void |
a2369ed3 | 1718 | optimization_options (int level ATTRIBUTE_UNUSED, int size ATTRIBUTE_UNUSED) |
5accd822 | 1719 | { |
5accd822 | 1720 | } |
3cfa4909 MM |
1721 | \f |
1722 | /* Do anything needed at the start of the asm file. */ | |
1723 | ||
1bc7c5b6 | 1724 | static void |
863d938c | 1725 | rs6000_file_start (void) |
3cfa4909 | 1726 | { |
c4d38ccb | 1727 | size_t i; |
3cfa4909 | 1728 | char buffer[80]; |
d330fd93 | 1729 | const char *start = buffer; |
3cfa4909 | 1730 | struct rs6000_cpu_select *ptr; |
1bc7c5b6 ZW |
1731 | const char *default_cpu = TARGET_CPU_DEFAULT; |
1732 | FILE *file = asm_out_file; | |
1733 | ||
1734 | default_file_start (); | |
1735 | ||
1736 | #ifdef TARGET_BI_ARCH | |
1737 | if ((TARGET_DEFAULT ^ target_flags) & MASK_64BIT) | |
1738 | default_cpu = 0; | |
1739 | #endif | |
3cfa4909 MM |
1740 | |
1741 | if (flag_verbose_asm) | |
1742 | { | |
1743 | sprintf (buffer, "\n%s rs6000/powerpc options:", ASM_COMMENT_START); | |
1744 | rs6000_select[0].string = default_cpu; | |
1745 | ||
b6a1cbae | 1746 | for (i = 0; i < ARRAY_SIZE (rs6000_select); i++) |
3cfa4909 MM |
1747 | { |
1748 | ptr = &rs6000_select[i]; | |
1749 | if (ptr->string != (char *)0 && ptr->string[0] != '\0') | |
1750 | { | |
1751 | fprintf (file, "%s %s%s", start, ptr->name, ptr->string); | |
1752 | start = ""; | |
1753 | } | |
1754 | } | |
1755 | ||
b91da81f | 1756 | #ifdef USING_ELFOS_H |
3cfa4909 MM |
1757 | switch (rs6000_sdata) |
1758 | { | |
1759 | case SDATA_NONE: fprintf (file, "%s -msdata=none", start); start = ""; break; | |
1760 | case SDATA_DATA: fprintf (file, "%s -msdata=data", start); start = ""; break; | |
1761 | case SDATA_SYSV: fprintf (file, "%s -msdata=sysv", start); start = ""; break; | |
1762 | case SDATA_EABI: fprintf (file, "%s -msdata=eabi", start); start = ""; break; | |
1763 | } | |
1764 | ||
1765 | if (rs6000_sdata && g_switch_value) | |
1766 | { | |
307b599c MK |
1767 | fprintf (file, "%s -G " HOST_WIDE_INT_PRINT_UNSIGNED, start, |
1768 | g_switch_value); | |
3cfa4909 MM |
1769 | start = ""; |
1770 | } | |
1771 | #endif | |
1772 | ||
1773 | if (*start == '\0') | |
949ea356 | 1774 | putc ('\n', file); |
3cfa4909 | 1775 | } |
b723e82f JJ |
1776 | |
1777 | if (DEFAULT_ABI == ABI_AIX || (TARGET_ELF && flag_pic == 2)) | |
1778 | { | |
1779 | toc_section (); | |
1780 | text_section (); | |
1781 | } | |
3cfa4909 | 1782 | } |
c4e18b1c | 1783 | |
5248c961 | 1784 | \f |
a0ab749a | 1785 | /* Return nonzero if this function is known to have a null epilogue. */ |
9878760c RK |
1786 | |
1787 | int | |
863d938c | 1788 | direct_return (void) |
9878760c | 1789 | { |
4697a36c MM |
1790 | if (reload_completed) |
1791 | { | |
1792 | rs6000_stack_t *info = rs6000_stack_info (); | |
1793 | ||
1794 | if (info->first_gp_reg_save == 32 | |
1795 | && info->first_fp_reg_save == 64 | |
00b960c7 | 1796 | && info->first_altivec_reg_save == LAST_ALTIVEC_REGNO + 1 |
c81fc13e DE |
1797 | && ! info->lr_save_p |
1798 | && ! info->cr_save_p | |
00b960c7 | 1799 | && info->vrsave_mask == 0 |
c81fc13e | 1800 | && ! info->push_p) |
4697a36c MM |
1801 | return 1; |
1802 | } | |
1803 | ||
1804 | return 0; | |
9878760c RK |
1805 | } |
1806 | ||
4e74d8ec MM |
1807 | /* Return the number of instructions it takes to form a constant in an |
1808 | integer register. */ | |
1809 | ||
48d72335 | 1810 | int |
a2369ed3 | 1811 | num_insns_constant_wide (HOST_WIDE_INT value) |
4e74d8ec MM |
1812 | { |
1813 | /* signed constant loadable with {cal|addi} */ | |
5f59ecb7 | 1814 | if (CONST_OK_FOR_LETTER_P (value, 'I')) |
0865c631 GK |
1815 | return 1; |
1816 | ||
4e74d8ec | 1817 | /* constant loadable with {cau|addis} */ |
5f59ecb7 | 1818 | else if (CONST_OK_FOR_LETTER_P (value, 'L')) |
4e74d8ec MM |
1819 | return 1; |
1820 | ||
5f59ecb7 | 1821 | #if HOST_BITS_PER_WIDE_INT == 64 |
c81fc13e | 1822 | else if (TARGET_POWERPC64) |
4e74d8ec | 1823 | { |
a65c591c DE |
1824 | HOST_WIDE_INT low = ((value & 0xffffffff) ^ 0x80000000) - 0x80000000; |
1825 | HOST_WIDE_INT high = value >> 31; | |
4e74d8ec | 1826 | |
a65c591c | 1827 | if (high == 0 || high == -1) |
4e74d8ec MM |
1828 | return 2; |
1829 | ||
a65c591c | 1830 | high >>= 1; |
4e74d8ec | 1831 | |
a65c591c | 1832 | if (low == 0) |
4e74d8ec | 1833 | return num_insns_constant_wide (high) + 1; |
4e74d8ec MM |
1834 | else |
1835 | return (num_insns_constant_wide (high) | |
e396202a | 1836 | + num_insns_constant_wide (low) + 1); |
4e74d8ec MM |
1837 | } |
1838 | #endif | |
1839 | ||
1840 | else | |
1841 | return 2; | |
1842 | } | |
1843 | ||
1844 | int | |
a2369ed3 | 1845 | num_insns_constant (rtx op, enum machine_mode mode) |
4e74d8ec | 1846 | { |
4e74d8ec | 1847 | if (GET_CODE (op) == CONST_INT) |
0d30d435 DE |
1848 | { |
1849 | #if HOST_BITS_PER_WIDE_INT == 64 | |
4e2c1c44 DE |
1850 | if ((INTVAL (op) >> 31) != 0 && (INTVAL (op) >> 31) != -1 |
1851 | && mask64_operand (op, mode)) | |
c4ad648e | 1852 | return 2; |
0d30d435 DE |
1853 | else |
1854 | #endif | |
1855 | return num_insns_constant_wide (INTVAL (op)); | |
1856 | } | |
4e74d8ec | 1857 | |
6fc48950 MM |
1858 | else if (GET_CODE (op) == CONST_DOUBLE && mode == SFmode) |
1859 | { | |
1860 | long l; | |
1861 | REAL_VALUE_TYPE rv; | |
1862 | ||
1863 | REAL_VALUE_FROM_CONST_DOUBLE (rv, op); | |
1864 | REAL_VALUE_TO_TARGET_SINGLE (rv, l); | |
e72247f4 | 1865 | return num_insns_constant_wide ((HOST_WIDE_INT) l); |
6fc48950 MM |
1866 | } |
1867 | ||
47ad8c61 | 1868 | else if (GET_CODE (op) == CONST_DOUBLE) |
4e74d8ec | 1869 | { |
47ad8c61 MM |
1870 | HOST_WIDE_INT low; |
1871 | HOST_WIDE_INT high; | |
1872 | long l[2]; | |
1873 | REAL_VALUE_TYPE rv; | |
1874 | int endian = (WORDS_BIG_ENDIAN == 0); | |
4e74d8ec | 1875 | |
47ad8c61 MM |
1876 | if (mode == VOIDmode || mode == DImode) |
1877 | { | |
1878 | high = CONST_DOUBLE_HIGH (op); | |
1879 | low = CONST_DOUBLE_LOW (op); | |
1880 | } | |
1881 | else | |
1882 | { | |
1883 | REAL_VALUE_FROM_CONST_DOUBLE (rv, op); | |
1884 | REAL_VALUE_TO_TARGET_DOUBLE (rv, l); | |
1885 | high = l[endian]; | |
1886 | low = l[1 - endian]; | |
1887 | } | |
4e74d8ec | 1888 | |
47ad8c61 MM |
1889 | if (TARGET_32BIT) |
1890 | return (num_insns_constant_wide (low) | |
1891 | + num_insns_constant_wide (high)); | |
4e74d8ec MM |
1892 | |
1893 | else | |
47ad8c61 | 1894 | { |
e72247f4 | 1895 | if (high == 0 && low >= 0) |
47ad8c61 MM |
1896 | return num_insns_constant_wide (low); |
1897 | ||
e72247f4 | 1898 | else if (high == -1 && low < 0) |
47ad8c61 MM |
1899 | return num_insns_constant_wide (low); |
1900 | ||
a260abc9 DE |
1901 | else if (mask64_operand (op, mode)) |
1902 | return 2; | |
1903 | ||
47ad8c61 MM |
1904 | else if (low == 0) |
1905 | return num_insns_constant_wide (high) + 1; | |
1906 | ||
1907 | else | |
1908 | return (num_insns_constant_wide (high) | |
1909 | + num_insns_constant_wide (low) + 1); | |
1910 | } | |
4e74d8ec MM |
1911 | } |
1912 | ||
1913 | else | |
1914 | abort (); | |
1915 | } | |
1916 | ||
effa5d5d | 1917 | /* Returns the constant for the splat instruction, if exists. */ |
452a7d36 | 1918 | |
48d72335 | 1919 | int |
452a7d36 HP |
1920 | easy_vector_splat_const (int cst, enum machine_mode mode) |
1921 | { | |
f676971a | 1922 | switch (mode) |
452a7d36 HP |
1923 | { |
1924 | case V4SImode: | |
f676971a EC |
1925 | if (EASY_VECTOR_15 (cst) |
1926 | || EASY_VECTOR_15_ADD_SELF (cst)) | |
452a7d36 HP |
1927 | return cst; |
1928 | if ((cst & 0xffff) != ((cst >> 16) & 0xffff)) | |
1929 | break; | |
1930 | cst = cst >> 16; | |
c4ad648e AM |
1931 | /* Fall thru */ |
1932 | ||
452a7d36 | 1933 | case V8HImode: |
f676971a EC |
1934 | if (EASY_VECTOR_15 (cst) |
1935 | || EASY_VECTOR_15_ADD_SELF (cst)) | |
452a7d36 HP |
1936 | return cst; |
1937 | if ((cst & 0xff) != ((cst >> 8) & 0xff)) | |
1938 | break; | |
1939 | cst = cst >> 8; | |
c4ad648e AM |
1940 | /* Fall thru */ |
1941 | ||
452a7d36 | 1942 | case V16QImode: |
c4ad648e AM |
1943 | if (EASY_VECTOR_15 (cst) |
1944 | || EASY_VECTOR_15_ADD_SELF (cst)) | |
1945 | return cst; | |
f676971a | 1946 | default: |
452a7d36 HP |
1947 | break; |
1948 | } | |
1949 | return 0; | |
1950 | } | |
1951 | ||
72ac76be | 1952 | /* Return nonzero if all elements of a vector have the same value. */ |
69ef87e2 | 1953 | |
48d72335 | 1954 | int |
a2369ed3 | 1955 | easy_vector_same (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
d744e06e AH |
1956 | { |
1957 | int units, i, cst; | |
1958 | ||
1959 | units = CONST_VECTOR_NUNITS (op); | |
1960 | ||
1961 | cst = INTVAL (CONST_VECTOR_ELT (op, 0)); | |
1962 | for (i = 1; i < units; ++i) | |
1963 | if (INTVAL (CONST_VECTOR_ELT (op, i)) != cst) | |
1964 | break; | |
452a7d36 | 1965 | if (i == units && easy_vector_splat_const (cst, mode)) |
d744e06e AH |
1966 | return 1; |
1967 | return 0; | |
1968 | } | |
1969 | ||
452a7d36 | 1970 | /* Generate easy_vector_constant out of a easy_vector_constant_add_self. */ |
d744e06e | 1971 | |
f676971a | 1972 | rtx |
452a7d36 HP |
1973 | gen_easy_vector_constant_add_self (rtx op) |
1974 | { | |
1975 | int i, units; | |
1976 | rtvec v; | |
1977 | units = GET_MODE_NUNITS (GET_MODE (op)); | |
1978 | v = rtvec_alloc (units); | |
1979 | ||
1980 | for (i = 0; i < units; i++) | |
f676971a | 1981 | RTVEC_ELT (v, i) = |
452a7d36 HP |
1982 | GEN_INT (INTVAL (CONST_VECTOR_ELT (op, i)) >> 1); |
1983 | return gen_rtx_raw_CONST_VECTOR (GET_MODE (op), v); | |
d744e06e AH |
1984 | } |
1985 | ||
1986 | const char * | |
a2369ed3 | 1987 | output_vec_const_move (rtx *operands) |
d744e06e AH |
1988 | { |
1989 | int cst, cst2; | |
1990 | enum machine_mode mode; | |
1991 | rtx dest, vec; | |
1992 | ||
1993 | dest = operands[0]; | |
1994 | vec = operands[1]; | |
69ef87e2 | 1995 | |
d744e06e AH |
1996 | cst = INTVAL (CONST_VECTOR_ELT (vec, 0)); |
1997 | cst2 = INTVAL (CONST_VECTOR_ELT (vec, 1)); | |
1998 | mode = GET_MODE (dest); | |
69ef87e2 | 1999 | |
d744e06e AH |
2000 | if (TARGET_ALTIVEC) |
2001 | { | |
2002 | if (zero_constant (vec, mode)) | |
2003 | return "vxor %0,%0,%0"; | |
ce1f50b2 | 2004 | else if (easy_vector_constant (vec, mode)) |
98ef3137 | 2005 | { |
d744e06e AH |
2006 | operands[1] = GEN_INT (cst); |
2007 | switch (mode) | |
2008 | { | |
2009 | case V4SImode: | |
452a7d36 | 2010 | if (EASY_VECTOR_15 (cst)) |
ce1f50b2 HP |
2011 | { |
2012 | operands[1] = GEN_INT (cst); | |
2013 | return "vspltisw %0,%1"; | |
2014 | } | |
452a7d36 HP |
2015 | else if (EASY_VECTOR_15_ADD_SELF (cst)) |
2016 | return "#"; | |
ce1f50b2 | 2017 | cst = cst >> 16; |
c4ad648e AM |
2018 | /* Fall thru */ |
2019 | ||
d744e06e | 2020 | case V8HImode: |
452a7d36 | 2021 | if (EASY_VECTOR_15 (cst)) |
ce1f50b2 HP |
2022 | { |
2023 | operands[1] = GEN_INT (cst); | |
2024 | return "vspltish %0,%1"; | |
2025 | } | |
452a7d36 HP |
2026 | else if (EASY_VECTOR_15_ADD_SELF (cst)) |
2027 | return "#"; | |
ce1f50b2 | 2028 | cst = cst >> 8; |
c4ad648e AM |
2029 | /* Fall thru */ |
2030 | ||
d744e06e | 2031 | case V16QImode: |
452a7d36 | 2032 | if (EASY_VECTOR_15 (cst)) |
ce1f50b2 HP |
2033 | { |
2034 | operands[1] = GEN_INT (cst); | |
2035 | return "vspltisb %0,%1"; | |
2036 | } | |
452a7d36 HP |
2037 | else if (EASY_VECTOR_15_ADD_SELF (cst)) |
2038 | return "#"; | |
c4ad648e | 2039 | |
d744e06e AH |
2040 | default: |
2041 | abort (); | |
2042 | } | |
98ef3137 | 2043 | } |
d744e06e AH |
2044 | else |
2045 | abort (); | |
69ef87e2 AH |
2046 | } |
2047 | ||
d744e06e AH |
2048 | if (TARGET_SPE) |
2049 | { | |
2050 | /* Vector constant 0 is handled as a splitter of V2SI, and in the | |
2051 | pattern of V1DI, V4HI, and V2SF. | |
2052 | ||
c1207243 | 2053 | FIXME: We should probably return # and add post reload |
c4ad648e | 2054 | splitters for these, but this way is so easy ;-). */ |
d744e06e AH |
2055 | operands[1] = GEN_INT (cst); |
2056 | operands[2] = GEN_INT (cst2); | |
2057 | if (cst == cst2) | |
2058 | return "li %0,%1\n\tevmergelo %0,%0,%0"; | |
2059 | else | |
2060 | return "li %0,%1\n\tevmergelo %0,%0,%0\n\tli %0,%2"; | |
2061 | } | |
2062 | ||
2063 | abort (); | |
69ef87e2 AH |
2064 | } |
2065 | ||
914c2e77 | 2066 | int |
e1e2e653 NS |
2067 | mask64_1or2_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED, |
2068 | bool allow_one) | |
0ba1b2ff AM |
2069 | { |
2070 | if (GET_CODE (op) == CONST_INT) | |
a260abc9 | 2071 | { |
0ba1b2ff | 2072 | HOST_WIDE_INT c, lsb; |
e1e2e653 NS |
2073 | bool one_ok; |
2074 | ||
0ba1b2ff | 2075 | c = INTVAL (op); |
a260abc9 | 2076 | |
0ba1b2ff AM |
2077 | /* Disallow all zeros. */ |
2078 | if (c == 0) | |
2079 | return 0; | |
a260abc9 | 2080 | |
e1e2e653 NS |
2081 | /* We can use a single rlwinm insn if no upper bits of C are set |
2082 | AND there are zero, one or two transitions in the _whole_ of | |
2083 | C. */ | |
2084 | one_ok = !(c & ~(HOST_WIDE_INT)0xffffffff); | |
2085 | ||
0ba1b2ff AM |
2086 | /* We don't change the number of transitions by inverting, |
2087 | so make sure we start with the LS bit zero. */ | |
2088 | if (c & 1) | |
2089 | c = ~c; | |
a260abc9 | 2090 | |
0ba1b2ff AM |
2091 | /* Find the first transition. */ |
2092 | lsb = c & -c; | |
a260abc9 | 2093 | |
0ba1b2ff AM |
2094 | /* Invert to look for a second transition. */ |
2095 | c = ~c; | |
2096 | ||
2097 | /* Erase first transition. */ | |
2098 | c &= -lsb; | |
2099 | ||
2100 | /* Find the second transition. */ | |
2101 | lsb = c & -c; | |
2102 | ||
2103 | /* Invert to look for a third transition. */ | |
2104 | c = ~c; | |
2105 | ||
2106 | /* Erase second transition. */ | |
2107 | c &= -lsb; | |
2108 | ||
e1e2e653 NS |
2109 | if (one_ok && !(allow_one || c)) |
2110 | return 0; | |
2111 | ||
0ba1b2ff AM |
2112 | /* Find the third transition (if any). */ |
2113 | lsb = c & -c; | |
2114 | ||
2115 | /* Match if all the bits above are 1's (or c is zero). */ | |
2116 | return c == -lsb; | |
2117 | } | |
2118 | return 0; | |
2119 | } | |
2120 | ||
2121 | /* Generates shifts and masks for a pair of rldicl or rldicr insns to | |
2122 | implement ANDing by the mask IN. */ | |
2123 | void | |
a2369ed3 | 2124 | build_mask64_2_operands (rtx in, rtx *out) |
0ba1b2ff AM |
2125 | { |
2126 | #if HOST_BITS_PER_WIDE_INT >= 64 | |
2127 | unsigned HOST_WIDE_INT c, lsb, m1, m2; | |
2128 | int shift; | |
2129 | ||
2130 | if (GET_CODE (in) != CONST_INT) | |
2131 | abort (); | |
2132 | ||
2133 | c = INTVAL (in); | |
2134 | if (c & 1) | |
2135 | { | |
2136 | /* Assume c initially something like 0x00fff000000fffff. The idea | |
2137 | is to rotate the word so that the middle ^^^^^^ group of zeros | |
2138 | is at the MS end and can be cleared with an rldicl mask. We then | |
2139 | rotate back and clear off the MS ^^ group of zeros with a | |
2140 | second rldicl. */ | |
2141 | c = ~c; /* c == 0xff000ffffff00000 */ | |
2142 | lsb = c & -c; /* lsb == 0x0000000000100000 */ | |
2143 | m1 = -lsb; /* m1 == 0xfffffffffff00000 */ | |
2144 | c = ~c; /* c == 0x00fff000000fffff */ | |
2145 | c &= -lsb; /* c == 0x00fff00000000000 */ | |
2146 | lsb = c & -c; /* lsb == 0x0000100000000000 */ | |
2147 | c = ~c; /* c == 0xff000fffffffffff */ | |
2148 | c &= -lsb; /* c == 0xff00000000000000 */ | |
2149 | shift = 0; | |
2150 | while ((lsb >>= 1) != 0) | |
2151 | shift++; /* shift == 44 on exit from loop */ | |
2152 | m1 <<= 64 - shift; /* m1 == 0xffffff0000000000 */ | |
2153 | m1 = ~m1; /* m1 == 0x000000ffffffffff */ | |
2154 | m2 = ~c; /* m2 == 0x00ffffffffffffff */ | |
a260abc9 DE |
2155 | } |
2156 | else | |
0ba1b2ff AM |
2157 | { |
2158 | /* Assume c initially something like 0xff000f0000000000. The idea | |
2159 | is to rotate the word so that the ^^^ middle group of zeros | |
2160 | is at the LS end and can be cleared with an rldicr mask. We then | |
2161 | rotate back and clear off the LS group of ^^^^^^^^^^ zeros with | |
2162 | a second rldicr. */ | |
2163 | lsb = c & -c; /* lsb == 0x0000010000000000 */ | |
2164 | m2 = -lsb; /* m2 == 0xffffff0000000000 */ | |
2165 | c = ~c; /* c == 0x00fff0ffffffffff */ | |
2166 | c &= -lsb; /* c == 0x00fff00000000000 */ | |
2167 | lsb = c & -c; /* lsb == 0x0000100000000000 */ | |
2168 | c = ~c; /* c == 0xff000fffffffffff */ | |
2169 | c &= -lsb; /* c == 0xff00000000000000 */ | |
2170 | shift = 0; | |
2171 | while ((lsb >>= 1) != 0) | |
2172 | shift++; /* shift == 44 on exit from loop */ | |
2173 | m1 = ~c; /* m1 == 0x00ffffffffffffff */ | |
2174 | m1 >>= shift; /* m1 == 0x0000000000000fff */ | |
2175 | m1 = ~m1; /* m1 == 0xfffffffffffff000 */ | |
2176 | } | |
2177 | ||
2178 | /* Note that when we only have two 0->1 and 1->0 transitions, one of the | |
2179 | masks will be all 1's. We are guaranteed more than one transition. */ | |
2180 | out[0] = GEN_INT (64 - shift); | |
2181 | out[1] = GEN_INT (m1); | |
2182 | out[2] = GEN_INT (shift); | |
2183 | out[3] = GEN_INT (m2); | |
2184 | #else | |
045572c7 GK |
2185 | (void)in; |
2186 | (void)out; | |
0ba1b2ff AM |
2187 | abort (); |
2188 | #endif | |
a260abc9 DE |
2189 | } |
2190 | ||
54b695e7 | 2191 | /* Return TRUE if OP is an invalid SUBREG operation on the e500. */ |
48d72335 DE |
2192 | |
2193 | bool | |
54b695e7 AH |
2194 | invalid_e500_subreg (rtx op, enum machine_mode mode) |
2195 | { | |
2196 | /* Reject (subreg:SI (reg:DF)). */ | |
2197 | if (GET_CODE (op) == SUBREG | |
2198 | && mode == SImode | |
2199 | && REG_P (SUBREG_REG (op)) | |
2200 | && GET_MODE (SUBREG_REG (op)) == DFmode) | |
2201 | return true; | |
2202 | ||
2203 | /* Reject (subreg:DF (reg:DI)). */ | |
2204 | if (GET_CODE (op) == SUBREG | |
2205 | && mode == DFmode | |
2206 | && REG_P (SUBREG_REG (op)) | |
2207 | && GET_MODE (SUBREG_REG (op)) == DImode) | |
2208 | return true; | |
2209 | ||
2210 | return false; | |
2211 | } | |
2212 | ||
95727fb8 AP |
2213 | /* Darwin, AIX increases natural record alignment to doubleword if the first |
2214 | field is an FP double while the FP fields remain word aligned. */ | |
2215 | ||
19d66194 | 2216 | unsigned int |
95727fb8 AP |
2217 | rs6000_special_round_type_align (tree type, int computed, int specified) |
2218 | { | |
2219 | tree field = TYPE_FIELDS (type); | |
95727fb8 | 2220 | |
85962ac8 AP |
2221 | /* Skip all non field decls */ |
2222 | while (field != NULL && TREE_CODE (field) != FIELD_DECL) | |
95727fb8 AP |
2223 | field = TREE_CHAIN (field); |
2224 | ||
3ce5437a | 2225 | if (field == NULL || field == type || DECL_MODE (field) != DFmode) |
95727fb8 AP |
2226 | return MAX (computed, specified); |
2227 | ||
2228 | return MAX (MAX (computed, specified), 64); | |
2229 | } | |
2230 | ||
a4f6c312 | 2231 | /* Return 1 for an operand in small memory on V.4/eabi. */ |
7509c759 MM |
2232 | |
2233 | int | |
f676971a | 2234 | small_data_operand (rtx op ATTRIBUTE_UNUSED, |
a2369ed3 | 2235 | enum machine_mode mode ATTRIBUTE_UNUSED) |
7509c759 | 2236 | { |
38c1f2d7 | 2237 | #if TARGET_ELF |
5f59ecb7 | 2238 | rtx sym_ref; |
7509c759 | 2239 | |
d9407988 | 2240 | if (rs6000_sdata == SDATA_NONE || rs6000_sdata == SDATA_DATA) |
a54d04b7 | 2241 | return 0; |
a54d04b7 | 2242 | |
f607bc57 | 2243 | if (DEFAULT_ABI != ABI_V4) |
7509c759 MM |
2244 | return 0; |
2245 | ||
88228c4b MM |
2246 | if (GET_CODE (op) == SYMBOL_REF) |
2247 | sym_ref = op; | |
2248 | ||
2249 | else if (GET_CODE (op) != CONST | |
2250 | || GET_CODE (XEXP (op, 0)) != PLUS | |
2251 | || GET_CODE (XEXP (XEXP (op, 0), 0)) != SYMBOL_REF | |
2252 | || GET_CODE (XEXP (XEXP (op, 0), 1)) != CONST_INT) | |
7509c759 MM |
2253 | return 0; |
2254 | ||
88228c4b | 2255 | else |
dbf55e53 MM |
2256 | { |
2257 | rtx sum = XEXP (op, 0); | |
2258 | HOST_WIDE_INT summand; | |
2259 | ||
2260 | /* We have to be careful here, because it is the referenced address | |
c4ad648e | 2261 | that must be 32k from _SDA_BASE_, not just the symbol. */ |
dbf55e53 | 2262 | summand = INTVAL (XEXP (sum, 1)); |
307b599c | 2263 | if (summand < 0 || (unsigned HOST_WIDE_INT) summand > g_switch_value) |
dbf55e53 MM |
2264 | return 0; |
2265 | ||
2266 | sym_ref = XEXP (sum, 0); | |
2267 | } | |
88228c4b | 2268 | |
20bfcd69 | 2269 | return SYMBOL_REF_SMALL_P (sym_ref); |
d9407988 MM |
2270 | #else |
2271 | return 0; | |
2272 | #endif | |
7509c759 | 2273 | } |
46c07df8 | 2274 | |
d2288d5d HP |
2275 | /* Return true, if operand is a memory operand and has a |
2276 | displacement divisible by 4. */ | |
2277 | ||
2278 | int | |
2279 | word_offset_memref_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) | |
2280 | { | |
2281 | rtx addr; | |
2282 | int off = 0; | |
2283 | ||
2284 | if (!memory_operand (op, mode)) | |
2285 | return 0; | |
2286 | ||
2287 | addr = XEXP (op, 0); | |
2288 | if (GET_CODE (addr) == PLUS | |
2289 | && GET_CODE (XEXP (addr, 0)) == REG | |
2290 | && GET_CODE (XEXP (addr, 1)) == CONST_INT) | |
2291 | off = INTVAL (XEXP (addr, 1)); | |
2292 | ||
2293 | return (off % 4) == 0; | |
2294 | } | |
2295 | ||
3a1f863f | 2296 | /* Return true if either operand is a general purpose register. */ |
46c07df8 | 2297 | |
3a1f863f DE |
2298 | bool |
2299 | gpr_or_gpr_p (rtx op0, rtx op1) | |
46c07df8 | 2300 | { |
3a1f863f DE |
2301 | return ((REG_P (op0) && INT_REGNO_P (REGNO (op0))) |
2302 | || (REG_P (op1) && INT_REGNO_P (REGNO (op1)))); | |
46c07df8 HP |
2303 | } |
2304 | ||
9ebbca7d | 2305 | \f |
4d588c14 RH |
2306 | /* Subroutines of rs6000_legitimize_address and rs6000_legitimate_address. */ |
2307 | ||
f676971a EC |
2308 | static int |
2309 | constant_pool_expr_1 (rtx op, int *have_sym, int *have_toc) | |
9ebbca7d | 2310 | { |
f676971a | 2311 | switch (GET_CODE(op)) |
9ebbca7d GK |
2312 | { |
2313 | case SYMBOL_REF: | |
c4501e62 JJ |
2314 | if (RS6000_SYMBOL_REF_TLS_P (op)) |
2315 | return 0; | |
2316 | else if (CONSTANT_POOL_ADDRESS_P (op)) | |
a4f6c312 SS |
2317 | { |
2318 | if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (op), Pmode)) | |
2319 | { | |
2320 | *have_sym = 1; | |
2321 | return 1; | |
2322 | } | |
2323 | else | |
2324 | return 0; | |
2325 | } | |
2326 | else if (! strcmp (XSTR (op, 0), toc_label_name)) | |
2327 | { | |
2328 | *have_toc = 1; | |
2329 | return 1; | |
2330 | } | |
2331 | else | |
2332 | return 0; | |
9ebbca7d GK |
2333 | case PLUS: |
2334 | case MINUS: | |
c1f11548 DE |
2335 | return (constant_pool_expr_1 (XEXP (op, 0), have_sym, have_toc) |
2336 | && constant_pool_expr_1 (XEXP (op, 1), have_sym, have_toc)); | |
9ebbca7d | 2337 | case CONST: |
a4f6c312 | 2338 | return constant_pool_expr_1 (XEXP (op, 0), have_sym, have_toc); |
9ebbca7d | 2339 | case CONST_INT: |
a4f6c312 | 2340 | return 1; |
9ebbca7d | 2341 | default: |
a4f6c312 | 2342 | return 0; |
9ebbca7d GK |
2343 | } |
2344 | } | |
2345 | ||
4d588c14 | 2346 | static bool |
a2369ed3 | 2347 | constant_pool_expr_p (rtx op) |
9ebbca7d GK |
2348 | { |
2349 | int have_sym = 0; | |
2350 | int have_toc = 0; | |
2351 | return constant_pool_expr_1 (op, &have_sym, &have_toc) && have_sym; | |
2352 | } | |
2353 | ||
48d72335 | 2354 | bool |
a2369ed3 | 2355 | toc_relative_expr_p (rtx op) |
9ebbca7d | 2356 | { |
4d588c14 RH |
2357 | int have_sym = 0; |
2358 | int have_toc = 0; | |
2359 | return constant_pool_expr_1 (op, &have_sym, &have_toc) && have_toc; | |
2360 | } | |
2361 | ||
4d588c14 | 2362 | bool |
a2369ed3 | 2363 | legitimate_constant_pool_address_p (rtx x) |
4d588c14 RH |
2364 | { |
2365 | return (TARGET_TOC | |
2366 | && GET_CODE (x) == PLUS | |
2367 | && GET_CODE (XEXP (x, 0)) == REG | |
2368 | && (TARGET_MINIMAL_TOC || REGNO (XEXP (x, 0)) == TOC_REGISTER) | |
2369 | && constant_pool_expr_p (XEXP (x, 1))); | |
2370 | } | |
2371 | ||
2372 | static bool | |
a2369ed3 | 2373 | legitimate_small_data_p (enum machine_mode mode, rtx x) |
4d588c14 RH |
2374 | { |
2375 | return (DEFAULT_ABI == ABI_V4 | |
2376 | && !flag_pic && !TARGET_TOC | |
2377 | && (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST) | |
2378 | && small_data_operand (x, mode)); | |
2379 | } | |
2380 | ||
60cdabab DE |
2381 | /* SPE offset addressing is limited to 5-bits worth of double words. */ |
2382 | #define SPE_CONST_OFFSET_OK(x) (((x) & ~0xf8) == 0) | |
2383 | ||
76d2b81d DJ |
2384 | bool |
2385 | rs6000_legitimate_offset_address_p (enum machine_mode mode, rtx x, int strict) | |
4d588c14 RH |
2386 | { |
2387 | unsigned HOST_WIDE_INT offset, extra; | |
2388 | ||
2389 | if (GET_CODE (x) != PLUS) | |
2390 | return false; | |
2391 | if (GET_CODE (XEXP (x, 0)) != REG) | |
2392 | return false; | |
2393 | if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict)) | |
2394 | return false; | |
60cdabab DE |
2395 | if (legitimate_constant_pool_address_p (x)) |
2396 | return true; | |
4d588c14 RH |
2397 | if (GET_CODE (XEXP (x, 1)) != CONST_INT) |
2398 | return false; | |
2399 | ||
2400 | offset = INTVAL (XEXP (x, 1)); | |
2401 | extra = 0; | |
2402 | switch (mode) | |
2403 | { | |
2404 | case V16QImode: | |
2405 | case V8HImode: | |
2406 | case V4SFmode: | |
2407 | case V4SImode: | |
2408 | /* AltiVec vector modes. Only reg+reg addressing is valid here, | |
2409 | which leaves the only valid constant offset of zero, which by | |
2410 | canonicalization rules is also invalid. */ | |
2411 | return false; | |
2412 | ||
2413 | case V4HImode: | |
2414 | case V2SImode: | |
2415 | case V1DImode: | |
2416 | case V2SFmode: | |
2417 | /* SPE vector modes. */ | |
2418 | return SPE_CONST_OFFSET_OK (offset); | |
2419 | ||
2420 | case DFmode: | |
4d4cbc0e AH |
2421 | if (TARGET_E500_DOUBLE) |
2422 | return SPE_CONST_OFFSET_OK (offset); | |
2423 | ||
4d588c14 | 2424 | case DImode: |
54b695e7 AH |
2425 | /* On e500v2, we may have: |
2426 | ||
2427 | (subreg:DF (mem:DI (plus (reg) (const_int))) 0). | |
2428 | ||
2429 | Which gets addressed with evldd instructions. */ | |
2430 | if (TARGET_E500_DOUBLE) | |
2431 | return SPE_CONST_OFFSET_OK (offset); | |
2432 | ||
3364872d | 2433 | if (mode == DFmode || !TARGET_POWERPC64) |
4d588c14 RH |
2434 | extra = 4; |
2435 | else if (offset & 3) | |
2436 | return false; | |
2437 | break; | |
2438 | ||
2439 | case TFmode: | |
2440 | case TImode: | |
3364872d | 2441 | if (mode == TFmode || !TARGET_POWERPC64) |
4d588c14 RH |
2442 | extra = 12; |
2443 | else if (offset & 3) | |
2444 | return false; | |
2445 | else | |
2446 | extra = 8; | |
2447 | break; | |
2448 | ||
2449 | default: | |
2450 | break; | |
2451 | } | |
2452 | ||
b1917422 AM |
2453 | offset += 0x8000; |
2454 | return (offset < 0x10000) && (offset + extra < 0x10000); | |
4d588c14 RH |
2455 | } |
2456 | ||
2457 | static bool | |
a2369ed3 | 2458 | legitimate_indexed_address_p (rtx x, int strict) |
4d588c14 RH |
2459 | { |
2460 | rtx op0, op1; | |
2461 | ||
2462 | if (GET_CODE (x) != PLUS) | |
2463 | return false; | |
850e8d3d | 2464 | |
4d588c14 RH |
2465 | op0 = XEXP (x, 0); |
2466 | op1 = XEXP (x, 1); | |
2467 | ||
2468 | if (!REG_P (op0) || !REG_P (op1)) | |
2469 | return false; | |
2470 | ||
2471 | return ((INT_REG_OK_FOR_BASE_P (op0, strict) | |
2472 | && INT_REG_OK_FOR_INDEX_P (op1, strict)) | |
2473 | || (INT_REG_OK_FOR_BASE_P (op1, strict) | |
2474 | && INT_REG_OK_FOR_INDEX_P (op0, strict))); | |
9ebbca7d GK |
2475 | } |
2476 | ||
48d72335 | 2477 | inline bool |
a2369ed3 | 2478 | legitimate_indirect_address_p (rtx x, int strict) |
4d588c14 RH |
2479 | { |
2480 | return GET_CODE (x) == REG && INT_REG_OK_FOR_BASE_P (x, strict); | |
2481 | } | |
2482 | ||
48d72335 | 2483 | bool |
4c81e946 FJ |
2484 | macho_lo_sum_memory_operand (rtx x, enum machine_mode mode) |
2485 | { | |
c4ad648e AM |
2486 | if (!TARGET_MACHO || !flag_pic |
2487 | || mode != SImode || GET_CODE(x) != MEM) | |
2488 | return false; | |
2489 | x = XEXP (x, 0); | |
4c81e946 FJ |
2490 | |
2491 | if (GET_CODE (x) != LO_SUM) | |
2492 | return false; | |
2493 | if (GET_CODE (XEXP (x, 0)) != REG) | |
2494 | return false; | |
2495 | if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), 0)) | |
2496 | return false; | |
2497 | x = XEXP (x, 1); | |
2498 | ||
2499 | return CONSTANT_P (x); | |
2500 | } | |
2501 | ||
4d588c14 | 2502 | static bool |
a2369ed3 | 2503 | legitimate_lo_sum_address_p (enum machine_mode mode, rtx x, int strict) |
4d588c14 RH |
2504 | { |
2505 | if (GET_CODE (x) != LO_SUM) | |
2506 | return false; | |
2507 | if (GET_CODE (XEXP (x, 0)) != REG) | |
2508 | return false; | |
2509 | if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict)) | |
2510 | return false; | |
54b695e7 AH |
2511 | /* Restrict addressing for DI because of our SUBREG hackery. */ |
2512 | if (TARGET_E500_DOUBLE && (mode == DFmode || mode == DImode)) | |
f82f556d | 2513 | return false; |
4d588c14 RH |
2514 | x = XEXP (x, 1); |
2515 | ||
8622e235 | 2516 | if (TARGET_ELF || TARGET_MACHO) |
4d588c14 | 2517 | { |
a29077da | 2518 | if (DEFAULT_ABI != ABI_AIX && DEFAULT_ABI != ABI_DARWIN && flag_pic) |
4d588c14 RH |
2519 | return false; |
2520 | if (TARGET_TOC) | |
2521 | return false; | |
2522 | if (GET_MODE_NUNITS (mode) != 1) | |
2523 | return false; | |
5e5f01b9 | 2524 | if (GET_MODE_BITSIZE (mode) > 64 |
3c028f65 AM |
2525 | || (GET_MODE_BITSIZE (mode) > 32 && !TARGET_POWERPC64 |
2526 | && !(TARGET_HARD_FLOAT && TARGET_FPRS && mode == DFmode))) | |
4d588c14 RH |
2527 | return false; |
2528 | ||
2529 | return CONSTANT_P (x); | |
2530 | } | |
2531 | ||
2532 | return false; | |
2533 | } | |
2534 | ||
2535 | ||
9ebbca7d GK |
2536 | /* Try machine-dependent ways of modifying an illegitimate address |
2537 | to be legitimate. If we find one, return the new, valid address. | |
2538 | This is used from only one place: `memory_address' in explow.c. | |
2539 | ||
a4f6c312 SS |
2540 | OLDX is the address as it was before break_out_memory_refs was |
2541 | called. In some cases it is useful to look at this to decide what | |
2542 | needs to be done. | |
9ebbca7d | 2543 | |
a4f6c312 | 2544 | MODE is passed so that this function can use GO_IF_LEGITIMATE_ADDRESS. |
9ebbca7d | 2545 | |
a4f6c312 SS |
2546 | It is always safe for this function to do nothing. It exists to |
2547 | recognize opportunities to optimize the output. | |
9ebbca7d GK |
2548 | |
2549 | On RS/6000, first check for the sum of a register with a constant | |
2550 | integer that is out of range. If so, generate code to add the | |
2551 | constant with the low-order 16 bits masked to the register and force | |
2552 | this result into another register (this can be done with `cau'). | |
2553 | Then generate an address of REG+(CONST&0xffff), allowing for the | |
2554 | possibility of bit 16 being a one. | |
2555 | ||
2556 | Then check for the sum of a register and something not constant, try to | |
2557 | load the other things into a register and return the sum. */ | |
4d588c14 | 2558 | |
9ebbca7d | 2559 | rtx |
a2369ed3 DJ |
2560 | rs6000_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED, |
2561 | enum machine_mode mode) | |
0ac081f6 | 2562 | { |
c4501e62 JJ |
2563 | if (GET_CODE (x) == SYMBOL_REF) |
2564 | { | |
2565 | enum tls_model model = SYMBOL_REF_TLS_MODEL (x); | |
2566 | if (model != 0) | |
2567 | return rs6000_legitimize_tls_address (x, model); | |
2568 | } | |
2569 | ||
f676971a | 2570 | if (GET_CODE (x) == PLUS |
9ebbca7d GK |
2571 | && GET_CODE (XEXP (x, 0)) == REG |
2572 | && GET_CODE (XEXP (x, 1)) == CONST_INT | |
2573 | && (unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 1)) + 0x8000) >= 0x10000) | |
f676971a | 2574 | { |
9ebbca7d GK |
2575 | HOST_WIDE_INT high_int, low_int; |
2576 | rtx sum; | |
a65c591c DE |
2577 | low_int = ((INTVAL (XEXP (x, 1)) & 0xffff) ^ 0x8000) - 0x8000; |
2578 | high_int = INTVAL (XEXP (x, 1)) - low_int; | |
9ebbca7d GK |
2579 | sum = force_operand (gen_rtx_PLUS (Pmode, XEXP (x, 0), |
2580 | GEN_INT (high_int)), 0); | |
2581 | return gen_rtx_PLUS (Pmode, sum, GEN_INT (low_int)); | |
2582 | } | |
f676971a | 2583 | else if (GET_CODE (x) == PLUS |
9ebbca7d GK |
2584 | && GET_CODE (XEXP (x, 0)) == REG |
2585 | && GET_CODE (XEXP (x, 1)) != CONST_INT | |
6ac7bf2c | 2586 | && GET_MODE_NUNITS (mode) == 1 |
a3170dc6 AH |
2587 | && ((TARGET_HARD_FLOAT && TARGET_FPRS) |
2588 | || TARGET_POWERPC64 | |
54b695e7 AH |
2589 | || (((mode != DImode && mode != DFmode) || TARGET_E500_DOUBLE) |
2590 | && mode != TFmode)) | |
9ebbca7d GK |
2591 | && (TARGET_POWERPC64 || mode != DImode) |
2592 | && mode != TImode) | |
2593 | { | |
2594 | return gen_rtx_PLUS (Pmode, XEXP (x, 0), | |
2595 | force_reg (Pmode, force_operand (XEXP (x, 1), 0))); | |
2596 | } | |
0ac081f6 AH |
2597 | else if (ALTIVEC_VECTOR_MODE (mode)) |
2598 | { | |
2599 | rtx reg; | |
2600 | ||
2601 | /* Make sure both operands are registers. */ | |
2602 | if (GET_CODE (x) == PLUS) | |
9f85ed45 | 2603 | return gen_rtx_PLUS (Pmode, force_reg (Pmode, XEXP (x, 0)), |
0ac081f6 AH |
2604 | force_reg (Pmode, XEXP (x, 1))); |
2605 | ||
2606 | reg = force_reg (Pmode, x); | |
2607 | return reg; | |
2608 | } | |
4d4cbc0e | 2609 | else if (SPE_VECTOR_MODE (mode) |
54b695e7 AH |
2610 | || (TARGET_E500_DOUBLE && (mode == DFmode |
2611 | || mode == DImode))) | |
a3170dc6 | 2612 | { |
54b695e7 AH |
2613 | if (mode == DImode) |
2614 | return NULL_RTX; | |
a3170dc6 AH |
2615 | /* We accept [reg + reg] and [reg + OFFSET]. */ |
2616 | ||
2617 | if (GET_CODE (x) == PLUS) | |
c4ad648e AM |
2618 | { |
2619 | rtx op1 = XEXP (x, 0); | |
2620 | rtx op2 = XEXP (x, 1); | |
a3170dc6 | 2621 | |
c4ad648e | 2622 | op1 = force_reg (Pmode, op1); |
a3170dc6 | 2623 | |
c4ad648e AM |
2624 | if (GET_CODE (op2) != REG |
2625 | && (GET_CODE (op2) != CONST_INT | |
2626 | || !SPE_CONST_OFFSET_OK (INTVAL (op2)))) | |
2627 | op2 = force_reg (Pmode, op2); | |
a3170dc6 | 2628 | |
c4ad648e AM |
2629 | return gen_rtx_PLUS (Pmode, op1, op2); |
2630 | } | |
a3170dc6 AH |
2631 | |
2632 | return force_reg (Pmode, x); | |
2633 | } | |
f1384257 AM |
2634 | else if (TARGET_ELF |
2635 | && TARGET_32BIT | |
2636 | && TARGET_NO_TOC | |
2637 | && ! flag_pic | |
9ebbca7d | 2638 | && GET_CODE (x) != CONST_INT |
f676971a | 2639 | && GET_CODE (x) != CONST_DOUBLE |
9ebbca7d | 2640 | && CONSTANT_P (x) |
6ac7bf2c GK |
2641 | && GET_MODE_NUNITS (mode) == 1 |
2642 | && (GET_MODE_BITSIZE (mode) <= 32 | |
a3170dc6 | 2643 | || ((TARGET_HARD_FLOAT && TARGET_FPRS) && mode == DFmode))) |
9ebbca7d GK |
2644 | { |
2645 | rtx reg = gen_reg_rtx (Pmode); | |
8a1977f3 GK |
2646 | emit_insn (gen_elf_high (reg, x)); |
2647 | return gen_rtx_LO_SUM (Pmode, reg, x); | |
9ebbca7d | 2648 | } |
ee890fe2 SS |
2649 | else if (TARGET_MACHO && TARGET_32BIT && TARGET_NO_TOC |
2650 | && ! flag_pic | |
ab82a49f AP |
2651 | #if TARGET_MACHO |
2652 | && ! MACHO_DYNAMIC_NO_PIC_P | |
2653 | #endif | |
ee890fe2 | 2654 | && GET_CODE (x) != CONST_INT |
f676971a | 2655 | && GET_CODE (x) != CONST_DOUBLE |
ee890fe2 | 2656 | && CONSTANT_P (x) |
f82f556d | 2657 | && ((TARGET_HARD_FLOAT && TARGET_FPRS) || mode != DFmode) |
f676971a | 2658 | && mode != DImode |
ee890fe2 SS |
2659 | && mode != TImode) |
2660 | { | |
2661 | rtx reg = gen_reg_rtx (Pmode); | |
8a1977f3 GK |
2662 | emit_insn (gen_macho_high (reg, x)); |
2663 | return gen_rtx_LO_SUM (Pmode, reg, x); | |
ee890fe2 | 2664 | } |
f676971a | 2665 | else if (TARGET_TOC |
4d588c14 | 2666 | && constant_pool_expr_p (x) |
a9098fd0 | 2667 | && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x), Pmode)) |
9ebbca7d GK |
2668 | { |
2669 | return create_TOC_reference (x); | |
2670 | } | |
2671 | else | |
2672 | return NULL_RTX; | |
2673 | } | |
258bfae2 | 2674 | |
c973d557 JJ |
2675 | /* This is called from dwarf2out.c via ASM_OUTPUT_DWARF_DTPREL. |
2676 | We need to emit DTP-relative relocations. */ | |
2677 | ||
2678 | void | |
2679 | rs6000_output_dwarf_dtprel (FILE *file, int size, rtx x) | |
2680 | { | |
2681 | switch (size) | |
2682 | { | |
2683 | case 4: | |
2684 | fputs ("\t.long\t", file); | |
2685 | break; | |
2686 | case 8: | |
2687 | fputs (DOUBLE_INT_ASM_OP, file); | |
2688 | break; | |
2689 | default: | |
2690 | abort (); | |
2691 | } | |
2692 | output_addr_const (file, x); | |
2693 | fputs ("@dtprel+0x8000", file); | |
2694 | } | |
2695 | ||
c4501e62 JJ |
2696 | /* Construct the SYMBOL_REF for the tls_get_addr function. */ |
2697 | ||
2698 | static GTY(()) rtx rs6000_tls_symbol; | |
2699 | static rtx | |
863d938c | 2700 | rs6000_tls_get_addr (void) |
c4501e62 JJ |
2701 | { |
2702 | if (!rs6000_tls_symbol) | |
2703 | rs6000_tls_symbol = init_one_libfunc ("__tls_get_addr"); | |
2704 | ||
2705 | return rs6000_tls_symbol; | |
2706 | } | |
2707 | ||
2708 | /* Construct the SYMBOL_REF for TLS GOT references. */ | |
2709 | ||
2710 | static GTY(()) rtx rs6000_got_symbol; | |
2711 | static rtx | |
863d938c | 2712 | rs6000_got_sym (void) |
c4501e62 JJ |
2713 | { |
2714 | if (!rs6000_got_symbol) | |
2715 | { | |
2716 | rs6000_got_symbol = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_"); | |
2717 | SYMBOL_REF_FLAGS (rs6000_got_symbol) |= SYMBOL_FLAG_LOCAL; | |
2718 | SYMBOL_REF_FLAGS (rs6000_got_symbol) |= SYMBOL_FLAG_EXTERNAL; | |
f676971a | 2719 | } |
c4501e62 JJ |
2720 | |
2721 | return rs6000_got_symbol; | |
2722 | } | |
2723 | ||
2724 | /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute | |
2725 | this (thread-local) address. */ | |
2726 | ||
2727 | static rtx | |
a2369ed3 | 2728 | rs6000_legitimize_tls_address (rtx addr, enum tls_model model) |
c4501e62 JJ |
2729 | { |
2730 | rtx dest, insn; | |
2731 | ||
2732 | dest = gen_reg_rtx (Pmode); | |
2733 | if (model == TLS_MODEL_LOCAL_EXEC && rs6000_tls_size == 16) | |
2734 | { | |
2735 | rtx tlsreg; | |
2736 | ||
2737 | if (TARGET_64BIT) | |
2738 | { | |
2739 | tlsreg = gen_rtx_REG (Pmode, 13); | |
2740 | insn = gen_tls_tprel_64 (dest, tlsreg, addr); | |
2741 | } | |
2742 | else | |
2743 | { | |
2744 | tlsreg = gen_rtx_REG (Pmode, 2); | |
2745 | insn = gen_tls_tprel_32 (dest, tlsreg, addr); | |
2746 | } | |
2747 | emit_insn (insn); | |
2748 | } | |
2749 | else if (model == TLS_MODEL_LOCAL_EXEC && rs6000_tls_size == 32) | |
2750 | { | |
2751 | rtx tlsreg, tmp; | |
2752 | ||
2753 | tmp = gen_reg_rtx (Pmode); | |
2754 | if (TARGET_64BIT) | |
2755 | { | |
2756 | tlsreg = gen_rtx_REG (Pmode, 13); | |
2757 | insn = gen_tls_tprel_ha_64 (tmp, tlsreg, addr); | |
2758 | } | |
2759 | else | |
2760 | { | |
2761 | tlsreg = gen_rtx_REG (Pmode, 2); | |
2762 | insn = gen_tls_tprel_ha_32 (tmp, tlsreg, addr); | |
2763 | } | |
2764 | emit_insn (insn); | |
2765 | if (TARGET_64BIT) | |
2766 | insn = gen_tls_tprel_lo_64 (dest, tmp, addr); | |
2767 | else | |
2768 | insn = gen_tls_tprel_lo_32 (dest, tmp, addr); | |
2769 | emit_insn (insn); | |
2770 | } | |
2771 | else | |
2772 | { | |
2773 | rtx r3, got, tga, tmp1, tmp2, eqv; | |
2774 | ||
2775 | if (TARGET_64BIT) | |
2776 | got = gen_rtx_REG (Pmode, TOC_REGISTER); | |
2777 | else | |
2778 | { | |
2779 | if (flag_pic == 1) | |
2780 | got = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM); | |
2781 | else | |
2782 | { | |
2783 | rtx gsym = rs6000_got_sym (); | |
2784 | got = gen_reg_rtx (Pmode); | |
2785 | if (flag_pic == 0) | |
2786 | rs6000_emit_move (got, gsym, Pmode); | |
2787 | else | |
2788 | { | |
2789 | char buf[30]; | |
2790 | static int tls_got_labelno = 0; | |
2791 | rtx tempLR, lab, tmp3, mem; | |
2792 | rtx first, last; | |
2793 | ||
2794 | ASM_GENERATE_INTERNAL_LABEL (buf, "LTLS", tls_got_labelno++); | |
2795 | lab = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); | |
2796 | tempLR = gen_reg_rtx (Pmode); | |
2797 | tmp1 = gen_reg_rtx (Pmode); | |
2798 | tmp2 = gen_reg_rtx (Pmode); | |
2799 | tmp3 = gen_reg_rtx (Pmode); | |
542a8afa | 2800 | mem = gen_const_mem (Pmode, tmp1); |
c4501e62 JJ |
2801 | |
2802 | first = emit_insn (gen_load_toc_v4_PIC_1b (tempLR, lab, | |
2803 | gsym)); | |
2804 | emit_move_insn (tmp1, tempLR); | |
2805 | emit_move_insn (tmp2, mem); | |
2806 | emit_insn (gen_addsi3 (tmp3, tmp1, tmp2)); | |
2807 | last = emit_move_insn (got, tmp3); | |
2808 | REG_NOTES (last) = gen_rtx_EXPR_LIST (REG_EQUAL, gsym, | |
2809 | REG_NOTES (last)); | |
2810 | REG_NOTES (first) = gen_rtx_INSN_LIST (REG_LIBCALL, last, | |
2811 | REG_NOTES (first)); | |
2812 | REG_NOTES (last) = gen_rtx_INSN_LIST (REG_RETVAL, first, | |
2813 | REG_NOTES (last)); | |
2814 | } | |
2815 | } | |
2816 | } | |
2817 | ||
2818 | if (model == TLS_MODEL_GLOBAL_DYNAMIC) | |
2819 | { | |
2820 | r3 = gen_rtx_REG (Pmode, 3); | |
2821 | if (TARGET_64BIT) | |
2822 | insn = gen_tls_gd_64 (r3, got, addr); | |
2823 | else | |
2824 | insn = gen_tls_gd_32 (r3, got, addr); | |
2825 | start_sequence (); | |
2826 | emit_insn (insn); | |
2827 | tga = gen_rtx_MEM (Pmode, rs6000_tls_get_addr ()); | |
2828 | insn = gen_call_value (r3, tga, const0_rtx, const0_rtx); | |
2829 | insn = emit_call_insn (insn); | |
2830 | CONST_OR_PURE_CALL_P (insn) = 1; | |
2831 | use_reg (&CALL_INSN_FUNCTION_USAGE (insn), r3); | |
2832 | insn = get_insns (); | |
2833 | end_sequence (); | |
2834 | emit_libcall_block (insn, dest, r3, addr); | |
2835 | } | |
2836 | else if (model == TLS_MODEL_LOCAL_DYNAMIC) | |
2837 | { | |
2838 | r3 = gen_rtx_REG (Pmode, 3); | |
2839 | if (TARGET_64BIT) | |
2840 | insn = gen_tls_ld_64 (r3, got); | |
2841 | else | |
2842 | insn = gen_tls_ld_32 (r3, got); | |
2843 | start_sequence (); | |
2844 | emit_insn (insn); | |
2845 | tga = gen_rtx_MEM (Pmode, rs6000_tls_get_addr ()); | |
2846 | insn = gen_call_value (r3, tga, const0_rtx, const0_rtx); | |
2847 | insn = emit_call_insn (insn); | |
2848 | CONST_OR_PURE_CALL_P (insn) = 1; | |
2849 | use_reg (&CALL_INSN_FUNCTION_USAGE (insn), r3); | |
2850 | insn = get_insns (); | |
2851 | end_sequence (); | |
2852 | tmp1 = gen_reg_rtx (Pmode); | |
2853 | eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), | |
2854 | UNSPEC_TLSLD); | |
2855 | emit_libcall_block (insn, tmp1, r3, eqv); | |
2856 | if (rs6000_tls_size == 16) | |
2857 | { | |
2858 | if (TARGET_64BIT) | |
2859 | insn = gen_tls_dtprel_64 (dest, tmp1, addr); | |
2860 | else | |
2861 | insn = gen_tls_dtprel_32 (dest, tmp1, addr); | |
2862 | } | |
2863 | else if (rs6000_tls_size == 32) | |
2864 | { | |
2865 | tmp2 = gen_reg_rtx (Pmode); | |
2866 | if (TARGET_64BIT) | |
2867 | insn = gen_tls_dtprel_ha_64 (tmp2, tmp1, addr); | |
2868 | else | |
2869 | insn = gen_tls_dtprel_ha_32 (tmp2, tmp1, addr); | |
2870 | emit_insn (insn); | |
2871 | if (TARGET_64BIT) | |
2872 | insn = gen_tls_dtprel_lo_64 (dest, tmp2, addr); | |
2873 | else | |
2874 | insn = gen_tls_dtprel_lo_32 (dest, tmp2, addr); | |
2875 | } | |
2876 | else | |
2877 | { | |
2878 | tmp2 = gen_reg_rtx (Pmode); | |
2879 | if (TARGET_64BIT) | |
2880 | insn = gen_tls_got_dtprel_64 (tmp2, got, addr); | |
2881 | else | |
2882 | insn = gen_tls_got_dtprel_32 (tmp2, got, addr); | |
2883 | emit_insn (insn); | |
2884 | insn = gen_rtx_SET (Pmode, dest, | |
2885 | gen_rtx_PLUS (Pmode, tmp2, tmp1)); | |
2886 | } | |
2887 | emit_insn (insn); | |
2888 | } | |
2889 | else | |
2890 | { | |
2891 | /* IE, or 64 bit offset LE. */ | |
2892 | tmp2 = gen_reg_rtx (Pmode); | |
2893 | if (TARGET_64BIT) | |
2894 | insn = gen_tls_got_tprel_64 (tmp2, got, addr); | |
2895 | else | |
2896 | insn = gen_tls_got_tprel_32 (tmp2, got, addr); | |
2897 | emit_insn (insn); | |
2898 | if (TARGET_64BIT) | |
2899 | insn = gen_tls_tls_64 (dest, tmp2, addr); | |
2900 | else | |
2901 | insn = gen_tls_tls_32 (dest, tmp2, addr); | |
2902 | emit_insn (insn); | |
2903 | } | |
2904 | } | |
2905 | ||
2906 | return dest; | |
2907 | } | |
2908 | ||
c4501e62 JJ |
2909 | /* Return 1 if X contains a thread-local symbol. */ |
2910 | ||
2911 | bool | |
a2369ed3 | 2912 | rs6000_tls_referenced_p (rtx x) |
c4501e62 | 2913 | { |
cd413cab AP |
2914 | if (! TARGET_HAVE_TLS) |
2915 | return false; | |
2916 | ||
c4501e62 JJ |
2917 | return for_each_rtx (&x, &rs6000_tls_symbol_ref_1, 0); |
2918 | } | |
2919 | ||
2920 | /* Return 1 if *X is a thread-local symbol. This is the same as | |
2921 | rs6000_tls_symbol_ref except for the type of the unused argument. */ | |
2922 | ||
2923 | static inline int | |
a2369ed3 | 2924 | rs6000_tls_symbol_ref_1 (rtx *x, void *data ATTRIBUTE_UNUSED) |
c4501e62 JJ |
2925 | { |
2926 | return RS6000_SYMBOL_REF_TLS_P (*x); | |
2927 | } | |
2928 | ||
24ea750e DJ |
2929 | /* The convention appears to be to define this wherever it is used. |
2930 | With legitimize_reload_address now defined here, REG_MODE_OK_FOR_BASE_P | |
2931 | is now used here. */ | |
2932 | #ifndef REG_MODE_OK_FOR_BASE_P | |
2933 | #define REG_MODE_OK_FOR_BASE_P(REGNO, MODE) REG_OK_FOR_BASE_P (REGNO) | |
2934 | #endif | |
2935 | ||
2936 | /* Our implementation of LEGITIMIZE_RELOAD_ADDRESS. Returns a value to | |
2937 | replace the input X, or the original X if no replacement is called for. | |
2938 | The output parameter *WIN is 1 if the calling macro should goto WIN, | |
2939 | 0 if it should not. | |
2940 | ||
2941 | For RS/6000, we wish to handle large displacements off a base | |
2942 | register by splitting the addend across an addiu/addis and the mem insn. | |
2943 | This cuts number of extra insns needed from 3 to 1. | |
2944 | ||
2945 | On Darwin, we use this to generate code for floating point constants. | |
2946 | A movsf_low is generated so we wind up with 2 instructions rather than 3. | |
2947 | The Darwin code is inside #if TARGET_MACHO because only then is | |
2948 | machopic_function_base_name() defined. */ | |
2949 | rtx | |
f676971a | 2950 | rs6000_legitimize_reload_address (rtx x, enum machine_mode mode, |
c4ad648e AM |
2951 | int opnum, int type, |
2952 | int ind_levels ATTRIBUTE_UNUSED, int *win) | |
24ea750e | 2953 | { |
f676971a | 2954 | /* We must recognize output that we have already generated ourselves. */ |
24ea750e DJ |
2955 | if (GET_CODE (x) == PLUS |
2956 | && GET_CODE (XEXP (x, 0)) == PLUS | |
2957 | && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG | |
2958 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT | |
2959 | && GET_CODE (XEXP (x, 1)) == CONST_INT) | |
2960 | { | |
2961 | push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL, | |
c4ad648e AM |
2962 | BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0, |
2963 | opnum, (enum reload_type)type); | |
24ea750e DJ |
2964 | *win = 1; |
2965 | return x; | |
2966 | } | |
3deb2758 | 2967 | |
24ea750e DJ |
2968 | #if TARGET_MACHO |
2969 | if (DEFAULT_ABI == ABI_DARWIN && flag_pic | |
2970 | && GET_CODE (x) == LO_SUM | |
2971 | && GET_CODE (XEXP (x, 0)) == PLUS | |
2972 | && XEXP (XEXP (x, 0), 0) == pic_offset_table_rtx | |
2973 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == HIGH | |
2974 | && GET_CODE (XEXP (XEXP (XEXP (x, 0), 1), 0)) == CONST | |
2975 | && XEXP (XEXP (XEXP (x, 0), 1), 0) == XEXP (x, 1) | |
2976 | && GET_CODE (XEXP (XEXP (x, 1), 0)) == MINUS | |
2977 | && GET_CODE (XEXP (XEXP (XEXP (x, 1), 0), 0)) == SYMBOL_REF | |
2978 | && GET_CODE (XEXP (XEXP (XEXP (x, 1), 0), 1)) == SYMBOL_REF) | |
2979 | { | |
2980 | /* Result of previous invocation of this function on Darwin | |
6f317ef3 | 2981 | floating point constant. */ |
24ea750e | 2982 | push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL, |
c4ad648e AM |
2983 | BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, |
2984 | opnum, (enum reload_type)type); | |
24ea750e DJ |
2985 | *win = 1; |
2986 | return x; | |
2987 | } | |
2988 | #endif | |
4937d02d DE |
2989 | |
2990 | /* Force ld/std non-word aligned offset into base register by wrapping | |
2991 | in offset 0. */ | |
2992 | if (GET_CODE (x) == PLUS | |
2993 | && GET_CODE (XEXP (x, 0)) == REG | |
2994 | && REGNO (XEXP (x, 0)) < 32 | |
2995 | && REG_MODE_OK_FOR_BASE_P (XEXP (x, 0), mode) | |
2996 | && GET_CODE (XEXP (x, 1)) == CONST_INT | |
2997 | && (INTVAL (XEXP (x, 1)) & 3) != 0 | |
78796ad5 | 2998 | && !ALTIVEC_VECTOR_MODE (mode) |
4937d02d DE |
2999 | && GET_MODE_SIZE (mode) >= UNITS_PER_WORD |
3000 | && TARGET_POWERPC64) | |
3001 | { | |
3002 | x = gen_rtx_PLUS (GET_MODE (x), x, GEN_INT (0)); | |
3003 | push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL, | |
3004 | BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0, | |
3005 | opnum, (enum reload_type) type); | |
3006 | *win = 1; | |
3007 | return x; | |
3008 | } | |
3009 | ||
24ea750e DJ |
3010 | if (GET_CODE (x) == PLUS |
3011 | && GET_CODE (XEXP (x, 0)) == REG | |
3012 | && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER | |
3013 | && REG_MODE_OK_FOR_BASE_P (XEXP (x, 0), mode) | |
78c875e8 | 3014 | && GET_CODE (XEXP (x, 1)) == CONST_INT |
93638d7a | 3015 | && !SPE_VECTOR_MODE (mode) |
54b695e7 AH |
3016 | && !(TARGET_E500_DOUBLE && (mode == DFmode |
3017 | || mode == DImode)) | |
78c875e8 | 3018 | && !ALTIVEC_VECTOR_MODE (mode)) |
24ea750e DJ |
3019 | { |
3020 | HOST_WIDE_INT val = INTVAL (XEXP (x, 1)); | |
3021 | HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000; | |
3022 | HOST_WIDE_INT high | |
c4ad648e | 3023 | = (((val - low) & 0xffffffff) ^ 0x80000000) - 0x80000000; |
24ea750e DJ |
3024 | |
3025 | /* Check for 32-bit overflow. */ | |
3026 | if (high + low != val) | |
c4ad648e | 3027 | { |
24ea750e DJ |
3028 | *win = 0; |
3029 | return x; | |
3030 | } | |
3031 | ||
3032 | /* Reload the high part into a base reg; leave the low part | |
c4ad648e | 3033 | in the mem directly. */ |
24ea750e DJ |
3034 | |
3035 | x = gen_rtx_PLUS (GET_MODE (x), | |
c4ad648e AM |
3036 | gen_rtx_PLUS (GET_MODE (x), XEXP (x, 0), |
3037 | GEN_INT (high)), | |
3038 | GEN_INT (low)); | |
24ea750e DJ |
3039 | |
3040 | push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL, | |
c4ad648e AM |
3041 | BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0, |
3042 | opnum, (enum reload_type)type); | |
24ea750e DJ |
3043 | *win = 1; |
3044 | return x; | |
3045 | } | |
4937d02d | 3046 | |
24ea750e DJ |
3047 | #if TARGET_MACHO |
3048 | if (GET_CODE (x) == SYMBOL_REF | |
3049 | && DEFAULT_ABI == ABI_DARWIN | |
69ef87e2 | 3050 | && !ALTIVEC_VECTOR_MODE (mode) |
a29077da | 3051 | && (flag_pic || MACHO_DYNAMIC_NO_PIC_P) |
0d8c1c97 AM |
3052 | /* Don't do this for TFmode, since the result isn't offsettable. |
3053 | The same goes for DImode without 64-bit gprs. */ | |
3054 | && mode != TFmode | |
3055 | && (mode != DImode || TARGET_POWERPC64)) | |
24ea750e | 3056 | { |
a29077da GK |
3057 | if (flag_pic) |
3058 | { | |
3059 | rtx offset = gen_rtx_CONST (Pmode, | |
3060 | gen_rtx_MINUS (Pmode, x, | |
11abc112 | 3061 | machopic_function_base_sym ())); |
a29077da GK |
3062 | x = gen_rtx_LO_SUM (GET_MODE (x), |
3063 | gen_rtx_PLUS (Pmode, pic_offset_table_rtx, | |
3064 | gen_rtx_HIGH (Pmode, offset)), offset); | |
3065 | } | |
3066 | else | |
3067 | x = gen_rtx_LO_SUM (GET_MODE (x), | |
c4ad648e | 3068 | gen_rtx_HIGH (Pmode, x), x); |
a29077da | 3069 | |
24ea750e | 3070 | push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL, |
a29077da GK |
3071 | BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, |
3072 | opnum, (enum reload_type)type); | |
24ea750e DJ |
3073 | *win = 1; |
3074 | return x; | |
3075 | } | |
3076 | #endif | |
4937d02d | 3077 | |
24ea750e | 3078 | if (TARGET_TOC |
4d588c14 | 3079 | && constant_pool_expr_p (x) |
c1f11548 | 3080 | && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x), mode)) |
24ea750e DJ |
3081 | { |
3082 | (x) = create_TOC_reference (x); | |
3083 | *win = 1; | |
3084 | return x; | |
3085 | } | |
3086 | *win = 0; | |
3087 | return x; | |
f676971a | 3088 | } |
24ea750e | 3089 | |
258bfae2 FS |
3090 | /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression |
3091 | that is a valid memory address for an instruction. | |
3092 | The MODE argument is the machine mode for the MEM expression | |
3093 | that wants to use this address. | |
3094 | ||
3095 | On the RS/6000, there are four valid address: a SYMBOL_REF that | |
3096 | refers to a constant pool entry of an address (or the sum of it | |
3097 | plus a constant), a short (16-bit signed) constant plus a register, | |
3098 | the sum of two registers, or a register indirect, possibly with an | |
5bdc5878 | 3099 | auto-increment. For DFmode and DImode with a constant plus register, |
258bfae2 FS |
3100 | we must ensure that both words are addressable or PowerPC64 with offset |
3101 | word aligned. | |
3102 | ||
3103 | For modes spanning multiple registers (DFmode in 32-bit GPRs, | |
76d2b81d | 3104 | 32-bit DImode, TImode, TFmode), indexed addressing cannot be used because |
258bfae2 FS |
3105 | adjacent memory cells are accessed by adding word-sized offsets |
3106 | during assembly output. */ | |
3107 | int | |
a2369ed3 | 3108 | rs6000_legitimate_address (enum machine_mode mode, rtx x, int reg_ok_strict) |
258bfae2 | 3109 | { |
850e8d3d DN |
3110 | /* If this is an unaligned stvx/ldvx type address, discard the outer AND. */ |
3111 | if (TARGET_ALTIVEC | |
3112 | && ALTIVEC_VECTOR_MODE (mode) | |
3113 | && GET_CODE (x) == AND | |
3114 | && GET_CODE (XEXP (x, 1)) == CONST_INT | |
3115 | && INTVAL (XEXP (x, 1)) == -16) | |
3116 | x = XEXP (x, 0); | |
3117 | ||
c4501e62 JJ |
3118 | if (RS6000_SYMBOL_REF_TLS_P (x)) |
3119 | return 0; | |
4d588c14 | 3120 | if (legitimate_indirect_address_p (x, reg_ok_strict)) |
258bfae2 FS |
3121 | return 1; |
3122 | if ((GET_CODE (x) == PRE_INC || GET_CODE (x) == PRE_DEC) | |
0d6d6892 | 3123 | && !ALTIVEC_VECTOR_MODE (mode) |
a3170dc6 | 3124 | && !SPE_VECTOR_MODE (mode) |
54b695e7 AH |
3125 | /* Restrict addressing for DI because of our SUBREG hackery. */ |
3126 | && !(TARGET_E500_DOUBLE && (mode == DFmode || mode == DImode)) | |
258bfae2 | 3127 | && TARGET_UPDATE |
4d588c14 | 3128 | && legitimate_indirect_address_p (XEXP (x, 0), reg_ok_strict)) |
258bfae2 | 3129 | return 1; |
4d588c14 | 3130 | if (legitimate_small_data_p (mode, x)) |
258bfae2 | 3131 | return 1; |
4d588c14 | 3132 | if (legitimate_constant_pool_address_p (x)) |
258bfae2 FS |
3133 | return 1; |
3134 | /* If not REG_OK_STRICT (before reload) let pass any stack offset. */ | |
3135 | if (! reg_ok_strict | |
3136 | && GET_CODE (x) == PLUS | |
3137 | && GET_CODE (XEXP (x, 0)) == REG | |
708d2456 | 3138 | && (XEXP (x, 0) == virtual_stack_vars_rtx |
c4ad648e | 3139 | || XEXP (x, 0) == arg_pointer_rtx) |
258bfae2 FS |
3140 | && GET_CODE (XEXP (x, 1)) == CONST_INT) |
3141 | return 1; | |
76d2b81d | 3142 | if (rs6000_legitimate_offset_address_p (mode, x, reg_ok_strict)) |
258bfae2 FS |
3143 | return 1; |
3144 | if (mode != TImode | |
76d2b81d | 3145 | && mode != TFmode |
a3170dc6 AH |
3146 | && ((TARGET_HARD_FLOAT && TARGET_FPRS) |
3147 | || TARGET_POWERPC64 | |
4d4cbc0e | 3148 | || ((mode != DFmode || TARGET_E500_DOUBLE) && mode != TFmode)) |
258bfae2 | 3149 | && (TARGET_POWERPC64 || mode != DImode) |
4d588c14 | 3150 | && legitimate_indexed_address_p (x, reg_ok_strict)) |
258bfae2 | 3151 | return 1; |
4d588c14 | 3152 | if (legitimate_lo_sum_address_p (mode, x, reg_ok_strict)) |
258bfae2 FS |
3153 | return 1; |
3154 | return 0; | |
3155 | } | |
4d588c14 RH |
3156 | |
3157 | /* Go to LABEL if ADDR (a legitimate address expression) | |
3158 | has an effect that depends on the machine mode it is used for. | |
3159 | ||
3160 | On the RS/6000 this is true of all integral offsets (since AltiVec | |
3161 | modes don't allow them) or is a pre-increment or decrement. | |
3162 | ||
3163 | ??? Except that due to conceptual problems in offsettable_address_p | |
3164 | we can't really report the problems of integral offsets. So leave | |
f676971a | 3165 | this assuming that the adjustable offset must be valid for the |
4d588c14 RH |
3166 | sub-words of a TFmode operand, which is what we had before. */ |
3167 | ||
3168 | bool | |
a2369ed3 | 3169 | rs6000_mode_dependent_address (rtx addr) |
4d588c14 RH |
3170 | { |
3171 | switch (GET_CODE (addr)) | |
3172 | { | |
3173 | case PLUS: | |
3174 | if (GET_CODE (XEXP (addr, 1)) == CONST_INT) | |
3175 | { | |
3176 | unsigned HOST_WIDE_INT val = INTVAL (XEXP (addr, 1)); | |
3177 | return val + 12 + 0x8000 >= 0x10000; | |
3178 | } | |
3179 | break; | |
3180 | ||
3181 | case LO_SUM: | |
3182 | return true; | |
3183 | ||
3184 | case PRE_INC: | |
3185 | case PRE_DEC: | |
3186 | return TARGET_UPDATE; | |
3187 | ||
3188 | default: | |
3189 | break; | |
3190 | } | |
3191 | ||
3192 | return false; | |
3193 | } | |
d8ecbcdb AH |
3194 | |
3195 | /* Return number of consecutive hard regs needed starting at reg REGNO | |
3196 | to hold something of mode MODE. | |
3197 | This is ordinarily the length in words of a value of mode MODE | |
3198 | but can be less for certain modes in special long registers. | |
3199 | ||
3200 | For the SPE, GPRs are 64 bits but only 32 bits are visible in | |
3201 | scalar instructions. The upper 32 bits are only available to the | |
3202 | SIMD instructions. | |
3203 | ||
3204 | POWER and PowerPC GPRs hold 32 bits worth; | |
3205 | PowerPC64 GPRs and FPRs point register holds 64 bits worth. */ | |
3206 | ||
3207 | int | |
3208 | rs6000_hard_regno_nregs (int regno, enum machine_mode mode) | |
3209 | { | |
3210 | if (FP_REGNO_P (regno)) | |
3211 | return (GET_MODE_SIZE (mode) + UNITS_PER_FP_WORD - 1) / UNITS_PER_FP_WORD; | |
3212 | ||
4d4cbc0e AH |
3213 | if (TARGET_E500_DOUBLE && mode == DFmode) |
3214 | return 1; | |
3215 | ||
d8ecbcdb AH |
3216 | if (SPE_SIMD_REGNO_P (regno) && TARGET_SPE && SPE_VECTOR_MODE (mode)) |
3217 | return (GET_MODE_SIZE (mode) + UNITS_PER_SPE_WORD - 1) / UNITS_PER_SPE_WORD; | |
3218 | ||
3219 | if (ALTIVEC_REGNO_P (regno)) | |
3220 | return | |
3221 | (GET_MODE_SIZE (mode) + UNITS_PER_ALTIVEC_WORD - 1) / UNITS_PER_ALTIVEC_WORD; | |
3222 | ||
3223 | return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD; | |
3224 | } | |
2aa4498c AH |
3225 | |
3226 | /* Change register usage conditional on target flags. */ | |
3227 | void | |
3228 | rs6000_conditional_register_usage (void) | |
3229 | { | |
3230 | int i; | |
3231 | ||
3232 | /* Set MQ register fixed (already call_used) if not POWER | |
3233 | architecture (RIOS1, RIOS2, RSC, and PPC601) so that it will not | |
3234 | be allocated. */ | |
3235 | if (! TARGET_POWER) | |
3236 | fixed_regs[64] = 1; | |
3237 | ||
3238 | /* 64-bit AIX reserves GPR13 for thread-private data. */ | |
3239 | if (TARGET_64BIT) | |
3240 | fixed_regs[13] = call_used_regs[13] | |
3241 | = call_really_used_regs[13] = 1; | |
3242 | ||
3243 | /* Conditionally disable FPRs. */ | |
3244 | if (TARGET_SOFT_FLOAT || !TARGET_FPRS) | |
3245 | for (i = 32; i < 64; i++) | |
3246 | fixed_regs[i] = call_used_regs[i] | |
c4ad648e | 3247 | = call_really_used_regs[i] = 1; |
2aa4498c AH |
3248 | |
3249 | if (DEFAULT_ABI == ABI_V4 | |
3250 | && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM | |
3251 | && flag_pic == 2) | |
3252 | fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1; | |
3253 | ||
3254 | if (DEFAULT_ABI == ABI_V4 | |
3255 | && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM | |
3256 | && flag_pic == 1) | |
3257 | fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] | |
3258 | = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] | |
3259 | = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1; | |
3260 | ||
3261 | if (DEFAULT_ABI == ABI_DARWIN | |
3262 | && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) | |
3263 | global_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] | |
3264 | = fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] | |
3265 | = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] | |
3266 | = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1; | |
3267 | ||
b4db40bf JJ |
3268 | if (TARGET_TOC && TARGET_MINIMAL_TOC) |
3269 | fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] | |
3270 | = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1; | |
3271 | ||
2aa4498c AH |
3272 | if (TARGET_ALTIVEC) |
3273 | global_regs[VSCR_REGNO] = 1; | |
3274 | ||
3275 | if (TARGET_SPE) | |
3276 | { | |
3277 | global_regs[SPEFSCR_REGNO] = 1; | |
3278 | fixed_regs[FIXED_SCRATCH] | |
c4ad648e | 3279 | = call_used_regs[FIXED_SCRATCH] |
2aa4498c AH |
3280 | = call_really_used_regs[FIXED_SCRATCH] = 1; |
3281 | } | |
3282 | ||
3283 | if (! TARGET_ALTIVEC) | |
3284 | { | |
3285 | for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i) | |
3286 | fixed_regs[i] = call_used_regs[i] = call_really_used_regs[i] = 1; | |
3287 | call_really_used_regs[VRSAVE_REGNO] = 1; | |
3288 | } | |
3289 | ||
3290 | if (TARGET_ALTIVEC_ABI) | |
3291 | for (i = FIRST_ALTIVEC_REGNO; i < FIRST_ALTIVEC_REGNO + 20; ++i) | |
3292 | call_used_regs[i] = call_really_used_regs[i] = 1; | |
3293 | } | |
fb4d4348 | 3294 | \f |
a4f6c312 SS |
3295 | /* Try to output insns to set TARGET equal to the constant C if it can |
3296 | be done in less than N insns. Do all computations in MODE. | |
3297 | Returns the place where the output has been placed if it can be | |
3298 | done and the insns have been emitted. If it would take more than N | |
3299 | insns, zero is returned and no insns and emitted. */ | |
2bfcf297 DB |
3300 | |
3301 | rtx | |
f676971a | 3302 | rs6000_emit_set_const (rtx dest, enum machine_mode mode, |
a2369ed3 | 3303 | rtx source, int n ATTRIBUTE_UNUSED) |
2bfcf297 | 3304 | { |
af8cb5c5 | 3305 | rtx result, insn, set; |
2bfcf297 DB |
3306 | HOST_WIDE_INT c0, c1; |
3307 | ||
af8cb5c5 | 3308 | if (mode == QImode || mode == HImode) |
2bfcf297 DB |
3309 | { |
3310 | if (dest == NULL) | |
c4ad648e | 3311 | dest = gen_reg_rtx (mode); |
2bfcf297 DB |
3312 | emit_insn (gen_rtx_SET (VOIDmode, dest, source)); |
3313 | return dest; | |
3314 | } | |
af8cb5c5 | 3315 | else if (mode == SImode) |
2bfcf297 | 3316 | { |
af8cb5c5 DE |
3317 | result = no_new_pseudos ? dest : gen_reg_rtx (SImode); |
3318 | ||
3319 | emit_insn (gen_rtx_SET (VOIDmode, result, | |
3320 | GEN_INT (INTVAL (source) | |
3321 | & (~ (HOST_WIDE_INT) 0xffff)))); | |
3322 | emit_insn (gen_rtx_SET (VOIDmode, dest, | |
3323 | gen_rtx_IOR (SImode, result, | |
3324 | GEN_INT (INTVAL (source) & 0xffff)))); | |
3325 | result = dest; | |
2bfcf297 | 3326 | } |
af8cb5c5 | 3327 | else if (mode == DImode) |
2bfcf297 | 3328 | { |
af8cb5c5 DE |
3329 | if (GET_CODE (source) == CONST_INT) |
3330 | { | |
3331 | c0 = INTVAL (source); | |
3332 | c1 = -(c0 < 0); | |
3333 | } | |
3334 | else if (GET_CODE (source) == CONST_DOUBLE) | |
3335 | { | |
2bfcf297 | 3336 | #if HOST_BITS_PER_WIDE_INT >= 64 |
af8cb5c5 DE |
3337 | c0 = CONST_DOUBLE_LOW (source); |
3338 | c1 = -(c0 < 0); | |
2bfcf297 | 3339 | #else |
af8cb5c5 DE |
3340 | c0 = CONST_DOUBLE_LOW (source); |
3341 | c1 = CONST_DOUBLE_HIGH (source); | |
2bfcf297 | 3342 | #endif |
af8cb5c5 DE |
3343 | } |
3344 | else | |
3345 | abort (); | |
3346 | ||
3347 | result = rs6000_emit_set_long_const (dest, c0, c1); | |
2bfcf297 DB |
3348 | } |
3349 | else | |
a4f6c312 | 3350 | abort (); |
2bfcf297 | 3351 | |
af8cb5c5 DE |
3352 | insn = get_last_insn (); |
3353 | set = single_set (insn); | |
3354 | if (! CONSTANT_P (SET_SRC (set))) | |
3355 | set_unique_reg_note (insn, REG_EQUAL, source); | |
3356 | ||
3357 | return result; | |
2bfcf297 DB |
3358 | } |
3359 | ||
3360 | /* Having failed to find a 3 insn sequence in rs6000_emit_set_const, | |
3361 | fall back to a straight forward decomposition. We do this to avoid | |
3362 | exponential run times encountered when looking for longer sequences | |
3363 | with rs6000_emit_set_const. */ | |
3364 | static rtx | |
a2369ed3 | 3365 | rs6000_emit_set_long_const (rtx dest, HOST_WIDE_INT c1, HOST_WIDE_INT c2) |
2bfcf297 DB |
3366 | { |
3367 | if (!TARGET_POWERPC64) | |
3368 | { | |
3369 | rtx operand1, operand2; | |
3370 | ||
3371 | operand1 = operand_subword_force (dest, WORDS_BIG_ENDIAN == 0, | |
3372 | DImode); | |
3373 | operand2 = operand_subword_force (dest, WORDS_BIG_ENDIAN != 0, | |
3374 | DImode); | |
3375 | emit_move_insn (operand1, GEN_INT (c1)); | |
3376 | emit_move_insn (operand2, GEN_INT (c2)); | |
3377 | } | |
3378 | else | |
3379 | { | |
bc06712d | 3380 | HOST_WIDE_INT ud1, ud2, ud3, ud4; |
252b88f7 | 3381 | |
bc06712d | 3382 | ud1 = c1 & 0xffff; |
f921c9c9 | 3383 | ud2 = (c1 & 0xffff0000) >> 16; |
2bfcf297 | 3384 | #if HOST_BITS_PER_WIDE_INT >= 64 |
bc06712d | 3385 | c2 = c1 >> 32; |
2bfcf297 | 3386 | #endif |
bc06712d | 3387 | ud3 = c2 & 0xffff; |
f921c9c9 | 3388 | ud4 = (c2 & 0xffff0000) >> 16; |
2bfcf297 | 3389 | |
f676971a | 3390 | if ((ud4 == 0xffff && ud3 == 0xffff && ud2 == 0xffff && (ud1 & 0x8000)) |
bc06712d | 3391 | || (ud4 == 0 && ud3 == 0 && ud2 == 0 && ! (ud1 & 0x8000))) |
2bfcf297 | 3392 | { |
bc06712d | 3393 | if (ud1 & 0x8000) |
b78d48dd | 3394 | emit_move_insn (dest, GEN_INT (((ud1 ^ 0x8000) - 0x8000))); |
bc06712d TR |
3395 | else |
3396 | emit_move_insn (dest, GEN_INT (ud1)); | |
2bfcf297 | 3397 | } |
2bfcf297 | 3398 | |
f676971a | 3399 | else if ((ud4 == 0xffff && ud3 == 0xffff && (ud2 & 0x8000)) |
bc06712d | 3400 | || (ud4 == 0 && ud3 == 0 && ! (ud2 & 0x8000))) |
252b88f7 | 3401 | { |
bc06712d | 3402 | if (ud2 & 0x8000) |
f676971a | 3403 | emit_move_insn (dest, GEN_INT (((ud2 << 16) ^ 0x80000000) |
bc06712d | 3404 | - 0x80000000)); |
252b88f7 | 3405 | else |
bc06712d TR |
3406 | emit_move_insn (dest, GEN_INT (ud2 << 16)); |
3407 | if (ud1 != 0) | |
3408 | emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud1))); | |
252b88f7 | 3409 | } |
f676971a | 3410 | else if ((ud4 == 0xffff && (ud3 & 0x8000)) |
bc06712d TR |
3411 | || (ud4 == 0 && ! (ud3 & 0x8000))) |
3412 | { | |
3413 | if (ud3 & 0x8000) | |
f676971a | 3414 | emit_move_insn (dest, GEN_INT (((ud3 << 16) ^ 0x80000000) |
bc06712d TR |
3415 | - 0x80000000)); |
3416 | else | |
3417 | emit_move_insn (dest, GEN_INT (ud3 << 16)); | |
3418 | ||
3419 | if (ud2 != 0) | |
3420 | emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud2))); | |
3421 | emit_move_insn (dest, gen_rtx_ASHIFT (DImode, dest, GEN_INT (16))); | |
3422 | if (ud1 != 0) | |
3423 | emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud1))); | |
3424 | } | |
f676971a | 3425 | else |
bc06712d TR |
3426 | { |
3427 | if (ud4 & 0x8000) | |
f676971a | 3428 | emit_move_insn (dest, GEN_INT (((ud4 << 16) ^ 0x80000000) |
bc06712d TR |
3429 | - 0x80000000)); |
3430 | else | |
3431 | emit_move_insn (dest, GEN_INT (ud4 << 16)); | |
3432 | ||
3433 | if (ud3 != 0) | |
3434 | emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud3))); | |
2bfcf297 | 3435 | |
bc06712d TR |
3436 | emit_move_insn (dest, gen_rtx_ASHIFT (DImode, dest, GEN_INT (32))); |
3437 | if (ud2 != 0) | |
f676971a EC |
3438 | emit_move_insn (dest, gen_rtx_IOR (DImode, dest, |
3439 | GEN_INT (ud2 << 16))); | |
bc06712d TR |
3440 | if (ud1 != 0) |
3441 | emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud1))); | |
3442 | } | |
3443 | } | |
2bfcf297 DB |
3444 | return dest; |
3445 | } | |
3446 | ||
76d2b81d DJ |
3447 | /* Helper for the following. Get rid of [r+r] memory refs |
3448 | in cases where it won't work (TImode, TFmode). */ | |
3449 | ||
3450 | static void | |
3451 | rs6000_eliminate_indexed_memrefs (rtx operands[2]) | |
3452 | { | |
3453 | if (GET_CODE (operands[0]) == MEM | |
3454 | && GET_CODE (XEXP (operands[0], 0)) != REG | |
55aa0757 | 3455 | && ! legitimate_constant_pool_address_p (XEXP (operands[0], 0)) |
76d2b81d DJ |
3456 | && ! reload_in_progress) |
3457 | operands[0] | |
3458 | = replace_equiv_address (operands[0], | |
3459 | copy_addr_to_reg (XEXP (operands[0], 0))); | |
3460 | ||
3461 | if (GET_CODE (operands[1]) == MEM | |
3462 | && GET_CODE (XEXP (operands[1], 0)) != REG | |
55aa0757 | 3463 | && ! legitimate_constant_pool_address_p (XEXP (operands[1], 0)) |
76d2b81d DJ |
3464 | && ! reload_in_progress) |
3465 | operands[1] | |
3466 | = replace_equiv_address (operands[1], | |
3467 | copy_addr_to_reg (XEXP (operands[1], 0))); | |
3468 | } | |
3469 | ||
fb4d4348 GK |
3470 | /* Emit a move from SOURCE to DEST in mode MODE. */ |
3471 | void | |
a2369ed3 | 3472 | rs6000_emit_move (rtx dest, rtx source, enum machine_mode mode) |
fb4d4348 GK |
3473 | { |
3474 | rtx operands[2]; | |
3475 | operands[0] = dest; | |
3476 | operands[1] = source; | |
f676971a | 3477 | |
fb4d4348 GK |
3478 | /* Sanity checks. Check that we get CONST_DOUBLE only when we should. */ |
3479 | if (GET_CODE (operands[1]) == CONST_DOUBLE | |
3480 | && ! FLOAT_MODE_P (mode) | |
3481 | && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT) | |
3482 | { | |
3483 | /* FIXME. This should never happen. */ | |
3484 | /* Since it seems that it does, do the safe thing and convert | |
3485 | to a CONST_INT. */ | |
2496c7bd | 3486 | operands[1] = gen_int_mode (CONST_DOUBLE_LOW (operands[1]), mode); |
fb4d4348 GK |
3487 | } |
3488 | if (GET_CODE (operands[1]) == CONST_DOUBLE | |
3489 | && ! FLOAT_MODE_P (mode) | |
3490 | && ((CONST_DOUBLE_HIGH (operands[1]) == 0 | |
3491 | && CONST_DOUBLE_LOW (operands[1]) >= 0) | |
3492 | || (CONST_DOUBLE_HIGH (operands[1]) == -1 | |
3493 | && CONST_DOUBLE_LOW (operands[1]) < 0))) | |
3494 | abort (); | |
c9e8cb32 DD |
3495 | |
3496 | /* Check if GCC is setting up a block move that will end up using FP | |
3497 | registers as temporaries. We must make sure this is acceptable. */ | |
3498 | if (GET_CODE (operands[0]) == MEM | |
3499 | && GET_CODE (operands[1]) == MEM | |
3500 | && mode == DImode | |
41543739 GK |
3501 | && (SLOW_UNALIGNED_ACCESS (DImode, MEM_ALIGN (operands[0])) |
3502 | || SLOW_UNALIGNED_ACCESS (DImode, MEM_ALIGN (operands[1]))) | |
3503 | && ! (SLOW_UNALIGNED_ACCESS (SImode, (MEM_ALIGN (operands[0]) > 32 | |
3504 | ? 32 : MEM_ALIGN (operands[0]))) | |
3505 | || SLOW_UNALIGNED_ACCESS (SImode, (MEM_ALIGN (operands[1]) > 32 | |
f676971a | 3506 | ? 32 |
41543739 GK |
3507 | : MEM_ALIGN (operands[1])))) |
3508 | && ! MEM_VOLATILE_P (operands [0]) | |
3509 | && ! MEM_VOLATILE_P (operands [1])) | |
c9e8cb32 | 3510 | { |
41543739 GK |
3511 | emit_move_insn (adjust_address (operands[0], SImode, 0), |
3512 | adjust_address (operands[1], SImode, 0)); | |
3513 | emit_move_insn (adjust_address (operands[0], SImode, 4), | |
3514 | adjust_address (operands[1], SImode, 4)); | |
c9e8cb32 DD |
3515 | return; |
3516 | } | |
630d42a0 | 3517 | |
55aa0757 | 3518 | if (!no_new_pseudos && GET_CODE (operands[0]) == MEM |
c9dbf840 | 3519 | && !gpc_reg_operand (operands[1], mode)) |
f6219a5e | 3520 | operands[1] = force_reg (mode, operands[1]); |
a9098fd0 | 3521 | |
a3170dc6 AH |
3522 | if (mode == SFmode && ! TARGET_POWERPC |
3523 | && TARGET_HARD_FLOAT && TARGET_FPRS | |
ffc14f31 | 3524 | && GET_CODE (operands[0]) == MEM) |
fb4d4348 | 3525 | { |
ffc14f31 GK |
3526 | int regnum; |
3527 | ||
3528 | if (reload_in_progress || reload_completed) | |
3529 | regnum = true_regnum (operands[1]); | |
3530 | else if (GET_CODE (operands[1]) == REG) | |
3531 | regnum = REGNO (operands[1]); | |
3532 | else | |
3533 | regnum = -1; | |
f676971a | 3534 | |
fb4d4348 GK |
3535 | /* If operands[1] is a register, on POWER it may have |
3536 | double-precision data in it, so truncate it to single | |
3537 | precision. */ | |
3538 | if (FP_REGNO_P (regnum) || regnum >= FIRST_PSEUDO_REGISTER) | |
3539 | { | |
3540 | rtx newreg; | |
3541 | newreg = (no_new_pseudos ? operands[1] : gen_reg_rtx (mode)); | |
3542 | emit_insn (gen_aux_truncdfsf2 (newreg, operands[1])); | |
3543 | operands[1] = newreg; | |
3544 | } | |
3545 | } | |
3546 | ||
c4501e62 JJ |
3547 | /* Recognize the case where operand[1] is a reference to thread-local |
3548 | data and load its address to a register. */ | |
3549 | if (GET_CODE (operands[1]) == SYMBOL_REF) | |
3550 | { | |
3551 | enum tls_model model = SYMBOL_REF_TLS_MODEL (operands[1]); | |
3552 | if (model != 0) | |
3553 | operands[1] = rs6000_legitimize_tls_address (operands[1], model); | |
3554 | } | |
3555 | ||
8f4e6caf RH |
3556 | /* Handle the case where reload calls us with an invalid address. */ |
3557 | if (reload_in_progress && mode == Pmode | |
69ef87e2 | 3558 | && (! general_operand (operands[1], mode) |
8f4e6caf RH |
3559 | || ! nonimmediate_operand (operands[0], mode))) |
3560 | goto emit_set; | |
3561 | ||
a9baceb1 GK |
3562 | /* 128-bit constant floating-point values on Darwin should really be |
3563 | loaded as two parts. */ | |
3564 | if ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) | |
3565 | && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128 | |
3566 | && mode == TFmode && GET_CODE (operands[1]) == CONST_DOUBLE) | |
3567 | { | |
3568 | /* DImode is used, not DFmode, because simplify_gen_subreg doesn't | |
3569 | know how to get a DFmode SUBREG of a TFmode. */ | |
3570 | rs6000_emit_move (simplify_gen_subreg (DImode, operands[0], mode, 0), | |
3571 | simplify_gen_subreg (DImode, operands[1], mode, 0), | |
3572 | DImode); | |
3573 | rs6000_emit_move (simplify_gen_subreg (DImode, operands[0], mode, | |
3574 | GET_MODE_SIZE (DImode)), | |
3575 | simplify_gen_subreg (DImode, operands[1], mode, | |
3576 | GET_MODE_SIZE (DImode)), | |
3577 | DImode); | |
3578 | return; | |
3579 | } | |
3580 | ||
fb4d4348 GK |
3581 | /* FIXME: In the long term, this switch statement should go away |
3582 | and be replaced by a sequence of tests based on things like | |
3583 | mode == Pmode. */ | |
3584 | switch (mode) | |
3585 | { | |
3586 | case HImode: | |
3587 | case QImode: | |
3588 | if (CONSTANT_P (operands[1]) | |
3589 | && GET_CODE (operands[1]) != CONST_INT) | |
a9098fd0 | 3590 | operands[1] = force_const_mem (mode, operands[1]); |
fb4d4348 GK |
3591 | break; |
3592 | ||
06f4e019 | 3593 | case TFmode: |
76d2b81d DJ |
3594 | rs6000_eliminate_indexed_memrefs (operands); |
3595 | /* fall through */ | |
3596 | ||
fb4d4348 GK |
3597 | case DFmode: |
3598 | case SFmode: | |
f676971a | 3599 | if (CONSTANT_P (operands[1]) |
fb4d4348 | 3600 | && ! easy_fp_constant (operands[1], mode)) |
a9098fd0 | 3601 | operands[1] = force_const_mem (mode, operands[1]); |
fb4d4348 | 3602 | break; |
f676971a | 3603 | |
0ac081f6 AH |
3604 | case V16QImode: |
3605 | case V8HImode: | |
3606 | case V4SFmode: | |
3607 | case V4SImode: | |
a3170dc6 AH |
3608 | case V4HImode: |
3609 | case V2SFmode: | |
3610 | case V2SImode: | |
00a892b8 | 3611 | case V1DImode: |
69ef87e2 | 3612 | if (CONSTANT_P (operands[1]) |
d744e06e | 3613 | && !easy_vector_constant (operands[1], mode)) |
0ac081f6 AH |
3614 | operands[1] = force_const_mem (mode, operands[1]); |
3615 | break; | |
f676971a | 3616 | |
fb4d4348 | 3617 | case SImode: |
a9098fd0 | 3618 | case DImode: |
fb4d4348 GK |
3619 | /* Use default pattern for address of ELF small data */ |
3620 | if (TARGET_ELF | |
a9098fd0 | 3621 | && mode == Pmode |
f607bc57 | 3622 | && DEFAULT_ABI == ABI_V4 |
f676971a | 3623 | && (GET_CODE (operands[1]) == SYMBOL_REF |
a9098fd0 GK |
3624 | || GET_CODE (operands[1]) == CONST) |
3625 | && small_data_operand (operands[1], mode)) | |
fb4d4348 GK |
3626 | { |
3627 | emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1])); | |
3628 | return; | |
3629 | } | |
3630 | ||
f607bc57 | 3631 | if (DEFAULT_ABI == ABI_V4 |
a9098fd0 GK |
3632 | && mode == Pmode && mode == SImode |
3633 | && flag_pic == 1 && got_operand (operands[1], mode)) | |
fb4d4348 GK |
3634 | { |
3635 | emit_insn (gen_movsi_got (operands[0], operands[1])); | |
3636 | return; | |
3637 | } | |
3638 | ||
ee890fe2 | 3639 | if ((TARGET_ELF || DEFAULT_ABI == ABI_DARWIN) |
f1384257 AM |
3640 | && TARGET_NO_TOC |
3641 | && ! flag_pic | |
a9098fd0 | 3642 | && mode == Pmode |
fb4d4348 GK |
3643 | && CONSTANT_P (operands[1]) |
3644 | && GET_CODE (operands[1]) != HIGH | |
3645 | && GET_CODE (operands[1]) != CONST_INT) | |
3646 | { | |
a9098fd0 | 3647 | rtx target = (no_new_pseudos ? operands[0] : gen_reg_rtx (mode)); |
fb4d4348 GK |
3648 | |
3649 | /* If this is a function address on -mcall-aixdesc, | |
3650 | convert it to the address of the descriptor. */ | |
3651 | if (DEFAULT_ABI == ABI_AIX | |
3652 | && GET_CODE (operands[1]) == SYMBOL_REF | |
3653 | && XSTR (operands[1], 0)[0] == '.') | |
3654 | { | |
3655 | const char *name = XSTR (operands[1], 0); | |
3656 | rtx new_ref; | |
3657 | while (*name == '.') | |
3658 | name++; | |
3659 | new_ref = gen_rtx_SYMBOL_REF (Pmode, name); | |
3660 | CONSTANT_POOL_ADDRESS_P (new_ref) | |
3661 | = CONSTANT_POOL_ADDRESS_P (operands[1]); | |
d1908feb | 3662 | SYMBOL_REF_FLAGS (new_ref) = SYMBOL_REF_FLAGS (operands[1]); |
fb4d4348 | 3663 | SYMBOL_REF_USED (new_ref) = SYMBOL_REF_USED (operands[1]); |
d1908feb | 3664 | SYMBOL_REF_DECL (new_ref) = SYMBOL_REF_DECL (operands[1]); |
fb4d4348 GK |
3665 | operands[1] = new_ref; |
3666 | } | |
7509c759 | 3667 | |
ee890fe2 SS |
3668 | if (DEFAULT_ABI == ABI_DARWIN) |
3669 | { | |
ab82a49f AP |
3670 | #if TARGET_MACHO |
3671 | if (MACHO_DYNAMIC_NO_PIC_P) | |
3672 | { | |
3673 | /* Take care of any required data indirection. */ | |
3674 | operands[1] = rs6000_machopic_legitimize_pic_address ( | |
3675 | operands[1], mode, operands[0]); | |
3676 | if (operands[0] != operands[1]) | |
3677 | emit_insn (gen_rtx_SET (VOIDmode, | |
c4ad648e | 3678 | operands[0], operands[1])); |
ab82a49f AP |
3679 | return; |
3680 | } | |
3681 | #endif | |
b8a55285 AP |
3682 | emit_insn (gen_macho_high (target, operands[1])); |
3683 | emit_insn (gen_macho_low (operands[0], target, operands[1])); | |
ee890fe2 SS |
3684 | return; |
3685 | } | |
3686 | ||
fb4d4348 GK |
3687 | emit_insn (gen_elf_high (target, operands[1])); |
3688 | emit_insn (gen_elf_low (operands[0], target, operands[1])); | |
3689 | return; | |
3690 | } | |
3691 | ||
a9098fd0 GK |
3692 | /* If this is a SYMBOL_REF that refers to a constant pool entry, |
3693 | and we have put it in the TOC, we just need to make a TOC-relative | |
3694 | reference to it. */ | |
3695 | if (TARGET_TOC | |
3696 | && GET_CODE (operands[1]) == SYMBOL_REF | |
4d588c14 | 3697 | && constant_pool_expr_p (operands[1]) |
a9098fd0 GK |
3698 | && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (operands[1]), |
3699 | get_pool_mode (operands[1]))) | |
fb4d4348 | 3700 | { |
a9098fd0 | 3701 | operands[1] = create_TOC_reference (operands[1]); |
fb4d4348 | 3702 | } |
a9098fd0 GK |
3703 | else if (mode == Pmode |
3704 | && CONSTANT_P (operands[1]) | |
38886f37 AO |
3705 | && ((GET_CODE (operands[1]) != CONST_INT |
3706 | && ! easy_fp_constant (operands[1], mode)) | |
3707 | || (GET_CODE (operands[1]) == CONST_INT | |
3708 | && num_insns_constant (operands[1], mode) > 2) | |
3709 | || (GET_CODE (operands[0]) == REG | |
3710 | && FP_REGNO_P (REGNO (operands[0])))) | |
a9098fd0 | 3711 | && GET_CODE (operands[1]) != HIGH |
4d588c14 RH |
3712 | && ! legitimate_constant_pool_address_p (operands[1]) |
3713 | && ! toc_relative_expr_p (operands[1])) | |
fb4d4348 GK |
3714 | { |
3715 | /* Emit a USE operation so that the constant isn't deleted if | |
3716 | expensive optimizations are turned on because nobody | |
3717 | references it. This should only be done for operands that | |
3718 | contain SYMBOL_REFs with CONSTANT_POOL_ADDRESS_P set. | |
3719 | This should not be done for operands that contain LABEL_REFs. | |
3720 | For now, we just handle the obvious case. */ | |
3721 | if (GET_CODE (operands[1]) != LABEL_REF) | |
3722 | emit_insn (gen_rtx_USE (VOIDmode, operands[1])); | |
3723 | ||
c859cda6 | 3724 | #if TARGET_MACHO |
ee890fe2 | 3725 | /* Darwin uses a special PIC legitimizer. */ |
ab82a49f | 3726 | if (DEFAULT_ABI == ABI_DARWIN && MACHOPIC_INDIRECT) |
ee890fe2 | 3727 | { |
ee890fe2 SS |
3728 | operands[1] = |
3729 | rs6000_machopic_legitimize_pic_address (operands[1], mode, | |
c859cda6 DJ |
3730 | operands[0]); |
3731 | if (operands[0] != operands[1]) | |
3732 | emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1])); | |
ee890fe2 SS |
3733 | return; |
3734 | } | |
c859cda6 | 3735 | #endif |
ee890fe2 | 3736 | |
fb4d4348 GK |
3737 | /* If we are to limit the number of things we put in the TOC and |
3738 | this is a symbol plus a constant we can add in one insn, | |
3739 | just put the symbol in the TOC and add the constant. Don't do | |
3740 | this if reload is in progress. */ | |
3741 | if (GET_CODE (operands[1]) == CONST | |
3742 | && TARGET_NO_SUM_IN_TOC && ! reload_in_progress | |
3743 | && GET_CODE (XEXP (operands[1], 0)) == PLUS | |
a9098fd0 | 3744 | && add_operand (XEXP (XEXP (operands[1], 0), 1), mode) |
fb4d4348 GK |
3745 | && (GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == LABEL_REF |
3746 | || GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == SYMBOL_REF) | |
3747 | && ! side_effects_p (operands[0])) | |
3748 | { | |
a4f6c312 SS |
3749 | rtx sym = |
3750 | force_const_mem (mode, XEXP (XEXP (operands[1], 0), 0)); | |
fb4d4348 GK |
3751 | rtx other = XEXP (XEXP (operands[1], 0), 1); |
3752 | ||
a9098fd0 GK |
3753 | sym = force_reg (mode, sym); |
3754 | if (mode == SImode) | |
3755 | emit_insn (gen_addsi3 (operands[0], sym, other)); | |
3756 | else | |
3757 | emit_insn (gen_adddi3 (operands[0], sym, other)); | |
fb4d4348 GK |
3758 | return; |
3759 | } | |
3760 | ||
a9098fd0 | 3761 | operands[1] = force_const_mem (mode, operands[1]); |
fb4d4348 | 3762 | |
f676971a | 3763 | if (TARGET_TOC |
4d588c14 | 3764 | && constant_pool_expr_p (XEXP (operands[1], 0)) |
d34c5b80 DE |
3765 | && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P ( |
3766 | get_pool_constant (XEXP (operands[1], 0)), | |
3767 | get_pool_mode (XEXP (operands[1], 0)))) | |
a9098fd0 | 3768 | { |
ba4828e0 | 3769 | operands[1] |
542a8afa | 3770 | = gen_const_mem (mode, |
c4ad648e | 3771 | create_TOC_reference (XEXP (operands[1], 0))); |
ba4828e0 | 3772 | set_mem_alias_set (operands[1], get_TOC_alias_set ()); |
a9098fd0 | 3773 | } |
fb4d4348 GK |
3774 | } |
3775 | break; | |
a9098fd0 | 3776 | |
fb4d4348 | 3777 | case TImode: |
76d2b81d DJ |
3778 | rs6000_eliminate_indexed_memrefs (operands); |
3779 | ||
27dc0551 DE |
3780 | if (TARGET_POWER) |
3781 | { | |
3782 | emit_insn (gen_rtx_PARALLEL (VOIDmode, | |
3783 | gen_rtvec (2, | |
3784 | gen_rtx_SET (VOIDmode, | |
3785 | operands[0], operands[1]), | |
3786 | gen_rtx_CLOBBER (VOIDmode, | |
3787 | gen_rtx_SCRATCH (SImode))))); | |
3788 | return; | |
3789 | } | |
fb4d4348 GK |
3790 | break; |
3791 | ||
3792 | default: | |
3793 | abort (); | |
3794 | } | |
3795 | ||
a9098fd0 GK |
3796 | /* Above, we may have called force_const_mem which may have returned |
3797 | an invalid address. If we can, fix this up; otherwise, reload will | |
3798 | have to deal with it. */ | |
8f4e6caf RH |
3799 | if (GET_CODE (operands[1]) == MEM && ! reload_in_progress) |
3800 | operands[1] = validize_mem (operands[1]); | |
a9098fd0 | 3801 | |
8f4e6caf | 3802 | emit_set: |
fb4d4348 GK |
3803 | emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1])); |
3804 | } | |
4697a36c | 3805 | \f |
2858f73a GK |
3806 | /* Nonzero if we can use a floating-point register to pass this arg. */ |
3807 | #define USE_FP_FOR_ARG_P(CUM,MODE,TYPE) \ | |
3808 | (GET_MODE_CLASS (MODE) == MODE_FLOAT \ | |
3809 | && (CUM)->fregno <= FP_ARG_MAX_REG \ | |
3810 | && TARGET_HARD_FLOAT && TARGET_FPRS) | |
3811 | ||
3812 | /* Nonzero if we can use an AltiVec register to pass this arg. */ | |
3813 | #define USE_ALTIVEC_FOR_ARG_P(CUM,MODE,TYPE,NAMED) \ | |
3814 | (ALTIVEC_VECTOR_MODE (MODE) \ | |
3815 | && (CUM)->vregno <= ALTIVEC_ARG_MAX_REG \ | |
3816 | && TARGET_ALTIVEC_ABI \ | |
83953138 | 3817 | && (NAMED)) |
2858f73a | 3818 | |
c6e8c921 GK |
3819 | /* Return a nonzero value to say to return the function value in |
3820 | memory, just as large structures are always returned. TYPE will be | |
3821 | the data type of the value, and FNTYPE will be the type of the | |
3822 | function doing the returning, or @code{NULL} for libcalls. | |
3823 | ||
3824 | The AIX ABI for the RS/6000 specifies that all structures are | |
3825 | returned in memory. The Darwin ABI does the same. The SVR4 ABI | |
3826 | specifies that structures <= 8 bytes are returned in r3/r4, but a | |
3827 | draft put them in memory, and GCC used to implement the draft | |
3828 | instead of the final standard. Therefore, TARGET_AIX_STRUCT_RET | |
3829 | controls this instead of DEFAULT_ABI; V.4 targets needing backward | |
3830 | compatibility can change DRAFT_V4_STRUCT_RET to override the | |
3831 | default, and -m switches get the final word. See | |
3832 | rs6000_override_options for more details. | |
3833 | ||
3834 | The PPC32 SVR4 ABI uses IEEE double extended for long double, if 128-bit | |
3835 | long double support is enabled. These values are returned in memory. | |
3836 | ||
3837 | int_size_in_bytes returns -1 for variable size objects, which go in | |
3838 | memory always. The cast to unsigned makes -1 > 8. */ | |
3839 | ||
3840 | static bool | |
3841 | rs6000_return_in_memory (tree type, tree fntype ATTRIBUTE_UNUSED) | |
3842 | { | |
594a51fe SS |
3843 | /* In the darwin64 abi, try to use registers for larger structs |
3844 | if possible. */ | |
0b5383eb | 3845 | if (rs6000_darwin64_abi |
594a51fe | 3846 | && TREE_CODE (type) == RECORD_TYPE |
0b5383eb DJ |
3847 | && int_size_in_bytes (type) > 0) |
3848 | { | |
3849 | CUMULATIVE_ARGS valcum; | |
3850 | rtx valret; | |
3851 | ||
3852 | valcum.words = 0; | |
3853 | valcum.fregno = FP_ARG_MIN_REG; | |
3854 | valcum.vregno = ALTIVEC_ARG_MIN_REG; | |
3855 | /* Do a trial code generation as if this were going to be passed | |
3856 | as an argument; if any part goes in memory, we return NULL. */ | |
3857 | valret = rs6000_darwin64_record_arg (&valcum, type, 1, true); | |
3858 | if (valret) | |
3859 | return false; | |
3860 | /* Otherwise fall through to more conventional ABI rules. */ | |
3861 | } | |
594a51fe | 3862 | |
c6e8c921 GK |
3863 | if (AGGREGATE_TYPE_P (type) |
3864 | && (TARGET_AIX_STRUCT_RET | |
3865 | || (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 8)) | |
3866 | return true; | |
b693336b | 3867 | |
bada2eb8 DE |
3868 | /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector |
3869 | modes only exist for GCC vector types if -maltivec. */ | |
3870 | if (TARGET_32BIT && !TARGET_ALTIVEC_ABI | |
3871 | && ALTIVEC_VECTOR_MODE (TYPE_MODE (type))) | |
3872 | return false; | |
3873 | ||
b693336b PB |
3874 | /* Return synthetic vectors in memory. */ |
3875 | if (TREE_CODE (type) == VECTOR_TYPE | |
ad630bef | 3876 | && int_size_in_bytes (type) > (TARGET_ALTIVEC_ABI ? 16 : 8)) |
b693336b PB |
3877 | { |
3878 | static bool warned_for_return_big_vectors = false; | |
3879 | if (!warned_for_return_big_vectors) | |
3880 | { | |
bada2eb8 | 3881 | warning ("GCC vector returned by reference: " |
b693336b PB |
3882 | "non-standard ABI extension with no compatibility guarantee"); |
3883 | warned_for_return_big_vectors = true; | |
3884 | } | |
3885 | return true; | |
3886 | } | |
3887 | ||
c6e8c921 GK |
3888 | if (DEFAULT_ABI == ABI_V4 && TYPE_MODE (type) == TFmode) |
3889 | return true; | |
ad630bef | 3890 | |
c6e8c921 GK |
3891 | return false; |
3892 | } | |
3893 | ||
4697a36c MM |
3894 | /* Initialize a variable CUM of type CUMULATIVE_ARGS |
3895 | for a call to a function whose data type is FNTYPE. | |
3896 | For a library call, FNTYPE is 0. | |
3897 | ||
3898 | For incoming args we set the number of arguments in the prototype large | |
1c20ae99 | 3899 | so we never return a PARALLEL. */ |
4697a36c MM |
3900 | |
3901 | void | |
f676971a | 3902 | init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype, |
0f6937fe AM |
3903 | rtx libname ATTRIBUTE_UNUSED, int incoming, |
3904 | int libcall, int n_named_args) | |
4697a36c MM |
3905 | { |
3906 | static CUMULATIVE_ARGS zero_cumulative; | |
3907 | ||
3908 | *cum = zero_cumulative; | |
3909 | cum->words = 0; | |
3910 | cum->fregno = FP_ARG_MIN_REG; | |
0ac081f6 | 3911 | cum->vregno = ALTIVEC_ARG_MIN_REG; |
4697a36c | 3912 | cum->prototype = (fntype && TYPE_ARG_TYPES (fntype)); |
ddcc8263 DE |
3913 | cum->call_cookie = ((DEFAULT_ABI == ABI_V4 && libcall) |
3914 | ? CALL_LIBCALL : CALL_NORMAL); | |
4cc833b7 | 3915 | cum->sysv_gregno = GP_ARG_MIN_REG; |
a6c9bed4 AH |
3916 | cum->stdarg = fntype |
3917 | && (TYPE_ARG_TYPES (fntype) != 0 | |
3918 | && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype))) | |
3919 | != void_type_node)); | |
4697a36c | 3920 | |
0f6937fe AM |
3921 | cum->nargs_prototype = 0; |
3922 | if (incoming || cum->prototype) | |
3923 | cum->nargs_prototype = n_named_args; | |
4697a36c | 3924 | |
a5c76ee6 | 3925 | /* Check for a longcall attribute. */ |
3eb4e360 AM |
3926 | if ((!fntype && rs6000_default_long_calls) |
3927 | || (fntype | |
3928 | && lookup_attribute ("longcall", TYPE_ATTRIBUTES (fntype)) | |
3929 | && !lookup_attribute ("shortcall", TYPE_ATTRIBUTES (fntype)))) | |
3930 | cum->call_cookie |= CALL_LONG; | |
6a4cee5f | 3931 | |
4697a36c MM |
3932 | if (TARGET_DEBUG_ARG) |
3933 | { | |
3934 | fprintf (stderr, "\ninit_cumulative_args:"); | |
3935 | if (fntype) | |
3936 | { | |
3937 | tree ret_type = TREE_TYPE (fntype); | |
3938 | fprintf (stderr, " ret code = %s,", | |
3939 | tree_code_name[ (int)TREE_CODE (ret_type) ]); | |
3940 | } | |
3941 | ||
6a4cee5f MM |
3942 | if (cum->call_cookie & CALL_LONG) |
3943 | fprintf (stderr, " longcall,"); | |
3944 | ||
4697a36c MM |
3945 | fprintf (stderr, " proto = %d, nargs = %d\n", |
3946 | cum->prototype, cum->nargs_prototype); | |
3947 | } | |
f676971a | 3948 | |
c4ad648e AM |
3949 | if (fntype |
3950 | && !TARGET_ALTIVEC | |
3951 | && TARGET_ALTIVEC_ABI | |
3952 | && ALTIVEC_VECTOR_MODE (TYPE_MODE (TREE_TYPE (fntype)))) | |
3953 | { | |
3954 | error ("Cannot return value in vector register because" | |
3955 | " altivec instructions are disabled, use -maltivec" | |
3956 | " to enable them."); | |
3957 | } | |
4697a36c MM |
3958 | } |
3959 | \f | |
fe984136 RH |
3960 | /* Return true if TYPE must be passed on the stack and not in registers. */ |
3961 | ||
3962 | static bool | |
3963 | rs6000_must_pass_in_stack (enum machine_mode mode, tree type) | |
3964 | { | |
3965 | if (DEFAULT_ABI == ABI_AIX || TARGET_64BIT) | |
3966 | return must_pass_in_stack_var_size (mode, type); | |
3967 | else | |
3968 | return must_pass_in_stack_var_size_or_pad (mode, type); | |
3969 | } | |
3970 | ||
c229cba9 DE |
3971 | /* If defined, a C expression which determines whether, and in which |
3972 | direction, to pad out an argument with extra space. The value | |
3973 | should be of type `enum direction': either `upward' to pad above | |
3974 | the argument, `downward' to pad below, or `none' to inhibit | |
3975 | padding. | |
3976 | ||
3977 | For the AIX ABI structs are always stored left shifted in their | |
3978 | argument slot. */ | |
3979 | ||
9ebbca7d | 3980 | enum direction |
a2369ed3 | 3981 | function_arg_padding (enum machine_mode mode, tree type) |
c229cba9 | 3982 | { |
6e985040 AM |
3983 | #ifndef AGGREGATE_PADDING_FIXED |
3984 | #define AGGREGATE_PADDING_FIXED 0 | |
3985 | #endif | |
3986 | #ifndef AGGREGATES_PAD_UPWARD_ALWAYS | |
3987 | #define AGGREGATES_PAD_UPWARD_ALWAYS 0 | |
3988 | #endif | |
3989 | ||
3990 | if (!AGGREGATE_PADDING_FIXED) | |
3991 | { | |
3992 | /* GCC used to pass structures of the same size as integer types as | |
3993 | if they were in fact integers, ignoring FUNCTION_ARG_PADDING. | |
19525b57 | 3994 | i.e. Structures of size 1 or 2 (or 4 when TARGET_64BIT) were |
6e985040 AM |
3995 | passed padded downward, except that -mstrict-align further |
3996 | muddied the water in that multi-component structures of 2 and 4 | |
3997 | bytes in size were passed padded upward. | |
3998 | ||
3999 | The following arranges for best compatibility with previous | |
4000 | versions of gcc, but removes the -mstrict-align dependency. */ | |
4001 | if (BYTES_BIG_ENDIAN) | |
4002 | { | |
4003 | HOST_WIDE_INT size = 0; | |
4004 | ||
4005 | if (mode == BLKmode) | |
4006 | { | |
4007 | if (type && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST) | |
4008 | size = int_size_in_bytes (type); | |
4009 | } | |
4010 | else | |
4011 | size = GET_MODE_SIZE (mode); | |
4012 | ||
4013 | if (size == 1 || size == 2 || size == 4) | |
4014 | return downward; | |
4015 | } | |
4016 | return upward; | |
4017 | } | |
4018 | ||
4019 | if (AGGREGATES_PAD_UPWARD_ALWAYS) | |
4020 | { | |
4021 | if (type != 0 && AGGREGATE_TYPE_P (type)) | |
4022 | return upward; | |
4023 | } | |
c229cba9 | 4024 | |
d3704c46 KH |
4025 | /* Fall back to the default. */ |
4026 | return DEFAULT_FUNCTION_ARG_PADDING (mode, type); | |
c229cba9 DE |
4027 | } |
4028 | ||
b6c9286a | 4029 | /* If defined, a C expression that gives the alignment boundary, in bits, |
f676971a | 4030 | of an argument with the specified mode and type. If it is not defined, |
b6c9286a | 4031 | PARM_BOUNDARY is used for all arguments. |
f676971a | 4032 | |
b693336b PB |
4033 | V.4 wants long longs to be double word aligned. |
4034 | Doubleword align SPE vectors. | |
4035 | Quadword align Altivec vectors. | |
4036 | Quadword align large synthetic vector types. */ | |
b6c9286a MM |
4037 | |
4038 | int | |
b693336b | 4039 | function_arg_boundary (enum machine_mode mode, tree type) |
b6c9286a | 4040 | { |
4ed78545 AM |
4041 | if (DEFAULT_ABI == ABI_V4 && GET_MODE_SIZE (mode) == 8) |
4042 | return 64; | |
ad630bef DE |
4043 | else if (SPE_VECTOR_MODE (mode) |
4044 | || (type && TREE_CODE (type) == VECTOR_TYPE | |
4045 | && int_size_in_bytes (type) >= 8 | |
4046 | && int_size_in_bytes (type) < 16)) | |
e1f83b4d | 4047 | return 64; |
ad630bef DE |
4048 | else if (ALTIVEC_VECTOR_MODE (mode) |
4049 | || (type && TREE_CODE (type) == VECTOR_TYPE | |
4050 | && int_size_in_bytes (type) >= 16)) | |
0ac081f6 | 4051 | return 128; |
0b5383eb DJ |
4052 | else if (rs6000_darwin64_abi && mode == BLKmode |
4053 | && type && TYPE_ALIGN (type) > 64) | |
4054 | return 128; | |
9ebbca7d | 4055 | else |
b6c9286a | 4056 | return PARM_BOUNDARY; |
b6c9286a | 4057 | } |
c53bdcf5 AM |
4058 | |
4059 | /* Compute the size (in words) of a function argument. */ | |
4060 | ||
4061 | static unsigned long | |
4062 | rs6000_arg_size (enum machine_mode mode, tree type) | |
4063 | { | |
4064 | unsigned long size; | |
4065 | ||
4066 | if (mode != BLKmode) | |
4067 | size = GET_MODE_SIZE (mode); | |
4068 | else | |
4069 | size = int_size_in_bytes (type); | |
4070 | ||
4071 | if (TARGET_32BIT) | |
4072 | return (size + 3) >> 2; | |
4073 | else | |
4074 | return (size + 7) >> 3; | |
4075 | } | |
b6c9286a | 4076 | \f |
0b5383eb | 4077 | /* Use this to flush pending int fields. */ |
594a51fe SS |
4078 | |
4079 | static void | |
0b5383eb DJ |
4080 | rs6000_darwin64_record_arg_advance_flush (CUMULATIVE_ARGS *cum, |
4081 | HOST_WIDE_INT bitpos) | |
594a51fe | 4082 | { |
0b5383eb DJ |
4083 | unsigned int startbit, endbit; |
4084 | int intregs, intoffset; | |
4085 | enum machine_mode mode; | |
594a51fe | 4086 | |
0b5383eb DJ |
4087 | if (cum->intoffset == -1) |
4088 | return; | |
594a51fe | 4089 | |
0b5383eb DJ |
4090 | intoffset = cum->intoffset; |
4091 | cum->intoffset = -1; | |
4092 | ||
4093 | if (intoffset % BITS_PER_WORD != 0) | |
4094 | { | |
4095 | mode = mode_for_size (BITS_PER_WORD - intoffset % BITS_PER_WORD, | |
4096 | MODE_INT, 0); | |
4097 | if (mode == BLKmode) | |
594a51fe | 4098 | { |
0b5383eb DJ |
4099 | /* We couldn't find an appropriate mode, which happens, |
4100 | e.g., in packed structs when there are 3 bytes to load. | |
4101 | Back intoffset back to the beginning of the word in this | |
4102 | case. */ | |
4103 | intoffset = intoffset & -BITS_PER_WORD; | |
594a51fe | 4104 | } |
594a51fe | 4105 | } |
0b5383eb DJ |
4106 | |
4107 | startbit = intoffset & -BITS_PER_WORD; | |
4108 | endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD; | |
4109 | intregs = (endbit - startbit) / BITS_PER_WORD; | |
4110 | cum->words += intregs; | |
4111 | } | |
4112 | ||
4113 | /* The darwin64 ABI calls for us to recurse down through structs, | |
4114 | looking for elements passed in registers. Unfortunately, we have | |
4115 | to track int register count here also because of misalignments | |
4116 | in powerpc alignment mode. */ | |
4117 | ||
4118 | static void | |
4119 | rs6000_darwin64_record_arg_advance_recurse (CUMULATIVE_ARGS *cum, | |
4120 | tree type, | |
4121 | HOST_WIDE_INT startbitpos) | |
4122 | { | |
4123 | tree f; | |
4124 | ||
4125 | for (f = TYPE_FIELDS (type); f ; f = TREE_CHAIN (f)) | |
4126 | if (TREE_CODE (f) == FIELD_DECL) | |
4127 | { | |
4128 | HOST_WIDE_INT bitpos = startbitpos; | |
4129 | tree ftype = TREE_TYPE (f); | |
4130 | enum machine_mode mode = TYPE_MODE (ftype); | |
4131 | ||
4132 | if (DECL_SIZE (f) != 0 | |
4133 | && host_integerp (bit_position (f), 1)) | |
4134 | bitpos += int_bit_position (f); | |
4135 | ||
4136 | /* ??? FIXME: else assume zero offset. */ | |
4137 | ||
4138 | if (TREE_CODE (ftype) == RECORD_TYPE) | |
4139 | rs6000_darwin64_record_arg_advance_recurse (cum, ftype, bitpos); | |
4140 | else if (USE_FP_FOR_ARG_P (cum, mode, ftype)) | |
4141 | { | |
4142 | rs6000_darwin64_record_arg_advance_flush (cum, bitpos); | |
4143 | cum->fregno += (GET_MODE_SIZE (mode) + 7) >> 3; | |
4144 | cum->words += (GET_MODE_SIZE (mode) + 7) >> 3; | |
4145 | } | |
4146 | else if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, 1)) | |
4147 | { | |
4148 | rs6000_darwin64_record_arg_advance_flush (cum, bitpos); | |
4149 | cum->vregno++; | |
4150 | cum->words += 2; | |
4151 | } | |
4152 | else if (cum->intoffset == -1) | |
4153 | cum->intoffset = bitpos; | |
4154 | } | |
594a51fe SS |
4155 | } |
4156 | ||
4697a36c MM |
4157 | /* Update the data in CUM to advance over an argument |
4158 | of mode MODE and data type TYPE. | |
b2d04ecf AM |
4159 | (TYPE is null for libcalls where that information may not be available.) |
4160 | ||
4161 | Note that for args passed by reference, function_arg will be called | |
4162 | with MODE and TYPE set to that of the pointer to the arg, not the arg | |
4163 | itself. */ | |
4697a36c MM |
4164 | |
4165 | void | |
f676971a | 4166 | function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode, |
594a51fe | 4167 | tree type, int named, int depth) |
4697a36c | 4168 | { |
0b5383eb DJ |
4169 | int size; |
4170 | ||
594a51fe SS |
4171 | /* Only tick off an argument if we're not recursing. */ |
4172 | if (depth == 0) | |
4173 | cum->nargs_prototype--; | |
4697a36c | 4174 | |
ad630bef DE |
4175 | if (TARGET_ALTIVEC_ABI |
4176 | && (ALTIVEC_VECTOR_MODE (mode) | |
4177 | || (type && TREE_CODE (type) == VECTOR_TYPE | |
4178 | && int_size_in_bytes (type) == 16))) | |
0ac081f6 | 4179 | { |
4ed78545 AM |
4180 | bool stack = false; |
4181 | ||
2858f73a | 4182 | if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named)) |
c4ad648e | 4183 | { |
6d0ef01e HP |
4184 | cum->vregno++; |
4185 | if (!TARGET_ALTIVEC) | |
4186 | error ("Cannot pass argument in vector register because" | |
4187 | " altivec instructions are disabled, use -maltivec" | |
4188 | " to enable them."); | |
4ed78545 AM |
4189 | |
4190 | /* PowerPC64 Linux and AIX allocate GPRs for a vector argument | |
f676971a | 4191 | even if it is going to be passed in a vector register. |
4ed78545 AM |
4192 | Darwin does the same for variable-argument functions. */ |
4193 | if ((DEFAULT_ABI == ABI_AIX && TARGET_64BIT) | |
4194 | || (cum->stdarg && DEFAULT_ABI != ABI_V4)) | |
4195 | stack = true; | |
6d0ef01e | 4196 | } |
4ed78545 AM |
4197 | else |
4198 | stack = true; | |
4199 | ||
4200 | if (stack) | |
c4ad648e | 4201 | { |
a594a19c | 4202 | int align; |
f676971a | 4203 | |
2858f73a GK |
4204 | /* Vector parameters must be 16-byte aligned. This places |
4205 | them at 2 mod 4 in terms of words in 32-bit mode, since | |
4206 | the parameter save area starts at offset 24 from the | |
4207 | stack. In 64-bit mode, they just have to start on an | |
4208 | even word, since the parameter save area is 16-byte | |
4209 | aligned. Space for GPRs is reserved even if the argument | |
4210 | will be passed in memory. */ | |
4211 | if (TARGET_32BIT) | |
4ed78545 | 4212 | align = (2 - cum->words) & 3; |
2858f73a GK |
4213 | else |
4214 | align = cum->words & 1; | |
c53bdcf5 | 4215 | cum->words += align + rs6000_arg_size (mode, type); |
f676971a | 4216 | |
a594a19c GK |
4217 | if (TARGET_DEBUG_ARG) |
4218 | { | |
f676971a | 4219 | fprintf (stderr, "function_adv: words = %2d, align=%d, ", |
a594a19c GK |
4220 | cum->words, align); |
4221 | fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s\n", | |
f676971a | 4222 | cum->nargs_prototype, cum->prototype, |
2858f73a | 4223 | GET_MODE_NAME (mode)); |
a594a19c GK |
4224 | } |
4225 | } | |
0ac081f6 | 4226 | } |
a4b0320c | 4227 | else if (TARGET_SPE_ABI && TARGET_SPE && SPE_VECTOR_MODE (mode) |
a6c9bed4 AH |
4228 | && !cum->stdarg |
4229 | && cum->sysv_gregno <= GP_ARG_MAX_REG) | |
a4b0320c | 4230 | cum->sysv_gregno++; |
594a51fe SS |
4231 | |
4232 | else if (rs6000_darwin64_abi | |
4233 | && mode == BLKmode | |
0b5383eb DJ |
4234 | && TREE_CODE (type) == RECORD_TYPE |
4235 | && (size = int_size_in_bytes (type)) > 0) | |
4236 | { | |
4237 | /* Variable sized types have size == -1 and are | |
4238 | treated as if consisting entirely of ints. | |
4239 | Pad to 16 byte boundary if needed. */ | |
4240 | if (TYPE_ALIGN (type) >= 2 * BITS_PER_WORD | |
4241 | && (cum->words % 2) != 0) | |
4242 | cum->words++; | |
4243 | /* For varargs, we can just go up by the size of the struct. */ | |
4244 | if (!named) | |
4245 | cum->words += (size + 7) / 8; | |
4246 | else | |
4247 | { | |
4248 | /* It is tempting to say int register count just goes up by | |
4249 | sizeof(type)/8, but this is wrong in a case such as | |
4250 | { int; double; int; } [powerpc alignment]. We have to | |
4251 | grovel through the fields for these too. */ | |
4252 | cum->intoffset = 0; | |
4253 | rs6000_darwin64_record_arg_advance_recurse (cum, type, 0); | |
4254 | rs6000_darwin64_record_arg_advance_flush (cum, | |
4255 | size * BITS_PER_UNIT); | |
4256 | } | |
4257 | } | |
f607bc57 | 4258 | else if (DEFAULT_ABI == ABI_V4) |
4697a36c | 4259 | { |
a3170dc6 | 4260 | if (TARGET_HARD_FLOAT && TARGET_FPRS |
4cc833b7 | 4261 | && (mode == SFmode || mode == DFmode)) |
4697a36c | 4262 | { |
4cc833b7 RH |
4263 | if (cum->fregno <= FP_ARG_V4_MAX_REG) |
4264 | cum->fregno++; | |
4265 | else | |
4266 | { | |
4267 | if (mode == DFmode) | |
c4ad648e | 4268 | cum->words += cum->words & 1; |
c53bdcf5 | 4269 | cum->words += rs6000_arg_size (mode, type); |
4cc833b7 | 4270 | } |
4697a36c | 4271 | } |
4cc833b7 RH |
4272 | else |
4273 | { | |
b2d04ecf | 4274 | int n_words = rs6000_arg_size (mode, type); |
4cc833b7 RH |
4275 | int gregno = cum->sysv_gregno; |
4276 | ||
4ed78545 AM |
4277 | /* Long long and SPE vectors are put in (r3,r4), (r5,r6), |
4278 | (r7,r8) or (r9,r10). As does any other 2 word item such | |
4279 | as complex int due to a historical mistake. */ | |
4280 | if (n_words == 2) | |
4281 | gregno += (1 - gregno) & 1; | |
4cc833b7 | 4282 | |
4ed78545 | 4283 | /* Multi-reg args are not split between registers and stack. */ |
4cc833b7 RH |
4284 | if (gregno + n_words - 1 > GP_ARG_MAX_REG) |
4285 | { | |
4ed78545 AM |
4286 | /* Long long and SPE vectors are aligned on the stack. |
4287 | So are other 2 word items such as complex int due to | |
4288 | a historical mistake. */ | |
4cc833b7 RH |
4289 | if (n_words == 2) |
4290 | cum->words += cum->words & 1; | |
4291 | cum->words += n_words; | |
4292 | } | |
4697a36c | 4293 | |
4cc833b7 RH |
4294 | /* Note: continuing to accumulate gregno past when we've started |
4295 | spilling to the stack indicates the fact that we've started | |
4296 | spilling to the stack to expand_builtin_saveregs. */ | |
4297 | cum->sysv_gregno = gregno + n_words; | |
4298 | } | |
4697a36c | 4299 | |
4cc833b7 RH |
4300 | if (TARGET_DEBUG_ARG) |
4301 | { | |
4302 | fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ", | |
4303 | cum->words, cum->fregno); | |
4304 | fprintf (stderr, "gregno = %2d, nargs = %4d, proto = %d, ", | |
4305 | cum->sysv_gregno, cum->nargs_prototype, cum->prototype); | |
4306 | fprintf (stderr, "mode = %4s, named = %d\n", | |
4307 | GET_MODE_NAME (mode), named); | |
4308 | } | |
4697a36c MM |
4309 | } |
4310 | else | |
4cc833b7 | 4311 | { |
b2d04ecf AM |
4312 | int n_words = rs6000_arg_size (mode, type); |
4313 | int align = function_arg_boundary (mode, type) / PARM_BOUNDARY - 1; | |
a4f6c312 | 4314 | |
b2d04ecf AM |
4315 | /* The simple alignment calculation here works because |
4316 | function_arg_boundary / PARM_BOUNDARY will only be 1 or 2. | |
4317 | If we ever want to handle alignments larger than 8 bytes for | |
4318 | 32-bit or 16 bytes for 64-bit, then we'll need to take into | |
4319 | account the offset to the start of the parm save area. */ | |
4320 | align &= cum->words; | |
4321 | cum->words += align + n_words; | |
4697a36c | 4322 | |
a3170dc6 AH |
4323 | if (GET_MODE_CLASS (mode) == MODE_FLOAT |
4324 | && TARGET_HARD_FLOAT && TARGET_FPRS) | |
c53bdcf5 | 4325 | cum->fregno += (GET_MODE_SIZE (mode) + 7) >> 3; |
4cc833b7 RH |
4326 | |
4327 | if (TARGET_DEBUG_ARG) | |
4328 | { | |
4329 | fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ", | |
4330 | cum->words, cum->fregno); | |
4331 | fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s, ", | |
4332 | cum->nargs_prototype, cum->prototype, GET_MODE_NAME (mode)); | |
594a51fe SS |
4333 | fprintf (stderr, "named = %d, align = %d, depth = %d\n", |
4334 | named, align, depth); | |
4cc833b7 RH |
4335 | } |
4336 | } | |
4697a36c | 4337 | } |
a6c9bed4 | 4338 | |
f82f556d AH |
4339 | static rtx |
4340 | spe_build_register_parallel (enum machine_mode mode, int gregno) | |
4341 | { | |
54b695e7 | 4342 | rtx r1, r3; |
f82f556d AH |
4343 | |
4344 | if (mode == DFmode) | |
4345 | { | |
54b695e7 AH |
4346 | r1 = gen_rtx_REG (DImode, gregno); |
4347 | r1 = gen_rtx_EXPR_LIST (VOIDmode, r1, const0_rtx); | |
4348 | return gen_rtx_PARALLEL (mode, gen_rtvec (1, r1)); | |
18f63bfa AH |
4349 | } |
4350 | else if (mode == DCmode) | |
4351 | { | |
54b695e7 AH |
4352 | r1 = gen_rtx_REG (DImode, gregno); |
4353 | r1 = gen_rtx_EXPR_LIST (VOIDmode, r1, const0_rtx); | |
4354 | r3 = gen_rtx_REG (DImode, gregno + 2); | |
4355 | r3 = gen_rtx_EXPR_LIST (VOIDmode, r3, GEN_INT (8)); | |
4356 | return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r3)); | |
f82f556d | 4357 | } |
54b695e7 | 4358 | abort(); |
18f63bfa | 4359 | return NULL_RTX; |
f82f556d | 4360 | } |
b78d48dd | 4361 | |
f82f556d | 4362 | /* Determine where to put a SIMD argument on the SPE. */ |
a6c9bed4 | 4363 | static rtx |
f676971a | 4364 | rs6000_spe_function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode, |
a2369ed3 | 4365 | tree type) |
a6c9bed4 | 4366 | { |
f82f556d AH |
4367 | int gregno = cum->sysv_gregno; |
4368 | ||
4369 | /* On E500 v2, double arithmetic is done on the full 64-bit GPR, but | |
600e1f95 | 4370 | are passed and returned in a pair of GPRs for ABI compatibility. */ |
18f63bfa | 4371 | if (TARGET_E500_DOUBLE && (mode == DFmode || mode == DCmode)) |
f82f556d | 4372 | { |
b5870bee AH |
4373 | int n_words = rs6000_arg_size (mode, type); |
4374 | ||
f82f556d | 4375 | /* Doubles go in an odd/even register pair (r5/r6, etc). */ |
b5870bee AH |
4376 | if (mode == DFmode) |
4377 | gregno += (1 - gregno) & 1; | |
f82f556d | 4378 | |
b5870bee AH |
4379 | /* Multi-reg args are not split between registers and stack. */ |
4380 | if (gregno + n_words - 1 > GP_ARG_MAX_REG) | |
f82f556d AH |
4381 | return NULL_RTX; |
4382 | ||
4383 | return spe_build_register_parallel (mode, gregno); | |
4384 | } | |
a6c9bed4 AH |
4385 | if (cum->stdarg) |
4386 | { | |
c53bdcf5 | 4387 | int n_words = rs6000_arg_size (mode, type); |
a6c9bed4 AH |
4388 | |
4389 | /* SPE vectors are put in odd registers. */ | |
4390 | if (n_words == 2 && (gregno & 1) == 0) | |
4391 | gregno += 1; | |
4392 | ||
4393 | if (gregno + n_words - 1 <= GP_ARG_MAX_REG) | |
4394 | { | |
4395 | rtx r1, r2; | |
4396 | enum machine_mode m = SImode; | |
4397 | ||
4398 | r1 = gen_rtx_REG (m, gregno); | |
4399 | r1 = gen_rtx_EXPR_LIST (m, r1, const0_rtx); | |
4400 | r2 = gen_rtx_REG (m, gregno + 1); | |
4401 | r2 = gen_rtx_EXPR_LIST (m, r2, GEN_INT (4)); | |
4402 | return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r2)); | |
4403 | } | |
4404 | else | |
b78d48dd | 4405 | return NULL_RTX; |
a6c9bed4 AH |
4406 | } |
4407 | else | |
4408 | { | |
f82f556d AH |
4409 | if (gregno <= GP_ARG_MAX_REG) |
4410 | return gen_rtx_REG (mode, gregno); | |
a6c9bed4 | 4411 | else |
b78d48dd | 4412 | return NULL_RTX; |
a6c9bed4 AH |
4413 | } |
4414 | } | |
4415 | ||
0b5383eb DJ |
4416 | /* A subroutine of rs6000_darwin64_record_arg. Assign the bits of the |
4417 | structure between cum->intoffset and bitpos to integer registers. */ | |
594a51fe | 4418 | |
0b5383eb DJ |
4419 | static void |
4420 | rs6000_darwin64_record_arg_flush (CUMULATIVE_ARGS *cum, | |
4421 | HOST_WIDE_INT bitpos, rtx rvec[], int *k) | |
594a51fe | 4422 | { |
0b5383eb DJ |
4423 | enum machine_mode mode; |
4424 | unsigned int regno; | |
4425 | unsigned int startbit, endbit; | |
4426 | int this_regno, intregs, intoffset; | |
4427 | rtx reg; | |
594a51fe | 4428 | |
0b5383eb DJ |
4429 | if (cum->intoffset == -1) |
4430 | return; | |
4431 | ||
4432 | intoffset = cum->intoffset; | |
4433 | cum->intoffset = -1; | |
4434 | ||
4435 | /* If this is the trailing part of a word, try to only load that | |
4436 | much into the register. Otherwise load the whole register. Note | |
4437 | that in the latter case we may pick up unwanted bits. It's not a | |
4438 | problem at the moment but may wish to revisit. */ | |
4439 | ||
4440 | if (intoffset % BITS_PER_WORD != 0) | |
594a51fe | 4441 | { |
0b5383eb DJ |
4442 | mode = mode_for_size (BITS_PER_WORD - intoffset % BITS_PER_WORD, |
4443 | MODE_INT, 0); | |
4444 | if (mode == BLKmode) | |
4445 | { | |
4446 | /* We couldn't find an appropriate mode, which happens, | |
4447 | e.g., in packed structs when there are 3 bytes to load. | |
4448 | Back intoffset back to the beginning of the word in this | |
4449 | case. */ | |
4450 | intoffset = intoffset & -BITS_PER_WORD; | |
4451 | mode = word_mode; | |
4452 | } | |
4453 | } | |
4454 | else | |
4455 | mode = word_mode; | |
4456 | ||
4457 | startbit = intoffset & -BITS_PER_WORD; | |
4458 | endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD; | |
4459 | intregs = (endbit - startbit) / BITS_PER_WORD; | |
4460 | this_regno = cum->words + intoffset / BITS_PER_WORD; | |
4461 | ||
4462 | if (intregs > 0 && intregs > GP_ARG_NUM_REG - this_regno) | |
4463 | cum->use_stack = 1; | |
4464 | ||
4465 | intregs = MIN (intregs, GP_ARG_NUM_REG - this_regno); | |
4466 | if (intregs <= 0) | |
4467 | return; | |
4468 | ||
4469 | intoffset /= BITS_PER_UNIT; | |
4470 | do | |
4471 | { | |
4472 | regno = GP_ARG_MIN_REG + this_regno; | |
4473 | reg = gen_rtx_REG (mode, regno); | |
4474 | rvec[(*k)++] = | |
4475 | gen_rtx_EXPR_LIST (VOIDmode, reg, GEN_INT (intoffset)); | |
4476 | ||
4477 | this_regno += 1; | |
4478 | intoffset = (intoffset | (UNITS_PER_WORD-1)) + 1; | |
4479 | mode = word_mode; | |
4480 | intregs -= 1; | |
4481 | } | |
4482 | while (intregs > 0); | |
4483 | } | |
4484 | ||
4485 | /* Recursive workhorse for the following. */ | |
4486 | ||
4487 | static void | |
4488 | rs6000_darwin64_record_arg_recurse (CUMULATIVE_ARGS *cum, tree type, | |
4489 | HOST_WIDE_INT startbitpos, rtx rvec[], | |
4490 | int *k) | |
4491 | { | |
4492 | tree f; | |
4493 | ||
4494 | for (f = TYPE_FIELDS (type); f ; f = TREE_CHAIN (f)) | |
4495 | if (TREE_CODE (f) == FIELD_DECL) | |
4496 | { | |
4497 | HOST_WIDE_INT bitpos = startbitpos; | |
4498 | tree ftype = TREE_TYPE (f); | |
4499 | enum machine_mode mode = TYPE_MODE (ftype); | |
4500 | ||
4501 | if (DECL_SIZE (f) != 0 | |
4502 | && host_integerp (bit_position (f), 1)) | |
4503 | bitpos += int_bit_position (f); | |
4504 | ||
4505 | /* ??? FIXME: else assume zero offset. */ | |
4506 | ||
4507 | if (TREE_CODE (ftype) == RECORD_TYPE) | |
4508 | rs6000_darwin64_record_arg_recurse (cum, ftype, bitpos, rvec, k); | |
4509 | else if (cum->named && USE_FP_FOR_ARG_P (cum, mode, ftype)) | |
594a51fe | 4510 | { |
0b5383eb DJ |
4511 | #if 0 |
4512 | switch (mode) | |
594a51fe | 4513 | { |
0b5383eb DJ |
4514 | case SCmode: mode = SFmode; break; |
4515 | case DCmode: mode = DFmode; break; | |
4516 | case TCmode: mode = TFmode; break; | |
4517 | default: break; | |
594a51fe | 4518 | } |
0b5383eb DJ |
4519 | #endif |
4520 | rs6000_darwin64_record_arg_flush (cum, bitpos, rvec, k); | |
4521 | rvec[(*k)++] | |
4522 | = gen_rtx_EXPR_LIST (VOIDmode, | |
4523 | gen_rtx_REG (mode, cum->fregno++), | |
4524 | GEN_INT (bitpos / BITS_PER_UNIT)); | |
4525 | if (mode == TFmode) | |
4526 | cum->fregno++; | |
594a51fe | 4527 | } |
0b5383eb DJ |
4528 | else if (cum->named && USE_ALTIVEC_FOR_ARG_P (cum, mode, ftype, 1)) |
4529 | { | |
4530 | rs6000_darwin64_record_arg_flush (cum, bitpos, rvec, k); | |
4531 | rvec[(*k)++] | |
4532 | = gen_rtx_EXPR_LIST (VOIDmode, | |
4533 | gen_rtx_REG (mode, cum->vregno++), | |
4534 | GEN_INT (bitpos / BITS_PER_UNIT)); | |
4535 | } | |
4536 | else if (cum->intoffset == -1) | |
4537 | cum->intoffset = bitpos; | |
4538 | } | |
4539 | } | |
594a51fe | 4540 | |
0b5383eb DJ |
4541 | /* For the darwin64 ABI, we want to construct a PARALLEL consisting of |
4542 | the register(s) to be used for each field and subfield of a struct | |
4543 | being passed by value, along with the offset of where the | |
4544 | register's value may be found in the block. FP fields go in FP | |
4545 | register, vector fields go in vector registers, and everything | |
4546 | else goes in int registers, packed as in memory. | |
8ff40a74 | 4547 | |
0b5383eb DJ |
4548 | This code is also used for function return values. RETVAL indicates |
4549 | whether this is the case. | |
8ff40a74 | 4550 | |
0b5383eb DJ |
4551 | Much of this is taken from the Sparc V9 port, which has a similar |
4552 | calling convention. */ | |
594a51fe | 4553 | |
0b5383eb DJ |
4554 | static rtx |
4555 | rs6000_darwin64_record_arg (CUMULATIVE_ARGS *orig_cum, tree type, | |
4556 | int named, bool retval) | |
4557 | { | |
4558 | rtx rvec[FIRST_PSEUDO_REGISTER]; | |
4559 | int k = 1, kbase = 1; | |
4560 | HOST_WIDE_INT typesize = int_size_in_bytes (type); | |
4561 | /* This is a copy; modifications are not visible to our caller. */ | |
4562 | CUMULATIVE_ARGS copy_cum = *orig_cum; | |
4563 | CUMULATIVE_ARGS *cum = ©_cum; | |
4564 | ||
4565 | /* Pad to 16 byte boundary if needed. */ | |
4566 | if (!retval && TYPE_ALIGN (type) >= 2 * BITS_PER_WORD | |
4567 | && (cum->words % 2) != 0) | |
4568 | cum->words++; | |
4569 | ||
4570 | cum->intoffset = 0; | |
4571 | cum->use_stack = 0; | |
4572 | cum->named = named; | |
4573 | ||
4574 | /* Put entries into rvec[] for individual FP and vector fields, and | |
4575 | for the chunks of memory that go in int regs. Note we start at | |
4576 | element 1; 0 is reserved for an indication of using memory, and | |
4577 | may or may not be filled in below. */ | |
4578 | rs6000_darwin64_record_arg_recurse (cum, type, 0, rvec, &k); | |
4579 | rs6000_darwin64_record_arg_flush (cum, typesize * BITS_PER_UNIT, rvec, &k); | |
4580 | ||
4581 | /* If any part of the struct went on the stack put all of it there. | |
4582 | This hack is because the generic code for | |
4583 | FUNCTION_ARG_PARTIAL_NREGS cannot handle cases where the register | |
4584 | parts of the struct are not at the beginning. */ | |
4585 | if (cum->use_stack) | |
4586 | { | |
4587 | if (retval) | |
4588 | return NULL_RTX; /* doesn't go in registers at all */ | |
4589 | kbase = 0; | |
4590 | rvec[0] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx); | |
4591 | } | |
4592 | if (k > 1 || cum->use_stack) | |
4593 | return gen_rtx_PARALLEL (BLKmode, gen_rtvec_v (k - kbase, &rvec[kbase])); | |
594a51fe SS |
4594 | else |
4595 | return NULL_RTX; | |
4596 | } | |
4597 | ||
b78d48dd FJ |
4598 | /* Determine where to place an argument in 64-bit mode with 32-bit ABI. */ |
4599 | ||
4600 | static rtx | |
ec6376ab | 4601 | rs6000_mixed_function_arg (enum machine_mode mode, tree type, int align_words) |
b78d48dd | 4602 | { |
ec6376ab AM |
4603 | int n_units; |
4604 | int i, k; | |
4605 | rtx rvec[GP_ARG_NUM_REG + 1]; | |
4606 | ||
4607 | if (align_words >= GP_ARG_NUM_REG) | |
4608 | return NULL_RTX; | |
4609 | ||
4610 | n_units = rs6000_arg_size (mode, type); | |
4611 | ||
4612 | /* Optimize the simple case where the arg fits in one gpr, except in | |
4613 | the case of BLKmode due to assign_parms assuming that registers are | |
4614 | BITS_PER_WORD wide. */ | |
4615 | if (n_units == 0 | |
4616 | || (n_units == 1 && mode != BLKmode)) | |
4617 | return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words); | |
4618 | ||
4619 | k = 0; | |
4620 | if (align_words + n_units > GP_ARG_NUM_REG) | |
4621 | /* Not all of the arg fits in gprs. Say that it goes in memory too, | |
4622 | using a magic NULL_RTX component. | |
4623 | FIXME: This is not strictly correct. Only some of the arg | |
4624 | belongs in memory, not all of it. However, there isn't any way | |
4625 | to do this currently, apart from building rtx descriptions for | |
4626 | the pieces of memory we want stored. Due to bugs in the generic | |
4627 | code we can't use the normal function_arg_partial_nregs scheme | |
4628 | with the PARALLEL arg description we emit here. | |
4629 | In any case, the code to store the whole arg to memory is often | |
4630 | more efficient than code to store pieces, and we know that space | |
4631 | is available in the right place for the whole arg. */ | |
78a52f11 RH |
4632 | /* FIXME: This should be fixed since the conversion to |
4633 | TARGET_ARG_PARTIAL_BYTES. */ | |
ec6376ab AM |
4634 | rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx); |
4635 | ||
4636 | i = 0; | |
4637 | do | |
36a454e1 | 4638 | { |
ec6376ab AM |
4639 | rtx r = gen_rtx_REG (SImode, GP_ARG_MIN_REG + align_words); |
4640 | rtx off = GEN_INT (i++ * 4); | |
4641 | rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off); | |
36a454e1 | 4642 | } |
ec6376ab AM |
4643 | while (++align_words < GP_ARG_NUM_REG && --n_units != 0); |
4644 | ||
4645 | return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec)); | |
b78d48dd FJ |
4646 | } |
4647 | ||
4697a36c MM |
4648 | /* Determine where to put an argument to a function. |
4649 | Value is zero to push the argument on the stack, | |
4650 | or a hard register in which to store the argument. | |
4651 | ||
4652 | MODE is the argument's machine mode. | |
4653 | TYPE is the data type of the argument (as a tree). | |
4654 | This is null for libcalls where that information may | |
4655 | not be available. | |
4656 | CUM is a variable of type CUMULATIVE_ARGS which gives info about | |
0b5383eb DJ |
4657 | the preceding args and about the function being called. It is |
4658 | not modified in this routine. | |
4697a36c MM |
4659 | NAMED is nonzero if this argument is a named parameter |
4660 | (otherwise it is an extra parameter matching an ellipsis). | |
4661 | ||
4662 | On RS/6000 the first eight words of non-FP are normally in registers | |
4663 | and the rest are pushed. Under AIX, the first 13 FP args are in registers. | |
4664 | Under V.4, the first 8 FP args are in registers. | |
4665 | ||
4666 | If this is floating-point and no prototype is specified, we use | |
4667 | both an FP and integer register (or possibly FP reg and stack). Library | |
b9599e46 | 4668 | functions (when CALL_LIBCALL is set) always have the proper types for args, |
4697a36c | 4669 | so we can pass the FP value just in one register. emit_library_function |
b2d04ecf AM |
4670 | doesn't support PARALLEL anyway. |
4671 | ||
4672 | Note that for args passed by reference, function_arg will be called | |
4673 | with MODE and TYPE set to that of the pointer to the arg, not the arg | |
4674 | itself. */ | |
4697a36c MM |
4675 | |
4676 | struct rtx_def * | |
f676971a | 4677 | function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode, |
a2369ed3 | 4678 | tree type, int named) |
4697a36c | 4679 | { |
4cc833b7 | 4680 | enum rs6000_abi abi = DEFAULT_ABI; |
4697a36c | 4681 | |
a4f6c312 SS |
4682 | /* Return a marker to indicate whether CR1 needs to set or clear the |
4683 | bit that V.4 uses to say fp args were passed in registers. | |
4684 | Assume that we don't need the marker for software floating point, | |
4685 | or compiler generated library calls. */ | |
4697a36c MM |
4686 | if (mode == VOIDmode) |
4687 | { | |
f607bc57 | 4688 | if (abi == ABI_V4 |
7509c759 | 4689 | && cum->nargs_prototype < 0 |
b9599e46 FS |
4690 | && (cum->call_cookie & CALL_LIBCALL) == 0 |
4691 | && (cum->prototype || TARGET_NO_PROTOTYPE)) | |
7509c759 | 4692 | { |
a3170dc6 AH |
4693 | /* For the SPE, we need to crxor CR6 always. */ |
4694 | if (TARGET_SPE_ABI) | |
4695 | return GEN_INT (cum->call_cookie | CALL_V4_SET_FP_ARGS); | |
4696 | else if (TARGET_HARD_FLOAT && TARGET_FPRS) | |
4697 | return GEN_INT (cum->call_cookie | |
4698 | | ((cum->fregno == FP_ARG_MIN_REG) | |
4699 | ? CALL_V4_SET_FP_ARGS | |
4700 | : CALL_V4_CLEAR_FP_ARGS)); | |
7509c759 | 4701 | } |
4697a36c | 4702 | |
7509c759 | 4703 | return GEN_INT (cum->call_cookie); |
4697a36c MM |
4704 | } |
4705 | ||
0b5383eb DJ |
4706 | if (rs6000_darwin64_abi && mode == BLKmode |
4707 | && TREE_CODE (type) == RECORD_TYPE) | |
8ff40a74 | 4708 | { |
0b5383eb | 4709 | rtx rslt = rs6000_darwin64_record_arg (cum, type, named, false); |
8ff40a74 SS |
4710 | if (rslt != NULL_RTX) |
4711 | return rslt; | |
4712 | /* Else fall through to usual handling. */ | |
4713 | } | |
4714 | ||
2858f73a | 4715 | if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named)) |
c72d6c26 HP |
4716 | if (TARGET_64BIT && ! cum->prototype) |
4717 | { | |
c4ad648e AM |
4718 | /* Vector parameters get passed in vector register |
4719 | and also in GPRs or memory, in absence of prototype. */ | |
4720 | int align_words; | |
4721 | rtx slot; | |
4722 | align_words = (cum->words + 1) & ~1; | |
4723 | ||
4724 | if (align_words >= GP_ARG_NUM_REG) | |
4725 | { | |
4726 | slot = NULL_RTX; | |
4727 | } | |
4728 | else | |
4729 | { | |
4730 | slot = gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words); | |
4731 | } | |
4732 | return gen_rtx_PARALLEL (mode, | |
4733 | gen_rtvec (2, | |
4734 | gen_rtx_EXPR_LIST (VOIDmode, | |
4735 | slot, const0_rtx), | |
4736 | gen_rtx_EXPR_LIST (VOIDmode, | |
4737 | gen_rtx_REG (mode, cum->vregno), | |
4738 | const0_rtx))); | |
c72d6c26 HP |
4739 | } |
4740 | else | |
4741 | return gen_rtx_REG (mode, cum->vregno); | |
ad630bef DE |
4742 | else if (TARGET_ALTIVEC_ABI |
4743 | && (ALTIVEC_VECTOR_MODE (mode) | |
4744 | || (type && TREE_CODE (type) == VECTOR_TYPE | |
4745 | && int_size_in_bytes (type) == 16))) | |
0ac081f6 | 4746 | { |
2858f73a | 4747 | if (named || abi == ABI_V4) |
a594a19c | 4748 | return NULL_RTX; |
0ac081f6 | 4749 | else |
a594a19c GK |
4750 | { |
4751 | /* Vector parameters to varargs functions under AIX or Darwin | |
4752 | get passed in memory and possibly also in GPRs. */ | |
ec6376ab AM |
4753 | int align, align_words, n_words; |
4754 | enum machine_mode part_mode; | |
a594a19c GK |
4755 | |
4756 | /* Vector parameters must be 16-byte aligned. This places them at | |
2858f73a GK |
4757 | 2 mod 4 in terms of words in 32-bit mode, since the parameter |
4758 | save area starts at offset 24 from the stack. In 64-bit mode, | |
4759 | they just have to start on an even word, since the parameter | |
4760 | save area is 16-byte aligned. */ | |
4761 | if (TARGET_32BIT) | |
4ed78545 | 4762 | align = (2 - cum->words) & 3; |
2858f73a GK |
4763 | else |
4764 | align = cum->words & 1; | |
a594a19c GK |
4765 | align_words = cum->words + align; |
4766 | ||
4767 | /* Out of registers? Memory, then. */ | |
4768 | if (align_words >= GP_ARG_NUM_REG) | |
4769 | return NULL_RTX; | |
ec6376ab AM |
4770 | |
4771 | if (TARGET_32BIT && TARGET_POWERPC64) | |
4772 | return rs6000_mixed_function_arg (mode, type, align_words); | |
4773 | ||
2858f73a GK |
4774 | /* The vector value goes in GPRs. Only the part of the |
4775 | value in GPRs is reported here. */ | |
ec6376ab AM |
4776 | part_mode = mode; |
4777 | n_words = rs6000_arg_size (mode, type); | |
4778 | if (align_words + n_words > GP_ARG_NUM_REG) | |
839a4992 | 4779 | /* Fortunately, there are only two possibilities, the value |
2858f73a GK |
4780 | is either wholly in GPRs or half in GPRs and half not. */ |
4781 | part_mode = DImode; | |
ec6376ab AM |
4782 | |
4783 | return gen_rtx_REG (part_mode, GP_ARG_MIN_REG + align_words); | |
a594a19c | 4784 | } |
0ac081f6 | 4785 | } |
f82f556d AH |
4786 | else if (TARGET_SPE_ABI && TARGET_SPE |
4787 | && (SPE_VECTOR_MODE (mode) | |
18f63bfa AH |
4788 | || (TARGET_E500_DOUBLE && (mode == DFmode |
4789 | || mode == DCmode)))) | |
a6c9bed4 | 4790 | return rs6000_spe_function_arg (cum, mode, type); |
594a51fe | 4791 | |
f607bc57 | 4792 | else if (abi == ABI_V4) |
4697a36c | 4793 | { |
a3170dc6 | 4794 | if (TARGET_HARD_FLOAT && TARGET_FPRS |
4cc833b7 RH |
4795 | && (mode == SFmode || mode == DFmode)) |
4796 | { | |
4797 | if (cum->fregno <= FP_ARG_V4_MAX_REG) | |
4798 | return gen_rtx_REG (mode, cum->fregno); | |
4799 | else | |
b78d48dd | 4800 | return NULL_RTX; |
4cc833b7 RH |
4801 | } |
4802 | else | |
4803 | { | |
b2d04ecf | 4804 | int n_words = rs6000_arg_size (mode, type); |
4cc833b7 RH |
4805 | int gregno = cum->sysv_gregno; |
4806 | ||
4ed78545 AM |
4807 | /* Long long and SPE vectors are put in (r3,r4), (r5,r6), |
4808 | (r7,r8) or (r9,r10). As does any other 2 word item such | |
4809 | as complex int due to a historical mistake. */ | |
4810 | if (n_words == 2) | |
4811 | gregno += (1 - gregno) & 1; | |
4cc833b7 | 4812 | |
4ed78545 | 4813 | /* Multi-reg args are not split between registers and stack. */ |
ec6376ab | 4814 | if (gregno + n_words - 1 > GP_ARG_MAX_REG) |
b78d48dd | 4815 | return NULL_RTX; |
ec6376ab AM |
4816 | |
4817 | if (TARGET_32BIT && TARGET_POWERPC64) | |
4818 | return rs6000_mixed_function_arg (mode, type, | |
4819 | gregno - GP_ARG_MIN_REG); | |
4820 | return gen_rtx_REG (mode, gregno); | |
4cc833b7 | 4821 | } |
4697a36c | 4822 | } |
4cc833b7 RH |
4823 | else |
4824 | { | |
b2d04ecf AM |
4825 | int align = function_arg_boundary (mode, type) / PARM_BOUNDARY - 1; |
4826 | int align_words = cum->words + (cum->words & align); | |
b78d48dd | 4827 | |
2858f73a | 4828 | if (USE_FP_FOR_ARG_P (cum, mode, type)) |
4cc833b7 | 4829 | { |
ec6376ab AM |
4830 | rtx rvec[GP_ARG_NUM_REG + 1]; |
4831 | rtx r; | |
4832 | int k; | |
c53bdcf5 AM |
4833 | bool needs_psave; |
4834 | enum machine_mode fmode = mode; | |
c53bdcf5 AM |
4835 | unsigned long n_fpreg = (GET_MODE_SIZE (mode) + 7) >> 3; |
4836 | ||
4837 | if (cum->fregno + n_fpreg > FP_ARG_MAX_REG + 1) | |
4838 | { | |
c53bdcf5 AM |
4839 | /* Currently, we only ever need one reg here because complex |
4840 | doubles are split. */ | |
ec6376ab | 4841 | if (cum->fregno != FP_ARG_MAX_REG || fmode != TFmode) |
c53bdcf5 | 4842 | abort (); |
ec6376ab AM |
4843 | |
4844 | /* Long double split over regs and memory. */ | |
4845 | fmode = DFmode; | |
c53bdcf5 | 4846 | } |
c53bdcf5 AM |
4847 | |
4848 | /* Do we also need to pass this arg in the parameter save | |
4849 | area? */ | |
4850 | needs_psave = (type | |
4851 | && (cum->nargs_prototype <= 0 | |
4852 | || (DEFAULT_ABI == ABI_AIX | |
de17c25f | 4853 | && TARGET_XL_COMPAT |
c53bdcf5 AM |
4854 | && align_words >= GP_ARG_NUM_REG))); |
4855 | ||
4856 | if (!needs_psave && mode == fmode) | |
ec6376ab | 4857 | return gen_rtx_REG (fmode, cum->fregno); |
c53bdcf5 | 4858 | |
ec6376ab | 4859 | k = 0; |
c53bdcf5 AM |
4860 | if (needs_psave) |
4861 | { | |
ec6376ab | 4862 | /* Describe the part that goes in gprs or the stack. |
c53bdcf5 | 4863 | This piece must come first, before the fprs. */ |
c53bdcf5 AM |
4864 | if (align_words < GP_ARG_NUM_REG) |
4865 | { | |
4866 | unsigned long n_words = rs6000_arg_size (mode, type); | |
ec6376ab AM |
4867 | |
4868 | if (align_words + n_words > GP_ARG_NUM_REG | |
4869 | || (TARGET_32BIT && TARGET_POWERPC64)) | |
4870 | { | |
4871 | /* If this is partially on the stack, then we only | |
4872 | include the portion actually in registers here. */ | |
4873 | enum machine_mode rmode = TARGET_32BIT ? SImode : DImode; | |
4874 | rtx off; | |
2e6c9641 | 4875 | int i=0; |
c4ad648e AM |
4876 | if (align_words + n_words > GP_ARG_NUM_REG |
4877 | && (TARGET_32BIT && TARGET_POWERPC64)) | |
4878 | /* Not all of the arg fits in gprs. Say that it | |
4879 | goes in memory too, using a magic NULL_RTX | |
4880 | component. Also see comment in | |
4881 | rs6000_mixed_function_arg for why the normal | |
4882 | function_arg_partial_nregs scheme doesn't work | |
4883 | in this case. */ | |
4884 | rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, | |
4885 | const0_rtx); | |
ec6376ab AM |
4886 | do |
4887 | { | |
4888 | r = gen_rtx_REG (rmode, | |
4889 | GP_ARG_MIN_REG + align_words); | |
2e6c9641 | 4890 | off = GEN_INT (i++ * GET_MODE_SIZE (rmode)); |
ec6376ab AM |
4891 | rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off); |
4892 | } | |
4893 | while (++align_words < GP_ARG_NUM_REG && --n_words != 0); | |
4894 | } | |
4895 | else | |
4896 | { | |
4897 | /* The whole arg fits in gprs. */ | |
4898 | r = gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words); | |
4899 | rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, const0_rtx); | |
4900 | } | |
c53bdcf5 | 4901 | } |
ec6376ab AM |
4902 | else |
4903 | /* It's entirely in memory. */ | |
4904 | rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx); | |
c53bdcf5 AM |
4905 | } |
4906 | ||
ec6376ab AM |
4907 | /* Describe where this piece goes in the fprs. */ |
4908 | r = gen_rtx_REG (fmode, cum->fregno); | |
4909 | rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, const0_rtx); | |
4910 | ||
4911 | return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec)); | |
4cc833b7 RH |
4912 | } |
4913 | else if (align_words < GP_ARG_NUM_REG) | |
b2d04ecf | 4914 | { |
ec6376ab AM |
4915 | if (TARGET_32BIT && TARGET_POWERPC64) |
4916 | return rs6000_mixed_function_arg (mode, type, align_words); | |
b2d04ecf | 4917 | |
4eeca74f AM |
4918 | if (mode == BLKmode) |
4919 | mode = Pmode; | |
4920 | ||
b2d04ecf AM |
4921 | return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words); |
4922 | } | |
4cc833b7 RH |
4923 | else |
4924 | return NULL_RTX; | |
4697a36c | 4925 | } |
4697a36c MM |
4926 | } |
4927 | \f | |
ec6376ab AM |
4928 | /* For an arg passed partly in registers and partly in memory, this is |
4929 | the number of registers used. For args passed entirely in registers | |
4930 | or entirely in memory, zero. When an arg is described by a PARALLEL, | |
4931 | perhaps using more than one register type, this function returns the | |
78a52f11 | 4932 | number of bytes of registers used by the PARALLEL. */ |
4697a36c | 4933 | |
78a52f11 RH |
4934 | static int |
4935 | rs6000_arg_partial_bytes (CUMULATIVE_ARGS *cum, enum machine_mode mode, | |
4936 | tree type, bool named) | |
4697a36c | 4937 | { |
c53bdcf5 | 4938 | int ret = 0; |
ec6376ab AM |
4939 | int align; |
4940 | int parm_offset; | |
4941 | int align_words; | |
c53bdcf5 | 4942 | |
f607bc57 | 4943 | if (DEFAULT_ABI == ABI_V4) |
4697a36c | 4944 | return 0; |
4697a36c | 4945 | |
c53bdcf5 AM |
4946 | if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named) |
4947 | && cum->nargs_prototype >= 0) | |
4948 | return 0; | |
4949 | ||
0b5383eb DJ |
4950 | /* In this complicated case we just disable the partial_nregs code. */ |
4951 | if (rs6000_darwin64_abi && mode == BLKmode | |
4952 | && TREE_CODE (type) == RECORD_TYPE | |
4953 | && int_size_in_bytes (type) > 0) | |
4954 | return 0; | |
4955 | ||
ec6376ab AM |
4956 | align = function_arg_boundary (mode, type) / PARM_BOUNDARY - 1; |
4957 | parm_offset = TARGET_32BIT ? 2 : 0; | |
4958 | align_words = cum->words + ((parm_offset - cum->words) & align); | |
4959 | ||
4960 | if (USE_FP_FOR_ARG_P (cum, mode, type) | |
4961 | /* If we are passing this arg in gprs as well, then this function | |
4962 | should return the number of gprs (or memory) partially passed, | |
4963 | *not* the number of fprs. */ | |
4964 | && !(type | |
4965 | && (cum->nargs_prototype <= 0 | |
4966 | || (DEFAULT_ABI == ABI_AIX | |
de17c25f | 4967 | && TARGET_XL_COMPAT |
ec6376ab | 4968 | && align_words >= GP_ARG_NUM_REG)))) |
4697a36c | 4969 | { |
c53bdcf5 | 4970 | if (cum->fregno + ((GET_MODE_SIZE (mode) + 7) >> 3) > FP_ARG_MAX_REG + 1) |
ec6376ab | 4971 | ret = FP_ARG_MAX_REG + 1 - cum->fregno; |
c53bdcf5 | 4972 | else if (cum->nargs_prototype >= 0) |
4697a36c MM |
4973 | return 0; |
4974 | } | |
4975 | ||
ec6376ab AM |
4976 | if (align_words < GP_ARG_NUM_REG |
4977 | && GP_ARG_NUM_REG < align_words + rs6000_arg_size (mode, type)) | |
4978 | ret = GP_ARG_NUM_REG - align_words; | |
4697a36c | 4979 | |
78a52f11 RH |
4980 | ret *= (TARGET_32BIT ? 4 : 8); |
4981 | ||
c53bdcf5 | 4982 | if (ret != 0 && TARGET_DEBUG_ARG) |
78a52f11 | 4983 | fprintf (stderr, "rs6000_arg_partial_bytes: %d\n", ret); |
4697a36c | 4984 | |
c53bdcf5 | 4985 | return ret; |
4697a36c MM |
4986 | } |
4987 | \f | |
4988 | /* A C expression that indicates when an argument must be passed by | |
4989 | reference. If nonzero for an argument, a copy of that argument is | |
4990 | made in memory and a pointer to the argument is passed instead of | |
4991 | the argument itself. The pointer is passed in whatever way is | |
4992 | appropriate for passing a pointer to that type. | |
4993 | ||
b2d04ecf AM |
4994 | Under V.4, aggregates and long double are passed by reference. |
4995 | ||
4996 | As an extension to all 32-bit ABIs, AltiVec vectors are passed by | |
4997 | reference unless the AltiVec vector extension ABI is in force. | |
c8c99a68 DE |
4998 | |
4999 | As an extension to all ABIs, variable sized types are passed by | |
5000 | reference. */ | |
4697a36c | 5001 | |
8cd5a4e0 | 5002 | static bool |
f676971a | 5003 | rs6000_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED, |
bada2eb8 DE |
5004 | enum machine_mode mode, tree type, |
5005 | bool named ATTRIBUTE_UNUSED) | |
4697a36c | 5006 | { |
bada2eb8 | 5007 | if (DEFAULT_ABI == ABI_V4 && mode == TFmode) |
4697a36c MM |
5008 | { |
5009 | if (TARGET_DEBUG_ARG) | |
bada2eb8 DE |
5010 | fprintf (stderr, "function_arg_pass_by_reference: V4 long double\n"); |
5011 | return 1; | |
5012 | } | |
5013 | ||
5014 | if (!type) | |
5015 | return 0; | |
4697a36c | 5016 | |
bada2eb8 DE |
5017 | if (DEFAULT_ABI == ABI_V4 && AGGREGATE_TYPE_P (type)) |
5018 | { | |
5019 | if (TARGET_DEBUG_ARG) | |
5020 | fprintf (stderr, "function_arg_pass_by_reference: V4 aggregate\n"); | |
5021 | return 1; | |
5022 | } | |
5023 | ||
5024 | if (int_size_in_bytes (type) < 0) | |
5025 | { | |
5026 | if (TARGET_DEBUG_ARG) | |
5027 | fprintf (stderr, "function_arg_pass_by_reference: variable size\n"); | |
5028 | return 1; | |
5029 | } | |
5030 | ||
5031 | /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector | |
5032 | modes only exist for GCC vector types if -maltivec. */ | |
5033 | if (TARGET_32BIT && !TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode)) | |
5034 | { | |
5035 | if (TARGET_DEBUG_ARG) | |
5036 | fprintf (stderr, "function_arg_pass_by_reference: AltiVec\n"); | |
4697a36c MM |
5037 | return 1; |
5038 | } | |
b693336b PB |
5039 | |
5040 | /* Pass synthetic vectors in memory. */ | |
bada2eb8 | 5041 | if (TREE_CODE (type) == VECTOR_TYPE |
ad630bef | 5042 | && int_size_in_bytes (type) > (TARGET_ALTIVEC_ABI ? 16 : 8)) |
b693336b PB |
5043 | { |
5044 | static bool warned_for_pass_big_vectors = false; | |
5045 | if (TARGET_DEBUG_ARG) | |
5046 | fprintf (stderr, "function_arg_pass_by_reference: synthetic vector\n"); | |
5047 | if (!warned_for_pass_big_vectors) | |
5048 | { | |
bada2eb8 | 5049 | warning ("GCC vector passed by reference: " |
b693336b PB |
5050 | "non-standard ABI extension with no compatibility guarantee"); |
5051 | warned_for_pass_big_vectors = true; | |
5052 | } | |
5053 | return 1; | |
5054 | } | |
5055 | ||
b2d04ecf | 5056 | return 0; |
4697a36c | 5057 | } |
5985c7a6 FJ |
5058 | |
5059 | static void | |
2d9db8eb | 5060 | rs6000_move_block_from_reg (int regno, rtx x, int nregs) |
5985c7a6 FJ |
5061 | { |
5062 | int i; | |
5063 | enum machine_mode reg_mode = TARGET_32BIT ? SImode : DImode; | |
5064 | ||
5065 | if (nregs == 0) | |
5066 | return; | |
5067 | ||
c4ad648e | 5068 | for (i = 0; i < nregs; i++) |
5985c7a6 FJ |
5069 | { |
5070 | rtx tem = adjust_address_nv (x, reg_mode, i*GET_MODE_SIZE(reg_mode)); | |
5071 | if (reload_completed) | |
c4ad648e AM |
5072 | { |
5073 | if (! strict_memory_address_p (reg_mode, XEXP (tem, 0))) | |
5074 | tem = NULL_RTX; | |
5075 | else | |
5076 | tem = simplify_gen_subreg (reg_mode, x, BLKmode, | |
5077 | i * GET_MODE_SIZE(reg_mode)); | |
5078 | } | |
5985c7a6 FJ |
5079 | else |
5080 | tem = replace_equiv_address (tem, XEXP (tem, 0)); | |
5081 | ||
5082 | if (tem == NULL_RTX) | |
c4ad648e | 5083 | abort (); |
5985c7a6 FJ |
5084 | |
5085 | emit_move_insn (tem, gen_rtx_REG (reg_mode, regno + i)); | |
5086 | } | |
5087 | } | |
4697a36c MM |
5088 | \f |
5089 | /* Perform any needed actions needed for a function that is receiving a | |
f676971a | 5090 | variable number of arguments. |
4697a36c MM |
5091 | |
5092 | CUM is as above. | |
5093 | ||
5094 | MODE and TYPE are the mode and type of the current parameter. | |
5095 | ||
5096 | PRETEND_SIZE is a variable that should be set to the amount of stack | |
5097 | that must be pushed by the prolog to pretend that our caller pushed | |
5098 | it. | |
5099 | ||
5100 | Normally, this macro will push all remaining incoming registers on the | |
5101 | stack and set PRETEND_SIZE to the length of the registers pushed. */ | |
5102 | ||
c6e8c921 | 5103 | static void |
f676971a | 5104 | setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode, |
c4ad648e AM |
5105 | tree type, int *pretend_size ATTRIBUTE_UNUSED, |
5106 | int no_rtl) | |
4697a36c | 5107 | { |
4cc833b7 RH |
5108 | CUMULATIVE_ARGS next_cum; |
5109 | int reg_size = TARGET_32BIT ? 4 : 8; | |
ca5adc63 | 5110 | rtx save_area = NULL_RTX, mem; |
dfafc897 | 5111 | int first_reg_offset, set; |
4697a36c | 5112 | |
f31bf321 | 5113 | /* Skip the last named argument. */ |
d34c5b80 | 5114 | next_cum = *cum; |
594a51fe | 5115 | function_arg_advance (&next_cum, mode, type, 1, 0); |
4cc833b7 | 5116 | |
f607bc57 | 5117 | if (DEFAULT_ABI == ABI_V4) |
d34c5b80 | 5118 | { |
60e2d0ca | 5119 | if (! no_rtl) |
2c4974b7 | 5120 | save_area = plus_constant (virtual_stack_vars_rtx, |
bd227acc | 5121 | - RS6000_VARARGS_SIZE); |
4cc833b7 RH |
5122 | |
5123 | first_reg_offset = next_cum.sysv_gregno - GP_ARG_MIN_REG; | |
4697a36c | 5124 | } |
60e2d0ca | 5125 | else |
4697a36c | 5126 | { |
d34c5b80 | 5127 | first_reg_offset = next_cum.words; |
4cc833b7 | 5128 | save_area = virtual_incoming_args_rtx; |
4697a36c | 5129 | |
fe984136 | 5130 | if (targetm.calls.must_pass_in_stack (mode, type)) |
c53bdcf5 | 5131 | first_reg_offset += rs6000_arg_size (TYPE_MODE (type), type); |
4cc833b7 | 5132 | } |
4697a36c | 5133 | |
dfafc897 | 5134 | set = get_varargs_alias_set (); |
5496b36f | 5135 | if (! no_rtl && first_reg_offset < GP_ARG_NUM_REG) |
4cc833b7 | 5136 | { |
dfafc897 | 5137 | mem = gen_rtx_MEM (BLKmode, |
c4ad648e | 5138 | plus_constant (save_area, |
dfafc897 | 5139 | first_reg_offset * reg_size)), |
ba4828e0 | 5140 | set_mem_alias_set (mem, set); |
8ac61af7 | 5141 | set_mem_align (mem, BITS_PER_WORD); |
dfafc897 | 5142 | |
f676971a | 5143 | rs6000_move_block_from_reg (GP_ARG_MIN_REG + first_reg_offset, mem, |
c4ad648e | 5144 | GP_ARG_NUM_REG - first_reg_offset); |
4697a36c MM |
5145 | } |
5146 | ||
4697a36c | 5147 | /* Save FP registers if needed. */ |
f607bc57 | 5148 | if (DEFAULT_ABI == ABI_V4 |
a3170dc6 AH |
5149 | && TARGET_HARD_FLOAT && TARGET_FPRS |
5150 | && ! no_rtl | |
5496b36f | 5151 | && next_cum.fregno <= FP_ARG_V4_MAX_REG) |
4697a36c | 5152 | { |
5496b36f | 5153 | int fregno = next_cum.fregno; |
9ebbca7d | 5154 | rtx cr1 = gen_rtx_REG (CCmode, CR1_REGNO); |
4cc833b7 RH |
5155 | rtx lab = gen_label_rtx (); |
5156 | int off = (GP_ARG_NUM_REG * reg_size) + ((fregno - FP_ARG_MIN_REG) * 8); | |
4697a36c | 5157 | |
c4ad648e AM |
5158 | emit_jump_insn |
5159 | (gen_rtx_SET (VOIDmode, | |
5160 | pc_rtx, | |
5161 | gen_rtx_IF_THEN_ELSE (VOIDmode, | |
4cc833b7 | 5162 | gen_rtx_NE (VOIDmode, cr1, |
c4ad648e | 5163 | const0_rtx), |
39403d82 | 5164 | gen_rtx_LABEL_REF (VOIDmode, lab), |
4697a36c MM |
5165 | pc_rtx))); |
5166 | ||
5496b36f | 5167 | while (fregno <= FP_ARG_V4_MAX_REG) |
4cc833b7 | 5168 | { |
5496b36f | 5169 | mem = gen_rtx_MEM (DFmode, plus_constant (save_area, off)); |
c4ad648e | 5170 | set_mem_alias_set (mem, set); |
94ff898d | 5171 | set_mem_align (mem, GET_MODE_ALIGNMENT (DFmode)); |
dfafc897 | 5172 | emit_move_insn (mem, gen_rtx_REG (DFmode, fregno)); |
5496b36f JJ |
5173 | fregno++; |
5174 | off += 8; | |
4697a36c | 5175 | } |
4cc833b7 RH |
5176 | |
5177 | emit_label (lab); | |
4697a36c | 5178 | } |
4697a36c | 5179 | } |
4697a36c | 5180 | |
dfafc897 | 5181 | /* Create the va_list data type. */ |
2c4974b7 | 5182 | |
c35d187f RH |
5183 | static tree |
5184 | rs6000_build_builtin_va_list (void) | |
dfafc897 | 5185 | { |
64c2816f | 5186 | tree f_gpr, f_fpr, f_res, f_ovf, f_sav, record, type_decl; |
4697a36c | 5187 | |
9ebbca7d GK |
5188 | /* For AIX, prefer 'char *' because that's what the system |
5189 | header files like. */ | |
f607bc57 | 5190 | if (DEFAULT_ABI != ABI_V4) |
9ebbca7d | 5191 | return build_pointer_type (char_type_node); |
dfafc897 | 5192 | |
f1e639b1 | 5193 | record = (*lang_hooks.types.make_type) (RECORD_TYPE); |
bab45a51 | 5194 | type_decl = build_decl (TYPE_DECL, get_identifier ("__va_list_tag"), record); |
0f4fd75d | 5195 | |
f676971a | 5196 | f_gpr = build_decl (FIELD_DECL, get_identifier ("gpr"), |
9ebbca7d | 5197 | unsigned_char_type_node); |
f676971a | 5198 | f_fpr = build_decl (FIELD_DECL, get_identifier ("fpr"), |
9ebbca7d | 5199 | unsigned_char_type_node); |
64c2816f DT |
5200 | /* Give the two bytes of padding a name, so that -Wpadded won't warn on |
5201 | every user file. */ | |
5202 | f_res = build_decl (FIELD_DECL, get_identifier ("reserved"), | |
5203 | short_unsigned_type_node); | |
dfafc897 FS |
5204 | f_ovf = build_decl (FIELD_DECL, get_identifier ("overflow_arg_area"), |
5205 | ptr_type_node); | |
5206 | f_sav = build_decl (FIELD_DECL, get_identifier ("reg_save_area"), | |
5207 | ptr_type_node); | |
5208 | ||
5209 | DECL_FIELD_CONTEXT (f_gpr) = record; | |
5210 | DECL_FIELD_CONTEXT (f_fpr) = record; | |
64c2816f | 5211 | DECL_FIELD_CONTEXT (f_res) = record; |
dfafc897 FS |
5212 | DECL_FIELD_CONTEXT (f_ovf) = record; |
5213 | DECL_FIELD_CONTEXT (f_sav) = record; | |
5214 | ||
bab45a51 FS |
5215 | TREE_CHAIN (record) = type_decl; |
5216 | TYPE_NAME (record) = type_decl; | |
dfafc897 FS |
5217 | TYPE_FIELDS (record) = f_gpr; |
5218 | TREE_CHAIN (f_gpr) = f_fpr; | |
64c2816f DT |
5219 | TREE_CHAIN (f_fpr) = f_res; |
5220 | TREE_CHAIN (f_res) = f_ovf; | |
dfafc897 FS |
5221 | TREE_CHAIN (f_ovf) = f_sav; |
5222 | ||
5223 | layout_type (record); | |
5224 | ||
5225 | /* The correct type is an array type of one element. */ | |
5226 | return build_array_type (record, build_index_type (size_zero_node)); | |
5227 | } | |
5228 | ||
5229 | /* Implement va_start. */ | |
5230 | ||
5231 | void | |
a2369ed3 | 5232 | rs6000_va_start (tree valist, rtx nextarg) |
4697a36c | 5233 | { |
dfafc897 | 5234 | HOST_WIDE_INT words, n_gpr, n_fpr; |
c566f9bd | 5235 | tree f_gpr, f_fpr, f_res, f_ovf, f_sav; |
dfafc897 | 5236 | tree gpr, fpr, ovf, sav, t; |
2c4974b7 | 5237 | |
dfafc897 | 5238 | /* Only SVR4 needs something special. */ |
f607bc57 | 5239 | if (DEFAULT_ABI != ABI_V4) |
dfafc897 | 5240 | { |
e5faf155 | 5241 | std_expand_builtin_va_start (valist, nextarg); |
dfafc897 FS |
5242 | return; |
5243 | } | |
5244 | ||
973a648b | 5245 | f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node)); |
dfafc897 | 5246 | f_fpr = TREE_CHAIN (f_gpr); |
c566f9bd DT |
5247 | f_res = TREE_CHAIN (f_fpr); |
5248 | f_ovf = TREE_CHAIN (f_res); | |
dfafc897 FS |
5249 | f_sav = TREE_CHAIN (f_ovf); |
5250 | ||
872a65b5 | 5251 | valist = build_va_arg_indirect_ref (valist); |
44de5aeb RK |
5252 | gpr = build (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE); |
5253 | fpr = build (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE); | |
5254 | ovf = build (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE); | |
5255 | sav = build (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE); | |
dfafc897 FS |
5256 | |
5257 | /* Count number of gp and fp argument registers used. */ | |
4cc833b7 | 5258 | words = current_function_args_info.words; |
987732e0 DE |
5259 | n_gpr = MIN (current_function_args_info.sysv_gregno - GP_ARG_MIN_REG, |
5260 | GP_ARG_NUM_REG); | |
5261 | n_fpr = MIN (current_function_args_info.fregno - FP_ARG_MIN_REG, | |
5262 | FP_ARG_NUM_REG); | |
dfafc897 FS |
5263 | |
5264 | if (TARGET_DEBUG_ARG) | |
4a0a75dd KG |
5265 | fprintf (stderr, "va_start: words = "HOST_WIDE_INT_PRINT_DEC", n_gpr = " |
5266 | HOST_WIDE_INT_PRINT_DEC", n_fpr = "HOST_WIDE_INT_PRINT_DEC"\n", | |
5267 | words, n_gpr, n_fpr); | |
dfafc897 | 5268 | |
5496b36f JJ |
5269 | t = build (MODIFY_EXPR, TREE_TYPE (gpr), gpr, |
5270 | build_int_cst (NULL_TREE, n_gpr)); | |
5271 | TREE_SIDE_EFFECTS (t) = 1; | |
5272 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
58c8adc1 | 5273 | |
5496b36f JJ |
5274 | t = build (MODIFY_EXPR, TREE_TYPE (fpr), fpr, |
5275 | build_int_cst (NULL_TREE, n_fpr)); | |
5276 | TREE_SIDE_EFFECTS (t) = 1; | |
5277 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
dfafc897 FS |
5278 | |
5279 | /* Find the overflow area. */ | |
5280 | t = make_tree (TREE_TYPE (ovf), virtual_incoming_args_rtx); | |
5281 | if (words != 0) | |
5282 | t = build (PLUS_EXPR, TREE_TYPE (ovf), t, | |
7d60be94 | 5283 | build_int_cst (NULL_TREE, words * UNITS_PER_WORD)); |
dfafc897 FS |
5284 | t = build (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t); |
5285 | TREE_SIDE_EFFECTS (t) = 1; | |
5286 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
5287 | ||
5288 | /* Find the register save area. */ | |
5289 | t = make_tree (TREE_TYPE (sav), virtual_stack_vars_rtx); | |
5290 | t = build (PLUS_EXPR, TREE_TYPE (sav), t, | |
7d60be94 | 5291 | build_int_cst (NULL_TREE, -RS6000_VARARGS_SIZE)); |
dfafc897 FS |
5292 | t = build (MODIFY_EXPR, TREE_TYPE (sav), sav, t); |
5293 | TREE_SIDE_EFFECTS (t) = 1; | |
5294 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
5295 | } | |
5296 | ||
5297 | /* Implement va_arg. */ | |
5298 | ||
23a60a04 JM |
5299 | tree |
5300 | rs6000_gimplify_va_arg (tree valist, tree type, tree *pre_p, tree *post_p) | |
cd3ce9b4 | 5301 | { |
cd3ce9b4 JM |
5302 | tree f_gpr, f_fpr, f_res, f_ovf, f_sav; |
5303 | tree gpr, fpr, ovf, sav, reg, t, u; | |
08b0dc1b | 5304 | int size, rsize, n_reg, sav_ofs, sav_scale; |
cd3ce9b4 JM |
5305 | tree lab_false, lab_over, addr; |
5306 | int align; | |
5307 | tree ptrtype = build_pointer_type (type); | |
5308 | ||
08b0dc1b RH |
5309 | if (pass_by_reference (NULL, TYPE_MODE (type), type, false)) |
5310 | { | |
5311 | t = rs6000_gimplify_va_arg (valist, ptrtype, pre_p, post_p); | |
872a65b5 | 5312 | return build_va_arg_indirect_ref (t); |
08b0dc1b RH |
5313 | } |
5314 | ||
cd3ce9b4 JM |
5315 | if (DEFAULT_ABI != ABI_V4) |
5316 | { | |
08b0dc1b | 5317 | if (targetm.calls.split_complex_arg && TREE_CODE (type) == COMPLEX_TYPE) |
cd3ce9b4 JM |
5318 | { |
5319 | tree elem_type = TREE_TYPE (type); | |
5320 | enum machine_mode elem_mode = TYPE_MODE (elem_type); | |
5321 | int elem_size = GET_MODE_SIZE (elem_mode); | |
5322 | ||
5323 | if (elem_size < UNITS_PER_WORD) | |
5324 | { | |
23a60a04 | 5325 | tree real_part, imag_part; |
cd3ce9b4 JM |
5326 | tree post = NULL_TREE; |
5327 | ||
23a60a04 JM |
5328 | real_part = rs6000_gimplify_va_arg (valist, elem_type, pre_p, |
5329 | &post); | |
5330 | /* Copy the value into a temporary, lest the formal temporary | |
5331 | be reused out from under us. */ | |
5332 | real_part = get_initialized_tmp_var (real_part, pre_p, &post); | |
cd3ce9b4 JM |
5333 | append_to_statement_list (post, pre_p); |
5334 | ||
23a60a04 JM |
5335 | imag_part = rs6000_gimplify_va_arg (valist, elem_type, pre_p, |
5336 | post_p); | |
cd3ce9b4 | 5337 | |
23a60a04 | 5338 | return build (COMPLEX_EXPR, type, real_part, imag_part); |
cd3ce9b4 JM |
5339 | } |
5340 | } | |
5341 | ||
23a60a04 | 5342 | return std_gimplify_va_arg_expr (valist, type, pre_p, post_p); |
cd3ce9b4 JM |
5343 | } |
5344 | ||
5345 | f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node)); | |
5346 | f_fpr = TREE_CHAIN (f_gpr); | |
5347 | f_res = TREE_CHAIN (f_fpr); | |
5348 | f_ovf = TREE_CHAIN (f_res); | |
5349 | f_sav = TREE_CHAIN (f_ovf); | |
5350 | ||
872a65b5 | 5351 | valist = build_va_arg_indirect_ref (valist); |
44de5aeb RK |
5352 | gpr = build (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE); |
5353 | fpr = build (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE); | |
5354 | ovf = build (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE); | |
5355 | sav = build (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE); | |
cd3ce9b4 JM |
5356 | |
5357 | size = int_size_in_bytes (type); | |
5358 | rsize = (size + 3) / 4; | |
5359 | align = 1; | |
5360 | ||
08b0dc1b RH |
5361 | if (TARGET_HARD_FLOAT && TARGET_FPRS |
5362 | && (TYPE_MODE (type) == SFmode || TYPE_MODE (type) == DFmode)) | |
cd3ce9b4 JM |
5363 | { |
5364 | /* FP args go in FP registers, if present. */ | |
cd3ce9b4 JM |
5365 | reg = fpr; |
5366 | n_reg = 1; | |
5367 | sav_ofs = 8*4; | |
5368 | sav_scale = 8; | |
5369 | if (TYPE_MODE (type) == DFmode) | |
5370 | align = 8; | |
5371 | } | |
5372 | else | |
5373 | { | |
5374 | /* Otherwise into GP registers. */ | |
cd3ce9b4 JM |
5375 | reg = gpr; |
5376 | n_reg = rsize; | |
5377 | sav_ofs = 0; | |
5378 | sav_scale = 4; | |
5379 | if (n_reg == 2) | |
5380 | align = 8; | |
5381 | } | |
5382 | ||
5383 | /* Pull the value out of the saved registers.... */ | |
5384 | ||
5385 | lab_over = NULL; | |
5386 | addr = create_tmp_var (ptr_type_node, "addr"); | |
5387 | DECL_POINTER_ALIAS_SET (addr) = get_varargs_alias_set (); | |
5388 | ||
5389 | /* AltiVec vectors never go in registers when -mabi=altivec. */ | |
5390 | if (TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (TYPE_MODE (type))) | |
5391 | align = 16; | |
5392 | else | |
5393 | { | |
5394 | lab_false = create_artificial_label (); | |
5395 | lab_over = create_artificial_label (); | |
5396 | ||
5397 | /* Long long and SPE vectors are aligned in the registers. | |
5398 | As are any other 2 gpr item such as complex int due to a | |
5399 | historical mistake. */ | |
5400 | u = reg; | |
5401 | if (n_reg == 2) | |
5402 | { | |
5403 | u = build2 (BIT_AND_EXPR, TREE_TYPE (reg), reg, | |
95674810 | 5404 | size_int (n_reg - 1)); |
cd3ce9b4 JM |
5405 | u = build2 (POSTINCREMENT_EXPR, TREE_TYPE (reg), reg, u); |
5406 | } | |
5407 | ||
95674810 | 5408 | t = fold_convert (TREE_TYPE (reg), size_int (8 - n_reg + 1)); |
cd3ce9b4 JM |
5409 | t = build2 (GE_EXPR, boolean_type_node, u, t); |
5410 | u = build1 (GOTO_EXPR, void_type_node, lab_false); | |
5411 | t = build3 (COND_EXPR, void_type_node, t, u, NULL_TREE); | |
5412 | gimplify_and_add (t, pre_p); | |
5413 | ||
5414 | t = sav; | |
5415 | if (sav_ofs) | |
95674810 | 5416 | t = build2 (PLUS_EXPR, ptr_type_node, sav, size_int (sav_ofs)); |
cd3ce9b4 | 5417 | |
95674810 | 5418 | u = build2 (POSTINCREMENT_EXPR, TREE_TYPE (reg), reg, size_int (n_reg)); |
cd3ce9b4 | 5419 | u = build1 (CONVERT_EXPR, integer_type_node, u); |
95674810 | 5420 | u = build2 (MULT_EXPR, integer_type_node, u, size_int (sav_scale)); |
cd3ce9b4 JM |
5421 | t = build2 (PLUS_EXPR, ptr_type_node, t, u); |
5422 | ||
5423 | t = build2 (MODIFY_EXPR, void_type_node, addr, t); | |
5424 | gimplify_and_add (t, pre_p); | |
5425 | ||
5426 | t = build1 (GOTO_EXPR, void_type_node, lab_over); | |
5427 | gimplify_and_add (t, pre_p); | |
5428 | ||
5429 | t = build1 (LABEL_EXPR, void_type_node, lab_false); | |
5430 | append_to_statement_list (t, pre_p); | |
5431 | ||
5432 | if (n_reg > 2) | |
5433 | { | |
5434 | /* Ensure that we don't find any more args in regs. | |
5435 | Alignment has taken care of the n_reg == 2 case. */ | |
95674810 | 5436 | t = build (MODIFY_EXPR, TREE_TYPE (reg), reg, size_int (8)); |
cd3ce9b4 JM |
5437 | gimplify_and_add (t, pre_p); |
5438 | } | |
5439 | } | |
5440 | ||
5441 | /* ... otherwise out of the overflow area. */ | |
5442 | ||
5443 | /* Care for on-stack alignment if needed. */ | |
5444 | t = ovf; | |
5445 | if (align != 1) | |
5446 | { | |
95674810 | 5447 | t = build2 (PLUS_EXPR, TREE_TYPE (t), t, size_int (align - 1)); |
4a90aeeb | 5448 | t = build2 (BIT_AND_EXPR, TREE_TYPE (t), t, |
7d60be94 | 5449 | build_int_cst (NULL_TREE, -align)); |
cd3ce9b4 JM |
5450 | } |
5451 | gimplify_expr (&t, pre_p, NULL, is_gimple_val, fb_rvalue); | |
5452 | ||
5453 | u = build2 (MODIFY_EXPR, void_type_node, addr, t); | |
5454 | gimplify_and_add (u, pre_p); | |
5455 | ||
95674810 | 5456 | t = build2 (PLUS_EXPR, TREE_TYPE (t), t, size_int (size)); |
cd3ce9b4 JM |
5457 | t = build2 (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t); |
5458 | gimplify_and_add (t, pre_p); | |
5459 | ||
5460 | if (lab_over) | |
5461 | { | |
5462 | t = build1 (LABEL_EXPR, void_type_node, lab_over); | |
5463 | append_to_statement_list (t, pre_p); | |
5464 | } | |
5465 | ||
08b0dc1b | 5466 | addr = fold_convert (ptrtype, addr); |
872a65b5 | 5467 | return build_va_arg_indirect_ref (addr); |
cd3ce9b4 JM |
5468 | } |
5469 | ||
0ac081f6 AH |
5470 | /* Builtins. */ |
5471 | ||
6e34d3a3 JM |
5472 | #define def_builtin(MASK, NAME, TYPE, CODE) \ |
5473 | do { \ | |
5474 | if ((MASK) & target_flags) \ | |
5475 | lang_hooks.builtin_function ((NAME), (TYPE), (CODE), BUILT_IN_MD, \ | |
5476 | NULL, NULL_TREE); \ | |
0ac081f6 AH |
5477 | } while (0) |
5478 | ||
24408032 AH |
5479 | /* Simple ternary operations: VECd = foo (VECa, VECb, VECc). */ |
5480 | ||
2212663f | 5481 | static const struct builtin_description bdesc_3arg[] = |
24408032 AH |
5482 | { |
5483 | { MASK_ALTIVEC, CODE_FOR_altivec_vmaddfp, "__builtin_altivec_vmaddfp", ALTIVEC_BUILTIN_VMADDFP }, | |
5484 | { MASK_ALTIVEC, CODE_FOR_altivec_vmhaddshs, "__builtin_altivec_vmhaddshs", ALTIVEC_BUILTIN_VMHADDSHS }, | |
5485 | { MASK_ALTIVEC, CODE_FOR_altivec_vmhraddshs, "__builtin_altivec_vmhraddshs", ALTIVEC_BUILTIN_VMHRADDSHS }, | |
5486 | { MASK_ALTIVEC, CODE_FOR_altivec_vmladduhm, "__builtin_altivec_vmladduhm", ALTIVEC_BUILTIN_VMLADDUHM}, | |
5487 | { MASK_ALTIVEC, CODE_FOR_altivec_vmsumubm, "__builtin_altivec_vmsumubm", ALTIVEC_BUILTIN_VMSUMUBM }, | |
5488 | { MASK_ALTIVEC, CODE_FOR_altivec_vmsummbm, "__builtin_altivec_vmsummbm", ALTIVEC_BUILTIN_VMSUMMBM }, | |
5489 | { MASK_ALTIVEC, CODE_FOR_altivec_vmsumuhm, "__builtin_altivec_vmsumuhm", ALTIVEC_BUILTIN_VMSUMUHM }, | |
5490 | { MASK_ALTIVEC, CODE_FOR_altivec_vmsumshm, "__builtin_altivec_vmsumshm", ALTIVEC_BUILTIN_VMSUMSHM }, | |
5491 | { MASK_ALTIVEC, CODE_FOR_altivec_vmsumuhs, "__builtin_altivec_vmsumuhs", ALTIVEC_BUILTIN_VMSUMUHS }, | |
5492 | { MASK_ALTIVEC, CODE_FOR_altivec_vmsumshs, "__builtin_altivec_vmsumshs", ALTIVEC_BUILTIN_VMSUMSHS }, | |
f676971a | 5493 | { MASK_ALTIVEC, CODE_FOR_altivec_vnmsubfp, "__builtin_altivec_vnmsubfp", ALTIVEC_BUILTIN_VNMSUBFP }, |
aba5fb01 NS |
5494 | { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v4sf, "__builtin_altivec_vperm_4sf", ALTIVEC_BUILTIN_VPERM_4SF }, |
5495 | { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v4si, "__builtin_altivec_vperm_4si", ALTIVEC_BUILTIN_VPERM_4SI }, | |
5496 | { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v8hi, "__builtin_altivec_vperm_8hi", ALTIVEC_BUILTIN_VPERM_8HI }, | |
5497 | { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v16qi, "__builtin_altivec_vperm_16qi", ALTIVEC_BUILTIN_VPERM_16QI }, | |
5498 | { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v4sf, "__builtin_altivec_vsel_4sf", ALTIVEC_BUILTIN_VSEL_4SF }, | |
5499 | { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v4si, "__builtin_altivec_vsel_4si", ALTIVEC_BUILTIN_VSEL_4SI }, | |
5500 | { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v8hi, "__builtin_altivec_vsel_8hi", ALTIVEC_BUILTIN_VSEL_8HI }, | |
5501 | { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v16qi, "__builtin_altivec_vsel_16qi", ALTIVEC_BUILTIN_VSEL_16QI }, | |
5502 | { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v16qi, "__builtin_altivec_vsldoi_16qi", ALTIVEC_BUILTIN_VSLDOI_16QI }, | |
5503 | { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v8hi, "__builtin_altivec_vsldoi_8hi", ALTIVEC_BUILTIN_VSLDOI_8HI }, | |
5504 | { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v4si, "__builtin_altivec_vsldoi_4si", ALTIVEC_BUILTIN_VSLDOI_4SI }, | |
5505 | { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v4sf, "__builtin_altivec_vsldoi_4sf", ALTIVEC_BUILTIN_VSLDOI_4SF }, | |
24408032 | 5506 | }; |
2212663f | 5507 | |
95385cbb AH |
5508 | /* DST operations: void foo (void *, const int, const char). */ |
5509 | ||
5510 | static const struct builtin_description bdesc_dst[] = | |
5511 | { | |
5512 | { MASK_ALTIVEC, CODE_FOR_altivec_dst, "__builtin_altivec_dst", ALTIVEC_BUILTIN_DST }, | |
5513 | { MASK_ALTIVEC, CODE_FOR_altivec_dstt, "__builtin_altivec_dstt", ALTIVEC_BUILTIN_DSTT }, | |
5514 | { MASK_ALTIVEC, CODE_FOR_altivec_dstst, "__builtin_altivec_dstst", ALTIVEC_BUILTIN_DSTST }, | |
5515 | { MASK_ALTIVEC, CODE_FOR_altivec_dststt, "__builtin_altivec_dststt", ALTIVEC_BUILTIN_DSTSTT } | |
5516 | }; | |
5517 | ||
2212663f | 5518 | /* Simple binary operations: VECc = foo (VECa, VECb). */ |
24408032 | 5519 | |
a3170dc6 | 5520 | static struct builtin_description bdesc_2arg[] = |
0ac081f6 | 5521 | { |
f18c054f DB |
5522 | { MASK_ALTIVEC, CODE_FOR_addv16qi3, "__builtin_altivec_vaddubm", ALTIVEC_BUILTIN_VADDUBM }, |
5523 | { MASK_ALTIVEC, CODE_FOR_addv8hi3, "__builtin_altivec_vadduhm", ALTIVEC_BUILTIN_VADDUHM }, | |
5524 | { MASK_ALTIVEC, CODE_FOR_addv4si3, "__builtin_altivec_vadduwm", ALTIVEC_BUILTIN_VADDUWM }, | |
5525 | { MASK_ALTIVEC, CODE_FOR_addv4sf3, "__builtin_altivec_vaddfp", ALTIVEC_BUILTIN_VADDFP }, | |
0ac081f6 AH |
5526 | { MASK_ALTIVEC, CODE_FOR_altivec_vaddcuw, "__builtin_altivec_vaddcuw", ALTIVEC_BUILTIN_VADDCUW }, |
5527 | { MASK_ALTIVEC, CODE_FOR_altivec_vaddubs, "__builtin_altivec_vaddubs", ALTIVEC_BUILTIN_VADDUBS }, | |
5528 | { MASK_ALTIVEC, CODE_FOR_altivec_vaddsbs, "__builtin_altivec_vaddsbs", ALTIVEC_BUILTIN_VADDSBS }, | |
5529 | { MASK_ALTIVEC, CODE_FOR_altivec_vadduhs, "__builtin_altivec_vadduhs", ALTIVEC_BUILTIN_VADDUHS }, | |
5530 | { MASK_ALTIVEC, CODE_FOR_altivec_vaddshs, "__builtin_altivec_vaddshs", ALTIVEC_BUILTIN_VADDSHS }, | |
5531 | { MASK_ALTIVEC, CODE_FOR_altivec_vadduws, "__builtin_altivec_vadduws", ALTIVEC_BUILTIN_VADDUWS }, | |
5532 | { MASK_ALTIVEC, CODE_FOR_altivec_vaddsws, "__builtin_altivec_vaddsws", ALTIVEC_BUILTIN_VADDSWS }, | |
f18c054f | 5533 | { MASK_ALTIVEC, CODE_FOR_andv4si3, "__builtin_altivec_vand", ALTIVEC_BUILTIN_VAND }, |
aba5fb01 | 5534 | { MASK_ALTIVEC, CODE_FOR_andcv4si3, "__builtin_altivec_vandc", ALTIVEC_BUILTIN_VANDC }, |
0ac081f6 AH |
5535 | { MASK_ALTIVEC, CODE_FOR_altivec_vavgub, "__builtin_altivec_vavgub", ALTIVEC_BUILTIN_VAVGUB }, |
5536 | { MASK_ALTIVEC, CODE_FOR_altivec_vavgsb, "__builtin_altivec_vavgsb", ALTIVEC_BUILTIN_VAVGSB }, | |
5537 | { MASK_ALTIVEC, CODE_FOR_altivec_vavguh, "__builtin_altivec_vavguh", ALTIVEC_BUILTIN_VAVGUH }, | |
5538 | { MASK_ALTIVEC, CODE_FOR_altivec_vavgsh, "__builtin_altivec_vavgsh", ALTIVEC_BUILTIN_VAVGSH }, | |
5539 | { MASK_ALTIVEC, CODE_FOR_altivec_vavguw, "__builtin_altivec_vavguw", ALTIVEC_BUILTIN_VAVGUW }, | |
5540 | { MASK_ALTIVEC, CODE_FOR_altivec_vavgsw, "__builtin_altivec_vavgsw", ALTIVEC_BUILTIN_VAVGSW }, | |
617e0e1d DB |
5541 | { MASK_ALTIVEC, CODE_FOR_altivec_vcfux, "__builtin_altivec_vcfux", ALTIVEC_BUILTIN_VCFUX }, |
5542 | { MASK_ALTIVEC, CODE_FOR_altivec_vcfsx, "__builtin_altivec_vcfsx", ALTIVEC_BUILTIN_VCFSX }, | |
0ac081f6 AH |
5543 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpbfp, "__builtin_altivec_vcmpbfp", ALTIVEC_BUILTIN_VCMPBFP }, |
5544 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequb, "__builtin_altivec_vcmpequb", ALTIVEC_BUILTIN_VCMPEQUB }, | |
5545 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequh, "__builtin_altivec_vcmpequh", ALTIVEC_BUILTIN_VCMPEQUH }, | |
5546 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequw, "__builtin_altivec_vcmpequw", ALTIVEC_BUILTIN_VCMPEQUW }, | |
5547 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpeqfp, "__builtin_altivec_vcmpeqfp", ALTIVEC_BUILTIN_VCMPEQFP }, | |
5548 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgefp, "__builtin_altivec_vcmpgefp", ALTIVEC_BUILTIN_VCMPGEFP }, | |
5549 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtub, "__builtin_altivec_vcmpgtub", ALTIVEC_BUILTIN_VCMPGTUB }, | |
5550 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsb, "__builtin_altivec_vcmpgtsb", ALTIVEC_BUILTIN_VCMPGTSB }, | |
5551 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtuh, "__builtin_altivec_vcmpgtuh", ALTIVEC_BUILTIN_VCMPGTUH }, | |
5552 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsh, "__builtin_altivec_vcmpgtsh", ALTIVEC_BUILTIN_VCMPGTSH }, | |
5553 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtuw, "__builtin_altivec_vcmpgtuw", ALTIVEC_BUILTIN_VCMPGTUW }, | |
5554 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsw, "__builtin_altivec_vcmpgtsw", ALTIVEC_BUILTIN_VCMPGTSW }, | |
5555 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtfp, "__builtin_altivec_vcmpgtfp", ALTIVEC_BUILTIN_VCMPGTFP }, | |
617e0e1d DB |
5556 | { MASK_ALTIVEC, CODE_FOR_altivec_vctsxs, "__builtin_altivec_vctsxs", ALTIVEC_BUILTIN_VCTSXS }, |
5557 | { MASK_ALTIVEC, CODE_FOR_altivec_vctuxs, "__builtin_altivec_vctuxs", ALTIVEC_BUILTIN_VCTUXS }, | |
f18c054f DB |
5558 | { MASK_ALTIVEC, CODE_FOR_umaxv16qi3, "__builtin_altivec_vmaxub", ALTIVEC_BUILTIN_VMAXUB }, |
5559 | { MASK_ALTIVEC, CODE_FOR_smaxv16qi3, "__builtin_altivec_vmaxsb", ALTIVEC_BUILTIN_VMAXSB }, | |
df966bff AH |
5560 | { MASK_ALTIVEC, CODE_FOR_umaxv8hi3, "__builtin_altivec_vmaxuh", ALTIVEC_BUILTIN_VMAXUH }, |
5561 | { MASK_ALTIVEC, CODE_FOR_smaxv8hi3, "__builtin_altivec_vmaxsh", ALTIVEC_BUILTIN_VMAXSH }, | |
5562 | { MASK_ALTIVEC, CODE_FOR_umaxv4si3, "__builtin_altivec_vmaxuw", ALTIVEC_BUILTIN_VMAXUW }, | |
5563 | { MASK_ALTIVEC, CODE_FOR_smaxv4si3, "__builtin_altivec_vmaxsw", ALTIVEC_BUILTIN_VMAXSW }, | |
5564 | { MASK_ALTIVEC, CODE_FOR_smaxv4sf3, "__builtin_altivec_vmaxfp", ALTIVEC_BUILTIN_VMAXFP }, | |
0ac081f6 AH |
5565 | { MASK_ALTIVEC, CODE_FOR_altivec_vmrghb, "__builtin_altivec_vmrghb", ALTIVEC_BUILTIN_VMRGHB }, |
5566 | { MASK_ALTIVEC, CODE_FOR_altivec_vmrghh, "__builtin_altivec_vmrghh", ALTIVEC_BUILTIN_VMRGHH }, | |
5567 | { MASK_ALTIVEC, CODE_FOR_altivec_vmrghw, "__builtin_altivec_vmrghw", ALTIVEC_BUILTIN_VMRGHW }, | |
5568 | { MASK_ALTIVEC, CODE_FOR_altivec_vmrglb, "__builtin_altivec_vmrglb", ALTIVEC_BUILTIN_VMRGLB }, | |
5569 | { MASK_ALTIVEC, CODE_FOR_altivec_vmrglh, "__builtin_altivec_vmrglh", ALTIVEC_BUILTIN_VMRGLH }, | |
5570 | { MASK_ALTIVEC, CODE_FOR_altivec_vmrglw, "__builtin_altivec_vmrglw", ALTIVEC_BUILTIN_VMRGLW }, | |
f18c054f DB |
5571 | { MASK_ALTIVEC, CODE_FOR_uminv16qi3, "__builtin_altivec_vminub", ALTIVEC_BUILTIN_VMINUB }, |
5572 | { MASK_ALTIVEC, CODE_FOR_sminv16qi3, "__builtin_altivec_vminsb", ALTIVEC_BUILTIN_VMINSB }, | |
5573 | { MASK_ALTIVEC, CODE_FOR_uminv8hi3, "__builtin_altivec_vminuh", ALTIVEC_BUILTIN_VMINUH }, | |
5574 | { MASK_ALTIVEC, CODE_FOR_sminv8hi3, "__builtin_altivec_vminsh", ALTIVEC_BUILTIN_VMINSH }, | |
5575 | { MASK_ALTIVEC, CODE_FOR_uminv4si3, "__builtin_altivec_vminuw", ALTIVEC_BUILTIN_VMINUW }, | |
5576 | { MASK_ALTIVEC, CODE_FOR_sminv4si3, "__builtin_altivec_vminsw", ALTIVEC_BUILTIN_VMINSW }, | |
5577 | { MASK_ALTIVEC, CODE_FOR_sminv4sf3, "__builtin_altivec_vminfp", ALTIVEC_BUILTIN_VMINFP }, | |
0ac081f6 AH |
5578 | { MASK_ALTIVEC, CODE_FOR_altivec_vmuleub, "__builtin_altivec_vmuleub", ALTIVEC_BUILTIN_VMULEUB }, |
5579 | { MASK_ALTIVEC, CODE_FOR_altivec_vmulesb, "__builtin_altivec_vmulesb", ALTIVEC_BUILTIN_VMULESB }, | |
5580 | { MASK_ALTIVEC, CODE_FOR_altivec_vmuleuh, "__builtin_altivec_vmuleuh", ALTIVEC_BUILTIN_VMULEUH }, | |
5581 | { MASK_ALTIVEC, CODE_FOR_altivec_vmulesh, "__builtin_altivec_vmulesh", ALTIVEC_BUILTIN_VMULESH }, | |
5582 | { MASK_ALTIVEC, CODE_FOR_altivec_vmuloub, "__builtin_altivec_vmuloub", ALTIVEC_BUILTIN_VMULOUB }, | |
5583 | { MASK_ALTIVEC, CODE_FOR_altivec_vmulosb, "__builtin_altivec_vmulosb", ALTIVEC_BUILTIN_VMULOSB }, | |
5584 | { MASK_ALTIVEC, CODE_FOR_altivec_vmulouh, "__builtin_altivec_vmulouh", ALTIVEC_BUILTIN_VMULOUH }, | |
5585 | { MASK_ALTIVEC, CODE_FOR_altivec_vmulosh, "__builtin_altivec_vmulosh", ALTIVEC_BUILTIN_VMULOSH }, | |
f96bc213 | 5586 | { MASK_ALTIVEC, CODE_FOR_altivec_norv4si3, "__builtin_altivec_vnor", ALTIVEC_BUILTIN_VNOR }, |
f18c054f | 5587 | { MASK_ALTIVEC, CODE_FOR_iorv4si3, "__builtin_altivec_vor", ALTIVEC_BUILTIN_VOR }, |
0ac081f6 AH |
5588 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhum, "__builtin_altivec_vpkuhum", ALTIVEC_BUILTIN_VPKUHUM }, |
5589 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwum, "__builtin_altivec_vpkuwum", ALTIVEC_BUILTIN_VPKUWUM }, | |
5590 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkpx, "__builtin_altivec_vpkpx", ALTIVEC_BUILTIN_VPKPX }, | |
5591 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhss, "__builtin_altivec_vpkuhss", ALTIVEC_BUILTIN_VPKUHSS }, | |
5592 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkshss, "__builtin_altivec_vpkshss", ALTIVEC_BUILTIN_VPKSHSS }, | |
5593 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwss, "__builtin_altivec_vpkuwss", ALTIVEC_BUILTIN_VPKUWSS }, | |
5594 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkswss, "__builtin_altivec_vpkswss", ALTIVEC_BUILTIN_VPKSWSS }, | |
5595 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhus, "__builtin_altivec_vpkuhus", ALTIVEC_BUILTIN_VPKUHUS }, | |
5596 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkshus, "__builtin_altivec_vpkshus", ALTIVEC_BUILTIN_VPKSHUS }, | |
5597 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwus, "__builtin_altivec_vpkuwus", ALTIVEC_BUILTIN_VPKUWUS }, | |
5598 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkswus, "__builtin_altivec_vpkswus", ALTIVEC_BUILTIN_VPKSWUS }, | |
5599 | { MASK_ALTIVEC, CODE_FOR_altivec_vrlb, "__builtin_altivec_vrlb", ALTIVEC_BUILTIN_VRLB }, | |
5600 | { MASK_ALTIVEC, CODE_FOR_altivec_vrlh, "__builtin_altivec_vrlh", ALTIVEC_BUILTIN_VRLH }, | |
5601 | { MASK_ALTIVEC, CODE_FOR_altivec_vrlw, "__builtin_altivec_vrlw", ALTIVEC_BUILTIN_VRLW }, | |
5602 | { MASK_ALTIVEC, CODE_FOR_altivec_vslb, "__builtin_altivec_vslb", ALTIVEC_BUILTIN_VSLB }, | |
5603 | { MASK_ALTIVEC, CODE_FOR_altivec_vslh, "__builtin_altivec_vslh", ALTIVEC_BUILTIN_VSLH }, | |
5604 | { MASK_ALTIVEC, CODE_FOR_altivec_vslw, "__builtin_altivec_vslw", ALTIVEC_BUILTIN_VSLW }, | |
5605 | { MASK_ALTIVEC, CODE_FOR_altivec_vsl, "__builtin_altivec_vsl", ALTIVEC_BUILTIN_VSL }, | |
5606 | { MASK_ALTIVEC, CODE_FOR_altivec_vslo, "__builtin_altivec_vslo", ALTIVEC_BUILTIN_VSLO }, | |
2212663f DB |
5607 | { MASK_ALTIVEC, CODE_FOR_altivec_vspltb, "__builtin_altivec_vspltb", ALTIVEC_BUILTIN_VSPLTB }, |
5608 | { MASK_ALTIVEC, CODE_FOR_altivec_vsplth, "__builtin_altivec_vsplth", ALTIVEC_BUILTIN_VSPLTH }, | |
5609 | { MASK_ALTIVEC, CODE_FOR_altivec_vspltw, "__builtin_altivec_vspltw", ALTIVEC_BUILTIN_VSPLTW }, | |
0ac081f6 | 5610 | { MASK_ALTIVEC, CODE_FOR_altivec_vsrb, "__builtin_altivec_vsrb", ALTIVEC_BUILTIN_VSRB }, |
f18c054f DB |
5611 | { MASK_ALTIVEC, CODE_FOR_altivec_vsrh, "__builtin_altivec_vsrh", ALTIVEC_BUILTIN_VSRH }, |
5612 | { MASK_ALTIVEC, CODE_FOR_altivec_vsrw, "__builtin_altivec_vsrw", ALTIVEC_BUILTIN_VSRW }, | |
0ac081f6 AH |
5613 | { MASK_ALTIVEC, CODE_FOR_altivec_vsrab, "__builtin_altivec_vsrab", ALTIVEC_BUILTIN_VSRAB }, |
5614 | { MASK_ALTIVEC, CODE_FOR_altivec_vsrah, "__builtin_altivec_vsrah", ALTIVEC_BUILTIN_VSRAH }, | |
5615 | { MASK_ALTIVEC, CODE_FOR_altivec_vsraw, "__builtin_altivec_vsraw", ALTIVEC_BUILTIN_VSRAW }, | |
5616 | { MASK_ALTIVEC, CODE_FOR_altivec_vsr, "__builtin_altivec_vsr", ALTIVEC_BUILTIN_VSR }, | |
5617 | { MASK_ALTIVEC, CODE_FOR_altivec_vsro, "__builtin_altivec_vsro", ALTIVEC_BUILTIN_VSRO }, | |
f18c054f DB |
5618 | { MASK_ALTIVEC, CODE_FOR_subv16qi3, "__builtin_altivec_vsububm", ALTIVEC_BUILTIN_VSUBUBM }, |
5619 | { MASK_ALTIVEC, CODE_FOR_subv8hi3, "__builtin_altivec_vsubuhm", ALTIVEC_BUILTIN_VSUBUHM }, | |
5620 | { MASK_ALTIVEC, CODE_FOR_subv4si3, "__builtin_altivec_vsubuwm", ALTIVEC_BUILTIN_VSUBUWM }, | |
5621 | { MASK_ALTIVEC, CODE_FOR_subv4sf3, "__builtin_altivec_vsubfp", ALTIVEC_BUILTIN_VSUBFP }, | |
0ac081f6 AH |
5622 | { MASK_ALTIVEC, CODE_FOR_altivec_vsubcuw, "__builtin_altivec_vsubcuw", ALTIVEC_BUILTIN_VSUBCUW }, |
5623 | { MASK_ALTIVEC, CODE_FOR_altivec_vsububs, "__builtin_altivec_vsububs", ALTIVEC_BUILTIN_VSUBUBS }, | |
5624 | { MASK_ALTIVEC, CODE_FOR_altivec_vsubsbs, "__builtin_altivec_vsubsbs", ALTIVEC_BUILTIN_VSUBSBS }, | |
5625 | { MASK_ALTIVEC, CODE_FOR_altivec_vsubuhs, "__builtin_altivec_vsubuhs", ALTIVEC_BUILTIN_VSUBUHS }, | |
5626 | { MASK_ALTIVEC, CODE_FOR_altivec_vsubshs, "__builtin_altivec_vsubshs", ALTIVEC_BUILTIN_VSUBSHS }, | |
5627 | { MASK_ALTIVEC, CODE_FOR_altivec_vsubuws, "__builtin_altivec_vsubuws", ALTIVEC_BUILTIN_VSUBUWS }, | |
5628 | { MASK_ALTIVEC, CODE_FOR_altivec_vsubsws, "__builtin_altivec_vsubsws", ALTIVEC_BUILTIN_VSUBSWS }, | |
5629 | { MASK_ALTIVEC, CODE_FOR_altivec_vsum4ubs, "__builtin_altivec_vsum4ubs", ALTIVEC_BUILTIN_VSUM4UBS }, | |
5630 | { MASK_ALTIVEC, CODE_FOR_altivec_vsum4sbs, "__builtin_altivec_vsum4sbs", ALTIVEC_BUILTIN_VSUM4SBS }, | |
5631 | { MASK_ALTIVEC, CODE_FOR_altivec_vsum4shs, "__builtin_altivec_vsum4shs", ALTIVEC_BUILTIN_VSUM4SHS }, | |
5632 | { MASK_ALTIVEC, CODE_FOR_altivec_vsum2sws, "__builtin_altivec_vsum2sws", ALTIVEC_BUILTIN_VSUM2SWS }, | |
5633 | { MASK_ALTIVEC, CODE_FOR_altivec_vsumsws, "__builtin_altivec_vsumsws", ALTIVEC_BUILTIN_VSUMSWS }, | |
f18c054f | 5634 | { MASK_ALTIVEC, CODE_FOR_xorv4si3, "__builtin_altivec_vxor", ALTIVEC_BUILTIN_VXOR }, |
a3170dc6 AH |
5635 | |
5636 | /* Place holder, leave as first spe builtin. */ | |
5637 | { 0, CODE_FOR_spe_evaddw, "__builtin_spe_evaddw", SPE_BUILTIN_EVADDW }, | |
5638 | { 0, CODE_FOR_spe_evand, "__builtin_spe_evand", SPE_BUILTIN_EVAND }, | |
5639 | { 0, CODE_FOR_spe_evandc, "__builtin_spe_evandc", SPE_BUILTIN_EVANDC }, | |
5640 | { 0, CODE_FOR_spe_evdivws, "__builtin_spe_evdivws", SPE_BUILTIN_EVDIVWS }, | |
5641 | { 0, CODE_FOR_spe_evdivwu, "__builtin_spe_evdivwu", SPE_BUILTIN_EVDIVWU }, | |
5642 | { 0, CODE_FOR_spe_eveqv, "__builtin_spe_eveqv", SPE_BUILTIN_EVEQV }, | |
5643 | { 0, CODE_FOR_spe_evfsadd, "__builtin_spe_evfsadd", SPE_BUILTIN_EVFSADD }, | |
5644 | { 0, CODE_FOR_spe_evfsdiv, "__builtin_spe_evfsdiv", SPE_BUILTIN_EVFSDIV }, | |
5645 | { 0, CODE_FOR_spe_evfsmul, "__builtin_spe_evfsmul", SPE_BUILTIN_EVFSMUL }, | |
5646 | { 0, CODE_FOR_spe_evfssub, "__builtin_spe_evfssub", SPE_BUILTIN_EVFSSUB }, | |
5647 | { 0, CODE_FOR_spe_evmergehi, "__builtin_spe_evmergehi", SPE_BUILTIN_EVMERGEHI }, | |
5648 | { 0, CODE_FOR_spe_evmergehilo, "__builtin_spe_evmergehilo", SPE_BUILTIN_EVMERGEHILO }, | |
5649 | { 0, CODE_FOR_spe_evmergelo, "__builtin_spe_evmergelo", SPE_BUILTIN_EVMERGELO }, | |
5650 | { 0, CODE_FOR_spe_evmergelohi, "__builtin_spe_evmergelohi", SPE_BUILTIN_EVMERGELOHI }, | |
5651 | { 0, CODE_FOR_spe_evmhegsmfaa, "__builtin_spe_evmhegsmfaa", SPE_BUILTIN_EVMHEGSMFAA }, | |
5652 | { 0, CODE_FOR_spe_evmhegsmfan, "__builtin_spe_evmhegsmfan", SPE_BUILTIN_EVMHEGSMFAN }, | |
5653 | { 0, CODE_FOR_spe_evmhegsmiaa, "__builtin_spe_evmhegsmiaa", SPE_BUILTIN_EVMHEGSMIAA }, | |
5654 | { 0, CODE_FOR_spe_evmhegsmian, "__builtin_spe_evmhegsmian", SPE_BUILTIN_EVMHEGSMIAN }, | |
5655 | { 0, CODE_FOR_spe_evmhegumiaa, "__builtin_spe_evmhegumiaa", SPE_BUILTIN_EVMHEGUMIAA }, | |
5656 | { 0, CODE_FOR_spe_evmhegumian, "__builtin_spe_evmhegumian", SPE_BUILTIN_EVMHEGUMIAN }, | |
5657 | { 0, CODE_FOR_spe_evmhesmf, "__builtin_spe_evmhesmf", SPE_BUILTIN_EVMHESMF }, | |
5658 | { 0, CODE_FOR_spe_evmhesmfa, "__builtin_spe_evmhesmfa", SPE_BUILTIN_EVMHESMFA }, | |
5659 | { 0, CODE_FOR_spe_evmhesmfaaw, "__builtin_spe_evmhesmfaaw", SPE_BUILTIN_EVMHESMFAAW }, | |
5660 | { 0, CODE_FOR_spe_evmhesmfanw, "__builtin_spe_evmhesmfanw", SPE_BUILTIN_EVMHESMFANW }, | |
5661 | { 0, CODE_FOR_spe_evmhesmi, "__builtin_spe_evmhesmi", SPE_BUILTIN_EVMHESMI }, | |
5662 | { 0, CODE_FOR_spe_evmhesmia, "__builtin_spe_evmhesmia", SPE_BUILTIN_EVMHESMIA }, | |
5663 | { 0, CODE_FOR_spe_evmhesmiaaw, "__builtin_spe_evmhesmiaaw", SPE_BUILTIN_EVMHESMIAAW }, | |
5664 | { 0, CODE_FOR_spe_evmhesmianw, "__builtin_spe_evmhesmianw", SPE_BUILTIN_EVMHESMIANW }, | |
5665 | { 0, CODE_FOR_spe_evmhessf, "__builtin_spe_evmhessf", SPE_BUILTIN_EVMHESSF }, | |
5666 | { 0, CODE_FOR_spe_evmhessfa, "__builtin_spe_evmhessfa", SPE_BUILTIN_EVMHESSFA }, | |
5667 | { 0, CODE_FOR_spe_evmhessfaaw, "__builtin_spe_evmhessfaaw", SPE_BUILTIN_EVMHESSFAAW }, | |
5668 | { 0, CODE_FOR_spe_evmhessfanw, "__builtin_spe_evmhessfanw", SPE_BUILTIN_EVMHESSFANW }, | |
5669 | { 0, CODE_FOR_spe_evmhessiaaw, "__builtin_spe_evmhessiaaw", SPE_BUILTIN_EVMHESSIAAW }, | |
5670 | { 0, CODE_FOR_spe_evmhessianw, "__builtin_spe_evmhessianw", SPE_BUILTIN_EVMHESSIANW }, | |
5671 | { 0, CODE_FOR_spe_evmheumi, "__builtin_spe_evmheumi", SPE_BUILTIN_EVMHEUMI }, | |
5672 | { 0, CODE_FOR_spe_evmheumia, "__builtin_spe_evmheumia", SPE_BUILTIN_EVMHEUMIA }, | |
5673 | { 0, CODE_FOR_spe_evmheumiaaw, "__builtin_spe_evmheumiaaw", SPE_BUILTIN_EVMHEUMIAAW }, | |
5674 | { 0, CODE_FOR_spe_evmheumianw, "__builtin_spe_evmheumianw", SPE_BUILTIN_EVMHEUMIANW }, | |
5675 | { 0, CODE_FOR_spe_evmheusiaaw, "__builtin_spe_evmheusiaaw", SPE_BUILTIN_EVMHEUSIAAW }, | |
5676 | { 0, CODE_FOR_spe_evmheusianw, "__builtin_spe_evmheusianw", SPE_BUILTIN_EVMHEUSIANW }, | |
5677 | { 0, CODE_FOR_spe_evmhogsmfaa, "__builtin_spe_evmhogsmfaa", SPE_BUILTIN_EVMHOGSMFAA }, | |
5678 | { 0, CODE_FOR_spe_evmhogsmfan, "__builtin_spe_evmhogsmfan", SPE_BUILTIN_EVMHOGSMFAN }, | |
5679 | { 0, CODE_FOR_spe_evmhogsmiaa, "__builtin_spe_evmhogsmiaa", SPE_BUILTIN_EVMHOGSMIAA }, | |
5680 | { 0, CODE_FOR_spe_evmhogsmian, "__builtin_spe_evmhogsmian", SPE_BUILTIN_EVMHOGSMIAN }, | |
5681 | { 0, CODE_FOR_spe_evmhogumiaa, "__builtin_spe_evmhogumiaa", SPE_BUILTIN_EVMHOGUMIAA }, | |
5682 | { 0, CODE_FOR_spe_evmhogumian, "__builtin_spe_evmhogumian", SPE_BUILTIN_EVMHOGUMIAN }, | |
5683 | { 0, CODE_FOR_spe_evmhosmf, "__builtin_spe_evmhosmf", SPE_BUILTIN_EVMHOSMF }, | |
5684 | { 0, CODE_FOR_spe_evmhosmfa, "__builtin_spe_evmhosmfa", SPE_BUILTIN_EVMHOSMFA }, | |
5685 | { 0, CODE_FOR_spe_evmhosmfaaw, "__builtin_spe_evmhosmfaaw", SPE_BUILTIN_EVMHOSMFAAW }, | |
5686 | { 0, CODE_FOR_spe_evmhosmfanw, "__builtin_spe_evmhosmfanw", SPE_BUILTIN_EVMHOSMFANW }, | |
5687 | { 0, CODE_FOR_spe_evmhosmi, "__builtin_spe_evmhosmi", SPE_BUILTIN_EVMHOSMI }, | |
5688 | { 0, CODE_FOR_spe_evmhosmia, "__builtin_spe_evmhosmia", SPE_BUILTIN_EVMHOSMIA }, | |
5689 | { 0, CODE_FOR_spe_evmhosmiaaw, "__builtin_spe_evmhosmiaaw", SPE_BUILTIN_EVMHOSMIAAW }, | |
5690 | { 0, CODE_FOR_spe_evmhosmianw, "__builtin_spe_evmhosmianw", SPE_BUILTIN_EVMHOSMIANW }, | |
5691 | { 0, CODE_FOR_spe_evmhossf, "__builtin_spe_evmhossf", SPE_BUILTIN_EVMHOSSF }, | |
5692 | { 0, CODE_FOR_spe_evmhossfa, "__builtin_spe_evmhossfa", SPE_BUILTIN_EVMHOSSFA }, | |
5693 | { 0, CODE_FOR_spe_evmhossfaaw, "__builtin_spe_evmhossfaaw", SPE_BUILTIN_EVMHOSSFAAW }, | |
5694 | { 0, CODE_FOR_spe_evmhossfanw, "__builtin_spe_evmhossfanw", SPE_BUILTIN_EVMHOSSFANW }, | |
5695 | { 0, CODE_FOR_spe_evmhossiaaw, "__builtin_spe_evmhossiaaw", SPE_BUILTIN_EVMHOSSIAAW }, | |
5696 | { 0, CODE_FOR_spe_evmhossianw, "__builtin_spe_evmhossianw", SPE_BUILTIN_EVMHOSSIANW }, | |
5697 | { 0, CODE_FOR_spe_evmhoumi, "__builtin_spe_evmhoumi", SPE_BUILTIN_EVMHOUMI }, | |
5698 | { 0, CODE_FOR_spe_evmhoumia, "__builtin_spe_evmhoumia", SPE_BUILTIN_EVMHOUMIA }, | |
5699 | { 0, CODE_FOR_spe_evmhoumiaaw, "__builtin_spe_evmhoumiaaw", SPE_BUILTIN_EVMHOUMIAAW }, | |
5700 | { 0, CODE_FOR_spe_evmhoumianw, "__builtin_spe_evmhoumianw", SPE_BUILTIN_EVMHOUMIANW }, | |
5701 | { 0, CODE_FOR_spe_evmhousiaaw, "__builtin_spe_evmhousiaaw", SPE_BUILTIN_EVMHOUSIAAW }, | |
5702 | { 0, CODE_FOR_spe_evmhousianw, "__builtin_spe_evmhousianw", SPE_BUILTIN_EVMHOUSIANW }, | |
5703 | { 0, CODE_FOR_spe_evmwhsmf, "__builtin_spe_evmwhsmf", SPE_BUILTIN_EVMWHSMF }, | |
5704 | { 0, CODE_FOR_spe_evmwhsmfa, "__builtin_spe_evmwhsmfa", SPE_BUILTIN_EVMWHSMFA }, | |
5705 | { 0, CODE_FOR_spe_evmwhsmi, "__builtin_spe_evmwhsmi", SPE_BUILTIN_EVMWHSMI }, | |
5706 | { 0, CODE_FOR_spe_evmwhsmia, "__builtin_spe_evmwhsmia", SPE_BUILTIN_EVMWHSMIA }, | |
5707 | { 0, CODE_FOR_spe_evmwhssf, "__builtin_spe_evmwhssf", SPE_BUILTIN_EVMWHSSF }, | |
5708 | { 0, CODE_FOR_spe_evmwhssfa, "__builtin_spe_evmwhssfa", SPE_BUILTIN_EVMWHSSFA }, | |
5709 | { 0, CODE_FOR_spe_evmwhumi, "__builtin_spe_evmwhumi", SPE_BUILTIN_EVMWHUMI }, | |
5710 | { 0, CODE_FOR_spe_evmwhumia, "__builtin_spe_evmwhumia", SPE_BUILTIN_EVMWHUMIA }, | |
a3170dc6 AH |
5711 | { 0, CODE_FOR_spe_evmwlsmiaaw, "__builtin_spe_evmwlsmiaaw", SPE_BUILTIN_EVMWLSMIAAW }, |
5712 | { 0, CODE_FOR_spe_evmwlsmianw, "__builtin_spe_evmwlsmianw", SPE_BUILTIN_EVMWLSMIANW }, | |
a3170dc6 AH |
5713 | { 0, CODE_FOR_spe_evmwlssiaaw, "__builtin_spe_evmwlssiaaw", SPE_BUILTIN_EVMWLSSIAAW }, |
5714 | { 0, CODE_FOR_spe_evmwlssianw, "__builtin_spe_evmwlssianw", SPE_BUILTIN_EVMWLSSIANW }, | |
5715 | { 0, CODE_FOR_spe_evmwlumi, "__builtin_spe_evmwlumi", SPE_BUILTIN_EVMWLUMI }, | |
5716 | { 0, CODE_FOR_spe_evmwlumia, "__builtin_spe_evmwlumia", SPE_BUILTIN_EVMWLUMIA }, | |
5717 | { 0, CODE_FOR_spe_evmwlumiaaw, "__builtin_spe_evmwlumiaaw", SPE_BUILTIN_EVMWLUMIAAW }, | |
5718 | { 0, CODE_FOR_spe_evmwlumianw, "__builtin_spe_evmwlumianw", SPE_BUILTIN_EVMWLUMIANW }, | |
5719 | { 0, CODE_FOR_spe_evmwlusiaaw, "__builtin_spe_evmwlusiaaw", SPE_BUILTIN_EVMWLUSIAAW }, | |
5720 | { 0, CODE_FOR_spe_evmwlusianw, "__builtin_spe_evmwlusianw", SPE_BUILTIN_EVMWLUSIANW }, | |
5721 | { 0, CODE_FOR_spe_evmwsmf, "__builtin_spe_evmwsmf", SPE_BUILTIN_EVMWSMF }, | |
5722 | { 0, CODE_FOR_spe_evmwsmfa, "__builtin_spe_evmwsmfa", SPE_BUILTIN_EVMWSMFA }, | |
5723 | { 0, CODE_FOR_spe_evmwsmfaa, "__builtin_spe_evmwsmfaa", SPE_BUILTIN_EVMWSMFAA }, | |
5724 | { 0, CODE_FOR_spe_evmwsmfan, "__builtin_spe_evmwsmfan", SPE_BUILTIN_EVMWSMFAN }, | |
5725 | { 0, CODE_FOR_spe_evmwsmi, "__builtin_spe_evmwsmi", SPE_BUILTIN_EVMWSMI }, | |
5726 | { 0, CODE_FOR_spe_evmwsmia, "__builtin_spe_evmwsmia", SPE_BUILTIN_EVMWSMIA }, | |
5727 | { 0, CODE_FOR_spe_evmwsmiaa, "__builtin_spe_evmwsmiaa", SPE_BUILTIN_EVMWSMIAA }, | |
5728 | { 0, CODE_FOR_spe_evmwsmian, "__builtin_spe_evmwsmian", SPE_BUILTIN_EVMWSMIAN }, | |
5729 | { 0, CODE_FOR_spe_evmwssf, "__builtin_spe_evmwssf", SPE_BUILTIN_EVMWSSF }, | |
5730 | { 0, CODE_FOR_spe_evmwssfa, "__builtin_spe_evmwssfa", SPE_BUILTIN_EVMWSSFA }, | |
5731 | { 0, CODE_FOR_spe_evmwssfaa, "__builtin_spe_evmwssfaa", SPE_BUILTIN_EVMWSSFAA }, | |
5732 | { 0, CODE_FOR_spe_evmwssfan, "__builtin_spe_evmwssfan", SPE_BUILTIN_EVMWSSFAN }, | |
5733 | { 0, CODE_FOR_spe_evmwumi, "__builtin_spe_evmwumi", SPE_BUILTIN_EVMWUMI }, | |
5734 | { 0, CODE_FOR_spe_evmwumia, "__builtin_spe_evmwumia", SPE_BUILTIN_EVMWUMIA }, | |
5735 | { 0, CODE_FOR_spe_evmwumiaa, "__builtin_spe_evmwumiaa", SPE_BUILTIN_EVMWUMIAA }, | |
5736 | { 0, CODE_FOR_spe_evmwumian, "__builtin_spe_evmwumian", SPE_BUILTIN_EVMWUMIAN }, | |
5737 | { 0, CODE_FOR_spe_evnand, "__builtin_spe_evnand", SPE_BUILTIN_EVNAND }, | |
5738 | { 0, CODE_FOR_spe_evnor, "__builtin_spe_evnor", SPE_BUILTIN_EVNOR }, | |
5739 | { 0, CODE_FOR_spe_evor, "__builtin_spe_evor", SPE_BUILTIN_EVOR }, | |
5740 | { 0, CODE_FOR_spe_evorc, "__builtin_spe_evorc", SPE_BUILTIN_EVORC }, | |
5741 | { 0, CODE_FOR_spe_evrlw, "__builtin_spe_evrlw", SPE_BUILTIN_EVRLW }, | |
5742 | { 0, CODE_FOR_spe_evslw, "__builtin_spe_evslw", SPE_BUILTIN_EVSLW }, | |
5743 | { 0, CODE_FOR_spe_evsrws, "__builtin_spe_evsrws", SPE_BUILTIN_EVSRWS }, | |
5744 | { 0, CODE_FOR_spe_evsrwu, "__builtin_spe_evsrwu", SPE_BUILTIN_EVSRWU }, | |
5745 | { 0, CODE_FOR_spe_evsubfw, "__builtin_spe_evsubfw", SPE_BUILTIN_EVSUBFW }, | |
5746 | ||
5747 | /* SPE binary operations expecting a 5-bit unsigned literal. */ | |
5748 | { 0, CODE_FOR_spe_evaddiw, "__builtin_spe_evaddiw", SPE_BUILTIN_EVADDIW }, | |
5749 | ||
5750 | { 0, CODE_FOR_spe_evrlwi, "__builtin_spe_evrlwi", SPE_BUILTIN_EVRLWI }, | |
5751 | { 0, CODE_FOR_spe_evslwi, "__builtin_spe_evslwi", SPE_BUILTIN_EVSLWI }, | |
5752 | { 0, CODE_FOR_spe_evsrwis, "__builtin_spe_evsrwis", SPE_BUILTIN_EVSRWIS }, | |
5753 | { 0, CODE_FOR_spe_evsrwiu, "__builtin_spe_evsrwiu", SPE_BUILTIN_EVSRWIU }, | |
5754 | { 0, CODE_FOR_spe_evsubifw, "__builtin_spe_evsubifw", SPE_BUILTIN_EVSUBIFW }, | |
5755 | { 0, CODE_FOR_spe_evmwhssfaa, "__builtin_spe_evmwhssfaa", SPE_BUILTIN_EVMWHSSFAA }, | |
5756 | { 0, CODE_FOR_spe_evmwhssmaa, "__builtin_spe_evmwhssmaa", SPE_BUILTIN_EVMWHSSMAA }, | |
5757 | { 0, CODE_FOR_spe_evmwhsmfaa, "__builtin_spe_evmwhsmfaa", SPE_BUILTIN_EVMWHSMFAA }, | |
5758 | { 0, CODE_FOR_spe_evmwhsmiaa, "__builtin_spe_evmwhsmiaa", SPE_BUILTIN_EVMWHSMIAA }, | |
5759 | { 0, CODE_FOR_spe_evmwhusiaa, "__builtin_spe_evmwhusiaa", SPE_BUILTIN_EVMWHUSIAA }, | |
5760 | { 0, CODE_FOR_spe_evmwhumiaa, "__builtin_spe_evmwhumiaa", SPE_BUILTIN_EVMWHUMIAA }, | |
5761 | { 0, CODE_FOR_spe_evmwhssfan, "__builtin_spe_evmwhssfan", SPE_BUILTIN_EVMWHSSFAN }, | |
5762 | { 0, CODE_FOR_spe_evmwhssian, "__builtin_spe_evmwhssian", SPE_BUILTIN_EVMWHSSIAN }, | |
5763 | { 0, CODE_FOR_spe_evmwhsmfan, "__builtin_spe_evmwhsmfan", SPE_BUILTIN_EVMWHSMFAN }, | |
5764 | { 0, CODE_FOR_spe_evmwhsmian, "__builtin_spe_evmwhsmian", SPE_BUILTIN_EVMWHSMIAN }, | |
5765 | { 0, CODE_FOR_spe_evmwhusian, "__builtin_spe_evmwhusian", SPE_BUILTIN_EVMWHUSIAN }, | |
5766 | { 0, CODE_FOR_spe_evmwhumian, "__builtin_spe_evmwhumian", SPE_BUILTIN_EVMWHUMIAN }, | |
5767 | { 0, CODE_FOR_spe_evmwhgssfaa, "__builtin_spe_evmwhgssfaa", SPE_BUILTIN_EVMWHGSSFAA }, | |
5768 | { 0, CODE_FOR_spe_evmwhgsmfaa, "__builtin_spe_evmwhgsmfaa", SPE_BUILTIN_EVMWHGSMFAA }, | |
5769 | { 0, CODE_FOR_spe_evmwhgsmiaa, "__builtin_spe_evmwhgsmiaa", SPE_BUILTIN_EVMWHGSMIAA }, | |
5770 | { 0, CODE_FOR_spe_evmwhgumiaa, "__builtin_spe_evmwhgumiaa", SPE_BUILTIN_EVMWHGUMIAA }, | |
5771 | { 0, CODE_FOR_spe_evmwhgssfan, "__builtin_spe_evmwhgssfan", SPE_BUILTIN_EVMWHGSSFAN }, | |
5772 | { 0, CODE_FOR_spe_evmwhgsmfan, "__builtin_spe_evmwhgsmfan", SPE_BUILTIN_EVMWHGSMFAN }, | |
5773 | { 0, CODE_FOR_spe_evmwhgsmian, "__builtin_spe_evmwhgsmian", SPE_BUILTIN_EVMWHGSMIAN }, | |
5774 | { 0, CODE_FOR_spe_evmwhgumian, "__builtin_spe_evmwhgumian", SPE_BUILTIN_EVMWHGUMIAN }, | |
5775 | { 0, CODE_FOR_spe_brinc, "__builtin_spe_brinc", SPE_BUILTIN_BRINC }, | |
5776 | ||
5777 | /* Place-holder. Leave as last binary SPE builtin. */ | |
17edbda5 | 5778 | { 0, CODE_FOR_xorv2si3, "__builtin_spe_evxor", SPE_BUILTIN_EVXOR }, |
ae4b4a02 AH |
5779 | }; |
5780 | ||
5781 | /* AltiVec predicates. */ | |
5782 | ||
5783 | struct builtin_description_predicates | |
5784 | { | |
5785 | const unsigned int mask; | |
5786 | const enum insn_code icode; | |
5787 | const char *opcode; | |
5788 | const char *const name; | |
5789 | const enum rs6000_builtins code; | |
5790 | }; | |
5791 | ||
5792 | static const struct builtin_description_predicates bdesc_altivec_preds[] = | |
5793 | { | |
5794 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpbfp.", "__builtin_altivec_vcmpbfp_p", ALTIVEC_BUILTIN_VCMPBFP_P }, | |
5795 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpeqfp.", "__builtin_altivec_vcmpeqfp_p", ALTIVEC_BUILTIN_VCMPEQFP_P }, | |
5796 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpgefp.", "__builtin_altivec_vcmpgefp_p", ALTIVEC_BUILTIN_VCMPGEFP_P }, | |
5797 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpgtfp.", "__builtin_altivec_vcmpgtfp_p", ALTIVEC_BUILTIN_VCMPGTFP_P }, | |
5798 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpequw.", "__builtin_altivec_vcmpequw_p", ALTIVEC_BUILTIN_VCMPEQUW_P }, | |
5799 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpgtsw.", "__builtin_altivec_vcmpgtsw_p", ALTIVEC_BUILTIN_VCMPGTSW_P }, | |
5800 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpgtuw.", "__builtin_altivec_vcmpgtuw_p", ALTIVEC_BUILTIN_VCMPGTUW_P }, | |
5801 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpgtuh.", "__builtin_altivec_vcmpgtuh_p", ALTIVEC_BUILTIN_VCMPGTUH_P }, | |
5802 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpgtsh.", "__builtin_altivec_vcmpgtsh_p", ALTIVEC_BUILTIN_VCMPGTSH_P }, | |
5803 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpequh.", "__builtin_altivec_vcmpequh_p", ALTIVEC_BUILTIN_VCMPEQUH_P }, | |
5804 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpequb.", "__builtin_altivec_vcmpequb_p", ALTIVEC_BUILTIN_VCMPEQUB_P }, | |
5805 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpgtsb.", "__builtin_altivec_vcmpgtsb_p", ALTIVEC_BUILTIN_VCMPGTSB_P }, | |
5806 | { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpgtub.", "__builtin_altivec_vcmpgtub_p", ALTIVEC_BUILTIN_VCMPGTUB_P } | |
0ac081f6 | 5807 | }; |
24408032 | 5808 | |
a3170dc6 AH |
5809 | /* SPE predicates. */ |
5810 | static struct builtin_description bdesc_spe_predicates[] = | |
5811 | { | |
5812 | /* Place-holder. Leave as first. */ | |
5813 | { 0, CODE_FOR_spe_evcmpeq, "__builtin_spe_evcmpeq", SPE_BUILTIN_EVCMPEQ }, | |
5814 | { 0, CODE_FOR_spe_evcmpgts, "__builtin_spe_evcmpgts", SPE_BUILTIN_EVCMPGTS }, | |
5815 | { 0, CODE_FOR_spe_evcmpgtu, "__builtin_spe_evcmpgtu", SPE_BUILTIN_EVCMPGTU }, | |
5816 | { 0, CODE_FOR_spe_evcmplts, "__builtin_spe_evcmplts", SPE_BUILTIN_EVCMPLTS }, | |
5817 | { 0, CODE_FOR_spe_evcmpltu, "__builtin_spe_evcmpltu", SPE_BUILTIN_EVCMPLTU }, | |
5818 | { 0, CODE_FOR_spe_evfscmpeq, "__builtin_spe_evfscmpeq", SPE_BUILTIN_EVFSCMPEQ }, | |
5819 | { 0, CODE_FOR_spe_evfscmpgt, "__builtin_spe_evfscmpgt", SPE_BUILTIN_EVFSCMPGT }, | |
5820 | { 0, CODE_FOR_spe_evfscmplt, "__builtin_spe_evfscmplt", SPE_BUILTIN_EVFSCMPLT }, | |
5821 | { 0, CODE_FOR_spe_evfststeq, "__builtin_spe_evfststeq", SPE_BUILTIN_EVFSTSTEQ }, | |
5822 | { 0, CODE_FOR_spe_evfststgt, "__builtin_spe_evfststgt", SPE_BUILTIN_EVFSTSTGT }, | |
5823 | /* Place-holder. Leave as last. */ | |
5824 | { 0, CODE_FOR_spe_evfststlt, "__builtin_spe_evfststlt", SPE_BUILTIN_EVFSTSTLT }, | |
5825 | }; | |
5826 | ||
5827 | /* SPE evsel predicates. */ | |
5828 | static struct builtin_description bdesc_spe_evsel[] = | |
5829 | { | |
5830 | /* Place-holder. Leave as first. */ | |
5831 | { 0, CODE_FOR_spe_evcmpgts, "__builtin_spe_evsel_gts", SPE_BUILTIN_EVSEL_CMPGTS }, | |
5832 | { 0, CODE_FOR_spe_evcmpgtu, "__builtin_spe_evsel_gtu", SPE_BUILTIN_EVSEL_CMPGTU }, | |
5833 | { 0, CODE_FOR_spe_evcmplts, "__builtin_spe_evsel_lts", SPE_BUILTIN_EVSEL_CMPLTS }, | |
5834 | { 0, CODE_FOR_spe_evcmpltu, "__builtin_spe_evsel_ltu", SPE_BUILTIN_EVSEL_CMPLTU }, | |
5835 | { 0, CODE_FOR_spe_evcmpeq, "__builtin_spe_evsel_eq", SPE_BUILTIN_EVSEL_CMPEQ }, | |
5836 | { 0, CODE_FOR_spe_evfscmpgt, "__builtin_spe_evsel_fsgt", SPE_BUILTIN_EVSEL_FSCMPGT }, | |
5837 | { 0, CODE_FOR_spe_evfscmplt, "__builtin_spe_evsel_fslt", SPE_BUILTIN_EVSEL_FSCMPLT }, | |
5838 | { 0, CODE_FOR_spe_evfscmpeq, "__builtin_spe_evsel_fseq", SPE_BUILTIN_EVSEL_FSCMPEQ }, | |
5839 | { 0, CODE_FOR_spe_evfststgt, "__builtin_spe_evsel_fststgt", SPE_BUILTIN_EVSEL_FSTSTGT }, | |
5840 | { 0, CODE_FOR_spe_evfststlt, "__builtin_spe_evsel_fststlt", SPE_BUILTIN_EVSEL_FSTSTLT }, | |
5841 | /* Place-holder. Leave as last. */ | |
5842 | { 0, CODE_FOR_spe_evfststeq, "__builtin_spe_evsel_fststeq", SPE_BUILTIN_EVSEL_FSTSTEQ }, | |
5843 | }; | |
5844 | ||
b6d08ca1 | 5845 | /* ABS* operations. */ |
100c4561 AH |
5846 | |
5847 | static const struct builtin_description bdesc_abs[] = | |
5848 | { | |
5849 | { MASK_ALTIVEC, CODE_FOR_absv4si2, "__builtin_altivec_abs_v4si", ALTIVEC_BUILTIN_ABS_V4SI }, | |
5850 | { MASK_ALTIVEC, CODE_FOR_absv8hi2, "__builtin_altivec_abs_v8hi", ALTIVEC_BUILTIN_ABS_V8HI }, | |
5851 | { MASK_ALTIVEC, CODE_FOR_absv4sf2, "__builtin_altivec_abs_v4sf", ALTIVEC_BUILTIN_ABS_V4SF }, | |
5852 | { MASK_ALTIVEC, CODE_FOR_absv16qi2, "__builtin_altivec_abs_v16qi", ALTIVEC_BUILTIN_ABS_V16QI }, | |
5853 | { MASK_ALTIVEC, CODE_FOR_altivec_abss_v4si, "__builtin_altivec_abss_v4si", ALTIVEC_BUILTIN_ABSS_V4SI }, | |
5854 | { MASK_ALTIVEC, CODE_FOR_altivec_abss_v8hi, "__builtin_altivec_abss_v8hi", ALTIVEC_BUILTIN_ABSS_V8HI }, | |
5855 | { MASK_ALTIVEC, CODE_FOR_altivec_abss_v16qi, "__builtin_altivec_abss_v16qi", ALTIVEC_BUILTIN_ABSS_V16QI } | |
5856 | }; | |
5857 | ||
617e0e1d DB |
5858 | /* Simple unary operations: VECb = foo (unsigned literal) or VECb = |
5859 | foo (VECa). */ | |
24408032 | 5860 | |
a3170dc6 | 5861 | static struct builtin_description bdesc_1arg[] = |
2212663f | 5862 | { |
617e0e1d DB |
5863 | { MASK_ALTIVEC, CODE_FOR_altivec_vexptefp, "__builtin_altivec_vexptefp", ALTIVEC_BUILTIN_VEXPTEFP }, |
5864 | { MASK_ALTIVEC, CODE_FOR_altivec_vlogefp, "__builtin_altivec_vlogefp", ALTIVEC_BUILTIN_VLOGEFP }, | |
5865 | { MASK_ALTIVEC, CODE_FOR_altivec_vrefp, "__builtin_altivec_vrefp", ALTIVEC_BUILTIN_VREFP }, | |
5866 | { MASK_ALTIVEC, CODE_FOR_altivec_vrfim, "__builtin_altivec_vrfim", ALTIVEC_BUILTIN_VRFIM }, | |
5867 | { MASK_ALTIVEC, CODE_FOR_altivec_vrfin, "__builtin_altivec_vrfin", ALTIVEC_BUILTIN_VRFIN }, | |
5868 | { MASK_ALTIVEC, CODE_FOR_altivec_vrfip, "__builtin_altivec_vrfip", ALTIVEC_BUILTIN_VRFIP }, | |
5869 | { MASK_ALTIVEC, CODE_FOR_ftruncv4sf2, "__builtin_altivec_vrfiz", ALTIVEC_BUILTIN_VRFIZ }, | |
5870 | { MASK_ALTIVEC, CODE_FOR_altivec_vrsqrtefp, "__builtin_altivec_vrsqrtefp", ALTIVEC_BUILTIN_VRSQRTEFP }, | |
2212663f DB |
5871 | { MASK_ALTIVEC, CODE_FOR_altivec_vspltisb, "__builtin_altivec_vspltisb", ALTIVEC_BUILTIN_VSPLTISB }, |
5872 | { MASK_ALTIVEC, CODE_FOR_altivec_vspltish, "__builtin_altivec_vspltish", ALTIVEC_BUILTIN_VSPLTISH }, | |
5873 | { MASK_ALTIVEC, CODE_FOR_altivec_vspltisw, "__builtin_altivec_vspltisw", ALTIVEC_BUILTIN_VSPLTISW }, | |
20e26713 AH |
5874 | { MASK_ALTIVEC, CODE_FOR_altivec_vupkhsb, "__builtin_altivec_vupkhsb", ALTIVEC_BUILTIN_VUPKHSB }, |
5875 | { MASK_ALTIVEC, CODE_FOR_altivec_vupkhpx, "__builtin_altivec_vupkhpx", ALTIVEC_BUILTIN_VUPKHPX }, | |
5876 | { MASK_ALTIVEC, CODE_FOR_altivec_vupkhsh, "__builtin_altivec_vupkhsh", ALTIVEC_BUILTIN_VUPKHSH }, | |
5877 | { MASK_ALTIVEC, CODE_FOR_altivec_vupklsb, "__builtin_altivec_vupklsb", ALTIVEC_BUILTIN_VUPKLSB }, | |
5878 | { MASK_ALTIVEC, CODE_FOR_altivec_vupklpx, "__builtin_altivec_vupklpx", ALTIVEC_BUILTIN_VUPKLPX }, | |
5879 | { MASK_ALTIVEC, CODE_FOR_altivec_vupklsh, "__builtin_altivec_vupklsh", ALTIVEC_BUILTIN_VUPKLSH }, | |
a3170dc6 AH |
5880 | |
5881 | /* The SPE unary builtins must start with SPE_BUILTIN_EVABS and | |
5882 | end with SPE_BUILTIN_EVSUBFUSIAAW. */ | |
5883 | { 0, CODE_FOR_spe_evabs, "__builtin_spe_evabs", SPE_BUILTIN_EVABS }, | |
5884 | { 0, CODE_FOR_spe_evaddsmiaaw, "__builtin_spe_evaddsmiaaw", SPE_BUILTIN_EVADDSMIAAW }, | |
5885 | { 0, CODE_FOR_spe_evaddssiaaw, "__builtin_spe_evaddssiaaw", SPE_BUILTIN_EVADDSSIAAW }, | |
5886 | { 0, CODE_FOR_spe_evaddumiaaw, "__builtin_spe_evaddumiaaw", SPE_BUILTIN_EVADDUMIAAW }, | |
5887 | { 0, CODE_FOR_spe_evaddusiaaw, "__builtin_spe_evaddusiaaw", SPE_BUILTIN_EVADDUSIAAW }, | |
5888 | { 0, CODE_FOR_spe_evcntlsw, "__builtin_spe_evcntlsw", SPE_BUILTIN_EVCNTLSW }, | |
5889 | { 0, CODE_FOR_spe_evcntlzw, "__builtin_spe_evcntlzw", SPE_BUILTIN_EVCNTLZW }, | |
5890 | { 0, CODE_FOR_spe_evextsb, "__builtin_spe_evextsb", SPE_BUILTIN_EVEXTSB }, | |
5891 | { 0, CODE_FOR_spe_evextsh, "__builtin_spe_evextsh", SPE_BUILTIN_EVEXTSH }, | |
5892 | { 0, CODE_FOR_spe_evfsabs, "__builtin_spe_evfsabs", SPE_BUILTIN_EVFSABS }, | |
5893 | { 0, CODE_FOR_spe_evfscfsf, "__builtin_spe_evfscfsf", SPE_BUILTIN_EVFSCFSF }, | |
5894 | { 0, CODE_FOR_spe_evfscfsi, "__builtin_spe_evfscfsi", SPE_BUILTIN_EVFSCFSI }, | |
5895 | { 0, CODE_FOR_spe_evfscfuf, "__builtin_spe_evfscfuf", SPE_BUILTIN_EVFSCFUF }, | |
5896 | { 0, CODE_FOR_spe_evfscfui, "__builtin_spe_evfscfui", SPE_BUILTIN_EVFSCFUI }, | |
5897 | { 0, CODE_FOR_spe_evfsctsf, "__builtin_spe_evfsctsf", SPE_BUILTIN_EVFSCTSF }, | |
5898 | { 0, CODE_FOR_spe_evfsctsi, "__builtin_spe_evfsctsi", SPE_BUILTIN_EVFSCTSI }, | |
5899 | { 0, CODE_FOR_spe_evfsctsiz, "__builtin_spe_evfsctsiz", SPE_BUILTIN_EVFSCTSIZ }, | |
5900 | { 0, CODE_FOR_spe_evfsctuf, "__builtin_spe_evfsctuf", SPE_BUILTIN_EVFSCTUF }, | |
5901 | { 0, CODE_FOR_spe_evfsctui, "__builtin_spe_evfsctui", SPE_BUILTIN_EVFSCTUI }, | |
5902 | { 0, CODE_FOR_spe_evfsctuiz, "__builtin_spe_evfsctuiz", SPE_BUILTIN_EVFSCTUIZ }, | |
5903 | { 0, CODE_FOR_spe_evfsnabs, "__builtin_spe_evfsnabs", SPE_BUILTIN_EVFSNABS }, | |
5904 | { 0, CODE_FOR_spe_evfsneg, "__builtin_spe_evfsneg", SPE_BUILTIN_EVFSNEG }, | |
5905 | { 0, CODE_FOR_spe_evmra, "__builtin_spe_evmra", SPE_BUILTIN_EVMRA }, | |
6a599451 | 5906 | { 0, CODE_FOR_negv2si2, "__builtin_spe_evneg", SPE_BUILTIN_EVNEG }, |
a3170dc6 AH |
5907 | { 0, CODE_FOR_spe_evrndw, "__builtin_spe_evrndw", SPE_BUILTIN_EVRNDW }, |
5908 | { 0, CODE_FOR_spe_evsubfsmiaaw, "__builtin_spe_evsubfsmiaaw", SPE_BUILTIN_EVSUBFSMIAAW }, | |
5909 | { 0, CODE_FOR_spe_evsubfssiaaw, "__builtin_spe_evsubfssiaaw", SPE_BUILTIN_EVSUBFSSIAAW }, | |
5910 | { 0, CODE_FOR_spe_evsubfumiaaw, "__builtin_spe_evsubfumiaaw", SPE_BUILTIN_EVSUBFUMIAAW }, | |
a3170dc6 AH |
5911 | |
5912 | /* Place-holder. Leave as last unary SPE builtin. */ | |
5913 | { 0, CODE_FOR_spe_evsubfusiaaw, "__builtin_spe_evsubfusiaaw", SPE_BUILTIN_EVSUBFUSIAAW }, | |
2212663f DB |
5914 | }; |
5915 | ||
5916 | static rtx | |
a2369ed3 | 5917 | rs6000_expand_unop_builtin (enum insn_code icode, tree arglist, rtx target) |
2212663f DB |
5918 | { |
5919 | rtx pat; | |
5920 | tree arg0 = TREE_VALUE (arglist); | |
5921 | rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
5922 | enum machine_mode tmode = insn_data[icode].operand[0].mode; | |
5923 | enum machine_mode mode0 = insn_data[icode].operand[1].mode; | |
5924 | ||
0559cc77 DE |
5925 | if (icode == CODE_FOR_nothing) |
5926 | /* Builtin not supported on this processor. */ | |
5927 | return 0; | |
5928 | ||
20e26713 AH |
5929 | /* If we got invalid arguments bail out before generating bad rtl. */ |
5930 | if (arg0 == error_mark_node) | |
9a171fcd | 5931 | return const0_rtx; |
20e26713 | 5932 | |
0559cc77 DE |
5933 | if (icode == CODE_FOR_altivec_vspltisb |
5934 | || icode == CODE_FOR_altivec_vspltish | |
5935 | || icode == CODE_FOR_altivec_vspltisw | |
5936 | || icode == CODE_FOR_spe_evsplatfi | |
5937 | || icode == CODE_FOR_spe_evsplati) | |
b44140e7 AH |
5938 | { |
5939 | /* Only allow 5-bit *signed* literals. */ | |
b44140e7 AH |
5940 | if (GET_CODE (op0) != CONST_INT |
5941 | || INTVAL (op0) > 0x1f | |
5942 | || INTVAL (op0) < -0x1f) | |
5943 | { | |
5944 | error ("argument 1 must be a 5-bit signed literal"); | |
9a171fcd | 5945 | return const0_rtx; |
b44140e7 | 5946 | } |
b44140e7 AH |
5947 | } |
5948 | ||
c62f2db5 | 5949 | if (target == 0 |
2212663f DB |
5950 | || GET_MODE (target) != tmode |
5951 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
5952 | target = gen_reg_rtx (tmode); | |
5953 | ||
5954 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) | |
5955 | op0 = copy_to_mode_reg (mode0, op0); | |
5956 | ||
5957 | pat = GEN_FCN (icode) (target, op0); | |
5958 | if (! pat) | |
5959 | return 0; | |
5960 | emit_insn (pat); | |
0ac081f6 | 5961 | |
2212663f DB |
5962 | return target; |
5963 | } | |
ae4b4a02 | 5964 | |
100c4561 | 5965 | static rtx |
a2369ed3 | 5966 | altivec_expand_abs_builtin (enum insn_code icode, tree arglist, rtx target) |
100c4561 AH |
5967 | { |
5968 | rtx pat, scratch1, scratch2; | |
5969 | tree arg0 = TREE_VALUE (arglist); | |
5970 | rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
5971 | enum machine_mode tmode = insn_data[icode].operand[0].mode; | |
5972 | enum machine_mode mode0 = insn_data[icode].operand[1].mode; | |
5973 | ||
5974 | /* If we have invalid arguments, bail out before generating bad rtl. */ | |
5975 | if (arg0 == error_mark_node) | |
9a171fcd | 5976 | return const0_rtx; |
100c4561 AH |
5977 | |
5978 | if (target == 0 | |
5979 | || GET_MODE (target) != tmode | |
5980 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
5981 | target = gen_reg_rtx (tmode); | |
5982 | ||
5983 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) | |
5984 | op0 = copy_to_mode_reg (mode0, op0); | |
5985 | ||
5986 | scratch1 = gen_reg_rtx (mode0); | |
5987 | scratch2 = gen_reg_rtx (mode0); | |
5988 | ||
5989 | pat = GEN_FCN (icode) (target, op0, scratch1, scratch2); | |
5990 | if (! pat) | |
5991 | return 0; | |
5992 | emit_insn (pat); | |
5993 | ||
5994 | return target; | |
5995 | } | |
5996 | ||
0ac081f6 | 5997 | static rtx |
a2369ed3 | 5998 | rs6000_expand_binop_builtin (enum insn_code icode, tree arglist, rtx target) |
0ac081f6 AH |
5999 | { |
6000 | rtx pat; | |
6001 | tree arg0 = TREE_VALUE (arglist); | |
6002 | tree arg1 = TREE_VALUE (TREE_CHAIN (arglist)); | |
6003 | rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
6004 | rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); | |
6005 | enum machine_mode tmode = insn_data[icode].operand[0].mode; | |
6006 | enum machine_mode mode0 = insn_data[icode].operand[1].mode; | |
6007 | enum machine_mode mode1 = insn_data[icode].operand[2].mode; | |
6008 | ||
0559cc77 DE |
6009 | if (icode == CODE_FOR_nothing) |
6010 | /* Builtin not supported on this processor. */ | |
6011 | return 0; | |
6012 | ||
20e26713 AH |
6013 | /* If we got invalid arguments bail out before generating bad rtl. */ |
6014 | if (arg0 == error_mark_node || arg1 == error_mark_node) | |
9a171fcd | 6015 | return const0_rtx; |
20e26713 | 6016 | |
0559cc77 DE |
6017 | if (icode == CODE_FOR_altivec_vcfux |
6018 | || icode == CODE_FOR_altivec_vcfsx | |
6019 | || icode == CODE_FOR_altivec_vctsxs | |
6020 | || icode == CODE_FOR_altivec_vctuxs | |
6021 | || icode == CODE_FOR_altivec_vspltb | |
6022 | || icode == CODE_FOR_altivec_vsplth | |
6023 | || icode == CODE_FOR_altivec_vspltw | |
6024 | || icode == CODE_FOR_spe_evaddiw | |
6025 | || icode == CODE_FOR_spe_evldd | |
6026 | || icode == CODE_FOR_spe_evldh | |
6027 | || icode == CODE_FOR_spe_evldw | |
6028 | || icode == CODE_FOR_spe_evlhhesplat | |
6029 | || icode == CODE_FOR_spe_evlhhossplat | |
6030 | || icode == CODE_FOR_spe_evlhhousplat | |
6031 | || icode == CODE_FOR_spe_evlwhe | |
6032 | || icode == CODE_FOR_spe_evlwhos | |
6033 | || icode == CODE_FOR_spe_evlwhou | |
6034 | || icode == CODE_FOR_spe_evlwhsplat | |
6035 | || icode == CODE_FOR_spe_evlwwsplat | |
6036 | || icode == CODE_FOR_spe_evrlwi | |
6037 | || icode == CODE_FOR_spe_evslwi | |
6038 | || icode == CODE_FOR_spe_evsrwis | |
f5119d10 | 6039 | || icode == CODE_FOR_spe_evsubifw |
0559cc77 | 6040 | || icode == CODE_FOR_spe_evsrwiu) |
b44140e7 AH |
6041 | { |
6042 | /* Only allow 5-bit unsigned literals. */ | |
8bb418a3 | 6043 | STRIP_NOPS (arg1); |
b44140e7 AH |
6044 | if (TREE_CODE (arg1) != INTEGER_CST |
6045 | || TREE_INT_CST_LOW (arg1) & ~0x1f) | |
6046 | { | |
6047 | error ("argument 2 must be a 5-bit unsigned literal"); | |
9a171fcd | 6048 | return const0_rtx; |
b44140e7 | 6049 | } |
b44140e7 AH |
6050 | } |
6051 | ||
c62f2db5 | 6052 | if (target == 0 |
0ac081f6 AH |
6053 | || GET_MODE (target) != tmode |
6054 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
6055 | target = gen_reg_rtx (tmode); | |
6056 | ||
6057 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) | |
6058 | op0 = copy_to_mode_reg (mode0, op0); | |
6059 | if (! (*insn_data[icode].operand[2].predicate) (op1, mode1)) | |
6060 | op1 = copy_to_mode_reg (mode1, op1); | |
6061 | ||
6062 | pat = GEN_FCN (icode) (target, op0, op1); | |
6063 | if (! pat) | |
6064 | return 0; | |
6065 | emit_insn (pat); | |
6066 | ||
6067 | return target; | |
6068 | } | |
6525c0e7 | 6069 | |
ae4b4a02 | 6070 | static rtx |
f676971a | 6071 | altivec_expand_predicate_builtin (enum insn_code icode, const char *opcode, |
a2369ed3 | 6072 | tree arglist, rtx target) |
ae4b4a02 AH |
6073 | { |
6074 | rtx pat, scratch; | |
6075 | tree cr6_form = TREE_VALUE (arglist); | |
6076 | tree arg0 = TREE_VALUE (TREE_CHAIN (arglist)); | |
6077 | tree arg1 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist))); | |
6078 | rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
6079 | rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); | |
6080 | enum machine_mode tmode = SImode; | |
6081 | enum machine_mode mode0 = insn_data[icode].operand[1].mode; | |
6082 | enum machine_mode mode1 = insn_data[icode].operand[2].mode; | |
6083 | int cr6_form_int; | |
6084 | ||
6085 | if (TREE_CODE (cr6_form) != INTEGER_CST) | |
6086 | { | |
6087 | error ("argument 1 of __builtin_altivec_predicate must be a constant"); | |
9a171fcd | 6088 | return const0_rtx; |
ae4b4a02 AH |
6089 | } |
6090 | else | |
6091 | cr6_form_int = TREE_INT_CST_LOW (cr6_form); | |
6092 | ||
6093 | if (mode0 != mode1) | |
6094 | abort (); | |
6095 | ||
6096 | /* If we have invalid arguments, bail out before generating bad rtl. */ | |
6097 | if (arg0 == error_mark_node || arg1 == error_mark_node) | |
9a171fcd | 6098 | return const0_rtx; |
ae4b4a02 AH |
6099 | |
6100 | if (target == 0 | |
6101 | || GET_MODE (target) != tmode | |
6102 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
6103 | target = gen_reg_rtx (tmode); | |
6104 | ||
6105 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) | |
6106 | op0 = copy_to_mode_reg (mode0, op0); | |
6107 | if (! (*insn_data[icode].operand[2].predicate) (op1, mode1)) | |
6108 | op1 = copy_to_mode_reg (mode1, op1); | |
6109 | ||
6110 | scratch = gen_reg_rtx (mode0); | |
6111 | ||
6112 | pat = GEN_FCN (icode) (scratch, op0, op1, | |
f1c25d3b | 6113 | gen_rtx_SYMBOL_REF (Pmode, opcode)); |
ae4b4a02 AH |
6114 | if (! pat) |
6115 | return 0; | |
6116 | emit_insn (pat); | |
6117 | ||
6118 | /* The vec_any* and vec_all* predicates use the same opcodes for two | |
6119 | different operations, but the bits in CR6 will be different | |
6120 | depending on what information we want. So we have to play tricks | |
6121 | with CR6 to get the right bits out. | |
6122 | ||
6123 | If you think this is disgusting, look at the specs for the | |
6124 | AltiVec predicates. */ | |
6125 | ||
c4ad648e AM |
6126 | switch (cr6_form_int) |
6127 | { | |
6128 | case 0: | |
6129 | emit_insn (gen_cr6_test_for_zero (target)); | |
6130 | break; | |
6131 | case 1: | |
6132 | emit_insn (gen_cr6_test_for_zero_reverse (target)); | |
6133 | break; | |
6134 | case 2: | |
6135 | emit_insn (gen_cr6_test_for_lt (target)); | |
6136 | break; | |
6137 | case 3: | |
6138 | emit_insn (gen_cr6_test_for_lt_reverse (target)); | |
6139 | break; | |
6140 | default: | |
6141 | error ("argument 1 of __builtin_altivec_predicate is out of range"); | |
6142 | break; | |
6143 | } | |
ae4b4a02 AH |
6144 | |
6145 | return target; | |
6146 | } | |
6147 | ||
b4a62fa0 | 6148 | static rtx |
38f391a5 | 6149 | altivec_expand_lv_builtin (enum insn_code icode, tree arglist, rtx target) |
b4a62fa0 SB |
6150 | { |
6151 | rtx pat, addr; | |
6152 | tree arg0 = TREE_VALUE (arglist); | |
6153 | tree arg1 = TREE_VALUE (TREE_CHAIN (arglist)); | |
6154 | enum machine_mode tmode = insn_data[icode].operand[0].mode; | |
6155 | enum machine_mode mode0 = Pmode; | |
6156 | enum machine_mode mode1 = Pmode; | |
6157 | rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
6158 | rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); | |
6159 | ||
6160 | if (icode == CODE_FOR_nothing) | |
6161 | /* Builtin not supported on this processor. */ | |
6162 | return 0; | |
6163 | ||
6164 | /* If we got invalid arguments bail out before generating bad rtl. */ | |
6165 | if (arg0 == error_mark_node || arg1 == error_mark_node) | |
6166 | return const0_rtx; | |
6167 | ||
6168 | if (target == 0 | |
6169 | || GET_MODE (target) != tmode | |
6170 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
6171 | target = gen_reg_rtx (tmode); | |
6172 | ||
f676971a | 6173 | op1 = copy_to_mode_reg (mode1, op1); |
b4a62fa0 SB |
6174 | |
6175 | if (op0 == const0_rtx) | |
6176 | { | |
6177 | addr = gen_rtx_MEM (tmode, op1); | |
6178 | } | |
6179 | else | |
6180 | { | |
6181 | op0 = copy_to_mode_reg (mode0, op0); | |
6182 | addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op0, op1)); | |
6183 | } | |
6184 | ||
6185 | pat = GEN_FCN (icode) (target, addr); | |
6186 | ||
6187 | if (! pat) | |
6188 | return 0; | |
6189 | emit_insn (pat); | |
6190 | ||
6191 | return target; | |
6192 | } | |
6193 | ||
61bea3b0 AH |
6194 | static rtx |
6195 | spe_expand_stv_builtin (enum insn_code icode, tree arglist) | |
6196 | { | |
6197 | tree arg0 = TREE_VALUE (arglist); | |
6198 | tree arg1 = TREE_VALUE (TREE_CHAIN (arglist)); | |
6199 | tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist))); | |
6200 | rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
6201 | rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); | |
6202 | rtx op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0); | |
6203 | rtx pat; | |
6204 | enum machine_mode mode0 = insn_data[icode].operand[0].mode; | |
6205 | enum machine_mode mode1 = insn_data[icode].operand[1].mode; | |
6206 | enum machine_mode mode2 = insn_data[icode].operand[2].mode; | |
6207 | ||
6208 | /* Invalid arguments. Bail before doing anything stoopid! */ | |
6209 | if (arg0 == error_mark_node | |
6210 | || arg1 == error_mark_node | |
6211 | || arg2 == error_mark_node) | |
6212 | return const0_rtx; | |
6213 | ||
6214 | if (! (*insn_data[icode].operand[2].predicate) (op0, mode2)) | |
6215 | op0 = copy_to_mode_reg (mode2, op0); | |
6216 | if (! (*insn_data[icode].operand[0].predicate) (op1, mode0)) | |
6217 | op1 = copy_to_mode_reg (mode0, op1); | |
6218 | if (! (*insn_data[icode].operand[1].predicate) (op2, mode1)) | |
6219 | op2 = copy_to_mode_reg (mode1, op2); | |
6220 | ||
6221 | pat = GEN_FCN (icode) (op1, op2, op0); | |
6222 | if (pat) | |
6223 | emit_insn (pat); | |
6224 | return NULL_RTX; | |
6225 | } | |
6226 | ||
6525c0e7 | 6227 | static rtx |
a2369ed3 | 6228 | altivec_expand_stv_builtin (enum insn_code icode, tree arglist) |
6525c0e7 AH |
6229 | { |
6230 | tree arg0 = TREE_VALUE (arglist); | |
6231 | tree arg1 = TREE_VALUE (TREE_CHAIN (arglist)); | |
6232 | tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist))); | |
6233 | rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
6234 | rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); | |
6235 | rtx op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0); | |
b4a62fa0 SB |
6236 | rtx pat, addr; |
6237 | enum machine_mode tmode = insn_data[icode].operand[0].mode; | |
6238 | enum machine_mode mode1 = Pmode; | |
6239 | enum machine_mode mode2 = Pmode; | |
6525c0e7 AH |
6240 | |
6241 | /* Invalid arguments. Bail before doing anything stoopid! */ | |
6242 | if (arg0 == error_mark_node | |
6243 | || arg1 == error_mark_node | |
6244 | || arg2 == error_mark_node) | |
9a171fcd | 6245 | return const0_rtx; |
6525c0e7 | 6246 | |
b4a62fa0 SB |
6247 | if (! (*insn_data[icode].operand[1].predicate) (op0, tmode)) |
6248 | op0 = copy_to_mode_reg (tmode, op0); | |
6249 | ||
f676971a | 6250 | op2 = copy_to_mode_reg (mode2, op2); |
b4a62fa0 SB |
6251 | |
6252 | if (op1 == const0_rtx) | |
6253 | { | |
6254 | addr = gen_rtx_MEM (tmode, op2); | |
6255 | } | |
6256 | else | |
6257 | { | |
6258 | op1 = copy_to_mode_reg (mode1, op1); | |
6259 | addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op1, op2)); | |
6260 | } | |
6525c0e7 | 6261 | |
b4a62fa0 | 6262 | pat = GEN_FCN (icode) (addr, op0); |
6525c0e7 AH |
6263 | if (pat) |
6264 | emit_insn (pat); | |
6265 | return NULL_RTX; | |
6266 | } | |
6267 | ||
2212663f | 6268 | static rtx |
a2369ed3 | 6269 | rs6000_expand_ternop_builtin (enum insn_code icode, tree arglist, rtx target) |
2212663f DB |
6270 | { |
6271 | rtx pat; | |
6272 | tree arg0 = TREE_VALUE (arglist); | |
6273 | tree arg1 = TREE_VALUE (TREE_CHAIN (arglist)); | |
6274 | tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist))); | |
6275 | rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
6276 | rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); | |
6277 | rtx op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0); | |
6278 | enum machine_mode tmode = insn_data[icode].operand[0].mode; | |
6279 | enum machine_mode mode0 = insn_data[icode].operand[1].mode; | |
6280 | enum machine_mode mode1 = insn_data[icode].operand[2].mode; | |
6281 | enum machine_mode mode2 = insn_data[icode].operand[3].mode; | |
0ac081f6 | 6282 | |
774b5662 DE |
6283 | if (icode == CODE_FOR_nothing) |
6284 | /* Builtin not supported on this processor. */ | |
6285 | return 0; | |
6286 | ||
20e26713 AH |
6287 | /* If we got invalid arguments bail out before generating bad rtl. */ |
6288 | if (arg0 == error_mark_node | |
6289 | || arg1 == error_mark_node | |
6290 | || arg2 == error_mark_node) | |
9a171fcd | 6291 | return const0_rtx; |
20e26713 | 6292 | |
aba5fb01 NS |
6293 | if (icode == CODE_FOR_altivec_vsldoi_v4sf |
6294 | || icode == CODE_FOR_altivec_vsldoi_v4si | |
6295 | || icode == CODE_FOR_altivec_vsldoi_v8hi | |
6296 | || icode == CODE_FOR_altivec_vsldoi_v16qi) | |
b44140e7 AH |
6297 | { |
6298 | /* Only allow 4-bit unsigned literals. */ | |
8bb418a3 | 6299 | STRIP_NOPS (arg2); |
b44140e7 AH |
6300 | if (TREE_CODE (arg2) != INTEGER_CST |
6301 | || TREE_INT_CST_LOW (arg2) & ~0xf) | |
6302 | { | |
6303 | error ("argument 3 must be a 4-bit unsigned literal"); | |
e3277ffb | 6304 | return const0_rtx; |
b44140e7 | 6305 | } |
b44140e7 AH |
6306 | } |
6307 | ||
c62f2db5 | 6308 | if (target == 0 |
2212663f DB |
6309 | || GET_MODE (target) != tmode |
6310 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
6311 | target = gen_reg_rtx (tmode); | |
6312 | ||
6313 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) | |
6314 | op0 = copy_to_mode_reg (mode0, op0); | |
6315 | if (! (*insn_data[icode].operand[2].predicate) (op1, mode1)) | |
6316 | op1 = copy_to_mode_reg (mode1, op1); | |
6317 | if (! (*insn_data[icode].operand[3].predicate) (op2, mode2)) | |
6318 | op2 = copy_to_mode_reg (mode2, op2); | |
6319 | ||
6320 | pat = GEN_FCN (icode) (target, op0, op1, op2); | |
6321 | if (! pat) | |
6322 | return 0; | |
6323 | emit_insn (pat); | |
6324 | ||
6325 | return target; | |
6326 | } | |
92898235 | 6327 | |
3a9b8c7e | 6328 | /* Expand the lvx builtins. */ |
0ac081f6 | 6329 | static rtx |
a2369ed3 | 6330 | altivec_expand_ld_builtin (tree exp, rtx target, bool *expandedp) |
0ac081f6 | 6331 | { |
0ac081f6 AH |
6332 | tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0); |
6333 | tree arglist = TREE_OPERAND (exp, 1); | |
0ac081f6 | 6334 | unsigned int fcode = DECL_FUNCTION_CODE (fndecl); |
3a9b8c7e AH |
6335 | tree arg0; |
6336 | enum machine_mode tmode, mode0; | |
7c3abc73 | 6337 | rtx pat, op0; |
3a9b8c7e | 6338 | enum insn_code icode; |
92898235 | 6339 | |
0ac081f6 AH |
6340 | switch (fcode) |
6341 | { | |
f18c054f | 6342 | case ALTIVEC_BUILTIN_LD_INTERNAL_16qi: |
81466555 | 6343 | icode = CODE_FOR_altivec_lvx_v16qi; |
3a9b8c7e | 6344 | break; |
f18c054f | 6345 | case ALTIVEC_BUILTIN_LD_INTERNAL_8hi: |
81466555 | 6346 | icode = CODE_FOR_altivec_lvx_v8hi; |
3a9b8c7e AH |
6347 | break; |
6348 | case ALTIVEC_BUILTIN_LD_INTERNAL_4si: | |
81466555 | 6349 | icode = CODE_FOR_altivec_lvx_v4si; |
3a9b8c7e AH |
6350 | break; |
6351 | case ALTIVEC_BUILTIN_LD_INTERNAL_4sf: | |
81466555 | 6352 | icode = CODE_FOR_altivec_lvx_v4sf; |
3a9b8c7e AH |
6353 | break; |
6354 | default: | |
6355 | *expandedp = false; | |
6356 | return NULL_RTX; | |
6357 | } | |
0ac081f6 | 6358 | |
3a9b8c7e | 6359 | *expandedp = true; |
f18c054f | 6360 | |
3a9b8c7e AH |
6361 | arg0 = TREE_VALUE (arglist); |
6362 | op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
6363 | tmode = insn_data[icode].operand[0].mode; | |
6364 | mode0 = insn_data[icode].operand[1].mode; | |
f18c054f | 6365 | |
3a9b8c7e AH |
6366 | if (target == 0 |
6367 | || GET_MODE (target) != tmode | |
6368 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
6369 | target = gen_reg_rtx (tmode); | |
24408032 | 6370 | |
3a9b8c7e AH |
6371 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) |
6372 | op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0)); | |
f18c054f | 6373 | |
3a9b8c7e AH |
6374 | pat = GEN_FCN (icode) (target, op0); |
6375 | if (! pat) | |
6376 | return 0; | |
6377 | emit_insn (pat); | |
6378 | return target; | |
6379 | } | |
f18c054f | 6380 | |
3a9b8c7e AH |
6381 | /* Expand the stvx builtins. */ |
6382 | static rtx | |
f676971a | 6383 | altivec_expand_st_builtin (tree exp, rtx target ATTRIBUTE_UNUSED, |
a2369ed3 | 6384 | bool *expandedp) |
3a9b8c7e AH |
6385 | { |
6386 | tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0); | |
6387 | tree arglist = TREE_OPERAND (exp, 1); | |
6388 | unsigned int fcode = DECL_FUNCTION_CODE (fndecl); | |
6389 | tree arg0, arg1; | |
6390 | enum machine_mode mode0, mode1; | |
7c3abc73 | 6391 | rtx pat, op0, op1; |
3a9b8c7e | 6392 | enum insn_code icode; |
f18c054f | 6393 | |
3a9b8c7e AH |
6394 | switch (fcode) |
6395 | { | |
6396 | case ALTIVEC_BUILTIN_ST_INTERNAL_16qi: | |
81466555 | 6397 | icode = CODE_FOR_altivec_stvx_v16qi; |
3a9b8c7e AH |
6398 | break; |
6399 | case ALTIVEC_BUILTIN_ST_INTERNAL_8hi: | |
81466555 | 6400 | icode = CODE_FOR_altivec_stvx_v8hi; |
3a9b8c7e AH |
6401 | break; |
6402 | case ALTIVEC_BUILTIN_ST_INTERNAL_4si: | |
81466555 | 6403 | icode = CODE_FOR_altivec_stvx_v4si; |
3a9b8c7e AH |
6404 | break; |
6405 | case ALTIVEC_BUILTIN_ST_INTERNAL_4sf: | |
81466555 | 6406 | icode = CODE_FOR_altivec_stvx_v4sf; |
3a9b8c7e AH |
6407 | break; |
6408 | default: | |
6409 | *expandedp = false; | |
6410 | return NULL_RTX; | |
6411 | } | |
24408032 | 6412 | |
3a9b8c7e AH |
6413 | arg0 = TREE_VALUE (arglist); |
6414 | arg1 = TREE_VALUE (TREE_CHAIN (arglist)); | |
6415 | op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
6416 | op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); | |
6417 | mode0 = insn_data[icode].operand[0].mode; | |
6418 | mode1 = insn_data[icode].operand[1].mode; | |
f18c054f | 6419 | |
3a9b8c7e AH |
6420 | if (! (*insn_data[icode].operand[0].predicate) (op0, mode0)) |
6421 | op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0)); | |
6422 | if (! (*insn_data[icode].operand[1].predicate) (op1, mode1)) | |
6423 | op1 = copy_to_mode_reg (mode1, op1); | |
f18c054f | 6424 | |
3a9b8c7e AH |
6425 | pat = GEN_FCN (icode) (op0, op1); |
6426 | if (pat) | |
6427 | emit_insn (pat); | |
f18c054f | 6428 | |
3a9b8c7e AH |
6429 | *expandedp = true; |
6430 | return NULL_RTX; | |
6431 | } | |
f18c054f | 6432 | |
3a9b8c7e AH |
6433 | /* Expand the dst builtins. */ |
6434 | static rtx | |
f676971a | 6435 | altivec_expand_dst_builtin (tree exp, rtx target ATTRIBUTE_UNUSED, |
a2369ed3 | 6436 | bool *expandedp) |
3a9b8c7e AH |
6437 | { |
6438 | tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0); | |
6439 | tree arglist = TREE_OPERAND (exp, 1); | |
6440 | unsigned int fcode = DECL_FUNCTION_CODE (fndecl); | |
6441 | tree arg0, arg1, arg2; | |
6442 | enum machine_mode mode0, mode1, mode2; | |
7c3abc73 | 6443 | rtx pat, op0, op1, op2; |
3a9b8c7e | 6444 | struct builtin_description *d; |
a3170dc6 | 6445 | size_t i; |
f18c054f | 6446 | |
3a9b8c7e | 6447 | *expandedp = false; |
f18c054f | 6448 | |
3a9b8c7e AH |
6449 | /* Handle DST variants. */ |
6450 | d = (struct builtin_description *) bdesc_dst; | |
6451 | for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++) | |
6452 | if (d->code == fcode) | |
6453 | { | |
6454 | arg0 = TREE_VALUE (arglist); | |
6455 | arg1 = TREE_VALUE (TREE_CHAIN (arglist)); | |
6456 | arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist))); | |
6457 | op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
6458 | op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); | |
6459 | op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0); | |
6460 | mode0 = insn_data[d->icode].operand[0].mode; | |
6461 | mode1 = insn_data[d->icode].operand[1].mode; | |
6462 | mode2 = insn_data[d->icode].operand[2].mode; | |
24408032 | 6463 | |
3a9b8c7e AH |
6464 | /* Invalid arguments, bail out before generating bad rtl. */ |
6465 | if (arg0 == error_mark_node | |
6466 | || arg1 == error_mark_node | |
6467 | || arg2 == error_mark_node) | |
6468 | return const0_rtx; | |
f18c054f | 6469 | |
86e7df90 | 6470 | *expandedp = true; |
8bb418a3 | 6471 | STRIP_NOPS (arg2); |
3a9b8c7e AH |
6472 | if (TREE_CODE (arg2) != INTEGER_CST |
6473 | || TREE_INT_CST_LOW (arg2) & ~0x3) | |
6474 | { | |
9e637a26 | 6475 | error ("argument to %qs must be a 2-bit unsigned literal", d->name); |
3a9b8c7e AH |
6476 | return const0_rtx; |
6477 | } | |
f18c054f | 6478 | |
3a9b8c7e | 6479 | if (! (*insn_data[d->icode].operand[0].predicate) (op0, mode0)) |
666158b9 | 6480 | op0 = copy_to_mode_reg (Pmode, op0); |
3a9b8c7e AH |
6481 | if (! (*insn_data[d->icode].operand[1].predicate) (op1, mode1)) |
6482 | op1 = copy_to_mode_reg (mode1, op1); | |
24408032 | 6483 | |
3a9b8c7e AH |
6484 | pat = GEN_FCN (d->icode) (op0, op1, op2); |
6485 | if (pat != 0) | |
6486 | emit_insn (pat); | |
f18c054f | 6487 | |
3a9b8c7e AH |
6488 | return NULL_RTX; |
6489 | } | |
f18c054f | 6490 | |
3a9b8c7e AH |
6491 | return NULL_RTX; |
6492 | } | |
24408032 | 6493 | |
3a9b8c7e AH |
6494 | /* Expand the builtin in EXP and store the result in TARGET. Store |
6495 | true in *EXPANDEDP if we found a builtin to expand. */ | |
6496 | static rtx | |
a2369ed3 | 6497 | altivec_expand_builtin (tree exp, rtx target, bool *expandedp) |
3a9b8c7e AH |
6498 | { |
6499 | struct builtin_description *d; | |
6500 | struct builtin_description_predicates *dp; | |
6501 | size_t i; | |
6502 | enum insn_code icode; | |
6503 | tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0); | |
6504 | tree arglist = TREE_OPERAND (exp, 1); | |
7c3abc73 AH |
6505 | tree arg0; |
6506 | rtx op0, pat; | |
6507 | enum machine_mode tmode, mode0; | |
3a9b8c7e | 6508 | unsigned int fcode = DECL_FUNCTION_CODE (fndecl); |
0ac081f6 | 6509 | |
3a9b8c7e AH |
6510 | target = altivec_expand_ld_builtin (exp, target, expandedp); |
6511 | if (*expandedp) | |
6512 | return target; | |
0ac081f6 | 6513 | |
3a9b8c7e AH |
6514 | target = altivec_expand_st_builtin (exp, target, expandedp); |
6515 | if (*expandedp) | |
6516 | return target; | |
6517 | ||
6518 | target = altivec_expand_dst_builtin (exp, target, expandedp); | |
6519 | if (*expandedp) | |
6520 | return target; | |
6521 | ||
6522 | *expandedp = true; | |
95385cbb | 6523 | |
3a9b8c7e AH |
6524 | switch (fcode) |
6525 | { | |
6525c0e7 AH |
6526 | case ALTIVEC_BUILTIN_STVX: |
6527 | return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx, arglist); | |
6528 | case ALTIVEC_BUILTIN_STVEBX: | |
6529 | return altivec_expand_stv_builtin (CODE_FOR_altivec_stvebx, arglist); | |
6530 | case ALTIVEC_BUILTIN_STVEHX: | |
6531 | return altivec_expand_stv_builtin (CODE_FOR_altivec_stvehx, arglist); | |
6532 | case ALTIVEC_BUILTIN_STVEWX: | |
6533 | return altivec_expand_stv_builtin (CODE_FOR_altivec_stvewx, arglist); | |
6534 | case ALTIVEC_BUILTIN_STVXL: | |
6535 | return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl, arglist); | |
3a9b8c7e | 6536 | |
95385cbb AH |
6537 | case ALTIVEC_BUILTIN_MFVSCR: |
6538 | icode = CODE_FOR_altivec_mfvscr; | |
6539 | tmode = insn_data[icode].operand[0].mode; | |
6540 | ||
6541 | if (target == 0 | |
6542 | || GET_MODE (target) != tmode | |
6543 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
6544 | target = gen_reg_rtx (tmode); | |
f676971a | 6545 | |
95385cbb | 6546 | pat = GEN_FCN (icode) (target); |
0ac081f6 AH |
6547 | if (! pat) |
6548 | return 0; | |
6549 | emit_insn (pat); | |
95385cbb AH |
6550 | return target; |
6551 | ||
6552 | case ALTIVEC_BUILTIN_MTVSCR: | |
6553 | icode = CODE_FOR_altivec_mtvscr; | |
6554 | arg0 = TREE_VALUE (arglist); | |
6555 | op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
6556 | mode0 = insn_data[icode].operand[0].mode; | |
6557 | ||
6558 | /* If we got invalid arguments bail out before generating bad rtl. */ | |
6559 | if (arg0 == error_mark_node) | |
9a171fcd | 6560 | return const0_rtx; |
95385cbb AH |
6561 | |
6562 | if (! (*insn_data[icode].operand[0].predicate) (op0, mode0)) | |
6563 | op0 = copy_to_mode_reg (mode0, op0); | |
6564 | ||
6565 | pat = GEN_FCN (icode) (op0); | |
6566 | if (pat) | |
6567 | emit_insn (pat); | |
6568 | return NULL_RTX; | |
3a9b8c7e | 6569 | |
95385cbb AH |
6570 | case ALTIVEC_BUILTIN_DSSALL: |
6571 | emit_insn (gen_altivec_dssall ()); | |
6572 | return NULL_RTX; | |
6573 | ||
6574 | case ALTIVEC_BUILTIN_DSS: | |
6575 | icode = CODE_FOR_altivec_dss; | |
6576 | arg0 = TREE_VALUE (arglist); | |
8bb418a3 | 6577 | STRIP_NOPS (arg0); |
95385cbb AH |
6578 | op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); |
6579 | mode0 = insn_data[icode].operand[0].mode; | |
6580 | ||
6581 | /* If we got invalid arguments bail out before generating bad rtl. */ | |
6582 | if (arg0 == error_mark_node) | |
9a171fcd | 6583 | return const0_rtx; |
95385cbb | 6584 | |
b44140e7 AH |
6585 | if (TREE_CODE (arg0) != INTEGER_CST |
6586 | || TREE_INT_CST_LOW (arg0) & ~0x3) | |
6587 | { | |
6588 | error ("argument to dss must be a 2-bit unsigned literal"); | |
9a171fcd | 6589 | return const0_rtx; |
b44140e7 AH |
6590 | } |
6591 | ||
95385cbb AH |
6592 | if (! (*insn_data[icode].operand[0].predicate) (op0, mode0)) |
6593 | op0 = copy_to_mode_reg (mode0, op0); | |
6594 | ||
6595 | emit_insn (gen_altivec_dss (op0)); | |
0ac081f6 | 6596 | return NULL_RTX; |
f676971a | 6597 | |
8bb418a3 ZL |
6598 | case ALTIVEC_BUILTIN_COMPILETIME_ERROR: |
6599 | arg0 = TREE_VALUE (arglist); | |
97dc04b3 | 6600 | while (TREE_CODE (arg0) == NOP_EXPR || TREE_CODE (arg0) == ADDR_EXPR |
c4ad648e | 6601 | || TREE_CODE (arg0) == ARRAY_REF) |
8bb418a3 | 6602 | arg0 = TREE_OPERAND (arg0, 0); |
9e637a26 | 6603 | error ("invalid parameter combination for %qs AltiVec intrinsic", |
8bb418a3 ZL |
6604 | TREE_STRING_POINTER (arg0)); |
6605 | ||
6606 | return const0_rtx; | |
0ac081f6 | 6607 | } |
24408032 | 6608 | |
100c4561 AH |
6609 | /* Expand abs* operations. */ |
6610 | d = (struct builtin_description *) bdesc_abs; | |
ca7558fc | 6611 | for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++) |
100c4561 AH |
6612 | if (d->code == fcode) |
6613 | return altivec_expand_abs_builtin (d->icode, arglist, target); | |
6614 | ||
ae4b4a02 AH |
6615 | /* Expand the AltiVec predicates. */ |
6616 | dp = (struct builtin_description_predicates *) bdesc_altivec_preds; | |
ca7558fc | 6617 | for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, dp++) |
ae4b4a02 | 6618 | if (dp->code == fcode) |
c4ad648e AM |
6619 | return altivec_expand_predicate_builtin (dp->icode, dp->opcode, |
6620 | arglist, target); | |
ae4b4a02 | 6621 | |
6525c0e7 AH |
6622 | /* LV* are funky. We initialized them differently. */ |
6623 | switch (fcode) | |
6624 | { | |
6625 | case ALTIVEC_BUILTIN_LVSL: | |
b4a62fa0 | 6626 | return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsl, |
c4ad648e | 6627 | arglist, target); |
6525c0e7 | 6628 | case ALTIVEC_BUILTIN_LVSR: |
b4a62fa0 | 6629 | return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsr, |
c4ad648e | 6630 | arglist, target); |
6525c0e7 | 6631 | case ALTIVEC_BUILTIN_LVEBX: |
b4a62fa0 | 6632 | return altivec_expand_lv_builtin (CODE_FOR_altivec_lvebx, |
c4ad648e | 6633 | arglist, target); |
6525c0e7 | 6634 | case ALTIVEC_BUILTIN_LVEHX: |
b4a62fa0 | 6635 | return altivec_expand_lv_builtin (CODE_FOR_altivec_lvehx, |
c4ad648e | 6636 | arglist, target); |
6525c0e7 | 6637 | case ALTIVEC_BUILTIN_LVEWX: |
b4a62fa0 | 6638 | return altivec_expand_lv_builtin (CODE_FOR_altivec_lvewx, |
c4ad648e | 6639 | arglist, target); |
6525c0e7 | 6640 | case ALTIVEC_BUILTIN_LVXL: |
b4a62fa0 | 6641 | return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl, |
c4ad648e | 6642 | arglist, target); |
6525c0e7 | 6643 | case ALTIVEC_BUILTIN_LVX: |
b4a62fa0 | 6644 | return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx, |
c4ad648e | 6645 | arglist, target); |
6525c0e7 AH |
6646 | default: |
6647 | break; | |
6648 | /* Fall through. */ | |
6649 | } | |
95385cbb | 6650 | |
92898235 | 6651 | *expandedp = false; |
0ac081f6 AH |
6652 | return NULL_RTX; |
6653 | } | |
6654 | ||
a3170dc6 AH |
6655 | /* Binops that need to be initialized manually, but can be expanded |
6656 | automagically by rs6000_expand_binop_builtin. */ | |
6657 | static struct builtin_description bdesc_2arg_spe[] = | |
6658 | { | |
6659 | { 0, CODE_FOR_spe_evlddx, "__builtin_spe_evlddx", SPE_BUILTIN_EVLDDX }, | |
6660 | { 0, CODE_FOR_spe_evldwx, "__builtin_spe_evldwx", SPE_BUILTIN_EVLDWX }, | |
6661 | { 0, CODE_FOR_spe_evldhx, "__builtin_spe_evldhx", SPE_BUILTIN_EVLDHX }, | |
6662 | { 0, CODE_FOR_spe_evlwhex, "__builtin_spe_evlwhex", SPE_BUILTIN_EVLWHEX }, | |
6663 | { 0, CODE_FOR_spe_evlwhoux, "__builtin_spe_evlwhoux", SPE_BUILTIN_EVLWHOUX }, | |
6664 | { 0, CODE_FOR_spe_evlwhosx, "__builtin_spe_evlwhosx", SPE_BUILTIN_EVLWHOSX }, | |
6665 | { 0, CODE_FOR_spe_evlwwsplatx, "__builtin_spe_evlwwsplatx", SPE_BUILTIN_EVLWWSPLATX }, | |
6666 | { 0, CODE_FOR_spe_evlwhsplatx, "__builtin_spe_evlwhsplatx", SPE_BUILTIN_EVLWHSPLATX }, | |
6667 | { 0, CODE_FOR_spe_evlhhesplatx, "__builtin_spe_evlhhesplatx", SPE_BUILTIN_EVLHHESPLATX }, | |
6668 | { 0, CODE_FOR_spe_evlhhousplatx, "__builtin_spe_evlhhousplatx", SPE_BUILTIN_EVLHHOUSPLATX }, | |
6669 | { 0, CODE_FOR_spe_evlhhossplatx, "__builtin_spe_evlhhossplatx", SPE_BUILTIN_EVLHHOSSPLATX }, | |
6670 | { 0, CODE_FOR_spe_evldd, "__builtin_spe_evldd", SPE_BUILTIN_EVLDD }, | |
6671 | { 0, CODE_FOR_spe_evldw, "__builtin_spe_evldw", SPE_BUILTIN_EVLDW }, | |
6672 | { 0, CODE_FOR_spe_evldh, "__builtin_spe_evldh", SPE_BUILTIN_EVLDH }, | |
6673 | { 0, CODE_FOR_spe_evlwhe, "__builtin_spe_evlwhe", SPE_BUILTIN_EVLWHE }, | |
6674 | { 0, CODE_FOR_spe_evlwhou, "__builtin_spe_evlwhou", SPE_BUILTIN_EVLWHOU }, | |
6675 | { 0, CODE_FOR_spe_evlwhos, "__builtin_spe_evlwhos", SPE_BUILTIN_EVLWHOS }, | |
6676 | { 0, CODE_FOR_spe_evlwwsplat, "__builtin_spe_evlwwsplat", SPE_BUILTIN_EVLWWSPLAT }, | |
6677 | { 0, CODE_FOR_spe_evlwhsplat, "__builtin_spe_evlwhsplat", SPE_BUILTIN_EVLWHSPLAT }, | |
6678 | { 0, CODE_FOR_spe_evlhhesplat, "__builtin_spe_evlhhesplat", SPE_BUILTIN_EVLHHESPLAT }, | |
6679 | { 0, CODE_FOR_spe_evlhhousplat, "__builtin_spe_evlhhousplat", SPE_BUILTIN_EVLHHOUSPLAT }, | |
6680 | { 0, CODE_FOR_spe_evlhhossplat, "__builtin_spe_evlhhossplat", SPE_BUILTIN_EVLHHOSSPLAT } | |
6681 | }; | |
6682 | ||
6683 | /* Expand the builtin in EXP and store the result in TARGET. Store | |
6684 | true in *EXPANDEDP if we found a builtin to expand. | |
6685 | ||
6686 | This expands the SPE builtins that are not simple unary and binary | |
6687 | operations. */ | |
6688 | static rtx | |
a2369ed3 | 6689 | spe_expand_builtin (tree exp, rtx target, bool *expandedp) |
a3170dc6 AH |
6690 | { |
6691 | tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0); | |
6692 | tree arglist = TREE_OPERAND (exp, 1); | |
6693 | tree arg1, arg0; | |
6694 | unsigned int fcode = DECL_FUNCTION_CODE (fndecl); | |
6695 | enum insn_code icode; | |
6696 | enum machine_mode tmode, mode0; | |
6697 | rtx pat, op0; | |
6698 | struct builtin_description *d; | |
6699 | size_t i; | |
6700 | ||
6701 | *expandedp = true; | |
6702 | ||
6703 | /* Syntax check for a 5-bit unsigned immediate. */ | |
6704 | switch (fcode) | |
6705 | { | |
6706 | case SPE_BUILTIN_EVSTDD: | |
6707 | case SPE_BUILTIN_EVSTDH: | |
6708 | case SPE_BUILTIN_EVSTDW: | |
6709 | case SPE_BUILTIN_EVSTWHE: | |
6710 | case SPE_BUILTIN_EVSTWHO: | |
6711 | case SPE_BUILTIN_EVSTWWE: | |
6712 | case SPE_BUILTIN_EVSTWWO: | |
6713 | arg1 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist))); | |
6714 | if (TREE_CODE (arg1) != INTEGER_CST | |
6715 | || TREE_INT_CST_LOW (arg1) & ~0x1f) | |
6716 | { | |
6717 | error ("argument 2 must be a 5-bit unsigned literal"); | |
6718 | return const0_rtx; | |
6719 | } | |
6720 | break; | |
6721 | default: | |
6722 | break; | |
6723 | } | |
6724 | ||
00332c9f AH |
6725 | /* The evsplat*i instructions are not quite generic. */ |
6726 | switch (fcode) | |
6727 | { | |
6728 | case SPE_BUILTIN_EVSPLATFI: | |
6729 | return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplatfi, | |
6730 | arglist, target); | |
6731 | case SPE_BUILTIN_EVSPLATI: | |
6732 | return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplati, | |
6733 | arglist, target); | |
6734 | default: | |
6735 | break; | |
6736 | } | |
6737 | ||
a3170dc6 AH |
6738 | d = (struct builtin_description *) bdesc_2arg_spe; |
6739 | for (i = 0; i < ARRAY_SIZE (bdesc_2arg_spe); ++i, ++d) | |
6740 | if (d->code == fcode) | |
6741 | return rs6000_expand_binop_builtin (d->icode, arglist, target); | |
6742 | ||
6743 | d = (struct builtin_description *) bdesc_spe_predicates; | |
6744 | for (i = 0; i < ARRAY_SIZE (bdesc_spe_predicates); ++i, ++d) | |
6745 | if (d->code == fcode) | |
6746 | return spe_expand_predicate_builtin (d->icode, arglist, target); | |
6747 | ||
6748 | d = (struct builtin_description *) bdesc_spe_evsel; | |
6749 | for (i = 0; i < ARRAY_SIZE (bdesc_spe_evsel); ++i, ++d) | |
6750 | if (d->code == fcode) | |
6751 | return spe_expand_evsel_builtin (d->icode, arglist, target); | |
6752 | ||
6753 | switch (fcode) | |
6754 | { | |
6755 | case SPE_BUILTIN_EVSTDDX: | |
61bea3b0 | 6756 | return spe_expand_stv_builtin (CODE_FOR_spe_evstddx, arglist); |
a3170dc6 | 6757 | case SPE_BUILTIN_EVSTDHX: |
61bea3b0 | 6758 | return spe_expand_stv_builtin (CODE_FOR_spe_evstdhx, arglist); |
a3170dc6 | 6759 | case SPE_BUILTIN_EVSTDWX: |
61bea3b0 | 6760 | return spe_expand_stv_builtin (CODE_FOR_spe_evstdwx, arglist); |
a3170dc6 | 6761 | case SPE_BUILTIN_EVSTWHEX: |
61bea3b0 | 6762 | return spe_expand_stv_builtin (CODE_FOR_spe_evstwhex, arglist); |
a3170dc6 | 6763 | case SPE_BUILTIN_EVSTWHOX: |
61bea3b0 | 6764 | return spe_expand_stv_builtin (CODE_FOR_spe_evstwhox, arglist); |
a3170dc6 | 6765 | case SPE_BUILTIN_EVSTWWEX: |
61bea3b0 | 6766 | return spe_expand_stv_builtin (CODE_FOR_spe_evstwwex, arglist); |
a3170dc6 | 6767 | case SPE_BUILTIN_EVSTWWOX: |
61bea3b0 | 6768 | return spe_expand_stv_builtin (CODE_FOR_spe_evstwwox, arglist); |
a3170dc6 | 6769 | case SPE_BUILTIN_EVSTDD: |
61bea3b0 | 6770 | return spe_expand_stv_builtin (CODE_FOR_spe_evstdd, arglist); |
a3170dc6 | 6771 | case SPE_BUILTIN_EVSTDH: |
61bea3b0 | 6772 | return spe_expand_stv_builtin (CODE_FOR_spe_evstdh, arglist); |
a3170dc6 | 6773 | case SPE_BUILTIN_EVSTDW: |
61bea3b0 | 6774 | return spe_expand_stv_builtin (CODE_FOR_spe_evstdw, arglist); |
a3170dc6 | 6775 | case SPE_BUILTIN_EVSTWHE: |
61bea3b0 | 6776 | return spe_expand_stv_builtin (CODE_FOR_spe_evstwhe, arglist); |
a3170dc6 | 6777 | case SPE_BUILTIN_EVSTWHO: |
61bea3b0 | 6778 | return spe_expand_stv_builtin (CODE_FOR_spe_evstwho, arglist); |
a3170dc6 | 6779 | case SPE_BUILTIN_EVSTWWE: |
61bea3b0 | 6780 | return spe_expand_stv_builtin (CODE_FOR_spe_evstwwe, arglist); |
a3170dc6 | 6781 | case SPE_BUILTIN_EVSTWWO: |
61bea3b0 | 6782 | return spe_expand_stv_builtin (CODE_FOR_spe_evstwwo, arglist); |
a3170dc6 AH |
6783 | case SPE_BUILTIN_MFSPEFSCR: |
6784 | icode = CODE_FOR_spe_mfspefscr; | |
6785 | tmode = insn_data[icode].operand[0].mode; | |
6786 | ||
6787 | if (target == 0 | |
6788 | || GET_MODE (target) != tmode | |
6789 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
6790 | target = gen_reg_rtx (tmode); | |
f676971a | 6791 | |
a3170dc6 AH |
6792 | pat = GEN_FCN (icode) (target); |
6793 | if (! pat) | |
6794 | return 0; | |
6795 | emit_insn (pat); | |
6796 | return target; | |
6797 | case SPE_BUILTIN_MTSPEFSCR: | |
6798 | icode = CODE_FOR_spe_mtspefscr; | |
6799 | arg0 = TREE_VALUE (arglist); | |
6800 | op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
6801 | mode0 = insn_data[icode].operand[0].mode; | |
6802 | ||
6803 | if (arg0 == error_mark_node) | |
6804 | return const0_rtx; | |
6805 | ||
6806 | if (! (*insn_data[icode].operand[0].predicate) (op0, mode0)) | |
6807 | op0 = copy_to_mode_reg (mode0, op0); | |
6808 | ||
6809 | pat = GEN_FCN (icode) (op0); | |
6810 | if (pat) | |
6811 | emit_insn (pat); | |
6812 | return NULL_RTX; | |
6813 | default: | |
6814 | break; | |
6815 | } | |
6816 | ||
6817 | *expandedp = false; | |
6818 | return NULL_RTX; | |
6819 | } | |
6820 | ||
6821 | static rtx | |
a2369ed3 | 6822 | spe_expand_predicate_builtin (enum insn_code icode, tree arglist, rtx target) |
a3170dc6 AH |
6823 | { |
6824 | rtx pat, scratch, tmp; | |
6825 | tree form = TREE_VALUE (arglist); | |
6826 | tree arg0 = TREE_VALUE (TREE_CHAIN (arglist)); | |
6827 | tree arg1 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist))); | |
6828 | rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
6829 | rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); | |
6830 | enum machine_mode mode0 = insn_data[icode].operand[1].mode; | |
6831 | enum machine_mode mode1 = insn_data[icode].operand[2].mode; | |
6832 | int form_int; | |
6833 | enum rtx_code code; | |
6834 | ||
6835 | if (TREE_CODE (form) != INTEGER_CST) | |
6836 | { | |
6837 | error ("argument 1 of __builtin_spe_predicate must be a constant"); | |
6838 | return const0_rtx; | |
6839 | } | |
6840 | else | |
6841 | form_int = TREE_INT_CST_LOW (form); | |
6842 | ||
6843 | if (mode0 != mode1) | |
6844 | abort (); | |
6845 | ||
6846 | if (arg0 == error_mark_node || arg1 == error_mark_node) | |
6847 | return const0_rtx; | |
6848 | ||
6849 | if (target == 0 | |
6850 | || GET_MODE (target) != SImode | |
6851 | || ! (*insn_data[icode].operand[0].predicate) (target, SImode)) | |
6852 | target = gen_reg_rtx (SImode); | |
6853 | ||
6854 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) | |
6855 | op0 = copy_to_mode_reg (mode0, op0); | |
6856 | if (! (*insn_data[icode].operand[2].predicate) (op1, mode1)) | |
6857 | op1 = copy_to_mode_reg (mode1, op1); | |
6858 | ||
6859 | scratch = gen_reg_rtx (CCmode); | |
6860 | ||
6861 | pat = GEN_FCN (icode) (scratch, op0, op1); | |
6862 | if (! pat) | |
6863 | return const0_rtx; | |
6864 | emit_insn (pat); | |
6865 | ||
6866 | /* There are 4 variants for each predicate: _any_, _all_, _upper_, | |
6867 | _lower_. We use one compare, but look in different bits of the | |
6868 | CR for each variant. | |
6869 | ||
6870 | There are 2 elements in each SPE simd type (upper/lower). The CR | |
6871 | bits are set as follows: | |
6872 | ||
6873 | BIT0 | BIT 1 | BIT 2 | BIT 3 | |
6874 | U | L | (U | L) | (U & L) | |
6875 | ||
6876 | So, for an "all" relationship, BIT 3 would be set. | |
6877 | For an "any" relationship, BIT 2 would be set. Etc. | |
6878 | ||
6879 | Following traditional nomenclature, these bits map to: | |
6880 | ||
6881 | BIT0 | BIT 1 | BIT 2 | BIT 3 | |
6882 | LT | GT | EQ | OV | |
6883 | ||
6884 | Later, we will generate rtl to look in the LT/EQ/EQ/OV bits. | |
6885 | */ | |
6886 | ||
6887 | switch (form_int) | |
6888 | { | |
6889 | /* All variant. OV bit. */ | |
6890 | case 0: | |
6891 | /* We need to get to the OV bit, which is the ORDERED bit. We | |
6892 | could generate (ordered:SI (reg:CC xx) (const_int 0)), but | |
6893 | that's ugly and will trigger a validate_condition_mode abort. | |
6894 | So let's just use another pattern. */ | |
6895 | emit_insn (gen_move_from_CR_ov_bit (target, scratch)); | |
6896 | return target; | |
6897 | /* Any variant. EQ bit. */ | |
6898 | case 1: | |
6899 | code = EQ; | |
6900 | break; | |
6901 | /* Upper variant. LT bit. */ | |
6902 | case 2: | |
6903 | code = LT; | |
6904 | break; | |
6905 | /* Lower variant. GT bit. */ | |
6906 | case 3: | |
6907 | code = GT; | |
6908 | break; | |
6909 | default: | |
6910 | error ("argument 1 of __builtin_spe_predicate is out of range"); | |
6911 | return const0_rtx; | |
6912 | } | |
6913 | ||
6914 | tmp = gen_rtx_fmt_ee (code, SImode, scratch, const0_rtx); | |
6915 | emit_move_insn (target, tmp); | |
6916 | ||
6917 | return target; | |
6918 | } | |
6919 | ||
6920 | /* The evsel builtins look like this: | |
6921 | ||
6922 | e = __builtin_spe_evsel_OP (a, b, c, d); | |
6923 | ||
6924 | and work like this: | |
6925 | ||
6926 | e[upper] = a[upper] *OP* b[upper] ? c[upper] : d[upper]; | |
6927 | e[lower] = a[lower] *OP* b[lower] ? c[lower] : d[lower]; | |
6928 | */ | |
6929 | ||
6930 | static rtx | |
a2369ed3 | 6931 | spe_expand_evsel_builtin (enum insn_code icode, tree arglist, rtx target) |
a3170dc6 AH |
6932 | { |
6933 | rtx pat, scratch; | |
6934 | tree arg0 = TREE_VALUE (arglist); | |
6935 | tree arg1 = TREE_VALUE (TREE_CHAIN (arglist)); | |
6936 | tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist))); | |
6937 | tree arg3 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (TREE_CHAIN (arglist)))); | |
6938 | rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
6939 | rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); | |
6940 | rtx op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0); | |
6941 | rtx op3 = expand_expr (arg3, NULL_RTX, VOIDmode, 0); | |
6942 | enum machine_mode mode0 = insn_data[icode].operand[1].mode; | |
6943 | enum machine_mode mode1 = insn_data[icode].operand[2].mode; | |
6944 | ||
6945 | if (mode0 != mode1) | |
6946 | abort (); | |
6947 | ||
6948 | if (arg0 == error_mark_node || arg1 == error_mark_node | |
6949 | || arg2 == error_mark_node || arg3 == error_mark_node) | |
6950 | return const0_rtx; | |
6951 | ||
6952 | if (target == 0 | |
6953 | || GET_MODE (target) != mode0 | |
6954 | || ! (*insn_data[icode].operand[0].predicate) (target, mode0)) | |
6955 | target = gen_reg_rtx (mode0); | |
6956 | ||
6957 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) | |
6958 | op0 = copy_to_mode_reg (mode0, op0); | |
6959 | if (! (*insn_data[icode].operand[1].predicate) (op1, mode1)) | |
6960 | op1 = copy_to_mode_reg (mode0, op1); | |
6961 | if (! (*insn_data[icode].operand[1].predicate) (op2, mode1)) | |
6962 | op2 = copy_to_mode_reg (mode0, op2); | |
6963 | if (! (*insn_data[icode].operand[1].predicate) (op3, mode1)) | |
6964 | op3 = copy_to_mode_reg (mode0, op3); | |
6965 | ||
6966 | /* Generate the compare. */ | |
6967 | scratch = gen_reg_rtx (CCmode); | |
6968 | pat = GEN_FCN (icode) (scratch, op0, op1); | |
6969 | if (! pat) | |
6970 | return const0_rtx; | |
6971 | emit_insn (pat); | |
6972 | ||
6973 | if (mode0 == V2SImode) | |
6974 | emit_insn (gen_spe_evsel (target, op2, op3, scratch)); | |
6975 | else | |
6976 | emit_insn (gen_spe_evsel_fs (target, op2, op3, scratch)); | |
6977 | ||
6978 | return target; | |
6979 | } | |
6980 | ||
0ac081f6 AH |
6981 | /* Expand an expression EXP that calls a built-in function, |
6982 | with result going to TARGET if that's convenient | |
6983 | (and in mode MODE if that's convenient). | |
6984 | SUBTARGET may be used as the target for computing one of EXP's operands. | |
6985 | IGNORE is nonzero if the value is to be ignored. */ | |
6986 | ||
6987 | static rtx | |
a2369ed3 | 6988 | rs6000_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED, |
c4ad648e AM |
6989 | enum machine_mode mode ATTRIBUTE_UNUSED, |
6990 | int ignore ATTRIBUTE_UNUSED) | |
0ac081f6 | 6991 | { |
92898235 AH |
6992 | tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0); |
6993 | tree arglist = TREE_OPERAND (exp, 1); | |
6994 | unsigned int fcode = DECL_FUNCTION_CODE (fndecl); | |
6995 | struct builtin_description *d; | |
6996 | size_t i; | |
6997 | rtx ret; | |
6998 | bool success; | |
f676971a | 6999 | |
7ccf35ed DN |
7000 | if (fcode == ALTIVEC_BUILTIN_MASK_FOR_LOAD |
7001 | || fcode == ALTIVEC_BUILTIN_MASK_FOR_STORE) | |
7002 | { | |
7003 | int icode = (int) CODE_FOR_altivec_lvsr; | |
7004 | enum machine_mode tmode = insn_data[icode].operand[0].mode; | |
7005 | enum machine_mode mode = insn_data[icode].operand[1].mode; | |
7006 | tree arg; | |
7007 | rtx op, addr, pat; | |
7008 | ||
7009 | if (!TARGET_ALTIVEC) | |
7010 | abort (); | |
7011 | ||
7012 | arg = TREE_VALUE (arglist); | |
7013 | if (TREE_CODE (TREE_TYPE (arg)) != POINTER_TYPE) | |
7014 | abort (); | |
7015 | op = expand_expr (arg, NULL_RTX, Pmode, EXPAND_NORMAL); | |
7016 | addr = memory_address (mode, op); | |
7017 | if (fcode == ALTIVEC_BUILTIN_MASK_FOR_STORE) | |
7018 | op = addr; | |
7019 | else | |
7020 | { | |
7021 | /* For the load case need to negate the address. */ | |
7022 | op = gen_reg_rtx (GET_MODE (addr)); | |
7023 | emit_insn (gen_rtx_SET (VOIDmode, op, | |
7024 | gen_rtx_NEG (GET_MODE (addr), addr))); | |
c4ad648e | 7025 | } |
7ccf35ed DN |
7026 | op = gen_rtx_MEM (mode, op); |
7027 | ||
7028 | if (target == 0 | |
7029 | || GET_MODE (target) != tmode | |
7030 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
7031 | target = gen_reg_rtx (tmode); | |
7032 | ||
7033 | /*pat = gen_altivec_lvsr (target, op);*/ | |
7034 | pat = GEN_FCN (icode) (target, op); | |
7035 | if (!pat) | |
7036 | return 0; | |
7037 | emit_insn (pat); | |
7038 | ||
7039 | return target; | |
7040 | } | |
7041 | ||
0ac081f6 | 7042 | if (TARGET_ALTIVEC) |
92898235 AH |
7043 | { |
7044 | ret = altivec_expand_builtin (exp, target, &success); | |
7045 | ||
a3170dc6 AH |
7046 | if (success) |
7047 | return ret; | |
7048 | } | |
7049 | if (TARGET_SPE) | |
7050 | { | |
7051 | ret = spe_expand_builtin (exp, target, &success); | |
7052 | ||
92898235 AH |
7053 | if (success) |
7054 | return ret; | |
7055 | } | |
7056 | ||
0559cc77 DE |
7057 | if (TARGET_ALTIVEC || TARGET_SPE) |
7058 | { | |
7059 | /* Handle simple unary operations. */ | |
7060 | d = (struct builtin_description *) bdesc_1arg; | |
7061 | for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++) | |
7062 | if (d->code == fcode) | |
7063 | return rs6000_expand_unop_builtin (d->icode, arglist, target); | |
7064 | ||
7065 | /* Handle simple binary operations. */ | |
7066 | d = (struct builtin_description *) bdesc_2arg; | |
7067 | for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++) | |
7068 | if (d->code == fcode) | |
7069 | return rs6000_expand_binop_builtin (d->icode, arglist, target); | |
7070 | ||
7071 | /* Handle simple ternary operations. */ | |
7072 | d = (struct builtin_description *) bdesc_3arg; | |
7073 | for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++) | |
7074 | if (d->code == fcode) | |
7075 | return rs6000_expand_ternop_builtin (d->icode, arglist, target); | |
7076 | } | |
0ac081f6 AH |
7077 | |
7078 | abort (); | |
92898235 | 7079 | return NULL_RTX; |
0ac081f6 AH |
7080 | } |
7081 | ||
7c62e993 PB |
7082 | static tree |
7083 | build_opaque_vector_type (tree node, int nunits) | |
7084 | { | |
7085 | node = copy_node (node); | |
7086 | TYPE_MAIN_VARIANT (node) = node; | |
7087 | return build_vector_type (node, nunits); | |
7088 | } | |
7089 | ||
0ac081f6 | 7090 | static void |
863d938c | 7091 | rs6000_init_builtins (void) |
0ac081f6 | 7092 | { |
4a5eab38 PB |
7093 | V2SI_type_node = build_vector_type (intSI_type_node, 2); |
7094 | V2SF_type_node = build_vector_type (float_type_node, 2); | |
7095 | V4HI_type_node = build_vector_type (intHI_type_node, 4); | |
7096 | V4SI_type_node = build_vector_type (intSI_type_node, 4); | |
7097 | V4SF_type_node = build_vector_type (float_type_node, 4); | |
7e463bda | 7098 | V8HI_type_node = build_vector_type (intHI_type_node, 8); |
4a5eab38 PB |
7099 | V16QI_type_node = build_vector_type (intQI_type_node, 16); |
7100 | ||
7101 | unsigned_V16QI_type_node = build_vector_type (unsigned_intQI_type_node, 16); | |
7102 | unsigned_V8HI_type_node = build_vector_type (unsigned_intHI_type_node, 8); | |
7103 | unsigned_V4SI_type_node = build_vector_type (unsigned_intSI_type_node, 4); | |
7104 | ||
7c62e993 PB |
7105 | opaque_V2SF_type_node = build_opaque_vector_type (float_type_node, 2); |
7106 | opaque_V2SI_type_node = build_opaque_vector_type (intSI_type_node, 2); | |
6035d635 | 7107 | opaque_p_V2SI_type_node = build_pointer_type (opaque_V2SI_type_node); |
3fdaa45a | 7108 | |
8bb418a3 ZL |
7109 | /* The 'vector bool ...' types must be kept distinct from 'vector unsigned ...' |
7110 | types, especially in C++ land. Similarly, 'vector pixel' is distinct from | |
7111 | 'vector unsigned short'. */ | |
7112 | ||
8dd16ecc NS |
7113 | bool_char_type_node = build_distinct_type_copy (unsigned_intQI_type_node); |
7114 | bool_short_type_node = build_distinct_type_copy (unsigned_intHI_type_node); | |
7115 | bool_int_type_node = build_distinct_type_copy (unsigned_intSI_type_node); | |
7116 | pixel_type_node = build_distinct_type_copy (unsigned_intHI_type_node); | |
8bb418a3 ZL |
7117 | |
7118 | (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL, | |
7119 | get_identifier ("__bool char"), | |
7120 | bool_char_type_node)); | |
7121 | (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL, | |
7122 | get_identifier ("__bool short"), | |
7123 | bool_short_type_node)); | |
7124 | (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL, | |
7125 | get_identifier ("__bool int"), | |
7126 | bool_int_type_node)); | |
7127 | (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL, | |
7128 | get_identifier ("__pixel"), | |
7129 | pixel_type_node)); | |
7130 | ||
4a5eab38 PB |
7131 | bool_V16QI_type_node = build_vector_type (bool_char_type_node, 16); |
7132 | bool_V8HI_type_node = build_vector_type (bool_short_type_node, 8); | |
7133 | bool_V4SI_type_node = build_vector_type (bool_int_type_node, 4); | |
7134 | pixel_V8HI_type_node = build_vector_type (pixel_type_node, 8); | |
8bb418a3 ZL |
7135 | |
7136 | (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL, | |
7137 | get_identifier ("__vector unsigned char"), | |
7138 | unsigned_V16QI_type_node)); | |
7139 | (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL, | |
7140 | get_identifier ("__vector signed char"), | |
7141 | V16QI_type_node)); | |
7142 | (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL, | |
7143 | get_identifier ("__vector __bool char"), | |
7144 | bool_V16QI_type_node)); | |
7145 | ||
7146 | (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL, | |
7147 | get_identifier ("__vector unsigned short"), | |
7148 | unsigned_V8HI_type_node)); | |
7149 | (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL, | |
7150 | get_identifier ("__vector signed short"), | |
7151 | V8HI_type_node)); | |
7152 | (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL, | |
7153 | get_identifier ("__vector __bool short"), | |
7154 | bool_V8HI_type_node)); | |
7155 | ||
7156 | (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL, | |
7157 | get_identifier ("__vector unsigned int"), | |
7158 | unsigned_V4SI_type_node)); | |
7159 | (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL, | |
7160 | get_identifier ("__vector signed int"), | |
7161 | V4SI_type_node)); | |
7162 | (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL, | |
7163 | get_identifier ("__vector __bool int"), | |
7164 | bool_V4SI_type_node)); | |
7165 | ||
7166 | (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL, | |
7167 | get_identifier ("__vector float"), | |
7168 | V4SF_type_node)); | |
7169 | (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL, | |
7170 | get_identifier ("__vector __pixel"), | |
7171 | pixel_V8HI_type_node)); | |
7172 | ||
a3170dc6 | 7173 | if (TARGET_SPE) |
3fdaa45a | 7174 | spe_init_builtins (); |
0ac081f6 AH |
7175 | if (TARGET_ALTIVEC) |
7176 | altivec_init_builtins (); | |
0559cc77 DE |
7177 | if (TARGET_ALTIVEC || TARGET_SPE) |
7178 | rs6000_common_init_builtins (); | |
0ac081f6 AH |
7179 | } |
7180 | ||
a3170dc6 AH |
7181 | /* Search through a set of builtins and enable the mask bits. |
7182 | DESC is an array of builtins. | |
b6d08ca1 | 7183 | SIZE is the total number of builtins. |
a3170dc6 AH |
7184 | START is the builtin enum at which to start. |
7185 | END is the builtin enum at which to end. */ | |
0ac081f6 | 7186 | static void |
a2369ed3 | 7187 | enable_mask_for_builtins (struct builtin_description *desc, int size, |
f676971a | 7188 | enum rs6000_builtins start, |
a2369ed3 | 7189 | enum rs6000_builtins end) |
a3170dc6 AH |
7190 | { |
7191 | int i; | |
7192 | ||
7193 | for (i = 0; i < size; ++i) | |
7194 | if (desc[i].code == start) | |
7195 | break; | |
7196 | ||
7197 | if (i == size) | |
7198 | return; | |
7199 | ||
7200 | for (; i < size; ++i) | |
7201 | { | |
7202 | /* Flip all the bits on. */ | |
7203 | desc[i].mask = target_flags; | |
7204 | if (desc[i].code == end) | |
7205 | break; | |
7206 | } | |
7207 | } | |
7208 | ||
7209 | static void | |
863d938c | 7210 | spe_init_builtins (void) |
0ac081f6 | 7211 | { |
a3170dc6 AH |
7212 | tree endlink = void_list_node; |
7213 | tree puint_type_node = build_pointer_type (unsigned_type_node); | |
7214 | tree pushort_type_node = build_pointer_type (short_unsigned_type_node); | |
ae4b4a02 | 7215 | struct builtin_description *d; |
0ac081f6 AH |
7216 | size_t i; |
7217 | ||
a3170dc6 AH |
7218 | tree v2si_ftype_4_v2si |
7219 | = build_function_type | |
3fdaa45a AH |
7220 | (opaque_V2SI_type_node, |
7221 | tree_cons (NULL_TREE, opaque_V2SI_type_node, | |
7222 | tree_cons (NULL_TREE, opaque_V2SI_type_node, | |
7223 | tree_cons (NULL_TREE, opaque_V2SI_type_node, | |
7224 | tree_cons (NULL_TREE, opaque_V2SI_type_node, | |
a3170dc6 AH |
7225 | endlink))))); |
7226 | ||
7227 | tree v2sf_ftype_4_v2sf | |
7228 | = build_function_type | |
3fdaa45a AH |
7229 | (opaque_V2SF_type_node, |
7230 | tree_cons (NULL_TREE, opaque_V2SF_type_node, | |
7231 | tree_cons (NULL_TREE, opaque_V2SF_type_node, | |
7232 | tree_cons (NULL_TREE, opaque_V2SF_type_node, | |
7233 | tree_cons (NULL_TREE, opaque_V2SF_type_node, | |
a3170dc6 AH |
7234 | endlink))))); |
7235 | ||
7236 | tree int_ftype_int_v2si_v2si | |
7237 | = build_function_type | |
7238 | (integer_type_node, | |
7239 | tree_cons (NULL_TREE, integer_type_node, | |
3fdaa45a AH |
7240 | tree_cons (NULL_TREE, opaque_V2SI_type_node, |
7241 | tree_cons (NULL_TREE, opaque_V2SI_type_node, | |
a3170dc6 AH |
7242 | endlink)))); |
7243 | ||
7244 | tree int_ftype_int_v2sf_v2sf | |
7245 | = build_function_type | |
7246 | (integer_type_node, | |
7247 | tree_cons (NULL_TREE, integer_type_node, | |
3fdaa45a AH |
7248 | tree_cons (NULL_TREE, opaque_V2SF_type_node, |
7249 | tree_cons (NULL_TREE, opaque_V2SF_type_node, | |
a3170dc6 AH |
7250 | endlink)))); |
7251 | ||
7252 | tree void_ftype_v2si_puint_int | |
7253 | = build_function_type (void_type_node, | |
3fdaa45a | 7254 | tree_cons (NULL_TREE, opaque_V2SI_type_node, |
a3170dc6 AH |
7255 | tree_cons (NULL_TREE, puint_type_node, |
7256 | tree_cons (NULL_TREE, | |
7257 | integer_type_node, | |
7258 | endlink)))); | |
7259 | ||
7260 | tree void_ftype_v2si_puint_char | |
7261 | = build_function_type (void_type_node, | |
3fdaa45a | 7262 | tree_cons (NULL_TREE, opaque_V2SI_type_node, |
a3170dc6 AH |
7263 | tree_cons (NULL_TREE, puint_type_node, |
7264 | tree_cons (NULL_TREE, | |
7265 | char_type_node, | |
7266 | endlink)))); | |
7267 | ||
7268 | tree void_ftype_v2si_pv2si_int | |
7269 | = build_function_type (void_type_node, | |
3fdaa45a | 7270 | tree_cons (NULL_TREE, opaque_V2SI_type_node, |
6035d635 | 7271 | tree_cons (NULL_TREE, opaque_p_V2SI_type_node, |
a3170dc6 AH |
7272 | tree_cons (NULL_TREE, |
7273 | integer_type_node, | |
7274 | endlink)))); | |
7275 | ||
7276 | tree void_ftype_v2si_pv2si_char | |
7277 | = build_function_type (void_type_node, | |
3fdaa45a | 7278 | tree_cons (NULL_TREE, opaque_V2SI_type_node, |
6035d635 | 7279 | tree_cons (NULL_TREE, opaque_p_V2SI_type_node, |
a3170dc6 AH |
7280 | tree_cons (NULL_TREE, |
7281 | char_type_node, | |
7282 | endlink)))); | |
7283 | ||
7284 | tree void_ftype_int | |
7285 | = build_function_type (void_type_node, | |
7286 | tree_cons (NULL_TREE, integer_type_node, endlink)); | |
7287 | ||
7288 | tree int_ftype_void | |
36e8d515 | 7289 | = build_function_type (integer_type_node, endlink); |
a3170dc6 AH |
7290 | |
7291 | tree v2si_ftype_pv2si_int | |
3fdaa45a | 7292 | = build_function_type (opaque_V2SI_type_node, |
6035d635 | 7293 | tree_cons (NULL_TREE, opaque_p_V2SI_type_node, |
a3170dc6 AH |
7294 | tree_cons (NULL_TREE, integer_type_node, |
7295 | endlink))); | |
7296 | ||
7297 | tree v2si_ftype_puint_int | |
3fdaa45a | 7298 | = build_function_type (opaque_V2SI_type_node, |
a3170dc6 AH |
7299 | tree_cons (NULL_TREE, puint_type_node, |
7300 | tree_cons (NULL_TREE, integer_type_node, | |
7301 | endlink))); | |
7302 | ||
7303 | tree v2si_ftype_pushort_int | |
3fdaa45a | 7304 | = build_function_type (opaque_V2SI_type_node, |
a3170dc6 AH |
7305 | tree_cons (NULL_TREE, pushort_type_node, |
7306 | tree_cons (NULL_TREE, integer_type_node, | |
7307 | endlink))); | |
7308 | ||
00332c9f AH |
7309 | tree v2si_ftype_signed_char |
7310 | = build_function_type (opaque_V2SI_type_node, | |
7311 | tree_cons (NULL_TREE, signed_char_type_node, | |
7312 | endlink)); | |
7313 | ||
a3170dc6 AH |
7314 | /* The initialization of the simple binary and unary builtins is |
7315 | done in rs6000_common_init_builtins, but we have to enable the | |
7316 | mask bits here manually because we have run out of `target_flags' | |
7317 | bits. We really need to redesign this mask business. */ | |
7318 | ||
7319 | enable_mask_for_builtins ((struct builtin_description *) bdesc_2arg, | |
7320 | ARRAY_SIZE (bdesc_2arg), | |
7321 | SPE_BUILTIN_EVADDW, | |
7322 | SPE_BUILTIN_EVXOR); | |
7323 | enable_mask_for_builtins ((struct builtin_description *) bdesc_1arg, | |
7324 | ARRAY_SIZE (bdesc_1arg), | |
7325 | SPE_BUILTIN_EVABS, | |
7326 | SPE_BUILTIN_EVSUBFUSIAAW); | |
7327 | enable_mask_for_builtins ((struct builtin_description *) bdesc_spe_predicates, | |
7328 | ARRAY_SIZE (bdesc_spe_predicates), | |
7329 | SPE_BUILTIN_EVCMPEQ, | |
7330 | SPE_BUILTIN_EVFSTSTLT); | |
7331 | enable_mask_for_builtins ((struct builtin_description *) bdesc_spe_evsel, | |
7332 | ARRAY_SIZE (bdesc_spe_evsel), | |
7333 | SPE_BUILTIN_EVSEL_CMPGTS, | |
7334 | SPE_BUILTIN_EVSEL_FSTSTEQ); | |
7335 | ||
36252949 AH |
7336 | (*lang_hooks.decls.pushdecl) |
7337 | (build_decl (TYPE_DECL, get_identifier ("__ev64_opaque__"), | |
7338 | opaque_V2SI_type_node)); | |
7339 | ||
a3170dc6 | 7340 | /* Initialize irregular SPE builtins. */ |
f676971a | 7341 | |
a3170dc6 AH |
7342 | def_builtin (target_flags, "__builtin_spe_mtspefscr", void_ftype_int, SPE_BUILTIN_MTSPEFSCR); |
7343 | def_builtin (target_flags, "__builtin_spe_mfspefscr", int_ftype_void, SPE_BUILTIN_MFSPEFSCR); | |
7344 | def_builtin (target_flags, "__builtin_spe_evstddx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDDX); | |
7345 | def_builtin (target_flags, "__builtin_spe_evstdhx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDHX); | |
7346 | def_builtin (target_flags, "__builtin_spe_evstdwx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDWX); | |
7347 | def_builtin (target_flags, "__builtin_spe_evstwhex", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWHEX); | |
7348 | def_builtin (target_flags, "__builtin_spe_evstwhox", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWHOX); | |
7349 | def_builtin (target_flags, "__builtin_spe_evstwwex", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWWEX); | |
7350 | def_builtin (target_flags, "__builtin_spe_evstwwox", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWWOX); | |
7351 | def_builtin (target_flags, "__builtin_spe_evstdd", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDD); | |
7352 | def_builtin (target_flags, "__builtin_spe_evstdh", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDH); | |
7353 | def_builtin (target_flags, "__builtin_spe_evstdw", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDW); | |
7354 | def_builtin (target_flags, "__builtin_spe_evstwhe", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWHE); | |
7355 | def_builtin (target_flags, "__builtin_spe_evstwho", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWHO); | |
7356 | def_builtin (target_flags, "__builtin_spe_evstwwe", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWWE); | |
7357 | def_builtin (target_flags, "__builtin_spe_evstwwo", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWWO); | |
00332c9f AH |
7358 | def_builtin (target_flags, "__builtin_spe_evsplatfi", v2si_ftype_signed_char, SPE_BUILTIN_EVSPLATFI); |
7359 | def_builtin (target_flags, "__builtin_spe_evsplati", v2si_ftype_signed_char, SPE_BUILTIN_EVSPLATI); | |
a3170dc6 AH |
7360 | |
7361 | /* Loads. */ | |
7362 | def_builtin (target_flags, "__builtin_spe_evlddx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDDX); | |
7363 | def_builtin (target_flags, "__builtin_spe_evldwx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDWX); | |
7364 | def_builtin (target_flags, "__builtin_spe_evldhx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDHX); | |
7365 | def_builtin (target_flags, "__builtin_spe_evlwhex", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHEX); | |
7366 | def_builtin (target_flags, "__builtin_spe_evlwhoux", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOUX); | |
7367 | def_builtin (target_flags, "__builtin_spe_evlwhosx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOSX); | |
7368 | def_builtin (target_flags, "__builtin_spe_evlwwsplatx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWWSPLATX); | |
7369 | def_builtin (target_flags, "__builtin_spe_evlwhsplatx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHSPLATX); | |
7370 | def_builtin (target_flags, "__builtin_spe_evlhhesplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHESPLATX); | |
7371 | def_builtin (target_flags, "__builtin_spe_evlhhousplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOUSPLATX); | |
7372 | def_builtin (target_flags, "__builtin_spe_evlhhossplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOSSPLATX); | |
7373 | def_builtin (target_flags, "__builtin_spe_evldd", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDD); | |
7374 | def_builtin (target_flags, "__builtin_spe_evldw", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDW); | |
7375 | def_builtin (target_flags, "__builtin_spe_evldh", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDH); | |
7376 | def_builtin (target_flags, "__builtin_spe_evlhhesplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHESPLAT); | |
7377 | def_builtin (target_flags, "__builtin_spe_evlhhossplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOSSPLAT); | |
7378 | def_builtin (target_flags, "__builtin_spe_evlhhousplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOUSPLAT); | |
7379 | def_builtin (target_flags, "__builtin_spe_evlwhe", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHE); | |
7380 | def_builtin (target_flags, "__builtin_spe_evlwhos", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOS); | |
7381 | def_builtin (target_flags, "__builtin_spe_evlwhou", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOU); | |
7382 | def_builtin (target_flags, "__builtin_spe_evlwhsplat", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHSPLAT); | |
7383 | def_builtin (target_flags, "__builtin_spe_evlwwsplat", v2si_ftype_puint_int, SPE_BUILTIN_EVLWWSPLAT); | |
7384 | ||
7385 | /* Predicates. */ | |
7386 | d = (struct builtin_description *) bdesc_spe_predicates; | |
7387 | for (i = 0; i < ARRAY_SIZE (bdesc_spe_predicates); ++i, d++) | |
7388 | { | |
7389 | tree type; | |
7390 | ||
7391 | switch (insn_data[d->icode].operand[1].mode) | |
7392 | { | |
7393 | case V2SImode: | |
7394 | type = int_ftype_int_v2si_v2si; | |
7395 | break; | |
7396 | case V2SFmode: | |
7397 | type = int_ftype_int_v2sf_v2sf; | |
7398 | break; | |
7399 | default: | |
7400 | abort (); | |
7401 | } | |
7402 | ||
7403 | def_builtin (d->mask, d->name, type, d->code); | |
7404 | } | |
7405 | ||
7406 | /* Evsel predicates. */ | |
7407 | d = (struct builtin_description *) bdesc_spe_evsel; | |
7408 | for (i = 0; i < ARRAY_SIZE (bdesc_spe_evsel); ++i, d++) | |
7409 | { | |
7410 | tree type; | |
7411 | ||
7412 | switch (insn_data[d->icode].operand[1].mode) | |
7413 | { | |
7414 | case V2SImode: | |
7415 | type = v2si_ftype_4_v2si; | |
7416 | break; | |
7417 | case V2SFmode: | |
7418 | type = v2sf_ftype_4_v2sf; | |
7419 | break; | |
7420 | default: | |
7421 | abort (); | |
7422 | } | |
7423 | ||
7424 | def_builtin (d->mask, d->name, type, d->code); | |
7425 | } | |
7426 | } | |
7427 | ||
7428 | static void | |
863d938c | 7429 | altivec_init_builtins (void) |
a3170dc6 AH |
7430 | { |
7431 | struct builtin_description *d; | |
7432 | struct builtin_description_predicates *dp; | |
7433 | size_t i; | |
7434 | tree pfloat_type_node = build_pointer_type (float_type_node); | |
7435 | tree pint_type_node = build_pointer_type (integer_type_node); | |
7436 | tree pshort_type_node = build_pointer_type (short_integer_type_node); | |
7437 | tree pchar_type_node = build_pointer_type (char_type_node); | |
7438 | ||
7439 | tree pvoid_type_node = build_pointer_type (void_type_node); | |
7440 | ||
0dbc3651 ZW |
7441 | tree pcfloat_type_node = build_pointer_type (build_qualified_type (float_type_node, TYPE_QUAL_CONST)); |
7442 | tree pcint_type_node = build_pointer_type (build_qualified_type (integer_type_node, TYPE_QUAL_CONST)); | |
7443 | tree pcshort_type_node = build_pointer_type (build_qualified_type (short_integer_type_node, TYPE_QUAL_CONST)); | |
7444 | tree pcchar_type_node = build_pointer_type (build_qualified_type (char_type_node, TYPE_QUAL_CONST)); | |
7445 | ||
7446 | tree pcvoid_type_node = build_pointer_type (build_qualified_type (void_type_node, TYPE_QUAL_CONST)); | |
7447 | ||
a3170dc6 AH |
7448 | tree int_ftype_int_v4si_v4si |
7449 | = build_function_type_list (integer_type_node, | |
7450 | integer_type_node, V4SI_type_node, | |
7451 | V4SI_type_node, NULL_TREE); | |
0dbc3651 ZW |
7452 | tree v4sf_ftype_pcfloat |
7453 | = build_function_type_list (V4SF_type_node, pcfloat_type_node, NULL_TREE); | |
a3170dc6 | 7454 | tree void_ftype_pfloat_v4sf |
b4de2f7d | 7455 | = build_function_type_list (void_type_node, |
a3170dc6 | 7456 | pfloat_type_node, V4SF_type_node, NULL_TREE); |
0dbc3651 ZW |
7457 | tree v4si_ftype_pcint |
7458 | = build_function_type_list (V4SI_type_node, pcint_type_node, NULL_TREE); | |
7459 | tree void_ftype_pint_v4si | |
b4de2f7d AH |
7460 | = build_function_type_list (void_type_node, |
7461 | pint_type_node, V4SI_type_node, NULL_TREE); | |
0dbc3651 ZW |
7462 | tree v8hi_ftype_pcshort |
7463 | = build_function_type_list (V8HI_type_node, pcshort_type_node, NULL_TREE); | |
f18c054f | 7464 | tree void_ftype_pshort_v8hi |
b4de2f7d AH |
7465 | = build_function_type_list (void_type_node, |
7466 | pshort_type_node, V8HI_type_node, NULL_TREE); | |
0dbc3651 ZW |
7467 | tree v16qi_ftype_pcchar |
7468 | = build_function_type_list (V16QI_type_node, pcchar_type_node, NULL_TREE); | |
f18c054f | 7469 | tree void_ftype_pchar_v16qi |
b4de2f7d AH |
7470 | = build_function_type_list (void_type_node, |
7471 | pchar_type_node, V16QI_type_node, NULL_TREE); | |
95385cbb | 7472 | tree void_ftype_v4si |
b4de2f7d | 7473 | = build_function_type_list (void_type_node, V4SI_type_node, NULL_TREE); |
a3170dc6 AH |
7474 | tree v8hi_ftype_void |
7475 | = build_function_type (V8HI_type_node, void_list_node); | |
7476 | tree void_ftype_void | |
7477 | = build_function_type (void_type_node, void_list_node); | |
e34b6648 JJ |
7478 | tree void_ftype_int |
7479 | = build_function_type_list (void_type_node, integer_type_node, NULL_TREE); | |
0dbc3651 | 7480 | |
b4a62fa0 | 7481 | tree v16qi_ftype_long_pcvoid |
a3170dc6 | 7482 | = build_function_type_list (V16QI_type_node, |
b4a62fa0 SB |
7483 | long_integer_type_node, pcvoid_type_node, NULL_TREE); |
7484 | tree v8hi_ftype_long_pcvoid | |
a3170dc6 | 7485 | = build_function_type_list (V8HI_type_node, |
b4a62fa0 SB |
7486 | long_integer_type_node, pcvoid_type_node, NULL_TREE); |
7487 | tree v4si_ftype_long_pcvoid | |
a3170dc6 | 7488 | = build_function_type_list (V4SI_type_node, |
b4a62fa0 | 7489 | long_integer_type_node, pcvoid_type_node, NULL_TREE); |
0dbc3651 | 7490 | |
b4a62fa0 | 7491 | tree void_ftype_v4si_long_pvoid |
b4de2f7d | 7492 | = build_function_type_list (void_type_node, |
b4a62fa0 | 7493 | V4SI_type_node, long_integer_type_node, |
b4de2f7d | 7494 | pvoid_type_node, NULL_TREE); |
b4a62fa0 | 7495 | tree void_ftype_v16qi_long_pvoid |
b4de2f7d | 7496 | = build_function_type_list (void_type_node, |
b4a62fa0 | 7497 | V16QI_type_node, long_integer_type_node, |
b4de2f7d | 7498 | pvoid_type_node, NULL_TREE); |
b4a62fa0 | 7499 | tree void_ftype_v8hi_long_pvoid |
b4de2f7d | 7500 | = build_function_type_list (void_type_node, |
b4a62fa0 | 7501 | V8HI_type_node, long_integer_type_node, |
b4de2f7d | 7502 | pvoid_type_node, NULL_TREE); |
a3170dc6 AH |
7503 | tree int_ftype_int_v8hi_v8hi |
7504 | = build_function_type_list (integer_type_node, | |
7505 | integer_type_node, V8HI_type_node, | |
7506 | V8HI_type_node, NULL_TREE); | |
7507 | tree int_ftype_int_v16qi_v16qi | |
7508 | = build_function_type_list (integer_type_node, | |
7509 | integer_type_node, V16QI_type_node, | |
7510 | V16QI_type_node, NULL_TREE); | |
7511 | tree int_ftype_int_v4sf_v4sf | |
7512 | = build_function_type_list (integer_type_node, | |
7513 | integer_type_node, V4SF_type_node, | |
7514 | V4SF_type_node, NULL_TREE); | |
7515 | tree v4si_ftype_v4si | |
7516 | = build_function_type_list (V4SI_type_node, V4SI_type_node, NULL_TREE); | |
7517 | tree v8hi_ftype_v8hi | |
7518 | = build_function_type_list (V8HI_type_node, V8HI_type_node, NULL_TREE); | |
7519 | tree v16qi_ftype_v16qi | |
7520 | = build_function_type_list (V16QI_type_node, V16QI_type_node, NULL_TREE); | |
7521 | tree v4sf_ftype_v4sf | |
7522 | = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE); | |
8bb418a3 | 7523 | tree void_ftype_pcvoid_int_int |
a3170dc6 | 7524 | = build_function_type_list (void_type_node, |
0dbc3651 | 7525 | pcvoid_type_node, integer_type_node, |
8bb418a3 ZL |
7526 | integer_type_node, NULL_TREE); |
7527 | tree int_ftype_pcchar | |
7528 | = build_function_type_list (integer_type_node, | |
7529 | pcchar_type_node, NULL_TREE); | |
7530 | ||
0dbc3651 ZW |
7531 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_4sf", v4sf_ftype_pcfloat, |
7532 | ALTIVEC_BUILTIN_LD_INTERNAL_4sf); | |
7533 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_4sf", void_ftype_pfloat_v4sf, | |
7534 | ALTIVEC_BUILTIN_ST_INTERNAL_4sf); | |
7535 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_4si", v4si_ftype_pcint, | |
7536 | ALTIVEC_BUILTIN_LD_INTERNAL_4si); | |
7537 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_4si", void_ftype_pint_v4si, | |
7538 | ALTIVEC_BUILTIN_ST_INTERNAL_4si); | |
7539 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_8hi", v8hi_ftype_pcshort, | |
7540 | ALTIVEC_BUILTIN_LD_INTERNAL_8hi); | |
7541 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_8hi", void_ftype_pshort_v8hi, | |
7542 | ALTIVEC_BUILTIN_ST_INTERNAL_8hi); | |
7543 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_16qi", v16qi_ftype_pcchar, | |
7544 | ALTIVEC_BUILTIN_LD_INTERNAL_16qi); | |
7545 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_16qi", void_ftype_pchar_v16qi, | |
7546 | ALTIVEC_BUILTIN_ST_INTERNAL_16qi); | |
a3170dc6 AH |
7547 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_mtvscr", void_ftype_v4si, ALTIVEC_BUILTIN_MTVSCR); |
7548 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_mfvscr", v8hi_ftype_void, ALTIVEC_BUILTIN_MFVSCR); | |
7549 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_dssall", void_ftype_void, ALTIVEC_BUILTIN_DSSALL); | |
e34b6648 | 7550 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_dss", void_ftype_int, ALTIVEC_BUILTIN_DSS); |
b4a62fa0 SB |
7551 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvsl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSL); |
7552 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvsr", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSR); | |
7553 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvebx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEBX); | |
7554 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvehx", v8hi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEHX); | |
7555 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvewx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEWX); | |
7556 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvxl", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVXL); | |
7557 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVX); | |
7558 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVX); | |
7559 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvewx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVEWX); | |
7560 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvxl", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVXL); | |
7561 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvebx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVEBX); | |
7562 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvehx", void_ftype_v8hi_long_pvoid, ALTIVEC_BUILTIN_STVEHX); | |
a3170dc6 | 7563 | |
8bb418a3 ZL |
7564 | /* See altivec.h for usage of "__builtin_altivec_compiletime_error". */ |
7565 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_compiletime_error", int_ftype_pcchar, | |
7566 | ALTIVEC_BUILTIN_COMPILETIME_ERROR); | |
7567 | ||
a3170dc6 AH |
7568 | /* Add the DST variants. */ |
7569 | d = (struct builtin_description *) bdesc_dst; | |
7570 | for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++) | |
8bb418a3 | 7571 | def_builtin (d->mask, d->name, void_ftype_pcvoid_int_int, d->code); |
a3170dc6 AH |
7572 | |
7573 | /* Initialize the predicates. */ | |
7574 | dp = (struct builtin_description_predicates *) bdesc_altivec_preds; | |
7575 | for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, dp++) | |
7576 | { | |
7577 | enum machine_mode mode1; | |
7578 | tree type; | |
7579 | ||
7580 | mode1 = insn_data[dp->icode].operand[1].mode; | |
7581 | ||
7582 | switch (mode1) | |
7583 | { | |
7584 | case V4SImode: | |
7585 | type = int_ftype_int_v4si_v4si; | |
7586 | break; | |
7587 | case V8HImode: | |
7588 | type = int_ftype_int_v8hi_v8hi; | |
7589 | break; | |
7590 | case V16QImode: | |
7591 | type = int_ftype_int_v16qi_v16qi; | |
7592 | break; | |
7593 | case V4SFmode: | |
7594 | type = int_ftype_int_v4sf_v4sf; | |
7595 | break; | |
7596 | default: | |
7597 | abort (); | |
7598 | } | |
f676971a | 7599 | |
a3170dc6 AH |
7600 | def_builtin (dp->mask, dp->name, type, dp->code); |
7601 | } | |
7602 | ||
7603 | /* Initialize the abs* operators. */ | |
7604 | d = (struct builtin_description *) bdesc_abs; | |
7605 | for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++) | |
7606 | { | |
7607 | enum machine_mode mode0; | |
7608 | tree type; | |
7609 | ||
7610 | mode0 = insn_data[d->icode].operand[0].mode; | |
7611 | ||
7612 | switch (mode0) | |
7613 | { | |
7614 | case V4SImode: | |
7615 | type = v4si_ftype_v4si; | |
7616 | break; | |
7617 | case V8HImode: | |
7618 | type = v8hi_ftype_v8hi; | |
7619 | break; | |
7620 | case V16QImode: | |
7621 | type = v16qi_ftype_v16qi; | |
7622 | break; | |
7623 | case V4SFmode: | |
7624 | type = v4sf_ftype_v4sf; | |
7625 | break; | |
7626 | default: | |
7627 | abort (); | |
7628 | } | |
f676971a | 7629 | |
a3170dc6 AH |
7630 | def_builtin (d->mask, d->name, type, d->code); |
7631 | } | |
7ccf35ed | 7632 | |
13c62176 DN |
7633 | if (TARGET_ALTIVEC) |
7634 | { | |
7635 | tree decl; | |
7636 | ||
7637 | /* Initialize target builtin that implements | |
7638 | targetm.vectorize.builtin_mask_for_load. */ | |
7639 | ||
7640 | decl = lang_hooks.builtin_function ("__builtin_altivec_mask_for_load", | |
7641 | v16qi_ftype_long_pcvoid, | |
7642 | ALTIVEC_BUILTIN_MASK_FOR_LOAD, | |
7643 | BUILT_IN_MD, NULL, NULL_TREE); | |
7644 | /* Record the decl. Will be used by rs6000_builtin_mask_for_load. */ | |
7645 | altivec_builtin_mask_for_load = decl; | |
13c62176 | 7646 | } |
a3170dc6 AH |
7647 | } |
7648 | ||
7649 | static void | |
863d938c | 7650 | rs6000_common_init_builtins (void) |
a3170dc6 AH |
7651 | { |
7652 | struct builtin_description *d; | |
7653 | size_t i; | |
7654 | ||
7655 | tree v4sf_ftype_v4sf_v4sf_v16qi | |
7656 | = build_function_type_list (V4SF_type_node, | |
7657 | V4SF_type_node, V4SF_type_node, | |
7658 | V16QI_type_node, NULL_TREE); | |
7659 | tree v4si_ftype_v4si_v4si_v16qi | |
7660 | = build_function_type_list (V4SI_type_node, | |
7661 | V4SI_type_node, V4SI_type_node, | |
7662 | V16QI_type_node, NULL_TREE); | |
7663 | tree v8hi_ftype_v8hi_v8hi_v16qi | |
7664 | = build_function_type_list (V8HI_type_node, | |
7665 | V8HI_type_node, V8HI_type_node, | |
7666 | V16QI_type_node, NULL_TREE); | |
7667 | tree v16qi_ftype_v16qi_v16qi_v16qi | |
7668 | = build_function_type_list (V16QI_type_node, | |
7669 | V16QI_type_node, V16QI_type_node, | |
7670 | V16QI_type_node, NULL_TREE); | |
b9e4e5d1 ZL |
7671 | tree v4si_ftype_int |
7672 | = build_function_type_list (V4SI_type_node, integer_type_node, NULL_TREE); | |
7673 | tree v8hi_ftype_int | |
7674 | = build_function_type_list (V8HI_type_node, integer_type_node, NULL_TREE); | |
7675 | tree v16qi_ftype_int | |
7676 | = build_function_type_list (V16QI_type_node, integer_type_node, NULL_TREE); | |
a3170dc6 AH |
7677 | tree v8hi_ftype_v16qi |
7678 | = build_function_type_list (V8HI_type_node, V16QI_type_node, NULL_TREE); | |
7679 | tree v4sf_ftype_v4sf | |
7680 | = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE); | |
7681 | ||
7682 | tree v2si_ftype_v2si_v2si | |
2abe3e28 AH |
7683 | = build_function_type_list (opaque_V2SI_type_node, |
7684 | opaque_V2SI_type_node, | |
7685 | opaque_V2SI_type_node, NULL_TREE); | |
a3170dc6 AH |
7686 | |
7687 | tree v2sf_ftype_v2sf_v2sf | |
2abe3e28 AH |
7688 | = build_function_type_list (opaque_V2SF_type_node, |
7689 | opaque_V2SF_type_node, | |
7690 | opaque_V2SF_type_node, NULL_TREE); | |
a3170dc6 AH |
7691 | |
7692 | tree v2si_ftype_int_int | |
2abe3e28 | 7693 | = build_function_type_list (opaque_V2SI_type_node, |
a3170dc6 AH |
7694 | integer_type_node, integer_type_node, |
7695 | NULL_TREE); | |
7696 | ||
7697 | tree v2si_ftype_v2si | |
2abe3e28 AH |
7698 | = build_function_type_list (opaque_V2SI_type_node, |
7699 | opaque_V2SI_type_node, NULL_TREE); | |
a3170dc6 AH |
7700 | |
7701 | tree v2sf_ftype_v2sf | |
2abe3e28 AH |
7702 | = build_function_type_list (opaque_V2SF_type_node, |
7703 | opaque_V2SF_type_node, NULL_TREE); | |
f676971a | 7704 | |
a3170dc6 | 7705 | tree v2sf_ftype_v2si |
2abe3e28 AH |
7706 | = build_function_type_list (opaque_V2SF_type_node, |
7707 | opaque_V2SI_type_node, NULL_TREE); | |
a3170dc6 AH |
7708 | |
7709 | tree v2si_ftype_v2sf | |
2abe3e28 AH |
7710 | = build_function_type_list (opaque_V2SI_type_node, |
7711 | opaque_V2SF_type_node, NULL_TREE); | |
a3170dc6 AH |
7712 | |
7713 | tree v2si_ftype_v2si_char | |
2abe3e28 AH |
7714 | = build_function_type_list (opaque_V2SI_type_node, |
7715 | opaque_V2SI_type_node, | |
7716 | char_type_node, NULL_TREE); | |
a3170dc6 AH |
7717 | |
7718 | tree v2si_ftype_int_char | |
2abe3e28 | 7719 | = build_function_type_list (opaque_V2SI_type_node, |
a3170dc6 AH |
7720 | integer_type_node, char_type_node, NULL_TREE); |
7721 | ||
7722 | tree v2si_ftype_char | |
2abe3e28 AH |
7723 | = build_function_type_list (opaque_V2SI_type_node, |
7724 | char_type_node, NULL_TREE); | |
a3170dc6 AH |
7725 | |
7726 | tree int_ftype_int_int | |
7727 | = build_function_type_list (integer_type_node, | |
7728 | integer_type_node, integer_type_node, | |
7729 | NULL_TREE); | |
95385cbb | 7730 | |
0ac081f6 | 7731 | tree v4si_ftype_v4si_v4si |
b4de2f7d AH |
7732 | = build_function_type_list (V4SI_type_node, |
7733 | V4SI_type_node, V4SI_type_node, NULL_TREE); | |
b9e4e5d1 | 7734 | tree v4sf_ftype_v4si_int |
b4de2f7d | 7735 | = build_function_type_list (V4SF_type_node, |
b9e4e5d1 ZL |
7736 | V4SI_type_node, integer_type_node, NULL_TREE); |
7737 | tree v4si_ftype_v4sf_int | |
b4de2f7d | 7738 | = build_function_type_list (V4SI_type_node, |
b9e4e5d1 ZL |
7739 | V4SF_type_node, integer_type_node, NULL_TREE); |
7740 | tree v4si_ftype_v4si_int | |
b4de2f7d | 7741 | = build_function_type_list (V4SI_type_node, |
b9e4e5d1 ZL |
7742 | V4SI_type_node, integer_type_node, NULL_TREE); |
7743 | tree v8hi_ftype_v8hi_int | |
b4de2f7d | 7744 | = build_function_type_list (V8HI_type_node, |
b9e4e5d1 ZL |
7745 | V8HI_type_node, integer_type_node, NULL_TREE); |
7746 | tree v16qi_ftype_v16qi_int | |
b4de2f7d | 7747 | = build_function_type_list (V16QI_type_node, |
b9e4e5d1 ZL |
7748 | V16QI_type_node, integer_type_node, NULL_TREE); |
7749 | tree v16qi_ftype_v16qi_v16qi_int | |
b4de2f7d AH |
7750 | = build_function_type_list (V16QI_type_node, |
7751 | V16QI_type_node, V16QI_type_node, | |
b9e4e5d1 ZL |
7752 | integer_type_node, NULL_TREE); |
7753 | tree v8hi_ftype_v8hi_v8hi_int | |
b4de2f7d AH |
7754 | = build_function_type_list (V8HI_type_node, |
7755 | V8HI_type_node, V8HI_type_node, | |
b9e4e5d1 ZL |
7756 | integer_type_node, NULL_TREE); |
7757 | tree v4si_ftype_v4si_v4si_int | |
b4de2f7d AH |
7758 | = build_function_type_list (V4SI_type_node, |
7759 | V4SI_type_node, V4SI_type_node, | |
b9e4e5d1 ZL |
7760 | integer_type_node, NULL_TREE); |
7761 | tree v4sf_ftype_v4sf_v4sf_int | |
b4de2f7d AH |
7762 | = build_function_type_list (V4SF_type_node, |
7763 | V4SF_type_node, V4SF_type_node, | |
b9e4e5d1 | 7764 | integer_type_node, NULL_TREE); |
0ac081f6 | 7765 | tree v4sf_ftype_v4sf_v4sf |
b4de2f7d AH |
7766 | = build_function_type_list (V4SF_type_node, |
7767 | V4SF_type_node, V4SF_type_node, NULL_TREE); | |
617e0e1d | 7768 | tree v4sf_ftype_v4sf_v4sf_v4si |
b4de2f7d AH |
7769 | = build_function_type_list (V4SF_type_node, |
7770 | V4SF_type_node, V4SF_type_node, | |
7771 | V4SI_type_node, NULL_TREE); | |
2212663f | 7772 | tree v4sf_ftype_v4sf_v4sf_v4sf |
b4de2f7d AH |
7773 | = build_function_type_list (V4SF_type_node, |
7774 | V4SF_type_node, V4SF_type_node, | |
7775 | V4SF_type_node, NULL_TREE); | |
f676971a | 7776 | tree v4si_ftype_v4si_v4si_v4si |
b4de2f7d AH |
7777 | = build_function_type_list (V4SI_type_node, |
7778 | V4SI_type_node, V4SI_type_node, | |
7779 | V4SI_type_node, NULL_TREE); | |
0ac081f6 | 7780 | tree v8hi_ftype_v8hi_v8hi |
b4de2f7d AH |
7781 | = build_function_type_list (V8HI_type_node, |
7782 | V8HI_type_node, V8HI_type_node, NULL_TREE); | |
2212663f | 7783 | tree v8hi_ftype_v8hi_v8hi_v8hi |
b4de2f7d AH |
7784 | = build_function_type_list (V8HI_type_node, |
7785 | V8HI_type_node, V8HI_type_node, | |
7786 | V8HI_type_node, NULL_TREE); | |
c4ad648e | 7787 | tree v4si_ftype_v8hi_v8hi_v4si |
b4de2f7d AH |
7788 | = build_function_type_list (V4SI_type_node, |
7789 | V8HI_type_node, V8HI_type_node, | |
7790 | V4SI_type_node, NULL_TREE); | |
c4ad648e | 7791 | tree v4si_ftype_v16qi_v16qi_v4si |
b4de2f7d AH |
7792 | = build_function_type_list (V4SI_type_node, |
7793 | V16QI_type_node, V16QI_type_node, | |
7794 | V4SI_type_node, NULL_TREE); | |
0ac081f6 | 7795 | tree v16qi_ftype_v16qi_v16qi |
b4de2f7d AH |
7796 | = build_function_type_list (V16QI_type_node, |
7797 | V16QI_type_node, V16QI_type_node, NULL_TREE); | |
0ac081f6 | 7798 | tree v4si_ftype_v4sf_v4sf |
b4de2f7d AH |
7799 | = build_function_type_list (V4SI_type_node, |
7800 | V4SF_type_node, V4SF_type_node, NULL_TREE); | |
0ac081f6 | 7801 | tree v8hi_ftype_v16qi_v16qi |
b4de2f7d AH |
7802 | = build_function_type_list (V8HI_type_node, |
7803 | V16QI_type_node, V16QI_type_node, NULL_TREE); | |
0ac081f6 | 7804 | tree v4si_ftype_v8hi_v8hi |
b4de2f7d AH |
7805 | = build_function_type_list (V4SI_type_node, |
7806 | V8HI_type_node, V8HI_type_node, NULL_TREE); | |
0ac081f6 | 7807 | tree v8hi_ftype_v4si_v4si |
b4de2f7d AH |
7808 | = build_function_type_list (V8HI_type_node, |
7809 | V4SI_type_node, V4SI_type_node, NULL_TREE); | |
0ac081f6 | 7810 | tree v16qi_ftype_v8hi_v8hi |
b4de2f7d AH |
7811 | = build_function_type_list (V16QI_type_node, |
7812 | V8HI_type_node, V8HI_type_node, NULL_TREE); | |
0ac081f6 | 7813 | tree v4si_ftype_v16qi_v4si |
b4de2f7d AH |
7814 | = build_function_type_list (V4SI_type_node, |
7815 | V16QI_type_node, V4SI_type_node, NULL_TREE); | |
fa066a23 | 7816 | tree v4si_ftype_v16qi_v16qi |
b4de2f7d AH |
7817 | = build_function_type_list (V4SI_type_node, |
7818 | V16QI_type_node, V16QI_type_node, NULL_TREE); | |
0ac081f6 | 7819 | tree v4si_ftype_v8hi_v4si |
b4de2f7d AH |
7820 | = build_function_type_list (V4SI_type_node, |
7821 | V8HI_type_node, V4SI_type_node, NULL_TREE); | |
a3170dc6 AH |
7822 | tree v4si_ftype_v8hi |
7823 | = build_function_type_list (V4SI_type_node, V8HI_type_node, NULL_TREE); | |
7824 | tree int_ftype_v4si_v4si | |
7825 | = build_function_type_list (integer_type_node, | |
7826 | V4SI_type_node, V4SI_type_node, NULL_TREE); | |
7827 | tree int_ftype_v4sf_v4sf | |
7828 | = build_function_type_list (integer_type_node, | |
7829 | V4SF_type_node, V4SF_type_node, NULL_TREE); | |
7830 | tree int_ftype_v16qi_v16qi | |
7831 | = build_function_type_list (integer_type_node, | |
7832 | V16QI_type_node, V16QI_type_node, NULL_TREE); | |
0ac081f6 | 7833 | tree int_ftype_v8hi_v8hi |
b4de2f7d AH |
7834 | = build_function_type_list (integer_type_node, |
7835 | V8HI_type_node, V8HI_type_node, NULL_TREE); | |
0ac081f6 | 7836 | |
6f317ef3 | 7837 | /* Add the simple ternary operators. */ |
2212663f | 7838 | d = (struct builtin_description *) bdesc_3arg; |
ca7558fc | 7839 | for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++) |
2212663f | 7840 | { |
f676971a | 7841 | |
2212663f DB |
7842 | enum machine_mode mode0, mode1, mode2, mode3; |
7843 | tree type; | |
7844 | ||
0559cc77 | 7845 | if (d->name == 0 || d->icode == CODE_FOR_nothing) |
2212663f | 7846 | continue; |
f676971a | 7847 | |
2212663f DB |
7848 | mode0 = insn_data[d->icode].operand[0].mode; |
7849 | mode1 = insn_data[d->icode].operand[1].mode; | |
7850 | mode2 = insn_data[d->icode].operand[2].mode; | |
7851 | mode3 = insn_data[d->icode].operand[3].mode; | |
f676971a | 7852 | |
2212663f DB |
7853 | /* When all four are of the same mode. */ |
7854 | if (mode0 == mode1 && mode1 == mode2 && mode2 == mode3) | |
7855 | { | |
7856 | switch (mode0) | |
7857 | { | |
617e0e1d DB |
7858 | case V4SImode: |
7859 | type = v4si_ftype_v4si_v4si_v4si; | |
7860 | break; | |
2212663f DB |
7861 | case V4SFmode: |
7862 | type = v4sf_ftype_v4sf_v4sf_v4sf; | |
7863 | break; | |
7864 | case V8HImode: | |
7865 | type = v8hi_ftype_v8hi_v8hi_v8hi; | |
f676971a | 7866 | break; |
2212663f DB |
7867 | case V16QImode: |
7868 | type = v16qi_ftype_v16qi_v16qi_v16qi; | |
f676971a | 7869 | break; |
2212663f | 7870 | default: |
f676971a | 7871 | abort(); |
2212663f DB |
7872 | } |
7873 | } | |
7874 | else if (mode0 == mode1 && mode1 == mode2 && mode3 == V16QImode) | |
c4ad648e | 7875 | { |
2212663f DB |
7876 | switch (mode0) |
7877 | { | |
7878 | case V4SImode: | |
7879 | type = v4si_ftype_v4si_v4si_v16qi; | |
7880 | break; | |
7881 | case V4SFmode: | |
7882 | type = v4sf_ftype_v4sf_v4sf_v16qi; | |
7883 | break; | |
7884 | case V8HImode: | |
7885 | type = v8hi_ftype_v8hi_v8hi_v16qi; | |
f676971a | 7886 | break; |
2212663f DB |
7887 | case V16QImode: |
7888 | type = v16qi_ftype_v16qi_v16qi_v16qi; | |
f676971a | 7889 | break; |
2212663f | 7890 | default: |
f676971a | 7891 | abort(); |
2212663f DB |
7892 | } |
7893 | } | |
f676971a | 7894 | else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V16QImode |
2212663f | 7895 | && mode3 == V4SImode) |
24408032 | 7896 | type = v4si_ftype_v16qi_v16qi_v4si; |
f676971a | 7897 | else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V8HImode |
2212663f | 7898 | && mode3 == V4SImode) |
24408032 | 7899 | type = v4si_ftype_v8hi_v8hi_v4si; |
f676971a | 7900 | else if (mode0 == V4SFmode && mode1 == V4SFmode && mode2 == V4SFmode |
617e0e1d | 7901 | && mode3 == V4SImode) |
24408032 AH |
7902 | type = v4sf_ftype_v4sf_v4sf_v4si; |
7903 | ||
7904 | /* vchar, vchar, vchar, 4 bit literal. */ | |
7905 | else if (mode0 == V16QImode && mode1 == mode0 && mode2 == mode0 | |
7906 | && mode3 == QImode) | |
b9e4e5d1 | 7907 | type = v16qi_ftype_v16qi_v16qi_int; |
24408032 AH |
7908 | |
7909 | /* vshort, vshort, vshort, 4 bit literal. */ | |
7910 | else if (mode0 == V8HImode && mode1 == mode0 && mode2 == mode0 | |
7911 | && mode3 == QImode) | |
b9e4e5d1 | 7912 | type = v8hi_ftype_v8hi_v8hi_int; |
24408032 AH |
7913 | |
7914 | /* vint, vint, vint, 4 bit literal. */ | |
7915 | else if (mode0 == V4SImode && mode1 == mode0 && mode2 == mode0 | |
7916 | && mode3 == QImode) | |
b9e4e5d1 | 7917 | type = v4si_ftype_v4si_v4si_int; |
24408032 AH |
7918 | |
7919 | /* vfloat, vfloat, vfloat, 4 bit literal. */ | |
7920 | else if (mode0 == V4SFmode && mode1 == mode0 && mode2 == mode0 | |
7921 | && mode3 == QImode) | |
b9e4e5d1 | 7922 | type = v4sf_ftype_v4sf_v4sf_int; |
24408032 | 7923 | |
2212663f DB |
7924 | else |
7925 | abort (); | |
7926 | ||
7927 | def_builtin (d->mask, d->name, type, d->code); | |
7928 | } | |
7929 | ||
0ac081f6 | 7930 | /* Add the simple binary operators. */ |
00b960c7 | 7931 | d = (struct builtin_description *) bdesc_2arg; |
ca7558fc | 7932 | for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++) |
0ac081f6 AH |
7933 | { |
7934 | enum machine_mode mode0, mode1, mode2; | |
7935 | tree type; | |
7936 | ||
0559cc77 | 7937 | if (d->name == 0 || d->icode == CODE_FOR_nothing) |
0ac081f6 | 7938 | continue; |
f676971a | 7939 | |
0ac081f6 AH |
7940 | mode0 = insn_data[d->icode].operand[0].mode; |
7941 | mode1 = insn_data[d->icode].operand[1].mode; | |
7942 | mode2 = insn_data[d->icode].operand[2].mode; | |
7943 | ||
7944 | /* When all three operands are of the same mode. */ | |
7945 | if (mode0 == mode1 && mode1 == mode2) | |
7946 | { | |
7947 | switch (mode0) | |
7948 | { | |
7949 | case V4SFmode: | |
7950 | type = v4sf_ftype_v4sf_v4sf; | |
7951 | break; | |
7952 | case V4SImode: | |
7953 | type = v4si_ftype_v4si_v4si; | |
7954 | break; | |
7955 | case V16QImode: | |
7956 | type = v16qi_ftype_v16qi_v16qi; | |
7957 | break; | |
7958 | case V8HImode: | |
7959 | type = v8hi_ftype_v8hi_v8hi; | |
7960 | break; | |
a3170dc6 AH |
7961 | case V2SImode: |
7962 | type = v2si_ftype_v2si_v2si; | |
7963 | break; | |
7964 | case V2SFmode: | |
7965 | type = v2sf_ftype_v2sf_v2sf; | |
7966 | break; | |
7967 | case SImode: | |
7968 | type = int_ftype_int_int; | |
7969 | break; | |
0ac081f6 AH |
7970 | default: |
7971 | abort (); | |
7972 | } | |
7973 | } | |
7974 | ||
7975 | /* A few other combos we really don't want to do manually. */ | |
7976 | ||
7977 | /* vint, vfloat, vfloat. */ | |
7978 | else if (mode0 == V4SImode && mode1 == V4SFmode && mode2 == V4SFmode) | |
7979 | type = v4si_ftype_v4sf_v4sf; | |
7980 | ||
7981 | /* vshort, vchar, vchar. */ | |
7982 | else if (mode0 == V8HImode && mode1 == V16QImode && mode2 == V16QImode) | |
7983 | type = v8hi_ftype_v16qi_v16qi; | |
7984 | ||
7985 | /* vint, vshort, vshort. */ | |
7986 | else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V8HImode) | |
7987 | type = v4si_ftype_v8hi_v8hi; | |
7988 | ||
7989 | /* vshort, vint, vint. */ | |
7990 | else if (mode0 == V8HImode && mode1 == V4SImode && mode2 == V4SImode) | |
7991 | type = v8hi_ftype_v4si_v4si; | |
7992 | ||
7993 | /* vchar, vshort, vshort. */ | |
7994 | else if (mode0 == V16QImode && mode1 == V8HImode && mode2 == V8HImode) | |
7995 | type = v16qi_ftype_v8hi_v8hi; | |
7996 | ||
7997 | /* vint, vchar, vint. */ | |
7998 | else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V4SImode) | |
7999 | type = v4si_ftype_v16qi_v4si; | |
8000 | ||
fa066a23 AH |
8001 | /* vint, vchar, vchar. */ |
8002 | else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V16QImode) | |
8003 | type = v4si_ftype_v16qi_v16qi; | |
8004 | ||
0ac081f6 AH |
8005 | /* vint, vshort, vint. */ |
8006 | else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V4SImode) | |
8007 | type = v4si_ftype_v8hi_v4si; | |
f676971a | 8008 | |
2212663f DB |
8009 | /* vint, vint, 5 bit literal. */ |
8010 | else if (mode0 == V4SImode && mode1 == V4SImode && mode2 == QImode) | |
b9e4e5d1 | 8011 | type = v4si_ftype_v4si_int; |
f676971a | 8012 | |
2212663f DB |
8013 | /* vshort, vshort, 5 bit literal. */ |
8014 | else if (mode0 == V8HImode && mode1 == V8HImode && mode2 == QImode) | |
b9e4e5d1 | 8015 | type = v8hi_ftype_v8hi_int; |
f676971a | 8016 | |
2212663f DB |
8017 | /* vchar, vchar, 5 bit literal. */ |
8018 | else if (mode0 == V16QImode && mode1 == V16QImode && mode2 == QImode) | |
b9e4e5d1 | 8019 | type = v16qi_ftype_v16qi_int; |
0ac081f6 | 8020 | |
617e0e1d DB |
8021 | /* vfloat, vint, 5 bit literal. */ |
8022 | else if (mode0 == V4SFmode && mode1 == V4SImode && mode2 == QImode) | |
b9e4e5d1 | 8023 | type = v4sf_ftype_v4si_int; |
f676971a | 8024 | |
617e0e1d DB |
8025 | /* vint, vfloat, 5 bit literal. */ |
8026 | else if (mode0 == V4SImode && mode1 == V4SFmode && mode2 == QImode) | |
b9e4e5d1 | 8027 | type = v4si_ftype_v4sf_int; |
617e0e1d | 8028 | |
a3170dc6 AH |
8029 | else if (mode0 == V2SImode && mode1 == SImode && mode2 == SImode) |
8030 | type = v2si_ftype_int_int; | |
8031 | ||
8032 | else if (mode0 == V2SImode && mode1 == V2SImode && mode2 == QImode) | |
8033 | type = v2si_ftype_v2si_char; | |
8034 | ||
8035 | else if (mode0 == V2SImode && mode1 == SImode && mode2 == QImode) | |
8036 | type = v2si_ftype_int_char; | |
8037 | ||
0ac081f6 AH |
8038 | /* int, x, x. */ |
8039 | else if (mode0 == SImode) | |
8040 | { | |
8041 | switch (mode1) | |
8042 | { | |
8043 | case V4SImode: | |
8044 | type = int_ftype_v4si_v4si; | |
8045 | break; | |
8046 | case V4SFmode: | |
8047 | type = int_ftype_v4sf_v4sf; | |
8048 | break; | |
8049 | case V16QImode: | |
8050 | type = int_ftype_v16qi_v16qi; | |
8051 | break; | |
8052 | case V8HImode: | |
8053 | type = int_ftype_v8hi_v8hi; | |
8054 | break; | |
8055 | default: | |
8056 | abort (); | |
8057 | } | |
8058 | } | |
8059 | ||
8060 | else | |
8061 | abort (); | |
8062 | ||
2212663f DB |
8063 | def_builtin (d->mask, d->name, type, d->code); |
8064 | } | |
24408032 | 8065 | |
2212663f DB |
8066 | /* Add the simple unary operators. */ |
8067 | d = (struct builtin_description *) bdesc_1arg; | |
ca7558fc | 8068 | for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++) |
2212663f DB |
8069 | { |
8070 | enum machine_mode mode0, mode1; | |
8071 | tree type; | |
8072 | ||
0559cc77 | 8073 | if (d->name == 0 || d->icode == CODE_FOR_nothing) |
2212663f | 8074 | continue; |
f676971a | 8075 | |
2212663f DB |
8076 | mode0 = insn_data[d->icode].operand[0].mode; |
8077 | mode1 = insn_data[d->icode].operand[1].mode; | |
8078 | ||
8079 | if (mode0 == V4SImode && mode1 == QImode) | |
c4ad648e | 8080 | type = v4si_ftype_int; |
2212663f | 8081 | else if (mode0 == V8HImode && mode1 == QImode) |
c4ad648e | 8082 | type = v8hi_ftype_int; |
2212663f | 8083 | else if (mode0 == V16QImode && mode1 == QImode) |
c4ad648e | 8084 | type = v16qi_ftype_int; |
617e0e1d DB |
8085 | else if (mode0 == V4SFmode && mode1 == V4SFmode) |
8086 | type = v4sf_ftype_v4sf; | |
20e26713 AH |
8087 | else if (mode0 == V8HImode && mode1 == V16QImode) |
8088 | type = v8hi_ftype_v16qi; | |
8089 | else if (mode0 == V4SImode && mode1 == V8HImode) | |
8090 | type = v4si_ftype_v8hi; | |
a3170dc6 AH |
8091 | else if (mode0 == V2SImode && mode1 == V2SImode) |
8092 | type = v2si_ftype_v2si; | |
8093 | else if (mode0 == V2SFmode && mode1 == V2SFmode) | |
8094 | type = v2sf_ftype_v2sf; | |
8095 | else if (mode0 == V2SFmode && mode1 == V2SImode) | |
8096 | type = v2sf_ftype_v2si; | |
8097 | else if (mode0 == V2SImode && mode1 == V2SFmode) | |
8098 | type = v2si_ftype_v2sf; | |
8099 | else if (mode0 == V2SImode && mode1 == QImode) | |
8100 | type = v2si_ftype_char; | |
2212663f DB |
8101 | else |
8102 | abort (); | |
8103 | ||
0ac081f6 AH |
8104 | def_builtin (d->mask, d->name, type, d->code); |
8105 | } | |
8106 | } | |
8107 | ||
c15c90bb ZW |
8108 | static void |
8109 | rs6000_init_libfuncs (void) | |
8110 | { | |
8111 | if (!TARGET_HARD_FLOAT) | |
8112 | return; | |
8113 | ||
c9034561 | 8114 | if (DEFAULT_ABI != ABI_V4) |
c15c90bb | 8115 | { |
c9034561 | 8116 | if (TARGET_XCOFF && ! TARGET_POWER2 && ! TARGET_POWERPC) |
c15c90bb | 8117 | { |
c9034561 | 8118 | /* AIX library routines for float->int conversion. */ |
85363ca0 ZW |
8119 | set_conv_libfunc (sfix_optab, SImode, DFmode, "__itrunc"); |
8120 | set_conv_libfunc (ufix_optab, SImode, DFmode, "__uitrunc"); | |
4274207b DE |
8121 | set_conv_libfunc (sfix_optab, SImode, TFmode, "_qitrunc"); |
8122 | set_conv_libfunc (ufix_optab, SImode, TFmode, "_quitrunc"); | |
c15c90bb ZW |
8123 | } |
8124 | ||
c9034561 | 8125 | /* Standard AIX/Darwin/64-bit SVR4 quad floating point routines. */ |
6f85d0c4 DE |
8126 | set_optab_libfunc (add_optab, TFmode, "__gcc_qadd"); |
8127 | set_optab_libfunc (sub_optab, TFmode, "__gcc_qsub"); | |
8128 | set_optab_libfunc (smul_optab, TFmode, "__gcc_qmul"); | |
8129 | set_optab_libfunc (sdiv_optab, TFmode, "__gcc_qdiv"); | |
c15c90bb | 8130 | } |
c9034561 | 8131 | else |
c15c90bb | 8132 | { |
c9034561 | 8133 | /* 32-bit SVR4 quad floating point routines. */ |
c15c90bb ZW |
8134 | |
8135 | set_optab_libfunc (add_optab, TFmode, "_q_add"); | |
8136 | set_optab_libfunc (sub_optab, TFmode, "_q_sub"); | |
8137 | set_optab_libfunc (neg_optab, TFmode, "_q_neg"); | |
8138 | set_optab_libfunc (smul_optab, TFmode, "_q_mul"); | |
8139 | set_optab_libfunc (sdiv_optab, TFmode, "_q_div"); | |
8140 | if (TARGET_PPC_GPOPT || TARGET_POWER2) | |
8141 | set_optab_libfunc (sqrt_optab, TFmode, "_q_sqrt"); | |
8142 | ||
c9034561 ZW |
8143 | set_optab_libfunc (eq_optab, TFmode, "_q_feq"); |
8144 | set_optab_libfunc (ne_optab, TFmode, "_q_fne"); | |
8145 | set_optab_libfunc (gt_optab, TFmode, "_q_fgt"); | |
8146 | set_optab_libfunc (ge_optab, TFmode, "_q_fge"); | |
8147 | set_optab_libfunc (lt_optab, TFmode, "_q_flt"); | |
8148 | set_optab_libfunc (le_optab, TFmode, "_q_fle"); | |
8149 | ||
85363ca0 ZW |
8150 | set_conv_libfunc (sext_optab, TFmode, SFmode, "_q_stoq"); |
8151 | set_conv_libfunc (sext_optab, TFmode, DFmode, "_q_dtoq"); | |
8152 | set_conv_libfunc (trunc_optab, SFmode, TFmode, "_q_qtos"); | |
8153 | set_conv_libfunc (trunc_optab, DFmode, TFmode, "_q_qtod"); | |
8154 | set_conv_libfunc (sfix_optab, SImode, TFmode, "_q_qtoi"); | |
8155 | set_conv_libfunc (ufix_optab, SImode, TFmode, "_q_qtou"); | |
8156 | set_conv_libfunc (sfloat_optab, TFmode, SImode, "_q_itoq"); | |
c15c90bb ZW |
8157 | } |
8158 | } | |
fba73eb1 DE |
8159 | |
8160 | \f | |
8161 | /* Expand a block clear operation, and return 1 if successful. Return 0 | |
8162 | if we should let the compiler generate normal code. | |
8163 | ||
8164 | operands[0] is the destination | |
8165 | operands[1] is the length | |
8166 | operands[2] is the alignment */ | |
8167 | ||
8168 | int | |
8169 | expand_block_clear (rtx operands[]) | |
8170 | { | |
8171 | rtx orig_dest = operands[0]; | |
8172 | rtx bytes_rtx = operands[1]; | |
8173 | rtx align_rtx = operands[2]; | |
5514620a GK |
8174 | bool constp = (GET_CODE (bytes_rtx) == CONST_INT); |
8175 | HOST_WIDE_INT align; | |
8176 | HOST_WIDE_INT bytes; | |
fba73eb1 DE |
8177 | int offset; |
8178 | int clear_bytes; | |
5514620a | 8179 | int clear_step; |
fba73eb1 DE |
8180 | |
8181 | /* If this is not a fixed size move, just call memcpy */ | |
8182 | if (! constp) | |
8183 | return 0; | |
8184 | ||
8185 | /* If this is not a fixed size alignment, abort */ | |
8186 | if (GET_CODE (align_rtx) != CONST_INT) | |
8187 | abort (); | |
8188 | align = INTVAL (align_rtx) * BITS_PER_UNIT; | |
8189 | ||
8190 | /* Anything to clear? */ | |
8191 | bytes = INTVAL (bytes_rtx); | |
8192 | if (bytes <= 0) | |
8193 | return 1; | |
8194 | ||
5514620a GK |
8195 | /* Use the builtin memset after a point, to avoid huge code bloat. |
8196 | When optimize_size, avoid any significant code bloat; calling | |
8197 | memset is about 4 instructions, so allow for one instruction to | |
8198 | load zero and three to do clearing. */ | |
8199 | if (TARGET_ALTIVEC && align >= 128) | |
8200 | clear_step = 16; | |
8201 | else if (TARGET_POWERPC64 && align >= 32) | |
8202 | clear_step = 8; | |
8203 | else | |
8204 | clear_step = 4; | |
fba73eb1 | 8205 | |
5514620a GK |
8206 | if (optimize_size && bytes > 3 * clear_step) |
8207 | return 0; | |
8208 | if (! optimize_size && bytes > 8 * clear_step) | |
fba73eb1 DE |
8209 | return 0; |
8210 | ||
8211 | for (offset = 0; bytes > 0; offset += clear_bytes, bytes -= clear_bytes) | |
8212 | { | |
fba73eb1 DE |
8213 | enum machine_mode mode = BLKmode; |
8214 | rtx dest; | |
f676971a | 8215 | |
5514620a GK |
8216 | if (bytes >= 16 && TARGET_ALTIVEC && align >= 128) |
8217 | { | |
8218 | clear_bytes = 16; | |
8219 | mode = V4SImode; | |
8220 | } | |
8221 | else if (bytes >= 8 && TARGET_POWERPC64 | |
8222 | /* 64-bit loads and stores require word-aligned | |
8223 | displacements. */ | |
8224 | && (align >= 64 || (!STRICT_ALIGNMENT && align >= 32))) | |
fba73eb1 DE |
8225 | { |
8226 | clear_bytes = 8; | |
8227 | mode = DImode; | |
fba73eb1 | 8228 | } |
5514620a | 8229 | else if (bytes >= 4 && (align >= 32 || !STRICT_ALIGNMENT)) |
fba73eb1 DE |
8230 | { /* move 4 bytes */ |
8231 | clear_bytes = 4; | |
8232 | mode = SImode; | |
fba73eb1 | 8233 | } |
5514620a | 8234 | else if (bytes == 2 && (align >= 16 || !STRICT_ALIGNMENT)) |
fba73eb1 DE |
8235 | { /* move 2 bytes */ |
8236 | clear_bytes = 2; | |
8237 | mode = HImode; | |
fba73eb1 DE |
8238 | } |
8239 | else /* move 1 byte at a time */ | |
8240 | { | |
8241 | clear_bytes = 1; | |
8242 | mode = QImode; | |
fba73eb1 | 8243 | } |
f676971a | 8244 | |
fba73eb1 | 8245 | dest = adjust_address (orig_dest, mode, offset); |
f676971a | 8246 | |
5514620a | 8247 | emit_move_insn (dest, CONST0_RTX (mode)); |
fba73eb1 DE |
8248 | } |
8249 | ||
8250 | return 1; | |
8251 | } | |
8252 | ||
35aff10b | 8253 | \f |
7e69e155 MM |
8254 | /* Expand a block move operation, and return 1 if successful. Return 0 |
8255 | if we should let the compiler generate normal code. | |
8256 | ||
8257 | operands[0] is the destination | |
8258 | operands[1] is the source | |
8259 | operands[2] is the length | |
8260 | operands[3] is the alignment */ | |
8261 | ||
3933e0e1 MM |
8262 | #define MAX_MOVE_REG 4 |
8263 | ||
7e69e155 | 8264 | int |
a2369ed3 | 8265 | expand_block_move (rtx operands[]) |
7e69e155 | 8266 | { |
b6c9286a MM |
8267 | rtx orig_dest = operands[0]; |
8268 | rtx orig_src = operands[1]; | |
7e69e155 | 8269 | rtx bytes_rtx = operands[2]; |
7e69e155 | 8270 | rtx align_rtx = operands[3]; |
3933e0e1 | 8271 | int constp = (GET_CODE (bytes_rtx) == CONST_INT); |
5ee95df6 | 8272 | int align; |
3933e0e1 MM |
8273 | int bytes; |
8274 | int offset; | |
7e69e155 | 8275 | int move_bytes; |
cabfd258 GK |
8276 | rtx stores[MAX_MOVE_REG]; |
8277 | int num_reg = 0; | |
7e69e155 | 8278 | |
3933e0e1 | 8279 | /* If this is not a fixed size move, just call memcpy */ |
cc0d9ba8 | 8280 | if (! constp) |
3933e0e1 MM |
8281 | return 0; |
8282 | ||
5ee95df6 FS |
8283 | /* If this is not a fixed size alignment, abort */ |
8284 | if (GET_CODE (align_rtx) != CONST_INT) | |
8285 | abort (); | |
fba73eb1 | 8286 | align = INTVAL (align_rtx) * BITS_PER_UNIT; |
5ee95df6 | 8287 | |
7e69e155 | 8288 | /* Anything to move? */ |
3933e0e1 MM |
8289 | bytes = INTVAL (bytes_rtx); |
8290 | if (bytes <= 0) | |
7e69e155 MM |
8291 | return 1; |
8292 | ||
ea9982a8 | 8293 | /* store_one_arg depends on expand_block_move to handle at least the size of |
f676971a | 8294 | reg_parm_stack_space. */ |
ea9982a8 | 8295 | if (bytes > (TARGET_POWERPC64 ? 64 : 32)) |
7e69e155 MM |
8296 | return 0; |
8297 | ||
cabfd258 | 8298 | for (offset = 0; bytes > 0; offset += move_bytes, bytes -= move_bytes) |
7e69e155 | 8299 | { |
cabfd258 | 8300 | union { |
70128ad9 | 8301 | rtx (*movmemsi) (rtx, rtx, rtx, rtx); |
a2369ed3 | 8302 | rtx (*mov) (rtx, rtx); |
cabfd258 GK |
8303 | } gen_func; |
8304 | enum machine_mode mode = BLKmode; | |
8305 | rtx src, dest; | |
f676971a | 8306 | |
5514620a GK |
8307 | /* Altivec first, since it will be faster than a string move |
8308 | when it applies, and usually not significantly larger. */ | |
8309 | if (TARGET_ALTIVEC && bytes >= 16 && align >= 128) | |
8310 | { | |
8311 | move_bytes = 16; | |
8312 | mode = V4SImode; | |
8313 | gen_func.mov = gen_movv4si; | |
8314 | } | |
8315 | else if (TARGET_STRING | |
cabfd258 GK |
8316 | && bytes > 24 /* move up to 32 bytes at a time */ |
8317 | && ! fixed_regs[5] | |
8318 | && ! fixed_regs[6] | |
8319 | && ! fixed_regs[7] | |
8320 | && ! fixed_regs[8] | |
8321 | && ! fixed_regs[9] | |
8322 | && ! fixed_regs[10] | |
8323 | && ! fixed_regs[11] | |
8324 | && ! fixed_regs[12]) | |
7e69e155 | 8325 | { |
cabfd258 | 8326 | move_bytes = (bytes > 32) ? 32 : bytes; |
70128ad9 | 8327 | gen_func.movmemsi = gen_movmemsi_8reg; |
cabfd258 GK |
8328 | } |
8329 | else if (TARGET_STRING | |
8330 | && bytes > 16 /* move up to 24 bytes at a time */ | |
8331 | && ! fixed_regs[5] | |
8332 | && ! fixed_regs[6] | |
8333 | && ! fixed_regs[7] | |
8334 | && ! fixed_regs[8] | |
8335 | && ! fixed_regs[9] | |
8336 | && ! fixed_regs[10]) | |
8337 | { | |
8338 | move_bytes = (bytes > 24) ? 24 : bytes; | |
70128ad9 | 8339 | gen_func.movmemsi = gen_movmemsi_6reg; |
cabfd258 GK |
8340 | } |
8341 | else if (TARGET_STRING | |
8342 | && bytes > 8 /* move up to 16 bytes at a time */ | |
8343 | && ! fixed_regs[5] | |
8344 | && ! fixed_regs[6] | |
8345 | && ! fixed_regs[7] | |
8346 | && ! fixed_regs[8]) | |
8347 | { | |
8348 | move_bytes = (bytes > 16) ? 16 : bytes; | |
70128ad9 | 8349 | gen_func.movmemsi = gen_movmemsi_4reg; |
cabfd258 GK |
8350 | } |
8351 | else if (bytes >= 8 && TARGET_POWERPC64 | |
8352 | /* 64-bit loads and stores require word-aligned | |
8353 | displacements. */ | |
fba73eb1 | 8354 | && (align >= 64 || (!STRICT_ALIGNMENT && align >= 32))) |
cabfd258 GK |
8355 | { |
8356 | move_bytes = 8; | |
8357 | mode = DImode; | |
8358 | gen_func.mov = gen_movdi; | |
8359 | } | |
8360 | else if (TARGET_STRING && bytes > 4 && !TARGET_POWERPC64) | |
8361 | { /* move up to 8 bytes at a time */ | |
8362 | move_bytes = (bytes > 8) ? 8 : bytes; | |
70128ad9 | 8363 | gen_func.movmemsi = gen_movmemsi_2reg; |
cabfd258 | 8364 | } |
cd7d9ca4 | 8365 | else if (bytes >= 4 && (align >= 32 || !STRICT_ALIGNMENT)) |
cabfd258 GK |
8366 | { /* move 4 bytes */ |
8367 | move_bytes = 4; | |
8368 | mode = SImode; | |
8369 | gen_func.mov = gen_movsi; | |
8370 | } | |
cd7d9ca4 | 8371 | else if (bytes == 2 && (align >= 16 || !STRICT_ALIGNMENT)) |
cabfd258 GK |
8372 | { /* move 2 bytes */ |
8373 | move_bytes = 2; | |
8374 | mode = HImode; | |
8375 | gen_func.mov = gen_movhi; | |
8376 | } | |
8377 | else if (TARGET_STRING && bytes > 1) | |
8378 | { /* move up to 4 bytes at a time */ | |
8379 | move_bytes = (bytes > 4) ? 4 : bytes; | |
70128ad9 | 8380 | gen_func.movmemsi = gen_movmemsi_1reg; |
cabfd258 GK |
8381 | } |
8382 | else /* move 1 byte at a time */ | |
8383 | { | |
8384 | move_bytes = 1; | |
8385 | mode = QImode; | |
8386 | gen_func.mov = gen_movqi; | |
8387 | } | |
f676971a | 8388 | |
cabfd258 GK |
8389 | src = adjust_address (orig_src, mode, offset); |
8390 | dest = adjust_address (orig_dest, mode, offset); | |
f676971a EC |
8391 | |
8392 | if (mode != BLKmode) | |
cabfd258 GK |
8393 | { |
8394 | rtx tmp_reg = gen_reg_rtx (mode); | |
f676971a | 8395 | |
cabfd258 GK |
8396 | emit_insn ((*gen_func.mov) (tmp_reg, src)); |
8397 | stores[num_reg++] = (*gen_func.mov) (dest, tmp_reg); | |
4c64a852 | 8398 | } |
3933e0e1 | 8399 | |
cabfd258 GK |
8400 | if (mode == BLKmode || num_reg >= MAX_MOVE_REG || bytes == move_bytes) |
8401 | { | |
8402 | int i; | |
8403 | for (i = 0; i < num_reg; i++) | |
8404 | emit_insn (stores[i]); | |
8405 | num_reg = 0; | |
8406 | } | |
35aff10b | 8407 | |
cabfd258 | 8408 | if (mode == BLKmode) |
7e69e155 | 8409 | { |
70128ad9 | 8410 | /* Move the address into scratch registers. The movmemsi |
cabfd258 GK |
8411 | patterns require zero offset. */ |
8412 | if (!REG_P (XEXP (src, 0))) | |
b6c9286a | 8413 | { |
cabfd258 GK |
8414 | rtx src_reg = copy_addr_to_reg (XEXP (src, 0)); |
8415 | src = replace_equiv_address (src, src_reg); | |
b6c9286a | 8416 | } |
cabfd258 | 8417 | set_mem_size (src, GEN_INT (move_bytes)); |
f676971a | 8418 | |
cabfd258 | 8419 | if (!REG_P (XEXP (dest, 0))) |
3933e0e1 | 8420 | { |
cabfd258 GK |
8421 | rtx dest_reg = copy_addr_to_reg (XEXP (dest, 0)); |
8422 | dest = replace_equiv_address (dest, dest_reg); | |
7e69e155 | 8423 | } |
cabfd258 | 8424 | set_mem_size (dest, GEN_INT (move_bytes)); |
f676971a | 8425 | |
70128ad9 | 8426 | emit_insn ((*gen_func.movmemsi) (dest, src, |
cabfd258 GK |
8427 | GEN_INT (move_bytes & 31), |
8428 | align_rtx)); | |
7e69e155 | 8429 | } |
7e69e155 MM |
8430 | } |
8431 | ||
8432 | return 1; | |
8433 | } | |
8434 | ||
d62294f5 | 8435 | \f |
9caa3eb2 DE |
8436 | /* Return a string to perform a load_multiple operation. |
8437 | operands[0] is the vector. | |
8438 | operands[1] is the source address. | |
8439 | operands[2] is the first destination register. */ | |
8440 | ||
8441 | const char * | |
a2369ed3 | 8442 | rs6000_output_load_multiple (rtx operands[3]) |
9caa3eb2 DE |
8443 | { |
8444 | /* We have to handle the case where the pseudo used to contain the address | |
8445 | is assigned to one of the output registers. */ | |
8446 | int i, j; | |
8447 | int words = XVECLEN (operands[0], 0); | |
8448 | rtx xop[10]; | |
8449 | ||
8450 | if (XVECLEN (operands[0], 0) == 1) | |
8451 | return "{l|lwz} %2,0(%1)"; | |
8452 | ||
8453 | for (i = 0; i < words; i++) | |
8454 | if (refers_to_regno_p (REGNO (operands[2]) + i, | |
8455 | REGNO (operands[2]) + i + 1, operands[1], 0)) | |
8456 | { | |
8457 | if (i == words-1) | |
8458 | { | |
8459 | xop[0] = GEN_INT (4 * (words-1)); | |
8460 | xop[1] = operands[1]; | |
8461 | xop[2] = operands[2]; | |
8462 | output_asm_insn ("{lsi|lswi} %2,%1,%0\n\t{l|lwz} %1,%0(%1)", xop); | |
8463 | return ""; | |
8464 | } | |
8465 | else if (i == 0) | |
8466 | { | |
8467 | xop[0] = GEN_INT (4 * (words-1)); | |
8468 | xop[1] = operands[1]; | |
8469 | xop[2] = gen_rtx_REG (SImode, REGNO (operands[2]) + 1); | |
8470 | output_asm_insn ("{cal %1,4(%1)|addi %1,%1,4}\n\t{lsi|lswi} %2,%1,%0\n\t{l|lwz} %1,-4(%1)", xop); | |
8471 | return ""; | |
8472 | } | |
8473 | else | |
8474 | { | |
8475 | for (j = 0; j < words; j++) | |
8476 | if (j != i) | |
8477 | { | |
8478 | xop[0] = GEN_INT (j * 4); | |
8479 | xop[1] = operands[1]; | |
8480 | xop[2] = gen_rtx_REG (SImode, REGNO (operands[2]) + j); | |
8481 | output_asm_insn ("{l|lwz} %2,%0(%1)", xop); | |
8482 | } | |
8483 | xop[0] = GEN_INT (i * 4); | |
8484 | xop[1] = operands[1]; | |
8485 | output_asm_insn ("{l|lwz} %1,%0(%1)", xop); | |
8486 | return ""; | |
8487 | } | |
8488 | } | |
8489 | ||
8490 | return "{lsi|lswi} %2,%1,%N0"; | |
8491 | } | |
8492 | ||
9878760c | 8493 | \f |
a4f6c312 SS |
8494 | /* A validation routine: say whether CODE, a condition code, and MODE |
8495 | match. The other alternatives either don't make sense or should | |
8496 | never be generated. */ | |
39a10a29 | 8497 | |
48d72335 | 8498 | void |
a2369ed3 | 8499 | validate_condition_mode (enum rtx_code code, enum machine_mode mode) |
39a10a29 | 8500 | { |
ec8e098d PB |
8501 | if ((GET_RTX_CLASS (code) != RTX_COMPARE |
8502 | && GET_RTX_CLASS (code) != RTX_COMM_COMPARE) | |
39a10a29 GK |
8503 | || GET_MODE_CLASS (mode) != MODE_CC) |
8504 | abort (); | |
8505 | ||
8506 | /* These don't make sense. */ | |
8507 | if ((code == GT || code == LT || code == GE || code == LE) | |
8508 | && mode == CCUNSmode) | |
8509 | abort (); | |
8510 | ||
8511 | if ((code == GTU || code == LTU || code == GEU || code == LEU) | |
8512 | && mode != CCUNSmode) | |
8513 | abort (); | |
8514 | ||
8515 | if (mode != CCFPmode | |
8516 | && (code == ORDERED || code == UNORDERED | |
8517 | || code == UNEQ || code == LTGT | |
8518 | || code == UNGT || code == UNLT | |
8519 | || code == UNGE || code == UNLE)) | |
a4f6c312 | 8520 | abort (); |
f676971a EC |
8521 | |
8522 | /* These should never be generated except for | |
bc9ec0e0 | 8523 | flag_finite_math_only. */ |
39a10a29 | 8524 | if (mode == CCFPmode |
ad72b533 | 8525 | && ! flag_finite_math_only |
39a10a29 GK |
8526 | && (code == LE || code == GE |
8527 | || code == UNEQ || code == LTGT | |
8528 | || code == UNGT || code == UNLT)) | |
8529 | abort (); | |
8530 | ||
8531 | /* These are invalid; the information is not there. */ | |
f676971a | 8532 | if (mode == CCEQmode |
39a10a29 GK |
8533 | && code != EQ && code != NE) |
8534 | abort (); | |
8535 | } | |
8536 | ||
9878760c RK |
8537 | \f |
8538 | /* Return 1 if ANDOP is a mask that has no bits on that are not in the | |
8539 | mask required to convert the result of a rotate insn into a shift | |
b1765bde | 8540 | left insn of SHIFTOP bits. Both are known to be SImode CONST_INT. */ |
9878760c RK |
8541 | |
8542 | int | |
a2369ed3 | 8543 | includes_lshift_p (rtx shiftop, rtx andop) |
9878760c | 8544 | { |
e2c953b6 DE |
8545 | unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0; |
8546 | ||
8547 | shift_mask <<= INTVAL (shiftop); | |
9878760c | 8548 | |
b1765bde | 8549 | return (INTVAL (andop) & 0xffffffff & ~shift_mask) == 0; |
9878760c RK |
8550 | } |
8551 | ||
8552 | /* Similar, but for right shift. */ | |
8553 | ||
8554 | int | |
a2369ed3 | 8555 | includes_rshift_p (rtx shiftop, rtx andop) |
9878760c | 8556 | { |
a7653a2c | 8557 | unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0; |
9878760c RK |
8558 | |
8559 | shift_mask >>= INTVAL (shiftop); | |
8560 | ||
b1765bde | 8561 | return (INTVAL (andop) & 0xffffffff & ~shift_mask) == 0; |
e2c953b6 DE |
8562 | } |
8563 | ||
c5059423 AM |
8564 | /* Return 1 if ANDOP is a mask suitable for use with an rldic insn |
8565 | to perform a left shift. It must have exactly SHIFTOP least | |
b6d08ca1 | 8566 | significant 0's, then one or more 1's, then zero or more 0's. */ |
e2c953b6 DE |
8567 | |
8568 | int | |
a2369ed3 | 8569 | includes_rldic_lshift_p (rtx shiftop, rtx andop) |
e2c953b6 | 8570 | { |
c5059423 AM |
8571 | if (GET_CODE (andop) == CONST_INT) |
8572 | { | |
02071907 | 8573 | HOST_WIDE_INT c, lsb, shift_mask; |
e2c953b6 | 8574 | |
c5059423 | 8575 | c = INTVAL (andop); |
02071907 | 8576 | if (c == 0 || c == ~0) |
c5059423 | 8577 | return 0; |
e2c953b6 | 8578 | |
02071907 | 8579 | shift_mask = ~0; |
c5059423 AM |
8580 | shift_mask <<= INTVAL (shiftop); |
8581 | ||
b6d08ca1 | 8582 | /* Find the least significant one bit. */ |
c5059423 AM |
8583 | lsb = c & -c; |
8584 | ||
8585 | /* It must coincide with the LSB of the shift mask. */ | |
8586 | if (-lsb != shift_mask) | |
8587 | return 0; | |
e2c953b6 | 8588 | |
c5059423 AM |
8589 | /* Invert to look for the next transition (if any). */ |
8590 | c = ~c; | |
8591 | ||
8592 | /* Remove the low group of ones (originally low group of zeros). */ | |
8593 | c &= -lsb; | |
8594 | ||
8595 | /* Again find the lsb, and check we have all 1's above. */ | |
8596 | lsb = c & -c; | |
8597 | return c == -lsb; | |
8598 | } | |
8599 | else if (GET_CODE (andop) == CONST_DOUBLE | |
8600 | && (GET_MODE (andop) == VOIDmode || GET_MODE (andop) == DImode)) | |
8601 | { | |
02071907 AM |
8602 | HOST_WIDE_INT low, high, lsb; |
8603 | HOST_WIDE_INT shift_mask_low, shift_mask_high; | |
c5059423 AM |
8604 | |
8605 | low = CONST_DOUBLE_LOW (andop); | |
8606 | if (HOST_BITS_PER_WIDE_INT < 64) | |
8607 | high = CONST_DOUBLE_HIGH (andop); | |
8608 | ||
8609 | if ((low == 0 && (HOST_BITS_PER_WIDE_INT >= 64 || high == 0)) | |
02071907 | 8610 | || (low == ~0 && (HOST_BITS_PER_WIDE_INT >= 64 || high == ~0))) |
c5059423 AM |
8611 | return 0; |
8612 | ||
8613 | if (HOST_BITS_PER_WIDE_INT < 64 && low == 0) | |
8614 | { | |
02071907 | 8615 | shift_mask_high = ~0; |
c5059423 AM |
8616 | if (INTVAL (shiftop) > 32) |
8617 | shift_mask_high <<= INTVAL (shiftop) - 32; | |
8618 | ||
8619 | lsb = high & -high; | |
8620 | ||
8621 | if (-lsb != shift_mask_high || INTVAL (shiftop) < 32) | |
8622 | return 0; | |
8623 | ||
8624 | high = ~high; | |
8625 | high &= -lsb; | |
8626 | ||
8627 | lsb = high & -high; | |
8628 | return high == -lsb; | |
8629 | } | |
8630 | ||
02071907 | 8631 | shift_mask_low = ~0; |
c5059423 AM |
8632 | shift_mask_low <<= INTVAL (shiftop); |
8633 | ||
8634 | lsb = low & -low; | |
8635 | ||
8636 | if (-lsb != shift_mask_low) | |
8637 | return 0; | |
8638 | ||
8639 | if (HOST_BITS_PER_WIDE_INT < 64) | |
8640 | high = ~high; | |
8641 | low = ~low; | |
8642 | low &= -lsb; | |
8643 | ||
8644 | if (HOST_BITS_PER_WIDE_INT < 64 && low == 0) | |
8645 | { | |
8646 | lsb = high & -high; | |
8647 | return high == -lsb; | |
8648 | } | |
8649 | ||
8650 | lsb = low & -low; | |
8651 | return low == -lsb && (HOST_BITS_PER_WIDE_INT >= 64 || high == ~0); | |
8652 | } | |
8653 | else | |
8654 | return 0; | |
8655 | } | |
e2c953b6 | 8656 | |
c5059423 AM |
8657 | /* Return 1 if ANDOP is a mask suitable for use with an rldicr insn |
8658 | to perform a left shift. It must have SHIFTOP or more least | |
c1207243 | 8659 | significant 0's, with the remainder of the word 1's. */ |
e2c953b6 | 8660 | |
c5059423 | 8661 | int |
a2369ed3 | 8662 | includes_rldicr_lshift_p (rtx shiftop, rtx andop) |
c5059423 | 8663 | { |
e2c953b6 | 8664 | if (GET_CODE (andop) == CONST_INT) |
c5059423 | 8665 | { |
02071907 | 8666 | HOST_WIDE_INT c, lsb, shift_mask; |
c5059423 | 8667 | |
02071907 | 8668 | shift_mask = ~0; |
c5059423 AM |
8669 | shift_mask <<= INTVAL (shiftop); |
8670 | c = INTVAL (andop); | |
8671 | ||
c1207243 | 8672 | /* Find the least significant one bit. */ |
c5059423 AM |
8673 | lsb = c & -c; |
8674 | ||
8675 | /* It must be covered by the shift mask. | |
a4f6c312 | 8676 | This test also rejects c == 0. */ |
c5059423 AM |
8677 | if ((lsb & shift_mask) == 0) |
8678 | return 0; | |
8679 | ||
8680 | /* Check we have all 1's above the transition, and reject all 1's. */ | |
8681 | return c == -lsb && lsb != 1; | |
8682 | } | |
8683 | else if (GET_CODE (andop) == CONST_DOUBLE | |
8684 | && (GET_MODE (andop) == VOIDmode || GET_MODE (andop) == DImode)) | |
8685 | { | |
02071907 | 8686 | HOST_WIDE_INT low, lsb, shift_mask_low; |
c5059423 AM |
8687 | |
8688 | low = CONST_DOUBLE_LOW (andop); | |
8689 | ||
8690 | if (HOST_BITS_PER_WIDE_INT < 64) | |
8691 | { | |
02071907 | 8692 | HOST_WIDE_INT high, shift_mask_high; |
c5059423 AM |
8693 | |
8694 | high = CONST_DOUBLE_HIGH (andop); | |
8695 | ||
8696 | if (low == 0) | |
8697 | { | |
02071907 | 8698 | shift_mask_high = ~0; |
c5059423 AM |
8699 | if (INTVAL (shiftop) > 32) |
8700 | shift_mask_high <<= INTVAL (shiftop) - 32; | |
8701 | ||
8702 | lsb = high & -high; | |
8703 | ||
8704 | if ((lsb & shift_mask_high) == 0) | |
8705 | return 0; | |
8706 | ||
8707 | return high == -lsb; | |
8708 | } | |
8709 | if (high != ~0) | |
8710 | return 0; | |
8711 | } | |
8712 | ||
02071907 | 8713 | shift_mask_low = ~0; |
c5059423 AM |
8714 | shift_mask_low <<= INTVAL (shiftop); |
8715 | ||
8716 | lsb = low & -low; | |
8717 | ||
8718 | if ((lsb & shift_mask_low) == 0) | |
8719 | return 0; | |
8720 | ||
8721 | return low == -lsb && lsb != 1; | |
8722 | } | |
e2c953b6 | 8723 | else |
c5059423 | 8724 | return 0; |
9878760c | 8725 | } |
35068b43 | 8726 | |
11ac38b2 DE |
8727 | /* Return 1 if operands will generate a valid arguments to rlwimi |
8728 | instruction for insert with right shift in 64-bit mode. The mask may | |
8729 | not start on the first bit or stop on the last bit because wrap-around | |
8730 | effects of instruction do not correspond to semantics of RTL insn. */ | |
8731 | ||
8732 | int | |
8733 | insvdi_rshift_rlwimi_p (rtx sizeop, rtx startop, rtx shiftop) | |
8734 | { | |
8735 | if (INTVAL (startop) < 64 | |
8736 | && INTVAL (startop) > 32 | |
8737 | && (INTVAL (sizeop) + INTVAL (startop) < 64) | |
8738 | && (INTVAL (sizeop) + INTVAL (startop) > 33) | |
8739 | && (INTVAL (sizeop) + INTVAL (startop) + INTVAL (shiftop) < 96) | |
8740 | && (INTVAL (sizeop) + INTVAL (startop) + INTVAL (shiftop) >= 64) | |
8741 | && (64 - (INTVAL (shiftop) & 63)) >= INTVAL (sizeop)) | |
8742 | return 1; | |
8743 | ||
8744 | return 0; | |
8745 | } | |
8746 | ||
35068b43 | 8747 | /* Return 1 if REGNO (reg1) == REGNO (reg2) - 1 making them candidates |
90f81f99 | 8748 | for lfq and stfq insns iff the registers are hard registers. */ |
35068b43 RK |
8749 | |
8750 | int | |
a2369ed3 | 8751 | registers_ok_for_quad_peep (rtx reg1, rtx reg2) |
35068b43 RK |
8752 | { |
8753 | /* We might have been passed a SUBREG. */ | |
f676971a | 8754 | if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG) |
35068b43 | 8755 | return 0; |
f676971a | 8756 | |
90f81f99 AP |
8757 | /* We might have been passed non floating point registers. */ |
8758 | if (!FP_REGNO_P (REGNO (reg1)) | |
8759 | || !FP_REGNO_P (REGNO (reg2))) | |
8760 | return 0; | |
35068b43 RK |
8761 | |
8762 | return (REGNO (reg1) == REGNO (reg2) - 1); | |
8763 | } | |
8764 | ||
a4f6c312 SS |
8765 | /* Return 1 if addr1 and addr2 are suitable for lfq or stfq insn. |
8766 | addr1 and addr2 must be in consecutive memory locations | |
8767 | (addr2 == addr1 + 8). */ | |
35068b43 RK |
8768 | |
8769 | int | |
90f81f99 | 8770 | mems_ok_for_quad_peep (rtx mem1, rtx mem2) |
35068b43 | 8771 | { |
90f81f99 | 8772 | rtx addr1, addr2; |
e2c953b6 | 8773 | unsigned int reg1; |
35068b43 RK |
8774 | int offset1; |
8775 | ||
90f81f99 AP |
8776 | /* The mems cannot be volatile. */ |
8777 | if (MEM_VOLATILE_P (mem1) || MEM_VOLATILE_P (mem2)) | |
8778 | return 0; | |
f676971a | 8779 | |
90f81f99 AP |
8780 | addr1 = XEXP (mem1, 0); |
8781 | addr2 = XEXP (mem2, 0); | |
8782 | ||
35068b43 RK |
8783 | /* Extract an offset (if used) from the first addr. */ |
8784 | if (GET_CODE (addr1) == PLUS) | |
8785 | { | |
8786 | /* If not a REG, return zero. */ | |
8787 | if (GET_CODE (XEXP (addr1, 0)) != REG) | |
8788 | return 0; | |
8789 | else | |
8790 | { | |
c4ad648e | 8791 | reg1 = REGNO (XEXP (addr1, 0)); |
35068b43 RK |
8792 | /* The offset must be constant! */ |
8793 | if (GET_CODE (XEXP (addr1, 1)) != CONST_INT) | |
c4ad648e AM |
8794 | return 0; |
8795 | offset1 = INTVAL (XEXP (addr1, 1)); | |
35068b43 RK |
8796 | } |
8797 | } | |
8798 | else if (GET_CODE (addr1) != REG) | |
8799 | return 0; | |
8800 | else | |
8801 | { | |
8802 | reg1 = REGNO (addr1); | |
8803 | /* This was a simple (mem (reg)) expression. Offset is 0. */ | |
8804 | offset1 = 0; | |
8805 | } | |
8806 | ||
a2369ed3 | 8807 | /* Make sure the second address is a (mem (plus (reg) (const_int))) |
f676971a | 8808 | or if it is (mem (reg)) then make sure that offset1 is -8 and the same |
0f6937fe | 8809 | register as addr1. */ |
984e25ac | 8810 | if (offset1 == -8 && GET_CODE (addr2) == REG && reg1 == REGNO (addr2)) |
0f6937fe | 8811 | return 1; |
35068b43 RK |
8812 | if (GET_CODE (addr2) != PLUS) |
8813 | return 0; | |
8814 | ||
8815 | if (GET_CODE (XEXP (addr2, 0)) != REG | |
8816 | || GET_CODE (XEXP (addr2, 1)) != CONST_INT) | |
8817 | return 0; | |
8818 | ||
8819 | if (reg1 != REGNO (XEXP (addr2, 0))) | |
8820 | return 0; | |
8821 | ||
8822 | /* The offset for the second addr must be 8 more than the first addr. */ | |
8823 | if (INTVAL (XEXP (addr2, 1)) != offset1 + 8) | |
8824 | return 0; | |
8825 | ||
8826 | /* All the tests passed. addr1 and addr2 are valid for lfq or stfq | |
8827 | instructions. */ | |
8828 | return 1; | |
8829 | } | |
9878760c RK |
8830 | \f |
8831 | /* Return the register class of a scratch register needed to copy IN into | |
8832 | or out of a register in CLASS in MODE. If it can be done directly, | |
8833 | NO_REGS is returned. */ | |
8834 | ||
8835 | enum reg_class | |
f676971a | 8836 | secondary_reload_class (enum reg_class class, |
a9baceb1 GK |
8837 | enum machine_mode mode ATTRIBUTE_UNUSED, |
8838 | rtx in) | |
9878760c | 8839 | { |
5accd822 | 8840 | int regno; |
9878760c | 8841 | |
ab82a49f AP |
8842 | if (TARGET_ELF || (DEFAULT_ABI == ABI_DARWIN |
8843 | #if TARGET_MACHO | |
c4ad648e | 8844 | && MACHOPIC_INDIRECT |
ab82a49f | 8845 | #endif |
c4ad648e | 8846 | )) |
46fad5b7 DJ |
8847 | { |
8848 | /* We cannot copy a symbolic operand directly into anything | |
c4ad648e AM |
8849 | other than BASE_REGS for TARGET_ELF. So indicate that a |
8850 | register from BASE_REGS is needed as an intermediate | |
8851 | register. | |
f676971a | 8852 | |
46fad5b7 DJ |
8853 | On Darwin, pic addresses require a load from memory, which |
8854 | needs a base register. */ | |
8855 | if (class != BASE_REGS | |
c4ad648e AM |
8856 | && (GET_CODE (in) == SYMBOL_REF |
8857 | || GET_CODE (in) == HIGH | |
8858 | || GET_CODE (in) == LABEL_REF | |
8859 | || GET_CODE (in) == CONST)) | |
8860 | return BASE_REGS; | |
46fad5b7 | 8861 | } |
e7b7998a | 8862 | |
5accd822 DE |
8863 | if (GET_CODE (in) == REG) |
8864 | { | |
8865 | regno = REGNO (in); | |
8866 | if (regno >= FIRST_PSEUDO_REGISTER) | |
8867 | { | |
8868 | regno = true_regnum (in); | |
8869 | if (regno >= FIRST_PSEUDO_REGISTER) | |
8870 | regno = -1; | |
8871 | } | |
8872 | } | |
8873 | else if (GET_CODE (in) == SUBREG) | |
8874 | { | |
8875 | regno = true_regnum (in); | |
8876 | if (regno >= FIRST_PSEUDO_REGISTER) | |
8877 | regno = -1; | |
8878 | } | |
8879 | else | |
8880 | regno = -1; | |
8881 | ||
9878760c RK |
8882 | /* We can place anything into GENERAL_REGS and can put GENERAL_REGS |
8883 | into anything. */ | |
8884 | if (class == GENERAL_REGS || class == BASE_REGS | |
8885 | || (regno >= 0 && INT_REGNO_P (regno))) | |
8886 | return NO_REGS; | |
8887 | ||
8888 | /* Constants, memory, and FP registers can go into FP registers. */ | |
8889 | if ((regno == -1 || FP_REGNO_P (regno)) | |
8890 | && (class == FLOAT_REGS || class == NON_SPECIAL_REGS)) | |
8891 | return NO_REGS; | |
8892 | ||
0ac081f6 AH |
8893 | /* Memory, and AltiVec registers can go into AltiVec registers. */ |
8894 | if ((regno == -1 || ALTIVEC_REGNO_P (regno)) | |
8895 | && class == ALTIVEC_REGS) | |
8896 | return NO_REGS; | |
8897 | ||
9878760c RK |
8898 | /* We can copy among the CR registers. */ |
8899 | if ((class == CR_REGS || class == CR0_REGS) | |
8900 | && regno >= 0 && CR_REGNO_P (regno)) | |
8901 | return NO_REGS; | |
8902 | ||
8903 | /* Otherwise, we need GENERAL_REGS. */ | |
8904 | return GENERAL_REGS; | |
8905 | } | |
8906 | \f | |
8907 | /* Given a comparison operation, return the bit number in CCR to test. We | |
f676971a | 8908 | know this is a valid comparison. |
9878760c RK |
8909 | |
8910 | SCC_P is 1 if this is for an scc. That means that %D will have been | |
8911 | used instead of %C, so the bits will be in different places. | |
8912 | ||
b4ac57ab | 8913 | Return -1 if OP isn't a valid comparison for some reason. */ |
9878760c RK |
8914 | |
8915 | int | |
a2369ed3 | 8916 | ccr_bit (rtx op, int scc_p) |
9878760c RK |
8917 | { |
8918 | enum rtx_code code = GET_CODE (op); | |
8919 | enum machine_mode cc_mode; | |
8920 | int cc_regnum; | |
8921 | int base_bit; | |
9ebbca7d | 8922 | rtx reg; |
9878760c | 8923 | |
ec8e098d | 8924 | if (!COMPARISON_P (op)) |
9878760c RK |
8925 | return -1; |
8926 | ||
9ebbca7d GK |
8927 | reg = XEXP (op, 0); |
8928 | ||
8929 | if (GET_CODE (reg) != REG | |
8930 | || ! CR_REGNO_P (REGNO (reg))) | |
8931 | abort (); | |
8932 | ||
8933 | cc_mode = GET_MODE (reg); | |
8934 | cc_regnum = REGNO (reg); | |
8935 | base_bit = 4 * (cc_regnum - CR0_REGNO); | |
9878760c | 8936 | |
39a10a29 | 8937 | validate_condition_mode (code, cc_mode); |
c5defebb | 8938 | |
b7053a3f GK |
8939 | /* When generating a sCOND operation, only positive conditions are |
8940 | allowed. */ | |
8941 | if (scc_p && code != EQ && code != GT && code != LT && code != UNORDERED | |
8942 | && code != GTU && code != LTU) | |
8943 | abort (); | |
f676971a | 8944 | |
9878760c RK |
8945 | switch (code) |
8946 | { | |
8947 | case NE: | |
8948 | return scc_p ? base_bit + 3 : base_bit + 2; | |
8949 | case EQ: | |
8950 | return base_bit + 2; | |
1c882ea4 | 8951 | case GT: case GTU: case UNLE: |
9878760c | 8952 | return base_bit + 1; |
1c882ea4 | 8953 | case LT: case LTU: case UNGE: |
9878760c | 8954 | return base_bit; |
1c882ea4 GK |
8955 | case ORDERED: case UNORDERED: |
8956 | return base_bit + 3; | |
9878760c RK |
8957 | |
8958 | case GE: case GEU: | |
39a10a29 | 8959 | /* If scc, we will have done a cror to put the bit in the |
9878760c RK |
8960 | unordered position. So test that bit. For integer, this is ! LT |
8961 | unless this is an scc insn. */ | |
39a10a29 | 8962 | return scc_p ? base_bit + 3 : base_bit; |
9878760c RK |
8963 | |
8964 | case LE: case LEU: | |
39a10a29 | 8965 | return scc_p ? base_bit + 3 : base_bit + 1; |
1c882ea4 | 8966 | |
9878760c RK |
8967 | default: |
8968 | abort (); | |
8969 | } | |
8970 | } | |
1ff7789b | 8971 | \f |
8d30c4ee | 8972 | /* Return the GOT register. */ |
1ff7789b MM |
8973 | |
8974 | struct rtx_def * | |
a2369ed3 | 8975 | rs6000_got_register (rtx value ATTRIBUTE_UNUSED) |
1ff7789b | 8976 | { |
a4f6c312 SS |
8977 | /* The second flow pass currently (June 1999) can't update |
8978 | regs_ever_live without disturbing other parts of the compiler, so | |
8979 | update it here to make the prolog/epilogue code happy. */ | |
1db02437 FS |
8980 | if (no_new_pseudos && ! regs_ever_live[RS6000_PIC_OFFSET_TABLE_REGNUM]) |
8981 | regs_ever_live[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1; | |
1ff7789b | 8982 | |
8d30c4ee | 8983 | current_function_uses_pic_offset_table = 1; |
3cb999d8 | 8984 | |
1ff7789b MM |
8985 | return pic_offset_table_rtx; |
8986 | } | |
a7df97e6 | 8987 | \f |
e2500fed GK |
8988 | /* Function to init struct machine_function. |
8989 | This will be called, via a pointer variable, | |
8990 | from push_function_context. */ | |
a7df97e6 | 8991 | |
e2500fed | 8992 | static struct machine_function * |
863d938c | 8993 | rs6000_init_machine_status (void) |
a7df97e6 | 8994 | { |
e2500fed | 8995 | return ggc_alloc_cleared (sizeof (machine_function)); |
a7df97e6 | 8996 | } |
9878760c | 8997 | \f |
0ba1b2ff AM |
8998 | /* These macros test for integers and extract the low-order bits. */ |
8999 | #define INT_P(X) \ | |
9000 | ((GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST_DOUBLE) \ | |
9001 | && GET_MODE (X) == VOIDmode) | |
9002 | ||
9003 | #define INT_LOWPART(X) \ | |
9004 | (GET_CODE (X) == CONST_INT ? INTVAL (X) : CONST_DOUBLE_LOW (X)) | |
9005 | ||
9006 | int | |
a2369ed3 | 9007 | extract_MB (rtx op) |
0ba1b2ff AM |
9008 | { |
9009 | int i; | |
9010 | unsigned long val = INT_LOWPART (op); | |
9011 | ||
9012 | /* If the high bit is zero, the value is the first 1 bit we find | |
9013 | from the left. */ | |
9014 | if ((val & 0x80000000) == 0) | |
9015 | { | |
9016 | if ((val & 0xffffffff) == 0) | |
9017 | abort (); | |
9018 | ||
9019 | i = 1; | |
9020 | while (((val <<= 1) & 0x80000000) == 0) | |
9021 | ++i; | |
9022 | return i; | |
9023 | } | |
9024 | ||
9025 | /* If the high bit is set and the low bit is not, or the mask is all | |
9026 | 1's, the value is zero. */ | |
9027 | if ((val & 1) == 0 || (val & 0xffffffff) == 0xffffffff) | |
9028 | return 0; | |
9029 | ||
9030 | /* Otherwise we have a wrap-around mask. Look for the first 0 bit | |
9031 | from the right. */ | |
9032 | i = 31; | |
9033 | while (((val >>= 1) & 1) != 0) | |
9034 | --i; | |
9035 | ||
9036 | return i; | |
9037 | } | |
9038 | ||
9039 | int | |
a2369ed3 | 9040 | extract_ME (rtx op) |
0ba1b2ff AM |
9041 | { |
9042 | int i; | |
9043 | unsigned long val = INT_LOWPART (op); | |
9044 | ||
9045 | /* If the low bit is zero, the value is the first 1 bit we find from | |
9046 | the right. */ | |
9047 | if ((val & 1) == 0) | |
9048 | { | |
9049 | if ((val & 0xffffffff) == 0) | |
9050 | abort (); | |
9051 | ||
9052 | i = 30; | |
9053 | while (((val >>= 1) & 1) == 0) | |
9054 | --i; | |
9055 | ||
9056 | return i; | |
9057 | } | |
9058 | ||
9059 | /* If the low bit is set and the high bit is not, or the mask is all | |
9060 | 1's, the value is 31. */ | |
9061 | if ((val & 0x80000000) == 0 || (val & 0xffffffff) == 0xffffffff) | |
9062 | return 31; | |
9063 | ||
9064 | /* Otherwise we have a wrap-around mask. Look for the first 0 bit | |
9065 | from the left. */ | |
9066 | i = 0; | |
9067 | while (((val <<= 1) & 0x80000000) != 0) | |
9068 | ++i; | |
9069 | ||
9070 | return i; | |
9071 | } | |
9072 | ||
c4501e62 JJ |
9073 | /* Locate some local-dynamic symbol still in use by this function |
9074 | so that we can print its name in some tls_ld pattern. */ | |
9075 | ||
9076 | static const char * | |
863d938c | 9077 | rs6000_get_some_local_dynamic_name (void) |
c4501e62 JJ |
9078 | { |
9079 | rtx insn; | |
9080 | ||
9081 | if (cfun->machine->some_ld_name) | |
9082 | return cfun->machine->some_ld_name; | |
9083 | ||
9084 | for (insn = get_insns (); insn ; insn = NEXT_INSN (insn)) | |
9085 | if (INSN_P (insn) | |
9086 | && for_each_rtx (&PATTERN (insn), | |
9087 | rs6000_get_some_local_dynamic_name_1, 0)) | |
9088 | return cfun->machine->some_ld_name; | |
9089 | ||
9090 | abort (); | |
9091 | } | |
9092 | ||
9093 | /* Helper function for rs6000_get_some_local_dynamic_name. */ | |
9094 | ||
9095 | static int | |
a2369ed3 | 9096 | rs6000_get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED) |
c4501e62 JJ |
9097 | { |
9098 | rtx x = *px; | |
9099 | ||
9100 | if (GET_CODE (x) == SYMBOL_REF) | |
9101 | { | |
9102 | const char *str = XSTR (x, 0); | |
9103 | if (SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC) | |
9104 | { | |
9105 | cfun->machine->some_ld_name = str; | |
9106 | return 1; | |
9107 | } | |
9108 | } | |
9109 | ||
9110 | return 0; | |
9111 | } | |
9112 | ||
85b776df AM |
9113 | /* Write out a function code label. */ |
9114 | ||
9115 | void | |
9116 | rs6000_output_function_entry (FILE *file, const char *fname) | |
9117 | { | |
9118 | if (fname[0] != '.') | |
9119 | { | |
9120 | switch (DEFAULT_ABI) | |
9121 | { | |
9122 | default: | |
9123 | abort (); | |
9124 | ||
9125 | case ABI_AIX: | |
9126 | if (DOT_SYMBOLS) | |
9127 | putc ('.', file); | |
9128 | else | |
9129 | ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "L."); | |
9130 | break; | |
9131 | ||
9132 | case ABI_V4: | |
9133 | case ABI_DARWIN: | |
9134 | break; | |
9135 | } | |
9136 | } | |
9137 | if (TARGET_AIX) | |
9138 | RS6000_OUTPUT_BASENAME (file, fname); | |
9139 | else | |
9140 | assemble_name (file, fname); | |
9141 | } | |
9142 | ||
9878760c RK |
9143 | /* Print an operand. Recognize special options, documented below. */ |
9144 | ||
38c1f2d7 | 9145 | #if TARGET_ELF |
d9407988 | 9146 | #define SMALL_DATA_RELOC ((rs6000_sdata == SDATA_EABI) ? "sda21" : "sdarel") |
8fbd2dc7 | 9147 | #define SMALL_DATA_REG ((rs6000_sdata == SDATA_EABI) ? 0 : 13) |
ba5e43aa MM |
9148 | #else |
9149 | #define SMALL_DATA_RELOC "sda21" | |
8fbd2dc7 | 9150 | #define SMALL_DATA_REG 0 |
ba5e43aa MM |
9151 | #endif |
9152 | ||
9878760c | 9153 | void |
a2369ed3 | 9154 | print_operand (FILE *file, rtx x, int code) |
9878760c RK |
9155 | { |
9156 | int i; | |
a260abc9 | 9157 | HOST_WIDE_INT val; |
0ba1b2ff | 9158 | unsigned HOST_WIDE_INT uval; |
9878760c RK |
9159 | |
9160 | switch (code) | |
9161 | { | |
a8b3aeda | 9162 | case '.': |
a85d226b RK |
9163 | /* Write out an instruction after the call which may be replaced |
9164 | with glue code by the loader. This depends on the AIX version. */ | |
9165 | asm_fprintf (file, RS6000_CALL_GLUE); | |
a8b3aeda RK |
9166 | return; |
9167 | ||
81eace42 GK |
9168 | /* %a is output_address. */ |
9169 | ||
9854d9ed RK |
9170 | case 'A': |
9171 | /* If X is a constant integer whose low-order 5 bits are zero, | |
9172 | write 'l'. Otherwise, write 'r'. This is a kludge to fix a bug | |
76229ac8 | 9173 | in the AIX assembler where "sri" with a zero shift count |
20e26713 | 9174 | writes a trash instruction. */ |
9854d9ed | 9175 | if (GET_CODE (x) == CONST_INT && (INTVAL (x) & 31) == 0) |
76229ac8 | 9176 | putc ('l', file); |
9854d9ed | 9177 | else |
76229ac8 | 9178 | putc ('r', file); |
9854d9ed RK |
9179 | return; |
9180 | ||
9181 | case 'b': | |
e2c953b6 DE |
9182 | /* If constant, low-order 16 bits of constant, unsigned. |
9183 | Otherwise, write normally. */ | |
9184 | if (INT_P (x)) | |
9185 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 0xffff); | |
9186 | else | |
9187 | print_operand (file, x, 0); | |
cad12a8d RK |
9188 | return; |
9189 | ||
a260abc9 DE |
9190 | case 'B': |
9191 | /* If the low-order bit is zero, write 'r'; otherwise, write 'l' | |
9192 | for 64-bit mask direction. */ | |
296b8152 | 9193 | putc (((INT_LOWPART(x) & 1) == 0 ? 'r' : 'l'), file); |
a238cd8b | 9194 | return; |
a260abc9 | 9195 | |
81eace42 GK |
9196 | /* %c is output_addr_const if a CONSTANT_ADDRESS_P, otherwise |
9197 | output_operand. */ | |
9198 | ||
423c1189 AH |
9199 | case 'c': |
9200 | /* X is a CR register. Print the number of the GT bit of the CR. */ | |
9201 | if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x))) | |
9202 | output_operand_lossage ("invalid %%E value"); | |
9203 | else | |
9204 | fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO) + 1); | |
9205 | return; | |
9206 | ||
9207 | case 'D': | |
6b1fedc3 | 9208 | /* Like 'J' but get to the EQ bit. */ |
423c1189 AH |
9209 | if (GET_CODE (x) != REG) |
9210 | abort (); | |
9211 | ||
6b1fedc3 AH |
9212 | /* Bit 1 is EQ bit. */ |
9213 | i = 4 * (REGNO (x) - CR0_REGNO) + 2; | |
423c1189 AH |
9214 | |
9215 | /* If we want bit 31, write a shift count of zero, not 32. */ | |
9216 | fprintf (file, "%d", i == 31 ? 0 : i + 1); | |
9217 | return; | |
9218 | ||
9854d9ed | 9219 | case 'E': |
39a10a29 | 9220 | /* X is a CR register. Print the number of the EQ bit of the CR */ |
9854d9ed RK |
9221 | if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x))) |
9222 | output_operand_lossage ("invalid %%E value"); | |
78fbdbf7 | 9223 | else |
39a10a29 | 9224 | fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO) + 2); |
a85d226b | 9225 | return; |
9854d9ed RK |
9226 | |
9227 | case 'f': | |
9228 | /* X is a CR register. Print the shift count needed to move it | |
9229 | to the high-order four bits. */ | |
9230 | if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x))) | |
9231 | output_operand_lossage ("invalid %%f value"); | |
9232 | else | |
9ebbca7d | 9233 | fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO)); |
9854d9ed RK |
9234 | return; |
9235 | ||
9236 | case 'F': | |
9237 | /* Similar, but print the count for the rotate in the opposite | |
9238 | direction. */ | |
9239 | if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x))) | |
9240 | output_operand_lossage ("invalid %%F value"); | |
9241 | else | |
9ebbca7d | 9242 | fprintf (file, "%d", 32 - 4 * (REGNO (x) - CR0_REGNO)); |
9854d9ed RK |
9243 | return; |
9244 | ||
9245 | case 'G': | |
9246 | /* X is a constant integer. If it is negative, print "m", | |
43aa4e05 | 9247 | otherwise print "z". This is to make an aze or ame insn. */ |
9854d9ed RK |
9248 | if (GET_CODE (x) != CONST_INT) |
9249 | output_operand_lossage ("invalid %%G value"); | |
9250 | else if (INTVAL (x) >= 0) | |
76229ac8 | 9251 | putc ('z', file); |
9854d9ed | 9252 | else |
76229ac8 | 9253 | putc ('m', file); |
9854d9ed | 9254 | return; |
e2c953b6 | 9255 | |
9878760c | 9256 | case 'h': |
a4f6c312 SS |
9257 | /* If constant, output low-order five bits. Otherwise, write |
9258 | normally. */ | |
9878760c | 9259 | if (INT_P (x)) |
5f59ecb7 | 9260 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 31); |
9878760c RK |
9261 | else |
9262 | print_operand (file, x, 0); | |
9263 | return; | |
9264 | ||
64305719 | 9265 | case 'H': |
a4f6c312 SS |
9266 | /* If constant, output low-order six bits. Otherwise, write |
9267 | normally. */ | |
64305719 | 9268 | if (INT_P (x)) |
5f59ecb7 | 9269 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 63); |
64305719 DE |
9270 | else |
9271 | print_operand (file, x, 0); | |
9272 | return; | |
9273 | ||
9854d9ed RK |
9274 | case 'I': |
9275 | /* Print `i' if this is a constant, else nothing. */ | |
9878760c | 9276 | if (INT_P (x)) |
76229ac8 | 9277 | putc ('i', file); |
9878760c RK |
9278 | return; |
9279 | ||
9854d9ed RK |
9280 | case 'j': |
9281 | /* Write the bit number in CCR for jump. */ | |
9282 | i = ccr_bit (x, 0); | |
9283 | if (i == -1) | |
9284 | output_operand_lossage ("invalid %%j code"); | |
9878760c | 9285 | else |
9854d9ed | 9286 | fprintf (file, "%d", i); |
9878760c RK |
9287 | return; |
9288 | ||
9854d9ed RK |
9289 | case 'J': |
9290 | /* Similar, but add one for shift count in rlinm for scc and pass | |
9291 | scc flag to `ccr_bit'. */ | |
9292 | i = ccr_bit (x, 1); | |
9293 | if (i == -1) | |
9294 | output_operand_lossage ("invalid %%J code"); | |
9295 | else | |
a0466a68 RK |
9296 | /* If we want bit 31, write a shift count of zero, not 32. */ |
9297 | fprintf (file, "%d", i == 31 ? 0 : i + 1); | |
9878760c RK |
9298 | return; |
9299 | ||
9854d9ed RK |
9300 | case 'k': |
9301 | /* X must be a constant. Write the 1's complement of the | |
9302 | constant. */ | |
9878760c | 9303 | if (! INT_P (x)) |
9854d9ed | 9304 | output_operand_lossage ("invalid %%k value"); |
e2c953b6 DE |
9305 | else |
9306 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, ~ INT_LOWPART (x)); | |
9878760c RK |
9307 | return; |
9308 | ||
81eace42 | 9309 | case 'K': |
9ebbca7d GK |
9310 | /* X must be a symbolic constant on ELF. Write an |
9311 | expression suitable for an 'addi' that adds in the low 16 | |
9312 | bits of the MEM. */ | |
9313 | if (GET_CODE (x) != CONST) | |
9314 | { | |
9315 | print_operand_address (file, x); | |
9316 | fputs ("@l", file); | |
9317 | } | |
9318 | else | |
9319 | { | |
9320 | if (GET_CODE (XEXP (x, 0)) != PLUS | |
9321 | || (GET_CODE (XEXP (XEXP (x, 0), 0)) != SYMBOL_REF | |
9322 | && GET_CODE (XEXP (XEXP (x, 0), 0)) != LABEL_REF) | |
9323 | || GET_CODE (XEXP (XEXP (x, 0), 1)) != CONST_INT) | |
53cd5d6c | 9324 | output_operand_lossage ("invalid %%K value"); |
9ebbca7d GK |
9325 | print_operand_address (file, XEXP (XEXP (x, 0), 0)); |
9326 | fputs ("@l", file); | |
ed8d2920 MM |
9327 | /* For GNU as, there must be a non-alphanumeric character |
9328 | between 'l' and the number. The '-' is added by | |
9329 | print_operand() already. */ | |
9330 | if (INTVAL (XEXP (XEXP (x, 0), 1)) >= 0) | |
9331 | fputs ("+", file); | |
9ebbca7d GK |
9332 | print_operand (file, XEXP (XEXP (x, 0), 1), 0); |
9333 | } | |
81eace42 GK |
9334 | return; |
9335 | ||
9336 | /* %l is output_asm_label. */ | |
9ebbca7d | 9337 | |
9854d9ed RK |
9338 | case 'L': |
9339 | /* Write second word of DImode or DFmode reference. Works on register | |
9340 | or non-indexed memory only. */ | |
9341 | if (GET_CODE (x) == REG) | |
fb5c67a7 | 9342 | fputs (reg_names[REGNO (x) + 1], file); |
9854d9ed RK |
9343 | else if (GET_CODE (x) == MEM) |
9344 | { | |
9345 | /* Handle possible auto-increment. Since it is pre-increment and | |
1427100a | 9346 | we have already done it, we can just use an offset of word. */ |
9854d9ed RK |
9347 | if (GET_CODE (XEXP (x, 0)) == PRE_INC |
9348 | || GET_CODE (XEXP (x, 0)) == PRE_DEC) | |
ed8908e7 RK |
9349 | output_address (plus_constant (XEXP (XEXP (x, 0), 0), |
9350 | UNITS_PER_WORD)); | |
9854d9ed | 9351 | else |
d7624dc0 RK |
9352 | output_address (XEXP (adjust_address_nv (x, SImode, |
9353 | UNITS_PER_WORD), | |
9354 | 0)); | |
ed8908e7 | 9355 | |
ba5e43aa | 9356 | if (small_data_operand (x, GET_MODE (x))) |
8fbd2dc7 MM |
9357 | fprintf (file, "@%s(%s)", SMALL_DATA_RELOC, |
9358 | reg_names[SMALL_DATA_REG]); | |
9854d9ed | 9359 | } |
9878760c | 9360 | return; |
f676971a | 9361 | |
9878760c RK |
9362 | case 'm': |
9363 | /* MB value for a mask operand. */ | |
b1765bde | 9364 | if (! mask_operand (x, SImode)) |
9878760c RK |
9365 | output_operand_lossage ("invalid %%m value"); |
9366 | ||
0ba1b2ff | 9367 | fprintf (file, "%d", extract_MB (x)); |
9878760c RK |
9368 | return; |
9369 | ||
9370 | case 'M': | |
9371 | /* ME value for a mask operand. */ | |
b1765bde | 9372 | if (! mask_operand (x, SImode)) |
a260abc9 | 9373 | output_operand_lossage ("invalid %%M value"); |
9878760c | 9374 | |
0ba1b2ff | 9375 | fprintf (file, "%d", extract_ME (x)); |
9878760c RK |
9376 | return; |
9377 | ||
81eace42 GK |
9378 | /* %n outputs the negative of its operand. */ |
9379 | ||
9878760c RK |
9380 | case 'N': |
9381 | /* Write the number of elements in the vector times 4. */ | |
9382 | if (GET_CODE (x) != PARALLEL) | |
9383 | output_operand_lossage ("invalid %%N value"); | |
e2c953b6 DE |
9384 | else |
9385 | fprintf (file, "%d", XVECLEN (x, 0) * 4); | |
9878760c RK |
9386 | return; |
9387 | ||
9388 | case 'O': | |
9389 | /* Similar, but subtract 1 first. */ | |
9390 | if (GET_CODE (x) != PARALLEL) | |
1427100a | 9391 | output_operand_lossage ("invalid %%O value"); |
e2c953b6 DE |
9392 | else |
9393 | fprintf (file, "%d", (XVECLEN (x, 0) - 1) * 4); | |
9878760c RK |
9394 | return; |
9395 | ||
9854d9ed RK |
9396 | case 'p': |
9397 | /* X is a CONST_INT that is a power of two. Output the logarithm. */ | |
9398 | if (! INT_P (x) | |
2bfcf297 | 9399 | || INT_LOWPART (x) < 0 |
9854d9ed RK |
9400 | || (i = exact_log2 (INT_LOWPART (x))) < 0) |
9401 | output_operand_lossage ("invalid %%p value"); | |
e2c953b6 DE |
9402 | else |
9403 | fprintf (file, "%d", i); | |
9854d9ed RK |
9404 | return; |
9405 | ||
9878760c RK |
9406 | case 'P': |
9407 | /* The operand must be an indirect memory reference. The result | |
8bb418a3 | 9408 | is the register name. */ |
9878760c RK |
9409 | if (GET_CODE (x) != MEM || GET_CODE (XEXP (x, 0)) != REG |
9410 | || REGNO (XEXP (x, 0)) >= 32) | |
9411 | output_operand_lossage ("invalid %%P value"); | |
e2c953b6 | 9412 | else |
fb5c67a7 | 9413 | fputs (reg_names[REGNO (XEXP (x, 0))], file); |
9878760c RK |
9414 | return; |
9415 | ||
dfbdccdb GK |
9416 | case 'q': |
9417 | /* This outputs the logical code corresponding to a boolean | |
9418 | expression. The expression may have one or both operands | |
39a10a29 | 9419 | negated (if one, only the first one). For condition register |
c4ad648e AM |
9420 | logical operations, it will also treat the negated |
9421 | CR codes as NOTs, but not handle NOTs of them. */ | |
dfbdccdb | 9422 | { |
63bc1d05 | 9423 | const char *const *t = 0; |
dfbdccdb GK |
9424 | const char *s; |
9425 | enum rtx_code code = GET_CODE (x); | |
9426 | static const char * const tbl[3][3] = { | |
9427 | { "and", "andc", "nor" }, | |
9428 | { "or", "orc", "nand" }, | |
9429 | { "xor", "eqv", "xor" } }; | |
9430 | ||
9431 | if (code == AND) | |
9432 | t = tbl[0]; | |
9433 | else if (code == IOR) | |
9434 | t = tbl[1]; | |
9435 | else if (code == XOR) | |
9436 | t = tbl[2]; | |
9437 | else | |
9438 | output_operand_lossage ("invalid %%q value"); | |
9439 | ||
9440 | if (GET_CODE (XEXP (x, 0)) != NOT) | |
9441 | s = t[0]; | |
9442 | else | |
9443 | { | |
9444 | if (GET_CODE (XEXP (x, 1)) == NOT) | |
9445 | s = t[2]; | |
9446 | else | |
9447 | s = t[1]; | |
9448 | } | |
f676971a | 9449 | |
dfbdccdb GK |
9450 | fputs (s, file); |
9451 | } | |
9452 | return; | |
9453 | ||
2c4a9cff DE |
9454 | case 'Q': |
9455 | if (TARGET_MFCRF) | |
3b6ce0af | 9456 | fputc (',', file); |
5efb1046 | 9457 | /* FALLTHRU */ |
2c4a9cff DE |
9458 | else |
9459 | return; | |
9460 | ||
9854d9ed RK |
9461 | case 'R': |
9462 | /* X is a CR register. Print the mask for `mtcrf'. */ | |
9463 | if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x))) | |
9464 | output_operand_lossage ("invalid %%R value"); | |
9465 | else | |
9ebbca7d | 9466 | fprintf (file, "%d", 128 >> (REGNO (x) - CR0_REGNO)); |
9878760c | 9467 | return; |
9854d9ed RK |
9468 | |
9469 | case 's': | |
9470 | /* Low 5 bits of 32 - value */ | |
9471 | if (! INT_P (x)) | |
9472 | output_operand_lossage ("invalid %%s value"); | |
e2c953b6 DE |
9473 | else |
9474 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, (32 - INT_LOWPART (x)) & 31); | |
9878760c | 9475 | return; |
9854d9ed | 9476 | |
a260abc9 | 9477 | case 'S': |
0ba1b2ff | 9478 | /* PowerPC64 mask position. All 0's is excluded. |
a260abc9 DE |
9479 | CONST_INT 32-bit mask is considered sign-extended so any |
9480 | transition must occur within the CONST_INT, not on the boundary. */ | |
b1765bde | 9481 | if (! mask64_operand (x, DImode)) |
a260abc9 DE |
9482 | output_operand_lossage ("invalid %%S value"); |
9483 | ||
0ba1b2ff | 9484 | uval = INT_LOWPART (x); |
a260abc9 | 9485 | |
0ba1b2ff | 9486 | if (uval & 1) /* Clear Left */ |
a260abc9 | 9487 | { |
f099d360 GK |
9488 | #if HOST_BITS_PER_WIDE_INT > 64 |
9489 | uval &= ((unsigned HOST_WIDE_INT) 1 << 64) - 1; | |
9490 | #endif | |
0ba1b2ff | 9491 | i = 64; |
a260abc9 | 9492 | } |
0ba1b2ff | 9493 | else /* Clear Right */ |
a260abc9 | 9494 | { |
0ba1b2ff | 9495 | uval = ~uval; |
f099d360 GK |
9496 | #if HOST_BITS_PER_WIDE_INT > 64 |
9497 | uval &= ((unsigned HOST_WIDE_INT) 1 << 64) - 1; | |
9498 | #endif | |
0ba1b2ff | 9499 | i = 63; |
a260abc9 | 9500 | } |
0ba1b2ff AM |
9501 | while (uval != 0) |
9502 | --i, uval >>= 1; | |
9503 | if (i < 0) | |
9504 | abort (); | |
9505 | fprintf (file, "%d", i); | |
9506 | return; | |
a260abc9 | 9507 | |
a3170dc6 AH |
9508 | case 't': |
9509 | /* Like 'J' but get to the OVERFLOW/UNORDERED bit. */ | |
9510 | if (GET_CODE (x) != REG || GET_MODE (x) != CCmode) | |
9511 | abort (); | |
9512 | ||
9513 | /* Bit 3 is OV bit. */ | |
9514 | i = 4 * (REGNO (x) - CR0_REGNO) + 3; | |
9515 | ||
9516 | /* If we want bit 31, write a shift count of zero, not 32. */ | |
9517 | fprintf (file, "%d", i == 31 ? 0 : i + 1); | |
9518 | return; | |
9519 | ||
cccf3bdc DE |
9520 | case 'T': |
9521 | /* Print the symbolic name of a branch target register. */ | |
9522 | if (GET_CODE (x) != REG || (REGNO (x) != LINK_REGISTER_REGNUM | |
9523 | && REGNO (x) != COUNT_REGISTER_REGNUM)) | |
9524 | output_operand_lossage ("invalid %%T value"); | |
e2c953b6 | 9525 | else if (REGNO (x) == LINK_REGISTER_REGNUM) |
cccf3bdc DE |
9526 | fputs (TARGET_NEW_MNEMONICS ? "lr" : "r", file); |
9527 | else | |
9528 | fputs ("ctr", file); | |
9529 | return; | |
9530 | ||
9854d9ed | 9531 | case 'u': |
802a0058 | 9532 | /* High-order 16 bits of constant for use in unsigned operand. */ |
9854d9ed RK |
9533 | if (! INT_P (x)) |
9534 | output_operand_lossage ("invalid %%u value"); | |
e2c953b6 | 9535 | else |
f676971a | 9536 | fprintf (file, HOST_WIDE_INT_PRINT_HEX, |
e2c953b6 | 9537 | (INT_LOWPART (x) >> 16) & 0xffff); |
9878760c RK |
9538 | return; |
9539 | ||
802a0058 MM |
9540 | case 'v': |
9541 | /* High-order 16 bits of constant for use in signed operand. */ | |
9542 | if (! INT_P (x)) | |
9543 | output_operand_lossage ("invalid %%v value"); | |
e2c953b6 | 9544 | else |
134c32f6 DE |
9545 | fprintf (file, HOST_WIDE_INT_PRINT_HEX, |
9546 | (INT_LOWPART (x) >> 16) & 0xffff); | |
9547 | return; | |
802a0058 | 9548 | |
9854d9ed RK |
9549 | case 'U': |
9550 | /* Print `u' if this has an auto-increment or auto-decrement. */ | |
9551 | if (GET_CODE (x) == MEM | |
9552 | && (GET_CODE (XEXP (x, 0)) == PRE_INC | |
9553 | || GET_CODE (XEXP (x, 0)) == PRE_DEC)) | |
76229ac8 | 9554 | putc ('u', file); |
9854d9ed | 9555 | return; |
9878760c | 9556 | |
e0cd0770 JC |
9557 | case 'V': |
9558 | /* Print the trap code for this operand. */ | |
9559 | switch (GET_CODE (x)) | |
9560 | { | |
9561 | case EQ: | |
9562 | fputs ("eq", file); /* 4 */ | |
9563 | break; | |
9564 | case NE: | |
9565 | fputs ("ne", file); /* 24 */ | |
9566 | break; | |
9567 | case LT: | |
9568 | fputs ("lt", file); /* 16 */ | |
9569 | break; | |
9570 | case LE: | |
9571 | fputs ("le", file); /* 20 */ | |
9572 | break; | |
9573 | case GT: | |
9574 | fputs ("gt", file); /* 8 */ | |
9575 | break; | |
9576 | case GE: | |
9577 | fputs ("ge", file); /* 12 */ | |
9578 | break; | |
9579 | case LTU: | |
9580 | fputs ("llt", file); /* 2 */ | |
9581 | break; | |
9582 | case LEU: | |
9583 | fputs ("lle", file); /* 6 */ | |
9584 | break; | |
9585 | case GTU: | |
9586 | fputs ("lgt", file); /* 1 */ | |
9587 | break; | |
9588 | case GEU: | |
9589 | fputs ("lge", file); /* 5 */ | |
9590 | break; | |
9591 | default: | |
9592 | abort (); | |
9593 | } | |
9594 | break; | |
9595 | ||
9854d9ed RK |
9596 | case 'w': |
9597 | /* If constant, low-order 16 bits of constant, signed. Otherwise, write | |
9598 | normally. */ | |
9599 | if (INT_P (x)) | |
f676971a | 9600 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, |
5f59ecb7 | 9601 | ((INT_LOWPART (x) & 0xffff) ^ 0x8000) - 0x8000); |
9854d9ed RK |
9602 | else |
9603 | print_operand (file, x, 0); | |
9878760c RK |
9604 | return; |
9605 | ||
9854d9ed | 9606 | case 'W': |
e2c953b6 | 9607 | /* MB value for a PowerPC64 rldic operand. */ |
e2c953b6 DE |
9608 | val = (GET_CODE (x) == CONST_INT |
9609 | ? INTVAL (x) : CONST_DOUBLE_HIGH (x)); | |
9610 | ||
9611 | if (val < 0) | |
9612 | i = -1; | |
9854d9ed | 9613 | else |
e2c953b6 DE |
9614 | for (i = 0; i < HOST_BITS_PER_WIDE_INT; i++) |
9615 | if ((val <<= 1) < 0) | |
9616 | break; | |
9617 | ||
9618 | #if HOST_BITS_PER_WIDE_INT == 32 | |
9619 | if (GET_CODE (x) == CONST_INT && i >= 0) | |
9620 | i += 32; /* zero-extend high-part was all 0's */ | |
9621 | else if (GET_CODE (x) == CONST_DOUBLE && i == 32) | |
9622 | { | |
9623 | val = CONST_DOUBLE_LOW (x); | |
9624 | ||
9625 | if (val == 0) | |
a4f6c312 | 9626 | abort (); |
e2c953b6 DE |
9627 | else if (val < 0) |
9628 | --i; | |
9629 | else | |
9630 | for ( ; i < 64; i++) | |
9631 | if ((val <<= 1) < 0) | |
9632 | break; | |
9633 | } | |
9634 | #endif | |
9635 | ||
9636 | fprintf (file, "%d", i + 1); | |
9854d9ed | 9637 | return; |
9878760c | 9638 | |
9854d9ed RK |
9639 | case 'X': |
9640 | if (GET_CODE (x) == MEM | |
4d588c14 | 9641 | && legitimate_indexed_address_p (XEXP (x, 0), 0)) |
76229ac8 | 9642 | putc ('x', file); |
9854d9ed | 9643 | return; |
9878760c | 9644 | |
9854d9ed RK |
9645 | case 'Y': |
9646 | /* Like 'L', for third word of TImode */ | |
9647 | if (GET_CODE (x) == REG) | |
fb5c67a7 | 9648 | fputs (reg_names[REGNO (x) + 2], file); |
9854d9ed | 9649 | else if (GET_CODE (x) == MEM) |
9878760c | 9650 | { |
9854d9ed RK |
9651 | if (GET_CODE (XEXP (x, 0)) == PRE_INC |
9652 | || GET_CODE (XEXP (x, 0)) == PRE_DEC) | |
a54d04b7 | 9653 | output_address (plus_constant (XEXP (XEXP (x, 0), 0), 8)); |
9854d9ed | 9654 | else |
d7624dc0 | 9655 | output_address (XEXP (adjust_address_nv (x, SImode, 8), 0)); |
ba5e43aa | 9656 | if (small_data_operand (x, GET_MODE (x))) |
8fbd2dc7 MM |
9657 | fprintf (file, "@%s(%s)", SMALL_DATA_RELOC, |
9658 | reg_names[SMALL_DATA_REG]); | |
9878760c RK |
9659 | } |
9660 | return; | |
f676971a | 9661 | |
9878760c | 9662 | case 'z': |
b4ac57ab RS |
9663 | /* X is a SYMBOL_REF. Write out the name preceded by a |
9664 | period and without any trailing data in brackets. Used for function | |
4d30c363 MM |
9665 | names. If we are configured for System V (or the embedded ABI) on |
9666 | the PowerPC, do not emit the period, since those systems do not use | |
9667 | TOCs and the like. */ | |
9878760c RK |
9668 | if (GET_CODE (x) != SYMBOL_REF) |
9669 | abort (); | |
9670 | ||
c4ad648e AM |
9671 | /* Mark the decl as referenced so that cgraph will output the |
9672 | function. */ | |
9bf6462a | 9673 | if (SYMBOL_REF_DECL (x)) |
c4ad648e | 9674 | mark_decl_referenced (SYMBOL_REF_DECL (x)); |
9bf6462a | 9675 | |
85b776df | 9676 | /* For macho, check to see if we need a stub. */ |
f9da97f0 AP |
9677 | if (TARGET_MACHO) |
9678 | { | |
9679 | const char *name = XSTR (x, 0); | |
a031e781 | 9680 | #if TARGET_MACHO |
3b48085e | 9681 | if (MACHOPIC_INDIRECT |
11abc112 MM |
9682 | && machopic_classify_symbol (x) == MACHOPIC_UNDEFINED_FUNCTION) |
9683 | name = machopic_indirection_name (x, /*stub_p=*/true); | |
f9da97f0 AP |
9684 | #endif |
9685 | assemble_name (file, name); | |
9686 | } | |
85b776df | 9687 | else if (!DOT_SYMBOLS) |
9739c90c | 9688 | assemble_name (file, XSTR (x, 0)); |
85b776df AM |
9689 | else |
9690 | rs6000_output_function_entry (file, XSTR (x, 0)); | |
9878760c RK |
9691 | return; |
9692 | ||
9854d9ed RK |
9693 | case 'Z': |
9694 | /* Like 'L', for last word of TImode. */ | |
9695 | if (GET_CODE (x) == REG) | |
fb5c67a7 | 9696 | fputs (reg_names[REGNO (x) + 3], file); |
9854d9ed RK |
9697 | else if (GET_CODE (x) == MEM) |
9698 | { | |
9699 | if (GET_CODE (XEXP (x, 0)) == PRE_INC | |
9700 | || GET_CODE (XEXP (x, 0)) == PRE_DEC) | |
a54d04b7 | 9701 | output_address (plus_constant (XEXP (XEXP (x, 0), 0), 12)); |
9854d9ed | 9702 | else |
d7624dc0 | 9703 | output_address (XEXP (adjust_address_nv (x, SImode, 12), 0)); |
ba5e43aa | 9704 | if (small_data_operand (x, GET_MODE (x))) |
8fbd2dc7 MM |
9705 | fprintf (file, "@%s(%s)", SMALL_DATA_RELOC, |
9706 | reg_names[SMALL_DATA_REG]); | |
9854d9ed | 9707 | } |
5c23c401 | 9708 | return; |
0ac081f6 | 9709 | |
a3170dc6 | 9710 | /* Print AltiVec or SPE memory operand. */ |
0ac081f6 AH |
9711 | case 'y': |
9712 | { | |
9713 | rtx tmp; | |
9714 | ||
9715 | if (GET_CODE (x) != MEM) | |
9716 | abort (); | |
9717 | ||
9718 | tmp = XEXP (x, 0); | |
9719 | ||
993f19a8 | 9720 | if (TARGET_E500) |
a3170dc6 AH |
9721 | { |
9722 | /* Handle [reg]. */ | |
9723 | if (GET_CODE (tmp) == REG) | |
9724 | { | |
9725 | fprintf (file, "0(%s)", reg_names[REGNO (tmp)]); | |
9726 | break; | |
9727 | } | |
9728 | /* Handle [reg+UIMM]. */ | |
9729 | else if (GET_CODE (tmp) == PLUS && | |
9730 | GET_CODE (XEXP (tmp, 1)) == CONST_INT) | |
9731 | { | |
9732 | int x; | |
9733 | ||
9734 | if (GET_CODE (XEXP (tmp, 0)) != REG) | |
9735 | abort (); | |
9736 | ||
9737 | x = INTVAL (XEXP (tmp, 1)); | |
9738 | fprintf (file, "%d(%s)", x, reg_names[REGNO (XEXP (tmp, 0))]); | |
9739 | break; | |
9740 | } | |
9741 | ||
9742 | /* Fall through. Must be [reg+reg]. */ | |
9743 | } | |
850e8d3d DN |
9744 | if (TARGET_ALTIVEC |
9745 | && GET_CODE (tmp) == AND | |
9746 | && GET_CODE (XEXP (tmp, 1)) == CONST_INT | |
9747 | && INTVAL (XEXP (tmp, 1)) == -16) | |
9748 | tmp = XEXP (tmp, 0); | |
0ac081f6 | 9749 | if (GET_CODE (tmp) == REG) |
c62f2db5 | 9750 | fprintf (file, "0,%s", reg_names[REGNO (tmp)]); |
0ac081f6 AH |
9751 | else if (GET_CODE (tmp) == PLUS && GET_CODE (XEXP (tmp, 1)) == REG) |
9752 | { | |
9753 | if (REGNO (XEXP (tmp, 0)) == 0) | |
9754 | fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 1)) ], | |
9755 | reg_names[ REGNO (XEXP (tmp, 0)) ]); | |
9756 | else | |
9757 | fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 0)) ], | |
9758 | reg_names[ REGNO (XEXP (tmp, 1)) ]); | |
9759 | } | |
9760 | else | |
9761 | abort (); | |
9762 | break; | |
9763 | } | |
f676971a | 9764 | |
9878760c RK |
9765 | case 0: |
9766 | if (GET_CODE (x) == REG) | |
9767 | fprintf (file, "%s", reg_names[REGNO (x)]); | |
9768 | else if (GET_CODE (x) == MEM) | |
9769 | { | |
9770 | /* We need to handle PRE_INC and PRE_DEC here, since we need to | |
9771 | know the width from the mode. */ | |
9772 | if (GET_CODE (XEXP (x, 0)) == PRE_INC) | |
79ba6d34 MM |
9773 | fprintf (file, "%d(%s)", GET_MODE_SIZE (GET_MODE (x)), |
9774 | reg_names[REGNO (XEXP (XEXP (x, 0), 0))]); | |
9878760c | 9775 | else if (GET_CODE (XEXP (x, 0)) == PRE_DEC) |
79ba6d34 MM |
9776 | fprintf (file, "%d(%s)", - GET_MODE_SIZE (GET_MODE (x)), |
9777 | reg_names[REGNO (XEXP (XEXP (x, 0), 0))]); | |
9878760c | 9778 | else |
a54d04b7 | 9779 | output_address (XEXP (x, 0)); |
9878760c RK |
9780 | } |
9781 | else | |
a54d04b7 | 9782 | output_addr_const (file, x); |
a85d226b | 9783 | return; |
9878760c | 9784 | |
c4501e62 JJ |
9785 | case '&': |
9786 | assemble_name (file, rs6000_get_some_local_dynamic_name ()); | |
9787 | return; | |
9788 | ||
9878760c RK |
9789 | default: |
9790 | output_operand_lossage ("invalid %%xn code"); | |
9791 | } | |
9792 | } | |
9793 | \f | |
9794 | /* Print the address of an operand. */ | |
9795 | ||
9796 | void | |
a2369ed3 | 9797 | print_operand_address (FILE *file, rtx x) |
9878760c RK |
9798 | { |
9799 | if (GET_CODE (x) == REG) | |
4697a36c | 9800 | fprintf (file, "0(%s)", reg_names[ REGNO (x) ]); |
9ebbca7d GK |
9801 | else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST |
9802 | || GET_CODE (x) == LABEL_REF) | |
9878760c RK |
9803 | { |
9804 | output_addr_const (file, x); | |
ba5e43aa | 9805 | if (small_data_operand (x, GET_MODE (x))) |
8fbd2dc7 MM |
9806 | fprintf (file, "@%s(%s)", SMALL_DATA_RELOC, |
9807 | reg_names[SMALL_DATA_REG]); | |
9ebbca7d | 9808 | else if (TARGET_TOC) |
a4f6c312 | 9809 | abort (); |
9878760c RK |
9810 | } |
9811 | else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == REG) | |
9812 | { | |
9813 | if (REGNO (XEXP (x, 0)) == 0) | |
4697a36c MM |
9814 | fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 1)) ], |
9815 | reg_names[ REGNO (XEXP (x, 0)) ]); | |
9878760c | 9816 | else |
4697a36c MM |
9817 | fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 0)) ], |
9818 | reg_names[ REGNO (XEXP (x, 1)) ]); | |
9878760c RK |
9819 | } |
9820 | else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT) | |
4a0a75dd KG |
9821 | fprintf (file, HOST_WIDE_INT_PRINT_DEC "(%s)", |
9822 | INTVAL (XEXP (x, 1)), reg_names[ REGNO (XEXP (x, 0)) ]); | |
3cb999d8 DE |
9823 | #if TARGET_ELF |
9824 | else if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 0)) == REG | |
c4ad648e | 9825 | && CONSTANT_P (XEXP (x, 1))) |
4697a36c MM |
9826 | { |
9827 | output_addr_const (file, XEXP (x, 1)); | |
9828 | fprintf (file, "@l(%s)", reg_names[ REGNO (XEXP (x, 0)) ]); | |
9829 | } | |
c859cda6 DJ |
9830 | #endif |
9831 | #if TARGET_MACHO | |
9832 | else if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 0)) == REG | |
c4ad648e | 9833 | && CONSTANT_P (XEXP (x, 1))) |
c859cda6 DJ |
9834 | { |
9835 | fprintf (file, "lo16("); | |
9836 | output_addr_const (file, XEXP (x, 1)); | |
9837 | fprintf (file, ")(%s)", reg_names[ REGNO (XEXP (x, 0)) ]); | |
9838 | } | |
3cb999d8 | 9839 | #endif |
4d588c14 | 9840 | else if (legitimate_constant_pool_address_p (x)) |
9ebbca7d | 9841 | { |
2bfcf297 | 9842 | if (TARGET_AIX && (!TARGET_ELF || !TARGET_MINIMAL_TOC)) |
9ebbca7d | 9843 | { |
2bfcf297 DB |
9844 | rtx contains_minus = XEXP (x, 1); |
9845 | rtx minus, symref; | |
9846 | const char *name; | |
f676971a | 9847 | |
9ebbca7d | 9848 | /* Find the (minus (sym) (toc)) buried in X, and temporarily |
a4f6c312 | 9849 | turn it into (sym) for output_addr_const. */ |
9ebbca7d GK |
9850 | while (GET_CODE (XEXP (contains_minus, 0)) != MINUS) |
9851 | contains_minus = XEXP (contains_minus, 0); | |
9852 | ||
2bfcf297 DB |
9853 | minus = XEXP (contains_minus, 0); |
9854 | symref = XEXP (minus, 0); | |
9855 | XEXP (contains_minus, 0) = symref; | |
9856 | if (TARGET_ELF) | |
9857 | { | |
9858 | char *newname; | |
9859 | ||
9860 | name = XSTR (symref, 0); | |
9861 | newname = alloca (strlen (name) + sizeof ("@toc")); | |
9862 | strcpy (newname, name); | |
9863 | strcat (newname, "@toc"); | |
9864 | XSTR (symref, 0) = newname; | |
9865 | } | |
9866 | output_addr_const (file, XEXP (x, 1)); | |
9867 | if (TARGET_ELF) | |
9868 | XSTR (symref, 0) = name; | |
9ebbca7d GK |
9869 | XEXP (contains_minus, 0) = minus; |
9870 | } | |
9871 | else | |
9872 | output_addr_const (file, XEXP (x, 1)); | |
9873 | ||
9874 | fprintf (file, "(%s)", reg_names[REGNO (XEXP (x, 0))]); | |
9875 | } | |
9878760c RK |
9876 | else |
9877 | abort (); | |
9878 | } | |
9879 | \f | |
88cad84b | 9880 | /* Target hook for assembling integer objects. The PowerPC version has |
301d03af RS |
9881 | to handle fixup entries for relocatable code if RELOCATABLE_NEEDS_FIXUP |
9882 | is defined. It also needs to handle DI-mode objects on 64-bit | |
9883 | targets. */ | |
9884 | ||
9885 | static bool | |
a2369ed3 | 9886 | rs6000_assemble_integer (rtx x, unsigned int size, int aligned_p) |
301d03af | 9887 | { |
f4f4921e | 9888 | #ifdef RELOCATABLE_NEEDS_FIXUP |
301d03af | 9889 | /* Special handling for SI values. */ |
84dcde01 | 9890 | if (RELOCATABLE_NEEDS_FIXUP && size == 4 && aligned_p) |
301d03af | 9891 | { |
a2369ed3 | 9892 | extern int in_toc_section (void); |
301d03af | 9893 | static int recurse = 0; |
f676971a | 9894 | |
301d03af RS |
9895 | /* For -mrelocatable, we mark all addresses that need to be fixed up |
9896 | in the .fixup section. */ | |
9897 | if (TARGET_RELOCATABLE | |
9898 | && !in_toc_section () | |
9899 | && !in_text_section () | |
642af3be | 9900 | && !in_unlikely_text_section () |
301d03af RS |
9901 | && !recurse |
9902 | && GET_CODE (x) != CONST_INT | |
9903 | && GET_CODE (x) != CONST_DOUBLE | |
9904 | && CONSTANT_P (x)) | |
9905 | { | |
9906 | char buf[256]; | |
9907 | ||
9908 | recurse = 1; | |
9909 | ASM_GENERATE_INTERNAL_LABEL (buf, "LCP", fixuplabelno); | |
9910 | fixuplabelno++; | |
9911 | ASM_OUTPUT_LABEL (asm_out_file, buf); | |
9912 | fprintf (asm_out_file, "\t.long\t("); | |
9913 | output_addr_const (asm_out_file, x); | |
9914 | fprintf (asm_out_file, ")@fixup\n"); | |
9915 | fprintf (asm_out_file, "\t.section\t\".fixup\",\"aw\"\n"); | |
9916 | ASM_OUTPUT_ALIGN (asm_out_file, 2); | |
9917 | fprintf (asm_out_file, "\t.long\t"); | |
9918 | assemble_name (asm_out_file, buf); | |
9919 | fprintf (asm_out_file, "\n\t.previous\n"); | |
9920 | recurse = 0; | |
9921 | return true; | |
9922 | } | |
9923 | /* Remove initial .'s to turn a -mcall-aixdesc function | |
9924 | address into the address of the descriptor, not the function | |
9925 | itself. */ | |
9926 | else if (GET_CODE (x) == SYMBOL_REF | |
9927 | && XSTR (x, 0)[0] == '.' | |
9928 | && DEFAULT_ABI == ABI_AIX) | |
9929 | { | |
9930 | const char *name = XSTR (x, 0); | |
9931 | while (*name == '.') | |
9932 | name++; | |
9933 | ||
9934 | fprintf (asm_out_file, "\t.long\t%s\n", name); | |
9935 | return true; | |
9936 | } | |
9937 | } | |
f4f4921e | 9938 | #endif /* RELOCATABLE_NEEDS_FIXUP */ |
301d03af RS |
9939 | return default_assemble_integer (x, size, aligned_p); |
9940 | } | |
93638d7a AM |
9941 | |
9942 | #ifdef HAVE_GAS_HIDDEN | |
9943 | /* Emit an assembler directive to set symbol visibility for DECL to | |
9944 | VISIBILITY_TYPE. */ | |
9945 | ||
5add3202 | 9946 | static void |
a2369ed3 | 9947 | rs6000_assemble_visibility (tree decl, int vis) |
93638d7a | 9948 | { |
93638d7a AM |
9949 | /* Functions need to have their entry point symbol visibility set as |
9950 | well as their descriptor symbol visibility. */ | |
85b776df AM |
9951 | if (DEFAULT_ABI == ABI_AIX |
9952 | && DOT_SYMBOLS | |
9953 | && TREE_CODE (decl) == FUNCTION_DECL) | |
93638d7a | 9954 | { |
25fdb4dc | 9955 | static const char * const visibility_types[] = { |
c4ad648e | 9956 | NULL, "internal", "hidden", "protected" |
25fdb4dc RH |
9957 | }; |
9958 | ||
9959 | const char *name, *type; | |
93638d7a AM |
9960 | |
9961 | name = ((* targetm.strip_name_encoding) | |
9962 | (IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl)))); | |
25fdb4dc | 9963 | type = visibility_types[vis]; |
93638d7a | 9964 | |
25fdb4dc RH |
9965 | fprintf (asm_out_file, "\t.%s\t%s\n", type, name); |
9966 | fprintf (asm_out_file, "\t.%s\t.%s\n", type, name); | |
93638d7a | 9967 | } |
25fdb4dc RH |
9968 | else |
9969 | default_assemble_visibility (decl, vis); | |
93638d7a AM |
9970 | } |
9971 | #endif | |
301d03af | 9972 | \f |
39a10a29 | 9973 | enum rtx_code |
a2369ed3 | 9974 | rs6000_reverse_condition (enum machine_mode mode, enum rtx_code code) |
39a10a29 GK |
9975 | { |
9976 | /* Reversal of FP compares takes care -- an ordered compare | |
9977 | becomes an unordered compare and vice versa. */ | |
f676971a | 9978 | if (mode == CCFPmode |
bc9ec0e0 GK |
9979 | && (!flag_finite_math_only |
9980 | || code == UNLT || code == UNLE || code == UNGT || code == UNGE | |
9981 | || code == UNEQ || code == LTGT)) | |
bab6226b | 9982 | return reverse_condition_maybe_unordered (code); |
39a10a29 | 9983 | else |
bab6226b | 9984 | return reverse_condition (code); |
39a10a29 GK |
9985 | } |
9986 | ||
39a10a29 GK |
9987 | /* Generate a compare for CODE. Return a brand-new rtx that |
9988 | represents the result of the compare. */ | |
a4f6c312 | 9989 | |
39a10a29 | 9990 | static rtx |
a2369ed3 | 9991 | rs6000_generate_compare (enum rtx_code code) |
39a10a29 GK |
9992 | { |
9993 | enum machine_mode comp_mode; | |
9994 | rtx compare_result; | |
9995 | ||
9996 | if (rs6000_compare_fp_p) | |
9997 | comp_mode = CCFPmode; | |
9998 | else if (code == GTU || code == LTU | |
c4ad648e | 9999 | || code == GEU || code == LEU) |
39a10a29 | 10000 | comp_mode = CCUNSmode; |
60934f9c NS |
10001 | else if ((code == EQ || code == NE) |
10002 | && GET_CODE (rs6000_compare_op0) == SUBREG | |
10003 | && GET_CODE (rs6000_compare_op1) == SUBREG | |
10004 | && SUBREG_PROMOTED_UNSIGNED_P (rs6000_compare_op0) | |
10005 | && SUBREG_PROMOTED_UNSIGNED_P (rs6000_compare_op1)) | |
10006 | /* These are unsigned values, perhaps there will be a later | |
10007 | ordering compare that can be shared with this one. | |
10008 | Unfortunately we cannot detect the signedness of the operands | |
10009 | for non-subregs. */ | |
10010 | comp_mode = CCUNSmode; | |
39a10a29 GK |
10011 | else |
10012 | comp_mode = CCmode; | |
10013 | ||
10014 | /* First, the compare. */ | |
10015 | compare_result = gen_reg_rtx (comp_mode); | |
a3170dc6 AH |
10016 | |
10017 | /* SPE FP compare instructions on the GPRs. Yuck! */ | |
993f19a8 AH |
10018 | if ((TARGET_E500 && !TARGET_FPRS && TARGET_HARD_FLOAT) |
10019 | && rs6000_compare_fp_p) | |
a3170dc6 AH |
10020 | { |
10021 | rtx cmp, or1, or2, or_result, compare_result2; | |
4d4cbc0e AH |
10022 | enum machine_mode op_mode = GET_MODE (rs6000_compare_op0); |
10023 | ||
10024 | if (op_mode == VOIDmode) | |
10025 | op_mode = GET_MODE (rs6000_compare_op1); | |
a3170dc6 | 10026 | |
423c1189 AH |
10027 | /* Note: The E500 comparison instructions set the GT bit (x + |
10028 | 1), on success. This explains the mess. */ | |
10029 | ||
a3170dc6 AH |
10030 | switch (code) |
10031 | { | |
423c1189 | 10032 | case EQ: case UNEQ: case NE: case LTGT: |
4d4cbc0e | 10033 | if (op_mode == SFmode) |
5ca18999 | 10034 | cmp = flag_unsafe_math_optimizations |
4d4cbc0e AH |
10035 | ? gen_tstsfeq_gpr (compare_result, rs6000_compare_op0, |
10036 | rs6000_compare_op1) | |
10037 | : gen_cmpsfeq_gpr (compare_result, rs6000_compare_op0, | |
10038 | rs6000_compare_op1); | |
10039 | else if (op_mode == DFmode) | |
5ca18999 | 10040 | cmp = flag_unsafe_math_optimizations |
4d4cbc0e AH |
10041 | ? gen_tstdfeq_gpr (compare_result, rs6000_compare_op0, |
10042 | rs6000_compare_op1) | |
10043 | : gen_cmpdfeq_gpr (compare_result, rs6000_compare_op0, | |
10044 | rs6000_compare_op1); | |
10045 | else abort (); | |
a3170dc6 | 10046 | break; |
423c1189 | 10047 | case GT: case GTU: case UNGT: case UNGE: case GE: case GEU: |
4d4cbc0e | 10048 | if (op_mode == SFmode) |
5ca18999 | 10049 | cmp = flag_unsafe_math_optimizations |
4d4cbc0e AH |
10050 | ? gen_tstsfgt_gpr (compare_result, rs6000_compare_op0, |
10051 | rs6000_compare_op1) | |
10052 | : gen_cmpsfgt_gpr (compare_result, rs6000_compare_op0, | |
10053 | rs6000_compare_op1); | |
10054 | else if (op_mode == DFmode) | |
5ca18999 | 10055 | cmp = flag_unsafe_math_optimizations |
4d4cbc0e AH |
10056 | ? gen_tstdfgt_gpr (compare_result, rs6000_compare_op0, |
10057 | rs6000_compare_op1) | |
10058 | : gen_cmpdfgt_gpr (compare_result, rs6000_compare_op0, | |
10059 | rs6000_compare_op1); | |
10060 | else abort (); | |
a3170dc6 | 10061 | break; |
423c1189 | 10062 | case LT: case LTU: case UNLT: case UNLE: case LE: case LEU: |
4d4cbc0e | 10063 | if (op_mode == SFmode) |
5ca18999 | 10064 | cmp = flag_unsafe_math_optimizations |
4d4cbc0e AH |
10065 | ? gen_tstsflt_gpr (compare_result, rs6000_compare_op0, |
10066 | rs6000_compare_op1) | |
10067 | : gen_cmpsflt_gpr (compare_result, rs6000_compare_op0, | |
10068 | rs6000_compare_op1); | |
10069 | else if (op_mode == DFmode) | |
5ca18999 | 10070 | cmp = flag_unsafe_math_optimizations |
4d4cbc0e AH |
10071 | ? gen_tstdflt_gpr (compare_result, rs6000_compare_op0, |
10072 | rs6000_compare_op1) | |
10073 | : gen_cmpdflt_gpr (compare_result, rs6000_compare_op0, | |
10074 | rs6000_compare_op1); | |
10075 | else abort (); | |
a3170dc6 | 10076 | break; |
4d4cbc0e AH |
10077 | default: |
10078 | abort (); | |
a3170dc6 AH |
10079 | } |
10080 | ||
10081 | /* Synthesize LE and GE from LT/GT || EQ. */ | |
10082 | if (code == LE || code == GE || code == LEU || code == GEU) | |
10083 | { | |
a3170dc6 AH |
10084 | emit_insn (cmp); |
10085 | ||
10086 | switch (code) | |
10087 | { | |
10088 | case LE: code = LT; break; | |
10089 | case GE: code = GT; break; | |
10090 | case LEU: code = LT; break; | |
10091 | case GEU: code = GT; break; | |
10092 | default: abort (); | |
10093 | } | |
10094 | ||
10095 | or1 = gen_reg_rtx (SImode); | |
10096 | or2 = gen_reg_rtx (SImode); | |
10097 | or_result = gen_reg_rtx (CCEQmode); | |
10098 | compare_result2 = gen_reg_rtx (CCFPmode); | |
10099 | ||
10100 | /* Do the EQ. */ | |
4d4cbc0e | 10101 | if (op_mode == SFmode) |
5ca18999 | 10102 | cmp = flag_unsafe_math_optimizations |
4d4cbc0e AH |
10103 | ? gen_tstsfeq_gpr (compare_result2, rs6000_compare_op0, |
10104 | rs6000_compare_op1) | |
10105 | : gen_cmpsfeq_gpr (compare_result2, rs6000_compare_op0, | |
10106 | rs6000_compare_op1); | |
10107 | else if (op_mode == DFmode) | |
5ca18999 | 10108 | cmp = flag_unsafe_math_optimizations |
4d4cbc0e AH |
10109 | ? gen_tstdfeq_gpr (compare_result2, rs6000_compare_op0, |
10110 | rs6000_compare_op1) | |
10111 | : gen_cmpdfeq_gpr (compare_result2, rs6000_compare_op0, | |
10112 | rs6000_compare_op1); | |
10113 | else abort (); | |
a3170dc6 AH |
10114 | emit_insn (cmp); |
10115 | ||
423c1189 AH |
10116 | or1 = gen_rtx_GT (SImode, compare_result, const0_rtx); |
10117 | or2 = gen_rtx_GT (SImode, compare_result2, const0_rtx); | |
a3170dc6 AH |
10118 | |
10119 | /* OR them together. */ | |
10120 | cmp = gen_rtx_SET (VOIDmode, or_result, | |
10121 | gen_rtx_COMPARE (CCEQmode, | |
10122 | gen_rtx_IOR (SImode, or1, or2), | |
10123 | const_true_rtx)); | |
10124 | compare_result = or_result; | |
10125 | code = EQ; | |
10126 | } | |
10127 | else | |
10128 | { | |
a3170dc6 | 10129 | if (code == NE || code == LTGT) |
a3170dc6 | 10130 | code = NE; |
423c1189 AH |
10131 | else |
10132 | code = EQ; | |
a3170dc6 AH |
10133 | } |
10134 | ||
10135 | emit_insn (cmp); | |
10136 | } | |
10137 | else | |
de17c25f DE |
10138 | { |
10139 | /* Generate XLC-compatible TFmode compare as PARALLEL with extra | |
10140 | CLOBBERs to match cmptf_internal2 pattern. */ | |
10141 | if (comp_mode == CCFPmode && TARGET_XL_COMPAT | |
10142 | && GET_MODE (rs6000_compare_op0) == TFmode | |
10143 | && (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) | |
10144 | && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128) | |
10145 | emit_insn (gen_rtx_PARALLEL (VOIDmode, | |
10146 | gen_rtvec (9, | |
10147 | gen_rtx_SET (VOIDmode, | |
10148 | compare_result, | |
10149 | gen_rtx_COMPARE (comp_mode, | |
10150 | rs6000_compare_op0, | |
10151 | rs6000_compare_op1)), | |
10152 | gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)), | |
10153 | gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)), | |
10154 | gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)), | |
10155 | gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)), | |
10156 | gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)), | |
10157 | gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)), | |
10158 | gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)), | |
10159 | gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode))))); | |
10160 | else | |
10161 | emit_insn (gen_rtx_SET (VOIDmode, compare_result, | |
10162 | gen_rtx_COMPARE (comp_mode, | |
10163 | rs6000_compare_op0, | |
10164 | rs6000_compare_op1))); | |
10165 | } | |
f676971a | 10166 | |
ca5adc63 | 10167 | /* Some kinds of FP comparisons need an OR operation; |
5ca18999 | 10168 | under flag_unsafe_math_optimizations we don't bother. */ |
39a10a29 | 10169 | if (rs6000_compare_fp_p |
5ca18999 | 10170 | && ! flag_unsafe_math_optimizations |
993f19a8 | 10171 | && ! (TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS) |
39a10a29 GK |
10172 | && (code == LE || code == GE |
10173 | || code == UNEQ || code == LTGT | |
10174 | || code == UNGT || code == UNLT)) | |
10175 | { | |
10176 | enum rtx_code or1, or2; | |
10177 | rtx or1_rtx, or2_rtx, compare2_rtx; | |
10178 | rtx or_result = gen_reg_rtx (CCEQmode); | |
f676971a | 10179 | |
39a10a29 GK |
10180 | switch (code) |
10181 | { | |
10182 | case LE: or1 = LT; or2 = EQ; break; | |
10183 | case GE: or1 = GT; or2 = EQ; break; | |
10184 | case UNEQ: or1 = UNORDERED; or2 = EQ; break; | |
10185 | case LTGT: or1 = LT; or2 = GT; break; | |
10186 | case UNGT: or1 = UNORDERED; or2 = GT; break; | |
10187 | case UNLT: or1 = UNORDERED; or2 = LT; break; | |
10188 | default: abort (); | |
10189 | } | |
10190 | validate_condition_mode (or1, comp_mode); | |
10191 | validate_condition_mode (or2, comp_mode); | |
1c563bed KH |
10192 | or1_rtx = gen_rtx_fmt_ee (or1, SImode, compare_result, const0_rtx); |
10193 | or2_rtx = gen_rtx_fmt_ee (or2, SImode, compare_result, const0_rtx); | |
39a10a29 GK |
10194 | compare2_rtx = gen_rtx_COMPARE (CCEQmode, |
10195 | gen_rtx_IOR (SImode, or1_rtx, or2_rtx), | |
10196 | const_true_rtx); | |
10197 | emit_insn (gen_rtx_SET (VOIDmode, or_result, compare2_rtx)); | |
10198 | ||
10199 | compare_result = or_result; | |
10200 | code = EQ; | |
10201 | } | |
10202 | ||
10203 | validate_condition_mode (code, GET_MODE (compare_result)); | |
f676971a | 10204 | |
1c563bed | 10205 | return gen_rtx_fmt_ee (code, VOIDmode, compare_result, const0_rtx); |
39a10a29 GK |
10206 | } |
10207 | ||
10208 | ||
10209 | /* Emit the RTL for an sCOND pattern. */ | |
10210 | ||
10211 | void | |
a2369ed3 | 10212 | rs6000_emit_sCOND (enum rtx_code code, rtx result) |
39a10a29 GK |
10213 | { |
10214 | rtx condition_rtx; | |
10215 | enum machine_mode op_mode; | |
b7053a3f | 10216 | enum rtx_code cond_code; |
39a10a29 GK |
10217 | |
10218 | condition_rtx = rs6000_generate_compare (code); | |
b7053a3f GK |
10219 | cond_code = GET_CODE (condition_rtx); |
10220 | ||
423c1189 AH |
10221 | if (TARGET_E500 && rs6000_compare_fp_p |
10222 | && !TARGET_FPRS && TARGET_HARD_FLOAT) | |
10223 | { | |
10224 | rtx t; | |
10225 | ||
10226 | PUT_MODE (condition_rtx, SImode); | |
10227 | t = XEXP (condition_rtx, 0); | |
10228 | ||
10229 | if (cond_code != NE && cond_code != EQ) | |
10230 | abort (); | |
10231 | ||
10232 | if (cond_code == NE) | |
6b1fedc3 | 10233 | emit_insn (gen_e500_flip_eq_bit (t, t)); |
423c1189 | 10234 | |
6b1fedc3 | 10235 | emit_insn (gen_move_from_CR_eq_bit (result, t)); |
423c1189 AH |
10236 | return; |
10237 | } | |
10238 | ||
b7053a3f GK |
10239 | if (cond_code == NE |
10240 | || cond_code == GE || cond_code == LE | |
10241 | || cond_code == GEU || cond_code == LEU | |
10242 | || cond_code == ORDERED || cond_code == UNGE || cond_code == UNLE) | |
10243 | { | |
10244 | rtx not_result = gen_reg_rtx (CCEQmode); | |
10245 | rtx not_op, rev_cond_rtx; | |
10246 | enum machine_mode cc_mode; | |
f676971a | 10247 | |
b7053a3f GK |
10248 | cc_mode = GET_MODE (XEXP (condition_rtx, 0)); |
10249 | ||
1c563bed | 10250 | rev_cond_rtx = gen_rtx_fmt_ee (rs6000_reverse_condition (cc_mode, cond_code), |
0f4c242b | 10251 | SImode, XEXP (condition_rtx, 0), const0_rtx); |
b7053a3f GK |
10252 | not_op = gen_rtx_COMPARE (CCEQmode, rev_cond_rtx, const0_rtx); |
10253 | emit_insn (gen_rtx_SET (VOIDmode, not_result, not_op)); | |
10254 | condition_rtx = gen_rtx_EQ (VOIDmode, not_result, const0_rtx); | |
10255 | } | |
39a10a29 GK |
10256 | |
10257 | op_mode = GET_MODE (rs6000_compare_op0); | |
10258 | if (op_mode == VOIDmode) | |
10259 | op_mode = GET_MODE (rs6000_compare_op1); | |
10260 | ||
10261 | if (TARGET_POWERPC64 && (op_mode == DImode || rs6000_compare_fp_p)) | |
10262 | { | |
10263 | PUT_MODE (condition_rtx, DImode); | |
10264 | convert_move (result, condition_rtx, 0); | |
10265 | } | |
10266 | else | |
10267 | { | |
10268 | PUT_MODE (condition_rtx, SImode); | |
10269 | emit_insn (gen_rtx_SET (VOIDmode, result, condition_rtx)); | |
10270 | } | |
10271 | } | |
10272 | ||
39a10a29 GK |
10273 | /* Emit a branch of kind CODE to location LOC. */ |
10274 | ||
10275 | void | |
a2369ed3 | 10276 | rs6000_emit_cbranch (enum rtx_code code, rtx loc) |
39a10a29 GK |
10277 | { |
10278 | rtx condition_rtx, loc_ref; | |
10279 | ||
10280 | condition_rtx = rs6000_generate_compare (code); | |
10281 | loc_ref = gen_rtx_LABEL_REF (VOIDmode, loc); | |
10282 | emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, | |
10283 | gen_rtx_IF_THEN_ELSE (VOIDmode, condition_rtx, | |
10284 | loc_ref, pc_rtx))); | |
10285 | } | |
10286 | ||
12a4e8c5 GK |
10287 | /* Return the string to output a conditional branch to LABEL, which is |
10288 | the operand number of the label, or -1 if the branch is really a | |
f676971a | 10289 | conditional return. |
12a4e8c5 GK |
10290 | |
10291 | OP is the conditional expression. XEXP (OP, 0) is assumed to be a | |
10292 | condition code register and its mode specifies what kind of | |
10293 | comparison we made. | |
10294 | ||
a0ab749a | 10295 | REVERSED is nonzero if we should reverse the sense of the comparison. |
12a4e8c5 GK |
10296 | |
10297 | INSN is the insn. */ | |
10298 | ||
10299 | char * | |
a2369ed3 | 10300 | output_cbranch (rtx op, const char *label, int reversed, rtx insn) |
12a4e8c5 GK |
10301 | { |
10302 | static char string[64]; | |
10303 | enum rtx_code code = GET_CODE (op); | |
10304 | rtx cc_reg = XEXP (op, 0); | |
10305 | enum machine_mode mode = GET_MODE (cc_reg); | |
10306 | int cc_regno = REGNO (cc_reg) - CR0_REGNO; | |
39a10a29 | 10307 | int need_longbranch = label != NULL && get_attr_length (insn) == 8; |
12a4e8c5 GK |
10308 | int really_reversed = reversed ^ need_longbranch; |
10309 | char *s = string; | |
10310 | const char *ccode; | |
10311 | const char *pred; | |
10312 | rtx note; | |
10313 | ||
39a10a29 GK |
10314 | validate_condition_mode (code, mode); |
10315 | ||
10316 | /* Work out which way this really branches. We could use | |
10317 | reverse_condition_maybe_unordered here always but this | |
10318 | makes the resulting assembler clearer. */ | |
12a4e8c5 | 10319 | if (really_reversed) |
de40e1df DJ |
10320 | { |
10321 | /* Reversal of FP compares takes care -- an ordered compare | |
10322 | becomes an unordered compare and vice versa. */ | |
10323 | if (mode == CCFPmode) | |
10324 | code = reverse_condition_maybe_unordered (code); | |
10325 | else | |
10326 | code = reverse_condition (code); | |
10327 | } | |
12a4e8c5 | 10328 | |
993f19a8 | 10329 | if ((TARGET_E500 && !TARGET_FPRS && TARGET_HARD_FLOAT) && mode == CCFPmode) |
a3170dc6 AH |
10330 | { |
10331 | /* The efscmp/tst* instructions twiddle bit 2, which maps nicely | |
10332 | to the GT bit. */ | |
10333 | if (code == EQ) | |
10334 | /* Opposite of GT. */ | |
a3170dc6 | 10335 | code = GT; |
423c1189 AH |
10336 | else if (code == NE) |
10337 | code = UNLE; | |
a3170dc6 AH |
10338 | else |
10339 | abort (); | |
10340 | } | |
10341 | ||
39a10a29 | 10342 | switch (code) |
12a4e8c5 GK |
10343 | { |
10344 | /* Not all of these are actually distinct opcodes, but | |
10345 | we distinguish them for clarity of the resulting assembler. */ | |
50a0b056 GK |
10346 | case NE: case LTGT: |
10347 | ccode = "ne"; break; | |
10348 | case EQ: case UNEQ: | |
10349 | ccode = "eq"; break; | |
f676971a | 10350 | case GE: case GEU: |
50a0b056 | 10351 | ccode = "ge"; break; |
f676971a | 10352 | case GT: case GTU: case UNGT: |
50a0b056 | 10353 | ccode = "gt"; break; |
f676971a | 10354 | case LE: case LEU: |
50a0b056 | 10355 | ccode = "le"; break; |
f676971a | 10356 | case LT: case LTU: case UNLT: |
50a0b056 | 10357 | ccode = "lt"; break; |
12a4e8c5 GK |
10358 | case UNORDERED: ccode = "un"; break; |
10359 | case ORDERED: ccode = "nu"; break; | |
10360 | case UNGE: ccode = "nl"; break; | |
10361 | case UNLE: ccode = "ng"; break; | |
10362 | default: | |
a4f6c312 | 10363 | abort (); |
12a4e8c5 | 10364 | } |
f676971a EC |
10365 | |
10366 | /* Maybe we have a guess as to how likely the branch is. | |
94a54f47 | 10367 | The old mnemonics don't have a way to specify this information. */ |
f4857b9b | 10368 | pred = ""; |
12a4e8c5 GK |
10369 | note = find_reg_note (insn, REG_BR_PROB, NULL_RTX); |
10370 | if (note != NULL_RTX) | |
10371 | { | |
10372 | /* PROB is the difference from 50%. */ | |
10373 | int prob = INTVAL (XEXP (note, 0)) - REG_BR_PROB_BASE / 2; | |
f4857b9b AM |
10374 | |
10375 | /* Only hint for highly probable/improbable branches on newer | |
10376 | cpus as static prediction overrides processor dynamic | |
10377 | prediction. For older cpus we may as well always hint, but | |
10378 | assume not taken for branches that are very close to 50% as a | |
10379 | mispredicted taken branch is more expensive than a | |
f676971a | 10380 | mispredicted not-taken branch. */ |
ec507f2d | 10381 | if (rs6000_always_hint |
f4857b9b AM |
10382 | || abs (prob) > REG_BR_PROB_BASE / 100 * 48) |
10383 | { | |
10384 | if (abs (prob) > REG_BR_PROB_BASE / 20 | |
10385 | && ((prob > 0) ^ need_longbranch)) | |
c4ad648e | 10386 | pred = "+"; |
f4857b9b AM |
10387 | else |
10388 | pred = "-"; | |
10389 | } | |
12a4e8c5 | 10390 | } |
12a4e8c5 GK |
10391 | |
10392 | if (label == NULL) | |
94a54f47 | 10393 | s += sprintf (s, "{b%sr|b%slr%s} ", ccode, ccode, pred); |
12a4e8c5 | 10394 | else |
94a54f47 | 10395 | s += sprintf (s, "{b%s|b%s%s} ", ccode, ccode, pred); |
12a4e8c5 | 10396 | |
37c67319 | 10397 | /* We need to escape any '%' characters in the reg_names string. |
a3c9585f | 10398 | Assume they'd only be the first character.... */ |
37c67319 GK |
10399 | if (reg_names[cc_regno + CR0_REGNO][0] == '%') |
10400 | *s++ = '%'; | |
94a54f47 | 10401 | s += sprintf (s, "%s", reg_names[cc_regno + CR0_REGNO]); |
12a4e8c5 GK |
10402 | |
10403 | if (label != NULL) | |
10404 | { | |
10405 | /* If the branch distance was too far, we may have to use an | |
10406 | unconditional branch to go the distance. */ | |
10407 | if (need_longbranch) | |
44518ddd | 10408 | s += sprintf (s, ",$+8\n\tb %s", label); |
12a4e8c5 GK |
10409 | else |
10410 | s += sprintf (s, ",%s", label); | |
10411 | } | |
10412 | ||
10413 | return string; | |
10414 | } | |
50a0b056 | 10415 | |
6b1fedc3 | 10416 | /* Return the string to flip the EQ bit on a CR. */ |
423c1189 | 10417 | char * |
6b1fedc3 | 10418 | output_e500_flip_eq_bit (rtx dst, rtx src) |
423c1189 AH |
10419 | { |
10420 | static char string[64]; | |
10421 | int a, b; | |
10422 | ||
10423 | if (GET_CODE (dst) != REG || ! CR_REGNO_P (REGNO (dst)) | |
10424 | || GET_CODE (src) != REG || ! CR_REGNO_P (REGNO (src))) | |
10425 | abort (); | |
10426 | ||
6b1fedc3 AH |
10427 | /* EQ bit. */ |
10428 | a = 4 * (REGNO (dst) - CR0_REGNO) + 2; | |
10429 | b = 4 * (REGNO (src) - CR0_REGNO) + 2; | |
423c1189 AH |
10430 | |
10431 | sprintf (string, "crnot %d,%d", a, b); | |
10432 | return string; | |
10433 | } | |
10434 | ||
21213b4c DP |
10435 | /* Return insn index for the vector compare instruction for given CODE, |
10436 | and DEST_MODE, OP_MODE. Return INSN_NOT_AVAILABLE if valid insn is | |
10437 | not available. */ | |
10438 | ||
10439 | static int | |
94ff898d | 10440 | get_vec_cmp_insn (enum rtx_code code, |
21213b4c DP |
10441 | enum machine_mode dest_mode, |
10442 | enum machine_mode op_mode) | |
10443 | { | |
10444 | if (!TARGET_ALTIVEC) | |
10445 | return INSN_NOT_AVAILABLE; | |
10446 | ||
10447 | switch (code) | |
10448 | { | |
10449 | case EQ: | |
10450 | if (dest_mode == V16QImode && op_mode == V16QImode) | |
10451 | return UNSPEC_VCMPEQUB; | |
10452 | if (dest_mode == V8HImode && op_mode == V8HImode) | |
10453 | return UNSPEC_VCMPEQUH; | |
10454 | if (dest_mode == V4SImode && op_mode == V4SImode) | |
10455 | return UNSPEC_VCMPEQUW; | |
10456 | if (dest_mode == V4SImode && op_mode == V4SFmode) | |
10457 | return UNSPEC_VCMPEQFP; | |
10458 | break; | |
10459 | case GE: | |
10460 | if (dest_mode == V4SImode && op_mode == V4SFmode) | |
10461 | return UNSPEC_VCMPGEFP; | |
10462 | case GT: | |
10463 | if (dest_mode == V16QImode && op_mode == V16QImode) | |
10464 | return UNSPEC_VCMPGTSB; | |
10465 | if (dest_mode == V8HImode && op_mode == V8HImode) | |
10466 | return UNSPEC_VCMPGTSH; | |
10467 | if (dest_mode == V4SImode && op_mode == V4SImode) | |
10468 | return UNSPEC_VCMPGTSW; | |
10469 | if (dest_mode == V4SImode && op_mode == V4SFmode) | |
10470 | return UNSPEC_VCMPGTFP; | |
10471 | break; | |
10472 | case GTU: | |
10473 | if (dest_mode == V16QImode && op_mode == V16QImode) | |
10474 | return UNSPEC_VCMPGTUB; | |
10475 | if (dest_mode == V8HImode && op_mode == V8HImode) | |
10476 | return UNSPEC_VCMPGTUH; | |
10477 | if (dest_mode == V4SImode && op_mode == V4SImode) | |
10478 | return UNSPEC_VCMPGTUW; | |
10479 | break; | |
10480 | default: | |
10481 | break; | |
10482 | } | |
10483 | return INSN_NOT_AVAILABLE; | |
10484 | } | |
10485 | ||
10486 | /* Emit vector compare for operands OP0 and OP1 using code RCODE. | |
10487 | DMODE is expected destination mode. This is a recursive function. */ | |
10488 | ||
10489 | static rtx | |
10490 | rs6000_emit_vector_compare (enum rtx_code rcode, | |
10491 | rtx op0, rtx op1, | |
10492 | enum machine_mode dmode) | |
10493 | { | |
10494 | int vec_cmp_insn; | |
10495 | rtx mask; | |
10496 | enum machine_mode dest_mode; | |
10497 | enum machine_mode op_mode = GET_MODE (op1); | |
10498 | ||
10499 | #ifdef ENABLE_CHECKING | |
10500 | if (!TARGET_ALTIVEC) | |
10501 | abort (); | |
10502 | ||
10503 | if (GET_MODE (op0) != GET_MODE (op1)) | |
10504 | abort (); | |
10505 | #endif | |
10506 | ||
10507 | /* Floating point vector compare instructions uses destination V4SImode. | |
10508 | Move destination to appropriate mode later. */ | |
10509 | if (dmode == V4SFmode) | |
10510 | dest_mode = V4SImode; | |
10511 | else | |
10512 | dest_mode = dmode; | |
10513 | ||
10514 | mask = gen_reg_rtx (dest_mode); | |
10515 | vec_cmp_insn = get_vec_cmp_insn (rcode, dest_mode, op_mode); | |
10516 | ||
10517 | if (vec_cmp_insn == INSN_NOT_AVAILABLE) | |
10518 | { | |
10519 | bool swap_operands = false; | |
10520 | bool try_again = false; | |
10521 | switch (rcode) | |
10522 | { | |
10523 | case LT: | |
10524 | rcode = GT; | |
10525 | swap_operands = true; | |
10526 | try_again = true; | |
10527 | break; | |
10528 | case LTU: | |
10529 | rcode = GTU; | |
10530 | swap_operands = true; | |
10531 | try_again = true; | |
10532 | break; | |
10533 | case NE: | |
10534 | /* Treat A != B as ~(A==B). */ | |
10535 | { | |
10536 | enum insn_code nor_code; | |
10537 | rtx eq_rtx = rs6000_emit_vector_compare (EQ, op0, op1, | |
10538 | dest_mode); | |
94ff898d | 10539 | |
21213b4c DP |
10540 | nor_code = one_cmpl_optab->handlers[(int)dest_mode].insn_code; |
10541 | if (nor_code == CODE_FOR_nothing) | |
10542 | abort (); | |
10543 | emit_insn (GEN_FCN (nor_code) (mask, eq_rtx)); | |
10544 | ||
10545 | if (dmode != dest_mode) | |
10546 | { | |
10547 | rtx temp = gen_reg_rtx (dest_mode); | |
10548 | convert_move (temp, mask, 0); | |
10549 | return temp; | |
10550 | } | |
10551 | return mask; | |
10552 | } | |
10553 | break; | |
10554 | case GE: | |
10555 | case GEU: | |
10556 | case LE: | |
10557 | case LEU: | |
10558 | /* Try GT/GTU/LT/LTU OR EQ */ | |
10559 | { | |
10560 | rtx c_rtx, eq_rtx; | |
10561 | enum insn_code ior_code; | |
10562 | enum rtx_code new_code; | |
10563 | ||
10564 | if (rcode == GE) | |
10565 | new_code = GT; | |
10566 | else if (rcode == GEU) | |
10567 | new_code = GTU; | |
10568 | else if (rcode == LE) | |
10569 | new_code = LT; | |
10570 | else if (rcode == LEU) | |
10571 | new_code = LTU; | |
10572 | else | |
10573 | abort (); | |
10574 | ||
10575 | c_rtx = rs6000_emit_vector_compare (new_code, | |
10576 | op0, op1, dest_mode); | |
10577 | eq_rtx = rs6000_emit_vector_compare (EQ, op0, op1, | |
10578 | dest_mode); | |
10579 | ||
10580 | ior_code = ior_optab->handlers[(int)dest_mode].insn_code; | |
10581 | if (ior_code == CODE_FOR_nothing) | |
10582 | abort (); | |
10583 | emit_insn (GEN_FCN (ior_code) (mask, c_rtx, eq_rtx)); | |
10584 | if (dmode != dest_mode) | |
10585 | { | |
10586 | rtx temp = gen_reg_rtx (dest_mode); | |
10587 | convert_move (temp, mask, 0); | |
10588 | return temp; | |
10589 | } | |
10590 | return mask; | |
10591 | } | |
10592 | break; | |
10593 | default: | |
10594 | abort (); | |
10595 | } | |
10596 | ||
10597 | if (try_again) | |
10598 | { | |
10599 | vec_cmp_insn = get_vec_cmp_insn (rcode, dest_mode, op_mode); | |
10600 | if (vec_cmp_insn == INSN_NOT_AVAILABLE) | |
10601 | /* You only get two chances. */ | |
10602 | abort (); | |
10603 | } | |
10604 | ||
10605 | if (swap_operands) | |
10606 | { | |
10607 | rtx tmp; | |
10608 | tmp = op0; | |
10609 | op0 = op1; | |
10610 | op1 = tmp; | |
10611 | } | |
10612 | } | |
10613 | ||
10614 | emit_insn (gen_rtx_fmt_ee (SET, | |
10615 | VOIDmode, | |
10616 | mask, | |
10617 | gen_rtx_fmt_Ei (UNSPEC, dest_mode, | |
10618 | gen_rtvec (2, op0, op1), | |
10619 | vec_cmp_insn))); | |
10620 | if (dmode != dest_mode) | |
10621 | { | |
10622 | rtx temp = gen_reg_rtx (dest_mode); | |
10623 | convert_move (temp, mask, 0); | |
10624 | return temp; | |
10625 | } | |
10626 | return mask; | |
10627 | } | |
10628 | ||
10629 | /* Return vector select instruction for MODE. Return INSN_NOT_AVAILABLE, if | |
10630 | valid insn doesn exist for given mode. */ | |
10631 | ||
10632 | static int | |
10633 | get_vsel_insn (enum machine_mode mode) | |
10634 | { | |
10635 | switch (mode) | |
10636 | { | |
10637 | case V4SImode: | |
10638 | return UNSPEC_VSEL4SI; | |
10639 | break; | |
10640 | case V4SFmode: | |
10641 | return UNSPEC_VSEL4SF; | |
10642 | break; | |
10643 | case V8HImode: | |
10644 | return UNSPEC_VSEL8HI; | |
10645 | break; | |
10646 | case V16QImode: | |
10647 | return UNSPEC_VSEL16QI; | |
10648 | break; | |
10649 | default: | |
10650 | return INSN_NOT_AVAILABLE; | |
10651 | break; | |
10652 | } | |
10653 | return INSN_NOT_AVAILABLE; | |
10654 | } | |
10655 | ||
10656 | /* Emit vector select insn where DEST is destination using | |
10657 | operands OP1, OP2 and MASK. */ | |
10658 | ||
10659 | static void | |
10660 | rs6000_emit_vector_select (rtx dest, rtx op1, rtx op2, rtx mask) | |
10661 | { | |
10662 | rtx t, temp; | |
10663 | enum machine_mode dest_mode = GET_MODE (dest); | |
10664 | int vsel_insn_index = get_vsel_insn (GET_MODE (dest)); | |
10665 | ||
10666 | temp = gen_reg_rtx (dest_mode); | |
94ff898d | 10667 | |
21213b4c DP |
10668 | t = gen_rtx_fmt_ee (SET, VOIDmode, temp, |
10669 | gen_rtx_fmt_Ei (UNSPEC, dest_mode, | |
10670 | gen_rtvec (3, op1, op2, mask), | |
10671 | vsel_insn_index)); | |
10672 | emit_insn (t); | |
10673 | emit_move_insn (dest, temp); | |
10674 | return; | |
10675 | } | |
10676 | ||
94ff898d | 10677 | /* Emit vector conditional expression. |
21213b4c DP |
10678 | DEST is destination. OP1 and OP2 are two VEC_COND_EXPR operands. |
10679 | CC_OP0 and CC_OP1 are the two operands for the relation operation COND. */ | |
10680 | ||
10681 | int | |
10682 | rs6000_emit_vector_cond_expr (rtx dest, rtx op1, rtx op2, | |
10683 | rtx cond, rtx cc_op0, rtx cc_op1) | |
10684 | { | |
10685 | enum machine_mode dest_mode = GET_MODE (dest); | |
10686 | enum rtx_code rcode = GET_CODE (cond); | |
10687 | rtx mask; | |
10688 | ||
10689 | if (!TARGET_ALTIVEC) | |
10690 | return 0; | |
10691 | ||
10692 | /* Get the vector mask for the given relational operations. */ | |
10693 | mask = rs6000_emit_vector_compare (rcode, cc_op0, cc_op1, dest_mode); | |
10694 | ||
10695 | rs6000_emit_vector_select (dest, op1, op2, mask); | |
10696 | ||
10697 | return 1; | |
10698 | } | |
10699 | ||
50a0b056 GK |
10700 | /* Emit a conditional move: move TRUE_COND to DEST if OP of the |
10701 | operands of the last comparison is nonzero/true, FALSE_COND if it | |
10702 | is zero/false. Return 0 if the hardware has no such operation. */ | |
a4f6c312 | 10703 | |
50a0b056 | 10704 | int |
a2369ed3 | 10705 | rs6000_emit_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond) |
50a0b056 GK |
10706 | { |
10707 | enum rtx_code code = GET_CODE (op); | |
10708 | rtx op0 = rs6000_compare_op0; | |
10709 | rtx op1 = rs6000_compare_op1; | |
10710 | REAL_VALUE_TYPE c1; | |
3148ad6d DJ |
10711 | enum machine_mode compare_mode = GET_MODE (op0); |
10712 | enum machine_mode result_mode = GET_MODE (dest); | |
50a0b056 | 10713 | rtx temp; |
add2402e | 10714 | bool is_against_zero; |
50a0b056 | 10715 | |
a3c9585f | 10716 | /* These modes should always match. */ |
a3170dc6 AH |
10717 | if (GET_MODE (op1) != compare_mode |
10718 | /* In the isel case however, we can use a compare immediate, so | |
10719 | op1 may be a small constant. */ | |
10720 | && (!TARGET_ISEL || !short_cint_operand (op1, VOIDmode))) | |
3148ad6d | 10721 | return 0; |
178c3eff | 10722 | if (GET_MODE (true_cond) != result_mode) |
3148ad6d | 10723 | return 0; |
178c3eff | 10724 | if (GET_MODE (false_cond) != result_mode) |
3148ad6d DJ |
10725 | return 0; |
10726 | ||
50a0b056 | 10727 | /* First, work out if the hardware can do this at all, or |
a3c9585f | 10728 | if it's too slow.... */ |
50a0b056 | 10729 | if (! rs6000_compare_fp_p) |
a3170dc6 AH |
10730 | { |
10731 | if (TARGET_ISEL) | |
10732 | return rs6000_emit_int_cmove (dest, op, true_cond, false_cond); | |
10733 | return 0; | |
10734 | } | |
fef98bf2 AH |
10735 | else if (TARGET_E500 && TARGET_HARD_FLOAT && !TARGET_FPRS |
10736 | && GET_MODE_CLASS (compare_mode) == MODE_FLOAT) | |
10737 | return 0; | |
50a0b056 | 10738 | |
add2402e | 10739 | is_against_zero = op1 == CONST0_RTX (compare_mode); |
94ff898d | 10740 | |
add2402e GK |
10741 | /* A floating-point subtract might overflow, underflow, or produce |
10742 | an inexact result, thus changing the floating-point flags, so it | |
10743 | can't be generated if we care about that. It's safe if one side | |
10744 | of the construct is zero, since then no subtract will be | |
10745 | generated. */ | |
10746 | if (GET_MODE_CLASS (compare_mode) == MODE_FLOAT | |
10747 | && flag_trapping_math && ! is_against_zero) | |
10748 | return 0; | |
10749 | ||
50a0b056 GK |
10750 | /* Eliminate half of the comparisons by switching operands, this |
10751 | makes the remaining code simpler. */ | |
10752 | if (code == UNLT || code == UNGT || code == UNORDERED || code == NE | |
bc9ec0e0 | 10753 | || code == LTGT || code == LT || code == UNLE) |
50a0b056 GK |
10754 | { |
10755 | code = reverse_condition_maybe_unordered (code); | |
10756 | temp = true_cond; | |
10757 | true_cond = false_cond; | |
10758 | false_cond = temp; | |
10759 | } | |
10760 | ||
10761 | /* UNEQ and LTGT take four instructions for a comparison with zero, | |
10762 | it'll probably be faster to use a branch here too. */ | |
bc9ec0e0 | 10763 | if (code == UNEQ && HONOR_NANS (compare_mode)) |
50a0b056 | 10764 | return 0; |
f676971a | 10765 | |
50a0b056 GK |
10766 | if (GET_CODE (op1) == CONST_DOUBLE) |
10767 | REAL_VALUE_FROM_CONST_DOUBLE (c1, op1); | |
f676971a | 10768 | |
b6d08ca1 | 10769 | /* We're going to try to implement comparisons by performing |
50a0b056 GK |
10770 | a subtract, then comparing against zero. Unfortunately, |
10771 | Inf - Inf is NaN which is not zero, and so if we don't | |
27d30956 | 10772 | know that the operand is finite and the comparison |
50a0b056 | 10773 | would treat EQ different to UNORDERED, we can't do it. */ |
bc9ec0e0 | 10774 | if (HONOR_INFINITIES (compare_mode) |
50a0b056 | 10775 | && code != GT && code != UNGE |
045572c7 | 10776 | && (GET_CODE (op1) != CONST_DOUBLE || real_isinf (&c1)) |
50a0b056 GK |
10777 | /* Constructs of the form (a OP b ? a : b) are safe. */ |
10778 | && ((! rtx_equal_p (op0, false_cond) && ! rtx_equal_p (op1, false_cond)) | |
f676971a | 10779 | || (! rtx_equal_p (op0, true_cond) |
50a0b056 GK |
10780 | && ! rtx_equal_p (op1, true_cond)))) |
10781 | return 0; | |
add2402e | 10782 | |
50a0b056 GK |
10783 | /* At this point we know we can use fsel. */ |
10784 | ||
10785 | /* Reduce the comparison to a comparison against zero. */ | |
add2402e GK |
10786 | if (! is_against_zero) |
10787 | { | |
10788 | temp = gen_reg_rtx (compare_mode); | |
10789 | emit_insn (gen_rtx_SET (VOIDmode, temp, | |
10790 | gen_rtx_MINUS (compare_mode, op0, op1))); | |
10791 | op0 = temp; | |
10792 | op1 = CONST0_RTX (compare_mode); | |
10793 | } | |
50a0b056 GK |
10794 | |
10795 | /* If we don't care about NaNs we can reduce some of the comparisons | |
10796 | down to faster ones. */ | |
bc9ec0e0 | 10797 | if (! HONOR_NANS (compare_mode)) |
50a0b056 GK |
10798 | switch (code) |
10799 | { | |
10800 | case GT: | |
10801 | code = LE; | |
10802 | temp = true_cond; | |
10803 | true_cond = false_cond; | |
10804 | false_cond = temp; | |
10805 | break; | |
10806 | case UNGE: | |
10807 | code = GE; | |
10808 | break; | |
10809 | case UNEQ: | |
10810 | code = EQ; | |
10811 | break; | |
10812 | default: | |
10813 | break; | |
10814 | } | |
10815 | ||
10816 | /* Now, reduce everything down to a GE. */ | |
10817 | switch (code) | |
10818 | { | |
10819 | case GE: | |
10820 | break; | |
10821 | ||
10822 | case LE: | |
3148ad6d DJ |
10823 | temp = gen_reg_rtx (compare_mode); |
10824 | emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0))); | |
50a0b056 GK |
10825 | op0 = temp; |
10826 | break; | |
10827 | ||
10828 | case ORDERED: | |
3148ad6d DJ |
10829 | temp = gen_reg_rtx (compare_mode); |
10830 | emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_ABS (compare_mode, op0))); | |
50a0b056 GK |
10831 | op0 = temp; |
10832 | break; | |
10833 | ||
10834 | case EQ: | |
3148ad6d | 10835 | temp = gen_reg_rtx (compare_mode); |
f676971a | 10836 | emit_insn (gen_rtx_SET (VOIDmode, temp, |
3148ad6d DJ |
10837 | gen_rtx_NEG (compare_mode, |
10838 | gen_rtx_ABS (compare_mode, op0)))); | |
50a0b056 GK |
10839 | op0 = temp; |
10840 | break; | |
10841 | ||
10842 | case UNGE: | |
bc9ec0e0 | 10843 | /* a UNGE 0 <-> (a GE 0 || -a UNLT 0) */ |
3148ad6d | 10844 | temp = gen_reg_rtx (result_mode); |
50a0b056 | 10845 | emit_insn (gen_rtx_SET (VOIDmode, temp, |
3148ad6d | 10846 | gen_rtx_IF_THEN_ELSE (result_mode, |
50a0b056 GK |
10847 | gen_rtx_GE (VOIDmode, |
10848 | op0, op1), | |
10849 | true_cond, false_cond))); | |
bc9ec0e0 GK |
10850 | false_cond = true_cond; |
10851 | true_cond = temp; | |
50a0b056 | 10852 | |
3148ad6d DJ |
10853 | temp = gen_reg_rtx (compare_mode); |
10854 | emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0))); | |
50a0b056 GK |
10855 | op0 = temp; |
10856 | break; | |
10857 | ||
10858 | case GT: | |
bc9ec0e0 | 10859 | /* a GT 0 <-> (a GE 0 && -a UNLT 0) */ |
3148ad6d | 10860 | temp = gen_reg_rtx (result_mode); |
50a0b056 | 10861 | emit_insn (gen_rtx_SET (VOIDmode, temp, |
f676971a | 10862 | gen_rtx_IF_THEN_ELSE (result_mode, |
50a0b056 GK |
10863 | gen_rtx_GE (VOIDmode, |
10864 | op0, op1), | |
10865 | true_cond, false_cond))); | |
bc9ec0e0 GK |
10866 | true_cond = false_cond; |
10867 | false_cond = temp; | |
50a0b056 | 10868 | |
3148ad6d DJ |
10869 | temp = gen_reg_rtx (compare_mode); |
10870 | emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0))); | |
50a0b056 GK |
10871 | op0 = temp; |
10872 | break; | |
10873 | ||
10874 | default: | |
10875 | abort (); | |
10876 | } | |
10877 | ||
10878 | emit_insn (gen_rtx_SET (VOIDmode, dest, | |
3148ad6d | 10879 | gen_rtx_IF_THEN_ELSE (result_mode, |
50a0b056 GK |
10880 | gen_rtx_GE (VOIDmode, |
10881 | op0, op1), | |
10882 | true_cond, false_cond))); | |
10883 | return 1; | |
10884 | } | |
10885 | ||
a3170dc6 AH |
10886 | /* Same as above, but for ints (isel). */ |
10887 | ||
10888 | static int | |
a2369ed3 | 10889 | rs6000_emit_int_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond) |
a3170dc6 AH |
10890 | { |
10891 | rtx condition_rtx, cr; | |
10892 | ||
10893 | /* All isel implementations thus far are 32-bits. */ | |
10894 | if (GET_MODE (rs6000_compare_op0) != SImode) | |
10895 | return 0; | |
10896 | ||
10897 | /* We still have to do the compare, because isel doesn't do a | |
10898 | compare, it just looks at the CRx bits set by a previous compare | |
10899 | instruction. */ | |
10900 | condition_rtx = rs6000_generate_compare (GET_CODE (op)); | |
10901 | cr = XEXP (condition_rtx, 0); | |
10902 | ||
10903 | if (GET_MODE (cr) == CCmode) | |
10904 | emit_insn (gen_isel_signed (dest, condition_rtx, | |
10905 | true_cond, false_cond, cr)); | |
10906 | else | |
10907 | emit_insn (gen_isel_unsigned (dest, condition_rtx, | |
10908 | true_cond, false_cond, cr)); | |
10909 | ||
10910 | return 1; | |
10911 | } | |
10912 | ||
10913 | const char * | |
a2369ed3 | 10914 | output_isel (rtx *operands) |
a3170dc6 AH |
10915 | { |
10916 | enum rtx_code code; | |
10917 | ||
10918 | code = GET_CODE (operands[1]); | |
10919 | if (code == GE || code == GEU || code == LE || code == LEU || code == NE) | |
10920 | { | |
10921 | PUT_CODE (operands[1], reverse_condition (code)); | |
10922 | return "isel %0,%3,%2,%j1"; | |
10923 | } | |
10924 | else | |
10925 | return "isel %0,%2,%3,%j1"; | |
10926 | } | |
10927 | ||
50a0b056 | 10928 | void |
a2369ed3 | 10929 | rs6000_emit_minmax (rtx dest, enum rtx_code code, rtx op0, rtx op1) |
50a0b056 GK |
10930 | { |
10931 | enum machine_mode mode = GET_MODE (op0); | |
5dc8d536 | 10932 | enum rtx_code c; |
50a0b056 | 10933 | rtx target; |
5dc8d536 AH |
10934 | |
10935 | if (code == SMAX || code == SMIN) | |
10936 | c = GE; | |
10937 | else | |
10938 | c = GEU; | |
10939 | ||
50a0b056 | 10940 | if (code == SMAX || code == UMAX) |
f676971a | 10941 | target = emit_conditional_move (dest, c, op0, op1, mode, |
50a0b056 GK |
10942 | op0, op1, mode, 0); |
10943 | else | |
f676971a | 10944 | target = emit_conditional_move (dest, c, op0, op1, mode, |
50a0b056 GK |
10945 | op1, op0, mode, 0); |
10946 | if (target == NULL_RTX) | |
10947 | abort (); | |
10948 | if (target != dest) | |
10949 | emit_move_insn (dest, target); | |
10950 | } | |
46c07df8 | 10951 | |
a9baceb1 GK |
10952 | /* Emit instructions to move SRC to DST. Called by splitters for |
10953 | multi-register moves. It will emit at most one instruction for | |
10954 | each register that is accessed; that is, it won't emit li/lis pairs | |
10955 | (or equivalent for 64-bit code). One of SRC or DST must be a hard | |
10956 | register. */ | |
46c07df8 | 10957 | |
46c07df8 | 10958 | void |
a9baceb1 | 10959 | rs6000_split_multireg_move (rtx dst, rtx src) |
46c07df8 | 10960 | { |
a9baceb1 GK |
10961 | /* The register number of the first register being moved. */ |
10962 | int reg; | |
10963 | /* The mode that is to be moved. */ | |
10964 | enum machine_mode mode; | |
10965 | /* The mode that the move is being done in, and its size. */ | |
10966 | enum machine_mode reg_mode; | |
10967 | int reg_mode_size; | |
10968 | /* The number of registers that will be moved. */ | |
10969 | int nregs; | |
10970 | ||
10971 | reg = REG_P (dst) ? REGNO (dst) : REGNO (src); | |
10972 | mode = GET_MODE (dst); | |
10973 | nregs = HARD_REGNO_NREGS (reg, mode); | |
10974 | if (FP_REGNO_P (reg)) | |
10975 | reg_mode = DFmode; | |
10976 | else if (ALTIVEC_REGNO_P (reg)) | |
10977 | reg_mode = V16QImode; | |
10978 | else | |
10979 | reg_mode = word_mode; | |
10980 | reg_mode_size = GET_MODE_SIZE (reg_mode); | |
f676971a | 10981 | |
a9baceb1 GK |
10982 | if (reg_mode_size * nregs != GET_MODE_SIZE (mode)) |
10983 | abort (); | |
f676971a | 10984 | |
a9baceb1 GK |
10985 | if (REG_P (src) && REG_P (dst) && (REGNO (src) < REGNO (dst))) |
10986 | { | |
10987 | /* Move register range backwards, if we might have destructive | |
10988 | overlap. */ | |
10989 | int i; | |
10990 | for (i = nregs - 1; i >= 0; i--) | |
f676971a | 10991 | emit_insn (gen_rtx_SET (VOIDmode, |
a9baceb1 GK |
10992 | simplify_gen_subreg (reg_mode, dst, mode, |
10993 | i * reg_mode_size), | |
10994 | simplify_gen_subreg (reg_mode, src, mode, | |
10995 | i * reg_mode_size))); | |
10996 | } | |
46c07df8 HP |
10997 | else |
10998 | { | |
a9baceb1 GK |
10999 | int i; |
11000 | int j = -1; | |
11001 | bool used_update = false; | |
46c07df8 | 11002 | |
c1e55850 | 11003 | if (MEM_P (src) && INT_REGNO_P (reg)) |
c4ad648e AM |
11004 | { |
11005 | rtx breg; | |
3a1f863f | 11006 | |
a9baceb1 GK |
11007 | if (GET_CODE (XEXP (src, 0)) == PRE_INC |
11008 | || GET_CODE (XEXP (src, 0)) == PRE_DEC) | |
3a1f863f DE |
11009 | { |
11010 | rtx delta_rtx; | |
a9baceb1 | 11011 | breg = XEXP (XEXP (src, 0), 0); |
c4ad648e AM |
11012 | delta_rtx = (GET_CODE (XEXP (src, 0)) == PRE_INC |
11013 | ? GEN_INT (GET_MODE_SIZE (GET_MODE (src))) | |
11014 | : GEN_INT (-GET_MODE_SIZE (GET_MODE (src)))); | |
a9baceb1 GK |
11015 | emit_insn (TARGET_32BIT |
11016 | ? gen_addsi3 (breg, breg, delta_rtx) | |
11017 | : gen_adddi3 (breg, breg, delta_rtx)); | |
3a1f863f DE |
11018 | src = gen_rtx_MEM (mode, breg); |
11019 | } | |
c1e55850 GK |
11020 | else if (! offsettable_memref_p (src)) |
11021 | { | |
11022 | rtx newsrc, basereg; | |
11023 | basereg = gen_rtx_REG (Pmode, reg); | |
11024 | emit_insn (gen_rtx_SET (VOIDmode, basereg, XEXP (src, 0))); | |
11025 | newsrc = gen_rtx_MEM (GET_MODE (src), basereg); | |
11026 | MEM_COPY_ATTRIBUTES (newsrc, src); | |
11027 | src = newsrc; | |
11028 | } | |
3a1f863f | 11029 | |
0423421f AM |
11030 | breg = XEXP (src, 0); |
11031 | if (GET_CODE (breg) == PLUS || GET_CODE (breg) == LO_SUM) | |
11032 | breg = XEXP (breg, 0); | |
11033 | ||
11034 | /* If the base register we are using to address memory is | |
11035 | also a destination reg, then change that register last. */ | |
11036 | if (REG_P (breg) | |
11037 | && REGNO (breg) >= REGNO (dst) | |
3a1f863f DE |
11038 | && REGNO (breg) < REGNO (dst) + nregs) |
11039 | j = REGNO (breg) - REGNO (dst); | |
c4ad648e | 11040 | } |
46c07df8 | 11041 | |
a9baceb1 | 11042 | if (GET_CODE (dst) == MEM && INT_REGNO_P (reg)) |
3a1f863f DE |
11043 | { |
11044 | rtx breg; | |
11045 | ||
a9baceb1 GK |
11046 | if (GET_CODE (XEXP (dst, 0)) == PRE_INC |
11047 | || GET_CODE (XEXP (dst, 0)) == PRE_DEC) | |
3a1f863f DE |
11048 | { |
11049 | rtx delta_rtx; | |
a9baceb1 | 11050 | breg = XEXP (XEXP (dst, 0), 0); |
c4ad648e AM |
11051 | delta_rtx = (GET_CODE (XEXP (dst, 0)) == PRE_INC |
11052 | ? GEN_INT (GET_MODE_SIZE (GET_MODE (dst))) | |
11053 | : GEN_INT (-GET_MODE_SIZE (GET_MODE (dst)))); | |
3a1f863f DE |
11054 | |
11055 | /* We have to update the breg before doing the store. | |
11056 | Use store with update, if available. */ | |
11057 | ||
11058 | if (TARGET_UPDATE) | |
11059 | { | |
a9baceb1 | 11060 | rtx nsrc = simplify_gen_subreg (reg_mode, src, mode, 0); |
c4ad648e AM |
11061 | emit_insn (TARGET_32BIT |
11062 | ? (TARGET_POWERPC64 | |
11063 | ? gen_movdi_si_update (breg, breg, delta_rtx, nsrc) | |
11064 | : gen_movsi_update (breg, breg, delta_rtx, nsrc)) | |
11065 | : gen_movdi_di_update (breg, breg, delta_rtx, nsrc)); | |
a9baceb1 | 11066 | used_update = true; |
3a1f863f DE |
11067 | } |
11068 | else | |
a9baceb1 GK |
11069 | emit_insn (TARGET_32BIT |
11070 | ? gen_addsi3 (breg, breg, delta_rtx) | |
11071 | : gen_adddi3 (breg, breg, delta_rtx)); | |
3a1f863f DE |
11072 | dst = gen_rtx_MEM (mode, breg); |
11073 | } | |
c1e55850 | 11074 | else if (! offsettable_memref_p (dst)) |
112ccb83 | 11075 | abort (); |
3a1f863f DE |
11076 | } |
11077 | ||
46c07df8 | 11078 | for (i = 0; i < nregs; i++) |
f676971a | 11079 | { |
3a1f863f DE |
11080 | /* Calculate index to next subword. */ |
11081 | ++j; | |
f676971a | 11082 | if (j == nregs) |
3a1f863f | 11083 | j = 0; |
46c07df8 | 11084 | |
112cdef5 | 11085 | /* If compiler already emitted move of first word by |
a9baceb1 | 11086 | store with update, no need to do anything. */ |
3a1f863f | 11087 | if (j == 0 && used_update) |
a9baceb1 | 11088 | continue; |
f676971a | 11089 | |
a9baceb1 GK |
11090 | emit_insn (gen_rtx_SET (VOIDmode, |
11091 | simplify_gen_subreg (reg_mode, dst, mode, | |
11092 | j * reg_mode_size), | |
11093 | simplify_gen_subreg (reg_mode, src, mode, | |
11094 | j * reg_mode_size))); | |
3a1f863f | 11095 | } |
46c07df8 HP |
11096 | } |
11097 | } | |
11098 | ||
12a4e8c5 | 11099 | \f |
a4f6c312 SS |
11100 | /* This page contains routines that are used to determine what the |
11101 | function prologue and epilogue code will do and write them out. */ | |
9878760c | 11102 | |
a4f6c312 SS |
11103 | /* Return the first fixed-point register that is required to be |
11104 | saved. 32 if none. */ | |
9878760c RK |
11105 | |
11106 | int | |
863d938c | 11107 | first_reg_to_save (void) |
9878760c RK |
11108 | { |
11109 | int first_reg; | |
11110 | ||
11111 | /* Find lowest numbered live register. */ | |
11112 | for (first_reg = 13; first_reg <= 31; first_reg++) | |
f676971a | 11113 | if (regs_ever_live[first_reg] |
a38d360d | 11114 | && (! call_used_regs[first_reg] |
1db02437 | 11115 | || (first_reg == RS6000_PIC_OFFSET_TABLE_REGNUM |
14f00213 | 11116 | && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0) |
b4db40bf JJ |
11117 | || (DEFAULT_ABI == ABI_DARWIN && flag_pic) |
11118 | || (TARGET_TOC && TARGET_MINIMAL_TOC))))) | |
9878760c RK |
11119 | break; |
11120 | ||
ee890fe2 | 11121 | #if TARGET_MACHO |
93638d7a AM |
11122 | if (flag_pic |
11123 | && current_function_uses_pic_offset_table | |
11124 | && first_reg > RS6000_PIC_OFFSET_TABLE_REGNUM) | |
1db02437 | 11125 | return RS6000_PIC_OFFSET_TABLE_REGNUM; |
ee890fe2 SS |
11126 | #endif |
11127 | ||
9878760c RK |
11128 | return first_reg; |
11129 | } | |
11130 | ||
11131 | /* Similar, for FP regs. */ | |
11132 | ||
11133 | int | |
863d938c | 11134 | first_fp_reg_to_save (void) |
9878760c RK |
11135 | { |
11136 | int first_reg; | |
11137 | ||
11138 | /* Find lowest numbered live register. */ | |
11139 | for (first_reg = 14 + 32; first_reg <= 63; first_reg++) | |
11140 | if (regs_ever_live[first_reg]) | |
11141 | break; | |
11142 | ||
11143 | return first_reg; | |
11144 | } | |
00b960c7 AH |
11145 | |
11146 | /* Similar, for AltiVec regs. */ | |
11147 | ||
11148 | static int | |
863d938c | 11149 | first_altivec_reg_to_save (void) |
00b960c7 AH |
11150 | { |
11151 | int i; | |
11152 | ||
11153 | /* Stack frame remains as is unless we are in AltiVec ABI. */ | |
11154 | if (! TARGET_ALTIVEC_ABI) | |
11155 | return LAST_ALTIVEC_REGNO + 1; | |
11156 | ||
11157 | /* Find lowest numbered live register. */ | |
11158 | for (i = FIRST_ALTIVEC_REGNO + 20; i <= LAST_ALTIVEC_REGNO; ++i) | |
11159 | if (regs_ever_live[i]) | |
11160 | break; | |
11161 | ||
11162 | return i; | |
11163 | } | |
11164 | ||
11165 | /* Return a 32-bit mask of the AltiVec registers we need to set in | |
11166 | VRSAVE. Bit n of the return value is 1 if Vn is live. The MSB in | |
11167 | the 32-bit word is 0. */ | |
11168 | ||
11169 | static unsigned int | |
863d938c | 11170 | compute_vrsave_mask (void) |
00b960c7 AH |
11171 | { |
11172 | unsigned int i, mask = 0; | |
11173 | ||
11174 | /* First, find out if we use _any_ altivec registers. */ | |
11175 | for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i) | |
11176 | if (regs_ever_live[i]) | |
11177 | mask |= ALTIVEC_REG_BIT (i); | |
11178 | ||
11179 | if (mask == 0) | |
11180 | return mask; | |
11181 | ||
00b960c7 AH |
11182 | /* Next, remove the argument registers from the set. These must |
11183 | be in the VRSAVE mask set by the caller, so we don't need to add | |
11184 | them in again. More importantly, the mask we compute here is | |
11185 | used to generate CLOBBERs in the set_vrsave insn, and we do not | |
11186 | wish the argument registers to die. */ | |
a6cf80f2 | 11187 | for (i = cfun->args_info.vregno - 1; i >= ALTIVEC_ARG_MIN_REG; --i) |
00b960c7 AH |
11188 | mask &= ~ALTIVEC_REG_BIT (i); |
11189 | ||
11190 | /* Similarly, remove the return value from the set. */ | |
11191 | { | |
11192 | bool yes = false; | |
11193 | diddle_return_value (is_altivec_return_reg, &yes); | |
11194 | if (yes) | |
11195 | mask &= ~ALTIVEC_REG_BIT (ALTIVEC_ARG_RETURN); | |
11196 | } | |
11197 | ||
11198 | return mask; | |
11199 | } | |
11200 | ||
d62294f5 | 11201 | /* For a very restricted set of circumstances, we can cut down the |
f57fe068 AM |
11202 | size of prologues/epilogues by calling our own save/restore-the-world |
11203 | routines. */ | |
d62294f5 FJ |
11204 | |
11205 | static void | |
f57fe068 AM |
11206 | compute_save_world_info (rs6000_stack_t *info_ptr) |
11207 | { | |
11208 | info_ptr->world_save_p = 1; | |
11209 | info_ptr->world_save_p | |
11210 | = (WORLD_SAVE_P (info_ptr) | |
11211 | && DEFAULT_ABI == ABI_DARWIN | |
11212 | && ! (current_function_calls_setjmp && flag_exceptions) | |
11213 | && info_ptr->first_fp_reg_save == FIRST_SAVED_FP_REGNO | |
11214 | && info_ptr->first_gp_reg_save == FIRST_SAVED_GP_REGNO | |
11215 | && info_ptr->first_altivec_reg_save == FIRST_SAVED_ALTIVEC_REGNO | |
11216 | && info_ptr->cr_save_p); | |
f676971a | 11217 | |
d62294f5 FJ |
11218 | /* This will not work in conjunction with sibcalls. Make sure there |
11219 | are none. (This check is expensive, but seldom executed.) */ | |
f57fe068 | 11220 | if (WORLD_SAVE_P (info_ptr)) |
f676971a | 11221 | { |
d62294f5 FJ |
11222 | rtx insn; |
11223 | for ( insn = get_last_insn_anywhere (); insn; insn = PREV_INSN (insn)) | |
c4ad648e AM |
11224 | if ( GET_CODE (insn) == CALL_INSN |
11225 | && SIBLING_CALL_P (insn)) | |
11226 | { | |
11227 | info_ptr->world_save_p = 0; | |
11228 | break; | |
11229 | } | |
d62294f5 | 11230 | } |
f676971a | 11231 | |
f57fe068 | 11232 | if (WORLD_SAVE_P (info_ptr)) |
d62294f5 FJ |
11233 | { |
11234 | /* Even if we're not touching VRsave, make sure there's room on the | |
11235 | stack for it, if it looks like we're calling SAVE_WORLD, which | |
c4ad648e | 11236 | will attempt to save it. */ |
d62294f5 FJ |
11237 | info_ptr->vrsave_size = 4; |
11238 | ||
11239 | /* "Save" the VRsave register too if we're saving the world. */ | |
11240 | if (info_ptr->vrsave_mask == 0) | |
c4ad648e | 11241 | info_ptr->vrsave_mask = compute_vrsave_mask (); |
d62294f5 FJ |
11242 | |
11243 | /* Because the Darwin register save/restore routines only handle | |
c4ad648e AM |
11244 | F14 .. F31 and V20 .. V31 as per the ABI, perform a consistency |
11245 | check and abort if there's something worng. */ | |
f676971a | 11246 | if (info_ptr->first_fp_reg_save < FIRST_SAVED_FP_REGNO |
c4ad648e AM |
11247 | || info_ptr->first_altivec_reg_save < FIRST_SAVED_ALTIVEC_REGNO) |
11248 | abort (); | |
d62294f5 | 11249 | } |
f676971a | 11250 | return; |
d62294f5 FJ |
11251 | } |
11252 | ||
11253 | ||
00b960c7 | 11254 | static void |
a2369ed3 | 11255 | is_altivec_return_reg (rtx reg, void *xyes) |
00b960c7 AH |
11256 | { |
11257 | bool *yes = (bool *) xyes; | |
11258 | if (REGNO (reg) == ALTIVEC_ARG_RETURN) | |
11259 | *yes = true; | |
11260 | } | |
11261 | ||
4697a36c MM |
11262 | \f |
11263 | /* Calculate the stack information for the current function. This is | |
11264 | complicated by having two separate calling sequences, the AIX calling | |
11265 | sequence and the V.4 calling sequence. | |
11266 | ||
592696dd | 11267 | AIX (and Darwin/Mac OS X) stack frames look like: |
a260abc9 | 11268 | 32-bit 64-bit |
4697a36c | 11269 | SP----> +---------------------------------------+ |
a260abc9 | 11270 | | back chain to caller | 0 0 |
4697a36c | 11271 | +---------------------------------------+ |
a260abc9 | 11272 | | saved CR | 4 8 (8-11) |
4697a36c | 11273 | +---------------------------------------+ |
a260abc9 | 11274 | | saved LR | 8 16 |
4697a36c | 11275 | +---------------------------------------+ |
a260abc9 | 11276 | | reserved for compilers | 12 24 |
4697a36c | 11277 | +---------------------------------------+ |
a260abc9 | 11278 | | reserved for binders | 16 32 |
4697a36c | 11279 | +---------------------------------------+ |
a260abc9 | 11280 | | saved TOC pointer | 20 40 |
4697a36c | 11281 | +---------------------------------------+ |
a260abc9 | 11282 | | Parameter save area (P) | 24 48 |
4697a36c | 11283 | +---------------------------------------+ |
a260abc9 | 11284 | | Alloca space (A) | 24+P etc. |
802a0058 | 11285 | +---------------------------------------+ |
a7df97e6 | 11286 | | Local variable space (L) | 24+P+A |
4697a36c | 11287 | +---------------------------------------+ |
a7df97e6 | 11288 | | Float/int conversion temporary (X) | 24+P+A+L |
4697a36c | 11289 | +---------------------------------------+ |
00b960c7 AH |
11290 | | Save area for AltiVec registers (W) | 24+P+A+L+X |
11291 | +---------------------------------------+ | |
11292 | | AltiVec alignment padding (Y) | 24+P+A+L+X+W | |
11293 | +---------------------------------------+ | |
11294 | | Save area for VRSAVE register (Z) | 24+P+A+L+X+W+Y | |
4697a36c | 11295 | +---------------------------------------+ |
00b960c7 AH |
11296 | | Save area for GP registers (G) | 24+P+A+X+L+X+W+Y+Z |
11297 | +---------------------------------------+ | |
11298 | | Save area for FP registers (F) | 24+P+A+X+L+X+W+Y+Z+G | |
4697a36c MM |
11299 | +---------------------------------------+ |
11300 | old SP->| back chain to caller's caller | | |
11301 | +---------------------------------------+ | |
11302 | ||
5376a30c KR |
11303 | The required alignment for AIX configurations is two words (i.e., 8 |
11304 | or 16 bytes). | |
11305 | ||
11306 | ||
4697a36c MM |
11307 | V.4 stack frames look like: |
11308 | ||
11309 | SP----> +---------------------------------------+ | |
11310 | | back chain to caller | 0 | |
11311 | +---------------------------------------+ | |
5eb387b8 | 11312 | | caller's saved LR | 4 |
4697a36c MM |
11313 | +---------------------------------------+ |
11314 | | Parameter save area (P) | 8 | |
11315 | +---------------------------------------+ | |
a7df97e6 | 11316 | | Alloca space (A) | 8+P |
f676971a | 11317 | +---------------------------------------+ |
a7df97e6 | 11318 | | Varargs save area (V) | 8+P+A |
f676971a | 11319 | +---------------------------------------+ |
a7df97e6 | 11320 | | Local variable space (L) | 8+P+A+V |
f676971a | 11321 | +---------------------------------------+ |
a7df97e6 | 11322 | | Float/int conversion temporary (X) | 8+P+A+V+L |
4697a36c | 11323 | +---------------------------------------+ |
00b960c7 AH |
11324 | | Save area for AltiVec registers (W) | 8+P+A+V+L+X |
11325 | +---------------------------------------+ | |
11326 | | AltiVec alignment padding (Y) | 8+P+A+V+L+X+W | |
11327 | +---------------------------------------+ | |
11328 | | Save area for VRSAVE register (Z) | 8+P+A+V+L+X+W+Y | |
11329 | +---------------------------------------+ | |
c4ad648e AM |
11330 | | SPE: area for 64-bit GP registers | |
11331 | +---------------------------------------+ | |
11332 | | SPE alignment padding | | |
11333 | +---------------------------------------+ | |
00b960c7 | 11334 | | saved CR (C) | 8+P+A+V+L+X+W+Y+Z |
f676971a | 11335 | +---------------------------------------+ |
00b960c7 | 11336 | | Save area for GP registers (G) | 8+P+A+V+L+X+W+Y+Z+C |
f676971a | 11337 | +---------------------------------------+ |
00b960c7 | 11338 | | Save area for FP registers (F) | 8+P+A+V+L+X+W+Y+Z+C+G |
4697a36c MM |
11339 | +---------------------------------------+ |
11340 | old SP->| back chain to caller's caller | | |
11341 | +---------------------------------------+ | |
b6c9286a | 11342 | |
5376a30c KR |
11343 | The required alignment for V.4 is 16 bytes, or 8 bytes if -meabi is |
11344 | given. (But note below and in sysv4.h that we require only 8 and | |
11345 | may round up the size of our stack frame anyways. The historical | |
11346 | reason is early versions of powerpc-linux which didn't properly | |
11347 | align the stack at program startup. A happy side-effect is that | |
11348 | -mno-eabi libraries can be used with -meabi programs.) | |
11349 | ||
50d440bc | 11350 | The EABI configuration defaults to the V.4 layout. However, |
5376a30c KR |
11351 | the stack alignment requirements may differ. If -mno-eabi is not |
11352 | given, the required stack alignment is 8 bytes; if -mno-eabi is | |
11353 | given, the required alignment is 16 bytes. (But see V.4 comment | |
11354 | above.) */ | |
4697a36c | 11355 | |
61b2fbe7 MM |
11356 | #ifndef ABI_STACK_BOUNDARY |
11357 | #define ABI_STACK_BOUNDARY STACK_BOUNDARY | |
11358 | #endif | |
11359 | ||
d1d0c603 | 11360 | static rs6000_stack_t * |
863d938c | 11361 | rs6000_stack_info (void) |
4697a36c MM |
11362 | { |
11363 | static rs6000_stack_t info, zero_info; | |
11364 | rs6000_stack_t *info_ptr = &info; | |
327e5343 | 11365 | int reg_size = TARGET_32BIT ? 4 : 8; |
83720594 | 11366 | int ehrd_size; |
64045029 | 11367 | int save_align; |
44688022 | 11368 | HOST_WIDE_INT non_fixed_size; |
4697a36c | 11369 | |
a4f6c312 | 11370 | /* Zero all fields portably. */ |
4697a36c MM |
11371 | info = zero_info; |
11372 | ||
c19de7aa AH |
11373 | if (TARGET_SPE) |
11374 | { | |
11375 | /* Cache value so we don't rescan instruction chain over and over. */ | |
9b7b447f | 11376 | if (cfun->machine->insn_chain_scanned_p == 0) |
b5a5beb9 AH |
11377 | cfun->machine->insn_chain_scanned_p |
11378 | = spe_func_has_64bit_regs_p () + 1; | |
11379 | info_ptr->spe_64bit_regs_used = cfun->machine->insn_chain_scanned_p - 1; | |
c19de7aa AH |
11380 | } |
11381 | ||
a4f6c312 | 11382 | /* Select which calling sequence. */ |
178274da | 11383 | info_ptr->abi = DEFAULT_ABI; |
9878760c | 11384 | |
a4f6c312 | 11385 | /* Calculate which registers need to be saved & save area size. */ |
4697a36c | 11386 | info_ptr->first_gp_reg_save = first_reg_to_save (); |
f676971a | 11387 | /* Assume that we will have to save RS6000_PIC_OFFSET_TABLE_REGNUM, |
906fb125 | 11388 | even if it currently looks like we won't. */ |
2bfcf297 | 11389 | if (((TARGET_TOC && TARGET_MINIMAL_TOC) |
178274da AM |
11390 | || (flag_pic == 1 && DEFAULT_ABI == ABI_V4) |
11391 | || (flag_pic && DEFAULT_ABI == ABI_DARWIN)) | |
1db02437 FS |
11392 | && info_ptr->first_gp_reg_save > RS6000_PIC_OFFSET_TABLE_REGNUM) |
11393 | info_ptr->gp_size = reg_size * (32 - RS6000_PIC_OFFSET_TABLE_REGNUM); | |
906fb125 GK |
11394 | else |
11395 | info_ptr->gp_size = reg_size * (32 - info_ptr->first_gp_reg_save); | |
4697a36c | 11396 | |
a3170dc6 AH |
11397 | /* For the SPE, we have an additional upper 32-bits on each GPR. |
11398 | Ideally we should save the entire 64-bits only when the upper | |
11399 | half is used in SIMD instructions. Since we only record | |
11400 | registers live (not the size they are used in), this proves | |
11401 | difficult because we'd have to traverse the instruction chain at | |
11402 | the right time, taking reload into account. This is a real pain, | |
c19de7aa AH |
11403 | so we opt to save the GPRs in 64-bits always if but one register |
11404 | gets used in 64-bits. Otherwise, all the registers in the frame | |
11405 | get saved in 32-bits. | |
a3170dc6 | 11406 | |
c19de7aa | 11407 | So... since when we save all GPRs (except the SP) in 64-bits, the |
a3170dc6 | 11408 | traditional GP save area will be empty. */ |
c19de7aa | 11409 | if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0) |
a3170dc6 AH |
11410 | info_ptr->gp_size = 0; |
11411 | ||
4697a36c MM |
11412 | info_ptr->first_fp_reg_save = first_fp_reg_to_save (); |
11413 | info_ptr->fp_size = 8 * (64 - info_ptr->first_fp_reg_save); | |
11414 | ||
00b960c7 AH |
11415 | info_ptr->first_altivec_reg_save = first_altivec_reg_to_save (); |
11416 | info_ptr->altivec_size = 16 * (LAST_ALTIVEC_REGNO + 1 | |
11417 | - info_ptr->first_altivec_reg_save); | |
11418 | ||
592696dd | 11419 | /* Does this function call anything? */ |
71f123ca FS |
11420 | info_ptr->calls_p = (! current_function_is_leaf |
11421 | || cfun->machine->ra_needs_full_frame); | |
b6c9286a | 11422 | |
a4f6c312 | 11423 | /* Determine if we need to save the link register. */ |
71f123ca | 11424 | if (rs6000_ra_ever_killed () |
ffcfcb5f AM |
11425 | || (DEFAULT_ABI == ABI_AIX |
11426 | && current_function_profile | |
11427 | && !TARGET_PROFILE_KERNEL) | |
4697a36c MM |
11428 | #ifdef TARGET_RELOCATABLE |
11429 | || (TARGET_RELOCATABLE && (get_pool_size () != 0)) | |
11430 | #endif | |
11431 | || (info_ptr->first_fp_reg_save != 64 | |
11432 | && !FP_SAVE_INLINE (info_ptr->first_fp_reg_save)) | |
00b960c7 | 11433 | || info_ptr->first_altivec_reg_save <= LAST_ALTIVEC_REGNO |
178274da | 11434 | || (DEFAULT_ABI == ABI_V4 && current_function_calls_alloca) |
a4f6c312 SS |
11435 | || (DEFAULT_ABI == ABI_DARWIN |
11436 | && flag_pic | |
11437 | && current_function_uses_pic_offset_table) | |
4697a36c MM |
11438 | || info_ptr->calls_p) |
11439 | { | |
11440 | info_ptr->lr_save_p = 1; | |
9ebbca7d | 11441 | regs_ever_live[LINK_REGISTER_REGNUM] = 1; |
4697a36c MM |
11442 | } |
11443 | ||
9ebbca7d | 11444 | /* Determine if we need to save the condition code registers. */ |
f676971a | 11445 | if (regs_ever_live[CR2_REGNO] |
9ebbca7d GK |
11446 | || regs_ever_live[CR3_REGNO] |
11447 | || regs_ever_live[CR4_REGNO]) | |
4697a36c MM |
11448 | { |
11449 | info_ptr->cr_save_p = 1; | |
178274da | 11450 | if (DEFAULT_ABI == ABI_V4) |
4697a36c MM |
11451 | info_ptr->cr_size = reg_size; |
11452 | } | |
11453 | ||
83720594 RH |
11454 | /* If the current function calls __builtin_eh_return, then we need |
11455 | to allocate stack space for registers that will hold data for | |
11456 | the exception handler. */ | |
11457 | if (current_function_calls_eh_return) | |
11458 | { | |
11459 | unsigned int i; | |
11460 | for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; ++i) | |
11461 | continue; | |
a3170dc6 AH |
11462 | |
11463 | /* SPE saves EH registers in 64-bits. */ | |
c19de7aa AH |
11464 | ehrd_size = i * (TARGET_SPE_ABI |
11465 | && info_ptr->spe_64bit_regs_used != 0 | |
11466 | ? UNITS_PER_SPE_WORD : UNITS_PER_WORD); | |
83720594 RH |
11467 | } |
11468 | else | |
11469 | ehrd_size = 0; | |
11470 | ||
592696dd | 11471 | /* Determine various sizes. */ |
4697a36c MM |
11472 | info_ptr->reg_size = reg_size; |
11473 | info_ptr->fixed_size = RS6000_SAVE_AREA; | |
11474 | info_ptr->varargs_size = RS6000_VARARGS_AREA; | |
189e03e3 | 11475 | info_ptr->vars_size = RS6000_ALIGN (get_frame_size (), 8); |
a4f6c312 | 11476 | info_ptr->parm_size = RS6000_ALIGN (current_function_outgoing_args_size, |
03e007d7 | 11477 | TARGET_ALTIVEC ? 16 : 8); |
00b960c7 | 11478 | |
c19de7aa | 11479 | if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0) |
a3170dc6 AH |
11480 | info_ptr->spe_gp_size = 8 * (32 - info_ptr->first_gp_reg_save); |
11481 | else | |
11482 | info_ptr->spe_gp_size = 0; | |
11483 | ||
4d774ff8 HP |
11484 | if (TARGET_ALTIVEC_ABI) |
11485 | info_ptr->vrsave_mask = compute_vrsave_mask (); | |
00b960c7 | 11486 | else |
4d774ff8 HP |
11487 | info_ptr->vrsave_mask = 0; |
11488 | ||
11489 | if (TARGET_ALTIVEC_VRSAVE && info_ptr->vrsave_mask) | |
11490 | info_ptr->vrsave_size = 4; | |
11491 | else | |
11492 | info_ptr->vrsave_size = 0; | |
b6c9286a | 11493 | |
d62294f5 FJ |
11494 | compute_save_world_info (info_ptr); |
11495 | ||
592696dd | 11496 | /* Calculate the offsets. */ |
178274da | 11497 | switch (DEFAULT_ABI) |
4697a36c | 11498 | { |
b6c9286a | 11499 | case ABI_NONE: |
24d304eb | 11500 | default: |
b6c9286a MM |
11501 | abort (); |
11502 | ||
11503 | case ABI_AIX: | |
ee890fe2 | 11504 | case ABI_DARWIN: |
b6c9286a MM |
11505 | info_ptr->fp_save_offset = - info_ptr->fp_size; |
11506 | info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size; | |
00b960c7 AH |
11507 | |
11508 | if (TARGET_ALTIVEC_ABI) | |
11509 | { | |
11510 | info_ptr->vrsave_save_offset | |
11511 | = info_ptr->gp_save_offset - info_ptr->vrsave_size; | |
11512 | ||
11513 | /* Align stack so vector save area is on a quadword boundary. */ | |
11514 | if (info_ptr->altivec_size != 0) | |
11515 | info_ptr->altivec_padding_size | |
11516 | = 16 - (-info_ptr->vrsave_save_offset % 16); | |
11517 | else | |
11518 | info_ptr->altivec_padding_size = 0; | |
11519 | ||
11520 | info_ptr->altivec_save_offset | |
11521 | = info_ptr->vrsave_save_offset | |
11522 | - info_ptr->altivec_padding_size | |
11523 | - info_ptr->altivec_size; | |
11524 | ||
11525 | /* Adjust for AltiVec case. */ | |
11526 | info_ptr->ehrd_offset = info_ptr->altivec_save_offset - ehrd_size; | |
11527 | } | |
11528 | else | |
11529 | info_ptr->ehrd_offset = info_ptr->gp_save_offset - ehrd_size; | |
a260abc9 DE |
11530 | info_ptr->cr_save_offset = reg_size; /* first word when 64-bit. */ |
11531 | info_ptr->lr_save_offset = 2*reg_size; | |
24d304eb RK |
11532 | break; |
11533 | ||
11534 | case ABI_V4: | |
b6c9286a MM |
11535 | info_ptr->fp_save_offset = - info_ptr->fp_size; |
11536 | info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size; | |
a7df97e6 | 11537 | info_ptr->cr_save_offset = info_ptr->gp_save_offset - info_ptr->cr_size; |
00b960c7 | 11538 | |
c19de7aa | 11539 | if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0) |
c4ad648e AM |
11540 | { |
11541 | /* Align stack so SPE GPR save area is aligned on a | |
11542 | double-word boundary. */ | |
11543 | if (info_ptr->spe_gp_size != 0) | |
11544 | info_ptr->spe_padding_size | |
11545 | = 8 - (-info_ptr->cr_save_offset % 8); | |
11546 | else | |
11547 | info_ptr->spe_padding_size = 0; | |
11548 | ||
11549 | info_ptr->spe_gp_save_offset | |
11550 | = info_ptr->cr_save_offset | |
11551 | - info_ptr->spe_padding_size | |
11552 | - info_ptr->spe_gp_size; | |
11553 | ||
11554 | /* Adjust for SPE case. */ | |
11555 | info_ptr->toc_save_offset | |
11556 | = info_ptr->spe_gp_save_offset - info_ptr->toc_size; | |
11557 | } | |
a3170dc6 | 11558 | else if (TARGET_ALTIVEC_ABI) |
00b960c7 AH |
11559 | { |
11560 | info_ptr->vrsave_save_offset | |
11561 | = info_ptr->cr_save_offset - info_ptr->vrsave_size; | |
11562 | ||
11563 | /* Align stack so vector save area is on a quadword boundary. */ | |
11564 | if (info_ptr->altivec_size != 0) | |
11565 | info_ptr->altivec_padding_size | |
11566 | = 16 - (-info_ptr->vrsave_save_offset % 16); | |
11567 | else | |
11568 | info_ptr->altivec_padding_size = 0; | |
11569 | ||
11570 | info_ptr->altivec_save_offset | |
11571 | = info_ptr->vrsave_save_offset | |
11572 | - info_ptr->altivec_padding_size | |
11573 | - info_ptr->altivec_size; | |
11574 | ||
11575 | /* Adjust for AltiVec case. */ | |
11576 | info_ptr->toc_save_offset | |
11577 | = info_ptr->altivec_save_offset - info_ptr->toc_size; | |
11578 | } | |
11579 | else | |
11580 | info_ptr->toc_save_offset = info_ptr->cr_save_offset - info_ptr->toc_size; | |
83720594 | 11581 | info_ptr->ehrd_offset = info_ptr->toc_save_offset - ehrd_size; |
b6c9286a MM |
11582 | info_ptr->lr_save_offset = reg_size; |
11583 | break; | |
4697a36c MM |
11584 | } |
11585 | ||
64045029 | 11586 | save_align = (TARGET_ALTIVEC_ABI || DEFAULT_ABI == ABI_DARWIN) ? 16 : 8; |
00b960c7 AH |
11587 | info_ptr->save_size = RS6000_ALIGN (info_ptr->fp_size |
11588 | + info_ptr->gp_size | |
11589 | + info_ptr->altivec_size | |
11590 | + info_ptr->altivec_padding_size | |
a3170dc6 AH |
11591 | + info_ptr->spe_gp_size |
11592 | + info_ptr->spe_padding_size | |
00b960c7 AH |
11593 | + ehrd_size |
11594 | + info_ptr->cr_size | |
11595 | + info_ptr->lr_size | |
11596 | + info_ptr->vrsave_size | |
11597 | + info_ptr->toc_size, | |
64045029 | 11598 | save_align); |
00b960c7 | 11599 | |
44688022 | 11600 | non_fixed_size = (info_ptr->vars_size |
ff381587 | 11601 | + info_ptr->parm_size |
ff381587 | 11602 | + info_ptr->save_size |
44688022 | 11603 | + info_ptr->varargs_size); |
ff381587 | 11604 | |
44688022 AM |
11605 | info_ptr->total_size = RS6000_ALIGN (non_fixed_size + info_ptr->fixed_size, |
11606 | ABI_STACK_BOUNDARY / BITS_PER_UNIT); | |
ff381587 MM |
11607 | |
11608 | /* Determine if we need to allocate any stack frame: | |
11609 | ||
a4f6c312 SS |
11610 | For AIX we need to push the stack if a frame pointer is needed |
11611 | (because the stack might be dynamically adjusted), if we are | |
11612 | debugging, if we make calls, or if the sum of fp_save, gp_save, | |
11613 | and local variables are more than the space needed to save all | |
11614 | non-volatile registers: 32-bit: 18*8 + 19*4 = 220 or 64-bit: 18*8 | |
11615 | + 18*8 = 288 (GPR13 reserved). | |
ff381587 | 11616 | |
a4f6c312 SS |
11617 | For V.4 we don't have the stack cushion that AIX uses, but assume |
11618 | that the debugger can handle stackless frames. */ | |
ff381587 MM |
11619 | |
11620 | if (info_ptr->calls_p) | |
11621 | info_ptr->push_p = 1; | |
11622 | ||
178274da | 11623 | else if (DEFAULT_ABI == ABI_V4) |
44688022 | 11624 | info_ptr->push_p = non_fixed_size != 0; |
ff381587 | 11625 | |
178274da AM |
11626 | else if (frame_pointer_needed) |
11627 | info_ptr->push_p = 1; | |
11628 | ||
11629 | else if (TARGET_XCOFF && write_symbols != NO_DEBUG) | |
11630 | info_ptr->push_p = 1; | |
11631 | ||
ff381587 | 11632 | else |
44688022 | 11633 | info_ptr->push_p = non_fixed_size > (TARGET_32BIT ? 220 : 288); |
ff381587 | 11634 | |
a4f6c312 | 11635 | /* Zero offsets if we're not saving those registers. */ |
8dda1a21 | 11636 | if (info_ptr->fp_size == 0) |
4697a36c MM |
11637 | info_ptr->fp_save_offset = 0; |
11638 | ||
8dda1a21 | 11639 | if (info_ptr->gp_size == 0) |
4697a36c MM |
11640 | info_ptr->gp_save_offset = 0; |
11641 | ||
00b960c7 AH |
11642 | if (! TARGET_ALTIVEC_ABI || info_ptr->altivec_size == 0) |
11643 | info_ptr->altivec_save_offset = 0; | |
11644 | ||
11645 | if (! TARGET_ALTIVEC_ABI || info_ptr->vrsave_mask == 0) | |
11646 | info_ptr->vrsave_save_offset = 0; | |
11647 | ||
c19de7aa AH |
11648 | if (! TARGET_SPE_ABI |
11649 | || info_ptr->spe_64bit_regs_used == 0 | |
11650 | || info_ptr->spe_gp_size == 0) | |
a3170dc6 AH |
11651 | info_ptr->spe_gp_save_offset = 0; |
11652 | ||
c81fc13e | 11653 | if (! info_ptr->lr_save_p) |
4697a36c MM |
11654 | info_ptr->lr_save_offset = 0; |
11655 | ||
c81fc13e | 11656 | if (! info_ptr->cr_save_p) |
4697a36c MM |
11657 | info_ptr->cr_save_offset = 0; |
11658 | ||
c81fc13e | 11659 | if (! info_ptr->toc_save_p) |
b6c9286a MM |
11660 | info_ptr->toc_save_offset = 0; |
11661 | ||
4697a36c MM |
11662 | return info_ptr; |
11663 | } | |
11664 | ||
c19de7aa AH |
11665 | /* Return true if the current function uses any GPRs in 64-bit SIMD |
11666 | mode. */ | |
11667 | ||
11668 | static bool | |
863d938c | 11669 | spe_func_has_64bit_regs_p (void) |
c19de7aa AH |
11670 | { |
11671 | rtx insns, insn; | |
11672 | ||
11673 | /* Functions that save and restore all the call-saved registers will | |
11674 | need to save/restore the registers in 64-bits. */ | |
11675 | if (current_function_calls_eh_return | |
11676 | || current_function_calls_setjmp | |
11677 | || current_function_has_nonlocal_goto) | |
11678 | return true; | |
11679 | ||
11680 | insns = get_insns (); | |
11681 | ||
11682 | for (insn = NEXT_INSN (insns); insn != NULL_RTX; insn = NEXT_INSN (insn)) | |
11683 | { | |
11684 | if (INSN_P (insn)) | |
11685 | { | |
11686 | rtx i; | |
11687 | ||
b5a5beb9 AH |
11688 | /* FIXME: This should be implemented with attributes... |
11689 | ||
11690 | (set_attr "spe64" "true")....then, | |
11691 | if (get_spe64(insn)) return true; | |
11692 | ||
11693 | It's the only reliable way to do the stuff below. */ | |
11694 | ||
c19de7aa | 11695 | i = PATTERN (insn); |
f82f556d AH |
11696 | if (GET_CODE (i) == SET) |
11697 | { | |
11698 | enum machine_mode mode = GET_MODE (SET_SRC (i)); | |
11699 | ||
11700 | if (SPE_VECTOR_MODE (mode)) | |
11701 | return true; | |
11702 | if (TARGET_E500_DOUBLE && mode == DFmode) | |
11703 | return true; | |
11704 | } | |
c19de7aa AH |
11705 | } |
11706 | } | |
11707 | ||
11708 | return false; | |
11709 | } | |
11710 | ||
d1d0c603 | 11711 | static void |
a2369ed3 | 11712 | debug_stack_info (rs6000_stack_t *info) |
9878760c | 11713 | { |
d330fd93 | 11714 | const char *abi_string; |
24d304eb | 11715 | |
c81fc13e | 11716 | if (! info) |
4697a36c MM |
11717 | info = rs6000_stack_info (); |
11718 | ||
11719 | fprintf (stderr, "\nStack information for function %s:\n", | |
11720 | ((current_function_decl && DECL_NAME (current_function_decl)) | |
11721 | ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl)) | |
11722 | : "<unknown>")); | |
11723 | ||
24d304eb RK |
11724 | switch (info->abi) |
11725 | { | |
b6c9286a MM |
11726 | default: abi_string = "Unknown"; break; |
11727 | case ABI_NONE: abi_string = "NONE"; break; | |
50d440bc | 11728 | case ABI_AIX: abi_string = "AIX"; break; |
ee890fe2 | 11729 | case ABI_DARWIN: abi_string = "Darwin"; break; |
b6c9286a | 11730 | case ABI_V4: abi_string = "V.4"; break; |
24d304eb RK |
11731 | } |
11732 | ||
11733 | fprintf (stderr, "\tABI = %5s\n", abi_string); | |
11734 | ||
00b960c7 AH |
11735 | if (TARGET_ALTIVEC_ABI) |
11736 | fprintf (stderr, "\tALTIVEC ABI extensions enabled.\n"); | |
11737 | ||
a3170dc6 AH |
11738 | if (TARGET_SPE_ABI) |
11739 | fprintf (stderr, "\tSPE ABI extensions enabled.\n"); | |
11740 | ||
4697a36c MM |
11741 | if (info->first_gp_reg_save != 32) |
11742 | fprintf (stderr, "\tfirst_gp_reg_save = %5d\n", info->first_gp_reg_save); | |
11743 | ||
11744 | if (info->first_fp_reg_save != 64) | |
11745 | fprintf (stderr, "\tfirst_fp_reg_save = %5d\n", info->first_fp_reg_save); | |
9878760c | 11746 | |
00b960c7 AH |
11747 | if (info->first_altivec_reg_save <= LAST_ALTIVEC_REGNO) |
11748 | fprintf (stderr, "\tfirst_altivec_reg_save = %5d\n", | |
11749 | info->first_altivec_reg_save); | |
11750 | ||
4697a36c MM |
11751 | if (info->lr_save_p) |
11752 | fprintf (stderr, "\tlr_save_p = %5d\n", info->lr_save_p); | |
9878760c | 11753 | |
4697a36c MM |
11754 | if (info->cr_save_p) |
11755 | fprintf (stderr, "\tcr_save_p = %5d\n", info->cr_save_p); | |
11756 | ||
b6c9286a MM |
11757 | if (info->toc_save_p) |
11758 | fprintf (stderr, "\ttoc_save_p = %5d\n", info->toc_save_p); | |
11759 | ||
00b960c7 AH |
11760 | if (info->vrsave_mask) |
11761 | fprintf (stderr, "\tvrsave_mask = 0x%x\n", info->vrsave_mask); | |
11762 | ||
4697a36c MM |
11763 | if (info->push_p) |
11764 | fprintf (stderr, "\tpush_p = %5d\n", info->push_p); | |
11765 | ||
11766 | if (info->calls_p) | |
11767 | fprintf (stderr, "\tcalls_p = %5d\n", info->calls_p); | |
11768 | ||
4697a36c MM |
11769 | if (info->gp_save_offset) |
11770 | fprintf (stderr, "\tgp_save_offset = %5d\n", info->gp_save_offset); | |
11771 | ||
11772 | if (info->fp_save_offset) | |
11773 | fprintf (stderr, "\tfp_save_offset = %5d\n", info->fp_save_offset); | |
11774 | ||
00b960c7 AH |
11775 | if (info->altivec_save_offset) |
11776 | fprintf (stderr, "\taltivec_save_offset = %5d\n", | |
11777 | info->altivec_save_offset); | |
11778 | ||
a3170dc6 AH |
11779 | if (info->spe_gp_save_offset) |
11780 | fprintf (stderr, "\tspe_gp_save_offset = %5d\n", | |
11781 | info->spe_gp_save_offset); | |
11782 | ||
00b960c7 AH |
11783 | if (info->vrsave_save_offset) |
11784 | fprintf (stderr, "\tvrsave_save_offset = %5d\n", | |
11785 | info->vrsave_save_offset); | |
11786 | ||
4697a36c MM |
11787 | if (info->lr_save_offset) |
11788 | fprintf (stderr, "\tlr_save_offset = %5d\n", info->lr_save_offset); | |
11789 | ||
11790 | if (info->cr_save_offset) | |
11791 | fprintf (stderr, "\tcr_save_offset = %5d\n", info->cr_save_offset); | |
11792 | ||
b6c9286a MM |
11793 | if (info->toc_save_offset) |
11794 | fprintf (stderr, "\ttoc_save_offset = %5d\n", info->toc_save_offset); | |
11795 | ||
4697a36c MM |
11796 | if (info->varargs_save_offset) |
11797 | fprintf (stderr, "\tvarargs_save_offset = %5d\n", info->varargs_save_offset); | |
11798 | ||
11799 | if (info->total_size) | |
d1d0c603 JJ |
11800 | fprintf (stderr, "\ttotal_size = "HOST_WIDE_INT_PRINT_DEC"\n", |
11801 | info->total_size); | |
4697a36c MM |
11802 | |
11803 | if (info->varargs_size) | |
11804 | fprintf (stderr, "\tvarargs_size = %5d\n", info->varargs_size); | |
11805 | ||
11806 | if (info->vars_size) | |
d1d0c603 JJ |
11807 | fprintf (stderr, "\tvars_size = "HOST_WIDE_INT_PRINT_DEC"\n", |
11808 | info->vars_size); | |
4697a36c MM |
11809 | |
11810 | if (info->parm_size) | |
11811 | fprintf (stderr, "\tparm_size = %5d\n", info->parm_size); | |
11812 | ||
11813 | if (info->fixed_size) | |
11814 | fprintf (stderr, "\tfixed_size = %5d\n", info->fixed_size); | |
11815 | ||
11816 | if (info->gp_size) | |
11817 | fprintf (stderr, "\tgp_size = %5d\n", info->gp_size); | |
11818 | ||
a3170dc6 AH |
11819 | if (info->spe_gp_size) |
11820 | fprintf (stderr, "\tspe_gp_size = %5d\n", info->spe_gp_size); | |
11821 | ||
4697a36c MM |
11822 | if (info->fp_size) |
11823 | fprintf (stderr, "\tfp_size = %5d\n", info->fp_size); | |
11824 | ||
00b960c7 AH |
11825 | if (info->altivec_size) |
11826 | fprintf (stderr, "\taltivec_size = %5d\n", info->altivec_size); | |
11827 | ||
11828 | if (info->vrsave_size) | |
11829 | fprintf (stderr, "\tvrsave_size = %5d\n", info->vrsave_size); | |
11830 | ||
11831 | if (info->altivec_padding_size) | |
11832 | fprintf (stderr, "\taltivec_padding_size= %5d\n", | |
11833 | info->altivec_padding_size); | |
11834 | ||
a3170dc6 AH |
11835 | if (info->spe_padding_size) |
11836 | fprintf (stderr, "\tspe_padding_size = %5d\n", | |
11837 | info->spe_padding_size); | |
11838 | ||
a4f6c312 | 11839 | if (info->lr_size) |
ed947a96 | 11840 | fprintf (stderr, "\tlr_size = %5d\n", info->lr_size); |
b6c9286a | 11841 | |
4697a36c MM |
11842 | if (info->cr_size) |
11843 | fprintf (stderr, "\tcr_size = %5d\n", info->cr_size); | |
11844 | ||
a4f6c312 | 11845 | if (info->toc_size) |
b6c9286a MM |
11846 | fprintf (stderr, "\ttoc_size = %5d\n", info->toc_size); |
11847 | ||
4697a36c MM |
11848 | if (info->save_size) |
11849 | fprintf (stderr, "\tsave_size = %5d\n", info->save_size); | |
11850 | ||
11851 | if (info->reg_size != 4) | |
11852 | fprintf (stderr, "\treg_size = %5d\n", info->reg_size); | |
11853 | ||
11854 | fprintf (stderr, "\n"); | |
9878760c | 11855 | } |
71f123ca FS |
11856 | |
11857 | rtx | |
a2369ed3 | 11858 | rs6000_return_addr (int count, rtx frame) |
71f123ca | 11859 | { |
a4f6c312 SS |
11860 | /* Currently we don't optimize very well between prolog and body |
11861 | code and for PIC code the code can be actually quite bad, so | |
11862 | don't try to be too clever here. */ | |
f1384257 | 11863 | if (count != 0 || (DEFAULT_ABI != ABI_AIX && flag_pic)) |
71f123ca FS |
11864 | { |
11865 | cfun->machine->ra_needs_full_frame = 1; | |
8ac61af7 RK |
11866 | |
11867 | return | |
11868 | gen_rtx_MEM | |
11869 | (Pmode, | |
11870 | memory_address | |
11871 | (Pmode, | |
11872 | plus_constant (copy_to_reg | |
11873 | (gen_rtx_MEM (Pmode, | |
11874 | memory_address (Pmode, frame))), | |
11875 | RETURN_ADDRESS_OFFSET))); | |
71f123ca FS |
11876 | } |
11877 | ||
8c29550d | 11878 | cfun->machine->ra_need_lr = 1; |
9e2f7ec7 | 11879 | return get_hard_reg_initial_val (Pmode, LINK_REGISTER_REGNUM); |
71f123ca FS |
11880 | } |
11881 | ||
5e1bf043 DJ |
11882 | /* Say whether a function is a candidate for sibcall handling or not. |
11883 | We do not allow indirect calls to be optimized into sibling calls. | |
11884 | Also, we can't do it if there are any vector parameters; there's | |
11885 | nowhere to put the VRsave code so it works; note that functions with | |
11886 | vector parameters are required to have a prototype, so the argument | |
11887 | type info must be available here. (The tail recursion case can work | |
11888 | with vector parameters, but there's no way to distinguish here.) */ | |
4977bab6 | 11889 | static bool |
a2369ed3 | 11890 | rs6000_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED) |
5e1bf043 DJ |
11891 | { |
11892 | tree type; | |
4977bab6 | 11893 | if (decl) |
5e1bf043 DJ |
11894 | { |
11895 | if (TARGET_ALTIVEC_VRSAVE) | |
c4ad648e | 11896 | { |
4977bab6 | 11897 | for (type = TYPE_ARG_TYPES (TREE_TYPE (decl)); |
5e1bf043 DJ |
11898 | type; type = TREE_CHAIN (type)) |
11899 | { | |
c15b529f | 11900 | if (TREE_CODE (TREE_VALUE (type)) == VECTOR_TYPE) |
4977bab6 | 11901 | return false; |
5e1bf043 | 11902 | } |
c4ad648e | 11903 | } |
5e1bf043 | 11904 | if (DEFAULT_ABI == ABI_DARWIN |
4977bab6 | 11905 | || (*targetm.binds_local_p) (decl)) |
2bcc50d0 | 11906 | { |
4977bab6 | 11907 | tree attr_list = TYPE_ATTRIBUTES (TREE_TYPE (decl)); |
2bcc50d0 AM |
11908 | |
11909 | if (!lookup_attribute ("longcall", attr_list) | |
11910 | || lookup_attribute ("shortcall", attr_list)) | |
4977bab6 | 11911 | return true; |
2bcc50d0 | 11912 | } |
5e1bf043 | 11913 | } |
4977bab6 | 11914 | return false; |
5e1bf043 DJ |
11915 | } |
11916 | ||
71f123ca | 11917 | static int |
863d938c | 11918 | rs6000_ra_ever_killed (void) |
71f123ca FS |
11919 | { |
11920 | rtx top; | |
5e1bf043 DJ |
11921 | rtx reg; |
11922 | rtx insn; | |
71f123ca | 11923 | |
dd292d0a | 11924 | if (current_function_is_thunk) |
71f123ca | 11925 | return 0; |
eb0424da | 11926 | |
36f7e964 AH |
11927 | /* regs_ever_live has LR marked as used if any sibcalls are present, |
11928 | but this should not force saving and restoring in the | |
11929 | pro/epilogue. Likewise, reg_set_between_p thinks a sibcall | |
a3c9585f | 11930 | clobbers LR, so that is inappropriate. */ |
36f7e964 | 11931 | |
5e1bf043 DJ |
11932 | /* Also, the prologue can generate a store into LR that |
11933 | doesn't really count, like this: | |
36f7e964 | 11934 | |
5e1bf043 DJ |
11935 | move LR->R0 |
11936 | bcl to set PIC register | |
11937 | move LR->R31 | |
11938 | move R0->LR | |
36f7e964 AH |
11939 | |
11940 | When we're called from the epilogue, we need to avoid counting | |
11941 | this as a store. */ | |
f676971a | 11942 | |
71f123ca FS |
11943 | push_topmost_sequence (); |
11944 | top = get_insns (); | |
11945 | pop_topmost_sequence (); | |
5e1bf043 | 11946 | reg = gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM); |
71f123ca | 11947 | |
5e1bf043 DJ |
11948 | for (insn = NEXT_INSN (top); insn != NULL_RTX; insn = NEXT_INSN (insn)) |
11949 | { | |
11950 | if (INSN_P (insn)) | |
11951 | { | |
11952 | if (FIND_REG_INC_NOTE (insn, reg)) | |
11953 | return 1; | |
f676971a | 11954 | else if (GET_CODE (insn) == CALL_INSN |
c15b529f | 11955 | && !SIBLING_CALL_P (insn)) |
5e1bf043 | 11956 | return 1; |
36f7e964 AH |
11957 | else if (set_of (reg, insn) != NULL_RTX |
11958 | && !prologue_epilogue_contains (insn)) | |
5e1bf043 DJ |
11959 | return 1; |
11960 | } | |
11961 | } | |
11962 | return 0; | |
71f123ca | 11963 | } |
4697a36c | 11964 | \f |
8cd8f856 GK |
11965 | /* Add a REG_MAYBE_DEAD note to the insn. */ |
11966 | static void | |
a2369ed3 | 11967 | rs6000_maybe_dead (rtx insn) |
8cd8f856 GK |
11968 | { |
11969 | REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD, | |
11970 | const0_rtx, | |
11971 | REG_NOTES (insn)); | |
11972 | } | |
11973 | ||
9ebbca7d | 11974 | /* Emit instructions needed to load the TOC register. |
c7ca610e | 11975 | This is only needed when TARGET_TOC, TARGET_MINIMAL_TOC, and there is |
9ebbca7d | 11976 | a constant pool; or for SVR4 -fpic. */ |
c7ca610e RK |
11977 | |
11978 | void | |
a2369ed3 | 11979 | rs6000_emit_load_toc_table (int fromprolog) |
c7ca610e | 11980 | { |
027fbf43 | 11981 | rtx dest, insn; |
1db02437 | 11982 | dest = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM); |
c7ca610e | 11983 | |
20b71b17 AM |
11984 | if (TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 1) |
11985 | { | |
11986 | rtx temp = (fromprolog | |
11987 | ? gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM) | |
11988 | : gen_reg_rtx (Pmode)); | |
027fbf43 JJ |
11989 | insn = emit_insn (gen_load_toc_v4_pic_si (temp)); |
11990 | if (fromprolog) | |
11991 | rs6000_maybe_dead (insn); | |
11992 | insn = emit_move_insn (dest, temp); | |
11993 | if (fromprolog) | |
11994 | rs6000_maybe_dead (insn); | |
20b71b17 AM |
11995 | } |
11996 | else if (TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2) | |
11997 | { | |
11998 | char buf[30]; | |
11999 | rtx tempLR = (fromprolog | |
12000 | ? gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM) | |
12001 | : gen_reg_rtx (Pmode)); | |
12002 | rtx temp0 = (fromprolog | |
12003 | ? gen_rtx_REG (Pmode, 0) | |
12004 | : gen_reg_rtx (Pmode)); | |
12005 | rtx symF; | |
12006 | ||
20b71b17 AM |
12007 | if (fromprolog) |
12008 | { | |
12009 | rtx symL; | |
38c1f2d7 | 12010 | |
20b71b17 AM |
12011 | ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno); |
12012 | symF = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); | |
9ebbca7d | 12013 | |
20b71b17 AM |
12014 | ASM_GENERATE_INTERNAL_LABEL (buf, "LCL", rs6000_pic_labelno); |
12015 | symL = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); | |
12016 | ||
12017 | rs6000_maybe_dead (emit_insn (gen_load_toc_v4_PIC_1 (tempLR, | |
12018 | symF))); | |
12019 | rs6000_maybe_dead (emit_move_insn (dest, tempLR)); | |
12020 | rs6000_maybe_dead (emit_insn (gen_load_toc_v4_PIC_2 (temp0, dest, | |
12021 | symL, | |
12022 | symF))); | |
9ebbca7d GK |
12023 | } |
12024 | else | |
20b71b17 AM |
12025 | { |
12026 | rtx tocsym; | |
12027 | static int reload_toc_labelno = 0; | |
12028 | ||
12029 | tocsym = gen_rtx_SYMBOL_REF (Pmode, toc_label_name); | |
12030 | ||
12031 | ASM_GENERATE_INTERNAL_LABEL (buf, "LCG", reload_toc_labelno++); | |
12032 | symF = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); | |
12033 | ||
027fbf43 JJ |
12034 | emit_insn (gen_load_toc_v4_PIC_1b (tempLR, symF, tocsym)); |
12035 | emit_move_insn (dest, tempLR); | |
12036 | emit_move_insn (temp0, gen_rtx_MEM (Pmode, dest)); | |
20b71b17 | 12037 | } |
027fbf43 JJ |
12038 | insn = emit_insn (gen_addsi3 (dest, temp0, dest)); |
12039 | if (fromprolog) | |
12040 | rs6000_maybe_dead (insn); | |
9ebbca7d | 12041 | } |
20b71b17 AM |
12042 | else if (TARGET_ELF && !TARGET_AIX && flag_pic == 0 && TARGET_MINIMAL_TOC) |
12043 | { | |
12044 | /* This is for AIX code running in non-PIC ELF32. */ | |
12045 | char buf[30]; | |
12046 | rtx realsym; | |
12047 | ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1); | |
12048 | realsym = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); | |
12049 | ||
027fbf43 JJ |
12050 | insn = emit_insn (gen_elf_high (dest, realsym)); |
12051 | if (fromprolog) | |
12052 | rs6000_maybe_dead (insn); | |
12053 | insn = emit_insn (gen_elf_low (dest, dest, realsym)); | |
12054 | if (fromprolog) | |
12055 | rs6000_maybe_dead (insn); | |
20b71b17 AM |
12056 | } |
12057 | else if (DEFAULT_ABI == ABI_AIX) | |
9ebbca7d GK |
12058 | { |
12059 | if (TARGET_32BIT) | |
027fbf43 | 12060 | insn = emit_insn (gen_load_toc_aix_si (dest)); |
9ebbca7d | 12061 | else |
027fbf43 JJ |
12062 | insn = emit_insn (gen_load_toc_aix_di (dest)); |
12063 | if (fromprolog) | |
12064 | rs6000_maybe_dead (insn); | |
9ebbca7d | 12065 | } |
20b71b17 AM |
12066 | else |
12067 | abort (); | |
9ebbca7d GK |
12068 | } |
12069 | ||
d1d0c603 JJ |
12070 | /* Emit instructions to restore the link register after determining where |
12071 | its value has been stored. */ | |
12072 | ||
12073 | void | |
12074 | rs6000_emit_eh_reg_restore (rtx source, rtx scratch) | |
12075 | { | |
12076 | rs6000_stack_t *info = rs6000_stack_info (); | |
12077 | rtx operands[2]; | |
12078 | ||
12079 | operands[0] = source; | |
12080 | operands[1] = scratch; | |
12081 | ||
12082 | if (info->lr_save_p) | |
12083 | { | |
12084 | rtx frame_rtx = stack_pointer_rtx; | |
12085 | HOST_WIDE_INT sp_offset = 0; | |
12086 | rtx tmp; | |
12087 | ||
12088 | if (frame_pointer_needed | |
12089 | || current_function_calls_alloca | |
12090 | || info->total_size > 32767) | |
12091 | { | |
12092 | emit_move_insn (operands[1], gen_rtx_MEM (Pmode, frame_rtx)); | |
12093 | frame_rtx = operands[1]; | |
12094 | } | |
12095 | else if (info->push_p) | |
12096 | sp_offset = info->total_size; | |
12097 | ||
12098 | tmp = plus_constant (frame_rtx, info->lr_save_offset + sp_offset); | |
12099 | tmp = gen_rtx_MEM (Pmode, tmp); | |
12100 | emit_move_insn (tmp, operands[0]); | |
12101 | } | |
12102 | else | |
12103 | emit_move_insn (gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM), operands[0]); | |
12104 | } | |
12105 | ||
f103e34d GK |
12106 | static GTY(()) int set = -1; |
12107 | ||
f676971a | 12108 | int |
863d938c | 12109 | get_TOC_alias_set (void) |
9ebbca7d | 12110 | { |
f103e34d GK |
12111 | if (set == -1) |
12112 | set = new_alias_set (); | |
12113 | return set; | |
f676971a | 12114 | } |
9ebbca7d | 12115 | |
c1207243 | 12116 | /* This returns nonzero if the current function uses the TOC. This is |
3c9eb5f4 AM |
12117 | determined by the presence of (use (unspec ... UNSPEC_TOC)), which |
12118 | is generated by the ABI_V4 load_toc_* patterns. */ | |
c954844a | 12119 | #if TARGET_ELF |
3c9eb5f4 | 12120 | static int |
f676971a | 12121 | uses_TOC (void) |
9ebbca7d | 12122 | { |
c4501e62 | 12123 | rtx insn; |
38c1f2d7 | 12124 | |
c4501e62 JJ |
12125 | for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) |
12126 | if (INSN_P (insn)) | |
12127 | { | |
12128 | rtx pat = PATTERN (insn); | |
12129 | int i; | |
9ebbca7d | 12130 | |
f676971a | 12131 | if (GET_CODE (pat) == PARALLEL) |
c4501e62 JJ |
12132 | for (i = 0; i < XVECLEN (pat, 0); i++) |
12133 | { | |
12134 | rtx sub = XVECEXP (pat, 0, i); | |
12135 | if (GET_CODE (sub) == USE) | |
12136 | { | |
12137 | sub = XEXP (sub, 0); | |
12138 | if (GET_CODE (sub) == UNSPEC | |
12139 | && XINT (sub, 1) == UNSPEC_TOC) | |
12140 | return 1; | |
12141 | } | |
12142 | } | |
12143 | } | |
12144 | return 0; | |
9ebbca7d | 12145 | } |
c954844a | 12146 | #endif |
38c1f2d7 | 12147 | |
9ebbca7d | 12148 | rtx |
f676971a | 12149 | create_TOC_reference (rtx symbol) |
9ebbca7d | 12150 | { |
f676971a | 12151 | return gen_rtx_PLUS (Pmode, |
a8a05998 | 12152 | gen_rtx_REG (Pmode, TOC_REGISTER), |
f676971a EC |
12153 | gen_rtx_CONST (Pmode, |
12154 | gen_rtx_MINUS (Pmode, symbol, | |
b999aaeb | 12155 | gen_rtx_SYMBOL_REF (Pmode, toc_label_name)))); |
9ebbca7d | 12156 | } |
38c1f2d7 | 12157 | |
fc4767bb JJ |
12158 | /* If _Unwind_* has been called from within the same module, |
12159 | toc register is not guaranteed to be saved to 40(1) on function | |
12160 | entry. Save it there in that case. */ | |
c7ca610e | 12161 | |
9ebbca7d | 12162 | void |
863d938c | 12163 | rs6000_aix_emit_builtin_unwind_init (void) |
9ebbca7d GK |
12164 | { |
12165 | rtx mem; | |
12166 | rtx stack_top = gen_reg_rtx (Pmode); | |
12167 | rtx opcode_addr = gen_reg_rtx (Pmode); | |
fc4767bb JJ |
12168 | rtx opcode = gen_reg_rtx (SImode); |
12169 | rtx tocompare = gen_reg_rtx (SImode); | |
12170 | rtx no_toc_save_needed = gen_label_rtx (); | |
9ebbca7d GK |
12171 | |
12172 | mem = gen_rtx_MEM (Pmode, hard_frame_pointer_rtx); | |
12173 | emit_move_insn (stack_top, mem); | |
12174 | ||
fc4767bb JJ |
12175 | mem = gen_rtx_MEM (Pmode, |
12176 | gen_rtx_PLUS (Pmode, stack_top, | |
9ebbca7d GK |
12177 | GEN_INT (2 * GET_MODE_SIZE (Pmode)))); |
12178 | emit_move_insn (opcode_addr, mem); | |
fc4767bb JJ |
12179 | emit_move_insn (opcode, gen_rtx_MEM (SImode, opcode_addr)); |
12180 | emit_move_insn (tocompare, gen_int_mode (TARGET_32BIT ? 0x80410014 | |
2496c7bd | 12181 | : 0xE8410028, SImode)); |
9ebbca7d | 12182 | |
fc4767bb | 12183 | do_compare_rtx_and_jump (opcode, tocompare, EQ, 1, |
06f4e019 | 12184 | SImode, NULL_RTX, NULL_RTX, |
fc4767bb | 12185 | no_toc_save_needed); |
9ebbca7d | 12186 | |
fc4767bb JJ |
12187 | mem = gen_rtx_MEM (Pmode, |
12188 | gen_rtx_PLUS (Pmode, stack_top, | |
12189 | GEN_INT (5 * GET_MODE_SIZE (Pmode)))); | |
12190 | emit_move_insn (mem, gen_rtx_REG (Pmode, 2)); | |
12191 | emit_label (no_toc_save_needed); | |
9ebbca7d | 12192 | } |
38c1f2d7 | 12193 | \f |
ba4828e0 RK |
12194 | /* This ties together stack memory (MEM with an alias set of |
12195 | rs6000_sr_alias_set) and the change to the stack pointer. */ | |
12196 | ||
9ebbca7d | 12197 | static void |
863d938c | 12198 | rs6000_emit_stack_tie (void) |
9ebbca7d | 12199 | { |
ba4828e0 RK |
12200 | rtx mem = gen_rtx_MEM (BLKmode, gen_rtx_REG (Pmode, STACK_POINTER_REGNUM)); |
12201 | ||
12202 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
9ebbca7d GK |
12203 | emit_insn (gen_stack_tie (mem)); |
12204 | } | |
38c1f2d7 | 12205 | |
9ebbca7d GK |
12206 | /* Emit the correct code for allocating stack space, as insns. |
12207 | If COPY_R12, make sure a copy of the old frame is left in r12. | |
12208 | The generated code may use hard register 0 as a temporary. */ | |
12209 | ||
12210 | static void | |
a2369ed3 | 12211 | rs6000_emit_allocate_stack (HOST_WIDE_INT size, int copy_r12) |
38c1f2d7 | 12212 | { |
9ebbca7d GK |
12213 | rtx insn; |
12214 | rtx stack_reg = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM); | |
12215 | rtx tmp_reg = gen_rtx_REG (Pmode, 0); | |
61168ff1 RS |
12216 | rtx todec = gen_int_mode (-size, Pmode); |
12217 | ||
12218 | if (INTVAL (todec) != -size) | |
12219 | { | |
12220 | warning("stack frame too large"); | |
12221 | emit_insn (gen_trap ()); | |
12222 | return; | |
12223 | } | |
a157febd GK |
12224 | |
12225 | if (current_function_limit_stack) | |
12226 | { | |
12227 | if (REG_P (stack_limit_rtx) | |
f676971a | 12228 | && REGNO (stack_limit_rtx) > 1 |
a157febd GK |
12229 | && REGNO (stack_limit_rtx) <= 31) |
12230 | { | |
5b71a4e7 | 12231 | emit_insn (TARGET_32BIT |
9ebbca7d GK |
12232 | ? gen_addsi3 (tmp_reg, |
12233 | stack_limit_rtx, | |
12234 | GEN_INT (size)) | |
12235 | : gen_adddi3 (tmp_reg, | |
12236 | stack_limit_rtx, | |
12237 | GEN_INT (size))); | |
5b71a4e7 | 12238 | |
9ebbca7d GK |
12239 | emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg, |
12240 | const0_rtx)); | |
a157febd GK |
12241 | } |
12242 | else if (GET_CODE (stack_limit_rtx) == SYMBOL_REF | |
9ebbca7d | 12243 | && TARGET_32BIT |
f607bc57 | 12244 | && DEFAULT_ABI == ABI_V4) |
a157febd | 12245 | { |
9ebbca7d | 12246 | rtx toload = gen_rtx_CONST (VOIDmode, |
f676971a EC |
12247 | gen_rtx_PLUS (Pmode, |
12248 | stack_limit_rtx, | |
9ebbca7d | 12249 | GEN_INT (size))); |
5b71a4e7 | 12250 | |
9ebbca7d GK |
12251 | emit_insn (gen_elf_high (tmp_reg, toload)); |
12252 | emit_insn (gen_elf_low (tmp_reg, tmp_reg, toload)); | |
12253 | emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg, | |
12254 | const0_rtx)); | |
a157febd GK |
12255 | } |
12256 | else | |
12257 | warning ("stack limit expression is not supported"); | |
12258 | } | |
12259 | ||
9ebbca7d GK |
12260 | if (copy_r12 || ! TARGET_UPDATE) |
12261 | emit_move_insn (gen_rtx_REG (Pmode, 12), stack_reg); | |
12262 | ||
38c1f2d7 MM |
12263 | if (TARGET_UPDATE) |
12264 | { | |
9ebbca7d | 12265 | if (size > 32767) |
38c1f2d7 | 12266 | { |
9ebbca7d GK |
12267 | /* Need a note here so that try_split doesn't get confused. */ |
12268 | if (get_last_insn() == NULL_RTX) | |
2e040219 | 12269 | emit_note (NOTE_INSN_DELETED); |
9ebbca7d GK |
12270 | insn = emit_move_insn (tmp_reg, todec); |
12271 | try_split (PATTERN (insn), insn, 0); | |
12272 | todec = tmp_reg; | |
38c1f2d7 | 12273 | } |
5b71a4e7 DE |
12274 | |
12275 | insn = emit_insn (TARGET_32BIT | |
12276 | ? gen_movsi_update (stack_reg, stack_reg, | |
12277 | todec, stack_reg) | |
c4ad648e | 12278 | : gen_movdi_di_update (stack_reg, stack_reg, |
9ebbca7d | 12279 | todec, stack_reg)); |
38c1f2d7 MM |
12280 | } |
12281 | else | |
12282 | { | |
5b71a4e7 DE |
12283 | insn = emit_insn (TARGET_32BIT |
12284 | ? gen_addsi3 (stack_reg, stack_reg, todec) | |
12285 | : gen_adddi3 (stack_reg, stack_reg, todec)); | |
9ebbca7d GK |
12286 | emit_move_insn (gen_rtx_MEM (Pmode, stack_reg), |
12287 | gen_rtx_REG (Pmode, 12)); | |
12288 | } | |
f676971a | 12289 | |
9ebbca7d | 12290 | RTX_FRAME_RELATED_P (insn) = 1; |
f676971a | 12291 | REG_NOTES (insn) = |
9ebbca7d | 12292 | gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, |
f676971a | 12293 | gen_rtx_SET (VOIDmode, stack_reg, |
9ebbca7d GK |
12294 | gen_rtx_PLUS (Pmode, stack_reg, |
12295 | GEN_INT (-size))), | |
12296 | REG_NOTES (insn)); | |
12297 | } | |
12298 | ||
a4f6c312 SS |
12299 | /* Add to 'insn' a note which is PATTERN (INSN) but with REG replaced |
12300 | with (plus:P (reg 1) VAL), and with REG2 replaced with RREG if REG2 | |
12301 | is not NULL. It would be nice if dwarf2out_frame_debug_expr could | |
12302 | deduce these equivalences by itself so it wasn't necessary to hold | |
12303 | its hand so much. */ | |
9ebbca7d GK |
12304 | |
12305 | static void | |
f676971a | 12306 | rs6000_frame_related (rtx insn, rtx reg, HOST_WIDE_INT val, |
a2369ed3 | 12307 | rtx reg2, rtx rreg) |
9ebbca7d GK |
12308 | { |
12309 | rtx real, temp; | |
12310 | ||
e56c4463 JL |
12311 | /* copy_rtx will not make unique copies of registers, so we need to |
12312 | ensure we don't have unwanted sharing here. */ | |
12313 | if (reg == reg2) | |
12314 | reg = gen_raw_REG (GET_MODE (reg), REGNO (reg)); | |
12315 | ||
12316 | if (reg == rreg) | |
12317 | reg = gen_raw_REG (GET_MODE (reg), REGNO (reg)); | |
12318 | ||
9ebbca7d GK |
12319 | real = copy_rtx (PATTERN (insn)); |
12320 | ||
89e7058f AH |
12321 | if (reg2 != NULL_RTX) |
12322 | real = replace_rtx (real, reg2, rreg); | |
f676971a EC |
12323 | |
12324 | real = replace_rtx (real, reg, | |
9ebbca7d GK |
12325 | gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode, |
12326 | STACK_POINTER_REGNUM), | |
12327 | GEN_INT (val))); | |
f676971a | 12328 | |
9ebbca7d GK |
12329 | /* We expect that 'real' is either a SET or a PARALLEL containing |
12330 | SETs (and possibly other stuff). In a PARALLEL, all the SETs | |
12331 | are important so they all have to be marked RTX_FRAME_RELATED_P. */ | |
12332 | ||
12333 | if (GET_CODE (real) == SET) | |
12334 | { | |
12335 | rtx set = real; | |
f676971a | 12336 | |
9ebbca7d GK |
12337 | temp = simplify_rtx (SET_SRC (set)); |
12338 | if (temp) | |
12339 | SET_SRC (set) = temp; | |
12340 | temp = simplify_rtx (SET_DEST (set)); | |
12341 | if (temp) | |
12342 | SET_DEST (set) = temp; | |
12343 | if (GET_CODE (SET_DEST (set)) == MEM) | |
38c1f2d7 | 12344 | { |
9ebbca7d GK |
12345 | temp = simplify_rtx (XEXP (SET_DEST (set), 0)); |
12346 | if (temp) | |
12347 | XEXP (SET_DEST (set), 0) = temp; | |
38c1f2d7 | 12348 | } |
38c1f2d7 | 12349 | } |
9ebbca7d GK |
12350 | else if (GET_CODE (real) == PARALLEL) |
12351 | { | |
12352 | int i; | |
12353 | for (i = 0; i < XVECLEN (real, 0); i++) | |
12354 | if (GET_CODE (XVECEXP (real, 0, i)) == SET) | |
12355 | { | |
12356 | rtx set = XVECEXP (real, 0, i); | |
f676971a | 12357 | |
9ebbca7d GK |
12358 | temp = simplify_rtx (SET_SRC (set)); |
12359 | if (temp) | |
12360 | SET_SRC (set) = temp; | |
12361 | temp = simplify_rtx (SET_DEST (set)); | |
12362 | if (temp) | |
12363 | SET_DEST (set) = temp; | |
12364 | if (GET_CODE (SET_DEST (set)) == MEM) | |
12365 | { | |
12366 | temp = simplify_rtx (XEXP (SET_DEST (set), 0)); | |
12367 | if (temp) | |
12368 | XEXP (SET_DEST (set), 0) = temp; | |
12369 | } | |
12370 | RTX_FRAME_RELATED_P (set) = 1; | |
12371 | } | |
12372 | } | |
12373 | else | |
a4f6c312 | 12374 | abort (); |
c19de7aa AH |
12375 | |
12376 | if (TARGET_SPE) | |
12377 | real = spe_synthesize_frame_save (real); | |
12378 | ||
9ebbca7d GK |
12379 | RTX_FRAME_RELATED_P (insn) = 1; |
12380 | REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, | |
12381 | real, | |
12382 | REG_NOTES (insn)); | |
38c1f2d7 MM |
12383 | } |
12384 | ||
c19de7aa AH |
12385 | /* Given an SPE frame note, return a PARALLEL of SETs with the |
12386 | original note, plus a synthetic register save. */ | |
12387 | ||
12388 | static rtx | |
a2369ed3 | 12389 | spe_synthesize_frame_save (rtx real) |
c19de7aa AH |
12390 | { |
12391 | rtx synth, offset, reg, real2; | |
12392 | ||
12393 | if (GET_CODE (real) != SET | |
12394 | || GET_MODE (SET_SRC (real)) != V2SImode) | |
12395 | return real; | |
12396 | ||
12397 | /* For the SPE, registers saved in 64-bits, get a PARALLEL for their | |
12398 | frame related note. The parallel contains a set of the register | |
41f3a930 | 12399 | being saved, and another set to a synthetic register (n+1200). |
c19de7aa AH |
12400 | This is so we can differentiate between 64-bit and 32-bit saves. |
12401 | Words cannot describe this nastiness. */ | |
12402 | ||
12403 | if (GET_CODE (SET_DEST (real)) != MEM | |
12404 | || GET_CODE (XEXP (SET_DEST (real), 0)) != PLUS | |
12405 | || GET_CODE (SET_SRC (real)) != REG) | |
12406 | abort (); | |
12407 | ||
12408 | /* Transform: | |
12409 | (set (mem (plus (reg x) (const y))) | |
12410 | (reg z)) | |
12411 | into: | |
12412 | (set (mem (plus (reg x) (const y+4))) | |
41f3a930 | 12413 | (reg z+1200)) |
c19de7aa AH |
12414 | */ |
12415 | ||
12416 | real2 = copy_rtx (real); | |
12417 | PUT_MODE (SET_DEST (real2), SImode); | |
12418 | reg = SET_SRC (real2); | |
12419 | real2 = replace_rtx (real2, reg, gen_rtx_REG (SImode, REGNO (reg))); | |
12420 | synth = copy_rtx (real2); | |
12421 | ||
12422 | if (BYTES_BIG_ENDIAN) | |
12423 | { | |
12424 | offset = XEXP (XEXP (SET_DEST (real2), 0), 1); | |
12425 | real2 = replace_rtx (real2, offset, GEN_INT (INTVAL (offset) + 4)); | |
12426 | } | |
12427 | ||
12428 | reg = SET_SRC (synth); | |
41f3a930 | 12429 | |
c19de7aa | 12430 | synth = replace_rtx (synth, reg, |
41f3a930 | 12431 | gen_rtx_REG (SImode, REGNO (reg) + 1200)); |
c19de7aa AH |
12432 | |
12433 | offset = XEXP (XEXP (SET_DEST (synth), 0), 1); | |
12434 | synth = replace_rtx (synth, offset, | |
12435 | GEN_INT (INTVAL (offset) | |
12436 | + (BYTES_BIG_ENDIAN ? 0 : 4))); | |
12437 | ||
12438 | RTX_FRAME_RELATED_P (synth) = 1; | |
12439 | RTX_FRAME_RELATED_P (real2) = 1; | |
12440 | if (BYTES_BIG_ENDIAN) | |
12441 | real = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, synth, real2)); | |
12442 | else | |
12443 | real = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, real2, synth)); | |
12444 | ||
12445 | return real; | |
12446 | } | |
12447 | ||
00b960c7 AH |
12448 | /* Returns an insn that has a vrsave set operation with the |
12449 | appropriate CLOBBERs. */ | |
12450 | ||
12451 | static rtx | |
a2369ed3 | 12452 | generate_set_vrsave (rtx reg, rs6000_stack_t *info, int epiloguep) |
00b960c7 AH |
12453 | { |
12454 | int nclobs, i; | |
12455 | rtx insn, clobs[TOTAL_ALTIVEC_REGS + 1]; | |
a004eb82 | 12456 | rtx vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO); |
00b960c7 | 12457 | |
a004eb82 AH |
12458 | clobs[0] |
12459 | = gen_rtx_SET (VOIDmode, | |
12460 | vrsave, | |
12461 | gen_rtx_UNSPEC_VOLATILE (SImode, | |
12462 | gen_rtvec (2, reg, vrsave), | |
12463 | 30)); | |
00b960c7 AH |
12464 | |
12465 | nclobs = 1; | |
12466 | ||
9aa86737 AH |
12467 | /* We need to clobber the registers in the mask so the scheduler |
12468 | does not move sets to VRSAVE before sets of AltiVec registers. | |
12469 | ||
12470 | However, if the function receives nonlocal gotos, reload will set | |
12471 | all call saved registers live. We will end up with: | |
12472 | ||
12473 | (set (reg 999) (mem)) | |
12474 | (parallel [ (set (reg vrsave) (unspec blah)) | |
12475 | (clobber (reg 999))]) | |
12476 | ||
12477 | The clobber will cause the store into reg 999 to be dead, and | |
12478 | flow will attempt to delete an epilogue insn. In this case, we | |
12479 | need an unspec use/set of the register. */ | |
00b960c7 AH |
12480 | |
12481 | for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i) | |
44688022 | 12482 | if (info->vrsave_mask & ALTIVEC_REG_BIT (i)) |
9aa86737 AH |
12483 | { |
12484 | if (!epiloguep || call_used_regs [i]) | |
12485 | clobs[nclobs++] = gen_rtx_CLOBBER (VOIDmode, | |
12486 | gen_rtx_REG (V4SImode, i)); | |
12487 | else | |
12488 | { | |
12489 | rtx reg = gen_rtx_REG (V4SImode, i); | |
9aa86737 AH |
12490 | |
12491 | clobs[nclobs++] | |
a004eb82 AH |
12492 | = gen_rtx_SET (VOIDmode, |
12493 | reg, | |
12494 | gen_rtx_UNSPEC (V4SImode, | |
12495 | gen_rtvec (1, reg), 27)); | |
9aa86737 AH |
12496 | } |
12497 | } | |
00b960c7 AH |
12498 | |
12499 | insn = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (nclobs)); | |
12500 | ||
12501 | for (i = 0; i < nclobs; ++i) | |
12502 | XVECEXP (insn, 0, i) = clobs[i]; | |
12503 | ||
12504 | return insn; | |
12505 | } | |
12506 | ||
89e7058f AH |
12507 | /* Save a register into the frame, and emit RTX_FRAME_RELATED_P notes. |
12508 | Save REGNO into [FRAME_REG + OFFSET] in mode MODE. */ | |
12509 | ||
12510 | static void | |
f676971a | 12511 | emit_frame_save (rtx frame_reg, rtx frame_ptr, enum machine_mode mode, |
d1d0c603 | 12512 | unsigned int regno, int offset, HOST_WIDE_INT total_size) |
89e7058f AH |
12513 | { |
12514 | rtx reg, offset_rtx, insn, mem, addr, int_rtx; | |
12515 | rtx replacea, replaceb; | |
12516 | ||
12517 | int_rtx = GEN_INT (offset); | |
12518 | ||
12519 | /* Some cases that need register indexed addressing. */ | |
12520 | if ((TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode)) | |
4d4cbc0e | 12521 | || (TARGET_E500_DOUBLE && mode == DFmode) |
a3170dc6 AH |
12522 | || (TARGET_SPE_ABI |
12523 | && SPE_VECTOR_MODE (mode) | |
12524 | && !SPE_CONST_OFFSET_OK (offset))) | |
89e7058f AH |
12525 | { |
12526 | /* Whomever calls us must make sure r11 is available in the | |
c4ad648e | 12527 | flow path of instructions in the prologue. */ |
89e7058f AH |
12528 | offset_rtx = gen_rtx_REG (Pmode, 11); |
12529 | emit_move_insn (offset_rtx, int_rtx); | |
12530 | ||
12531 | replacea = offset_rtx; | |
12532 | replaceb = int_rtx; | |
12533 | } | |
12534 | else | |
12535 | { | |
12536 | offset_rtx = int_rtx; | |
12537 | replacea = NULL_RTX; | |
12538 | replaceb = NULL_RTX; | |
12539 | } | |
12540 | ||
12541 | reg = gen_rtx_REG (mode, regno); | |
12542 | addr = gen_rtx_PLUS (Pmode, frame_reg, offset_rtx); | |
12543 | mem = gen_rtx_MEM (mode, addr); | |
12544 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
12545 | ||
12546 | insn = emit_move_insn (mem, reg); | |
12547 | ||
12548 | rs6000_frame_related (insn, frame_ptr, total_size, replacea, replaceb); | |
12549 | } | |
12550 | ||
a3170dc6 AH |
12551 | /* Emit an offset memory reference suitable for a frame store, while |
12552 | converting to a valid addressing mode. */ | |
12553 | ||
12554 | static rtx | |
a2369ed3 | 12555 | gen_frame_mem_offset (enum machine_mode mode, rtx reg, int offset) |
a3170dc6 AH |
12556 | { |
12557 | rtx int_rtx, offset_rtx; | |
12558 | ||
12559 | int_rtx = GEN_INT (offset); | |
12560 | ||
4d4cbc0e AH |
12561 | if ((TARGET_SPE_ABI && SPE_VECTOR_MODE (mode)) |
12562 | || (TARGET_E500_DOUBLE && mode == DFmode)) | |
a3170dc6 AH |
12563 | { |
12564 | offset_rtx = gen_rtx_REG (Pmode, FIXED_SCRATCH); | |
12565 | emit_move_insn (offset_rtx, int_rtx); | |
12566 | } | |
12567 | else | |
12568 | offset_rtx = int_rtx; | |
12569 | ||
12570 | return gen_rtx_MEM (mode, gen_rtx_PLUS (Pmode, reg, offset_rtx)); | |
12571 | } | |
12572 | ||
699c914a MS |
12573 | #ifndef TARGET_FIX_AND_CONTINUE |
12574 | #define TARGET_FIX_AND_CONTINUE 0 | |
12575 | #endif | |
12576 | ||
9ebbca7d GK |
12577 | /* Emit function prologue as insns. */ |
12578 | ||
9878760c | 12579 | void |
863d938c | 12580 | rs6000_emit_prologue (void) |
9878760c | 12581 | { |
4697a36c | 12582 | rs6000_stack_t *info = rs6000_stack_info (); |
0e67400a | 12583 | enum machine_mode reg_mode = Pmode; |
327e5343 | 12584 | int reg_size = TARGET_32BIT ? 4 : 8; |
9ebbca7d GK |
12585 | rtx sp_reg_rtx = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM); |
12586 | rtx frame_ptr_rtx = gen_rtx_REG (Pmode, 12); | |
12587 | rtx frame_reg_rtx = sp_reg_rtx; | |
b78d48dd | 12588 | rtx cr_save_rtx = NULL_RTX; |
9ebbca7d GK |
12589 | rtx insn; |
12590 | int saving_FPRs_inline; | |
12591 | int using_store_multiple; | |
12592 | HOST_WIDE_INT sp_offset = 0; | |
f676971a | 12593 | |
699c914a MS |
12594 | if (TARGET_FIX_AND_CONTINUE) |
12595 | { | |
12596 | /* gdb on darwin arranges to forward a function from the old | |
12597 | address by modifying the first 4 instructions of the function | |
12598 | to branch to the overriding function. This is necessary to | |
12599 | permit function pointers that point to the old function to | |
12600 | actually forward to the new function. */ | |
12601 | emit_insn (gen_nop ()); | |
12602 | emit_insn (gen_nop ()); | |
12603 | emit_insn (gen_nop ()); | |
12604 | emit_insn (gen_nop ()); | |
12605 | } | |
12606 | ||
12607 | if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0) | |
12608 | { | |
12609 | reg_mode = V2SImode; | |
12610 | reg_size = 8; | |
12611 | } | |
a3170dc6 | 12612 | |
9ebbca7d | 12613 | using_store_multiple = (TARGET_MULTIPLE && ! TARGET_POWERPC64 |
c19de7aa AH |
12614 | && (!TARGET_SPE_ABI |
12615 | || info->spe_64bit_regs_used == 0) | |
9ebbca7d GK |
12616 | && info->first_gp_reg_save < 31); |
12617 | saving_FPRs_inline = (info->first_fp_reg_save == 64 | |
8c29550d | 12618 | || FP_SAVE_INLINE (info->first_fp_reg_save) |
acd0b319 | 12619 | || current_function_calls_eh_return |
8c29550d | 12620 | || cfun->machine->ra_need_lr); |
9ebbca7d GK |
12621 | |
12622 | /* For V.4, update stack before we do any saving and set back pointer. */ | |
fc4767bb | 12623 | if (info->push_p |
acd0b319 AM |
12624 | && (DEFAULT_ABI == ABI_V4 |
12625 | || current_function_calls_eh_return)) | |
9ebbca7d GK |
12626 | { |
12627 | if (info->total_size < 32767) | |
12628 | sp_offset = info->total_size; | |
12629 | else | |
12630 | frame_reg_rtx = frame_ptr_rtx; | |
f676971a | 12631 | rs6000_emit_allocate_stack (info->total_size, |
9ebbca7d GK |
12632 | (frame_reg_rtx != sp_reg_rtx |
12633 | && (info->cr_save_p | |
12634 | || info->lr_save_p | |
12635 | || info->first_fp_reg_save < 64 | |
12636 | || info->first_gp_reg_save < 32 | |
12637 | ))); | |
12638 | if (frame_reg_rtx != sp_reg_rtx) | |
12639 | rs6000_emit_stack_tie (); | |
12640 | } | |
12641 | ||
d62294f5 | 12642 | /* Handle world saves specially here. */ |
f57fe068 | 12643 | if (WORLD_SAVE_P (info)) |
d62294f5 FJ |
12644 | { |
12645 | int i, j, sz; | |
12646 | rtx treg; | |
12647 | rtvec p; | |
12648 | ||
12649 | /* save_world expects lr in r0. */ | |
12650 | if (info->lr_save_p) | |
c4ad648e AM |
12651 | { |
12652 | insn = emit_move_insn (gen_rtx_REG (Pmode, 0), | |
12653 | gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)); | |
12654 | RTX_FRAME_RELATED_P (insn) = 1; | |
12655 | } | |
d62294f5 FJ |
12656 | |
12657 | /* The SAVE_WORLD and RESTORE_WORLD routines make a number of | |
c4ad648e AM |
12658 | assumptions about the offsets of various bits of the stack |
12659 | frame. Abort if things aren't what they should be. */ | |
d62294f5 | 12660 | if (info->gp_save_offset != -220 |
c4ad648e AM |
12661 | || info->fp_save_offset != -144 |
12662 | || info->lr_save_offset != 8 | |
12663 | || info->cr_save_offset != 4 | |
12664 | || !info->push_p | |
12665 | || !info->lr_save_p | |
12666 | || (current_function_calls_eh_return && info->ehrd_offset != -432) | |
12667 | || (info->vrsave_save_offset != -224 | |
12668 | || info->altivec_save_offset != (-224 -16 -192))) | |
12669 | abort (); | |
d62294f5 FJ |
12670 | |
12671 | treg = gen_rtx_REG (SImode, 11); | |
12672 | emit_move_insn (treg, GEN_INT (-info->total_size)); | |
12673 | ||
12674 | /* SAVE_WORLD takes the caller's LR in R0 and the frame size | |
c4ad648e | 12675 | in R11. It also clobbers R12, so beware! */ |
d62294f5 FJ |
12676 | |
12677 | /* Preserve CR2 for save_world prologues */ | |
12678 | sz = 6; | |
12679 | sz += 32 - info->first_gp_reg_save; | |
12680 | sz += 64 - info->first_fp_reg_save; | |
12681 | sz += LAST_ALTIVEC_REGNO - info->first_altivec_reg_save + 1; | |
12682 | p = rtvec_alloc (sz); | |
12683 | j = 0; | |
12684 | RTVEC_ELT (p, j++) = gen_rtx_CLOBBER (VOIDmode, | |
c4ad648e AM |
12685 | gen_rtx_REG (Pmode, |
12686 | LINK_REGISTER_REGNUM)); | |
d62294f5 | 12687 | RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode, |
c4ad648e AM |
12688 | gen_rtx_SYMBOL_REF (Pmode, |
12689 | "*save_world")); | |
d62294f5 | 12690 | /* We do floats first so that the instruction pattern matches |
c4ad648e AM |
12691 | properly. */ |
12692 | for (i = 0; i < 64 - info->first_fp_reg_save; i++) | |
12693 | { | |
12694 | rtx reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i); | |
12695 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
12696 | GEN_INT (info->fp_save_offset | |
12697 | + sp_offset + 8 * i)); | |
12698 | rtx mem = gen_rtx_MEM (DFmode, addr); | |
12699 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
12700 | ||
12701 | RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg); | |
12702 | } | |
d62294f5 | 12703 | for (i = 0; info->first_altivec_reg_save + i <= LAST_ALTIVEC_REGNO; i++) |
c4ad648e AM |
12704 | { |
12705 | rtx reg = gen_rtx_REG (V4SImode, info->first_altivec_reg_save + i); | |
12706 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
12707 | GEN_INT (info->altivec_save_offset | |
12708 | + sp_offset + 16 * i)); | |
12709 | rtx mem = gen_rtx_MEM (V4SImode, addr); | |
12710 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
12711 | ||
12712 | RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg); | |
12713 | } | |
d62294f5 | 12714 | for (i = 0; i < 32 - info->first_gp_reg_save; i++) |
c4ad648e AM |
12715 | { |
12716 | rtx reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i); | |
12717 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
12718 | GEN_INT (info->gp_save_offset | |
12719 | + sp_offset + reg_size * i)); | |
12720 | rtx mem = gen_rtx_MEM (reg_mode, addr); | |
12721 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
12722 | ||
12723 | RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg); | |
12724 | } | |
12725 | ||
12726 | { | |
12727 | /* CR register traditionally saved as CR2. */ | |
12728 | rtx reg = gen_rtx_REG (reg_mode, CR2_REGNO); | |
12729 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
12730 | GEN_INT (info->cr_save_offset | |
12731 | + sp_offset)); | |
12732 | rtx mem = gen_rtx_MEM (reg_mode, addr); | |
12733 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
12734 | ||
12735 | RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg); | |
12736 | } | |
d62294f5 FJ |
12737 | /* Prevent any attempt to delete the setting of r0 and treg! */ |
12738 | RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode, gen_rtx_REG (Pmode, 0)); | |
12739 | RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode, treg); | |
12740 | RTVEC_ELT (p, j++) = gen_rtx_CLOBBER (VOIDmode, sp_reg_rtx); | |
12741 | ||
12742 | insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p)); | |
12743 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, | |
c4ad648e | 12744 | NULL_RTX, NULL_RTX); |
d62294f5 FJ |
12745 | |
12746 | if (current_function_calls_eh_return) | |
c4ad648e AM |
12747 | { |
12748 | unsigned int i; | |
12749 | for (i = 0; ; ++i) | |
12750 | { | |
12751 | unsigned int regno = EH_RETURN_DATA_REGNO (i); | |
12752 | if (regno == INVALID_REGNUM) | |
12753 | break; | |
12754 | emit_frame_save (frame_reg_rtx, frame_ptr_rtx, reg_mode, regno, | |
12755 | info->ehrd_offset + sp_offset | |
12756 | + reg_size * (int) i, | |
12757 | info->total_size); | |
12758 | } | |
12759 | } | |
d62294f5 FJ |
12760 | } |
12761 | ||
9aa86737 | 12762 | /* Save AltiVec registers if needed. */ |
f57fe068 | 12763 | if (!WORLD_SAVE_P (info) && TARGET_ALTIVEC_ABI && info->altivec_size != 0) |
9aa86737 AH |
12764 | { |
12765 | int i; | |
12766 | ||
12767 | /* There should be a non inline version of this, for when we | |
12768 | are saving lots of vector registers. */ | |
12769 | for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i) | |
12770 | if (info->vrsave_mask & ALTIVEC_REG_BIT (i)) | |
12771 | { | |
12772 | rtx areg, savereg, mem; | |
12773 | int offset; | |
12774 | ||
12775 | offset = info->altivec_save_offset + sp_offset | |
12776 | + 16 * (i - info->first_altivec_reg_save); | |
12777 | ||
12778 | savereg = gen_rtx_REG (V4SImode, i); | |
12779 | ||
12780 | areg = gen_rtx_REG (Pmode, 0); | |
12781 | emit_move_insn (areg, GEN_INT (offset)); | |
12782 | ||
12783 | /* AltiVec addressing mode is [reg+reg]. */ | |
12784 | mem = gen_rtx_MEM (V4SImode, | |
12785 | gen_rtx_PLUS (Pmode, frame_reg_rtx, areg)); | |
f676971a | 12786 | |
9aa86737 AH |
12787 | set_mem_alias_set (mem, rs6000_sr_alias_set); |
12788 | ||
12789 | insn = emit_move_insn (mem, savereg); | |
12790 | ||
5c242421 SB |
12791 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, |
12792 | areg, GEN_INT (offset)); | |
9aa86737 AH |
12793 | } |
12794 | } | |
12795 | ||
12796 | /* VRSAVE is a bit vector representing which AltiVec registers | |
12797 | are used. The OS uses this to determine which vector | |
12798 | registers to save on a context switch. We need to save | |
12799 | VRSAVE on the stack frame, add whatever AltiVec registers we | |
12800 | used in this function, and do the corresponding magic in the | |
12801 | epilogue. */ | |
12802 | ||
4d774ff8 | 12803 | if (TARGET_ALTIVEC && TARGET_ALTIVEC_VRSAVE |
f57fe068 | 12804 | && !WORLD_SAVE_P (info) && info->vrsave_mask != 0) |
9aa86737 | 12805 | { |
a004eb82 | 12806 | rtx reg, mem, vrsave; |
9aa86737 AH |
12807 | int offset; |
12808 | ||
eab97e44 AM |
12809 | /* Get VRSAVE onto a GPR. Note that ABI_V4 might be using r12 |
12810 | as frame_reg_rtx and r11 as the static chain pointer for | |
12811 | nested functions. */ | |
12812 | reg = gen_rtx_REG (SImode, 0); | |
a004eb82 | 12813 | vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO); |
b188f760 AH |
12814 | if (TARGET_MACHO) |
12815 | emit_insn (gen_get_vrsave_internal (reg)); | |
12816 | else | |
12817 | emit_insn (gen_rtx_SET (VOIDmode, reg, vrsave)); | |
9aa86737 AH |
12818 | |
12819 | /* Save VRSAVE. */ | |
12820 | offset = info->vrsave_save_offset + sp_offset; | |
12821 | mem | |
12822 | = gen_rtx_MEM (SImode, | |
12823 | gen_rtx_PLUS (Pmode, frame_reg_rtx, GEN_INT (offset))); | |
12824 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
12825 | insn = emit_move_insn (mem, reg); | |
12826 | ||
12827 | /* Include the registers in the mask. */ | |
12828 | emit_insn (gen_iorsi3 (reg, reg, GEN_INT ((int) info->vrsave_mask))); | |
12829 | ||
12830 | insn = emit_insn (generate_set_vrsave (reg, info, 0)); | |
12831 | } | |
12832 | ||
9ebbca7d | 12833 | /* If we use the link register, get it into r0. */ |
f57fe068 | 12834 | if (!WORLD_SAVE_P (info) && info->lr_save_p) |
f8a57be8 GK |
12835 | { |
12836 | insn = emit_move_insn (gen_rtx_REG (Pmode, 0), | |
12837 | gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)); | |
12838 | RTX_FRAME_RELATED_P (insn) = 1; | |
12839 | } | |
9ebbca7d GK |
12840 | |
12841 | /* If we need to save CR, put it into r12. */ | |
f57fe068 | 12842 | if (!WORLD_SAVE_P (info) && info->cr_save_p && frame_reg_rtx != frame_ptr_rtx) |
9ebbca7d | 12843 | { |
f8a57be8 | 12844 | rtx set; |
f676971a | 12845 | |
9ebbca7d | 12846 | cr_save_rtx = gen_rtx_REG (SImode, 12); |
f8a57be8 GK |
12847 | insn = emit_insn (gen_movesi_from_cr (cr_save_rtx)); |
12848 | RTX_FRAME_RELATED_P (insn) = 1; | |
12849 | /* Now, there's no way that dwarf2out_frame_debug_expr is going | |
12850 | to understand '(unspec:SI [(reg:CC 68) ...] UNSPEC_MOVESI_FROM_CR)'. | |
12851 | But that's OK. All we have to do is specify that _one_ condition | |
12852 | code register is saved in this stack slot. The thrower's epilogue | |
12853 | will then restore all the call-saved registers. | |
12854 | We use CR2_REGNO (70) to be compatible with gcc-2.95 on Linux. */ | |
12855 | set = gen_rtx_SET (VOIDmode, cr_save_rtx, | |
12856 | gen_rtx_REG (SImode, CR2_REGNO)); | |
12857 | REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, | |
12858 | set, | |
12859 | REG_NOTES (insn)); | |
9ebbca7d GK |
12860 | } |
12861 | ||
a4f6c312 SS |
12862 | /* Do any required saving of fpr's. If only one or two to save, do |
12863 | it ourselves. Otherwise, call function. */ | |
f57fe068 | 12864 | if (!WORLD_SAVE_P (info) && saving_FPRs_inline) |
9ebbca7d GK |
12865 | { |
12866 | int i; | |
12867 | for (i = 0; i < 64 - info->first_fp_reg_save; i++) | |
f676971a | 12868 | if ((regs_ever_live[info->first_fp_reg_save+i] |
9ebbca7d | 12869 | && ! call_used_regs[info->first_fp_reg_save+i])) |
89e7058f AH |
12870 | emit_frame_save (frame_reg_rtx, frame_ptr_rtx, DFmode, |
12871 | info->first_fp_reg_save + i, | |
12872 | info->fp_save_offset + sp_offset + 8 * i, | |
12873 | info->total_size); | |
9ebbca7d | 12874 | } |
f57fe068 | 12875 | else if (!WORLD_SAVE_P (info) && info->first_fp_reg_save != 64) |
9ebbca7d GK |
12876 | { |
12877 | int i; | |
12878 | char rname[30]; | |
520a57c8 | 12879 | const char *alloc_rname; |
9ebbca7d GK |
12880 | rtvec p; |
12881 | p = rtvec_alloc (2 + 64 - info->first_fp_reg_save); | |
f676971a EC |
12882 | |
12883 | RTVEC_ELT (p, 0) = gen_rtx_CLOBBER (VOIDmode, | |
12884 | gen_rtx_REG (Pmode, | |
9ebbca7d GK |
12885 | LINK_REGISTER_REGNUM)); |
12886 | sprintf (rname, "%s%d%s", SAVE_FP_PREFIX, | |
12887 | info->first_fp_reg_save - 32, SAVE_FP_SUFFIX); | |
a8a05998 | 12888 | alloc_rname = ggc_strdup (rname); |
9ebbca7d GK |
12889 | RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode, |
12890 | gen_rtx_SYMBOL_REF (Pmode, | |
12891 | alloc_rname)); | |
12892 | for (i = 0; i < 64 - info->first_fp_reg_save; i++) | |
12893 | { | |
12894 | rtx addr, reg, mem; | |
12895 | reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i); | |
12896 | addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
f676971a | 12897 | GEN_INT (info->fp_save_offset |
9ebbca7d GK |
12898 | + sp_offset + 8*i)); |
12899 | mem = gen_rtx_MEM (DFmode, addr); | |
ba4828e0 | 12900 | set_mem_alias_set (mem, rs6000_sr_alias_set); |
9ebbca7d GK |
12901 | |
12902 | RTVEC_ELT (p, i + 2) = gen_rtx_SET (VOIDmode, mem, reg); | |
12903 | } | |
12904 | insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p)); | |
f676971a | 12905 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, |
9ebbca7d GK |
12906 | NULL_RTX, NULL_RTX); |
12907 | } | |
b6c9286a | 12908 | |
9ebbca7d GK |
12909 | /* Save GPRs. This is done as a PARALLEL if we are using |
12910 | the store-multiple instructions. */ | |
f57fe068 | 12911 | if (!WORLD_SAVE_P (info) && using_store_multiple) |
b6c9286a | 12912 | { |
308c142a | 12913 | rtvec p; |
9ebbca7d GK |
12914 | int i; |
12915 | p = rtvec_alloc (32 - info->first_gp_reg_save); | |
9ebbca7d GK |
12916 | for (i = 0; i < 32 - info->first_gp_reg_save; i++) |
12917 | { | |
12918 | rtx addr, reg, mem; | |
12919 | reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i); | |
f676971a EC |
12920 | addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, |
12921 | GEN_INT (info->gp_save_offset | |
12922 | + sp_offset | |
9ebbca7d GK |
12923 | + reg_size * i)); |
12924 | mem = gen_rtx_MEM (reg_mode, addr); | |
ba4828e0 | 12925 | set_mem_alias_set (mem, rs6000_sr_alias_set); |
9ebbca7d GK |
12926 | |
12927 | RTVEC_ELT (p, i) = gen_rtx_SET (VOIDmode, mem, reg); | |
12928 | } | |
12929 | insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p)); | |
f676971a | 12930 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, |
9ebbca7d | 12931 | NULL_RTX, NULL_RTX); |
b6c9286a | 12932 | } |
f57fe068 | 12933 | else if (!WORLD_SAVE_P (info)) |
b6c9286a | 12934 | { |
9ebbca7d GK |
12935 | int i; |
12936 | for (i = 0; i < 32 - info->first_gp_reg_save; i++) | |
f676971a | 12937 | if ((regs_ever_live[info->first_gp_reg_save+i] |
b4db40bf JJ |
12938 | && (! call_used_regs[info->first_gp_reg_save+i] |
12939 | || (i+info->first_gp_reg_save | |
12940 | == RS6000_PIC_OFFSET_TABLE_REGNUM | |
12941 | && TARGET_TOC && TARGET_MINIMAL_TOC))) | |
1db02437 | 12942 | || (i+info->first_gp_reg_save == RS6000_PIC_OFFSET_TABLE_REGNUM |
14f00213 | 12943 | && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0) |
f607bc57 | 12944 | || (DEFAULT_ABI == ABI_DARWIN && flag_pic)))) |
a3170dc6 AH |
12945 | { |
12946 | rtx addr, reg, mem; | |
12947 | reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i); | |
12948 | ||
c19de7aa | 12949 | if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0) |
a3170dc6 AH |
12950 | { |
12951 | int offset = info->spe_gp_save_offset + sp_offset + 8 * i; | |
12952 | rtx b; | |
12953 | ||
12954 | if (!SPE_CONST_OFFSET_OK (offset)) | |
12955 | { | |
12956 | b = gen_rtx_REG (Pmode, FIXED_SCRATCH); | |
12957 | emit_move_insn (b, GEN_INT (offset)); | |
12958 | } | |
12959 | else | |
12960 | b = GEN_INT (offset); | |
12961 | ||
12962 | addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, b); | |
12963 | mem = gen_rtx_MEM (V2SImode, addr); | |
12964 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
12965 | insn = emit_move_insn (mem, reg); | |
12966 | ||
12967 | if (GET_CODE (b) == CONST_INT) | |
12968 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, | |
12969 | NULL_RTX, NULL_RTX); | |
12970 | else | |
12971 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, | |
12972 | b, GEN_INT (offset)); | |
12973 | } | |
12974 | else | |
12975 | { | |
f676971a EC |
12976 | addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, |
12977 | GEN_INT (info->gp_save_offset | |
12978 | + sp_offset | |
a3170dc6 AH |
12979 | + reg_size * i)); |
12980 | mem = gen_rtx_MEM (reg_mode, addr); | |
12981 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
12982 | ||
12983 | insn = emit_move_insn (mem, reg); | |
f676971a | 12984 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, |
a3170dc6 AH |
12985 | NULL_RTX, NULL_RTX); |
12986 | } | |
12987 | } | |
9ebbca7d GK |
12988 | } |
12989 | ||
83720594 RH |
12990 | /* ??? There's no need to emit actual instructions here, but it's the |
12991 | easiest way to get the frame unwind information emitted. */ | |
f57fe068 | 12992 | if (!WORLD_SAVE_P (info) && current_function_calls_eh_return) |
83720594 | 12993 | { |
78e1b90d DE |
12994 | unsigned int i, regno; |
12995 | ||
fc4767bb JJ |
12996 | /* In AIX ABI we need to pretend we save r2 here. */ |
12997 | if (TARGET_AIX) | |
12998 | { | |
12999 | rtx addr, reg, mem; | |
13000 | ||
13001 | reg = gen_rtx_REG (reg_mode, 2); | |
13002 | addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
13003 | GEN_INT (sp_offset + 5 * reg_size)); | |
13004 | mem = gen_rtx_MEM (reg_mode, addr); | |
13005 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
13006 | ||
13007 | insn = emit_move_insn (mem, reg); | |
f676971a | 13008 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, |
fc4767bb JJ |
13009 | NULL_RTX, NULL_RTX); |
13010 | PATTERN (insn) = gen_blockage (); | |
13011 | } | |
13012 | ||
83720594 RH |
13013 | for (i = 0; ; ++i) |
13014 | { | |
83720594 RH |
13015 | regno = EH_RETURN_DATA_REGNO (i); |
13016 | if (regno == INVALID_REGNUM) | |
13017 | break; | |
13018 | ||
89e7058f AH |
13019 | emit_frame_save (frame_reg_rtx, frame_ptr_rtx, reg_mode, regno, |
13020 | info->ehrd_offset + sp_offset | |
13021 | + reg_size * (int) i, | |
13022 | info->total_size); | |
83720594 RH |
13023 | } |
13024 | } | |
13025 | ||
9ebbca7d | 13026 | /* Save lr if we used it. */ |
f57fe068 | 13027 | if (!WORLD_SAVE_P (info) && info->lr_save_p) |
9ebbca7d GK |
13028 | { |
13029 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
13030 | GEN_INT (info->lr_save_offset + sp_offset)); | |
13031 | rtx reg = gen_rtx_REG (Pmode, 0); | |
13032 | rtx mem = gen_rtx_MEM (Pmode, addr); | |
13033 | /* This should not be of rs6000_sr_alias_set, because of | |
13034 | __builtin_return_address. */ | |
f676971a | 13035 | |
9ebbca7d | 13036 | insn = emit_move_insn (mem, reg); |
f676971a | 13037 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, |
f8a57be8 | 13038 | NULL_RTX, NULL_RTX); |
9ebbca7d GK |
13039 | } |
13040 | ||
13041 | /* Save CR if we use any that must be preserved. */ | |
f57fe068 | 13042 | if (!WORLD_SAVE_P (info) && info->cr_save_p) |
9ebbca7d GK |
13043 | { |
13044 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
13045 | GEN_INT (info->cr_save_offset + sp_offset)); | |
13046 | rtx mem = gen_rtx_MEM (SImode, addr); | |
f8a57be8 GK |
13047 | /* See the large comment above about why CR2_REGNO is used. */ |
13048 | rtx magic_eh_cr_reg = gen_rtx_REG (SImode, CR2_REGNO); | |
ba4828e0 RK |
13049 | |
13050 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
9ebbca7d GK |
13051 | |
13052 | /* If r12 was used to hold the original sp, copy cr into r0 now | |
13053 | that it's free. */ | |
13054 | if (REGNO (frame_reg_rtx) == 12) | |
13055 | { | |
f8a57be8 GK |
13056 | rtx set; |
13057 | ||
9ebbca7d | 13058 | cr_save_rtx = gen_rtx_REG (SImode, 0); |
f8a57be8 GK |
13059 | insn = emit_insn (gen_movesi_from_cr (cr_save_rtx)); |
13060 | RTX_FRAME_RELATED_P (insn) = 1; | |
13061 | set = gen_rtx_SET (VOIDmode, cr_save_rtx, magic_eh_cr_reg); | |
13062 | REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, | |
13063 | set, | |
13064 | REG_NOTES (insn)); | |
f676971a | 13065 | |
9ebbca7d GK |
13066 | } |
13067 | insn = emit_move_insn (mem, cr_save_rtx); | |
13068 | ||
f676971a | 13069 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, |
f8a57be8 | 13070 | NULL_RTX, NULL_RTX); |
9ebbca7d GK |
13071 | } |
13072 | ||
f676971a | 13073 | /* Update stack and set back pointer unless this is V.4, |
9ebbca7d | 13074 | for which it was done previously. */ |
f57fe068 | 13075 | if (!WORLD_SAVE_P (info) && info->push_p |
fc4767bb | 13076 | && !(DEFAULT_ABI == ABI_V4 || current_function_calls_eh_return)) |
9ebbca7d GK |
13077 | rs6000_emit_allocate_stack (info->total_size, FALSE); |
13078 | ||
13079 | /* Set frame pointer, if needed. */ | |
13080 | if (frame_pointer_needed) | |
13081 | { | |
f676971a | 13082 | insn = emit_move_insn (gen_rtx_REG (Pmode, FRAME_POINTER_REGNUM), |
9ebbca7d GK |
13083 | sp_reg_rtx); |
13084 | RTX_FRAME_RELATED_P (insn) = 1; | |
b6c9286a | 13085 | } |
9878760c | 13086 | |
1db02437 | 13087 | /* If we are using RS6000_PIC_OFFSET_TABLE_REGNUM, we need to set it up. */ |
9ebbca7d | 13088 | if ((TARGET_TOC && TARGET_MINIMAL_TOC && get_pool_size () != 0) |
f607bc57 | 13089 | || (DEFAULT_ABI == ABI_V4 && flag_pic == 1 |
1db02437 | 13090 | && regs_ever_live[RS6000_PIC_OFFSET_TABLE_REGNUM])) |
c4ad648e AM |
13091 | { |
13092 | /* If emit_load_toc_table will use the link register, we need to save | |
13093 | it. We use R12 for this purpose because emit_load_toc_table | |
13094 | can use register 0. This allows us to use a plain 'blr' to return | |
13095 | from the procedure more often. */ | |
13096 | int save_LR_around_toc_setup = (TARGET_ELF | |
13097 | && DEFAULT_ABI != ABI_AIX | |
13098 | && flag_pic | |
13099 | && ! info->lr_save_p | |
13100 | && EDGE_COUNT (EXIT_BLOCK_PTR->preds) > 0); | |
13101 | if (save_LR_around_toc_setup) | |
13102 | { | |
13103 | rtx lr = gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM); | |
f8a57be8 | 13104 | |
c4ad648e AM |
13105 | insn = emit_move_insn (frame_ptr_rtx, lr); |
13106 | rs6000_maybe_dead (insn); | |
13107 | RTX_FRAME_RELATED_P (insn) = 1; | |
f8a57be8 | 13108 | |
c4ad648e | 13109 | rs6000_emit_load_toc_table (TRUE); |
f8a57be8 | 13110 | |
c4ad648e AM |
13111 | insn = emit_move_insn (lr, frame_ptr_rtx); |
13112 | rs6000_maybe_dead (insn); | |
13113 | RTX_FRAME_RELATED_P (insn) = 1; | |
13114 | } | |
13115 | else | |
13116 | rs6000_emit_load_toc_table (TRUE); | |
13117 | } | |
ee890fe2 | 13118 | |
fcce224d | 13119 | #if TARGET_MACHO |
ee890fe2 SS |
13120 | if (DEFAULT_ABI == ABI_DARWIN |
13121 | && flag_pic && current_function_uses_pic_offset_table) | |
13122 | { | |
f8a57be8 | 13123 | rtx lr = gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM); |
11abc112 | 13124 | rtx src = machopic_function_base_sym (); |
ee890fe2 | 13125 | |
f8a57be8 | 13126 | rs6000_maybe_dead (emit_insn (gen_load_macho_picbase (lr, src))); |
ee890fe2 | 13127 | |
f676971a | 13128 | insn = emit_move_insn (gen_rtx_REG (Pmode, |
f8a57be8 GK |
13129 | RS6000_PIC_OFFSET_TABLE_REGNUM), |
13130 | lr); | |
13131 | rs6000_maybe_dead (insn); | |
ee890fe2 | 13132 | } |
fcce224d | 13133 | #endif |
9ebbca7d GK |
13134 | } |
13135 | ||
9ebbca7d | 13136 | /* Write function prologue. */ |
a4f6c312 | 13137 | |
08c148a8 | 13138 | static void |
f676971a | 13139 | rs6000_output_function_prologue (FILE *file, |
a2369ed3 | 13140 | HOST_WIDE_INT size ATTRIBUTE_UNUSED) |
9ebbca7d GK |
13141 | { |
13142 | rs6000_stack_t *info = rs6000_stack_info (); | |
13143 | ||
4697a36c MM |
13144 | if (TARGET_DEBUG_STACK) |
13145 | debug_stack_info (info); | |
9878760c | 13146 | |
a4f6c312 SS |
13147 | /* Write .extern for any function we will call to save and restore |
13148 | fp values. */ | |
13149 | if (info->first_fp_reg_save < 64 | |
13150 | && !FP_SAVE_INLINE (info->first_fp_reg_save)) | |
4d30c363 | 13151 | fprintf (file, "\t.extern %s%d%s\n\t.extern %s%d%s\n", |
4697a36c | 13152 | SAVE_FP_PREFIX, info->first_fp_reg_save - 32, SAVE_FP_SUFFIX, |
a4f6c312 SS |
13153 | RESTORE_FP_PREFIX, info->first_fp_reg_save - 32, |
13154 | RESTORE_FP_SUFFIX); | |
9878760c | 13155 | |
c764f757 RK |
13156 | /* Write .extern for AIX common mode routines, if needed. */ |
13157 | if (! TARGET_POWER && ! TARGET_POWERPC && ! common_mode_defined) | |
13158 | { | |
f6709c70 JW |
13159 | fputs ("\t.extern __mulh\n", file); |
13160 | fputs ("\t.extern __mull\n", file); | |
13161 | fputs ("\t.extern __divss\n", file); | |
13162 | fputs ("\t.extern __divus\n", file); | |
13163 | fputs ("\t.extern __quoss\n", file); | |
13164 | fputs ("\t.extern __quous\n", file); | |
c764f757 RK |
13165 | common_mode_defined = 1; |
13166 | } | |
9878760c | 13167 | |
9ebbca7d | 13168 | if (! HAVE_prologue) |
979721f8 | 13169 | { |
9ebbca7d | 13170 | start_sequence (); |
9dda4cc8 | 13171 | |
a4f6c312 SS |
13172 | /* A NOTE_INSN_DELETED is supposed to be at the start and end of |
13173 | the "toplevel" insn chain. */ | |
2e040219 | 13174 | emit_note (NOTE_INSN_DELETED); |
9ebbca7d | 13175 | rs6000_emit_prologue (); |
2e040219 | 13176 | emit_note (NOTE_INSN_DELETED); |
178c3eff | 13177 | |
a3c9585f | 13178 | /* Expand INSN_ADDRESSES so final() doesn't crash. */ |
178c3eff DJ |
13179 | { |
13180 | rtx insn; | |
13181 | unsigned addr = 0; | |
13182 | for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn)) | |
13183 | { | |
13184 | INSN_ADDRESSES_NEW (insn, addr); | |
13185 | addr += 4; | |
13186 | } | |
13187 | } | |
9dda4cc8 | 13188 | |
9ebbca7d | 13189 | if (TARGET_DEBUG_STACK) |
a4f6c312 SS |
13190 | debug_rtx_list (get_insns (), 100); |
13191 | final (get_insns (), file, FALSE, FALSE); | |
9ebbca7d | 13192 | end_sequence (); |
979721f8 MM |
13193 | } |
13194 | ||
9ebbca7d GK |
13195 | rs6000_pic_labelno++; |
13196 | } | |
f676971a | 13197 | |
9ebbca7d | 13198 | /* Emit function epilogue as insns. |
9878760c | 13199 | |
9ebbca7d GK |
13200 | At present, dwarf2out_frame_debug_expr doesn't understand |
13201 | register restores, so we don't bother setting RTX_FRAME_RELATED_P | |
13202 | anywhere in the epilogue. Most of the insns below would in any case | |
13203 | need special notes to explain where r11 is in relation to the stack. */ | |
9878760c | 13204 | |
9ebbca7d | 13205 | void |
a2369ed3 | 13206 | rs6000_emit_epilogue (int sibcall) |
9ebbca7d GK |
13207 | { |
13208 | rs6000_stack_t *info; | |
13209 | int restoring_FPRs_inline; | |
13210 | int using_load_multiple; | |
13211 | int using_mfcr_multiple; | |
13212 | int use_backchain_to_restore_sp; | |
13213 | int sp_offset = 0; | |
13214 | rtx sp_reg_rtx = gen_rtx_REG (Pmode, 1); | |
13215 | rtx frame_reg_rtx = sp_reg_rtx; | |
0e67400a | 13216 | enum machine_mode reg_mode = Pmode; |
327e5343 | 13217 | int reg_size = TARGET_32BIT ? 4 : 8; |
9ebbca7d GK |
13218 | int i; |
13219 | ||
c19de7aa AH |
13220 | info = rs6000_stack_info (); |
13221 | ||
13222 | if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0) | |
a3170dc6 AH |
13223 | { |
13224 | reg_mode = V2SImode; | |
13225 | reg_size = 8; | |
13226 | } | |
13227 | ||
9ebbca7d | 13228 | using_load_multiple = (TARGET_MULTIPLE && ! TARGET_POWERPC64 |
c19de7aa AH |
13229 | && (!TARGET_SPE_ABI |
13230 | || info->spe_64bit_regs_used == 0) | |
9ebbca7d GK |
13231 | && info->first_gp_reg_save < 31); |
13232 | restoring_FPRs_inline = (sibcall | |
83720594 | 13233 | || current_function_calls_eh_return |
9ebbca7d GK |
13234 | || info->first_fp_reg_save == 64 |
13235 | || FP_SAVE_INLINE (info->first_fp_reg_save)); | |
f676971a | 13236 | use_backchain_to_restore_sp = (frame_pointer_needed |
9ebbca7d GK |
13237 | || current_function_calls_alloca |
13238 | || info->total_size > 32767); | |
13239 | using_mfcr_multiple = (rs6000_cpu == PROCESSOR_PPC601 | |
13240 | || rs6000_cpu == PROCESSOR_PPC603 | |
13241 | || rs6000_cpu == PROCESSOR_PPC750 | |
13242 | || optimize_size); | |
13243 | ||
f57fe068 | 13244 | if (WORLD_SAVE_P (info)) |
d62294f5 FJ |
13245 | { |
13246 | int i, j; | |
13247 | char rname[30]; | |
13248 | const char *alloc_rname; | |
13249 | rtvec p; | |
13250 | ||
13251 | /* eh_rest_world_r10 will return to the location saved in the LR | |
c4ad648e AM |
13252 | stack slot (which is not likely to be our caller.) |
13253 | Input: R10 -- stack adjustment. Clobbers R0, R11, R12, R7, R8. | |
13254 | rest_world is similar, except any R10 parameter is ignored. | |
13255 | The exception-handling stuff that was here in 2.95 is no | |
13256 | longer necessary. */ | |
d62294f5 FJ |
13257 | |
13258 | p = rtvec_alloc (9 | |
13259 | + 1 | |
f676971a | 13260 | + 32 - info->first_gp_reg_save |
c4ad648e AM |
13261 | + LAST_ALTIVEC_REGNO + 1 - info->first_altivec_reg_save |
13262 | + 63 + 1 - info->first_fp_reg_save); | |
d62294f5 | 13263 | |
c4ad648e AM |
13264 | strcpy (rname, ((current_function_calls_eh_return) ? |
13265 | "*eh_rest_world_r10" : "*rest_world")); | |
d62294f5 FJ |
13266 | alloc_rname = ggc_strdup (rname); |
13267 | ||
13268 | j = 0; | |
13269 | RTVEC_ELT (p, j++) = gen_rtx_RETURN (VOIDmode); | |
13270 | RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode, | |
c4ad648e AM |
13271 | gen_rtx_REG (Pmode, |
13272 | LINK_REGISTER_REGNUM)); | |
d62294f5 | 13273 | RTVEC_ELT (p, j++) |
c4ad648e | 13274 | = gen_rtx_USE (VOIDmode, gen_rtx_SYMBOL_REF (Pmode, alloc_rname)); |
d62294f5 | 13275 | /* The instruction pattern requires a clobber here; |
c4ad648e | 13276 | it is shared with the restVEC helper. */ |
d62294f5 | 13277 | RTVEC_ELT (p, j++) |
c4ad648e | 13278 | = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 11)); |
d62294f5 FJ |
13279 | |
13280 | { | |
c4ad648e AM |
13281 | /* CR register traditionally saved as CR2. */ |
13282 | rtx reg = gen_rtx_REG (reg_mode, CR2_REGNO); | |
13283 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
13284 | GEN_INT (info->cr_save_offset)); | |
13285 | rtx mem = gen_rtx_MEM (reg_mode, addr); | |
13286 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
13287 | ||
13288 | RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem); | |
d62294f5 FJ |
13289 | } |
13290 | ||
13291 | for (i = 0; i < 32 - info->first_gp_reg_save; i++) | |
c4ad648e AM |
13292 | { |
13293 | rtx reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i); | |
13294 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
13295 | GEN_INT (info->gp_save_offset | |
13296 | + reg_size * i)); | |
13297 | rtx mem = gen_rtx_MEM (reg_mode, addr); | |
13298 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
13299 | ||
13300 | RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem); | |
13301 | } | |
d62294f5 | 13302 | for (i = 0; info->first_altivec_reg_save + i <= LAST_ALTIVEC_REGNO; i++) |
c4ad648e AM |
13303 | { |
13304 | rtx reg = gen_rtx_REG (V4SImode, info->first_altivec_reg_save + i); | |
13305 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
13306 | GEN_INT (info->altivec_save_offset | |
13307 | + 16 * i)); | |
13308 | rtx mem = gen_rtx_MEM (V4SImode, addr); | |
13309 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
13310 | ||
13311 | RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem); | |
13312 | } | |
d62294f5 | 13313 | for (i = 0; info->first_fp_reg_save + i <= 63; i++) |
c4ad648e AM |
13314 | { |
13315 | rtx reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i); | |
13316 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
13317 | GEN_INT (info->fp_save_offset | |
13318 | + 8 * i)); | |
13319 | rtx mem = gen_rtx_MEM (DFmode, addr); | |
13320 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
13321 | ||
13322 | RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem); | |
13323 | } | |
d62294f5 | 13324 | RTVEC_ELT (p, j++) |
c4ad648e | 13325 | = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 0)); |
d62294f5 | 13326 | RTVEC_ELT (p, j++) |
c4ad648e | 13327 | = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 12)); |
d62294f5 | 13328 | RTVEC_ELT (p, j++) |
c4ad648e | 13329 | = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 7)); |
d62294f5 | 13330 | RTVEC_ELT (p, j++) |
c4ad648e | 13331 | = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 8)); |
d62294f5 | 13332 | RTVEC_ELT (p, j++) |
c4ad648e | 13333 | = gen_rtx_USE (VOIDmode, gen_rtx_REG (SImode, 10)); |
d62294f5 FJ |
13334 | emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p)); |
13335 | ||
13336 | return; | |
13337 | } | |
13338 | ||
9ebbca7d GK |
13339 | /* If we have a frame pointer, a call to alloca, or a large stack |
13340 | frame, restore the old stack pointer using the backchain. Otherwise, | |
13341 | we know what size to update it with. */ | |
13342 | if (use_backchain_to_restore_sp) | |
bacbde18 | 13343 | { |
9ebbca7d GK |
13344 | /* Under V.4, don't reset the stack pointer until after we're done |
13345 | loading the saved registers. */ | |
f607bc57 | 13346 | if (DEFAULT_ABI == ABI_V4) |
9ebbca7d | 13347 | frame_reg_rtx = gen_rtx_REG (Pmode, 11); |
4697a36c | 13348 | |
9ebbca7d GK |
13349 | emit_move_insn (frame_reg_rtx, |
13350 | gen_rtx_MEM (Pmode, sp_reg_rtx)); | |
f676971a | 13351 | |
bacbde18 | 13352 | } |
9ebbca7d | 13353 | else if (info->push_p) |
85638c0d | 13354 | { |
fc4767bb JJ |
13355 | if (DEFAULT_ABI == ABI_V4 |
13356 | || current_function_calls_eh_return) | |
9ebbca7d GK |
13357 | sp_offset = info->total_size; |
13358 | else | |
13359 | { | |
13360 | emit_insn (TARGET_32BIT | |
13361 | ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx, | |
13362 | GEN_INT (info->total_size)) | |
13363 | : gen_adddi3 (sp_reg_rtx, sp_reg_rtx, | |
13364 | GEN_INT (info->total_size))); | |
13365 | } | |
85638c0d | 13366 | } |
f676971a | 13367 | |
9aa86737 AH |
13368 | /* Restore AltiVec registers if needed. */ |
13369 | if (TARGET_ALTIVEC_ABI && info->altivec_size != 0) | |
13370 | { | |
13371 | int i; | |
13372 | ||
13373 | for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i) | |
13374 | if (info->vrsave_mask & ALTIVEC_REG_BIT (i)) | |
13375 | { | |
13376 | rtx addr, areg, mem; | |
13377 | ||
13378 | areg = gen_rtx_REG (Pmode, 0); | |
13379 | emit_move_insn | |
13380 | (areg, GEN_INT (info->altivec_save_offset | |
13381 | + sp_offset | |
13382 | + 16 * (i - info->first_altivec_reg_save))); | |
13383 | ||
13384 | /* AltiVec addressing mode is [reg+reg]. */ | |
13385 | addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, areg); | |
13386 | mem = gen_rtx_MEM (V4SImode, addr); | |
13387 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
13388 | ||
13389 | emit_move_insn (gen_rtx_REG (V4SImode, i), mem); | |
13390 | } | |
13391 | } | |
13392 | ||
13393 | /* Restore VRSAVE if needed. */ | |
44688022 | 13394 | if (TARGET_ALTIVEC && TARGET_ALTIVEC_VRSAVE |
4d774ff8 | 13395 | && info->vrsave_mask != 0) |
9aa86737 AH |
13396 | { |
13397 | rtx addr, mem, reg; | |
13398 | ||
13399 | addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
13400 | GEN_INT (info->vrsave_save_offset + sp_offset)); | |
13401 | mem = gen_rtx_MEM (SImode, addr); | |
13402 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
13403 | reg = gen_rtx_REG (SImode, 12); | |
13404 | emit_move_insn (reg, mem); | |
13405 | ||
13406 | emit_insn (generate_set_vrsave (reg, info, 1)); | |
13407 | } | |
13408 | ||
9ebbca7d GK |
13409 | /* Get the old lr if we saved it. */ |
13410 | if (info->lr_save_p) | |
b6c9286a | 13411 | { |
a3170dc6 AH |
13412 | rtx mem = gen_frame_mem_offset (Pmode, frame_reg_rtx, |
13413 | info->lr_save_offset + sp_offset); | |
ba4828e0 RK |
13414 | |
13415 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
b6c9286a | 13416 | |
9ebbca7d | 13417 | emit_move_insn (gen_rtx_REG (Pmode, 0), mem); |
b6c9286a | 13418 | } |
f676971a | 13419 | |
9ebbca7d GK |
13420 | /* Get the old cr if we saved it. */ |
13421 | if (info->cr_save_p) | |
13422 | { | |
13423 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
13424 | GEN_INT (info->cr_save_offset + sp_offset)); | |
13425 | rtx mem = gen_rtx_MEM (SImode, addr); | |
ba4828e0 RK |
13426 | |
13427 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
b6c9286a | 13428 | |
9ebbca7d GK |
13429 | emit_move_insn (gen_rtx_REG (SImode, 12), mem); |
13430 | } | |
f676971a | 13431 | |
9ebbca7d | 13432 | /* Set LR here to try to overlap restores below. */ |
4697a36c | 13433 | if (info->lr_save_p) |
9ebbca7d GK |
13434 | emit_move_insn (gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM), |
13435 | gen_rtx_REG (Pmode, 0)); | |
f676971a | 13436 | |
83720594 RH |
13437 | /* Load exception handler data registers, if needed. */ |
13438 | if (current_function_calls_eh_return) | |
13439 | { | |
78e1b90d DE |
13440 | unsigned int i, regno; |
13441 | ||
fc4767bb JJ |
13442 | if (TARGET_AIX) |
13443 | { | |
13444 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
13445 | GEN_INT (sp_offset + 5 * reg_size)); | |
13446 | rtx mem = gen_rtx_MEM (reg_mode, addr); | |
13447 | ||
13448 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
13449 | ||
13450 | emit_move_insn (gen_rtx_REG (reg_mode, 2), mem); | |
13451 | } | |
13452 | ||
83720594 RH |
13453 | for (i = 0; ; ++i) |
13454 | { | |
a3170dc6 | 13455 | rtx mem; |
83720594 RH |
13456 | |
13457 | regno = EH_RETURN_DATA_REGNO (i); | |
13458 | if (regno == INVALID_REGNUM) | |
13459 | break; | |
13460 | ||
a3170dc6 AH |
13461 | mem = gen_frame_mem_offset (reg_mode, frame_reg_rtx, |
13462 | info->ehrd_offset + sp_offset | |
13463 | + reg_size * (int) i); | |
ba4828e0 | 13464 | set_mem_alias_set (mem, rs6000_sr_alias_set); |
83720594 RH |
13465 | |
13466 | emit_move_insn (gen_rtx_REG (reg_mode, regno), mem); | |
13467 | } | |
13468 | } | |
f676971a | 13469 | |
9ebbca7d GK |
13470 | /* Restore GPRs. This is done as a PARALLEL if we are using |
13471 | the load-multiple instructions. */ | |
13472 | if (using_load_multiple) | |
979721f8 | 13473 | { |
9ebbca7d GK |
13474 | rtvec p; |
13475 | p = rtvec_alloc (32 - info->first_gp_reg_save); | |
13476 | for (i = 0; i < 32 - info->first_gp_reg_save; i++) | |
979721f8 | 13477 | { |
f676971a EC |
13478 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, |
13479 | GEN_INT (info->gp_save_offset | |
13480 | + sp_offset | |
9ebbca7d GK |
13481 | + reg_size * i)); |
13482 | rtx mem = gen_rtx_MEM (reg_mode, addr); | |
ba4828e0 RK |
13483 | |
13484 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
9ebbca7d | 13485 | |
f676971a | 13486 | RTVEC_ELT (p, i) = |
9ebbca7d GK |
13487 | gen_rtx_SET (VOIDmode, |
13488 | gen_rtx_REG (reg_mode, info->first_gp_reg_save + i), | |
13489 | mem); | |
979721f8 | 13490 | } |
9ebbca7d | 13491 | emit_insn (gen_rtx_PARALLEL (VOIDmode, p)); |
979721f8 | 13492 | } |
9ebbca7d GK |
13493 | else |
13494 | for (i = 0; i < 32 - info->first_gp_reg_save; i++) | |
f676971a | 13495 | if ((regs_ever_live[info->first_gp_reg_save+i] |
b4db40bf JJ |
13496 | && (! call_used_regs[info->first_gp_reg_save+i] |
13497 | || (i+info->first_gp_reg_save == RS6000_PIC_OFFSET_TABLE_REGNUM | |
13498 | && TARGET_TOC && TARGET_MINIMAL_TOC))) | |
1db02437 | 13499 | || (i+info->first_gp_reg_save == RS6000_PIC_OFFSET_TABLE_REGNUM |
14f00213 | 13500 | && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0) |
f607bc57 | 13501 | || (DEFAULT_ABI == ABI_DARWIN && flag_pic)))) |
9ebbca7d | 13502 | { |
f676971a EC |
13503 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, |
13504 | GEN_INT (info->gp_save_offset | |
13505 | + sp_offset | |
9ebbca7d GK |
13506 | + reg_size * i)); |
13507 | rtx mem = gen_rtx_MEM (reg_mode, addr); | |
ba4828e0 | 13508 | |
a3170dc6 | 13509 | /* Restore 64-bit quantities for SPE. */ |
c19de7aa | 13510 | if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0) |
a3170dc6 AH |
13511 | { |
13512 | int offset = info->spe_gp_save_offset + sp_offset + 8 * i; | |
13513 | rtx b; | |
13514 | ||
13515 | if (!SPE_CONST_OFFSET_OK (offset)) | |
13516 | { | |
13517 | b = gen_rtx_REG (Pmode, FIXED_SCRATCH); | |
13518 | emit_move_insn (b, GEN_INT (offset)); | |
13519 | } | |
13520 | else | |
13521 | b = GEN_INT (offset); | |
13522 | ||
13523 | addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, b); | |
13524 | mem = gen_rtx_MEM (V2SImode, addr); | |
13525 | } | |
13526 | ||
ba4828e0 | 13527 | set_mem_alias_set (mem, rs6000_sr_alias_set); |
9ebbca7d | 13528 | |
f676971a | 13529 | emit_move_insn (gen_rtx_REG (reg_mode, |
a3170dc6 | 13530 | info->first_gp_reg_save + i), mem); |
9ebbca7d | 13531 | } |
9878760c | 13532 | |
9ebbca7d GK |
13533 | /* Restore fpr's if we need to do it without calling a function. */ |
13534 | if (restoring_FPRs_inline) | |
13535 | for (i = 0; i < 64 - info->first_fp_reg_save; i++) | |
f676971a | 13536 | if ((regs_ever_live[info->first_fp_reg_save+i] |
9ebbca7d GK |
13537 | && ! call_used_regs[info->first_fp_reg_save+i])) |
13538 | { | |
13539 | rtx addr, mem; | |
13540 | addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
f676971a EC |
13541 | GEN_INT (info->fp_save_offset |
13542 | + sp_offset | |
a4f6c312 | 13543 | + 8 * i)); |
9ebbca7d | 13544 | mem = gen_rtx_MEM (DFmode, addr); |
ba4828e0 | 13545 | set_mem_alias_set (mem, rs6000_sr_alias_set); |
9ebbca7d | 13546 | |
f676971a | 13547 | emit_move_insn (gen_rtx_REG (DFmode, |
9ebbca7d GK |
13548 | info->first_fp_reg_save + i), |
13549 | mem); | |
13550 | } | |
8d30c4ee | 13551 | |
9ebbca7d GK |
13552 | /* If we saved cr, restore it here. Just those that were used. */ |
13553 | if (info->cr_save_p) | |
979721f8 | 13554 | { |
9ebbca7d | 13555 | rtx r12_rtx = gen_rtx_REG (SImode, 12); |
e35b9579 | 13556 | int count = 0; |
f676971a | 13557 | |
9ebbca7d | 13558 | if (using_mfcr_multiple) |
979721f8 | 13559 | { |
9ebbca7d GK |
13560 | for (i = 0; i < 8; i++) |
13561 | if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i]) | |
e35b9579 | 13562 | count++; |
9ebbca7d | 13563 | if (count == 0) |
e35b9579 GK |
13564 | abort (); |
13565 | } | |
13566 | ||
13567 | if (using_mfcr_multiple && count > 1) | |
13568 | { | |
13569 | rtvec p; | |
13570 | int ndx; | |
f676971a | 13571 | |
e35b9579 | 13572 | p = rtvec_alloc (count); |
9ebbca7d | 13573 | |
e35b9579 | 13574 | ndx = 0; |
9ebbca7d GK |
13575 | for (i = 0; i < 8; i++) |
13576 | if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i]) | |
13577 | { | |
13578 | rtvec r = rtvec_alloc (2); | |
13579 | RTVEC_ELT (r, 0) = r12_rtx; | |
13580 | RTVEC_ELT (r, 1) = GEN_INT (1 << (7-i)); | |
e35b9579 | 13581 | RTVEC_ELT (p, ndx) = |
f676971a | 13582 | gen_rtx_SET (VOIDmode, gen_rtx_REG (CCmode, CR0_REGNO+i), |
615158e2 | 13583 | gen_rtx_UNSPEC (CCmode, r, UNSPEC_MOVESI_TO_CR)); |
e35b9579 | 13584 | ndx++; |
9ebbca7d GK |
13585 | } |
13586 | emit_insn (gen_rtx_PARALLEL (VOIDmode, p)); | |
e35b9579 GK |
13587 | if (ndx != count) |
13588 | abort (); | |
979721f8 MM |
13589 | } |
13590 | else | |
9ebbca7d GK |
13591 | for (i = 0; i < 8; i++) |
13592 | if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i]) | |
979721f8 | 13593 | { |
f676971a | 13594 | emit_insn (gen_movsi_to_cr_one (gen_rtx_REG (CCmode, |
9ebbca7d GK |
13595 | CR0_REGNO+i), |
13596 | r12_rtx)); | |
979721f8 | 13597 | } |
979721f8 MM |
13598 | } |
13599 | ||
9ebbca7d GK |
13600 | /* If this is V.4, unwind the stack pointer after all of the loads |
13601 | have been done. We need to emit a block here so that sched | |
13602 | doesn't decide to move the sp change before the register restores | |
13603 | (which may not have any obvious dependency on the stack). This | |
13604 | doesn't hurt performance, because there is no scheduling that can | |
13605 | be done after this point. */ | |
fc4767bb JJ |
13606 | if (DEFAULT_ABI == ABI_V4 |
13607 | || current_function_calls_eh_return) | |
b6c9286a | 13608 | { |
9ebbca7d | 13609 | if (frame_reg_rtx != sp_reg_rtx) |
c4ad648e | 13610 | rs6000_emit_stack_tie (); |
b6c9286a | 13611 | |
9ebbca7d | 13612 | if (use_backchain_to_restore_sp) |
b6c9286a | 13613 | { |
9ebbca7d | 13614 | emit_move_insn (sp_reg_rtx, frame_reg_rtx); |
b6c9286a | 13615 | } |
9ebbca7d | 13616 | else if (sp_offset != 0) |
13f1623b | 13617 | { |
5b71a4e7 | 13618 | emit_insn (TARGET_32BIT |
9ebbca7d GK |
13619 | ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx, |
13620 | GEN_INT (sp_offset)) | |
13621 | : gen_adddi3 (sp_reg_rtx, sp_reg_rtx, | |
13622 | GEN_INT (sp_offset))); | |
13f1623b | 13623 | } |
9ebbca7d | 13624 | } |
b6c9286a | 13625 | |
83720594 RH |
13626 | if (current_function_calls_eh_return) |
13627 | { | |
13628 | rtx sa = EH_RETURN_STACKADJ_RTX; | |
5b71a4e7 | 13629 | emit_insn (TARGET_32BIT |
83720594 RH |
13630 | ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx, sa) |
13631 | : gen_adddi3 (sp_reg_rtx, sp_reg_rtx, sa)); | |
13632 | } | |
13633 | ||
9ebbca7d GK |
13634 | if (!sibcall) |
13635 | { | |
13636 | rtvec p; | |
13637 | if (! restoring_FPRs_inline) | |
13638 | p = rtvec_alloc (3 + 64 - info->first_fp_reg_save); | |
13639 | else | |
13640 | p = rtvec_alloc (2); | |
b6c9286a | 13641 | |
e35b9579 | 13642 | RTVEC_ELT (p, 0) = gen_rtx_RETURN (VOIDmode); |
f676971a EC |
13643 | RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode, |
13644 | gen_rtx_REG (Pmode, | |
9ebbca7d | 13645 | LINK_REGISTER_REGNUM)); |
9ebbca7d GK |
13646 | |
13647 | /* If we have to restore more than two FP registers, branch to the | |
13648 | restore function. It will return to our caller. */ | |
13649 | if (! restoring_FPRs_inline) | |
13650 | { | |
13651 | int i; | |
13652 | char rname[30]; | |
520a57c8 | 13653 | const char *alloc_rname; |
979721f8 | 13654 | |
f676971a | 13655 | sprintf (rname, "%s%d%s", RESTORE_FP_PREFIX, |
9ebbca7d | 13656 | info->first_fp_reg_save - 32, RESTORE_FP_SUFFIX); |
a8a05998 | 13657 | alloc_rname = ggc_strdup (rname); |
9ebbca7d GK |
13658 | RTVEC_ELT (p, 2) = gen_rtx_USE (VOIDmode, |
13659 | gen_rtx_SYMBOL_REF (Pmode, | |
13660 | alloc_rname)); | |
b6c9286a | 13661 | |
9ebbca7d GK |
13662 | for (i = 0; i < 64 - info->first_fp_reg_save; i++) |
13663 | { | |
13664 | rtx addr, mem; | |
13665 | addr = gen_rtx_PLUS (Pmode, sp_reg_rtx, | |
13666 | GEN_INT (info->fp_save_offset + 8*i)); | |
13667 | mem = gen_rtx_MEM (DFmode, addr); | |
ba4828e0 | 13668 | set_mem_alias_set (mem, rs6000_sr_alias_set); |
9ebbca7d | 13669 | |
f676971a | 13670 | RTVEC_ELT (p, i+3) = |
9ebbca7d GK |
13671 | gen_rtx_SET (VOIDmode, |
13672 | gen_rtx_REG (DFmode, info->first_fp_reg_save + i), | |
13673 | mem); | |
b6c9286a MM |
13674 | } |
13675 | } | |
f676971a | 13676 | |
9ebbca7d | 13677 | emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p)); |
3daf36a4 | 13678 | } |
9878760c RK |
13679 | } |
13680 | ||
13681 | /* Write function epilogue. */ | |
13682 | ||
08c148a8 | 13683 | static void |
f676971a | 13684 | rs6000_output_function_epilogue (FILE *file, |
a2369ed3 | 13685 | HOST_WIDE_INT size ATTRIBUTE_UNUSED) |
9878760c | 13686 | { |
4697a36c | 13687 | rs6000_stack_t *info = rs6000_stack_info (); |
9878760c | 13688 | |
9ebbca7d | 13689 | if (! HAVE_epilogue) |
9878760c | 13690 | { |
9ebbca7d GK |
13691 | rtx insn = get_last_insn (); |
13692 | /* If the last insn was a BARRIER, we don't have to write anything except | |
13693 | the trace table. */ | |
13694 | if (GET_CODE (insn) == NOTE) | |
13695 | insn = prev_nonnote_insn (insn); | |
13696 | if (insn == 0 || GET_CODE (insn) != BARRIER) | |
4697a36c | 13697 | { |
9ebbca7d GK |
13698 | /* This is slightly ugly, but at least we don't have two |
13699 | copies of the epilogue-emitting code. */ | |
13700 | start_sequence (); | |
13701 | ||
13702 | /* A NOTE_INSN_DELETED is supposed to be at the start | |
13703 | and end of the "toplevel" insn chain. */ | |
2e040219 | 13704 | emit_note (NOTE_INSN_DELETED); |
9ebbca7d | 13705 | rs6000_emit_epilogue (FALSE); |
2e040219 | 13706 | emit_note (NOTE_INSN_DELETED); |
9ebbca7d | 13707 | |
a3c9585f | 13708 | /* Expand INSN_ADDRESSES so final() doesn't crash. */ |
178c3eff DJ |
13709 | { |
13710 | rtx insn; | |
13711 | unsigned addr = 0; | |
13712 | for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn)) | |
13713 | { | |
13714 | INSN_ADDRESSES_NEW (insn, addr); | |
13715 | addr += 4; | |
13716 | } | |
13717 | } | |
13718 | ||
9ebbca7d | 13719 | if (TARGET_DEBUG_STACK) |
a4f6c312 SS |
13720 | debug_rtx_list (get_insns (), 100); |
13721 | final (get_insns (), file, FALSE, FALSE); | |
9ebbca7d | 13722 | end_sequence (); |
4697a36c | 13723 | } |
9878760c | 13724 | } |
b4ac57ab | 13725 | |
efdba735 SH |
13726 | #if TARGET_MACHO |
13727 | macho_branch_islands (); | |
0e5da0be GK |
13728 | /* Mach-O doesn't support labels at the end of objects, so if |
13729 | it looks like we might want one, insert a NOP. */ | |
13730 | { | |
13731 | rtx insn = get_last_insn (); | |
13732 | while (insn | |
13733 | && NOTE_P (insn) | |
13734 | && NOTE_LINE_NUMBER (insn) != NOTE_INSN_DELETED_LABEL) | |
13735 | insn = PREV_INSN (insn); | |
f676971a EC |
13736 | if (insn |
13737 | && (LABEL_P (insn) | |
0e5da0be GK |
13738 | || (NOTE_P (insn) |
13739 | && NOTE_LINE_NUMBER (insn) == NOTE_INSN_DELETED_LABEL))) | |
13740 | fputs ("\tnop\n", file); | |
13741 | } | |
13742 | #endif | |
13743 | ||
9b30bae2 | 13744 | /* Output a traceback table here. See /usr/include/sys/debug.h for info |
314fc5a9 ILT |
13745 | on its format. |
13746 | ||
13747 | We don't output a traceback table if -finhibit-size-directive was | |
13748 | used. The documentation for -finhibit-size-directive reads | |
13749 | ``don't output a @code{.size} assembler directive, or anything | |
13750 | else that would cause trouble if the function is split in the | |
13751 | middle, and the two halves are placed at locations far apart in | |
13752 | memory.'' The traceback table has this property, since it | |
13753 | includes the offset from the start of the function to the | |
4d30c363 MM |
13754 | traceback table itself. |
13755 | ||
13756 | System V.4 Powerpc's (and the embedded ABI derived from it) use a | |
b6c9286a | 13757 | different traceback table. */ |
57ac7be9 AM |
13758 | if (DEFAULT_ABI == ABI_AIX && ! flag_inhibit_size_directive |
13759 | && rs6000_traceback != traceback_none) | |
9b30bae2 | 13760 | { |
69c75916 | 13761 | const char *fname = NULL; |
3ac88239 | 13762 | const char *language_string = lang_hooks.name; |
6041bf2f | 13763 | int fixed_parms = 0, float_parms = 0, parm_info = 0; |
314fc5a9 | 13764 | int i; |
57ac7be9 AM |
13765 | int optional_tbtab; |
13766 | ||
13767 | if (rs6000_traceback == traceback_full) | |
13768 | optional_tbtab = 1; | |
13769 | else if (rs6000_traceback == traceback_part) | |
13770 | optional_tbtab = 0; | |
13771 | else | |
13772 | optional_tbtab = !optimize_size && !TARGET_ELF; | |
314fc5a9 | 13773 | |
69c75916 AM |
13774 | if (optional_tbtab) |
13775 | { | |
13776 | fname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0); | |
13777 | while (*fname == '.') /* V.4 encodes . in the name */ | |
13778 | fname++; | |
13779 | ||
13780 | /* Need label immediately before tbtab, so we can compute | |
13781 | its offset from the function start. */ | |
13782 | ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT"); | |
13783 | ASM_OUTPUT_LABEL (file, fname); | |
13784 | } | |
314fc5a9 ILT |
13785 | |
13786 | /* The .tbtab pseudo-op can only be used for the first eight | |
13787 | expressions, since it can't handle the possibly variable | |
13788 | length fields that follow. However, if you omit the optional | |
13789 | fields, the assembler outputs zeros for all optional fields | |
13790 | anyways, giving each variable length field is minimum length | |
13791 | (as defined in sys/debug.h). Thus we can not use the .tbtab | |
13792 | pseudo-op at all. */ | |
13793 | ||
13794 | /* An all-zero word flags the start of the tbtab, for debuggers | |
13795 | that have to find it by searching forward from the entry | |
13796 | point or from the current pc. */ | |
19d2d16f | 13797 | fputs ("\t.long 0\n", file); |
314fc5a9 ILT |
13798 | |
13799 | /* Tbtab format type. Use format type 0. */ | |
19d2d16f | 13800 | fputs ("\t.byte 0,", file); |
314fc5a9 | 13801 | |
5fc921c1 DE |
13802 | /* Language type. Unfortunately, there does not seem to be any |
13803 | official way to discover the language being compiled, so we | |
13804 | use language_string. | |
13805 | C is 0. Fortran is 1. Pascal is 2. Ada is 3. C++ is 9. | |
13806 | Java is 13. Objective-C is 14. */ | |
13807 | if (! strcmp (language_string, "GNU C")) | |
314fc5a9 | 13808 | i = 0; |
6de9cd9a DN |
13809 | else if (! strcmp (language_string, "GNU F77") |
13810 | || ! strcmp (language_string, "GNU F95")) | |
314fc5a9 | 13811 | i = 1; |
8b83775b | 13812 | else if (! strcmp (language_string, "GNU Pascal")) |
314fc5a9 | 13813 | i = 2; |
5fc921c1 DE |
13814 | else if (! strcmp (language_string, "GNU Ada")) |
13815 | i = 3; | |
314fc5a9 ILT |
13816 | else if (! strcmp (language_string, "GNU C++")) |
13817 | i = 9; | |
9517ead8 AG |
13818 | else if (! strcmp (language_string, "GNU Java")) |
13819 | i = 13; | |
5fc921c1 DE |
13820 | else if (! strcmp (language_string, "GNU Objective-C")) |
13821 | i = 14; | |
314fc5a9 ILT |
13822 | else |
13823 | abort (); | |
13824 | fprintf (file, "%d,", i); | |
13825 | ||
13826 | /* 8 single bit fields: global linkage (not set for C extern linkage, | |
13827 | apparently a PL/I convention?), out-of-line epilogue/prologue, offset | |
13828 | from start of procedure stored in tbtab, internal function, function | |
13829 | has controlled storage, function has no toc, function uses fp, | |
13830 | function logs/aborts fp operations. */ | |
13831 | /* Assume that fp operations are used if any fp reg must be saved. */ | |
6041bf2f DE |
13832 | fprintf (file, "%d,", |
13833 | (optional_tbtab << 5) | ((info->first_fp_reg_save != 64) << 1)); | |
314fc5a9 ILT |
13834 | |
13835 | /* 6 bitfields: function is interrupt handler, name present in | |
13836 | proc table, function calls alloca, on condition directives | |
13837 | (controls stack walks, 3 bits), saves condition reg, saves | |
13838 | link reg. */ | |
13839 | /* The `function calls alloca' bit seems to be set whenever reg 31 is | |
13840 | set up as a frame pointer, even when there is no alloca call. */ | |
13841 | fprintf (file, "%d,", | |
6041bf2f DE |
13842 | ((optional_tbtab << 6) |
13843 | | ((optional_tbtab & frame_pointer_needed) << 5) | |
13844 | | (info->cr_save_p << 1) | |
13845 | | (info->lr_save_p))); | |
314fc5a9 | 13846 | |
6041bf2f | 13847 | /* 3 bitfields: saves backchain, fixup code, number of fpr saved |
314fc5a9 ILT |
13848 | (6 bits). */ |
13849 | fprintf (file, "%d,", | |
4697a36c | 13850 | (info->push_p << 7) | (64 - info->first_fp_reg_save)); |
314fc5a9 ILT |
13851 | |
13852 | /* 2 bitfields: spare bits (2 bits), number of gpr saved (6 bits). */ | |
13853 | fprintf (file, "%d,", (32 - first_reg_to_save ())); | |
13854 | ||
6041bf2f DE |
13855 | if (optional_tbtab) |
13856 | { | |
13857 | /* Compute the parameter info from the function decl argument | |
13858 | list. */ | |
13859 | tree decl; | |
13860 | int next_parm_info_bit = 31; | |
314fc5a9 | 13861 | |
6041bf2f DE |
13862 | for (decl = DECL_ARGUMENTS (current_function_decl); |
13863 | decl; decl = TREE_CHAIN (decl)) | |
13864 | { | |
13865 | rtx parameter = DECL_INCOMING_RTL (decl); | |
13866 | enum machine_mode mode = GET_MODE (parameter); | |
314fc5a9 | 13867 | |
6041bf2f DE |
13868 | if (GET_CODE (parameter) == REG) |
13869 | { | |
13870 | if (GET_MODE_CLASS (mode) == MODE_FLOAT) | |
13871 | { | |
13872 | int bits; | |
13873 | ||
13874 | float_parms++; | |
13875 | ||
13876 | if (mode == SFmode) | |
13877 | bits = 0x2; | |
fcce224d | 13878 | else if (mode == DFmode || mode == TFmode) |
6041bf2f DE |
13879 | bits = 0x3; |
13880 | else | |
13881 | abort (); | |
13882 | ||
13883 | /* If only one bit will fit, don't or in this entry. */ | |
13884 | if (next_parm_info_bit > 0) | |
13885 | parm_info |= (bits << (next_parm_info_bit - 1)); | |
13886 | next_parm_info_bit -= 2; | |
13887 | } | |
13888 | else | |
13889 | { | |
13890 | fixed_parms += ((GET_MODE_SIZE (mode) | |
13891 | + (UNITS_PER_WORD - 1)) | |
13892 | / UNITS_PER_WORD); | |
13893 | next_parm_info_bit -= 1; | |
13894 | } | |
13895 | } | |
13896 | } | |
13897 | } | |
314fc5a9 ILT |
13898 | |
13899 | /* Number of fixed point parameters. */ | |
13900 | /* This is actually the number of words of fixed point parameters; thus | |
13901 | an 8 byte struct counts as 2; and thus the maximum value is 8. */ | |
13902 | fprintf (file, "%d,", fixed_parms); | |
13903 | ||
13904 | /* 2 bitfields: number of floating point parameters (7 bits), parameters | |
13905 | all on stack. */ | |
13906 | /* This is actually the number of fp registers that hold parameters; | |
13907 | and thus the maximum value is 13. */ | |
13908 | /* Set parameters on stack bit if parameters are not in their original | |
13909 | registers, regardless of whether they are on the stack? Xlc | |
13910 | seems to set the bit when not optimizing. */ | |
13911 | fprintf (file, "%d\n", ((float_parms << 1) | (! optimize))); | |
13912 | ||
6041bf2f DE |
13913 | if (! optional_tbtab) |
13914 | return; | |
13915 | ||
314fc5a9 ILT |
13916 | /* Optional fields follow. Some are variable length. */ |
13917 | ||
13918 | /* Parameter types, left adjusted bit fields: 0 fixed, 10 single float, | |
13919 | 11 double float. */ | |
13920 | /* There is an entry for each parameter in a register, in the order that | |
13921 | they occur in the parameter list. Any intervening arguments on the | |
13922 | stack are ignored. If the list overflows a long (max possible length | |
13923 | 34 bits) then completely leave off all elements that don't fit. */ | |
13924 | /* Only emit this long if there was at least one parameter. */ | |
13925 | if (fixed_parms || float_parms) | |
13926 | fprintf (file, "\t.long %d\n", parm_info); | |
13927 | ||
13928 | /* Offset from start of code to tb table. */ | |
19d2d16f | 13929 | fputs ("\t.long ", file); |
314fc5a9 | 13930 | ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT"); |
85b776df AM |
13931 | if (TARGET_AIX) |
13932 | RS6000_OUTPUT_BASENAME (file, fname); | |
13933 | else | |
13934 | assemble_name (file, fname); | |
13935 | putc ('-', file); | |
13936 | rs6000_output_function_entry (file, fname); | |
19d2d16f | 13937 | putc ('\n', file); |
314fc5a9 ILT |
13938 | |
13939 | /* Interrupt handler mask. */ | |
13940 | /* Omit this long, since we never set the interrupt handler bit | |
13941 | above. */ | |
13942 | ||
13943 | /* Number of CTL (controlled storage) anchors. */ | |
13944 | /* Omit this long, since the has_ctl bit is never set above. */ | |
13945 | ||
13946 | /* Displacement into stack of each CTL anchor. */ | |
13947 | /* Omit this list of longs, because there are no CTL anchors. */ | |
13948 | ||
13949 | /* Length of function name. */ | |
69c75916 AM |
13950 | if (*fname == '*') |
13951 | ++fname; | |
296b8152 | 13952 | fprintf (file, "\t.short %d\n", (int) strlen (fname)); |
314fc5a9 ILT |
13953 | |
13954 | /* Function name. */ | |
13955 | assemble_string (fname, strlen (fname)); | |
13956 | ||
13957 | /* Register for alloca automatic storage; this is always reg 31. | |
13958 | Only emit this if the alloca bit was set above. */ | |
13959 | if (frame_pointer_needed) | |
19d2d16f | 13960 | fputs ("\t.byte 31\n", file); |
b1765bde DE |
13961 | |
13962 | fputs ("\t.align 2\n", file); | |
9b30bae2 | 13963 | } |
9878760c | 13964 | } |
17167fd8 | 13965 | \f |
a4f6c312 SS |
13966 | /* A C compound statement that outputs the assembler code for a thunk |
13967 | function, used to implement C++ virtual function calls with | |
13968 | multiple inheritance. The thunk acts as a wrapper around a virtual | |
13969 | function, adjusting the implicit object parameter before handing | |
13970 | control off to the real function. | |
13971 | ||
13972 | First, emit code to add the integer DELTA to the location that | |
13973 | contains the incoming first argument. Assume that this argument | |
13974 | contains a pointer, and is the one used to pass the `this' pointer | |
13975 | in C++. This is the incoming argument *before* the function | |
13976 | prologue, e.g. `%o0' on a sparc. The addition must preserve the | |
13977 | values of all other incoming arguments. | |
17167fd8 MM |
13978 | |
13979 | After the addition, emit code to jump to FUNCTION, which is a | |
a4f6c312 SS |
13980 | `FUNCTION_DECL'. This is a direct pure jump, not a call, and does |
13981 | not touch the return address. Hence returning from FUNCTION will | |
13982 | return to whoever called the current `thunk'. | |
17167fd8 | 13983 | |
a4f6c312 SS |
13984 | The effect must be as if FUNCTION had been called directly with the |
13985 | adjusted first argument. This macro is responsible for emitting | |
13986 | all of the code for a thunk function; output_function_prologue() | |
13987 | and output_function_epilogue() are not invoked. | |
17167fd8 | 13988 | |
a4f6c312 SS |
13989 | The THUNK_FNDECL is redundant. (DELTA and FUNCTION have already |
13990 | been extracted from it.) It might possibly be useful on some | |
13991 | targets, but probably not. | |
17167fd8 | 13992 | |
a4f6c312 SS |
13993 | If you do not define this macro, the target-independent code in the |
13994 | C++ frontend will generate a less efficient heavyweight thunk that | |
13995 | calls FUNCTION instead of jumping to it. The generic approach does | |
13996 | not support varargs. */ | |
17167fd8 | 13997 | |
3961e8fe | 13998 | static void |
f676971a EC |
13999 | rs6000_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED, |
14000 | HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset, | |
a2369ed3 | 14001 | tree function) |
17167fd8 | 14002 | { |
5b71a4e7 | 14003 | rtx this, insn, funexp; |
17167fd8 | 14004 | |
5b71a4e7 | 14005 | reload_completed = 1; |
fe3ad572 | 14006 | epilogue_completed = 1; |
5b71a4e7 | 14007 | no_new_pseudos = 1; |
6429e3be | 14008 | reset_block_changes (); |
56a7189a | 14009 | |
5b71a4e7 | 14010 | /* Mark the end of the (empty) prologue. */ |
2e040219 | 14011 | emit_note (NOTE_INSN_PROLOGUE_END); |
17167fd8 | 14012 | |
5b71a4e7 DE |
14013 | /* Find the "this" pointer. If the function returns a structure, |
14014 | the structure return pointer is in r3. */ | |
61f71b34 | 14015 | if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function)) |
5b71a4e7 | 14016 | this = gen_rtx_REG (Pmode, 4); |
56a7189a | 14017 | else |
5b71a4e7 | 14018 | this = gen_rtx_REG (Pmode, 3); |
17167fd8 | 14019 | |
5b71a4e7 DE |
14020 | /* Apply the constant offset, if required. */ |
14021 | if (delta) | |
14022 | { | |
14023 | rtx delta_rtx = GEN_INT (delta); | |
14024 | emit_insn (TARGET_32BIT | |
14025 | ? gen_addsi3 (this, this, delta_rtx) | |
14026 | : gen_adddi3 (this, this, delta_rtx)); | |
17167fd8 MM |
14027 | } |
14028 | ||
5b71a4e7 DE |
14029 | /* Apply the offset from the vtable, if required. */ |
14030 | if (vcall_offset) | |
17167fd8 | 14031 | { |
5b71a4e7 DE |
14032 | rtx vcall_offset_rtx = GEN_INT (vcall_offset); |
14033 | rtx tmp = gen_rtx_REG (Pmode, 12); | |
17167fd8 | 14034 | |
5b71a4e7 | 14035 | emit_move_insn (tmp, gen_rtx_MEM (Pmode, this)); |
eeff9307 JJ |
14036 | if (((unsigned HOST_WIDE_INT) vcall_offset) + 0x8000 >= 0x10000) |
14037 | { | |
14038 | emit_insn (TARGET_32BIT | |
14039 | ? gen_addsi3 (tmp, tmp, vcall_offset_rtx) | |
14040 | : gen_adddi3 (tmp, tmp, vcall_offset_rtx)); | |
14041 | emit_move_insn (tmp, gen_rtx_MEM (Pmode, tmp)); | |
14042 | } | |
14043 | else | |
14044 | { | |
14045 | rtx loc = gen_rtx_PLUS (Pmode, tmp, vcall_offset_rtx); | |
14046 | ||
14047 | emit_move_insn (tmp, gen_rtx_MEM (Pmode, loc)); | |
14048 | } | |
5b71a4e7 DE |
14049 | emit_insn (TARGET_32BIT |
14050 | ? gen_addsi3 (this, this, tmp) | |
14051 | : gen_adddi3 (this, this, tmp)); | |
17167fd8 MM |
14052 | } |
14053 | ||
5b71a4e7 DE |
14054 | /* Generate a tail call to the target function. */ |
14055 | if (!TREE_USED (function)) | |
14056 | { | |
14057 | assemble_external (function); | |
14058 | TREE_USED (function) = 1; | |
14059 | } | |
14060 | funexp = XEXP (DECL_RTL (function), 0); | |
5b71a4e7 | 14061 | funexp = gen_rtx_MEM (FUNCTION_MODE, funexp); |
ee890fe2 SS |
14062 | |
14063 | #if TARGET_MACHO | |
ab82a49f | 14064 | if (MACHOPIC_INDIRECT) |
5b71a4e7 | 14065 | funexp = machopic_indirect_call_target (funexp); |
ee890fe2 | 14066 | #endif |
5b71a4e7 DE |
14067 | |
14068 | /* gen_sibcall expects reload to convert scratch pseudo to LR so we must | |
14069 | generate sibcall RTL explicitly to avoid constraint abort. */ | |
14070 | insn = emit_call_insn ( | |
14071 | gen_rtx_PARALLEL (VOIDmode, | |
14072 | gen_rtvec (4, | |
14073 | gen_rtx_CALL (VOIDmode, | |
14074 | funexp, const0_rtx), | |
14075 | gen_rtx_USE (VOIDmode, const0_rtx), | |
14076 | gen_rtx_USE (VOIDmode, | |
14077 | gen_rtx_REG (SImode, | |
14078 | LINK_REGISTER_REGNUM)), | |
14079 | gen_rtx_RETURN (VOIDmode)))); | |
14080 | SIBLING_CALL_P (insn) = 1; | |
14081 | emit_barrier (); | |
14082 | ||
14083 | /* Run just enough of rest_of_compilation to get the insns emitted. | |
14084 | There's not really enough bulk here to make other passes such as | |
14085 | instruction scheduling worth while. Note that use_thunk calls | |
14086 | assemble_start_function and assemble_end_function. */ | |
14087 | insn = get_insns (); | |
a2855205 | 14088 | insn_locators_initialize (); |
5b71a4e7 DE |
14089 | shorten_branches (insn); |
14090 | final_start_function (insn, file, 1); | |
14091 | final (insn, file, 1, 0); | |
14092 | final_end_function (); | |
14093 | ||
14094 | reload_completed = 0; | |
fe3ad572 | 14095 | epilogue_completed = 0; |
5b71a4e7 | 14096 | no_new_pseudos = 0; |
9ebbca7d | 14097 | } |
9ebbca7d GK |
14098 | \f |
14099 | /* A quick summary of the various types of 'constant-pool tables' | |
14100 | under PowerPC: | |
14101 | ||
f676971a | 14102 | Target Flags Name One table per |
9ebbca7d GK |
14103 | AIX (none) AIX TOC object file |
14104 | AIX -mfull-toc AIX TOC object file | |
14105 | AIX -mminimal-toc AIX minimal TOC translation unit | |
14106 | SVR4/EABI (none) SVR4 SDATA object file | |
14107 | SVR4/EABI -fpic SVR4 pic object file | |
14108 | SVR4/EABI -fPIC SVR4 PIC translation unit | |
14109 | SVR4/EABI -mrelocatable EABI TOC function | |
14110 | SVR4/EABI -maix AIX TOC object file | |
f676971a | 14111 | SVR4/EABI -maix -mminimal-toc |
9ebbca7d GK |
14112 | AIX minimal TOC translation unit |
14113 | ||
14114 | Name Reg. Set by entries contains: | |
14115 | made by addrs? fp? sum? | |
14116 | ||
14117 | AIX TOC 2 crt0 as Y option option | |
14118 | AIX minimal TOC 30 prolog gcc Y Y option | |
14119 | SVR4 SDATA 13 crt0 gcc N Y N | |
14120 | SVR4 pic 30 prolog ld Y not yet N | |
14121 | SVR4 PIC 30 prolog gcc Y option option | |
14122 | EABI TOC 30 prolog gcc Y option option | |
14123 | ||
14124 | */ | |
14125 | ||
9ebbca7d GK |
14126 | /* Hash functions for the hash table. */ |
14127 | ||
14128 | static unsigned | |
a2369ed3 | 14129 | rs6000_hash_constant (rtx k) |
9ebbca7d | 14130 | { |
46b33600 RH |
14131 | enum rtx_code code = GET_CODE (k); |
14132 | enum machine_mode mode = GET_MODE (k); | |
14133 | unsigned result = (code << 3) ^ mode; | |
14134 | const char *format; | |
14135 | int flen, fidx; | |
f676971a | 14136 | |
46b33600 RH |
14137 | format = GET_RTX_FORMAT (code); |
14138 | flen = strlen (format); | |
14139 | fidx = 0; | |
9ebbca7d | 14140 | |
46b33600 RH |
14141 | switch (code) |
14142 | { | |
14143 | case LABEL_REF: | |
14144 | return result * 1231 + (unsigned) INSN_UID (XEXP (k, 0)); | |
14145 | ||
14146 | case CONST_DOUBLE: | |
14147 | if (mode != VOIDmode) | |
14148 | return real_hash (CONST_DOUBLE_REAL_VALUE (k)) * result; | |
14149 | flen = 2; | |
14150 | break; | |
14151 | ||
14152 | case CODE_LABEL: | |
14153 | fidx = 3; | |
14154 | break; | |
14155 | ||
14156 | default: | |
14157 | break; | |
14158 | } | |
9ebbca7d GK |
14159 | |
14160 | for (; fidx < flen; fidx++) | |
14161 | switch (format[fidx]) | |
14162 | { | |
14163 | case 's': | |
14164 | { | |
14165 | unsigned i, len; | |
14166 | const char *str = XSTR (k, fidx); | |
14167 | len = strlen (str); | |
14168 | result = result * 613 + len; | |
14169 | for (i = 0; i < len; i++) | |
14170 | result = result * 613 + (unsigned) str[i]; | |
17167fd8 MM |
14171 | break; |
14172 | } | |
9ebbca7d GK |
14173 | case 'u': |
14174 | case 'e': | |
14175 | result = result * 1231 + rs6000_hash_constant (XEXP (k, fidx)); | |
14176 | break; | |
14177 | case 'i': | |
14178 | case 'n': | |
14179 | result = result * 613 + (unsigned) XINT (k, fidx); | |
14180 | break; | |
14181 | case 'w': | |
14182 | if (sizeof (unsigned) >= sizeof (HOST_WIDE_INT)) | |
14183 | result = result * 613 + (unsigned) XWINT (k, fidx); | |
14184 | else | |
14185 | { | |
14186 | size_t i; | |
14187 | for (i = 0; i < sizeof(HOST_WIDE_INT)/sizeof(unsigned); i++) | |
14188 | result = result * 613 + (unsigned) (XWINT (k, fidx) | |
14189 | >> CHAR_BIT * i); | |
14190 | } | |
14191 | break; | |
09501938 DE |
14192 | case '0': |
14193 | break; | |
9ebbca7d | 14194 | default: |
a4f6c312 | 14195 | abort (); |
9ebbca7d | 14196 | } |
46b33600 | 14197 | |
9ebbca7d GK |
14198 | return result; |
14199 | } | |
14200 | ||
14201 | static unsigned | |
a2369ed3 | 14202 | toc_hash_function (const void *hash_entry) |
9ebbca7d | 14203 | { |
f676971a | 14204 | const struct toc_hash_struct *thc = |
a9098fd0 GK |
14205 | (const struct toc_hash_struct *) hash_entry; |
14206 | return rs6000_hash_constant (thc->key) ^ thc->key_mode; | |
9ebbca7d GK |
14207 | } |
14208 | ||
14209 | /* Compare H1 and H2 for equivalence. */ | |
14210 | ||
14211 | static int | |
a2369ed3 | 14212 | toc_hash_eq (const void *h1, const void *h2) |
9ebbca7d GK |
14213 | { |
14214 | rtx r1 = ((const struct toc_hash_struct *) h1)->key; | |
14215 | rtx r2 = ((const struct toc_hash_struct *) h2)->key; | |
14216 | ||
a9098fd0 GK |
14217 | if (((const struct toc_hash_struct *) h1)->key_mode |
14218 | != ((const struct toc_hash_struct *) h2)->key_mode) | |
14219 | return 0; | |
14220 | ||
5692c7bc | 14221 | return rtx_equal_p (r1, r2); |
9ebbca7d GK |
14222 | } |
14223 | ||
28e510bd MM |
14224 | /* These are the names given by the C++ front-end to vtables, and |
14225 | vtable-like objects. Ideally, this logic should not be here; | |
14226 | instead, there should be some programmatic way of inquiring as | |
14227 | to whether or not an object is a vtable. */ | |
14228 | ||
14229 | #define VTABLE_NAME_P(NAME) \ | |
14230 | (strncmp ("_vt.", name, strlen("_vt.")) == 0 \ | |
14231 | || strncmp ("_ZTV", name, strlen ("_ZTV")) == 0 \ | |
14232 | || strncmp ("_ZTT", name, strlen ("_ZTT")) == 0 \ | |
26be75db | 14233 | || strncmp ("_ZTI", name, strlen ("_ZTI")) == 0 \ |
f676971a | 14234 | || strncmp ("_ZTC", name, strlen ("_ZTC")) == 0) |
28e510bd MM |
14235 | |
14236 | void | |
a2369ed3 | 14237 | rs6000_output_symbol_ref (FILE *file, rtx x) |
28e510bd MM |
14238 | { |
14239 | /* Currently C++ toc references to vtables can be emitted before it | |
14240 | is decided whether the vtable is public or private. If this is | |
14241 | the case, then the linker will eventually complain that there is | |
f676971a | 14242 | a reference to an unknown section. Thus, for vtables only, |
28e510bd MM |
14243 | we emit the TOC reference to reference the symbol and not the |
14244 | section. */ | |
14245 | const char *name = XSTR (x, 0); | |
54ee9799 | 14246 | |
f676971a | 14247 | if (VTABLE_NAME_P (name)) |
54ee9799 DE |
14248 | { |
14249 | RS6000_OUTPUT_BASENAME (file, name); | |
14250 | } | |
14251 | else | |
14252 | assemble_name (file, name); | |
28e510bd MM |
14253 | } |
14254 | ||
a4f6c312 SS |
14255 | /* Output a TOC entry. We derive the entry name from what is being |
14256 | written. */ | |
9878760c RK |
14257 | |
14258 | void | |
a2369ed3 | 14259 | output_toc (FILE *file, rtx x, int labelno, enum machine_mode mode) |
9878760c RK |
14260 | { |
14261 | char buf[256]; | |
3cce094d | 14262 | const char *name = buf; |
ec940faa | 14263 | const char *real_name; |
9878760c RK |
14264 | rtx base = x; |
14265 | int offset = 0; | |
14266 | ||
4697a36c MM |
14267 | if (TARGET_NO_TOC) |
14268 | abort (); | |
14269 | ||
9ebbca7d GK |
14270 | /* When the linker won't eliminate them, don't output duplicate |
14271 | TOC entries (this happens on AIX if there is any kind of TOC, | |
17211ab5 GK |
14272 | and on SVR4 under -fPIC or -mrelocatable). Don't do this for |
14273 | CODE_LABELs. */ | |
14274 | if (TARGET_TOC && GET_CODE (x) != LABEL_REF) | |
9ebbca7d GK |
14275 | { |
14276 | struct toc_hash_struct *h; | |
14277 | void * * found; | |
f676971a | 14278 | |
17211ab5 | 14279 | /* Create toc_hash_table. This can't be done at OVERRIDE_OPTIONS |
c4ad648e | 14280 | time because GGC is not initialized at that point. */ |
17211ab5 | 14281 | if (toc_hash_table == NULL) |
f676971a | 14282 | toc_hash_table = htab_create_ggc (1021, toc_hash_function, |
17211ab5 GK |
14283 | toc_hash_eq, NULL); |
14284 | ||
9ebbca7d GK |
14285 | h = ggc_alloc (sizeof (*h)); |
14286 | h->key = x; | |
a9098fd0 | 14287 | h->key_mode = mode; |
9ebbca7d | 14288 | h->labelno = labelno; |
f676971a | 14289 | |
9ebbca7d GK |
14290 | found = htab_find_slot (toc_hash_table, h, 1); |
14291 | if (*found == NULL) | |
14292 | *found = h; | |
f676971a | 14293 | else /* This is indeed a duplicate. |
9ebbca7d GK |
14294 | Set this label equal to that label. */ |
14295 | { | |
14296 | fputs ("\t.set ", file); | |
14297 | ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC"); | |
14298 | fprintf (file, "%d,", labelno); | |
14299 | ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC"); | |
f676971a | 14300 | fprintf (file, "%d\n", ((*(const struct toc_hash_struct **) |
9ebbca7d GK |
14301 | found)->labelno)); |
14302 | return; | |
14303 | } | |
14304 | } | |
14305 | ||
14306 | /* If we're going to put a double constant in the TOC, make sure it's | |
14307 | aligned properly when strict alignment is on. */ | |
ff1720ed RK |
14308 | if (GET_CODE (x) == CONST_DOUBLE |
14309 | && STRICT_ALIGNMENT | |
a9098fd0 | 14310 | && GET_MODE_BITSIZE (mode) >= 64 |
ff1720ed RK |
14311 | && ! (TARGET_NO_FP_IN_TOC && ! TARGET_MINIMAL_TOC)) { |
14312 | ASM_OUTPUT_ALIGN (file, 3); | |
14313 | } | |
14314 | ||
4977bab6 | 14315 | (*targetm.asm_out.internal_label) (file, "LC", labelno); |
9878760c | 14316 | |
37c37a57 RK |
14317 | /* Handle FP constants specially. Note that if we have a minimal |
14318 | TOC, things we put here aren't actually in the TOC, so we can allow | |
14319 | FP constants. */ | |
fcce224d DE |
14320 | if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == TFmode) |
14321 | { | |
14322 | REAL_VALUE_TYPE rv; | |
14323 | long k[4]; | |
14324 | ||
14325 | REAL_VALUE_FROM_CONST_DOUBLE (rv, x); | |
14326 | REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv, k); | |
14327 | ||
14328 | if (TARGET_64BIT) | |
14329 | { | |
14330 | if (TARGET_MINIMAL_TOC) | |
14331 | fputs (DOUBLE_INT_ASM_OP, file); | |
14332 | else | |
14333 | fprintf (file, "\t.tc FT_%lx_%lx_%lx_%lx[TC],", | |
14334 | k[0] & 0xffffffff, k[1] & 0xffffffff, | |
14335 | k[2] & 0xffffffff, k[3] & 0xffffffff); | |
14336 | fprintf (file, "0x%lx%08lx,0x%lx%08lx\n", | |
14337 | k[0] & 0xffffffff, k[1] & 0xffffffff, | |
14338 | k[2] & 0xffffffff, k[3] & 0xffffffff); | |
14339 | return; | |
14340 | } | |
14341 | else | |
14342 | { | |
14343 | if (TARGET_MINIMAL_TOC) | |
14344 | fputs ("\t.long ", file); | |
14345 | else | |
14346 | fprintf (file, "\t.tc FT_%lx_%lx_%lx_%lx[TC],", | |
14347 | k[0] & 0xffffffff, k[1] & 0xffffffff, | |
14348 | k[2] & 0xffffffff, k[3] & 0xffffffff); | |
14349 | fprintf (file, "0x%lx,0x%lx,0x%lx,0x%lx\n", | |
14350 | k[0] & 0xffffffff, k[1] & 0xffffffff, | |
14351 | k[2] & 0xffffffff, k[3] & 0xffffffff); | |
14352 | return; | |
14353 | } | |
14354 | } | |
14355 | else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == DFmode) | |
9878760c | 14356 | { |
042259f2 DE |
14357 | REAL_VALUE_TYPE rv; |
14358 | long k[2]; | |
0adc764e | 14359 | |
042259f2 DE |
14360 | REAL_VALUE_FROM_CONST_DOUBLE (rv, x); |
14361 | REAL_VALUE_TO_TARGET_DOUBLE (rv, k); | |
31bfaa0b | 14362 | |
13ded975 DE |
14363 | if (TARGET_64BIT) |
14364 | { | |
14365 | if (TARGET_MINIMAL_TOC) | |
2bfcf297 | 14366 | fputs (DOUBLE_INT_ASM_OP, file); |
13ded975 | 14367 | else |
2f0552b6 AM |
14368 | fprintf (file, "\t.tc FD_%lx_%lx[TC],", |
14369 | k[0] & 0xffffffff, k[1] & 0xffffffff); | |
14370 | fprintf (file, "0x%lx%08lx\n", | |
14371 | k[0] & 0xffffffff, k[1] & 0xffffffff); | |
13ded975 DE |
14372 | return; |
14373 | } | |
1875cc88 | 14374 | else |
13ded975 DE |
14375 | { |
14376 | if (TARGET_MINIMAL_TOC) | |
2bfcf297 | 14377 | fputs ("\t.long ", file); |
13ded975 | 14378 | else |
2f0552b6 AM |
14379 | fprintf (file, "\t.tc FD_%lx_%lx[TC],", |
14380 | k[0] & 0xffffffff, k[1] & 0xffffffff); | |
14381 | fprintf (file, "0x%lx,0x%lx\n", | |
14382 | k[0] & 0xffffffff, k[1] & 0xffffffff); | |
13ded975 DE |
14383 | return; |
14384 | } | |
9878760c | 14385 | } |
a9098fd0 | 14386 | else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == SFmode) |
9878760c | 14387 | { |
042259f2 DE |
14388 | REAL_VALUE_TYPE rv; |
14389 | long l; | |
9878760c | 14390 | |
042259f2 DE |
14391 | REAL_VALUE_FROM_CONST_DOUBLE (rv, x); |
14392 | REAL_VALUE_TO_TARGET_SINGLE (rv, l); | |
14393 | ||
31bfaa0b DE |
14394 | if (TARGET_64BIT) |
14395 | { | |
14396 | if (TARGET_MINIMAL_TOC) | |
2bfcf297 | 14397 | fputs (DOUBLE_INT_ASM_OP, file); |
31bfaa0b | 14398 | else |
2f0552b6 AM |
14399 | fprintf (file, "\t.tc FS_%lx[TC],", l & 0xffffffff); |
14400 | fprintf (file, "0x%lx00000000\n", l & 0xffffffff); | |
31bfaa0b DE |
14401 | return; |
14402 | } | |
042259f2 | 14403 | else |
31bfaa0b DE |
14404 | { |
14405 | if (TARGET_MINIMAL_TOC) | |
2bfcf297 | 14406 | fputs ("\t.long ", file); |
31bfaa0b | 14407 | else |
2f0552b6 AM |
14408 | fprintf (file, "\t.tc FS_%lx[TC],", l & 0xffffffff); |
14409 | fprintf (file, "0x%lx\n", l & 0xffffffff); | |
31bfaa0b DE |
14410 | return; |
14411 | } | |
042259f2 | 14412 | } |
f176e826 | 14413 | else if (GET_MODE (x) == VOIDmode |
a9098fd0 | 14414 | && (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE)) |
042259f2 | 14415 | { |
e2c953b6 | 14416 | unsigned HOST_WIDE_INT low; |
042259f2 DE |
14417 | HOST_WIDE_INT high; |
14418 | ||
14419 | if (GET_CODE (x) == CONST_DOUBLE) | |
14420 | { | |
14421 | low = CONST_DOUBLE_LOW (x); | |
14422 | high = CONST_DOUBLE_HIGH (x); | |
14423 | } | |
14424 | else | |
14425 | #if HOST_BITS_PER_WIDE_INT == 32 | |
14426 | { | |
14427 | low = INTVAL (x); | |
0858c623 | 14428 | high = (low & 0x80000000) ? ~0 : 0; |
042259f2 DE |
14429 | } |
14430 | #else | |
14431 | { | |
c4ad648e AM |
14432 | low = INTVAL (x) & 0xffffffff; |
14433 | high = (HOST_WIDE_INT) INTVAL (x) >> 32; | |
042259f2 DE |
14434 | } |
14435 | #endif | |
9878760c | 14436 | |
a9098fd0 GK |
14437 | /* TOC entries are always Pmode-sized, but since this |
14438 | is a bigendian machine then if we're putting smaller | |
14439 | integer constants in the TOC we have to pad them. | |
14440 | (This is still a win over putting the constants in | |
14441 | a separate constant pool, because then we'd have | |
02a4ec28 FS |
14442 | to have both a TOC entry _and_ the actual constant.) |
14443 | ||
14444 | For a 32-bit target, CONST_INT values are loaded and shifted | |
14445 | entirely within `low' and can be stored in one TOC entry. */ | |
14446 | ||
14447 | if (TARGET_64BIT && POINTER_SIZE < GET_MODE_BITSIZE (mode)) | |
a9098fd0 | 14448 | abort ();/* It would be easy to make this work, but it doesn't now. */ |
02a4ec28 FS |
14449 | |
14450 | if (POINTER_SIZE > GET_MODE_BITSIZE (mode)) | |
fb52d8de AM |
14451 | { |
14452 | #if HOST_BITS_PER_WIDE_INT == 32 | |
14453 | lshift_double (low, high, POINTER_SIZE - GET_MODE_BITSIZE (mode), | |
14454 | POINTER_SIZE, &low, &high, 0); | |
14455 | #else | |
14456 | low |= high << 32; | |
14457 | low <<= POINTER_SIZE - GET_MODE_BITSIZE (mode); | |
14458 | high = (HOST_WIDE_INT) low >> 32; | |
14459 | low &= 0xffffffff; | |
14460 | #endif | |
14461 | } | |
a9098fd0 | 14462 | |
13ded975 DE |
14463 | if (TARGET_64BIT) |
14464 | { | |
14465 | if (TARGET_MINIMAL_TOC) | |
2bfcf297 | 14466 | fputs (DOUBLE_INT_ASM_OP, file); |
13ded975 | 14467 | else |
2f0552b6 AM |
14468 | fprintf (file, "\t.tc ID_%lx_%lx[TC],", |
14469 | (long) high & 0xffffffff, (long) low & 0xffffffff); | |
14470 | fprintf (file, "0x%lx%08lx\n", | |
14471 | (long) high & 0xffffffff, (long) low & 0xffffffff); | |
13ded975 DE |
14472 | return; |
14473 | } | |
1875cc88 | 14474 | else |
13ded975 | 14475 | { |
02a4ec28 FS |
14476 | if (POINTER_SIZE < GET_MODE_BITSIZE (mode)) |
14477 | { | |
14478 | if (TARGET_MINIMAL_TOC) | |
2bfcf297 | 14479 | fputs ("\t.long ", file); |
02a4ec28 | 14480 | else |
2bfcf297 | 14481 | fprintf (file, "\t.tc ID_%lx_%lx[TC],", |
2f0552b6 AM |
14482 | (long) high & 0xffffffff, (long) low & 0xffffffff); |
14483 | fprintf (file, "0x%lx,0x%lx\n", | |
14484 | (long) high & 0xffffffff, (long) low & 0xffffffff); | |
02a4ec28 | 14485 | } |
13ded975 | 14486 | else |
02a4ec28 FS |
14487 | { |
14488 | if (TARGET_MINIMAL_TOC) | |
2bfcf297 | 14489 | fputs ("\t.long ", file); |
02a4ec28 | 14490 | else |
2f0552b6 AM |
14491 | fprintf (file, "\t.tc IS_%lx[TC],", (long) low & 0xffffffff); |
14492 | fprintf (file, "0x%lx\n", (long) low & 0xffffffff); | |
02a4ec28 | 14493 | } |
13ded975 DE |
14494 | return; |
14495 | } | |
9878760c RK |
14496 | } |
14497 | ||
14498 | if (GET_CODE (x) == CONST) | |
14499 | { | |
2bfcf297 DB |
14500 | if (GET_CODE (XEXP (x, 0)) != PLUS) |
14501 | abort (); | |
14502 | ||
9878760c RK |
14503 | base = XEXP (XEXP (x, 0), 0); |
14504 | offset = INTVAL (XEXP (XEXP (x, 0), 1)); | |
14505 | } | |
f676971a | 14506 | |
9878760c RK |
14507 | if (GET_CODE (base) == SYMBOL_REF) |
14508 | name = XSTR (base, 0); | |
14509 | else if (GET_CODE (base) == LABEL_REF) | |
14510 | ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (XEXP (base, 0))); | |
14511 | else if (GET_CODE (base) == CODE_LABEL) | |
14512 | ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (base)); | |
14513 | else | |
14514 | abort (); | |
14515 | ||
772c5265 | 14516 | real_name = (*targetm.strip_name_encoding) (name); |
1875cc88 | 14517 | if (TARGET_MINIMAL_TOC) |
2bfcf297 | 14518 | fputs (TARGET_32BIT ? "\t.long " : DOUBLE_INT_ASM_OP, file); |
1875cc88 JW |
14519 | else |
14520 | { | |
b6c9286a | 14521 | fprintf (file, "\t.tc %s", real_name); |
9878760c | 14522 | |
1875cc88 JW |
14523 | if (offset < 0) |
14524 | fprintf (file, ".N%d", - offset); | |
14525 | else if (offset) | |
14526 | fprintf (file, ".P%d", offset); | |
9878760c | 14527 | |
19d2d16f | 14528 | fputs ("[TC],", file); |
1875cc88 | 14529 | } |
581bc4de MM |
14530 | |
14531 | /* Currently C++ toc references to vtables can be emitted before it | |
14532 | is decided whether the vtable is public or private. If this is | |
14533 | the case, then the linker will eventually complain that there is | |
14534 | a TOC reference to an unknown section. Thus, for vtables only, | |
14535 | we emit the TOC reference to reference the symbol and not the | |
14536 | section. */ | |
28e510bd | 14537 | if (VTABLE_NAME_P (name)) |
581bc4de | 14538 | { |
54ee9799 | 14539 | RS6000_OUTPUT_BASENAME (file, name); |
581bc4de MM |
14540 | if (offset < 0) |
14541 | fprintf (file, "%d", offset); | |
14542 | else if (offset > 0) | |
14543 | fprintf (file, "+%d", offset); | |
14544 | } | |
14545 | else | |
14546 | output_addr_const (file, x); | |
19d2d16f | 14547 | putc ('\n', file); |
9878760c RK |
14548 | } |
14549 | \f | |
14550 | /* Output an assembler pseudo-op to write an ASCII string of N characters | |
14551 | starting at P to FILE. | |
14552 | ||
14553 | On the RS/6000, we have to do this using the .byte operation and | |
14554 | write out special characters outside the quoted string. | |
14555 | Also, the assembler is broken; very long strings are truncated, | |
a4f6c312 | 14556 | so we must artificially break them up early. */ |
9878760c RK |
14557 | |
14558 | void | |
a2369ed3 | 14559 | output_ascii (FILE *file, const char *p, int n) |
9878760c RK |
14560 | { |
14561 | char c; | |
14562 | int i, count_string; | |
d330fd93 KG |
14563 | const char *for_string = "\t.byte \""; |
14564 | const char *for_decimal = "\t.byte "; | |
14565 | const char *to_close = NULL; | |
9878760c RK |
14566 | |
14567 | count_string = 0; | |
14568 | for (i = 0; i < n; i++) | |
14569 | { | |
14570 | c = *p++; | |
14571 | if (c >= ' ' && c < 0177) | |
14572 | { | |
14573 | if (for_string) | |
14574 | fputs (for_string, file); | |
14575 | putc (c, file); | |
14576 | ||
14577 | /* Write two quotes to get one. */ | |
14578 | if (c == '"') | |
14579 | { | |
14580 | putc (c, file); | |
14581 | ++count_string; | |
14582 | } | |
14583 | ||
14584 | for_string = NULL; | |
14585 | for_decimal = "\"\n\t.byte "; | |
14586 | to_close = "\"\n"; | |
14587 | ++count_string; | |
14588 | ||
14589 | if (count_string >= 512) | |
14590 | { | |
14591 | fputs (to_close, file); | |
14592 | ||
14593 | for_string = "\t.byte \""; | |
14594 | for_decimal = "\t.byte "; | |
14595 | to_close = NULL; | |
14596 | count_string = 0; | |
14597 | } | |
14598 | } | |
14599 | else | |
14600 | { | |
14601 | if (for_decimal) | |
14602 | fputs (for_decimal, file); | |
14603 | fprintf (file, "%d", c); | |
14604 | ||
14605 | for_string = "\n\t.byte \""; | |
14606 | for_decimal = ", "; | |
14607 | to_close = "\n"; | |
14608 | count_string = 0; | |
14609 | } | |
14610 | } | |
14611 | ||
14612 | /* Now close the string if we have written one. Then end the line. */ | |
14613 | if (to_close) | |
9ebbca7d | 14614 | fputs (to_close, file); |
9878760c RK |
14615 | } |
14616 | \f | |
14617 | /* Generate a unique section name for FILENAME for a section type | |
14618 | represented by SECTION_DESC. Output goes into BUF. | |
14619 | ||
14620 | SECTION_DESC can be any string, as long as it is different for each | |
14621 | possible section type. | |
14622 | ||
14623 | We name the section in the same manner as xlc. The name begins with an | |
14624 | underscore followed by the filename (after stripping any leading directory | |
11e5fe42 RK |
14625 | names) with the last period replaced by the string SECTION_DESC. If |
14626 | FILENAME does not contain a period, SECTION_DESC is appended to the end of | |
14627 | the name. */ | |
9878760c RK |
14628 | |
14629 | void | |
f676971a | 14630 | rs6000_gen_section_name (char **buf, const char *filename, |
c4ad648e | 14631 | const char *section_desc) |
9878760c | 14632 | { |
9ebbca7d | 14633 | const char *q, *after_last_slash, *last_period = 0; |
9878760c RK |
14634 | char *p; |
14635 | int len; | |
9878760c RK |
14636 | |
14637 | after_last_slash = filename; | |
14638 | for (q = filename; *q; q++) | |
11e5fe42 RK |
14639 | { |
14640 | if (*q == '/') | |
14641 | after_last_slash = q + 1; | |
14642 | else if (*q == '.') | |
14643 | last_period = q; | |
14644 | } | |
9878760c | 14645 | |
11e5fe42 | 14646 | len = strlen (after_last_slash) + strlen (section_desc) + 2; |
6d9f628e | 14647 | *buf = (char *) xmalloc (len); |
9878760c RK |
14648 | |
14649 | p = *buf; | |
14650 | *p++ = '_'; | |
14651 | ||
14652 | for (q = after_last_slash; *q; q++) | |
14653 | { | |
11e5fe42 | 14654 | if (q == last_period) |
c4ad648e | 14655 | { |
9878760c RK |
14656 | strcpy (p, section_desc); |
14657 | p += strlen (section_desc); | |
e3981aab | 14658 | break; |
c4ad648e | 14659 | } |
9878760c | 14660 | |
e9a780ec | 14661 | else if (ISALNUM (*q)) |
c4ad648e | 14662 | *p++ = *q; |
9878760c RK |
14663 | } |
14664 | ||
11e5fe42 | 14665 | if (last_period == 0) |
9878760c RK |
14666 | strcpy (p, section_desc); |
14667 | else | |
14668 | *p = '\0'; | |
14669 | } | |
e165f3f0 | 14670 | \f |
a4f6c312 | 14671 | /* Emit profile function. */ |
411707f4 | 14672 | |
411707f4 | 14673 | void |
a2369ed3 | 14674 | output_profile_hook (int labelno ATTRIBUTE_UNUSED) |
411707f4 | 14675 | { |
ffcfcb5f AM |
14676 | if (TARGET_PROFILE_KERNEL) |
14677 | return; | |
14678 | ||
8480e480 CC |
14679 | if (DEFAULT_ABI == ABI_AIX) |
14680 | { | |
9739c90c JJ |
14681 | #ifndef NO_PROFILE_COUNTERS |
14682 | # define NO_PROFILE_COUNTERS 0 | |
14683 | #endif | |
f676971a | 14684 | if (NO_PROFILE_COUNTERS) |
9739c90c JJ |
14685 | emit_library_call (init_one_libfunc (RS6000_MCOUNT), 0, VOIDmode, 0); |
14686 | else | |
14687 | { | |
14688 | char buf[30]; | |
14689 | const char *label_name; | |
14690 | rtx fun; | |
411707f4 | 14691 | |
9739c90c JJ |
14692 | ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno); |
14693 | label_name = (*targetm.strip_name_encoding) (ggc_strdup (buf)); | |
14694 | fun = gen_rtx_SYMBOL_REF (Pmode, label_name); | |
411707f4 | 14695 | |
9739c90c JJ |
14696 | emit_library_call (init_one_libfunc (RS6000_MCOUNT), 0, VOIDmode, 1, |
14697 | fun, Pmode); | |
14698 | } | |
8480e480 | 14699 | } |
ee890fe2 SS |
14700 | else if (DEFAULT_ABI == ABI_DARWIN) |
14701 | { | |
d5fa86ba | 14702 | const char *mcount_name = RS6000_MCOUNT; |
ee890fe2 SS |
14703 | int caller_addr_regno = LINK_REGISTER_REGNUM; |
14704 | ||
14705 | /* Be conservative and always set this, at least for now. */ | |
14706 | current_function_uses_pic_offset_table = 1; | |
14707 | ||
14708 | #if TARGET_MACHO | |
14709 | /* For PIC code, set up a stub and collect the caller's address | |
14710 | from r0, which is where the prologue puts it. */ | |
11abc112 MM |
14711 | if (MACHOPIC_INDIRECT |
14712 | && current_function_uses_pic_offset_table) | |
14713 | caller_addr_regno = 0; | |
ee890fe2 SS |
14714 | #endif |
14715 | emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mcount_name), | |
14716 | 0, VOIDmode, 1, | |
14717 | gen_rtx_REG (Pmode, caller_addr_regno), Pmode); | |
14718 | } | |
411707f4 CC |
14719 | } |
14720 | ||
a4f6c312 | 14721 | /* Write function profiler code. */ |
e165f3f0 RK |
14722 | |
14723 | void | |
a2369ed3 | 14724 | output_function_profiler (FILE *file, int labelno) |
e165f3f0 | 14725 | { |
3daf36a4 | 14726 | char buf[100]; |
09eeeacb | 14727 | int save_lr = 8; |
e165f3f0 | 14728 | |
38c1f2d7 | 14729 | switch (DEFAULT_ABI) |
3daf36a4 | 14730 | { |
38c1f2d7 MM |
14731 | default: |
14732 | abort (); | |
14733 | ||
14734 | case ABI_V4: | |
09eeeacb | 14735 | save_lr = 4; |
09eeeacb AM |
14736 | if (!TARGET_32BIT) |
14737 | { | |
14738 | warning ("no profiling of 64-bit code for this ABI"); | |
14739 | return; | |
14740 | } | |
ffcfcb5f | 14741 | ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno); |
38c1f2d7 MM |
14742 | fprintf (file, "\tmflr %s\n", reg_names[0]); |
14743 | if (flag_pic == 1) | |
14744 | { | |
dfdfa60f | 14745 | fputs ("\tbl _GLOBAL_OFFSET_TABLE_@local-4\n", file); |
09eeeacb AM |
14746 | asm_fprintf (file, "\t{st|stw} %s,%d(%s)\n", |
14747 | reg_names[0], save_lr, reg_names[1]); | |
17167fd8 | 14748 | asm_fprintf (file, "\tmflr %s\n", reg_names[12]); |
dfdfa60f | 14749 | asm_fprintf (file, "\t{l|lwz} %s,", reg_names[0]); |
38c1f2d7 | 14750 | assemble_name (file, buf); |
17167fd8 | 14751 | asm_fprintf (file, "@got(%s)\n", reg_names[12]); |
38c1f2d7 | 14752 | } |
9ebbca7d | 14753 | else if (flag_pic > 1) |
38c1f2d7 | 14754 | { |
09eeeacb AM |
14755 | asm_fprintf (file, "\t{st|stw} %s,%d(%s)\n", |
14756 | reg_names[0], save_lr, reg_names[1]); | |
9ebbca7d GK |
14757 | /* Now, we need to get the address of the label. */ |
14758 | fputs ("\tbl 1f\n\t.long ", file); | |
034e84c4 | 14759 | assemble_name (file, buf); |
9ebbca7d GK |
14760 | fputs ("-.\n1:", file); |
14761 | asm_fprintf (file, "\tmflr %s\n", reg_names[11]); | |
f676971a | 14762 | asm_fprintf (file, "\t{l|lwz} %s,0(%s)\n", |
9ebbca7d GK |
14763 | reg_names[0], reg_names[11]); |
14764 | asm_fprintf (file, "\t{cax|add} %s,%s,%s\n", | |
14765 | reg_names[0], reg_names[0], reg_names[11]); | |
38c1f2d7 | 14766 | } |
38c1f2d7 MM |
14767 | else |
14768 | { | |
17167fd8 | 14769 | asm_fprintf (file, "\t{liu|lis} %s,", reg_names[12]); |
38c1f2d7 | 14770 | assemble_name (file, buf); |
dfdfa60f | 14771 | fputs ("@ha\n", file); |
09eeeacb AM |
14772 | asm_fprintf (file, "\t{st|stw} %s,%d(%s)\n", |
14773 | reg_names[0], save_lr, reg_names[1]); | |
a260abc9 | 14774 | asm_fprintf (file, "\t{cal|la} %s,", reg_names[0]); |
38c1f2d7 | 14775 | assemble_name (file, buf); |
17167fd8 | 14776 | asm_fprintf (file, "@l(%s)\n", reg_names[12]); |
38c1f2d7 MM |
14777 | } |
14778 | ||
50d440bc | 14779 | /* ABI_V4 saves the static chain reg with ASM_OUTPUT_REG_PUSH. */ |
3b6ce0af DE |
14780 | fprintf (file, "\tbl %s%s\n", |
14781 | RS6000_MCOUNT, flag_pic ? "@plt" : ""); | |
38c1f2d7 MM |
14782 | break; |
14783 | ||
14784 | case ABI_AIX: | |
ee890fe2 | 14785 | case ABI_DARWIN: |
ffcfcb5f AM |
14786 | if (!TARGET_PROFILE_KERNEL) |
14787 | { | |
a3c9585f | 14788 | /* Don't do anything, done in output_profile_hook (). */ |
ffcfcb5f AM |
14789 | } |
14790 | else | |
14791 | { | |
14792 | if (TARGET_32BIT) | |
14793 | abort (); | |
14794 | ||
14795 | asm_fprintf (file, "\tmflr %s\n", reg_names[0]); | |
14796 | asm_fprintf (file, "\tstd %s,16(%s)\n", reg_names[0], reg_names[1]); | |
14797 | ||
6de9cd9a | 14798 | if (cfun->static_chain_decl != NULL) |
ffcfcb5f AM |
14799 | { |
14800 | asm_fprintf (file, "\tstd %s,24(%s)\n", | |
14801 | reg_names[STATIC_CHAIN_REGNUM], reg_names[1]); | |
14802 | fprintf (file, "\tbl %s\n", RS6000_MCOUNT); | |
14803 | asm_fprintf (file, "\tld %s,24(%s)\n", | |
14804 | reg_names[STATIC_CHAIN_REGNUM], reg_names[1]); | |
14805 | } | |
14806 | else | |
14807 | fprintf (file, "\tbl %s\n", RS6000_MCOUNT); | |
14808 | } | |
38c1f2d7 MM |
14809 | break; |
14810 | } | |
e165f3f0 | 14811 | } |
a251ffd0 | 14812 | |
b54cf83a | 14813 | \f |
b54cf83a DE |
14814 | /* Power4 load update and store update instructions are cracked into a |
14815 | load or store and an integer insn which are executed in the same cycle. | |
14816 | Branches have their own dispatch slot which does not count against the | |
14817 | GCC issue rate, but it changes the program flow so there are no other | |
14818 | instructions to issue in this cycle. */ | |
14819 | ||
14820 | static int | |
f676971a EC |
14821 | rs6000_variable_issue (FILE *stream ATTRIBUTE_UNUSED, |
14822 | int verbose ATTRIBUTE_UNUSED, | |
a2369ed3 | 14823 | rtx insn, int more) |
b54cf83a DE |
14824 | { |
14825 | if (GET_CODE (PATTERN (insn)) == USE | |
14826 | || GET_CODE (PATTERN (insn)) == CLOBBER) | |
14827 | return more; | |
14828 | ||
ec507f2d | 14829 | if (rs6000_sched_groups) |
b54cf83a | 14830 | { |
cbe26ab8 | 14831 | if (is_microcoded_insn (insn)) |
c4ad648e | 14832 | return 0; |
cbe26ab8 | 14833 | else if (is_cracked_insn (insn)) |
c4ad648e | 14834 | return more > 2 ? more - 2 : 0; |
b54cf83a | 14835 | } |
165b263e DE |
14836 | |
14837 | return more - 1; | |
b54cf83a DE |
14838 | } |
14839 | ||
a251ffd0 TG |
14840 | /* Adjust the cost of a scheduling dependency. Return the new cost of |
14841 | a dependency LINK or INSN on DEP_INSN. COST is the current cost. */ | |
14842 | ||
c237e94a | 14843 | static int |
0a4f0294 | 14844 | rs6000_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost) |
a251ffd0 TG |
14845 | { |
14846 | if (! recog_memoized (insn)) | |
14847 | return 0; | |
14848 | ||
14849 | if (REG_NOTE_KIND (link) != 0) | |
14850 | return 0; | |
14851 | ||
14852 | if (REG_NOTE_KIND (link) == 0) | |
14853 | { | |
ed947a96 DJ |
14854 | /* Data dependency; DEP_INSN writes a register that INSN reads |
14855 | some cycles later. */ | |
c9dbf840 DE |
14856 | |
14857 | /* Separate a load from a narrower, dependent store. */ | |
14858 | if (rs6000_sched_groups | |
14859 | && GET_CODE (PATTERN (insn)) == SET | |
14860 | && GET_CODE (PATTERN (dep_insn)) == SET | |
14861 | && GET_CODE (XEXP (PATTERN (insn), 1)) == MEM | |
14862 | && GET_CODE (XEXP (PATTERN (dep_insn), 0)) == MEM | |
14863 | && (GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (insn), 1))) | |
14864 | > GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (dep_insn), 0))))) | |
14865 | return cost + 14; | |
14866 | ||
ed947a96 DJ |
14867 | switch (get_attr_type (insn)) |
14868 | { | |
14869 | case TYPE_JMPREG: | |
309323c2 | 14870 | /* Tell the first scheduling pass about the latency between |
ed947a96 DJ |
14871 | a mtctr and bctr (and mtlr and br/blr). The first |
14872 | scheduling pass will not know about this latency since | |
14873 | the mtctr instruction, which has the latency associated | |
14874 | to it, will be generated by reload. */ | |
309323c2 | 14875 | return TARGET_POWER ? 5 : 4; |
ed947a96 DJ |
14876 | case TYPE_BRANCH: |
14877 | /* Leave some extra cycles between a compare and its | |
14878 | dependent branch, to inhibit expensive mispredicts. */ | |
309323c2 DE |
14879 | if ((rs6000_cpu_attr == CPU_PPC603 |
14880 | || rs6000_cpu_attr == CPU_PPC604 | |
14881 | || rs6000_cpu_attr == CPU_PPC604E | |
14882 | || rs6000_cpu_attr == CPU_PPC620 | |
14883 | || rs6000_cpu_attr == CPU_PPC630 | |
14884 | || rs6000_cpu_attr == CPU_PPC750 | |
14885 | || rs6000_cpu_attr == CPU_PPC7400 | |
14886 | || rs6000_cpu_attr == CPU_PPC7450 | |
ec507f2d DE |
14887 | || rs6000_cpu_attr == CPU_POWER4 |
14888 | || rs6000_cpu_attr == CPU_POWER5) | |
ed947a96 DJ |
14889 | && recog_memoized (dep_insn) |
14890 | && (INSN_CODE (dep_insn) >= 0) | |
b54cf83a DE |
14891 | && (get_attr_type (dep_insn) == TYPE_CMP |
14892 | || get_attr_type (dep_insn) == TYPE_COMPARE | |
ed947a96 | 14893 | || get_attr_type (dep_insn) == TYPE_DELAYED_COMPARE |
9259f3b0 DE |
14894 | || get_attr_type (dep_insn) == TYPE_IMUL_COMPARE |
14895 | || get_attr_type (dep_insn) == TYPE_LMUL_COMPARE | |
ed947a96 | 14896 | || get_attr_type (dep_insn) == TYPE_FPCOMPARE |
b54cf83a DE |
14897 | || get_attr_type (dep_insn) == TYPE_CR_LOGICAL |
14898 | || get_attr_type (dep_insn) == TYPE_DELAYED_CR)) | |
ed947a96 DJ |
14899 | return cost + 2; |
14900 | default: | |
14901 | break; | |
14902 | } | |
a251ffd0 TG |
14903 | /* Fall out to return default cost. */ |
14904 | } | |
14905 | ||
14906 | return cost; | |
14907 | } | |
b6c9286a | 14908 | |
cbe26ab8 | 14909 | /* The function returns a true if INSN is microcoded. |
839a4992 | 14910 | Return false otherwise. */ |
cbe26ab8 DN |
14911 | |
14912 | static bool | |
14913 | is_microcoded_insn (rtx insn) | |
14914 | { | |
14915 | if (!insn || !INSN_P (insn) | |
14916 | || GET_CODE (PATTERN (insn)) == USE | |
14917 | || GET_CODE (PATTERN (insn)) == CLOBBER) | |
14918 | return false; | |
14919 | ||
ec507f2d | 14920 | if (rs6000_sched_groups) |
cbe26ab8 DN |
14921 | { |
14922 | enum attr_type type = get_attr_type (insn); | |
14923 | if (type == TYPE_LOAD_EXT_U | |
14924 | || type == TYPE_LOAD_EXT_UX | |
14925 | || type == TYPE_LOAD_UX | |
14926 | || type == TYPE_STORE_UX | |
14927 | || type == TYPE_MFCR) | |
c4ad648e | 14928 | return true; |
cbe26ab8 DN |
14929 | } |
14930 | ||
14931 | return false; | |
14932 | } | |
14933 | ||
5c425df5 | 14934 | /* The function returns a nonzero value if INSN can be scheduled only |
cbe26ab8 DN |
14935 | as the first insn in a dispatch group ("dispatch-slot restricted"). |
14936 | In this case, the returned value indicates how many dispatch slots | |
14937 | the insn occupies (at the beginning of the group). | |
79ae11c4 DN |
14938 | Return 0 otherwise. */ |
14939 | ||
cbe26ab8 | 14940 | static int |
79ae11c4 DN |
14941 | is_dispatch_slot_restricted (rtx insn) |
14942 | { | |
14943 | enum attr_type type; | |
14944 | ||
ec507f2d | 14945 | if (!rs6000_sched_groups) |
79ae11c4 DN |
14946 | return 0; |
14947 | ||
14948 | if (!insn | |
14949 | || insn == NULL_RTX | |
14950 | || GET_CODE (insn) == NOTE | |
14951 | || GET_CODE (PATTERN (insn)) == USE | |
14952 | || GET_CODE (PATTERN (insn)) == CLOBBER) | |
14953 | return 0; | |
14954 | ||
14955 | type = get_attr_type (insn); | |
14956 | ||
ec507f2d DE |
14957 | switch (type) |
14958 | { | |
14959 | case TYPE_MFCR: | |
14960 | case TYPE_MFCRF: | |
14961 | case TYPE_MTCR: | |
14962 | case TYPE_DELAYED_CR: | |
14963 | case TYPE_CR_LOGICAL: | |
14964 | case TYPE_MTJMPR: | |
14965 | case TYPE_MFJMPR: | |
14966 | return 1; | |
14967 | case TYPE_IDIV: | |
14968 | case TYPE_LDIV: | |
14969 | return 2; | |
14970 | default: | |
14971 | if (rs6000_cpu == PROCESSOR_POWER5 | |
14972 | && is_cracked_insn (insn)) | |
14973 | return 2; | |
14974 | return 0; | |
14975 | } | |
79ae11c4 DN |
14976 | } |
14977 | ||
cbe26ab8 DN |
14978 | /* The function returns true if INSN is cracked into 2 instructions |
14979 | by the processor (and therefore occupies 2 issue slots). */ | |
14980 | ||
14981 | static bool | |
14982 | is_cracked_insn (rtx insn) | |
14983 | { | |
14984 | if (!insn || !INSN_P (insn) | |
14985 | || GET_CODE (PATTERN (insn)) == USE | |
14986 | || GET_CODE (PATTERN (insn)) == CLOBBER) | |
14987 | return false; | |
14988 | ||
ec507f2d | 14989 | if (rs6000_sched_groups) |
cbe26ab8 DN |
14990 | { |
14991 | enum attr_type type = get_attr_type (insn); | |
14992 | if (type == TYPE_LOAD_U || type == TYPE_STORE_U | |
c4ad648e AM |
14993 | || type == TYPE_FPLOAD_U || type == TYPE_FPSTORE_U |
14994 | || type == TYPE_FPLOAD_UX || type == TYPE_FPSTORE_UX | |
14995 | || type == TYPE_LOAD_EXT || type == TYPE_DELAYED_CR | |
14996 | || type == TYPE_COMPARE || type == TYPE_DELAYED_COMPARE | |
14997 | || type == TYPE_IMUL_COMPARE || type == TYPE_LMUL_COMPARE | |
14998 | || type == TYPE_IDIV || type == TYPE_LDIV | |
14999 | || type == TYPE_INSERT_WORD) | |
15000 | return true; | |
cbe26ab8 DN |
15001 | } |
15002 | ||
15003 | return false; | |
15004 | } | |
15005 | ||
15006 | /* The function returns true if INSN can be issued only from | |
a3c9585f | 15007 | the branch slot. */ |
cbe26ab8 DN |
15008 | |
15009 | static bool | |
15010 | is_branch_slot_insn (rtx insn) | |
15011 | { | |
15012 | if (!insn || !INSN_P (insn) | |
15013 | || GET_CODE (PATTERN (insn)) == USE | |
15014 | || GET_CODE (PATTERN (insn)) == CLOBBER) | |
15015 | return false; | |
15016 | ||
ec507f2d | 15017 | if (rs6000_sched_groups) |
cbe26ab8 DN |
15018 | { |
15019 | enum attr_type type = get_attr_type (insn); | |
15020 | if (type == TYPE_BRANCH || type == TYPE_JMPREG) | |
f676971a | 15021 | return true; |
cbe26ab8 DN |
15022 | return false; |
15023 | } | |
15024 | ||
15025 | return false; | |
15026 | } | |
79ae11c4 | 15027 | |
a4f6c312 | 15028 | /* A C statement (sans semicolon) to update the integer scheduling |
79ae11c4 DN |
15029 | priority INSN_PRIORITY (INSN). Increase the priority to execute the |
15030 | INSN earlier, reduce the priority to execute INSN later. Do not | |
a4f6c312 SS |
15031 | define this macro if you do not need to adjust the scheduling |
15032 | priorities of insns. */ | |
bef84347 | 15033 | |
c237e94a | 15034 | static int |
a2369ed3 | 15035 | rs6000_adjust_priority (rtx insn ATTRIBUTE_UNUSED, int priority) |
bef84347 | 15036 | { |
a4f6c312 SS |
15037 | /* On machines (like the 750) which have asymmetric integer units, |
15038 | where one integer unit can do multiply and divides and the other | |
15039 | can't, reduce the priority of multiply/divide so it is scheduled | |
15040 | before other integer operations. */ | |
bef84347 VM |
15041 | |
15042 | #if 0 | |
2c3c49de | 15043 | if (! INSN_P (insn)) |
bef84347 VM |
15044 | return priority; |
15045 | ||
15046 | if (GET_CODE (PATTERN (insn)) == USE) | |
15047 | return priority; | |
15048 | ||
15049 | switch (rs6000_cpu_attr) { | |
15050 | case CPU_PPC750: | |
15051 | switch (get_attr_type (insn)) | |
15052 | { | |
15053 | default: | |
15054 | break; | |
15055 | ||
15056 | case TYPE_IMUL: | |
15057 | case TYPE_IDIV: | |
3cb999d8 DE |
15058 | fprintf (stderr, "priority was %#x (%d) before adjustment\n", |
15059 | priority, priority); | |
bef84347 VM |
15060 | if (priority >= 0 && priority < 0x01000000) |
15061 | priority >>= 3; | |
15062 | break; | |
15063 | } | |
15064 | } | |
15065 | #endif | |
15066 | ||
79ae11c4 DN |
15067 | if (is_dispatch_slot_restricted (insn) |
15068 | && reload_completed | |
f676971a | 15069 | && current_sched_info->sched_max_insns_priority |
79ae11c4 DN |
15070 | && rs6000_sched_restricted_insns_priority) |
15071 | { | |
15072 | ||
c4ad648e AM |
15073 | /* Prioritize insns that can be dispatched only in the first |
15074 | dispatch slot. */ | |
79ae11c4 | 15075 | if (rs6000_sched_restricted_insns_priority == 1) |
f676971a EC |
15076 | /* Attach highest priority to insn. This means that in |
15077 | haifa-sched.c:ready_sort(), dispatch-slot restriction considerations | |
79ae11c4 | 15078 | precede 'priority' (critical path) considerations. */ |
f676971a | 15079 | return current_sched_info->sched_max_insns_priority; |
79ae11c4 | 15080 | else if (rs6000_sched_restricted_insns_priority == 2) |
f676971a | 15081 | /* Increase priority of insn by a minimal amount. This means that in |
c4ad648e AM |
15082 | haifa-sched.c:ready_sort(), only 'priority' (critical path) |
15083 | considerations precede dispatch-slot restriction considerations. */ | |
f676971a EC |
15084 | return (priority + 1); |
15085 | } | |
79ae11c4 | 15086 | |
bef84347 VM |
15087 | return priority; |
15088 | } | |
15089 | ||
a4f6c312 SS |
15090 | /* Return how many instructions the machine can issue per cycle. */ |
15091 | ||
c237e94a | 15092 | static int |
863d938c | 15093 | rs6000_issue_rate (void) |
b6c9286a | 15094 | { |
3317bab1 DE |
15095 | /* Use issue rate of 1 for first scheduling pass to decrease degradation. */ |
15096 | if (!reload_completed) | |
15097 | return 1; | |
15098 | ||
b6c9286a | 15099 | switch (rs6000_cpu_attr) { |
3cb999d8 DE |
15100 | case CPU_RIOS1: /* ? */ |
15101 | case CPU_RS64A: | |
15102 | case CPU_PPC601: /* ? */ | |
ed947a96 | 15103 | case CPU_PPC7450: |
3cb999d8 | 15104 | return 3; |
b54cf83a | 15105 | case CPU_PPC440: |
b6c9286a | 15106 | case CPU_PPC603: |
bef84347 | 15107 | case CPU_PPC750: |
ed947a96 | 15108 | case CPU_PPC7400: |
be12c2b0 | 15109 | case CPU_PPC8540: |
f676971a | 15110 | return 2; |
3cb999d8 | 15111 | case CPU_RIOS2: |
b6c9286a | 15112 | case CPU_PPC604: |
19684119 | 15113 | case CPU_PPC604E: |
b6c9286a | 15114 | case CPU_PPC620: |
3cb999d8 | 15115 | case CPU_PPC630: |
b6c9286a | 15116 | return 4; |
cbe26ab8 | 15117 | case CPU_POWER4: |
ec507f2d | 15118 | case CPU_POWER5: |
cbe26ab8 | 15119 | return 5; |
b6c9286a MM |
15120 | default: |
15121 | return 1; | |
15122 | } | |
15123 | } | |
15124 | ||
be12c2b0 VM |
15125 | /* Return how many instructions to look ahead for better insn |
15126 | scheduling. */ | |
15127 | ||
15128 | static int | |
863d938c | 15129 | rs6000_use_sched_lookahead (void) |
be12c2b0 VM |
15130 | { |
15131 | if (rs6000_cpu_attr == CPU_PPC8540) | |
15132 | return 4; | |
15133 | return 0; | |
15134 | } | |
15135 | ||
569fa502 DN |
15136 | /* Determine is PAT refers to memory. */ |
15137 | ||
15138 | static bool | |
15139 | is_mem_ref (rtx pat) | |
15140 | { | |
15141 | const char * fmt; | |
15142 | int i, j; | |
15143 | bool ret = false; | |
15144 | ||
15145 | if (GET_CODE (pat) == MEM) | |
15146 | return true; | |
15147 | ||
15148 | /* Recursively process the pattern. */ | |
15149 | fmt = GET_RTX_FORMAT (GET_CODE (pat)); | |
15150 | ||
15151 | for (i = GET_RTX_LENGTH (GET_CODE (pat)) - 1; i >= 0 && !ret; i--) | |
15152 | { | |
15153 | if (fmt[i] == 'e') | |
15154 | ret |= is_mem_ref (XEXP (pat, i)); | |
15155 | else if (fmt[i] == 'E') | |
15156 | for (j = XVECLEN (pat, i) - 1; j >= 0; j--) | |
15157 | ret |= is_mem_ref (XVECEXP (pat, i, j)); | |
15158 | } | |
15159 | ||
15160 | return ret; | |
15161 | } | |
15162 | ||
15163 | /* Determine if PAT is a PATTERN of a load insn. */ | |
f676971a | 15164 | |
569fa502 DN |
15165 | static bool |
15166 | is_load_insn1 (rtx pat) | |
15167 | { | |
15168 | if (!pat || pat == NULL_RTX) | |
15169 | return false; | |
15170 | ||
15171 | if (GET_CODE (pat) == SET) | |
15172 | return is_mem_ref (SET_SRC (pat)); | |
15173 | ||
15174 | if (GET_CODE (pat) == PARALLEL) | |
15175 | { | |
15176 | int i; | |
15177 | ||
15178 | for (i = 0; i < XVECLEN (pat, 0); i++) | |
15179 | if (is_load_insn1 (XVECEXP (pat, 0, i))) | |
15180 | return true; | |
15181 | } | |
15182 | ||
15183 | return false; | |
15184 | } | |
15185 | ||
15186 | /* Determine if INSN loads from memory. */ | |
15187 | ||
15188 | static bool | |
15189 | is_load_insn (rtx insn) | |
15190 | { | |
15191 | if (!insn || !INSN_P (insn)) | |
15192 | return false; | |
15193 | ||
15194 | if (GET_CODE (insn) == CALL_INSN) | |
15195 | return false; | |
15196 | ||
15197 | return is_load_insn1 (PATTERN (insn)); | |
15198 | } | |
15199 | ||
15200 | /* Determine if PAT is a PATTERN of a store insn. */ | |
15201 | ||
15202 | static bool | |
15203 | is_store_insn1 (rtx pat) | |
15204 | { | |
15205 | if (!pat || pat == NULL_RTX) | |
15206 | return false; | |
15207 | ||
15208 | if (GET_CODE (pat) == SET) | |
15209 | return is_mem_ref (SET_DEST (pat)); | |
15210 | ||
15211 | if (GET_CODE (pat) == PARALLEL) | |
15212 | { | |
15213 | int i; | |
15214 | ||
15215 | for (i = 0; i < XVECLEN (pat, 0); i++) | |
15216 | if (is_store_insn1 (XVECEXP (pat, 0, i))) | |
15217 | return true; | |
15218 | } | |
15219 | ||
15220 | return false; | |
15221 | } | |
15222 | ||
15223 | /* Determine if INSN stores to memory. */ | |
15224 | ||
15225 | static bool | |
15226 | is_store_insn (rtx insn) | |
15227 | { | |
15228 | if (!insn || !INSN_P (insn)) | |
15229 | return false; | |
15230 | ||
15231 | return is_store_insn1 (PATTERN (insn)); | |
15232 | } | |
15233 | ||
15234 | /* Returns whether the dependence between INSN and NEXT is considered | |
15235 | costly by the given target. */ | |
15236 | ||
15237 | static bool | |
c4ad648e AM |
15238 | rs6000_is_costly_dependence (rtx insn, rtx next, rtx link, int cost, |
15239 | int distance) | |
f676971a | 15240 | { |
569fa502 | 15241 | /* If the flag is not enbled - no dependence is considered costly; |
f676971a | 15242 | allow all dependent insns in the same group. |
569fa502 DN |
15243 | This is the most aggressive option. */ |
15244 | if (rs6000_sched_costly_dep == no_dep_costly) | |
15245 | return false; | |
15246 | ||
f676971a | 15247 | /* If the flag is set to 1 - a dependence is always considered costly; |
569fa502 DN |
15248 | do not allow dependent instructions in the same group. |
15249 | This is the most conservative option. */ | |
15250 | if (rs6000_sched_costly_dep == all_deps_costly) | |
f676971a | 15251 | return true; |
569fa502 | 15252 | |
f676971a EC |
15253 | if (rs6000_sched_costly_dep == store_to_load_dep_costly |
15254 | && is_load_insn (next) | |
569fa502 DN |
15255 | && is_store_insn (insn)) |
15256 | /* Prevent load after store in the same group. */ | |
15257 | return true; | |
15258 | ||
15259 | if (rs6000_sched_costly_dep == true_store_to_load_dep_costly | |
f676971a | 15260 | && is_load_insn (next) |
569fa502 DN |
15261 | && is_store_insn (insn) |
15262 | && (!link || (int) REG_NOTE_KIND (link) == 0)) | |
c4ad648e AM |
15263 | /* Prevent load after store in the same group if it is a true |
15264 | dependence. */ | |
569fa502 | 15265 | return true; |
f676971a EC |
15266 | |
15267 | /* The flag is set to X; dependences with latency >= X are considered costly, | |
569fa502 DN |
15268 | and will not be scheduled in the same group. */ |
15269 | if (rs6000_sched_costly_dep <= max_dep_latency | |
15270 | && ((cost - distance) >= (int)rs6000_sched_costly_dep)) | |
15271 | return true; | |
15272 | ||
15273 | return false; | |
15274 | } | |
15275 | ||
f676971a | 15276 | /* Return the next insn after INSN that is found before TAIL is reached, |
cbe26ab8 DN |
15277 | skipping any "non-active" insns - insns that will not actually occupy |
15278 | an issue slot. Return NULL_RTX if such an insn is not found. */ | |
15279 | ||
15280 | static rtx | |
15281 | get_next_active_insn (rtx insn, rtx tail) | |
15282 | { | |
15283 | rtx next_insn; | |
15284 | ||
15285 | if (!insn || insn == tail) | |
15286 | return NULL_RTX; | |
15287 | ||
15288 | next_insn = NEXT_INSN (insn); | |
15289 | ||
15290 | while (next_insn | |
15291 | && next_insn != tail | |
15292 | && (GET_CODE(next_insn) == NOTE | |
15293 | || GET_CODE (PATTERN (next_insn)) == USE | |
15294 | || GET_CODE (PATTERN (next_insn)) == CLOBBER)) | |
15295 | { | |
15296 | next_insn = NEXT_INSN (next_insn); | |
15297 | } | |
15298 | ||
15299 | if (!next_insn || next_insn == tail) | |
15300 | return NULL_RTX; | |
15301 | ||
15302 | return next_insn; | |
15303 | } | |
15304 | ||
839a4992 | 15305 | /* Return whether the presence of INSN causes a dispatch group termination |
cbe26ab8 DN |
15306 | of group WHICH_GROUP. |
15307 | ||
15308 | If WHICH_GROUP == current_group, this function will return true if INSN | |
15309 | causes the termination of the current group (i.e, the dispatch group to | |
15310 | which INSN belongs). This means that INSN will be the last insn in the | |
15311 | group it belongs to. | |
15312 | ||
15313 | If WHICH_GROUP == previous_group, this function will return true if INSN | |
15314 | causes the termination of the previous group (i.e, the dispatch group that | |
15315 | precedes the group to which INSN belongs). This means that INSN will be | |
15316 | the first insn in the group it belongs to). */ | |
15317 | ||
15318 | static bool | |
15319 | insn_terminates_group_p (rtx insn, enum group_termination which_group) | |
15320 | { | |
15321 | enum attr_type type; | |
15322 | ||
15323 | if (! insn) | |
15324 | return false; | |
569fa502 | 15325 | |
cbe26ab8 DN |
15326 | type = get_attr_type (insn); |
15327 | ||
15328 | if (is_microcoded_insn (insn)) | |
15329 | return true; | |
15330 | ||
15331 | if (which_group == current_group) | |
15332 | { | |
15333 | if (is_branch_slot_insn (insn)) | |
c4ad648e | 15334 | return true; |
cbe26ab8 DN |
15335 | return false; |
15336 | } | |
15337 | else if (which_group == previous_group) | |
15338 | { | |
15339 | if (is_dispatch_slot_restricted (insn)) | |
c4ad648e | 15340 | return true; |
cbe26ab8 DN |
15341 | return false; |
15342 | } | |
15343 | ||
15344 | return false; | |
15345 | } | |
15346 | ||
839a4992 | 15347 | /* Return true if it is recommended to keep NEXT_INSN "far" (in a separate |
cbe26ab8 DN |
15348 | dispatch group) from the insns in GROUP_INSNS. Return false otherwise. */ |
15349 | ||
15350 | static bool | |
15351 | is_costly_group (rtx *group_insns, rtx next_insn) | |
15352 | { | |
15353 | int i; | |
15354 | rtx link; | |
15355 | int cost; | |
15356 | int issue_rate = rs6000_issue_rate (); | |
15357 | ||
15358 | for (i = 0; i < issue_rate; i++) | |
15359 | { | |
15360 | rtx insn = group_insns[i]; | |
15361 | if (!insn) | |
c4ad648e | 15362 | continue; |
cbe26ab8 | 15363 | for (link = INSN_DEPEND (insn); link != 0; link = XEXP (link, 1)) |
c4ad648e AM |
15364 | { |
15365 | rtx next = XEXP (link, 0); | |
15366 | if (next == next_insn) | |
15367 | { | |
15368 | cost = insn_cost (insn, link, next_insn); | |
15369 | if (rs6000_is_costly_dependence (insn, next_insn, link, cost, 0)) | |
15370 | return true; | |
15371 | } | |
15372 | } | |
cbe26ab8 DN |
15373 | } |
15374 | ||
15375 | return false; | |
15376 | } | |
15377 | ||
f676971a | 15378 | /* Utility of the function redefine_groups. |
cbe26ab8 DN |
15379 | Check if it is too costly to schedule NEXT_INSN together with GROUP_INSNS |
15380 | in the same dispatch group. If so, insert nops before NEXT_INSN, in order | |
15381 | to keep it "far" (in a separate group) from GROUP_INSNS, following | |
15382 | one of the following schemes, depending on the value of the flag | |
15383 | -minsert_sched_nops = X: | |
15384 | (1) X == sched_finish_regroup_exact: insert exactly as many nops as needed | |
839a4992 | 15385 | in order to force NEXT_INSN into a separate group. |
f676971a EC |
15386 | (2) X < sched_finish_regroup_exact: insert exactly X nops. |
15387 | GROUP_END, CAN_ISSUE_MORE and GROUP_COUNT record the state after nop | |
cbe26ab8 DN |
15388 | insertion (has a group just ended, how many vacant issue slots remain in the |
15389 | last group, and how many dispatch groups were encountered so far). */ | |
15390 | ||
f676971a | 15391 | static int |
c4ad648e AM |
15392 | force_new_group (int sched_verbose, FILE *dump, rtx *group_insns, |
15393 | rtx next_insn, bool *group_end, int can_issue_more, | |
15394 | int *group_count) | |
cbe26ab8 DN |
15395 | { |
15396 | rtx nop; | |
15397 | bool force; | |
15398 | int issue_rate = rs6000_issue_rate (); | |
15399 | bool end = *group_end; | |
15400 | int i; | |
15401 | ||
15402 | if (next_insn == NULL_RTX) | |
15403 | return can_issue_more; | |
15404 | ||
15405 | if (rs6000_sched_insert_nops > sched_finish_regroup_exact) | |
15406 | return can_issue_more; | |
15407 | ||
15408 | force = is_costly_group (group_insns, next_insn); | |
15409 | if (!force) | |
15410 | return can_issue_more; | |
15411 | ||
15412 | if (sched_verbose > 6) | |
15413 | fprintf (dump,"force: group count = %d, can_issue_more = %d\n", | |
c4ad648e | 15414 | *group_count ,can_issue_more); |
cbe26ab8 DN |
15415 | |
15416 | if (rs6000_sched_insert_nops == sched_finish_regroup_exact) | |
15417 | { | |
15418 | if (*group_end) | |
c4ad648e | 15419 | can_issue_more = 0; |
cbe26ab8 DN |
15420 | |
15421 | /* Since only a branch can be issued in the last issue_slot, it is | |
15422 | sufficient to insert 'can_issue_more - 1' nops if next_insn is not | |
15423 | a branch. If next_insn is a branch, we insert 'can_issue_more' nops; | |
c4ad648e AM |
15424 | in this case the last nop will start a new group and the branch |
15425 | will be forced to the new group. */ | |
cbe26ab8 | 15426 | if (can_issue_more && !is_branch_slot_insn (next_insn)) |
c4ad648e | 15427 | can_issue_more--; |
cbe26ab8 DN |
15428 | |
15429 | while (can_issue_more > 0) | |
c4ad648e AM |
15430 | { |
15431 | nop = gen_nop(); | |
15432 | emit_insn_before (nop, next_insn); | |
15433 | can_issue_more--; | |
15434 | } | |
cbe26ab8 DN |
15435 | |
15436 | *group_end = true; | |
15437 | return 0; | |
f676971a | 15438 | } |
cbe26ab8 DN |
15439 | |
15440 | if (rs6000_sched_insert_nops < sched_finish_regroup_exact) | |
15441 | { | |
15442 | int n_nops = rs6000_sched_insert_nops; | |
15443 | ||
f676971a | 15444 | /* Nops can't be issued from the branch slot, so the effective |
c4ad648e | 15445 | issue_rate for nops is 'issue_rate - 1'. */ |
cbe26ab8 | 15446 | if (can_issue_more == 0) |
c4ad648e | 15447 | can_issue_more = issue_rate; |
cbe26ab8 DN |
15448 | can_issue_more--; |
15449 | if (can_issue_more == 0) | |
c4ad648e AM |
15450 | { |
15451 | can_issue_more = issue_rate - 1; | |
15452 | (*group_count)++; | |
15453 | end = true; | |
15454 | for (i = 0; i < issue_rate; i++) | |
15455 | { | |
15456 | group_insns[i] = 0; | |
15457 | } | |
15458 | } | |
cbe26ab8 DN |
15459 | |
15460 | while (n_nops > 0) | |
c4ad648e AM |
15461 | { |
15462 | nop = gen_nop (); | |
15463 | emit_insn_before (nop, next_insn); | |
15464 | if (can_issue_more == issue_rate - 1) /* new group begins */ | |
15465 | end = false; | |
15466 | can_issue_more--; | |
15467 | if (can_issue_more == 0) | |
15468 | { | |
15469 | can_issue_more = issue_rate - 1; | |
15470 | (*group_count)++; | |
15471 | end = true; | |
15472 | for (i = 0; i < issue_rate; i++) | |
15473 | { | |
15474 | group_insns[i] = 0; | |
15475 | } | |
15476 | } | |
15477 | n_nops--; | |
15478 | } | |
cbe26ab8 DN |
15479 | |
15480 | /* Scale back relative to 'issue_rate' (instead of 'issue_rate - 1'). */ | |
f676971a | 15481 | can_issue_more++; |
cbe26ab8 | 15482 | |
c4ad648e AM |
15483 | /* Is next_insn going to start a new group? */ |
15484 | *group_end | |
15485 | = (end | |
cbe26ab8 DN |
15486 | || (can_issue_more == 1 && !is_branch_slot_insn (next_insn)) |
15487 | || (can_issue_more <= 2 && is_cracked_insn (next_insn)) | |
15488 | || (can_issue_more < issue_rate && | |
c4ad648e | 15489 | insn_terminates_group_p (next_insn, previous_group))); |
cbe26ab8 | 15490 | if (*group_end && end) |
c4ad648e | 15491 | (*group_count)--; |
cbe26ab8 DN |
15492 | |
15493 | if (sched_verbose > 6) | |
c4ad648e AM |
15494 | fprintf (dump, "done force: group count = %d, can_issue_more = %d\n", |
15495 | *group_count, can_issue_more); | |
f676971a EC |
15496 | return can_issue_more; |
15497 | } | |
cbe26ab8 DN |
15498 | |
15499 | return can_issue_more; | |
15500 | } | |
15501 | ||
15502 | /* This function tries to synch the dispatch groups that the compiler "sees" | |
f676971a | 15503 | with the dispatch groups that the processor dispatcher is expected to |
cbe26ab8 DN |
15504 | form in practice. It tries to achieve this synchronization by forcing the |
15505 | estimated processor grouping on the compiler (as opposed to the function | |
15506 | 'pad_goups' which tries to force the scheduler's grouping on the processor). | |
15507 | ||
15508 | The function scans the insn sequence between PREV_HEAD_INSN and TAIL and | |
15509 | examines the (estimated) dispatch groups that will be formed by the processor | |
15510 | dispatcher. It marks these group boundaries to reflect the estimated | |
15511 | processor grouping, overriding the grouping that the scheduler had marked. | |
15512 | Depending on the value of the flag '-minsert-sched-nops' this function can | |
15513 | force certain insns into separate groups or force a certain distance between | |
15514 | them by inserting nops, for example, if there exists a "costly dependence" | |
15515 | between the insns. | |
15516 | ||
15517 | The function estimates the group boundaries that the processor will form as | |
15518 | folllows: It keeps track of how many vacant issue slots are available after | |
15519 | each insn. A subsequent insn will start a new group if one of the following | |
15520 | 4 cases applies: | |
15521 | - no more vacant issue slots remain in the current dispatch group. | |
15522 | - only the last issue slot, which is the branch slot, is vacant, but the next | |
15523 | insn is not a branch. | |
15524 | - only the last 2 or less issue slots, including the branch slot, are vacant, | |
15525 | which means that a cracked insn (which occupies two issue slots) can't be | |
15526 | issued in this group. | |
f676971a | 15527 | - less than 'issue_rate' slots are vacant, and the next insn always needs to |
cbe26ab8 DN |
15528 | start a new group. */ |
15529 | ||
15530 | static int | |
15531 | redefine_groups (FILE *dump, int sched_verbose, rtx prev_head_insn, rtx tail) | |
15532 | { | |
15533 | rtx insn, next_insn; | |
15534 | int issue_rate; | |
15535 | int can_issue_more; | |
15536 | int slot, i; | |
15537 | bool group_end; | |
15538 | int group_count = 0; | |
15539 | rtx *group_insns; | |
15540 | ||
15541 | /* Initialize. */ | |
15542 | issue_rate = rs6000_issue_rate (); | |
15543 | group_insns = alloca (issue_rate * sizeof (rtx)); | |
f676971a | 15544 | for (i = 0; i < issue_rate; i++) |
cbe26ab8 DN |
15545 | { |
15546 | group_insns[i] = 0; | |
15547 | } | |
15548 | can_issue_more = issue_rate; | |
15549 | slot = 0; | |
15550 | insn = get_next_active_insn (prev_head_insn, tail); | |
15551 | group_end = false; | |
15552 | ||
15553 | while (insn != NULL_RTX) | |
15554 | { | |
15555 | slot = (issue_rate - can_issue_more); | |
15556 | group_insns[slot] = insn; | |
15557 | can_issue_more = | |
c4ad648e | 15558 | rs6000_variable_issue (dump, sched_verbose, insn, can_issue_more); |
cbe26ab8 | 15559 | if (insn_terminates_group_p (insn, current_group)) |
c4ad648e | 15560 | can_issue_more = 0; |
cbe26ab8 DN |
15561 | |
15562 | next_insn = get_next_active_insn (insn, tail); | |
15563 | if (next_insn == NULL_RTX) | |
c4ad648e | 15564 | return group_count + 1; |
cbe26ab8 | 15565 | |
c4ad648e AM |
15566 | /* Is next_insn going to start a new group? */ |
15567 | group_end | |
15568 | = (can_issue_more == 0 | |
15569 | || (can_issue_more == 1 && !is_branch_slot_insn (next_insn)) | |
15570 | || (can_issue_more <= 2 && is_cracked_insn (next_insn)) | |
15571 | || (can_issue_more < issue_rate && | |
15572 | insn_terminates_group_p (next_insn, previous_group))); | |
cbe26ab8 | 15573 | |
f676971a | 15574 | can_issue_more = force_new_group (sched_verbose, dump, group_insns, |
c4ad648e AM |
15575 | next_insn, &group_end, can_issue_more, |
15576 | &group_count); | |
cbe26ab8 DN |
15577 | |
15578 | if (group_end) | |
c4ad648e AM |
15579 | { |
15580 | group_count++; | |
15581 | can_issue_more = 0; | |
15582 | for (i = 0; i < issue_rate; i++) | |
15583 | { | |
15584 | group_insns[i] = 0; | |
15585 | } | |
15586 | } | |
cbe26ab8 DN |
15587 | |
15588 | if (GET_MODE (next_insn) == TImode && can_issue_more) | |
c4ad648e | 15589 | PUT_MODE(next_insn, VOIDmode); |
cbe26ab8 | 15590 | else if (!can_issue_more && GET_MODE (next_insn) != TImode) |
c4ad648e | 15591 | PUT_MODE (next_insn, TImode); |
cbe26ab8 DN |
15592 | |
15593 | insn = next_insn; | |
15594 | if (can_issue_more == 0) | |
c4ad648e AM |
15595 | can_issue_more = issue_rate; |
15596 | } /* while */ | |
cbe26ab8 DN |
15597 | |
15598 | return group_count; | |
15599 | } | |
15600 | ||
15601 | /* Scan the insn sequence between PREV_HEAD_INSN and TAIL and examine the | |
15602 | dispatch group boundaries that the scheduler had marked. Pad with nops | |
15603 | any dispatch groups which have vacant issue slots, in order to force the | |
15604 | scheduler's grouping on the processor dispatcher. The function | |
15605 | returns the number of dispatch groups found. */ | |
15606 | ||
15607 | static int | |
15608 | pad_groups (FILE *dump, int sched_verbose, rtx prev_head_insn, rtx tail) | |
15609 | { | |
15610 | rtx insn, next_insn; | |
15611 | rtx nop; | |
15612 | int issue_rate; | |
15613 | int can_issue_more; | |
15614 | int group_end; | |
15615 | int group_count = 0; | |
15616 | ||
15617 | /* Initialize issue_rate. */ | |
15618 | issue_rate = rs6000_issue_rate (); | |
15619 | can_issue_more = issue_rate; | |
15620 | ||
15621 | insn = get_next_active_insn (prev_head_insn, tail); | |
15622 | next_insn = get_next_active_insn (insn, tail); | |
15623 | ||
15624 | while (insn != NULL_RTX) | |
15625 | { | |
15626 | can_issue_more = | |
15627 | rs6000_variable_issue (dump, sched_verbose, insn, can_issue_more); | |
15628 | ||
15629 | group_end = (next_insn == NULL_RTX || GET_MODE (next_insn) == TImode); | |
15630 | ||
15631 | if (next_insn == NULL_RTX) | |
c4ad648e | 15632 | break; |
cbe26ab8 DN |
15633 | |
15634 | if (group_end) | |
c4ad648e AM |
15635 | { |
15636 | /* If the scheduler had marked group termination at this location | |
15637 | (between insn and next_indn), and neither insn nor next_insn will | |
15638 | force group termination, pad the group with nops to force group | |
15639 | termination. */ | |
15640 | if (can_issue_more | |
15641 | && (rs6000_sched_insert_nops == sched_finish_pad_groups) | |
15642 | && !insn_terminates_group_p (insn, current_group) | |
15643 | && !insn_terminates_group_p (next_insn, previous_group)) | |
15644 | { | |
15645 | if (!is_branch_slot_insn(next_insn)) | |
15646 | can_issue_more--; | |
15647 | ||
15648 | while (can_issue_more) | |
15649 | { | |
15650 | nop = gen_nop (); | |
15651 | emit_insn_before (nop, next_insn); | |
15652 | can_issue_more--; | |
15653 | } | |
15654 | } | |
15655 | ||
15656 | can_issue_more = issue_rate; | |
15657 | group_count++; | |
15658 | } | |
cbe26ab8 DN |
15659 | |
15660 | insn = next_insn; | |
15661 | next_insn = get_next_active_insn (insn, tail); | |
15662 | } | |
15663 | ||
15664 | return group_count; | |
15665 | } | |
15666 | ||
15667 | /* The following function is called at the end of scheduling BB. | |
15668 | After reload, it inserts nops at insn group bundling. */ | |
15669 | ||
15670 | static void | |
38f391a5 | 15671 | rs6000_sched_finish (FILE *dump, int sched_verbose) |
cbe26ab8 DN |
15672 | { |
15673 | int n_groups; | |
15674 | ||
15675 | if (sched_verbose) | |
15676 | fprintf (dump, "=== Finishing schedule.\n"); | |
15677 | ||
ec507f2d | 15678 | if (reload_completed && rs6000_sched_groups) |
cbe26ab8 DN |
15679 | { |
15680 | if (rs6000_sched_insert_nops == sched_finish_none) | |
c4ad648e | 15681 | return; |
cbe26ab8 DN |
15682 | |
15683 | if (rs6000_sched_insert_nops == sched_finish_pad_groups) | |
c4ad648e AM |
15684 | n_groups = pad_groups (dump, sched_verbose, |
15685 | current_sched_info->prev_head, | |
15686 | current_sched_info->next_tail); | |
cbe26ab8 | 15687 | else |
c4ad648e AM |
15688 | n_groups = redefine_groups (dump, sched_verbose, |
15689 | current_sched_info->prev_head, | |
15690 | current_sched_info->next_tail); | |
cbe26ab8 DN |
15691 | |
15692 | if (sched_verbose >= 6) | |
15693 | { | |
15694 | fprintf (dump, "ngroups = %d\n", n_groups); | |
15695 | print_rtl (dump, current_sched_info->prev_head); | |
15696 | fprintf (dump, "Done finish_sched\n"); | |
15697 | } | |
15698 | } | |
15699 | } | |
b6c9286a | 15700 | \f |
b6c9286a MM |
15701 | /* Length in units of the trampoline for entering a nested function. */ |
15702 | ||
15703 | int | |
863d938c | 15704 | rs6000_trampoline_size (void) |
b6c9286a MM |
15705 | { |
15706 | int ret = 0; | |
15707 | ||
15708 | switch (DEFAULT_ABI) | |
15709 | { | |
15710 | default: | |
15711 | abort (); | |
15712 | ||
15713 | case ABI_AIX: | |
8f802bfb | 15714 | ret = (TARGET_32BIT) ? 12 : 24; |
b6c9286a MM |
15715 | break; |
15716 | ||
4dabc42d | 15717 | case ABI_DARWIN: |
b6c9286a | 15718 | case ABI_V4: |
03a7e1a5 | 15719 | ret = (TARGET_32BIT) ? 40 : 48; |
b6c9286a | 15720 | break; |
b6c9286a MM |
15721 | } |
15722 | ||
15723 | return ret; | |
15724 | } | |
15725 | ||
15726 | /* Emit RTL insns to initialize the variable parts of a trampoline. | |
15727 | FNADDR is an RTX for the address of the function's pure code. | |
15728 | CXT is an RTX for the static chain value for the function. */ | |
15729 | ||
15730 | void | |
a2369ed3 | 15731 | rs6000_initialize_trampoline (rtx addr, rtx fnaddr, rtx cxt) |
b6c9286a | 15732 | { |
ac2a93a1 | 15733 | enum machine_mode pmode = Pmode; |
8bd04c56 MM |
15734 | int regsize = (TARGET_32BIT) ? 4 : 8; |
15735 | rtx ctx_reg = force_reg (pmode, cxt); | |
b6c9286a MM |
15736 | |
15737 | switch (DEFAULT_ABI) | |
15738 | { | |
15739 | default: | |
15740 | abort (); | |
15741 | ||
8bd04c56 | 15742 | /* Macros to shorten the code expansions below. */ |
39403d82 | 15743 | #define MEM_DEREF(addr) gen_rtx_MEM (pmode, memory_address (pmode, addr)) |
c5c76735 JL |
15744 | #define MEM_PLUS(addr,offset) \ |
15745 | gen_rtx_MEM (pmode, memory_address (pmode, plus_constant (addr, offset))) | |
7c59dc5d | 15746 | |
b6c9286a MM |
15747 | /* Under AIX, just build the 3 word function descriptor */ |
15748 | case ABI_AIX: | |
8bd04c56 MM |
15749 | { |
15750 | rtx fn_reg = gen_reg_rtx (pmode); | |
15751 | rtx toc_reg = gen_reg_rtx (pmode); | |
15752 | emit_move_insn (fn_reg, MEM_DEREF (fnaddr)); | |
1cb18e3c | 15753 | emit_move_insn (toc_reg, MEM_PLUS (fnaddr, regsize)); |
8bd04c56 MM |
15754 | emit_move_insn (MEM_DEREF (addr), fn_reg); |
15755 | emit_move_insn (MEM_PLUS (addr, regsize), toc_reg); | |
15756 | emit_move_insn (MEM_PLUS (addr, 2*regsize), ctx_reg); | |
15757 | } | |
b6c9286a MM |
15758 | break; |
15759 | ||
4dabc42d TC |
15760 | /* Under V.4/eabi/darwin, __trampoline_setup does the real work. */ |
15761 | case ABI_DARWIN: | |
b6c9286a | 15762 | case ABI_V4: |
39403d82 | 15763 | emit_library_call (gen_rtx_SYMBOL_REF (SImode, "__trampoline_setup"), |
eaf1bcf1 MM |
15764 | FALSE, VOIDmode, 4, |
15765 | addr, pmode, | |
15766 | GEN_INT (rs6000_trampoline_size ()), SImode, | |
15767 | fnaddr, pmode, | |
15768 | ctx_reg, pmode); | |
b6c9286a | 15769 | break; |
b6c9286a MM |
15770 | } |
15771 | ||
15772 | return; | |
15773 | } | |
7509c759 MM |
15774 | |
15775 | \f | |
91d231cb | 15776 | /* Table of valid machine attributes. */ |
a4f6c312 | 15777 | |
91d231cb | 15778 | const struct attribute_spec rs6000_attribute_table[] = |
7509c759 | 15779 | { |
91d231cb | 15780 | /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */ |
8bb418a3 | 15781 | { "altivec", 1, 1, false, true, false, rs6000_handle_altivec_attribute }, |
a5c76ee6 ZW |
15782 | { "longcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute }, |
15783 | { "shortcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute }, | |
005c1a13 GK |
15784 | #ifdef SUBTARGET_ATTRIBUTE_TABLE |
15785 | SUBTARGET_ATTRIBUTE_TABLE, | |
15786 | #endif | |
a5c76ee6 | 15787 | { NULL, 0, 0, false, false, false, NULL } |
91d231cb | 15788 | }; |
7509c759 | 15789 | |
8bb418a3 ZL |
15790 | /* Handle the "altivec" attribute. The attribute may have |
15791 | arguments as follows: | |
f676971a | 15792 | |
8bb418a3 ZL |
15793 | __attribute__((altivec(vector__))) |
15794 | __attribute__((altivec(pixel__))) (always followed by 'unsigned short') | |
15795 | __attribute__((altivec(bool__))) (always followed by 'unsigned') | |
15796 | ||
15797 | and may appear more than once (e.g., 'vector bool char') in a | |
15798 | given declaration. */ | |
15799 | ||
15800 | static tree | |
f90ac3f0 UP |
15801 | rs6000_handle_altivec_attribute (tree *node, |
15802 | tree name ATTRIBUTE_UNUSED, | |
15803 | tree args, | |
8bb418a3 ZL |
15804 | int flags ATTRIBUTE_UNUSED, |
15805 | bool *no_add_attrs) | |
15806 | { | |
15807 | tree type = *node, result = NULL_TREE; | |
15808 | enum machine_mode mode; | |
15809 | int unsigned_p; | |
15810 | char altivec_type | |
15811 | = ((args && TREE_CODE (args) == TREE_LIST && TREE_VALUE (args) | |
15812 | && TREE_CODE (TREE_VALUE (args)) == IDENTIFIER_NODE) | |
15813 | ? *IDENTIFIER_POINTER (TREE_VALUE (args)) | |
f676971a | 15814 | : '?'); |
8bb418a3 ZL |
15815 | |
15816 | while (POINTER_TYPE_P (type) | |
15817 | || TREE_CODE (type) == FUNCTION_TYPE | |
15818 | || TREE_CODE (type) == METHOD_TYPE | |
15819 | || TREE_CODE (type) == ARRAY_TYPE) | |
15820 | type = TREE_TYPE (type); | |
15821 | ||
15822 | mode = TYPE_MODE (type); | |
15823 | ||
f90ac3f0 UP |
15824 | /* Check for invalid AltiVec type qualifiers. */ |
15825 | if (type == long_unsigned_type_node || type == long_integer_type_node) | |
15826 | { | |
15827 | if (TARGET_64BIT) | |
15828 | error ("use of %<long%> in AltiVec types is invalid for 64-bit code"); | |
15829 | else if (rs6000_warn_altivec_long) | |
15830 | warning ("use of %<long%> in AltiVec types is deprecated; use %<int%>"); | |
15831 | } | |
15832 | else if (type == long_long_unsigned_type_node | |
15833 | || type == long_long_integer_type_node) | |
15834 | error ("use of %<long long%> in AltiVec types is invalid"); | |
15835 | else if (type == double_type_node) | |
15836 | error ("use of %<double%> in AltiVec types is invalid"); | |
15837 | else if (type == long_double_type_node) | |
15838 | error ("use of %<long double%> in AltiVec types is invalid"); | |
15839 | else if (type == boolean_type_node) | |
15840 | error ("use of boolean types in AltiVec types is invalid"); | |
15841 | else if (TREE_CODE (type) == COMPLEX_TYPE) | |
15842 | error ("use of %<complex%> in AltiVec types is invalid"); | |
8bb418a3 ZL |
15843 | |
15844 | switch (altivec_type) | |
15845 | { | |
15846 | case 'v': | |
8df83eae | 15847 | unsigned_p = TYPE_UNSIGNED (type); |
8bb418a3 ZL |
15848 | switch (mode) |
15849 | { | |
c4ad648e AM |
15850 | case SImode: |
15851 | result = (unsigned_p ? unsigned_V4SI_type_node : V4SI_type_node); | |
15852 | break; | |
15853 | case HImode: | |
15854 | result = (unsigned_p ? unsigned_V8HI_type_node : V8HI_type_node); | |
15855 | break; | |
15856 | case QImode: | |
15857 | result = (unsigned_p ? unsigned_V16QI_type_node : V16QI_type_node); | |
15858 | break; | |
15859 | case SFmode: result = V4SF_type_node; break; | |
15860 | /* If the user says 'vector int bool', we may be handed the 'bool' | |
15861 | attribute _before_ the 'vector' attribute, and so select the | |
15862 | proper type in the 'b' case below. */ | |
15863 | case V4SImode: case V8HImode: case V16QImode: case V4SFmode: | |
15864 | result = type; | |
15865 | default: break; | |
8bb418a3 ZL |
15866 | } |
15867 | break; | |
15868 | case 'b': | |
15869 | switch (mode) | |
15870 | { | |
c4ad648e AM |
15871 | case SImode: case V4SImode: result = bool_V4SI_type_node; break; |
15872 | case HImode: case V8HImode: result = bool_V8HI_type_node; break; | |
15873 | case QImode: case V16QImode: result = bool_V16QI_type_node; | |
15874 | default: break; | |
8bb418a3 ZL |
15875 | } |
15876 | break; | |
15877 | case 'p': | |
15878 | switch (mode) | |
15879 | { | |
c4ad648e AM |
15880 | case V8HImode: result = pixel_V8HI_type_node; |
15881 | default: break; | |
8bb418a3 ZL |
15882 | } |
15883 | default: break; | |
15884 | } | |
15885 | ||
7958a2a6 FJ |
15886 | if (result && result != type && TYPE_READONLY (type)) |
15887 | result = build_qualified_type (result, TYPE_QUAL_CONST); | |
15888 | ||
8bb418a3 ZL |
15889 | *no_add_attrs = true; /* No need to hang on to the attribute. */ |
15890 | ||
f90ac3f0 | 15891 | if (result) |
8bb418a3 ZL |
15892 | *node = reconstruct_complex_type (*node, result); |
15893 | ||
15894 | return NULL_TREE; | |
15895 | } | |
15896 | ||
f18eca82 ZL |
15897 | /* AltiVec defines four built-in scalar types that serve as vector |
15898 | elements; we must teach the compiler how to mangle them. */ | |
15899 | ||
15900 | static const char * | |
15901 | rs6000_mangle_fundamental_type (tree type) | |
15902 | { | |
15903 | if (type == bool_char_type_node) return "U6__boolc"; | |
15904 | if (type == bool_short_type_node) return "U6__bools"; | |
15905 | if (type == pixel_type_node) return "u7__pixel"; | |
15906 | if (type == bool_int_type_node) return "U6__booli"; | |
15907 | ||
15908 | /* For all other types, use normal C++ mangling. */ | |
15909 | return NULL; | |
15910 | } | |
15911 | ||
a5c76ee6 ZW |
15912 | /* Handle a "longcall" or "shortcall" attribute; arguments as in |
15913 | struct attribute_spec.handler. */ | |
a4f6c312 | 15914 | |
91d231cb | 15915 | static tree |
f676971a EC |
15916 | rs6000_handle_longcall_attribute (tree *node, tree name, |
15917 | tree args ATTRIBUTE_UNUSED, | |
15918 | int flags ATTRIBUTE_UNUSED, | |
a2369ed3 | 15919 | bool *no_add_attrs) |
91d231cb JM |
15920 | { |
15921 | if (TREE_CODE (*node) != FUNCTION_TYPE | |
15922 | && TREE_CODE (*node) != FIELD_DECL | |
15923 | && TREE_CODE (*node) != TYPE_DECL) | |
15924 | { | |
9e637a26 | 15925 | warning ("%qs attribute only applies to functions", |
91d231cb JM |
15926 | IDENTIFIER_POINTER (name)); |
15927 | *no_add_attrs = true; | |
15928 | } | |
6a4cee5f | 15929 | |
91d231cb | 15930 | return NULL_TREE; |
7509c759 MM |
15931 | } |
15932 | ||
a5c76ee6 ZW |
15933 | /* Set longcall attributes on all functions declared when |
15934 | rs6000_default_long_calls is true. */ | |
15935 | static void | |
a2369ed3 | 15936 | rs6000_set_default_type_attributes (tree type) |
a5c76ee6 ZW |
15937 | { |
15938 | if (rs6000_default_long_calls | |
15939 | && (TREE_CODE (type) == FUNCTION_TYPE | |
15940 | || TREE_CODE (type) == METHOD_TYPE)) | |
15941 | TYPE_ATTRIBUTES (type) = tree_cons (get_identifier ("longcall"), | |
15942 | NULL_TREE, | |
15943 | TYPE_ATTRIBUTES (type)); | |
15944 | } | |
15945 | ||
3cb999d8 DE |
15946 | /* Return a reference suitable for calling a function with the |
15947 | longcall attribute. */ | |
a4f6c312 | 15948 | |
6a4cee5f | 15949 | struct rtx_def * |
a2369ed3 | 15950 | rs6000_longcall_ref (rtx call_ref) |
6a4cee5f | 15951 | { |
d330fd93 | 15952 | const char *call_name; |
6a4cee5f MM |
15953 | tree node; |
15954 | ||
15955 | if (GET_CODE (call_ref) != SYMBOL_REF) | |
15956 | return call_ref; | |
15957 | ||
15958 | /* System V adds '.' to the internal name, so skip them. */ | |
15959 | call_name = XSTR (call_ref, 0); | |
15960 | if (*call_name == '.') | |
15961 | { | |
15962 | while (*call_name == '.') | |
15963 | call_name++; | |
15964 | ||
15965 | node = get_identifier (call_name); | |
39403d82 | 15966 | call_ref = gen_rtx_SYMBOL_REF (VOIDmode, IDENTIFIER_POINTER (node)); |
6a4cee5f MM |
15967 | } |
15968 | ||
15969 | return force_reg (Pmode, call_ref); | |
15970 | } | |
7509c759 | 15971 | \f |
b64a1b53 RH |
15972 | #ifdef USING_ELFOS_H |
15973 | ||
7509c759 MM |
15974 | /* A C statement or statements to switch to the appropriate section |
15975 | for output of RTX in mode MODE. You can assume that RTX is some | |
15976 | kind of constant in RTL. The argument MODE is redundant except in | |
15977 | the case of a `const_int' rtx. Select the section by calling | |
15978 | `text_section' or one of the alternatives for other sections. | |
15979 | ||
15980 | Do not define this macro if you put all constants in the read-only | |
15981 | data section. */ | |
15982 | ||
b64a1b53 | 15983 | static void |
f676971a | 15984 | rs6000_elf_select_rtx_section (enum machine_mode mode, rtx x, |
a2369ed3 | 15985 | unsigned HOST_WIDE_INT align) |
7509c759 | 15986 | { |
a9098fd0 | 15987 | if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode)) |
7509c759 | 15988 | toc_section (); |
7509c759 | 15989 | else |
b64a1b53 | 15990 | default_elf_select_rtx_section (mode, x, align); |
7509c759 MM |
15991 | } |
15992 | ||
15993 | /* A C statement or statements to switch to the appropriate | |
15994 | section for output of DECL. DECL is either a `VAR_DECL' node | |
15995 | or a constant of some sort. RELOC indicates whether forming | |
15996 | the initial value of DECL requires link-time relocations. */ | |
15997 | ||
ae46c4e0 | 15998 | static void |
f676971a | 15999 | rs6000_elf_select_section (tree decl, int reloc, |
a2369ed3 | 16000 | unsigned HOST_WIDE_INT align) |
7509c759 | 16001 | { |
f1384257 AM |
16002 | /* Pretend that we're always building for a shared library when |
16003 | ABI_AIX, because otherwise we end up with dynamic relocations | |
16004 | in read-only sections. This happens for function pointers, | |
16005 | references to vtables in typeinfo, and probably other cases. */ | |
0e5dbd9b DE |
16006 | default_elf_select_section_1 (decl, reloc, align, |
16007 | flag_pic || DEFAULT_ABI == ABI_AIX); | |
63019373 GK |
16008 | } |
16009 | ||
16010 | /* A C statement to build up a unique section name, expressed as a | |
16011 | STRING_CST node, and assign it to DECL_SECTION_NAME (decl). | |
16012 | RELOC indicates whether the initial value of EXP requires | |
16013 | link-time relocations. If you do not define this macro, GCC will use | |
16014 | the symbol name prefixed by `.' as the section name. Note - this | |
f5143c46 | 16015 | macro can now be called for uninitialized data items as well as |
4912a07c | 16016 | initialized data and functions. */ |
63019373 | 16017 | |
ae46c4e0 | 16018 | static void |
a2369ed3 | 16019 | rs6000_elf_unique_section (tree decl, int reloc) |
63019373 | 16020 | { |
f1384257 AM |
16021 | /* As above, pretend that we're always building for a shared library |
16022 | when ABI_AIX, to avoid dynamic relocations in read-only sections. */ | |
0e5dbd9b DE |
16023 | default_unique_section_1 (decl, reloc, |
16024 | flag_pic || DEFAULT_ABI == ABI_AIX); | |
7509c759 | 16025 | } |
d9407988 | 16026 | \f |
d1908feb JJ |
16027 | /* For a SYMBOL_REF, set generic flags and then perform some |
16028 | target-specific processing. | |
16029 | ||
d1908feb JJ |
16030 | When the AIX ABI is requested on a non-AIX system, replace the |
16031 | function name with the real name (with a leading .) rather than the | |
16032 | function descriptor name. This saves a lot of overriding code to | |
16033 | read the prefixes. */ | |
d9407988 | 16034 | |
fb49053f | 16035 | static void |
a2369ed3 | 16036 | rs6000_elf_encode_section_info (tree decl, rtx rtl, int first) |
d9407988 | 16037 | { |
d1908feb | 16038 | default_encode_section_info (decl, rtl, first); |
b2003250 | 16039 | |
d1908feb JJ |
16040 | if (first |
16041 | && TREE_CODE (decl) == FUNCTION_DECL | |
16042 | && !TARGET_AIX | |
16043 | && DEFAULT_ABI == ABI_AIX) | |
d9407988 | 16044 | { |
c6a2438a | 16045 | rtx sym_ref = XEXP (rtl, 0); |
d1908feb JJ |
16046 | size_t len = strlen (XSTR (sym_ref, 0)); |
16047 | char *str = alloca (len + 2); | |
16048 | str[0] = '.'; | |
16049 | memcpy (str + 1, XSTR (sym_ref, 0), len + 1); | |
16050 | XSTR (sym_ref, 0) = ggc_alloc_string (str, len + 1); | |
d9407988 | 16051 | } |
d9407988 MM |
16052 | } |
16053 | ||
0e5dbd9b | 16054 | static bool |
a2369ed3 | 16055 | rs6000_elf_in_small_data_p (tree decl) |
0e5dbd9b DE |
16056 | { |
16057 | if (rs6000_sdata == SDATA_NONE) | |
16058 | return false; | |
16059 | ||
7482ad25 AF |
16060 | /* We want to merge strings, so we never consider them small data. */ |
16061 | if (TREE_CODE (decl) == STRING_CST) | |
16062 | return false; | |
16063 | ||
16064 | /* Functions are never in the small data area. */ | |
16065 | if (TREE_CODE (decl) == FUNCTION_DECL) | |
16066 | return false; | |
16067 | ||
0e5dbd9b DE |
16068 | if (TREE_CODE (decl) == VAR_DECL && DECL_SECTION_NAME (decl)) |
16069 | { | |
16070 | const char *section = TREE_STRING_POINTER (DECL_SECTION_NAME (decl)); | |
16071 | if (strcmp (section, ".sdata") == 0 | |
16072 | || strcmp (section, ".sdata2") == 0 | |
20bfcd69 GK |
16073 | || strcmp (section, ".sbss") == 0 |
16074 | || strcmp (section, ".sbss2") == 0 | |
16075 | || strcmp (section, ".PPC.EMB.sdata0") == 0 | |
16076 | || strcmp (section, ".PPC.EMB.sbss0") == 0) | |
0e5dbd9b DE |
16077 | return true; |
16078 | } | |
16079 | else | |
16080 | { | |
16081 | HOST_WIDE_INT size = int_size_in_bytes (TREE_TYPE (decl)); | |
16082 | ||
16083 | if (size > 0 | |
307b599c | 16084 | && (unsigned HOST_WIDE_INT) size <= g_switch_value |
20bfcd69 GK |
16085 | /* If it's not public, and we're not going to reference it there, |
16086 | there's no need to put it in the small data section. */ | |
0e5dbd9b DE |
16087 | && (rs6000_sdata != SDATA_DATA || TREE_PUBLIC (decl))) |
16088 | return true; | |
16089 | } | |
16090 | ||
16091 | return false; | |
16092 | } | |
16093 | ||
b91da81f | 16094 | #endif /* USING_ELFOS_H */ |
000034eb | 16095 | |
a6c2a102 | 16096 | \f |
000034eb | 16097 | /* Return a REG that occurs in ADDR with coefficient 1. |
02441cd6 JL |
16098 | ADDR can be effectively incremented by incrementing REG. |
16099 | ||
16100 | r0 is special and we must not select it as an address | |
16101 | register by this routine since our caller will try to | |
16102 | increment the returned register via an "la" instruction. */ | |
000034eb DE |
16103 | |
16104 | struct rtx_def * | |
a2369ed3 | 16105 | find_addr_reg (rtx addr) |
000034eb DE |
16106 | { |
16107 | while (GET_CODE (addr) == PLUS) | |
16108 | { | |
02441cd6 JL |
16109 | if (GET_CODE (XEXP (addr, 0)) == REG |
16110 | && REGNO (XEXP (addr, 0)) != 0) | |
000034eb | 16111 | addr = XEXP (addr, 0); |
02441cd6 JL |
16112 | else if (GET_CODE (XEXP (addr, 1)) == REG |
16113 | && REGNO (XEXP (addr, 1)) != 0) | |
000034eb DE |
16114 | addr = XEXP (addr, 1); |
16115 | else if (CONSTANT_P (XEXP (addr, 0))) | |
16116 | addr = XEXP (addr, 1); | |
16117 | else if (CONSTANT_P (XEXP (addr, 1))) | |
16118 | addr = XEXP (addr, 0); | |
16119 | else | |
16120 | abort (); | |
16121 | } | |
02441cd6 | 16122 | if (GET_CODE (addr) == REG && REGNO (addr) != 0) |
000034eb DE |
16123 | return addr; |
16124 | abort (); | |
16125 | } | |
16126 | ||
a6c2a102 | 16127 | void |
a2369ed3 | 16128 | rs6000_fatal_bad_address (rtx op) |
a6c2a102 DE |
16129 | { |
16130 | fatal_insn ("bad address", op); | |
16131 | } | |
c8023011 | 16132 | |
ee890fe2 SS |
16133 | #if TARGET_MACHO |
16134 | ||
efdba735 | 16135 | static tree branch_island_list = 0; |
ee890fe2 | 16136 | |
efdba735 SH |
16137 | /* Remember to generate a branch island for far calls to the given |
16138 | function. */ | |
ee890fe2 | 16139 | |
f676971a | 16140 | static void |
c4ad648e AM |
16141 | add_compiler_branch_island (tree label_name, tree function_name, |
16142 | int line_number) | |
ee890fe2 | 16143 | { |
efdba735 | 16144 | tree branch_island = build_tree_list (function_name, label_name); |
7d60be94 | 16145 | TREE_TYPE (branch_island) = build_int_cst (NULL_TREE, line_number); |
efdba735 SH |
16146 | TREE_CHAIN (branch_island) = branch_island_list; |
16147 | branch_island_list = branch_island; | |
ee890fe2 SS |
16148 | } |
16149 | ||
efdba735 SH |
16150 | #define BRANCH_ISLAND_LABEL_NAME(BRANCH_ISLAND) TREE_VALUE (BRANCH_ISLAND) |
16151 | #define BRANCH_ISLAND_FUNCTION_NAME(BRANCH_ISLAND) TREE_PURPOSE (BRANCH_ISLAND) | |
16152 | #define BRANCH_ISLAND_LINE_NUMBER(BRANCH_ISLAND) \ | |
16153 | TREE_INT_CST_LOW (TREE_TYPE (BRANCH_ISLAND)) | |
ee890fe2 | 16154 | |
efdba735 SH |
16155 | /* Generate far-jump branch islands for everything on the |
16156 | branch_island_list. Invoked immediately after the last instruction | |
16157 | of the epilogue has been emitted; the branch-islands must be | |
16158 | appended to, and contiguous with, the function body. Mach-O stubs | |
16159 | are generated in machopic_output_stub(). */ | |
ee890fe2 | 16160 | |
efdba735 SH |
16161 | static void |
16162 | macho_branch_islands (void) | |
16163 | { | |
16164 | char tmp_buf[512]; | |
16165 | tree branch_island; | |
16166 | ||
16167 | for (branch_island = branch_island_list; | |
16168 | branch_island; | |
16169 | branch_island = TREE_CHAIN (branch_island)) | |
16170 | { | |
16171 | const char *label = | |
16172 | IDENTIFIER_POINTER (BRANCH_ISLAND_LABEL_NAME (branch_island)); | |
16173 | const char *name = | |
11abc112 | 16174 | IDENTIFIER_POINTER (BRANCH_ISLAND_FUNCTION_NAME (branch_island)); |
efdba735 SH |
16175 | char name_buf[512]; |
16176 | /* Cheap copy of the details from the Darwin ASM_OUTPUT_LABELREF(). */ | |
16177 | if (name[0] == '*' || name[0] == '&') | |
16178 | strcpy (name_buf, name+1); | |
16179 | else | |
16180 | { | |
16181 | name_buf[0] = '_'; | |
16182 | strcpy (name_buf+1, name); | |
16183 | } | |
16184 | strcpy (tmp_buf, "\n"); | |
16185 | strcat (tmp_buf, label); | |
ee890fe2 | 16186 | #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO) |
efdba735 | 16187 | if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG) |
93a27b7b | 16188 | dbxout_stabd (N_SLINE, BRANCH_ISLAND_LINE_NUMBER (branch_island)); |
ee890fe2 | 16189 | #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */ |
efdba735 SH |
16190 | if (flag_pic) |
16191 | { | |
16192 | strcat (tmp_buf, ":\n\tmflr r0\n\tbcl 20,31,"); | |
16193 | strcat (tmp_buf, label); | |
16194 | strcat (tmp_buf, "_pic\n"); | |
16195 | strcat (tmp_buf, label); | |
16196 | strcat (tmp_buf, "_pic:\n\tmflr r11\n"); | |
f676971a | 16197 | |
efdba735 SH |
16198 | strcat (tmp_buf, "\taddis r11,r11,ha16("); |
16199 | strcat (tmp_buf, name_buf); | |
16200 | strcat (tmp_buf, " - "); | |
16201 | strcat (tmp_buf, label); | |
16202 | strcat (tmp_buf, "_pic)\n"); | |
f676971a | 16203 | |
efdba735 | 16204 | strcat (tmp_buf, "\tmtlr r0\n"); |
f676971a | 16205 | |
efdba735 SH |
16206 | strcat (tmp_buf, "\taddi r12,r11,lo16("); |
16207 | strcat (tmp_buf, name_buf); | |
16208 | strcat (tmp_buf, " - "); | |
16209 | strcat (tmp_buf, label); | |
16210 | strcat (tmp_buf, "_pic)\n"); | |
f676971a | 16211 | |
efdba735 SH |
16212 | strcat (tmp_buf, "\tmtctr r12\n\tbctr\n"); |
16213 | } | |
16214 | else | |
16215 | { | |
16216 | strcat (tmp_buf, ":\nlis r12,hi16("); | |
16217 | strcat (tmp_buf, name_buf); | |
16218 | strcat (tmp_buf, ")\n\tori r12,r12,lo16("); | |
16219 | strcat (tmp_buf, name_buf); | |
16220 | strcat (tmp_buf, ")\n\tmtctr r12\n\tbctr"); | |
16221 | } | |
16222 | output_asm_insn (tmp_buf, 0); | |
ee890fe2 | 16223 | #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO) |
efdba735 | 16224 | if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG) |
93a27b7b | 16225 | dbxout_stabd (N_SLINE, BRANCH_ISLAND_LINE_NUMBER (branch_island)); |
ee890fe2 | 16226 | #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */ |
efdba735 | 16227 | } |
ee890fe2 | 16228 | |
efdba735 | 16229 | branch_island_list = 0; |
ee890fe2 SS |
16230 | } |
16231 | ||
16232 | /* NO_PREVIOUS_DEF checks in the link list whether the function name is | |
16233 | already there or not. */ | |
16234 | ||
efdba735 | 16235 | static int |
a2369ed3 | 16236 | no_previous_def (tree function_name) |
ee890fe2 | 16237 | { |
efdba735 SH |
16238 | tree branch_island; |
16239 | for (branch_island = branch_island_list; | |
16240 | branch_island; | |
16241 | branch_island = TREE_CHAIN (branch_island)) | |
16242 | if (function_name == BRANCH_ISLAND_FUNCTION_NAME (branch_island)) | |
ee890fe2 SS |
16243 | return 0; |
16244 | return 1; | |
16245 | } | |
16246 | ||
16247 | /* GET_PREV_LABEL gets the label name from the previous definition of | |
16248 | the function. */ | |
16249 | ||
efdba735 | 16250 | static tree |
a2369ed3 | 16251 | get_prev_label (tree function_name) |
ee890fe2 | 16252 | { |
efdba735 SH |
16253 | tree branch_island; |
16254 | for (branch_island = branch_island_list; | |
16255 | branch_island; | |
16256 | branch_island = TREE_CHAIN (branch_island)) | |
16257 | if (function_name == BRANCH_ISLAND_FUNCTION_NAME (branch_island)) | |
16258 | return BRANCH_ISLAND_LABEL_NAME (branch_island); | |
ee890fe2 SS |
16259 | return 0; |
16260 | } | |
16261 | ||
16262 | /* INSN is either a function call or a millicode call. It may have an | |
f676971a | 16263 | unconditional jump in its delay slot. |
ee890fe2 SS |
16264 | |
16265 | CALL_DEST is the routine we are calling. */ | |
16266 | ||
16267 | char * | |
c4ad648e AM |
16268 | output_call (rtx insn, rtx *operands, int dest_operand_number, |
16269 | int cookie_operand_number) | |
ee890fe2 SS |
16270 | { |
16271 | static char buf[256]; | |
efdba735 SH |
16272 | if (GET_CODE (operands[dest_operand_number]) == SYMBOL_REF |
16273 | && (INTVAL (operands[cookie_operand_number]) & CALL_LONG)) | |
ee890fe2 SS |
16274 | { |
16275 | tree labelname; | |
efdba735 | 16276 | tree funname = get_identifier (XSTR (operands[dest_operand_number], 0)); |
f676971a | 16277 | |
ee890fe2 SS |
16278 | if (no_previous_def (funname)) |
16279 | { | |
308c142a | 16280 | int line_number = 0; |
ee890fe2 SS |
16281 | rtx label_rtx = gen_label_rtx (); |
16282 | char *label_buf, temp_buf[256]; | |
16283 | ASM_GENERATE_INTERNAL_LABEL (temp_buf, "L", | |
16284 | CODE_LABEL_NUMBER (label_rtx)); | |
16285 | label_buf = temp_buf[0] == '*' ? temp_buf + 1 : temp_buf; | |
16286 | labelname = get_identifier (label_buf); | |
16287 | for (; insn && GET_CODE (insn) != NOTE; insn = PREV_INSN (insn)); | |
16288 | if (insn) | |
16289 | line_number = NOTE_LINE_NUMBER (insn); | |
efdba735 | 16290 | add_compiler_branch_island (labelname, funname, line_number); |
ee890fe2 SS |
16291 | } |
16292 | else | |
16293 | labelname = get_prev_label (funname); | |
16294 | ||
efdba735 SH |
16295 | /* "jbsr foo, L42" is Mach-O for "Link as 'bl foo' if a 'bl' |
16296 | instruction will reach 'foo', otherwise link as 'bl L42'". | |
16297 | "L42" should be a 'branch island', that will do a far jump to | |
16298 | 'foo'. Branch islands are generated in | |
16299 | macho_branch_islands(). */ | |
ee890fe2 | 16300 | sprintf (buf, "jbsr %%z%d,%.246s", |
efdba735 | 16301 | dest_operand_number, IDENTIFIER_POINTER (labelname)); |
ee890fe2 SS |
16302 | } |
16303 | else | |
efdba735 SH |
16304 | sprintf (buf, "bl %%z%d", dest_operand_number); |
16305 | return buf; | |
ee890fe2 SS |
16306 | } |
16307 | ||
ee890fe2 SS |
16308 | /* Generate PIC and indirect symbol stubs. */ |
16309 | ||
16310 | void | |
a2369ed3 | 16311 | machopic_output_stub (FILE *file, const char *symb, const char *stub) |
ee890fe2 SS |
16312 | { |
16313 | unsigned int length; | |
a4f6c312 SS |
16314 | char *symbol_name, *lazy_ptr_name; |
16315 | char *local_label_0; | |
ee890fe2 SS |
16316 | static int label = 0; |
16317 | ||
df56a27f | 16318 | /* Lose our funky encoding stuff so it doesn't contaminate the stub. */ |
772c5265 | 16319 | symb = (*targetm.strip_name_encoding) (symb); |
df56a27f | 16320 | |
ee890fe2 | 16321 | |
ee890fe2 SS |
16322 | length = strlen (symb); |
16323 | symbol_name = alloca (length + 32); | |
16324 | GEN_SYMBOL_NAME_FOR_SYMBOL (symbol_name, symb, length); | |
16325 | ||
16326 | lazy_ptr_name = alloca (length + 32); | |
16327 | GEN_LAZY_PTR_NAME_FOR_SYMBOL (lazy_ptr_name, symb, length); | |
16328 | ||
ee890fe2 | 16329 | if (flag_pic == 2) |
d3c300d2 | 16330 | machopic_picsymbol_stub1_section (); |
ee890fe2 | 16331 | else |
d3c300d2 | 16332 | machopic_symbol_stub1_section (); |
ee890fe2 SS |
16333 | |
16334 | if (flag_pic == 2) | |
16335 | { | |
d974312d DJ |
16336 | fprintf (file, "\t.align 5\n"); |
16337 | ||
16338 | fprintf (file, "%s:\n", stub); | |
16339 | fprintf (file, "\t.indirect_symbol %s\n", symbol_name); | |
16340 | ||
876455fa AP |
16341 | label++; |
16342 | local_label_0 = alloca (sizeof("\"L0000000000$spb\"")); | |
16343 | sprintf (local_label_0, "\"L%011d$spb\"", label); | |
f676971a | 16344 | |
ee890fe2 SS |
16345 | fprintf (file, "\tmflr r0\n"); |
16346 | fprintf (file, "\tbcl 20,31,%s\n", local_label_0); | |
16347 | fprintf (file, "%s:\n\tmflr r11\n", local_label_0); | |
16348 | fprintf (file, "\taddis r11,r11,ha16(%s-%s)\n", | |
16349 | lazy_ptr_name, local_label_0); | |
16350 | fprintf (file, "\tmtlr r0\n"); | |
3d0e2d58 SS |
16351 | fprintf (file, "\t%s r12,lo16(%s-%s)(r11)\n", |
16352 | (TARGET_64BIT ? "ldu" : "lwzu"), | |
ee890fe2 SS |
16353 | lazy_ptr_name, local_label_0); |
16354 | fprintf (file, "\tmtctr r12\n"); | |
ee890fe2 SS |
16355 | fprintf (file, "\tbctr\n"); |
16356 | } | |
16357 | else | |
d974312d DJ |
16358 | { |
16359 | fprintf (file, "\t.align 4\n"); | |
16360 | ||
16361 | fprintf (file, "%s:\n", stub); | |
16362 | fprintf (file, "\t.indirect_symbol %s\n", symbol_name); | |
16363 | ||
16364 | fprintf (file, "\tlis r11,ha16(%s)\n", lazy_ptr_name); | |
d9e4e4f5 SS |
16365 | fprintf (file, "\t%s r12,lo16(%s)(r11)\n", |
16366 | (TARGET_64BIT ? "ldu" : "lwzu"), | |
16367 | lazy_ptr_name); | |
d974312d DJ |
16368 | fprintf (file, "\tmtctr r12\n"); |
16369 | fprintf (file, "\tbctr\n"); | |
16370 | } | |
f676971a | 16371 | |
ee890fe2 SS |
16372 | machopic_lazy_symbol_ptr_section (); |
16373 | fprintf (file, "%s:\n", lazy_ptr_name); | |
16374 | fprintf (file, "\t.indirect_symbol %s\n", symbol_name); | |
49bd1d27 SS |
16375 | fprintf (file, "%sdyld_stub_binding_helper\n", |
16376 | (TARGET_64BIT ? DOUBLE_INT_ASM_OP : "\t.long\t")); | |
ee890fe2 SS |
16377 | } |
16378 | ||
16379 | /* Legitimize PIC addresses. If the address is already | |
16380 | position-independent, we return ORIG. Newly generated | |
16381 | position-independent addresses go into a reg. This is REG if non | |
16382 | zero, otherwise we allocate register(s) as necessary. */ | |
16383 | ||
c859cda6 | 16384 | #define SMALL_INT(X) ((unsigned) (INTVAL(X) + 0x8000) < 0x10000) |
ee890fe2 SS |
16385 | |
16386 | rtx | |
f676971a | 16387 | rs6000_machopic_legitimize_pic_address (rtx orig, enum machine_mode mode, |
a2369ed3 | 16388 | rtx reg) |
ee890fe2 SS |
16389 | { |
16390 | rtx base, offset; | |
16391 | ||
16392 | if (reg == NULL && ! reload_in_progress && ! reload_completed) | |
16393 | reg = gen_reg_rtx (Pmode); | |
16394 | ||
16395 | if (GET_CODE (orig) == CONST) | |
16396 | { | |
16397 | if (GET_CODE (XEXP (orig, 0)) == PLUS | |
16398 | && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx) | |
16399 | return orig; | |
16400 | ||
16401 | if (GET_CODE (XEXP (orig, 0)) == PLUS) | |
16402 | { | |
2cf520bf | 16403 | /* Use a different reg for the intermediate value, as |
a3c9585f | 16404 | it will be marked UNCHANGING. */ |
2cf520bf GK |
16405 | rtx reg_temp = no_new_pseudos ? reg : gen_reg_rtx (Pmode); |
16406 | ||
a4f6c312 SS |
16407 | base = |
16408 | rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 0), | |
2cf520bf | 16409 | Pmode, reg_temp); |
a4f6c312 SS |
16410 | offset = |
16411 | rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 1), | |
16412 | Pmode, reg); | |
ee890fe2 SS |
16413 | } |
16414 | else | |
16415 | abort (); | |
16416 | ||
16417 | if (GET_CODE (offset) == CONST_INT) | |
16418 | { | |
16419 | if (SMALL_INT (offset)) | |
ed8908e7 | 16420 | return plus_constant (base, INTVAL (offset)); |
ee890fe2 SS |
16421 | else if (! reload_in_progress && ! reload_completed) |
16422 | offset = force_reg (Pmode, offset); | |
16423 | else | |
c859cda6 DJ |
16424 | { |
16425 | rtx mem = force_const_mem (Pmode, orig); | |
16426 | return machopic_legitimize_pic_address (mem, Pmode, reg); | |
16427 | } | |
ee890fe2 | 16428 | } |
f1c25d3b | 16429 | return gen_rtx_PLUS (Pmode, base, offset); |
ee890fe2 SS |
16430 | } |
16431 | ||
16432 | /* Fall back on generic machopic code. */ | |
16433 | return machopic_legitimize_pic_address (orig, mode, reg); | |
16434 | } | |
16435 | ||
16436 | /* This is just a placeholder to make linking work without having to | |
16437 | add this to the generic Darwin EXTRA_SECTIONS. If -mcall-aix is | |
16438 | ever needed for Darwin (not too likely!) this would have to get a | |
16439 | real definition. */ | |
16440 | ||
16441 | void | |
863d938c | 16442 | toc_section (void) |
ee890fe2 SS |
16443 | { |
16444 | } | |
16445 | ||
c4e18b1c GK |
16446 | /* Output a .machine directive for the Darwin assembler, and call |
16447 | the generic start_file routine. */ | |
16448 | ||
16449 | static void | |
16450 | rs6000_darwin_file_start (void) | |
16451 | { | |
94ff898d | 16452 | static const struct |
c4e18b1c GK |
16453 | { |
16454 | const char *arg; | |
16455 | const char *name; | |
16456 | int if_set; | |
16457 | } mapping[] = { | |
55dbfb48 | 16458 | { "ppc64", "ppc64", MASK_64BIT }, |
c4e18b1c GK |
16459 | { "970", "ppc970", MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64 }, |
16460 | { "power4", "ppc970", 0 }, | |
16461 | { "G5", "ppc970", 0 }, | |
16462 | { "7450", "ppc7450", 0 }, | |
16463 | { "7400", "ppc7400", MASK_ALTIVEC }, | |
16464 | { "G4", "ppc7400", 0 }, | |
16465 | { "750", "ppc750", 0 }, | |
16466 | { "740", "ppc750", 0 }, | |
16467 | { "G3", "ppc750", 0 }, | |
16468 | { "604e", "ppc604e", 0 }, | |
16469 | { "604", "ppc604", 0 }, | |
16470 | { "603e", "ppc603", 0 }, | |
16471 | { "603", "ppc603", 0 }, | |
16472 | { "601", "ppc601", 0 }, | |
16473 | { NULL, "ppc", 0 } }; | |
16474 | const char *cpu_id = ""; | |
16475 | size_t i; | |
94ff898d | 16476 | |
c4e18b1c GK |
16477 | rs6000_file_start(); |
16478 | ||
16479 | /* Determine the argument to -mcpu=. Default to G3 if not specified. */ | |
16480 | for (i = 0; i < ARRAY_SIZE (rs6000_select); i++) | |
16481 | if (rs6000_select[i].set_arch_p && rs6000_select[i].string | |
16482 | && rs6000_select[i].string[0] != '\0') | |
16483 | cpu_id = rs6000_select[i].string; | |
16484 | ||
16485 | /* Look through the mapping array. Pick the first name that either | |
16486 | matches the argument, has a bit set in IF_SET that is also set | |
16487 | in the target flags, or has a NULL name. */ | |
16488 | ||
16489 | i = 0; | |
16490 | while (mapping[i].arg != NULL | |
16491 | && strcmp (mapping[i].arg, cpu_id) != 0 | |
16492 | && (mapping[i].if_set & target_flags) == 0) | |
16493 | i++; | |
16494 | ||
16495 | fprintf (asm_out_file, "\t.machine %s\n", mapping[i].name); | |
16496 | } | |
16497 | ||
ee890fe2 | 16498 | #endif /* TARGET_MACHO */ |
7c262518 RH |
16499 | |
16500 | #if TARGET_ELF | |
16501 | static unsigned int | |
a2369ed3 | 16502 | rs6000_elf_section_type_flags (tree decl, const char *name, int reloc) |
7c262518 | 16503 | { |
1ff8f81a AM |
16504 | return default_section_type_flags_1 (decl, name, reloc, |
16505 | flag_pic || DEFAULT_ABI == ABI_AIX); | |
7c262518 | 16506 | } |
d9f6800d RH |
16507 | |
16508 | /* Record an element in the table of global constructors. SYMBOL is | |
16509 | a SYMBOL_REF of the function to be called; PRIORITY is a number | |
16510 | between 0 and MAX_INIT_PRIORITY. | |
16511 | ||
16512 | This differs from default_named_section_asm_out_constructor in | |
16513 | that we have special handling for -mrelocatable. */ | |
16514 | ||
16515 | static void | |
a2369ed3 | 16516 | rs6000_elf_asm_out_constructor (rtx symbol, int priority) |
d9f6800d RH |
16517 | { |
16518 | const char *section = ".ctors"; | |
16519 | char buf[16]; | |
16520 | ||
16521 | if (priority != DEFAULT_INIT_PRIORITY) | |
16522 | { | |
16523 | sprintf (buf, ".ctors.%.5u", | |
c4ad648e AM |
16524 | /* Invert the numbering so the linker puts us in the proper |
16525 | order; constructors are run from right to left, and the | |
16526 | linker sorts in increasing order. */ | |
16527 | MAX_INIT_PRIORITY - priority); | |
d9f6800d RH |
16528 | section = buf; |
16529 | } | |
16530 | ||
715bdd29 RH |
16531 | named_section_flags (section, SECTION_WRITE); |
16532 | assemble_align (POINTER_SIZE); | |
d9f6800d RH |
16533 | |
16534 | if (TARGET_RELOCATABLE) | |
16535 | { | |
16536 | fputs ("\t.long (", asm_out_file); | |
16537 | output_addr_const (asm_out_file, symbol); | |
16538 | fputs (")@fixup\n", asm_out_file); | |
16539 | } | |
16540 | else | |
c8af3574 | 16541 | assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1); |
d9f6800d RH |
16542 | } |
16543 | ||
16544 | static void | |
a2369ed3 | 16545 | rs6000_elf_asm_out_destructor (rtx symbol, int priority) |
d9f6800d RH |
16546 | { |
16547 | const char *section = ".dtors"; | |
16548 | char buf[16]; | |
16549 | ||
16550 | if (priority != DEFAULT_INIT_PRIORITY) | |
16551 | { | |
16552 | sprintf (buf, ".dtors.%.5u", | |
c4ad648e AM |
16553 | /* Invert the numbering so the linker puts us in the proper |
16554 | order; constructors are run from right to left, and the | |
16555 | linker sorts in increasing order. */ | |
16556 | MAX_INIT_PRIORITY - priority); | |
d9f6800d RH |
16557 | section = buf; |
16558 | } | |
16559 | ||
715bdd29 RH |
16560 | named_section_flags (section, SECTION_WRITE); |
16561 | assemble_align (POINTER_SIZE); | |
d9f6800d RH |
16562 | |
16563 | if (TARGET_RELOCATABLE) | |
16564 | { | |
16565 | fputs ("\t.long (", asm_out_file); | |
16566 | output_addr_const (asm_out_file, symbol); | |
16567 | fputs (")@fixup\n", asm_out_file); | |
16568 | } | |
16569 | else | |
c8af3574 | 16570 | assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1); |
d9f6800d | 16571 | } |
9739c90c JJ |
16572 | |
16573 | void | |
a2369ed3 | 16574 | rs6000_elf_declare_function_name (FILE *file, const char *name, tree decl) |
9739c90c JJ |
16575 | { |
16576 | if (TARGET_64BIT) | |
16577 | { | |
16578 | fputs ("\t.section\t\".opd\",\"aw\"\n\t.align 3\n", file); | |
16579 | ASM_OUTPUT_LABEL (file, name); | |
16580 | fputs (DOUBLE_INT_ASM_OP, file); | |
85b776df AM |
16581 | rs6000_output_function_entry (file, name); |
16582 | fputs (",.TOC.@tocbase,0\n\t.previous\n", file); | |
16583 | if (DOT_SYMBOLS) | |
9739c90c | 16584 | { |
85b776df | 16585 | fputs ("\t.size\t", file); |
9739c90c | 16586 | assemble_name (file, name); |
85b776df AM |
16587 | fputs (",24\n\t.type\t.", file); |
16588 | assemble_name (file, name); | |
16589 | fputs (",@function\n", file); | |
16590 | if (TREE_PUBLIC (decl) && ! DECL_WEAK (decl)) | |
16591 | { | |
16592 | fputs ("\t.globl\t.", file); | |
16593 | assemble_name (file, name); | |
16594 | putc ('\n', file); | |
16595 | } | |
9739c90c | 16596 | } |
85b776df AM |
16597 | else |
16598 | ASM_OUTPUT_TYPE_DIRECTIVE (file, name, "function"); | |
9739c90c | 16599 | ASM_DECLARE_RESULT (file, DECL_RESULT (decl)); |
85b776df AM |
16600 | rs6000_output_function_entry (file, name); |
16601 | fputs (":\n", file); | |
9739c90c JJ |
16602 | return; |
16603 | } | |
16604 | ||
16605 | if (TARGET_RELOCATABLE | |
16606 | && (get_pool_size () != 0 || current_function_profile) | |
3c9eb5f4 | 16607 | && uses_TOC ()) |
9739c90c JJ |
16608 | { |
16609 | char buf[256]; | |
16610 | ||
16611 | (*targetm.asm_out.internal_label) (file, "LCL", rs6000_pic_labelno); | |
16612 | ||
16613 | ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1); | |
16614 | fprintf (file, "\t.long "); | |
16615 | assemble_name (file, buf); | |
16616 | putc ('-', file); | |
16617 | ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno); | |
16618 | assemble_name (file, buf); | |
16619 | putc ('\n', file); | |
16620 | } | |
16621 | ||
16622 | ASM_OUTPUT_TYPE_DIRECTIVE (file, name, "function"); | |
16623 | ASM_DECLARE_RESULT (file, DECL_RESULT (decl)); | |
16624 | ||
16625 | if (DEFAULT_ABI == ABI_AIX) | |
16626 | { | |
16627 | const char *desc_name, *orig_name; | |
16628 | ||
16629 | orig_name = (*targetm.strip_name_encoding) (name); | |
16630 | desc_name = orig_name; | |
16631 | while (*desc_name == '.') | |
16632 | desc_name++; | |
16633 | ||
16634 | if (TREE_PUBLIC (decl)) | |
16635 | fprintf (file, "\t.globl %s\n", desc_name); | |
16636 | ||
16637 | fprintf (file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP); | |
16638 | fprintf (file, "%s:\n", desc_name); | |
16639 | fprintf (file, "\t.long %s\n", orig_name); | |
16640 | fputs ("\t.long _GLOBAL_OFFSET_TABLE_\n", file); | |
16641 | if (DEFAULT_ABI == ABI_AIX) | |
16642 | fputs ("\t.long 0\n", file); | |
16643 | fprintf (file, "\t.previous\n"); | |
16644 | } | |
16645 | ASM_OUTPUT_LABEL (file, name); | |
16646 | } | |
7c262518 RH |
16647 | #endif |
16648 | ||
cbaaba19 | 16649 | #if TARGET_XCOFF |
7c262518 | 16650 | static void |
a2369ed3 | 16651 | rs6000_xcoff_asm_globalize_label (FILE *stream, const char *name) |
b275d088 DE |
16652 | { |
16653 | fputs (GLOBAL_ASM_OP, stream); | |
16654 | RS6000_OUTPUT_BASENAME (stream, name); | |
16655 | putc ('\n', stream); | |
16656 | } | |
16657 | ||
16658 | static void | |
c18a5b6c MM |
16659 | rs6000_xcoff_asm_named_section (const char *name, unsigned int flags, |
16660 | tree decl ATTRIBUTE_UNUSED) | |
7c262518 | 16661 | { |
0e5dbd9b DE |
16662 | int smclass; |
16663 | static const char * const suffix[3] = { "PR", "RO", "RW" }; | |
16664 | ||
16665 | if (flags & SECTION_CODE) | |
16666 | smclass = 0; | |
16667 | else if (flags & SECTION_WRITE) | |
16668 | smclass = 2; | |
16669 | else | |
16670 | smclass = 1; | |
16671 | ||
5b5198f7 | 16672 | fprintf (asm_out_file, "\t.csect %s%s[%s],%u\n", |
0e5dbd9b | 16673 | (flags & SECTION_CODE) ? "." : "", |
5b5198f7 | 16674 | name, suffix[smclass], flags & SECTION_ENTSIZE); |
7c262518 | 16675 | } |
ae46c4e0 RH |
16676 | |
16677 | static void | |
f676971a | 16678 | rs6000_xcoff_select_section (tree decl, int reloc, |
c4ad648e | 16679 | unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED) |
ae46c4e0 | 16680 | { |
5add3202 | 16681 | if (decl_readonly_section_1 (decl, reloc, 1)) |
ae46c4e0 | 16682 | { |
0e5dbd9b | 16683 | if (TREE_PUBLIC (decl)) |
c4ad648e | 16684 | read_only_data_section (); |
ae46c4e0 | 16685 | else |
c4ad648e | 16686 | read_only_private_data_section (); |
ae46c4e0 RH |
16687 | } |
16688 | else | |
16689 | { | |
0e5dbd9b | 16690 | if (TREE_PUBLIC (decl)) |
c4ad648e | 16691 | data_section (); |
ae46c4e0 | 16692 | else |
c4ad648e | 16693 | private_data_section (); |
ae46c4e0 RH |
16694 | } |
16695 | } | |
16696 | ||
16697 | static void | |
a2369ed3 | 16698 | rs6000_xcoff_unique_section (tree decl, int reloc ATTRIBUTE_UNUSED) |
ae46c4e0 RH |
16699 | { |
16700 | const char *name; | |
ae46c4e0 | 16701 | |
5b5198f7 DE |
16702 | /* Use select_section for private and uninitialized data. */ |
16703 | if (!TREE_PUBLIC (decl) | |
16704 | || DECL_COMMON (decl) | |
0e5dbd9b DE |
16705 | || DECL_INITIAL (decl) == NULL_TREE |
16706 | || DECL_INITIAL (decl) == error_mark_node | |
16707 | || (flag_zero_initialized_in_bss | |
16708 | && initializer_zerop (DECL_INITIAL (decl)))) | |
16709 | return; | |
16710 | ||
16711 | name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl)); | |
16712 | name = (*targetm.strip_name_encoding) (name); | |
16713 | DECL_SECTION_NAME (decl) = build_string (strlen (name), name); | |
ae46c4e0 | 16714 | } |
b64a1b53 | 16715 | |
fb49053f RH |
16716 | /* Select section for constant in constant pool. |
16717 | ||
16718 | On RS/6000, all constants are in the private read-only data area. | |
16719 | However, if this is being placed in the TOC it must be output as a | |
16720 | toc entry. */ | |
16721 | ||
b64a1b53 | 16722 | static void |
f676971a | 16723 | rs6000_xcoff_select_rtx_section (enum machine_mode mode, rtx x, |
c4ad648e | 16724 | unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED) |
b64a1b53 RH |
16725 | { |
16726 | if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode)) | |
16727 | toc_section (); | |
16728 | else | |
16729 | read_only_private_data_section (); | |
16730 | } | |
772c5265 RH |
16731 | |
16732 | /* Remove any trailing [DS] or the like from the symbol name. */ | |
16733 | ||
16734 | static const char * | |
a2369ed3 | 16735 | rs6000_xcoff_strip_name_encoding (const char *name) |
772c5265 RH |
16736 | { |
16737 | size_t len; | |
16738 | if (*name == '*') | |
16739 | name++; | |
16740 | len = strlen (name); | |
16741 | if (name[len - 1] == ']') | |
16742 | return ggc_alloc_string (name, len - 4); | |
16743 | else | |
16744 | return name; | |
16745 | } | |
16746 | ||
5add3202 DE |
16747 | /* Section attributes. AIX is always PIC. */ |
16748 | ||
16749 | static unsigned int | |
a2369ed3 | 16750 | rs6000_xcoff_section_type_flags (tree decl, const char *name, int reloc) |
5add3202 | 16751 | { |
5b5198f7 DE |
16752 | unsigned int align; |
16753 | unsigned int flags = default_section_type_flags_1 (decl, name, reloc, 1); | |
16754 | ||
16755 | /* Align to at least UNIT size. */ | |
16756 | if (flags & SECTION_CODE) | |
16757 | align = MIN_UNITS_PER_WORD; | |
16758 | else | |
16759 | /* Increase alignment of large objects if not already stricter. */ | |
16760 | align = MAX ((DECL_ALIGN (decl) / BITS_PER_UNIT), | |
16761 | int_size_in_bytes (TREE_TYPE (decl)) > MIN_UNITS_PER_WORD | |
16762 | ? UNITS_PER_FP_WORD : MIN_UNITS_PER_WORD); | |
16763 | ||
16764 | return flags | (exact_log2 (align) & SECTION_ENTSIZE); | |
5add3202 | 16765 | } |
a5fe455b | 16766 | |
1bc7c5b6 ZW |
16767 | /* Output at beginning of assembler file. |
16768 | ||
16769 | Initialize the section names for the RS/6000 at this point. | |
16770 | ||
16771 | Specify filename, including full path, to assembler. | |
16772 | ||
16773 | We want to go into the TOC section so at least one .toc will be emitted. | |
16774 | Also, in order to output proper .bs/.es pairs, we need at least one static | |
16775 | [RW] section emitted. | |
16776 | ||
16777 | Finally, declare mcount when profiling to make the assembler happy. */ | |
16778 | ||
16779 | static void | |
863d938c | 16780 | rs6000_xcoff_file_start (void) |
1bc7c5b6 ZW |
16781 | { |
16782 | rs6000_gen_section_name (&xcoff_bss_section_name, | |
16783 | main_input_filename, ".bss_"); | |
16784 | rs6000_gen_section_name (&xcoff_private_data_section_name, | |
16785 | main_input_filename, ".rw_"); | |
16786 | rs6000_gen_section_name (&xcoff_read_only_section_name, | |
16787 | main_input_filename, ".ro_"); | |
16788 | ||
16789 | fputs ("\t.file\t", asm_out_file); | |
16790 | output_quoted_string (asm_out_file, main_input_filename); | |
16791 | fputc ('\n', asm_out_file); | |
1bc7c5b6 ZW |
16792 | if (write_symbols != NO_DEBUG) |
16793 | private_data_section (); | |
16794 | text_section (); | |
16795 | if (profile_flag) | |
16796 | fprintf (asm_out_file, "\t.extern %s\n", RS6000_MCOUNT); | |
16797 | rs6000_file_start (); | |
16798 | } | |
16799 | ||
a5fe455b ZW |
16800 | /* Output at end of assembler file. |
16801 | On the RS/6000, referencing data should automatically pull in text. */ | |
16802 | ||
16803 | static void | |
863d938c | 16804 | rs6000_xcoff_file_end (void) |
a5fe455b ZW |
16805 | { |
16806 | text_section (); | |
16807 | fputs ("_section_.text:\n", asm_out_file); | |
16808 | data_section (); | |
16809 | fputs (TARGET_32BIT | |
16810 | ? "\t.long _section_.text\n" : "\t.llong _section_.text\n", | |
16811 | asm_out_file); | |
16812 | } | |
f1384257 | 16813 | #endif /* TARGET_XCOFF */ |
0e5dbd9b | 16814 | |
f1384257 AM |
16815 | #if TARGET_MACHO |
16816 | /* Cross-module name binding. Darwin does not support overriding | |
7f3d8013 | 16817 | functions at dynamic-link time. */ |
0e5dbd9b | 16818 | |
2bcc50d0 | 16819 | static bool |
a2369ed3 | 16820 | rs6000_binds_local_p (tree decl) |
0e5dbd9b | 16821 | { |
f1384257 | 16822 | return default_binds_local_p_1 (decl, 0); |
0e5dbd9b | 16823 | } |
f1384257 | 16824 | #endif |
34bb030a | 16825 | |
3c50106f RH |
16826 | /* Compute a (partial) cost for rtx X. Return true if the complete |
16827 | cost has been computed, and false if subexpressions should be | |
16828 | scanned. In either case, *TOTAL contains the cost result. */ | |
16829 | ||
16830 | static bool | |
1494c534 | 16831 | rs6000_rtx_costs (rtx x, int code, int outer_code, int *total) |
3c50106f | 16832 | { |
f0517163 RS |
16833 | enum machine_mode mode = GET_MODE (x); |
16834 | ||
3c50106f RH |
16835 | switch (code) |
16836 | { | |
30a555d9 | 16837 | /* On the RS/6000, if it is valid in the insn, it is free. */ |
3c50106f | 16838 | case CONST_INT: |
066cd967 DE |
16839 | if (((outer_code == SET |
16840 | || outer_code == PLUS | |
16841 | || outer_code == MINUS) | |
16842 | && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'I') | |
16843 | || CONST_OK_FOR_LETTER_P (INTVAL (x), 'L'))) | |
066cd967 DE |
16844 | || (outer_code == AND |
16845 | && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'K') | |
22e54023 DE |
16846 | || (CONST_OK_FOR_LETTER_P (INTVAL (x), |
16847 | mode == SImode ? 'L' : 'J')) | |
d5861a7a | 16848 | || mask_operand (x, VOIDmode))) |
22e54023 DE |
16849 | || ((outer_code == IOR || outer_code == XOR) |
16850 | && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'K') | |
16851 | || (CONST_OK_FOR_LETTER_P (INTVAL (x), | |
16852 | mode == SImode ? 'L' : 'J')))) | |
066cd967 DE |
16853 | || outer_code == ASHIFT |
16854 | || outer_code == ASHIFTRT | |
16855 | || outer_code == LSHIFTRT | |
16856 | || outer_code == ROTATE | |
16857 | || outer_code == ROTATERT | |
d5861a7a | 16858 | || outer_code == ZERO_EXTRACT |
066cd967 DE |
16859 | || (outer_code == MULT |
16860 | && CONST_OK_FOR_LETTER_P (INTVAL (x), 'I')) | |
22e54023 DE |
16861 | || ((outer_code == DIV || outer_code == UDIV |
16862 | || outer_code == MOD || outer_code == UMOD) | |
16863 | && exact_log2 (INTVAL (x)) >= 0) | |
066cd967 DE |
16864 | || (outer_code == COMPARE |
16865 | && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'I') | |
22e54023 DE |
16866 | || CONST_OK_FOR_LETTER_P (INTVAL (x), 'K'))) |
16867 | || (outer_code == EQ | |
16868 | && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'I') | |
16869 | || CONST_OK_FOR_LETTER_P (INTVAL (x), 'K') | |
16870 | || (CONST_OK_FOR_LETTER_P (INTVAL (x), | |
16871 | mode == SImode ? 'L' : 'J')))) | |
16872 | || (outer_code == GTU | |
16873 | && CONST_OK_FOR_LETTER_P (INTVAL (x), 'I')) | |
16874 | || (outer_code == LTU | |
16875 | && CONST_OK_FOR_LETTER_P (INTVAL (x), 'P'))) | |
066cd967 DE |
16876 | { |
16877 | *total = 0; | |
16878 | return true; | |
16879 | } | |
16880 | else if ((outer_code == PLUS | |
16881 | && reg_or_add_cint64_operand (x, VOIDmode)) | |
16882 | || (outer_code == MINUS | |
16883 | && reg_or_sub_cint64_operand (x, VOIDmode)) | |
16884 | || ((outer_code == SET | |
16885 | || outer_code == IOR | |
16886 | || outer_code == XOR) | |
16887 | && (INTVAL (x) | |
16888 | & ~ (unsigned HOST_WIDE_INT) 0xffffffff) == 0)) | |
16889 | { | |
16890 | *total = COSTS_N_INSNS (1); | |
16891 | return true; | |
16892 | } | |
16893 | /* FALLTHRU */ | |
16894 | ||
16895 | case CONST_DOUBLE: | |
16896 | if (mode == DImode | |
16897 | && ((outer_code == AND | |
16898 | && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'K') | |
16899 | || CONST_OK_FOR_LETTER_P (INTVAL (x), 'L') | |
d5861a7a | 16900 | || mask64_operand (x, DImode))) |
066cd967 DE |
16901 | || ((outer_code == IOR || outer_code == XOR) |
16902 | && CONST_DOUBLE_HIGH (x) == 0 | |
16903 | && (CONST_DOUBLE_LOW (x) | |
16904 | & ~ (unsigned HOST_WIDE_INT) 0xffff) == 0))) | |
16905 | { | |
16906 | *total = 0; | |
16907 | return true; | |
16908 | } | |
16909 | else if (mode == DImode | |
16910 | && (outer_code == SET | |
16911 | || outer_code == IOR | |
16912 | || outer_code == XOR) | |
16913 | && CONST_DOUBLE_HIGH (x) == 0) | |
16914 | { | |
16915 | *total = COSTS_N_INSNS (1); | |
16916 | return true; | |
16917 | } | |
16918 | /* FALLTHRU */ | |
16919 | ||
3c50106f | 16920 | case CONST: |
066cd967 | 16921 | case HIGH: |
3c50106f | 16922 | case SYMBOL_REF: |
066cd967 DE |
16923 | case MEM: |
16924 | /* When optimizing for size, MEM should be slightly more expensive | |
16925 | than generating address, e.g., (plus (reg) (const)). | |
c112cf2b | 16926 | L1 cache latency is about two instructions. */ |
066cd967 | 16927 | *total = optimize_size ? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (2); |
3c50106f RH |
16928 | return true; |
16929 | ||
30a555d9 DE |
16930 | case LABEL_REF: |
16931 | *total = 0; | |
16932 | return true; | |
16933 | ||
3c50106f | 16934 | case PLUS: |
f0517163 | 16935 | if (mode == DFmode) |
066cd967 DE |
16936 | { |
16937 | if (GET_CODE (XEXP (x, 0)) == MULT) | |
16938 | { | |
16939 | /* FNMA accounted in outer NEG. */ | |
16940 | if (outer_code == NEG) | |
16941 | *total = rs6000_cost->dmul - rs6000_cost->fp; | |
16942 | else | |
16943 | *total = rs6000_cost->dmul; | |
16944 | } | |
16945 | else | |
16946 | *total = rs6000_cost->fp; | |
16947 | } | |
f0517163 | 16948 | else if (mode == SFmode) |
066cd967 DE |
16949 | { |
16950 | /* FNMA accounted in outer NEG. */ | |
16951 | if (outer_code == NEG && GET_CODE (XEXP (x, 0)) == MULT) | |
16952 | *total = 0; | |
16953 | else | |
16954 | *total = rs6000_cost->fp; | |
16955 | } | |
938bf747 RS |
16956 | else if (GET_CODE (XEXP (x, 0)) == MULT) |
16957 | { | |
16958 | /* The rs6000 doesn't have shift-and-add instructions. */ | |
16959 | rs6000_rtx_costs (XEXP (x, 0), MULT, PLUS, total); | |
16960 | *total += COSTS_N_INSNS (1); | |
16961 | } | |
f0517163 | 16962 | else |
066cd967 DE |
16963 | *total = COSTS_N_INSNS (1); |
16964 | return false; | |
3c50106f | 16965 | |
52190329 | 16966 | case MINUS: |
f0517163 | 16967 | if (mode == DFmode) |
066cd967 DE |
16968 | { |
16969 | if (GET_CODE (XEXP (x, 0)) == MULT) | |
16970 | { | |
16971 | /* FNMA accounted in outer NEG. */ | |
16972 | if (outer_code == NEG) | |
16973 | *total = 0; | |
16974 | else | |
16975 | *total = rs6000_cost->dmul; | |
16976 | } | |
16977 | else | |
16978 | *total = rs6000_cost->fp; | |
16979 | } | |
f0517163 | 16980 | else if (mode == SFmode) |
066cd967 DE |
16981 | { |
16982 | /* FNMA accounted in outer NEG. */ | |
16983 | if (outer_code == NEG && GET_CODE (XEXP (x, 0)) == MULT) | |
16984 | *total = 0; | |
16985 | else | |
16986 | *total = rs6000_cost->fp; | |
16987 | } | |
938bf747 RS |
16988 | else if (GET_CODE (XEXP (x, 0)) == MULT) |
16989 | { | |
16990 | /* The rs6000 doesn't have shift-and-sub instructions. */ | |
16991 | rs6000_rtx_costs (XEXP (x, 0), MULT, MINUS, total); | |
16992 | *total += COSTS_N_INSNS (1); | |
16993 | } | |
f0517163 | 16994 | else |
c4ad648e | 16995 | *total = COSTS_N_INSNS (1); |
066cd967 | 16996 | return false; |
3c50106f RH |
16997 | |
16998 | case MULT: | |
c9dbf840 DE |
16999 | if (GET_CODE (XEXP (x, 1)) == CONST_INT |
17000 | && CONST_OK_FOR_LETTER_P (INTVAL (XEXP (x, 1)), 'I')) | |
3c50106f | 17001 | { |
8b897cfa RS |
17002 | if (INTVAL (XEXP (x, 1)) >= -256 |
17003 | && INTVAL (XEXP (x, 1)) <= 255) | |
06a67bdd | 17004 | *total = rs6000_cost->mulsi_const9; |
8b897cfa | 17005 | else |
06a67bdd | 17006 | *total = rs6000_cost->mulsi_const; |
3c50106f | 17007 | } |
066cd967 DE |
17008 | /* FMA accounted in outer PLUS/MINUS. */ |
17009 | else if ((mode == DFmode || mode == SFmode) | |
17010 | && (outer_code == PLUS || outer_code == MINUS)) | |
17011 | *total = 0; | |
f0517163 | 17012 | else if (mode == DFmode) |
06a67bdd | 17013 | *total = rs6000_cost->dmul; |
f0517163 | 17014 | else if (mode == SFmode) |
06a67bdd | 17015 | *total = rs6000_cost->fp; |
f0517163 | 17016 | else if (mode == DImode) |
06a67bdd | 17017 | *total = rs6000_cost->muldi; |
8b897cfa | 17018 | else |
06a67bdd | 17019 | *total = rs6000_cost->mulsi; |
066cd967 | 17020 | return false; |
3c50106f RH |
17021 | |
17022 | case DIV: | |
17023 | case MOD: | |
f0517163 RS |
17024 | if (FLOAT_MODE_P (mode)) |
17025 | { | |
06a67bdd RS |
17026 | *total = mode == DFmode ? rs6000_cost->ddiv |
17027 | : rs6000_cost->sdiv; | |
066cd967 | 17028 | return false; |
f0517163 | 17029 | } |
5efb1046 | 17030 | /* FALLTHRU */ |
3c50106f RH |
17031 | |
17032 | case UDIV: | |
17033 | case UMOD: | |
627b6fe2 DJ |
17034 | if (GET_CODE (XEXP (x, 1)) == CONST_INT |
17035 | && exact_log2 (INTVAL (XEXP (x, 1))) >= 0) | |
17036 | { | |
17037 | if (code == DIV || code == MOD) | |
17038 | /* Shift, addze */ | |
17039 | *total = COSTS_N_INSNS (2); | |
17040 | else | |
17041 | /* Shift */ | |
17042 | *total = COSTS_N_INSNS (1); | |
17043 | } | |
c4ad648e | 17044 | else |
627b6fe2 DJ |
17045 | { |
17046 | if (GET_MODE (XEXP (x, 1)) == DImode) | |
17047 | *total = rs6000_cost->divdi; | |
17048 | else | |
17049 | *total = rs6000_cost->divsi; | |
17050 | } | |
17051 | /* Add in shift and subtract for MOD. */ | |
17052 | if (code == MOD || code == UMOD) | |
17053 | *total += COSTS_N_INSNS (2); | |
066cd967 | 17054 | return false; |
3c50106f RH |
17055 | |
17056 | case FFS: | |
17057 | *total = COSTS_N_INSNS (4); | |
066cd967 | 17058 | return false; |
3c50106f | 17059 | |
06a67bdd | 17060 | case NOT: |
066cd967 DE |
17061 | if (outer_code == AND || outer_code == IOR || outer_code == XOR) |
17062 | { | |
17063 | *total = 0; | |
17064 | return false; | |
17065 | } | |
17066 | /* FALLTHRU */ | |
17067 | ||
17068 | case AND: | |
17069 | case IOR: | |
17070 | case XOR: | |
d5861a7a DE |
17071 | case ZERO_EXTRACT: |
17072 | *total = COSTS_N_INSNS (1); | |
17073 | return false; | |
17074 | ||
066cd967 DE |
17075 | case ASHIFT: |
17076 | case ASHIFTRT: | |
17077 | case LSHIFTRT: | |
17078 | case ROTATE: | |
17079 | case ROTATERT: | |
d5861a7a | 17080 | /* Handle mul_highpart. */ |
066cd967 DE |
17081 | if (outer_code == TRUNCATE |
17082 | && GET_CODE (XEXP (x, 0)) == MULT) | |
17083 | { | |
17084 | if (mode == DImode) | |
17085 | *total = rs6000_cost->muldi; | |
17086 | else | |
17087 | *total = rs6000_cost->mulsi; | |
17088 | return true; | |
17089 | } | |
d5861a7a DE |
17090 | else if (outer_code == AND) |
17091 | *total = 0; | |
17092 | else | |
17093 | *total = COSTS_N_INSNS (1); | |
17094 | return false; | |
17095 | ||
17096 | case SIGN_EXTEND: | |
17097 | case ZERO_EXTEND: | |
17098 | if (GET_CODE (XEXP (x, 0)) == MEM) | |
17099 | *total = 0; | |
17100 | else | |
17101 | *total = COSTS_N_INSNS (1); | |
066cd967 | 17102 | return false; |
06a67bdd | 17103 | |
066cd967 DE |
17104 | case COMPARE: |
17105 | case NEG: | |
17106 | case ABS: | |
17107 | if (!FLOAT_MODE_P (mode)) | |
17108 | { | |
17109 | *total = COSTS_N_INSNS (1); | |
17110 | return false; | |
17111 | } | |
17112 | /* FALLTHRU */ | |
17113 | ||
17114 | case FLOAT: | |
17115 | case UNSIGNED_FLOAT: | |
17116 | case FIX: | |
17117 | case UNSIGNED_FIX: | |
17118 | case FLOAT_EXTEND: | |
06a67bdd RS |
17119 | case FLOAT_TRUNCATE: |
17120 | *total = rs6000_cost->fp; | |
066cd967 | 17121 | return false; |
06a67bdd RS |
17122 | |
17123 | case UNSPEC: | |
17124 | switch (XINT (x, 1)) | |
17125 | { | |
17126 | case UNSPEC_FRSP: | |
17127 | *total = rs6000_cost->fp; | |
17128 | return true; | |
17129 | ||
17130 | default: | |
17131 | break; | |
17132 | } | |
17133 | break; | |
17134 | ||
17135 | case CALL: | |
17136 | case IF_THEN_ELSE: | |
17137 | if (optimize_size) | |
17138 | { | |
17139 | *total = COSTS_N_INSNS (1); | |
17140 | return true; | |
17141 | } | |
066cd967 DE |
17142 | else if (FLOAT_MODE_P (mode) |
17143 | && TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS) | |
17144 | { | |
17145 | *total = rs6000_cost->fp; | |
17146 | return false; | |
17147 | } | |
06a67bdd RS |
17148 | break; |
17149 | ||
c0600ecd DE |
17150 | case EQ: |
17151 | case GTU: | |
17152 | case LTU: | |
22e54023 DE |
17153 | /* Carry bit requires mode == Pmode. |
17154 | NEG or PLUS already counted so only add one. */ | |
17155 | if (mode == Pmode | |
17156 | && (outer_code == NEG || outer_code == PLUS)) | |
c0600ecd | 17157 | { |
22e54023 DE |
17158 | *total = COSTS_N_INSNS (1); |
17159 | return true; | |
17160 | } | |
17161 | if (outer_code == SET) | |
17162 | { | |
17163 | if (XEXP (x, 1) == const0_rtx) | |
c0600ecd | 17164 | { |
22e54023 | 17165 | *total = COSTS_N_INSNS (2); |
c0600ecd | 17166 | return true; |
c0600ecd | 17167 | } |
22e54023 DE |
17168 | else if (mode == Pmode) |
17169 | { | |
17170 | *total = COSTS_N_INSNS (3); | |
17171 | return false; | |
17172 | } | |
17173 | } | |
17174 | /* FALLTHRU */ | |
17175 | ||
17176 | case GT: | |
17177 | case LT: | |
17178 | case UNORDERED: | |
17179 | if (outer_code == SET && (XEXP (x, 1) == const0_rtx)) | |
17180 | { | |
17181 | *total = COSTS_N_INSNS (2); | |
17182 | return true; | |
c0600ecd | 17183 | } |
22e54023 DE |
17184 | /* CC COMPARE. */ |
17185 | if (outer_code == COMPARE) | |
17186 | { | |
17187 | *total = 0; | |
17188 | return true; | |
17189 | } | |
17190 | break; | |
c0600ecd | 17191 | |
3c50106f | 17192 | default: |
06a67bdd | 17193 | break; |
3c50106f | 17194 | } |
06a67bdd RS |
17195 | |
17196 | return false; | |
3c50106f RH |
17197 | } |
17198 | ||
34bb030a DE |
17199 | /* A C expression returning the cost of moving data from a register of class |
17200 | CLASS1 to one of CLASS2. */ | |
17201 | ||
17202 | int | |
f676971a | 17203 | rs6000_register_move_cost (enum machine_mode mode, |
a2369ed3 | 17204 | enum reg_class from, enum reg_class to) |
34bb030a DE |
17205 | { |
17206 | /* Moves from/to GENERAL_REGS. */ | |
17207 | if (reg_classes_intersect_p (to, GENERAL_REGS) | |
17208 | || reg_classes_intersect_p (from, GENERAL_REGS)) | |
17209 | { | |
17210 | if (! reg_classes_intersect_p (to, GENERAL_REGS)) | |
17211 | from = to; | |
17212 | ||
17213 | if (from == FLOAT_REGS || from == ALTIVEC_REGS) | |
17214 | return (rs6000_memory_move_cost (mode, from, 0) | |
17215 | + rs6000_memory_move_cost (mode, GENERAL_REGS, 0)); | |
17216 | ||
c4ad648e AM |
17217 | /* It's more expensive to move CR_REGS than CR0_REGS because of the |
17218 | shift. */ | |
34bb030a DE |
17219 | else if (from == CR_REGS) |
17220 | return 4; | |
17221 | ||
17222 | else | |
c4ad648e | 17223 | /* A move will cost one instruction per GPR moved. */ |
34bb030a DE |
17224 | return 2 * HARD_REGNO_NREGS (0, mode); |
17225 | } | |
17226 | ||
c4ad648e | 17227 | /* Moving between two similar registers is just one instruction. */ |
34bb030a DE |
17228 | else if (reg_classes_intersect_p (to, from)) |
17229 | return mode == TFmode ? 4 : 2; | |
17230 | ||
c4ad648e | 17231 | /* Everything else has to go through GENERAL_REGS. */ |
34bb030a | 17232 | else |
f676971a | 17233 | return (rs6000_register_move_cost (mode, GENERAL_REGS, to) |
34bb030a DE |
17234 | + rs6000_register_move_cost (mode, from, GENERAL_REGS)); |
17235 | } | |
17236 | ||
17237 | /* A C expressions returning the cost of moving data of MODE from a register to | |
17238 | or from memory. */ | |
17239 | ||
17240 | int | |
f676971a | 17241 | rs6000_memory_move_cost (enum machine_mode mode, enum reg_class class, |
a2369ed3 | 17242 | int in ATTRIBUTE_UNUSED) |
34bb030a DE |
17243 | { |
17244 | if (reg_classes_intersect_p (class, GENERAL_REGS)) | |
17245 | return 4 * HARD_REGNO_NREGS (0, mode); | |
17246 | else if (reg_classes_intersect_p (class, FLOAT_REGS)) | |
17247 | return 4 * HARD_REGNO_NREGS (32, mode); | |
17248 | else if (reg_classes_intersect_p (class, ALTIVEC_REGS)) | |
17249 | return 4 * HARD_REGNO_NREGS (FIRST_ALTIVEC_REGNO, mode); | |
17250 | else | |
17251 | return 4 + rs6000_register_move_cost (mode, class, GENERAL_REGS); | |
17252 | } | |
17253 | ||
ded9bf77 AH |
17254 | /* Return an RTX representing where to find the function value of a |
17255 | function returning MODE. */ | |
17256 | static rtx | |
17257 | rs6000_complex_function_value (enum machine_mode mode) | |
17258 | { | |
17259 | unsigned int regno; | |
17260 | rtx r1, r2; | |
17261 | enum machine_mode inner = GET_MODE_INNER (mode); | |
fb7e4164 | 17262 | unsigned int inner_bytes = GET_MODE_SIZE (inner); |
ded9bf77 | 17263 | |
18f63bfa AH |
17264 | if (FLOAT_MODE_P (mode) && TARGET_HARD_FLOAT && TARGET_FPRS) |
17265 | regno = FP_ARG_RETURN; | |
354ed18f AH |
17266 | else |
17267 | { | |
18f63bfa | 17268 | regno = GP_ARG_RETURN; |
ded9bf77 | 17269 | |
18f63bfa AH |
17270 | /* 32-bit is OK since it'll go in r3/r4. */ |
17271 | if (TARGET_32BIT && inner_bytes >= 4) | |
ded9bf77 AH |
17272 | return gen_rtx_REG (mode, regno); |
17273 | } | |
17274 | ||
18f63bfa AH |
17275 | if (inner_bytes >= 8) |
17276 | return gen_rtx_REG (mode, regno); | |
17277 | ||
ded9bf77 AH |
17278 | r1 = gen_rtx_EXPR_LIST (inner, gen_rtx_REG (inner, regno), |
17279 | const0_rtx); | |
17280 | r2 = gen_rtx_EXPR_LIST (inner, gen_rtx_REG (inner, regno + 1), | |
fb7e4164 | 17281 | GEN_INT (inner_bytes)); |
ded9bf77 AH |
17282 | return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r2)); |
17283 | } | |
17284 | ||
a6ebc39a AH |
17285 | /* Define how to find the value returned by a function. |
17286 | VALTYPE is the data type of the value (as a tree). | |
17287 | If the precise function being called is known, FUNC is its FUNCTION_DECL; | |
17288 | otherwise, FUNC is 0. | |
17289 | ||
17290 | On the SPE, both FPs and vectors are returned in r3. | |
17291 | ||
17292 | On RS/6000 an integer value is in r3 and a floating-point value is in | |
17293 | fp1, unless -msoft-float. */ | |
17294 | ||
17295 | rtx | |
17296 | rs6000_function_value (tree valtype, tree func ATTRIBUTE_UNUSED) | |
17297 | { | |
17298 | enum machine_mode mode; | |
2a8fa26c | 17299 | unsigned int regno; |
a6ebc39a | 17300 | |
594a51fe SS |
17301 | /* Special handling for structs in darwin64. */ |
17302 | if (rs6000_darwin64_abi | |
17303 | && TYPE_MODE (valtype) == BLKmode | |
0b5383eb DJ |
17304 | && TREE_CODE (valtype) == RECORD_TYPE |
17305 | && int_size_in_bytes (valtype) > 0) | |
594a51fe SS |
17306 | { |
17307 | CUMULATIVE_ARGS valcum; | |
17308 | rtx valret; | |
17309 | ||
0b5383eb | 17310 | valcum.words = 0; |
594a51fe SS |
17311 | valcum.fregno = FP_ARG_MIN_REG; |
17312 | valcum.vregno = ALTIVEC_ARG_MIN_REG; | |
0b5383eb DJ |
17313 | /* Do a trial code generation as if this were going to be passed as |
17314 | an argument; if any part goes in memory, we return NULL. */ | |
17315 | valret = rs6000_darwin64_record_arg (&valcum, valtype, 1, true); | |
594a51fe SS |
17316 | if (valret) |
17317 | return valret; | |
17318 | /* Otherwise fall through to standard ABI rules. */ | |
17319 | } | |
17320 | ||
0e67400a FJ |
17321 | if (TARGET_32BIT && TARGET_POWERPC64 && TYPE_MODE (valtype) == DImode) |
17322 | { | |
17323 | /* Long long return value need be split in -mpowerpc64, 32bit ABI. */ | |
17324 | return gen_rtx_PARALLEL (DImode, | |
17325 | gen_rtvec (2, | |
17326 | gen_rtx_EXPR_LIST (VOIDmode, | |
17327 | gen_rtx_REG (SImode, GP_ARG_RETURN), | |
17328 | const0_rtx), | |
17329 | gen_rtx_EXPR_LIST (VOIDmode, | |
17330 | gen_rtx_REG (SImode, | |
17331 | GP_ARG_RETURN + 1), | |
17332 | GEN_INT (4)))); | |
17333 | } | |
17334 | ||
a6ebc39a AH |
17335 | if ((INTEGRAL_TYPE_P (valtype) |
17336 | && TYPE_PRECISION (valtype) < BITS_PER_WORD) | |
17337 | || POINTER_TYPE_P (valtype)) | |
b78d48dd | 17338 | mode = TARGET_32BIT ? SImode : DImode; |
a6ebc39a AH |
17339 | else |
17340 | mode = TYPE_MODE (valtype); | |
17341 | ||
4ed78545 | 17342 | if (SCALAR_FLOAT_TYPE_P (valtype) && TARGET_HARD_FLOAT && TARGET_FPRS) |
2a8fa26c | 17343 | regno = FP_ARG_RETURN; |
ded9bf77 | 17344 | else if (TREE_CODE (valtype) == COMPLEX_TYPE |
42ba5130 | 17345 | && targetm.calls.split_complex_arg) |
ded9bf77 | 17346 | return rs6000_complex_function_value (mode); |
44688022 | 17347 | else if (TREE_CODE (valtype) == VECTOR_TYPE |
d0b2079e | 17348 | && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI |
23ba09f0 | 17349 | && ALTIVEC_VECTOR_MODE (mode)) |
a6ebc39a | 17350 | regno = ALTIVEC_ARG_RETURN; |
18f63bfa AH |
17351 | else if (TARGET_E500_DOUBLE && TARGET_HARD_FLOAT |
17352 | && (mode == DFmode || mode == DCmode)) | |
17353 | return spe_build_register_parallel (mode, GP_ARG_RETURN); | |
a6ebc39a AH |
17354 | else |
17355 | regno = GP_ARG_RETURN; | |
17356 | ||
17357 | return gen_rtx_REG (mode, regno); | |
17358 | } | |
17359 | ||
ded9bf77 AH |
17360 | /* Define how to find the value returned by a library function |
17361 | assuming the value has mode MODE. */ | |
17362 | rtx | |
17363 | rs6000_libcall_value (enum machine_mode mode) | |
17364 | { | |
17365 | unsigned int regno; | |
17366 | ||
2e6c9641 FJ |
17367 | if (TARGET_32BIT && TARGET_POWERPC64 && mode == DImode) |
17368 | { | |
17369 | /* Long long return value need be split in -mpowerpc64, 32bit ABI. */ | |
17370 | return gen_rtx_PARALLEL (DImode, | |
17371 | gen_rtvec (2, | |
17372 | gen_rtx_EXPR_LIST (VOIDmode, | |
17373 | gen_rtx_REG (SImode, GP_ARG_RETURN), | |
17374 | const0_rtx), | |
17375 | gen_rtx_EXPR_LIST (VOIDmode, | |
17376 | gen_rtx_REG (SImode, | |
17377 | GP_ARG_RETURN + 1), | |
17378 | GEN_INT (4)))); | |
17379 | } | |
17380 | ||
ded9bf77 AH |
17381 | if (GET_MODE_CLASS (mode) == MODE_FLOAT |
17382 | && TARGET_HARD_FLOAT && TARGET_FPRS) | |
17383 | regno = FP_ARG_RETURN; | |
44688022 AM |
17384 | else if (ALTIVEC_VECTOR_MODE (mode) |
17385 | && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI) | |
ded9bf77 | 17386 | regno = ALTIVEC_ARG_RETURN; |
42ba5130 | 17387 | else if (COMPLEX_MODE_P (mode) && targetm.calls.split_complex_arg) |
ded9bf77 | 17388 | return rs6000_complex_function_value (mode); |
18f63bfa AH |
17389 | else if (TARGET_E500_DOUBLE && TARGET_HARD_FLOAT |
17390 | && (mode == DFmode || mode == DCmode)) | |
17391 | return spe_build_register_parallel (mode, GP_ARG_RETURN); | |
ded9bf77 AH |
17392 | else |
17393 | regno = GP_ARG_RETURN; | |
17394 | ||
17395 | return gen_rtx_REG (mode, regno); | |
17396 | } | |
17397 | ||
d1d0c603 JJ |
17398 | /* Define the offset between two registers, FROM to be eliminated and its |
17399 | replacement TO, at the start of a routine. */ | |
17400 | HOST_WIDE_INT | |
17401 | rs6000_initial_elimination_offset (int from, int to) | |
17402 | { | |
17403 | rs6000_stack_t *info = rs6000_stack_info (); | |
17404 | HOST_WIDE_INT offset; | |
17405 | ||
17406 | if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM) | |
17407 | offset = info->push_p ? 0 : -info->total_size; | |
17408 | else if (from == ARG_POINTER_REGNUM && to == FRAME_POINTER_REGNUM) | |
17409 | offset = info->total_size; | |
17410 | else if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM) | |
17411 | offset = info->push_p ? info->total_size : 0; | |
17412 | else if (from == RS6000_PIC_OFFSET_TABLE_REGNUM) | |
17413 | offset = 0; | |
17414 | else | |
17415 | abort (); | |
17416 | ||
17417 | return offset; | |
17418 | } | |
17419 | ||
62e1dfcf NC |
17420 | /* Return true if TYPE is of type __ev64_opaque__. */ |
17421 | ||
c8e4f0e9 | 17422 | static bool |
a2369ed3 | 17423 | is_ev64_opaque_type (tree type) |
62e1dfcf | 17424 | { |
c8e4f0e9 | 17425 | return (TARGET_SPE |
2abe3e28 AH |
17426 | && (type == opaque_V2SI_type_node |
17427 | || type == opaque_V2SF_type_node | |
36252949 | 17428 | || type == opaque_p_V2SI_type_node)); |
62e1dfcf NC |
17429 | } |
17430 | ||
96714395 | 17431 | static rtx |
a2369ed3 | 17432 | rs6000_dwarf_register_span (rtx reg) |
96714395 AH |
17433 | { |
17434 | unsigned regno; | |
17435 | ||
4d4cbc0e AH |
17436 | if (TARGET_SPE |
17437 | && (SPE_VECTOR_MODE (GET_MODE (reg)) | |
17438 | || (TARGET_E500_DOUBLE && GET_MODE (reg) == DFmode))) | |
17439 | ; | |
17440 | else | |
96714395 AH |
17441 | return NULL_RTX; |
17442 | ||
17443 | regno = REGNO (reg); | |
17444 | ||
17445 | /* The duality of the SPE register size wreaks all kinds of havoc. | |
17446 | This is a way of distinguishing r0 in 32-bits from r0 in | |
17447 | 64-bits. */ | |
17448 | return | |
17449 | gen_rtx_PARALLEL (VOIDmode, | |
3bd104d1 AH |
17450 | BYTES_BIG_ENDIAN |
17451 | ? gen_rtvec (2, | |
17452 | gen_rtx_REG (SImode, regno + 1200), | |
17453 | gen_rtx_REG (SImode, regno)) | |
17454 | : gen_rtvec (2, | |
17455 | gen_rtx_REG (SImode, regno), | |
17456 | gen_rtx_REG (SImode, regno + 1200))); | |
96714395 AH |
17457 | } |
17458 | ||
93c9d1ba AM |
17459 | /* Map internal gcc register numbers to DWARF2 register numbers. */ |
17460 | ||
17461 | unsigned int | |
17462 | rs6000_dbx_register_number (unsigned int regno) | |
17463 | { | |
17464 | if (regno <= 63 || write_symbols != DWARF2_DEBUG) | |
17465 | return regno; | |
17466 | if (regno == MQ_REGNO) | |
17467 | return 100; | |
17468 | if (regno == LINK_REGISTER_REGNUM) | |
17469 | return 108; | |
17470 | if (regno == COUNT_REGISTER_REGNUM) | |
17471 | return 109; | |
17472 | if (CR_REGNO_P (regno)) | |
17473 | return regno - CR0_REGNO + 86; | |
17474 | if (regno == XER_REGNO) | |
17475 | return 101; | |
17476 | if (ALTIVEC_REGNO_P (regno)) | |
17477 | return regno - FIRST_ALTIVEC_REGNO + 1124; | |
17478 | if (regno == VRSAVE_REGNO) | |
17479 | return 356; | |
17480 | if (regno == VSCR_REGNO) | |
17481 | return 67; | |
17482 | if (regno == SPE_ACC_REGNO) | |
17483 | return 99; | |
17484 | if (regno == SPEFSCR_REGNO) | |
17485 | return 612; | |
17486 | /* SPE high reg number. We get these values of regno from | |
17487 | rs6000_dwarf_register_span. */ | |
17488 | if (regno >= 1200 && regno < 1232) | |
17489 | return regno; | |
17490 | ||
17491 | abort (); | |
17492 | } | |
17493 | ||
93f90be6 | 17494 | /* target hook eh_return_filter_mode */ |
f676971a | 17495 | static enum machine_mode |
93f90be6 FJ |
17496 | rs6000_eh_return_filter_mode (void) |
17497 | { | |
17498 | return TARGET_32BIT ? SImode : word_mode; | |
17499 | } | |
17500 | ||
f676971a EC |
17501 | /* Target hook for vector_mode_supported_p. */ |
17502 | static bool | |
17503 | rs6000_vector_mode_supported_p (enum machine_mode mode) | |
17504 | { | |
17505 | ||
17506 | if (TARGET_SPE && SPE_VECTOR_MODE (mode)) | |
17507 | return true; | |
17508 | ||
17509 | else if (TARGET_ALTIVEC && ALTIVEC_VECTOR_MODE (mode)) | |
17510 | return true; | |
17511 | ||
17512 | else | |
17513 | return false; | |
17514 | } | |
17515 | ||
17211ab5 | 17516 | #include "gt-rs6000.h" |