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9878760c | 1 | /* Subroutines used for code generation on IBM RS/6000. |
9ebbca7d | 2 | Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, |
63b6e069 | 3 | 2000, 2001 Free Software Foundation, Inc. |
fab3bcc3 | 4 | Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu) |
9878760c RK |
5 | |
6 | This file is part of GNU CC. | |
7 | ||
8 | GNU CC is free software; you can redistribute it and/or modify | |
9 | it under the terms of the GNU General Public License as published by | |
10 | the Free Software Foundation; either version 2, or (at your option) | |
11 | any later version. | |
12 | ||
13 | GNU CC is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
19 | along with GNU CC; see the file COPYING. If not, write to | |
c15c9075 RK |
20 | the Free Software Foundation, 59 Temple Place - Suite 330, |
21 | Boston, MA 02111-1307, USA. */ | |
9878760c | 22 | |
956d6950 | 23 | #include "config.h" |
c4d38ccb | 24 | #include "system.h" |
9878760c RK |
25 | #include "rtl.h" |
26 | #include "regs.h" | |
27 | #include "hard-reg-set.h" | |
28 | #include "real.h" | |
29 | #include "insn-config.h" | |
30 | #include "conditions.h" | |
9878760c RK |
31 | #include "insn-attr.h" |
32 | #include "flags.h" | |
33 | #include "recog.h" | |
9878760c | 34 | #include "obstack.h" |
9b30bae2 | 35 | #include "tree.h" |
dfafc897 | 36 | #include "expr.h" |
2fc1c679 | 37 | #include "optabs.h" |
2a430ec1 | 38 | #include "except.h" |
a7df97e6 | 39 | #include "function.h" |
296b8152 | 40 | #include "output.h" |
d5fa86ba | 41 | #include "basic-block.h" |
d0101753 | 42 | #include "integrate.h" |
296b8152 | 43 | #include "toplev.h" |
c8023011 | 44 | #include "ggc.h" |
9ebbca7d GK |
45 | #include "hashtab.h" |
46 | #include "tm_p.h" | |
672a6f42 NB |
47 | #include "target.h" |
48 | #include "target-def.h" | |
3ac88239 | 49 | #include "langhooks.h" |
9b30bae2 | 50 | |
7509c759 MM |
51 | #ifndef TARGET_NO_PROTOTYPE |
52 | #define TARGET_NO_PROTOTYPE 0 | |
53 | #endif | |
54 | ||
5248c961 | 55 | extern int profile_block_flag; |
9878760c RK |
56 | |
57 | #define min(A,B) ((A) < (B) ? (A) : (B)) | |
58 | #define max(A,B) ((A) > (B) ? (A) : (B)) | |
59 | ||
5248c961 RK |
60 | /* Target cpu type */ |
61 | ||
62 | enum processor_type rs6000_cpu; | |
8e3f41e7 MM |
63 | struct rs6000_cpu_select rs6000_select[3] = |
64 | { | |
815cdc52 MM |
65 | /* switch name, tune arch */ |
66 | { (const char *)0, "--with-cpu=", 1, 1 }, | |
67 | { (const char *)0, "-mcpu=", 1, 1 }, | |
68 | { (const char *)0, "-mtune=", 1, 0 }, | |
8e3f41e7 | 69 | }; |
5248c961 | 70 | |
c764f757 RK |
71 | /* Set to non-zero once AIX common-mode calls have been defined. */ |
72 | static int common_mode_defined; | |
c81bebd7 | 73 | |
9878760c RK |
74 | /* Save information from a "cmpxx" operation until the branch or scc is |
75 | emitted. */ | |
9878760c RK |
76 | rtx rs6000_compare_op0, rs6000_compare_op1; |
77 | int rs6000_compare_fp_p; | |
874a0744 | 78 | |
874a0744 MM |
79 | /* Label number of label created for -mrelocatable, to call to so we can |
80 | get the address of the GOT section */ | |
81 | int rs6000_pic_labelno; | |
c81bebd7 | 82 | |
b91da81f | 83 | #ifdef USING_ELFOS_H |
c81bebd7 | 84 | /* Which abi to adhere to */ |
815cdc52 | 85 | const char *rs6000_abi_name = RS6000_ABI_NAME; |
d9407988 MM |
86 | |
87 | /* Semantics of the small data area */ | |
88 | enum rs6000_sdata_type rs6000_sdata = SDATA_DATA; | |
89 | ||
90 | /* Which small data model to use */ | |
815cdc52 | 91 | const char *rs6000_sdata_name = (char *)0; |
9ebbca7d GK |
92 | |
93 | /* Counter for labels which are to be placed in .fixup. */ | |
94 | int fixuplabelno = 0; | |
874a0744 | 95 | #endif |
4697a36c | 96 | |
b6c9286a MM |
97 | /* ABI enumeration available for subtarget to use. */ |
98 | enum rs6000_abi rs6000_current_abi; | |
99 | ||
0ac081f6 AH |
100 | /* ABI string from -mabi= option. */ |
101 | const char *rs6000_abi_string; | |
102 | ||
38c1f2d7 | 103 | /* Debug flags */ |
815cdc52 | 104 | const char *rs6000_debug_name; |
38c1f2d7 MM |
105 | int rs6000_debug_stack; /* debug stack applications */ |
106 | int rs6000_debug_arg; /* debug argument handling */ | |
107 | ||
108 | /* Flag to say the TOC is initialized */ | |
109 | int toc_initialized; | |
9ebbca7d | 110 | char toc_label_name[10]; |
38c1f2d7 | 111 | |
9ebbca7d GK |
112 | /* Alias set for saves and restores from the rs6000 stack. */ |
113 | static int rs6000_sr_alias_set; | |
c8023011 | 114 | |
9ebbca7d GK |
115 | static void rs6000_add_gc_roots PARAMS ((void)); |
116 | static int num_insns_constant_wide PARAMS ((HOST_WIDE_INT)); | |
117 | static rtx expand_block_move_mem PARAMS ((enum machine_mode, rtx, rtx)); | |
39a10a29 GK |
118 | static void validate_condition_mode |
119 | PARAMS ((enum rtx_code, enum machine_mode)); | |
120 | static rtx rs6000_generate_compare PARAMS ((enum rtx_code)); | |
e50f5f3d | 121 | static void rs6000_maybe_dead PARAMS ((rtx)); |
9ebbca7d GK |
122 | static void rs6000_emit_stack_tie PARAMS ((void)); |
123 | static void rs6000_frame_related PARAMS ((rtx, rtx, HOST_WIDE_INT, rtx, rtx)); | |
124 | static void rs6000_emit_allocate_stack PARAMS ((HOST_WIDE_INT, int)); | |
125 | static unsigned rs6000_hash_constant PARAMS ((rtx)); | |
126 | static unsigned toc_hash_function PARAMS ((const void *)); | |
127 | static int toc_hash_eq PARAMS ((const void *, const void *)); | |
2eba1afa | 128 | static int toc_hash_mark_entry PARAMS ((void **, void *)); |
9ebbca7d GK |
129 | static void toc_hash_mark_table PARAMS ((void *)); |
130 | static int constant_pool_expr_1 PARAMS ((rtx, int *, int *)); | |
6fee9e99 NC |
131 | static void rs6000_free_machine_status PARAMS ((struct function *)); |
132 | static void rs6000_init_machine_status PARAMS ((struct function *)); | |
71f123ca | 133 | static int rs6000_ra_ever_killed PARAMS ((void)); |
91d231cb JM |
134 | static tree rs6000_handle_longcall_attribute PARAMS ((tree *, tree, tree, int, bool *)); |
135 | const struct attribute_spec rs6000_attribute_table[]; | |
08c148a8 NB |
136 | static void rs6000_output_function_prologue PARAMS ((FILE *, HOST_WIDE_INT)); |
137 | static void rs6000_output_function_epilogue PARAMS ((FILE *, HOST_WIDE_INT)); | |
2bfcf297 DB |
138 | static rtx rs6000_emit_set_long_const PARAMS ((rtx, |
139 | HOST_WIDE_INT, HOST_WIDE_INT)); | |
7c262518 RH |
140 | #if TARGET_ELF |
141 | static unsigned int rs6000_elf_section_type_flags PARAMS ((tree, const char *, | |
142 | int)); | |
d9f6800d RH |
143 | static void rs6000_elf_asm_out_constructor PARAMS ((rtx, int)); |
144 | static void rs6000_elf_asm_out_destructor PARAMS ((rtx, int)); | |
7c262518 RH |
145 | #endif |
146 | #ifdef OBJECT_FORMAT_COFF | |
715bdd29 | 147 | static void xcoff_asm_named_section PARAMS ((const char *, unsigned int)); |
7c262518 | 148 | #endif |
c237e94a ZW |
149 | static int rs6000_adjust_cost PARAMS ((rtx, rtx, rtx, int)); |
150 | static int rs6000_adjust_priority PARAMS ((rtx, int)); | |
151 | static int rs6000_issue_rate PARAMS ((void)); | |
152 | ||
0ac081f6 AH |
153 | static void rs6000_init_builtins PARAMS ((tree)); |
154 | static void altivec_init_builtins PARAMS ((void)); | |
155 | static rtx rs6000_expand_builtin PARAMS ((tree, rtx, rtx, enum machine_mode, int)); | |
00b960c7 | 156 | static rtx altivec_expand_builtin PARAMS ((tree, rtx)); |
0ac081f6 AH |
157 | static rtx altivec_expand_binop_builtin PARAMS ((enum insn_code, tree, rtx)); |
158 | ||
159 | static void rs6000_parse_abi_options PARAMS ((void)); | |
00b960c7 AH |
160 | static int first_altivec_reg_to_save PARAMS ((void)); |
161 | static unsigned int compute_vrsave_mask PARAMS ((void)); | |
162 | static void is_altivec_return_reg PARAMS ((rtx, void *)); | |
163 | int vrsave_operation PARAMS ((rtx, enum machine_mode)); | |
164 | static rtx generate_set_vrsave PARAMS ((rtx, rs6000_stack_t *)); | |
c81bebd7 MM |
165 | \f |
166 | /* Default register names. */ | |
167 | char rs6000_reg_names[][8] = | |
168 | { | |
802a0058 MM |
169 | "0", "1", "2", "3", "4", "5", "6", "7", |
170 | "8", "9", "10", "11", "12", "13", "14", "15", | |
171 | "16", "17", "18", "19", "20", "21", "22", "23", | |
172 | "24", "25", "26", "27", "28", "29", "30", "31", | |
173 | "0", "1", "2", "3", "4", "5", "6", "7", | |
174 | "8", "9", "10", "11", "12", "13", "14", "15", | |
175 | "16", "17", "18", "19", "20", "21", "22", "23", | |
176 | "24", "25", "26", "27", "28", "29", "30", "31", | |
177 | "mq", "lr", "ctr","ap", | |
178 | "0", "1", "2", "3", "4", "5", "6", "7", | |
0ac081f6 AH |
179 | "xer", |
180 | /* AltiVec registers. */ | |
0cd5e3a1 AH |
181 | "0", "1", "2", "3", "4", "5", "6", "7", |
182 | "8", "9", "10", "11", "12", "13", "14", "15", | |
183 | "16", "17", "18", "19", "20", "21", "22", "23", | |
184 | "24", "25", "26", "27", "28", "29", "30", "31", | |
0ac081f6 | 185 | "vrsave" |
c81bebd7 MM |
186 | }; |
187 | ||
188 | #ifdef TARGET_REGNAMES | |
8b60264b | 189 | static const char alt_reg_names[][8] = |
c81bebd7 | 190 | { |
802a0058 MM |
191 | "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7", |
192 | "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15", | |
193 | "%r16", "%r17", "%r18", "%r19", "%r20", "%r21", "%r22", "%r23", | |
194 | "%r24", "%r25", "%r26", "%r27", "%r28", "%r29", "%r30", "%r31", | |
195 | "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7", | |
196 | "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15", | |
197 | "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23", | |
198 | "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31", | |
199 | "mq", "lr", "ctr", "ap", | |
200 | "%cr0", "%cr1", "%cr2", "%cr3", "%cr4", "%cr5", "%cr6", "%cr7", | |
0ac081f6 AH |
201 | "xer", |
202 | /* AltiVec registers. */ | |
203 | "%v0", "%v1", "%v2", "%v3", "%v4", "%v5", "%v6", "%v7", | |
204 | "%v8", "%v9", "%v10", "%v11", "%v12", "%v13", "%v14", "%v15", | |
205 | "%v16", "%v17", "%v18", "%v19", "%v20", "%v21", "%v22", "%v23", | |
206 | "%v24", "%v25", "%v26", "%v27", "%v28", "%v29", "%v30", "%v31", | |
207 | "%vrsave" | |
c81bebd7 MM |
208 | }; |
209 | #endif | |
9878760c | 210 | \f |
daf11973 MM |
211 | #ifndef MASK_STRICT_ALIGN |
212 | #define MASK_STRICT_ALIGN 0 | |
213 | #endif | |
672a6f42 NB |
214 | \f |
215 | /* Initialize the GCC target structure. */ | |
91d231cb JM |
216 | #undef TARGET_ATTRIBUTE_TABLE |
217 | #define TARGET_ATTRIBUTE_TABLE rs6000_attribute_table | |
daf11973 | 218 | |
08c148a8 NB |
219 | #undef TARGET_ASM_FUNCTION_PROLOGUE |
220 | #define TARGET_ASM_FUNCTION_PROLOGUE rs6000_output_function_prologue | |
221 | #undef TARGET_ASM_FUNCTION_EPILOGUE | |
222 | #define TARGET_ASM_FUNCTION_EPILOGUE rs6000_output_function_epilogue | |
223 | ||
7c262518 RH |
224 | #if TARGET_ELF |
225 | #undef TARGET_SECTION_TYPE_FLAGS | |
226 | #define TARGET_SECTION_TYPE_FLAGS rs6000_elf_section_type_flags | |
227 | #endif | |
228 | ||
c237e94a ZW |
229 | #undef TARGET_SCHED_ISSUE_RATE |
230 | #define TARGET_SCHED_ISSUE_RATE rs6000_issue_rate | |
231 | #undef TARGET_SCHED_ADJUST_COST | |
232 | #define TARGET_SCHED_ADJUST_COST rs6000_adjust_cost | |
233 | #undef TARGET_SCHED_ADJUST_PRIORITY | |
234 | #define TARGET_SCHED_ADJUST_PRIORITY rs6000_adjust_priority | |
235 | ||
0ac081f6 AH |
236 | #undef TARGET_INIT_BUILTINS |
237 | #define TARGET_INIT_BUILTINS rs6000_init_builtins | |
238 | ||
239 | #undef TARGET_EXPAND_BUILTIN | |
240 | #define TARGET_EXPAND_BUILTIN rs6000_expand_builtin | |
241 | ||
00b960c7 AH |
242 | /* The VRSAVE bitmask puts bit %v0 as the most significant bit. */ |
243 | #define ALTIVEC_REG_BIT(REGNO) (0x80000000 >> ((REGNO) - FIRST_ALTIVEC_REGNO)) | |
244 | ||
f6897b10 | 245 | struct gcc_target targetm = TARGET_INITIALIZER; |
672a6f42 | 246 | \f |
5248c961 RK |
247 | /* Override command line options. Mostly we process the processor |
248 | type and sometimes adjust other TARGET_ options. */ | |
249 | ||
250 | void | |
8e3f41e7 | 251 | rs6000_override_options (default_cpu) |
d330fd93 | 252 | const char *default_cpu; |
5248c961 | 253 | { |
c4d38ccb | 254 | size_t i, j; |
8e3f41e7 | 255 | struct rs6000_cpu_select *ptr; |
5248c961 | 256 | |
85638c0d RK |
257 | /* Simplify the entries below by making a mask for any POWER |
258 | variant and any PowerPC variant. */ | |
259 | ||
938937d8 | 260 | #define POWER_MASKS (MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING) |
68c49ffa RK |
261 | #define POWERPC_MASKS (MASK_POWERPC | MASK_PPC_GPOPT \ |
262 | | MASK_PPC_GFXOPT | MASK_POWERPC64) | |
263 | #define POWERPC_OPT_MASKS (MASK_PPC_GPOPT | MASK_PPC_GFXOPT) | |
85638c0d | 264 | |
5248c961 RK |
265 | static struct ptt |
266 | { | |
8b60264b KG |
267 | const char *const name; /* Canonical processor name. */ |
268 | const enum processor_type processor; /* Processor type enum value. */ | |
269 | const int target_enable; /* Target flags to enable. */ | |
270 | const int target_disable; /* Target flags to disable. */ | |
271 | } const processor_target_table[] | |
cf27b467 MM |
272 | = {{"common", PROCESSOR_COMMON, MASK_NEW_MNEMONICS, |
273 | POWER_MASKS | POWERPC_MASKS}, | |
db7f1e43 | 274 | {"power", PROCESSOR_POWER, |
938937d8 | 275 | MASK_POWER | MASK_MULTIPLE | MASK_STRING, |
db7f1e43 | 276 | MASK_POWER2 | POWERPC_MASKS | MASK_NEW_MNEMONICS}, |
8e3f41e7 MM |
277 | {"power2", PROCESSOR_POWER, |
278 | MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING, | |
279 | POWERPC_MASKS | MASK_NEW_MNEMONICS}, | |
c71791e0 DE |
280 | {"power3", PROCESSOR_PPC630, |
281 | MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS, | |
282 | POWER_MASKS | MASK_PPC_GPOPT}, | |
db7f1e43 RK |
283 | {"powerpc", PROCESSOR_POWERPC, |
284 | MASK_POWERPC | MASK_NEW_MNEMONICS, | |
68c49ffa | 285 | POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64}, |
3cb999d8 DE |
286 | {"powerpc64", PROCESSOR_POWERPC64, |
287 | MASK_POWERPC | MASK_POWERPC64 | MASK_NEW_MNEMONICS, | |
288 | POWER_MASKS | POWERPC_OPT_MASKS}, | |
db7f1e43 | 289 | {"rios", PROCESSOR_RIOS1, |
938937d8 | 290 | MASK_POWER | MASK_MULTIPLE | MASK_STRING, |
db7f1e43 RK |
291 | MASK_POWER2 | POWERPC_MASKS | MASK_NEW_MNEMONICS}, |
292 | {"rios1", PROCESSOR_RIOS1, | |
938937d8 | 293 | MASK_POWER | MASK_MULTIPLE | MASK_STRING, |
db7f1e43 RK |
294 | MASK_POWER2 | POWERPC_MASKS | MASK_NEW_MNEMONICS}, |
295 | {"rsc", PROCESSOR_PPC601, | |
938937d8 | 296 | MASK_POWER | MASK_MULTIPLE | MASK_STRING, |
db7f1e43 RK |
297 | MASK_POWER2 | POWERPC_MASKS | MASK_NEW_MNEMONICS}, |
298 | {"rsc1", PROCESSOR_PPC601, | |
938937d8 | 299 | MASK_POWER | MASK_MULTIPLE | MASK_STRING, |
db7f1e43 RK |
300 | MASK_POWER2 | POWERPC_MASKS | MASK_NEW_MNEMONICS}, |
301 | {"rios2", PROCESSOR_RIOS2, | |
938937d8 | 302 | MASK_POWER | MASK_MULTIPLE | MASK_STRING | MASK_POWER2, |
db7f1e43 | 303 | POWERPC_MASKS | MASK_NEW_MNEMONICS}, |
3cb999d8 DE |
304 | {"rs64a", PROCESSOR_RS64A, |
305 | MASK_POWERPC | MASK_NEW_MNEMONICS, | |
306 | POWER_MASKS | POWERPC_OPT_MASKS}, | |
a3a1dbf6 MM |
307 | {"401", PROCESSOR_PPC403, |
308 | MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS, | |
309 | POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64}, | |
49a0b204 | 310 | {"403", PROCESSOR_PPC403, |
daf11973 | 311 | MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS | MASK_STRICT_ALIGN, |
49a0b204 | 312 | POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64}, |
cf27b467 MM |
313 | {"505", PROCESSOR_MPCCORE, |
314 | MASK_POWERPC | MASK_NEW_MNEMONICS, | |
315 | POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64}, | |
5248c961 | 316 | {"601", PROCESSOR_PPC601, |
938937d8 | 317 | MASK_POWER | MASK_POWERPC | MASK_NEW_MNEMONICS | MASK_MULTIPLE | MASK_STRING, |
68c49ffa | 318 | MASK_POWER2 | POWERPC_OPT_MASKS | MASK_POWERPC64}, |
1ec26da6 | 319 | {"602", PROCESSOR_PPC603, |
cf27b467 MM |
320 | MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS, |
321 | POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64}, | |
5248c961 | 322 | {"603", PROCESSOR_PPC603, |
68c49ffa RK |
323 | MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS, |
324 | POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64}, | |
b6c9286a MM |
325 | {"603e", PROCESSOR_PPC603, |
326 | MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS, | |
327 | POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64}, | |
b5370a88 | 328 | {"ec603e", PROCESSOR_PPC603, |
a3a1dbf6 MM |
329 | MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS, |
330 | POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64}, | |
5248c961 | 331 | {"604", PROCESSOR_PPC604, |
b6c9286a MM |
332 | MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS, |
333 | POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64}, | |
cac8ce95 | 334 | {"604e", PROCESSOR_PPC604e, |
07e6159a MM |
335 | MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS, |
336 | POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64}, | |
b6c9286a | 337 | {"620", PROCESSOR_PPC620, |
68c49ffa | 338 | MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS, |
a260abc9 | 339 | POWER_MASKS | MASK_PPC_GPOPT}, |
3cb999d8 DE |
340 | {"630", PROCESSOR_PPC630, |
341 | MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS, | |
342 | POWER_MASKS | MASK_PPC_GPOPT}, | |
bef84347 VM |
343 | {"740", PROCESSOR_PPC750, |
344 | MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS, | |
345 | POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64}, | |
346 | {"750", PROCESSOR_PPC750, | |
347 | MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS, | |
348 | POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64}, | |
a4f6c312 SS |
349 | {"7400", PROCESSOR_PPC7400, |
350 | MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS, | |
351 | POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64}, | |
352 | {"7450", PROCESSOR_PPC7450, | |
353 | MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS, | |
354 | POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64}, | |
07e6159a MM |
355 | {"801", PROCESSOR_MPCCORE, |
356 | MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS, | |
357 | POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64}, | |
cf27b467 MM |
358 | {"821", PROCESSOR_MPCCORE, |
359 | MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS, | |
360 | POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64}, | |
07e6159a MM |
361 | {"823", PROCESSOR_MPCCORE, |
362 | MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS, | |
363 | POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64}, | |
cf27b467 MM |
364 | {"860", PROCESSOR_MPCCORE, |
365 | MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS, | |
366 | POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64}}; | |
5248c961 | 367 | |
c4d38ccb | 368 | size_t ptt_size = sizeof (processor_target_table) / sizeof (struct ptt); |
5248c961 | 369 | |
a4f6c312 SS |
370 | /* Save current -mmultiple/-mno-multiple status. */ |
371 | int multiple = TARGET_MULTIPLE; | |
372 | /* Save current -mstring/-mno-string status. */ | |
373 | int string = TARGET_STRING; | |
8a61d227 | 374 | |
5248c961 RK |
375 | profile_block_flag = 0; |
376 | ||
a4f6c312 | 377 | /* Identify the processor type. */ |
8e3f41e7 | 378 | rs6000_select[0].string = default_cpu; |
3cb999d8 | 379 | rs6000_cpu = TARGET_POWERPC64 ? PROCESSOR_DEFAULT64 : PROCESSOR_DEFAULT; |
8e3f41e7 | 380 | |
b6a1cbae | 381 | for (i = 0; i < ARRAY_SIZE (rs6000_select); i++) |
5248c961 | 382 | { |
8e3f41e7 MM |
383 | ptr = &rs6000_select[i]; |
384 | if (ptr->string != (char *)0 && ptr->string[0] != '\0') | |
5248c961 | 385 | { |
8e3f41e7 MM |
386 | for (j = 0; j < ptt_size; j++) |
387 | if (! strcmp (ptr->string, processor_target_table[j].name)) | |
388 | { | |
389 | if (ptr->set_tune_p) | |
390 | rs6000_cpu = processor_target_table[j].processor; | |
391 | ||
392 | if (ptr->set_arch_p) | |
393 | { | |
394 | target_flags |= processor_target_table[j].target_enable; | |
395 | target_flags &= ~processor_target_table[j].target_disable; | |
396 | } | |
397 | break; | |
398 | } | |
399 | ||
4406229e | 400 | if (j == ptt_size) |
8e3f41e7 | 401 | error ("bad value (%s) for %s switch", ptr->string, ptr->name); |
5248c961 RK |
402 | } |
403 | } | |
8a61d227 | 404 | |
a4f6c312 SS |
405 | /* If we are optimizing big endian systems for space, use the store |
406 | multiple instructions. */ | |
ef792183 MM |
407 | if (BYTES_BIG_ENDIAN && optimize_size) |
408 | target_flags |= MASK_MULTIPLE; | |
409 | ||
8a61d227 MM |
410 | /* If -mmultiple or -mno-multiple was explicitly used, don't |
411 | override with the processor default */ | |
412 | if (TARGET_MULTIPLE_SET) | |
413 | target_flags = (target_flags & ~MASK_MULTIPLE) | multiple; | |
7e69e155 | 414 | |
a4f6c312 SS |
415 | /* If -mstring or -mno-string was explicitly used, don't override |
416 | with the processor default. */ | |
938937d8 | 417 | if (TARGET_STRING_SET) |
1f5515bf | 418 | target_flags = (target_flags & ~MASK_STRING) | string; |
938937d8 | 419 | |
a4f6c312 SS |
420 | /* Don't allow -mmultiple or -mstring on little endian systems |
421 | unless the cpu is a 750, because the hardware doesn't support the | |
422 | instructions used in little endian mode, and causes an alignment | |
423 | trap. The 750 does not cause an alignment trap (except when the | |
424 | target is unaligned). */ | |
bef84347 | 425 | |
bfc79d3b | 426 | if (! BYTES_BIG_ENDIAN && rs6000_cpu != PROCESSOR_PPC750) |
7e69e155 MM |
427 | { |
428 | if (TARGET_MULTIPLE) | |
429 | { | |
430 | target_flags &= ~MASK_MULTIPLE; | |
431 | if (TARGET_MULTIPLE_SET) | |
432 | warning ("-mmultiple is not supported on little endian systems"); | |
433 | } | |
434 | ||
435 | if (TARGET_STRING) | |
436 | { | |
437 | target_flags &= ~MASK_STRING; | |
938937d8 MM |
438 | if (TARGET_STRING_SET) |
439 | warning ("-mstring is not supported on little endian systems"); | |
7e69e155 MM |
440 | } |
441 | } | |
3933e0e1 | 442 | |
2bfcf297 | 443 | if (flag_pic && DEFAULT_ABI == ABI_AIX) |
a260abc9 | 444 | { |
2bfcf297 | 445 | warning ("-f%s ignored (all code is position independent)", |
a260abc9 DE |
446 | (flag_pic > 1) ? "PIC" : "pic"); |
447 | flag_pic = 0; | |
448 | } | |
449 | ||
2bfcf297 | 450 | #ifdef XCOFF_DEBUGGING_INFO |
9861b0c9 | 451 | if (flag_function_sections && (write_symbols != NO_DEBUG) |
2bfcf297 | 452 | && DEFAULT_ABI == ABI_AIX) |
9861b0c9 DE |
453 | { |
454 | warning ("-ffunction-sections disabled on AIX when debugging"); | |
455 | flag_function_sections = 0; | |
456 | } | |
457 | ||
458 | if (flag_data_sections && (DEFAULT_ABI == ABI_AIX)) | |
459 | { | |
460 | warning ("-fdata-sections not supported on AIX"); | |
461 | flag_data_sections = 0; | |
462 | } | |
2bfcf297 | 463 | #endif |
9861b0c9 | 464 | |
38c1f2d7 MM |
465 | /* Set debug flags */ |
466 | if (rs6000_debug_name) | |
467 | { | |
bfc79d3b | 468 | if (! strcmp (rs6000_debug_name, "all")) |
38c1f2d7 | 469 | rs6000_debug_stack = rs6000_debug_arg = 1; |
bfc79d3b | 470 | else if (! strcmp (rs6000_debug_name, "stack")) |
38c1f2d7 | 471 | rs6000_debug_stack = 1; |
bfc79d3b | 472 | else if (! strcmp (rs6000_debug_name, "arg")) |
38c1f2d7 MM |
473 | rs6000_debug_arg = 1; |
474 | else | |
475 | error ("Unknown -mdebug-%s switch", rs6000_debug_name); | |
476 | } | |
477 | ||
0ac081f6 AH |
478 | /* Handle -mabi= options. */ |
479 | rs6000_parse_abi_options (); | |
480 | ||
c81bebd7 | 481 | #ifdef TARGET_REGNAMES |
a4f6c312 SS |
482 | /* If the user desires alternate register names, copy in the |
483 | alternate names now. */ | |
c81bebd7 | 484 | if (TARGET_REGNAMES) |
4e135bdd | 485 | memcpy (rs6000_reg_names, alt_reg_names, sizeof (rs6000_reg_names)); |
c81bebd7 MM |
486 | #endif |
487 | ||
3933e0e1 MM |
488 | #ifdef SUBTARGET_OVERRIDE_OPTIONS |
489 | SUBTARGET_OVERRIDE_OPTIONS; | |
490 | #endif | |
c8023011 MM |
491 | |
492 | /* Register global variables with the garbage collector. */ | |
493 | rs6000_add_gc_roots (); | |
9ebbca7d GK |
494 | |
495 | /* Allocate an alias set for register saves & restores from stack. */ | |
496 | rs6000_sr_alias_set = new_alias_set (); | |
497 | ||
498 | if (TARGET_TOC) | |
499 | ASM_GENERATE_INTERNAL_LABEL (toc_label_name, "LCTOC", 1); | |
71f123ca FS |
500 | |
501 | /* Arrange to save and restore machine status around nested functions. */ | |
502 | init_machine_status = rs6000_init_machine_status; | |
71f123ca | 503 | free_machine_status = rs6000_free_machine_status; |
5248c961 | 504 | } |
5accd822 | 505 | |
0ac081f6 | 506 | /* Handle -mabi= options. */ |
00b960c7 AH |
507 | static void |
508 | rs6000_parse_abi_options () | |
0ac081f6 AH |
509 | { |
510 | if (rs6000_abi_string == 0) | |
511 | return; | |
512 | else if (! strcmp (rs6000_abi_string, "altivec")) | |
513 | target_flags |= MASK_ALTIVEC_ABI; | |
514 | else | |
515 | error ("Unknown ABI specified: '%s'", rs6000_abi_string); | |
516 | } | |
517 | ||
5accd822 DE |
518 | void |
519 | optimization_options (level, size) | |
e2c953b6 | 520 | int level ATTRIBUTE_UNUSED; |
5accd822 DE |
521 | int size ATTRIBUTE_UNUSED; |
522 | { | |
5accd822 | 523 | } |
3cfa4909 MM |
524 | \f |
525 | /* Do anything needed at the start of the asm file. */ | |
526 | ||
527 | void | |
528 | rs6000_file_start (file, default_cpu) | |
529 | FILE *file; | |
d330fd93 | 530 | const char *default_cpu; |
3cfa4909 | 531 | { |
c4d38ccb | 532 | size_t i; |
3cfa4909 | 533 | char buffer[80]; |
d330fd93 | 534 | const char *start = buffer; |
3cfa4909 MM |
535 | struct rs6000_cpu_select *ptr; |
536 | ||
537 | if (flag_verbose_asm) | |
538 | { | |
539 | sprintf (buffer, "\n%s rs6000/powerpc options:", ASM_COMMENT_START); | |
540 | rs6000_select[0].string = default_cpu; | |
541 | ||
b6a1cbae | 542 | for (i = 0; i < ARRAY_SIZE (rs6000_select); i++) |
3cfa4909 MM |
543 | { |
544 | ptr = &rs6000_select[i]; | |
545 | if (ptr->string != (char *)0 && ptr->string[0] != '\0') | |
546 | { | |
547 | fprintf (file, "%s %s%s", start, ptr->name, ptr->string); | |
548 | start = ""; | |
549 | } | |
550 | } | |
551 | ||
b91da81f | 552 | #ifdef USING_ELFOS_H |
3cfa4909 MM |
553 | switch (rs6000_sdata) |
554 | { | |
555 | case SDATA_NONE: fprintf (file, "%s -msdata=none", start); start = ""; break; | |
556 | case SDATA_DATA: fprintf (file, "%s -msdata=data", start); start = ""; break; | |
557 | case SDATA_SYSV: fprintf (file, "%s -msdata=sysv", start); start = ""; break; | |
558 | case SDATA_EABI: fprintf (file, "%s -msdata=eabi", start); start = ""; break; | |
559 | } | |
560 | ||
561 | if (rs6000_sdata && g_switch_value) | |
562 | { | |
563 | fprintf (file, "%s -G %d", start, g_switch_value); | |
564 | start = ""; | |
565 | } | |
566 | #endif | |
567 | ||
568 | if (*start == '\0') | |
949ea356 | 569 | putc ('\n', file); |
3cfa4909 MM |
570 | } |
571 | } | |
572 | ||
24d304eb RK |
573 | \f |
574 | /* Create a CONST_DOUBLE from a string. */ | |
575 | ||
576 | struct rtx_def * | |
577 | rs6000_float_const (string, mode) | |
d330fd93 | 578 | const char *string; |
24d304eb RK |
579 | enum machine_mode mode; |
580 | { | |
ca5adc63 GK |
581 | REAL_VALUE_TYPE value; |
582 | value = REAL_VALUE_ATOF (string, mode); | |
24d304eb RK |
583 | return immed_real_const_1 (value, mode); |
584 | } | |
5248c961 | 585 | \f |
9878760c RK |
586 | /* Return non-zero if this function is known to have a null epilogue. */ |
587 | ||
588 | int | |
589 | direct_return () | |
590 | { | |
4697a36c MM |
591 | if (reload_completed) |
592 | { | |
593 | rs6000_stack_t *info = rs6000_stack_info (); | |
594 | ||
595 | if (info->first_gp_reg_save == 32 | |
596 | && info->first_fp_reg_save == 64 | |
00b960c7 | 597 | && info->first_altivec_reg_save == LAST_ALTIVEC_REGNO + 1 |
c81fc13e DE |
598 | && ! info->lr_save_p |
599 | && ! info->cr_save_p | |
00b960c7 | 600 | && info->vrsave_mask == 0 |
c81fc13e | 601 | && ! info->push_p) |
4697a36c MM |
602 | return 1; |
603 | } | |
604 | ||
605 | return 0; | |
9878760c RK |
606 | } |
607 | ||
608 | /* Returns 1 always. */ | |
609 | ||
610 | int | |
611 | any_operand (op, mode) | |
592696dd | 612 | rtx op ATTRIBUTE_UNUSED; |
296b8152 | 613 | enum machine_mode mode ATTRIBUTE_UNUSED; |
9878760c RK |
614 | { |
615 | return 1; | |
616 | } | |
617 | ||
a4f6c312 | 618 | /* Returns 1 if op is the count register. */ |
38c1f2d7 | 619 | int |
a4f6c312 | 620 | count_register_operand (op, mode) |
592696dd | 621 | rtx op; |
296b8152 | 622 | enum machine_mode mode ATTRIBUTE_UNUSED; |
b6c9286a MM |
623 | { |
624 | if (GET_CODE (op) != REG) | |
625 | return 0; | |
626 | ||
627 | if (REGNO (op) == COUNT_REGISTER_REGNUM) | |
628 | return 1; | |
629 | ||
630 | if (REGNO (op) > FIRST_PSEUDO_REGISTER) | |
631 | return 1; | |
632 | ||
633 | return 0; | |
634 | } | |
635 | ||
38c1f2d7 | 636 | int |
a4f6c312 | 637 | xer_operand (op, mode) |
592696dd | 638 | rtx op; |
296b8152 | 639 | enum machine_mode mode ATTRIBUTE_UNUSED; |
802a0058 MM |
640 | { |
641 | if (GET_CODE (op) != REG) | |
642 | return 0; | |
643 | ||
9ebbca7d | 644 | if (XER_REGNO_P (REGNO (op))) |
802a0058 MM |
645 | return 1; |
646 | ||
802a0058 MM |
647 | return 0; |
648 | } | |
649 | ||
9878760c RK |
650 | /* Return 1 if OP is a constant that can fit in a D field. */ |
651 | ||
652 | int | |
653 | short_cint_operand (op, mode) | |
592696dd | 654 | rtx op; |
296b8152 | 655 | enum machine_mode mode ATTRIBUTE_UNUSED; |
9878760c | 656 | { |
5f59ecb7 DE |
657 | return (GET_CODE (op) == CONST_INT |
658 | && CONST_OK_FOR_LETTER_P (INTVAL (op), 'I')); | |
9878760c RK |
659 | } |
660 | ||
5519a4f9 | 661 | /* Similar for an unsigned D field. */ |
9878760c RK |
662 | |
663 | int | |
664 | u_short_cint_operand (op, mode) | |
592696dd | 665 | rtx op; |
296b8152 | 666 | enum machine_mode mode ATTRIBUTE_UNUSED; |
9878760c | 667 | { |
19684119 | 668 | return (GET_CODE (op) == CONST_INT |
5f59ecb7 | 669 | && CONST_OK_FOR_LETTER_P (INTVAL (op), 'K')); |
9878760c RK |
670 | } |
671 | ||
dcfedcd0 RK |
672 | /* Return 1 if OP is a CONST_INT that cannot fit in a signed D field. */ |
673 | ||
674 | int | |
675 | non_short_cint_operand (op, mode) | |
592696dd | 676 | rtx op; |
296b8152 | 677 | enum machine_mode mode ATTRIBUTE_UNUSED; |
dcfedcd0 RK |
678 | { |
679 | return (GET_CODE (op) == CONST_INT | |
a7653a2c | 680 | && (unsigned HOST_WIDE_INT) (INTVAL (op) + 0x8000) >= 0x10000); |
dcfedcd0 RK |
681 | } |
682 | ||
2bfcf297 DB |
683 | /* Returns 1 if OP is a CONST_INT that is a positive value |
684 | and an exact power of 2. */ | |
685 | ||
686 | int | |
687 | exact_log2_cint_operand (op, mode) | |
592696dd | 688 | rtx op; |
2bfcf297 DB |
689 | enum machine_mode mode ATTRIBUTE_UNUSED; |
690 | { | |
691 | return (GET_CODE (op) == CONST_INT | |
692 | && INTVAL (op) > 0 | |
693 | && exact_log2 (INTVAL (op)) >= 0); | |
694 | } | |
695 | ||
9878760c RK |
696 | /* Returns 1 if OP is a register that is not special (i.e., not MQ, |
697 | ctr, or lr). */ | |
698 | ||
699 | int | |
cd2b37d9 | 700 | gpc_reg_operand (op, mode) |
592696dd | 701 | rtx op; |
9878760c RK |
702 | enum machine_mode mode; |
703 | { | |
704 | return (register_operand (op, mode) | |
802a0058 | 705 | && (GET_CODE (op) != REG |
9ebbca7d GK |
706 | || (REGNO (op) >= ARG_POINTER_REGNUM |
707 | && !XER_REGNO_P (REGNO (op))) | |
708 | || REGNO (op) < MQ_REGNO)); | |
9878760c RK |
709 | } |
710 | ||
711 | /* Returns 1 if OP is either a pseudo-register or a register denoting a | |
712 | CR field. */ | |
713 | ||
714 | int | |
715 | cc_reg_operand (op, mode) | |
592696dd | 716 | rtx op; |
9878760c RK |
717 | enum machine_mode mode; |
718 | { | |
719 | return (register_operand (op, mode) | |
720 | && (GET_CODE (op) != REG | |
721 | || REGNO (op) >= FIRST_PSEUDO_REGISTER | |
722 | || CR_REGNO_P (REGNO (op)))); | |
723 | } | |
724 | ||
815cdc52 MM |
725 | /* Returns 1 if OP is either a pseudo-register or a register denoting a |
726 | CR field that isn't CR0. */ | |
727 | ||
728 | int | |
729 | cc_reg_not_cr0_operand (op, mode) | |
592696dd | 730 | rtx op; |
815cdc52 MM |
731 | enum machine_mode mode; |
732 | { | |
733 | return (register_operand (op, mode) | |
734 | && (GET_CODE (op) != REG | |
735 | || REGNO (op) >= FIRST_PSEUDO_REGISTER | |
736 | || CR_REGNO_NOT_CR0_P (REGNO (op)))); | |
737 | } | |
738 | ||
a4f6c312 SS |
739 | /* Returns 1 if OP is either a constant integer valid for a D-field or |
740 | a non-special register. If a register, it must be in the proper | |
741 | mode unless MODE is VOIDmode. */ | |
9878760c RK |
742 | |
743 | int | |
744 | reg_or_short_operand (op, mode) | |
592696dd | 745 | rtx op; |
9878760c RK |
746 | enum machine_mode mode; |
747 | { | |
f5a28898 | 748 | return short_cint_operand (op, mode) || gpc_reg_operand (op, mode); |
9878760c RK |
749 | } |
750 | ||
a4f6c312 SS |
751 | /* Similar, except check if the negation of the constant would be |
752 | valid for a D-field. */ | |
9878760c RK |
753 | |
754 | int | |
755 | reg_or_neg_short_operand (op, mode) | |
592696dd | 756 | rtx op; |
9878760c RK |
757 | enum machine_mode mode; |
758 | { | |
759 | if (GET_CODE (op) == CONST_INT) | |
760 | return CONST_OK_FOR_LETTER_P (INTVAL (op), 'P'); | |
761 | ||
cd2b37d9 | 762 | return gpc_reg_operand (op, mode); |
9878760c RK |
763 | } |
764 | ||
a4f6c312 SS |
765 | /* Return 1 if the operand is either a register or an integer whose |
766 | high-order 16 bits are zero. */ | |
9878760c RK |
767 | |
768 | int | |
769 | reg_or_u_short_operand (op, mode) | |
592696dd | 770 | rtx op; |
9878760c RK |
771 | enum machine_mode mode; |
772 | { | |
e675f625 | 773 | return u_short_cint_operand (op, mode) || gpc_reg_operand (op, mode); |
9878760c RK |
774 | } |
775 | ||
776 | /* Return 1 is the operand is either a non-special register or ANY | |
777 | constant integer. */ | |
778 | ||
779 | int | |
780 | reg_or_cint_operand (op, mode) | |
592696dd | 781 | rtx op; |
9878760c RK |
782 | enum machine_mode mode; |
783 | { | |
a4f6c312 | 784 | return (GET_CODE (op) == CONST_INT || gpc_reg_operand (op, mode)); |
f6bf7de2 DE |
785 | } |
786 | ||
787 | /* Return 1 is the operand is either a non-special register or ANY | |
788 | 32-bit signed constant integer. */ | |
789 | ||
790 | int | |
791 | reg_or_arith_cint_operand (op, mode) | |
592696dd | 792 | rtx op; |
f6bf7de2 DE |
793 | enum machine_mode mode; |
794 | { | |
a4f6c312 SS |
795 | return (gpc_reg_operand (op, mode) |
796 | || (GET_CODE (op) == CONST_INT | |
f6bf7de2 | 797 | #if HOST_BITS_PER_WIDE_INT != 32 |
a4f6c312 SS |
798 | && ((unsigned HOST_WIDE_INT) (INTVAL (op) + 0x80000000) |
799 | < (unsigned HOST_WIDE_INT) 0x100000000ll) | |
f6bf7de2 | 800 | #endif |
a4f6c312 | 801 | )); |
9878760c RK |
802 | } |
803 | ||
2bfcf297 DB |
804 | /* Return 1 is the operand is either a non-special register or a 32-bit |
805 | signed constant integer valid for 64-bit addition. */ | |
806 | ||
807 | int | |
808 | reg_or_add_cint64_operand (op, mode) | |
592696dd | 809 | rtx op; |
2bfcf297 DB |
810 | enum machine_mode mode; |
811 | { | |
a4f6c312 SS |
812 | return (gpc_reg_operand (op, mode) |
813 | || (GET_CODE (op) == CONST_INT | |
814 | && INTVAL (op) < 0x7fff8000 | |
2bfcf297 | 815 | #if HOST_BITS_PER_WIDE_INT != 32 |
a4f6c312 SS |
816 | && ((unsigned HOST_WIDE_INT) (INTVAL (op) + 0x80008000) |
817 | < 0x100000000ll) | |
2bfcf297 | 818 | #endif |
a4f6c312 | 819 | )); |
2bfcf297 DB |
820 | } |
821 | ||
822 | /* Return 1 is the operand is either a non-special register or a 32-bit | |
823 | signed constant integer valid for 64-bit subtraction. */ | |
824 | ||
825 | int | |
826 | reg_or_sub_cint64_operand (op, mode) | |
592696dd | 827 | rtx op; |
2bfcf297 DB |
828 | enum machine_mode mode; |
829 | { | |
a4f6c312 SS |
830 | return (gpc_reg_operand (op, mode) |
831 | || (GET_CODE (op) == CONST_INT | |
832 | && (- INTVAL (op)) < 0x7fff8000 | |
2bfcf297 | 833 | #if HOST_BITS_PER_WIDE_INT != 32 |
a4f6c312 SS |
834 | && ((unsigned HOST_WIDE_INT) ((- INTVAL (op)) + 0x80008000) |
835 | < 0x100000000ll) | |
2bfcf297 | 836 | #endif |
a4f6c312 | 837 | )); |
2bfcf297 DB |
838 | } |
839 | ||
9ebbca7d GK |
840 | /* Return 1 is the operand is either a non-special register or ANY |
841 | 32-bit unsigned constant integer. */ | |
842 | ||
843 | int | |
1d328b19 | 844 | reg_or_logical_cint_operand (op, mode) |
592696dd | 845 | rtx op; |
9ebbca7d GK |
846 | enum machine_mode mode; |
847 | { | |
1d328b19 GK |
848 | if (GET_CODE (op) == CONST_INT) |
849 | { | |
850 | if (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT) | |
851 | { | |
852 | if (GET_MODE_BITSIZE (mode) <= 32) | |
a4f6c312 | 853 | abort (); |
1d328b19 GK |
854 | |
855 | if (INTVAL (op) < 0) | |
856 | return 0; | |
857 | } | |
858 | ||
859 | return ((INTVAL (op) & GET_MODE_MASK (mode) | |
0858c623 | 860 | & (~ (unsigned HOST_WIDE_INT) 0xffffffff)) == 0); |
1d328b19 GK |
861 | } |
862 | else if (GET_CODE (op) == CONST_DOUBLE) | |
863 | { | |
864 | if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT | |
865 | || mode != DImode) | |
a4f6c312 | 866 | abort (); |
1d328b19 GK |
867 | |
868 | return CONST_DOUBLE_HIGH (op) == 0; | |
869 | } | |
870 | else | |
871 | return gpc_reg_operand (op, mode); | |
9ebbca7d GK |
872 | } |
873 | ||
51d3e7d6 | 874 | /* Return 1 if the operand is an operand that can be loaded via the GOT. */ |
766a866c MM |
875 | |
876 | int | |
877 | got_operand (op, mode) | |
592696dd | 878 | rtx op; |
296b8152 | 879 | enum machine_mode mode ATTRIBUTE_UNUSED; |
766a866c MM |
880 | { |
881 | return (GET_CODE (op) == SYMBOL_REF | |
882 | || GET_CODE (op) == CONST | |
883 | || GET_CODE (op) == LABEL_REF); | |
884 | } | |
885 | ||
38c1f2d7 MM |
886 | /* Return 1 if the operand is a simple references that can be loaded via |
887 | the GOT (labels involving addition aren't allowed). */ | |
888 | ||
889 | int | |
890 | got_no_const_operand (op, mode) | |
592696dd | 891 | rtx op; |
296b8152 | 892 | enum machine_mode mode ATTRIBUTE_UNUSED; |
38c1f2d7 MM |
893 | { |
894 | return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF); | |
895 | } | |
896 | ||
4e74d8ec MM |
897 | /* Return the number of instructions it takes to form a constant in an |
898 | integer register. */ | |
899 | ||
900 | static int | |
901 | num_insns_constant_wide (value) | |
902 | HOST_WIDE_INT value; | |
903 | { | |
904 | /* signed constant loadable with {cal|addi} */ | |
5f59ecb7 | 905 | if (CONST_OK_FOR_LETTER_P (value, 'I')) |
0865c631 GK |
906 | return 1; |
907 | ||
4e74d8ec | 908 | /* constant loadable with {cau|addis} */ |
5f59ecb7 | 909 | else if (CONST_OK_FOR_LETTER_P (value, 'L')) |
4e74d8ec MM |
910 | return 1; |
911 | ||
5f59ecb7 | 912 | #if HOST_BITS_PER_WIDE_INT == 64 |
c81fc13e | 913 | else if (TARGET_POWERPC64) |
4e74d8ec | 914 | { |
0d30d435 | 915 | HOST_WIDE_INT low = value & 0xffffffff; |
4e74d8ec MM |
916 | HOST_WIDE_INT high = value >> 32; |
917 | ||
0d30d435 DE |
918 | low = (low ^ 0x80000000) - 0x80000000; /* sign extend */ |
919 | ||
0858c623 | 920 | if (high == 0 && (low & 0x80000000) == 0) |
4e74d8ec MM |
921 | return 2; |
922 | ||
0858c623 | 923 | else if (high == -1 && (low & 0x80000000) != 0) |
4e74d8ec MM |
924 | return 2; |
925 | ||
c81fc13e | 926 | else if (! low) |
4e74d8ec MM |
927 | return num_insns_constant_wide (high) + 1; |
928 | ||
929 | else | |
930 | return (num_insns_constant_wide (high) | |
e396202a | 931 | + num_insns_constant_wide (low) + 1); |
4e74d8ec MM |
932 | } |
933 | #endif | |
934 | ||
935 | else | |
936 | return 2; | |
937 | } | |
938 | ||
939 | int | |
940 | num_insns_constant (op, mode) | |
941 | rtx op; | |
942 | enum machine_mode mode; | |
943 | { | |
4e74d8ec | 944 | if (GET_CODE (op) == CONST_INT) |
0d30d435 DE |
945 | { |
946 | #if HOST_BITS_PER_WIDE_INT == 64 | |
4e2c1c44 DE |
947 | if ((INTVAL (op) >> 31) != 0 && (INTVAL (op) >> 31) != -1 |
948 | && mask64_operand (op, mode)) | |
0d30d435 DE |
949 | return 2; |
950 | else | |
951 | #endif | |
952 | return num_insns_constant_wide (INTVAL (op)); | |
953 | } | |
4e74d8ec | 954 | |
6fc48950 MM |
955 | else if (GET_CODE (op) == CONST_DOUBLE && mode == SFmode) |
956 | { | |
957 | long l; | |
958 | REAL_VALUE_TYPE rv; | |
959 | ||
960 | REAL_VALUE_FROM_CONST_DOUBLE (rv, op); | |
961 | REAL_VALUE_TO_TARGET_SINGLE (rv, l); | |
962 | return num_insns_constant_wide ((HOST_WIDE_INT)l); | |
963 | } | |
964 | ||
47ad8c61 | 965 | else if (GET_CODE (op) == CONST_DOUBLE) |
4e74d8ec | 966 | { |
47ad8c61 MM |
967 | HOST_WIDE_INT low; |
968 | HOST_WIDE_INT high; | |
969 | long l[2]; | |
970 | REAL_VALUE_TYPE rv; | |
971 | int endian = (WORDS_BIG_ENDIAN == 0); | |
4e74d8ec | 972 | |
47ad8c61 MM |
973 | if (mode == VOIDmode || mode == DImode) |
974 | { | |
975 | high = CONST_DOUBLE_HIGH (op); | |
976 | low = CONST_DOUBLE_LOW (op); | |
977 | } | |
978 | else | |
979 | { | |
980 | REAL_VALUE_FROM_CONST_DOUBLE (rv, op); | |
981 | REAL_VALUE_TO_TARGET_DOUBLE (rv, l); | |
982 | high = l[endian]; | |
983 | low = l[1 - endian]; | |
984 | } | |
4e74d8ec | 985 | |
47ad8c61 MM |
986 | if (TARGET_32BIT) |
987 | return (num_insns_constant_wide (low) | |
988 | + num_insns_constant_wide (high)); | |
4e74d8ec MM |
989 | |
990 | else | |
47ad8c61 | 991 | { |
0858c623 | 992 | if (high == 0 && (low & 0x80000000) == 0) |
47ad8c61 MM |
993 | return num_insns_constant_wide (low); |
994 | ||
0858c623 | 995 | else if (high == -1 && (low & 0x80000000) != 0) |
47ad8c61 MM |
996 | return num_insns_constant_wide (low); |
997 | ||
a260abc9 DE |
998 | else if (mask64_operand (op, mode)) |
999 | return 2; | |
1000 | ||
47ad8c61 MM |
1001 | else if (low == 0) |
1002 | return num_insns_constant_wide (high) + 1; | |
1003 | ||
1004 | else | |
1005 | return (num_insns_constant_wide (high) | |
1006 | + num_insns_constant_wide (low) + 1); | |
1007 | } | |
4e74d8ec MM |
1008 | } |
1009 | ||
1010 | else | |
1011 | abort (); | |
1012 | } | |
1013 | ||
a4f6c312 SS |
1014 | /* Return 1 if the operand is a CONST_DOUBLE and it can be put into a |
1015 | register with one instruction per word. We only do this if we can | |
1016 | safely read CONST_DOUBLE_{LOW,HIGH}. */ | |
9878760c RK |
1017 | |
1018 | int | |
1019 | easy_fp_constant (op, mode) | |
592696dd SS |
1020 | rtx op; |
1021 | enum machine_mode mode; | |
9878760c | 1022 | { |
9878760c RK |
1023 | if (GET_CODE (op) != CONST_DOUBLE |
1024 | || GET_MODE (op) != mode | |
4e74d8ec | 1025 | || (GET_MODE_CLASS (mode) != MODE_FLOAT && mode != DImode)) |
9878760c RK |
1026 | return 0; |
1027 | ||
a4f6c312 | 1028 | /* Consider all constants with -msoft-float to be easy. */ |
4e74d8ec | 1029 | if (TARGET_SOFT_FLOAT && mode != DImode) |
b6c9286a MM |
1030 | return 1; |
1031 | ||
a4f6c312 | 1032 | /* If we are using V.4 style PIC, consider all constants to be hard. */ |
f607bc57 | 1033 | if (flag_pic && DEFAULT_ABI == ABI_V4) |
a7273471 MM |
1034 | return 0; |
1035 | ||
5ae4759c | 1036 | #ifdef TARGET_RELOCATABLE |
a4f6c312 SS |
1037 | /* Similarly if we are using -mrelocatable, consider all constants |
1038 | to be hard. */ | |
5ae4759c MM |
1039 | if (TARGET_RELOCATABLE) |
1040 | return 0; | |
1041 | #endif | |
1042 | ||
042259f2 DE |
1043 | if (mode == DFmode) |
1044 | { | |
1045 | long k[2]; | |
1046 | REAL_VALUE_TYPE rv; | |
1047 | ||
1048 | REAL_VALUE_FROM_CONST_DOUBLE (rv, op); | |
1049 | REAL_VALUE_TO_TARGET_DOUBLE (rv, k); | |
9878760c | 1050 | |
4e74d8ec MM |
1051 | return (num_insns_constant_wide ((HOST_WIDE_INT)k[0]) == 1 |
1052 | && num_insns_constant_wide ((HOST_WIDE_INT)k[1]) == 1); | |
042259f2 | 1053 | } |
4e74d8ec MM |
1054 | |
1055 | else if (mode == SFmode) | |
042259f2 DE |
1056 | { |
1057 | long l; | |
1058 | REAL_VALUE_TYPE rv; | |
1059 | ||
1060 | REAL_VALUE_FROM_CONST_DOUBLE (rv, op); | |
1061 | REAL_VALUE_TO_TARGET_SINGLE (rv, l); | |
9878760c | 1062 | |
4e74d8ec | 1063 | return num_insns_constant_wide (l) == 1; |
042259f2 | 1064 | } |
4e74d8ec | 1065 | |
a260abc9 | 1066 | else if (mode == DImode) |
c81fc13e | 1067 | return ((TARGET_POWERPC64 |
a260abc9 DE |
1068 | && GET_CODE (op) == CONST_DOUBLE && CONST_DOUBLE_LOW (op) == 0) |
1069 | || (num_insns_constant (op, DImode) <= 2)); | |
4e74d8ec | 1070 | |
a9098fd0 GK |
1071 | else if (mode == SImode) |
1072 | return 1; | |
4e74d8ec MM |
1073 | else |
1074 | abort (); | |
9878760c | 1075 | } |
8f75773e | 1076 | |
50a0b056 GK |
1077 | /* Return 1 if the operand is 0.0. */ |
1078 | int | |
1079 | zero_fp_constant (op, mode) | |
592696dd SS |
1080 | rtx op; |
1081 | enum machine_mode mode; | |
50a0b056 GK |
1082 | { |
1083 | return GET_MODE_CLASS (mode) == MODE_FLOAT && op == CONST0_RTX (mode); | |
1084 | } | |
1085 | ||
a4f6c312 SS |
1086 | /* Return 1 if the operand is in volatile memory. Note that during |
1087 | the RTL generation phase, memory_operand does not return TRUE for | |
b6c9286a MM |
1088 | volatile memory references. So this function allows us to |
1089 | recognize volatile references where its safe. */ | |
1090 | ||
1091 | int | |
1092 | volatile_mem_operand (op, mode) | |
592696dd | 1093 | rtx op; |
b6c9286a MM |
1094 | enum machine_mode mode; |
1095 | { | |
1096 | if (GET_CODE (op) != MEM) | |
1097 | return 0; | |
1098 | ||
1099 | if (!MEM_VOLATILE_P (op)) | |
1100 | return 0; | |
1101 | ||
1102 | if (mode != GET_MODE (op)) | |
1103 | return 0; | |
1104 | ||
1105 | if (reload_completed) | |
1106 | return memory_operand (op, mode); | |
1107 | ||
1108 | if (reload_in_progress) | |
1109 | return strict_memory_address_p (mode, XEXP (op, 0)); | |
1110 | ||
1111 | return memory_address_p (mode, XEXP (op, 0)); | |
1112 | } | |
1113 | ||
97f6e72f | 1114 | /* Return 1 if the operand is an offsettable memory operand. */ |
914c2e77 RK |
1115 | |
1116 | int | |
97f6e72f | 1117 | offsettable_mem_operand (op, mode) |
592696dd | 1118 | rtx op; |
914c2e77 RK |
1119 | enum machine_mode mode; |
1120 | { | |
97f6e72f | 1121 | return ((GET_CODE (op) == MEM) |
677a9668 | 1122 | && offsettable_address_p (reload_completed || reload_in_progress, |
97f6e72f | 1123 | mode, XEXP (op, 0))); |
914c2e77 RK |
1124 | } |
1125 | ||
9878760c RK |
1126 | /* Return 1 if the operand is either an easy FP constant (see above) or |
1127 | memory. */ | |
1128 | ||
1129 | int | |
1130 | mem_or_easy_const_operand (op, mode) | |
592696dd | 1131 | rtx op; |
9878760c RK |
1132 | enum machine_mode mode; |
1133 | { | |
1134 | return memory_operand (op, mode) || easy_fp_constant (op, mode); | |
1135 | } | |
1136 | ||
1137 | /* Return 1 if the operand is either a non-special register or an item | |
5f59ecb7 | 1138 | that can be used as the operand of a `mode' add insn. */ |
9878760c RK |
1139 | |
1140 | int | |
1141 | add_operand (op, mode) | |
592696dd | 1142 | rtx op; |
9878760c RK |
1143 | enum machine_mode mode; |
1144 | { | |
2bfcf297 DB |
1145 | if (GET_CODE (op) == CONST_INT) |
1146 | return (CONST_OK_FOR_LETTER_P (INTVAL(op), 'I') | |
1147 | || CONST_OK_FOR_LETTER_P (INTVAL(op), 'L')); | |
1148 | ||
1149 | return gpc_reg_operand (op, mode); | |
9878760c RK |
1150 | } |
1151 | ||
dcfedcd0 RK |
1152 | /* Return 1 if OP is a constant but not a valid add_operand. */ |
1153 | ||
1154 | int | |
1155 | non_add_cint_operand (op, mode) | |
592696dd | 1156 | rtx op; |
296b8152 | 1157 | enum machine_mode mode ATTRIBUTE_UNUSED; |
dcfedcd0 RK |
1158 | { |
1159 | return (GET_CODE (op) == CONST_INT | |
a7653a2c | 1160 | && (unsigned HOST_WIDE_INT) (INTVAL (op) + 0x8000) >= 0x10000 |
38886f37 | 1161 | && ! CONST_OK_FOR_LETTER_P (INTVAL (op), 'L')); |
dcfedcd0 RK |
1162 | } |
1163 | ||
9878760c RK |
1164 | /* Return 1 if the operand is a non-special register or a constant that |
1165 | can be used as the operand of an OR or XOR insn on the RS/6000. */ | |
1166 | ||
1167 | int | |
1168 | logical_operand (op, mode) | |
592696dd | 1169 | rtx op; |
9878760c RK |
1170 | enum machine_mode mode; |
1171 | { | |
40501e5f | 1172 | HOST_WIDE_INT opl, oph; |
1d328b19 | 1173 | |
dfbdccdb GK |
1174 | if (gpc_reg_operand (op, mode)) |
1175 | return 1; | |
1d328b19 | 1176 | |
dfbdccdb | 1177 | if (GET_CODE (op) == CONST_INT) |
40501e5f AM |
1178 | { |
1179 | opl = INTVAL (op) & GET_MODE_MASK (mode); | |
1180 | ||
1181 | #if HOST_BITS_PER_WIDE_INT <= 32 | |
1182 | if (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT && opl < 0) | |
1183 | return 0; | |
1184 | #endif | |
1185 | } | |
dfbdccdb GK |
1186 | else if (GET_CODE (op) == CONST_DOUBLE) |
1187 | { | |
1d328b19 | 1188 | if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT) |
40501e5f | 1189 | abort (); |
1d328b19 GK |
1190 | |
1191 | opl = CONST_DOUBLE_LOW (op); | |
1192 | oph = CONST_DOUBLE_HIGH (op); | |
40501e5f | 1193 | if (oph != 0) |
38886f37 | 1194 | return 0; |
dfbdccdb GK |
1195 | } |
1196 | else | |
1197 | return 0; | |
1d328b19 | 1198 | |
40501e5f AM |
1199 | return ((opl & ~ (unsigned HOST_WIDE_INT) 0xffff) == 0 |
1200 | || (opl & ~ (unsigned HOST_WIDE_INT) 0xffff0000) == 0); | |
9878760c RK |
1201 | } |
1202 | ||
dcfedcd0 | 1203 | /* Return 1 if C is a constant that is not a logical operand (as |
1d328b19 | 1204 | above), but could be split into one. */ |
dcfedcd0 RK |
1205 | |
1206 | int | |
1207 | non_logical_cint_operand (op, mode) | |
592696dd | 1208 | rtx op; |
5f59ecb7 | 1209 | enum machine_mode mode; |
dcfedcd0 | 1210 | { |
dfbdccdb | 1211 | return ((GET_CODE (op) == CONST_INT || GET_CODE (op) == CONST_DOUBLE) |
1d328b19 GK |
1212 | && ! logical_operand (op, mode) |
1213 | && reg_or_logical_cint_operand (op, mode)); | |
dcfedcd0 RK |
1214 | } |
1215 | ||
19ba8161 | 1216 | /* Return 1 if C is a constant that can be encoded in a 32-bit mask on the |
9878760c RK |
1217 | RS/6000. It is if there are no more than two 1->0 or 0->1 transitions. |
1218 | Reject all ones and all zeros, since these should have been optimized | |
1219 | away and confuse the making of MB and ME. */ | |
1220 | ||
1221 | int | |
19ba8161 | 1222 | mask_operand (op, mode) |
592696dd | 1223 | rtx op; |
19ba8161 | 1224 | enum machine_mode mode ATTRIBUTE_UNUSED; |
9878760c | 1225 | { |
02071907 | 1226 | HOST_WIDE_INT c, lsb; |
9878760c | 1227 | |
19ba8161 DE |
1228 | if (GET_CODE (op) != CONST_INT) |
1229 | return 0; | |
1230 | ||
1231 | c = INTVAL (op); | |
1232 | ||
c5059423 AM |
1233 | /* We don't change the number of transitions by inverting, |
1234 | so make sure we start with the LS bit zero. */ | |
1235 | if (c & 1) | |
1236 | c = ~c; | |
1237 | ||
1238 | /* Reject all zeros or all ones. */ | |
1239 | if (c == 0) | |
9878760c RK |
1240 | return 0; |
1241 | ||
c5059423 AM |
1242 | /* Find the first transition. */ |
1243 | lsb = c & -c; | |
1244 | ||
1245 | /* Invert to look for a second transition. */ | |
1246 | c = ~c; | |
9878760c | 1247 | |
c5059423 AM |
1248 | /* Erase first transition. */ |
1249 | c &= -lsb; | |
9878760c | 1250 | |
c5059423 AM |
1251 | /* Find the second transition (if any). */ |
1252 | lsb = c & -c; | |
1253 | ||
1254 | /* Match if all the bits above are 1's (or c is zero). */ | |
1255 | return c == -lsb; | |
9878760c RK |
1256 | } |
1257 | ||
a260abc9 DE |
1258 | /* Return 1 if the operand is a constant that is a PowerPC64 mask. |
1259 | It is if there are no more than one 1->0 or 0->1 transitions. | |
1260 | Reject all ones and all zeros, since these should have been optimized | |
1261 | away and confuse the making of MB and ME. */ | |
9878760c RK |
1262 | |
1263 | int | |
a260abc9 | 1264 | mask64_operand (op, mode) |
592696dd | 1265 | rtx op; |
a260abc9 DE |
1266 | enum machine_mode mode; |
1267 | { | |
1268 | if (GET_CODE (op) == CONST_INT) | |
1269 | { | |
02071907 | 1270 | HOST_WIDE_INT c, lsb; |
a260abc9 | 1271 | |
c5059423 AM |
1272 | /* We don't change the number of transitions by inverting, |
1273 | so make sure we start with the LS bit zero. */ | |
1274 | c = INTVAL (op); | |
1275 | if (c & 1) | |
1276 | c = ~c; | |
a260abc9 | 1277 | |
c5059423 AM |
1278 | /* Reject all zeros or all ones. */ |
1279 | if (c == 0) | |
e2c953b6 DE |
1280 | return 0; |
1281 | ||
c5059423 AM |
1282 | /* Find the transition, and check that all bits above are 1's. */ |
1283 | lsb = c & -c; | |
1284 | return c == -lsb; | |
e2c953b6 | 1285 | } |
a260abc9 DE |
1286 | else if (GET_CODE (op) == CONST_DOUBLE |
1287 | && (mode == VOIDmode || mode == DImode)) | |
1288 | { | |
02071907 | 1289 | HOST_WIDE_INT low, high, lsb; |
a260abc9 | 1290 | |
c5059423 AM |
1291 | if (HOST_BITS_PER_WIDE_INT < 64) |
1292 | high = CONST_DOUBLE_HIGH (op); | |
a260abc9 | 1293 | |
c5059423 AM |
1294 | low = CONST_DOUBLE_LOW (op); |
1295 | if (low & 1) | |
1296 | { | |
1297 | if (HOST_BITS_PER_WIDE_INT < 64) | |
1298 | high = ~high; | |
1299 | low = ~low; | |
1300 | } | |
a260abc9 | 1301 | |
c5059423 AM |
1302 | if (low == 0) |
1303 | { | |
1304 | if (HOST_BITS_PER_WIDE_INT >= 64 || high == 0) | |
1305 | return 0; | |
a260abc9 | 1306 | |
c5059423 AM |
1307 | lsb = high & -high; |
1308 | return high == -lsb; | |
1309 | } | |
a260abc9 | 1310 | |
c5059423 AM |
1311 | lsb = low & -low; |
1312 | return low == -lsb && (HOST_BITS_PER_WIDE_INT >= 64 || high == ~0); | |
a260abc9 DE |
1313 | } |
1314 | else | |
1315 | return 0; | |
1316 | } | |
1317 | ||
1318 | /* Return 1 if the operand is either a non-special register or a constant | |
1319 | that can be used as the operand of a PowerPC64 logical AND insn. */ | |
1320 | ||
1321 | int | |
1322 | and64_operand (op, mode) | |
592696dd | 1323 | rtx op; |
9878760c RK |
1324 | enum machine_mode mode; |
1325 | { | |
a4f6c312 | 1326 | if (fixed_regs[CR0_REGNO]) /* CR0 not available, don't do andi./andis. */ |
52d3af72 DE |
1327 | return (gpc_reg_operand (op, mode) || mask64_operand (op, mode)); |
1328 | ||
1329 | return (logical_operand (op, mode) || mask64_operand (op, mode)); | |
9878760c RK |
1330 | } |
1331 | ||
a260abc9 DE |
1332 | /* Return 1 if the operand is either a non-special register or a |
1333 | constant that can be used as the operand of an RS/6000 logical AND insn. */ | |
dcfedcd0 RK |
1334 | |
1335 | int | |
a260abc9 | 1336 | and_operand (op, mode) |
592696dd | 1337 | rtx op; |
a260abc9 | 1338 | enum machine_mode mode; |
dcfedcd0 | 1339 | { |
a4f6c312 | 1340 | if (fixed_regs[CR0_REGNO]) /* CR0 not available, don't do andi./andis. */ |
52d3af72 DE |
1341 | return (gpc_reg_operand (op, mode) || mask_operand (op, mode)); |
1342 | ||
1343 | return (logical_operand (op, mode) || mask_operand (op, mode)); | |
dcfedcd0 RK |
1344 | } |
1345 | ||
9878760c RK |
1346 | /* Return 1 if the operand is a general register or memory operand. */ |
1347 | ||
1348 | int | |
1349 | reg_or_mem_operand (op, mode) | |
592696dd SS |
1350 | rtx op; |
1351 | enum machine_mode mode; | |
9878760c | 1352 | { |
b6c9286a MM |
1353 | return (gpc_reg_operand (op, mode) |
1354 | || memory_operand (op, mode) | |
1355 | || volatile_mem_operand (op, mode)); | |
9878760c RK |
1356 | } |
1357 | ||
a7a813f7 | 1358 | /* Return 1 if the operand is a general register or memory operand without |
3cb999d8 | 1359 | pre_inc or pre_dec which produces invalid form of PowerPC lwa |
a7a813f7 RK |
1360 | instruction. */ |
1361 | ||
1362 | int | |
1363 | lwa_operand (op, mode) | |
592696dd SS |
1364 | rtx op; |
1365 | enum machine_mode mode; | |
a7a813f7 RK |
1366 | { |
1367 | rtx inner = op; | |
1368 | ||
1369 | if (reload_completed && GET_CODE (inner) == SUBREG) | |
1370 | inner = SUBREG_REG (inner); | |
1371 | ||
1372 | return gpc_reg_operand (inner, mode) | |
1373 | || (memory_operand (inner, mode) | |
1374 | && GET_CODE (XEXP (inner, 0)) != PRE_INC | |
6a40a9d6 DE |
1375 | && GET_CODE (XEXP (inner, 0)) != PRE_DEC |
1376 | && (GET_CODE (XEXP (inner, 0)) != PLUS | |
e903c96a DE |
1377 | || GET_CODE (XEXP (XEXP (inner, 0), 1)) != CONST_INT |
1378 | || INTVAL (XEXP (XEXP (inner, 0), 1)) % 4 == 0)); | |
a7a813f7 RK |
1379 | } |
1380 | ||
9878760c RK |
1381 | /* Return 1 if the operand, used inside a MEM, is a valid first argument |
1382 | to CALL. This is a SYMBOL_REF or a pseudo-register, which will be | |
1383 | forced to lr. */ | |
1384 | ||
1385 | int | |
1386 | call_operand (op, mode) | |
592696dd | 1387 | rtx op; |
9878760c RK |
1388 | enum machine_mode mode; |
1389 | { | |
1390 | if (mode != VOIDmode && GET_MODE (op) != mode) | |
1391 | return 0; | |
1392 | ||
1393 | return (GET_CODE (op) == SYMBOL_REF | |
1394 | || (GET_CODE (op) == REG && REGNO (op) >= FIRST_PSEUDO_REGISTER)); | |
1395 | } | |
1396 | ||
2af3d377 | 1397 | /* Return 1 if the operand is a SYMBOL_REF for a function known to be in |
a4f6c312 | 1398 | this file and the function is not weakly defined. */ |
2af3d377 RK |
1399 | |
1400 | int | |
1401 | current_file_function_operand (op, mode) | |
592696dd | 1402 | rtx op; |
296b8152 | 1403 | enum machine_mode mode ATTRIBUTE_UNUSED; |
2af3d377 RK |
1404 | { |
1405 | return (GET_CODE (op) == SYMBOL_REF | |
1406 | && (SYMBOL_REF_FLAG (op) | |
8f1b829e | 1407 | || (op == XEXP (DECL_RTL (current_function_decl), 0) |
c81fc13e | 1408 | && ! DECL_WEAK (current_function_decl)))); |
2af3d377 RK |
1409 | } |
1410 | ||
9878760c RK |
1411 | /* Return 1 if this operand is a valid input for a move insn. */ |
1412 | ||
1413 | int | |
1414 | input_operand (op, mode) | |
592696dd | 1415 | rtx op; |
9878760c RK |
1416 | enum machine_mode mode; |
1417 | { | |
eb4e8003 | 1418 | /* Memory is always valid. */ |
9878760c RK |
1419 | if (memory_operand (op, mode)) |
1420 | return 1; | |
1421 | ||
34792e82 | 1422 | /* Only a tiny bit of handling for CONSTANT_P_RTX is necessary. */ |
01b4cf2b | 1423 | if (GET_CODE (op) == CONSTANT_P_RTX) |
34792e82 JL |
1424 | return 1; |
1425 | ||
eb4e8003 RK |
1426 | /* For floating-point, easy constants are valid. */ |
1427 | if (GET_MODE_CLASS (mode) == MODE_FLOAT | |
1428 | && CONSTANT_P (op) | |
1429 | && easy_fp_constant (op, mode)) | |
1430 | return 1; | |
1431 | ||
4e74d8ec MM |
1432 | /* Allow any integer constant. */ |
1433 | if (GET_MODE_CLASS (mode) == MODE_INT | |
e675f625 | 1434 | && (GET_CODE (op) == CONST_INT |
e675f625 | 1435 | || GET_CODE (op) == CONST_DOUBLE)) |
4e74d8ec MM |
1436 | return 1; |
1437 | ||
eb4e8003 RK |
1438 | /* For floating-point or multi-word mode, the only remaining valid type |
1439 | is a register. */ | |
9878760c RK |
1440 | if (GET_MODE_CLASS (mode) == MODE_FLOAT |
1441 | || GET_MODE_SIZE (mode) > UNITS_PER_WORD) | |
eb4e8003 | 1442 | return register_operand (op, mode); |
9878760c | 1443 | |
88fe15a1 RK |
1444 | /* The only cases left are integral modes one word or smaller (we |
1445 | do not get called for MODE_CC values). These can be in any | |
1446 | register. */ | |
1447 | if (register_operand (op, mode)) | |
a8b3aeda | 1448 | return 1; |
88fe15a1 | 1449 | |
84cf9dda | 1450 | /* A SYMBOL_REF referring to the TOC is valid. */ |
7fec4abd | 1451 | if (LEGITIMATE_CONSTANT_POOL_ADDRESS_P (op)) |
84cf9dda RK |
1452 | return 1; |
1453 | ||
9ebbca7d GK |
1454 | /* A constant pool expression (relative to the TOC) is valid */ |
1455 | if (TOC_RELATIVE_EXPR_P (op)) | |
b6c9286a MM |
1456 | return 1; |
1457 | ||
88228c4b MM |
1458 | /* V.4 allows SYMBOL_REFs and CONSTs that are in the small data region |
1459 | to be valid. */ | |
f607bc57 | 1460 | if (DEFAULT_ABI == ABI_V4 |
88228c4b MM |
1461 | && (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST) |
1462 | && small_data_operand (op, Pmode)) | |
1463 | return 1; | |
1464 | ||
042259f2 | 1465 | return 0; |
9878760c | 1466 | } |
7509c759 | 1467 | |
a4f6c312 | 1468 | /* Return 1 for an operand in small memory on V.4/eabi. */ |
7509c759 MM |
1469 | |
1470 | int | |
1471 | small_data_operand (op, mode) | |
296b8152 KG |
1472 | rtx op ATTRIBUTE_UNUSED; |
1473 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
7509c759 | 1474 | { |
38c1f2d7 | 1475 | #if TARGET_ELF |
5f59ecb7 | 1476 | rtx sym_ref; |
7509c759 | 1477 | |
d9407988 | 1478 | if (rs6000_sdata == SDATA_NONE || rs6000_sdata == SDATA_DATA) |
a54d04b7 | 1479 | return 0; |
a54d04b7 | 1480 | |
f607bc57 | 1481 | if (DEFAULT_ABI != ABI_V4) |
7509c759 MM |
1482 | return 0; |
1483 | ||
88228c4b MM |
1484 | if (GET_CODE (op) == SYMBOL_REF) |
1485 | sym_ref = op; | |
1486 | ||
1487 | else if (GET_CODE (op) != CONST | |
1488 | || GET_CODE (XEXP (op, 0)) != PLUS | |
1489 | || GET_CODE (XEXP (XEXP (op, 0), 0)) != SYMBOL_REF | |
1490 | || GET_CODE (XEXP (XEXP (op, 0), 1)) != CONST_INT) | |
7509c759 MM |
1491 | return 0; |
1492 | ||
88228c4b | 1493 | else |
dbf55e53 MM |
1494 | { |
1495 | rtx sum = XEXP (op, 0); | |
1496 | HOST_WIDE_INT summand; | |
1497 | ||
1498 | /* We have to be careful here, because it is the referenced address | |
1499 | that must be 32k from _SDA_BASE_, not just the symbol. */ | |
1500 | summand = INTVAL (XEXP (sum, 1)); | |
1501 | if (summand < 0 || summand > g_switch_value) | |
1502 | return 0; | |
1503 | ||
1504 | sym_ref = XEXP (sum, 0); | |
1505 | } | |
88228c4b MM |
1506 | |
1507 | if (*XSTR (sym_ref, 0) != '@') | |
7509c759 MM |
1508 | return 0; |
1509 | ||
1510 | return 1; | |
d9407988 MM |
1511 | |
1512 | #else | |
1513 | return 0; | |
1514 | #endif | |
7509c759 | 1515 | } |
9ebbca7d GK |
1516 | \f |
1517 | static int | |
1518 | constant_pool_expr_1 (op, have_sym, have_toc) | |
1519 | rtx op; | |
1520 | int *have_sym; | |
1521 | int *have_toc; | |
1522 | { | |
1523 | switch (GET_CODE(op)) | |
1524 | { | |
1525 | case SYMBOL_REF: | |
a4f6c312 SS |
1526 | if (CONSTANT_POOL_ADDRESS_P (op)) |
1527 | { | |
1528 | if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (op), Pmode)) | |
1529 | { | |
1530 | *have_sym = 1; | |
1531 | return 1; | |
1532 | } | |
1533 | else | |
1534 | return 0; | |
1535 | } | |
1536 | else if (! strcmp (XSTR (op, 0), toc_label_name)) | |
1537 | { | |
1538 | *have_toc = 1; | |
1539 | return 1; | |
1540 | } | |
1541 | else | |
1542 | return 0; | |
9ebbca7d GK |
1543 | case PLUS: |
1544 | case MINUS: | |
a4f6c312 SS |
1545 | return constant_pool_expr_1 (XEXP (op, 0), have_sym, have_toc) && |
1546 | constant_pool_expr_1 (XEXP (op, 1), have_sym, have_toc); | |
9ebbca7d | 1547 | case CONST: |
a4f6c312 | 1548 | return constant_pool_expr_1 (XEXP (op, 0), have_sym, have_toc); |
9ebbca7d | 1549 | case CONST_INT: |
a4f6c312 | 1550 | return 1; |
9ebbca7d | 1551 | default: |
a4f6c312 | 1552 | return 0; |
9ebbca7d GK |
1553 | } |
1554 | } | |
1555 | ||
1556 | int | |
1557 | constant_pool_expr_p (op) | |
1558 | rtx op; | |
1559 | { | |
1560 | int have_sym = 0; | |
1561 | int have_toc = 0; | |
1562 | return constant_pool_expr_1 (op, &have_sym, &have_toc) && have_sym; | |
1563 | } | |
1564 | ||
1565 | int | |
1566 | toc_relative_expr_p (op) | |
1567 | rtx op; | |
1568 | { | |
1569 | int have_sym = 0; | |
1570 | int have_toc = 0; | |
1571 | return constant_pool_expr_1 (op, &have_sym, &have_toc) && have_toc; | |
1572 | } | |
1573 | ||
1574 | /* Try machine-dependent ways of modifying an illegitimate address | |
1575 | to be legitimate. If we find one, return the new, valid address. | |
1576 | This is used from only one place: `memory_address' in explow.c. | |
1577 | ||
a4f6c312 SS |
1578 | OLDX is the address as it was before break_out_memory_refs was |
1579 | called. In some cases it is useful to look at this to decide what | |
1580 | needs to be done. | |
9ebbca7d | 1581 | |
a4f6c312 | 1582 | MODE is passed so that this function can use GO_IF_LEGITIMATE_ADDRESS. |
9ebbca7d | 1583 | |
a4f6c312 SS |
1584 | It is always safe for this function to do nothing. It exists to |
1585 | recognize opportunities to optimize the output. | |
9ebbca7d GK |
1586 | |
1587 | On RS/6000, first check for the sum of a register with a constant | |
1588 | integer that is out of range. If so, generate code to add the | |
1589 | constant with the low-order 16 bits masked to the register and force | |
1590 | this result into another register (this can be done with `cau'). | |
1591 | Then generate an address of REG+(CONST&0xffff), allowing for the | |
1592 | possibility of bit 16 being a one. | |
1593 | ||
1594 | Then check for the sum of a register and something not constant, try to | |
1595 | load the other things into a register and return the sum. */ | |
1596 | rtx | |
1597 | rs6000_legitimize_address (x, oldx, mode) | |
1598 | rtx x; | |
1599 | rtx oldx ATTRIBUTE_UNUSED; | |
1600 | enum machine_mode mode; | |
0ac081f6 | 1601 | { |
9ebbca7d GK |
1602 | if (GET_CODE (x) == PLUS |
1603 | && GET_CODE (XEXP (x, 0)) == REG | |
1604 | && GET_CODE (XEXP (x, 1)) == CONST_INT | |
1605 | && (unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 1)) + 0x8000) >= 0x10000) | |
1606 | { | |
1607 | HOST_WIDE_INT high_int, low_int; | |
1608 | rtx sum; | |
1609 | high_int = INTVAL (XEXP (x, 1)) & (~ (HOST_WIDE_INT) 0xffff); | |
1610 | low_int = INTVAL (XEXP (x, 1)) & 0xffff; | |
1611 | if (low_int & 0x8000) | |
1612 | high_int += 0x10000, low_int |= ((HOST_WIDE_INT) -1) << 16; | |
1613 | sum = force_operand (gen_rtx_PLUS (Pmode, XEXP (x, 0), | |
1614 | GEN_INT (high_int)), 0); | |
1615 | return gen_rtx_PLUS (Pmode, sum, GEN_INT (low_int)); | |
1616 | } | |
1617 | else if (GET_CODE (x) == PLUS | |
1618 | && GET_CODE (XEXP (x, 0)) == REG | |
1619 | && GET_CODE (XEXP (x, 1)) != CONST_INT | |
1620 | && (TARGET_HARD_FLOAT || TARGET_POWERPC64 || mode != DFmode) | |
1621 | && (TARGET_POWERPC64 || mode != DImode) | |
1622 | && mode != TImode) | |
1623 | { | |
1624 | return gen_rtx_PLUS (Pmode, XEXP (x, 0), | |
1625 | force_reg (Pmode, force_operand (XEXP (x, 1), 0))); | |
1626 | } | |
0ac081f6 AH |
1627 | else if (ALTIVEC_VECTOR_MODE (mode)) |
1628 | { | |
1629 | rtx reg; | |
1630 | ||
1631 | /* Make sure both operands are registers. */ | |
1632 | if (GET_CODE (x) == PLUS) | |
1633 | return gen_rtx_PLUS (Pmode, XEXP (x, 0), | |
1634 | force_reg (Pmode, XEXP (x, 1))); | |
1635 | ||
1636 | reg = force_reg (Pmode, x); | |
1637 | return reg; | |
1638 | } | |
9ebbca7d GK |
1639 | else if (TARGET_ELF && TARGET_32BIT && TARGET_NO_TOC && ! flag_pic |
1640 | && GET_CODE (x) != CONST_INT | |
1641 | && GET_CODE (x) != CONST_DOUBLE | |
1642 | && CONSTANT_P (x) | |
1643 | && (TARGET_HARD_FLOAT || mode != DFmode) | |
1644 | && mode != DImode | |
1645 | && mode != TImode) | |
1646 | { | |
1647 | rtx reg = gen_reg_rtx (Pmode); | |
1648 | emit_insn (gen_elf_high (reg, (x))); | |
1649 | return gen_rtx_LO_SUM (Pmode, reg, (x)); | |
1650 | } | |
ee890fe2 SS |
1651 | else if (TARGET_MACHO && TARGET_32BIT && TARGET_NO_TOC |
1652 | && ! flag_pic | |
1653 | && GET_CODE (x) != CONST_INT | |
1654 | && GET_CODE (x) != CONST_DOUBLE | |
1655 | && CONSTANT_P (x) | |
1656 | && (TARGET_HARD_FLOAT || mode != DFmode) | |
1657 | && mode != DImode | |
1658 | && mode != TImode) | |
1659 | { | |
1660 | rtx reg = gen_reg_rtx (Pmode); | |
1661 | emit_insn (gen_macho_high (reg, (x))); | |
1662 | return gen_rtx_LO_SUM (Pmode, reg, (x)); | |
1663 | } | |
9ebbca7d GK |
1664 | else if (TARGET_TOC |
1665 | && CONSTANT_POOL_EXPR_P (x) | |
a9098fd0 | 1666 | && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x), Pmode)) |
9ebbca7d GK |
1667 | { |
1668 | return create_TOC_reference (x); | |
1669 | } | |
1670 | else | |
1671 | return NULL_RTX; | |
1672 | } | |
258bfae2 FS |
1673 | |
1674 | /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression | |
1675 | that is a valid memory address for an instruction. | |
1676 | The MODE argument is the machine mode for the MEM expression | |
1677 | that wants to use this address. | |
1678 | ||
1679 | On the RS/6000, there are four valid address: a SYMBOL_REF that | |
1680 | refers to a constant pool entry of an address (or the sum of it | |
1681 | plus a constant), a short (16-bit signed) constant plus a register, | |
1682 | the sum of two registers, or a register indirect, possibly with an | |
1683 | auto-increment. For DFmode and DImode with an constant plus register, | |
1684 | we must ensure that both words are addressable or PowerPC64 with offset | |
1685 | word aligned. | |
1686 | ||
1687 | For modes spanning multiple registers (DFmode in 32-bit GPRs, | |
1688 | 32-bit DImode, TImode), indexed addressing cannot be used because | |
1689 | adjacent memory cells are accessed by adding word-sized offsets | |
1690 | during assembly output. */ | |
1691 | int | |
1692 | rs6000_legitimate_address (mode, x, reg_ok_strict) | |
1693 | enum machine_mode mode; | |
1694 | rtx x; | |
1695 | int reg_ok_strict; | |
1696 | { | |
1697 | if (LEGITIMATE_INDIRECT_ADDRESS_P (x, reg_ok_strict)) | |
1698 | return 1; | |
1699 | if ((GET_CODE (x) == PRE_INC || GET_CODE (x) == PRE_DEC) | |
1700 | && TARGET_UPDATE | |
1701 | && LEGITIMATE_INDIRECT_ADDRESS_P (XEXP (x, 0), reg_ok_strict)) | |
1702 | return 1; | |
1703 | if (LEGITIMATE_SMALL_DATA_P (mode, x)) | |
1704 | return 1; | |
1705 | if (LEGITIMATE_CONSTANT_POOL_ADDRESS_P (x)) | |
1706 | return 1; | |
1707 | /* If not REG_OK_STRICT (before reload) let pass any stack offset. */ | |
1708 | if (! reg_ok_strict | |
1709 | && GET_CODE (x) == PLUS | |
1710 | && GET_CODE (XEXP (x, 0)) == REG | |
1711 | && XEXP (x, 0) == virtual_stack_vars_rtx | |
1712 | && GET_CODE (XEXP (x, 1)) == CONST_INT) | |
1713 | return 1; | |
1714 | if (LEGITIMATE_OFFSET_ADDRESS_P (mode, x, reg_ok_strict)) | |
1715 | return 1; | |
1716 | if (mode != TImode | |
1717 | && (TARGET_HARD_FLOAT || TARGET_POWERPC64 || mode != DFmode) | |
1718 | && (TARGET_POWERPC64 || mode != DImode) | |
1719 | && LEGITIMATE_INDEXED_ADDRESS_P (x, reg_ok_strict)) | |
1720 | return 1; | |
1721 | if (LEGITIMATE_LO_SUM_ADDRESS_P (mode, x, reg_ok_strict)) | |
1722 | return 1; | |
1723 | return 0; | |
1724 | } | |
fb4d4348 | 1725 | \f |
a4f6c312 SS |
1726 | /* Try to output insns to set TARGET equal to the constant C if it can |
1727 | be done in less than N insns. Do all computations in MODE. | |
1728 | Returns the place where the output has been placed if it can be | |
1729 | done and the insns have been emitted. If it would take more than N | |
1730 | insns, zero is returned and no insns and emitted. */ | |
2bfcf297 DB |
1731 | |
1732 | rtx | |
1733 | rs6000_emit_set_const (dest, mode, source, n) | |
1734 | rtx dest, source; | |
1735 | enum machine_mode mode; | |
1736 | int n ATTRIBUTE_UNUSED; | |
1737 | { | |
1738 | HOST_WIDE_INT c0, c1; | |
1739 | ||
1740 | if (mode == QImode || mode == HImode || mode == SImode) | |
1741 | { | |
1742 | if (dest == NULL) | |
1743 | dest = gen_reg_rtx (mode); | |
1744 | emit_insn (gen_rtx_SET (VOIDmode, dest, source)); | |
1745 | return dest; | |
1746 | } | |
1747 | ||
1748 | if (GET_CODE (source) == CONST_INT) | |
1749 | { | |
1750 | c0 = INTVAL (source); | |
1751 | c1 = -(c0 < 0); | |
1752 | } | |
1753 | else if (GET_CODE (source) == CONST_DOUBLE) | |
1754 | { | |
1755 | #if HOST_BITS_PER_WIDE_INT >= 64 | |
1756 | c0 = CONST_DOUBLE_LOW (source); | |
1757 | c1 = -(c0 < 0); | |
1758 | #else | |
1759 | c0 = CONST_DOUBLE_LOW (source); | |
1760 | c1 = CONST_DOUBLE_HIGH (source); | |
1761 | #endif | |
1762 | } | |
1763 | else | |
a4f6c312 | 1764 | abort (); |
2bfcf297 DB |
1765 | |
1766 | return rs6000_emit_set_long_const (dest, c0, c1); | |
1767 | } | |
1768 | ||
1769 | /* Having failed to find a 3 insn sequence in rs6000_emit_set_const, | |
1770 | fall back to a straight forward decomposition. We do this to avoid | |
1771 | exponential run times encountered when looking for longer sequences | |
1772 | with rs6000_emit_set_const. */ | |
1773 | static rtx | |
1774 | rs6000_emit_set_long_const (dest, c1, c2) | |
1775 | rtx dest; | |
1776 | HOST_WIDE_INT c1, c2; | |
1777 | { | |
1778 | if (!TARGET_POWERPC64) | |
1779 | { | |
1780 | rtx operand1, operand2; | |
1781 | ||
1782 | operand1 = operand_subword_force (dest, WORDS_BIG_ENDIAN == 0, | |
1783 | DImode); | |
1784 | operand2 = operand_subword_force (dest, WORDS_BIG_ENDIAN != 0, | |
1785 | DImode); | |
1786 | emit_move_insn (operand1, GEN_INT (c1)); | |
1787 | emit_move_insn (operand2, GEN_INT (c2)); | |
1788 | } | |
1789 | else | |
1790 | { | |
1791 | HOST_WIDE_INT d1, d2, d3, d4; | |
1792 | ||
1793 | /* Decompose the entire word */ | |
1794 | #if HOST_BITS_PER_WIDE_INT >= 64 | |
1795 | if (c2 != -(c1 < 0)) | |
1796 | abort (); | |
1797 | d1 = ((c1 & 0xffff) ^ 0x8000) - 0x8000; | |
1798 | c1 -= d1; | |
1799 | d2 = ((c1 & 0xffffffff) ^ 0x80000000) - 0x80000000; | |
1800 | c1 = (c1 - d2) >> 32; | |
1801 | d3 = ((c1 & 0xffff) ^ 0x8000) - 0x8000; | |
1802 | c1 -= d3; | |
1803 | d4 = ((c1 & 0xffffffff) ^ 0x80000000) - 0x80000000; | |
1804 | if (c1 != d4) | |
1805 | abort (); | |
1806 | #else | |
1807 | d1 = ((c1 & 0xffff) ^ 0x8000) - 0x8000; | |
1808 | c1 -= d1; | |
1809 | d2 = ((c1 & 0xffffffff) ^ 0x80000000) - 0x80000000; | |
1810 | if (c1 != d2) | |
1811 | abort (); | |
1812 | c2 += (d2 < 0); | |
1813 | d3 = ((c2 & 0xffff) ^ 0x8000) - 0x8000; | |
1814 | c2 -= d3; | |
1815 | d4 = ((c2 & 0xffffffff) ^ 0x80000000) - 0x80000000; | |
1816 | if (c2 != d4) | |
1817 | abort (); | |
1818 | #endif | |
1819 | ||
1820 | /* Construct the high word */ | |
40501e5f | 1821 | if (d4 != 0) |
2bfcf297 DB |
1822 | { |
1823 | emit_move_insn (dest, GEN_INT (d4)); | |
40501e5f | 1824 | if (d3 != 0) |
2bfcf297 DB |
1825 | emit_move_insn (dest, |
1826 | gen_rtx_PLUS (DImode, dest, GEN_INT (d3))); | |
1827 | } | |
1828 | else | |
1829 | emit_move_insn (dest, GEN_INT (d3)); | |
1830 | ||
1831 | /* Shift it into place */ | |
40501e5f AM |
1832 | if (d3 != 0 || d4 != 0) |
1833 | emit_move_insn (dest, gen_rtx_ASHIFT (DImode, dest, GEN_INT (32))); | |
2bfcf297 DB |
1834 | |
1835 | /* Add in the low bits. */ | |
40501e5f | 1836 | if (d2 != 0) |
2bfcf297 | 1837 | emit_move_insn (dest, gen_rtx_PLUS (DImode, dest, GEN_INT (d2))); |
40501e5f | 1838 | if (d1 != 0) |
2bfcf297 DB |
1839 | emit_move_insn (dest, gen_rtx_PLUS (DImode, dest, GEN_INT (d1))); |
1840 | } | |
1841 | ||
1842 | return dest; | |
1843 | } | |
1844 | ||
fb4d4348 GK |
1845 | /* Emit a move from SOURCE to DEST in mode MODE. */ |
1846 | void | |
1847 | rs6000_emit_move (dest, source, mode) | |
1848 | rtx dest; | |
1849 | rtx source; | |
1850 | enum machine_mode mode; | |
1851 | { | |
1852 | rtx operands[2]; | |
1853 | operands[0] = dest; | |
1854 | operands[1] = source; | |
1855 | ||
1856 | /* Sanity checks. Check that we get CONST_DOUBLE only when we should. */ | |
1857 | if (GET_CODE (operands[1]) == CONST_DOUBLE | |
1858 | && ! FLOAT_MODE_P (mode) | |
1859 | && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT) | |
1860 | { | |
1861 | /* FIXME. This should never happen. */ | |
1862 | /* Since it seems that it does, do the safe thing and convert | |
1863 | to a CONST_INT. */ | |
1864 | operands[1] = | |
1865 | GEN_INT (trunc_int_for_mode (CONST_DOUBLE_LOW (operands[1]), mode)); | |
1866 | } | |
1867 | if (GET_CODE (operands[1]) == CONST_DOUBLE | |
1868 | && ! FLOAT_MODE_P (mode) | |
1869 | && ((CONST_DOUBLE_HIGH (operands[1]) == 0 | |
1870 | && CONST_DOUBLE_LOW (operands[1]) >= 0) | |
1871 | || (CONST_DOUBLE_HIGH (operands[1]) == -1 | |
1872 | && CONST_DOUBLE_LOW (operands[1]) < 0))) | |
1873 | abort (); | |
c9e8cb32 DD |
1874 | |
1875 | /* Check if GCC is setting up a block move that will end up using FP | |
1876 | registers as temporaries. We must make sure this is acceptable. */ | |
1877 | if (GET_CODE (operands[0]) == MEM | |
1878 | && GET_CODE (operands[1]) == MEM | |
1879 | && mode == DImode | |
c9e8cb32 DD |
1880 | && (SLOW_UNALIGNED_ACCESS(DImode, MEM_ALIGN(operands[0])) |
1881 | || SLOW_UNALIGNED_ACCESS(DImode, MEM_ALIGN(operands[1])))) | |
1882 | { | |
46aaf10d DE |
1883 | if (!TARGET_POWERPC64) |
1884 | { | |
1885 | emit_move_insn (simplify_subreg (SImode, operands[0], DImode, 0), | |
1886 | simplify_subreg (SImode, operands[1], DImode, 0)); | |
1887 | emit_move_insn (simplify_subreg (SImode, operands[0], DImode, 4), | |
1888 | simplify_subreg (SImode, operands[1], DImode, 4)); | |
1889 | } | |
1890 | else | |
1891 | { | |
1892 | emit_move_insn (gen_lowpart (SImode, operands[0]), | |
1893 | gen_lowpart (SImode, operands[1])); | |
1894 | emit_move_insn (gen_highpart (SImode, operands[0]), | |
1895 | gen_highpart (SImode, operands[1])); | |
1896 | } | |
c9e8cb32 DD |
1897 | return; |
1898 | } | |
fb4d4348 GK |
1899 | |
1900 | if (! no_new_pseudos && GET_CODE (operands[0]) != REG) | |
1901 | operands[1] = force_reg (mode, operands[1]); | |
a9098fd0 | 1902 | |
ffc14f31 GK |
1903 | if (mode == SFmode && ! TARGET_POWERPC && TARGET_HARD_FLOAT |
1904 | && GET_CODE (operands[0]) == MEM) | |
fb4d4348 | 1905 | { |
ffc14f31 GK |
1906 | int regnum; |
1907 | ||
1908 | if (reload_in_progress || reload_completed) | |
1909 | regnum = true_regnum (operands[1]); | |
1910 | else if (GET_CODE (operands[1]) == REG) | |
1911 | regnum = REGNO (operands[1]); | |
1912 | else | |
1913 | regnum = -1; | |
fb4d4348 GK |
1914 | |
1915 | /* If operands[1] is a register, on POWER it may have | |
1916 | double-precision data in it, so truncate it to single | |
1917 | precision. */ | |
1918 | if (FP_REGNO_P (regnum) || regnum >= FIRST_PSEUDO_REGISTER) | |
1919 | { | |
1920 | rtx newreg; | |
1921 | newreg = (no_new_pseudos ? operands[1] : gen_reg_rtx (mode)); | |
1922 | emit_insn (gen_aux_truncdfsf2 (newreg, operands[1])); | |
1923 | operands[1] = newreg; | |
1924 | } | |
1925 | } | |
1926 | ||
a9098fd0 GK |
1927 | /* Handle the case where reload calls us with an invalid address; |
1928 | and the case of CONSTANT_P_RTX. */ | |
1929 | if (! general_operand (operands[1], mode) | |
1930 | || ! nonimmediate_operand (operands[0], mode) | |
1931 | || GET_CODE (operands[1]) == CONSTANT_P_RTX) | |
fb4d4348 GK |
1932 | { |
1933 | emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1])); | |
1934 | return; | |
1935 | } | |
a9098fd0 | 1936 | |
fb4d4348 GK |
1937 | /* FIXME: In the long term, this switch statement should go away |
1938 | and be replaced by a sequence of tests based on things like | |
1939 | mode == Pmode. */ | |
1940 | switch (mode) | |
1941 | { | |
1942 | case HImode: | |
1943 | case QImode: | |
1944 | if (CONSTANT_P (operands[1]) | |
1945 | && GET_CODE (operands[1]) != CONST_INT) | |
a9098fd0 | 1946 | operands[1] = force_const_mem (mode, operands[1]); |
fb4d4348 GK |
1947 | break; |
1948 | ||
06f4e019 | 1949 | case TFmode: |
fb4d4348 GK |
1950 | case DFmode: |
1951 | case SFmode: | |
1952 | if (CONSTANT_P (operands[1]) | |
1953 | && ! easy_fp_constant (operands[1], mode)) | |
a9098fd0 | 1954 | operands[1] = force_const_mem (mode, operands[1]); |
fb4d4348 GK |
1955 | break; |
1956 | ||
0ac081f6 AH |
1957 | case V16QImode: |
1958 | case V8HImode: | |
1959 | case V4SFmode: | |
1960 | case V4SImode: | |
1961 | /* fixme: aldyh -- allow vector constants when they are implemented. */ | |
1962 | if (CONSTANT_P (operands[1])) | |
1963 | operands[1] = force_const_mem (mode, operands[1]); | |
1964 | break; | |
1965 | ||
fb4d4348 | 1966 | case SImode: |
a9098fd0 | 1967 | case DImode: |
fb4d4348 GK |
1968 | /* Use default pattern for address of ELF small data */ |
1969 | if (TARGET_ELF | |
a9098fd0 | 1970 | && mode == Pmode |
f607bc57 | 1971 | && DEFAULT_ABI == ABI_V4 |
a9098fd0 GK |
1972 | && (GET_CODE (operands[1]) == SYMBOL_REF |
1973 | || GET_CODE (operands[1]) == CONST) | |
1974 | && small_data_operand (operands[1], mode)) | |
fb4d4348 GK |
1975 | { |
1976 | emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1])); | |
1977 | return; | |
1978 | } | |
1979 | ||
f607bc57 | 1980 | if (DEFAULT_ABI == ABI_V4 |
a9098fd0 GK |
1981 | && mode == Pmode && mode == SImode |
1982 | && flag_pic == 1 && got_operand (operands[1], mode)) | |
fb4d4348 GK |
1983 | { |
1984 | emit_insn (gen_movsi_got (operands[0], operands[1])); | |
1985 | return; | |
1986 | } | |
1987 | ||
ee890fe2 SS |
1988 | if ((TARGET_ELF || DEFAULT_ABI == ABI_DARWIN) |
1989 | && TARGET_NO_TOC && ! flag_pic | |
a9098fd0 | 1990 | && mode == Pmode |
fb4d4348 GK |
1991 | && CONSTANT_P (operands[1]) |
1992 | && GET_CODE (operands[1]) != HIGH | |
1993 | && GET_CODE (operands[1]) != CONST_INT) | |
1994 | { | |
a9098fd0 | 1995 | rtx target = (no_new_pseudos ? operands[0] : gen_reg_rtx (mode)); |
fb4d4348 GK |
1996 | |
1997 | /* If this is a function address on -mcall-aixdesc, | |
1998 | convert it to the address of the descriptor. */ | |
1999 | if (DEFAULT_ABI == ABI_AIX | |
2000 | && GET_CODE (operands[1]) == SYMBOL_REF | |
2001 | && XSTR (operands[1], 0)[0] == '.') | |
2002 | { | |
2003 | const char *name = XSTR (operands[1], 0); | |
2004 | rtx new_ref; | |
2005 | while (*name == '.') | |
2006 | name++; | |
2007 | new_ref = gen_rtx_SYMBOL_REF (Pmode, name); | |
2008 | CONSTANT_POOL_ADDRESS_P (new_ref) | |
2009 | = CONSTANT_POOL_ADDRESS_P (operands[1]); | |
2010 | SYMBOL_REF_FLAG (new_ref) = SYMBOL_REF_FLAG (operands[1]); | |
2011 | SYMBOL_REF_USED (new_ref) = SYMBOL_REF_USED (operands[1]); | |
2012 | operands[1] = new_ref; | |
2013 | } | |
7509c759 | 2014 | |
ee890fe2 SS |
2015 | if (DEFAULT_ABI == ABI_DARWIN) |
2016 | { | |
2017 | emit_insn (gen_macho_high (target, operands[1])); | |
2018 | emit_insn (gen_macho_low (operands[0], target, operands[1])); | |
2019 | return; | |
2020 | } | |
2021 | ||
fb4d4348 GK |
2022 | emit_insn (gen_elf_high (target, operands[1])); |
2023 | emit_insn (gen_elf_low (operands[0], target, operands[1])); | |
2024 | return; | |
2025 | } | |
2026 | ||
a9098fd0 GK |
2027 | /* If this is a SYMBOL_REF that refers to a constant pool entry, |
2028 | and we have put it in the TOC, we just need to make a TOC-relative | |
2029 | reference to it. */ | |
2030 | if (TARGET_TOC | |
2031 | && GET_CODE (operands[1]) == SYMBOL_REF | |
2032 | && CONSTANT_POOL_EXPR_P (operands[1]) | |
2033 | && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (operands[1]), | |
2034 | get_pool_mode (operands[1]))) | |
fb4d4348 | 2035 | { |
a9098fd0 | 2036 | operands[1] = create_TOC_reference (operands[1]); |
fb4d4348 | 2037 | } |
a9098fd0 GK |
2038 | else if (mode == Pmode |
2039 | && CONSTANT_P (operands[1]) | |
38886f37 AO |
2040 | && ((GET_CODE (operands[1]) != CONST_INT |
2041 | && ! easy_fp_constant (operands[1], mode)) | |
2042 | || (GET_CODE (operands[1]) == CONST_INT | |
2043 | && num_insns_constant (operands[1], mode) > 2) | |
2044 | || (GET_CODE (operands[0]) == REG | |
2045 | && FP_REGNO_P (REGNO (operands[0])))) | |
a9098fd0 GK |
2046 | && GET_CODE (operands[1]) != HIGH |
2047 | && ! LEGITIMATE_CONSTANT_POOL_ADDRESS_P (operands[1]) | |
2048 | && ! TOC_RELATIVE_EXPR_P (operands[1])) | |
fb4d4348 GK |
2049 | { |
2050 | /* Emit a USE operation so that the constant isn't deleted if | |
2051 | expensive optimizations are turned on because nobody | |
2052 | references it. This should only be done for operands that | |
2053 | contain SYMBOL_REFs with CONSTANT_POOL_ADDRESS_P set. | |
2054 | This should not be done for operands that contain LABEL_REFs. | |
2055 | For now, we just handle the obvious case. */ | |
2056 | if (GET_CODE (operands[1]) != LABEL_REF) | |
2057 | emit_insn (gen_rtx_USE (VOIDmode, operands[1])); | |
2058 | ||
ee890fe2 SS |
2059 | /* Darwin uses a special PIC legitimizer. */ |
2060 | if (DEFAULT_ABI == ABI_DARWIN && flag_pic) | |
2061 | { | |
78e1b90d | 2062 | #if TARGET_MACHO |
ee890fe2 SS |
2063 | rtx temp_reg = ((reload_in_progress || reload_completed) |
2064 | ? operands[0] : NULL); | |
2065 | ||
ee890fe2 SS |
2066 | operands[1] = |
2067 | rs6000_machopic_legitimize_pic_address (operands[1], mode, | |
a4f6c312 | 2068 | temp_reg); |
ee890fe2 SS |
2069 | #endif |
2070 | emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1])); | |
2071 | return; | |
2072 | } | |
2073 | ||
fb4d4348 GK |
2074 | /* If we are to limit the number of things we put in the TOC and |
2075 | this is a symbol plus a constant we can add in one insn, | |
2076 | just put the symbol in the TOC and add the constant. Don't do | |
2077 | this if reload is in progress. */ | |
2078 | if (GET_CODE (operands[1]) == CONST | |
2079 | && TARGET_NO_SUM_IN_TOC && ! reload_in_progress | |
2080 | && GET_CODE (XEXP (operands[1], 0)) == PLUS | |
a9098fd0 | 2081 | && add_operand (XEXP (XEXP (operands[1], 0), 1), mode) |
fb4d4348 GK |
2082 | && (GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == LABEL_REF |
2083 | || GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == SYMBOL_REF) | |
2084 | && ! side_effects_p (operands[0])) | |
2085 | { | |
a4f6c312 SS |
2086 | rtx sym = |
2087 | force_const_mem (mode, XEXP (XEXP (operands[1], 0), 0)); | |
fb4d4348 GK |
2088 | rtx other = XEXP (XEXP (operands[1], 0), 1); |
2089 | ||
a9098fd0 GK |
2090 | sym = force_reg (mode, sym); |
2091 | if (mode == SImode) | |
2092 | emit_insn (gen_addsi3 (operands[0], sym, other)); | |
2093 | else | |
2094 | emit_insn (gen_adddi3 (operands[0], sym, other)); | |
fb4d4348 GK |
2095 | return; |
2096 | } | |
2097 | ||
a9098fd0 | 2098 | operands[1] = force_const_mem (mode, operands[1]); |
fb4d4348 GK |
2099 | |
2100 | if (TARGET_TOC | |
d34c5b80 DE |
2101 | && CONSTANT_POOL_EXPR_P (XEXP (operands[1], 0)) |
2102 | && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P ( | |
2103 | get_pool_constant (XEXP (operands[1], 0)), | |
2104 | get_pool_mode (XEXP (operands[1], 0)))) | |
a9098fd0 | 2105 | { |
ba4828e0 RK |
2106 | operands[1] |
2107 | = gen_rtx_MEM (mode, | |
2108 | create_TOC_reference (XEXP (operands[1], 0))); | |
2109 | set_mem_alias_set (operands[1], get_TOC_alias_set ()); | |
fb4d4348 | 2110 | RTX_UNCHANGING_P (operands[1]) = 1; |
a9098fd0 | 2111 | } |
fb4d4348 GK |
2112 | } |
2113 | break; | |
a9098fd0 | 2114 | |
fb4d4348 GK |
2115 | case TImode: |
2116 | if (GET_CODE (operands[0]) == MEM | |
2117 | && GET_CODE (XEXP (operands[0], 0)) != REG | |
2118 | && ! reload_in_progress) | |
792760b9 RK |
2119 | operands[0] |
2120 | = replace_equiv_address (operands[0], | |
2121 | copy_addr_to_reg (XEXP (operands[0], 0))); | |
fb4d4348 GK |
2122 | |
2123 | if (GET_CODE (operands[1]) == MEM | |
2124 | && GET_CODE (XEXP (operands[1], 0)) != REG | |
2125 | && ! reload_in_progress) | |
792760b9 RK |
2126 | operands[1] |
2127 | = replace_equiv_address (operands[1], | |
2128 | copy_addr_to_reg (XEXP (operands[1], 0))); | |
fb4d4348 GK |
2129 | break; |
2130 | ||
2131 | default: | |
2132 | abort (); | |
2133 | } | |
2134 | ||
a9098fd0 GK |
2135 | /* Above, we may have called force_const_mem which may have returned |
2136 | an invalid address. If we can, fix this up; otherwise, reload will | |
2137 | have to deal with it. */ | |
2138 | if (GET_CODE (operands[1]) == MEM | |
2139 | && ! memory_address_p (mode, XEXP (operands[1], 0)) | |
2140 | && ! reload_in_progress) | |
f4ef873c | 2141 | operands[1] = adjust_address (operands[1], mode, 0); |
a9098fd0 | 2142 | |
fb4d4348 | 2143 | emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1])); |
02a4ec28 | 2144 | return; |
fb4d4348 | 2145 | } |
4697a36c MM |
2146 | \f |
2147 | /* Initialize a variable CUM of type CUMULATIVE_ARGS | |
2148 | for a call to a function whose data type is FNTYPE. | |
2149 | For a library call, FNTYPE is 0. | |
2150 | ||
2151 | For incoming args we set the number of arguments in the prototype large | |
1c20ae99 | 2152 | so we never return a PARALLEL. */ |
4697a36c MM |
2153 | |
2154 | void | |
2155 | init_cumulative_args (cum, fntype, libname, incoming) | |
2156 | CUMULATIVE_ARGS *cum; | |
2157 | tree fntype; | |
296b8152 | 2158 | rtx libname ATTRIBUTE_UNUSED; |
4697a36c MM |
2159 | int incoming; |
2160 | { | |
2161 | static CUMULATIVE_ARGS zero_cumulative; | |
2162 | ||
2163 | *cum = zero_cumulative; | |
2164 | cum->words = 0; | |
2165 | cum->fregno = FP_ARG_MIN_REG; | |
0ac081f6 | 2166 | cum->vregno = ALTIVEC_ARG_MIN_REG; |
4697a36c | 2167 | cum->prototype = (fntype && TYPE_ARG_TYPES (fntype)); |
7509c759 | 2168 | cum->call_cookie = CALL_NORMAL; |
4cc833b7 | 2169 | cum->sysv_gregno = GP_ARG_MIN_REG; |
4697a36c MM |
2170 | |
2171 | if (incoming) | |
bd227acc | 2172 | cum->nargs_prototype = 1000; /* don't return a PARALLEL */ |
4697a36c MM |
2173 | |
2174 | else if (cum->prototype) | |
2175 | cum->nargs_prototype = (list_length (TYPE_ARG_TYPES (fntype)) - 1 | |
2176 | + (TYPE_MODE (TREE_TYPE (fntype)) == BLKmode | |
2177 | || RETURN_IN_MEMORY (TREE_TYPE (fntype)))); | |
2178 | ||
2179 | else | |
2180 | cum->nargs_prototype = 0; | |
2181 | ||
2182 | cum->orig_nargs = cum->nargs_prototype; | |
7509c759 | 2183 | |
9ebbca7d GK |
2184 | /* Check for longcall's */ |
2185 | if (fntype && lookup_attribute ("longcall", TYPE_ATTRIBUTES (fntype))) | |
6a4cee5f MM |
2186 | cum->call_cookie = CALL_LONG; |
2187 | ||
4697a36c MM |
2188 | if (TARGET_DEBUG_ARG) |
2189 | { | |
2190 | fprintf (stderr, "\ninit_cumulative_args:"); | |
2191 | if (fntype) | |
2192 | { | |
2193 | tree ret_type = TREE_TYPE (fntype); | |
2194 | fprintf (stderr, " ret code = %s,", | |
2195 | tree_code_name[ (int)TREE_CODE (ret_type) ]); | |
2196 | } | |
2197 | ||
6a4cee5f MM |
2198 | if (cum->call_cookie & CALL_LONG) |
2199 | fprintf (stderr, " longcall,"); | |
2200 | ||
4697a36c MM |
2201 | fprintf (stderr, " proto = %d, nargs = %d\n", |
2202 | cum->prototype, cum->nargs_prototype); | |
2203 | } | |
2204 | } | |
2205 | \f | |
c229cba9 DE |
2206 | /* If defined, a C expression which determines whether, and in which |
2207 | direction, to pad out an argument with extra space. The value | |
2208 | should be of type `enum direction': either `upward' to pad above | |
2209 | the argument, `downward' to pad below, or `none' to inhibit | |
2210 | padding. | |
2211 | ||
2212 | For the AIX ABI structs are always stored left shifted in their | |
2213 | argument slot. */ | |
2214 | ||
9ebbca7d | 2215 | enum direction |
c229cba9 DE |
2216 | function_arg_padding (mode, type) |
2217 | enum machine_mode mode; | |
2218 | tree type; | |
2219 | { | |
c85f7c16 | 2220 | if (type != 0 && AGGREGATE_TYPE_P (type)) |
9ebbca7d | 2221 | return upward; |
c229cba9 DE |
2222 | |
2223 | /* This is the default definition. */ | |
2224 | return (! BYTES_BIG_ENDIAN | |
9ebbca7d | 2225 | ? upward |
c229cba9 DE |
2226 | : ((mode == BLKmode |
2227 | ? (type && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST | |
2228 | && int_size_in_bytes (type) < (PARM_BOUNDARY / BITS_PER_UNIT)) | |
2229 | : GET_MODE_BITSIZE (mode) < PARM_BOUNDARY) | |
9ebbca7d | 2230 | ? downward : upward)); |
c229cba9 DE |
2231 | } |
2232 | ||
b6c9286a MM |
2233 | /* If defined, a C expression that gives the alignment boundary, in bits, |
2234 | of an argument with the specified mode and type. If it is not defined, | |
2235 | PARM_BOUNDARY is used for all arguments. | |
2236 | ||
2310f99a | 2237 | V.4 wants long longs to be double word aligned. */ |
b6c9286a MM |
2238 | |
2239 | int | |
2240 | function_arg_boundary (mode, type) | |
2241 | enum machine_mode mode; | |
9ebbca7d | 2242 | tree type ATTRIBUTE_UNUSED; |
b6c9286a | 2243 | { |
f607bc57 | 2244 | if (DEFAULT_ABI == ABI_V4 && (mode == DImode || mode == DFmode)) |
e1f83b4d | 2245 | return 64; |
0ac081f6 AH |
2246 | else if (TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode)) |
2247 | return 128; | |
9ebbca7d | 2248 | else |
b6c9286a | 2249 | return PARM_BOUNDARY; |
b6c9286a MM |
2250 | } |
2251 | \f | |
4697a36c MM |
2252 | /* Update the data in CUM to advance over an argument |
2253 | of mode MODE and data type TYPE. | |
2254 | (TYPE is null for libcalls where that information may not be available.) */ | |
2255 | ||
2256 | void | |
2257 | function_arg_advance (cum, mode, type, named) | |
2258 | CUMULATIVE_ARGS *cum; | |
2259 | enum machine_mode mode; | |
2260 | tree type; | |
2261 | int named; | |
2262 | { | |
2263 | cum->nargs_prototype--; | |
2264 | ||
0ac081f6 AH |
2265 | if (TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode)) |
2266 | { | |
2267 | if (cum->vregno <= ALTIVEC_ARG_MAX_REG && cum->nargs_prototype >= 0) | |
2268 | cum->vregno++; | |
2269 | else | |
2270 | cum->words += RS6000_ARG_SIZE (mode, type); | |
2271 | } | |
f607bc57 | 2272 | else if (DEFAULT_ABI == ABI_V4) |
4697a36c | 2273 | { |
4cc833b7 RH |
2274 | if (TARGET_HARD_FLOAT |
2275 | && (mode == SFmode || mode == DFmode)) | |
4697a36c | 2276 | { |
4cc833b7 RH |
2277 | if (cum->fregno <= FP_ARG_V4_MAX_REG) |
2278 | cum->fregno++; | |
2279 | else | |
2280 | { | |
2281 | if (mode == DFmode) | |
2282 | cum->words += cum->words & 1; | |
d34c5b80 | 2283 | cum->words += RS6000_ARG_SIZE (mode, type); |
4cc833b7 | 2284 | } |
4697a36c | 2285 | } |
4cc833b7 RH |
2286 | else |
2287 | { | |
2288 | int n_words; | |
2289 | int gregno = cum->sysv_gregno; | |
2290 | ||
2291 | /* Aggregates and IEEE quad get passed by reference. */ | |
2292 | if ((type && AGGREGATE_TYPE_P (type)) | |
2293 | || mode == TFmode) | |
2294 | n_words = 1; | |
2295 | else | |
d34c5b80 | 2296 | n_words = RS6000_ARG_SIZE (mode, type); |
4cc833b7 RH |
2297 | |
2298 | /* Long long is put in odd registers. */ | |
2299 | if (n_words == 2 && (gregno & 1) == 0) | |
2300 | gregno += 1; | |
2301 | ||
2302 | /* Long long is not split between registers and stack. */ | |
2303 | if (gregno + n_words - 1 > GP_ARG_MAX_REG) | |
2304 | { | |
2305 | /* Long long is aligned on the stack. */ | |
2306 | if (n_words == 2) | |
2307 | cum->words += cum->words & 1; | |
2308 | cum->words += n_words; | |
2309 | } | |
4697a36c | 2310 | |
4cc833b7 RH |
2311 | /* Note: continuing to accumulate gregno past when we've started |
2312 | spilling to the stack indicates the fact that we've started | |
2313 | spilling to the stack to expand_builtin_saveregs. */ | |
2314 | cum->sysv_gregno = gregno + n_words; | |
2315 | } | |
4697a36c | 2316 | |
4cc833b7 RH |
2317 | if (TARGET_DEBUG_ARG) |
2318 | { | |
2319 | fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ", | |
2320 | cum->words, cum->fregno); | |
2321 | fprintf (stderr, "gregno = %2d, nargs = %4d, proto = %d, ", | |
2322 | cum->sysv_gregno, cum->nargs_prototype, cum->prototype); | |
2323 | fprintf (stderr, "mode = %4s, named = %d\n", | |
2324 | GET_MODE_NAME (mode), named); | |
2325 | } | |
4697a36c MM |
2326 | } |
2327 | else | |
4cc833b7 RH |
2328 | { |
2329 | int align = (TARGET_32BIT && (cum->words & 1) != 0 | |
2330 | && function_arg_boundary (mode, type) == 64) ? 1 : 0; | |
a4f6c312 | 2331 | |
d34c5b80 | 2332 | cum->words += align + RS6000_ARG_SIZE (mode, type); |
4697a36c | 2333 | |
d34c5b80 DE |
2334 | if (GET_MODE_CLASS (mode) == MODE_FLOAT && TARGET_HARD_FLOAT) |
2335 | cum->fregno++; | |
4cc833b7 RH |
2336 | |
2337 | if (TARGET_DEBUG_ARG) | |
2338 | { | |
2339 | fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ", | |
2340 | cum->words, cum->fregno); | |
2341 | fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s, ", | |
2342 | cum->nargs_prototype, cum->prototype, GET_MODE_NAME (mode)); | |
2343 | fprintf (stderr, "named = %d, align = %d\n", named, align); | |
2344 | } | |
2345 | } | |
4697a36c MM |
2346 | } |
2347 | \f | |
2348 | /* Determine where to put an argument to a function. | |
2349 | Value is zero to push the argument on the stack, | |
2350 | or a hard register in which to store the argument. | |
2351 | ||
2352 | MODE is the argument's machine mode. | |
2353 | TYPE is the data type of the argument (as a tree). | |
2354 | This is null for libcalls where that information may | |
2355 | not be available. | |
2356 | CUM is a variable of type CUMULATIVE_ARGS which gives info about | |
2357 | the preceding args and about the function being called. | |
2358 | NAMED is nonzero if this argument is a named parameter | |
2359 | (otherwise it is an extra parameter matching an ellipsis). | |
2360 | ||
2361 | On RS/6000 the first eight words of non-FP are normally in registers | |
2362 | and the rest are pushed. Under AIX, the first 13 FP args are in registers. | |
2363 | Under V.4, the first 8 FP args are in registers. | |
2364 | ||
2365 | If this is floating-point and no prototype is specified, we use | |
2366 | both an FP and integer register (or possibly FP reg and stack). Library | |
2367 | functions (when TYPE is zero) always have the proper types for args, | |
2368 | so we can pass the FP value just in one register. emit_library_function | |
1c20ae99 | 2369 | doesn't support PARALLEL anyway. */ |
4697a36c MM |
2370 | |
2371 | struct rtx_def * | |
2372 | function_arg (cum, mode, type, named) | |
2373 | CUMULATIVE_ARGS *cum; | |
2374 | enum machine_mode mode; | |
2375 | tree type; | |
d34c5b80 | 2376 | int named ATTRIBUTE_UNUSED; |
4697a36c | 2377 | { |
4cc833b7 | 2378 | enum rs6000_abi abi = DEFAULT_ABI; |
4697a36c | 2379 | |
a4f6c312 SS |
2380 | /* Return a marker to indicate whether CR1 needs to set or clear the |
2381 | bit that V.4 uses to say fp args were passed in registers. | |
2382 | Assume that we don't need the marker for software floating point, | |
2383 | or compiler generated library calls. */ | |
4697a36c MM |
2384 | if (mode == VOIDmode) |
2385 | { | |
f607bc57 | 2386 | if (abi == ABI_V4 |
7509c759 MM |
2387 | && TARGET_HARD_FLOAT |
2388 | && cum->nargs_prototype < 0 | |
4697a36c | 2389 | && type && (cum->prototype || TARGET_NO_PROTOTYPE)) |
7509c759 | 2390 | { |
6a4cee5f MM |
2391 | return GEN_INT (cum->call_cookie |
2392 | | ((cum->fregno == FP_ARG_MIN_REG) | |
2393 | ? CALL_V4_SET_FP_ARGS | |
2394 | : CALL_V4_CLEAR_FP_ARGS)); | |
7509c759 | 2395 | } |
4697a36c | 2396 | |
7509c759 | 2397 | return GEN_INT (cum->call_cookie); |
4697a36c MM |
2398 | } |
2399 | ||
0ac081f6 AH |
2400 | if (TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode)) |
2401 | { | |
2402 | if (cum->vregno <= ALTIVEC_ARG_MAX_REG) | |
2403 | return gen_rtx_REG (mode, cum->vregno); | |
2404 | else | |
2405 | return NULL; | |
2406 | } | |
f607bc57 | 2407 | else if (abi == ABI_V4) |
4697a36c | 2408 | { |
4cc833b7 RH |
2409 | if (TARGET_HARD_FLOAT |
2410 | && (mode == SFmode || mode == DFmode)) | |
2411 | { | |
2412 | if (cum->fregno <= FP_ARG_V4_MAX_REG) | |
2413 | return gen_rtx_REG (mode, cum->fregno); | |
2414 | else | |
2415 | return NULL; | |
2416 | } | |
2417 | else | |
2418 | { | |
2419 | int n_words; | |
2420 | int gregno = cum->sysv_gregno; | |
2421 | ||
2422 | /* Aggregates and IEEE quad get passed by reference. */ | |
2423 | if ((type && AGGREGATE_TYPE_P (type)) | |
2424 | || mode == TFmode) | |
2425 | n_words = 1; | |
2426 | else | |
d34c5b80 | 2427 | n_words = RS6000_ARG_SIZE (mode, type); |
4cc833b7 RH |
2428 | |
2429 | /* Long long is put in odd registers. */ | |
2430 | if (n_words == 2 && (gregno & 1) == 0) | |
2431 | gregno += 1; | |
2432 | ||
2433 | /* Long long is not split between registers and stack. */ | |
2434 | if (gregno + n_words - 1 <= GP_ARG_MAX_REG) | |
2435 | return gen_rtx_REG (mode, gregno); | |
2436 | else | |
2437 | return NULL; | |
2438 | } | |
4697a36c | 2439 | } |
4cc833b7 RH |
2440 | else |
2441 | { | |
2442 | int align = (TARGET_32BIT && (cum->words & 1) != 0 | |
2443 | && function_arg_boundary (mode, type) == 64) ? 1 : 0; | |
2444 | int align_words = cum->words + align; | |
4697a36c | 2445 | |
4cc833b7 RH |
2446 | if (type && TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST) |
2447 | return NULL_RTX; | |
2448 | ||
2449 | if (USE_FP_FOR_ARG_P (*cum, mode, type)) | |
2450 | { | |
2451 | if (! type | |
2452 | || ((cum->nargs_prototype > 0) | |
2453 | /* IBM AIX extended its linkage convention definition always | |
2454 | to require FP args after register save area hole on the | |
2455 | stack. */ | |
2456 | && (DEFAULT_ABI != ABI_AIX | |
2457 | || ! TARGET_XL_CALL | |
2458 | || (align_words < GP_ARG_NUM_REG)))) | |
2459 | return gen_rtx_REG (mode, cum->fregno); | |
2460 | ||
2461 | return gen_rtx_PARALLEL (mode, | |
2462 | gen_rtvec (2, | |
39403d82 | 2463 | gen_rtx_EXPR_LIST (VOIDmode, |
1c20ae99 JW |
2464 | ((align_words >= GP_ARG_NUM_REG) |
2465 | ? NULL_RTX | |
2466 | : (align_words | |
d34c5b80 | 2467 | + RS6000_ARG_SIZE (mode, type) |
1c20ae99 JW |
2468 | > GP_ARG_NUM_REG |
2469 | /* If this is partially on the stack, then | |
2470 | we only include the portion actually | |
2471 | in registers here. */ | |
39403d82 | 2472 | ? gen_rtx_REG (SImode, |
1c20ae99 | 2473 | GP_ARG_MIN_REG + align_words) |
39403d82 | 2474 | : gen_rtx_REG (mode, |
1c20ae99 JW |
2475 | GP_ARG_MIN_REG + align_words))), |
2476 | const0_rtx), | |
39403d82 DE |
2477 | gen_rtx_EXPR_LIST (VOIDmode, |
2478 | gen_rtx_REG (mode, cum->fregno), | |
1c20ae99 | 2479 | const0_rtx))); |
4cc833b7 RH |
2480 | } |
2481 | else if (align_words < GP_ARG_NUM_REG) | |
2482 | return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words); | |
2483 | else | |
2484 | return NULL_RTX; | |
4697a36c | 2485 | } |
4697a36c MM |
2486 | } |
2487 | \f | |
2488 | /* For an arg passed partly in registers and partly in memory, | |
2489 | this is the number of registers used. | |
2490 | For args passed entirely in registers or entirely in memory, zero. */ | |
2491 | ||
2492 | int | |
2493 | function_arg_partial_nregs (cum, mode, type, named) | |
2494 | CUMULATIVE_ARGS *cum; | |
2495 | enum machine_mode mode; | |
2496 | tree type; | |
d34c5b80 | 2497 | int named ATTRIBUTE_UNUSED; |
4697a36c | 2498 | { |
f607bc57 | 2499 | if (DEFAULT_ABI == ABI_V4) |
4697a36c | 2500 | return 0; |
4697a36c | 2501 | |
0ac081f6 AH |
2502 | if (USE_FP_FOR_ARG_P (*cum, mode, type) |
2503 | || USE_ALTIVEC_FOR_ARG_P (*cum, mode, type)) | |
4697a36c MM |
2504 | { |
2505 | if (cum->nargs_prototype >= 0) | |
2506 | return 0; | |
2507 | } | |
2508 | ||
2509 | if (cum->words < GP_ARG_NUM_REG | |
d34c5b80 | 2510 | && GP_ARG_NUM_REG < (cum->words + RS6000_ARG_SIZE (mode, type))) |
4697a36c MM |
2511 | { |
2512 | int ret = GP_ARG_NUM_REG - cum->words; | |
2513 | if (ret && TARGET_DEBUG_ARG) | |
2514 | fprintf (stderr, "function_arg_partial_nregs: %d\n", ret); | |
2515 | ||
2516 | return ret; | |
2517 | } | |
2518 | ||
2519 | return 0; | |
2520 | } | |
2521 | \f | |
2522 | /* A C expression that indicates when an argument must be passed by | |
2523 | reference. If nonzero for an argument, a copy of that argument is | |
2524 | made in memory and a pointer to the argument is passed instead of | |
2525 | the argument itself. The pointer is passed in whatever way is | |
2526 | appropriate for passing a pointer to that type. | |
2527 | ||
2528 | Under V.4, structures and unions are passed by reference. */ | |
2529 | ||
2530 | int | |
2531 | function_arg_pass_by_reference (cum, mode, type, named) | |
296b8152 KG |
2532 | CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED; |
2533 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
4697a36c | 2534 | tree type; |
296b8152 | 2535 | int named ATTRIBUTE_UNUSED; |
4697a36c | 2536 | { |
f607bc57 | 2537 | if (DEFAULT_ABI == ABI_V4 |
4cc833b7 RH |
2538 | && ((type && AGGREGATE_TYPE_P (type)) |
2539 | || mode == TFmode)) | |
4697a36c MM |
2540 | { |
2541 | if (TARGET_DEBUG_ARG) | |
2542 | fprintf (stderr, "function_arg_pass_by_reference: aggregate\n"); | |
2543 | ||
2544 | return 1; | |
2545 | } | |
4697a36c MM |
2546 | |
2547 | return 0; | |
2548 | } | |
4697a36c MM |
2549 | \f |
2550 | /* Perform any needed actions needed for a function that is receiving a | |
2551 | variable number of arguments. | |
2552 | ||
2553 | CUM is as above. | |
2554 | ||
2555 | MODE and TYPE are the mode and type of the current parameter. | |
2556 | ||
2557 | PRETEND_SIZE is a variable that should be set to the amount of stack | |
2558 | that must be pushed by the prolog to pretend that our caller pushed | |
2559 | it. | |
2560 | ||
2561 | Normally, this macro will push all remaining incoming registers on the | |
2562 | stack and set PRETEND_SIZE to the length of the registers pushed. */ | |
2563 | ||
2564 | void | |
2565 | setup_incoming_varargs (cum, mode, type, pretend_size, no_rtl) | |
2566 | CUMULATIVE_ARGS *cum; | |
2567 | enum machine_mode mode; | |
2568 | tree type; | |
2569 | int *pretend_size; | |
2570 | int no_rtl; | |
2571 | ||
2572 | { | |
4cc833b7 RH |
2573 | CUMULATIVE_ARGS next_cum; |
2574 | int reg_size = TARGET_32BIT ? 4 : 8; | |
ca5adc63 | 2575 | rtx save_area = NULL_RTX, mem; |
dfafc897 | 2576 | int first_reg_offset, set; |
d34c5b80 DE |
2577 | tree fntype; |
2578 | int stdarg_p; | |
4697a36c | 2579 | |
d34c5b80 DE |
2580 | fntype = TREE_TYPE (current_function_decl); |
2581 | stdarg_p = (TYPE_ARG_TYPES (fntype) != 0 | |
2582 | && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype))) | |
2583 | != void_type_node)); | |
4cc833b7 | 2584 | |
d34c5b80 DE |
2585 | /* For varargs, we do not want to skip the dummy va_dcl argument. |
2586 | For stdargs, we do want to skip the last named argument. */ | |
2587 | next_cum = *cum; | |
2588 | if (stdarg_p) | |
2589 | function_arg_advance (&next_cum, mode, type, 1); | |
4cc833b7 | 2590 | |
f607bc57 | 2591 | if (DEFAULT_ABI == ABI_V4) |
d34c5b80 | 2592 | { |
4cc833b7 RH |
2593 | /* Indicate to allocate space on the stack for varargs save area. */ |
2594 | /* ??? Does this really have to be located at a magic spot on the | |
2595 | stack, or can we allocate this with assign_stack_local instead. */ | |
00dba523 | 2596 | cfun->machine->sysv_varargs_p = 1; |
60e2d0ca | 2597 | if (! no_rtl) |
2c4974b7 | 2598 | save_area = plus_constant (virtual_stack_vars_rtx, |
bd227acc | 2599 | - RS6000_VARARGS_SIZE); |
4cc833b7 RH |
2600 | |
2601 | first_reg_offset = next_cum.sysv_gregno - GP_ARG_MIN_REG; | |
4697a36c | 2602 | } |
60e2d0ca | 2603 | else |
4697a36c | 2604 | { |
d34c5b80 | 2605 | first_reg_offset = next_cum.words; |
4cc833b7 | 2606 | save_area = virtual_incoming_args_rtx; |
00dba523 | 2607 | cfun->machine->sysv_varargs_p = 0; |
4697a36c MM |
2608 | |
2609 | if (MUST_PASS_IN_STACK (mode, type)) | |
d34c5b80 | 2610 | first_reg_offset += RS6000_ARG_SIZE (TYPE_MODE (type), type); |
4cc833b7 | 2611 | } |
4697a36c | 2612 | |
dfafc897 | 2613 | set = get_varargs_alias_set (); |
c81fc13e | 2614 | if (! no_rtl && first_reg_offset < GP_ARG_NUM_REG) |
4cc833b7 | 2615 | { |
dfafc897 FS |
2616 | mem = gen_rtx_MEM (BLKmode, |
2617 | plus_constant (save_area, | |
2618 | first_reg_offset * reg_size)), | |
ba4828e0 | 2619 | set_mem_alias_set (mem, set); |
8ac61af7 | 2620 | set_mem_align (mem, BITS_PER_WORD); |
dfafc897 | 2621 | |
4cc833b7 | 2622 | move_block_from_reg |
dfafc897 | 2623 | (GP_ARG_MIN_REG + first_reg_offset, mem, |
4cc833b7 RH |
2624 | GP_ARG_NUM_REG - first_reg_offset, |
2625 | (GP_ARG_NUM_REG - first_reg_offset) * UNITS_PER_WORD); | |
2626 | ||
2627 | /* ??? Does ABI_V4 need this at all? */ | |
4697a36c MM |
2628 | *pretend_size = (GP_ARG_NUM_REG - first_reg_offset) * UNITS_PER_WORD; |
2629 | } | |
2630 | ||
4697a36c | 2631 | /* Save FP registers if needed. */ |
f607bc57 | 2632 | if (DEFAULT_ABI == ABI_V4 |
c81fc13e | 2633 | && TARGET_HARD_FLOAT && ! no_rtl |
4cc833b7 | 2634 | && next_cum.fregno <= FP_ARG_V4_MAX_REG) |
4697a36c | 2635 | { |
4cc833b7 | 2636 | int fregno = next_cum.fregno; |
9ebbca7d | 2637 | rtx cr1 = gen_rtx_REG (CCmode, CR1_REGNO); |
4cc833b7 RH |
2638 | rtx lab = gen_label_rtx (); |
2639 | int off = (GP_ARG_NUM_REG * reg_size) + ((fregno - FP_ARG_MIN_REG) * 8); | |
4697a36c | 2640 | |
4cc833b7 | 2641 | emit_jump_insn (gen_rtx_SET (VOIDmode, |
4697a36c | 2642 | pc_rtx, |
39403d82 | 2643 | gen_rtx_IF_THEN_ELSE (VOIDmode, |
4cc833b7 RH |
2644 | gen_rtx_NE (VOIDmode, cr1, |
2645 | const0_rtx), | |
39403d82 | 2646 | gen_rtx_LABEL_REF (VOIDmode, lab), |
4697a36c MM |
2647 | pc_rtx))); |
2648 | ||
4cc833b7 RH |
2649 | while (fregno <= FP_ARG_V4_MAX_REG) |
2650 | { | |
dfafc897 | 2651 | mem = gen_rtx_MEM (DFmode, plus_constant (save_area, off)); |
ba4828e0 | 2652 | set_mem_alias_set (mem, set); |
dfafc897 | 2653 | emit_move_insn (mem, gen_rtx_REG (DFmode, fregno)); |
4cc833b7 RH |
2654 | fregno++; |
2655 | off += 8; | |
4697a36c | 2656 | } |
4cc833b7 RH |
2657 | |
2658 | emit_label (lab); | |
4697a36c | 2659 | } |
4697a36c | 2660 | } |
4697a36c | 2661 | |
dfafc897 | 2662 | /* Create the va_list data type. */ |
2c4974b7 | 2663 | |
dfafc897 FS |
2664 | tree |
2665 | rs6000_build_va_list () | |
2666 | { | |
bab45a51 | 2667 | tree f_gpr, f_fpr, f_ovf, f_sav, record, type_decl; |
4697a36c | 2668 | |
9ebbca7d GK |
2669 | /* For AIX, prefer 'char *' because that's what the system |
2670 | header files like. */ | |
f607bc57 | 2671 | if (DEFAULT_ABI != ABI_V4) |
9ebbca7d | 2672 | return build_pointer_type (char_type_node); |
dfafc897 | 2673 | |
0f4fd75d | 2674 | record = make_lang_type (RECORD_TYPE); |
bab45a51 | 2675 | type_decl = build_decl (TYPE_DECL, get_identifier ("__va_list_tag"), record); |
0f4fd75d | 2676 | |
9ebbca7d GK |
2677 | f_gpr = build_decl (FIELD_DECL, get_identifier ("gpr"), |
2678 | unsigned_char_type_node); | |
2679 | f_fpr = build_decl (FIELD_DECL, get_identifier ("fpr"), | |
2680 | unsigned_char_type_node); | |
dfafc897 FS |
2681 | f_ovf = build_decl (FIELD_DECL, get_identifier ("overflow_arg_area"), |
2682 | ptr_type_node); | |
2683 | f_sav = build_decl (FIELD_DECL, get_identifier ("reg_save_area"), | |
2684 | ptr_type_node); | |
2685 | ||
2686 | DECL_FIELD_CONTEXT (f_gpr) = record; | |
2687 | DECL_FIELD_CONTEXT (f_fpr) = record; | |
2688 | DECL_FIELD_CONTEXT (f_ovf) = record; | |
2689 | DECL_FIELD_CONTEXT (f_sav) = record; | |
2690 | ||
bab45a51 FS |
2691 | TREE_CHAIN (record) = type_decl; |
2692 | TYPE_NAME (record) = type_decl; | |
dfafc897 FS |
2693 | TYPE_FIELDS (record) = f_gpr; |
2694 | TREE_CHAIN (f_gpr) = f_fpr; | |
2695 | TREE_CHAIN (f_fpr) = f_ovf; | |
2696 | TREE_CHAIN (f_ovf) = f_sav; | |
2697 | ||
2698 | layout_type (record); | |
2699 | ||
2700 | /* The correct type is an array type of one element. */ | |
2701 | return build_array_type (record, build_index_type (size_zero_node)); | |
2702 | } | |
2703 | ||
2704 | /* Implement va_start. */ | |
2705 | ||
2706 | void | |
2707 | rs6000_va_start (stdarg_p, valist, nextarg) | |
2708 | int stdarg_p; | |
2709 | tree valist; | |
2710 | rtx nextarg; | |
4697a36c | 2711 | { |
dfafc897 FS |
2712 | HOST_WIDE_INT words, n_gpr, n_fpr; |
2713 | tree f_gpr, f_fpr, f_ovf, f_sav; | |
2714 | tree gpr, fpr, ovf, sav, t; | |
2c4974b7 | 2715 | |
dfafc897 | 2716 | /* Only SVR4 needs something special. */ |
f607bc57 | 2717 | if (DEFAULT_ABI != ABI_V4) |
dfafc897 FS |
2718 | { |
2719 | std_expand_builtin_va_start (stdarg_p, valist, nextarg); | |
2720 | return; | |
2721 | } | |
2722 | ||
973a648b | 2723 | f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node)); |
dfafc897 FS |
2724 | f_fpr = TREE_CHAIN (f_gpr); |
2725 | f_ovf = TREE_CHAIN (f_fpr); | |
2726 | f_sav = TREE_CHAIN (f_ovf); | |
2727 | ||
8ebecc3b | 2728 | valist = build1 (INDIRECT_REF, TREE_TYPE (TREE_TYPE (valist)), valist); |
dfafc897 FS |
2729 | gpr = build (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr); |
2730 | fpr = build (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr); | |
2731 | ovf = build (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf); | |
2732 | sav = build (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav); | |
2733 | ||
2734 | /* Count number of gp and fp argument registers used. */ | |
4cc833b7 | 2735 | words = current_function_args_info.words; |
dfafc897 FS |
2736 | n_gpr = current_function_args_info.sysv_gregno - GP_ARG_MIN_REG; |
2737 | n_fpr = current_function_args_info.fregno - FP_ARG_MIN_REG; | |
2738 | ||
2739 | if (TARGET_DEBUG_ARG) | |
78e1b90d DE |
2740 | { |
2741 | fputs ("va_start: words = ", stderr); | |
2742 | fprintf (stderr, HOST_WIDE_INT_PRINT_DEC, words); | |
2743 | fputs (", n_gpr = ", stderr); | |
2744 | fprintf (stderr, HOST_WIDE_INT_PRINT_DEC, n_gpr); | |
2745 | fputs (", n_fpr = ", stderr); | |
2746 | fprintf (stderr, HOST_WIDE_INT_PRINT_DEC, n_fpr); | |
2747 | putc ('\n', stderr); | |
2748 | } | |
dfafc897 FS |
2749 | |
2750 | t = build (MODIFY_EXPR, TREE_TYPE (gpr), gpr, build_int_2 (n_gpr, 0)); | |
2751 | TREE_SIDE_EFFECTS (t) = 1; | |
2752 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
2753 | ||
2754 | t = build (MODIFY_EXPR, TREE_TYPE (fpr), fpr, build_int_2 (n_fpr, 0)); | |
2755 | TREE_SIDE_EFFECTS (t) = 1; | |
2756 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
2757 | ||
2758 | /* Find the overflow area. */ | |
2759 | t = make_tree (TREE_TYPE (ovf), virtual_incoming_args_rtx); | |
2760 | if (words != 0) | |
2761 | t = build (PLUS_EXPR, TREE_TYPE (ovf), t, | |
2762 | build_int_2 (words * UNITS_PER_WORD, 0)); | |
2763 | t = build (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t); | |
2764 | TREE_SIDE_EFFECTS (t) = 1; | |
2765 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
2766 | ||
2767 | /* Find the register save area. */ | |
2768 | t = make_tree (TREE_TYPE (sav), virtual_stack_vars_rtx); | |
2769 | t = build (PLUS_EXPR, TREE_TYPE (sav), t, | |
2770 | build_int_2 (-RS6000_VARARGS_SIZE, -1)); | |
2771 | t = build (MODIFY_EXPR, TREE_TYPE (sav), sav, t); | |
2772 | TREE_SIDE_EFFECTS (t) = 1; | |
2773 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
2774 | } | |
2775 | ||
2776 | /* Implement va_arg. */ | |
2777 | ||
2778 | rtx | |
2779 | rs6000_va_arg (valist, type) | |
2780 | tree valist, type; | |
2781 | { | |
2782 | tree f_gpr, f_fpr, f_ovf, f_sav; | |
2783 | tree gpr, fpr, ovf, sav, reg, t, u; | |
2784 | int indirect_p, size, rsize, n_reg, sav_ofs, sav_scale; | |
2785 | rtx lab_false, lab_over, addr_rtx, r; | |
2786 | ||
9ebbca7d GK |
2787 | /* For AIX, the rule is that structures are passed left-aligned in |
2788 | their stack slot. However, GCC does not presently do this: | |
2789 | structures which are the same size as integer types are passed | |
2790 | right-aligned, as if they were in fact integers. This only | |
2791 | matters for structures of size 1 or 2, or 4 when TARGET_64BIT. */ | |
f607bc57 | 2792 | if (DEFAULT_ABI != ABI_V4) |
9ebbca7d GK |
2793 | { |
2794 | HOST_WIDE_INT align, rounded_size; | |
2795 | enum machine_mode mode; | |
2796 | tree addr_tree; | |
2797 | ||
2798 | /* Compute the rounded size of the type. */ | |
2799 | align = PARM_BOUNDARY / BITS_PER_UNIT; | |
2800 | rounded_size = (((int_size_in_bytes (type) + align - 1) / align) | |
2801 | * align); | |
2802 | ||
2803 | addr_tree = valist; | |
2804 | ||
2805 | mode = TYPE_MODE (type); | |
2806 | if (mode != BLKmode) | |
2807 | { | |
2808 | HOST_WIDE_INT adj; | |
2809 | adj = TREE_INT_CST_LOW (TYPE_SIZE (type)) / BITS_PER_UNIT; | |
2810 | if (rounded_size > align) | |
2811 | adj = rounded_size; | |
2812 | ||
2813 | addr_tree = build (PLUS_EXPR, TREE_TYPE (addr_tree), addr_tree, | |
2814 | build_int_2 (rounded_size - adj, 0)); | |
2815 | } | |
2816 | ||
2817 | addr_rtx = expand_expr (addr_tree, NULL_RTX, Pmode, EXPAND_NORMAL); | |
2818 | addr_rtx = copy_to_reg (addr_rtx); | |
2819 | ||
2820 | /* Compute new value for AP. */ | |
2821 | t = build (MODIFY_EXPR, TREE_TYPE (valist), valist, | |
2822 | build (PLUS_EXPR, TREE_TYPE (valist), valist, | |
2823 | build_int_2 (rounded_size, 0))); | |
2824 | TREE_SIDE_EFFECTS (t) = 1; | |
2825 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
2826 | ||
2827 | return addr_rtx; | |
2828 | } | |
dfafc897 | 2829 | |
973a648b | 2830 | f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node)); |
dfafc897 FS |
2831 | f_fpr = TREE_CHAIN (f_gpr); |
2832 | f_ovf = TREE_CHAIN (f_fpr); | |
2833 | f_sav = TREE_CHAIN (f_ovf); | |
2834 | ||
8ebecc3b | 2835 | valist = build1 (INDIRECT_REF, TREE_TYPE (TREE_TYPE (valist)), valist); |
dfafc897 FS |
2836 | gpr = build (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr); |
2837 | fpr = build (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr); | |
2838 | ovf = build (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf); | |
2839 | sav = build (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav); | |
2840 | ||
2841 | size = int_size_in_bytes (type); | |
2842 | rsize = (size + UNITS_PER_WORD - 1) / UNITS_PER_WORD; | |
4cc833b7 | 2843 | |
dfafc897 | 2844 | if (AGGREGATE_TYPE_P (type) || TYPE_MODE (type) == TFmode) |
4cc833b7 | 2845 | { |
dfafc897 FS |
2846 | /* Aggregates and long doubles are passed by reference. */ |
2847 | indirect_p = 1; | |
2848 | reg = gpr; | |
2849 | n_reg = 1; | |
2850 | sav_ofs = 0; | |
2851 | sav_scale = 4; | |
2852 | size = rsize = UNITS_PER_WORD; | |
2853 | } | |
2854 | else if (FLOAT_TYPE_P (type) && ! TARGET_SOFT_FLOAT) | |
2855 | { | |
2856 | /* FP args go in FP registers, if present. */ | |
2857 | indirect_p = 0; | |
2858 | reg = fpr; | |
2859 | n_reg = 1; | |
2860 | sav_ofs = 8*4; | |
2861 | sav_scale = 8; | |
4cc833b7 | 2862 | } |
dfafc897 FS |
2863 | else |
2864 | { | |
2865 | /* Otherwise into GP registers. */ | |
2866 | indirect_p = 0; | |
2867 | reg = gpr; | |
2868 | n_reg = rsize; | |
2869 | sav_ofs = 0; | |
2870 | sav_scale = 4; | |
2871 | } | |
2872 | ||
a4f6c312 | 2873 | /* Pull the value out of the saved registers ... */ |
dfafc897 FS |
2874 | |
2875 | lab_false = gen_label_rtx (); | |
2876 | lab_over = gen_label_rtx (); | |
2877 | addr_rtx = gen_reg_rtx (Pmode); | |
2878 | ||
2879 | emit_cmp_and_jump_insns (expand_expr (reg, NULL_RTX, QImode, EXPAND_NORMAL), | |
a06ef755 RK |
2880 | GEN_INT (8 - n_reg + 1), GE, const1_rtx, QImode, 1, |
2881 | lab_false); | |
2c4974b7 | 2882 | |
dfafc897 FS |
2883 | /* Long long is aligned in the registers. */ |
2884 | if (n_reg > 1) | |
2c4974b7 | 2885 | { |
dfafc897 FS |
2886 | u = build (BIT_AND_EXPR, TREE_TYPE (reg), reg, |
2887 | build_int_2 (n_reg - 1, 0)); | |
2888 | u = build (PLUS_EXPR, TREE_TYPE (reg), reg, u); | |
2889 | u = build (MODIFY_EXPR, TREE_TYPE (reg), reg, u); | |
2890 | TREE_SIDE_EFFECTS (u) = 1; | |
2891 | expand_expr (u, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
2c4974b7 | 2892 | } |
dfafc897 FS |
2893 | |
2894 | if (sav_ofs) | |
2895 | t = build (PLUS_EXPR, ptr_type_node, sav, build_int_2 (sav_ofs, 0)); | |
2c4974b7 | 2896 | else |
dfafc897 | 2897 | t = sav; |
2c4974b7 | 2898 | |
dfafc897 FS |
2899 | u = build (POSTINCREMENT_EXPR, TREE_TYPE (reg), reg, build_int_2 (n_reg, 0)); |
2900 | TREE_SIDE_EFFECTS (u) = 1; | |
2c4974b7 | 2901 | |
dfafc897 FS |
2902 | u = build1 (CONVERT_EXPR, integer_type_node, u); |
2903 | TREE_SIDE_EFFECTS (u) = 1; | |
2c4974b7 | 2904 | |
dfafc897 FS |
2905 | u = build (MULT_EXPR, integer_type_node, u, build_int_2 (sav_scale, 0)); |
2906 | TREE_SIDE_EFFECTS (u) = 1; | |
2907 | ||
2908 | t = build (PLUS_EXPR, ptr_type_node, t, u); | |
2909 | TREE_SIDE_EFFECTS (t) = 1; | |
2910 | ||
2911 | r = expand_expr (t, addr_rtx, Pmode, EXPAND_NORMAL); | |
2912 | if (r != addr_rtx) | |
2913 | emit_move_insn (addr_rtx, r); | |
2914 | ||
2915 | emit_jump_insn (gen_jump (lab_over)); | |
2916 | emit_barrier (); | |
2917 | emit_label (lab_false); | |
2918 | ||
a4f6c312 | 2919 | /* ... otherwise out of the overflow area. */ |
dfafc897 FS |
2920 | |
2921 | /* Make sure we don't find reg 7 for the next int arg. */ | |
2922 | if (n_reg > 1) | |
2923 | { | |
2924 | t = build (MODIFY_EXPR, TREE_TYPE (reg), reg, build_int_2 (8, 0)); | |
2925 | TREE_SIDE_EFFECTS (t) = 1; | |
2926 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
2927 | } | |
2928 | ||
2929 | /* Care for on-stack alignment if needed. */ | |
2930 | if (rsize <= 1) | |
2931 | t = ovf; | |
2932 | else | |
2933 | { | |
2934 | t = build (PLUS_EXPR, TREE_TYPE (ovf), ovf, build_int_2 (7, 0)); | |
2935 | t = build (BIT_AND_EXPR, TREE_TYPE (t), t, build_int_2 (-8, -1)); | |
2936 | } | |
2937 | t = save_expr (t); | |
2938 | ||
2939 | r = expand_expr (t, addr_rtx, Pmode, EXPAND_NORMAL); | |
2940 | if (r != addr_rtx) | |
2941 | emit_move_insn (addr_rtx, r); | |
2942 | ||
2943 | t = build (PLUS_EXPR, TREE_TYPE (t), t, build_int_2 (size, 0)); | |
2944 | t = build (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t); | |
2945 | TREE_SIDE_EFFECTS (t) = 1; | |
2946 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
2947 | ||
2948 | emit_label (lab_over); | |
2949 | ||
2950 | if (indirect_p) | |
2951 | { | |
2952 | r = gen_rtx_MEM (Pmode, addr_rtx); | |
ba4828e0 | 2953 | set_mem_alias_set (r, get_varargs_alias_set ()); |
dfafc897 FS |
2954 | emit_move_insn (addr_rtx, r); |
2955 | } | |
2956 | ||
2957 | return addr_rtx; | |
4697a36c | 2958 | } |
0ac081f6 AH |
2959 | |
2960 | /* Builtins. */ | |
2961 | ||
2962 | #define def_builtin(MASK, NAME, TYPE, CODE) \ | |
2963 | do { \ | |
2964 | if ((MASK) & target_flags) \ | |
2965 | builtin_function ((NAME), (TYPE), (CODE), BUILT_IN_MD, NULL); \ | |
2966 | } while (0) | |
2967 | ||
2968 | struct builtin_description | |
2969 | { | |
2970 | const unsigned int mask; | |
2971 | const enum insn_code icode; | |
2972 | const char *const name; | |
2973 | const enum rs6000_builtins code; | |
2974 | }; | |
2975 | ||
2976 | /* Simple binary operatiors: VECc = foo (VECa, VECb). */ | |
2977 | static const struct builtin_description bdesc_2arg[] = | |
2978 | { | |
2979 | { MASK_ALTIVEC, CODE_FOR_altivec_vaddubm, "__builtin_altivec_vaddubm", ALTIVEC_BUILTIN_VADDUBM }, | |
2980 | { MASK_ALTIVEC, CODE_FOR_altivec_vadduhm, "__builtin_altivec_vadduhm", ALTIVEC_BUILTIN_VADDUHM }, | |
2981 | { MASK_ALTIVEC, CODE_FOR_altivec_vadduwm, "__builtin_altivec_vadduwm", ALTIVEC_BUILTIN_VADDUWM }, | |
2982 | { MASK_ALTIVEC, CODE_FOR_altivec_vaddfp, "__builtin_altivec_vaddfp", ALTIVEC_BUILTIN_VADDFP }, | |
2983 | { MASK_ALTIVEC, CODE_FOR_altivec_vaddcuw, "__builtin_altivec_vaddcuw", ALTIVEC_BUILTIN_VADDCUW }, | |
2984 | { MASK_ALTIVEC, CODE_FOR_altivec_vaddubs, "__builtin_altivec_vaddubs", ALTIVEC_BUILTIN_VADDUBS }, | |
2985 | { MASK_ALTIVEC, CODE_FOR_altivec_vaddsbs, "__builtin_altivec_vaddsbs", ALTIVEC_BUILTIN_VADDSBS }, | |
2986 | { MASK_ALTIVEC, CODE_FOR_altivec_vadduhs, "__builtin_altivec_vadduhs", ALTIVEC_BUILTIN_VADDUHS }, | |
2987 | { MASK_ALTIVEC, CODE_FOR_altivec_vaddshs, "__builtin_altivec_vaddshs", ALTIVEC_BUILTIN_VADDSHS }, | |
2988 | { MASK_ALTIVEC, CODE_FOR_altivec_vadduws, "__builtin_altivec_vadduws", ALTIVEC_BUILTIN_VADDUWS }, | |
2989 | { MASK_ALTIVEC, CODE_FOR_altivec_vaddsws, "__builtin_altivec_vaddsws", ALTIVEC_BUILTIN_VADDSWS }, | |
2990 | { MASK_ALTIVEC, CODE_FOR_altivec_vand, "__builtin_altivec_vand", ALTIVEC_BUILTIN_VAND }, | |
2991 | { MASK_ALTIVEC, CODE_FOR_altivec_vandc, "__builtin_altivec_vandc", ALTIVEC_BUILTIN_VANDC }, | |
2992 | { MASK_ALTIVEC, CODE_FOR_altivec_vavgub, "__builtin_altivec_vavgub", ALTIVEC_BUILTIN_VAVGUB }, | |
2993 | { MASK_ALTIVEC, CODE_FOR_altivec_vavgsb, "__builtin_altivec_vavgsb", ALTIVEC_BUILTIN_VAVGSB }, | |
2994 | { MASK_ALTIVEC, CODE_FOR_altivec_vavguh, "__builtin_altivec_vavguh", ALTIVEC_BUILTIN_VAVGUH }, | |
2995 | { MASK_ALTIVEC, CODE_FOR_altivec_vavgsh, "__builtin_altivec_vavgsh", ALTIVEC_BUILTIN_VAVGSH }, | |
2996 | { MASK_ALTIVEC, CODE_FOR_altivec_vavguw, "__builtin_altivec_vavguw", ALTIVEC_BUILTIN_VAVGUW }, | |
2997 | { MASK_ALTIVEC, CODE_FOR_altivec_vavgsw, "__builtin_altivec_vavgsw", ALTIVEC_BUILTIN_VAVGSW }, | |
2998 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpbfp, "__builtin_altivec_vcmpbfp", ALTIVEC_BUILTIN_VCMPBFP }, | |
2999 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequb, "__builtin_altivec_vcmpequb", ALTIVEC_BUILTIN_VCMPEQUB }, | |
3000 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequh, "__builtin_altivec_vcmpequh", ALTIVEC_BUILTIN_VCMPEQUH }, | |
3001 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequw, "__builtin_altivec_vcmpequw", ALTIVEC_BUILTIN_VCMPEQUW }, | |
3002 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpeqfp, "__builtin_altivec_vcmpeqfp", ALTIVEC_BUILTIN_VCMPEQFP }, | |
3003 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgefp, "__builtin_altivec_vcmpgefp", ALTIVEC_BUILTIN_VCMPGEFP }, | |
3004 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtub, "__builtin_altivec_vcmpgtub", ALTIVEC_BUILTIN_VCMPGTUB }, | |
3005 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsb, "__builtin_altivec_vcmpgtsb", ALTIVEC_BUILTIN_VCMPGTSB }, | |
3006 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtuh, "__builtin_altivec_vcmpgtuh", ALTIVEC_BUILTIN_VCMPGTUH }, | |
3007 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsh, "__builtin_altivec_vcmpgtsh", ALTIVEC_BUILTIN_VCMPGTSH }, | |
3008 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtuw, "__builtin_altivec_vcmpgtuw", ALTIVEC_BUILTIN_VCMPGTUW }, | |
3009 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsw, "__builtin_altivec_vcmpgtsw", ALTIVEC_BUILTIN_VCMPGTSW }, | |
3010 | { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtfp, "__builtin_altivec_vcmpgtfp", ALTIVEC_BUILTIN_VCMPGTFP }, | |
3011 | { MASK_ALTIVEC, CODE_FOR_altivec_vmaxub, "__builtin_altivec_vmaxub", ALTIVEC_BUILTIN_VMAXUB }, | |
3012 | { MASK_ALTIVEC, CODE_FOR_altivec_vmaxsb, "__builtin_altivec_vmaxsb", ALTIVEC_BUILTIN_VMAXSB }, | |
3013 | { MASK_ALTIVEC, CODE_FOR_altivec_vmaxuh, "__builtin_altivec_vmaxuh", ALTIVEC_BUILTIN_VMAXUH }, | |
3014 | { MASK_ALTIVEC, CODE_FOR_altivec_vmaxsh, "__builtin_altivec_vmaxsh", ALTIVEC_BUILTIN_VMAXSH }, | |
3015 | { MASK_ALTIVEC, CODE_FOR_altivec_vmaxuw, "__builtin_altivec_vmaxuw", ALTIVEC_BUILTIN_VMAXUW }, | |
3016 | { MASK_ALTIVEC, CODE_FOR_altivec_vmaxsw, "__builtin_altivec_vmaxsw", ALTIVEC_BUILTIN_VMAXSW }, | |
3017 | { MASK_ALTIVEC, CODE_FOR_altivec_vmaxfp, "__builtin_altivec_vmaxfp", ALTIVEC_BUILTIN_VMAXFP }, | |
3018 | { MASK_ALTIVEC, CODE_FOR_altivec_vmrghb, "__builtin_altivec_vmrghb", ALTIVEC_BUILTIN_VMRGHB }, | |
3019 | { MASK_ALTIVEC, CODE_FOR_altivec_vmrghh, "__builtin_altivec_vmrghh", ALTIVEC_BUILTIN_VMRGHH }, | |
3020 | { MASK_ALTIVEC, CODE_FOR_altivec_vmrghw, "__builtin_altivec_vmrghw", ALTIVEC_BUILTIN_VMRGHW }, | |
3021 | { MASK_ALTIVEC, CODE_FOR_altivec_vmrglb, "__builtin_altivec_vmrglb", ALTIVEC_BUILTIN_VMRGLB }, | |
3022 | { MASK_ALTIVEC, CODE_FOR_altivec_vmrglh, "__builtin_altivec_vmrglh", ALTIVEC_BUILTIN_VMRGLH }, | |
3023 | { MASK_ALTIVEC, CODE_FOR_altivec_vmrglw, "__builtin_altivec_vmrglw", ALTIVEC_BUILTIN_VMRGLW }, | |
3024 | { MASK_ALTIVEC, CODE_FOR_altivec_vminub, "__builtin_altivec_vminub", ALTIVEC_BUILTIN_VMINUB }, | |
3025 | { MASK_ALTIVEC, CODE_FOR_altivec_vminsb, "__builtin_altivec_vminsb", ALTIVEC_BUILTIN_VMINSB }, | |
3026 | { MASK_ALTIVEC, CODE_FOR_altivec_vminuh, "__builtin_altivec_vminuh", ALTIVEC_BUILTIN_VMINUH }, | |
3027 | { MASK_ALTIVEC, CODE_FOR_altivec_vminsh, "__builtin_altivec_vminsh", ALTIVEC_BUILTIN_VMINSH }, | |
3028 | { MASK_ALTIVEC, CODE_FOR_altivec_vminuw, "__builtin_altivec_vminuw", ALTIVEC_BUILTIN_VMINUW }, | |
3029 | { MASK_ALTIVEC, CODE_FOR_altivec_vminsw, "__builtin_altivec_vminsw", ALTIVEC_BUILTIN_VMINSW }, | |
3030 | { MASK_ALTIVEC, CODE_FOR_altivec_vminfp, "__builtin_altivec_vminfp", ALTIVEC_BUILTIN_VMINFP }, | |
3031 | { MASK_ALTIVEC, CODE_FOR_altivec_vmuleub, "__builtin_altivec_vmuleub", ALTIVEC_BUILTIN_VMULEUB }, | |
3032 | { MASK_ALTIVEC, CODE_FOR_altivec_vmulesb, "__builtin_altivec_vmulesb", ALTIVEC_BUILTIN_VMULESB }, | |
3033 | { MASK_ALTIVEC, CODE_FOR_altivec_vmuleuh, "__builtin_altivec_vmuleuh", ALTIVEC_BUILTIN_VMULEUH }, | |
3034 | { MASK_ALTIVEC, CODE_FOR_altivec_vmulesh, "__builtin_altivec_vmulesh", ALTIVEC_BUILTIN_VMULESH }, | |
3035 | { MASK_ALTIVEC, CODE_FOR_altivec_vmuloub, "__builtin_altivec_vmuloub", ALTIVEC_BUILTIN_VMULOUB }, | |
3036 | { MASK_ALTIVEC, CODE_FOR_altivec_vmulosb, "__builtin_altivec_vmulosb", ALTIVEC_BUILTIN_VMULOSB }, | |
3037 | { MASK_ALTIVEC, CODE_FOR_altivec_vmulouh, "__builtin_altivec_vmulouh", ALTIVEC_BUILTIN_VMULOUH }, | |
3038 | { MASK_ALTIVEC, CODE_FOR_altivec_vmulosh, "__builtin_altivec_vmulosh", ALTIVEC_BUILTIN_VMULOSH }, | |
3039 | { MASK_ALTIVEC, CODE_FOR_altivec_vnor, "__builtin_altivec_vnor", ALTIVEC_BUILTIN_VNOR }, | |
3040 | { MASK_ALTIVEC, CODE_FOR_altivec_vor, "__builtin_altivec_vor", ALTIVEC_BUILTIN_VOR }, | |
3041 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhum, "__builtin_altivec_vpkuhum", ALTIVEC_BUILTIN_VPKUHUM }, | |
3042 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwum, "__builtin_altivec_vpkuwum", ALTIVEC_BUILTIN_VPKUWUM }, | |
3043 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkpx, "__builtin_altivec_vpkpx", ALTIVEC_BUILTIN_VPKPX }, | |
3044 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhss, "__builtin_altivec_vpkuhss", ALTIVEC_BUILTIN_VPKUHSS }, | |
3045 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkshss, "__builtin_altivec_vpkshss", ALTIVEC_BUILTIN_VPKSHSS }, | |
3046 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwss, "__builtin_altivec_vpkuwss", ALTIVEC_BUILTIN_VPKUWSS }, | |
3047 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkswss, "__builtin_altivec_vpkswss", ALTIVEC_BUILTIN_VPKSWSS }, | |
3048 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhus, "__builtin_altivec_vpkuhus", ALTIVEC_BUILTIN_VPKUHUS }, | |
3049 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkshus, "__builtin_altivec_vpkshus", ALTIVEC_BUILTIN_VPKSHUS }, | |
3050 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwus, "__builtin_altivec_vpkuwus", ALTIVEC_BUILTIN_VPKUWUS }, | |
3051 | { MASK_ALTIVEC, CODE_FOR_altivec_vpkswus, "__builtin_altivec_vpkswus", ALTIVEC_BUILTIN_VPKSWUS }, | |
3052 | { MASK_ALTIVEC, CODE_FOR_altivec_vrlb, "__builtin_altivec_vrlb", ALTIVEC_BUILTIN_VRLB }, | |
3053 | { MASK_ALTIVEC, CODE_FOR_altivec_vrlh, "__builtin_altivec_vrlh", ALTIVEC_BUILTIN_VRLH }, | |
3054 | { MASK_ALTIVEC, CODE_FOR_altivec_vrlw, "__builtin_altivec_vrlw", ALTIVEC_BUILTIN_VRLW }, | |
3055 | { MASK_ALTIVEC, CODE_FOR_altivec_vslb, "__builtin_altivec_vslb", ALTIVEC_BUILTIN_VSLB }, | |
3056 | { MASK_ALTIVEC, CODE_FOR_altivec_vslh, "__builtin_altivec_vslh", ALTIVEC_BUILTIN_VSLH }, | |
3057 | { MASK_ALTIVEC, CODE_FOR_altivec_vslw, "__builtin_altivec_vslw", ALTIVEC_BUILTIN_VSLW }, | |
3058 | { MASK_ALTIVEC, CODE_FOR_altivec_vsl, "__builtin_altivec_vsl", ALTIVEC_BUILTIN_VSL }, | |
3059 | { MASK_ALTIVEC, CODE_FOR_altivec_vslo, "__builtin_altivec_vslo", ALTIVEC_BUILTIN_VSLO }, | |
3060 | { MASK_ALTIVEC, CODE_FOR_altivec_vsrb, "__builtin_altivec_vsrb", ALTIVEC_BUILTIN_VSRB }, | |
3061 | { MASK_ALTIVEC, CODE_FOR_altivec_vrsh, "__builtin_altivec_vrsh", ALTIVEC_BUILTIN_VRSH }, | |
3062 | { MASK_ALTIVEC, CODE_FOR_altivec_vrsw, "__builtin_altivec_vrsw", ALTIVEC_BUILTIN_VRSW }, | |
3063 | { MASK_ALTIVEC, CODE_FOR_altivec_vsrab, "__builtin_altivec_vsrab", ALTIVEC_BUILTIN_VSRAB }, | |
3064 | { MASK_ALTIVEC, CODE_FOR_altivec_vsrah, "__builtin_altivec_vsrah", ALTIVEC_BUILTIN_VSRAH }, | |
3065 | { MASK_ALTIVEC, CODE_FOR_altivec_vsraw, "__builtin_altivec_vsraw", ALTIVEC_BUILTIN_VSRAW }, | |
3066 | { MASK_ALTIVEC, CODE_FOR_altivec_vsr, "__builtin_altivec_vsr", ALTIVEC_BUILTIN_VSR }, | |
3067 | { MASK_ALTIVEC, CODE_FOR_altivec_vsro, "__builtin_altivec_vsro", ALTIVEC_BUILTIN_VSRO }, | |
3068 | { MASK_ALTIVEC, CODE_FOR_altivec_vsububm, "__builtin_altivec_vsububm", ALTIVEC_BUILTIN_VSUBUBM }, | |
3069 | { MASK_ALTIVEC, CODE_FOR_altivec_vsubuhm, "__builtin_altivec_vsubuhm", ALTIVEC_BUILTIN_VSUBUHM }, | |
3070 | { MASK_ALTIVEC, CODE_FOR_altivec_vsubuwm, "__builtin_altivec_vsubuwm", ALTIVEC_BUILTIN_VSUBUWM }, | |
3071 | { MASK_ALTIVEC, CODE_FOR_altivec_vsubfp, "__builtin_altivec_vsubfp", ALTIVEC_BUILTIN_VSUBFP }, | |
3072 | { MASK_ALTIVEC, CODE_FOR_altivec_vsubcuw, "__builtin_altivec_vsubcuw", ALTIVEC_BUILTIN_VSUBCUW }, | |
3073 | { MASK_ALTIVEC, CODE_FOR_altivec_vsububs, "__builtin_altivec_vsububs", ALTIVEC_BUILTIN_VSUBUBS }, | |
3074 | { MASK_ALTIVEC, CODE_FOR_altivec_vsubsbs, "__builtin_altivec_vsubsbs", ALTIVEC_BUILTIN_VSUBSBS }, | |
3075 | { MASK_ALTIVEC, CODE_FOR_altivec_vsubuhs, "__builtin_altivec_vsubuhs", ALTIVEC_BUILTIN_VSUBUHS }, | |
3076 | { MASK_ALTIVEC, CODE_FOR_altivec_vsubshs, "__builtin_altivec_vsubshs", ALTIVEC_BUILTIN_VSUBSHS }, | |
3077 | { MASK_ALTIVEC, CODE_FOR_altivec_vsubuws, "__builtin_altivec_vsubuws", ALTIVEC_BUILTIN_VSUBUWS }, | |
3078 | { MASK_ALTIVEC, CODE_FOR_altivec_vsubsws, "__builtin_altivec_vsubsws", ALTIVEC_BUILTIN_VSUBSWS }, | |
3079 | { MASK_ALTIVEC, CODE_FOR_altivec_vsum4ubs, "__builtin_altivec_vsum4ubs", ALTIVEC_BUILTIN_VSUM4UBS }, | |
3080 | { MASK_ALTIVEC, CODE_FOR_altivec_vsum4sbs, "__builtin_altivec_vsum4sbs", ALTIVEC_BUILTIN_VSUM4SBS }, | |
3081 | { MASK_ALTIVEC, CODE_FOR_altivec_vsum4shs, "__builtin_altivec_vsum4shs", ALTIVEC_BUILTIN_VSUM4SHS }, | |
3082 | { MASK_ALTIVEC, CODE_FOR_altivec_vsum2sws, "__builtin_altivec_vsum2sws", ALTIVEC_BUILTIN_VSUM2SWS }, | |
3083 | { MASK_ALTIVEC, CODE_FOR_altivec_vsumsws, "__builtin_altivec_vsumsws", ALTIVEC_BUILTIN_VSUMSWS }, | |
3084 | { MASK_ALTIVEC, CODE_FOR_altivec_vxor, "__builtin_altivec_vxor", ALTIVEC_BUILTIN_VXOR }, | |
3085 | }; | |
3086 | ||
3087 | static rtx | |
3088 | altivec_expand_binop_builtin (icode, arglist, target) | |
3089 | enum insn_code icode; | |
3090 | tree arglist; | |
3091 | rtx target; | |
3092 | { | |
3093 | rtx pat; | |
3094 | tree arg0 = TREE_VALUE (arglist); | |
3095 | tree arg1 = TREE_VALUE (TREE_CHAIN (arglist)); | |
3096 | rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
3097 | rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); | |
3098 | enum machine_mode tmode = insn_data[icode].operand[0].mode; | |
3099 | enum machine_mode mode0 = insn_data[icode].operand[1].mode; | |
3100 | enum machine_mode mode1 = insn_data[icode].operand[2].mode; | |
3101 | ||
3102 | if (! target | |
3103 | || GET_MODE (target) != tmode | |
3104 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
3105 | target = gen_reg_rtx (tmode); | |
3106 | ||
3107 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) | |
3108 | op0 = copy_to_mode_reg (mode0, op0); | |
3109 | if (! (*insn_data[icode].operand[2].predicate) (op1, mode1)) | |
3110 | op1 = copy_to_mode_reg (mode1, op1); | |
3111 | ||
3112 | pat = GEN_FCN (icode) (target, op0, op1); | |
3113 | if (! pat) | |
3114 | return 0; | |
3115 | emit_insn (pat); | |
3116 | ||
3117 | return target; | |
3118 | } | |
3119 | ||
3120 | static rtx | |
00b960c7 | 3121 | altivec_expand_builtin (exp, target) |
0ac081f6 AH |
3122 | tree exp; |
3123 | rtx target; | |
0ac081f6 AH |
3124 | { |
3125 | struct builtin_description *d; | |
3126 | size_t i; | |
3127 | enum insn_code icode; | |
3128 | tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0); | |
3129 | tree arglist = TREE_OPERAND (exp, 1); | |
00b960c7 AH |
3130 | tree arg0, arg1; |
3131 | rtx op0, op1, pat; | |
3132 | enum machine_mode tmode, mode0, mode1; | |
0ac081f6 AH |
3133 | unsigned int fcode = DECL_FUNCTION_CODE (fndecl); |
3134 | ||
3135 | switch (fcode) | |
3136 | { | |
3137 | case ALTIVEC_BUILTIN_LD_INTERNAL: | |
3138 | icode = CODE_FOR_altivec_lvx; | |
3139 | arg0 = TREE_VALUE (arglist); | |
3140 | op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
3141 | tmode = insn_data[icode].operand[0].mode; | |
3142 | mode0 = insn_data[icode].operand[1].mode; | |
3143 | ||
3144 | if (! target | |
3145 | || GET_MODE (target) != tmode | |
3146 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
3147 | target = gen_reg_rtx (tmode); | |
3148 | ||
3149 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) | |
3150 | op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0)); | |
3151 | ||
3152 | pat = GEN_FCN (icode) (target, op0); | |
3153 | if (! pat) | |
3154 | return 0; | |
3155 | emit_insn (pat); | |
3156 | return target; | |
3157 | ||
3158 | case ALTIVEC_BUILTIN_ST_INTERNAL: | |
3159 | icode = CODE_FOR_altivec_stvx; | |
3160 | arg0 = TREE_VALUE (arglist); | |
3161 | arg1 = TREE_VALUE (TREE_CHAIN (arglist)); | |
3162 | op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
3163 | op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); | |
3164 | mode0 = insn_data[icode].operand[0].mode; | |
3165 | mode1 = insn_data[icode].operand[1].mode; | |
3166 | ||
3167 | if (! (*insn_data[icode].operand[0].predicate) (op0, mode0)) | |
3168 | op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0)); | |
3169 | if (! (*insn_data[icode].operand[1].predicate) (op1, mode1)) | |
3170 | op1 = copy_to_mode_reg (mode1, op1); | |
3171 | ||
3172 | pat = GEN_FCN (icode) (op0, op1); | |
3173 | if (! pat) | |
3174 | return 0; | |
3175 | emit_insn (pat); | |
3176 | return NULL_RTX; | |
3177 | } | |
3178 | ||
3179 | /* Handle simple binary operations. */ | |
00b960c7 AH |
3180 | d = (struct builtin_description *) bdesc_2arg; |
3181 | for (i = 0; i < sizeof (bdesc_2arg) / sizeof *d; i++, d++) | |
0ac081f6 AH |
3182 | if (d->code == fcode) |
3183 | return altivec_expand_binop_builtin (d->icode, arglist, target); | |
3184 | ||
3185 | abort (); | |
3186 | return NULL_RTX; | |
3187 | } | |
3188 | ||
3189 | /* Expand an expression EXP that calls a built-in function, | |
3190 | with result going to TARGET if that's convenient | |
3191 | (and in mode MODE if that's convenient). | |
3192 | SUBTARGET may be used as the target for computing one of EXP's operands. | |
3193 | IGNORE is nonzero if the value is to be ignored. */ | |
3194 | ||
3195 | static rtx | |
3196 | rs6000_expand_builtin (exp, target, subtarget, mode, ignore) | |
3197 | tree exp; | |
3198 | rtx target; | |
00b960c7 AH |
3199 | rtx subtarget ATTRIBUTE_UNUSED; |
3200 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
3201 | int ignore ATTRIBUTE_UNUSED; | |
0ac081f6 AH |
3202 | { |
3203 | if (TARGET_ALTIVEC) | |
00b960c7 | 3204 | return altivec_expand_builtin (exp, target); |
0ac081f6 AH |
3205 | |
3206 | abort (); | |
3207 | } | |
3208 | ||
3209 | static void | |
3210 | rs6000_init_builtins (list_node) | |
3211 | tree list_node ATTRIBUTE_UNUSED; | |
3212 | { | |
3213 | if (TARGET_ALTIVEC) | |
3214 | altivec_init_builtins (); | |
3215 | } | |
3216 | ||
3217 | static void | |
3218 | altivec_init_builtins (void) | |
3219 | { | |
3220 | struct builtin_description * d; | |
3221 | size_t i; | |
3222 | ||
3223 | tree endlink = void_list_node; | |
3224 | ||
3225 | tree pint_type_node = build_pointer_type (integer_type_node); | |
3226 | ||
3227 | /* V4SI foo (int *). */ | |
3228 | tree v4si_ftype_pint | |
3229 | = build_function_type (V4SI_type_node, | |
3230 | tree_cons (NULL_TREE, pint_type_node, endlink)); | |
3231 | ||
3232 | /* void foo (int *, V4SI). */ | |
3233 | tree void_ftype_pint_v4si | |
3234 | = build_function_type (void_type_node, | |
3235 | tree_cons (NULL_TREE, pint_type_node, | |
3236 | tree_cons (NULL_TREE, V4SI_type_node, | |
3237 | endlink))); | |
3238 | ||
3239 | tree v4si_ftype_v4si_v4si | |
3240 | = build_function_type (V4SI_type_node, | |
3241 | tree_cons (NULL_TREE, V4SI_type_node, | |
3242 | tree_cons (NULL_TREE, V4SI_type_node, | |
3243 | endlink))); | |
3244 | ||
3245 | tree v4sf_ftype_v4sf_v4sf | |
3246 | = build_function_type (V4SF_type_node, | |
3247 | tree_cons (NULL_TREE, V4SF_type_node, | |
3248 | tree_cons (NULL_TREE, V4SF_type_node, | |
3249 | endlink))); | |
3250 | ||
3251 | tree v8hi_ftype_v8hi_v8hi | |
3252 | = build_function_type (V8HI_type_node, | |
3253 | tree_cons (NULL_TREE, V8HI_type_node, | |
3254 | tree_cons (NULL_TREE, V8HI_type_node, | |
3255 | endlink))); | |
3256 | ||
3257 | tree v16qi_ftype_v16qi_v16qi | |
3258 | = build_function_type (V16QI_type_node, | |
3259 | tree_cons (NULL_TREE, V16QI_type_node, | |
3260 | tree_cons (NULL_TREE, V16QI_type_node, | |
3261 | endlink))); | |
3262 | ||
3263 | tree v4si_ftype_v4sf_v4sf | |
3264 | = build_function_type (V4SI_type_node, | |
3265 | tree_cons (NULL_TREE, V4SF_type_node, | |
3266 | tree_cons (NULL_TREE, V4SF_type_node, | |
3267 | endlink))); | |
3268 | ||
3269 | tree v8hi_ftype_v16qi_v16qi | |
3270 | = build_function_type (V8HI_type_node, | |
3271 | tree_cons (NULL_TREE, V16QI_type_node, | |
3272 | tree_cons (NULL_TREE, V16QI_type_node, | |
3273 | endlink))); | |
3274 | ||
3275 | tree v4si_ftype_v8hi_v8hi | |
3276 | = build_function_type (V4SI_type_node, | |
3277 | tree_cons (NULL_TREE, V8HI_type_node, | |
3278 | tree_cons (NULL_TREE, V8HI_type_node, | |
3279 | endlink))); | |
3280 | ||
3281 | tree v8hi_ftype_v4si_v4si | |
3282 | = build_function_type (V8HI_type_node, | |
3283 | tree_cons (NULL_TREE, V4SI_type_node, | |
3284 | tree_cons (NULL_TREE, V4SI_type_node, | |
3285 | endlink))); | |
3286 | ||
3287 | tree v16qi_ftype_v8hi_v8hi | |
3288 | = build_function_type (V16QI_type_node, | |
3289 | tree_cons (NULL_TREE, V8HI_type_node, | |
3290 | tree_cons (NULL_TREE, V8HI_type_node, | |
3291 | endlink))); | |
3292 | ||
3293 | tree v4si_ftype_v16qi_v4si | |
3294 | = build_function_type (V4SI_type_node, | |
3295 | tree_cons (NULL_TREE, V16QI_type_node, | |
3296 | tree_cons (NULL_TREE, V4SI_type_node, | |
3297 | endlink))); | |
3298 | ||
3299 | tree v4si_ftype_v8hi_v4si | |
3300 | = build_function_type (V4SI_type_node, | |
3301 | tree_cons (NULL_TREE, V8HI_type_node, | |
3302 | tree_cons (NULL_TREE, V4SI_type_node, | |
3303 | endlink))); | |
3304 | ||
3305 | tree int_ftype_v4si_v4si | |
3306 | = build_function_type (integer_type_node, | |
3307 | tree_cons (NULL_TREE, V4SI_type_node, | |
3308 | tree_cons (NULL_TREE, V4SI_type_node, | |
3309 | endlink))); | |
3310 | ||
3311 | tree int_ftype_v4sf_v4sf | |
3312 | = build_function_type (integer_type_node, | |
3313 | tree_cons (NULL_TREE, V4SF_type_node, | |
3314 | tree_cons (NULL_TREE, V4SF_type_node, | |
3315 | endlink))); | |
3316 | ||
3317 | tree int_ftype_v16qi_v16qi | |
3318 | = build_function_type (integer_type_node, | |
3319 | tree_cons (NULL_TREE, V16QI_type_node, | |
3320 | tree_cons (NULL_TREE, V16QI_type_node, | |
3321 | endlink))); | |
3322 | ||
3323 | tree int_ftype_v8hi_v8hi | |
3324 | = build_function_type (integer_type_node, | |
3325 | tree_cons (NULL_TREE, V8HI_type_node, | |
3326 | tree_cons (NULL_TREE, V8HI_type_node, | |
3327 | endlink))); | |
3328 | ||
3329 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal", v4si_ftype_pint, ALTIVEC_BUILTIN_LD_INTERNAL); | |
3330 | def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal", void_ftype_pint_v4si, ALTIVEC_BUILTIN_ST_INTERNAL); | |
3331 | ||
3332 | /* Add the simple binary operators. */ | |
00b960c7 AH |
3333 | d = (struct builtin_description *) bdesc_2arg; |
3334 | for (i = 0; i < sizeof (bdesc_2arg) / sizeof *d; i++, d++) | |
0ac081f6 AH |
3335 | { |
3336 | enum machine_mode mode0, mode1, mode2; | |
3337 | tree type; | |
3338 | ||
3339 | if (d->name == 0) | |
3340 | continue; | |
3341 | ||
3342 | mode0 = insn_data[d->icode].operand[0].mode; | |
3343 | mode1 = insn_data[d->icode].operand[1].mode; | |
3344 | mode2 = insn_data[d->icode].operand[2].mode; | |
3345 | ||
3346 | /* When all three operands are of the same mode. */ | |
3347 | if (mode0 == mode1 && mode1 == mode2) | |
3348 | { | |
3349 | switch (mode0) | |
3350 | { | |
3351 | case V4SFmode: | |
3352 | type = v4sf_ftype_v4sf_v4sf; | |
3353 | break; | |
3354 | case V4SImode: | |
3355 | type = v4si_ftype_v4si_v4si; | |
3356 | break; | |
3357 | case V16QImode: | |
3358 | type = v16qi_ftype_v16qi_v16qi; | |
3359 | break; | |
3360 | case V8HImode: | |
3361 | type = v8hi_ftype_v8hi_v8hi; | |
3362 | break; | |
3363 | default: | |
3364 | abort (); | |
3365 | } | |
3366 | } | |
3367 | ||
3368 | /* A few other combos we really don't want to do manually. */ | |
3369 | ||
3370 | /* vint, vfloat, vfloat. */ | |
3371 | else if (mode0 == V4SImode && mode1 == V4SFmode && mode2 == V4SFmode) | |
3372 | type = v4si_ftype_v4sf_v4sf; | |
3373 | ||
3374 | /* vshort, vchar, vchar. */ | |
3375 | else if (mode0 == V8HImode && mode1 == V16QImode && mode2 == V16QImode) | |
3376 | type = v8hi_ftype_v16qi_v16qi; | |
3377 | ||
3378 | /* vint, vshort, vshort. */ | |
3379 | else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V8HImode) | |
3380 | type = v4si_ftype_v8hi_v8hi; | |
3381 | ||
3382 | /* vshort, vint, vint. */ | |
3383 | else if (mode0 == V8HImode && mode1 == V4SImode && mode2 == V4SImode) | |
3384 | type = v8hi_ftype_v4si_v4si; | |
3385 | ||
3386 | /* vchar, vshort, vshort. */ | |
3387 | else if (mode0 == V16QImode && mode1 == V8HImode && mode2 == V8HImode) | |
3388 | type = v16qi_ftype_v8hi_v8hi; | |
3389 | ||
3390 | /* vint, vchar, vint. */ | |
3391 | else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V4SImode) | |
3392 | type = v4si_ftype_v16qi_v4si; | |
3393 | ||
3394 | /* vint, vshort, vint. */ | |
3395 | else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V4SImode) | |
3396 | type = v4si_ftype_v8hi_v4si; | |
3397 | ||
3398 | /* fixme: aldyh */ | |
3399 | /* int, x, x. */ | |
3400 | else if (mode0 == SImode) | |
3401 | { | |
3402 | switch (mode1) | |
3403 | { | |
3404 | case V4SImode: | |
3405 | type = int_ftype_v4si_v4si; | |
3406 | break; | |
3407 | case V4SFmode: | |
3408 | type = int_ftype_v4sf_v4sf; | |
3409 | break; | |
3410 | case V16QImode: | |
3411 | type = int_ftype_v16qi_v16qi; | |
3412 | break; | |
3413 | case V8HImode: | |
3414 | type = int_ftype_v8hi_v8hi; | |
3415 | break; | |
3416 | default: | |
3417 | abort (); | |
3418 | } | |
3419 | } | |
3420 | ||
3421 | else | |
3422 | abort (); | |
3423 | ||
3424 | def_builtin (d->mask, d->name, type, d->code); | |
3425 | } | |
3426 | } | |
3427 | ||
5b5040b9 RK |
3428 | \f |
3429 | /* Generate a memory reference for expand_block_move, copying volatile, | |
3430 | and other bits from an original memory reference. */ | |
3431 | ||
3432 | static rtx | |
3433 | expand_block_move_mem (mode, addr, orig_mem) | |
3434 | enum machine_mode mode; | |
3435 | rtx addr; | |
3436 | rtx orig_mem; | |
3437 | { | |
39403d82 | 3438 | rtx mem = gen_rtx_MEM (mode, addr); |
b6c9286a | 3439 | |
c6df88cb | 3440 | MEM_COPY_ATTRIBUTES (mem, orig_mem); |
5b5040b9 RK |
3441 | return mem; |
3442 | } | |
3443 | ||
7e69e155 MM |
3444 | /* Expand a block move operation, and return 1 if successful. Return 0 |
3445 | if we should let the compiler generate normal code. | |
3446 | ||
3447 | operands[0] is the destination | |
3448 | operands[1] is the source | |
3449 | operands[2] is the length | |
3450 | operands[3] is the alignment */ | |
3451 | ||
3933e0e1 MM |
3452 | #define MAX_MOVE_REG 4 |
3453 | ||
7e69e155 MM |
3454 | int |
3455 | expand_block_move (operands) | |
3456 | rtx operands[]; | |
3457 | { | |
b6c9286a MM |
3458 | rtx orig_dest = operands[0]; |
3459 | rtx orig_src = operands[1]; | |
7e69e155 | 3460 | rtx bytes_rtx = operands[2]; |
7e69e155 | 3461 | rtx align_rtx = operands[3]; |
3933e0e1 | 3462 | int constp = (GET_CODE (bytes_rtx) == CONST_INT); |
5ee95df6 | 3463 | int align; |
3933e0e1 MM |
3464 | int bytes; |
3465 | int offset; | |
3466 | int num_reg; | |
3467 | int i; | |
7e69e155 MM |
3468 | rtx src_reg; |
3469 | rtx dest_reg; | |
3933e0e1 MM |
3470 | rtx src_addr; |
3471 | rtx dest_addr; | |
7e69e155 | 3472 | rtx tmp_reg; |
3933e0e1 | 3473 | rtx stores[MAX_MOVE_REG]; |
7e69e155 MM |
3474 | int move_bytes; |
3475 | ||
3933e0e1 | 3476 | /* If this is not a fixed size move, just call memcpy */ |
cc0d9ba8 | 3477 | if (! constp) |
3933e0e1 MM |
3478 | return 0; |
3479 | ||
5ee95df6 FS |
3480 | /* If this is not a fixed size alignment, abort */ |
3481 | if (GET_CODE (align_rtx) != CONST_INT) | |
3482 | abort (); | |
3483 | align = INTVAL (align_rtx); | |
3484 | ||
7e69e155 | 3485 | /* Anything to move? */ |
3933e0e1 MM |
3486 | bytes = INTVAL (bytes_rtx); |
3487 | if (bytes <= 0) | |
7e69e155 MM |
3488 | return 1; |
3489 | ||
3933e0e1 MM |
3490 | /* Don't support real large moves. If string instructions are not used, |
3491 | then don't generate more than 8 loads. */ | |
3492 | if (TARGET_STRING) | |
3493 | { | |
c81fc13e | 3494 | if (bytes > 8*4) |
3933e0e1 MM |
3495 | return 0; |
3496 | } | |
cc0d9ba8 | 3497 | else if (! STRICT_ALIGNMENT) |
3933e0e1 | 3498 | { |
c81fc13e DE |
3499 | if (TARGET_POWERPC64 && align >= 4) |
3500 | { | |
3501 | if (bytes > 8*8) | |
3502 | return 0; | |
3503 | } | |
3504 | else | |
3505 | if (bytes > 8*4) | |
3506 | return 0; | |
3933e0e1 MM |
3507 | } |
3508 | else if (bytes > 8*align) | |
7e69e155 MM |
3509 | return 0; |
3510 | ||
3511 | /* Move the address into scratch registers. */ | |
b6c9286a MM |
3512 | dest_reg = copy_addr_to_reg (XEXP (orig_dest, 0)); |
3513 | src_reg = copy_addr_to_reg (XEXP (orig_src, 0)); | |
7e69e155 | 3514 | |
3933e0e1 | 3515 | if (TARGET_STRING) /* string instructions are available */ |
7e69e155 | 3516 | { |
3933e0e1 | 3517 | for ( ; bytes > 0; bytes -= move_bytes) |
7e69e155 | 3518 | { |
3933e0e1 | 3519 | if (bytes > 24 /* move up to 32 bytes at a time */ |
cc0d9ba8 DE |
3520 | && ! fixed_regs[5] |
3521 | && ! fixed_regs[6] | |
3522 | && ! fixed_regs[7] | |
3523 | && ! fixed_regs[8] | |
3524 | && ! fixed_regs[9] | |
3525 | && ! fixed_regs[10] | |
3526 | && ! fixed_regs[11] | |
3527 | && ! fixed_regs[12]) | |
3933e0e1 MM |
3528 | { |
3529 | move_bytes = (bytes > 32) ? 32 : bytes; | |
cc0d9ba8 DE |
3530 | emit_insn (gen_movstrsi_8reg (expand_block_move_mem (BLKmode, |
3531 | dest_reg, | |
3532 | orig_dest), | |
3533 | expand_block_move_mem (BLKmode, | |
3534 | src_reg, | |
3535 | orig_src), | |
3536 | GEN_INT ((move_bytes == 32) | |
3537 | ? 0 : move_bytes), | |
4c64a852 | 3538 | align_rtx)); |
3933e0e1 MM |
3539 | } |
3540 | else if (bytes > 16 /* move up to 24 bytes at a time */ | |
f9562f27 DE |
3541 | && ! fixed_regs[5] |
3542 | && ! fixed_regs[6] | |
cc0d9ba8 DE |
3543 | && ! fixed_regs[7] |
3544 | && ! fixed_regs[8] | |
3545 | && ! fixed_regs[9] | |
f9562f27 | 3546 | && ! fixed_regs[10]) |
3933e0e1 MM |
3547 | { |
3548 | move_bytes = (bytes > 24) ? 24 : bytes; | |
cc0d9ba8 DE |
3549 | emit_insn (gen_movstrsi_6reg (expand_block_move_mem (BLKmode, |
3550 | dest_reg, | |
3551 | orig_dest), | |
3552 | expand_block_move_mem (BLKmode, | |
3553 | src_reg, | |
3554 | orig_src), | |
3933e0e1 | 3555 | GEN_INT (move_bytes), |
4c64a852 | 3556 | align_rtx)); |
3933e0e1 MM |
3557 | } |
3558 | else if (bytes > 8 /* move up to 16 bytes at a time */ | |
f9562f27 DE |
3559 | && ! fixed_regs[5] |
3560 | && ! fixed_regs[6] | |
3561 | && ! fixed_regs[7] | |
3562 | && ! fixed_regs[8]) | |
3933e0e1 MM |
3563 | { |
3564 | move_bytes = (bytes > 16) ? 16 : bytes; | |
cc0d9ba8 DE |
3565 | emit_insn (gen_movstrsi_4reg (expand_block_move_mem (BLKmode, |
3566 | dest_reg, | |
3567 | orig_dest), | |
3568 | expand_block_move_mem (BLKmode, | |
3569 | src_reg, | |
3570 | orig_src), | |
3933e0e1 | 3571 | GEN_INT (move_bytes), |
4c64a852 | 3572 | align_rtx)); |
3933e0e1 | 3573 | } |
acad7ed3 | 3574 | else if (bytes >= 8 && TARGET_POWERPC64 |
a4f6c312 | 3575 | /* 64-bit loads and stores require word-aligned |
82e41834 | 3576 | displacements. */ |
a4f6c312 | 3577 | && (align >= 8 || (! STRICT_ALIGNMENT && align >= 4))) |
acad7ed3 DE |
3578 | { |
3579 | move_bytes = 8; | |
3580 | tmp_reg = gen_reg_rtx (DImode); | |
3581 | emit_move_insn (tmp_reg, | |
3582 | expand_block_move_mem (DImode, | |
2eba1afa | 3583 | src_reg, orig_src)); |
acad7ed3 | 3584 | emit_move_insn (expand_block_move_mem (DImode, |
2eba1afa | 3585 | dest_reg, orig_dest), |
acad7ed3 DE |
3586 | tmp_reg); |
3587 | } | |
3588 | else if (bytes > 4) | |
3933e0e1 MM |
3589 | { /* move up to 8 bytes at a time */ |
3590 | move_bytes = (bytes > 8) ? 8 : bytes; | |
cc0d9ba8 DE |
3591 | emit_insn (gen_movstrsi_2reg (expand_block_move_mem (BLKmode, |
3592 | dest_reg, | |
3593 | orig_dest), | |
3594 | expand_block_move_mem (BLKmode, | |
3595 | src_reg, | |
3596 | orig_src), | |
3933e0e1 | 3597 | GEN_INT (move_bytes), |
4c64a852 | 3598 | align_rtx)); |
3933e0e1 | 3599 | } |
cc0d9ba8 | 3600 | else if (bytes >= 4 && (align >= 4 || ! STRICT_ALIGNMENT)) |
3933e0e1 MM |
3601 | { /* move 4 bytes */ |
3602 | move_bytes = 4; | |
3603 | tmp_reg = gen_reg_rtx (SImode); | |
cc0d9ba8 DE |
3604 | emit_move_insn (tmp_reg, |
3605 | expand_block_move_mem (SImode, | |
3606 | src_reg, orig_src)); | |
3607 | emit_move_insn (expand_block_move_mem (SImode, | |
3608 | dest_reg, orig_dest), | |
3609 | tmp_reg); | |
3933e0e1 | 3610 | } |
cc0d9ba8 | 3611 | else if (bytes == 2 && (align >= 2 || ! STRICT_ALIGNMENT)) |
3933e0e1 MM |
3612 | { /* move 2 bytes */ |
3613 | move_bytes = 2; | |
3614 | tmp_reg = gen_reg_rtx (HImode); | |
cc0d9ba8 DE |
3615 | emit_move_insn (tmp_reg, |
3616 | expand_block_move_mem (HImode, | |
3617 | src_reg, orig_src)); | |
3618 | emit_move_insn (expand_block_move_mem (HImode, | |
3619 | dest_reg, orig_dest), | |
3620 | tmp_reg); | |
3933e0e1 MM |
3621 | } |
3622 | else if (bytes == 1) /* move 1 byte */ | |
3623 | { | |
3624 | move_bytes = 1; | |
3625 | tmp_reg = gen_reg_rtx (QImode); | |
cc0d9ba8 DE |
3626 | emit_move_insn (tmp_reg, |
3627 | expand_block_move_mem (QImode, | |
3628 | src_reg, orig_src)); | |
3629 | emit_move_insn (expand_block_move_mem (QImode, | |
3630 | dest_reg, orig_dest), | |
3631 | tmp_reg); | |
3933e0e1 MM |
3632 | } |
3633 | else | |
3634 | { /* move up to 4 bytes at a time */ | |
3635 | move_bytes = (bytes > 4) ? 4 : bytes; | |
cc0d9ba8 DE |
3636 | emit_insn (gen_movstrsi_1reg (expand_block_move_mem (BLKmode, |
3637 | dest_reg, | |
3638 | orig_dest), | |
3639 | expand_block_move_mem (BLKmode, | |
3640 | src_reg, | |
3641 | orig_src), | |
3933e0e1 | 3642 | GEN_INT (move_bytes), |
4c64a852 | 3643 | align_rtx)); |
3933e0e1 | 3644 | } |
4c64a852 | 3645 | |
015892ee RK |
3646 | if (bytes > move_bytes) |
3647 | { | |
cc0d9ba8 DE |
3648 | if (! TARGET_POWERPC64) |
3649 | { | |
3650 | emit_insn (gen_addsi3 (src_reg, src_reg, | |
3651 | GEN_INT (move_bytes))); | |
3652 | emit_insn (gen_addsi3 (dest_reg, dest_reg, | |
3653 | GEN_INT (move_bytes))); | |
3654 | } | |
3655 | else | |
3656 | { | |
3657 | emit_insn (gen_adddi3 (src_reg, src_reg, | |
3658 | GEN_INT (move_bytes))); | |
3659 | emit_insn (gen_adddi3 (dest_reg, dest_reg, | |
3660 | GEN_INT (move_bytes))); | |
3661 | } | |
015892ee | 3662 | } |
4c64a852 | 3663 | } |
3933e0e1 MM |
3664 | } |
3665 | ||
3666 | else /* string instructions not available */ | |
3667 | { | |
3668 | num_reg = offset = 0; | |
3669 | for ( ; bytes > 0; (bytes -= move_bytes), (offset += move_bytes)) | |
7e69e155 | 3670 | { |
3933e0e1 MM |
3671 | /* Calculate the correct offset for src/dest */ |
3672 | if (offset == 0) | |
7e69e155 | 3673 | { |
3933e0e1 MM |
3674 | src_addr = src_reg; |
3675 | dest_addr = dest_reg; | |
3676 | } | |
3677 | else | |
3678 | { | |
c5c76735 JL |
3679 | src_addr = plus_constant (src_reg, offset); |
3680 | dest_addr = plus_constant (dest_reg, offset); | |
3933e0e1 MM |
3681 | } |
3682 | ||
cc0d9ba8 DE |
3683 | /* Generate the appropriate load and store, saving the stores |
3684 | for later. */ | |
3685 | if (bytes >= 8 && TARGET_POWERPC64 | |
a4f6c312 SS |
3686 | /* 64-bit loads and stores require word-aligned |
3687 | displacements. */ | |
cc0d9ba8 | 3688 | && (align >= 8 || (! STRICT_ALIGNMENT && align >= 4))) |
b6c9286a MM |
3689 | { |
3690 | move_bytes = 8; | |
3691 | tmp_reg = gen_reg_rtx (DImode); | |
cc0d9ba8 DE |
3692 | emit_insn (gen_movdi (tmp_reg, |
3693 | expand_block_move_mem (DImode, | |
3694 | src_addr, | |
3695 | orig_src))); | |
3696 | stores[num_reg++] = gen_movdi (expand_block_move_mem (DImode, | |
3697 | dest_addr, | |
3698 | orig_dest), | |
3699 | tmp_reg); | |
b6c9286a | 3700 | } |
cc0d9ba8 | 3701 | else if (bytes >= 4 && (align >= 4 || ! STRICT_ALIGNMENT)) |
3933e0e1 MM |
3702 | { |
3703 | move_bytes = 4; | |
3704 | tmp_reg = gen_reg_rtx (SImode); | |
cc0d9ba8 DE |
3705 | emit_insn (gen_movsi (tmp_reg, |
3706 | expand_block_move_mem (SImode, | |
3707 | src_addr, | |
3708 | orig_src))); | |
3709 | stores[num_reg++] = gen_movsi (expand_block_move_mem (SImode, | |
3710 | dest_addr, | |
3711 | orig_dest), | |
3712 | tmp_reg); | |
3933e0e1 | 3713 | } |
cc0d9ba8 | 3714 | else if (bytes >= 2 && (align >= 2 || ! STRICT_ALIGNMENT)) |
3933e0e1 MM |
3715 | { |
3716 | move_bytes = 2; | |
3717 | tmp_reg = gen_reg_rtx (HImode); | |
c81fc13e | 3718 | emit_insn (gen_movhi (tmp_reg, |
cc0d9ba8 DE |
3719 | expand_block_move_mem (HImode, |
3720 | src_addr, | |
3721 | orig_src))); | |
3722 | stores[num_reg++] = gen_movhi (expand_block_move_mem (HImode, | |
3723 | dest_addr, | |
3724 | orig_dest), | |
3725 | tmp_reg); | |
3933e0e1 MM |
3726 | } |
3727 | else | |
3728 | { | |
3729 | move_bytes = 1; | |
3730 | tmp_reg = gen_reg_rtx (QImode); | |
c81fc13e | 3731 | emit_insn (gen_movqi (tmp_reg, |
cc0d9ba8 DE |
3732 | expand_block_move_mem (QImode, |
3733 | src_addr, | |
3734 | orig_src))); | |
3735 | stores[num_reg++] = gen_movqi (expand_block_move_mem (QImode, | |
3736 | dest_addr, | |
3737 | orig_dest), | |
a4f6c312 | 3738 | tmp_reg); |
3933e0e1 MM |
3739 | } |
3740 | ||
3741 | if (num_reg >= MAX_MOVE_REG) | |
3742 | { | |
3743 | for (i = 0; i < num_reg; i++) | |
3744 | emit_insn (stores[i]); | |
3745 | num_reg = 0; | |
7e69e155 MM |
3746 | } |
3747 | } | |
3933e0e1 | 3748 | |
b6c9286a MM |
3749 | for (i = 0; i < num_reg; i++) |
3750 | emit_insn (stores[i]); | |
7e69e155 MM |
3751 | } |
3752 | ||
3753 | return 1; | |
3754 | } | |
3755 | ||
9878760c RK |
3756 | \f |
3757 | /* Return 1 if OP is a load multiple operation. It is known to be a | |
3758 | PARALLEL and the first section will be tested. */ | |
3759 | ||
3760 | int | |
3761 | load_multiple_operation (op, mode) | |
3762 | rtx op; | |
296b8152 | 3763 | enum machine_mode mode ATTRIBUTE_UNUSED; |
9878760c RK |
3764 | { |
3765 | int count = XVECLEN (op, 0); | |
e2c953b6 | 3766 | unsigned int dest_regno; |
9878760c RK |
3767 | rtx src_addr; |
3768 | int i; | |
3769 | ||
3770 | /* Perform a quick check so we don't blow up below. */ | |
3771 | if (count <= 1 | |
3772 | || GET_CODE (XVECEXP (op, 0, 0)) != SET | |
3773 | || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG | |
3774 | || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM) | |
3775 | return 0; | |
3776 | ||
3777 | dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0))); | |
3778 | src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0); | |
3779 | ||
3780 | for (i = 1; i < count; i++) | |
3781 | { | |
3782 | rtx elt = XVECEXP (op, 0, i); | |
3783 | ||
3784 | if (GET_CODE (elt) != SET | |
3785 | || GET_CODE (SET_DEST (elt)) != REG | |
3786 | || GET_MODE (SET_DEST (elt)) != SImode | |
3787 | || REGNO (SET_DEST (elt)) != dest_regno + i | |
3788 | || GET_CODE (SET_SRC (elt)) != MEM | |
3789 | || GET_MODE (SET_SRC (elt)) != SImode | |
3790 | || GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS | |
3791 | || ! rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr) | |
3792 | || GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT | |
3793 | || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != i * 4) | |
3794 | return 0; | |
3795 | } | |
3796 | ||
3797 | return 1; | |
3798 | } | |
3799 | ||
3800 | /* Similar, but tests for store multiple. Here, the second vector element | |
3801 | is a CLOBBER. It will be tested later. */ | |
3802 | ||
3803 | int | |
3804 | store_multiple_operation (op, mode) | |
3805 | rtx op; | |
296b8152 | 3806 | enum machine_mode mode ATTRIBUTE_UNUSED; |
9878760c RK |
3807 | { |
3808 | int count = XVECLEN (op, 0) - 1; | |
e2c953b6 | 3809 | unsigned int src_regno; |
9878760c RK |
3810 | rtx dest_addr; |
3811 | int i; | |
3812 | ||
3813 | /* Perform a quick check so we don't blow up below. */ | |
3814 | if (count <= 1 | |
3815 | || GET_CODE (XVECEXP (op, 0, 0)) != SET | |
3816 | || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM | |
3817 | || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG) | |
3818 | return 0; | |
3819 | ||
3820 | src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0))); | |
3821 | dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0); | |
3822 | ||
3823 | for (i = 1; i < count; i++) | |
3824 | { | |
3825 | rtx elt = XVECEXP (op, 0, i + 1); | |
3826 | ||
3827 | if (GET_CODE (elt) != SET | |
3828 | || GET_CODE (SET_SRC (elt)) != REG | |
3829 | || GET_MODE (SET_SRC (elt)) != SImode | |
3830 | || REGNO (SET_SRC (elt)) != src_regno + i | |
3831 | || GET_CODE (SET_DEST (elt)) != MEM | |
3832 | || GET_MODE (SET_DEST (elt)) != SImode | |
3833 | || GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS | |
3834 | || ! rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr) | |
3835 | || GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT | |
3836 | || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != i * 4) | |
3837 | return 0; | |
3838 | } | |
3839 | ||
3840 | return 1; | |
3841 | } | |
9ebbca7d | 3842 | |
00b960c7 AH |
3843 | /* Return 1 for a parallel vrsave operation. */ |
3844 | ||
3845 | int | |
3846 | vrsave_operation (op, mode) | |
3847 | rtx op; | |
3848 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
3849 | { | |
3850 | int count = XVECLEN (op, 0); | |
3851 | unsigned int dest_regno, src_regno; | |
3852 | int i; | |
3853 | ||
3854 | if (count <= 1 | |
3855 | || GET_CODE (XVECEXP (op, 0, 0)) != SET | |
3856 | || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG | |
3857 | || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC) | |
3858 | return 0; | |
3859 | ||
3860 | dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0))); | |
3861 | src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0))); | |
3862 | ||
3863 | if (dest_regno != VRSAVE_REGNO | |
3864 | && src_regno != VRSAVE_REGNO) | |
3865 | return 0; | |
3866 | ||
3867 | for (i = 1; i < count; i++) | |
3868 | { | |
3869 | rtx elt = XVECEXP (op, 0, i); | |
3870 | ||
3871 | if (GET_CODE (elt) != CLOBBER) | |
3872 | return 0; | |
3873 | } | |
3874 | ||
3875 | return 1; | |
3876 | } | |
3877 | ||
a4f6c312 | 3878 | /* Return 1 for an PARALLEL suitable for mtcrf. */ |
9ebbca7d GK |
3879 | |
3880 | int | |
3881 | mtcrf_operation (op, mode) | |
3882 | rtx op; | |
3883 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
3884 | { | |
3885 | int count = XVECLEN (op, 0); | |
3886 | int i; | |
9ebbca7d GK |
3887 | rtx src_reg; |
3888 | ||
3889 | /* Perform a quick check so we don't blow up below. */ | |
e35b9579 GK |
3890 | if (count < 1 |
3891 | || GET_CODE (XVECEXP (op, 0, 0)) != SET | |
3892 | || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC | |
3893 | || XVECLEN (SET_SRC (XVECEXP (op, 0, 0)), 0) != 2) | |
9ebbca7d | 3894 | return 0; |
e35b9579 | 3895 | src_reg = XVECEXP (SET_SRC (XVECEXP (op, 0, 0)), 0, 0); |
9ebbca7d GK |
3896 | |
3897 | if (GET_CODE (src_reg) != REG | |
3898 | || GET_MODE (src_reg) != SImode | |
3899 | || ! INT_REGNO_P (REGNO (src_reg))) | |
3900 | return 0; | |
3901 | ||
e35b9579 | 3902 | for (i = 0; i < count; i++) |
9ebbca7d GK |
3903 | { |
3904 | rtx exp = XVECEXP (op, 0, i); | |
3905 | rtx unspec; | |
3906 | int maskval; | |
3907 | ||
3908 | if (GET_CODE (exp) != SET | |
3909 | || GET_CODE (SET_DEST (exp)) != REG | |
3910 | || GET_MODE (SET_DEST (exp)) != CCmode | |
3911 | || ! CR_REGNO_P (REGNO (SET_DEST (exp)))) | |
3912 | return 0; | |
3913 | unspec = SET_SRC (exp); | |
3914 | maskval = 1 << (MAX_CR_REGNO - REGNO (SET_DEST (exp))); | |
9ebbca7d GK |
3915 | |
3916 | if (GET_CODE (unspec) != UNSPEC | |
3917 | || XINT (unspec, 1) != 20 | |
3918 | || XVECLEN (unspec, 0) != 2 | |
3919 | || XVECEXP (unspec, 0, 0) != src_reg | |
3920 | || GET_CODE (XVECEXP (unspec, 0, 1)) != CONST_INT | |
3921 | || INTVAL (XVECEXP (unspec, 0, 1)) != maskval) | |
3922 | return 0; | |
3923 | } | |
e35b9579 | 3924 | return 1; |
9ebbca7d GK |
3925 | } |
3926 | ||
a4f6c312 | 3927 | /* Return 1 for an PARALLEL suitable for lmw. */ |
9ebbca7d GK |
3928 | |
3929 | int | |
3930 | lmw_operation (op, mode) | |
3931 | rtx op; | |
3932 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
3933 | { | |
3934 | int count = XVECLEN (op, 0); | |
e2c953b6 | 3935 | unsigned int dest_regno; |
9ebbca7d | 3936 | rtx src_addr; |
e2c953b6 | 3937 | unsigned int base_regno; |
9ebbca7d GK |
3938 | HOST_WIDE_INT offset; |
3939 | int i; | |
3940 | ||
3941 | /* Perform a quick check so we don't blow up below. */ | |
3942 | if (count <= 1 | |
3943 | || GET_CODE (XVECEXP (op, 0, 0)) != SET | |
3944 | || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG | |
3945 | || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM) | |
3946 | return 0; | |
3947 | ||
3948 | dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0))); | |
3949 | src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0); | |
3950 | ||
3951 | if (dest_regno > 31 | |
e2c953b6 | 3952 | || count != 32 - (int) dest_regno) |
9ebbca7d GK |
3953 | return 0; |
3954 | ||
258bfae2 | 3955 | if (LEGITIMATE_INDIRECT_ADDRESS_P (src_addr, 0)) |
9ebbca7d GK |
3956 | { |
3957 | offset = 0; | |
3958 | base_regno = REGNO (src_addr); | |
3959 | if (base_regno == 0) | |
3960 | return 0; | |
3961 | } | |
258bfae2 | 3962 | else if (LEGITIMATE_OFFSET_ADDRESS_P (SImode, src_addr, 0)) |
9ebbca7d GK |
3963 | { |
3964 | offset = INTVAL (XEXP (src_addr, 1)); | |
3965 | base_regno = REGNO (XEXP (src_addr, 0)); | |
3966 | } | |
3967 | else | |
3968 | return 0; | |
3969 | ||
3970 | for (i = 0; i < count; i++) | |
3971 | { | |
3972 | rtx elt = XVECEXP (op, 0, i); | |
3973 | rtx newaddr; | |
3974 | rtx addr_reg; | |
3975 | HOST_WIDE_INT newoffset; | |
3976 | ||
3977 | if (GET_CODE (elt) != SET | |
3978 | || GET_CODE (SET_DEST (elt)) != REG | |
3979 | || GET_MODE (SET_DEST (elt)) != SImode | |
3980 | || REGNO (SET_DEST (elt)) != dest_regno + i | |
3981 | || GET_CODE (SET_SRC (elt)) != MEM | |
3982 | || GET_MODE (SET_SRC (elt)) != SImode) | |
3983 | return 0; | |
3984 | newaddr = XEXP (SET_SRC (elt), 0); | |
258bfae2 | 3985 | if (LEGITIMATE_INDIRECT_ADDRESS_P (newaddr, 0)) |
9ebbca7d GK |
3986 | { |
3987 | newoffset = 0; | |
3988 | addr_reg = newaddr; | |
3989 | } | |
258bfae2 | 3990 | else if (LEGITIMATE_OFFSET_ADDRESS_P (SImode, newaddr, 0)) |
9ebbca7d GK |
3991 | { |
3992 | addr_reg = XEXP (newaddr, 0); | |
3993 | newoffset = INTVAL (XEXP (newaddr, 1)); | |
3994 | } | |
3995 | else | |
3996 | return 0; | |
3997 | if (REGNO (addr_reg) != base_regno | |
3998 | || newoffset != offset + 4 * i) | |
3999 | return 0; | |
4000 | } | |
4001 | ||
4002 | return 1; | |
4003 | } | |
4004 | ||
a4f6c312 | 4005 | /* Return 1 for an PARALLEL suitable for stmw. */ |
9ebbca7d GK |
4006 | |
4007 | int | |
4008 | stmw_operation (op, mode) | |
4009 | rtx op; | |
4010 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
4011 | { | |
4012 | int count = XVECLEN (op, 0); | |
e2c953b6 | 4013 | unsigned int src_regno; |
9ebbca7d | 4014 | rtx dest_addr; |
e2c953b6 | 4015 | unsigned int base_regno; |
9ebbca7d GK |
4016 | HOST_WIDE_INT offset; |
4017 | int i; | |
4018 | ||
4019 | /* Perform a quick check so we don't blow up below. */ | |
4020 | if (count <= 1 | |
4021 | || GET_CODE (XVECEXP (op, 0, 0)) != SET | |
4022 | || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM | |
4023 | || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG) | |
4024 | return 0; | |
4025 | ||
4026 | src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0))); | |
4027 | dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0); | |
4028 | ||
4029 | if (src_regno > 31 | |
e2c953b6 | 4030 | || count != 32 - (int) src_regno) |
9ebbca7d GK |
4031 | return 0; |
4032 | ||
258bfae2 | 4033 | if (LEGITIMATE_INDIRECT_ADDRESS_P (dest_addr, 0)) |
9ebbca7d GK |
4034 | { |
4035 | offset = 0; | |
4036 | base_regno = REGNO (dest_addr); | |
4037 | if (base_regno == 0) | |
4038 | return 0; | |
4039 | } | |
258bfae2 | 4040 | else if (LEGITIMATE_OFFSET_ADDRESS_P (SImode, dest_addr, 0)) |
9ebbca7d GK |
4041 | { |
4042 | offset = INTVAL (XEXP (dest_addr, 1)); | |
4043 | base_regno = REGNO (XEXP (dest_addr, 0)); | |
4044 | } | |
4045 | else | |
4046 | return 0; | |
4047 | ||
4048 | for (i = 0; i < count; i++) | |
4049 | { | |
4050 | rtx elt = XVECEXP (op, 0, i); | |
4051 | rtx newaddr; | |
4052 | rtx addr_reg; | |
4053 | HOST_WIDE_INT newoffset; | |
4054 | ||
4055 | if (GET_CODE (elt) != SET | |
4056 | || GET_CODE (SET_SRC (elt)) != REG | |
4057 | || GET_MODE (SET_SRC (elt)) != SImode | |
4058 | || REGNO (SET_SRC (elt)) != src_regno + i | |
4059 | || GET_CODE (SET_DEST (elt)) != MEM | |
4060 | || GET_MODE (SET_DEST (elt)) != SImode) | |
4061 | return 0; | |
4062 | newaddr = XEXP (SET_DEST (elt), 0); | |
258bfae2 | 4063 | if (LEGITIMATE_INDIRECT_ADDRESS_P (newaddr, 0)) |
9ebbca7d GK |
4064 | { |
4065 | newoffset = 0; | |
4066 | addr_reg = newaddr; | |
4067 | } | |
258bfae2 | 4068 | else if (LEGITIMATE_OFFSET_ADDRESS_P (SImode, newaddr, 0)) |
9ebbca7d GK |
4069 | { |
4070 | addr_reg = XEXP (newaddr, 0); | |
4071 | newoffset = INTVAL (XEXP (newaddr, 1)); | |
4072 | } | |
4073 | else | |
4074 | return 0; | |
4075 | if (REGNO (addr_reg) != base_regno | |
4076 | || newoffset != offset + 4 * i) | |
4077 | return 0; | |
4078 | } | |
4079 | ||
4080 | return 1; | |
4081 | } | |
9878760c | 4082 | \f |
a4f6c312 SS |
4083 | /* A validation routine: say whether CODE, a condition code, and MODE |
4084 | match. The other alternatives either don't make sense or should | |
4085 | never be generated. */ | |
39a10a29 | 4086 | |
39a10a29 GK |
4087 | static void |
4088 | validate_condition_mode (code, mode) | |
4089 | enum rtx_code code; | |
4090 | enum machine_mode mode; | |
4091 | { | |
4092 | if (GET_RTX_CLASS (code) != '<' | |
4093 | || GET_MODE_CLASS (mode) != MODE_CC) | |
4094 | abort (); | |
4095 | ||
4096 | /* These don't make sense. */ | |
4097 | if ((code == GT || code == LT || code == GE || code == LE) | |
4098 | && mode == CCUNSmode) | |
4099 | abort (); | |
4100 | ||
4101 | if ((code == GTU || code == LTU || code == GEU || code == LEU) | |
4102 | && mode != CCUNSmode) | |
4103 | abort (); | |
4104 | ||
4105 | if (mode != CCFPmode | |
4106 | && (code == ORDERED || code == UNORDERED | |
4107 | || code == UNEQ || code == LTGT | |
4108 | || code == UNGT || code == UNLT | |
4109 | || code == UNGE || code == UNLE)) | |
a4f6c312 | 4110 | abort (); |
39a10a29 | 4111 | |
de6c5979 BL |
4112 | /* These should never be generated except for |
4113 | flag_unsafe_math_optimizations. */ | |
39a10a29 | 4114 | if (mode == CCFPmode |
de6c5979 | 4115 | && ! flag_unsafe_math_optimizations |
39a10a29 GK |
4116 | && (code == LE || code == GE |
4117 | || code == UNEQ || code == LTGT | |
4118 | || code == UNGT || code == UNLT)) | |
4119 | abort (); | |
4120 | ||
4121 | /* These are invalid; the information is not there. */ | |
4122 | if (mode == CCEQmode | |
4123 | && code != EQ && code != NE) | |
4124 | abort (); | |
4125 | } | |
4126 | ||
9878760c RK |
4127 | /* Return 1 if OP is a comparison operation that is valid for a branch insn. |
4128 | We only check the opcode against the mode of the CC value here. */ | |
4129 | ||
4130 | int | |
4131 | branch_comparison_operator (op, mode) | |
592696dd | 4132 | rtx op; |
296b8152 | 4133 | enum machine_mode mode ATTRIBUTE_UNUSED; |
9878760c RK |
4134 | { |
4135 | enum rtx_code code = GET_CODE (op); | |
4136 | enum machine_mode cc_mode; | |
4137 | ||
4138 | if (GET_RTX_CLASS (code) != '<') | |
4139 | return 0; | |
4140 | ||
4141 | cc_mode = GET_MODE (XEXP (op, 0)); | |
4142 | if (GET_MODE_CLASS (cc_mode) != MODE_CC) | |
4143 | return 0; | |
4144 | ||
39a10a29 | 4145 | validate_condition_mode (code, cc_mode); |
9878760c | 4146 | |
39a10a29 GK |
4147 | return 1; |
4148 | } | |
4149 | ||
4150 | /* Return 1 if OP is a comparison operation that is valid for a branch | |
4151 | insn and which is true if the corresponding bit in the CC register | |
4152 | is set. */ | |
4153 | ||
4154 | int | |
4155 | branch_positive_comparison_operator (op, mode) | |
592696dd | 4156 | rtx op; |
39a10a29 GK |
4157 | enum machine_mode mode; |
4158 | { | |
4159 | enum rtx_code code; | |
4160 | ||
4161 | if (! branch_comparison_operator (op, mode)) | |
9878760c RK |
4162 | return 0; |
4163 | ||
39a10a29 GK |
4164 | code = GET_CODE (op); |
4165 | return (code == EQ || code == LT || code == GT | |
4166 | || code == LTU || code == GTU | |
4167 | || code == UNORDERED); | |
9878760c RK |
4168 | } |
4169 | ||
4170 | /* Return 1 if OP is a comparison operation that is valid for an scc insn. | |
4171 | We check the opcode against the mode of the CC value and disallow EQ or | |
4172 | NE comparisons for integers. */ | |
4173 | ||
4174 | int | |
4175 | scc_comparison_operator (op, mode) | |
592696dd | 4176 | rtx op; |
9878760c RK |
4177 | enum machine_mode mode; |
4178 | { | |
4179 | enum rtx_code code = GET_CODE (op); | |
4180 | enum machine_mode cc_mode; | |
4181 | ||
4182 | if (GET_MODE (op) != mode && mode != VOIDmode) | |
4183 | return 0; | |
4184 | ||
4185 | if (GET_RTX_CLASS (code) != '<') | |
4186 | return 0; | |
4187 | ||
4188 | cc_mode = GET_MODE (XEXP (op, 0)); | |
4189 | if (GET_MODE_CLASS (cc_mode) != MODE_CC) | |
4190 | return 0; | |
4191 | ||
39a10a29 | 4192 | validate_condition_mode (code, cc_mode); |
9878760c | 4193 | |
39a10a29 | 4194 | if (code == NE && cc_mode != CCFPmode) |
c5defebb RK |
4195 | return 0; |
4196 | ||
9878760c RK |
4197 | return 1; |
4198 | } | |
e0cd0770 JC |
4199 | |
4200 | int | |
4201 | trap_comparison_operator (op, mode) | |
4202 | rtx op; | |
4203 | enum machine_mode mode; | |
4204 | { | |
4205 | if (mode != VOIDmode && mode != GET_MODE (op)) | |
4206 | return 0; | |
39a10a29 | 4207 | return GET_RTX_CLASS (GET_CODE (op)) == '<'; |
e0cd0770 | 4208 | } |
dfbdccdb GK |
4209 | |
4210 | int | |
4211 | boolean_operator (op, mode) | |
4212 | rtx op; | |
4213 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
4214 | { | |
4215 | enum rtx_code code = GET_CODE (op); | |
4216 | return (code == AND || code == IOR || code == XOR); | |
4217 | } | |
1d328b19 GK |
4218 | |
4219 | int | |
4220 | boolean_or_operator (op, mode) | |
4221 | rtx op; | |
4222 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
4223 | { | |
4224 | enum rtx_code code = GET_CODE (op); | |
4225 | return (code == IOR || code == XOR); | |
4226 | } | |
50a0b056 GK |
4227 | |
4228 | int | |
4229 | min_max_operator (op, mode) | |
4230 | rtx op; | |
4231 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
4232 | { | |
4233 | enum rtx_code code = GET_CODE (op); | |
4234 | return (code == SMIN || code == SMAX || code == UMIN || code == UMAX); | |
4235 | } | |
9878760c RK |
4236 | \f |
4237 | /* Return 1 if ANDOP is a mask that has no bits on that are not in the | |
4238 | mask required to convert the result of a rotate insn into a shift | |
4239 | left insn of SHIFTOP bits. Both are known to be CONST_INT. */ | |
4240 | ||
4241 | int | |
4242 | includes_lshift_p (shiftop, andop) | |
592696dd SS |
4243 | rtx shiftop; |
4244 | rtx andop; | |
9878760c | 4245 | { |
e2c953b6 DE |
4246 | unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0; |
4247 | ||
4248 | shift_mask <<= INTVAL (shiftop); | |
9878760c RK |
4249 | |
4250 | return (INTVAL (andop) & ~shift_mask) == 0; | |
4251 | } | |
4252 | ||
4253 | /* Similar, but for right shift. */ | |
4254 | ||
4255 | int | |
4256 | includes_rshift_p (shiftop, andop) | |
592696dd SS |
4257 | rtx shiftop; |
4258 | rtx andop; | |
9878760c | 4259 | { |
a7653a2c | 4260 | unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0; |
9878760c RK |
4261 | |
4262 | shift_mask >>= INTVAL (shiftop); | |
4263 | ||
e2c953b6 DE |
4264 | return (INTVAL (andop) & ~shift_mask) == 0; |
4265 | } | |
4266 | ||
c5059423 AM |
4267 | /* Return 1 if ANDOP is a mask suitable for use with an rldic insn |
4268 | to perform a left shift. It must have exactly SHIFTOP least | |
4269 | signifigant 0's, then one or more 1's, then zero or more 0's. */ | |
e2c953b6 DE |
4270 | |
4271 | int | |
c5059423 | 4272 | includes_rldic_lshift_p (shiftop, andop) |
592696dd SS |
4273 | rtx shiftop; |
4274 | rtx andop; | |
e2c953b6 | 4275 | { |
c5059423 AM |
4276 | if (GET_CODE (andop) == CONST_INT) |
4277 | { | |
02071907 | 4278 | HOST_WIDE_INT c, lsb, shift_mask; |
e2c953b6 | 4279 | |
c5059423 | 4280 | c = INTVAL (andop); |
02071907 | 4281 | if (c == 0 || c == ~0) |
c5059423 | 4282 | return 0; |
e2c953b6 | 4283 | |
02071907 | 4284 | shift_mask = ~0; |
c5059423 AM |
4285 | shift_mask <<= INTVAL (shiftop); |
4286 | ||
4287 | /* Find the least signifigant one bit. */ | |
4288 | lsb = c & -c; | |
4289 | ||
4290 | /* It must coincide with the LSB of the shift mask. */ | |
4291 | if (-lsb != shift_mask) | |
4292 | return 0; | |
e2c953b6 | 4293 | |
c5059423 AM |
4294 | /* Invert to look for the next transition (if any). */ |
4295 | c = ~c; | |
4296 | ||
4297 | /* Remove the low group of ones (originally low group of zeros). */ | |
4298 | c &= -lsb; | |
4299 | ||
4300 | /* Again find the lsb, and check we have all 1's above. */ | |
4301 | lsb = c & -c; | |
4302 | return c == -lsb; | |
4303 | } | |
4304 | else if (GET_CODE (andop) == CONST_DOUBLE | |
4305 | && (GET_MODE (andop) == VOIDmode || GET_MODE (andop) == DImode)) | |
4306 | { | |
02071907 AM |
4307 | HOST_WIDE_INT low, high, lsb; |
4308 | HOST_WIDE_INT shift_mask_low, shift_mask_high; | |
c5059423 AM |
4309 | |
4310 | low = CONST_DOUBLE_LOW (andop); | |
4311 | if (HOST_BITS_PER_WIDE_INT < 64) | |
4312 | high = CONST_DOUBLE_HIGH (andop); | |
4313 | ||
4314 | if ((low == 0 && (HOST_BITS_PER_WIDE_INT >= 64 || high == 0)) | |
02071907 | 4315 | || (low == ~0 && (HOST_BITS_PER_WIDE_INT >= 64 || high == ~0))) |
c5059423 AM |
4316 | return 0; |
4317 | ||
4318 | if (HOST_BITS_PER_WIDE_INT < 64 && low == 0) | |
4319 | { | |
02071907 | 4320 | shift_mask_high = ~0; |
c5059423 AM |
4321 | if (INTVAL (shiftop) > 32) |
4322 | shift_mask_high <<= INTVAL (shiftop) - 32; | |
4323 | ||
4324 | lsb = high & -high; | |
4325 | ||
4326 | if (-lsb != shift_mask_high || INTVAL (shiftop) < 32) | |
4327 | return 0; | |
4328 | ||
4329 | high = ~high; | |
4330 | high &= -lsb; | |
4331 | ||
4332 | lsb = high & -high; | |
4333 | return high == -lsb; | |
4334 | } | |
4335 | ||
02071907 | 4336 | shift_mask_low = ~0; |
c5059423 AM |
4337 | shift_mask_low <<= INTVAL (shiftop); |
4338 | ||
4339 | lsb = low & -low; | |
4340 | ||
4341 | if (-lsb != shift_mask_low) | |
4342 | return 0; | |
4343 | ||
4344 | if (HOST_BITS_PER_WIDE_INT < 64) | |
4345 | high = ~high; | |
4346 | low = ~low; | |
4347 | low &= -lsb; | |
4348 | ||
4349 | if (HOST_BITS_PER_WIDE_INT < 64 && low == 0) | |
4350 | { | |
4351 | lsb = high & -high; | |
4352 | return high == -lsb; | |
4353 | } | |
4354 | ||
4355 | lsb = low & -low; | |
4356 | return low == -lsb && (HOST_BITS_PER_WIDE_INT >= 64 || high == ~0); | |
4357 | } | |
4358 | else | |
4359 | return 0; | |
4360 | } | |
e2c953b6 | 4361 | |
c5059423 AM |
4362 | /* Return 1 if ANDOP is a mask suitable for use with an rldicr insn |
4363 | to perform a left shift. It must have SHIFTOP or more least | |
4364 | signifigant 0's, with the remainder of the word 1's. */ | |
e2c953b6 | 4365 | |
c5059423 AM |
4366 | int |
4367 | includes_rldicr_lshift_p (shiftop, andop) | |
592696dd SS |
4368 | rtx shiftop; |
4369 | rtx andop; | |
c5059423 | 4370 | { |
e2c953b6 | 4371 | if (GET_CODE (andop) == CONST_INT) |
c5059423 | 4372 | { |
02071907 | 4373 | HOST_WIDE_INT c, lsb, shift_mask; |
c5059423 | 4374 | |
02071907 | 4375 | shift_mask = ~0; |
c5059423 AM |
4376 | shift_mask <<= INTVAL (shiftop); |
4377 | c = INTVAL (andop); | |
4378 | ||
4379 | /* Find the least signifigant one bit. */ | |
4380 | lsb = c & -c; | |
4381 | ||
4382 | /* It must be covered by the shift mask. | |
a4f6c312 | 4383 | This test also rejects c == 0. */ |
c5059423 AM |
4384 | if ((lsb & shift_mask) == 0) |
4385 | return 0; | |
4386 | ||
4387 | /* Check we have all 1's above the transition, and reject all 1's. */ | |
4388 | return c == -lsb && lsb != 1; | |
4389 | } | |
4390 | else if (GET_CODE (andop) == CONST_DOUBLE | |
4391 | && (GET_MODE (andop) == VOIDmode || GET_MODE (andop) == DImode)) | |
4392 | { | |
02071907 | 4393 | HOST_WIDE_INT low, lsb, shift_mask_low; |
c5059423 AM |
4394 | |
4395 | low = CONST_DOUBLE_LOW (andop); | |
4396 | ||
4397 | if (HOST_BITS_PER_WIDE_INT < 64) | |
4398 | { | |
02071907 | 4399 | HOST_WIDE_INT high, shift_mask_high; |
c5059423 AM |
4400 | |
4401 | high = CONST_DOUBLE_HIGH (andop); | |
4402 | ||
4403 | if (low == 0) | |
4404 | { | |
02071907 | 4405 | shift_mask_high = ~0; |
c5059423 AM |
4406 | if (INTVAL (shiftop) > 32) |
4407 | shift_mask_high <<= INTVAL (shiftop) - 32; | |
4408 | ||
4409 | lsb = high & -high; | |
4410 | ||
4411 | if ((lsb & shift_mask_high) == 0) | |
4412 | return 0; | |
4413 | ||
4414 | return high == -lsb; | |
4415 | } | |
4416 | if (high != ~0) | |
4417 | return 0; | |
4418 | } | |
4419 | ||
02071907 | 4420 | shift_mask_low = ~0; |
c5059423 AM |
4421 | shift_mask_low <<= INTVAL (shiftop); |
4422 | ||
4423 | lsb = low & -low; | |
4424 | ||
4425 | if ((lsb & shift_mask_low) == 0) | |
4426 | return 0; | |
4427 | ||
4428 | return low == -lsb && lsb != 1; | |
4429 | } | |
e2c953b6 | 4430 | else |
c5059423 | 4431 | return 0; |
9878760c | 4432 | } |
35068b43 RK |
4433 | |
4434 | /* Return 1 if REGNO (reg1) == REGNO (reg2) - 1 making them candidates | |
4435 | for lfq and stfq insns. | |
4436 | ||
4437 | Note reg1 and reg2 *must* be hard registers. To be sure we will | |
4438 | abort if we are passed pseudo registers. */ | |
4439 | ||
4440 | int | |
4441 | registers_ok_for_quad_peep (reg1, reg2) | |
4442 | rtx reg1, reg2; | |
4443 | { | |
4444 | /* We might have been passed a SUBREG. */ | |
4445 | if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG) | |
4446 | return 0; | |
4447 | ||
4448 | return (REGNO (reg1) == REGNO (reg2) - 1); | |
4449 | } | |
4450 | ||
a4f6c312 SS |
4451 | /* Return 1 if addr1 and addr2 are suitable for lfq or stfq insn. |
4452 | addr1 and addr2 must be in consecutive memory locations | |
4453 | (addr2 == addr1 + 8). */ | |
35068b43 RK |
4454 | |
4455 | int | |
4456 | addrs_ok_for_quad_peep (addr1, addr2) | |
592696dd SS |
4457 | rtx addr1; |
4458 | rtx addr2; | |
35068b43 | 4459 | { |
e2c953b6 | 4460 | unsigned int reg1; |
35068b43 RK |
4461 | int offset1; |
4462 | ||
4463 | /* Extract an offset (if used) from the first addr. */ | |
4464 | if (GET_CODE (addr1) == PLUS) | |
4465 | { | |
4466 | /* If not a REG, return zero. */ | |
4467 | if (GET_CODE (XEXP (addr1, 0)) != REG) | |
4468 | return 0; | |
4469 | else | |
4470 | { | |
4471 | reg1 = REGNO (XEXP (addr1, 0)); | |
4472 | /* The offset must be constant! */ | |
4473 | if (GET_CODE (XEXP (addr1, 1)) != CONST_INT) | |
4474 | return 0; | |
4475 | offset1 = INTVAL (XEXP (addr1, 1)); | |
4476 | } | |
4477 | } | |
4478 | else if (GET_CODE (addr1) != REG) | |
4479 | return 0; | |
4480 | else | |
4481 | { | |
4482 | reg1 = REGNO (addr1); | |
4483 | /* This was a simple (mem (reg)) expression. Offset is 0. */ | |
4484 | offset1 = 0; | |
4485 | } | |
4486 | ||
acad7ed3 | 4487 | /* Make sure the second address is a (mem (plus (reg) (const_int))). */ |
35068b43 RK |
4488 | if (GET_CODE (addr2) != PLUS) |
4489 | return 0; | |
4490 | ||
4491 | if (GET_CODE (XEXP (addr2, 0)) != REG | |
4492 | || GET_CODE (XEXP (addr2, 1)) != CONST_INT) | |
4493 | return 0; | |
4494 | ||
4495 | if (reg1 != REGNO (XEXP (addr2, 0))) | |
4496 | return 0; | |
4497 | ||
4498 | /* The offset for the second addr must be 8 more than the first addr. */ | |
4499 | if (INTVAL (XEXP (addr2, 1)) != offset1 + 8) | |
4500 | return 0; | |
4501 | ||
4502 | /* All the tests passed. addr1 and addr2 are valid for lfq or stfq | |
4503 | instructions. */ | |
4504 | return 1; | |
4505 | } | |
9878760c RK |
4506 | \f |
4507 | /* Return the register class of a scratch register needed to copy IN into | |
4508 | or out of a register in CLASS in MODE. If it can be done directly, | |
4509 | NO_REGS is returned. */ | |
4510 | ||
4511 | enum reg_class | |
4512 | secondary_reload_class (class, mode, in) | |
4513 | enum reg_class class; | |
296b8152 | 4514 | enum machine_mode mode ATTRIBUTE_UNUSED; |
9878760c RK |
4515 | rtx in; |
4516 | { | |
5accd822 | 4517 | int regno; |
9878760c | 4518 | |
46fad5b7 DJ |
4519 | if (TARGET_ELF || (DEFAULT_ABI == ABI_DARWIN && flag_pic)) |
4520 | { | |
4521 | /* We cannot copy a symbolic operand directly into anything | |
4522 | other than BASE_REGS for TARGET_ELF. So indicate that a | |
4523 | register from BASE_REGS is needed as an intermediate | |
4524 | register. | |
4525 | ||
4526 | On Darwin, pic addresses require a load from memory, which | |
4527 | needs a base register. */ | |
4528 | if (class != BASE_REGS | |
4529 | && (GET_CODE (in) == SYMBOL_REF | |
4530 | || GET_CODE (in) == HIGH | |
4531 | || GET_CODE (in) == LABEL_REF | |
4532 | || GET_CODE (in) == CONST)) | |
4533 | return BASE_REGS; | |
4534 | } | |
e7b7998a | 4535 | |
5accd822 DE |
4536 | if (GET_CODE (in) == REG) |
4537 | { | |
4538 | regno = REGNO (in); | |
4539 | if (regno >= FIRST_PSEUDO_REGISTER) | |
4540 | { | |
4541 | regno = true_regnum (in); | |
4542 | if (regno >= FIRST_PSEUDO_REGISTER) | |
4543 | regno = -1; | |
4544 | } | |
4545 | } | |
4546 | else if (GET_CODE (in) == SUBREG) | |
4547 | { | |
4548 | regno = true_regnum (in); | |
4549 | if (regno >= FIRST_PSEUDO_REGISTER) | |
4550 | regno = -1; | |
4551 | } | |
4552 | else | |
4553 | regno = -1; | |
4554 | ||
9878760c RK |
4555 | /* We can place anything into GENERAL_REGS and can put GENERAL_REGS |
4556 | into anything. */ | |
4557 | if (class == GENERAL_REGS || class == BASE_REGS | |
4558 | || (regno >= 0 && INT_REGNO_P (regno))) | |
4559 | return NO_REGS; | |
4560 | ||
4561 | /* Constants, memory, and FP registers can go into FP registers. */ | |
4562 | if ((regno == -1 || FP_REGNO_P (regno)) | |
4563 | && (class == FLOAT_REGS || class == NON_SPECIAL_REGS)) | |
4564 | return NO_REGS; | |
4565 | ||
0ac081f6 AH |
4566 | /* Memory, and AltiVec registers can go into AltiVec registers. */ |
4567 | if ((regno == -1 || ALTIVEC_REGNO_P (regno)) | |
4568 | && class == ALTIVEC_REGS) | |
4569 | return NO_REGS; | |
4570 | ||
9878760c RK |
4571 | /* We can copy among the CR registers. */ |
4572 | if ((class == CR_REGS || class == CR0_REGS) | |
4573 | && regno >= 0 && CR_REGNO_P (regno)) | |
4574 | return NO_REGS; | |
4575 | ||
4576 | /* Otherwise, we need GENERAL_REGS. */ | |
4577 | return GENERAL_REGS; | |
4578 | } | |
4579 | \f | |
4580 | /* Given a comparison operation, return the bit number in CCR to test. We | |
4581 | know this is a valid comparison. | |
4582 | ||
4583 | SCC_P is 1 if this is for an scc. That means that %D will have been | |
4584 | used instead of %C, so the bits will be in different places. | |
4585 | ||
b4ac57ab | 4586 | Return -1 if OP isn't a valid comparison for some reason. */ |
9878760c RK |
4587 | |
4588 | int | |
4589 | ccr_bit (op, scc_p) | |
592696dd | 4590 | rtx op; |
9878760c RK |
4591 | int scc_p; |
4592 | { | |
4593 | enum rtx_code code = GET_CODE (op); | |
4594 | enum machine_mode cc_mode; | |
4595 | int cc_regnum; | |
4596 | int base_bit; | |
9ebbca7d | 4597 | rtx reg; |
9878760c RK |
4598 | |
4599 | if (GET_RTX_CLASS (code) != '<') | |
4600 | return -1; | |
4601 | ||
9ebbca7d GK |
4602 | reg = XEXP (op, 0); |
4603 | ||
4604 | if (GET_CODE (reg) != REG | |
4605 | || ! CR_REGNO_P (REGNO (reg))) | |
4606 | abort (); | |
4607 | ||
4608 | cc_mode = GET_MODE (reg); | |
4609 | cc_regnum = REGNO (reg); | |
4610 | base_bit = 4 * (cc_regnum - CR0_REGNO); | |
9878760c | 4611 | |
39a10a29 | 4612 | validate_condition_mode (code, cc_mode); |
c5defebb | 4613 | |
9878760c RK |
4614 | switch (code) |
4615 | { | |
4616 | case NE: | |
4617 | return scc_p ? base_bit + 3 : base_bit + 2; | |
4618 | case EQ: | |
4619 | return base_bit + 2; | |
1c882ea4 | 4620 | case GT: case GTU: case UNLE: |
9878760c | 4621 | return base_bit + 1; |
1c882ea4 | 4622 | case LT: case LTU: case UNGE: |
9878760c | 4623 | return base_bit; |
1c882ea4 GK |
4624 | case ORDERED: case UNORDERED: |
4625 | return base_bit + 3; | |
9878760c RK |
4626 | |
4627 | case GE: case GEU: | |
39a10a29 | 4628 | /* If scc, we will have done a cror to put the bit in the |
9878760c RK |
4629 | unordered position. So test that bit. For integer, this is ! LT |
4630 | unless this is an scc insn. */ | |
39a10a29 | 4631 | return scc_p ? base_bit + 3 : base_bit; |
9878760c RK |
4632 | |
4633 | case LE: case LEU: | |
39a10a29 | 4634 | return scc_p ? base_bit + 3 : base_bit + 1; |
1c882ea4 | 4635 | |
9878760c RK |
4636 | default: |
4637 | abort (); | |
4638 | } | |
4639 | } | |
1ff7789b | 4640 | \f |
8d30c4ee | 4641 | /* Return the GOT register. */ |
1ff7789b MM |
4642 | |
4643 | struct rtx_def * | |
4644 | rs6000_got_register (value) | |
5f59ecb7 | 4645 | rtx value ATTRIBUTE_UNUSED; |
1ff7789b | 4646 | { |
a4f6c312 SS |
4647 | /* The second flow pass currently (June 1999) can't update |
4648 | regs_ever_live without disturbing other parts of the compiler, so | |
4649 | update it here to make the prolog/epilogue code happy. */ | |
3cb999d8 | 4650 | if (no_new_pseudos && ! regs_ever_live[PIC_OFFSET_TABLE_REGNUM]) |
8d30c4ee | 4651 | regs_ever_live[PIC_OFFSET_TABLE_REGNUM] = 1; |
1ff7789b | 4652 | |
8d30c4ee | 4653 | current_function_uses_pic_offset_table = 1; |
3cb999d8 | 4654 | |
1ff7789b MM |
4655 | return pic_offset_table_rtx; |
4656 | } | |
a7df97e6 | 4657 | \f |
71f123ca | 4658 | /* Functions to init, mark and free struct machine_function. |
a7df97e6 MM |
4659 | These will be called, via pointer variables, |
4660 | from push_function_context and pop_function_context. */ | |
4661 | ||
00dba523 NC |
4662 | static void |
4663 | rs6000_init_machine_status (p) | |
a7df97e6 MM |
4664 | struct function *p; |
4665 | { | |
71f123ca FS |
4666 | p->machine = (machine_function *) xcalloc (1, sizeof (machine_function)); |
4667 | } | |
a7df97e6 | 4668 | |
00dba523 NC |
4669 | static void |
4670 | rs6000_free_machine_status (p) | |
a7df97e6 MM |
4671 | struct function *p; |
4672 | { | |
00dba523 NC |
4673 | if (p->machine == NULL) |
4674 | return; | |
a7df97e6 | 4675 | |
00dba523 NC |
4676 | free (p->machine); |
4677 | p->machine = NULL; | |
a7df97e6 MM |
4678 | } |
4679 | ||
9878760c RK |
4680 | \f |
4681 | /* Print an operand. Recognize special options, documented below. */ | |
4682 | ||
38c1f2d7 | 4683 | #if TARGET_ELF |
d9407988 | 4684 | #define SMALL_DATA_RELOC ((rs6000_sdata == SDATA_EABI) ? "sda21" : "sdarel") |
8fbd2dc7 | 4685 | #define SMALL_DATA_REG ((rs6000_sdata == SDATA_EABI) ? 0 : 13) |
ba5e43aa MM |
4686 | #else |
4687 | #define SMALL_DATA_RELOC "sda21" | |
8fbd2dc7 | 4688 | #define SMALL_DATA_REG 0 |
ba5e43aa MM |
4689 | #endif |
4690 | ||
9878760c RK |
4691 | void |
4692 | print_operand (file, x, code) | |
4693 | FILE *file; | |
4694 | rtx x; | |
9ebbca7d | 4695 | int code; |
9878760c RK |
4696 | { |
4697 | int i; | |
a260abc9 | 4698 | HOST_WIDE_INT val; |
9878760c RK |
4699 | |
4700 | /* These macros test for integers and extract the low-order bits. */ | |
4701 | #define INT_P(X) \ | |
4702 | ((GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST_DOUBLE) \ | |
4703 | && GET_MODE (X) == VOIDmode) | |
4704 | ||
4705 | #define INT_LOWPART(X) \ | |
4706 | (GET_CODE (X) == CONST_INT ? INTVAL (X) : CONST_DOUBLE_LOW (X)) | |
4707 | ||
4708 | switch (code) | |
4709 | { | |
a8b3aeda | 4710 | case '.': |
a85d226b RK |
4711 | /* Write out an instruction after the call which may be replaced |
4712 | with glue code by the loader. This depends on the AIX version. */ | |
4713 | asm_fprintf (file, RS6000_CALL_GLUE); | |
a8b3aeda RK |
4714 | return; |
4715 | ||
81eace42 GK |
4716 | /* %a is output_address. */ |
4717 | ||
9854d9ed RK |
4718 | case 'A': |
4719 | /* If X is a constant integer whose low-order 5 bits are zero, | |
4720 | write 'l'. Otherwise, write 'r'. This is a kludge to fix a bug | |
76229ac8 | 4721 | in the AIX assembler where "sri" with a zero shift count |
9854d9ed RK |
4722 | write a trash instruction. */ |
4723 | if (GET_CODE (x) == CONST_INT && (INTVAL (x) & 31) == 0) | |
76229ac8 | 4724 | putc ('l', file); |
9854d9ed | 4725 | else |
76229ac8 | 4726 | putc ('r', file); |
9854d9ed RK |
4727 | return; |
4728 | ||
4729 | case 'b': | |
e2c953b6 DE |
4730 | /* If constant, low-order 16 bits of constant, unsigned. |
4731 | Otherwise, write normally. */ | |
4732 | if (INT_P (x)) | |
4733 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 0xffff); | |
4734 | else | |
4735 | print_operand (file, x, 0); | |
cad12a8d RK |
4736 | return; |
4737 | ||
a260abc9 DE |
4738 | case 'B': |
4739 | /* If the low-order bit is zero, write 'r'; otherwise, write 'l' | |
4740 | for 64-bit mask direction. */ | |
296b8152 | 4741 | putc (((INT_LOWPART(x) & 1) == 0 ? 'r' : 'l'), file); |
a238cd8b | 4742 | return; |
a260abc9 | 4743 | |
81eace42 GK |
4744 | /* %c is output_addr_const if a CONSTANT_ADDRESS_P, otherwise |
4745 | output_operand. */ | |
4746 | ||
9854d9ed | 4747 | case 'D': |
39a10a29 GK |
4748 | /* There used to be a comment for 'C' reading "This is an |
4749 | optional cror needed for certain floating-point | |
4750 | comparisons. Otherwise write nothing." */ | |
4751 | ||
9854d9ed RK |
4752 | /* Similar, except that this is for an scc, so we must be able to |
4753 | encode the test in a single bit that is one. We do the above | |
4754 | for any LE, GE, GEU, or LEU and invert the bit for NE. */ | |
4755 | if (GET_CODE (x) == LE || GET_CODE (x) == GE | |
4756 | || GET_CODE (x) == LEU || GET_CODE (x) == GEU) | |
4757 | { | |
9ebbca7d | 4758 | int base_bit = 4 * (REGNO (XEXP (x, 0)) - CR0_REGNO); |
9854d9ed RK |
4759 | |
4760 | fprintf (file, "cror %d,%d,%d\n\t", base_bit + 3, | |
4761 | base_bit + 2, | |
4762 | base_bit + (GET_CODE (x) == GE || GET_CODE (x) == GEU)); | |
4763 | } | |
4764 | ||
4765 | else if (GET_CODE (x) == NE) | |
4766 | { | |
9ebbca7d | 4767 | int base_bit = 4 * (REGNO (XEXP (x, 0)) - CR0_REGNO); |
9854d9ed RK |
4768 | |
4769 | fprintf (file, "crnor %d,%d,%d\n\t", base_bit + 3, | |
4770 | base_bit + 2, base_bit + 2); | |
4771 | } | |
4772 | return; | |
4773 | ||
4774 | case 'E': | |
39a10a29 | 4775 | /* X is a CR register. Print the number of the EQ bit of the CR */ |
9854d9ed RK |
4776 | if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x))) |
4777 | output_operand_lossage ("invalid %%E value"); | |
78fbdbf7 | 4778 | else |
39a10a29 | 4779 | fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO) + 2); |
a85d226b | 4780 | return; |
9854d9ed RK |
4781 | |
4782 | case 'f': | |
4783 | /* X is a CR register. Print the shift count needed to move it | |
4784 | to the high-order four bits. */ | |
4785 | if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x))) | |
4786 | output_operand_lossage ("invalid %%f value"); | |
4787 | else | |
9ebbca7d | 4788 | fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO)); |
9854d9ed RK |
4789 | return; |
4790 | ||
4791 | case 'F': | |
4792 | /* Similar, but print the count for the rotate in the opposite | |
4793 | direction. */ | |
4794 | if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x))) | |
4795 | output_operand_lossage ("invalid %%F value"); | |
4796 | else | |
9ebbca7d | 4797 | fprintf (file, "%d", 32 - 4 * (REGNO (x) - CR0_REGNO)); |
9854d9ed RK |
4798 | return; |
4799 | ||
4800 | case 'G': | |
4801 | /* X is a constant integer. If it is negative, print "m", | |
4802 | otherwise print "z". This is to make a aze or ame insn. */ | |
4803 | if (GET_CODE (x) != CONST_INT) | |
4804 | output_operand_lossage ("invalid %%G value"); | |
4805 | else if (INTVAL (x) >= 0) | |
76229ac8 | 4806 | putc ('z', file); |
9854d9ed | 4807 | else |
76229ac8 | 4808 | putc ('m', file); |
9854d9ed | 4809 | return; |
e2c953b6 | 4810 | |
9878760c | 4811 | case 'h': |
a4f6c312 SS |
4812 | /* If constant, output low-order five bits. Otherwise, write |
4813 | normally. */ | |
9878760c | 4814 | if (INT_P (x)) |
5f59ecb7 | 4815 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 31); |
9878760c RK |
4816 | else |
4817 | print_operand (file, x, 0); | |
4818 | return; | |
4819 | ||
64305719 | 4820 | case 'H': |
a4f6c312 SS |
4821 | /* If constant, output low-order six bits. Otherwise, write |
4822 | normally. */ | |
64305719 | 4823 | if (INT_P (x)) |
5f59ecb7 | 4824 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 63); |
64305719 DE |
4825 | else |
4826 | print_operand (file, x, 0); | |
4827 | return; | |
4828 | ||
9854d9ed RK |
4829 | case 'I': |
4830 | /* Print `i' if this is a constant, else nothing. */ | |
9878760c | 4831 | if (INT_P (x)) |
76229ac8 | 4832 | putc ('i', file); |
9878760c RK |
4833 | return; |
4834 | ||
9854d9ed RK |
4835 | case 'j': |
4836 | /* Write the bit number in CCR for jump. */ | |
4837 | i = ccr_bit (x, 0); | |
4838 | if (i == -1) | |
4839 | output_operand_lossage ("invalid %%j code"); | |
9878760c | 4840 | else |
9854d9ed | 4841 | fprintf (file, "%d", i); |
9878760c RK |
4842 | return; |
4843 | ||
9854d9ed RK |
4844 | case 'J': |
4845 | /* Similar, but add one for shift count in rlinm for scc and pass | |
4846 | scc flag to `ccr_bit'. */ | |
4847 | i = ccr_bit (x, 1); | |
4848 | if (i == -1) | |
4849 | output_operand_lossage ("invalid %%J code"); | |
4850 | else | |
a0466a68 RK |
4851 | /* If we want bit 31, write a shift count of zero, not 32. */ |
4852 | fprintf (file, "%d", i == 31 ? 0 : i + 1); | |
9878760c RK |
4853 | return; |
4854 | ||
9854d9ed RK |
4855 | case 'k': |
4856 | /* X must be a constant. Write the 1's complement of the | |
4857 | constant. */ | |
9878760c | 4858 | if (! INT_P (x)) |
9854d9ed | 4859 | output_operand_lossage ("invalid %%k value"); |
e2c953b6 DE |
4860 | else |
4861 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, ~ INT_LOWPART (x)); | |
9878760c RK |
4862 | return; |
4863 | ||
81eace42 | 4864 | case 'K': |
9ebbca7d GK |
4865 | /* X must be a symbolic constant on ELF. Write an |
4866 | expression suitable for an 'addi' that adds in the low 16 | |
4867 | bits of the MEM. */ | |
4868 | if (GET_CODE (x) != CONST) | |
4869 | { | |
4870 | print_operand_address (file, x); | |
4871 | fputs ("@l", file); | |
4872 | } | |
4873 | else | |
4874 | { | |
4875 | if (GET_CODE (XEXP (x, 0)) != PLUS | |
4876 | || (GET_CODE (XEXP (XEXP (x, 0), 0)) != SYMBOL_REF | |
4877 | && GET_CODE (XEXP (XEXP (x, 0), 0)) != LABEL_REF) | |
4878 | || GET_CODE (XEXP (XEXP (x, 0), 1)) != CONST_INT) | |
53cd5d6c | 4879 | output_operand_lossage ("invalid %%K value"); |
9ebbca7d GK |
4880 | print_operand_address (file, XEXP (XEXP (x, 0), 0)); |
4881 | fputs ("@l", file); | |
4882 | print_operand (file, XEXP (XEXP (x, 0), 1), 0); | |
4883 | } | |
81eace42 GK |
4884 | return; |
4885 | ||
4886 | /* %l is output_asm_label. */ | |
9ebbca7d | 4887 | |
9854d9ed RK |
4888 | case 'L': |
4889 | /* Write second word of DImode or DFmode reference. Works on register | |
4890 | or non-indexed memory only. */ | |
4891 | if (GET_CODE (x) == REG) | |
5ebfb2ba | 4892 | fprintf (file, "%s", reg_names[REGNO (x) + 1]); |
9854d9ed RK |
4893 | else if (GET_CODE (x) == MEM) |
4894 | { | |
4895 | /* Handle possible auto-increment. Since it is pre-increment and | |
1427100a | 4896 | we have already done it, we can just use an offset of word. */ |
9854d9ed RK |
4897 | if (GET_CODE (XEXP (x, 0)) == PRE_INC |
4898 | || GET_CODE (XEXP (x, 0)) == PRE_DEC) | |
ed8908e7 RK |
4899 | output_address (plus_constant (XEXP (XEXP (x, 0), 0), |
4900 | UNITS_PER_WORD)); | |
9854d9ed | 4901 | else |
d7624dc0 RK |
4902 | output_address (XEXP (adjust_address_nv (x, SImode, |
4903 | UNITS_PER_WORD), | |
4904 | 0)); | |
ed8908e7 | 4905 | |
ba5e43aa | 4906 | if (small_data_operand (x, GET_MODE (x))) |
8fbd2dc7 MM |
4907 | fprintf (file, "@%s(%s)", SMALL_DATA_RELOC, |
4908 | reg_names[SMALL_DATA_REG]); | |
9854d9ed | 4909 | } |
9878760c | 4910 | return; |
9854d9ed | 4911 | |
9878760c RK |
4912 | case 'm': |
4913 | /* MB value for a mask operand. */ | |
4914 | if (! mask_operand (x, VOIDmode)) | |
4915 | output_operand_lossage ("invalid %%m value"); | |
4916 | ||
4917 | val = INT_LOWPART (x); | |
4918 | ||
4919 | /* If the high bit is set and the low bit is not, the value is zero. | |
4920 | If the high bit is zero, the value is the first 1 bit we find from | |
4921 | the left. */ | |
0858c623 | 4922 | if ((val & 0x80000000) && ((val & 1) == 0)) |
9878760c | 4923 | { |
19d2d16f | 4924 | putc ('0', file); |
9878760c RK |
4925 | return; |
4926 | } | |
0858c623 | 4927 | else if ((val & 0x80000000) == 0) |
9878760c RK |
4928 | { |
4929 | for (i = 1; i < 32; i++) | |
0858c623 | 4930 | if ((val <<= 1) & 0x80000000) |
9878760c RK |
4931 | break; |
4932 | fprintf (file, "%d", i); | |
4933 | return; | |
4934 | } | |
4935 | ||
4936 | /* Otherwise, look for the first 0 bit from the right. The result is its | |
4937 | number plus 1. We know the low-order bit is one. */ | |
4938 | for (i = 0; i < 32; i++) | |
4939 | if (((val >>= 1) & 1) == 0) | |
4940 | break; | |
4941 | ||
a260abc9 | 4942 | /* If we ended in ...01, i would be 0. The correct value is 31, so |
9878760c RK |
4943 | we want 31 - i. */ |
4944 | fprintf (file, "%d", 31 - i); | |
4945 | return; | |
4946 | ||
4947 | case 'M': | |
4948 | /* ME value for a mask operand. */ | |
4949 | if (! mask_operand (x, VOIDmode)) | |
a260abc9 | 4950 | output_operand_lossage ("invalid %%M value"); |
9878760c RK |
4951 | |
4952 | val = INT_LOWPART (x); | |
4953 | ||
4954 | /* If the low bit is set and the high bit is not, the value is 31. | |
4955 | If the low bit is zero, the value is the first 1 bit we find from | |
4956 | the right. */ | |
0858c623 | 4957 | if ((val & 1) && ((val & 0x80000000) == 0)) |
9878760c | 4958 | { |
76229ac8 | 4959 | fputs ("31", file); |
9878760c RK |
4960 | return; |
4961 | } | |
4962 | else if ((val & 1) == 0) | |
4963 | { | |
4964 | for (i = 0; i < 32; i++) | |
4965 | if ((val >>= 1) & 1) | |
4966 | break; | |
4967 | ||
a260abc9 | 4968 | /* If we had ....10, i would be 0. The result should be |
9878760c RK |
4969 | 30, so we need 30 - i. */ |
4970 | fprintf (file, "%d", 30 - i); | |
4971 | return; | |
4972 | } | |
4973 | ||
4974 | /* Otherwise, look for the first 0 bit from the left. The result is its | |
4975 | number minus 1. We know the high-order bit is one. */ | |
4976 | for (i = 0; i < 32; i++) | |
0858c623 | 4977 | if (((val <<= 1) & 0x80000000) == 0) |
9878760c RK |
4978 | break; |
4979 | ||
4980 | fprintf (file, "%d", i); | |
4981 | return; | |
4982 | ||
81eace42 GK |
4983 | /* %n outputs the negative of its operand. */ |
4984 | ||
9878760c RK |
4985 | case 'N': |
4986 | /* Write the number of elements in the vector times 4. */ | |
4987 | if (GET_CODE (x) != PARALLEL) | |
4988 | output_operand_lossage ("invalid %%N value"); | |
e2c953b6 DE |
4989 | else |
4990 | fprintf (file, "%d", XVECLEN (x, 0) * 4); | |
9878760c RK |
4991 | return; |
4992 | ||
4993 | case 'O': | |
4994 | /* Similar, but subtract 1 first. */ | |
4995 | if (GET_CODE (x) != PARALLEL) | |
1427100a | 4996 | output_operand_lossage ("invalid %%O value"); |
e2c953b6 DE |
4997 | else |
4998 | fprintf (file, "%d", (XVECLEN (x, 0) - 1) * 4); | |
9878760c RK |
4999 | return; |
5000 | ||
9854d9ed RK |
5001 | case 'p': |
5002 | /* X is a CONST_INT that is a power of two. Output the logarithm. */ | |
5003 | if (! INT_P (x) | |
2bfcf297 | 5004 | || INT_LOWPART (x) < 0 |
9854d9ed RK |
5005 | || (i = exact_log2 (INT_LOWPART (x))) < 0) |
5006 | output_operand_lossage ("invalid %%p value"); | |
e2c953b6 DE |
5007 | else |
5008 | fprintf (file, "%d", i); | |
9854d9ed RK |
5009 | return; |
5010 | ||
9878760c RK |
5011 | case 'P': |
5012 | /* The operand must be an indirect memory reference. The result | |
a4f6c312 | 5013 | is the register number. */ |
9878760c RK |
5014 | if (GET_CODE (x) != MEM || GET_CODE (XEXP (x, 0)) != REG |
5015 | || REGNO (XEXP (x, 0)) >= 32) | |
5016 | output_operand_lossage ("invalid %%P value"); | |
e2c953b6 DE |
5017 | else |
5018 | fprintf (file, "%d", REGNO (XEXP (x, 0))); | |
9878760c RK |
5019 | return; |
5020 | ||
dfbdccdb GK |
5021 | case 'q': |
5022 | /* This outputs the logical code corresponding to a boolean | |
5023 | expression. The expression may have one or both operands | |
39a10a29 GK |
5024 | negated (if one, only the first one). For condition register |
5025 | logical operations, it will also treat the negated | |
5026 | CR codes as NOTs, but not handle NOTs of them. */ | |
dfbdccdb | 5027 | { |
63bc1d05 | 5028 | const char *const *t = 0; |
dfbdccdb GK |
5029 | const char *s; |
5030 | enum rtx_code code = GET_CODE (x); | |
5031 | static const char * const tbl[3][3] = { | |
5032 | { "and", "andc", "nor" }, | |
5033 | { "or", "orc", "nand" }, | |
5034 | { "xor", "eqv", "xor" } }; | |
5035 | ||
5036 | if (code == AND) | |
5037 | t = tbl[0]; | |
5038 | else if (code == IOR) | |
5039 | t = tbl[1]; | |
5040 | else if (code == XOR) | |
5041 | t = tbl[2]; | |
5042 | else | |
5043 | output_operand_lossage ("invalid %%q value"); | |
5044 | ||
5045 | if (GET_CODE (XEXP (x, 0)) != NOT) | |
5046 | s = t[0]; | |
5047 | else | |
5048 | { | |
5049 | if (GET_CODE (XEXP (x, 1)) == NOT) | |
5050 | s = t[2]; | |
5051 | else | |
5052 | s = t[1]; | |
5053 | } | |
5054 | ||
5055 | fputs (s, file); | |
5056 | } | |
5057 | return; | |
5058 | ||
9854d9ed RK |
5059 | case 'R': |
5060 | /* X is a CR register. Print the mask for `mtcrf'. */ | |
5061 | if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x))) | |
5062 | output_operand_lossage ("invalid %%R value"); | |
5063 | else | |
9ebbca7d | 5064 | fprintf (file, "%d", 128 >> (REGNO (x) - CR0_REGNO)); |
9878760c | 5065 | return; |
9854d9ed RK |
5066 | |
5067 | case 's': | |
5068 | /* Low 5 bits of 32 - value */ | |
5069 | if (! INT_P (x)) | |
5070 | output_operand_lossage ("invalid %%s value"); | |
e2c953b6 DE |
5071 | else |
5072 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, (32 - INT_LOWPART (x)) & 31); | |
9878760c | 5073 | return; |
9854d9ed | 5074 | |
a260abc9 DE |
5075 | case 'S': |
5076 | /* PowerPC64 mask position. All 0's and all 1's are excluded. | |
5077 | CONST_INT 32-bit mask is considered sign-extended so any | |
5078 | transition must occur within the CONST_INT, not on the boundary. */ | |
5079 | if (! mask64_operand (x, VOIDmode)) | |
5080 | output_operand_lossage ("invalid %%S value"); | |
5081 | ||
5082 | val = INT_LOWPART (x); | |
5083 | ||
5084 | if (val & 1) /* Clear Left */ | |
5085 | { | |
a238cd8b DE |
5086 | for (i = 0; i < HOST_BITS_PER_WIDE_INT; i++) |
5087 | if (!((val >>= 1) & 1)) | |
5088 | break; | |
a260abc9 | 5089 | |
a238cd8b DE |
5090 | #if HOST_BITS_PER_WIDE_INT == 32 |
5091 | if (GET_CODE (x) == CONST_DOUBLE && i == 32) | |
5092 | { | |
5093 | val = CONST_DOUBLE_HIGH (x); | |
5094 | ||
5095 | if (val == 0) | |
5096 | --i; | |
5097 | else | |
5098 | for (i = 32; i < 64; i++) | |
5099 | if (!((val >>= 1) & 1)) | |
5100 | break; | |
5101 | } | |
a260abc9 | 5102 | #endif |
a238cd8b DE |
5103 | /* i = index of last set bit from right |
5104 | mask begins at 63 - i from left */ | |
5105 | if (i > 63) | |
5106 | output_operand_lossage ("%%S computed all 1's mask"); | |
cccf3bdc | 5107 | |
a260abc9 DE |
5108 | fprintf (file, "%d", 63 - i); |
5109 | return; | |
5110 | } | |
5111 | else /* Clear Right */ | |
5112 | { | |
a238cd8b DE |
5113 | for (i = 0; i < HOST_BITS_PER_WIDE_INT; i++) |
5114 | if ((val >>= 1) & 1) | |
5115 | break; | |
a260abc9 | 5116 | |
a238cd8b | 5117 | #if HOST_BITS_PER_WIDE_INT == 32 |
a260abc9 DE |
5118 | if (GET_CODE (x) == CONST_DOUBLE && i == 32) |
5119 | { | |
a238cd8b | 5120 | val = CONST_DOUBLE_HIGH (x); |
a260abc9 | 5121 | |
a238cd8b | 5122 | if (val == (HOST_WIDE_INT) -1) |
a260abc9 | 5123 | --i; |
a260abc9 | 5124 | else |
a238cd8b DE |
5125 | for (i = 32; i < 64; i++) |
5126 | if ((val >>= 1) & 1) | |
a260abc9 DE |
5127 | break; |
5128 | } | |
5129 | #endif | |
a238cd8b DE |
5130 | /* i = index of last clear bit from right |
5131 | mask ends at 62 - i from left */ | |
5132 | if (i > 62) | |
5133 | output_operand_lossage ("%%S computed all 0's mask"); | |
cccf3bdc | 5134 | |
a238cd8b | 5135 | fprintf (file, "%d", 62 - i); |
a260abc9 DE |
5136 | return; |
5137 | } | |
5138 | ||
cccf3bdc DE |
5139 | case 'T': |
5140 | /* Print the symbolic name of a branch target register. */ | |
5141 | if (GET_CODE (x) != REG || (REGNO (x) != LINK_REGISTER_REGNUM | |
5142 | && REGNO (x) != COUNT_REGISTER_REGNUM)) | |
5143 | output_operand_lossage ("invalid %%T value"); | |
e2c953b6 | 5144 | else if (REGNO (x) == LINK_REGISTER_REGNUM) |
cccf3bdc DE |
5145 | fputs (TARGET_NEW_MNEMONICS ? "lr" : "r", file); |
5146 | else | |
5147 | fputs ("ctr", file); | |
5148 | return; | |
5149 | ||
9854d9ed | 5150 | case 'u': |
802a0058 | 5151 | /* High-order 16 bits of constant for use in unsigned operand. */ |
9854d9ed RK |
5152 | if (! INT_P (x)) |
5153 | output_operand_lossage ("invalid %%u value"); | |
e2c953b6 DE |
5154 | else |
5155 | fprintf (file, HOST_WIDE_INT_PRINT_HEX, | |
5156 | (INT_LOWPART (x) >> 16) & 0xffff); | |
9878760c RK |
5157 | return; |
5158 | ||
802a0058 MM |
5159 | case 'v': |
5160 | /* High-order 16 bits of constant for use in signed operand. */ | |
5161 | if (! INT_P (x)) | |
5162 | output_operand_lossage ("invalid %%v value"); | |
e2c953b6 DE |
5163 | else |
5164 | { | |
f607bc57 | 5165 | fprintf (file, "0x%x", (INT_LOWPART (x) >> 16) & 0xffff); |
e2c953b6 DE |
5166 | return; |
5167 | } | |
802a0058 | 5168 | |
9854d9ed RK |
5169 | case 'U': |
5170 | /* Print `u' if this has an auto-increment or auto-decrement. */ | |
5171 | if (GET_CODE (x) == MEM | |
5172 | && (GET_CODE (XEXP (x, 0)) == PRE_INC | |
5173 | || GET_CODE (XEXP (x, 0)) == PRE_DEC)) | |
76229ac8 | 5174 | putc ('u', file); |
9854d9ed | 5175 | return; |
9878760c | 5176 | |
e0cd0770 JC |
5177 | case 'V': |
5178 | /* Print the trap code for this operand. */ | |
5179 | switch (GET_CODE (x)) | |
5180 | { | |
5181 | case EQ: | |
5182 | fputs ("eq", file); /* 4 */ | |
5183 | break; | |
5184 | case NE: | |
5185 | fputs ("ne", file); /* 24 */ | |
5186 | break; | |
5187 | case LT: | |
5188 | fputs ("lt", file); /* 16 */ | |
5189 | break; | |
5190 | case LE: | |
5191 | fputs ("le", file); /* 20 */ | |
5192 | break; | |
5193 | case GT: | |
5194 | fputs ("gt", file); /* 8 */ | |
5195 | break; | |
5196 | case GE: | |
5197 | fputs ("ge", file); /* 12 */ | |
5198 | break; | |
5199 | case LTU: | |
5200 | fputs ("llt", file); /* 2 */ | |
5201 | break; | |
5202 | case LEU: | |
5203 | fputs ("lle", file); /* 6 */ | |
5204 | break; | |
5205 | case GTU: | |
5206 | fputs ("lgt", file); /* 1 */ | |
5207 | break; | |
5208 | case GEU: | |
5209 | fputs ("lge", file); /* 5 */ | |
5210 | break; | |
5211 | default: | |
5212 | abort (); | |
5213 | } | |
5214 | break; | |
5215 | ||
9854d9ed RK |
5216 | case 'w': |
5217 | /* If constant, low-order 16 bits of constant, signed. Otherwise, write | |
5218 | normally. */ | |
5219 | if (INT_P (x)) | |
5f59ecb7 DE |
5220 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, |
5221 | ((INT_LOWPART (x) & 0xffff) ^ 0x8000) - 0x8000); | |
9854d9ed RK |
5222 | else |
5223 | print_operand (file, x, 0); | |
9878760c RK |
5224 | return; |
5225 | ||
9854d9ed | 5226 | case 'W': |
e2c953b6 | 5227 | /* MB value for a PowerPC64 rldic operand. */ |
e2c953b6 DE |
5228 | val = (GET_CODE (x) == CONST_INT |
5229 | ? INTVAL (x) : CONST_DOUBLE_HIGH (x)); | |
5230 | ||
5231 | if (val < 0) | |
5232 | i = -1; | |
9854d9ed | 5233 | else |
e2c953b6 DE |
5234 | for (i = 0; i < HOST_BITS_PER_WIDE_INT; i++) |
5235 | if ((val <<= 1) < 0) | |
5236 | break; | |
5237 | ||
5238 | #if HOST_BITS_PER_WIDE_INT == 32 | |
5239 | if (GET_CODE (x) == CONST_INT && i >= 0) | |
5240 | i += 32; /* zero-extend high-part was all 0's */ | |
5241 | else if (GET_CODE (x) == CONST_DOUBLE && i == 32) | |
5242 | { | |
5243 | val = CONST_DOUBLE_LOW (x); | |
5244 | ||
5245 | if (val == 0) | |
a4f6c312 | 5246 | abort (); |
e2c953b6 DE |
5247 | else if (val < 0) |
5248 | --i; | |
5249 | else | |
5250 | for ( ; i < 64; i++) | |
5251 | if ((val <<= 1) < 0) | |
5252 | break; | |
5253 | } | |
5254 | #endif | |
5255 | ||
5256 | fprintf (file, "%d", i + 1); | |
9854d9ed | 5257 | return; |
9878760c | 5258 | |
9854d9ed RK |
5259 | case 'X': |
5260 | if (GET_CODE (x) == MEM | |
258bfae2 | 5261 | && LEGITIMATE_INDEXED_ADDRESS_P (XEXP (x, 0), 0)) |
76229ac8 | 5262 | putc ('x', file); |
9854d9ed | 5263 | return; |
9878760c | 5264 | |
9854d9ed RK |
5265 | case 'Y': |
5266 | /* Like 'L', for third word of TImode */ | |
5267 | if (GET_CODE (x) == REG) | |
5ebfb2ba | 5268 | fprintf (file, "%s", reg_names[REGNO (x) + 2]); |
9854d9ed | 5269 | else if (GET_CODE (x) == MEM) |
9878760c | 5270 | { |
9854d9ed RK |
5271 | if (GET_CODE (XEXP (x, 0)) == PRE_INC |
5272 | || GET_CODE (XEXP (x, 0)) == PRE_DEC) | |
a54d04b7 | 5273 | output_address (plus_constant (XEXP (XEXP (x, 0), 0), 8)); |
9854d9ed | 5274 | else |
d7624dc0 | 5275 | output_address (XEXP (adjust_address_nv (x, SImode, 8), 0)); |
ba5e43aa | 5276 | if (small_data_operand (x, GET_MODE (x))) |
8fbd2dc7 MM |
5277 | fprintf (file, "@%s(%s)", SMALL_DATA_RELOC, |
5278 | reg_names[SMALL_DATA_REG]); | |
9878760c RK |
5279 | } |
5280 | return; | |
9854d9ed | 5281 | |
9878760c | 5282 | case 'z': |
b4ac57ab RS |
5283 | /* X is a SYMBOL_REF. Write out the name preceded by a |
5284 | period and without any trailing data in brackets. Used for function | |
4d30c363 MM |
5285 | names. If we are configured for System V (or the embedded ABI) on |
5286 | the PowerPC, do not emit the period, since those systems do not use | |
5287 | TOCs and the like. */ | |
9878760c RK |
5288 | if (GET_CODE (x) != SYMBOL_REF) |
5289 | abort (); | |
5290 | ||
b6c9286a MM |
5291 | if (XSTR (x, 0)[0] != '.') |
5292 | { | |
5293 | switch (DEFAULT_ABI) | |
5294 | { | |
5295 | default: | |
5296 | abort (); | |
5297 | ||
5298 | case ABI_AIX: | |
5299 | putc ('.', file); | |
5300 | break; | |
5301 | ||
5302 | case ABI_V4: | |
5303 | case ABI_AIX_NODESC: | |
ee890fe2 | 5304 | case ABI_DARWIN: |
b6c9286a | 5305 | break; |
b6c9286a MM |
5306 | } |
5307 | } | |
54ee9799 DE |
5308 | #if TARGET_AIX |
5309 | RS6000_OUTPUT_BASENAME (file, XSTR (x, 0)); | |
5310 | #else | |
9ebbca7d | 5311 | assemble_name (file, XSTR (x, 0)); |
54ee9799 | 5312 | #endif |
9878760c RK |
5313 | return; |
5314 | ||
9854d9ed RK |
5315 | case 'Z': |
5316 | /* Like 'L', for last word of TImode. */ | |
5317 | if (GET_CODE (x) == REG) | |
5ebfb2ba | 5318 | fprintf (file, "%s", reg_names[REGNO (x) + 3]); |
9854d9ed RK |
5319 | else if (GET_CODE (x) == MEM) |
5320 | { | |
5321 | if (GET_CODE (XEXP (x, 0)) == PRE_INC | |
5322 | || GET_CODE (XEXP (x, 0)) == PRE_DEC) | |
a54d04b7 | 5323 | output_address (plus_constant (XEXP (XEXP (x, 0), 0), 12)); |
9854d9ed | 5324 | else |
d7624dc0 | 5325 | output_address (XEXP (adjust_address_nv (x, SImode, 12), 0)); |
ba5e43aa | 5326 | if (small_data_operand (x, GET_MODE (x))) |
8fbd2dc7 MM |
5327 | fprintf (file, "@%s(%s)", SMALL_DATA_RELOC, |
5328 | reg_names[SMALL_DATA_REG]); | |
9854d9ed | 5329 | } |
5c23c401 | 5330 | return; |
0ac081f6 AH |
5331 | |
5332 | /* Print AltiVec memory operand. */ | |
5333 | case 'y': | |
5334 | { | |
5335 | rtx tmp; | |
5336 | ||
5337 | if (GET_CODE (x) != MEM) | |
5338 | abort (); | |
5339 | ||
5340 | tmp = XEXP (x, 0); | |
5341 | ||
5342 | if (GET_CODE (tmp) == REG) | |
5343 | fprintf (file, "0, %s", reg_names[REGNO (tmp)]); | |
5344 | else if (GET_CODE (tmp) == PLUS && GET_CODE (XEXP (tmp, 1)) == REG) | |
5345 | { | |
5346 | if (REGNO (XEXP (tmp, 0)) == 0) | |
5347 | fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 1)) ], | |
5348 | reg_names[ REGNO (XEXP (tmp, 0)) ]); | |
5349 | else | |
5350 | fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 0)) ], | |
5351 | reg_names[ REGNO (XEXP (tmp, 1)) ]); | |
5352 | } | |
5353 | else | |
5354 | abort (); | |
5355 | break; | |
5356 | } | |
9854d9ed | 5357 | |
9878760c RK |
5358 | case 0: |
5359 | if (GET_CODE (x) == REG) | |
5360 | fprintf (file, "%s", reg_names[REGNO (x)]); | |
5361 | else if (GET_CODE (x) == MEM) | |
5362 | { | |
5363 | /* We need to handle PRE_INC and PRE_DEC here, since we need to | |
5364 | know the width from the mode. */ | |
5365 | if (GET_CODE (XEXP (x, 0)) == PRE_INC) | |
79ba6d34 MM |
5366 | fprintf (file, "%d(%s)", GET_MODE_SIZE (GET_MODE (x)), |
5367 | reg_names[REGNO (XEXP (XEXP (x, 0), 0))]); | |
9878760c | 5368 | else if (GET_CODE (XEXP (x, 0)) == PRE_DEC) |
79ba6d34 MM |
5369 | fprintf (file, "%d(%s)", - GET_MODE_SIZE (GET_MODE (x)), |
5370 | reg_names[REGNO (XEXP (XEXP (x, 0), 0))]); | |
9878760c | 5371 | else |
a54d04b7 | 5372 | output_address (XEXP (x, 0)); |
9878760c RK |
5373 | } |
5374 | else | |
a54d04b7 | 5375 | output_addr_const (file, x); |
a85d226b | 5376 | return; |
9878760c RK |
5377 | |
5378 | default: | |
5379 | output_operand_lossage ("invalid %%xn code"); | |
5380 | } | |
5381 | } | |
5382 | \f | |
5383 | /* Print the address of an operand. */ | |
5384 | ||
5385 | void | |
5386 | print_operand_address (file, x) | |
5387 | FILE *file; | |
592696dd | 5388 | rtx x; |
9878760c RK |
5389 | { |
5390 | if (GET_CODE (x) == REG) | |
4697a36c | 5391 | fprintf (file, "0(%s)", reg_names[ REGNO (x) ]); |
9ebbca7d GK |
5392 | else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST |
5393 | || GET_CODE (x) == LABEL_REF) | |
9878760c RK |
5394 | { |
5395 | output_addr_const (file, x); | |
ba5e43aa | 5396 | if (small_data_operand (x, GET_MODE (x))) |
8fbd2dc7 MM |
5397 | fprintf (file, "@%s(%s)", SMALL_DATA_RELOC, |
5398 | reg_names[SMALL_DATA_REG]); | |
9ebbca7d | 5399 | else if (TARGET_TOC) |
a4f6c312 | 5400 | abort (); |
9878760c RK |
5401 | } |
5402 | else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == REG) | |
5403 | { | |
5404 | if (REGNO (XEXP (x, 0)) == 0) | |
4697a36c MM |
5405 | fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 1)) ], |
5406 | reg_names[ REGNO (XEXP (x, 0)) ]); | |
9878760c | 5407 | else |
4697a36c MM |
5408 | fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 0)) ], |
5409 | reg_names[ REGNO (XEXP (x, 1)) ]); | |
9878760c RK |
5410 | } |
5411 | else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT) | |
5f59ecb7 DE |
5412 | { |
5413 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (XEXP (x, 1))); | |
5414 | fprintf (file, "(%s)", reg_names[ REGNO (XEXP (x, 0)) ]); | |
5415 | } | |
3cb999d8 DE |
5416 | #if TARGET_ELF |
5417 | else if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 0)) == REG | |
5418 | && CONSTANT_P (XEXP (x, 1))) | |
4697a36c MM |
5419 | { |
5420 | output_addr_const (file, XEXP (x, 1)); | |
5421 | fprintf (file, "@l(%s)", reg_names[ REGNO (XEXP (x, 0)) ]); | |
5422 | } | |
3cb999d8 | 5423 | #endif |
9ebbca7d GK |
5424 | else if (LEGITIMATE_CONSTANT_POOL_ADDRESS_P (x)) |
5425 | { | |
2bfcf297 | 5426 | if (TARGET_AIX && (!TARGET_ELF || !TARGET_MINIMAL_TOC)) |
9ebbca7d | 5427 | { |
2bfcf297 DB |
5428 | rtx contains_minus = XEXP (x, 1); |
5429 | rtx minus, symref; | |
5430 | const char *name; | |
9ebbca7d GK |
5431 | |
5432 | /* Find the (minus (sym) (toc)) buried in X, and temporarily | |
a4f6c312 | 5433 | turn it into (sym) for output_addr_const. */ |
9ebbca7d GK |
5434 | while (GET_CODE (XEXP (contains_minus, 0)) != MINUS) |
5435 | contains_minus = XEXP (contains_minus, 0); | |
5436 | ||
2bfcf297 DB |
5437 | minus = XEXP (contains_minus, 0); |
5438 | symref = XEXP (minus, 0); | |
5439 | XEXP (contains_minus, 0) = symref; | |
5440 | if (TARGET_ELF) | |
5441 | { | |
5442 | char *newname; | |
5443 | ||
5444 | name = XSTR (symref, 0); | |
5445 | newname = alloca (strlen (name) + sizeof ("@toc")); | |
5446 | strcpy (newname, name); | |
5447 | strcat (newname, "@toc"); | |
5448 | XSTR (symref, 0) = newname; | |
5449 | } | |
5450 | output_addr_const (file, XEXP (x, 1)); | |
5451 | if (TARGET_ELF) | |
5452 | XSTR (symref, 0) = name; | |
9ebbca7d GK |
5453 | XEXP (contains_minus, 0) = minus; |
5454 | } | |
5455 | else | |
5456 | output_addr_const (file, XEXP (x, 1)); | |
5457 | ||
5458 | fprintf (file, "(%s)", reg_names[REGNO (XEXP (x, 0))]); | |
5459 | } | |
9878760c RK |
5460 | else |
5461 | abort (); | |
5462 | } | |
5463 | \f | |
39a10a29 GK |
5464 | enum rtx_code |
5465 | rs6000_reverse_condition (mode, code) | |
5466 | enum machine_mode mode; | |
5467 | enum rtx_code code; | |
5468 | { | |
5469 | /* Reversal of FP compares takes care -- an ordered compare | |
5470 | becomes an unordered compare and vice versa. */ | |
5471 | if (mode == CCFPmode) | |
bab6226b | 5472 | return reverse_condition_maybe_unordered (code); |
39a10a29 | 5473 | else |
bab6226b | 5474 | return reverse_condition (code); |
39a10a29 GK |
5475 | } |
5476 | ||
39a10a29 GK |
5477 | /* Generate a compare for CODE. Return a brand-new rtx that |
5478 | represents the result of the compare. */ | |
a4f6c312 | 5479 | |
39a10a29 GK |
5480 | static rtx |
5481 | rs6000_generate_compare (code) | |
5482 | enum rtx_code code; | |
5483 | { | |
5484 | enum machine_mode comp_mode; | |
5485 | rtx compare_result; | |
5486 | ||
5487 | if (rs6000_compare_fp_p) | |
5488 | comp_mode = CCFPmode; | |
5489 | else if (code == GTU || code == LTU | |
5490 | || code == GEU || code == LEU) | |
5491 | comp_mode = CCUNSmode; | |
5492 | else | |
5493 | comp_mode = CCmode; | |
5494 | ||
5495 | /* First, the compare. */ | |
5496 | compare_result = gen_reg_rtx (comp_mode); | |
5497 | emit_insn (gen_rtx_SET (VOIDmode, compare_result, | |
5498 | gen_rtx_COMPARE (comp_mode, | |
5499 | rs6000_compare_op0, | |
5500 | rs6000_compare_op1))); | |
5501 | ||
ca5adc63 | 5502 | /* Some kinds of FP comparisons need an OR operation; |
de6c5979 | 5503 | except for flag_unsafe_math_optimizations we don't bother. */ |
39a10a29 | 5504 | if (rs6000_compare_fp_p |
de6c5979 | 5505 | && ! flag_unsafe_math_optimizations |
39a10a29 GK |
5506 | && (code == LE || code == GE |
5507 | || code == UNEQ || code == LTGT | |
5508 | || code == UNGT || code == UNLT)) | |
5509 | { | |
5510 | enum rtx_code or1, or2; | |
5511 | rtx or1_rtx, or2_rtx, compare2_rtx; | |
5512 | rtx or_result = gen_reg_rtx (CCEQmode); | |
5513 | ||
5514 | switch (code) | |
5515 | { | |
5516 | case LE: or1 = LT; or2 = EQ; break; | |
5517 | case GE: or1 = GT; or2 = EQ; break; | |
5518 | case UNEQ: or1 = UNORDERED; or2 = EQ; break; | |
5519 | case LTGT: or1 = LT; or2 = GT; break; | |
5520 | case UNGT: or1 = UNORDERED; or2 = GT; break; | |
5521 | case UNLT: or1 = UNORDERED; or2 = LT; break; | |
5522 | default: abort (); | |
5523 | } | |
5524 | validate_condition_mode (or1, comp_mode); | |
5525 | validate_condition_mode (or2, comp_mode); | |
5526 | or1_rtx = gen_rtx (or1, SImode, compare_result, const0_rtx); | |
5527 | or2_rtx = gen_rtx (or2, SImode, compare_result, const0_rtx); | |
5528 | compare2_rtx = gen_rtx_COMPARE (CCEQmode, | |
5529 | gen_rtx_IOR (SImode, or1_rtx, or2_rtx), | |
5530 | const_true_rtx); | |
5531 | emit_insn (gen_rtx_SET (VOIDmode, or_result, compare2_rtx)); | |
5532 | ||
5533 | compare_result = or_result; | |
5534 | code = EQ; | |
5535 | } | |
5536 | ||
5537 | validate_condition_mode (code, GET_MODE (compare_result)); | |
5538 | ||
5539 | return gen_rtx (code, VOIDmode, compare_result, const0_rtx); | |
5540 | } | |
5541 | ||
5542 | ||
5543 | /* Emit the RTL for an sCOND pattern. */ | |
5544 | ||
5545 | void | |
5546 | rs6000_emit_sCOND (code, result) | |
5547 | enum rtx_code code; | |
5548 | rtx result; | |
5549 | { | |
5550 | rtx condition_rtx; | |
5551 | enum machine_mode op_mode; | |
5552 | ||
5553 | condition_rtx = rs6000_generate_compare (code); | |
5554 | ||
5555 | op_mode = GET_MODE (rs6000_compare_op0); | |
5556 | if (op_mode == VOIDmode) | |
5557 | op_mode = GET_MODE (rs6000_compare_op1); | |
5558 | ||
5559 | if (TARGET_POWERPC64 && (op_mode == DImode || rs6000_compare_fp_p)) | |
5560 | { | |
5561 | PUT_MODE (condition_rtx, DImode); | |
5562 | convert_move (result, condition_rtx, 0); | |
5563 | } | |
5564 | else | |
5565 | { | |
5566 | PUT_MODE (condition_rtx, SImode); | |
5567 | emit_insn (gen_rtx_SET (VOIDmode, result, condition_rtx)); | |
5568 | } | |
5569 | } | |
5570 | ||
39a10a29 GK |
5571 | /* Emit a branch of kind CODE to location LOC. */ |
5572 | ||
5573 | void | |
5574 | rs6000_emit_cbranch (code, loc) | |
5575 | enum rtx_code code; | |
5576 | rtx loc; | |
5577 | { | |
5578 | rtx condition_rtx, loc_ref; | |
5579 | ||
5580 | condition_rtx = rs6000_generate_compare (code); | |
5581 | loc_ref = gen_rtx_LABEL_REF (VOIDmode, loc); | |
5582 | emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, | |
5583 | gen_rtx_IF_THEN_ELSE (VOIDmode, condition_rtx, | |
5584 | loc_ref, pc_rtx))); | |
5585 | } | |
5586 | ||
12a4e8c5 GK |
5587 | /* Return the string to output a conditional branch to LABEL, which is |
5588 | the operand number of the label, or -1 if the branch is really a | |
5589 | conditional return. | |
5590 | ||
5591 | OP is the conditional expression. XEXP (OP, 0) is assumed to be a | |
5592 | condition code register and its mode specifies what kind of | |
5593 | comparison we made. | |
5594 | ||
5595 | REVERSED is non-zero if we should reverse the sense of the comparison. | |
5596 | ||
5597 | INSN is the insn. */ | |
5598 | ||
5599 | char * | |
5600 | output_cbranch (op, label, reversed, insn) | |
5601 | rtx op; | |
5602 | const char * label; | |
5603 | int reversed; | |
5604 | rtx insn; | |
5605 | { | |
5606 | static char string[64]; | |
5607 | enum rtx_code code = GET_CODE (op); | |
5608 | rtx cc_reg = XEXP (op, 0); | |
5609 | enum machine_mode mode = GET_MODE (cc_reg); | |
5610 | int cc_regno = REGNO (cc_reg) - CR0_REGNO; | |
39a10a29 | 5611 | int need_longbranch = label != NULL && get_attr_length (insn) == 8; |
12a4e8c5 GK |
5612 | int really_reversed = reversed ^ need_longbranch; |
5613 | char *s = string; | |
5614 | const char *ccode; | |
5615 | const char *pred; | |
5616 | rtx note; | |
5617 | ||
39a10a29 GK |
5618 | validate_condition_mode (code, mode); |
5619 | ||
5620 | /* Work out which way this really branches. We could use | |
5621 | reverse_condition_maybe_unordered here always but this | |
5622 | makes the resulting assembler clearer. */ | |
12a4e8c5 | 5623 | if (really_reversed) |
39a10a29 | 5624 | code = rs6000_reverse_condition (mode, code); |
12a4e8c5 | 5625 | |
39a10a29 | 5626 | switch (code) |
12a4e8c5 GK |
5627 | { |
5628 | /* Not all of these are actually distinct opcodes, but | |
5629 | we distinguish them for clarity of the resulting assembler. */ | |
50a0b056 GK |
5630 | case NE: case LTGT: |
5631 | ccode = "ne"; break; | |
5632 | case EQ: case UNEQ: | |
5633 | ccode = "eq"; break; | |
5634 | case GE: case GEU: | |
5635 | ccode = "ge"; break; | |
5636 | case GT: case GTU: case UNGT: | |
5637 | ccode = "gt"; break; | |
5638 | case LE: case LEU: | |
5639 | ccode = "le"; break; | |
5640 | case LT: case LTU: case UNLT: | |
5641 | ccode = "lt"; break; | |
12a4e8c5 GK |
5642 | case UNORDERED: ccode = "un"; break; |
5643 | case ORDERED: ccode = "nu"; break; | |
5644 | case UNGE: ccode = "nl"; break; | |
5645 | case UNLE: ccode = "ng"; break; | |
5646 | default: | |
a4f6c312 | 5647 | abort (); |
12a4e8c5 GK |
5648 | } |
5649 | ||
94a54f47 GK |
5650 | /* Maybe we have a guess as to how likely the branch is. |
5651 | The old mnemonics don't have a way to specify this information. */ | |
12a4e8c5 GK |
5652 | note = find_reg_note (insn, REG_BR_PROB, NULL_RTX); |
5653 | if (note != NULL_RTX) | |
5654 | { | |
5655 | /* PROB is the difference from 50%. */ | |
5656 | int prob = INTVAL (XEXP (note, 0)) - REG_BR_PROB_BASE / 2; | |
5657 | ||
5658 | /* For branches that are very close to 50%, assume not-taken. */ | |
5659 | if (abs (prob) > REG_BR_PROB_BASE / 20 | |
5660 | && ((prob > 0) ^ need_longbranch)) | |
5661 | pred = "+"; | |
5662 | else | |
5663 | pred = "-"; | |
5664 | } | |
5665 | else | |
5666 | pred = ""; | |
5667 | ||
5668 | if (label == NULL) | |
94a54f47 | 5669 | s += sprintf (s, "{b%sr|b%slr%s} ", ccode, ccode, pred); |
12a4e8c5 | 5670 | else |
94a54f47 | 5671 | s += sprintf (s, "{b%s|b%s%s} ", ccode, ccode, pred); |
12a4e8c5 | 5672 | |
37c67319 GK |
5673 | /* We need to escape any '%' characters in the reg_names string. |
5674 | Assume they'd only be the first character... */ | |
5675 | if (reg_names[cc_regno + CR0_REGNO][0] == '%') | |
5676 | *s++ = '%'; | |
94a54f47 | 5677 | s += sprintf (s, "%s", reg_names[cc_regno + CR0_REGNO]); |
12a4e8c5 GK |
5678 | |
5679 | if (label != NULL) | |
5680 | { | |
5681 | /* If the branch distance was too far, we may have to use an | |
5682 | unconditional branch to go the distance. */ | |
5683 | if (need_longbranch) | |
44518ddd | 5684 | s += sprintf (s, ",$+8\n\tb %s", label); |
12a4e8c5 GK |
5685 | else |
5686 | s += sprintf (s, ",%s", label); | |
5687 | } | |
5688 | ||
5689 | return string; | |
5690 | } | |
50a0b056 GK |
5691 | |
5692 | /* Emit a conditional move: move TRUE_COND to DEST if OP of the | |
5693 | operands of the last comparison is nonzero/true, FALSE_COND if it | |
5694 | is zero/false. Return 0 if the hardware has no such operation. */ | |
a4f6c312 | 5695 | |
50a0b056 GK |
5696 | int |
5697 | rs6000_emit_cmove (dest, op, true_cond, false_cond) | |
5698 | rtx dest; | |
5699 | rtx op; | |
5700 | rtx true_cond; | |
5701 | rtx false_cond; | |
5702 | { | |
5703 | enum rtx_code code = GET_CODE (op); | |
5704 | rtx op0 = rs6000_compare_op0; | |
5705 | rtx op1 = rs6000_compare_op1; | |
5706 | REAL_VALUE_TYPE c1; | |
5707 | enum machine_mode mode = GET_MODE (op0); | |
5708 | rtx temp; | |
5709 | ||
5710 | /* First, work out if the hardware can do this at all, or | |
5711 | if it's too slow... */ | |
5712 | /* If the comparison is an integer one, since we only have fsel | |
5713 | it'll be cheaper to use a branch. */ | |
5714 | if (! rs6000_compare_fp_p) | |
5715 | return 0; | |
5716 | ||
5717 | /* Eliminate half of the comparisons by switching operands, this | |
5718 | makes the remaining code simpler. */ | |
5719 | if (code == UNLT || code == UNGT || code == UNORDERED || code == NE | |
5720 | || code == LTGT || code == LT) | |
5721 | { | |
5722 | code = reverse_condition_maybe_unordered (code); | |
5723 | temp = true_cond; | |
5724 | true_cond = false_cond; | |
5725 | false_cond = temp; | |
5726 | } | |
5727 | ||
5728 | /* UNEQ and LTGT take four instructions for a comparison with zero, | |
5729 | it'll probably be faster to use a branch here too. */ | |
5730 | if (code == UNEQ) | |
5731 | return 0; | |
5732 | ||
5733 | if (GET_CODE (op1) == CONST_DOUBLE) | |
5734 | REAL_VALUE_FROM_CONST_DOUBLE (c1, op1); | |
5735 | ||
5736 | /* We're going to try to implement comparions by performing | |
5737 | a subtract, then comparing against zero. Unfortunately, | |
5738 | Inf - Inf is NaN which is not zero, and so if we don't | |
5739 | know that the the operand is finite and the comparison | |
5740 | would treat EQ different to UNORDERED, we can't do it. */ | |
5741 | if (! flag_unsafe_math_optimizations | |
5742 | && code != GT && code != UNGE | |
5743 | && (GET_CODE (op1) != CONST_DOUBLE || target_isinf (c1)) | |
5744 | /* Constructs of the form (a OP b ? a : b) are safe. */ | |
5745 | && ((! rtx_equal_p (op0, false_cond) && ! rtx_equal_p (op1, false_cond)) | |
5746 | || (! rtx_equal_p (op0, true_cond) | |
5747 | && ! rtx_equal_p (op1, true_cond)))) | |
5748 | return 0; | |
5749 | /* At this point we know we can use fsel. */ | |
5750 | ||
5751 | /* Reduce the comparison to a comparison against zero. */ | |
5752 | temp = gen_reg_rtx (mode); | |
5753 | emit_insn (gen_rtx_SET (VOIDmode, temp, | |
5754 | gen_rtx_MINUS (mode, op0, op1))); | |
5755 | op0 = temp; | |
5756 | op1 = CONST0_RTX (mode); | |
5757 | ||
5758 | /* If we don't care about NaNs we can reduce some of the comparisons | |
5759 | down to faster ones. */ | |
5760 | if (flag_unsafe_math_optimizations) | |
5761 | switch (code) | |
5762 | { | |
5763 | case GT: | |
5764 | code = LE; | |
5765 | temp = true_cond; | |
5766 | true_cond = false_cond; | |
5767 | false_cond = temp; | |
5768 | break; | |
5769 | case UNGE: | |
5770 | code = GE; | |
5771 | break; | |
5772 | case UNEQ: | |
5773 | code = EQ; | |
5774 | break; | |
5775 | default: | |
5776 | break; | |
5777 | } | |
5778 | ||
5779 | /* Now, reduce everything down to a GE. */ | |
5780 | switch (code) | |
5781 | { | |
5782 | case GE: | |
5783 | break; | |
5784 | ||
5785 | case LE: | |
5786 | temp = gen_reg_rtx (mode); | |
5787 | emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (mode, op0))); | |
5788 | op0 = temp; | |
5789 | break; | |
5790 | ||
5791 | case ORDERED: | |
5792 | temp = gen_reg_rtx (mode); | |
5793 | emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_ABS (mode, op0))); | |
5794 | op0 = temp; | |
5795 | break; | |
5796 | ||
5797 | case EQ: | |
5798 | temp = gen_reg_rtx (mode); | |
5799 | emit_insn (gen_rtx_SET (VOIDmode, temp, | |
5800 | gen_rtx_NEG (mode, | |
5801 | gen_rtx_ABS (mode, op0)))); | |
5802 | op0 = temp; | |
5803 | break; | |
5804 | ||
5805 | case UNGE: | |
5806 | temp = gen_reg_rtx (mode); | |
5807 | emit_insn (gen_rtx_SET (VOIDmode, temp, | |
5808 | gen_rtx_IF_THEN_ELSE (mode, | |
5809 | gen_rtx_GE (VOIDmode, | |
5810 | op0, op1), | |
5811 | true_cond, false_cond))); | |
5812 | false_cond = temp; | |
5813 | true_cond = false_cond; | |
5814 | ||
5815 | temp = gen_reg_rtx (mode); | |
5816 | emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (mode, op0))); | |
5817 | op0 = temp; | |
5818 | break; | |
5819 | ||
5820 | case GT: | |
5821 | temp = gen_reg_rtx (mode); | |
5822 | emit_insn (gen_rtx_SET (VOIDmode, temp, | |
5823 | gen_rtx_IF_THEN_ELSE (mode, | |
5824 | gen_rtx_GE (VOIDmode, | |
5825 | op0, op1), | |
5826 | true_cond, false_cond))); | |
5827 | true_cond = temp; | |
5828 | false_cond = true_cond; | |
5829 | ||
5830 | temp = gen_reg_rtx (mode); | |
5831 | emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (mode, op0))); | |
5832 | op0 = temp; | |
5833 | break; | |
5834 | ||
5835 | default: | |
5836 | abort (); | |
5837 | } | |
5838 | ||
5839 | emit_insn (gen_rtx_SET (VOIDmode, dest, | |
9f1a9740 | 5840 | gen_rtx_IF_THEN_ELSE (GET_MODE (dest), |
50a0b056 GK |
5841 | gen_rtx_GE (VOIDmode, |
5842 | op0, op1), | |
5843 | true_cond, false_cond))); | |
5844 | return 1; | |
5845 | } | |
5846 | ||
5847 | void | |
5848 | rs6000_emit_minmax (dest, code, op0, op1) | |
5849 | rtx dest; | |
5850 | enum rtx_code code; | |
5851 | rtx op0; | |
5852 | rtx op1; | |
5853 | { | |
5854 | enum machine_mode mode = GET_MODE (op0); | |
5855 | rtx target; | |
5856 | if (code == SMAX || code == UMAX) | |
5857 | target = emit_conditional_move (dest, GE, op0, op1, mode, | |
5858 | op0, op1, mode, 0); | |
5859 | else | |
5860 | target = emit_conditional_move (dest, GE, op0, op1, mode, | |
5861 | op1, op0, mode, 0); | |
5862 | if (target == NULL_RTX) | |
5863 | abort (); | |
5864 | if (target != dest) | |
5865 | emit_move_insn (dest, target); | |
5866 | } | |
12a4e8c5 | 5867 | \f |
a4f6c312 SS |
5868 | /* This page contains routines that are used to determine what the |
5869 | function prologue and epilogue code will do and write them out. */ | |
9878760c | 5870 | |
a4f6c312 SS |
5871 | /* Return the first fixed-point register that is required to be |
5872 | saved. 32 if none. */ | |
9878760c RK |
5873 | |
5874 | int | |
5875 | first_reg_to_save () | |
5876 | { | |
5877 | int first_reg; | |
5878 | ||
5879 | /* Find lowest numbered live register. */ | |
5880 | for (first_reg = 13; first_reg <= 31; first_reg++) | |
a38d360d GK |
5881 | if (regs_ever_live[first_reg] |
5882 | && (! call_used_regs[first_reg] | |
5883 | || (first_reg == PIC_OFFSET_TABLE_REGNUM | |
f607bc57 ZW |
5884 | && ((DEFAULT_ABI == ABI_V4 && flag_pic == 1) |
5885 | || (DEFAULT_ABI == ABI_DARWIN && flag_pic))))) | |
9878760c RK |
5886 | break; |
5887 | ||
b5253831 DE |
5888 | if (profile_flag) |
5889 | { | |
5890 | /* AIX must save/restore every register that contains a parameter | |
5891 | before/after the .__mcount call plus an additional register | |
5892 | for the static chain, if needed; use registers from 30 down to 22 | |
5893 | to do this. */ | |
ee890fe2 | 5894 | if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) |
b5253831 DE |
5895 | { |
5896 | int last_parm_reg, profile_first_reg; | |
5897 | ||
5898 | /* Figure out last used parameter register. The proper thing | |
5899 | to do is to walk incoming args of the function. A function | |
5900 | might have live parameter registers even if it has no | |
5901 | incoming args. */ | |
5902 | for (last_parm_reg = 10; | |
5903 | last_parm_reg > 2 && ! regs_ever_live [last_parm_reg]; | |
5904 | last_parm_reg--) | |
5905 | ; | |
5906 | ||
5907 | /* Calculate first reg for saving parameter registers | |
5908 | and static chain. | |
5909 | Skip reg 31 which may contain the frame pointer. */ | |
5910 | profile_first_reg = (33 - last_parm_reg | |
5911 | - (current_function_needs_context ? 1 : 0)); | |
ee890fe2 SS |
5912 | #if TARGET_MACHO |
5913 | /* Need to skip another reg to account for R31 being PICBASE | |
5914 | (when flag_pic is set) or R30 being used as the frame | |
5915 | pointer (when flag_pic is not set). */ | |
5916 | --profile_first_reg; | |
5917 | #endif | |
b5253831 DE |
5918 | /* Do not save frame pointer if no parameters needs to be saved. */ |
5919 | if (profile_first_reg == 31) | |
5920 | profile_first_reg = 32; | |
5921 | ||
5922 | if (first_reg > profile_first_reg) | |
5923 | first_reg = profile_first_reg; | |
5924 | } | |
e165f3f0 | 5925 | |
b5253831 DE |
5926 | /* SVR4 may need one register to preserve the static chain. */ |
5927 | else if (current_function_needs_context) | |
5928 | { | |
5929 | /* Skip reg 31 which may contain the frame pointer. */ | |
5930 | if (first_reg > 30) | |
5931 | first_reg = 30; | |
5932 | } | |
5933 | } | |
e165f3f0 | 5934 | |
ee890fe2 SS |
5935 | #if TARGET_MACHO |
5936 | if (flag_pic && current_function_uses_pic_offset_table && | |
5937 | (first_reg > PIC_OFFSET_TABLE_REGNUM)) | |
5938 | return PIC_OFFSET_TABLE_REGNUM; | |
5939 | #endif | |
5940 | ||
9878760c RK |
5941 | return first_reg; |
5942 | } | |
5943 | ||
5944 | /* Similar, for FP regs. */ | |
5945 | ||
5946 | int | |
5947 | first_fp_reg_to_save () | |
5948 | { | |
5949 | int first_reg; | |
5950 | ||
5951 | /* Find lowest numbered live register. */ | |
5952 | for (first_reg = 14 + 32; first_reg <= 63; first_reg++) | |
5953 | if (regs_ever_live[first_reg]) | |
5954 | break; | |
5955 | ||
5956 | return first_reg; | |
5957 | } | |
00b960c7 AH |
5958 | |
5959 | /* Similar, for AltiVec regs. */ | |
5960 | ||
5961 | static int | |
5962 | first_altivec_reg_to_save () | |
5963 | { | |
5964 | int i; | |
5965 | ||
5966 | /* Stack frame remains as is unless we are in AltiVec ABI. */ | |
5967 | if (! TARGET_ALTIVEC_ABI) | |
5968 | return LAST_ALTIVEC_REGNO + 1; | |
5969 | ||
5970 | /* Find lowest numbered live register. */ | |
5971 | for (i = FIRST_ALTIVEC_REGNO + 20; i <= LAST_ALTIVEC_REGNO; ++i) | |
5972 | if (regs_ever_live[i]) | |
5973 | break; | |
5974 | ||
5975 | return i; | |
5976 | } | |
5977 | ||
5978 | /* Return a 32-bit mask of the AltiVec registers we need to set in | |
5979 | VRSAVE. Bit n of the return value is 1 if Vn is live. The MSB in | |
5980 | the 32-bit word is 0. */ | |
5981 | ||
5982 | static unsigned int | |
5983 | compute_vrsave_mask () | |
5984 | { | |
5985 | unsigned int i, mask = 0; | |
5986 | ||
5987 | /* First, find out if we use _any_ altivec registers. */ | |
5988 | for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i) | |
5989 | if (regs_ever_live[i]) | |
5990 | mask |= ALTIVEC_REG_BIT (i); | |
5991 | ||
5992 | if (mask == 0) | |
5993 | return mask; | |
5994 | ||
5995 | /* Next, add all registers that are call-clobbered. We do this | |
5996 | because post-reload register optimizers such as regrename_optimize | |
5997 | may choose to use them. They never change the register class | |
5998 | chosen by reload, so cannot create new uses of altivec registers | |
5999 | if there were none before, so the early exit above is safe. */ | |
6000 | /* ??? Alternately, we could define HARD_REGNO_RENAME_OK to disallow | |
6001 | altivec registers not saved in the mask, which might well make the | |
6002 | adjustments below more effective in eliding the save/restore of | |
6003 | VRSAVE in small functions. */ | |
6004 | for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i) | |
6005 | if (call_used_regs[i]) | |
6006 | mask |= ALTIVEC_REG_BIT (i); | |
6007 | ||
6008 | /* Next, remove the argument registers from the set. These must | |
6009 | be in the VRSAVE mask set by the caller, so we don't need to add | |
6010 | them in again. More importantly, the mask we compute here is | |
6011 | used to generate CLOBBERs in the set_vrsave insn, and we do not | |
6012 | wish the argument registers to die. */ | |
6013 | for (i = cfun->args_info.vregno; i >= ALTIVEC_ARG_MIN_REG; --i) | |
6014 | mask &= ~ALTIVEC_REG_BIT (i); | |
6015 | ||
6016 | /* Similarly, remove the return value from the set. */ | |
6017 | { | |
6018 | bool yes = false; | |
6019 | diddle_return_value (is_altivec_return_reg, &yes); | |
6020 | if (yes) | |
6021 | mask &= ~ALTIVEC_REG_BIT (ALTIVEC_ARG_RETURN); | |
6022 | } | |
6023 | ||
6024 | return mask; | |
6025 | } | |
6026 | ||
6027 | static void | |
6028 | is_altivec_return_reg (reg, xyes) | |
6029 | rtx reg; | |
6030 | void *xyes; | |
6031 | { | |
6032 | bool *yes = (bool *) xyes; | |
6033 | if (REGNO (reg) == ALTIVEC_ARG_RETURN) | |
6034 | *yes = true; | |
6035 | } | |
6036 | ||
4697a36c MM |
6037 | \f |
6038 | /* Calculate the stack information for the current function. This is | |
6039 | complicated by having two separate calling sequences, the AIX calling | |
6040 | sequence and the V.4 calling sequence. | |
6041 | ||
592696dd | 6042 | AIX (and Darwin/Mac OS X) stack frames look like: |
a260abc9 | 6043 | 32-bit 64-bit |
4697a36c | 6044 | SP----> +---------------------------------------+ |
a260abc9 | 6045 | | back chain to caller | 0 0 |
4697a36c | 6046 | +---------------------------------------+ |
a260abc9 | 6047 | | saved CR | 4 8 (8-11) |
4697a36c | 6048 | +---------------------------------------+ |
a260abc9 | 6049 | | saved LR | 8 16 |
4697a36c | 6050 | +---------------------------------------+ |
a260abc9 | 6051 | | reserved for compilers | 12 24 |
4697a36c | 6052 | +---------------------------------------+ |
a260abc9 | 6053 | | reserved for binders | 16 32 |
4697a36c | 6054 | +---------------------------------------+ |
a260abc9 | 6055 | | saved TOC pointer | 20 40 |
4697a36c | 6056 | +---------------------------------------+ |
a260abc9 | 6057 | | Parameter save area (P) | 24 48 |
4697a36c | 6058 | +---------------------------------------+ |
a260abc9 | 6059 | | Alloca space (A) | 24+P etc. |
802a0058 | 6060 | +---------------------------------------+ |
a7df97e6 | 6061 | | Local variable space (L) | 24+P+A |
4697a36c | 6062 | +---------------------------------------+ |
a7df97e6 | 6063 | | Float/int conversion temporary (X) | 24+P+A+L |
4697a36c | 6064 | +---------------------------------------+ |
00b960c7 AH |
6065 | | Save area for AltiVec registers (W) | 24+P+A+L+X |
6066 | +---------------------------------------+ | |
6067 | | AltiVec alignment padding (Y) | 24+P+A+L+X+W | |
6068 | +---------------------------------------+ | |
6069 | | Save area for VRSAVE register (Z) | 24+P+A+L+X+W+Y | |
4697a36c | 6070 | +---------------------------------------+ |
00b960c7 AH |
6071 | | Save area for GP registers (G) | 24+P+A+X+L+X+W+Y+Z |
6072 | +---------------------------------------+ | |
6073 | | Save area for FP registers (F) | 24+P+A+X+L+X+W+Y+Z+G | |
4697a36c MM |
6074 | +---------------------------------------+ |
6075 | old SP->| back chain to caller's caller | | |
6076 | +---------------------------------------+ | |
6077 | ||
5376a30c KR |
6078 | The required alignment for AIX configurations is two words (i.e., 8 |
6079 | or 16 bytes). | |
6080 | ||
6081 | ||
4697a36c MM |
6082 | V.4 stack frames look like: |
6083 | ||
6084 | SP----> +---------------------------------------+ | |
6085 | | back chain to caller | 0 | |
6086 | +---------------------------------------+ | |
5eb387b8 | 6087 | | caller's saved LR | 4 |
4697a36c MM |
6088 | +---------------------------------------+ |
6089 | | Parameter save area (P) | 8 | |
6090 | +---------------------------------------+ | |
a7df97e6 MM |
6091 | | Alloca space (A) | 8+P |
6092 | +---------------------------------------+ | |
6093 | | Varargs save area (V) | 8+P+A | |
6094 | +---------------------------------------+ | |
6095 | | Local variable space (L) | 8+P+A+V | |
6096 | +---------------------------------------+ | |
6097 | | Float/int conversion temporary (X) | 8+P+A+V+L | |
4697a36c | 6098 | +---------------------------------------+ |
00b960c7 AH |
6099 | | Save area for AltiVec registers (W) | 8+P+A+V+L+X |
6100 | +---------------------------------------+ | |
6101 | | AltiVec alignment padding (Y) | 8+P+A+V+L+X+W | |
6102 | +---------------------------------------+ | |
6103 | | Save area for VRSAVE register (Z) | 8+P+A+V+L+X+W+Y | |
6104 | +---------------------------------------+ | |
6105 | | saved CR (C) | 8+P+A+V+L+X+W+Y+Z | |
a7df97e6 | 6106 | +---------------------------------------+ |
00b960c7 | 6107 | | Save area for GP registers (G) | 8+P+A+V+L+X+W+Y+Z+C |
a7df97e6 | 6108 | +---------------------------------------+ |
00b960c7 | 6109 | | Save area for FP registers (F) | 8+P+A+V+L+X+W+Y+Z+C+G |
4697a36c MM |
6110 | +---------------------------------------+ |
6111 | old SP->| back chain to caller's caller | | |
6112 | +---------------------------------------+ | |
b6c9286a | 6113 | |
5376a30c KR |
6114 | The required alignment for V.4 is 16 bytes, or 8 bytes if -meabi is |
6115 | given. (But note below and in sysv4.h that we require only 8 and | |
6116 | may round up the size of our stack frame anyways. The historical | |
6117 | reason is early versions of powerpc-linux which didn't properly | |
6118 | align the stack at program startup. A happy side-effect is that | |
6119 | -mno-eabi libraries can be used with -meabi programs.) | |
6120 | ||
5376a30c KR |
6121 | The EABI configuration defaults to the V.4 layout, unless |
6122 | -mcall-aix is used, in which case the AIX layout is used. However, | |
6123 | the stack alignment requirements may differ. If -mno-eabi is not | |
6124 | given, the required stack alignment is 8 bytes; if -mno-eabi is | |
6125 | given, the required alignment is 16 bytes. (But see V.4 comment | |
6126 | above.) */ | |
4697a36c | 6127 | |
61b2fbe7 MM |
6128 | #ifndef ABI_STACK_BOUNDARY |
6129 | #define ABI_STACK_BOUNDARY STACK_BOUNDARY | |
6130 | #endif | |
6131 | ||
4697a36c MM |
6132 | rs6000_stack_t * |
6133 | rs6000_stack_info () | |
6134 | { | |
6135 | static rs6000_stack_t info, zero_info; | |
6136 | rs6000_stack_t *info_ptr = &info; | |
9ebbca7d | 6137 | int reg_size = TARGET_POWERPC64 ? 8 : 4; |
24d304eb | 6138 | enum rs6000_abi abi; |
83720594 | 6139 | int ehrd_size; |
b6c9286a | 6140 | int total_raw_size; |
4697a36c | 6141 | |
a4f6c312 | 6142 | /* Zero all fields portably. */ |
4697a36c MM |
6143 | info = zero_info; |
6144 | ||
a4f6c312 | 6145 | /* Select which calling sequence. */ |
b6c9286a | 6146 | info_ptr->abi = abi = DEFAULT_ABI; |
9878760c | 6147 | |
a4f6c312 | 6148 | /* Calculate which registers need to be saved & save area size. */ |
4697a36c | 6149 | info_ptr->first_gp_reg_save = first_reg_to_save (); |
906fb125 GK |
6150 | /* Assume that we will have to save PIC_OFFSET_TABLE_REGNUM, |
6151 | even if it currently looks like we won't. */ | |
2bfcf297 | 6152 | if (((TARGET_TOC && TARGET_MINIMAL_TOC) |
f607bc57 ZW |
6153 | || (flag_pic == 1 && abi == ABI_V4) |
6154 | || (flag_pic && abi == ABI_DARWIN)) | |
906fb125 GK |
6155 | && info_ptr->first_gp_reg_save > PIC_OFFSET_TABLE_REGNUM) |
6156 | info_ptr->gp_size = reg_size * (32 - PIC_OFFSET_TABLE_REGNUM); | |
6157 | else | |
6158 | info_ptr->gp_size = reg_size * (32 - info_ptr->first_gp_reg_save); | |
4697a36c MM |
6159 | |
6160 | info_ptr->first_fp_reg_save = first_fp_reg_to_save (); | |
6161 | info_ptr->fp_size = 8 * (64 - info_ptr->first_fp_reg_save); | |
6162 | ||
00b960c7 AH |
6163 | info_ptr->first_altivec_reg_save = first_altivec_reg_to_save (); |
6164 | info_ptr->altivec_size = 16 * (LAST_ALTIVEC_REGNO + 1 | |
6165 | - info_ptr->first_altivec_reg_save); | |
6166 | ||
592696dd | 6167 | /* Does this function call anything? */ |
71f123ca FS |
6168 | info_ptr->calls_p = (! current_function_is_leaf |
6169 | || cfun->machine->ra_needs_full_frame); | |
b6c9286a | 6170 | |
a4f6c312 | 6171 | /* Determine if we need to save the link register. */ |
71f123ca | 6172 | if (rs6000_ra_ever_killed () |
38c1f2d7 | 6173 | || (DEFAULT_ABI == ABI_AIX && profile_flag) |
4697a36c MM |
6174 | #ifdef TARGET_RELOCATABLE |
6175 | || (TARGET_RELOCATABLE && (get_pool_size () != 0)) | |
6176 | #endif | |
6177 | || (info_ptr->first_fp_reg_save != 64 | |
6178 | && !FP_SAVE_INLINE (info_ptr->first_fp_reg_save)) | |
00b960c7 | 6179 | || info_ptr->first_altivec_reg_save <= LAST_ALTIVEC_REGNO |
24d304eb | 6180 | || (abi == ABI_V4 && current_function_calls_alloca) |
a4f6c312 SS |
6181 | || (DEFAULT_ABI == ABI_DARWIN |
6182 | && flag_pic | |
6183 | && current_function_uses_pic_offset_table) | |
4697a36c MM |
6184 | || info_ptr->calls_p) |
6185 | { | |
6186 | info_ptr->lr_save_p = 1; | |
9ebbca7d | 6187 | regs_ever_live[LINK_REGISTER_REGNUM] = 1; |
4697a36c MM |
6188 | } |
6189 | ||
9ebbca7d GK |
6190 | /* Determine if we need to save the condition code registers. */ |
6191 | if (regs_ever_live[CR2_REGNO] | |
6192 | || regs_ever_live[CR3_REGNO] | |
6193 | || regs_ever_live[CR4_REGNO]) | |
4697a36c MM |
6194 | { |
6195 | info_ptr->cr_save_p = 1; | |
f607bc57 | 6196 | if (abi == ABI_V4) |
4697a36c MM |
6197 | info_ptr->cr_size = reg_size; |
6198 | } | |
6199 | ||
83720594 RH |
6200 | /* If the current function calls __builtin_eh_return, then we need |
6201 | to allocate stack space for registers that will hold data for | |
6202 | the exception handler. */ | |
6203 | if (current_function_calls_eh_return) | |
6204 | { | |
6205 | unsigned int i; | |
6206 | for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; ++i) | |
6207 | continue; | |
6208 | ehrd_size = i * UNITS_PER_WORD; | |
6209 | } | |
6210 | else | |
6211 | ehrd_size = 0; | |
6212 | ||
592696dd | 6213 | /* Determine various sizes. */ |
4697a36c MM |
6214 | info_ptr->reg_size = reg_size; |
6215 | info_ptr->fixed_size = RS6000_SAVE_AREA; | |
6216 | info_ptr->varargs_size = RS6000_VARARGS_AREA; | |
189e03e3 | 6217 | info_ptr->vars_size = RS6000_ALIGN (get_frame_size (), 8); |
a4f6c312 SS |
6218 | info_ptr->parm_size = RS6000_ALIGN (current_function_outgoing_args_size, |
6219 | 8); | |
00b960c7 AH |
6220 | |
6221 | if (TARGET_ALTIVEC_ABI) | |
6222 | { | |
6223 | info_ptr->vrsave_mask = compute_vrsave_mask (); | |
6224 | info_ptr->vrsave_size = info_ptr->vrsave_mask ? 4 : 0; | |
6225 | } | |
6226 | else | |
6227 | { | |
6228 | info_ptr->vrsave_mask = 0; | |
6229 | info_ptr->vrsave_size = 0; | |
6230 | } | |
b6c9286a | 6231 | |
592696dd | 6232 | /* Calculate the offsets. */ |
24d304eb | 6233 | switch (abi) |
4697a36c | 6234 | { |
b6c9286a | 6235 | case ABI_NONE: |
24d304eb | 6236 | default: |
b6c9286a MM |
6237 | abort (); |
6238 | ||
6239 | case ABI_AIX: | |
6240 | case ABI_AIX_NODESC: | |
ee890fe2 | 6241 | case ABI_DARWIN: |
b6c9286a MM |
6242 | info_ptr->fp_save_offset = - info_ptr->fp_size; |
6243 | info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size; | |
00b960c7 AH |
6244 | |
6245 | if (TARGET_ALTIVEC_ABI) | |
6246 | { | |
6247 | info_ptr->vrsave_save_offset | |
6248 | = info_ptr->gp_save_offset - info_ptr->vrsave_size; | |
6249 | ||
6250 | /* Align stack so vector save area is on a quadword boundary. */ | |
6251 | if (info_ptr->altivec_size != 0) | |
6252 | info_ptr->altivec_padding_size | |
6253 | = 16 - (-info_ptr->vrsave_save_offset % 16); | |
6254 | else | |
6255 | info_ptr->altivec_padding_size = 0; | |
6256 | ||
6257 | info_ptr->altivec_save_offset | |
6258 | = info_ptr->vrsave_save_offset | |
6259 | - info_ptr->altivec_padding_size | |
6260 | - info_ptr->altivec_size; | |
6261 | ||
6262 | /* Adjust for AltiVec case. */ | |
6263 | info_ptr->ehrd_offset = info_ptr->altivec_save_offset - ehrd_size; | |
6264 | } | |
6265 | else | |
6266 | info_ptr->ehrd_offset = info_ptr->gp_save_offset - ehrd_size; | |
a260abc9 DE |
6267 | info_ptr->cr_save_offset = reg_size; /* first word when 64-bit. */ |
6268 | info_ptr->lr_save_offset = 2*reg_size; | |
24d304eb RK |
6269 | break; |
6270 | ||
6271 | case ABI_V4: | |
b6c9286a MM |
6272 | info_ptr->fp_save_offset = - info_ptr->fp_size; |
6273 | info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size; | |
a7df97e6 | 6274 | info_ptr->cr_save_offset = info_ptr->gp_save_offset - info_ptr->cr_size; |
00b960c7 AH |
6275 | |
6276 | if (TARGET_ALTIVEC_ABI) | |
6277 | { | |
6278 | info_ptr->vrsave_save_offset | |
6279 | = info_ptr->cr_save_offset - info_ptr->vrsave_size; | |
6280 | ||
6281 | /* Align stack so vector save area is on a quadword boundary. */ | |
6282 | if (info_ptr->altivec_size != 0) | |
6283 | info_ptr->altivec_padding_size | |
6284 | = 16 - (-info_ptr->vrsave_save_offset % 16); | |
6285 | else | |
6286 | info_ptr->altivec_padding_size = 0; | |
6287 | ||
6288 | info_ptr->altivec_save_offset | |
6289 | = info_ptr->vrsave_save_offset | |
6290 | - info_ptr->altivec_padding_size | |
6291 | - info_ptr->altivec_size; | |
6292 | ||
6293 | /* Adjust for AltiVec case. */ | |
6294 | info_ptr->toc_save_offset | |
6295 | = info_ptr->altivec_save_offset - info_ptr->toc_size; | |
6296 | } | |
6297 | else | |
6298 | info_ptr->toc_save_offset = info_ptr->cr_save_offset - info_ptr->toc_size; | |
83720594 | 6299 | info_ptr->ehrd_offset = info_ptr->toc_save_offset - ehrd_size; |
b6c9286a MM |
6300 | info_ptr->lr_save_offset = reg_size; |
6301 | break; | |
4697a36c MM |
6302 | } |
6303 | ||
00b960c7 AH |
6304 | info_ptr->save_size = RS6000_ALIGN (info_ptr->fp_size |
6305 | + info_ptr->gp_size | |
6306 | + info_ptr->altivec_size | |
6307 | + info_ptr->altivec_padding_size | |
6308 | + info_ptr->vrsave_size | |
6309 | + ehrd_size | |
6310 | + info_ptr->cr_size | |
6311 | + info_ptr->lr_size | |
6312 | + info_ptr->vrsave_size | |
6313 | + info_ptr->toc_size, | |
6314 | (TARGET_ALTIVEC_ABI || ABI_DARWIN) | |
6315 | ? 16 : 8); | |
6316 | ||
ff381587 MM |
6317 | total_raw_size = (info_ptr->vars_size |
6318 | + info_ptr->parm_size | |
ff381587 MM |
6319 | + info_ptr->save_size |
6320 | + info_ptr->varargs_size | |
6321 | + info_ptr->fixed_size); | |
6322 | ||
a4f6c312 SS |
6323 | info_ptr->total_size = |
6324 | RS6000_ALIGN (total_raw_size, ABI_STACK_BOUNDARY / BITS_PER_UNIT); | |
ff381587 MM |
6325 | |
6326 | /* Determine if we need to allocate any stack frame: | |
6327 | ||
a4f6c312 SS |
6328 | For AIX we need to push the stack if a frame pointer is needed |
6329 | (because the stack might be dynamically adjusted), if we are | |
6330 | debugging, if we make calls, or if the sum of fp_save, gp_save, | |
6331 | and local variables are more than the space needed to save all | |
6332 | non-volatile registers: 32-bit: 18*8 + 19*4 = 220 or 64-bit: 18*8 | |
6333 | + 18*8 = 288 (GPR13 reserved). | |
ff381587 | 6334 | |
a4f6c312 SS |
6335 | For V.4 we don't have the stack cushion that AIX uses, but assume |
6336 | that the debugger can handle stackless frames. */ | |
ff381587 MM |
6337 | |
6338 | if (info_ptr->calls_p) | |
6339 | info_ptr->push_p = 1; | |
6340 | ||
f607bc57 | 6341 | else if (abi == ABI_V4) |
ff381587 | 6342 | info_ptr->push_p = (total_raw_size > info_ptr->fixed_size |
9ebbca7d | 6343 | || info_ptr->calls_p); |
ff381587 MM |
6344 | |
6345 | else | |
6346 | info_ptr->push_p = (frame_pointer_needed | |
ee890fe2 | 6347 | || (abi != ABI_DARWIN && write_symbols != NO_DEBUG) |
ff381587 | 6348 | || ((total_raw_size - info_ptr->fixed_size) |
bfc79d3b | 6349 | > (TARGET_32BIT ? 220 : 288))); |
ff381587 | 6350 | |
a4f6c312 | 6351 | /* Zero offsets if we're not saving those registers. */ |
8dda1a21 | 6352 | if (info_ptr->fp_size == 0) |
4697a36c MM |
6353 | info_ptr->fp_save_offset = 0; |
6354 | ||
8dda1a21 | 6355 | if (info_ptr->gp_size == 0) |
4697a36c MM |
6356 | info_ptr->gp_save_offset = 0; |
6357 | ||
00b960c7 AH |
6358 | if (! TARGET_ALTIVEC_ABI || info_ptr->altivec_size == 0) |
6359 | info_ptr->altivec_save_offset = 0; | |
6360 | ||
6361 | if (! TARGET_ALTIVEC_ABI || info_ptr->vrsave_mask == 0) | |
6362 | info_ptr->vrsave_save_offset = 0; | |
6363 | ||
c81fc13e | 6364 | if (! info_ptr->lr_save_p) |
4697a36c MM |
6365 | info_ptr->lr_save_offset = 0; |
6366 | ||
c81fc13e | 6367 | if (! info_ptr->cr_save_p) |
4697a36c MM |
6368 | info_ptr->cr_save_offset = 0; |
6369 | ||
c81fc13e | 6370 | if (! info_ptr->toc_save_p) |
b6c9286a MM |
6371 | info_ptr->toc_save_offset = 0; |
6372 | ||
4697a36c MM |
6373 | return info_ptr; |
6374 | } | |
6375 | ||
6376 | void | |
6377 | debug_stack_info (info) | |
6378 | rs6000_stack_t *info; | |
9878760c | 6379 | { |
d330fd93 | 6380 | const char *abi_string; |
24d304eb | 6381 | |
c81fc13e | 6382 | if (! info) |
4697a36c MM |
6383 | info = rs6000_stack_info (); |
6384 | ||
6385 | fprintf (stderr, "\nStack information for function %s:\n", | |
6386 | ((current_function_decl && DECL_NAME (current_function_decl)) | |
6387 | ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl)) | |
6388 | : "<unknown>")); | |
6389 | ||
24d304eb RK |
6390 | switch (info->abi) |
6391 | { | |
b6c9286a MM |
6392 | default: abi_string = "Unknown"; break; |
6393 | case ABI_NONE: abi_string = "NONE"; break; | |
f607bc57 | 6394 | case ABI_AIX: |
b6c9286a | 6395 | case ABI_AIX_NODESC: abi_string = "AIX"; break; |
ee890fe2 | 6396 | case ABI_DARWIN: abi_string = "Darwin"; break; |
b6c9286a | 6397 | case ABI_V4: abi_string = "V.4"; break; |
24d304eb RK |
6398 | } |
6399 | ||
6400 | fprintf (stderr, "\tABI = %5s\n", abi_string); | |
6401 | ||
00b960c7 AH |
6402 | if (TARGET_ALTIVEC_ABI) |
6403 | fprintf (stderr, "\tALTIVEC ABI extensions enabled.\n"); | |
6404 | ||
4697a36c MM |
6405 | if (info->first_gp_reg_save != 32) |
6406 | fprintf (stderr, "\tfirst_gp_reg_save = %5d\n", info->first_gp_reg_save); | |
6407 | ||
6408 | if (info->first_fp_reg_save != 64) | |
6409 | fprintf (stderr, "\tfirst_fp_reg_save = %5d\n", info->first_fp_reg_save); | |
9878760c | 6410 | |
00b960c7 AH |
6411 | if (info->first_altivec_reg_save <= LAST_ALTIVEC_REGNO) |
6412 | fprintf (stderr, "\tfirst_altivec_reg_save = %5d\n", | |
6413 | info->first_altivec_reg_save); | |
6414 | ||
4697a36c MM |
6415 | if (info->lr_save_p) |
6416 | fprintf (stderr, "\tlr_save_p = %5d\n", info->lr_save_p); | |
9878760c | 6417 | |
4697a36c MM |
6418 | if (info->cr_save_p) |
6419 | fprintf (stderr, "\tcr_save_p = %5d\n", info->cr_save_p); | |
6420 | ||
b6c9286a MM |
6421 | if (info->toc_save_p) |
6422 | fprintf (stderr, "\ttoc_save_p = %5d\n", info->toc_save_p); | |
6423 | ||
00b960c7 AH |
6424 | if (info->vrsave_mask) |
6425 | fprintf (stderr, "\tvrsave_mask = 0x%x\n", info->vrsave_mask); | |
6426 | ||
4697a36c MM |
6427 | if (info->push_p) |
6428 | fprintf (stderr, "\tpush_p = %5d\n", info->push_p); | |
6429 | ||
6430 | if (info->calls_p) | |
6431 | fprintf (stderr, "\tcalls_p = %5d\n", info->calls_p); | |
6432 | ||
4697a36c MM |
6433 | if (info->gp_save_offset) |
6434 | fprintf (stderr, "\tgp_save_offset = %5d\n", info->gp_save_offset); | |
6435 | ||
6436 | if (info->fp_save_offset) | |
6437 | fprintf (stderr, "\tfp_save_offset = %5d\n", info->fp_save_offset); | |
6438 | ||
00b960c7 AH |
6439 | if (info->altivec_save_offset) |
6440 | fprintf (stderr, "\taltivec_save_offset = %5d\n", | |
6441 | info->altivec_save_offset); | |
6442 | ||
6443 | if (info->vrsave_save_offset) | |
6444 | fprintf (stderr, "\tvrsave_save_offset = %5d\n", | |
6445 | info->vrsave_save_offset); | |
6446 | ||
4697a36c MM |
6447 | if (info->lr_save_offset) |
6448 | fprintf (stderr, "\tlr_save_offset = %5d\n", info->lr_save_offset); | |
6449 | ||
6450 | if (info->cr_save_offset) | |
6451 | fprintf (stderr, "\tcr_save_offset = %5d\n", info->cr_save_offset); | |
6452 | ||
b6c9286a MM |
6453 | if (info->toc_save_offset) |
6454 | fprintf (stderr, "\ttoc_save_offset = %5d\n", info->toc_save_offset); | |
6455 | ||
4697a36c MM |
6456 | if (info->varargs_save_offset) |
6457 | fprintf (stderr, "\tvarargs_save_offset = %5d\n", info->varargs_save_offset); | |
6458 | ||
6459 | if (info->total_size) | |
6460 | fprintf (stderr, "\ttotal_size = %5d\n", info->total_size); | |
6461 | ||
6462 | if (info->varargs_size) | |
6463 | fprintf (stderr, "\tvarargs_size = %5d\n", info->varargs_size); | |
6464 | ||
6465 | if (info->vars_size) | |
6466 | fprintf (stderr, "\tvars_size = %5d\n", info->vars_size); | |
6467 | ||
6468 | if (info->parm_size) | |
6469 | fprintf (stderr, "\tparm_size = %5d\n", info->parm_size); | |
6470 | ||
6471 | if (info->fixed_size) | |
6472 | fprintf (stderr, "\tfixed_size = %5d\n", info->fixed_size); | |
6473 | ||
6474 | if (info->gp_size) | |
6475 | fprintf (stderr, "\tgp_size = %5d\n", info->gp_size); | |
6476 | ||
6477 | if (info->fp_size) | |
6478 | fprintf (stderr, "\tfp_size = %5d\n", info->fp_size); | |
6479 | ||
00b960c7 AH |
6480 | if (info->altivec_size) |
6481 | fprintf (stderr, "\taltivec_size = %5d\n", info->altivec_size); | |
6482 | ||
6483 | if (info->vrsave_size) | |
6484 | fprintf (stderr, "\tvrsave_size = %5d\n", info->vrsave_size); | |
6485 | ||
6486 | if (info->altivec_padding_size) | |
6487 | fprintf (stderr, "\taltivec_padding_size= %5d\n", | |
6488 | info->altivec_padding_size); | |
6489 | ||
a4f6c312 | 6490 | if (info->lr_size) |
ed947a96 | 6491 | fprintf (stderr, "\tlr_size = %5d\n", info->lr_size); |
b6c9286a | 6492 | |
4697a36c MM |
6493 | if (info->cr_size) |
6494 | fprintf (stderr, "\tcr_size = %5d\n", info->cr_size); | |
6495 | ||
a4f6c312 | 6496 | if (info->toc_size) |
b6c9286a MM |
6497 | fprintf (stderr, "\ttoc_size = %5d\n", info->toc_size); |
6498 | ||
4697a36c MM |
6499 | if (info->save_size) |
6500 | fprintf (stderr, "\tsave_size = %5d\n", info->save_size); | |
6501 | ||
6502 | if (info->reg_size != 4) | |
6503 | fprintf (stderr, "\treg_size = %5d\n", info->reg_size); | |
6504 | ||
6505 | fprintf (stderr, "\n"); | |
9878760c | 6506 | } |
71f123ca FS |
6507 | |
6508 | rtx | |
6509 | rs6000_return_addr (count, frame) | |
6510 | int count; | |
6511 | rtx frame; | |
6512 | { | |
a4f6c312 SS |
6513 | /* Currently we don't optimize very well between prolog and body |
6514 | code and for PIC code the code can be actually quite bad, so | |
6515 | don't try to be too clever here. */ | |
3418dd3a FS |
6516 | if (count != 0 |
6517 | || flag_pic != 0 | |
6518 | || DEFAULT_ABI == ABI_AIX | |
6519 | || DEFAULT_ABI == ABI_AIX_NODESC) | |
71f123ca FS |
6520 | { |
6521 | cfun->machine->ra_needs_full_frame = 1; | |
8ac61af7 RK |
6522 | |
6523 | return | |
6524 | gen_rtx_MEM | |
6525 | (Pmode, | |
6526 | memory_address | |
6527 | (Pmode, | |
6528 | plus_constant (copy_to_reg | |
6529 | (gen_rtx_MEM (Pmode, | |
6530 | memory_address (Pmode, frame))), | |
6531 | RETURN_ADDRESS_OFFSET))); | |
71f123ca FS |
6532 | } |
6533 | ||
9e2f7ec7 | 6534 | return get_hard_reg_initial_val (Pmode, LINK_REGISTER_REGNUM); |
71f123ca FS |
6535 | } |
6536 | ||
6537 | static int | |
6538 | rs6000_ra_ever_killed () | |
6539 | { | |
6540 | rtx top; | |
6541 | ||
6542 | #ifdef ASM_OUTPUT_MI_THUNK | |
6543 | if (current_function_is_thunk) | |
6544 | return 0; | |
6545 | #endif | |
9e2f7ec7 DD |
6546 | if (!has_hard_reg_initial_val (Pmode, LINK_REGISTER_REGNUM) |
6547 | || cfun->machine->ra_needs_full_frame) | |
71f123ca FS |
6548 | return regs_ever_live[LINK_REGISTER_REGNUM]; |
6549 | ||
6550 | push_topmost_sequence (); | |
6551 | top = get_insns (); | |
6552 | pop_topmost_sequence (); | |
6553 | ||
6554 | return reg_set_between_p (gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM), | |
6555 | top, NULL_RTX); | |
6556 | } | |
4697a36c | 6557 | \f |
8cd8f856 GK |
6558 | /* Add a REG_MAYBE_DEAD note to the insn. */ |
6559 | static void | |
6560 | rs6000_maybe_dead (insn) | |
6561 | rtx insn; | |
6562 | { | |
6563 | REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD, | |
6564 | const0_rtx, | |
6565 | REG_NOTES (insn)); | |
6566 | } | |
6567 | ||
9ebbca7d | 6568 | /* Emit instructions needed to load the TOC register. |
c7ca610e | 6569 | This is only needed when TARGET_TOC, TARGET_MINIMAL_TOC, and there is |
9ebbca7d | 6570 | a constant pool; or for SVR4 -fpic. */ |
c7ca610e RK |
6571 | |
6572 | void | |
9ebbca7d GK |
6573 | rs6000_emit_load_toc_table (fromprolog) |
6574 | int fromprolog; | |
c7ca610e | 6575 | { |
9ebbca7d GK |
6576 | rtx dest; |
6577 | dest = gen_rtx_REG (Pmode, PIC_OFFSET_TABLE_REGNUM); | |
c7ca610e | 6578 | |
2bfcf297 | 6579 | if (TARGET_ELF && DEFAULT_ABI != ABI_AIX) |
c7ca610e | 6580 | { |
f607bc57 | 6581 | if (DEFAULT_ABI == ABI_V4 && flag_pic == 1) |
38c1f2d7 | 6582 | { |
9ebbca7d GK |
6583 | rtx temp = (fromprolog |
6584 | ? gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM) | |
6585 | : gen_reg_rtx (Pmode)); | |
2bfcf297 | 6586 | rs6000_maybe_dead (emit_insn (gen_load_toc_v4_pic_si (temp))); |
8cd8f856 | 6587 | rs6000_maybe_dead (emit_move_insn (dest, temp)); |
38c1f2d7 | 6588 | } |
9ebbca7d GK |
6589 | else if (flag_pic == 2) |
6590 | { | |
6591 | char buf[30]; | |
6592 | rtx tempLR = (fromprolog | |
6593 | ? gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM) | |
6594 | : gen_reg_rtx (Pmode)); | |
6595 | rtx temp0 = (fromprolog | |
6596 | ? gen_rtx_REG (Pmode, 0) | |
6597 | : gen_reg_rtx (Pmode)); | |
6598 | rtx symF; | |
6599 | ||
6600 | /* possibly create the toc section */ | |
6601 | if (! toc_initialized) | |
6602 | { | |
6603 | toc_section (); | |
6604 | function_section (current_function_decl); | |
6605 | } | |
6606 | ||
6607 | if (fromprolog) | |
6608 | { | |
6609 | rtx symL; | |
6610 | ||
6611 | ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno); | |
a8a05998 | 6612 | symF = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); |
38c1f2d7 | 6613 | |
9ebbca7d | 6614 | ASM_GENERATE_INTERNAL_LABEL (buf, "LCL", rs6000_pic_labelno); |
a8a05998 | 6615 | symL = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); |
38c1f2d7 | 6616 | |
8cd8f856 GK |
6617 | rs6000_maybe_dead (emit_insn (gen_load_toc_v4_PIC_1 (tempLR, |
6618 | symF))); | |
6619 | rs6000_maybe_dead (emit_move_insn (dest, tempLR)); | |
6620 | rs6000_maybe_dead (emit_insn (gen_load_toc_v4_PIC_2 (temp0, dest, | |
6621 | symL, | |
6622 | symF))); | |
9ebbca7d GK |
6623 | } |
6624 | else | |
6625 | { | |
6626 | rtx tocsym; | |
6627 | static int reload_toc_labelno = 0; | |
6628 | ||
b999aaeb | 6629 | tocsym = gen_rtx_SYMBOL_REF (Pmode, toc_label_name); |
38c1f2d7 | 6630 | |
9ebbca7d | 6631 | ASM_GENERATE_INTERNAL_LABEL (buf, "LCG", reload_toc_labelno++); |
a8a05998 | 6632 | symF = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); |
9ebbca7d | 6633 | |
8cd8f856 GK |
6634 | rs6000_maybe_dead (emit_insn (gen_load_toc_v4_PIC_1b (tempLR, |
6635 | symF, | |
6636 | tocsym))); | |
6637 | rs6000_maybe_dead (emit_move_insn (dest, tempLR)); | |
6638 | rs6000_maybe_dead (emit_move_insn (temp0, | |
6639 | gen_rtx_MEM (Pmode, dest))); | |
9ebbca7d | 6640 | } |
8cd8f856 | 6641 | rs6000_maybe_dead (emit_insn (gen_addsi3 (dest, temp0, dest))); |
9ebbca7d GK |
6642 | } |
6643 | else if (flag_pic == 0 && TARGET_MINIMAL_TOC) | |
6644 | { | |
6645 | /* This is for AIX code running in non-PIC ELF. */ | |
6646 | char buf[30]; | |
6647 | rtx realsym; | |
38c1f2d7 | 6648 | ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1); |
a8a05998 | 6649 | realsym = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); |
9ebbca7d | 6650 | |
8cd8f856 GK |
6651 | rs6000_maybe_dead (emit_insn (gen_elf_high (dest, realsym))); |
6652 | rs6000_maybe_dead (emit_insn (gen_elf_low (dest, dest, realsym))); | |
9ebbca7d GK |
6653 | } |
6654 | else | |
a4f6c312 | 6655 | abort (); |
9ebbca7d GK |
6656 | } |
6657 | else | |
6658 | { | |
6659 | if (TARGET_32BIT) | |
8cd8f856 | 6660 | rs6000_maybe_dead (emit_insn (gen_load_toc_aix_si (dest))); |
9ebbca7d | 6661 | else |
8cd8f856 | 6662 | rs6000_maybe_dead (emit_insn (gen_load_toc_aix_di (dest))); |
9ebbca7d GK |
6663 | } |
6664 | } | |
6665 | ||
6666 | int | |
6667 | get_TOC_alias_set () | |
6668 | { | |
6669 | static int set = -1; | |
6670 | if (set == -1) | |
6671 | set = new_alias_set (); | |
6672 | return set; | |
6673 | } | |
6674 | ||
6675 | /* This retuns nonzero if the current function uses the TOC. This is | |
6676 | determined by the presence of (unspec ... 7), which is generated by | |
6677 | the various load_toc_* patterns. */ | |
a4f6c312 | 6678 | |
9ebbca7d GK |
6679 | int |
6680 | uses_TOC () | |
6681 | { | |
6682 | rtx insn; | |
38c1f2d7 | 6683 | |
9ebbca7d | 6684 | for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) |
2c3c49de | 6685 | if (INSN_P (insn)) |
9ebbca7d GK |
6686 | { |
6687 | rtx pat = PATTERN (insn); | |
6688 | int i; | |
6689 | ||
8cd8f856 | 6690 | if (GET_CODE (pat) == PARALLEL) |
9ebbca7d GK |
6691 | for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++) |
6692 | if (GET_CODE (XVECEXP (PATTERN (insn), 0, i)) == UNSPEC | |
6693 | && XINT (XVECEXP (PATTERN (insn), 0, i), 1) == 7) | |
6694 | return 1; | |
38c1f2d7 | 6695 | } |
9ebbca7d GK |
6696 | return 0; |
6697 | } | |
38c1f2d7 | 6698 | |
9ebbca7d | 6699 | rtx |
a4f6c312 | 6700 | create_TOC_reference (symbol) |
9ebbca7d GK |
6701 | rtx symbol; |
6702 | { | |
a8a05998 ZW |
6703 | return gen_rtx_PLUS (Pmode, |
6704 | gen_rtx_REG (Pmode, TOC_REGISTER), | |
6705 | gen_rtx_CONST (Pmode, | |
6706 | gen_rtx_MINUS (Pmode, symbol, | |
b999aaeb | 6707 | gen_rtx_SYMBOL_REF (Pmode, toc_label_name)))); |
9ebbca7d | 6708 | } |
38c1f2d7 | 6709 | |
9ebbca7d GK |
6710 | #if TARGET_AIX |
6711 | /* __throw will restore its own return address to be the same as the | |
6712 | return address of the function that the throw is being made to. | |
6713 | This is unfortunate, because we want to check the original | |
6714 | return address to see if we need to restore the TOC. | |
6715 | So we have to squirrel it away here. | |
6716 | This is used only in compiling __throw and __rethrow. | |
c7ca610e | 6717 | |
9ebbca7d GK |
6718 | Most of this code should be removed by CSE. */ |
6719 | static rtx insn_after_throw; | |
c7ca610e | 6720 | |
a4f6c312 | 6721 | /* This does the saving... */ |
9ebbca7d GK |
6722 | void |
6723 | rs6000_aix_emit_builtin_unwind_init () | |
6724 | { | |
6725 | rtx mem; | |
6726 | rtx stack_top = gen_reg_rtx (Pmode); | |
6727 | rtx opcode_addr = gen_reg_rtx (Pmode); | |
6728 | ||
6729 | insn_after_throw = gen_reg_rtx (SImode); | |
6730 | ||
6731 | mem = gen_rtx_MEM (Pmode, hard_frame_pointer_rtx); | |
6732 | emit_move_insn (stack_top, mem); | |
6733 | ||
6734 | mem = gen_rtx_MEM (Pmode, | |
6735 | gen_rtx_PLUS (Pmode, stack_top, | |
6736 | GEN_INT (2 * GET_MODE_SIZE (Pmode)))); | |
6737 | emit_move_insn (opcode_addr, mem); | |
6738 | emit_move_insn (insn_after_throw, gen_rtx_MEM (SImode, opcode_addr)); | |
c7ca610e RK |
6739 | } |
6740 | ||
a4f6c312 SS |
6741 | /* Emit insns to _restore_ the TOC register, at runtime (specifically |
6742 | in _eh.o). Only used on AIX. | |
9ebbca7d GK |
6743 | |
6744 | The idea is that on AIX, function calls look like this: | |
6745 | bl somefunction-trampoline | |
6746 | lwz r2,20(sp) | |
6747 | ||
a4f6c312 | 6748 | and later, |
9ebbca7d GK |
6749 | somefunction-trampoline: |
6750 | stw r2,20(sp) | |
6751 | ... load function address in the count register ... | |
6752 | bctr | |
6753 | or like this, if the linker determines that this is not a cross-module call | |
6754 | and so the TOC need not be restored: | |
6755 | bl somefunction | |
6756 | nop | |
6757 | or like this, if the compiler could determine that this is not a | |
6758 | cross-module call: | |
6759 | bl somefunction | |
6760 | now, the tricky bit here is that register 2 is saved and restored | |
6761 | by the _linker_, so we can't readily generate debugging information | |
6762 | for it. So we need to go back up the call chain looking at the | |
6763 | insns at return addresses to see which calls saved the TOC register | |
6764 | and so see where it gets restored from. | |
6765 | ||
6766 | Oh, and all this gets done in RTL inside the eh_epilogue pattern, | |
6767 | just before the actual epilogue. | |
6768 | ||
6769 | On the bright side, this incurs no space or time overhead unless an | |
6770 | exception is thrown, except for the extra code in libgcc.a. | |
6771 | ||
6772 | The parameter STACKSIZE is a register containing (at runtime) | |
6773 | the amount to be popped off the stack in addition to the stack frame | |
6774 | of this routine (which will be __throw or __rethrow, and so is | |
6775 | guaranteed to have a stack frame). */ | |
a4f6c312 | 6776 | |
9ebbca7d GK |
6777 | void |
6778 | rs6000_emit_eh_toc_restore (stacksize) | |
6779 | rtx stacksize; | |
6780 | { | |
6781 | rtx top_of_stack; | |
6782 | rtx bottom_of_stack = gen_reg_rtx (Pmode); | |
6783 | rtx tocompare = gen_reg_rtx (SImode); | |
6784 | rtx opcode = gen_reg_rtx (SImode); | |
6785 | rtx opcode_addr = gen_reg_rtx (Pmode); | |
6786 | rtx mem; | |
6787 | rtx loop_start = gen_label_rtx (); | |
6788 | rtx no_toc_restore_needed = gen_label_rtx (); | |
6789 | rtx loop_exit = gen_label_rtx (); | |
6790 | ||
6791 | mem = gen_rtx_MEM (Pmode, hard_frame_pointer_rtx); | |
ba4828e0 | 6792 | set_mem_alias_set (mem, rs6000_sr_alias_set); |
9ebbca7d GK |
6793 | emit_move_insn (bottom_of_stack, mem); |
6794 | ||
6795 | top_of_stack = expand_binop (Pmode, add_optab, | |
6796 | bottom_of_stack, stacksize, | |
6797 | NULL_RTX, 1, OPTAB_WIDEN); | |
6798 | ||
6799 | emit_move_insn (tocompare, | |
6800 | GEN_INT (trunc_int_for_mode (TARGET_32BIT | |
6801 | ? 0x80410014 | |
6802 | : 0xE8410028, SImode))); | |
6803 | ||
6804 | if (insn_after_throw == NULL_RTX) | |
a4f6c312 | 6805 | abort (); |
9ebbca7d GK |
6806 | emit_move_insn (opcode, insn_after_throw); |
6807 | ||
6496a589 | 6808 | emit_note (NULL, NOTE_INSN_LOOP_BEG); |
9ebbca7d GK |
6809 | emit_label (loop_start); |
6810 | ||
6811 | do_compare_rtx_and_jump (opcode, tocompare, NE, 1, | |
06f4e019 | 6812 | SImode, NULL_RTX, NULL_RTX, |
9ebbca7d GK |
6813 | no_toc_restore_needed); |
6814 | ||
6815 | mem = gen_rtx_MEM (Pmode, | |
6816 | gen_rtx_PLUS (Pmode, bottom_of_stack, | |
6817 | GEN_INT (5 * GET_MODE_SIZE (Pmode)))); | |
6818 | emit_move_insn (gen_rtx_REG (Pmode, 2), mem); | |
6819 | ||
6820 | emit_label (no_toc_restore_needed); | |
6821 | do_compare_rtx_and_jump (top_of_stack, bottom_of_stack, EQ, 1, | |
06f4e019 | 6822 | Pmode, NULL_RTX, NULL_RTX, |
9ebbca7d GK |
6823 | loop_exit); |
6824 | ||
6825 | mem = gen_rtx_MEM (Pmode, bottom_of_stack); | |
ba4828e0 | 6826 | set_mem_alias_set (mem, rs6000_sr_alias_set); |
9ebbca7d GK |
6827 | emit_move_insn (bottom_of_stack, mem); |
6828 | ||
6829 | mem = gen_rtx_MEM (Pmode, | |
6830 | gen_rtx_PLUS (Pmode, bottom_of_stack, | |
6831 | GEN_INT (2 * GET_MODE_SIZE (Pmode)))); | |
6832 | emit_move_insn (opcode_addr, mem); | |
6833 | emit_move_insn (opcode, gen_rtx_MEM (SImode, opcode_addr)); | |
6834 | ||
6496a589 | 6835 | emit_note (NULL, NOTE_INSN_LOOP_CONT); |
9ebbca7d | 6836 | emit_jump (loop_start); |
6496a589 | 6837 | emit_note (NULL, NOTE_INSN_LOOP_END); |
9ebbca7d GK |
6838 | emit_label (loop_exit); |
6839 | } | |
6840 | #endif /* TARGET_AIX */ | |
38c1f2d7 | 6841 | \f |
ba4828e0 RK |
6842 | /* This ties together stack memory (MEM with an alias set of |
6843 | rs6000_sr_alias_set) and the change to the stack pointer. */ | |
6844 | ||
9ebbca7d GK |
6845 | static void |
6846 | rs6000_emit_stack_tie () | |
6847 | { | |
ba4828e0 RK |
6848 | rtx mem = gen_rtx_MEM (BLKmode, gen_rtx_REG (Pmode, STACK_POINTER_REGNUM)); |
6849 | ||
6850 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
9ebbca7d GK |
6851 | emit_insn (gen_stack_tie (mem)); |
6852 | } | |
38c1f2d7 | 6853 | |
9ebbca7d GK |
6854 | /* Emit the correct code for allocating stack space, as insns. |
6855 | If COPY_R12, make sure a copy of the old frame is left in r12. | |
6856 | The generated code may use hard register 0 as a temporary. */ | |
6857 | ||
6858 | static void | |
6859 | rs6000_emit_allocate_stack (size, copy_r12) | |
6860 | HOST_WIDE_INT size; | |
38c1f2d7 MM |
6861 | int copy_r12; |
6862 | { | |
9ebbca7d GK |
6863 | rtx insn; |
6864 | rtx stack_reg = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM); | |
6865 | rtx tmp_reg = gen_rtx_REG (Pmode, 0); | |
6866 | rtx todec = GEN_INT (-size); | |
a157febd GK |
6867 | |
6868 | if (current_function_limit_stack) | |
6869 | { | |
6870 | if (REG_P (stack_limit_rtx) | |
6871 | && REGNO (stack_limit_rtx) > 1 | |
6872 | && REGNO (stack_limit_rtx) <= 31) | |
6873 | { | |
9ebbca7d GK |
6874 | emit_insn (Pmode == SImode |
6875 | ? gen_addsi3 (tmp_reg, | |
6876 | stack_limit_rtx, | |
6877 | GEN_INT (size)) | |
6878 | : gen_adddi3 (tmp_reg, | |
6879 | stack_limit_rtx, | |
6880 | GEN_INT (size))); | |
6881 | ||
6882 | emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg, | |
6883 | const0_rtx)); | |
a157febd GK |
6884 | } |
6885 | else if (GET_CODE (stack_limit_rtx) == SYMBOL_REF | |
9ebbca7d | 6886 | && TARGET_32BIT |
f607bc57 | 6887 | && DEFAULT_ABI == ABI_V4) |
a157febd | 6888 | { |
9ebbca7d GK |
6889 | rtx toload = gen_rtx_CONST (VOIDmode, |
6890 | gen_rtx_PLUS (Pmode, | |
6891 | stack_limit_rtx, | |
6892 | GEN_INT (size))); | |
6893 | ||
6894 | emit_insn (gen_elf_high (tmp_reg, toload)); | |
6895 | emit_insn (gen_elf_low (tmp_reg, tmp_reg, toload)); | |
6896 | emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg, | |
6897 | const0_rtx)); | |
a157febd GK |
6898 | } |
6899 | else | |
6900 | warning ("stack limit expression is not supported"); | |
6901 | } | |
6902 | ||
9ebbca7d GK |
6903 | if (copy_r12 || ! TARGET_UPDATE) |
6904 | emit_move_insn (gen_rtx_REG (Pmode, 12), stack_reg); | |
6905 | ||
38c1f2d7 MM |
6906 | if (TARGET_UPDATE) |
6907 | { | |
9ebbca7d | 6908 | if (size > 32767) |
38c1f2d7 | 6909 | { |
9ebbca7d GK |
6910 | /* Need a note here so that try_split doesn't get confused. */ |
6911 | if (get_last_insn() == NULL_RTX) | |
6912 | emit_note (0, NOTE_INSN_DELETED); | |
6913 | insn = emit_move_insn (tmp_reg, todec); | |
6914 | try_split (PATTERN (insn), insn, 0); | |
6915 | todec = tmp_reg; | |
38c1f2d7 | 6916 | } |
9ebbca7d GK |
6917 | |
6918 | if (Pmode == SImode) | |
6919 | insn = emit_insn (gen_movsi_update (stack_reg, stack_reg, | |
6920 | todec, stack_reg)); | |
6921 | else | |
6922 | insn = emit_insn (gen_movdi_update (stack_reg, stack_reg, | |
6923 | todec, stack_reg)); | |
38c1f2d7 MM |
6924 | } |
6925 | else | |
6926 | { | |
9ebbca7d GK |
6927 | if (Pmode == SImode) |
6928 | insn = emit_insn (gen_addsi3 (stack_reg, stack_reg, todec)); | |
38c1f2d7 | 6929 | else |
9ebbca7d GK |
6930 | insn = emit_insn (gen_adddi3 (stack_reg, stack_reg, todec)); |
6931 | emit_move_insn (gen_rtx_MEM (Pmode, stack_reg), | |
6932 | gen_rtx_REG (Pmode, 12)); | |
6933 | } | |
6934 | ||
6935 | RTX_FRAME_RELATED_P (insn) = 1; | |
6936 | REG_NOTES (insn) = | |
6937 | gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, | |
6938 | gen_rtx_SET (VOIDmode, stack_reg, | |
6939 | gen_rtx_PLUS (Pmode, stack_reg, | |
6940 | GEN_INT (-size))), | |
6941 | REG_NOTES (insn)); | |
6942 | } | |
6943 | ||
a4f6c312 SS |
6944 | /* Add to 'insn' a note which is PATTERN (INSN) but with REG replaced |
6945 | with (plus:P (reg 1) VAL), and with REG2 replaced with RREG if REG2 | |
6946 | is not NULL. It would be nice if dwarf2out_frame_debug_expr could | |
6947 | deduce these equivalences by itself so it wasn't necessary to hold | |
6948 | its hand so much. */ | |
9ebbca7d GK |
6949 | |
6950 | static void | |
6951 | rs6000_frame_related (insn, reg, val, reg2, rreg) | |
6952 | rtx insn; | |
6953 | rtx reg; | |
6954 | HOST_WIDE_INT val; | |
6955 | rtx reg2; | |
6956 | rtx rreg; | |
6957 | { | |
6958 | rtx real, temp; | |
6959 | ||
6960 | real = copy_rtx (PATTERN (insn)); | |
6961 | ||
6962 | real = replace_rtx (real, reg, | |
6963 | gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode, | |
6964 | STACK_POINTER_REGNUM), | |
6965 | GEN_INT (val))); | |
6966 | ||
6967 | /* We expect that 'real' is either a SET or a PARALLEL containing | |
6968 | SETs (and possibly other stuff). In a PARALLEL, all the SETs | |
6969 | are important so they all have to be marked RTX_FRAME_RELATED_P. */ | |
6970 | ||
6971 | if (GET_CODE (real) == SET) | |
6972 | { | |
6973 | rtx set = real; | |
6974 | ||
6975 | temp = simplify_rtx (SET_SRC (set)); | |
6976 | if (temp) | |
6977 | SET_SRC (set) = temp; | |
6978 | temp = simplify_rtx (SET_DEST (set)); | |
6979 | if (temp) | |
6980 | SET_DEST (set) = temp; | |
6981 | if (GET_CODE (SET_DEST (set)) == MEM) | |
38c1f2d7 | 6982 | { |
9ebbca7d GK |
6983 | temp = simplify_rtx (XEXP (SET_DEST (set), 0)); |
6984 | if (temp) | |
6985 | XEXP (SET_DEST (set), 0) = temp; | |
38c1f2d7 | 6986 | } |
38c1f2d7 | 6987 | } |
9ebbca7d GK |
6988 | else if (GET_CODE (real) == PARALLEL) |
6989 | { | |
6990 | int i; | |
6991 | for (i = 0; i < XVECLEN (real, 0); i++) | |
6992 | if (GET_CODE (XVECEXP (real, 0, i)) == SET) | |
6993 | { | |
6994 | rtx set = XVECEXP (real, 0, i); | |
6995 | ||
6996 | temp = simplify_rtx (SET_SRC (set)); | |
6997 | if (temp) | |
6998 | SET_SRC (set) = temp; | |
6999 | temp = simplify_rtx (SET_DEST (set)); | |
7000 | if (temp) | |
7001 | SET_DEST (set) = temp; | |
7002 | if (GET_CODE (SET_DEST (set)) == MEM) | |
7003 | { | |
7004 | temp = simplify_rtx (XEXP (SET_DEST (set), 0)); | |
7005 | if (temp) | |
7006 | XEXP (SET_DEST (set), 0) = temp; | |
7007 | } | |
7008 | RTX_FRAME_RELATED_P (set) = 1; | |
7009 | } | |
7010 | } | |
7011 | else | |
a4f6c312 | 7012 | abort (); |
9ebbca7d GK |
7013 | |
7014 | if (reg2 != NULL_RTX) | |
7015 | real = replace_rtx (real, reg2, rreg); | |
7016 | ||
7017 | RTX_FRAME_RELATED_P (insn) = 1; | |
7018 | REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, | |
7019 | real, | |
7020 | REG_NOTES (insn)); | |
38c1f2d7 MM |
7021 | } |
7022 | ||
00b960c7 AH |
7023 | /* Returns an insn that has a vrsave set operation with the |
7024 | appropriate CLOBBERs. */ | |
7025 | ||
7026 | static rtx | |
7027 | generate_set_vrsave (reg, info) | |
7028 | rtx reg; | |
7029 | rs6000_stack_t *info; | |
7030 | { | |
7031 | int nclobs, i; | |
7032 | rtx insn, clobs[TOTAL_ALTIVEC_REGS + 1]; | |
7033 | ||
7034 | clobs[0] = gen_set_vrsave (reg); | |
7035 | ||
7036 | nclobs = 1; | |
7037 | ||
7038 | /* CLOBBER the registers in the mask. */ | |
7039 | ||
7040 | for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i) | |
7041 | if (info->vrsave_mask != 0 && ALTIVEC_REG_BIT (i) != 0) | |
7042 | clobs[nclobs++] = gen_rtx_CLOBBER (VOIDmode, | |
7043 | gen_rtx_REG (V4SImode, i)); | |
7044 | ||
7045 | insn = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (nclobs)); | |
7046 | ||
7047 | for (i = 0; i < nclobs; ++i) | |
7048 | XVECEXP (insn, 0, i) = clobs[i]; | |
7049 | ||
7050 | return insn; | |
7051 | } | |
7052 | ||
9ebbca7d GK |
7053 | /* Emit function prologue as insns. */ |
7054 | ||
9878760c | 7055 | void |
83720594 | 7056 | rs6000_emit_prologue () |
9878760c | 7057 | { |
4697a36c | 7058 | rs6000_stack_t *info = rs6000_stack_info (); |
9ebbca7d GK |
7059 | enum machine_mode reg_mode = TARGET_POWERPC64 ? DImode : SImode; |
7060 | int reg_size = TARGET_POWERPC64 ? 8 : 4; | |
7061 | rtx sp_reg_rtx = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM); | |
7062 | rtx frame_ptr_rtx = gen_rtx_REG (Pmode, 12); | |
7063 | rtx frame_reg_rtx = sp_reg_rtx; | |
7064 | rtx cr_save_rtx = NULL; | |
7065 | rtx insn; | |
7066 | int saving_FPRs_inline; | |
7067 | int using_store_multiple; | |
7068 | HOST_WIDE_INT sp_offset = 0; | |
7069 | ||
7070 | using_store_multiple = (TARGET_MULTIPLE && ! TARGET_POWERPC64 | |
7071 | && info->first_gp_reg_save < 31); | |
7072 | saving_FPRs_inline = (info->first_fp_reg_save == 64 | |
7073 | || FP_SAVE_INLINE (info->first_fp_reg_save)); | |
7074 | ||
7075 | /* For V.4, update stack before we do any saving and set back pointer. */ | |
f607bc57 | 7076 | if (info->push_p && DEFAULT_ABI == ABI_V4) |
9ebbca7d GK |
7077 | { |
7078 | if (info->total_size < 32767) | |
7079 | sp_offset = info->total_size; | |
7080 | else | |
7081 | frame_reg_rtx = frame_ptr_rtx; | |
7082 | rs6000_emit_allocate_stack (info->total_size, | |
7083 | (frame_reg_rtx != sp_reg_rtx | |
7084 | && (info->cr_save_p | |
7085 | || info->lr_save_p | |
7086 | || info->first_fp_reg_save < 64 | |
7087 | || info->first_gp_reg_save < 32 | |
7088 | ))); | |
7089 | if (frame_reg_rtx != sp_reg_rtx) | |
7090 | rs6000_emit_stack_tie (); | |
7091 | } | |
7092 | ||
7093 | /* If we use the link register, get it into r0. */ | |
7094 | if (info->lr_save_p) | |
71f123ca | 7095 | emit_move_insn (gen_rtx_REG (Pmode, 0), |
9ebbca7d GK |
7096 | gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)); |
7097 | ||
7098 | /* If we need to save CR, put it into r12. */ | |
7099 | if (info->cr_save_p && frame_reg_rtx != frame_ptr_rtx) | |
7100 | { | |
7101 | cr_save_rtx = gen_rtx_REG (SImode, 12); | |
7102 | emit_insn (gen_movesi_from_cr (cr_save_rtx)); | |
7103 | } | |
7104 | ||
a4f6c312 SS |
7105 | /* Do any required saving of fpr's. If only one or two to save, do |
7106 | it ourselves. Otherwise, call function. */ | |
9ebbca7d GK |
7107 | if (saving_FPRs_inline) |
7108 | { | |
7109 | int i; | |
7110 | for (i = 0; i < 64 - info->first_fp_reg_save; i++) | |
7111 | if ((regs_ever_live[info->first_fp_reg_save+i] | |
7112 | && ! call_used_regs[info->first_fp_reg_save+i])) | |
7113 | { | |
7114 | rtx addr, reg, mem; | |
7115 | reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i); | |
7116 | addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
7117 | GEN_INT (info->fp_save_offset | |
7118 | + sp_offset | |
a4f6c312 | 7119 | + 8 * i)); |
9ebbca7d | 7120 | mem = gen_rtx_MEM (DFmode, addr); |
ba4828e0 | 7121 | set_mem_alias_set (mem, rs6000_sr_alias_set); |
9ebbca7d GK |
7122 | |
7123 | insn = emit_move_insn (mem, reg); | |
7124 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, | |
7125 | NULL_RTX, NULL_RTX); | |
7126 | } | |
7127 | } | |
7128 | else if (info->first_fp_reg_save != 64) | |
7129 | { | |
7130 | int i; | |
7131 | char rname[30]; | |
520a57c8 | 7132 | const char *alloc_rname; |
9ebbca7d GK |
7133 | rtvec p; |
7134 | p = rtvec_alloc (2 + 64 - info->first_fp_reg_save); | |
7135 | ||
7136 | RTVEC_ELT (p, 0) = gen_rtx_CLOBBER (VOIDmode, | |
7137 | gen_rtx_REG (Pmode, | |
7138 | LINK_REGISTER_REGNUM)); | |
7139 | sprintf (rname, "%s%d%s", SAVE_FP_PREFIX, | |
7140 | info->first_fp_reg_save - 32, SAVE_FP_SUFFIX); | |
a8a05998 | 7141 | alloc_rname = ggc_strdup (rname); |
9ebbca7d GK |
7142 | RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode, |
7143 | gen_rtx_SYMBOL_REF (Pmode, | |
7144 | alloc_rname)); | |
7145 | for (i = 0; i < 64 - info->first_fp_reg_save; i++) | |
7146 | { | |
7147 | rtx addr, reg, mem; | |
7148 | reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i); | |
7149 | addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
7150 | GEN_INT (info->fp_save_offset | |
7151 | + sp_offset + 8*i)); | |
7152 | mem = gen_rtx_MEM (DFmode, addr); | |
ba4828e0 | 7153 | set_mem_alias_set (mem, rs6000_sr_alias_set); |
9ebbca7d GK |
7154 | |
7155 | RTVEC_ELT (p, i + 2) = gen_rtx_SET (VOIDmode, mem, reg); | |
7156 | } | |
7157 | insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p)); | |
7158 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, | |
7159 | NULL_RTX, NULL_RTX); | |
7160 | } | |
b6c9286a | 7161 | |
9ebbca7d GK |
7162 | /* Save GPRs. This is done as a PARALLEL if we are using |
7163 | the store-multiple instructions. */ | |
7164 | if (using_store_multiple) | |
b6c9286a | 7165 | { |
9ebbca7d GK |
7166 | rtvec p, dwarfp; |
7167 | int i; | |
7168 | p = rtvec_alloc (32 - info->first_gp_reg_save); | |
7169 | dwarfp = rtvec_alloc (32 - info->first_gp_reg_save); | |
7170 | for (i = 0; i < 32 - info->first_gp_reg_save; i++) | |
7171 | { | |
7172 | rtx addr, reg, mem; | |
7173 | reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i); | |
7174 | addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
7175 | GEN_INT (info->gp_save_offset | |
7176 | + sp_offset | |
7177 | + reg_size * i)); | |
7178 | mem = gen_rtx_MEM (reg_mode, addr); | |
ba4828e0 | 7179 | set_mem_alias_set (mem, rs6000_sr_alias_set); |
9ebbca7d GK |
7180 | |
7181 | RTVEC_ELT (p, i) = gen_rtx_SET (VOIDmode, mem, reg); | |
7182 | } | |
7183 | insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p)); | |
7184 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, | |
7185 | NULL_RTX, NULL_RTX); | |
b6c9286a MM |
7186 | } |
7187 | else | |
7188 | { | |
9ebbca7d GK |
7189 | int i; |
7190 | for (i = 0; i < 32 - info->first_gp_reg_save; i++) | |
7191 | if ((regs_ever_live[info->first_gp_reg_save+i] | |
7192 | && ! call_used_regs[info->first_gp_reg_save+i]) | |
7193 | || (i+info->first_gp_reg_save == PIC_OFFSET_TABLE_REGNUM | |
f607bc57 ZW |
7194 | && ((DEFAULT_ABI == ABI_V4 && flag_pic == 1) |
7195 | || (DEFAULT_ABI == ABI_DARWIN && flag_pic)))) | |
9ebbca7d GK |
7196 | { |
7197 | rtx addr, reg, mem; | |
7198 | reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i); | |
7199 | addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
7200 | GEN_INT (info->gp_save_offset | |
7201 | + sp_offset | |
7202 | + reg_size * i)); | |
7203 | mem = gen_rtx_MEM (reg_mode, addr); | |
ba4828e0 | 7204 | set_mem_alias_set (mem, rs6000_sr_alias_set); |
9ebbca7d GK |
7205 | |
7206 | insn = emit_move_insn (mem, reg); | |
7207 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, | |
7208 | NULL_RTX, NULL_RTX); | |
7209 | } | |
7210 | } | |
7211 | ||
83720594 RH |
7212 | /* ??? There's no need to emit actual instructions here, but it's the |
7213 | easiest way to get the frame unwind information emitted. */ | |
7214 | if (current_function_calls_eh_return) | |
7215 | { | |
78e1b90d DE |
7216 | unsigned int i, regno; |
7217 | ||
83720594 RH |
7218 | for (i = 0; ; ++i) |
7219 | { | |
7220 | rtx addr, reg, mem; | |
7221 | ||
7222 | regno = EH_RETURN_DATA_REGNO (i); | |
7223 | if (regno == INVALID_REGNUM) | |
7224 | break; | |
7225 | ||
7226 | reg = gen_rtx_REG (reg_mode, regno); | |
7227 | addr = plus_constant (frame_reg_rtx, | |
78e1b90d DE |
7228 | info->ehrd_offset + sp_offset |
7229 | + reg_size * (int) i); | |
83720594 | 7230 | mem = gen_rtx_MEM (reg_mode, addr); |
ba4828e0 | 7231 | set_mem_alias_set (mem, rs6000_sr_alias_set); |
83720594 RH |
7232 | |
7233 | insn = emit_move_insn (mem, reg); | |
7234 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, | |
7235 | NULL_RTX, NULL_RTX); | |
7236 | } | |
7237 | } | |
7238 | ||
9ebbca7d GK |
7239 | /* Save lr if we used it. */ |
7240 | if (info->lr_save_p) | |
7241 | { | |
7242 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
7243 | GEN_INT (info->lr_save_offset + sp_offset)); | |
7244 | rtx reg = gen_rtx_REG (Pmode, 0); | |
7245 | rtx mem = gen_rtx_MEM (Pmode, addr); | |
7246 | /* This should not be of rs6000_sr_alias_set, because of | |
7247 | __builtin_return_address. */ | |
7248 | ||
7249 | insn = emit_move_insn (mem, reg); | |
7250 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, | |
7251 | reg, gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)); | |
7252 | } | |
7253 | ||
7254 | /* Save CR if we use any that must be preserved. */ | |
7255 | if (info->cr_save_p) | |
7256 | { | |
7257 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
7258 | GEN_INT (info->cr_save_offset + sp_offset)); | |
7259 | rtx mem = gen_rtx_MEM (SImode, addr); | |
ba4828e0 RK |
7260 | |
7261 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
9ebbca7d GK |
7262 | |
7263 | /* If r12 was used to hold the original sp, copy cr into r0 now | |
7264 | that it's free. */ | |
7265 | if (REGNO (frame_reg_rtx) == 12) | |
7266 | { | |
7267 | cr_save_rtx = gen_rtx_REG (SImode, 0); | |
7268 | emit_insn (gen_movesi_from_cr (cr_save_rtx)); | |
7269 | } | |
7270 | insn = emit_move_insn (mem, cr_save_rtx); | |
7271 | ||
7272 | /* Now, there's no way that dwarf2out_frame_debug_expr is going | |
7273 | to understand '(unspec:SI [(reg:CC 68) ...] 19)'. But that's | |
7274 | OK. All we have to do is specify that _one_ condition code | |
7275 | register is saved in this stack slot. The thrower's epilogue | |
a1dc9455 FS |
7276 | will then restore all the call-saved registers. |
7277 | We use CR2_REGNO (70) to be compatible with gcc-2.95 on Linux. */ | |
9ebbca7d | 7278 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, |
a1dc9455 | 7279 | cr_save_rtx, gen_rtx_REG (SImode, CR2_REGNO)); |
9ebbca7d GK |
7280 | } |
7281 | ||
7282 | /* Update stack and set back pointer unless this is V.4, | |
7283 | for which it was done previously. */ | |
f607bc57 | 7284 | if (info->push_p && DEFAULT_ABI != ABI_V4) |
9ebbca7d GK |
7285 | rs6000_emit_allocate_stack (info->total_size, FALSE); |
7286 | ||
00b960c7 AH |
7287 | /* Save AltiVec registers if needed. */ |
7288 | if (TARGET_ALTIVEC_ABI && info->altivec_size != 0) | |
7289 | { | |
7290 | int i; | |
7291 | ||
7292 | /* There should be a non inline version of this, for when we | |
7293 | are saving lots of vector registers. */ | |
7294 | for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i) | |
7295 | if (regs_ever_live[i] && ! call_used_regs[i]) | |
7296 | { | |
7297 | rtx addr, areg, savereg, mem; | |
7298 | ||
7299 | savereg = gen_rtx_REG (V4SImode, i); | |
7300 | ||
7301 | areg = gen_rtx_REG (Pmode, 0); | |
7302 | emit_move_insn | |
7303 | (areg, GEN_INT (info->altivec_save_offset | |
7304 | + sp_offset | |
7305 | + 16 * (i - info->first_altivec_reg_save))); | |
7306 | ||
7307 | /* AltiVec addressing mode is [reg+reg]. */ | |
7308 | addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, areg); | |
7309 | mem = gen_rtx_MEM (V4SImode, addr); | |
7310 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
7311 | ||
7312 | insn = emit_move_insn (mem, savereg); | |
7313 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, | |
7314 | NULL_RTX, NULL_RTX); | |
7315 | } | |
7316 | } | |
7317 | ||
7318 | /* VRSAVE is a bit vector representing which AltiVec registers | |
7319 | are used. The OS uses this to determine which vector | |
7320 | registers to save on a context switch. We need to save | |
7321 | VRSAVE on the stack frame, add whatever AltiVec registers we | |
7322 | used in this function, and do the corresponding magic in the | |
7323 | epilogue. */ | |
7324 | ||
7325 | if (TARGET_ALTIVEC && info->vrsave_mask != 0) | |
7326 | { | |
7327 | rtx reg, addr, mem; | |
7328 | ||
7329 | /* Get VRSAVE onto a GPR. */ | |
7330 | reg = gen_rtx_REG (SImode, 12); | |
7331 | emit_insn (gen_get_vrsave (reg)); | |
7332 | ||
7333 | /* Save VRSAVE. */ | |
7334 | addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
7335 | GEN_INT (info->vrsave_save_offset + sp_offset)); | |
7336 | mem = gen_rtx_MEM (SImode, addr); | |
7337 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
7338 | insn = emit_move_insn (mem, reg); | |
7339 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, | |
7340 | NULL_RTX, NULL_RTX); | |
7341 | ||
7342 | /* Include the registers in the mask. */ | |
7343 | emit_insn (gen_iorsi3 (reg, reg, GEN_INT ((int) info->vrsave_mask))); | |
7344 | ||
7345 | insn = emit_insn (generate_set_vrsave (reg, info)); | |
7346 | ||
7347 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, | |
7348 | NULL_RTX, NULL_RTX); | |
7349 | } | |
7350 | ||
9ebbca7d GK |
7351 | /* Set frame pointer, if needed. */ |
7352 | if (frame_pointer_needed) | |
7353 | { | |
7354 | insn = emit_move_insn (gen_rtx_REG (reg_mode, FRAME_POINTER_REGNUM), | |
7355 | sp_reg_rtx); | |
7356 | RTX_FRAME_RELATED_P (insn) = 1; | |
b6c9286a | 7357 | } |
9878760c | 7358 | |
9ebbca7d GK |
7359 | /* If we are using PIC_OFFSET_TABLE_REGNUM, we need to set it up. */ |
7360 | if ((TARGET_TOC && TARGET_MINIMAL_TOC && get_pool_size () != 0) | |
f607bc57 ZW |
7361 | || (DEFAULT_ABI == ABI_V4 && flag_pic == 1 |
7362 | && regs_ever_live[PIC_OFFSET_TABLE_REGNUM])) | |
9ebbca7d GK |
7363 | { |
7364 | /* If emit_load_toc_table will use the link register, we need to save | |
7365 | it. We use R11 for this purpose because emit_load_toc_table | |
7366 | can use register 0. This allows us to use a plain 'blr' to return | |
7367 | from the procedure more often. */ | |
d5fa86ba GK |
7368 | int save_LR_around_toc_setup = (TARGET_ELF && flag_pic != 0 |
7369 | && ! info->lr_save_p | |
7370 | && EXIT_BLOCK_PTR->pred != NULL); | |
9ebbca7d GK |
7371 | if (save_LR_around_toc_setup) |
7372 | emit_move_insn (gen_rtx_REG (Pmode, 11), | |
7373 | gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)); | |
7374 | ||
7375 | rs6000_emit_load_toc_table (TRUE); | |
7376 | ||
7377 | if (save_LR_around_toc_setup) | |
7378 | emit_move_insn (gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM), | |
7379 | gen_rtx_REG (Pmode, 11)); | |
7380 | } | |
ee890fe2 SS |
7381 | |
7382 | if (DEFAULT_ABI == ABI_DARWIN | |
7383 | && flag_pic && current_function_uses_pic_offset_table) | |
7384 | { | |
7385 | rtx dest = gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM); | |
7386 | ||
7387 | rs6000_maybe_dead (emit_insn (gen_load_macho_picbase (dest))); | |
7388 | ||
7389 | rs6000_maybe_dead ( | |
7390 | emit_move_insn (gen_rtx_REG (Pmode, PIC_OFFSET_TABLE_REGNUM), | |
7391 | gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM))); | |
7392 | } | |
9ebbca7d GK |
7393 | } |
7394 | ||
9ebbca7d | 7395 | /* Write function prologue. */ |
a4f6c312 | 7396 | |
08c148a8 NB |
7397 | static void |
7398 | rs6000_output_function_prologue (file, size) | |
9ebbca7d | 7399 | FILE *file; |
08c148a8 | 7400 | HOST_WIDE_INT size ATTRIBUTE_UNUSED; |
9ebbca7d GK |
7401 | { |
7402 | rs6000_stack_t *info = rs6000_stack_info (); | |
7403 | ||
4697a36c MM |
7404 | if (TARGET_DEBUG_STACK) |
7405 | debug_stack_info (info); | |
9878760c | 7406 | |
a4f6c312 SS |
7407 | /* Write .extern for any function we will call to save and restore |
7408 | fp values. */ | |
7409 | if (info->first_fp_reg_save < 64 | |
7410 | && !FP_SAVE_INLINE (info->first_fp_reg_save)) | |
4d30c363 | 7411 | fprintf (file, "\t.extern %s%d%s\n\t.extern %s%d%s\n", |
4697a36c | 7412 | SAVE_FP_PREFIX, info->first_fp_reg_save - 32, SAVE_FP_SUFFIX, |
a4f6c312 SS |
7413 | RESTORE_FP_PREFIX, info->first_fp_reg_save - 32, |
7414 | RESTORE_FP_SUFFIX); | |
9878760c | 7415 | |
c764f757 RK |
7416 | /* Write .extern for AIX common mode routines, if needed. */ |
7417 | if (! TARGET_POWER && ! TARGET_POWERPC && ! common_mode_defined) | |
7418 | { | |
f6709c70 JW |
7419 | fputs ("\t.extern __mulh\n", file); |
7420 | fputs ("\t.extern __mull\n", file); | |
7421 | fputs ("\t.extern __divss\n", file); | |
7422 | fputs ("\t.extern __divus\n", file); | |
7423 | fputs ("\t.extern __quoss\n", file); | |
7424 | fputs ("\t.extern __quous\n", file); | |
c764f757 RK |
7425 | common_mode_defined = 1; |
7426 | } | |
9878760c | 7427 | |
9ebbca7d | 7428 | if (! HAVE_prologue) |
979721f8 | 7429 | { |
9ebbca7d GK |
7430 | start_sequence (); |
7431 | ||
a4f6c312 SS |
7432 | /* A NOTE_INSN_DELETED is supposed to be at the start and end of |
7433 | the "toplevel" insn chain. */ | |
9ebbca7d GK |
7434 | emit_note (0, NOTE_INSN_DELETED); |
7435 | rs6000_emit_prologue (); | |
7436 | emit_note (0, NOTE_INSN_DELETED); | |
7437 | ||
7438 | if (TARGET_DEBUG_STACK) | |
a4f6c312 SS |
7439 | debug_rtx_list (get_insns (), 100); |
7440 | final (get_insns (), file, FALSE, FALSE); | |
9ebbca7d | 7441 | end_sequence (); |
979721f8 MM |
7442 | } |
7443 | ||
9ebbca7d GK |
7444 | rs6000_pic_labelno++; |
7445 | } | |
7446 | ||
7447 | /* Emit function epilogue as insns. | |
9878760c | 7448 | |
9ebbca7d GK |
7449 | At present, dwarf2out_frame_debug_expr doesn't understand |
7450 | register restores, so we don't bother setting RTX_FRAME_RELATED_P | |
7451 | anywhere in the epilogue. Most of the insns below would in any case | |
7452 | need special notes to explain where r11 is in relation to the stack. */ | |
9878760c | 7453 | |
9ebbca7d | 7454 | void |
83720594 | 7455 | rs6000_emit_epilogue (sibcall) |
9ebbca7d GK |
7456 | int sibcall; |
7457 | { | |
7458 | rs6000_stack_t *info; | |
7459 | int restoring_FPRs_inline; | |
7460 | int using_load_multiple; | |
7461 | int using_mfcr_multiple; | |
7462 | int use_backchain_to_restore_sp; | |
7463 | int sp_offset = 0; | |
7464 | rtx sp_reg_rtx = gen_rtx_REG (Pmode, 1); | |
7465 | rtx frame_reg_rtx = sp_reg_rtx; | |
7466 | enum machine_mode reg_mode = TARGET_POWERPC64 ? DImode : SImode; | |
7467 | int reg_size = TARGET_POWERPC64 ? 8 : 4; | |
7468 | int i; | |
7469 | ||
7470 | info = rs6000_stack_info (); | |
7471 | using_load_multiple = (TARGET_MULTIPLE && ! TARGET_POWERPC64 | |
7472 | && info->first_gp_reg_save < 31); | |
7473 | restoring_FPRs_inline = (sibcall | |
83720594 | 7474 | || current_function_calls_eh_return |
9ebbca7d GK |
7475 | || info->first_fp_reg_save == 64 |
7476 | || FP_SAVE_INLINE (info->first_fp_reg_save)); | |
7477 | use_backchain_to_restore_sp = (frame_pointer_needed | |
7478 | || current_function_calls_alloca | |
7479 | || info->total_size > 32767); | |
7480 | using_mfcr_multiple = (rs6000_cpu == PROCESSOR_PPC601 | |
7481 | || rs6000_cpu == PROCESSOR_PPC603 | |
7482 | || rs6000_cpu == PROCESSOR_PPC750 | |
7483 | || optimize_size); | |
7484 | ||
7485 | /* If we have a frame pointer, a call to alloca, or a large stack | |
7486 | frame, restore the old stack pointer using the backchain. Otherwise, | |
7487 | we know what size to update it with. */ | |
7488 | if (use_backchain_to_restore_sp) | |
bacbde18 | 7489 | { |
9ebbca7d GK |
7490 | /* Under V.4, don't reset the stack pointer until after we're done |
7491 | loading the saved registers. */ | |
f607bc57 | 7492 | if (DEFAULT_ABI == ABI_V4) |
9ebbca7d | 7493 | frame_reg_rtx = gen_rtx_REG (Pmode, 11); |
4697a36c | 7494 | |
9ebbca7d GK |
7495 | emit_move_insn (frame_reg_rtx, |
7496 | gen_rtx_MEM (Pmode, sp_reg_rtx)); | |
7497 | ||
bacbde18 | 7498 | } |
9ebbca7d | 7499 | else if (info->push_p) |
85638c0d | 7500 | { |
f607bc57 | 7501 | if (DEFAULT_ABI == ABI_V4) |
9ebbca7d GK |
7502 | sp_offset = info->total_size; |
7503 | else | |
7504 | { | |
7505 | emit_insn (TARGET_32BIT | |
7506 | ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx, | |
7507 | GEN_INT (info->total_size)) | |
7508 | : gen_adddi3 (sp_reg_rtx, sp_reg_rtx, | |
7509 | GEN_INT (info->total_size))); | |
7510 | } | |
85638c0d | 7511 | } |
9ebbca7d GK |
7512 | |
7513 | /* Get the old lr if we saved it. */ | |
7514 | if (info->lr_save_p) | |
b6c9286a | 7515 | { |
9ebbca7d GK |
7516 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, |
7517 | GEN_INT (info->lr_save_offset + sp_offset)); | |
7518 | rtx mem = gen_rtx_MEM (Pmode, addr); | |
ba4828e0 RK |
7519 | |
7520 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
b6c9286a | 7521 | |
9ebbca7d | 7522 | emit_move_insn (gen_rtx_REG (Pmode, 0), mem); |
b6c9286a | 7523 | } |
9ebbca7d GK |
7524 | |
7525 | /* Get the old cr if we saved it. */ | |
7526 | if (info->cr_save_p) | |
7527 | { | |
7528 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
7529 | GEN_INT (info->cr_save_offset + sp_offset)); | |
7530 | rtx mem = gen_rtx_MEM (SImode, addr); | |
ba4828e0 RK |
7531 | |
7532 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
b6c9286a | 7533 | |
9ebbca7d GK |
7534 | emit_move_insn (gen_rtx_REG (SImode, 12), mem); |
7535 | } | |
7536 | ||
7537 | /* Set LR here to try to overlap restores below. */ | |
4697a36c | 7538 | if (info->lr_save_p) |
9ebbca7d GK |
7539 | emit_move_insn (gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM), |
7540 | gen_rtx_REG (Pmode, 0)); | |
7541 | ||
83720594 RH |
7542 | /* Load exception handler data registers, if needed. */ |
7543 | if (current_function_calls_eh_return) | |
7544 | { | |
78e1b90d DE |
7545 | unsigned int i, regno; |
7546 | ||
83720594 RH |
7547 | for (i = 0; ; ++i) |
7548 | { | |
7549 | rtx addr, mem; | |
7550 | ||
7551 | regno = EH_RETURN_DATA_REGNO (i); | |
7552 | if (regno == INVALID_REGNUM) | |
7553 | break; | |
7554 | ||
7555 | addr = plus_constant (frame_reg_rtx, | |
78e1b90d DE |
7556 | info->ehrd_offset + sp_offset |
7557 | + reg_size * (int) i); | |
83720594 | 7558 | mem = gen_rtx_MEM (reg_mode, addr); |
ba4828e0 | 7559 | set_mem_alias_set (mem, rs6000_sr_alias_set); |
83720594 RH |
7560 | |
7561 | emit_move_insn (gen_rtx_REG (reg_mode, regno), mem); | |
7562 | } | |
7563 | } | |
9ebbca7d GK |
7564 | |
7565 | /* Restore GPRs. This is done as a PARALLEL if we are using | |
7566 | the load-multiple instructions. */ | |
7567 | if (using_load_multiple) | |
979721f8 | 7568 | { |
9ebbca7d GK |
7569 | rtvec p; |
7570 | p = rtvec_alloc (32 - info->first_gp_reg_save); | |
7571 | for (i = 0; i < 32 - info->first_gp_reg_save; i++) | |
979721f8 | 7572 | { |
9ebbca7d GK |
7573 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, |
7574 | GEN_INT (info->gp_save_offset | |
7575 | + sp_offset | |
7576 | + reg_size * i)); | |
7577 | rtx mem = gen_rtx_MEM (reg_mode, addr); | |
ba4828e0 RK |
7578 | |
7579 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
9ebbca7d GK |
7580 | |
7581 | RTVEC_ELT (p, i) = | |
7582 | gen_rtx_SET (VOIDmode, | |
7583 | gen_rtx_REG (reg_mode, info->first_gp_reg_save + i), | |
7584 | mem); | |
979721f8 | 7585 | } |
9ebbca7d | 7586 | emit_insn (gen_rtx_PARALLEL (VOIDmode, p)); |
979721f8 | 7587 | } |
9ebbca7d GK |
7588 | else |
7589 | for (i = 0; i < 32 - info->first_gp_reg_save; i++) | |
7590 | if ((regs_ever_live[info->first_gp_reg_save+i] | |
7591 | && ! call_used_regs[info->first_gp_reg_save+i]) | |
7592 | || (i+info->first_gp_reg_save == PIC_OFFSET_TABLE_REGNUM | |
f607bc57 ZW |
7593 | && ((DEFAULT_ABI == ABI_V4 && flag_pic == 1) |
7594 | || (DEFAULT_ABI == ABI_DARWIN && flag_pic)))) | |
9ebbca7d GK |
7595 | { |
7596 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
7597 | GEN_INT (info->gp_save_offset | |
7598 | + sp_offset | |
7599 | + reg_size * i)); | |
7600 | rtx mem = gen_rtx_MEM (reg_mode, addr); | |
ba4828e0 RK |
7601 | |
7602 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
9ebbca7d GK |
7603 | |
7604 | emit_move_insn (gen_rtx_REG (reg_mode, | |
7605 | info->first_gp_reg_save + i), | |
7606 | mem); | |
7607 | } | |
9878760c | 7608 | |
9ebbca7d GK |
7609 | /* Restore fpr's if we need to do it without calling a function. */ |
7610 | if (restoring_FPRs_inline) | |
7611 | for (i = 0; i < 64 - info->first_fp_reg_save; i++) | |
7612 | if ((regs_ever_live[info->first_fp_reg_save+i] | |
7613 | && ! call_used_regs[info->first_fp_reg_save+i])) | |
7614 | { | |
7615 | rtx addr, mem; | |
7616 | addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
7617 | GEN_INT (info->fp_save_offset | |
7618 | + sp_offset | |
a4f6c312 | 7619 | + 8 * i)); |
9ebbca7d | 7620 | mem = gen_rtx_MEM (DFmode, addr); |
ba4828e0 | 7621 | set_mem_alias_set (mem, rs6000_sr_alias_set); |
9ebbca7d GK |
7622 | |
7623 | emit_move_insn (gen_rtx_REG (DFmode, | |
7624 | info->first_fp_reg_save + i), | |
7625 | mem); | |
7626 | } | |
8d30c4ee | 7627 | |
00b960c7 AH |
7628 | /* Restore AltiVec registers if needed. */ |
7629 | if (TARGET_ALTIVEC_ABI && info->altivec_size != 0) | |
7630 | { | |
7631 | int i; | |
7632 | ||
7633 | for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i) | |
7634 | if (regs_ever_live[i] && ! call_used_regs[i]) | |
7635 | { | |
7636 | rtx addr, areg, mem; | |
7637 | ||
7638 | areg = gen_rtx_REG (Pmode, 0); | |
7639 | emit_move_insn | |
7640 | (areg, GEN_INT (info->altivec_save_offset | |
7641 | + sp_offset | |
7642 | + 16 * (i - info->first_altivec_reg_save))); | |
7643 | ||
7644 | /* AltiVec addressing mode is [reg+reg]. */ | |
7645 | addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, areg); | |
7646 | mem = gen_rtx_MEM (V4SImode, addr); | |
7647 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
7648 | ||
7649 | emit_move_insn (gen_rtx_REG (V4SImode, i), mem); | |
7650 | } | |
7651 | } | |
7652 | ||
7653 | /* Restore VRSAVE if needed. */ | |
7654 | if (TARGET_ALTIVEC_ABI && info->vrsave_mask != 0) | |
7655 | { | |
7656 | rtx addr, mem, reg; | |
7657 | ||
7658 | addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
7659 | GEN_INT (info->vrsave_save_offset + sp_offset)); | |
7660 | mem = gen_rtx_MEM (SImode, addr); | |
7661 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
7662 | reg = gen_rtx_REG (SImode, 12); | |
7663 | emit_move_insn (reg, mem); | |
7664 | ||
7665 | emit_insn (generate_set_vrsave (reg, info)); | |
7666 | } | |
7667 | ||
9ebbca7d GK |
7668 | /* If we saved cr, restore it here. Just those that were used. */ |
7669 | if (info->cr_save_p) | |
979721f8 | 7670 | { |
9ebbca7d | 7671 | rtx r12_rtx = gen_rtx_REG (SImode, 12); |
e35b9579 | 7672 | int count = 0; |
9ebbca7d GK |
7673 | |
7674 | if (using_mfcr_multiple) | |
979721f8 | 7675 | { |
9ebbca7d GK |
7676 | for (i = 0; i < 8; i++) |
7677 | if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i]) | |
e35b9579 | 7678 | count++; |
9ebbca7d | 7679 | if (count == 0) |
e35b9579 GK |
7680 | abort (); |
7681 | } | |
7682 | ||
7683 | if (using_mfcr_multiple && count > 1) | |
7684 | { | |
7685 | rtvec p; | |
7686 | int ndx; | |
9ebbca7d | 7687 | |
e35b9579 | 7688 | p = rtvec_alloc (count); |
9ebbca7d | 7689 | |
e35b9579 | 7690 | ndx = 0; |
9ebbca7d GK |
7691 | for (i = 0; i < 8; i++) |
7692 | if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i]) | |
7693 | { | |
7694 | rtvec r = rtvec_alloc (2); | |
7695 | RTVEC_ELT (r, 0) = r12_rtx; | |
7696 | RTVEC_ELT (r, 1) = GEN_INT (1 << (7-i)); | |
e35b9579 | 7697 | RTVEC_ELT (p, ndx) = |
9ebbca7d GK |
7698 | gen_rtx_SET (VOIDmode, gen_rtx_REG (CCmode, CR0_REGNO+i), |
7699 | gen_rtx_UNSPEC (CCmode, r, 20)); | |
e35b9579 | 7700 | ndx++; |
9ebbca7d GK |
7701 | } |
7702 | emit_insn (gen_rtx_PARALLEL (VOIDmode, p)); | |
e35b9579 GK |
7703 | if (ndx != count) |
7704 | abort (); | |
979721f8 MM |
7705 | } |
7706 | else | |
9ebbca7d GK |
7707 | for (i = 0; i < 8; i++) |
7708 | if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i]) | |
979721f8 | 7709 | { |
9ebbca7d GK |
7710 | emit_insn (gen_movsi_to_cr_one (gen_rtx_REG (CCmode, |
7711 | CR0_REGNO+i), | |
7712 | r12_rtx)); | |
979721f8 | 7713 | } |
979721f8 MM |
7714 | } |
7715 | ||
9ebbca7d GK |
7716 | /* If this is V.4, unwind the stack pointer after all of the loads |
7717 | have been done. We need to emit a block here so that sched | |
7718 | doesn't decide to move the sp change before the register restores | |
7719 | (which may not have any obvious dependency on the stack). This | |
7720 | doesn't hurt performance, because there is no scheduling that can | |
7721 | be done after this point. */ | |
f607bc57 | 7722 | if (DEFAULT_ABI == ABI_V4) |
b6c9286a | 7723 | { |
9ebbca7d GK |
7724 | if (frame_reg_rtx != sp_reg_rtx) |
7725 | rs6000_emit_stack_tie (); | |
b6c9286a | 7726 | |
9ebbca7d | 7727 | if (use_backchain_to_restore_sp) |
b6c9286a | 7728 | { |
9ebbca7d | 7729 | emit_move_insn (sp_reg_rtx, frame_reg_rtx); |
b6c9286a | 7730 | } |
9ebbca7d | 7731 | else if (sp_offset != 0) |
13f1623b | 7732 | { |
9ebbca7d GK |
7733 | emit_insn (Pmode == SImode |
7734 | ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx, | |
7735 | GEN_INT (sp_offset)) | |
7736 | : gen_adddi3 (sp_reg_rtx, sp_reg_rtx, | |
7737 | GEN_INT (sp_offset))); | |
13f1623b | 7738 | } |
9ebbca7d | 7739 | } |
b6c9286a | 7740 | |
83720594 RH |
7741 | if (current_function_calls_eh_return) |
7742 | { | |
7743 | rtx sa = EH_RETURN_STACKADJ_RTX; | |
7744 | emit_insn (Pmode == SImode | |
7745 | ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx, sa) | |
7746 | : gen_adddi3 (sp_reg_rtx, sp_reg_rtx, sa)); | |
7747 | } | |
7748 | ||
9ebbca7d GK |
7749 | if (!sibcall) |
7750 | { | |
7751 | rtvec p; | |
7752 | if (! restoring_FPRs_inline) | |
7753 | p = rtvec_alloc (3 + 64 - info->first_fp_reg_save); | |
7754 | else | |
7755 | p = rtvec_alloc (2); | |
b6c9286a | 7756 | |
e35b9579 GK |
7757 | RTVEC_ELT (p, 0) = gen_rtx_RETURN (VOIDmode); |
7758 | RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode, | |
9ebbca7d GK |
7759 | gen_rtx_REG (Pmode, |
7760 | LINK_REGISTER_REGNUM)); | |
9ebbca7d GK |
7761 | |
7762 | /* If we have to restore more than two FP registers, branch to the | |
7763 | restore function. It will return to our caller. */ | |
7764 | if (! restoring_FPRs_inline) | |
7765 | { | |
7766 | int i; | |
7767 | char rname[30]; | |
520a57c8 | 7768 | const char *alloc_rname; |
979721f8 | 7769 | |
9ebbca7d GK |
7770 | sprintf (rname, "%s%d%s", RESTORE_FP_PREFIX, |
7771 | info->first_fp_reg_save - 32, RESTORE_FP_SUFFIX); | |
a8a05998 | 7772 | alloc_rname = ggc_strdup (rname); |
9ebbca7d GK |
7773 | RTVEC_ELT (p, 2) = gen_rtx_USE (VOIDmode, |
7774 | gen_rtx_SYMBOL_REF (Pmode, | |
7775 | alloc_rname)); | |
b6c9286a | 7776 | |
9ebbca7d GK |
7777 | for (i = 0; i < 64 - info->first_fp_reg_save; i++) |
7778 | { | |
7779 | rtx addr, mem; | |
7780 | addr = gen_rtx_PLUS (Pmode, sp_reg_rtx, | |
7781 | GEN_INT (info->fp_save_offset + 8*i)); | |
7782 | mem = gen_rtx_MEM (DFmode, addr); | |
ba4828e0 | 7783 | set_mem_alias_set (mem, rs6000_sr_alias_set); |
9ebbca7d GK |
7784 | |
7785 | RTVEC_ELT (p, i+3) = | |
7786 | gen_rtx_SET (VOIDmode, | |
7787 | gen_rtx_REG (DFmode, info->first_fp_reg_save + i), | |
7788 | mem); | |
b6c9286a MM |
7789 | } |
7790 | } | |
9ebbca7d GK |
7791 | |
7792 | emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p)); | |
3daf36a4 | 7793 | } |
9878760c RK |
7794 | } |
7795 | ||
7796 | /* Write function epilogue. */ | |
7797 | ||
08c148a8 NB |
7798 | static void |
7799 | rs6000_output_function_epilogue (file, size) | |
9878760c | 7800 | FILE *file; |
08c148a8 | 7801 | HOST_WIDE_INT size ATTRIBUTE_UNUSED; |
9878760c | 7802 | { |
4697a36c | 7803 | rs6000_stack_t *info = rs6000_stack_info (); |
9878760c | 7804 | |
9ebbca7d | 7805 | if (! HAVE_epilogue) |
9878760c | 7806 | { |
9ebbca7d GK |
7807 | rtx insn = get_last_insn (); |
7808 | /* If the last insn was a BARRIER, we don't have to write anything except | |
7809 | the trace table. */ | |
7810 | if (GET_CODE (insn) == NOTE) | |
7811 | insn = prev_nonnote_insn (insn); | |
7812 | if (insn == 0 || GET_CODE (insn) != BARRIER) | |
4697a36c | 7813 | { |
9ebbca7d GK |
7814 | /* This is slightly ugly, but at least we don't have two |
7815 | copies of the epilogue-emitting code. */ | |
7816 | start_sequence (); | |
7817 | ||
7818 | /* A NOTE_INSN_DELETED is supposed to be at the start | |
7819 | and end of the "toplevel" insn chain. */ | |
7820 | emit_note (0, NOTE_INSN_DELETED); | |
7821 | rs6000_emit_epilogue (FALSE); | |
7822 | emit_note (0, NOTE_INSN_DELETED); | |
7823 | ||
7824 | if (TARGET_DEBUG_STACK) | |
a4f6c312 SS |
7825 | debug_rtx_list (get_insns (), 100); |
7826 | final (get_insns (), file, FALSE, FALSE); | |
9ebbca7d | 7827 | end_sequence (); |
4697a36c | 7828 | } |
9878760c | 7829 | } |
b4ac57ab | 7830 | |
9b30bae2 | 7831 | /* Output a traceback table here. See /usr/include/sys/debug.h for info |
314fc5a9 ILT |
7832 | on its format. |
7833 | ||
7834 | We don't output a traceback table if -finhibit-size-directive was | |
7835 | used. The documentation for -finhibit-size-directive reads | |
7836 | ``don't output a @code{.size} assembler directive, or anything | |
7837 | else that would cause trouble if the function is split in the | |
7838 | middle, and the two halves are placed at locations far apart in | |
7839 | memory.'' The traceback table has this property, since it | |
7840 | includes the offset from the start of the function to the | |
4d30c363 MM |
7841 | traceback table itself. |
7842 | ||
7843 | System V.4 Powerpc's (and the embedded ABI derived from it) use a | |
b6c9286a MM |
7844 | different traceback table. */ |
7845 | if (DEFAULT_ABI == ABI_AIX && ! flag_inhibit_size_directive) | |
9b30bae2 | 7846 | { |
3cce094d | 7847 | const char *fname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0); |
3ac88239 | 7848 | const char *language_string = lang_hooks.name; |
314fc5a9 ILT |
7849 | int fixed_parms, float_parms, parm_info; |
7850 | int i; | |
7851 | ||
b6c9286a MM |
7852 | while (*fname == '.') /* V.4 encodes . in the name */ |
7853 | fname++; | |
7854 | ||
314fc5a9 ILT |
7855 | /* Need label immediately before tbtab, so we can compute its offset |
7856 | from the function start. */ | |
7857 | if (*fname == '*') | |
7858 | ++fname; | |
7859 | ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT"); | |
7860 | ASM_OUTPUT_LABEL (file, fname); | |
7861 | ||
7862 | /* The .tbtab pseudo-op can only be used for the first eight | |
7863 | expressions, since it can't handle the possibly variable | |
7864 | length fields that follow. However, if you omit the optional | |
7865 | fields, the assembler outputs zeros for all optional fields | |
7866 | anyways, giving each variable length field is minimum length | |
7867 | (as defined in sys/debug.h). Thus we can not use the .tbtab | |
7868 | pseudo-op at all. */ | |
7869 | ||
7870 | /* An all-zero word flags the start of the tbtab, for debuggers | |
7871 | that have to find it by searching forward from the entry | |
7872 | point or from the current pc. */ | |
19d2d16f | 7873 | fputs ("\t.long 0\n", file); |
314fc5a9 ILT |
7874 | |
7875 | /* Tbtab format type. Use format type 0. */ | |
19d2d16f | 7876 | fputs ("\t.byte 0,", file); |
314fc5a9 ILT |
7877 | |
7878 | /* Language type. Unfortunately, there doesn't seem to be any | |
7879 | official way to get this info, so we use language_string. C | |
7880 | is 0. C++ is 9. No number defined for Obj-C, so use the | |
9517ead8 | 7881 | value for C for now. There is no official value for Java, |
6f573ff9 | 7882 | although IBM appears to be using 13. There is no official value |
f710504c | 7883 | for Chill, so we've chosen 44 pseudo-randomly. */ |
314fc5a9 | 7884 | if (! strcmp (language_string, "GNU C") |
e2c953b6 | 7885 | || ! strcmp (language_string, "GNU Objective-C")) |
314fc5a9 ILT |
7886 | i = 0; |
7887 | else if (! strcmp (language_string, "GNU F77")) | |
7888 | i = 1; | |
7889 | else if (! strcmp (language_string, "GNU Ada")) | |
7890 | i = 3; | |
8b83775b | 7891 | else if (! strcmp (language_string, "GNU Pascal")) |
314fc5a9 ILT |
7892 | i = 2; |
7893 | else if (! strcmp (language_string, "GNU C++")) | |
7894 | i = 9; | |
9517ead8 AG |
7895 | else if (! strcmp (language_string, "GNU Java")) |
7896 | i = 13; | |
6f573ff9 JL |
7897 | else if (! strcmp (language_string, "GNU CHILL")) |
7898 | i = 44; | |
314fc5a9 ILT |
7899 | else |
7900 | abort (); | |
7901 | fprintf (file, "%d,", i); | |
7902 | ||
7903 | /* 8 single bit fields: global linkage (not set for C extern linkage, | |
7904 | apparently a PL/I convention?), out-of-line epilogue/prologue, offset | |
7905 | from start of procedure stored in tbtab, internal function, function | |
7906 | has controlled storage, function has no toc, function uses fp, | |
7907 | function logs/aborts fp operations. */ | |
7908 | /* Assume that fp operations are used if any fp reg must be saved. */ | |
4697a36c | 7909 | fprintf (file, "%d,", (1 << 5) | ((info->first_fp_reg_save != 64) << 1)); |
314fc5a9 ILT |
7910 | |
7911 | /* 6 bitfields: function is interrupt handler, name present in | |
7912 | proc table, function calls alloca, on condition directives | |
7913 | (controls stack walks, 3 bits), saves condition reg, saves | |
7914 | link reg. */ | |
7915 | /* The `function calls alloca' bit seems to be set whenever reg 31 is | |
7916 | set up as a frame pointer, even when there is no alloca call. */ | |
7917 | fprintf (file, "%d,", | |
7918 | ((1 << 6) | (frame_pointer_needed << 5) | |
4697a36c | 7919 | | (info->cr_save_p << 1) | (info->lr_save_p))); |
314fc5a9 ILT |
7920 | |
7921 | /* 3 bitfields: saves backchain, spare bit, number of fpr saved | |
7922 | (6 bits). */ | |
7923 | fprintf (file, "%d,", | |
4697a36c | 7924 | (info->push_p << 7) | (64 - info->first_fp_reg_save)); |
314fc5a9 ILT |
7925 | |
7926 | /* 2 bitfields: spare bits (2 bits), number of gpr saved (6 bits). */ | |
7927 | fprintf (file, "%d,", (32 - first_reg_to_save ())); | |
7928 | ||
7929 | { | |
7930 | /* Compute the parameter info from the function decl argument | |
7931 | list. */ | |
7932 | tree decl; | |
7933 | int next_parm_info_bit; | |
7934 | ||
7935 | next_parm_info_bit = 31; | |
7936 | parm_info = 0; | |
7937 | fixed_parms = 0; | |
7938 | float_parms = 0; | |
7939 | ||
7940 | for (decl = DECL_ARGUMENTS (current_function_decl); | |
7941 | decl; decl = TREE_CHAIN (decl)) | |
7942 | { | |
7943 | rtx parameter = DECL_INCOMING_RTL (decl); | |
7944 | enum machine_mode mode = GET_MODE (parameter); | |
7945 | ||
7946 | if (GET_CODE (parameter) == REG) | |
7947 | { | |
7948 | if (GET_MODE_CLASS (mode) == MODE_FLOAT) | |
7949 | { | |
7950 | int bits; | |
7951 | ||
7952 | float_parms++; | |
7953 | ||
7954 | if (mode == SFmode) | |
7955 | bits = 0x2; | |
7956 | else if (mode == DFmode) | |
7957 | bits = 0x3; | |
7958 | else | |
7959 | abort (); | |
7960 | ||
7961 | /* If only one bit will fit, don't or in this entry. */ | |
7962 | if (next_parm_info_bit > 0) | |
7963 | parm_info |= (bits << (next_parm_info_bit - 1)); | |
7964 | next_parm_info_bit -= 2; | |
7965 | } | |
7966 | else | |
7967 | { | |
7968 | fixed_parms += ((GET_MODE_SIZE (mode) | |
7969 | + (UNITS_PER_WORD - 1)) | |
7970 | / UNITS_PER_WORD); | |
7971 | next_parm_info_bit -= 1; | |
7972 | } | |
7973 | } | |
7974 | } | |
7975 | } | |
7976 | ||
7977 | /* Number of fixed point parameters. */ | |
7978 | /* This is actually the number of words of fixed point parameters; thus | |
7979 | an 8 byte struct counts as 2; and thus the maximum value is 8. */ | |
7980 | fprintf (file, "%d,", fixed_parms); | |
7981 | ||
7982 | /* 2 bitfields: number of floating point parameters (7 bits), parameters | |
7983 | all on stack. */ | |
7984 | /* This is actually the number of fp registers that hold parameters; | |
7985 | and thus the maximum value is 13. */ | |
7986 | /* Set parameters on stack bit if parameters are not in their original | |
7987 | registers, regardless of whether they are on the stack? Xlc | |
7988 | seems to set the bit when not optimizing. */ | |
7989 | fprintf (file, "%d\n", ((float_parms << 1) | (! optimize))); | |
7990 | ||
7991 | /* Optional fields follow. Some are variable length. */ | |
7992 | ||
7993 | /* Parameter types, left adjusted bit fields: 0 fixed, 10 single float, | |
7994 | 11 double float. */ | |
7995 | /* There is an entry for each parameter in a register, in the order that | |
7996 | they occur in the parameter list. Any intervening arguments on the | |
7997 | stack are ignored. If the list overflows a long (max possible length | |
7998 | 34 bits) then completely leave off all elements that don't fit. */ | |
7999 | /* Only emit this long if there was at least one parameter. */ | |
8000 | if (fixed_parms || float_parms) | |
8001 | fprintf (file, "\t.long %d\n", parm_info); | |
8002 | ||
8003 | /* Offset from start of code to tb table. */ | |
19d2d16f | 8004 | fputs ("\t.long ", file); |
314fc5a9 | 8005 | ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT"); |
54ee9799 DE |
8006 | #if TARGET_AIX |
8007 | RS6000_OUTPUT_BASENAME (file, fname); | |
8008 | #else | |
9ebbca7d | 8009 | assemble_name (file, fname); |
54ee9799 | 8010 | #endif |
19d2d16f | 8011 | fputs ("-.", file); |
54ee9799 DE |
8012 | #if TARGET_AIX |
8013 | RS6000_OUTPUT_BASENAME (file, fname); | |
8014 | #else | |
9ebbca7d | 8015 | assemble_name (file, fname); |
54ee9799 | 8016 | #endif |
19d2d16f | 8017 | putc ('\n', file); |
314fc5a9 ILT |
8018 | |
8019 | /* Interrupt handler mask. */ | |
8020 | /* Omit this long, since we never set the interrupt handler bit | |
8021 | above. */ | |
8022 | ||
8023 | /* Number of CTL (controlled storage) anchors. */ | |
8024 | /* Omit this long, since the has_ctl bit is never set above. */ | |
8025 | ||
8026 | /* Displacement into stack of each CTL anchor. */ | |
8027 | /* Omit this list of longs, because there are no CTL anchors. */ | |
8028 | ||
8029 | /* Length of function name. */ | |
296b8152 | 8030 | fprintf (file, "\t.short %d\n", (int) strlen (fname)); |
314fc5a9 ILT |
8031 | |
8032 | /* Function name. */ | |
8033 | assemble_string (fname, strlen (fname)); | |
8034 | ||
8035 | /* Register for alloca automatic storage; this is always reg 31. | |
8036 | Only emit this if the alloca bit was set above. */ | |
8037 | if (frame_pointer_needed) | |
19d2d16f | 8038 | fputs ("\t.byte 31\n", file); |
9b30bae2 | 8039 | } |
9878760c | 8040 | } |
17167fd8 | 8041 | \f |
a4f6c312 SS |
8042 | /* A C compound statement that outputs the assembler code for a thunk |
8043 | function, used to implement C++ virtual function calls with | |
8044 | multiple inheritance. The thunk acts as a wrapper around a virtual | |
8045 | function, adjusting the implicit object parameter before handing | |
8046 | control off to the real function. | |
8047 | ||
8048 | First, emit code to add the integer DELTA to the location that | |
8049 | contains the incoming first argument. Assume that this argument | |
8050 | contains a pointer, and is the one used to pass the `this' pointer | |
8051 | in C++. This is the incoming argument *before* the function | |
8052 | prologue, e.g. `%o0' on a sparc. The addition must preserve the | |
8053 | values of all other incoming arguments. | |
17167fd8 MM |
8054 | |
8055 | After the addition, emit code to jump to FUNCTION, which is a | |
a4f6c312 SS |
8056 | `FUNCTION_DECL'. This is a direct pure jump, not a call, and does |
8057 | not touch the return address. Hence returning from FUNCTION will | |
8058 | return to whoever called the current `thunk'. | |
17167fd8 | 8059 | |
a4f6c312 SS |
8060 | The effect must be as if FUNCTION had been called directly with the |
8061 | adjusted first argument. This macro is responsible for emitting | |
8062 | all of the code for a thunk function; output_function_prologue() | |
8063 | and output_function_epilogue() are not invoked. | |
17167fd8 | 8064 | |
a4f6c312 SS |
8065 | The THUNK_FNDECL is redundant. (DELTA and FUNCTION have already |
8066 | been extracted from it.) It might possibly be useful on some | |
8067 | targets, but probably not. | |
17167fd8 | 8068 | |
a4f6c312 SS |
8069 | If you do not define this macro, the target-independent code in the |
8070 | C++ frontend will generate a less efficient heavyweight thunk that | |
8071 | calls FUNCTION instead of jumping to it. The generic approach does | |
8072 | not support varargs. */ | |
17167fd8 MM |
8073 | |
8074 | void | |
8075 | output_mi_thunk (file, thunk_fndecl, delta, function) | |
8076 | FILE *file; | |
d330fd93 | 8077 | tree thunk_fndecl ATTRIBUTE_UNUSED; |
17167fd8 MM |
8078 | int delta; |
8079 | tree function; | |
8080 | { | |
a4f6c312 SS |
8081 | const char *this_reg = |
8082 | reg_names[ aggregate_value_p (TREE_TYPE (TREE_TYPE (function))) ? 4 : 3 ]; | |
d330fd93 | 8083 | const char *prefix; |
3cce094d | 8084 | const char *fname; |
d330fd93 | 8085 | const char *r0 = reg_names[0]; |
d330fd93 KG |
8086 | const char *toc = reg_names[2]; |
8087 | const char *schain = reg_names[11]; | |
8088 | const char *r12 = reg_names[12]; | |
17167fd8 MM |
8089 | char buf[512]; |
8090 | static int labelno = 0; | |
8091 | ||
a4f6c312 | 8092 | /* Small constants that can be done by one add instruction. */ |
17167fd8 MM |
8093 | if (delta >= -32768 && delta <= 32767) |
8094 | { | |
22b4a3b0 | 8095 | if (! TARGET_NEW_MNEMONICS) |
17167fd8 MM |
8096 | fprintf (file, "\tcal %s,%d(%s)\n", this_reg, delta, this_reg); |
8097 | else | |
8098 | fprintf (file, "\taddi %s,%s,%d\n", this_reg, this_reg, delta); | |
8099 | } | |
8100 | ||
a4f6c312 | 8101 | /* Large constants that can be done by one addis instruction. */ |
17167fd8 MM |
8102 | else if ((delta & 0xffff) == 0 && num_insns_constant_wide (delta) == 1) |
8103 | asm_fprintf (file, "\t{cau|addis} %s,%s,%d\n", this_reg, this_reg, | |
8104 | delta >> 16); | |
8105 | ||
8106 | /* 32-bit constants that can be done by an add and addis instruction. */ | |
8107 | else if (TARGET_32BIT || num_insns_constant_wide (delta) == 1) | |
8108 | { | |
a4f6c312 SS |
8109 | /* Break into two pieces, propagating the sign bit from the low |
8110 | word to the upper word. */ | |
17167fd8 MM |
8111 | int delta_high = delta >> 16; |
8112 | int delta_low = delta & 0xffff; | |
8113 | if ((delta_low & 0x8000) != 0) | |
8114 | { | |
8115 | delta_high++; | |
8116 | delta_low = (delta_low ^ 0x8000) - 0x8000; /* sign extend */ | |
8117 | } | |
8118 | ||
8119 | asm_fprintf (file, "\t{cau|addis} %s,%s,%d\n", this_reg, this_reg, | |
8120 | delta_high); | |
8121 | ||
22b4a3b0 | 8122 | if (! TARGET_NEW_MNEMONICS) |
17167fd8 MM |
8123 | fprintf (file, "\tcal %s,%d(%s)\n", this_reg, delta_low, this_reg); |
8124 | else | |
8125 | fprintf (file, "\taddi %s,%s,%d\n", this_reg, this_reg, delta_low); | |
8126 | } | |
8127 | ||
8128 | /* 64-bit constants, fixme */ | |
8129 | else | |
8130 | abort (); | |
8131 | ||
8132 | /* Get the prefix in front of the names. */ | |
8133 | switch (DEFAULT_ABI) | |
8134 | { | |
8135 | default: | |
8136 | abort (); | |
8137 | ||
8138 | case ABI_AIX: | |
8139 | prefix = "."; | |
8140 | break; | |
8141 | ||
8142 | case ABI_V4: | |
8143 | case ABI_AIX_NODESC: | |
17167fd8 MM |
8144 | prefix = ""; |
8145 | break; | |
17167fd8 MM |
8146 | } |
8147 | ||
8148 | /* If the function is compiled in this module, jump to it directly. | |
8149 | Otherwise, load up its address and jump to it. */ | |
8150 | ||
8151 | fname = XSTR (XEXP (DECL_RTL (function), 0), 0); | |
42820a49 | 8152 | |
9ebbca7d | 8153 | if (current_file_function_operand (XEXP (DECL_RTL (function), 0), VOIDmode) |
22b4a3b0 FS |
8154 | && ! lookup_attribute ("longcall", |
8155 | TYPE_ATTRIBUTES (TREE_TYPE (function)))) | |
17167fd8 MM |
8156 | { |
8157 | fprintf (file, "\tb %s", prefix); | |
8158 | assemble_name (file, fname); | |
22b4a3b0 | 8159 | if (DEFAULT_ABI == ABI_V4 && flag_pic) fputs ("@local", file); |
949ea356 | 8160 | putc ('\n', file); |
17167fd8 MM |
8161 | } |
8162 | ||
8163 | else | |
8164 | { | |
8165 | switch (DEFAULT_ABI) | |
8166 | { | |
8167 | default: | |
17167fd8 MM |
8168 | abort (); |
8169 | ||
8170 | case ABI_AIX: | |
8171 | /* Set up a TOC entry for the function. */ | |
8172 | ASM_GENERATE_INTERNAL_LABEL (buf, "Lthunk", labelno); | |
8173 | toc_section (); | |
8174 | ASM_OUTPUT_INTERNAL_LABEL (file, "Lthunk", labelno); | |
8175 | labelno++; | |
8176 | ||
a4f6c312 SS |
8177 | /* Note, MINIMAL_TOC doesn't make sense in the case of a |
8178 | thunk, since there will be only one TOC entry for this | |
8179 | function. */ | |
17167fd8 MM |
8180 | fputs ("\t.tc\t", file); |
8181 | assemble_name (file, buf); | |
8182 | fputs ("[TC],", file); | |
8183 | assemble_name (file, buf); | |
8184 | putc ('\n', file); | |
8185 | text_section (); | |
d2574c50 | 8186 | asm_fprintf (file, (TARGET_32BIT) ? "\t{l|lwz} %s," : "\tld %s,", r12); |
17167fd8 MM |
8187 | assemble_name (file, buf); |
8188 | asm_fprintf (file, "(%s)\n", reg_names[2]); | |
8189 | asm_fprintf (file, | |
8190 | (TARGET_32BIT) ? "\t{l|lwz} %s,0(%s)\n" : "\tld %s,0(%s)\n", | |
8191 | r0, r12); | |
8192 | ||
8193 | asm_fprintf (file, | |
8194 | (TARGET_32BIT) ? "\t{l|lwz} %s,4(%s)\n" : "\tld %s,8(%s)\n", | |
8195 | toc, r12); | |
8196 | ||
8197 | asm_fprintf (file, "\tmtctr %s\n", r0); | |
8198 | asm_fprintf (file, | |
8199 | (TARGET_32BIT) ? "\t{l|lwz} %s,8(%s)\n" : "\tld %s,16(%s)\n", | |
8200 | schain, r12); | |
8201 | ||
8202 | asm_fprintf (file, "\tbctr\n"); | |
8203 | break; | |
8204 | ||
9ebbca7d | 8205 | case ABI_AIX_NODESC: |
17167fd8 | 8206 | case ABI_V4: |
22b4a3b0 FS |
8207 | fprintf (file, "\tb %s", prefix); |
8208 | assemble_name (file, fname); | |
8209 | if (flag_pic) fputs ("@plt", file); | |
949ea356 | 8210 | putc ('\n', file); |
22b4a3b0 | 8211 | break; |
ee890fe2 SS |
8212 | |
8213 | #if TARGET_MACHO | |
8214 | case ABI_DARWIN: | |
8215 | fprintf (file, "\tb %s", prefix); | |
8216 | if (flag_pic && !machopic_name_defined_p (fname)) | |
8217 | assemble_name (file, machopic_stub_name (fname)); | |
8218 | else | |
8219 | assemble_name (file, fname); | |
8220 | putc ('\n', file); | |
8221 | break; | |
8222 | #endif | |
9ebbca7d GK |
8223 | } |
8224 | } | |
8225 | } | |
42820a49 | 8226 | |
9ebbca7d GK |
8227 | \f |
8228 | /* A quick summary of the various types of 'constant-pool tables' | |
8229 | under PowerPC: | |
8230 | ||
8231 | Target Flags Name One table per | |
8232 | AIX (none) AIX TOC object file | |
8233 | AIX -mfull-toc AIX TOC object file | |
8234 | AIX -mminimal-toc AIX minimal TOC translation unit | |
8235 | SVR4/EABI (none) SVR4 SDATA object file | |
8236 | SVR4/EABI -fpic SVR4 pic object file | |
8237 | SVR4/EABI -fPIC SVR4 PIC translation unit | |
8238 | SVR4/EABI -mrelocatable EABI TOC function | |
8239 | SVR4/EABI -maix AIX TOC object file | |
8240 | SVR4/EABI -maix -mminimal-toc | |
8241 | AIX minimal TOC translation unit | |
8242 | ||
8243 | Name Reg. Set by entries contains: | |
8244 | made by addrs? fp? sum? | |
8245 | ||
8246 | AIX TOC 2 crt0 as Y option option | |
8247 | AIX minimal TOC 30 prolog gcc Y Y option | |
8248 | SVR4 SDATA 13 crt0 gcc N Y N | |
8249 | SVR4 pic 30 prolog ld Y not yet N | |
8250 | SVR4 PIC 30 prolog gcc Y option option | |
8251 | EABI TOC 30 prolog gcc Y option option | |
8252 | ||
8253 | */ | |
8254 | ||
8255 | /* Hash table stuff for keeping track of TOC entries. */ | |
8256 | ||
8257 | struct toc_hash_struct | |
8258 | { | |
8259 | /* `key' will satisfy CONSTANT_P; in fact, it will satisfy | |
8260 | ASM_OUTPUT_SPECIAL_POOL_ENTRY_P. */ | |
8261 | rtx key; | |
a9098fd0 | 8262 | enum machine_mode key_mode; |
9ebbca7d GK |
8263 | int labelno; |
8264 | }; | |
17167fd8 | 8265 | |
9ebbca7d GK |
8266 | static htab_t toc_hash_table; |
8267 | ||
8268 | /* Hash functions for the hash table. */ | |
8269 | ||
8270 | static unsigned | |
8271 | rs6000_hash_constant (k) | |
8272 | rtx k; | |
8273 | { | |
a9098fd0 | 8274 | unsigned result = (GET_CODE (k) << 3) ^ GET_MODE (k); |
9ebbca7d GK |
8275 | const char *format = GET_RTX_FORMAT (GET_CODE (k)); |
8276 | int flen = strlen (format); | |
8277 | int fidx; | |
8278 | ||
8279 | if (GET_CODE (k) == LABEL_REF) | |
832ea3b3 | 8280 | return result * 1231 + X0INT (XEXP (k, 0), 3); |
9ebbca7d GK |
8281 | |
8282 | if (GET_CODE (k) == CONST_DOUBLE) | |
592bf28c | 8283 | fidx = 1; |
9ebbca7d GK |
8284 | else if (GET_CODE (k) == CODE_LABEL) |
8285 | fidx = 3; | |
8286 | else | |
8287 | fidx = 0; | |
8288 | ||
8289 | for (; fidx < flen; fidx++) | |
8290 | switch (format[fidx]) | |
8291 | { | |
8292 | case 's': | |
8293 | { | |
8294 | unsigned i, len; | |
8295 | const char *str = XSTR (k, fidx); | |
8296 | len = strlen (str); | |
8297 | result = result * 613 + len; | |
8298 | for (i = 0; i < len; i++) | |
8299 | result = result * 613 + (unsigned) str[i]; | |
17167fd8 MM |
8300 | break; |
8301 | } | |
9ebbca7d GK |
8302 | case 'u': |
8303 | case 'e': | |
8304 | result = result * 1231 + rs6000_hash_constant (XEXP (k, fidx)); | |
8305 | break; | |
8306 | case 'i': | |
8307 | case 'n': | |
8308 | result = result * 613 + (unsigned) XINT (k, fidx); | |
8309 | break; | |
8310 | case 'w': | |
8311 | if (sizeof (unsigned) >= sizeof (HOST_WIDE_INT)) | |
8312 | result = result * 613 + (unsigned) XWINT (k, fidx); | |
8313 | else | |
8314 | { | |
8315 | size_t i; | |
8316 | for (i = 0; i < sizeof(HOST_WIDE_INT)/sizeof(unsigned); i++) | |
8317 | result = result * 613 + (unsigned) (XWINT (k, fidx) | |
8318 | >> CHAR_BIT * i); | |
8319 | } | |
8320 | break; | |
8321 | default: | |
a4f6c312 | 8322 | abort (); |
9ebbca7d GK |
8323 | } |
8324 | return result; | |
8325 | } | |
8326 | ||
8327 | static unsigned | |
8328 | toc_hash_function (hash_entry) | |
8329 | const void * hash_entry; | |
8330 | { | |
a9098fd0 GK |
8331 | const struct toc_hash_struct *thc = |
8332 | (const struct toc_hash_struct *) hash_entry; | |
8333 | return rs6000_hash_constant (thc->key) ^ thc->key_mode; | |
9ebbca7d GK |
8334 | } |
8335 | ||
8336 | /* Compare H1 and H2 for equivalence. */ | |
8337 | ||
8338 | static int | |
8339 | toc_hash_eq (h1, h2) | |
8340 | const void * h1; | |
8341 | const void * h2; | |
8342 | { | |
8343 | rtx r1 = ((const struct toc_hash_struct *) h1)->key; | |
8344 | rtx r2 = ((const struct toc_hash_struct *) h2)->key; | |
8345 | ||
a9098fd0 GK |
8346 | if (((const struct toc_hash_struct *) h1)->key_mode |
8347 | != ((const struct toc_hash_struct *) h2)->key_mode) | |
8348 | return 0; | |
8349 | ||
9ebbca7d GK |
8350 | /* Gotcha: One of these const_doubles will be in memory. |
8351 | The other may be on the constant-pool chain. | |
a4f6c312 | 8352 | So rtx_equal_p will think they are different... */ |
9ebbca7d GK |
8353 | if (r1 == r2) |
8354 | return 1; | |
8355 | if (GET_CODE (r1) != GET_CODE (r2) | |
8356 | || GET_MODE (r1) != GET_MODE (r2)) | |
8357 | return 0; | |
8358 | if (GET_CODE (r1) == CONST_DOUBLE) | |
8359 | { | |
8360 | int format_len = strlen (GET_RTX_FORMAT (CONST_DOUBLE)); | |
8361 | int i; | |
592bf28c | 8362 | for (i = 1; i < format_len; i++) |
9ebbca7d GK |
8363 | if (XWINT (r1, i) != XWINT (r2, i)) |
8364 | return 0; | |
8365 | ||
8366 | return 1; | |
17167fd8 | 8367 | } |
9ebbca7d | 8368 | else if (GET_CODE (r1) == LABEL_REF) |
e4a0656f GK |
8369 | return (CODE_LABEL_NUMBER (XEXP (r1, 0)) |
8370 | == CODE_LABEL_NUMBER (XEXP (r2, 0))); | |
9ebbca7d GK |
8371 | else |
8372 | return rtx_equal_p (r1, r2); | |
8373 | } | |
8374 | ||
8375 | /* Mark the hash table-entry HASH_ENTRY. */ | |
8376 | ||
8377 | static int | |
8378 | toc_hash_mark_entry (hash_slot, unused) | |
2eba1afa | 8379 | void ** hash_slot; |
9ebbca7d GK |
8380 | void * unused ATTRIBUTE_UNUSED; |
8381 | { | |
8382 | const struct toc_hash_struct * hash_entry = | |
8383 | *(const struct toc_hash_struct **) hash_slot; | |
8384 | rtx r = hash_entry->key; | |
8385 | ggc_set_mark (hash_entry); | |
a4f6c312 | 8386 | /* For CODE_LABELS, we don't want to drag in the whole insn chain... */ |
9ebbca7d GK |
8387 | if (GET_CODE (r) == LABEL_REF) |
8388 | { | |
8389 | ggc_set_mark (r); | |
8390 | ggc_set_mark (XEXP (r, 0)); | |
8391 | } | |
8392 | else | |
8393 | ggc_mark_rtx (r); | |
8394 | return 1; | |
8395 | } | |
8396 | ||
8397 | /* Mark all the elements of the TOC hash-table *HT. */ | |
8398 | ||
8399 | static void | |
8400 | toc_hash_mark_table (vht) | |
8401 | void *vht; | |
8402 | { | |
8403 | htab_t *ht = vht; | |
8404 | ||
8405 | htab_traverse (*ht, toc_hash_mark_entry, (void *)0); | |
17167fd8 MM |
8406 | } |
8407 | ||
28e510bd MM |
8408 | /* These are the names given by the C++ front-end to vtables, and |
8409 | vtable-like objects. Ideally, this logic should not be here; | |
8410 | instead, there should be some programmatic way of inquiring as | |
8411 | to whether or not an object is a vtable. */ | |
8412 | ||
8413 | #define VTABLE_NAME_P(NAME) \ | |
8414 | (strncmp ("_vt.", name, strlen("_vt.")) == 0 \ | |
8415 | || strncmp ("_ZTV", name, strlen ("_ZTV")) == 0 \ | |
8416 | || strncmp ("_ZTT", name, strlen ("_ZTT")) == 0 \ | |
8417 | || strncmp ("_ZTC", name, strlen ("_ZTC")) == 0) | |
8418 | ||
8419 | void | |
8420 | rs6000_output_symbol_ref (file, x) | |
8421 | FILE *file; | |
8422 | rtx x; | |
8423 | { | |
8424 | /* Currently C++ toc references to vtables can be emitted before it | |
8425 | is decided whether the vtable is public or private. If this is | |
8426 | the case, then the linker will eventually complain that there is | |
8427 | a reference to an unknown section. Thus, for vtables only, | |
8428 | we emit the TOC reference to reference the symbol and not the | |
8429 | section. */ | |
8430 | const char *name = XSTR (x, 0); | |
54ee9799 DE |
8431 | |
8432 | if (VTABLE_NAME_P (name)) | |
8433 | { | |
8434 | RS6000_OUTPUT_BASENAME (file, name); | |
8435 | } | |
8436 | else | |
8437 | assemble_name (file, name); | |
28e510bd MM |
8438 | } |
8439 | ||
a4f6c312 SS |
8440 | /* Output a TOC entry. We derive the entry name from what is being |
8441 | written. */ | |
9878760c RK |
8442 | |
8443 | void | |
a9098fd0 | 8444 | output_toc (file, x, labelno, mode) |
9878760c RK |
8445 | FILE *file; |
8446 | rtx x; | |
8447 | int labelno; | |
a9098fd0 | 8448 | enum machine_mode mode; |
9878760c RK |
8449 | { |
8450 | char buf[256]; | |
3cce094d | 8451 | const char *name = buf; |
ec940faa | 8452 | const char *real_name; |
9878760c RK |
8453 | rtx base = x; |
8454 | int offset = 0; | |
8455 | ||
4697a36c MM |
8456 | if (TARGET_NO_TOC) |
8457 | abort (); | |
8458 | ||
9ebbca7d GK |
8459 | /* When the linker won't eliminate them, don't output duplicate |
8460 | TOC entries (this happens on AIX if there is any kind of TOC, | |
1f8f4a0b MM |
8461 | and on SVR4 under -fPIC or -mrelocatable). */ |
8462 | if (TARGET_TOC) | |
9ebbca7d GK |
8463 | { |
8464 | struct toc_hash_struct *h; | |
8465 | void * * found; | |
8466 | ||
8467 | h = ggc_alloc (sizeof (*h)); | |
8468 | h->key = x; | |
a9098fd0 | 8469 | h->key_mode = mode; |
9ebbca7d GK |
8470 | h->labelno = labelno; |
8471 | ||
8472 | found = htab_find_slot (toc_hash_table, h, 1); | |
8473 | if (*found == NULL) | |
8474 | *found = h; | |
8475 | else /* This is indeed a duplicate. | |
8476 | Set this label equal to that label. */ | |
8477 | { | |
8478 | fputs ("\t.set ", file); | |
8479 | ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC"); | |
8480 | fprintf (file, "%d,", labelno); | |
8481 | ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC"); | |
8482 | fprintf (file, "%d\n", ((*(const struct toc_hash_struct **) | |
8483 | found)->labelno)); | |
8484 | return; | |
8485 | } | |
8486 | } | |
8487 | ||
8488 | /* If we're going to put a double constant in the TOC, make sure it's | |
8489 | aligned properly when strict alignment is on. */ | |
ff1720ed RK |
8490 | if (GET_CODE (x) == CONST_DOUBLE |
8491 | && STRICT_ALIGNMENT | |
a9098fd0 | 8492 | && GET_MODE_BITSIZE (mode) >= 64 |
ff1720ed RK |
8493 | && ! (TARGET_NO_FP_IN_TOC && ! TARGET_MINIMAL_TOC)) { |
8494 | ASM_OUTPUT_ALIGN (file, 3); | |
8495 | } | |
8496 | ||
9ebbca7d | 8497 | ASM_OUTPUT_INTERNAL_LABEL (file, "LC", labelno); |
9878760c | 8498 | |
37c37a57 RK |
8499 | /* Handle FP constants specially. Note that if we have a minimal |
8500 | TOC, things we put here aren't actually in the TOC, so we can allow | |
8501 | FP constants. */ | |
a9098fd0 | 8502 | if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == DFmode) |
9878760c | 8503 | { |
042259f2 DE |
8504 | REAL_VALUE_TYPE rv; |
8505 | long k[2]; | |
0adc764e | 8506 | |
042259f2 DE |
8507 | REAL_VALUE_FROM_CONST_DOUBLE (rv, x); |
8508 | REAL_VALUE_TO_TARGET_DOUBLE (rv, k); | |
31bfaa0b | 8509 | |
13ded975 DE |
8510 | if (TARGET_64BIT) |
8511 | { | |
8512 | if (TARGET_MINIMAL_TOC) | |
2bfcf297 | 8513 | fputs (DOUBLE_INT_ASM_OP, file); |
13ded975 | 8514 | else |
2bfcf297 DB |
8515 | fprintf (file, "\t.tc FD_%lx_%lx[TC],", k[0], k[1]); |
8516 | fprintf (file, "0x%lx%08lx\n", k[0], k[1]); | |
13ded975 DE |
8517 | return; |
8518 | } | |
1875cc88 | 8519 | else |
13ded975 DE |
8520 | { |
8521 | if (TARGET_MINIMAL_TOC) | |
2bfcf297 | 8522 | fputs ("\t.long ", file); |
13ded975 | 8523 | else |
2bfcf297 DB |
8524 | fprintf (file, "\t.tc FD_%lx_%lx[TC],", k[0], k[1]); |
8525 | fprintf (file, "0x%lx,0x%lx\n", k[0], k[1]); | |
13ded975 DE |
8526 | return; |
8527 | } | |
9878760c | 8528 | } |
a9098fd0 | 8529 | else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == SFmode) |
9878760c | 8530 | { |
042259f2 DE |
8531 | REAL_VALUE_TYPE rv; |
8532 | long l; | |
9878760c | 8533 | |
042259f2 DE |
8534 | REAL_VALUE_FROM_CONST_DOUBLE (rv, x); |
8535 | REAL_VALUE_TO_TARGET_SINGLE (rv, l); | |
8536 | ||
31bfaa0b DE |
8537 | if (TARGET_64BIT) |
8538 | { | |
8539 | if (TARGET_MINIMAL_TOC) | |
2bfcf297 | 8540 | fputs (DOUBLE_INT_ASM_OP, file); |
31bfaa0b | 8541 | else |
2bfcf297 DB |
8542 | fprintf (file, "\t.tc FS_%lx[TC],", l); |
8543 | fprintf (file, "0x%lx00000000\n", l); | |
31bfaa0b DE |
8544 | return; |
8545 | } | |
042259f2 | 8546 | else |
31bfaa0b DE |
8547 | { |
8548 | if (TARGET_MINIMAL_TOC) | |
2bfcf297 | 8549 | fputs ("\t.long ", file); |
31bfaa0b | 8550 | else |
2bfcf297 DB |
8551 | fprintf (file, "\t.tc FS_%lx[TC],", l); |
8552 | fprintf (file, "0x%lx\n", l); | |
31bfaa0b DE |
8553 | return; |
8554 | } | |
042259f2 | 8555 | } |
f176e826 | 8556 | else if (GET_MODE (x) == VOIDmode |
a9098fd0 | 8557 | && (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE)) |
042259f2 | 8558 | { |
e2c953b6 | 8559 | unsigned HOST_WIDE_INT low; |
042259f2 DE |
8560 | HOST_WIDE_INT high; |
8561 | ||
8562 | if (GET_CODE (x) == CONST_DOUBLE) | |
8563 | { | |
8564 | low = CONST_DOUBLE_LOW (x); | |
8565 | high = CONST_DOUBLE_HIGH (x); | |
8566 | } | |
8567 | else | |
8568 | #if HOST_BITS_PER_WIDE_INT == 32 | |
8569 | { | |
8570 | low = INTVAL (x); | |
0858c623 | 8571 | high = (low & 0x80000000) ? ~0 : 0; |
042259f2 DE |
8572 | } |
8573 | #else | |
8574 | { | |
0858c623 | 8575 | low = INTVAL (x) & 0xffffffff; |
042259f2 DE |
8576 | high = (HOST_WIDE_INT) INTVAL (x) >> 32; |
8577 | } | |
8578 | #endif | |
9878760c | 8579 | |
a9098fd0 GK |
8580 | /* TOC entries are always Pmode-sized, but since this |
8581 | is a bigendian machine then if we're putting smaller | |
8582 | integer constants in the TOC we have to pad them. | |
8583 | (This is still a win over putting the constants in | |
8584 | a separate constant pool, because then we'd have | |
02a4ec28 FS |
8585 | to have both a TOC entry _and_ the actual constant.) |
8586 | ||
8587 | For a 32-bit target, CONST_INT values are loaded and shifted | |
8588 | entirely within `low' and can be stored in one TOC entry. */ | |
8589 | ||
8590 | if (TARGET_64BIT && POINTER_SIZE < GET_MODE_BITSIZE (mode)) | |
a9098fd0 | 8591 | abort ();/* It would be easy to make this work, but it doesn't now. */ |
02a4ec28 FS |
8592 | |
8593 | if (POINTER_SIZE > GET_MODE_BITSIZE (mode)) | |
a9098fd0 GK |
8594 | lshift_double (low, high, POINTER_SIZE - GET_MODE_BITSIZE (mode), |
8595 | POINTER_SIZE, &low, &high, 0); | |
8596 | ||
13ded975 DE |
8597 | if (TARGET_64BIT) |
8598 | { | |
8599 | if (TARGET_MINIMAL_TOC) | |
2bfcf297 | 8600 | fputs (DOUBLE_INT_ASM_OP, file); |
13ded975 | 8601 | else |
2bfcf297 DB |
8602 | fprintf (file, "\t.tc ID_%lx_%lx[TC],", (long)high, (long)low); |
8603 | fprintf (file, "0x%lx%08lx\n", (long) high, (long) low); | |
13ded975 DE |
8604 | return; |
8605 | } | |
1875cc88 | 8606 | else |
13ded975 | 8607 | { |
02a4ec28 FS |
8608 | if (POINTER_SIZE < GET_MODE_BITSIZE (mode)) |
8609 | { | |
8610 | if (TARGET_MINIMAL_TOC) | |
2bfcf297 | 8611 | fputs ("\t.long ", file); |
02a4ec28 | 8612 | else |
2bfcf297 DB |
8613 | fprintf (file, "\t.tc ID_%lx_%lx[TC],", |
8614 | (long)high, (long)low); | |
8615 | fprintf (file, "0x%lx,0x%lx\n", (long) high, (long) low); | |
02a4ec28 | 8616 | } |
13ded975 | 8617 | else |
02a4ec28 FS |
8618 | { |
8619 | if (TARGET_MINIMAL_TOC) | |
2bfcf297 | 8620 | fputs ("\t.long ", file); |
02a4ec28 | 8621 | else |
2bfcf297 DB |
8622 | fprintf (file, "\t.tc IS_%lx[TC],", (long) low); |
8623 | fprintf (file, "0x%lx\n", (long) low); | |
02a4ec28 | 8624 | } |
13ded975 DE |
8625 | return; |
8626 | } | |
9878760c RK |
8627 | } |
8628 | ||
8629 | if (GET_CODE (x) == CONST) | |
8630 | { | |
2bfcf297 DB |
8631 | if (GET_CODE (XEXP (x, 0)) != PLUS) |
8632 | abort (); | |
8633 | ||
9878760c RK |
8634 | base = XEXP (XEXP (x, 0), 0); |
8635 | offset = INTVAL (XEXP (XEXP (x, 0), 1)); | |
8636 | } | |
8637 | ||
8638 | if (GET_CODE (base) == SYMBOL_REF) | |
8639 | name = XSTR (base, 0); | |
8640 | else if (GET_CODE (base) == LABEL_REF) | |
8641 | ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (XEXP (base, 0))); | |
8642 | else if (GET_CODE (base) == CODE_LABEL) | |
8643 | ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (base)); | |
8644 | else | |
8645 | abort (); | |
8646 | ||
2e4eb9b0 | 8647 | STRIP_NAME_ENCODING (real_name, name); |
1875cc88 | 8648 | if (TARGET_MINIMAL_TOC) |
2bfcf297 | 8649 | fputs (TARGET_32BIT ? "\t.long " : DOUBLE_INT_ASM_OP, file); |
1875cc88 JW |
8650 | else |
8651 | { | |
b6c9286a | 8652 | fprintf (file, "\t.tc %s", real_name); |
9878760c | 8653 | |
1875cc88 JW |
8654 | if (offset < 0) |
8655 | fprintf (file, ".N%d", - offset); | |
8656 | else if (offset) | |
8657 | fprintf (file, ".P%d", offset); | |
9878760c | 8658 | |
19d2d16f | 8659 | fputs ("[TC],", file); |
1875cc88 | 8660 | } |
581bc4de MM |
8661 | |
8662 | /* Currently C++ toc references to vtables can be emitted before it | |
8663 | is decided whether the vtable is public or private. If this is | |
8664 | the case, then the linker will eventually complain that there is | |
8665 | a TOC reference to an unknown section. Thus, for vtables only, | |
8666 | we emit the TOC reference to reference the symbol and not the | |
8667 | section. */ | |
28e510bd | 8668 | if (VTABLE_NAME_P (name)) |
581bc4de | 8669 | { |
54ee9799 | 8670 | RS6000_OUTPUT_BASENAME (file, name); |
581bc4de MM |
8671 | if (offset < 0) |
8672 | fprintf (file, "%d", offset); | |
8673 | else if (offset > 0) | |
8674 | fprintf (file, "+%d", offset); | |
8675 | } | |
8676 | else | |
8677 | output_addr_const (file, x); | |
19d2d16f | 8678 | putc ('\n', file); |
9878760c RK |
8679 | } |
8680 | \f | |
8681 | /* Output an assembler pseudo-op to write an ASCII string of N characters | |
8682 | starting at P to FILE. | |
8683 | ||
8684 | On the RS/6000, we have to do this using the .byte operation and | |
8685 | write out special characters outside the quoted string. | |
8686 | Also, the assembler is broken; very long strings are truncated, | |
a4f6c312 | 8687 | so we must artificially break them up early. */ |
9878760c RK |
8688 | |
8689 | void | |
8690 | output_ascii (file, p, n) | |
8691 | FILE *file; | |
d330fd93 | 8692 | const char *p; |
9878760c RK |
8693 | int n; |
8694 | { | |
8695 | char c; | |
8696 | int i, count_string; | |
d330fd93 KG |
8697 | const char *for_string = "\t.byte \""; |
8698 | const char *for_decimal = "\t.byte "; | |
8699 | const char *to_close = NULL; | |
9878760c RK |
8700 | |
8701 | count_string = 0; | |
8702 | for (i = 0; i < n; i++) | |
8703 | { | |
8704 | c = *p++; | |
8705 | if (c >= ' ' && c < 0177) | |
8706 | { | |
8707 | if (for_string) | |
8708 | fputs (for_string, file); | |
8709 | putc (c, file); | |
8710 | ||
8711 | /* Write two quotes to get one. */ | |
8712 | if (c == '"') | |
8713 | { | |
8714 | putc (c, file); | |
8715 | ++count_string; | |
8716 | } | |
8717 | ||
8718 | for_string = NULL; | |
8719 | for_decimal = "\"\n\t.byte "; | |
8720 | to_close = "\"\n"; | |
8721 | ++count_string; | |
8722 | ||
8723 | if (count_string >= 512) | |
8724 | { | |
8725 | fputs (to_close, file); | |
8726 | ||
8727 | for_string = "\t.byte \""; | |
8728 | for_decimal = "\t.byte "; | |
8729 | to_close = NULL; | |
8730 | count_string = 0; | |
8731 | } | |
8732 | } | |
8733 | else | |
8734 | { | |
8735 | if (for_decimal) | |
8736 | fputs (for_decimal, file); | |
8737 | fprintf (file, "%d", c); | |
8738 | ||
8739 | for_string = "\n\t.byte \""; | |
8740 | for_decimal = ", "; | |
8741 | to_close = "\n"; | |
8742 | count_string = 0; | |
8743 | } | |
8744 | } | |
8745 | ||
8746 | /* Now close the string if we have written one. Then end the line. */ | |
8747 | if (to_close) | |
9ebbca7d | 8748 | fputs (to_close, file); |
9878760c RK |
8749 | } |
8750 | \f | |
8751 | /* Generate a unique section name for FILENAME for a section type | |
8752 | represented by SECTION_DESC. Output goes into BUF. | |
8753 | ||
8754 | SECTION_DESC can be any string, as long as it is different for each | |
8755 | possible section type. | |
8756 | ||
8757 | We name the section in the same manner as xlc. The name begins with an | |
8758 | underscore followed by the filename (after stripping any leading directory | |
11e5fe42 RK |
8759 | names) with the last period replaced by the string SECTION_DESC. If |
8760 | FILENAME does not contain a period, SECTION_DESC is appended to the end of | |
8761 | the name. */ | |
9878760c RK |
8762 | |
8763 | void | |
8764 | rs6000_gen_section_name (buf, filename, section_desc) | |
8765 | char **buf; | |
9ebbca7d GK |
8766 | const char *filename; |
8767 | const char *section_desc; | |
9878760c | 8768 | { |
9ebbca7d | 8769 | const char *q, *after_last_slash, *last_period = 0; |
9878760c RK |
8770 | char *p; |
8771 | int len; | |
9878760c RK |
8772 | |
8773 | after_last_slash = filename; | |
8774 | for (q = filename; *q; q++) | |
11e5fe42 RK |
8775 | { |
8776 | if (*q == '/') | |
8777 | after_last_slash = q + 1; | |
8778 | else if (*q == '.') | |
8779 | last_period = q; | |
8780 | } | |
9878760c | 8781 | |
11e5fe42 | 8782 | len = strlen (after_last_slash) + strlen (section_desc) + 2; |
9878760c RK |
8783 | *buf = (char *) permalloc (len); |
8784 | ||
8785 | p = *buf; | |
8786 | *p++ = '_'; | |
8787 | ||
8788 | for (q = after_last_slash; *q; q++) | |
8789 | { | |
11e5fe42 | 8790 | if (q == last_period) |
9878760c RK |
8791 | { |
8792 | strcpy (p, section_desc); | |
8793 | p += strlen (section_desc); | |
9878760c RK |
8794 | } |
8795 | ||
e9a780ec | 8796 | else if (ISALNUM (*q)) |
9878760c RK |
8797 | *p++ = *q; |
8798 | } | |
8799 | ||
11e5fe42 | 8800 | if (last_period == 0) |
9878760c RK |
8801 | strcpy (p, section_desc); |
8802 | else | |
8803 | *p = '\0'; | |
8804 | } | |
e165f3f0 | 8805 | \f |
a4f6c312 | 8806 | /* Emit profile function. */ |
411707f4 | 8807 | |
411707f4 CC |
8808 | void |
8809 | output_profile_hook (labelno) | |
8810 | int labelno; | |
8811 | { | |
8480e480 CC |
8812 | if (DEFAULT_ABI == ABI_AIX) |
8813 | { | |
8814 | char buf[30]; | |
40501e5f | 8815 | const char *label_name; |
8480e480 | 8816 | rtx fun; |
411707f4 | 8817 | |
8480e480 | 8818 | labelno += 1; |
411707f4 | 8819 | |
8480e480 CC |
8820 | ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno); |
8821 | STRIP_NAME_ENCODING (label_name, ggc_strdup (buf)); | |
8822 | fun = gen_rtx_SYMBOL_REF (Pmode, label_name); | |
411707f4 | 8823 | |
8480e480 CC |
8824 | emit_library_call (init_one_libfunc (RS6000_MCOUNT), 0, VOIDmode, 1, |
8825 | fun, Pmode); | |
8826 | } | |
ee890fe2 SS |
8827 | else if (DEFAULT_ABI == ABI_DARWIN) |
8828 | { | |
d5fa86ba | 8829 | const char *mcount_name = RS6000_MCOUNT; |
ee890fe2 SS |
8830 | int caller_addr_regno = LINK_REGISTER_REGNUM; |
8831 | ||
8832 | /* Be conservative and always set this, at least for now. */ | |
8833 | current_function_uses_pic_offset_table = 1; | |
8834 | ||
8835 | #if TARGET_MACHO | |
8836 | /* For PIC code, set up a stub and collect the caller's address | |
8837 | from r0, which is where the prologue puts it. */ | |
8838 | if (flag_pic) | |
8839 | { | |
8840 | mcount_name = machopic_stub_name (mcount_name); | |
8841 | if (current_function_uses_pic_offset_table) | |
8842 | caller_addr_regno = 0; | |
8843 | } | |
8844 | #endif | |
8845 | emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mcount_name), | |
8846 | 0, VOIDmode, 1, | |
8847 | gen_rtx_REG (Pmode, caller_addr_regno), Pmode); | |
8848 | } | |
411707f4 CC |
8849 | } |
8850 | ||
a4f6c312 | 8851 | /* Write function profiler code. */ |
e165f3f0 RK |
8852 | |
8853 | void | |
8854 | output_function_profiler (file, labelno) | |
8855 | FILE *file; | |
8856 | int labelno; | |
8857 | { | |
3daf36a4 | 8858 | char buf[100]; |
e165f3f0 | 8859 | |
3daf36a4 | 8860 | ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno); |
38c1f2d7 | 8861 | switch (DEFAULT_ABI) |
3daf36a4 | 8862 | { |
38c1f2d7 MM |
8863 | default: |
8864 | abort (); | |
8865 | ||
8866 | case ABI_V4: | |
38c1f2d7 MM |
8867 | case ABI_AIX_NODESC: |
8868 | fprintf (file, "\tmflr %s\n", reg_names[0]); | |
8869 | if (flag_pic == 1) | |
8870 | { | |
dfdfa60f DE |
8871 | fputs ("\tbl _GLOBAL_OFFSET_TABLE_@local-4\n", file); |
8872 | asm_fprintf (file, "\t{st|stw} %s,4(%s)\n", | |
8873 | reg_names[0], reg_names[1]); | |
17167fd8 | 8874 | asm_fprintf (file, "\tmflr %s\n", reg_names[12]); |
dfdfa60f | 8875 | asm_fprintf (file, "\t{l|lwz} %s,", reg_names[0]); |
38c1f2d7 | 8876 | assemble_name (file, buf); |
17167fd8 | 8877 | asm_fprintf (file, "@got(%s)\n", reg_names[12]); |
38c1f2d7 | 8878 | } |
9ebbca7d | 8879 | else if (flag_pic > 1) |
38c1f2d7 | 8880 | { |
dfdfa60f DE |
8881 | asm_fprintf (file, "\t{st|stw} %s,4(%s)\n", |
8882 | reg_names[0], reg_names[1]); | |
9ebbca7d GK |
8883 | /* Now, we need to get the address of the label. */ |
8884 | fputs ("\tbl 1f\n\t.long ", file); | |
034e84c4 | 8885 | assemble_name (file, buf); |
9ebbca7d GK |
8886 | fputs ("-.\n1:", file); |
8887 | asm_fprintf (file, "\tmflr %s\n", reg_names[11]); | |
8888 | asm_fprintf (file, "\t{l|lwz} %s,0(%s)\n", | |
8889 | reg_names[0], reg_names[11]); | |
8890 | asm_fprintf (file, "\t{cax|add} %s,%s,%s\n", | |
8891 | reg_names[0], reg_names[0], reg_names[11]); | |
38c1f2d7 | 8892 | } |
38c1f2d7 MM |
8893 | else |
8894 | { | |
17167fd8 | 8895 | asm_fprintf (file, "\t{liu|lis} %s,", reg_names[12]); |
38c1f2d7 | 8896 | assemble_name (file, buf); |
dfdfa60f | 8897 | fputs ("@ha\n", file); |
b5253831 DE |
8898 | asm_fprintf (file, "\t{st|stw} %s,4(%s)\n", |
8899 | reg_names[0], reg_names[1]); | |
a260abc9 | 8900 | asm_fprintf (file, "\t{cal|la} %s,", reg_names[0]); |
38c1f2d7 | 8901 | assemble_name (file, buf); |
17167fd8 | 8902 | asm_fprintf (file, "@l(%s)\n", reg_names[12]); |
38c1f2d7 MM |
8903 | } |
8904 | ||
b5253831 DE |
8905 | if (current_function_needs_context) |
8906 | asm_fprintf (file, "\tmr %s,%s\n", | |
8907 | reg_names[30], reg_names[STATIC_CHAIN_REGNUM]); | |
38c1f2d7 | 8908 | fprintf (file, "\tbl %s\n", RS6000_MCOUNT); |
b5253831 DE |
8909 | if (current_function_needs_context) |
8910 | asm_fprintf (file, "\tmr %s,%s\n", | |
8911 | reg_names[STATIC_CHAIN_REGNUM], reg_names[30]); | |
38c1f2d7 MM |
8912 | break; |
8913 | ||
8914 | case ABI_AIX: | |
ee890fe2 | 8915 | case ABI_DARWIN: |
a4f6c312 | 8916 | /* Don't do anything, done in output_profile_hook (). */ |
38c1f2d7 | 8917 | break; |
411707f4 | 8918 | |
38c1f2d7 | 8919 | } |
e165f3f0 | 8920 | } |
a251ffd0 TG |
8921 | |
8922 | /* Adjust the cost of a scheduling dependency. Return the new cost of | |
8923 | a dependency LINK or INSN on DEP_INSN. COST is the current cost. */ | |
8924 | ||
c237e94a | 8925 | static int |
a06faf84 | 8926 | rs6000_adjust_cost (insn, link, dep_insn, cost) |
a251ffd0 TG |
8927 | rtx insn; |
8928 | rtx link; | |
296b8152 | 8929 | rtx dep_insn ATTRIBUTE_UNUSED; |
a251ffd0 TG |
8930 | int cost; |
8931 | { | |
8932 | if (! recog_memoized (insn)) | |
8933 | return 0; | |
8934 | ||
8935 | if (REG_NOTE_KIND (link) != 0) | |
8936 | return 0; | |
8937 | ||
8938 | if (REG_NOTE_KIND (link) == 0) | |
8939 | { | |
ed947a96 DJ |
8940 | /* Data dependency; DEP_INSN writes a register that INSN reads |
8941 | some cycles later. */ | |
8942 | switch (get_attr_type (insn)) | |
8943 | { | |
8944 | case TYPE_JMPREG: | |
8945 | /* Tell the first scheduling pass about the latency between | |
8946 | a mtctr and bctr (and mtlr and br/blr). The first | |
8947 | scheduling pass will not know about this latency since | |
8948 | the mtctr instruction, which has the latency associated | |
8949 | to it, will be generated by reload. */ | |
8950 | return TARGET_POWER ? 5 : 4; | |
8951 | case TYPE_BRANCH: | |
8952 | /* Leave some extra cycles between a compare and its | |
8953 | dependent branch, to inhibit expensive mispredicts. */ | |
8954 | if ((rs6000_cpu_attr == CPU_PPC750 | |
8955 | || rs6000_cpu_attr == CPU_PPC7400 | |
8956 | || rs6000_cpu_attr == CPU_PPC7450) | |
8957 | && recog_memoized (dep_insn) | |
8958 | && (INSN_CODE (dep_insn) >= 0) | |
8959 | && (get_attr_type (dep_insn) == TYPE_COMPARE | |
8960 | || get_attr_type (dep_insn) == TYPE_DELAYED_COMPARE | |
8961 | || get_attr_type (dep_insn) == TYPE_FPCOMPARE | |
8962 | || get_attr_type (dep_insn) == TYPE_CR_LOGICAL)) | |
8963 | return cost + 2; | |
8964 | default: | |
8965 | break; | |
8966 | } | |
a251ffd0 TG |
8967 | /* Fall out to return default cost. */ |
8968 | } | |
8969 | ||
8970 | return cost; | |
8971 | } | |
b6c9286a | 8972 | |
a4f6c312 SS |
8973 | /* A C statement (sans semicolon) to update the integer scheduling |
8974 | priority INSN_PRIORITY (INSN). Reduce the priority to execute the | |
8975 | INSN earlier, increase the priority to execute INSN later. Do not | |
8976 | define this macro if you do not need to adjust the scheduling | |
8977 | priorities of insns. */ | |
bef84347 | 8978 | |
c237e94a | 8979 | static int |
bef84347 | 8980 | rs6000_adjust_priority (insn, priority) |
d330fd93 | 8981 | rtx insn ATTRIBUTE_UNUSED; |
bef84347 VM |
8982 | int priority; |
8983 | { | |
a4f6c312 SS |
8984 | /* On machines (like the 750) which have asymmetric integer units, |
8985 | where one integer unit can do multiply and divides and the other | |
8986 | can't, reduce the priority of multiply/divide so it is scheduled | |
8987 | before other integer operations. */ | |
bef84347 VM |
8988 | |
8989 | #if 0 | |
2c3c49de | 8990 | if (! INSN_P (insn)) |
bef84347 VM |
8991 | return priority; |
8992 | ||
8993 | if (GET_CODE (PATTERN (insn)) == USE) | |
8994 | return priority; | |
8995 | ||
8996 | switch (rs6000_cpu_attr) { | |
8997 | case CPU_PPC750: | |
8998 | switch (get_attr_type (insn)) | |
8999 | { | |
9000 | default: | |
9001 | break; | |
9002 | ||
9003 | case TYPE_IMUL: | |
9004 | case TYPE_IDIV: | |
3cb999d8 DE |
9005 | fprintf (stderr, "priority was %#x (%d) before adjustment\n", |
9006 | priority, priority); | |
bef84347 VM |
9007 | if (priority >= 0 && priority < 0x01000000) |
9008 | priority >>= 3; | |
9009 | break; | |
9010 | } | |
9011 | } | |
9012 | #endif | |
9013 | ||
9014 | return priority; | |
9015 | } | |
9016 | ||
a4f6c312 SS |
9017 | /* Return how many instructions the machine can issue per cycle. */ |
9018 | ||
c237e94a ZW |
9019 | static int |
9020 | rs6000_issue_rate () | |
b6c9286a MM |
9021 | { |
9022 | switch (rs6000_cpu_attr) { | |
3cb999d8 DE |
9023 | case CPU_RIOS1: /* ? */ |
9024 | case CPU_RS64A: | |
9025 | case CPU_PPC601: /* ? */ | |
ed947a96 | 9026 | case CPU_PPC7450: |
3cb999d8 | 9027 | return 3; |
b6c9286a | 9028 | case CPU_PPC603: |
bef84347 | 9029 | case CPU_PPC750: |
ed947a96 | 9030 | case CPU_PPC7400: |
bef84347 | 9031 | return 2; |
3cb999d8 | 9032 | case CPU_RIOS2: |
b6c9286a | 9033 | case CPU_PPC604: |
19684119 | 9034 | case CPU_PPC604E: |
b6c9286a | 9035 | case CPU_PPC620: |
3cb999d8 | 9036 | case CPU_PPC630: |
b6c9286a MM |
9037 | return 4; |
9038 | default: | |
9039 | return 1; | |
9040 | } | |
9041 | } | |
9042 | ||
b6c9286a | 9043 | \f |
b6c9286a MM |
9044 | /* Length in units of the trampoline for entering a nested function. */ |
9045 | ||
9046 | int | |
9047 | rs6000_trampoline_size () | |
9048 | { | |
9049 | int ret = 0; | |
9050 | ||
9051 | switch (DEFAULT_ABI) | |
9052 | { | |
9053 | default: | |
9054 | abort (); | |
9055 | ||
9056 | case ABI_AIX: | |
8f802bfb | 9057 | ret = (TARGET_32BIT) ? 12 : 24; |
b6c9286a MM |
9058 | break; |
9059 | ||
9060 | case ABI_V4: | |
9061 | case ABI_AIX_NODESC: | |
03a7e1a5 | 9062 | ret = (TARGET_32BIT) ? 40 : 48; |
b6c9286a | 9063 | break; |
b6c9286a MM |
9064 | } |
9065 | ||
9066 | return ret; | |
9067 | } | |
9068 | ||
9069 | /* Emit RTL insns to initialize the variable parts of a trampoline. | |
9070 | FNADDR is an RTX for the address of the function's pure code. | |
9071 | CXT is an RTX for the static chain value for the function. */ | |
9072 | ||
9073 | void | |
9074 | rs6000_initialize_trampoline (addr, fnaddr, cxt) | |
9075 | rtx addr; | |
9076 | rtx fnaddr; | |
9077 | rtx cxt; | |
9078 | { | |
ac2a93a1 | 9079 | enum machine_mode pmode = Pmode; |
8bd04c56 MM |
9080 | int regsize = (TARGET_32BIT) ? 4 : 8; |
9081 | rtx ctx_reg = force_reg (pmode, cxt); | |
b6c9286a MM |
9082 | |
9083 | switch (DEFAULT_ABI) | |
9084 | { | |
9085 | default: | |
9086 | abort (); | |
9087 | ||
8bd04c56 | 9088 | /* Macros to shorten the code expansions below. */ |
39403d82 | 9089 | #define MEM_DEREF(addr) gen_rtx_MEM (pmode, memory_address (pmode, addr)) |
c5c76735 JL |
9090 | #define MEM_PLUS(addr,offset) \ |
9091 | gen_rtx_MEM (pmode, memory_address (pmode, plus_constant (addr, offset))) | |
7c59dc5d | 9092 | |
b6c9286a MM |
9093 | /* Under AIX, just build the 3 word function descriptor */ |
9094 | case ABI_AIX: | |
8bd04c56 MM |
9095 | { |
9096 | rtx fn_reg = gen_reg_rtx (pmode); | |
9097 | rtx toc_reg = gen_reg_rtx (pmode); | |
9098 | emit_move_insn (fn_reg, MEM_DEREF (fnaddr)); | |
1cb18e3c | 9099 | emit_move_insn (toc_reg, MEM_PLUS (fnaddr, regsize)); |
8bd04c56 MM |
9100 | emit_move_insn (MEM_DEREF (addr), fn_reg); |
9101 | emit_move_insn (MEM_PLUS (addr, regsize), toc_reg); | |
9102 | emit_move_insn (MEM_PLUS (addr, 2*regsize), ctx_reg); | |
9103 | } | |
b6c9286a MM |
9104 | break; |
9105 | ||
eaf1bcf1 | 9106 | /* Under V.4/eabi, call __trampoline_setup to do the real work. */ |
b6c9286a MM |
9107 | case ABI_V4: |
9108 | case ABI_AIX_NODESC: | |
39403d82 | 9109 | emit_library_call (gen_rtx_SYMBOL_REF (SImode, "__trampoline_setup"), |
eaf1bcf1 MM |
9110 | FALSE, VOIDmode, 4, |
9111 | addr, pmode, | |
9112 | GEN_INT (rs6000_trampoline_size ()), SImode, | |
9113 | fnaddr, pmode, | |
9114 | ctx_reg, pmode); | |
b6c9286a | 9115 | break; |
b6c9286a MM |
9116 | } |
9117 | ||
9118 | return; | |
9119 | } | |
7509c759 MM |
9120 | |
9121 | \f | |
91d231cb | 9122 | /* Table of valid machine attributes. */ |
a4f6c312 | 9123 | |
91d231cb | 9124 | const struct attribute_spec rs6000_attribute_table[] = |
7509c759 | 9125 | { |
91d231cb JM |
9126 | /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */ |
9127 | { "longcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute }, | |
9128 | { NULL, 0, 0, false, false, false, NULL } | |
9129 | }; | |
7509c759 | 9130 | |
a4f6c312 SS |
9131 | /* Handle a "longcall" attribute; arguments as in struct |
9132 | attribute_spec.handler. */ | |
9133 | ||
91d231cb JM |
9134 | static tree |
9135 | rs6000_handle_longcall_attribute (node, name, args, flags, no_add_attrs) | |
9136 | tree *node; | |
9137 | tree name; | |
9138 | tree args ATTRIBUTE_UNUSED; | |
9139 | int flags ATTRIBUTE_UNUSED; | |
9140 | bool *no_add_attrs; | |
9141 | { | |
9142 | if (TREE_CODE (*node) != FUNCTION_TYPE | |
9143 | && TREE_CODE (*node) != FIELD_DECL | |
9144 | && TREE_CODE (*node) != TYPE_DECL) | |
9145 | { | |
9146 | warning ("`%s' attribute only applies to functions", | |
9147 | IDENTIFIER_POINTER (name)); | |
9148 | *no_add_attrs = true; | |
9149 | } | |
6a4cee5f | 9150 | |
91d231cb | 9151 | return NULL_TREE; |
7509c759 MM |
9152 | } |
9153 | ||
3cb999d8 DE |
9154 | /* Return a reference suitable for calling a function with the |
9155 | longcall attribute. */ | |
a4f6c312 | 9156 | |
6a4cee5f MM |
9157 | struct rtx_def * |
9158 | rs6000_longcall_ref (call_ref) | |
9159 | rtx call_ref; | |
9160 | { | |
d330fd93 | 9161 | const char *call_name; |
6a4cee5f MM |
9162 | tree node; |
9163 | ||
9164 | if (GET_CODE (call_ref) != SYMBOL_REF) | |
9165 | return call_ref; | |
9166 | ||
9167 | /* System V adds '.' to the internal name, so skip them. */ | |
9168 | call_name = XSTR (call_ref, 0); | |
9169 | if (*call_name == '.') | |
9170 | { | |
9171 | while (*call_name == '.') | |
9172 | call_name++; | |
9173 | ||
9174 | node = get_identifier (call_name); | |
39403d82 | 9175 | call_ref = gen_rtx_SYMBOL_REF (VOIDmode, IDENTIFIER_POINTER (node)); |
6a4cee5f MM |
9176 | } |
9177 | ||
9178 | return force_reg (Pmode, call_ref); | |
9179 | } | |
9180 | ||
7509c759 MM |
9181 | \f |
9182 | /* A C statement or statements to switch to the appropriate section | |
9183 | for output of RTX in mode MODE. You can assume that RTX is some | |
9184 | kind of constant in RTL. The argument MODE is redundant except in | |
9185 | the case of a `const_int' rtx. Select the section by calling | |
9186 | `text_section' or one of the alternatives for other sections. | |
9187 | ||
9188 | Do not define this macro if you put all constants in the read-only | |
9189 | data section. */ | |
9190 | ||
b91da81f | 9191 | #ifdef USING_ELFOS_H |
7509c759 MM |
9192 | |
9193 | void | |
9194 | rs6000_select_rtx_section (mode, x) | |
a9098fd0 | 9195 | enum machine_mode mode; |
7509c759 MM |
9196 | rtx x; |
9197 | { | |
a9098fd0 | 9198 | if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode)) |
7509c759 | 9199 | toc_section (); |
7509c759 MM |
9200 | else |
9201 | const_section (); | |
9202 | } | |
9203 | ||
9204 | /* A C statement or statements to switch to the appropriate | |
9205 | section for output of DECL. DECL is either a `VAR_DECL' node | |
9206 | or a constant of some sort. RELOC indicates whether forming | |
9207 | the initial value of DECL requires link-time relocations. */ | |
9208 | ||
9209 | void | |
9210 | rs6000_select_section (decl, reloc) | |
9211 | tree decl; | |
9212 | int reloc; | |
9213 | { | |
9214 | int size = int_size_in_bytes (TREE_TYPE (decl)); | |
63019373 GK |
9215 | int needs_sdata; |
9216 | int readonly; | |
9217 | static void (* const sec_funcs[4]) PARAMS ((void)) = { | |
9218 | &const_section, | |
9219 | &sdata2_section, | |
9220 | &data_section, | |
9221 | &sdata_section | |
9222 | }; | |
9223 | ||
9224 | needs_sdata = (size > 0 | |
9225 | && size <= g_switch_value | |
9226 | && rs6000_sdata != SDATA_NONE | |
9227 | && (rs6000_sdata != SDATA_DATA || TREE_PUBLIC (decl))); | |
7509c759 MM |
9228 | |
9229 | if (TREE_CODE (decl) == STRING_CST) | |
63019373 | 9230 | readonly = ! flag_writable_strings; |
a9098fd0 | 9231 | else if (TREE_CODE (decl) == VAR_DECL) |
63019373 GK |
9232 | readonly = (! (flag_pic && reloc) |
9233 | && TREE_READONLY (decl) | |
9234 | && ! TREE_SIDE_EFFECTS (decl) | |
9235 | && DECL_INITIAL (decl) | |
9236 | && DECL_INITIAL (decl) != error_mark_node | |
9237 | && TREE_CONSTANT (DECL_INITIAL (decl))); | |
ac4f7ad9 GK |
9238 | else if (TREE_CODE (decl) == CONSTRUCTOR) |
9239 | readonly = (! (flag_pic && reloc) | |
ac4f7ad9 | 9240 | && ! TREE_SIDE_EFFECTS (decl) |
f3afc192 | 9241 | && TREE_CONSTANT (decl)); |
7509c759 | 9242 | else |
63019373 GK |
9243 | readonly = 1; |
9244 | if (needs_sdata && rs6000_sdata != SDATA_EABI) | |
9245 | readonly = 0; | |
9246 | ||
9247 | (*sec_funcs[(readonly ? 0 : 2) + (needs_sdata ? 1 : 0)])(); | |
9248 | } | |
9249 | ||
9250 | /* A C statement to build up a unique section name, expressed as a | |
9251 | STRING_CST node, and assign it to DECL_SECTION_NAME (decl). | |
9252 | RELOC indicates whether the initial value of EXP requires | |
9253 | link-time relocations. If you do not define this macro, GCC will use | |
9254 | the symbol name prefixed by `.' as the section name. Note - this | |
f5143c46 | 9255 | macro can now be called for uninitialized data items as well as |
63019373 GK |
9256 | initialised data and functions. */ |
9257 | ||
9258 | void | |
9259 | rs6000_unique_section (decl, reloc) | |
9260 | tree decl; | |
9261 | int reloc; | |
9262 | { | |
9263 | int size = int_size_in_bytes (TREE_TYPE (decl)); | |
9264 | int needs_sdata; | |
9265 | int readonly; | |
9266 | int len; | |
9267 | int sec; | |
9268 | const char *name; | |
9269 | char *string; | |
9270 | const char *prefix; | |
9271 | ||
9272 | static const char *const prefixes[7][2] = | |
9273 | { | |
9274 | { ".text.", ".gnu.linkonce.t." }, | |
9275 | { ".rodata.", ".gnu.linkonce.r." }, | |
9276 | { ".sdata2.", ".gnu.linkonce.s2." }, | |
9277 | { ".data.", ".gnu.linkonce.d." }, | |
9278 | { ".sdata.", ".gnu.linkonce.s." }, | |
9279 | { ".bss.", ".gnu.linkonce.b." }, | |
9280 | { ".sbss.", ".gnu.linkonce.sb." } | |
9281 | }; | |
9282 | ||
9283 | needs_sdata = (TREE_CODE (decl) != FUNCTION_DECL | |
9284 | && size > 0 | |
9285 | && size <= g_switch_value | |
9286 | && rs6000_sdata != SDATA_NONE | |
9287 | && (rs6000_sdata != SDATA_DATA || TREE_PUBLIC (decl))); | |
9288 | ||
9289 | if (TREE_CODE (decl) == STRING_CST) | |
9290 | readonly = ! flag_writable_strings; | |
9291 | else if (TREE_CODE (decl) == VAR_DECL) | |
9292 | readonly = (! (flag_pic && reloc) | |
9293 | && TREE_READONLY (decl) | |
9294 | && ! TREE_SIDE_EFFECTS (decl) | |
9295 | && DECL_INITIAL (decl) | |
9296 | && DECL_INITIAL (decl) != error_mark_node | |
9297 | && TREE_CONSTANT (DECL_INITIAL (decl))); | |
9298 | else | |
9299 | readonly = 1; | |
9300 | if (needs_sdata && rs6000_sdata != SDATA_EABI) | |
9301 | readonly = 0; | |
9302 | ||
9303 | sec = ((TREE_CODE (decl) == FUNCTION_DECL ? 0 : 1) | |
9304 | + (readonly ? 0 : 2) | |
9305 | + (needs_sdata ? 1 : 0) | |
9306 | + (DECL_INITIAL (decl) == 0 | |
9307 | || DECL_INITIAL (decl) == error_mark_node) ? 4 : 0); | |
9308 | ||
e6978109 | 9309 | STRIP_NAME_ENCODING (name, IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl))); |
63019373 GK |
9310 | prefix = prefixes[sec][DECL_ONE_ONLY (decl)]; |
9311 | len = strlen (name) + strlen (prefix); | |
9312 | string = alloca (len + 1); | |
9313 | ||
9314 | sprintf (string, "%s%s", prefix, name); | |
9315 | ||
9316 | DECL_SECTION_NAME (decl) = build_string (len, string); | |
7509c759 | 9317 | } |
d9407988 MM |
9318 | |
9319 | \f | |
d9407988 MM |
9320 | /* If we are referencing a function that is static or is known to be |
9321 | in this file, make the SYMBOL_REF special. We can use this to indicate | |
9322 | that we can branch to this function without emitting a no-op after the | |
9ebbca7d | 9323 | call. For real AIX calling sequences, we also replace the |
d9407988 MM |
9324 | function name with the real name (1 or 2 leading .'s), rather than |
9325 | the function descriptor name. This saves a lot of overriding code | |
a260abc9 | 9326 | to read the prefixes. */ |
d9407988 MM |
9327 | |
9328 | void | |
9329 | rs6000_encode_section_info (decl) | |
9330 | tree decl; | |
9331 | { | |
9332 | if (TREE_CODE (decl) == FUNCTION_DECL) | |
9333 | { | |
9334 | rtx sym_ref = XEXP (DECL_RTL (decl), 0); | |
8f1b829e | 9335 | if ((TREE_ASM_WRITTEN (decl) || ! TREE_PUBLIC (decl)) |
c81fc13e | 9336 | && ! DECL_WEAK (decl)) |
d9407988 MM |
9337 | SYMBOL_REF_FLAG (sym_ref) = 1; |
9338 | ||
9ebbca7d | 9339 | if (DEFAULT_ABI == ABI_AIX) |
d9407988 | 9340 | { |
ff669a6c RH |
9341 | size_t len1 = (DEFAULT_ABI == ABI_AIX) ? 1 : 2; |
9342 | size_t len2 = strlen (XSTR (sym_ref, 0)); | |
520a57c8 | 9343 | char *str = alloca (len1 + len2 + 1); |
ff669a6c RH |
9344 | str[0] = '.'; |
9345 | str[1] = '.'; | |
9346 | memcpy (str + len1, XSTR (sym_ref, 0), len2 + 1); | |
9347 | ||
520a57c8 | 9348 | XSTR (sym_ref, 0) = ggc_alloc_string (str, len1 + len2); |
d9407988 MM |
9349 | } |
9350 | } | |
9351 | else if (rs6000_sdata != SDATA_NONE | |
f607bc57 | 9352 | && DEFAULT_ABI == ABI_V4 |
d9407988 MM |
9353 | && TREE_CODE (decl) == VAR_DECL) |
9354 | { | |
9355 | int size = int_size_in_bytes (TREE_TYPE (decl)); | |
9356 | tree section_name = DECL_SECTION_NAME (decl); | |
d330fd93 | 9357 | const char *name = (char *)0; |
d9407988 MM |
9358 | int len = 0; |
9359 | ||
9360 | if (section_name) | |
9361 | { | |
9362 | if (TREE_CODE (section_name) == STRING_CST) | |
9363 | { | |
9364 | name = TREE_STRING_POINTER (section_name); | |
9365 | len = TREE_STRING_LENGTH (section_name); | |
9366 | } | |
9367 | else | |
9368 | abort (); | |
9369 | } | |
9370 | ||
9371 | if ((size > 0 && size <= g_switch_value) | |
9372 | || (name | |
5f59ecb7 | 9373 | && ((len == sizeof (".sdata") - 1 |
3cb999d8 | 9374 | && strcmp (name, ".sdata") == 0) |
5f59ecb7 | 9375 | || (len == sizeof (".sdata2") - 1 |
3cb999d8 | 9376 | && strcmp (name, ".sdata2") == 0) |
5f59ecb7 | 9377 | || (len == sizeof (".sbss") - 1 |
3cb999d8 | 9378 | && strcmp (name, ".sbss") == 0) |
5f59ecb7 | 9379 | || (len == sizeof (".sbss2") - 1 |
3cb999d8 | 9380 | && strcmp (name, ".sbss2") == 0) |
5f59ecb7 | 9381 | || (len == sizeof (".PPC.EMB.sdata0") - 1 |
3cb999d8 | 9382 | && strcmp (name, ".PPC.EMB.sdata0") == 0) |
5f59ecb7 | 9383 | || (len == sizeof (".PPC.EMB.sbss0") - 1 |
3cb999d8 | 9384 | && strcmp (name, ".PPC.EMB.sbss0") == 0)))) |
d9407988 MM |
9385 | { |
9386 | rtx sym_ref = XEXP (DECL_RTL (decl), 0); | |
ff669a6c | 9387 | size_t len = strlen (XSTR (sym_ref, 0)); |
88c1e412 | 9388 | char *str = alloca (len + 2); |
ff669a6c | 9389 | |
ff669a6c RH |
9390 | str[0] = '@'; |
9391 | memcpy (str + 1, XSTR (sym_ref, 0), len + 1); | |
88c1e412 | 9392 | XSTR (sym_ref, 0) = ggc_alloc_string (str, len + 1); |
d9407988 MM |
9393 | } |
9394 | } | |
9395 | } | |
9396 | ||
b91da81f | 9397 | #endif /* USING_ELFOS_H */ |
000034eb | 9398 | |
a6c2a102 | 9399 | \f |
000034eb | 9400 | /* Return a REG that occurs in ADDR with coefficient 1. |
02441cd6 JL |
9401 | ADDR can be effectively incremented by incrementing REG. |
9402 | ||
9403 | r0 is special and we must not select it as an address | |
9404 | register by this routine since our caller will try to | |
9405 | increment the returned register via an "la" instruction. */ | |
000034eb DE |
9406 | |
9407 | struct rtx_def * | |
9408 | find_addr_reg (addr) | |
9409 | rtx addr; | |
9410 | { | |
9411 | while (GET_CODE (addr) == PLUS) | |
9412 | { | |
02441cd6 JL |
9413 | if (GET_CODE (XEXP (addr, 0)) == REG |
9414 | && REGNO (XEXP (addr, 0)) != 0) | |
000034eb | 9415 | addr = XEXP (addr, 0); |
02441cd6 JL |
9416 | else if (GET_CODE (XEXP (addr, 1)) == REG |
9417 | && REGNO (XEXP (addr, 1)) != 0) | |
000034eb DE |
9418 | addr = XEXP (addr, 1); |
9419 | else if (CONSTANT_P (XEXP (addr, 0))) | |
9420 | addr = XEXP (addr, 1); | |
9421 | else if (CONSTANT_P (XEXP (addr, 1))) | |
9422 | addr = XEXP (addr, 0); | |
9423 | else | |
9424 | abort (); | |
9425 | } | |
02441cd6 | 9426 | if (GET_CODE (addr) == REG && REGNO (addr) != 0) |
000034eb DE |
9427 | return addr; |
9428 | abort (); | |
9429 | } | |
9430 | ||
a6c2a102 DE |
9431 | void |
9432 | rs6000_fatal_bad_address (op) | |
9433 | rtx op; | |
9434 | { | |
9435 | fatal_insn ("bad address", op); | |
9436 | } | |
c8023011 MM |
9437 | |
9438 | /* Called to register all of our global variables with the garbage | |
9439 | collector. */ | |
9440 | ||
9441 | static void | |
9442 | rs6000_add_gc_roots () | |
9443 | { | |
9444 | ggc_add_rtx_root (&rs6000_compare_op0, 1); | |
9445 | ggc_add_rtx_root (&rs6000_compare_op1, 1); | |
9ebbca7d GK |
9446 | |
9447 | toc_hash_table = htab_create (1021, toc_hash_function, toc_hash_eq, NULL); | |
9448 | ggc_add_root (&toc_hash_table, 1, sizeof (toc_hash_table), | |
9449 | toc_hash_mark_table); | |
ee890fe2 SS |
9450 | |
9451 | #if TARGET_MACHO | |
9452 | machopic_add_gc_roots (); | |
9453 | #endif | |
9454 | } | |
9455 | ||
9456 | #if TARGET_MACHO | |
9457 | ||
9458 | #if 0 | |
9459 | /* Returns 1 if OP is either a symbol reference or a sum of a symbol | |
9460 | reference and a constant. */ | |
9461 | ||
9462 | int | |
9463 | symbolic_operand (op) | |
592696dd | 9464 | rtx op; |
ee890fe2 SS |
9465 | { |
9466 | switch (GET_CODE (op)) | |
9467 | { | |
9468 | case SYMBOL_REF: | |
9469 | case LABEL_REF: | |
9470 | return 1; | |
9471 | case CONST: | |
9472 | op = XEXP (op, 0); | |
9473 | return (GET_CODE (op) == SYMBOL_REF || | |
9474 | (GET_CODE (XEXP (op, 0)) == SYMBOL_REF | |
9475 | || GET_CODE (XEXP (op, 0)) == LABEL_REF) | |
9476 | && GET_CODE (XEXP (op, 1)) == CONST_INT); | |
9477 | default: | |
9478 | return 0; | |
9479 | } | |
c8023011 | 9480 | } |
ee890fe2 SS |
9481 | #endif |
9482 | ||
9483 | #ifdef RS6000_LONG_BRANCH | |
9484 | ||
9485 | static tree stub_list = 0; | |
9486 | ||
9487 | /* ADD_COMPILER_STUB adds the compiler generated stub for handling | |
9488 | procedure calls to the linked list. */ | |
9489 | ||
9490 | void | |
9491 | add_compiler_stub (label_name, function_name, line_number) | |
9492 | tree label_name; | |
9493 | tree function_name; | |
9494 | int line_number; | |
9495 | { | |
9496 | tree stub = build_tree_list (function_name, label_name); | |
9497 | TREE_TYPE (stub) = build_int_2 (line_number, 0); | |
9498 | TREE_CHAIN (stub) = stub_list; | |
9499 | stub_list = stub; | |
9500 | } | |
9501 | ||
9502 | #define STUB_LABEL_NAME(STUB) TREE_VALUE (STUB) | |
9503 | #define STUB_FUNCTION_NAME(STUB) TREE_PURPOSE (STUB) | |
9504 | #define STUB_LINE_NUMBER(STUB) TREE_INT_CST_LOW (TREE_TYPE (STUB)) | |
9505 | ||
a4f6c312 SS |
9506 | /* OUTPUT_COMPILER_STUB outputs the compiler generated stub for |
9507 | handling procedure calls from the linked list and initializes the | |
9508 | linked list. */ | |
ee890fe2 | 9509 | |
a4f6c312 SS |
9510 | void |
9511 | output_compiler_stub () | |
ee890fe2 SS |
9512 | { |
9513 | char tmp_buf[256]; | |
9514 | char label_buf[256]; | |
9515 | char *label; | |
9516 | tree tmp_stub, stub; | |
9517 | ||
9518 | if (!flag_pic) | |
9519 | for (stub = stub_list; stub; stub = TREE_CHAIN (stub)) | |
9520 | { | |
9521 | fprintf (asm_out_file, | |
9522 | "%s:\n", IDENTIFIER_POINTER(STUB_LABEL_NAME(stub))); | |
9523 | ||
9524 | #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO) | |
9525 | if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG) | |
9526 | fprintf (asm_out_file, "\t.stabd 68,0,%d\n", STUB_LINE_NUMBER(stub)); | |
9527 | #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */ | |
9528 | ||
9529 | if (IDENTIFIER_POINTER (STUB_FUNCTION_NAME (stub))[0] == '*') | |
9530 | strcpy (label_buf, | |
9531 | IDENTIFIER_POINTER (STUB_FUNCTION_NAME (stub))+1); | |
9532 | else | |
9533 | { | |
9534 | label_buf[0] = '_'; | |
9535 | strcpy (label_buf+1, | |
9536 | IDENTIFIER_POINTER (STUB_FUNCTION_NAME (stub))); | |
9537 | } | |
9538 | ||
9539 | strcpy (tmp_buf, "lis r12,hi16("); | |
9540 | strcat (tmp_buf, label_buf); | |
9541 | strcat (tmp_buf, ")\n\tori r12,r12,lo16("); | |
9542 | strcat (tmp_buf, label_buf); | |
9543 | strcat (tmp_buf, ")\n\tmtctr r12\n\tbctr"); | |
9544 | output_asm_insn (tmp_buf, 0); | |
9545 | ||
9546 | #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO) | |
9547 | if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG) | |
9548 | fprintf(asm_out_file, "\t.stabd 68,0,%d\n", STUB_LINE_NUMBER (stub)); | |
9549 | #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */ | |
9550 | } | |
9551 | ||
9552 | stub_list = 0; | |
9553 | } | |
9554 | ||
9555 | /* NO_PREVIOUS_DEF checks in the link list whether the function name is | |
9556 | already there or not. */ | |
9557 | ||
a4f6c312 SS |
9558 | int |
9559 | no_previous_def (function_name) | |
ee890fe2 SS |
9560 | tree function_name; |
9561 | { | |
9562 | tree stub; | |
9563 | for (stub = stub_list; stub; stub = TREE_CHAIN (stub)) | |
9564 | if (function_name == STUB_FUNCTION_NAME (stub)) | |
9565 | return 0; | |
9566 | return 1; | |
9567 | } | |
9568 | ||
9569 | /* GET_PREV_LABEL gets the label name from the previous definition of | |
9570 | the function. */ | |
9571 | ||
a4f6c312 SS |
9572 | tree |
9573 | get_prev_label (function_name) | |
ee890fe2 SS |
9574 | tree function_name; |
9575 | { | |
9576 | tree stub; | |
9577 | for (stub = stub_list; stub; stub = TREE_CHAIN (stub)) | |
9578 | if (function_name == STUB_FUNCTION_NAME (stub)) | |
9579 | return STUB_LABEL_NAME (stub); | |
9580 | return 0; | |
9581 | } | |
9582 | ||
9583 | /* INSN is either a function call or a millicode call. It may have an | |
9584 | unconditional jump in its delay slot. | |
9585 | ||
9586 | CALL_DEST is the routine we are calling. */ | |
9587 | ||
9588 | char * | |
9589 | output_call (insn, call_dest, operand_number) | |
9590 | rtx insn; | |
9591 | rtx call_dest; | |
9592 | int operand_number; | |
9593 | { | |
9594 | static char buf[256]; | |
9595 | if (GET_CODE (call_dest) == SYMBOL_REF && TARGET_LONG_BRANCH && !flag_pic) | |
9596 | { | |
9597 | tree labelname; | |
9598 | tree funname = get_identifier (XSTR (call_dest, 0)); | |
9599 | ||
9600 | if (no_previous_def (funname)) | |
9601 | { | |
9602 | int line_number; | |
9603 | rtx label_rtx = gen_label_rtx (); | |
9604 | char *label_buf, temp_buf[256]; | |
9605 | ASM_GENERATE_INTERNAL_LABEL (temp_buf, "L", | |
9606 | CODE_LABEL_NUMBER (label_rtx)); | |
9607 | label_buf = temp_buf[0] == '*' ? temp_buf + 1 : temp_buf; | |
9608 | labelname = get_identifier (label_buf); | |
9609 | for (; insn && GET_CODE (insn) != NOTE; insn = PREV_INSN (insn)); | |
9610 | if (insn) | |
9611 | line_number = NOTE_LINE_NUMBER (insn); | |
9612 | add_compiler_stub (labelname, funname, line_number); | |
9613 | } | |
9614 | else | |
9615 | labelname = get_prev_label (funname); | |
9616 | ||
9617 | sprintf (buf, "jbsr %%z%d,%.246s", | |
9618 | operand_number, IDENTIFIER_POINTER (labelname)); | |
9619 | return buf; | |
9620 | } | |
9621 | else | |
9622 | { | |
9623 | sprintf (buf, "bl %%z%d", operand_number); | |
9624 | return buf; | |
9625 | } | |
9626 | } | |
9627 | ||
9628 | #endif /* RS6000_LONG_BRANCH */ | |
9629 | ||
9630 | #define GEN_LOCAL_LABEL_FOR_SYMBOL(BUF,SYMBOL,LENGTH,N) \ | |
9631 | do { \ | |
83182544 | 9632 | const char *const symbol_ = (SYMBOL); \ |
ee890fe2 SS |
9633 | char *buffer_ = (BUF); \ |
9634 | if (symbol_[0] == '"') \ | |
9635 | { \ | |
9636 | sprintf(buffer_, "\"L%d$%s", (N), symbol_+1); \ | |
9637 | } \ | |
9638 | else if (name_needs_quotes(symbol_)) \ | |
9639 | { \ | |
9640 | sprintf(buffer_, "\"L%d$%s\"", (N), symbol_); \ | |
9641 | } \ | |
9642 | else \ | |
9643 | { \ | |
9644 | sprintf(buffer_, "L%d$%s", (N), symbol_); \ | |
9645 | } \ | |
9646 | } while (0) | |
9647 | ||
9648 | ||
9649 | /* Generate PIC and indirect symbol stubs. */ | |
9650 | ||
9651 | void | |
9652 | machopic_output_stub (file, symb, stub) | |
9653 | FILE *file; | |
9654 | const char *symb, *stub; | |
9655 | { | |
9656 | unsigned int length; | |
a4f6c312 SS |
9657 | char *symbol_name, *lazy_ptr_name; |
9658 | char *local_label_0; | |
ee890fe2 SS |
9659 | static int label = 0; |
9660 | ||
df56a27f SS |
9661 | /* Lose our funky encoding stuff so it doesn't contaminate the stub. */ |
9662 | STRIP_NAME_ENCODING (symb, symb); | |
9663 | ||
ee890fe2 SS |
9664 | label += 1; |
9665 | ||
ee890fe2 SS |
9666 | length = strlen (symb); |
9667 | symbol_name = alloca (length + 32); | |
9668 | GEN_SYMBOL_NAME_FOR_SYMBOL (symbol_name, symb, length); | |
9669 | ||
9670 | lazy_ptr_name = alloca (length + 32); | |
9671 | GEN_LAZY_PTR_NAME_FOR_SYMBOL (lazy_ptr_name, symb, length); | |
9672 | ||
9673 | local_label_0 = alloca (length + 32); | |
9674 | GEN_LOCAL_LABEL_FOR_SYMBOL (local_label_0, symb, length, 0); | |
9675 | ||
ee890fe2 SS |
9676 | if (flag_pic == 2) |
9677 | machopic_picsymbol_stub_section (); | |
9678 | else | |
9679 | machopic_symbol_stub_section (); | |
9680 | ||
9681 | fprintf (file, "%s:\n", stub); | |
9682 | fprintf (file, "\t.indirect_symbol %s\n", symbol_name); | |
9683 | ||
9684 | if (flag_pic == 2) | |
9685 | { | |
9686 | fprintf (file, "\tmflr r0\n"); | |
9687 | fprintf (file, "\tbcl 20,31,%s\n", local_label_0); | |
9688 | fprintf (file, "%s:\n\tmflr r11\n", local_label_0); | |
9689 | fprintf (file, "\taddis r11,r11,ha16(%s-%s)\n", | |
9690 | lazy_ptr_name, local_label_0); | |
9691 | fprintf (file, "\tmtlr r0\n"); | |
9692 | fprintf (file, "\tlwz r12,lo16(%s-%s)(r11)\n", | |
9693 | lazy_ptr_name, local_label_0); | |
9694 | fprintf (file, "\tmtctr r12\n"); | |
9695 | fprintf (file, "\taddi r11,r11,lo16(%s-%s)\n", | |
9696 | lazy_ptr_name, local_label_0); | |
9697 | fprintf (file, "\tbctr\n"); | |
9698 | } | |
9699 | else | |
9700 | fprintf (file, "non-pure not supported\n"); | |
9701 | ||
9702 | machopic_lazy_symbol_ptr_section (); | |
9703 | fprintf (file, "%s:\n", lazy_ptr_name); | |
9704 | fprintf (file, "\t.indirect_symbol %s\n", symbol_name); | |
9705 | fprintf (file, "\t.long dyld_stub_binding_helper\n"); | |
9706 | } | |
9707 | ||
9708 | /* Legitimize PIC addresses. If the address is already | |
9709 | position-independent, we return ORIG. Newly generated | |
9710 | position-independent addresses go into a reg. This is REG if non | |
9711 | zero, otherwise we allocate register(s) as necessary. */ | |
9712 | ||
9713 | #define SMALL_INT(X) ((unsigned) (INTVAL(X) + 0x4000) < 0x8000) | |
9714 | ||
9715 | rtx | |
9716 | rs6000_machopic_legitimize_pic_address (orig, mode, reg) | |
9717 | rtx orig; | |
9718 | enum machine_mode mode; | |
9719 | rtx reg; | |
9720 | { | |
9721 | rtx base, offset; | |
9722 | ||
9723 | if (reg == NULL && ! reload_in_progress && ! reload_completed) | |
9724 | reg = gen_reg_rtx (Pmode); | |
9725 | ||
9726 | if (GET_CODE (orig) == CONST) | |
9727 | { | |
9728 | if (GET_CODE (XEXP (orig, 0)) == PLUS | |
9729 | && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx) | |
9730 | return orig; | |
9731 | ||
9732 | if (GET_CODE (XEXP (orig, 0)) == PLUS) | |
9733 | { | |
a4f6c312 SS |
9734 | base = |
9735 | rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 0), | |
9736 | Pmode, reg); | |
9737 | offset = | |
9738 | rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 1), | |
9739 | Pmode, reg); | |
ee890fe2 SS |
9740 | } |
9741 | else | |
9742 | abort (); | |
9743 | ||
9744 | if (GET_CODE (offset) == CONST_INT) | |
9745 | { | |
9746 | if (SMALL_INT (offset)) | |
ed8908e7 | 9747 | return plus_constant (base, INTVAL (offset)); |
ee890fe2 SS |
9748 | else if (! reload_in_progress && ! reload_completed) |
9749 | offset = force_reg (Pmode, offset); | |
9750 | else | |
9751 | abort (); | |
9752 | } | |
9753 | return gen_rtx (PLUS, Pmode, base, offset); | |
9754 | } | |
9755 | ||
9756 | /* Fall back on generic machopic code. */ | |
9757 | return machopic_legitimize_pic_address (orig, mode, reg); | |
9758 | } | |
9759 | ||
9760 | /* This is just a placeholder to make linking work without having to | |
9761 | add this to the generic Darwin EXTRA_SECTIONS. If -mcall-aix is | |
9762 | ever needed for Darwin (not too likely!) this would have to get a | |
9763 | real definition. */ | |
9764 | ||
9765 | void | |
9766 | toc_section () | |
9767 | { | |
9768 | } | |
9769 | ||
9770 | #endif /* TARGET_MACHO */ | |
7c262518 RH |
9771 | |
9772 | #if TARGET_ELF | |
9773 | static unsigned int | |
9774 | rs6000_elf_section_type_flags (decl, name, reloc) | |
9775 | tree decl; | |
9776 | const char *name; | |
9777 | int reloc; | |
9778 | { | |
9779 | unsigned int flags = default_section_type_flags (decl, name, reloc); | |
9780 | ||
270fc29b RH |
9781 | if (TARGET_RELOCATABLE) |
9782 | flags |= SECTION_WRITE; | |
7c262518 | 9783 | |
d0101753 | 9784 | return flags; |
7c262518 | 9785 | } |
d9f6800d RH |
9786 | |
9787 | /* Record an element in the table of global constructors. SYMBOL is | |
9788 | a SYMBOL_REF of the function to be called; PRIORITY is a number | |
9789 | between 0 and MAX_INIT_PRIORITY. | |
9790 | ||
9791 | This differs from default_named_section_asm_out_constructor in | |
9792 | that we have special handling for -mrelocatable. */ | |
9793 | ||
9794 | static void | |
9795 | rs6000_elf_asm_out_constructor (symbol, priority) | |
9796 | rtx symbol; | |
9797 | int priority; | |
9798 | { | |
9799 | const char *section = ".ctors"; | |
9800 | char buf[16]; | |
9801 | ||
9802 | if (priority != DEFAULT_INIT_PRIORITY) | |
9803 | { | |
9804 | sprintf (buf, ".ctors.%.5u", | |
9805 | /* Invert the numbering so the linker puts us in the proper | |
9806 | order; constructors are run from right to left, and the | |
9807 | linker sorts in increasing order. */ | |
9808 | MAX_INIT_PRIORITY - priority); | |
9809 | section = buf; | |
9810 | } | |
9811 | ||
715bdd29 RH |
9812 | named_section_flags (section, SECTION_WRITE); |
9813 | assemble_align (POINTER_SIZE); | |
d9f6800d RH |
9814 | |
9815 | if (TARGET_RELOCATABLE) | |
9816 | { | |
9817 | fputs ("\t.long (", asm_out_file); | |
9818 | output_addr_const (asm_out_file, symbol); | |
9819 | fputs (")@fixup\n", asm_out_file); | |
9820 | } | |
9821 | else | |
c8af3574 | 9822 | assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1); |
d9f6800d RH |
9823 | } |
9824 | ||
9825 | static void | |
9826 | rs6000_elf_asm_out_destructor (symbol, priority) | |
9827 | rtx symbol; | |
9828 | int priority; | |
9829 | { | |
9830 | const char *section = ".dtors"; | |
9831 | char buf[16]; | |
9832 | ||
9833 | if (priority != DEFAULT_INIT_PRIORITY) | |
9834 | { | |
9835 | sprintf (buf, ".dtors.%.5u", | |
9836 | /* Invert the numbering so the linker puts us in the proper | |
9837 | order; constructors are run from right to left, and the | |
9838 | linker sorts in increasing order. */ | |
9839 | MAX_INIT_PRIORITY - priority); | |
9840 | section = buf; | |
9841 | } | |
9842 | ||
715bdd29 RH |
9843 | named_section_flags (section, SECTION_WRITE); |
9844 | assemble_align (POINTER_SIZE); | |
d9f6800d RH |
9845 | |
9846 | if (TARGET_RELOCATABLE) | |
9847 | { | |
9848 | fputs ("\t.long (", asm_out_file); | |
9849 | output_addr_const (asm_out_file, symbol); | |
9850 | fputs (")@fixup\n", asm_out_file); | |
9851 | } | |
9852 | else | |
c8af3574 | 9853 | assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1); |
d9f6800d | 9854 | } |
7c262518 RH |
9855 | #endif |
9856 | ||
9857 | #ifdef OBJECT_FORMAT_COFF | |
9858 | static void | |
715bdd29 | 9859 | xcoff_asm_named_section (name, flags) |
7c262518 RH |
9860 | const char *name; |
9861 | unsigned int flags ATTRIBUTE_UNUSED; | |
7c262518 RH |
9862 | { |
9863 | fprintf (asm_out_file, "\t.csect %s\n", name); | |
9864 | } | |
9865 | #endif |