]>
Commit | Line | Data |
---|---|---|
9878760c | 1 | /* Subroutines used for code generation on IBM RS/6000. |
4d30c363 | 2 | Copyright (C) 1991, 1993, 1994, 1995 Free Software Foundation, Inc. |
fab3bcc3 | 3 | Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu) |
9878760c RK |
4 | |
5 | This file is part of GNU CC. | |
6 | ||
7 | GNU CC is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 2, or (at your option) | |
10 | any later version. | |
11 | ||
12 | GNU CC is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with GNU CC; see the file COPYING. If not, write to | |
19 | the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ | |
20 | ||
21 | #include <stdio.h> | |
127b0efc | 22 | #include <ctype.h> |
9878760c RK |
23 | #include "config.h" |
24 | #include "rtl.h" | |
25 | #include "regs.h" | |
26 | #include "hard-reg-set.h" | |
27 | #include "real.h" | |
28 | #include "insn-config.h" | |
29 | #include "conditions.h" | |
30 | #include "insn-flags.h" | |
31 | #include "output.h" | |
32 | #include "insn-attr.h" | |
33 | #include "flags.h" | |
34 | #include "recog.h" | |
35 | #include "expr.h" | |
36 | #include "obstack.h" | |
9b30bae2 JW |
37 | #include "tree.h" |
38 | ||
39 | extern char *language_string; | |
5248c961 | 40 | extern int profile_block_flag; |
9878760c RK |
41 | |
42 | #define min(A,B) ((A) < (B) ? (A) : (B)) | |
43 | #define max(A,B) ((A) > (B) ? (A) : (B)) | |
44 | ||
5248c961 RK |
45 | /* Target cpu type */ |
46 | ||
47 | enum processor_type rs6000_cpu; | |
48 | char *rs6000_cpu_string; | |
49 | ||
9878760c RK |
50 | /* Set to non-zero by "fix" operation to indicate that itrunc and |
51 | uitrunc must be defined. */ | |
52 | ||
53 | int rs6000_trunc_used; | |
54 | ||
55 | /* Set to non-zero once they have been defined. */ | |
56 | ||
57 | static int trunc_defined; | |
58 | ||
c764f757 RK |
59 | /* Set to non-zero once AIX common-mode calls have been defined. */ |
60 | static int common_mode_defined; | |
9878760c RK |
61 | /* Save information from a "cmpxx" operation until the branch or scc is |
62 | emitted. */ | |
63 | ||
64 | rtx rs6000_compare_op0, rs6000_compare_op1; | |
65 | int rs6000_compare_fp_p; | |
874a0744 MM |
66 | |
67 | #ifdef USING_SVR4_H | |
68 | /* Label number of label created for -mrelocatable, to call to so we can | |
69 | get the address of the GOT section */ | |
70 | int rs6000_pic_labelno; | |
71 | #endif | |
9878760c | 72 | \f |
5248c961 RK |
73 | /* Override command line options. Mostly we process the processor |
74 | type and sometimes adjust other TARGET_ options. */ | |
75 | ||
76 | void | |
77 | rs6000_override_options () | |
78 | { | |
79 | int i; | |
80 | ||
85638c0d RK |
81 | /* Simplify the entries below by making a mask for any POWER |
82 | variant and any PowerPC variant. */ | |
83 | ||
d14a6d05 | 84 | #define POWER_MASKS (MASK_POWER | MASK_POWER2 | MASK_MULTIPLE) |
68c49ffa RK |
85 | #define POWERPC_MASKS (MASK_POWERPC | MASK_PPC_GPOPT \ |
86 | | MASK_PPC_GFXOPT | MASK_POWERPC64) | |
87 | #define POWERPC_OPT_MASKS (MASK_PPC_GPOPT | MASK_PPC_GFXOPT) | |
85638c0d | 88 | |
5248c961 RK |
89 | static struct ptt |
90 | { | |
91 | char *name; /* Canonical processor name. */ | |
92 | enum processor_type processor; /* Processor type enum value. */ | |
93 | int target_enable; /* Target flags to enable. */ | |
94 | int target_disable; /* Target flags to disable. */ | |
95 | } processor_target_table[] | |
db7f1e43 RK |
96 | = {{"common", PROCESSOR_COMMON, 0, POWER_MASKS | POWERPC_MASKS}, |
97 | {"power", PROCESSOR_POWER, | |
d14a6d05 | 98 | MASK_POWER | MASK_MULTIPLE, |
db7f1e43 RK |
99 | MASK_POWER2 | POWERPC_MASKS | MASK_NEW_MNEMONICS}, |
100 | {"powerpc", PROCESSOR_POWERPC, | |
101 | MASK_POWERPC | MASK_NEW_MNEMONICS, | |
68c49ffa | 102 | POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64}, |
db7f1e43 | 103 | {"rios", PROCESSOR_RIOS1, |
d14a6d05 | 104 | MASK_POWER | MASK_MULTIPLE, |
db7f1e43 RK |
105 | MASK_POWER2 | POWERPC_MASKS | MASK_NEW_MNEMONICS}, |
106 | {"rios1", PROCESSOR_RIOS1, | |
d14a6d05 | 107 | MASK_POWER | MASK_MULTIPLE, |
db7f1e43 RK |
108 | MASK_POWER2 | POWERPC_MASKS | MASK_NEW_MNEMONICS}, |
109 | {"rsc", PROCESSOR_PPC601, | |
d14a6d05 | 110 | MASK_POWER | MASK_MULTIPLE, |
db7f1e43 RK |
111 | MASK_POWER2 | POWERPC_MASKS | MASK_NEW_MNEMONICS}, |
112 | {"rsc1", PROCESSOR_PPC601, | |
d14a6d05 | 113 | MASK_POWER | MASK_MULTIPLE, |
db7f1e43 RK |
114 | MASK_POWER2 | POWERPC_MASKS | MASK_NEW_MNEMONICS}, |
115 | {"rios2", PROCESSOR_RIOS2, | |
d14a6d05 | 116 | MASK_POWER | MASK_MULTIPLE | MASK_POWER2, |
db7f1e43 | 117 | POWERPC_MASKS | MASK_NEW_MNEMONICS}, |
49a0b204 MM |
118 | {"403", PROCESSOR_PPC403, |
119 | MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS, | |
120 | POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64}, | |
121 | {"mpc403", PROCESSOR_PPC403, | |
122 | MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS, | |
123 | POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64}, | |
124 | {"ppc403", PROCESSOR_PPC403, | |
125 | MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS, | |
126 | POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64}, | |
5248c961 | 127 | {"601", PROCESSOR_PPC601, |
d14a6d05 | 128 | MASK_POWER | MASK_POWERPC | MASK_NEW_MNEMONICS | MASK_MULTIPLE, |
68c49ffa | 129 | MASK_POWER2 | POWERPC_OPT_MASKS | MASK_POWERPC64}, |
49947f18 | 130 | {"mpc601", PROCESSOR_PPC601, |
d14a6d05 | 131 | MASK_POWER | MASK_POWERPC | MASK_NEW_MNEMONICS | MASK_MULTIPLE, |
68c49ffa | 132 | MASK_POWER2 | POWERPC_OPT_MASKS | MASK_POWERPC64}, |
85638c0d | 133 | {"ppc601", PROCESSOR_PPC601, |
d14a6d05 | 134 | MASK_POWER | MASK_POWERPC | MASK_NEW_MNEMONICS | MASK_MULTIPLE, |
68c49ffa | 135 | MASK_POWER2 | POWERPC_OPT_MASKS | MASK_POWERPC64}, |
5248c961 | 136 | {"603", PROCESSOR_PPC603, |
68c49ffa RK |
137 | MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS, |
138 | POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64}, | |
49947f18 | 139 | {"mpc603", PROCESSOR_PPC603, |
68c49ffa RK |
140 | MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS, |
141 | POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64}, | |
85638c0d | 142 | {"ppc603", PROCESSOR_PPC603, |
68c49ffa RK |
143 | MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS, |
144 | POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64}, | |
5248c961 | 145 | {"604", PROCESSOR_PPC604, |
68c49ffa RK |
146 | MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS, |
147 | POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64}, | |
49947f18 | 148 | {"mpc604", PROCESSOR_PPC604, |
68c49ffa RK |
149 | MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS, |
150 | POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64}, | |
85638c0d | 151 | {"ppc604", PROCESSOR_PPC604, |
68c49ffa | 152 | MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS, |
9ad92d9b | 153 | POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64}}; |
5248c961 RK |
154 | |
155 | int ptt_size = sizeof (processor_target_table) / sizeof (struct ptt); | |
156 | ||
8a61d227 MM |
157 | int multiple = TARGET_MULTIPLE; /* save current -mmultiple/-mno-multiple status */ |
158 | ||
5248c961 RK |
159 | profile_block_flag = 0; |
160 | ||
161 | /* Identify the processor type */ | |
162 | if (rs6000_cpu_string == 0) | |
163 | rs6000_cpu = PROCESSOR_DEFAULT; | |
164 | else | |
165 | { | |
166 | for (i = 0; i < ptt_size; i++) | |
167 | if (! strcmp (rs6000_cpu_string, processor_target_table[i].name)) | |
168 | { | |
169 | rs6000_cpu = processor_target_table[i].processor; | |
170 | target_flags |= processor_target_table[i].target_enable; | |
171 | target_flags &= ~processor_target_table[i].target_disable; | |
172 | break; | |
173 | } | |
174 | ||
175 | if (i == ptt_size) | |
176 | { | |
177 | error ("bad value (%s) for -mcpu= switch", rs6000_cpu_string); | |
178 | rs6000_cpu_string = "default"; | |
179 | rs6000_cpu = PROCESSOR_DEFAULT; | |
180 | } | |
181 | } | |
8a61d227 MM |
182 | |
183 | /* If -mmultiple or -mno-multiple was explicitly used, don't | |
184 | override with the processor default */ | |
185 | if (TARGET_MULTIPLE_SET) | |
186 | target_flags = (target_flags & ~MASK_MULTIPLE) | multiple; | |
5248c961 | 187 | } |
75814ad4 MM |
188 | \f |
189 | /* Create a CONST_DOUBLE like immed_double_const, except reverse the | |
190 | two parts of the constant if the target is little endian. */ | |
191 | ||
192 | struct rtx_def *rs6000_immed_double_const (i0, i1, mode) | |
193 | HOST_WIDE_INT i0, i1; | |
194 | enum machine_mode mode; | |
195 | { | |
196 | if (! WORDS_BIG_ENDIAN) | |
197 | return immed_double_const (i1, i0, mode); | |
198 | ||
199 | return immed_double_const (i0, i1, mode); | |
200 | } | |
201 | ||
5248c961 | 202 | \f |
9878760c RK |
203 | /* Return non-zero if this function is known to have a null epilogue. */ |
204 | ||
205 | int | |
206 | direct_return () | |
207 | { | |
208 | return (reload_completed | |
209 | && first_reg_to_save () == 32 | |
210 | && first_fp_reg_to_save () == 64 | |
211 | && ! regs_ever_live[65] | |
212 | && ! rs6000_pushes_stack ()); | |
213 | } | |
214 | ||
215 | /* Returns 1 always. */ | |
216 | ||
217 | int | |
218 | any_operand (op, mode) | |
219 | register rtx op; | |
220 | enum machine_mode mode; | |
221 | { | |
222 | return 1; | |
223 | } | |
224 | ||
225 | /* Return 1 if OP is a constant that can fit in a D field. */ | |
226 | ||
227 | int | |
228 | short_cint_operand (op, mode) | |
229 | register rtx op; | |
230 | enum machine_mode mode; | |
231 | { | |
232 | return (GET_CODE (op) == CONST_INT | |
233 | && (unsigned) (INTVAL (op) + 0x8000) < 0x10000); | |
234 | } | |
235 | ||
236 | /* Similar for a unsigned D field. */ | |
237 | ||
238 | int | |
239 | u_short_cint_operand (op, mode) | |
240 | register rtx op; | |
241 | enum machine_mode mode; | |
242 | { | |
243 | return (GET_CODE (op) == CONST_INT && (INTVAL (op) & 0xffff0000) == 0); | |
244 | } | |
245 | ||
dcfedcd0 RK |
246 | /* Return 1 if OP is a CONST_INT that cannot fit in a signed D field. */ |
247 | ||
248 | int | |
249 | non_short_cint_operand (op, mode) | |
250 | register rtx op; | |
251 | enum machine_mode mode; | |
252 | { | |
253 | return (GET_CODE (op) == CONST_INT | |
254 | && (unsigned) (INTVAL (op) + 0x8000) >= 0x10000); | |
255 | } | |
256 | ||
9878760c RK |
257 | /* Returns 1 if OP is a register that is not special (i.e., not MQ, |
258 | ctr, or lr). */ | |
259 | ||
260 | int | |
cd2b37d9 | 261 | gpc_reg_operand (op, mode) |
9878760c RK |
262 | register rtx op; |
263 | enum machine_mode mode; | |
264 | { | |
265 | return (register_operand (op, mode) | |
266 | && (GET_CODE (op) != REG || REGNO (op) >= 67 || REGNO (op) < 64)); | |
267 | } | |
268 | ||
269 | /* Returns 1 if OP is either a pseudo-register or a register denoting a | |
270 | CR field. */ | |
271 | ||
272 | int | |
273 | cc_reg_operand (op, mode) | |
274 | register rtx op; | |
275 | enum machine_mode mode; | |
276 | { | |
277 | return (register_operand (op, mode) | |
278 | && (GET_CODE (op) != REG | |
279 | || REGNO (op) >= FIRST_PSEUDO_REGISTER | |
280 | || CR_REGNO_P (REGNO (op)))); | |
281 | } | |
282 | ||
283 | /* Returns 1 if OP is either a constant integer valid for a D-field or a | |
284 | non-special register. If a register, it must be in the proper mode unless | |
285 | MODE is VOIDmode. */ | |
286 | ||
287 | int | |
288 | reg_or_short_operand (op, mode) | |
289 | register rtx op; | |
290 | enum machine_mode mode; | |
291 | { | |
f5a28898 | 292 | return short_cint_operand (op, mode) || gpc_reg_operand (op, mode); |
9878760c RK |
293 | } |
294 | ||
295 | /* Similar, except check if the negation of the constant would be valid for | |
296 | a D-field. */ | |
297 | ||
298 | int | |
299 | reg_or_neg_short_operand (op, mode) | |
300 | register rtx op; | |
301 | enum machine_mode mode; | |
302 | { | |
303 | if (GET_CODE (op) == CONST_INT) | |
304 | return CONST_OK_FOR_LETTER_P (INTVAL (op), 'P'); | |
305 | ||
cd2b37d9 | 306 | return gpc_reg_operand (op, mode); |
9878760c RK |
307 | } |
308 | ||
309 | /* Return 1 if the operand is either a register or an integer whose high-order | |
310 | 16 bits are zero. */ | |
311 | ||
312 | int | |
313 | reg_or_u_short_operand (op, mode) | |
314 | register rtx op; | |
315 | enum machine_mode mode; | |
316 | { | |
317 | if (GET_CODE (op) == CONST_INT | |
318 | && (INTVAL (op) & 0xffff0000) == 0) | |
319 | return 1; | |
320 | ||
cd2b37d9 | 321 | return gpc_reg_operand (op, mode); |
9878760c RK |
322 | } |
323 | ||
324 | /* Return 1 is the operand is either a non-special register or ANY | |
325 | constant integer. */ | |
326 | ||
327 | int | |
328 | reg_or_cint_operand (op, mode) | |
329 | register rtx op; | |
330 | enum machine_mode mode; | |
331 | { | |
cd2b37d9 | 332 | return GET_CODE (op) == CONST_INT || gpc_reg_operand (op, mode); |
9878760c RK |
333 | } |
334 | ||
6f2f8311 RK |
335 | /* Return 1 if the operand is a CONST_DOUBLE and it can be put into a register |
336 | with one instruction per word. We only do this if we can safely read | |
337 | CONST_DOUBLE_{LOW,HIGH}. */ | |
9878760c RK |
338 | |
339 | int | |
340 | easy_fp_constant (op, mode) | |
341 | register rtx op; | |
342 | register enum machine_mode mode; | |
343 | { | |
344 | rtx low, high; | |
345 | ||
346 | if (GET_CODE (op) != CONST_DOUBLE | |
347 | || GET_MODE (op) != mode | |
348 | || GET_MODE_CLASS (mode) != MODE_FLOAT) | |
349 | return 0; | |
350 | ||
351 | high = operand_subword (op, 0, 0, mode); | |
352 | low = operand_subword (op, 1, 0, mode); | |
353 | ||
6f2f8311 | 354 | if (high == 0 || ! input_operand (high, word_mode)) |
9878760c RK |
355 | return 0; |
356 | ||
357 | return (mode == SFmode | |
6f2f8311 | 358 | || (low != 0 && input_operand (low, word_mode))); |
9878760c RK |
359 | } |
360 | ||
914c2e77 RK |
361 | /* Return 1 if the operand is a constant whose low-order 32 bits are |
362 | zero. */ | |
363 | ||
364 | int | |
365 | low_32_bit_operand (op, mode) | |
366 | register rtx op; | |
367 | enum machine_mode mode; | |
368 | { | |
369 | rtx low; | |
370 | ||
371 | if (GET_CODE (op) != CONST_DOUBLE && GET_CODE (op) != CONST_INT) | |
372 | return 0; | |
373 | ||
374 | low = operand_subword (op, 1, 0, mode); | |
375 | return low != 0 && GET_CODE (low) == CONST_INT && INTVAL (low) == 0; | |
376 | } | |
377 | ||
9878760c RK |
378 | /* Return 1 if the operand is either a floating-point register, a pseudo |
379 | register, or memory. */ | |
380 | ||
381 | int | |
382 | fp_reg_or_mem_operand (op, mode) | |
383 | register rtx op; | |
384 | enum machine_mode mode; | |
385 | { | |
386 | return (memory_operand (op, mode) | |
387 | || (register_operand (op, mode) | |
388 | && (GET_CODE (op) != REG | |
389 | || REGNO (op) >= FIRST_PSEUDO_REGISTER | |
390 | || FP_REGNO_P (REGNO (op))))); | |
391 | } | |
392 | ||
393 | /* Return 1 if the operand is either an easy FP constant (see above) or | |
394 | memory. */ | |
395 | ||
396 | int | |
397 | mem_or_easy_const_operand (op, mode) | |
398 | register rtx op; | |
399 | enum machine_mode mode; | |
400 | { | |
401 | return memory_operand (op, mode) || easy_fp_constant (op, mode); | |
402 | } | |
403 | ||
404 | /* Return 1 if the operand is either a non-special register or an item | |
405 | that can be used as the operand of an SI add insn. */ | |
406 | ||
407 | int | |
408 | add_operand (op, mode) | |
409 | register rtx op; | |
410 | enum machine_mode mode; | |
411 | { | |
412 | return (reg_or_short_operand (op, mode) | |
413 | || (GET_CODE (op) == CONST_INT && (INTVAL (op) & 0xffff) == 0)); | |
414 | } | |
415 | ||
dcfedcd0 RK |
416 | /* Return 1 if OP is a constant but not a valid add_operand. */ |
417 | ||
418 | int | |
419 | non_add_cint_operand (op, mode) | |
420 | register rtx op; | |
421 | enum machine_mode mode; | |
422 | { | |
423 | return (GET_CODE (op) == CONST_INT | |
424 | && (unsigned) (INTVAL (op) + 0x8000) >= 0x10000 | |
425 | && (INTVAL (op) & 0xffff) != 0); | |
426 | } | |
427 | ||
9878760c RK |
428 | /* Return 1 if the operand is a non-special register or a constant that |
429 | can be used as the operand of an OR or XOR insn on the RS/6000. */ | |
430 | ||
431 | int | |
432 | logical_operand (op, mode) | |
433 | register rtx op; | |
434 | enum machine_mode mode; | |
435 | { | |
cd2b37d9 | 436 | return (gpc_reg_operand (op, mode) |
9878760c RK |
437 | || (GET_CODE (op) == CONST_INT |
438 | && ((INTVAL (op) & 0xffff0000) == 0 | |
439 | || (INTVAL (op) & 0xffff) == 0))); | |
440 | } | |
441 | ||
dcfedcd0 RK |
442 | /* Return 1 if C is a constant that is not a logical operand (as |
443 | above). */ | |
444 | ||
445 | int | |
446 | non_logical_cint_operand (op, mode) | |
447 | register rtx op; | |
448 | enum machine_mode mode; | |
449 | { | |
450 | return (GET_CODE (op) == CONST_INT | |
451 | && (INTVAL (op) & 0xffff0000) != 0 | |
452 | && (INTVAL (op) & 0xffff) != 0); | |
453 | } | |
454 | ||
9878760c RK |
455 | /* Return 1 if C is a constant that can be encoded in a mask on the |
456 | RS/6000. It is if there are no more than two 1->0 or 0->1 transitions. | |
457 | Reject all ones and all zeros, since these should have been optimized | |
458 | away and confuse the making of MB and ME. */ | |
459 | ||
460 | int | |
461 | mask_constant (c) | |
462 | register int c; | |
463 | { | |
464 | int i; | |
465 | int last_bit_value; | |
466 | int transitions = 0; | |
467 | ||
468 | if (c == 0 || c == ~0) | |
469 | return 0; | |
470 | ||
471 | last_bit_value = c & 1; | |
472 | ||
473 | for (i = 1; i < 32; i++) | |
474 | if (((c >>= 1) & 1) != last_bit_value) | |
475 | last_bit_value ^= 1, transitions++; | |
476 | ||
477 | return transitions <= 2; | |
478 | } | |
479 | ||
480 | /* Return 1 if the operand is a constant that is a mask on the RS/6000. */ | |
481 | ||
482 | int | |
483 | mask_operand (op, mode) | |
484 | register rtx op; | |
485 | enum machine_mode mode; | |
486 | { | |
487 | return GET_CODE (op) == CONST_INT && mask_constant (INTVAL (op)); | |
488 | } | |
489 | ||
490 | /* Return 1 if the operand is either a non-special register or a | |
491 | constant that can be used as the operand of an RS/6000 logical AND insn. */ | |
492 | ||
493 | int | |
494 | and_operand (op, mode) | |
495 | register rtx op; | |
496 | enum machine_mode mode; | |
497 | { | |
498 | return (reg_or_short_operand (op, mode) | |
499 | || logical_operand (op, mode) | |
500 | || mask_operand (op, mode)); | |
501 | } | |
502 | ||
dcfedcd0 RK |
503 | /* Return 1 if the operand is a constant but not a valid operand for an AND |
504 | insn. */ | |
505 | ||
506 | int | |
507 | non_and_cint_operand (op, mode) | |
508 | register rtx op; | |
509 | enum machine_mode mode; | |
510 | { | |
511 | return GET_CODE (op) == CONST_INT && ! and_operand (op, mode); | |
512 | } | |
513 | ||
9878760c RK |
514 | /* Return 1 if the operand is a general register or memory operand. */ |
515 | ||
516 | int | |
517 | reg_or_mem_operand (op, mode) | |
518 | register rtx op; | |
519 | register enum machine_mode mode; | |
520 | { | |
cd2b37d9 | 521 | return gpc_reg_operand (op, mode) || memory_operand (op, mode); |
9878760c RK |
522 | } |
523 | ||
a7a813f7 RK |
524 | /* Return 1 if the operand is a general register or memory operand without |
525 | pre-inc or pre_dec which produces invalid form of PowerPC lwa | |
526 | instruction. */ | |
527 | ||
528 | int | |
529 | lwa_operand (op, mode) | |
530 | register rtx op; | |
531 | register enum machine_mode mode; | |
532 | { | |
533 | rtx inner = op; | |
534 | ||
535 | if (reload_completed && GET_CODE (inner) == SUBREG) | |
536 | inner = SUBREG_REG (inner); | |
537 | ||
538 | return gpc_reg_operand (inner, mode) | |
539 | || (memory_operand (inner, mode) | |
540 | && GET_CODE (XEXP (inner, 0)) != PRE_INC | |
541 | && GET_CODE (XEXP (inner, 0)) != PRE_DEC); | |
542 | } | |
543 | ||
9878760c RK |
544 | /* Return 1 if the operand, used inside a MEM, is a valid first argument |
545 | to CALL. This is a SYMBOL_REF or a pseudo-register, which will be | |
546 | forced to lr. */ | |
547 | ||
548 | int | |
549 | call_operand (op, mode) | |
550 | register rtx op; | |
551 | enum machine_mode mode; | |
552 | { | |
553 | if (mode != VOIDmode && GET_MODE (op) != mode) | |
554 | return 0; | |
555 | ||
556 | return (GET_CODE (op) == SYMBOL_REF | |
557 | || (GET_CODE (op) == REG && REGNO (op) >= FIRST_PSEUDO_REGISTER)); | |
558 | } | |
559 | ||
2af3d377 RK |
560 | |
561 | /* Return 1 if the operand is a SYMBOL_REF for a function known to be in | |
562 | this file. */ | |
563 | ||
564 | int | |
565 | current_file_function_operand (op, mode) | |
566 | register rtx op; | |
567 | enum machine_mode mode; | |
568 | { | |
569 | return (GET_CODE (op) == SYMBOL_REF | |
570 | && (SYMBOL_REF_FLAG (op) | |
571 | || op == XEXP (DECL_RTL (current_function_decl), 0))); | |
572 | } | |
573 | ||
574 | ||
9878760c RK |
575 | /* Return 1 if this operand is a valid input for a move insn. */ |
576 | ||
577 | int | |
578 | input_operand (op, mode) | |
579 | register rtx op; | |
580 | enum machine_mode mode; | |
581 | { | |
eb4e8003 | 582 | /* Memory is always valid. */ |
9878760c RK |
583 | if (memory_operand (op, mode)) |
584 | return 1; | |
585 | ||
eb4e8003 RK |
586 | /* For floating-point, easy constants are valid. */ |
587 | if (GET_MODE_CLASS (mode) == MODE_FLOAT | |
588 | && CONSTANT_P (op) | |
589 | && easy_fp_constant (op, mode)) | |
590 | return 1; | |
591 | ||
592 | /* For floating-point or multi-word mode, the only remaining valid type | |
593 | is a register. */ | |
9878760c RK |
594 | if (GET_MODE_CLASS (mode) == MODE_FLOAT |
595 | || GET_MODE_SIZE (mode) > UNITS_PER_WORD) | |
eb4e8003 | 596 | return register_operand (op, mode); |
9878760c | 597 | |
88fe15a1 RK |
598 | /* The only cases left are integral modes one word or smaller (we |
599 | do not get called for MODE_CC values). These can be in any | |
600 | register. */ | |
601 | if (register_operand (op, mode)) | |
a8b3aeda | 602 | return 1; |
88fe15a1 RK |
603 | |
604 | /* For HImode and QImode, any constant is valid. */ | |
605 | if ((mode == HImode || mode == QImode) | |
606 | && GET_CODE (op) == CONST_INT) | |
9878760c RK |
607 | return 1; |
608 | ||
84cf9dda | 609 | /* A SYMBOL_REF referring to the TOC is valid. */ |
7fec4abd | 610 | if (LEGITIMATE_CONSTANT_POOL_ADDRESS_P (op)) |
84cf9dda RK |
611 | return 1; |
612 | ||
9878760c RK |
613 | /* Otherwise, we will be doing this SET with an add, so anything valid |
614 | for an add will be valid. */ | |
615 | return add_operand (op, mode); | |
616 | } | |
617 | \f | |
618 | /* Return 1 if OP is a load multiple operation. It is known to be a | |
619 | PARALLEL and the first section will be tested. */ | |
620 | ||
621 | int | |
622 | load_multiple_operation (op, mode) | |
623 | rtx op; | |
624 | enum machine_mode mode; | |
625 | { | |
626 | int count = XVECLEN (op, 0); | |
627 | int dest_regno; | |
628 | rtx src_addr; | |
629 | int i; | |
630 | ||
631 | /* Perform a quick check so we don't blow up below. */ | |
632 | if (count <= 1 | |
633 | || GET_CODE (XVECEXP (op, 0, 0)) != SET | |
634 | || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG | |
635 | || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM) | |
636 | return 0; | |
637 | ||
638 | dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0))); | |
639 | src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0); | |
640 | ||
641 | for (i = 1; i < count; i++) | |
642 | { | |
643 | rtx elt = XVECEXP (op, 0, i); | |
644 | ||
645 | if (GET_CODE (elt) != SET | |
646 | || GET_CODE (SET_DEST (elt)) != REG | |
647 | || GET_MODE (SET_DEST (elt)) != SImode | |
648 | || REGNO (SET_DEST (elt)) != dest_regno + i | |
649 | || GET_CODE (SET_SRC (elt)) != MEM | |
650 | || GET_MODE (SET_SRC (elt)) != SImode | |
651 | || GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS | |
652 | || ! rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr) | |
653 | || GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT | |
654 | || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != i * 4) | |
655 | return 0; | |
656 | } | |
657 | ||
658 | return 1; | |
659 | } | |
660 | ||
661 | /* Similar, but tests for store multiple. Here, the second vector element | |
662 | is a CLOBBER. It will be tested later. */ | |
663 | ||
664 | int | |
665 | store_multiple_operation (op, mode) | |
666 | rtx op; | |
667 | enum machine_mode mode; | |
668 | { | |
669 | int count = XVECLEN (op, 0) - 1; | |
670 | int src_regno; | |
671 | rtx dest_addr; | |
672 | int i; | |
673 | ||
674 | /* Perform a quick check so we don't blow up below. */ | |
675 | if (count <= 1 | |
676 | || GET_CODE (XVECEXP (op, 0, 0)) != SET | |
677 | || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM | |
678 | || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG) | |
679 | return 0; | |
680 | ||
681 | src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0))); | |
682 | dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0); | |
683 | ||
684 | for (i = 1; i < count; i++) | |
685 | { | |
686 | rtx elt = XVECEXP (op, 0, i + 1); | |
687 | ||
688 | if (GET_CODE (elt) != SET | |
689 | || GET_CODE (SET_SRC (elt)) != REG | |
690 | || GET_MODE (SET_SRC (elt)) != SImode | |
691 | || REGNO (SET_SRC (elt)) != src_regno + i | |
692 | || GET_CODE (SET_DEST (elt)) != MEM | |
693 | || GET_MODE (SET_DEST (elt)) != SImode | |
694 | || GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS | |
695 | || ! rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr) | |
696 | || GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT | |
697 | || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != i * 4) | |
698 | return 0; | |
699 | } | |
700 | ||
701 | return 1; | |
702 | } | |
703 | \f | |
704 | /* Return 1 if OP is a comparison operation that is valid for a branch insn. | |
705 | We only check the opcode against the mode of the CC value here. */ | |
706 | ||
707 | int | |
708 | branch_comparison_operator (op, mode) | |
709 | register rtx op; | |
710 | enum machine_mode mode; | |
711 | { | |
712 | enum rtx_code code = GET_CODE (op); | |
713 | enum machine_mode cc_mode; | |
714 | ||
715 | if (GET_RTX_CLASS (code) != '<') | |
716 | return 0; | |
717 | ||
718 | cc_mode = GET_MODE (XEXP (op, 0)); | |
719 | if (GET_MODE_CLASS (cc_mode) != MODE_CC) | |
720 | return 0; | |
721 | ||
722 | if ((code == GT || code == LT || code == GE || code == LE) | |
723 | && cc_mode == CCUNSmode) | |
724 | return 0; | |
725 | ||
726 | if ((code == GTU || code == LTU || code == GEU || code == LEU) | |
727 | && (cc_mode != CCUNSmode)) | |
728 | return 0; | |
729 | ||
730 | return 1; | |
731 | } | |
732 | ||
733 | /* Return 1 if OP is a comparison operation that is valid for an scc insn. | |
734 | We check the opcode against the mode of the CC value and disallow EQ or | |
735 | NE comparisons for integers. */ | |
736 | ||
737 | int | |
738 | scc_comparison_operator (op, mode) | |
739 | register rtx op; | |
740 | enum machine_mode mode; | |
741 | { | |
742 | enum rtx_code code = GET_CODE (op); | |
743 | enum machine_mode cc_mode; | |
744 | ||
745 | if (GET_MODE (op) != mode && mode != VOIDmode) | |
746 | return 0; | |
747 | ||
748 | if (GET_RTX_CLASS (code) != '<') | |
749 | return 0; | |
750 | ||
751 | cc_mode = GET_MODE (XEXP (op, 0)); | |
752 | if (GET_MODE_CLASS (cc_mode) != MODE_CC) | |
753 | return 0; | |
754 | ||
755 | if (code == NE && cc_mode != CCFPmode) | |
756 | return 0; | |
757 | ||
758 | if ((code == GT || code == LT || code == GE || code == LE) | |
759 | && cc_mode == CCUNSmode) | |
760 | return 0; | |
761 | ||
762 | if ((code == GTU || code == LTU || code == GEU || code == LEU) | |
763 | && (cc_mode != CCUNSmode)) | |
764 | return 0; | |
765 | ||
c5defebb RK |
766 | if (cc_mode == CCEQmode && code != EQ && code != NE) |
767 | return 0; | |
768 | ||
9878760c RK |
769 | return 1; |
770 | } | |
771 | \f | |
772 | /* Return 1 if ANDOP is a mask that has no bits on that are not in the | |
773 | mask required to convert the result of a rotate insn into a shift | |
774 | left insn of SHIFTOP bits. Both are known to be CONST_INT. */ | |
775 | ||
776 | int | |
777 | includes_lshift_p (shiftop, andop) | |
778 | register rtx shiftop; | |
779 | register rtx andop; | |
780 | { | |
781 | int shift_mask = (~0 << INTVAL (shiftop)); | |
782 | ||
783 | return (INTVAL (andop) & ~shift_mask) == 0; | |
784 | } | |
785 | ||
786 | /* Similar, but for right shift. */ | |
787 | ||
788 | int | |
789 | includes_rshift_p (shiftop, andop) | |
790 | register rtx shiftop; | |
791 | register rtx andop; | |
792 | { | |
793 | unsigned shift_mask = ~0; | |
794 | ||
795 | shift_mask >>= INTVAL (shiftop); | |
796 | ||
797 | return (INTVAL (andop) & ~ shift_mask) == 0; | |
798 | } | |
35068b43 RK |
799 | |
800 | /* Return 1 if REGNO (reg1) == REGNO (reg2) - 1 making them candidates | |
801 | for lfq and stfq insns. | |
802 | ||
803 | Note reg1 and reg2 *must* be hard registers. To be sure we will | |
804 | abort if we are passed pseudo registers. */ | |
805 | ||
806 | int | |
807 | registers_ok_for_quad_peep (reg1, reg2) | |
808 | rtx reg1, reg2; | |
809 | { | |
810 | /* We might have been passed a SUBREG. */ | |
811 | if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG) | |
812 | return 0; | |
813 | ||
814 | return (REGNO (reg1) == REGNO (reg2) - 1); | |
815 | } | |
816 | ||
817 | /* Return 1 if addr1 and addr2 are suitable for lfq or stfq insn. addr1 and | |
818 | addr2 must be in consecutive memory locations (addr2 == addr1 + 8). */ | |
819 | ||
820 | int | |
821 | addrs_ok_for_quad_peep (addr1, addr2) | |
822 | register rtx addr1; | |
823 | register rtx addr2; | |
824 | { | |
825 | int reg1; | |
826 | int offset1; | |
827 | ||
828 | /* Extract an offset (if used) from the first addr. */ | |
829 | if (GET_CODE (addr1) == PLUS) | |
830 | { | |
831 | /* If not a REG, return zero. */ | |
832 | if (GET_CODE (XEXP (addr1, 0)) != REG) | |
833 | return 0; | |
834 | else | |
835 | { | |
836 | reg1 = REGNO (XEXP (addr1, 0)); | |
837 | /* The offset must be constant! */ | |
838 | if (GET_CODE (XEXP (addr1, 1)) != CONST_INT) | |
839 | return 0; | |
840 | offset1 = INTVAL (XEXP (addr1, 1)); | |
841 | } | |
842 | } | |
843 | else if (GET_CODE (addr1) != REG) | |
844 | return 0; | |
845 | else | |
846 | { | |
847 | reg1 = REGNO (addr1); | |
848 | /* This was a simple (mem (reg)) expression. Offset is 0. */ | |
849 | offset1 = 0; | |
850 | } | |
851 | ||
852 | /* Make sure the second address is a (mem (plus (reg) (const_int). */ | |
853 | if (GET_CODE (addr2) != PLUS) | |
854 | return 0; | |
855 | ||
856 | if (GET_CODE (XEXP (addr2, 0)) != REG | |
857 | || GET_CODE (XEXP (addr2, 1)) != CONST_INT) | |
858 | return 0; | |
859 | ||
860 | if (reg1 != REGNO (XEXP (addr2, 0))) | |
861 | return 0; | |
862 | ||
863 | /* The offset for the second addr must be 8 more than the first addr. */ | |
864 | if (INTVAL (XEXP (addr2, 1)) != offset1 + 8) | |
865 | return 0; | |
866 | ||
867 | /* All the tests passed. addr1 and addr2 are valid for lfq or stfq | |
868 | instructions. */ | |
869 | return 1; | |
870 | } | |
9878760c RK |
871 | \f |
872 | /* Return the register class of a scratch register needed to copy IN into | |
873 | or out of a register in CLASS in MODE. If it can be done directly, | |
874 | NO_REGS is returned. */ | |
875 | ||
876 | enum reg_class | |
877 | secondary_reload_class (class, mode, in) | |
878 | enum reg_class class; | |
879 | enum machine_mode mode; | |
880 | rtx in; | |
881 | { | |
882 | int regno = true_regnum (in); | |
883 | ||
884 | if (regno >= FIRST_PSEUDO_REGISTER) | |
885 | regno = -1; | |
886 | ||
887 | /* We can place anything into GENERAL_REGS and can put GENERAL_REGS | |
888 | into anything. */ | |
889 | if (class == GENERAL_REGS || class == BASE_REGS | |
890 | || (regno >= 0 && INT_REGNO_P (regno))) | |
891 | return NO_REGS; | |
892 | ||
893 | /* Constants, memory, and FP registers can go into FP registers. */ | |
894 | if ((regno == -1 || FP_REGNO_P (regno)) | |
895 | && (class == FLOAT_REGS || class == NON_SPECIAL_REGS)) | |
896 | return NO_REGS; | |
897 | ||
898 | /* We can copy among the CR registers. */ | |
899 | if ((class == CR_REGS || class == CR0_REGS) | |
900 | && regno >= 0 && CR_REGNO_P (regno)) | |
901 | return NO_REGS; | |
902 | ||
903 | /* Otherwise, we need GENERAL_REGS. */ | |
904 | return GENERAL_REGS; | |
905 | } | |
906 | \f | |
907 | /* Given a comparison operation, return the bit number in CCR to test. We | |
908 | know this is a valid comparison. | |
909 | ||
910 | SCC_P is 1 if this is for an scc. That means that %D will have been | |
911 | used instead of %C, so the bits will be in different places. | |
912 | ||
b4ac57ab | 913 | Return -1 if OP isn't a valid comparison for some reason. */ |
9878760c RK |
914 | |
915 | int | |
916 | ccr_bit (op, scc_p) | |
917 | register rtx op; | |
918 | int scc_p; | |
919 | { | |
920 | enum rtx_code code = GET_CODE (op); | |
921 | enum machine_mode cc_mode; | |
922 | int cc_regnum; | |
923 | int base_bit; | |
924 | ||
925 | if (GET_RTX_CLASS (code) != '<') | |
926 | return -1; | |
927 | ||
928 | cc_mode = GET_MODE (XEXP (op, 0)); | |
929 | cc_regnum = REGNO (XEXP (op, 0)); | |
930 | base_bit = 4 * (cc_regnum - 68); | |
931 | ||
c5defebb RK |
932 | /* In CCEQmode cases we have made sure that the result is always in the |
933 | third bit of the CR field. */ | |
934 | ||
935 | if (cc_mode == CCEQmode) | |
936 | return base_bit + 3; | |
937 | ||
9878760c RK |
938 | switch (code) |
939 | { | |
940 | case NE: | |
941 | return scc_p ? base_bit + 3 : base_bit + 2; | |
942 | case EQ: | |
943 | return base_bit + 2; | |
944 | case GT: case GTU: | |
945 | return base_bit + 1; | |
946 | case LT: case LTU: | |
947 | return base_bit; | |
948 | ||
949 | case GE: case GEU: | |
950 | /* If floating-point, we will have done a cror to put the bit in the | |
951 | unordered position. So test that bit. For integer, this is ! LT | |
952 | unless this is an scc insn. */ | |
953 | return cc_mode == CCFPmode || scc_p ? base_bit + 3 : base_bit; | |
954 | ||
955 | case LE: case LEU: | |
956 | return cc_mode == CCFPmode || scc_p ? base_bit + 3 : base_bit + 1; | |
957 | ||
958 | default: | |
959 | abort (); | |
960 | } | |
961 | } | |
962 | \f | |
963 | /* Print an operand. Recognize special options, documented below. */ | |
964 | ||
965 | void | |
966 | print_operand (file, x, code) | |
967 | FILE *file; | |
968 | rtx x; | |
969 | char code; | |
970 | { | |
971 | int i; | |
972 | int val; | |
973 | ||
974 | /* These macros test for integers and extract the low-order bits. */ | |
975 | #define INT_P(X) \ | |
976 | ((GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST_DOUBLE) \ | |
977 | && GET_MODE (X) == VOIDmode) | |
978 | ||
979 | #define INT_LOWPART(X) \ | |
980 | (GET_CODE (X) == CONST_INT ? INTVAL (X) : CONST_DOUBLE_LOW (X)) | |
981 | ||
982 | switch (code) | |
983 | { | |
a8b3aeda | 984 | case '.': |
a85d226b RK |
985 | /* Write out an instruction after the call which may be replaced |
986 | with glue code by the loader. This depends on the AIX version. */ | |
987 | asm_fprintf (file, RS6000_CALL_GLUE); | |
a8b3aeda RK |
988 | return; |
989 | ||
cfaaaf2e RK |
990 | case '*': |
991 | /* Write the register number of the TOC register. */ | |
992 | fputs (TARGET_MINIMAL_TOC ? "30" : "2", file); | |
993 | return; | |
994 | ||
9854d9ed RK |
995 | case 'A': |
996 | /* If X is a constant integer whose low-order 5 bits are zero, | |
997 | write 'l'. Otherwise, write 'r'. This is a kludge to fix a bug | |
76229ac8 | 998 | in the AIX assembler where "sri" with a zero shift count |
9854d9ed RK |
999 | write a trash instruction. */ |
1000 | if (GET_CODE (x) == CONST_INT && (INTVAL (x) & 31) == 0) | |
76229ac8 | 1001 | putc ('l', file); |
9854d9ed | 1002 | else |
76229ac8 | 1003 | putc ('r', file); |
9854d9ed RK |
1004 | return; |
1005 | ||
1006 | case 'b': | |
1007 | /* Low-order 16 bits of constant, unsigned. */ | |
cad12a8d | 1008 | if (! INT_P (x)) |
9854d9ed | 1009 | output_operand_lossage ("invalid %%b value"); |
cad12a8d | 1010 | |
9854d9ed | 1011 | fprintf (file, "%d", INT_LOWPART (x) & 0xffff); |
cad12a8d RK |
1012 | return; |
1013 | ||
9854d9ed RK |
1014 | case 'C': |
1015 | /* This is an optional cror needed for LE or GE floating-point | |
1016 | comparisons. Otherwise write nothing. */ | |
1017 | if ((GET_CODE (x) == LE || GET_CODE (x) == GE) | |
1018 | && GET_MODE (XEXP (x, 0)) == CCFPmode) | |
1019 | { | |
1020 | int base_bit = 4 * (REGNO (XEXP (x, 0)) - 68); | |
1021 | ||
1022 | fprintf (file, "cror %d,%d,%d\n\t", base_bit + 3, | |
1023 | base_bit + 2, base_bit + (GET_CODE (x) == GE)); | |
1024 | } | |
1025 | return; | |
1026 | ||
1027 | case 'D': | |
1028 | /* Similar, except that this is for an scc, so we must be able to | |
1029 | encode the test in a single bit that is one. We do the above | |
1030 | for any LE, GE, GEU, or LEU and invert the bit for NE. */ | |
1031 | if (GET_CODE (x) == LE || GET_CODE (x) == GE | |
1032 | || GET_CODE (x) == LEU || GET_CODE (x) == GEU) | |
1033 | { | |
1034 | int base_bit = 4 * (REGNO (XEXP (x, 0)) - 68); | |
1035 | ||
1036 | fprintf (file, "cror %d,%d,%d\n\t", base_bit + 3, | |
1037 | base_bit + 2, | |
1038 | base_bit + (GET_CODE (x) == GE || GET_CODE (x) == GEU)); | |
1039 | } | |
1040 | ||
1041 | else if (GET_CODE (x) == NE) | |
1042 | { | |
1043 | int base_bit = 4 * (REGNO (XEXP (x, 0)) - 68); | |
1044 | ||
1045 | fprintf (file, "crnor %d,%d,%d\n\t", base_bit + 3, | |
1046 | base_bit + 2, base_bit + 2); | |
1047 | } | |
1048 | return; | |
1049 | ||
1050 | case 'E': | |
1051 | /* X is a CR register. Print the number of the third bit of the CR */ | |
1052 | if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x))) | |
1053 | output_operand_lossage ("invalid %%E value"); | |
1054 | ||
1055 | fprintf(file, "%d", 4 * (REGNO (x) - 68) + 3); | |
a85d226b | 1056 | return; |
9854d9ed RK |
1057 | |
1058 | case 'f': | |
1059 | /* X is a CR register. Print the shift count needed to move it | |
1060 | to the high-order four bits. */ | |
1061 | if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x))) | |
1062 | output_operand_lossage ("invalid %%f value"); | |
1063 | else | |
1064 | fprintf (file, "%d", 4 * (REGNO (x) - 68)); | |
1065 | return; | |
1066 | ||
1067 | case 'F': | |
1068 | /* Similar, but print the count for the rotate in the opposite | |
1069 | direction. */ | |
1070 | if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x))) | |
1071 | output_operand_lossage ("invalid %%F value"); | |
1072 | else | |
1073 | fprintf (file, "%d", 32 - 4 * (REGNO (x) - 68)); | |
1074 | return; | |
1075 | ||
1076 | case 'G': | |
1077 | /* X is a constant integer. If it is negative, print "m", | |
1078 | otherwise print "z". This is to make a aze or ame insn. */ | |
1079 | if (GET_CODE (x) != CONST_INT) | |
1080 | output_operand_lossage ("invalid %%G value"); | |
1081 | else if (INTVAL (x) >= 0) | |
76229ac8 | 1082 | putc ('z', file); |
9854d9ed | 1083 | else |
76229ac8 | 1084 | putc ('m', file); |
9854d9ed RK |
1085 | return; |
1086 | ||
9878760c | 1087 | case 'h': |
df3d94ed RK |
1088 | /* If constant, output low-order five bits. Otherwise, |
1089 | write normally. */ | |
9878760c RK |
1090 | if (INT_P (x)) |
1091 | fprintf (file, "%d", INT_LOWPART (x) & 31); | |
1092 | else | |
1093 | print_operand (file, x, 0); | |
1094 | return; | |
1095 | ||
9854d9ed RK |
1096 | case 'I': |
1097 | /* Print `i' if this is a constant, else nothing. */ | |
9878760c | 1098 | if (INT_P (x)) |
76229ac8 | 1099 | putc ('i', file); |
9878760c RK |
1100 | return; |
1101 | ||
9854d9ed RK |
1102 | case 'j': |
1103 | /* Write the bit number in CCR for jump. */ | |
1104 | i = ccr_bit (x, 0); | |
1105 | if (i == -1) | |
1106 | output_operand_lossage ("invalid %%j code"); | |
9878760c | 1107 | else |
9854d9ed | 1108 | fprintf (file, "%d", i); |
9878760c RK |
1109 | return; |
1110 | ||
9854d9ed RK |
1111 | case 'J': |
1112 | /* Similar, but add one for shift count in rlinm for scc and pass | |
1113 | scc flag to `ccr_bit'. */ | |
1114 | i = ccr_bit (x, 1); | |
1115 | if (i == -1) | |
1116 | output_operand_lossage ("invalid %%J code"); | |
1117 | else | |
a0466a68 RK |
1118 | /* If we want bit 31, write a shift count of zero, not 32. */ |
1119 | fprintf (file, "%d", i == 31 ? 0 : i + 1); | |
9878760c RK |
1120 | return; |
1121 | ||
9854d9ed RK |
1122 | case 'k': |
1123 | /* X must be a constant. Write the 1's complement of the | |
1124 | constant. */ | |
9878760c | 1125 | if (! INT_P (x)) |
9854d9ed | 1126 | output_operand_lossage ("invalid %%k value"); |
9878760c | 1127 | |
9854d9ed | 1128 | fprintf (file, "%d", ~ INT_LOWPART (x)); |
9878760c RK |
1129 | return; |
1130 | ||
9854d9ed RK |
1131 | case 'L': |
1132 | /* Write second word of DImode or DFmode reference. Works on register | |
1133 | or non-indexed memory only. */ | |
1134 | if (GET_CODE (x) == REG) | |
1135 | fprintf (file, "%d", REGNO (x) + 1); | |
1136 | else if (GET_CODE (x) == MEM) | |
1137 | { | |
1138 | /* Handle possible auto-increment. Since it is pre-increment and | |
1139 | we have already done it, we can just use an offset of four. */ | |
1140 | if (GET_CODE (XEXP (x, 0)) == PRE_INC | |
1141 | || GET_CODE (XEXP (x, 0)) == PRE_DEC) | |
1142 | output_address (plus_constant (XEXP (XEXP (x, 0), 0), 4)); | |
1143 | else | |
1144 | output_address (plus_constant (XEXP (x, 0), 4)); | |
1145 | } | |
9878760c | 1146 | return; |
9854d9ed | 1147 | |
9878760c RK |
1148 | case 'm': |
1149 | /* MB value for a mask operand. */ | |
1150 | if (! mask_operand (x, VOIDmode)) | |
1151 | output_operand_lossage ("invalid %%m value"); | |
1152 | ||
1153 | val = INT_LOWPART (x); | |
1154 | ||
1155 | /* If the high bit is set and the low bit is not, the value is zero. | |
1156 | If the high bit is zero, the value is the first 1 bit we find from | |
1157 | the left. */ | |
1158 | if (val < 0 && (val & 1) == 0) | |
1159 | { | |
1160 | fprintf (file, "0"); | |
1161 | return; | |
1162 | } | |
1163 | else if (val >= 0) | |
1164 | { | |
1165 | for (i = 1; i < 32; i++) | |
1166 | if ((val <<= 1) < 0) | |
1167 | break; | |
1168 | fprintf (file, "%d", i); | |
1169 | return; | |
1170 | } | |
1171 | ||
1172 | /* Otherwise, look for the first 0 bit from the right. The result is its | |
1173 | number plus 1. We know the low-order bit is one. */ | |
1174 | for (i = 0; i < 32; i++) | |
1175 | if (((val >>= 1) & 1) == 0) | |
1176 | break; | |
1177 | ||
1178 | /* If we ended in ...01, I would be 0. The correct value is 31, so | |
1179 | we want 31 - i. */ | |
1180 | fprintf (file, "%d", 31 - i); | |
1181 | return; | |
1182 | ||
1183 | case 'M': | |
1184 | /* ME value for a mask operand. */ | |
1185 | if (! mask_operand (x, VOIDmode)) | |
1186 | output_operand_lossage ("invalid %%m value"); | |
1187 | ||
1188 | val = INT_LOWPART (x); | |
1189 | ||
1190 | /* If the low bit is set and the high bit is not, the value is 31. | |
1191 | If the low bit is zero, the value is the first 1 bit we find from | |
1192 | the right. */ | |
1193 | if ((val & 1) && val >= 0) | |
1194 | { | |
76229ac8 | 1195 | fputs ("31", file); |
9878760c RK |
1196 | return; |
1197 | } | |
1198 | else if ((val & 1) == 0) | |
1199 | { | |
1200 | for (i = 0; i < 32; i++) | |
1201 | if ((val >>= 1) & 1) | |
1202 | break; | |
1203 | ||
1204 | /* If we had ....10, I would be 0. The result should be | |
1205 | 30, so we need 30 - i. */ | |
1206 | fprintf (file, "%d", 30 - i); | |
1207 | return; | |
1208 | } | |
1209 | ||
1210 | /* Otherwise, look for the first 0 bit from the left. The result is its | |
1211 | number minus 1. We know the high-order bit is one. */ | |
1212 | for (i = 0; i < 32; i++) | |
1213 | if ((val <<= 1) >= 0) | |
1214 | break; | |
1215 | ||
1216 | fprintf (file, "%d", i); | |
1217 | return; | |
1218 | ||
9878760c RK |
1219 | case 'N': |
1220 | /* Write the number of elements in the vector times 4. */ | |
1221 | if (GET_CODE (x) != PARALLEL) | |
1222 | output_operand_lossage ("invalid %%N value"); | |
1223 | ||
1224 | fprintf (file, "%d", XVECLEN (x, 0) * 4); | |
1225 | return; | |
1226 | ||
1227 | case 'O': | |
1228 | /* Similar, but subtract 1 first. */ | |
1229 | if (GET_CODE (x) != PARALLEL) | |
1230 | output_operand_lossage ("invalid %%N value"); | |
1231 | ||
1232 | fprintf (file, "%d", (XVECLEN (x, 0) - 1) * 4); | |
1233 | return; | |
1234 | ||
9854d9ed RK |
1235 | case 'p': |
1236 | /* X is a CONST_INT that is a power of two. Output the logarithm. */ | |
1237 | if (! INT_P (x) | |
1238 | || (i = exact_log2 (INT_LOWPART (x))) < 0) | |
1239 | output_operand_lossage ("invalid %%p value"); | |
1240 | ||
1241 | fprintf (file, "%d", i); | |
1242 | return; | |
1243 | ||
9878760c RK |
1244 | case 'P': |
1245 | /* The operand must be an indirect memory reference. The result | |
1246 | is the register number. */ | |
1247 | if (GET_CODE (x) != MEM || GET_CODE (XEXP (x, 0)) != REG | |
1248 | || REGNO (XEXP (x, 0)) >= 32) | |
1249 | output_operand_lossage ("invalid %%P value"); | |
1250 | ||
1251 | fprintf (file, "%d", REGNO (XEXP (x, 0))); | |
1252 | return; | |
1253 | ||
9854d9ed RK |
1254 | case 'R': |
1255 | /* X is a CR register. Print the mask for `mtcrf'. */ | |
1256 | if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x))) | |
1257 | output_operand_lossage ("invalid %%R value"); | |
1258 | else | |
1259 | fprintf (file, "%d", 128 >> (REGNO (x) - 68)); | |
9878760c | 1260 | return; |
9854d9ed RK |
1261 | |
1262 | case 's': | |
1263 | /* Low 5 bits of 32 - value */ | |
1264 | if (! INT_P (x)) | |
1265 | output_operand_lossage ("invalid %%s value"); | |
1266 | ||
1267 | fprintf (file, "%d", (32 - INT_LOWPART (x)) & 31); | |
9878760c | 1268 | return; |
9854d9ed | 1269 | |
9878760c RK |
1270 | case 't': |
1271 | /* Write 12 if this jump operation will branch if true, 4 otherwise. | |
1272 | All floating-point operations except NE branch true and integer | |
1273 | EQ, LT, GT, LTU and GTU also branch true. */ | |
1274 | if (GET_RTX_CLASS (GET_CODE (x)) != '<') | |
1275 | output_operand_lossage ("invalid %%t value"); | |
1276 | ||
1277 | else if ((GET_MODE (XEXP (x, 0)) == CCFPmode | |
1278 | && GET_CODE (x) != NE) | |
1279 | || GET_CODE (x) == EQ | |
1280 | || GET_CODE (x) == LT || GET_CODE (x) == GT | |
1281 | || GET_CODE (x) == LTU || GET_CODE (x) == GTU) | |
76229ac8 | 1282 | fputs ("12", file); |
9878760c | 1283 | else |
76229ac8 | 1284 | putc ('4', file); |
9878760c RK |
1285 | return; |
1286 | ||
1287 | case 'T': | |
1288 | /* Opposite of 't': write 4 if this jump operation will branch if true, | |
1289 | 12 otherwise. */ | |
1290 | if (GET_RTX_CLASS (GET_CODE (x)) != '<') | |
1291 | output_operand_lossage ("invalid %%t value"); | |
1292 | ||
1293 | else if ((GET_MODE (XEXP (x, 0)) == CCFPmode | |
1294 | && GET_CODE (x) != NE) | |
1295 | || GET_CODE (x) == EQ | |
1296 | || GET_CODE (x) == LT || GET_CODE (x) == GT | |
1297 | || GET_CODE (x) == LTU || GET_CODE (x) == GTU) | |
76229ac8 | 1298 | putc ('4', file); |
9878760c | 1299 | else |
76229ac8 | 1300 | fputs ("12", file); |
9878760c RK |
1301 | return; |
1302 | ||
9854d9ed RK |
1303 | case 'u': |
1304 | /* High-order 16 bits of constant. */ | |
1305 | if (! INT_P (x)) | |
1306 | output_operand_lossage ("invalid %%u value"); | |
9878760c | 1307 | |
76229ac8 | 1308 | fprintf (file, "0x%x", (INT_LOWPART (x) >> 16) & 0xffff); |
9878760c RK |
1309 | return; |
1310 | ||
9854d9ed RK |
1311 | case 'U': |
1312 | /* Print `u' if this has an auto-increment or auto-decrement. */ | |
1313 | if (GET_CODE (x) == MEM | |
1314 | && (GET_CODE (XEXP (x, 0)) == PRE_INC | |
1315 | || GET_CODE (XEXP (x, 0)) == PRE_DEC)) | |
76229ac8 | 1316 | putc ('u', file); |
9854d9ed | 1317 | return; |
9878760c | 1318 | |
9854d9ed RK |
1319 | case 'w': |
1320 | /* If constant, low-order 16 bits of constant, signed. Otherwise, write | |
1321 | normally. */ | |
1322 | if (INT_P (x)) | |
1323 | fprintf (file, "%d", | |
1324 | (INT_LOWPART (x) & 0xffff) - 2 * (INT_LOWPART (x) & 0x8000)); | |
1325 | else | |
1326 | print_operand (file, x, 0); | |
9878760c RK |
1327 | return; |
1328 | ||
9854d9ed RK |
1329 | case 'W': |
1330 | /* If constant, low-order 16 bits of constant, unsigned. | |
1331 | Otherwise, write normally. */ | |
1332 | if (INT_P (x)) | |
1333 | fprintf (file, "%d", INT_LOWPART (x) & 0xffff); | |
1334 | else | |
1335 | print_operand (file, x, 0); | |
1336 | return; | |
9878760c | 1337 | |
9854d9ed RK |
1338 | case 'X': |
1339 | if (GET_CODE (x) == MEM | |
1340 | && LEGITIMATE_INDEXED_ADDRESS_P (XEXP (x, 0))) | |
76229ac8 | 1341 | putc ('x', file); |
9854d9ed | 1342 | return; |
9878760c | 1343 | |
9854d9ed RK |
1344 | case 'Y': |
1345 | /* Like 'L', for third word of TImode */ | |
1346 | if (GET_CODE (x) == REG) | |
1347 | fprintf (file, "%d", REGNO (x) + 2); | |
1348 | else if (GET_CODE (x) == MEM) | |
9878760c | 1349 | { |
9854d9ed RK |
1350 | if (GET_CODE (XEXP (x, 0)) == PRE_INC |
1351 | || GET_CODE (XEXP (x, 0)) == PRE_DEC) | |
1352 | output_address (plus_constant (XEXP (XEXP (x, 0), 0), 8)); | |
1353 | else | |
1354 | output_address (plus_constant (XEXP (x, 0), 8)); | |
9878760c RK |
1355 | } |
1356 | return; | |
9854d9ed | 1357 | |
9878760c | 1358 | case 'z': |
b4ac57ab RS |
1359 | /* X is a SYMBOL_REF. Write out the name preceded by a |
1360 | period and without any trailing data in brackets. Used for function | |
4d30c363 MM |
1361 | names. If we are configured for System V (or the embedded ABI) on |
1362 | the PowerPC, do not emit the period, since those systems do not use | |
1363 | TOCs and the like. */ | |
9878760c RK |
1364 | if (GET_CODE (x) != SYMBOL_REF) |
1365 | abort (); | |
1366 | ||
4d30c363 | 1367 | #ifndef USING_SVR4_H |
76229ac8 | 1368 | putc ('.', file); |
4d30c363 | 1369 | #endif |
9878760c RK |
1370 | RS6000_OUTPUT_BASENAME (file, XSTR (x, 0)); |
1371 | return; | |
1372 | ||
9854d9ed RK |
1373 | case 'Z': |
1374 | /* Like 'L', for last word of TImode. */ | |
1375 | if (GET_CODE (x) == REG) | |
1376 | fprintf (file, "%d", REGNO (x) + 3); | |
1377 | else if (GET_CODE (x) == MEM) | |
1378 | { | |
1379 | if (GET_CODE (XEXP (x, 0)) == PRE_INC | |
1380 | || GET_CODE (XEXP (x, 0)) == PRE_DEC) | |
1381 | output_address (plus_constant (XEXP (XEXP (x, 0), 0), 12)); | |
1382 | else | |
1383 | output_address (plus_constant (XEXP (x, 0), 12)); | |
1384 | } | |
5c23c401 | 1385 | return; |
9854d9ed | 1386 | |
9878760c RK |
1387 | case 0: |
1388 | if (GET_CODE (x) == REG) | |
1389 | fprintf (file, "%s", reg_names[REGNO (x)]); | |
1390 | else if (GET_CODE (x) == MEM) | |
1391 | { | |
1392 | /* We need to handle PRE_INC and PRE_DEC here, since we need to | |
1393 | know the width from the mode. */ | |
1394 | if (GET_CODE (XEXP (x, 0)) == PRE_INC) | |
1395 | fprintf (file, "%d(%d)", GET_MODE_SIZE (GET_MODE (x)), | |
1396 | REGNO (XEXP (XEXP (x, 0), 0))); | |
1397 | else if (GET_CODE (XEXP (x, 0)) == PRE_DEC) | |
1398 | fprintf (file, "%d(%d)", - GET_MODE_SIZE (GET_MODE (x)), | |
1399 | REGNO (XEXP (XEXP (x, 0), 0))); | |
1400 | else | |
1401 | output_address (XEXP (x, 0)); | |
1402 | } | |
1403 | else | |
1404 | output_addr_const (file, x); | |
a85d226b | 1405 | return; |
9878760c RK |
1406 | |
1407 | default: | |
1408 | output_operand_lossage ("invalid %%xn code"); | |
1409 | } | |
1410 | } | |
1411 | \f | |
1412 | /* Print the address of an operand. */ | |
1413 | ||
1414 | void | |
1415 | print_operand_address (file, x) | |
1416 | FILE *file; | |
1417 | register rtx x; | |
1418 | { | |
1419 | if (GET_CODE (x) == REG) | |
1420 | fprintf (file, "0(%d)", REGNO (x)); | |
1421 | else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST) | |
1422 | { | |
1423 | output_addr_const (file, x); | |
1875cc88 JW |
1424 | /* When TARGET_MINIMAL_TOC, use the indirected toc table pointer instead |
1425 | of the toc pointer. */ | |
1426 | if (TARGET_MINIMAL_TOC) | |
1427 | fprintf (file, "(30)"); | |
1428 | else | |
1429 | fprintf (file, "(2)"); | |
9878760c RK |
1430 | } |
1431 | else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == REG) | |
1432 | { | |
1433 | if (REGNO (XEXP (x, 0)) == 0) | |
1434 | fprintf (file, "%d,%d", REGNO (XEXP (x, 1)), REGNO (XEXP (x, 0))); | |
1435 | else | |
1436 | fprintf (file, "%d,%d", REGNO (XEXP (x, 0)), REGNO (XEXP (x, 1))); | |
1437 | } | |
1438 | else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT) | |
1439 | fprintf (file, "%d(%d)", INTVAL (XEXP (x, 1)), REGNO (XEXP (x, 0))); | |
1440 | else | |
1441 | abort (); | |
1442 | } | |
1443 | \f | |
1444 | /* This page contains routines that are used to determine what the function | |
1445 | prologue and epilogue code will do and write them out. */ | |
1446 | ||
1447 | /* Return the first fixed-point register that is required to be saved. 32 if | |
1448 | none. */ | |
1449 | ||
1450 | int | |
1451 | first_reg_to_save () | |
1452 | { | |
1453 | int first_reg; | |
1454 | ||
1455 | /* Find lowest numbered live register. */ | |
1456 | for (first_reg = 13; first_reg <= 31; first_reg++) | |
1457 | if (regs_ever_live[first_reg]) | |
1458 | break; | |
1459 | ||
e165f3f0 RK |
1460 | /* If profiling, then we must save/restore every register that contains |
1461 | a parameter before/after the .mcount call. Use registers from 30 down | |
1462 | to 23 to do this. Don't use the frame pointer in reg 31. | |
1463 | ||
1464 | For now, save enough room for all of the parameter registers. */ | |
1465 | if (profile_flag) | |
1466 | if (first_reg > 23) | |
1467 | first_reg = 23; | |
1468 | ||
9878760c RK |
1469 | return first_reg; |
1470 | } | |
1471 | ||
1472 | /* Similar, for FP regs. */ | |
1473 | ||
1474 | int | |
1475 | first_fp_reg_to_save () | |
1476 | { | |
1477 | int first_reg; | |
1478 | ||
1479 | /* Find lowest numbered live register. */ | |
1480 | for (first_reg = 14 + 32; first_reg <= 63; first_reg++) | |
1481 | if (regs_ever_live[first_reg]) | |
1482 | break; | |
1483 | ||
1484 | return first_reg; | |
1485 | } | |
1486 | ||
1487 | /* Return 1 if we need to save CR. */ | |
1488 | ||
1489 | int | |
1490 | must_save_cr () | |
1491 | { | |
1492 | return regs_ever_live[70] || regs_ever_live[71] || regs_ever_live[72]; | |
1493 | } | |
1494 | ||
1495 | /* Compute the size of the save area in the stack, including the space for | |
1496 | the fixed area. */ | |
1497 | ||
1498 | int | |
1499 | rs6000_sa_size () | |
1500 | { | |
1501 | int size; | |
9878760c RK |
1502 | |
1503 | /* We have the six fixed words, plus the size of the register save | |
1504 | areas, rounded to a double-word. */ | |
1505 | size = 6 + (32 - first_reg_to_save ()) + (64 - first_fp_reg_to_save ()) * 2; | |
1506 | if (size & 1) | |
1507 | size++; | |
1508 | ||
1509 | return size * 4; | |
1510 | } | |
1511 | ||
1512 | /* Return non-zero if this function makes calls. */ | |
1513 | ||
1514 | int | |
1515 | rs6000_makes_calls () | |
1516 | { | |
1517 | rtx insn; | |
1518 | ||
0c61c946 RK |
1519 | /* If we are profiling, we will be making a call to mcount. */ |
1520 | if (profile_flag) | |
1521 | return 1; | |
1522 | ||
9878760c RK |
1523 | for (insn = get_insns (); insn; insn = next_insn (insn)) |
1524 | if (GET_CODE (insn) == CALL_INSN) | |
1525 | return 1; | |
1526 | ||
1527 | return 0; | |
1528 | } | |
1529 | ||
1530 | /* Return non-zero if this function needs to push space on the stack. */ | |
1531 | ||
1532 | int | |
1533 | rs6000_pushes_stack () | |
1534 | { | |
1535 | int total_size = (rs6000_sa_size () + get_frame_size () | |
1536 | + current_function_outgoing_args_size); | |
1537 | ||
1538 | /* We need to push the stack if a frame pointer is needed (because the | |
1539 | stack might be dynamically adjusted), if we are debugging, if the | |
1540 | total stack size is more than 220 bytes, or if we make calls. */ | |
1541 | ||
1542 | return (frame_pointer_needed || write_symbols != NO_DEBUG | |
1543 | || total_size > 220 | |
1544 | || rs6000_makes_calls ()); | |
1545 | } | |
1546 | ||
4d30c363 MM |
1547 | #ifdef USING_SVR4_H |
1548 | /* Write out a System V.4 style traceback table before the prologue | |
1549 | ||
1550 | At present, only emit the basic tag table (ie, do not emit tag_types other | |
1551 | than 0, which might use more than 1 tag word). | |
1552 | ||
1553 | The first tag word looks like: | |
1554 | ||
1555 | 0 1 2 3 | |
1556 | 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 | |
1557 | +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | |
1558 | | 0 |ver| tag |e|s| alloca | # fprs | # gprs |s|l|c|f| | |
1559 | +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | |
1560 | ||
1561 | */ | |
1562 | ||
1563 | void | |
1564 | svr4_traceback (file, name, decl) | |
1565 | FILE *file; | |
1566 | tree name, decl; | |
1567 | { | |
1568 | ||
1569 | int first_reg = first_reg_to_save (); | |
1570 | int first_fp_reg = first_fp_reg_to_save (); | |
1571 | int pushes_stack = rs6000_pushes_stack (); | |
1572 | long tag; | |
1573 | long version = 0; /* version number */ | |
1574 | long tag_type = 0; /* function type */ | |
1575 | long extended_tag = 0; /* additional tag words needed */ | |
1576 | long spare = 0; /* reserved for future use */ | |
1577 | long alloca_reg; /* stack/frame register */ | |
1578 | long fpr_max = 64 - first_fp_reg; /* # of floating point registers saved */ | |
1579 | long gpr_max = 32 - first_reg; /* # of general purpose registers saved */ | |
ddd5a7c1 | 1580 | long sp_max; /* 1 if the function acquires a stack frame */ |
4d30c363 MM |
1581 | long lr_max; /* 1 if the function stores the link register */ |
1582 | long cr_max; /* 1 if the function has a CR save word */ | |
1583 | long fpscr_max = 0; /* 1 if the function has a FPSCR save word */ | |
1584 | ||
1585 | if (frame_pointer_needed) | |
1586 | alloca_reg = 31; | |
1587 | ||
1588 | else if (pushes_stack != 0) | |
1589 | alloca_reg = 1; | |
1590 | ||
1591 | else | |
1592 | alloca_reg = 0; | |
1593 | ||
1594 | lr_max = (regs_ever_live[65] || first_fp_reg < 62 || profile_flag); | |
1595 | cr_max = (must_save_cr () != 0); | |
1596 | sp_max = (pushes_stack != 0); | |
1597 | ||
1598 | tag = (((version & 3) << 24) | |
1599 | | ((tag_type & 7) << 21) | |
1600 | | ((extended_tag & 1) << 20) | |
1601 | | ((spare & 1) << 19) | |
1602 | | ((alloca_reg & 0x1f) << 14) | |
1603 | | ((fpr_max & 0x1f) << 9) | |
1604 | | ((gpr_max & 0x1f) << 4) | |
1605 | | ((sp_max & 1) << 3) | |
1606 | | ((lr_max & 1) << 2) | |
1607 | | ((cr_max & 1) << 1) | |
1608 | | ((fpscr_max & 1) << 0)); | |
1609 | ||
1610 | fprintf (file, "\t.long 0x%lx\n", tag); | |
1611 | } | |
1612 | ||
1613 | #endif /* USING_SVR4_H */ | |
1614 | ||
9878760c RK |
1615 | /* Write function prologue. */ |
1616 | ||
1617 | void | |
1618 | output_prolog (file, size) | |
1619 | FILE *file; | |
1620 | int size; | |
1621 | { | |
1622 | int first_reg = first_reg_to_save (); | |
1623 | int must_push = rs6000_pushes_stack (); | |
1624 | int first_fp_reg = first_fp_reg_to_save (); | |
1625 | int basic_size = rs6000_sa_size (); | |
1626 | int total_size = (basic_size + size + current_function_outgoing_args_size); | |
874a0744 | 1627 | char buf[256]; |
9878760c | 1628 | |
d1d27b4c MM |
1629 | /* If this is eabi, call __eabi with main, but do so before the minimal TOC |
1630 | is setup, so we can't use the normal mechanism. */ | |
1631 | #if defined(USING_SVR4_H) && defined(NAME__MAIN) && !defined(INVOKE__main) | |
1632 | int main_p = 0; | |
1633 | ||
1634 | if (IDENTIFIER_LENGTH (DECL_NAME (current_function_decl)) == 4 | |
1635 | && !strcmp (IDENTIFIER_POINTER (DECL_NAME (current_function_decl)), "main")) | |
1636 | { | |
1637 | main_p = 1; | |
1638 | regs_ever_live[65] = 1; | |
1639 | } | |
1640 | #endif | |
1641 | ||
9878760c RK |
1642 | /* Round size to multiple of 8 bytes. */ |
1643 | total_size = (total_size + 7) & ~7; | |
1644 | ||
1645 | /* Write .extern for any function we will call to save and restore fp | |
1646 | values. */ | |
1647 | if (first_fp_reg < 62) | |
4d30c363 MM |
1648 | fprintf (file, "\t.extern %s%d%s\n\t.extern %s%d%s\n", |
1649 | SAVE_FP_PREFIX, first_fp_reg - 32, SAVE_FP_SUFFIX, | |
1650 | RESTORE_FP_PREFIX, first_fp_reg - 32, RESTORE_FP_SUFFIX); | |
9878760c RK |
1651 | |
1652 | /* Write .extern for truncation routines, if needed. */ | |
1653 | if (rs6000_trunc_used && ! trunc_defined) | |
1654 | { | |
e138174b ILT |
1655 | fprintf (file, "\t.extern .%s\n\t.extern .%s\n", |
1656 | RS6000_ITRUNC, RS6000_UITRUNC); | |
9878760c RK |
1657 | trunc_defined = 1; |
1658 | } | |
c764f757 RK |
1659 | /* Write .extern for AIX common mode routines, if needed. */ |
1660 | if (! TARGET_POWER && ! TARGET_POWERPC && ! common_mode_defined) | |
1661 | { | |
f6709c70 JW |
1662 | fputs ("\t.extern __mulh\n", file); |
1663 | fputs ("\t.extern __mull\n", file); | |
1664 | fputs ("\t.extern __divss\n", file); | |
1665 | fputs ("\t.extern __divus\n", file); | |
1666 | fputs ("\t.extern __quoss\n", file); | |
1667 | fputs ("\t.extern __quous\n", file); | |
c764f757 RK |
1668 | common_mode_defined = 1; |
1669 | } | |
9878760c | 1670 | |
d14a6d05 MM |
1671 | #ifdef USING_SVR4_H |
1672 | /* If we have a relocatable GOT section, we need to save the LR. */ | |
1673 | if (TARGET_RELOCATABLE && get_pool_size () != 0) | |
1674 | regs_ever_live[65] = 1; | |
1675 | #endif | |
1676 | ||
e165f3f0 RK |
1677 | /* If we have to call a function to save fpr's, or if we are doing profiling, |
1678 | then we will be using LR. */ | |
1679 | if (first_fp_reg < 62 || profile_flag) | |
9878760c RK |
1680 | regs_ever_live[65] = 1; |
1681 | ||
1682 | /* If we use the link register, get it into r0. */ | |
1683 | if (regs_ever_live[65]) | |
85638c0d | 1684 | asm_fprintf (file, "\tmflr 0\n"); |
9878760c RK |
1685 | |
1686 | /* If we need to save CR, put it into r12. */ | |
1687 | if (must_save_cr ()) | |
85638c0d | 1688 | asm_fprintf (file, "\tmfcr 12\n"); |
9878760c RK |
1689 | |
1690 | /* Do any required saving of fpr's. If only one or two to save, do it | |
53322b0c RK |
1691 | ourself. Otherwise, call function. Note that since they are statically |
1692 | linked, we do not need a nop following them. */ | |
9878760c | 1693 | if (first_fp_reg == 62) |
85638c0d | 1694 | asm_fprintf (file, "\tstfd 30,-16(1)\n\tstfd 31,-8(1)\n"); |
9878760c | 1695 | else if (first_fp_reg == 63) |
85638c0d | 1696 | asm_fprintf (file, "\tstfd 31,-8(1)\n"); |
9878760c | 1697 | else if (first_fp_reg != 64) |
4d30c363 | 1698 | asm_fprintf (file, "\tbl %s%d%s\n", SAVE_FP_PREFIX, first_fp_reg - 32, SAVE_FP_SUFFIX); |
9878760c RK |
1699 | |
1700 | /* Now save gpr's. */ | |
4d30c363 | 1701 | if (! TARGET_MULTIPLE || first_reg == 31) |
85638c0d RK |
1702 | { |
1703 | int regno, loc; | |
1704 | ||
1705 | for (regno = first_reg, | |
1706 | loc = - (32 - first_reg) * 4 - (64 - first_fp_reg) * 8; | |
1707 | regno < 32; | |
1708 | regno++, loc += 4) | |
1709 | asm_fprintf (file, "\t{st|stw} %d,%d(1)\n", regno, loc); | |
1710 | } | |
1711 | ||
9878760c | 1712 | else if (first_reg != 32) |
85638c0d | 1713 | asm_fprintf (file, "\t{stm|stmw} %d,%d(1)\n", first_reg, |
9878760c RK |
1714 | - (32 - first_reg) * 4 - (64 - first_fp_reg) * 8); |
1715 | ||
1716 | /* Save lr if we used it. */ | |
1717 | if (regs_ever_live[65]) | |
85638c0d | 1718 | asm_fprintf (file, "\t{st|stw} 0,8(1)\n"); |
9878760c RK |
1719 | |
1720 | /* Save CR if we use any that must be preserved. */ | |
1721 | if (must_save_cr ()) | |
85638c0d | 1722 | asm_fprintf (file, "\t{st|stw} 12,4(1)\n"); |
9878760c RK |
1723 | |
1724 | /* Update stack and set back pointer. */ | |
1725 | if (must_push) | |
1726 | { | |
1727 | if (total_size < 32767) | |
85638c0d | 1728 | asm_fprintf (file, "\t{stu|stwu} 1,%d(1)\n", - total_size); |
9878760c RK |
1729 | else |
1730 | { | |
35068b43 | 1731 | asm_fprintf (file, "\t{liu|lis} 0,%d\n\t{oril|ori} 0,0,%d\n", |
9878760c | 1732 | (total_size >> 16) & 0xffff, total_size & 0xffff); |
1f5f71ae RK |
1733 | if (TARGET_POWERPC) |
1734 | asm_fprintf (file, "\tsubf 12,0,1\n"); | |
1735 | else | |
1736 | asm_fprintf (file, "\t{sf|subfc} 12,0,1\n"); | |
1737 | asm_fprintf (file, "\t{st|stw} 1,0(12)\n\tmr 1,12\n"); | |
9878760c RK |
1738 | } |
1739 | } | |
1740 | ||
1741 | /* Set frame pointer, if needed. */ | |
1742 | if (frame_pointer_needed) | |
1f5f71ae | 1743 | asm_fprintf (file, "\tmr 31,1\n"); |
1875cc88 | 1744 | |
d1d27b4c MM |
1745 | /* If this is eabi, call __eabi before loading up the minimal TOC */ |
1746 | #if defined(USING_SVR4_H) && defined(NAME__MAIN) && !defined(INVOKE__main) | |
1747 | if (main_p) | |
1748 | fprintf (file, "\tbl %s\n", NAME__MAIN); | |
1749 | #endif | |
1750 | ||
1875cc88 JW |
1751 | /* If TARGET_MINIMAL_TOC, and the constant pool is needed, then load the |
1752 | TOC_TABLE address into register 30. */ | |
1753 | if (TARGET_MINIMAL_TOC && get_pool_size () != 0) | |
3daf36a4 | 1754 | { |
d14a6d05 MM |
1755 | char buf[256]; |
1756 | ||
1757 | #ifdef USING_SVR4_H | |
1758 | if (TARGET_RELOCATABLE) | |
1759 | { | |
874a0744 | 1760 | ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno); |
d14a6d05 MM |
1761 | fprintf (file, "\tbl "); |
1762 | assemble_name (file, buf); | |
1763 | fprintf (file, "\n"); | |
1764 | ||
874a0744 | 1765 | ASM_OUTPUT_INTERNAL_LABEL (file, "LCF", rs6000_pic_labelno); |
d14a6d05 | 1766 | fprintf (file, "\tmflr 30\n"); |
3daf36a4 | 1767 | |
874a0744 MM |
1768 | if (TARGET_POWERPC64) |
1769 | fprintf (file, "\tld 0,"); | |
1770 | else if (TARGET_NEW_MNEMONICS) | |
1771 | fprintf (file, "\tlwz 0,"); | |
1772 | else | |
1773 | fprintf (file, "\tl 0,"); | |
1774 | ||
1775 | fprintf (file, "("); | |
1776 | ASM_GENERATE_INTERNAL_LABEL (buf, "LCL", rs6000_pic_labelno); | |
1777 | assemble_name (file, buf); | |
1778 | fprintf (file, "-"); | |
1779 | ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno); | |
1780 | assemble_name (file, buf); | |
1781 | fprintf (file, ")(30)\n"); | |
d14a6d05 | 1782 | asm_fprintf (file, "\t{cax|add} 30,0,30\n"); |
874a0744 | 1783 | rs6000_pic_labelno++; |
d14a6d05 MM |
1784 | } |
1785 | else | |
1786 | #endif /* USING_SVR4_H */ | |
1787 | { | |
1788 | ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 0); | |
1789 | asm_fprintf (file, "\t{l|lwz} 30,"); | |
1790 | assemble_name (file, buf); | |
1791 | asm_fprintf (file, "(2)\n"); | |
1792 | } | |
3daf36a4 | 1793 | } |
9878760c RK |
1794 | } |
1795 | ||
1796 | /* Write function epilogue. */ | |
1797 | ||
1798 | void | |
1799 | output_epilog (file, size) | |
1800 | FILE *file; | |
1801 | int size; | |
1802 | { | |
1803 | int first_reg = first_reg_to_save (); | |
1804 | int must_push = rs6000_pushes_stack (); | |
1805 | int first_fp_reg = first_fp_reg_to_save (); | |
1806 | int basic_size = rs6000_sa_size (); | |
1807 | int total_size = (basic_size + size + current_function_outgoing_args_size); | |
1808 | rtx insn = get_last_insn (); | |
1809 | ||
1810 | /* Round size to multiple of 8 bytes. */ | |
1811 | total_size = (total_size + 7) & ~7; | |
1812 | ||
1813 | /* If the last insn was a BARRIER, we don't have to write anything except | |
1814 | the trace table. */ | |
1815 | if (GET_CODE (insn) == NOTE) | |
1816 | insn = prev_nonnote_insn (insn); | |
1817 | if (insn == 0 || GET_CODE (insn) != BARRIER) | |
1818 | { | |
1819 | /* If we have a frame pointer, a call to alloca, or a large stack | |
1820 | frame, restore the old stack pointer using the backchain. Otherwise, | |
1821 | we know what size to update it with. */ | |
1822 | if (frame_pointer_needed || current_function_calls_alloca | |
1823 | || total_size > 32767) | |
85638c0d | 1824 | asm_fprintf (file, "\t{l|lwz} 1,0(1)\n"); |
9878760c | 1825 | else if (must_push) |
1f5f71ae | 1826 | asm_fprintf (file, "\t{cal 1,%d(1)|addi 1,1,%d}\n", total_size); |
9878760c | 1827 | |
b4ac57ab | 1828 | /* Get the old lr if we saved it. */ |
9878760c | 1829 | if (regs_ever_live[65]) |
85638c0d | 1830 | asm_fprintf (file, "\t{l|lwz} 0,8(1)\n"); |
9878760c RK |
1831 | |
1832 | /* Get the old cr if we saved it. */ | |
1833 | if (must_save_cr ()) | |
85638c0d | 1834 | asm_fprintf (file, "\t{l|lwz} 12,4(1)\n"); |
9878760c | 1835 | |
b4ac57ab RS |
1836 | /* Set LR here to try to overlap restores below. */ |
1837 | if (regs_ever_live[65]) | |
85638c0d | 1838 | asm_fprintf (file, "\tmtlr 0\n"); |
b4ac57ab | 1839 | |
9878760c | 1840 | /* Restore gpr's. */ |
4d30c363 | 1841 | if (! TARGET_MULTIPLE || first_reg == 31) |
85638c0d RK |
1842 | { |
1843 | int regno, loc; | |
1844 | ||
1845 | for (regno = first_reg, | |
1846 | loc = - (32 - first_reg) * 4 - (64 - first_fp_reg) * 8; | |
1847 | regno < 32; | |
1848 | regno++, loc += 4) | |
1849 | asm_fprintf (file, "\t{l|lwz} %d,%d(1)\n", regno, loc); | |
1850 | } | |
1851 | ||
9878760c | 1852 | else if (first_reg != 32) |
85638c0d RK |
1853 | asm_fprintf (file, "\t{lm|lmw} %d,%d(1)\n", first_reg, |
1854 | - (32 - first_reg) * 4 - (64 - first_fp_reg) * 8); | |
9878760c | 1855 | |
b4ac57ab | 1856 | /* Restore fpr's if we can do it without calling a function. */ |
9878760c | 1857 | if (first_fp_reg == 62) |
85638c0d | 1858 | asm_fprintf (file, "\tlfd 30,-16(1)\n\tlfd 31,-8(1)\n"); |
9878760c | 1859 | else if (first_fp_reg == 63) |
85638c0d | 1860 | asm_fprintf (file, "\tlfd 31,-8(1)\n"); |
9878760c | 1861 | |
28edebac RK |
1862 | /* If we saved cr, restore it here. Just those of cr2, cr3, and cr4 |
1863 | that were used. */ | |
9878760c | 1864 | if (must_save_cr ()) |
85638c0d RK |
1865 | asm_fprintf (file, "\tmtcrf %d,12\n", |
1866 | (regs_ever_live[70] != 0) * 0x20 | |
1867 | + (regs_ever_live[71] != 0) * 0x10 | |
1868 | + (regs_ever_live[72] != 0) * 0x8); | |
9878760c | 1869 | |
b4ac57ab RS |
1870 | /* If we have to restore more than two FP registers, branch to the |
1871 | restore function. It will return to our caller. */ | |
1872 | if (first_fp_reg < 62) | |
4d30c363 | 1873 | asm_fprintf (file, "\tb %s%d%s\n", RESTORE_FP_PREFIX, first_fp_reg - 32, RESTORE_FP_SUFFIX); |
b4ac57ab | 1874 | else |
85638c0d | 1875 | asm_fprintf (file, "\t{br|blr}\n"); |
9878760c | 1876 | } |
b4ac57ab | 1877 | |
9b30bae2 | 1878 | /* Output a traceback table here. See /usr/include/sys/debug.h for info |
314fc5a9 ILT |
1879 | on its format. |
1880 | ||
1881 | We don't output a traceback table if -finhibit-size-directive was | |
1882 | used. The documentation for -finhibit-size-directive reads | |
1883 | ``don't output a @code{.size} assembler directive, or anything | |
1884 | else that would cause trouble if the function is split in the | |
1885 | middle, and the two halves are placed at locations far apart in | |
1886 | memory.'' The traceback table has this property, since it | |
1887 | includes the offset from the start of the function to the | |
4d30c363 MM |
1888 | traceback table itself. |
1889 | ||
1890 | System V.4 Powerpc's (and the embedded ABI derived from it) use a | |
1891 | different traceback table located before the prologue. */ | |
1892 | #ifndef USING_SVR4_H | |
314fc5a9 | 1893 | if (! flag_inhibit_size_directive) |
9b30bae2 | 1894 | { |
314fc5a9 ILT |
1895 | char *fname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0); |
1896 | int fixed_parms, float_parms, parm_info; | |
1897 | int i; | |
1898 | ||
1899 | /* Need label immediately before tbtab, so we can compute its offset | |
1900 | from the function start. */ | |
1901 | if (*fname == '*') | |
1902 | ++fname; | |
1903 | ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT"); | |
1904 | ASM_OUTPUT_LABEL (file, fname); | |
1905 | ||
1906 | /* The .tbtab pseudo-op can only be used for the first eight | |
1907 | expressions, since it can't handle the possibly variable | |
1908 | length fields that follow. However, if you omit the optional | |
1909 | fields, the assembler outputs zeros for all optional fields | |
1910 | anyways, giving each variable length field is minimum length | |
1911 | (as defined in sys/debug.h). Thus we can not use the .tbtab | |
1912 | pseudo-op at all. */ | |
1913 | ||
1914 | /* An all-zero word flags the start of the tbtab, for debuggers | |
1915 | that have to find it by searching forward from the entry | |
1916 | point or from the current pc. */ | |
1917 | fprintf (file, "\t.long 0\n"); | |
1918 | ||
1919 | /* Tbtab format type. Use format type 0. */ | |
1920 | fprintf (file, "\t.byte 0,"); | |
1921 | ||
1922 | /* Language type. Unfortunately, there doesn't seem to be any | |
1923 | official way to get this info, so we use language_string. C | |
1924 | is 0. C++ is 9. No number defined for Obj-C, so use the | |
1925 | value for C for now. */ | |
1926 | if (! strcmp (language_string, "GNU C") | |
1927 | || ! strcmp (language_string, "GNU Obj-C")) | |
1928 | i = 0; | |
1929 | else if (! strcmp (language_string, "GNU F77")) | |
1930 | i = 1; | |
1931 | else if (! strcmp (language_string, "GNU Ada")) | |
1932 | i = 3; | |
1933 | else if (! strcmp (language_string, "GNU PASCAL")) | |
1934 | i = 2; | |
1935 | else if (! strcmp (language_string, "GNU C++")) | |
1936 | i = 9; | |
1937 | else | |
1938 | abort (); | |
1939 | fprintf (file, "%d,", i); | |
1940 | ||
1941 | /* 8 single bit fields: global linkage (not set for C extern linkage, | |
1942 | apparently a PL/I convention?), out-of-line epilogue/prologue, offset | |
1943 | from start of procedure stored in tbtab, internal function, function | |
1944 | has controlled storage, function has no toc, function uses fp, | |
1945 | function logs/aborts fp operations. */ | |
1946 | /* Assume that fp operations are used if any fp reg must be saved. */ | |
1947 | fprintf (file, "%d,", (1 << 5) | ((first_fp_reg != 64) << 1)); | |
1948 | ||
1949 | /* 6 bitfields: function is interrupt handler, name present in | |
1950 | proc table, function calls alloca, on condition directives | |
1951 | (controls stack walks, 3 bits), saves condition reg, saves | |
1952 | link reg. */ | |
1953 | /* The `function calls alloca' bit seems to be set whenever reg 31 is | |
1954 | set up as a frame pointer, even when there is no alloca call. */ | |
1955 | fprintf (file, "%d,", | |
1956 | ((1 << 6) | (frame_pointer_needed << 5) | |
1957 | | (must_save_cr () << 1) | (regs_ever_live[65]))); | |
1958 | ||
1959 | /* 3 bitfields: saves backchain, spare bit, number of fpr saved | |
1960 | (6 bits). */ | |
1961 | fprintf (file, "%d,", | |
1962 | (must_push << 7) | (64 - first_fp_reg_to_save ())); | |
1963 | ||
1964 | /* 2 bitfields: spare bits (2 bits), number of gpr saved (6 bits). */ | |
1965 | fprintf (file, "%d,", (32 - first_reg_to_save ())); | |
1966 | ||
1967 | { | |
1968 | /* Compute the parameter info from the function decl argument | |
1969 | list. */ | |
1970 | tree decl; | |
1971 | int next_parm_info_bit; | |
1972 | ||
1973 | next_parm_info_bit = 31; | |
1974 | parm_info = 0; | |
1975 | fixed_parms = 0; | |
1976 | float_parms = 0; | |
1977 | ||
1978 | for (decl = DECL_ARGUMENTS (current_function_decl); | |
1979 | decl; decl = TREE_CHAIN (decl)) | |
1980 | { | |
1981 | rtx parameter = DECL_INCOMING_RTL (decl); | |
1982 | enum machine_mode mode = GET_MODE (parameter); | |
1983 | ||
1984 | if (GET_CODE (parameter) == REG) | |
1985 | { | |
1986 | if (GET_MODE_CLASS (mode) == MODE_FLOAT) | |
1987 | { | |
1988 | int bits; | |
1989 | ||
1990 | float_parms++; | |
1991 | ||
1992 | if (mode == SFmode) | |
1993 | bits = 0x2; | |
1994 | else if (mode == DFmode) | |
1995 | bits = 0x3; | |
1996 | else | |
1997 | abort (); | |
1998 | ||
1999 | /* If only one bit will fit, don't or in this entry. */ | |
2000 | if (next_parm_info_bit > 0) | |
2001 | parm_info |= (bits << (next_parm_info_bit - 1)); | |
2002 | next_parm_info_bit -= 2; | |
2003 | } | |
2004 | else | |
2005 | { | |
2006 | fixed_parms += ((GET_MODE_SIZE (mode) | |
2007 | + (UNITS_PER_WORD - 1)) | |
2008 | / UNITS_PER_WORD); | |
2009 | next_parm_info_bit -= 1; | |
2010 | } | |
2011 | } | |
2012 | } | |
2013 | } | |
2014 | ||
2015 | /* Number of fixed point parameters. */ | |
2016 | /* This is actually the number of words of fixed point parameters; thus | |
2017 | an 8 byte struct counts as 2; and thus the maximum value is 8. */ | |
2018 | fprintf (file, "%d,", fixed_parms); | |
2019 | ||
2020 | /* 2 bitfields: number of floating point parameters (7 bits), parameters | |
2021 | all on stack. */ | |
2022 | /* This is actually the number of fp registers that hold parameters; | |
2023 | and thus the maximum value is 13. */ | |
2024 | /* Set parameters on stack bit if parameters are not in their original | |
2025 | registers, regardless of whether they are on the stack? Xlc | |
2026 | seems to set the bit when not optimizing. */ | |
2027 | fprintf (file, "%d\n", ((float_parms << 1) | (! optimize))); | |
2028 | ||
2029 | /* Optional fields follow. Some are variable length. */ | |
2030 | ||
2031 | /* Parameter types, left adjusted bit fields: 0 fixed, 10 single float, | |
2032 | 11 double float. */ | |
2033 | /* There is an entry for each parameter in a register, in the order that | |
2034 | they occur in the parameter list. Any intervening arguments on the | |
2035 | stack are ignored. If the list overflows a long (max possible length | |
2036 | 34 bits) then completely leave off all elements that don't fit. */ | |
2037 | /* Only emit this long if there was at least one parameter. */ | |
2038 | if (fixed_parms || float_parms) | |
2039 | fprintf (file, "\t.long %d\n", parm_info); | |
2040 | ||
2041 | /* Offset from start of code to tb table. */ | |
2042 | fprintf (file, "\t.long "); | |
2043 | ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT"); | |
2044 | RS6000_OUTPUT_BASENAME (file, fname); | |
2045 | fprintf (file, "-."); | |
2046 | RS6000_OUTPUT_BASENAME (file, fname); | |
2047 | fprintf (file, "\n"); | |
2048 | ||
2049 | /* Interrupt handler mask. */ | |
2050 | /* Omit this long, since we never set the interrupt handler bit | |
2051 | above. */ | |
2052 | ||
2053 | /* Number of CTL (controlled storage) anchors. */ | |
2054 | /* Omit this long, since the has_ctl bit is never set above. */ | |
2055 | ||
2056 | /* Displacement into stack of each CTL anchor. */ | |
2057 | /* Omit this list of longs, because there are no CTL anchors. */ | |
2058 | ||
2059 | /* Length of function name. */ | |
2060 | fprintf (file, "\t.short %d\n", strlen (fname)); | |
2061 | ||
2062 | /* Function name. */ | |
2063 | assemble_string (fname, strlen (fname)); | |
2064 | ||
2065 | /* Register for alloca automatic storage; this is always reg 31. | |
2066 | Only emit this if the alloca bit was set above. */ | |
2067 | if (frame_pointer_needed) | |
2068 | fprintf (file, "\t.byte 31\n"); | |
9b30bae2 | 2069 | } |
4d30c363 | 2070 | #endif /* !USING_SVR4_H */ |
9878760c RK |
2071 | } |
2072 | \f | |
2073 | /* Output a TOC entry. We derive the entry name from what is | |
2074 | being written. */ | |
2075 | ||
2076 | void | |
2077 | output_toc (file, x, labelno) | |
2078 | FILE *file; | |
2079 | rtx x; | |
2080 | int labelno; | |
2081 | { | |
2082 | char buf[256]; | |
2083 | char *name = buf; | |
2084 | rtx base = x; | |
2085 | int offset = 0; | |
2086 | ||
d14a6d05 MM |
2087 | #ifdef USING_SVR4_H |
2088 | if (TARGET_MINIMAL_TOC) | |
2089 | { | |
2090 | ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC"); | |
2091 | fprintf (file, "%d = .-", labelno); | |
2092 | ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LCTOC"); | |
2093 | fprintf (file, "1\n"); | |
2094 | } | |
2095 | else | |
2096 | #endif /* USING_SVR4_H */ | |
2097 | ASM_OUTPUT_INTERNAL_LABEL (file, "LC", labelno); | |
9878760c | 2098 | |
37c37a57 RK |
2099 | /* Handle FP constants specially. Note that if we have a minimal |
2100 | TOC, things we put here aren't actually in the TOC, so we can allow | |
2101 | FP constants. */ | |
9878760c RK |
2102 | if (GET_CODE (x) == CONST_DOUBLE |
2103 | && GET_MODE (x) == DFmode | |
37c37a57 | 2104 | && ! (TARGET_NO_FP_IN_TOC && ! TARGET_MINIMAL_TOC)) |
9878760c | 2105 | { |
0adc764e RK |
2106 | REAL_VALUE_TYPE r; |
2107 | long l[2]; | |
2108 | ||
2109 | REAL_VALUE_FROM_CONST_DOUBLE (r, x); | |
2110 | REAL_VALUE_TO_TARGET_DOUBLE (r, l); | |
1875cc88 | 2111 | if (TARGET_MINIMAL_TOC) |
0adc764e | 2112 | fprintf (file, "\t.long %ld\n\t.long %ld\n", l[0], l[1]); |
1875cc88 | 2113 | else |
0adc764e RK |
2114 | fprintf (file, "\t.tc FD_%lx_%lx[TC],%ld,%ld\n", |
2115 | l[0], l[1], l[0], l[1]); | |
9878760c RK |
2116 | return; |
2117 | } | |
2118 | else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == SFmode | |
37c37a57 | 2119 | && ! (TARGET_NO_FP_IN_TOC && ! TARGET_MINIMAL_TOC)) |
9878760c RK |
2120 | { |
2121 | rtx val = operand_subword (x, 0, 0, SFmode); | |
2122 | ||
2123 | if (val == 0 || GET_CODE (val) != CONST_INT) | |
2124 | abort (); | |
2125 | ||
1875cc88 JW |
2126 | if (TARGET_MINIMAL_TOC) |
2127 | fprintf (file, "\t.long %d\n", INTVAL (val)); | |
2128 | else | |
2129 | fprintf (file, "\t.tc FS_%x[TC],%d\n", INTVAL (val), INTVAL (val)); | |
9878760c RK |
2130 | return; |
2131 | } | |
2132 | ||
2133 | if (GET_CODE (x) == CONST) | |
2134 | { | |
2135 | base = XEXP (XEXP (x, 0), 0); | |
2136 | offset = INTVAL (XEXP (XEXP (x, 0), 1)); | |
2137 | } | |
2138 | ||
2139 | if (GET_CODE (base) == SYMBOL_REF) | |
2140 | name = XSTR (base, 0); | |
2141 | else if (GET_CODE (base) == LABEL_REF) | |
2142 | ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (XEXP (base, 0))); | |
2143 | else if (GET_CODE (base) == CODE_LABEL) | |
2144 | ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (base)); | |
2145 | else | |
2146 | abort (); | |
2147 | ||
1875cc88 JW |
2148 | if (TARGET_MINIMAL_TOC) |
2149 | fprintf (file, "\t.long "); | |
2150 | else | |
2151 | { | |
2152 | fprintf (file, "\t.tc "); | |
2153 | RS6000_OUTPUT_BASENAME (file, name); | |
9878760c | 2154 | |
1875cc88 JW |
2155 | if (offset < 0) |
2156 | fprintf (file, ".N%d", - offset); | |
2157 | else if (offset) | |
2158 | fprintf (file, ".P%d", offset); | |
9878760c | 2159 | |
1875cc88 JW |
2160 | fprintf (file, "[TC],"); |
2161 | } | |
9878760c RK |
2162 | output_addr_const (file, x); |
2163 | fprintf (file, "\n"); | |
2164 | } | |
2165 | \f | |
2166 | /* Output an assembler pseudo-op to write an ASCII string of N characters | |
2167 | starting at P to FILE. | |
2168 | ||
2169 | On the RS/6000, we have to do this using the .byte operation and | |
2170 | write out special characters outside the quoted string. | |
2171 | Also, the assembler is broken; very long strings are truncated, | |
2172 | so we must artificially break them up early. */ | |
2173 | ||
2174 | void | |
2175 | output_ascii (file, p, n) | |
2176 | FILE *file; | |
2177 | char *p; | |
2178 | int n; | |
2179 | { | |
2180 | char c; | |
2181 | int i, count_string; | |
2182 | char *for_string = "\t.byte \""; | |
2183 | char *for_decimal = "\t.byte "; | |
2184 | char *to_close = NULL; | |
2185 | ||
2186 | count_string = 0; | |
2187 | for (i = 0; i < n; i++) | |
2188 | { | |
2189 | c = *p++; | |
2190 | if (c >= ' ' && c < 0177) | |
2191 | { | |
2192 | if (for_string) | |
2193 | fputs (for_string, file); | |
2194 | putc (c, file); | |
2195 | ||
2196 | /* Write two quotes to get one. */ | |
2197 | if (c == '"') | |
2198 | { | |
2199 | putc (c, file); | |
2200 | ++count_string; | |
2201 | } | |
2202 | ||
2203 | for_string = NULL; | |
2204 | for_decimal = "\"\n\t.byte "; | |
2205 | to_close = "\"\n"; | |
2206 | ++count_string; | |
2207 | ||
2208 | if (count_string >= 512) | |
2209 | { | |
2210 | fputs (to_close, file); | |
2211 | ||
2212 | for_string = "\t.byte \""; | |
2213 | for_decimal = "\t.byte "; | |
2214 | to_close = NULL; | |
2215 | count_string = 0; | |
2216 | } | |
2217 | } | |
2218 | else | |
2219 | { | |
2220 | if (for_decimal) | |
2221 | fputs (for_decimal, file); | |
2222 | fprintf (file, "%d", c); | |
2223 | ||
2224 | for_string = "\n\t.byte \""; | |
2225 | for_decimal = ", "; | |
2226 | to_close = "\n"; | |
2227 | count_string = 0; | |
2228 | } | |
2229 | } | |
2230 | ||
2231 | /* Now close the string if we have written one. Then end the line. */ | |
2232 | if (to_close) | |
2233 | fprintf (file, to_close); | |
2234 | } | |
2235 | \f | |
2236 | /* Generate a unique section name for FILENAME for a section type | |
2237 | represented by SECTION_DESC. Output goes into BUF. | |
2238 | ||
2239 | SECTION_DESC can be any string, as long as it is different for each | |
2240 | possible section type. | |
2241 | ||
2242 | We name the section in the same manner as xlc. The name begins with an | |
2243 | underscore followed by the filename (after stripping any leading directory | |
11e5fe42 RK |
2244 | names) with the last period replaced by the string SECTION_DESC. If |
2245 | FILENAME does not contain a period, SECTION_DESC is appended to the end of | |
2246 | the name. */ | |
9878760c RK |
2247 | |
2248 | void | |
2249 | rs6000_gen_section_name (buf, filename, section_desc) | |
2250 | char **buf; | |
2251 | char *filename; | |
2252 | char *section_desc; | |
2253 | { | |
11e5fe42 | 2254 | char *q, *after_last_slash, *last_period; |
9878760c RK |
2255 | char *p; |
2256 | int len; | |
9878760c RK |
2257 | |
2258 | after_last_slash = filename; | |
2259 | for (q = filename; *q; q++) | |
11e5fe42 RK |
2260 | { |
2261 | if (*q == '/') | |
2262 | after_last_slash = q + 1; | |
2263 | else if (*q == '.') | |
2264 | last_period = q; | |
2265 | } | |
9878760c | 2266 | |
11e5fe42 | 2267 | len = strlen (after_last_slash) + strlen (section_desc) + 2; |
9878760c RK |
2268 | *buf = (char *) permalloc (len); |
2269 | ||
2270 | p = *buf; | |
2271 | *p++ = '_'; | |
2272 | ||
2273 | for (q = after_last_slash; *q; q++) | |
2274 | { | |
11e5fe42 | 2275 | if (q == last_period) |
9878760c RK |
2276 | { |
2277 | strcpy (p, section_desc); | |
2278 | p += strlen (section_desc); | |
9878760c RK |
2279 | } |
2280 | ||
2281 | else if (isalnum (*q)) | |
2282 | *p++ = *q; | |
2283 | } | |
2284 | ||
11e5fe42 | 2285 | if (last_period == 0) |
9878760c RK |
2286 | strcpy (p, section_desc); |
2287 | else | |
2288 | *p = '\0'; | |
2289 | } | |
e165f3f0 RK |
2290 | \f |
2291 | /* Write function profiler code. */ | |
2292 | ||
2293 | void | |
2294 | output_function_profiler (file, labelno) | |
2295 | FILE *file; | |
2296 | int labelno; | |
2297 | { | |
4d30c363 MM |
2298 | #ifdef USING_SVR4_H |
2299 | abort (); | |
2300 | #else | |
e165f3f0 RK |
2301 | /* The last used parameter register. */ |
2302 | int last_parm_reg; | |
2303 | int i, j; | |
3daf36a4 | 2304 | char buf[100]; |
e165f3f0 RK |
2305 | |
2306 | /* Set up a TOC entry for the profiler label. */ | |
2307 | toc_section (); | |
3daf36a4 ILT |
2308 | ASM_OUTPUT_INTERNAL_LABEL (file, "LPC", labelno); |
2309 | ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno); | |
35fc1624 | 2310 | if (TARGET_MINIMAL_TOC) |
3daf36a4 ILT |
2311 | { |
2312 | fprintf (file, "\t.long "); | |
2313 | assemble_name (file, buf); | |
2314 | fprintf (file, "\n"); | |
2315 | } | |
35fc1624 | 2316 | else |
3daf36a4 ILT |
2317 | { |
2318 | fprintf (file, "\t.tc\t"); | |
2319 | assemble_name (file, buf); | |
2320 | fprintf (file, "[TC],"); | |
2321 | assemble_name (file, buf); | |
2322 | fprintf (file, "\n"); | |
2323 | } | |
e165f3f0 RK |
2324 | text_section (); |
2325 | ||
2326 | /* Figure out last used parameter register. The proper thing to do is | |
2327 | to walk incoming args of the function. A function might have live | |
2328 | parameter registers even if it has no incoming args. */ | |
2329 | ||
2330 | for (last_parm_reg = 10; | |
2331 | last_parm_reg > 2 && ! regs_ever_live [last_parm_reg]; | |
2332 | last_parm_reg--) | |
2333 | ; | |
2334 | ||
2335 | /* Save parameter registers in regs 23-30. Don't overwrite reg 31, since | |
2336 | it might be set up as the frame pointer. */ | |
2337 | ||
2338 | for (i = 3, j = 30; i <= last_parm_reg; i++, j--) | |
2339 | fprintf (file, "\tai %d,%d,0\n", j, i); | |
2340 | ||
2341 | /* Load location address into r3, and call mcount. */ | |
2342 | ||
3daf36a4 ILT |
2343 | ASM_GENERATE_INTERNAL_LABEL (buf, "LPC", labelno); |
2344 | fprintf (file, "\tl 3,"); | |
2345 | assemble_name (file, buf); | |
2346 | fprintf (file, "(2)\n\tbl .mcount\n"); | |
e165f3f0 RK |
2347 | |
2348 | /* Restore parameter registers. */ | |
2349 | ||
2350 | for (i = 3, j = 30; i <= last_parm_reg; i++, j--) | |
2351 | fprintf (file, "\tai %d,%d,0\n", i, j); | |
4d30c363 | 2352 | #endif |
e165f3f0 | 2353 | } |
a251ffd0 TG |
2354 | |
2355 | /* Adjust the cost of a scheduling dependency. Return the new cost of | |
2356 | a dependency LINK or INSN on DEP_INSN. COST is the current cost. */ | |
2357 | ||
2358 | int | |
a06faf84 | 2359 | rs6000_adjust_cost (insn, link, dep_insn, cost) |
a251ffd0 TG |
2360 | rtx insn; |
2361 | rtx link; | |
2362 | rtx dep_insn; | |
2363 | int cost; | |
2364 | { | |
2365 | if (! recog_memoized (insn)) | |
2366 | return 0; | |
2367 | ||
2368 | if (REG_NOTE_KIND (link) != 0) | |
2369 | return 0; | |
2370 | ||
2371 | if (REG_NOTE_KIND (link) == 0) | |
2372 | { | |
2373 | /* Data dependency; DEP_INSN writes a register that INSN reads some | |
2374 | cycles later. */ | |
2375 | ||
2376 | /* Tell the first scheduling pass about the latency between a mtctr | |
2377 | and bctr (and mtlr and br/blr). The first scheduling pass will not | |
2378 | know about this latency since the mtctr instruction, which has the | |
2379 | latency associated to it, will be generated by reload. */ | |
2380 | if (get_attr_type (insn) == TYPE_JMPREG) | |
2381 | return TARGET_POWER ? 5 : 4; | |
2382 | ||
2383 | /* Fall out to return default cost. */ | |
2384 | } | |
2385 | ||
2386 | return cost; | |
2387 | } |