]>
Commit | Line | Data |
---|---|---|
9878760c | 1 | /* Subroutines used for code generation on IBM RS/6000. |
9ebbca7d | 2 | Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, |
63b6e069 | 3 | 2000, 2001 Free Software Foundation, Inc. |
fab3bcc3 | 4 | Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu) |
9878760c RK |
5 | |
6 | This file is part of GNU CC. | |
7 | ||
8 | GNU CC is free software; you can redistribute it and/or modify | |
9 | it under the terms of the GNU General Public License as published by | |
10 | the Free Software Foundation; either version 2, or (at your option) | |
11 | any later version. | |
12 | ||
13 | GNU CC is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
19 | along with GNU CC; see the file COPYING. If not, write to | |
c15c9075 RK |
20 | the Free Software Foundation, 59 Temple Place - Suite 330, |
21 | Boston, MA 02111-1307, USA. */ | |
9878760c | 22 | |
956d6950 | 23 | #include "config.h" |
c4d38ccb | 24 | #include "system.h" |
9878760c RK |
25 | #include "rtl.h" |
26 | #include "regs.h" | |
27 | #include "hard-reg-set.h" | |
28 | #include "real.h" | |
29 | #include "insn-config.h" | |
30 | #include "conditions.h" | |
9878760c RK |
31 | #include "insn-attr.h" |
32 | #include "flags.h" | |
33 | #include "recog.h" | |
9878760c | 34 | #include "obstack.h" |
9b30bae2 | 35 | #include "tree.h" |
dfafc897 | 36 | #include "expr.h" |
2a430ec1 | 37 | #include "except.h" |
a7df97e6 | 38 | #include "function.h" |
296b8152 | 39 | #include "output.h" |
d5fa86ba | 40 | #include "basic-block.h" |
296b8152 | 41 | #include "toplev.h" |
c8023011 | 42 | #include "ggc.h" |
9ebbca7d GK |
43 | #include "hashtab.h" |
44 | #include "tm_p.h" | |
672a6f42 NB |
45 | #include "target.h" |
46 | #include "target-def.h" | |
9b30bae2 | 47 | |
7509c759 MM |
48 | #ifndef TARGET_NO_PROTOTYPE |
49 | #define TARGET_NO_PROTOTYPE 0 | |
50 | #endif | |
51 | ||
5248c961 | 52 | extern int profile_block_flag; |
9878760c RK |
53 | |
54 | #define min(A,B) ((A) < (B) ? (A) : (B)) | |
55 | #define max(A,B) ((A) > (B) ? (A) : (B)) | |
56 | ||
5248c961 RK |
57 | /* Target cpu type */ |
58 | ||
59 | enum processor_type rs6000_cpu; | |
8e3f41e7 MM |
60 | struct rs6000_cpu_select rs6000_select[3] = |
61 | { | |
815cdc52 MM |
62 | /* switch name, tune arch */ |
63 | { (const char *)0, "--with-cpu=", 1, 1 }, | |
64 | { (const char *)0, "-mcpu=", 1, 1 }, | |
65 | { (const char *)0, "-mtune=", 1, 0 }, | |
8e3f41e7 | 66 | }; |
5248c961 | 67 | |
c764f757 RK |
68 | /* Set to non-zero once AIX common-mode calls have been defined. */ |
69 | static int common_mode_defined; | |
c81bebd7 | 70 | |
9878760c RK |
71 | /* Save information from a "cmpxx" operation until the branch or scc is |
72 | emitted. */ | |
9878760c RK |
73 | rtx rs6000_compare_op0, rs6000_compare_op1; |
74 | int rs6000_compare_fp_p; | |
874a0744 | 75 | |
874a0744 MM |
76 | /* Label number of label created for -mrelocatable, to call to so we can |
77 | get the address of the GOT section */ | |
78 | int rs6000_pic_labelno; | |
c81bebd7 | 79 | |
9ebbca7d | 80 | #ifdef USING_SVR4_H |
c81bebd7 | 81 | /* Which abi to adhere to */ |
815cdc52 | 82 | const char *rs6000_abi_name = RS6000_ABI_NAME; |
d9407988 MM |
83 | |
84 | /* Semantics of the small data area */ | |
85 | enum rs6000_sdata_type rs6000_sdata = SDATA_DATA; | |
86 | ||
87 | /* Which small data model to use */ | |
815cdc52 | 88 | const char *rs6000_sdata_name = (char *)0; |
9ebbca7d GK |
89 | |
90 | /* Counter for labels which are to be placed in .fixup. */ | |
91 | int fixuplabelno = 0; | |
874a0744 | 92 | #endif |
4697a36c | 93 | |
b6c9286a MM |
94 | /* ABI enumeration available for subtarget to use. */ |
95 | enum rs6000_abi rs6000_current_abi; | |
96 | ||
38c1f2d7 | 97 | /* Debug flags */ |
815cdc52 | 98 | const char *rs6000_debug_name; |
38c1f2d7 MM |
99 | int rs6000_debug_stack; /* debug stack applications */ |
100 | int rs6000_debug_arg; /* debug argument handling */ | |
101 | ||
102 | /* Flag to say the TOC is initialized */ | |
103 | int toc_initialized; | |
9ebbca7d | 104 | char toc_label_name[10]; |
38c1f2d7 | 105 | |
9ebbca7d GK |
106 | /* Alias set for saves and restores from the rs6000 stack. */ |
107 | static int rs6000_sr_alias_set; | |
c8023011 | 108 | |
9ebbca7d GK |
109 | static void rs6000_add_gc_roots PARAMS ((void)); |
110 | static int num_insns_constant_wide PARAMS ((HOST_WIDE_INT)); | |
111 | static rtx expand_block_move_mem PARAMS ((enum machine_mode, rtx, rtx)); | |
39a10a29 GK |
112 | static void validate_condition_mode |
113 | PARAMS ((enum rtx_code, enum machine_mode)); | |
114 | static rtx rs6000_generate_compare PARAMS ((enum rtx_code)); | |
e50f5f3d | 115 | static void rs6000_maybe_dead PARAMS ((rtx)); |
9ebbca7d GK |
116 | static void rs6000_emit_stack_tie PARAMS ((void)); |
117 | static void rs6000_frame_related PARAMS ((rtx, rtx, HOST_WIDE_INT, rtx, rtx)); | |
118 | static void rs6000_emit_allocate_stack PARAMS ((HOST_WIDE_INT, int)); | |
119 | static unsigned rs6000_hash_constant PARAMS ((rtx)); | |
120 | static unsigned toc_hash_function PARAMS ((const void *)); | |
121 | static int toc_hash_eq PARAMS ((const void *, const void *)); | |
2eba1afa | 122 | static int toc_hash_mark_entry PARAMS ((void **, void *)); |
9ebbca7d GK |
123 | static void toc_hash_mark_table PARAMS ((void *)); |
124 | static int constant_pool_expr_1 PARAMS ((rtx, int *, int *)); | |
6fee9e99 NC |
125 | static void rs6000_free_machine_status PARAMS ((struct function *)); |
126 | static void rs6000_init_machine_status PARAMS ((struct function *)); | |
71f123ca | 127 | static int rs6000_ra_ever_killed PARAMS ((void)); |
672a6f42 | 128 | static int rs6000_valid_type_attribute_p PARAMS ((tree, tree, tree, tree)); |
c81bebd7 MM |
129 | \f |
130 | /* Default register names. */ | |
131 | char rs6000_reg_names[][8] = | |
132 | { | |
802a0058 MM |
133 | "0", "1", "2", "3", "4", "5", "6", "7", |
134 | "8", "9", "10", "11", "12", "13", "14", "15", | |
135 | "16", "17", "18", "19", "20", "21", "22", "23", | |
136 | "24", "25", "26", "27", "28", "29", "30", "31", | |
137 | "0", "1", "2", "3", "4", "5", "6", "7", | |
138 | "8", "9", "10", "11", "12", "13", "14", "15", | |
139 | "16", "17", "18", "19", "20", "21", "22", "23", | |
140 | "24", "25", "26", "27", "28", "29", "30", "31", | |
141 | "mq", "lr", "ctr","ap", | |
142 | "0", "1", "2", "3", "4", "5", "6", "7", | |
9ebbca7d | 143 | "xer" |
c81bebd7 MM |
144 | }; |
145 | ||
146 | #ifdef TARGET_REGNAMES | |
147 | static char alt_reg_names[][8] = | |
148 | { | |
802a0058 MM |
149 | "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7", |
150 | "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15", | |
151 | "%r16", "%r17", "%r18", "%r19", "%r20", "%r21", "%r22", "%r23", | |
152 | "%r24", "%r25", "%r26", "%r27", "%r28", "%r29", "%r30", "%r31", | |
153 | "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7", | |
154 | "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15", | |
155 | "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23", | |
156 | "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31", | |
157 | "mq", "lr", "ctr", "ap", | |
158 | "%cr0", "%cr1", "%cr2", "%cr3", "%cr4", "%cr5", "%cr6", "%cr7", | |
9ebbca7d | 159 | "xer" |
c81bebd7 MM |
160 | }; |
161 | #endif | |
9878760c | 162 | \f |
daf11973 MM |
163 | #ifndef MASK_STRICT_ALIGN |
164 | #define MASK_STRICT_ALIGN 0 | |
165 | #endif | |
672a6f42 NB |
166 | \f |
167 | /* Initialize the GCC target structure. */ | |
168 | #undef TARGET_VALID_TYPE_ATTRIBUTE | |
169 | #define TARGET_VALID_TYPE_ATTRIBUTE rs6000_valid_type_attribute_p | |
daf11973 | 170 | |
672a6f42 NB |
171 | struct gcc_target target = TARGET_INITIALIZER; |
172 | \f | |
5248c961 RK |
173 | /* Override command line options. Mostly we process the processor |
174 | type and sometimes adjust other TARGET_ options. */ | |
175 | ||
176 | void | |
8e3f41e7 | 177 | rs6000_override_options (default_cpu) |
d330fd93 | 178 | const char *default_cpu; |
5248c961 | 179 | { |
c4d38ccb | 180 | size_t i, j; |
8e3f41e7 | 181 | struct rs6000_cpu_select *ptr; |
5248c961 | 182 | |
85638c0d RK |
183 | /* Simplify the entries below by making a mask for any POWER |
184 | variant and any PowerPC variant. */ | |
185 | ||
938937d8 | 186 | #define POWER_MASKS (MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING) |
68c49ffa RK |
187 | #define POWERPC_MASKS (MASK_POWERPC | MASK_PPC_GPOPT \ |
188 | | MASK_PPC_GFXOPT | MASK_POWERPC64) | |
189 | #define POWERPC_OPT_MASKS (MASK_PPC_GPOPT | MASK_PPC_GFXOPT) | |
85638c0d | 190 | |
5248c961 RK |
191 | static struct ptt |
192 | { | |
d330fd93 | 193 | const char *name; /* Canonical processor name. */ |
5248c961 RK |
194 | enum processor_type processor; /* Processor type enum value. */ |
195 | int target_enable; /* Target flags to enable. */ | |
196 | int target_disable; /* Target flags to disable. */ | |
197 | } processor_target_table[] | |
cf27b467 MM |
198 | = {{"common", PROCESSOR_COMMON, MASK_NEW_MNEMONICS, |
199 | POWER_MASKS | POWERPC_MASKS}, | |
db7f1e43 | 200 | {"power", PROCESSOR_POWER, |
938937d8 | 201 | MASK_POWER | MASK_MULTIPLE | MASK_STRING, |
db7f1e43 | 202 | MASK_POWER2 | POWERPC_MASKS | MASK_NEW_MNEMONICS}, |
8e3f41e7 MM |
203 | {"power2", PROCESSOR_POWER, |
204 | MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING, | |
205 | POWERPC_MASKS | MASK_NEW_MNEMONICS}, | |
c71791e0 DE |
206 | {"power3", PROCESSOR_PPC630, |
207 | MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS, | |
208 | POWER_MASKS | MASK_PPC_GPOPT}, | |
db7f1e43 RK |
209 | {"powerpc", PROCESSOR_POWERPC, |
210 | MASK_POWERPC | MASK_NEW_MNEMONICS, | |
68c49ffa | 211 | POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64}, |
3cb999d8 DE |
212 | {"powerpc64", PROCESSOR_POWERPC64, |
213 | MASK_POWERPC | MASK_POWERPC64 | MASK_NEW_MNEMONICS, | |
214 | POWER_MASKS | POWERPC_OPT_MASKS}, | |
db7f1e43 | 215 | {"rios", PROCESSOR_RIOS1, |
938937d8 | 216 | MASK_POWER | MASK_MULTIPLE | MASK_STRING, |
db7f1e43 RK |
217 | MASK_POWER2 | POWERPC_MASKS | MASK_NEW_MNEMONICS}, |
218 | {"rios1", PROCESSOR_RIOS1, | |
938937d8 | 219 | MASK_POWER | MASK_MULTIPLE | MASK_STRING, |
db7f1e43 RK |
220 | MASK_POWER2 | POWERPC_MASKS | MASK_NEW_MNEMONICS}, |
221 | {"rsc", PROCESSOR_PPC601, | |
938937d8 | 222 | MASK_POWER | MASK_MULTIPLE | MASK_STRING, |
db7f1e43 RK |
223 | MASK_POWER2 | POWERPC_MASKS | MASK_NEW_MNEMONICS}, |
224 | {"rsc1", PROCESSOR_PPC601, | |
938937d8 | 225 | MASK_POWER | MASK_MULTIPLE | MASK_STRING, |
db7f1e43 RK |
226 | MASK_POWER2 | POWERPC_MASKS | MASK_NEW_MNEMONICS}, |
227 | {"rios2", PROCESSOR_RIOS2, | |
938937d8 | 228 | MASK_POWER | MASK_MULTIPLE | MASK_STRING | MASK_POWER2, |
db7f1e43 | 229 | POWERPC_MASKS | MASK_NEW_MNEMONICS}, |
3cb999d8 DE |
230 | {"rs64a", PROCESSOR_RS64A, |
231 | MASK_POWERPC | MASK_NEW_MNEMONICS, | |
232 | POWER_MASKS | POWERPC_OPT_MASKS}, | |
a3a1dbf6 MM |
233 | {"401", PROCESSOR_PPC403, |
234 | MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS, | |
235 | POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64}, | |
49a0b204 | 236 | {"403", PROCESSOR_PPC403, |
daf11973 | 237 | MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS | MASK_STRICT_ALIGN, |
49a0b204 | 238 | POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64}, |
cf27b467 MM |
239 | {"505", PROCESSOR_MPCCORE, |
240 | MASK_POWERPC | MASK_NEW_MNEMONICS, | |
241 | POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64}, | |
5248c961 | 242 | {"601", PROCESSOR_PPC601, |
938937d8 | 243 | MASK_POWER | MASK_POWERPC | MASK_NEW_MNEMONICS | MASK_MULTIPLE | MASK_STRING, |
68c49ffa | 244 | MASK_POWER2 | POWERPC_OPT_MASKS | MASK_POWERPC64}, |
1ec26da6 | 245 | {"602", PROCESSOR_PPC603, |
cf27b467 MM |
246 | MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS, |
247 | POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64}, | |
5248c961 | 248 | {"603", PROCESSOR_PPC603, |
68c49ffa RK |
249 | MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS, |
250 | POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64}, | |
b6c9286a MM |
251 | {"603e", PROCESSOR_PPC603, |
252 | MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS, | |
253 | POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64}, | |
b5370a88 | 254 | {"ec603e", PROCESSOR_PPC603, |
a3a1dbf6 MM |
255 | MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS, |
256 | POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64}, | |
5248c961 | 257 | {"604", PROCESSOR_PPC604, |
b6c9286a MM |
258 | MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS, |
259 | POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64}, | |
cac8ce95 | 260 | {"604e", PROCESSOR_PPC604e, |
07e6159a MM |
261 | MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS, |
262 | POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64}, | |
b6c9286a | 263 | {"620", PROCESSOR_PPC620, |
68c49ffa | 264 | MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS, |
a260abc9 | 265 | POWER_MASKS | MASK_PPC_GPOPT}, |
3cb999d8 DE |
266 | {"630", PROCESSOR_PPC630, |
267 | MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS, | |
268 | POWER_MASKS | MASK_PPC_GPOPT}, | |
bef84347 VM |
269 | {"740", PROCESSOR_PPC750, |
270 | MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS, | |
271 | POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64}, | |
272 | {"750", PROCESSOR_PPC750, | |
273 | MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS, | |
274 | POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64}, | |
07e6159a MM |
275 | {"801", PROCESSOR_MPCCORE, |
276 | MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS, | |
277 | POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64}, | |
cf27b467 MM |
278 | {"821", PROCESSOR_MPCCORE, |
279 | MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS, | |
280 | POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64}, | |
07e6159a MM |
281 | {"823", PROCESSOR_MPCCORE, |
282 | MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS, | |
283 | POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64}, | |
cf27b467 MM |
284 | {"860", PROCESSOR_MPCCORE, |
285 | MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS, | |
286 | POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64}}; | |
5248c961 | 287 | |
c4d38ccb | 288 | size_t ptt_size = sizeof (processor_target_table) / sizeof (struct ptt); |
5248c961 | 289 | |
8a61d227 | 290 | int multiple = TARGET_MULTIPLE; /* save current -mmultiple/-mno-multiple status */ |
938937d8 | 291 | int string = TARGET_STRING; /* save current -mstring/-mno-string status */ |
8a61d227 | 292 | |
5248c961 RK |
293 | profile_block_flag = 0; |
294 | ||
295 | /* Identify the processor type */ | |
8e3f41e7 | 296 | rs6000_select[0].string = default_cpu; |
3cb999d8 | 297 | rs6000_cpu = TARGET_POWERPC64 ? PROCESSOR_DEFAULT64 : PROCESSOR_DEFAULT; |
8e3f41e7 | 298 | |
b6a1cbae | 299 | for (i = 0; i < ARRAY_SIZE (rs6000_select); i++) |
5248c961 | 300 | { |
8e3f41e7 MM |
301 | ptr = &rs6000_select[i]; |
302 | if (ptr->string != (char *)0 && ptr->string[0] != '\0') | |
5248c961 | 303 | { |
8e3f41e7 MM |
304 | for (j = 0; j < ptt_size; j++) |
305 | if (! strcmp (ptr->string, processor_target_table[j].name)) | |
306 | { | |
307 | if (ptr->set_tune_p) | |
308 | rs6000_cpu = processor_target_table[j].processor; | |
309 | ||
310 | if (ptr->set_arch_p) | |
311 | { | |
312 | target_flags |= processor_target_table[j].target_enable; | |
313 | target_flags &= ~processor_target_table[j].target_disable; | |
314 | } | |
315 | break; | |
316 | } | |
317 | ||
4406229e | 318 | if (j == ptt_size) |
8e3f41e7 | 319 | error ("bad value (%s) for %s switch", ptr->string, ptr->name); |
5248c961 RK |
320 | } |
321 | } | |
8a61d227 | 322 | |
ef792183 MM |
323 | /* If we are optimizing big endian systems for space, use the |
324 | store multiple instructions. */ | |
325 | if (BYTES_BIG_ENDIAN && optimize_size) | |
326 | target_flags |= MASK_MULTIPLE; | |
327 | ||
8a61d227 MM |
328 | /* If -mmultiple or -mno-multiple was explicitly used, don't |
329 | override with the processor default */ | |
330 | if (TARGET_MULTIPLE_SET) | |
331 | target_flags = (target_flags & ~MASK_MULTIPLE) | multiple; | |
7e69e155 | 332 | |
938937d8 MM |
333 | /* If -mstring or -mno-string was explicitly used, don't |
334 | override with the processor default */ | |
335 | if (TARGET_STRING_SET) | |
1f5515bf | 336 | target_flags = (target_flags & ~MASK_STRING) | string; |
938937d8 | 337 | |
bef84347 VM |
338 | /* Don't allow -mmultiple or -mstring on little endian systems unless the cpu |
339 | is a 750, because the hardware doesn't support the instructions used in | |
340 | little endian mode, and causes an alignment trap. The 750 does not cause | |
341 | an alignment trap (except when the target is unaligned). */ | |
342 | ||
bfc79d3b | 343 | if (! BYTES_BIG_ENDIAN && rs6000_cpu != PROCESSOR_PPC750) |
7e69e155 MM |
344 | { |
345 | if (TARGET_MULTIPLE) | |
346 | { | |
347 | target_flags &= ~MASK_MULTIPLE; | |
348 | if (TARGET_MULTIPLE_SET) | |
349 | warning ("-mmultiple is not supported on little endian systems"); | |
350 | } | |
351 | ||
352 | if (TARGET_STRING) | |
353 | { | |
354 | target_flags &= ~MASK_STRING; | |
938937d8 MM |
355 | if (TARGET_STRING_SET) |
356 | warning ("-mstring is not supported on little endian systems"); | |
7e69e155 MM |
357 | } |
358 | } | |
3933e0e1 | 359 | |
a260abc9 DE |
360 | if (flag_pic && (DEFAULT_ABI == ABI_AIX)) |
361 | { | |
362 | warning ("-f%s ignored for AIX (all code is position independent)", | |
363 | (flag_pic > 1) ? "PIC" : "pic"); | |
364 | flag_pic = 0; | |
365 | } | |
366 | ||
9861b0c9 DE |
367 | if (flag_function_sections && (write_symbols != NO_DEBUG) |
368 | && (DEFAULT_ABI == ABI_AIX)) | |
369 | { | |
370 | warning ("-ffunction-sections disabled on AIX when debugging"); | |
371 | flag_function_sections = 0; | |
372 | } | |
373 | ||
374 | if (flag_data_sections && (DEFAULT_ABI == ABI_AIX)) | |
375 | { | |
376 | warning ("-fdata-sections not supported on AIX"); | |
377 | flag_data_sections = 0; | |
378 | } | |
379 | ||
38c1f2d7 MM |
380 | /* Set debug flags */ |
381 | if (rs6000_debug_name) | |
382 | { | |
bfc79d3b | 383 | if (! strcmp (rs6000_debug_name, "all")) |
38c1f2d7 | 384 | rs6000_debug_stack = rs6000_debug_arg = 1; |
bfc79d3b | 385 | else if (! strcmp (rs6000_debug_name, "stack")) |
38c1f2d7 | 386 | rs6000_debug_stack = 1; |
bfc79d3b | 387 | else if (! strcmp (rs6000_debug_name, "arg")) |
38c1f2d7 MM |
388 | rs6000_debug_arg = 1; |
389 | else | |
390 | error ("Unknown -mdebug-%s switch", rs6000_debug_name); | |
391 | } | |
392 | ||
c81bebd7 MM |
393 | #ifdef TARGET_REGNAMES |
394 | /* If the user desires alternate register names, copy in the alternate names | |
395 | now. */ | |
396 | if (TARGET_REGNAMES) | |
4e135bdd | 397 | memcpy (rs6000_reg_names, alt_reg_names, sizeof (rs6000_reg_names)); |
c81bebd7 MM |
398 | #endif |
399 | ||
3933e0e1 MM |
400 | #ifdef SUBTARGET_OVERRIDE_OPTIONS |
401 | SUBTARGET_OVERRIDE_OPTIONS; | |
402 | #endif | |
c8023011 MM |
403 | |
404 | /* Register global variables with the garbage collector. */ | |
405 | rs6000_add_gc_roots (); | |
9ebbca7d GK |
406 | |
407 | /* Allocate an alias set for register saves & restores from stack. */ | |
408 | rs6000_sr_alias_set = new_alias_set (); | |
409 | ||
410 | if (TARGET_TOC) | |
411 | ASM_GENERATE_INTERNAL_LABEL (toc_label_name, "LCTOC", 1); | |
71f123ca FS |
412 | |
413 | /* Arrange to save and restore machine status around nested functions. */ | |
414 | init_machine_status = rs6000_init_machine_status; | |
71f123ca | 415 | free_machine_status = rs6000_free_machine_status; |
5248c961 | 416 | } |
5accd822 DE |
417 | |
418 | void | |
419 | optimization_options (level, size) | |
e2c953b6 | 420 | int level ATTRIBUTE_UNUSED; |
5accd822 DE |
421 | int size ATTRIBUTE_UNUSED; |
422 | { | |
5accd822 | 423 | } |
3cfa4909 MM |
424 | \f |
425 | /* Do anything needed at the start of the asm file. */ | |
426 | ||
427 | void | |
428 | rs6000_file_start (file, default_cpu) | |
429 | FILE *file; | |
d330fd93 | 430 | const char *default_cpu; |
3cfa4909 | 431 | { |
c4d38ccb | 432 | size_t i; |
3cfa4909 | 433 | char buffer[80]; |
d330fd93 | 434 | const char *start = buffer; |
3cfa4909 MM |
435 | struct rs6000_cpu_select *ptr; |
436 | ||
437 | if (flag_verbose_asm) | |
438 | { | |
439 | sprintf (buffer, "\n%s rs6000/powerpc options:", ASM_COMMENT_START); | |
440 | rs6000_select[0].string = default_cpu; | |
441 | ||
b6a1cbae | 442 | for (i = 0; i < ARRAY_SIZE (rs6000_select); i++) |
3cfa4909 MM |
443 | { |
444 | ptr = &rs6000_select[i]; | |
445 | if (ptr->string != (char *)0 && ptr->string[0] != '\0') | |
446 | { | |
447 | fprintf (file, "%s %s%s", start, ptr->name, ptr->string); | |
448 | start = ""; | |
449 | } | |
450 | } | |
451 | ||
452 | #ifdef USING_SVR4_H | |
453 | switch (rs6000_sdata) | |
454 | { | |
455 | case SDATA_NONE: fprintf (file, "%s -msdata=none", start); start = ""; break; | |
456 | case SDATA_DATA: fprintf (file, "%s -msdata=data", start); start = ""; break; | |
457 | case SDATA_SYSV: fprintf (file, "%s -msdata=sysv", start); start = ""; break; | |
458 | case SDATA_EABI: fprintf (file, "%s -msdata=eabi", start); start = ""; break; | |
459 | } | |
460 | ||
461 | if (rs6000_sdata && g_switch_value) | |
462 | { | |
463 | fprintf (file, "%s -G %d", start, g_switch_value); | |
464 | start = ""; | |
465 | } | |
466 | #endif | |
467 | ||
468 | if (*start == '\0') | |
949ea356 | 469 | putc ('\n', file); |
3cfa4909 MM |
470 | } |
471 | } | |
472 | ||
24d304eb RK |
473 | \f |
474 | /* Create a CONST_DOUBLE from a string. */ | |
475 | ||
476 | struct rtx_def * | |
477 | rs6000_float_const (string, mode) | |
d330fd93 | 478 | const char *string; |
24d304eb RK |
479 | enum machine_mode mode; |
480 | { | |
ca5adc63 GK |
481 | REAL_VALUE_TYPE value; |
482 | value = REAL_VALUE_ATOF (string, mode); | |
24d304eb RK |
483 | return immed_real_const_1 (value, mode); |
484 | } | |
5248c961 | 485 | \f |
9878760c RK |
486 | /* Return non-zero if this function is known to have a null epilogue. */ |
487 | ||
488 | int | |
489 | direct_return () | |
490 | { | |
4697a36c MM |
491 | if (reload_completed) |
492 | { | |
493 | rs6000_stack_t *info = rs6000_stack_info (); | |
494 | ||
495 | if (info->first_gp_reg_save == 32 | |
496 | && info->first_fp_reg_save == 64 | |
c81fc13e DE |
497 | && ! info->lr_save_p |
498 | && ! info->cr_save_p | |
499 | && ! info->push_p) | |
4697a36c MM |
500 | return 1; |
501 | } | |
502 | ||
503 | return 0; | |
9878760c RK |
504 | } |
505 | ||
506 | /* Returns 1 always. */ | |
507 | ||
508 | int | |
509 | any_operand (op, mode) | |
296b8152 KG |
510 | register rtx op ATTRIBUTE_UNUSED; |
511 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
9878760c RK |
512 | { |
513 | return 1; | |
514 | } | |
515 | ||
b6c9286a | 516 | /* Returns 1 if op is the count register */ |
38c1f2d7 MM |
517 | int |
518 | count_register_operand(op, mode) | |
b6c9286a | 519 | register rtx op; |
296b8152 | 520 | enum machine_mode mode ATTRIBUTE_UNUSED; |
b6c9286a MM |
521 | { |
522 | if (GET_CODE (op) != REG) | |
523 | return 0; | |
524 | ||
525 | if (REGNO (op) == COUNT_REGISTER_REGNUM) | |
526 | return 1; | |
527 | ||
528 | if (REGNO (op) > FIRST_PSEUDO_REGISTER) | |
529 | return 1; | |
530 | ||
531 | return 0; | |
532 | } | |
533 | ||
38c1f2d7 | 534 | int |
9ebbca7d | 535 | xer_operand(op, mode) |
802a0058 | 536 | register rtx op; |
296b8152 | 537 | enum machine_mode mode ATTRIBUTE_UNUSED; |
802a0058 MM |
538 | { |
539 | if (GET_CODE (op) != REG) | |
540 | return 0; | |
541 | ||
9ebbca7d | 542 | if (XER_REGNO_P (REGNO (op))) |
802a0058 MM |
543 | return 1; |
544 | ||
802a0058 MM |
545 | return 0; |
546 | } | |
547 | ||
9878760c RK |
548 | /* Return 1 if OP is a constant that can fit in a D field. */ |
549 | ||
550 | int | |
551 | short_cint_operand (op, mode) | |
552 | register rtx op; | |
296b8152 | 553 | enum machine_mode mode ATTRIBUTE_UNUSED; |
9878760c | 554 | { |
5f59ecb7 DE |
555 | return (GET_CODE (op) == CONST_INT |
556 | && CONST_OK_FOR_LETTER_P (INTVAL (op), 'I')); | |
9878760c RK |
557 | } |
558 | ||
559 | /* Similar for a unsigned D field. */ | |
560 | ||
561 | int | |
562 | u_short_cint_operand (op, mode) | |
563 | register rtx op; | |
296b8152 | 564 | enum machine_mode mode ATTRIBUTE_UNUSED; |
9878760c | 565 | { |
19684119 | 566 | return (GET_CODE (op) == CONST_INT |
5f59ecb7 | 567 | && CONST_OK_FOR_LETTER_P (INTVAL (op), 'K')); |
9878760c RK |
568 | } |
569 | ||
dcfedcd0 RK |
570 | /* Return 1 if OP is a CONST_INT that cannot fit in a signed D field. */ |
571 | ||
572 | int | |
573 | non_short_cint_operand (op, mode) | |
574 | register rtx op; | |
296b8152 | 575 | enum machine_mode mode ATTRIBUTE_UNUSED; |
dcfedcd0 RK |
576 | { |
577 | return (GET_CODE (op) == CONST_INT | |
a7653a2c | 578 | && (unsigned HOST_WIDE_INT) (INTVAL (op) + 0x8000) >= 0x10000); |
dcfedcd0 RK |
579 | } |
580 | ||
9878760c RK |
581 | /* Returns 1 if OP is a register that is not special (i.e., not MQ, |
582 | ctr, or lr). */ | |
583 | ||
584 | int | |
cd2b37d9 | 585 | gpc_reg_operand (op, mode) |
9878760c RK |
586 | register rtx op; |
587 | enum machine_mode mode; | |
588 | { | |
589 | return (register_operand (op, mode) | |
802a0058 | 590 | && (GET_CODE (op) != REG |
9ebbca7d GK |
591 | || (REGNO (op) >= ARG_POINTER_REGNUM |
592 | && !XER_REGNO_P (REGNO (op))) | |
593 | || REGNO (op) < MQ_REGNO)); | |
9878760c RK |
594 | } |
595 | ||
596 | /* Returns 1 if OP is either a pseudo-register or a register denoting a | |
597 | CR field. */ | |
598 | ||
599 | int | |
600 | cc_reg_operand (op, mode) | |
601 | register rtx op; | |
602 | enum machine_mode mode; | |
603 | { | |
604 | return (register_operand (op, mode) | |
605 | && (GET_CODE (op) != REG | |
606 | || REGNO (op) >= FIRST_PSEUDO_REGISTER | |
607 | || CR_REGNO_P (REGNO (op)))); | |
608 | } | |
609 | ||
815cdc52 MM |
610 | /* Returns 1 if OP is either a pseudo-register or a register denoting a |
611 | CR field that isn't CR0. */ | |
612 | ||
613 | int | |
614 | cc_reg_not_cr0_operand (op, mode) | |
615 | register rtx op; | |
616 | enum machine_mode mode; | |
617 | { | |
618 | return (register_operand (op, mode) | |
619 | && (GET_CODE (op) != REG | |
620 | || REGNO (op) >= FIRST_PSEUDO_REGISTER | |
621 | || CR_REGNO_NOT_CR0_P (REGNO (op)))); | |
622 | } | |
623 | ||
9878760c RK |
624 | /* Returns 1 if OP is either a constant integer valid for a D-field or a |
625 | non-special register. If a register, it must be in the proper mode unless | |
626 | MODE is VOIDmode. */ | |
627 | ||
628 | int | |
629 | reg_or_short_operand (op, mode) | |
630 | register rtx op; | |
631 | enum machine_mode mode; | |
632 | { | |
f5a28898 | 633 | return short_cint_operand (op, mode) || gpc_reg_operand (op, mode); |
9878760c RK |
634 | } |
635 | ||
636 | /* Similar, except check if the negation of the constant would be valid for | |
637 | a D-field. */ | |
638 | ||
639 | int | |
640 | reg_or_neg_short_operand (op, mode) | |
641 | register rtx op; | |
642 | enum machine_mode mode; | |
643 | { | |
644 | if (GET_CODE (op) == CONST_INT) | |
645 | return CONST_OK_FOR_LETTER_P (INTVAL (op), 'P'); | |
646 | ||
cd2b37d9 | 647 | return gpc_reg_operand (op, mode); |
9878760c RK |
648 | } |
649 | ||
650 | /* Return 1 if the operand is either a register or an integer whose high-order | |
651 | 16 bits are zero. */ | |
652 | ||
653 | int | |
654 | reg_or_u_short_operand (op, mode) | |
655 | register rtx op; | |
656 | enum machine_mode mode; | |
657 | { | |
e675f625 | 658 | return u_short_cint_operand (op, mode) || gpc_reg_operand (op, mode); |
9878760c RK |
659 | } |
660 | ||
661 | /* Return 1 is the operand is either a non-special register or ANY | |
662 | constant integer. */ | |
663 | ||
664 | int | |
665 | reg_or_cint_operand (op, mode) | |
666 | register rtx op; | |
667 | enum machine_mode mode; | |
668 | { | |
f6bf7de2 DE |
669 | return (GET_CODE (op) == CONST_INT || gpc_reg_operand (op, mode)); |
670 | } | |
671 | ||
672 | /* Return 1 is the operand is either a non-special register or ANY | |
673 | 32-bit signed constant integer. */ | |
674 | ||
675 | int | |
676 | reg_or_arith_cint_operand (op, mode) | |
677 | register rtx op; | |
678 | enum machine_mode mode; | |
679 | { | |
680 | return (gpc_reg_operand (op, mode) | |
681 | || (GET_CODE (op) == CONST_INT | |
682 | #if HOST_BITS_PER_WIDE_INT != 32 | |
683 | && ((unsigned HOST_WIDE_INT) (INTVAL (op) + 0x80000000) | |
78e1b90d | 684 | < (unsigned HOST_WIDE_INT) 0x100000000ll) |
f6bf7de2 DE |
685 | #endif |
686 | )); | |
9878760c RK |
687 | } |
688 | ||
9ebbca7d GK |
689 | /* Return 1 is the operand is either a non-special register or ANY |
690 | 32-bit unsigned constant integer. */ | |
691 | ||
692 | int | |
1d328b19 | 693 | reg_or_logical_cint_operand (op, mode) |
9ebbca7d GK |
694 | register rtx op; |
695 | enum machine_mode mode; | |
696 | { | |
1d328b19 GK |
697 | if (GET_CODE (op) == CONST_INT) |
698 | { | |
699 | if (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT) | |
700 | { | |
701 | if (GET_MODE_BITSIZE (mode) <= 32) | |
702 | abort(); | |
703 | ||
704 | if (INTVAL (op) < 0) | |
705 | return 0; | |
706 | } | |
707 | ||
708 | return ((INTVAL (op) & GET_MODE_MASK (mode) | |
0858c623 | 709 | & (~ (unsigned HOST_WIDE_INT) 0xffffffff)) == 0); |
1d328b19 GK |
710 | } |
711 | else if (GET_CODE (op) == CONST_DOUBLE) | |
712 | { | |
713 | if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT | |
714 | || mode != DImode) | |
715 | abort(); | |
716 | ||
717 | return CONST_DOUBLE_HIGH (op) == 0; | |
718 | } | |
719 | else | |
720 | return gpc_reg_operand (op, mode); | |
9ebbca7d GK |
721 | } |
722 | ||
766a866c MM |
723 | /* Return 1 if the operand is an operand that can be loaded via the GOT */ |
724 | ||
725 | int | |
726 | got_operand (op, mode) | |
727 | register rtx op; | |
296b8152 | 728 | enum machine_mode mode ATTRIBUTE_UNUSED; |
766a866c MM |
729 | { |
730 | return (GET_CODE (op) == SYMBOL_REF | |
731 | || GET_CODE (op) == CONST | |
732 | || GET_CODE (op) == LABEL_REF); | |
733 | } | |
734 | ||
38c1f2d7 MM |
735 | /* Return 1 if the operand is a simple references that can be loaded via |
736 | the GOT (labels involving addition aren't allowed). */ | |
737 | ||
738 | int | |
739 | got_no_const_operand (op, mode) | |
740 | register rtx op; | |
296b8152 | 741 | enum machine_mode mode ATTRIBUTE_UNUSED; |
38c1f2d7 MM |
742 | { |
743 | return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF); | |
744 | } | |
745 | ||
4e74d8ec MM |
746 | /* Return the number of instructions it takes to form a constant in an |
747 | integer register. */ | |
748 | ||
749 | static int | |
750 | num_insns_constant_wide (value) | |
751 | HOST_WIDE_INT value; | |
752 | { | |
753 | /* signed constant loadable with {cal|addi} */ | |
5f59ecb7 | 754 | if (CONST_OK_FOR_LETTER_P (value, 'I')) |
0865c631 GK |
755 | return 1; |
756 | ||
4e74d8ec | 757 | /* constant loadable with {cau|addis} */ |
5f59ecb7 | 758 | else if (CONST_OK_FOR_LETTER_P (value, 'L')) |
4e74d8ec MM |
759 | return 1; |
760 | ||
5f59ecb7 | 761 | #if HOST_BITS_PER_WIDE_INT == 64 |
c81fc13e | 762 | else if (TARGET_POWERPC64) |
4e74d8ec | 763 | { |
0d30d435 | 764 | HOST_WIDE_INT low = value & 0xffffffff; |
4e74d8ec MM |
765 | HOST_WIDE_INT high = value >> 32; |
766 | ||
0d30d435 DE |
767 | low = (low ^ 0x80000000) - 0x80000000; /* sign extend */ |
768 | ||
0858c623 | 769 | if (high == 0 && (low & 0x80000000) == 0) |
4e74d8ec MM |
770 | return 2; |
771 | ||
0858c623 | 772 | else if (high == -1 && (low & 0x80000000) != 0) |
4e74d8ec MM |
773 | return 2; |
774 | ||
c81fc13e | 775 | else if (! low) |
4e74d8ec MM |
776 | return num_insns_constant_wide (high) + 1; |
777 | ||
778 | else | |
779 | return (num_insns_constant_wide (high) | |
e396202a | 780 | + num_insns_constant_wide (low) + 1); |
4e74d8ec MM |
781 | } |
782 | #endif | |
783 | ||
784 | else | |
785 | return 2; | |
786 | } | |
787 | ||
788 | int | |
789 | num_insns_constant (op, mode) | |
790 | rtx op; | |
791 | enum machine_mode mode; | |
792 | { | |
4e74d8ec | 793 | if (GET_CODE (op) == CONST_INT) |
0d30d435 DE |
794 | { |
795 | #if HOST_BITS_PER_WIDE_INT == 64 | |
796 | if (mask64_operand (op, mode)) | |
797 | return 2; | |
798 | else | |
799 | #endif | |
800 | return num_insns_constant_wide (INTVAL (op)); | |
801 | } | |
4e74d8ec | 802 | |
6fc48950 MM |
803 | else if (GET_CODE (op) == CONST_DOUBLE && mode == SFmode) |
804 | { | |
805 | long l; | |
806 | REAL_VALUE_TYPE rv; | |
807 | ||
808 | REAL_VALUE_FROM_CONST_DOUBLE (rv, op); | |
809 | REAL_VALUE_TO_TARGET_SINGLE (rv, l); | |
810 | return num_insns_constant_wide ((HOST_WIDE_INT)l); | |
811 | } | |
812 | ||
47ad8c61 | 813 | else if (GET_CODE (op) == CONST_DOUBLE) |
4e74d8ec | 814 | { |
47ad8c61 MM |
815 | HOST_WIDE_INT low; |
816 | HOST_WIDE_INT high; | |
817 | long l[2]; | |
818 | REAL_VALUE_TYPE rv; | |
819 | int endian = (WORDS_BIG_ENDIAN == 0); | |
4e74d8ec | 820 | |
47ad8c61 MM |
821 | if (mode == VOIDmode || mode == DImode) |
822 | { | |
823 | high = CONST_DOUBLE_HIGH (op); | |
824 | low = CONST_DOUBLE_LOW (op); | |
825 | } | |
826 | else | |
827 | { | |
828 | REAL_VALUE_FROM_CONST_DOUBLE (rv, op); | |
829 | REAL_VALUE_TO_TARGET_DOUBLE (rv, l); | |
830 | high = l[endian]; | |
831 | low = l[1 - endian]; | |
832 | } | |
4e74d8ec | 833 | |
47ad8c61 MM |
834 | if (TARGET_32BIT) |
835 | return (num_insns_constant_wide (low) | |
836 | + num_insns_constant_wide (high)); | |
4e74d8ec MM |
837 | |
838 | else | |
47ad8c61 | 839 | { |
0858c623 | 840 | if (high == 0 && (low & 0x80000000) == 0) |
47ad8c61 MM |
841 | return num_insns_constant_wide (low); |
842 | ||
0858c623 | 843 | else if (high == -1 && (low & 0x80000000) != 0) |
47ad8c61 MM |
844 | return num_insns_constant_wide (low); |
845 | ||
a260abc9 DE |
846 | else if (mask64_operand (op, mode)) |
847 | return 2; | |
848 | ||
47ad8c61 MM |
849 | else if (low == 0) |
850 | return num_insns_constant_wide (high) + 1; | |
851 | ||
852 | else | |
853 | return (num_insns_constant_wide (high) | |
854 | + num_insns_constant_wide (low) + 1); | |
855 | } | |
4e74d8ec MM |
856 | } |
857 | ||
858 | else | |
859 | abort (); | |
860 | } | |
861 | ||
6f2f8311 RK |
862 | /* Return 1 if the operand is a CONST_DOUBLE and it can be put into a register |
863 | with one instruction per word. We only do this if we can safely read | |
864 | CONST_DOUBLE_{LOW,HIGH}. */ | |
9878760c RK |
865 | |
866 | int | |
867 | easy_fp_constant (op, mode) | |
868 | register rtx op; | |
869 | register enum machine_mode mode; | |
870 | { | |
9878760c RK |
871 | if (GET_CODE (op) != CONST_DOUBLE |
872 | || GET_MODE (op) != mode | |
4e74d8ec | 873 | || (GET_MODE_CLASS (mode) != MODE_FLOAT && mode != DImode)) |
9878760c RK |
874 | return 0; |
875 | ||
b6c9286a | 876 | /* Consider all constants with -msoft-float to be easy */ |
4e74d8ec | 877 | if (TARGET_SOFT_FLOAT && mode != DImode) |
b6c9286a MM |
878 | return 1; |
879 | ||
a7273471 MM |
880 | /* If we are using V.4 style PIC, consider all constants to be hard */ |
881 | if (flag_pic && (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS)) | |
882 | return 0; | |
883 | ||
5ae4759c MM |
884 | #ifdef TARGET_RELOCATABLE |
885 | /* Similarly if we are using -mrelocatable, consider all constants to be hard */ | |
886 | if (TARGET_RELOCATABLE) | |
887 | return 0; | |
888 | #endif | |
889 | ||
042259f2 DE |
890 | if (mode == DFmode) |
891 | { | |
892 | long k[2]; | |
893 | REAL_VALUE_TYPE rv; | |
894 | ||
895 | REAL_VALUE_FROM_CONST_DOUBLE (rv, op); | |
896 | REAL_VALUE_TO_TARGET_DOUBLE (rv, k); | |
9878760c | 897 | |
4e74d8ec MM |
898 | return (num_insns_constant_wide ((HOST_WIDE_INT)k[0]) == 1 |
899 | && num_insns_constant_wide ((HOST_WIDE_INT)k[1]) == 1); | |
042259f2 | 900 | } |
4e74d8ec MM |
901 | |
902 | else if (mode == SFmode) | |
042259f2 DE |
903 | { |
904 | long l; | |
905 | REAL_VALUE_TYPE rv; | |
906 | ||
907 | REAL_VALUE_FROM_CONST_DOUBLE (rv, op); | |
908 | REAL_VALUE_TO_TARGET_SINGLE (rv, l); | |
9878760c | 909 | |
4e74d8ec | 910 | return num_insns_constant_wide (l) == 1; |
042259f2 | 911 | } |
4e74d8ec | 912 | |
a260abc9 | 913 | else if (mode == DImode) |
c81fc13e | 914 | return ((TARGET_POWERPC64 |
a260abc9 DE |
915 | && GET_CODE (op) == CONST_DOUBLE && CONST_DOUBLE_LOW (op) == 0) |
916 | || (num_insns_constant (op, DImode) <= 2)); | |
4e74d8ec | 917 | |
a9098fd0 GK |
918 | else if (mode == SImode) |
919 | return 1; | |
4e74d8ec MM |
920 | else |
921 | abort (); | |
9878760c | 922 | } |
8f75773e | 923 | |
50a0b056 GK |
924 | /* Return 1 if the operand is 0.0. */ |
925 | int | |
926 | zero_fp_constant (op, mode) | |
927 | register rtx op; | |
928 | register enum machine_mode mode; | |
929 | { | |
930 | return GET_MODE_CLASS (mode) == MODE_FLOAT && op == CONST0_RTX (mode); | |
931 | } | |
932 | ||
b6c9286a MM |
933 | /* Return 1 if the operand is in volatile memory. Note that during the |
934 | RTL generation phase, memory_operand does not return TRUE for | |
935 | volatile memory references. So this function allows us to | |
936 | recognize volatile references where its safe. */ | |
937 | ||
938 | int | |
939 | volatile_mem_operand (op, mode) | |
940 | register rtx op; | |
941 | enum machine_mode mode; | |
942 | { | |
943 | if (GET_CODE (op) != MEM) | |
944 | return 0; | |
945 | ||
946 | if (!MEM_VOLATILE_P (op)) | |
947 | return 0; | |
948 | ||
949 | if (mode != GET_MODE (op)) | |
950 | return 0; | |
951 | ||
952 | if (reload_completed) | |
953 | return memory_operand (op, mode); | |
954 | ||
955 | if (reload_in_progress) | |
956 | return strict_memory_address_p (mode, XEXP (op, 0)); | |
957 | ||
958 | return memory_address_p (mode, XEXP (op, 0)); | |
959 | } | |
960 | ||
97f6e72f | 961 | /* Return 1 if the operand is an offsettable memory operand. */ |
914c2e77 RK |
962 | |
963 | int | |
97f6e72f | 964 | offsettable_mem_operand (op, mode) |
914c2e77 RK |
965 | register rtx op; |
966 | enum machine_mode mode; | |
967 | { | |
97f6e72f | 968 | return ((GET_CODE (op) == MEM) |
677a9668 | 969 | && offsettable_address_p (reload_completed || reload_in_progress, |
97f6e72f | 970 | mode, XEXP (op, 0))); |
914c2e77 RK |
971 | } |
972 | ||
9878760c RK |
973 | /* Return 1 if the operand is either an easy FP constant (see above) or |
974 | memory. */ | |
975 | ||
976 | int | |
977 | mem_or_easy_const_operand (op, mode) | |
978 | register rtx op; | |
979 | enum machine_mode mode; | |
980 | { | |
981 | return memory_operand (op, mode) || easy_fp_constant (op, mode); | |
982 | } | |
983 | ||
984 | /* Return 1 if the operand is either a non-special register or an item | |
5f59ecb7 | 985 | that can be used as the operand of a `mode' add insn. */ |
9878760c RK |
986 | |
987 | int | |
988 | add_operand (op, mode) | |
989 | register rtx op; | |
990 | enum machine_mode mode; | |
991 | { | |
992 | return (reg_or_short_operand (op, mode) | |
19684119 | 993 | || (GET_CODE (op) == CONST_INT |
38886f37 | 994 | && CONST_OK_FOR_LETTER_P (INTVAL (op), 'L'))); |
9878760c RK |
995 | } |
996 | ||
dcfedcd0 RK |
997 | /* Return 1 if OP is a constant but not a valid add_operand. */ |
998 | ||
999 | int | |
1000 | non_add_cint_operand (op, mode) | |
1001 | register rtx op; | |
296b8152 | 1002 | enum machine_mode mode ATTRIBUTE_UNUSED; |
dcfedcd0 RK |
1003 | { |
1004 | return (GET_CODE (op) == CONST_INT | |
a7653a2c | 1005 | && (unsigned HOST_WIDE_INT) (INTVAL (op) + 0x8000) >= 0x10000 |
38886f37 | 1006 | && ! CONST_OK_FOR_LETTER_P (INTVAL (op), 'L')); |
dcfedcd0 RK |
1007 | } |
1008 | ||
9878760c RK |
1009 | /* Return 1 if the operand is a non-special register or a constant that |
1010 | can be used as the operand of an OR or XOR insn on the RS/6000. */ | |
1011 | ||
1012 | int | |
1013 | logical_operand (op, mode) | |
1014 | register rtx op; | |
1015 | enum machine_mode mode; | |
1016 | { | |
1d328b19 GK |
1017 | /* an unsigned representation of 'op'. */ |
1018 | unsigned HOST_WIDE_INT opl, oph; | |
1019 | ||
dfbdccdb GK |
1020 | if (gpc_reg_operand (op, mode)) |
1021 | return 1; | |
1d328b19 | 1022 | |
dfbdccdb | 1023 | if (GET_CODE (op) == CONST_INT) |
38886f37 | 1024 | opl = INTVAL (op); |
dfbdccdb GK |
1025 | else if (GET_CODE (op) == CONST_DOUBLE) |
1026 | { | |
1d328b19 GK |
1027 | if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT) |
1028 | abort(); | |
1029 | ||
1030 | opl = CONST_DOUBLE_LOW (op); | |
1031 | oph = CONST_DOUBLE_HIGH (op); | |
38886f37 AO |
1032 | |
1033 | if (oph != ((unsigned HOST_WIDE_INT)0 | |
1034 | - ((opl & ((unsigned HOST_WIDE_INT)1 | |
1035 | << (HOST_BITS_PER_WIDE_INT - 1))) != 0))) | |
1036 | return 0; | |
dfbdccdb GK |
1037 | } |
1038 | else | |
1039 | return 0; | |
1d328b19 | 1040 | |
38886f37 | 1041 | /* This must really be SImode, not MODE. */ |
78e1b90d | 1042 | if (opl != (unsigned HOST_WIDE_INT) trunc_int_for_mode (opl, SImode)) |
38886f37 AO |
1043 | return 0; |
1044 | ||
1045 | return ((opl & 0xffff) == 0 | |
1046 | || (opl & ~ (unsigned HOST_WIDE_INT) 0xffff) == 0); | |
9878760c RK |
1047 | } |
1048 | ||
dcfedcd0 | 1049 | /* Return 1 if C is a constant that is not a logical operand (as |
1d328b19 | 1050 | above), but could be split into one. */ |
dcfedcd0 RK |
1051 | |
1052 | int | |
1053 | non_logical_cint_operand (op, mode) | |
1054 | register rtx op; | |
5f59ecb7 | 1055 | enum machine_mode mode; |
dcfedcd0 | 1056 | { |
dfbdccdb | 1057 | return ((GET_CODE (op) == CONST_INT || GET_CODE (op) == CONST_DOUBLE) |
1d328b19 GK |
1058 | && ! logical_operand (op, mode) |
1059 | && reg_or_logical_cint_operand (op, mode)); | |
dcfedcd0 RK |
1060 | } |
1061 | ||
19ba8161 | 1062 | /* Return 1 if C is a constant that can be encoded in a 32-bit mask on the |
9878760c RK |
1063 | RS/6000. It is if there are no more than two 1->0 or 0->1 transitions. |
1064 | Reject all ones and all zeros, since these should have been optimized | |
1065 | away and confuse the making of MB and ME. */ | |
1066 | ||
1067 | int | |
19ba8161 DE |
1068 | mask_operand (op, mode) |
1069 | register rtx op; | |
1070 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
9878760c | 1071 | { |
19ba8161 | 1072 | HOST_WIDE_INT c; |
9878760c RK |
1073 | int i; |
1074 | int last_bit_value; | |
1075 | int transitions = 0; | |
1076 | ||
19ba8161 DE |
1077 | if (GET_CODE (op) != CONST_INT) |
1078 | return 0; | |
1079 | ||
1080 | c = INTVAL (op); | |
1081 | ||
9878760c RK |
1082 | if (c == 0 || c == ~0) |
1083 | return 0; | |
1084 | ||
1085 | last_bit_value = c & 1; | |
1086 | ||
1087 | for (i = 1; i < 32; i++) | |
1088 | if (((c >>= 1) & 1) != last_bit_value) | |
1089 | last_bit_value ^= 1, transitions++; | |
1090 | ||
1091 | return transitions <= 2; | |
1092 | } | |
1093 | ||
a260abc9 DE |
1094 | /* Return 1 if the operand is a constant that is a PowerPC64 mask. |
1095 | It is if there are no more than one 1->0 or 0->1 transitions. | |
1096 | Reject all ones and all zeros, since these should have been optimized | |
1097 | away and confuse the making of MB and ME. */ | |
9878760c RK |
1098 | |
1099 | int | |
a260abc9 DE |
1100 | mask64_operand (op, mode) |
1101 | register rtx op; | |
1102 | enum machine_mode mode; | |
1103 | { | |
1104 | if (GET_CODE (op) == CONST_INT) | |
1105 | { | |
1106 | HOST_WIDE_INT c = INTVAL (op); | |
1107 | int i; | |
1108 | int last_bit_value; | |
1109 | int transitions = 0; | |
1110 | ||
1111 | if (c == 0 || c == ~0) | |
1112 | return 0; | |
1113 | ||
1114 | last_bit_value = c & 1; | |
1115 | ||
1116 | for (i = 1; i < HOST_BITS_PER_WIDE_INT; i++) | |
1117 | if (((c >>= 1) & 1) != last_bit_value) | |
1118 | last_bit_value ^= 1, transitions++; | |
1119 | ||
e2c953b6 DE |
1120 | return transitions <= 1; |
1121 | } | |
1122 | else if (GET_CODE (op) == CONST_DOUBLE | |
1123 | && (mode == VOIDmode || mode == DImode)) | |
1124 | { | |
1125 | HOST_WIDE_INT low = CONST_DOUBLE_LOW (op); | |
1126 | #if HOST_BITS_PER_WIDE_INT == 32 | |
1127 | HOST_WIDE_INT high = CONST_DOUBLE_HIGH (op); | |
1128 | #endif | |
1129 | int i; | |
1130 | int last_bit_value; | |
1131 | int transitions = 0; | |
1132 | ||
1133 | if ((low == 0 | |
1134 | #if HOST_BITS_PER_WIDE_INT == 32 | |
1135 | && high == 0 | |
1136 | #endif | |
1137 | ) | |
1138 | || (low == ~0 | |
1139 | #if HOST_BITS_PER_WIDE_INT == 32 | |
1140 | && high == ~0 | |
1141 | #endif | |
1142 | )) | |
1143 | return 0; | |
1144 | ||
1145 | last_bit_value = low & 1; | |
1146 | ||
1147 | for (i = 1; i < HOST_BITS_PER_WIDE_INT; i++) | |
1148 | if (((low >>= 1) & 1) != last_bit_value) | |
1149 | last_bit_value ^= 1, transitions++; | |
1150 | ||
a238cd8b | 1151 | #if HOST_BITS_PER_WIDE_INT == 32 |
e2c953b6 DE |
1152 | if ((high & 1) != last_bit_value) |
1153 | last_bit_value ^= 1, transitions++; | |
1154 | ||
1155 | for (i = 1; i < HOST_BITS_PER_WIDE_INT; i++) | |
1156 | if (((high >>= 1) & 1) != last_bit_value) | |
1157 | last_bit_value ^= 1, transitions++; | |
a260abc9 DE |
1158 | #endif |
1159 | ||
1160 | return transitions <= 1; | |
1161 | } | |
e2c953b6 DE |
1162 | else |
1163 | return 0; | |
1164 | } | |
1165 | ||
1166 | /* Return 1 if the operand is a constant that is a PowerPC64 mask. | |
1167 | It is if there are no more than two 1->0 or 0->1 transitions. | |
1168 | Reject all ones and all zeros, since these should have been optimized | |
1169 | away and confuse the making of MB and ME. */ | |
1170 | ||
1171 | int | |
1172 | rldic_operand (op, mode) | |
1173 | register rtx op; | |
1174 | enum machine_mode mode; | |
1175 | { | |
1176 | if (GET_CODE (op) == CONST_INT) | |
1177 | { | |
1178 | HOST_WIDE_INT c = INTVAL (op); | |
1179 | int i; | |
1180 | int last_bit_value; | |
1181 | int transitions = 0; | |
1182 | ||
1183 | if (c == 0 || c == ~0) | |
1184 | return 0; | |
1185 | ||
1186 | last_bit_value = c & 1; | |
1187 | ||
1188 | for (i = 1; i < HOST_BITS_PER_WIDE_INT; i++) | |
1189 | if (((c >>= 1) & 1) != last_bit_value) | |
1190 | last_bit_value ^= 1, transitions++; | |
1191 | ||
1192 | return transitions <= 2; | |
1193 | } | |
a260abc9 DE |
1194 | else if (GET_CODE (op) == CONST_DOUBLE |
1195 | && (mode == VOIDmode || mode == DImode)) | |
1196 | { | |
1197 | HOST_WIDE_INT low = CONST_DOUBLE_LOW (op); | |
a238cd8b | 1198 | #if HOST_BITS_PER_WIDE_INT == 32 |
a260abc9 DE |
1199 | HOST_WIDE_INT high = CONST_DOUBLE_HIGH (op); |
1200 | #endif | |
1201 | int i; | |
1202 | int last_bit_value; | |
1203 | int transitions = 0; | |
1204 | ||
1205 | if ((low == 0 | |
a238cd8b | 1206 | #if HOST_BITS_PER_WIDE_INT == 32 |
a260abc9 DE |
1207 | && high == 0 |
1208 | #endif | |
1209 | ) | |
1210 | || (low == ~0 | |
a238cd8b | 1211 | #if HOST_BITS_PER_WIDE_INT == 32 |
a260abc9 DE |
1212 | && high == ~0 |
1213 | #endif | |
1214 | )) | |
1215 | return 0; | |
1216 | ||
1217 | last_bit_value = low & 1; | |
1218 | ||
1219 | for (i = 1; i < HOST_BITS_PER_WIDE_INT; i++) | |
1220 | if (((low >>= 1) & 1) != last_bit_value) | |
1221 | last_bit_value ^= 1, transitions++; | |
1222 | ||
a238cd8b | 1223 | #if HOST_BITS_PER_WIDE_INT == 32 |
a260abc9 DE |
1224 | if ((high & 1) != last_bit_value) |
1225 | last_bit_value ^= 1, transitions++; | |
1226 | ||
1227 | for (i = 1; i < HOST_BITS_PER_WIDE_INT; i++) | |
1228 | if (((high >>= 1) & 1) != last_bit_value) | |
1229 | last_bit_value ^= 1, transitions++; | |
1230 | #endif | |
1231 | ||
e2c953b6 | 1232 | return transitions <= 2; |
a260abc9 DE |
1233 | } |
1234 | else | |
1235 | return 0; | |
1236 | } | |
1237 | ||
1238 | /* Return 1 if the operand is either a non-special register or a constant | |
1239 | that can be used as the operand of a PowerPC64 logical AND insn. */ | |
1240 | ||
1241 | int | |
1242 | and64_operand (op, mode) | |
9878760c RK |
1243 | register rtx op; |
1244 | enum machine_mode mode; | |
1245 | { | |
9ebbca7d | 1246 | if (fixed_regs[CR0_REGNO]) /* CR0 not available, don't do andi./andis. */ |
52d3af72 DE |
1247 | return (gpc_reg_operand (op, mode) || mask64_operand (op, mode)); |
1248 | ||
1249 | return (logical_operand (op, mode) || mask64_operand (op, mode)); | |
9878760c RK |
1250 | } |
1251 | ||
a260abc9 DE |
1252 | /* Return 1 if the operand is either a non-special register or a |
1253 | constant that can be used as the operand of an RS/6000 logical AND insn. */ | |
dcfedcd0 RK |
1254 | |
1255 | int | |
a260abc9 DE |
1256 | and_operand (op, mode) |
1257 | register rtx op; | |
1258 | enum machine_mode mode; | |
dcfedcd0 | 1259 | { |
9ebbca7d | 1260 | if (fixed_regs[CR0_REGNO]) /* CR0 not available, don't do andi./andis. */ |
52d3af72 DE |
1261 | return (gpc_reg_operand (op, mode) || mask_operand (op, mode)); |
1262 | ||
1263 | return (logical_operand (op, mode) || mask_operand (op, mode)); | |
dcfedcd0 RK |
1264 | } |
1265 | ||
9878760c RK |
1266 | /* Return 1 if the operand is a general register or memory operand. */ |
1267 | ||
1268 | int | |
1269 | reg_or_mem_operand (op, mode) | |
1270 | register rtx op; | |
1271 | register enum machine_mode mode; | |
1272 | { | |
b6c9286a MM |
1273 | return (gpc_reg_operand (op, mode) |
1274 | || memory_operand (op, mode) | |
1275 | || volatile_mem_operand (op, mode)); | |
9878760c RK |
1276 | } |
1277 | ||
a7a813f7 | 1278 | /* Return 1 if the operand is a general register or memory operand without |
3cb999d8 | 1279 | pre_inc or pre_dec which produces invalid form of PowerPC lwa |
a7a813f7 RK |
1280 | instruction. */ |
1281 | ||
1282 | int | |
1283 | lwa_operand (op, mode) | |
1284 | register rtx op; | |
1285 | register enum machine_mode mode; | |
1286 | { | |
1287 | rtx inner = op; | |
1288 | ||
1289 | if (reload_completed && GET_CODE (inner) == SUBREG) | |
1290 | inner = SUBREG_REG (inner); | |
1291 | ||
1292 | return gpc_reg_operand (inner, mode) | |
1293 | || (memory_operand (inner, mode) | |
1294 | && GET_CODE (XEXP (inner, 0)) != PRE_INC | |
1295 | && GET_CODE (XEXP (inner, 0)) != PRE_DEC); | |
1296 | } | |
1297 | ||
9878760c RK |
1298 | /* Return 1 if the operand, used inside a MEM, is a valid first argument |
1299 | to CALL. This is a SYMBOL_REF or a pseudo-register, which will be | |
1300 | forced to lr. */ | |
1301 | ||
1302 | int | |
1303 | call_operand (op, mode) | |
1304 | register rtx op; | |
1305 | enum machine_mode mode; | |
1306 | { | |
1307 | if (mode != VOIDmode && GET_MODE (op) != mode) | |
1308 | return 0; | |
1309 | ||
1310 | return (GET_CODE (op) == SYMBOL_REF | |
1311 | || (GET_CODE (op) == REG && REGNO (op) >= FIRST_PSEUDO_REGISTER)); | |
1312 | } | |
1313 | ||
2af3d377 RK |
1314 | |
1315 | /* Return 1 if the operand is a SYMBOL_REF for a function known to be in | |
8f1b829e | 1316 | this file and the function is not weakly defined. */ |
2af3d377 RK |
1317 | |
1318 | int | |
1319 | current_file_function_operand (op, mode) | |
1320 | register rtx op; | |
296b8152 | 1321 | enum machine_mode mode ATTRIBUTE_UNUSED; |
2af3d377 RK |
1322 | { |
1323 | return (GET_CODE (op) == SYMBOL_REF | |
1324 | && (SYMBOL_REF_FLAG (op) | |
8f1b829e | 1325 | || (op == XEXP (DECL_RTL (current_function_decl), 0) |
c81fc13e | 1326 | && ! DECL_WEAK (current_function_decl)))); |
2af3d377 RK |
1327 | } |
1328 | ||
1329 | ||
9878760c RK |
1330 | /* Return 1 if this operand is a valid input for a move insn. */ |
1331 | ||
1332 | int | |
1333 | input_operand (op, mode) | |
1334 | register rtx op; | |
1335 | enum machine_mode mode; | |
1336 | { | |
eb4e8003 | 1337 | /* Memory is always valid. */ |
9878760c RK |
1338 | if (memory_operand (op, mode)) |
1339 | return 1; | |
1340 | ||
34792e82 | 1341 | /* Only a tiny bit of handling for CONSTANT_P_RTX is necessary. */ |
01b4cf2b | 1342 | if (GET_CODE (op) == CONSTANT_P_RTX) |
34792e82 JL |
1343 | return 1; |
1344 | ||
eb4e8003 RK |
1345 | /* For floating-point, easy constants are valid. */ |
1346 | if (GET_MODE_CLASS (mode) == MODE_FLOAT | |
1347 | && CONSTANT_P (op) | |
1348 | && easy_fp_constant (op, mode)) | |
1349 | return 1; | |
1350 | ||
4e74d8ec MM |
1351 | /* Allow any integer constant. */ |
1352 | if (GET_MODE_CLASS (mode) == MODE_INT | |
e675f625 | 1353 | && (GET_CODE (op) == CONST_INT |
e675f625 | 1354 | || GET_CODE (op) == CONST_DOUBLE)) |
4e74d8ec MM |
1355 | return 1; |
1356 | ||
eb4e8003 RK |
1357 | /* For floating-point or multi-word mode, the only remaining valid type |
1358 | is a register. */ | |
9878760c RK |
1359 | if (GET_MODE_CLASS (mode) == MODE_FLOAT |
1360 | || GET_MODE_SIZE (mode) > UNITS_PER_WORD) | |
eb4e8003 | 1361 | return register_operand (op, mode); |
9878760c | 1362 | |
88fe15a1 RK |
1363 | /* The only cases left are integral modes one word or smaller (we |
1364 | do not get called for MODE_CC values). These can be in any | |
1365 | register. */ | |
1366 | if (register_operand (op, mode)) | |
a8b3aeda | 1367 | return 1; |
88fe15a1 | 1368 | |
84cf9dda | 1369 | /* A SYMBOL_REF referring to the TOC is valid. */ |
7fec4abd | 1370 | if (LEGITIMATE_CONSTANT_POOL_ADDRESS_P (op)) |
84cf9dda RK |
1371 | return 1; |
1372 | ||
9ebbca7d GK |
1373 | /* A constant pool expression (relative to the TOC) is valid */ |
1374 | if (TOC_RELATIVE_EXPR_P (op)) | |
b6c9286a MM |
1375 | return 1; |
1376 | ||
88228c4b MM |
1377 | /* V.4 allows SYMBOL_REFs and CONSTs that are in the small data region |
1378 | to be valid. */ | |
c81bebd7 | 1379 | if ((DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) |
88228c4b MM |
1380 | && (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST) |
1381 | && small_data_operand (op, Pmode)) | |
1382 | return 1; | |
1383 | ||
042259f2 | 1384 | return 0; |
9878760c | 1385 | } |
7509c759 MM |
1386 | |
1387 | /* Return 1 for an operand in small memory on V.4/eabi */ | |
1388 | ||
1389 | int | |
1390 | small_data_operand (op, mode) | |
296b8152 KG |
1391 | rtx op ATTRIBUTE_UNUSED; |
1392 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
7509c759 | 1393 | { |
38c1f2d7 | 1394 | #if TARGET_ELF |
5f59ecb7 | 1395 | rtx sym_ref; |
7509c759 | 1396 | |
d9407988 | 1397 | if (rs6000_sdata == SDATA_NONE || rs6000_sdata == SDATA_DATA) |
a54d04b7 | 1398 | return 0; |
a54d04b7 | 1399 | |
5b9d9a0c | 1400 | if (DEFAULT_ABI != ABI_V4 && DEFAULT_ABI != ABI_SOLARIS) |
7509c759 MM |
1401 | return 0; |
1402 | ||
88228c4b MM |
1403 | if (GET_CODE (op) == SYMBOL_REF) |
1404 | sym_ref = op; | |
1405 | ||
1406 | else if (GET_CODE (op) != CONST | |
1407 | || GET_CODE (XEXP (op, 0)) != PLUS | |
1408 | || GET_CODE (XEXP (XEXP (op, 0), 0)) != SYMBOL_REF | |
1409 | || GET_CODE (XEXP (XEXP (op, 0), 1)) != CONST_INT) | |
7509c759 MM |
1410 | return 0; |
1411 | ||
88228c4b | 1412 | else |
dbf55e53 MM |
1413 | { |
1414 | rtx sum = XEXP (op, 0); | |
1415 | HOST_WIDE_INT summand; | |
1416 | ||
1417 | /* We have to be careful here, because it is the referenced address | |
1418 | that must be 32k from _SDA_BASE_, not just the symbol. */ | |
1419 | summand = INTVAL (XEXP (sum, 1)); | |
1420 | if (summand < 0 || summand > g_switch_value) | |
1421 | return 0; | |
1422 | ||
1423 | sym_ref = XEXP (sum, 0); | |
1424 | } | |
88228c4b MM |
1425 | |
1426 | if (*XSTR (sym_ref, 0) != '@') | |
7509c759 MM |
1427 | return 0; |
1428 | ||
1429 | return 1; | |
d9407988 MM |
1430 | |
1431 | #else | |
1432 | return 0; | |
1433 | #endif | |
7509c759 | 1434 | } |
9ebbca7d GK |
1435 | \f |
1436 | static int | |
1437 | constant_pool_expr_1 (op, have_sym, have_toc) | |
1438 | rtx op; | |
1439 | int *have_sym; | |
1440 | int *have_toc; | |
1441 | { | |
1442 | switch (GET_CODE(op)) | |
1443 | { | |
1444 | case SYMBOL_REF: | |
1445 | if (CONSTANT_POOL_ADDRESS_P (op)) | |
1446 | { | |
a9098fd0 | 1447 | if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (op), Pmode)) |
9ebbca7d GK |
1448 | { |
1449 | *have_sym = 1; | |
1450 | return 1; | |
1451 | } | |
1452 | else | |
1453 | return 0; | |
1454 | } | |
1455 | else if (! strcmp (XSTR (op, 0), toc_label_name)) | |
1456 | { | |
1457 | *have_toc = 1; | |
1458 | return 1; | |
1459 | } | |
1460 | else | |
1461 | return 0; | |
1462 | case PLUS: | |
1463 | case MINUS: | |
1464 | return constant_pool_expr_1 (XEXP (op, 0), have_sym, have_toc) && | |
1465 | constant_pool_expr_1 (XEXP (op, 1), have_sym, have_toc); | |
1466 | case CONST: | |
1467 | return constant_pool_expr_1 (XEXP (op, 0), have_sym, have_toc); | |
1468 | case CONST_INT: | |
1469 | return 1; | |
1470 | default: | |
1471 | return 0; | |
1472 | } | |
1473 | } | |
1474 | ||
1475 | int | |
1476 | constant_pool_expr_p (op) | |
1477 | rtx op; | |
1478 | { | |
1479 | int have_sym = 0; | |
1480 | int have_toc = 0; | |
1481 | return constant_pool_expr_1 (op, &have_sym, &have_toc) && have_sym; | |
1482 | } | |
1483 | ||
1484 | int | |
1485 | toc_relative_expr_p (op) | |
1486 | rtx op; | |
1487 | { | |
1488 | int have_sym = 0; | |
1489 | int have_toc = 0; | |
1490 | return constant_pool_expr_1 (op, &have_sym, &have_toc) && have_toc; | |
1491 | } | |
1492 | ||
1493 | /* Try machine-dependent ways of modifying an illegitimate address | |
1494 | to be legitimate. If we find one, return the new, valid address. | |
1495 | This is used from only one place: `memory_address' in explow.c. | |
1496 | ||
1497 | OLDX is the address as it was before break_out_memory_refs was called. | |
1498 | In some cases it is useful to look at this to decide what needs to be done. | |
1499 | ||
1500 | MODE is passed so that this macro can use GO_IF_LEGITIMATE_ADDRESS. | |
1501 | ||
1502 | It is always safe for this macro to do nothing. It exists to recognize | |
1503 | opportunities to optimize the output. | |
1504 | ||
1505 | On RS/6000, first check for the sum of a register with a constant | |
1506 | integer that is out of range. If so, generate code to add the | |
1507 | constant with the low-order 16 bits masked to the register and force | |
1508 | this result into another register (this can be done with `cau'). | |
1509 | Then generate an address of REG+(CONST&0xffff), allowing for the | |
1510 | possibility of bit 16 being a one. | |
1511 | ||
1512 | Then check for the sum of a register and something not constant, try to | |
1513 | load the other things into a register and return the sum. */ | |
1514 | rtx | |
1515 | rs6000_legitimize_address (x, oldx, mode) | |
1516 | rtx x; | |
1517 | rtx oldx ATTRIBUTE_UNUSED; | |
1518 | enum machine_mode mode; | |
1519 | { | |
1520 | if (GET_CODE (x) == PLUS | |
1521 | && GET_CODE (XEXP (x, 0)) == REG | |
1522 | && GET_CODE (XEXP (x, 1)) == CONST_INT | |
1523 | && (unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 1)) + 0x8000) >= 0x10000) | |
1524 | { | |
1525 | HOST_WIDE_INT high_int, low_int; | |
1526 | rtx sum; | |
1527 | high_int = INTVAL (XEXP (x, 1)) & (~ (HOST_WIDE_INT) 0xffff); | |
1528 | low_int = INTVAL (XEXP (x, 1)) & 0xffff; | |
1529 | if (low_int & 0x8000) | |
1530 | high_int += 0x10000, low_int |= ((HOST_WIDE_INT) -1) << 16; | |
1531 | sum = force_operand (gen_rtx_PLUS (Pmode, XEXP (x, 0), | |
1532 | GEN_INT (high_int)), 0); | |
1533 | return gen_rtx_PLUS (Pmode, sum, GEN_INT (low_int)); | |
1534 | } | |
1535 | else if (GET_CODE (x) == PLUS | |
1536 | && GET_CODE (XEXP (x, 0)) == REG | |
1537 | && GET_CODE (XEXP (x, 1)) != CONST_INT | |
1538 | && (TARGET_HARD_FLOAT || TARGET_POWERPC64 || mode != DFmode) | |
1539 | && (TARGET_POWERPC64 || mode != DImode) | |
1540 | && mode != TImode) | |
1541 | { | |
1542 | return gen_rtx_PLUS (Pmode, XEXP (x, 0), | |
1543 | force_reg (Pmode, force_operand (XEXP (x, 1), 0))); | |
1544 | } | |
1545 | else if (TARGET_ELF && TARGET_32BIT && TARGET_NO_TOC && ! flag_pic | |
1546 | && GET_CODE (x) != CONST_INT | |
1547 | && GET_CODE (x) != CONST_DOUBLE | |
1548 | && CONSTANT_P (x) | |
1549 | && (TARGET_HARD_FLOAT || mode != DFmode) | |
1550 | && mode != DImode | |
1551 | && mode != TImode) | |
1552 | { | |
1553 | rtx reg = gen_reg_rtx (Pmode); | |
1554 | emit_insn (gen_elf_high (reg, (x))); | |
1555 | return gen_rtx_LO_SUM (Pmode, reg, (x)); | |
1556 | } | |
ee890fe2 SS |
1557 | else if (TARGET_MACHO && TARGET_32BIT && TARGET_NO_TOC |
1558 | && ! flag_pic | |
1559 | && GET_CODE (x) != CONST_INT | |
1560 | && GET_CODE (x) != CONST_DOUBLE | |
1561 | && CONSTANT_P (x) | |
1562 | && (TARGET_HARD_FLOAT || mode != DFmode) | |
1563 | && mode != DImode | |
1564 | && mode != TImode) | |
1565 | { | |
1566 | rtx reg = gen_reg_rtx (Pmode); | |
1567 | emit_insn (gen_macho_high (reg, (x))); | |
1568 | return gen_rtx_LO_SUM (Pmode, reg, (x)); | |
1569 | } | |
9ebbca7d GK |
1570 | else if (TARGET_TOC |
1571 | && CONSTANT_POOL_EXPR_P (x) | |
a9098fd0 | 1572 | && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x), Pmode)) |
9ebbca7d GK |
1573 | { |
1574 | return create_TOC_reference (x); | |
1575 | } | |
1576 | else | |
1577 | return NULL_RTX; | |
1578 | } | |
258bfae2 FS |
1579 | |
1580 | /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression | |
1581 | that is a valid memory address for an instruction. | |
1582 | The MODE argument is the machine mode for the MEM expression | |
1583 | that wants to use this address. | |
1584 | ||
1585 | On the RS/6000, there are four valid address: a SYMBOL_REF that | |
1586 | refers to a constant pool entry of an address (or the sum of it | |
1587 | plus a constant), a short (16-bit signed) constant plus a register, | |
1588 | the sum of two registers, or a register indirect, possibly with an | |
1589 | auto-increment. For DFmode and DImode with an constant plus register, | |
1590 | we must ensure that both words are addressable or PowerPC64 with offset | |
1591 | word aligned. | |
1592 | ||
1593 | For modes spanning multiple registers (DFmode in 32-bit GPRs, | |
1594 | 32-bit DImode, TImode), indexed addressing cannot be used because | |
1595 | adjacent memory cells are accessed by adding word-sized offsets | |
1596 | during assembly output. */ | |
1597 | int | |
1598 | rs6000_legitimate_address (mode, x, reg_ok_strict) | |
1599 | enum machine_mode mode; | |
1600 | rtx x; | |
1601 | int reg_ok_strict; | |
1602 | { | |
1603 | if (LEGITIMATE_INDIRECT_ADDRESS_P (x, reg_ok_strict)) | |
1604 | return 1; | |
1605 | if ((GET_CODE (x) == PRE_INC || GET_CODE (x) == PRE_DEC) | |
1606 | && TARGET_UPDATE | |
1607 | && LEGITIMATE_INDIRECT_ADDRESS_P (XEXP (x, 0), reg_ok_strict)) | |
1608 | return 1; | |
1609 | if (LEGITIMATE_SMALL_DATA_P (mode, x)) | |
1610 | return 1; | |
1611 | if (LEGITIMATE_CONSTANT_POOL_ADDRESS_P (x)) | |
1612 | return 1; | |
1613 | /* If not REG_OK_STRICT (before reload) let pass any stack offset. */ | |
1614 | if (! reg_ok_strict | |
1615 | && GET_CODE (x) == PLUS | |
1616 | && GET_CODE (XEXP (x, 0)) == REG | |
1617 | && XEXP (x, 0) == virtual_stack_vars_rtx | |
1618 | && GET_CODE (XEXP (x, 1)) == CONST_INT) | |
1619 | return 1; | |
1620 | if (LEGITIMATE_OFFSET_ADDRESS_P (mode, x, reg_ok_strict)) | |
1621 | return 1; | |
1622 | if (mode != TImode | |
1623 | && (TARGET_HARD_FLOAT || TARGET_POWERPC64 || mode != DFmode) | |
1624 | && (TARGET_POWERPC64 || mode != DImode) | |
1625 | && LEGITIMATE_INDEXED_ADDRESS_P (x, reg_ok_strict)) | |
1626 | return 1; | |
1627 | if (LEGITIMATE_LO_SUM_ADDRESS_P (mode, x, reg_ok_strict)) | |
1628 | return 1; | |
1629 | return 0; | |
1630 | } | |
fb4d4348 GK |
1631 | \f |
1632 | /* Emit a move from SOURCE to DEST in mode MODE. */ | |
1633 | void | |
1634 | rs6000_emit_move (dest, source, mode) | |
1635 | rtx dest; | |
1636 | rtx source; | |
1637 | enum machine_mode mode; | |
1638 | { | |
1639 | rtx operands[2]; | |
1640 | operands[0] = dest; | |
1641 | operands[1] = source; | |
1642 | ||
1643 | /* Sanity checks. Check that we get CONST_DOUBLE only when we should. */ | |
1644 | if (GET_CODE (operands[1]) == CONST_DOUBLE | |
1645 | && ! FLOAT_MODE_P (mode) | |
1646 | && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT) | |
1647 | { | |
1648 | /* FIXME. This should never happen. */ | |
1649 | /* Since it seems that it does, do the safe thing and convert | |
1650 | to a CONST_INT. */ | |
1651 | operands[1] = | |
1652 | GEN_INT (trunc_int_for_mode (CONST_DOUBLE_LOW (operands[1]), mode)); | |
1653 | } | |
1654 | if (GET_CODE (operands[1]) == CONST_DOUBLE | |
1655 | && ! FLOAT_MODE_P (mode) | |
1656 | && ((CONST_DOUBLE_HIGH (operands[1]) == 0 | |
1657 | && CONST_DOUBLE_LOW (operands[1]) >= 0) | |
1658 | || (CONST_DOUBLE_HIGH (operands[1]) == -1 | |
1659 | && CONST_DOUBLE_LOW (operands[1]) < 0))) | |
1660 | abort (); | |
1661 | ||
1662 | if (! no_new_pseudos && GET_CODE (operands[0]) != REG) | |
1663 | operands[1] = force_reg (mode, operands[1]); | |
a9098fd0 | 1664 | |
ffc14f31 GK |
1665 | if (mode == SFmode && ! TARGET_POWERPC && TARGET_HARD_FLOAT |
1666 | && GET_CODE (operands[0]) == MEM) | |
fb4d4348 | 1667 | { |
ffc14f31 GK |
1668 | int regnum; |
1669 | ||
1670 | if (reload_in_progress || reload_completed) | |
1671 | regnum = true_regnum (operands[1]); | |
1672 | else if (GET_CODE (operands[1]) == REG) | |
1673 | regnum = REGNO (operands[1]); | |
1674 | else | |
1675 | regnum = -1; | |
fb4d4348 GK |
1676 | |
1677 | /* If operands[1] is a register, on POWER it may have | |
1678 | double-precision data in it, so truncate it to single | |
1679 | precision. */ | |
1680 | if (FP_REGNO_P (regnum) || regnum >= FIRST_PSEUDO_REGISTER) | |
1681 | { | |
1682 | rtx newreg; | |
1683 | newreg = (no_new_pseudos ? operands[1] : gen_reg_rtx (mode)); | |
1684 | emit_insn (gen_aux_truncdfsf2 (newreg, operands[1])); | |
1685 | operands[1] = newreg; | |
1686 | } | |
1687 | } | |
1688 | ||
a9098fd0 GK |
1689 | /* Handle the case where reload calls us with an invalid address; |
1690 | and the case of CONSTANT_P_RTX. */ | |
1691 | if (! general_operand (operands[1], mode) | |
1692 | || ! nonimmediate_operand (operands[0], mode) | |
1693 | || GET_CODE (operands[1]) == CONSTANT_P_RTX) | |
fb4d4348 GK |
1694 | { |
1695 | emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1])); | |
1696 | return; | |
1697 | } | |
a9098fd0 | 1698 | |
fb4d4348 GK |
1699 | /* FIXME: In the long term, this switch statement should go away |
1700 | and be replaced by a sequence of tests based on things like | |
1701 | mode == Pmode. */ | |
1702 | switch (mode) | |
1703 | { | |
1704 | case HImode: | |
1705 | case QImode: | |
1706 | if (CONSTANT_P (operands[1]) | |
1707 | && GET_CODE (operands[1]) != CONST_INT) | |
a9098fd0 | 1708 | operands[1] = force_const_mem (mode, operands[1]); |
fb4d4348 GK |
1709 | break; |
1710 | ||
1711 | case DFmode: | |
1712 | case SFmode: | |
1713 | if (CONSTANT_P (operands[1]) | |
1714 | && ! easy_fp_constant (operands[1], mode)) | |
a9098fd0 | 1715 | operands[1] = force_const_mem (mode, operands[1]); |
fb4d4348 GK |
1716 | break; |
1717 | ||
1718 | case SImode: | |
a9098fd0 | 1719 | case DImode: |
fb4d4348 GK |
1720 | /* Use default pattern for address of ELF small data */ |
1721 | if (TARGET_ELF | |
a9098fd0 | 1722 | && mode == Pmode |
fb4d4348 | 1723 | && (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) |
a9098fd0 GK |
1724 | && (GET_CODE (operands[1]) == SYMBOL_REF |
1725 | || GET_CODE (operands[1]) == CONST) | |
1726 | && small_data_operand (operands[1], mode)) | |
fb4d4348 GK |
1727 | { |
1728 | emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1])); | |
1729 | return; | |
1730 | } | |
1731 | ||
1732 | if ((DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) | |
a9098fd0 GK |
1733 | && mode == Pmode && mode == SImode |
1734 | && flag_pic == 1 && got_operand (operands[1], mode)) | |
fb4d4348 GK |
1735 | { |
1736 | emit_insn (gen_movsi_got (operands[0], operands[1])); | |
1737 | return; | |
1738 | } | |
1739 | ||
ee890fe2 SS |
1740 | if ((TARGET_ELF || DEFAULT_ABI == ABI_DARWIN) |
1741 | && TARGET_NO_TOC && ! flag_pic | |
a9098fd0 | 1742 | && mode == Pmode |
fb4d4348 GK |
1743 | && CONSTANT_P (operands[1]) |
1744 | && GET_CODE (operands[1]) != HIGH | |
1745 | && GET_CODE (operands[1]) != CONST_INT) | |
1746 | { | |
a9098fd0 | 1747 | rtx target = (no_new_pseudos ? operands[0] : gen_reg_rtx (mode)); |
fb4d4348 GK |
1748 | |
1749 | /* If this is a function address on -mcall-aixdesc, | |
1750 | convert it to the address of the descriptor. */ | |
1751 | if (DEFAULT_ABI == ABI_AIX | |
1752 | && GET_CODE (operands[1]) == SYMBOL_REF | |
1753 | && XSTR (operands[1], 0)[0] == '.') | |
1754 | { | |
1755 | const char *name = XSTR (operands[1], 0); | |
1756 | rtx new_ref; | |
1757 | while (*name == '.') | |
1758 | name++; | |
1759 | new_ref = gen_rtx_SYMBOL_REF (Pmode, name); | |
1760 | CONSTANT_POOL_ADDRESS_P (new_ref) | |
1761 | = CONSTANT_POOL_ADDRESS_P (operands[1]); | |
1762 | SYMBOL_REF_FLAG (new_ref) = SYMBOL_REF_FLAG (operands[1]); | |
1763 | SYMBOL_REF_USED (new_ref) = SYMBOL_REF_USED (operands[1]); | |
1764 | operands[1] = new_ref; | |
1765 | } | |
7509c759 | 1766 | |
ee890fe2 SS |
1767 | if (DEFAULT_ABI == ABI_DARWIN) |
1768 | { | |
1769 | emit_insn (gen_macho_high (target, operands[1])); | |
1770 | emit_insn (gen_macho_low (operands[0], target, operands[1])); | |
1771 | return; | |
1772 | } | |
1773 | ||
fb4d4348 GK |
1774 | emit_insn (gen_elf_high (target, operands[1])); |
1775 | emit_insn (gen_elf_low (operands[0], target, operands[1])); | |
1776 | return; | |
1777 | } | |
1778 | ||
a9098fd0 GK |
1779 | /* If this is a SYMBOL_REF that refers to a constant pool entry, |
1780 | and we have put it in the TOC, we just need to make a TOC-relative | |
1781 | reference to it. */ | |
1782 | if (TARGET_TOC | |
1783 | && GET_CODE (operands[1]) == SYMBOL_REF | |
1784 | && CONSTANT_POOL_EXPR_P (operands[1]) | |
1785 | && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (operands[1]), | |
1786 | get_pool_mode (operands[1]))) | |
fb4d4348 | 1787 | { |
a9098fd0 | 1788 | operands[1] = create_TOC_reference (operands[1]); |
fb4d4348 | 1789 | } |
a9098fd0 GK |
1790 | else if (mode == Pmode |
1791 | && CONSTANT_P (operands[1]) | |
38886f37 AO |
1792 | && ((GET_CODE (operands[1]) != CONST_INT |
1793 | && ! easy_fp_constant (operands[1], mode)) | |
1794 | || (GET_CODE (operands[1]) == CONST_INT | |
1795 | && num_insns_constant (operands[1], mode) > 2) | |
1796 | || (GET_CODE (operands[0]) == REG | |
1797 | && FP_REGNO_P (REGNO (operands[0])))) | |
a9098fd0 GK |
1798 | && GET_CODE (operands[1]) != HIGH |
1799 | && ! LEGITIMATE_CONSTANT_POOL_ADDRESS_P (operands[1]) | |
1800 | && ! TOC_RELATIVE_EXPR_P (operands[1])) | |
fb4d4348 GK |
1801 | { |
1802 | /* Emit a USE operation so that the constant isn't deleted if | |
1803 | expensive optimizations are turned on because nobody | |
1804 | references it. This should only be done for operands that | |
1805 | contain SYMBOL_REFs with CONSTANT_POOL_ADDRESS_P set. | |
1806 | This should not be done for operands that contain LABEL_REFs. | |
1807 | For now, we just handle the obvious case. */ | |
1808 | if (GET_CODE (operands[1]) != LABEL_REF) | |
1809 | emit_insn (gen_rtx_USE (VOIDmode, operands[1])); | |
1810 | ||
ee890fe2 SS |
1811 | /* Darwin uses a special PIC legitimizer. */ |
1812 | if (DEFAULT_ABI == ABI_DARWIN && flag_pic) | |
1813 | { | |
78e1b90d | 1814 | #if TARGET_MACHO |
ee890fe2 SS |
1815 | rtx temp_reg = ((reload_in_progress || reload_completed) |
1816 | ? operands[0] : NULL); | |
1817 | ||
ee890fe2 SS |
1818 | operands[1] = |
1819 | rs6000_machopic_legitimize_pic_address (operands[1], mode, | |
1820 | temp_reg); | |
1821 | #endif | |
1822 | emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1])); | |
1823 | return; | |
1824 | } | |
1825 | ||
fb4d4348 GK |
1826 | /* If we are to limit the number of things we put in the TOC and |
1827 | this is a symbol plus a constant we can add in one insn, | |
1828 | just put the symbol in the TOC and add the constant. Don't do | |
1829 | this if reload is in progress. */ | |
1830 | if (GET_CODE (operands[1]) == CONST | |
1831 | && TARGET_NO_SUM_IN_TOC && ! reload_in_progress | |
1832 | && GET_CODE (XEXP (operands[1], 0)) == PLUS | |
a9098fd0 | 1833 | && add_operand (XEXP (XEXP (operands[1], 0), 1), mode) |
fb4d4348 GK |
1834 | && (GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == LABEL_REF |
1835 | || GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == SYMBOL_REF) | |
1836 | && ! side_effects_p (operands[0])) | |
1837 | { | |
a9098fd0 | 1838 | rtx sym = force_const_mem (mode, XEXP (XEXP (operands[1], 0), 0)); |
fb4d4348 GK |
1839 | rtx other = XEXP (XEXP (operands[1], 0), 1); |
1840 | ||
a9098fd0 GK |
1841 | sym = force_reg (mode, sym); |
1842 | if (mode == SImode) | |
1843 | emit_insn (gen_addsi3 (operands[0], sym, other)); | |
1844 | else | |
1845 | emit_insn (gen_adddi3 (operands[0], sym, other)); | |
fb4d4348 GK |
1846 | return; |
1847 | } | |
1848 | ||
a9098fd0 | 1849 | operands[1] = force_const_mem (mode, operands[1]); |
fb4d4348 GK |
1850 | |
1851 | if (TARGET_TOC | |
d34c5b80 DE |
1852 | && CONSTANT_POOL_EXPR_P (XEXP (operands[1], 0)) |
1853 | && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P ( | |
1854 | get_pool_constant (XEXP (operands[1], 0)), | |
1855 | get_pool_mode (XEXP (operands[1], 0)))) | |
a9098fd0 GK |
1856 | { |
1857 | operands[1] = gen_rtx_MEM (mode, | |
1858 | create_TOC_reference (XEXP (operands[1], 0))); | |
fb4d4348 GK |
1859 | MEM_ALIAS_SET (operands[1]) = get_TOC_alias_set (); |
1860 | RTX_UNCHANGING_P (operands[1]) = 1; | |
a9098fd0 | 1861 | } |
fb4d4348 GK |
1862 | } |
1863 | break; | |
a9098fd0 | 1864 | |
fb4d4348 GK |
1865 | case TImode: |
1866 | if (GET_CODE (operands[0]) == MEM | |
1867 | && GET_CODE (XEXP (operands[0], 0)) != REG | |
1868 | && ! reload_in_progress) | |
1869 | operands[0] = change_address (operands[0], TImode, | |
1870 | copy_addr_to_reg (XEXP (operands[0], 0))); | |
1871 | ||
1872 | if (GET_CODE (operands[1]) == MEM | |
1873 | && GET_CODE (XEXP (operands[1], 0)) != REG | |
1874 | && ! reload_in_progress) | |
1875 | operands[1] = change_address (operands[1], TImode, | |
1876 | copy_addr_to_reg (XEXP (operands[1], 0))); | |
1877 | break; | |
1878 | ||
1879 | default: | |
1880 | abort (); | |
1881 | } | |
1882 | ||
a9098fd0 GK |
1883 | /* Above, we may have called force_const_mem which may have returned |
1884 | an invalid address. If we can, fix this up; otherwise, reload will | |
1885 | have to deal with it. */ | |
1886 | if (GET_CODE (operands[1]) == MEM | |
1887 | && ! memory_address_p (mode, XEXP (operands[1], 0)) | |
1888 | && ! reload_in_progress) | |
f4ef873c | 1889 | operands[1] = adjust_address (operands[1], mode, 0); |
a9098fd0 | 1890 | |
fb4d4348 | 1891 | emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1])); |
02a4ec28 | 1892 | return; |
fb4d4348 | 1893 | } |
4697a36c MM |
1894 | \f |
1895 | /* Initialize a variable CUM of type CUMULATIVE_ARGS | |
1896 | for a call to a function whose data type is FNTYPE. | |
1897 | For a library call, FNTYPE is 0. | |
1898 | ||
1899 | For incoming args we set the number of arguments in the prototype large | |
1c20ae99 | 1900 | so we never return a PARALLEL. */ |
4697a36c MM |
1901 | |
1902 | void | |
1903 | init_cumulative_args (cum, fntype, libname, incoming) | |
1904 | CUMULATIVE_ARGS *cum; | |
1905 | tree fntype; | |
296b8152 | 1906 | rtx libname ATTRIBUTE_UNUSED; |
4697a36c MM |
1907 | int incoming; |
1908 | { | |
1909 | static CUMULATIVE_ARGS zero_cumulative; | |
1910 | ||
1911 | *cum = zero_cumulative; | |
1912 | cum->words = 0; | |
1913 | cum->fregno = FP_ARG_MIN_REG; | |
1914 | cum->prototype = (fntype && TYPE_ARG_TYPES (fntype)); | |
7509c759 | 1915 | cum->call_cookie = CALL_NORMAL; |
4cc833b7 | 1916 | cum->sysv_gregno = GP_ARG_MIN_REG; |
4697a36c MM |
1917 | |
1918 | if (incoming) | |
bd227acc | 1919 | cum->nargs_prototype = 1000; /* don't return a PARALLEL */ |
4697a36c MM |
1920 | |
1921 | else if (cum->prototype) | |
1922 | cum->nargs_prototype = (list_length (TYPE_ARG_TYPES (fntype)) - 1 | |
1923 | + (TYPE_MODE (TREE_TYPE (fntype)) == BLKmode | |
1924 | || RETURN_IN_MEMORY (TREE_TYPE (fntype)))); | |
1925 | ||
1926 | else | |
1927 | cum->nargs_prototype = 0; | |
1928 | ||
1929 | cum->orig_nargs = cum->nargs_prototype; | |
7509c759 | 1930 | |
9ebbca7d GK |
1931 | /* Check for longcall's */ |
1932 | if (fntype && lookup_attribute ("longcall", TYPE_ATTRIBUTES (fntype))) | |
6a4cee5f MM |
1933 | cum->call_cookie = CALL_LONG; |
1934 | ||
4697a36c MM |
1935 | if (TARGET_DEBUG_ARG) |
1936 | { | |
1937 | fprintf (stderr, "\ninit_cumulative_args:"); | |
1938 | if (fntype) | |
1939 | { | |
1940 | tree ret_type = TREE_TYPE (fntype); | |
1941 | fprintf (stderr, " ret code = %s,", | |
1942 | tree_code_name[ (int)TREE_CODE (ret_type) ]); | |
1943 | } | |
1944 | ||
6a4cee5f MM |
1945 | if (cum->call_cookie & CALL_LONG) |
1946 | fprintf (stderr, " longcall,"); | |
1947 | ||
4697a36c MM |
1948 | fprintf (stderr, " proto = %d, nargs = %d\n", |
1949 | cum->prototype, cum->nargs_prototype); | |
1950 | } | |
1951 | } | |
1952 | \f | |
c229cba9 DE |
1953 | /* If defined, a C expression which determines whether, and in which |
1954 | direction, to pad out an argument with extra space. The value | |
1955 | should be of type `enum direction': either `upward' to pad above | |
1956 | the argument, `downward' to pad below, or `none' to inhibit | |
1957 | padding. | |
1958 | ||
1959 | For the AIX ABI structs are always stored left shifted in their | |
1960 | argument slot. */ | |
1961 | ||
9ebbca7d | 1962 | enum direction |
c229cba9 DE |
1963 | function_arg_padding (mode, type) |
1964 | enum machine_mode mode; | |
1965 | tree type; | |
1966 | { | |
c85f7c16 | 1967 | if (type != 0 && AGGREGATE_TYPE_P (type)) |
9ebbca7d | 1968 | return upward; |
c229cba9 DE |
1969 | |
1970 | /* This is the default definition. */ | |
1971 | return (! BYTES_BIG_ENDIAN | |
9ebbca7d | 1972 | ? upward |
c229cba9 DE |
1973 | : ((mode == BLKmode |
1974 | ? (type && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST | |
1975 | && int_size_in_bytes (type) < (PARM_BOUNDARY / BITS_PER_UNIT)) | |
1976 | : GET_MODE_BITSIZE (mode) < PARM_BOUNDARY) | |
9ebbca7d | 1977 | ? downward : upward)); |
c229cba9 DE |
1978 | } |
1979 | ||
b6c9286a MM |
1980 | /* If defined, a C expression that gives the alignment boundary, in bits, |
1981 | of an argument with the specified mode and type. If it is not defined, | |
1982 | PARM_BOUNDARY is used for all arguments. | |
1983 | ||
2310f99a | 1984 | V.4 wants long longs to be double word aligned. */ |
b6c9286a MM |
1985 | |
1986 | int | |
1987 | function_arg_boundary (mode, type) | |
1988 | enum machine_mode mode; | |
9ebbca7d | 1989 | tree type ATTRIBUTE_UNUSED; |
b6c9286a | 1990 | { |
4cc833b7 RH |
1991 | if ((DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) |
1992 | && (mode == DImode || mode == DFmode)) | |
e1f83b4d | 1993 | return 64; |
9ebbca7d | 1994 | else |
b6c9286a | 1995 | return PARM_BOUNDARY; |
b6c9286a MM |
1996 | } |
1997 | \f | |
4697a36c MM |
1998 | /* Update the data in CUM to advance over an argument |
1999 | of mode MODE and data type TYPE. | |
2000 | (TYPE is null for libcalls where that information may not be available.) */ | |
2001 | ||
2002 | void | |
2003 | function_arg_advance (cum, mode, type, named) | |
2004 | CUMULATIVE_ARGS *cum; | |
2005 | enum machine_mode mode; | |
2006 | tree type; | |
2007 | int named; | |
2008 | { | |
2009 | cum->nargs_prototype--; | |
2010 | ||
c81bebd7 | 2011 | if (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) |
4697a36c | 2012 | { |
4cc833b7 RH |
2013 | if (TARGET_HARD_FLOAT |
2014 | && (mode == SFmode || mode == DFmode)) | |
4697a36c | 2015 | { |
4cc833b7 RH |
2016 | if (cum->fregno <= FP_ARG_V4_MAX_REG) |
2017 | cum->fregno++; | |
2018 | else | |
2019 | { | |
2020 | if (mode == DFmode) | |
2021 | cum->words += cum->words & 1; | |
d34c5b80 | 2022 | cum->words += RS6000_ARG_SIZE (mode, type); |
4cc833b7 | 2023 | } |
4697a36c | 2024 | } |
4cc833b7 RH |
2025 | else |
2026 | { | |
2027 | int n_words; | |
2028 | int gregno = cum->sysv_gregno; | |
2029 | ||
2030 | /* Aggregates and IEEE quad get passed by reference. */ | |
2031 | if ((type && AGGREGATE_TYPE_P (type)) | |
2032 | || mode == TFmode) | |
2033 | n_words = 1; | |
2034 | else | |
d34c5b80 | 2035 | n_words = RS6000_ARG_SIZE (mode, type); |
4cc833b7 RH |
2036 | |
2037 | /* Long long is put in odd registers. */ | |
2038 | if (n_words == 2 && (gregno & 1) == 0) | |
2039 | gregno += 1; | |
2040 | ||
2041 | /* Long long is not split between registers and stack. */ | |
2042 | if (gregno + n_words - 1 > GP_ARG_MAX_REG) | |
2043 | { | |
2044 | /* Long long is aligned on the stack. */ | |
2045 | if (n_words == 2) | |
2046 | cum->words += cum->words & 1; | |
2047 | cum->words += n_words; | |
2048 | } | |
4697a36c | 2049 | |
4cc833b7 RH |
2050 | /* Note: continuing to accumulate gregno past when we've started |
2051 | spilling to the stack indicates the fact that we've started | |
2052 | spilling to the stack to expand_builtin_saveregs. */ | |
2053 | cum->sysv_gregno = gregno + n_words; | |
2054 | } | |
4697a36c | 2055 | |
4cc833b7 RH |
2056 | if (TARGET_DEBUG_ARG) |
2057 | { | |
2058 | fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ", | |
2059 | cum->words, cum->fregno); | |
2060 | fprintf (stderr, "gregno = %2d, nargs = %4d, proto = %d, ", | |
2061 | cum->sysv_gregno, cum->nargs_prototype, cum->prototype); | |
2062 | fprintf (stderr, "mode = %4s, named = %d\n", | |
2063 | GET_MODE_NAME (mode), named); | |
2064 | } | |
4697a36c MM |
2065 | } |
2066 | else | |
4cc833b7 RH |
2067 | { |
2068 | int align = (TARGET_32BIT && (cum->words & 1) != 0 | |
2069 | && function_arg_boundary (mode, type) == 64) ? 1 : 0; | |
d34c5b80 | 2070 | cum->words += align + RS6000_ARG_SIZE (mode, type); |
4697a36c | 2071 | |
d34c5b80 DE |
2072 | if (GET_MODE_CLASS (mode) == MODE_FLOAT && TARGET_HARD_FLOAT) |
2073 | cum->fregno++; | |
4cc833b7 RH |
2074 | |
2075 | if (TARGET_DEBUG_ARG) | |
2076 | { | |
2077 | fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ", | |
2078 | cum->words, cum->fregno); | |
2079 | fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s, ", | |
2080 | cum->nargs_prototype, cum->prototype, GET_MODE_NAME (mode)); | |
2081 | fprintf (stderr, "named = %d, align = %d\n", named, align); | |
2082 | } | |
2083 | } | |
4697a36c MM |
2084 | } |
2085 | \f | |
2086 | /* Determine where to put an argument to a function. | |
2087 | Value is zero to push the argument on the stack, | |
2088 | or a hard register in which to store the argument. | |
2089 | ||
2090 | MODE is the argument's machine mode. | |
2091 | TYPE is the data type of the argument (as a tree). | |
2092 | This is null for libcalls where that information may | |
2093 | not be available. | |
2094 | CUM is a variable of type CUMULATIVE_ARGS which gives info about | |
2095 | the preceding args and about the function being called. | |
2096 | NAMED is nonzero if this argument is a named parameter | |
2097 | (otherwise it is an extra parameter matching an ellipsis). | |
2098 | ||
2099 | On RS/6000 the first eight words of non-FP are normally in registers | |
2100 | and the rest are pushed. Under AIX, the first 13 FP args are in registers. | |
2101 | Under V.4, the first 8 FP args are in registers. | |
2102 | ||
2103 | If this is floating-point and no prototype is specified, we use | |
2104 | both an FP and integer register (or possibly FP reg and stack). Library | |
2105 | functions (when TYPE is zero) always have the proper types for args, | |
2106 | so we can pass the FP value just in one register. emit_library_function | |
1c20ae99 | 2107 | doesn't support PARALLEL anyway. */ |
4697a36c MM |
2108 | |
2109 | struct rtx_def * | |
2110 | function_arg (cum, mode, type, named) | |
2111 | CUMULATIVE_ARGS *cum; | |
2112 | enum machine_mode mode; | |
2113 | tree type; | |
d34c5b80 | 2114 | int named ATTRIBUTE_UNUSED; |
4697a36c | 2115 | { |
4cc833b7 | 2116 | enum rs6000_abi abi = DEFAULT_ABI; |
4697a36c | 2117 | |
4cc833b7 RH |
2118 | /* Return a marker to indicate whether CR1 needs to set or clear the bit |
2119 | that V.4 uses to say fp args were passed in registers. Assume that we | |
2120 | don't need the marker for software floating point, or compiler generated | |
2121 | library calls. */ | |
4697a36c MM |
2122 | if (mode == VOIDmode) |
2123 | { | |
c81bebd7 | 2124 | if ((abi == ABI_V4 || abi == ABI_SOLARIS) |
7509c759 MM |
2125 | && TARGET_HARD_FLOAT |
2126 | && cum->nargs_prototype < 0 | |
4697a36c | 2127 | && type && (cum->prototype || TARGET_NO_PROTOTYPE)) |
7509c759 | 2128 | { |
6a4cee5f MM |
2129 | return GEN_INT (cum->call_cookie |
2130 | | ((cum->fregno == FP_ARG_MIN_REG) | |
2131 | ? CALL_V4_SET_FP_ARGS | |
2132 | : CALL_V4_CLEAR_FP_ARGS)); | |
7509c759 | 2133 | } |
4697a36c | 2134 | |
7509c759 | 2135 | return GEN_INT (cum->call_cookie); |
4697a36c MM |
2136 | } |
2137 | ||
4cc833b7 | 2138 | if (abi == ABI_V4 || abi == ABI_SOLARIS) |
4697a36c | 2139 | { |
4cc833b7 RH |
2140 | if (TARGET_HARD_FLOAT |
2141 | && (mode == SFmode || mode == DFmode)) | |
2142 | { | |
2143 | if (cum->fregno <= FP_ARG_V4_MAX_REG) | |
2144 | return gen_rtx_REG (mode, cum->fregno); | |
2145 | else | |
2146 | return NULL; | |
2147 | } | |
2148 | else | |
2149 | { | |
2150 | int n_words; | |
2151 | int gregno = cum->sysv_gregno; | |
2152 | ||
2153 | /* Aggregates and IEEE quad get passed by reference. */ | |
2154 | if ((type && AGGREGATE_TYPE_P (type)) | |
2155 | || mode == TFmode) | |
2156 | n_words = 1; | |
2157 | else | |
d34c5b80 | 2158 | n_words = RS6000_ARG_SIZE (mode, type); |
4cc833b7 RH |
2159 | |
2160 | /* Long long is put in odd registers. */ | |
2161 | if (n_words == 2 && (gregno & 1) == 0) | |
2162 | gregno += 1; | |
2163 | ||
2164 | /* Long long is not split between registers and stack. */ | |
2165 | if (gregno + n_words - 1 <= GP_ARG_MAX_REG) | |
2166 | return gen_rtx_REG (mode, gregno); | |
2167 | else | |
2168 | return NULL; | |
2169 | } | |
4697a36c | 2170 | } |
4cc833b7 RH |
2171 | else |
2172 | { | |
2173 | int align = (TARGET_32BIT && (cum->words & 1) != 0 | |
2174 | && function_arg_boundary (mode, type) == 64) ? 1 : 0; | |
2175 | int align_words = cum->words + align; | |
4697a36c | 2176 | |
4cc833b7 RH |
2177 | if (type && TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST) |
2178 | return NULL_RTX; | |
2179 | ||
2180 | if (USE_FP_FOR_ARG_P (*cum, mode, type)) | |
2181 | { | |
2182 | if (! type | |
2183 | || ((cum->nargs_prototype > 0) | |
2184 | /* IBM AIX extended its linkage convention definition always | |
2185 | to require FP args after register save area hole on the | |
2186 | stack. */ | |
2187 | && (DEFAULT_ABI != ABI_AIX | |
2188 | || ! TARGET_XL_CALL | |
2189 | || (align_words < GP_ARG_NUM_REG)))) | |
2190 | return gen_rtx_REG (mode, cum->fregno); | |
2191 | ||
2192 | return gen_rtx_PARALLEL (mode, | |
2193 | gen_rtvec (2, | |
39403d82 | 2194 | gen_rtx_EXPR_LIST (VOIDmode, |
1c20ae99 JW |
2195 | ((align_words >= GP_ARG_NUM_REG) |
2196 | ? NULL_RTX | |
2197 | : (align_words | |
d34c5b80 | 2198 | + RS6000_ARG_SIZE (mode, type) |
1c20ae99 JW |
2199 | > GP_ARG_NUM_REG |
2200 | /* If this is partially on the stack, then | |
2201 | we only include the portion actually | |
2202 | in registers here. */ | |
39403d82 | 2203 | ? gen_rtx_REG (SImode, |
1c20ae99 | 2204 | GP_ARG_MIN_REG + align_words) |
39403d82 | 2205 | : gen_rtx_REG (mode, |
1c20ae99 JW |
2206 | GP_ARG_MIN_REG + align_words))), |
2207 | const0_rtx), | |
39403d82 DE |
2208 | gen_rtx_EXPR_LIST (VOIDmode, |
2209 | gen_rtx_REG (mode, cum->fregno), | |
1c20ae99 | 2210 | const0_rtx))); |
4cc833b7 RH |
2211 | } |
2212 | else if (align_words < GP_ARG_NUM_REG) | |
2213 | return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words); | |
2214 | else | |
2215 | return NULL_RTX; | |
4697a36c | 2216 | } |
4697a36c MM |
2217 | } |
2218 | \f | |
2219 | /* For an arg passed partly in registers and partly in memory, | |
2220 | this is the number of registers used. | |
2221 | For args passed entirely in registers or entirely in memory, zero. */ | |
2222 | ||
2223 | int | |
2224 | function_arg_partial_nregs (cum, mode, type, named) | |
2225 | CUMULATIVE_ARGS *cum; | |
2226 | enum machine_mode mode; | |
2227 | tree type; | |
d34c5b80 | 2228 | int named ATTRIBUTE_UNUSED; |
4697a36c | 2229 | { |
c81bebd7 | 2230 | if (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) |
4697a36c | 2231 | return 0; |
4697a36c MM |
2232 | |
2233 | if (USE_FP_FOR_ARG_P (*cum, mode, type)) | |
2234 | { | |
2235 | if (cum->nargs_prototype >= 0) | |
2236 | return 0; | |
2237 | } | |
2238 | ||
2239 | if (cum->words < GP_ARG_NUM_REG | |
d34c5b80 | 2240 | && GP_ARG_NUM_REG < (cum->words + RS6000_ARG_SIZE (mode, type))) |
4697a36c MM |
2241 | { |
2242 | int ret = GP_ARG_NUM_REG - cum->words; | |
2243 | if (ret && TARGET_DEBUG_ARG) | |
2244 | fprintf (stderr, "function_arg_partial_nregs: %d\n", ret); | |
2245 | ||
2246 | return ret; | |
2247 | } | |
2248 | ||
2249 | return 0; | |
2250 | } | |
2251 | \f | |
2252 | /* A C expression that indicates when an argument must be passed by | |
2253 | reference. If nonzero for an argument, a copy of that argument is | |
2254 | made in memory and a pointer to the argument is passed instead of | |
2255 | the argument itself. The pointer is passed in whatever way is | |
2256 | appropriate for passing a pointer to that type. | |
2257 | ||
2258 | Under V.4, structures and unions are passed by reference. */ | |
2259 | ||
2260 | int | |
2261 | function_arg_pass_by_reference (cum, mode, type, named) | |
296b8152 KG |
2262 | CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED; |
2263 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
4697a36c | 2264 | tree type; |
296b8152 | 2265 | int named ATTRIBUTE_UNUSED; |
4697a36c | 2266 | { |
c81bebd7 | 2267 | if ((DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) |
4cc833b7 RH |
2268 | && ((type && AGGREGATE_TYPE_P (type)) |
2269 | || mode == TFmode)) | |
4697a36c MM |
2270 | { |
2271 | if (TARGET_DEBUG_ARG) | |
2272 | fprintf (stderr, "function_arg_pass_by_reference: aggregate\n"); | |
2273 | ||
2274 | return 1; | |
2275 | } | |
4697a36c MM |
2276 | |
2277 | return 0; | |
2278 | } | |
4697a36c MM |
2279 | \f |
2280 | /* Perform any needed actions needed for a function that is receiving a | |
2281 | variable number of arguments. | |
2282 | ||
2283 | CUM is as above. | |
2284 | ||
2285 | MODE and TYPE are the mode and type of the current parameter. | |
2286 | ||
2287 | PRETEND_SIZE is a variable that should be set to the amount of stack | |
2288 | that must be pushed by the prolog to pretend that our caller pushed | |
2289 | it. | |
2290 | ||
2291 | Normally, this macro will push all remaining incoming registers on the | |
2292 | stack and set PRETEND_SIZE to the length of the registers pushed. */ | |
2293 | ||
2294 | void | |
2295 | setup_incoming_varargs (cum, mode, type, pretend_size, no_rtl) | |
2296 | CUMULATIVE_ARGS *cum; | |
2297 | enum machine_mode mode; | |
2298 | tree type; | |
2299 | int *pretend_size; | |
2300 | int no_rtl; | |
2301 | ||
2302 | { | |
4cc833b7 RH |
2303 | CUMULATIVE_ARGS next_cum; |
2304 | int reg_size = TARGET_32BIT ? 4 : 8; | |
ca5adc63 | 2305 | rtx save_area = NULL_RTX, mem; |
dfafc897 | 2306 | int first_reg_offset, set; |
d34c5b80 DE |
2307 | tree fntype; |
2308 | int stdarg_p; | |
4697a36c | 2309 | |
d34c5b80 DE |
2310 | fntype = TREE_TYPE (current_function_decl); |
2311 | stdarg_p = (TYPE_ARG_TYPES (fntype) != 0 | |
2312 | && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype))) | |
2313 | != void_type_node)); | |
4cc833b7 | 2314 | |
d34c5b80 DE |
2315 | /* For varargs, we do not want to skip the dummy va_dcl argument. |
2316 | For stdargs, we do want to skip the last named argument. */ | |
2317 | next_cum = *cum; | |
2318 | if (stdarg_p) | |
2319 | function_arg_advance (&next_cum, mode, type, 1); | |
4cc833b7 | 2320 | |
d34c5b80 DE |
2321 | if (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) |
2322 | { | |
4cc833b7 RH |
2323 | /* Indicate to allocate space on the stack for varargs save area. */ |
2324 | /* ??? Does this really have to be located at a magic spot on the | |
2325 | stack, or can we allocate this with assign_stack_local instead. */ | |
00dba523 | 2326 | cfun->machine->sysv_varargs_p = 1; |
60e2d0ca | 2327 | if (! no_rtl) |
2c4974b7 | 2328 | save_area = plus_constant (virtual_stack_vars_rtx, |
bd227acc | 2329 | - RS6000_VARARGS_SIZE); |
4cc833b7 RH |
2330 | |
2331 | first_reg_offset = next_cum.sysv_gregno - GP_ARG_MIN_REG; | |
4697a36c | 2332 | } |
60e2d0ca | 2333 | else |
4697a36c | 2334 | { |
d34c5b80 | 2335 | first_reg_offset = next_cum.words; |
4cc833b7 | 2336 | save_area = virtual_incoming_args_rtx; |
00dba523 | 2337 | cfun->machine->sysv_varargs_p = 0; |
4697a36c MM |
2338 | |
2339 | if (MUST_PASS_IN_STACK (mode, type)) | |
d34c5b80 | 2340 | first_reg_offset += RS6000_ARG_SIZE (TYPE_MODE (type), type); |
4cc833b7 | 2341 | } |
4697a36c | 2342 | |
dfafc897 | 2343 | set = get_varargs_alias_set (); |
c81fc13e | 2344 | if (! no_rtl && first_reg_offset < GP_ARG_NUM_REG) |
4cc833b7 | 2345 | { |
dfafc897 FS |
2346 | mem = gen_rtx_MEM (BLKmode, |
2347 | plus_constant (save_area, | |
2348 | first_reg_offset * reg_size)), | |
2349 | MEM_ALIAS_SET (mem) = set; | |
2350 | ||
4cc833b7 | 2351 | move_block_from_reg |
dfafc897 | 2352 | (GP_ARG_MIN_REG + first_reg_offset, mem, |
4cc833b7 RH |
2353 | GP_ARG_NUM_REG - first_reg_offset, |
2354 | (GP_ARG_NUM_REG - first_reg_offset) * UNITS_PER_WORD); | |
2355 | ||
2356 | /* ??? Does ABI_V4 need this at all? */ | |
4697a36c MM |
2357 | *pretend_size = (GP_ARG_NUM_REG - first_reg_offset) * UNITS_PER_WORD; |
2358 | } | |
2359 | ||
4697a36c | 2360 | /* Save FP registers if needed. */ |
4cc833b7 | 2361 | if ((DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) |
c81fc13e | 2362 | && TARGET_HARD_FLOAT && ! no_rtl |
4cc833b7 | 2363 | && next_cum.fregno <= FP_ARG_V4_MAX_REG) |
4697a36c | 2364 | { |
4cc833b7 | 2365 | int fregno = next_cum.fregno; |
9ebbca7d | 2366 | rtx cr1 = gen_rtx_REG (CCmode, CR1_REGNO); |
4cc833b7 RH |
2367 | rtx lab = gen_label_rtx (); |
2368 | int off = (GP_ARG_NUM_REG * reg_size) + ((fregno - FP_ARG_MIN_REG) * 8); | |
4697a36c | 2369 | |
4cc833b7 | 2370 | emit_jump_insn (gen_rtx_SET (VOIDmode, |
4697a36c | 2371 | pc_rtx, |
39403d82 | 2372 | gen_rtx_IF_THEN_ELSE (VOIDmode, |
4cc833b7 RH |
2373 | gen_rtx_NE (VOIDmode, cr1, |
2374 | const0_rtx), | |
39403d82 | 2375 | gen_rtx_LABEL_REF (VOIDmode, lab), |
4697a36c MM |
2376 | pc_rtx))); |
2377 | ||
4cc833b7 RH |
2378 | while (fregno <= FP_ARG_V4_MAX_REG) |
2379 | { | |
dfafc897 FS |
2380 | mem = gen_rtx_MEM (DFmode, plus_constant (save_area, off)); |
2381 | MEM_ALIAS_SET (mem) = set; | |
2382 | emit_move_insn (mem, gen_rtx_REG (DFmode, fregno)); | |
4cc833b7 RH |
2383 | fregno++; |
2384 | off += 8; | |
4697a36c | 2385 | } |
4cc833b7 RH |
2386 | |
2387 | emit_label (lab); | |
4697a36c | 2388 | } |
4697a36c | 2389 | } |
4697a36c | 2390 | |
dfafc897 | 2391 | /* Create the va_list data type. */ |
2c4974b7 | 2392 | |
dfafc897 FS |
2393 | tree |
2394 | rs6000_build_va_list () | |
2395 | { | |
bab45a51 | 2396 | tree f_gpr, f_fpr, f_ovf, f_sav, record, type_decl; |
4697a36c | 2397 | |
9ebbca7d GK |
2398 | /* For AIX, prefer 'char *' because that's what the system |
2399 | header files like. */ | |
dfafc897 | 2400 | if (DEFAULT_ABI != ABI_V4 && DEFAULT_ABI != ABI_SOLARIS) |
9ebbca7d | 2401 | return build_pointer_type (char_type_node); |
dfafc897 | 2402 | |
0f4fd75d | 2403 | record = make_lang_type (RECORD_TYPE); |
bab45a51 | 2404 | type_decl = build_decl (TYPE_DECL, get_identifier ("__va_list_tag"), record); |
0f4fd75d | 2405 | |
9ebbca7d GK |
2406 | f_gpr = build_decl (FIELD_DECL, get_identifier ("gpr"), |
2407 | unsigned_char_type_node); | |
2408 | f_fpr = build_decl (FIELD_DECL, get_identifier ("fpr"), | |
2409 | unsigned_char_type_node); | |
dfafc897 FS |
2410 | f_ovf = build_decl (FIELD_DECL, get_identifier ("overflow_arg_area"), |
2411 | ptr_type_node); | |
2412 | f_sav = build_decl (FIELD_DECL, get_identifier ("reg_save_area"), | |
2413 | ptr_type_node); | |
2414 | ||
2415 | DECL_FIELD_CONTEXT (f_gpr) = record; | |
2416 | DECL_FIELD_CONTEXT (f_fpr) = record; | |
2417 | DECL_FIELD_CONTEXT (f_ovf) = record; | |
2418 | DECL_FIELD_CONTEXT (f_sav) = record; | |
2419 | ||
bab45a51 FS |
2420 | TREE_CHAIN (record) = type_decl; |
2421 | TYPE_NAME (record) = type_decl; | |
dfafc897 FS |
2422 | TYPE_FIELDS (record) = f_gpr; |
2423 | TREE_CHAIN (f_gpr) = f_fpr; | |
2424 | TREE_CHAIN (f_fpr) = f_ovf; | |
2425 | TREE_CHAIN (f_ovf) = f_sav; | |
2426 | ||
2427 | layout_type (record); | |
2428 | ||
2429 | /* The correct type is an array type of one element. */ | |
2430 | return build_array_type (record, build_index_type (size_zero_node)); | |
2431 | } | |
2432 | ||
2433 | /* Implement va_start. */ | |
2434 | ||
2435 | void | |
2436 | rs6000_va_start (stdarg_p, valist, nextarg) | |
2437 | int stdarg_p; | |
2438 | tree valist; | |
2439 | rtx nextarg; | |
4697a36c | 2440 | { |
dfafc897 FS |
2441 | HOST_WIDE_INT words, n_gpr, n_fpr; |
2442 | tree f_gpr, f_fpr, f_ovf, f_sav; | |
2443 | tree gpr, fpr, ovf, sav, t; | |
2c4974b7 | 2444 | |
dfafc897 | 2445 | /* Only SVR4 needs something special. */ |
2c4974b7 | 2446 | if (DEFAULT_ABI != ABI_V4 && DEFAULT_ABI != ABI_SOLARIS) |
dfafc897 FS |
2447 | { |
2448 | std_expand_builtin_va_start (stdarg_p, valist, nextarg); | |
2449 | return; | |
2450 | } | |
2451 | ||
973a648b | 2452 | f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node)); |
dfafc897 FS |
2453 | f_fpr = TREE_CHAIN (f_gpr); |
2454 | f_ovf = TREE_CHAIN (f_fpr); | |
2455 | f_sav = TREE_CHAIN (f_ovf); | |
2456 | ||
8ebecc3b | 2457 | valist = build1 (INDIRECT_REF, TREE_TYPE (TREE_TYPE (valist)), valist); |
dfafc897 FS |
2458 | gpr = build (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr); |
2459 | fpr = build (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr); | |
2460 | ovf = build (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf); | |
2461 | sav = build (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav); | |
2462 | ||
2463 | /* Count number of gp and fp argument registers used. */ | |
4cc833b7 | 2464 | words = current_function_args_info.words; |
dfafc897 FS |
2465 | n_gpr = current_function_args_info.sysv_gregno - GP_ARG_MIN_REG; |
2466 | n_fpr = current_function_args_info.fregno - FP_ARG_MIN_REG; | |
2467 | ||
2468 | if (TARGET_DEBUG_ARG) | |
78e1b90d DE |
2469 | { |
2470 | fputs ("va_start: words = ", stderr); | |
2471 | fprintf (stderr, HOST_WIDE_INT_PRINT_DEC, words); | |
2472 | fputs (", n_gpr = ", stderr); | |
2473 | fprintf (stderr, HOST_WIDE_INT_PRINT_DEC, n_gpr); | |
2474 | fputs (", n_fpr = ", stderr); | |
2475 | fprintf (stderr, HOST_WIDE_INT_PRINT_DEC, n_fpr); | |
2476 | putc ('\n', stderr); | |
2477 | } | |
dfafc897 FS |
2478 | |
2479 | t = build (MODIFY_EXPR, TREE_TYPE (gpr), gpr, build_int_2 (n_gpr, 0)); | |
2480 | TREE_SIDE_EFFECTS (t) = 1; | |
2481 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
2482 | ||
2483 | t = build (MODIFY_EXPR, TREE_TYPE (fpr), fpr, build_int_2 (n_fpr, 0)); | |
2484 | TREE_SIDE_EFFECTS (t) = 1; | |
2485 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
2486 | ||
2487 | /* Find the overflow area. */ | |
2488 | t = make_tree (TREE_TYPE (ovf), virtual_incoming_args_rtx); | |
2489 | if (words != 0) | |
2490 | t = build (PLUS_EXPR, TREE_TYPE (ovf), t, | |
2491 | build_int_2 (words * UNITS_PER_WORD, 0)); | |
2492 | t = build (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t); | |
2493 | TREE_SIDE_EFFECTS (t) = 1; | |
2494 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
2495 | ||
2496 | /* Find the register save area. */ | |
2497 | t = make_tree (TREE_TYPE (sav), virtual_stack_vars_rtx); | |
2498 | t = build (PLUS_EXPR, TREE_TYPE (sav), t, | |
2499 | build_int_2 (-RS6000_VARARGS_SIZE, -1)); | |
2500 | t = build (MODIFY_EXPR, TREE_TYPE (sav), sav, t); | |
2501 | TREE_SIDE_EFFECTS (t) = 1; | |
2502 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
2503 | } | |
2504 | ||
2505 | /* Implement va_arg. */ | |
2506 | ||
2507 | rtx | |
2508 | rs6000_va_arg (valist, type) | |
2509 | tree valist, type; | |
2510 | { | |
2511 | tree f_gpr, f_fpr, f_ovf, f_sav; | |
2512 | tree gpr, fpr, ovf, sav, reg, t, u; | |
2513 | int indirect_p, size, rsize, n_reg, sav_ofs, sav_scale; | |
2514 | rtx lab_false, lab_over, addr_rtx, r; | |
2515 | ||
9ebbca7d GK |
2516 | /* For AIX, the rule is that structures are passed left-aligned in |
2517 | their stack slot. However, GCC does not presently do this: | |
2518 | structures which are the same size as integer types are passed | |
2519 | right-aligned, as if they were in fact integers. This only | |
2520 | matters for structures of size 1 or 2, or 4 when TARGET_64BIT. */ | |
dfafc897 | 2521 | if (DEFAULT_ABI != ABI_V4 && DEFAULT_ABI != ABI_SOLARIS) |
9ebbca7d GK |
2522 | { |
2523 | HOST_WIDE_INT align, rounded_size; | |
2524 | enum machine_mode mode; | |
2525 | tree addr_tree; | |
2526 | ||
2527 | /* Compute the rounded size of the type. */ | |
2528 | align = PARM_BOUNDARY / BITS_PER_UNIT; | |
2529 | rounded_size = (((int_size_in_bytes (type) + align - 1) / align) | |
2530 | * align); | |
2531 | ||
2532 | addr_tree = valist; | |
2533 | ||
2534 | mode = TYPE_MODE (type); | |
2535 | if (mode != BLKmode) | |
2536 | { | |
2537 | HOST_WIDE_INT adj; | |
2538 | adj = TREE_INT_CST_LOW (TYPE_SIZE (type)) / BITS_PER_UNIT; | |
2539 | if (rounded_size > align) | |
2540 | adj = rounded_size; | |
2541 | ||
2542 | addr_tree = build (PLUS_EXPR, TREE_TYPE (addr_tree), addr_tree, | |
2543 | build_int_2 (rounded_size - adj, 0)); | |
2544 | } | |
2545 | ||
2546 | addr_rtx = expand_expr (addr_tree, NULL_RTX, Pmode, EXPAND_NORMAL); | |
2547 | addr_rtx = copy_to_reg (addr_rtx); | |
2548 | ||
2549 | /* Compute new value for AP. */ | |
2550 | t = build (MODIFY_EXPR, TREE_TYPE (valist), valist, | |
2551 | build (PLUS_EXPR, TREE_TYPE (valist), valist, | |
2552 | build_int_2 (rounded_size, 0))); | |
2553 | TREE_SIDE_EFFECTS (t) = 1; | |
2554 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
2555 | ||
2556 | return addr_rtx; | |
2557 | } | |
dfafc897 | 2558 | |
973a648b | 2559 | f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node)); |
dfafc897 FS |
2560 | f_fpr = TREE_CHAIN (f_gpr); |
2561 | f_ovf = TREE_CHAIN (f_fpr); | |
2562 | f_sav = TREE_CHAIN (f_ovf); | |
2563 | ||
8ebecc3b | 2564 | valist = build1 (INDIRECT_REF, TREE_TYPE (TREE_TYPE (valist)), valist); |
dfafc897 FS |
2565 | gpr = build (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr); |
2566 | fpr = build (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr); | |
2567 | ovf = build (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf); | |
2568 | sav = build (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav); | |
2569 | ||
2570 | size = int_size_in_bytes (type); | |
2571 | rsize = (size + UNITS_PER_WORD - 1) / UNITS_PER_WORD; | |
4cc833b7 | 2572 | |
dfafc897 | 2573 | if (AGGREGATE_TYPE_P (type) || TYPE_MODE (type) == TFmode) |
4cc833b7 | 2574 | { |
dfafc897 FS |
2575 | /* Aggregates and long doubles are passed by reference. */ |
2576 | indirect_p = 1; | |
2577 | reg = gpr; | |
2578 | n_reg = 1; | |
2579 | sav_ofs = 0; | |
2580 | sav_scale = 4; | |
2581 | size = rsize = UNITS_PER_WORD; | |
2582 | } | |
2583 | else if (FLOAT_TYPE_P (type) && ! TARGET_SOFT_FLOAT) | |
2584 | { | |
2585 | /* FP args go in FP registers, if present. */ | |
2586 | indirect_p = 0; | |
2587 | reg = fpr; | |
2588 | n_reg = 1; | |
2589 | sav_ofs = 8*4; | |
2590 | sav_scale = 8; | |
4cc833b7 | 2591 | } |
dfafc897 FS |
2592 | else |
2593 | { | |
2594 | /* Otherwise into GP registers. */ | |
2595 | indirect_p = 0; | |
2596 | reg = gpr; | |
2597 | n_reg = rsize; | |
2598 | sav_ofs = 0; | |
2599 | sav_scale = 4; | |
2600 | } | |
2601 | ||
2602 | /* | |
2603 | * Pull the value out of the saved registers ... | |
2604 | */ | |
2605 | ||
2606 | lab_false = gen_label_rtx (); | |
2607 | lab_over = gen_label_rtx (); | |
2608 | addr_rtx = gen_reg_rtx (Pmode); | |
2609 | ||
2610 | emit_cmp_and_jump_insns (expand_expr (reg, NULL_RTX, QImode, EXPAND_NORMAL), | |
2611 | GEN_INT (8 - n_reg + 1), | |
2612 | GE, const1_rtx, QImode, 1, 1, lab_false); | |
2c4974b7 | 2613 | |
dfafc897 FS |
2614 | /* Long long is aligned in the registers. */ |
2615 | if (n_reg > 1) | |
2c4974b7 | 2616 | { |
dfafc897 FS |
2617 | u = build (BIT_AND_EXPR, TREE_TYPE (reg), reg, |
2618 | build_int_2 (n_reg - 1, 0)); | |
2619 | u = build (PLUS_EXPR, TREE_TYPE (reg), reg, u); | |
2620 | u = build (MODIFY_EXPR, TREE_TYPE (reg), reg, u); | |
2621 | TREE_SIDE_EFFECTS (u) = 1; | |
2622 | expand_expr (u, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
2c4974b7 | 2623 | } |
dfafc897 FS |
2624 | |
2625 | if (sav_ofs) | |
2626 | t = build (PLUS_EXPR, ptr_type_node, sav, build_int_2 (sav_ofs, 0)); | |
2c4974b7 | 2627 | else |
dfafc897 | 2628 | t = sav; |
2c4974b7 | 2629 | |
dfafc897 FS |
2630 | u = build (POSTINCREMENT_EXPR, TREE_TYPE (reg), reg, build_int_2 (n_reg, 0)); |
2631 | TREE_SIDE_EFFECTS (u) = 1; | |
2c4974b7 | 2632 | |
dfafc897 FS |
2633 | u = build1 (CONVERT_EXPR, integer_type_node, u); |
2634 | TREE_SIDE_EFFECTS (u) = 1; | |
2c4974b7 | 2635 | |
dfafc897 FS |
2636 | u = build (MULT_EXPR, integer_type_node, u, build_int_2 (sav_scale, 0)); |
2637 | TREE_SIDE_EFFECTS (u) = 1; | |
2638 | ||
2639 | t = build (PLUS_EXPR, ptr_type_node, t, u); | |
2640 | TREE_SIDE_EFFECTS (t) = 1; | |
2641 | ||
2642 | r = expand_expr (t, addr_rtx, Pmode, EXPAND_NORMAL); | |
2643 | if (r != addr_rtx) | |
2644 | emit_move_insn (addr_rtx, r); | |
2645 | ||
2646 | emit_jump_insn (gen_jump (lab_over)); | |
2647 | emit_barrier (); | |
2648 | emit_label (lab_false); | |
2649 | ||
2650 | /* | |
2651 | * ... otherwise out of the overflow area. | |
2652 | */ | |
2653 | ||
2654 | /* Make sure we don't find reg 7 for the next int arg. */ | |
2655 | if (n_reg > 1) | |
2656 | { | |
2657 | t = build (MODIFY_EXPR, TREE_TYPE (reg), reg, build_int_2 (8, 0)); | |
2658 | TREE_SIDE_EFFECTS (t) = 1; | |
2659 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
2660 | } | |
2661 | ||
2662 | /* Care for on-stack alignment if needed. */ | |
2663 | if (rsize <= 1) | |
2664 | t = ovf; | |
2665 | else | |
2666 | { | |
2667 | t = build (PLUS_EXPR, TREE_TYPE (ovf), ovf, build_int_2 (7, 0)); | |
2668 | t = build (BIT_AND_EXPR, TREE_TYPE (t), t, build_int_2 (-8, -1)); | |
2669 | } | |
2670 | t = save_expr (t); | |
2671 | ||
2672 | r = expand_expr (t, addr_rtx, Pmode, EXPAND_NORMAL); | |
2673 | if (r != addr_rtx) | |
2674 | emit_move_insn (addr_rtx, r); | |
2675 | ||
2676 | t = build (PLUS_EXPR, TREE_TYPE (t), t, build_int_2 (size, 0)); | |
2677 | t = build (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t); | |
2678 | TREE_SIDE_EFFECTS (t) = 1; | |
2679 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
2680 | ||
2681 | emit_label (lab_over); | |
2682 | ||
2683 | if (indirect_p) | |
2684 | { | |
2685 | r = gen_rtx_MEM (Pmode, addr_rtx); | |
2686 | MEM_ALIAS_SET (r) = get_varargs_alias_set (); | |
2687 | emit_move_insn (addr_rtx, r); | |
2688 | } | |
2689 | ||
2690 | return addr_rtx; | |
4697a36c | 2691 | } |
5b5040b9 RK |
2692 | \f |
2693 | /* Generate a memory reference for expand_block_move, copying volatile, | |
2694 | and other bits from an original memory reference. */ | |
2695 | ||
2696 | static rtx | |
2697 | expand_block_move_mem (mode, addr, orig_mem) | |
2698 | enum machine_mode mode; | |
2699 | rtx addr; | |
2700 | rtx orig_mem; | |
2701 | { | |
39403d82 | 2702 | rtx mem = gen_rtx_MEM (mode, addr); |
b6c9286a | 2703 | |
c6df88cb | 2704 | MEM_COPY_ATTRIBUTES (mem, orig_mem); |
b6c9286a MM |
2705 | #ifdef MEM_UNALIGNED_P |
2706 | MEM_UNALIGNED_P (mem) = MEM_UNALIGNED_P (orig_mem); | |
2707 | #endif | |
5b5040b9 RK |
2708 | return mem; |
2709 | } | |
2710 | ||
7e69e155 MM |
2711 | /* Expand a block move operation, and return 1 if successful. Return 0 |
2712 | if we should let the compiler generate normal code. | |
2713 | ||
2714 | operands[0] is the destination | |
2715 | operands[1] is the source | |
2716 | operands[2] is the length | |
2717 | operands[3] is the alignment */ | |
2718 | ||
3933e0e1 MM |
2719 | #define MAX_MOVE_REG 4 |
2720 | ||
7e69e155 MM |
2721 | int |
2722 | expand_block_move (operands) | |
2723 | rtx operands[]; | |
2724 | { | |
b6c9286a MM |
2725 | rtx orig_dest = operands[0]; |
2726 | rtx orig_src = operands[1]; | |
7e69e155 | 2727 | rtx bytes_rtx = operands[2]; |
7e69e155 | 2728 | rtx align_rtx = operands[3]; |
3933e0e1 | 2729 | int constp = (GET_CODE (bytes_rtx) == CONST_INT); |
5ee95df6 | 2730 | int align; |
3933e0e1 MM |
2731 | int bytes; |
2732 | int offset; | |
2733 | int num_reg; | |
2734 | int i; | |
7e69e155 MM |
2735 | rtx src_reg; |
2736 | rtx dest_reg; | |
3933e0e1 MM |
2737 | rtx src_addr; |
2738 | rtx dest_addr; | |
7e69e155 | 2739 | rtx tmp_reg; |
3933e0e1 | 2740 | rtx stores[MAX_MOVE_REG]; |
7e69e155 MM |
2741 | int move_bytes; |
2742 | ||
3933e0e1 | 2743 | /* If this is not a fixed size move, just call memcpy */ |
cc0d9ba8 | 2744 | if (! constp) |
3933e0e1 MM |
2745 | return 0; |
2746 | ||
5ee95df6 FS |
2747 | /* If this is not a fixed size alignment, abort */ |
2748 | if (GET_CODE (align_rtx) != CONST_INT) | |
2749 | abort (); | |
2750 | align = INTVAL (align_rtx); | |
2751 | ||
7e69e155 | 2752 | /* Anything to move? */ |
3933e0e1 MM |
2753 | bytes = INTVAL (bytes_rtx); |
2754 | if (bytes <= 0) | |
7e69e155 MM |
2755 | return 1; |
2756 | ||
3933e0e1 MM |
2757 | /* Don't support real large moves. If string instructions are not used, |
2758 | then don't generate more than 8 loads. */ | |
2759 | if (TARGET_STRING) | |
2760 | { | |
c81fc13e | 2761 | if (bytes > 8*4) |
3933e0e1 MM |
2762 | return 0; |
2763 | } | |
cc0d9ba8 | 2764 | else if (! STRICT_ALIGNMENT) |
3933e0e1 | 2765 | { |
c81fc13e DE |
2766 | if (TARGET_POWERPC64 && align >= 4) |
2767 | { | |
2768 | if (bytes > 8*8) | |
2769 | return 0; | |
2770 | } | |
2771 | else | |
2772 | if (bytes > 8*4) | |
2773 | return 0; | |
3933e0e1 MM |
2774 | } |
2775 | else if (bytes > 8*align) | |
7e69e155 MM |
2776 | return 0; |
2777 | ||
2778 | /* Move the address into scratch registers. */ | |
b6c9286a MM |
2779 | dest_reg = copy_addr_to_reg (XEXP (orig_dest, 0)); |
2780 | src_reg = copy_addr_to_reg (XEXP (orig_src, 0)); | |
7e69e155 | 2781 | |
3933e0e1 | 2782 | if (TARGET_STRING) /* string instructions are available */ |
7e69e155 | 2783 | { |
3933e0e1 | 2784 | for ( ; bytes > 0; bytes -= move_bytes) |
7e69e155 | 2785 | { |
3933e0e1 | 2786 | if (bytes > 24 /* move up to 32 bytes at a time */ |
cc0d9ba8 DE |
2787 | && ! fixed_regs[5] |
2788 | && ! fixed_regs[6] | |
2789 | && ! fixed_regs[7] | |
2790 | && ! fixed_regs[8] | |
2791 | && ! fixed_regs[9] | |
2792 | && ! fixed_regs[10] | |
2793 | && ! fixed_regs[11] | |
2794 | && ! fixed_regs[12]) | |
3933e0e1 MM |
2795 | { |
2796 | move_bytes = (bytes > 32) ? 32 : bytes; | |
cc0d9ba8 DE |
2797 | emit_insn (gen_movstrsi_8reg (expand_block_move_mem (BLKmode, |
2798 | dest_reg, | |
2799 | orig_dest), | |
2800 | expand_block_move_mem (BLKmode, | |
2801 | src_reg, | |
2802 | orig_src), | |
2803 | GEN_INT ((move_bytes == 32) | |
2804 | ? 0 : move_bytes), | |
4c64a852 | 2805 | align_rtx)); |
3933e0e1 MM |
2806 | } |
2807 | else if (bytes > 16 /* move up to 24 bytes at a time */ | |
f9562f27 DE |
2808 | && ! fixed_regs[5] |
2809 | && ! fixed_regs[6] | |
cc0d9ba8 DE |
2810 | && ! fixed_regs[7] |
2811 | && ! fixed_regs[8] | |
2812 | && ! fixed_regs[9] | |
f9562f27 | 2813 | && ! fixed_regs[10]) |
3933e0e1 MM |
2814 | { |
2815 | move_bytes = (bytes > 24) ? 24 : bytes; | |
cc0d9ba8 DE |
2816 | emit_insn (gen_movstrsi_6reg (expand_block_move_mem (BLKmode, |
2817 | dest_reg, | |
2818 | orig_dest), | |
2819 | expand_block_move_mem (BLKmode, | |
2820 | src_reg, | |
2821 | orig_src), | |
3933e0e1 | 2822 | GEN_INT (move_bytes), |
4c64a852 | 2823 | align_rtx)); |
3933e0e1 MM |
2824 | } |
2825 | else if (bytes > 8 /* move up to 16 bytes at a time */ | |
f9562f27 DE |
2826 | && ! fixed_regs[5] |
2827 | && ! fixed_regs[6] | |
2828 | && ! fixed_regs[7] | |
2829 | && ! fixed_regs[8]) | |
3933e0e1 MM |
2830 | { |
2831 | move_bytes = (bytes > 16) ? 16 : bytes; | |
cc0d9ba8 DE |
2832 | emit_insn (gen_movstrsi_4reg (expand_block_move_mem (BLKmode, |
2833 | dest_reg, | |
2834 | orig_dest), | |
2835 | expand_block_move_mem (BLKmode, | |
2836 | src_reg, | |
2837 | orig_src), | |
3933e0e1 | 2838 | GEN_INT (move_bytes), |
4c64a852 | 2839 | align_rtx)); |
3933e0e1 | 2840 | } |
acad7ed3 DE |
2841 | else if (bytes >= 8 && TARGET_POWERPC64 |
2842 | /* 64-bit loads and stores require word-aligned displacements. */ | |
2843 | && (align >= 8 || (! STRICT_ALIGNMENT && align >= 4))) | |
2844 | { | |
2845 | move_bytes = 8; | |
2846 | tmp_reg = gen_reg_rtx (DImode); | |
2847 | emit_move_insn (tmp_reg, | |
2848 | expand_block_move_mem (DImode, | |
2eba1afa | 2849 | src_reg, orig_src)); |
acad7ed3 | 2850 | emit_move_insn (expand_block_move_mem (DImode, |
2eba1afa | 2851 | dest_reg, orig_dest), |
acad7ed3 DE |
2852 | tmp_reg); |
2853 | } | |
2854 | else if (bytes > 4) | |
3933e0e1 MM |
2855 | { /* move up to 8 bytes at a time */ |
2856 | move_bytes = (bytes > 8) ? 8 : bytes; | |
cc0d9ba8 DE |
2857 | emit_insn (gen_movstrsi_2reg (expand_block_move_mem (BLKmode, |
2858 | dest_reg, | |
2859 | orig_dest), | |
2860 | expand_block_move_mem (BLKmode, | |
2861 | src_reg, | |
2862 | orig_src), | |
3933e0e1 | 2863 | GEN_INT (move_bytes), |
4c64a852 | 2864 | align_rtx)); |
3933e0e1 | 2865 | } |
cc0d9ba8 | 2866 | else if (bytes >= 4 && (align >= 4 || ! STRICT_ALIGNMENT)) |
3933e0e1 MM |
2867 | { /* move 4 bytes */ |
2868 | move_bytes = 4; | |
2869 | tmp_reg = gen_reg_rtx (SImode); | |
cc0d9ba8 DE |
2870 | emit_move_insn (tmp_reg, |
2871 | expand_block_move_mem (SImode, | |
2872 | src_reg, orig_src)); | |
2873 | emit_move_insn (expand_block_move_mem (SImode, | |
2874 | dest_reg, orig_dest), | |
2875 | tmp_reg); | |
3933e0e1 | 2876 | } |
cc0d9ba8 | 2877 | else if (bytes == 2 && (align >= 2 || ! STRICT_ALIGNMENT)) |
3933e0e1 MM |
2878 | { /* move 2 bytes */ |
2879 | move_bytes = 2; | |
2880 | tmp_reg = gen_reg_rtx (HImode); | |
cc0d9ba8 DE |
2881 | emit_move_insn (tmp_reg, |
2882 | expand_block_move_mem (HImode, | |
2883 | src_reg, orig_src)); | |
2884 | emit_move_insn (expand_block_move_mem (HImode, | |
2885 | dest_reg, orig_dest), | |
2886 | tmp_reg); | |
3933e0e1 MM |
2887 | } |
2888 | else if (bytes == 1) /* move 1 byte */ | |
2889 | { | |
2890 | move_bytes = 1; | |
2891 | tmp_reg = gen_reg_rtx (QImode); | |
cc0d9ba8 DE |
2892 | emit_move_insn (tmp_reg, |
2893 | expand_block_move_mem (QImode, | |
2894 | src_reg, orig_src)); | |
2895 | emit_move_insn (expand_block_move_mem (QImode, | |
2896 | dest_reg, orig_dest), | |
2897 | tmp_reg); | |
3933e0e1 MM |
2898 | } |
2899 | else | |
2900 | { /* move up to 4 bytes at a time */ | |
2901 | move_bytes = (bytes > 4) ? 4 : bytes; | |
cc0d9ba8 DE |
2902 | emit_insn (gen_movstrsi_1reg (expand_block_move_mem (BLKmode, |
2903 | dest_reg, | |
2904 | orig_dest), | |
2905 | expand_block_move_mem (BLKmode, | |
2906 | src_reg, | |
2907 | orig_src), | |
3933e0e1 | 2908 | GEN_INT (move_bytes), |
4c64a852 | 2909 | align_rtx)); |
3933e0e1 | 2910 | } |
4c64a852 | 2911 | |
015892ee RK |
2912 | if (bytes > move_bytes) |
2913 | { | |
cc0d9ba8 DE |
2914 | if (! TARGET_POWERPC64) |
2915 | { | |
2916 | emit_insn (gen_addsi3 (src_reg, src_reg, | |
2917 | GEN_INT (move_bytes))); | |
2918 | emit_insn (gen_addsi3 (dest_reg, dest_reg, | |
2919 | GEN_INT (move_bytes))); | |
2920 | } | |
2921 | else | |
2922 | { | |
2923 | emit_insn (gen_adddi3 (src_reg, src_reg, | |
2924 | GEN_INT (move_bytes))); | |
2925 | emit_insn (gen_adddi3 (dest_reg, dest_reg, | |
2926 | GEN_INT (move_bytes))); | |
2927 | } | |
015892ee | 2928 | } |
4c64a852 | 2929 | } |
3933e0e1 MM |
2930 | } |
2931 | ||
2932 | else /* string instructions not available */ | |
2933 | { | |
2934 | num_reg = offset = 0; | |
2935 | for ( ; bytes > 0; (bytes -= move_bytes), (offset += move_bytes)) | |
7e69e155 | 2936 | { |
3933e0e1 MM |
2937 | /* Calculate the correct offset for src/dest */ |
2938 | if (offset == 0) | |
7e69e155 | 2939 | { |
3933e0e1 MM |
2940 | src_addr = src_reg; |
2941 | dest_addr = dest_reg; | |
2942 | } | |
2943 | else | |
2944 | { | |
c5c76735 JL |
2945 | src_addr = plus_constant (src_reg, offset); |
2946 | dest_addr = plus_constant (dest_reg, offset); | |
3933e0e1 MM |
2947 | } |
2948 | ||
cc0d9ba8 DE |
2949 | /* Generate the appropriate load and store, saving the stores |
2950 | for later. */ | |
2951 | if (bytes >= 8 && TARGET_POWERPC64 | |
2952 | /* 64-bit loads and stores require word-aligned displacements. */ | |
2953 | && (align >= 8 || (! STRICT_ALIGNMENT && align >= 4))) | |
b6c9286a MM |
2954 | { |
2955 | move_bytes = 8; | |
2956 | tmp_reg = gen_reg_rtx (DImode); | |
cc0d9ba8 DE |
2957 | emit_insn (gen_movdi (tmp_reg, |
2958 | expand_block_move_mem (DImode, | |
2959 | src_addr, | |
2960 | orig_src))); | |
2961 | stores[num_reg++] = gen_movdi (expand_block_move_mem (DImode, | |
2962 | dest_addr, | |
2963 | orig_dest), | |
2964 | tmp_reg); | |
b6c9286a | 2965 | } |
cc0d9ba8 | 2966 | else if (bytes >= 4 && (align >= 4 || ! STRICT_ALIGNMENT)) |
3933e0e1 MM |
2967 | { |
2968 | move_bytes = 4; | |
2969 | tmp_reg = gen_reg_rtx (SImode); | |
cc0d9ba8 DE |
2970 | emit_insn (gen_movsi (tmp_reg, |
2971 | expand_block_move_mem (SImode, | |
2972 | src_addr, | |
2973 | orig_src))); | |
2974 | stores[num_reg++] = gen_movsi (expand_block_move_mem (SImode, | |
2975 | dest_addr, | |
2976 | orig_dest), | |
2977 | tmp_reg); | |
3933e0e1 | 2978 | } |
cc0d9ba8 | 2979 | else if (bytes >= 2 && (align >= 2 || ! STRICT_ALIGNMENT)) |
3933e0e1 MM |
2980 | { |
2981 | move_bytes = 2; | |
2982 | tmp_reg = gen_reg_rtx (HImode); | |
c81fc13e | 2983 | emit_insn (gen_movhi (tmp_reg, |
cc0d9ba8 DE |
2984 | expand_block_move_mem (HImode, |
2985 | src_addr, | |
2986 | orig_src))); | |
2987 | stores[num_reg++] = gen_movhi (expand_block_move_mem (HImode, | |
2988 | dest_addr, | |
2989 | orig_dest), | |
2990 | tmp_reg); | |
3933e0e1 MM |
2991 | } |
2992 | else | |
2993 | { | |
2994 | move_bytes = 1; | |
2995 | tmp_reg = gen_reg_rtx (QImode); | |
c81fc13e | 2996 | emit_insn (gen_movqi (tmp_reg, |
cc0d9ba8 DE |
2997 | expand_block_move_mem (QImode, |
2998 | src_addr, | |
2999 | orig_src))); | |
3000 | stores[num_reg++] = gen_movqi (expand_block_move_mem (QImode, | |
3001 | dest_addr, | |
3002 | orig_dest), | |
3003 | tmp_reg); | |
3933e0e1 MM |
3004 | } |
3005 | ||
3006 | if (num_reg >= MAX_MOVE_REG) | |
3007 | { | |
3008 | for (i = 0; i < num_reg; i++) | |
3009 | emit_insn (stores[i]); | |
3010 | num_reg = 0; | |
7e69e155 MM |
3011 | } |
3012 | } | |
3933e0e1 | 3013 | |
b6c9286a MM |
3014 | for (i = 0; i < num_reg; i++) |
3015 | emit_insn (stores[i]); | |
7e69e155 MM |
3016 | } |
3017 | ||
3018 | return 1; | |
3019 | } | |
3020 | ||
9878760c RK |
3021 | \f |
3022 | /* Return 1 if OP is a load multiple operation. It is known to be a | |
3023 | PARALLEL and the first section will be tested. */ | |
3024 | ||
3025 | int | |
3026 | load_multiple_operation (op, mode) | |
3027 | rtx op; | |
296b8152 | 3028 | enum machine_mode mode ATTRIBUTE_UNUSED; |
9878760c RK |
3029 | { |
3030 | int count = XVECLEN (op, 0); | |
e2c953b6 | 3031 | unsigned int dest_regno; |
9878760c RK |
3032 | rtx src_addr; |
3033 | int i; | |
3034 | ||
3035 | /* Perform a quick check so we don't blow up below. */ | |
3036 | if (count <= 1 | |
3037 | || GET_CODE (XVECEXP (op, 0, 0)) != SET | |
3038 | || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG | |
3039 | || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM) | |
3040 | return 0; | |
3041 | ||
3042 | dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0))); | |
3043 | src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0); | |
3044 | ||
3045 | for (i = 1; i < count; i++) | |
3046 | { | |
3047 | rtx elt = XVECEXP (op, 0, i); | |
3048 | ||
3049 | if (GET_CODE (elt) != SET | |
3050 | || GET_CODE (SET_DEST (elt)) != REG | |
3051 | || GET_MODE (SET_DEST (elt)) != SImode | |
3052 | || REGNO (SET_DEST (elt)) != dest_regno + i | |
3053 | || GET_CODE (SET_SRC (elt)) != MEM | |
3054 | || GET_MODE (SET_SRC (elt)) != SImode | |
3055 | || GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS | |
3056 | || ! rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr) | |
3057 | || GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT | |
3058 | || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != i * 4) | |
3059 | return 0; | |
3060 | } | |
3061 | ||
3062 | return 1; | |
3063 | } | |
3064 | ||
3065 | /* Similar, but tests for store multiple. Here, the second vector element | |
3066 | is a CLOBBER. It will be tested later. */ | |
3067 | ||
3068 | int | |
3069 | store_multiple_operation (op, mode) | |
3070 | rtx op; | |
296b8152 | 3071 | enum machine_mode mode ATTRIBUTE_UNUSED; |
9878760c RK |
3072 | { |
3073 | int count = XVECLEN (op, 0) - 1; | |
e2c953b6 | 3074 | unsigned int src_regno; |
9878760c RK |
3075 | rtx dest_addr; |
3076 | int i; | |
3077 | ||
3078 | /* Perform a quick check so we don't blow up below. */ | |
3079 | if (count <= 1 | |
3080 | || GET_CODE (XVECEXP (op, 0, 0)) != SET | |
3081 | || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM | |
3082 | || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG) | |
3083 | return 0; | |
3084 | ||
3085 | src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0))); | |
3086 | dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0); | |
3087 | ||
3088 | for (i = 1; i < count; i++) | |
3089 | { | |
3090 | rtx elt = XVECEXP (op, 0, i + 1); | |
3091 | ||
3092 | if (GET_CODE (elt) != SET | |
3093 | || GET_CODE (SET_SRC (elt)) != REG | |
3094 | || GET_MODE (SET_SRC (elt)) != SImode | |
3095 | || REGNO (SET_SRC (elt)) != src_regno + i | |
3096 | || GET_CODE (SET_DEST (elt)) != MEM | |
3097 | || GET_MODE (SET_DEST (elt)) != SImode | |
3098 | || GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS | |
3099 | || ! rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr) | |
3100 | || GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT | |
3101 | || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != i * 4) | |
3102 | return 0; | |
3103 | } | |
3104 | ||
3105 | return 1; | |
3106 | } | |
9ebbca7d GK |
3107 | |
3108 | /* Return 1 for an PARALLEL suitable for mtcrf. */ | |
3109 | ||
3110 | int | |
3111 | mtcrf_operation (op, mode) | |
3112 | rtx op; | |
3113 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
3114 | { | |
3115 | int count = XVECLEN (op, 0); | |
3116 | int i; | |
9ebbca7d GK |
3117 | rtx src_reg; |
3118 | ||
3119 | /* Perform a quick check so we don't blow up below. */ | |
e35b9579 GK |
3120 | if (count < 1 |
3121 | || GET_CODE (XVECEXP (op, 0, 0)) != SET | |
3122 | || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC | |
3123 | || XVECLEN (SET_SRC (XVECEXP (op, 0, 0)), 0) != 2) | |
9ebbca7d | 3124 | return 0; |
e35b9579 | 3125 | src_reg = XVECEXP (SET_SRC (XVECEXP (op, 0, 0)), 0, 0); |
9ebbca7d GK |
3126 | |
3127 | if (GET_CODE (src_reg) != REG | |
3128 | || GET_MODE (src_reg) != SImode | |
3129 | || ! INT_REGNO_P (REGNO (src_reg))) | |
3130 | return 0; | |
3131 | ||
e35b9579 | 3132 | for (i = 0; i < count; i++) |
9ebbca7d GK |
3133 | { |
3134 | rtx exp = XVECEXP (op, 0, i); | |
3135 | rtx unspec; | |
3136 | int maskval; | |
3137 | ||
3138 | if (GET_CODE (exp) != SET | |
3139 | || GET_CODE (SET_DEST (exp)) != REG | |
3140 | || GET_MODE (SET_DEST (exp)) != CCmode | |
3141 | || ! CR_REGNO_P (REGNO (SET_DEST (exp)))) | |
3142 | return 0; | |
3143 | unspec = SET_SRC (exp); | |
3144 | maskval = 1 << (MAX_CR_REGNO - REGNO (SET_DEST (exp))); | |
9ebbca7d GK |
3145 | |
3146 | if (GET_CODE (unspec) != UNSPEC | |
3147 | || XINT (unspec, 1) != 20 | |
3148 | || XVECLEN (unspec, 0) != 2 | |
3149 | || XVECEXP (unspec, 0, 0) != src_reg | |
3150 | || GET_CODE (XVECEXP (unspec, 0, 1)) != CONST_INT | |
3151 | || INTVAL (XVECEXP (unspec, 0, 1)) != maskval) | |
3152 | return 0; | |
3153 | } | |
e35b9579 | 3154 | return 1; |
9ebbca7d GK |
3155 | } |
3156 | ||
3157 | /* Return 1 for an PARALLEL suitable for lmw. */ | |
3158 | ||
3159 | int | |
3160 | lmw_operation (op, mode) | |
3161 | rtx op; | |
3162 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
3163 | { | |
3164 | int count = XVECLEN (op, 0); | |
e2c953b6 | 3165 | unsigned int dest_regno; |
9ebbca7d | 3166 | rtx src_addr; |
e2c953b6 | 3167 | unsigned int base_regno; |
9ebbca7d GK |
3168 | HOST_WIDE_INT offset; |
3169 | int i; | |
3170 | ||
3171 | /* Perform a quick check so we don't blow up below. */ | |
3172 | if (count <= 1 | |
3173 | || GET_CODE (XVECEXP (op, 0, 0)) != SET | |
3174 | || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG | |
3175 | || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM) | |
3176 | return 0; | |
3177 | ||
3178 | dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0))); | |
3179 | src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0); | |
3180 | ||
3181 | if (dest_regno > 31 | |
e2c953b6 | 3182 | || count != 32 - (int) dest_regno) |
9ebbca7d GK |
3183 | return 0; |
3184 | ||
258bfae2 | 3185 | if (LEGITIMATE_INDIRECT_ADDRESS_P (src_addr, 0)) |
9ebbca7d GK |
3186 | { |
3187 | offset = 0; | |
3188 | base_regno = REGNO (src_addr); | |
3189 | if (base_regno == 0) | |
3190 | return 0; | |
3191 | } | |
258bfae2 | 3192 | else if (LEGITIMATE_OFFSET_ADDRESS_P (SImode, src_addr, 0)) |
9ebbca7d GK |
3193 | { |
3194 | offset = INTVAL (XEXP (src_addr, 1)); | |
3195 | base_regno = REGNO (XEXP (src_addr, 0)); | |
3196 | } | |
3197 | else | |
3198 | return 0; | |
3199 | ||
3200 | for (i = 0; i < count; i++) | |
3201 | { | |
3202 | rtx elt = XVECEXP (op, 0, i); | |
3203 | rtx newaddr; | |
3204 | rtx addr_reg; | |
3205 | HOST_WIDE_INT newoffset; | |
3206 | ||
3207 | if (GET_CODE (elt) != SET | |
3208 | || GET_CODE (SET_DEST (elt)) != REG | |
3209 | || GET_MODE (SET_DEST (elt)) != SImode | |
3210 | || REGNO (SET_DEST (elt)) != dest_regno + i | |
3211 | || GET_CODE (SET_SRC (elt)) != MEM | |
3212 | || GET_MODE (SET_SRC (elt)) != SImode) | |
3213 | return 0; | |
3214 | newaddr = XEXP (SET_SRC (elt), 0); | |
258bfae2 | 3215 | if (LEGITIMATE_INDIRECT_ADDRESS_P (newaddr, 0)) |
9ebbca7d GK |
3216 | { |
3217 | newoffset = 0; | |
3218 | addr_reg = newaddr; | |
3219 | } | |
258bfae2 | 3220 | else if (LEGITIMATE_OFFSET_ADDRESS_P (SImode, newaddr, 0)) |
9ebbca7d GK |
3221 | { |
3222 | addr_reg = XEXP (newaddr, 0); | |
3223 | newoffset = INTVAL (XEXP (newaddr, 1)); | |
3224 | } | |
3225 | else | |
3226 | return 0; | |
3227 | if (REGNO (addr_reg) != base_regno | |
3228 | || newoffset != offset + 4 * i) | |
3229 | return 0; | |
3230 | } | |
3231 | ||
3232 | return 1; | |
3233 | } | |
3234 | ||
3235 | /* Return 1 for an PARALLEL suitable for stmw. */ | |
3236 | ||
3237 | int | |
3238 | stmw_operation (op, mode) | |
3239 | rtx op; | |
3240 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
3241 | { | |
3242 | int count = XVECLEN (op, 0); | |
e2c953b6 | 3243 | unsigned int src_regno; |
9ebbca7d | 3244 | rtx dest_addr; |
e2c953b6 | 3245 | unsigned int base_regno; |
9ebbca7d GK |
3246 | HOST_WIDE_INT offset; |
3247 | int i; | |
3248 | ||
3249 | /* Perform a quick check so we don't blow up below. */ | |
3250 | if (count <= 1 | |
3251 | || GET_CODE (XVECEXP (op, 0, 0)) != SET | |
3252 | || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM | |
3253 | || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG) | |
3254 | return 0; | |
3255 | ||
3256 | src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0))); | |
3257 | dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0); | |
3258 | ||
3259 | if (src_regno > 31 | |
e2c953b6 | 3260 | || count != 32 - (int) src_regno) |
9ebbca7d GK |
3261 | return 0; |
3262 | ||
258bfae2 | 3263 | if (LEGITIMATE_INDIRECT_ADDRESS_P (dest_addr, 0)) |
9ebbca7d GK |
3264 | { |
3265 | offset = 0; | |
3266 | base_regno = REGNO (dest_addr); | |
3267 | if (base_regno == 0) | |
3268 | return 0; | |
3269 | } | |
258bfae2 | 3270 | else if (LEGITIMATE_OFFSET_ADDRESS_P (SImode, dest_addr, 0)) |
9ebbca7d GK |
3271 | { |
3272 | offset = INTVAL (XEXP (dest_addr, 1)); | |
3273 | base_regno = REGNO (XEXP (dest_addr, 0)); | |
3274 | } | |
3275 | else | |
3276 | return 0; | |
3277 | ||
3278 | for (i = 0; i < count; i++) | |
3279 | { | |
3280 | rtx elt = XVECEXP (op, 0, i); | |
3281 | rtx newaddr; | |
3282 | rtx addr_reg; | |
3283 | HOST_WIDE_INT newoffset; | |
3284 | ||
3285 | if (GET_CODE (elt) != SET | |
3286 | || GET_CODE (SET_SRC (elt)) != REG | |
3287 | || GET_MODE (SET_SRC (elt)) != SImode | |
3288 | || REGNO (SET_SRC (elt)) != src_regno + i | |
3289 | || GET_CODE (SET_DEST (elt)) != MEM | |
3290 | || GET_MODE (SET_DEST (elt)) != SImode) | |
3291 | return 0; | |
3292 | newaddr = XEXP (SET_DEST (elt), 0); | |
258bfae2 | 3293 | if (LEGITIMATE_INDIRECT_ADDRESS_P (newaddr, 0)) |
9ebbca7d GK |
3294 | { |
3295 | newoffset = 0; | |
3296 | addr_reg = newaddr; | |
3297 | } | |
258bfae2 | 3298 | else if (LEGITIMATE_OFFSET_ADDRESS_P (SImode, newaddr, 0)) |
9ebbca7d GK |
3299 | { |
3300 | addr_reg = XEXP (newaddr, 0); | |
3301 | newoffset = INTVAL (XEXP (newaddr, 1)); | |
3302 | } | |
3303 | else | |
3304 | return 0; | |
3305 | if (REGNO (addr_reg) != base_regno | |
3306 | || newoffset != offset + 4 * i) | |
3307 | return 0; | |
3308 | } | |
3309 | ||
3310 | return 1; | |
3311 | } | |
9878760c | 3312 | \f |
39a10a29 GK |
3313 | |
3314 | /* A validation routine: say whether CODE, a condition code, | |
3315 | and MODE match. The other alternatives either don't make | |
3316 | sense or should never be generated. */ | |
3317 | static void | |
3318 | validate_condition_mode (code, mode) | |
3319 | enum rtx_code code; | |
3320 | enum machine_mode mode; | |
3321 | { | |
3322 | if (GET_RTX_CLASS (code) != '<' | |
3323 | || GET_MODE_CLASS (mode) != MODE_CC) | |
3324 | abort (); | |
3325 | ||
3326 | /* These don't make sense. */ | |
3327 | if ((code == GT || code == LT || code == GE || code == LE) | |
3328 | && mode == CCUNSmode) | |
3329 | abort (); | |
3330 | ||
3331 | if ((code == GTU || code == LTU || code == GEU || code == LEU) | |
3332 | && mode != CCUNSmode) | |
3333 | abort (); | |
3334 | ||
3335 | if (mode != CCFPmode | |
3336 | && (code == ORDERED || code == UNORDERED | |
3337 | || code == UNEQ || code == LTGT | |
3338 | || code == UNGT || code == UNLT | |
3339 | || code == UNGE || code == UNLE)) | |
3340 | abort(); | |
3341 | ||
de6c5979 BL |
3342 | /* These should never be generated except for |
3343 | flag_unsafe_math_optimizations. */ | |
39a10a29 | 3344 | if (mode == CCFPmode |
de6c5979 | 3345 | && ! flag_unsafe_math_optimizations |
39a10a29 GK |
3346 | && (code == LE || code == GE |
3347 | || code == UNEQ || code == LTGT | |
3348 | || code == UNGT || code == UNLT)) | |
3349 | abort (); | |
3350 | ||
3351 | /* These are invalid; the information is not there. */ | |
3352 | if (mode == CCEQmode | |
3353 | && code != EQ && code != NE) | |
3354 | abort (); | |
3355 | } | |
3356 | ||
9878760c RK |
3357 | /* Return 1 if OP is a comparison operation that is valid for a branch insn. |
3358 | We only check the opcode against the mode of the CC value here. */ | |
3359 | ||
3360 | int | |
3361 | branch_comparison_operator (op, mode) | |
3362 | register rtx op; | |
296b8152 | 3363 | enum machine_mode mode ATTRIBUTE_UNUSED; |
9878760c RK |
3364 | { |
3365 | enum rtx_code code = GET_CODE (op); | |
3366 | enum machine_mode cc_mode; | |
3367 | ||
3368 | if (GET_RTX_CLASS (code) != '<') | |
3369 | return 0; | |
3370 | ||
3371 | cc_mode = GET_MODE (XEXP (op, 0)); | |
3372 | if (GET_MODE_CLASS (cc_mode) != MODE_CC) | |
3373 | return 0; | |
3374 | ||
39a10a29 | 3375 | validate_condition_mode (code, cc_mode); |
9878760c | 3376 | |
39a10a29 GK |
3377 | return 1; |
3378 | } | |
3379 | ||
3380 | /* Return 1 if OP is a comparison operation that is valid for a branch | |
3381 | insn and which is true if the corresponding bit in the CC register | |
3382 | is set. */ | |
3383 | ||
3384 | int | |
3385 | branch_positive_comparison_operator (op, mode) | |
3386 | register rtx op; | |
3387 | enum machine_mode mode; | |
3388 | { | |
3389 | enum rtx_code code; | |
3390 | ||
3391 | if (! branch_comparison_operator (op, mode)) | |
9878760c RK |
3392 | return 0; |
3393 | ||
39a10a29 GK |
3394 | code = GET_CODE (op); |
3395 | return (code == EQ || code == LT || code == GT | |
3396 | || code == LTU || code == GTU | |
3397 | || code == UNORDERED); | |
9878760c RK |
3398 | } |
3399 | ||
39a10a29 | 3400 | |
9878760c RK |
3401 | /* Return 1 if OP is a comparison operation that is valid for an scc insn. |
3402 | We check the opcode against the mode of the CC value and disallow EQ or | |
3403 | NE comparisons for integers. */ | |
3404 | ||
3405 | int | |
3406 | scc_comparison_operator (op, mode) | |
3407 | register rtx op; | |
3408 | enum machine_mode mode; | |
3409 | { | |
3410 | enum rtx_code code = GET_CODE (op); | |
3411 | enum machine_mode cc_mode; | |
3412 | ||
3413 | if (GET_MODE (op) != mode && mode != VOIDmode) | |
3414 | return 0; | |
3415 | ||
3416 | if (GET_RTX_CLASS (code) != '<') | |
3417 | return 0; | |
3418 | ||
3419 | cc_mode = GET_MODE (XEXP (op, 0)); | |
3420 | if (GET_MODE_CLASS (cc_mode) != MODE_CC) | |
3421 | return 0; | |
3422 | ||
39a10a29 | 3423 | validate_condition_mode (code, cc_mode); |
9878760c | 3424 | |
39a10a29 | 3425 | if (code == NE && cc_mode != CCFPmode) |
c5defebb RK |
3426 | return 0; |
3427 | ||
9878760c RK |
3428 | return 1; |
3429 | } | |
e0cd0770 JC |
3430 | |
3431 | int | |
3432 | trap_comparison_operator (op, mode) | |
3433 | rtx op; | |
3434 | enum machine_mode mode; | |
3435 | { | |
3436 | if (mode != VOIDmode && mode != GET_MODE (op)) | |
3437 | return 0; | |
39a10a29 | 3438 | return GET_RTX_CLASS (GET_CODE (op)) == '<'; |
e0cd0770 | 3439 | } |
dfbdccdb GK |
3440 | |
3441 | int | |
3442 | boolean_operator (op, mode) | |
3443 | rtx op; | |
3444 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
3445 | { | |
3446 | enum rtx_code code = GET_CODE (op); | |
3447 | return (code == AND || code == IOR || code == XOR); | |
3448 | } | |
1d328b19 GK |
3449 | |
3450 | int | |
3451 | boolean_or_operator (op, mode) | |
3452 | rtx op; | |
3453 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
3454 | { | |
3455 | enum rtx_code code = GET_CODE (op); | |
3456 | return (code == IOR || code == XOR); | |
3457 | } | |
50a0b056 GK |
3458 | |
3459 | int | |
3460 | min_max_operator (op, mode) | |
3461 | rtx op; | |
3462 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
3463 | { | |
3464 | enum rtx_code code = GET_CODE (op); | |
3465 | return (code == SMIN || code == SMAX || code == UMIN || code == UMAX); | |
3466 | } | |
9878760c RK |
3467 | \f |
3468 | /* Return 1 if ANDOP is a mask that has no bits on that are not in the | |
3469 | mask required to convert the result of a rotate insn into a shift | |
3470 | left insn of SHIFTOP bits. Both are known to be CONST_INT. */ | |
3471 | ||
3472 | int | |
3473 | includes_lshift_p (shiftop, andop) | |
3474 | register rtx shiftop; | |
3475 | register rtx andop; | |
3476 | { | |
e2c953b6 DE |
3477 | unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0; |
3478 | ||
3479 | shift_mask <<= INTVAL (shiftop); | |
9878760c RK |
3480 | |
3481 | return (INTVAL (andop) & ~shift_mask) == 0; | |
3482 | } | |
3483 | ||
3484 | /* Similar, but for right shift. */ | |
3485 | ||
3486 | int | |
3487 | includes_rshift_p (shiftop, andop) | |
3488 | register rtx shiftop; | |
3489 | register rtx andop; | |
3490 | { | |
a7653a2c | 3491 | unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0; |
9878760c RK |
3492 | |
3493 | shift_mask >>= INTVAL (shiftop); | |
3494 | ||
e2c953b6 DE |
3495 | return (INTVAL (andop) & ~shift_mask) == 0; |
3496 | } | |
3497 | ||
3498 | /* Return 1 if ANDOP is a mask that has no bits on that are not in the | |
3499 | mask required to convert the result of a rotate insn into a shift | |
3500 | left insn of SHIFTOP bits. */ | |
3501 | ||
3502 | int | |
3503 | includes_lshift64_p (shiftop, andop) | |
3504 | register rtx shiftop; | |
3505 | register rtx andop; | |
3506 | { | |
3507 | #if HOST_BITS_PER_WIDE_INT == 64 | |
3508 | unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0; | |
3509 | ||
3510 | shift_mask <<= INTVAL (shiftop); | |
3511 | ||
3512 | return (INTVAL (andop) & ~shift_mask) == 0; | |
3513 | #else | |
3514 | unsigned HOST_WIDE_INT shift_mask_low = ~(unsigned HOST_WIDE_INT) 0; | |
3515 | unsigned HOST_WIDE_INT shift_mask_high = ~(unsigned HOST_WIDE_INT) 0; | |
3516 | ||
3517 | shift_mask_low <<= INTVAL (shiftop); | |
3518 | ||
3519 | if (INTVAL (shiftop) > 32) | |
3520 | shift_mask_high <<= (INTVAL (shiftop) - 32); | |
3521 | ||
3522 | if (GET_CODE (andop) == CONST_INT) | |
3523 | return (INTVAL (andop) & ~shift_mask_low) == 0; | |
3524 | else | |
3525 | return ((CONST_DOUBLE_HIGH (andop) & ~shift_mask_high) == 0 | |
3526 | && (CONST_DOUBLE_LOW (andop) & ~shift_mask_low) == 0); | |
3527 | #endif | |
9878760c | 3528 | } |
35068b43 RK |
3529 | |
3530 | /* Return 1 if REGNO (reg1) == REGNO (reg2) - 1 making them candidates | |
3531 | for lfq and stfq insns. | |
3532 | ||
3533 | Note reg1 and reg2 *must* be hard registers. To be sure we will | |
3534 | abort if we are passed pseudo registers. */ | |
3535 | ||
3536 | int | |
3537 | registers_ok_for_quad_peep (reg1, reg2) | |
3538 | rtx reg1, reg2; | |
3539 | { | |
3540 | /* We might have been passed a SUBREG. */ | |
3541 | if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG) | |
3542 | return 0; | |
3543 | ||
3544 | return (REGNO (reg1) == REGNO (reg2) - 1); | |
3545 | } | |
3546 | ||
3547 | /* Return 1 if addr1 and addr2 are suitable for lfq or stfq insn. addr1 and | |
3548 | addr2 must be in consecutive memory locations (addr2 == addr1 + 8). */ | |
3549 | ||
3550 | int | |
3551 | addrs_ok_for_quad_peep (addr1, addr2) | |
3552 | register rtx addr1; | |
3553 | register rtx addr2; | |
3554 | { | |
e2c953b6 | 3555 | unsigned int reg1; |
35068b43 RK |
3556 | int offset1; |
3557 | ||
3558 | /* Extract an offset (if used) from the first addr. */ | |
3559 | if (GET_CODE (addr1) == PLUS) | |
3560 | { | |
3561 | /* If not a REG, return zero. */ | |
3562 | if (GET_CODE (XEXP (addr1, 0)) != REG) | |
3563 | return 0; | |
3564 | else | |
3565 | { | |
3566 | reg1 = REGNO (XEXP (addr1, 0)); | |
3567 | /* The offset must be constant! */ | |
3568 | if (GET_CODE (XEXP (addr1, 1)) != CONST_INT) | |
3569 | return 0; | |
3570 | offset1 = INTVAL (XEXP (addr1, 1)); | |
3571 | } | |
3572 | } | |
3573 | else if (GET_CODE (addr1) != REG) | |
3574 | return 0; | |
3575 | else | |
3576 | { | |
3577 | reg1 = REGNO (addr1); | |
3578 | /* This was a simple (mem (reg)) expression. Offset is 0. */ | |
3579 | offset1 = 0; | |
3580 | } | |
3581 | ||
acad7ed3 | 3582 | /* Make sure the second address is a (mem (plus (reg) (const_int))). */ |
35068b43 RK |
3583 | if (GET_CODE (addr2) != PLUS) |
3584 | return 0; | |
3585 | ||
3586 | if (GET_CODE (XEXP (addr2, 0)) != REG | |
3587 | || GET_CODE (XEXP (addr2, 1)) != CONST_INT) | |
3588 | return 0; | |
3589 | ||
3590 | if (reg1 != REGNO (XEXP (addr2, 0))) | |
3591 | return 0; | |
3592 | ||
3593 | /* The offset for the second addr must be 8 more than the first addr. */ | |
3594 | if (INTVAL (XEXP (addr2, 1)) != offset1 + 8) | |
3595 | return 0; | |
3596 | ||
3597 | /* All the tests passed. addr1 and addr2 are valid for lfq or stfq | |
3598 | instructions. */ | |
3599 | return 1; | |
3600 | } | |
9878760c RK |
3601 | \f |
3602 | /* Return the register class of a scratch register needed to copy IN into | |
3603 | or out of a register in CLASS in MODE. If it can be done directly, | |
3604 | NO_REGS is returned. */ | |
3605 | ||
3606 | enum reg_class | |
3607 | secondary_reload_class (class, mode, in) | |
3608 | enum reg_class class; | |
296b8152 | 3609 | enum machine_mode mode ATTRIBUTE_UNUSED; |
9878760c RK |
3610 | rtx in; |
3611 | { | |
5accd822 | 3612 | int regno; |
9878760c | 3613 | |
46fad5b7 DJ |
3614 | if (TARGET_ELF || (DEFAULT_ABI == ABI_DARWIN && flag_pic)) |
3615 | { | |
3616 | /* We cannot copy a symbolic operand directly into anything | |
3617 | other than BASE_REGS for TARGET_ELF. So indicate that a | |
3618 | register from BASE_REGS is needed as an intermediate | |
3619 | register. | |
3620 | ||
3621 | On Darwin, pic addresses require a load from memory, which | |
3622 | needs a base register. */ | |
3623 | if (class != BASE_REGS | |
3624 | && (GET_CODE (in) == SYMBOL_REF | |
3625 | || GET_CODE (in) == HIGH | |
3626 | || GET_CODE (in) == LABEL_REF | |
3627 | || GET_CODE (in) == CONST)) | |
3628 | return BASE_REGS; | |
3629 | } | |
e7b7998a | 3630 | |
5accd822 DE |
3631 | if (GET_CODE (in) == REG) |
3632 | { | |
3633 | regno = REGNO (in); | |
3634 | if (regno >= FIRST_PSEUDO_REGISTER) | |
3635 | { | |
3636 | regno = true_regnum (in); | |
3637 | if (regno >= FIRST_PSEUDO_REGISTER) | |
3638 | regno = -1; | |
3639 | } | |
3640 | } | |
3641 | else if (GET_CODE (in) == SUBREG) | |
3642 | { | |
3643 | regno = true_regnum (in); | |
3644 | if (regno >= FIRST_PSEUDO_REGISTER) | |
3645 | regno = -1; | |
3646 | } | |
3647 | else | |
3648 | regno = -1; | |
3649 | ||
9878760c RK |
3650 | /* We can place anything into GENERAL_REGS and can put GENERAL_REGS |
3651 | into anything. */ | |
3652 | if (class == GENERAL_REGS || class == BASE_REGS | |
3653 | || (regno >= 0 && INT_REGNO_P (regno))) | |
3654 | return NO_REGS; | |
3655 | ||
3656 | /* Constants, memory, and FP registers can go into FP registers. */ | |
3657 | if ((regno == -1 || FP_REGNO_P (regno)) | |
3658 | && (class == FLOAT_REGS || class == NON_SPECIAL_REGS)) | |
3659 | return NO_REGS; | |
3660 | ||
3661 | /* We can copy among the CR registers. */ | |
3662 | if ((class == CR_REGS || class == CR0_REGS) | |
3663 | && regno >= 0 && CR_REGNO_P (regno)) | |
3664 | return NO_REGS; | |
3665 | ||
3666 | /* Otherwise, we need GENERAL_REGS. */ | |
3667 | return GENERAL_REGS; | |
3668 | } | |
3669 | \f | |
3670 | /* Given a comparison operation, return the bit number in CCR to test. We | |
3671 | know this is a valid comparison. | |
3672 | ||
3673 | SCC_P is 1 if this is for an scc. That means that %D will have been | |
3674 | used instead of %C, so the bits will be in different places. | |
3675 | ||
b4ac57ab | 3676 | Return -1 if OP isn't a valid comparison for some reason. */ |
9878760c RK |
3677 | |
3678 | int | |
3679 | ccr_bit (op, scc_p) | |
3680 | register rtx op; | |
3681 | int scc_p; | |
3682 | { | |
3683 | enum rtx_code code = GET_CODE (op); | |
3684 | enum machine_mode cc_mode; | |
3685 | int cc_regnum; | |
3686 | int base_bit; | |
9ebbca7d | 3687 | rtx reg; |
9878760c RK |
3688 | |
3689 | if (GET_RTX_CLASS (code) != '<') | |
3690 | return -1; | |
3691 | ||
9ebbca7d GK |
3692 | reg = XEXP (op, 0); |
3693 | ||
3694 | if (GET_CODE (reg) != REG | |
3695 | || ! CR_REGNO_P (REGNO (reg))) | |
3696 | abort (); | |
3697 | ||
3698 | cc_mode = GET_MODE (reg); | |
3699 | cc_regnum = REGNO (reg); | |
3700 | base_bit = 4 * (cc_regnum - CR0_REGNO); | |
9878760c | 3701 | |
39a10a29 | 3702 | validate_condition_mode (code, cc_mode); |
c5defebb | 3703 | |
9878760c RK |
3704 | switch (code) |
3705 | { | |
3706 | case NE: | |
3707 | return scc_p ? base_bit + 3 : base_bit + 2; | |
3708 | case EQ: | |
3709 | return base_bit + 2; | |
1c882ea4 | 3710 | case GT: case GTU: case UNLE: |
9878760c | 3711 | return base_bit + 1; |
1c882ea4 | 3712 | case LT: case LTU: case UNGE: |
9878760c | 3713 | return base_bit; |
1c882ea4 GK |
3714 | case ORDERED: case UNORDERED: |
3715 | return base_bit + 3; | |
9878760c RK |
3716 | |
3717 | case GE: case GEU: | |
39a10a29 | 3718 | /* If scc, we will have done a cror to put the bit in the |
9878760c RK |
3719 | unordered position. So test that bit. For integer, this is ! LT |
3720 | unless this is an scc insn. */ | |
39a10a29 | 3721 | return scc_p ? base_bit + 3 : base_bit; |
9878760c RK |
3722 | |
3723 | case LE: case LEU: | |
39a10a29 | 3724 | return scc_p ? base_bit + 3 : base_bit + 1; |
1c882ea4 | 3725 | |
9878760c RK |
3726 | default: |
3727 | abort (); | |
3728 | } | |
3729 | } | |
1ff7789b | 3730 | \f |
8d30c4ee | 3731 | /* Return the GOT register. */ |
1ff7789b MM |
3732 | |
3733 | struct rtx_def * | |
3734 | rs6000_got_register (value) | |
5f59ecb7 | 3735 | rtx value ATTRIBUTE_UNUSED; |
1ff7789b | 3736 | { |
8d30c4ee FS |
3737 | /* The second flow pass currently (June 1999) can't update regs_ever_live |
3738 | without disturbing other parts of the compiler, so update it here to | |
3739 | make the prolog/epilogue code happy. */ | |
3cb999d8 | 3740 | if (no_new_pseudos && ! regs_ever_live[PIC_OFFSET_TABLE_REGNUM]) |
8d30c4ee | 3741 | regs_ever_live[PIC_OFFSET_TABLE_REGNUM] = 1; |
1ff7789b | 3742 | |
8d30c4ee | 3743 | current_function_uses_pic_offset_table = 1; |
3cb999d8 | 3744 | |
1ff7789b MM |
3745 | return pic_offset_table_rtx; |
3746 | } | |
a7df97e6 | 3747 | \f |
71f123ca | 3748 | /* Functions to init, mark and free struct machine_function. |
a7df97e6 MM |
3749 | These will be called, via pointer variables, |
3750 | from push_function_context and pop_function_context. */ | |
3751 | ||
00dba523 NC |
3752 | static void |
3753 | rs6000_init_machine_status (p) | |
a7df97e6 MM |
3754 | struct function *p; |
3755 | { | |
71f123ca FS |
3756 | p->machine = (machine_function *) xcalloc (1, sizeof (machine_function)); |
3757 | } | |
a7df97e6 | 3758 | |
00dba523 NC |
3759 | static void |
3760 | rs6000_free_machine_status (p) | |
a7df97e6 MM |
3761 | struct function *p; |
3762 | { | |
00dba523 NC |
3763 | if (p->machine == NULL) |
3764 | return; | |
a7df97e6 | 3765 | |
00dba523 NC |
3766 | free (p->machine); |
3767 | p->machine = NULL; | |
a7df97e6 MM |
3768 | } |
3769 | ||
9878760c RK |
3770 | \f |
3771 | /* Print an operand. Recognize special options, documented below. */ | |
3772 | ||
38c1f2d7 | 3773 | #if TARGET_ELF |
d9407988 | 3774 | #define SMALL_DATA_RELOC ((rs6000_sdata == SDATA_EABI) ? "sda21" : "sdarel") |
8fbd2dc7 | 3775 | #define SMALL_DATA_REG ((rs6000_sdata == SDATA_EABI) ? 0 : 13) |
ba5e43aa MM |
3776 | #else |
3777 | #define SMALL_DATA_RELOC "sda21" | |
8fbd2dc7 | 3778 | #define SMALL_DATA_REG 0 |
ba5e43aa MM |
3779 | #endif |
3780 | ||
9878760c RK |
3781 | void |
3782 | print_operand (file, x, code) | |
3783 | FILE *file; | |
3784 | rtx x; | |
9ebbca7d | 3785 | int code; |
9878760c RK |
3786 | { |
3787 | int i; | |
a260abc9 | 3788 | HOST_WIDE_INT val; |
9878760c RK |
3789 | |
3790 | /* These macros test for integers and extract the low-order bits. */ | |
3791 | #define INT_P(X) \ | |
3792 | ((GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST_DOUBLE) \ | |
3793 | && GET_MODE (X) == VOIDmode) | |
3794 | ||
3795 | #define INT_LOWPART(X) \ | |
3796 | (GET_CODE (X) == CONST_INT ? INTVAL (X) : CONST_DOUBLE_LOW (X)) | |
3797 | ||
3798 | switch (code) | |
3799 | { | |
a8b3aeda | 3800 | case '.': |
a85d226b RK |
3801 | /* Write out an instruction after the call which may be replaced |
3802 | with glue code by the loader. This depends on the AIX version. */ | |
3803 | asm_fprintf (file, RS6000_CALL_GLUE); | |
a8b3aeda RK |
3804 | return; |
3805 | ||
c81bebd7 MM |
3806 | case '$': |
3807 | /* Write out either a '.' or '$' for the current location, depending | |
3808 | on whether this is Solaris or not. */ | |
3809 | putc ((DEFAULT_ABI == ABI_SOLARIS) ? '.' : '$', file); | |
3810 | return; | |
3811 | ||
81eace42 GK |
3812 | /* %a is output_address. */ |
3813 | ||
9854d9ed RK |
3814 | case 'A': |
3815 | /* If X is a constant integer whose low-order 5 bits are zero, | |
3816 | write 'l'. Otherwise, write 'r'. This is a kludge to fix a bug | |
76229ac8 | 3817 | in the AIX assembler where "sri" with a zero shift count |
9854d9ed RK |
3818 | write a trash instruction. */ |
3819 | if (GET_CODE (x) == CONST_INT && (INTVAL (x) & 31) == 0) | |
76229ac8 | 3820 | putc ('l', file); |
9854d9ed | 3821 | else |
76229ac8 | 3822 | putc ('r', file); |
9854d9ed RK |
3823 | return; |
3824 | ||
3825 | case 'b': | |
e2c953b6 DE |
3826 | /* If constant, low-order 16 bits of constant, unsigned. |
3827 | Otherwise, write normally. */ | |
3828 | if (INT_P (x)) | |
3829 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 0xffff); | |
3830 | else | |
3831 | print_operand (file, x, 0); | |
cad12a8d RK |
3832 | return; |
3833 | ||
a260abc9 DE |
3834 | case 'B': |
3835 | /* If the low-order bit is zero, write 'r'; otherwise, write 'l' | |
3836 | for 64-bit mask direction. */ | |
296b8152 | 3837 | putc (((INT_LOWPART(x) & 1) == 0 ? 'r' : 'l'), file); |
a238cd8b | 3838 | return; |
a260abc9 | 3839 | |
81eace42 GK |
3840 | /* %c is output_addr_const if a CONSTANT_ADDRESS_P, otherwise |
3841 | output_operand. */ | |
3842 | ||
9854d9ed | 3843 | case 'D': |
39a10a29 GK |
3844 | /* There used to be a comment for 'C' reading "This is an |
3845 | optional cror needed for certain floating-point | |
3846 | comparisons. Otherwise write nothing." */ | |
3847 | ||
9854d9ed RK |
3848 | /* Similar, except that this is for an scc, so we must be able to |
3849 | encode the test in a single bit that is one. We do the above | |
3850 | for any LE, GE, GEU, or LEU and invert the bit for NE. */ | |
3851 | if (GET_CODE (x) == LE || GET_CODE (x) == GE | |
3852 | || GET_CODE (x) == LEU || GET_CODE (x) == GEU) | |
3853 | { | |
9ebbca7d | 3854 | int base_bit = 4 * (REGNO (XEXP (x, 0)) - CR0_REGNO); |
9854d9ed RK |
3855 | |
3856 | fprintf (file, "cror %d,%d,%d\n\t", base_bit + 3, | |
3857 | base_bit + 2, | |
3858 | base_bit + (GET_CODE (x) == GE || GET_CODE (x) == GEU)); | |
3859 | } | |
3860 | ||
3861 | else if (GET_CODE (x) == NE) | |
3862 | { | |
9ebbca7d | 3863 | int base_bit = 4 * (REGNO (XEXP (x, 0)) - CR0_REGNO); |
9854d9ed RK |
3864 | |
3865 | fprintf (file, "crnor %d,%d,%d\n\t", base_bit + 3, | |
3866 | base_bit + 2, base_bit + 2); | |
3867 | } | |
3868 | return; | |
3869 | ||
3870 | case 'E': | |
39a10a29 | 3871 | /* X is a CR register. Print the number of the EQ bit of the CR */ |
9854d9ed RK |
3872 | if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x))) |
3873 | output_operand_lossage ("invalid %%E value"); | |
78fbdbf7 | 3874 | else |
39a10a29 | 3875 | fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO) + 2); |
a85d226b | 3876 | return; |
9854d9ed RK |
3877 | |
3878 | case 'f': | |
3879 | /* X is a CR register. Print the shift count needed to move it | |
3880 | to the high-order four bits. */ | |
3881 | if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x))) | |
3882 | output_operand_lossage ("invalid %%f value"); | |
3883 | else | |
9ebbca7d | 3884 | fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO)); |
9854d9ed RK |
3885 | return; |
3886 | ||
3887 | case 'F': | |
3888 | /* Similar, but print the count for the rotate in the opposite | |
3889 | direction. */ | |
3890 | if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x))) | |
3891 | output_operand_lossage ("invalid %%F value"); | |
3892 | else | |
9ebbca7d | 3893 | fprintf (file, "%d", 32 - 4 * (REGNO (x) - CR0_REGNO)); |
9854d9ed RK |
3894 | return; |
3895 | ||
3896 | case 'G': | |
3897 | /* X is a constant integer. If it is negative, print "m", | |
3898 | otherwise print "z". This is to make a aze or ame insn. */ | |
3899 | if (GET_CODE (x) != CONST_INT) | |
3900 | output_operand_lossage ("invalid %%G value"); | |
3901 | else if (INTVAL (x) >= 0) | |
76229ac8 | 3902 | putc ('z', file); |
9854d9ed | 3903 | else |
76229ac8 | 3904 | putc ('m', file); |
9854d9ed | 3905 | return; |
e2c953b6 | 3906 | |
9878760c | 3907 | case 'h': |
df3d94ed RK |
3908 | /* If constant, output low-order five bits. Otherwise, |
3909 | write normally. */ | |
9878760c | 3910 | if (INT_P (x)) |
5f59ecb7 | 3911 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 31); |
9878760c RK |
3912 | else |
3913 | print_operand (file, x, 0); | |
3914 | return; | |
3915 | ||
64305719 DE |
3916 | case 'H': |
3917 | /* If constant, output low-order six bits. Otherwise, | |
3918 | write normally. */ | |
3919 | if (INT_P (x)) | |
5f59ecb7 | 3920 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 63); |
64305719 DE |
3921 | else |
3922 | print_operand (file, x, 0); | |
3923 | return; | |
3924 | ||
9854d9ed RK |
3925 | case 'I': |
3926 | /* Print `i' if this is a constant, else nothing. */ | |
9878760c | 3927 | if (INT_P (x)) |
76229ac8 | 3928 | putc ('i', file); |
9878760c RK |
3929 | return; |
3930 | ||
9854d9ed RK |
3931 | case 'j': |
3932 | /* Write the bit number in CCR for jump. */ | |
3933 | i = ccr_bit (x, 0); | |
3934 | if (i == -1) | |
3935 | output_operand_lossage ("invalid %%j code"); | |
9878760c | 3936 | else |
9854d9ed | 3937 | fprintf (file, "%d", i); |
9878760c RK |
3938 | return; |
3939 | ||
9854d9ed RK |
3940 | case 'J': |
3941 | /* Similar, but add one for shift count in rlinm for scc and pass | |
3942 | scc flag to `ccr_bit'. */ | |
3943 | i = ccr_bit (x, 1); | |
3944 | if (i == -1) | |
3945 | output_operand_lossage ("invalid %%J code"); | |
3946 | else | |
a0466a68 RK |
3947 | /* If we want bit 31, write a shift count of zero, not 32. */ |
3948 | fprintf (file, "%d", i == 31 ? 0 : i + 1); | |
9878760c RK |
3949 | return; |
3950 | ||
9854d9ed RK |
3951 | case 'k': |
3952 | /* X must be a constant. Write the 1's complement of the | |
3953 | constant. */ | |
9878760c | 3954 | if (! INT_P (x)) |
9854d9ed | 3955 | output_operand_lossage ("invalid %%k value"); |
e2c953b6 DE |
3956 | else |
3957 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, ~ INT_LOWPART (x)); | |
9878760c RK |
3958 | return; |
3959 | ||
81eace42 | 3960 | case 'K': |
9ebbca7d GK |
3961 | /* X must be a symbolic constant on ELF. Write an |
3962 | expression suitable for an 'addi' that adds in the low 16 | |
3963 | bits of the MEM. */ | |
3964 | if (GET_CODE (x) != CONST) | |
3965 | { | |
3966 | print_operand_address (file, x); | |
3967 | fputs ("@l", file); | |
3968 | } | |
3969 | else | |
3970 | { | |
3971 | if (GET_CODE (XEXP (x, 0)) != PLUS | |
3972 | || (GET_CODE (XEXP (XEXP (x, 0), 0)) != SYMBOL_REF | |
3973 | && GET_CODE (XEXP (XEXP (x, 0), 0)) != LABEL_REF) | |
3974 | || GET_CODE (XEXP (XEXP (x, 0), 1)) != CONST_INT) | |
53cd5d6c | 3975 | output_operand_lossage ("invalid %%K value"); |
9ebbca7d GK |
3976 | print_operand_address (file, XEXP (XEXP (x, 0), 0)); |
3977 | fputs ("@l", file); | |
3978 | print_operand (file, XEXP (XEXP (x, 0), 1), 0); | |
3979 | } | |
81eace42 GK |
3980 | return; |
3981 | ||
3982 | /* %l is output_asm_label. */ | |
9ebbca7d | 3983 | |
9854d9ed RK |
3984 | case 'L': |
3985 | /* Write second word of DImode or DFmode reference. Works on register | |
3986 | or non-indexed memory only. */ | |
3987 | if (GET_CODE (x) == REG) | |
5ebfb2ba | 3988 | fprintf (file, "%s", reg_names[REGNO (x) + 1]); |
9854d9ed RK |
3989 | else if (GET_CODE (x) == MEM) |
3990 | { | |
3991 | /* Handle possible auto-increment. Since it is pre-increment and | |
1427100a | 3992 | we have already done it, we can just use an offset of word. */ |
9854d9ed RK |
3993 | if (GET_CODE (XEXP (x, 0)) == PRE_INC |
3994 | || GET_CODE (XEXP (x, 0)) == PRE_DEC) | |
ed8908e7 RK |
3995 | output_address (plus_constant (XEXP (XEXP (x, 0), 0), |
3996 | UNITS_PER_WORD)); | |
9854d9ed | 3997 | else |
ed8908e7 RK |
3998 | output_address (plus_constant (XEXP (x, 0), UNITS_PER_WORD)); |
3999 | ||
ba5e43aa | 4000 | if (small_data_operand (x, GET_MODE (x))) |
8fbd2dc7 MM |
4001 | fprintf (file, "@%s(%s)", SMALL_DATA_RELOC, |
4002 | reg_names[SMALL_DATA_REG]); | |
9854d9ed | 4003 | } |
9878760c | 4004 | return; |
9854d9ed | 4005 | |
9878760c RK |
4006 | case 'm': |
4007 | /* MB value for a mask operand. */ | |
4008 | if (! mask_operand (x, VOIDmode)) | |
4009 | output_operand_lossage ("invalid %%m value"); | |
4010 | ||
4011 | val = INT_LOWPART (x); | |
4012 | ||
4013 | /* If the high bit is set and the low bit is not, the value is zero. | |
4014 | If the high bit is zero, the value is the first 1 bit we find from | |
4015 | the left. */ | |
0858c623 | 4016 | if ((val & 0x80000000) && ((val & 1) == 0)) |
9878760c | 4017 | { |
19d2d16f | 4018 | putc ('0', file); |
9878760c RK |
4019 | return; |
4020 | } | |
0858c623 | 4021 | else if ((val & 0x80000000) == 0) |
9878760c RK |
4022 | { |
4023 | for (i = 1; i < 32; i++) | |
0858c623 | 4024 | if ((val <<= 1) & 0x80000000) |
9878760c RK |
4025 | break; |
4026 | fprintf (file, "%d", i); | |
4027 | return; | |
4028 | } | |
4029 | ||
4030 | /* Otherwise, look for the first 0 bit from the right. The result is its | |
4031 | number plus 1. We know the low-order bit is one. */ | |
4032 | for (i = 0; i < 32; i++) | |
4033 | if (((val >>= 1) & 1) == 0) | |
4034 | break; | |
4035 | ||
a260abc9 | 4036 | /* If we ended in ...01, i would be 0. The correct value is 31, so |
9878760c RK |
4037 | we want 31 - i. */ |
4038 | fprintf (file, "%d", 31 - i); | |
4039 | return; | |
4040 | ||
4041 | case 'M': | |
4042 | /* ME value for a mask operand. */ | |
4043 | if (! mask_operand (x, VOIDmode)) | |
a260abc9 | 4044 | output_operand_lossage ("invalid %%M value"); |
9878760c RK |
4045 | |
4046 | val = INT_LOWPART (x); | |
4047 | ||
4048 | /* If the low bit is set and the high bit is not, the value is 31. | |
4049 | If the low bit is zero, the value is the first 1 bit we find from | |
4050 | the right. */ | |
0858c623 | 4051 | if ((val & 1) && ((val & 0x80000000) == 0)) |
9878760c | 4052 | { |
76229ac8 | 4053 | fputs ("31", file); |
9878760c RK |
4054 | return; |
4055 | } | |
4056 | else if ((val & 1) == 0) | |
4057 | { | |
4058 | for (i = 0; i < 32; i++) | |
4059 | if ((val >>= 1) & 1) | |
4060 | break; | |
4061 | ||
a260abc9 | 4062 | /* If we had ....10, i would be 0. The result should be |
9878760c RK |
4063 | 30, so we need 30 - i. */ |
4064 | fprintf (file, "%d", 30 - i); | |
4065 | return; | |
4066 | } | |
4067 | ||
4068 | /* Otherwise, look for the first 0 bit from the left. The result is its | |
4069 | number minus 1. We know the high-order bit is one. */ | |
4070 | for (i = 0; i < 32; i++) | |
0858c623 | 4071 | if (((val <<= 1) & 0x80000000) == 0) |
9878760c RK |
4072 | break; |
4073 | ||
4074 | fprintf (file, "%d", i); | |
4075 | return; | |
4076 | ||
81eace42 GK |
4077 | /* %n outputs the negative of its operand. */ |
4078 | ||
9878760c RK |
4079 | case 'N': |
4080 | /* Write the number of elements in the vector times 4. */ | |
4081 | if (GET_CODE (x) != PARALLEL) | |
4082 | output_operand_lossage ("invalid %%N value"); | |
e2c953b6 DE |
4083 | else |
4084 | fprintf (file, "%d", XVECLEN (x, 0) * 4); | |
9878760c RK |
4085 | return; |
4086 | ||
4087 | case 'O': | |
4088 | /* Similar, but subtract 1 first. */ | |
4089 | if (GET_CODE (x) != PARALLEL) | |
1427100a | 4090 | output_operand_lossage ("invalid %%O value"); |
e2c953b6 DE |
4091 | else |
4092 | fprintf (file, "%d", (XVECLEN (x, 0) - 1) * 4); | |
9878760c RK |
4093 | return; |
4094 | ||
9854d9ed RK |
4095 | case 'p': |
4096 | /* X is a CONST_INT that is a power of two. Output the logarithm. */ | |
4097 | if (! INT_P (x) | |
4098 | || (i = exact_log2 (INT_LOWPART (x))) < 0) | |
4099 | output_operand_lossage ("invalid %%p value"); | |
e2c953b6 DE |
4100 | else |
4101 | fprintf (file, "%d", i); | |
9854d9ed RK |
4102 | return; |
4103 | ||
9878760c RK |
4104 | case 'P': |
4105 | /* The operand must be an indirect memory reference. The result | |
4106 | is the register number. */ | |
4107 | if (GET_CODE (x) != MEM || GET_CODE (XEXP (x, 0)) != REG | |
4108 | || REGNO (XEXP (x, 0)) >= 32) | |
4109 | output_operand_lossage ("invalid %%P value"); | |
e2c953b6 DE |
4110 | else |
4111 | fprintf (file, "%d", REGNO (XEXP (x, 0))); | |
9878760c RK |
4112 | return; |
4113 | ||
dfbdccdb GK |
4114 | case 'q': |
4115 | /* This outputs the logical code corresponding to a boolean | |
4116 | expression. The expression may have one or both operands | |
39a10a29 GK |
4117 | negated (if one, only the first one). For condition register |
4118 | logical operations, it will also treat the negated | |
4119 | CR codes as NOTs, but not handle NOTs of them. */ | |
dfbdccdb | 4120 | { |
63bc1d05 | 4121 | const char *const *t = 0; |
dfbdccdb GK |
4122 | const char *s; |
4123 | enum rtx_code code = GET_CODE (x); | |
4124 | static const char * const tbl[3][3] = { | |
4125 | { "and", "andc", "nor" }, | |
4126 | { "or", "orc", "nand" }, | |
4127 | { "xor", "eqv", "xor" } }; | |
4128 | ||
4129 | if (code == AND) | |
4130 | t = tbl[0]; | |
4131 | else if (code == IOR) | |
4132 | t = tbl[1]; | |
4133 | else if (code == XOR) | |
4134 | t = tbl[2]; | |
4135 | else | |
4136 | output_operand_lossage ("invalid %%q value"); | |
4137 | ||
4138 | if (GET_CODE (XEXP (x, 0)) != NOT) | |
4139 | s = t[0]; | |
4140 | else | |
4141 | { | |
4142 | if (GET_CODE (XEXP (x, 1)) == NOT) | |
4143 | s = t[2]; | |
4144 | else | |
4145 | s = t[1]; | |
4146 | } | |
4147 | ||
4148 | fputs (s, file); | |
4149 | } | |
4150 | return; | |
4151 | ||
9854d9ed RK |
4152 | case 'R': |
4153 | /* X is a CR register. Print the mask for `mtcrf'. */ | |
4154 | if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x))) | |
4155 | output_operand_lossage ("invalid %%R value"); | |
4156 | else | |
9ebbca7d | 4157 | fprintf (file, "%d", 128 >> (REGNO (x) - CR0_REGNO)); |
9878760c | 4158 | return; |
9854d9ed RK |
4159 | |
4160 | case 's': | |
4161 | /* Low 5 bits of 32 - value */ | |
4162 | if (! INT_P (x)) | |
4163 | output_operand_lossage ("invalid %%s value"); | |
e2c953b6 DE |
4164 | else |
4165 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, (32 - INT_LOWPART (x)) & 31); | |
9878760c | 4166 | return; |
9854d9ed | 4167 | |
a260abc9 DE |
4168 | case 'S': |
4169 | /* PowerPC64 mask position. All 0's and all 1's are excluded. | |
4170 | CONST_INT 32-bit mask is considered sign-extended so any | |
4171 | transition must occur within the CONST_INT, not on the boundary. */ | |
4172 | if (! mask64_operand (x, VOIDmode)) | |
4173 | output_operand_lossage ("invalid %%S value"); | |
4174 | ||
4175 | val = INT_LOWPART (x); | |
4176 | ||
4177 | if (val & 1) /* Clear Left */ | |
4178 | { | |
a238cd8b DE |
4179 | for (i = 0; i < HOST_BITS_PER_WIDE_INT; i++) |
4180 | if (!((val >>= 1) & 1)) | |
4181 | break; | |
a260abc9 | 4182 | |
a238cd8b DE |
4183 | #if HOST_BITS_PER_WIDE_INT == 32 |
4184 | if (GET_CODE (x) == CONST_DOUBLE && i == 32) | |
4185 | { | |
4186 | val = CONST_DOUBLE_HIGH (x); | |
4187 | ||
4188 | if (val == 0) | |
4189 | --i; | |
4190 | else | |
4191 | for (i = 32; i < 64; i++) | |
4192 | if (!((val >>= 1) & 1)) | |
4193 | break; | |
4194 | } | |
a260abc9 | 4195 | #endif |
a238cd8b DE |
4196 | /* i = index of last set bit from right |
4197 | mask begins at 63 - i from left */ | |
4198 | if (i > 63) | |
4199 | output_operand_lossage ("%%S computed all 1's mask"); | |
cccf3bdc | 4200 | |
a260abc9 DE |
4201 | fprintf (file, "%d", 63 - i); |
4202 | return; | |
4203 | } | |
4204 | else /* Clear Right */ | |
4205 | { | |
a238cd8b DE |
4206 | for (i = 0; i < HOST_BITS_PER_WIDE_INT; i++) |
4207 | if ((val >>= 1) & 1) | |
4208 | break; | |
a260abc9 | 4209 | |
a238cd8b | 4210 | #if HOST_BITS_PER_WIDE_INT == 32 |
a260abc9 DE |
4211 | if (GET_CODE (x) == CONST_DOUBLE && i == 32) |
4212 | { | |
a238cd8b | 4213 | val = CONST_DOUBLE_HIGH (x); |
a260abc9 | 4214 | |
a238cd8b | 4215 | if (val == (HOST_WIDE_INT) -1) |
a260abc9 | 4216 | --i; |
a260abc9 | 4217 | else |
a238cd8b DE |
4218 | for (i = 32; i < 64; i++) |
4219 | if ((val >>= 1) & 1) | |
a260abc9 DE |
4220 | break; |
4221 | } | |
4222 | #endif | |
a238cd8b DE |
4223 | /* i = index of last clear bit from right |
4224 | mask ends at 62 - i from left */ | |
4225 | if (i > 62) | |
4226 | output_operand_lossage ("%%S computed all 0's mask"); | |
cccf3bdc | 4227 | |
a238cd8b | 4228 | fprintf (file, "%d", 62 - i); |
a260abc9 DE |
4229 | return; |
4230 | } | |
4231 | ||
cccf3bdc DE |
4232 | case 'T': |
4233 | /* Print the symbolic name of a branch target register. */ | |
4234 | if (GET_CODE (x) != REG || (REGNO (x) != LINK_REGISTER_REGNUM | |
4235 | && REGNO (x) != COUNT_REGISTER_REGNUM)) | |
4236 | output_operand_lossage ("invalid %%T value"); | |
e2c953b6 | 4237 | else if (REGNO (x) == LINK_REGISTER_REGNUM) |
cccf3bdc DE |
4238 | fputs (TARGET_NEW_MNEMONICS ? "lr" : "r", file); |
4239 | else | |
4240 | fputs ("ctr", file); | |
4241 | return; | |
4242 | ||
9854d9ed | 4243 | case 'u': |
802a0058 | 4244 | /* High-order 16 bits of constant for use in unsigned operand. */ |
9854d9ed RK |
4245 | if (! INT_P (x)) |
4246 | output_operand_lossage ("invalid %%u value"); | |
e2c953b6 DE |
4247 | else |
4248 | fprintf (file, HOST_WIDE_INT_PRINT_HEX, | |
4249 | (INT_LOWPART (x) >> 16) & 0xffff); | |
9878760c RK |
4250 | return; |
4251 | ||
802a0058 MM |
4252 | case 'v': |
4253 | /* High-order 16 bits of constant for use in signed operand. */ | |
4254 | if (! INT_P (x)) | |
4255 | output_operand_lossage ("invalid %%v value"); | |
e2c953b6 DE |
4256 | else |
4257 | { | |
4258 | int value = (INT_LOWPART (x) >> 16) & 0xffff; | |
802a0058 | 4259 | |
e2c953b6 DE |
4260 | /* Solaris assembler doesn't like lis 0,0x8000 */ |
4261 | if (DEFAULT_ABI == ABI_SOLARIS && (value & 0x8000) != 0) | |
4262 | fprintf (file, "%d", value | (~0 << 16)); | |
4263 | else | |
4264 | fprintf (file, "0x%x", value); | |
4265 | return; | |
4266 | } | |
802a0058 | 4267 | |
9854d9ed RK |
4268 | case 'U': |
4269 | /* Print `u' if this has an auto-increment or auto-decrement. */ | |
4270 | if (GET_CODE (x) == MEM | |
4271 | && (GET_CODE (XEXP (x, 0)) == PRE_INC | |
4272 | || GET_CODE (XEXP (x, 0)) == PRE_DEC)) | |
76229ac8 | 4273 | putc ('u', file); |
9854d9ed | 4274 | return; |
9878760c | 4275 | |
e0cd0770 JC |
4276 | case 'V': |
4277 | /* Print the trap code for this operand. */ | |
4278 | switch (GET_CODE (x)) | |
4279 | { | |
4280 | case EQ: | |
4281 | fputs ("eq", file); /* 4 */ | |
4282 | break; | |
4283 | case NE: | |
4284 | fputs ("ne", file); /* 24 */ | |
4285 | break; | |
4286 | case LT: | |
4287 | fputs ("lt", file); /* 16 */ | |
4288 | break; | |
4289 | case LE: | |
4290 | fputs ("le", file); /* 20 */ | |
4291 | break; | |
4292 | case GT: | |
4293 | fputs ("gt", file); /* 8 */ | |
4294 | break; | |
4295 | case GE: | |
4296 | fputs ("ge", file); /* 12 */ | |
4297 | break; | |
4298 | case LTU: | |
4299 | fputs ("llt", file); /* 2 */ | |
4300 | break; | |
4301 | case LEU: | |
4302 | fputs ("lle", file); /* 6 */ | |
4303 | break; | |
4304 | case GTU: | |
4305 | fputs ("lgt", file); /* 1 */ | |
4306 | break; | |
4307 | case GEU: | |
4308 | fputs ("lge", file); /* 5 */ | |
4309 | break; | |
4310 | default: | |
4311 | abort (); | |
4312 | } | |
4313 | break; | |
4314 | ||
9854d9ed RK |
4315 | case 'w': |
4316 | /* If constant, low-order 16 bits of constant, signed. Otherwise, write | |
4317 | normally. */ | |
4318 | if (INT_P (x)) | |
5f59ecb7 DE |
4319 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, |
4320 | ((INT_LOWPART (x) & 0xffff) ^ 0x8000) - 0x8000); | |
9854d9ed RK |
4321 | else |
4322 | print_operand (file, x, 0); | |
9878760c RK |
4323 | return; |
4324 | ||
9854d9ed | 4325 | case 'W': |
e2c953b6 DE |
4326 | /* MB value for a PowerPC64 rldic operand. */ |
4327 | if (! rldic_operand (x, VOIDmode)) | |
4328 | output_operand_lossage ("invalid %%W value"); | |
4329 | ||
4330 | val = (GET_CODE (x) == CONST_INT | |
4331 | ? INTVAL (x) : CONST_DOUBLE_HIGH (x)); | |
4332 | ||
4333 | if (val < 0) | |
4334 | i = -1; | |
9854d9ed | 4335 | else |
e2c953b6 DE |
4336 | for (i = 0; i < HOST_BITS_PER_WIDE_INT; i++) |
4337 | if ((val <<= 1) < 0) | |
4338 | break; | |
4339 | ||
4340 | #if HOST_BITS_PER_WIDE_INT == 32 | |
4341 | if (GET_CODE (x) == CONST_INT && i >= 0) | |
4342 | i += 32; /* zero-extend high-part was all 0's */ | |
4343 | else if (GET_CODE (x) == CONST_DOUBLE && i == 32) | |
4344 | { | |
4345 | val = CONST_DOUBLE_LOW (x); | |
4346 | ||
4347 | if (val == 0) | |
4348 | abort(); | |
4349 | else if (val < 0) | |
4350 | --i; | |
4351 | else | |
4352 | for ( ; i < 64; i++) | |
4353 | if ((val <<= 1) < 0) | |
4354 | break; | |
4355 | } | |
4356 | #endif | |
4357 | ||
4358 | fprintf (file, "%d", i + 1); | |
9854d9ed | 4359 | return; |
9878760c | 4360 | |
9854d9ed RK |
4361 | case 'X': |
4362 | if (GET_CODE (x) == MEM | |
258bfae2 | 4363 | && LEGITIMATE_INDEXED_ADDRESS_P (XEXP (x, 0), 0)) |
76229ac8 | 4364 | putc ('x', file); |
9854d9ed | 4365 | return; |
9878760c | 4366 | |
9854d9ed RK |
4367 | case 'Y': |
4368 | /* Like 'L', for third word of TImode */ | |
4369 | if (GET_CODE (x) == REG) | |
5ebfb2ba | 4370 | fprintf (file, "%s", reg_names[REGNO (x) + 2]); |
9854d9ed | 4371 | else if (GET_CODE (x) == MEM) |
9878760c | 4372 | { |
9854d9ed RK |
4373 | if (GET_CODE (XEXP (x, 0)) == PRE_INC |
4374 | || GET_CODE (XEXP (x, 0)) == PRE_DEC) | |
a54d04b7 | 4375 | output_address (plus_constant (XEXP (XEXP (x, 0), 0), 8)); |
9854d9ed | 4376 | else |
a54d04b7 | 4377 | output_address (plus_constant (XEXP (x, 0), 8)); |
ba5e43aa | 4378 | if (small_data_operand (x, GET_MODE (x))) |
8fbd2dc7 MM |
4379 | fprintf (file, "@%s(%s)", SMALL_DATA_RELOC, |
4380 | reg_names[SMALL_DATA_REG]); | |
9878760c RK |
4381 | } |
4382 | return; | |
9854d9ed | 4383 | |
9878760c | 4384 | case 'z': |
b4ac57ab RS |
4385 | /* X is a SYMBOL_REF. Write out the name preceded by a |
4386 | period and without any trailing data in brackets. Used for function | |
4d30c363 MM |
4387 | names. If we are configured for System V (or the embedded ABI) on |
4388 | the PowerPC, do not emit the period, since those systems do not use | |
4389 | TOCs and the like. */ | |
9878760c RK |
4390 | if (GET_CODE (x) != SYMBOL_REF) |
4391 | abort (); | |
4392 | ||
b6c9286a MM |
4393 | if (XSTR (x, 0)[0] != '.') |
4394 | { | |
4395 | switch (DEFAULT_ABI) | |
4396 | { | |
4397 | default: | |
4398 | abort (); | |
4399 | ||
4400 | case ABI_AIX: | |
4401 | putc ('.', file); | |
4402 | break; | |
4403 | ||
4404 | case ABI_V4: | |
4405 | case ABI_AIX_NODESC: | |
c81bebd7 | 4406 | case ABI_SOLARIS: |
ee890fe2 | 4407 | case ABI_DARWIN: |
b6c9286a | 4408 | break; |
b6c9286a MM |
4409 | } |
4410 | } | |
9ebbca7d | 4411 | #if TARGET_AIX |
9878760c | 4412 | RS6000_OUTPUT_BASENAME (file, XSTR (x, 0)); |
9ebbca7d GK |
4413 | #else |
4414 | assemble_name (file, XSTR (x, 0)); | |
4415 | #endif | |
9878760c RK |
4416 | return; |
4417 | ||
9854d9ed RK |
4418 | case 'Z': |
4419 | /* Like 'L', for last word of TImode. */ | |
4420 | if (GET_CODE (x) == REG) | |
5ebfb2ba | 4421 | fprintf (file, "%s", reg_names[REGNO (x) + 3]); |
9854d9ed RK |
4422 | else if (GET_CODE (x) == MEM) |
4423 | { | |
4424 | if (GET_CODE (XEXP (x, 0)) == PRE_INC | |
4425 | || GET_CODE (XEXP (x, 0)) == PRE_DEC) | |
a54d04b7 | 4426 | output_address (plus_constant (XEXP (XEXP (x, 0), 0), 12)); |
9854d9ed | 4427 | else |
a54d04b7 | 4428 | output_address (plus_constant (XEXP (x, 0), 12)); |
ba5e43aa | 4429 | if (small_data_operand (x, GET_MODE (x))) |
8fbd2dc7 MM |
4430 | fprintf (file, "@%s(%s)", SMALL_DATA_RELOC, |
4431 | reg_names[SMALL_DATA_REG]); | |
9854d9ed | 4432 | } |
5c23c401 | 4433 | return; |
9854d9ed | 4434 | |
9878760c RK |
4435 | case 0: |
4436 | if (GET_CODE (x) == REG) | |
4437 | fprintf (file, "%s", reg_names[REGNO (x)]); | |
4438 | else if (GET_CODE (x) == MEM) | |
4439 | { | |
4440 | /* We need to handle PRE_INC and PRE_DEC here, since we need to | |
4441 | know the width from the mode. */ | |
4442 | if (GET_CODE (XEXP (x, 0)) == PRE_INC) | |
79ba6d34 MM |
4443 | fprintf (file, "%d(%s)", GET_MODE_SIZE (GET_MODE (x)), |
4444 | reg_names[REGNO (XEXP (XEXP (x, 0), 0))]); | |
9878760c | 4445 | else if (GET_CODE (XEXP (x, 0)) == PRE_DEC) |
79ba6d34 MM |
4446 | fprintf (file, "%d(%s)", - GET_MODE_SIZE (GET_MODE (x)), |
4447 | reg_names[REGNO (XEXP (XEXP (x, 0), 0))]); | |
9878760c | 4448 | else |
a54d04b7 | 4449 | output_address (XEXP (x, 0)); |
9878760c RK |
4450 | } |
4451 | else | |
a54d04b7 | 4452 | output_addr_const (file, x); |
a85d226b | 4453 | return; |
9878760c RK |
4454 | |
4455 | default: | |
4456 | output_operand_lossage ("invalid %%xn code"); | |
4457 | } | |
4458 | } | |
4459 | \f | |
4460 | /* Print the address of an operand. */ | |
4461 | ||
4462 | void | |
4463 | print_operand_address (file, x) | |
4464 | FILE *file; | |
4465 | register rtx x; | |
4466 | { | |
4467 | if (GET_CODE (x) == REG) | |
4697a36c | 4468 | fprintf (file, "0(%s)", reg_names[ REGNO (x) ]); |
9ebbca7d GK |
4469 | else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST |
4470 | || GET_CODE (x) == LABEL_REF) | |
9878760c RK |
4471 | { |
4472 | output_addr_const (file, x); | |
ba5e43aa | 4473 | if (small_data_operand (x, GET_MODE (x))) |
8fbd2dc7 MM |
4474 | fprintf (file, "@%s(%s)", SMALL_DATA_RELOC, |
4475 | reg_names[SMALL_DATA_REG]); | |
9ebbca7d GK |
4476 | else if (TARGET_TOC) |
4477 | abort(); | |
9878760c RK |
4478 | } |
4479 | else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == REG) | |
4480 | { | |
4481 | if (REGNO (XEXP (x, 0)) == 0) | |
4697a36c MM |
4482 | fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 1)) ], |
4483 | reg_names[ REGNO (XEXP (x, 0)) ]); | |
9878760c | 4484 | else |
4697a36c MM |
4485 | fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 0)) ], |
4486 | reg_names[ REGNO (XEXP (x, 1)) ]); | |
9878760c RK |
4487 | } |
4488 | else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT) | |
5f59ecb7 DE |
4489 | { |
4490 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (XEXP (x, 1))); | |
4491 | fprintf (file, "(%s)", reg_names[ REGNO (XEXP (x, 0)) ]); | |
4492 | } | |
3cb999d8 DE |
4493 | #if TARGET_ELF |
4494 | else if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 0)) == REG | |
4495 | && CONSTANT_P (XEXP (x, 1))) | |
4697a36c MM |
4496 | { |
4497 | output_addr_const (file, XEXP (x, 1)); | |
4498 | fprintf (file, "@l(%s)", reg_names[ REGNO (XEXP (x, 0)) ]); | |
4499 | } | |
3cb999d8 | 4500 | #endif |
9ebbca7d GK |
4501 | else if (LEGITIMATE_CONSTANT_POOL_ADDRESS_P (x)) |
4502 | { | |
4503 | if (TARGET_AIX) | |
4504 | { | |
4505 | rtx contains_minus = XEXP (x, 1); | |
4506 | rtx minus; | |
4507 | ||
4508 | /* Find the (minus (sym) (toc)) buried in X, and temporarily | |
4509 | turn it into (sym) for output_addr_const. */ | |
4510 | while (GET_CODE (XEXP (contains_minus, 0)) != MINUS) | |
4511 | contains_minus = XEXP (contains_minus, 0); | |
4512 | ||
4513 | minus = XEXP (contains_minus, 0); | |
4514 | XEXP (contains_minus, 0) = XEXP (minus, 0); | |
4515 | output_addr_const (file, XEXP (x, 1)); | |
4516 | XEXP (contains_minus, 0) = minus; | |
4517 | } | |
4518 | else | |
4519 | output_addr_const (file, XEXP (x, 1)); | |
4520 | ||
4521 | fprintf (file, "(%s)", reg_names[REGNO (XEXP (x, 0))]); | |
4522 | } | |
9878760c RK |
4523 | else |
4524 | abort (); | |
4525 | } | |
4526 | \f | |
39a10a29 GK |
4527 | enum rtx_code |
4528 | rs6000_reverse_condition (mode, code) | |
4529 | enum machine_mode mode; | |
4530 | enum rtx_code code; | |
4531 | { | |
4532 | /* Reversal of FP compares takes care -- an ordered compare | |
4533 | becomes an unordered compare and vice versa. */ | |
4534 | if (mode == CCFPmode) | |
bab6226b | 4535 | return reverse_condition_maybe_unordered (code); |
39a10a29 | 4536 | else |
bab6226b | 4537 | return reverse_condition (code); |
39a10a29 GK |
4538 | } |
4539 | ||
4540 | ||
4541 | /* Generate a compare for CODE. Return a brand-new rtx that | |
4542 | represents the result of the compare. */ | |
4543 | static rtx | |
4544 | rs6000_generate_compare (code) | |
4545 | enum rtx_code code; | |
4546 | { | |
4547 | enum machine_mode comp_mode; | |
4548 | rtx compare_result; | |
4549 | ||
4550 | if (rs6000_compare_fp_p) | |
4551 | comp_mode = CCFPmode; | |
4552 | else if (code == GTU || code == LTU | |
4553 | || code == GEU || code == LEU) | |
4554 | comp_mode = CCUNSmode; | |
4555 | else | |
4556 | comp_mode = CCmode; | |
4557 | ||
4558 | /* First, the compare. */ | |
4559 | compare_result = gen_reg_rtx (comp_mode); | |
4560 | emit_insn (gen_rtx_SET (VOIDmode, compare_result, | |
4561 | gen_rtx_COMPARE (comp_mode, | |
4562 | rs6000_compare_op0, | |
4563 | rs6000_compare_op1))); | |
4564 | ||
ca5adc63 | 4565 | /* Some kinds of FP comparisons need an OR operation; |
de6c5979 | 4566 | except for flag_unsafe_math_optimizations we don't bother. */ |
39a10a29 | 4567 | if (rs6000_compare_fp_p |
de6c5979 | 4568 | && ! flag_unsafe_math_optimizations |
39a10a29 GK |
4569 | && (code == LE || code == GE |
4570 | || code == UNEQ || code == LTGT | |
4571 | || code == UNGT || code == UNLT)) | |
4572 | { | |
4573 | enum rtx_code or1, or2; | |
4574 | rtx or1_rtx, or2_rtx, compare2_rtx; | |
4575 | rtx or_result = gen_reg_rtx (CCEQmode); | |
4576 | ||
4577 | switch (code) | |
4578 | { | |
4579 | case LE: or1 = LT; or2 = EQ; break; | |
4580 | case GE: or1 = GT; or2 = EQ; break; | |
4581 | case UNEQ: or1 = UNORDERED; or2 = EQ; break; | |
4582 | case LTGT: or1 = LT; or2 = GT; break; | |
4583 | case UNGT: or1 = UNORDERED; or2 = GT; break; | |
4584 | case UNLT: or1 = UNORDERED; or2 = LT; break; | |
4585 | default: abort (); | |
4586 | } | |
4587 | validate_condition_mode (or1, comp_mode); | |
4588 | validate_condition_mode (or2, comp_mode); | |
4589 | or1_rtx = gen_rtx (or1, SImode, compare_result, const0_rtx); | |
4590 | or2_rtx = gen_rtx (or2, SImode, compare_result, const0_rtx); | |
4591 | compare2_rtx = gen_rtx_COMPARE (CCEQmode, | |
4592 | gen_rtx_IOR (SImode, or1_rtx, or2_rtx), | |
4593 | const_true_rtx); | |
4594 | emit_insn (gen_rtx_SET (VOIDmode, or_result, compare2_rtx)); | |
4595 | ||
4596 | compare_result = or_result; | |
4597 | code = EQ; | |
4598 | } | |
4599 | ||
4600 | validate_condition_mode (code, GET_MODE (compare_result)); | |
4601 | ||
4602 | return gen_rtx (code, VOIDmode, compare_result, const0_rtx); | |
4603 | } | |
4604 | ||
4605 | ||
4606 | /* Emit the RTL for an sCOND pattern. */ | |
4607 | ||
4608 | void | |
4609 | rs6000_emit_sCOND (code, result) | |
4610 | enum rtx_code code; | |
4611 | rtx result; | |
4612 | { | |
4613 | rtx condition_rtx; | |
4614 | enum machine_mode op_mode; | |
4615 | ||
4616 | condition_rtx = rs6000_generate_compare (code); | |
4617 | ||
4618 | op_mode = GET_MODE (rs6000_compare_op0); | |
4619 | if (op_mode == VOIDmode) | |
4620 | op_mode = GET_MODE (rs6000_compare_op1); | |
4621 | ||
4622 | if (TARGET_POWERPC64 && (op_mode == DImode || rs6000_compare_fp_p)) | |
4623 | { | |
4624 | PUT_MODE (condition_rtx, DImode); | |
4625 | convert_move (result, condition_rtx, 0); | |
4626 | } | |
4627 | else | |
4628 | { | |
4629 | PUT_MODE (condition_rtx, SImode); | |
4630 | emit_insn (gen_rtx_SET (VOIDmode, result, condition_rtx)); | |
4631 | } | |
4632 | } | |
4633 | ||
4634 | ||
4635 | /* Emit a branch of kind CODE to location LOC. */ | |
4636 | ||
4637 | void | |
4638 | rs6000_emit_cbranch (code, loc) | |
4639 | enum rtx_code code; | |
4640 | rtx loc; | |
4641 | { | |
4642 | rtx condition_rtx, loc_ref; | |
4643 | ||
4644 | condition_rtx = rs6000_generate_compare (code); | |
4645 | loc_ref = gen_rtx_LABEL_REF (VOIDmode, loc); | |
4646 | emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, | |
4647 | gen_rtx_IF_THEN_ELSE (VOIDmode, condition_rtx, | |
4648 | loc_ref, pc_rtx))); | |
4649 | } | |
4650 | ||
4651 | ||
12a4e8c5 GK |
4652 | /* Return the string to output a conditional branch to LABEL, which is |
4653 | the operand number of the label, or -1 if the branch is really a | |
4654 | conditional return. | |
4655 | ||
4656 | OP is the conditional expression. XEXP (OP, 0) is assumed to be a | |
4657 | condition code register and its mode specifies what kind of | |
4658 | comparison we made. | |
4659 | ||
4660 | REVERSED is non-zero if we should reverse the sense of the comparison. | |
4661 | ||
4662 | INSN is the insn. */ | |
4663 | ||
4664 | char * | |
4665 | output_cbranch (op, label, reversed, insn) | |
4666 | rtx op; | |
4667 | const char * label; | |
4668 | int reversed; | |
4669 | rtx insn; | |
4670 | { | |
4671 | static char string[64]; | |
4672 | enum rtx_code code = GET_CODE (op); | |
4673 | rtx cc_reg = XEXP (op, 0); | |
4674 | enum machine_mode mode = GET_MODE (cc_reg); | |
4675 | int cc_regno = REGNO (cc_reg) - CR0_REGNO; | |
39a10a29 | 4676 | int need_longbranch = label != NULL && get_attr_length (insn) == 8; |
12a4e8c5 GK |
4677 | int really_reversed = reversed ^ need_longbranch; |
4678 | char *s = string; | |
4679 | const char *ccode; | |
4680 | const char *pred; | |
4681 | rtx note; | |
4682 | ||
39a10a29 GK |
4683 | validate_condition_mode (code, mode); |
4684 | ||
4685 | /* Work out which way this really branches. We could use | |
4686 | reverse_condition_maybe_unordered here always but this | |
4687 | makes the resulting assembler clearer. */ | |
12a4e8c5 | 4688 | if (really_reversed) |
39a10a29 | 4689 | code = rs6000_reverse_condition (mode, code); |
12a4e8c5 | 4690 | |
39a10a29 | 4691 | switch (code) |
12a4e8c5 GK |
4692 | { |
4693 | /* Not all of these are actually distinct opcodes, but | |
4694 | we distinguish them for clarity of the resulting assembler. */ | |
50a0b056 GK |
4695 | case NE: case LTGT: |
4696 | ccode = "ne"; break; | |
4697 | case EQ: case UNEQ: | |
4698 | ccode = "eq"; break; | |
4699 | case GE: case GEU: | |
4700 | ccode = "ge"; break; | |
4701 | case GT: case GTU: case UNGT: | |
4702 | ccode = "gt"; break; | |
4703 | case LE: case LEU: | |
4704 | ccode = "le"; break; | |
4705 | case LT: case LTU: case UNLT: | |
4706 | ccode = "lt"; break; | |
12a4e8c5 GK |
4707 | case UNORDERED: ccode = "un"; break; |
4708 | case ORDERED: ccode = "nu"; break; | |
4709 | case UNGE: ccode = "nl"; break; | |
4710 | case UNLE: ccode = "ng"; break; | |
4711 | default: | |
4712 | abort(); | |
4713 | } | |
4714 | ||
94a54f47 GK |
4715 | /* Maybe we have a guess as to how likely the branch is. |
4716 | The old mnemonics don't have a way to specify this information. */ | |
12a4e8c5 GK |
4717 | note = find_reg_note (insn, REG_BR_PROB, NULL_RTX); |
4718 | if (note != NULL_RTX) | |
4719 | { | |
4720 | /* PROB is the difference from 50%. */ | |
4721 | int prob = INTVAL (XEXP (note, 0)) - REG_BR_PROB_BASE / 2; | |
4722 | ||
4723 | /* For branches that are very close to 50%, assume not-taken. */ | |
4724 | if (abs (prob) > REG_BR_PROB_BASE / 20 | |
4725 | && ((prob > 0) ^ need_longbranch)) | |
4726 | pred = "+"; | |
4727 | else | |
4728 | pred = "-"; | |
4729 | } | |
4730 | else | |
4731 | pred = ""; | |
4732 | ||
4733 | if (label == NULL) | |
94a54f47 | 4734 | s += sprintf (s, "{b%sr|b%slr%s} ", ccode, ccode, pred); |
12a4e8c5 | 4735 | else |
94a54f47 | 4736 | s += sprintf (s, "{b%s|b%s%s} ", ccode, ccode, pred); |
12a4e8c5 | 4737 | |
37c67319 GK |
4738 | /* We need to escape any '%' characters in the reg_names string. |
4739 | Assume they'd only be the first character... */ | |
4740 | if (reg_names[cc_regno + CR0_REGNO][0] == '%') | |
4741 | *s++ = '%'; | |
94a54f47 | 4742 | s += sprintf (s, "%s", reg_names[cc_regno + CR0_REGNO]); |
12a4e8c5 GK |
4743 | |
4744 | if (label != NULL) | |
4745 | { | |
4746 | /* If the branch distance was too far, we may have to use an | |
4747 | unconditional branch to go the distance. */ | |
4748 | if (need_longbranch) | |
33011c35 | 4749 | s += sprintf (s, ",%c$+8\n\tb %s", '%', label); |
12a4e8c5 GK |
4750 | else |
4751 | s += sprintf (s, ",%s", label); | |
4752 | } | |
4753 | ||
4754 | return string; | |
4755 | } | |
50a0b056 GK |
4756 | |
4757 | /* Emit a conditional move: move TRUE_COND to DEST if OP of the | |
4758 | operands of the last comparison is nonzero/true, FALSE_COND if it | |
4759 | is zero/false. Return 0 if the hardware has no such operation. */ | |
4760 | int | |
4761 | rs6000_emit_cmove (dest, op, true_cond, false_cond) | |
4762 | rtx dest; | |
4763 | rtx op; | |
4764 | rtx true_cond; | |
4765 | rtx false_cond; | |
4766 | { | |
4767 | enum rtx_code code = GET_CODE (op); | |
4768 | rtx op0 = rs6000_compare_op0; | |
4769 | rtx op1 = rs6000_compare_op1; | |
4770 | REAL_VALUE_TYPE c1; | |
4771 | enum machine_mode mode = GET_MODE (op0); | |
4772 | rtx temp; | |
4773 | ||
4774 | /* First, work out if the hardware can do this at all, or | |
4775 | if it's too slow... */ | |
4776 | /* If the comparison is an integer one, since we only have fsel | |
4777 | it'll be cheaper to use a branch. */ | |
4778 | if (! rs6000_compare_fp_p) | |
4779 | return 0; | |
4780 | ||
4781 | /* Eliminate half of the comparisons by switching operands, this | |
4782 | makes the remaining code simpler. */ | |
4783 | if (code == UNLT || code == UNGT || code == UNORDERED || code == NE | |
4784 | || code == LTGT || code == LT) | |
4785 | { | |
4786 | code = reverse_condition_maybe_unordered (code); | |
4787 | temp = true_cond; | |
4788 | true_cond = false_cond; | |
4789 | false_cond = temp; | |
4790 | } | |
4791 | ||
4792 | /* UNEQ and LTGT take four instructions for a comparison with zero, | |
4793 | it'll probably be faster to use a branch here too. */ | |
4794 | if (code == UNEQ) | |
4795 | return 0; | |
4796 | ||
4797 | if (GET_CODE (op1) == CONST_DOUBLE) | |
4798 | REAL_VALUE_FROM_CONST_DOUBLE (c1, op1); | |
4799 | ||
4800 | /* We're going to try to implement comparions by performing | |
4801 | a subtract, then comparing against zero. Unfortunately, | |
4802 | Inf - Inf is NaN which is not zero, and so if we don't | |
4803 | know that the the operand is finite and the comparison | |
4804 | would treat EQ different to UNORDERED, we can't do it. */ | |
4805 | if (! flag_unsafe_math_optimizations | |
4806 | && code != GT && code != UNGE | |
4807 | && (GET_CODE (op1) != CONST_DOUBLE || target_isinf (c1)) | |
4808 | /* Constructs of the form (a OP b ? a : b) are safe. */ | |
4809 | && ((! rtx_equal_p (op0, false_cond) && ! rtx_equal_p (op1, false_cond)) | |
4810 | || (! rtx_equal_p (op0, true_cond) | |
4811 | && ! rtx_equal_p (op1, true_cond)))) | |
4812 | return 0; | |
4813 | /* At this point we know we can use fsel. */ | |
4814 | ||
4815 | /* Reduce the comparison to a comparison against zero. */ | |
4816 | temp = gen_reg_rtx (mode); | |
4817 | emit_insn (gen_rtx_SET (VOIDmode, temp, | |
4818 | gen_rtx_MINUS (mode, op0, op1))); | |
4819 | op0 = temp; | |
4820 | op1 = CONST0_RTX (mode); | |
4821 | ||
4822 | /* If we don't care about NaNs we can reduce some of the comparisons | |
4823 | down to faster ones. */ | |
4824 | if (flag_unsafe_math_optimizations) | |
4825 | switch (code) | |
4826 | { | |
4827 | case GT: | |
4828 | code = LE; | |
4829 | temp = true_cond; | |
4830 | true_cond = false_cond; | |
4831 | false_cond = temp; | |
4832 | break; | |
4833 | case UNGE: | |
4834 | code = GE; | |
4835 | break; | |
4836 | case UNEQ: | |
4837 | code = EQ; | |
4838 | break; | |
4839 | default: | |
4840 | break; | |
4841 | } | |
4842 | ||
4843 | /* Now, reduce everything down to a GE. */ | |
4844 | switch (code) | |
4845 | { | |
4846 | case GE: | |
4847 | break; | |
4848 | ||
4849 | case LE: | |
4850 | temp = gen_reg_rtx (mode); | |
4851 | emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (mode, op0))); | |
4852 | op0 = temp; | |
4853 | break; | |
4854 | ||
4855 | case ORDERED: | |
4856 | temp = gen_reg_rtx (mode); | |
4857 | emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_ABS (mode, op0))); | |
4858 | op0 = temp; | |
4859 | break; | |
4860 | ||
4861 | case EQ: | |
4862 | temp = gen_reg_rtx (mode); | |
4863 | emit_insn (gen_rtx_SET (VOIDmode, temp, | |
4864 | gen_rtx_NEG (mode, | |
4865 | gen_rtx_ABS (mode, op0)))); | |
4866 | op0 = temp; | |
4867 | break; | |
4868 | ||
4869 | case UNGE: | |
4870 | temp = gen_reg_rtx (mode); | |
4871 | emit_insn (gen_rtx_SET (VOIDmode, temp, | |
4872 | gen_rtx_IF_THEN_ELSE (mode, | |
4873 | gen_rtx_GE (VOIDmode, | |
4874 | op0, op1), | |
4875 | true_cond, false_cond))); | |
4876 | false_cond = temp; | |
4877 | true_cond = false_cond; | |
4878 | ||
4879 | temp = gen_reg_rtx (mode); | |
4880 | emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (mode, op0))); | |
4881 | op0 = temp; | |
4882 | break; | |
4883 | ||
4884 | case GT: | |
4885 | temp = gen_reg_rtx (mode); | |
4886 | emit_insn (gen_rtx_SET (VOIDmode, temp, | |
4887 | gen_rtx_IF_THEN_ELSE (mode, | |
4888 | gen_rtx_GE (VOIDmode, | |
4889 | op0, op1), | |
4890 | true_cond, false_cond))); | |
4891 | true_cond = temp; | |
4892 | false_cond = true_cond; | |
4893 | ||
4894 | temp = gen_reg_rtx (mode); | |
4895 | emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (mode, op0))); | |
4896 | op0 = temp; | |
4897 | break; | |
4898 | ||
4899 | default: | |
4900 | abort (); | |
4901 | } | |
4902 | ||
4903 | emit_insn (gen_rtx_SET (VOIDmode, dest, | |
4904 | gen_rtx_IF_THEN_ELSE (mode, | |
4905 | gen_rtx_GE (VOIDmode, | |
4906 | op0, op1), | |
4907 | true_cond, false_cond))); | |
4908 | return 1; | |
4909 | } | |
4910 | ||
4911 | void | |
4912 | rs6000_emit_minmax (dest, code, op0, op1) | |
4913 | rtx dest; | |
4914 | enum rtx_code code; | |
4915 | rtx op0; | |
4916 | rtx op1; | |
4917 | { | |
4918 | enum machine_mode mode = GET_MODE (op0); | |
4919 | rtx target; | |
4920 | if (code == SMAX || code == UMAX) | |
4921 | target = emit_conditional_move (dest, GE, op0, op1, mode, | |
4922 | op0, op1, mode, 0); | |
4923 | else | |
4924 | target = emit_conditional_move (dest, GE, op0, op1, mode, | |
4925 | op1, op0, mode, 0); | |
4926 | if (target == NULL_RTX) | |
4927 | abort (); | |
4928 | if (target != dest) | |
4929 | emit_move_insn (dest, target); | |
4930 | } | |
12a4e8c5 | 4931 | \f |
9878760c RK |
4932 | /* This page contains routines that are used to determine what the function |
4933 | prologue and epilogue code will do and write them out. */ | |
4934 | ||
4935 | /* Return the first fixed-point register that is required to be saved. 32 if | |
4936 | none. */ | |
4937 | ||
4938 | int | |
4939 | first_reg_to_save () | |
4940 | { | |
4941 | int first_reg; | |
4942 | ||
4943 | /* Find lowest numbered live register. */ | |
4944 | for (first_reg = 13; first_reg <= 31; first_reg++) | |
a38d360d GK |
4945 | if (regs_ever_live[first_reg] |
4946 | && (! call_used_regs[first_reg] | |
4947 | || (first_reg == PIC_OFFSET_TABLE_REGNUM | |
ee890fe2 SS |
4948 | && (((DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) |
4949 | && flag_pic == 1) | |
4950 | || (DEFAULT_ABI == ABI_DARWIN | |
4951 | && flag_pic))))) | |
9878760c RK |
4952 | break; |
4953 | ||
b5253831 DE |
4954 | if (profile_flag) |
4955 | { | |
4956 | /* AIX must save/restore every register that contains a parameter | |
4957 | before/after the .__mcount call plus an additional register | |
4958 | for the static chain, if needed; use registers from 30 down to 22 | |
4959 | to do this. */ | |
ee890fe2 | 4960 | if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) |
b5253831 DE |
4961 | { |
4962 | int last_parm_reg, profile_first_reg; | |
4963 | ||
4964 | /* Figure out last used parameter register. The proper thing | |
4965 | to do is to walk incoming args of the function. A function | |
4966 | might have live parameter registers even if it has no | |
4967 | incoming args. */ | |
4968 | for (last_parm_reg = 10; | |
4969 | last_parm_reg > 2 && ! regs_ever_live [last_parm_reg]; | |
4970 | last_parm_reg--) | |
4971 | ; | |
4972 | ||
4973 | /* Calculate first reg for saving parameter registers | |
4974 | and static chain. | |
4975 | Skip reg 31 which may contain the frame pointer. */ | |
4976 | profile_first_reg = (33 - last_parm_reg | |
4977 | - (current_function_needs_context ? 1 : 0)); | |
ee890fe2 SS |
4978 | #if TARGET_MACHO |
4979 | /* Need to skip another reg to account for R31 being PICBASE | |
4980 | (when flag_pic is set) or R30 being used as the frame | |
4981 | pointer (when flag_pic is not set). */ | |
4982 | --profile_first_reg; | |
4983 | #endif | |
b5253831 DE |
4984 | /* Do not save frame pointer if no parameters needs to be saved. */ |
4985 | if (profile_first_reg == 31) | |
4986 | profile_first_reg = 32; | |
4987 | ||
4988 | if (first_reg > profile_first_reg) | |
4989 | first_reg = profile_first_reg; | |
4990 | } | |
e165f3f0 | 4991 | |
b5253831 DE |
4992 | /* SVR4 may need one register to preserve the static chain. */ |
4993 | else if (current_function_needs_context) | |
4994 | { | |
4995 | /* Skip reg 31 which may contain the frame pointer. */ | |
4996 | if (first_reg > 30) | |
4997 | first_reg = 30; | |
4998 | } | |
4999 | } | |
e165f3f0 | 5000 | |
ee890fe2 SS |
5001 | #if TARGET_MACHO |
5002 | if (flag_pic && current_function_uses_pic_offset_table && | |
5003 | (first_reg > PIC_OFFSET_TABLE_REGNUM)) | |
5004 | return PIC_OFFSET_TABLE_REGNUM; | |
5005 | #endif | |
5006 | ||
9878760c RK |
5007 | return first_reg; |
5008 | } | |
5009 | ||
5010 | /* Similar, for FP regs. */ | |
5011 | ||
5012 | int | |
5013 | first_fp_reg_to_save () | |
5014 | { | |
5015 | int first_reg; | |
5016 | ||
5017 | /* Find lowest numbered live register. */ | |
5018 | for (first_reg = 14 + 32; first_reg <= 63; first_reg++) | |
5019 | if (regs_ever_live[first_reg]) | |
5020 | break; | |
5021 | ||
5022 | return first_reg; | |
5023 | } | |
4697a36c MM |
5024 | \f |
5025 | /* Calculate the stack information for the current function. This is | |
5026 | complicated by having two separate calling sequences, the AIX calling | |
5027 | sequence and the V.4 calling sequence. | |
5028 | ||
ee890fe2 | 5029 | AIX (and Darwin/Mac OS) stack frames look like: |
a260abc9 | 5030 | 32-bit 64-bit |
4697a36c | 5031 | SP----> +---------------------------------------+ |
a260abc9 | 5032 | | back chain to caller | 0 0 |
4697a36c | 5033 | +---------------------------------------+ |
a260abc9 | 5034 | | saved CR | 4 8 (8-11) |
4697a36c | 5035 | +---------------------------------------+ |
a260abc9 | 5036 | | saved LR | 8 16 |
4697a36c | 5037 | +---------------------------------------+ |
a260abc9 | 5038 | | reserved for compilers | 12 24 |
4697a36c | 5039 | +---------------------------------------+ |
a260abc9 | 5040 | | reserved for binders | 16 32 |
4697a36c | 5041 | +---------------------------------------+ |
a260abc9 | 5042 | | saved TOC pointer | 20 40 |
4697a36c | 5043 | +---------------------------------------+ |
a260abc9 | 5044 | | Parameter save area (P) | 24 48 |
4697a36c | 5045 | +---------------------------------------+ |
a260abc9 | 5046 | | Alloca space (A) | 24+P etc. |
802a0058 | 5047 | +---------------------------------------+ |
a7df97e6 | 5048 | | Local variable space (L) | 24+P+A |
4697a36c | 5049 | +---------------------------------------+ |
a7df97e6 | 5050 | | Float/int conversion temporary (X) | 24+P+A+L |
4697a36c | 5051 | +---------------------------------------+ |
a7df97e6 | 5052 | | Save area for GP registers (G) | 24+P+A+X+L |
4697a36c | 5053 | +---------------------------------------+ |
a7df97e6 | 5054 | | Save area for FP registers (F) | 24+P+A+X+L+G |
4697a36c MM |
5055 | +---------------------------------------+ |
5056 | old SP->| back chain to caller's caller | | |
5057 | +---------------------------------------+ | |
5058 | ||
5376a30c KR |
5059 | The required alignment for AIX configurations is two words (i.e., 8 |
5060 | or 16 bytes). | |
5061 | ||
5062 | ||
4697a36c MM |
5063 | V.4 stack frames look like: |
5064 | ||
5065 | SP----> +---------------------------------------+ | |
5066 | | back chain to caller | 0 | |
5067 | +---------------------------------------+ | |
5eb387b8 | 5068 | | caller's saved LR | 4 |
4697a36c MM |
5069 | +---------------------------------------+ |
5070 | | Parameter save area (P) | 8 | |
5071 | +---------------------------------------+ | |
a7df97e6 MM |
5072 | | Alloca space (A) | 8+P |
5073 | +---------------------------------------+ | |
5074 | | Varargs save area (V) | 8+P+A | |
5075 | +---------------------------------------+ | |
5076 | | Local variable space (L) | 8+P+A+V | |
5077 | +---------------------------------------+ | |
5078 | | Float/int conversion temporary (X) | 8+P+A+V+L | |
4697a36c | 5079 | +---------------------------------------+ |
a7df97e6 MM |
5080 | | saved CR (C) | 8+P+A+V+L+X |
5081 | +---------------------------------------+ | |
5082 | | Save area for GP registers (G) | 8+P+A+V+L+X+C | |
5083 | +---------------------------------------+ | |
5084 | | Save area for FP registers (F) | 8+P+A+V+L+X+C+G | |
4697a36c MM |
5085 | +---------------------------------------+ |
5086 | old SP->| back chain to caller's caller | | |
5087 | +---------------------------------------+ | |
b6c9286a | 5088 | |
5376a30c KR |
5089 | The required alignment for V.4 is 16 bytes, or 8 bytes if -meabi is |
5090 | given. (But note below and in sysv4.h that we require only 8 and | |
5091 | may round up the size of our stack frame anyways. The historical | |
5092 | reason is early versions of powerpc-linux which didn't properly | |
5093 | align the stack at program startup. A happy side-effect is that | |
5094 | -mno-eabi libraries can be used with -meabi programs.) | |
5095 | ||
b6c9286a | 5096 | |
5376a30c KR |
5097 | The EABI configuration defaults to the V.4 layout, unless |
5098 | -mcall-aix is used, in which case the AIX layout is used. However, | |
5099 | the stack alignment requirements may differ. If -mno-eabi is not | |
5100 | given, the required stack alignment is 8 bytes; if -mno-eabi is | |
5101 | given, the required alignment is 16 bytes. (But see V.4 comment | |
5102 | above.) */ | |
4697a36c | 5103 | |
61b2fbe7 MM |
5104 | #ifndef ABI_STACK_BOUNDARY |
5105 | #define ABI_STACK_BOUNDARY STACK_BOUNDARY | |
5106 | #endif | |
5107 | ||
4697a36c MM |
5108 | rs6000_stack_t * |
5109 | rs6000_stack_info () | |
5110 | { | |
5111 | static rs6000_stack_t info, zero_info; | |
5112 | rs6000_stack_t *info_ptr = &info; | |
9ebbca7d | 5113 | int reg_size = TARGET_POWERPC64 ? 8 : 4; |
24d304eb | 5114 | enum rs6000_abi abi; |
83720594 | 5115 | int ehrd_size; |
b6c9286a | 5116 | int total_raw_size; |
4697a36c MM |
5117 | |
5118 | /* Zero all fields portably */ | |
5119 | info = zero_info; | |
5120 | ||
5121 | /* Select which calling sequence */ | |
b6c9286a | 5122 | info_ptr->abi = abi = DEFAULT_ABI; |
9878760c | 5123 | |
4697a36c MM |
5124 | /* Calculate which registers need to be saved & save area size */ |
5125 | info_ptr->first_gp_reg_save = first_reg_to_save (); | |
906fb125 GK |
5126 | /* Assume that we will have to save PIC_OFFSET_TABLE_REGNUM, |
5127 | even if it currently looks like we won't. */ | |
ee890fe2 SS |
5128 | if (((flag_pic == 1 |
5129 | && (abi == ABI_V4 || abi == ABI_SOLARIS)) | |
5130 | || (flag_pic && | |
5131 | abi == ABI_DARWIN)) | |
906fb125 GK |
5132 | && info_ptr->first_gp_reg_save > PIC_OFFSET_TABLE_REGNUM) |
5133 | info_ptr->gp_size = reg_size * (32 - PIC_OFFSET_TABLE_REGNUM); | |
5134 | else | |
5135 | info_ptr->gp_size = reg_size * (32 - info_ptr->first_gp_reg_save); | |
4697a36c MM |
5136 | |
5137 | info_ptr->first_fp_reg_save = first_fp_reg_to_save (); | |
5138 | info_ptr->fp_size = 8 * (64 - info_ptr->first_fp_reg_save); | |
5139 | ||
5140 | /* Does this function call anything? */ | |
71f123ca FS |
5141 | info_ptr->calls_p = (! current_function_is_leaf |
5142 | || cfun->machine->ra_needs_full_frame); | |
b6c9286a | 5143 | |
4697a36c | 5144 | /* Determine if we need to save the link register */ |
71f123ca | 5145 | if (rs6000_ra_ever_killed () |
38c1f2d7 | 5146 | || (DEFAULT_ABI == ABI_AIX && profile_flag) |
4697a36c MM |
5147 | #ifdef TARGET_RELOCATABLE |
5148 | || (TARGET_RELOCATABLE && (get_pool_size () != 0)) | |
5149 | #endif | |
5150 | || (info_ptr->first_fp_reg_save != 64 | |
5151 | && !FP_SAVE_INLINE (info_ptr->first_fp_reg_save)) | |
24d304eb | 5152 | || (abi == ABI_V4 && current_function_calls_alloca) |
c81bebd7 | 5153 | || (abi == ABI_SOLARIS && current_function_calls_alloca) |
ee890fe2 | 5154 | || (DEFAULT_ABI == ABI_DARWIN && flag_pic && current_function_uses_pic_offset_table) |
4697a36c MM |
5155 | || info_ptr->calls_p) |
5156 | { | |
5157 | info_ptr->lr_save_p = 1; | |
9ebbca7d | 5158 | regs_ever_live[LINK_REGISTER_REGNUM] = 1; |
4697a36c MM |
5159 | } |
5160 | ||
9ebbca7d GK |
5161 | /* Determine if we need to save the condition code registers. */ |
5162 | if (regs_ever_live[CR2_REGNO] | |
5163 | || regs_ever_live[CR3_REGNO] | |
5164 | || regs_ever_live[CR4_REGNO]) | |
4697a36c MM |
5165 | { |
5166 | info_ptr->cr_save_p = 1; | |
9ebbca7d | 5167 | if (abi == ABI_V4 || abi == ABI_SOLARIS) |
4697a36c MM |
5168 | info_ptr->cr_size = reg_size; |
5169 | } | |
5170 | ||
83720594 RH |
5171 | /* If the current function calls __builtin_eh_return, then we need |
5172 | to allocate stack space for registers that will hold data for | |
5173 | the exception handler. */ | |
5174 | if (current_function_calls_eh_return) | |
5175 | { | |
5176 | unsigned int i; | |
5177 | for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; ++i) | |
5178 | continue; | |
5179 | ehrd_size = i * UNITS_PER_WORD; | |
5180 | } | |
5181 | else | |
5182 | ehrd_size = 0; | |
5183 | ||
4697a36c MM |
5184 | /* Determine various sizes */ |
5185 | info_ptr->reg_size = reg_size; | |
5186 | info_ptr->fixed_size = RS6000_SAVE_AREA; | |
5187 | info_ptr->varargs_size = RS6000_VARARGS_AREA; | |
189e03e3 DE |
5188 | info_ptr->vars_size = RS6000_ALIGN (get_frame_size (), 8); |
5189 | info_ptr->parm_size = RS6000_ALIGN (current_function_outgoing_args_size, 8); | |
189e03e3 | 5190 | info_ptr->save_size = RS6000_ALIGN (info_ptr->fp_size |
b6c9286a | 5191 | + info_ptr->gp_size |
83720594 | 5192 | + ehrd_size |
b6c9286a MM |
5193 | + info_ptr->cr_size |
5194 | + info_ptr->lr_size | |
9ebbca7d | 5195 | + info_ptr->toc_size, 8); |
ee890fe2 SS |
5196 | if (DEFAULT_ABI == ABI_DARWIN) |
5197 | info_ptr->save_size = RS6000_ALIGN (info_ptr->save_size, 16); | |
b6c9286a | 5198 | |
4697a36c | 5199 | /* Calculate the offsets */ |
24d304eb | 5200 | switch (abi) |
4697a36c | 5201 | { |
b6c9286a | 5202 | case ABI_NONE: |
24d304eb | 5203 | default: |
b6c9286a MM |
5204 | abort (); |
5205 | ||
5206 | case ABI_AIX: | |
5207 | case ABI_AIX_NODESC: | |
ee890fe2 | 5208 | case ABI_DARWIN: |
b6c9286a MM |
5209 | info_ptr->fp_save_offset = - info_ptr->fp_size; |
5210 | info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size; | |
83720594 | 5211 | info_ptr->ehrd_offset = info_ptr->gp_save_offset - ehrd_size; |
a260abc9 DE |
5212 | info_ptr->cr_save_offset = reg_size; /* first word when 64-bit. */ |
5213 | info_ptr->lr_save_offset = 2*reg_size; | |
24d304eb RK |
5214 | break; |
5215 | ||
5216 | case ABI_V4: | |
c81bebd7 | 5217 | case ABI_SOLARIS: |
b6c9286a MM |
5218 | info_ptr->fp_save_offset = - info_ptr->fp_size; |
5219 | info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size; | |
a7df97e6 MM |
5220 | info_ptr->cr_save_offset = info_ptr->gp_save_offset - info_ptr->cr_size; |
5221 | info_ptr->toc_save_offset = info_ptr->cr_save_offset - info_ptr->toc_size; | |
83720594 | 5222 | info_ptr->ehrd_offset = info_ptr->toc_save_offset - ehrd_size; |
b6c9286a MM |
5223 | info_ptr->lr_save_offset = reg_size; |
5224 | break; | |
4697a36c MM |
5225 | } |
5226 | ||
ff381587 MM |
5227 | total_raw_size = (info_ptr->vars_size |
5228 | + info_ptr->parm_size | |
ff381587 MM |
5229 | + info_ptr->save_size |
5230 | + info_ptr->varargs_size | |
5231 | + info_ptr->fixed_size); | |
5232 | ||
5233 | info_ptr->total_size = RS6000_ALIGN (total_raw_size, ABI_STACK_BOUNDARY / BITS_PER_UNIT); | |
5234 | ||
5235 | /* Determine if we need to allocate any stack frame: | |
5236 | ||
5237 | For AIX we need to push the stack if a frame pointer is needed (because | |
5238 | the stack might be dynamically adjusted), if we are debugging, if we | |
9ebbca7d | 5239 | make calls, or if the sum of fp_save, gp_save, and local variables |
ff381587 | 5240 | are more than the space needed to save all non-volatile registers: |
bfc79d3b | 5241 | 32-bit: 18*8 + 19*4 = 220 or 64-bit: 18*8 + 18*8 = 288 (GPR13 reserved). |
ff381587 MM |
5242 | |
5243 | For V.4 we don't have the stack cushion that AIX uses, but assume that | |
5244 | the debugger can handle stackless frames. */ | |
5245 | ||
5246 | if (info_ptr->calls_p) | |
5247 | info_ptr->push_p = 1; | |
5248 | ||
9ebbca7d | 5249 | else if (abi == ABI_V4 || abi == ABI_SOLARIS) |
ff381587 | 5250 | info_ptr->push_p = (total_raw_size > info_ptr->fixed_size |
9ebbca7d | 5251 | || info_ptr->calls_p); |
ff381587 MM |
5252 | |
5253 | else | |
5254 | info_ptr->push_p = (frame_pointer_needed | |
ee890fe2 | 5255 | || (abi != ABI_DARWIN && write_symbols != NO_DEBUG) |
ff381587 | 5256 | || ((total_raw_size - info_ptr->fixed_size) |
bfc79d3b | 5257 | > (TARGET_32BIT ? 220 : 288))); |
ff381587 | 5258 | |
4697a36c | 5259 | /* Zero offsets if we're not saving those registers */ |
8dda1a21 | 5260 | if (info_ptr->fp_size == 0) |
4697a36c MM |
5261 | info_ptr->fp_save_offset = 0; |
5262 | ||
8dda1a21 | 5263 | if (info_ptr->gp_size == 0) |
4697a36c MM |
5264 | info_ptr->gp_save_offset = 0; |
5265 | ||
c81fc13e | 5266 | if (! info_ptr->lr_save_p) |
4697a36c MM |
5267 | info_ptr->lr_save_offset = 0; |
5268 | ||
c81fc13e | 5269 | if (! info_ptr->cr_save_p) |
4697a36c MM |
5270 | info_ptr->cr_save_offset = 0; |
5271 | ||
c81fc13e | 5272 | if (! info_ptr->toc_save_p) |
b6c9286a MM |
5273 | info_ptr->toc_save_offset = 0; |
5274 | ||
4697a36c MM |
5275 | return info_ptr; |
5276 | } | |
5277 | ||
5278 | void | |
5279 | debug_stack_info (info) | |
5280 | rs6000_stack_t *info; | |
9878760c | 5281 | { |
d330fd93 | 5282 | const char *abi_string; |
24d304eb | 5283 | |
c81fc13e | 5284 | if (! info) |
4697a36c MM |
5285 | info = rs6000_stack_info (); |
5286 | ||
5287 | fprintf (stderr, "\nStack information for function %s:\n", | |
5288 | ((current_function_decl && DECL_NAME (current_function_decl)) | |
5289 | ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl)) | |
5290 | : "<unknown>")); | |
5291 | ||
24d304eb RK |
5292 | switch (info->abi) |
5293 | { | |
b6c9286a MM |
5294 | default: abi_string = "Unknown"; break; |
5295 | case ABI_NONE: abi_string = "NONE"; break; | |
5296 | case ABI_AIX: abi_string = "AIX"; break; | |
5297 | case ABI_AIX_NODESC: abi_string = "AIX"; break; | |
ee890fe2 | 5298 | case ABI_DARWIN: abi_string = "Darwin"; break; |
b6c9286a | 5299 | case ABI_V4: abi_string = "V.4"; break; |
c81bebd7 | 5300 | case ABI_SOLARIS: abi_string = "Solaris"; break; |
24d304eb RK |
5301 | } |
5302 | ||
5303 | fprintf (stderr, "\tABI = %5s\n", abi_string); | |
5304 | ||
4697a36c MM |
5305 | if (info->first_gp_reg_save != 32) |
5306 | fprintf (stderr, "\tfirst_gp_reg_save = %5d\n", info->first_gp_reg_save); | |
5307 | ||
5308 | if (info->first_fp_reg_save != 64) | |
5309 | fprintf (stderr, "\tfirst_fp_reg_save = %5d\n", info->first_fp_reg_save); | |
9878760c | 5310 | |
4697a36c MM |
5311 | if (info->lr_save_p) |
5312 | fprintf (stderr, "\tlr_save_p = %5d\n", info->lr_save_p); | |
9878760c | 5313 | |
4697a36c MM |
5314 | if (info->cr_save_p) |
5315 | fprintf (stderr, "\tcr_save_p = %5d\n", info->cr_save_p); | |
5316 | ||
b6c9286a MM |
5317 | if (info->toc_save_p) |
5318 | fprintf (stderr, "\ttoc_save_p = %5d\n", info->toc_save_p); | |
5319 | ||
4697a36c MM |
5320 | if (info->push_p) |
5321 | fprintf (stderr, "\tpush_p = %5d\n", info->push_p); | |
5322 | ||
5323 | if (info->calls_p) | |
5324 | fprintf (stderr, "\tcalls_p = %5d\n", info->calls_p); | |
5325 | ||
4697a36c MM |
5326 | if (info->gp_save_offset) |
5327 | fprintf (stderr, "\tgp_save_offset = %5d\n", info->gp_save_offset); | |
5328 | ||
5329 | if (info->fp_save_offset) | |
5330 | fprintf (stderr, "\tfp_save_offset = %5d\n", info->fp_save_offset); | |
5331 | ||
5332 | if (info->lr_save_offset) | |
5333 | fprintf (stderr, "\tlr_save_offset = %5d\n", info->lr_save_offset); | |
5334 | ||
5335 | if (info->cr_save_offset) | |
5336 | fprintf (stderr, "\tcr_save_offset = %5d\n", info->cr_save_offset); | |
5337 | ||
b6c9286a MM |
5338 | if (info->toc_save_offset) |
5339 | fprintf (stderr, "\ttoc_save_offset = %5d\n", info->toc_save_offset); | |
5340 | ||
4697a36c MM |
5341 | if (info->varargs_save_offset) |
5342 | fprintf (stderr, "\tvarargs_save_offset = %5d\n", info->varargs_save_offset); | |
5343 | ||
5344 | if (info->total_size) | |
5345 | fprintf (stderr, "\ttotal_size = %5d\n", info->total_size); | |
5346 | ||
5347 | if (info->varargs_size) | |
5348 | fprintf (stderr, "\tvarargs_size = %5d\n", info->varargs_size); | |
5349 | ||
5350 | if (info->vars_size) | |
5351 | fprintf (stderr, "\tvars_size = %5d\n", info->vars_size); | |
5352 | ||
5353 | if (info->parm_size) | |
5354 | fprintf (stderr, "\tparm_size = %5d\n", info->parm_size); | |
5355 | ||
5356 | if (info->fixed_size) | |
5357 | fprintf (stderr, "\tfixed_size = %5d\n", info->fixed_size); | |
5358 | ||
5359 | if (info->gp_size) | |
5360 | fprintf (stderr, "\tgp_size = %5d\n", info->gp_size); | |
5361 | ||
5362 | if (info->fp_size) | |
5363 | fprintf (stderr, "\tfp_size = %5d\n", info->fp_size); | |
5364 | ||
b6c9286a MM |
5365 | if (info->lr_size) |
5366 | fprintf (stderr, "\tlr_size = %5d\n", info->cr_size); | |
5367 | ||
4697a36c MM |
5368 | if (info->cr_size) |
5369 | fprintf (stderr, "\tcr_size = %5d\n", info->cr_size); | |
5370 | ||
b6c9286a MM |
5371 | if (info->toc_size) |
5372 | fprintf (stderr, "\ttoc_size = %5d\n", info->toc_size); | |
5373 | ||
4697a36c MM |
5374 | if (info->save_size) |
5375 | fprintf (stderr, "\tsave_size = %5d\n", info->save_size); | |
5376 | ||
5377 | if (info->reg_size != 4) | |
5378 | fprintf (stderr, "\treg_size = %5d\n", info->reg_size); | |
5379 | ||
5380 | fprintf (stderr, "\n"); | |
9878760c | 5381 | } |
71f123ca FS |
5382 | |
5383 | rtx | |
5384 | rs6000_return_addr (count, frame) | |
5385 | int count; | |
5386 | rtx frame; | |
5387 | { | |
71f123ca FS |
5388 | /* Currently we don't optimize very well between prolog and body code and |
5389 | for PIC code the code can be actually quite bad, so don't try to be | |
5390 | too clever here. */ | |
3418dd3a FS |
5391 | if (count != 0 |
5392 | || flag_pic != 0 | |
5393 | || DEFAULT_ABI == ABI_AIX | |
5394 | || DEFAULT_ABI == ABI_AIX_NODESC) | |
71f123ca FS |
5395 | { |
5396 | cfun->machine->ra_needs_full_frame = 1; | |
5397 | return | |
5398 | gen_rtx_MEM (Pmode, | |
3418dd3a | 5399 | memory_address (Pmode, |
71f123ca FS |
5400 | plus_constant (copy_to_reg (gen_rtx_MEM (Pmode, |
5401 | memory_address (Pmode, frame))), | |
5402 | RETURN_ADDRESS_OFFSET))); | |
5403 | } | |
5404 | ||
9e2f7ec7 | 5405 | return get_hard_reg_initial_val (Pmode, LINK_REGISTER_REGNUM); |
71f123ca FS |
5406 | } |
5407 | ||
5408 | static int | |
5409 | rs6000_ra_ever_killed () | |
5410 | { | |
5411 | rtx top; | |
5412 | ||
5413 | #ifdef ASM_OUTPUT_MI_THUNK | |
5414 | if (current_function_is_thunk) | |
5415 | return 0; | |
5416 | #endif | |
9e2f7ec7 DD |
5417 | if (!has_hard_reg_initial_val (Pmode, LINK_REGISTER_REGNUM) |
5418 | || cfun->machine->ra_needs_full_frame) | |
71f123ca FS |
5419 | return regs_ever_live[LINK_REGISTER_REGNUM]; |
5420 | ||
5421 | push_topmost_sequence (); | |
5422 | top = get_insns (); | |
5423 | pop_topmost_sequence (); | |
5424 | ||
5425 | return reg_set_between_p (gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM), | |
5426 | top, NULL_RTX); | |
5427 | } | |
4697a36c | 5428 | \f |
8cd8f856 GK |
5429 | /* Add a REG_MAYBE_DEAD note to the insn. */ |
5430 | static void | |
5431 | rs6000_maybe_dead (insn) | |
5432 | rtx insn; | |
5433 | { | |
5434 | REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD, | |
5435 | const0_rtx, | |
5436 | REG_NOTES (insn)); | |
5437 | } | |
5438 | ||
9ebbca7d | 5439 | /* Emit instructions needed to load the TOC register. |
c7ca610e | 5440 | This is only needed when TARGET_TOC, TARGET_MINIMAL_TOC, and there is |
9ebbca7d | 5441 | a constant pool; or for SVR4 -fpic. */ |
c7ca610e RK |
5442 | |
5443 | void | |
9ebbca7d GK |
5444 | rs6000_emit_load_toc_table (fromprolog) |
5445 | int fromprolog; | |
c7ca610e | 5446 | { |
9ebbca7d GK |
5447 | rtx dest; |
5448 | dest = gen_rtx_REG (Pmode, PIC_OFFSET_TABLE_REGNUM); | |
c7ca610e | 5449 | |
9ebbca7d | 5450 | if (TARGET_ELF) |
c7ca610e | 5451 | { |
9ebbca7d GK |
5452 | if ((DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) |
5453 | && flag_pic == 1) | |
38c1f2d7 | 5454 | { |
9ebbca7d GK |
5455 | rtx temp = (fromprolog |
5456 | ? gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM) | |
5457 | : gen_reg_rtx (Pmode)); | |
5458 | if (TARGET_32BIT) | |
8cd8f856 | 5459 | rs6000_maybe_dead (emit_insn (gen_load_toc_v4_pic_si (temp))); |
9ebbca7d | 5460 | else |
8cd8f856 GK |
5461 | rs6000_maybe_dead (emit_insn (gen_load_toc_v4_pic_di (temp))); |
5462 | rs6000_maybe_dead (emit_move_insn (dest, temp)); | |
38c1f2d7 | 5463 | } |
9ebbca7d GK |
5464 | else if (flag_pic == 2) |
5465 | { | |
5466 | char buf[30]; | |
5467 | rtx tempLR = (fromprolog | |
5468 | ? gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM) | |
5469 | : gen_reg_rtx (Pmode)); | |
5470 | rtx temp0 = (fromprolog | |
5471 | ? gen_rtx_REG (Pmode, 0) | |
5472 | : gen_reg_rtx (Pmode)); | |
5473 | rtx symF; | |
5474 | ||
5475 | /* possibly create the toc section */ | |
5476 | if (! toc_initialized) | |
5477 | { | |
5478 | toc_section (); | |
5479 | function_section (current_function_decl); | |
5480 | } | |
5481 | ||
5482 | if (fromprolog) | |
5483 | { | |
5484 | rtx symL; | |
5485 | ||
5486 | ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno); | |
a8a05998 | 5487 | symF = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); |
38c1f2d7 | 5488 | |
9ebbca7d | 5489 | ASM_GENERATE_INTERNAL_LABEL (buf, "LCL", rs6000_pic_labelno); |
a8a05998 | 5490 | symL = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); |
38c1f2d7 | 5491 | |
8cd8f856 GK |
5492 | rs6000_maybe_dead (emit_insn (gen_load_toc_v4_PIC_1 (tempLR, |
5493 | symF))); | |
5494 | rs6000_maybe_dead (emit_move_insn (dest, tempLR)); | |
5495 | rs6000_maybe_dead (emit_insn (gen_load_toc_v4_PIC_2 (temp0, dest, | |
5496 | symL, | |
5497 | symF))); | |
9ebbca7d GK |
5498 | } |
5499 | else | |
5500 | { | |
5501 | rtx tocsym; | |
5502 | static int reload_toc_labelno = 0; | |
5503 | ||
a8a05998 | 5504 | tocsym = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (toc_label_name)); |
38c1f2d7 | 5505 | |
9ebbca7d | 5506 | ASM_GENERATE_INTERNAL_LABEL (buf, "LCG", reload_toc_labelno++); |
a8a05998 | 5507 | symF = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); |
9ebbca7d | 5508 | |
8cd8f856 GK |
5509 | rs6000_maybe_dead (emit_insn (gen_load_toc_v4_PIC_1b (tempLR, |
5510 | symF, | |
5511 | tocsym))); | |
5512 | rs6000_maybe_dead (emit_move_insn (dest, tempLR)); | |
5513 | rs6000_maybe_dead (emit_move_insn (temp0, | |
5514 | gen_rtx_MEM (Pmode, dest))); | |
9ebbca7d | 5515 | } |
8cd8f856 | 5516 | rs6000_maybe_dead (emit_insn (gen_addsi3 (dest, temp0, dest))); |
9ebbca7d GK |
5517 | } |
5518 | else if (flag_pic == 0 && TARGET_MINIMAL_TOC) | |
5519 | { | |
5520 | /* This is for AIX code running in non-PIC ELF. */ | |
5521 | char buf[30]; | |
5522 | rtx realsym; | |
38c1f2d7 | 5523 | ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1); |
a8a05998 | 5524 | realsym = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); |
9ebbca7d | 5525 | |
8cd8f856 GK |
5526 | rs6000_maybe_dead (emit_insn (gen_elf_high (dest, realsym))); |
5527 | rs6000_maybe_dead (emit_insn (gen_elf_low (dest, dest, realsym))); | |
9ebbca7d GK |
5528 | } |
5529 | else | |
5530 | abort(); | |
5531 | } | |
5532 | else | |
5533 | { | |
5534 | if (TARGET_32BIT) | |
8cd8f856 | 5535 | rs6000_maybe_dead (emit_insn (gen_load_toc_aix_si (dest))); |
9ebbca7d | 5536 | else |
8cd8f856 | 5537 | rs6000_maybe_dead (emit_insn (gen_load_toc_aix_di (dest))); |
9ebbca7d GK |
5538 | } |
5539 | } | |
5540 | ||
5541 | int | |
5542 | get_TOC_alias_set () | |
5543 | { | |
5544 | static int set = -1; | |
5545 | if (set == -1) | |
5546 | set = new_alias_set (); | |
5547 | return set; | |
5548 | } | |
5549 | ||
5550 | /* This retuns nonzero if the current function uses the TOC. This is | |
5551 | determined by the presence of (unspec ... 7), which is generated by | |
5552 | the various load_toc_* patterns. */ | |
5553 | int | |
5554 | uses_TOC () | |
5555 | { | |
5556 | rtx insn; | |
38c1f2d7 | 5557 | |
9ebbca7d | 5558 | for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) |
2c3c49de | 5559 | if (INSN_P (insn)) |
9ebbca7d GK |
5560 | { |
5561 | rtx pat = PATTERN (insn); | |
5562 | int i; | |
5563 | ||
8cd8f856 | 5564 | if (GET_CODE (pat) == PARALLEL) |
9ebbca7d GK |
5565 | for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++) |
5566 | if (GET_CODE (XVECEXP (PATTERN (insn), 0, i)) == UNSPEC | |
5567 | && XINT (XVECEXP (PATTERN (insn), 0, i), 1) == 7) | |
5568 | return 1; | |
38c1f2d7 | 5569 | } |
9ebbca7d GK |
5570 | return 0; |
5571 | } | |
38c1f2d7 | 5572 | |
9ebbca7d GK |
5573 | rtx |
5574 | create_TOC_reference(symbol) | |
5575 | rtx symbol; | |
5576 | { | |
a8a05998 ZW |
5577 | return gen_rtx_PLUS (Pmode, |
5578 | gen_rtx_REG (Pmode, TOC_REGISTER), | |
5579 | gen_rtx_CONST (Pmode, | |
5580 | gen_rtx_MINUS (Pmode, symbol, | |
5581 | gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (toc_label_name))))); | |
9ebbca7d | 5582 | } |
38c1f2d7 | 5583 | |
9ebbca7d GK |
5584 | #if TARGET_AIX |
5585 | /* __throw will restore its own return address to be the same as the | |
5586 | return address of the function that the throw is being made to. | |
5587 | This is unfortunate, because we want to check the original | |
5588 | return address to see if we need to restore the TOC. | |
5589 | So we have to squirrel it away here. | |
5590 | This is used only in compiling __throw and __rethrow. | |
c7ca610e | 5591 | |
9ebbca7d GK |
5592 | Most of this code should be removed by CSE. */ |
5593 | static rtx insn_after_throw; | |
c7ca610e | 5594 | |
9ebbca7d GK |
5595 | /* This does the saving... */ |
5596 | void | |
5597 | rs6000_aix_emit_builtin_unwind_init () | |
5598 | { | |
5599 | rtx mem; | |
5600 | rtx stack_top = gen_reg_rtx (Pmode); | |
5601 | rtx opcode_addr = gen_reg_rtx (Pmode); | |
5602 | ||
5603 | insn_after_throw = gen_reg_rtx (SImode); | |
5604 | ||
5605 | mem = gen_rtx_MEM (Pmode, hard_frame_pointer_rtx); | |
5606 | emit_move_insn (stack_top, mem); | |
5607 | ||
5608 | mem = gen_rtx_MEM (Pmode, | |
5609 | gen_rtx_PLUS (Pmode, stack_top, | |
5610 | GEN_INT (2 * GET_MODE_SIZE (Pmode)))); | |
5611 | emit_move_insn (opcode_addr, mem); | |
5612 | emit_move_insn (insn_after_throw, gen_rtx_MEM (SImode, opcode_addr)); | |
c7ca610e RK |
5613 | } |
5614 | ||
9ebbca7d GK |
5615 | /* Emit insns to _restore_ the TOC register, at runtime (specifically in _eh.o). |
5616 | Only used on AIX. | |
5617 | ||
5618 | The idea is that on AIX, function calls look like this: | |
5619 | bl somefunction-trampoline | |
5620 | lwz r2,20(sp) | |
5621 | ||
5622 | and later, | |
5623 | somefunction-trampoline: | |
5624 | stw r2,20(sp) | |
5625 | ... load function address in the count register ... | |
5626 | bctr | |
5627 | or like this, if the linker determines that this is not a cross-module call | |
5628 | and so the TOC need not be restored: | |
5629 | bl somefunction | |
5630 | nop | |
5631 | or like this, if the compiler could determine that this is not a | |
5632 | cross-module call: | |
5633 | bl somefunction | |
5634 | now, the tricky bit here is that register 2 is saved and restored | |
5635 | by the _linker_, so we can't readily generate debugging information | |
5636 | for it. So we need to go back up the call chain looking at the | |
5637 | insns at return addresses to see which calls saved the TOC register | |
5638 | and so see where it gets restored from. | |
5639 | ||
5640 | Oh, and all this gets done in RTL inside the eh_epilogue pattern, | |
5641 | just before the actual epilogue. | |
5642 | ||
5643 | On the bright side, this incurs no space or time overhead unless an | |
5644 | exception is thrown, except for the extra code in libgcc.a. | |
5645 | ||
5646 | The parameter STACKSIZE is a register containing (at runtime) | |
5647 | the amount to be popped off the stack in addition to the stack frame | |
5648 | of this routine (which will be __throw or __rethrow, and so is | |
5649 | guaranteed to have a stack frame). */ | |
5650 | void | |
5651 | rs6000_emit_eh_toc_restore (stacksize) | |
5652 | rtx stacksize; | |
5653 | { | |
5654 | rtx top_of_stack; | |
5655 | rtx bottom_of_stack = gen_reg_rtx (Pmode); | |
5656 | rtx tocompare = gen_reg_rtx (SImode); | |
5657 | rtx opcode = gen_reg_rtx (SImode); | |
5658 | rtx opcode_addr = gen_reg_rtx (Pmode); | |
5659 | rtx mem; | |
5660 | rtx loop_start = gen_label_rtx (); | |
5661 | rtx no_toc_restore_needed = gen_label_rtx (); | |
5662 | rtx loop_exit = gen_label_rtx (); | |
5663 | ||
5664 | mem = gen_rtx_MEM (Pmode, hard_frame_pointer_rtx); | |
5665 | MEM_ALIAS_SET (mem) = rs6000_sr_alias_set; | |
5666 | emit_move_insn (bottom_of_stack, mem); | |
5667 | ||
5668 | top_of_stack = expand_binop (Pmode, add_optab, | |
5669 | bottom_of_stack, stacksize, | |
5670 | NULL_RTX, 1, OPTAB_WIDEN); | |
5671 | ||
5672 | emit_move_insn (tocompare, | |
5673 | GEN_INT (trunc_int_for_mode (TARGET_32BIT | |
5674 | ? 0x80410014 | |
5675 | : 0xE8410028, SImode))); | |
5676 | ||
5677 | if (insn_after_throw == NULL_RTX) | |
5678 | abort(); | |
5679 | emit_move_insn (opcode, insn_after_throw); | |
5680 | ||
6496a589 | 5681 | emit_note (NULL, NOTE_INSN_LOOP_BEG); |
9ebbca7d GK |
5682 | emit_label (loop_start); |
5683 | ||
5684 | do_compare_rtx_and_jump (opcode, tocompare, NE, 1, | |
5685 | SImode, NULL_RTX, 0, NULL_RTX, | |
5686 | no_toc_restore_needed); | |
5687 | ||
5688 | mem = gen_rtx_MEM (Pmode, | |
5689 | gen_rtx_PLUS (Pmode, bottom_of_stack, | |
5690 | GEN_INT (5 * GET_MODE_SIZE (Pmode)))); | |
5691 | emit_move_insn (gen_rtx_REG (Pmode, 2), mem); | |
5692 | ||
5693 | emit_label (no_toc_restore_needed); | |
5694 | do_compare_rtx_and_jump (top_of_stack, bottom_of_stack, EQ, 1, | |
5695 | Pmode, NULL_RTX, 0, NULL_RTX, | |
5696 | loop_exit); | |
5697 | ||
5698 | mem = gen_rtx_MEM (Pmode, bottom_of_stack); | |
5699 | MEM_ALIAS_SET (mem) = rs6000_sr_alias_set; | |
5700 | emit_move_insn (bottom_of_stack, mem); | |
5701 | ||
5702 | mem = gen_rtx_MEM (Pmode, | |
5703 | gen_rtx_PLUS (Pmode, bottom_of_stack, | |
5704 | GEN_INT (2 * GET_MODE_SIZE (Pmode)))); | |
5705 | emit_move_insn (opcode_addr, mem); | |
5706 | emit_move_insn (opcode, gen_rtx_MEM (SImode, opcode_addr)); | |
5707 | ||
6496a589 | 5708 | emit_note (NULL, NOTE_INSN_LOOP_CONT); |
9ebbca7d | 5709 | emit_jump (loop_start); |
6496a589 | 5710 | emit_note (NULL, NOTE_INSN_LOOP_END); |
9ebbca7d GK |
5711 | emit_label (loop_exit); |
5712 | } | |
5713 | #endif /* TARGET_AIX */ | |
38c1f2d7 | 5714 | \f |
9ebbca7d GK |
5715 | /* This ties together stack memory |
5716 | (MEM with an alias set of rs6000_sr_alias_set) | |
5717 | and the change to the stack pointer. */ | |
5718 | static void | |
5719 | rs6000_emit_stack_tie () | |
5720 | { | |
5721 | rtx mem; | |
5722 | mem = gen_rtx_MEM (BLKmode, gen_rtx_REG (Pmode, STACK_POINTER_REGNUM)); | |
5723 | MEM_ALIAS_SET (mem) = rs6000_sr_alias_set; | |
5724 | emit_insn (gen_stack_tie (mem)); | |
5725 | } | |
38c1f2d7 | 5726 | |
9ebbca7d GK |
5727 | /* Emit the correct code for allocating stack space, as insns. |
5728 | If COPY_R12, make sure a copy of the old frame is left in r12. | |
5729 | The generated code may use hard register 0 as a temporary. */ | |
5730 | ||
5731 | static void | |
5732 | rs6000_emit_allocate_stack (size, copy_r12) | |
5733 | HOST_WIDE_INT size; | |
38c1f2d7 MM |
5734 | int copy_r12; |
5735 | { | |
9ebbca7d GK |
5736 | rtx insn; |
5737 | rtx stack_reg = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM); | |
5738 | rtx tmp_reg = gen_rtx_REG (Pmode, 0); | |
5739 | rtx todec = GEN_INT (-size); | |
a157febd GK |
5740 | |
5741 | if (current_function_limit_stack) | |
5742 | { | |
5743 | if (REG_P (stack_limit_rtx) | |
5744 | && REGNO (stack_limit_rtx) > 1 | |
5745 | && REGNO (stack_limit_rtx) <= 31) | |
5746 | { | |
9ebbca7d GK |
5747 | emit_insn (Pmode == SImode |
5748 | ? gen_addsi3 (tmp_reg, | |
5749 | stack_limit_rtx, | |
5750 | GEN_INT (size)) | |
5751 | : gen_adddi3 (tmp_reg, | |
5752 | stack_limit_rtx, | |
5753 | GEN_INT (size))); | |
5754 | ||
5755 | emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg, | |
5756 | const0_rtx)); | |
a157febd GK |
5757 | } |
5758 | else if (GET_CODE (stack_limit_rtx) == SYMBOL_REF | |
9ebbca7d | 5759 | && TARGET_32BIT |
a157febd GK |
5760 | && (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS)) |
5761 | { | |
9ebbca7d GK |
5762 | rtx toload = gen_rtx_CONST (VOIDmode, |
5763 | gen_rtx_PLUS (Pmode, | |
5764 | stack_limit_rtx, | |
5765 | GEN_INT (size))); | |
5766 | ||
5767 | emit_insn (gen_elf_high (tmp_reg, toload)); | |
5768 | emit_insn (gen_elf_low (tmp_reg, tmp_reg, toload)); | |
5769 | emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg, | |
5770 | const0_rtx)); | |
a157febd GK |
5771 | } |
5772 | else | |
5773 | warning ("stack limit expression is not supported"); | |
5774 | } | |
5775 | ||
9ebbca7d GK |
5776 | if (copy_r12 || ! TARGET_UPDATE) |
5777 | emit_move_insn (gen_rtx_REG (Pmode, 12), stack_reg); | |
5778 | ||
38c1f2d7 MM |
5779 | if (TARGET_UPDATE) |
5780 | { | |
9ebbca7d | 5781 | if (size > 32767) |
38c1f2d7 | 5782 | { |
9ebbca7d GK |
5783 | /* Need a note here so that try_split doesn't get confused. */ |
5784 | if (get_last_insn() == NULL_RTX) | |
5785 | emit_note (0, NOTE_INSN_DELETED); | |
5786 | insn = emit_move_insn (tmp_reg, todec); | |
5787 | try_split (PATTERN (insn), insn, 0); | |
5788 | todec = tmp_reg; | |
38c1f2d7 | 5789 | } |
9ebbca7d GK |
5790 | |
5791 | if (Pmode == SImode) | |
5792 | insn = emit_insn (gen_movsi_update (stack_reg, stack_reg, | |
5793 | todec, stack_reg)); | |
5794 | else | |
5795 | insn = emit_insn (gen_movdi_update (stack_reg, stack_reg, | |
5796 | todec, stack_reg)); | |
38c1f2d7 MM |
5797 | } |
5798 | else | |
5799 | { | |
9ebbca7d GK |
5800 | if (Pmode == SImode) |
5801 | insn = emit_insn (gen_addsi3 (stack_reg, stack_reg, todec)); | |
38c1f2d7 | 5802 | else |
9ebbca7d GK |
5803 | insn = emit_insn (gen_adddi3 (stack_reg, stack_reg, todec)); |
5804 | emit_move_insn (gen_rtx_MEM (Pmode, stack_reg), | |
5805 | gen_rtx_REG (Pmode, 12)); | |
5806 | } | |
5807 | ||
5808 | RTX_FRAME_RELATED_P (insn) = 1; | |
5809 | REG_NOTES (insn) = | |
5810 | gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, | |
5811 | gen_rtx_SET (VOIDmode, stack_reg, | |
5812 | gen_rtx_PLUS (Pmode, stack_reg, | |
5813 | GEN_INT (-size))), | |
5814 | REG_NOTES (insn)); | |
5815 | } | |
5816 | ||
5817 | /* Add to 'insn' a note which is PATTERN (INSN) but with REG replaced with | |
5818 | (plus:P (reg 1) VAL), and with REG2 replaced with RREG if REG2 is not | |
5819 | NULL. | |
5820 | It would be nice if dwarf2out_frame_debug_expr could deduce these | |
5821 | equivalences by itself so it wasn't necessary to hold its hand so much. */ | |
5822 | ||
5823 | static void | |
5824 | rs6000_frame_related (insn, reg, val, reg2, rreg) | |
5825 | rtx insn; | |
5826 | rtx reg; | |
5827 | HOST_WIDE_INT val; | |
5828 | rtx reg2; | |
5829 | rtx rreg; | |
5830 | { | |
5831 | rtx real, temp; | |
5832 | ||
5833 | real = copy_rtx (PATTERN (insn)); | |
5834 | ||
5835 | real = replace_rtx (real, reg, | |
5836 | gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode, | |
5837 | STACK_POINTER_REGNUM), | |
5838 | GEN_INT (val))); | |
5839 | ||
5840 | /* We expect that 'real' is either a SET or a PARALLEL containing | |
5841 | SETs (and possibly other stuff). In a PARALLEL, all the SETs | |
5842 | are important so they all have to be marked RTX_FRAME_RELATED_P. */ | |
5843 | ||
5844 | if (GET_CODE (real) == SET) | |
5845 | { | |
5846 | rtx set = real; | |
5847 | ||
5848 | temp = simplify_rtx (SET_SRC (set)); | |
5849 | if (temp) | |
5850 | SET_SRC (set) = temp; | |
5851 | temp = simplify_rtx (SET_DEST (set)); | |
5852 | if (temp) | |
5853 | SET_DEST (set) = temp; | |
5854 | if (GET_CODE (SET_DEST (set)) == MEM) | |
38c1f2d7 | 5855 | { |
9ebbca7d GK |
5856 | temp = simplify_rtx (XEXP (SET_DEST (set), 0)); |
5857 | if (temp) | |
5858 | XEXP (SET_DEST (set), 0) = temp; | |
38c1f2d7 | 5859 | } |
38c1f2d7 | 5860 | } |
9ebbca7d GK |
5861 | else if (GET_CODE (real) == PARALLEL) |
5862 | { | |
5863 | int i; | |
5864 | for (i = 0; i < XVECLEN (real, 0); i++) | |
5865 | if (GET_CODE (XVECEXP (real, 0, i)) == SET) | |
5866 | { | |
5867 | rtx set = XVECEXP (real, 0, i); | |
5868 | ||
5869 | temp = simplify_rtx (SET_SRC (set)); | |
5870 | if (temp) | |
5871 | SET_SRC (set) = temp; | |
5872 | temp = simplify_rtx (SET_DEST (set)); | |
5873 | if (temp) | |
5874 | SET_DEST (set) = temp; | |
5875 | if (GET_CODE (SET_DEST (set)) == MEM) | |
5876 | { | |
5877 | temp = simplify_rtx (XEXP (SET_DEST (set), 0)); | |
5878 | if (temp) | |
5879 | XEXP (SET_DEST (set), 0) = temp; | |
5880 | } | |
5881 | RTX_FRAME_RELATED_P (set) = 1; | |
5882 | } | |
5883 | } | |
5884 | else | |
5885 | abort(); | |
5886 | ||
5887 | if (reg2 != NULL_RTX) | |
5888 | real = replace_rtx (real, reg2, rreg); | |
5889 | ||
5890 | RTX_FRAME_RELATED_P (insn) = 1; | |
5891 | REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, | |
5892 | real, | |
5893 | REG_NOTES (insn)); | |
38c1f2d7 MM |
5894 | } |
5895 | ||
9ebbca7d GK |
5896 | /* Emit function prologue as insns. */ |
5897 | ||
9878760c | 5898 | void |
83720594 | 5899 | rs6000_emit_prologue () |
9878760c | 5900 | { |
4697a36c | 5901 | rs6000_stack_t *info = rs6000_stack_info (); |
9ebbca7d GK |
5902 | enum machine_mode reg_mode = TARGET_POWERPC64 ? DImode : SImode; |
5903 | int reg_size = TARGET_POWERPC64 ? 8 : 4; | |
5904 | rtx sp_reg_rtx = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM); | |
5905 | rtx frame_ptr_rtx = gen_rtx_REG (Pmode, 12); | |
5906 | rtx frame_reg_rtx = sp_reg_rtx; | |
5907 | rtx cr_save_rtx = NULL; | |
5908 | rtx insn; | |
5909 | int saving_FPRs_inline; | |
5910 | int using_store_multiple; | |
5911 | HOST_WIDE_INT sp_offset = 0; | |
5912 | ||
5913 | using_store_multiple = (TARGET_MULTIPLE && ! TARGET_POWERPC64 | |
5914 | && info->first_gp_reg_save < 31); | |
5915 | saving_FPRs_inline = (info->first_fp_reg_save == 64 | |
5916 | || FP_SAVE_INLINE (info->first_fp_reg_save)); | |
5917 | ||
5918 | /* For V.4, update stack before we do any saving and set back pointer. */ | |
5919 | if (info->push_p && (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS)) | |
5920 | { | |
5921 | if (info->total_size < 32767) | |
5922 | sp_offset = info->total_size; | |
5923 | else | |
5924 | frame_reg_rtx = frame_ptr_rtx; | |
5925 | rs6000_emit_allocate_stack (info->total_size, | |
5926 | (frame_reg_rtx != sp_reg_rtx | |
5927 | && (info->cr_save_p | |
5928 | || info->lr_save_p | |
5929 | || info->first_fp_reg_save < 64 | |
5930 | || info->first_gp_reg_save < 32 | |
5931 | ))); | |
5932 | if (frame_reg_rtx != sp_reg_rtx) | |
5933 | rs6000_emit_stack_tie (); | |
5934 | } | |
5935 | ||
5936 | /* If we use the link register, get it into r0. */ | |
5937 | if (info->lr_save_p) | |
71f123ca | 5938 | emit_move_insn (gen_rtx_REG (Pmode, 0), |
9ebbca7d GK |
5939 | gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)); |
5940 | ||
5941 | /* If we need to save CR, put it into r12. */ | |
5942 | if (info->cr_save_p && frame_reg_rtx != frame_ptr_rtx) | |
5943 | { | |
5944 | cr_save_rtx = gen_rtx_REG (SImode, 12); | |
5945 | emit_insn (gen_movesi_from_cr (cr_save_rtx)); | |
5946 | } | |
5947 | ||
5948 | /* Do any required saving of fpr's. If only one or two to save, do it | |
5949 | ourself. Otherwise, call function. */ | |
5950 | if (saving_FPRs_inline) | |
5951 | { | |
5952 | int i; | |
5953 | for (i = 0; i < 64 - info->first_fp_reg_save; i++) | |
5954 | if ((regs_ever_live[info->first_fp_reg_save+i] | |
5955 | && ! call_used_regs[info->first_fp_reg_save+i])) | |
5956 | { | |
5957 | rtx addr, reg, mem; | |
5958 | reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i); | |
5959 | addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
5960 | GEN_INT (info->fp_save_offset | |
5961 | + sp_offset | |
5962 | + 8*i)); | |
5963 | mem = gen_rtx_MEM (DFmode, addr); | |
5964 | MEM_ALIAS_SET (mem) = rs6000_sr_alias_set; | |
5965 | ||
5966 | insn = emit_move_insn (mem, reg); | |
5967 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, | |
5968 | NULL_RTX, NULL_RTX); | |
5969 | } | |
5970 | } | |
5971 | else if (info->first_fp_reg_save != 64) | |
5972 | { | |
5973 | int i; | |
5974 | char rname[30]; | |
520a57c8 | 5975 | const char *alloc_rname; |
9ebbca7d GK |
5976 | rtvec p; |
5977 | p = rtvec_alloc (2 + 64 - info->first_fp_reg_save); | |
5978 | ||
5979 | RTVEC_ELT (p, 0) = gen_rtx_CLOBBER (VOIDmode, | |
5980 | gen_rtx_REG (Pmode, | |
5981 | LINK_REGISTER_REGNUM)); | |
5982 | sprintf (rname, "%s%d%s", SAVE_FP_PREFIX, | |
5983 | info->first_fp_reg_save - 32, SAVE_FP_SUFFIX); | |
a8a05998 | 5984 | alloc_rname = ggc_strdup (rname); |
9ebbca7d GK |
5985 | RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode, |
5986 | gen_rtx_SYMBOL_REF (Pmode, | |
5987 | alloc_rname)); | |
5988 | for (i = 0; i < 64 - info->first_fp_reg_save; i++) | |
5989 | { | |
5990 | rtx addr, reg, mem; | |
5991 | reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i); | |
5992 | addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
5993 | GEN_INT (info->fp_save_offset | |
5994 | + sp_offset + 8*i)); | |
5995 | mem = gen_rtx_MEM (DFmode, addr); | |
5996 | MEM_ALIAS_SET (mem) = rs6000_sr_alias_set; | |
5997 | ||
5998 | RTVEC_ELT (p, i + 2) = gen_rtx_SET (VOIDmode, mem, reg); | |
5999 | } | |
6000 | insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p)); | |
6001 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, | |
6002 | NULL_RTX, NULL_RTX); | |
6003 | } | |
b6c9286a | 6004 | |
9ebbca7d GK |
6005 | /* Save GPRs. This is done as a PARALLEL if we are using |
6006 | the store-multiple instructions. */ | |
6007 | if (using_store_multiple) | |
b6c9286a | 6008 | { |
9ebbca7d GK |
6009 | rtvec p, dwarfp; |
6010 | int i; | |
6011 | p = rtvec_alloc (32 - info->first_gp_reg_save); | |
6012 | dwarfp = rtvec_alloc (32 - info->first_gp_reg_save); | |
6013 | for (i = 0; i < 32 - info->first_gp_reg_save; i++) | |
6014 | { | |
6015 | rtx addr, reg, mem; | |
6016 | reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i); | |
6017 | addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
6018 | GEN_INT (info->gp_save_offset | |
6019 | + sp_offset | |
6020 | + reg_size * i)); | |
6021 | mem = gen_rtx_MEM (reg_mode, addr); | |
6022 | MEM_ALIAS_SET (mem) = rs6000_sr_alias_set; | |
6023 | ||
6024 | RTVEC_ELT (p, i) = gen_rtx_SET (VOIDmode, mem, reg); | |
6025 | } | |
6026 | insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p)); | |
6027 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, | |
6028 | NULL_RTX, NULL_RTX); | |
b6c9286a MM |
6029 | } |
6030 | else | |
6031 | { | |
9ebbca7d GK |
6032 | int i; |
6033 | for (i = 0; i < 32 - info->first_gp_reg_save; i++) | |
6034 | if ((regs_ever_live[info->first_gp_reg_save+i] | |
6035 | && ! call_used_regs[info->first_gp_reg_save+i]) | |
6036 | || (i+info->first_gp_reg_save == PIC_OFFSET_TABLE_REGNUM | |
ee890fe2 SS |
6037 | && (((DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) |
6038 | && flag_pic == 1) | |
6039 | || (DEFAULT_ABI == ABI_DARWIN | |
6040 | && flag_pic)))) | |
9ebbca7d GK |
6041 | { |
6042 | rtx addr, reg, mem; | |
6043 | reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i); | |
6044 | addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
6045 | GEN_INT (info->gp_save_offset | |
6046 | + sp_offset | |
6047 | + reg_size * i)); | |
6048 | mem = gen_rtx_MEM (reg_mode, addr); | |
6049 | MEM_ALIAS_SET (mem) = rs6000_sr_alias_set; | |
6050 | ||
6051 | insn = emit_move_insn (mem, reg); | |
6052 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, | |
6053 | NULL_RTX, NULL_RTX); | |
6054 | } | |
6055 | } | |
6056 | ||
83720594 RH |
6057 | /* ??? There's no need to emit actual instructions here, but it's the |
6058 | easiest way to get the frame unwind information emitted. */ | |
6059 | if (current_function_calls_eh_return) | |
6060 | { | |
78e1b90d DE |
6061 | unsigned int i, regno; |
6062 | ||
83720594 RH |
6063 | for (i = 0; ; ++i) |
6064 | { | |
6065 | rtx addr, reg, mem; | |
6066 | ||
6067 | regno = EH_RETURN_DATA_REGNO (i); | |
6068 | if (regno == INVALID_REGNUM) | |
6069 | break; | |
6070 | ||
6071 | reg = gen_rtx_REG (reg_mode, regno); | |
6072 | addr = plus_constant (frame_reg_rtx, | |
78e1b90d DE |
6073 | info->ehrd_offset + sp_offset |
6074 | + reg_size * (int) i); | |
83720594 RH |
6075 | mem = gen_rtx_MEM (reg_mode, addr); |
6076 | MEM_ALIAS_SET (mem) = rs6000_sr_alias_set; | |
6077 | ||
6078 | insn = emit_move_insn (mem, reg); | |
6079 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, | |
6080 | NULL_RTX, NULL_RTX); | |
6081 | } | |
6082 | } | |
6083 | ||
9ebbca7d GK |
6084 | /* Save lr if we used it. */ |
6085 | if (info->lr_save_p) | |
6086 | { | |
6087 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
6088 | GEN_INT (info->lr_save_offset + sp_offset)); | |
6089 | rtx reg = gen_rtx_REG (Pmode, 0); | |
6090 | rtx mem = gen_rtx_MEM (Pmode, addr); | |
6091 | /* This should not be of rs6000_sr_alias_set, because of | |
6092 | __builtin_return_address. */ | |
6093 | ||
6094 | insn = emit_move_insn (mem, reg); | |
6095 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, | |
6096 | reg, gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)); | |
6097 | } | |
6098 | ||
6099 | /* Save CR if we use any that must be preserved. */ | |
6100 | if (info->cr_save_p) | |
6101 | { | |
6102 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
6103 | GEN_INT (info->cr_save_offset + sp_offset)); | |
6104 | rtx mem = gen_rtx_MEM (SImode, addr); | |
6105 | MEM_ALIAS_SET (mem) = rs6000_sr_alias_set; | |
6106 | ||
6107 | /* If r12 was used to hold the original sp, copy cr into r0 now | |
6108 | that it's free. */ | |
6109 | if (REGNO (frame_reg_rtx) == 12) | |
6110 | { | |
6111 | cr_save_rtx = gen_rtx_REG (SImode, 0); | |
6112 | emit_insn (gen_movesi_from_cr (cr_save_rtx)); | |
6113 | } | |
6114 | insn = emit_move_insn (mem, cr_save_rtx); | |
6115 | ||
6116 | /* Now, there's no way that dwarf2out_frame_debug_expr is going | |
6117 | to understand '(unspec:SI [(reg:CC 68) ...] 19)'. But that's | |
6118 | OK. All we have to do is specify that _one_ condition code | |
6119 | register is saved in this stack slot. The thrower's epilogue | |
6120 | will then restore all the call-saved registers. */ | |
6121 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, | |
6122 | cr_save_rtx, gen_rtx_REG (SImode, CR0_REGNO)); | |
6123 | } | |
6124 | ||
6125 | /* Update stack and set back pointer unless this is V.4, | |
6126 | for which it was done previously. */ | |
6127 | if (info->push_p && DEFAULT_ABI != ABI_V4 && DEFAULT_ABI != ABI_SOLARIS) | |
6128 | rs6000_emit_allocate_stack (info->total_size, FALSE); | |
6129 | ||
6130 | /* Set frame pointer, if needed. */ | |
6131 | if (frame_pointer_needed) | |
6132 | { | |
6133 | insn = emit_move_insn (gen_rtx_REG (reg_mode, FRAME_POINTER_REGNUM), | |
6134 | sp_reg_rtx); | |
6135 | RTX_FRAME_RELATED_P (insn) = 1; | |
b6c9286a | 6136 | } |
9878760c | 6137 | |
9ebbca7d GK |
6138 | /* If we are using PIC_OFFSET_TABLE_REGNUM, we need to set it up. */ |
6139 | if ((TARGET_TOC && TARGET_MINIMAL_TOC && get_pool_size () != 0) | |
6140 | || ((DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) | |
6141 | && flag_pic == 1 && regs_ever_live[PIC_OFFSET_TABLE_REGNUM])) | |
6142 | { | |
6143 | /* If emit_load_toc_table will use the link register, we need to save | |
6144 | it. We use R11 for this purpose because emit_load_toc_table | |
6145 | can use register 0. This allows us to use a plain 'blr' to return | |
6146 | from the procedure more often. */ | |
d5fa86ba GK |
6147 | int save_LR_around_toc_setup = (TARGET_ELF && flag_pic != 0 |
6148 | && ! info->lr_save_p | |
6149 | && EXIT_BLOCK_PTR->pred != NULL); | |
9ebbca7d GK |
6150 | if (save_LR_around_toc_setup) |
6151 | emit_move_insn (gen_rtx_REG (Pmode, 11), | |
6152 | gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)); | |
6153 | ||
6154 | rs6000_emit_load_toc_table (TRUE); | |
6155 | ||
6156 | if (save_LR_around_toc_setup) | |
6157 | emit_move_insn (gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM), | |
6158 | gen_rtx_REG (Pmode, 11)); | |
6159 | } | |
ee890fe2 SS |
6160 | |
6161 | if (DEFAULT_ABI == ABI_DARWIN | |
6162 | && flag_pic && current_function_uses_pic_offset_table) | |
6163 | { | |
6164 | rtx dest = gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM); | |
6165 | ||
6166 | rs6000_maybe_dead (emit_insn (gen_load_macho_picbase (dest))); | |
6167 | ||
6168 | rs6000_maybe_dead ( | |
6169 | emit_move_insn (gen_rtx_REG (Pmode, PIC_OFFSET_TABLE_REGNUM), | |
6170 | gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM))); | |
6171 | } | |
9ebbca7d GK |
6172 | } |
6173 | ||
6174 | ||
6175 | /* Write function prologue. */ | |
6176 | void | |
6177 | output_prolog (file, size) | |
6178 | FILE *file; | |
6179 | int size ATTRIBUTE_UNUSED; | |
6180 | { | |
6181 | rs6000_stack_t *info = rs6000_stack_info (); | |
6182 | ||
4697a36c MM |
6183 | if (TARGET_DEBUG_STACK) |
6184 | debug_stack_info (info); | |
9878760c RK |
6185 | |
6186 | /* Write .extern for any function we will call to save and restore fp | |
6187 | values. */ | |
b6c9286a | 6188 | if (info->first_fp_reg_save < 64 && !FP_SAVE_INLINE (info->first_fp_reg_save)) |
4d30c363 | 6189 | fprintf (file, "\t.extern %s%d%s\n\t.extern %s%d%s\n", |
4697a36c MM |
6190 | SAVE_FP_PREFIX, info->first_fp_reg_save - 32, SAVE_FP_SUFFIX, |
6191 | RESTORE_FP_PREFIX, info->first_fp_reg_save - 32, RESTORE_FP_SUFFIX); | |
9878760c | 6192 | |
c764f757 RK |
6193 | /* Write .extern for AIX common mode routines, if needed. */ |
6194 | if (! TARGET_POWER && ! TARGET_POWERPC && ! common_mode_defined) | |
6195 | { | |
f6709c70 JW |
6196 | fputs ("\t.extern __mulh\n", file); |
6197 | fputs ("\t.extern __mull\n", file); | |
6198 | fputs ("\t.extern __divss\n", file); | |
6199 | fputs ("\t.extern __divus\n", file); | |
6200 | fputs ("\t.extern __quoss\n", file); | |
6201 | fputs ("\t.extern __quous\n", file); | |
c764f757 RK |
6202 | common_mode_defined = 1; |
6203 | } | |
9878760c | 6204 | |
9ebbca7d | 6205 | if (! HAVE_prologue) |
979721f8 | 6206 | { |
9ebbca7d GK |
6207 | start_sequence (); |
6208 | ||
6209 | /* A NOTE_INSN_DELETED is supposed to be at the start | |
6210 | and end of the "toplevel" insn chain. */ | |
6211 | emit_note (0, NOTE_INSN_DELETED); | |
6212 | rs6000_emit_prologue (); | |
6213 | emit_note (0, NOTE_INSN_DELETED); | |
6214 | ||
6215 | if (TARGET_DEBUG_STACK) | |
6216 | debug_rtx_list (get_insns(), 100); | |
6217 | final (get_insns(), file, FALSE, FALSE); | |
6218 | end_sequence (); | |
979721f8 MM |
6219 | } |
6220 | ||
9ebbca7d GK |
6221 | rs6000_pic_labelno++; |
6222 | } | |
6223 | ||
6224 | /* Emit function epilogue as insns. | |
9878760c | 6225 | |
9ebbca7d GK |
6226 | At present, dwarf2out_frame_debug_expr doesn't understand |
6227 | register restores, so we don't bother setting RTX_FRAME_RELATED_P | |
6228 | anywhere in the epilogue. Most of the insns below would in any case | |
6229 | need special notes to explain where r11 is in relation to the stack. */ | |
9878760c | 6230 | |
9ebbca7d | 6231 | void |
83720594 | 6232 | rs6000_emit_epilogue (sibcall) |
9ebbca7d GK |
6233 | int sibcall; |
6234 | { | |
6235 | rs6000_stack_t *info; | |
6236 | int restoring_FPRs_inline; | |
6237 | int using_load_multiple; | |
6238 | int using_mfcr_multiple; | |
6239 | int use_backchain_to_restore_sp; | |
6240 | int sp_offset = 0; | |
6241 | rtx sp_reg_rtx = gen_rtx_REG (Pmode, 1); | |
6242 | rtx frame_reg_rtx = sp_reg_rtx; | |
6243 | enum machine_mode reg_mode = TARGET_POWERPC64 ? DImode : SImode; | |
6244 | int reg_size = TARGET_POWERPC64 ? 8 : 4; | |
6245 | int i; | |
6246 | ||
6247 | info = rs6000_stack_info (); | |
6248 | using_load_multiple = (TARGET_MULTIPLE && ! TARGET_POWERPC64 | |
6249 | && info->first_gp_reg_save < 31); | |
6250 | restoring_FPRs_inline = (sibcall | |
83720594 | 6251 | || current_function_calls_eh_return |
9ebbca7d GK |
6252 | || info->first_fp_reg_save == 64 |
6253 | || FP_SAVE_INLINE (info->first_fp_reg_save)); | |
6254 | use_backchain_to_restore_sp = (frame_pointer_needed | |
6255 | || current_function_calls_alloca | |
6256 | || info->total_size > 32767); | |
6257 | using_mfcr_multiple = (rs6000_cpu == PROCESSOR_PPC601 | |
6258 | || rs6000_cpu == PROCESSOR_PPC603 | |
6259 | || rs6000_cpu == PROCESSOR_PPC750 | |
6260 | || optimize_size); | |
6261 | ||
6262 | /* If we have a frame pointer, a call to alloca, or a large stack | |
6263 | frame, restore the old stack pointer using the backchain. Otherwise, | |
6264 | we know what size to update it with. */ | |
6265 | if (use_backchain_to_restore_sp) | |
bacbde18 | 6266 | { |
9ebbca7d GK |
6267 | /* Under V.4, don't reset the stack pointer until after we're done |
6268 | loading the saved registers. */ | |
6269 | if (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) | |
6270 | frame_reg_rtx = gen_rtx_REG (Pmode, 11); | |
4697a36c | 6271 | |
9ebbca7d GK |
6272 | emit_move_insn (frame_reg_rtx, |
6273 | gen_rtx_MEM (Pmode, sp_reg_rtx)); | |
6274 | ||
bacbde18 | 6275 | } |
9ebbca7d | 6276 | else if (info->push_p) |
85638c0d | 6277 | { |
9ebbca7d GK |
6278 | if (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) |
6279 | sp_offset = info->total_size; | |
6280 | else | |
6281 | { | |
6282 | emit_insn (TARGET_32BIT | |
6283 | ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx, | |
6284 | GEN_INT (info->total_size)) | |
6285 | : gen_adddi3 (sp_reg_rtx, sp_reg_rtx, | |
6286 | GEN_INT (info->total_size))); | |
6287 | } | |
85638c0d | 6288 | } |
9ebbca7d GK |
6289 | |
6290 | /* Get the old lr if we saved it. */ | |
6291 | if (info->lr_save_p) | |
b6c9286a | 6292 | { |
9ebbca7d GK |
6293 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, |
6294 | GEN_INT (info->lr_save_offset + sp_offset)); | |
6295 | rtx mem = gen_rtx_MEM (Pmode, addr); | |
6296 | MEM_ALIAS_SET (mem) = rs6000_sr_alias_set; | |
b6c9286a | 6297 | |
9ebbca7d | 6298 | emit_move_insn (gen_rtx_REG (Pmode, 0), mem); |
b6c9286a | 6299 | } |
9ebbca7d GK |
6300 | |
6301 | /* Get the old cr if we saved it. */ | |
6302 | if (info->cr_save_p) | |
6303 | { | |
6304 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
6305 | GEN_INT (info->cr_save_offset + sp_offset)); | |
6306 | rtx mem = gen_rtx_MEM (SImode, addr); | |
6307 | MEM_ALIAS_SET (mem) = rs6000_sr_alias_set; | |
b6c9286a | 6308 | |
9ebbca7d GK |
6309 | emit_move_insn (gen_rtx_REG (SImode, 12), mem); |
6310 | } | |
6311 | ||
6312 | /* Set LR here to try to overlap restores below. */ | |
4697a36c | 6313 | if (info->lr_save_p) |
9ebbca7d GK |
6314 | emit_move_insn (gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM), |
6315 | gen_rtx_REG (Pmode, 0)); | |
6316 | ||
83720594 RH |
6317 | /* Load exception handler data registers, if needed. */ |
6318 | if (current_function_calls_eh_return) | |
6319 | { | |
78e1b90d DE |
6320 | unsigned int i, regno; |
6321 | ||
83720594 RH |
6322 | for (i = 0; ; ++i) |
6323 | { | |
6324 | rtx addr, mem; | |
6325 | ||
6326 | regno = EH_RETURN_DATA_REGNO (i); | |
6327 | if (regno == INVALID_REGNUM) | |
6328 | break; | |
6329 | ||
6330 | addr = plus_constant (frame_reg_rtx, | |
78e1b90d DE |
6331 | info->ehrd_offset + sp_offset |
6332 | + reg_size * (int) i); | |
83720594 RH |
6333 | mem = gen_rtx_MEM (reg_mode, addr); |
6334 | MEM_ALIAS_SET (mem) = rs6000_sr_alias_set; | |
6335 | ||
6336 | emit_move_insn (gen_rtx_REG (reg_mode, regno), mem); | |
6337 | } | |
6338 | } | |
9ebbca7d GK |
6339 | |
6340 | /* Restore GPRs. This is done as a PARALLEL if we are using | |
6341 | the load-multiple instructions. */ | |
6342 | if (using_load_multiple) | |
979721f8 | 6343 | { |
9ebbca7d GK |
6344 | rtvec p; |
6345 | p = rtvec_alloc (32 - info->first_gp_reg_save); | |
6346 | for (i = 0; i < 32 - info->first_gp_reg_save; i++) | |
979721f8 | 6347 | { |
9ebbca7d GK |
6348 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, |
6349 | GEN_INT (info->gp_save_offset | |
6350 | + sp_offset | |
6351 | + reg_size * i)); | |
6352 | rtx mem = gen_rtx_MEM (reg_mode, addr); | |
6353 | MEM_ALIAS_SET (mem) = rs6000_sr_alias_set; | |
6354 | ||
6355 | RTVEC_ELT (p, i) = | |
6356 | gen_rtx_SET (VOIDmode, | |
6357 | gen_rtx_REG (reg_mode, info->first_gp_reg_save + i), | |
6358 | mem); | |
979721f8 | 6359 | } |
9ebbca7d | 6360 | emit_insn (gen_rtx_PARALLEL (VOIDmode, p)); |
979721f8 | 6361 | } |
9ebbca7d GK |
6362 | else |
6363 | for (i = 0; i < 32 - info->first_gp_reg_save; i++) | |
6364 | if ((regs_ever_live[info->first_gp_reg_save+i] | |
6365 | && ! call_used_regs[info->first_gp_reg_save+i]) | |
6366 | || (i+info->first_gp_reg_save == PIC_OFFSET_TABLE_REGNUM | |
ee890fe2 SS |
6367 | && (((DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) |
6368 | && flag_pic == 1) | |
6369 | || (DEFAULT_ABI == ABI_DARWIN | |
6370 | && flag_pic)))) | |
9ebbca7d GK |
6371 | { |
6372 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
6373 | GEN_INT (info->gp_save_offset | |
6374 | + sp_offset | |
6375 | + reg_size * i)); | |
6376 | rtx mem = gen_rtx_MEM (reg_mode, addr); | |
6377 | MEM_ALIAS_SET (mem) = rs6000_sr_alias_set; | |
6378 | ||
6379 | emit_move_insn (gen_rtx_REG (reg_mode, | |
6380 | info->first_gp_reg_save + i), | |
6381 | mem); | |
6382 | } | |
9878760c | 6383 | |
9ebbca7d GK |
6384 | /* Restore fpr's if we need to do it without calling a function. */ |
6385 | if (restoring_FPRs_inline) | |
6386 | for (i = 0; i < 64 - info->first_fp_reg_save; i++) | |
6387 | if ((regs_ever_live[info->first_fp_reg_save+i] | |
6388 | && ! call_used_regs[info->first_fp_reg_save+i])) | |
6389 | { | |
6390 | rtx addr, mem; | |
6391 | addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
6392 | GEN_INT (info->fp_save_offset | |
6393 | + sp_offset | |
6394 | + 8*i)); | |
6395 | mem = gen_rtx_MEM (DFmode, addr); | |
6396 | MEM_ALIAS_SET (mem) = rs6000_sr_alias_set; | |
6397 | ||
6398 | emit_move_insn (gen_rtx_REG (DFmode, | |
6399 | info->first_fp_reg_save + i), | |
6400 | mem); | |
6401 | } | |
8d30c4ee | 6402 | |
9ebbca7d GK |
6403 | /* If we saved cr, restore it here. Just those that were used. */ |
6404 | if (info->cr_save_p) | |
979721f8 | 6405 | { |
9ebbca7d | 6406 | rtx r12_rtx = gen_rtx_REG (SImode, 12); |
e35b9579 | 6407 | int count = 0; |
9ebbca7d GK |
6408 | |
6409 | if (using_mfcr_multiple) | |
979721f8 | 6410 | { |
9ebbca7d GK |
6411 | for (i = 0; i < 8; i++) |
6412 | if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i]) | |
e35b9579 | 6413 | count++; |
9ebbca7d | 6414 | if (count == 0) |
e35b9579 GK |
6415 | abort (); |
6416 | } | |
6417 | ||
6418 | if (using_mfcr_multiple && count > 1) | |
6419 | { | |
6420 | rtvec p; | |
6421 | int ndx; | |
9ebbca7d | 6422 | |
e35b9579 | 6423 | p = rtvec_alloc (count); |
9ebbca7d | 6424 | |
e35b9579 | 6425 | ndx = 0; |
9ebbca7d GK |
6426 | for (i = 0; i < 8; i++) |
6427 | if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i]) | |
6428 | { | |
6429 | rtvec r = rtvec_alloc (2); | |
6430 | RTVEC_ELT (r, 0) = r12_rtx; | |
6431 | RTVEC_ELT (r, 1) = GEN_INT (1 << (7-i)); | |
e35b9579 | 6432 | RTVEC_ELT (p, ndx) = |
9ebbca7d GK |
6433 | gen_rtx_SET (VOIDmode, gen_rtx_REG (CCmode, CR0_REGNO+i), |
6434 | gen_rtx_UNSPEC (CCmode, r, 20)); | |
e35b9579 | 6435 | ndx++; |
9ebbca7d GK |
6436 | } |
6437 | emit_insn (gen_rtx_PARALLEL (VOIDmode, p)); | |
e35b9579 GK |
6438 | if (ndx != count) |
6439 | abort (); | |
979721f8 MM |
6440 | } |
6441 | else | |
9ebbca7d GK |
6442 | for (i = 0; i < 8; i++) |
6443 | if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i]) | |
979721f8 | 6444 | { |
9ebbca7d GK |
6445 | emit_insn (gen_movsi_to_cr_one (gen_rtx_REG (CCmode, |
6446 | CR0_REGNO+i), | |
6447 | r12_rtx)); | |
979721f8 | 6448 | } |
979721f8 MM |
6449 | } |
6450 | ||
9ebbca7d GK |
6451 | /* If this is V.4, unwind the stack pointer after all of the loads |
6452 | have been done. We need to emit a block here so that sched | |
6453 | doesn't decide to move the sp change before the register restores | |
6454 | (which may not have any obvious dependency on the stack). This | |
6455 | doesn't hurt performance, because there is no scheduling that can | |
6456 | be done after this point. */ | |
6457 | if (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) | |
b6c9286a | 6458 | { |
9ebbca7d GK |
6459 | if (frame_reg_rtx != sp_reg_rtx) |
6460 | rs6000_emit_stack_tie (); | |
b6c9286a | 6461 | |
9ebbca7d | 6462 | if (use_backchain_to_restore_sp) |
b6c9286a | 6463 | { |
9ebbca7d | 6464 | emit_move_insn (sp_reg_rtx, frame_reg_rtx); |
b6c9286a | 6465 | } |
9ebbca7d | 6466 | else if (sp_offset != 0) |
13f1623b | 6467 | { |
9ebbca7d GK |
6468 | emit_insn (Pmode == SImode |
6469 | ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx, | |
6470 | GEN_INT (sp_offset)) | |
6471 | : gen_adddi3 (sp_reg_rtx, sp_reg_rtx, | |
6472 | GEN_INT (sp_offset))); | |
13f1623b | 6473 | } |
9ebbca7d | 6474 | } |
b6c9286a | 6475 | |
83720594 RH |
6476 | if (current_function_calls_eh_return) |
6477 | { | |
6478 | rtx sa = EH_RETURN_STACKADJ_RTX; | |
6479 | emit_insn (Pmode == SImode | |
6480 | ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx, sa) | |
6481 | : gen_adddi3 (sp_reg_rtx, sp_reg_rtx, sa)); | |
6482 | } | |
6483 | ||
9ebbca7d GK |
6484 | if (!sibcall) |
6485 | { | |
6486 | rtvec p; | |
6487 | if (! restoring_FPRs_inline) | |
6488 | p = rtvec_alloc (3 + 64 - info->first_fp_reg_save); | |
6489 | else | |
6490 | p = rtvec_alloc (2); | |
b6c9286a | 6491 | |
e35b9579 GK |
6492 | RTVEC_ELT (p, 0) = gen_rtx_RETURN (VOIDmode); |
6493 | RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode, | |
9ebbca7d GK |
6494 | gen_rtx_REG (Pmode, |
6495 | LINK_REGISTER_REGNUM)); | |
9ebbca7d GK |
6496 | |
6497 | /* If we have to restore more than two FP registers, branch to the | |
6498 | restore function. It will return to our caller. */ | |
6499 | if (! restoring_FPRs_inline) | |
6500 | { | |
6501 | int i; | |
6502 | char rname[30]; | |
520a57c8 | 6503 | const char *alloc_rname; |
979721f8 | 6504 | |
9ebbca7d GK |
6505 | sprintf (rname, "%s%d%s", RESTORE_FP_PREFIX, |
6506 | info->first_fp_reg_save - 32, RESTORE_FP_SUFFIX); | |
a8a05998 | 6507 | alloc_rname = ggc_strdup (rname); |
9ebbca7d GK |
6508 | RTVEC_ELT (p, 2) = gen_rtx_USE (VOIDmode, |
6509 | gen_rtx_SYMBOL_REF (Pmode, | |
6510 | alloc_rname)); | |
b6c9286a | 6511 | |
9ebbca7d GK |
6512 | for (i = 0; i < 64 - info->first_fp_reg_save; i++) |
6513 | { | |
6514 | rtx addr, mem; | |
6515 | addr = gen_rtx_PLUS (Pmode, sp_reg_rtx, | |
6516 | GEN_INT (info->fp_save_offset + 8*i)); | |
6517 | mem = gen_rtx_MEM (DFmode, addr); | |
6518 | MEM_ALIAS_SET (mem) = rs6000_sr_alias_set; | |
6519 | ||
6520 | RTVEC_ELT (p, i+3) = | |
6521 | gen_rtx_SET (VOIDmode, | |
6522 | gen_rtx_REG (DFmode, info->first_fp_reg_save + i), | |
6523 | mem); | |
b6c9286a MM |
6524 | } |
6525 | } | |
9ebbca7d GK |
6526 | |
6527 | emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p)); | |
3daf36a4 | 6528 | } |
9878760c RK |
6529 | } |
6530 | ||
6531 | /* Write function epilogue. */ | |
6532 | ||
6533 | void | |
6534 | output_epilog (file, size) | |
6535 | FILE *file; | |
296b8152 | 6536 | int size ATTRIBUTE_UNUSED; |
9878760c | 6537 | { |
4697a36c | 6538 | rs6000_stack_t *info = rs6000_stack_info (); |
9878760c | 6539 | |
9ebbca7d | 6540 | if (! HAVE_epilogue) |
9878760c | 6541 | { |
9ebbca7d GK |
6542 | rtx insn = get_last_insn (); |
6543 | /* If the last insn was a BARRIER, we don't have to write anything except | |
6544 | the trace table. */ | |
6545 | if (GET_CODE (insn) == NOTE) | |
6546 | insn = prev_nonnote_insn (insn); | |
6547 | if (insn == 0 || GET_CODE (insn) != BARRIER) | |
4697a36c | 6548 | { |
9ebbca7d GK |
6549 | /* This is slightly ugly, but at least we don't have two |
6550 | copies of the epilogue-emitting code. */ | |
6551 | start_sequence (); | |
6552 | ||
6553 | /* A NOTE_INSN_DELETED is supposed to be at the start | |
6554 | and end of the "toplevel" insn chain. */ | |
6555 | emit_note (0, NOTE_INSN_DELETED); | |
6556 | rs6000_emit_epilogue (FALSE); | |
6557 | emit_note (0, NOTE_INSN_DELETED); | |
6558 | ||
6559 | if (TARGET_DEBUG_STACK) | |
6560 | debug_rtx_list (get_insns(), 100); | |
6561 | final (get_insns(), file, FALSE, FALSE); | |
6562 | end_sequence (); | |
4697a36c | 6563 | } |
9878760c | 6564 | } |
b4ac57ab | 6565 | |
9b30bae2 | 6566 | /* Output a traceback table here. See /usr/include/sys/debug.h for info |
314fc5a9 ILT |
6567 | on its format. |
6568 | ||
6569 | We don't output a traceback table if -finhibit-size-directive was | |
6570 | used. The documentation for -finhibit-size-directive reads | |
6571 | ``don't output a @code{.size} assembler directive, or anything | |
6572 | else that would cause trouble if the function is split in the | |
6573 | middle, and the two halves are placed at locations far apart in | |
6574 | memory.'' The traceback table has this property, since it | |
6575 | includes the offset from the start of the function to the | |
4d30c363 MM |
6576 | traceback table itself. |
6577 | ||
6578 | System V.4 Powerpc's (and the embedded ABI derived from it) use a | |
b6c9286a MM |
6579 | different traceback table. */ |
6580 | if (DEFAULT_ABI == ABI_AIX && ! flag_inhibit_size_directive) | |
9b30bae2 | 6581 | { |
3cce094d | 6582 | const char *fname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0); |
314fc5a9 ILT |
6583 | int fixed_parms, float_parms, parm_info; |
6584 | int i; | |
6585 | ||
b6c9286a MM |
6586 | while (*fname == '.') /* V.4 encodes . in the name */ |
6587 | fname++; | |
6588 | ||
314fc5a9 ILT |
6589 | /* Need label immediately before tbtab, so we can compute its offset |
6590 | from the function start. */ | |
6591 | if (*fname == '*') | |
6592 | ++fname; | |
6593 | ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT"); | |
6594 | ASM_OUTPUT_LABEL (file, fname); | |
6595 | ||
6596 | /* The .tbtab pseudo-op can only be used for the first eight | |
6597 | expressions, since it can't handle the possibly variable | |
6598 | length fields that follow. However, if you omit the optional | |
6599 | fields, the assembler outputs zeros for all optional fields | |
6600 | anyways, giving each variable length field is minimum length | |
6601 | (as defined in sys/debug.h). Thus we can not use the .tbtab | |
6602 | pseudo-op at all. */ | |
6603 | ||
6604 | /* An all-zero word flags the start of the tbtab, for debuggers | |
6605 | that have to find it by searching forward from the entry | |
6606 | point or from the current pc. */ | |
19d2d16f | 6607 | fputs ("\t.long 0\n", file); |
314fc5a9 ILT |
6608 | |
6609 | /* Tbtab format type. Use format type 0. */ | |
19d2d16f | 6610 | fputs ("\t.byte 0,", file); |
314fc5a9 ILT |
6611 | |
6612 | /* Language type. Unfortunately, there doesn't seem to be any | |
6613 | official way to get this info, so we use language_string. C | |
6614 | is 0. C++ is 9. No number defined for Obj-C, so use the | |
9517ead8 | 6615 | value for C for now. There is no official value for Java, |
6f573ff9 JL |
6616 | although IBM appears to be using 13. There is no official value |
6617 | for Chill, so we've choosen 44 pseudo-randomly. */ | |
314fc5a9 | 6618 | if (! strcmp (language_string, "GNU C") |
e2c953b6 | 6619 | || ! strcmp (language_string, "GNU Objective-C")) |
314fc5a9 ILT |
6620 | i = 0; |
6621 | else if (! strcmp (language_string, "GNU F77")) | |
6622 | i = 1; | |
6623 | else if (! strcmp (language_string, "GNU Ada")) | |
6624 | i = 3; | |
8b83775b | 6625 | else if (! strcmp (language_string, "GNU Pascal")) |
314fc5a9 ILT |
6626 | i = 2; |
6627 | else if (! strcmp (language_string, "GNU C++")) | |
6628 | i = 9; | |
9517ead8 AG |
6629 | else if (! strcmp (language_string, "GNU Java")) |
6630 | i = 13; | |
6f573ff9 JL |
6631 | else if (! strcmp (language_string, "GNU CHILL")) |
6632 | i = 44; | |
314fc5a9 ILT |
6633 | else |
6634 | abort (); | |
6635 | fprintf (file, "%d,", i); | |
6636 | ||
6637 | /* 8 single bit fields: global linkage (not set for C extern linkage, | |
6638 | apparently a PL/I convention?), out-of-line epilogue/prologue, offset | |
6639 | from start of procedure stored in tbtab, internal function, function | |
6640 | has controlled storage, function has no toc, function uses fp, | |
6641 | function logs/aborts fp operations. */ | |
6642 | /* Assume that fp operations are used if any fp reg must be saved. */ | |
4697a36c | 6643 | fprintf (file, "%d,", (1 << 5) | ((info->first_fp_reg_save != 64) << 1)); |
314fc5a9 ILT |
6644 | |
6645 | /* 6 bitfields: function is interrupt handler, name present in | |
6646 | proc table, function calls alloca, on condition directives | |
6647 | (controls stack walks, 3 bits), saves condition reg, saves | |
6648 | link reg. */ | |
6649 | /* The `function calls alloca' bit seems to be set whenever reg 31 is | |
6650 | set up as a frame pointer, even when there is no alloca call. */ | |
6651 | fprintf (file, "%d,", | |
6652 | ((1 << 6) | (frame_pointer_needed << 5) | |
4697a36c | 6653 | | (info->cr_save_p << 1) | (info->lr_save_p))); |
314fc5a9 ILT |
6654 | |
6655 | /* 3 bitfields: saves backchain, spare bit, number of fpr saved | |
6656 | (6 bits). */ | |
6657 | fprintf (file, "%d,", | |
4697a36c | 6658 | (info->push_p << 7) | (64 - info->first_fp_reg_save)); |
314fc5a9 ILT |
6659 | |
6660 | /* 2 bitfields: spare bits (2 bits), number of gpr saved (6 bits). */ | |
6661 | fprintf (file, "%d,", (32 - first_reg_to_save ())); | |
6662 | ||
6663 | { | |
6664 | /* Compute the parameter info from the function decl argument | |
6665 | list. */ | |
6666 | tree decl; | |
6667 | int next_parm_info_bit; | |
6668 | ||
6669 | next_parm_info_bit = 31; | |
6670 | parm_info = 0; | |
6671 | fixed_parms = 0; | |
6672 | float_parms = 0; | |
6673 | ||
6674 | for (decl = DECL_ARGUMENTS (current_function_decl); | |
6675 | decl; decl = TREE_CHAIN (decl)) | |
6676 | { | |
6677 | rtx parameter = DECL_INCOMING_RTL (decl); | |
6678 | enum machine_mode mode = GET_MODE (parameter); | |
6679 | ||
6680 | if (GET_CODE (parameter) == REG) | |
6681 | { | |
6682 | if (GET_MODE_CLASS (mode) == MODE_FLOAT) | |
6683 | { | |
6684 | int bits; | |
6685 | ||
6686 | float_parms++; | |
6687 | ||
6688 | if (mode == SFmode) | |
6689 | bits = 0x2; | |
6690 | else if (mode == DFmode) | |
6691 | bits = 0x3; | |
6692 | else | |
6693 | abort (); | |
6694 | ||
6695 | /* If only one bit will fit, don't or in this entry. */ | |
6696 | if (next_parm_info_bit > 0) | |
6697 | parm_info |= (bits << (next_parm_info_bit - 1)); | |
6698 | next_parm_info_bit -= 2; | |
6699 | } | |
6700 | else | |
6701 | { | |
6702 | fixed_parms += ((GET_MODE_SIZE (mode) | |
6703 | + (UNITS_PER_WORD - 1)) | |
6704 | / UNITS_PER_WORD); | |
6705 | next_parm_info_bit -= 1; | |
6706 | } | |
6707 | } | |
6708 | } | |
6709 | } | |
6710 | ||
6711 | /* Number of fixed point parameters. */ | |
6712 | /* This is actually the number of words of fixed point parameters; thus | |
6713 | an 8 byte struct counts as 2; and thus the maximum value is 8. */ | |
6714 | fprintf (file, "%d,", fixed_parms); | |
6715 | ||
6716 | /* 2 bitfields: number of floating point parameters (7 bits), parameters | |
6717 | all on stack. */ | |
6718 | /* This is actually the number of fp registers that hold parameters; | |
6719 | and thus the maximum value is 13. */ | |
6720 | /* Set parameters on stack bit if parameters are not in their original | |
6721 | registers, regardless of whether they are on the stack? Xlc | |
6722 | seems to set the bit when not optimizing. */ | |
6723 | fprintf (file, "%d\n", ((float_parms << 1) | (! optimize))); | |
6724 | ||
6725 | /* Optional fields follow. Some are variable length. */ | |
6726 | ||
6727 | /* Parameter types, left adjusted bit fields: 0 fixed, 10 single float, | |
6728 | 11 double float. */ | |
6729 | /* There is an entry for each parameter in a register, in the order that | |
6730 | they occur in the parameter list. Any intervening arguments on the | |
6731 | stack are ignored. If the list overflows a long (max possible length | |
6732 | 34 bits) then completely leave off all elements that don't fit. */ | |
6733 | /* Only emit this long if there was at least one parameter. */ | |
6734 | if (fixed_parms || float_parms) | |
6735 | fprintf (file, "\t.long %d\n", parm_info); | |
6736 | ||
6737 | /* Offset from start of code to tb table. */ | |
19d2d16f | 6738 | fputs ("\t.long ", file); |
314fc5a9 | 6739 | ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT"); |
9ebbca7d | 6740 | #if TARGET_AIX |
314fc5a9 | 6741 | RS6000_OUTPUT_BASENAME (file, fname); |
9ebbca7d GK |
6742 | #else |
6743 | assemble_name (file, fname); | |
6744 | #endif | |
19d2d16f | 6745 | fputs ("-.", file); |
9ebbca7d | 6746 | #if TARGET_AIX |
314fc5a9 | 6747 | RS6000_OUTPUT_BASENAME (file, fname); |
9ebbca7d GK |
6748 | #else |
6749 | assemble_name (file, fname); | |
6750 | #endif | |
19d2d16f | 6751 | putc ('\n', file); |
314fc5a9 ILT |
6752 | |
6753 | /* Interrupt handler mask. */ | |
6754 | /* Omit this long, since we never set the interrupt handler bit | |
6755 | above. */ | |
6756 | ||
6757 | /* Number of CTL (controlled storage) anchors. */ | |
6758 | /* Omit this long, since the has_ctl bit is never set above. */ | |
6759 | ||
6760 | /* Displacement into stack of each CTL anchor. */ | |
6761 | /* Omit this list of longs, because there are no CTL anchors. */ | |
6762 | ||
6763 | /* Length of function name. */ | |
296b8152 | 6764 | fprintf (file, "\t.short %d\n", (int) strlen (fname)); |
314fc5a9 ILT |
6765 | |
6766 | /* Function name. */ | |
6767 | assemble_string (fname, strlen (fname)); | |
6768 | ||
6769 | /* Register for alloca automatic storage; this is always reg 31. | |
6770 | Only emit this if the alloca bit was set above. */ | |
6771 | if (frame_pointer_needed) | |
19d2d16f | 6772 | fputs ("\t.byte 31\n", file); |
9b30bae2 | 6773 | } |
9878760c | 6774 | } |
17167fd8 MM |
6775 | \f |
6776 | /* A C compound statement that outputs the assembler code for a thunk function, | |
6777 | used to implement C++ virtual function calls with multiple inheritance. The | |
6778 | thunk acts as a wrapper around a virtual function, adjusting the implicit | |
6779 | object parameter before handing control off to the real function. | |
6780 | ||
6781 | First, emit code to add the integer DELTA to the location that contains the | |
6782 | incoming first argument. Assume that this argument contains a pointer, and | |
6783 | is the one used to pass the `this' pointer in C++. This is the incoming | |
6784 | argument *before* the function prologue, e.g. `%o0' on a sparc. The | |
6785 | addition must preserve the values of all other incoming arguments. | |
6786 | ||
6787 | After the addition, emit code to jump to FUNCTION, which is a | |
6788 | `FUNCTION_DECL'. This is a direct pure jump, not a call, and does not touch | |
6789 | the return address. Hence returning from FUNCTION will return to whoever | |
6790 | called the current `thunk'. | |
6791 | ||
6792 | The effect must be as if FUNCTION had been called directly with the adjusted | |
6793 | first argument. This macro is responsible for emitting all of the code for | |
6794 | a thunk function; `FUNCTION_PROLOGUE' and `FUNCTION_EPILOGUE' are not | |
6795 | invoked. | |
6796 | ||
6797 | The THUNK_FNDECL is redundant. (DELTA and FUNCTION have already been | |
6798 | extracted from it.) It might possibly be useful on some targets, but | |
6799 | probably not. | |
6800 | ||
6801 | If you do not define this macro, the target-independent code in the C++ | |
6802 | frontend will generate a less efficient heavyweight thunk that calls | |
6803 | FUNCTION instead of jumping to it. The generic approach does not support | |
6804 | varargs. */ | |
6805 | ||
6806 | void | |
6807 | output_mi_thunk (file, thunk_fndecl, delta, function) | |
6808 | FILE *file; | |
d330fd93 | 6809 | tree thunk_fndecl ATTRIBUTE_UNUSED; |
17167fd8 MM |
6810 | int delta; |
6811 | tree function; | |
6812 | { | |
d330fd93 KG |
6813 | const char *this_reg = reg_names[ aggregate_value_p (TREE_TYPE (TREE_TYPE (function))) ? 4 : 3 ]; |
6814 | const char *prefix; | |
3cce094d | 6815 | const char *fname; |
d330fd93 | 6816 | const char *r0 = reg_names[0]; |
d330fd93 KG |
6817 | const char *toc = reg_names[2]; |
6818 | const char *schain = reg_names[11]; | |
6819 | const char *r12 = reg_names[12]; | |
17167fd8 MM |
6820 | char buf[512]; |
6821 | static int labelno = 0; | |
6822 | ||
6823 | /* Small constants that can be done by one add instruction */ | |
6824 | if (delta >= -32768 && delta <= 32767) | |
6825 | { | |
22b4a3b0 | 6826 | if (! TARGET_NEW_MNEMONICS) |
17167fd8 MM |
6827 | fprintf (file, "\tcal %s,%d(%s)\n", this_reg, delta, this_reg); |
6828 | else | |
6829 | fprintf (file, "\taddi %s,%s,%d\n", this_reg, this_reg, delta); | |
6830 | } | |
6831 | ||
6832 | /* Large constants that can be done by one addis instruction */ | |
6833 | else if ((delta & 0xffff) == 0 && num_insns_constant_wide (delta) == 1) | |
6834 | asm_fprintf (file, "\t{cau|addis} %s,%s,%d\n", this_reg, this_reg, | |
6835 | delta >> 16); | |
6836 | ||
6837 | /* 32-bit constants that can be done by an add and addis instruction. */ | |
6838 | else if (TARGET_32BIT || num_insns_constant_wide (delta) == 1) | |
6839 | { | |
22b4a3b0 | 6840 | /* Break into two pieces, propagating the sign bit from the low word to |
17167fd8 MM |
6841 | the upper word. */ |
6842 | int delta_high = delta >> 16; | |
6843 | int delta_low = delta & 0xffff; | |
6844 | if ((delta_low & 0x8000) != 0) | |
6845 | { | |
6846 | delta_high++; | |
6847 | delta_low = (delta_low ^ 0x8000) - 0x8000; /* sign extend */ | |
6848 | } | |
6849 | ||
6850 | asm_fprintf (file, "\t{cau|addis} %s,%s,%d\n", this_reg, this_reg, | |
6851 | delta_high); | |
6852 | ||
22b4a3b0 | 6853 | if (! TARGET_NEW_MNEMONICS) |
17167fd8 MM |
6854 | fprintf (file, "\tcal %s,%d(%s)\n", this_reg, delta_low, this_reg); |
6855 | else | |
6856 | fprintf (file, "\taddi %s,%s,%d\n", this_reg, this_reg, delta_low); | |
6857 | } | |
6858 | ||
6859 | /* 64-bit constants, fixme */ | |
6860 | else | |
6861 | abort (); | |
6862 | ||
6863 | /* Get the prefix in front of the names. */ | |
6864 | switch (DEFAULT_ABI) | |
6865 | { | |
6866 | default: | |
6867 | abort (); | |
6868 | ||
6869 | case ABI_AIX: | |
6870 | prefix = "."; | |
6871 | break; | |
6872 | ||
6873 | case ABI_V4: | |
6874 | case ABI_AIX_NODESC: | |
6875 | case ABI_SOLARIS: | |
6876 | prefix = ""; | |
6877 | break; | |
17167fd8 MM |
6878 | } |
6879 | ||
6880 | /* If the function is compiled in this module, jump to it directly. | |
6881 | Otherwise, load up its address and jump to it. */ | |
6882 | ||
6883 | fname = XSTR (XEXP (DECL_RTL (function), 0), 0); | |
42820a49 | 6884 | |
9ebbca7d | 6885 | if (current_file_function_operand (XEXP (DECL_RTL (function), 0), VOIDmode) |
22b4a3b0 FS |
6886 | && ! lookup_attribute ("longcall", |
6887 | TYPE_ATTRIBUTES (TREE_TYPE (function)))) | |
17167fd8 MM |
6888 | { |
6889 | fprintf (file, "\tb %s", prefix); | |
6890 | assemble_name (file, fname); | |
22b4a3b0 | 6891 | if (DEFAULT_ABI == ABI_V4 && flag_pic) fputs ("@local", file); |
949ea356 | 6892 | putc ('\n', file); |
17167fd8 MM |
6893 | } |
6894 | ||
6895 | else | |
6896 | { | |
6897 | switch (DEFAULT_ABI) | |
6898 | { | |
6899 | default: | |
17167fd8 MM |
6900 | abort (); |
6901 | ||
6902 | case ABI_AIX: | |
6903 | /* Set up a TOC entry for the function. */ | |
6904 | ASM_GENERATE_INTERNAL_LABEL (buf, "Lthunk", labelno); | |
6905 | toc_section (); | |
6906 | ASM_OUTPUT_INTERNAL_LABEL (file, "Lthunk", labelno); | |
6907 | labelno++; | |
6908 | ||
6909 | /* Note, MINIMAL_TOC doesn't make sense in the case of a thunk, since | |
6910 | there will be only one TOC entry for this function. */ | |
6911 | fputs ("\t.tc\t", file); | |
6912 | assemble_name (file, buf); | |
6913 | fputs ("[TC],", file); | |
6914 | assemble_name (file, buf); | |
6915 | putc ('\n', file); | |
6916 | text_section (); | |
6917 | asm_fprintf (file, (TARGET_32BIT) ? "\t{l|lwz} %s," : "\tld %s", r12); | |
6918 | assemble_name (file, buf); | |
6919 | asm_fprintf (file, "(%s)\n", reg_names[2]); | |
6920 | asm_fprintf (file, | |
6921 | (TARGET_32BIT) ? "\t{l|lwz} %s,0(%s)\n" : "\tld %s,0(%s)\n", | |
6922 | r0, r12); | |
6923 | ||
6924 | asm_fprintf (file, | |
6925 | (TARGET_32BIT) ? "\t{l|lwz} %s,4(%s)\n" : "\tld %s,8(%s)\n", | |
6926 | toc, r12); | |
6927 | ||
6928 | asm_fprintf (file, "\tmtctr %s\n", r0); | |
6929 | asm_fprintf (file, | |
6930 | (TARGET_32BIT) ? "\t{l|lwz} %s,8(%s)\n" : "\tld %s,16(%s)\n", | |
6931 | schain, r12); | |
6932 | ||
6933 | asm_fprintf (file, "\tbctr\n"); | |
6934 | break; | |
6935 | ||
9ebbca7d GK |
6936 | case ABI_AIX_NODESC: |
6937 | case ABI_SOLARIS: | |
17167fd8 | 6938 | case ABI_V4: |
22b4a3b0 FS |
6939 | fprintf (file, "\tb %s", prefix); |
6940 | assemble_name (file, fname); | |
6941 | if (flag_pic) fputs ("@plt", file); | |
949ea356 | 6942 | putc ('\n', file); |
22b4a3b0 | 6943 | break; |
ee890fe2 SS |
6944 | |
6945 | #if TARGET_MACHO | |
6946 | case ABI_DARWIN: | |
6947 | fprintf (file, "\tb %s", prefix); | |
6948 | if (flag_pic && !machopic_name_defined_p (fname)) | |
6949 | assemble_name (file, machopic_stub_name (fname)); | |
6950 | else | |
6951 | assemble_name (file, fname); | |
6952 | putc ('\n', file); | |
6953 | break; | |
6954 | #endif | |
9ebbca7d GK |
6955 | } |
6956 | } | |
6957 | } | |
42820a49 | 6958 | |
9ebbca7d GK |
6959 | \f |
6960 | /* A quick summary of the various types of 'constant-pool tables' | |
6961 | under PowerPC: | |
6962 | ||
6963 | Target Flags Name One table per | |
6964 | AIX (none) AIX TOC object file | |
6965 | AIX -mfull-toc AIX TOC object file | |
6966 | AIX -mminimal-toc AIX minimal TOC translation unit | |
6967 | SVR4/EABI (none) SVR4 SDATA object file | |
6968 | SVR4/EABI -fpic SVR4 pic object file | |
6969 | SVR4/EABI -fPIC SVR4 PIC translation unit | |
6970 | SVR4/EABI -mrelocatable EABI TOC function | |
6971 | SVR4/EABI -maix AIX TOC object file | |
6972 | SVR4/EABI -maix -mminimal-toc | |
6973 | AIX minimal TOC translation unit | |
6974 | ||
6975 | Name Reg. Set by entries contains: | |
6976 | made by addrs? fp? sum? | |
6977 | ||
6978 | AIX TOC 2 crt0 as Y option option | |
6979 | AIX minimal TOC 30 prolog gcc Y Y option | |
6980 | SVR4 SDATA 13 crt0 gcc N Y N | |
6981 | SVR4 pic 30 prolog ld Y not yet N | |
6982 | SVR4 PIC 30 prolog gcc Y option option | |
6983 | EABI TOC 30 prolog gcc Y option option | |
6984 | ||
6985 | */ | |
6986 | ||
6987 | /* Hash table stuff for keeping track of TOC entries. */ | |
6988 | ||
6989 | struct toc_hash_struct | |
6990 | { | |
6991 | /* `key' will satisfy CONSTANT_P; in fact, it will satisfy | |
6992 | ASM_OUTPUT_SPECIAL_POOL_ENTRY_P. */ | |
6993 | rtx key; | |
a9098fd0 | 6994 | enum machine_mode key_mode; |
9ebbca7d GK |
6995 | int labelno; |
6996 | }; | |
17167fd8 | 6997 | |
9ebbca7d GK |
6998 | static htab_t toc_hash_table; |
6999 | ||
7000 | /* Hash functions for the hash table. */ | |
7001 | ||
7002 | static unsigned | |
7003 | rs6000_hash_constant (k) | |
7004 | rtx k; | |
7005 | { | |
a9098fd0 | 7006 | unsigned result = (GET_CODE (k) << 3) ^ GET_MODE (k); |
9ebbca7d GK |
7007 | const char *format = GET_RTX_FORMAT (GET_CODE (k)); |
7008 | int flen = strlen (format); | |
7009 | int fidx; | |
7010 | ||
7011 | if (GET_CODE (k) == LABEL_REF) | |
832ea3b3 | 7012 | return result * 1231 + X0INT (XEXP (k, 0), 3); |
9ebbca7d GK |
7013 | |
7014 | if (GET_CODE (k) == CONST_DOUBLE) | |
7015 | fidx = 2; | |
7016 | else if (GET_CODE (k) == CODE_LABEL) | |
7017 | fidx = 3; | |
7018 | else | |
7019 | fidx = 0; | |
7020 | ||
7021 | for (; fidx < flen; fidx++) | |
7022 | switch (format[fidx]) | |
7023 | { | |
7024 | case 's': | |
7025 | { | |
7026 | unsigned i, len; | |
7027 | const char *str = XSTR (k, fidx); | |
7028 | len = strlen (str); | |
7029 | result = result * 613 + len; | |
7030 | for (i = 0; i < len; i++) | |
7031 | result = result * 613 + (unsigned) str[i]; | |
17167fd8 MM |
7032 | break; |
7033 | } | |
9ebbca7d GK |
7034 | case 'u': |
7035 | case 'e': | |
7036 | result = result * 1231 + rs6000_hash_constant (XEXP (k, fidx)); | |
7037 | break; | |
7038 | case 'i': | |
7039 | case 'n': | |
7040 | result = result * 613 + (unsigned) XINT (k, fidx); | |
7041 | break; | |
7042 | case 'w': | |
7043 | if (sizeof (unsigned) >= sizeof (HOST_WIDE_INT)) | |
7044 | result = result * 613 + (unsigned) XWINT (k, fidx); | |
7045 | else | |
7046 | { | |
7047 | size_t i; | |
7048 | for (i = 0; i < sizeof(HOST_WIDE_INT)/sizeof(unsigned); i++) | |
7049 | result = result * 613 + (unsigned) (XWINT (k, fidx) | |
7050 | >> CHAR_BIT * i); | |
7051 | } | |
7052 | break; | |
7053 | default: | |
7054 | abort(); | |
7055 | } | |
7056 | return result; | |
7057 | } | |
7058 | ||
7059 | static unsigned | |
7060 | toc_hash_function (hash_entry) | |
7061 | const void * hash_entry; | |
7062 | { | |
a9098fd0 GK |
7063 | const struct toc_hash_struct *thc = |
7064 | (const struct toc_hash_struct *) hash_entry; | |
7065 | return rs6000_hash_constant (thc->key) ^ thc->key_mode; | |
9ebbca7d GK |
7066 | } |
7067 | ||
7068 | /* Compare H1 and H2 for equivalence. */ | |
7069 | ||
7070 | static int | |
7071 | toc_hash_eq (h1, h2) | |
7072 | const void * h1; | |
7073 | const void * h2; | |
7074 | { | |
7075 | rtx r1 = ((const struct toc_hash_struct *) h1)->key; | |
7076 | rtx r2 = ((const struct toc_hash_struct *) h2)->key; | |
7077 | ||
a9098fd0 GK |
7078 | if (((const struct toc_hash_struct *) h1)->key_mode |
7079 | != ((const struct toc_hash_struct *) h2)->key_mode) | |
7080 | return 0; | |
7081 | ||
9ebbca7d GK |
7082 | /* Gotcha: One of these const_doubles will be in memory. |
7083 | The other may be on the constant-pool chain. | |
7084 | So rtx_equal_p will think they are different... */ | |
7085 | if (r1 == r2) | |
7086 | return 1; | |
7087 | if (GET_CODE (r1) != GET_CODE (r2) | |
7088 | || GET_MODE (r1) != GET_MODE (r2)) | |
7089 | return 0; | |
7090 | if (GET_CODE (r1) == CONST_DOUBLE) | |
7091 | { | |
7092 | int format_len = strlen (GET_RTX_FORMAT (CONST_DOUBLE)); | |
7093 | int i; | |
7094 | for (i = 2; i < format_len; i++) | |
7095 | if (XWINT (r1, i) != XWINT (r2, i)) | |
7096 | return 0; | |
7097 | ||
7098 | return 1; | |
17167fd8 | 7099 | } |
9ebbca7d | 7100 | else if (GET_CODE (r1) == LABEL_REF) |
e4a0656f GK |
7101 | return (CODE_LABEL_NUMBER (XEXP (r1, 0)) |
7102 | == CODE_LABEL_NUMBER (XEXP (r2, 0))); | |
9ebbca7d GK |
7103 | else |
7104 | return rtx_equal_p (r1, r2); | |
7105 | } | |
7106 | ||
7107 | /* Mark the hash table-entry HASH_ENTRY. */ | |
7108 | ||
7109 | static int | |
7110 | toc_hash_mark_entry (hash_slot, unused) | |
2eba1afa | 7111 | void ** hash_slot; |
9ebbca7d GK |
7112 | void * unused ATTRIBUTE_UNUSED; |
7113 | { | |
7114 | const struct toc_hash_struct * hash_entry = | |
7115 | *(const struct toc_hash_struct **) hash_slot; | |
7116 | rtx r = hash_entry->key; | |
7117 | ggc_set_mark (hash_entry); | |
7118 | /* For CODE_LABELS, we don't want to drag in the whole insn chain... */ | |
7119 | if (GET_CODE (r) == LABEL_REF) | |
7120 | { | |
7121 | ggc_set_mark (r); | |
7122 | ggc_set_mark (XEXP (r, 0)); | |
7123 | } | |
7124 | else | |
7125 | ggc_mark_rtx (r); | |
7126 | return 1; | |
7127 | } | |
7128 | ||
7129 | /* Mark all the elements of the TOC hash-table *HT. */ | |
7130 | ||
7131 | static void | |
7132 | toc_hash_mark_table (vht) | |
7133 | void *vht; | |
7134 | { | |
7135 | htab_t *ht = vht; | |
7136 | ||
7137 | htab_traverse (*ht, toc_hash_mark_entry, (void *)0); | |
17167fd8 MM |
7138 | } |
7139 | ||
28e510bd MM |
7140 | /* These are the names given by the C++ front-end to vtables, and |
7141 | vtable-like objects. Ideally, this logic should not be here; | |
7142 | instead, there should be some programmatic way of inquiring as | |
7143 | to whether or not an object is a vtable. */ | |
7144 | ||
7145 | #define VTABLE_NAME_P(NAME) \ | |
7146 | (strncmp ("_vt.", name, strlen("_vt.")) == 0 \ | |
7147 | || strncmp ("_ZTV", name, strlen ("_ZTV")) == 0 \ | |
7148 | || strncmp ("_ZTT", name, strlen ("_ZTT")) == 0 \ | |
7149 | || strncmp ("_ZTC", name, strlen ("_ZTC")) == 0) | |
7150 | ||
7151 | void | |
7152 | rs6000_output_symbol_ref (file, x) | |
7153 | FILE *file; | |
7154 | rtx x; | |
7155 | { | |
7156 | /* Currently C++ toc references to vtables can be emitted before it | |
7157 | is decided whether the vtable is public or private. If this is | |
7158 | the case, then the linker will eventually complain that there is | |
7159 | a reference to an unknown section. Thus, for vtables only, | |
7160 | we emit the TOC reference to reference the symbol and not the | |
7161 | section. */ | |
7162 | const char *name = XSTR (x, 0); | |
7163 | ||
7164 | if (VTABLE_NAME_P (name)) | |
7165 | { | |
7166 | RS6000_OUTPUT_BASENAME (file, name); | |
7167 | } | |
7168 | else | |
7169 | assemble_name (file, name); | |
7170 | } | |
7171 | ||
9878760c RK |
7172 | /* Output a TOC entry. We derive the entry name from what is |
7173 | being written. */ | |
7174 | ||
7175 | void | |
a9098fd0 | 7176 | output_toc (file, x, labelno, mode) |
9878760c RK |
7177 | FILE *file; |
7178 | rtx x; | |
7179 | int labelno; | |
a9098fd0 | 7180 | enum machine_mode mode; |
9878760c RK |
7181 | { |
7182 | char buf[256]; | |
3cce094d | 7183 | const char *name = buf; |
ec940faa | 7184 | const char *real_name; |
9878760c RK |
7185 | rtx base = x; |
7186 | int offset = 0; | |
7187 | ||
4697a36c MM |
7188 | if (TARGET_NO_TOC) |
7189 | abort (); | |
7190 | ||
9ebbca7d GK |
7191 | /* When the linker won't eliminate them, don't output duplicate |
7192 | TOC entries (this happens on AIX if there is any kind of TOC, | |
1f8f4a0b MM |
7193 | and on SVR4 under -fPIC or -mrelocatable). */ |
7194 | if (TARGET_TOC) | |
9ebbca7d GK |
7195 | { |
7196 | struct toc_hash_struct *h; | |
7197 | void * * found; | |
7198 | ||
7199 | h = ggc_alloc (sizeof (*h)); | |
7200 | h->key = x; | |
a9098fd0 | 7201 | h->key_mode = mode; |
9ebbca7d GK |
7202 | h->labelno = labelno; |
7203 | ||
7204 | found = htab_find_slot (toc_hash_table, h, 1); | |
7205 | if (*found == NULL) | |
7206 | *found = h; | |
7207 | else /* This is indeed a duplicate. | |
7208 | Set this label equal to that label. */ | |
7209 | { | |
7210 | fputs ("\t.set ", file); | |
7211 | ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC"); | |
7212 | fprintf (file, "%d,", labelno); | |
7213 | ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC"); | |
7214 | fprintf (file, "%d\n", ((*(const struct toc_hash_struct **) | |
7215 | found)->labelno)); | |
7216 | return; | |
7217 | } | |
7218 | } | |
7219 | ||
7220 | /* If we're going to put a double constant in the TOC, make sure it's | |
7221 | aligned properly when strict alignment is on. */ | |
ff1720ed RK |
7222 | if (GET_CODE (x) == CONST_DOUBLE |
7223 | && STRICT_ALIGNMENT | |
a9098fd0 | 7224 | && GET_MODE_BITSIZE (mode) >= 64 |
ff1720ed RK |
7225 | && ! (TARGET_NO_FP_IN_TOC && ! TARGET_MINIMAL_TOC)) { |
7226 | ASM_OUTPUT_ALIGN (file, 3); | |
7227 | } | |
7228 | ||
9ebbca7d | 7229 | ASM_OUTPUT_INTERNAL_LABEL (file, "LC", labelno); |
9878760c | 7230 | |
37c37a57 RK |
7231 | /* Handle FP constants specially. Note that if we have a minimal |
7232 | TOC, things we put here aren't actually in the TOC, so we can allow | |
7233 | FP constants. */ | |
a9098fd0 | 7234 | if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == DFmode) |
9878760c | 7235 | { |
042259f2 DE |
7236 | REAL_VALUE_TYPE rv; |
7237 | long k[2]; | |
0adc764e | 7238 | |
042259f2 DE |
7239 | REAL_VALUE_FROM_CONST_DOUBLE (rv, x); |
7240 | REAL_VALUE_TO_TARGET_DOUBLE (rv, k); | |
31bfaa0b | 7241 | |
13ded975 DE |
7242 | if (TARGET_64BIT) |
7243 | { | |
7244 | if (TARGET_MINIMAL_TOC) | |
7245 | fprintf (file, "\t.llong 0x%lx%08lx\n", k[0], k[1]); | |
7246 | else | |
7247 | fprintf (file, "\t.tc FD_%lx_%lx[TC],0x%lx%08lx\n", | |
0858c623 | 7248 | k[0], k[1], k[0] & 0xffffffff, k[1] & 0xffffffff); |
13ded975 DE |
7249 | return; |
7250 | } | |
1875cc88 | 7251 | else |
13ded975 DE |
7252 | { |
7253 | if (TARGET_MINIMAL_TOC) | |
31bfaa0b | 7254 | fprintf (file, "\t.long 0x%lx\n\t.long 0x%lx\n", k[0], k[1]); |
13ded975 | 7255 | else |
31bfaa0b | 7256 | fprintf (file, "\t.tc FD_%lx_%lx[TC],0x%lx,0x%lx\n", |
13ded975 DE |
7257 | k[0], k[1], k[0], k[1]); |
7258 | return; | |
7259 | } | |
9878760c | 7260 | } |
a9098fd0 | 7261 | else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == SFmode) |
9878760c | 7262 | { |
042259f2 DE |
7263 | REAL_VALUE_TYPE rv; |
7264 | long l; | |
9878760c | 7265 | |
042259f2 DE |
7266 | REAL_VALUE_FROM_CONST_DOUBLE (rv, x); |
7267 | REAL_VALUE_TO_TARGET_SINGLE (rv, l); | |
7268 | ||
31bfaa0b DE |
7269 | if (TARGET_64BIT) |
7270 | { | |
7271 | if (TARGET_MINIMAL_TOC) | |
7272 | fprintf (file, "\t.llong 0x%lx00000000\n", l); | |
7273 | else | |
7274 | fprintf (file, "\t.tc FS_%lx[TC],0x%lx00000000\n", l, l); | |
7275 | return; | |
7276 | } | |
042259f2 | 7277 | else |
31bfaa0b DE |
7278 | { |
7279 | if (TARGET_MINIMAL_TOC) | |
7280 | fprintf (file, "\t.long 0x%lx\n", l); | |
7281 | else | |
7282 | fprintf (file, "\t.tc FS_%lx[TC],0x%lx\n", l, l); | |
7283 | return; | |
7284 | } | |
042259f2 | 7285 | } |
f176e826 | 7286 | else if (GET_MODE (x) == VOIDmode |
a9098fd0 | 7287 | && (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE)) |
042259f2 | 7288 | { |
e2c953b6 | 7289 | unsigned HOST_WIDE_INT low; |
042259f2 DE |
7290 | HOST_WIDE_INT high; |
7291 | ||
7292 | if (GET_CODE (x) == CONST_DOUBLE) | |
7293 | { | |
7294 | low = CONST_DOUBLE_LOW (x); | |
7295 | high = CONST_DOUBLE_HIGH (x); | |
7296 | } | |
7297 | else | |
7298 | #if HOST_BITS_PER_WIDE_INT == 32 | |
7299 | { | |
7300 | low = INTVAL (x); | |
0858c623 | 7301 | high = (low & 0x80000000) ? ~0 : 0; |
042259f2 DE |
7302 | } |
7303 | #else | |
7304 | { | |
0858c623 | 7305 | low = INTVAL (x) & 0xffffffff; |
042259f2 DE |
7306 | high = (HOST_WIDE_INT) INTVAL (x) >> 32; |
7307 | } | |
7308 | #endif | |
9878760c | 7309 | |
a9098fd0 GK |
7310 | /* TOC entries are always Pmode-sized, but since this |
7311 | is a bigendian machine then if we're putting smaller | |
7312 | integer constants in the TOC we have to pad them. | |
7313 | (This is still a win over putting the constants in | |
7314 | a separate constant pool, because then we'd have | |
02a4ec28 FS |
7315 | to have both a TOC entry _and_ the actual constant.) |
7316 | ||
7317 | For a 32-bit target, CONST_INT values are loaded and shifted | |
7318 | entirely within `low' and can be stored in one TOC entry. */ | |
7319 | ||
7320 | if (TARGET_64BIT && POINTER_SIZE < GET_MODE_BITSIZE (mode)) | |
a9098fd0 | 7321 | abort ();/* It would be easy to make this work, but it doesn't now. */ |
02a4ec28 FS |
7322 | |
7323 | if (POINTER_SIZE > GET_MODE_BITSIZE (mode)) | |
a9098fd0 GK |
7324 | lshift_double (low, high, POINTER_SIZE - GET_MODE_BITSIZE (mode), |
7325 | POINTER_SIZE, &low, &high, 0); | |
7326 | ||
13ded975 DE |
7327 | if (TARGET_64BIT) |
7328 | { | |
7329 | if (TARGET_MINIMAL_TOC) | |
7330 | fprintf (file, "\t.llong 0x%lx%08lx\n", (long)high, (long)low); | |
7331 | else | |
7332 | fprintf (file, "\t.tc ID_%lx_%lx[TC],0x%lx%08lx\n", | |
7333 | (long)high, (long)low, (long)high, (long)low); | |
7334 | return; | |
7335 | } | |
1875cc88 | 7336 | else |
13ded975 | 7337 | { |
02a4ec28 FS |
7338 | if (POINTER_SIZE < GET_MODE_BITSIZE (mode)) |
7339 | { | |
7340 | if (TARGET_MINIMAL_TOC) | |
7341 | fprintf (file, "\t.long 0x%lx\n\t.long 0x%lx\n", | |
7342 | (long)high, (long)low); | |
7343 | else | |
7344 | fprintf (file, "\t.tc ID_%lx_%lx[TC],0x%lx,0x%lx\n", | |
7345 | (long)high, (long)low, (long)high, (long)low); | |
7346 | } | |
13ded975 | 7347 | else |
02a4ec28 FS |
7348 | { |
7349 | if (TARGET_MINIMAL_TOC) | |
7350 | fprintf (file, "\t.long 0x%lx\n", | |
7351 | (long)low); | |
7352 | else | |
7353 | fprintf (file, "\t.tc IS_%lx[TC],0x%lx\n", | |
7354 | (long)low, (long)low); | |
7355 | } | |
13ded975 DE |
7356 | return; |
7357 | } | |
9878760c RK |
7358 | } |
7359 | ||
7360 | if (GET_CODE (x) == CONST) | |
7361 | { | |
7362 | base = XEXP (XEXP (x, 0), 0); | |
7363 | offset = INTVAL (XEXP (XEXP (x, 0), 1)); | |
7364 | } | |
7365 | ||
7366 | if (GET_CODE (base) == SYMBOL_REF) | |
7367 | name = XSTR (base, 0); | |
7368 | else if (GET_CODE (base) == LABEL_REF) | |
7369 | ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (XEXP (base, 0))); | |
7370 | else if (GET_CODE (base) == CODE_LABEL) | |
7371 | ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (base)); | |
7372 | else | |
7373 | abort (); | |
7374 | ||
2e4eb9b0 | 7375 | STRIP_NAME_ENCODING (real_name, name); |
1875cc88 | 7376 | if (TARGET_MINIMAL_TOC) |
13ded975 | 7377 | fputs (TARGET_32BIT ? "\t.long " : "\t.llong ", file); |
1875cc88 JW |
7378 | else |
7379 | { | |
b6c9286a | 7380 | fprintf (file, "\t.tc %s", real_name); |
9878760c | 7381 | |
1875cc88 JW |
7382 | if (offset < 0) |
7383 | fprintf (file, ".N%d", - offset); | |
7384 | else if (offset) | |
7385 | fprintf (file, ".P%d", offset); | |
9878760c | 7386 | |
19d2d16f | 7387 | fputs ("[TC],", file); |
1875cc88 | 7388 | } |
581bc4de MM |
7389 | |
7390 | /* Currently C++ toc references to vtables can be emitted before it | |
7391 | is decided whether the vtable is public or private. If this is | |
7392 | the case, then the linker will eventually complain that there is | |
7393 | a TOC reference to an unknown section. Thus, for vtables only, | |
7394 | we emit the TOC reference to reference the symbol and not the | |
7395 | section. */ | |
28e510bd | 7396 | if (VTABLE_NAME_P (name)) |
581bc4de | 7397 | { |
89c01f0e | 7398 | RS6000_OUTPUT_BASENAME (file, name); |
581bc4de MM |
7399 | if (offset < 0) |
7400 | fprintf (file, "%d", offset); | |
7401 | else if (offset > 0) | |
7402 | fprintf (file, "+%d", offset); | |
7403 | } | |
7404 | else | |
7405 | output_addr_const (file, x); | |
19d2d16f | 7406 | putc ('\n', file); |
9878760c RK |
7407 | } |
7408 | \f | |
7409 | /* Output an assembler pseudo-op to write an ASCII string of N characters | |
7410 | starting at P to FILE. | |
7411 | ||
7412 | On the RS/6000, we have to do this using the .byte operation and | |
7413 | write out special characters outside the quoted string. | |
7414 | Also, the assembler is broken; very long strings are truncated, | |
7415 | so we must artificially break them up early. */ | |
7416 | ||
7417 | void | |
7418 | output_ascii (file, p, n) | |
7419 | FILE *file; | |
d330fd93 | 7420 | const char *p; |
9878760c RK |
7421 | int n; |
7422 | { | |
7423 | char c; | |
7424 | int i, count_string; | |
d330fd93 KG |
7425 | const char *for_string = "\t.byte \""; |
7426 | const char *for_decimal = "\t.byte "; | |
7427 | const char *to_close = NULL; | |
9878760c RK |
7428 | |
7429 | count_string = 0; | |
7430 | for (i = 0; i < n; i++) | |
7431 | { | |
7432 | c = *p++; | |
7433 | if (c >= ' ' && c < 0177) | |
7434 | { | |
7435 | if (for_string) | |
7436 | fputs (for_string, file); | |
7437 | putc (c, file); | |
7438 | ||
7439 | /* Write two quotes to get one. */ | |
7440 | if (c == '"') | |
7441 | { | |
7442 | putc (c, file); | |
7443 | ++count_string; | |
7444 | } | |
7445 | ||
7446 | for_string = NULL; | |
7447 | for_decimal = "\"\n\t.byte "; | |
7448 | to_close = "\"\n"; | |
7449 | ++count_string; | |
7450 | ||
7451 | if (count_string >= 512) | |
7452 | { | |
7453 | fputs (to_close, file); | |
7454 | ||
7455 | for_string = "\t.byte \""; | |
7456 | for_decimal = "\t.byte "; | |
7457 | to_close = NULL; | |
7458 | count_string = 0; | |
7459 | } | |
7460 | } | |
7461 | else | |
7462 | { | |
7463 | if (for_decimal) | |
7464 | fputs (for_decimal, file); | |
7465 | fprintf (file, "%d", c); | |
7466 | ||
7467 | for_string = "\n\t.byte \""; | |
7468 | for_decimal = ", "; | |
7469 | to_close = "\n"; | |
7470 | count_string = 0; | |
7471 | } | |
7472 | } | |
7473 | ||
7474 | /* Now close the string if we have written one. Then end the line. */ | |
7475 | if (to_close) | |
9ebbca7d | 7476 | fputs (to_close, file); |
9878760c RK |
7477 | } |
7478 | \f | |
7479 | /* Generate a unique section name for FILENAME for a section type | |
7480 | represented by SECTION_DESC. Output goes into BUF. | |
7481 | ||
7482 | SECTION_DESC can be any string, as long as it is different for each | |
7483 | possible section type. | |
7484 | ||
7485 | We name the section in the same manner as xlc. The name begins with an | |
7486 | underscore followed by the filename (after stripping any leading directory | |
11e5fe42 RK |
7487 | names) with the last period replaced by the string SECTION_DESC. If |
7488 | FILENAME does not contain a period, SECTION_DESC is appended to the end of | |
7489 | the name. */ | |
9878760c RK |
7490 | |
7491 | void | |
7492 | rs6000_gen_section_name (buf, filename, section_desc) | |
7493 | char **buf; | |
9ebbca7d GK |
7494 | const char *filename; |
7495 | const char *section_desc; | |
9878760c | 7496 | { |
9ebbca7d | 7497 | const char *q, *after_last_slash, *last_period = 0; |
9878760c RK |
7498 | char *p; |
7499 | int len; | |
9878760c RK |
7500 | |
7501 | after_last_slash = filename; | |
7502 | for (q = filename; *q; q++) | |
11e5fe42 RK |
7503 | { |
7504 | if (*q == '/') | |
7505 | after_last_slash = q + 1; | |
7506 | else if (*q == '.') | |
7507 | last_period = q; | |
7508 | } | |
9878760c | 7509 | |
11e5fe42 | 7510 | len = strlen (after_last_slash) + strlen (section_desc) + 2; |
9878760c RK |
7511 | *buf = (char *) permalloc (len); |
7512 | ||
7513 | p = *buf; | |
7514 | *p++ = '_'; | |
7515 | ||
7516 | for (q = after_last_slash; *q; q++) | |
7517 | { | |
11e5fe42 | 7518 | if (q == last_period) |
9878760c RK |
7519 | { |
7520 | strcpy (p, section_desc); | |
7521 | p += strlen (section_desc); | |
9878760c RK |
7522 | } |
7523 | ||
e9a780ec | 7524 | else if (ISALNUM (*q)) |
9878760c RK |
7525 | *p++ = *q; |
7526 | } | |
7527 | ||
11e5fe42 | 7528 | if (last_period == 0) |
9878760c RK |
7529 | strcpy (p, section_desc); |
7530 | else | |
7531 | *p = '\0'; | |
7532 | } | |
e165f3f0 | 7533 | \f |
411707f4 CC |
7534 | |
7535 | /* Emit profile function. */ | |
7536 | void | |
7537 | output_profile_hook (labelno) | |
7538 | int labelno; | |
7539 | { | |
8480e480 CC |
7540 | if (DEFAULT_ABI == ABI_AIX) |
7541 | { | |
7542 | char buf[30]; | |
7543 | char *label_name; | |
7544 | rtx fun; | |
411707f4 | 7545 | |
8480e480 | 7546 | labelno += 1; |
411707f4 | 7547 | |
8480e480 CC |
7548 | ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno); |
7549 | STRIP_NAME_ENCODING (label_name, ggc_strdup (buf)); | |
7550 | fun = gen_rtx_SYMBOL_REF (Pmode, label_name); | |
411707f4 | 7551 | |
8480e480 CC |
7552 | emit_library_call (init_one_libfunc (RS6000_MCOUNT), 0, VOIDmode, 1, |
7553 | fun, Pmode); | |
7554 | } | |
ee890fe2 SS |
7555 | else if (DEFAULT_ABI == ABI_DARWIN) |
7556 | { | |
d5fa86ba | 7557 | const char *mcount_name = RS6000_MCOUNT; |
ee890fe2 SS |
7558 | int caller_addr_regno = LINK_REGISTER_REGNUM; |
7559 | ||
7560 | /* Be conservative and always set this, at least for now. */ | |
7561 | current_function_uses_pic_offset_table = 1; | |
7562 | ||
7563 | #if TARGET_MACHO | |
7564 | /* For PIC code, set up a stub and collect the caller's address | |
7565 | from r0, which is where the prologue puts it. */ | |
7566 | if (flag_pic) | |
7567 | { | |
7568 | mcount_name = machopic_stub_name (mcount_name); | |
7569 | if (current_function_uses_pic_offset_table) | |
7570 | caller_addr_regno = 0; | |
7571 | } | |
7572 | #endif | |
7573 | emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mcount_name), | |
7574 | 0, VOIDmode, 1, | |
7575 | gen_rtx_REG (Pmode, caller_addr_regno), Pmode); | |
7576 | } | |
411707f4 CC |
7577 | } |
7578 | ||
e165f3f0 RK |
7579 | /* Write function profiler code. */ |
7580 | ||
7581 | void | |
7582 | output_function_profiler (file, labelno) | |
7583 | FILE *file; | |
7584 | int labelno; | |
7585 | { | |
3daf36a4 | 7586 | char buf[100]; |
e165f3f0 | 7587 | |
3daf36a4 | 7588 | ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno); |
38c1f2d7 | 7589 | switch (DEFAULT_ABI) |
3daf36a4 | 7590 | { |
38c1f2d7 MM |
7591 | default: |
7592 | abort (); | |
7593 | ||
7594 | case ABI_V4: | |
7595 | case ABI_SOLARIS: | |
7596 | case ABI_AIX_NODESC: | |
7597 | fprintf (file, "\tmflr %s\n", reg_names[0]); | |
7598 | if (flag_pic == 1) | |
7599 | { | |
dfdfa60f DE |
7600 | fputs ("\tbl _GLOBAL_OFFSET_TABLE_@local-4\n", file); |
7601 | asm_fprintf (file, "\t{st|stw} %s,4(%s)\n", | |
7602 | reg_names[0], reg_names[1]); | |
17167fd8 | 7603 | asm_fprintf (file, "\tmflr %s\n", reg_names[12]); |
dfdfa60f | 7604 | asm_fprintf (file, "\t{l|lwz} %s,", reg_names[0]); |
38c1f2d7 | 7605 | assemble_name (file, buf); |
17167fd8 | 7606 | asm_fprintf (file, "@got(%s)\n", reg_names[12]); |
38c1f2d7 | 7607 | } |
9ebbca7d | 7608 | else if (flag_pic > 1) |
38c1f2d7 | 7609 | { |
dfdfa60f DE |
7610 | asm_fprintf (file, "\t{st|stw} %s,4(%s)\n", |
7611 | reg_names[0], reg_names[1]); | |
9ebbca7d GK |
7612 | /* Now, we need to get the address of the label. */ |
7613 | fputs ("\tbl 1f\n\t.long ", file); | |
034e84c4 | 7614 | assemble_name (file, buf); |
9ebbca7d GK |
7615 | fputs ("-.\n1:", file); |
7616 | asm_fprintf (file, "\tmflr %s\n", reg_names[11]); | |
7617 | asm_fprintf (file, "\t{l|lwz} %s,0(%s)\n", | |
7618 | reg_names[0], reg_names[11]); | |
7619 | asm_fprintf (file, "\t{cax|add} %s,%s,%s\n", | |
7620 | reg_names[0], reg_names[0], reg_names[11]); | |
38c1f2d7 | 7621 | } |
38c1f2d7 MM |
7622 | else |
7623 | { | |
17167fd8 | 7624 | asm_fprintf (file, "\t{liu|lis} %s,", reg_names[12]); |
38c1f2d7 | 7625 | assemble_name (file, buf); |
dfdfa60f | 7626 | fputs ("@ha\n", file); |
b5253831 DE |
7627 | asm_fprintf (file, "\t{st|stw} %s,4(%s)\n", |
7628 | reg_names[0], reg_names[1]); | |
a260abc9 | 7629 | asm_fprintf (file, "\t{cal|la} %s,", reg_names[0]); |
38c1f2d7 | 7630 | assemble_name (file, buf); |
17167fd8 | 7631 | asm_fprintf (file, "@l(%s)\n", reg_names[12]); |
38c1f2d7 MM |
7632 | } |
7633 | ||
b5253831 DE |
7634 | if (current_function_needs_context) |
7635 | asm_fprintf (file, "\tmr %s,%s\n", | |
7636 | reg_names[30], reg_names[STATIC_CHAIN_REGNUM]); | |
38c1f2d7 | 7637 | fprintf (file, "\tbl %s\n", RS6000_MCOUNT); |
b5253831 DE |
7638 | if (current_function_needs_context) |
7639 | asm_fprintf (file, "\tmr %s,%s\n", | |
7640 | reg_names[STATIC_CHAIN_REGNUM], reg_names[30]); | |
38c1f2d7 MM |
7641 | break; |
7642 | ||
7643 | case ABI_AIX: | |
ee890fe2 | 7644 | case ABI_DARWIN: |
411707f4 | 7645 | /* Don't do anything, done in output_profile_hook (). */ |
38c1f2d7 | 7646 | break; |
411707f4 | 7647 | |
38c1f2d7 | 7648 | } |
e165f3f0 | 7649 | } |
a251ffd0 TG |
7650 | |
7651 | /* Adjust the cost of a scheduling dependency. Return the new cost of | |
7652 | a dependency LINK or INSN on DEP_INSN. COST is the current cost. */ | |
7653 | ||
7654 | int | |
a06faf84 | 7655 | rs6000_adjust_cost (insn, link, dep_insn, cost) |
a251ffd0 TG |
7656 | rtx insn; |
7657 | rtx link; | |
296b8152 | 7658 | rtx dep_insn ATTRIBUTE_UNUSED; |
a251ffd0 TG |
7659 | int cost; |
7660 | { | |
7661 | if (! recog_memoized (insn)) | |
7662 | return 0; | |
7663 | ||
7664 | if (REG_NOTE_KIND (link) != 0) | |
7665 | return 0; | |
7666 | ||
7667 | if (REG_NOTE_KIND (link) == 0) | |
7668 | { | |
7669 | /* Data dependency; DEP_INSN writes a register that INSN reads some | |
7670 | cycles later. */ | |
7671 | ||
7672 | /* Tell the first scheduling pass about the latency between a mtctr | |
7673 | and bctr (and mtlr and br/blr). The first scheduling pass will not | |
7674 | know about this latency since the mtctr instruction, which has the | |
7675 | latency associated to it, will be generated by reload. */ | |
7676 | if (get_attr_type (insn) == TYPE_JMPREG) | |
7677 | return TARGET_POWER ? 5 : 4; | |
7678 | ||
7679 | /* Fall out to return default cost. */ | |
7680 | } | |
7681 | ||
7682 | return cost; | |
7683 | } | |
b6c9286a | 7684 | |
bef84347 VM |
7685 | /* A C statement (sans semicolon) to update the integer scheduling priority |
7686 | INSN_PRIORITY (INSN). Reduce the priority to execute the INSN earlier, | |
7687 | increase the priority to execute INSN later. Do not define this macro if | |
7688 | you do not need to adjust the scheduling priorities of insns. */ | |
7689 | ||
7690 | int | |
7691 | rs6000_adjust_priority (insn, priority) | |
d330fd93 | 7692 | rtx insn ATTRIBUTE_UNUSED; |
bef84347 VM |
7693 | int priority; |
7694 | { | |
7695 | /* On machines (like the 750) which have asymetric integer units, where one | |
7696 | integer unit can do multiply and divides and the other can't, reduce the | |
7697 | priority of multiply/divide so it is scheduled before other integer | |
7698 | operationss. */ | |
7699 | ||
7700 | #if 0 | |
2c3c49de | 7701 | if (! INSN_P (insn)) |
bef84347 VM |
7702 | return priority; |
7703 | ||
7704 | if (GET_CODE (PATTERN (insn)) == USE) | |
7705 | return priority; | |
7706 | ||
7707 | switch (rs6000_cpu_attr) { | |
7708 | case CPU_PPC750: | |
7709 | switch (get_attr_type (insn)) | |
7710 | { | |
7711 | default: | |
7712 | break; | |
7713 | ||
7714 | case TYPE_IMUL: | |
7715 | case TYPE_IDIV: | |
3cb999d8 DE |
7716 | fprintf (stderr, "priority was %#x (%d) before adjustment\n", |
7717 | priority, priority); | |
bef84347 VM |
7718 | if (priority >= 0 && priority < 0x01000000) |
7719 | priority >>= 3; | |
7720 | break; | |
7721 | } | |
7722 | } | |
7723 | #endif | |
7724 | ||
7725 | return priority; | |
7726 | } | |
7727 | ||
b6c9286a MM |
7728 | /* Return how many instructions the machine can issue per cycle */ |
7729 | int get_issue_rate() | |
7730 | { | |
7731 | switch (rs6000_cpu_attr) { | |
3cb999d8 DE |
7732 | case CPU_RIOS1: /* ? */ |
7733 | case CPU_RS64A: | |
7734 | case CPU_PPC601: /* ? */ | |
7735 | return 3; | |
b6c9286a | 7736 | case CPU_PPC603: |
bef84347 VM |
7737 | case CPU_PPC750: |
7738 | return 2; | |
3cb999d8 | 7739 | case CPU_RIOS2: |
b6c9286a | 7740 | case CPU_PPC604: |
19684119 | 7741 | case CPU_PPC604E: |
b6c9286a | 7742 | case CPU_PPC620: |
3cb999d8 | 7743 | case CPU_PPC630: |
b6c9286a MM |
7744 | return 4; |
7745 | default: | |
7746 | return 1; | |
7747 | } | |
7748 | } | |
7749 | ||
b6c9286a | 7750 | \f |
b6c9286a MM |
7751 | /* Length in units of the trampoline for entering a nested function. */ |
7752 | ||
7753 | int | |
7754 | rs6000_trampoline_size () | |
7755 | { | |
7756 | int ret = 0; | |
7757 | ||
7758 | switch (DEFAULT_ABI) | |
7759 | { | |
7760 | default: | |
7761 | abort (); | |
7762 | ||
7763 | case ABI_AIX: | |
8f802bfb | 7764 | ret = (TARGET_32BIT) ? 12 : 24; |
b6c9286a MM |
7765 | break; |
7766 | ||
7767 | case ABI_V4: | |
c81bebd7 | 7768 | case ABI_SOLARIS: |
b6c9286a | 7769 | case ABI_AIX_NODESC: |
03a7e1a5 | 7770 | ret = (TARGET_32BIT) ? 40 : 48; |
b6c9286a | 7771 | break; |
b6c9286a MM |
7772 | } |
7773 | ||
7774 | return ret; | |
7775 | } | |
7776 | ||
7777 | /* Emit RTL insns to initialize the variable parts of a trampoline. | |
7778 | FNADDR is an RTX for the address of the function's pure code. | |
7779 | CXT is an RTX for the static chain value for the function. */ | |
7780 | ||
7781 | void | |
7782 | rs6000_initialize_trampoline (addr, fnaddr, cxt) | |
7783 | rtx addr; | |
7784 | rtx fnaddr; | |
7785 | rtx cxt; | |
7786 | { | |
ac2a93a1 | 7787 | enum machine_mode pmode = Pmode; |
8bd04c56 MM |
7788 | int regsize = (TARGET_32BIT) ? 4 : 8; |
7789 | rtx ctx_reg = force_reg (pmode, cxt); | |
b6c9286a MM |
7790 | |
7791 | switch (DEFAULT_ABI) | |
7792 | { | |
7793 | default: | |
7794 | abort (); | |
7795 | ||
8bd04c56 | 7796 | /* Macros to shorten the code expansions below. */ |
39403d82 | 7797 | #define MEM_DEREF(addr) gen_rtx_MEM (pmode, memory_address (pmode, addr)) |
c5c76735 JL |
7798 | #define MEM_PLUS(addr,offset) \ |
7799 | gen_rtx_MEM (pmode, memory_address (pmode, plus_constant (addr, offset))) | |
7c59dc5d | 7800 | |
b6c9286a MM |
7801 | /* Under AIX, just build the 3 word function descriptor */ |
7802 | case ABI_AIX: | |
8bd04c56 MM |
7803 | { |
7804 | rtx fn_reg = gen_reg_rtx (pmode); | |
7805 | rtx toc_reg = gen_reg_rtx (pmode); | |
7806 | emit_move_insn (fn_reg, MEM_DEREF (fnaddr)); | |
7807 | emit_move_insn (toc_reg, MEM_PLUS (fnaddr, 4)); | |
7808 | emit_move_insn (MEM_DEREF (addr), fn_reg); | |
7809 | emit_move_insn (MEM_PLUS (addr, regsize), toc_reg); | |
7810 | emit_move_insn (MEM_PLUS (addr, 2*regsize), ctx_reg); | |
7811 | } | |
b6c9286a MM |
7812 | break; |
7813 | ||
eaf1bcf1 | 7814 | /* Under V.4/eabi, call __trampoline_setup to do the real work. */ |
b6c9286a | 7815 | case ABI_V4: |
c81bebd7 | 7816 | case ABI_SOLARIS: |
b6c9286a | 7817 | case ABI_AIX_NODESC: |
39403d82 | 7818 | emit_library_call (gen_rtx_SYMBOL_REF (SImode, "__trampoline_setup"), |
eaf1bcf1 MM |
7819 | FALSE, VOIDmode, 4, |
7820 | addr, pmode, | |
7821 | GEN_INT (rs6000_trampoline_size ()), SImode, | |
7822 | fnaddr, pmode, | |
7823 | ctx_reg, pmode); | |
b6c9286a | 7824 | break; |
b6c9286a MM |
7825 | } |
7826 | ||
7827 | return; | |
7828 | } | |
7509c759 MM |
7829 | |
7830 | \f | |
7509c759 MM |
7831 | /* If defined, a C expression whose value is nonzero if IDENTIFIER |
7832 | with arguments ARGS is a valid machine specific attribute for TYPE. | |
7833 | The attributes in ATTRIBUTES have previously been assigned to TYPE. */ | |
7834 | ||
672a6f42 | 7835 | static int |
7509c759 MM |
7836 | rs6000_valid_type_attribute_p (type, attributes, identifier, args) |
7837 | tree type; | |
296b8152 | 7838 | tree attributes ATTRIBUTE_UNUSED; |
7509c759 MM |
7839 | tree identifier; |
7840 | tree args; | |
7841 | { | |
7842 | if (TREE_CODE (type) != FUNCTION_TYPE | |
7843 | && TREE_CODE (type) != FIELD_DECL | |
7844 | && TREE_CODE (type) != TYPE_DECL) | |
7845 | return 0; | |
7846 | ||
6a4cee5f MM |
7847 | /* Longcall attribute says that the function is not within 2**26 bytes |
7848 | of the current function, and to do an indirect call. */ | |
7849 | if (is_attribute_p ("longcall", identifier)) | |
7850 | return (args == NULL_TREE); | |
7851 | ||
7509c759 MM |
7852 | return 0; |
7853 | } | |
7854 | ||
3cb999d8 DE |
7855 | /* Return a reference suitable for calling a function with the |
7856 | longcall attribute. */ | |
6a4cee5f MM |
7857 | struct rtx_def * |
7858 | rs6000_longcall_ref (call_ref) | |
7859 | rtx call_ref; | |
7860 | { | |
d330fd93 | 7861 | const char *call_name; |
6a4cee5f MM |
7862 | tree node; |
7863 | ||
7864 | if (GET_CODE (call_ref) != SYMBOL_REF) | |
7865 | return call_ref; | |
7866 | ||
7867 | /* System V adds '.' to the internal name, so skip them. */ | |
7868 | call_name = XSTR (call_ref, 0); | |
7869 | if (*call_name == '.') | |
7870 | { | |
7871 | while (*call_name == '.') | |
7872 | call_name++; | |
7873 | ||
7874 | node = get_identifier (call_name); | |
39403d82 | 7875 | call_ref = gen_rtx_SYMBOL_REF (VOIDmode, IDENTIFIER_POINTER (node)); |
6a4cee5f MM |
7876 | } |
7877 | ||
7878 | return force_reg (Pmode, call_ref); | |
7879 | } | |
7880 | ||
7509c759 MM |
7881 | \f |
7882 | /* A C statement or statements to switch to the appropriate section | |
7883 | for output of RTX in mode MODE. You can assume that RTX is some | |
7884 | kind of constant in RTL. The argument MODE is redundant except in | |
7885 | the case of a `const_int' rtx. Select the section by calling | |
7886 | `text_section' or one of the alternatives for other sections. | |
7887 | ||
7888 | Do not define this macro if you put all constants in the read-only | |
7889 | data section. */ | |
7890 | ||
7891 | #ifdef USING_SVR4_H | |
7892 | ||
7893 | void | |
7894 | rs6000_select_rtx_section (mode, x) | |
a9098fd0 | 7895 | enum machine_mode mode; |
7509c759 MM |
7896 | rtx x; |
7897 | { | |
a9098fd0 | 7898 | if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode)) |
7509c759 | 7899 | toc_section (); |
7509c759 MM |
7900 | else |
7901 | const_section (); | |
7902 | } | |
7903 | ||
7904 | /* A C statement or statements to switch to the appropriate | |
7905 | section for output of DECL. DECL is either a `VAR_DECL' node | |
7906 | or a constant of some sort. RELOC indicates whether forming | |
7907 | the initial value of DECL requires link-time relocations. */ | |
7908 | ||
7909 | void | |
7910 | rs6000_select_section (decl, reloc) | |
7911 | tree decl; | |
7912 | int reloc; | |
7913 | { | |
7914 | int size = int_size_in_bytes (TREE_TYPE (decl)); | |
63019373 GK |
7915 | int needs_sdata; |
7916 | int readonly; | |
7917 | static void (* const sec_funcs[4]) PARAMS ((void)) = { | |
7918 | &const_section, | |
7919 | &sdata2_section, | |
7920 | &data_section, | |
7921 | &sdata_section | |
7922 | }; | |
7923 | ||
7924 | needs_sdata = (size > 0 | |
7925 | && size <= g_switch_value | |
7926 | && rs6000_sdata != SDATA_NONE | |
7927 | && (rs6000_sdata != SDATA_DATA || TREE_PUBLIC (decl))); | |
7509c759 MM |
7928 | |
7929 | if (TREE_CODE (decl) == STRING_CST) | |
63019373 | 7930 | readonly = ! flag_writable_strings; |
a9098fd0 | 7931 | else if (TREE_CODE (decl) == VAR_DECL) |
63019373 GK |
7932 | readonly = (! (flag_pic && reloc) |
7933 | && TREE_READONLY (decl) | |
7934 | && ! TREE_SIDE_EFFECTS (decl) | |
7935 | && DECL_INITIAL (decl) | |
7936 | && DECL_INITIAL (decl) != error_mark_node | |
7937 | && TREE_CONSTANT (DECL_INITIAL (decl))); | |
7509c759 | 7938 | else |
63019373 GK |
7939 | readonly = 1; |
7940 | if (needs_sdata && rs6000_sdata != SDATA_EABI) | |
7941 | readonly = 0; | |
7942 | ||
7943 | (*sec_funcs[(readonly ? 0 : 2) + (needs_sdata ? 1 : 0)])(); | |
7944 | } | |
7945 | ||
7946 | /* A C statement to build up a unique section name, expressed as a | |
7947 | STRING_CST node, and assign it to DECL_SECTION_NAME (decl). | |
7948 | RELOC indicates whether the initial value of EXP requires | |
7949 | link-time relocations. If you do not define this macro, GCC will use | |
7950 | the symbol name prefixed by `.' as the section name. Note - this | |
7951 | macro can now be called for unitialised data items as well as | |
7952 | initialised data and functions. */ | |
7953 | ||
7954 | void | |
7955 | rs6000_unique_section (decl, reloc) | |
7956 | tree decl; | |
7957 | int reloc; | |
7958 | { | |
7959 | int size = int_size_in_bytes (TREE_TYPE (decl)); | |
7960 | int needs_sdata; | |
7961 | int readonly; | |
7962 | int len; | |
7963 | int sec; | |
7964 | const char *name; | |
7965 | char *string; | |
7966 | const char *prefix; | |
7967 | ||
7968 | static const char *const prefixes[7][2] = | |
7969 | { | |
7970 | { ".text.", ".gnu.linkonce.t." }, | |
7971 | { ".rodata.", ".gnu.linkonce.r." }, | |
7972 | { ".sdata2.", ".gnu.linkonce.s2." }, | |
7973 | { ".data.", ".gnu.linkonce.d." }, | |
7974 | { ".sdata.", ".gnu.linkonce.s." }, | |
7975 | { ".bss.", ".gnu.linkonce.b." }, | |
7976 | { ".sbss.", ".gnu.linkonce.sb." } | |
7977 | }; | |
7978 | ||
7979 | needs_sdata = (TREE_CODE (decl) != FUNCTION_DECL | |
7980 | && size > 0 | |
7981 | && size <= g_switch_value | |
7982 | && rs6000_sdata != SDATA_NONE | |
7983 | && (rs6000_sdata != SDATA_DATA || TREE_PUBLIC (decl))); | |
7984 | ||
7985 | if (TREE_CODE (decl) == STRING_CST) | |
7986 | readonly = ! flag_writable_strings; | |
7987 | else if (TREE_CODE (decl) == VAR_DECL) | |
7988 | readonly = (! (flag_pic && reloc) | |
7989 | && TREE_READONLY (decl) | |
7990 | && ! TREE_SIDE_EFFECTS (decl) | |
7991 | && DECL_INITIAL (decl) | |
7992 | && DECL_INITIAL (decl) != error_mark_node | |
7993 | && TREE_CONSTANT (DECL_INITIAL (decl))); | |
7994 | else | |
7995 | readonly = 1; | |
7996 | if (needs_sdata && rs6000_sdata != SDATA_EABI) | |
7997 | readonly = 0; | |
7998 | ||
7999 | sec = ((TREE_CODE (decl) == FUNCTION_DECL ? 0 : 1) | |
8000 | + (readonly ? 0 : 2) | |
8001 | + (needs_sdata ? 1 : 0) | |
8002 | + (DECL_INITIAL (decl) == 0 | |
8003 | || DECL_INITIAL (decl) == error_mark_node) ? 4 : 0); | |
8004 | ||
e6978109 | 8005 | STRIP_NAME_ENCODING (name, IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl))); |
63019373 GK |
8006 | prefix = prefixes[sec][DECL_ONE_ONLY (decl)]; |
8007 | len = strlen (name) + strlen (prefix); | |
8008 | string = alloca (len + 1); | |
8009 | ||
8010 | sprintf (string, "%s%s", prefix, name); | |
8011 | ||
8012 | DECL_SECTION_NAME (decl) = build_string (len, string); | |
7509c759 | 8013 | } |
d9407988 MM |
8014 | |
8015 | \f | |
d9407988 MM |
8016 | /* If we are referencing a function that is static or is known to be |
8017 | in this file, make the SYMBOL_REF special. We can use this to indicate | |
8018 | that we can branch to this function without emitting a no-op after the | |
9ebbca7d | 8019 | call. For real AIX calling sequences, we also replace the |
d9407988 MM |
8020 | function name with the real name (1 or 2 leading .'s), rather than |
8021 | the function descriptor name. This saves a lot of overriding code | |
a260abc9 | 8022 | to read the prefixes. */ |
d9407988 MM |
8023 | |
8024 | void | |
8025 | rs6000_encode_section_info (decl) | |
8026 | tree decl; | |
8027 | { | |
8028 | if (TREE_CODE (decl) == FUNCTION_DECL) | |
8029 | { | |
8030 | rtx sym_ref = XEXP (DECL_RTL (decl), 0); | |
8f1b829e | 8031 | if ((TREE_ASM_WRITTEN (decl) || ! TREE_PUBLIC (decl)) |
c81fc13e | 8032 | && ! DECL_WEAK (decl)) |
d9407988 MM |
8033 | SYMBOL_REF_FLAG (sym_ref) = 1; |
8034 | ||
9ebbca7d | 8035 | if (DEFAULT_ABI == ABI_AIX) |
d9407988 | 8036 | { |
ff669a6c RH |
8037 | size_t len1 = (DEFAULT_ABI == ABI_AIX) ? 1 : 2; |
8038 | size_t len2 = strlen (XSTR (sym_ref, 0)); | |
520a57c8 | 8039 | char *str = alloca (len1 + len2 + 1); |
ff669a6c RH |
8040 | str[0] = '.'; |
8041 | str[1] = '.'; | |
8042 | memcpy (str + len1, XSTR (sym_ref, 0), len2 + 1); | |
8043 | ||
520a57c8 | 8044 | XSTR (sym_ref, 0) = ggc_alloc_string (str, len1 + len2); |
d9407988 MM |
8045 | } |
8046 | } | |
8047 | else if (rs6000_sdata != SDATA_NONE | |
8048 | && (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) | |
8049 | && TREE_CODE (decl) == VAR_DECL) | |
8050 | { | |
8051 | int size = int_size_in_bytes (TREE_TYPE (decl)); | |
8052 | tree section_name = DECL_SECTION_NAME (decl); | |
d330fd93 | 8053 | const char *name = (char *)0; |
d9407988 MM |
8054 | int len = 0; |
8055 | ||
8056 | if (section_name) | |
8057 | { | |
8058 | if (TREE_CODE (section_name) == STRING_CST) | |
8059 | { | |
8060 | name = TREE_STRING_POINTER (section_name); | |
8061 | len = TREE_STRING_LENGTH (section_name); | |
8062 | } | |
8063 | else | |
8064 | abort (); | |
8065 | } | |
8066 | ||
8067 | if ((size > 0 && size <= g_switch_value) | |
8068 | || (name | |
5f59ecb7 | 8069 | && ((len == sizeof (".sdata") - 1 |
3cb999d8 | 8070 | && strcmp (name, ".sdata") == 0) |
5f59ecb7 | 8071 | || (len == sizeof (".sdata2") - 1 |
3cb999d8 | 8072 | && strcmp (name, ".sdata2") == 0) |
5f59ecb7 | 8073 | || (len == sizeof (".sbss") - 1 |
3cb999d8 | 8074 | && strcmp (name, ".sbss") == 0) |
5f59ecb7 | 8075 | || (len == sizeof (".sbss2") - 1 |
3cb999d8 | 8076 | && strcmp (name, ".sbss2") == 0) |
5f59ecb7 | 8077 | || (len == sizeof (".PPC.EMB.sdata0") - 1 |
3cb999d8 | 8078 | && strcmp (name, ".PPC.EMB.sdata0") == 0) |
5f59ecb7 | 8079 | || (len == sizeof (".PPC.EMB.sbss0") - 1 |
3cb999d8 | 8080 | && strcmp (name, ".PPC.EMB.sbss0") == 0)))) |
d9407988 MM |
8081 | { |
8082 | rtx sym_ref = XEXP (DECL_RTL (decl), 0); | |
ff669a6c | 8083 | size_t len = strlen (XSTR (sym_ref, 0)); |
88c1e412 | 8084 | char *str = alloca (len + 2); |
ff669a6c | 8085 | |
ff669a6c RH |
8086 | str[0] = '@'; |
8087 | memcpy (str + 1, XSTR (sym_ref, 0), len + 1); | |
88c1e412 | 8088 | XSTR (sym_ref, 0) = ggc_alloc_string (str, len + 1); |
d9407988 MM |
8089 | } |
8090 | } | |
8091 | } | |
8092 | ||
7509c759 | 8093 | #endif /* USING_SVR4_H */ |
000034eb | 8094 | |
a6c2a102 | 8095 | \f |
000034eb | 8096 | /* Return a REG that occurs in ADDR with coefficient 1. |
02441cd6 JL |
8097 | ADDR can be effectively incremented by incrementing REG. |
8098 | ||
8099 | r0 is special and we must not select it as an address | |
8100 | register by this routine since our caller will try to | |
8101 | increment the returned register via an "la" instruction. */ | |
000034eb DE |
8102 | |
8103 | struct rtx_def * | |
8104 | find_addr_reg (addr) | |
8105 | rtx addr; | |
8106 | { | |
8107 | while (GET_CODE (addr) == PLUS) | |
8108 | { | |
02441cd6 JL |
8109 | if (GET_CODE (XEXP (addr, 0)) == REG |
8110 | && REGNO (XEXP (addr, 0)) != 0) | |
000034eb | 8111 | addr = XEXP (addr, 0); |
02441cd6 JL |
8112 | else if (GET_CODE (XEXP (addr, 1)) == REG |
8113 | && REGNO (XEXP (addr, 1)) != 0) | |
000034eb DE |
8114 | addr = XEXP (addr, 1); |
8115 | else if (CONSTANT_P (XEXP (addr, 0))) | |
8116 | addr = XEXP (addr, 1); | |
8117 | else if (CONSTANT_P (XEXP (addr, 1))) | |
8118 | addr = XEXP (addr, 0); | |
8119 | else | |
8120 | abort (); | |
8121 | } | |
02441cd6 | 8122 | if (GET_CODE (addr) == REG && REGNO (addr) != 0) |
000034eb DE |
8123 | return addr; |
8124 | abort (); | |
8125 | } | |
8126 | ||
a6c2a102 DE |
8127 | void |
8128 | rs6000_fatal_bad_address (op) | |
8129 | rtx op; | |
8130 | { | |
8131 | fatal_insn ("bad address", op); | |
8132 | } | |
c8023011 MM |
8133 | |
8134 | /* Called to register all of our global variables with the garbage | |
8135 | collector. */ | |
8136 | ||
8137 | static void | |
8138 | rs6000_add_gc_roots () | |
8139 | { | |
8140 | ggc_add_rtx_root (&rs6000_compare_op0, 1); | |
8141 | ggc_add_rtx_root (&rs6000_compare_op1, 1); | |
9ebbca7d GK |
8142 | |
8143 | toc_hash_table = htab_create (1021, toc_hash_function, toc_hash_eq, NULL); | |
8144 | ggc_add_root (&toc_hash_table, 1, sizeof (toc_hash_table), | |
8145 | toc_hash_mark_table); | |
ee890fe2 SS |
8146 | |
8147 | #if TARGET_MACHO | |
8148 | machopic_add_gc_roots (); | |
8149 | #endif | |
8150 | } | |
8151 | ||
8152 | #if TARGET_MACHO | |
8153 | ||
8154 | #if 0 | |
8155 | /* Returns 1 if OP is either a symbol reference or a sum of a symbol | |
8156 | reference and a constant. */ | |
8157 | ||
8158 | int | |
8159 | symbolic_operand (op) | |
8160 | register rtx op; | |
8161 | { | |
8162 | switch (GET_CODE (op)) | |
8163 | { | |
8164 | case SYMBOL_REF: | |
8165 | case LABEL_REF: | |
8166 | return 1; | |
8167 | case CONST: | |
8168 | op = XEXP (op, 0); | |
8169 | return (GET_CODE (op) == SYMBOL_REF || | |
8170 | (GET_CODE (XEXP (op, 0)) == SYMBOL_REF | |
8171 | || GET_CODE (XEXP (op, 0)) == LABEL_REF) | |
8172 | && GET_CODE (XEXP (op, 1)) == CONST_INT); | |
8173 | default: | |
8174 | return 0; | |
8175 | } | |
c8023011 | 8176 | } |
ee890fe2 SS |
8177 | #endif |
8178 | ||
8179 | #ifdef RS6000_LONG_BRANCH | |
8180 | ||
8181 | static tree stub_list = 0; | |
8182 | ||
8183 | /* ADD_COMPILER_STUB adds the compiler generated stub for handling | |
8184 | procedure calls to the linked list. */ | |
8185 | ||
8186 | void | |
8187 | add_compiler_stub (label_name, function_name, line_number) | |
8188 | tree label_name; | |
8189 | tree function_name; | |
8190 | int line_number; | |
8191 | { | |
8192 | tree stub = build_tree_list (function_name, label_name); | |
8193 | TREE_TYPE (stub) = build_int_2 (line_number, 0); | |
8194 | TREE_CHAIN (stub) = stub_list; | |
8195 | stub_list = stub; | |
8196 | } | |
8197 | ||
8198 | #define STUB_LABEL_NAME(STUB) TREE_VALUE (STUB) | |
8199 | #define STUB_FUNCTION_NAME(STUB) TREE_PURPOSE (STUB) | |
8200 | #define STUB_LINE_NUMBER(STUB) TREE_INT_CST_LOW (TREE_TYPE (STUB)) | |
8201 | ||
8202 | /* OUTPUT_COMPILER_STUB outputs the compiler generated stub for handling | |
8203 | procedure calls from the linked list and initializes the linked list. */ | |
8204 | ||
8205 | void output_compiler_stub () | |
8206 | { | |
8207 | char tmp_buf[256]; | |
8208 | char label_buf[256]; | |
8209 | char *label; | |
8210 | tree tmp_stub, stub; | |
8211 | ||
8212 | if (!flag_pic) | |
8213 | for (stub = stub_list; stub; stub = TREE_CHAIN (stub)) | |
8214 | { | |
8215 | fprintf (asm_out_file, | |
8216 | "%s:\n", IDENTIFIER_POINTER(STUB_LABEL_NAME(stub))); | |
8217 | ||
8218 | #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO) | |
8219 | if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG) | |
8220 | fprintf (asm_out_file, "\t.stabd 68,0,%d\n", STUB_LINE_NUMBER(stub)); | |
8221 | #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */ | |
8222 | ||
8223 | if (IDENTIFIER_POINTER (STUB_FUNCTION_NAME (stub))[0] == '*') | |
8224 | strcpy (label_buf, | |
8225 | IDENTIFIER_POINTER (STUB_FUNCTION_NAME (stub))+1); | |
8226 | else | |
8227 | { | |
8228 | label_buf[0] = '_'; | |
8229 | strcpy (label_buf+1, | |
8230 | IDENTIFIER_POINTER (STUB_FUNCTION_NAME (stub))); | |
8231 | } | |
8232 | ||
8233 | strcpy (tmp_buf, "lis r12,hi16("); | |
8234 | strcat (tmp_buf, label_buf); | |
8235 | strcat (tmp_buf, ")\n\tori r12,r12,lo16("); | |
8236 | strcat (tmp_buf, label_buf); | |
8237 | strcat (tmp_buf, ")\n\tmtctr r12\n\tbctr"); | |
8238 | output_asm_insn (tmp_buf, 0); | |
8239 | ||
8240 | #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO) | |
8241 | if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG) | |
8242 | fprintf(asm_out_file, "\t.stabd 68,0,%d\n", STUB_LINE_NUMBER (stub)); | |
8243 | #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */ | |
8244 | } | |
8245 | ||
8246 | stub_list = 0; | |
8247 | } | |
8248 | ||
8249 | /* NO_PREVIOUS_DEF checks in the link list whether the function name is | |
8250 | already there or not. */ | |
8251 | ||
8252 | int no_previous_def (function_name) | |
8253 | tree function_name; | |
8254 | { | |
8255 | tree stub; | |
8256 | for (stub = stub_list; stub; stub = TREE_CHAIN (stub)) | |
8257 | if (function_name == STUB_FUNCTION_NAME (stub)) | |
8258 | return 0; | |
8259 | return 1; | |
8260 | } | |
8261 | ||
8262 | /* GET_PREV_LABEL gets the label name from the previous definition of | |
8263 | the function. */ | |
8264 | ||
8265 | tree get_prev_label (function_name) | |
8266 | tree function_name; | |
8267 | { | |
8268 | tree stub; | |
8269 | for (stub = stub_list; stub; stub = TREE_CHAIN (stub)) | |
8270 | if (function_name == STUB_FUNCTION_NAME (stub)) | |
8271 | return STUB_LABEL_NAME (stub); | |
8272 | return 0; | |
8273 | } | |
8274 | ||
8275 | /* INSN is either a function call or a millicode call. It may have an | |
8276 | unconditional jump in its delay slot. | |
8277 | ||
8278 | CALL_DEST is the routine we are calling. */ | |
8279 | ||
8280 | char * | |
8281 | output_call (insn, call_dest, operand_number) | |
8282 | rtx insn; | |
8283 | rtx call_dest; | |
8284 | int operand_number; | |
8285 | { | |
8286 | static char buf[256]; | |
8287 | if (GET_CODE (call_dest) == SYMBOL_REF && TARGET_LONG_BRANCH && !flag_pic) | |
8288 | { | |
8289 | tree labelname; | |
8290 | tree funname = get_identifier (XSTR (call_dest, 0)); | |
8291 | ||
8292 | if (no_previous_def (funname)) | |
8293 | { | |
8294 | int line_number; | |
8295 | rtx label_rtx = gen_label_rtx (); | |
8296 | char *label_buf, temp_buf[256]; | |
8297 | ASM_GENERATE_INTERNAL_LABEL (temp_buf, "L", | |
8298 | CODE_LABEL_NUMBER (label_rtx)); | |
8299 | label_buf = temp_buf[0] == '*' ? temp_buf + 1 : temp_buf; | |
8300 | labelname = get_identifier (label_buf); | |
8301 | for (; insn && GET_CODE (insn) != NOTE; insn = PREV_INSN (insn)); | |
8302 | if (insn) | |
8303 | line_number = NOTE_LINE_NUMBER (insn); | |
8304 | add_compiler_stub (labelname, funname, line_number); | |
8305 | } | |
8306 | else | |
8307 | labelname = get_prev_label (funname); | |
8308 | ||
8309 | sprintf (buf, "jbsr %%z%d,%.246s", | |
8310 | operand_number, IDENTIFIER_POINTER (labelname)); | |
8311 | return buf; | |
8312 | } | |
8313 | else | |
8314 | { | |
8315 | sprintf (buf, "bl %%z%d", operand_number); | |
8316 | return buf; | |
8317 | } | |
8318 | } | |
8319 | ||
8320 | #endif /* RS6000_LONG_BRANCH */ | |
8321 | ||
8322 | #define GEN_LOCAL_LABEL_FOR_SYMBOL(BUF,SYMBOL,LENGTH,N) \ | |
8323 | do { \ | |
8324 | const char *symbol_ = (SYMBOL); \ | |
8325 | char *buffer_ = (BUF); \ | |
8326 | if (symbol_[0] == '"') \ | |
8327 | { \ | |
8328 | sprintf(buffer_, "\"L%d$%s", (N), symbol_+1); \ | |
8329 | } \ | |
8330 | else if (name_needs_quotes(symbol_)) \ | |
8331 | { \ | |
8332 | sprintf(buffer_, "\"L%d$%s\"", (N), symbol_); \ | |
8333 | } \ | |
8334 | else \ | |
8335 | { \ | |
8336 | sprintf(buffer_, "L%d$%s", (N), symbol_); \ | |
8337 | } \ | |
8338 | } while (0) | |
8339 | ||
8340 | ||
8341 | /* Generate PIC and indirect symbol stubs. */ | |
8342 | ||
8343 | void | |
8344 | machopic_output_stub (file, symb, stub) | |
8345 | FILE *file; | |
8346 | const char *symb, *stub; | |
8347 | { | |
8348 | unsigned int length; | |
8349 | char *binder_name, *symbol_name, *lazy_ptr_name; | |
8350 | char *local_label_0, *local_label_1, *local_label_2; | |
8351 | static int label = 0; | |
8352 | ||
df56a27f SS |
8353 | /* Lose our funky encoding stuff so it doesn't contaminate the stub. */ |
8354 | STRIP_NAME_ENCODING (symb, symb); | |
8355 | ||
ee890fe2 SS |
8356 | label += 1; |
8357 | ||
8358 | length = strlen (stub); | |
8359 | binder_name = alloca (length + 32); | |
8360 | GEN_BINDER_NAME_FOR_STUB (binder_name, stub, length); | |
8361 | ||
8362 | length = strlen (symb); | |
8363 | symbol_name = alloca (length + 32); | |
8364 | GEN_SYMBOL_NAME_FOR_SYMBOL (symbol_name, symb, length); | |
8365 | ||
8366 | lazy_ptr_name = alloca (length + 32); | |
8367 | GEN_LAZY_PTR_NAME_FOR_SYMBOL (lazy_ptr_name, symb, length); | |
8368 | ||
8369 | local_label_0 = alloca (length + 32); | |
8370 | GEN_LOCAL_LABEL_FOR_SYMBOL (local_label_0, symb, length, 0); | |
8371 | ||
8372 | local_label_1 = alloca (length + 32); | |
8373 | GEN_LOCAL_LABEL_FOR_SYMBOL (local_label_1, symb, length, 1); | |
8374 | ||
8375 | local_label_2 = alloca (length + 32); | |
8376 | GEN_LOCAL_LABEL_FOR_SYMBOL (local_label_2, symb, length, 2); | |
8377 | ||
8378 | if (flag_pic == 2) | |
8379 | machopic_picsymbol_stub_section (); | |
8380 | else | |
8381 | machopic_symbol_stub_section (); | |
8382 | ||
8383 | fprintf (file, "%s:\n", stub); | |
8384 | fprintf (file, "\t.indirect_symbol %s\n", symbol_name); | |
8385 | ||
8386 | if (flag_pic == 2) | |
8387 | { | |
8388 | fprintf (file, "\tmflr r0\n"); | |
8389 | fprintf (file, "\tbcl 20,31,%s\n", local_label_0); | |
8390 | fprintf (file, "%s:\n\tmflr r11\n", local_label_0); | |
8391 | fprintf (file, "\taddis r11,r11,ha16(%s-%s)\n", | |
8392 | lazy_ptr_name, local_label_0); | |
8393 | fprintf (file, "\tmtlr r0\n"); | |
8394 | fprintf (file, "\tlwz r12,lo16(%s-%s)(r11)\n", | |
8395 | lazy_ptr_name, local_label_0); | |
8396 | fprintf (file, "\tmtctr r12\n"); | |
8397 | fprintf (file, "\taddi r11,r11,lo16(%s-%s)\n", | |
8398 | lazy_ptr_name, local_label_0); | |
8399 | fprintf (file, "\tbctr\n"); | |
8400 | } | |
8401 | else | |
8402 | fprintf (file, "non-pure not supported\n"); | |
8403 | ||
8404 | machopic_lazy_symbol_ptr_section (); | |
8405 | fprintf (file, "%s:\n", lazy_ptr_name); | |
8406 | fprintf (file, "\t.indirect_symbol %s\n", symbol_name); | |
8407 | fprintf (file, "\t.long dyld_stub_binding_helper\n"); | |
8408 | } | |
8409 | ||
8410 | /* Legitimize PIC addresses. If the address is already | |
8411 | position-independent, we return ORIG. Newly generated | |
8412 | position-independent addresses go into a reg. This is REG if non | |
8413 | zero, otherwise we allocate register(s) as necessary. */ | |
8414 | ||
8415 | #define SMALL_INT(X) ((unsigned) (INTVAL(X) + 0x4000) < 0x8000) | |
8416 | ||
8417 | rtx | |
8418 | rs6000_machopic_legitimize_pic_address (orig, mode, reg) | |
8419 | rtx orig; | |
8420 | enum machine_mode mode; | |
8421 | rtx reg; | |
8422 | { | |
8423 | rtx base, offset; | |
8424 | ||
8425 | if (reg == NULL && ! reload_in_progress && ! reload_completed) | |
8426 | reg = gen_reg_rtx (Pmode); | |
8427 | ||
8428 | if (GET_CODE (orig) == CONST) | |
8429 | { | |
8430 | if (GET_CODE (XEXP (orig, 0)) == PLUS | |
8431 | && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx) | |
8432 | return orig; | |
8433 | ||
8434 | if (GET_CODE (XEXP (orig, 0)) == PLUS) | |
8435 | { | |
8436 | base = rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 0), | |
8437 | Pmode, reg); | |
8438 | offset = rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 1), | |
8439 | Pmode, reg); | |
8440 | } | |
8441 | else | |
8442 | abort (); | |
8443 | ||
8444 | if (GET_CODE (offset) == CONST_INT) | |
8445 | { | |
8446 | if (SMALL_INT (offset)) | |
ed8908e7 | 8447 | return plus_constant (base, INTVAL (offset)); |
ee890fe2 SS |
8448 | else if (! reload_in_progress && ! reload_completed) |
8449 | offset = force_reg (Pmode, offset); | |
8450 | else | |
8451 | abort (); | |
8452 | } | |
8453 | return gen_rtx (PLUS, Pmode, base, offset); | |
8454 | } | |
8455 | ||
8456 | /* Fall back on generic machopic code. */ | |
8457 | return machopic_legitimize_pic_address (orig, mode, reg); | |
8458 | } | |
8459 | ||
8460 | /* This is just a placeholder to make linking work without having to | |
8461 | add this to the generic Darwin EXTRA_SECTIONS. If -mcall-aix is | |
8462 | ever needed for Darwin (not too likely!) this would have to get a | |
8463 | real definition. */ | |
8464 | ||
8465 | void | |
8466 | toc_section () | |
8467 | { | |
8468 | } | |
8469 | ||
8470 | #endif /* TARGET_MACHO */ |