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9878760c | 1 | /* Subroutines used for code generation on IBM RS/6000. |
9ebbca7d | 2 | Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, |
63b6e069 | 3 | 2000, 2001 Free Software Foundation, Inc. |
fab3bcc3 | 4 | Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu) |
9878760c RK |
5 | |
6 | This file is part of GNU CC. | |
7 | ||
8 | GNU CC is free software; you can redistribute it and/or modify | |
9 | it under the terms of the GNU General Public License as published by | |
10 | the Free Software Foundation; either version 2, or (at your option) | |
11 | any later version. | |
12 | ||
13 | GNU CC is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
19 | along with GNU CC; see the file COPYING. If not, write to | |
c15c9075 RK |
20 | the Free Software Foundation, 59 Temple Place - Suite 330, |
21 | Boston, MA 02111-1307, USA. */ | |
9878760c | 22 | |
956d6950 | 23 | #include "config.h" |
c4d38ccb | 24 | #include "system.h" |
9878760c RK |
25 | #include "rtl.h" |
26 | #include "regs.h" | |
27 | #include "hard-reg-set.h" | |
28 | #include "real.h" | |
29 | #include "insn-config.h" | |
30 | #include "conditions.h" | |
9878760c RK |
31 | #include "insn-attr.h" |
32 | #include "flags.h" | |
33 | #include "recog.h" | |
9878760c | 34 | #include "obstack.h" |
9b30bae2 | 35 | #include "tree.h" |
dfafc897 | 36 | #include "expr.h" |
2fc1c679 | 37 | #include "optabs.h" |
2a430ec1 | 38 | #include "except.h" |
a7df97e6 | 39 | #include "function.h" |
296b8152 | 40 | #include "output.h" |
d5fa86ba | 41 | #include "basic-block.h" |
d0101753 | 42 | #include "integrate.h" |
296b8152 | 43 | #include "toplev.h" |
c8023011 | 44 | #include "ggc.h" |
9ebbca7d GK |
45 | #include "hashtab.h" |
46 | #include "tm_p.h" | |
672a6f42 NB |
47 | #include "target.h" |
48 | #include "target-def.h" | |
9b30bae2 | 49 | |
7509c759 MM |
50 | #ifndef TARGET_NO_PROTOTYPE |
51 | #define TARGET_NO_PROTOTYPE 0 | |
52 | #endif | |
53 | ||
5248c961 | 54 | extern int profile_block_flag; |
9878760c RK |
55 | |
56 | #define min(A,B) ((A) < (B) ? (A) : (B)) | |
57 | #define max(A,B) ((A) > (B) ? (A) : (B)) | |
58 | ||
5248c961 RK |
59 | /* Target cpu type */ |
60 | ||
61 | enum processor_type rs6000_cpu; | |
8e3f41e7 MM |
62 | struct rs6000_cpu_select rs6000_select[3] = |
63 | { | |
815cdc52 MM |
64 | /* switch name, tune arch */ |
65 | { (const char *)0, "--with-cpu=", 1, 1 }, | |
66 | { (const char *)0, "-mcpu=", 1, 1 }, | |
67 | { (const char *)0, "-mtune=", 1, 0 }, | |
8e3f41e7 | 68 | }; |
5248c961 | 69 | |
c764f757 RK |
70 | /* Set to non-zero once AIX common-mode calls have been defined. */ |
71 | static int common_mode_defined; | |
c81bebd7 | 72 | |
9878760c RK |
73 | /* Save information from a "cmpxx" operation until the branch or scc is |
74 | emitted. */ | |
9878760c RK |
75 | rtx rs6000_compare_op0, rs6000_compare_op1; |
76 | int rs6000_compare_fp_p; | |
874a0744 | 77 | |
874a0744 MM |
78 | /* Label number of label created for -mrelocatable, to call to so we can |
79 | get the address of the GOT section */ | |
80 | int rs6000_pic_labelno; | |
c81bebd7 | 81 | |
9ebbca7d | 82 | #ifdef USING_SVR4_H |
c81bebd7 | 83 | /* Which abi to adhere to */ |
815cdc52 | 84 | const char *rs6000_abi_name = RS6000_ABI_NAME; |
d9407988 MM |
85 | |
86 | /* Semantics of the small data area */ | |
87 | enum rs6000_sdata_type rs6000_sdata = SDATA_DATA; | |
88 | ||
89 | /* Which small data model to use */ | |
815cdc52 | 90 | const char *rs6000_sdata_name = (char *)0; |
9ebbca7d GK |
91 | |
92 | /* Counter for labels which are to be placed in .fixup. */ | |
93 | int fixuplabelno = 0; | |
874a0744 | 94 | #endif |
4697a36c | 95 | |
b6c9286a MM |
96 | /* ABI enumeration available for subtarget to use. */ |
97 | enum rs6000_abi rs6000_current_abi; | |
98 | ||
38c1f2d7 | 99 | /* Debug flags */ |
815cdc52 | 100 | const char *rs6000_debug_name; |
38c1f2d7 MM |
101 | int rs6000_debug_stack; /* debug stack applications */ |
102 | int rs6000_debug_arg; /* debug argument handling */ | |
103 | ||
104 | /* Flag to say the TOC is initialized */ | |
105 | int toc_initialized; | |
9ebbca7d | 106 | char toc_label_name[10]; |
38c1f2d7 | 107 | |
9ebbca7d GK |
108 | /* Alias set for saves and restores from the rs6000 stack. */ |
109 | static int rs6000_sr_alias_set; | |
c8023011 | 110 | |
9ebbca7d GK |
111 | static void rs6000_add_gc_roots PARAMS ((void)); |
112 | static int num_insns_constant_wide PARAMS ((HOST_WIDE_INT)); | |
113 | static rtx expand_block_move_mem PARAMS ((enum machine_mode, rtx, rtx)); | |
39a10a29 GK |
114 | static void validate_condition_mode |
115 | PARAMS ((enum rtx_code, enum machine_mode)); | |
116 | static rtx rs6000_generate_compare PARAMS ((enum rtx_code)); | |
e50f5f3d | 117 | static void rs6000_maybe_dead PARAMS ((rtx)); |
9ebbca7d GK |
118 | static void rs6000_emit_stack_tie PARAMS ((void)); |
119 | static void rs6000_frame_related PARAMS ((rtx, rtx, HOST_WIDE_INT, rtx, rtx)); | |
120 | static void rs6000_emit_allocate_stack PARAMS ((HOST_WIDE_INT, int)); | |
121 | static unsigned rs6000_hash_constant PARAMS ((rtx)); | |
122 | static unsigned toc_hash_function PARAMS ((const void *)); | |
123 | static int toc_hash_eq PARAMS ((const void *, const void *)); | |
2eba1afa | 124 | static int toc_hash_mark_entry PARAMS ((void **, void *)); |
9ebbca7d GK |
125 | static void toc_hash_mark_table PARAMS ((void *)); |
126 | static int constant_pool_expr_1 PARAMS ((rtx, int *, int *)); | |
6fee9e99 NC |
127 | static void rs6000_free_machine_status PARAMS ((struct function *)); |
128 | static void rs6000_init_machine_status PARAMS ((struct function *)); | |
71f123ca | 129 | static int rs6000_ra_ever_killed PARAMS ((void)); |
672a6f42 | 130 | static int rs6000_valid_type_attribute_p PARAMS ((tree, tree, tree, tree)); |
08c148a8 NB |
131 | static void rs6000_output_function_prologue PARAMS ((FILE *, HOST_WIDE_INT)); |
132 | static void rs6000_output_function_epilogue PARAMS ((FILE *, HOST_WIDE_INT)); | |
2bfcf297 DB |
133 | static rtx rs6000_emit_set_long_const PARAMS ((rtx, |
134 | HOST_WIDE_INT, HOST_WIDE_INT)); | |
7c262518 RH |
135 | #if TARGET_ELF |
136 | static unsigned int rs6000_elf_section_type_flags PARAMS ((tree, const char *, | |
137 | int)); | |
d9f6800d RH |
138 | static void rs6000_elf_asm_out_constructor PARAMS ((rtx, int)); |
139 | static void rs6000_elf_asm_out_destructor PARAMS ((rtx, int)); | |
7c262518 RH |
140 | #endif |
141 | #ifdef OBJECT_FORMAT_COFF | |
715bdd29 | 142 | static void xcoff_asm_named_section PARAMS ((const char *, unsigned int)); |
7c262518 | 143 | #endif |
c81bebd7 MM |
144 | \f |
145 | /* Default register names. */ | |
146 | char rs6000_reg_names[][8] = | |
147 | { | |
802a0058 MM |
148 | "0", "1", "2", "3", "4", "5", "6", "7", |
149 | "8", "9", "10", "11", "12", "13", "14", "15", | |
150 | "16", "17", "18", "19", "20", "21", "22", "23", | |
151 | "24", "25", "26", "27", "28", "29", "30", "31", | |
152 | "0", "1", "2", "3", "4", "5", "6", "7", | |
153 | "8", "9", "10", "11", "12", "13", "14", "15", | |
154 | "16", "17", "18", "19", "20", "21", "22", "23", | |
155 | "24", "25", "26", "27", "28", "29", "30", "31", | |
156 | "mq", "lr", "ctr","ap", | |
157 | "0", "1", "2", "3", "4", "5", "6", "7", | |
9ebbca7d | 158 | "xer" |
c81bebd7 MM |
159 | }; |
160 | ||
161 | #ifdef TARGET_REGNAMES | |
162 | static char alt_reg_names[][8] = | |
163 | { | |
802a0058 MM |
164 | "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7", |
165 | "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15", | |
166 | "%r16", "%r17", "%r18", "%r19", "%r20", "%r21", "%r22", "%r23", | |
167 | "%r24", "%r25", "%r26", "%r27", "%r28", "%r29", "%r30", "%r31", | |
168 | "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7", | |
169 | "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15", | |
170 | "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23", | |
171 | "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31", | |
172 | "mq", "lr", "ctr", "ap", | |
173 | "%cr0", "%cr1", "%cr2", "%cr3", "%cr4", "%cr5", "%cr6", "%cr7", | |
9ebbca7d | 174 | "xer" |
c81bebd7 MM |
175 | }; |
176 | #endif | |
9878760c | 177 | \f |
daf11973 MM |
178 | #ifndef MASK_STRICT_ALIGN |
179 | #define MASK_STRICT_ALIGN 0 | |
180 | #endif | |
672a6f42 NB |
181 | \f |
182 | /* Initialize the GCC target structure. */ | |
183 | #undef TARGET_VALID_TYPE_ATTRIBUTE | |
184 | #define TARGET_VALID_TYPE_ATTRIBUTE rs6000_valid_type_attribute_p | |
daf11973 | 185 | |
08c148a8 NB |
186 | #undef TARGET_ASM_FUNCTION_PROLOGUE |
187 | #define TARGET_ASM_FUNCTION_PROLOGUE rs6000_output_function_prologue | |
188 | #undef TARGET_ASM_FUNCTION_EPILOGUE | |
189 | #define TARGET_ASM_FUNCTION_EPILOGUE rs6000_output_function_epilogue | |
190 | ||
7c262518 RH |
191 | #if TARGET_ELF |
192 | #undef TARGET_SECTION_TYPE_FLAGS | |
193 | #define TARGET_SECTION_TYPE_FLAGS rs6000_elf_section_type_flags | |
194 | #endif | |
195 | ||
f6897b10 | 196 | struct gcc_target targetm = TARGET_INITIALIZER; |
672a6f42 | 197 | \f |
5248c961 RK |
198 | /* Override command line options. Mostly we process the processor |
199 | type and sometimes adjust other TARGET_ options. */ | |
200 | ||
201 | void | |
8e3f41e7 | 202 | rs6000_override_options (default_cpu) |
d330fd93 | 203 | const char *default_cpu; |
5248c961 | 204 | { |
c4d38ccb | 205 | size_t i, j; |
8e3f41e7 | 206 | struct rs6000_cpu_select *ptr; |
5248c961 | 207 | |
85638c0d RK |
208 | /* Simplify the entries below by making a mask for any POWER |
209 | variant and any PowerPC variant. */ | |
210 | ||
938937d8 | 211 | #define POWER_MASKS (MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING) |
68c49ffa RK |
212 | #define POWERPC_MASKS (MASK_POWERPC | MASK_PPC_GPOPT \ |
213 | | MASK_PPC_GFXOPT | MASK_POWERPC64) | |
214 | #define POWERPC_OPT_MASKS (MASK_PPC_GPOPT | MASK_PPC_GFXOPT) | |
85638c0d | 215 | |
5248c961 RK |
216 | static struct ptt |
217 | { | |
d330fd93 | 218 | const char *name; /* Canonical processor name. */ |
5248c961 RK |
219 | enum processor_type processor; /* Processor type enum value. */ |
220 | int target_enable; /* Target flags to enable. */ | |
221 | int target_disable; /* Target flags to disable. */ | |
222 | } processor_target_table[] | |
cf27b467 MM |
223 | = {{"common", PROCESSOR_COMMON, MASK_NEW_MNEMONICS, |
224 | POWER_MASKS | POWERPC_MASKS}, | |
db7f1e43 | 225 | {"power", PROCESSOR_POWER, |
938937d8 | 226 | MASK_POWER | MASK_MULTIPLE | MASK_STRING, |
db7f1e43 | 227 | MASK_POWER2 | POWERPC_MASKS | MASK_NEW_MNEMONICS}, |
8e3f41e7 MM |
228 | {"power2", PROCESSOR_POWER, |
229 | MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING, | |
230 | POWERPC_MASKS | MASK_NEW_MNEMONICS}, | |
c71791e0 DE |
231 | {"power3", PROCESSOR_PPC630, |
232 | MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS, | |
233 | POWER_MASKS | MASK_PPC_GPOPT}, | |
db7f1e43 RK |
234 | {"powerpc", PROCESSOR_POWERPC, |
235 | MASK_POWERPC | MASK_NEW_MNEMONICS, | |
68c49ffa | 236 | POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64}, |
3cb999d8 DE |
237 | {"powerpc64", PROCESSOR_POWERPC64, |
238 | MASK_POWERPC | MASK_POWERPC64 | MASK_NEW_MNEMONICS, | |
239 | POWER_MASKS | POWERPC_OPT_MASKS}, | |
db7f1e43 | 240 | {"rios", PROCESSOR_RIOS1, |
938937d8 | 241 | MASK_POWER | MASK_MULTIPLE | MASK_STRING, |
db7f1e43 RK |
242 | MASK_POWER2 | POWERPC_MASKS | MASK_NEW_MNEMONICS}, |
243 | {"rios1", PROCESSOR_RIOS1, | |
938937d8 | 244 | MASK_POWER | MASK_MULTIPLE | MASK_STRING, |
db7f1e43 RK |
245 | MASK_POWER2 | POWERPC_MASKS | MASK_NEW_MNEMONICS}, |
246 | {"rsc", PROCESSOR_PPC601, | |
938937d8 | 247 | MASK_POWER | MASK_MULTIPLE | MASK_STRING, |
db7f1e43 RK |
248 | MASK_POWER2 | POWERPC_MASKS | MASK_NEW_MNEMONICS}, |
249 | {"rsc1", PROCESSOR_PPC601, | |
938937d8 | 250 | MASK_POWER | MASK_MULTIPLE | MASK_STRING, |
db7f1e43 RK |
251 | MASK_POWER2 | POWERPC_MASKS | MASK_NEW_MNEMONICS}, |
252 | {"rios2", PROCESSOR_RIOS2, | |
938937d8 | 253 | MASK_POWER | MASK_MULTIPLE | MASK_STRING | MASK_POWER2, |
db7f1e43 | 254 | POWERPC_MASKS | MASK_NEW_MNEMONICS}, |
3cb999d8 DE |
255 | {"rs64a", PROCESSOR_RS64A, |
256 | MASK_POWERPC | MASK_NEW_MNEMONICS, | |
257 | POWER_MASKS | POWERPC_OPT_MASKS}, | |
a3a1dbf6 MM |
258 | {"401", PROCESSOR_PPC403, |
259 | MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS, | |
260 | POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64}, | |
49a0b204 | 261 | {"403", PROCESSOR_PPC403, |
daf11973 | 262 | MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS | MASK_STRICT_ALIGN, |
49a0b204 | 263 | POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64}, |
cf27b467 MM |
264 | {"505", PROCESSOR_MPCCORE, |
265 | MASK_POWERPC | MASK_NEW_MNEMONICS, | |
266 | POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64}, | |
5248c961 | 267 | {"601", PROCESSOR_PPC601, |
938937d8 | 268 | MASK_POWER | MASK_POWERPC | MASK_NEW_MNEMONICS | MASK_MULTIPLE | MASK_STRING, |
68c49ffa | 269 | MASK_POWER2 | POWERPC_OPT_MASKS | MASK_POWERPC64}, |
1ec26da6 | 270 | {"602", PROCESSOR_PPC603, |
cf27b467 MM |
271 | MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS, |
272 | POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64}, | |
5248c961 | 273 | {"603", PROCESSOR_PPC603, |
68c49ffa RK |
274 | MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS, |
275 | POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64}, | |
b6c9286a MM |
276 | {"603e", PROCESSOR_PPC603, |
277 | MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS, | |
278 | POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64}, | |
b5370a88 | 279 | {"ec603e", PROCESSOR_PPC603, |
a3a1dbf6 MM |
280 | MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS, |
281 | POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64}, | |
5248c961 | 282 | {"604", PROCESSOR_PPC604, |
b6c9286a MM |
283 | MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS, |
284 | POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64}, | |
cac8ce95 | 285 | {"604e", PROCESSOR_PPC604e, |
07e6159a MM |
286 | MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS, |
287 | POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64}, | |
b6c9286a | 288 | {"620", PROCESSOR_PPC620, |
68c49ffa | 289 | MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS, |
a260abc9 | 290 | POWER_MASKS | MASK_PPC_GPOPT}, |
3cb999d8 DE |
291 | {"630", PROCESSOR_PPC630, |
292 | MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS, | |
293 | POWER_MASKS | MASK_PPC_GPOPT}, | |
bef84347 VM |
294 | {"740", PROCESSOR_PPC750, |
295 | MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS, | |
296 | POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64}, | |
297 | {"750", PROCESSOR_PPC750, | |
298 | MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS, | |
299 | POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64}, | |
07e6159a MM |
300 | {"801", PROCESSOR_MPCCORE, |
301 | MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS, | |
302 | POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64}, | |
cf27b467 MM |
303 | {"821", PROCESSOR_MPCCORE, |
304 | MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS, | |
305 | POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64}, | |
07e6159a MM |
306 | {"823", PROCESSOR_MPCCORE, |
307 | MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS, | |
308 | POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64}, | |
cf27b467 MM |
309 | {"860", PROCESSOR_MPCCORE, |
310 | MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS, | |
311 | POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64}}; | |
5248c961 | 312 | |
c4d38ccb | 313 | size_t ptt_size = sizeof (processor_target_table) / sizeof (struct ptt); |
5248c961 | 314 | |
8a61d227 | 315 | int multiple = TARGET_MULTIPLE; /* save current -mmultiple/-mno-multiple status */ |
938937d8 | 316 | int string = TARGET_STRING; /* save current -mstring/-mno-string status */ |
8a61d227 | 317 | |
5248c961 RK |
318 | profile_block_flag = 0; |
319 | ||
320 | /* Identify the processor type */ | |
8e3f41e7 | 321 | rs6000_select[0].string = default_cpu; |
3cb999d8 | 322 | rs6000_cpu = TARGET_POWERPC64 ? PROCESSOR_DEFAULT64 : PROCESSOR_DEFAULT; |
8e3f41e7 | 323 | |
b6a1cbae | 324 | for (i = 0; i < ARRAY_SIZE (rs6000_select); i++) |
5248c961 | 325 | { |
8e3f41e7 MM |
326 | ptr = &rs6000_select[i]; |
327 | if (ptr->string != (char *)0 && ptr->string[0] != '\0') | |
5248c961 | 328 | { |
8e3f41e7 MM |
329 | for (j = 0; j < ptt_size; j++) |
330 | if (! strcmp (ptr->string, processor_target_table[j].name)) | |
331 | { | |
332 | if (ptr->set_tune_p) | |
333 | rs6000_cpu = processor_target_table[j].processor; | |
334 | ||
335 | if (ptr->set_arch_p) | |
336 | { | |
337 | target_flags |= processor_target_table[j].target_enable; | |
338 | target_flags &= ~processor_target_table[j].target_disable; | |
339 | } | |
340 | break; | |
341 | } | |
342 | ||
4406229e | 343 | if (j == ptt_size) |
8e3f41e7 | 344 | error ("bad value (%s) for %s switch", ptr->string, ptr->name); |
5248c961 RK |
345 | } |
346 | } | |
8a61d227 | 347 | |
ef792183 MM |
348 | /* If we are optimizing big endian systems for space, use the |
349 | store multiple instructions. */ | |
350 | if (BYTES_BIG_ENDIAN && optimize_size) | |
351 | target_flags |= MASK_MULTIPLE; | |
352 | ||
8a61d227 MM |
353 | /* If -mmultiple or -mno-multiple was explicitly used, don't |
354 | override with the processor default */ | |
355 | if (TARGET_MULTIPLE_SET) | |
356 | target_flags = (target_flags & ~MASK_MULTIPLE) | multiple; | |
7e69e155 | 357 | |
938937d8 MM |
358 | /* If -mstring or -mno-string was explicitly used, don't |
359 | override with the processor default */ | |
360 | if (TARGET_STRING_SET) | |
1f5515bf | 361 | target_flags = (target_flags & ~MASK_STRING) | string; |
938937d8 | 362 | |
bef84347 VM |
363 | /* Don't allow -mmultiple or -mstring on little endian systems unless the cpu |
364 | is a 750, because the hardware doesn't support the instructions used in | |
365 | little endian mode, and causes an alignment trap. The 750 does not cause | |
366 | an alignment trap (except when the target is unaligned). */ | |
367 | ||
bfc79d3b | 368 | if (! BYTES_BIG_ENDIAN && rs6000_cpu != PROCESSOR_PPC750) |
7e69e155 MM |
369 | { |
370 | if (TARGET_MULTIPLE) | |
371 | { | |
372 | target_flags &= ~MASK_MULTIPLE; | |
373 | if (TARGET_MULTIPLE_SET) | |
374 | warning ("-mmultiple is not supported on little endian systems"); | |
375 | } | |
376 | ||
377 | if (TARGET_STRING) | |
378 | { | |
379 | target_flags &= ~MASK_STRING; | |
938937d8 MM |
380 | if (TARGET_STRING_SET) |
381 | warning ("-mstring is not supported on little endian systems"); | |
7e69e155 MM |
382 | } |
383 | } | |
3933e0e1 | 384 | |
2bfcf297 | 385 | if (flag_pic && DEFAULT_ABI == ABI_AIX) |
a260abc9 | 386 | { |
2bfcf297 | 387 | warning ("-f%s ignored (all code is position independent)", |
a260abc9 DE |
388 | (flag_pic > 1) ? "PIC" : "pic"); |
389 | flag_pic = 0; | |
390 | } | |
391 | ||
2bfcf297 | 392 | #ifdef XCOFF_DEBUGGING_INFO |
9861b0c9 | 393 | if (flag_function_sections && (write_symbols != NO_DEBUG) |
2bfcf297 | 394 | && DEFAULT_ABI == ABI_AIX) |
9861b0c9 DE |
395 | { |
396 | warning ("-ffunction-sections disabled on AIX when debugging"); | |
397 | flag_function_sections = 0; | |
398 | } | |
399 | ||
400 | if (flag_data_sections && (DEFAULT_ABI == ABI_AIX)) | |
401 | { | |
402 | warning ("-fdata-sections not supported on AIX"); | |
403 | flag_data_sections = 0; | |
404 | } | |
2bfcf297 | 405 | #endif |
9861b0c9 | 406 | |
38c1f2d7 MM |
407 | /* Set debug flags */ |
408 | if (rs6000_debug_name) | |
409 | { | |
bfc79d3b | 410 | if (! strcmp (rs6000_debug_name, "all")) |
38c1f2d7 | 411 | rs6000_debug_stack = rs6000_debug_arg = 1; |
bfc79d3b | 412 | else if (! strcmp (rs6000_debug_name, "stack")) |
38c1f2d7 | 413 | rs6000_debug_stack = 1; |
bfc79d3b | 414 | else if (! strcmp (rs6000_debug_name, "arg")) |
38c1f2d7 MM |
415 | rs6000_debug_arg = 1; |
416 | else | |
417 | error ("Unknown -mdebug-%s switch", rs6000_debug_name); | |
418 | } | |
419 | ||
c81bebd7 MM |
420 | #ifdef TARGET_REGNAMES |
421 | /* If the user desires alternate register names, copy in the alternate names | |
422 | now. */ | |
423 | if (TARGET_REGNAMES) | |
4e135bdd | 424 | memcpy (rs6000_reg_names, alt_reg_names, sizeof (rs6000_reg_names)); |
c81bebd7 MM |
425 | #endif |
426 | ||
3933e0e1 MM |
427 | #ifdef SUBTARGET_OVERRIDE_OPTIONS |
428 | SUBTARGET_OVERRIDE_OPTIONS; | |
429 | #endif | |
c8023011 MM |
430 | |
431 | /* Register global variables with the garbage collector. */ | |
432 | rs6000_add_gc_roots (); | |
9ebbca7d GK |
433 | |
434 | /* Allocate an alias set for register saves & restores from stack. */ | |
435 | rs6000_sr_alias_set = new_alias_set (); | |
436 | ||
437 | if (TARGET_TOC) | |
438 | ASM_GENERATE_INTERNAL_LABEL (toc_label_name, "LCTOC", 1); | |
71f123ca FS |
439 | |
440 | /* Arrange to save and restore machine status around nested functions. */ | |
441 | init_machine_status = rs6000_init_machine_status; | |
71f123ca | 442 | free_machine_status = rs6000_free_machine_status; |
5248c961 | 443 | } |
5accd822 DE |
444 | |
445 | void | |
446 | optimization_options (level, size) | |
e2c953b6 | 447 | int level ATTRIBUTE_UNUSED; |
5accd822 DE |
448 | int size ATTRIBUTE_UNUSED; |
449 | { | |
5accd822 | 450 | } |
3cfa4909 MM |
451 | \f |
452 | /* Do anything needed at the start of the asm file. */ | |
453 | ||
454 | void | |
455 | rs6000_file_start (file, default_cpu) | |
456 | FILE *file; | |
d330fd93 | 457 | const char *default_cpu; |
3cfa4909 | 458 | { |
c4d38ccb | 459 | size_t i; |
3cfa4909 | 460 | char buffer[80]; |
d330fd93 | 461 | const char *start = buffer; |
3cfa4909 MM |
462 | struct rs6000_cpu_select *ptr; |
463 | ||
464 | if (flag_verbose_asm) | |
465 | { | |
466 | sprintf (buffer, "\n%s rs6000/powerpc options:", ASM_COMMENT_START); | |
467 | rs6000_select[0].string = default_cpu; | |
468 | ||
b6a1cbae | 469 | for (i = 0; i < ARRAY_SIZE (rs6000_select); i++) |
3cfa4909 MM |
470 | { |
471 | ptr = &rs6000_select[i]; | |
472 | if (ptr->string != (char *)0 && ptr->string[0] != '\0') | |
473 | { | |
474 | fprintf (file, "%s %s%s", start, ptr->name, ptr->string); | |
475 | start = ""; | |
476 | } | |
477 | } | |
478 | ||
479 | #ifdef USING_SVR4_H | |
480 | switch (rs6000_sdata) | |
481 | { | |
482 | case SDATA_NONE: fprintf (file, "%s -msdata=none", start); start = ""; break; | |
483 | case SDATA_DATA: fprintf (file, "%s -msdata=data", start); start = ""; break; | |
484 | case SDATA_SYSV: fprintf (file, "%s -msdata=sysv", start); start = ""; break; | |
485 | case SDATA_EABI: fprintf (file, "%s -msdata=eabi", start); start = ""; break; | |
486 | } | |
487 | ||
488 | if (rs6000_sdata && g_switch_value) | |
489 | { | |
490 | fprintf (file, "%s -G %d", start, g_switch_value); | |
491 | start = ""; | |
492 | } | |
493 | #endif | |
494 | ||
495 | if (*start == '\0') | |
949ea356 | 496 | putc ('\n', file); |
3cfa4909 MM |
497 | } |
498 | } | |
499 | ||
24d304eb RK |
500 | \f |
501 | /* Create a CONST_DOUBLE from a string. */ | |
502 | ||
503 | struct rtx_def * | |
504 | rs6000_float_const (string, mode) | |
d330fd93 | 505 | const char *string; |
24d304eb RK |
506 | enum machine_mode mode; |
507 | { | |
ca5adc63 GK |
508 | REAL_VALUE_TYPE value; |
509 | value = REAL_VALUE_ATOF (string, mode); | |
24d304eb RK |
510 | return immed_real_const_1 (value, mode); |
511 | } | |
5248c961 | 512 | \f |
9878760c RK |
513 | /* Return non-zero if this function is known to have a null epilogue. */ |
514 | ||
515 | int | |
516 | direct_return () | |
517 | { | |
4697a36c MM |
518 | if (reload_completed) |
519 | { | |
520 | rs6000_stack_t *info = rs6000_stack_info (); | |
521 | ||
522 | if (info->first_gp_reg_save == 32 | |
523 | && info->first_fp_reg_save == 64 | |
c81fc13e DE |
524 | && ! info->lr_save_p |
525 | && ! info->cr_save_p | |
526 | && ! info->push_p) | |
4697a36c MM |
527 | return 1; |
528 | } | |
529 | ||
530 | return 0; | |
9878760c RK |
531 | } |
532 | ||
533 | /* Returns 1 always. */ | |
534 | ||
535 | int | |
536 | any_operand (op, mode) | |
296b8152 KG |
537 | register rtx op ATTRIBUTE_UNUSED; |
538 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
9878760c RK |
539 | { |
540 | return 1; | |
541 | } | |
542 | ||
b6c9286a | 543 | /* Returns 1 if op is the count register */ |
38c1f2d7 MM |
544 | int |
545 | count_register_operand(op, mode) | |
b6c9286a | 546 | register rtx op; |
296b8152 | 547 | enum machine_mode mode ATTRIBUTE_UNUSED; |
b6c9286a MM |
548 | { |
549 | if (GET_CODE (op) != REG) | |
550 | return 0; | |
551 | ||
552 | if (REGNO (op) == COUNT_REGISTER_REGNUM) | |
553 | return 1; | |
554 | ||
555 | if (REGNO (op) > FIRST_PSEUDO_REGISTER) | |
556 | return 1; | |
557 | ||
558 | return 0; | |
559 | } | |
560 | ||
38c1f2d7 | 561 | int |
9ebbca7d | 562 | xer_operand(op, mode) |
802a0058 | 563 | register rtx op; |
296b8152 | 564 | enum machine_mode mode ATTRIBUTE_UNUSED; |
802a0058 MM |
565 | { |
566 | if (GET_CODE (op) != REG) | |
567 | return 0; | |
568 | ||
9ebbca7d | 569 | if (XER_REGNO_P (REGNO (op))) |
802a0058 MM |
570 | return 1; |
571 | ||
802a0058 MM |
572 | return 0; |
573 | } | |
574 | ||
9878760c RK |
575 | /* Return 1 if OP is a constant that can fit in a D field. */ |
576 | ||
577 | int | |
578 | short_cint_operand (op, mode) | |
579 | register rtx op; | |
296b8152 | 580 | enum machine_mode mode ATTRIBUTE_UNUSED; |
9878760c | 581 | { |
5f59ecb7 DE |
582 | return (GET_CODE (op) == CONST_INT |
583 | && CONST_OK_FOR_LETTER_P (INTVAL (op), 'I')); | |
9878760c RK |
584 | } |
585 | ||
586 | /* Similar for a unsigned D field. */ | |
587 | ||
588 | int | |
589 | u_short_cint_operand (op, mode) | |
590 | register rtx op; | |
296b8152 | 591 | enum machine_mode mode ATTRIBUTE_UNUSED; |
9878760c | 592 | { |
19684119 | 593 | return (GET_CODE (op) == CONST_INT |
5f59ecb7 | 594 | && CONST_OK_FOR_LETTER_P (INTVAL (op), 'K')); |
9878760c RK |
595 | } |
596 | ||
dcfedcd0 RK |
597 | /* Return 1 if OP is a CONST_INT that cannot fit in a signed D field. */ |
598 | ||
599 | int | |
600 | non_short_cint_operand (op, mode) | |
601 | register rtx op; | |
296b8152 | 602 | enum machine_mode mode ATTRIBUTE_UNUSED; |
dcfedcd0 RK |
603 | { |
604 | return (GET_CODE (op) == CONST_INT | |
a7653a2c | 605 | && (unsigned HOST_WIDE_INT) (INTVAL (op) + 0x8000) >= 0x10000); |
dcfedcd0 RK |
606 | } |
607 | ||
2bfcf297 DB |
608 | /* Returns 1 if OP is a CONST_INT that is a positive value |
609 | and an exact power of 2. */ | |
610 | ||
611 | int | |
612 | exact_log2_cint_operand (op, mode) | |
613 | register rtx op; | |
614 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
615 | { | |
616 | return (GET_CODE (op) == CONST_INT | |
617 | && INTVAL (op) > 0 | |
618 | && exact_log2 (INTVAL (op)) >= 0); | |
619 | } | |
620 | ||
9878760c RK |
621 | /* Returns 1 if OP is a register that is not special (i.e., not MQ, |
622 | ctr, or lr). */ | |
623 | ||
624 | int | |
cd2b37d9 | 625 | gpc_reg_operand (op, mode) |
9878760c RK |
626 | register rtx op; |
627 | enum machine_mode mode; | |
628 | { | |
629 | return (register_operand (op, mode) | |
802a0058 | 630 | && (GET_CODE (op) != REG |
9ebbca7d GK |
631 | || (REGNO (op) >= ARG_POINTER_REGNUM |
632 | && !XER_REGNO_P (REGNO (op))) | |
633 | || REGNO (op) < MQ_REGNO)); | |
9878760c RK |
634 | } |
635 | ||
636 | /* Returns 1 if OP is either a pseudo-register or a register denoting a | |
637 | CR field. */ | |
638 | ||
639 | int | |
640 | cc_reg_operand (op, mode) | |
641 | register rtx op; | |
642 | enum machine_mode mode; | |
643 | { | |
644 | return (register_operand (op, mode) | |
645 | && (GET_CODE (op) != REG | |
646 | || REGNO (op) >= FIRST_PSEUDO_REGISTER | |
647 | || CR_REGNO_P (REGNO (op)))); | |
648 | } | |
649 | ||
815cdc52 MM |
650 | /* Returns 1 if OP is either a pseudo-register or a register denoting a |
651 | CR field that isn't CR0. */ | |
652 | ||
653 | int | |
654 | cc_reg_not_cr0_operand (op, mode) | |
655 | register rtx op; | |
656 | enum machine_mode mode; | |
657 | { | |
658 | return (register_operand (op, mode) | |
659 | && (GET_CODE (op) != REG | |
660 | || REGNO (op) >= FIRST_PSEUDO_REGISTER | |
661 | || CR_REGNO_NOT_CR0_P (REGNO (op)))); | |
662 | } | |
663 | ||
9878760c RK |
664 | /* Returns 1 if OP is either a constant integer valid for a D-field or a |
665 | non-special register. If a register, it must be in the proper mode unless | |
666 | MODE is VOIDmode. */ | |
667 | ||
668 | int | |
669 | reg_or_short_operand (op, mode) | |
670 | register rtx op; | |
671 | enum machine_mode mode; | |
672 | { | |
f5a28898 | 673 | return short_cint_operand (op, mode) || gpc_reg_operand (op, mode); |
9878760c RK |
674 | } |
675 | ||
676 | /* Similar, except check if the negation of the constant would be valid for | |
677 | a D-field. */ | |
678 | ||
679 | int | |
680 | reg_or_neg_short_operand (op, mode) | |
681 | register rtx op; | |
682 | enum machine_mode mode; | |
683 | { | |
684 | if (GET_CODE (op) == CONST_INT) | |
685 | return CONST_OK_FOR_LETTER_P (INTVAL (op), 'P'); | |
686 | ||
cd2b37d9 | 687 | return gpc_reg_operand (op, mode); |
9878760c RK |
688 | } |
689 | ||
690 | /* Return 1 if the operand is either a register or an integer whose high-order | |
691 | 16 bits are zero. */ | |
692 | ||
693 | int | |
694 | reg_or_u_short_operand (op, mode) | |
695 | register rtx op; | |
696 | enum machine_mode mode; | |
697 | { | |
e675f625 | 698 | return u_short_cint_operand (op, mode) || gpc_reg_operand (op, mode); |
9878760c RK |
699 | } |
700 | ||
701 | /* Return 1 is the operand is either a non-special register or ANY | |
702 | constant integer. */ | |
703 | ||
704 | int | |
705 | reg_or_cint_operand (op, mode) | |
706 | register rtx op; | |
707 | enum machine_mode mode; | |
708 | { | |
f6bf7de2 DE |
709 | return (GET_CODE (op) == CONST_INT || gpc_reg_operand (op, mode)); |
710 | } | |
711 | ||
712 | /* Return 1 is the operand is either a non-special register or ANY | |
713 | 32-bit signed constant integer. */ | |
714 | ||
715 | int | |
716 | reg_or_arith_cint_operand (op, mode) | |
717 | register rtx op; | |
718 | enum machine_mode mode; | |
719 | { | |
720 | return (gpc_reg_operand (op, mode) | |
721 | || (GET_CODE (op) == CONST_INT | |
722 | #if HOST_BITS_PER_WIDE_INT != 32 | |
723 | && ((unsigned HOST_WIDE_INT) (INTVAL (op) + 0x80000000) | |
78e1b90d | 724 | < (unsigned HOST_WIDE_INT) 0x100000000ll) |
f6bf7de2 DE |
725 | #endif |
726 | )); | |
9878760c RK |
727 | } |
728 | ||
2bfcf297 DB |
729 | /* Return 1 is the operand is either a non-special register or a 32-bit |
730 | signed constant integer valid for 64-bit addition. */ | |
731 | ||
732 | int | |
733 | reg_or_add_cint64_operand (op, mode) | |
734 | register rtx op; | |
735 | enum machine_mode mode; | |
736 | { | |
737 | return (gpc_reg_operand (op, mode) | |
738 | || (GET_CODE (op) == CONST_INT | |
739 | && INTVAL (op) < 0x7fff8000 | |
740 | #if HOST_BITS_PER_WIDE_INT != 32 | |
741 | && ((unsigned HOST_WIDE_INT) (INTVAL (op) + 0x80008000) | |
742 | < 0x100000000ll) | |
743 | #endif | |
744 | )); | |
745 | } | |
746 | ||
747 | /* Return 1 is the operand is either a non-special register or a 32-bit | |
748 | signed constant integer valid for 64-bit subtraction. */ | |
749 | ||
750 | int | |
751 | reg_or_sub_cint64_operand (op, mode) | |
752 | register rtx op; | |
753 | enum machine_mode mode; | |
754 | { | |
755 | return (gpc_reg_operand (op, mode) | |
756 | || (GET_CODE (op) == CONST_INT | |
757 | && (- INTVAL (op)) < 0x7fff8000 | |
758 | #if HOST_BITS_PER_WIDE_INT != 32 | |
759 | && ((unsigned HOST_WIDE_INT) ((- INTVAL (op)) + 0x80008000) | |
760 | < 0x100000000ll) | |
761 | #endif | |
762 | )); | |
763 | } | |
764 | ||
9ebbca7d GK |
765 | /* Return 1 is the operand is either a non-special register or ANY |
766 | 32-bit unsigned constant integer. */ | |
767 | ||
768 | int | |
1d328b19 | 769 | reg_or_logical_cint_operand (op, mode) |
9ebbca7d GK |
770 | register rtx op; |
771 | enum machine_mode mode; | |
772 | { | |
1d328b19 GK |
773 | if (GET_CODE (op) == CONST_INT) |
774 | { | |
775 | if (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT) | |
776 | { | |
777 | if (GET_MODE_BITSIZE (mode) <= 32) | |
778 | abort(); | |
779 | ||
780 | if (INTVAL (op) < 0) | |
781 | return 0; | |
782 | } | |
783 | ||
784 | return ((INTVAL (op) & GET_MODE_MASK (mode) | |
0858c623 | 785 | & (~ (unsigned HOST_WIDE_INT) 0xffffffff)) == 0); |
1d328b19 GK |
786 | } |
787 | else if (GET_CODE (op) == CONST_DOUBLE) | |
788 | { | |
789 | if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT | |
790 | || mode != DImode) | |
791 | abort(); | |
792 | ||
793 | return CONST_DOUBLE_HIGH (op) == 0; | |
794 | } | |
795 | else | |
796 | return gpc_reg_operand (op, mode); | |
9ebbca7d GK |
797 | } |
798 | ||
766a866c MM |
799 | /* Return 1 if the operand is an operand that can be loaded via the GOT */ |
800 | ||
801 | int | |
802 | got_operand (op, mode) | |
803 | register rtx op; | |
296b8152 | 804 | enum machine_mode mode ATTRIBUTE_UNUSED; |
766a866c MM |
805 | { |
806 | return (GET_CODE (op) == SYMBOL_REF | |
807 | || GET_CODE (op) == CONST | |
808 | || GET_CODE (op) == LABEL_REF); | |
809 | } | |
810 | ||
38c1f2d7 MM |
811 | /* Return 1 if the operand is a simple references that can be loaded via |
812 | the GOT (labels involving addition aren't allowed). */ | |
813 | ||
814 | int | |
815 | got_no_const_operand (op, mode) | |
816 | register rtx op; | |
296b8152 | 817 | enum machine_mode mode ATTRIBUTE_UNUSED; |
38c1f2d7 MM |
818 | { |
819 | return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF); | |
820 | } | |
821 | ||
4e74d8ec MM |
822 | /* Return the number of instructions it takes to form a constant in an |
823 | integer register. */ | |
824 | ||
825 | static int | |
826 | num_insns_constant_wide (value) | |
827 | HOST_WIDE_INT value; | |
828 | { | |
829 | /* signed constant loadable with {cal|addi} */ | |
5f59ecb7 | 830 | if (CONST_OK_FOR_LETTER_P (value, 'I')) |
0865c631 GK |
831 | return 1; |
832 | ||
4e74d8ec | 833 | /* constant loadable with {cau|addis} */ |
5f59ecb7 | 834 | else if (CONST_OK_FOR_LETTER_P (value, 'L')) |
4e74d8ec MM |
835 | return 1; |
836 | ||
5f59ecb7 | 837 | #if HOST_BITS_PER_WIDE_INT == 64 |
c81fc13e | 838 | else if (TARGET_POWERPC64) |
4e74d8ec | 839 | { |
0d30d435 | 840 | HOST_WIDE_INT low = value & 0xffffffff; |
4e74d8ec MM |
841 | HOST_WIDE_INT high = value >> 32; |
842 | ||
0d30d435 DE |
843 | low = (low ^ 0x80000000) - 0x80000000; /* sign extend */ |
844 | ||
0858c623 | 845 | if (high == 0 && (low & 0x80000000) == 0) |
4e74d8ec MM |
846 | return 2; |
847 | ||
0858c623 | 848 | else if (high == -1 && (low & 0x80000000) != 0) |
4e74d8ec MM |
849 | return 2; |
850 | ||
c81fc13e | 851 | else if (! low) |
4e74d8ec MM |
852 | return num_insns_constant_wide (high) + 1; |
853 | ||
854 | else | |
855 | return (num_insns_constant_wide (high) | |
e396202a | 856 | + num_insns_constant_wide (low) + 1); |
4e74d8ec MM |
857 | } |
858 | #endif | |
859 | ||
860 | else | |
861 | return 2; | |
862 | } | |
863 | ||
864 | int | |
865 | num_insns_constant (op, mode) | |
866 | rtx op; | |
867 | enum machine_mode mode; | |
868 | { | |
4e74d8ec | 869 | if (GET_CODE (op) == CONST_INT) |
0d30d435 DE |
870 | { |
871 | #if HOST_BITS_PER_WIDE_INT == 64 | |
872 | if (mask64_operand (op, mode)) | |
873 | return 2; | |
874 | else | |
875 | #endif | |
876 | return num_insns_constant_wide (INTVAL (op)); | |
877 | } | |
4e74d8ec | 878 | |
6fc48950 MM |
879 | else if (GET_CODE (op) == CONST_DOUBLE && mode == SFmode) |
880 | { | |
881 | long l; | |
882 | REAL_VALUE_TYPE rv; | |
883 | ||
884 | REAL_VALUE_FROM_CONST_DOUBLE (rv, op); | |
885 | REAL_VALUE_TO_TARGET_SINGLE (rv, l); | |
886 | return num_insns_constant_wide ((HOST_WIDE_INT)l); | |
887 | } | |
888 | ||
47ad8c61 | 889 | else if (GET_CODE (op) == CONST_DOUBLE) |
4e74d8ec | 890 | { |
47ad8c61 MM |
891 | HOST_WIDE_INT low; |
892 | HOST_WIDE_INT high; | |
893 | long l[2]; | |
894 | REAL_VALUE_TYPE rv; | |
895 | int endian = (WORDS_BIG_ENDIAN == 0); | |
4e74d8ec | 896 | |
47ad8c61 MM |
897 | if (mode == VOIDmode || mode == DImode) |
898 | { | |
899 | high = CONST_DOUBLE_HIGH (op); | |
900 | low = CONST_DOUBLE_LOW (op); | |
901 | } | |
902 | else | |
903 | { | |
904 | REAL_VALUE_FROM_CONST_DOUBLE (rv, op); | |
905 | REAL_VALUE_TO_TARGET_DOUBLE (rv, l); | |
906 | high = l[endian]; | |
907 | low = l[1 - endian]; | |
908 | } | |
4e74d8ec | 909 | |
47ad8c61 MM |
910 | if (TARGET_32BIT) |
911 | return (num_insns_constant_wide (low) | |
912 | + num_insns_constant_wide (high)); | |
4e74d8ec MM |
913 | |
914 | else | |
47ad8c61 | 915 | { |
0858c623 | 916 | if (high == 0 && (low & 0x80000000) == 0) |
47ad8c61 MM |
917 | return num_insns_constant_wide (low); |
918 | ||
0858c623 | 919 | else if (high == -1 && (low & 0x80000000) != 0) |
47ad8c61 MM |
920 | return num_insns_constant_wide (low); |
921 | ||
a260abc9 DE |
922 | else if (mask64_operand (op, mode)) |
923 | return 2; | |
924 | ||
47ad8c61 MM |
925 | else if (low == 0) |
926 | return num_insns_constant_wide (high) + 1; | |
927 | ||
928 | else | |
929 | return (num_insns_constant_wide (high) | |
930 | + num_insns_constant_wide (low) + 1); | |
931 | } | |
4e74d8ec MM |
932 | } |
933 | ||
934 | else | |
935 | abort (); | |
936 | } | |
937 | ||
6f2f8311 RK |
938 | /* Return 1 if the operand is a CONST_DOUBLE and it can be put into a register |
939 | with one instruction per word. We only do this if we can safely read | |
940 | CONST_DOUBLE_{LOW,HIGH}. */ | |
9878760c RK |
941 | |
942 | int | |
943 | easy_fp_constant (op, mode) | |
944 | register rtx op; | |
945 | register enum machine_mode mode; | |
946 | { | |
9878760c RK |
947 | if (GET_CODE (op) != CONST_DOUBLE |
948 | || GET_MODE (op) != mode | |
4e74d8ec | 949 | || (GET_MODE_CLASS (mode) != MODE_FLOAT && mode != DImode)) |
9878760c RK |
950 | return 0; |
951 | ||
b6c9286a | 952 | /* Consider all constants with -msoft-float to be easy */ |
4e74d8ec | 953 | if (TARGET_SOFT_FLOAT && mode != DImode) |
b6c9286a MM |
954 | return 1; |
955 | ||
a7273471 MM |
956 | /* If we are using V.4 style PIC, consider all constants to be hard */ |
957 | if (flag_pic && (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS)) | |
958 | return 0; | |
959 | ||
5ae4759c MM |
960 | #ifdef TARGET_RELOCATABLE |
961 | /* Similarly if we are using -mrelocatable, consider all constants to be hard */ | |
962 | if (TARGET_RELOCATABLE) | |
963 | return 0; | |
964 | #endif | |
965 | ||
042259f2 DE |
966 | if (mode == DFmode) |
967 | { | |
968 | long k[2]; | |
969 | REAL_VALUE_TYPE rv; | |
970 | ||
971 | REAL_VALUE_FROM_CONST_DOUBLE (rv, op); | |
972 | REAL_VALUE_TO_TARGET_DOUBLE (rv, k); | |
9878760c | 973 | |
4e74d8ec MM |
974 | return (num_insns_constant_wide ((HOST_WIDE_INT)k[0]) == 1 |
975 | && num_insns_constant_wide ((HOST_WIDE_INT)k[1]) == 1); | |
042259f2 | 976 | } |
4e74d8ec MM |
977 | |
978 | else if (mode == SFmode) | |
042259f2 DE |
979 | { |
980 | long l; | |
981 | REAL_VALUE_TYPE rv; | |
982 | ||
983 | REAL_VALUE_FROM_CONST_DOUBLE (rv, op); | |
984 | REAL_VALUE_TO_TARGET_SINGLE (rv, l); | |
9878760c | 985 | |
4e74d8ec | 986 | return num_insns_constant_wide (l) == 1; |
042259f2 | 987 | } |
4e74d8ec | 988 | |
a260abc9 | 989 | else if (mode == DImode) |
c81fc13e | 990 | return ((TARGET_POWERPC64 |
a260abc9 DE |
991 | && GET_CODE (op) == CONST_DOUBLE && CONST_DOUBLE_LOW (op) == 0) |
992 | || (num_insns_constant (op, DImode) <= 2)); | |
4e74d8ec | 993 | |
a9098fd0 GK |
994 | else if (mode == SImode) |
995 | return 1; | |
4e74d8ec MM |
996 | else |
997 | abort (); | |
9878760c | 998 | } |
8f75773e | 999 | |
50a0b056 GK |
1000 | /* Return 1 if the operand is 0.0. */ |
1001 | int | |
1002 | zero_fp_constant (op, mode) | |
1003 | register rtx op; | |
1004 | register enum machine_mode mode; | |
1005 | { | |
1006 | return GET_MODE_CLASS (mode) == MODE_FLOAT && op == CONST0_RTX (mode); | |
1007 | } | |
1008 | ||
b6c9286a MM |
1009 | /* Return 1 if the operand is in volatile memory. Note that during the |
1010 | RTL generation phase, memory_operand does not return TRUE for | |
1011 | volatile memory references. So this function allows us to | |
1012 | recognize volatile references where its safe. */ | |
1013 | ||
1014 | int | |
1015 | volatile_mem_operand (op, mode) | |
1016 | register rtx op; | |
1017 | enum machine_mode mode; | |
1018 | { | |
1019 | if (GET_CODE (op) != MEM) | |
1020 | return 0; | |
1021 | ||
1022 | if (!MEM_VOLATILE_P (op)) | |
1023 | return 0; | |
1024 | ||
1025 | if (mode != GET_MODE (op)) | |
1026 | return 0; | |
1027 | ||
1028 | if (reload_completed) | |
1029 | return memory_operand (op, mode); | |
1030 | ||
1031 | if (reload_in_progress) | |
1032 | return strict_memory_address_p (mode, XEXP (op, 0)); | |
1033 | ||
1034 | return memory_address_p (mode, XEXP (op, 0)); | |
1035 | } | |
1036 | ||
97f6e72f | 1037 | /* Return 1 if the operand is an offsettable memory operand. */ |
914c2e77 RK |
1038 | |
1039 | int | |
97f6e72f | 1040 | offsettable_mem_operand (op, mode) |
914c2e77 RK |
1041 | register rtx op; |
1042 | enum machine_mode mode; | |
1043 | { | |
97f6e72f | 1044 | return ((GET_CODE (op) == MEM) |
677a9668 | 1045 | && offsettable_address_p (reload_completed || reload_in_progress, |
97f6e72f | 1046 | mode, XEXP (op, 0))); |
914c2e77 RK |
1047 | } |
1048 | ||
9878760c RK |
1049 | /* Return 1 if the operand is either an easy FP constant (see above) or |
1050 | memory. */ | |
1051 | ||
1052 | int | |
1053 | mem_or_easy_const_operand (op, mode) | |
1054 | register rtx op; | |
1055 | enum machine_mode mode; | |
1056 | { | |
1057 | return memory_operand (op, mode) || easy_fp_constant (op, mode); | |
1058 | } | |
1059 | ||
1060 | /* Return 1 if the operand is either a non-special register or an item | |
5f59ecb7 | 1061 | that can be used as the operand of a `mode' add insn. */ |
9878760c RK |
1062 | |
1063 | int | |
1064 | add_operand (op, mode) | |
1065 | register rtx op; | |
1066 | enum machine_mode mode; | |
1067 | { | |
2bfcf297 DB |
1068 | if (GET_CODE (op) == CONST_INT) |
1069 | return (CONST_OK_FOR_LETTER_P (INTVAL(op), 'I') | |
1070 | || CONST_OK_FOR_LETTER_P (INTVAL(op), 'L')); | |
1071 | ||
1072 | return gpc_reg_operand (op, mode); | |
9878760c RK |
1073 | } |
1074 | ||
dcfedcd0 RK |
1075 | /* Return 1 if OP is a constant but not a valid add_operand. */ |
1076 | ||
1077 | int | |
1078 | non_add_cint_operand (op, mode) | |
1079 | register rtx op; | |
296b8152 | 1080 | enum machine_mode mode ATTRIBUTE_UNUSED; |
dcfedcd0 RK |
1081 | { |
1082 | return (GET_CODE (op) == CONST_INT | |
a7653a2c | 1083 | && (unsigned HOST_WIDE_INT) (INTVAL (op) + 0x8000) >= 0x10000 |
38886f37 | 1084 | && ! CONST_OK_FOR_LETTER_P (INTVAL (op), 'L')); |
dcfedcd0 RK |
1085 | } |
1086 | ||
9878760c RK |
1087 | /* Return 1 if the operand is a non-special register or a constant that |
1088 | can be used as the operand of an OR or XOR insn on the RS/6000. */ | |
1089 | ||
1090 | int | |
1091 | logical_operand (op, mode) | |
1092 | register rtx op; | |
1093 | enum machine_mode mode; | |
1094 | { | |
1d328b19 GK |
1095 | /* an unsigned representation of 'op'. */ |
1096 | unsigned HOST_WIDE_INT opl, oph; | |
1097 | ||
dfbdccdb GK |
1098 | if (gpc_reg_operand (op, mode)) |
1099 | return 1; | |
1d328b19 | 1100 | |
dfbdccdb | 1101 | if (GET_CODE (op) == CONST_INT) |
38886f37 | 1102 | opl = INTVAL (op); |
dfbdccdb GK |
1103 | else if (GET_CODE (op) == CONST_DOUBLE) |
1104 | { | |
1d328b19 GK |
1105 | if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT) |
1106 | abort(); | |
1107 | ||
1108 | opl = CONST_DOUBLE_LOW (op); | |
1109 | oph = CONST_DOUBLE_HIGH (op); | |
38886f37 AO |
1110 | |
1111 | if (oph != ((unsigned HOST_WIDE_INT)0 | |
1112 | - ((opl & ((unsigned HOST_WIDE_INT)1 | |
1113 | << (HOST_BITS_PER_WIDE_INT - 1))) != 0))) | |
1114 | return 0; | |
dfbdccdb GK |
1115 | } |
1116 | else | |
1117 | return 0; | |
1d328b19 | 1118 | |
38886f37 | 1119 | /* This must really be SImode, not MODE. */ |
78e1b90d | 1120 | if (opl != (unsigned HOST_WIDE_INT) trunc_int_for_mode (opl, SImode)) |
38886f37 AO |
1121 | return 0; |
1122 | ||
1123 | return ((opl & 0xffff) == 0 | |
1124 | || (opl & ~ (unsigned HOST_WIDE_INT) 0xffff) == 0); | |
9878760c RK |
1125 | } |
1126 | ||
dcfedcd0 | 1127 | /* Return 1 if C is a constant that is not a logical operand (as |
1d328b19 | 1128 | above), but could be split into one. */ |
dcfedcd0 RK |
1129 | |
1130 | int | |
1131 | non_logical_cint_operand (op, mode) | |
1132 | register rtx op; | |
5f59ecb7 | 1133 | enum machine_mode mode; |
dcfedcd0 | 1134 | { |
dfbdccdb | 1135 | return ((GET_CODE (op) == CONST_INT || GET_CODE (op) == CONST_DOUBLE) |
1d328b19 GK |
1136 | && ! logical_operand (op, mode) |
1137 | && reg_or_logical_cint_operand (op, mode)); | |
dcfedcd0 RK |
1138 | } |
1139 | ||
19ba8161 | 1140 | /* Return 1 if C is a constant that can be encoded in a 32-bit mask on the |
9878760c RK |
1141 | RS/6000. It is if there are no more than two 1->0 or 0->1 transitions. |
1142 | Reject all ones and all zeros, since these should have been optimized | |
1143 | away and confuse the making of MB and ME. */ | |
1144 | ||
1145 | int | |
19ba8161 DE |
1146 | mask_operand (op, mode) |
1147 | register rtx op; | |
1148 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
9878760c | 1149 | { |
19ba8161 | 1150 | HOST_WIDE_INT c; |
9878760c RK |
1151 | int i; |
1152 | int last_bit_value; | |
1153 | int transitions = 0; | |
1154 | ||
19ba8161 DE |
1155 | if (GET_CODE (op) != CONST_INT) |
1156 | return 0; | |
1157 | ||
1158 | c = INTVAL (op); | |
1159 | ||
9878760c RK |
1160 | if (c == 0 || c == ~0) |
1161 | return 0; | |
1162 | ||
1163 | last_bit_value = c & 1; | |
1164 | ||
1165 | for (i = 1; i < 32; i++) | |
1166 | if (((c >>= 1) & 1) != last_bit_value) | |
1167 | last_bit_value ^= 1, transitions++; | |
1168 | ||
1169 | return transitions <= 2; | |
1170 | } | |
1171 | ||
a260abc9 DE |
1172 | /* Return 1 if the operand is a constant that is a PowerPC64 mask. |
1173 | It is if there are no more than one 1->0 or 0->1 transitions. | |
1174 | Reject all ones and all zeros, since these should have been optimized | |
1175 | away and confuse the making of MB and ME. */ | |
9878760c RK |
1176 | |
1177 | int | |
a260abc9 DE |
1178 | mask64_operand (op, mode) |
1179 | register rtx op; | |
1180 | enum machine_mode mode; | |
1181 | { | |
1182 | if (GET_CODE (op) == CONST_INT) | |
1183 | { | |
1184 | HOST_WIDE_INT c = INTVAL (op); | |
1185 | int i; | |
1186 | int last_bit_value; | |
1187 | int transitions = 0; | |
1188 | ||
1189 | if (c == 0 || c == ~0) | |
1190 | return 0; | |
1191 | ||
1192 | last_bit_value = c & 1; | |
1193 | ||
1194 | for (i = 1; i < HOST_BITS_PER_WIDE_INT; i++) | |
1195 | if (((c >>= 1) & 1) != last_bit_value) | |
1196 | last_bit_value ^= 1, transitions++; | |
1197 | ||
e2c953b6 DE |
1198 | return transitions <= 1; |
1199 | } | |
1200 | else if (GET_CODE (op) == CONST_DOUBLE | |
1201 | && (mode == VOIDmode || mode == DImode)) | |
1202 | { | |
1203 | HOST_WIDE_INT low = CONST_DOUBLE_LOW (op); | |
1204 | #if HOST_BITS_PER_WIDE_INT == 32 | |
1205 | HOST_WIDE_INT high = CONST_DOUBLE_HIGH (op); | |
1206 | #endif | |
1207 | int i; | |
1208 | int last_bit_value; | |
1209 | int transitions = 0; | |
1210 | ||
1211 | if ((low == 0 | |
1212 | #if HOST_BITS_PER_WIDE_INT == 32 | |
1213 | && high == 0 | |
1214 | #endif | |
1215 | ) | |
1216 | || (low == ~0 | |
1217 | #if HOST_BITS_PER_WIDE_INT == 32 | |
1218 | && high == ~0 | |
1219 | #endif | |
1220 | )) | |
1221 | return 0; | |
1222 | ||
1223 | last_bit_value = low & 1; | |
1224 | ||
1225 | for (i = 1; i < HOST_BITS_PER_WIDE_INT; i++) | |
1226 | if (((low >>= 1) & 1) != last_bit_value) | |
1227 | last_bit_value ^= 1, transitions++; | |
1228 | ||
a238cd8b | 1229 | #if HOST_BITS_PER_WIDE_INT == 32 |
e2c953b6 DE |
1230 | if ((high & 1) != last_bit_value) |
1231 | last_bit_value ^= 1, transitions++; | |
1232 | ||
1233 | for (i = 1; i < HOST_BITS_PER_WIDE_INT; i++) | |
1234 | if (((high >>= 1) & 1) != last_bit_value) | |
1235 | last_bit_value ^= 1, transitions++; | |
a260abc9 DE |
1236 | #endif |
1237 | ||
1238 | return transitions <= 1; | |
1239 | } | |
e2c953b6 DE |
1240 | else |
1241 | return 0; | |
1242 | } | |
1243 | ||
1244 | /* Return 1 if the operand is a constant that is a PowerPC64 mask. | |
1245 | It is if there are no more than two 1->0 or 0->1 transitions. | |
1246 | Reject all ones and all zeros, since these should have been optimized | |
1247 | away and confuse the making of MB and ME. */ | |
1248 | ||
1249 | int | |
1250 | rldic_operand (op, mode) | |
1251 | register rtx op; | |
1252 | enum machine_mode mode; | |
1253 | { | |
1254 | if (GET_CODE (op) == CONST_INT) | |
1255 | { | |
1256 | HOST_WIDE_INT c = INTVAL (op); | |
1257 | int i; | |
1258 | int last_bit_value; | |
1259 | int transitions = 0; | |
1260 | ||
1261 | if (c == 0 || c == ~0) | |
1262 | return 0; | |
1263 | ||
1264 | last_bit_value = c & 1; | |
1265 | ||
1266 | for (i = 1; i < HOST_BITS_PER_WIDE_INT; i++) | |
1267 | if (((c >>= 1) & 1) != last_bit_value) | |
1268 | last_bit_value ^= 1, transitions++; | |
1269 | ||
1270 | return transitions <= 2; | |
1271 | } | |
a260abc9 DE |
1272 | else if (GET_CODE (op) == CONST_DOUBLE |
1273 | && (mode == VOIDmode || mode == DImode)) | |
1274 | { | |
1275 | HOST_WIDE_INT low = CONST_DOUBLE_LOW (op); | |
a238cd8b | 1276 | #if HOST_BITS_PER_WIDE_INT == 32 |
a260abc9 DE |
1277 | HOST_WIDE_INT high = CONST_DOUBLE_HIGH (op); |
1278 | #endif | |
1279 | int i; | |
1280 | int last_bit_value; | |
1281 | int transitions = 0; | |
1282 | ||
1283 | if ((low == 0 | |
a238cd8b | 1284 | #if HOST_BITS_PER_WIDE_INT == 32 |
a260abc9 DE |
1285 | && high == 0 |
1286 | #endif | |
1287 | ) | |
1288 | || (low == ~0 | |
a238cd8b | 1289 | #if HOST_BITS_PER_WIDE_INT == 32 |
a260abc9 DE |
1290 | && high == ~0 |
1291 | #endif | |
1292 | )) | |
1293 | return 0; | |
1294 | ||
1295 | last_bit_value = low & 1; | |
1296 | ||
1297 | for (i = 1; i < HOST_BITS_PER_WIDE_INT; i++) | |
1298 | if (((low >>= 1) & 1) != last_bit_value) | |
1299 | last_bit_value ^= 1, transitions++; | |
1300 | ||
a238cd8b | 1301 | #if HOST_BITS_PER_WIDE_INT == 32 |
a260abc9 DE |
1302 | if ((high & 1) != last_bit_value) |
1303 | last_bit_value ^= 1, transitions++; | |
1304 | ||
1305 | for (i = 1; i < HOST_BITS_PER_WIDE_INT; i++) | |
1306 | if (((high >>= 1) & 1) != last_bit_value) | |
1307 | last_bit_value ^= 1, transitions++; | |
1308 | #endif | |
1309 | ||
e2c953b6 | 1310 | return transitions <= 2; |
a260abc9 DE |
1311 | } |
1312 | else | |
1313 | return 0; | |
1314 | } | |
1315 | ||
1316 | /* Return 1 if the operand is either a non-special register or a constant | |
1317 | that can be used as the operand of a PowerPC64 logical AND insn. */ | |
1318 | ||
1319 | int | |
1320 | and64_operand (op, mode) | |
9878760c RK |
1321 | register rtx op; |
1322 | enum machine_mode mode; | |
1323 | { | |
9ebbca7d | 1324 | if (fixed_regs[CR0_REGNO]) /* CR0 not available, don't do andi./andis. */ |
52d3af72 DE |
1325 | return (gpc_reg_operand (op, mode) || mask64_operand (op, mode)); |
1326 | ||
1327 | return (logical_operand (op, mode) || mask64_operand (op, mode)); | |
9878760c RK |
1328 | } |
1329 | ||
a260abc9 DE |
1330 | /* Return 1 if the operand is either a non-special register or a |
1331 | constant that can be used as the operand of an RS/6000 logical AND insn. */ | |
dcfedcd0 RK |
1332 | |
1333 | int | |
a260abc9 DE |
1334 | and_operand (op, mode) |
1335 | register rtx op; | |
1336 | enum machine_mode mode; | |
dcfedcd0 | 1337 | { |
9ebbca7d | 1338 | if (fixed_regs[CR0_REGNO]) /* CR0 not available, don't do andi./andis. */ |
52d3af72 DE |
1339 | return (gpc_reg_operand (op, mode) || mask_operand (op, mode)); |
1340 | ||
1341 | return (logical_operand (op, mode) || mask_operand (op, mode)); | |
dcfedcd0 RK |
1342 | } |
1343 | ||
9878760c RK |
1344 | /* Return 1 if the operand is a general register or memory operand. */ |
1345 | ||
1346 | int | |
1347 | reg_or_mem_operand (op, mode) | |
1348 | register rtx op; | |
1349 | register enum machine_mode mode; | |
1350 | { | |
b6c9286a MM |
1351 | return (gpc_reg_operand (op, mode) |
1352 | || memory_operand (op, mode) | |
1353 | || volatile_mem_operand (op, mode)); | |
9878760c RK |
1354 | } |
1355 | ||
a7a813f7 | 1356 | /* Return 1 if the operand is a general register or memory operand without |
3cb999d8 | 1357 | pre_inc or pre_dec which produces invalid form of PowerPC lwa |
a7a813f7 RK |
1358 | instruction. */ |
1359 | ||
1360 | int | |
1361 | lwa_operand (op, mode) | |
1362 | register rtx op; | |
1363 | register enum machine_mode mode; | |
1364 | { | |
1365 | rtx inner = op; | |
1366 | ||
1367 | if (reload_completed && GET_CODE (inner) == SUBREG) | |
1368 | inner = SUBREG_REG (inner); | |
1369 | ||
1370 | return gpc_reg_operand (inner, mode) | |
1371 | || (memory_operand (inner, mode) | |
1372 | && GET_CODE (XEXP (inner, 0)) != PRE_INC | |
1373 | && GET_CODE (XEXP (inner, 0)) != PRE_DEC); | |
1374 | } | |
1375 | ||
9878760c RK |
1376 | /* Return 1 if the operand, used inside a MEM, is a valid first argument |
1377 | to CALL. This is a SYMBOL_REF or a pseudo-register, which will be | |
1378 | forced to lr. */ | |
1379 | ||
1380 | int | |
1381 | call_operand (op, mode) | |
1382 | register rtx op; | |
1383 | enum machine_mode mode; | |
1384 | { | |
1385 | if (mode != VOIDmode && GET_MODE (op) != mode) | |
1386 | return 0; | |
1387 | ||
1388 | return (GET_CODE (op) == SYMBOL_REF | |
1389 | || (GET_CODE (op) == REG && REGNO (op) >= FIRST_PSEUDO_REGISTER)); | |
1390 | } | |
1391 | ||
2af3d377 RK |
1392 | |
1393 | /* Return 1 if the operand is a SYMBOL_REF for a function known to be in | |
8f1b829e | 1394 | this file and the function is not weakly defined. */ |
2af3d377 RK |
1395 | |
1396 | int | |
1397 | current_file_function_operand (op, mode) | |
1398 | register rtx op; | |
296b8152 | 1399 | enum machine_mode mode ATTRIBUTE_UNUSED; |
2af3d377 RK |
1400 | { |
1401 | return (GET_CODE (op) == SYMBOL_REF | |
1402 | && (SYMBOL_REF_FLAG (op) | |
8f1b829e | 1403 | || (op == XEXP (DECL_RTL (current_function_decl), 0) |
c81fc13e | 1404 | && ! DECL_WEAK (current_function_decl)))); |
2af3d377 RK |
1405 | } |
1406 | ||
1407 | ||
9878760c RK |
1408 | /* Return 1 if this operand is a valid input for a move insn. */ |
1409 | ||
1410 | int | |
1411 | input_operand (op, mode) | |
1412 | register rtx op; | |
1413 | enum machine_mode mode; | |
1414 | { | |
eb4e8003 | 1415 | /* Memory is always valid. */ |
9878760c RK |
1416 | if (memory_operand (op, mode)) |
1417 | return 1; | |
1418 | ||
34792e82 | 1419 | /* Only a tiny bit of handling for CONSTANT_P_RTX is necessary. */ |
01b4cf2b | 1420 | if (GET_CODE (op) == CONSTANT_P_RTX) |
34792e82 JL |
1421 | return 1; |
1422 | ||
eb4e8003 RK |
1423 | /* For floating-point, easy constants are valid. */ |
1424 | if (GET_MODE_CLASS (mode) == MODE_FLOAT | |
1425 | && CONSTANT_P (op) | |
1426 | && easy_fp_constant (op, mode)) | |
1427 | return 1; | |
1428 | ||
4e74d8ec MM |
1429 | /* Allow any integer constant. */ |
1430 | if (GET_MODE_CLASS (mode) == MODE_INT | |
e675f625 | 1431 | && (GET_CODE (op) == CONST_INT |
e675f625 | 1432 | || GET_CODE (op) == CONST_DOUBLE)) |
4e74d8ec MM |
1433 | return 1; |
1434 | ||
eb4e8003 RK |
1435 | /* For floating-point or multi-word mode, the only remaining valid type |
1436 | is a register. */ | |
9878760c RK |
1437 | if (GET_MODE_CLASS (mode) == MODE_FLOAT |
1438 | || GET_MODE_SIZE (mode) > UNITS_PER_WORD) | |
eb4e8003 | 1439 | return register_operand (op, mode); |
9878760c | 1440 | |
88fe15a1 RK |
1441 | /* The only cases left are integral modes one word or smaller (we |
1442 | do not get called for MODE_CC values). These can be in any | |
1443 | register. */ | |
1444 | if (register_operand (op, mode)) | |
a8b3aeda | 1445 | return 1; |
88fe15a1 | 1446 | |
84cf9dda | 1447 | /* A SYMBOL_REF referring to the TOC is valid. */ |
7fec4abd | 1448 | if (LEGITIMATE_CONSTANT_POOL_ADDRESS_P (op)) |
84cf9dda RK |
1449 | return 1; |
1450 | ||
9ebbca7d GK |
1451 | /* A constant pool expression (relative to the TOC) is valid */ |
1452 | if (TOC_RELATIVE_EXPR_P (op)) | |
b6c9286a MM |
1453 | return 1; |
1454 | ||
88228c4b MM |
1455 | /* V.4 allows SYMBOL_REFs and CONSTs that are in the small data region |
1456 | to be valid. */ | |
c81bebd7 | 1457 | if ((DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) |
88228c4b MM |
1458 | && (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST) |
1459 | && small_data_operand (op, Pmode)) | |
1460 | return 1; | |
1461 | ||
042259f2 | 1462 | return 0; |
9878760c | 1463 | } |
7509c759 MM |
1464 | |
1465 | /* Return 1 for an operand in small memory on V.4/eabi */ | |
1466 | ||
1467 | int | |
1468 | small_data_operand (op, mode) | |
296b8152 KG |
1469 | rtx op ATTRIBUTE_UNUSED; |
1470 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
7509c759 | 1471 | { |
38c1f2d7 | 1472 | #if TARGET_ELF |
5f59ecb7 | 1473 | rtx sym_ref; |
7509c759 | 1474 | |
d9407988 | 1475 | if (rs6000_sdata == SDATA_NONE || rs6000_sdata == SDATA_DATA) |
a54d04b7 | 1476 | return 0; |
a54d04b7 | 1477 | |
5b9d9a0c | 1478 | if (DEFAULT_ABI != ABI_V4 && DEFAULT_ABI != ABI_SOLARIS) |
7509c759 MM |
1479 | return 0; |
1480 | ||
88228c4b MM |
1481 | if (GET_CODE (op) == SYMBOL_REF) |
1482 | sym_ref = op; | |
1483 | ||
1484 | else if (GET_CODE (op) != CONST | |
1485 | || GET_CODE (XEXP (op, 0)) != PLUS | |
1486 | || GET_CODE (XEXP (XEXP (op, 0), 0)) != SYMBOL_REF | |
1487 | || GET_CODE (XEXP (XEXP (op, 0), 1)) != CONST_INT) | |
7509c759 MM |
1488 | return 0; |
1489 | ||
88228c4b | 1490 | else |
dbf55e53 MM |
1491 | { |
1492 | rtx sum = XEXP (op, 0); | |
1493 | HOST_WIDE_INT summand; | |
1494 | ||
1495 | /* We have to be careful here, because it is the referenced address | |
1496 | that must be 32k from _SDA_BASE_, not just the symbol. */ | |
1497 | summand = INTVAL (XEXP (sum, 1)); | |
1498 | if (summand < 0 || summand > g_switch_value) | |
1499 | return 0; | |
1500 | ||
1501 | sym_ref = XEXP (sum, 0); | |
1502 | } | |
88228c4b MM |
1503 | |
1504 | if (*XSTR (sym_ref, 0) != '@') | |
7509c759 MM |
1505 | return 0; |
1506 | ||
1507 | return 1; | |
d9407988 MM |
1508 | |
1509 | #else | |
1510 | return 0; | |
1511 | #endif | |
7509c759 | 1512 | } |
9ebbca7d GK |
1513 | \f |
1514 | static int | |
1515 | constant_pool_expr_1 (op, have_sym, have_toc) | |
1516 | rtx op; | |
1517 | int *have_sym; | |
1518 | int *have_toc; | |
1519 | { | |
1520 | switch (GET_CODE(op)) | |
1521 | { | |
1522 | case SYMBOL_REF: | |
1523 | if (CONSTANT_POOL_ADDRESS_P (op)) | |
1524 | { | |
a9098fd0 | 1525 | if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (op), Pmode)) |
9ebbca7d GK |
1526 | { |
1527 | *have_sym = 1; | |
1528 | return 1; | |
1529 | } | |
1530 | else | |
1531 | return 0; | |
1532 | } | |
1533 | else if (! strcmp (XSTR (op, 0), toc_label_name)) | |
1534 | { | |
1535 | *have_toc = 1; | |
1536 | return 1; | |
1537 | } | |
1538 | else | |
1539 | return 0; | |
1540 | case PLUS: | |
1541 | case MINUS: | |
1542 | return constant_pool_expr_1 (XEXP (op, 0), have_sym, have_toc) && | |
1543 | constant_pool_expr_1 (XEXP (op, 1), have_sym, have_toc); | |
1544 | case CONST: | |
1545 | return constant_pool_expr_1 (XEXP (op, 0), have_sym, have_toc); | |
1546 | case CONST_INT: | |
1547 | return 1; | |
1548 | default: | |
1549 | return 0; | |
1550 | } | |
1551 | } | |
1552 | ||
1553 | int | |
1554 | constant_pool_expr_p (op) | |
1555 | rtx op; | |
1556 | { | |
1557 | int have_sym = 0; | |
1558 | int have_toc = 0; | |
1559 | return constant_pool_expr_1 (op, &have_sym, &have_toc) && have_sym; | |
1560 | } | |
1561 | ||
1562 | int | |
1563 | toc_relative_expr_p (op) | |
1564 | rtx op; | |
1565 | { | |
1566 | int have_sym = 0; | |
1567 | int have_toc = 0; | |
1568 | return constant_pool_expr_1 (op, &have_sym, &have_toc) && have_toc; | |
1569 | } | |
1570 | ||
1571 | /* Try machine-dependent ways of modifying an illegitimate address | |
1572 | to be legitimate. If we find one, return the new, valid address. | |
1573 | This is used from only one place: `memory_address' in explow.c. | |
1574 | ||
1575 | OLDX is the address as it was before break_out_memory_refs was called. | |
1576 | In some cases it is useful to look at this to decide what needs to be done. | |
1577 | ||
1578 | MODE is passed so that this macro can use GO_IF_LEGITIMATE_ADDRESS. | |
1579 | ||
1580 | It is always safe for this macro to do nothing. It exists to recognize | |
1581 | opportunities to optimize the output. | |
1582 | ||
1583 | On RS/6000, first check for the sum of a register with a constant | |
1584 | integer that is out of range. If so, generate code to add the | |
1585 | constant with the low-order 16 bits masked to the register and force | |
1586 | this result into another register (this can be done with `cau'). | |
1587 | Then generate an address of REG+(CONST&0xffff), allowing for the | |
1588 | possibility of bit 16 being a one. | |
1589 | ||
1590 | Then check for the sum of a register and something not constant, try to | |
1591 | load the other things into a register and return the sum. */ | |
1592 | rtx | |
1593 | rs6000_legitimize_address (x, oldx, mode) | |
1594 | rtx x; | |
1595 | rtx oldx ATTRIBUTE_UNUSED; | |
1596 | enum machine_mode mode; | |
1597 | { | |
1598 | if (GET_CODE (x) == PLUS | |
1599 | && GET_CODE (XEXP (x, 0)) == REG | |
1600 | && GET_CODE (XEXP (x, 1)) == CONST_INT | |
1601 | && (unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 1)) + 0x8000) >= 0x10000) | |
1602 | { | |
1603 | HOST_WIDE_INT high_int, low_int; | |
1604 | rtx sum; | |
1605 | high_int = INTVAL (XEXP (x, 1)) & (~ (HOST_WIDE_INT) 0xffff); | |
1606 | low_int = INTVAL (XEXP (x, 1)) & 0xffff; | |
1607 | if (low_int & 0x8000) | |
1608 | high_int += 0x10000, low_int |= ((HOST_WIDE_INT) -1) << 16; | |
1609 | sum = force_operand (gen_rtx_PLUS (Pmode, XEXP (x, 0), | |
1610 | GEN_INT (high_int)), 0); | |
1611 | return gen_rtx_PLUS (Pmode, sum, GEN_INT (low_int)); | |
1612 | } | |
1613 | else if (GET_CODE (x) == PLUS | |
1614 | && GET_CODE (XEXP (x, 0)) == REG | |
1615 | && GET_CODE (XEXP (x, 1)) != CONST_INT | |
1616 | && (TARGET_HARD_FLOAT || TARGET_POWERPC64 || mode != DFmode) | |
1617 | && (TARGET_POWERPC64 || mode != DImode) | |
1618 | && mode != TImode) | |
1619 | { | |
1620 | return gen_rtx_PLUS (Pmode, XEXP (x, 0), | |
1621 | force_reg (Pmode, force_operand (XEXP (x, 1), 0))); | |
1622 | } | |
1623 | else if (TARGET_ELF && TARGET_32BIT && TARGET_NO_TOC && ! flag_pic | |
1624 | && GET_CODE (x) != CONST_INT | |
1625 | && GET_CODE (x) != CONST_DOUBLE | |
1626 | && CONSTANT_P (x) | |
1627 | && (TARGET_HARD_FLOAT || mode != DFmode) | |
1628 | && mode != DImode | |
1629 | && mode != TImode) | |
1630 | { | |
1631 | rtx reg = gen_reg_rtx (Pmode); | |
1632 | emit_insn (gen_elf_high (reg, (x))); | |
1633 | return gen_rtx_LO_SUM (Pmode, reg, (x)); | |
1634 | } | |
ee890fe2 SS |
1635 | else if (TARGET_MACHO && TARGET_32BIT && TARGET_NO_TOC |
1636 | && ! flag_pic | |
1637 | && GET_CODE (x) != CONST_INT | |
1638 | && GET_CODE (x) != CONST_DOUBLE | |
1639 | && CONSTANT_P (x) | |
1640 | && (TARGET_HARD_FLOAT || mode != DFmode) | |
1641 | && mode != DImode | |
1642 | && mode != TImode) | |
1643 | { | |
1644 | rtx reg = gen_reg_rtx (Pmode); | |
1645 | emit_insn (gen_macho_high (reg, (x))); | |
1646 | return gen_rtx_LO_SUM (Pmode, reg, (x)); | |
1647 | } | |
9ebbca7d GK |
1648 | else if (TARGET_TOC |
1649 | && CONSTANT_POOL_EXPR_P (x) | |
a9098fd0 | 1650 | && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x), Pmode)) |
9ebbca7d GK |
1651 | { |
1652 | return create_TOC_reference (x); | |
1653 | } | |
1654 | else | |
1655 | return NULL_RTX; | |
1656 | } | |
258bfae2 FS |
1657 | |
1658 | /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression | |
1659 | that is a valid memory address for an instruction. | |
1660 | The MODE argument is the machine mode for the MEM expression | |
1661 | that wants to use this address. | |
1662 | ||
1663 | On the RS/6000, there are four valid address: a SYMBOL_REF that | |
1664 | refers to a constant pool entry of an address (or the sum of it | |
1665 | plus a constant), a short (16-bit signed) constant plus a register, | |
1666 | the sum of two registers, or a register indirect, possibly with an | |
1667 | auto-increment. For DFmode and DImode with an constant plus register, | |
1668 | we must ensure that both words are addressable or PowerPC64 with offset | |
1669 | word aligned. | |
1670 | ||
1671 | For modes spanning multiple registers (DFmode in 32-bit GPRs, | |
1672 | 32-bit DImode, TImode), indexed addressing cannot be used because | |
1673 | adjacent memory cells are accessed by adding word-sized offsets | |
1674 | during assembly output. */ | |
1675 | int | |
1676 | rs6000_legitimate_address (mode, x, reg_ok_strict) | |
1677 | enum machine_mode mode; | |
1678 | rtx x; | |
1679 | int reg_ok_strict; | |
1680 | { | |
1681 | if (LEGITIMATE_INDIRECT_ADDRESS_P (x, reg_ok_strict)) | |
1682 | return 1; | |
1683 | if ((GET_CODE (x) == PRE_INC || GET_CODE (x) == PRE_DEC) | |
1684 | && TARGET_UPDATE | |
1685 | && LEGITIMATE_INDIRECT_ADDRESS_P (XEXP (x, 0), reg_ok_strict)) | |
1686 | return 1; | |
1687 | if (LEGITIMATE_SMALL_DATA_P (mode, x)) | |
1688 | return 1; | |
1689 | if (LEGITIMATE_CONSTANT_POOL_ADDRESS_P (x)) | |
1690 | return 1; | |
1691 | /* If not REG_OK_STRICT (before reload) let pass any stack offset. */ | |
1692 | if (! reg_ok_strict | |
1693 | && GET_CODE (x) == PLUS | |
1694 | && GET_CODE (XEXP (x, 0)) == REG | |
1695 | && XEXP (x, 0) == virtual_stack_vars_rtx | |
1696 | && GET_CODE (XEXP (x, 1)) == CONST_INT) | |
1697 | return 1; | |
1698 | if (LEGITIMATE_OFFSET_ADDRESS_P (mode, x, reg_ok_strict)) | |
1699 | return 1; | |
1700 | if (mode != TImode | |
1701 | && (TARGET_HARD_FLOAT || TARGET_POWERPC64 || mode != DFmode) | |
1702 | && (TARGET_POWERPC64 || mode != DImode) | |
1703 | && LEGITIMATE_INDEXED_ADDRESS_P (x, reg_ok_strict)) | |
1704 | return 1; | |
1705 | if (LEGITIMATE_LO_SUM_ADDRESS_P (mode, x, reg_ok_strict)) | |
1706 | return 1; | |
1707 | return 0; | |
1708 | } | |
fb4d4348 | 1709 | \f |
2bfcf297 DB |
1710 | /* Try to output insns to set TARGET equal to the constant C if it can be |
1711 | done in less than N insns. Do all computations in MODE. Returns the place | |
1712 | where the output has been placed if it can be done and the insns have been | |
1713 | emitted. If it would take more than N insns, zero is returned and no | |
1714 | insns and emitted. */ | |
1715 | ||
1716 | rtx | |
1717 | rs6000_emit_set_const (dest, mode, source, n) | |
1718 | rtx dest, source; | |
1719 | enum machine_mode mode; | |
1720 | int n ATTRIBUTE_UNUSED; | |
1721 | { | |
1722 | HOST_WIDE_INT c0, c1; | |
1723 | ||
1724 | if (mode == QImode || mode == HImode || mode == SImode) | |
1725 | { | |
1726 | if (dest == NULL) | |
1727 | dest = gen_reg_rtx (mode); | |
1728 | emit_insn (gen_rtx_SET (VOIDmode, dest, source)); | |
1729 | return dest; | |
1730 | } | |
1731 | ||
1732 | if (GET_CODE (source) == CONST_INT) | |
1733 | { | |
1734 | c0 = INTVAL (source); | |
1735 | c1 = -(c0 < 0); | |
1736 | } | |
1737 | else if (GET_CODE (source) == CONST_DOUBLE) | |
1738 | { | |
1739 | #if HOST_BITS_PER_WIDE_INT >= 64 | |
1740 | c0 = CONST_DOUBLE_LOW (source); | |
1741 | c1 = -(c0 < 0); | |
1742 | #else | |
1743 | c0 = CONST_DOUBLE_LOW (source); | |
1744 | c1 = CONST_DOUBLE_HIGH (source); | |
1745 | #endif | |
1746 | } | |
1747 | else | |
1748 | abort(); | |
1749 | ||
1750 | return rs6000_emit_set_long_const (dest, c0, c1); | |
1751 | } | |
1752 | ||
1753 | /* Having failed to find a 3 insn sequence in rs6000_emit_set_const, | |
1754 | fall back to a straight forward decomposition. We do this to avoid | |
1755 | exponential run times encountered when looking for longer sequences | |
1756 | with rs6000_emit_set_const. */ | |
1757 | static rtx | |
1758 | rs6000_emit_set_long_const (dest, c1, c2) | |
1759 | rtx dest; | |
1760 | HOST_WIDE_INT c1, c2; | |
1761 | { | |
1762 | if (!TARGET_POWERPC64) | |
1763 | { | |
1764 | rtx operand1, operand2; | |
1765 | ||
1766 | operand1 = operand_subword_force (dest, WORDS_BIG_ENDIAN == 0, | |
1767 | DImode); | |
1768 | operand2 = operand_subword_force (dest, WORDS_BIG_ENDIAN != 0, | |
1769 | DImode); | |
1770 | emit_move_insn (operand1, GEN_INT (c1)); | |
1771 | emit_move_insn (operand2, GEN_INT (c2)); | |
1772 | } | |
1773 | else | |
1774 | { | |
1775 | HOST_WIDE_INT d1, d2, d3, d4; | |
1776 | ||
1777 | /* Decompose the entire word */ | |
1778 | #if HOST_BITS_PER_WIDE_INT >= 64 | |
1779 | if (c2 != -(c1 < 0)) | |
1780 | abort (); | |
1781 | d1 = ((c1 & 0xffff) ^ 0x8000) - 0x8000; | |
1782 | c1 -= d1; | |
1783 | d2 = ((c1 & 0xffffffff) ^ 0x80000000) - 0x80000000; | |
1784 | c1 = (c1 - d2) >> 32; | |
1785 | d3 = ((c1 & 0xffff) ^ 0x8000) - 0x8000; | |
1786 | c1 -= d3; | |
1787 | d4 = ((c1 & 0xffffffff) ^ 0x80000000) - 0x80000000; | |
1788 | if (c1 != d4) | |
1789 | abort (); | |
1790 | #else | |
1791 | d1 = ((c1 & 0xffff) ^ 0x8000) - 0x8000; | |
1792 | c1 -= d1; | |
1793 | d2 = ((c1 & 0xffffffff) ^ 0x80000000) - 0x80000000; | |
1794 | if (c1 != d2) | |
1795 | abort (); | |
1796 | c2 += (d2 < 0); | |
1797 | d3 = ((c2 & 0xffff) ^ 0x8000) - 0x8000; | |
1798 | c2 -= d3; | |
1799 | d4 = ((c2 & 0xffffffff) ^ 0x80000000) - 0x80000000; | |
1800 | if (c2 != d4) | |
1801 | abort (); | |
1802 | #endif | |
1803 | ||
1804 | /* Construct the high word */ | |
1805 | if (d4) | |
1806 | { | |
1807 | emit_move_insn (dest, GEN_INT (d4)); | |
1808 | if (d3) | |
1809 | emit_move_insn (dest, | |
1810 | gen_rtx_PLUS (DImode, dest, GEN_INT (d3))); | |
1811 | } | |
1812 | else | |
1813 | emit_move_insn (dest, GEN_INT (d3)); | |
1814 | ||
1815 | /* Shift it into place */ | |
1816 | emit_move_insn (dest, gen_rtx_ASHIFT (DImode, dest, GEN_INT (32))); | |
1817 | ||
1818 | /* Add in the low bits. */ | |
1819 | if (d2) | |
1820 | emit_move_insn (dest, gen_rtx_PLUS (DImode, dest, GEN_INT (d2))); | |
1821 | if (d1) | |
1822 | emit_move_insn (dest, gen_rtx_PLUS (DImode, dest, GEN_INT (d1))); | |
1823 | } | |
1824 | ||
1825 | return dest; | |
1826 | } | |
1827 | ||
fb4d4348 GK |
1828 | /* Emit a move from SOURCE to DEST in mode MODE. */ |
1829 | void | |
1830 | rs6000_emit_move (dest, source, mode) | |
1831 | rtx dest; | |
1832 | rtx source; | |
1833 | enum machine_mode mode; | |
1834 | { | |
1835 | rtx operands[2]; | |
1836 | operands[0] = dest; | |
1837 | operands[1] = source; | |
1838 | ||
1839 | /* Sanity checks. Check that we get CONST_DOUBLE only when we should. */ | |
1840 | if (GET_CODE (operands[1]) == CONST_DOUBLE | |
1841 | && ! FLOAT_MODE_P (mode) | |
1842 | && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT) | |
1843 | { | |
1844 | /* FIXME. This should never happen. */ | |
1845 | /* Since it seems that it does, do the safe thing and convert | |
1846 | to a CONST_INT. */ | |
1847 | operands[1] = | |
1848 | GEN_INT (trunc_int_for_mode (CONST_DOUBLE_LOW (operands[1]), mode)); | |
1849 | } | |
1850 | if (GET_CODE (operands[1]) == CONST_DOUBLE | |
1851 | && ! FLOAT_MODE_P (mode) | |
1852 | && ((CONST_DOUBLE_HIGH (operands[1]) == 0 | |
1853 | && CONST_DOUBLE_LOW (operands[1]) >= 0) | |
1854 | || (CONST_DOUBLE_HIGH (operands[1]) == -1 | |
1855 | && CONST_DOUBLE_LOW (operands[1]) < 0))) | |
1856 | abort (); | |
1857 | ||
1858 | if (! no_new_pseudos && GET_CODE (operands[0]) != REG) | |
1859 | operands[1] = force_reg (mode, operands[1]); | |
a9098fd0 | 1860 | |
ffc14f31 GK |
1861 | if (mode == SFmode && ! TARGET_POWERPC && TARGET_HARD_FLOAT |
1862 | && GET_CODE (operands[0]) == MEM) | |
fb4d4348 | 1863 | { |
ffc14f31 GK |
1864 | int regnum; |
1865 | ||
1866 | if (reload_in_progress || reload_completed) | |
1867 | regnum = true_regnum (operands[1]); | |
1868 | else if (GET_CODE (operands[1]) == REG) | |
1869 | regnum = REGNO (operands[1]); | |
1870 | else | |
1871 | regnum = -1; | |
fb4d4348 GK |
1872 | |
1873 | /* If operands[1] is a register, on POWER it may have | |
1874 | double-precision data in it, so truncate it to single | |
1875 | precision. */ | |
1876 | if (FP_REGNO_P (regnum) || regnum >= FIRST_PSEUDO_REGISTER) | |
1877 | { | |
1878 | rtx newreg; | |
1879 | newreg = (no_new_pseudos ? operands[1] : gen_reg_rtx (mode)); | |
1880 | emit_insn (gen_aux_truncdfsf2 (newreg, operands[1])); | |
1881 | operands[1] = newreg; | |
1882 | } | |
1883 | } | |
1884 | ||
a9098fd0 GK |
1885 | /* Handle the case where reload calls us with an invalid address; |
1886 | and the case of CONSTANT_P_RTX. */ | |
1887 | if (! general_operand (operands[1], mode) | |
1888 | || ! nonimmediate_operand (operands[0], mode) | |
1889 | || GET_CODE (operands[1]) == CONSTANT_P_RTX) | |
fb4d4348 GK |
1890 | { |
1891 | emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1])); | |
1892 | return; | |
1893 | } | |
a9098fd0 | 1894 | |
fb4d4348 GK |
1895 | /* FIXME: In the long term, this switch statement should go away |
1896 | and be replaced by a sequence of tests based on things like | |
1897 | mode == Pmode. */ | |
1898 | switch (mode) | |
1899 | { | |
1900 | case HImode: | |
1901 | case QImode: | |
1902 | if (CONSTANT_P (operands[1]) | |
1903 | && GET_CODE (operands[1]) != CONST_INT) | |
a9098fd0 | 1904 | operands[1] = force_const_mem (mode, operands[1]); |
fb4d4348 GK |
1905 | break; |
1906 | ||
1907 | case DFmode: | |
1908 | case SFmode: | |
1909 | if (CONSTANT_P (operands[1]) | |
1910 | && ! easy_fp_constant (operands[1], mode)) | |
a9098fd0 | 1911 | operands[1] = force_const_mem (mode, operands[1]); |
fb4d4348 GK |
1912 | break; |
1913 | ||
1914 | case SImode: | |
a9098fd0 | 1915 | case DImode: |
fb4d4348 GK |
1916 | /* Use default pattern for address of ELF small data */ |
1917 | if (TARGET_ELF | |
a9098fd0 | 1918 | && mode == Pmode |
fb4d4348 | 1919 | && (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) |
a9098fd0 GK |
1920 | && (GET_CODE (operands[1]) == SYMBOL_REF |
1921 | || GET_CODE (operands[1]) == CONST) | |
1922 | && small_data_operand (operands[1], mode)) | |
fb4d4348 GK |
1923 | { |
1924 | emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1])); | |
1925 | return; | |
1926 | } | |
1927 | ||
1928 | if ((DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) | |
a9098fd0 GK |
1929 | && mode == Pmode && mode == SImode |
1930 | && flag_pic == 1 && got_operand (operands[1], mode)) | |
fb4d4348 GK |
1931 | { |
1932 | emit_insn (gen_movsi_got (operands[0], operands[1])); | |
1933 | return; | |
1934 | } | |
1935 | ||
ee890fe2 SS |
1936 | if ((TARGET_ELF || DEFAULT_ABI == ABI_DARWIN) |
1937 | && TARGET_NO_TOC && ! flag_pic | |
a9098fd0 | 1938 | && mode == Pmode |
fb4d4348 GK |
1939 | && CONSTANT_P (operands[1]) |
1940 | && GET_CODE (operands[1]) != HIGH | |
1941 | && GET_CODE (operands[1]) != CONST_INT) | |
1942 | { | |
a9098fd0 | 1943 | rtx target = (no_new_pseudos ? operands[0] : gen_reg_rtx (mode)); |
fb4d4348 GK |
1944 | |
1945 | /* If this is a function address on -mcall-aixdesc, | |
1946 | convert it to the address of the descriptor. */ | |
1947 | if (DEFAULT_ABI == ABI_AIX | |
1948 | && GET_CODE (operands[1]) == SYMBOL_REF | |
1949 | && XSTR (operands[1], 0)[0] == '.') | |
1950 | { | |
1951 | const char *name = XSTR (operands[1], 0); | |
1952 | rtx new_ref; | |
1953 | while (*name == '.') | |
1954 | name++; | |
1955 | new_ref = gen_rtx_SYMBOL_REF (Pmode, name); | |
1956 | CONSTANT_POOL_ADDRESS_P (new_ref) | |
1957 | = CONSTANT_POOL_ADDRESS_P (operands[1]); | |
1958 | SYMBOL_REF_FLAG (new_ref) = SYMBOL_REF_FLAG (operands[1]); | |
1959 | SYMBOL_REF_USED (new_ref) = SYMBOL_REF_USED (operands[1]); | |
1960 | operands[1] = new_ref; | |
1961 | } | |
7509c759 | 1962 | |
ee890fe2 SS |
1963 | if (DEFAULT_ABI == ABI_DARWIN) |
1964 | { | |
1965 | emit_insn (gen_macho_high (target, operands[1])); | |
1966 | emit_insn (gen_macho_low (operands[0], target, operands[1])); | |
1967 | return; | |
1968 | } | |
1969 | ||
fb4d4348 GK |
1970 | emit_insn (gen_elf_high (target, operands[1])); |
1971 | emit_insn (gen_elf_low (operands[0], target, operands[1])); | |
1972 | return; | |
1973 | } | |
1974 | ||
a9098fd0 GK |
1975 | /* If this is a SYMBOL_REF that refers to a constant pool entry, |
1976 | and we have put it in the TOC, we just need to make a TOC-relative | |
1977 | reference to it. */ | |
1978 | if (TARGET_TOC | |
1979 | && GET_CODE (operands[1]) == SYMBOL_REF | |
1980 | && CONSTANT_POOL_EXPR_P (operands[1]) | |
1981 | && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (operands[1]), | |
1982 | get_pool_mode (operands[1]))) | |
fb4d4348 | 1983 | { |
a9098fd0 | 1984 | operands[1] = create_TOC_reference (operands[1]); |
fb4d4348 | 1985 | } |
a9098fd0 GK |
1986 | else if (mode == Pmode |
1987 | && CONSTANT_P (operands[1]) | |
38886f37 AO |
1988 | && ((GET_CODE (operands[1]) != CONST_INT |
1989 | && ! easy_fp_constant (operands[1], mode)) | |
1990 | || (GET_CODE (operands[1]) == CONST_INT | |
1991 | && num_insns_constant (operands[1], mode) > 2) | |
1992 | || (GET_CODE (operands[0]) == REG | |
1993 | && FP_REGNO_P (REGNO (operands[0])))) | |
a9098fd0 GK |
1994 | && GET_CODE (operands[1]) != HIGH |
1995 | && ! LEGITIMATE_CONSTANT_POOL_ADDRESS_P (operands[1]) | |
1996 | && ! TOC_RELATIVE_EXPR_P (operands[1])) | |
fb4d4348 GK |
1997 | { |
1998 | /* Emit a USE operation so that the constant isn't deleted if | |
1999 | expensive optimizations are turned on because nobody | |
2000 | references it. This should only be done for operands that | |
2001 | contain SYMBOL_REFs with CONSTANT_POOL_ADDRESS_P set. | |
2002 | This should not be done for operands that contain LABEL_REFs. | |
2003 | For now, we just handle the obvious case. */ | |
2004 | if (GET_CODE (operands[1]) != LABEL_REF) | |
2005 | emit_insn (gen_rtx_USE (VOIDmode, operands[1])); | |
2006 | ||
ee890fe2 SS |
2007 | /* Darwin uses a special PIC legitimizer. */ |
2008 | if (DEFAULT_ABI == ABI_DARWIN && flag_pic) | |
2009 | { | |
78e1b90d | 2010 | #if TARGET_MACHO |
ee890fe2 SS |
2011 | rtx temp_reg = ((reload_in_progress || reload_completed) |
2012 | ? operands[0] : NULL); | |
2013 | ||
ee890fe2 SS |
2014 | operands[1] = |
2015 | rs6000_machopic_legitimize_pic_address (operands[1], mode, | |
2016 | temp_reg); | |
2017 | #endif | |
2018 | emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1])); | |
2019 | return; | |
2020 | } | |
2021 | ||
fb4d4348 GK |
2022 | /* If we are to limit the number of things we put in the TOC and |
2023 | this is a symbol plus a constant we can add in one insn, | |
2024 | just put the symbol in the TOC and add the constant. Don't do | |
2025 | this if reload is in progress. */ | |
2026 | if (GET_CODE (operands[1]) == CONST | |
2027 | && TARGET_NO_SUM_IN_TOC && ! reload_in_progress | |
2028 | && GET_CODE (XEXP (operands[1], 0)) == PLUS | |
a9098fd0 | 2029 | && add_operand (XEXP (XEXP (operands[1], 0), 1), mode) |
fb4d4348 GK |
2030 | && (GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == LABEL_REF |
2031 | || GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == SYMBOL_REF) | |
2032 | && ! side_effects_p (operands[0])) | |
2033 | { | |
a9098fd0 | 2034 | rtx sym = force_const_mem (mode, XEXP (XEXP (operands[1], 0), 0)); |
fb4d4348 GK |
2035 | rtx other = XEXP (XEXP (operands[1], 0), 1); |
2036 | ||
a9098fd0 GK |
2037 | sym = force_reg (mode, sym); |
2038 | if (mode == SImode) | |
2039 | emit_insn (gen_addsi3 (operands[0], sym, other)); | |
2040 | else | |
2041 | emit_insn (gen_adddi3 (operands[0], sym, other)); | |
fb4d4348 GK |
2042 | return; |
2043 | } | |
2044 | ||
a9098fd0 | 2045 | operands[1] = force_const_mem (mode, operands[1]); |
fb4d4348 GK |
2046 | |
2047 | if (TARGET_TOC | |
d34c5b80 DE |
2048 | && CONSTANT_POOL_EXPR_P (XEXP (operands[1], 0)) |
2049 | && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P ( | |
2050 | get_pool_constant (XEXP (operands[1], 0)), | |
2051 | get_pool_mode (XEXP (operands[1], 0)))) | |
a9098fd0 | 2052 | { |
ba4828e0 RK |
2053 | operands[1] |
2054 | = gen_rtx_MEM (mode, | |
2055 | create_TOC_reference (XEXP (operands[1], 0))); | |
2056 | set_mem_alias_set (operands[1], get_TOC_alias_set ()); | |
fb4d4348 | 2057 | RTX_UNCHANGING_P (operands[1]) = 1; |
a9098fd0 | 2058 | } |
fb4d4348 GK |
2059 | } |
2060 | break; | |
a9098fd0 | 2061 | |
fb4d4348 GK |
2062 | case TImode: |
2063 | if (GET_CODE (operands[0]) == MEM | |
2064 | && GET_CODE (XEXP (operands[0], 0)) != REG | |
2065 | && ! reload_in_progress) | |
792760b9 RK |
2066 | operands[0] |
2067 | = replace_equiv_address (operands[0], | |
2068 | copy_addr_to_reg (XEXP (operands[0], 0))); | |
fb4d4348 GK |
2069 | |
2070 | if (GET_CODE (operands[1]) == MEM | |
2071 | && GET_CODE (XEXP (operands[1], 0)) != REG | |
2072 | && ! reload_in_progress) | |
792760b9 RK |
2073 | operands[1] |
2074 | = replace_equiv_address (operands[1], | |
2075 | copy_addr_to_reg (XEXP (operands[1], 0))); | |
fb4d4348 GK |
2076 | break; |
2077 | ||
2078 | default: | |
2079 | abort (); | |
2080 | } | |
2081 | ||
a9098fd0 GK |
2082 | /* Above, we may have called force_const_mem which may have returned |
2083 | an invalid address. If we can, fix this up; otherwise, reload will | |
2084 | have to deal with it. */ | |
2085 | if (GET_CODE (operands[1]) == MEM | |
2086 | && ! memory_address_p (mode, XEXP (operands[1], 0)) | |
2087 | && ! reload_in_progress) | |
f4ef873c | 2088 | operands[1] = adjust_address (operands[1], mode, 0); |
a9098fd0 | 2089 | |
fb4d4348 | 2090 | emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1])); |
02a4ec28 | 2091 | return; |
fb4d4348 | 2092 | } |
4697a36c MM |
2093 | \f |
2094 | /* Initialize a variable CUM of type CUMULATIVE_ARGS | |
2095 | for a call to a function whose data type is FNTYPE. | |
2096 | For a library call, FNTYPE is 0. | |
2097 | ||
2098 | For incoming args we set the number of arguments in the prototype large | |
1c20ae99 | 2099 | so we never return a PARALLEL. */ |
4697a36c MM |
2100 | |
2101 | void | |
2102 | init_cumulative_args (cum, fntype, libname, incoming) | |
2103 | CUMULATIVE_ARGS *cum; | |
2104 | tree fntype; | |
296b8152 | 2105 | rtx libname ATTRIBUTE_UNUSED; |
4697a36c MM |
2106 | int incoming; |
2107 | { | |
2108 | static CUMULATIVE_ARGS zero_cumulative; | |
2109 | ||
2110 | *cum = zero_cumulative; | |
2111 | cum->words = 0; | |
2112 | cum->fregno = FP_ARG_MIN_REG; | |
2113 | cum->prototype = (fntype && TYPE_ARG_TYPES (fntype)); | |
7509c759 | 2114 | cum->call_cookie = CALL_NORMAL; |
4cc833b7 | 2115 | cum->sysv_gregno = GP_ARG_MIN_REG; |
4697a36c MM |
2116 | |
2117 | if (incoming) | |
bd227acc | 2118 | cum->nargs_prototype = 1000; /* don't return a PARALLEL */ |
4697a36c MM |
2119 | |
2120 | else if (cum->prototype) | |
2121 | cum->nargs_prototype = (list_length (TYPE_ARG_TYPES (fntype)) - 1 | |
2122 | + (TYPE_MODE (TREE_TYPE (fntype)) == BLKmode | |
2123 | || RETURN_IN_MEMORY (TREE_TYPE (fntype)))); | |
2124 | ||
2125 | else | |
2126 | cum->nargs_prototype = 0; | |
2127 | ||
2128 | cum->orig_nargs = cum->nargs_prototype; | |
7509c759 | 2129 | |
9ebbca7d GK |
2130 | /* Check for longcall's */ |
2131 | if (fntype && lookup_attribute ("longcall", TYPE_ATTRIBUTES (fntype))) | |
6a4cee5f MM |
2132 | cum->call_cookie = CALL_LONG; |
2133 | ||
4697a36c MM |
2134 | if (TARGET_DEBUG_ARG) |
2135 | { | |
2136 | fprintf (stderr, "\ninit_cumulative_args:"); | |
2137 | if (fntype) | |
2138 | { | |
2139 | tree ret_type = TREE_TYPE (fntype); | |
2140 | fprintf (stderr, " ret code = %s,", | |
2141 | tree_code_name[ (int)TREE_CODE (ret_type) ]); | |
2142 | } | |
2143 | ||
6a4cee5f MM |
2144 | if (cum->call_cookie & CALL_LONG) |
2145 | fprintf (stderr, " longcall,"); | |
2146 | ||
4697a36c MM |
2147 | fprintf (stderr, " proto = %d, nargs = %d\n", |
2148 | cum->prototype, cum->nargs_prototype); | |
2149 | } | |
2150 | } | |
2151 | \f | |
c229cba9 DE |
2152 | /* If defined, a C expression which determines whether, and in which |
2153 | direction, to pad out an argument with extra space. The value | |
2154 | should be of type `enum direction': either `upward' to pad above | |
2155 | the argument, `downward' to pad below, or `none' to inhibit | |
2156 | padding. | |
2157 | ||
2158 | For the AIX ABI structs are always stored left shifted in their | |
2159 | argument slot. */ | |
2160 | ||
9ebbca7d | 2161 | enum direction |
c229cba9 DE |
2162 | function_arg_padding (mode, type) |
2163 | enum machine_mode mode; | |
2164 | tree type; | |
2165 | { | |
c85f7c16 | 2166 | if (type != 0 && AGGREGATE_TYPE_P (type)) |
9ebbca7d | 2167 | return upward; |
c229cba9 DE |
2168 | |
2169 | /* This is the default definition. */ | |
2170 | return (! BYTES_BIG_ENDIAN | |
9ebbca7d | 2171 | ? upward |
c229cba9 DE |
2172 | : ((mode == BLKmode |
2173 | ? (type && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST | |
2174 | && int_size_in_bytes (type) < (PARM_BOUNDARY / BITS_PER_UNIT)) | |
2175 | : GET_MODE_BITSIZE (mode) < PARM_BOUNDARY) | |
9ebbca7d | 2176 | ? downward : upward)); |
c229cba9 DE |
2177 | } |
2178 | ||
b6c9286a MM |
2179 | /* If defined, a C expression that gives the alignment boundary, in bits, |
2180 | of an argument with the specified mode and type. If it is not defined, | |
2181 | PARM_BOUNDARY is used for all arguments. | |
2182 | ||
2310f99a | 2183 | V.4 wants long longs to be double word aligned. */ |
b6c9286a MM |
2184 | |
2185 | int | |
2186 | function_arg_boundary (mode, type) | |
2187 | enum machine_mode mode; | |
9ebbca7d | 2188 | tree type ATTRIBUTE_UNUSED; |
b6c9286a | 2189 | { |
4cc833b7 RH |
2190 | if ((DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) |
2191 | && (mode == DImode || mode == DFmode)) | |
e1f83b4d | 2192 | return 64; |
9ebbca7d | 2193 | else |
b6c9286a | 2194 | return PARM_BOUNDARY; |
b6c9286a MM |
2195 | } |
2196 | \f | |
4697a36c MM |
2197 | /* Update the data in CUM to advance over an argument |
2198 | of mode MODE and data type TYPE. | |
2199 | (TYPE is null for libcalls where that information may not be available.) */ | |
2200 | ||
2201 | void | |
2202 | function_arg_advance (cum, mode, type, named) | |
2203 | CUMULATIVE_ARGS *cum; | |
2204 | enum machine_mode mode; | |
2205 | tree type; | |
2206 | int named; | |
2207 | { | |
2208 | cum->nargs_prototype--; | |
2209 | ||
c81bebd7 | 2210 | if (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) |
4697a36c | 2211 | { |
4cc833b7 RH |
2212 | if (TARGET_HARD_FLOAT |
2213 | && (mode == SFmode || mode == DFmode)) | |
4697a36c | 2214 | { |
4cc833b7 RH |
2215 | if (cum->fregno <= FP_ARG_V4_MAX_REG) |
2216 | cum->fregno++; | |
2217 | else | |
2218 | { | |
2219 | if (mode == DFmode) | |
2220 | cum->words += cum->words & 1; | |
d34c5b80 | 2221 | cum->words += RS6000_ARG_SIZE (mode, type); |
4cc833b7 | 2222 | } |
4697a36c | 2223 | } |
4cc833b7 RH |
2224 | else |
2225 | { | |
2226 | int n_words; | |
2227 | int gregno = cum->sysv_gregno; | |
2228 | ||
2229 | /* Aggregates and IEEE quad get passed by reference. */ | |
2230 | if ((type && AGGREGATE_TYPE_P (type)) | |
2231 | || mode == TFmode) | |
2232 | n_words = 1; | |
2233 | else | |
d34c5b80 | 2234 | n_words = RS6000_ARG_SIZE (mode, type); |
4cc833b7 RH |
2235 | |
2236 | /* Long long is put in odd registers. */ | |
2237 | if (n_words == 2 && (gregno & 1) == 0) | |
2238 | gregno += 1; | |
2239 | ||
2240 | /* Long long is not split between registers and stack. */ | |
2241 | if (gregno + n_words - 1 > GP_ARG_MAX_REG) | |
2242 | { | |
2243 | /* Long long is aligned on the stack. */ | |
2244 | if (n_words == 2) | |
2245 | cum->words += cum->words & 1; | |
2246 | cum->words += n_words; | |
2247 | } | |
4697a36c | 2248 | |
4cc833b7 RH |
2249 | /* Note: continuing to accumulate gregno past when we've started |
2250 | spilling to the stack indicates the fact that we've started | |
2251 | spilling to the stack to expand_builtin_saveregs. */ | |
2252 | cum->sysv_gregno = gregno + n_words; | |
2253 | } | |
4697a36c | 2254 | |
4cc833b7 RH |
2255 | if (TARGET_DEBUG_ARG) |
2256 | { | |
2257 | fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ", | |
2258 | cum->words, cum->fregno); | |
2259 | fprintf (stderr, "gregno = %2d, nargs = %4d, proto = %d, ", | |
2260 | cum->sysv_gregno, cum->nargs_prototype, cum->prototype); | |
2261 | fprintf (stderr, "mode = %4s, named = %d\n", | |
2262 | GET_MODE_NAME (mode), named); | |
2263 | } | |
4697a36c MM |
2264 | } |
2265 | else | |
4cc833b7 RH |
2266 | { |
2267 | int align = (TARGET_32BIT && (cum->words & 1) != 0 | |
2268 | && function_arg_boundary (mode, type) == 64) ? 1 : 0; | |
d34c5b80 | 2269 | cum->words += align + RS6000_ARG_SIZE (mode, type); |
4697a36c | 2270 | |
d34c5b80 DE |
2271 | if (GET_MODE_CLASS (mode) == MODE_FLOAT && TARGET_HARD_FLOAT) |
2272 | cum->fregno++; | |
4cc833b7 RH |
2273 | |
2274 | if (TARGET_DEBUG_ARG) | |
2275 | { | |
2276 | fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ", | |
2277 | cum->words, cum->fregno); | |
2278 | fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s, ", | |
2279 | cum->nargs_prototype, cum->prototype, GET_MODE_NAME (mode)); | |
2280 | fprintf (stderr, "named = %d, align = %d\n", named, align); | |
2281 | } | |
2282 | } | |
4697a36c MM |
2283 | } |
2284 | \f | |
2285 | /* Determine where to put an argument to a function. | |
2286 | Value is zero to push the argument on the stack, | |
2287 | or a hard register in which to store the argument. | |
2288 | ||
2289 | MODE is the argument's machine mode. | |
2290 | TYPE is the data type of the argument (as a tree). | |
2291 | This is null for libcalls where that information may | |
2292 | not be available. | |
2293 | CUM is a variable of type CUMULATIVE_ARGS which gives info about | |
2294 | the preceding args and about the function being called. | |
2295 | NAMED is nonzero if this argument is a named parameter | |
2296 | (otherwise it is an extra parameter matching an ellipsis). | |
2297 | ||
2298 | On RS/6000 the first eight words of non-FP are normally in registers | |
2299 | and the rest are pushed. Under AIX, the first 13 FP args are in registers. | |
2300 | Under V.4, the first 8 FP args are in registers. | |
2301 | ||
2302 | If this is floating-point and no prototype is specified, we use | |
2303 | both an FP and integer register (or possibly FP reg and stack). Library | |
2304 | functions (when TYPE is zero) always have the proper types for args, | |
2305 | so we can pass the FP value just in one register. emit_library_function | |
1c20ae99 | 2306 | doesn't support PARALLEL anyway. */ |
4697a36c MM |
2307 | |
2308 | struct rtx_def * | |
2309 | function_arg (cum, mode, type, named) | |
2310 | CUMULATIVE_ARGS *cum; | |
2311 | enum machine_mode mode; | |
2312 | tree type; | |
d34c5b80 | 2313 | int named ATTRIBUTE_UNUSED; |
4697a36c | 2314 | { |
4cc833b7 | 2315 | enum rs6000_abi abi = DEFAULT_ABI; |
4697a36c | 2316 | |
4cc833b7 RH |
2317 | /* Return a marker to indicate whether CR1 needs to set or clear the bit |
2318 | that V.4 uses to say fp args were passed in registers. Assume that we | |
2319 | don't need the marker for software floating point, or compiler generated | |
2320 | library calls. */ | |
4697a36c MM |
2321 | if (mode == VOIDmode) |
2322 | { | |
c81bebd7 | 2323 | if ((abi == ABI_V4 || abi == ABI_SOLARIS) |
7509c759 MM |
2324 | && TARGET_HARD_FLOAT |
2325 | && cum->nargs_prototype < 0 | |
4697a36c | 2326 | && type && (cum->prototype || TARGET_NO_PROTOTYPE)) |
7509c759 | 2327 | { |
6a4cee5f MM |
2328 | return GEN_INT (cum->call_cookie |
2329 | | ((cum->fregno == FP_ARG_MIN_REG) | |
2330 | ? CALL_V4_SET_FP_ARGS | |
2331 | : CALL_V4_CLEAR_FP_ARGS)); | |
7509c759 | 2332 | } |
4697a36c | 2333 | |
7509c759 | 2334 | return GEN_INT (cum->call_cookie); |
4697a36c MM |
2335 | } |
2336 | ||
4cc833b7 | 2337 | if (abi == ABI_V4 || abi == ABI_SOLARIS) |
4697a36c | 2338 | { |
4cc833b7 RH |
2339 | if (TARGET_HARD_FLOAT |
2340 | && (mode == SFmode || mode == DFmode)) | |
2341 | { | |
2342 | if (cum->fregno <= FP_ARG_V4_MAX_REG) | |
2343 | return gen_rtx_REG (mode, cum->fregno); | |
2344 | else | |
2345 | return NULL; | |
2346 | } | |
2347 | else | |
2348 | { | |
2349 | int n_words; | |
2350 | int gregno = cum->sysv_gregno; | |
2351 | ||
2352 | /* Aggregates and IEEE quad get passed by reference. */ | |
2353 | if ((type && AGGREGATE_TYPE_P (type)) | |
2354 | || mode == TFmode) | |
2355 | n_words = 1; | |
2356 | else | |
d34c5b80 | 2357 | n_words = RS6000_ARG_SIZE (mode, type); |
4cc833b7 RH |
2358 | |
2359 | /* Long long is put in odd registers. */ | |
2360 | if (n_words == 2 && (gregno & 1) == 0) | |
2361 | gregno += 1; | |
2362 | ||
2363 | /* Long long is not split between registers and stack. */ | |
2364 | if (gregno + n_words - 1 <= GP_ARG_MAX_REG) | |
2365 | return gen_rtx_REG (mode, gregno); | |
2366 | else | |
2367 | return NULL; | |
2368 | } | |
4697a36c | 2369 | } |
4cc833b7 RH |
2370 | else |
2371 | { | |
2372 | int align = (TARGET_32BIT && (cum->words & 1) != 0 | |
2373 | && function_arg_boundary (mode, type) == 64) ? 1 : 0; | |
2374 | int align_words = cum->words + align; | |
4697a36c | 2375 | |
4cc833b7 RH |
2376 | if (type && TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST) |
2377 | return NULL_RTX; | |
2378 | ||
2379 | if (USE_FP_FOR_ARG_P (*cum, mode, type)) | |
2380 | { | |
2381 | if (! type | |
2382 | || ((cum->nargs_prototype > 0) | |
2383 | /* IBM AIX extended its linkage convention definition always | |
2384 | to require FP args after register save area hole on the | |
2385 | stack. */ | |
2386 | && (DEFAULT_ABI != ABI_AIX | |
2387 | || ! TARGET_XL_CALL | |
2388 | || (align_words < GP_ARG_NUM_REG)))) | |
2389 | return gen_rtx_REG (mode, cum->fregno); | |
2390 | ||
2391 | return gen_rtx_PARALLEL (mode, | |
2392 | gen_rtvec (2, | |
39403d82 | 2393 | gen_rtx_EXPR_LIST (VOIDmode, |
1c20ae99 JW |
2394 | ((align_words >= GP_ARG_NUM_REG) |
2395 | ? NULL_RTX | |
2396 | : (align_words | |
d34c5b80 | 2397 | + RS6000_ARG_SIZE (mode, type) |
1c20ae99 JW |
2398 | > GP_ARG_NUM_REG |
2399 | /* If this is partially on the stack, then | |
2400 | we only include the portion actually | |
2401 | in registers here. */ | |
39403d82 | 2402 | ? gen_rtx_REG (SImode, |
1c20ae99 | 2403 | GP_ARG_MIN_REG + align_words) |
39403d82 | 2404 | : gen_rtx_REG (mode, |
1c20ae99 JW |
2405 | GP_ARG_MIN_REG + align_words))), |
2406 | const0_rtx), | |
39403d82 DE |
2407 | gen_rtx_EXPR_LIST (VOIDmode, |
2408 | gen_rtx_REG (mode, cum->fregno), | |
1c20ae99 | 2409 | const0_rtx))); |
4cc833b7 RH |
2410 | } |
2411 | else if (align_words < GP_ARG_NUM_REG) | |
2412 | return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words); | |
2413 | else | |
2414 | return NULL_RTX; | |
4697a36c | 2415 | } |
4697a36c MM |
2416 | } |
2417 | \f | |
2418 | /* For an arg passed partly in registers and partly in memory, | |
2419 | this is the number of registers used. | |
2420 | For args passed entirely in registers or entirely in memory, zero. */ | |
2421 | ||
2422 | int | |
2423 | function_arg_partial_nregs (cum, mode, type, named) | |
2424 | CUMULATIVE_ARGS *cum; | |
2425 | enum machine_mode mode; | |
2426 | tree type; | |
d34c5b80 | 2427 | int named ATTRIBUTE_UNUSED; |
4697a36c | 2428 | { |
c81bebd7 | 2429 | if (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) |
4697a36c | 2430 | return 0; |
4697a36c MM |
2431 | |
2432 | if (USE_FP_FOR_ARG_P (*cum, mode, type)) | |
2433 | { | |
2434 | if (cum->nargs_prototype >= 0) | |
2435 | return 0; | |
2436 | } | |
2437 | ||
2438 | if (cum->words < GP_ARG_NUM_REG | |
d34c5b80 | 2439 | && GP_ARG_NUM_REG < (cum->words + RS6000_ARG_SIZE (mode, type))) |
4697a36c MM |
2440 | { |
2441 | int ret = GP_ARG_NUM_REG - cum->words; | |
2442 | if (ret && TARGET_DEBUG_ARG) | |
2443 | fprintf (stderr, "function_arg_partial_nregs: %d\n", ret); | |
2444 | ||
2445 | return ret; | |
2446 | } | |
2447 | ||
2448 | return 0; | |
2449 | } | |
2450 | \f | |
2451 | /* A C expression that indicates when an argument must be passed by | |
2452 | reference. If nonzero for an argument, a copy of that argument is | |
2453 | made in memory and a pointer to the argument is passed instead of | |
2454 | the argument itself. The pointer is passed in whatever way is | |
2455 | appropriate for passing a pointer to that type. | |
2456 | ||
2457 | Under V.4, structures and unions are passed by reference. */ | |
2458 | ||
2459 | int | |
2460 | function_arg_pass_by_reference (cum, mode, type, named) | |
296b8152 KG |
2461 | CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED; |
2462 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
4697a36c | 2463 | tree type; |
296b8152 | 2464 | int named ATTRIBUTE_UNUSED; |
4697a36c | 2465 | { |
c81bebd7 | 2466 | if ((DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) |
4cc833b7 RH |
2467 | && ((type && AGGREGATE_TYPE_P (type)) |
2468 | || mode == TFmode)) | |
4697a36c MM |
2469 | { |
2470 | if (TARGET_DEBUG_ARG) | |
2471 | fprintf (stderr, "function_arg_pass_by_reference: aggregate\n"); | |
2472 | ||
2473 | return 1; | |
2474 | } | |
4697a36c MM |
2475 | |
2476 | return 0; | |
2477 | } | |
4697a36c MM |
2478 | \f |
2479 | /* Perform any needed actions needed for a function that is receiving a | |
2480 | variable number of arguments. | |
2481 | ||
2482 | CUM is as above. | |
2483 | ||
2484 | MODE and TYPE are the mode and type of the current parameter. | |
2485 | ||
2486 | PRETEND_SIZE is a variable that should be set to the amount of stack | |
2487 | that must be pushed by the prolog to pretend that our caller pushed | |
2488 | it. | |
2489 | ||
2490 | Normally, this macro will push all remaining incoming registers on the | |
2491 | stack and set PRETEND_SIZE to the length of the registers pushed. */ | |
2492 | ||
2493 | void | |
2494 | setup_incoming_varargs (cum, mode, type, pretend_size, no_rtl) | |
2495 | CUMULATIVE_ARGS *cum; | |
2496 | enum machine_mode mode; | |
2497 | tree type; | |
2498 | int *pretend_size; | |
2499 | int no_rtl; | |
2500 | ||
2501 | { | |
4cc833b7 RH |
2502 | CUMULATIVE_ARGS next_cum; |
2503 | int reg_size = TARGET_32BIT ? 4 : 8; | |
ca5adc63 | 2504 | rtx save_area = NULL_RTX, mem; |
dfafc897 | 2505 | int first_reg_offset, set; |
d34c5b80 DE |
2506 | tree fntype; |
2507 | int stdarg_p; | |
4697a36c | 2508 | |
d34c5b80 DE |
2509 | fntype = TREE_TYPE (current_function_decl); |
2510 | stdarg_p = (TYPE_ARG_TYPES (fntype) != 0 | |
2511 | && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype))) | |
2512 | != void_type_node)); | |
4cc833b7 | 2513 | |
d34c5b80 DE |
2514 | /* For varargs, we do not want to skip the dummy va_dcl argument. |
2515 | For stdargs, we do want to skip the last named argument. */ | |
2516 | next_cum = *cum; | |
2517 | if (stdarg_p) | |
2518 | function_arg_advance (&next_cum, mode, type, 1); | |
4cc833b7 | 2519 | |
d34c5b80 DE |
2520 | if (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) |
2521 | { | |
4cc833b7 RH |
2522 | /* Indicate to allocate space on the stack for varargs save area. */ |
2523 | /* ??? Does this really have to be located at a magic spot on the | |
2524 | stack, or can we allocate this with assign_stack_local instead. */ | |
00dba523 | 2525 | cfun->machine->sysv_varargs_p = 1; |
60e2d0ca | 2526 | if (! no_rtl) |
2c4974b7 | 2527 | save_area = plus_constant (virtual_stack_vars_rtx, |
bd227acc | 2528 | - RS6000_VARARGS_SIZE); |
4cc833b7 RH |
2529 | |
2530 | first_reg_offset = next_cum.sysv_gregno - GP_ARG_MIN_REG; | |
4697a36c | 2531 | } |
60e2d0ca | 2532 | else |
4697a36c | 2533 | { |
d34c5b80 | 2534 | first_reg_offset = next_cum.words; |
4cc833b7 | 2535 | save_area = virtual_incoming_args_rtx; |
00dba523 | 2536 | cfun->machine->sysv_varargs_p = 0; |
4697a36c MM |
2537 | |
2538 | if (MUST_PASS_IN_STACK (mode, type)) | |
d34c5b80 | 2539 | first_reg_offset += RS6000_ARG_SIZE (TYPE_MODE (type), type); |
4cc833b7 | 2540 | } |
4697a36c | 2541 | |
dfafc897 | 2542 | set = get_varargs_alias_set (); |
c81fc13e | 2543 | if (! no_rtl && first_reg_offset < GP_ARG_NUM_REG) |
4cc833b7 | 2544 | { |
dfafc897 FS |
2545 | mem = gen_rtx_MEM (BLKmode, |
2546 | plus_constant (save_area, | |
2547 | first_reg_offset * reg_size)), | |
ba4828e0 | 2548 | set_mem_alias_set (mem, set); |
dfafc897 | 2549 | |
4cc833b7 | 2550 | move_block_from_reg |
dfafc897 | 2551 | (GP_ARG_MIN_REG + first_reg_offset, mem, |
4cc833b7 RH |
2552 | GP_ARG_NUM_REG - first_reg_offset, |
2553 | (GP_ARG_NUM_REG - first_reg_offset) * UNITS_PER_WORD); | |
2554 | ||
2555 | /* ??? Does ABI_V4 need this at all? */ | |
4697a36c MM |
2556 | *pretend_size = (GP_ARG_NUM_REG - first_reg_offset) * UNITS_PER_WORD; |
2557 | } | |
2558 | ||
4697a36c | 2559 | /* Save FP registers if needed. */ |
4cc833b7 | 2560 | if ((DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) |
c81fc13e | 2561 | && TARGET_HARD_FLOAT && ! no_rtl |
4cc833b7 | 2562 | && next_cum.fregno <= FP_ARG_V4_MAX_REG) |
4697a36c | 2563 | { |
4cc833b7 | 2564 | int fregno = next_cum.fregno; |
9ebbca7d | 2565 | rtx cr1 = gen_rtx_REG (CCmode, CR1_REGNO); |
4cc833b7 RH |
2566 | rtx lab = gen_label_rtx (); |
2567 | int off = (GP_ARG_NUM_REG * reg_size) + ((fregno - FP_ARG_MIN_REG) * 8); | |
4697a36c | 2568 | |
4cc833b7 | 2569 | emit_jump_insn (gen_rtx_SET (VOIDmode, |
4697a36c | 2570 | pc_rtx, |
39403d82 | 2571 | gen_rtx_IF_THEN_ELSE (VOIDmode, |
4cc833b7 RH |
2572 | gen_rtx_NE (VOIDmode, cr1, |
2573 | const0_rtx), | |
39403d82 | 2574 | gen_rtx_LABEL_REF (VOIDmode, lab), |
4697a36c MM |
2575 | pc_rtx))); |
2576 | ||
4cc833b7 RH |
2577 | while (fregno <= FP_ARG_V4_MAX_REG) |
2578 | { | |
dfafc897 | 2579 | mem = gen_rtx_MEM (DFmode, plus_constant (save_area, off)); |
ba4828e0 | 2580 | set_mem_alias_set (mem, set); |
dfafc897 | 2581 | emit_move_insn (mem, gen_rtx_REG (DFmode, fregno)); |
4cc833b7 RH |
2582 | fregno++; |
2583 | off += 8; | |
4697a36c | 2584 | } |
4cc833b7 RH |
2585 | |
2586 | emit_label (lab); | |
4697a36c | 2587 | } |
4697a36c | 2588 | } |
4697a36c | 2589 | |
dfafc897 | 2590 | /* Create the va_list data type. */ |
2c4974b7 | 2591 | |
dfafc897 FS |
2592 | tree |
2593 | rs6000_build_va_list () | |
2594 | { | |
bab45a51 | 2595 | tree f_gpr, f_fpr, f_ovf, f_sav, record, type_decl; |
4697a36c | 2596 | |
9ebbca7d GK |
2597 | /* For AIX, prefer 'char *' because that's what the system |
2598 | header files like. */ | |
dfafc897 | 2599 | if (DEFAULT_ABI != ABI_V4 && DEFAULT_ABI != ABI_SOLARIS) |
9ebbca7d | 2600 | return build_pointer_type (char_type_node); |
dfafc897 | 2601 | |
0f4fd75d | 2602 | record = make_lang_type (RECORD_TYPE); |
bab45a51 | 2603 | type_decl = build_decl (TYPE_DECL, get_identifier ("__va_list_tag"), record); |
0f4fd75d | 2604 | |
9ebbca7d GK |
2605 | f_gpr = build_decl (FIELD_DECL, get_identifier ("gpr"), |
2606 | unsigned_char_type_node); | |
2607 | f_fpr = build_decl (FIELD_DECL, get_identifier ("fpr"), | |
2608 | unsigned_char_type_node); | |
dfafc897 FS |
2609 | f_ovf = build_decl (FIELD_DECL, get_identifier ("overflow_arg_area"), |
2610 | ptr_type_node); | |
2611 | f_sav = build_decl (FIELD_DECL, get_identifier ("reg_save_area"), | |
2612 | ptr_type_node); | |
2613 | ||
2614 | DECL_FIELD_CONTEXT (f_gpr) = record; | |
2615 | DECL_FIELD_CONTEXT (f_fpr) = record; | |
2616 | DECL_FIELD_CONTEXT (f_ovf) = record; | |
2617 | DECL_FIELD_CONTEXT (f_sav) = record; | |
2618 | ||
bab45a51 FS |
2619 | TREE_CHAIN (record) = type_decl; |
2620 | TYPE_NAME (record) = type_decl; | |
dfafc897 FS |
2621 | TYPE_FIELDS (record) = f_gpr; |
2622 | TREE_CHAIN (f_gpr) = f_fpr; | |
2623 | TREE_CHAIN (f_fpr) = f_ovf; | |
2624 | TREE_CHAIN (f_ovf) = f_sav; | |
2625 | ||
2626 | layout_type (record); | |
2627 | ||
2628 | /* The correct type is an array type of one element. */ | |
2629 | return build_array_type (record, build_index_type (size_zero_node)); | |
2630 | } | |
2631 | ||
2632 | /* Implement va_start. */ | |
2633 | ||
2634 | void | |
2635 | rs6000_va_start (stdarg_p, valist, nextarg) | |
2636 | int stdarg_p; | |
2637 | tree valist; | |
2638 | rtx nextarg; | |
4697a36c | 2639 | { |
dfafc897 FS |
2640 | HOST_WIDE_INT words, n_gpr, n_fpr; |
2641 | tree f_gpr, f_fpr, f_ovf, f_sav; | |
2642 | tree gpr, fpr, ovf, sav, t; | |
2c4974b7 | 2643 | |
dfafc897 | 2644 | /* Only SVR4 needs something special. */ |
2c4974b7 | 2645 | if (DEFAULT_ABI != ABI_V4 && DEFAULT_ABI != ABI_SOLARIS) |
dfafc897 FS |
2646 | { |
2647 | std_expand_builtin_va_start (stdarg_p, valist, nextarg); | |
2648 | return; | |
2649 | } | |
2650 | ||
973a648b | 2651 | f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node)); |
dfafc897 FS |
2652 | f_fpr = TREE_CHAIN (f_gpr); |
2653 | f_ovf = TREE_CHAIN (f_fpr); | |
2654 | f_sav = TREE_CHAIN (f_ovf); | |
2655 | ||
8ebecc3b | 2656 | valist = build1 (INDIRECT_REF, TREE_TYPE (TREE_TYPE (valist)), valist); |
dfafc897 FS |
2657 | gpr = build (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr); |
2658 | fpr = build (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr); | |
2659 | ovf = build (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf); | |
2660 | sav = build (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav); | |
2661 | ||
2662 | /* Count number of gp and fp argument registers used. */ | |
4cc833b7 | 2663 | words = current_function_args_info.words; |
dfafc897 FS |
2664 | n_gpr = current_function_args_info.sysv_gregno - GP_ARG_MIN_REG; |
2665 | n_fpr = current_function_args_info.fregno - FP_ARG_MIN_REG; | |
2666 | ||
2667 | if (TARGET_DEBUG_ARG) | |
78e1b90d DE |
2668 | { |
2669 | fputs ("va_start: words = ", stderr); | |
2670 | fprintf (stderr, HOST_WIDE_INT_PRINT_DEC, words); | |
2671 | fputs (", n_gpr = ", stderr); | |
2672 | fprintf (stderr, HOST_WIDE_INT_PRINT_DEC, n_gpr); | |
2673 | fputs (", n_fpr = ", stderr); | |
2674 | fprintf (stderr, HOST_WIDE_INT_PRINT_DEC, n_fpr); | |
2675 | putc ('\n', stderr); | |
2676 | } | |
dfafc897 FS |
2677 | |
2678 | t = build (MODIFY_EXPR, TREE_TYPE (gpr), gpr, build_int_2 (n_gpr, 0)); | |
2679 | TREE_SIDE_EFFECTS (t) = 1; | |
2680 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
2681 | ||
2682 | t = build (MODIFY_EXPR, TREE_TYPE (fpr), fpr, build_int_2 (n_fpr, 0)); | |
2683 | TREE_SIDE_EFFECTS (t) = 1; | |
2684 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
2685 | ||
2686 | /* Find the overflow area. */ | |
2687 | t = make_tree (TREE_TYPE (ovf), virtual_incoming_args_rtx); | |
2688 | if (words != 0) | |
2689 | t = build (PLUS_EXPR, TREE_TYPE (ovf), t, | |
2690 | build_int_2 (words * UNITS_PER_WORD, 0)); | |
2691 | t = build (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t); | |
2692 | TREE_SIDE_EFFECTS (t) = 1; | |
2693 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
2694 | ||
2695 | /* Find the register save area. */ | |
2696 | t = make_tree (TREE_TYPE (sav), virtual_stack_vars_rtx); | |
2697 | t = build (PLUS_EXPR, TREE_TYPE (sav), t, | |
2698 | build_int_2 (-RS6000_VARARGS_SIZE, -1)); | |
2699 | t = build (MODIFY_EXPR, TREE_TYPE (sav), sav, t); | |
2700 | TREE_SIDE_EFFECTS (t) = 1; | |
2701 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
2702 | } | |
2703 | ||
2704 | /* Implement va_arg. */ | |
2705 | ||
2706 | rtx | |
2707 | rs6000_va_arg (valist, type) | |
2708 | tree valist, type; | |
2709 | { | |
2710 | tree f_gpr, f_fpr, f_ovf, f_sav; | |
2711 | tree gpr, fpr, ovf, sav, reg, t, u; | |
2712 | int indirect_p, size, rsize, n_reg, sav_ofs, sav_scale; | |
2713 | rtx lab_false, lab_over, addr_rtx, r; | |
2714 | ||
9ebbca7d GK |
2715 | /* For AIX, the rule is that structures are passed left-aligned in |
2716 | their stack slot. However, GCC does not presently do this: | |
2717 | structures which are the same size as integer types are passed | |
2718 | right-aligned, as if they were in fact integers. This only | |
2719 | matters for structures of size 1 or 2, or 4 when TARGET_64BIT. */ | |
dfafc897 | 2720 | if (DEFAULT_ABI != ABI_V4 && DEFAULT_ABI != ABI_SOLARIS) |
9ebbca7d GK |
2721 | { |
2722 | HOST_WIDE_INT align, rounded_size; | |
2723 | enum machine_mode mode; | |
2724 | tree addr_tree; | |
2725 | ||
2726 | /* Compute the rounded size of the type. */ | |
2727 | align = PARM_BOUNDARY / BITS_PER_UNIT; | |
2728 | rounded_size = (((int_size_in_bytes (type) + align - 1) / align) | |
2729 | * align); | |
2730 | ||
2731 | addr_tree = valist; | |
2732 | ||
2733 | mode = TYPE_MODE (type); | |
2734 | if (mode != BLKmode) | |
2735 | { | |
2736 | HOST_WIDE_INT adj; | |
2737 | adj = TREE_INT_CST_LOW (TYPE_SIZE (type)) / BITS_PER_UNIT; | |
2738 | if (rounded_size > align) | |
2739 | adj = rounded_size; | |
2740 | ||
2741 | addr_tree = build (PLUS_EXPR, TREE_TYPE (addr_tree), addr_tree, | |
2742 | build_int_2 (rounded_size - adj, 0)); | |
2743 | } | |
2744 | ||
2745 | addr_rtx = expand_expr (addr_tree, NULL_RTX, Pmode, EXPAND_NORMAL); | |
2746 | addr_rtx = copy_to_reg (addr_rtx); | |
2747 | ||
2748 | /* Compute new value for AP. */ | |
2749 | t = build (MODIFY_EXPR, TREE_TYPE (valist), valist, | |
2750 | build (PLUS_EXPR, TREE_TYPE (valist), valist, | |
2751 | build_int_2 (rounded_size, 0))); | |
2752 | TREE_SIDE_EFFECTS (t) = 1; | |
2753 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
2754 | ||
2755 | return addr_rtx; | |
2756 | } | |
dfafc897 | 2757 | |
973a648b | 2758 | f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node)); |
dfafc897 FS |
2759 | f_fpr = TREE_CHAIN (f_gpr); |
2760 | f_ovf = TREE_CHAIN (f_fpr); | |
2761 | f_sav = TREE_CHAIN (f_ovf); | |
2762 | ||
8ebecc3b | 2763 | valist = build1 (INDIRECT_REF, TREE_TYPE (TREE_TYPE (valist)), valist); |
dfafc897 FS |
2764 | gpr = build (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr); |
2765 | fpr = build (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr); | |
2766 | ovf = build (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf); | |
2767 | sav = build (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav); | |
2768 | ||
2769 | size = int_size_in_bytes (type); | |
2770 | rsize = (size + UNITS_PER_WORD - 1) / UNITS_PER_WORD; | |
4cc833b7 | 2771 | |
dfafc897 | 2772 | if (AGGREGATE_TYPE_P (type) || TYPE_MODE (type) == TFmode) |
4cc833b7 | 2773 | { |
dfafc897 FS |
2774 | /* Aggregates and long doubles are passed by reference. */ |
2775 | indirect_p = 1; | |
2776 | reg = gpr; | |
2777 | n_reg = 1; | |
2778 | sav_ofs = 0; | |
2779 | sav_scale = 4; | |
2780 | size = rsize = UNITS_PER_WORD; | |
2781 | } | |
2782 | else if (FLOAT_TYPE_P (type) && ! TARGET_SOFT_FLOAT) | |
2783 | { | |
2784 | /* FP args go in FP registers, if present. */ | |
2785 | indirect_p = 0; | |
2786 | reg = fpr; | |
2787 | n_reg = 1; | |
2788 | sav_ofs = 8*4; | |
2789 | sav_scale = 8; | |
4cc833b7 | 2790 | } |
dfafc897 FS |
2791 | else |
2792 | { | |
2793 | /* Otherwise into GP registers. */ | |
2794 | indirect_p = 0; | |
2795 | reg = gpr; | |
2796 | n_reg = rsize; | |
2797 | sav_ofs = 0; | |
2798 | sav_scale = 4; | |
2799 | } | |
2800 | ||
2801 | /* | |
2802 | * Pull the value out of the saved registers ... | |
2803 | */ | |
2804 | ||
2805 | lab_false = gen_label_rtx (); | |
2806 | lab_over = gen_label_rtx (); | |
2807 | addr_rtx = gen_reg_rtx (Pmode); | |
2808 | ||
2809 | emit_cmp_and_jump_insns (expand_expr (reg, NULL_RTX, QImode, EXPAND_NORMAL), | |
2810 | GEN_INT (8 - n_reg + 1), | |
2811 | GE, const1_rtx, QImode, 1, 1, lab_false); | |
2c4974b7 | 2812 | |
dfafc897 FS |
2813 | /* Long long is aligned in the registers. */ |
2814 | if (n_reg > 1) | |
2c4974b7 | 2815 | { |
dfafc897 FS |
2816 | u = build (BIT_AND_EXPR, TREE_TYPE (reg), reg, |
2817 | build_int_2 (n_reg - 1, 0)); | |
2818 | u = build (PLUS_EXPR, TREE_TYPE (reg), reg, u); | |
2819 | u = build (MODIFY_EXPR, TREE_TYPE (reg), reg, u); | |
2820 | TREE_SIDE_EFFECTS (u) = 1; | |
2821 | expand_expr (u, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
2c4974b7 | 2822 | } |
dfafc897 FS |
2823 | |
2824 | if (sav_ofs) | |
2825 | t = build (PLUS_EXPR, ptr_type_node, sav, build_int_2 (sav_ofs, 0)); | |
2c4974b7 | 2826 | else |
dfafc897 | 2827 | t = sav; |
2c4974b7 | 2828 | |
dfafc897 FS |
2829 | u = build (POSTINCREMENT_EXPR, TREE_TYPE (reg), reg, build_int_2 (n_reg, 0)); |
2830 | TREE_SIDE_EFFECTS (u) = 1; | |
2c4974b7 | 2831 | |
dfafc897 FS |
2832 | u = build1 (CONVERT_EXPR, integer_type_node, u); |
2833 | TREE_SIDE_EFFECTS (u) = 1; | |
2c4974b7 | 2834 | |
dfafc897 FS |
2835 | u = build (MULT_EXPR, integer_type_node, u, build_int_2 (sav_scale, 0)); |
2836 | TREE_SIDE_EFFECTS (u) = 1; | |
2837 | ||
2838 | t = build (PLUS_EXPR, ptr_type_node, t, u); | |
2839 | TREE_SIDE_EFFECTS (t) = 1; | |
2840 | ||
2841 | r = expand_expr (t, addr_rtx, Pmode, EXPAND_NORMAL); | |
2842 | if (r != addr_rtx) | |
2843 | emit_move_insn (addr_rtx, r); | |
2844 | ||
2845 | emit_jump_insn (gen_jump (lab_over)); | |
2846 | emit_barrier (); | |
2847 | emit_label (lab_false); | |
2848 | ||
2849 | /* | |
2850 | * ... otherwise out of the overflow area. | |
2851 | */ | |
2852 | ||
2853 | /* Make sure we don't find reg 7 for the next int arg. */ | |
2854 | if (n_reg > 1) | |
2855 | { | |
2856 | t = build (MODIFY_EXPR, TREE_TYPE (reg), reg, build_int_2 (8, 0)); | |
2857 | TREE_SIDE_EFFECTS (t) = 1; | |
2858 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
2859 | } | |
2860 | ||
2861 | /* Care for on-stack alignment if needed. */ | |
2862 | if (rsize <= 1) | |
2863 | t = ovf; | |
2864 | else | |
2865 | { | |
2866 | t = build (PLUS_EXPR, TREE_TYPE (ovf), ovf, build_int_2 (7, 0)); | |
2867 | t = build (BIT_AND_EXPR, TREE_TYPE (t), t, build_int_2 (-8, -1)); | |
2868 | } | |
2869 | t = save_expr (t); | |
2870 | ||
2871 | r = expand_expr (t, addr_rtx, Pmode, EXPAND_NORMAL); | |
2872 | if (r != addr_rtx) | |
2873 | emit_move_insn (addr_rtx, r); | |
2874 | ||
2875 | t = build (PLUS_EXPR, TREE_TYPE (t), t, build_int_2 (size, 0)); | |
2876 | t = build (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t); | |
2877 | TREE_SIDE_EFFECTS (t) = 1; | |
2878 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
2879 | ||
2880 | emit_label (lab_over); | |
2881 | ||
2882 | if (indirect_p) | |
2883 | { | |
2884 | r = gen_rtx_MEM (Pmode, addr_rtx); | |
ba4828e0 | 2885 | set_mem_alias_set (r, get_varargs_alias_set ()); |
dfafc897 FS |
2886 | emit_move_insn (addr_rtx, r); |
2887 | } | |
2888 | ||
2889 | return addr_rtx; | |
4697a36c | 2890 | } |
5b5040b9 RK |
2891 | \f |
2892 | /* Generate a memory reference for expand_block_move, copying volatile, | |
2893 | and other bits from an original memory reference. */ | |
2894 | ||
2895 | static rtx | |
2896 | expand_block_move_mem (mode, addr, orig_mem) | |
2897 | enum machine_mode mode; | |
2898 | rtx addr; | |
2899 | rtx orig_mem; | |
2900 | { | |
39403d82 | 2901 | rtx mem = gen_rtx_MEM (mode, addr); |
b6c9286a | 2902 | |
c6df88cb | 2903 | MEM_COPY_ATTRIBUTES (mem, orig_mem); |
b6c9286a MM |
2904 | #ifdef MEM_UNALIGNED_P |
2905 | MEM_UNALIGNED_P (mem) = MEM_UNALIGNED_P (orig_mem); | |
2906 | #endif | |
5b5040b9 RK |
2907 | return mem; |
2908 | } | |
2909 | ||
7e69e155 MM |
2910 | /* Expand a block move operation, and return 1 if successful. Return 0 |
2911 | if we should let the compiler generate normal code. | |
2912 | ||
2913 | operands[0] is the destination | |
2914 | operands[1] is the source | |
2915 | operands[2] is the length | |
2916 | operands[3] is the alignment */ | |
2917 | ||
3933e0e1 MM |
2918 | #define MAX_MOVE_REG 4 |
2919 | ||
7e69e155 MM |
2920 | int |
2921 | expand_block_move (operands) | |
2922 | rtx operands[]; | |
2923 | { | |
b6c9286a MM |
2924 | rtx orig_dest = operands[0]; |
2925 | rtx orig_src = operands[1]; | |
7e69e155 | 2926 | rtx bytes_rtx = operands[2]; |
7e69e155 | 2927 | rtx align_rtx = operands[3]; |
3933e0e1 | 2928 | int constp = (GET_CODE (bytes_rtx) == CONST_INT); |
5ee95df6 | 2929 | int align; |
3933e0e1 MM |
2930 | int bytes; |
2931 | int offset; | |
2932 | int num_reg; | |
2933 | int i; | |
7e69e155 MM |
2934 | rtx src_reg; |
2935 | rtx dest_reg; | |
3933e0e1 MM |
2936 | rtx src_addr; |
2937 | rtx dest_addr; | |
7e69e155 | 2938 | rtx tmp_reg; |
3933e0e1 | 2939 | rtx stores[MAX_MOVE_REG]; |
7e69e155 MM |
2940 | int move_bytes; |
2941 | ||
3933e0e1 | 2942 | /* If this is not a fixed size move, just call memcpy */ |
cc0d9ba8 | 2943 | if (! constp) |
3933e0e1 MM |
2944 | return 0; |
2945 | ||
5ee95df6 FS |
2946 | /* If this is not a fixed size alignment, abort */ |
2947 | if (GET_CODE (align_rtx) != CONST_INT) | |
2948 | abort (); | |
2949 | align = INTVAL (align_rtx); | |
2950 | ||
7e69e155 | 2951 | /* Anything to move? */ |
3933e0e1 MM |
2952 | bytes = INTVAL (bytes_rtx); |
2953 | if (bytes <= 0) | |
7e69e155 MM |
2954 | return 1; |
2955 | ||
3933e0e1 MM |
2956 | /* Don't support real large moves. If string instructions are not used, |
2957 | then don't generate more than 8 loads. */ | |
2958 | if (TARGET_STRING) | |
2959 | { | |
c81fc13e | 2960 | if (bytes > 8*4) |
3933e0e1 MM |
2961 | return 0; |
2962 | } | |
cc0d9ba8 | 2963 | else if (! STRICT_ALIGNMENT) |
3933e0e1 | 2964 | { |
c81fc13e DE |
2965 | if (TARGET_POWERPC64 && align >= 4) |
2966 | { | |
2967 | if (bytes > 8*8) | |
2968 | return 0; | |
2969 | } | |
2970 | else | |
2971 | if (bytes > 8*4) | |
2972 | return 0; | |
3933e0e1 MM |
2973 | } |
2974 | else if (bytes > 8*align) | |
7e69e155 MM |
2975 | return 0; |
2976 | ||
2977 | /* Move the address into scratch registers. */ | |
b6c9286a MM |
2978 | dest_reg = copy_addr_to_reg (XEXP (orig_dest, 0)); |
2979 | src_reg = copy_addr_to_reg (XEXP (orig_src, 0)); | |
7e69e155 | 2980 | |
3933e0e1 | 2981 | if (TARGET_STRING) /* string instructions are available */ |
7e69e155 | 2982 | { |
3933e0e1 | 2983 | for ( ; bytes > 0; bytes -= move_bytes) |
7e69e155 | 2984 | { |
3933e0e1 | 2985 | if (bytes > 24 /* move up to 32 bytes at a time */ |
cc0d9ba8 DE |
2986 | && ! fixed_regs[5] |
2987 | && ! fixed_regs[6] | |
2988 | && ! fixed_regs[7] | |
2989 | && ! fixed_regs[8] | |
2990 | && ! fixed_regs[9] | |
2991 | && ! fixed_regs[10] | |
2992 | && ! fixed_regs[11] | |
2993 | && ! fixed_regs[12]) | |
3933e0e1 MM |
2994 | { |
2995 | move_bytes = (bytes > 32) ? 32 : bytes; | |
cc0d9ba8 DE |
2996 | emit_insn (gen_movstrsi_8reg (expand_block_move_mem (BLKmode, |
2997 | dest_reg, | |
2998 | orig_dest), | |
2999 | expand_block_move_mem (BLKmode, | |
3000 | src_reg, | |
3001 | orig_src), | |
3002 | GEN_INT ((move_bytes == 32) | |
3003 | ? 0 : move_bytes), | |
4c64a852 | 3004 | align_rtx)); |
3933e0e1 MM |
3005 | } |
3006 | else if (bytes > 16 /* move up to 24 bytes at a time */ | |
f9562f27 DE |
3007 | && ! fixed_regs[5] |
3008 | && ! fixed_regs[6] | |
cc0d9ba8 DE |
3009 | && ! fixed_regs[7] |
3010 | && ! fixed_regs[8] | |
3011 | && ! fixed_regs[9] | |
f9562f27 | 3012 | && ! fixed_regs[10]) |
3933e0e1 MM |
3013 | { |
3014 | move_bytes = (bytes > 24) ? 24 : bytes; | |
cc0d9ba8 DE |
3015 | emit_insn (gen_movstrsi_6reg (expand_block_move_mem (BLKmode, |
3016 | dest_reg, | |
3017 | orig_dest), | |
3018 | expand_block_move_mem (BLKmode, | |
3019 | src_reg, | |
3020 | orig_src), | |
3933e0e1 | 3021 | GEN_INT (move_bytes), |
4c64a852 | 3022 | align_rtx)); |
3933e0e1 MM |
3023 | } |
3024 | else if (bytes > 8 /* move up to 16 bytes at a time */ | |
f9562f27 DE |
3025 | && ! fixed_regs[5] |
3026 | && ! fixed_regs[6] | |
3027 | && ! fixed_regs[7] | |
3028 | && ! fixed_regs[8]) | |
3933e0e1 MM |
3029 | { |
3030 | move_bytes = (bytes > 16) ? 16 : bytes; | |
cc0d9ba8 DE |
3031 | emit_insn (gen_movstrsi_4reg (expand_block_move_mem (BLKmode, |
3032 | dest_reg, | |
3033 | orig_dest), | |
3034 | expand_block_move_mem (BLKmode, | |
3035 | src_reg, | |
3036 | orig_src), | |
3933e0e1 | 3037 | GEN_INT (move_bytes), |
4c64a852 | 3038 | align_rtx)); |
3933e0e1 | 3039 | } |
acad7ed3 DE |
3040 | else if (bytes >= 8 && TARGET_POWERPC64 |
3041 | /* 64-bit loads and stores require word-aligned displacements. */ | |
3042 | && (align >= 8 || (! STRICT_ALIGNMENT && align >= 4))) | |
3043 | { | |
3044 | move_bytes = 8; | |
3045 | tmp_reg = gen_reg_rtx (DImode); | |
3046 | emit_move_insn (tmp_reg, | |
3047 | expand_block_move_mem (DImode, | |
2eba1afa | 3048 | src_reg, orig_src)); |
acad7ed3 | 3049 | emit_move_insn (expand_block_move_mem (DImode, |
2eba1afa | 3050 | dest_reg, orig_dest), |
acad7ed3 DE |
3051 | tmp_reg); |
3052 | } | |
3053 | else if (bytes > 4) | |
3933e0e1 MM |
3054 | { /* move up to 8 bytes at a time */ |
3055 | move_bytes = (bytes > 8) ? 8 : bytes; | |
cc0d9ba8 DE |
3056 | emit_insn (gen_movstrsi_2reg (expand_block_move_mem (BLKmode, |
3057 | dest_reg, | |
3058 | orig_dest), | |
3059 | expand_block_move_mem (BLKmode, | |
3060 | src_reg, | |
3061 | orig_src), | |
3933e0e1 | 3062 | GEN_INT (move_bytes), |
4c64a852 | 3063 | align_rtx)); |
3933e0e1 | 3064 | } |
cc0d9ba8 | 3065 | else if (bytes >= 4 && (align >= 4 || ! STRICT_ALIGNMENT)) |
3933e0e1 MM |
3066 | { /* move 4 bytes */ |
3067 | move_bytes = 4; | |
3068 | tmp_reg = gen_reg_rtx (SImode); | |
cc0d9ba8 DE |
3069 | emit_move_insn (tmp_reg, |
3070 | expand_block_move_mem (SImode, | |
3071 | src_reg, orig_src)); | |
3072 | emit_move_insn (expand_block_move_mem (SImode, | |
3073 | dest_reg, orig_dest), | |
3074 | tmp_reg); | |
3933e0e1 | 3075 | } |
cc0d9ba8 | 3076 | else if (bytes == 2 && (align >= 2 || ! STRICT_ALIGNMENT)) |
3933e0e1 MM |
3077 | { /* move 2 bytes */ |
3078 | move_bytes = 2; | |
3079 | tmp_reg = gen_reg_rtx (HImode); | |
cc0d9ba8 DE |
3080 | emit_move_insn (tmp_reg, |
3081 | expand_block_move_mem (HImode, | |
3082 | src_reg, orig_src)); | |
3083 | emit_move_insn (expand_block_move_mem (HImode, | |
3084 | dest_reg, orig_dest), | |
3085 | tmp_reg); | |
3933e0e1 MM |
3086 | } |
3087 | else if (bytes == 1) /* move 1 byte */ | |
3088 | { | |
3089 | move_bytes = 1; | |
3090 | tmp_reg = gen_reg_rtx (QImode); | |
cc0d9ba8 DE |
3091 | emit_move_insn (tmp_reg, |
3092 | expand_block_move_mem (QImode, | |
3093 | src_reg, orig_src)); | |
3094 | emit_move_insn (expand_block_move_mem (QImode, | |
3095 | dest_reg, orig_dest), | |
3096 | tmp_reg); | |
3933e0e1 MM |
3097 | } |
3098 | else | |
3099 | { /* move up to 4 bytes at a time */ | |
3100 | move_bytes = (bytes > 4) ? 4 : bytes; | |
cc0d9ba8 DE |
3101 | emit_insn (gen_movstrsi_1reg (expand_block_move_mem (BLKmode, |
3102 | dest_reg, | |
3103 | orig_dest), | |
3104 | expand_block_move_mem (BLKmode, | |
3105 | src_reg, | |
3106 | orig_src), | |
3933e0e1 | 3107 | GEN_INT (move_bytes), |
4c64a852 | 3108 | align_rtx)); |
3933e0e1 | 3109 | } |
4c64a852 | 3110 | |
015892ee RK |
3111 | if (bytes > move_bytes) |
3112 | { | |
cc0d9ba8 DE |
3113 | if (! TARGET_POWERPC64) |
3114 | { | |
3115 | emit_insn (gen_addsi3 (src_reg, src_reg, | |
3116 | GEN_INT (move_bytes))); | |
3117 | emit_insn (gen_addsi3 (dest_reg, dest_reg, | |
3118 | GEN_INT (move_bytes))); | |
3119 | } | |
3120 | else | |
3121 | { | |
3122 | emit_insn (gen_adddi3 (src_reg, src_reg, | |
3123 | GEN_INT (move_bytes))); | |
3124 | emit_insn (gen_adddi3 (dest_reg, dest_reg, | |
3125 | GEN_INT (move_bytes))); | |
3126 | } | |
015892ee | 3127 | } |
4c64a852 | 3128 | } |
3933e0e1 MM |
3129 | } |
3130 | ||
3131 | else /* string instructions not available */ | |
3132 | { | |
3133 | num_reg = offset = 0; | |
3134 | for ( ; bytes > 0; (bytes -= move_bytes), (offset += move_bytes)) | |
7e69e155 | 3135 | { |
3933e0e1 MM |
3136 | /* Calculate the correct offset for src/dest */ |
3137 | if (offset == 0) | |
7e69e155 | 3138 | { |
3933e0e1 MM |
3139 | src_addr = src_reg; |
3140 | dest_addr = dest_reg; | |
3141 | } | |
3142 | else | |
3143 | { | |
c5c76735 JL |
3144 | src_addr = plus_constant (src_reg, offset); |
3145 | dest_addr = plus_constant (dest_reg, offset); | |
3933e0e1 MM |
3146 | } |
3147 | ||
cc0d9ba8 DE |
3148 | /* Generate the appropriate load and store, saving the stores |
3149 | for later. */ | |
3150 | if (bytes >= 8 && TARGET_POWERPC64 | |
3151 | /* 64-bit loads and stores require word-aligned displacements. */ | |
3152 | && (align >= 8 || (! STRICT_ALIGNMENT && align >= 4))) | |
b6c9286a MM |
3153 | { |
3154 | move_bytes = 8; | |
3155 | tmp_reg = gen_reg_rtx (DImode); | |
cc0d9ba8 DE |
3156 | emit_insn (gen_movdi (tmp_reg, |
3157 | expand_block_move_mem (DImode, | |
3158 | src_addr, | |
3159 | orig_src))); | |
3160 | stores[num_reg++] = gen_movdi (expand_block_move_mem (DImode, | |
3161 | dest_addr, | |
3162 | orig_dest), | |
3163 | tmp_reg); | |
b6c9286a | 3164 | } |
cc0d9ba8 | 3165 | else if (bytes >= 4 && (align >= 4 || ! STRICT_ALIGNMENT)) |
3933e0e1 MM |
3166 | { |
3167 | move_bytes = 4; | |
3168 | tmp_reg = gen_reg_rtx (SImode); | |
cc0d9ba8 DE |
3169 | emit_insn (gen_movsi (tmp_reg, |
3170 | expand_block_move_mem (SImode, | |
3171 | src_addr, | |
3172 | orig_src))); | |
3173 | stores[num_reg++] = gen_movsi (expand_block_move_mem (SImode, | |
3174 | dest_addr, | |
3175 | orig_dest), | |
3176 | tmp_reg); | |
3933e0e1 | 3177 | } |
cc0d9ba8 | 3178 | else if (bytes >= 2 && (align >= 2 || ! STRICT_ALIGNMENT)) |
3933e0e1 MM |
3179 | { |
3180 | move_bytes = 2; | |
3181 | tmp_reg = gen_reg_rtx (HImode); | |
c81fc13e | 3182 | emit_insn (gen_movhi (tmp_reg, |
cc0d9ba8 DE |
3183 | expand_block_move_mem (HImode, |
3184 | src_addr, | |
3185 | orig_src))); | |
3186 | stores[num_reg++] = gen_movhi (expand_block_move_mem (HImode, | |
3187 | dest_addr, | |
3188 | orig_dest), | |
3189 | tmp_reg); | |
3933e0e1 MM |
3190 | } |
3191 | else | |
3192 | { | |
3193 | move_bytes = 1; | |
3194 | tmp_reg = gen_reg_rtx (QImode); | |
c81fc13e | 3195 | emit_insn (gen_movqi (tmp_reg, |
cc0d9ba8 DE |
3196 | expand_block_move_mem (QImode, |
3197 | src_addr, | |
3198 | orig_src))); | |
3199 | stores[num_reg++] = gen_movqi (expand_block_move_mem (QImode, | |
3200 | dest_addr, | |
3201 | orig_dest), | |
3202 | tmp_reg); | |
3933e0e1 MM |
3203 | } |
3204 | ||
3205 | if (num_reg >= MAX_MOVE_REG) | |
3206 | { | |
3207 | for (i = 0; i < num_reg; i++) | |
3208 | emit_insn (stores[i]); | |
3209 | num_reg = 0; | |
7e69e155 MM |
3210 | } |
3211 | } | |
3933e0e1 | 3212 | |
b6c9286a MM |
3213 | for (i = 0; i < num_reg; i++) |
3214 | emit_insn (stores[i]); | |
7e69e155 MM |
3215 | } |
3216 | ||
3217 | return 1; | |
3218 | } | |
3219 | ||
9878760c RK |
3220 | \f |
3221 | /* Return 1 if OP is a load multiple operation. It is known to be a | |
3222 | PARALLEL and the first section will be tested. */ | |
3223 | ||
3224 | int | |
3225 | load_multiple_operation (op, mode) | |
3226 | rtx op; | |
296b8152 | 3227 | enum machine_mode mode ATTRIBUTE_UNUSED; |
9878760c RK |
3228 | { |
3229 | int count = XVECLEN (op, 0); | |
e2c953b6 | 3230 | unsigned int dest_regno; |
9878760c RK |
3231 | rtx src_addr; |
3232 | int i; | |
3233 | ||
3234 | /* Perform a quick check so we don't blow up below. */ | |
3235 | if (count <= 1 | |
3236 | || GET_CODE (XVECEXP (op, 0, 0)) != SET | |
3237 | || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG | |
3238 | || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM) | |
3239 | return 0; | |
3240 | ||
3241 | dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0))); | |
3242 | src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0); | |
3243 | ||
3244 | for (i = 1; i < count; i++) | |
3245 | { | |
3246 | rtx elt = XVECEXP (op, 0, i); | |
3247 | ||
3248 | if (GET_CODE (elt) != SET | |
3249 | || GET_CODE (SET_DEST (elt)) != REG | |
3250 | || GET_MODE (SET_DEST (elt)) != SImode | |
3251 | || REGNO (SET_DEST (elt)) != dest_regno + i | |
3252 | || GET_CODE (SET_SRC (elt)) != MEM | |
3253 | || GET_MODE (SET_SRC (elt)) != SImode | |
3254 | || GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS | |
3255 | || ! rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr) | |
3256 | || GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT | |
3257 | || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != i * 4) | |
3258 | return 0; | |
3259 | } | |
3260 | ||
3261 | return 1; | |
3262 | } | |
3263 | ||
3264 | /* Similar, but tests for store multiple. Here, the second vector element | |
3265 | is a CLOBBER. It will be tested later. */ | |
3266 | ||
3267 | int | |
3268 | store_multiple_operation (op, mode) | |
3269 | rtx op; | |
296b8152 | 3270 | enum machine_mode mode ATTRIBUTE_UNUSED; |
9878760c RK |
3271 | { |
3272 | int count = XVECLEN (op, 0) - 1; | |
e2c953b6 | 3273 | unsigned int src_regno; |
9878760c RK |
3274 | rtx dest_addr; |
3275 | int i; | |
3276 | ||
3277 | /* Perform a quick check so we don't blow up below. */ | |
3278 | if (count <= 1 | |
3279 | || GET_CODE (XVECEXP (op, 0, 0)) != SET | |
3280 | || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM | |
3281 | || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG) | |
3282 | return 0; | |
3283 | ||
3284 | src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0))); | |
3285 | dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0); | |
3286 | ||
3287 | for (i = 1; i < count; i++) | |
3288 | { | |
3289 | rtx elt = XVECEXP (op, 0, i + 1); | |
3290 | ||
3291 | if (GET_CODE (elt) != SET | |
3292 | || GET_CODE (SET_SRC (elt)) != REG | |
3293 | || GET_MODE (SET_SRC (elt)) != SImode | |
3294 | || REGNO (SET_SRC (elt)) != src_regno + i | |
3295 | || GET_CODE (SET_DEST (elt)) != MEM | |
3296 | || GET_MODE (SET_DEST (elt)) != SImode | |
3297 | || GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS | |
3298 | || ! rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr) | |
3299 | || GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT | |
3300 | || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != i * 4) | |
3301 | return 0; | |
3302 | } | |
3303 | ||
3304 | return 1; | |
3305 | } | |
9ebbca7d GK |
3306 | |
3307 | /* Return 1 for an PARALLEL suitable for mtcrf. */ | |
3308 | ||
3309 | int | |
3310 | mtcrf_operation (op, mode) | |
3311 | rtx op; | |
3312 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
3313 | { | |
3314 | int count = XVECLEN (op, 0); | |
3315 | int i; | |
9ebbca7d GK |
3316 | rtx src_reg; |
3317 | ||
3318 | /* Perform a quick check so we don't blow up below. */ | |
e35b9579 GK |
3319 | if (count < 1 |
3320 | || GET_CODE (XVECEXP (op, 0, 0)) != SET | |
3321 | || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC | |
3322 | || XVECLEN (SET_SRC (XVECEXP (op, 0, 0)), 0) != 2) | |
9ebbca7d | 3323 | return 0; |
e35b9579 | 3324 | src_reg = XVECEXP (SET_SRC (XVECEXP (op, 0, 0)), 0, 0); |
9ebbca7d GK |
3325 | |
3326 | if (GET_CODE (src_reg) != REG | |
3327 | || GET_MODE (src_reg) != SImode | |
3328 | || ! INT_REGNO_P (REGNO (src_reg))) | |
3329 | return 0; | |
3330 | ||
e35b9579 | 3331 | for (i = 0; i < count; i++) |
9ebbca7d GK |
3332 | { |
3333 | rtx exp = XVECEXP (op, 0, i); | |
3334 | rtx unspec; | |
3335 | int maskval; | |
3336 | ||
3337 | if (GET_CODE (exp) != SET | |
3338 | || GET_CODE (SET_DEST (exp)) != REG | |
3339 | || GET_MODE (SET_DEST (exp)) != CCmode | |
3340 | || ! CR_REGNO_P (REGNO (SET_DEST (exp)))) | |
3341 | return 0; | |
3342 | unspec = SET_SRC (exp); | |
3343 | maskval = 1 << (MAX_CR_REGNO - REGNO (SET_DEST (exp))); | |
9ebbca7d GK |
3344 | |
3345 | if (GET_CODE (unspec) != UNSPEC | |
3346 | || XINT (unspec, 1) != 20 | |
3347 | || XVECLEN (unspec, 0) != 2 | |
3348 | || XVECEXP (unspec, 0, 0) != src_reg | |
3349 | || GET_CODE (XVECEXP (unspec, 0, 1)) != CONST_INT | |
3350 | || INTVAL (XVECEXP (unspec, 0, 1)) != maskval) | |
3351 | return 0; | |
3352 | } | |
e35b9579 | 3353 | return 1; |
9ebbca7d GK |
3354 | } |
3355 | ||
3356 | /* Return 1 for an PARALLEL suitable for lmw. */ | |
3357 | ||
3358 | int | |
3359 | lmw_operation (op, mode) | |
3360 | rtx op; | |
3361 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
3362 | { | |
3363 | int count = XVECLEN (op, 0); | |
e2c953b6 | 3364 | unsigned int dest_regno; |
9ebbca7d | 3365 | rtx src_addr; |
e2c953b6 | 3366 | unsigned int base_regno; |
9ebbca7d GK |
3367 | HOST_WIDE_INT offset; |
3368 | int i; | |
3369 | ||
3370 | /* Perform a quick check so we don't blow up below. */ | |
3371 | if (count <= 1 | |
3372 | || GET_CODE (XVECEXP (op, 0, 0)) != SET | |
3373 | || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG | |
3374 | || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM) | |
3375 | return 0; | |
3376 | ||
3377 | dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0))); | |
3378 | src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0); | |
3379 | ||
3380 | if (dest_regno > 31 | |
e2c953b6 | 3381 | || count != 32 - (int) dest_regno) |
9ebbca7d GK |
3382 | return 0; |
3383 | ||
258bfae2 | 3384 | if (LEGITIMATE_INDIRECT_ADDRESS_P (src_addr, 0)) |
9ebbca7d GK |
3385 | { |
3386 | offset = 0; | |
3387 | base_regno = REGNO (src_addr); | |
3388 | if (base_regno == 0) | |
3389 | return 0; | |
3390 | } | |
258bfae2 | 3391 | else if (LEGITIMATE_OFFSET_ADDRESS_P (SImode, src_addr, 0)) |
9ebbca7d GK |
3392 | { |
3393 | offset = INTVAL (XEXP (src_addr, 1)); | |
3394 | base_regno = REGNO (XEXP (src_addr, 0)); | |
3395 | } | |
3396 | else | |
3397 | return 0; | |
3398 | ||
3399 | for (i = 0; i < count; i++) | |
3400 | { | |
3401 | rtx elt = XVECEXP (op, 0, i); | |
3402 | rtx newaddr; | |
3403 | rtx addr_reg; | |
3404 | HOST_WIDE_INT newoffset; | |
3405 | ||
3406 | if (GET_CODE (elt) != SET | |
3407 | || GET_CODE (SET_DEST (elt)) != REG | |
3408 | || GET_MODE (SET_DEST (elt)) != SImode | |
3409 | || REGNO (SET_DEST (elt)) != dest_regno + i | |
3410 | || GET_CODE (SET_SRC (elt)) != MEM | |
3411 | || GET_MODE (SET_SRC (elt)) != SImode) | |
3412 | return 0; | |
3413 | newaddr = XEXP (SET_SRC (elt), 0); | |
258bfae2 | 3414 | if (LEGITIMATE_INDIRECT_ADDRESS_P (newaddr, 0)) |
9ebbca7d GK |
3415 | { |
3416 | newoffset = 0; | |
3417 | addr_reg = newaddr; | |
3418 | } | |
258bfae2 | 3419 | else if (LEGITIMATE_OFFSET_ADDRESS_P (SImode, newaddr, 0)) |
9ebbca7d GK |
3420 | { |
3421 | addr_reg = XEXP (newaddr, 0); | |
3422 | newoffset = INTVAL (XEXP (newaddr, 1)); | |
3423 | } | |
3424 | else | |
3425 | return 0; | |
3426 | if (REGNO (addr_reg) != base_regno | |
3427 | || newoffset != offset + 4 * i) | |
3428 | return 0; | |
3429 | } | |
3430 | ||
3431 | return 1; | |
3432 | } | |
3433 | ||
3434 | /* Return 1 for an PARALLEL suitable for stmw. */ | |
3435 | ||
3436 | int | |
3437 | stmw_operation (op, mode) | |
3438 | rtx op; | |
3439 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
3440 | { | |
3441 | int count = XVECLEN (op, 0); | |
e2c953b6 | 3442 | unsigned int src_regno; |
9ebbca7d | 3443 | rtx dest_addr; |
e2c953b6 | 3444 | unsigned int base_regno; |
9ebbca7d GK |
3445 | HOST_WIDE_INT offset; |
3446 | int i; | |
3447 | ||
3448 | /* Perform a quick check so we don't blow up below. */ | |
3449 | if (count <= 1 | |
3450 | || GET_CODE (XVECEXP (op, 0, 0)) != SET | |
3451 | || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM | |
3452 | || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG) | |
3453 | return 0; | |
3454 | ||
3455 | src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0))); | |
3456 | dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0); | |
3457 | ||
3458 | if (src_regno > 31 | |
e2c953b6 | 3459 | || count != 32 - (int) src_regno) |
9ebbca7d GK |
3460 | return 0; |
3461 | ||
258bfae2 | 3462 | if (LEGITIMATE_INDIRECT_ADDRESS_P (dest_addr, 0)) |
9ebbca7d GK |
3463 | { |
3464 | offset = 0; | |
3465 | base_regno = REGNO (dest_addr); | |
3466 | if (base_regno == 0) | |
3467 | return 0; | |
3468 | } | |
258bfae2 | 3469 | else if (LEGITIMATE_OFFSET_ADDRESS_P (SImode, dest_addr, 0)) |
9ebbca7d GK |
3470 | { |
3471 | offset = INTVAL (XEXP (dest_addr, 1)); | |
3472 | base_regno = REGNO (XEXP (dest_addr, 0)); | |
3473 | } | |
3474 | else | |
3475 | return 0; | |
3476 | ||
3477 | for (i = 0; i < count; i++) | |
3478 | { | |
3479 | rtx elt = XVECEXP (op, 0, i); | |
3480 | rtx newaddr; | |
3481 | rtx addr_reg; | |
3482 | HOST_WIDE_INT newoffset; | |
3483 | ||
3484 | if (GET_CODE (elt) != SET | |
3485 | || GET_CODE (SET_SRC (elt)) != REG | |
3486 | || GET_MODE (SET_SRC (elt)) != SImode | |
3487 | || REGNO (SET_SRC (elt)) != src_regno + i | |
3488 | || GET_CODE (SET_DEST (elt)) != MEM | |
3489 | || GET_MODE (SET_DEST (elt)) != SImode) | |
3490 | return 0; | |
3491 | newaddr = XEXP (SET_DEST (elt), 0); | |
258bfae2 | 3492 | if (LEGITIMATE_INDIRECT_ADDRESS_P (newaddr, 0)) |
9ebbca7d GK |
3493 | { |
3494 | newoffset = 0; | |
3495 | addr_reg = newaddr; | |
3496 | } | |
258bfae2 | 3497 | else if (LEGITIMATE_OFFSET_ADDRESS_P (SImode, newaddr, 0)) |
9ebbca7d GK |
3498 | { |
3499 | addr_reg = XEXP (newaddr, 0); | |
3500 | newoffset = INTVAL (XEXP (newaddr, 1)); | |
3501 | } | |
3502 | else | |
3503 | return 0; | |
3504 | if (REGNO (addr_reg) != base_regno | |
3505 | || newoffset != offset + 4 * i) | |
3506 | return 0; | |
3507 | } | |
3508 | ||
3509 | return 1; | |
3510 | } | |
9878760c | 3511 | \f |
39a10a29 GK |
3512 | |
3513 | /* A validation routine: say whether CODE, a condition code, | |
3514 | and MODE match. The other alternatives either don't make | |
3515 | sense or should never be generated. */ | |
3516 | static void | |
3517 | validate_condition_mode (code, mode) | |
3518 | enum rtx_code code; | |
3519 | enum machine_mode mode; | |
3520 | { | |
3521 | if (GET_RTX_CLASS (code) != '<' | |
3522 | || GET_MODE_CLASS (mode) != MODE_CC) | |
3523 | abort (); | |
3524 | ||
3525 | /* These don't make sense. */ | |
3526 | if ((code == GT || code == LT || code == GE || code == LE) | |
3527 | && mode == CCUNSmode) | |
3528 | abort (); | |
3529 | ||
3530 | if ((code == GTU || code == LTU || code == GEU || code == LEU) | |
3531 | && mode != CCUNSmode) | |
3532 | abort (); | |
3533 | ||
3534 | if (mode != CCFPmode | |
3535 | && (code == ORDERED || code == UNORDERED | |
3536 | || code == UNEQ || code == LTGT | |
3537 | || code == UNGT || code == UNLT | |
3538 | || code == UNGE || code == UNLE)) | |
3539 | abort(); | |
3540 | ||
de6c5979 BL |
3541 | /* These should never be generated except for |
3542 | flag_unsafe_math_optimizations. */ | |
39a10a29 | 3543 | if (mode == CCFPmode |
de6c5979 | 3544 | && ! flag_unsafe_math_optimizations |
39a10a29 GK |
3545 | && (code == LE || code == GE |
3546 | || code == UNEQ || code == LTGT | |
3547 | || code == UNGT || code == UNLT)) | |
3548 | abort (); | |
3549 | ||
3550 | /* These are invalid; the information is not there. */ | |
3551 | if (mode == CCEQmode | |
3552 | && code != EQ && code != NE) | |
3553 | abort (); | |
3554 | } | |
3555 | ||
9878760c RK |
3556 | /* Return 1 if OP is a comparison operation that is valid for a branch insn. |
3557 | We only check the opcode against the mode of the CC value here. */ | |
3558 | ||
3559 | int | |
3560 | branch_comparison_operator (op, mode) | |
3561 | register rtx op; | |
296b8152 | 3562 | enum machine_mode mode ATTRIBUTE_UNUSED; |
9878760c RK |
3563 | { |
3564 | enum rtx_code code = GET_CODE (op); | |
3565 | enum machine_mode cc_mode; | |
3566 | ||
3567 | if (GET_RTX_CLASS (code) != '<') | |
3568 | return 0; | |
3569 | ||
3570 | cc_mode = GET_MODE (XEXP (op, 0)); | |
3571 | if (GET_MODE_CLASS (cc_mode) != MODE_CC) | |
3572 | return 0; | |
3573 | ||
39a10a29 | 3574 | validate_condition_mode (code, cc_mode); |
9878760c | 3575 | |
39a10a29 GK |
3576 | return 1; |
3577 | } | |
3578 | ||
3579 | /* Return 1 if OP is a comparison operation that is valid for a branch | |
3580 | insn and which is true if the corresponding bit in the CC register | |
3581 | is set. */ | |
3582 | ||
3583 | int | |
3584 | branch_positive_comparison_operator (op, mode) | |
3585 | register rtx op; | |
3586 | enum machine_mode mode; | |
3587 | { | |
3588 | enum rtx_code code; | |
3589 | ||
3590 | if (! branch_comparison_operator (op, mode)) | |
9878760c RK |
3591 | return 0; |
3592 | ||
39a10a29 GK |
3593 | code = GET_CODE (op); |
3594 | return (code == EQ || code == LT || code == GT | |
3595 | || code == LTU || code == GTU | |
3596 | || code == UNORDERED); | |
9878760c RK |
3597 | } |
3598 | ||
39a10a29 | 3599 | |
9878760c RK |
3600 | /* Return 1 if OP is a comparison operation that is valid for an scc insn. |
3601 | We check the opcode against the mode of the CC value and disallow EQ or | |
3602 | NE comparisons for integers. */ | |
3603 | ||
3604 | int | |
3605 | scc_comparison_operator (op, mode) | |
3606 | register rtx op; | |
3607 | enum machine_mode mode; | |
3608 | { | |
3609 | enum rtx_code code = GET_CODE (op); | |
3610 | enum machine_mode cc_mode; | |
3611 | ||
3612 | if (GET_MODE (op) != mode && mode != VOIDmode) | |
3613 | return 0; | |
3614 | ||
3615 | if (GET_RTX_CLASS (code) != '<') | |
3616 | return 0; | |
3617 | ||
3618 | cc_mode = GET_MODE (XEXP (op, 0)); | |
3619 | if (GET_MODE_CLASS (cc_mode) != MODE_CC) | |
3620 | return 0; | |
3621 | ||
39a10a29 | 3622 | validate_condition_mode (code, cc_mode); |
9878760c | 3623 | |
39a10a29 | 3624 | if (code == NE && cc_mode != CCFPmode) |
c5defebb RK |
3625 | return 0; |
3626 | ||
9878760c RK |
3627 | return 1; |
3628 | } | |
e0cd0770 JC |
3629 | |
3630 | int | |
3631 | trap_comparison_operator (op, mode) | |
3632 | rtx op; | |
3633 | enum machine_mode mode; | |
3634 | { | |
3635 | if (mode != VOIDmode && mode != GET_MODE (op)) | |
3636 | return 0; | |
39a10a29 | 3637 | return GET_RTX_CLASS (GET_CODE (op)) == '<'; |
e0cd0770 | 3638 | } |
dfbdccdb GK |
3639 | |
3640 | int | |
3641 | boolean_operator (op, mode) | |
3642 | rtx op; | |
3643 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
3644 | { | |
3645 | enum rtx_code code = GET_CODE (op); | |
3646 | return (code == AND || code == IOR || code == XOR); | |
3647 | } | |
1d328b19 GK |
3648 | |
3649 | int | |
3650 | boolean_or_operator (op, mode) | |
3651 | rtx op; | |
3652 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
3653 | { | |
3654 | enum rtx_code code = GET_CODE (op); | |
3655 | return (code == IOR || code == XOR); | |
3656 | } | |
50a0b056 GK |
3657 | |
3658 | int | |
3659 | min_max_operator (op, mode) | |
3660 | rtx op; | |
3661 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
3662 | { | |
3663 | enum rtx_code code = GET_CODE (op); | |
3664 | return (code == SMIN || code == SMAX || code == UMIN || code == UMAX); | |
3665 | } | |
9878760c RK |
3666 | \f |
3667 | /* Return 1 if ANDOP is a mask that has no bits on that are not in the | |
3668 | mask required to convert the result of a rotate insn into a shift | |
3669 | left insn of SHIFTOP bits. Both are known to be CONST_INT. */ | |
3670 | ||
3671 | int | |
3672 | includes_lshift_p (shiftop, andop) | |
3673 | register rtx shiftop; | |
3674 | register rtx andop; | |
3675 | { | |
e2c953b6 DE |
3676 | unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0; |
3677 | ||
3678 | shift_mask <<= INTVAL (shiftop); | |
9878760c RK |
3679 | |
3680 | return (INTVAL (andop) & ~shift_mask) == 0; | |
3681 | } | |
3682 | ||
3683 | /* Similar, but for right shift. */ | |
3684 | ||
3685 | int | |
3686 | includes_rshift_p (shiftop, andop) | |
3687 | register rtx shiftop; | |
3688 | register rtx andop; | |
3689 | { | |
a7653a2c | 3690 | unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0; |
9878760c RK |
3691 | |
3692 | shift_mask >>= INTVAL (shiftop); | |
3693 | ||
e2c953b6 DE |
3694 | return (INTVAL (andop) & ~shift_mask) == 0; |
3695 | } | |
3696 | ||
3697 | /* Return 1 if ANDOP is a mask that has no bits on that are not in the | |
3698 | mask required to convert the result of a rotate insn into a shift | |
3699 | left insn of SHIFTOP bits. */ | |
3700 | ||
3701 | int | |
3702 | includes_lshift64_p (shiftop, andop) | |
3703 | register rtx shiftop; | |
3704 | register rtx andop; | |
3705 | { | |
3706 | #if HOST_BITS_PER_WIDE_INT == 64 | |
3707 | unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0; | |
3708 | ||
3709 | shift_mask <<= INTVAL (shiftop); | |
3710 | ||
3711 | return (INTVAL (andop) & ~shift_mask) == 0; | |
3712 | #else | |
3713 | unsigned HOST_WIDE_INT shift_mask_low = ~(unsigned HOST_WIDE_INT) 0; | |
3714 | unsigned HOST_WIDE_INT shift_mask_high = ~(unsigned HOST_WIDE_INT) 0; | |
3715 | ||
3716 | shift_mask_low <<= INTVAL (shiftop); | |
3717 | ||
3718 | if (INTVAL (shiftop) > 32) | |
3719 | shift_mask_high <<= (INTVAL (shiftop) - 32); | |
3720 | ||
3721 | if (GET_CODE (andop) == CONST_INT) | |
3722 | return (INTVAL (andop) & ~shift_mask_low) == 0; | |
3723 | else | |
3724 | return ((CONST_DOUBLE_HIGH (andop) & ~shift_mask_high) == 0 | |
3725 | && (CONST_DOUBLE_LOW (andop) & ~shift_mask_low) == 0); | |
3726 | #endif | |
9878760c | 3727 | } |
35068b43 RK |
3728 | |
3729 | /* Return 1 if REGNO (reg1) == REGNO (reg2) - 1 making them candidates | |
3730 | for lfq and stfq insns. | |
3731 | ||
3732 | Note reg1 and reg2 *must* be hard registers. To be sure we will | |
3733 | abort if we are passed pseudo registers. */ | |
3734 | ||
3735 | int | |
3736 | registers_ok_for_quad_peep (reg1, reg2) | |
3737 | rtx reg1, reg2; | |
3738 | { | |
3739 | /* We might have been passed a SUBREG. */ | |
3740 | if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG) | |
3741 | return 0; | |
3742 | ||
3743 | return (REGNO (reg1) == REGNO (reg2) - 1); | |
3744 | } | |
3745 | ||
3746 | /* Return 1 if addr1 and addr2 are suitable for lfq or stfq insn. addr1 and | |
3747 | addr2 must be in consecutive memory locations (addr2 == addr1 + 8). */ | |
3748 | ||
3749 | int | |
3750 | addrs_ok_for_quad_peep (addr1, addr2) | |
3751 | register rtx addr1; | |
3752 | register rtx addr2; | |
3753 | { | |
e2c953b6 | 3754 | unsigned int reg1; |
35068b43 RK |
3755 | int offset1; |
3756 | ||
3757 | /* Extract an offset (if used) from the first addr. */ | |
3758 | if (GET_CODE (addr1) == PLUS) | |
3759 | { | |
3760 | /* If not a REG, return zero. */ | |
3761 | if (GET_CODE (XEXP (addr1, 0)) != REG) | |
3762 | return 0; | |
3763 | else | |
3764 | { | |
3765 | reg1 = REGNO (XEXP (addr1, 0)); | |
3766 | /* The offset must be constant! */ | |
3767 | if (GET_CODE (XEXP (addr1, 1)) != CONST_INT) | |
3768 | return 0; | |
3769 | offset1 = INTVAL (XEXP (addr1, 1)); | |
3770 | } | |
3771 | } | |
3772 | else if (GET_CODE (addr1) != REG) | |
3773 | return 0; | |
3774 | else | |
3775 | { | |
3776 | reg1 = REGNO (addr1); | |
3777 | /* This was a simple (mem (reg)) expression. Offset is 0. */ | |
3778 | offset1 = 0; | |
3779 | } | |
3780 | ||
acad7ed3 | 3781 | /* Make sure the second address is a (mem (plus (reg) (const_int))). */ |
35068b43 RK |
3782 | if (GET_CODE (addr2) != PLUS) |
3783 | return 0; | |
3784 | ||
3785 | if (GET_CODE (XEXP (addr2, 0)) != REG | |
3786 | || GET_CODE (XEXP (addr2, 1)) != CONST_INT) | |
3787 | return 0; | |
3788 | ||
3789 | if (reg1 != REGNO (XEXP (addr2, 0))) | |
3790 | return 0; | |
3791 | ||
3792 | /* The offset for the second addr must be 8 more than the first addr. */ | |
3793 | if (INTVAL (XEXP (addr2, 1)) != offset1 + 8) | |
3794 | return 0; | |
3795 | ||
3796 | /* All the tests passed. addr1 and addr2 are valid for lfq or stfq | |
3797 | instructions. */ | |
3798 | return 1; | |
3799 | } | |
9878760c RK |
3800 | \f |
3801 | /* Return the register class of a scratch register needed to copy IN into | |
3802 | or out of a register in CLASS in MODE. If it can be done directly, | |
3803 | NO_REGS is returned. */ | |
3804 | ||
3805 | enum reg_class | |
3806 | secondary_reload_class (class, mode, in) | |
3807 | enum reg_class class; | |
296b8152 | 3808 | enum machine_mode mode ATTRIBUTE_UNUSED; |
9878760c RK |
3809 | rtx in; |
3810 | { | |
5accd822 | 3811 | int regno; |
9878760c | 3812 | |
46fad5b7 DJ |
3813 | if (TARGET_ELF || (DEFAULT_ABI == ABI_DARWIN && flag_pic)) |
3814 | { | |
3815 | /* We cannot copy a symbolic operand directly into anything | |
3816 | other than BASE_REGS for TARGET_ELF. So indicate that a | |
3817 | register from BASE_REGS is needed as an intermediate | |
3818 | register. | |
3819 | ||
3820 | On Darwin, pic addresses require a load from memory, which | |
3821 | needs a base register. */ | |
3822 | if (class != BASE_REGS | |
3823 | && (GET_CODE (in) == SYMBOL_REF | |
3824 | || GET_CODE (in) == HIGH | |
3825 | || GET_CODE (in) == LABEL_REF | |
3826 | || GET_CODE (in) == CONST)) | |
3827 | return BASE_REGS; | |
3828 | } | |
e7b7998a | 3829 | |
5accd822 DE |
3830 | if (GET_CODE (in) == REG) |
3831 | { | |
3832 | regno = REGNO (in); | |
3833 | if (regno >= FIRST_PSEUDO_REGISTER) | |
3834 | { | |
3835 | regno = true_regnum (in); | |
3836 | if (regno >= FIRST_PSEUDO_REGISTER) | |
3837 | regno = -1; | |
3838 | } | |
3839 | } | |
3840 | else if (GET_CODE (in) == SUBREG) | |
3841 | { | |
3842 | regno = true_regnum (in); | |
3843 | if (regno >= FIRST_PSEUDO_REGISTER) | |
3844 | regno = -1; | |
3845 | } | |
3846 | else | |
3847 | regno = -1; | |
3848 | ||
9878760c RK |
3849 | /* We can place anything into GENERAL_REGS and can put GENERAL_REGS |
3850 | into anything. */ | |
3851 | if (class == GENERAL_REGS || class == BASE_REGS | |
3852 | || (regno >= 0 && INT_REGNO_P (regno))) | |
3853 | return NO_REGS; | |
3854 | ||
3855 | /* Constants, memory, and FP registers can go into FP registers. */ | |
3856 | if ((regno == -1 || FP_REGNO_P (regno)) | |
3857 | && (class == FLOAT_REGS || class == NON_SPECIAL_REGS)) | |
3858 | return NO_REGS; | |
3859 | ||
3860 | /* We can copy among the CR registers. */ | |
3861 | if ((class == CR_REGS || class == CR0_REGS) | |
3862 | && regno >= 0 && CR_REGNO_P (regno)) | |
3863 | return NO_REGS; | |
3864 | ||
3865 | /* Otherwise, we need GENERAL_REGS. */ | |
3866 | return GENERAL_REGS; | |
3867 | } | |
3868 | \f | |
3869 | /* Given a comparison operation, return the bit number in CCR to test. We | |
3870 | know this is a valid comparison. | |
3871 | ||
3872 | SCC_P is 1 if this is for an scc. That means that %D will have been | |
3873 | used instead of %C, so the bits will be in different places. | |
3874 | ||
b4ac57ab | 3875 | Return -1 if OP isn't a valid comparison for some reason. */ |
9878760c RK |
3876 | |
3877 | int | |
3878 | ccr_bit (op, scc_p) | |
3879 | register rtx op; | |
3880 | int scc_p; | |
3881 | { | |
3882 | enum rtx_code code = GET_CODE (op); | |
3883 | enum machine_mode cc_mode; | |
3884 | int cc_regnum; | |
3885 | int base_bit; | |
9ebbca7d | 3886 | rtx reg; |
9878760c RK |
3887 | |
3888 | if (GET_RTX_CLASS (code) != '<') | |
3889 | return -1; | |
3890 | ||
9ebbca7d GK |
3891 | reg = XEXP (op, 0); |
3892 | ||
3893 | if (GET_CODE (reg) != REG | |
3894 | || ! CR_REGNO_P (REGNO (reg))) | |
3895 | abort (); | |
3896 | ||
3897 | cc_mode = GET_MODE (reg); | |
3898 | cc_regnum = REGNO (reg); | |
3899 | base_bit = 4 * (cc_regnum - CR0_REGNO); | |
9878760c | 3900 | |
39a10a29 | 3901 | validate_condition_mode (code, cc_mode); |
c5defebb | 3902 | |
9878760c RK |
3903 | switch (code) |
3904 | { | |
3905 | case NE: | |
3906 | return scc_p ? base_bit + 3 : base_bit + 2; | |
3907 | case EQ: | |
3908 | return base_bit + 2; | |
1c882ea4 | 3909 | case GT: case GTU: case UNLE: |
9878760c | 3910 | return base_bit + 1; |
1c882ea4 | 3911 | case LT: case LTU: case UNGE: |
9878760c | 3912 | return base_bit; |
1c882ea4 GK |
3913 | case ORDERED: case UNORDERED: |
3914 | return base_bit + 3; | |
9878760c RK |
3915 | |
3916 | case GE: case GEU: | |
39a10a29 | 3917 | /* If scc, we will have done a cror to put the bit in the |
9878760c RK |
3918 | unordered position. So test that bit. For integer, this is ! LT |
3919 | unless this is an scc insn. */ | |
39a10a29 | 3920 | return scc_p ? base_bit + 3 : base_bit; |
9878760c RK |
3921 | |
3922 | case LE: case LEU: | |
39a10a29 | 3923 | return scc_p ? base_bit + 3 : base_bit + 1; |
1c882ea4 | 3924 | |
9878760c RK |
3925 | default: |
3926 | abort (); | |
3927 | } | |
3928 | } | |
1ff7789b | 3929 | \f |
8d30c4ee | 3930 | /* Return the GOT register. */ |
1ff7789b MM |
3931 | |
3932 | struct rtx_def * | |
3933 | rs6000_got_register (value) | |
5f59ecb7 | 3934 | rtx value ATTRIBUTE_UNUSED; |
1ff7789b | 3935 | { |
8d30c4ee FS |
3936 | /* The second flow pass currently (June 1999) can't update regs_ever_live |
3937 | without disturbing other parts of the compiler, so update it here to | |
3938 | make the prolog/epilogue code happy. */ | |
3cb999d8 | 3939 | if (no_new_pseudos && ! regs_ever_live[PIC_OFFSET_TABLE_REGNUM]) |
8d30c4ee | 3940 | regs_ever_live[PIC_OFFSET_TABLE_REGNUM] = 1; |
1ff7789b | 3941 | |
8d30c4ee | 3942 | current_function_uses_pic_offset_table = 1; |
3cb999d8 | 3943 | |
1ff7789b MM |
3944 | return pic_offset_table_rtx; |
3945 | } | |
a7df97e6 | 3946 | \f |
71f123ca | 3947 | /* Functions to init, mark and free struct machine_function. |
a7df97e6 MM |
3948 | These will be called, via pointer variables, |
3949 | from push_function_context and pop_function_context. */ | |
3950 | ||
00dba523 NC |
3951 | static void |
3952 | rs6000_init_machine_status (p) | |
a7df97e6 MM |
3953 | struct function *p; |
3954 | { | |
71f123ca FS |
3955 | p->machine = (machine_function *) xcalloc (1, sizeof (machine_function)); |
3956 | } | |
a7df97e6 | 3957 | |
00dba523 NC |
3958 | static void |
3959 | rs6000_free_machine_status (p) | |
a7df97e6 MM |
3960 | struct function *p; |
3961 | { | |
00dba523 NC |
3962 | if (p->machine == NULL) |
3963 | return; | |
a7df97e6 | 3964 | |
00dba523 NC |
3965 | free (p->machine); |
3966 | p->machine = NULL; | |
a7df97e6 MM |
3967 | } |
3968 | ||
9878760c RK |
3969 | \f |
3970 | /* Print an operand. Recognize special options, documented below. */ | |
3971 | ||
38c1f2d7 | 3972 | #if TARGET_ELF |
d9407988 | 3973 | #define SMALL_DATA_RELOC ((rs6000_sdata == SDATA_EABI) ? "sda21" : "sdarel") |
8fbd2dc7 | 3974 | #define SMALL_DATA_REG ((rs6000_sdata == SDATA_EABI) ? 0 : 13) |
ba5e43aa MM |
3975 | #else |
3976 | #define SMALL_DATA_RELOC "sda21" | |
8fbd2dc7 | 3977 | #define SMALL_DATA_REG 0 |
ba5e43aa MM |
3978 | #endif |
3979 | ||
9878760c RK |
3980 | void |
3981 | print_operand (file, x, code) | |
3982 | FILE *file; | |
3983 | rtx x; | |
9ebbca7d | 3984 | int code; |
9878760c RK |
3985 | { |
3986 | int i; | |
a260abc9 | 3987 | HOST_WIDE_INT val; |
9878760c RK |
3988 | |
3989 | /* These macros test for integers and extract the low-order bits. */ | |
3990 | #define INT_P(X) \ | |
3991 | ((GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST_DOUBLE) \ | |
3992 | && GET_MODE (X) == VOIDmode) | |
3993 | ||
3994 | #define INT_LOWPART(X) \ | |
3995 | (GET_CODE (X) == CONST_INT ? INTVAL (X) : CONST_DOUBLE_LOW (X)) | |
3996 | ||
3997 | switch (code) | |
3998 | { | |
a8b3aeda | 3999 | case '.': |
a85d226b RK |
4000 | /* Write out an instruction after the call which may be replaced |
4001 | with glue code by the loader. This depends on the AIX version. */ | |
4002 | asm_fprintf (file, RS6000_CALL_GLUE); | |
a8b3aeda RK |
4003 | return; |
4004 | ||
c81bebd7 MM |
4005 | case '$': |
4006 | /* Write out either a '.' or '$' for the current location, depending | |
4007 | on whether this is Solaris or not. */ | |
4008 | putc ((DEFAULT_ABI == ABI_SOLARIS) ? '.' : '$', file); | |
4009 | return; | |
4010 | ||
81eace42 GK |
4011 | /* %a is output_address. */ |
4012 | ||
9854d9ed RK |
4013 | case 'A': |
4014 | /* If X is a constant integer whose low-order 5 bits are zero, | |
4015 | write 'l'. Otherwise, write 'r'. This is a kludge to fix a bug | |
76229ac8 | 4016 | in the AIX assembler where "sri" with a zero shift count |
9854d9ed RK |
4017 | write a trash instruction. */ |
4018 | if (GET_CODE (x) == CONST_INT && (INTVAL (x) & 31) == 0) | |
76229ac8 | 4019 | putc ('l', file); |
9854d9ed | 4020 | else |
76229ac8 | 4021 | putc ('r', file); |
9854d9ed RK |
4022 | return; |
4023 | ||
4024 | case 'b': | |
e2c953b6 DE |
4025 | /* If constant, low-order 16 bits of constant, unsigned. |
4026 | Otherwise, write normally. */ | |
4027 | if (INT_P (x)) | |
4028 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 0xffff); | |
4029 | else | |
4030 | print_operand (file, x, 0); | |
cad12a8d RK |
4031 | return; |
4032 | ||
a260abc9 DE |
4033 | case 'B': |
4034 | /* If the low-order bit is zero, write 'r'; otherwise, write 'l' | |
4035 | for 64-bit mask direction. */ | |
296b8152 | 4036 | putc (((INT_LOWPART(x) & 1) == 0 ? 'r' : 'l'), file); |
a238cd8b | 4037 | return; |
a260abc9 | 4038 | |
81eace42 GK |
4039 | /* %c is output_addr_const if a CONSTANT_ADDRESS_P, otherwise |
4040 | output_operand. */ | |
4041 | ||
9854d9ed | 4042 | case 'D': |
39a10a29 GK |
4043 | /* There used to be a comment for 'C' reading "This is an |
4044 | optional cror needed for certain floating-point | |
4045 | comparisons. Otherwise write nothing." */ | |
4046 | ||
9854d9ed RK |
4047 | /* Similar, except that this is for an scc, so we must be able to |
4048 | encode the test in a single bit that is one. We do the above | |
4049 | for any LE, GE, GEU, or LEU and invert the bit for NE. */ | |
4050 | if (GET_CODE (x) == LE || GET_CODE (x) == GE | |
4051 | || GET_CODE (x) == LEU || GET_CODE (x) == GEU) | |
4052 | { | |
9ebbca7d | 4053 | int base_bit = 4 * (REGNO (XEXP (x, 0)) - CR0_REGNO); |
9854d9ed RK |
4054 | |
4055 | fprintf (file, "cror %d,%d,%d\n\t", base_bit + 3, | |
4056 | base_bit + 2, | |
4057 | base_bit + (GET_CODE (x) == GE || GET_CODE (x) == GEU)); | |
4058 | } | |
4059 | ||
4060 | else if (GET_CODE (x) == NE) | |
4061 | { | |
9ebbca7d | 4062 | int base_bit = 4 * (REGNO (XEXP (x, 0)) - CR0_REGNO); |
9854d9ed RK |
4063 | |
4064 | fprintf (file, "crnor %d,%d,%d\n\t", base_bit + 3, | |
4065 | base_bit + 2, base_bit + 2); | |
4066 | } | |
4067 | return; | |
4068 | ||
4069 | case 'E': | |
39a10a29 | 4070 | /* X is a CR register. Print the number of the EQ bit of the CR */ |
9854d9ed RK |
4071 | if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x))) |
4072 | output_operand_lossage ("invalid %%E value"); | |
78fbdbf7 | 4073 | else |
39a10a29 | 4074 | fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO) + 2); |
a85d226b | 4075 | return; |
9854d9ed RK |
4076 | |
4077 | case 'f': | |
4078 | /* X is a CR register. Print the shift count needed to move it | |
4079 | to the high-order four bits. */ | |
4080 | if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x))) | |
4081 | output_operand_lossage ("invalid %%f value"); | |
4082 | else | |
9ebbca7d | 4083 | fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO)); |
9854d9ed RK |
4084 | return; |
4085 | ||
4086 | case 'F': | |
4087 | /* Similar, but print the count for the rotate in the opposite | |
4088 | direction. */ | |
4089 | if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x))) | |
4090 | output_operand_lossage ("invalid %%F value"); | |
4091 | else | |
9ebbca7d | 4092 | fprintf (file, "%d", 32 - 4 * (REGNO (x) - CR0_REGNO)); |
9854d9ed RK |
4093 | return; |
4094 | ||
4095 | case 'G': | |
4096 | /* X is a constant integer. If it is negative, print "m", | |
4097 | otherwise print "z". This is to make a aze or ame insn. */ | |
4098 | if (GET_CODE (x) != CONST_INT) | |
4099 | output_operand_lossage ("invalid %%G value"); | |
4100 | else if (INTVAL (x) >= 0) | |
76229ac8 | 4101 | putc ('z', file); |
9854d9ed | 4102 | else |
76229ac8 | 4103 | putc ('m', file); |
9854d9ed | 4104 | return; |
e2c953b6 | 4105 | |
9878760c | 4106 | case 'h': |
df3d94ed RK |
4107 | /* If constant, output low-order five bits. Otherwise, |
4108 | write normally. */ | |
9878760c | 4109 | if (INT_P (x)) |
5f59ecb7 | 4110 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 31); |
9878760c RK |
4111 | else |
4112 | print_operand (file, x, 0); | |
4113 | return; | |
4114 | ||
64305719 DE |
4115 | case 'H': |
4116 | /* If constant, output low-order six bits. Otherwise, | |
4117 | write normally. */ | |
4118 | if (INT_P (x)) | |
5f59ecb7 | 4119 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 63); |
64305719 DE |
4120 | else |
4121 | print_operand (file, x, 0); | |
4122 | return; | |
4123 | ||
9854d9ed RK |
4124 | case 'I': |
4125 | /* Print `i' if this is a constant, else nothing. */ | |
9878760c | 4126 | if (INT_P (x)) |
76229ac8 | 4127 | putc ('i', file); |
9878760c RK |
4128 | return; |
4129 | ||
9854d9ed RK |
4130 | case 'j': |
4131 | /* Write the bit number in CCR for jump. */ | |
4132 | i = ccr_bit (x, 0); | |
4133 | if (i == -1) | |
4134 | output_operand_lossage ("invalid %%j code"); | |
9878760c | 4135 | else |
9854d9ed | 4136 | fprintf (file, "%d", i); |
9878760c RK |
4137 | return; |
4138 | ||
9854d9ed RK |
4139 | case 'J': |
4140 | /* Similar, but add one for shift count in rlinm for scc and pass | |
4141 | scc flag to `ccr_bit'. */ | |
4142 | i = ccr_bit (x, 1); | |
4143 | if (i == -1) | |
4144 | output_operand_lossage ("invalid %%J code"); | |
4145 | else | |
a0466a68 RK |
4146 | /* If we want bit 31, write a shift count of zero, not 32. */ |
4147 | fprintf (file, "%d", i == 31 ? 0 : i + 1); | |
9878760c RK |
4148 | return; |
4149 | ||
9854d9ed RK |
4150 | case 'k': |
4151 | /* X must be a constant. Write the 1's complement of the | |
4152 | constant. */ | |
9878760c | 4153 | if (! INT_P (x)) |
9854d9ed | 4154 | output_operand_lossage ("invalid %%k value"); |
e2c953b6 DE |
4155 | else |
4156 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, ~ INT_LOWPART (x)); | |
9878760c RK |
4157 | return; |
4158 | ||
81eace42 | 4159 | case 'K': |
9ebbca7d GK |
4160 | /* X must be a symbolic constant on ELF. Write an |
4161 | expression suitable for an 'addi' that adds in the low 16 | |
4162 | bits of the MEM. */ | |
4163 | if (GET_CODE (x) != CONST) | |
4164 | { | |
4165 | print_operand_address (file, x); | |
4166 | fputs ("@l", file); | |
4167 | } | |
4168 | else | |
4169 | { | |
4170 | if (GET_CODE (XEXP (x, 0)) != PLUS | |
4171 | || (GET_CODE (XEXP (XEXP (x, 0), 0)) != SYMBOL_REF | |
4172 | && GET_CODE (XEXP (XEXP (x, 0), 0)) != LABEL_REF) | |
4173 | || GET_CODE (XEXP (XEXP (x, 0), 1)) != CONST_INT) | |
53cd5d6c | 4174 | output_operand_lossage ("invalid %%K value"); |
9ebbca7d GK |
4175 | print_operand_address (file, XEXP (XEXP (x, 0), 0)); |
4176 | fputs ("@l", file); | |
4177 | print_operand (file, XEXP (XEXP (x, 0), 1), 0); | |
4178 | } | |
81eace42 GK |
4179 | return; |
4180 | ||
4181 | /* %l is output_asm_label. */ | |
9ebbca7d | 4182 | |
9854d9ed RK |
4183 | case 'L': |
4184 | /* Write second word of DImode or DFmode reference. Works on register | |
4185 | or non-indexed memory only. */ | |
4186 | if (GET_CODE (x) == REG) | |
5ebfb2ba | 4187 | fprintf (file, "%s", reg_names[REGNO (x) + 1]); |
9854d9ed RK |
4188 | else if (GET_CODE (x) == MEM) |
4189 | { | |
4190 | /* Handle possible auto-increment. Since it is pre-increment and | |
1427100a | 4191 | we have already done it, we can just use an offset of word. */ |
9854d9ed RK |
4192 | if (GET_CODE (XEXP (x, 0)) == PRE_INC |
4193 | || GET_CODE (XEXP (x, 0)) == PRE_DEC) | |
ed8908e7 RK |
4194 | output_address (plus_constant (XEXP (XEXP (x, 0), 0), |
4195 | UNITS_PER_WORD)); | |
9854d9ed | 4196 | else |
d7624dc0 RK |
4197 | output_address (XEXP (adjust_address_nv (x, SImode, |
4198 | UNITS_PER_WORD), | |
4199 | 0)); | |
ed8908e7 | 4200 | |
ba5e43aa | 4201 | if (small_data_operand (x, GET_MODE (x))) |
8fbd2dc7 MM |
4202 | fprintf (file, "@%s(%s)", SMALL_DATA_RELOC, |
4203 | reg_names[SMALL_DATA_REG]); | |
9854d9ed | 4204 | } |
9878760c | 4205 | return; |
9854d9ed | 4206 | |
9878760c RK |
4207 | case 'm': |
4208 | /* MB value for a mask operand. */ | |
4209 | if (! mask_operand (x, VOIDmode)) | |
4210 | output_operand_lossage ("invalid %%m value"); | |
4211 | ||
4212 | val = INT_LOWPART (x); | |
4213 | ||
4214 | /* If the high bit is set and the low bit is not, the value is zero. | |
4215 | If the high bit is zero, the value is the first 1 bit we find from | |
4216 | the left. */ | |
0858c623 | 4217 | if ((val & 0x80000000) && ((val & 1) == 0)) |
9878760c | 4218 | { |
19d2d16f | 4219 | putc ('0', file); |
9878760c RK |
4220 | return; |
4221 | } | |
0858c623 | 4222 | else if ((val & 0x80000000) == 0) |
9878760c RK |
4223 | { |
4224 | for (i = 1; i < 32; i++) | |
0858c623 | 4225 | if ((val <<= 1) & 0x80000000) |
9878760c RK |
4226 | break; |
4227 | fprintf (file, "%d", i); | |
4228 | return; | |
4229 | } | |
4230 | ||
4231 | /* Otherwise, look for the first 0 bit from the right. The result is its | |
4232 | number plus 1. We know the low-order bit is one. */ | |
4233 | for (i = 0; i < 32; i++) | |
4234 | if (((val >>= 1) & 1) == 0) | |
4235 | break; | |
4236 | ||
a260abc9 | 4237 | /* If we ended in ...01, i would be 0. The correct value is 31, so |
9878760c RK |
4238 | we want 31 - i. */ |
4239 | fprintf (file, "%d", 31 - i); | |
4240 | return; | |
4241 | ||
4242 | case 'M': | |
4243 | /* ME value for a mask operand. */ | |
4244 | if (! mask_operand (x, VOIDmode)) | |
a260abc9 | 4245 | output_operand_lossage ("invalid %%M value"); |
9878760c RK |
4246 | |
4247 | val = INT_LOWPART (x); | |
4248 | ||
4249 | /* If the low bit is set and the high bit is not, the value is 31. | |
4250 | If the low bit is zero, the value is the first 1 bit we find from | |
4251 | the right. */ | |
0858c623 | 4252 | if ((val & 1) && ((val & 0x80000000) == 0)) |
9878760c | 4253 | { |
76229ac8 | 4254 | fputs ("31", file); |
9878760c RK |
4255 | return; |
4256 | } | |
4257 | else if ((val & 1) == 0) | |
4258 | { | |
4259 | for (i = 0; i < 32; i++) | |
4260 | if ((val >>= 1) & 1) | |
4261 | break; | |
4262 | ||
a260abc9 | 4263 | /* If we had ....10, i would be 0. The result should be |
9878760c RK |
4264 | 30, so we need 30 - i. */ |
4265 | fprintf (file, "%d", 30 - i); | |
4266 | return; | |
4267 | } | |
4268 | ||
4269 | /* Otherwise, look for the first 0 bit from the left. The result is its | |
4270 | number minus 1. We know the high-order bit is one. */ | |
4271 | for (i = 0; i < 32; i++) | |
0858c623 | 4272 | if (((val <<= 1) & 0x80000000) == 0) |
9878760c RK |
4273 | break; |
4274 | ||
4275 | fprintf (file, "%d", i); | |
4276 | return; | |
4277 | ||
81eace42 GK |
4278 | /* %n outputs the negative of its operand. */ |
4279 | ||
9878760c RK |
4280 | case 'N': |
4281 | /* Write the number of elements in the vector times 4. */ | |
4282 | if (GET_CODE (x) != PARALLEL) | |
4283 | output_operand_lossage ("invalid %%N value"); | |
e2c953b6 DE |
4284 | else |
4285 | fprintf (file, "%d", XVECLEN (x, 0) * 4); | |
9878760c RK |
4286 | return; |
4287 | ||
4288 | case 'O': | |
4289 | /* Similar, but subtract 1 first. */ | |
4290 | if (GET_CODE (x) != PARALLEL) | |
1427100a | 4291 | output_operand_lossage ("invalid %%O value"); |
e2c953b6 DE |
4292 | else |
4293 | fprintf (file, "%d", (XVECLEN (x, 0) - 1) * 4); | |
9878760c RK |
4294 | return; |
4295 | ||
9854d9ed RK |
4296 | case 'p': |
4297 | /* X is a CONST_INT that is a power of two. Output the logarithm. */ | |
4298 | if (! INT_P (x) | |
2bfcf297 | 4299 | || INT_LOWPART (x) < 0 |
9854d9ed RK |
4300 | || (i = exact_log2 (INT_LOWPART (x))) < 0) |
4301 | output_operand_lossage ("invalid %%p value"); | |
e2c953b6 DE |
4302 | else |
4303 | fprintf (file, "%d", i); | |
9854d9ed RK |
4304 | return; |
4305 | ||
9878760c RK |
4306 | case 'P': |
4307 | /* The operand must be an indirect memory reference. The result | |
4308 | is the register number. */ | |
4309 | if (GET_CODE (x) != MEM || GET_CODE (XEXP (x, 0)) != REG | |
4310 | || REGNO (XEXP (x, 0)) >= 32) | |
4311 | output_operand_lossage ("invalid %%P value"); | |
e2c953b6 DE |
4312 | else |
4313 | fprintf (file, "%d", REGNO (XEXP (x, 0))); | |
9878760c RK |
4314 | return; |
4315 | ||
dfbdccdb GK |
4316 | case 'q': |
4317 | /* This outputs the logical code corresponding to a boolean | |
4318 | expression. The expression may have one or both operands | |
39a10a29 GK |
4319 | negated (if one, only the first one). For condition register |
4320 | logical operations, it will also treat the negated | |
4321 | CR codes as NOTs, but not handle NOTs of them. */ | |
dfbdccdb | 4322 | { |
63bc1d05 | 4323 | const char *const *t = 0; |
dfbdccdb GK |
4324 | const char *s; |
4325 | enum rtx_code code = GET_CODE (x); | |
4326 | static const char * const tbl[3][3] = { | |
4327 | { "and", "andc", "nor" }, | |
4328 | { "or", "orc", "nand" }, | |
4329 | { "xor", "eqv", "xor" } }; | |
4330 | ||
4331 | if (code == AND) | |
4332 | t = tbl[0]; | |
4333 | else if (code == IOR) | |
4334 | t = tbl[1]; | |
4335 | else if (code == XOR) | |
4336 | t = tbl[2]; | |
4337 | else | |
4338 | output_operand_lossage ("invalid %%q value"); | |
4339 | ||
4340 | if (GET_CODE (XEXP (x, 0)) != NOT) | |
4341 | s = t[0]; | |
4342 | else | |
4343 | { | |
4344 | if (GET_CODE (XEXP (x, 1)) == NOT) | |
4345 | s = t[2]; | |
4346 | else | |
4347 | s = t[1]; | |
4348 | } | |
4349 | ||
4350 | fputs (s, file); | |
4351 | } | |
4352 | return; | |
4353 | ||
9854d9ed RK |
4354 | case 'R': |
4355 | /* X is a CR register. Print the mask for `mtcrf'. */ | |
4356 | if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x))) | |
4357 | output_operand_lossage ("invalid %%R value"); | |
4358 | else | |
9ebbca7d | 4359 | fprintf (file, "%d", 128 >> (REGNO (x) - CR0_REGNO)); |
9878760c | 4360 | return; |
9854d9ed RK |
4361 | |
4362 | case 's': | |
4363 | /* Low 5 bits of 32 - value */ | |
4364 | if (! INT_P (x)) | |
4365 | output_operand_lossage ("invalid %%s value"); | |
e2c953b6 DE |
4366 | else |
4367 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, (32 - INT_LOWPART (x)) & 31); | |
9878760c | 4368 | return; |
9854d9ed | 4369 | |
a260abc9 DE |
4370 | case 'S': |
4371 | /* PowerPC64 mask position. All 0's and all 1's are excluded. | |
4372 | CONST_INT 32-bit mask is considered sign-extended so any | |
4373 | transition must occur within the CONST_INT, not on the boundary. */ | |
4374 | if (! mask64_operand (x, VOIDmode)) | |
4375 | output_operand_lossage ("invalid %%S value"); | |
4376 | ||
4377 | val = INT_LOWPART (x); | |
4378 | ||
4379 | if (val & 1) /* Clear Left */ | |
4380 | { | |
a238cd8b DE |
4381 | for (i = 0; i < HOST_BITS_PER_WIDE_INT; i++) |
4382 | if (!((val >>= 1) & 1)) | |
4383 | break; | |
a260abc9 | 4384 | |
a238cd8b DE |
4385 | #if HOST_BITS_PER_WIDE_INT == 32 |
4386 | if (GET_CODE (x) == CONST_DOUBLE && i == 32) | |
4387 | { | |
4388 | val = CONST_DOUBLE_HIGH (x); | |
4389 | ||
4390 | if (val == 0) | |
4391 | --i; | |
4392 | else | |
4393 | for (i = 32; i < 64; i++) | |
4394 | if (!((val >>= 1) & 1)) | |
4395 | break; | |
4396 | } | |
a260abc9 | 4397 | #endif |
a238cd8b DE |
4398 | /* i = index of last set bit from right |
4399 | mask begins at 63 - i from left */ | |
4400 | if (i > 63) | |
4401 | output_operand_lossage ("%%S computed all 1's mask"); | |
cccf3bdc | 4402 | |
a260abc9 DE |
4403 | fprintf (file, "%d", 63 - i); |
4404 | return; | |
4405 | } | |
4406 | else /* Clear Right */ | |
4407 | { | |
a238cd8b DE |
4408 | for (i = 0; i < HOST_BITS_PER_WIDE_INT; i++) |
4409 | if ((val >>= 1) & 1) | |
4410 | break; | |
a260abc9 | 4411 | |
a238cd8b | 4412 | #if HOST_BITS_PER_WIDE_INT == 32 |
a260abc9 DE |
4413 | if (GET_CODE (x) == CONST_DOUBLE && i == 32) |
4414 | { | |
a238cd8b | 4415 | val = CONST_DOUBLE_HIGH (x); |
a260abc9 | 4416 | |
a238cd8b | 4417 | if (val == (HOST_WIDE_INT) -1) |
a260abc9 | 4418 | --i; |
a260abc9 | 4419 | else |
a238cd8b DE |
4420 | for (i = 32; i < 64; i++) |
4421 | if ((val >>= 1) & 1) | |
a260abc9 DE |
4422 | break; |
4423 | } | |
4424 | #endif | |
a238cd8b DE |
4425 | /* i = index of last clear bit from right |
4426 | mask ends at 62 - i from left */ | |
4427 | if (i > 62) | |
4428 | output_operand_lossage ("%%S computed all 0's mask"); | |
cccf3bdc | 4429 | |
a238cd8b | 4430 | fprintf (file, "%d", 62 - i); |
a260abc9 DE |
4431 | return; |
4432 | } | |
4433 | ||
cccf3bdc DE |
4434 | case 'T': |
4435 | /* Print the symbolic name of a branch target register. */ | |
4436 | if (GET_CODE (x) != REG || (REGNO (x) != LINK_REGISTER_REGNUM | |
4437 | && REGNO (x) != COUNT_REGISTER_REGNUM)) | |
4438 | output_operand_lossage ("invalid %%T value"); | |
e2c953b6 | 4439 | else if (REGNO (x) == LINK_REGISTER_REGNUM) |
cccf3bdc DE |
4440 | fputs (TARGET_NEW_MNEMONICS ? "lr" : "r", file); |
4441 | else | |
4442 | fputs ("ctr", file); | |
4443 | return; | |
4444 | ||
9854d9ed | 4445 | case 'u': |
802a0058 | 4446 | /* High-order 16 bits of constant for use in unsigned operand. */ |
9854d9ed RK |
4447 | if (! INT_P (x)) |
4448 | output_operand_lossage ("invalid %%u value"); | |
e2c953b6 DE |
4449 | else |
4450 | fprintf (file, HOST_WIDE_INT_PRINT_HEX, | |
4451 | (INT_LOWPART (x) >> 16) & 0xffff); | |
9878760c RK |
4452 | return; |
4453 | ||
802a0058 MM |
4454 | case 'v': |
4455 | /* High-order 16 bits of constant for use in signed operand. */ | |
4456 | if (! INT_P (x)) | |
4457 | output_operand_lossage ("invalid %%v value"); | |
e2c953b6 DE |
4458 | else |
4459 | { | |
4460 | int value = (INT_LOWPART (x) >> 16) & 0xffff; | |
802a0058 | 4461 | |
e2c953b6 DE |
4462 | /* Solaris assembler doesn't like lis 0,0x8000 */ |
4463 | if (DEFAULT_ABI == ABI_SOLARIS && (value & 0x8000) != 0) | |
4464 | fprintf (file, "%d", value | (~0 << 16)); | |
4465 | else | |
4466 | fprintf (file, "0x%x", value); | |
4467 | return; | |
4468 | } | |
802a0058 | 4469 | |
9854d9ed RK |
4470 | case 'U': |
4471 | /* Print `u' if this has an auto-increment or auto-decrement. */ | |
4472 | if (GET_CODE (x) == MEM | |
4473 | && (GET_CODE (XEXP (x, 0)) == PRE_INC | |
4474 | || GET_CODE (XEXP (x, 0)) == PRE_DEC)) | |
76229ac8 | 4475 | putc ('u', file); |
9854d9ed | 4476 | return; |
9878760c | 4477 | |
e0cd0770 JC |
4478 | case 'V': |
4479 | /* Print the trap code for this operand. */ | |
4480 | switch (GET_CODE (x)) | |
4481 | { | |
4482 | case EQ: | |
4483 | fputs ("eq", file); /* 4 */ | |
4484 | break; | |
4485 | case NE: | |
4486 | fputs ("ne", file); /* 24 */ | |
4487 | break; | |
4488 | case LT: | |
4489 | fputs ("lt", file); /* 16 */ | |
4490 | break; | |
4491 | case LE: | |
4492 | fputs ("le", file); /* 20 */ | |
4493 | break; | |
4494 | case GT: | |
4495 | fputs ("gt", file); /* 8 */ | |
4496 | break; | |
4497 | case GE: | |
4498 | fputs ("ge", file); /* 12 */ | |
4499 | break; | |
4500 | case LTU: | |
4501 | fputs ("llt", file); /* 2 */ | |
4502 | break; | |
4503 | case LEU: | |
4504 | fputs ("lle", file); /* 6 */ | |
4505 | break; | |
4506 | case GTU: | |
4507 | fputs ("lgt", file); /* 1 */ | |
4508 | break; | |
4509 | case GEU: | |
4510 | fputs ("lge", file); /* 5 */ | |
4511 | break; | |
4512 | default: | |
4513 | abort (); | |
4514 | } | |
4515 | break; | |
4516 | ||
9854d9ed RK |
4517 | case 'w': |
4518 | /* If constant, low-order 16 bits of constant, signed. Otherwise, write | |
4519 | normally. */ | |
4520 | if (INT_P (x)) | |
5f59ecb7 DE |
4521 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, |
4522 | ((INT_LOWPART (x) & 0xffff) ^ 0x8000) - 0x8000); | |
9854d9ed RK |
4523 | else |
4524 | print_operand (file, x, 0); | |
9878760c RK |
4525 | return; |
4526 | ||
9854d9ed | 4527 | case 'W': |
e2c953b6 DE |
4528 | /* MB value for a PowerPC64 rldic operand. */ |
4529 | if (! rldic_operand (x, VOIDmode)) | |
4530 | output_operand_lossage ("invalid %%W value"); | |
4531 | ||
4532 | val = (GET_CODE (x) == CONST_INT | |
4533 | ? INTVAL (x) : CONST_DOUBLE_HIGH (x)); | |
4534 | ||
4535 | if (val < 0) | |
4536 | i = -1; | |
9854d9ed | 4537 | else |
e2c953b6 DE |
4538 | for (i = 0; i < HOST_BITS_PER_WIDE_INT; i++) |
4539 | if ((val <<= 1) < 0) | |
4540 | break; | |
4541 | ||
4542 | #if HOST_BITS_PER_WIDE_INT == 32 | |
4543 | if (GET_CODE (x) == CONST_INT && i >= 0) | |
4544 | i += 32; /* zero-extend high-part was all 0's */ | |
4545 | else if (GET_CODE (x) == CONST_DOUBLE && i == 32) | |
4546 | { | |
4547 | val = CONST_DOUBLE_LOW (x); | |
4548 | ||
4549 | if (val == 0) | |
4550 | abort(); | |
4551 | else if (val < 0) | |
4552 | --i; | |
4553 | else | |
4554 | for ( ; i < 64; i++) | |
4555 | if ((val <<= 1) < 0) | |
4556 | break; | |
4557 | } | |
4558 | #endif | |
4559 | ||
4560 | fprintf (file, "%d", i + 1); | |
9854d9ed | 4561 | return; |
9878760c | 4562 | |
9854d9ed RK |
4563 | case 'X': |
4564 | if (GET_CODE (x) == MEM | |
258bfae2 | 4565 | && LEGITIMATE_INDEXED_ADDRESS_P (XEXP (x, 0), 0)) |
76229ac8 | 4566 | putc ('x', file); |
9854d9ed | 4567 | return; |
9878760c | 4568 | |
9854d9ed RK |
4569 | case 'Y': |
4570 | /* Like 'L', for third word of TImode */ | |
4571 | if (GET_CODE (x) == REG) | |
5ebfb2ba | 4572 | fprintf (file, "%s", reg_names[REGNO (x) + 2]); |
9854d9ed | 4573 | else if (GET_CODE (x) == MEM) |
9878760c | 4574 | { |
9854d9ed RK |
4575 | if (GET_CODE (XEXP (x, 0)) == PRE_INC |
4576 | || GET_CODE (XEXP (x, 0)) == PRE_DEC) | |
a54d04b7 | 4577 | output_address (plus_constant (XEXP (XEXP (x, 0), 0), 8)); |
9854d9ed | 4578 | else |
d7624dc0 | 4579 | output_address (XEXP (adjust_address_nv (x, SImode, 8), 0)); |
ba5e43aa | 4580 | if (small_data_operand (x, GET_MODE (x))) |
8fbd2dc7 MM |
4581 | fprintf (file, "@%s(%s)", SMALL_DATA_RELOC, |
4582 | reg_names[SMALL_DATA_REG]); | |
9878760c RK |
4583 | } |
4584 | return; | |
9854d9ed | 4585 | |
9878760c | 4586 | case 'z': |
b4ac57ab RS |
4587 | /* X is a SYMBOL_REF. Write out the name preceded by a |
4588 | period and without any trailing data in brackets. Used for function | |
4d30c363 MM |
4589 | names. If we are configured for System V (or the embedded ABI) on |
4590 | the PowerPC, do not emit the period, since those systems do not use | |
4591 | TOCs and the like. */ | |
9878760c RK |
4592 | if (GET_CODE (x) != SYMBOL_REF) |
4593 | abort (); | |
4594 | ||
b6c9286a MM |
4595 | if (XSTR (x, 0)[0] != '.') |
4596 | { | |
4597 | switch (DEFAULT_ABI) | |
4598 | { | |
4599 | default: | |
4600 | abort (); | |
4601 | ||
4602 | case ABI_AIX: | |
4603 | putc ('.', file); | |
4604 | break; | |
4605 | ||
4606 | case ABI_V4: | |
4607 | case ABI_AIX_NODESC: | |
c81bebd7 | 4608 | case ABI_SOLARIS: |
ee890fe2 | 4609 | case ABI_DARWIN: |
b6c9286a | 4610 | break; |
b6c9286a MM |
4611 | } |
4612 | } | |
9ebbca7d | 4613 | #if TARGET_AIX |
9878760c | 4614 | RS6000_OUTPUT_BASENAME (file, XSTR (x, 0)); |
9ebbca7d GK |
4615 | #else |
4616 | assemble_name (file, XSTR (x, 0)); | |
4617 | #endif | |
9878760c RK |
4618 | return; |
4619 | ||
9854d9ed RK |
4620 | case 'Z': |
4621 | /* Like 'L', for last word of TImode. */ | |
4622 | if (GET_CODE (x) == REG) | |
5ebfb2ba | 4623 | fprintf (file, "%s", reg_names[REGNO (x) + 3]); |
9854d9ed RK |
4624 | else if (GET_CODE (x) == MEM) |
4625 | { | |
4626 | if (GET_CODE (XEXP (x, 0)) == PRE_INC | |
4627 | || GET_CODE (XEXP (x, 0)) == PRE_DEC) | |
a54d04b7 | 4628 | output_address (plus_constant (XEXP (XEXP (x, 0), 0), 12)); |
9854d9ed | 4629 | else |
d7624dc0 | 4630 | output_address (XEXP (adjust_address_nv (x, SImode, 12), 0)); |
ba5e43aa | 4631 | if (small_data_operand (x, GET_MODE (x))) |
8fbd2dc7 MM |
4632 | fprintf (file, "@%s(%s)", SMALL_DATA_RELOC, |
4633 | reg_names[SMALL_DATA_REG]); | |
9854d9ed | 4634 | } |
5c23c401 | 4635 | return; |
9854d9ed | 4636 | |
9878760c RK |
4637 | case 0: |
4638 | if (GET_CODE (x) == REG) | |
4639 | fprintf (file, "%s", reg_names[REGNO (x)]); | |
4640 | else if (GET_CODE (x) == MEM) | |
4641 | { | |
4642 | /* We need to handle PRE_INC and PRE_DEC here, since we need to | |
4643 | know the width from the mode. */ | |
4644 | if (GET_CODE (XEXP (x, 0)) == PRE_INC) | |
79ba6d34 MM |
4645 | fprintf (file, "%d(%s)", GET_MODE_SIZE (GET_MODE (x)), |
4646 | reg_names[REGNO (XEXP (XEXP (x, 0), 0))]); | |
9878760c | 4647 | else if (GET_CODE (XEXP (x, 0)) == PRE_DEC) |
79ba6d34 MM |
4648 | fprintf (file, "%d(%s)", - GET_MODE_SIZE (GET_MODE (x)), |
4649 | reg_names[REGNO (XEXP (XEXP (x, 0), 0))]); | |
9878760c | 4650 | else |
a54d04b7 | 4651 | output_address (XEXP (x, 0)); |
9878760c RK |
4652 | } |
4653 | else | |
a54d04b7 | 4654 | output_addr_const (file, x); |
a85d226b | 4655 | return; |
9878760c RK |
4656 | |
4657 | default: | |
4658 | output_operand_lossage ("invalid %%xn code"); | |
4659 | } | |
4660 | } | |
4661 | \f | |
4662 | /* Print the address of an operand. */ | |
4663 | ||
4664 | void | |
4665 | print_operand_address (file, x) | |
4666 | FILE *file; | |
4667 | register rtx x; | |
4668 | { | |
4669 | if (GET_CODE (x) == REG) | |
4697a36c | 4670 | fprintf (file, "0(%s)", reg_names[ REGNO (x) ]); |
9ebbca7d GK |
4671 | else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST |
4672 | || GET_CODE (x) == LABEL_REF) | |
9878760c RK |
4673 | { |
4674 | output_addr_const (file, x); | |
ba5e43aa | 4675 | if (small_data_operand (x, GET_MODE (x))) |
8fbd2dc7 MM |
4676 | fprintf (file, "@%s(%s)", SMALL_DATA_RELOC, |
4677 | reg_names[SMALL_DATA_REG]); | |
9ebbca7d GK |
4678 | else if (TARGET_TOC) |
4679 | abort(); | |
9878760c RK |
4680 | } |
4681 | else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == REG) | |
4682 | { | |
4683 | if (REGNO (XEXP (x, 0)) == 0) | |
4697a36c MM |
4684 | fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 1)) ], |
4685 | reg_names[ REGNO (XEXP (x, 0)) ]); | |
9878760c | 4686 | else |
4697a36c MM |
4687 | fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 0)) ], |
4688 | reg_names[ REGNO (XEXP (x, 1)) ]); | |
9878760c RK |
4689 | } |
4690 | else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT) | |
5f59ecb7 DE |
4691 | { |
4692 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (XEXP (x, 1))); | |
4693 | fprintf (file, "(%s)", reg_names[ REGNO (XEXP (x, 0)) ]); | |
4694 | } | |
3cb999d8 DE |
4695 | #if TARGET_ELF |
4696 | else if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 0)) == REG | |
4697 | && CONSTANT_P (XEXP (x, 1))) | |
4697a36c MM |
4698 | { |
4699 | output_addr_const (file, XEXP (x, 1)); | |
4700 | fprintf (file, "@l(%s)", reg_names[ REGNO (XEXP (x, 0)) ]); | |
4701 | } | |
3cb999d8 | 4702 | #endif |
9ebbca7d GK |
4703 | else if (LEGITIMATE_CONSTANT_POOL_ADDRESS_P (x)) |
4704 | { | |
2bfcf297 | 4705 | if (TARGET_AIX && (!TARGET_ELF || !TARGET_MINIMAL_TOC)) |
9ebbca7d | 4706 | { |
2bfcf297 DB |
4707 | rtx contains_minus = XEXP (x, 1); |
4708 | rtx minus, symref; | |
4709 | const char *name; | |
9ebbca7d GK |
4710 | |
4711 | /* Find the (minus (sym) (toc)) buried in X, and temporarily | |
4712 | turn it into (sym) for output_addr_const. */ | |
4713 | while (GET_CODE (XEXP (contains_minus, 0)) != MINUS) | |
4714 | contains_minus = XEXP (contains_minus, 0); | |
4715 | ||
2bfcf297 DB |
4716 | minus = XEXP (contains_minus, 0); |
4717 | symref = XEXP (minus, 0); | |
4718 | XEXP (contains_minus, 0) = symref; | |
4719 | if (TARGET_ELF) | |
4720 | { | |
4721 | char *newname; | |
4722 | ||
4723 | name = XSTR (symref, 0); | |
4724 | newname = alloca (strlen (name) + sizeof ("@toc")); | |
4725 | strcpy (newname, name); | |
4726 | strcat (newname, "@toc"); | |
4727 | XSTR (symref, 0) = newname; | |
4728 | } | |
4729 | output_addr_const (file, XEXP (x, 1)); | |
4730 | if (TARGET_ELF) | |
4731 | XSTR (symref, 0) = name; | |
9ebbca7d GK |
4732 | XEXP (contains_minus, 0) = minus; |
4733 | } | |
4734 | else | |
4735 | output_addr_const (file, XEXP (x, 1)); | |
4736 | ||
4737 | fprintf (file, "(%s)", reg_names[REGNO (XEXP (x, 0))]); | |
4738 | } | |
9878760c RK |
4739 | else |
4740 | abort (); | |
4741 | } | |
4742 | \f | |
39a10a29 GK |
4743 | enum rtx_code |
4744 | rs6000_reverse_condition (mode, code) | |
4745 | enum machine_mode mode; | |
4746 | enum rtx_code code; | |
4747 | { | |
4748 | /* Reversal of FP compares takes care -- an ordered compare | |
4749 | becomes an unordered compare and vice versa. */ | |
4750 | if (mode == CCFPmode) | |
bab6226b | 4751 | return reverse_condition_maybe_unordered (code); |
39a10a29 | 4752 | else |
bab6226b | 4753 | return reverse_condition (code); |
39a10a29 GK |
4754 | } |
4755 | ||
4756 | ||
4757 | /* Generate a compare for CODE. Return a brand-new rtx that | |
4758 | represents the result of the compare. */ | |
4759 | static rtx | |
4760 | rs6000_generate_compare (code) | |
4761 | enum rtx_code code; | |
4762 | { | |
4763 | enum machine_mode comp_mode; | |
4764 | rtx compare_result; | |
4765 | ||
4766 | if (rs6000_compare_fp_p) | |
4767 | comp_mode = CCFPmode; | |
4768 | else if (code == GTU || code == LTU | |
4769 | || code == GEU || code == LEU) | |
4770 | comp_mode = CCUNSmode; | |
4771 | else | |
4772 | comp_mode = CCmode; | |
4773 | ||
4774 | /* First, the compare. */ | |
4775 | compare_result = gen_reg_rtx (comp_mode); | |
4776 | emit_insn (gen_rtx_SET (VOIDmode, compare_result, | |
4777 | gen_rtx_COMPARE (comp_mode, | |
4778 | rs6000_compare_op0, | |
4779 | rs6000_compare_op1))); | |
4780 | ||
ca5adc63 | 4781 | /* Some kinds of FP comparisons need an OR operation; |
de6c5979 | 4782 | except for flag_unsafe_math_optimizations we don't bother. */ |
39a10a29 | 4783 | if (rs6000_compare_fp_p |
de6c5979 | 4784 | && ! flag_unsafe_math_optimizations |
39a10a29 GK |
4785 | && (code == LE || code == GE |
4786 | || code == UNEQ || code == LTGT | |
4787 | || code == UNGT || code == UNLT)) | |
4788 | { | |
4789 | enum rtx_code or1, or2; | |
4790 | rtx or1_rtx, or2_rtx, compare2_rtx; | |
4791 | rtx or_result = gen_reg_rtx (CCEQmode); | |
4792 | ||
4793 | switch (code) | |
4794 | { | |
4795 | case LE: or1 = LT; or2 = EQ; break; | |
4796 | case GE: or1 = GT; or2 = EQ; break; | |
4797 | case UNEQ: or1 = UNORDERED; or2 = EQ; break; | |
4798 | case LTGT: or1 = LT; or2 = GT; break; | |
4799 | case UNGT: or1 = UNORDERED; or2 = GT; break; | |
4800 | case UNLT: or1 = UNORDERED; or2 = LT; break; | |
4801 | default: abort (); | |
4802 | } | |
4803 | validate_condition_mode (or1, comp_mode); | |
4804 | validate_condition_mode (or2, comp_mode); | |
4805 | or1_rtx = gen_rtx (or1, SImode, compare_result, const0_rtx); | |
4806 | or2_rtx = gen_rtx (or2, SImode, compare_result, const0_rtx); | |
4807 | compare2_rtx = gen_rtx_COMPARE (CCEQmode, | |
4808 | gen_rtx_IOR (SImode, or1_rtx, or2_rtx), | |
4809 | const_true_rtx); | |
4810 | emit_insn (gen_rtx_SET (VOIDmode, or_result, compare2_rtx)); | |
4811 | ||
4812 | compare_result = or_result; | |
4813 | code = EQ; | |
4814 | } | |
4815 | ||
4816 | validate_condition_mode (code, GET_MODE (compare_result)); | |
4817 | ||
4818 | return gen_rtx (code, VOIDmode, compare_result, const0_rtx); | |
4819 | } | |
4820 | ||
4821 | ||
4822 | /* Emit the RTL for an sCOND pattern. */ | |
4823 | ||
4824 | void | |
4825 | rs6000_emit_sCOND (code, result) | |
4826 | enum rtx_code code; | |
4827 | rtx result; | |
4828 | { | |
4829 | rtx condition_rtx; | |
4830 | enum machine_mode op_mode; | |
4831 | ||
4832 | condition_rtx = rs6000_generate_compare (code); | |
4833 | ||
4834 | op_mode = GET_MODE (rs6000_compare_op0); | |
4835 | if (op_mode == VOIDmode) | |
4836 | op_mode = GET_MODE (rs6000_compare_op1); | |
4837 | ||
4838 | if (TARGET_POWERPC64 && (op_mode == DImode || rs6000_compare_fp_p)) | |
4839 | { | |
4840 | PUT_MODE (condition_rtx, DImode); | |
4841 | convert_move (result, condition_rtx, 0); | |
4842 | } | |
4843 | else | |
4844 | { | |
4845 | PUT_MODE (condition_rtx, SImode); | |
4846 | emit_insn (gen_rtx_SET (VOIDmode, result, condition_rtx)); | |
4847 | } | |
4848 | } | |
4849 | ||
4850 | ||
4851 | /* Emit a branch of kind CODE to location LOC. */ | |
4852 | ||
4853 | void | |
4854 | rs6000_emit_cbranch (code, loc) | |
4855 | enum rtx_code code; | |
4856 | rtx loc; | |
4857 | { | |
4858 | rtx condition_rtx, loc_ref; | |
4859 | ||
4860 | condition_rtx = rs6000_generate_compare (code); | |
4861 | loc_ref = gen_rtx_LABEL_REF (VOIDmode, loc); | |
4862 | emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, | |
4863 | gen_rtx_IF_THEN_ELSE (VOIDmode, condition_rtx, | |
4864 | loc_ref, pc_rtx))); | |
4865 | } | |
4866 | ||
4867 | ||
12a4e8c5 GK |
4868 | /* Return the string to output a conditional branch to LABEL, which is |
4869 | the operand number of the label, or -1 if the branch is really a | |
4870 | conditional return. | |
4871 | ||
4872 | OP is the conditional expression. XEXP (OP, 0) is assumed to be a | |
4873 | condition code register and its mode specifies what kind of | |
4874 | comparison we made. | |
4875 | ||
4876 | REVERSED is non-zero if we should reverse the sense of the comparison. | |
4877 | ||
4878 | INSN is the insn. */ | |
4879 | ||
4880 | char * | |
4881 | output_cbranch (op, label, reversed, insn) | |
4882 | rtx op; | |
4883 | const char * label; | |
4884 | int reversed; | |
4885 | rtx insn; | |
4886 | { | |
4887 | static char string[64]; | |
4888 | enum rtx_code code = GET_CODE (op); | |
4889 | rtx cc_reg = XEXP (op, 0); | |
4890 | enum machine_mode mode = GET_MODE (cc_reg); | |
4891 | int cc_regno = REGNO (cc_reg) - CR0_REGNO; | |
39a10a29 | 4892 | int need_longbranch = label != NULL && get_attr_length (insn) == 8; |
12a4e8c5 GK |
4893 | int really_reversed = reversed ^ need_longbranch; |
4894 | char *s = string; | |
4895 | const char *ccode; | |
4896 | const char *pred; | |
4897 | rtx note; | |
4898 | ||
39a10a29 GK |
4899 | validate_condition_mode (code, mode); |
4900 | ||
4901 | /* Work out which way this really branches. We could use | |
4902 | reverse_condition_maybe_unordered here always but this | |
4903 | makes the resulting assembler clearer. */ | |
12a4e8c5 | 4904 | if (really_reversed) |
39a10a29 | 4905 | code = rs6000_reverse_condition (mode, code); |
12a4e8c5 | 4906 | |
39a10a29 | 4907 | switch (code) |
12a4e8c5 GK |
4908 | { |
4909 | /* Not all of these are actually distinct opcodes, but | |
4910 | we distinguish them for clarity of the resulting assembler. */ | |
50a0b056 GK |
4911 | case NE: case LTGT: |
4912 | ccode = "ne"; break; | |
4913 | case EQ: case UNEQ: | |
4914 | ccode = "eq"; break; | |
4915 | case GE: case GEU: | |
4916 | ccode = "ge"; break; | |
4917 | case GT: case GTU: case UNGT: | |
4918 | ccode = "gt"; break; | |
4919 | case LE: case LEU: | |
4920 | ccode = "le"; break; | |
4921 | case LT: case LTU: case UNLT: | |
4922 | ccode = "lt"; break; | |
12a4e8c5 GK |
4923 | case UNORDERED: ccode = "un"; break; |
4924 | case ORDERED: ccode = "nu"; break; | |
4925 | case UNGE: ccode = "nl"; break; | |
4926 | case UNLE: ccode = "ng"; break; | |
4927 | default: | |
4928 | abort(); | |
4929 | } | |
4930 | ||
94a54f47 GK |
4931 | /* Maybe we have a guess as to how likely the branch is. |
4932 | The old mnemonics don't have a way to specify this information. */ | |
12a4e8c5 GK |
4933 | note = find_reg_note (insn, REG_BR_PROB, NULL_RTX); |
4934 | if (note != NULL_RTX) | |
4935 | { | |
4936 | /* PROB is the difference from 50%. */ | |
4937 | int prob = INTVAL (XEXP (note, 0)) - REG_BR_PROB_BASE / 2; | |
4938 | ||
4939 | /* For branches that are very close to 50%, assume not-taken. */ | |
4940 | if (abs (prob) > REG_BR_PROB_BASE / 20 | |
4941 | && ((prob > 0) ^ need_longbranch)) | |
4942 | pred = "+"; | |
4943 | else | |
4944 | pred = "-"; | |
4945 | } | |
4946 | else | |
4947 | pred = ""; | |
4948 | ||
4949 | if (label == NULL) | |
94a54f47 | 4950 | s += sprintf (s, "{b%sr|b%slr%s} ", ccode, ccode, pred); |
12a4e8c5 | 4951 | else |
94a54f47 | 4952 | s += sprintf (s, "{b%s|b%s%s} ", ccode, ccode, pred); |
12a4e8c5 | 4953 | |
37c67319 GK |
4954 | /* We need to escape any '%' characters in the reg_names string. |
4955 | Assume they'd only be the first character... */ | |
4956 | if (reg_names[cc_regno + CR0_REGNO][0] == '%') | |
4957 | *s++ = '%'; | |
94a54f47 | 4958 | s += sprintf (s, "%s", reg_names[cc_regno + CR0_REGNO]); |
12a4e8c5 GK |
4959 | |
4960 | if (label != NULL) | |
4961 | { | |
4962 | /* If the branch distance was too far, we may have to use an | |
4963 | unconditional branch to go the distance. */ | |
4964 | if (need_longbranch) | |
33011c35 | 4965 | s += sprintf (s, ",%c$+8\n\tb %s", '%', label); |
12a4e8c5 GK |
4966 | else |
4967 | s += sprintf (s, ",%s", label); | |
4968 | } | |
4969 | ||
4970 | return string; | |
4971 | } | |
50a0b056 GK |
4972 | |
4973 | /* Emit a conditional move: move TRUE_COND to DEST if OP of the | |
4974 | operands of the last comparison is nonzero/true, FALSE_COND if it | |
4975 | is zero/false. Return 0 if the hardware has no such operation. */ | |
4976 | int | |
4977 | rs6000_emit_cmove (dest, op, true_cond, false_cond) | |
4978 | rtx dest; | |
4979 | rtx op; | |
4980 | rtx true_cond; | |
4981 | rtx false_cond; | |
4982 | { | |
4983 | enum rtx_code code = GET_CODE (op); | |
4984 | rtx op0 = rs6000_compare_op0; | |
4985 | rtx op1 = rs6000_compare_op1; | |
4986 | REAL_VALUE_TYPE c1; | |
4987 | enum machine_mode mode = GET_MODE (op0); | |
4988 | rtx temp; | |
4989 | ||
4990 | /* First, work out if the hardware can do this at all, or | |
4991 | if it's too slow... */ | |
4992 | /* If the comparison is an integer one, since we only have fsel | |
4993 | it'll be cheaper to use a branch. */ | |
4994 | if (! rs6000_compare_fp_p) | |
4995 | return 0; | |
4996 | ||
4997 | /* Eliminate half of the comparisons by switching operands, this | |
4998 | makes the remaining code simpler. */ | |
4999 | if (code == UNLT || code == UNGT || code == UNORDERED || code == NE | |
5000 | || code == LTGT || code == LT) | |
5001 | { | |
5002 | code = reverse_condition_maybe_unordered (code); | |
5003 | temp = true_cond; | |
5004 | true_cond = false_cond; | |
5005 | false_cond = temp; | |
5006 | } | |
5007 | ||
5008 | /* UNEQ and LTGT take four instructions for a comparison with zero, | |
5009 | it'll probably be faster to use a branch here too. */ | |
5010 | if (code == UNEQ) | |
5011 | return 0; | |
5012 | ||
5013 | if (GET_CODE (op1) == CONST_DOUBLE) | |
5014 | REAL_VALUE_FROM_CONST_DOUBLE (c1, op1); | |
5015 | ||
5016 | /* We're going to try to implement comparions by performing | |
5017 | a subtract, then comparing against zero. Unfortunately, | |
5018 | Inf - Inf is NaN which is not zero, and so if we don't | |
5019 | know that the the operand is finite and the comparison | |
5020 | would treat EQ different to UNORDERED, we can't do it. */ | |
5021 | if (! flag_unsafe_math_optimizations | |
5022 | && code != GT && code != UNGE | |
5023 | && (GET_CODE (op1) != CONST_DOUBLE || target_isinf (c1)) | |
5024 | /* Constructs of the form (a OP b ? a : b) are safe. */ | |
5025 | && ((! rtx_equal_p (op0, false_cond) && ! rtx_equal_p (op1, false_cond)) | |
5026 | || (! rtx_equal_p (op0, true_cond) | |
5027 | && ! rtx_equal_p (op1, true_cond)))) | |
5028 | return 0; | |
5029 | /* At this point we know we can use fsel. */ | |
5030 | ||
5031 | /* Reduce the comparison to a comparison against zero. */ | |
5032 | temp = gen_reg_rtx (mode); | |
5033 | emit_insn (gen_rtx_SET (VOIDmode, temp, | |
5034 | gen_rtx_MINUS (mode, op0, op1))); | |
5035 | op0 = temp; | |
5036 | op1 = CONST0_RTX (mode); | |
5037 | ||
5038 | /* If we don't care about NaNs we can reduce some of the comparisons | |
5039 | down to faster ones. */ | |
5040 | if (flag_unsafe_math_optimizations) | |
5041 | switch (code) | |
5042 | { | |
5043 | case GT: | |
5044 | code = LE; | |
5045 | temp = true_cond; | |
5046 | true_cond = false_cond; | |
5047 | false_cond = temp; | |
5048 | break; | |
5049 | case UNGE: | |
5050 | code = GE; | |
5051 | break; | |
5052 | case UNEQ: | |
5053 | code = EQ; | |
5054 | break; | |
5055 | default: | |
5056 | break; | |
5057 | } | |
5058 | ||
5059 | /* Now, reduce everything down to a GE. */ | |
5060 | switch (code) | |
5061 | { | |
5062 | case GE: | |
5063 | break; | |
5064 | ||
5065 | case LE: | |
5066 | temp = gen_reg_rtx (mode); | |
5067 | emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (mode, op0))); | |
5068 | op0 = temp; | |
5069 | break; | |
5070 | ||
5071 | case ORDERED: | |
5072 | temp = gen_reg_rtx (mode); | |
5073 | emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_ABS (mode, op0))); | |
5074 | op0 = temp; | |
5075 | break; | |
5076 | ||
5077 | case EQ: | |
5078 | temp = gen_reg_rtx (mode); | |
5079 | emit_insn (gen_rtx_SET (VOIDmode, temp, | |
5080 | gen_rtx_NEG (mode, | |
5081 | gen_rtx_ABS (mode, op0)))); | |
5082 | op0 = temp; | |
5083 | break; | |
5084 | ||
5085 | case UNGE: | |
5086 | temp = gen_reg_rtx (mode); | |
5087 | emit_insn (gen_rtx_SET (VOIDmode, temp, | |
5088 | gen_rtx_IF_THEN_ELSE (mode, | |
5089 | gen_rtx_GE (VOIDmode, | |
5090 | op0, op1), | |
5091 | true_cond, false_cond))); | |
5092 | false_cond = temp; | |
5093 | true_cond = false_cond; | |
5094 | ||
5095 | temp = gen_reg_rtx (mode); | |
5096 | emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (mode, op0))); | |
5097 | op0 = temp; | |
5098 | break; | |
5099 | ||
5100 | case GT: | |
5101 | temp = gen_reg_rtx (mode); | |
5102 | emit_insn (gen_rtx_SET (VOIDmode, temp, | |
5103 | gen_rtx_IF_THEN_ELSE (mode, | |
5104 | gen_rtx_GE (VOIDmode, | |
5105 | op0, op1), | |
5106 | true_cond, false_cond))); | |
5107 | true_cond = temp; | |
5108 | false_cond = true_cond; | |
5109 | ||
5110 | temp = gen_reg_rtx (mode); | |
5111 | emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (mode, op0))); | |
5112 | op0 = temp; | |
5113 | break; | |
5114 | ||
5115 | default: | |
5116 | abort (); | |
5117 | } | |
5118 | ||
5119 | emit_insn (gen_rtx_SET (VOIDmode, dest, | |
5120 | gen_rtx_IF_THEN_ELSE (mode, | |
5121 | gen_rtx_GE (VOIDmode, | |
5122 | op0, op1), | |
5123 | true_cond, false_cond))); | |
5124 | return 1; | |
5125 | } | |
5126 | ||
5127 | void | |
5128 | rs6000_emit_minmax (dest, code, op0, op1) | |
5129 | rtx dest; | |
5130 | enum rtx_code code; | |
5131 | rtx op0; | |
5132 | rtx op1; | |
5133 | { | |
5134 | enum machine_mode mode = GET_MODE (op0); | |
5135 | rtx target; | |
5136 | if (code == SMAX || code == UMAX) | |
5137 | target = emit_conditional_move (dest, GE, op0, op1, mode, | |
5138 | op0, op1, mode, 0); | |
5139 | else | |
5140 | target = emit_conditional_move (dest, GE, op0, op1, mode, | |
5141 | op1, op0, mode, 0); | |
5142 | if (target == NULL_RTX) | |
5143 | abort (); | |
5144 | if (target != dest) | |
5145 | emit_move_insn (dest, target); | |
5146 | } | |
12a4e8c5 | 5147 | \f |
9878760c RK |
5148 | /* This page contains routines that are used to determine what the function |
5149 | prologue and epilogue code will do and write them out. */ | |
5150 | ||
5151 | /* Return the first fixed-point register that is required to be saved. 32 if | |
5152 | none. */ | |
5153 | ||
5154 | int | |
5155 | first_reg_to_save () | |
5156 | { | |
5157 | int first_reg; | |
5158 | ||
5159 | /* Find lowest numbered live register. */ | |
5160 | for (first_reg = 13; first_reg <= 31; first_reg++) | |
a38d360d GK |
5161 | if (regs_ever_live[first_reg] |
5162 | && (! call_used_regs[first_reg] | |
5163 | || (first_reg == PIC_OFFSET_TABLE_REGNUM | |
ee890fe2 SS |
5164 | && (((DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) |
5165 | && flag_pic == 1) | |
5166 | || (DEFAULT_ABI == ABI_DARWIN | |
5167 | && flag_pic))))) | |
9878760c RK |
5168 | break; |
5169 | ||
b5253831 DE |
5170 | if (profile_flag) |
5171 | { | |
5172 | /* AIX must save/restore every register that contains a parameter | |
5173 | before/after the .__mcount call plus an additional register | |
5174 | for the static chain, if needed; use registers from 30 down to 22 | |
5175 | to do this. */ | |
ee890fe2 | 5176 | if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) |
b5253831 DE |
5177 | { |
5178 | int last_parm_reg, profile_first_reg; | |
5179 | ||
5180 | /* Figure out last used parameter register. The proper thing | |
5181 | to do is to walk incoming args of the function. A function | |
5182 | might have live parameter registers even if it has no | |
5183 | incoming args. */ | |
5184 | for (last_parm_reg = 10; | |
5185 | last_parm_reg > 2 && ! regs_ever_live [last_parm_reg]; | |
5186 | last_parm_reg--) | |
5187 | ; | |
5188 | ||
5189 | /* Calculate first reg for saving parameter registers | |
5190 | and static chain. | |
5191 | Skip reg 31 which may contain the frame pointer. */ | |
5192 | profile_first_reg = (33 - last_parm_reg | |
5193 | - (current_function_needs_context ? 1 : 0)); | |
ee890fe2 SS |
5194 | #if TARGET_MACHO |
5195 | /* Need to skip another reg to account for R31 being PICBASE | |
5196 | (when flag_pic is set) or R30 being used as the frame | |
5197 | pointer (when flag_pic is not set). */ | |
5198 | --profile_first_reg; | |
5199 | #endif | |
b5253831 DE |
5200 | /* Do not save frame pointer if no parameters needs to be saved. */ |
5201 | if (profile_first_reg == 31) | |
5202 | profile_first_reg = 32; | |
5203 | ||
5204 | if (first_reg > profile_first_reg) | |
5205 | first_reg = profile_first_reg; | |
5206 | } | |
e165f3f0 | 5207 | |
b5253831 DE |
5208 | /* SVR4 may need one register to preserve the static chain. */ |
5209 | else if (current_function_needs_context) | |
5210 | { | |
5211 | /* Skip reg 31 which may contain the frame pointer. */ | |
5212 | if (first_reg > 30) | |
5213 | first_reg = 30; | |
5214 | } | |
5215 | } | |
e165f3f0 | 5216 | |
ee890fe2 SS |
5217 | #if TARGET_MACHO |
5218 | if (flag_pic && current_function_uses_pic_offset_table && | |
5219 | (first_reg > PIC_OFFSET_TABLE_REGNUM)) | |
5220 | return PIC_OFFSET_TABLE_REGNUM; | |
5221 | #endif | |
5222 | ||
9878760c RK |
5223 | return first_reg; |
5224 | } | |
5225 | ||
5226 | /* Similar, for FP regs. */ | |
5227 | ||
5228 | int | |
5229 | first_fp_reg_to_save () | |
5230 | { | |
5231 | int first_reg; | |
5232 | ||
5233 | /* Find lowest numbered live register. */ | |
5234 | for (first_reg = 14 + 32; first_reg <= 63; first_reg++) | |
5235 | if (regs_ever_live[first_reg]) | |
5236 | break; | |
5237 | ||
5238 | return first_reg; | |
5239 | } | |
4697a36c MM |
5240 | \f |
5241 | /* Calculate the stack information for the current function. This is | |
5242 | complicated by having two separate calling sequences, the AIX calling | |
5243 | sequence and the V.4 calling sequence. | |
5244 | ||
ee890fe2 | 5245 | AIX (and Darwin/Mac OS) stack frames look like: |
a260abc9 | 5246 | 32-bit 64-bit |
4697a36c | 5247 | SP----> +---------------------------------------+ |
a260abc9 | 5248 | | back chain to caller | 0 0 |
4697a36c | 5249 | +---------------------------------------+ |
a260abc9 | 5250 | | saved CR | 4 8 (8-11) |
4697a36c | 5251 | +---------------------------------------+ |
a260abc9 | 5252 | | saved LR | 8 16 |
4697a36c | 5253 | +---------------------------------------+ |
a260abc9 | 5254 | | reserved for compilers | 12 24 |
4697a36c | 5255 | +---------------------------------------+ |
a260abc9 | 5256 | | reserved for binders | 16 32 |
4697a36c | 5257 | +---------------------------------------+ |
a260abc9 | 5258 | | saved TOC pointer | 20 40 |
4697a36c | 5259 | +---------------------------------------+ |
a260abc9 | 5260 | | Parameter save area (P) | 24 48 |
4697a36c | 5261 | +---------------------------------------+ |
a260abc9 | 5262 | | Alloca space (A) | 24+P etc. |
802a0058 | 5263 | +---------------------------------------+ |
a7df97e6 | 5264 | | Local variable space (L) | 24+P+A |
4697a36c | 5265 | +---------------------------------------+ |
a7df97e6 | 5266 | | Float/int conversion temporary (X) | 24+P+A+L |
4697a36c | 5267 | +---------------------------------------+ |
a7df97e6 | 5268 | | Save area for GP registers (G) | 24+P+A+X+L |
4697a36c | 5269 | +---------------------------------------+ |
a7df97e6 | 5270 | | Save area for FP registers (F) | 24+P+A+X+L+G |
4697a36c MM |
5271 | +---------------------------------------+ |
5272 | old SP->| back chain to caller's caller | | |
5273 | +---------------------------------------+ | |
5274 | ||
5376a30c KR |
5275 | The required alignment for AIX configurations is two words (i.e., 8 |
5276 | or 16 bytes). | |
5277 | ||
5278 | ||
4697a36c MM |
5279 | V.4 stack frames look like: |
5280 | ||
5281 | SP----> +---------------------------------------+ | |
5282 | | back chain to caller | 0 | |
5283 | +---------------------------------------+ | |
5eb387b8 | 5284 | | caller's saved LR | 4 |
4697a36c MM |
5285 | +---------------------------------------+ |
5286 | | Parameter save area (P) | 8 | |
5287 | +---------------------------------------+ | |
a7df97e6 MM |
5288 | | Alloca space (A) | 8+P |
5289 | +---------------------------------------+ | |
5290 | | Varargs save area (V) | 8+P+A | |
5291 | +---------------------------------------+ | |
5292 | | Local variable space (L) | 8+P+A+V | |
5293 | +---------------------------------------+ | |
5294 | | Float/int conversion temporary (X) | 8+P+A+V+L | |
4697a36c | 5295 | +---------------------------------------+ |
a7df97e6 MM |
5296 | | saved CR (C) | 8+P+A+V+L+X |
5297 | +---------------------------------------+ | |
5298 | | Save area for GP registers (G) | 8+P+A+V+L+X+C | |
5299 | +---------------------------------------+ | |
5300 | | Save area for FP registers (F) | 8+P+A+V+L+X+C+G | |
4697a36c MM |
5301 | +---------------------------------------+ |
5302 | old SP->| back chain to caller's caller | | |
5303 | +---------------------------------------+ | |
b6c9286a | 5304 | |
5376a30c KR |
5305 | The required alignment for V.4 is 16 bytes, or 8 bytes if -meabi is |
5306 | given. (But note below and in sysv4.h that we require only 8 and | |
5307 | may round up the size of our stack frame anyways. The historical | |
5308 | reason is early versions of powerpc-linux which didn't properly | |
5309 | align the stack at program startup. A happy side-effect is that | |
5310 | -mno-eabi libraries can be used with -meabi programs.) | |
5311 | ||
b6c9286a | 5312 | |
5376a30c KR |
5313 | The EABI configuration defaults to the V.4 layout, unless |
5314 | -mcall-aix is used, in which case the AIX layout is used. However, | |
5315 | the stack alignment requirements may differ. If -mno-eabi is not | |
5316 | given, the required stack alignment is 8 bytes; if -mno-eabi is | |
5317 | given, the required alignment is 16 bytes. (But see V.4 comment | |
5318 | above.) */ | |
4697a36c | 5319 | |
61b2fbe7 MM |
5320 | #ifndef ABI_STACK_BOUNDARY |
5321 | #define ABI_STACK_BOUNDARY STACK_BOUNDARY | |
5322 | #endif | |
5323 | ||
4697a36c MM |
5324 | rs6000_stack_t * |
5325 | rs6000_stack_info () | |
5326 | { | |
5327 | static rs6000_stack_t info, zero_info; | |
5328 | rs6000_stack_t *info_ptr = &info; | |
9ebbca7d | 5329 | int reg_size = TARGET_POWERPC64 ? 8 : 4; |
24d304eb | 5330 | enum rs6000_abi abi; |
83720594 | 5331 | int ehrd_size; |
b6c9286a | 5332 | int total_raw_size; |
4697a36c MM |
5333 | |
5334 | /* Zero all fields portably */ | |
5335 | info = zero_info; | |
5336 | ||
5337 | /* Select which calling sequence */ | |
b6c9286a | 5338 | info_ptr->abi = abi = DEFAULT_ABI; |
9878760c | 5339 | |
4697a36c MM |
5340 | /* Calculate which registers need to be saved & save area size */ |
5341 | info_ptr->first_gp_reg_save = first_reg_to_save (); | |
906fb125 GK |
5342 | /* Assume that we will have to save PIC_OFFSET_TABLE_REGNUM, |
5343 | even if it currently looks like we won't. */ | |
2bfcf297 DB |
5344 | if (((TARGET_TOC && TARGET_MINIMAL_TOC) |
5345 | || (flag_pic == 1 | |
5346 | && (abi == ABI_V4 || abi == ABI_SOLARIS)) | |
ee890fe2 SS |
5347 | || (flag_pic && |
5348 | abi == ABI_DARWIN)) | |
906fb125 GK |
5349 | && info_ptr->first_gp_reg_save > PIC_OFFSET_TABLE_REGNUM) |
5350 | info_ptr->gp_size = reg_size * (32 - PIC_OFFSET_TABLE_REGNUM); | |
5351 | else | |
5352 | info_ptr->gp_size = reg_size * (32 - info_ptr->first_gp_reg_save); | |
4697a36c MM |
5353 | |
5354 | info_ptr->first_fp_reg_save = first_fp_reg_to_save (); | |
5355 | info_ptr->fp_size = 8 * (64 - info_ptr->first_fp_reg_save); | |
5356 | ||
5357 | /* Does this function call anything? */ | |
71f123ca FS |
5358 | info_ptr->calls_p = (! current_function_is_leaf |
5359 | || cfun->machine->ra_needs_full_frame); | |
b6c9286a | 5360 | |
4697a36c | 5361 | /* Determine if we need to save the link register */ |
71f123ca | 5362 | if (rs6000_ra_ever_killed () |
38c1f2d7 | 5363 | || (DEFAULT_ABI == ABI_AIX && profile_flag) |
4697a36c MM |
5364 | #ifdef TARGET_RELOCATABLE |
5365 | || (TARGET_RELOCATABLE && (get_pool_size () != 0)) | |
5366 | #endif | |
5367 | || (info_ptr->first_fp_reg_save != 64 | |
5368 | && !FP_SAVE_INLINE (info_ptr->first_fp_reg_save)) | |
24d304eb | 5369 | || (abi == ABI_V4 && current_function_calls_alloca) |
c81bebd7 | 5370 | || (abi == ABI_SOLARIS && current_function_calls_alloca) |
ee890fe2 | 5371 | || (DEFAULT_ABI == ABI_DARWIN && flag_pic && current_function_uses_pic_offset_table) |
4697a36c MM |
5372 | || info_ptr->calls_p) |
5373 | { | |
5374 | info_ptr->lr_save_p = 1; | |
9ebbca7d | 5375 | regs_ever_live[LINK_REGISTER_REGNUM] = 1; |
4697a36c MM |
5376 | } |
5377 | ||
9ebbca7d GK |
5378 | /* Determine if we need to save the condition code registers. */ |
5379 | if (regs_ever_live[CR2_REGNO] | |
5380 | || regs_ever_live[CR3_REGNO] | |
5381 | || regs_ever_live[CR4_REGNO]) | |
4697a36c MM |
5382 | { |
5383 | info_ptr->cr_save_p = 1; | |
9ebbca7d | 5384 | if (abi == ABI_V4 || abi == ABI_SOLARIS) |
4697a36c MM |
5385 | info_ptr->cr_size = reg_size; |
5386 | } | |
5387 | ||
83720594 RH |
5388 | /* If the current function calls __builtin_eh_return, then we need |
5389 | to allocate stack space for registers that will hold data for | |
5390 | the exception handler. */ | |
5391 | if (current_function_calls_eh_return) | |
5392 | { | |
5393 | unsigned int i; | |
5394 | for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; ++i) | |
5395 | continue; | |
5396 | ehrd_size = i * UNITS_PER_WORD; | |
5397 | } | |
5398 | else | |
5399 | ehrd_size = 0; | |
5400 | ||
4697a36c MM |
5401 | /* Determine various sizes */ |
5402 | info_ptr->reg_size = reg_size; | |
5403 | info_ptr->fixed_size = RS6000_SAVE_AREA; | |
5404 | info_ptr->varargs_size = RS6000_VARARGS_AREA; | |
189e03e3 DE |
5405 | info_ptr->vars_size = RS6000_ALIGN (get_frame_size (), 8); |
5406 | info_ptr->parm_size = RS6000_ALIGN (current_function_outgoing_args_size, 8); | |
189e03e3 | 5407 | info_ptr->save_size = RS6000_ALIGN (info_ptr->fp_size |
b6c9286a | 5408 | + info_ptr->gp_size |
83720594 | 5409 | + ehrd_size |
b6c9286a MM |
5410 | + info_ptr->cr_size |
5411 | + info_ptr->lr_size | |
9ebbca7d | 5412 | + info_ptr->toc_size, 8); |
ee890fe2 SS |
5413 | if (DEFAULT_ABI == ABI_DARWIN) |
5414 | info_ptr->save_size = RS6000_ALIGN (info_ptr->save_size, 16); | |
b6c9286a | 5415 | |
4697a36c | 5416 | /* Calculate the offsets */ |
24d304eb | 5417 | switch (abi) |
4697a36c | 5418 | { |
b6c9286a | 5419 | case ABI_NONE: |
24d304eb | 5420 | default: |
b6c9286a MM |
5421 | abort (); |
5422 | ||
5423 | case ABI_AIX: | |
5424 | case ABI_AIX_NODESC: | |
ee890fe2 | 5425 | case ABI_DARWIN: |
b6c9286a MM |
5426 | info_ptr->fp_save_offset = - info_ptr->fp_size; |
5427 | info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size; | |
83720594 | 5428 | info_ptr->ehrd_offset = info_ptr->gp_save_offset - ehrd_size; |
a260abc9 DE |
5429 | info_ptr->cr_save_offset = reg_size; /* first word when 64-bit. */ |
5430 | info_ptr->lr_save_offset = 2*reg_size; | |
24d304eb RK |
5431 | break; |
5432 | ||
5433 | case ABI_V4: | |
c81bebd7 | 5434 | case ABI_SOLARIS: |
b6c9286a MM |
5435 | info_ptr->fp_save_offset = - info_ptr->fp_size; |
5436 | info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size; | |
a7df97e6 MM |
5437 | info_ptr->cr_save_offset = info_ptr->gp_save_offset - info_ptr->cr_size; |
5438 | info_ptr->toc_save_offset = info_ptr->cr_save_offset - info_ptr->toc_size; | |
83720594 | 5439 | info_ptr->ehrd_offset = info_ptr->toc_save_offset - ehrd_size; |
b6c9286a MM |
5440 | info_ptr->lr_save_offset = reg_size; |
5441 | break; | |
4697a36c MM |
5442 | } |
5443 | ||
ff381587 MM |
5444 | total_raw_size = (info_ptr->vars_size |
5445 | + info_ptr->parm_size | |
ff381587 MM |
5446 | + info_ptr->save_size |
5447 | + info_ptr->varargs_size | |
5448 | + info_ptr->fixed_size); | |
5449 | ||
5450 | info_ptr->total_size = RS6000_ALIGN (total_raw_size, ABI_STACK_BOUNDARY / BITS_PER_UNIT); | |
5451 | ||
5452 | /* Determine if we need to allocate any stack frame: | |
5453 | ||
5454 | For AIX we need to push the stack if a frame pointer is needed (because | |
5455 | the stack might be dynamically adjusted), if we are debugging, if we | |
9ebbca7d | 5456 | make calls, or if the sum of fp_save, gp_save, and local variables |
ff381587 | 5457 | are more than the space needed to save all non-volatile registers: |
bfc79d3b | 5458 | 32-bit: 18*8 + 19*4 = 220 or 64-bit: 18*8 + 18*8 = 288 (GPR13 reserved). |
ff381587 MM |
5459 | |
5460 | For V.4 we don't have the stack cushion that AIX uses, but assume that | |
5461 | the debugger can handle stackless frames. */ | |
5462 | ||
5463 | if (info_ptr->calls_p) | |
5464 | info_ptr->push_p = 1; | |
5465 | ||
9ebbca7d | 5466 | else if (abi == ABI_V4 || abi == ABI_SOLARIS) |
ff381587 | 5467 | info_ptr->push_p = (total_raw_size > info_ptr->fixed_size |
9ebbca7d | 5468 | || info_ptr->calls_p); |
ff381587 MM |
5469 | |
5470 | else | |
5471 | info_ptr->push_p = (frame_pointer_needed | |
ee890fe2 | 5472 | || (abi != ABI_DARWIN && write_symbols != NO_DEBUG) |
ff381587 | 5473 | || ((total_raw_size - info_ptr->fixed_size) |
bfc79d3b | 5474 | > (TARGET_32BIT ? 220 : 288))); |
ff381587 | 5475 | |
4697a36c | 5476 | /* Zero offsets if we're not saving those registers */ |
8dda1a21 | 5477 | if (info_ptr->fp_size == 0) |
4697a36c MM |
5478 | info_ptr->fp_save_offset = 0; |
5479 | ||
8dda1a21 | 5480 | if (info_ptr->gp_size == 0) |
4697a36c MM |
5481 | info_ptr->gp_save_offset = 0; |
5482 | ||
c81fc13e | 5483 | if (! info_ptr->lr_save_p) |
4697a36c MM |
5484 | info_ptr->lr_save_offset = 0; |
5485 | ||
c81fc13e | 5486 | if (! info_ptr->cr_save_p) |
4697a36c MM |
5487 | info_ptr->cr_save_offset = 0; |
5488 | ||
c81fc13e | 5489 | if (! info_ptr->toc_save_p) |
b6c9286a MM |
5490 | info_ptr->toc_save_offset = 0; |
5491 | ||
4697a36c MM |
5492 | return info_ptr; |
5493 | } | |
5494 | ||
5495 | void | |
5496 | debug_stack_info (info) | |
5497 | rs6000_stack_t *info; | |
9878760c | 5498 | { |
d330fd93 | 5499 | const char *abi_string; |
24d304eb | 5500 | |
c81fc13e | 5501 | if (! info) |
4697a36c MM |
5502 | info = rs6000_stack_info (); |
5503 | ||
5504 | fprintf (stderr, "\nStack information for function %s:\n", | |
5505 | ((current_function_decl && DECL_NAME (current_function_decl)) | |
5506 | ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl)) | |
5507 | : "<unknown>")); | |
5508 | ||
24d304eb RK |
5509 | switch (info->abi) |
5510 | { | |
b6c9286a MM |
5511 | default: abi_string = "Unknown"; break; |
5512 | case ABI_NONE: abi_string = "NONE"; break; | |
5513 | case ABI_AIX: abi_string = "AIX"; break; | |
5514 | case ABI_AIX_NODESC: abi_string = "AIX"; break; | |
ee890fe2 | 5515 | case ABI_DARWIN: abi_string = "Darwin"; break; |
b6c9286a | 5516 | case ABI_V4: abi_string = "V.4"; break; |
c81bebd7 | 5517 | case ABI_SOLARIS: abi_string = "Solaris"; break; |
24d304eb RK |
5518 | } |
5519 | ||
5520 | fprintf (stderr, "\tABI = %5s\n", abi_string); | |
5521 | ||
4697a36c MM |
5522 | if (info->first_gp_reg_save != 32) |
5523 | fprintf (stderr, "\tfirst_gp_reg_save = %5d\n", info->first_gp_reg_save); | |
5524 | ||
5525 | if (info->first_fp_reg_save != 64) | |
5526 | fprintf (stderr, "\tfirst_fp_reg_save = %5d\n", info->first_fp_reg_save); | |
9878760c | 5527 | |
4697a36c MM |
5528 | if (info->lr_save_p) |
5529 | fprintf (stderr, "\tlr_save_p = %5d\n", info->lr_save_p); | |
9878760c | 5530 | |
4697a36c MM |
5531 | if (info->cr_save_p) |
5532 | fprintf (stderr, "\tcr_save_p = %5d\n", info->cr_save_p); | |
5533 | ||
b6c9286a MM |
5534 | if (info->toc_save_p) |
5535 | fprintf (stderr, "\ttoc_save_p = %5d\n", info->toc_save_p); | |
5536 | ||
4697a36c MM |
5537 | if (info->push_p) |
5538 | fprintf (stderr, "\tpush_p = %5d\n", info->push_p); | |
5539 | ||
5540 | if (info->calls_p) | |
5541 | fprintf (stderr, "\tcalls_p = %5d\n", info->calls_p); | |
5542 | ||
4697a36c MM |
5543 | if (info->gp_save_offset) |
5544 | fprintf (stderr, "\tgp_save_offset = %5d\n", info->gp_save_offset); | |
5545 | ||
5546 | if (info->fp_save_offset) | |
5547 | fprintf (stderr, "\tfp_save_offset = %5d\n", info->fp_save_offset); | |
5548 | ||
5549 | if (info->lr_save_offset) | |
5550 | fprintf (stderr, "\tlr_save_offset = %5d\n", info->lr_save_offset); | |
5551 | ||
5552 | if (info->cr_save_offset) | |
5553 | fprintf (stderr, "\tcr_save_offset = %5d\n", info->cr_save_offset); | |
5554 | ||
b6c9286a MM |
5555 | if (info->toc_save_offset) |
5556 | fprintf (stderr, "\ttoc_save_offset = %5d\n", info->toc_save_offset); | |
5557 | ||
4697a36c MM |
5558 | if (info->varargs_save_offset) |
5559 | fprintf (stderr, "\tvarargs_save_offset = %5d\n", info->varargs_save_offset); | |
5560 | ||
5561 | if (info->total_size) | |
5562 | fprintf (stderr, "\ttotal_size = %5d\n", info->total_size); | |
5563 | ||
5564 | if (info->varargs_size) | |
5565 | fprintf (stderr, "\tvarargs_size = %5d\n", info->varargs_size); | |
5566 | ||
5567 | if (info->vars_size) | |
5568 | fprintf (stderr, "\tvars_size = %5d\n", info->vars_size); | |
5569 | ||
5570 | if (info->parm_size) | |
5571 | fprintf (stderr, "\tparm_size = %5d\n", info->parm_size); | |
5572 | ||
5573 | if (info->fixed_size) | |
5574 | fprintf (stderr, "\tfixed_size = %5d\n", info->fixed_size); | |
5575 | ||
5576 | if (info->gp_size) | |
5577 | fprintf (stderr, "\tgp_size = %5d\n", info->gp_size); | |
5578 | ||
5579 | if (info->fp_size) | |
5580 | fprintf (stderr, "\tfp_size = %5d\n", info->fp_size); | |
5581 | ||
b6c9286a MM |
5582 | if (info->lr_size) |
5583 | fprintf (stderr, "\tlr_size = %5d\n", info->cr_size); | |
5584 | ||
4697a36c MM |
5585 | if (info->cr_size) |
5586 | fprintf (stderr, "\tcr_size = %5d\n", info->cr_size); | |
5587 | ||
b6c9286a MM |
5588 | if (info->toc_size) |
5589 | fprintf (stderr, "\ttoc_size = %5d\n", info->toc_size); | |
5590 | ||
4697a36c MM |
5591 | if (info->save_size) |
5592 | fprintf (stderr, "\tsave_size = %5d\n", info->save_size); | |
5593 | ||
5594 | if (info->reg_size != 4) | |
5595 | fprintf (stderr, "\treg_size = %5d\n", info->reg_size); | |
5596 | ||
5597 | fprintf (stderr, "\n"); | |
9878760c | 5598 | } |
71f123ca FS |
5599 | |
5600 | rtx | |
5601 | rs6000_return_addr (count, frame) | |
5602 | int count; | |
5603 | rtx frame; | |
5604 | { | |
71f123ca FS |
5605 | /* Currently we don't optimize very well between prolog and body code and |
5606 | for PIC code the code can be actually quite bad, so don't try to be | |
5607 | too clever here. */ | |
3418dd3a FS |
5608 | if (count != 0 |
5609 | || flag_pic != 0 | |
5610 | || DEFAULT_ABI == ABI_AIX | |
5611 | || DEFAULT_ABI == ABI_AIX_NODESC) | |
71f123ca FS |
5612 | { |
5613 | cfun->machine->ra_needs_full_frame = 1; | |
5614 | return | |
5615 | gen_rtx_MEM (Pmode, | |
3418dd3a | 5616 | memory_address (Pmode, |
71f123ca FS |
5617 | plus_constant (copy_to_reg (gen_rtx_MEM (Pmode, |
5618 | memory_address (Pmode, frame))), | |
5619 | RETURN_ADDRESS_OFFSET))); | |
5620 | } | |
5621 | ||
9e2f7ec7 | 5622 | return get_hard_reg_initial_val (Pmode, LINK_REGISTER_REGNUM); |
71f123ca FS |
5623 | } |
5624 | ||
5625 | static int | |
5626 | rs6000_ra_ever_killed () | |
5627 | { | |
5628 | rtx top; | |
5629 | ||
5630 | #ifdef ASM_OUTPUT_MI_THUNK | |
5631 | if (current_function_is_thunk) | |
5632 | return 0; | |
5633 | #endif | |
9e2f7ec7 DD |
5634 | if (!has_hard_reg_initial_val (Pmode, LINK_REGISTER_REGNUM) |
5635 | || cfun->machine->ra_needs_full_frame) | |
71f123ca FS |
5636 | return regs_ever_live[LINK_REGISTER_REGNUM]; |
5637 | ||
5638 | push_topmost_sequence (); | |
5639 | top = get_insns (); | |
5640 | pop_topmost_sequence (); | |
5641 | ||
5642 | return reg_set_between_p (gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM), | |
5643 | top, NULL_RTX); | |
5644 | } | |
4697a36c | 5645 | \f |
8cd8f856 GK |
5646 | /* Add a REG_MAYBE_DEAD note to the insn. */ |
5647 | static void | |
5648 | rs6000_maybe_dead (insn) | |
5649 | rtx insn; | |
5650 | { | |
5651 | REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD, | |
5652 | const0_rtx, | |
5653 | REG_NOTES (insn)); | |
5654 | } | |
5655 | ||
9ebbca7d | 5656 | /* Emit instructions needed to load the TOC register. |
c7ca610e | 5657 | This is only needed when TARGET_TOC, TARGET_MINIMAL_TOC, and there is |
9ebbca7d | 5658 | a constant pool; or for SVR4 -fpic. */ |
c7ca610e RK |
5659 | |
5660 | void | |
9ebbca7d GK |
5661 | rs6000_emit_load_toc_table (fromprolog) |
5662 | int fromprolog; | |
c7ca610e | 5663 | { |
9ebbca7d GK |
5664 | rtx dest; |
5665 | dest = gen_rtx_REG (Pmode, PIC_OFFSET_TABLE_REGNUM); | |
c7ca610e | 5666 | |
2bfcf297 | 5667 | if (TARGET_ELF && DEFAULT_ABI != ABI_AIX) |
c7ca610e | 5668 | { |
9ebbca7d GK |
5669 | if ((DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) |
5670 | && flag_pic == 1) | |
38c1f2d7 | 5671 | { |
9ebbca7d GK |
5672 | rtx temp = (fromprolog |
5673 | ? gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM) | |
5674 | : gen_reg_rtx (Pmode)); | |
2bfcf297 | 5675 | rs6000_maybe_dead (emit_insn (gen_load_toc_v4_pic_si (temp))); |
8cd8f856 | 5676 | rs6000_maybe_dead (emit_move_insn (dest, temp)); |
38c1f2d7 | 5677 | } |
9ebbca7d GK |
5678 | else if (flag_pic == 2) |
5679 | { | |
5680 | char buf[30]; | |
5681 | rtx tempLR = (fromprolog | |
5682 | ? gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM) | |
5683 | : gen_reg_rtx (Pmode)); | |
5684 | rtx temp0 = (fromprolog | |
5685 | ? gen_rtx_REG (Pmode, 0) | |
5686 | : gen_reg_rtx (Pmode)); | |
5687 | rtx symF; | |
5688 | ||
5689 | /* possibly create the toc section */ | |
5690 | if (! toc_initialized) | |
5691 | { | |
5692 | toc_section (); | |
5693 | function_section (current_function_decl); | |
5694 | } | |
5695 | ||
5696 | if (fromprolog) | |
5697 | { | |
5698 | rtx symL; | |
5699 | ||
5700 | ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno); | |
a8a05998 | 5701 | symF = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); |
38c1f2d7 | 5702 | |
9ebbca7d | 5703 | ASM_GENERATE_INTERNAL_LABEL (buf, "LCL", rs6000_pic_labelno); |
a8a05998 | 5704 | symL = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); |
38c1f2d7 | 5705 | |
8cd8f856 GK |
5706 | rs6000_maybe_dead (emit_insn (gen_load_toc_v4_PIC_1 (tempLR, |
5707 | symF))); | |
5708 | rs6000_maybe_dead (emit_move_insn (dest, tempLR)); | |
5709 | rs6000_maybe_dead (emit_insn (gen_load_toc_v4_PIC_2 (temp0, dest, | |
5710 | symL, | |
5711 | symF))); | |
9ebbca7d GK |
5712 | } |
5713 | else | |
5714 | { | |
5715 | rtx tocsym; | |
5716 | static int reload_toc_labelno = 0; | |
5717 | ||
a8a05998 | 5718 | tocsym = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (toc_label_name)); |
38c1f2d7 | 5719 | |
9ebbca7d | 5720 | ASM_GENERATE_INTERNAL_LABEL (buf, "LCG", reload_toc_labelno++); |
a8a05998 | 5721 | symF = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); |
9ebbca7d | 5722 | |
8cd8f856 GK |
5723 | rs6000_maybe_dead (emit_insn (gen_load_toc_v4_PIC_1b (tempLR, |
5724 | symF, | |
5725 | tocsym))); | |
5726 | rs6000_maybe_dead (emit_move_insn (dest, tempLR)); | |
5727 | rs6000_maybe_dead (emit_move_insn (temp0, | |
5728 | gen_rtx_MEM (Pmode, dest))); | |
9ebbca7d | 5729 | } |
8cd8f856 | 5730 | rs6000_maybe_dead (emit_insn (gen_addsi3 (dest, temp0, dest))); |
9ebbca7d GK |
5731 | } |
5732 | else if (flag_pic == 0 && TARGET_MINIMAL_TOC) | |
5733 | { | |
5734 | /* This is for AIX code running in non-PIC ELF. */ | |
5735 | char buf[30]; | |
5736 | rtx realsym; | |
38c1f2d7 | 5737 | ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1); |
a8a05998 | 5738 | realsym = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); |
9ebbca7d | 5739 | |
8cd8f856 GK |
5740 | rs6000_maybe_dead (emit_insn (gen_elf_high (dest, realsym))); |
5741 | rs6000_maybe_dead (emit_insn (gen_elf_low (dest, dest, realsym))); | |
9ebbca7d GK |
5742 | } |
5743 | else | |
5744 | abort(); | |
5745 | } | |
5746 | else | |
5747 | { | |
5748 | if (TARGET_32BIT) | |
8cd8f856 | 5749 | rs6000_maybe_dead (emit_insn (gen_load_toc_aix_si (dest))); |
9ebbca7d | 5750 | else |
8cd8f856 | 5751 | rs6000_maybe_dead (emit_insn (gen_load_toc_aix_di (dest))); |
9ebbca7d GK |
5752 | } |
5753 | } | |
5754 | ||
5755 | int | |
5756 | get_TOC_alias_set () | |
5757 | { | |
5758 | static int set = -1; | |
5759 | if (set == -1) | |
5760 | set = new_alias_set (); | |
5761 | return set; | |
5762 | } | |
5763 | ||
5764 | /* This retuns nonzero if the current function uses the TOC. This is | |
5765 | determined by the presence of (unspec ... 7), which is generated by | |
5766 | the various load_toc_* patterns. */ | |
5767 | int | |
5768 | uses_TOC () | |
5769 | { | |
5770 | rtx insn; | |
38c1f2d7 | 5771 | |
9ebbca7d | 5772 | for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) |
2c3c49de | 5773 | if (INSN_P (insn)) |
9ebbca7d GK |
5774 | { |
5775 | rtx pat = PATTERN (insn); | |
5776 | int i; | |
5777 | ||
8cd8f856 | 5778 | if (GET_CODE (pat) == PARALLEL) |
9ebbca7d GK |
5779 | for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++) |
5780 | if (GET_CODE (XVECEXP (PATTERN (insn), 0, i)) == UNSPEC | |
5781 | && XINT (XVECEXP (PATTERN (insn), 0, i), 1) == 7) | |
5782 | return 1; | |
38c1f2d7 | 5783 | } |
9ebbca7d GK |
5784 | return 0; |
5785 | } | |
38c1f2d7 | 5786 | |
9ebbca7d GK |
5787 | rtx |
5788 | create_TOC_reference(symbol) | |
5789 | rtx symbol; | |
5790 | { | |
a8a05998 ZW |
5791 | return gen_rtx_PLUS (Pmode, |
5792 | gen_rtx_REG (Pmode, TOC_REGISTER), | |
5793 | gen_rtx_CONST (Pmode, | |
5794 | gen_rtx_MINUS (Pmode, symbol, | |
5795 | gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (toc_label_name))))); | |
9ebbca7d | 5796 | } |
38c1f2d7 | 5797 | |
9ebbca7d GK |
5798 | #if TARGET_AIX |
5799 | /* __throw will restore its own return address to be the same as the | |
5800 | return address of the function that the throw is being made to. | |
5801 | This is unfortunate, because we want to check the original | |
5802 | return address to see if we need to restore the TOC. | |
5803 | So we have to squirrel it away here. | |
5804 | This is used only in compiling __throw and __rethrow. | |
c7ca610e | 5805 | |
9ebbca7d GK |
5806 | Most of this code should be removed by CSE. */ |
5807 | static rtx insn_after_throw; | |
c7ca610e | 5808 | |
9ebbca7d GK |
5809 | /* This does the saving... */ |
5810 | void | |
5811 | rs6000_aix_emit_builtin_unwind_init () | |
5812 | { | |
5813 | rtx mem; | |
5814 | rtx stack_top = gen_reg_rtx (Pmode); | |
5815 | rtx opcode_addr = gen_reg_rtx (Pmode); | |
5816 | ||
5817 | insn_after_throw = gen_reg_rtx (SImode); | |
5818 | ||
5819 | mem = gen_rtx_MEM (Pmode, hard_frame_pointer_rtx); | |
5820 | emit_move_insn (stack_top, mem); | |
5821 | ||
5822 | mem = gen_rtx_MEM (Pmode, | |
5823 | gen_rtx_PLUS (Pmode, stack_top, | |
5824 | GEN_INT (2 * GET_MODE_SIZE (Pmode)))); | |
5825 | emit_move_insn (opcode_addr, mem); | |
5826 | emit_move_insn (insn_after_throw, gen_rtx_MEM (SImode, opcode_addr)); | |
c7ca610e RK |
5827 | } |
5828 | ||
9ebbca7d GK |
5829 | /* Emit insns to _restore_ the TOC register, at runtime (specifically in _eh.o). |
5830 | Only used on AIX. | |
5831 | ||
5832 | The idea is that on AIX, function calls look like this: | |
5833 | bl somefunction-trampoline | |
5834 | lwz r2,20(sp) | |
5835 | ||
5836 | and later, | |
5837 | somefunction-trampoline: | |
5838 | stw r2,20(sp) | |
5839 | ... load function address in the count register ... | |
5840 | bctr | |
5841 | or like this, if the linker determines that this is not a cross-module call | |
5842 | and so the TOC need not be restored: | |
5843 | bl somefunction | |
5844 | nop | |
5845 | or like this, if the compiler could determine that this is not a | |
5846 | cross-module call: | |
5847 | bl somefunction | |
5848 | now, the tricky bit here is that register 2 is saved and restored | |
5849 | by the _linker_, so we can't readily generate debugging information | |
5850 | for it. So we need to go back up the call chain looking at the | |
5851 | insns at return addresses to see which calls saved the TOC register | |
5852 | and so see where it gets restored from. | |
5853 | ||
5854 | Oh, and all this gets done in RTL inside the eh_epilogue pattern, | |
5855 | just before the actual epilogue. | |
5856 | ||
5857 | On the bright side, this incurs no space or time overhead unless an | |
5858 | exception is thrown, except for the extra code in libgcc.a. | |
5859 | ||
5860 | The parameter STACKSIZE is a register containing (at runtime) | |
5861 | the amount to be popped off the stack in addition to the stack frame | |
5862 | of this routine (which will be __throw or __rethrow, and so is | |
5863 | guaranteed to have a stack frame). */ | |
5864 | void | |
5865 | rs6000_emit_eh_toc_restore (stacksize) | |
5866 | rtx stacksize; | |
5867 | { | |
5868 | rtx top_of_stack; | |
5869 | rtx bottom_of_stack = gen_reg_rtx (Pmode); | |
5870 | rtx tocompare = gen_reg_rtx (SImode); | |
5871 | rtx opcode = gen_reg_rtx (SImode); | |
5872 | rtx opcode_addr = gen_reg_rtx (Pmode); | |
5873 | rtx mem; | |
5874 | rtx loop_start = gen_label_rtx (); | |
5875 | rtx no_toc_restore_needed = gen_label_rtx (); | |
5876 | rtx loop_exit = gen_label_rtx (); | |
5877 | ||
5878 | mem = gen_rtx_MEM (Pmode, hard_frame_pointer_rtx); | |
ba4828e0 | 5879 | set_mem_alias_set (mem, rs6000_sr_alias_set); |
9ebbca7d GK |
5880 | emit_move_insn (bottom_of_stack, mem); |
5881 | ||
5882 | top_of_stack = expand_binop (Pmode, add_optab, | |
5883 | bottom_of_stack, stacksize, | |
5884 | NULL_RTX, 1, OPTAB_WIDEN); | |
5885 | ||
5886 | emit_move_insn (tocompare, | |
5887 | GEN_INT (trunc_int_for_mode (TARGET_32BIT | |
5888 | ? 0x80410014 | |
5889 | : 0xE8410028, SImode))); | |
5890 | ||
5891 | if (insn_after_throw == NULL_RTX) | |
5892 | abort(); | |
5893 | emit_move_insn (opcode, insn_after_throw); | |
5894 | ||
6496a589 | 5895 | emit_note (NULL, NOTE_INSN_LOOP_BEG); |
9ebbca7d GK |
5896 | emit_label (loop_start); |
5897 | ||
5898 | do_compare_rtx_and_jump (opcode, tocompare, NE, 1, | |
5899 | SImode, NULL_RTX, 0, NULL_RTX, | |
5900 | no_toc_restore_needed); | |
5901 | ||
5902 | mem = gen_rtx_MEM (Pmode, | |
5903 | gen_rtx_PLUS (Pmode, bottom_of_stack, | |
5904 | GEN_INT (5 * GET_MODE_SIZE (Pmode)))); | |
5905 | emit_move_insn (gen_rtx_REG (Pmode, 2), mem); | |
5906 | ||
5907 | emit_label (no_toc_restore_needed); | |
5908 | do_compare_rtx_and_jump (top_of_stack, bottom_of_stack, EQ, 1, | |
5909 | Pmode, NULL_RTX, 0, NULL_RTX, | |
5910 | loop_exit); | |
5911 | ||
5912 | mem = gen_rtx_MEM (Pmode, bottom_of_stack); | |
ba4828e0 | 5913 | set_mem_alias_set (mem, rs6000_sr_alias_set); |
9ebbca7d GK |
5914 | emit_move_insn (bottom_of_stack, mem); |
5915 | ||
5916 | mem = gen_rtx_MEM (Pmode, | |
5917 | gen_rtx_PLUS (Pmode, bottom_of_stack, | |
5918 | GEN_INT (2 * GET_MODE_SIZE (Pmode)))); | |
5919 | emit_move_insn (opcode_addr, mem); | |
5920 | emit_move_insn (opcode, gen_rtx_MEM (SImode, opcode_addr)); | |
5921 | ||
6496a589 | 5922 | emit_note (NULL, NOTE_INSN_LOOP_CONT); |
9ebbca7d | 5923 | emit_jump (loop_start); |
6496a589 | 5924 | emit_note (NULL, NOTE_INSN_LOOP_END); |
9ebbca7d GK |
5925 | emit_label (loop_exit); |
5926 | } | |
5927 | #endif /* TARGET_AIX */ | |
38c1f2d7 | 5928 | \f |
ba4828e0 RK |
5929 | /* This ties together stack memory (MEM with an alias set of |
5930 | rs6000_sr_alias_set) and the change to the stack pointer. */ | |
5931 | ||
9ebbca7d GK |
5932 | static void |
5933 | rs6000_emit_stack_tie () | |
5934 | { | |
ba4828e0 RK |
5935 | rtx mem = gen_rtx_MEM (BLKmode, gen_rtx_REG (Pmode, STACK_POINTER_REGNUM)); |
5936 | ||
5937 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
9ebbca7d GK |
5938 | emit_insn (gen_stack_tie (mem)); |
5939 | } | |
38c1f2d7 | 5940 | |
9ebbca7d GK |
5941 | /* Emit the correct code for allocating stack space, as insns. |
5942 | If COPY_R12, make sure a copy of the old frame is left in r12. | |
5943 | The generated code may use hard register 0 as a temporary. */ | |
5944 | ||
5945 | static void | |
5946 | rs6000_emit_allocate_stack (size, copy_r12) | |
5947 | HOST_WIDE_INT size; | |
38c1f2d7 MM |
5948 | int copy_r12; |
5949 | { | |
9ebbca7d GK |
5950 | rtx insn; |
5951 | rtx stack_reg = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM); | |
5952 | rtx tmp_reg = gen_rtx_REG (Pmode, 0); | |
5953 | rtx todec = GEN_INT (-size); | |
a157febd GK |
5954 | |
5955 | if (current_function_limit_stack) | |
5956 | { | |
5957 | if (REG_P (stack_limit_rtx) | |
5958 | && REGNO (stack_limit_rtx) > 1 | |
5959 | && REGNO (stack_limit_rtx) <= 31) | |
5960 | { | |
9ebbca7d GK |
5961 | emit_insn (Pmode == SImode |
5962 | ? gen_addsi3 (tmp_reg, | |
5963 | stack_limit_rtx, | |
5964 | GEN_INT (size)) | |
5965 | : gen_adddi3 (tmp_reg, | |
5966 | stack_limit_rtx, | |
5967 | GEN_INT (size))); | |
5968 | ||
5969 | emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg, | |
5970 | const0_rtx)); | |
a157febd GK |
5971 | } |
5972 | else if (GET_CODE (stack_limit_rtx) == SYMBOL_REF | |
9ebbca7d | 5973 | && TARGET_32BIT |
a157febd GK |
5974 | && (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS)) |
5975 | { | |
9ebbca7d GK |
5976 | rtx toload = gen_rtx_CONST (VOIDmode, |
5977 | gen_rtx_PLUS (Pmode, | |
5978 | stack_limit_rtx, | |
5979 | GEN_INT (size))); | |
5980 | ||
5981 | emit_insn (gen_elf_high (tmp_reg, toload)); | |
5982 | emit_insn (gen_elf_low (tmp_reg, tmp_reg, toload)); | |
5983 | emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg, | |
5984 | const0_rtx)); | |
a157febd GK |
5985 | } |
5986 | else | |
5987 | warning ("stack limit expression is not supported"); | |
5988 | } | |
5989 | ||
9ebbca7d GK |
5990 | if (copy_r12 || ! TARGET_UPDATE) |
5991 | emit_move_insn (gen_rtx_REG (Pmode, 12), stack_reg); | |
5992 | ||
38c1f2d7 MM |
5993 | if (TARGET_UPDATE) |
5994 | { | |
9ebbca7d | 5995 | if (size > 32767) |
38c1f2d7 | 5996 | { |
9ebbca7d GK |
5997 | /* Need a note here so that try_split doesn't get confused. */ |
5998 | if (get_last_insn() == NULL_RTX) | |
5999 | emit_note (0, NOTE_INSN_DELETED); | |
6000 | insn = emit_move_insn (tmp_reg, todec); | |
6001 | try_split (PATTERN (insn), insn, 0); | |
6002 | todec = tmp_reg; | |
38c1f2d7 | 6003 | } |
9ebbca7d GK |
6004 | |
6005 | if (Pmode == SImode) | |
6006 | insn = emit_insn (gen_movsi_update (stack_reg, stack_reg, | |
6007 | todec, stack_reg)); | |
6008 | else | |
6009 | insn = emit_insn (gen_movdi_update (stack_reg, stack_reg, | |
6010 | todec, stack_reg)); | |
38c1f2d7 MM |
6011 | } |
6012 | else | |
6013 | { | |
9ebbca7d GK |
6014 | if (Pmode == SImode) |
6015 | insn = emit_insn (gen_addsi3 (stack_reg, stack_reg, todec)); | |
38c1f2d7 | 6016 | else |
9ebbca7d GK |
6017 | insn = emit_insn (gen_adddi3 (stack_reg, stack_reg, todec)); |
6018 | emit_move_insn (gen_rtx_MEM (Pmode, stack_reg), | |
6019 | gen_rtx_REG (Pmode, 12)); | |
6020 | } | |
6021 | ||
6022 | RTX_FRAME_RELATED_P (insn) = 1; | |
6023 | REG_NOTES (insn) = | |
6024 | gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, | |
6025 | gen_rtx_SET (VOIDmode, stack_reg, | |
6026 | gen_rtx_PLUS (Pmode, stack_reg, | |
6027 | GEN_INT (-size))), | |
6028 | REG_NOTES (insn)); | |
6029 | } | |
6030 | ||
6031 | /* Add to 'insn' a note which is PATTERN (INSN) but with REG replaced with | |
6032 | (plus:P (reg 1) VAL), and with REG2 replaced with RREG if REG2 is not | |
6033 | NULL. | |
6034 | It would be nice if dwarf2out_frame_debug_expr could deduce these | |
6035 | equivalences by itself so it wasn't necessary to hold its hand so much. */ | |
6036 | ||
6037 | static void | |
6038 | rs6000_frame_related (insn, reg, val, reg2, rreg) | |
6039 | rtx insn; | |
6040 | rtx reg; | |
6041 | HOST_WIDE_INT val; | |
6042 | rtx reg2; | |
6043 | rtx rreg; | |
6044 | { | |
6045 | rtx real, temp; | |
6046 | ||
6047 | real = copy_rtx (PATTERN (insn)); | |
6048 | ||
6049 | real = replace_rtx (real, reg, | |
6050 | gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode, | |
6051 | STACK_POINTER_REGNUM), | |
6052 | GEN_INT (val))); | |
6053 | ||
6054 | /* We expect that 'real' is either a SET or a PARALLEL containing | |
6055 | SETs (and possibly other stuff). In a PARALLEL, all the SETs | |
6056 | are important so they all have to be marked RTX_FRAME_RELATED_P. */ | |
6057 | ||
6058 | if (GET_CODE (real) == SET) | |
6059 | { | |
6060 | rtx set = real; | |
6061 | ||
6062 | temp = simplify_rtx (SET_SRC (set)); | |
6063 | if (temp) | |
6064 | SET_SRC (set) = temp; | |
6065 | temp = simplify_rtx (SET_DEST (set)); | |
6066 | if (temp) | |
6067 | SET_DEST (set) = temp; | |
6068 | if (GET_CODE (SET_DEST (set)) == MEM) | |
38c1f2d7 | 6069 | { |
9ebbca7d GK |
6070 | temp = simplify_rtx (XEXP (SET_DEST (set), 0)); |
6071 | if (temp) | |
6072 | XEXP (SET_DEST (set), 0) = temp; | |
38c1f2d7 | 6073 | } |
38c1f2d7 | 6074 | } |
9ebbca7d GK |
6075 | else if (GET_CODE (real) == PARALLEL) |
6076 | { | |
6077 | int i; | |
6078 | for (i = 0; i < XVECLEN (real, 0); i++) | |
6079 | if (GET_CODE (XVECEXP (real, 0, i)) == SET) | |
6080 | { | |
6081 | rtx set = XVECEXP (real, 0, i); | |
6082 | ||
6083 | temp = simplify_rtx (SET_SRC (set)); | |
6084 | if (temp) | |
6085 | SET_SRC (set) = temp; | |
6086 | temp = simplify_rtx (SET_DEST (set)); | |
6087 | if (temp) | |
6088 | SET_DEST (set) = temp; | |
6089 | if (GET_CODE (SET_DEST (set)) == MEM) | |
6090 | { | |
6091 | temp = simplify_rtx (XEXP (SET_DEST (set), 0)); | |
6092 | if (temp) | |
6093 | XEXP (SET_DEST (set), 0) = temp; | |
6094 | } | |
6095 | RTX_FRAME_RELATED_P (set) = 1; | |
6096 | } | |
6097 | } | |
6098 | else | |
6099 | abort(); | |
6100 | ||
6101 | if (reg2 != NULL_RTX) | |
6102 | real = replace_rtx (real, reg2, rreg); | |
6103 | ||
6104 | RTX_FRAME_RELATED_P (insn) = 1; | |
6105 | REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, | |
6106 | real, | |
6107 | REG_NOTES (insn)); | |
38c1f2d7 MM |
6108 | } |
6109 | ||
9ebbca7d GK |
6110 | /* Emit function prologue as insns. */ |
6111 | ||
9878760c | 6112 | void |
83720594 | 6113 | rs6000_emit_prologue () |
9878760c | 6114 | { |
4697a36c | 6115 | rs6000_stack_t *info = rs6000_stack_info (); |
9ebbca7d GK |
6116 | enum machine_mode reg_mode = TARGET_POWERPC64 ? DImode : SImode; |
6117 | int reg_size = TARGET_POWERPC64 ? 8 : 4; | |
6118 | rtx sp_reg_rtx = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM); | |
6119 | rtx frame_ptr_rtx = gen_rtx_REG (Pmode, 12); | |
6120 | rtx frame_reg_rtx = sp_reg_rtx; | |
6121 | rtx cr_save_rtx = NULL; | |
6122 | rtx insn; | |
6123 | int saving_FPRs_inline; | |
6124 | int using_store_multiple; | |
6125 | HOST_WIDE_INT sp_offset = 0; | |
6126 | ||
6127 | using_store_multiple = (TARGET_MULTIPLE && ! TARGET_POWERPC64 | |
6128 | && info->first_gp_reg_save < 31); | |
6129 | saving_FPRs_inline = (info->first_fp_reg_save == 64 | |
6130 | || FP_SAVE_INLINE (info->first_fp_reg_save)); | |
6131 | ||
6132 | /* For V.4, update stack before we do any saving and set back pointer. */ | |
6133 | if (info->push_p && (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS)) | |
6134 | { | |
6135 | if (info->total_size < 32767) | |
6136 | sp_offset = info->total_size; | |
6137 | else | |
6138 | frame_reg_rtx = frame_ptr_rtx; | |
6139 | rs6000_emit_allocate_stack (info->total_size, | |
6140 | (frame_reg_rtx != sp_reg_rtx | |
6141 | && (info->cr_save_p | |
6142 | || info->lr_save_p | |
6143 | || info->first_fp_reg_save < 64 | |
6144 | || info->first_gp_reg_save < 32 | |
6145 | ))); | |
6146 | if (frame_reg_rtx != sp_reg_rtx) | |
6147 | rs6000_emit_stack_tie (); | |
6148 | } | |
6149 | ||
6150 | /* If we use the link register, get it into r0. */ | |
6151 | if (info->lr_save_p) | |
71f123ca | 6152 | emit_move_insn (gen_rtx_REG (Pmode, 0), |
9ebbca7d GK |
6153 | gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)); |
6154 | ||
6155 | /* If we need to save CR, put it into r12. */ | |
6156 | if (info->cr_save_p && frame_reg_rtx != frame_ptr_rtx) | |
6157 | { | |
6158 | cr_save_rtx = gen_rtx_REG (SImode, 12); | |
6159 | emit_insn (gen_movesi_from_cr (cr_save_rtx)); | |
6160 | } | |
6161 | ||
6162 | /* Do any required saving of fpr's. If only one or two to save, do it | |
6163 | ourself. Otherwise, call function. */ | |
6164 | if (saving_FPRs_inline) | |
6165 | { | |
6166 | int i; | |
6167 | for (i = 0; i < 64 - info->first_fp_reg_save; i++) | |
6168 | if ((regs_ever_live[info->first_fp_reg_save+i] | |
6169 | && ! call_used_regs[info->first_fp_reg_save+i])) | |
6170 | { | |
6171 | rtx addr, reg, mem; | |
6172 | reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i); | |
6173 | addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
6174 | GEN_INT (info->fp_save_offset | |
6175 | + sp_offset | |
6176 | + 8*i)); | |
6177 | mem = gen_rtx_MEM (DFmode, addr); | |
ba4828e0 | 6178 | set_mem_alias_set (mem, rs6000_sr_alias_set); |
9ebbca7d GK |
6179 | |
6180 | insn = emit_move_insn (mem, reg); | |
6181 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, | |
6182 | NULL_RTX, NULL_RTX); | |
6183 | } | |
6184 | } | |
6185 | else if (info->first_fp_reg_save != 64) | |
6186 | { | |
6187 | int i; | |
6188 | char rname[30]; | |
520a57c8 | 6189 | const char *alloc_rname; |
9ebbca7d GK |
6190 | rtvec p; |
6191 | p = rtvec_alloc (2 + 64 - info->first_fp_reg_save); | |
6192 | ||
6193 | RTVEC_ELT (p, 0) = gen_rtx_CLOBBER (VOIDmode, | |
6194 | gen_rtx_REG (Pmode, | |
6195 | LINK_REGISTER_REGNUM)); | |
6196 | sprintf (rname, "%s%d%s", SAVE_FP_PREFIX, | |
6197 | info->first_fp_reg_save - 32, SAVE_FP_SUFFIX); | |
a8a05998 | 6198 | alloc_rname = ggc_strdup (rname); |
9ebbca7d GK |
6199 | RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode, |
6200 | gen_rtx_SYMBOL_REF (Pmode, | |
6201 | alloc_rname)); | |
6202 | for (i = 0; i < 64 - info->first_fp_reg_save; i++) | |
6203 | { | |
6204 | rtx addr, reg, mem; | |
6205 | reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i); | |
6206 | addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
6207 | GEN_INT (info->fp_save_offset | |
6208 | + sp_offset + 8*i)); | |
6209 | mem = gen_rtx_MEM (DFmode, addr); | |
ba4828e0 | 6210 | set_mem_alias_set (mem, rs6000_sr_alias_set); |
9ebbca7d GK |
6211 | |
6212 | RTVEC_ELT (p, i + 2) = gen_rtx_SET (VOIDmode, mem, reg); | |
6213 | } | |
6214 | insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p)); | |
6215 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, | |
6216 | NULL_RTX, NULL_RTX); | |
6217 | } | |
b6c9286a | 6218 | |
9ebbca7d GK |
6219 | /* Save GPRs. This is done as a PARALLEL if we are using |
6220 | the store-multiple instructions. */ | |
6221 | if (using_store_multiple) | |
b6c9286a | 6222 | { |
9ebbca7d GK |
6223 | rtvec p, dwarfp; |
6224 | int i; | |
6225 | p = rtvec_alloc (32 - info->first_gp_reg_save); | |
6226 | dwarfp = rtvec_alloc (32 - info->first_gp_reg_save); | |
6227 | for (i = 0; i < 32 - info->first_gp_reg_save; i++) | |
6228 | { | |
6229 | rtx addr, reg, mem; | |
6230 | reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i); | |
6231 | addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
6232 | GEN_INT (info->gp_save_offset | |
6233 | + sp_offset | |
6234 | + reg_size * i)); | |
6235 | mem = gen_rtx_MEM (reg_mode, addr); | |
ba4828e0 | 6236 | set_mem_alias_set (mem, rs6000_sr_alias_set); |
9ebbca7d GK |
6237 | |
6238 | RTVEC_ELT (p, i) = gen_rtx_SET (VOIDmode, mem, reg); | |
6239 | } | |
6240 | insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p)); | |
6241 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, | |
6242 | NULL_RTX, NULL_RTX); | |
b6c9286a MM |
6243 | } |
6244 | else | |
6245 | { | |
9ebbca7d GK |
6246 | int i; |
6247 | for (i = 0; i < 32 - info->first_gp_reg_save; i++) | |
6248 | if ((regs_ever_live[info->first_gp_reg_save+i] | |
6249 | && ! call_used_regs[info->first_gp_reg_save+i]) | |
6250 | || (i+info->first_gp_reg_save == PIC_OFFSET_TABLE_REGNUM | |
ee890fe2 SS |
6251 | && (((DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) |
6252 | && flag_pic == 1) | |
6253 | || (DEFAULT_ABI == ABI_DARWIN | |
6254 | && flag_pic)))) | |
9ebbca7d GK |
6255 | { |
6256 | rtx addr, reg, mem; | |
6257 | reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i); | |
6258 | addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
6259 | GEN_INT (info->gp_save_offset | |
6260 | + sp_offset | |
6261 | + reg_size * i)); | |
6262 | mem = gen_rtx_MEM (reg_mode, addr); | |
ba4828e0 | 6263 | set_mem_alias_set (mem, rs6000_sr_alias_set); |
9ebbca7d GK |
6264 | |
6265 | insn = emit_move_insn (mem, reg); | |
6266 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, | |
6267 | NULL_RTX, NULL_RTX); | |
6268 | } | |
6269 | } | |
6270 | ||
83720594 RH |
6271 | /* ??? There's no need to emit actual instructions here, but it's the |
6272 | easiest way to get the frame unwind information emitted. */ | |
6273 | if (current_function_calls_eh_return) | |
6274 | { | |
78e1b90d DE |
6275 | unsigned int i, regno; |
6276 | ||
83720594 RH |
6277 | for (i = 0; ; ++i) |
6278 | { | |
6279 | rtx addr, reg, mem; | |
6280 | ||
6281 | regno = EH_RETURN_DATA_REGNO (i); | |
6282 | if (regno == INVALID_REGNUM) | |
6283 | break; | |
6284 | ||
6285 | reg = gen_rtx_REG (reg_mode, regno); | |
6286 | addr = plus_constant (frame_reg_rtx, | |
78e1b90d DE |
6287 | info->ehrd_offset + sp_offset |
6288 | + reg_size * (int) i); | |
83720594 | 6289 | mem = gen_rtx_MEM (reg_mode, addr); |
ba4828e0 | 6290 | set_mem_alias_set (mem, rs6000_sr_alias_set); |
83720594 RH |
6291 | |
6292 | insn = emit_move_insn (mem, reg); | |
6293 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, | |
6294 | NULL_RTX, NULL_RTX); | |
6295 | } | |
6296 | } | |
6297 | ||
9ebbca7d GK |
6298 | /* Save lr if we used it. */ |
6299 | if (info->lr_save_p) | |
6300 | { | |
6301 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
6302 | GEN_INT (info->lr_save_offset + sp_offset)); | |
6303 | rtx reg = gen_rtx_REG (Pmode, 0); | |
6304 | rtx mem = gen_rtx_MEM (Pmode, addr); | |
6305 | /* This should not be of rs6000_sr_alias_set, because of | |
6306 | __builtin_return_address. */ | |
6307 | ||
6308 | insn = emit_move_insn (mem, reg); | |
6309 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, | |
6310 | reg, gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)); | |
6311 | } | |
6312 | ||
6313 | /* Save CR if we use any that must be preserved. */ | |
6314 | if (info->cr_save_p) | |
6315 | { | |
6316 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
6317 | GEN_INT (info->cr_save_offset + sp_offset)); | |
6318 | rtx mem = gen_rtx_MEM (SImode, addr); | |
ba4828e0 RK |
6319 | |
6320 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
9ebbca7d GK |
6321 | |
6322 | /* If r12 was used to hold the original sp, copy cr into r0 now | |
6323 | that it's free. */ | |
6324 | if (REGNO (frame_reg_rtx) == 12) | |
6325 | { | |
6326 | cr_save_rtx = gen_rtx_REG (SImode, 0); | |
6327 | emit_insn (gen_movesi_from_cr (cr_save_rtx)); | |
6328 | } | |
6329 | insn = emit_move_insn (mem, cr_save_rtx); | |
6330 | ||
6331 | /* Now, there's no way that dwarf2out_frame_debug_expr is going | |
6332 | to understand '(unspec:SI [(reg:CC 68) ...] 19)'. But that's | |
6333 | OK. All we have to do is specify that _one_ condition code | |
6334 | register is saved in this stack slot. The thrower's epilogue | |
6335 | will then restore all the call-saved registers. */ | |
6336 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, | |
6337 | cr_save_rtx, gen_rtx_REG (SImode, CR0_REGNO)); | |
6338 | } | |
6339 | ||
6340 | /* Update stack and set back pointer unless this is V.4, | |
6341 | for which it was done previously. */ | |
6342 | if (info->push_p && DEFAULT_ABI != ABI_V4 && DEFAULT_ABI != ABI_SOLARIS) | |
6343 | rs6000_emit_allocate_stack (info->total_size, FALSE); | |
6344 | ||
6345 | /* Set frame pointer, if needed. */ | |
6346 | if (frame_pointer_needed) | |
6347 | { | |
6348 | insn = emit_move_insn (gen_rtx_REG (reg_mode, FRAME_POINTER_REGNUM), | |
6349 | sp_reg_rtx); | |
6350 | RTX_FRAME_RELATED_P (insn) = 1; | |
b6c9286a | 6351 | } |
9878760c | 6352 | |
9ebbca7d GK |
6353 | /* If we are using PIC_OFFSET_TABLE_REGNUM, we need to set it up. */ |
6354 | if ((TARGET_TOC && TARGET_MINIMAL_TOC && get_pool_size () != 0) | |
6355 | || ((DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) | |
6356 | && flag_pic == 1 && regs_ever_live[PIC_OFFSET_TABLE_REGNUM])) | |
6357 | { | |
6358 | /* If emit_load_toc_table will use the link register, we need to save | |
6359 | it. We use R11 for this purpose because emit_load_toc_table | |
6360 | can use register 0. This allows us to use a plain 'blr' to return | |
6361 | from the procedure more often. */ | |
d5fa86ba GK |
6362 | int save_LR_around_toc_setup = (TARGET_ELF && flag_pic != 0 |
6363 | && ! info->lr_save_p | |
6364 | && EXIT_BLOCK_PTR->pred != NULL); | |
9ebbca7d GK |
6365 | if (save_LR_around_toc_setup) |
6366 | emit_move_insn (gen_rtx_REG (Pmode, 11), | |
6367 | gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)); | |
6368 | ||
6369 | rs6000_emit_load_toc_table (TRUE); | |
6370 | ||
6371 | if (save_LR_around_toc_setup) | |
6372 | emit_move_insn (gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM), | |
6373 | gen_rtx_REG (Pmode, 11)); | |
6374 | } | |
ee890fe2 SS |
6375 | |
6376 | if (DEFAULT_ABI == ABI_DARWIN | |
6377 | && flag_pic && current_function_uses_pic_offset_table) | |
6378 | { | |
6379 | rtx dest = gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM); | |
6380 | ||
6381 | rs6000_maybe_dead (emit_insn (gen_load_macho_picbase (dest))); | |
6382 | ||
6383 | rs6000_maybe_dead ( | |
6384 | emit_move_insn (gen_rtx_REG (Pmode, PIC_OFFSET_TABLE_REGNUM), | |
6385 | gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM))); | |
6386 | } | |
9ebbca7d GK |
6387 | } |
6388 | ||
6389 | ||
6390 | /* Write function prologue. */ | |
08c148a8 NB |
6391 | static void |
6392 | rs6000_output_function_prologue (file, size) | |
9ebbca7d | 6393 | FILE *file; |
08c148a8 | 6394 | HOST_WIDE_INT size ATTRIBUTE_UNUSED; |
9ebbca7d GK |
6395 | { |
6396 | rs6000_stack_t *info = rs6000_stack_info (); | |
6397 | ||
4697a36c MM |
6398 | if (TARGET_DEBUG_STACK) |
6399 | debug_stack_info (info); | |
9878760c RK |
6400 | |
6401 | /* Write .extern for any function we will call to save and restore fp | |
6402 | values. */ | |
b6c9286a | 6403 | if (info->first_fp_reg_save < 64 && !FP_SAVE_INLINE (info->first_fp_reg_save)) |
4d30c363 | 6404 | fprintf (file, "\t.extern %s%d%s\n\t.extern %s%d%s\n", |
4697a36c MM |
6405 | SAVE_FP_PREFIX, info->first_fp_reg_save - 32, SAVE_FP_SUFFIX, |
6406 | RESTORE_FP_PREFIX, info->first_fp_reg_save - 32, RESTORE_FP_SUFFIX); | |
9878760c | 6407 | |
c764f757 RK |
6408 | /* Write .extern for AIX common mode routines, if needed. */ |
6409 | if (! TARGET_POWER && ! TARGET_POWERPC && ! common_mode_defined) | |
6410 | { | |
f6709c70 JW |
6411 | fputs ("\t.extern __mulh\n", file); |
6412 | fputs ("\t.extern __mull\n", file); | |
6413 | fputs ("\t.extern __divss\n", file); | |
6414 | fputs ("\t.extern __divus\n", file); | |
6415 | fputs ("\t.extern __quoss\n", file); | |
6416 | fputs ("\t.extern __quous\n", file); | |
c764f757 RK |
6417 | common_mode_defined = 1; |
6418 | } | |
9878760c | 6419 | |
9ebbca7d | 6420 | if (! HAVE_prologue) |
979721f8 | 6421 | { |
9ebbca7d GK |
6422 | start_sequence (); |
6423 | ||
6424 | /* A NOTE_INSN_DELETED is supposed to be at the start | |
6425 | and end of the "toplevel" insn chain. */ | |
6426 | emit_note (0, NOTE_INSN_DELETED); | |
6427 | rs6000_emit_prologue (); | |
6428 | emit_note (0, NOTE_INSN_DELETED); | |
6429 | ||
6430 | if (TARGET_DEBUG_STACK) | |
6431 | debug_rtx_list (get_insns(), 100); | |
6432 | final (get_insns(), file, FALSE, FALSE); | |
6433 | end_sequence (); | |
979721f8 MM |
6434 | } |
6435 | ||
9ebbca7d GK |
6436 | rs6000_pic_labelno++; |
6437 | } | |
6438 | ||
6439 | /* Emit function epilogue as insns. | |
9878760c | 6440 | |
9ebbca7d GK |
6441 | At present, dwarf2out_frame_debug_expr doesn't understand |
6442 | register restores, so we don't bother setting RTX_FRAME_RELATED_P | |
6443 | anywhere in the epilogue. Most of the insns below would in any case | |
6444 | need special notes to explain where r11 is in relation to the stack. */ | |
9878760c | 6445 | |
9ebbca7d | 6446 | void |
83720594 | 6447 | rs6000_emit_epilogue (sibcall) |
9ebbca7d GK |
6448 | int sibcall; |
6449 | { | |
6450 | rs6000_stack_t *info; | |
6451 | int restoring_FPRs_inline; | |
6452 | int using_load_multiple; | |
6453 | int using_mfcr_multiple; | |
6454 | int use_backchain_to_restore_sp; | |
6455 | int sp_offset = 0; | |
6456 | rtx sp_reg_rtx = gen_rtx_REG (Pmode, 1); | |
6457 | rtx frame_reg_rtx = sp_reg_rtx; | |
6458 | enum machine_mode reg_mode = TARGET_POWERPC64 ? DImode : SImode; | |
6459 | int reg_size = TARGET_POWERPC64 ? 8 : 4; | |
6460 | int i; | |
6461 | ||
6462 | info = rs6000_stack_info (); | |
6463 | using_load_multiple = (TARGET_MULTIPLE && ! TARGET_POWERPC64 | |
6464 | && info->first_gp_reg_save < 31); | |
6465 | restoring_FPRs_inline = (sibcall | |
83720594 | 6466 | || current_function_calls_eh_return |
9ebbca7d GK |
6467 | || info->first_fp_reg_save == 64 |
6468 | || FP_SAVE_INLINE (info->first_fp_reg_save)); | |
6469 | use_backchain_to_restore_sp = (frame_pointer_needed | |
6470 | || current_function_calls_alloca | |
6471 | || info->total_size > 32767); | |
6472 | using_mfcr_multiple = (rs6000_cpu == PROCESSOR_PPC601 | |
6473 | || rs6000_cpu == PROCESSOR_PPC603 | |
6474 | || rs6000_cpu == PROCESSOR_PPC750 | |
6475 | || optimize_size); | |
6476 | ||
6477 | /* If we have a frame pointer, a call to alloca, or a large stack | |
6478 | frame, restore the old stack pointer using the backchain. Otherwise, | |
6479 | we know what size to update it with. */ | |
6480 | if (use_backchain_to_restore_sp) | |
bacbde18 | 6481 | { |
9ebbca7d GK |
6482 | /* Under V.4, don't reset the stack pointer until after we're done |
6483 | loading the saved registers. */ | |
6484 | if (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) | |
6485 | frame_reg_rtx = gen_rtx_REG (Pmode, 11); | |
4697a36c | 6486 | |
9ebbca7d GK |
6487 | emit_move_insn (frame_reg_rtx, |
6488 | gen_rtx_MEM (Pmode, sp_reg_rtx)); | |
6489 | ||
bacbde18 | 6490 | } |
9ebbca7d | 6491 | else if (info->push_p) |
85638c0d | 6492 | { |
9ebbca7d GK |
6493 | if (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) |
6494 | sp_offset = info->total_size; | |
6495 | else | |
6496 | { | |
6497 | emit_insn (TARGET_32BIT | |
6498 | ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx, | |
6499 | GEN_INT (info->total_size)) | |
6500 | : gen_adddi3 (sp_reg_rtx, sp_reg_rtx, | |
6501 | GEN_INT (info->total_size))); | |
6502 | } | |
85638c0d | 6503 | } |
9ebbca7d GK |
6504 | |
6505 | /* Get the old lr if we saved it. */ | |
6506 | if (info->lr_save_p) | |
b6c9286a | 6507 | { |
9ebbca7d GK |
6508 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, |
6509 | GEN_INT (info->lr_save_offset + sp_offset)); | |
6510 | rtx mem = gen_rtx_MEM (Pmode, addr); | |
ba4828e0 RK |
6511 | |
6512 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
b6c9286a | 6513 | |
9ebbca7d | 6514 | emit_move_insn (gen_rtx_REG (Pmode, 0), mem); |
b6c9286a | 6515 | } |
9ebbca7d GK |
6516 | |
6517 | /* Get the old cr if we saved it. */ | |
6518 | if (info->cr_save_p) | |
6519 | { | |
6520 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
6521 | GEN_INT (info->cr_save_offset + sp_offset)); | |
6522 | rtx mem = gen_rtx_MEM (SImode, addr); | |
ba4828e0 RK |
6523 | |
6524 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
b6c9286a | 6525 | |
9ebbca7d GK |
6526 | emit_move_insn (gen_rtx_REG (SImode, 12), mem); |
6527 | } | |
6528 | ||
6529 | /* Set LR here to try to overlap restores below. */ | |
4697a36c | 6530 | if (info->lr_save_p) |
9ebbca7d GK |
6531 | emit_move_insn (gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM), |
6532 | gen_rtx_REG (Pmode, 0)); | |
6533 | ||
83720594 RH |
6534 | /* Load exception handler data registers, if needed. */ |
6535 | if (current_function_calls_eh_return) | |
6536 | { | |
78e1b90d DE |
6537 | unsigned int i, regno; |
6538 | ||
83720594 RH |
6539 | for (i = 0; ; ++i) |
6540 | { | |
6541 | rtx addr, mem; | |
6542 | ||
6543 | regno = EH_RETURN_DATA_REGNO (i); | |
6544 | if (regno == INVALID_REGNUM) | |
6545 | break; | |
6546 | ||
6547 | addr = plus_constant (frame_reg_rtx, | |
78e1b90d DE |
6548 | info->ehrd_offset + sp_offset |
6549 | + reg_size * (int) i); | |
83720594 | 6550 | mem = gen_rtx_MEM (reg_mode, addr); |
ba4828e0 | 6551 | set_mem_alias_set (mem, rs6000_sr_alias_set); |
83720594 RH |
6552 | |
6553 | emit_move_insn (gen_rtx_REG (reg_mode, regno), mem); | |
6554 | } | |
6555 | } | |
9ebbca7d GK |
6556 | |
6557 | /* Restore GPRs. This is done as a PARALLEL if we are using | |
6558 | the load-multiple instructions. */ | |
6559 | if (using_load_multiple) | |
979721f8 | 6560 | { |
9ebbca7d GK |
6561 | rtvec p; |
6562 | p = rtvec_alloc (32 - info->first_gp_reg_save); | |
6563 | for (i = 0; i < 32 - info->first_gp_reg_save; i++) | |
979721f8 | 6564 | { |
9ebbca7d GK |
6565 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, |
6566 | GEN_INT (info->gp_save_offset | |
6567 | + sp_offset | |
6568 | + reg_size * i)); | |
6569 | rtx mem = gen_rtx_MEM (reg_mode, addr); | |
ba4828e0 RK |
6570 | |
6571 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
9ebbca7d GK |
6572 | |
6573 | RTVEC_ELT (p, i) = | |
6574 | gen_rtx_SET (VOIDmode, | |
6575 | gen_rtx_REG (reg_mode, info->first_gp_reg_save + i), | |
6576 | mem); | |
979721f8 | 6577 | } |
9ebbca7d | 6578 | emit_insn (gen_rtx_PARALLEL (VOIDmode, p)); |
979721f8 | 6579 | } |
9ebbca7d GK |
6580 | else |
6581 | for (i = 0; i < 32 - info->first_gp_reg_save; i++) | |
6582 | if ((regs_ever_live[info->first_gp_reg_save+i] | |
6583 | && ! call_used_regs[info->first_gp_reg_save+i]) | |
6584 | || (i+info->first_gp_reg_save == PIC_OFFSET_TABLE_REGNUM | |
ee890fe2 SS |
6585 | && (((DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) |
6586 | && flag_pic == 1) | |
6587 | || (DEFAULT_ABI == ABI_DARWIN | |
6588 | && flag_pic)))) | |
9ebbca7d GK |
6589 | { |
6590 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
6591 | GEN_INT (info->gp_save_offset | |
6592 | + sp_offset | |
6593 | + reg_size * i)); | |
6594 | rtx mem = gen_rtx_MEM (reg_mode, addr); | |
ba4828e0 RK |
6595 | |
6596 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
9ebbca7d GK |
6597 | |
6598 | emit_move_insn (gen_rtx_REG (reg_mode, | |
6599 | info->first_gp_reg_save + i), | |
6600 | mem); | |
6601 | } | |
9878760c | 6602 | |
9ebbca7d GK |
6603 | /* Restore fpr's if we need to do it without calling a function. */ |
6604 | if (restoring_FPRs_inline) | |
6605 | for (i = 0; i < 64 - info->first_fp_reg_save; i++) | |
6606 | if ((regs_ever_live[info->first_fp_reg_save+i] | |
6607 | && ! call_used_regs[info->first_fp_reg_save+i])) | |
6608 | { | |
6609 | rtx addr, mem; | |
6610 | addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
6611 | GEN_INT (info->fp_save_offset | |
6612 | + sp_offset | |
6613 | + 8*i)); | |
6614 | mem = gen_rtx_MEM (DFmode, addr); | |
ba4828e0 | 6615 | set_mem_alias_set (mem, rs6000_sr_alias_set); |
9ebbca7d GK |
6616 | |
6617 | emit_move_insn (gen_rtx_REG (DFmode, | |
6618 | info->first_fp_reg_save + i), | |
6619 | mem); | |
6620 | } | |
8d30c4ee | 6621 | |
9ebbca7d GK |
6622 | /* If we saved cr, restore it here. Just those that were used. */ |
6623 | if (info->cr_save_p) | |
979721f8 | 6624 | { |
9ebbca7d | 6625 | rtx r12_rtx = gen_rtx_REG (SImode, 12); |
e35b9579 | 6626 | int count = 0; |
9ebbca7d GK |
6627 | |
6628 | if (using_mfcr_multiple) | |
979721f8 | 6629 | { |
9ebbca7d GK |
6630 | for (i = 0; i < 8; i++) |
6631 | if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i]) | |
e35b9579 | 6632 | count++; |
9ebbca7d | 6633 | if (count == 0) |
e35b9579 GK |
6634 | abort (); |
6635 | } | |
6636 | ||
6637 | if (using_mfcr_multiple && count > 1) | |
6638 | { | |
6639 | rtvec p; | |
6640 | int ndx; | |
9ebbca7d | 6641 | |
e35b9579 | 6642 | p = rtvec_alloc (count); |
9ebbca7d | 6643 | |
e35b9579 | 6644 | ndx = 0; |
9ebbca7d GK |
6645 | for (i = 0; i < 8; i++) |
6646 | if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i]) | |
6647 | { | |
6648 | rtvec r = rtvec_alloc (2); | |
6649 | RTVEC_ELT (r, 0) = r12_rtx; | |
6650 | RTVEC_ELT (r, 1) = GEN_INT (1 << (7-i)); | |
e35b9579 | 6651 | RTVEC_ELT (p, ndx) = |
9ebbca7d GK |
6652 | gen_rtx_SET (VOIDmode, gen_rtx_REG (CCmode, CR0_REGNO+i), |
6653 | gen_rtx_UNSPEC (CCmode, r, 20)); | |
e35b9579 | 6654 | ndx++; |
9ebbca7d GK |
6655 | } |
6656 | emit_insn (gen_rtx_PARALLEL (VOIDmode, p)); | |
e35b9579 GK |
6657 | if (ndx != count) |
6658 | abort (); | |
979721f8 MM |
6659 | } |
6660 | else | |
9ebbca7d GK |
6661 | for (i = 0; i < 8; i++) |
6662 | if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i]) | |
979721f8 | 6663 | { |
9ebbca7d GK |
6664 | emit_insn (gen_movsi_to_cr_one (gen_rtx_REG (CCmode, |
6665 | CR0_REGNO+i), | |
6666 | r12_rtx)); | |
979721f8 | 6667 | } |
979721f8 MM |
6668 | } |
6669 | ||
9ebbca7d GK |
6670 | /* If this is V.4, unwind the stack pointer after all of the loads |
6671 | have been done. We need to emit a block here so that sched | |
6672 | doesn't decide to move the sp change before the register restores | |
6673 | (which may not have any obvious dependency on the stack). This | |
6674 | doesn't hurt performance, because there is no scheduling that can | |
6675 | be done after this point. */ | |
6676 | if (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) | |
b6c9286a | 6677 | { |
9ebbca7d GK |
6678 | if (frame_reg_rtx != sp_reg_rtx) |
6679 | rs6000_emit_stack_tie (); | |
b6c9286a | 6680 | |
9ebbca7d | 6681 | if (use_backchain_to_restore_sp) |
b6c9286a | 6682 | { |
9ebbca7d | 6683 | emit_move_insn (sp_reg_rtx, frame_reg_rtx); |
b6c9286a | 6684 | } |
9ebbca7d | 6685 | else if (sp_offset != 0) |
13f1623b | 6686 | { |
9ebbca7d GK |
6687 | emit_insn (Pmode == SImode |
6688 | ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx, | |
6689 | GEN_INT (sp_offset)) | |
6690 | : gen_adddi3 (sp_reg_rtx, sp_reg_rtx, | |
6691 | GEN_INT (sp_offset))); | |
13f1623b | 6692 | } |
9ebbca7d | 6693 | } |
b6c9286a | 6694 | |
83720594 RH |
6695 | if (current_function_calls_eh_return) |
6696 | { | |
6697 | rtx sa = EH_RETURN_STACKADJ_RTX; | |
6698 | emit_insn (Pmode == SImode | |
6699 | ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx, sa) | |
6700 | : gen_adddi3 (sp_reg_rtx, sp_reg_rtx, sa)); | |
6701 | } | |
6702 | ||
9ebbca7d GK |
6703 | if (!sibcall) |
6704 | { | |
6705 | rtvec p; | |
6706 | if (! restoring_FPRs_inline) | |
6707 | p = rtvec_alloc (3 + 64 - info->first_fp_reg_save); | |
6708 | else | |
6709 | p = rtvec_alloc (2); | |
b6c9286a | 6710 | |
e35b9579 GK |
6711 | RTVEC_ELT (p, 0) = gen_rtx_RETURN (VOIDmode); |
6712 | RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode, | |
9ebbca7d GK |
6713 | gen_rtx_REG (Pmode, |
6714 | LINK_REGISTER_REGNUM)); | |
9ebbca7d GK |
6715 | |
6716 | /* If we have to restore more than two FP registers, branch to the | |
6717 | restore function. It will return to our caller. */ | |
6718 | if (! restoring_FPRs_inline) | |
6719 | { | |
6720 | int i; | |
6721 | char rname[30]; | |
520a57c8 | 6722 | const char *alloc_rname; |
979721f8 | 6723 | |
9ebbca7d GK |
6724 | sprintf (rname, "%s%d%s", RESTORE_FP_PREFIX, |
6725 | info->first_fp_reg_save - 32, RESTORE_FP_SUFFIX); | |
a8a05998 | 6726 | alloc_rname = ggc_strdup (rname); |
9ebbca7d GK |
6727 | RTVEC_ELT (p, 2) = gen_rtx_USE (VOIDmode, |
6728 | gen_rtx_SYMBOL_REF (Pmode, | |
6729 | alloc_rname)); | |
b6c9286a | 6730 | |
9ebbca7d GK |
6731 | for (i = 0; i < 64 - info->first_fp_reg_save; i++) |
6732 | { | |
6733 | rtx addr, mem; | |
6734 | addr = gen_rtx_PLUS (Pmode, sp_reg_rtx, | |
6735 | GEN_INT (info->fp_save_offset + 8*i)); | |
6736 | mem = gen_rtx_MEM (DFmode, addr); | |
ba4828e0 | 6737 | set_mem_alias_set (mem, rs6000_sr_alias_set); |
9ebbca7d GK |
6738 | |
6739 | RTVEC_ELT (p, i+3) = | |
6740 | gen_rtx_SET (VOIDmode, | |
6741 | gen_rtx_REG (DFmode, info->first_fp_reg_save + i), | |
6742 | mem); | |
b6c9286a MM |
6743 | } |
6744 | } | |
9ebbca7d GK |
6745 | |
6746 | emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p)); | |
3daf36a4 | 6747 | } |
9878760c RK |
6748 | } |
6749 | ||
6750 | /* Write function epilogue. */ | |
6751 | ||
08c148a8 NB |
6752 | static void |
6753 | rs6000_output_function_epilogue (file, size) | |
9878760c | 6754 | FILE *file; |
08c148a8 | 6755 | HOST_WIDE_INT size ATTRIBUTE_UNUSED; |
9878760c | 6756 | { |
4697a36c | 6757 | rs6000_stack_t *info = rs6000_stack_info (); |
9878760c | 6758 | |
9ebbca7d | 6759 | if (! HAVE_epilogue) |
9878760c | 6760 | { |
9ebbca7d GK |
6761 | rtx insn = get_last_insn (); |
6762 | /* If the last insn was a BARRIER, we don't have to write anything except | |
6763 | the trace table. */ | |
6764 | if (GET_CODE (insn) == NOTE) | |
6765 | insn = prev_nonnote_insn (insn); | |
6766 | if (insn == 0 || GET_CODE (insn) != BARRIER) | |
4697a36c | 6767 | { |
9ebbca7d GK |
6768 | /* This is slightly ugly, but at least we don't have two |
6769 | copies of the epilogue-emitting code. */ | |
6770 | start_sequence (); | |
6771 | ||
6772 | /* A NOTE_INSN_DELETED is supposed to be at the start | |
6773 | and end of the "toplevel" insn chain. */ | |
6774 | emit_note (0, NOTE_INSN_DELETED); | |
6775 | rs6000_emit_epilogue (FALSE); | |
6776 | emit_note (0, NOTE_INSN_DELETED); | |
6777 | ||
6778 | if (TARGET_DEBUG_STACK) | |
6779 | debug_rtx_list (get_insns(), 100); | |
6780 | final (get_insns(), file, FALSE, FALSE); | |
6781 | end_sequence (); | |
4697a36c | 6782 | } |
9878760c | 6783 | } |
b4ac57ab | 6784 | |
9b30bae2 | 6785 | /* Output a traceback table here. See /usr/include/sys/debug.h for info |
314fc5a9 ILT |
6786 | on its format. |
6787 | ||
6788 | We don't output a traceback table if -finhibit-size-directive was | |
6789 | used. The documentation for -finhibit-size-directive reads | |
6790 | ``don't output a @code{.size} assembler directive, or anything | |
6791 | else that would cause trouble if the function is split in the | |
6792 | middle, and the two halves are placed at locations far apart in | |
6793 | memory.'' The traceback table has this property, since it | |
6794 | includes the offset from the start of the function to the | |
4d30c363 MM |
6795 | traceback table itself. |
6796 | ||
6797 | System V.4 Powerpc's (and the embedded ABI derived from it) use a | |
b6c9286a MM |
6798 | different traceback table. */ |
6799 | if (DEFAULT_ABI == ABI_AIX && ! flag_inhibit_size_directive) | |
9b30bae2 | 6800 | { |
3cce094d | 6801 | const char *fname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0); |
314fc5a9 ILT |
6802 | int fixed_parms, float_parms, parm_info; |
6803 | int i; | |
6804 | ||
b6c9286a MM |
6805 | while (*fname == '.') /* V.4 encodes . in the name */ |
6806 | fname++; | |
6807 | ||
314fc5a9 ILT |
6808 | /* Need label immediately before tbtab, so we can compute its offset |
6809 | from the function start. */ | |
6810 | if (*fname == '*') | |
6811 | ++fname; | |
6812 | ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT"); | |
6813 | ASM_OUTPUT_LABEL (file, fname); | |
6814 | ||
6815 | /* The .tbtab pseudo-op can only be used for the first eight | |
6816 | expressions, since it can't handle the possibly variable | |
6817 | length fields that follow. However, if you omit the optional | |
6818 | fields, the assembler outputs zeros for all optional fields | |
6819 | anyways, giving each variable length field is minimum length | |
6820 | (as defined in sys/debug.h). Thus we can not use the .tbtab | |
6821 | pseudo-op at all. */ | |
6822 | ||
6823 | /* An all-zero word flags the start of the tbtab, for debuggers | |
6824 | that have to find it by searching forward from the entry | |
6825 | point or from the current pc. */ | |
19d2d16f | 6826 | fputs ("\t.long 0\n", file); |
314fc5a9 ILT |
6827 | |
6828 | /* Tbtab format type. Use format type 0. */ | |
19d2d16f | 6829 | fputs ("\t.byte 0,", file); |
314fc5a9 ILT |
6830 | |
6831 | /* Language type. Unfortunately, there doesn't seem to be any | |
6832 | official way to get this info, so we use language_string. C | |
6833 | is 0. C++ is 9. No number defined for Obj-C, so use the | |
9517ead8 | 6834 | value for C for now. There is no official value for Java, |
6f573ff9 JL |
6835 | although IBM appears to be using 13. There is no official value |
6836 | for Chill, so we've choosen 44 pseudo-randomly. */ | |
314fc5a9 | 6837 | if (! strcmp (language_string, "GNU C") |
e2c953b6 | 6838 | || ! strcmp (language_string, "GNU Objective-C")) |
314fc5a9 ILT |
6839 | i = 0; |
6840 | else if (! strcmp (language_string, "GNU F77")) | |
6841 | i = 1; | |
6842 | else if (! strcmp (language_string, "GNU Ada")) | |
6843 | i = 3; | |
8b83775b | 6844 | else if (! strcmp (language_string, "GNU Pascal")) |
314fc5a9 ILT |
6845 | i = 2; |
6846 | else if (! strcmp (language_string, "GNU C++")) | |
6847 | i = 9; | |
9517ead8 AG |
6848 | else if (! strcmp (language_string, "GNU Java")) |
6849 | i = 13; | |
6f573ff9 JL |
6850 | else if (! strcmp (language_string, "GNU CHILL")) |
6851 | i = 44; | |
314fc5a9 ILT |
6852 | else |
6853 | abort (); | |
6854 | fprintf (file, "%d,", i); | |
6855 | ||
6856 | /* 8 single bit fields: global linkage (not set for C extern linkage, | |
6857 | apparently a PL/I convention?), out-of-line epilogue/prologue, offset | |
6858 | from start of procedure stored in tbtab, internal function, function | |
6859 | has controlled storage, function has no toc, function uses fp, | |
6860 | function logs/aborts fp operations. */ | |
6861 | /* Assume that fp operations are used if any fp reg must be saved. */ | |
4697a36c | 6862 | fprintf (file, "%d,", (1 << 5) | ((info->first_fp_reg_save != 64) << 1)); |
314fc5a9 ILT |
6863 | |
6864 | /* 6 bitfields: function is interrupt handler, name present in | |
6865 | proc table, function calls alloca, on condition directives | |
6866 | (controls stack walks, 3 bits), saves condition reg, saves | |
6867 | link reg. */ | |
6868 | /* The `function calls alloca' bit seems to be set whenever reg 31 is | |
6869 | set up as a frame pointer, even when there is no alloca call. */ | |
6870 | fprintf (file, "%d,", | |
6871 | ((1 << 6) | (frame_pointer_needed << 5) | |
4697a36c | 6872 | | (info->cr_save_p << 1) | (info->lr_save_p))); |
314fc5a9 ILT |
6873 | |
6874 | /* 3 bitfields: saves backchain, spare bit, number of fpr saved | |
6875 | (6 bits). */ | |
6876 | fprintf (file, "%d,", | |
4697a36c | 6877 | (info->push_p << 7) | (64 - info->first_fp_reg_save)); |
314fc5a9 ILT |
6878 | |
6879 | /* 2 bitfields: spare bits (2 bits), number of gpr saved (6 bits). */ | |
6880 | fprintf (file, "%d,", (32 - first_reg_to_save ())); | |
6881 | ||
6882 | { | |
6883 | /* Compute the parameter info from the function decl argument | |
6884 | list. */ | |
6885 | tree decl; | |
6886 | int next_parm_info_bit; | |
6887 | ||
6888 | next_parm_info_bit = 31; | |
6889 | parm_info = 0; | |
6890 | fixed_parms = 0; | |
6891 | float_parms = 0; | |
6892 | ||
6893 | for (decl = DECL_ARGUMENTS (current_function_decl); | |
6894 | decl; decl = TREE_CHAIN (decl)) | |
6895 | { | |
6896 | rtx parameter = DECL_INCOMING_RTL (decl); | |
6897 | enum machine_mode mode = GET_MODE (parameter); | |
6898 | ||
6899 | if (GET_CODE (parameter) == REG) | |
6900 | { | |
6901 | if (GET_MODE_CLASS (mode) == MODE_FLOAT) | |
6902 | { | |
6903 | int bits; | |
6904 | ||
6905 | float_parms++; | |
6906 | ||
6907 | if (mode == SFmode) | |
6908 | bits = 0x2; | |
6909 | else if (mode == DFmode) | |
6910 | bits = 0x3; | |
6911 | else | |
6912 | abort (); | |
6913 | ||
6914 | /* If only one bit will fit, don't or in this entry. */ | |
6915 | if (next_parm_info_bit > 0) | |
6916 | parm_info |= (bits << (next_parm_info_bit - 1)); | |
6917 | next_parm_info_bit -= 2; | |
6918 | } | |
6919 | else | |
6920 | { | |
6921 | fixed_parms += ((GET_MODE_SIZE (mode) | |
6922 | + (UNITS_PER_WORD - 1)) | |
6923 | / UNITS_PER_WORD); | |
6924 | next_parm_info_bit -= 1; | |
6925 | } | |
6926 | } | |
6927 | } | |
6928 | } | |
6929 | ||
6930 | /* Number of fixed point parameters. */ | |
6931 | /* This is actually the number of words of fixed point parameters; thus | |
6932 | an 8 byte struct counts as 2; and thus the maximum value is 8. */ | |
6933 | fprintf (file, "%d,", fixed_parms); | |
6934 | ||
6935 | /* 2 bitfields: number of floating point parameters (7 bits), parameters | |
6936 | all on stack. */ | |
6937 | /* This is actually the number of fp registers that hold parameters; | |
6938 | and thus the maximum value is 13. */ | |
6939 | /* Set parameters on stack bit if parameters are not in their original | |
6940 | registers, regardless of whether they are on the stack? Xlc | |
6941 | seems to set the bit when not optimizing. */ | |
6942 | fprintf (file, "%d\n", ((float_parms << 1) | (! optimize))); | |
6943 | ||
6944 | /* Optional fields follow. Some are variable length. */ | |
6945 | ||
6946 | /* Parameter types, left adjusted bit fields: 0 fixed, 10 single float, | |
6947 | 11 double float. */ | |
6948 | /* There is an entry for each parameter in a register, in the order that | |
6949 | they occur in the parameter list. Any intervening arguments on the | |
6950 | stack are ignored. If the list overflows a long (max possible length | |
6951 | 34 bits) then completely leave off all elements that don't fit. */ | |
6952 | /* Only emit this long if there was at least one parameter. */ | |
6953 | if (fixed_parms || float_parms) | |
6954 | fprintf (file, "\t.long %d\n", parm_info); | |
6955 | ||
6956 | /* Offset from start of code to tb table. */ | |
19d2d16f | 6957 | fputs ("\t.long ", file); |
314fc5a9 | 6958 | ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT"); |
9ebbca7d | 6959 | #if TARGET_AIX |
314fc5a9 | 6960 | RS6000_OUTPUT_BASENAME (file, fname); |
9ebbca7d GK |
6961 | #else |
6962 | assemble_name (file, fname); | |
6963 | #endif | |
19d2d16f | 6964 | fputs ("-.", file); |
9ebbca7d | 6965 | #if TARGET_AIX |
314fc5a9 | 6966 | RS6000_OUTPUT_BASENAME (file, fname); |
9ebbca7d GK |
6967 | #else |
6968 | assemble_name (file, fname); | |
6969 | #endif | |
19d2d16f | 6970 | putc ('\n', file); |
314fc5a9 ILT |
6971 | |
6972 | /* Interrupt handler mask. */ | |
6973 | /* Omit this long, since we never set the interrupt handler bit | |
6974 | above. */ | |
6975 | ||
6976 | /* Number of CTL (controlled storage) anchors. */ | |
6977 | /* Omit this long, since the has_ctl bit is never set above. */ | |
6978 | ||
6979 | /* Displacement into stack of each CTL anchor. */ | |
6980 | /* Omit this list of longs, because there are no CTL anchors. */ | |
6981 | ||
6982 | /* Length of function name. */ | |
296b8152 | 6983 | fprintf (file, "\t.short %d\n", (int) strlen (fname)); |
314fc5a9 ILT |
6984 | |
6985 | /* Function name. */ | |
6986 | assemble_string (fname, strlen (fname)); | |
6987 | ||
6988 | /* Register for alloca automatic storage; this is always reg 31. | |
6989 | Only emit this if the alloca bit was set above. */ | |
6990 | if (frame_pointer_needed) | |
19d2d16f | 6991 | fputs ("\t.byte 31\n", file); |
9b30bae2 | 6992 | } |
9878760c | 6993 | } |
17167fd8 MM |
6994 | \f |
6995 | /* A C compound statement that outputs the assembler code for a thunk function, | |
6996 | used to implement C++ virtual function calls with multiple inheritance. The | |
6997 | thunk acts as a wrapper around a virtual function, adjusting the implicit | |
6998 | object parameter before handing control off to the real function. | |
6999 | ||
7000 | First, emit code to add the integer DELTA to the location that contains the | |
7001 | incoming first argument. Assume that this argument contains a pointer, and | |
7002 | is the one used to pass the `this' pointer in C++. This is the incoming | |
7003 | argument *before* the function prologue, e.g. `%o0' on a sparc. The | |
7004 | addition must preserve the values of all other incoming arguments. | |
7005 | ||
7006 | After the addition, emit code to jump to FUNCTION, which is a | |
7007 | `FUNCTION_DECL'. This is a direct pure jump, not a call, and does not touch | |
7008 | the return address. Hence returning from FUNCTION will return to whoever | |
7009 | called the current `thunk'. | |
7010 | ||
7011 | The effect must be as if FUNCTION had been called directly with the adjusted | |
7012 | first argument. This macro is responsible for emitting all of the code for | |
08c148a8 NB |
7013 | a thunk function; output_function_prologue() and output_function_epilogue() |
7014 | are not invoked. | |
17167fd8 MM |
7015 | |
7016 | The THUNK_FNDECL is redundant. (DELTA and FUNCTION have already been | |
7017 | extracted from it.) It might possibly be useful on some targets, but | |
7018 | probably not. | |
7019 | ||
7020 | If you do not define this macro, the target-independent code in the C++ | |
7021 | frontend will generate a less efficient heavyweight thunk that calls | |
7022 | FUNCTION instead of jumping to it. The generic approach does not support | |
7023 | varargs. */ | |
7024 | ||
7025 | void | |
7026 | output_mi_thunk (file, thunk_fndecl, delta, function) | |
7027 | FILE *file; | |
d330fd93 | 7028 | tree thunk_fndecl ATTRIBUTE_UNUSED; |
17167fd8 MM |
7029 | int delta; |
7030 | tree function; | |
7031 | { | |
d330fd93 KG |
7032 | const char *this_reg = reg_names[ aggregate_value_p (TREE_TYPE (TREE_TYPE (function))) ? 4 : 3 ]; |
7033 | const char *prefix; | |
3cce094d | 7034 | const char *fname; |
d330fd93 | 7035 | const char *r0 = reg_names[0]; |
d330fd93 KG |
7036 | const char *toc = reg_names[2]; |
7037 | const char *schain = reg_names[11]; | |
7038 | const char *r12 = reg_names[12]; | |
17167fd8 MM |
7039 | char buf[512]; |
7040 | static int labelno = 0; | |
7041 | ||
7042 | /* Small constants that can be done by one add instruction */ | |
7043 | if (delta >= -32768 && delta <= 32767) | |
7044 | { | |
22b4a3b0 | 7045 | if (! TARGET_NEW_MNEMONICS) |
17167fd8 MM |
7046 | fprintf (file, "\tcal %s,%d(%s)\n", this_reg, delta, this_reg); |
7047 | else | |
7048 | fprintf (file, "\taddi %s,%s,%d\n", this_reg, this_reg, delta); | |
7049 | } | |
7050 | ||
7051 | /* Large constants that can be done by one addis instruction */ | |
7052 | else if ((delta & 0xffff) == 0 && num_insns_constant_wide (delta) == 1) | |
7053 | asm_fprintf (file, "\t{cau|addis} %s,%s,%d\n", this_reg, this_reg, | |
7054 | delta >> 16); | |
7055 | ||
7056 | /* 32-bit constants that can be done by an add and addis instruction. */ | |
7057 | else if (TARGET_32BIT || num_insns_constant_wide (delta) == 1) | |
7058 | { | |
22b4a3b0 | 7059 | /* Break into two pieces, propagating the sign bit from the low word to |
17167fd8 MM |
7060 | the upper word. */ |
7061 | int delta_high = delta >> 16; | |
7062 | int delta_low = delta & 0xffff; | |
7063 | if ((delta_low & 0x8000) != 0) | |
7064 | { | |
7065 | delta_high++; | |
7066 | delta_low = (delta_low ^ 0x8000) - 0x8000; /* sign extend */ | |
7067 | } | |
7068 | ||
7069 | asm_fprintf (file, "\t{cau|addis} %s,%s,%d\n", this_reg, this_reg, | |
7070 | delta_high); | |
7071 | ||
22b4a3b0 | 7072 | if (! TARGET_NEW_MNEMONICS) |
17167fd8 MM |
7073 | fprintf (file, "\tcal %s,%d(%s)\n", this_reg, delta_low, this_reg); |
7074 | else | |
7075 | fprintf (file, "\taddi %s,%s,%d\n", this_reg, this_reg, delta_low); | |
7076 | } | |
7077 | ||
7078 | /* 64-bit constants, fixme */ | |
7079 | else | |
7080 | abort (); | |
7081 | ||
7082 | /* Get the prefix in front of the names. */ | |
7083 | switch (DEFAULT_ABI) | |
7084 | { | |
7085 | default: | |
7086 | abort (); | |
7087 | ||
7088 | case ABI_AIX: | |
7089 | prefix = "."; | |
7090 | break; | |
7091 | ||
7092 | case ABI_V4: | |
7093 | case ABI_AIX_NODESC: | |
7094 | case ABI_SOLARIS: | |
7095 | prefix = ""; | |
7096 | break; | |
17167fd8 MM |
7097 | } |
7098 | ||
7099 | /* If the function is compiled in this module, jump to it directly. | |
7100 | Otherwise, load up its address and jump to it. */ | |
7101 | ||
7102 | fname = XSTR (XEXP (DECL_RTL (function), 0), 0); | |
42820a49 | 7103 | |
9ebbca7d | 7104 | if (current_file_function_operand (XEXP (DECL_RTL (function), 0), VOIDmode) |
22b4a3b0 FS |
7105 | && ! lookup_attribute ("longcall", |
7106 | TYPE_ATTRIBUTES (TREE_TYPE (function)))) | |
17167fd8 MM |
7107 | { |
7108 | fprintf (file, "\tb %s", prefix); | |
7109 | assemble_name (file, fname); | |
22b4a3b0 | 7110 | if (DEFAULT_ABI == ABI_V4 && flag_pic) fputs ("@local", file); |
949ea356 | 7111 | putc ('\n', file); |
17167fd8 MM |
7112 | } |
7113 | ||
7114 | else | |
7115 | { | |
7116 | switch (DEFAULT_ABI) | |
7117 | { | |
7118 | default: | |
17167fd8 MM |
7119 | abort (); |
7120 | ||
7121 | case ABI_AIX: | |
7122 | /* Set up a TOC entry for the function. */ | |
7123 | ASM_GENERATE_INTERNAL_LABEL (buf, "Lthunk", labelno); | |
7124 | toc_section (); | |
7125 | ASM_OUTPUT_INTERNAL_LABEL (file, "Lthunk", labelno); | |
7126 | labelno++; | |
7127 | ||
7128 | /* Note, MINIMAL_TOC doesn't make sense in the case of a thunk, since | |
7129 | there will be only one TOC entry for this function. */ | |
7130 | fputs ("\t.tc\t", file); | |
7131 | assemble_name (file, buf); | |
7132 | fputs ("[TC],", file); | |
7133 | assemble_name (file, buf); | |
7134 | putc ('\n', file); | |
7135 | text_section (); | |
7136 | asm_fprintf (file, (TARGET_32BIT) ? "\t{l|lwz} %s," : "\tld %s", r12); | |
7137 | assemble_name (file, buf); | |
7138 | asm_fprintf (file, "(%s)\n", reg_names[2]); | |
7139 | asm_fprintf (file, | |
7140 | (TARGET_32BIT) ? "\t{l|lwz} %s,0(%s)\n" : "\tld %s,0(%s)\n", | |
7141 | r0, r12); | |
7142 | ||
7143 | asm_fprintf (file, | |
7144 | (TARGET_32BIT) ? "\t{l|lwz} %s,4(%s)\n" : "\tld %s,8(%s)\n", | |
7145 | toc, r12); | |
7146 | ||
7147 | asm_fprintf (file, "\tmtctr %s\n", r0); | |
7148 | asm_fprintf (file, | |
7149 | (TARGET_32BIT) ? "\t{l|lwz} %s,8(%s)\n" : "\tld %s,16(%s)\n", | |
7150 | schain, r12); | |
7151 | ||
7152 | asm_fprintf (file, "\tbctr\n"); | |
7153 | break; | |
7154 | ||
9ebbca7d GK |
7155 | case ABI_AIX_NODESC: |
7156 | case ABI_SOLARIS: | |
17167fd8 | 7157 | case ABI_V4: |
22b4a3b0 FS |
7158 | fprintf (file, "\tb %s", prefix); |
7159 | assemble_name (file, fname); | |
7160 | if (flag_pic) fputs ("@plt", file); | |
949ea356 | 7161 | putc ('\n', file); |
22b4a3b0 | 7162 | break; |
ee890fe2 SS |
7163 | |
7164 | #if TARGET_MACHO | |
7165 | case ABI_DARWIN: | |
7166 | fprintf (file, "\tb %s", prefix); | |
7167 | if (flag_pic && !machopic_name_defined_p (fname)) | |
7168 | assemble_name (file, machopic_stub_name (fname)); | |
7169 | else | |
7170 | assemble_name (file, fname); | |
7171 | putc ('\n', file); | |
7172 | break; | |
7173 | #endif | |
9ebbca7d GK |
7174 | } |
7175 | } | |
7176 | } | |
42820a49 | 7177 | |
9ebbca7d GK |
7178 | \f |
7179 | /* A quick summary of the various types of 'constant-pool tables' | |
7180 | under PowerPC: | |
7181 | ||
7182 | Target Flags Name One table per | |
7183 | AIX (none) AIX TOC object file | |
7184 | AIX -mfull-toc AIX TOC object file | |
7185 | AIX -mminimal-toc AIX minimal TOC translation unit | |
7186 | SVR4/EABI (none) SVR4 SDATA object file | |
7187 | SVR4/EABI -fpic SVR4 pic object file | |
7188 | SVR4/EABI -fPIC SVR4 PIC translation unit | |
7189 | SVR4/EABI -mrelocatable EABI TOC function | |
7190 | SVR4/EABI -maix AIX TOC object file | |
7191 | SVR4/EABI -maix -mminimal-toc | |
7192 | AIX minimal TOC translation unit | |
7193 | ||
7194 | Name Reg. Set by entries contains: | |
7195 | made by addrs? fp? sum? | |
7196 | ||
7197 | AIX TOC 2 crt0 as Y option option | |
7198 | AIX minimal TOC 30 prolog gcc Y Y option | |
7199 | SVR4 SDATA 13 crt0 gcc N Y N | |
7200 | SVR4 pic 30 prolog ld Y not yet N | |
7201 | SVR4 PIC 30 prolog gcc Y option option | |
7202 | EABI TOC 30 prolog gcc Y option option | |
7203 | ||
7204 | */ | |
7205 | ||
7206 | /* Hash table stuff for keeping track of TOC entries. */ | |
7207 | ||
7208 | struct toc_hash_struct | |
7209 | { | |
7210 | /* `key' will satisfy CONSTANT_P; in fact, it will satisfy | |
7211 | ASM_OUTPUT_SPECIAL_POOL_ENTRY_P. */ | |
7212 | rtx key; | |
a9098fd0 | 7213 | enum machine_mode key_mode; |
9ebbca7d GK |
7214 | int labelno; |
7215 | }; | |
17167fd8 | 7216 | |
9ebbca7d GK |
7217 | static htab_t toc_hash_table; |
7218 | ||
7219 | /* Hash functions for the hash table. */ | |
7220 | ||
7221 | static unsigned | |
7222 | rs6000_hash_constant (k) | |
7223 | rtx k; | |
7224 | { | |
a9098fd0 | 7225 | unsigned result = (GET_CODE (k) << 3) ^ GET_MODE (k); |
9ebbca7d GK |
7226 | const char *format = GET_RTX_FORMAT (GET_CODE (k)); |
7227 | int flen = strlen (format); | |
7228 | int fidx; | |
7229 | ||
7230 | if (GET_CODE (k) == LABEL_REF) | |
832ea3b3 | 7231 | return result * 1231 + X0INT (XEXP (k, 0), 3); |
9ebbca7d GK |
7232 | |
7233 | if (GET_CODE (k) == CONST_DOUBLE) | |
7234 | fidx = 2; | |
7235 | else if (GET_CODE (k) == CODE_LABEL) | |
7236 | fidx = 3; | |
7237 | else | |
7238 | fidx = 0; | |
7239 | ||
7240 | for (; fidx < flen; fidx++) | |
7241 | switch (format[fidx]) | |
7242 | { | |
7243 | case 's': | |
7244 | { | |
7245 | unsigned i, len; | |
7246 | const char *str = XSTR (k, fidx); | |
7247 | len = strlen (str); | |
7248 | result = result * 613 + len; | |
7249 | for (i = 0; i < len; i++) | |
7250 | result = result * 613 + (unsigned) str[i]; | |
17167fd8 MM |
7251 | break; |
7252 | } | |
9ebbca7d GK |
7253 | case 'u': |
7254 | case 'e': | |
7255 | result = result * 1231 + rs6000_hash_constant (XEXP (k, fidx)); | |
7256 | break; | |
7257 | case 'i': | |
7258 | case 'n': | |
7259 | result = result * 613 + (unsigned) XINT (k, fidx); | |
7260 | break; | |
7261 | case 'w': | |
7262 | if (sizeof (unsigned) >= sizeof (HOST_WIDE_INT)) | |
7263 | result = result * 613 + (unsigned) XWINT (k, fidx); | |
7264 | else | |
7265 | { | |
7266 | size_t i; | |
7267 | for (i = 0; i < sizeof(HOST_WIDE_INT)/sizeof(unsigned); i++) | |
7268 | result = result * 613 + (unsigned) (XWINT (k, fidx) | |
7269 | >> CHAR_BIT * i); | |
7270 | } | |
7271 | break; | |
7272 | default: | |
7273 | abort(); | |
7274 | } | |
7275 | return result; | |
7276 | } | |
7277 | ||
7278 | static unsigned | |
7279 | toc_hash_function (hash_entry) | |
7280 | const void * hash_entry; | |
7281 | { | |
a9098fd0 GK |
7282 | const struct toc_hash_struct *thc = |
7283 | (const struct toc_hash_struct *) hash_entry; | |
7284 | return rs6000_hash_constant (thc->key) ^ thc->key_mode; | |
9ebbca7d GK |
7285 | } |
7286 | ||
7287 | /* Compare H1 and H2 for equivalence. */ | |
7288 | ||
7289 | static int | |
7290 | toc_hash_eq (h1, h2) | |
7291 | const void * h1; | |
7292 | const void * h2; | |
7293 | { | |
7294 | rtx r1 = ((const struct toc_hash_struct *) h1)->key; | |
7295 | rtx r2 = ((const struct toc_hash_struct *) h2)->key; | |
7296 | ||
a9098fd0 GK |
7297 | if (((const struct toc_hash_struct *) h1)->key_mode |
7298 | != ((const struct toc_hash_struct *) h2)->key_mode) | |
7299 | return 0; | |
7300 | ||
9ebbca7d GK |
7301 | /* Gotcha: One of these const_doubles will be in memory. |
7302 | The other may be on the constant-pool chain. | |
7303 | So rtx_equal_p will think they are different... */ | |
7304 | if (r1 == r2) | |
7305 | return 1; | |
7306 | if (GET_CODE (r1) != GET_CODE (r2) | |
7307 | || GET_MODE (r1) != GET_MODE (r2)) | |
7308 | return 0; | |
7309 | if (GET_CODE (r1) == CONST_DOUBLE) | |
7310 | { | |
7311 | int format_len = strlen (GET_RTX_FORMAT (CONST_DOUBLE)); | |
7312 | int i; | |
7313 | for (i = 2; i < format_len; i++) | |
7314 | if (XWINT (r1, i) != XWINT (r2, i)) | |
7315 | return 0; | |
7316 | ||
7317 | return 1; | |
17167fd8 | 7318 | } |
9ebbca7d | 7319 | else if (GET_CODE (r1) == LABEL_REF) |
e4a0656f GK |
7320 | return (CODE_LABEL_NUMBER (XEXP (r1, 0)) |
7321 | == CODE_LABEL_NUMBER (XEXP (r2, 0))); | |
9ebbca7d GK |
7322 | else |
7323 | return rtx_equal_p (r1, r2); | |
7324 | } | |
7325 | ||
7326 | /* Mark the hash table-entry HASH_ENTRY. */ | |
7327 | ||
7328 | static int | |
7329 | toc_hash_mark_entry (hash_slot, unused) | |
2eba1afa | 7330 | void ** hash_slot; |
9ebbca7d GK |
7331 | void * unused ATTRIBUTE_UNUSED; |
7332 | { | |
7333 | const struct toc_hash_struct * hash_entry = | |
7334 | *(const struct toc_hash_struct **) hash_slot; | |
7335 | rtx r = hash_entry->key; | |
7336 | ggc_set_mark (hash_entry); | |
7337 | /* For CODE_LABELS, we don't want to drag in the whole insn chain... */ | |
7338 | if (GET_CODE (r) == LABEL_REF) | |
7339 | { | |
7340 | ggc_set_mark (r); | |
7341 | ggc_set_mark (XEXP (r, 0)); | |
7342 | } | |
7343 | else | |
7344 | ggc_mark_rtx (r); | |
7345 | return 1; | |
7346 | } | |
7347 | ||
7348 | /* Mark all the elements of the TOC hash-table *HT. */ | |
7349 | ||
7350 | static void | |
7351 | toc_hash_mark_table (vht) | |
7352 | void *vht; | |
7353 | { | |
7354 | htab_t *ht = vht; | |
7355 | ||
7356 | htab_traverse (*ht, toc_hash_mark_entry, (void *)0); | |
17167fd8 MM |
7357 | } |
7358 | ||
28e510bd MM |
7359 | /* These are the names given by the C++ front-end to vtables, and |
7360 | vtable-like objects. Ideally, this logic should not be here; | |
7361 | instead, there should be some programmatic way of inquiring as | |
7362 | to whether or not an object is a vtable. */ | |
7363 | ||
7364 | #define VTABLE_NAME_P(NAME) \ | |
7365 | (strncmp ("_vt.", name, strlen("_vt.")) == 0 \ | |
7366 | || strncmp ("_ZTV", name, strlen ("_ZTV")) == 0 \ | |
7367 | || strncmp ("_ZTT", name, strlen ("_ZTT")) == 0 \ | |
7368 | || strncmp ("_ZTC", name, strlen ("_ZTC")) == 0) | |
7369 | ||
7370 | void | |
7371 | rs6000_output_symbol_ref (file, x) | |
7372 | FILE *file; | |
7373 | rtx x; | |
7374 | { | |
7375 | /* Currently C++ toc references to vtables can be emitted before it | |
7376 | is decided whether the vtable is public or private. If this is | |
7377 | the case, then the linker will eventually complain that there is | |
7378 | a reference to an unknown section. Thus, for vtables only, | |
7379 | we emit the TOC reference to reference the symbol and not the | |
7380 | section. */ | |
7381 | const char *name = XSTR (x, 0); | |
7382 | ||
7383 | if (VTABLE_NAME_P (name)) | |
7384 | { | |
7385 | RS6000_OUTPUT_BASENAME (file, name); | |
7386 | } | |
7387 | else | |
7388 | assemble_name (file, name); | |
7389 | } | |
7390 | ||
9878760c RK |
7391 | /* Output a TOC entry. We derive the entry name from what is |
7392 | being written. */ | |
7393 | ||
7394 | void | |
a9098fd0 | 7395 | output_toc (file, x, labelno, mode) |
9878760c RK |
7396 | FILE *file; |
7397 | rtx x; | |
7398 | int labelno; | |
a9098fd0 | 7399 | enum machine_mode mode; |
9878760c RK |
7400 | { |
7401 | char buf[256]; | |
3cce094d | 7402 | const char *name = buf; |
ec940faa | 7403 | const char *real_name; |
9878760c RK |
7404 | rtx base = x; |
7405 | int offset = 0; | |
7406 | ||
4697a36c MM |
7407 | if (TARGET_NO_TOC) |
7408 | abort (); | |
7409 | ||
9ebbca7d GK |
7410 | /* When the linker won't eliminate them, don't output duplicate |
7411 | TOC entries (this happens on AIX if there is any kind of TOC, | |
1f8f4a0b MM |
7412 | and on SVR4 under -fPIC or -mrelocatable). */ |
7413 | if (TARGET_TOC) | |
9ebbca7d GK |
7414 | { |
7415 | struct toc_hash_struct *h; | |
7416 | void * * found; | |
7417 | ||
7418 | h = ggc_alloc (sizeof (*h)); | |
7419 | h->key = x; | |
a9098fd0 | 7420 | h->key_mode = mode; |
9ebbca7d GK |
7421 | h->labelno = labelno; |
7422 | ||
7423 | found = htab_find_slot (toc_hash_table, h, 1); | |
7424 | if (*found == NULL) | |
7425 | *found = h; | |
7426 | else /* This is indeed a duplicate. | |
7427 | Set this label equal to that label. */ | |
7428 | { | |
7429 | fputs ("\t.set ", file); | |
7430 | ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC"); | |
7431 | fprintf (file, "%d,", labelno); | |
7432 | ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC"); | |
7433 | fprintf (file, "%d\n", ((*(const struct toc_hash_struct **) | |
7434 | found)->labelno)); | |
7435 | return; | |
7436 | } | |
7437 | } | |
7438 | ||
7439 | /* If we're going to put a double constant in the TOC, make sure it's | |
7440 | aligned properly when strict alignment is on. */ | |
ff1720ed RK |
7441 | if (GET_CODE (x) == CONST_DOUBLE |
7442 | && STRICT_ALIGNMENT | |
a9098fd0 | 7443 | && GET_MODE_BITSIZE (mode) >= 64 |
ff1720ed RK |
7444 | && ! (TARGET_NO_FP_IN_TOC && ! TARGET_MINIMAL_TOC)) { |
7445 | ASM_OUTPUT_ALIGN (file, 3); | |
7446 | } | |
7447 | ||
9ebbca7d | 7448 | ASM_OUTPUT_INTERNAL_LABEL (file, "LC", labelno); |
9878760c | 7449 | |
37c37a57 RK |
7450 | /* Handle FP constants specially. Note that if we have a minimal |
7451 | TOC, things we put here aren't actually in the TOC, so we can allow | |
7452 | FP constants. */ | |
a9098fd0 | 7453 | if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == DFmode) |
9878760c | 7454 | { |
042259f2 DE |
7455 | REAL_VALUE_TYPE rv; |
7456 | long k[2]; | |
0adc764e | 7457 | |
042259f2 DE |
7458 | REAL_VALUE_FROM_CONST_DOUBLE (rv, x); |
7459 | REAL_VALUE_TO_TARGET_DOUBLE (rv, k); | |
31bfaa0b | 7460 | |
13ded975 DE |
7461 | if (TARGET_64BIT) |
7462 | { | |
7463 | if (TARGET_MINIMAL_TOC) | |
2bfcf297 | 7464 | fputs (DOUBLE_INT_ASM_OP, file); |
13ded975 | 7465 | else |
2bfcf297 DB |
7466 | fprintf (file, "\t.tc FD_%lx_%lx[TC],", k[0], k[1]); |
7467 | fprintf (file, "0x%lx%08lx\n", k[0], k[1]); | |
13ded975 DE |
7468 | return; |
7469 | } | |
1875cc88 | 7470 | else |
13ded975 DE |
7471 | { |
7472 | if (TARGET_MINIMAL_TOC) | |
2bfcf297 | 7473 | fputs ("\t.long ", file); |
13ded975 | 7474 | else |
2bfcf297 DB |
7475 | fprintf (file, "\t.tc FD_%lx_%lx[TC],", k[0], k[1]); |
7476 | fprintf (file, "0x%lx,0x%lx\n", k[0], k[1]); | |
13ded975 DE |
7477 | return; |
7478 | } | |
9878760c | 7479 | } |
a9098fd0 | 7480 | else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == SFmode) |
9878760c | 7481 | { |
042259f2 DE |
7482 | REAL_VALUE_TYPE rv; |
7483 | long l; | |
9878760c | 7484 | |
042259f2 DE |
7485 | REAL_VALUE_FROM_CONST_DOUBLE (rv, x); |
7486 | REAL_VALUE_TO_TARGET_SINGLE (rv, l); | |
7487 | ||
31bfaa0b DE |
7488 | if (TARGET_64BIT) |
7489 | { | |
7490 | if (TARGET_MINIMAL_TOC) | |
2bfcf297 | 7491 | fputs (DOUBLE_INT_ASM_OP, file); |
31bfaa0b | 7492 | else |
2bfcf297 DB |
7493 | fprintf (file, "\t.tc FS_%lx[TC],", l); |
7494 | fprintf (file, "0x%lx00000000\n", l); | |
31bfaa0b DE |
7495 | return; |
7496 | } | |
042259f2 | 7497 | else |
31bfaa0b DE |
7498 | { |
7499 | if (TARGET_MINIMAL_TOC) | |
2bfcf297 | 7500 | fputs ("\t.long ", file); |
31bfaa0b | 7501 | else |
2bfcf297 DB |
7502 | fprintf (file, "\t.tc FS_%lx[TC],", l); |
7503 | fprintf (file, "0x%lx\n", l); | |
31bfaa0b DE |
7504 | return; |
7505 | } | |
042259f2 | 7506 | } |
f176e826 | 7507 | else if (GET_MODE (x) == VOIDmode |
a9098fd0 | 7508 | && (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE)) |
042259f2 | 7509 | { |
e2c953b6 | 7510 | unsigned HOST_WIDE_INT low; |
042259f2 DE |
7511 | HOST_WIDE_INT high; |
7512 | ||
7513 | if (GET_CODE (x) == CONST_DOUBLE) | |
7514 | { | |
7515 | low = CONST_DOUBLE_LOW (x); | |
7516 | high = CONST_DOUBLE_HIGH (x); | |
7517 | } | |
7518 | else | |
7519 | #if HOST_BITS_PER_WIDE_INT == 32 | |
7520 | { | |
7521 | low = INTVAL (x); | |
0858c623 | 7522 | high = (low & 0x80000000) ? ~0 : 0; |
042259f2 DE |
7523 | } |
7524 | #else | |
7525 | { | |
0858c623 | 7526 | low = INTVAL (x) & 0xffffffff; |
042259f2 DE |
7527 | high = (HOST_WIDE_INT) INTVAL (x) >> 32; |
7528 | } | |
7529 | #endif | |
9878760c | 7530 | |
a9098fd0 GK |
7531 | /* TOC entries are always Pmode-sized, but since this |
7532 | is a bigendian machine then if we're putting smaller | |
7533 | integer constants in the TOC we have to pad them. | |
7534 | (This is still a win over putting the constants in | |
7535 | a separate constant pool, because then we'd have | |
02a4ec28 FS |
7536 | to have both a TOC entry _and_ the actual constant.) |
7537 | ||
7538 | For a 32-bit target, CONST_INT values are loaded and shifted | |
7539 | entirely within `low' and can be stored in one TOC entry. */ | |
7540 | ||
7541 | if (TARGET_64BIT && POINTER_SIZE < GET_MODE_BITSIZE (mode)) | |
a9098fd0 | 7542 | abort ();/* It would be easy to make this work, but it doesn't now. */ |
02a4ec28 FS |
7543 | |
7544 | if (POINTER_SIZE > GET_MODE_BITSIZE (mode)) | |
a9098fd0 GK |
7545 | lshift_double (low, high, POINTER_SIZE - GET_MODE_BITSIZE (mode), |
7546 | POINTER_SIZE, &low, &high, 0); | |
7547 | ||
13ded975 DE |
7548 | if (TARGET_64BIT) |
7549 | { | |
7550 | if (TARGET_MINIMAL_TOC) | |
2bfcf297 | 7551 | fputs (DOUBLE_INT_ASM_OP, file); |
13ded975 | 7552 | else |
2bfcf297 DB |
7553 | fprintf (file, "\t.tc ID_%lx_%lx[TC],", (long)high, (long)low); |
7554 | fprintf (file, "0x%lx%08lx\n", (long) high, (long) low); | |
13ded975 DE |
7555 | return; |
7556 | } | |
1875cc88 | 7557 | else |
13ded975 | 7558 | { |
02a4ec28 FS |
7559 | if (POINTER_SIZE < GET_MODE_BITSIZE (mode)) |
7560 | { | |
7561 | if (TARGET_MINIMAL_TOC) | |
2bfcf297 | 7562 | fputs ("\t.long ", file); |
02a4ec28 | 7563 | else |
2bfcf297 DB |
7564 | fprintf (file, "\t.tc ID_%lx_%lx[TC],", |
7565 | (long)high, (long)low); | |
7566 | fprintf (file, "0x%lx,0x%lx\n", (long) high, (long) low); | |
02a4ec28 | 7567 | } |
13ded975 | 7568 | else |
02a4ec28 FS |
7569 | { |
7570 | if (TARGET_MINIMAL_TOC) | |
2bfcf297 | 7571 | fputs ("\t.long ", file); |
02a4ec28 | 7572 | else |
2bfcf297 DB |
7573 | fprintf (file, "\t.tc IS_%lx[TC],", (long) low); |
7574 | fprintf (file, "0x%lx\n", (long) low); | |
02a4ec28 | 7575 | } |
13ded975 DE |
7576 | return; |
7577 | } | |
9878760c RK |
7578 | } |
7579 | ||
7580 | if (GET_CODE (x) == CONST) | |
7581 | { | |
2bfcf297 DB |
7582 | if (GET_CODE (XEXP (x, 0)) != PLUS) |
7583 | abort (); | |
7584 | ||
9878760c RK |
7585 | base = XEXP (XEXP (x, 0), 0); |
7586 | offset = INTVAL (XEXP (XEXP (x, 0), 1)); | |
7587 | } | |
7588 | ||
7589 | if (GET_CODE (base) == SYMBOL_REF) | |
7590 | name = XSTR (base, 0); | |
7591 | else if (GET_CODE (base) == LABEL_REF) | |
7592 | ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (XEXP (base, 0))); | |
7593 | else if (GET_CODE (base) == CODE_LABEL) | |
7594 | ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (base)); | |
7595 | else | |
7596 | abort (); | |
7597 | ||
2e4eb9b0 | 7598 | STRIP_NAME_ENCODING (real_name, name); |
1875cc88 | 7599 | if (TARGET_MINIMAL_TOC) |
2bfcf297 | 7600 | fputs (TARGET_32BIT ? "\t.long " : DOUBLE_INT_ASM_OP, file); |
1875cc88 JW |
7601 | else |
7602 | { | |
b6c9286a | 7603 | fprintf (file, "\t.tc %s", real_name); |
9878760c | 7604 | |
1875cc88 JW |
7605 | if (offset < 0) |
7606 | fprintf (file, ".N%d", - offset); | |
7607 | else if (offset) | |
7608 | fprintf (file, ".P%d", offset); | |
9878760c | 7609 | |
19d2d16f | 7610 | fputs ("[TC],", file); |
1875cc88 | 7611 | } |
581bc4de MM |
7612 | |
7613 | /* Currently C++ toc references to vtables can be emitted before it | |
7614 | is decided whether the vtable is public or private. If this is | |
7615 | the case, then the linker will eventually complain that there is | |
7616 | a TOC reference to an unknown section. Thus, for vtables only, | |
7617 | we emit the TOC reference to reference the symbol and not the | |
7618 | section. */ | |
28e510bd | 7619 | if (VTABLE_NAME_P (name)) |
581bc4de | 7620 | { |
89c01f0e | 7621 | RS6000_OUTPUT_BASENAME (file, name); |
581bc4de MM |
7622 | if (offset < 0) |
7623 | fprintf (file, "%d", offset); | |
7624 | else if (offset > 0) | |
7625 | fprintf (file, "+%d", offset); | |
7626 | } | |
7627 | else | |
7628 | output_addr_const (file, x); | |
19d2d16f | 7629 | putc ('\n', file); |
9878760c RK |
7630 | } |
7631 | \f | |
7632 | /* Output an assembler pseudo-op to write an ASCII string of N characters | |
7633 | starting at P to FILE. | |
7634 | ||
7635 | On the RS/6000, we have to do this using the .byte operation and | |
7636 | write out special characters outside the quoted string. | |
7637 | Also, the assembler is broken; very long strings are truncated, | |
7638 | so we must artificially break them up early. */ | |
7639 | ||
7640 | void | |
7641 | output_ascii (file, p, n) | |
7642 | FILE *file; | |
d330fd93 | 7643 | const char *p; |
9878760c RK |
7644 | int n; |
7645 | { | |
7646 | char c; | |
7647 | int i, count_string; | |
d330fd93 KG |
7648 | const char *for_string = "\t.byte \""; |
7649 | const char *for_decimal = "\t.byte "; | |
7650 | const char *to_close = NULL; | |
9878760c RK |
7651 | |
7652 | count_string = 0; | |
7653 | for (i = 0; i < n; i++) | |
7654 | { | |
7655 | c = *p++; | |
7656 | if (c >= ' ' && c < 0177) | |
7657 | { | |
7658 | if (for_string) | |
7659 | fputs (for_string, file); | |
7660 | putc (c, file); | |
7661 | ||
7662 | /* Write two quotes to get one. */ | |
7663 | if (c == '"') | |
7664 | { | |
7665 | putc (c, file); | |
7666 | ++count_string; | |
7667 | } | |
7668 | ||
7669 | for_string = NULL; | |
7670 | for_decimal = "\"\n\t.byte "; | |
7671 | to_close = "\"\n"; | |
7672 | ++count_string; | |
7673 | ||
7674 | if (count_string >= 512) | |
7675 | { | |
7676 | fputs (to_close, file); | |
7677 | ||
7678 | for_string = "\t.byte \""; | |
7679 | for_decimal = "\t.byte "; | |
7680 | to_close = NULL; | |
7681 | count_string = 0; | |
7682 | } | |
7683 | } | |
7684 | else | |
7685 | { | |
7686 | if (for_decimal) | |
7687 | fputs (for_decimal, file); | |
7688 | fprintf (file, "%d", c); | |
7689 | ||
7690 | for_string = "\n\t.byte \""; | |
7691 | for_decimal = ", "; | |
7692 | to_close = "\n"; | |
7693 | count_string = 0; | |
7694 | } | |
7695 | } | |
7696 | ||
7697 | /* Now close the string if we have written one. Then end the line. */ | |
7698 | if (to_close) | |
9ebbca7d | 7699 | fputs (to_close, file); |
9878760c RK |
7700 | } |
7701 | \f | |
7702 | /* Generate a unique section name for FILENAME for a section type | |
7703 | represented by SECTION_DESC. Output goes into BUF. | |
7704 | ||
7705 | SECTION_DESC can be any string, as long as it is different for each | |
7706 | possible section type. | |
7707 | ||
7708 | We name the section in the same manner as xlc. The name begins with an | |
7709 | underscore followed by the filename (after stripping any leading directory | |
11e5fe42 RK |
7710 | names) with the last period replaced by the string SECTION_DESC. If |
7711 | FILENAME does not contain a period, SECTION_DESC is appended to the end of | |
7712 | the name. */ | |
9878760c RK |
7713 | |
7714 | void | |
7715 | rs6000_gen_section_name (buf, filename, section_desc) | |
7716 | char **buf; | |
9ebbca7d GK |
7717 | const char *filename; |
7718 | const char *section_desc; | |
9878760c | 7719 | { |
9ebbca7d | 7720 | const char *q, *after_last_slash, *last_period = 0; |
9878760c RK |
7721 | char *p; |
7722 | int len; | |
9878760c RK |
7723 | |
7724 | after_last_slash = filename; | |
7725 | for (q = filename; *q; q++) | |
11e5fe42 RK |
7726 | { |
7727 | if (*q == '/') | |
7728 | after_last_slash = q + 1; | |
7729 | else if (*q == '.') | |
7730 | last_period = q; | |
7731 | } | |
9878760c | 7732 | |
11e5fe42 | 7733 | len = strlen (after_last_slash) + strlen (section_desc) + 2; |
9878760c RK |
7734 | *buf = (char *) permalloc (len); |
7735 | ||
7736 | p = *buf; | |
7737 | *p++ = '_'; | |
7738 | ||
7739 | for (q = after_last_slash; *q; q++) | |
7740 | { | |
11e5fe42 | 7741 | if (q == last_period) |
9878760c RK |
7742 | { |
7743 | strcpy (p, section_desc); | |
7744 | p += strlen (section_desc); | |
9878760c RK |
7745 | } |
7746 | ||
e9a780ec | 7747 | else if (ISALNUM (*q)) |
9878760c RK |
7748 | *p++ = *q; |
7749 | } | |
7750 | ||
11e5fe42 | 7751 | if (last_period == 0) |
9878760c RK |
7752 | strcpy (p, section_desc); |
7753 | else | |
7754 | *p = '\0'; | |
7755 | } | |
e165f3f0 | 7756 | \f |
411707f4 CC |
7757 | |
7758 | /* Emit profile function. */ | |
7759 | void | |
7760 | output_profile_hook (labelno) | |
7761 | int labelno; | |
7762 | { | |
8480e480 CC |
7763 | if (DEFAULT_ABI == ABI_AIX) |
7764 | { | |
7765 | char buf[30]; | |
7766 | char *label_name; | |
7767 | rtx fun; | |
411707f4 | 7768 | |
8480e480 | 7769 | labelno += 1; |
411707f4 | 7770 | |
8480e480 CC |
7771 | ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno); |
7772 | STRIP_NAME_ENCODING (label_name, ggc_strdup (buf)); | |
7773 | fun = gen_rtx_SYMBOL_REF (Pmode, label_name); | |
411707f4 | 7774 | |
8480e480 CC |
7775 | emit_library_call (init_one_libfunc (RS6000_MCOUNT), 0, VOIDmode, 1, |
7776 | fun, Pmode); | |
7777 | } | |
ee890fe2 SS |
7778 | else if (DEFAULT_ABI == ABI_DARWIN) |
7779 | { | |
d5fa86ba | 7780 | const char *mcount_name = RS6000_MCOUNT; |
ee890fe2 SS |
7781 | int caller_addr_regno = LINK_REGISTER_REGNUM; |
7782 | ||
7783 | /* Be conservative and always set this, at least for now. */ | |
7784 | current_function_uses_pic_offset_table = 1; | |
7785 | ||
7786 | #if TARGET_MACHO | |
7787 | /* For PIC code, set up a stub and collect the caller's address | |
7788 | from r0, which is where the prologue puts it. */ | |
7789 | if (flag_pic) | |
7790 | { | |
7791 | mcount_name = machopic_stub_name (mcount_name); | |
7792 | if (current_function_uses_pic_offset_table) | |
7793 | caller_addr_regno = 0; | |
7794 | } | |
7795 | #endif | |
7796 | emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mcount_name), | |
7797 | 0, VOIDmode, 1, | |
7798 | gen_rtx_REG (Pmode, caller_addr_regno), Pmode); | |
7799 | } | |
411707f4 CC |
7800 | } |
7801 | ||
e165f3f0 RK |
7802 | /* Write function profiler code. */ |
7803 | ||
7804 | void | |
7805 | output_function_profiler (file, labelno) | |
7806 | FILE *file; | |
7807 | int labelno; | |
7808 | { | |
3daf36a4 | 7809 | char buf[100]; |
e165f3f0 | 7810 | |
3daf36a4 | 7811 | ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno); |
38c1f2d7 | 7812 | switch (DEFAULT_ABI) |
3daf36a4 | 7813 | { |
38c1f2d7 MM |
7814 | default: |
7815 | abort (); | |
7816 | ||
7817 | case ABI_V4: | |
7818 | case ABI_SOLARIS: | |
7819 | case ABI_AIX_NODESC: | |
7820 | fprintf (file, "\tmflr %s\n", reg_names[0]); | |
7821 | if (flag_pic == 1) | |
7822 | { | |
dfdfa60f DE |
7823 | fputs ("\tbl _GLOBAL_OFFSET_TABLE_@local-4\n", file); |
7824 | asm_fprintf (file, "\t{st|stw} %s,4(%s)\n", | |
7825 | reg_names[0], reg_names[1]); | |
17167fd8 | 7826 | asm_fprintf (file, "\tmflr %s\n", reg_names[12]); |
dfdfa60f | 7827 | asm_fprintf (file, "\t{l|lwz} %s,", reg_names[0]); |
38c1f2d7 | 7828 | assemble_name (file, buf); |
17167fd8 | 7829 | asm_fprintf (file, "@got(%s)\n", reg_names[12]); |
38c1f2d7 | 7830 | } |
9ebbca7d | 7831 | else if (flag_pic > 1) |
38c1f2d7 | 7832 | { |
dfdfa60f DE |
7833 | asm_fprintf (file, "\t{st|stw} %s,4(%s)\n", |
7834 | reg_names[0], reg_names[1]); | |
9ebbca7d GK |
7835 | /* Now, we need to get the address of the label. */ |
7836 | fputs ("\tbl 1f\n\t.long ", file); | |
034e84c4 | 7837 | assemble_name (file, buf); |
9ebbca7d GK |
7838 | fputs ("-.\n1:", file); |
7839 | asm_fprintf (file, "\tmflr %s\n", reg_names[11]); | |
7840 | asm_fprintf (file, "\t{l|lwz} %s,0(%s)\n", | |
7841 | reg_names[0], reg_names[11]); | |
7842 | asm_fprintf (file, "\t{cax|add} %s,%s,%s\n", | |
7843 | reg_names[0], reg_names[0], reg_names[11]); | |
38c1f2d7 | 7844 | } |
38c1f2d7 MM |
7845 | else |
7846 | { | |
17167fd8 | 7847 | asm_fprintf (file, "\t{liu|lis} %s,", reg_names[12]); |
38c1f2d7 | 7848 | assemble_name (file, buf); |
dfdfa60f | 7849 | fputs ("@ha\n", file); |
b5253831 DE |
7850 | asm_fprintf (file, "\t{st|stw} %s,4(%s)\n", |
7851 | reg_names[0], reg_names[1]); | |
a260abc9 | 7852 | asm_fprintf (file, "\t{cal|la} %s,", reg_names[0]); |
38c1f2d7 | 7853 | assemble_name (file, buf); |
17167fd8 | 7854 | asm_fprintf (file, "@l(%s)\n", reg_names[12]); |
38c1f2d7 MM |
7855 | } |
7856 | ||
b5253831 DE |
7857 | if (current_function_needs_context) |
7858 | asm_fprintf (file, "\tmr %s,%s\n", | |
7859 | reg_names[30], reg_names[STATIC_CHAIN_REGNUM]); | |
38c1f2d7 | 7860 | fprintf (file, "\tbl %s\n", RS6000_MCOUNT); |
b5253831 DE |
7861 | if (current_function_needs_context) |
7862 | asm_fprintf (file, "\tmr %s,%s\n", | |
7863 | reg_names[STATIC_CHAIN_REGNUM], reg_names[30]); | |
38c1f2d7 MM |
7864 | break; |
7865 | ||
7866 | case ABI_AIX: | |
ee890fe2 | 7867 | case ABI_DARWIN: |
411707f4 | 7868 | /* Don't do anything, done in output_profile_hook (). */ |
38c1f2d7 | 7869 | break; |
411707f4 | 7870 | |
38c1f2d7 | 7871 | } |
e165f3f0 | 7872 | } |
a251ffd0 TG |
7873 | |
7874 | /* Adjust the cost of a scheduling dependency. Return the new cost of | |
7875 | a dependency LINK or INSN on DEP_INSN. COST is the current cost. */ | |
7876 | ||
7877 | int | |
a06faf84 | 7878 | rs6000_adjust_cost (insn, link, dep_insn, cost) |
a251ffd0 TG |
7879 | rtx insn; |
7880 | rtx link; | |
296b8152 | 7881 | rtx dep_insn ATTRIBUTE_UNUSED; |
a251ffd0 TG |
7882 | int cost; |
7883 | { | |
7884 | if (! recog_memoized (insn)) | |
7885 | return 0; | |
7886 | ||
7887 | if (REG_NOTE_KIND (link) != 0) | |
7888 | return 0; | |
7889 | ||
7890 | if (REG_NOTE_KIND (link) == 0) | |
7891 | { | |
7892 | /* Data dependency; DEP_INSN writes a register that INSN reads some | |
7893 | cycles later. */ | |
7894 | ||
7895 | /* Tell the first scheduling pass about the latency between a mtctr | |
7896 | and bctr (and mtlr and br/blr). The first scheduling pass will not | |
7897 | know about this latency since the mtctr instruction, which has the | |
7898 | latency associated to it, will be generated by reload. */ | |
7899 | if (get_attr_type (insn) == TYPE_JMPREG) | |
7900 | return TARGET_POWER ? 5 : 4; | |
7901 | ||
7902 | /* Fall out to return default cost. */ | |
7903 | } | |
7904 | ||
7905 | return cost; | |
7906 | } | |
b6c9286a | 7907 | |
bef84347 VM |
7908 | /* A C statement (sans semicolon) to update the integer scheduling priority |
7909 | INSN_PRIORITY (INSN). Reduce the priority to execute the INSN earlier, | |
7910 | increase the priority to execute INSN later. Do not define this macro if | |
7911 | you do not need to adjust the scheduling priorities of insns. */ | |
7912 | ||
7913 | int | |
7914 | rs6000_adjust_priority (insn, priority) | |
d330fd93 | 7915 | rtx insn ATTRIBUTE_UNUSED; |
bef84347 VM |
7916 | int priority; |
7917 | { | |
7918 | /* On machines (like the 750) which have asymetric integer units, where one | |
7919 | integer unit can do multiply and divides and the other can't, reduce the | |
7920 | priority of multiply/divide so it is scheduled before other integer | |
7921 | operationss. */ | |
7922 | ||
7923 | #if 0 | |
2c3c49de | 7924 | if (! INSN_P (insn)) |
bef84347 VM |
7925 | return priority; |
7926 | ||
7927 | if (GET_CODE (PATTERN (insn)) == USE) | |
7928 | return priority; | |
7929 | ||
7930 | switch (rs6000_cpu_attr) { | |
7931 | case CPU_PPC750: | |
7932 | switch (get_attr_type (insn)) | |
7933 | { | |
7934 | default: | |
7935 | break; | |
7936 | ||
7937 | case TYPE_IMUL: | |
7938 | case TYPE_IDIV: | |
3cb999d8 DE |
7939 | fprintf (stderr, "priority was %#x (%d) before adjustment\n", |
7940 | priority, priority); | |
bef84347 VM |
7941 | if (priority >= 0 && priority < 0x01000000) |
7942 | priority >>= 3; | |
7943 | break; | |
7944 | } | |
7945 | } | |
7946 | #endif | |
7947 | ||
7948 | return priority; | |
7949 | } | |
7950 | ||
b6c9286a MM |
7951 | /* Return how many instructions the machine can issue per cycle */ |
7952 | int get_issue_rate() | |
7953 | { | |
7954 | switch (rs6000_cpu_attr) { | |
3cb999d8 DE |
7955 | case CPU_RIOS1: /* ? */ |
7956 | case CPU_RS64A: | |
7957 | case CPU_PPC601: /* ? */ | |
7958 | return 3; | |
b6c9286a | 7959 | case CPU_PPC603: |
bef84347 VM |
7960 | case CPU_PPC750: |
7961 | return 2; | |
3cb999d8 | 7962 | case CPU_RIOS2: |
b6c9286a | 7963 | case CPU_PPC604: |
19684119 | 7964 | case CPU_PPC604E: |
b6c9286a | 7965 | case CPU_PPC620: |
3cb999d8 | 7966 | case CPU_PPC630: |
b6c9286a MM |
7967 | return 4; |
7968 | default: | |
7969 | return 1; | |
7970 | } | |
7971 | } | |
7972 | ||
b6c9286a | 7973 | \f |
b6c9286a MM |
7974 | /* Length in units of the trampoline for entering a nested function. */ |
7975 | ||
7976 | int | |
7977 | rs6000_trampoline_size () | |
7978 | { | |
7979 | int ret = 0; | |
7980 | ||
7981 | switch (DEFAULT_ABI) | |
7982 | { | |
7983 | default: | |
7984 | abort (); | |
7985 | ||
7986 | case ABI_AIX: | |
8f802bfb | 7987 | ret = (TARGET_32BIT) ? 12 : 24; |
b6c9286a MM |
7988 | break; |
7989 | ||
7990 | case ABI_V4: | |
c81bebd7 | 7991 | case ABI_SOLARIS: |
b6c9286a | 7992 | case ABI_AIX_NODESC: |
03a7e1a5 | 7993 | ret = (TARGET_32BIT) ? 40 : 48; |
b6c9286a | 7994 | break; |
b6c9286a MM |
7995 | } |
7996 | ||
7997 | return ret; | |
7998 | } | |
7999 | ||
8000 | /* Emit RTL insns to initialize the variable parts of a trampoline. | |
8001 | FNADDR is an RTX for the address of the function's pure code. | |
8002 | CXT is an RTX for the static chain value for the function. */ | |
8003 | ||
8004 | void | |
8005 | rs6000_initialize_trampoline (addr, fnaddr, cxt) | |
8006 | rtx addr; | |
8007 | rtx fnaddr; | |
8008 | rtx cxt; | |
8009 | { | |
ac2a93a1 | 8010 | enum machine_mode pmode = Pmode; |
8bd04c56 MM |
8011 | int regsize = (TARGET_32BIT) ? 4 : 8; |
8012 | rtx ctx_reg = force_reg (pmode, cxt); | |
b6c9286a MM |
8013 | |
8014 | switch (DEFAULT_ABI) | |
8015 | { | |
8016 | default: | |
8017 | abort (); | |
8018 | ||
8bd04c56 | 8019 | /* Macros to shorten the code expansions below. */ |
39403d82 | 8020 | #define MEM_DEREF(addr) gen_rtx_MEM (pmode, memory_address (pmode, addr)) |
c5c76735 JL |
8021 | #define MEM_PLUS(addr,offset) \ |
8022 | gen_rtx_MEM (pmode, memory_address (pmode, plus_constant (addr, offset))) | |
7c59dc5d | 8023 | |
b6c9286a MM |
8024 | /* Under AIX, just build the 3 word function descriptor */ |
8025 | case ABI_AIX: | |
8bd04c56 MM |
8026 | { |
8027 | rtx fn_reg = gen_reg_rtx (pmode); | |
8028 | rtx toc_reg = gen_reg_rtx (pmode); | |
8029 | emit_move_insn (fn_reg, MEM_DEREF (fnaddr)); | |
8030 | emit_move_insn (toc_reg, MEM_PLUS (fnaddr, 4)); | |
8031 | emit_move_insn (MEM_DEREF (addr), fn_reg); | |
8032 | emit_move_insn (MEM_PLUS (addr, regsize), toc_reg); | |
8033 | emit_move_insn (MEM_PLUS (addr, 2*regsize), ctx_reg); | |
8034 | } | |
b6c9286a MM |
8035 | break; |
8036 | ||
eaf1bcf1 | 8037 | /* Under V.4/eabi, call __trampoline_setup to do the real work. */ |
b6c9286a | 8038 | case ABI_V4: |
c81bebd7 | 8039 | case ABI_SOLARIS: |
b6c9286a | 8040 | case ABI_AIX_NODESC: |
39403d82 | 8041 | emit_library_call (gen_rtx_SYMBOL_REF (SImode, "__trampoline_setup"), |
eaf1bcf1 MM |
8042 | FALSE, VOIDmode, 4, |
8043 | addr, pmode, | |
8044 | GEN_INT (rs6000_trampoline_size ()), SImode, | |
8045 | fnaddr, pmode, | |
8046 | ctx_reg, pmode); | |
b6c9286a | 8047 | break; |
b6c9286a MM |
8048 | } |
8049 | ||
8050 | return; | |
8051 | } | |
7509c759 MM |
8052 | |
8053 | \f | |
7509c759 MM |
8054 | /* If defined, a C expression whose value is nonzero if IDENTIFIER |
8055 | with arguments ARGS is a valid machine specific attribute for TYPE. | |
8056 | The attributes in ATTRIBUTES have previously been assigned to TYPE. */ | |
8057 | ||
672a6f42 | 8058 | static int |
7509c759 MM |
8059 | rs6000_valid_type_attribute_p (type, attributes, identifier, args) |
8060 | tree type; | |
296b8152 | 8061 | tree attributes ATTRIBUTE_UNUSED; |
7509c759 MM |
8062 | tree identifier; |
8063 | tree args; | |
8064 | { | |
8065 | if (TREE_CODE (type) != FUNCTION_TYPE | |
8066 | && TREE_CODE (type) != FIELD_DECL | |
8067 | && TREE_CODE (type) != TYPE_DECL) | |
8068 | return 0; | |
8069 | ||
6a4cee5f MM |
8070 | /* Longcall attribute says that the function is not within 2**26 bytes |
8071 | of the current function, and to do an indirect call. */ | |
8072 | if (is_attribute_p ("longcall", identifier)) | |
8073 | return (args == NULL_TREE); | |
8074 | ||
7509c759 MM |
8075 | return 0; |
8076 | } | |
8077 | ||
3cb999d8 DE |
8078 | /* Return a reference suitable for calling a function with the |
8079 | longcall attribute. */ | |
6a4cee5f MM |
8080 | struct rtx_def * |
8081 | rs6000_longcall_ref (call_ref) | |
8082 | rtx call_ref; | |
8083 | { | |
d330fd93 | 8084 | const char *call_name; |
6a4cee5f MM |
8085 | tree node; |
8086 | ||
8087 | if (GET_CODE (call_ref) != SYMBOL_REF) | |
8088 | return call_ref; | |
8089 | ||
8090 | /* System V adds '.' to the internal name, so skip them. */ | |
8091 | call_name = XSTR (call_ref, 0); | |
8092 | if (*call_name == '.') | |
8093 | { | |
8094 | while (*call_name == '.') | |
8095 | call_name++; | |
8096 | ||
8097 | node = get_identifier (call_name); | |
39403d82 | 8098 | call_ref = gen_rtx_SYMBOL_REF (VOIDmode, IDENTIFIER_POINTER (node)); |
6a4cee5f MM |
8099 | } |
8100 | ||
8101 | return force_reg (Pmode, call_ref); | |
8102 | } | |
8103 | ||
7509c759 MM |
8104 | \f |
8105 | /* A C statement or statements to switch to the appropriate section | |
8106 | for output of RTX in mode MODE. You can assume that RTX is some | |
8107 | kind of constant in RTL. The argument MODE is redundant except in | |
8108 | the case of a `const_int' rtx. Select the section by calling | |
8109 | `text_section' or one of the alternatives for other sections. | |
8110 | ||
8111 | Do not define this macro if you put all constants in the read-only | |
8112 | data section. */ | |
8113 | ||
8114 | #ifdef USING_SVR4_H | |
8115 | ||
8116 | void | |
8117 | rs6000_select_rtx_section (mode, x) | |
a9098fd0 | 8118 | enum machine_mode mode; |
7509c759 MM |
8119 | rtx x; |
8120 | { | |
a9098fd0 | 8121 | if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode)) |
7509c759 | 8122 | toc_section (); |
7509c759 MM |
8123 | else |
8124 | const_section (); | |
8125 | } | |
8126 | ||
8127 | /* A C statement or statements to switch to the appropriate | |
8128 | section for output of DECL. DECL is either a `VAR_DECL' node | |
8129 | or a constant of some sort. RELOC indicates whether forming | |
8130 | the initial value of DECL requires link-time relocations. */ | |
8131 | ||
8132 | void | |
8133 | rs6000_select_section (decl, reloc) | |
8134 | tree decl; | |
8135 | int reloc; | |
8136 | { | |
8137 | int size = int_size_in_bytes (TREE_TYPE (decl)); | |
63019373 GK |
8138 | int needs_sdata; |
8139 | int readonly; | |
8140 | static void (* const sec_funcs[4]) PARAMS ((void)) = { | |
8141 | &const_section, | |
8142 | &sdata2_section, | |
8143 | &data_section, | |
8144 | &sdata_section | |
8145 | }; | |
8146 | ||
8147 | needs_sdata = (size > 0 | |
8148 | && size <= g_switch_value | |
8149 | && rs6000_sdata != SDATA_NONE | |
8150 | && (rs6000_sdata != SDATA_DATA || TREE_PUBLIC (decl))); | |
7509c759 MM |
8151 | |
8152 | if (TREE_CODE (decl) == STRING_CST) | |
63019373 | 8153 | readonly = ! flag_writable_strings; |
a9098fd0 | 8154 | else if (TREE_CODE (decl) == VAR_DECL) |
63019373 GK |
8155 | readonly = (! (flag_pic && reloc) |
8156 | && TREE_READONLY (decl) | |
8157 | && ! TREE_SIDE_EFFECTS (decl) | |
8158 | && DECL_INITIAL (decl) | |
8159 | && DECL_INITIAL (decl) != error_mark_node | |
8160 | && TREE_CONSTANT (DECL_INITIAL (decl))); | |
7509c759 | 8161 | else |
63019373 GK |
8162 | readonly = 1; |
8163 | if (needs_sdata && rs6000_sdata != SDATA_EABI) | |
8164 | readonly = 0; | |
8165 | ||
8166 | (*sec_funcs[(readonly ? 0 : 2) + (needs_sdata ? 1 : 0)])(); | |
8167 | } | |
8168 | ||
8169 | /* A C statement to build up a unique section name, expressed as a | |
8170 | STRING_CST node, and assign it to DECL_SECTION_NAME (decl). | |
8171 | RELOC indicates whether the initial value of EXP requires | |
8172 | link-time relocations. If you do not define this macro, GCC will use | |
8173 | the symbol name prefixed by `.' as the section name. Note - this | |
8174 | macro can now be called for unitialised data items as well as | |
8175 | initialised data and functions. */ | |
8176 | ||
8177 | void | |
8178 | rs6000_unique_section (decl, reloc) | |
8179 | tree decl; | |
8180 | int reloc; | |
8181 | { | |
8182 | int size = int_size_in_bytes (TREE_TYPE (decl)); | |
8183 | int needs_sdata; | |
8184 | int readonly; | |
8185 | int len; | |
8186 | int sec; | |
8187 | const char *name; | |
8188 | char *string; | |
8189 | const char *prefix; | |
8190 | ||
8191 | static const char *const prefixes[7][2] = | |
8192 | { | |
8193 | { ".text.", ".gnu.linkonce.t." }, | |
8194 | { ".rodata.", ".gnu.linkonce.r." }, | |
8195 | { ".sdata2.", ".gnu.linkonce.s2." }, | |
8196 | { ".data.", ".gnu.linkonce.d." }, | |
8197 | { ".sdata.", ".gnu.linkonce.s." }, | |
8198 | { ".bss.", ".gnu.linkonce.b." }, | |
8199 | { ".sbss.", ".gnu.linkonce.sb." } | |
8200 | }; | |
8201 | ||
8202 | needs_sdata = (TREE_CODE (decl) != FUNCTION_DECL | |
8203 | && size > 0 | |
8204 | && size <= g_switch_value | |
8205 | && rs6000_sdata != SDATA_NONE | |
8206 | && (rs6000_sdata != SDATA_DATA || TREE_PUBLIC (decl))); | |
8207 | ||
8208 | if (TREE_CODE (decl) == STRING_CST) | |
8209 | readonly = ! flag_writable_strings; | |
8210 | else if (TREE_CODE (decl) == VAR_DECL) | |
8211 | readonly = (! (flag_pic && reloc) | |
8212 | && TREE_READONLY (decl) | |
8213 | && ! TREE_SIDE_EFFECTS (decl) | |
8214 | && DECL_INITIAL (decl) | |
8215 | && DECL_INITIAL (decl) != error_mark_node | |
8216 | && TREE_CONSTANT (DECL_INITIAL (decl))); | |
8217 | else | |
8218 | readonly = 1; | |
8219 | if (needs_sdata && rs6000_sdata != SDATA_EABI) | |
8220 | readonly = 0; | |
8221 | ||
8222 | sec = ((TREE_CODE (decl) == FUNCTION_DECL ? 0 : 1) | |
8223 | + (readonly ? 0 : 2) | |
8224 | + (needs_sdata ? 1 : 0) | |
8225 | + (DECL_INITIAL (decl) == 0 | |
8226 | || DECL_INITIAL (decl) == error_mark_node) ? 4 : 0); | |
8227 | ||
e6978109 | 8228 | STRIP_NAME_ENCODING (name, IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl))); |
63019373 GK |
8229 | prefix = prefixes[sec][DECL_ONE_ONLY (decl)]; |
8230 | len = strlen (name) + strlen (prefix); | |
8231 | string = alloca (len + 1); | |
8232 | ||
8233 | sprintf (string, "%s%s", prefix, name); | |
8234 | ||
8235 | DECL_SECTION_NAME (decl) = build_string (len, string); | |
7509c759 | 8236 | } |
d9407988 MM |
8237 | |
8238 | \f | |
d9407988 MM |
8239 | /* If we are referencing a function that is static or is known to be |
8240 | in this file, make the SYMBOL_REF special. We can use this to indicate | |
8241 | that we can branch to this function without emitting a no-op after the | |
9ebbca7d | 8242 | call. For real AIX calling sequences, we also replace the |
d9407988 MM |
8243 | function name with the real name (1 or 2 leading .'s), rather than |
8244 | the function descriptor name. This saves a lot of overriding code | |
a260abc9 | 8245 | to read the prefixes. */ |
d9407988 MM |
8246 | |
8247 | void | |
8248 | rs6000_encode_section_info (decl) | |
8249 | tree decl; | |
8250 | { | |
8251 | if (TREE_CODE (decl) == FUNCTION_DECL) | |
8252 | { | |
8253 | rtx sym_ref = XEXP (DECL_RTL (decl), 0); | |
8f1b829e | 8254 | if ((TREE_ASM_WRITTEN (decl) || ! TREE_PUBLIC (decl)) |
c81fc13e | 8255 | && ! DECL_WEAK (decl)) |
d9407988 MM |
8256 | SYMBOL_REF_FLAG (sym_ref) = 1; |
8257 | ||
9ebbca7d | 8258 | if (DEFAULT_ABI == ABI_AIX) |
d9407988 | 8259 | { |
ff669a6c RH |
8260 | size_t len1 = (DEFAULT_ABI == ABI_AIX) ? 1 : 2; |
8261 | size_t len2 = strlen (XSTR (sym_ref, 0)); | |
520a57c8 | 8262 | char *str = alloca (len1 + len2 + 1); |
ff669a6c RH |
8263 | str[0] = '.'; |
8264 | str[1] = '.'; | |
8265 | memcpy (str + len1, XSTR (sym_ref, 0), len2 + 1); | |
8266 | ||
520a57c8 | 8267 | XSTR (sym_ref, 0) = ggc_alloc_string (str, len1 + len2); |
d9407988 MM |
8268 | } |
8269 | } | |
8270 | else if (rs6000_sdata != SDATA_NONE | |
8271 | && (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) | |
8272 | && TREE_CODE (decl) == VAR_DECL) | |
8273 | { | |
8274 | int size = int_size_in_bytes (TREE_TYPE (decl)); | |
8275 | tree section_name = DECL_SECTION_NAME (decl); | |
d330fd93 | 8276 | const char *name = (char *)0; |
d9407988 MM |
8277 | int len = 0; |
8278 | ||
8279 | if (section_name) | |
8280 | { | |
8281 | if (TREE_CODE (section_name) == STRING_CST) | |
8282 | { | |
8283 | name = TREE_STRING_POINTER (section_name); | |
8284 | len = TREE_STRING_LENGTH (section_name); | |
8285 | } | |
8286 | else | |
8287 | abort (); | |
8288 | } | |
8289 | ||
8290 | if ((size > 0 && size <= g_switch_value) | |
8291 | || (name | |
5f59ecb7 | 8292 | && ((len == sizeof (".sdata") - 1 |
3cb999d8 | 8293 | && strcmp (name, ".sdata") == 0) |
5f59ecb7 | 8294 | || (len == sizeof (".sdata2") - 1 |
3cb999d8 | 8295 | && strcmp (name, ".sdata2") == 0) |
5f59ecb7 | 8296 | || (len == sizeof (".sbss") - 1 |
3cb999d8 | 8297 | && strcmp (name, ".sbss") == 0) |
5f59ecb7 | 8298 | || (len == sizeof (".sbss2") - 1 |
3cb999d8 | 8299 | && strcmp (name, ".sbss2") == 0) |
5f59ecb7 | 8300 | || (len == sizeof (".PPC.EMB.sdata0") - 1 |
3cb999d8 | 8301 | && strcmp (name, ".PPC.EMB.sdata0") == 0) |
5f59ecb7 | 8302 | || (len == sizeof (".PPC.EMB.sbss0") - 1 |
3cb999d8 | 8303 | && strcmp (name, ".PPC.EMB.sbss0") == 0)))) |
d9407988 MM |
8304 | { |
8305 | rtx sym_ref = XEXP (DECL_RTL (decl), 0); | |
ff669a6c | 8306 | size_t len = strlen (XSTR (sym_ref, 0)); |
88c1e412 | 8307 | char *str = alloca (len + 2); |
ff669a6c | 8308 | |
ff669a6c RH |
8309 | str[0] = '@'; |
8310 | memcpy (str + 1, XSTR (sym_ref, 0), len + 1); | |
88c1e412 | 8311 | XSTR (sym_ref, 0) = ggc_alloc_string (str, len + 1); |
d9407988 MM |
8312 | } |
8313 | } | |
8314 | } | |
8315 | ||
7509c759 | 8316 | #endif /* USING_SVR4_H */ |
000034eb | 8317 | |
a6c2a102 | 8318 | \f |
000034eb | 8319 | /* Return a REG that occurs in ADDR with coefficient 1. |
02441cd6 JL |
8320 | ADDR can be effectively incremented by incrementing REG. |
8321 | ||
8322 | r0 is special and we must not select it as an address | |
8323 | register by this routine since our caller will try to | |
8324 | increment the returned register via an "la" instruction. */ | |
000034eb DE |
8325 | |
8326 | struct rtx_def * | |
8327 | find_addr_reg (addr) | |
8328 | rtx addr; | |
8329 | { | |
8330 | while (GET_CODE (addr) == PLUS) | |
8331 | { | |
02441cd6 JL |
8332 | if (GET_CODE (XEXP (addr, 0)) == REG |
8333 | && REGNO (XEXP (addr, 0)) != 0) | |
000034eb | 8334 | addr = XEXP (addr, 0); |
02441cd6 JL |
8335 | else if (GET_CODE (XEXP (addr, 1)) == REG |
8336 | && REGNO (XEXP (addr, 1)) != 0) | |
000034eb DE |
8337 | addr = XEXP (addr, 1); |
8338 | else if (CONSTANT_P (XEXP (addr, 0))) | |
8339 | addr = XEXP (addr, 1); | |
8340 | else if (CONSTANT_P (XEXP (addr, 1))) | |
8341 | addr = XEXP (addr, 0); | |
8342 | else | |
8343 | abort (); | |
8344 | } | |
02441cd6 | 8345 | if (GET_CODE (addr) == REG && REGNO (addr) != 0) |
000034eb DE |
8346 | return addr; |
8347 | abort (); | |
8348 | } | |
8349 | ||
a6c2a102 DE |
8350 | void |
8351 | rs6000_fatal_bad_address (op) | |
8352 | rtx op; | |
8353 | { | |
8354 | fatal_insn ("bad address", op); | |
8355 | } | |
c8023011 MM |
8356 | |
8357 | /* Called to register all of our global variables with the garbage | |
8358 | collector. */ | |
8359 | ||
8360 | static void | |
8361 | rs6000_add_gc_roots () | |
8362 | { | |
8363 | ggc_add_rtx_root (&rs6000_compare_op0, 1); | |
8364 | ggc_add_rtx_root (&rs6000_compare_op1, 1); | |
9ebbca7d GK |
8365 | |
8366 | toc_hash_table = htab_create (1021, toc_hash_function, toc_hash_eq, NULL); | |
8367 | ggc_add_root (&toc_hash_table, 1, sizeof (toc_hash_table), | |
8368 | toc_hash_mark_table); | |
ee890fe2 SS |
8369 | |
8370 | #if TARGET_MACHO | |
8371 | machopic_add_gc_roots (); | |
8372 | #endif | |
8373 | } | |
8374 | ||
8375 | #if TARGET_MACHO | |
8376 | ||
8377 | #if 0 | |
8378 | /* Returns 1 if OP is either a symbol reference or a sum of a symbol | |
8379 | reference and a constant. */ | |
8380 | ||
8381 | int | |
8382 | symbolic_operand (op) | |
8383 | register rtx op; | |
8384 | { | |
8385 | switch (GET_CODE (op)) | |
8386 | { | |
8387 | case SYMBOL_REF: | |
8388 | case LABEL_REF: | |
8389 | return 1; | |
8390 | case CONST: | |
8391 | op = XEXP (op, 0); | |
8392 | return (GET_CODE (op) == SYMBOL_REF || | |
8393 | (GET_CODE (XEXP (op, 0)) == SYMBOL_REF | |
8394 | || GET_CODE (XEXP (op, 0)) == LABEL_REF) | |
8395 | && GET_CODE (XEXP (op, 1)) == CONST_INT); | |
8396 | default: | |
8397 | return 0; | |
8398 | } | |
c8023011 | 8399 | } |
ee890fe2 SS |
8400 | #endif |
8401 | ||
8402 | #ifdef RS6000_LONG_BRANCH | |
8403 | ||
8404 | static tree stub_list = 0; | |
8405 | ||
8406 | /* ADD_COMPILER_STUB adds the compiler generated stub for handling | |
8407 | procedure calls to the linked list. */ | |
8408 | ||
8409 | void | |
8410 | add_compiler_stub (label_name, function_name, line_number) | |
8411 | tree label_name; | |
8412 | tree function_name; | |
8413 | int line_number; | |
8414 | { | |
8415 | tree stub = build_tree_list (function_name, label_name); | |
8416 | TREE_TYPE (stub) = build_int_2 (line_number, 0); | |
8417 | TREE_CHAIN (stub) = stub_list; | |
8418 | stub_list = stub; | |
8419 | } | |
8420 | ||
8421 | #define STUB_LABEL_NAME(STUB) TREE_VALUE (STUB) | |
8422 | #define STUB_FUNCTION_NAME(STUB) TREE_PURPOSE (STUB) | |
8423 | #define STUB_LINE_NUMBER(STUB) TREE_INT_CST_LOW (TREE_TYPE (STUB)) | |
8424 | ||
8425 | /* OUTPUT_COMPILER_STUB outputs the compiler generated stub for handling | |
8426 | procedure calls from the linked list and initializes the linked list. */ | |
8427 | ||
8428 | void output_compiler_stub () | |
8429 | { | |
8430 | char tmp_buf[256]; | |
8431 | char label_buf[256]; | |
8432 | char *label; | |
8433 | tree tmp_stub, stub; | |
8434 | ||
8435 | if (!flag_pic) | |
8436 | for (stub = stub_list; stub; stub = TREE_CHAIN (stub)) | |
8437 | { | |
8438 | fprintf (asm_out_file, | |
8439 | "%s:\n", IDENTIFIER_POINTER(STUB_LABEL_NAME(stub))); | |
8440 | ||
8441 | #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO) | |
8442 | if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG) | |
8443 | fprintf (asm_out_file, "\t.stabd 68,0,%d\n", STUB_LINE_NUMBER(stub)); | |
8444 | #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */ | |
8445 | ||
8446 | if (IDENTIFIER_POINTER (STUB_FUNCTION_NAME (stub))[0] == '*') | |
8447 | strcpy (label_buf, | |
8448 | IDENTIFIER_POINTER (STUB_FUNCTION_NAME (stub))+1); | |
8449 | else | |
8450 | { | |
8451 | label_buf[0] = '_'; | |
8452 | strcpy (label_buf+1, | |
8453 | IDENTIFIER_POINTER (STUB_FUNCTION_NAME (stub))); | |
8454 | } | |
8455 | ||
8456 | strcpy (tmp_buf, "lis r12,hi16("); | |
8457 | strcat (tmp_buf, label_buf); | |
8458 | strcat (tmp_buf, ")\n\tori r12,r12,lo16("); | |
8459 | strcat (tmp_buf, label_buf); | |
8460 | strcat (tmp_buf, ")\n\tmtctr r12\n\tbctr"); | |
8461 | output_asm_insn (tmp_buf, 0); | |
8462 | ||
8463 | #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO) | |
8464 | if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG) | |
8465 | fprintf(asm_out_file, "\t.stabd 68,0,%d\n", STUB_LINE_NUMBER (stub)); | |
8466 | #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */ | |
8467 | } | |
8468 | ||
8469 | stub_list = 0; | |
8470 | } | |
8471 | ||
8472 | /* NO_PREVIOUS_DEF checks in the link list whether the function name is | |
8473 | already there or not. */ | |
8474 | ||
8475 | int no_previous_def (function_name) | |
8476 | tree function_name; | |
8477 | { | |
8478 | tree stub; | |
8479 | for (stub = stub_list; stub; stub = TREE_CHAIN (stub)) | |
8480 | if (function_name == STUB_FUNCTION_NAME (stub)) | |
8481 | return 0; | |
8482 | return 1; | |
8483 | } | |
8484 | ||
8485 | /* GET_PREV_LABEL gets the label name from the previous definition of | |
8486 | the function. */ | |
8487 | ||
8488 | tree get_prev_label (function_name) | |
8489 | tree function_name; | |
8490 | { | |
8491 | tree stub; | |
8492 | for (stub = stub_list; stub; stub = TREE_CHAIN (stub)) | |
8493 | if (function_name == STUB_FUNCTION_NAME (stub)) | |
8494 | return STUB_LABEL_NAME (stub); | |
8495 | return 0; | |
8496 | } | |
8497 | ||
8498 | /* INSN is either a function call or a millicode call. It may have an | |
8499 | unconditional jump in its delay slot. | |
8500 | ||
8501 | CALL_DEST is the routine we are calling. */ | |
8502 | ||
8503 | char * | |
8504 | output_call (insn, call_dest, operand_number) | |
8505 | rtx insn; | |
8506 | rtx call_dest; | |
8507 | int operand_number; | |
8508 | { | |
8509 | static char buf[256]; | |
8510 | if (GET_CODE (call_dest) == SYMBOL_REF && TARGET_LONG_BRANCH && !flag_pic) | |
8511 | { | |
8512 | tree labelname; | |
8513 | tree funname = get_identifier (XSTR (call_dest, 0)); | |
8514 | ||
8515 | if (no_previous_def (funname)) | |
8516 | { | |
8517 | int line_number; | |
8518 | rtx label_rtx = gen_label_rtx (); | |
8519 | char *label_buf, temp_buf[256]; | |
8520 | ASM_GENERATE_INTERNAL_LABEL (temp_buf, "L", | |
8521 | CODE_LABEL_NUMBER (label_rtx)); | |
8522 | label_buf = temp_buf[0] == '*' ? temp_buf + 1 : temp_buf; | |
8523 | labelname = get_identifier (label_buf); | |
8524 | for (; insn && GET_CODE (insn) != NOTE; insn = PREV_INSN (insn)); | |
8525 | if (insn) | |
8526 | line_number = NOTE_LINE_NUMBER (insn); | |
8527 | add_compiler_stub (labelname, funname, line_number); | |
8528 | } | |
8529 | else | |
8530 | labelname = get_prev_label (funname); | |
8531 | ||
8532 | sprintf (buf, "jbsr %%z%d,%.246s", | |
8533 | operand_number, IDENTIFIER_POINTER (labelname)); | |
8534 | return buf; | |
8535 | } | |
8536 | else | |
8537 | { | |
8538 | sprintf (buf, "bl %%z%d", operand_number); | |
8539 | return buf; | |
8540 | } | |
8541 | } | |
8542 | ||
8543 | #endif /* RS6000_LONG_BRANCH */ | |
8544 | ||
8545 | #define GEN_LOCAL_LABEL_FOR_SYMBOL(BUF,SYMBOL,LENGTH,N) \ | |
8546 | do { \ | |
8547 | const char *symbol_ = (SYMBOL); \ | |
8548 | char *buffer_ = (BUF); \ | |
8549 | if (symbol_[0] == '"') \ | |
8550 | { \ | |
8551 | sprintf(buffer_, "\"L%d$%s", (N), symbol_+1); \ | |
8552 | } \ | |
8553 | else if (name_needs_quotes(symbol_)) \ | |
8554 | { \ | |
8555 | sprintf(buffer_, "\"L%d$%s\"", (N), symbol_); \ | |
8556 | } \ | |
8557 | else \ | |
8558 | { \ | |
8559 | sprintf(buffer_, "L%d$%s", (N), symbol_); \ | |
8560 | } \ | |
8561 | } while (0) | |
8562 | ||
8563 | ||
8564 | /* Generate PIC and indirect symbol stubs. */ | |
8565 | ||
8566 | void | |
8567 | machopic_output_stub (file, symb, stub) | |
8568 | FILE *file; | |
8569 | const char *symb, *stub; | |
8570 | { | |
8571 | unsigned int length; | |
8572 | char *binder_name, *symbol_name, *lazy_ptr_name; | |
8573 | char *local_label_0, *local_label_1, *local_label_2; | |
8574 | static int label = 0; | |
8575 | ||
df56a27f SS |
8576 | /* Lose our funky encoding stuff so it doesn't contaminate the stub. */ |
8577 | STRIP_NAME_ENCODING (symb, symb); | |
8578 | ||
ee890fe2 SS |
8579 | label += 1; |
8580 | ||
8581 | length = strlen (stub); | |
8582 | binder_name = alloca (length + 32); | |
8583 | GEN_BINDER_NAME_FOR_STUB (binder_name, stub, length); | |
8584 | ||
8585 | length = strlen (symb); | |
8586 | symbol_name = alloca (length + 32); | |
8587 | GEN_SYMBOL_NAME_FOR_SYMBOL (symbol_name, symb, length); | |
8588 | ||
8589 | lazy_ptr_name = alloca (length + 32); | |
8590 | GEN_LAZY_PTR_NAME_FOR_SYMBOL (lazy_ptr_name, symb, length); | |
8591 | ||
8592 | local_label_0 = alloca (length + 32); | |
8593 | GEN_LOCAL_LABEL_FOR_SYMBOL (local_label_0, symb, length, 0); | |
8594 | ||
8595 | local_label_1 = alloca (length + 32); | |
8596 | GEN_LOCAL_LABEL_FOR_SYMBOL (local_label_1, symb, length, 1); | |
8597 | ||
8598 | local_label_2 = alloca (length + 32); | |
8599 | GEN_LOCAL_LABEL_FOR_SYMBOL (local_label_2, symb, length, 2); | |
8600 | ||
8601 | if (flag_pic == 2) | |
8602 | machopic_picsymbol_stub_section (); | |
8603 | else | |
8604 | machopic_symbol_stub_section (); | |
8605 | ||
8606 | fprintf (file, "%s:\n", stub); | |
8607 | fprintf (file, "\t.indirect_symbol %s\n", symbol_name); | |
8608 | ||
8609 | if (flag_pic == 2) | |
8610 | { | |
8611 | fprintf (file, "\tmflr r0\n"); | |
8612 | fprintf (file, "\tbcl 20,31,%s\n", local_label_0); | |
8613 | fprintf (file, "%s:\n\tmflr r11\n", local_label_0); | |
8614 | fprintf (file, "\taddis r11,r11,ha16(%s-%s)\n", | |
8615 | lazy_ptr_name, local_label_0); | |
8616 | fprintf (file, "\tmtlr r0\n"); | |
8617 | fprintf (file, "\tlwz r12,lo16(%s-%s)(r11)\n", | |
8618 | lazy_ptr_name, local_label_0); | |
8619 | fprintf (file, "\tmtctr r12\n"); | |
8620 | fprintf (file, "\taddi r11,r11,lo16(%s-%s)\n", | |
8621 | lazy_ptr_name, local_label_0); | |
8622 | fprintf (file, "\tbctr\n"); | |
8623 | } | |
8624 | else | |
8625 | fprintf (file, "non-pure not supported\n"); | |
8626 | ||
8627 | machopic_lazy_symbol_ptr_section (); | |
8628 | fprintf (file, "%s:\n", lazy_ptr_name); | |
8629 | fprintf (file, "\t.indirect_symbol %s\n", symbol_name); | |
8630 | fprintf (file, "\t.long dyld_stub_binding_helper\n"); | |
8631 | } | |
8632 | ||
8633 | /* Legitimize PIC addresses. If the address is already | |
8634 | position-independent, we return ORIG. Newly generated | |
8635 | position-independent addresses go into a reg. This is REG if non | |
8636 | zero, otherwise we allocate register(s) as necessary. */ | |
8637 | ||
8638 | #define SMALL_INT(X) ((unsigned) (INTVAL(X) + 0x4000) < 0x8000) | |
8639 | ||
8640 | rtx | |
8641 | rs6000_machopic_legitimize_pic_address (orig, mode, reg) | |
8642 | rtx orig; | |
8643 | enum machine_mode mode; | |
8644 | rtx reg; | |
8645 | { | |
8646 | rtx base, offset; | |
8647 | ||
8648 | if (reg == NULL && ! reload_in_progress && ! reload_completed) | |
8649 | reg = gen_reg_rtx (Pmode); | |
8650 | ||
8651 | if (GET_CODE (orig) == CONST) | |
8652 | { | |
8653 | if (GET_CODE (XEXP (orig, 0)) == PLUS | |
8654 | && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx) | |
8655 | return orig; | |
8656 | ||
8657 | if (GET_CODE (XEXP (orig, 0)) == PLUS) | |
8658 | { | |
8659 | base = rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 0), | |
8660 | Pmode, reg); | |
8661 | offset = rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 1), | |
8662 | Pmode, reg); | |
8663 | } | |
8664 | else | |
8665 | abort (); | |
8666 | ||
8667 | if (GET_CODE (offset) == CONST_INT) | |
8668 | { | |
8669 | if (SMALL_INT (offset)) | |
ed8908e7 | 8670 | return plus_constant (base, INTVAL (offset)); |
ee890fe2 SS |
8671 | else if (! reload_in_progress && ! reload_completed) |
8672 | offset = force_reg (Pmode, offset); | |
8673 | else | |
8674 | abort (); | |
8675 | } | |
8676 | return gen_rtx (PLUS, Pmode, base, offset); | |
8677 | } | |
8678 | ||
8679 | /* Fall back on generic machopic code. */ | |
8680 | return machopic_legitimize_pic_address (orig, mode, reg); | |
8681 | } | |
8682 | ||
8683 | /* This is just a placeholder to make linking work without having to | |
8684 | add this to the generic Darwin EXTRA_SECTIONS. If -mcall-aix is | |
8685 | ever needed for Darwin (not too likely!) this would have to get a | |
8686 | real definition. */ | |
8687 | ||
8688 | void | |
8689 | toc_section () | |
8690 | { | |
8691 | } | |
8692 | ||
8693 | #endif /* TARGET_MACHO */ | |
7c262518 RH |
8694 | |
8695 | #if TARGET_ELF | |
8696 | static unsigned int | |
8697 | rs6000_elf_section_type_flags (decl, name, reloc) | |
8698 | tree decl; | |
8699 | const char *name; | |
8700 | int reloc; | |
8701 | { | |
8702 | unsigned int flags = default_section_type_flags (decl, name, reloc); | |
8703 | ||
270fc29b RH |
8704 | if (TARGET_RELOCATABLE) |
8705 | flags |= SECTION_WRITE; | |
7c262518 RH |
8706 | |
8707 | /* Solaris doesn't like @nobits, and gas can handle .sbss without it. */ | |
8708 | flags &= ~SECTION_BSS; | |
d0101753 FS |
8709 | |
8710 | return flags; | |
7c262518 | 8711 | } |
d9f6800d RH |
8712 | |
8713 | /* Record an element in the table of global constructors. SYMBOL is | |
8714 | a SYMBOL_REF of the function to be called; PRIORITY is a number | |
8715 | between 0 and MAX_INIT_PRIORITY. | |
8716 | ||
8717 | This differs from default_named_section_asm_out_constructor in | |
8718 | that we have special handling for -mrelocatable. */ | |
8719 | ||
8720 | static void | |
8721 | rs6000_elf_asm_out_constructor (symbol, priority) | |
8722 | rtx symbol; | |
8723 | int priority; | |
8724 | { | |
8725 | const char *section = ".ctors"; | |
8726 | char buf[16]; | |
8727 | ||
8728 | if (priority != DEFAULT_INIT_PRIORITY) | |
8729 | { | |
8730 | sprintf (buf, ".ctors.%.5u", | |
8731 | /* Invert the numbering so the linker puts us in the proper | |
8732 | order; constructors are run from right to left, and the | |
8733 | linker sorts in increasing order. */ | |
8734 | MAX_INIT_PRIORITY - priority); | |
8735 | section = buf; | |
8736 | } | |
8737 | ||
715bdd29 RH |
8738 | named_section_flags (section, SECTION_WRITE); |
8739 | assemble_align (POINTER_SIZE); | |
d9f6800d RH |
8740 | |
8741 | if (TARGET_RELOCATABLE) | |
8742 | { | |
8743 | fputs ("\t.long (", asm_out_file); | |
8744 | output_addr_const (asm_out_file, symbol); | |
8745 | fputs (")@fixup\n", asm_out_file); | |
8746 | } | |
8747 | else | |
c8af3574 | 8748 | assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1); |
d9f6800d RH |
8749 | } |
8750 | ||
8751 | static void | |
8752 | rs6000_elf_asm_out_destructor (symbol, priority) | |
8753 | rtx symbol; | |
8754 | int priority; | |
8755 | { | |
8756 | const char *section = ".dtors"; | |
8757 | char buf[16]; | |
8758 | ||
8759 | if (priority != DEFAULT_INIT_PRIORITY) | |
8760 | { | |
8761 | sprintf (buf, ".dtors.%.5u", | |
8762 | /* Invert the numbering so the linker puts us in the proper | |
8763 | order; constructors are run from right to left, and the | |
8764 | linker sorts in increasing order. */ | |
8765 | MAX_INIT_PRIORITY - priority); | |
8766 | section = buf; | |
8767 | } | |
8768 | ||
715bdd29 RH |
8769 | named_section_flags (section, SECTION_WRITE); |
8770 | assemble_align (POINTER_SIZE); | |
d9f6800d RH |
8771 | |
8772 | if (TARGET_RELOCATABLE) | |
8773 | { | |
8774 | fputs ("\t.long (", asm_out_file); | |
8775 | output_addr_const (asm_out_file, symbol); | |
8776 | fputs (")@fixup\n", asm_out_file); | |
8777 | } | |
8778 | else | |
c8af3574 | 8779 | assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1); |
d9f6800d | 8780 | } |
7c262518 RH |
8781 | #endif |
8782 | ||
8783 | #ifdef OBJECT_FORMAT_COFF | |
8784 | static void | |
715bdd29 | 8785 | xcoff_asm_named_section (name, flags) |
7c262518 RH |
8786 | const char *name; |
8787 | unsigned int flags ATTRIBUTE_UNUSED; | |
7c262518 RH |
8788 | { |
8789 | fprintf (asm_out_file, "\t.csect %s\n", name); | |
8790 | } | |
8791 | #endif |