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9878760c 1/* Subroutines used for code generation on IBM RS/6000.
f676971a 2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
5b86a469 3 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
fab3bcc3 4 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
9878760c 5
5de601cf 6 This file is part of GCC.
9878760c 7
5de601cf
NC		 8 GCC is free software; you can redistribute it and/or modify it
9 under the terms of the GNU General Public License as published
10 by the Free Software Foundation; either version 2, or (at your
11 option) any later version.
9878760c 12
5de601cf
NC		 13 GCC is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
9878760c 17
5de601cf
NC		 18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING. If not, write to the
20 Free Software Foundation, 59 Temple Place - Suite 330, Boston,
21 MA 02111-1307, USA. */
9878760c 22
956d6950 23#include "config.h"
c4d38ccb 24#include "system.h"
4977bab6
ZW		 25#include "coretypes.h"
26#include "tm.h"
9878760c
RK		 27#include "rtl.h"
28#include "regs.h"
29#include "hard-reg-set.h"
30#include "real.h"
31#include "insn-config.h"
32#include "conditions.h"
9878760c
RK		 33#include "insn-attr.h"
34#include "flags.h"
35#include "recog.h"
9878760c 36#include "obstack.h"
9b30bae2 37#include "tree.h"
dfafc897 38#include "expr.h"
2fc1c679 39#include "optabs.h"
2a430ec1 40#include "except.h"
a7df97e6 41#include "function.h"
296b8152 42#include "output.h"
d5fa86ba 43#include "basic-block.h"
d0101753 44#include "integrate.h"
296b8152 45#include "toplev.h"
c8023011 46#include "ggc.h"
9ebbca7d
GK		 47#include "hashtab.h"
48#include "tm_p.h"
672a6f42
NB		 49#include "target.h"
50#include "target-def.h"
3ac88239 51#include "langhooks.h"
24ea750e 52#include "reload.h"
117dca74 53#include "cfglayout.h"
79ae11c4 54#include "sched-int.h"
cd3ce9b4 55#include "tree-gimple.h"
4d3e6fae 56#include "intl.h"
1bc7c5b6
ZW		 57#if TARGET_XCOFF
58#include "xcoffout.h" /* get declarations of xcoff_*_section_name */
59#endif
93a27b7b
ZW		 60#if TARGET_MACHO
61#include "gstab.h" /* for N_SLINE */
62#endif
9b30bae2 63
7509c759
MM		 64#ifndef TARGET_NO_PROTOTYPE
65#define TARGET_NO_PROTOTYPE 0
66#endif
67
9878760c
RK		 68#define min(A,B) ((A) < (B) ? (A) : (B))
69#define max(A,B) ((A) > (B) ? (A) : (B))
70
d1d0c603
JJ		 71/* Structure used to define the rs6000 stack */
72typedef struct rs6000_stack {
73 int first_gp_reg_save; /* first callee saved GP register used */
74 int first_fp_reg_save; /* first callee saved FP register used */
75 int first_altivec_reg_save; /* first callee saved AltiVec register used */
76 int lr_save_p; /* true if the link reg needs to be saved */
77 int cr_save_p; /* true if the CR reg needs to be saved */
78 unsigned int vrsave_mask; /* mask of vec registers to save */
79 int toc_save_p; /* true if the TOC needs to be saved */
80 int push_p; /* true if we need to allocate stack space */
81 int calls_p; /* true if the function makes any calls */
c4ad648e 82 int world_save_p; /* true if we're saving *everything*:
d62294f5 83 r13-r31, cr, f14-f31, vrsave, v20-v31 */
d1d0c603
JJ		 84 enum rs6000_abi abi; /* which ABI to use */
85 int gp_save_offset; /* offset to save GP regs from initial SP */
86 int fp_save_offset; /* offset to save FP regs from initial SP */
87 int altivec_save_offset; /* offset to save AltiVec regs from initial SP */
88 int lr_save_offset; /* offset to save LR from initial SP */
89 int cr_save_offset; /* offset to save CR from initial SP */
90 int vrsave_save_offset; /* offset to save VRSAVE from initial SP */
91 int spe_gp_save_offset; /* offset to save spe 64-bit gprs */
92 int toc_save_offset; /* offset to save the TOC pointer */
93 int varargs_save_offset; /* offset to save the varargs registers */
94 int ehrd_offset; /* offset to EH return data */
95 int reg_size; /* register size (4 or 8) */
96 int varargs_size; /* size to hold V.4 args passed in regs */
97 HOST_WIDE_INT vars_size; /* variable save area size */
98 int parm_size; /* outgoing parameter size */
99 int save_size; /* save area size */
100 int fixed_size; /* fixed size of stack frame */
101 int gp_size; /* size of saved GP registers */
102 int fp_size; /* size of saved FP registers */
103 int altivec_size; /* size of saved AltiVec registers */
104 int cr_size; /* size to hold CR if not in save_size */
105 int lr_size; /* size to hold LR if not in save_size */
106 int vrsave_size; /* size to hold VRSAVE if not in save_size */
107 int altivec_padding_size; /* size of altivec alignment padding if
108 not in save_size */
109 int spe_gp_size; /* size of 64-bit GPR save size for SPE */
110 int spe_padding_size;
111 int toc_size; /* size to hold TOC if not in save_size */
112 HOST_WIDE_INT total_size; /* total bytes allocated for stack */
113 int spe_64bit_regs_used;
114} rs6000_stack_t;
115
5248c961
RK		 116/* Target cpu type */
117
118enum processor_type rs6000_cpu;
8e3f41e7
MM		 119struct rs6000_cpu_select rs6000_select[3] =
120{
815cdc52
MM		 121 /* switch name, tune arch */
122 { (const char *)0, "--with-cpu=", 1, 1 },
123 { (const char *)0, "-mcpu=", 1, 1 },
124 { (const char *)0, "-mtune=", 1, 0 },
8e3f41e7 125};
5248c961 126
ec507f2d
DE		 127/* Always emit branch hint bits. */
128static GTY(()) bool rs6000_always_hint;
129
130/* Schedule instructions for group formation. */
131static GTY(()) bool rs6000_sched_groups;
132
569fa502
DN		 133/* Support for -msched-costly-dep option. */
134const char *rs6000_sched_costly_dep_str;
135enum rs6000_dependence_cost rs6000_sched_costly_dep;
136
cbe26ab8
DN		 137/* Support for -minsert-sched-nops option. */
138const char *rs6000_sched_insert_nops_str;
139enum rs6000_nop_insertion rs6000_sched_insert_nops;
140
7ccf35ed 141/* Support targetm.vectorize.builtin_mask_for_load. */
13c62176 142static GTY(()) tree altivec_builtin_mask_for_load;
7ccf35ed 143
6fa3f289 144/* Size of long double */
6fa3f289
ZW		 145int rs6000_long_double_type_size;
146
147/* Whether -mabi=altivec has appeared */
148int rs6000_altivec_abi;
149
a3170dc6
AH		 150/* Nonzero if we want SPE ABI extensions. */
151int rs6000_spe_abi;
152
5da702b1
AH		 153/* Nonzero if floating point operations are done in the GPRs. */
154int rs6000_float_gprs = 0;
155
594a51fe
SS		 156/* Nonzero if we want Darwin's struct-by-value-in-regs ABI. */
157int rs6000_darwin64_abi;
158
a0ab749a 159/* Set to nonzero once AIX common-mode calls have been defined. */
bbfb86aa 160static GTY(()) int common_mode_defined;
c81bebd7 161
9878760c
RK		 162/* Save information from a "cmpxx" operation until the branch or scc is
163 emitted. */
9878760c
RK		 164rtx rs6000_compare_op0, rs6000_compare_op1;
165int rs6000_compare_fp_p;
874a0744 166
874a0744
MM		 167/* Label number of label created for -mrelocatable, to call to so we can
168 get the address of the GOT section */
169int rs6000_pic_labelno;
c81bebd7 170
b91da81f 171#ifdef USING_ELFOS_H
c81bebd7 172/* Which abi to adhere to */
9739c90c 173const char *rs6000_abi_name;
d9407988
MM		 174
175/* Semantics of the small data area */
176enum rs6000_sdata_type rs6000_sdata = SDATA_DATA;
177
178/* Which small data model to use */
815cdc52 179const char *rs6000_sdata_name = (char *)0;
9ebbca7d
GK		 180
181/* Counter for labels which are to be placed in .fixup. */
182int fixuplabelno = 0;
874a0744 183#endif
4697a36c 184
c4501e62
JJ		 185/* Bit size of immediate TLS offsets and string from which it is decoded. */
186int rs6000_tls_size = 32;
187const char *rs6000_tls_size_string;
188
b6c9286a
MM		 189/* ABI enumeration available for subtarget to use. */
190enum rs6000_abi rs6000_current_abi;
191
85b776df
AM		 192/* Whether to use variant of AIX ABI for PowerPC64 Linux. */
193int dot_symbols;
194
38c1f2d7 195/* Debug flags */
815cdc52 196const char *rs6000_debug_name;
38c1f2d7
MM		 197int rs6000_debug_stack; /* debug stack applications */
198int rs6000_debug_arg; /* debug argument handling */
199
aabcd309 200/* Value is TRUE if register/mode pair is acceptable. */
0d1fbc8c
AH		 201bool rs6000_hard_regno_mode_ok_p[NUM_MACHINE_MODES][FIRST_PSEUDO_REGISTER];
202
58646b77
PB		 203/* Built in types. */
204
205tree rs6000_builtin_types[RS6000_BTI_MAX];
206tree rs6000_builtin_decls[RS6000_BUILTIN_COUNT];
8bb418a3 207
57ac7be9
AM		 208const char *rs6000_traceback_name;
209static enum {
210 traceback_default = 0,
211 traceback_none,
212 traceback_part,
213 traceback_full
214} rs6000_traceback;
215
38c1f2d7
MM		 216/* Flag to say the TOC is initialized */
217int toc_initialized;
9ebbca7d 218char toc_label_name[10];
38c1f2d7 219
9ebbca7d 220/* Alias set for saves and restores from the rs6000 stack. */
f103e34d 221static GTY(()) int rs6000_sr_alias_set;
c8023011 222
a3c9585f
KH		 223/* Control alignment for fields within structures. */
224/* String from -malign-XXXXX. */
025d9908
KH		 225int rs6000_alignment_flags;
226
78f5898b
AH		 227/* True for any options that were explicitly set. */
228struct {
229 bool alignment; /* True if -malign- was used. */
230 bool abi; /* True if -mabi= was used. */
231 bool spe; /* True if -mspe= was used. */
232 bool float_gprs; /* True if -mfloat-gprs= was used. */
233 bool isel; /* True if -misel was used. */
234 bool long_double; /* True if -mlong-double- was used. */
235} rs6000_explicit_options;
236
a3170dc6
AH		 237struct builtin_description
238{
239 /* mask is not const because we're going to alter it below. This
240 nonsense will go away when we rewrite the -march infrastructure
241 to give us more target flag bits. */
242 unsigned int mask;
243 const enum insn_code icode;
244 const char *const name;
245 const enum rs6000_builtins code;
246};
8b897cfa
RS		 247\f
248/* Target cpu costs. */
249
250struct processor_costs {
c4ad648e 251 const int mulsi; /* cost of SImode multiplication. */
8b897cfa
RS		 252 const int mulsi_const; /* cost of SImode multiplication by constant. */
253 const int mulsi_const9; /* cost of SImode mult by short constant. */
c4ad648e
AM		 254 const int muldi; /* cost of DImode multiplication. */
255 const int divsi; /* cost of SImode division. */
256 const int divdi; /* cost of DImode division. */
257 const int fp; /* cost of simple SFmode and DFmode insns. */
258 const int dmul; /* cost of DFmode multiplication (and fmadd). */
259 const int sdiv; /* cost of SFmode division (fdivs). */
260 const int ddiv; /* cost of DFmode division (fdiv). */
8b897cfa
RS		 261};
262
263const struct processor_costs *rs6000_cost;
264
265/* Processor costs (relative to an add) */
266
267/* Instruction size costs on 32bit processors. */
268static const
269struct processor_costs size32_cost = {
06a67bdd
RS		 270 COSTS_N_INSNS (1), /* mulsi */
271 COSTS_N_INSNS (1), /* mulsi_const */
272 COSTS_N_INSNS (1), /* mulsi_const9 */
273 COSTS_N_INSNS (1), /* muldi */
274 COSTS_N_INSNS (1), /* divsi */
275 COSTS_N_INSNS (1), /* divdi */
276 COSTS_N_INSNS (1), /* fp */
277 COSTS_N_INSNS (1), /* dmul */
278 COSTS_N_INSNS (1), /* sdiv */
279 COSTS_N_INSNS (1), /* ddiv */
8b897cfa
RS		 280};
281
282/* Instruction size costs on 64bit processors. */
283static const
284struct processor_costs size64_cost = {
06a67bdd
RS		 285 COSTS_N_INSNS (1), /* mulsi */
286 COSTS_N_INSNS (1), /* mulsi_const */
287 COSTS_N_INSNS (1), /* mulsi_const9 */
288 COSTS_N_INSNS (1), /* muldi */
289 COSTS_N_INSNS (1), /* divsi */
290 COSTS_N_INSNS (1), /* divdi */
291 COSTS_N_INSNS (1), /* fp */
292 COSTS_N_INSNS (1), /* dmul */
293 COSTS_N_INSNS (1), /* sdiv */
294 COSTS_N_INSNS (1), /* ddiv */
8b897cfa
RS		 295};
296
297/* Instruction costs on RIOS1 processors. */
298static const
299struct processor_costs rios1_cost = {
06a67bdd
RS		 300 COSTS_N_INSNS (5), /* mulsi */
301 COSTS_N_INSNS (4), /* mulsi_const */
302 COSTS_N_INSNS (3), /* mulsi_const9 */
303 COSTS_N_INSNS (5), /* muldi */
304 COSTS_N_INSNS (19), /* divsi */
305 COSTS_N_INSNS (19), /* divdi */
306 COSTS_N_INSNS (2), /* fp */
307 COSTS_N_INSNS (2), /* dmul */
308 COSTS_N_INSNS (19), /* sdiv */
309 COSTS_N_INSNS (19), /* ddiv */
8b897cfa
RS		 310};
311
312/* Instruction costs on RIOS2 processors. */
313static const
314struct processor_costs rios2_cost = {
06a67bdd
RS		 315 COSTS_N_INSNS (2), /* mulsi */
316 COSTS_N_INSNS (2), /* mulsi_const */
317 COSTS_N_INSNS (2), /* mulsi_const9 */
318 COSTS_N_INSNS (2), /* muldi */
319 COSTS_N_INSNS (13), /* divsi */
320 COSTS_N_INSNS (13), /* divdi */
321 COSTS_N_INSNS (2), /* fp */
322 COSTS_N_INSNS (2), /* dmul */
323 COSTS_N_INSNS (17), /* sdiv */
324 COSTS_N_INSNS (17), /* ddiv */
8b897cfa
RS		 325};
326
327/* Instruction costs on RS64A processors. */
328static const
329struct processor_costs rs64a_cost = {
06a67bdd
RS		 330 COSTS_N_INSNS (20), /* mulsi */
331 COSTS_N_INSNS (12), /* mulsi_const */
332 COSTS_N_INSNS (8), /* mulsi_const9 */
333 COSTS_N_INSNS (34), /* muldi */
334 COSTS_N_INSNS (65), /* divsi */
335 COSTS_N_INSNS (67), /* divdi */
336 COSTS_N_INSNS (4), /* fp */
337 COSTS_N_INSNS (4), /* dmul */
338 COSTS_N_INSNS (31), /* sdiv */
339 COSTS_N_INSNS (31), /* ddiv */
8b897cfa
RS		 340};
341
342/* Instruction costs on MPCCORE processors. */
343static const
344struct processor_costs mpccore_cost = {
06a67bdd
RS		 345 COSTS_N_INSNS (2), /* mulsi */
346 COSTS_N_INSNS (2), /* mulsi_const */
347 COSTS_N_INSNS (2), /* mulsi_const9 */
348 COSTS_N_INSNS (2), /* muldi */
349 COSTS_N_INSNS (6), /* divsi */
350 COSTS_N_INSNS (6), /* divdi */
351 COSTS_N_INSNS (4), /* fp */
352 COSTS_N_INSNS (5), /* dmul */
353 COSTS_N_INSNS (10), /* sdiv */
354 COSTS_N_INSNS (17), /* ddiv */
8b897cfa
RS		 355};
356
357/* Instruction costs on PPC403 processors. */
358static const
359struct processor_costs ppc403_cost = {
06a67bdd
RS		 360 COSTS_N_INSNS (4), /* mulsi */
361 COSTS_N_INSNS (4), /* mulsi_const */
362 COSTS_N_INSNS (4), /* mulsi_const9 */
363 COSTS_N_INSNS (4), /* muldi */
364 COSTS_N_INSNS (33), /* divsi */
365 COSTS_N_INSNS (33), /* divdi */
366 COSTS_N_INSNS (11), /* fp */
367 COSTS_N_INSNS (11), /* dmul */
368 COSTS_N_INSNS (11), /* sdiv */
369 COSTS_N_INSNS (11), /* ddiv */
8b897cfa
RS		 370};
371
372/* Instruction costs on PPC405 processors. */
373static const
374struct processor_costs ppc405_cost = {
06a67bdd
RS		 375 COSTS_N_INSNS (5), /* mulsi */
376 COSTS_N_INSNS (4), /* mulsi_const */
377 COSTS_N_INSNS (3), /* mulsi_const9 */
378 COSTS_N_INSNS (5), /* muldi */
379 COSTS_N_INSNS (35), /* divsi */
380 COSTS_N_INSNS (35), /* divdi */
381 COSTS_N_INSNS (11), /* fp */
382 COSTS_N_INSNS (11), /* dmul */
383 COSTS_N_INSNS (11), /* sdiv */
384 COSTS_N_INSNS (11), /* ddiv */
8b897cfa
RS		 385};
386
387/* Instruction costs on PPC440 processors. */
388static const
389struct processor_costs ppc440_cost = {
06a67bdd
RS		 390 COSTS_N_INSNS (3), /* mulsi */
391 COSTS_N_INSNS (2), /* mulsi_const */
392 COSTS_N_INSNS (2), /* mulsi_const9 */
393 COSTS_N_INSNS (3), /* muldi */
394 COSTS_N_INSNS (34), /* divsi */
395 COSTS_N_INSNS (34), /* divdi */
396 COSTS_N_INSNS (5), /* fp */
397 COSTS_N_INSNS (5), /* dmul */
398 COSTS_N_INSNS (19), /* sdiv */
399 COSTS_N_INSNS (33), /* ddiv */
8b897cfa
RS		 400};
401
402/* Instruction costs on PPC601 processors. */
403static const
404struct processor_costs ppc601_cost = {
06a67bdd
RS		 405 COSTS_N_INSNS (5), /* mulsi */
406 COSTS_N_INSNS (5), /* mulsi_const */
407 COSTS_N_INSNS (5), /* mulsi_const9 */
408 COSTS_N_INSNS (5), /* muldi */
409 COSTS_N_INSNS (36), /* divsi */
410 COSTS_N_INSNS (36), /* divdi */
411 COSTS_N_INSNS (4), /* fp */
412 COSTS_N_INSNS (5), /* dmul */
413 COSTS_N_INSNS (17), /* sdiv */
414 COSTS_N_INSNS (31), /* ddiv */
8b897cfa
RS		 415};
416
417/* Instruction costs on PPC603 processors. */
418static const
419struct processor_costs ppc603_cost = {
06a67bdd
RS		 420 COSTS_N_INSNS (5), /* mulsi */
421 COSTS_N_INSNS (3), /* mulsi_const */
422 COSTS_N_INSNS (2), /* mulsi_const9 */
423 COSTS_N_INSNS (5), /* muldi */
424 COSTS_N_INSNS (37), /* divsi */
425 COSTS_N_INSNS (37), /* divdi */
426 COSTS_N_INSNS (3), /* fp */
427 COSTS_N_INSNS (4), /* dmul */
428 COSTS_N_INSNS (18), /* sdiv */
429 COSTS_N_INSNS (33), /* ddiv */
8b897cfa
RS		 430};
431
432/* Instruction costs on PPC604 processors. */
433static const
434struct processor_costs ppc604_cost = {
06a67bdd
RS		 435 COSTS_N_INSNS (4), /* mulsi */
436 COSTS_N_INSNS (4), /* mulsi_const */
437 COSTS_N_INSNS (4), /* mulsi_const9 */
438 COSTS_N_INSNS (4), /* muldi */
439 COSTS_N_INSNS (20), /* divsi */
440 COSTS_N_INSNS (20), /* divdi */
441 COSTS_N_INSNS (3), /* fp */
442 COSTS_N_INSNS (3), /* dmul */
443 COSTS_N_INSNS (18), /* sdiv */
444 COSTS_N_INSNS (32), /* ddiv */
8b897cfa
RS		 445};
446
447/* Instruction costs on PPC604e processors. */
448static const
449struct processor_costs ppc604e_cost = {
06a67bdd
RS		 450 COSTS_N_INSNS (2), /* mulsi */
451 COSTS_N_INSNS (2), /* mulsi_const */
452 COSTS_N_INSNS (2), /* mulsi_const9 */
453 COSTS_N_INSNS (2), /* muldi */
454 COSTS_N_INSNS (20), /* divsi */
455 COSTS_N_INSNS (20), /* divdi */
456 COSTS_N_INSNS (3), /* fp */
457 COSTS_N_INSNS (3), /* dmul */
458 COSTS_N_INSNS (18), /* sdiv */
459 COSTS_N_INSNS (32), /* ddiv */
8b897cfa
RS		 460};
461
f0517163 462/* Instruction costs on PPC620 processors. */
8b897cfa
RS		 463static const
464struct processor_costs ppc620_cost = {
06a67bdd
RS		 465 COSTS_N_INSNS (5), /* mulsi */
466 COSTS_N_INSNS (4), /* mulsi_const */
467 COSTS_N_INSNS (3), /* mulsi_const9 */
468 COSTS_N_INSNS (7), /* muldi */
469 COSTS_N_INSNS (21), /* divsi */
470 COSTS_N_INSNS (37), /* divdi */
471 COSTS_N_INSNS (3), /* fp */
472 COSTS_N_INSNS (3), /* dmul */
473 COSTS_N_INSNS (18), /* sdiv */
474 COSTS_N_INSNS (32), /* ddiv */
f0517163
RS		 475};
476
477/* Instruction costs on PPC630 processors. */
478static const
479struct processor_costs ppc630_cost = {
06a67bdd
RS		 480 COSTS_N_INSNS (5), /* mulsi */
481 COSTS_N_INSNS (4), /* mulsi_const */
482 COSTS_N_INSNS (3), /* mulsi_const9 */
483 COSTS_N_INSNS (7), /* muldi */
484 COSTS_N_INSNS (21), /* divsi */
485 COSTS_N_INSNS (37), /* divdi */
486 COSTS_N_INSNS (3), /* fp */
487 COSTS_N_INSNS (3), /* dmul */
488 COSTS_N_INSNS (17), /* sdiv */
489 COSTS_N_INSNS (21), /* ddiv */
8b897cfa
RS		 490};
491
492/* Instruction costs on PPC750 and PPC7400 processors. */
493static const
494struct processor_costs ppc750_cost = {
06a67bdd
RS		 495 COSTS_N_INSNS (5), /* mulsi */
496 COSTS_N_INSNS (3), /* mulsi_const */
497 COSTS_N_INSNS (2), /* mulsi_const9 */
498 COSTS_N_INSNS (5), /* muldi */
499 COSTS_N_INSNS (17), /* divsi */
500 COSTS_N_INSNS (17), /* divdi */
501 COSTS_N_INSNS (3), /* fp */
502 COSTS_N_INSNS (3), /* dmul */
503 COSTS_N_INSNS (17), /* sdiv */
504 COSTS_N_INSNS (31), /* ddiv */
8b897cfa
RS		 505};
506
507/* Instruction costs on PPC7450 processors. */
508static const
509struct processor_costs ppc7450_cost = {
06a67bdd
RS		 510 COSTS_N_INSNS (4), /* mulsi */
511 COSTS_N_INSNS (3), /* mulsi_const */
512 COSTS_N_INSNS (3), /* mulsi_const9 */
513 COSTS_N_INSNS (4), /* muldi */
514 COSTS_N_INSNS (23), /* divsi */
515 COSTS_N_INSNS (23), /* divdi */
516 COSTS_N_INSNS (5), /* fp */
517 COSTS_N_INSNS (5), /* dmul */
518 COSTS_N_INSNS (21), /* sdiv */
519 COSTS_N_INSNS (35), /* ddiv */
8b897cfa 520};
a3170dc6 521
8b897cfa
RS		 522/* Instruction costs on PPC8540 processors. */
523static const
524struct processor_costs ppc8540_cost = {
06a67bdd
RS		 525 COSTS_N_INSNS (4), /* mulsi */
526 COSTS_N_INSNS (4), /* mulsi_const */
527 COSTS_N_INSNS (4), /* mulsi_const9 */
528 COSTS_N_INSNS (4), /* muldi */
529 COSTS_N_INSNS (19), /* divsi */
530 COSTS_N_INSNS (19), /* divdi */
531 COSTS_N_INSNS (4), /* fp */
532 COSTS_N_INSNS (4), /* dmul */
533 COSTS_N_INSNS (29), /* sdiv */
534 COSTS_N_INSNS (29), /* ddiv */
8b897cfa
RS		 535};
536
537/* Instruction costs on POWER4 and POWER5 processors. */
538static const
539struct processor_costs power4_cost = {
06a67bdd
RS		 540 COSTS_N_INSNS (3), /* mulsi */
541 COSTS_N_INSNS (2), /* mulsi_const */
542 COSTS_N_INSNS (2), /* mulsi_const9 */
543 COSTS_N_INSNS (4), /* muldi */
544 COSTS_N_INSNS (18), /* divsi */
545 COSTS_N_INSNS (34), /* divdi */
546 COSTS_N_INSNS (3), /* fp */
547 COSTS_N_INSNS (3), /* dmul */
548 COSTS_N_INSNS (17), /* sdiv */
549 COSTS_N_INSNS (17), /* ddiv */
8b897cfa
RS		 550};
551
552\f
a2369ed3 553static bool rs6000_function_ok_for_sibcall (tree, tree);
a2369ed3
DJ		 554static rtx rs6000_generate_compare (enum rtx_code);
555static void rs6000_maybe_dead (rtx);
556static void rs6000_emit_stack_tie (void);
557static void rs6000_frame_related (rtx, rtx, HOST_WIDE_INT, rtx, rtx);
558static rtx spe_synthesize_frame_save (rtx);
559static bool spe_func_has_64bit_regs_p (void);
b20a9cca 560static void emit_frame_save (rtx, rtx, enum machine_mode, unsigned int,
d1d0c603 561 int, HOST_WIDE_INT);
a2369ed3
DJ		 562static rtx gen_frame_mem_offset (enum machine_mode, rtx, int);
563static void rs6000_emit_allocate_stack (HOST_WIDE_INT, int);
564static unsigned rs6000_hash_constant (rtx);
565static unsigned toc_hash_function (const void *);
566static int toc_hash_eq (const void *, const void *);
567static int constant_pool_expr_1 (rtx, int *, int *);
568static bool constant_pool_expr_p (rtx);
a2369ed3 569static bool legitimate_small_data_p (enum machine_mode, rtx);
a2369ed3 570static bool legitimate_indexed_address_p (rtx, int);
a2369ed3
DJ		 571static bool legitimate_lo_sum_address_p (enum machine_mode, rtx, int);
572static struct machine_function * rs6000_init_machine_status (void);
573static bool rs6000_assemble_integer (rtx, unsigned int, int);
5add3202 574#ifdef HAVE_GAS_HIDDEN
a2369ed3 575static void rs6000_assemble_visibility (tree, int);
5add3202 576#endif
a2369ed3
DJ		 577static int rs6000_ra_ever_killed (void);
578static tree rs6000_handle_longcall_attribute (tree *, tree, tree, int, bool *);
8bb418a3 579static tree rs6000_handle_altivec_attribute (tree *, tree, tree, int, bool *);
76d2b81d 580static void rs6000_eliminate_indexed_memrefs (rtx operands[2]);
f18eca82 581static const char *rs6000_mangle_fundamental_type (tree);
b86fe7b4 582extern const struct attribute_spec rs6000_attribute_table[];
a2369ed3
DJ		 583static void rs6000_set_default_type_attributes (tree);
584static void rs6000_output_function_prologue (FILE *, HOST_WIDE_INT);
585static void rs6000_output_function_epilogue (FILE *, HOST_WIDE_INT);
b20a9cca
AM		 586static void rs6000_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT,
587 tree);
a2369ed3 588static rtx rs6000_emit_set_long_const (rtx, HOST_WIDE_INT, HOST_WIDE_INT);
c6e8c921 589static bool rs6000_return_in_memory (tree, tree);
a2369ed3 590static void rs6000_file_start (void);
7c262518 591#if TARGET_ELF
a2369ed3
DJ		 592static unsigned int rs6000_elf_section_type_flags (tree, const char *, int);
593static void rs6000_elf_asm_out_constructor (rtx, int);
594static void rs6000_elf_asm_out_destructor (rtx, int);
1334b570 595static void rs6000_elf_end_indicate_exec_stack (void) ATTRIBUTE_UNUSED;
a2369ed3
DJ		 596static void rs6000_elf_select_section (tree, int, unsigned HOST_WIDE_INT);
597static void rs6000_elf_unique_section (tree, int);
598static void rs6000_elf_select_rtx_section (enum machine_mode, rtx,
b20a9cca 599 unsigned HOST_WIDE_INT);
a56d7372 600static void rs6000_elf_encode_section_info (tree, rtx, int)
0e5dbd9b 601 ATTRIBUTE_UNUSED;
a2369ed3 602static bool rs6000_elf_in_small_data_p (tree);
7c262518 603#endif
cbaaba19 604#if TARGET_XCOFF
a2369ed3 605static void rs6000_xcoff_asm_globalize_label (FILE *, const char *);
8210e4c4 606static void rs6000_xcoff_asm_named_section (const char *, unsigned int, tree);
a2369ed3
DJ		 607static void rs6000_xcoff_select_section (tree, int, unsigned HOST_WIDE_INT);
608static void rs6000_xcoff_unique_section (tree, int);
609static void rs6000_xcoff_select_rtx_section (enum machine_mode, rtx,
b20a9cca 610 unsigned HOST_WIDE_INT);
a2369ed3
DJ		 611static const char * rs6000_xcoff_strip_name_encoding (const char *);
612static unsigned int rs6000_xcoff_section_type_flags (tree, const char *, int);
613static void rs6000_xcoff_file_start (void);
614static void rs6000_xcoff_file_end (void);
f1384257
AM		 615#endif
616#if TARGET_MACHO
a2369ed3 617static bool rs6000_binds_local_p (tree);
f1384257 618#endif
a2369ed3
DJ		 619static int rs6000_variable_issue (FILE *, int, rtx, int);
620static bool rs6000_rtx_costs (rtx, int, int, int *);
621static int rs6000_adjust_cost (rtx, rtx, rtx, int);
cbe26ab8 622static bool is_microcoded_insn (rtx);
79ae11c4 623static int is_dispatch_slot_restricted (rtx);
cbe26ab8
DN		 624static bool is_cracked_insn (rtx);
625static bool is_branch_slot_insn (rtx);
a2369ed3
DJ		 626static int rs6000_adjust_priority (rtx, int);
627static int rs6000_issue_rate (void);
569fa502 628static bool rs6000_is_costly_dependence (rtx, rtx, rtx, int, int);
cbe26ab8
DN		 629static rtx get_next_active_insn (rtx, rtx);
630static bool insn_terminates_group_p (rtx , enum group_termination);
631static bool is_costly_group (rtx *, rtx);
632static int force_new_group (int, FILE *, rtx *, rtx, bool *, int, int *);
633static int redefine_groups (FILE *, int, rtx, rtx);
634static int pad_groups (FILE *, int, rtx, rtx);
635static void rs6000_sched_finish (FILE *, int);
a2369ed3 636static int rs6000_use_sched_lookahead (void);
7ccf35ed 637static tree rs6000_builtin_mask_for_load (void);
a2369ed3 638
58646b77 639static void def_builtin (int, const char *, tree, int);
a2369ed3
DJ		 640static void rs6000_init_builtins (void);
641static rtx rs6000_expand_unop_builtin (enum insn_code, tree, rtx);
642static rtx rs6000_expand_binop_builtin (enum insn_code, tree, rtx);
643static rtx rs6000_expand_ternop_builtin (enum insn_code, tree, rtx);
644static rtx rs6000_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
645static void altivec_init_builtins (void);
646static void rs6000_common_init_builtins (void);
c15c90bb 647static void rs6000_init_libfuncs (void);
a2369ed3 648
b20a9cca
AM		 649static void enable_mask_for_builtins (struct builtin_description *, int,
650 enum rs6000_builtins,
651 enum rs6000_builtins);
7c62e993 652static tree build_opaque_vector_type (tree, int);
a2369ed3
DJ		 653static void spe_init_builtins (void);
654static rtx spe_expand_builtin (tree, rtx, bool *);
61bea3b0 655static rtx spe_expand_stv_builtin (enum insn_code, tree);
a2369ed3
DJ		 656static rtx spe_expand_predicate_builtin (enum insn_code, tree, rtx);
657static rtx spe_expand_evsel_builtin (enum insn_code, tree, rtx);
658static int rs6000_emit_int_cmove (rtx, rtx, rtx, rtx);
d1d0c603
JJ		 659static rs6000_stack_t *rs6000_stack_info (void);
660static void debug_stack_info (rs6000_stack_t *);
a2369ed3
DJ		 661
662static rtx altivec_expand_builtin (tree, rtx, bool *);
663static rtx altivec_expand_ld_builtin (tree, rtx, bool *);
664static rtx altivec_expand_st_builtin (tree, rtx, bool *);
665static rtx altivec_expand_dst_builtin (tree, rtx, bool *);
666static rtx altivec_expand_abs_builtin (enum insn_code, tree, rtx);
f676971a 667static rtx altivec_expand_predicate_builtin (enum insn_code,
c4ad648e 668 const char *, tree, rtx);
b4a62fa0 669static rtx altivec_expand_lv_builtin (enum insn_code, tree, rtx);
a2369ed3 670static rtx altivec_expand_stv_builtin (enum insn_code, tree);
78f5898b 671static bool rs6000_handle_option (size_t, const char *, int);
a2369ed3 672static void rs6000_parse_tls_size_option (void);
5da702b1 673static void rs6000_parse_yes_no_option (const char *, const char *, int *);
a2369ed3
DJ		 674static int first_altivec_reg_to_save (void);
675static unsigned int compute_vrsave_mask (void);
9390387d 676static void compute_save_world_info (rs6000_stack_t *info_ptr);
a2369ed3
DJ		 677static void is_altivec_return_reg (rtx, void *);
678static rtx generate_set_vrsave (rtx, rs6000_stack_t *, int);
679int easy_vector_constant (rtx, enum machine_mode);
58646b77 680static bool rs6000_is_opaque_type (tree);
a2369ed3
DJ		 681static rtx rs6000_dwarf_register_span (rtx);
682static rtx rs6000_legitimize_tls_address (rtx, enum tls_model);
683static rtx rs6000_tls_get_addr (void);
684static rtx rs6000_got_sym (void);
9390387d 685static int rs6000_tls_symbol_ref_1 (rtx *, void *);
a2369ed3
DJ		 686static const char *rs6000_get_some_local_dynamic_name (void);
687static int rs6000_get_some_local_dynamic_name_1 (rtx *, void *);
ded9bf77 688static rtx rs6000_complex_function_value (enum machine_mode);
b20a9cca 689static rtx rs6000_spe_function_arg (CUMULATIVE_ARGS *,
a2369ed3 690 enum machine_mode, tree);
0b5383eb
DJ		 691static void rs6000_darwin64_record_arg_advance_flush (CUMULATIVE_ARGS *,
692 HOST_WIDE_INT);
693static void rs6000_darwin64_record_arg_advance_recurse (CUMULATIVE_ARGS *,
694 tree, HOST_WIDE_INT);
695static void rs6000_darwin64_record_arg_flush (CUMULATIVE_ARGS *,
696 HOST_WIDE_INT,
697 rtx[], int *);
698static void rs6000_darwin64_record_arg_recurse (CUMULATIVE_ARGS *,
699 tree, HOST_WIDE_INT,
700 rtx[], int *);
701static rtx rs6000_darwin64_record_arg (CUMULATIVE_ARGS *, tree, int, bool);
ec6376ab 702static rtx rs6000_mixed_function_arg (enum machine_mode, tree, int);
b1917422 703static void rs6000_move_block_from_reg (int regno, rtx x, int nregs);
c6e8c921
GK		 704static void setup_incoming_varargs (CUMULATIVE_ARGS *,
705 enum machine_mode, tree,
706 int *, int);
8cd5a4e0
RH		 707static bool rs6000_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode,
708 tree, bool);
78a52f11
RH		 709static int rs6000_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode,
710 tree, bool);
4d3e6fae 711static const char *invalid_arg_for_unprototyped_fn (tree, tree, tree);
efdba735
SH		 712#if TARGET_MACHO
713static void macho_branch_islands (void);
714static void add_compiler_branch_island (tree, tree, int);
715static int no_previous_def (tree function_name);
716static tree get_prev_label (tree function_name);
c4e18b1c 717static void rs6000_darwin_file_start (void);
efdba735
SH		 718#endif
719
c35d187f 720static tree rs6000_build_builtin_va_list (void);
23a60a04 721static tree rs6000_gimplify_va_arg (tree, tree, tree *, tree *);
fe984136 722static bool rs6000_must_pass_in_stack (enum machine_mode, tree);
f676971a 723static bool rs6000_vector_mode_supported_p (enum machine_mode);
94ff898d 724static int get_vec_cmp_insn (enum rtx_code, enum machine_mode,
21213b4c 725 enum machine_mode);
94ff898d 726static rtx rs6000_emit_vector_compare (enum rtx_code, rtx, rtx,
21213b4c
DP		 727 enum machine_mode);
728static int get_vsel_insn (enum machine_mode);
729static void rs6000_emit_vector_select (rtx, rtx, rtx, rtx);
17211ab5 730
21213b4c
DP		 731
732const int INSN_NOT_AVAILABLE = -1;
93f90be6
FJ		 733static enum machine_mode rs6000_eh_return_filter_mode (void);
734
17211ab5
GK		 735/* Hash table stuff for keeping track of TOC entries. */
736
737struct toc_hash_struct GTY(())
738{
739 /* `key' will satisfy CONSTANT_P; in fact, it will satisfy
740 ASM_OUTPUT_SPECIAL_POOL_ENTRY_P. */
741 rtx key;
742 enum machine_mode key_mode;
743 int labelno;
744};
745
746static GTY ((param_is (struct toc_hash_struct))) htab_t toc_hash_table;
c81bebd7
MM		 747\f
748/* Default register names. */
749char rs6000_reg_names[][8] =
750{
802a0058
MM		 751 "0", "1", "2", "3", "4", "5", "6", "7",
752 "8", "9", "10", "11", "12", "13", "14", "15",
753 "16", "17", "18", "19", "20", "21", "22", "23",
754 "24", "25", "26", "27", "28", "29", "30", "31",
755 "0", "1", "2", "3", "4", "5", "6", "7",
756 "8", "9", "10", "11", "12", "13", "14", "15",
757 "16", "17", "18", "19", "20", "21", "22", "23",
758 "24", "25", "26", "27", "28", "29", "30", "31",
759 "mq", "lr", "ctr","ap",
760 "0", "1", "2", "3", "4", "5", "6", "7",
0ac081f6
AH		 761 "xer",
762 /* AltiVec registers. */
0cd5e3a1
AH		 763 "0", "1", "2", "3", "4", "5", "6", "7",
764 "8", "9", "10", "11", "12", "13", "14", "15",
765 "16", "17", "18", "19", "20", "21", "22", "23",
766 "24", "25", "26", "27", "28", "29", "30", "31",
59a4c851
AH		 767 "vrsave", "vscr",
768 /* SPE registers. */
769 "spe_acc", "spefscr"
c81bebd7
MM		 770};
771
772#ifdef TARGET_REGNAMES
8b60264b 773static const char alt_reg_names[][8] =
c81bebd7 774{
802a0058
MM		 775 "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7",
776 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15",
777 "%r16", "%r17", "%r18", "%r19", "%r20", "%r21", "%r22", "%r23",
778 "%r24", "%r25", "%r26", "%r27", "%r28", "%r29", "%r30", "%r31",
779 "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7",
780 "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15",
781 "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23",
782 "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31",
783 "mq", "lr", "ctr", "ap",
784 "%cr0", "%cr1", "%cr2", "%cr3", "%cr4", "%cr5", "%cr6", "%cr7",
0ac081f6 785 "xer",
59a4c851 786 /* AltiVec registers. */
0ac081f6 787 "%v0", "%v1", "%v2", "%v3", "%v4", "%v5", "%v6", "%v7",
59a4c851
AH		 788 "%v8", "%v9", "%v10", "%v11", "%v12", "%v13", "%v14", "%v15",
789 "%v16", "%v17", "%v18", "%v19", "%v20", "%v21", "%v22", "%v23",
790 "%v24", "%v25", "%v26", "%v27", "%v28", "%v29", "%v30", "%v31",
791 "vrsave", "vscr",
792 /* SPE registers. */
793 "spe_acc", "spefscr"
c81bebd7
MM		 794};
795#endif
9878760c 796\f
daf11973
MM		 797#ifndef MASK_STRICT_ALIGN
798#define MASK_STRICT_ALIGN 0
799#endif
ffcfcb5f
AM		 800#ifndef TARGET_PROFILE_KERNEL
801#define TARGET_PROFILE_KERNEL 0
802#endif
3961e8fe
RH		 803
804/* The VRSAVE bitmask puts bit %v0 as the most significant bit. */
805#define ALTIVEC_REG_BIT(REGNO) (0x80000000 >> ((REGNO) - FIRST_ALTIVEC_REGNO))
672a6f42
NB		 806\f
807/* Initialize the GCC target structure. */
91d231cb
JM		 808#undef TARGET_ATTRIBUTE_TABLE
809#define TARGET_ATTRIBUTE_TABLE rs6000_attribute_table
a5c76ee6
ZW		 810#undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES
811#define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES rs6000_set_default_type_attributes
daf11973 812
301d03af
RS		 813#undef TARGET_ASM_ALIGNED_DI_OP
814#define TARGET_ASM_ALIGNED_DI_OP DOUBLE_INT_ASM_OP
815
816/* Default unaligned ops are only provided for ELF. Find the ops needed
817 for non-ELF systems. */
818#ifndef OBJECT_FORMAT_ELF
cbaaba19 819#if TARGET_XCOFF
ae6c1efd 820/* For XCOFF. rs6000_assemble_integer will handle unaligned DIs on
301d03af
RS		 821 64-bit targets. */
822#undef TARGET_ASM_UNALIGNED_HI_OP
823#define TARGET_ASM_UNALIGNED_HI_OP "\t.vbyte\t2,"
824#undef TARGET_ASM_UNALIGNED_SI_OP
825#define TARGET_ASM_UNALIGNED_SI_OP "\t.vbyte\t4,"
826#undef TARGET_ASM_UNALIGNED_DI_OP
827#define TARGET_ASM_UNALIGNED_DI_OP "\t.vbyte\t8,"
828#else
829/* For Darwin. */
830#undef TARGET_ASM_UNALIGNED_HI_OP
831#define TARGET_ASM_UNALIGNED_HI_OP "\t.short\t"
832#undef TARGET_ASM_UNALIGNED_SI_OP
833#define TARGET_ASM_UNALIGNED_SI_OP "\t.long\t"
49bd1d27
SS		 834#undef TARGET_ASM_UNALIGNED_DI_OP
835#define TARGET_ASM_UNALIGNED_DI_OP "\t.quad\t"
836#undef TARGET_ASM_ALIGNED_DI_OP
837#define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
301d03af
RS		 838#endif
839#endif
840
841/* This hook deals with fixups for relocatable code and DI-mode objects
842 in 64-bit code. */
843#undef TARGET_ASM_INTEGER
844#define TARGET_ASM_INTEGER rs6000_assemble_integer
845
93638d7a
AM		 846#ifdef HAVE_GAS_HIDDEN
847#undef TARGET_ASM_ASSEMBLE_VISIBILITY
848#define TARGET_ASM_ASSEMBLE_VISIBILITY rs6000_assemble_visibility
849#endif
850
c4501e62
JJ		 851#undef TARGET_HAVE_TLS
852#define TARGET_HAVE_TLS HAVE_AS_TLS
853
854#undef TARGET_CANNOT_FORCE_CONST_MEM
855#define TARGET_CANNOT_FORCE_CONST_MEM rs6000_tls_referenced_p
856
08c148a8
NB		 857#undef TARGET_ASM_FUNCTION_PROLOGUE
858#define TARGET_ASM_FUNCTION_PROLOGUE rs6000_output_function_prologue
859#undef TARGET_ASM_FUNCTION_EPILOGUE
860#define TARGET_ASM_FUNCTION_EPILOGUE rs6000_output_function_epilogue
861
b54cf83a
DE		 862#undef TARGET_SCHED_VARIABLE_ISSUE
863#define TARGET_SCHED_VARIABLE_ISSUE rs6000_variable_issue
864
c237e94a
ZW		 865#undef TARGET_SCHED_ISSUE_RATE
866#define TARGET_SCHED_ISSUE_RATE rs6000_issue_rate
867#undef TARGET_SCHED_ADJUST_COST
868#define TARGET_SCHED_ADJUST_COST rs6000_adjust_cost
869#undef TARGET_SCHED_ADJUST_PRIORITY
870#define TARGET_SCHED_ADJUST_PRIORITY rs6000_adjust_priority
f676971a 871#undef TARGET_SCHED_IS_COSTLY_DEPENDENCE
569fa502 872#define TARGET_SCHED_IS_COSTLY_DEPENDENCE rs6000_is_costly_dependence
cbe26ab8
DN		 873#undef TARGET_SCHED_FINISH
874#define TARGET_SCHED_FINISH rs6000_sched_finish
c237e94a 875
be12c2b0
VM		 876#undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
877#define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD rs6000_use_sched_lookahead
878
7ccf35ed
DN		 879#undef TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD
880#define TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD rs6000_builtin_mask_for_load
881
0ac081f6
AH		 882#undef TARGET_INIT_BUILTINS
883#define TARGET_INIT_BUILTINS rs6000_init_builtins
884
885#undef TARGET_EXPAND_BUILTIN
886#define TARGET_EXPAND_BUILTIN rs6000_expand_builtin
887
f18eca82
ZL		 888#undef TARGET_MANGLE_FUNDAMENTAL_TYPE
889#define TARGET_MANGLE_FUNDAMENTAL_TYPE rs6000_mangle_fundamental_type
890
c15c90bb
ZW		 891#undef TARGET_INIT_LIBFUNCS
892#define TARGET_INIT_LIBFUNCS rs6000_init_libfuncs
893
f1384257 894#if TARGET_MACHO
0e5dbd9b
DE		 895#undef TARGET_BINDS_LOCAL_P
896#define TARGET_BINDS_LOCAL_P rs6000_binds_local_p
f1384257 897#endif
0e5dbd9b 898
3961e8fe
RH		 899#undef TARGET_ASM_OUTPUT_MI_THUNK
900#define TARGET_ASM_OUTPUT_MI_THUNK rs6000_output_mi_thunk
901
3961e8fe 902#undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
5b71a4e7 903#define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_tree_hwi_hwi_tree_true
00b960c7 904
4977bab6
ZW		 905#undef TARGET_FUNCTION_OK_FOR_SIBCALL
906#define TARGET_FUNCTION_OK_FOR_SIBCALL rs6000_function_ok_for_sibcall
907
3c50106f
RH		 908#undef TARGET_RTX_COSTS
909#define TARGET_RTX_COSTS rs6000_rtx_costs
dcefdf67
RH		 910#undef TARGET_ADDRESS_COST
911#define TARGET_ADDRESS_COST hook_int_rtx_0
3c50106f 912
c8e4f0e9 913#undef TARGET_VECTOR_OPAQUE_P
58646b77 914#define TARGET_VECTOR_OPAQUE_P rs6000_is_opaque_type
62e1dfcf 915
96714395
AH		 916#undef TARGET_DWARF_REGISTER_SPAN
917#define TARGET_DWARF_REGISTER_SPAN rs6000_dwarf_register_span
918
c6e8c921
GK		 919/* On rs6000, function arguments are promoted, as are function return
920 values. */
921#undef TARGET_PROMOTE_FUNCTION_ARGS
922#define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
923#undef TARGET_PROMOTE_FUNCTION_RETURN
924#define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
925
c6e8c921
GK		 926#undef TARGET_RETURN_IN_MEMORY
927#define TARGET_RETURN_IN_MEMORY rs6000_return_in_memory
928
929#undef TARGET_SETUP_INCOMING_VARARGS
930#define TARGET_SETUP_INCOMING_VARARGS setup_incoming_varargs
931
932/* Always strict argument naming on rs6000. */
933#undef TARGET_STRICT_ARGUMENT_NAMING
934#define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
935#undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED
936#define TARGET_PRETEND_OUTGOING_VARARGS_NAMED hook_bool_CUMULATIVE_ARGS_true
42ba5130
RH		 937#undef TARGET_SPLIT_COMPLEX_ARG
938#define TARGET_SPLIT_COMPLEX_ARG hook_bool_tree_true
fe984136
RH		 939#undef TARGET_MUST_PASS_IN_STACK
940#define TARGET_MUST_PASS_IN_STACK rs6000_must_pass_in_stack
8cd5a4e0
RH		 941#undef TARGET_PASS_BY_REFERENCE
942#define TARGET_PASS_BY_REFERENCE rs6000_pass_by_reference
78a52f11
RH		 943#undef TARGET_ARG_PARTIAL_BYTES
944#define TARGET_ARG_PARTIAL_BYTES rs6000_arg_partial_bytes
c6e8c921 945
c35d187f
RH		 946#undef TARGET_BUILD_BUILTIN_VA_LIST
947#define TARGET_BUILD_BUILTIN_VA_LIST rs6000_build_builtin_va_list
948
cd3ce9b4
JM		 949#undef TARGET_GIMPLIFY_VA_ARG_EXPR
950#define TARGET_GIMPLIFY_VA_ARG_EXPR rs6000_gimplify_va_arg
951
93f90be6
FJ		 952#undef TARGET_EH_RETURN_FILTER_MODE
953#define TARGET_EH_RETURN_FILTER_MODE rs6000_eh_return_filter_mode
954
f676971a
EC		 955#undef TARGET_VECTOR_MODE_SUPPORTED_P
956#define TARGET_VECTOR_MODE_SUPPORTED_P rs6000_vector_mode_supported_p
957
4d3e6fae
FJ		 958#undef TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN
959#define TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN invalid_arg_for_unprototyped_fn
960
78f5898b
AH		 961#undef TARGET_HANDLE_OPTION
962#define TARGET_HANDLE_OPTION rs6000_handle_option
963
964#undef TARGET_DEFAULT_TARGET_FLAGS
965#define TARGET_DEFAULT_TARGET_FLAGS \
966 (TARGET_DEFAULT | MASK_SCHED_PROLOG)
967
445cf5eb
JM		 968/* MPC604EUM 3.5.2 Weak Consistency between Multiple Processors
969 The PowerPC architecture requires only weak consistency among
970 processors--that is, memory accesses between processors need not be
971 sequentially consistent and memory accesses among processors can occur
972 in any order. The ability to order memory accesses weakly provides
973 opportunities for more efficient use of the system bus. Unless a
974 dependency exists, the 604e allows read operations to precede store
975 operations. */
976#undef TARGET_RELAXED_ORDERING
977#define TARGET_RELAXED_ORDERING true
978
f6897b10 979struct gcc_target targetm = TARGET_INITIALIZER;
672a6f42 980\f
0d1fbc8c
AH		 981
982/* Value is 1 if hard register REGNO can hold a value of machine-mode
983 MODE. */
984static int
985rs6000_hard_regno_mode_ok (int regno, enum machine_mode mode)
986{
987 /* The GPRs can hold any mode, but values bigger than one register
988 cannot go past R31. */
989 if (INT_REGNO_P (regno))
990 return INT_REGNO_P (regno + HARD_REGNO_NREGS (regno, mode) - 1);
991
992 /* The float registers can only hold floating modes and DImode. */
993 if (FP_REGNO_P (regno))
994 return
995 (GET_MODE_CLASS (mode) == MODE_FLOAT
996 && FP_REGNO_P (regno + HARD_REGNO_NREGS (regno, mode) - 1))
997 || (GET_MODE_CLASS (mode) == MODE_INT
998 && GET_MODE_SIZE (mode) == UNITS_PER_FP_WORD);
999
1000 /* The CR register can only hold CC modes. */
1001 if (CR_REGNO_P (regno))
1002 return GET_MODE_CLASS (mode) == MODE_CC;
1003
1004 if (XER_REGNO_P (regno))
1005 return mode == PSImode;
1006
1007 /* AltiVec only in AldyVec registers. */
1008 if (ALTIVEC_REGNO_P (regno))
1009 return ALTIVEC_VECTOR_MODE (mode);
1010
1011 /* ...but GPRs can hold SIMD data on the SPE in one register. */
1012 if (SPE_SIMD_REGNO_P (regno) && TARGET_SPE && SPE_VECTOR_MODE (mode))
1013 return 1;
1014
1015 /* We cannot put TImode anywhere except general register and it must be
1016 able to fit within the register set. */
1017
1018 return GET_MODE_SIZE (mode) <= UNITS_PER_WORD;
1019}
1020
1021/* Initialize rs6000_hard_regno_mode_ok_p table. */
1022static void
1023rs6000_init_hard_regno_mode_ok (void)
1024{
1025 int r, m;
1026
1027 for (r = 0; r < FIRST_PSEUDO_REGISTER; ++r)
1028 for (m = 0; m < NUM_MACHINE_MODES; ++m)
1029 if (rs6000_hard_regno_mode_ok (r, m))
1030 rs6000_hard_regno_mode_ok_p[m][r] = true;
1031}
1032
c1e55850
GK		 1033/* If not otherwise specified by a target, make 'long double' equivalent to
1034 'double'. */
1035
1036#ifndef RS6000_DEFAULT_LONG_DOUBLE_SIZE
1037#define RS6000_DEFAULT_LONG_DOUBLE_SIZE 64
1038#endif
1039
5248c961
RK		 1040/* Override command line options. Mostly we process the processor
1041 type and sometimes adjust other TARGET_ options. */
1042
1043void
d779d0dc 1044rs6000_override_options (const char *default_cpu)
5248c961 1045{
c4d38ccb 1046 size_t i, j;
8e3f41e7 1047 struct rs6000_cpu_select *ptr;
66188a7e 1048 int set_masks;
5248c961 1049
66188a7e 1050 /* Simplifications for entries below. */
85638c0d 1051
66188a7e
GK		 1052 enum {
1053 POWERPC_BASE_MASK = MASK_POWERPC | MASK_NEW_MNEMONICS,
1054 POWERPC_7400_MASK = POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_ALTIVEC
1055 };
85638c0d 1056
66188a7e
GK		 1057 /* This table occasionally claims that a processor does not support
1058 a particular feature even though it does, but the feature is slower
1059 than the alternative. Thus, it shouldn't be relied on as a
f676971a 1060 complete description of the processor's support.
66188a7e
GK		 1061
1062 Please keep this list in order, and don't forget to update the
1063 documentation in invoke.texi when adding a new processor or
1064 flag. */
5248c961
RK		 1065 static struct ptt
1066 {
8b60264b
KG		 1067 const char *const name; /* Canonical processor name. */
1068 const enum processor_type processor; /* Processor type enum value. */
1069 const int target_enable; /* Target flags to enable. */
8b60264b 1070 } const processor_target_table[]
66188a7e 1071 = {{"401", PROCESSOR_PPC403, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
49a0b204 1072 {"403", PROCESSOR_PPC403,
66188a7e
GK		 1073 POWERPC_BASE_MASK | MASK_SOFT_FLOAT | MASK_STRICT_ALIGN},
1074 {"405", PROCESSOR_PPC405, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1075 {"405fp", PROCESSOR_PPC405, POWERPC_BASE_MASK},
1076 {"440", PROCESSOR_PPC440, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1077 {"440fp", PROCESSOR_PPC440, POWERPC_BASE_MASK},
1078 {"505", PROCESSOR_MPCCORE, POWERPC_BASE_MASK},
5248c961 1079 {"601", PROCESSOR_PPC601,
66188a7e
GK		 1080 MASK_POWER | POWERPC_BASE_MASK | MASK_MULTIPLE | MASK_STRING},
1081 {"602", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1082 {"603", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1083 {"603e", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1084 {"604", PROCESSOR_PPC604, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1085 {"604e", PROCESSOR_PPC604e, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
7ddb6568
AM		 1086 {"620", PROCESSOR_PPC620,
1087 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
1088 {"630", PROCESSOR_PPC630,
1089 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
66188a7e
GK		 1090 {"740", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1091 {"7400", PROCESSOR_PPC7400, POWERPC_7400_MASK},
1092 {"7450", PROCESSOR_PPC7450, POWERPC_7400_MASK},
1093 {"750", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1094 {"801", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1095 {"821", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1096 {"823", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1097 {"8540", PROCESSOR_PPC8540, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
4d4cbc0e
AH		 1098 /* 8548 has a dummy entry for now. */
1099 {"8548", PROCESSOR_PPC8540, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
66188a7e 1100 {"860", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
7177e720 1101 {"970", PROCESSOR_POWER4,
66188a7e
GK		 1102 POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64},
1103 {"common", PROCESSOR_COMMON, MASK_NEW_MNEMONICS},
1104 {"ec603e", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1105 {"G3", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1106 {"G4", PROCESSOR_PPC7450, POWERPC_7400_MASK},
49ffe578 1107 {"G5", PROCESSOR_POWER4,
66188a7e
GK		 1108 POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64},
1109 {"power", PROCESSOR_POWER, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1110 {"power2", PROCESSOR_POWER,
1111 MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING},
7ddb6568
AM		 1112 {"power3", PROCESSOR_PPC630,
1113 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
1114 {"power4", PROCESSOR_POWER4,
fc091c8e 1115 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POWERPC64},
ec507f2d 1116 {"power5", PROCESSOR_POWER5,
fc091c8e 1117 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POWERPC64},
66188a7e
GK		 1118 {"powerpc", PROCESSOR_POWERPC, POWERPC_BASE_MASK},
1119 {"powerpc64", PROCESSOR_POWERPC64,
98c41d98 1120 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
66188a7e
GK		 1121 {"rios", PROCESSOR_RIOS1, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1122 {"rios1", PROCESSOR_RIOS1, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1123 {"rios2", PROCESSOR_RIOS2,
1124 MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING},
1125 {"rsc", PROCESSOR_PPC601, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1126 {"rsc1", PROCESSOR_PPC601, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
98c41d98
DE		 1127 {"rs64", PROCESSOR_RS64A,
1128 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64}
66188a7e 1129 };
5248c961 1130
ca7558fc 1131 const size_t ptt_size = ARRAY_SIZE (processor_target_table);
5248c961 1132
66188a7e
GK		 1133 /* Some OSs don't support saving the high part of 64-bit registers on
1134 context switch. Other OSs don't support saving Altivec registers.
1135 On those OSs, we don't touch the MASK_POWERPC64 or MASK_ALTIVEC
1136 settings; if the user wants either, the user must explicitly specify
1137 them and we won't interfere with the user's specification. */
1138
1139 enum {
1140 POWER_MASKS = MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING,
f676971a 1141 POWERPC_MASKS = (POWERPC_BASE_MASK | MASK_PPC_GPOPT
66188a7e
GK		 1142 | MASK_PPC_GFXOPT | MASK_POWERPC64 | MASK_ALTIVEC
1143 | MASK_MFCRF)
1144 };
0d1fbc8c
AH		 1145
1146 rs6000_init_hard_regno_mode_ok ();
1147
c4ad648e 1148 set_masks = POWER_MASKS | POWERPC_MASKS | MASK_SOFT_FLOAT;
66188a7e
GK		 1149#ifdef OS_MISSING_POWERPC64
1150 if (OS_MISSING_POWERPC64)
1151 set_masks &= ~MASK_POWERPC64;
1152#endif
1153#ifdef OS_MISSING_ALTIVEC
1154 if (OS_MISSING_ALTIVEC)
1155 set_masks &= ~MASK_ALTIVEC;
1156#endif
1157
768875a8
AM		 1158 /* Don't override by the processor default if given explicitly. */
1159 set_masks &= ~target_flags_explicit;
957211c3 1160
a4f6c312 1161 /* Identify the processor type. */
8e3f41e7 1162 rs6000_select[0].string = default_cpu;
3cb999d8 1163 rs6000_cpu = TARGET_POWERPC64 ? PROCESSOR_DEFAULT64 : PROCESSOR_DEFAULT;
8e3f41e7 1164
b6a1cbae 1165 for (i = 0; i < ARRAY_SIZE (rs6000_select); i++)
5248c961 1166 {
8e3f41e7
MM		 1167 ptr = &rs6000_select[i];
1168 if (ptr->string != (char *)0 && ptr->string[0] != '\0')
5248c961 1169 {
8e3f41e7
MM		 1170 for (j = 0; j < ptt_size; j++)
1171 if (! strcmp (ptr->string, processor_target_table[j].name))
1172 {
1173 if (ptr->set_tune_p)
1174 rs6000_cpu = processor_target_table[j].processor;
1175
1176 if (ptr->set_arch_p)
1177 {
66188a7e
GK		 1178 target_flags &= ~set_masks;
1179 target_flags |= (processor_target_table[j].target_enable
1180 & set_masks);
8e3f41e7
MM		 1181 }
1182 break;
1183 }
1184
4406229e 1185 if (j == ptt_size)
8e3f41e7 1186 error ("bad value (%s) for %s switch", ptr->string, ptr->name);
5248c961
RK		 1187 }
1188 }
8a61d227 1189
993f19a8 1190 if (TARGET_E500)
a3170dc6
AH		 1191 rs6000_isel = 1;
1192
dff9f1b6
DE		 1193 /* If we are optimizing big endian systems for space, use the load/store
1194 multiple and string instructions. */
ef792183 1195 if (BYTES_BIG_ENDIAN && optimize_size)
957211c3 1196 target_flags |= ~target_flags_explicit & (MASK_MULTIPLE | MASK_STRING);
938937d8 1197
a4f6c312
SS		 1198 /* Don't allow -mmultiple or -mstring on little endian systems
1199 unless the cpu is a 750, because the hardware doesn't support the
1200 instructions used in little endian mode, and causes an alignment
1201 trap. The 750 does not cause an alignment trap (except when the
1202 target is unaligned). */
bef84347 1203
b21fb038 1204 if (!BYTES_BIG_ENDIAN && rs6000_cpu != PROCESSOR_PPC750)
7e69e155
MM		 1205 {
1206 if (TARGET_MULTIPLE)
1207 {
1208 target_flags &= ~MASK_MULTIPLE;
b21fb038 1209 if ((target_flags_explicit & MASK_MULTIPLE) != 0)
d4ee4d25 1210 warning (0, "-mmultiple is not supported on little endian systems");
7e69e155
MM		 1211 }
1212
1213 if (TARGET_STRING)
1214 {
1215 target_flags &= ~MASK_STRING;
b21fb038 1216 if ((target_flags_explicit & MASK_STRING) != 0)
d4ee4d25 1217 warning (0, "-mstring is not supported on little endian systems");
7e69e155
MM		 1218 }
1219 }
3933e0e1 1220
38c1f2d7
MM		 1221 /* Set debug flags */
1222 if (rs6000_debug_name)
1223 {
bfc79d3b 1224 if (! strcmp (rs6000_debug_name, "all"))
38c1f2d7 1225 rs6000_debug_stack = rs6000_debug_arg = 1;
bfc79d3b 1226 else if (! strcmp (rs6000_debug_name, "stack"))
38c1f2d7 1227 rs6000_debug_stack = 1;
bfc79d3b 1228 else if (! strcmp (rs6000_debug_name, "arg"))
38c1f2d7
MM		 1229 rs6000_debug_arg = 1;
1230 else
c725bd79 1231 error ("unknown -mdebug-%s switch", rs6000_debug_name);
38c1f2d7
MM		 1232 }
1233
57ac7be9
AM		 1234 if (rs6000_traceback_name)
1235 {
1236 if (! strncmp (rs6000_traceback_name, "full", 4))
1237 rs6000_traceback = traceback_full;
1238 else if (! strncmp (rs6000_traceback_name, "part", 4))
1239 rs6000_traceback = traceback_part;
1240 else if (! strncmp (rs6000_traceback_name, "no", 2))
1241 rs6000_traceback = traceback_none;
1242 else
9e637a26 1243 error ("unknown -mtraceback arg %qs; expecting %<full%>, %<partial%> or %<none%>",
57ac7be9
AM		 1244 rs6000_traceback_name);
1245 }
1246
78f5898b
AH		 1247 if (!rs6000_explicit_options.long_double)
1248 rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE;
6fa3f289 1249
6d0ef01e
HP		 1250 /* Set Altivec ABI as default for powerpc64 linux. */
1251 if (TARGET_ELF && TARGET_64BIT)
1252 {
1253 rs6000_altivec_abi = 1;
78f5898b
AH		 1254#if TARGET_ALTIVEC_VRSAVE != 0
1255 TARGET_ALTIVEC_VRSAVE = 1;
1256#endif
6d0ef01e
HP		 1257 }
1258
594a51fe
SS		 1259 /* Set the Darwin64 ABI as default for 64-bit Darwin. */
1260 if (DEFAULT_ABI == ABI_DARWIN && TARGET_64BIT)
1261 {
1262 rs6000_darwin64_abi = 1;
9c7956fd 1263#if TARGET_MACHO
6ac49599 1264 darwin_one_byte_bool = 1;
9c7956fd 1265#endif
d9168963
SS		 1266 /* Default to natural alignment, for better performance. */
1267 rs6000_alignment_flags = MASK_ALIGN_NATURAL;
594a51fe
SS		 1268 }
1269
c4501e62
JJ		 1270 /* Handle -mtls-size option. */
1271 rs6000_parse_tls_size_option ();
1272
a7ae18e2
AH		 1273#ifdef SUBTARGET_OVERRIDE_OPTIONS
1274 SUBTARGET_OVERRIDE_OPTIONS;
1275#endif
1276#ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
1277 SUBSUBTARGET_OVERRIDE_OPTIONS;
1278#endif
4d4cbc0e
AH		 1279#ifdef SUB3TARGET_OVERRIDE_OPTIONS
1280 SUB3TARGET_OVERRIDE_OPTIONS;
1281#endif
a7ae18e2 1282
5da702b1
AH		 1283 if (TARGET_E500)
1284 {
e4463bf1
AH		 1285 if (TARGET_ALTIVEC)
1286 error ("AltiVec and E500 instructions cannot coexist");
1287
5da702b1
AH		 1288 /* The e500 does not have string instructions, and we set
1289 MASK_STRING above when optimizing for size. */
1290 if ((target_flags & MASK_STRING) != 0)
1291 target_flags = target_flags & ~MASK_STRING;
1292 }
1293 else if (rs6000_select[1].string != NULL)
1294 {
1295 /* For the powerpc-eabispe configuration, we set all these by
1296 default, so let's unset them if we manually set another
1297 CPU that is not the E500. */
78f5898b 1298 if (!rs6000_explicit_options.abi)
5da702b1 1299 rs6000_spe_abi = 0;
78f5898b 1300 if (!rs6000_explicit_options.spe)
5da702b1 1301 rs6000_spe = 0;
78f5898b 1302 if (!rs6000_explicit_options.float_gprs)
5da702b1 1303 rs6000_float_gprs = 0;
78f5898b 1304 if (!rs6000_explicit_options.isel)
5da702b1 1305 rs6000_isel = 0;
78f5898b 1306 if (!rs6000_explicit_options.long_double)
c1e55850 1307 rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE;
5da702b1 1308 }
b5044283 1309
ec507f2d
DE		 1310 rs6000_always_hint = (rs6000_cpu != PROCESSOR_POWER4
1311 && rs6000_cpu != PROCESSOR_POWER5);
1312 rs6000_sched_groups = (rs6000_cpu == PROCESSOR_POWER4
1313 || rs6000_cpu == PROCESSOR_POWER5);
1314
78f5898b
AH		 1315 /* ?? I see no need for this. This variable was always initialized to 0,
1316 except when explicitly set. It's not set in any .h file either.
ec507f2d
DE		 1317 rs6000_sched_restricted_insns_priority
1318 = (rs6000_sched_groups ? 1 : 0);
78f5898b 1319 */
79ae11c4 1320
569fa502 1321 /* Handle -msched-costly-dep option. */
78f5898b
AH		 1322 /* ?? Same goes for this. When would rs6000_sched_costly_dep ever have
1323 a nonzero value upon entry to this function. ??
ec507f2d
DE		 1324 rs6000_sched_costly_dep
1325 = (rs6000_sched_groups ? store_to_load_dep_costly : no_dep_costly);
78f5898b 1326 */
569fa502
DN		 1327 if (rs6000_sched_costly_dep_str)
1328 {
f676971a 1329 if (! strcmp (rs6000_sched_costly_dep_str, "no"))
c4ad648e 1330 rs6000_sched_costly_dep = no_dep_costly;
569fa502 1331 else if (! strcmp (rs6000_sched_costly_dep_str, "all"))
c4ad648e 1332 rs6000_sched_costly_dep = all_deps_costly;
569fa502 1333 else if (! strcmp (rs6000_sched_costly_dep_str, "true_store_to_load"))
c4ad648e 1334 rs6000_sched_costly_dep = true_store_to_load_dep_costly;
569fa502 1335 else if (! strcmp (rs6000_sched_costly_dep_str, "store_to_load"))
c4ad648e 1336 rs6000_sched_costly_dep = store_to_load_dep_costly;
f676971a 1337 else
c4ad648e 1338 rs6000_sched_costly_dep = atoi (rs6000_sched_costly_dep_str);
cbe26ab8
DN		 1339 }
1340
1341 /* Handle -minsert-sched-nops option. */
ec507f2d
DE		 1342 rs6000_sched_insert_nops
1343 = (rs6000_sched_groups ? sched_finish_regroup_exact : sched_finish_none);
cbe26ab8
DN		 1344 if (rs6000_sched_insert_nops_str)
1345 {
1346 if (! strcmp (rs6000_sched_insert_nops_str, "no"))
c4ad648e 1347 rs6000_sched_insert_nops = sched_finish_none;
cbe26ab8 1348 else if (! strcmp (rs6000_sched_insert_nops_str, "pad"))
c4ad648e 1349 rs6000_sched_insert_nops = sched_finish_pad_groups;
cbe26ab8 1350 else if (! strcmp (rs6000_sched_insert_nops_str, "regroup_exact"))
c4ad648e 1351 rs6000_sched_insert_nops = sched_finish_regroup_exact;
cbe26ab8 1352 else
c4ad648e 1353 rs6000_sched_insert_nops = atoi (rs6000_sched_insert_nops_str);
569fa502
DN		 1354 }
1355
c81bebd7 1356#ifdef TARGET_REGNAMES
a4f6c312
SS		 1357 /* If the user desires alternate register names, copy in the
1358 alternate names now. */
c81bebd7 1359 if (TARGET_REGNAMES)
4e135bdd 1360 memcpy (rs6000_reg_names, alt_reg_names, sizeof (rs6000_reg_names));
c81bebd7
MM		 1361#endif
1362
6fa3f289
ZW		 1363 /* Set TARGET_AIX_STRUCT_RET last, after the ABI is determined.
1364 If -maix-struct-return or -msvr4-struct-return was explicitly
1365 used, don't override with the ABI default. */
b21fb038 1366 if ((target_flags_explicit & MASK_AIX_STRUCT_RET) == 0)
6fa3f289
ZW		 1367 {
1368 if (DEFAULT_ABI == ABI_V4 && !DRAFT_V4_STRUCT_RET)
1369 target_flags = (target_flags & ~MASK_AIX_STRUCT_RET);
1370 else
1371 target_flags |= MASK_AIX_STRUCT_RET;
1372 }
1373
fcce224d
DE		 1374 if (TARGET_LONG_DOUBLE_128
1375 && (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN))
70a01792 1376 REAL_MODE_FORMAT (TFmode) = &ibm_extended_format;
fcce224d 1377
9ebbca7d
GK		 1378 /* Allocate an alias set for register saves & restores from stack. */
1379 rs6000_sr_alias_set = new_alias_set ();
1380
f676971a 1381 if (TARGET_TOC)
9ebbca7d 1382 ASM_GENERATE_INTERNAL_LABEL (toc_label_name, "LCTOC", 1);
71f123ca 1383
301d03af
RS		 1384 /* We can only guarantee the availability of DI pseudo-ops when
1385 assembling for 64-bit targets. */
ae6c1efd 1386 if (!TARGET_64BIT)
301d03af
RS		 1387 {
1388 targetm.asm_out.aligned_op.di = NULL;
1389 targetm.asm_out.unaligned_op.di = NULL;
1390 }
1391
1494c534
DE		 1392 /* Set branch target alignment, if not optimizing for size. */
1393 if (!optimize_size)
1394 {
1395 if (rs6000_sched_groups)
1396 {
1397 if (align_functions <= 0)
1398 align_functions = 16;
1399 if (align_jumps <= 0)
1400 align_jumps = 16;
1401 if (align_loops <= 0)
1402 align_loops = 16;
1403 }
1404 if (align_jumps_max_skip <= 0)
1405 align_jumps_max_skip = 15;
1406 if (align_loops_max_skip <= 0)
1407 align_loops_max_skip = 15;
1408 }
2792d578 1409
71f123ca
FS		 1410 /* Arrange to save and restore machine status around nested functions. */
1411 init_machine_status = rs6000_init_machine_status;
42ba5130
RH		 1412
1413 /* We should always be splitting complex arguments, but we can't break
1414 Linux and Darwin ABIs at the moment. For now, only AIX is fixed. */
18f63bfa 1415 if (DEFAULT_ABI != ABI_AIX)
42ba5130 1416 targetm.calls.split_complex_arg = NULL;
8b897cfa
RS		 1417
1418 /* Initialize rs6000_cost with the appropriate target costs. */
1419 if (optimize_size)
1420 rs6000_cost = TARGET_POWERPC64 ? &size64_cost : &size32_cost;
1421 else
1422 switch (rs6000_cpu)
1423 {
1424 case PROCESSOR_RIOS1:
1425 rs6000_cost = &rios1_cost;
1426 break;
1427
1428 case PROCESSOR_RIOS2:
1429 rs6000_cost = &rios2_cost;
1430 break;
1431
1432 case PROCESSOR_RS64A:
1433 rs6000_cost = &rs64a_cost;
1434 break;
1435
1436 case PROCESSOR_MPCCORE:
1437 rs6000_cost = &mpccore_cost;
1438 break;
1439
1440 case PROCESSOR_PPC403:
1441 rs6000_cost = &ppc403_cost;
1442 break;
1443
1444 case PROCESSOR_PPC405:
1445 rs6000_cost = &ppc405_cost;
1446 break;
1447
1448 case PROCESSOR_PPC440:
1449 rs6000_cost = &ppc440_cost;
1450 break;
1451
1452 case PROCESSOR_PPC601:
1453 rs6000_cost = &ppc601_cost;
1454 break;
1455
1456 case PROCESSOR_PPC603:
1457 rs6000_cost = &ppc603_cost;
1458 break;
1459
1460 case PROCESSOR_PPC604:
1461 rs6000_cost = &ppc604_cost;
1462 break;
1463
1464 case PROCESSOR_PPC604e:
1465 rs6000_cost = &ppc604e_cost;
1466 break;
1467
1468 case PROCESSOR_PPC620:
8b897cfa
RS		 1469 rs6000_cost = &ppc620_cost;
1470 break;
1471
f0517163
RS		 1472 case PROCESSOR_PPC630:
1473 rs6000_cost = &ppc630_cost;
1474 break;
1475
8b897cfa
RS		 1476 case PROCESSOR_PPC750:
1477 case PROCESSOR_PPC7400:
1478 rs6000_cost = &ppc750_cost;
1479 break;
1480
1481 case PROCESSOR_PPC7450:
1482 rs6000_cost = &ppc7450_cost;
1483 break;
1484
1485 case PROCESSOR_PPC8540:
1486 rs6000_cost = &ppc8540_cost;
1487 break;
1488
1489 case PROCESSOR_POWER4:
1490 case PROCESSOR_POWER5:
1491 rs6000_cost = &power4_cost;
1492 break;
1493
1494 default:
37409796 1495 gcc_unreachable ();
8b897cfa 1496 }
5248c961 1497}
5accd822 1498
7ccf35ed
DN		 1499/* Implement targetm.vectorize.builtin_mask_for_load. */
1500static tree
1501rs6000_builtin_mask_for_load (void)
1502{
1503 if (TARGET_ALTIVEC)
1504 return altivec_builtin_mask_for_load;
1505 else
1506 return 0;
1507}
1508
5da702b1
AH		 1509/* Handle generic options of the form -mfoo=yes/no.
1510 NAME is the option name.
1511 VALUE is the option value.
1512 FLAG is the pointer to the flag where to store a 1 or 0, depending on
1513 whether the option value is 'yes' or 'no' respectively. */
993f19a8 1514static void
5da702b1 1515rs6000_parse_yes_no_option (const char *name, const char *value, int *flag)
993f19a8 1516{
5da702b1 1517 if (value == 0)
993f19a8 1518 return;
5da702b1
AH		 1519 else if (!strcmp (value, "yes"))
1520 *flag = 1;
1521 else if (!strcmp (value, "no"))
1522 *flag = 0;
08b57fb3 1523 else
5da702b1 1524 error ("unknown -m%s= option specified: '%s'", name, value);
08b57fb3
AH		 1525}
1526
c4501e62
JJ		 1527/* Validate and record the size specified with the -mtls-size option. */
1528
1529static void
863d938c 1530rs6000_parse_tls_size_option (void)
c4501e62
JJ		 1531{
1532 if (rs6000_tls_size_string == 0)
1533 return;
1534 else if (strcmp (rs6000_tls_size_string, "16") == 0)
1535 rs6000_tls_size = 16;
1536 else if (strcmp (rs6000_tls_size_string, "32") == 0)
1537 rs6000_tls_size = 32;
1538 else if (strcmp (rs6000_tls_size_string, "64") == 0)
1539 rs6000_tls_size = 64;
1540 else
9e637a26 1541 error ("bad value %qs for -mtls-size switch", rs6000_tls_size_string);
c4501e62
JJ		 1542}
1543
5accd822 1544void
a2369ed3 1545optimization_options (int level ATTRIBUTE_UNUSED, int size ATTRIBUTE_UNUSED)
5accd822 1546{
5accd822 1547}
78f5898b
AH		 1548
1549/* Implement TARGET_HANDLE_OPTION. */
1550
1551static bool
1552rs6000_handle_option (size_t code, const char *arg, int value)
1553{
1554 switch (code)
1555 {
1556 case OPT_mno_power:
1557 target_flags &= ~(MASK_POWER | MASK_POWER2
1558 | MASK_MULTIPLE | MASK_STRING);
1559 break;
1560 case OPT_mno_powerpc:
1561 target_flags &= ~(MASK_POWERPC | MASK_PPC_GPOPT
1562 | MASK_PPC_GFXOPT | MASK_POWERPC64);
1563 break;
1564 case OPT_mfull_toc:
1565 target_flags &= ~(MASK_MINIMAL_TOC | MASK_NO_FP_IN_TOC
1566 | MASK_NO_SUM_IN_TOC);
1567#ifdef TARGET_USES_SYSV4_OPT
1568 /* Note, V.4 no longer uses a normal TOC, so make -mfull-toc, be
1569 just the same as -mminimal-toc. */
1570 target_flags |= MASK_MINIMAL_TOC;
1571#endif
1572 break;
1573
1574#ifdef TARGET_USES_SYSV4_OPT
1575 case OPT_mtoc:
1576 /* Make -mtoc behave like -mminimal-toc. */
1577 target_flags |= MASK_MINIMAL_TOC;
1578 break;
1579#endif
1580
1581#ifdef TARGET_USES_AIX64_OPT
1582 case OPT_maix64:
1583#else
1584 case OPT_m64:
1585#endif
1586 target_flags |= MASK_POWERPC64 | MASK_POWERPC | MASK_PPC_GFXOPT;
1587 break;
1588
1589#ifdef TARGET_USES_AIX64_OPT
1590 case OPT_maix32:
1591#else
1592 case OPT_m32:
1593#endif
1594 target_flags &= ~MASK_POWERPC64;
1595 break;
1596
1597 case OPT_minsert_sched_nops_:
1598 rs6000_sched_insert_nops_str = arg;
1599 break;
1600
1601 case OPT_mminimal_toc:
1602 if (value == 1)
1603 {
1604 target_flags &= ~MASK_NO_FP_IN_TOC;
1605 target_flags &= ~MASK_NO_SUM_IN_TOC;
1606 }
1607 break;
1608
1609 case OPT_mpower:
1610 if (value == 1)
1611 target_flags |= (MASK_MULTIPLE | MASK_STRING);
1612 break;
1613
1614 case OPT_mpower2:
1615 if (value == 1)
1616 target_flags |= (MASK_POWER | MASK_MULTIPLE | MASK_STRING);
1617 break;
1618
1619 case OPT_mpowerpc_gpopt:
1620 case OPT_mpowerpc_gfxopt:
1621 if (value == 1)
1622 target_flags |= MASK_POWERPC;
1623 break;
1624
1625#if TARGET_ALTIVEC_VRSAVE != 0
1626 case OPT_mvrsave_:
1627 rs6000_parse_yes_no_option ("vrsave", arg, &(TARGET_ALTIVEC_VRSAVE));
1628 break;
1629#endif
1630
1631 case OPT_misel_:
1632 rs6000_explicit_options.isel = true;
1633 rs6000_parse_yes_no_option ("isel", arg, &(rs6000_isel));
1634 break;
1635
1636 case OPT_mspe_:
1637 rs6000_explicit_options.spe = true;
1638 rs6000_parse_yes_no_option ("spe", arg, &(rs6000_spe));
1639 /* No SPE means 64-bit long doubles, even if an E500. */
1640 if (!rs6000_spe)
1641 rs6000_long_double_type_size = 64;
1642 break;
1643
1644 case OPT_mdebug_:
1645 rs6000_debug_name = arg;
1646 break;
1647
1648#ifdef TARGET_USES_SYSV4_OPT
1649 case OPT_mcall_:
1650 rs6000_abi_name = arg;
1651 break;
1652
1653 case OPT_msdata_:
1654 rs6000_sdata_name = arg;
1655 break;
1656
1657 case OPT_mtls_size_:
1658 rs6000_tls_size_string = arg;
1659 break;
1660
1661 case OPT_mrelocatable:
1662 if (value == 1)
1663 target_flags |= MASK_MINIMAL_TOC | MASK_NO_FP_IN_TOC;
1664 break;
1665
1666 case OPT_mrelocatable_lib:
1667 if (value == 1)
1668 target_flags |= MASK_RELOCATABLE | MASK_MINIMAL_TOC
1669 | MASK_NO_FP_IN_TOC;
1670 else
1671 target_flags &= ~MASK_RELOCATABLE;
1672 break;
1673#endif
1674
1675 case OPT_mabi_:
1676 rs6000_explicit_options.abi = true;
1677 if (!strcmp (arg, "altivec"))
1678 {
1679 rs6000_altivec_abi = 1;
1680 rs6000_spe_abi = 0;
1681 }
1682 else if (! strcmp (arg, "no-altivec"))
1683 rs6000_altivec_abi = 0;
1684 else if (! strcmp (arg, "spe"))
1685 {
1686 rs6000_spe_abi = 1;
1687 rs6000_altivec_abi = 0;
1688 if (!TARGET_SPE_ABI)
1689 error ("not configured for ABI: '%s'", arg);
1690 }
1691 else if (! strcmp (arg, "no-spe"))
1692 rs6000_spe_abi = 0;
1693
1694 /* These are here for testing during development only, do not
1695 document in the manual please. */
1696 else if (! strcmp (arg, "d64"))
1697 {
1698 rs6000_darwin64_abi = 1;
1699 warning (0, "Using darwin64 ABI");
1700 }
1701 else if (! strcmp (arg, "d32"))
1702 {
1703 rs6000_darwin64_abi = 0;
1704 warning (0, "Using old darwin ABI");
1705 }
1706
1707 else
1708 {
1709 error ("unknown ABI specified: '%s'", arg);
1710 return false;
1711 }
1712 break;
1713
1714 case OPT_mcpu_:
1715 rs6000_select[1].string = arg;
1716 break;
1717
1718 case OPT_mtune_:
1719 rs6000_select[2].string = arg;
1720 break;
1721
1722 case OPT_mtraceback_:
1723 rs6000_traceback_name = arg;
1724 break;
1725
1726 case OPT_mfloat_gprs_:
1727 rs6000_explicit_options.float_gprs = true;
1728 if (! strcmp (arg, "yes") || ! strcmp (arg, "single"))
1729 rs6000_float_gprs = 1;
1730 else if (! strcmp (arg, "double"))
1731 rs6000_float_gprs = 2;
1732 else if (! strcmp (arg, "no"))
1733 rs6000_float_gprs = 0;
1734 else
1735 {
1736 error ("invalid option for -mfloat-gprs: '%s'", arg);
1737 return false;
1738 }
1739 break;
1740
1741 case OPT_mlong_double_:
1742 rs6000_explicit_options.long_double = true;
1743 rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE;
1744 if (value != 64 && value != 128)
1745 {
1746 error ("Unknown switch -mlong-double-%s", arg);
1747 rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE;
1748 return false;
1749 }
1750 else
1751 rs6000_long_double_type_size = value;
1752 break;
1753
1754 case OPT_msched_costly_dep_:
1755 rs6000_sched_costly_dep_str = arg;
1756 break;
1757
1758 case OPT_malign_:
1759 rs6000_explicit_options.alignment = true;
1760 if (! strcmp (arg, "power"))
1761 {
1762 /* On 64-bit Darwin, power alignment is ABI-incompatible with
1763 some C library functions, so warn about it. The flag may be
1764 useful for performance studies from time to time though, so
1765 don't disable it entirely. */
1766 if (DEFAULT_ABI == ABI_DARWIN && TARGET_64BIT)
1767 warning (0, "-malign-power is not supported for 64-bit Darwin;"
1768 " it is incompatible with the installed C and C++ libraries");
1769 rs6000_alignment_flags = MASK_ALIGN_POWER;
1770 }
1771 else if (! strcmp (arg, "natural"))
1772 rs6000_alignment_flags = MASK_ALIGN_NATURAL;
1773 else
1774 {
1775 error ("unknown -malign-XXXXX option specified: '%s'", arg);
1776 return false;
1777 }
1778 break;
1779 }
1780 return true;
1781}
3cfa4909
MM		 1782\f
1783/* Do anything needed at the start of the asm file. */
1784
1bc7c5b6 1785static void
863d938c 1786rs6000_file_start (void)
3cfa4909 1787{
c4d38ccb 1788 size_t i;
3cfa4909 1789 char buffer[80];
d330fd93 1790 const char *start = buffer;
3cfa4909 1791 struct rs6000_cpu_select *ptr;
1bc7c5b6
ZW		 1792 const char *default_cpu = TARGET_CPU_DEFAULT;
1793 FILE *file = asm_out_file;
1794
1795 default_file_start ();
1796
1797#ifdef TARGET_BI_ARCH
1798 if ((TARGET_DEFAULT ^ target_flags) & MASK_64BIT)
1799 default_cpu = 0;
1800#endif
3cfa4909
MM		 1801
1802 if (flag_verbose_asm)
1803 {
1804 sprintf (buffer, "\n%s rs6000/powerpc options:", ASM_COMMENT_START);
1805 rs6000_select[0].string = default_cpu;
1806
b6a1cbae 1807 for (i = 0; i < ARRAY_SIZE (rs6000_select); i++)
3cfa4909
MM		 1808 {
1809 ptr = &rs6000_select[i];
1810 if (ptr->string != (char *)0 && ptr->string[0] != '\0')
1811 {
1812 fprintf (file, "%s %s%s", start, ptr->name, ptr->string);
1813 start = "";
1814 }
1815 }
1816
b91da81f 1817#ifdef USING_ELFOS_H
3cfa4909
MM		 1818 switch (rs6000_sdata)
1819 {
1820 case SDATA_NONE: fprintf (file, "%s -msdata=none", start); start = ""; break;
1821 case SDATA_DATA: fprintf (file, "%s -msdata=data", start); start = ""; break;
1822 case SDATA_SYSV: fprintf (file, "%s -msdata=sysv", start); start = ""; break;
1823 case SDATA_EABI: fprintf (file, "%s -msdata=eabi", start); start = ""; break;
1824 }
1825
1826 if (rs6000_sdata && g_switch_value)
1827 {
307b599c
MK		 1828 fprintf (file, "%s -G " HOST_WIDE_INT_PRINT_UNSIGNED, start,
1829 g_switch_value);
3cfa4909
MM		 1830 start = "";
1831 }
1832#endif
1833
1834 if (*start == '\0')
949ea356 1835 putc ('\n', file);
3cfa4909 1836 }
b723e82f
JJ		 1837
1838 if (DEFAULT_ABI == ABI_AIX || (TARGET_ELF && flag_pic == 2))
1839 {
1840 toc_section ();
1841 text_section ();
1842 }
3cfa4909 1843}
c4e18b1c 1844
5248c961 1845\f
a0ab749a 1846/* Return nonzero if this function is known to have a null epilogue. */
9878760c
RK		 1847
1848int
863d938c 1849direct_return (void)
9878760c 1850{
4697a36c
MM		 1851 if (reload_completed)
1852 {
1853 rs6000_stack_t *info = rs6000_stack_info ();
1854
1855 if (info->first_gp_reg_save == 32
1856 && info->first_fp_reg_save == 64
00b960c7 1857 && info->first_altivec_reg_save == LAST_ALTIVEC_REGNO + 1
c81fc13e
DE		 1858 && ! info->lr_save_p
1859 && ! info->cr_save_p
00b960c7 1860 && info->vrsave_mask == 0
c81fc13e 1861 && ! info->push_p)
4697a36c
MM		 1862 return 1;
1863 }
1864
1865 return 0;
9878760c
RK		 1866}
1867
4e74d8ec
MM		 1868/* Return the number of instructions it takes to form a constant in an
1869 integer register. */
1870
48d72335 1871int
a2369ed3 1872num_insns_constant_wide (HOST_WIDE_INT value)
4e74d8ec
MM		 1873{
1874 /* signed constant loadable with {cal|addi} */
5f59ecb7 1875 if (CONST_OK_FOR_LETTER_P (value, 'I'))
0865c631
GK		 1876 return 1;
1877
4e74d8ec 1878 /* constant loadable with {cau|addis} */
5f59ecb7 1879 else if (CONST_OK_FOR_LETTER_P (value, 'L'))
4e74d8ec
MM		 1880 return 1;
1881
5f59ecb7 1882#if HOST_BITS_PER_WIDE_INT == 64
c81fc13e 1883 else if (TARGET_POWERPC64)
4e74d8ec 1884 {
a65c591c
DE		 1885 HOST_WIDE_INT low = ((value & 0xffffffff) ^ 0x80000000) - 0x80000000;
1886 HOST_WIDE_INT high = value >> 31;
4e74d8ec 1887
a65c591c 1888 if (high == 0 || high == -1)
4e74d8ec
MM		 1889 return 2;
1890
a65c591c 1891 high >>= 1;
4e74d8ec 1892
a65c591c 1893 if (low == 0)
4e74d8ec 1894 return num_insns_constant_wide (high) + 1;
4e74d8ec
MM		 1895 else
1896 return (num_insns_constant_wide (high)
e396202a 1897 + num_insns_constant_wide (low) + 1);
4e74d8ec
MM		 1898 }
1899#endif
1900
1901 else
1902 return 2;
1903}
1904
1905int
a2369ed3 1906num_insns_constant (rtx op, enum machine_mode mode)
4e74d8ec 1907{
37409796
NS		 1908 HOST_WIDE_INT low, high;
1909
1910 switch (GET_CODE (op))
0d30d435 1911 {
37409796 1912 case CONST_INT:
0d30d435 1913#if HOST_BITS_PER_WIDE_INT == 64
4e2c1c44
DE		 1914 if ((INTVAL (op) >> 31) != 0 && (INTVAL (op) >> 31) != -1
1915 && mask64_operand (op, mode))
c4ad648e 1916 return 2;
0d30d435
DE		 1917 else
1918#endif
1919 return num_insns_constant_wide (INTVAL (op));
4e74d8ec 1920
37409796
NS		 1921 case CONST_DOUBLE:
1922 if (mode == SFmode)
1923 {
1924 long l;
1925 REAL_VALUE_TYPE rv;
1926
1927 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
1928 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
1929 return num_insns_constant_wide ((HOST_WIDE_INT) l);
1930 }
a260abc9 1931
37409796
NS		 1932 if (mode == VOIDmode || mode == DImode)
1933 {
1934 high = CONST_DOUBLE_HIGH (op);
1935 low = CONST_DOUBLE_LOW (op);
1936 }
1937 else
1938 {
1939 long l[2];
1940 REAL_VALUE_TYPE rv;
1941
1942 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
1943 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
1944 high = l[WORDS_BIG_ENDIAN == 0];
1945 low = l[WORDS_BIG_ENDIAN != 0];
1946 }
47ad8c61 1947
37409796
NS		 1948 if (TARGET_32BIT)
1949 return (num_insns_constant_wide (low)
1950 + num_insns_constant_wide (high));
1951 else
1952 {
1953 if ((high == 0 && low >= 0)
1954 || (high == -1 && low < 0))
1955 return num_insns_constant_wide (low);
1956
1957 else if (mask64_operand (op, mode))
1958 return 2;
1959
1960 else if (low == 0)
1961 return num_insns_constant_wide (high) + 1;
1962
1963 else
1964 return (num_insns_constant_wide (high)
1965 + num_insns_constant_wide (low) + 1);
1966 }
1967
1968 default:
1969 gcc_unreachable ();
4e74d8ec 1970 }
4e74d8ec
MM		 1971}
1972
effa5d5d 1973/* Returns the constant for the splat instruction, if exists. */
452a7d36 1974
48d72335 1975int
452a7d36
HP		 1976easy_vector_splat_const (int cst, enum machine_mode mode)
1977{
f676971a 1978 switch (mode)
452a7d36
HP		 1979 {
1980 case V4SImode:
f676971a
EC		 1981 if (EASY_VECTOR_15 (cst)
1982 || EASY_VECTOR_15_ADD_SELF (cst))
452a7d36
HP		 1983 return cst;
1984 if ((cst & 0xffff) != ((cst >> 16) & 0xffff))
1985 break;
1986 cst = cst >> 16;
c4ad648e
AM		 1987 /* Fall thru */
1988
452a7d36 1989 case V8HImode:
f676971a
EC		 1990 if (EASY_VECTOR_15 (cst)
1991 || EASY_VECTOR_15_ADD_SELF (cst))
452a7d36
HP		 1992 return cst;
1993 if ((cst & 0xff) != ((cst >> 8) & 0xff))
1994 break;
1995 cst = cst >> 8;
c4ad648e
AM		 1996 /* Fall thru */
1997
452a7d36 1998 case V16QImode:
c4ad648e
AM		 1999 if (EASY_VECTOR_15 (cst)
2000 || EASY_VECTOR_15_ADD_SELF (cst))
2001 return cst;
f676971a 2002 default:
452a7d36
HP		 2003 break;
2004 }
2005 return 0;
2006}
2007
72ac76be 2008/* Return nonzero if all elements of a vector have the same value. */
69ef87e2 2009
48d72335 2010int
a2369ed3 2011easy_vector_same (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
d744e06e
AH		 2012{
2013 int units, i, cst;
2014
2015 units = CONST_VECTOR_NUNITS (op);
2016
2017 cst = INTVAL (CONST_VECTOR_ELT (op, 0));
2018 for (i = 1; i < units; ++i)
2019 if (INTVAL (CONST_VECTOR_ELT (op, i)) != cst)
2020 break;
452a7d36 2021 if (i == units && easy_vector_splat_const (cst, mode))
d744e06e
AH		 2022 return 1;
2023 return 0;
2024}
2025
452a7d36 2026/* Generate easy_vector_constant out of a easy_vector_constant_add_self. */
d744e06e 2027
f676971a 2028rtx
452a7d36
HP		 2029gen_easy_vector_constant_add_self (rtx op)
2030{
2031 int i, units;
2032 rtvec v;
2033 units = GET_MODE_NUNITS (GET_MODE (op));
2034 v = rtvec_alloc (units);
2035
2036 for (i = 0; i < units; i++)
f676971a 2037 RTVEC_ELT (v, i) =
452a7d36
HP		 2038 GEN_INT (INTVAL (CONST_VECTOR_ELT (op, i)) >> 1);
2039 return gen_rtx_raw_CONST_VECTOR (GET_MODE (op), v);
d744e06e
AH		 2040}
2041
2042const char *
a2369ed3 2043output_vec_const_move (rtx *operands)
d744e06e
AH		 2044{
2045 int cst, cst2;
2046 enum machine_mode mode;
2047 rtx dest, vec;
2048
2049 dest = operands[0];
2050 vec = operands[1];
69ef87e2 2051
d744e06e
AH		 2052 cst = INTVAL (CONST_VECTOR_ELT (vec, 0));
2053 cst2 = INTVAL (CONST_VECTOR_ELT (vec, 1));
2054 mode = GET_MODE (dest);
69ef87e2 2055
d744e06e
AH		 2056 if (TARGET_ALTIVEC)
2057 {
2058 if (zero_constant (vec, mode))
2059 return "vxor %0,%0,%0";
37409796
NS		 2060
2061 gcc_assert (easy_vector_constant (vec, mode));
2062
2063 operands[1] = GEN_INT (cst);
2064 switch (mode)
98ef3137 2065 {
37409796
NS		 2066 case V4SImode:
2067 if (EASY_VECTOR_15 (cst))
d744e06e 2068 {
37409796
NS		 2069 operands[1] = GEN_INT (cst);
2070 return "vspltisw %0,%1";
2071 }
2072 else if (EASY_VECTOR_15_ADD_SELF (cst))
2073 return "#";
2074 cst = cst >> 16;
2075 /* Fall thru */
c4ad648e 2076
37409796
NS		 2077 case V8HImode:
2078 if (EASY_VECTOR_15 (cst))
2079 {
2080 operands[1] = GEN_INT (cst);
2081 return "vspltish %0,%1";
2082 }
2083 else if (EASY_VECTOR_15_ADD_SELF (cst))
2084 return "#";
2085 cst = cst >> 8;
2086 /* Fall thru */
c4ad648e 2087
37409796
NS		 2088 case V16QImode:
2089 if (EASY_VECTOR_15 (cst))
2090 {
2091 operands[1] = GEN_INT (cst);
2092 return "vspltisb %0,%1";
d744e06e 2093 }
37409796
NS		 2094 else if (EASY_VECTOR_15_ADD_SELF (cst))
2095 return "#";
2096
2097 default:
2098 gcc_unreachable ();
98ef3137 2099 }
69ef87e2
AH		 2100 }
2101
37409796
NS		 2102 gcc_assert (TARGET_SPE);
2103
2104 /* Vector constant 0 is handled as a splitter of V2SI, and in the
2105 pattern of V1DI, V4HI, and V2SF.
2106
2107 FIXME: We should probably return # and add post reload
2108 splitters for these, but this way is so easy ;-). */
2109 operands[1] = GEN_INT (cst);
2110 operands[2] = GEN_INT (cst2);
2111 if (cst == cst2)
2112 return "li %0,%1\n\tevmergelo %0,%0,%0";
2113 else
2114 return "li %0,%1\n\tevmergelo %0,%0,%0\n\tli %0,%2";
69ef87e2
AH		 2115}
2116
914c2e77 2117int
e1e2e653
NS		 2118mask64_1or2_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED,
2119 bool allow_one)
0ba1b2ff
AM		 2120{
2121 if (GET_CODE (op) == CONST_INT)
a260abc9 2122 {
0ba1b2ff 2123 HOST_WIDE_INT c, lsb;
e1e2e653
NS		 2124 bool one_ok;
2125
0ba1b2ff 2126 c = INTVAL (op);
a260abc9 2127
0ba1b2ff
AM		 2128 /* Disallow all zeros. */
2129 if (c == 0)
2130 return 0;
a260abc9 2131
e1e2e653
NS		 2132 /* We can use a single rlwinm insn if no upper bits of C are set
2133 AND there are zero, one or two transitions in the _whole_ of
2134 C. */
2135 one_ok = !(c & ~(HOST_WIDE_INT)0xffffffff);
2136
0ba1b2ff
AM		 2137 /* We don't change the number of transitions by inverting,
2138 so make sure we start with the LS bit zero. */
2139 if (c & 1)
2140 c = ~c;
a260abc9 2141
0ba1b2ff
AM		 2142 /* Find the first transition. */
2143 lsb = c & -c;
a260abc9 2144
0ba1b2ff
AM		 2145 /* Invert to look for a second transition. */
2146 c = ~c;
2147
2148 /* Erase first transition. */
2149 c &= -lsb;
2150
2151 /* Find the second transition. */
2152 lsb = c & -c;
2153
2154 /* Invert to look for a third transition. */
2155 c = ~c;
2156
2157 /* Erase second transition. */
2158 c &= -lsb;
2159
e1e2e653
NS		 2160 if (one_ok && !(allow_one || c))
2161 return 0;
2162
0ba1b2ff
AM		 2163 /* Find the third transition (if any). */
2164 lsb = c & -c;
2165
2166 /* Match if all the bits above are 1's (or c is zero). */
2167 return c == -lsb;
2168 }
2169 return 0;
2170}
2171
2172/* Generates shifts and masks for a pair of rldicl or rldicr insns to
2173 implement ANDing by the mask IN. */
2174void
a2369ed3 2175build_mask64_2_operands (rtx in, rtx *out)
0ba1b2ff
AM		 2176{
2177#if HOST_BITS_PER_WIDE_INT >= 64
2178 unsigned HOST_WIDE_INT c, lsb, m1, m2;
2179 int shift;
2180
37409796 2181 gcc_assert (GET_CODE (in) == CONST_INT);
0ba1b2ff
AM		 2182
2183 c = INTVAL (in);
2184 if (c & 1)
2185 {
2186 /* Assume c initially something like 0x00fff000000fffff. The idea
2187 is to rotate the word so that the middle ^^^^^^ group of zeros
2188 is at the MS end and can be cleared with an rldicl mask. We then
2189 rotate back and clear off the MS ^^ group of zeros with a
2190 second rldicl. */
2191 c = ~c; /* c == 0xff000ffffff00000 */
2192 lsb = c & -c; /* lsb == 0x0000000000100000 */
2193 m1 = -lsb; /* m1 == 0xfffffffffff00000 */
2194 c = ~c; /* c == 0x00fff000000fffff */
2195 c &= -lsb; /* c == 0x00fff00000000000 */
2196 lsb = c & -c; /* lsb == 0x0000100000000000 */
2197 c = ~c; /* c == 0xff000fffffffffff */
2198 c &= -lsb; /* c == 0xff00000000000000 */
2199 shift = 0;
2200 while ((lsb >>= 1) != 0)
2201 shift++; /* shift == 44 on exit from loop */
2202 m1 <<= 64 - shift; /* m1 == 0xffffff0000000000 */
2203 m1 = ~m1; /* m1 == 0x000000ffffffffff */
2204 m2 = ~c; /* m2 == 0x00ffffffffffffff */
a260abc9
DE		 2205 }
2206 else
0ba1b2ff
AM		 2207 {
2208 /* Assume c initially something like 0xff000f0000000000. The idea
2209 is to rotate the word so that the ^^^ middle group of zeros
2210 is at the LS end and can be cleared with an rldicr mask. We then
2211 rotate back and clear off the LS group of ^^^^^^^^^^ zeros with
2212 a second rldicr. */
2213 lsb = c & -c; /* lsb == 0x0000010000000000 */
2214 m2 = -lsb; /* m2 == 0xffffff0000000000 */
2215 c = ~c; /* c == 0x00fff0ffffffffff */
2216 c &= -lsb; /* c == 0x00fff00000000000 */
2217 lsb = c & -c; /* lsb == 0x0000100000000000 */
2218 c = ~c; /* c == 0xff000fffffffffff */
2219 c &= -lsb; /* c == 0xff00000000000000 */
2220 shift = 0;
2221 while ((lsb >>= 1) != 0)
2222 shift++; /* shift == 44 on exit from loop */
2223 m1 = ~c; /* m1 == 0x00ffffffffffffff */
2224 m1 >>= shift; /* m1 == 0x0000000000000fff */
2225 m1 = ~m1; /* m1 == 0xfffffffffffff000 */
2226 }
2227
2228 /* Note that when we only have two 0->1 and 1->0 transitions, one of the
2229 masks will be all 1's. We are guaranteed more than one transition. */
2230 out[0] = GEN_INT (64 - shift);
2231 out[1] = GEN_INT (m1);
2232 out[2] = GEN_INT (shift);
2233 out[3] = GEN_INT (m2);
2234#else
045572c7
GK		 2235 (void)in;
2236 (void)out;
37409796 2237 gcc_unreachable ();
0ba1b2ff 2238#endif
a260abc9
DE		 2239}
2240
54b695e7 2241/* Return TRUE if OP is an invalid SUBREG operation on the e500. */
48d72335
DE		 2242
2243bool
54b695e7
AH		 2244invalid_e500_subreg (rtx op, enum machine_mode mode)
2245{
2246 /* Reject (subreg:SI (reg:DF)). */
2247 if (GET_CODE (op) == SUBREG
2248 && mode == SImode
2249 && REG_P (SUBREG_REG (op))
2250 && GET_MODE (SUBREG_REG (op)) == DFmode)
2251 return true;
2252
2253 /* Reject (subreg:DF (reg:DI)). */
2254 if (GET_CODE (op) == SUBREG
2255 && mode == DFmode
2256 && REG_P (SUBREG_REG (op))
2257 && GET_MODE (SUBREG_REG (op)) == DImode)
2258 return true;
2259
2260 return false;
2261}
2262
95727fb8
AP		 2263/* Darwin, AIX increases natural record alignment to doubleword if the first
2264 field is an FP double while the FP fields remain word aligned. */
2265
19d66194 2266unsigned int
95727fb8
AP		 2267rs6000_special_round_type_align (tree type, int computed, int specified)
2268{
2269 tree field = TYPE_FIELDS (type);
95727fb8 2270
85962ac8
AP		 2271 /* Skip all non field decls */
2272 while (field != NULL && TREE_CODE (field) != FIELD_DECL)
95727fb8
AP		 2273 field = TREE_CHAIN (field);
2274
3ce5437a 2275 if (field == NULL || field == type || DECL_MODE (field) != DFmode)
95727fb8
AP		 2276 return MAX (computed, specified);
2277
2278 return MAX (MAX (computed, specified), 64);
2279}
2280
a4f6c312 2281/* Return 1 for an operand in small memory on V.4/eabi. */
7509c759
MM		 2282
2283int
f676971a 2284small_data_operand (rtx op ATTRIBUTE_UNUSED,
a2369ed3 2285 enum machine_mode mode ATTRIBUTE_UNUSED)
7509c759 2286{
38c1f2d7 2287#if TARGET_ELF
5f59ecb7 2288 rtx sym_ref;
7509c759 2289
d9407988 2290 if (rs6000_sdata == SDATA_NONE || rs6000_sdata == SDATA_DATA)
a54d04b7 2291 return 0;
a54d04b7 2292
f607bc57 2293 if (DEFAULT_ABI != ABI_V4)
7509c759
MM		 2294 return 0;
2295
88228c4b
MM		 2296 if (GET_CODE (op) == SYMBOL_REF)
2297 sym_ref = op;
2298
2299 else if (GET_CODE (op) != CONST
2300 || GET_CODE (XEXP (op, 0)) != PLUS
2301 || GET_CODE (XEXP (XEXP (op, 0), 0)) != SYMBOL_REF
2302 || GET_CODE (XEXP (XEXP (op, 0), 1)) != CONST_INT)
7509c759
MM		 2303 return 0;
2304
88228c4b 2305 else
dbf55e53
MM		 2306 {
2307 rtx sum = XEXP (op, 0);
2308 HOST_WIDE_INT summand;
2309
2310 /* We have to be careful here, because it is the referenced address
c4ad648e 2311 that must be 32k from _SDA_BASE_, not just the symbol. */
dbf55e53 2312 summand = INTVAL (XEXP (sum, 1));
307b599c 2313 if (summand < 0 || (unsigned HOST_WIDE_INT) summand > g_switch_value)
9390387d 2314 return 0;
dbf55e53
MM		 2315
2316 sym_ref = XEXP (sum, 0);
2317 }
88228c4b 2318
20bfcd69 2319 return SYMBOL_REF_SMALL_P (sym_ref);
d9407988
MM		 2320#else
2321 return 0;
2322#endif
7509c759 2323}
46c07df8 2324
3a1f863f 2325/* Return true if either operand is a general purpose register. */
46c07df8 2326
3a1f863f
DE		 2327bool
2328gpr_or_gpr_p (rtx op0, rtx op1)
46c07df8 2329{
3a1f863f
DE		 2330 return ((REG_P (op0) && INT_REGNO_P (REGNO (op0)))
2331 || (REG_P (op1) && INT_REGNO_P (REGNO (op1))));
46c07df8
HP		 2332}
2333
9ebbca7d 2334\f
4d588c14
RH		 2335/* Subroutines of rs6000_legitimize_address and rs6000_legitimate_address. */
2336
f676971a
EC		 2337static int
2338constant_pool_expr_1 (rtx op, int *have_sym, int *have_toc)
9ebbca7d 2339{
9390387d 2340 switch (GET_CODE (op))
9ebbca7d
GK		 2341 {
2342 case SYMBOL_REF:
c4501e62
JJ		 2343 if (RS6000_SYMBOL_REF_TLS_P (op))
2344 return 0;
2345 else if (CONSTANT_POOL_ADDRESS_P (op))
a4f6c312
SS		 2346 {
2347 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (op), Pmode))
2348 {
2349 *have_sym = 1;
2350 return 1;
2351 }
2352 else
2353 return 0;
2354 }
2355 else if (! strcmp (XSTR (op, 0), toc_label_name))
2356 {
2357 *have_toc = 1;
2358 return 1;
2359 }
2360 else
2361 return 0;
9ebbca7d
GK		 2362 case PLUS:
2363 case MINUS:
c1f11548
DE		 2364 return (constant_pool_expr_1 (XEXP (op, 0), have_sym, have_toc)
2365 && constant_pool_expr_1 (XEXP (op, 1), have_sym, have_toc));
9ebbca7d 2366 case CONST:
a4f6c312 2367 return constant_pool_expr_1 (XEXP (op, 0), have_sym, have_toc);
9ebbca7d 2368 case CONST_INT:
a4f6c312 2369 return 1;
9ebbca7d 2370 default:
a4f6c312 2371 return 0;
9ebbca7d
GK		 2372 }
2373}
2374
4d588c14 2375static bool
a2369ed3 2376constant_pool_expr_p (rtx op)
9ebbca7d
GK		 2377{
2378 int have_sym = 0;
2379 int have_toc = 0;
2380 return constant_pool_expr_1 (op, &have_sym, &have_toc) && have_sym;
2381}
2382
48d72335 2383bool
a2369ed3 2384toc_relative_expr_p (rtx op)
9ebbca7d 2385{
4d588c14
RH		 2386 int have_sym = 0;
2387 int have_toc = 0;
2388 return constant_pool_expr_1 (op, &have_sym, &have_toc) && have_toc;
2389}
2390
4d588c14 2391bool
a2369ed3 2392legitimate_constant_pool_address_p (rtx x)
4d588c14
RH		 2393{
2394 return (TARGET_TOC
2395 && GET_CODE (x) == PLUS
2396 && GET_CODE (XEXP (x, 0)) == REG
2397 && (TARGET_MINIMAL_TOC || REGNO (XEXP (x, 0)) == TOC_REGISTER)
2398 && constant_pool_expr_p (XEXP (x, 1)));
2399}
2400
2401static bool
a2369ed3 2402legitimate_small_data_p (enum machine_mode mode, rtx x)
4d588c14
RH		 2403{
2404 return (DEFAULT_ABI == ABI_V4
2405 && !flag_pic && !TARGET_TOC
2406 && (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST)
2407 && small_data_operand (x, mode));
2408}
2409
60cdabab
DE		 2410/* SPE offset addressing is limited to 5-bits worth of double words. */
2411#define SPE_CONST_OFFSET_OK(x) (((x) & ~0xf8) == 0)
2412
76d2b81d
DJ		 2413bool
2414rs6000_legitimate_offset_address_p (enum machine_mode mode, rtx x, int strict)
4d588c14
RH		 2415{
2416 unsigned HOST_WIDE_INT offset, extra;
2417
2418 if (GET_CODE (x) != PLUS)
2419 return false;
2420 if (GET_CODE (XEXP (x, 0)) != REG)
2421 return false;
2422 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict))
2423 return false;
60cdabab
DE		 2424 if (legitimate_constant_pool_address_p (x))
2425 return true;
4d588c14
RH		 2426 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
2427 return false;
2428
2429 offset = INTVAL (XEXP (x, 1));
2430 extra = 0;
2431 switch (mode)
2432 {
2433 case V16QImode:
2434 case V8HImode:
2435 case V4SFmode:
2436 case V4SImode:
2437 /* AltiVec vector modes. Only reg+reg addressing is valid here,
2438 which leaves the only valid constant offset of zero, which by
2439 canonicalization rules is also invalid. */
2440 return false;
2441
2442 case V4HImode:
2443 case V2SImode:
2444 case V1DImode:
2445 case V2SFmode:
2446 /* SPE vector modes. */
2447 return SPE_CONST_OFFSET_OK (offset);
2448
2449 case DFmode:
4d4cbc0e
AH		 2450 if (TARGET_E500_DOUBLE)
2451 return SPE_CONST_OFFSET_OK (offset);
2452
4d588c14 2453 case DImode:
54b695e7
AH		 2454 /* On e500v2, we may have:
2455
2456 (subreg:DF (mem:DI (plus (reg) (const_int))) 0).
2457
2458 Which gets addressed with evldd instructions. */
2459 if (TARGET_E500_DOUBLE)
2460 return SPE_CONST_OFFSET_OK (offset);
2461
3364872d 2462 if (mode == DFmode || !TARGET_POWERPC64)
4d588c14
RH		 2463 extra = 4;
2464 else if (offset & 3)
2465 return false;
2466 break;
2467
2468 case TFmode:
2469 case TImode:
3364872d 2470 if (mode == TFmode || !TARGET_POWERPC64)
4d588c14
RH		 2471 extra = 12;
2472 else if (offset & 3)
2473 return false;
2474 else
2475 extra = 8;
2476 break;
2477
2478 default:
2479 break;
2480 }
2481
b1917422
AM		 2482 offset += 0x8000;
2483 return (offset < 0x10000) && (offset + extra < 0x10000);
4d588c14
RH		 2484}
2485
2486static bool
a2369ed3 2487legitimate_indexed_address_p (rtx x, int strict)
4d588c14
RH		 2488{
2489 rtx op0, op1;
2490
2491 if (GET_CODE (x) != PLUS)
2492 return false;
850e8d3d 2493
4d588c14
RH		 2494 op0 = XEXP (x, 0);
2495 op1 = XEXP (x, 1);
2496
2497 if (!REG_P (op0) || !REG_P (op1))
2498 return false;
2499
2500 return ((INT_REG_OK_FOR_BASE_P (op0, strict)
2501 && INT_REG_OK_FOR_INDEX_P (op1, strict))
2502 || (INT_REG_OK_FOR_BASE_P (op1, strict)
2503 && INT_REG_OK_FOR_INDEX_P (op0, strict)));
9ebbca7d
GK		 2504}
2505
48d72335 2506inline bool
a2369ed3 2507legitimate_indirect_address_p (rtx x, int strict)
4d588c14
RH		 2508{
2509 return GET_CODE (x) == REG && INT_REG_OK_FOR_BASE_P (x, strict);
2510}
2511
48d72335 2512bool
4c81e946
FJ		 2513macho_lo_sum_memory_operand (rtx x, enum machine_mode mode)
2514{
c4ad648e 2515 if (!TARGET_MACHO || !flag_pic
9390387d 2516 || mode != SImode || GET_CODE (x) != MEM)
c4ad648e
AM		 2517 return false;
2518 x = XEXP (x, 0);
4c81e946
FJ		 2519
2520 if (GET_CODE (x) != LO_SUM)
2521 return false;
2522 if (GET_CODE (XEXP (x, 0)) != REG)
2523 return false;
2524 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), 0))
2525 return false;
2526 x = XEXP (x, 1);
2527
2528 return CONSTANT_P (x);
2529}
2530
4d588c14 2531static bool
a2369ed3 2532legitimate_lo_sum_address_p (enum machine_mode mode, rtx x, int strict)
4d588c14
RH		 2533{
2534 if (GET_CODE (x) != LO_SUM)
2535 return false;
2536 if (GET_CODE (XEXP (x, 0)) != REG)
2537 return false;
2538 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict))
2539 return false;
54b695e7
AH		 2540 /* Restrict addressing for DI because of our SUBREG hackery. */
2541 if (TARGET_E500_DOUBLE && (mode == DFmode || mode == DImode))
f82f556d 2542 return false;
4d588c14
RH		 2543 x = XEXP (x, 1);
2544
8622e235 2545 if (TARGET_ELF || TARGET_MACHO)
4d588c14 2546 {
a29077da 2547 if (DEFAULT_ABI != ABI_AIX && DEFAULT_ABI != ABI_DARWIN && flag_pic)
4d588c14
RH		 2548 return false;
2549 if (TARGET_TOC)
2550 return false;
2551 if (GET_MODE_NUNITS (mode) != 1)
2552 return false;
5e5f01b9 2553 if (GET_MODE_BITSIZE (mode) > 64
3c028f65
AM		 2554 || (GET_MODE_BITSIZE (mode) > 32 && !TARGET_POWERPC64
2555 && !(TARGET_HARD_FLOAT && TARGET_FPRS && mode == DFmode)))
4d588c14
RH		 2556 return false;
2557
2558 return CONSTANT_P (x);
2559 }
2560
2561 return false;
2562}
2563
2564
9ebbca7d
GK		 2565/* Try machine-dependent ways of modifying an illegitimate address
2566 to be legitimate. If we find one, return the new, valid address.
2567 This is used from only one place: `memory_address' in explow.c.
2568
a4f6c312
SS		 2569 OLDX is the address as it was before break_out_memory_refs was
2570 called. In some cases it is useful to look at this to decide what
2571 needs to be done.
9ebbca7d 2572
a4f6c312 2573 MODE is passed so that this function can use GO_IF_LEGITIMATE_ADDRESS.
9ebbca7d 2574
a4f6c312
SS		 2575 It is always safe for this function to do nothing. It exists to
2576 recognize opportunities to optimize the output.
9ebbca7d
GK		 2577
2578 On RS/6000, first check for the sum of a register with a constant
2579 integer that is out of range. If so, generate code to add the
2580 constant with the low-order 16 bits masked to the register and force
2581 this result into another register (this can be done with `cau').
2582 Then generate an address of REG+(CONST&0xffff), allowing for the
2583 possibility of bit 16 being a one.
2584
2585 Then check for the sum of a register and something not constant, try to
2586 load the other things into a register and return the sum. */
4d588c14 2587
9ebbca7d 2588rtx
a2369ed3
DJ		 2589rs6000_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
2590 enum machine_mode mode)
0ac081f6 2591{
c4501e62
JJ		 2592 if (GET_CODE (x) == SYMBOL_REF)
2593 {
2594 enum tls_model model = SYMBOL_REF_TLS_MODEL (x);
2595 if (model != 0)
2596 return rs6000_legitimize_tls_address (x, model);
2597 }
2598
f676971a 2599 if (GET_CODE (x) == PLUS
9ebbca7d
GK		 2600 && GET_CODE (XEXP (x, 0)) == REG
2601 && GET_CODE (XEXP (x, 1)) == CONST_INT
2602 && (unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 1)) + 0x8000) >= 0x10000)
f676971a 2603 {
9ebbca7d
GK		 2604 HOST_WIDE_INT high_int, low_int;
2605 rtx sum;
a65c591c
DE		 2606 low_int = ((INTVAL (XEXP (x, 1)) & 0xffff) ^ 0x8000) - 0x8000;
2607 high_int = INTVAL (XEXP (x, 1)) - low_int;
9ebbca7d
GK		 2608 sum = force_operand (gen_rtx_PLUS (Pmode, XEXP (x, 0),
2609 GEN_INT (high_int)), 0);
2610 return gen_rtx_PLUS (Pmode, sum, GEN_INT (low_int));
2611 }
f676971a 2612 else if (GET_CODE (x) == PLUS
9ebbca7d
GK		 2613 && GET_CODE (XEXP (x, 0)) == REG
2614 && GET_CODE (XEXP (x, 1)) != CONST_INT
6ac7bf2c 2615 && GET_MODE_NUNITS (mode) == 1
a3170dc6
AH		 2616 && ((TARGET_HARD_FLOAT && TARGET_FPRS)
2617 || TARGET_POWERPC64
54b695e7
AH		 2618 || (((mode != DImode && mode != DFmode) || TARGET_E500_DOUBLE)
2619 && mode != TFmode))
9ebbca7d
GK		 2620 && (TARGET_POWERPC64 || mode != DImode)
2621 && mode != TImode)
2622 {
2623 return gen_rtx_PLUS (Pmode, XEXP (x, 0),
2624 force_reg (Pmode, force_operand (XEXP (x, 1), 0)));
2625 }
0ac081f6
AH		 2626 else if (ALTIVEC_VECTOR_MODE (mode))
2627 {
2628 rtx reg;
2629
2630 /* Make sure both operands are registers. */
2631 if (GET_CODE (x) == PLUS)
9f85ed45 2632 return gen_rtx_PLUS (Pmode, force_reg (Pmode, XEXP (x, 0)),
0ac081f6
AH		 2633 force_reg (Pmode, XEXP (x, 1)));
2634
2635 reg = force_reg (Pmode, x);
2636 return reg;
2637 }
4d4cbc0e 2638 else if (SPE_VECTOR_MODE (mode)
54b695e7
AH		 2639 || (TARGET_E500_DOUBLE && (mode == DFmode
2640 || mode == DImode)))
a3170dc6 2641 {
54b695e7
AH		 2642 if (mode == DImode)
2643 return NULL_RTX;
a3170dc6
AH		 2644 /* We accept [reg + reg] and [reg + OFFSET]. */
2645
2646 if (GET_CODE (x) == PLUS)
c4ad648e
AM		 2647 {
2648 rtx op1 = XEXP (x, 0);
2649 rtx op2 = XEXP (x, 1);
a3170dc6 2650
c4ad648e 2651 op1 = force_reg (Pmode, op1);
a3170dc6 2652
c4ad648e
AM		 2653 if (GET_CODE (op2) != REG
2654 && (GET_CODE (op2) != CONST_INT
2655 || !SPE_CONST_OFFSET_OK (INTVAL (op2))))
2656 op2 = force_reg (Pmode, op2);
a3170dc6 2657
c4ad648e
AM		 2658 return gen_rtx_PLUS (Pmode, op1, op2);
2659 }
a3170dc6
AH		 2660
2661 return force_reg (Pmode, x);
2662 }
f1384257
AM		 2663 else if (TARGET_ELF
2664 && TARGET_32BIT
2665 && TARGET_NO_TOC
2666 && ! flag_pic
9ebbca7d 2667 && GET_CODE (x) != CONST_INT
f676971a 2668 && GET_CODE (x) != CONST_DOUBLE
9ebbca7d 2669 && CONSTANT_P (x)
6ac7bf2c
GK		 2670 && GET_MODE_NUNITS (mode) == 1
2671 && (GET_MODE_BITSIZE (mode) <= 32
a3170dc6 2672 || ((TARGET_HARD_FLOAT && TARGET_FPRS) && mode == DFmode)))
9ebbca7d
GK		 2673 {
2674 rtx reg = gen_reg_rtx (Pmode);
8a1977f3
GK		 2675 emit_insn (gen_elf_high (reg, x));
2676 return gen_rtx_LO_SUM (Pmode, reg, x);
9ebbca7d 2677 }
ee890fe2
SS		 2678 else if (TARGET_MACHO && TARGET_32BIT && TARGET_NO_TOC
2679 && ! flag_pic
ab82a49f
AP		 2680#if TARGET_MACHO
2681 && ! MACHO_DYNAMIC_NO_PIC_P
2682#endif
ee890fe2 2683 && GET_CODE (x) != CONST_INT
f676971a 2684 && GET_CODE (x) != CONST_DOUBLE
ee890fe2 2685 && CONSTANT_P (x)
f82f556d 2686 && ((TARGET_HARD_FLOAT && TARGET_FPRS) || mode != DFmode)
f676971a 2687 && mode != DImode
ee890fe2
SS		 2688 && mode != TImode)
2689 {
2690 rtx reg = gen_reg_rtx (Pmode);
8a1977f3
GK		 2691 emit_insn (gen_macho_high (reg, x));
2692 return gen_rtx_LO_SUM (Pmode, reg, x);
ee890fe2 2693 }
f676971a 2694 else if (TARGET_TOC
4d588c14 2695 && constant_pool_expr_p (x)
a9098fd0 2696 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x), Pmode))
9ebbca7d
GK		 2697 {
2698 return create_TOC_reference (x);
2699 }
2700 else
2701 return NULL_RTX;
2702}
258bfae2 2703
c973d557
JJ		 2704/* This is called from dwarf2out.c via ASM_OUTPUT_DWARF_DTPREL.
2705 We need to emit DTP-relative relocations. */
2706
2707void
2708rs6000_output_dwarf_dtprel (FILE *file, int size, rtx x)
2709{
2710 switch (size)
2711 {
2712 case 4:
2713 fputs ("\t.long\t", file);
2714 break;
2715 case 8:
2716 fputs (DOUBLE_INT_ASM_OP, file);
2717 break;
2718 default:
37409796 2719 gcc_unreachable ();
c973d557
JJ		 2720 }
2721 output_addr_const (file, x);
2722 fputs ("@dtprel+0x8000", file);
2723}
2724
c4501e62
JJ		 2725/* Construct the SYMBOL_REF for the tls_get_addr function. */
2726
2727static GTY(()) rtx rs6000_tls_symbol;
2728static rtx
863d938c 2729rs6000_tls_get_addr (void)
c4501e62
JJ		 2730{
2731 if (!rs6000_tls_symbol)
2732 rs6000_tls_symbol = init_one_libfunc ("__tls_get_addr");
2733
2734 return rs6000_tls_symbol;
2735}
2736
2737/* Construct the SYMBOL_REF for TLS GOT references. */
2738
2739static GTY(()) rtx rs6000_got_symbol;
2740static rtx
863d938c 2741rs6000_got_sym (void)
c4501e62
JJ		 2742{
2743 if (!rs6000_got_symbol)
2744 {
2745 rs6000_got_symbol = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
2746 SYMBOL_REF_FLAGS (rs6000_got_symbol) |= SYMBOL_FLAG_LOCAL;
2747 SYMBOL_REF_FLAGS (rs6000_got_symbol) |= SYMBOL_FLAG_EXTERNAL;
f676971a 2748 }
c4501e62
JJ		 2749
2750 return rs6000_got_symbol;
2751}
2752
2753/* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
2754 this (thread-local) address. */
2755
2756static rtx
a2369ed3 2757rs6000_legitimize_tls_address (rtx addr, enum tls_model model)
c4501e62
JJ		 2758{
2759 rtx dest, insn;
2760
2761 dest = gen_reg_rtx (Pmode);
2762 if (model == TLS_MODEL_LOCAL_EXEC && rs6000_tls_size == 16)
2763 {
2764 rtx tlsreg;
2765
2766 if (TARGET_64BIT)
2767 {
2768 tlsreg = gen_rtx_REG (Pmode, 13);
2769 insn = gen_tls_tprel_64 (dest, tlsreg, addr);
2770 }
2771 else
2772 {
2773 tlsreg = gen_rtx_REG (Pmode, 2);
2774 insn = gen_tls_tprel_32 (dest, tlsreg, addr);
2775 }
2776 emit_insn (insn);
2777 }
2778 else if (model == TLS_MODEL_LOCAL_EXEC && rs6000_tls_size == 32)
2779 {
2780 rtx tlsreg, tmp;
2781
2782 tmp = gen_reg_rtx (Pmode);
2783 if (TARGET_64BIT)
2784 {
2785 tlsreg = gen_rtx_REG (Pmode, 13);
2786 insn = gen_tls_tprel_ha_64 (tmp, tlsreg, addr);
2787 }
2788 else
2789 {
2790 tlsreg = gen_rtx_REG (Pmode, 2);
2791 insn = gen_tls_tprel_ha_32 (tmp, tlsreg, addr);
2792 }
2793 emit_insn (insn);
2794 if (TARGET_64BIT)
2795 insn = gen_tls_tprel_lo_64 (dest, tmp, addr);
2796 else
2797 insn = gen_tls_tprel_lo_32 (dest, tmp, addr);
2798 emit_insn (insn);
2799 }
2800 else
2801 {
2802 rtx r3, got, tga, tmp1, tmp2, eqv;
2803
2804 if (TARGET_64BIT)
2805 got = gen_rtx_REG (Pmode, TOC_REGISTER);
2806 else
2807 {
2808 if (flag_pic == 1)
2809 got = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
2810 else
2811 {
2812 rtx gsym = rs6000_got_sym ();
2813 got = gen_reg_rtx (Pmode);
2814 if (flag_pic == 0)
2815 rs6000_emit_move (got, gsym, Pmode);
2816 else
2817 {
ccbca5e4 2818 rtx tempLR, tmp3, mem;
c4501e62
JJ		 2819 rtx first, last;
2820
c4501e62
JJ		 2821 tempLR = gen_reg_rtx (Pmode);
2822 tmp1 = gen_reg_rtx (Pmode);
2823 tmp2 = gen_reg_rtx (Pmode);
2824 tmp3 = gen_reg_rtx (Pmode);
542a8afa 2825 mem = gen_const_mem (Pmode, tmp1);
c4501e62 2826
ccbca5e4 2827 first = emit_insn (gen_load_toc_v4_PIC_1b (tempLR, gsym));
c4501e62
JJ		 2828 emit_move_insn (tmp1, tempLR);
2829 emit_move_insn (tmp2, mem);
2830 emit_insn (gen_addsi3 (tmp3, tmp1, tmp2));
2831 last = emit_move_insn (got, tmp3);
2832 REG_NOTES (last) = gen_rtx_EXPR_LIST (REG_EQUAL, gsym,
2833 REG_NOTES (last));
2834 REG_NOTES (first) = gen_rtx_INSN_LIST (REG_LIBCALL, last,
2835 REG_NOTES (first));
2836 REG_NOTES (last) = gen_rtx_INSN_LIST (REG_RETVAL, first,
2837 REG_NOTES (last));
2838 }
2839 }
2840 }
2841
2842 if (model == TLS_MODEL_GLOBAL_DYNAMIC)
2843 {
2844 r3 = gen_rtx_REG (Pmode, 3);
2845 if (TARGET_64BIT)
2846 insn = gen_tls_gd_64 (r3, got, addr);
2847 else
2848 insn = gen_tls_gd_32 (r3, got, addr);
2849 start_sequence ();
2850 emit_insn (insn);
2851 tga = gen_rtx_MEM (Pmode, rs6000_tls_get_addr ());
2852 insn = gen_call_value (r3, tga, const0_rtx, const0_rtx);
2853 insn = emit_call_insn (insn);
2854 CONST_OR_PURE_CALL_P (insn) = 1;
2855 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), r3);
2856 insn = get_insns ();
2857 end_sequence ();
2858 emit_libcall_block (insn, dest, r3, addr);
2859 }
2860 else if (model == TLS_MODEL_LOCAL_DYNAMIC)
2861 {
2862 r3 = gen_rtx_REG (Pmode, 3);
2863 if (TARGET_64BIT)
2864 insn = gen_tls_ld_64 (r3, got);
2865 else
2866 insn = gen_tls_ld_32 (r3, got);
2867 start_sequence ();
2868 emit_insn (insn);
2869 tga = gen_rtx_MEM (Pmode, rs6000_tls_get_addr ());
2870 insn = gen_call_value (r3, tga, const0_rtx, const0_rtx);
2871 insn = emit_call_insn (insn);
2872 CONST_OR_PURE_CALL_P (insn) = 1;
2873 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), r3);
2874 insn = get_insns ();
2875 end_sequence ();
2876 tmp1 = gen_reg_rtx (Pmode);
2877 eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
2878 UNSPEC_TLSLD);
2879 emit_libcall_block (insn, tmp1, r3, eqv);
2880 if (rs6000_tls_size == 16)
2881 {
2882 if (TARGET_64BIT)
2883 insn = gen_tls_dtprel_64 (dest, tmp1, addr);
2884 else
2885 insn = gen_tls_dtprel_32 (dest, tmp1, addr);
2886 }
2887 else if (rs6000_tls_size == 32)
2888 {
2889 tmp2 = gen_reg_rtx (Pmode);
2890 if (TARGET_64BIT)
2891 insn = gen_tls_dtprel_ha_64 (tmp2, tmp1, addr);
2892 else
2893 insn = gen_tls_dtprel_ha_32 (tmp2, tmp1, addr);
2894 emit_insn (insn);
2895 if (TARGET_64BIT)
2896 insn = gen_tls_dtprel_lo_64 (dest, tmp2, addr);
2897 else
2898 insn = gen_tls_dtprel_lo_32 (dest, tmp2, addr);
2899 }
2900 else
2901 {
2902 tmp2 = gen_reg_rtx (Pmode);
2903 if (TARGET_64BIT)
2904 insn = gen_tls_got_dtprel_64 (tmp2, got, addr);
2905 else
2906 insn = gen_tls_got_dtprel_32 (tmp2, got, addr);
2907 emit_insn (insn);
2908 insn = gen_rtx_SET (Pmode, dest,
2909 gen_rtx_PLUS (Pmode, tmp2, tmp1));
2910 }
2911 emit_insn (insn);
2912 }
2913 else
2914 {
2915 /* IE, or 64 bit offset LE. */
2916 tmp2 = gen_reg_rtx (Pmode);
2917 if (TARGET_64BIT)
2918 insn = gen_tls_got_tprel_64 (tmp2, got, addr);
2919 else
2920 insn = gen_tls_got_tprel_32 (tmp2, got, addr);
2921 emit_insn (insn);
2922 if (TARGET_64BIT)
2923 insn = gen_tls_tls_64 (dest, tmp2, addr);
2924 else
2925 insn = gen_tls_tls_32 (dest, tmp2, addr);
2926 emit_insn (insn);
2927 }
2928 }
2929
2930 return dest;
2931}
2932
c4501e62
JJ		 2933/* Return 1 if X contains a thread-local symbol. */
2934
2935bool
a2369ed3 2936rs6000_tls_referenced_p (rtx x)
c4501e62 2937{
cd413cab
AP		 2938 if (! TARGET_HAVE_TLS)
2939 return false;
2940
c4501e62
JJ		 2941 return for_each_rtx (&x, &rs6000_tls_symbol_ref_1, 0);
2942}
2943
2944/* Return 1 if *X is a thread-local symbol. This is the same as
2945 rs6000_tls_symbol_ref except for the type of the unused argument. */
2946
9390387d 2947static int
a2369ed3 2948rs6000_tls_symbol_ref_1 (rtx *x, void *data ATTRIBUTE_UNUSED)
c4501e62
JJ		 2949{
2950 return RS6000_SYMBOL_REF_TLS_P (*x);
2951}
2952
24ea750e
DJ		 2953/* The convention appears to be to define this wherever it is used.
2954 With legitimize_reload_address now defined here, REG_MODE_OK_FOR_BASE_P
2955 is now used here. */
2956#ifndef REG_MODE_OK_FOR_BASE_P
2957#define REG_MODE_OK_FOR_BASE_P(REGNO, MODE) REG_OK_FOR_BASE_P (REGNO)
2958#endif
2959
2960/* Our implementation of LEGITIMIZE_RELOAD_ADDRESS. Returns a value to
2961 replace the input X, or the original X if no replacement is called for.
2962 The output parameter *WIN is 1 if the calling macro should goto WIN,
2963 0 if it should not.
2964
2965 For RS/6000, we wish to handle large displacements off a base
2966 register by splitting the addend across an addiu/addis and the mem insn.
2967 This cuts number of extra insns needed from 3 to 1.
2968
2969 On Darwin, we use this to generate code for floating point constants.
2970 A movsf_low is generated so we wind up with 2 instructions rather than 3.
2971 The Darwin code is inside #if TARGET_MACHO because only then is
2972 machopic_function_base_name() defined. */
2973rtx
f676971a 2974rs6000_legitimize_reload_address (rtx x, enum machine_mode mode,
c4ad648e
AM		 2975 int opnum, int type,
2976 int ind_levels ATTRIBUTE_UNUSED, int *win)
24ea750e 2977{
f676971a 2978 /* We must recognize output that we have already generated ourselves. */
24ea750e
DJ		 2979 if (GET_CODE (x) == PLUS
2980 && GET_CODE (XEXP (x, 0)) == PLUS
2981 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
2982 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
2983 && GET_CODE (XEXP (x, 1)) == CONST_INT)
2984 {
2985 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
c4ad648e
AM		 2986 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
2987 opnum, (enum reload_type)type);
24ea750e
DJ		 2988 *win = 1;
2989 return x;
2990 }
3deb2758 2991
24ea750e
DJ		 2992#if TARGET_MACHO
2993 if (DEFAULT_ABI == ABI_DARWIN && flag_pic
2994 && GET_CODE (x) == LO_SUM
2995 && GET_CODE (XEXP (x, 0)) == PLUS
2996 && XEXP (XEXP (x, 0), 0) == pic_offset_table_rtx
2997 && GET_CODE (XEXP (XEXP (x, 0), 1)) == HIGH
2998 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 1), 0)) == CONST
2999 && XEXP (XEXP (XEXP (x, 0), 1), 0) == XEXP (x, 1)
3000 && GET_CODE (XEXP (XEXP (x, 1), 0)) == MINUS
3001 && GET_CODE (XEXP (XEXP (XEXP (x, 1), 0), 0)) == SYMBOL_REF
3002 && GET_CODE (XEXP (XEXP (XEXP (x, 1), 0), 1)) == SYMBOL_REF)
3003 {
3004 /* Result of previous invocation of this function on Darwin
6f317ef3 3005 floating point constant. */
24ea750e 3006 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
c4ad648e
AM		 3007 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
3008 opnum, (enum reload_type)type);
24ea750e
DJ		 3009 *win = 1;
3010 return x;
3011 }
3012#endif
4937d02d
DE		 3013
3014 /* Force ld/std non-word aligned offset into base register by wrapping
3015 in offset 0. */
3016 if (GET_CODE (x) == PLUS
3017 && GET_CODE (XEXP (x, 0)) == REG
3018 && REGNO (XEXP (x, 0)) < 32
3019 && REG_MODE_OK_FOR_BASE_P (XEXP (x, 0), mode)
3020 && GET_CODE (XEXP (x, 1)) == CONST_INT
3021 && (INTVAL (XEXP (x, 1)) & 3) != 0
78796ad5 3022 && !ALTIVEC_VECTOR_MODE (mode)
4937d02d
DE		 3023 && GET_MODE_SIZE (mode) >= UNITS_PER_WORD
3024 && TARGET_POWERPC64)
3025 {
3026 x = gen_rtx_PLUS (GET_MODE (x), x, GEN_INT (0));
3027 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3028 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
3029 opnum, (enum reload_type) type);
3030 *win = 1;
3031 return x;
3032 }
3033
24ea750e
DJ		 3034 if (GET_CODE (x) == PLUS
3035 && GET_CODE (XEXP (x, 0)) == REG
3036 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
3037 && REG_MODE_OK_FOR_BASE_P (XEXP (x, 0), mode)
78c875e8 3038 && GET_CODE (XEXP (x, 1)) == CONST_INT
93638d7a 3039 && !SPE_VECTOR_MODE (mode)
54b695e7
AH		 3040 && !(TARGET_E500_DOUBLE && (mode == DFmode
3041 || mode == DImode))
78c875e8 3042 && !ALTIVEC_VECTOR_MODE (mode))
24ea750e
DJ		 3043 {
3044 HOST_WIDE_INT val = INTVAL (XEXP (x, 1));
3045 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
3046 HOST_WIDE_INT high
c4ad648e 3047 = (((val - low) & 0xffffffff) ^ 0x80000000) - 0x80000000;
24ea750e
DJ		 3048
3049 /* Check for 32-bit overflow. */
3050 if (high + low != val)
c4ad648e 3051 {
24ea750e
DJ		 3052 *win = 0;
3053 return x;
3054 }
3055
3056 /* Reload the high part into a base reg; leave the low part
c4ad648e 3057 in the mem directly. */
24ea750e
DJ		 3058
3059 x = gen_rtx_PLUS (GET_MODE (x),
c4ad648e
AM		 3060 gen_rtx_PLUS (GET_MODE (x), XEXP (x, 0),
3061 GEN_INT (high)),
3062 GEN_INT (low));
24ea750e
DJ		 3063
3064 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
c4ad648e
AM		 3065 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
3066 opnum, (enum reload_type)type);
24ea750e
DJ		 3067 *win = 1;
3068 return x;
3069 }
4937d02d 3070
24ea750e
DJ		 3071#if TARGET_MACHO
3072 if (GET_CODE (x) == SYMBOL_REF
3073 && DEFAULT_ABI == ABI_DARWIN
69ef87e2 3074 && !ALTIVEC_VECTOR_MODE (mode)
a29077da 3075 && (flag_pic || MACHO_DYNAMIC_NO_PIC_P)
0d8c1c97
AM		 3076 /* Don't do this for TFmode, since the result isn't offsettable.
3077 The same goes for DImode without 64-bit gprs. */
3078 && mode != TFmode
3079 && (mode != DImode || TARGET_POWERPC64))
24ea750e 3080 {
a29077da
GK		 3081 if (flag_pic)
3082 {
3083 rtx offset = gen_rtx_CONST (Pmode,
3084 gen_rtx_MINUS (Pmode, x,
11abc112 3085 machopic_function_base_sym ()));
a29077da
GK		 3086 x = gen_rtx_LO_SUM (GET_MODE (x),
3087 gen_rtx_PLUS (Pmode, pic_offset_table_rtx,
3088 gen_rtx_HIGH (Pmode, offset)), offset);
3089 }
3090 else
3091 x = gen_rtx_LO_SUM (GET_MODE (x),
c4ad648e 3092 gen_rtx_HIGH (Pmode, x), x);
a29077da 3093
24ea750e 3094 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
a29077da
GK		 3095 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
3096 opnum, (enum reload_type)type);
24ea750e
DJ		 3097 *win = 1;
3098 return x;
3099 }
3100#endif
4937d02d 3101
24ea750e 3102 if (TARGET_TOC
4d588c14 3103 && constant_pool_expr_p (x)
c1f11548 3104 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x), mode))
24ea750e
DJ		 3105 {
3106 (x) = create_TOC_reference (x);
3107 *win = 1;
3108 return x;
3109 }
3110 *win = 0;
3111 return x;
f676971a 3112}
24ea750e 3113
258bfae2
FS		 3114/* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
3115 that is a valid memory address for an instruction.
3116 The MODE argument is the machine mode for the MEM expression
3117 that wants to use this address.
3118
3119 On the RS/6000, there are four valid address: a SYMBOL_REF that
3120 refers to a constant pool entry of an address (or the sum of it
3121 plus a constant), a short (16-bit signed) constant plus a register,
3122 the sum of two registers, or a register indirect, possibly with an
5bdc5878 3123 auto-increment. For DFmode and DImode with a constant plus register,
258bfae2
FS		 3124 we must ensure that both words are addressable or PowerPC64 with offset
3125 word aligned.
3126
3127 For modes spanning multiple registers (DFmode in 32-bit GPRs,
76d2b81d 3128 32-bit DImode, TImode, TFmode), indexed addressing cannot be used because
258bfae2
FS		 3129 adjacent memory cells are accessed by adding word-sized offsets
3130 during assembly output. */
3131int
a2369ed3 3132rs6000_legitimate_address (enum machine_mode mode, rtx x, int reg_ok_strict)
258bfae2 3133{
850e8d3d
DN		 3134 /* If this is an unaligned stvx/ldvx type address, discard the outer AND. */
3135 if (TARGET_ALTIVEC
3136 && ALTIVEC_VECTOR_MODE (mode)
3137 && GET_CODE (x) == AND
3138 && GET_CODE (XEXP (x, 1)) == CONST_INT
3139 && INTVAL (XEXP (x, 1)) == -16)
3140 x = XEXP (x, 0);
3141
c4501e62
JJ		 3142 if (RS6000_SYMBOL_REF_TLS_P (x))
3143 return 0;
4d588c14 3144 if (legitimate_indirect_address_p (x, reg_ok_strict))
258bfae2
FS		 3145 return 1;
3146 if ((GET_CODE (x) == PRE_INC || GET_CODE (x) == PRE_DEC)
0d6d6892 3147 && !ALTIVEC_VECTOR_MODE (mode)
a3170dc6 3148 && !SPE_VECTOR_MODE (mode)
54b695e7
AH		 3149 /* Restrict addressing for DI because of our SUBREG hackery. */
3150 && !(TARGET_E500_DOUBLE && (mode == DFmode || mode == DImode))
258bfae2 3151 && TARGET_UPDATE
4d588c14 3152 && legitimate_indirect_address_p (XEXP (x, 0), reg_ok_strict))
258bfae2 3153 return 1;
4d588c14 3154 if (legitimate_small_data_p (mode, x))
258bfae2 3155 return 1;
4d588c14 3156 if (legitimate_constant_pool_address_p (x))
258bfae2
FS		 3157 return 1;
3158 /* If not REG_OK_STRICT (before reload) let pass any stack offset. */
3159 if (! reg_ok_strict
3160 && GET_CODE (x) == PLUS
3161 && GET_CODE (XEXP (x, 0)) == REG
708d2456 3162 && (XEXP (x, 0) == virtual_stack_vars_rtx
c4ad648e 3163 || XEXP (x, 0) == arg_pointer_rtx)
258bfae2
FS		 3164 && GET_CODE (XEXP (x, 1)) == CONST_INT)
3165 return 1;
76d2b81d 3166 if (rs6000_legitimate_offset_address_p (mode, x, reg_ok_strict))
258bfae2
FS		 3167 return 1;
3168 if (mode != TImode
76d2b81d 3169 && mode != TFmode
a3170dc6
AH		 3170 && ((TARGET_HARD_FLOAT && TARGET_FPRS)
3171 || TARGET_POWERPC64
4d4cbc0e 3172 || ((mode != DFmode || TARGET_E500_DOUBLE) && mode != TFmode))
258bfae2 3173 && (TARGET_POWERPC64 || mode != DImode)
4d588c14 3174 && legitimate_indexed_address_p (x, reg_ok_strict))
258bfae2 3175 return 1;
4d588c14 3176 if (legitimate_lo_sum_address_p (mode, x, reg_ok_strict))
258bfae2
FS		 3177 return 1;
3178 return 0;
3179}
4d588c14
RH		 3180
3181/* Go to LABEL if ADDR (a legitimate address expression)
3182 has an effect that depends on the machine mode it is used for.
3183
3184 On the RS/6000 this is true of all integral offsets (since AltiVec
3185 modes don't allow them) or is a pre-increment or decrement.
3186
3187 ??? Except that due to conceptual problems in offsettable_address_p
3188 we can't really report the problems of integral offsets. So leave
f676971a 3189 this assuming that the adjustable offset must be valid for the
4d588c14
RH		 3190 sub-words of a TFmode operand, which is what we had before. */
3191
3192bool
a2369ed3 3193rs6000_mode_dependent_address (rtx addr)
4d588c14
RH		 3194{
3195 switch (GET_CODE (addr))
3196 {
3197 case PLUS:
3198 if (GET_CODE (XEXP (addr, 1)) == CONST_INT)
3199 {
3200 unsigned HOST_WIDE_INT val = INTVAL (XEXP (addr, 1));
3201 return val + 12 + 0x8000 >= 0x10000;
3202 }
3203 break;
3204
3205 case LO_SUM:
3206 return true;
3207
3208 case PRE_INC:
3209 case PRE_DEC:
3210 return TARGET_UPDATE;
3211
3212 default:
3213 break;
3214 }
3215
3216 return false;
3217}
d8ecbcdb
AH		 3218
3219/* Return number of consecutive hard regs needed starting at reg REGNO
3220 to hold something of mode MODE.
3221 This is ordinarily the length in words of a value of mode MODE
3222 but can be less for certain modes in special long registers.
3223
3224 For the SPE, GPRs are 64 bits but only 32 bits are visible in
3225 scalar instructions. The upper 32 bits are only available to the
3226 SIMD instructions.
3227
3228 POWER and PowerPC GPRs hold 32 bits worth;
3229 PowerPC64 GPRs and FPRs point register holds 64 bits worth. */
3230
3231int
3232rs6000_hard_regno_nregs (int regno, enum machine_mode mode)
3233{
3234 if (FP_REGNO_P (regno))
3235 return (GET_MODE_SIZE (mode) + UNITS_PER_FP_WORD - 1) / UNITS_PER_FP_WORD;
3236
4d4cbc0e
AH		 3237 if (TARGET_E500_DOUBLE && mode == DFmode)
3238 return 1;
3239
d8ecbcdb
AH		 3240 if (SPE_SIMD_REGNO_P (regno) && TARGET_SPE && SPE_VECTOR_MODE (mode))
3241 return (GET_MODE_SIZE (mode) + UNITS_PER_SPE_WORD - 1) / UNITS_PER_SPE_WORD;
3242
3243 if (ALTIVEC_REGNO_P (regno))
3244 return
3245 (GET_MODE_SIZE (mode) + UNITS_PER_ALTIVEC_WORD - 1) / UNITS_PER_ALTIVEC_WORD;
3246
3247 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
3248}
2aa4498c
AH		 3249
3250/* Change register usage conditional on target flags. */
3251void
3252rs6000_conditional_register_usage (void)
3253{
3254 int i;
3255
3256 /* Set MQ register fixed (already call_used) if not POWER
3257 architecture (RIOS1, RIOS2, RSC, and PPC601) so that it will not
3258 be allocated. */
3259 if (! TARGET_POWER)
3260 fixed_regs[64] = 1;
3261
3262 /* 64-bit AIX reserves GPR13 for thread-private data. */
3263 if (TARGET_64BIT)
3264 fixed_regs[13] = call_used_regs[13]
3265 = call_really_used_regs[13] = 1;
3266
3267 /* Conditionally disable FPRs. */
3268 if (TARGET_SOFT_FLOAT || !TARGET_FPRS)
3269 for (i = 32; i < 64; i++)
3270 fixed_regs[i] = call_used_regs[i]
c4ad648e 3271 = call_really_used_regs[i] = 1;
2aa4498c
AH		 3272
3273 if (DEFAULT_ABI == ABI_V4
3274 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM
3275 && flag_pic == 2)
3276 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
3277
3278 if (DEFAULT_ABI == ABI_V4
3279 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM
3280 && flag_pic == 1)
3281 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
3282 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
3283 = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
3284
3285 if (DEFAULT_ABI == ABI_DARWIN
3286 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM)
3287 global_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
3288 = fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
3289 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
3290 = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
3291
b4db40bf
JJ		 3292 if (TARGET_TOC && TARGET_MINIMAL_TOC)
3293 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
3294 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
3295
2aa4498c
AH		 3296 if (TARGET_ALTIVEC)
3297 global_regs[VSCR_REGNO] = 1;
3298
3299 if (TARGET_SPE)
3300 {
3301 global_regs[SPEFSCR_REGNO] = 1;
3302 fixed_regs[FIXED_SCRATCH]
c4ad648e 3303 = call_used_regs[FIXED_SCRATCH]
2aa4498c
AH		 3304 = call_really_used_regs[FIXED_SCRATCH] = 1;
3305 }
3306
3307 if (! TARGET_ALTIVEC)
3308 {
3309 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
3310 fixed_regs[i] = call_used_regs[i] = call_really_used_regs[i] = 1;
3311 call_really_used_regs[VRSAVE_REGNO] = 1;
3312 }
3313
3314 if (TARGET_ALTIVEC_ABI)
3315 for (i = FIRST_ALTIVEC_REGNO; i < FIRST_ALTIVEC_REGNO + 20; ++i)
3316 call_used_regs[i] = call_really_used_regs[i] = 1;
3317}
fb4d4348 3318\f
a4f6c312
SS		 3319/* Try to output insns to set TARGET equal to the constant C if it can
3320 be done in less than N insns. Do all computations in MODE.
3321 Returns the place where the output has been placed if it can be
3322 done and the insns have been emitted. If it would take more than N
3323 insns, zero is returned and no insns and emitted. */
2bfcf297
DB		 3324
3325rtx
f676971a 3326rs6000_emit_set_const (rtx dest, enum machine_mode mode,
a2369ed3 3327 rtx source, int n ATTRIBUTE_UNUSED)
2bfcf297 3328{
af8cb5c5 3329 rtx result, insn, set;
2bfcf297
DB		 3330 HOST_WIDE_INT c0, c1;
3331
37409796 3332 switch (mode)
2bfcf297 3333 {
37409796
NS		 3334 case QImode:
3335 case HImode:
2bfcf297 3336 if (dest == NULL)
c4ad648e 3337 dest = gen_reg_rtx (mode);
2bfcf297
DB		 3338 emit_insn (gen_rtx_SET (VOIDmode, dest, source));
3339 return dest;
37409796
NS		 3340
3341 case SImode:
af8cb5c5 3342 result = no_new_pseudos ? dest : gen_reg_rtx (SImode);
37409796 3343
af8cb5c5
DE		 3344 emit_insn (gen_rtx_SET (VOIDmode, result,
3345 GEN_INT (INTVAL (source)
3346 & (~ (HOST_WIDE_INT) 0xffff))));
3347 emit_insn (gen_rtx_SET (VOIDmode, dest,
3348 gen_rtx_IOR (SImode, result,
3349 GEN_INT (INTVAL (source) & 0xffff))));
3350 result = dest;
37409796
NS		 3351 break;
3352
3353 case DImode:
3354 switch (GET_CODE (source))
af8cb5c5 3355 {
37409796 3356 case CONST_INT:
af8cb5c5
DE		 3357 c0 = INTVAL (source);
3358 c1 = -(c0 < 0);
37409796
NS		 3359 break;
3360
3361 case CONST_DOUBLE:
2bfcf297 3362#if HOST_BITS_PER_WIDE_INT >= 64
af8cb5c5
DE		 3363 c0 = CONST_DOUBLE_LOW (source);
3364 c1 = -(c0 < 0);
2bfcf297 3365#else
af8cb5c5
DE		 3366 c0 = CONST_DOUBLE_LOW (source);
3367 c1 = CONST_DOUBLE_HIGH (source);
2bfcf297 3368#endif
37409796
NS		 3369 break;
3370
3371 default:
3372 gcc_unreachable ();
af8cb5c5 3373 }
af8cb5c5
DE		 3374
3375 result = rs6000_emit_set_long_const (dest, c0, c1);
37409796
NS		 3376 break;
3377
3378 default:
3379 gcc_unreachable ();
2bfcf297 3380 }
2bfcf297 3381
af8cb5c5
DE		 3382 insn = get_last_insn ();
3383 set = single_set (insn);
3384 if (! CONSTANT_P (SET_SRC (set)))
3385 set_unique_reg_note (insn, REG_EQUAL, source);
3386
3387 return result;
2bfcf297
DB		 3388}
3389
3390/* Having failed to find a 3 insn sequence in rs6000_emit_set_const,
3391 fall back to a straight forward decomposition. We do this to avoid
3392 exponential run times encountered when looking for longer sequences
3393 with rs6000_emit_set_const. */
3394static rtx
a2369ed3 3395rs6000_emit_set_long_const (rtx dest, HOST_WIDE_INT c1, HOST_WIDE_INT c2)
2bfcf297
DB		 3396{
3397 if (!TARGET_POWERPC64)
3398 {
3399 rtx operand1, operand2;
3400
3401 operand1 = operand_subword_force (dest, WORDS_BIG_ENDIAN == 0,
3402 DImode);
3403 operand2 = operand_subword_force (dest, WORDS_BIG_ENDIAN != 0,
3404 DImode);
3405 emit_move_insn (operand1, GEN_INT (c1));
3406 emit_move_insn (operand2, GEN_INT (c2));
3407 }
3408 else
3409 {
bc06712d 3410 HOST_WIDE_INT ud1, ud2, ud3, ud4;
252b88f7 3411
bc06712d 3412 ud1 = c1 & 0xffff;
f921c9c9 3413 ud2 = (c1 & 0xffff0000) >> 16;
2bfcf297 3414#if HOST_BITS_PER_WIDE_INT >= 64
bc06712d 3415 c2 = c1 >> 32;
2bfcf297 3416#endif
bc06712d 3417 ud3 = c2 & 0xffff;
f921c9c9 3418 ud4 = (c2 & 0xffff0000) >> 16;
2bfcf297 3419
f676971a 3420 if ((ud4 == 0xffff && ud3 == 0xffff && ud2 == 0xffff && (ud1 & 0x8000))
bc06712d 3421 || (ud4 == 0 && ud3 == 0 && ud2 == 0 && ! (ud1 & 0x8000)))
2bfcf297 3422 {
bc06712d 3423 if (ud1 & 0x8000)
b78d48dd 3424 emit_move_insn (dest, GEN_INT (((ud1 ^ 0x8000) - 0x8000)));
bc06712d
TR		 3425 else
3426 emit_move_insn (dest, GEN_INT (ud1));
2bfcf297 3427 }
2bfcf297 3428
f676971a 3429 else if ((ud4 == 0xffff && ud3 == 0xffff && (ud2 & 0x8000))
bc06712d 3430 || (ud4 == 0 && ud3 == 0 && ! (ud2 & 0x8000)))
252b88f7 3431 {
bc06712d 3432 if (ud2 & 0x8000)
f676971a 3433 emit_move_insn (dest, GEN_INT (((ud2 << 16) ^ 0x80000000)
bc06712d 3434 - 0x80000000));
252b88f7 3435 else
bc06712d
TR		 3436 emit_move_insn (dest, GEN_INT (ud2 << 16));
3437 if (ud1 != 0)
3438 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud1)));
252b88f7 3439 }
f676971a 3440 else if ((ud4 == 0xffff && (ud3 & 0x8000))
bc06712d
TR		 3441 || (ud4 == 0 && ! (ud3 & 0x8000)))
3442 {
3443 if (ud3 & 0x8000)
f676971a 3444 emit_move_insn (dest, GEN_INT (((ud3 << 16) ^ 0x80000000)
bc06712d
TR		 3445 - 0x80000000));
3446 else
3447 emit_move_insn (dest, GEN_INT (ud3 << 16));
3448
3449 if (ud2 != 0)
3450 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud2)));
3451 emit_move_insn (dest, gen_rtx_ASHIFT (DImode, dest, GEN_INT (16)));
3452 if (ud1 != 0)
3453 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud1)));
3454 }
f676971a 3455 else
bc06712d
TR		 3456 {
3457 if (ud4 & 0x8000)
f676971a 3458 emit_move_insn (dest, GEN_INT (((ud4 << 16) ^ 0x80000000)
bc06712d
TR		 3459 - 0x80000000));
3460 else
3461 emit_move_insn (dest, GEN_INT (ud4 << 16));
3462
3463 if (ud3 != 0)
3464 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud3)));
2bfcf297 3465
bc06712d
TR		 3466 emit_move_insn (dest, gen_rtx_ASHIFT (DImode, dest, GEN_INT (32)));
3467 if (ud2 != 0)
f676971a
EC		 3468 emit_move_insn (dest, gen_rtx_IOR (DImode, dest,
3469 GEN_INT (ud2 << 16)));
bc06712d
TR		 3470 if (ud1 != 0)
3471 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud1)));
3472 }
3473 }
2bfcf297
DB		 3474 return dest;
3475}
3476
76d2b81d
DJ		 3477/* Helper for the following. Get rid of [r+r] memory refs
3478 in cases where it won't work (TImode, TFmode). */
3479
3480static void
3481rs6000_eliminate_indexed_memrefs (rtx operands[2])
3482{
3483 if (GET_CODE (operands[0]) == MEM
3484 && GET_CODE (XEXP (operands[0], 0)) != REG
55aa0757 3485 && ! legitimate_constant_pool_address_p (XEXP (operands[0], 0))
76d2b81d
DJ		 3486 && ! reload_in_progress)
3487 operands[0]
3488 = replace_equiv_address (operands[0],
3489 copy_addr_to_reg (XEXP (operands[0], 0)));
3490
3491 if (GET_CODE (operands[1]) == MEM
3492 && GET_CODE (XEXP (operands[1], 0)) != REG
55aa0757 3493 && ! legitimate_constant_pool_address_p (XEXP (operands[1], 0))
76d2b81d
DJ		 3494 && ! reload_in_progress)
3495 operands[1]
3496 = replace_equiv_address (operands[1],
3497 copy_addr_to_reg (XEXP (operands[1], 0)));
3498}
3499
fb4d4348
GK		 3500/* Emit a move from SOURCE to DEST in mode MODE. */
3501void
a2369ed3 3502rs6000_emit_move (rtx dest, rtx source, enum machine_mode mode)
fb4d4348
GK		 3503{
3504 rtx operands[2];
3505 operands[0] = dest;
3506 operands[1] = source;
f676971a 3507
fb4d4348
GK		 3508 /* Sanity checks. Check that we get CONST_DOUBLE only when we should. */
3509 if (GET_CODE (operands[1]) == CONST_DOUBLE
3510 && ! FLOAT_MODE_P (mode)
3511 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
3512 {
3513 /* FIXME. This should never happen. */
3514 /* Since it seems that it does, do the safe thing and convert
3515 to a CONST_INT. */
2496c7bd 3516 operands[1] = gen_int_mode (CONST_DOUBLE_LOW (operands[1]), mode);
fb4d4348 3517 }
37409796
NS		 3518 gcc_assert (GET_CODE (operands[1]) != CONST_DOUBLE
3519 || FLOAT_MODE_P (mode)
3520 || ((CONST_DOUBLE_HIGH (operands[1]) != 0
3521 || CONST_DOUBLE_LOW (operands[1]) < 0)
3522 && (CONST_DOUBLE_HIGH (operands[1]) != -1
3523 || CONST_DOUBLE_LOW (operands[1]) >= 0)));
3524
c9e8cb32
DD		 3525 /* Check if GCC is setting up a block move that will end up using FP
3526 registers as temporaries. We must make sure this is acceptable. */
3527 if (GET_CODE (operands[0]) == MEM
3528 && GET_CODE (operands[1]) == MEM
3529 && mode == DImode
41543739
GK		 3530 && (SLOW_UNALIGNED_ACCESS (DImode, MEM_ALIGN (operands[0]))
3531 || SLOW_UNALIGNED_ACCESS (DImode, MEM_ALIGN (operands[1])))
3532 && ! (SLOW_UNALIGNED_ACCESS (SImode, (MEM_ALIGN (operands[0]) > 32
3533 ? 32 : MEM_ALIGN (operands[0])))
3534 || SLOW_UNALIGNED_ACCESS (SImode, (MEM_ALIGN (operands[1]) > 32
f676971a 3535 ? 32
41543739
GK		 3536 : MEM_ALIGN (operands[1]))))
3537 && ! MEM_VOLATILE_P (operands [0])
3538 && ! MEM_VOLATILE_P (operands [1]))
c9e8cb32 3539 {
41543739
GK		 3540 emit_move_insn (adjust_address (operands[0], SImode, 0),
3541 adjust_address (operands[1], SImode, 0));
3542 emit_move_insn (adjust_address (operands[0], SImode, 4),
3543 adjust_address (operands[1], SImode, 4));
c9e8cb32
DD		 3544 return;
3545 }
630d42a0 3546
55aa0757 3547 if (!no_new_pseudos && GET_CODE (operands[0]) == MEM
c9dbf840 3548 && !gpc_reg_operand (operands[1], mode))
f6219a5e 3549 operands[1] = force_reg (mode, operands[1]);
a9098fd0 3550
a3170dc6
AH		 3551 if (mode == SFmode && ! TARGET_POWERPC
3552 && TARGET_HARD_FLOAT && TARGET_FPRS
ffc14f31 3553 && GET_CODE (operands[0]) == MEM)
fb4d4348 3554 {
ffc14f31
GK		 3555 int regnum;
3556
3557 if (reload_in_progress || reload_completed)
3558 regnum = true_regnum (operands[1]);
3559 else if (GET_CODE (operands[1]) == REG)
3560 regnum = REGNO (operands[1]);
3561 else
3562 regnum = -1;
f676971a 3563
fb4d4348
GK		 3564 /* If operands[1] is a register, on POWER it may have
3565 double-precision data in it, so truncate it to single
3566 precision. */
3567 if (FP_REGNO_P (regnum) || regnum >= FIRST_PSEUDO_REGISTER)
3568 {
3569 rtx newreg;
3570 newreg = (no_new_pseudos ? operands[1] : gen_reg_rtx (mode));
3571 emit_insn (gen_aux_truncdfsf2 (newreg, operands[1]));
3572 operands[1] = newreg;
3573 }
3574 }
3575
c4501e62
JJ		 3576 /* Recognize the case where operand[1] is a reference to thread-local
3577 data and load its address to a register. */
3578 if (GET_CODE (operands[1]) == SYMBOL_REF)
3579 {
3580 enum tls_model model = SYMBOL_REF_TLS_MODEL (operands[1]);
3581 if (model != 0)
3582 operands[1] = rs6000_legitimize_tls_address (operands[1], model);
3583 }
3584
8f4e6caf
RH		 3585 /* Handle the case where reload calls us with an invalid address. */
3586 if (reload_in_progress && mode == Pmode
69ef87e2 3587 && (! general_operand (operands[1], mode)
8f4e6caf
RH		 3588 || ! nonimmediate_operand (operands[0], mode)))
3589 goto emit_set;
3590
a9baceb1
GK		 3591 /* 128-bit constant floating-point values on Darwin should really be
3592 loaded as two parts. */
3593 if ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
3594 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128
3595 && mode == TFmode && GET_CODE (operands[1]) == CONST_DOUBLE)
3596 {
3597 /* DImode is used, not DFmode, because simplify_gen_subreg doesn't
3598 know how to get a DFmode SUBREG of a TFmode. */
3599 rs6000_emit_move (simplify_gen_subreg (DImode, operands[0], mode, 0),
3600 simplify_gen_subreg (DImode, operands[1], mode, 0),
3601 DImode);
3602 rs6000_emit_move (simplify_gen_subreg (DImode, operands[0], mode,
3603 GET_MODE_SIZE (DImode)),
3604 simplify_gen_subreg (DImode, operands[1], mode,
3605 GET_MODE_SIZE (DImode)),
3606 DImode);
3607 return;
3608 }
3609
fb4d4348
GK		 3610 /* FIXME: In the long term, this switch statement should go away
3611 and be replaced by a sequence of tests based on things like
3612 mode == Pmode. */
3613 switch (mode)
3614 {
3615 case HImode:
3616 case QImode:
3617 if (CONSTANT_P (operands[1])
3618 && GET_CODE (operands[1]) != CONST_INT)
a9098fd0 3619 operands[1] = force_const_mem (mode, operands[1]);
fb4d4348
GK		 3620 break;
3621
06f4e019 3622 case TFmode:
76d2b81d
DJ		 3623 rs6000_eliminate_indexed_memrefs (operands);
3624 /* fall through */
3625
fb4d4348
GK		 3626 case DFmode:
3627 case SFmode:
f676971a 3628 if (CONSTANT_P (operands[1])
fb4d4348 3629 && ! easy_fp_constant (operands[1], mode))
a9098fd0 3630 operands[1] = force_const_mem (mode, operands[1]);
fb4d4348 3631 break;
f676971a 3632
0ac081f6
AH		 3633 case V16QImode:
3634 case V8HImode:
3635 case V4SFmode:
3636 case V4SImode:
a3170dc6
AH		 3637 case V4HImode:
3638 case V2SFmode:
3639 case V2SImode:
00a892b8 3640 case V1DImode:
69ef87e2 3641 if (CONSTANT_P (operands[1])
d744e06e 3642 && !easy_vector_constant (operands[1], mode))
0ac081f6
AH		 3643 operands[1] = force_const_mem (mode, operands[1]);
3644 break;
f676971a 3645
fb4d4348 3646 case SImode:
a9098fd0 3647 case DImode:
fb4d4348
GK		 3648 /* Use default pattern for address of ELF small data */
3649 if (TARGET_ELF
a9098fd0 3650 && mode == Pmode
f607bc57 3651 && DEFAULT_ABI == ABI_V4
f676971a 3652 && (GET_CODE (operands[1]) == SYMBOL_REF
a9098fd0
GK		 3653 || GET_CODE (operands[1]) == CONST)
3654 && small_data_operand (operands[1], mode))
fb4d4348
GK		 3655 {
3656 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
3657 return;
3658 }
3659
f607bc57 3660 if (DEFAULT_ABI == ABI_V4
a9098fd0
GK		 3661 && mode == Pmode && mode == SImode
3662 && flag_pic == 1 && got_operand (operands[1], mode))
fb4d4348
GK		 3663 {
3664 emit_insn (gen_movsi_got (operands[0], operands[1]));
3665 return;
3666 }
3667
ee890fe2 3668 if ((TARGET_ELF || DEFAULT_ABI == ABI_DARWIN)
f1384257
AM		 3669 && TARGET_NO_TOC
3670 && ! flag_pic
a9098fd0 3671 && mode == Pmode
fb4d4348
GK		 3672 && CONSTANT_P (operands[1])
3673 && GET_CODE (operands[1]) != HIGH
3674 && GET_CODE (operands[1]) != CONST_INT)
3675 {
a9098fd0 3676 rtx target = (no_new_pseudos ? operands[0] : gen_reg_rtx (mode));
fb4d4348
GK		 3677
3678 /* If this is a function address on -mcall-aixdesc,
3679 convert it to the address of the descriptor. */
3680 if (DEFAULT_ABI == ABI_AIX
3681 && GET_CODE (operands[1]) == SYMBOL_REF
3682 && XSTR (operands[1], 0)[0] == '.')
3683 {
3684 const char *name = XSTR (operands[1], 0);
3685 rtx new_ref;
3686 while (*name == '.')
3687 name++;
3688 new_ref = gen_rtx_SYMBOL_REF (Pmode, name);
3689 CONSTANT_POOL_ADDRESS_P (new_ref)
3690 = CONSTANT_POOL_ADDRESS_P (operands[1]);
d1908feb 3691 SYMBOL_REF_FLAGS (new_ref) = SYMBOL_REF_FLAGS (operands[1]);
fb4d4348 3692 SYMBOL_REF_USED (new_ref) = SYMBOL_REF_USED (operands[1]);
d1908feb 3693 SYMBOL_REF_DECL (new_ref) = SYMBOL_REF_DECL (operands[1]);
fb4d4348
GK		 3694 operands[1] = new_ref;
3695 }
7509c759 3696
ee890fe2
SS		 3697 if (DEFAULT_ABI == ABI_DARWIN)
3698 {
ab82a49f
AP		 3699#if TARGET_MACHO
3700 if (MACHO_DYNAMIC_NO_PIC_P)
3701 {
3702 /* Take care of any required data indirection. */
3703 operands[1] = rs6000_machopic_legitimize_pic_address (
3704 operands[1], mode, operands[0]);
3705 if (operands[0] != operands[1])
3706 emit_insn (gen_rtx_SET (VOIDmode,
c4ad648e 3707 operands[0], operands[1]));
ab82a49f
AP		 3708 return;
3709 }
3710#endif
b8a55285
AP		 3711 emit_insn (gen_macho_high (target, operands[1]));
3712 emit_insn (gen_macho_low (operands[0], target, operands[1]));
ee890fe2
SS		 3713 return;
3714 }
3715
fb4d4348
GK		 3716 emit_insn (gen_elf_high (target, operands[1]));
3717 emit_insn (gen_elf_low (operands[0], target, operands[1]));
3718 return;
3719 }
3720
a9098fd0
GK		 3721 /* If this is a SYMBOL_REF that refers to a constant pool entry,
3722 and we have put it in the TOC, we just need to make a TOC-relative
3723 reference to it. */
3724 if (TARGET_TOC
3725 && GET_CODE (operands[1]) == SYMBOL_REF
4d588c14 3726 && constant_pool_expr_p (operands[1])
a9098fd0
GK		 3727 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (operands[1]),
3728 get_pool_mode (operands[1])))
fb4d4348 3729 {
a9098fd0 3730 operands[1] = create_TOC_reference (operands[1]);
fb4d4348 3731 }
a9098fd0
GK		 3732 else if (mode == Pmode
3733 && CONSTANT_P (operands[1])
38886f37
AO		 3734 && ((GET_CODE (operands[1]) != CONST_INT
3735 && ! easy_fp_constant (operands[1], mode))
3736 || (GET_CODE (operands[1]) == CONST_INT
3737 && num_insns_constant (operands[1], mode) > 2)
3738 || (GET_CODE (operands[0]) == REG
3739 && FP_REGNO_P (REGNO (operands[0]))))
a9098fd0 3740 && GET_CODE (operands[1]) != HIGH
4d588c14
RH		 3741 && ! legitimate_constant_pool_address_p (operands[1])
3742 && ! toc_relative_expr_p (operands[1]))
fb4d4348
GK		 3743 {
3744 /* Emit a USE operation so that the constant isn't deleted if
3745 expensive optimizations are turned on because nobody
3746 references it. This should only be done for operands that
3747 contain SYMBOL_REFs with CONSTANT_POOL_ADDRESS_P set.
3748 This should not be done for operands that contain LABEL_REFs.
3749 For now, we just handle the obvious case. */
3750 if (GET_CODE (operands[1]) != LABEL_REF)
3751 emit_insn (gen_rtx_USE (VOIDmode, operands[1]));
3752
c859cda6 3753#if TARGET_MACHO
ee890fe2 3754 /* Darwin uses a special PIC legitimizer. */
ab82a49f 3755 if (DEFAULT_ABI == ABI_DARWIN && MACHOPIC_INDIRECT)
ee890fe2 3756 {
ee890fe2
SS		 3757 operands[1] =
3758 rs6000_machopic_legitimize_pic_address (operands[1], mode,
c859cda6
DJ		 3759 operands[0]);
3760 if (operands[0] != operands[1])
3761 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
ee890fe2
SS		 3762 return;
3763 }
c859cda6 3764#endif
ee890fe2 3765
fb4d4348
GK		 3766 /* If we are to limit the number of things we put in the TOC and
3767 this is a symbol plus a constant we can add in one insn,
3768 just put the symbol in the TOC and add the constant. Don't do
3769 this if reload is in progress. */
3770 if (GET_CODE (operands[1]) == CONST
3771 && TARGET_NO_SUM_IN_TOC && ! reload_in_progress
3772 && GET_CODE (XEXP (operands[1], 0)) == PLUS
a9098fd0 3773 && add_operand (XEXP (XEXP (operands[1], 0), 1), mode)
fb4d4348
GK		 3774 && (GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == LABEL_REF
3775 || GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == SYMBOL_REF)
3776 && ! side_effects_p (operands[0]))
3777 {
a4f6c312
SS		 3778 rtx sym =
3779 force_const_mem (mode, XEXP (XEXP (operands[1], 0), 0));
fb4d4348
GK		 3780 rtx other = XEXP (XEXP (operands[1], 0), 1);
3781
a9098fd0
GK		 3782 sym = force_reg (mode, sym);
3783 if (mode == SImode)
3784 emit_insn (gen_addsi3 (operands[0], sym, other));
3785 else
3786 emit_insn (gen_adddi3 (operands[0], sym, other));
fb4d4348
GK		 3787 return;
3788 }
3789
a9098fd0 3790 operands[1] = force_const_mem (mode, operands[1]);
fb4d4348 3791
f676971a 3792 if (TARGET_TOC
4d588c14 3793 && constant_pool_expr_p (XEXP (operands[1], 0))
d34c5b80
DE		 3794 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (
3795 get_pool_constant (XEXP (operands[1], 0)),
3796 get_pool_mode (XEXP (operands[1], 0))))
a9098fd0 3797 {
ba4828e0 3798 operands[1]
542a8afa 3799 = gen_const_mem (mode,
c4ad648e 3800 create_TOC_reference (XEXP (operands[1], 0)));
ba4828e0 3801 set_mem_alias_set (operands[1], get_TOC_alias_set ());
a9098fd0 3802 }
fb4d4348
GK		 3803 }
3804 break;
a9098fd0 3805
fb4d4348 3806 case TImode:
76d2b81d
DJ		 3807 rs6000_eliminate_indexed_memrefs (operands);
3808
27dc0551
DE		 3809 if (TARGET_POWER)
3810 {
3811 emit_insn (gen_rtx_PARALLEL (VOIDmode,
3812 gen_rtvec (2,
3813 gen_rtx_SET (VOIDmode,
3814 operands[0], operands[1]),
3815 gen_rtx_CLOBBER (VOIDmode,
3816 gen_rtx_SCRATCH (SImode)))));
3817 return;
3818 }
fb4d4348
GK		 3819 break;
3820
3821 default:
37409796 3822 gcc_unreachable ();
fb4d4348
GK		 3823 }
3824
a9098fd0
GK		 3825 /* Above, we may have called force_const_mem which may have returned
3826 an invalid address. If we can, fix this up; otherwise, reload will
3827 have to deal with it. */
8f4e6caf
RH		 3828 if (GET_CODE (operands[1]) == MEM && ! reload_in_progress)
3829 operands[1] = validize_mem (operands[1]);
a9098fd0 3830
8f4e6caf 3831 emit_set:
fb4d4348
GK		 3832 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
3833}
4697a36c 3834\f
2858f73a
GK		 3835/* Nonzero if we can use a floating-point register to pass this arg. */
3836#define USE_FP_FOR_ARG_P(CUM,MODE,TYPE) \
3837 (GET_MODE_CLASS (MODE) == MODE_FLOAT \
3838 && (CUM)->fregno <= FP_ARG_MAX_REG \
3839 && TARGET_HARD_FLOAT && TARGET_FPRS)
3840
3841/* Nonzero if we can use an AltiVec register to pass this arg. */
3842#define USE_ALTIVEC_FOR_ARG_P(CUM,MODE,TYPE,NAMED) \
3843 (ALTIVEC_VECTOR_MODE (MODE) \
3844 && (CUM)->vregno <= ALTIVEC_ARG_MAX_REG \
3845 && TARGET_ALTIVEC_ABI \
83953138 3846 && (NAMED))
2858f73a 3847
c6e8c921
GK		 3848/* Return a nonzero value to say to return the function value in
3849 memory, just as large structures are always returned. TYPE will be
3850 the data type of the value, and FNTYPE will be the type of the
3851 function doing the returning, or @code{NULL} for libcalls.
3852
3853 The AIX ABI for the RS/6000 specifies that all structures are
3854 returned in memory. The Darwin ABI does the same. The SVR4 ABI
3855 specifies that structures <= 8 bytes are returned in r3/r4, but a
3856 draft put them in memory, and GCC used to implement the draft
3857 instead of the final standard. Therefore, TARGET_AIX_STRUCT_RET
3858 controls this instead of DEFAULT_ABI; V.4 targets needing backward
3859 compatibility can change DRAFT_V4_STRUCT_RET to override the
3860 default, and -m switches get the final word. See
3861 rs6000_override_options for more details.
3862
3863 The PPC32 SVR4 ABI uses IEEE double extended for long double, if 128-bit
3864 long double support is enabled. These values are returned in memory.
3865
3866 int_size_in_bytes returns -1 for variable size objects, which go in
3867 memory always. The cast to unsigned makes -1 > 8. */
3868
3869static bool
3870rs6000_return_in_memory (tree type, tree fntype ATTRIBUTE_UNUSED)
3871{
594a51fe
SS		 3872 /* In the darwin64 abi, try to use registers for larger structs
3873 if possible. */
0b5383eb 3874 if (rs6000_darwin64_abi
594a51fe 3875 && TREE_CODE (type) == RECORD_TYPE
0b5383eb
DJ		 3876 && int_size_in_bytes (type) > 0)
3877 {
3878 CUMULATIVE_ARGS valcum;
3879 rtx valret;
3880
3881 valcum.words = 0;
3882 valcum.fregno = FP_ARG_MIN_REG;
3883 valcum.vregno = ALTIVEC_ARG_MIN_REG;
3884 /* Do a trial code generation as if this were going to be passed
3885 as an argument; if any part goes in memory, we return NULL. */
3886 valret = rs6000_darwin64_record_arg (&valcum, type, 1, true);
3887 if (valret)
3888 return false;
3889 /* Otherwise fall through to more conventional ABI rules. */
3890 }
594a51fe 3891
c6e8c921
GK		 3892 if (AGGREGATE_TYPE_P (type)
3893 && (TARGET_AIX_STRUCT_RET
3894 || (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 8))
3895 return true;
b693336b 3896
bada2eb8
DE		 3897 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
3898 modes only exist for GCC vector types if -maltivec. */
3899 if (TARGET_32BIT && !TARGET_ALTIVEC_ABI
3900 && ALTIVEC_VECTOR_MODE (TYPE_MODE (type)))
3901 return false;
3902
b693336b
PB		 3903 /* Return synthetic vectors in memory. */
3904 if (TREE_CODE (type) == VECTOR_TYPE
ad630bef 3905 && int_size_in_bytes (type) > (TARGET_ALTIVEC_ABI ? 16 : 8))
b693336b
PB		 3906 {
3907 static bool warned_for_return_big_vectors = false;
3908 if (!warned_for_return_big_vectors)
3909 {
d4ee4d25 3910 warning (0, "GCC vector returned by reference: "
b693336b
PB		 3911 "non-standard ABI extension with no compatibility guarantee");
3912 warned_for_return_big_vectors = true;
3913 }
3914 return true;
3915 }
3916
c6e8c921
GK		 3917 if (DEFAULT_ABI == ABI_V4 && TYPE_MODE (type) == TFmode)
3918 return true;
ad630bef 3919
c6e8c921
GK		 3920 return false;
3921}
3922
4697a36c
MM		 3923/* Initialize a variable CUM of type CUMULATIVE_ARGS
3924 for a call to a function whose data type is FNTYPE.
3925 For a library call, FNTYPE is 0.
3926
3927 For incoming args we set the number of arguments in the prototype large
1c20ae99 3928 so we never return a PARALLEL. */
4697a36c
MM		 3929
3930void
f676971a 3931init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype,
0f6937fe
AM		 3932 rtx libname ATTRIBUTE_UNUSED, int incoming,
3933 int libcall, int n_named_args)
4697a36c
MM		 3934{
3935 static CUMULATIVE_ARGS zero_cumulative;
3936
3937 *cum = zero_cumulative;
3938 cum->words = 0;
3939 cum->fregno = FP_ARG_MIN_REG;
0ac081f6 3940 cum->vregno = ALTIVEC_ARG_MIN_REG;
4697a36c 3941 cum->prototype = (fntype && TYPE_ARG_TYPES (fntype));
ddcc8263
DE		 3942 cum->call_cookie = ((DEFAULT_ABI == ABI_V4 && libcall)
3943 ? CALL_LIBCALL : CALL_NORMAL);
4cc833b7 3944 cum->sysv_gregno = GP_ARG_MIN_REG;
a6c9bed4
AH		 3945 cum->stdarg = fntype
3946 && (TYPE_ARG_TYPES (fntype) != 0
3947 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype)))
3948 != void_type_node));
4697a36c 3949
0f6937fe
AM		 3950 cum->nargs_prototype = 0;
3951 if (incoming || cum->prototype)
3952 cum->nargs_prototype = n_named_args;
4697a36c 3953
a5c76ee6 3954 /* Check for a longcall attribute. */
3eb4e360
AM		 3955 if ((!fntype && rs6000_default_long_calls)
3956 || (fntype
3957 && lookup_attribute ("longcall", TYPE_ATTRIBUTES (fntype))
3958 && !lookup_attribute ("shortcall", TYPE_ATTRIBUTES (fntype))))
3959 cum->call_cookie |= CALL_LONG;
6a4cee5f 3960
4697a36c
MM		 3961 if (TARGET_DEBUG_ARG)
3962 {
3963 fprintf (stderr, "\ninit_cumulative_args:");
3964 if (fntype)
3965 {
3966 tree ret_type = TREE_TYPE (fntype);
3967 fprintf (stderr, " ret code = %s,",
3968 tree_code_name[ (int)TREE_CODE (ret_type) ]);
3969 }
3970
6a4cee5f
MM		 3971 if (cum->call_cookie & CALL_LONG)
3972 fprintf (stderr, " longcall,");
3973
4697a36c
MM		 3974 fprintf (stderr, " proto = %d, nargs = %d\n",
3975 cum->prototype, cum->nargs_prototype);
3976 }
f676971a 3977
c4ad648e
AM		 3978 if (fntype
3979 && !TARGET_ALTIVEC
3980 && TARGET_ALTIVEC_ABI
3981 && ALTIVEC_VECTOR_MODE (TYPE_MODE (TREE_TYPE (fntype))))
3982 {
3983 error ("Cannot return value in vector register because"
3984 " altivec instructions are disabled, use -maltivec"
3985 " to enable them.");
3986 }
4697a36c
MM		 3987}
3988\f
fe984136
RH		 3989/* Return true if TYPE must be passed on the stack and not in registers. */
3990
3991static bool
3992rs6000_must_pass_in_stack (enum machine_mode mode, tree type)
3993{
3994 if (DEFAULT_ABI == ABI_AIX || TARGET_64BIT)
3995 return must_pass_in_stack_var_size (mode, type);
3996 else
3997 return must_pass_in_stack_var_size_or_pad (mode, type);
3998}
3999
c229cba9
DE		 4000/* If defined, a C expression which determines whether, and in which
4001 direction, to pad out an argument with extra space. The value
4002 should be of type `enum direction': either `upward' to pad above
4003 the argument, `downward' to pad below, or `none' to inhibit
4004 padding.
4005
4006 For the AIX ABI structs are always stored left shifted in their
4007 argument slot. */
4008
9ebbca7d 4009enum direction
a2369ed3 4010function_arg_padding (enum machine_mode mode, tree type)
c229cba9 4011{
6e985040
AM		 4012#ifndef AGGREGATE_PADDING_FIXED
4013#define AGGREGATE_PADDING_FIXED 0
4014#endif
4015#ifndef AGGREGATES_PAD_UPWARD_ALWAYS
4016#define AGGREGATES_PAD_UPWARD_ALWAYS 0
4017#endif
4018
4019 if (!AGGREGATE_PADDING_FIXED)
4020 {
4021 /* GCC used to pass structures of the same size as integer types as
4022 if they were in fact integers, ignoring FUNCTION_ARG_PADDING.
19525b57 4023 i.e. Structures of size 1 or 2 (or 4 when TARGET_64BIT) were
6e985040
AM		 4024 passed padded downward, except that -mstrict-align further
4025 muddied the water in that multi-component structures of 2 and 4
4026 bytes in size were passed padded upward.
4027
4028 The following arranges for best compatibility with previous
4029 versions of gcc, but removes the -mstrict-align dependency. */
4030 if (BYTES_BIG_ENDIAN)
4031 {
4032 HOST_WIDE_INT size = 0;
4033
4034 if (mode == BLKmode)
4035 {
4036 if (type && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST)
4037 size = int_size_in_bytes (type);
4038 }
4039 else
4040 size = GET_MODE_SIZE (mode);
4041
4042 if (size == 1 || size == 2 || size == 4)
4043 return downward;
4044 }
4045 return upward;
4046 }
4047
4048 if (AGGREGATES_PAD_UPWARD_ALWAYS)
4049 {
4050 if (type != 0 && AGGREGATE_TYPE_P (type))
4051 return upward;
4052 }
c229cba9 4053
d3704c46
KH		 4054 /* Fall back to the default. */
4055 return DEFAULT_FUNCTION_ARG_PADDING (mode, type);
c229cba9
DE		 4056}
4057
b6c9286a 4058/* If defined, a C expression that gives the alignment boundary, in bits,
f676971a 4059 of an argument with the specified mode and type. If it is not defined,
b6c9286a 4060 PARM_BOUNDARY is used for all arguments.
f676971a 4061
b693336b
PB		 4062 V.4 wants long longs to be double word aligned.
4063 Doubleword align SPE vectors.
4064 Quadword align Altivec vectors.
4065 Quadword align large synthetic vector types. */
b6c9286a
MM		 4066
4067int
b693336b 4068function_arg_boundary (enum machine_mode mode, tree type)
b6c9286a 4069{
4ed78545
AM		 4070 if (DEFAULT_ABI == ABI_V4 && GET_MODE_SIZE (mode) == 8)
4071 return 64;
ad630bef
DE		 4072 else if (SPE_VECTOR_MODE (mode)
4073 || (type && TREE_CODE (type) == VECTOR_TYPE
4074 && int_size_in_bytes (type) >= 8
4075 && int_size_in_bytes (type) < 16))
e1f83b4d 4076 return 64;
ad630bef
DE		 4077 else if (ALTIVEC_VECTOR_MODE (mode)
4078 || (type && TREE_CODE (type) == VECTOR_TYPE
4079 && int_size_in_bytes (type) >= 16))
0ac081f6 4080 return 128;
0b5383eb
DJ		 4081 else if (rs6000_darwin64_abi && mode == BLKmode
4082 && type && TYPE_ALIGN (type) > 64)
4083 return 128;
9ebbca7d 4084 else
b6c9286a 4085 return PARM_BOUNDARY;
b6c9286a 4086}
c53bdcf5 4087
294bd182
AM		 4088/* For a function parm of MODE and TYPE, return the starting word in
4089 the parameter area. NWORDS of the parameter area are already used. */
4090
4091static unsigned int
4092rs6000_parm_start (enum machine_mode mode, tree type, unsigned int nwords)
4093{
4094 unsigned int align;
4095 unsigned int parm_offset;
4096
4097 align = function_arg_boundary (mode, type) / PARM_BOUNDARY - 1;
4098 parm_offset = DEFAULT_ABI == ABI_V4 ? 2 : 6;
4099 return nwords + (-(parm_offset + nwords) & align);
4100}
4101
c53bdcf5
AM		 4102/* Compute the size (in words) of a function argument. */
4103
4104static unsigned long
4105rs6000_arg_size (enum machine_mode mode, tree type)
4106{
4107 unsigned long size;
4108
4109 if (mode != BLKmode)
4110 size = GET_MODE_SIZE (mode);
4111 else
4112 size = int_size_in_bytes (type);
4113
4114 if (TARGET_32BIT)
4115 return (size + 3) >> 2;
4116 else
4117 return (size + 7) >> 3;
4118}
b6c9286a 4119\f
0b5383eb 4120/* Use this to flush pending int fields. */
594a51fe
SS		 4121
4122static void
0b5383eb
DJ		 4123rs6000_darwin64_record_arg_advance_flush (CUMULATIVE_ARGS *cum,
4124 HOST_WIDE_INT bitpos)
594a51fe 4125{
0b5383eb
DJ		 4126 unsigned int startbit, endbit;
4127 int intregs, intoffset;
4128 enum machine_mode mode;
594a51fe 4129
0b5383eb
DJ		 4130 if (cum->intoffset == -1)
4131 return;
594a51fe 4132
0b5383eb
DJ		 4133 intoffset = cum->intoffset;
4134 cum->intoffset = -1;
4135
4136 if (intoffset % BITS_PER_WORD != 0)
4137 {
4138 mode = mode_for_size (BITS_PER_WORD - intoffset % BITS_PER_WORD,
4139 MODE_INT, 0);
4140 if (mode == BLKmode)
594a51fe 4141 {
0b5383eb
DJ		 4142 /* We couldn't find an appropriate mode, which happens,
4143 e.g., in packed structs when there are 3 bytes to load.
4144 Back intoffset back to the beginning of the word in this
4145 case. */
4146 intoffset = intoffset & -BITS_PER_WORD;
594a51fe 4147 }
594a51fe 4148 }
0b5383eb
DJ		 4149
4150 startbit = intoffset & -BITS_PER_WORD;
4151 endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD;
4152 intregs = (endbit - startbit) / BITS_PER_WORD;
4153 cum->words += intregs;
4154}
4155
4156/* The darwin64 ABI calls for us to recurse down through structs,
4157 looking for elements passed in registers. Unfortunately, we have
4158 to track int register count here also because of misalignments
4159 in powerpc alignment mode. */
4160
4161static void
4162rs6000_darwin64_record_arg_advance_recurse (CUMULATIVE_ARGS *cum,
4163 tree type,
4164 HOST_WIDE_INT startbitpos)
4165{
4166 tree f;
4167
4168 for (f = TYPE_FIELDS (type); f ; f = TREE_CHAIN (f))
4169 if (TREE_CODE (f) == FIELD_DECL)
4170 {
4171 HOST_WIDE_INT bitpos = startbitpos;
4172 tree ftype = TREE_TYPE (f);
4173 enum machine_mode mode = TYPE_MODE (ftype);
4174
4175 if (DECL_SIZE (f) != 0
4176 && host_integerp (bit_position (f), 1))
4177 bitpos += int_bit_position (f);
4178
4179 /* ??? FIXME: else assume zero offset. */
4180
4181 if (TREE_CODE (ftype) == RECORD_TYPE)
4182 rs6000_darwin64_record_arg_advance_recurse (cum, ftype, bitpos);
4183 else if (USE_FP_FOR_ARG_P (cum, mode, ftype))
4184 {
4185 rs6000_darwin64_record_arg_advance_flush (cum, bitpos);
4186 cum->fregno += (GET_MODE_SIZE (mode) + 7) >> 3;
4187 cum->words += (GET_MODE_SIZE (mode) + 7) >> 3;
4188 }
4189 else if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, 1))
4190 {
4191 rs6000_darwin64_record_arg_advance_flush (cum, bitpos);
4192 cum->vregno++;
4193 cum->words += 2;
4194 }
4195 else if (cum->intoffset == -1)
4196 cum->intoffset = bitpos;
4197 }
594a51fe
SS		 4198}
4199
4697a36c
MM		 4200/* Update the data in CUM to advance over an argument
4201 of mode MODE and data type TYPE.
b2d04ecf
AM		 4202 (TYPE is null for libcalls where that information may not be available.)
4203
4204 Note that for args passed by reference, function_arg will be called
4205 with MODE and TYPE set to that of the pointer to the arg, not the arg
4206 itself. */
4697a36c
MM		 4207
4208void
f676971a 4209function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
594a51fe 4210 tree type, int named, int depth)
4697a36c 4211{
0b5383eb
DJ		 4212 int size;
4213
594a51fe
SS		 4214 /* Only tick off an argument if we're not recursing. */
4215 if (depth == 0)
4216 cum->nargs_prototype--;
4697a36c 4217
ad630bef
DE		 4218 if (TARGET_ALTIVEC_ABI
4219 && (ALTIVEC_VECTOR_MODE (mode)
4220 || (type && TREE_CODE (type) == VECTOR_TYPE
4221 && int_size_in_bytes (type) == 16)))
0ac081f6 4222 {
4ed78545
AM		 4223 bool stack = false;
4224
2858f73a 4225 if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named))
c4ad648e 4226 {
6d0ef01e
HP		 4227 cum->vregno++;
4228 if (!TARGET_ALTIVEC)
4229 error ("Cannot pass argument in vector register because"
4230 " altivec instructions are disabled, use -maltivec"
4231 " to enable them.");
4ed78545
AM		 4232
4233 /* PowerPC64 Linux and AIX allocate GPRs for a vector argument
f676971a 4234 even if it is going to be passed in a vector register.
4ed78545
AM		 4235 Darwin does the same for variable-argument functions. */
4236 if ((DEFAULT_ABI == ABI_AIX && TARGET_64BIT)
4237 || (cum->stdarg && DEFAULT_ABI != ABI_V4))
4238 stack = true;
6d0ef01e 4239 }
4ed78545
AM		 4240 else
4241 stack = true;
4242
4243 if (stack)
c4ad648e 4244 {
a594a19c 4245 int align;
f676971a 4246
2858f73a
GK		 4247 /* Vector parameters must be 16-byte aligned. This places
4248 them at 2 mod 4 in terms of words in 32-bit mode, since
4249 the parameter save area starts at offset 24 from the
4250 stack. In 64-bit mode, they just have to start on an
4251 even word, since the parameter save area is 16-byte
4252 aligned. Space for GPRs is reserved even if the argument
4253 will be passed in memory. */
4254 if (TARGET_32BIT)
4ed78545 4255 align = (2 - cum->words) & 3;
2858f73a
GK		 4256 else
4257 align = cum->words & 1;
c53bdcf5 4258 cum->words += align + rs6000_arg_size (mode, type);
f676971a 4259
a594a19c
GK		 4260 if (TARGET_DEBUG_ARG)
4261 {
f676971a 4262 fprintf (stderr, "function_adv: words = %2d, align=%d, ",
a594a19c
GK		 4263 cum->words, align);
4264 fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s\n",
f676971a 4265 cum->nargs_prototype, cum->prototype,
2858f73a 4266 GET_MODE_NAME (mode));
a594a19c
GK		 4267 }
4268 }
0ac081f6 4269 }
a4b0320c 4270 else if (TARGET_SPE_ABI && TARGET_SPE && SPE_VECTOR_MODE (mode)
a6c9bed4
AH		 4271 && !cum->stdarg
4272 && cum->sysv_gregno <= GP_ARG_MAX_REG)
a4b0320c 4273 cum->sysv_gregno++;
594a51fe
SS		 4274
4275 else if (rs6000_darwin64_abi
4276 && mode == BLKmode
0b5383eb
DJ		 4277 && TREE_CODE (type) == RECORD_TYPE
4278 && (size = int_size_in_bytes (type)) > 0)
4279 {
4280 /* Variable sized types have size == -1 and are
4281 treated as if consisting entirely of ints.
4282 Pad to 16 byte boundary if needed. */
4283 if (TYPE_ALIGN (type) >= 2 * BITS_PER_WORD
4284 && (cum->words % 2) != 0)
4285 cum->words++;
4286 /* For varargs, we can just go up by the size of the struct. */
4287 if (!named)
4288 cum->words += (size + 7) / 8;
4289 else
4290 {
4291 /* It is tempting to say int register count just goes up by
4292 sizeof(type)/8, but this is wrong in a case such as
4293 { int; double; int; } [powerpc alignment]. We have to
4294 grovel through the fields for these too. */
4295 cum->intoffset = 0;
4296 rs6000_darwin64_record_arg_advance_recurse (cum, type, 0);
4297 rs6000_darwin64_record_arg_advance_flush (cum,
4298 size * BITS_PER_UNIT);
4299 }
4300 }
f607bc57 4301 else if (DEFAULT_ABI == ABI_V4)
4697a36c 4302 {
a3170dc6 4303 if (TARGET_HARD_FLOAT && TARGET_FPRS
4cc833b7 4304 && (mode == SFmode || mode == DFmode))
4697a36c 4305 {
4cc833b7
RH		 4306 if (cum->fregno <= FP_ARG_V4_MAX_REG)
4307 cum->fregno++;
4308 else
4309 {
4310 if (mode == DFmode)
c4ad648e 4311 cum->words += cum->words & 1;
c53bdcf5 4312 cum->words += rs6000_arg_size (mode, type);
4cc833b7 4313 }
4697a36c 4314 }
4cc833b7
RH		 4315 else
4316 {
b2d04ecf 4317 int n_words = rs6000_arg_size (mode, type);
4cc833b7
RH		 4318 int gregno = cum->sysv_gregno;
4319
4ed78545
AM		 4320 /* Long long and SPE vectors are put in (r3,r4), (r5,r6),
4321 (r7,r8) or (r9,r10). As does any other 2 word item such
4322 as complex int due to a historical mistake. */
4323 if (n_words == 2)
4324 gregno += (1 - gregno) & 1;
4cc833b7 4325
4ed78545 4326 /* Multi-reg args are not split between registers and stack. */
4cc833b7
RH		 4327 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
4328 {
4ed78545
AM		 4329 /* Long long and SPE vectors are aligned on the stack.
4330 So are other 2 word items such as complex int due to
4331 a historical mistake. */
4cc833b7
RH		 4332 if (n_words == 2)
4333 cum->words += cum->words & 1;
4334 cum->words += n_words;
4335 }
4697a36c 4336
4cc833b7
RH		 4337 /* Note: continuing to accumulate gregno past when we've started
4338 spilling to the stack indicates the fact that we've started
4339 spilling to the stack to expand_builtin_saveregs. */
4340 cum->sysv_gregno = gregno + n_words;
4341 }
4697a36c 4342
4cc833b7
RH		 4343 if (TARGET_DEBUG_ARG)
4344 {
4345 fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ",
4346 cum->words, cum->fregno);
4347 fprintf (stderr, "gregno = %2d, nargs = %4d, proto = %d, ",
4348 cum->sysv_gregno, cum->nargs_prototype, cum->prototype);
4349 fprintf (stderr, "mode = %4s, named = %d\n",
4350 GET_MODE_NAME (mode), named);
4351 }
4697a36c
MM		 4352 }
4353 else
4cc833b7 4354 {
b2d04ecf 4355 int n_words = rs6000_arg_size (mode, type);
294bd182
AM		 4356 int start_words = cum->words;
4357 int align_words = rs6000_parm_start (mode, type, start_words);
a4f6c312 4358
294bd182 4359 cum->words = align_words + n_words;
4697a36c 4360
a3170dc6
AH		 4361 if (GET_MODE_CLASS (mode) == MODE_FLOAT
4362 && TARGET_HARD_FLOAT && TARGET_FPRS)
c53bdcf5 4363 cum->fregno += (GET_MODE_SIZE (mode) + 7) >> 3;
4cc833b7
RH		 4364
4365 if (TARGET_DEBUG_ARG)
4366 {
4367 fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ",
4368 cum->words, cum->fregno);
4369 fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s, ",
4370 cum->nargs_prototype, cum->prototype, GET_MODE_NAME (mode));
594a51fe 4371 fprintf (stderr, "named = %d, align = %d, depth = %d\n",
294bd182 4372 named, align_words - start_words, depth);
4cc833b7
RH		 4373 }
4374 }
4697a36c 4375}
a6c9bed4 4376
f82f556d
AH		 4377static rtx
4378spe_build_register_parallel (enum machine_mode mode, int gregno)
4379{
54b695e7 4380 rtx r1, r3;
f82f556d 4381
37409796 4382 switch (mode)
f82f556d 4383 {
37409796 4384 case DFmode:
54b695e7
AH		 4385 r1 = gen_rtx_REG (DImode, gregno);
4386 r1 = gen_rtx_EXPR_LIST (VOIDmode, r1, const0_rtx);
4387 return gen_rtx_PARALLEL (mode, gen_rtvec (1, r1));
37409796
NS		 4388
4389 case DCmode:
54b695e7
AH		 4390 r1 = gen_rtx_REG (DImode, gregno);
4391 r1 = gen_rtx_EXPR_LIST (VOIDmode, r1, const0_rtx);
4392 r3 = gen_rtx_REG (DImode, gregno + 2);
4393 r3 = gen_rtx_EXPR_LIST (VOIDmode, r3, GEN_INT (8));
4394 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r3));
37409796
NS		 4395
4396 default:
4397 gcc_unreachable ();
f82f556d 4398 }
f82f556d 4399}
b78d48dd 4400
f82f556d 4401/* Determine where to put a SIMD argument on the SPE. */
a6c9bed4 4402static rtx
f676971a 4403rs6000_spe_function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
a2369ed3 4404 tree type)
a6c9bed4 4405{
f82f556d
AH		 4406 int gregno = cum->sysv_gregno;
4407
4408 /* On E500 v2, double arithmetic is done on the full 64-bit GPR, but
600e1f95 4409 are passed and returned in a pair of GPRs for ABI compatibility. */
18f63bfa 4410 if (TARGET_E500_DOUBLE && (mode == DFmode || mode == DCmode))
f82f556d 4411 {
b5870bee
AH		 4412 int n_words = rs6000_arg_size (mode, type);
4413
f82f556d 4414 /* Doubles go in an odd/even register pair (r5/r6, etc). */
b5870bee
AH		 4415 if (mode == DFmode)
4416 gregno += (1 - gregno) & 1;
f82f556d 4417
b5870bee
AH		 4418 /* Multi-reg args are not split between registers and stack. */
4419 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
f82f556d
AH		 4420 return NULL_RTX;
4421
4422 return spe_build_register_parallel (mode, gregno);
4423 }
a6c9bed4
AH		 4424 if (cum->stdarg)
4425 {
c53bdcf5 4426 int n_words = rs6000_arg_size (mode, type);
a6c9bed4
AH		 4427
4428 /* SPE vectors are put in odd registers. */
4429 if (n_words == 2 && (gregno & 1) == 0)
4430 gregno += 1;
4431
4432 if (gregno + n_words - 1 <= GP_ARG_MAX_REG)
4433 {
4434 rtx r1, r2;
4435 enum machine_mode m = SImode;
4436
4437 r1 = gen_rtx_REG (m, gregno);
4438 r1 = gen_rtx_EXPR_LIST (m, r1, const0_rtx);
4439 r2 = gen_rtx_REG (m, gregno + 1);
4440 r2 = gen_rtx_EXPR_LIST (m, r2, GEN_INT (4));
4441 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r2));
4442 }
4443 else
b78d48dd 4444 return NULL_RTX;
a6c9bed4
AH		 4445 }
4446 else
4447 {
f82f556d
AH		 4448 if (gregno <= GP_ARG_MAX_REG)
4449 return gen_rtx_REG (mode, gregno);
a6c9bed4 4450 else
b78d48dd 4451 return NULL_RTX;
a6c9bed4
AH		 4452 }
4453}
4454
0b5383eb
DJ		 4455/* A subroutine of rs6000_darwin64_record_arg. Assign the bits of the
4456 structure between cum->intoffset and bitpos to integer registers. */
594a51fe 4457
0b5383eb
DJ		 4458static void
4459rs6000_darwin64_record_arg_flush (CUMULATIVE_ARGS *cum,
4460 HOST_WIDE_INT bitpos, rtx rvec[], int *k)
594a51fe 4461{
0b5383eb
DJ		 4462 enum machine_mode mode;
4463 unsigned int regno;
4464 unsigned int startbit, endbit;
4465 int this_regno, intregs, intoffset;
4466 rtx reg;
594a51fe 4467
0b5383eb
DJ		 4468 if (cum->intoffset == -1)
4469 return;
4470
4471 intoffset = cum->intoffset;
4472 cum->intoffset = -1;
4473
4474 /* If this is the trailing part of a word, try to only load that
4475 much into the register. Otherwise load the whole register. Note
4476 that in the latter case we may pick up unwanted bits. It's not a
4477 problem at the moment but may wish to revisit. */
4478
4479 if (intoffset % BITS_PER_WORD != 0)
594a51fe 4480 {
0b5383eb
DJ		 4481 mode = mode_for_size (BITS_PER_WORD - intoffset % BITS_PER_WORD,
4482 MODE_INT, 0);
4483 if (mode == BLKmode)
4484 {
4485 /* We couldn't find an appropriate mode, which happens,
4486 e.g., in packed structs when there are 3 bytes to load.
4487 Back intoffset back to the beginning of the word in this
4488 case. */
4489 intoffset = intoffset & -BITS_PER_WORD;
4490 mode = word_mode;
4491 }
4492 }
4493 else
4494 mode = word_mode;
4495
4496 startbit = intoffset & -BITS_PER_WORD;
4497 endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD;
4498 intregs = (endbit - startbit) / BITS_PER_WORD;
4499 this_regno = cum->words + intoffset / BITS_PER_WORD;
4500
4501 if (intregs > 0 && intregs > GP_ARG_NUM_REG - this_regno)
4502 cum->use_stack = 1;
4503
4504 intregs = MIN (intregs, GP_ARG_NUM_REG - this_regno);
4505 if (intregs <= 0)
4506 return;
4507
4508 intoffset /= BITS_PER_UNIT;
4509 do
4510 {
4511 regno = GP_ARG_MIN_REG + this_regno;
4512 reg = gen_rtx_REG (mode, regno);
4513 rvec[(*k)++] =
4514 gen_rtx_EXPR_LIST (VOIDmode, reg, GEN_INT (intoffset));
4515
4516 this_regno += 1;
4517 intoffset = (intoffset | (UNITS_PER_WORD-1)) + 1;
4518 mode = word_mode;
4519 intregs -= 1;
4520 }
4521 while (intregs > 0);
4522}
4523
4524/* Recursive workhorse for the following. */
4525
4526static void
4527rs6000_darwin64_record_arg_recurse (CUMULATIVE_ARGS *cum, tree type,
4528 HOST_WIDE_INT startbitpos, rtx rvec[],
4529 int *k)
4530{
4531 tree f;
4532
4533 for (f = TYPE_FIELDS (type); f ; f = TREE_CHAIN (f))
4534 if (TREE_CODE (f) == FIELD_DECL)
4535 {
4536 HOST_WIDE_INT bitpos = startbitpos;
4537 tree ftype = TREE_TYPE (f);
4538 enum machine_mode mode = TYPE_MODE (ftype);
4539
4540 if (DECL_SIZE (f) != 0
4541 && host_integerp (bit_position (f), 1))
4542 bitpos += int_bit_position (f);
4543
4544 /* ??? FIXME: else assume zero offset. */
4545
4546 if (TREE_CODE (ftype) == RECORD_TYPE)
4547 rs6000_darwin64_record_arg_recurse (cum, ftype, bitpos, rvec, k);
4548 else if (cum->named && USE_FP_FOR_ARG_P (cum, mode, ftype))
594a51fe 4549 {
0b5383eb
DJ		 4550#if 0
4551 switch (mode)
594a51fe 4552 {
0b5383eb
DJ		 4553 case SCmode: mode = SFmode; break;
4554 case DCmode: mode = DFmode; break;
4555 case TCmode: mode = TFmode; break;
4556 default: break;
594a51fe 4557 }
0b5383eb
DJ		 4558#endif
4559 rs6000_darwin64_record_arg_flush (cum, bitpos, rvec, k);
4560 rvec[(*k)++]
4561 = gen_rtx_EXPR_LIST (VOIDmode,
4562 gen_rtx_REG (mode, cum->fregno++),
4563 GEN_INT (bitpos / BITS_PER_UNIT));
4564 if (mode == TFmode)
4565 cum->fregno++;
594a51fe 4566 }
0b5383eb
DJ		 4567 else if (cum->named && USE_ALTIVEC_FOR_ARG_P (cum, mode, ftype, 1))
4568 {
4569 rs6000_darwin64_record_arg_flush (cum, bitpos, rvec, k);
4570 rvec[(*k)++]
4571 = gen_rtx_EXPR_LIST (VOIDmode,
4572 gen_rtx_REG (mode, cum->vregno++),
4573 GEN_INT (bitpos / BITS_PER_UNIT));
4574 }
4575 else if (cum->intoffset == -1)
4576 cum->intoffset = bitpos;
4577 }
4578}
594a51fe 4579
0b5383eb
DJ		 4580/* For the darwin64 ABI, we want to construct a PARALLEL consisting of
4581 the register(s) to be used for each field and subfield of a struct
4582 being passed by value, along with the offset of where the
4583 register's value may be found in the block. FP fields go in FP
4584 register, vector fields go in vector registers, and everything
4585 else goes in int registers, packed as in memory.
8ff40a74 4586
0b5383eb
DJ		 4587 This code is also used for function return values. RETVAL indicates
4588 whether this is the case.
8ff40a74 4589
0b5383eb
DJ		 4590 Much of this is taken from the Sparc V9 port, which has a similar
4591 calling convention. */
594a51fe 4592
0b5383eb
DJ		 4593static rtx
4594rs6000_darwin64_record_arg (CUMULATIVE_ARGS *orig_cum, tree type,
4595 int named, bool retval)
4596{
4597 rtx rvec[FIRST_PSEUDO_REGISTER];
4598 int k = 1, kbase = 1;
4599 HOST_WIDE_INT typesize = int_size_in_bytes (type);
4600 /* This is a copy; modifications are not visible to our caller. */
4601 CUMULATIVE_ARGS copy_cum = *orig_cum;
4602 CUMULATIVE_ARGS *cum = &copy_cum;
4603
4604 /* Pad to 16 byte boundary if needed. */
4605 if (!retval && TYPE_ALIGN (type) >= 2 * BITS_PER_WORD
4606 && (cum->words % 2) != 0)
4607 cum->words++;
4608
4609 cum->intoffset = 0;
4610 cum->use_stack = 0;
4611 cum->named = named;
4612
4613 /* Put entries into rvec[] for individual FP and vector fields, and
4614 for the chunks of memory that go in int regs. Note we start at
4615 element 1; 0 is reserved for an indication of using memory, and
4616 may or may not be filled in below. */
4617 rs6000_darwin64_record_arg_recurse (cum, type, 0, rvec, &k);
4618 rs6000_darwin64_record_arg_flush (cum, typesize * BITS_PER_UNIT, rvec, &k);
4619
4620 /* If any part of the struct went on the stack put all of it there.
4621 This hack is because the generic code for
4622 FUNCTION_ARG_PARTIAL_NREGS cannot handle cases where the register
4623 parts of the struct are not at the beginning. */
4624 if (cum->use_stack)
4625 {
4626 if (retval)
4627 return NULL_RTX; /* doesn't go in registers at all */
4628 kbase = 0;
4629 rvec[0] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
4630 }
4631 if (k > 1 || cum->use_stack)
4632 return gen_rtx_PARALLEL (BLKmode, gen_rtvec_v (k - kbase, &rvec[kbase]));
594a51fe
SS		 4633 else
4634 return NULL_RTX;
4635}
4636
b78d48dd
FJ		 4637/* Determine where to place an argument in 64-bit mode with 32-bit ABI. */
4638
4639static rtx
ec6376ab 4640rs6000_mixed_function_arg (enum machine_mode mode, tree type, int align_words)
b78d48dd 4641{
ec6376ab
AM		 4642 int n_units;
4643 int i, k;
4644 rtx rvec[GP_ARG_NUM_REG + 1];
4645
4646 if (align_words >= GP_ARG_NUM_REG)
4647 return NULL_RTX;
4648
4649 n_units = rs6000_arg_size (mode, type);
4650
4651 /* Optimize the simple case where the arg fits in one gpr, except in
4652 the case of BLKmode due to assign_parms assuming that registers are
4653 BITS_PER_WORD wide. */
4654 if (n_units == 0
4655 || (n_units == 1 && mode != BLKmode))
4656 return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
4657
4658 k = 0;
4659 if (align_words + n_units > GP_ARG_NUM_REG)
4660 /* Not all of the arg fits in gprs. Say that it goes in memory too,
4661 using a magic NULL_RTX component.
4662 FIXME: This is not strictly correct. Only some of the arg
4663 belongs in memory, not all of it. However, there isn't any way
4664 to do this currently, apart from building rtx descriptions for
4665 the pieces of memory we want stored. Due to bugs in the generic
4666 code we can't use the normal function_arg_partial_nregs scheme
4667 with the PARALLEL arg description we emit here.
4668 In any case, the code to store the whole arg to memory is often
4669 more efficient than code to store pieces, and we know that space
4670 is available in the right place for the whole arg. */
78a52f11
RH		 4671 /* FIXME: This should be fixed since the conversion to
4672 TARGET_ARG_PARTIAL_BYTES. */
ec6376ab
AM		 4673 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
4674
4675 i = 0;
4676 do
36a454e1 4677 {
ec6376ab
AM		 4678 rtx r = gen_rtx_REG (SImode, GP_ARG_MIN_REG + align_words);
4679 rtx off = GEN_INT (i++ * 4);
4680 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
36a454e1 4681 }
ec6376ab
AM		 4682 while (++align_words < GP_ARG_NUM_REG && --n_units != 0);
4683
4684 return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec));
b78d48dd
FJ		 4685}
4686
4697a36c
MM		 4687/* Determine where to put an argument to a function.
4688 Value is zero to push the argument on the stack,
4689 or a hard register in which to store the argument.
4690
4691 MODE is the argument's machine mode.
4692 TYPE is the data type of the argument (as a tree).
4693 This is null for libcalls where that information may
4694 not be available.
4695 CUM is a variable of type CUMULATIVE_ARGS which gives info about
0b5383eb
DJ		 4696 the preceding args and about the function being called. It is
4697 not modified in this routine.
4697a36c
MM		 4698 NAMED is nonzero if this argument is a named parameter
4699 (otherwise it is an extra parameter matching an ellipsis).
4700
4701 On RS/6000 the first eight words of non-FP are normally in registers
4702 and the rest are pushed. Under AIX, the first 13 FP args are in registers.
4703 Under V.4, the first 8 FP args are in registers.
4704
4705 If this is floating-point and no prototype is specified, we use
4706 both an FP and integer register (or possibly FP reg and stack). Library
b9599e46 4707 functions (when CALL_LIBCALL is set) always have the proper types for args,
4697a36c 4708 so we can pass the FP value just in one register. emit_library_function
b2d04ecf
AM		 4709 doesn't support PARALLEL anyway.
4710
4711 Note that for args passed by reference, function_arg will be called
4712 with MODE and TYPE set to that of the pointer to the arg, not the arg
4713 itself. */
4697a36c 4714
9390387d 4715rtx
f676971a 4716function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
a2369ed3 4717 tree type, int named)
4697a36c 4718{
4cc833b7 4719 enum rs6000_abi abi = DEFAULT_ABI;
4697a36c 4720
a4f6c312
SS		 4721 /* Return a marker to indicate whether CR1 needs to set or clear the
4722 bit that V.4 uses to say fp args were passed in registers.
4723 Assume that we don't need the marker for software floating point,
4724 or compiler generated library calls. */
4697a36c
MM		 4725 if (mode == VOIDmode)
4726 {
f607bc57 4727 if (abi == ABI_V4
7509c759 4728 && cum->nargs_prototype < 0
b9599e46
FS		 4729 && (cum->call_cookie & CALL_LIBCALL) == 0
4730 && (cum->prototype || TARGET_NO_PROTOTYPE))
7509c759 4731 {
a3170dc6
AH		 4732 /* For the SPE, we need to crxor CR6 always. */
4733 if (TARGET_SPE_ABI)
4734 return GEN_INT (cum->call_cookie | CALL_V4_SET_FP_ARGS);
4735 else if (TARGET_HARD_FLOAT && TARGET_FPRS)
4736 return GEN_INT (cum->call_cookie
4737 | ((cum->fregno == FP_ARG_MIN_REG)
4738 ? CALL_V4_SET_FP_ARGS
4739 : CALL_V4_CLEAR_FP_ARGS));
7509c759 4740 }
4697a36c 4741
7509c759 4742 return GEN_INT (cum->call_cookie);
4697a36c
MM		 4743 }
4744
0b5383eb
DJ		 4745 if (rs6000_darwin64_abi && mode == BLKmode
4746 && TREE_CODE (type) == RECORD_TYPE)
8ff40a74 4747 {
0b5383eb 4748 rtx rslt = rs6000_darwin64_record_arg (cum, type, named, false);
8ff40a74
SS		 4749 if (rslt != NULL_RTX)
4750 return rslt;
4751 /* Else fall through to usual handling. */
4752 }
4753
2858f73a 4754 if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named))
c72d6c26
HP		 4755 if (TARGET_64BIT && ! cum->prototype)
4756 {
c4ad648e
AM		 4757 /* Vector parameters get passed in vector register
4758 and also in GPRs or memory, in absence of prototype. */
4759 int align_words;
4760 rtx slot;
4761 align_words = (cum->words + 1) & ~1;
4762
4763 if (align_words >= GP_ARG_NUM_REG)
4764 {
4765 slot = NULL_RTX;
4766 }
4767 else
4768 {
4769 slot = gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
4770 }
4771 return gen_rtx_PARALLEL (mode,
4772 gen_rtvec (2,
4773 gen_rtx_EXPR_LIST (VOIDmode,
4774 slot, const0_rtx),
4775 gen_rtx_EXPR_LIST (VOIDmode,
4776 gen_rtx_REG (mode, cum->vregno),
4777 const0_rtx)));
c72d6c26
HP		 4778 }
4779 else
4780 return gen_rtx_REG (mode, cum->vregno);
ad630bef
DE		 4781 else if (TARGET_ALTIVEC_ABI
4782 && (ALTIVEC_VECTOR_MODE (mode)
4783 || (type && TREE_CODE (type) == VECTOR_TYPE
4784 && int_size_in_bytes (type) == 16)))
0ac081f6 4785 {
2858f73a 4786 if (named || abi == ABI_V4)
a594a19c 4787 return NULL_RTX;
0ac081f6 4788 else
a594a19c
GK		 4789 {
4790 /* Vector parameters to varargs functions under AIX or Darwin
4791 get passed in memory and possibly also in GPRs. */
ec6376ab
AM		 4792 int align, align_words, n_words;
4793 enum machine_mode part_mode;
a594a19c
GK		 4794
4795 /* Vector parameters must be 16-byte aligned. This places them at
2858f73a
GK		 4796 2 mod 4 in terms of words in 32-bit mode, since the parameter
4797 save area starts at offset 24 from the stack. In 64-bit mode,
4798 they just have to start on an even word, since the parameter
4799 save area is 16-byte aligned. */
4800 if (TARGET_32BIT)
4ed78545 4801 align = (2 - cum->words) & 3;
2858f73a
GK		 4802 else
4803 align = cum->words & 1;
a594a19c
GK		 4804 align_words = cum->words + align;
4805
4806 /* Out of registers? Memory, then. */
4807 if (align_words >= GP_ARG_NUM_REG)
4808 return NULL_RTX;
ec6376ab
AM		 4809
4810 if (TARGET_32BIT && TARGET_POWERPC64)
4811 return rs6000_mixed_function_arg (mode, type, align_words);
4812
2858f73a
GK		 4813 /* The vector value goes in GPRs. Only the part of the
4814 value in GPRs is reported here. */
ec6376ab
AM		 4815 part_mode = mode;
4816 n_words = rs6000_arg_size (mode, type);
4817 if (align_words + n_words > GP_ARG_NUM_REG)
839a4992 4818 /* Fortunately, there are only two possibilities, the value
2858f73a
GK		 4819 is either wholly in GPRs or half in GPRs and half not. */
4820 part_mode = DImode;
ec6376ab
AM		 4821
4822 return gen_rtx_REG (part_mode, GP_ARG_MIN_REG + align_words);
a594a19c 4823 }
0ac081f6 4824 }
f82f556d
AH		 4825 else if (TARGET_SPE_ABI && TARGET_SPE
4826 && (SPE_VECTOR_MODE (mode)
18f63bfa
AH		 4827 || (TARGET_E500_DOUBLE && (mode == DFmode
4828 || mode == DCmode))))
a6c9bed4 4829 return rs6000_spe_function_arg (cum, mode, type);
594a51fe 4830
f607bc57 4831 else if (abi == ABI_V4)
4697a36c 4832 {
a3170dc6 4833 if (TARGET_HARD_FLOAT && TARGET_FPRS
4cc833b7
RH		 4834 && (mode == SFmode || mode == DFmode))
4835 {
4836 if (cum->fregno <= FP_ARG_V4_MAX_REG)
4837 return gen_rtx_REG (mode, cum->fregno);
4838 else
b78d48dd 4839 return NULL_RTX;
4cc833b7
RH		 4840 }
4841 else
4842 {
b2d04ecf 4843 int n_words = rs6000_arg_size (mode, type);
4cc833b7
RH		 4844 int gregno = cum->sysv_gregno;
4845
4ed78545
AM		 4846 /* Long long and SPE vectors are put in (r3,r4), (r5,r6),
4847 (r7,r8) or (r9,r10). As does any other 2 word item such
4848 as complex int due to a historical mistake. */
4849 if (n_words == 2)
4850 gregno += (1 - gregno) & 1;
4cc833b7 4851
4ed78545 4852 /* Multi-reg args are not split between registers and stack. */
ec6376ab 4853 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
b78d48dd 4854 return NULL_RTX;
ec6376ab
AM		 4855
4856 if (TARGET_32BIT && TARGET_POWERPC64)
4857 return rs6000_mixed_function_arg (mode, type,
4858 gregno - GP_ARG_MIN_REG);
4859 return gen_rtx_REG (mode, gregno);
4cc833b7 4860 }
4697a36c 4861 }
4cc833b7
RH		 4862 else
4863 {
294bd182 4864 int align_words = rs6000_parm_start (mode, type, cum->words);
b78d48dd 4865
2858f73a 4866 if (USE_FP_FOR_ARG_P (cum, mode, type))
4cc833b7 4867 {
ec6376ab
AM		 4868 rtx rvec[GP_ARG_NUM_REG + 1];
4869 rtx r;
4870 int k;
c53bdcf5
AM		 4871 bool needs_psave;
4872 enum machine_mode fmode = mode;
c53bdcf5
AM		 4873 unsigned long n_fpreg = (GET_MODE_SIZE (mode) + 7) >> 3;
4874
4875 if (cum->fregno + n_fpreg > FP_ARG_MAX_REG + 1)
4876 {
c53bdcf5
AM		 4877 /* Currently, we only ever need one reg here because complex
4878 doubles are split. */
37409796 4879 gcc_assert (cum->fregno == FP_ARG_MAX_REG && fmode == TFmode);
ec6376ab
AM		 4880
4881 /* Long double split over regs and memory. */
4882 fmode = DFmode;
c53bdcf5 4883 }
c53bdcf5
AM		 4884
4885 /* Do we also need to pass this arg in the parameter save
4886 area? */
4887 needs_psave = (type
4888 && (cum->nargs_prototype <= 0
4889 || (DEFAULT_ABI == ABI_AIX
de17c25f 4890 && TARGET_XL_COMPAT
c53bdcf5
AM		 4891 && align_words >= GP_ARG_NUM_REG)));
4892
4893 if (!needs_psave && mode == fmode)
ec6376ab 4894 return gen_rtx_REG (fmode, cum->fregno);
c53bdcf5 4895
ec6376ab 4896 k = 0;
c53bdcf5
AM		 4897 if (needs_psave)
4898 {
ec6376ab 4899 /* Describe the part that goes in gprs or the stack.
c53bdcf5 4900 This piece must come first, before the fprs. */
c53bdcf5
AM		 4901 if (align_words < GP_ARG_NUM_REG)
4902 {
4903 unsigned long n_words = rs6000_arg_size (mode, type);
ec6376ab
AM		 4904
4905 if (align_words + n_words > GP_ARG_NUM_REG
4906 || (TARGET_32BIT && TARGET_POWERPC64))
4907 {
4908 /* If this is partially on the stack, then we only
4909 include the portion actually in registers here. */
4910 enum machine_mode rmode = TARGET_32BIT ? SImode : DImode;
4911 rtx off;
2e6c9641 4912 int i=0;
c4ad648e
AM		 4913 if (align_words + n_words > GP_ARG_NUM_REG
4914 && (TARGET_32BIT && TARGET_POWERPC64))
4915 /* Not all of the arg fits in gprs. Say that it
4916 goes in memory too, using a magic NULL_RTX
4917 component. Also see comment in
4918 rs6000_mixed_function_arg for why the normal
4919 function_arg_partial_nregs scheme doesn't work
4920 in this case. */
4921 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX,
4922 const0_rtx);
ec6376ab
AM		 4923 do
4924 {
4925 r = gen_rtx_REG (rmode,
4926 GP_ARG_MIN_REG + align_words);
2e6c9641 4927 off = GEN_INT (i++ * GET_MODE_SIZE (rmode));
ec6376ab
AM		 4928 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
4929 }
4930 while (++align_words < GP_ARG_NUM_REG && --n_words != 0);
4931 }
4932 else
4933 {
4934 /* The whole arg fits in gprs. */
4935 r = gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
4936 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, const0_rtx);
4937 }
c53bdcf5 4938 }
ec6376ab
AM		 4939 else
4940 /* It's entirely in memory. */
4941 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
c53bdcf5
AM		 4942 }
4943
ec6376ab
AM		 4944 /* Describe where this piece goes in the fprs. */
4945 r = gen_rtx_REG (fmode, cum->fregno);
4946 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, const0_rtx);
4947
4948 return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec));
4cc833b7
RH		 4949 }
4950 else if (align_words < GP_ARG_NUM_REG)
b2d04ecf 4951 {
ec6376ab
AM		 4952 if (TARGET_32BIT && TARGET_POWERPC64)
4953 return rs6000_mixed_function_arg (mode, type, align_words);
b2d04ecf 4954
4eeca74f
AM		 4955 if (mode == BLKmode)
4956 mode = Pmode;
4957
b2d04ecf
AM		 4958 return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
4959 }
4cc833b7
RH		 4960 else
4961 return NULL_RTX;
4697a36c 4962 }
4697a36c
MM		 4963}
4964\f
ec6376ab 4965/* For an arg passed partly in registers and partly in memory, this is
fb63c729
AM		 4966 the number of bytes passed in registers. For args passed entirely in
4967 registers or entirely in memory, zero. When an arg is described by a
4968 PARALLEL, perhaps using more than one register type, this function
4969 returns the number of bytes used by the first element of the PARALLEL. */
4697a36c 4970
78a52f11
RH		 4971static int
4972rs6000_arg_partial_bytes (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4973 tree type, bool named)
4697a36c 4974{
c53bdcf5 4975 int ret = 0;
ec6376ab 4976 int align_words;
c53bdcf5 4977
f607bc57 4978 if (DEFAULT_ABI == ABI_V4)
4697a36c 4979 return 0;
4697a36c 4980
c53bdcf5
AM		 4981 if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named)
4982 && cum->nargs_prototype >= 0)
4983 return 0;
4984
0b5383eb
DJ		 4985 /* In this complicated case we just disable the partial_nregs code. */
4986 if (rs6000_darwin64_abi && mode == BLKmode
4987 && TREE_CODE (type) == RECORD_TYPE
4988 && int_size_in_bytes (type) > 0)
4989 return 0;
4990
294bd182 4991 align_words = rs6000_parm_start (mode, type, cum->words);
ec6376ab
AM		 4992
4993 if (USE_FP_FOR_ARG_P (cum, mode, type)
fb63c729
AM		 4994 /* If we are passing this arg in the fixed parameter save area
4995 (gprs or memory) as well as fprs, then this function should
4996 return the number of bytes passed in the parameter save area
4997 rather than bytes passed in fprs. */
ec6376ab
AM		 4998 && !(type
4999 && (cum->nargs_prototype <= 0
5000 || (DEFAULT_ABI == ABI_AIX
de17c25f 5001 && TARGET_XL_COMPAT
ec6376ab 5002 && align_words >= GP_ARG_NUM_REG))))
4697a36c 5003 {
c53bdcf5 5004 if (cum->fregno + ((GET_MODE_SIZE (mode) + 7) >> 3) > FP_ARG_MAX_REG + 1)
ac7e839c 5005 ret = (FP_ARG_MAX_REG + 1 - cum->fregno) * 8;
c53bdcf5 5006 else if (cum->nargs_prototype >= 0)
4697a36c
MM		 5007 return 0;
5008 }
5009
ec6376ab
AM		 5010 if (align_words < GP_ARG_NUM_REG
5011 && GP_ARG_NUM_REG < align_words + rs6000_arg_size (mode, type))
ac7e839c 5012 ret = (GP_ARG_NUM_REG - align_words) * (TARGET_32BIT ? 4 : 8);
78a52f11 5013
c53bdcf5 5014 if (ret != 0 && TARGET_DEBUG_ARG)
78a52f11 5015 fprintf (stderr, "rs6000_arg_partial_bytes: %d\n", ret);
4697a36c 5016
c53bdcf5 5017 return ret;
4697a36c
MM		 5018}
5019\f
5020/* A C expression that indicates when an argument must be passed by
5021 reference. If nonzero for an argument, a copy of that argument is
5022 made in memory and a pointer to the argument is passed instead of
5023 the argument itself. The pointer is passed in whatever way is
5024 appropriate for passing a pointer to that type.
5025
b2d04ecf
AM		 5026 Under V.4, aggregates and long double are passed by reference.
5027
5028 As an extension to all 32-bit ABIs, AltiVec vectors are passed by
5029 reference unless the AltiVec vector extension ABI is in force.
c8c99a68
DE		 5030
5031 As an extension to all ABIs, variable sized types are passed by
5032 reference. */
4697a36c 5033
8cd5a4e0 5034static bool
f676971a 5035rs6000_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
bada2eb8
DE		 5036 enum machine_mode mode, tree type,
5037 bool named ATTRIBUTE_UNUSED)
4697a36c 5038{
bada2eb8 5039 if (DEFAULT_ABI == ABI_V4 && mode == TFmode)
4697a36c
MM		 5040 {
5041 if (TARGET_DEBUG_ARG)
bada2eb8
DE		 5042 fprintf (stderr, "function_arg_pass_by_reference: V4 long double\n");
5043 return 1;
5044 }
5045
5046 if (!type)
5047 return 0;
4697a36c 5048
bada2eb8
DE		 5049 if (DEFAULT_ABI == ABI_V4 && AGGREGATE_TYPE_P (type))
5050 {
5051 if (TARGET_DEBUG_ARG)
5052 fprintf (stderr, "function_arg_pass_by_reference: V4 aggregate\n");
5053 return 1;
5054 }
5055
5056 if (int_size_in_bytes (type) < 0)
5057 {
5058 if (TARGET_DEBUG_ARG)
5059 fprintf (stderr, "function_arg_pass_by_reference: variable size\n");
5060 return 1;
5061 }
5062
5063 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
5064 modes only exist for GCC vector types if -maltivec. */
5065 if (TARGET_32BIT && !TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
5066 {
5067 if (TARGET_DEBUG_ARG)
5068 fprintf (stderr, "function_arg_pass_by_reference: AltiVec\n");
4697a36c
MM		 5069 return 1;
5070 }
b693336b
PB		 5071
5072 /* Pass synthetic vectors in memory. */
bada2eb8 5073 if (TREE_CODE (type) == VECTOR_TYPE
ad630bef 5074 && int_size_in_bytes (type) > (TARGET_ALTIVEC_ABI ? 16 : 8))
b693336b
PB		 5075 {
5076 static bool warned_for_pass_big_vectors = false;
5077 if (TARGET_DEBUG_ARG)
5078 fprintf (stderr, "function_arg_pass_by_reference: synthetic vector\n");
5079 if (!warned_for_pass_big_vectors)
5080 {
d4ee4d25 5081 warning (0, "GCC vector passed by reference: "
b693336b
PB		 5082 "non-standard ABI extension with no compatibility guarantee");
5083 warned_for_pass_big_vectors = true;
5084 }
5085 return 1;
5086 }
5087
b2d04ecf 5088 return 0;
4697a36c 5089}
5985c7a6
FJ		 5090
5091static void
2d9db8eb 5092rs6000_move_block_from_reg (int regno, rtx x, int nregs)
5985c7a6
FJ		 5093{
5094 int i;
5095 enum machine_mode reg_mode = TARGET_32BIT ? SImode : DImode;
5096
5097 if (nregs == 0)
5098 return;
5099
c4ad648e 5100 for (i = 0; i < nregs; i++)
5985c7a6 5101 {
9390387d 5102 rtx tem = adjust_address_nv (x, reg_mode, i * GET_MODE_SIZE (reg_mode));
5985c7a6 5103 if (reload_completed)
c4ad648e
AM		 5104 {
5105 if (! strict_memory_address_p (reg_mode, XEXP (tem, 0)))
5106 tem = NULL_RTX;
5107 else
5108 tem = simplify_gen_subreg (reg_mode, x, BLKmode,
9390387d 5109 i * GET_MODE_SIZE (reg_mode));
c4ad648e 5110 }
5985c7a6
FJ		 5111 else
5112 tem = replace_equiv_address (tem, XEXP (tem, 0));
5113
37409796 5114 gcc_assert (tem);
5985c7a6
FJ		 5115
5116 emit_move_insn (tem, gen_rtx_REG (reg_mode, regno + i));
5117 }
5118}
4697a36c
MM		 5119\f
5120/* Perform any needed actions needed for a function that is receiving a
f676971a 5121 variable number of arguments.
4697a36c
MM		 5122
5123 CUM is as above.
5124
5125 MODE and TYPE are the mode and type of the current parameter.
5126
5127 PRETEND_SIZE is a variable that should be set to the amount of stack
5128 that must be pushed by the prolog to pretend that our caller pushed
5129 it.
5130
5131 Normally, this macro will push all remaining incoming registers on the
5132 stack and set PRETEND_SIZE to the length of the registers pushed. */
5133
c6e8c921 5134static void
f676971a 5135setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
c4ad648e
AM		 5136 tree type, int *pretend_size ATTRIBUTE_UNUSED,
5137 int no_rtl)
4697a36c 5138{
4cc833b7
RH		 5139 CUMULATIVE_ARGS next_cum;
5140 int reg_size = TARGET_32BIT ? 4 : 8;
ca5adc63 5141 rtx save_area = NULL_RTX, mem;
dfafc897 5142 int first_reg_offset, set;
4697a36c 5143
f31bf321 5144 /* Skip the last named argument. */
d34c5b80 5145 next_cum = *cum;
594a51fe 5146 function_arg_advance (&next_cum, mode, type, 1, 0);
4cc833b7 5147
f607bc57 5148 if (DEFAULT_ABI == ABI_V4)
d34c5b80 5149 {
60e2d0ca 5150 if (! no_rtl)
2c4974b7 5151 save_area = plus_constant (virtual_stack_vars_rtx,
bd227acc 5152 - RS6000_VARARGS_SIZE);
4cc833b7
RH		 5153
5154 first_reg_offset = next_cum.sysv_gregno - GP_ARG_MIN_REG;
4697a36c 5155 }
60e2d0ca 5156 else
4697a36c 5157 {
d34c5b80 5158 first_reg_offset = next_cum.words;
4cc833b7 5159 save_area = virtual_incoming_args_rtx;
4697a36c 5160
fe984136 5161 if (targetm.calls.must_pass_in_stack (mode, type))
c53bdcf5 5162 first_reg_offset += rs6000_arg_size (TYPE_MODE (type), type);
4cc833b7 5163 }
4697a36c 5164
dfafc897 5165 set = get_varargs_alias_set ();
9d30f3c1
JJ		 5166 if (! no_rtl && first_reg_offset < GP_ARG_NUM_REG
5167 && cfun->va_list_gpr_size)
4cc833b7 5168 {
9d30f3c1
JJ		 5169 int nregs = GP_ARG_NUM_REG - first_reg_offset;
5170
5171 if (va_list_gpr_counter_field)
5172 {
5173 /* V4 va_list_gpr_size counts number of registers needed. */
5174 if (nregs > cfun->va_list_gpr_size)
5175 nregs = cfun->va_list_gpr_size;
5176 }
5177 else
5178 {
5179 /* char * va_list instead counts number of bytes needed. */
5180 if (nregs > cfun->va_list_gpr_size / reg_size)
5181 nregs = cfun->va_list_gpr_size / reg_size;
5182 }
5183
dfafc897 5184 mem = gen_rtx_MEM (BLKmode,
c4ad648e 5185 plus_constant (save_area,
dfafc897 5186 first_reg_offset * reg_size)),
ba4828e0 5187 set_mem_alias_set (mem, set);
8ac61af7 5188 set_mem_align (mem, BITS_PER_WORD);
dfafc897 5189
f676971a 5190 rs6000_move_block_from_reg (GP_ARG_MIN_REG + first_reg_offset, mem,
9d30f3c1 5191 nregs);
4697a36c
MM		 5192 }
5193
4697a36c 5194 /* Save FP registers if needed. */
f607bc57 5195 if (DEFAULT_ABI == ABI_V4
a3170dc6
AH		 5196 && TARGET_HARD_FLOAT && TARGET_FPRS
5197 && ! no_rtl
9d30f3c1
JJ		 5198 && next_cum.fregno <= FP_ARG_V4_MAX_REG
5199 && cfun->va_list_fpr_size)
4697a36c 5200 {
9d30f3c1 5201 int fregno = next_cum.fregno, nregs;
9ebbca7d 5202 rtx cr1 = gen_rtx_REG (CCmode, CR1_REGNO);
4cc833b7
RH		 5203 rtx lab = gen_label_rtx ();
5204 int off = (GP_ARG_NUM_REG * reg_size) + ((fregno - FP_ARG_MIN_REG) * 8);
4697a36c 5205
c4ad648e
AM		 5206 emit_jump_insn
5207 (gen_rtx_SET (VOIDmode,
5208 pc_rtx,
5209 gen_rtx_IF_THEN_ELSE (VOIDmode,
4cc833b7 5210 gen_rtx_NE (VOIDmode, cr1,
c4ad648e 5211 const0_rtx),
39403d82 5212 gen_rtx_LABEL_REF (VOIDmode, lab),
4697a36c
MM		 5213 pc_rtx)));
5214
9d30f3c1
JJ		 5215 for (nregs = 0;
5216 fregno <= FP_ARG_V4_MAX_REG && nregs < cfun->va_list_fpr_size;
5217 fregno++, off += 8, nregs++)
4cc833b7 5218 {
5496b36f 5219 mem = gen_rtx_MEM (DFmode, plus_constant (save_area, off));
c4ad648e 5220 set_mem_alias_set (mem, set);
94ff898d 5221 set_mem_align (mem, GET_MODE_ALIGNMENT (DFmode));
dfafc897 5222 emit_move_insn (mem, gen_rtx_REG (DFmode, fregno));
4697a36c 5223 }
4cc833b7
RH		 5224
5225 emit_label (lab);
4697a36c 5226 }
4697a36c 5227}
4697a36c 5228
dfafc897 5229/* Create the va_list data type. */
2c4974b7 5230
c35d187f
RH		 5231static tree
5232rs6000_build_builtin_va_list (void)
dfafc897 5233{
64c2816f 5234 tree f_gpr, f_fpr, f_res, f_ovf, f_sav, record, type_decl;
4697a36c 5235
9ebbca7d
GK		 5236 /* For AIX, prefer 'char *' because that's what the system
5237 header files like. */
f607bc57 5238 if (DEFAULT_ABI != ABI_V4)
9ebbca7d 5239 return build_pointer_type (char_type_node);
dfafc897 5240
f1e639b1 5241 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
bab45a51 5242 type_decl = build_decl (TYPE_DECL, get_identifier ("__va_list_tag"), record);
0f4fd75d 5243
f676971a 5244 f_gpr = build_decl (FIELD_DECL, get_identifier ("gpr"),
9ebbca7d 5245 unsigned_char_type_node);
f676971a 5246 f_fpr = build_decl (FIELD_DECL, get_identifier ("fpr"),
9ebbca7d 5247 unsigned_char_type_node);
64c2816f
DT		 5248 /* Give the two bytes of padding a name, so that -Wpadded won't warn on
5249 every user file. */
5250 f_res = build_decl (FIELD_DECL, get_identifier ("reserved"),
5251 short_unsigned_type_node);
dfafc897
FS		 5252 f_ovf = build_decl (FIELD_DECL, get_identifier ("overflow_arg_area"),
5253 ptr_type_node);
5254 f_sav = build_decl (FIELD_DECL, get_identifier ("reg_save_area"),
5255 ptr_type_node);
5256
9d30f3c1
JJ		 5257 va_list_gpr_counter_field = f_gpr;
5258 va_list_fpr_counter_field = f_fpr;
5259
dfafc897
FS		 5260 DECL_FIELD_CONTEXT (f_gpr) = record;
5261 DECL_FIELD_CONTEXT (f_fpr) = record;
64c2816f 5262 DECL_FIELD_CONTEXT (f_res) = record;
dfafc897
FS		 5263 DECL_FIELD_CONTEXT (f_ovf) = record;
5264 DECL_FIELD_CONTEXT (f_sav) = record;
5265
bab45a51
FS		 5266 TREE_CHAIN (record) = type_decl;
5267 TYPE_NAME (record) = type_decl;
dfafc897
FS		 5268 TYPE_FIELDS (record) = f_gpr;
5269 TREE_CHAIN (f_gpr) = f_fpr;
64c2816f
DT		 5270 TREE_CHAIN (f_fpr) = f_res;
5271 TREE_CHAIN (f_res) = f_ovf;
dfafc897
FS		 5272 TREE_CHAIN (f_ovf) = f_sav;
5273
5274 layout_type (record);
5275
5276 /* The correct type is an array type of one element. */
5277 return build_array_type (record, build_index_type (size_zero_node));
5278}
5279
5280/* Implement va_start. */
5281
5282void
a2369ed3 5283rs6000_va_start (tree valist, rtx nextarg)
4697a36c 5284{
dfafc897 5285 HOST_WIDE_INT words, n_gpr, n_fpr;
c566f9bd 5286 tree f_gpr, f_fpr, f_res, f_ovf, f_sav;
dfafc897 5287 tree gpr, fpr, ovf, sav, t;
2c4974b7 5288
dfafc897 5289 /* Only SVR4 needs something special. */
f607bc57 5290 if (DEFAULT_ABI != ABI_V4)
dfafc897 5291 {
e5faf155 5292 std_expand_builtin_va_start (valist, nextarg);
dfafc897
FS		 5293 return;
5294 }
5295
973a648b 5296 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
dfafc897 5297 f_fpr = TREE_CHAIN (f_gpr);
c566f9bd
DT		 5298 f_res = TREE_CHAIN (f_fpr);
5299 f_ovf = TREE_CHAIN (f_res);
dfafc897
FS		 5300 f_sav = TREE_CHAIN (f_ovf);
5301
872a65b5 5302 valist = build_va_arg_indirect_ref (valist);
44de5aeb
RK		 5303 gpr = build (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
5304 fpr = build (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
5305 ovf = build (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
5306 sav = build (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
dfafc897
FS		 5307
5308 /* Count number of gp and fp argument registers used. */
4cc833b7 5309 words = current_function_args_info.words;
987732e0
DE		 5310 n_gpr = MIN (current_function_args_info.sysv_gregno - GP_ARG_MIN_REG,
5311 GP_ARG_NUM_REG);
5312 n_fpr = MIN (current_function_args_info.fregno - FP_ARG_MIN_REG,
5313 FP_ARG_NUM_REG);
dfafc897
FS		 5314
5315 if (TARGET_DEBUG_ARG)
4a0a75dd
KG		 5316 fprintf (stderr, "va_start: words = "HOST_WIDE_INT_PRINT_DEC", n_gpr = "
5317 HOST_WIDE_INT_PRINT_DEC", n_fpr = "HOST_WIDE_INT_PRINT_DEC"\n",
5318 words, n_gpr, n_fpr);
dfafc897 5319
9d30f3c1
JJ		 5320 if (cfun->va_list_gpr_size)
5321 {
5322 t = build (MODIFY_EXPR, TREE_TYPE (gpr), gpr,
5323 build_int_cst (NULL_TREE, n_gpr));
5324 TREE_SIDE_EFFECTS (t) = 1;
5325 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5326 }
58c8adc1 5327
9d30f3c1
JJ		 5328 if (cfun->va_list_fpr_size)
5329 {
5330 t = build (MODIFY_EXPR, TREE_TYPE (fpr), fpr,
5331 build_int_cst (NULL_TREE, n_fpr));
5332 TREE_SIDE_EFFECTS (t) = 1;
5333 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5334 }
dfafc897
FS		 5335
5336 /* Find the overflow area. */
5337 t = make_tree (TREE_TYPE (ovf), virtual_incoming_args_rtx);
5338 if (words != 0)
5339 t = build (PLUS_EXPR, TREE_TYPE (ovf), t,
7d60be94 5340 build_int_cst (NULL_TREE, words * UNITS_PER_WORD));
dfafc897
FS		 5341 t = build (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t);
5342 TREE_SIDE_EFFECTS (t) = 1;
5343 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5344
9d30f3c1
JJ		 5345 /* If there were no va_arg invocations, don't set up the register
5346 save area. */
5347 if (!cfun->va_list_gpr_size
5348 && !cfun->va_list_fpr_size
5349 && n_gpr < GP_ARG_NUM_REG
5350 && n_fpr < FP_ARG_V4_MAX_REG)
5351 return;
5352
dfafc897
FS		 5353 /* Find the register save area. */
5354 t = make_tree (TREE_TYPE (sav), virtual_stack_vars_rtx);
5355 t = build (PLUS_EXPR, TREE_TYPE (sav), t,
7d60be94 5356 build_int_cst (NULL_TREE, -RS6000_VARARGS_SIZE));
dfafc897
FS		 5357 t = build (MODIFY_EXPR, TREE_TYPE (sav), sav, t);
5358 TREE_SIDE_EFFECTS (t) = 1;
5359 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5360}
5361
5362/* Implement va_arg. */
5363
23a60a04
JM		 5364tree
5365rs6000_gimplify_va_arg (tree valist, tree type, tree *pre_p, tree *post_p)
cd3ce9b4 5366{
cd3ce9b4
JM		 5367 tree f_gpr, f_fpr, f_res, f_ovf, f_sav;
5368 tree gpr, fpr, ovf, sav, reg, t, u;
08b0dc1b 5369 int size, rsize, n_reg, sav_ofs, sav_scale;
cd3ce9b4
JM		 5370 tree lab_false, lab_over, addr;
5371 int align;
5372 tree ptrtype = build_pointer_type (type);
5373
08b0dc1b
RH		 5374 if (pass_by_reference (NULL, TYPE_MODE (type), type, false))
5375 {
5376 t = rs6000_gimplify_va_arg (valist, ptrtype, pre_p, post_p);
872a65b5 5377 return build_va_arg_indirect_ref (t);
08b0dc1b
RH		 5378 }
5379
cd3ce9b4
JM		 5380 if (DEFAULT_ABI != ABI_V4)
5381 {
08b0dc1b 5382 if (targetm.calls.split_complex_arg && TREE_CODE (type) == COMPLEX_TYPE)
cd3ce9b4
JM		 5383 {
5384 tree elem_type = TREE_TYPE (type);
5385 enum machine_mode elem_mode = TYPE_MODE (elem_type);
5386 int elem_size = GET_MODE_SIZE (elem_mode);
5387
5388 if (elem_size < UNITS_PER_WORD)
5389 {
23a60a04 5390 tree real_part, imag_part;
cd3ce9b4
JM		 5391 tree post = NULL_TREE;
5392
23a60a04
JM		 5393 real_part = rs6000_gimplify_va_arg (valist, elem_type, pre_p,
5394 &post);
5395 /* Copy the value into a temporary, lest the formal temporary
5396 be reused out from under us. */
5397 real_part = get_initialized_tmp_var (real_part, pre_p, &post);
cd3ce9b4
JM		 5398 append_to_statement_list (post, pre_p);
5399
23a60a04
JM		 5400 imag_part = rs6000_gimplify_va_arg (valist, elem_type, pre_p,
5401 post_p);
cd3ce9b4 5402
23a60a04 5403 return build (COMPLEX_EXPR, type, real_part, imag_part);
cd3ce9b4
JM		 5404 }
5405 }
5406
23a60a04 5407 return std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
cd3ce9b4
JM		 5408 }
5409
5410 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
5411 f_fpr = TREE_CHAIN (f_gpr);
5412 f_res = TREE_CHAIN (f_fpr);
5413 f_ovf = TREE_CHAIN (f_res);
5414 f_sav = TREE_CHAIN (f_ovf);
5415
872a65b5 5416 valist = build_va_arg_indirect_ref (valist);
44de5aeb
RK		 5417 gpr = build (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
5418 fpr = build (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
5419 ovf = build (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
5420 sav = build (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
cd3ce9b4
JM		 5421
5422 size = int_size_in_bytes (type);
5423 rsize = (size + 3) / 4;
5424 align = 1;
5425
08b0dc1b
RH		 5426 if (TARGET_HARD_FLOAT && TARGET_FPRS
5427 && (TYPE_MODE (type) == SFmode || TYPE_MODE (type) == DFmode))
cd3ce9b4
JM		 5428 {
5429 /* FP args go in FP registers, if present. */
cd3ce9b4
JM		 5430 reg = fpr;
5431 n_reg = 1;
5432 sav_ofs = 8*4;
5433 sav_scale = 8;
5434 if (TYPE_MODE (type) == DFmode)
5435 align = 8;
5436 }
5437 else
5438 {
5439 /* Otherwise into GP registers. */
cd3ce9b4
JM		 5440 reg = gpr;
5441 n_reg = rsize;
5442 sav_ofs = 0;
5443 sav_scale = 4;
5444 if (n_reg == 2)
5445 align = 8;
5446 }
5447
5448 /* Pull the value out of the saved registers.... */
5449
5450 lab_over = NULL;
5451 addr = create_tmp_var (ptr_type_node, "addr");
5452 DECL_POINTER_ALIAS_SET (addr) = get_varargs_alias_set ();
5453
5454 /* AltiVec vectors never go in registers when -mabi=altivec. */
5455 if (TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (TYPE_MODE (type)))
5456 align = 16;
5457 else
5458 {
5459 lab_false = create_artificial_label ();
5460 lab_over = create_artificial_label ();
5461
5462 /* Long long and SPE vectors are aligned in the registers.
5463 As are any other 2 gpr item such as complex int due to a
5464 historical mistake. */
5465 u = reg;
5466 if (n_reg == 2)
5467 {
5468 u = build2 (BIT_AND_EXPR, TREE_TYPE (reg), reg,
95674810 5469 size_int (n_reg - 1));
cd3ce9b4
JM		 5470 u = build2 (POSTINCREMENT_EXPR, TREE_TYPE (reg), reg, u);
5471 }
5472
95674810 5473 t = fold_convert (TREE_TYPE (reg), size_int (8 - n_reg + 1));
cd3ce9b4
JM		 5474 t = build2 (GE_EXPR, boolean_type_node, u, t);
5475 u = build1 (GOTO_EXPR, void_type_node, lab_false);
5476 t = build3 (COND_EXPR, void_type_node, t, u, NULL_TREE);
5477 gimplify_and_add (t, pre_p);
5478
5479 t = sav;
5480 if (sav_ofs)
95674810 5481 t = build2 (PLUS_EXPR, ptr_type_node, sav, size_int (sav_ofs));
cd3ce9b4 5482
95674810 5483 u = build2 (POSTINCREMENT_EXPR, TREE_TYPE (reg), reg, size_int (n_reg));
cd3ce9b4 5484 u = build1 (CONVERT_EXPR, integer_type_node, u);
95674810 5485 u = build2 (MULT_EXPR, integer_type_node, u, size_int (sav_scale));
cd3ce9b4
JM		 5486 t = build2 (PLUS_EXPR, ptr_type_node, t, u);
5487
5488 t = build2 (MODIFY_EXPR, void_type_node, addr, t);
5489 gimplify_and_add (t, pre_p);
5490
5491 t = build1 (GOTO_EXPR, void_type_node, lab_over);
5492 gimplify_and_add (t, pre_p);
5493
5494 t = build1 (LABEL_EXPR, void_type_node, lab_false);
5495 append_to_statement_list (t, pre_p);
5496
5497 if (n_reg > 2)
5498 {
5499 /* Ensure that we don't find any more args in regs.
5500 Alignment has taken care of the n_reg == 2 case. */
95674810 5501 t = build (MODIFY_EXPR, TREE_TYPE (reg), reg, size_int (8));
cd3ce9b4
JM		 5502 gimplify_and_add (t, pre_p);
5503 }
5504 }
5505
5506 /* ... otherwise out of the overflow area. */
5507
5508 /* Care for on-stack alignment if needed. */
5509 t = ovf;
5510 if (align != 1)
5511 {
95674810 5512 t = build2 (PLUS_EXPR, TREE_TYPE (t), t, size_int (align - 1));
4a90aeeb 5513 t = build2 (BIT_AND_EXPR, TREE_TYPE (t), t,
7d60be94 5514 build_int_cst (NULL_TREE, -align));
cd3ce9b4
JM		 5515 }
5516 gimplify_expr (&t, pre_p, NULL, is_gimple_val, fb_rvalue);
5517
5518 u = build2 (MODIFY_EXPR, void_type_node, addr, t);
5519 gimplify_and_add (u, pre_p);
5520
95674810 5521 t = build2 (PLUS_EXPR, TREE_TYPE (t), t, size_int (size));
cd3ce9b4
JM		 5522 t = build2 (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t);
5523 gimplify_and_add (t, pre_p);
5524
5525 if (lab_over)
5526 {
5527 t = build1 (LABEL_EXPR, void_type_node, lab_over);
5528 append_to_statement_list (t, pre_p);
5529 }
5530
08b0dc1b 5531 addr = fold_convert (ptrtype, addr);
872a65b5 5532 return build_va_arg_indirect_ref (addr);
cd3ce9b4
JM		 5533}
5534
0ac081f6
AH		 5535/* Builtins. */
5536
58646b77
PB		 5537static void
5538def_builtin (int mask, const char *name, tree type, int code)
5539{
5540 if (mask & target_flags)
5541 {
5542 if (rs6000_builtin_decls[code])
5543 abort ();
5544
5545 rs6000_builtin_decls[code] =
5546 lang_hooks.builtin_function (name, type, code, BUILT_IN_MD,
5547 NULL, NULL_TREE);
5548 }
5549}
0ac081f6 5550
24408032
AH		 5551/* Simple ternary operations: VECd = foo (VECa, VECb, VECc). */
5552
2212663f 5553static const struct builtin_description bdesc_3arg[] =
24408032
AH		 5554{
5555 { MASK_ALTIVEC, CODE_FOR_altivec_vmaddfp, "__builtin_altivec_vmaddfp", ALTIVEC_BUILTIN_VMADDFP },
5556 { MASK_ALTIVEC, CODE_FOR_altivec_vmhaddshs, "__builtin_altivec_vmhaddshs", ALTIVEC_BUILTIN_VMHADDSHS },
5557 { MASK_ALTIVEC, CODE_FOR_altivec_vmhraddshs, "__builtin_altivec_vmhraddshs", ALTIVEC_BUILTIN_VMHRADDSHS },
5558 { MASK_ALTIVEC, CODE_FOR_altivec_vmladduhm, "__builtin_altivec_vmladduhm", ALTIVEC_BUILTIN_VMLADDUHM},
5559 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumubm, "__builtin_altivec_vmsumubm", ALTIVEC_BUILTIN_VMSUMUBM },
5560 { MASK_ALTIVEC, CODE_FOR_altivec_vmsummbm, "__builtin_altivec_vmsummbm", ALTIVEC_BUILTIN_VMSUMMBM },
5561 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumuhm, "__builtin_altivec_vmsumuhm", ALTIVEC_BUILTIN_VMSUMUHM },
5562 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumshm, "__builtin_altivec_vmsumshm", ALTIVEC_BUILTIN_VMSUMSHM },
5563 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumuhs, "__builtin_altivec_vmsumuhs", ALTIVEC_BUILTIN_VMSUMUHS },
5564 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumshs, "__builtin_altivec_vmsumshs", ALTIVEC_BUILTIN_VMSUMSHS },
f676971a 5565 { MASK_ALTIVEC, CODE_FOR_altivec_vnmsubfp, "__builtin_altivec_vnmsubfp", ALTIVEC_BUILTIN_VNMSUBFP },
aba5fb01
NS		 5566 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v4sf, "__builtin_altivec_vperm_4sf", ALTIVEC_BUILTIN_VPERM_4SF },
5567 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v4si, "__builtin_altivec_vperm_4si", ALTIVEC_BUILTIN_VPERM_4SI },
5568 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v8hi, "__builtin_altivec_vperm_8hi", ALTIVEC_BUILTIN_VPERM_8HI },
5569 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v16qi, "__builtin_altivec_vperm_16qi", ALTIVEC_BUILTIN_VPERM_16QI },
5570 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v4sf, "__builtin_altivec_vsel_4sf", ALTIVEC_BUILTIN_VSEL_4SF },
5571 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v4si, "__builtin_altivec_vsel_4si", ALTIVEC_BUILTIN_VSEL_4SI },
5572 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v8hi, "__builtin_altivec_vsel_8hi", ALTIVEC_BUILTIN_VSEL_8HI },
5573 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v16qi, "__builtin_altivec_vsel_16qi", ALTIVEC_BUILTIN_VSEL_16QI },
5574 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v16qi, "__builtin_altivec_vsldoi_16qi", ALTIVEC_BUILTIN_VSLDOI_16QI },
5575 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v8hi, "__builtin_altivec_vsldoi_8hi", ALTIVEC_BUILTIN_VSLDOI_8HI },
5576 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v4si, "__builtin_altivec_vsldoi_4si", ALTIVEC_BUILTIN_VSLDOI_4SI },
5577 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v4sf, "__builtin_altivec_vsldoi_4sf", ALTIVEC_BUILTIN_VSLDOI_4SF },
58646b77
PB		 5578
5579 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_madd", ALTIVEC_BUILTIN_VEC_MADD },
5580 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_madds", ALTIVEC_BUILTIN_VEC_MADDS },
5581 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mladd", ALTIVEC_BUILTIN_VEC_MLADD },
5582 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mradds", ALTIVEC_BUILTIN_VEC_MRADDS },
5583 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_msum", ALTIVEC_BUILTIN_VEC_MSUM },
5584 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumshm", ALTIVEC_BUILTIN_VEC_VMSUMSHM },
5585 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumuhm", ALTIVEC_BUILTIN_VEC_VMSUMUHM },
5586 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsummbm", ALTIVEC_BUILTIN_VEC_VMSUMMBM },
5587 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumubm", ALTIVEC_BUILTIN_VEC_VMSUMUBM },
5588 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_msums", ALTIVEC_BUILTIN_VEC_MSUMS },
5589 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumshs", ALTIVEC_BUILTIN_VEC_VMSUMSHS },
5590 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumuhs", ALTIVEC_BUILTIN_VEC_VMSUMUHS },
5591 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_nmsub", ALTIVEC_BUILTIN_VEC_NMSUB },
5592 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_perm", ALTIVEC_BUILTIN_VEC_PERM },
5593 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sel", ALTIVEC_BUILTIN_VEC_SEL },
24408032 5594};
2212663f 5595
95385cbb
AH		 5596/* DST operations: void foo (void *, const int, const char). */
5597
5598static const struct builtin_description bdesc_dst[] =
5599{
5600 { MASK_ALTIVEC, CODE_FOR_altivec_dst, "__builtin_altivec_dst", ALTIVEC_BUILTIN_DST },
5601 { MASK_ALTIVEC, CODE_FOR_altivec_dstt, "__builtin_altivec_dstt", ALTIVEC_BUILTIN_DSTT },
5602 { MASK_ALTIVEC, CODE_FOR_altivec_dstst, "__builtin_altivec_dstst", ALTIVEC_BUILTIN_DSTST },
58646b77
PB		 5603 { MASK_ALTIVEC, CODE_FOR_altivec_dststt, "__builtin_altivec_dststt", ALTIVEC_BUILTIN_DSTSTT },
5604
5605 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_dst", ALTIVEC_BUILTIN_VEC_DST },
5606 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_dstt", ALTIVEC_BUILTIN_VEC_DSTT },
5607 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_dstst", ALTIVEC_BUILTIN_VEC_DSTST },
5608 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_dststt", ALTIVEC_BUILTIN_VEC_DSTSTT }
95385cbb
AH		 5609};
5610
2212663f 5611/* Simple binary operations: VECc = foo (VECa, VECb). */
24408032 5612
a3170dc6 5613static struct builtin_description bdesc_2arg[] =
0ac081f6 5614{
f18c054f
DB		 5615 { MASK_ALTIVEC, CODE_FOR_addv16qi3, "__builtin_altivec_vaddubm", ALTIVEC_BUILTIN_VADDUBM },
5616 { MASK_ALTIVEC, CODE_FOR_addv8hi3, "__builtin_altivec_vadduhm", ALTIVEC_BUILTIN_VADDUHM },
5617 { MASK_ALTIVEC, CODE_FOR_addv4si3, "__builtin_altivec_vadduwm", ALTIVEC_BUILTIN_VADDUWM },
5618 { MASK_ALTIVEC, CODE_FOR_addv4sf3, "__builtin_altivec_vaddfp", ALTIVEC_BUILTIN_VADDFP },
0ac081f6
AH		 5619 { MASK_ALTIVEC, CODE_FOR_altivec_vaddcuw, "__builtin_altivec_vaddcuw", ALTIVEC_BUILTIN_VADDCUW },
5620 { MASK_ALTIVEC, CODE_FOR_altivec_vaddubs, "__builtin_altivec_vaddubs", ALTIVEC_BUILTIN_VADDUBS },
5621 { MASK_ALTIVEC, CODE_FOR_altivec_vaddsbs, "__builtin_altivec_vaddsbs", ALTIVEC_BUILTIN_VADDSBS },
5622 { MASK_ALTIVEC, CODE_FOR_altivec_vadduhs, "__builtin_altivec_vadduhs", ALTIVEC_BUILTIN_VADDUHS },
5623 { MASK_ALTIVEC, CODE_FOR_altivec_vaddshs, "__builtin_altivec_vaddshs", ALTIVEC_BUILTIN_VADDSHS },
5624 { MASK_ALTIVEC, CODE_FOR_altivec_vadduws, "__builtin_altivec_vadduws", ALTIVEC_BUILTIN_VADDUWS },
5625 { MASK_ALTIVEC, CODE_FOR_altivec_vaddsws, "__builtin_altivec_vaddsws", ALTIVEC_BUILTIN_VADDSWS },
f18c054f 5626 { MASK_ALTIVEC, CODE_FOR_andv4si3, "__builtin_altivec_vand", ALTIVEC_BUILTIN_VAND },
aba5fb01 5627 { MASK_ALTIVEC, CODE_FOR_andcv4si3, "__builtin_altivec_vandc", ALTIVEC_BUILTIN_VANDC },
0ac081f6
AH		 5628 { MASK_ALTIVEC, CODE_FOR_altivec_vavgub, "__builtin_altivec_vavgub", ALTIVEC_BUILTIN_VAVGUB },
5629 { MASK_ALTIVEC, CODE_FOR_altivec_vavgsb, "__builtin_altivec_vavgsb", ALTIVEC_BUILTIN_VAVGSB },
5630 { MASK_ALTIVEC, CODE_FOR_altivec_vavguh, "__builtin_altivec_vavguh", ALTIVEC_BUILTIN_VAVGUH },
5631 { MASK_ALTIVEC, CODE_FOR_altivec_vavgsh, "__builtin_altivec_vavgsh", ALTIVEC_BUILTIN_VAVGSH },
5632 { MASK_ALTIVEC, CODE_FOR_altivec_vavguw, "__builtin_altivec_vavguw", ALTIVEC_BUILTIN_VAVGUW },
5633 { MASK_ALTIVEC, CODE_FOR_altivec_vavgsw, "__builtin_altivec_vavgsw", ALTIVEC_BUILTIN_VAVGSW },
617e0e1d
DB		 5634 { MASK_ALTIVEC, CODE_FOR_altivec_vcfux, "__builtin_altivec_vcfux", ALTIVEC_BUILTIN_VCFUX },
5635 { MASK_ALTIVEC, CODE_FOR_altivec_vcfsx, "__builtin_altivec_vcfsx", ALTIVEC_BUILTIN_VCFSX },
0ac081f6
AH		 5636 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpbfp, "__builtin_altivec_vcmpbfp", ALTIVEC_BUILTIN_VCMPBFP },
5637 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequb, "__builtin_altivec_vcmpequb", ALTIVEC_BUILTIN_VCMPEQUB },
5638 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequh, "__builtin_altivec_vcmpequh", ALTIVEC_BUILTIN_VCMPEQUH },
5639 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequw, "__builtin_altivec_vcmpequw", ALTIVEC_BUILTIN_VCMPEQUW },
5640 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpeqfp, "__builtin_altivec_vcmpeqfp", ALTIVEC_BUILTIN_VCMPEQFP },
5641 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgefp, "__builtin_altivec_vcmpgefp", ALTIVEC_BUILTIN_VCMPGEFP },
5642 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtub, "__builtin_altivec_vcmpgtub", ALTIVEC_BUILTIN_VCMPGTUB },
5643 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsb, "__builtin_altivec_vcmpgtsb", ALTIVEC_BUILTIN_VCMPGTSB },
5644 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtuh, "__builtin_altivec_vcmpgtuh", ALTIVEC_BUILTIN_VCMPGTUH },
5645 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsh, "__builtin_altivec_vcmpgtsh", ALTIVEC_BUILTIN_VCMPGTSH },
5646 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtuw, "__builtin_altivec_vcmpgtuw", ALTIVEC_BUILTIN_VCMPGTUW },
5647 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsw, "__builtin_altivec_vcmpgtsw", ALTIVEC_BUILTIN_VCMPGTSW },
5648 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtfp, "__builtin_altivec_vcmpgtfp", ALTIVEC_BUILTIN_VCMPGTFP },
617e0e1d
DB		 5649 { MASK_ALTIVEC, CODE_FOR_altivec_vctsxs, "__builtin_altivec_vctsxs", ALTIVEC_BUILTIN_VCTSXS },
5650 { MASK_ALTIVEC, CODE_FOR_altivec_vctuxs, "__builtin_altivec_vctuxs", ALTIVEC_BUILTIN_VCTUXS },
f18c054f
DB		 5651 { MASK_ALTIVEC, CODE_FOR_umaxv16qi3, "__builtin_altivec_vmaxub", ALTIVEC_BUILTIN_VMAXUB },
5652 { MASK_ALTIVEC, CODE_FOR_smaxv16qi3, "__builtin_altivec_vmaxsb", ALTIVEC_BUILTIN_VMAXSB },
df966bff
AH		 5653 { MASK_ALTIVEC, CODE_FOR_umaxv8hi3, "__builtin_altivec_vmaxuh", ALTIVEC_BUILTIN_VMAXUH },
5654 { MASK_ALTIVEC, CODE_FOR_smaxv8hi3, "__builtin_altivec_vmaxsh", ALTIVEC_BUILTIN_VMAXSH },
5655 { MASK_ALTIVEC, CODE_FOR_umaxv4si3, "__builtin_altivec_vmaxuw", ALTIVEC_BUILTIN_VMAXUW },
5656 { MASK_ALTIVEC, CODE_FOR_smaxv4si3, "__builtin_altivec_vmaxsw", ALTIVEC_BUILTIN_VMAXSW },
5657 { MASK_ALTIVEC, CODE_FOR_smaxv4sf3, "__builtin_altivec_vmaxfp", ALTIVEC_BUILTIN_VMAXFP },
0ac081f6
AH		 5658 { MASK_ALTIVEC, CODE_FOR_altivec_vmrghb, "__builtin_altivec_vmrghb", ALTIVEC_BUILTIN_VMRGHB },
5659 { MASK_ALTIVEC, CODE_FOR_altivec_vmrghh, "__builtin_altivec_vmrghh", ALTIVEC_BUILTIN_VMRGHH },
5660 { MASK_ALTIVEC, CODE_FOR_altivec_vmrghw, "__builtin_altivec_vmrghw", ALTIVEC_BUILTIN_VMRGHW },
5661 { MASK_ALTIVEC, CODE_FOR_altivec_vmrglb, "__builtin_altivec_vmrglb", ALTIVEC_BUILTIN_VMRGLB },
5662 { MASK_ALTIVEC, CODE_FOR_altivec_vmrglh, "__builtin_altivec_vmrglh", ALTIVEC_BUILTIN_VMRGLH },
5663 { MASK_ALTIVEC, CODE_FOR_altivec_vmrglw, "__builtin_altivec_vmrglw", ALTIVEC_BUILTIN_VMRGLW },
f18c054f
DB		 5664 { MASK_ALTIVEC, CODE_FOR_uminv16qi3, "__builtin_altivec_vminub", ALTIVEC_BUILTIN_VMINUB },
5665 { MASK_ALTIVEC, CODE_FOR_sminv16qi3, "__builtin_altivec_vminsb", ALTIVEC_BUILTIN_VMINSB },
5666 { MASK_ALTIVEC, CODE_FOR_uminv8hi3, "__builtin_altivec_vminuh", ALTIVEC_BUILTIN_VMINUH },
5667 { MASK_ALTIVEC, CODE_FOR_sminv8hi3, "__builtin_altivec_vminsh", ALTIVEC_BUILTIN_VMINSH },
5668 { MASK_ALTIVEC, CODE_FOR_uminv4si3, "__builtin_altivec_vminuw", ALTIVEC_BUILTIN_VMINUW },
5669 { MASK_ALTIVEC, CODE_FOR_sminv4si3, "__builtin_altivec_vminsw", ALTIVEC_BUILTIN_VMINSW },
5670 { MASK_ALTIVEC, CODE_FOR_sminv4sf3, "__builtin_altivec_vminfp", ALTIVEC_BUILTIN_VMINFP },
0ac081f6
AH		 5671 { MASK_ALTIVEC, CODE_FOR_altivec_vmuleub, "__builtin_altivec_vmuleub", ALTIVEC_BUILTIN_VMULEUB },
5672 { MASK_ALTIVEC, CODE_FOR_altivec_vmulesb, "__builtin_altivec_vmulesb", ALTIVEC_BUILTIN_VMULESB },
5673 { MASK_ALTIVEC, CODE_FOR_altivec_vmuleuh, "__builtin_altivec_vmuleuh", ALTIVEC_BUILTIN_VMULEUH },
5674 { MASK_ALTIVEC, CODE_FOR_altivec_vmulesh, "__builtin_altivec_vmulesh", ALTIVEC_BUILTIN_VMULESH },
5675 { MASK_ALTIVEC, CODE_FOR_altivec_vmuloub, "__builtin_altivec_vmuloub", ALTIVEC_BUILTIN_VMULOUB },
5676 { MASK_ALTIVEC, CODE_FOR_altivec_vmulosb, "__builtin_altivec_vmulosb", ALTIVEC_BUILTIN_VMULOSB },
5677 { MASK_ALTIVEC, CODE_FOR_altivec_vmulouh, "__builtin_altivec_vmulouh", ALTIVEC_BUILTIN_VMULOUH },
5678 { MASK_ALTIVEC, CODE_FOR_altivec_vmulosh, "__builtin_altivec_vmulosh", ALTIVEC_BUILTIN_VMULOSH },
f96bc213 5679 { MASK_ALTIVEC, CODE_FOR_altivec_norv4si3, "__builtin_altivec_vnor", ALTIVEC_BUILTIN_VNOR },
f18c054f 5680 { MASK_ALTIVEC, CODE_FOR_iorv4si3, "__builtin_altivec_vor", ALTIVEC_BUILTIN_VOR },
0ac081f6
AH		 5681 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhum, "__builtin_altivec_vpkuhum", ALTIVEC_BUILTIN_VPKUHUM },
5682 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwum, "__builtin_altivec_vpkuwum", ALTIVEC_BUILTIN_VPKUWUM },
5683 { MASK_ALTIVEC, CODE_FOR_altivec_vpkpx, "__builtin_altivec_vpkpx", ALTIVEC_BUILTIN_VPKPX },
5684 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhss, "__builtin_altivec_vpkuhss", ALTIVEC_BUILTIN_VPKUHSS },
5685 { MASK_ALTIVEC, CODE_FOR_altivec_vpkshss, "__builtin_altivec_vpkshss", ALTIVEC_BUILTIN_VPKSHSS },
5686 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwss, "__builtin_altivec_vpkuwss", ALTIVEC_BUILTIN_VPKUWSS },
5687 { MASK_ALTIVEC, CODE_FOR_altivec_vpkswss, "__builtin_altivec_vpkswss", ALTIVEC_BUILTIN_VPKSWSS },
5688 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhus, "__builtin_altivec_vpkuhus", ALTIVEC_BUILTIN_VPKUHUS },
5689 { MASK_ALTIVEC, CODE_FOR_altivec_vpkshus, "__builtin_altivec_vpkshus", ALTIVEC_BUILTIN_VPKSHUS },
5690 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwus, "__builtin_altivec_vpkuwus", ALTIVEC_BUILTIN_VPKUWUS },
5691 { MASK_ALTIVEC, CODE_FOR_altivec_vpkswus, "__builtin_altivec_vpkswus", ALTIVEC_BUILTIN_VPKSWUS },
5692 { MASK_ALTIVEC, CODE_FOR_altivec_vrlb, "__builtin_altivec_vrlb", ALTIVEC_BUILTIN_VRLB },
5693 { MASK_ALTIVEC, CODE_FOR_altivec_vrlh, "__builtin_altivec_vrlh", ALTIVEC_BUILTIN_VRLH },
5694 { MASK_ALTIVEC, CODE_FOR_altivec_vrlw, "__builtin_altivec_vrlw", ALTIVEC_BUILTIN_VRLW },
5695 { MASK_ALTIVEC, CODE_FOR_altivec_vslb, "__builtin_altivec_vslb", ALTIVEC_BUILTIN_VSLB },
5696 { MASK_ALTIVEC, CODE_FOR_altivec_vslh, "__builtin_altivec_vslh", ALTIVEC_BUILTIN_VSLH },
5697 { MASK_ALTIVEC, CODE_FOR_altivec_vslw, "__builtin_altivec_vslw", ALTIVEC_BUILTIN_VSLW },
5698 { MASK_ALTIVEC, CODE_FOR_altivec_vsl, "__builtin_altivec_vsl", ALTIVEC_BUILTIN_VSL },
5699 { MASK_ALTIVEC, CODE_FOR_altivec_vslo, "__builtin_altivec_vslo", ALTIVEC_BUILTIN_VSLO },
2212663f
DB		 5700 { MASK_ALTIVEC, CODE_FOR_altivec_vspltb, "__builtin_altivec_vspltb", ALTIVEC_BUILTIN_VSPLTB },
5701 { MASK_ALTIVEC, CODE_FOR_altivec_vsplth, "__builtin_altivec_vsplth", ALTIVEC_BUILTIN_VSPLTH },
5702 { MASK_ALTIVEC, CODE_FOR_altivec_vspltw, "__builtin_altivec_vspltw", ALTIVEC_BUILTIN_VSPLTW },
3e0de9d1
DP		 5703 { MASK_ALTIVEC, CODE_FOR_lshrv16qi3, "__builtin_altivec_vsrb", ALTIVEC_BUILTIN_VSRB },
5704 { MASK_ALTIVEC, CODE_FOR_lshrv8hi3, "__builtin_altivec_vsrh", ALTIVEC_BUILTIN_VSRH },
5705 { MASK_ALTIVEC, CODE_FOR_lshrv4si3, "__builtin_altivec_vsrw", ALTIVEC_BUILTIN_VSRW },
5706 { MASK_ALTIVEC, CODE_FOR_ashrv16qi3, "__builtin_altivec_vsrab", ALTIVEC_BUILTIN_VSRAB },
5707 { MASK_ALTIVEC, CODE_FOR_ashrv8hi3, "__builtin_altivec_vsrah", ALTIVEC_BUILTIN_VSRAH },
5708 { MASK_ALTIVEC, CODE_FOR_ashrv4si3, "__builtin_altivec_vsraw", ALTIVEC_BUILTIN_VSRAW },
0ac081f6
AH		 5709 { MASK_ALTIVEC, CODE_FOR_altivec_vsr, "__builtin_altivec_vsr", ALTIVEC_BUILTIN_VSR },
5710 { MASK_ALTIVEC, CODE_FOR_altivec_vsro, "__builtin_altivec_vsro", ALTIVEC_BUILTIN_VSRO },
f18c054f
DB		 5711 { MASK_ALTIVEC, CODE_FOR_subv16qi3, "__builtin_altivec_vsububm", ALTIVEC_BUILTIN_VSUBUBM },
5712 { MASK_ALTIVEC, CODE_FOR_subv8hi3, "__builtin_altivec_vsubuhm", ALTIVEC_BUILTIN_VSUBUHM },
5713 { MASK_ALTIVEC, CODE_FOR_subv4si3, "__builtin_altivec_vsubuwm", ALTIVEC_BUILTIN_VSUBUWM },
5714 { MASK_ALTIVEC, CODE_FOR_subv4sf3, "__builtin_altivec_vsubfp", ALTIVEC_BUILTIN_VSUBFP },
0ac081f6
AH		 5715 { MASK_ALTIVEC, CODE_FOR_altivec_vsubcuw, "__builtin_altivec_vsubcuw", ALTIVEC_BUILTIN_VSUBCUW },
5716 { MASK_ALTIVEC, CODE_FOR_altivec_vsububs, "__builtin_altivec_vsububs", ALTIVEC_BUILTIN_VSUBUBS },
5717 { MASK_ALTIVEC, CODE_FOR_altivec_vsubsbs, "__builtin_altivec_vsubsbs", ALTIVEC_BUILTIN_VSUBSBS },
5718 { MASK_ALTIVEC, CODE_FOR_altivec_vsubuhs, "__builtin_altivec_vsubuhs", ALTIVEC_BUILTIN_VSUBUHS },
5719 { MASK_ALTIVEC, CODE_FOR_altivec_vsubshs, "__builtin_altivec_vsubshs", ALTIVEC_BUILTIN_VSUBSHS },
5720 { MASK_ALTIVEC, CODE_FOR_altivec_vsubuws, "__builtin_altivec_vsubuws", ALTIVEC_BUILTIN_VSUBUWS },
5721 { MASK_ALTIVEC, CODE_FOR_altivec_vsubsws, "__builtin_altivec_vsubsws", ALTIVEC_BUILTIN_VSUBSWS },
5722 { MASK_ALTIVEC, CODE_FOR_altivec_vsum4ubs, "__builtin_altivec_vsum4ubs", ALTIVEC_BUILTIN_VSUM4UBS },
5723 { MASK_ALTIVEC, CODE_FOR_altivec_vsum4sbs, "__builtin_altivec_vsum4sbs", ALTIVEC_BUILTIN_VSUM4SBS },
5724 { MASK_ALTIVEC, CODE_FOR_altivec_vsum4shs, "__builtin_altivec_vsum4shs", ALTIVEC_BUILTIN_VSUM4SHS },
5725 { MASK_ALTIVEC, CODE_FOR_altivec_vsum2sws, "__builtin_altivec_vsum2sws", ALTIVEC_BUILTIN_VSUM2SWS },
5726 { MASK_ALTIVEC, CODE_FOR_altivec_vsumsws, "__builtin_altivec_vsumsws", ALTIVEC_BUILTIN_VSUMSWS },
f18c054f 5727 { MASK_ALTIVEC, CODE_FOR_xorv4si3, "__builtin_altivec_vxor", ALTIVEC_BUILTIN_VXOR },
a3170dc6 5728
58646b77
PB		 5729 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_add", ALTIVEC_BUILTIN_VEC_ADD },
5730 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddfp", ALTIVEC_BUILTIN_VEC_VADDFP },
5731 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vadduwm", ALTIVEC_BUILTIN_VEC_VADDUWM },
5732 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vadduhm", ALTIVEC_BUILTIN_VEC_VADDUHM },
5733 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddubm", ALTIVEC_BUILTIN_VEC_VADDUBM },
5734 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_addc", ALTIVEC_BUILTIN_VEC_ADDC },
5735 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_adds", ALTIVEC_BUILTIN_VEC_ADDS },
5736 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddsws", ALTIVEC_BUILTIN_VEC_VADDSWS },
5737 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vadduws", ALTIVEC_BUILTIN_VEC_VADDUWS },
5738 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddshs", ALTIVEC_BUILTIN_VEC_VADDSHS },
5739 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vadduhs", ALTIVEC_BUILTIN_VEC_VADDUHS },
5740 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddsbs", ALTIVEC_BUILTIN_VEC_VADDSBS },
5741 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddubs", ALTIVEC_BUILTIN_VEC_VADDUBS },
5742 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_and", ALTIVEC_BUILTIN_VEC_AND },
5743 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_andc", ALTIVEC_BUILTIN_VEC_ANDC },
5744 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_avg", ALTIVEC_BUILTIN_VEC_AVG },
5745 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavgsw", ALTIVEC_BUILTIN_VEC_VAVGSW },
5746 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavguw", ALTIVEC_BUILTIN_VEC_VAVGUW },
5747 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavgsh", ALTIVEC_BUILTIN_VEC_VAVGSH },
5748 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavguh", ALTIVEC_BUILTIN_VEC_VAVGUH },
5749 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavgsb", ALTIVEC_BUILTIN_VEC_VAVGSB },
5750 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavgub", ALTIVEC_BUILTIN_VEC_VAVGUB },
5751 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmpb", ALTIVEC_BUILTIN_VEC_CMPB },
5752 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmpeq", ALTIVEC_BUILTIN_VEC_CMPEQ },
5753 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpeqfp", ALTIVEC_BUILTIN_VEC_VCMPEQFP },
5754 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpequw", ALTIVEC_BUILTIN_VEC_VCMPEQUW },
5755 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpequh", ALTIVEC_BUILTIN_VEC_VCMPEQUH },
5756 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpequb", ALTIVEC_BUILTIN_VEC_VCMPEQUB },
5757 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmpge", ALTIVEC_BUILTIN_VEC_CMPGE },
5758 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmpgt", ALTIVEC_BUILTIN_VEC_CMPGT },
5759 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtfp", ALTIVEC_BUILTIN_VEC_VCMPGTFP },
5760 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtsw", ALTIVEC_BUILTIN_VEC_VCMPGTSW },
5761 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtuw", ALTIVEC_BUILTIN_VEC_VCMPGTUW },
5762 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtsh", ALTIVEC_BUILTIN_VEC_VCMPGTSH },
5763 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtuh", ALTIVEC_BUILTIN_VEC_VCMPGTUH },
5764 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtsb", ALTIVEC_BUILTIN_VEC_VCMPGTSB },
5765 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtub", ALTIVEC_BUILTIN_VEC_VCMPGTUB },
5766 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmple", ALTIVEC_BUILTIN_VEC_CMPLE },
5767 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmplt", ALTIVEC_BUILTIN_VEC_CMPLT },
5768 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_max", ALTIVEC_BUILTIN_VEC_MAX },
5769 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxfp", ALTIVEC_BUILTIN_VEC_VMAXFP },
5770 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxsw", ALTIVEC_BUILTIN_VEC_VMAXSW },
5771 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxuw", ALTIVEC_BUILTIN_VEC_VMAXUW },
5772 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxsh", ALTIVEC_BUILTIN_VEC_VMAXSH },
5773 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxuh", ALTIVEC_BUILTIN_VEC_VMAXUH },
5774 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxsb", ALTIVEC_BUILTIN_VEC_VMAXSB },
5775 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxub", ALTIVEC_BUILTIN_VEC_VMAXUB },
5776 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mergeh", ALTIVEC_BUILTIN_VEC_MERGEH },
5777 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrghw", ALTIVEC_BUILTIN_VEC_VMRGHW },
5778 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrghh", ALTIVEC_BUILTIN_VEC_VMRGHH },
5779 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrghb", ALTIVEC_BUILTIN_VEC_VMRGHB },
5780 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mergel", ALTIVEC_BUILTIN_VEC_MERGEL },
5781 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrglw", ALTIVEC_BUILTIN_VEC_VMRGLW },
5782 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrglh", ALTIVEC_BUILTIN_VEC_VMRGLH },
5783 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrglb", ALTIVEC_BUILTIN_VEC_VMRGLB },
5784 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_min", ALTIVEC_BUILTIN_VEC_MIN },
5785 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminfp", ALTIVEC_BUILTIN_VEC_VMINFP },
5786 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminsw", ALTIVEC_BUILTIN_VEC_VMINSW },
5787 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminuw", ALTIVEC_BUILTIN_VEC_VMINUW },
5788 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminsh", ALTIVEC_BUILTIN_VEC_VMINSH },
5789 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminuh", ALTIVEC_BUILTIN_VEC_VMINUH },
5790 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminsb", ALTIVEC_BUILTIN_VEC_VMINSB },
5791 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminub", ALTIVEC_BUILTIN_VEC_VMINUB },
5792 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mule", ALTIVEC_BUILTIN_VEC_MULE },
5793 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmuleub", ALTIVEC_BUILTIN_VEC_VMULEUB },
5794 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulesb", ALTIVEC_BUILTIN_VEC_VMULESB },
5795 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmuleuh", ALTIVEC_BUILTIN_VEC_VMULEUH },
5796 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulesh", ALTIVEC_BUILTIN_VEC_VMULESH },
5797 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mulo", ALTIVEC_BUILTIN_VEC_MULO },
5798 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulosh", ALTIVEC_BUILTIN_VEC_VMULOSH },
5799 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulouh", ALTIVEC_BUILTIN_VEC_VMULOUH },
5800 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulosb", ALTIVEC_BUILTIN_VEC_VMULOSB },
5801 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmuloub", ALTIVEC_BUILTIN_VEC_VMULOUB },
5802 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_nor", ALTIVEC_BUILTIN_VEC_NOR },
5803 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_or", ALTIVEC_BUILTIN_VEC_OR },
5804 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_pack", ALTIVEC_BUILTIN_VEC_PACK },
5805 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkuwum", ALTIVEC_BUILTIN_VEC_VPKUWUM },
5806 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkuhum", ALTIVEC_BUILTIN_VEC_VPKUHUM },
5807 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_packpx", ALTIVEC_BUILTIN_VEC_PACKPX },
5808 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_packs", ALTIVEC_BUILTIN_VEC_PACKS },
5809 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkswss", ALTIVEC_BUILTIN_VEC_VPKSWSS },
5810 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkuwus", ALTIVEC_BUILTIN_VEC_VPKUWUS },
5811 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkshss", ALTIVEC_BUILTIN_VEC_VPKSHSS },
5812 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkuhus", ALTIVEC_BUILTIN_VEC_VPKUHUS },
5813 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_packsu", ALTIVEC_BUILTIN_VEC_PACKSU },
5814 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkswus", ALTIVEC_BUILTIN_VEC_VPKSWUS },
5815 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkshus", ALTIVEC_BUILTIN_VEC_VPKSHUS },
5816 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_rl", ALTIVEC_BUILTIN_VEC_RL },
5817 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vrlw", ALTIVEC_BUILTIN_VEC_VRLW },
5818 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vrlh", ALTIVEC_BUILTIN_VEC_VRLH },
5819 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vrlb", ALTIVEC_BUILTIN_VEC_VRLB },
5820 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sl", ALTIVEC_BUILTIN_VEC_SL },
5821 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vslw", ALTIVEC_BUILTIN_VEC_VSLW },
5822 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vslh", ALTIVEC_BUILTIN_VEC_VSLH },
5823 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vslb", ALTIVEC_BUILTIN_VEC_VSLB },
5824 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sll", ALTIVEC_BUILTIN_VEC_SLL },
5825 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_slo", ALTIVEC_BUILTIN_VEC_SLO },
5826 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sr", ALTIVEC_BUILTIN_VEC_SR },
5827 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrw", ALTIVEC_BUILTIN_VEC_VSRW },
5828 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrh", ALTIVEC_BUILTIN_VEC_VSRH },
5829 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrb", ALTIVEC_BUILTIN_VEC_VSRB },
5830 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sra", ALTIVEC_BUILTIN_VEC_SRA },
5831 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsraw", ALTIVEC_BUILTIN_VEC_VSRAW },
5832 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrah", ALTIVEC_BUILTIN_VEC_VSRAH },
5833 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrab", ALTIVEC_BUILTIN_VEC_VSRAB },
5834 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_srl", ALTIVEC_BUILTIN_VEC_SRL },
5835 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sro", ALTIVEC_BUILTIN_VEC_SRO },
5836 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sub", ALTIVEC_BUILTIN_VEC_SUB },
5837 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubfp", ALTIVEC_BUILTIN_VEC_VSUBFP },
5838 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubuwm", ALTIVEC_BUILTIN_VEC_VSUBUWM },
5839 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubuhm", ALTIVEC_BUILTIN_VEC_VSUBUHM },
5840 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsububm", ALTIVEC_BUILTIN_VEC_VSUBUBM },
5841 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_subc", ALTIVEC_BUILTIN_VEC_SUBC },
5842 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_subs", ALTIVEC_BUILTIN_VEC_SUBS },
5843 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubsws", ALTIVEC_BUILTIN_VEC_VSUBSWS },
5844 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubuws", ALTIVEC_BUILTIN_VEC_VSUBUWS },
5845 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubshs", ALTIVEC_BUILTIN_VEC_VSUBSHS },
5846 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubuhs", ALTIVEC_BUILTIN_VEC_VSUBUHS },
5847 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubsbs", ALTIVEC_BUILTIN_VEC_VSUBSBS },
5848 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsububs", ALTIVEC_BUILTIN_VEC_VSUBUBS },
5849 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sum4s", ALTIVEC_BUILTIN_VEC_SUM4S },
5850 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsum4shs", ALTIVEC_BUILTIN_VEC_VSUM4SHS },
5851 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsum4sbs", ALTIVEC_BUILTIN_VEC_VSUM4SBS },
5852 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsum4ubs", ALTIVEC_BUILTIN_VEC_VSUM4UBS },
5853 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sum2s", ALTIVEC_BUILTIN_VEC_SUM2S },
5854 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sums", ALTIVEC_BUILTIN_VEC_SUMS },
5855 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_xor", ALTIVEC_BUILTIN_VEC_XOR },
5856
a3170dc6
AH		 5857 /* Place holder, leave as first spe builtin. */
5858 { 0, CODE_FOR_spe_evaddw, "__builtin_spe_evaddw", SPE_BUILTIN_EVADDW },
5859 { 0, CODE_FOR_spe_evand, "__builtin_spe_evand", SPE_BUILTIN_EVAND },
5860 { 0, CODE_FOR_spe_evandc, "__builtin_spe_evandc", SPE_BUILTIN_EVANDC },
5861 { 0, CODE_FOR_spe_evdivws, "__builtin_spe_evdivws", SPE_BUILTIN_EVDIVWS },
5862 { 0, CODE_FOR_spe_evdivwu, "__builtin_spe_evdivwu", SPE_BUILTIN_EVDIVWU },
5863 { 0, CODE_FOR_spe_eveqv, "__builtin_spe_eveqv", SPE_BUILTIN_EVEQV },
5864 { 0, CODE_FOR_spe_evfsadd, "__builtin_spe_evfsadd", SPE_BUILTIN_EVFSADD },
5865 { 0, CODE_FOR_spe_evfsdiv, "__builtin_spe_evfsdiv", SPE_BUILTIN_EVFSDIV },
5866 { 0, CODE_FOR_spe_evfsmul, "__builtin_spe_evfsmul", SPE_BUILTIN_EVFSMUL },
5867 { 0, CODE_FOR_spe_evfssub, "__builtin_spe_evfssub", SPE_BUILTIN_EVFSSUB },
5868 { 0, CODE_FOR_spe_evmergehi, "__builtin_spe_evmergehi", SPE_BUILTIN_EVMERGEHI },
5869 { 0, CODE_FOR_spe_evmergehilo, "__builtin_spe_evmergehilo", SPE_BUILTIN_EVMERGEHILO },
5870 { 0, CODE_FOR_spe_evmergelo, "__builtin_spe_evmergelo", SPE_BUILTIN_EVMERGELO },
5871 { 0, CODE_FOR_spe_evmergelohi, "__builtin_spe_evmergelohi", SPE_BUILTIN_EVMERGELOHI },
5872 { 0, CODE_FOR_spe_evmhegsmfaa, "__builtin_spe_evmhegsmfaa", SPE_BUILTIN_EVMHEGSMFAA },
5873 { 0, CODE_FOR_spe_evmhegsmfan, "__builtin_spe_evmhegsmfan", SPE_BUILTIN_EVMHEGSMFAN },
5874 { 0, CODE_FOR_spe_evmhegsmiaa, "__builtin_spe_evmhegsmiaa", SPE_BUILTIN_EVMHEGSMIAA },
5875 { 0, CODE_FOR_spe_evmhegsmian, "__builtin_spe_evmhegsmian", SPE_BUILTIN_EVMHEGSMIAN },
5876 { 0, CODE_FOR_spe_evmhegumiaa, "__builtin_spe_evmhegumiaa", SPE_BUILTIN_EVMHEGUMIAA },
5877 { 0, CODE_FOR_spe_evmhegumian, "__builtin_spe_evmhegumian", SPE_BUILTIN_EVMHEGUMIAN },
5878 { 0, CODE_FOR_spe_evmhesmf, "__builtin_spe_evmhesmf", SPE_BUILTIN_EVMHESMF },
5879 { 0, CODE_FOR_spe_evmhesmfa, "__builtin_spe_evmhesmfa", SPE_BUILTIN_EVMHESMFA },
5880 { 0, CODE_FOR_spe_evmhesmfaaw, "__builtin_spe_evmhesmfaaw", SPE_BUILTIN_EVMHESMFAAW },
5881 { 0, CODE_FOR_spe_evmhesmfanw, "__builtin_spe_evmhesmfanw", SPE_BUILTIN_EVMHESMFANW },
5882 { 0, CODE_FOR_spe_evmhesmi, "__builtin_spe_evmhesmi", SPE_BUILTIN_EVMHESMI },
5883 { 0, CODE_FOR_spe_evmhesmia, "__builtin_spe_evmhesmia", SPE_BUILTIN_EVMHESMIA },
5884 { 0, CODE_FOR_spe_evmhesmiaaw, "__builtin_spe_evmhesmiaaw", SPE_BUILTIN_EVMHESMIAAW },
5885 { 0, CODE_FOR_spe_evmhesmianw, "__builtin_spe_evmhesmianw", SPE_BUILTIN_EVMHESMIANW },
5886 { 0, CODE_FOR_spe_evmhessf, "__builtin_spe_evmhessf", SPE_BUILTIN_EVMHESSF },
5887 { 0, CODE_FOR_spe_evmhessfa, "__builtin_spe_evmhessfa", SPE_BUILTIN_EVMHESSFA },
5888 { 0, CODE_FOR_spe_evmhessfaaw, "__builtin_spe_evmhessfaaw", SPE_BUILTIN_EVMHESSFAAW },
5889 { 0, CODE_FOR_spe_evmhessfanw, "__builtin_spe_evmhessfanw", SPE_BUILTIN_EVMHESSFANW },
5890 { 0, CODE_FOR_spe_evmhessiaaw, "__builtin_spe_evmhessiaaw", SPE_BUILTIN_EVMHESSIAAW },
5891 { 0, CODE_FOR_spe_evmhessianw, "__builtin_spe_evmhessianw", SPE_BUILTIN_EVMHESSIANW },
5892 { 0, CODE_FOR_spe_evmheumi, "__builtin_spe_evmheumi", SPE_BUILTIN_EVMHEUMI },
5893 { 0, CODE_FOR_spe_evmheumia, "__builtin_spe_evmheumia", SPE_BUILTIN_EVMHEUMIA },
5894 { 0, CODE_FOR_spe_evmheumiaaw, "__builtin_spe_evmheumiaaw", SPE_BUILTIN_EVMHEUMIAAW },
5895 { 0, CODE_FOR_spe_evmheumianw, "__builtin_spe_evmheumianw", SPE_BUILTIN_EVMHEUMIANW },
5896 { 0, CODE_FOR_spe_evmheusiaaw, "__builtin_spe_evmheusiaaw", SPE_BUILTIN_EVMHEUSIAAW },
5897 { 0, CODE_FOR_spe_evmheusianw, "__builtin_spe_evmheusianw", SPE_BUILTIN_EVMHEUSIANW },
5898 { 0, CODE_FOR_spe_evmhogsmfaa, "__builtin_spe_evmhogsmfaa", SPE_BUILTIN_EVMHOGSMFAA },
5899 { 0, CODE_FOR_spe_evmhogsmfan, "__builtin_spe_evmhogsmfan", SPE_BUILTIN_EVMHOGSMFAN },
5900 { 0, CODE_FOR_spe_evmhogsmiaa, "__builtin_spe_evmhogsmiaa", SPE_BUILTIN_EVMHOGSMIAA },
5901 { 0, CODE_FOR_spe_evmhogsmian, "__builtin_spe_evmhogsmian", SPE_BUILTIN_EVMHOGSMIAN },
5902 { 0, CODE_FOR_spe_evmhogumiaa, "__builtin_spe_evmhogumiaa", SPE_BUILTIN_EVMHOGUMIAA },
5903 { 0, CODE_FOR_spe_evmhogumian, "__builtin_spe_evmhogumian", SPE_BUILTIN_EVMHOGUMIAN },
5904 { 0, CODE_FOR_spe_evmhosmf, "__builtin_spe_evmhosmf", SPE_BUILTIN_EVMHOSMF },
5905 { 0, CODE_FOR_spe_evmhosmfa, "__builtin_spe_evmhosmfa", SPE_BUILTIN_EVMHOSMFA },
5906 { 0, CODE_FOR_spe_evmhosmfaaw, "__builtin_spe_evmhosmfaaw", SPE_BUILTIN_EVMHOSMFAAW },
5907 { 0, CODE_FOR_spe_evmhosmfanw, "__builtin_spe_evmhosmfanw", SPE_BUILTIN_EVMHOSMFANW },
5908 { 0, CODE_FOR_spe_evmhosmi, "__builtin_spe_evmhosmi", SPE_BUILTIN_EVMHOSMI },
5909 { 0, CODE_FOR_spe_evmhosmia, "__builtin_spe_evmhosmia", SPE_BUILTIN_EVMHOSMIA },
5910 { 0, CODE_FOR_spe_evmhosmiaaw, "__builtin_spe_evmhosmiaaw", SPE_BUILTIN_EVMHOSMIAAW },
5911 { 0, CODE_FOR_spe_evmhosmianw, "__builtin_spe_evmhosmianw", SPE_BUILTIN_EVMHOSMIANW },
5912 { 0, CODE_FOR_spe_evmhossf, "__builtin_spe_evmhossf", SPE_BUILTIN_EVMHOSSF },
5913 { 0, CODE_FOR_spe_evmhossfa, "__builtin_spe_evmhossfa", SPE_BUILTIN_EVMHOSSFA },
5914 { 0, CODE_FOR_spe_evmhossfaaw, "__builtin_spe_evmhossfaaw", SPE_BUILTIN_EVMHOSSFAAW },
5915 { 0, CODE_FOR_spe_evmhossfanw, "__builtin_spe_evmhossfanw", SPE_BUILTIN_EVMHOSSFANW },
5916 { 0, CODE_FOR_spe_evmhossiaaw, "__builtin_spe_evmhossiaaw", SPE_BUILTIN_EVMHOSSIAAW },
5917 { 0, CODE_FOR_spe_evmhossianw, "__builtin_spe_evmhossianw", SPE_BUILTIN_EVMHOSSIANW },
5918 { 0, CODE_FOR_spe_evmhoumi, "__builtin_spe_evmhoumi", SPE_BUILTIN_EVMHOUMI },
5919 { 0, CODE_FOR_spe_evmhoumia, "__builtin_spe_evmhoumia", SPE_BUILTIN_EVMHOUMIA },
5920 { 0, CODE_FOR_spe_evmhoumiaaw, "__builtin_spe_evmhoumiaaw", SPE_BUILTIN_EVMHOUMIAAW },
5921 { 0, CODE_FOR_spe_evmhoumianw, "__builtin_spe_evmhoumianw", SPE_BUILTIN_EVMHOUMIANW },
5922 { 0, CODE_FOR_spe_evmhousiaaw, "__builtin_spe_evmhousiaaw", SPE_BUILTIN_EVMHOUSIAAW },
5923 { 0, CODE_FOR_spe_evmhousianw, "__builtin_spe_evmhousianw", SPE_BUILTIN_EVMHOUSIANW },
5924 { 0, CODE_FOR_spe_evmwhsmf, "__builtin_spe_evmwhsmf", SPE_BUILTIN_EVMWHSMF },
5925 { 0, CODE_FOR_spe_evmwhsmfa, "__builtin_spe_evmwhsmfa", SPE_BUILTIN_EVMWHSMFA },
5926 { 0, CODE_FOR_spe_evmwhsmi, "__builtin_spe_evmwhsmi", SPE_BUILTIN_EVMWHSMI },
5927 { 0, CODE_FOR_spe_evmwhsmia, "__builtin_spe_evmwhsmia", SPE_BUILTIN_EVMWHSMIA },
5928 { 0, CODE_FOR_spe_evmwhssf, "__builtin_spe_evmwhssf", SPE_BUILTIN_EVMWHSSF },
5929 { 0, CODE_FOR_spe_evmwhssfa, "__builtin_spe_evmwhssfa", SPE_BUILTIN_EVMWHSSFA },
5930 { 0, CODE_FOR_spe_evmwhumi, "__builtin_spe_evmwhumi", SPE_BUILTIN_EVMWHUMI },
5931 { 0, CODE_FOR_spe_evmwhumia, "__builtin_spe_evmwhumia", SPE_BUILTIN_EVMWHUMIA },
a3170dc6
AH		 5932 { 0, CODE_FOR_spe_evmwlsmiaaw, "__builtin_spe_evmwlsmiaaw", SPE_BUILTIN_EVMWLSMIAAW },
5933 { 0, CODE_FOR_spe_evmwlsmianw, "__builtin_spe_evmwlsmianw", SPE_BUILTIN_EVMWLSMIANW },
a3170dc6
AH		 5934 { 0, CODE_FOR_spe_evmwlssiaaw, "__builtin_spe_evmwlssiaaw", SPE_BUILTIN_EVMWLSSIAAW },
5935 { 0, CODE_FOR_spe_evmwlssianw, "__builtin_spe_evmwlssianw", SPE_BUILTIN_EVMWLSSIANW },
5936 { 0, CODE_FOR_spe_evmwlumi, "__builtin_spe_evmwlumi", SPE_BUILTIN_EVMWLUMI },
5937 { 0, CODE_FOR_spe_evmwlumia, "__builtin_spe_evmwlumia", SPE_BUILTIN_EVMWLUMIA },
5938 { 0, CODE_FOR_spe_evmwlumiaaw, "__builtin_spe_evmwlumiaaw", SPE_BUILTIN_EVMWLUMIAAW },
5939 { 0, CODE_FOR_spe_evmwlumianw, "__builtin_spe_evmwlumianw", SPE_BUILTIN_EVMWLUMIANW },
5940 { 0, CODE_FOR_spe_evmwlusiaaw, "__builtin_spe_evmwlusiaaw", SPE_BUILTIN_EVMWLUSIAAW },
5941 { 0, CODE_FOR_spe_evmwlusianw, "__builtin_spe_evmwlusianw", SPE_BUILTIN_EVMWLUSIANW },
5942 { 0, CODE_FOR_spe_evmwsmf, "__builtin_spe_evmwsmf", SPE_BUILTIN_EVMWSMF },
5943 { 0, CODE_FOR_spe_evmwsmfa, "__builtin_spe_evmwsmfa", SPE_BUILTIN_EVMWSMFA },
5944 { 0, CODE_FOR_spe_evmwsmfaa, "__builtin_spe_evmwsmfaa", SPE_BUILTIN_EVMWSMFAA },
5945 { 0, CODE_FOR_spe_evmwsmfan, "__builtin_spe_evmwsmfan", SPE_BUILTIN_EVMWSMFAN },
5946 { 0, CODE_FOR_spe_evmwsmi, "__builtin_spe_evmwsmi", SPE_BUILTIN_EVMWSMI },
5947 { 0, CODE_FOR_spe_evmwsmia, "__builtin_spe_evmwsmia", SPE_BUILTIN_EVMWSMIA },
5948 { 0, CODE_FOR_spe_evmwsmiaa, "__builtin_spe_evmwsmiaa", SPE_BUILTIN_EVMWSMIAA },
5949 { 0, CODE_FOR_spe_evmwsmian, "__builtin_spe_evmwsmian", SPE_BUILTIN_EVMWSMIAN },
5950 { 0, CODE_FOR_spe_evmwssf, "__builtin_spe_evmwssf", SPE_BUILTIN_EVMWSSF },
5951 { 0, CODE_FOR_spe_evmwssfa, "__builtin_spe_evmwssfa", SPE_BUILTIN_EVMWSSFA },
5952 { 0, CODE_FOR_spe_evmwssfaa, "__builtin_spe_evmwssfaa", SPE_BUILTIN_EVMWSSFAA },
5953 { 0, CODE_FOR_spe_evmwssfan, "__builtin_spe_evmwssfan", SPE_BUILTIN_EVMWSSFAN },
5954 { 0, CODE_FOR_spe_evmwumi, "__builtin_spe_evmwumi", SPE_BUILTIN_EVMWUMI },
5955 { 0, CODE_FOR_spe_evmwumia, "__builtin_spe_evmwumia", SPE_BUILTIN_EVMWUMIA },
5956 { 0, CODE_FOR_spe_evmwumiaa, "__builtin_spe_evmwumiaa", SPE_BUILTIN_EVMWUMIAA },
5957 { 0, CODE_FOR_spe_evmwumian, "__builtin_spe_evmwumian", SPE_BUILTIN_EVMWUMIAN },
5958 { 0, CODE_FOR_spe_evnand, "__builtin_spe_evnand", SPE_BUILTIN_EVNAND },
5959 { 0, CODE_FOR_spe_evnor, "__builtin_spe_evnor", SPE_BUILTIN_EVNOR },
5960 { 0, CODE_FOR_spe_evor, "__builtin_spe_evor", SPE_BUILTIN_EVOR },
5961 { 0, CODE_FOR_spe_evorc, "__builtin_spe_evorc", SPE_BUILTIN_EVORC },
5962 { 0, CODE_FOR_spe_evrlw, "__builtin_spe_evrlw", SPE_BUILTIN_EVRLW },
5963 { 0, CODE_FOR_spe_evslw, "__builtin_spe_evslw", SPE_BUILTIN_EVSLW },
5964 { 0, CODE_FOR_spe_evsrws, "__builtin_spe_evsrws", SPE_BUILTIN_EVSRWS },
5965 { 0, CODE_FOR_spe_evsrwu, "__builtin_spe_evsrwu", SPE_BUILTIN_EVSRWU },
5966 { 0, CODE_FOR_spe_evsubfw, "__builtin_spe_evsubfw", SPE_BUILTIN_EVSUBFW },
5967
5968 /* SPE binary operations expecting a 5-bit unsigned literal. */
5969 { 0, CODE_FOR_spe_evaddiw, "__builtin_spe_evaddiw", SPE_BUILTIN_EVADDIW },
5970
5971 { 0, CODE_FOR_spe_evrlwi, "__builtin_spe_evrlwi", SPE_BUILTIN_EVRLWI },
5972 { 0, CODE_FOR_spe_evslwi, "__builtin_spe_evslwi", SPE_BUILTIN_EVSLWI },
5973 { 0, CODE_FOR_spe_evsrwis, "__builtin_spe_evsrwis", SPE_BUILTIN_EVSRWIS },
5974 { 0, CODE_FOR_spe_evsrwiu, "__builtin_spe_evsrwiu", SPE_BUILTIN_EVSRWIU },
5975 { 0, CODE_FOR_spe_evsubifw, "__builtin_spe_evsubifw", SPE_BUILTIN_EVSUBIFW },
5976 { 0, CODE_FOR_spe_evmwhssfaa, "__builtin_spe_evmwhssfaa", SPE_BUILTIN_EVMWHSSFAA },
5977 { 0, CODE_FOR_spe_evmwhssmaa, "__builtin_spe_evmwhssmaa", SPE_BUILTIN_EVMWHSSMAA },
5978 { 0, CODE_FOR_spe_evmwhsmfaa, "__builtin_spe_evmwhsmfaa", SPE_BUILTIN_EVMWHSMFAA },
5979 { 0, CODE_FOR_spe_evmwhsmiaa, "__builtin_spe_evmwhsmiaa", SPE_BUILTIN_EVMWHSMIAA },
5980 { 0, CODE_FOR_spe_evmwhusiaa, "__builtin_spe_evmwhusiaa", SPE_BUILTIN_EVMWHUSIAA },
5981 { 0, CODE_FOR_spe_evmwhumiaa, "__builtin_spe_evmwhumiaa", SPE_BUILTIN_EVMWHUMIAA },
5982 { 0, CODE_FOR_spe_evmwhssfan, "__builtin_spe_evmwhssfan", SPE_BUILTIN_EVMWHSSFAN },
5983 { 0, CODE_FOR_spe_evmwhssian, "__builtin_spe_evmwhssian", SPE_BUILTIN_EVMWHSSIAN },
5984 { 0, CODE_FOR_spe_evmwhsmfan, "__builtin_spe_evmwhsmfan", SPE_BUILTIN_EVMWHSMFAN },
5985 { 0, CODE_FOR_spe_evmwhsmian, "__builtin_spe_evmwhsmian", SPE_BUILTIN_EVMWHSMIAN },
5986 { 0, CODE_FOR_spe_evmwhusian, "__builtin_spe_evmwhusian", SPE_BUILTIN_EVMWHUSIAN },
5987 { 0, CODE_FOR_spe_evmwhumian, "__builtin_spe_evmwhumian", SPE_BUILTIN_EVMWHUMIAN },
5988 { 0, CODE_FOR_spe_evmwhgssfaa, "__builtin_spe_evmwhgssfaa", SPE_BUILTIN_EVMWHGSSFAA },
5989 { 0, CODE_FOR_spe_evmwhgsmfaa, "__builtin_spe_evmwhgsmfaa", SPE_BUILTIN_EVMWHGSMFAA },
5990 { 0, CODE_FOR_spe_evmwhgsmiaa, "__builtin_spe_evmwhgsmiaa", SPE_BUILTIN_EVMWHGSMIAA },
5991 { 0, CODE_FOR_spe_evmwhgumiaa, "__builtin_spe_evmwhgumiaa", SPE_BUILTIN_EVMWHGUMIAA },
5992 { 0, CODE_FOR_spe_evmwhgssfan, "__builtin_spe_evmwhgssfan", SPE_BUILTIN_EVMWHGSSFAN },
5993 { 0, CODE_FOR_spe_evmwhgsmfan, "__builtin_spe_evmwhgsmfan", SPE_BUILTIN_EVMWHGSMFAN },
5994 { 0, CODE_FOR_spe_evmwhgsmian, "__builtin_spe_evmwhgsmian", SPE_BUILTIN_EVMWHGSMIAN },
5995 { 0, CODE_FOR_spe_evmwhgumian, "__builtin_spe_evmwhgumian", SPE_BUILTIN_EVMWHGUMIAN },
5996 { 0, CODE_FOR_spe_brinc, "__builtin_spe_brinc", SPE_BUILTIN_BRINC },
5997
5998 /* Place-holder. Leave as last binary SPE builtin. */
58646b77 5999 { 0, CODE_FOR_xorv2si3, "__builtin_spe_evxor", SPE_BUILTIN_EVXOR }
ae4b4a02
AH		 6000};
6001
6002/* AltiVec predicates. */
6003
6004struct builtin_description_predicates
6005{
6006 const unsigned int mask;
6007 const enum insn_code icode;
6008 const char *opcode;
6009 const char *const name;
6010 const enum rs6000_builtins code;
6011};
6012
6013static const struct builtin_description_predicates bdesc_altivec_preds[] =
6014{
6015 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpbfp.", "__builtin_altivec_vcmpbfp_p", ALTIVEC_BUILTIN_VCMPBFP_P },
6016 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpeqfp.", "__builtin_altivec_vcmpeqfp_p", ALTIVEC_BUILTIN_VCMPEQFP_P },
6017 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpgefp.", "__builtin_altivec_vcmpgefp_p", ALTIVEC_BUILTIN_VCMPGEFP_P },
6018 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpgtfp.", "__builtin_altivec_vcmpgtfp_p", ALTIVEC_BUILTIN_VCMPGTFP_P },
6019 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpequw.", "__builtin_altivec_vcmpequw_p", ALTIVEC_BUILTIN_VCMPEQUW_P },
6020 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpgtsw.", "__builtin_altivec_vcmpgtsw_p", ALTIVEC_BUILTIN_VCMPGTSW_P },
6021 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpgtuw.", "__builtin_altivec_vcmpgtuw_p", ALTIVEC_BUILTIN_VCMPGTUW_P },
6022 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpgtuh.", "__builtin_altivec_vcmpgtuh_p", ALTIVEC_BUILTIN_VCMPGTUH_P },
6023 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpgtsh.", "__builtin_altivec_vcmpgtsh_p", ALTIVEC_BUILTIN_VCMPGTSH_P },
6024 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpequh.", "__builtin_altivec_vcmpequh_p", ALTIVEC_BUILTIN_VCMPEQUH_P },
6025 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpequb.", "__builtin_altivec_vcmpequb_p", ALTIVEC_BUILTIN_VCMPEQUB_P },
6026 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpgtsb.", "__builtin_altivec_vcmpgtsb_p", ALTIVEC_BUILTIN_VCMPGTSB_P },
58646b77
PB		 6027 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpgtub.", "__builtin_altivec_vcmpgtub_p", ALTIVEC_BUILTIN_VCMPGTUB_P },
6028
6029 { MASK_ALTIVEC, 0, NULL, "__builtin_vec_vcmpeq_p", ALTIVEC_BUILTIN_VCMPEQ_P },
6030 { MASK_ALTIVEC, 0, NULL, "__builtin_vec_vcmpgt_p", ALTIVEC_BUILTIN_VCMPGT_P },
6031 { MASK_ALTIVEC, 0, NULL, "__builtin_vec_vcmpge_p", ALTIVEC_BUILTIN_VCMPGE_P }
0ac081f6 6032};
24408032 6033
a3170dc6
AH		 6034/* SPE predicates. */
6035static struct builtin_description bdesc_spe_predicates[] =
6036{
6037 /* Place-holder. Leave as first. */
6038 { 0, CODE_FOR_spe_evcmpeq, "__builtin_spe_evcmpeq", SPE_BUILTIN_EVCMPEQ },
6039 { 0, CODE_FOR_spe_evcmpgts, "__builtin_spe_evcmpgts", SPE_BUILTIN_EVCMPGTS },
6040 { 0, CODE_FOR_spe_evcmpgtu, "__builtin_spe_evcmpgtu", SPE_BUILTIN_EVCMPGTU },
6041 { 0, CODE_FOR_spe_evcmplts, "__builtin_spe_evcmplts", SPE_BUILTIN_EVCMPLTS },
6042 { 0, CODE_FOR_spe_evcmpltu, "__builtin_spe_evcmpltu", SPE_BUILTIN_EVCMPLTU },
6043 { 0, CODE_FOR_spe_evfscmpeq, "__builtin_spe_evfscmpeq", SPE_BUILTIN_EVFSCMPEQ },
6044 { 0, CODE_FOR_spe_evfscmpgt, "__builtin_spe_evfscmpgt", SPE_BUILTIN_EVFSCMPGT },
6045 { 0, CODE_FOR_spe_evfscmplt, "__builtin_spe_evfscmplt", SPE_BUILTIN_EVFSCMPLT },
6046 { 0, CODE_FOR_spe_evfststeq, "__builtin_spe_evfststeq", SPE_BUILTIN_EVFSTSTEQ },
6047 { 0, CODE_FOR_spe_evfststgt, "__builtin_spe_evfststgt", SPE_BUILTIN_EVFSTSTGT },
6048 /* Place-holder. Leave as last. */
6049 { 0, CODE_FOR_spe_evfststlt, "__builtin_spe_evfststlt", SPE_BUILTIN_EVFSTSTLT },
6050};
6051
6052/* SPE evsel predicates. */
6053static struct builtin_description bdesc_spe_evsel[] =
6054{
6055 /* Place-holder. Leave as first. */
6056 { 0, CODE_FOR_spe_evcmpgts, "__builtin_spe_evsel_gts", SPE_BUILTIN_EVSEL_CMPGTS },
6057 { 0, CODE_FOR_spe_evcmpgtu, "__builtin_spe_evsel_gtu", SPE_BUILTIN_EVSEL_CMPGTU },
6058 { 0, CODE_FOR_spe_evcmplts, "__builtin_spe_evsel_lts", SPE_BUILTIN_EVSEL_CMPLTS },
6059 { 0, CODE_FOR_spe_evcmpltu, "__builtin_spe_evsel_ltu", SPE_BUILTIN_EVSEL_CMPLTU },
6060 { 0, CODE_FOR_spe_evcmpeq, "__builtin_spe_evsel_eq", SPE_BUILTIN_EVSEL_CMPEQ },
6061 { 0, CODE_FOR_spe_evfscmpgt, "__builtin_spe_evsel_fsgt", SPE_BUILTIN_EVSEL_FSCMPGT },
6062 { 0, CODE_FOR_spe_evfscmplt, "__builtin_spe_evsel_fslt", SPE_BUILTIN_EVSEL_FSCMPLT },
6063 { 0, CODE_FOR_spe_evfscmpeq, "__builtin_spe_evsel_fseq", SPE_BUILTIN_EVSEL_FSCMPEQ },
6064 { 0, CODE_FOR_spe_evfststgt, "__builtin_spe_evsel_fststgt", SPE_BUILTIN_EVSEL_FSTSTGT },
6065 { 0, CODE_FOR_spe_evfststlt, "__builtin_spe_evsel_fststlt", SPE_BUILTIN_EVSEL_FSTSTLT },
6066 /* Place-holder. Leave as last. */
6067 { 0, CODE_FOR_spe_evfststeq, "__builtin_spe_evsel_fststeq", SPE_BUILTIN_EVSEL_FSTSTEQ },
6068};
6069
b6d08ca1 6070/* ABS* operations. */
100c4561
AH		 6071
6072static const struct builtin_description bdesc_abs[] =
6073{
6074 { MASK_ALTIVEC, CODE_FOR_absv4si2, "__builtin_altivec_abs_v4si", ALTIVEC_BUILTIN_ABS_V4SI },
6075 { MASK_ALTIVEC, CODE_FOR_absv8hi2, "__builtin_altivec_abs_v8hi", ALTIVEC_BUILTIN_ABS_V8HI },
6076 { MASK_ALTIVEC, CODE_FOR_absv4sf2, "__builtin_altivec_abs_v4sf", ALTIVEC_BUILTIN_ABS_V4SF },
6077 { MASK_ALTIVEC, CODE_FOR_absv16qi2, "__builtin_altivec_abs_v16qi", ALTIVEC_BUILTIN_ABS_V16QI },
6078 { MASK_ALTIVEC, CODE_FOR_altivec_abss_v4si, "__builtin_altivec_abss_v4si", ALTIVEC_BUILTIN_ABSS_V4SI },
6079 { MASK_ALTIVEC, CODE_FOR_altivec_abss_v8hi, "__builtin_altivec_abss_v8hi", ALTIVEC_BUILTIN_ABSS_V8HI },
6080 { MASK_ALTIVEC, CODE_FOR_altivec_abss_v16qi, "__builtin_altivec_abss_v16qi", ALTIVEC_BUILTIN_ABSS_V16QI }
6081};
6082
617e0e1d
DB		 6083/* Simple unary operations: VECb = foo (unsigned literal) or VECb =
6084 foo (VECa). */
24408032 6085
a3170dc6 6086static struct builtin_description bdesc_1arg[] =
2212663f 6087{
617e0e1d
DB		 6088 { MASK_ALTIVEC, CODE_FOR_altivec_vexptefp, "__builtin_altivec_vexptefp", ALTIVEC_BUILTIN_VEXPTEFP },
6089 { MASK_ALTIVEC, CODE_FOR_altivec_vlogefp, "__builtin_altivec_vlogefp", ALTIVEC_BUILTIN_VLOGEFP },
6090 { MASK_ALTIVEC, CODE_FOR_altivec_vrefp, "__builtin_altivec_vrefp", ALTIVEC_BUILTIN_VREFP },
6091 { MASK_ALTIVEC, CODE_FOR_altivec_vrfim, "__builtin_altivec_vrfim", ALTIVEC_BUILTIN_VRFIM },
6092 { MASK_ALTIVEC, CODE_FOR_altivec_vrfin, "__builtin_altivec_vrfin", ALTIVEC_BUILTIN_VRFIN },
6093 { MASK_ALTIVEC, CODE_FOR_altivec_vrfip, "__builtin_altivec_vrfip", ALTIVEC_BUILTIN_VRFIP },
6094 { MASK_ALTIVEC, CODE_FOR_ftruncv4sf2, "__builtin_altivec_vrfiz", ALTIVEC_BUILTIN_VRFIZ },
6095 { MASK_ALTIVEC, CODE_FOR_altivec_vrsqrtefp, "__builtin_altivec_vrsqrtefp", ALTIVEC_BUILTIN_VRSQRTEFP },
2212663f
DB		 6096 { MASK_ALTIVEC, CODE_FOR_altivec_vspltisb, "__builtin_altivec_vspltisb", ALTIVEC_BUILTIN_VSPLTISB },
6097 { MASK_ALTIVEC, CODE_FOR_altivec_vspltish, "__builtin_altivec_vspltish", ALTIVEC_BUILTIN_VSPLTISH },
6098 { MASK_ALTIVEC, CODE_FOR_altivec_vspltisw, "__builtin_altivec_vspltisw", ALTIVEC_BUILTIN_VSPLTISW },
20e26713
AH		 6099 { MASK_ALTIVEC, CODE_FOR_altivec_vupkhsb, "__builtin_altivec_vupkhsb", ALTIVEC_BUILTIN_VUPKHSB },
6100 { MASK_ALTIVEC, CODE_FOR_altivec_vupkhpx, "__builtin_altivec_vupkhpx", ALTIVEC_BUILTIN_VUPKHPX },
6101 { MASK_ALTIVEC, CODE_FOR_altivec_vupkhsh, "__builtin_altivec_vupkhsh", ALTIVEC_BUILTIN_VUPKHSH },
6102 { MASK_ALTIVEC, CODE_FOR_altivec_vupklsb, "__builtin_altivec_vupklsb", ALTIVEC_BUILTIN_VUPKLSB },
6103 { MASK_ALTIVEC, CODE_FOR_altivec_vupklpx, "__builtin_altivec_vupklpx", ALTIVEC_BUILTIN_VUPKLPX },
6104 { MASK_ALTIVEC, CODE_FOR_altivec_vupklsh, "__builtin_altivec_vupklsh", ALTIVEC_BUILTIN_VUPKLSH },
a3170dc6 6105
58646b77
PB		 6106 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_abs", ALTIVEC_BUILTIN_VEC_ABS },
6107 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_abss", ALTIVEC_BUILTIN_VEC_ABSS },
6108 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_ceil", ALTIVEC_BUILTIN_VEC_CEIL },
6109 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_expte", ALTIVEC_BUILTIN_VEC_EXPTE },
6110 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_floor", ALTIVEC_BUILTIN_VEC_FLOOR },
6111 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_loge", ALTIVEC_BUILTIN_VEC_LOGE },
6112 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mtvscr", ALTIVEC_BUILTIN_VEC_MTVSCR },
6113 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_re", ALTIVEC_BUILTIN_VEC_RE },
6114 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_round", ALTIVEC_BUILTIN_VEC_ROUND },
6115 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_rsqrte", ALTIVEC_BUILTIN_VEC_RSQRTE },
6116 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_trunc", ALTIVEC_BUILTIN_VEC_TRUNC },
6117 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_unpackh", ALTIVEC_BUILTIN_VEC_UNPACKH },
6118 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupkhsh", ALTIVEC_BUILTIN_VEC_VUPKHSH },
6119 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupkhpx", ALTIVEC_BUILTIN_VEC_VUPKHPX },
6120 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupkhsb", ALTIVEC_BUILTIN_VEC_VUPKHSB },
6121 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_unpackl", ALTIVEC_BUILTIN_VEC_UNPACKL },
6122 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupklpx", ALTIVEC_BUILTIN_VEC_VUPKLPX },
6123 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupklsh", ALTIVEC_BUILTIN_VEC_VUPKLSH },
6124 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupklsb", ALTIVEC_BUILTIN_VEC_VUPKLSB },
6125
a3170dc6
AH		 6126 /* The SPE unary builtins must start with SPE_BUILTIN_EVABS and
6127 end with SPE_BUILTIN_EVSUBFUSIAAW. */
6128 { 0, CODE_FOR_spe_evabs, "__builtin_spe_evabs", SPE_BUILTIN_EVABS },
6129 { 0, CODE_FOR_spe_evaddsmiaaw, "__builtin_spe_evaddsmiaaw", SPE_BUILTIN_EVADDSMIAAW },
6130 { 0, CODE_FOR_spe_evaddssiaaw, "__builtin_spe_evaddssiaaw", SPE_BUILTIN_EVADDSSIAAW },
6131 { 0, CODE_FOR_spe_evaddumiaaw, "__builtin_spe_evaddumiaaw", SPE_BUILTIN_EVADDUMIAAW },
6132 { 0, CODE_FOR_spe_evaddusiaaw, "__builtin_spe_evaddusiaaw", SPE_BUILTIN_EVADDUSIAAW },
6133 { 0, CODE_FOR_spe_evcntlsw, "__builtin_spe_evcntlsw", SPE_BUILTIN_EVCNTLSW },
6134 { 0, CODE_FOR_spe_evcntlzw, "__builtin_spe_evcntlzw", SPE_BUILTIN_EVCNTLZW },
6135 { 0, CODE_FOR_spe_evextsb, "__builtin_spe_evextsb", SPE_BUILTIN_EVEXTSB },
6136 { 0, CODE_FOR_spe_evextsh, "__builtin_spe_evextsh", SPE_BUILTIN_EVEXTSH },
6137 { 0, CODE_FOR_spe_evfsabs, "__builtin_spe_evfsabs", SPE_BUILTIN_EVFSABS },
6138 { 0, CODE_FOR_spe_evfscfsf, "__builtin_spe_evfscfsf", SPE_BUILTIN_EVFSCFSF },
6139 { 0, CODE_FOR_spe_evfscfsi, "__builtin_spe_evfscfsi", SPE_BUILTIN_EVFSCFSI },
6140 { 0, CODE_FOR_spe_evfscfuf, "__builtin_spe_evfscfuf", SPE_BUILTIN_EVFSCFUF },
6141 { 0, CODE_FOR_spe_evfscfui, "__builtin_spe_evfscfui", SPE_BUILTIN_EVFSCFUI },
6142 { 0, CODE_FOR_spe_evfsctsf, "__builtin_spe_evfsctsf", SPE_BUILTIN_EVFSCTSF },
6143 { 0, CODE_FOR_spe_evfsctsi, "__builtin_spe_evfsctsi", SPE_BUILTIN_EVFSCTSI },
6144 { 0, CODE_FOR_spe_evfsctsiz, "__builtin_spe_evfsctsiz", SPE_BUILTIN_EVFSCTSIZ },
6145 { 0, CODE_FOR_spe_evfsctuf, "__builtin_spe_evfsctuf", SPE_BUILTIN_EVFSCTUF },
6146 { 0, CODE_FOR_spe_evfsctui, "__builtin_spe_evfsctui", SPE_BUILTIN_EVFSCTUI },
6147 { 0, CODE_FOR_spe_evfsctuiz, "__builtin_spe_evfsctuiz", SPE_BUILTIN_EVFSCTUIZ },
6148 { 0, CODE_FOR_spe_evfsnabs, "__builtin_spe_evfsnabs", SPE_BUILTIN_EVFSNABS },
6149 { 0, CODE_FOR_spe_evfsneg, "__builtin_spe_evfsneg", SPE_BUILTIN_EVFSNEG },
6150 { 0, CODE_FOR_spe_evmra, "__builtin_spe_evmra", SPE_BUILTIN_EVMRA },
6a599451 6151 { 0, CODE_FOR_negv2si2, "__builtin_spe_evneg", SPE_BUILTIN_EVNEG },
a3170dc6
AH		 6152 { 0, CODE_FOR_spe_evrndw, "__builtin_spe_evrndw", SPE_BUILTIN_EVRNDW },
6153 { 0, CODE_FOR_spe_evsubfsmiaaw, "__builtin_spe_evsubfsmiaaw", SPE_BUILTIN_EVSUBFSMIAAW },
6154 { 0, CODE_FOR_spe_evsubfssiaaw, "__builtin_spe_evsubfssiaaw", SPE_BUILTIN_EVSUBFSSIAAW },
6155 { 0, CODE_FOR_spe_evsubfumiaaw, "__builtin_spe_evsubfumiaaw", SPE_BUILTIN_EVSUBFUMIAAW },
a3170dc6
AH		 6156
6157 /* Place-holder. Leave as last unary SPE builtin. */
58646b77 6158 { 0, CODE_FOR_spe_evsubfusiaaw, "__builtin_spe_evsubfusiaaw", SPE_BUILTIN_EVSUBFUSIAAW }
2212663f
DB		 6159};
6160
6161static rtx
a2369ed3 6162rs6000_expand_unop_builtin (enum insn_code icode, tree arglist, rtx target)
2212663f
DB		 6163{
6164 rtx pat;
6165 tree arg0 = TREE_VALUE (arglist);
6166 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6167 enum machine_mode tmode = insn_data[icode].operand[0].mode;
6168 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
6169
0559cc77
DE		 6170 if (icode == CODE_FOR_nothing)
6171 /* Builtin not supported on this processor. */
6172 return 0;
6173
20e26713
AH		 6174 /* If we got invalid arguments bail out before generating bad rtl. */
6175 if (arg0 == error_mark_node)
9a171fcd 6176 return const0_rtx;
20e26713 6177
0559cc77
DE		 6178 if (icode == CODE_FOR_altivec_vspltisb
6179 || icode == CODE_FOR_altivec_vspltish
6180 || icode == CODE_FOR_altivec_vspltisw
6181 || icode == CODE_FOR_spe_evsplatfi
6182 || icode == CODE_FOR_spe_evsplati)
b44140e7
AH		 6183 {
6184 /* Only allow 5-bit *signed* literals. */
b44140e7
AH		 6185 if (GET_CODE (op0) != CONST_INT
6186 || INTVAL (op0) > 0x1f
6187 || INTVAL (op0) < -0x1f)
6188 {
6189 error ("argument 1 must be a 5-bit signed literal");
9a171fcd 6190 return const0_rtx;
b44140e7 6191 }
b44140e7
AH		 6192 }
6193
c62f2db5 6194 if (target == 0
2212663f
DB		 6195 || GET_MODE (target) != tmode
6196 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6197 target = gen_reg_rtx (tmode);
6198
6199 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
6200 op0 = copy_to_mode_reg (mode0, op0);
6201
6202 pat = GEN_FCN (icode) (target, op0);
6203 if (! pat)
6204 return 0;
6205 emit_insn (pat);
0ac081f6 6206
2212663f
DB		 6207 return target;
6208}
ae4b4a02 6209
100c4561 6210static rtx
a2369ed3 6211altivec_expand_abs_builtin (enum insn_code icode, tree arglist, rtx target)
100c4561
AH		 6212{
6213 rtx pat, scratch1, scratch2;
6214 tree arg0 = TREE_VALUE (arglist);
6215 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6216 enum machine_mode tmode = insn_data[icode].operand[0].mode;
6217 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
6218
6219 /* If we have invalid arguments, bail out before generating bad rtl. */
6220 if (arg0 == error_mark_node)
9a171fcd 6221 return const0_rtx;
100c4561
AH		 6222
6223 if (target == 0
6224 || GET_MODE (target) != tmode
6225 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6226 target = gen_reg_rtx (tmode);
6227
6228 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
6229 op0 = copy_to_mode_reg (mode0, op0);
6230
6231 scratch1 = gen_reg_rtx (mode0);
6232 scratch2 = gen_reg_rtx (mode0);
6233
6234 pat = GEN_FCN (icode) (target, op0, scratch1, scratch2);
6235 if (! pat)
6236 return 0;
6237 emit_insn (pat);
6238
6239 return target;
6240}
6241
0ac081f6 6242static rtx
a2369ed3 6243rs6000_expand_binop_builtin (enum insn_code icode, tree arglist, rtx target)
0ac081f6
AH		 6244{
6245 rtx pat;
6246 tree arg0 = TREE_VALUE (arglist);
6247 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6248 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6249 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6250 enum machine_mode tmode = insn_data[icode].operand[0].mode;
6251 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
6252 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
6253
0559cc77
DE		 6254 if (icode == CODE_FOR_nothing)
6255 /* Builtin not supported on this processor. */
6256 return 0;
6257
20e26713
AH		 6258 /* If we got invalid arguments bail out before generating bad rtl. */
6259 if (arg0 == error_mark_node || arg1 == error_mark_node)
9a171fcd 6260 return const0_rtx;
20e26713 6261
0559cc77
DE		 6262 if (icode == CODE_FOR_altivec_vcfux
6263 || icode == CODE_FOR_altivec_vcfsx
6264 || icode == CODE_FOR_altivec_vctsxs
6265 || icode == CODE_FOR_altivec_vctuxs
6266 || icode == CODE_FOR_altivec_vspltb
6267 || icode == CODE_FOR_altivec_vsplth
6268 || icode == CODE_FOR_altivec_vspltw
6269 || icode == CODE_FOR_spe_evaddiw
6270 || icode == CODE_FOR_spe_evldd
6271 || icode == CODE_FOR_spe_evldh
6272 || icode == CODE_FOR_spe_evldw
6273 || icode == CODE_FOR_spe_evlhhesplat
6274 || icode == CODE_FOR_spe_evlhhossplat
6275 || icode == CODE_FOR_spe_evlhhousplat
6276 || icode == CODE_FOR_spe_evlwhe
6277 || icode == CODE_FOR_spe_evlwhos
6278 || icode == CODE_FOR_spe_evlwhou
6279 || icode == CODE_FOR_spe_evlwhsplat
6280 || icode == CODE_FOR_spe_evlwwsplat
6281 || icode == CODE_FOR_spe_evrlwi
6282 || icode == CODE_FOR_spe_evslwi
6283 || icode == CODE_FOR_spe_evsrwis
f5119d10 6284 || icode == CODE_FOR_spe_evsubifw
0559cc77 6285 || icode == CODE_FOR_spe_evsrwiu)
b44140e7
AH		 6286 {
6287 /* Only allow 5-bit unsigned literals. */
8bb418a3 6288 STRIP_NOPS (arg1);
b44140e7
AH		 6289 if (TREE_CODE (arg1) != INTEGER_CST
6290 || TREE_INT_CST_LOW (arg1) & ~0x1f)
6291 {
6292 error ("argument 2 must be a 5-bit unsigned literal");
9a171fcd 6293 return const0_rtx;
b44140e7 6294 }
b44140e7
AH		 6295 }
6296
c62f2db5 6297 if (target == 0
0ac081f6
AH		 6298 || GET_MODE (target) != tmode
6299 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6300 target = gen_reg_rtx (tmode);
6301
6302 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
6303 op0 = copy_to_mode_reg (mode0, op0);
6304 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
6305 op1 = copy_to_mode_reg (mode1, op1);
6306
6307 pat = GEN_FCN (icode) (target, op0, op1);
6308 if (! pat)
6309 return 0;
6310 emit_insn (pat);
6311
6312 return target;
6313}
6525c0e7 6314
ae4b4a02 6315static rtx
f676971a 6316altivec_expand_predicate_builtin (enum insn_code icode, const char *opcode,
a2369ed3 6317 tree arglist, rtx target)
ae4b4a02
AH		 6318{
6319 rtx pat, scratch;
6320 tree cr6_form = TREE_VALUE (arglist);
6321 tree arg0 = TREE_VALUE (TREE_CHAIN (arglist));
6322 tree arg1 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
6323 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6324 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6325 enum machine_mode tmode = SImode;
6326 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
6327 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
6328 int cr6_form_int;
6329
6330 if (TREE_CODE (cr6_form) != INTEGER_CST)
6331 {
6332 error ("argument 1 of __builtin_altivec_predicate must be a constant");
9a171fcd 6333 return const0_rtx;
ae4b4a02
AH		 6334 }
6335 else
6336 cr6_form_int = TREE_INT_CST_LOW (cr6_form);
6337
37409796 6338 gcc_assert (mode0 == mode1);
ae4b4a02
AH		 6339
6340 /* If we have invalid arguments, bail out before generating bad rtl. */
6341 if (arg0 == error_mark_node || arg1 == error_mark_node)
9a171fcd 6342 return const0_rtx;
ae4b4a02
AH		 6343
6344 if (target == 0
6345 || GET_MODE (target) != tmode
6346 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6347 target = gen_reg_rtx (tmode);
6348
6349 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
6350 op0 = copy_to_mode_reg (mode0, op0);
6351 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
6352 op1 = copy_to_mode_reg (mode1, op1);
6353
6354 scratch = gen_reg_rtx (mode0);
6355
6356 pat = GEN_FCN (icode) (scratch, op0, op1,
f1c25d3b 6357 gen_rtx_SYMBOL_REF (Pmode, opcode));
ae4b4a02
AH		 6358 if (! pat)
6359 return 0;
6360 emit_insn (pat);
6361
6362 /* The vec_any* and vec_all* predicates use the same opcodes for two
6363 different operations, but the bits in CR6 will be different
6364 depending on what information we want. So we have to play tricks
6365 with CR6 to get the right bits out.
6366
6367 If you think this is disgusting, look at the specs for the
6368 AltiVec predicates. */
6369
c4ad648e
AM		 6370 switch (cr6_form_int)
6371 {
6372 case 0:
6373 emit_insn (gen_cr6_test_for_zero (target));
6374 break;
6375 case 1:
6376 emit_insn (gen_cr6_test_for_zero_reverse (target));
6377 break;
6378 case 2:
6379 emit_insn (gen_cr6_test_for_lt (target));
6380 break;
6381 case 3:
6382 emit_insn (gen_cr6_test_for_lt_reverse (target));
6383 break;
6384 default:
6385 error ("argument 1 of __builtin_altivec_predicate is out of range");
6386 break;
6387 }
ae4b4a02
AH		 6388
6389 return target;
6390}
6391
b4a62fa0 6392static rtx
38f391a5 6393altivec_expand_lv_builtin (enum insn_code icode, tree arglist, rtx target)
b4a62fa0
SB		 6394{
6395 rtx pat, addr;
6396 tree arg0 = TREE_VALUE (arglist);
6397 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6398 enum machine_mode tmode = insn_data[icode].operand[0].mode;
6399 enum machine_mode mode0 = Pmode;
6400 enum machine_mode mode1 = Pmode;
6401 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6402 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6403
6404 if (icode == CODE_FOR_nothing)
6405 /* Builtin not supported on this processor. */
6406 return 0;
6407
6408 /* If we got invalid arguments bail out before generating bad rtl. */
6409 if (arg0 == error_mark_node || arg1 == error_mark_node)
6410 return const0_rtx;
6411
6412 if (target == 0
6413 || GET_MODE (target) != tmode
6414 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6415 target = gen_reg_rtx (tmode);
6416
f676971a 6417 op1 = copy_to_mode_reg (mode1, op1);
b4a62fa0
SB		 6418
6419 if (op0 == const0_rtx)
6420 {
6421 addr = gen_rtx_MEM (tmode, op1);
6422 }
6423 else
6424 {
6425 op0 = copy_to_mode_reg (mode0, op0);
6426 addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op0, op1));
6427 }
6428
6429 pat = GEN_FCN (icode) (target, addr);
6430
6431 if (! pat)
6432 return 0;
6433 emit_insn (pat);
6434
6435 return target;
6436}
6437
61bea3b0
AH		 6438static rtx
6439spe_expand_stv_builtin (enum insn_code icode, tree arglist)
6440{
6441 tree arg0 = TREE_VALUE (arglist);
6442 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6443 tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
6444 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6445 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6446 rtx op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
6447 rtx pat;
6448 enum machine_mode mode0 = insn_data[icode].operand[0].mode;
6449 enum machine_mode mode1 = insn_data[icode].operand[1].mode;
6450 enum machine_mode mode2 = insn_data[icode].operand[2].mode;
6451
6452 /* Invalid arguments. Bail before doing anything stoopid! */
6453 if (arg0 == error_mark_node
6454 || arg1 == error_mark_node
6455 || arg2 == error_mark_node)
6456 return const0_rtx;
6457
6458 if (! (*insn_data[icode].operand[2].predicate) (op0, mode2))
6459 op0 = copy_to_mode_reg (mode2, op0);
6460 if (! (*insn_data[icode].operand[0].predicate) (op1, mode0))
6461 op1 = copy_to_mode_reg (mode0, op1);
6462 if (! (*insn_data[icode].operand[1].predicate) (op2, mode1))
6463 op2 = copy_to_mode_reg (mode1, op2);
6464
6465 pat = GEN_FCN (icode) (op1, op2, op0);
6466 if (pat)
6467 emit_insn (pat);
6468 return NULL_RTX;
6469}
6470
6525c0e7 6471static rtx
a2369ed3 6472altivec_expand_stv_builtin (enum insn_code icode, tree arglist)
6525c0e7
AH		 6473{
6474 tree arg0 = TREE_VALUE (arglist);
6475 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6476 tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
6477 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6478 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6479 rtx op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
b4a62fa0
SB		 6480 rtx pat, addr;
6481 enum machine_mode tmode = insn_data[icode].operand[0].mode;
6482 enum machine_mode mode1 = Pmode;
6483 enum machine_mode mode2 = Pmode;
6525c0e7
AH		 6484
6485 /* Invalid arguments. Bail before doing anything stoopid! */
6486 if (arg0 == error_mark_node
6487 || arg1 == error_mark_node
6488 || arg2 == error_mark_node)
9a171fcd 6489 return const0_rtx;
6525c0e7 6490
b4a62fa0
SB		 6491 if (! (*insn_data[icode].operand[1].predicate) (op0, tmode))
6492 op0 = copy_to_mode_reg (tmode, op0);
6493
f676971a 6494 op2 = copy_to_mode_reg (mode2, op2);
b4a62fa0
SB		 6495
6496 if (op1 == const0_rtx)
6497 {
6498 addr = gen_rtx_MEM (tmode, op2);
6499 }
6500 else
6501 {
6502 op1 = copy_to_mode_reg (mode1, op1);
6503 addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op1, op2));
6504 }
6525c0e7 6505
b4a62fa0 6506 pat = GEN_FCN (icode) (addr, op0);
6525c0e7
AH		 6507 if (pat)
6508 emit_insn (pat);
6509 return NULL_RTX;
6510}
6511
2212663f 6512static rtx
a2369ed3 6513rs6000_expand_ternop_builtin (enum insn_code icode, tree arglist, rtx target)
2212663f
DB		 6514{
6515 rtx pat;
6516 tree arg0 = TREE_VALUE (arglist);
6517 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6518 tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
6519 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6520 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6521 rtx op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
6522 enum machine_mode tmode = insn_data[icode].operand[0].mode;
6523 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
6524 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
6525 enum machine_mode mode2 = insn_data[icode].operand[3].mode;
0ac081f6 6526
774b5662
DE		 6527 if (icode == CODE_FOR_nothing)
6528 /* Builtin not supported on this processor. */
6529 return 0;
6530
20e26713
AH		 6531 /* If we got invalid arguments bail out before generating bad rtl. */
6532 if (arg0 == error_mark_node
6533 || arg1 == error_mark_node
6534 || arg2 == error_mark_node)
9a171fcd 6535 return const0_rtx;
20e26713 6536
aba5fb01
NS		 6537 if (icode == CODE_FOR_altivec_vsldoi_v4sf
6538 || icode == CODE_FOR_altivec_vsldoi_v4si
6539 || icode == CODE_FOR_altivec_vsldoi_v8hi
6540 || icode == CODE_FOR_altivec_vsldoi_v16qi)
b44140e7
AH		 6541 {
6542 /* Only allow 4-bit unsigned literals. */
8bb418a3 6543 STRIP_NOPS (arg2);
b44140e7
AH		 6544 if (TREE_CODE (arg2) != INTEGER_CST
6545 || TREE_INT_CST_LOW (arg2) & ~0xf)
6546 {
6547 error ("argument 3 must be a 4-bit unsigned literal");
e3277ffb 6548 return const0_rtx;
b44140e7 6549 }
b44140e7
AH		 6550 }
6551
c62f2db5 6552 if (target == 0
2212663f
DB		 6553 || GET_MODE (target) != tmode
6554 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6555 target = gen_reg_rtx (tmode);
6556
6557 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
6558 op0 = copy_to_mode_reg (mode0, op0);
6559 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
6560 op1 = copy_to_mode_reg (mode1, op1);
6561 if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
6562 op2 = copy_to_mode_reg (mode2, op2);
6563
6564 pat = GEN_FCN (icode) (target, op0, op1, op2);
6565 if (! pat)
6566 return 0;
6567 emit_insn (pat);
6568
6569 return target;
6570}
92898235 6571
3a9b8c7e 6572/* Expand the lvx builtins. */
0ac081f6 6573static rtx
a2369ed3 6574altivec_expand_ld_builtin (tree exp, rtx target, bool *expandedp)
0ac081f6 6575{
0ac081f6
AH		 6576 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
6577 tree arglist = TREE_OPERAND (exp, 1);
0ac081f6 6578 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
3a9b8c7e
AH		 6579 tree arg0;
6580 enum machine_mode tmode, mode0;
7c3abc73 6581 rtx pat, op0;
3a9b8c7e 6582 enum insn_code icode;
92898235 6583
0ac081f6
AH		 6584 switch (fcode)
6585 {
f18c054f 6586 case ALTIVEC_BUILTIN_LD_INTERNAL_16qi:
81466555 6587 icode = CODE_FOR_altivec_lvx_v16qi;
3a9b8c7e 6588 break;
f18c054f 6589 case ALTIVEC_BUILTIN_LD_INTERNAL_8hi:
81466555 6590 icode = CODE_FOR_altivec_lvx_v8hi;
3a9b8c7e
AH		 6591 break;
6592 case ALTIVEC_BUILTIN_LD_INTERNAL_4si:
81466555 6593 icode = CODE_FOR_altivec_lvx_v4si;
3a9b8c7e
AH		 6594 break;
6595 case ALTIVEC_BUILTIN_LD_INTERNAL_4sf:
81466555 6596 icode = CODE_FOR_altivec_lvx_v4sf;
3a9b8c7e
AH		 6597 break;
6598 default:
6599 *expandedp = false;
6600 return NULL_RTX;
6601 }
0ac081f6 6602
3a9b8c7e 6603 *expandedp = true;
f18c054f 6604
3a9b8c7e
AH		 6605 arg0 = TREE_VALUE (arglist);
6606 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6607 tmode = insn_data[icode].operand[0].mode;
6608 mode0 = insn_data[icode].operand[1].mode;
f18c054f 6609
3a9b8c7e
AH		 6610 if (target == 0
6611 || GET_MODE (target) != tmode
6612 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6613 target = gen_reg_rtx (tmode);
24408032 6614
3a9b8c7e
AH		 6615 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
6616 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
f18c054f 6617
3a9b8c7e
AH		 6618 pat = GEN_FCN (icode) (target, op0);
6619 if (! pat)
6620 return 0;
6621 emit_insn (pat);
6622 return target;
6623}
f18c054f 6624
3a9b8c7e
AH		 6625/* Expand the stvx builtins. */
6626static rtx
f676971a 6627altivec_expand_st_builtin (tree exp, rtx target ATTRIBUTE_UNUSED,
a2369ed3 6628 bool *expandedp)
3a9b8c7e
AH		 6629{
6630 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
6631 tree arglist = TREE_OPERAND (exp, 1);
6632 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
6633 tree arg0, arg1;
6634 enum machine_mode mode0, mode1;
7c3abc73 6635 rtx pat, op0, op1;
3a9b8c7e 6636 enum insn_code icode;
f18c054f 6637
3a9b8c7e
AH		 6638 switch (fcode)
6639 {
6640 case ALTIVEC_BUILTIN_ST_INTERNAL_16qi:
81466555 6641 icode = CODE_FOR_altivec_stvx_v16qi;
3a9b8c7e
AH		 6642 break;
6643 case ALTIVEC_BUILTIN_ST_INTERNAL_8hi:
81466555 6644 icode = CODE_FOR_altivec_stvx_v8hi;
3a9b8c7e
AH		 6645 break;
6646 case ALTIVEC_BUILTIN_ST_INTERNAL_4si:
81466555 6647 icode = CODE_FOR_altivec_stvx_v4si;
3a9b8c7e
AH		 6648 break;
6649 case ALTIVEC_BUILTIN_ST_INTERNAL_4sf:
81466555 6650 icode = CODE_FOR_altivec_stvx_v4sf;
3a9b8c7e
AH		 6651 break;
6652 default:
6653 *expandedp = false;
6654 return NULL_RTX;
6655 }
24408032 6656
3a9b8c7e
AH		 6657 arg0 = TREE_VALUE (arglist);
6658 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6659 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6660 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6661 mode0 = insn_data[icode].operand[0].mode;
6662 mode1 = insn_data[icode].operand[1].mode;
f18c054f 6663
3a9b8c7e
AH		 6664 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
6665 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
6666 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
6667 op1 = copy_to_mode_reg (mode1, op1);
f18c054f 6668
3a9b8c7e
AH		 6669 pat = GEN_FCN (icode) (op0, op1);
6670 if (pat)
6671 emit_insn (pat);
f18c054f 6672
3a9b8c7e
AH		 6673 *expandedp = true;
6674 return NULL_RTX;
6675}
f18c054f 6676
3a9b8c7e
AH		 6677/* Expand the dst builtins. */
6678static rtx
f676971a 6679altivec_expand_dst_builtin (tree exp, rtx target ATTRIBUTE_UNUSED,
a2369ed3 6680 bool *expandedp)
3a9b8c7e
AH		 6681{
6682 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
6683 tree arglist = TREE_OPERAND (exp, 1);
6684 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
6685 tree arg0, arg1, arg2;
6686 enum machine_mode mode0, mode1, mode2;
7c3abc73 6687 rtx pat, op0, op1, op2;
3a9b8c7e 6688 struct builtin_description *d;
a3170dc6 6689 size_t i;
f18c054f 6690
3a9b8c7e 6691 *expandedp = false;
f18c054f 6692
3a9b8c7e
AH		 6693 /* Handle DST variants. */
6694 d = (struct builtin_description *) bdesc_dst;
6695 for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++)
6696 if (d->code == fcode)
6697 {
6698 arg0 = TREE_VALUE (arglist);
6699 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6700 arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
6701 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6702 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6703 op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
6704 mode0 = insn_data[d->icode].operand[0].mode;
6705 mode1 = insn_data[d->icode].operand[1].mode;
6706 mode2 = insn_data[d->icode].operand[2].mode;
24408032 6707
3a9b8c7e
AH		 6708 /* Invalid arguments, bail out before generating bad rtl. */
6709 if (arg0 == error_mark_node
6710 || arg1 == error_mark_node
6711 || arg2 == error_mark_node)
6712 return const0_rtx;
f18c054f 6713
86e7df90 6714 *expandedp = true;
8bb418a3 6715 STRIP_NOPS (arg2);
3a9b8c7e
AH		 6716 if (TREE_CODE (arg2) != INTEGER_CST
6717 || TREE_INT_CST_LOW (arg2) & ~0x3)
6718 {
9e637a26 6719 error ("argument to %qs must be a 2-bit unsigned literal", d->name);
3a9b8c7e
AH		 6720 return const0_rtx;
6721 }
f18c054f 6722
3a9b8c7e 6723 if (! (*insn_data[d->icode].operand[0].predicate) (op0, mode0))
666158b9 6724 op0 = copy_to_mode_reg (Pmode, op0);
3a9b8c7e
AH		 6725 if (! (*insn_data[d->icode].operand[1].predicate) (op1, mode1))
6726 op1 = copy_to_mode_reg (mode1, op1);
24408032 6727
3a9b8c7e
AH		 6728 pat = GEN_FCN (d->icode) (op0, op1, op2);
6729 if (pat != 0)
6730 emit_insn (pat);
f18c054f 6731
3a9b8c7e
AH		 6732 return NULL_RTX;
6733 }
f18c054f 6734
3a9b8c7e
AH		 6735 return NULL_RTX;
6736}
24408032 6737
3a9b8c7e
AH		 6738/* Expand the builtin in EXP and store the result in TARGET. Store
6739 true in *EXPANDEDP if we found a builtin to expand. */
6740static rtx
a2369ed3 6741altivec_expand_builtin (tree exp, rtx target, bool *expandedp)
3a9b8c7e
AH		 6742{
6743 struct builtin_description *d;
6744 struct builtin_description_predicates *dp;
6745 size_t i;
6746 enum insn_code icode;
6747 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
6748 tree arglist = TREE_OPERAND (exp, 1);
7c3abc73
AH		 6749 tree arg0;
6750 rtx op0, pat;
6751 enum machine_mode tmode, mode0;
3a9b8c7e 6752 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
0ac081f6 6753
58646b77
PB		 6754 if (fcode >= ALTIVEC_BUILTIN_OVERLOADED_FIRST
6755 && fcode <= ALTIVEC_BUILTIN_OVERLOADED_LAST)
6756 {
6757 *expandedp = true;
6758 error ("unresolved overload for Altivec builtin %qE", fndecl);
6759 return const0_rtx;
6760 }
6761
3a9b8c7e
AH		 6762 target = altivec_expand_ld_builtin (exp, target, expandedp);
6763 if (*expandedp)
6764 return target;
0ac081f6 6765
3a9b8c7e
AH		 6766 target = altivec_expand_st_builtin (exp, target, expandedp);
6767 if (*expandedp)
6768 return target;
6769
6770 target = altivec_expand_dst_builtin (exp, target, expandedp);
6771 if (*expandedp)
6772 return target;
6773
6774 *expandedp = true;
95385cbb 6775
3a9b8c7e
AH		 6776 switch (fcode)
6777 {
6525c0e7
AH		 6778 case ALTIVEC_BUILTIN_STVX:
6779 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx, arglist);
6780 case ALTIVEC_BUILTIN_STVEBX:
6781 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvebx, arglist);
6782 case ALTIVEC_BUILTIN_STVEHX:
6783 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvehx, arglist);
6784 case ALTIVEC_BUILTIN_STVEWX:
6785 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvewx, arglist);
6786 case ALTIVEC_BUILTIN_STVXL:
6787 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl, arglist);
3a9b8c7e 6788
95385cbb
AH		 6789 case ALTIVEC_BUILTIN_MFVSCR:
6790 icode = CODE_FOR_altivec_mfvscr;
6791 tmode = insn_data[icode].operand[0].mode;
6792
6793 if (target == 0
6794 || GET_MODE (target) != tmode
6795 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6796 target = gen_reg_rtx (tmode);
f676971a 6797
95385cbb 6798 pat = GEN_FCN (icode) (target);
0ac081f6
AH		 6799 if (! pat)
6800 return 0;
6801 emit_insn (pat);
95385cbb
AH		 6802 return target;
6803
6804 case ALTIVEC_BUILTIN_MTVSCR:
6805 icode = CODE_FOR_altivec_mtvscr;
6806 arg0 = TREE_VALUE (arglist);
6807 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6808 mode0 = insn_data[icode].operand[0].mode;
6809
6810 /* If we got invalid arguments bail out before generating bad rtl. */
6811 if (arg0 == error_mark_node)
9a171fcd 6812 return const0_rtx;
95385cbb
AH		 6813
6814 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
6815 op0 = copy_to_mode_reg (mode0, op0);
6816
6817 pat = GEN_FCN (icode) (op0);
6818 if (pat)
6819 emit_insn (pat);
6820 return NULL_RTX;
3a9b8c7e 6821
95385cbb
AH		 6822 case ALTIVEC_BUILTIN_DSSALL:
6823 emit_insn (gen_altivec_dssall ());
6824 return NULL_RTX;
6825
6826 case ALTIVEC_BUILTIN_DSS:
6827 icode = CODE_FOR_altivec_dss;
6828 arg0 = TREE_VALUE (arglist);
8bb418a3 6829 STRIP_NOPS (arg0);
95385cbb
AH		 6830 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6831 mode0 = insn_data[icode].operand[0].mode;
6832
6833 /* If we got invalid arguments bail out before generating bad rtl. */
6834 if (arg0 == error_mark_node)
9a171fcd 6835 return const0_rtx;
95385cbb 6836
b44140e7
AH		 6837 if (TREE_CODE (arg0) != INTEGER_CST
6838 || TREE_INT_CST_LOW (arg0) & ~0x3)
6839 {
6840 error ("argument to dss must be a 2-bit unsigned literal");
9a171fcd 6841 return const0_rtx;
b44140e7
AH		 6842 }
6843
95385cbb
AH		 6844 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
6845 op0 = copy_to_mode_reg (mode0, op0);
6846
6847 emit_insn (gen_altivec_dss (op0));
0ac081f6
AH		 6848 return NULL_RTX;
6849 }
24408032 6850
100c4561
AH		 6851 /* Expand abs* operations. */
6852 d = (struct builtin_description *) bdesc_abs;
ca7558fc 6853 for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++)
100c4561
AH		 6854 if (d->code == fcode)
6855 return altivec_expand_abs_builtin (d->icode, arglist, target);
6856
ae4b4a02
AH		 6857 /* Expand the AltiVec predicates. */
6858 dp = (struct builtin_description_predicates *) bdesc_altivec_preds;
ca7558fc 6859 for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, dp++)
ae4b4a02 6860 if (dp->code == fcode)
c4ad648e
AM		 6861 return altivec_expand_predicate_builtin (dp->icode, dp->opcode,
6862 arglist, target);
ae4b4a02 6863
6525c0e7
AH		 6864 /* LV* are funky. We initialized them differently. */
6865 switch (fcode)
6866 {
6867 case ALTIVEC_BUILTIN_LVSL:
b4a62fa0 6868 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsl,
c4ad648e 6869 arglist, target);
6525c0e7 6870 case ALTIVEC_BUILTIN_LVSR:
b4a62fa0 6871 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsr,
c4ad648e 6872 arglist, target);
6525c0e7 6873 case ALTIVEC_BUILTIN_LVEBX:
b4a62fa0 6874 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvebx,
c4ad648e 6875 arglist, target);
6525c0e7 6876 case ALTIVEC_BUILTIN_LVEHX:
b4a62fa0 6877 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvehx,
c4ad648e 6878 arglist, target);
6525c0e7 6879 case ALTIVEC_BUILTIN_LVEWX:
b4a62fa0 6880 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvewx,
c4ad648e 6881 arglist, target);
6525c0e7 6882 case ALTIVEC_BUILTIN_LVXL:
b4a62fa0 6883 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl,
c4ad648e 6884 arglist, target);
6525c0e7 6885 case ALTIVEC_BUILTIN_LVX:
b4a62fa0 6886 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx,
c4ad648e 6887 arglist, target);
6525c0e7
AH		 6888 default:
6889 break;
6890 /* Fall through. */
6891 }
95385cbb 6892
92898235 6893 *expandedp = false;
0ac081f6
AH		 6894 return NULL_RTX;
6895}
6896
a3170dc6
AH		 6897/* Binops that need to be initialized manually, but can be expanded
6898 automagically by rs6000_expand_binop_builtin. */
6899static struct builtin_description bdesc_2arg_spe[] =
6900{
6901 { 0, CODE_FOR_spe_evlddx, "__builtin_spe_evlddx", SPE_BUILTIN_EVLDDX },
6902 { 0, CODE_FOR_spe_evldwx, "__builtin_spe_evldwx", SPE_BUILTIN_EVLDWX },
6903 { 0, CODE_FOR_spe_evldhx, "__builtin_spe_evldhx", SPE_BUILTIN_EVLDHX },
6904 { 0, CODE_FOR_spe_evlwhex, "__builtin_spe_evlwhex", SPE_BUILTIN_EVLWHEX },
6905 { 0, CODE_FOR_spe_evlwhoux, "__builtin_spe_evlwhoux", SPE_BUILTIN_EVLWHOUX },
6906 { 0, CODE_FOR_spe_evlwhosx, "__builtin_spe_evlwhosx", SPE_BUILTIN_EVLWHOSX },
6907 { 0, CODE_FOR_spe_evlwwsplatx, "__builtin_spe_evlwwsplatx", SPE_BUILTIN_EVLWWSPLATX },
6908 { 0, CODE_FOR_spe_evlwhsplatx, "__builtin_spe_evlwhsplatx", SPE_BUILTIN_EVLWHSPLATX },
6909 { 0, CODE_FOR_spe_evlhhesplatx, "__builtin_spe_evlhhesplatx", SPE_BUILTIN_EVLHHESPLATX },
6910 { 0, CODE_FOR_spe_evlhhousplatx, "__builtin_spe_evlhhousplatx", SPE_BUILTIN_EVLHHOUSPLATX },
6911 { 0, CODE_FOR_spe_evlhhossplatx, "__builtin_spe_evlhhossplatx", SPE_BUILTIN_EVLHHOSSPLATX },
6912 { 0, CODE_FOR_spe_evldd, "__builtin_spe_evldd", SPE_BUILTIN_EVLDD },
6913 { 0, CODE_FOR_spe_evldw, "__builtin_spe_evldw", SPE_BUILTIN_EVLDW },
6914 { 0, CODE_FOR_spe_evldh, "__builtin_spe_evldh", SPE_BUILTIN_EVLDH },
6915 { 0, CODE_FOR_spe_evlwhe, "__builtin_spe_evlwhe", SPE_BUILTIN_EVLWHE },
6916 { 0, CODE_FOR_spe_evlwhou, "__builtin_spe_evlwhou", SPE_BUILTIN_EVLWHOU },
6917 { 0, CODE_FOR_spe_evlwhos, "__builtin_spe_evlwhos", SPE_BUILTIN_EVLWHOS },
6918 { 0, CODE_FOR_spe_evlwwsplat, "__builtin_spe_evlwwsplat", SPE_BUILTIN_EVLWWSPLAT },
6919 { 0, CODE_FOR_spe_evlwhsplat, "__builtin_spe_evlwhsplat", SPE_BUILTIN_EVLWHSPLAT },
6920 { 0, CODE_FOR_spe_evlhhesplat, "__builtin_spe_evlhhesplat", SPE_BUILTIN_EVLHHESPLAT },
6921 { 0, CODE_FOR_spe_evlhhousplat, "__builtin_spe_evlhhousplat", SPE_BUILTIN_EVLHHOUSPLAT },
6922 { 0, CODE_FOR_spe_evlhhossplat, "__builtin_spe_evlhhossplat", SPE_BUILTIN_EVLHHOSSPLAT }
6923};
6924
6925/* Expand the builtin in EXP and store the result in TARGET. Store
6926 true in *EXPANDEDP if we found a builtin to expand.
6927
6928 This expands the SPE builtins that are not simple unary and binary
6929 operations. */
6930static rtx
a2369ed3 6931spe_expand_builtin (tree exp, rtx target, bool *expandedp)
a3170dc6
AH		 6932{
6933 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
6934 tree arglist = TREE_OPERAND (exp, 1);
6935 tree arg1, arg0;
6936 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
6937 enum insn_code icode;
6938 enum machine_mode tmode, mode0;
6939 rtx pat, op0;
6940 struct builtin_description *d;
6941 size_t i;
6942
6943 *expandedp = true;
6944
6945 /* Syntax check for a 5-bit unsigned immediate. */
6946 switch (fcode)
6947 {
6948 case SPE_BUILTIN_EVSTDD:
6949 case SPE_BUILTIN_EVSTDH:
6950 case SPE_BUILTIN_EVSTDW:
6951 case SPE_BUILTIN_EVSTWHE:
6952 case SPE_BUILTIN_EVSTWHO:
6953 case SPE_BUILTIN_EVSTWWE:
6954 case SPE_BUILTIN_EVSTWWO:
6955 arg1 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
6956 if (TREE_CODE (arg1) != INTEGER_CST
6957 || TREE_INT_CST_LOW (arg1) & ~0x1f)
6958 {
6959 error ("argument 2 must be a 5-bit unsigned literal");
6960 return const0_rtx;
6961 }
6962 break;
6963 default:
6964 break;
6965 }
6966
00332c9f
AH		 6967 /* The evsplat*i instructions are not quite generic. */
6968 switch (fcode)
6969 {
6970 case SPE_BUILTIN_EVSPLATFI:
6971 return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplatfi,
6972 arglist, target);
6973 case SPE_BUILTIN_EVSPLATI:
6974 return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplati,
6975 arglist, target);
6976 default:
6977 break;
6978 }
6979
a3170dc6
AH		 6980 d = (struct builtin_description *) bdesc_2arg_spe;
6981 for (i = 0; i < ARRAY_SIZE (bdesc_2arg_spe); ++i, ++d)
6982 if (d->code == fcode)
6983 return rs6000_expand_binop_builtin (d->icode, arglist, target);
6984
6985 d = (struct builtin_description *) bdesc_spe_predicates;
6986 for (i = 0; i < ARRAY_SIZE (bdesc_spe_predicates); ++i, ++d)
6987 if (d->code == fcode)
6988 return spe_expand_predicate_builtin (d->icode, arglist, target);
6989
6990 d = (struct builtin_description *) bdesc_spe_evsel;
6991 for (i = 0; i < ARRAY_SIZE (bdesc_spe_evsel); ++i, ++d)
6992 if (d->code == fcode)
6993 return spe_expand_evsel_builtin (d->icode, arglist, target);
6994
6995 switch (fcode)
6996 {
6997 case SPE_BUILTIN_EVSTDDX:
61bea3b0 6998 return spe_expand_stv_builtin (CODE_FOR_spe_evstddx, arglist);
a3170dc6 6999 case SPE_BUILTIN_EVSTDHX:
61bea3b0 7000 return spe_expand_stv_builtin (CODE_FOR_spe_evstdhx, arglist);
a3170dc6 7001 case SPE_BUILTIN_EVSTDWX:
61bea3b0 7002 return spe_expand_stv_builtin (CODE_FOR_spe_evstdwx, arglist);
a3170dc6 7003 case SPE_BUILTIN_EVSTWHEX:
61bea3b0 7004 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhex, arglist);
a3170dc6 7005 case SPE_BUILTIN_EVSTWHOX:
61bea3b0 7006 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhox, arglist);
a3170dc6 7007 case SPE_BUILTIN_EVSTWWEX:
61bea3b0 7008 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwex, arglist);
a3170dc6 7009 case SPE_BUILTIN_EVSTWWOX:
61bea3b0 7010 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwox, arglist);
a3170dc6 7011 case SPE_BUILTIN_EVSTDD:
61bea3b0 7012 return spe_expand_stv_builtin (CODE_FOR_spe_evstdd, arglist);
a3170dc6 7013 case SPE_BUILTIN_EVSTDH:
61bea3b0 7014 return spe_expand_stv_builtin (CODE_FOR_spe_evstdh, arglist);
a3170dc6 7015 case SPE_BUILTIN_EVSTDW:
61bea3b0 7016 return spe_expand_stv_builtin (CODE_FOR_spe_evstdw, arglist);
a3170dc6 7017 case SPE_BUILTIN_EVSTWHE:
61bea3b0 7018 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhe, arglist);
a3170dc6 7019 case SPE_BUILTIN_EVSTWHO:
61bea3b0 7020 return spe_expand_stv_builtin (CODE_FOR_spe_evstwho, arglist);
a3170dc6 7021 case SPE_BUILTIN_EVSTWWE:
61bea3b0 7022 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwe, arglist);
a3170dc6 7023 case SPE_BUILTIN_EVSTWWO:
61bea3b0 7024 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwo, arglist);
a3170dc6
AH		 7025 case SPE_BUILTIN_MFSPEFSCR:
7026 icode = CODE_FOR_spe_mfspefscr;
7027 tmode = insn_data[icode].operand[0].mode;
7028
7029 if (target == 0
7030 || GET_MODE (target) != tmode
7031 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7032 target = gen_reg_rtx (tmode);
f676971a 7033
a3170dc6
AH		 7034 pat = GEN_FCN (icode) (target);
7035 if (! pat)
7036 return 0;
7037 emit_insn (pat);
7038 return target;
7039 case SPE_BUILTIN_MTSPEFSCR:
7040 icode = CODE_FOR_spe_mtspefscr;
7041 arg0 = TREE_VALUE (arglist);
7042 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
7043 mode0 = insn_data[icode].operand[0].mode;
7044
7045 if (arg0 == error_mark_node)
7046 return const0_rtx;
7047
7048 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
7049 op0 = copy_to_mode_reg (mode0, op0);
7050
7051 pat = GEN_FCN (icode) (op0);
7052 if (pat)
7053 emit_insn (pat);
7054 return NULL_RTX;
7055 default:
7056 break;
7057 }
7058
7059 *expandedp = false;
7060 return NULL_RTX;
7061}
7062
7063static rtx
a2369ed3 7064spe_expand_predicate_builtin (enum insn_code icode, tree arglist, rtx target)
a3170dc6
AH		 7065{
7066 rtx pat, scratch, tmp;
7067 tree form = TREE_VALUE (arglist);
7068 tree arg0 = TREE_VALUE (TREE_CHAIN (arglist));
7069 tree arg1 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
7070 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
7071 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
7072 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
7073 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
7074 int form_int;
7075 enum rtx_code code;
7076
7077 if (TREE_CODE (form) != INTEGER_CST)
7078 {
7079 error ("argument 1 of __builtin_spe_predicate must be a constant");
7080 return const0_rtx;
7081 }
7082 else
7083 form_int = TREE_INT_CST_LOW (form);
7084
37409796 7085 gcc_assert (mode0 == mode1);
a3170dc6
AH		 7086
7087 if (arg0 == error_mark_node || arg1 == error_mark_node)
7088 return const0_rtx;
7089
7090 if (target == 0
7091 || GET_MODE (target) != SImode
7092 || ! (*insn_data[icode].operand[0].predicate) (target, SImode))
7093 target = gen_reg_rtx (SImode);
7094
7095 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
7096 op0 = copy_to_mode_reg (mode0, op0);
7097 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
7098 op1 = copy_to_mode_reg (mode1, op1);
7099
7100 scratch = gen_reg_rtx (CCmode);
7101
7102 pat = GEN_FCN (icode) (scratch, op0, op1);
7103 if (! pat)
7104 return const0_rtx;
7105 emit_insn (pat);
7106
7107 /* There are 4 variants for each predicate: _any_, _all_, _upper_,
7108 _lower_. We use one compare, but look in different bits of the
7109 CR for each variant.
7110
7111 There are 2 elements in each SPE simd type (upper/lower). The CR
7112 bits are set as follows:
7113
7114 BIT0 | BIT 1 | BIT 2 | BIT 3
7115 U | L | (U | L) | (U & L)
7116
7117 So, for an "all" relationship, BIT 3 would be set.
7118 For an "any" relationship, BIT 2 would be set. Etc.
7119
7120 Following traditional nomenclature, these bits map to:
7121
7122 BIT0 | BIT 1 | BIT 2 | BIT 3
7123 LT | GT | EQ | OV
7124
7125 Later, we will generate rtl to look in the LT/EQ/EQ/OV bits.
7126 */
7127
7128 switch (form_int)
7129 {
7130 /* All variant. OV bit. */
7131 case 0:
7132 /* We need to get to the OV bit, which is the ORDERED bit. We
7133 could generate (ordered:SI (reg:CC xx) (const_int 0)), but
992d08b1 7134 that's ugly and will make validate_condition_mode die.
a3170dc6
AH		 7135 So let's just use another pattern. */
7136 emit_insn (gen_move_from_CR_ov_bit (target, scratch));
7137 return target;
7138 /* Any variant. EQ bit. */
7139 case 1:
7140 code = EQ;
7141 break;
7142 /* Upper variant. LT bit. */
7143 case 2:
7144 code = LT;
7145 break;
7146 /* Lower variant. GT bit. */
7147 case 3:
7148 code = GT;
7149 break;
7150 default:
7151 error ("argument 1 of __builtin_spe_predicate is out of range");
7152 return const0_rtx;
7153 }
7154
7155 tmp = gen_rtx_fmt_ee (code, SImode, scratch, const0_rtx);
7156 emit_move_insn (target, tmp);
7157
7158 return target;
7159}
7160
7161/* The evsel builtins look like this:
7162
7163 e = __builtin_spe_evsel_OP (a, b, c, d);
7164
7165 and work like this:
7166
7167 e[upper] = a[upper] *OP* b[upper] ? c[upper] : d[upper];
7168 e[lower] = a[lower] *OP* b[lower] ? c[lower] : d[lower];
7169*/
7170
7171static rtx
a2369ed3 7172spe_expand_evsel_builtin (enum insn_code icode, tree arglist, rtx target)
a3170dc6
AH		 7173{
7174 rtx pat, scratch;
7175 tree arg0 = TREE_VALUE (arglist);
7176 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
7177 tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
7178 tree arg3 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (TREE_CHAIN (arglist))));
7179 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
7180 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
7181 rtx op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
7182 rtx op3 = expand_expr (arg3, NULL_RTX, VOIDmode, 0);
7183 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
7184 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
7185
37409796 7186 gcc_assert (mode0 == mode1);
a3170dc6
AH		 7187
7188 if (arg0 == error_mark_node || arg1 == error_mark_node
7189 || arg2 == error_mark_node || arg3 == error_mark_node)
7190 return const0_rtx;
7191
7192 if (target == 0
7193 || GET_MODE (target) != mode0
7194 || ! (*insn_data[icode].operand[0].predicate) (target, mode0))
7195 target = gen_reg_rtx (mode0);
7196
7197 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
7198 op0 = copy_to_mode_reg (mode0, op0);
7199 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
7200 op1 = copy_to_mode_reg (mode0, op1);
7201 if (! (*insn_data[icode].operand[1].predicate) (op2, mode1))
7202 op2 = copy_to_mode_reg (mode0, op2);
7203 if (! (*insn_data[icode].operand[1].predicate) (op3, mode1))
7204 op3 = copy_to_mode_reg (mode0, op3);
7205
7206 /* Generate the compare. */
7207 scratch = gen_reg_rtx (CCmode);
7208 pat = GEN_FCN (icode) (scratch, op0, op1);
7209 if (! pat)
7210 return const0_rtx;
7211 emit_insn (pat);
7212
7213 if (mode0 == V2SImode)
7214 emit_insn (gen_spe_evsel (target, op2, op3, scratch));
7215 else
7216 emit_insn (gen_spe_evsel_fs (target, op2, op3, scratch));
7217
7218 return target;
7219}
7220
0ac081f6
AH		 7221/* Expand an expression EXP that calls a built-in function,
7222 with result going to TARGET if that's convenient
7223 (and in mode MODE if that's convenient).
7224 SUBTARGET may be used as the target for computing one of EXP's operands.
7225 IGNORE is nonzero if the value is to be ignored. */
7226
7227static rtx
a2369ed3 7228rs6000_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
c4ad648e
AM		 7229 enum machine_mode mode ATTRIBUTE_UNUSED,
7230 int ignore ATTRIBUTE_UNUSED)
0ac081f6 7231{
92898235
AH		 7232 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
7233 tree arglist = TREE_OPERAND (exp, 1);
7234 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
7235 struct builtin_description *d;
7236 size_t i;
7237 rtx ret;
7238 bool success;
f676971a 7239
7ccf35ed
DN		 7240 if (fcode == ALTIVEC_BUILTIN_MASK_FOR_LOAD
7241 || fcode == ALTIVEC_BUILTIN_MASK_FOR_STORE)
7242 {
7243 int icode = (int) CODE_FOR_altivec_lvsr;
7244 enum machine_mode tmode = insn_data[icode].operand[0].mode;
7245 enum machine_mode mode = insn_data[icode].operand[1].mode;
7246 tree arg;
7247 rtx op, addr, pat;
7248
37409796 7249 gcc_assert (TARGET_ALTIVEC);
7ccf35ed
DN		 7250
7251 arg = TREE_VALUE (arglist);
37409796 7252 gcc_assert (TREE_CODE (TREE_TYPE (arg)) == POINTER_TYPE);
7ccf35ed
DN		 7253 op = expand_expr (arg, NULL_RTX, Pmode, EXPAND_NORMAL);
7254 addr = memory_address (mode, op);
7255 if (fcode == ALTIVEC_BUILTIN_MASK_FOR_STORE)
7256 op = addr;
7257 else
7258 {
7259 /* For the load case need to negate the address. */
7260 op = gen_reg_rtx (GET_MODE (addr));
7261 emit_insn (gen_rtx_SET (VOIDmode, op,
7262 gen_rtx_NEG (GET_MODE (addr), addr)));
c4ad648e 7263 }
7ccf35ed
DN		 7264 op = gen_rtx_MEM (mode, op);
7265
7266 if (target == 0
7267 || GET_MODE (target) != tmode
7268 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7269 target = gen_reg_rtx (tmode);
7270
7271 /*pat = gen_altivec_lvsr (target, op);*/
7272 pat = GEN_FCN (icode) (target, op);
7273 if (!pat)
7274 return 0;
7275 emit_insn (pat);
7276
7277 return target;
7278 }
7279
0ac081f6 7280 if (TARGET_ALTIVEC)
92898235
AH		 7281 {
7282 ret = altivec_expand_builtin (exp, target, &success);
7283
a3170dc6
AH		 7284 if (success)
7285 return ret;
7286 }
7287 if (TARGET_SPE)
7288 {
7289 ret = spe_expand_builtin (exp, target, &success);
7290
92898235
AH		 7291 if (success)
7292 return ret;
7293 }
7294
37409796
NS		 7295 gcc_assert (TARGET_ALTIVEC || TARGET_SPE);
7296
7297 /* Handle simple unary operations. */
7298 d = (struct builtin_description *) bdesc_1arg;
7299 for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
7300 if (d->code == fcode)
7301 return rs6000_expand_unop_builtin (d->icode, arglist, target);
7302
7303 /* Handle simple binary operations. */
7304 d = (struct builtin_description *) bdesc_2arg;
7305 for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
7306 if (d->code == fcode)
7307 return rs6000_expand_binop_builtin (d->icode, arglist, target);
0ac081f6 7308
37409796
NS		 7309 /* Handle simple ternary operations. */
7310 d = (struct builtin_description *) bdesc_3arg;
7311 for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++)
7312 if (d->code == fcode)
7313 return rs6000_expand_ternop_builtin (d->icode, arglist, target);
7314
7315 gcc_unreachable ();
0ac081f6
AH		 7316}
7317
7c62e993
PB		 7318static tree
7319build_opaque_vector_type (tree node, int nunits)
7320{
7321 node = copy_node (node);
7322 TYPE_MAIN_VARIANT (node) = node;
7323 return build_vector_type (node, nunits);
7324}
7325
0ac081f6 7326static void
863d938c 7327rs6000_init_builtins (void)
0ac081f6 7328{
4a5eab38
PB		 7329 V2SI_type_node = build_vector_type (intSI_type_node, 2);
7330 V2SF_type_node = build_vector_type (float_type_node, 2);
7331 V4HI_type_node = build_vector_type (intHI_type_node, 4);
7332 V4SI_type_node = build_vector_type (intSI_type_node, 4);
7333 V4SF_type_node = build_vector_type (float_type_node, 4);
7e463bda 7334 V8HI_type_node = build_vector_type (intHI_type_node, 8);
4a5eab38
PB		 7335 V16QI_type_node = build_vector_type (intQI_type_node, 16);
7336
7337 unsigned_V16QI_type_node = build_vector_type (unsigned_intQI_type_node, 16);
7338 unsigned_V8HI_type_node = build_vector_type (unsigned_intHI_type_node, 8);
7339 unsigned_V4SI_type_node = build_vector_type (unsigned_intSI_type_node, 4);
7340
7c62e993
PB		 7341 opaque_V2SF_type_node = build_opaque_vector_type (float_type_node, 2);
7342 opaque_V2SI_type_node = build_opaque_vector_type (intSI_type_node, 2);
6035d635 7343 opaque_p_V2SI_type_node = build_pointer_type (opaque_V2SI_type_node);
58646b77 7344 opaque_V4SI_type_node = copy_node (V4SI_type_node);
3fdaa45a 7345
8bb418a3
ZL		 7346 /* The 'vector bool ...' types must be kept distinct from 'vector unsigned ...'
7347 types, especially in C++ land. Similarly, 'vector pixel' is distinct from
7348 'vector unsigned short'. */
7349
8dd16ecc
NS		 7350 bool_char_type_node = build_distinct_type_copy (unsigned_intQI_type_node);
7351 bool_short_type_node = build_distinct_type_copy (unsigned_intHI_type_node);
7352 bool_int_type_node = build_distinct_type_copy (unsigned_intSI_type_node);
7353 pixel_type_node = build_distinct_type_copy (unsigned_intHI_type_node);
8bb418a3 7354
58646b77
PB		 7355 long_integer_type_internal_node = long_integer_type_node;
7356 long_unsigned_type_internal_node = long_unsigned_type_node;
7357 intQI_type_internal_node = intQI_type_node;
7358 uintQI_type_internal_node = unsigned_intQI_type_node;
7359 intHI_type_internal_node = intHI_type_node;
7360 uintHI_type_internal_node = unsigned_intHI_type_node;
7361 intSI_type_internal_node = intSI_type_node;
7362 uintSI_type_internal_node = unsigned_intSI_type_node;
7363 float_type_internal_node = float_type_node;
7364 void_type_internal_node = void_type_node;
7365
8bb418a3
ZL		 7366 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7367 get_identifier ("__bool char"),
7368 bool_char_type_node));
7369 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7370 get_identifier ("__bool short"),
7371 bool_short_type_node));
7372 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7373 get_identifier ("__bool int"),
7374 bool_int_type_node));
7375 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7376 get_identifier ("__pixel"),
7377 pixel_type_node));
7378
4a5eab38
PB		 7379 bool_V16QI_type_node = build_vector_type (bool_char_type_node, 16);
7380 bool_V8HI_type_node = build_vector_type (bool_short_type_node, 8);
7381 bool_V4SI_type_node = build_vector_type (bool_int_type_node, 4);
7382 pixel_V8HI_type_node = build_vector_type (pixel_type_node, 8);
8bb418a3
ZL		 7383
7384 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7385 get_identifier ("__vector unsigned char"),
7386 unsigned_V16QI_type_node));
7387 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7388 get_identifier ("__vector signed char"),
7389 V16QI_type_node));
7390 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7391 get_identifier ("__vector __bool char"),
7392 bool_V16QI_type_node));
7393
7394 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7395 get_identifier ("__vector unsigned short"),
7396 unsigned_V8HI_type_node));
7397 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7398 get_identifier ("__vector signed short"),
7399 V8HI_type_node));
7400 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7401 get_identifier ("__vector __bool short"),
7402 bool_V8HI_type_node));
7403
7404 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7405 get_identifier ("__vector unsigned int"),
7406 unsigned_V4SI_type_node));
7407 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7408 get_identifier ("__vector signed int"),
7409 V4SI_type_node));
7410 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7411 get_identifier ("__vector __bool int"),
7412 bool_V4SI_type_node));
7413
7414 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7415 get_identifier ("__vector float"),
7416 V4SF_type_node));
7417 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7418 get_identifier ("__vector __pixel"),
7419 pixel_V8HI_type_node));
7420
a3170dc6 7421 if (TARGET_SPE)
3fdaa45a 7422 spe_init_builtins ();
0ac081f6
AH		 7423 if (TARGET_ALTIVEC)
7424 altivec_init_builtins ();
0559cc77
DE		 7425 if (TARGET_ALTIVEC || TARGET_SPE)
7426 rs6000_common_init_builtins ();
0ac081f6
AH		 7427}
7428
a3170dc6
AH		 7429/* Search through a set of builtins and enable the mask bits.
7430 DESC is an array of builtins.
b6d08ca1 7431 SIZE is the total number of builtins.
a3170dc6
AH		 7432 START is the builtin enum at which to start.
7433 END is the builtin enum at which to end. */
0ac081f6 7434static void
a2369ed3 7435enable_mask_for_builtins (struct builtin_description *desc, int size,
f676971a 7436 enum rs6000_builtins start,
a2369ed3 7437 enum rs6000_builtins end)
a3170dc6
AH		 7438{
7439 int i;
7440
7441 for (i = 0; i < size; ++i)
7442 if (desc[i].code == start)
7443 break;
7444
7445 if (i == size)
7446 return;
7447
7448 for (; i < size; ++i)
7449 {
7450 /* Flip all the bits on. */
7451 desc[i].mask = target_flags;
7452 if (desc[i].code == end)
7453 break;
7454 }
7455}
7456
7457static void
863d938c 7458spe_init_builtins (void)
0ac081f6 7459{
a3170dc6
AH		 7460 tree endlink = void_list_node;
7461 tree puint_type_node = build_pointer_type (unsigned_type_node);
7462 tree pushort_type_node = build_pointer_type (short_unsigned_type_node);
ae4b4a02 7463 struct builtin_description *d;
0ac081f6
AH		 7464 size_t i;
7465
a3170dc6
AH		 7466 tree v2si_ftype_4_v2si
7467 = build_function_type
3fdaa45a
AH		 7468 (opaque_V2SI_type_node,
7469 tree_cons (NULL_TREE, opaque_V2SI_type_node,
7470 tree_cons (NULL_TREE, opaque_V2SI_type_node,
7471 tree_cons (NULL_TREE, opaque_V2SI_type_node,
7472 tree_cons (NULL_TREE, opaque_V2SI_type_node,
a3170dc6
AH		 7473 endlink)))));
7474
7475 tree v2sf_ftype_4_v2sf
7476 = build_function_type
3fdaa45a
AH		 7477 (opaque_V2SF_type_node,
7478 tree_cons (NULL_TREE, opaque_V2SF_type_node,
7479 tree_cons (NULL_TREE, opaque_V2SF_type_node,
7480 tree_cons (NULL_TREE, opaque_V2SF_type_node,
7481 tree_cons (NULL_TREE, opaque_V2SF_type_node,
a3170dc6
AH		 7482 endlink)))));
7483
7484 tree int_ftype_int_v2si_v2si
7485 = build_function_type
7486 (integer_type_node,
7487 tree_cons (NULL_TREE, integer_type_node,
3fdaa45a
AH		 7488 tree_cons (NULL_TREE, opaque_V2SI_type_node,
7489 tree_cons (NULL_TREE, opaque_V2SI_type_node,
a3170dc6
AH		 7490 endlink))));
7491
7492 tree int_ftype_int_v2sf_v2sf
7493 = build_function_type
7494 (integer_type_node,
7495 tree_cons (NULL_TREE, integer_type_node,
3fdaa45a
AH		 7496 tree_cons (NULL_TREE, opaque_V2SF_type_node,
7497 tree_cons (NULL_TREE, opaque_V2SF_type_node,
a3170dc6
AH		 7498 endlink))));
7499
7500 tree void_ftype_v2si_puint_int
7501 = build_function_type (void_type_node,
3fdaa45a 7502 tree_cons (NULL_TREE, opaque_V2SI_type_node,
a3170dc6
AH		 7503 tree_cons (NULL_TREE, puint_type_node,
7504 tree_cons (NULL_TREE,
7505 integer_type_node,
7506 endlink))));
7507
7508 tree void_ftype_v2si_puint_char
7509 = build_function_type (void_type_node,
3fdaa45a 7510 tree_cons (NULL_TREE, opaque_V2SI_type_node,
a3170dc6
AH		 7511 tree_cons (NULL_TREE, puint_type_node,
7512 tree_cons (NULL_TREE,
7513 char_type_node,
7514 endlink))));
7515
7516 tree void_ftype_v2si_pv2si_int
7517 = build_function_type (void_type_node,
3fdaa45a 7518 tree_cons (NULL_TREE, opaque_V2SI_type_node,
6035d635 7519 tree_cons (NULL_TREE, opaque_p_V2SI_type_node,
a3170dc6
AH		 7520 tree_cons (NULL_TREE,
7521 integer_type_node,
7522 endlink))));
7523
7524 tree void_ftype_v2si_pv2si_char
7525 = build_function_type (void_type_node,
3fdaa45a 7526 tree_cons (NULL_TREE, opaque_V2SI_type_node,
6035d635 7527 tree_cons (NULL_TREE, opaque_p_V2SI_type_node,
a3170dc6
AH		 7528 tree_cons (NULL_TREE,
7529 char_type_node,
7530 endlink))));
7531
7532 tree void_ftype_int
7533 = build_function_type (void_type_node,
7534 tree_cons (NULL_TREE, integer_type_node, endlink));
7535
7536 tree int_ftype_void
36e8d515 7537 = build_function_type (integer_type_node, endlink);
a3170dc6
AH		 7538
7539 tree v2si_ftype_pv2si_int
3fdaa45a 7540 = build_function_type (opaque_V2SI_type_node,
6035d635 7541 tree_cons (NULL_TREE, opaque_p_V2SI_type_node,
a3170dc6
AH		 7542 tree_cons (NULL_TREE, integer_type_node,
7543 endlink)));
7544
7545 tree v2si_ftype_puint_int
3fdaa45a 7546 = build_function_type (opaque_V2SI_type_node,
a3170dc6
AH		 7547 tree_cons (NULL_TREE, puint_type_node,
7548 tree_cons (NULL_TREE, integer_type_node,
7549 endlink)));
7550
7551 tree v2si_ftype_pushort_int
3fdaa45a 7552 = build_function_type (opaque_V2SI_type_node,
a3170dc6
AH		 7553 tree_cons (NULL_TREE, pushort_type_node,
7554 tree_cons (NULL_TREE, integer_type_node,
7555 endlink)));
7556
00332c9f
AH		 7557 tree v2si_ftype_signed_char
7558 = build_function_type (opaque_V2SI_type_node,
7559 tree_cons (NULL_TREE, signed_char_type_node,
7560 endlink));
7561
a3170dc6
AH		 7562 /* The initialization of the simple binary and unary builtins is
7563 done in rs6000_common_init_builtins, but we have to enable the
7564 mask bits here manually because we have run out of `target_flags'
7565 bits. We really need to redesign this mask business. */
7566
7567 enable_mask_for_builtins ((struct builtin_description *) bdesc_2arg,
7568 ARRAY_SIZE (bdesc_2arg),
7569 SPE_BUILTIN_EVADDW,
7570 SPE_BUILTIN_EVXOR);
7571 enable_mask_for_builtins ((struct builtin_description *) bdesc_1arg,
7572 ARRAY_SIZE (bdesc_1arg),
7573 SPE_BUILTIN_EVABS,
7574 SPE_BUILTIN_EVSUBFUSIAAW);
7575 enable_mask_for_builtins ((struct builtin_description *) bdesc_spe_predicates,
7576 ARRAY_SIZE (bdesc_spe_predicates),
7577 SPE_BUILTIN_EVCMPEQ,
7578 SPE_BUILTIN_EVFSTSTLT);
7579 enable_mask_for_builtins ((struct builtin_description *) bdesc_spe_evsel,
7580 ARRAY_SIZE (bdesc_spe_evsel),
7581 SPE_BUILTIN_EVSEL_CMPGTS,
7582 SPE_BUILTIN_EVSEL_FSTSTEQ);
7583
36252949
AH		 7584 (*lang_hooks.decls.pushdecl)
7585 (build_decl (TYPE_DECL, get_identifier ("__ev64_opaque__"),
7586 opaque_V2SI_type_node));
7587
a3170dc6 7588 /* Initialize irregular SPE builtins. */
f676971a 7589
a3170dc6
AH		 7590 def_builtin (target_flags, "__builtin_spe_mtspefscr", void_ftype_int, SPE_BUILTIN_MTSPEFSCR);
7591 def_builtin (target_flags, "__builtin_spe_mfspefscr", int_ftype_void, SPE_BUILTIN_MFSPEFSCR);
7592 def_builtin (target_flags, "__builtin_spe_evstddx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDDX);
7593 def_builtin (target_flags, "__builtin_spe_evstdhx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDHX);
7594 def_builtin (target_flags, "__builtin_spe_evstdwx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDWX);
7595 def_builtin (target_flags, "__builtin_spe_evstwhex", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWHEX);
7596 def_builtin (target_flags, "__builtin_spe_evstwhox", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWHOX);
7597 def_builtin (target_flags, "__builtin_spe_evstwwex", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWWEX);
7598 def_builtin (target_flags, "__builtin_spe_evstwwox", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWWOX);
7599 def_builtin (target_flags, "__builtin_spe_evstdd", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDD);
7600 def_builtin (target_flags, "__builtin_spe_evstdh", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDH);
7601 def_builtin (target_flags, "__builtin_spe_evstdw", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDW);
7602 def_builtin (target_flags, "__builtin_spe_evstwhe", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWHE);
7603 def_builtin (target_flags, "__builtin_spe_evstwho", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWHO);
7604 def_builtin (target_flags, "__builtin_spe_evstwwe", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWWE);
7605 def_builtin (target_flags, "__builtin_spe_evstwwo", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWWO);
00332c9f
AH		 7606 def_builtin (target_flags, "__builtin_spe_evsplatfi", v2si_ftype_signed_char, SPE_BUILTIN_EVSPLATFI);
7607 def_builtin (target_flags, "__builtin_spe_evsplati", v2si_ftype_signed_char, SPE_BUILTIN_EVSPLATI);
a3170dc6
AH		 7608
7609 /* Loads. */
7610 def_builtin (target_flags, "__builtin_spe_evlddx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDDX);
7611 def_builtin (target_flags, "__builtin_spe_evldwx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDWX);
7612 def_builtin (target_flags, "__builtin_spe_evldhx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDHX);
7613 def_builtin (target_flags, "__builtin_spe_evlwhex", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHEX);
7614 def_builtin (target_flags, "__builtin_spe_evlwhoux", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOUX);
7615 def_builtin (target_flags, "__builtin_spe_evlwhosx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOSX);
7616 def_builtin (target_flags, "__builtin_spe_evlwwsplatx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWWSPLATX);
7617 def_builtin (target_flags, "__builtin_spe_evlwhsplatx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHSPLATX);
7618 def_builtin (target_flags, "__builtin_spe_evlhhesplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHESPLATX);
7619 def_builtin (target_flags, "__builtin_spe_evlhhousplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOUSPLATX);
7620 def_builtin (target_flags, "__builtin_spe_evlhhossplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOSSPLATX);
7621 def_builtin (target_flags, "__builtin_spe_evldd", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDD);
7622 def_builtin (target_flags, "__builtin_spe_evldw", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDW);
7623 def_builtin (target_flags, "__builtin_spe_evldh", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDH);
7624 def_builtin (target_flags, "__builtin_spe_evlhhesplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHESPLAT);
7625 def_builtin (target_flags, "__builtin_spe_evlhhossplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOSSPLAT);
7626 def_builtin (target_flags, "__builtin_spe_evlhhousplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOUSPLAT);
7627 def_builtin (target_flags, "__builtin_spe_evlwhe", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHE);
7628 def_builtin (target_flags, "__builtin_spe_evlwhos", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOS);
7629 def_builtin (target_flags, "__builtin_spe_evlwhou", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOU);
7630 def_builtin (target_flags, "__builtin_spe_evlwhsplat", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHSPLAT);
7631 def_builtin (target_flags, "__builtin_spe_evlwwsplat", v2si_ftype_puint_int, SPE_BUILTIN_EVLWWSPLAT);
7632
7633 /* Predicates. */
7634 d = (struct builtin_description *) bdesc_spe_predicates;
7635 for (i = 0; i < ARRAY_SIZE (bdesc_spe_predicates); ++i, d++)
7636 {
7637 tree type;
7638
7639 switch (insn_data[d->icode].operand[1].mode)
7640 {
7641 case V2SImode:
7642 type = int_ftype_int_v2si_v2si;
7643 break;
7644 case V2SFmode:
7645 type = int_ftype_int_v2sf_v2sf;
7646 break;
7647 default:
37409796 7648 gcc_unreachable ();
a3170dc6
AH		 7649 }
7650
7651 def_builtin (d->mask, d->name, type, d->code);
7652 }
7653
7654 /* Evsel predicates. */
7655 d = (struct builtin_description *) bdesc_spe_evsel;
7656 for (i = 0; i < ARRAY_SIZE (bdesc_spe_evsel); ++i, d++)
7657 {
7658 tree type;
7659
7660 switch (insn_data[d->icode].operand[1].mode)
7661 {
7662 case V2SImode:
7663 type = v2si_ftype_4_v2si;
7664 break;
7665 case V2SFmode:
7666 type = v2sf_ftype_4_v2sf;
7667 break;
7668 default:
37409796 7669 gcc_unreachable ();
a3170dc6
AH		 7670 }
7671
7672 def_builtin (d->mask, d->name, type, d->code);
7673 }
7674}
7675
7676static void
863d938c 7677altivec_init_builtins (void)
a3170dc6
AH		 7678{
7679 struct builtin_description *d;
7680 struct builtin_description_predicates *dp;
7681 size_t i;
7682 tree pfloat_type_node = build_pointer_type (float_type_node);
7683 tree pint_type_node = build_pointer_type (integer_type_node);
7684 tree pshort_type_node = build_pointer_type (short_integer_type_node);
7685 tree pchar_type_node = build_pointer_type (char_type_node);
7686
7687 tree pvoid_type_node = build_pointer_type (void_type_node);
7688
0dbc3651
ZW		 7689 tree pcfloat_type_node = build_pointer_type (build_qualified_type (float_type_node, TYPE_QUAL_CONST));
7690 tree pcint_type_node = build_pointer_type (build_qualified_type (integer_type_node, TYPE_QUAL_CONST));
7691 tree pcshort_type_node = build_pointer_type (build_qualified_type (short_integer_type_node, TYPE_QUAL_CONST));
7692 tree pcchar_type_node = build_pointer_type (build_qualified_type (char_type_node, TYPE_QUAL_CONST));
7693
7694 tree pcvoid_type_node = build_pointer_type (build_qualified_type (void_type_node, TYPE_QUAL_CONST));
7695
58646b77
PB		 7696 tree int_ftype_opaque
7697 = build_function_type_list (integer_type_node,
7698 opaque_V4SI_type_node, NULL_TREE);
7699
7700 tree opaque_ftype_opaque_int
7701 = build_function_type_list (opaque_V4SI_type_node,
7702 opaque_V4SI_type_node, integer_type_node, NULL_TREE);
7703 tree opaque_ftype_opaque_opaque_int
7704 = build_function_type_list (opaque_V4SI_type_node,
7705 opaque_V4SI_type_node, opaque_V4SI_type_node,
7706 integer_type_node, NULL_TREE);
7707 tree int_ftype_int_opaque_opaque
7708 = build_function_type_list (integer_type_node,
7709 integer_type_node, opaque_V4SI_type_node,
7710 opaque_V4SI_type_node, NULL_TREE);
a3170dc6
AH		 7711 tree int_ftype_int_v4si_v4si
7712 = build_function_type_list (integer_type_node,
7713 integer_type_node, V4SI_type_node,
7714 V4SI_type_node, NULL_TREE);
0dbc3651
ZW		 7715 tree v4sf_ftype_pcfloat
7716 = build_function_type_list (V4SF_type_node, pcfloat_type_node, NULL_TREE);
a3170dc6 7717 tree void_ftype_pfloat_v4sf
b4de2f7d 7718 = build_function_type_list (void_type_node,
a3170dc6 7719 pfloat_type_node, V4SF_type_node, NULL_TREE);
0dbc3651
ZW		 7720 tree v4si_ftype_pcint
7721 = build_function_type_list (V4SI_type_node, pcint_type_node, NULL_TREE);
7722 tree void_ftype_pint_v4si
b4de2f7d
AH		 7723 = build_function_type_list (void_type_node,
7724 pint_type_node, V4SI_type_node, NULL_TREE);
0dbc3651
ZW		 7725 tree v8hi_ftype_pcshort
7726 = build_function_type_list (V8HI_type_node, pcshort_type_node, NULL_TREE);
f18c054f 7727 tree void_ftype_pshort_v8hi
b4de2f7d
AH		 7728 = build_function_type_list (void_type_node,
7729 pshort_type_node, V8HI_type_node, NULL_TREE);
0dbc3651
ZW		 7730 tree v16qi_ftype_pcchar
7731 = build_function_type_list (V16QI_type_node, pcchar_type_node, NULL_TREE);
f18c054f 7732 tree void_ftype_pchar_v16qi
b4de2f7d
AH		 7733 = build_function_type_list (void_type_node,
7734 pchar_type_node, V16QI_type_node, NULL_TREE);
95385cbb 7735 tree void_ftype_v4si
b4de2f7d 7736 = build_function_type_list (void_type_node, V4SI_type_node, NULL_TREE);
a3170dc6
AH		 7737 tree v8hi_ftype_void
7738 = build_function_type (V8HI_type_node, void_list_node);
7739 tree void_ftype_void
7740 = build_function_type (void_type_node, void_list_node);
e34b6648
JJ		 7741 tree void_ftype_int
7742 = build_function_type_list (void_type_node, integer_type_node, NULL_TREE);
0dbc3651 7743
58646b77
PB		 7744 tree opaque_ftype_long_pcvoid
7745 = build_function_type_list (opaque_V4SI_type_node,
7746 long_integer_type_node, pcvoid_type_node, NULL_TREE);
b4a62fa0 7747 tree v16qi_ftype_long_pcvoid
a3170dc6 7748 = build_function_type_list (V16QI_type_node,
b4a62fa0
SB		 7749 long_integer_type_node, pcvoid_type_node, NULL_TREE);
7750 tree v8hi_ftype_long_pcvoid
a3170dc6 7751 = build_function_type_list (V8HI_type_node,
b4a62fa0
SB		 7752 long_integer_type_node, pcvoid_type_node, NULL_TREE);
7753 tree v4si_ftype_long_pcvoid
a3170dc6 7754 = build_function_type_list (V4SI_type_node,
b4a62fa0 7755 long_integer_type_node, pcvoid_type_node, NULL_TREE);
0dbc3651 7756
58646b77
PB		 7757 tree void_ftype_opaque_long_pvoid
7758 = build_function_type_list (void_type_node,
7759 opaque_V4SI_type_node, long_integer_type_node,
7760 pvoid_type_node, NULL_TREE);
b4a62fa0 7761 tree void_ftype_v4si_long_pvoid
b4de2f7d 7762 = build_function_type_list (void_type_node,
b4a62fa0 7763 V4SI_type_node, long_integer_type_node,
b4de2f7d 7764 pvoid_type_node, NULL_TREE);
b4a62fa0 7765 tree void_ftype_v16qi_long_pvoid
b4de2f7d 7766 = build_function_type_list (void_type_node,
b4a62fa0 7767 V16QI_type_node, long_integer_type_node,
b4de2f7d 7768 pvoid_type_node, NULL_TREE);
b4a62fa0 7769 tree void_ftype_v8hi_long_pvoid
b4de2f7d 7770 = build_function_type_list (void_type_node,
b4a62fa0 7771 V8HI_type_node, long_integer_type_node,
b4de2f7d 7772 pvoid_type_node, NULL_TREE);
a3170dc6
AH		 7773 tree int_ftype_int_v8hi_v8hi
7774 = build_function_type_list (integer_type_node,
7775 integer_type_node, V8HI_type_node,
7776 V8HI_type_node, NULL_TREE);
7777 tree int_ftype_int_v16qi_v16qi
7778 = build_function_type_list (integer_type_node,
7779 integer_type_node, V16QI_type_node,
7780 V16QI_type_node, NULL_TREE);
7781 tree int_ftype_int_v4sf_v4sf
7782 = build_function_type_list (integer_type_node,
7783 integer_type_node, V4SF_type_node,
7784 V4SF_type_node, NULL_TREE);
7785 tree v4si_ftype_v4si
7786 = build_function_type_list (V4SI_type_node, V4SI_type_node, NULL_TREE);
7787 tree v8hi_ftype_v8hi
7788 = build_function_type_list (V8HI_type_node, V8HI_type_node, NULL_TREE);
7789 tree v16qi_ftype_v16qi
7790 = build_function_type_list (V16QI_type_node, V16QI_type_node, NULL_TREE);
7791 tree v4sf_ftype_v4sf
7792 = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE);
8bb418a3 7793 tree void_ftype_pcvoid_int_int
a3170dc6 7794 = build_function_type_list (void_type_node,
0dbc3651 7795 pcvoid_type_node, integer_type_node,
8bb418a3 7796 integer_type_node, NULL_TREE);
8bb418a3 7797
0dbc3651
ZW		 7798 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_4sf", v4sf_ftype_pcfloat,
7799 ALTIVEC_BUILTIN_LD_INTERNAL_4sf);
7800 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_4sf", void_ftype_pfloat_v4sf,
7801 ALTIVEC_BUILTIN_ST_INTERNAL_4sf);
7802 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_4si", v4si_ftype_pcint,
7803 ALTIVEC_BUILTIN_LD_INTERNAL_4si);
7804 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_4si", void_ftype_pint_v4si,
7805 ALTIVEC_BUILTIN_ST_INTERNAL_4si);
7806 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_8hi", v8hi_ftype_pcshort,
7807 ALTIVEC_BUILTIN_LD_INTERNAL_8hi);
7808 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_8hi", void_ftype_pshort_v8hi,
7809 ALTIVEC_BUILTIN_ST_INTERNAL_8hi);
7810 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_16qi", v16qi_ftype_pcchar,
7811 ALTIVEC_BUILTIN_LD_INTERNAL_16qi);
7812 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_16qi", void_ftype_pchar_v16qi,
7813 ALTIVEC_BUILTIN_ST_INTERNAL_16qi);
a3170dc6
AH		 7814 def_builtin (MASK_ALTIVEC, "__builtin_altivec_mtvscr", void_ftype_v4si, ALTIVEC_BUILTIN_MTVSCR);
7815 def_builtin (MASK_ALTIVEC, "__builtin_altivec_mfvscr", v8hi_ftype_void, ALTIVEC_BUILTIN_MFVSCR);
7816 def_builtin (MASK_ALTIVEC, "__builtin_altivec_dssall", void_ftype_void, ALTIVEC_BUILTIN_DSSALL);
e34b6648 7817 def_builtin (MASK_ALTIVEC, "__builtin_altivec_dss", void_ftype_int, ALTIVEC_BUILTIN_DSS);
b4a62fa0
SB		 7818 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvsl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSL);
7819 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvsr", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSR);
7820 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvebx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEBX);
7821 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvehx", v8hi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEHX);
7822 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvewx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEWX);
7823 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvxl", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVXL);
7824 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVX);
7825 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVX);
7826 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvewx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVEWX);
7827 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvxl", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVXL);
7828 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvebx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVEBX);
7829 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvehx", void_ftype_v8hi_long_pvoid, ALTIVEC_BUILTIN_STVEHX);
58646b77
PB		 7830 def_builtin (MASK_ALTIVEC, "__builtin_vec_ld", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LD);
7831 def_builtin (MASK_ALTIVEC, "__builtin_vec_lde", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LDE);
7832 def_builtin (MASK_ALTIVEC, "__builtin_vec_ldl", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LDL);
7833 def_builtin (MASK_ALTIVEC, "__builtin_vec_lvsl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVSL);
7834 def_builtin (MASK_ALTIVEC, "__builtin_vec_lvsr", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVSR);
7835 def_builtin (MASK_ALTIVEC, "__builtin_vec_lvebx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEBX);
7836 def_builtin (MASK_ALTIVEC, "__builtin_vec_lvehx", v8hi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEHX);
7837 def_builtin (MASK_ALTIVEC, "__builtin_vec_lvewx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEWX);
7838 def_builtin (MASK_ALTIVEC, "__builtin_vec_st", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_ST);
7839 def_builtin (MASK_ALTIVEC, "__builtin_vec_ste", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STE);
7840 def_builtin (MASK_ALTIVEC, "__builtin_vec_stl", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STL);
7841 def_builtin (MASK_ALTIVEC, "__builtin_vec_stvewx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEWX);
7842 def_builtin (MASK_ALTIVEC, "__builtin_vec_stvebx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEBX);
7843 def_builtin (MASK_ALTIVEC, "__builtin_vec_stvehx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEHX);
7844
7845 def_builtin (MASK_ALTIVEC, "__builtin_vec_step", int_ftype_opaque, ALTIVEC_BUILTIN_VEC_STEP);
7846
7847 def_builtin (MASK_ALTIVEC, "__builtin_vec_sld", opaque_ftype_opaque_opaque_int, ALTIVEC_BUILTIN_VEC_SLD);
7848 def_builtin (MASK_ALTIVEC, "__builtin_vec_splat", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_SPLAT);
7849 def_builtin (MASK_ALTIVEC, "__builtin_vec_vspltw", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTW);
7850 def_builtin (MASK_ALTIVEC, "__builtin_vec_vsplth", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTH);
7851 def_builtin (MASK_ALTIVEC, "__builtin_vec_vspltb", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTB);
7852 def_builtin (MASK_ALTIVEC, "__builtin_vec_ctf", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTF);
7853 def_builtin (MASK_ALTIVEC, "__builtin_vec_vcfsx", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VCFSX);
7854 def_builtin (MASK_ALTIVEC, "__builtin_vec_vcfux", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VCFUX);
7855 def_builtin (MASK_ALTIVEC, "__builtin_vec_cts", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTS);
7856 def_builtin (MASK_ALTIVEC, "__builtin_vec_ctu", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTU);
8bb418a3 7857
a3170dc6
AH		 7858 /* Add the DST variants. */
7859 d = (struct builtin_description *) bdesc_dst;
7860 for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++)
8bb418a3 7861 def_builtin (d->mask, d->name, void_ftype_pcvoid_int_int, d->code);
a3170dc6
AH		 7862
7863 /* Initialize the predicates. */
7864 dp = (struct builtin_description_predicates *) bdesc_altivec_preds;
7865 for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, dp++)
7866 {
7867 enum machine_mode mode1;
7868 tree type;
58646b77
PB		 7869 bool is_overloaded = dp->code >= ALTIVEC_BUILTIN_OVERLOADED_FIRST
7870 && dp->code <= ALTIVEC_BUILTIN_OVERLOADED_LAST;
a3170dc6 7871
58646b77
PB		 7872 if (is_overloaded)
7873 mode1 = VOIDmode;
7874 else
7875 mode1 = insn_data[dp->icode].operand[1].mode;
a3170dc6
AH		 7876
7877 switch (mode1)
7878 {
58646b77
PB		 7879 case VOIDmode:
7880 type = int_ftype_int_opaque_opaque;
7881 break;
a3170dc6
AH		 7882 case V4SImode:
7883 type = int_ftype_int_v4si_v4si;
7884 break;
7885 case V8HImode:
7886 type = int_ftype_int_v8hi_v8hi;
7887 break;
7888 case V16QImode:
7889 type = int_ftype_int_v16qi_v16qi;
7890 break;
7891 case V4SFmode:
7892 type = int_ftype_int_v4sf_v4sf;
7893 break;
7894 default:
37409796 7895 gcc_unreachable ();
a3170dc6 7896 }
f676971a 7897
a3170dc6
AH		 7898 def_builtin (dp->mask, dp->name, type, dp->code);
7899 }
7900
7901 /* Initialize the abs* operators. */
7902 d = (struct builtin_description *) bdesc_abs;
7903 for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++)
7904 {
7905 enum machine_mode mode0;
7906 tree type;
7907
7908 mode0 = insn_data[d->icode].operand[0].mode;
7909
7910 switch (mode0)
7911 {
7912 case V4SImode:
7913 type = v4si_ftype_v4si;
7914 break;
7915 case V8HImode:
7916 type = v8hi_ftype_v8hi;
7917 break;
7918 case V16QImode:
7919 type = v16qi_ftype_v16qi;
7920 break;
7921 case V4SFmode:
7922 type = v4sf_ftype_v4sf;
7923 break;
7924 default:
37409796 7925 gcc_unreachable ();
a3170dc6 7926 }
f676971a 7927
a3170dc6
AH		 7928 def_builtin (d->mask, d->name, type, d->code);
7929 }
7ccf35ed 7930
13c62176
DN		 7931 if (TARGET_ALTIVEC)
7932 {
7933 tree decl;
7934
7935 /* Initialize target builtin that implements
7936 targetm.vectorize.builtin_mask_for_load. */
7937
7938 decl = lang_hooks.builtin_function ("__builtin_altivec_mask_for_load",
8bb46326
DN		 7939 v16qi_ftype_long_pcvoid,
7940 ALTIVEC_BUILTIN_MASK_FOR_LOAD,
7941 BUILT_IN_MD, NULL,
7942 tree_cons (get_identifier ("const"),
7943 NULL_TREE, NULL_TREE));
13c62176
DN		 7944 /* Record the decl. Will be used by rs6000_builtin_mask_for_load. */
7945 altivec_builtin_mask_for_load = decl;
13c62176 7946 }
a3170dc6
AH		 7947}
7948
7949static void
863d938c 7950rs6000_common_init_builtins (void)
a3170dc6
AH		 7951{
7952 struct builtin_description *d;
7953 size_t i;
7954
7955 tree v4sf_ftype_v4sf_v4sf_v16qi
7956 = build_function_type_list (V4SF_type_node,
7957 V4SF_type_node, V4SF_type_node,
7958 V16QI_type_node, NULL_TREE);
7959 tree v4si_ftype_v4si_v4si_v16qi
7960 = build_function_type_list (V4SI_type_node,
7961 V4SI_type_node, V4SI_type_node,
7962 V16QI_type_node, NULL_TREE);
7963 tree v8hi_ftype_v8hi_v8hi_v16qi
7964 = build_function_type_list (V8HI_type_node,
7965 V8HI_type_node, V8HI_type_node,
7966 V16QI_type_node, NULL_TREE);
7967 tree v16qi_ftype_v16qi_v16qi_v16qi
7968 = build_function_type_list (V16QI_type_node,
7969 V16QI_type_node, V16QI_type_node,
7970 V16QI_type_node, NULL_TREE);
b9e4e5d1
ZL		 7971 tree v4si_ftype_int
7972 = build_function_type_list (V4SI_type_node, integer_type_node, NULL_TREE);
7973 tree v8hi_ftype_int
7974 = build_function_type_list (V8HI_type_node, integer_type_node, NULL_TREE);
7975 tree v16qi_ftype_int
7976 = build_function_type_list (V16QI_type_node, integer_type_node, NULL_TREE);
a3170dc6
AH		 7977 tree v8hi_ftype_v16qi
7978 = build_function_type_list (V8HI_type_node, V16QI_type_node, NULL_TREE);
7979 tree v4sf_ftype_v4sf
7980 = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE);
7981
7982 tree v2si_ftype_v2si_v2si
2abe3e28
AH		 7983 = build_function_type_list (opaque_V2SI_type_node,
7984 opaque_V2SI_type_node,
7985 opaque_V2SI_type_node, NULL_TREE);
a3170dc6
AH		 7986
7987 tree v2sf_ftype_v2sf_v2sf
2abe3e28
AH		 7988 = build_function_type_list (opaque_V2SF_type_node,
7989 opaque_V2SF_type_node,
7990 opaque_V2SF_type_node, NULL_TREE);
a3170dc6
AH		 7991
7992 tree v2si_ftype_int_int
2abe3e28 7993 = build_function_type_list (opaque_V2SI_type_node,
a3170dc6
AH		 7994 integer_type_node, integer_type_node,
7995 NULL_TREE);
7996
58646b77
PB		 7997 tree opaque_ftype_opaque
7998 = build_function_type_list (opaque_V4SI_type_node,
7999 opaque_V4SI_type_node, NULL_TREE);
8000
a3170dc6 8001 tree v2si_ftype_v2si
2abe3e28
AH		 8002 = build_function_type_list (opaque_V2SI_type_node,
8003 opaque_V2SI_type_node, NULL_TREE);
a3170dc6
AH		 8004
8005 tree v2sf_ftype_v2sf
2abe3e28
AH		 8006 = build_function_type_list (opaque_V2SF_type_node,
8007 opaque_V2SF_type_node, NULL_TREE);
f676971a 8008
a3170dc6 8009 tree v2sf_ftype_v2si
2abe3e28
AH		 8010 = build_function_type_list (opaque_V2SF_type_node,
8011 opaque_V2SI_type_node, NULL_TREE);
a3170dc6
AH		 8012
8013 tree v2si_ftype_v2sf
2abe3e28
AH		 8014 = build_function_type_list (opaque_V2SI_type_node,
8015 opaque_V2SF_type_node, NULL_TREE);
a3170dc6
AH		 8016
8017 tree v2si_ftype_v2si_char
2abe3e28
AH		 8018 = build_function_type_list (opaque_V2SI_type_node,
8019 opaque_V2SI_type_node,
8020 char_type_node, NULL_TREE);
a3170dc6
AH		 8021
8022 tree v2si_ftype_int_char
2abe3e28 8023 = build_function_type_list (opaque_V2SI_type_node,
a3170dc6
AH		 8024 integer_type_node, char_type_node, NULL_TREE);
8025
8026 tree v2si_ftype_char
2abe3e28
AH		 8027 = build_function_type_list (opaque_V2SI_type_node,
8028 char_type_node, NULL_TREE);
a3170dc6
AH		 8029
8030 tree int_ftype_int_int
8031 = build_function_type_list (integer_type_node,
8032 integer_type_node, integer_type_node,
8033 NULL_TREE);
95385cbb 8034
58646b77
PB		 8035 tree opaque_ftype_opaque_opaque
8036 = build_function_type_list (opaque_V4SI_type_node,
8037 opaque_V4SI_type_node, opaque_V4SI_type_node, NULL_TREE);
0ac081f6 8038 tree v4si_ftype_v4si_v4si
b4de2f7d
AH		 8039 = build_function_type_list (V4SI_type_node,
8040 V4SI_type_node, V4SI_type_node, NULL_TREE);
b9e4e5d1 8041 tree v4sf_ftype_v4si_int
b4de2f7d 8042 = build_function_type_list (V4SF_type_node,
b9e4e5d1
ZL		 8043 V4SI_type_node, integer_type_node, NULL_TREE);
8044 tree v4si_ftype_v4sf_int
b4de2f7d 8045 = build_function_type_list (V4SI_type_node,
b9e4e5d1
ZL		 8046 V4SF_type_node, integer_type_node, NULL_TREE);
8047 tree v4si_ftype_v4si_int
b4de2f7d 8048 = build_function_type_list (V4SI_type_node,
b9e4e5d1
ZL		 8049 V4SI_type_node, integer_type_node, NULL_TREE);
8050 tree v8hi_ftype_v8hi_int
b4de2f7d 8051 = build_function_type_list (V8HI_type_node,
b9e4e5d1
ZL		 8052 V8HI_type_node, integer_type_node, NULL_TREE);
8053 tree v16qi_ftype_v16qi_int
b4de2f7d 8054 = build_function_type_list (V16QI_type_node,
b9e4e5d1
ZL		 8055 V16QI_type_node, integer_type_node, NULL_TREE);
8056 tree v16qi_ftype_v16qi_v16qi_int
b4de2f7d
AH		 8057 = build_function_type_list (V16QI_type_node,
8058 V16QI_type_node, V16QI_type_node,
b9e4e5d1
ZL		 8059 integer_type_node, NULL_TREE);
8060 tree v8hi_ftype_v8hi_v8hi_int
b4de2f7d
AH		 8061 = build_function_type_list (V8HI_type_node,
8062 V8HI_type_node, V8HI_type_node,
b9e4e5d1
ZL		 8063 integer_type_node, NULL_TREE);
8064 tree v4si_ftype_v4si_v4si_int
b4de2f7d
AH		 8065 = build_function_type_list (V4SI_type_node,
8066 V4SI_type_node, V4SI_type_node,
b9e4e5d1
ZL		 8067 integer_type_node, NULL_TREE);
8068 tree v4sf_ftype_v4sf_v4sf_int
b4de2f7d
AH		 8069 = build_function_type_list (V4SF_type_node,
8070 V4SF_type_node, V4SF_type_node,
b9e4e5d1 8071 integer_type_node, NULL_TREE);
0ac081f6 8072 tree v4sf_ftype_v4sf_v4sf
b4de2f7d
AH		 8073 = build_function_type_list (V4SF_type_node,
8074 V4SF_type_node, V4SF_type_node, NULL_TREE);
58646b77
PB		 8075 tree opaque_ftype_opaque_opaque_opaque
8076 = build_function_type_list (opaque_V4SI_type_node,
8077 opaque_V4SI_type_node, opaque_V4SI_type_node,
8078 opaque_V4SI_type_node, NULL_TREE);
617e0e1d 8079 tree v4sf_ftype_v4sf_v4sf_v4si
b4de2f7d
AH		 8080 = build_function_type_list (V4SF_type_node,
8081 V4SF_type_node, V4SF_type_node,
8082 V4SI_type_node, NULL_TREE);
2212663f 8083 tree v4sf_ftype_v4sf_v4sf_v4sf
b4de2f7d
AH		 8084 = build_function_type_list (V4SF_type_node,
8085 V4SF_type_node, V4SF_type_node,
8086 V4SF_type_node, NULL_TREE);
f676971a 8087 tree v4si_ftype_v4si_v4si_v4si
b4de2f7d
AH		 8088 = build_function_type_list (V4SI_type_node,
8089 V4SI_type_node, V4SI_type_node,
8090 V4SI_type_node, NULL_TREE);
0ac081f6 8091 tree v8hi_ftype_v8hi_v8hi
b4de2f7d
AH		 8092 = build_function_type_list (V8HI_type_node,
8093 V8HI_type_node, V8HI_type_node, NULL_TREE);
2212663f 8094 tree v8hi_ftype_v8hi_v8hi_v8hi
b4de2f7d
AH		 8095 = build_function_type_list (V8HI_type_node,
8096 V8HI_type_node, V8HI_type_node,
8097 V8HI_type_node, NULL_TREE);
c4ad648e 8098 tree v4si_ftype_v8hi_v8hi_v4si
b4de2f7d
AH		 8099 = build_function_type_list (V4SI_type_node,
8100 V8HI_type_node, V8HI_type_node,
8101 V4SI_type_node, NULL_TREE);
c4ad648e 8102 tree v4si_ftype_v16qi_v16qi_v4si
b4de2f7d
AH		 8103 = build_function_type_list (V4SI_type_node,
8104 V16QI_type_node, V16QI_type_node,
8105 V4SI_type_node, NULL_TREE);
0ac081f6 8106 tree v16qi_ftype_v16qi_v16qi
b4de2f7d
AH		 8107 = build_function_type_list (V16QI_type_node,
8108 V16QI_type_node, V16QI_type_node, NULL_TREE);
0ac081f6 8109 tree v4si_ftype_v4sf_v4sf
b4de2f7d
AH		 8110 = build_function_type_list (V4SI_type_node,
8111 V4SF_type_node, V4SF_type_node, NULL_TREE);
0ac081f6 8112 tree v8hi_ftype_v16qi_v16qi
b4de2f7d
AH		 8113 = build_function_type_list (V8HI_type_node,
8114 V16QI_type_node, V16QI_type_node, NULL_TREE);
0ac081f6 8115 tree v4si_ftype_v8hi_v8hi
b4de2f7d
AH		 8116 = build_function_type_list (V4SI_type_node,
8117 V8HI_type_node, V8HI_type_node, NULL_TREE);
0ac081f6 8118 tree v8hi_ftype_v4si_v4si
b4de2f7d
AH		 8119 = build_function_type_list (V8HI_type_node,
8120 V4SI_type_node, V4SI_type_node, NULL_TREE);
0ac081f6 8121 tree v16qi_ftype_v8hi_v8hi
b4de2f7d
AH		 8122 = build_function_type_list (V16QI_type_node,
8123 V8HI_type_node, V8HI_type_node, NULL_TREE);
0ac081f6 8124 tree v4si_ftype_v16qi_v4si
b4de2f7d
AH		 8125 = build_function_type_list (V4SI_type_node,
8126 V16QI_type_node, V4SI_type_node, NULL_TREE);
fa066a23 8127 tree v4si_ftype_v16qi_v16qi
b4de2f7d
AH		 8128 = build_function_type_list (V4SI_type_node,
8129 V16QI_type_node, V16QI_type_node, NULL_TREE);
0ac081f6 8130 tree v4si_ftype_v8hi_v4si
b4de2f7d
AH		 8131 = build_function_type_list (V4SI_type_node,
8132 V8HI_type_node, V4SI_type_node, NULL_TREE);
a3170dc6
AH		 8133 tree v4si_ftype_v8hi
8134 = build_function_type_list (V4SI_type_node, V8HI_type_node, NULL_TREE);
8135 tree int_ftype_v4si_v4si
8136 = build_function_type_list (integer_type_node,
8137 V4SI_type_node, V4SI_type_node, NULL_TREE);
8138 tree int_ftype_v4sf_v4sf
8139 = build_function_type_list (integer_type_node,
8140 V4SF_type_node, V4SF_type_node, NULL_TREE);
8141 tree int_ftype_v16qi_v16qi
8142 = build_function_type_list (integer_type_node,
8143 V16QI_type_node, V16QI_type_node, NULL_TREE);
0ac081f6 8144 tree int_ftype_v8hi_v8hi
b4de2f7d
AH		 8145 = build_function_type_list (integer_type_node,
8146 V8HI_type_node, V8HI_type_node, NULL_TREE);
0ac081f6 8147
6f317ef3 8148 /* Add the simple ternary operators. */
2212663f 8149 d = (struct builtin_description *) bdesc_3arg;
ca7558fc 8150 for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++)
2212663f 8151 {
2212663f
DB		 8152 enum machine_mode mode0, mode1, mode2, mode3;
8153 tree type;
58646b77
PB		 8154 bool is_overloaded = d->code >= ALTIVEC_BUILTIN_OVERLOADED_FIRST
8155 && d->code <= ALTIVEC_BUILTIN_OVERLOADED_LAST;
2212663f 8156
58646b77
PB		 8157 if (is_overloaded)
8158 {
8159 mode0 = VOIDmode;
8160 mode1 = VOIDmode;
8161 mode2 = VOIDmode;
8162 mode3 = VOIDmode;
8163 }
8164 else
8165 {
8166 if (d->name == 0 || d->icode == CODE_FOR_nothing)
8167 continue;
f676971a 8168
58646b77
PB		 8169 mode0 = insn_data[d->icode].operand[0].mode;
8170 mode1 = insn_data[d->icode].operand[1].mode;
8171 mode2 = insn_data[d->icode].operand[2].mode;
8172 mode3 = insn_data[d->icode].operand[3].mode;
8173 }
8174
2212663f
DB		 8175 /* When all four are of the same mode. */
8176 if (mode0 == mode1 && mode1 == mode2 && mode2 == mode3)
8177 {
8178 switch (mode0)
8179 {
58646b77
PB		 8180 case VOIDmode:
8181 type = opaque_ftype_opaque_opaque_opaque;
8182 break;
617e0e1d
DB		 8183 case V4SImode:
8184 type = v4si_ftype_v4si_v4si_v4si;
8185 break;
2212663f
DB		 8186 case V4SFmode:
8187 type = v4sf_ftype_v4sf_v4sf_v4sf;
8188 break;
8189 case V8HImode:
8190 type = v8hi_ftype_v8hi_v8hi_v8hi;
f676971a 8191 break;
2212663f
DB		 8192 case V16QImode:
8193 type = v16qi_ftype_v16qi_v16qi_v16qi;
f676971a 8194 break;
2212663f 8195 default:
37409796 8196 gcc_unreachable ();
2212663f
DB		 8197 }
8198 }
8199 else if (mode0 == mode1 && mode1 == mode2 && mode3 == V16QImode)
c4ad648e 8200 {
2212663f
DB		 8201 switch (mode0)
8202 {
8203 case V4SImode:
8204 type = v4si_ftype_v4si_v4si_v16qi;
8205 break;
8206 case V4SFmode:
8207 type = v4sf_ftype_v4sf_v4sf_v16qi;
8208 break;
8209 case V8HImode:
8210 type = v8hi_ftype_v8hi_v8hi_v16qi;
f676971a 8211 break;
2212663f
DB		 8212 case V16QImode:
8213 type = v16qi_ftype_v16qi_v16qi_v16qi;
f676971a 8214 break;
2212663f 8215 default:
37409796 8216 gcc_unreachable ();
2212663f
DB		 8217 }
8218 }
f676971a 8219 else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V16QImode
2212663f 8220 && mode3 == V4SImode)
24408032 8221 type = v4si_ftype_v16qi_v16qi_v4si;
f676971a 8222 else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V8HImode
2212663f 8223 && mode3 == V4SImode)
24408032 8224 type = v4si_ftype_v8hi_v8hi_v4si;
f676971a 8225 else if (mode0 == V4SFmode && mode1 == V4SFmode && mode2 == V4SFmode
617e0e1d 8226 && mode3 == V4SImode)
24408032
AH		 8227 type = v4sf_ftype_v4sf_v4sf_v4si;
8228
8229 /* vchar, vchar, vchar, 4 bit literal. */
8230 else if (mode0 == V16QImode && mode1 == mode0 && mode2 == mode0
8231 && mode3 == QImode)
b9e4e5d1 8232 type = v16qi_ftype_v16qi_v16qi_int;
24408032
AH		 8233
8234 /* vshort, vshort, vshort, 4 bit literal. */
8235 else if (mode0 == V8HImode && mode1 == mode0 && mode2 == mode0
8236 && mode3 == QImode)
b9e4e5d1 8237 type = v8hi_ftype_v8hi_v8hi_int;
24408032
AH		 8238
8239 /* vint, vint, vint, 4 bit literal. */
8240 else if (mode0 == V4SImode && mode1 == mode0 && mode2 == mode0
8241 && mode3 == QImode)
b9e4e5d1 8242 type = v4si_ftype_v4si_v4si_int;
24408032
AH		 8243
8244 /* vfloat, vfloat, vfloat, 4 bit literal. */
8245 else if (mode0 == V4SFmode && mode1 == mode0 && mode2 == mode0
8246 && mode3 == QImode)
b9e4e5d1 8247 type = v4sf_ftype_v4sf_v4sf_int;
24408032 8248
2212663f 8249 else
37409796 8250 gcc_unreachable ();
2212663f
DB		 8251
8252 def_builtin (d->mask, d->name, type, d->code);
8253 }
8254
0ac081f6 8255 /* Add the simple binary operators. */
00b960c7 8256 d = (struct builtin_description *) bdesc_2arg;
ca7558fc 8257 for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
0ac081f6
AH		 8258 {
8259 enum machine_mode mode0, mode1, mode2;
8260 tree type;
58646b77
PB		 8261 bool is_overloaded = d->code >= ALTIVEC_BUILTIN_OVERLOADED_FIRST
8262 && d->code <= ALTIVEC_BUILTIN_OVERLOADED_LAST;
0ac081f6 8263
58646b77
PB		 8264 if (is_overloaded)
8265 {
8266 mode0 = VOIDmode;
8267 mode1 = VOIDmode;
8268 mode2 = VOIDmode;
8269 }
8270 else
8271 {
8272 if (d->name == 0 || d->icode == CODE_FOR_nothing)
8273 continue;
f676971a 8274
58646b77
PB		 8275 mode0 = insn_data[d->icode].operand[0].mode;
8276 mode1 = insn_data[d->icode].operand[1].mode;
8277 mode2 = insn_data[d->icode].operand[2].mode;
8278 }
0ac081f6
AH		 8279
8280 /* When all three operands are of the same mode. */
8281 if (mode0 == mode1 && mode1 == mode2)
8282 {
8283 switch (mode0)
8284 {
58646b77
PB		 8285 case VOIDmode:
8286 type = opaque_ftype_opaque_opaque;
8287 break;
0ac081f6
AH		 8288 case V4SFmode:
8289 type = v4sf_ftype_v4sf_v4sf;
8290 break;
8291 case V4SImode:
8292 type = v4si_ftype_v4si_v4si;
8293 break;
8294 case V16QImode:
8295 type = v16qi_ftype_v16qi_v16qi;
8296 break;
8297 case V8HImode:
8298 type = v8hi_ftype_v8hi_v8hi;
8299 break;
a3170dc6
AH		 8300 case V2SImode:
8301 type = v2si_ftype_v2si_v2si;
8302 break;
8303 case V2SFmode:
8304 type = v2sf_ftype_v2sf_v2sf;
8305 break;
8306 case SImode:
8307 type = int_ftype_int_int;
8308 break;
0ac081f6 8309 default:
37409796 8310 gcc_unreachable ();
0ac081f6
AH		 8311 }
8312 }
8313
8314 /* A few other combos we really don't want to do manually. */
8315
8316 /* vint, vfloat, vfloat. */
8317 else if (mode0 == V4SImode && mode1 == V4SFmode && mode2 == V4SFmode)
8318 type = v4si_ftype_v4sf_v4sf;
8319
8320 /* vshort, vchar, vchar. */
8321 else if (mode0 == V8HImode && mode1 == V16QImode && mode2 == V16QImode)
8322 type = v8hi_ftype_v16qi_v16qi;
8323
8324 /* vint, vshort, vshort. */
8325 else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V8HImode)
8326 type = v4si_ftype_v8hi_v8hi;
8327
8328 /* vshort, vint, vint. */
8329 else if (mode0 == V8HImode && mode1 == V4SImode && mode2 == V4SImode)
8330 type = v8hi_ftype_v4si_v4si;
8331
8332 /* vchar, vshort, vshort. */
8333 else if (mode0 == V16QImode && mode1 == V8HImode && mode2 == V8HImode)
8334 type = v16qi_ftype_v8hi_v8hi;
8335
8336 /* vint, vchar, vint. */
8337 else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V4SImode)
8338 type = v4si_ftype_v16qi_v4si;
8339
fa066a23
AH		 8340 /* vint, vchar, vchar. */
8341 else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V16QImode)
8342 type = v4si_ftype_v16qi_v16qi;
8343
0ac081f6
AH		 8344 /* vint, vshort, vint. */
8345 else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V4SImode)
8346 type = v4si_ftype_v8hi_v4si;
f676971a 8347
2212663f
DB		 8348 /* vint, vint, 5 bit literal. */
8349 else if (mode0 == V4SImode && mode1 == V4SImode && mode2 == QImode)
b9e4e5d1 8350 type = v4si_ftype_v4si_int;
f676971a 8351
2212663f
DB		 8352 /* vshort, vshort, 5 bit literal. */
8353 else if (mode0 == V8HImode && mode1 == V8HImode && mode2 == QImode)
b9e4e5d1 8354 type = v8hi_ftype_v8hi_int;
f676971a 8355
2212663f
DB		 8356 /* vchar, vchar, 5 bit literal. */
8357 else if (mode0 == V16QImode && mode1 == V16QImode && mode2 == QImode)
b9e4e5d1 8358 type = v16qi_ftype_v16qi_int;
0ac081f6 8359
617e0e1d
DB		 8360 /* vfloat, vint, 5 bit literal. */
8361 else if (mode0 == V4SFmode && mode1 == V4SImode && mode2 == QImode)
b9e4e5d1 8362 type = v4sf_ftype_v4si_int;
f676971a 8363
617e0e1d
DB		 8364 /* vint, vfloat, 5 bit literal. */
8365 else if (mode0 == V4SImode && mode1 == V4SFmode && mode2 == QImode)
b9e4e5d1 8366 type = v4si_ftype_v4sf_int;
617e0e1d 8367
a3170dc6
AH		 8368 else if (mode0 == V2SImode && mode1 == SImode && mode2 == SImode)
8369 type = v2si_ftype_int_int;
8370
8371 else if (mode0 == V2SImode && mode1 == V2SImode && mode2 == QImode)
8372 type = v2si_ftype_v2si_char;
8373
8374 else if (mode0 == V2SImode && mode1 == SImode && mode2 == QImode)
8375 type = v2si_ftype_int_char;
8376
37409796 8377 else
0ac081f6 8378 {
37409796
NS		 8379 /* int, x, x. */
8380 gcc_assert (mode0 == SImode);
0ac081f6
AH		 8381 switch (mode1)
8382 {
8383 case V4SImode:
8384 type = int_ftype_v4si_v4si;
8385 break;
8386 case V4SFmode:
8387 type = int_ftype_v4sf_v4sf;
8388 break;
8389 case V16QImode:
8390 type = int_ftype_v16qi_v16qi;
8391 break;
8392 case V8HImode:
8393 type = int_ftype_v8hi_v8hi;
8394 break;
8395 default:
37409796 8396 gcc_unreachable ();
0ac081f6
AH		 8397 }
8398 }
8399
2212663f
DB		 8400 def_builtin (d->mask, d->name, type, d->code);
8401 }
24408032 8402
2212663f
DB		 8403 /* Add the simple unary operators. */
8404 d = (struct builtin_description *) bdesc_1arg;
ca7558fc 8405 for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
2212663f
DB		 8406 {
8407 enum machine_mode mode0, mode1;
8408 tree type;
58646b77
PB		 8409 bool is_overloaded = d->code >= ALTIVEC_BUILTIN_OVERLOADED_FIRST
8410 && d->code <= ALTIVEC_BUILTIN_OVERLOADED_LAST;
8411
8412 if (is_overloaded)
8413 {
8414 mode0 = VOIDmode;
8415 mode1 = VOIDmode;
8416 }
8417 else
8418 {
8419 if (d->name == 0 || d->icode == CODE_FOR_nothing)
8420 continue;
8421
8422 mode0 = insn_data[d->icode].operand[0].mode;
8423 mode1 = insn_data[d->icode].operand[1].mode;
8424 }
2212663f
DB		 8425
8426 if (mode0 == V4SImode && mode1 == QImode)
c4ad648e 8427 type = v4si_ftype_int;
2212663f 8428 else if (mode0 == V8HImode && mode1 == QImode)
c4ad648e 8429 type = v8hi_ftype_int;
2212663f 8430 else if (mode0 == V16QImode && mode1 == QImode)
c4ad648e 8431 type = v16qi_ftype_int;
58646b77
PB		 8432 else if (mode0 == VOIDmode && mode1 == VOIDmode)
8433 type = opaque_ftype_opaque;
617e0e1d
DB		 8434 else if (mode0 == V4SFmode && mode1 == V4SFmode)
8435 type = v4sf_ftype_v4sf;
20e26713
AH		 8436 else if (mode0 == V8HImode && mode1 == V16QImode)
8437 type = v8hi_ftype_v16qi;
8438 else if (mode0 == V4SImode && mode1 == V8HImode)
8439 type = v4si_ftype_v8hi;
a3170dc6
AH		 8440 else if (mode0 == V2SImode && mode1 == V2SImode)
8441 type = v2si_ftype_v2si;
8442 else if (mode0 == V2SFmode && mode1 == V2SFmode)
8443 type = v2sf_ftype_v2sf;
8444 else if (mode0 == V2SFmode && mode1 == V2SImode)
8445 type = v2sf_ftype_v2si;
8446 else if (mode0 == V2SImode && mode1 == V2SFmode)
8447 type = v2si_ftype_v2sf;
8448 else if (mode0 == V2SImode && mode1 == QImode)
8449 type = v2si_ftype_char;
2212663f 8450 else
37409796 8451 gcc_unreachable ();
2212663f 8452
0ac081f6
AH		 8453 def_builtin (d->mask, d->name, type, d->code);
8454 }
8455}
8456
c15c90bb
ZW		 8457static void
8458rs6000_init_libfuncs (void)
8459{
8460 if (!TARGET_HARD_FLOAT)
8461 return;
8462
c9034561 8463 if (DEFAULT_ABI != ABI_V4)
c15c90bb 8464 {
c9034561 8465 if (TARGET_XCOFF && ! TARGET_POWER2 && ! TARGET_POWERPC)
c15c90bb 8466 {
c9034561 8467 /* AIX library routines for float->int conversion. */
85363ca0
ZW		 8468 set_conv_libfunc (sfix_optab, SImode, DFmode, "__itrunc");
8469 set_conv_libfunc (ufix_optab, SImode, DFmode, "__uitrunc");
4274207b
DE		 8470 set_conv_libfunc (sfix_optab, SImode, TFmode, "_qitrunc");
8471 set_conv_libfunc (ufix_optab, SImode, TFmode, "_quitrunc");
c15c90bb
ZW		 8472 }
8473
98c41d98
DE		 8474 /* AIX/Darwin/64-bit Linux quad floating point routines. */
8475 if (!TARGET_XL_COMPAT)
8476 {
8477 set_optab_libfunc (add_optab, TFmode, "__gcc_qadd");
8478 set_optab_libfunc (sub_optab, TFmode, "__gcc_qsub");
8479 set_optab_libfunc (smul_optab, TFmode, "__gcc_qmul");
8480 set_optab_libfunc (sdiv_optab, TFmode, "__gcc_qdiv");
8481 }
8482 else
8483 {
8484 set_optab_libfunc (add_optab, TFmode, "_xlqadd");
8485 set_optab_libfunc (sub_optab, TFmode, "_xlqsub");
8486 set_optab_libfunc (smul_optab, TFmode, "_xlqmul");
8487 set_optab_libfunc (sdiv_optab, TFmode, "_xlqdiv");
8488 }
c15c90bb 8489 }
c9034561 8490 else
c15c90bb 8491 {
c9034561 8492 /* 32-bit SVR4 quad floating point routines. */
c15c90bb
ZW		 8493
8494 set_optab_libfunc (add_optab, TFmode, "_q_add");
8495 set_optab_libfunc (sub_optab, TFmode, "_q_sub");
8496 set_optab_libfunc (neg_optab, TFmode, "_q_neg");
8497 set_optab_libfunc (smul_optab, TFmode, "_q_mul");
8498 set_optab_libfunc (sdiv_optab, TFmode, "_q_div");
8499 if (TARGET_PPC_GPOPT || TARGET_POWER2)
8500 set_optab_libfunc (sqrt_optab, TFmode, "_q_sqrt");
8501
c9034561
ZW		 8502 set_optab_libfunc (eq_optab, TFmode, "_q_feq");
8503 set_optab_libfunc (ne_optab, TFmode, "_q_fne");
8504 set_optab_libfunc (gt_optab, TFmode, "_q_fgt");
8505 set_optab_libfunc (ge_optab, TFmode, "_q_fge");
8506 set_optab_libfunc (lt_optab, TFmode, "_q_flt");
8507 set_optab_libfunc (le_optab, TFmode, "_q_fle");
8508
85363ca0
ZW		 8509 set_conv_libfunc (sext_optab, TFmode, SFmode, "_q_stoq");
8510 set_conv_libfunc (sext_optab, TFmode, DFmode, "_q_dtoq");
8511 set_conv_libfunc (trunc_optab, SFmode, TFmode, "_q_qtos");
8512 set_conv_libfunc (trunc_optab, DFmode, TFmode, "_q_qtod");
8513 set_conv_libfunc (sfix_optab, SImode, TFmode, "_q_qtoi");
8514 set_conv_libfunc (ufix_optab, SImode, TFmode, "_q_qtou");
8515 set_conv_libfunc (sfloat_optab, TFmode, SImode, "_q_itoq");
c15c90bb
ZW		 8516 }
8517}
fba73eb1
DE		 8518
8519\f
8520/* Expand a block clear operation, and return 1 if successful. Return 0
8521 if we should let the compiler generate normal code.
8522
8523 operands[0] is the destination
8524 operands[1] is the length
8525 operands[2] is the alignment */
8526
8527int
8528expand_block_clear (rtx operands[])
8529{
8530 rtx orig_dest = operands[0];
8531 rtx bytes_rtx = operands[1];
8532 rtx align_rtx = operands[2];
5514620a
GK		 8533 bool constp = (GET_CODE (bytes_rtx) == CONST_INT);
8534 HOST_WIDE_INT align;
8535 HOST_WIDE_INT bytes;
fba73eb1
DE		 8536 int offset;
8537 int clear_bytes;
5514620a 8538 int clear_step;
fba73eb1
DE		 8539
8540 /* If this is not a fixed size move, just call memcpy */
8541 if (! constp)
8542 return 0;
8543
37409796
NS		 8544 /* This must be a fixed size alignment */
8545 gcc_assert (GET_CODE (align_rtx) == CONST_INT);
fba73eb1
DE		 8546 align = INTVAL (align_rtx) * BITS_PER_UNIT;
8547
8548 /* Anything to clear? */
8549 bytes = INTVAL (bytes_rtx);
8550 if (bytes <= 0)
8551 return 1;
8552
5514620a
GK		 8553 /* Use the builtin memset after a point, to avoid huge code bloat.
8554 When optimize_size, avoid any significant code bloat; calling
8555 memset is about 4 instructions, so allow for one instruction to
8556 load zero and three to do clearing. */
8557 if (TARGET_ALTIVEC && align >= 128)
8558 clear_step = 16;
8559 else if (TARGET_POWERPC64 && align >= 32)
8560 clear_step = 8;
8561 else
8562 clear_step = 4;
fba73eb1 8563
5514620a
GK		 8564 if (optimize_size && bytes > 3 * clear_step)
8565 return 0;
8566 if (! optimize_size && bytes > 8 * clear_step)
fba73eb1
DE		 8567 return 0;
8568
8569 for (offset = 0; bytes > 0; offset += clear_bytes, bytes -= clear_bytes)
8570 {
fba73eb1
DE		 8571 enum machine_mode mode = BLKmode;
8572 rtx dest;
f676971a 8573
5514620a
GK		 8574 if (bytes >= 16 && TARGET_ALTIVEC && align >= 128)
8575 {
8576 clear_bytes = 16;
8577 mode = V4SImode;
8578 }
8579 else if (bytes >= 8 && TARGET_POWERPC64
8580 /* 64-bit loads and stores require word-aligned
8581 displacements. */
8582 && (align >= 64 || (!STRICT_ALIGNMENT && align >= 32)))
fba73eb1
DE		 8583 {
8584 clear_bytes = 8;
8585 mode = DImode;
fba73eb1 8586 }
5514620a 8587 else if (bytes >= 4 && (align >= 32 || !STRICT_ALIGNMENT))
fba73eb1
DE		 8588 { /* move 4 bytes */
8589 clear_bytes = 4;
8590 mode = SImode;
fba73eb1 8591 }
5514620a 8592 else if (bytes == 2 && (align >= 16 || !STRICT_ALIGNMENT))
fba73eb1
DE		 8593 { /* move 2 bytes */
8594 clear_bytes = 2;
8595 mode = HImode;
fba73eb1
DE		 8596 }
8597 else /* move 1 byte at a time */
8598 {
8599 clear_bytes = 1;
8600 mode = QImode;
fba73eb1 8601 }
f676971a 8602
fba73eb1 8603 dest = adjust_address (orig_dest, mode, offset);
f676971a 8604
5514620a 8605 emit_move_insn (dest, CONST0_RTX (mode));
fba73eb1
DE		 8606 }
8607
8608 return 1;
8609}
8610
35aff10b 8611\f
7e69e155
MM		 8612/* Expand a block move operation, and return 1 if successful. Return 0
8613 if we should let the compiler generate normal code.
8614
8615 operands[0] is the destination
8616 operands[1] is the source
8617 operands[2] is the length
8618 operands[3] is the alignment */
8619
3933e0e1
MM		 8620#define MAX_MOVE_REG 4
8621
7e69e155 8622int
a2369ed3 8623expand_block_move (rtx operands[])
7e69e155 8624{
b6c9286a
MM		 8625 rtx orig_dest = operands[0];
8626 rtx orig_src = operands[1];
7e69e155 8627 rtx bytes_rtx = operands[2];
7e69e155 8628 rtx align_rtx = operands[3];
3933e0e1 8629 int constp = (GET_CODE (bytes_rtx) == CONST_INT);
5ee95df6 8630 int align;
3933e0e1
MM		 8631 int bytes;
8632 int offset;
7e69e155 8633 int move_bytes;
cabfd258
GK		 8634 rtx stores[MAX_MOVE_REG];
8635 int num_reg = 0;
7e69e155 8636
3933e0e1 8637 /* If this is not a fixed size move, just call memcpy */
cc0d9ba8 8638 if (! constp)
3933e0e1
MM		 8639 return 0;
8640
37409796
NS		 8641 /* This must be a fixed size alignment */
8642 gcc_assert (GET_CODE (align_rtx) == CONST_INT);
fba73eb1 8643 align = INTVAL (align_rtx) * BITS_PER_UNIT;
5ee95df6 8644
7e69e155 8645 /* Anything to move? */
3933e0e1
MM		 8646 bytes = INTVAL (bytes_rtx);
8647 if (bytes <= 0)
7e69e155
MM		 8648 return 1;
8649
ea9982a8 8650 /* store_one_arg depends on expand_block_move to handle at least the size of
f676971a 8651 reg_parm_stack_space. */
ea9982a8 8652 if (bytes > (TARGET_POWERPC64 ? 64 : 32))
7e69e155
MM		 8653 return 0;
8654
cabfd258 8655 for (offset = 0; bytes > 0; offset += move_bytes, bytes -= move_bytes)
7e69e155 8656 {
cabfd258 8657 union {
70128ad9 8658 rtx (*movmemsi) (rtx, rtx, rtx, rtx);
a2369ed3 8659 rtx (*mov) (rtx, rtx);
cabfd258
GK		 8660 } gen_func;
8661 enum machine_mode mode = BLKmode;
8662 rtx src, dest;
f676971a 8663
5514620a
GK		 8664 /* Altivec first, since it will be faster than a string move
8665 when it applies, and usually not significantly larger. */
8666 if (TARGET_ALTIVEC && bytes >= 16 && align >= 128)
8667 {
8668 move_bytes = 16;
8669 mode = V4SImode;
8670 gen_func.mov = gen_movv4si;
8671 }
8672 else if (TARGET_STRING
cabfd258
GK		 8673 && bytes > 24 /* move up to 32 bytes at a time */
8674 && ! fixed_regs[5]
8675 && ! fixed_regs[6]
8676 && ! fixed_regs[7]
8677 && ! fixed_regs[8]
8678 && ! fixed_regs[9]
8679 && ! fixed_regs[10]
8680 && ! fixed_regs[11]
8681 && ! fixed_regs[12])
7e69e155 8682 {
cabfd258 8683 move_bytes = (bytes > 32) ? 32 : bytes;
70128ad9 8684 gen_func.movmemsi = gen_movmemsi_8reg;
cabfd258
GK		 8685 }
8686 else if (TARGET_STRING
8687 && bytes > 16 /* move up to 24 bytes at a time */
8688 && ! fixed_regs[5]
8689 && ! fixed_regs[6]
8690 && ! fixed_regs[7]
8691 && ! fixed_regs[8]
8692 && ! fixed_regs[9]
8693 && ! fixed_regs[10])
8694 {
8695 move_bytes = (bytes > 24) ? 24 : bytes;
70128ad9 8696 gen_func.movmemsi = gen_movmemsi_6reg;
cabfd258
GK		 8697 }
8698 else if (TARGET_STRING
8699 && bytes > 8 /* move up to 16 bytes at a time */
8700 && ! fixed_regs[5]
8701 && ! fixed_regs[6]
8702 && ! fixed_regs[7]
8703 && ! fixed_regs[8])
8704 {
8705 move_bytes = (bytes > 16) ? 16 : bytes;
70128ad9 8706 gen_func.movmemsi = gen_movmemsi_4reg;
cabfd258
GK		 8707 }
8708 else if (bytes >= 8 && TARGET_POWERPC64
8709 /* 64-bit loads and stores require word-aligned
8710 displacements. */
fba73eb1 8711 && (align >= 64 || (!STRICT_ALIGNMENT && align >= 32)))
cabfd258
GK		 8712 {
8713 move_bytes = 8;
8714 mode = DImode;
8715 gen_func.mov = gen_movdi;
8716 }
8717 else if (TARGET_STRING && bytes > 4 && !TARGET_POWERPC64)
8718 { /* move up to 8 bytes at a time */
8719 move_bytes = (bytes > 8) ? 8 : bytes;
70128ad9 8720 gen_func.movmemsi = gen_movmemsi_2reg;
cabfd258 8721 }
cd7d9ca4 8722 else if (bytes >= 4 && (align >= 32 || !STRICT_ALIGNMENT))
cabfd258
GK		 8723 { /* move 4 bytes */
8724 move_bytes = 4;
8725 mode = SImode;
8726 gen_func.mov = gen_movsi;
8727 }
cd7d9ca4 8728 else if (bytes == 2 && (align >= 16 || !STRICT_ALIGNMENT))
cabfd258
GK		 8729 { /* move 2 bytes */
8730 move_bytes = 2;
8731 mode = HImode;
8732 gen_func.mov = gen_movhi;
8733 }
8734 else if (TARGET_STRING && bytes > 1)
8735 { /* move up to 4 bytes at a time */
8736 move_bytes = (bytes > 4) ? 4 : bytes;
70128ad9 8737 gen_func.movmemsi = gen_movmemsi_1reg;
cabfd258
GK		 8738 }
8739 else /* move 1 byte at a time */
8740 {
8741 move_bytes = 1;
8742 mode = QImode;
8743 gen_func.mov = gen_movqi;
8744 }
f676971a 8745
cabfd258
GK		 8746 src = adjust_address (orig_src, mode, offset);
8747 dest = adjust_address (orig_dest, mode, offset);
f676971a
EC		 8748
8749 if (mode != BLKmode)
cabfd258
GK		 8750 {
8751 rtx tmp_reg = gen_reg_rtx (mode);
f676971a 8752
cabfd258
GK		 8753 emit_insn ((*gen_func.mov) (tmp_reg, src));
8754 stores[num_reg++] = (*gen_func.mov) (dest, tmp_reg);
4c64a852 8755 }
3933e0e1 8756
cabfd258
GK		 8757 if (mode == BLKmode || num_reg >= MAX_MOVE_REG || bytes == move_bytes)
8758 {
8759 int i;
8760 for (i = 0; i < num_reg; i++)
8761 emit_insn (stores[i]);
8762 num_reg = 0;
8763 }
35aff10b 8764
cabfd258 8765 if (mode == BLKmode)
7e69e155 8766 {
70128ad9 8767 /* Move the address into scratch registers. The movmemsi
cabfd258
GK		 8768 patterns require zero offset. */
8769 if (!REG_P (XEXP (src, 0)))
b6c9286a 8770 {
cabfd258
GK		 8771 rtx src_reg = copy_addr_to_reg (XEXP (src, 0));
8772 src = replace_equiv_address (src, src_reg);
b6c9286a 8773 }
cabfd258 8774 set_mem_size (src, GEN_INT (move_bytes));
f676971a 8775
cabfd258 8776 if (!REG_P (XEXP (dest, 0)))
3933e0e1 8777 {
cabfd258
GK		 8778 rtx dest_reg = copy_addr_to_reg (XEXP (dest, 0));
8779 dest = replace_equiv_address (dest, dest_reg);
7e69e155 8780 }
cabfd258 8781 set_mem_size (dest, GEN_INT (move_bytes));
f676971a 8782
70128ad9 8783 emit_insn ((*gen_func.movmemsi) (dest, src,
cabfd258
GK		 8784 GEN_INT (move_bytes & 31),
8785 align_rtx));
7e69e155 8786 }
7e69e155
MM		 8787 }
8788
8789 return 1;
8790}
8791
d62294f5 8792\f
9caa3eb2
DE		 8793/* Return a string to perform a load_multiple operation.
8794 operands[0] is the vector.
8795 operands[1] is the source address.
8796 operands[2] is the first destination register. */
8797
8798const char *
a2369ed3 8799rs6000_output_load_multiple (rtx operands[3])
9caa3eb2
DE		 8800{
8801 /* We have to handle the case where the pseudo used to contain the address
8802 is assigned to one of the output registers. */
8803 int i, j;
8804 int words = XVECLEN (operands[0], 0);
8805 rtx xop[10];
8806
8807 if (XVECLEN (operands[0], 0) == 1)
8808 return "{l|lwz} %2,0(%1)";
8809
8810 for (i = 0; i < words; i++)
8811 if (refers_to_regno_p (REGNO (operands[2]) + i,
8812 REGNO (operands[2]) + i + 1, operands[1], 0))
8813 {
8814 if (i == words-1)
8815 {
8816 xop[0] = GEN_INT (4 * (words-1));
8817 xop[1] = operands[1];
8818 xop[2] = operands[2];
8819 output_asm_insn ("{lsi|lswi} %2,%1,%0\n\t{l|lwz} %1,%0(%1)", xop);
8820 return "";
8821 }
8822 else if (i == 0)
8823 {
8824 xop[0] = GEN_INT (4 * (words-1));
8825 xop[1] = operands[1];
8826 xop[2] = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
8827 output_asm_insn ("{cal %1,4(%1)|addi %1,%1,4}\n\t{lsi|lswi} %2,%1,%0\n\t{l|lwz} %1,-4(%1)", xop);
8828 return "";
8829 }
8830 else
8831 {
8832 for (j = 0; j < words; j++)
8833 if (j != i)
8834 {
8835 xop[0] = GEN_INT (j * 4);
8836 xop[1] = operands[1];
8837 xop[2] = gen_rtx_REG (SImode, REGNO (operands[2]) + j);
8838 output_asm_insn ("{l|lwz} %2,%0(%1)", xop);
8839 }
8840 xop[0] = GEN_INT (i * 4);
8841 xop[1] = operands[1];
8842 output_asm_insn ("{l|lwz} %1,%0(%1)", xop);
8843 return "";
8844 }
8845 }
8846
8847 return "{lsi|lswi} %2,%1,%N0";
8848}
8849
9878760c 8850\f
a4f6c312
SS		 8851/* A validation routine: say whether CODE, a condition code, and MODE
8852 match. The other alternatives either don't make sense or should
8853 never be generated. */
39a10a29 8854
48d72335 8855void
a2369ed3 8856validate_condition_mode (enum rtx_code code, enum machine_mode mode)
39a10a29 8857{
37409796
NS		 8858 gcc_assert ((GET_RTX_CLASS (code) == RTX_COMPARE
8859 || GET_RTX_CLASS (code) == RTX_COMM_COMPARE)
8860 && GET_MODE_CLASS (mode) == MODE_CC);
39a10a29
GK		 8861
8862 /* These don't make sense. */
37409796
NS		 8863 gcc_assert ((code != GT && code != LT && code != GE && code != LE)
8864 || mode != CCUNSmode);
39a10a29 8865
37409796
NS		 8866 gcc_assert ((code != GTU && code != LTU && code != GEU && code != LEU)
8867 || mode == CCUNSmode);
39a10a29 8868
37409796
NS		 8869 gcc_assert (mode == CCFPmode
8870 || (code != ORDERED && code != UNORDERED
8871 && code != UNEQ && code != LTGT
8872 && code != UNGT && code != UNLT
8873 && code != UNGE && code != UNLE));
f676971a
EC		 8874
8875 /* These should never be generated except for
bc9ec0e0 8876 flag_finite_math_only. */
37409796
NS		 8877 gcc_assert (mode != CCFPmode
8878 || flag_finite_math_only
8879 || (code != LE && code != GE
8880 && code != UNEQ && code != LTGT
8881 && code != UNGT && code != UNLT));
39a10a29
GK		 8882
8883 /* These are invalid; the information is not there. */
37409796 8884 gcc_assert (mode != CCEQmode || code == EQ || code == NE);
39a10a29
GK		 8885}
8886
9878760c
RK		 8887\f
8888/* Return 1 if ANDOP is a mask that has no bits on that are not in the
8889 mask required to convert the result of a rotate insn into a shift
b1765bde 8890 left insn of SHIFTOP bits. Both are known to be SImode CONST_INT. */
9878760c
RK		 8891
8892int
a2369ed3 8893includes_lshift_p (rtx shiftop, rtx andop)
9878760c 8894{
e2c953b6
DE		 8895 unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0;
8896
8897 shift_mask <<= INTVAL (shiftop);
9878760c 8898
b1765bde 8899 return (INTVAL (andop) & 0xffffffff & ~shift_mask) == 0;
9878760c
RK		 8900}
8901
8902/* Similar, but for right shift. */
8903
8904int
a2369ed3 8905includes_rshift_p (rtx shiftop, rtx andop)
9878760c 8906{
a7653a2c 8907 unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0;
9878760c
RK		 8908
8909 shift_mask >>= INTVAL (shiftop);
8910
b1765bde 8911 return (INTVAL (andop) & 0xffffffff & ~shift_mask) == 0;
e2c953b6
DE		 8912}
8913
c5059423
AM		 8914/* Return 1 if ANDOP is a mask suitable for use with an rldic insn
8915 to perform a left shift. It must have exactly SHIFTOP least
b6d08ca1 8916 significant 0's, then one or more 1's, then zero or more 0's. */
e2c953b6
DE		 8917
8918int
a2369ed3 8919includes_rldic_lshift_p (rtx shiftop, rtx andop)
e2c953b6 8920{
c5059423
AM		 8921 if (GET_CODE (andop) == CONST_INT)
8922 {
02071907 8923 HOST_WIDE_INT c, lsb, shift_mask;
e2c953b6 8924
c5059423 8925 c = INTVAL (andop);
02071907 8926 if (c == 0 || c == ~0)
c5059423 8927 return 0;
e2c953b6 8928
02071907 8929 shift_mask = ~0;
c5059423
AM		 8930 shift_mask <<= INTVAL (shiftop);
8931
b6d08ca1 8932 /* Find the least significant one bit. */
c5059423
AM		 8933 lsb = c & -c;
8934
8935 /* It must coincide with the LSB of the shift mask. */
8936 if (-lsb != shift_mask)
8937 return 0;
e2c953b6 8938
c5059423
AM		 8939 /* Invert to look for the next transition (if any). */
8940 c = ~c;
8941
8942 /* Remove the low group of ones (originally low group of zeros). */
8943 c &= -lsb;
8944
8945 /* Again find the lsb, and check we have all 1's above. */
8946 lsb = c & -c;
8947 return c == -lsb;
8948 }
8949 else if (GET_CODE (andop) == CONST_DOUBLE
8950 && (GET_MODE (andop) == VOIDmode || GET_MODE (andop) == DImode))
8951 {
02071907
AM		 8952 HOST_WIDE_INT low, high, lsb;
8953 HOST_WIDE_INT shift_mask_low, shift_mask_high;
c5059423
AM		 8954
8955 low = CONST_DOUBLE_LOW (andop);
8956 if (HOST_BITS_PER_WIDE_INT < 64)
8957 high = CONST_DOUBLE_HIGH (andop);
8958
8959 if ((low == 0 && (HOST_BITS_PER_WIDE_INT >= 64 || high == 0))
02071907 8960 || (low == ~0 && (HOST_BITS_PER_WIDE_INT >= 64 || high == ~0)))
c5059423
AM		 8961 return 0;
8962
8963 if (HOST_BITS_PER_WIDE_INT < 64 && low == 0)
8964 {
02071907 8965 shift_mask_high = ~0;
c5059423
AM		 8966 if (INTVAL (shiftop) > 32)
8967 shift_mask_high <<= INTVAL (shiftop) - 32;
8968
8969 lsb = high & -high;
8970
8971 if (-lsb != shift_mask_high || INTVAL (shiftop) < 32)
8972 return 0;
8973
8974 high = ~high;
8975 high &= -lsb;
8976
8977 lsb = high & -high;
8978 return high == -lsb;
8979 }
8980
02071907 8981 shift_mask_low = ~0;
c5059423
AM		 8982 shift_mask_low <<= INTVAL (shiftop);
8983
8984 lsb = low & -low;
8985
8986 if (-lsb != shift_mask_low)
8987 return 0;
8988
8989 if (HOST_BITS_PER_WIDE_INT < 64)
8990 high = ~high;
8991 low = ~low;
8992 low &= -lsb;
8993
8994 if (HOST_BITS_PER_WIDE_INT < 64 && low == 0)
8995 {
8996 lsb = high & -high;
8997 return high == -lsb;
8998 }
8999
9000 lsb = low & -low;
9001 return low == -lsb && (HOST_BITS_PER_WIDE_INT >= 64 || high == ~0);
9002 }
9003 else
9004 return 0;
9005}
e2c953b6 9006
c5059423
AM		 9007/* Return 1 if ANDOP is a mask suitable for use with an rldicr insn
9008 to perform a left shift. It must have SHIFTOP or more least
c1207243 9009 significant 0's, with the remainder of the word 1's. */
e2c953b6 9010
c5059423 9011int
a2369ed3 9012includes_rldicr_lshift_p (rtx shiftop, rtx andop)
c5059423 9013{
e2c953b6 9014 if (GET_CODE (andop) == CONST_INT)
c5059423 9015 {
02071907 9016 HOST_WIDE_INT c, lsb, shift_mask;
c5059423 9017
02071907 9018 shift_mask = ~0;
c5059423
AM		 9019 shift_mask <<= INTVAL (shiftop);
9020 c = INTVAL (andop);
9021
c1207243 9022 /* Find the least significant one bit. */
c5059423
AM		 9023 lsb = c & -c;
9024
9025 /* It must be covered by the shift mask.
a4f6c312 9026 This test also rejects c == 0. */
c5059423
AM		 9027 if ((lsb & shift_mask) == 0)
9028 return 0;
9029
9030 /* Check we have all 1's above the transition, and reject all 1's. */
9031 return c == -lsb && lsb != 1;
9032 }
9033 else if (GET_CODE (andop) == CONST_DOUBLE
9034 && (GET_MODE (andop) == VOIDmode || GET_MODE (andop) == DImode))
9035 {
02071907 9036 HOST_WIDE_INT low, lsb, shift_mask_low;
c5059423
AM		 9037
9038 low = CONST_DOUBLE_LOW (andop);
9039
9040 if (HOST_BITS_PER_WIDE_INT < 64)
9041 {
02071907 9042 HOST_WIDE_INT high, shift_mask_high;
c5059423
AM		 9043
9044 high = CONST_DOUBLE_HIGH (andop);
9045
9046 if (low == 0)
9047 {
02071907 9048 shift_mask_high = ~0;
c5059423
AM		 9049 if (INTVAL (shiftop) > 32)
9050 shift_mask_high <<= INTVAL (shiftop) - 32;
9051
9052 lsb = high & -high;
9053
9054 if ((lsb & shift_mask_high) == 0)
9055 return 0;
9056
9057 return high == -lsb;
9058 }
9059 if (high != ~0)
9060 return 0;
9061 }
9062
02071907 9063 shift_mask_low = ~0;
c5059423
AM		 9064 shift_mask_low <<= INTVAL (shiftop);
9065
9066 lsb = low & -low;
9067
9068 if ((lsb & shift_mask_low) == 0)
9069 return 0;
9070
9071 return low == -lsb && lsb != 1;
9072 }
e2c953b6 9073 else
c5059423 9074 return 0;
9878760c 9075}
35068b43 9076
11ac38b2
DE		 9077/* Return 1 if operands will generate a valid arguments to rlwimi
9078instruction for insert with right shift in 64-bit mode. The mask may
9079not start on the first bit or stop on the last bit because wrap-around
9080effects of instruction do not correspond to semantics of RTL insn. */
9081
9082int
9083insvdi_rshift_rlwimi_p (rtx sizeop, rtx startop, rtx shiftop)
9084{
9085 if (INTVAL (startop) < 64
9086 && INTVAL (startop) > 32
9087 && (INTVAL (sizeop) + INTVAL (startop) < 64)
9088 && (INTVAL (sizeop) + INTVAL (startop) > 33)
9089 && (INTVAL (sizeop) + INTVAL (startop) + INTVAL (shiftop) < 96)
9090 && (INTVAL (sizeop) + INTVAL (startop) + INTVAL (shiftop) >= 64)
9091 && (64 - (INTVAL (shiftop) & 63)) >= INTVAL (sizeop))
9092 return 1;
9093
9094 return 0;
9095}
9096
35068b43 9097/* Return 1 if REGNO (reg1) == REGNO (reg2) - 1 making them candidates
90f81f99 9098 for lfq and stfq insns iff the registers are hard registers. */
35068b43
RK		 9099
9100int
a2369ed3 9101registers_ok_for_quad_peep (rtx reg1, rtx reg2)
35068b43
RK		 9102{
9103 /* We might have been passed a SUBREG. */
f676971a 9104 if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG)
35068b43 9105 return 0;
f676971a 9106
90f81f99
AP		 9107 /* We might have been passed non floating point registers. */
9108 if (!FP_REGNO_P (REGNO (reg1))
9109 || !FP_REGNO_P (REGNO (reg2)))
9110 return 0;
35068b43
RK		 9111
9112 return (REGNO (reg1) == REGNO (reg2) - 1);
9113}
9114
a4f6c312
SS		 9115/* Return 1 if addr1 and addr2 are suitable for lfq or stfq insn.
9116 addr1 and addr2 must be in consecutive memory locations
9117 (addr2 == addr1 + 8). */
35068b43
RK		 9118
9119int
90f81f99 9120mems_ok_for_quad_peep (rtx mem1, rtx mem2)
35068b43 9121{
90f81f99 9122 rtx addr1, addr2;
e2c953b6 9123 unsigned int reg1;
35068b43
RK		 9124 int offset1;
9125
90f81f99
AP		 9126 /* The mems cannot be volatile. */
9127 if (MEM_VOLATILE_P (mem1) || MEM_VOLATILE_P (mem2))
9128 return 0;
f676971a 9129
90f81f99
AP		 9130 addr1 = XEXP (mem1, 0);
9131 addr2 = XEXP (mem2, 0);
9132
35068b43
RK		 9133 /* Extract an offset (if used) from the first addr. */
9134 if (GET_CODE (addr1) == PLUS)
9135 {
9136 /* If not a REG, return zero. */
9137 if (GET_CODE (XEXP (addr1, 0)) != REG)
9138 return 0;
9139 else
9140 {
c4ad648e 9141 reg1 = REGNO (XEXP (addr1, 0));
35068b43
RK		 9142 /* The offset must be constant! */
9143 if (GET_CODE (XEXP (addr1, 1)) != CONST_INT)
c4ad648e
AM		 9144 return 0;
9145 offset1 = INTVAL (XEXP (addr1, 1));
35068b43
RK		 9146 }
9147 }
9148 else if (GET_CODE (addr1) != REG)
9149 return 0;
9150 else
9151 {
9152 reg1 = REGNO (addr1);
9153 /* This was a simple (mem (reg)) expression. Offset is 0. */
9154 offset1 = 0;
9155 }
9156
a2369ed3 9157 /* Make sure the second address is a (mem (plus (reg) (const_int)))
f676971a 9158 or if it is (mem (reg)) then make sure that offset1 is -8 and the same
0f6937fe 9159 register as addr1. */
984e25ac 9160 if (offset1 == -8 && GET_CODE (addr2) == REG && reg1 == REGNO (addr2))
0f6937fe 9161 return 1;
35068b43
RK		 9162 if (GET_CODE (addr2) != PLUS)
9163 return 0;
9164
9165 if (GET_CODE (XEXP (addr2, 0)) != REG
9166 || GET_CODE (XEXP (addr2, 1)) != CONST_INT)
9167 return 0;
9168
9169 if (reg1 != REGNO (XEXP (addr2, 0)))
9170 return 0;
9171
9172 /* The offset for the second addr must be 8 more than the first addr. */
9173 if (INTVAL (XEXP (addr2, 1)) != offset1 + 8)
9174 return 0;
9175
9176 /* All the tests passed. addr1 and addr2 are valid for lfq or stfq
9177 instructions. */
9178 return 1;
9179}
9878760c
RK		 9180\f
9181/* Return the register class of a scratch register needed to copy IN into
9182 or out of a register in CLASS in MODE. If it can be done directly,
9183 NO_REGS is returned. */
9184
9185enum reg_class
f676971a 9186secondary_reload_class (enum reg_class class,
a9baceb1
GK		 9187 enum machine_mode mode ATTRIBUTE_UNUSED,
9188 rtx in)
9878760c 9189{
5accd822 9190 int regno;
9878760c 9191
ab82a49f
AP		 9192 if (TARGET_ELF || (DEFAULT_ABI == ABI_DARWIN
9193#if TARGET_MACHO
c4ad648e 9194 && MACHOPIC_INDIRECT
ab82a49f 9195#endif
c4ad648e 9196 ))
46fad5b7
DJ		 9197 {
9198 /* We cannot copy a symbolic operand directly into anything
c4ad648e
AM		 9199 other than BASE_REGS for TARGET_ELF. So indicate that a
9200 register from BASE_REGS is needed as an intermediate
9201 register.
f676971a 9202
46fad5b7
DJ		 9203 On Darwin, pic addresses require a load from memory, which
9204 needs a base register. */
9205 if (class != BASE_REGS
c4ad648e
AM		 9206 && (GET_CODE (in) == SYMBOL_REF
9207 || GET_CODE (in) == HIGH
9208 || GET_CODE (in) == LABEL_REF
9209 || GET_CODE (in) == CONST))
9210 return BASE_REGS;
46fad5b7 9211 }
e7b7998a 9212
5accd822
DE		 9213 if (GET_CODE (in) == REG)
9214 {
9215 regno = REGNO (in);
9216 if (regno >= FIRST_PSEUDO_REGISTER)
9217 {
9218 regno = true_regnum (in);
9219 if (regno >= FIRST_PSEUDO_REGISTER)
9220 regno = -1;
9221 }
9222 }
9223 else if (GET_CODE (in) == SUBREG)
9224 {
9225 regno = true_regnum (in);
9226 if (regno >= FIRST_PSEUDO_REGISTER)
9227 regno = -1;
9228 }
9229 else
9230 regno = -1;
9231
9878760c
RK		 9232 /* We can place anything into GENERAL_REGS and can put GENERAL_REGS
9233 into anything. */
9234 if (class == GENERAL_REGS || class == BASE_REGS
9235 || (regno >= 0 && INT_REGNO_P (regno)))
9236 return NO_REGS;
9237
9238 /* Constants, memory, and FP registers can go into FP registers. */
9239 if ((regno == -1 || FP_REGNO_P (regno))
9240 && (class == FLOAT_REGS || class == NON_SPECIAL_REGS))
9241 return NO_REGS;
9242
0ac081f6
AH		 9243 /* Memory, and AltiVec registers can go into AltiVec registers. */
9244 if ((regno == -1 || ALTIVEC_REGNO_P (regno))
9245 && class == ALTIVEC_REGS)
9246 return NO_REGS;
9247
9878760c
RK		 9248 /* We can copy among the CR registers. */
9249 if ((class == CR_REGS || class == CR0_REGS)
9250 && regno >= 0 && CR_REGNO_P (regno))
9251 return NO_REGS;
9252
9253 /* Otherwise, we need GENERAL_REGS. */
9254 return GENERAL_REGS;
9255}
9256\f
9257/* Given a comparison operation, return the bit number in CCR to test. We
f676971a 9258 know this is a valid comparison.
9878760c
RK		 9259
9260 SCC_P is 1 if this is for an scc. That means that %D will have been
9261 used instead of %C, so the bits will be in different places.
9262
b4ac57ab 9263 Return -1 if OP isn't a valid comparison for some reason. */
9878760c
RK		 9264
9265int
a2369ed3 9266ccr_bit (rtx op, int scc_p)
9878760c
RK		 9267{
9268 enum rtx_code code = GET_CODE (op);
9269 enum machine_mode cc_mode;
9270 int cc_regnum;
9271 int base_bit;
9ebbca7d 9272 rtx reg;
9878760c 9273
ec8e098d 9274 if (!COMPARISON_P (op))
9878760c
RK		 9275 return -1;
9276
9ebbca7d
GK		 9277 reg = XEXP (op, 0);
9278
37409796 9279 gcc_assert (GET_CODE (reg) == REG && CR_REGNO_P (REGNO (reg)));
9ebbca7d
GK		 9280
9281 cc_mode = GET_MODE (reg);
9282 cc_regnum = REGNO (reg);
9283 base_bit = 4 * (cc_regnum - CR0_REGNO);
9878760c 9284
39a10a29 9285 validate_condition_mode (code, cc_mode);
c5defebb 9286
b7053a3f
GK		 9287 /* When generating a sCOND operation, only positive conditions are
9288 allowed. */
37409796
NS		 9289 gcc_assert (!scc_p
9290 || code == EQ || code == GT || code == LT || code == UNORDERED
9291 || code == GTU || code == LTU);
f676971a 9292
9878760c
RK		 9293 switch (code)
9294 {
9295 case NE:
9296 return scc_p ? base_bit + 3 : base_bit + 2;
9297 case EQ:
9298 return base_bit + 2;
1c882ea4 9299 case GT: case GTU: case UNLE:
9878760c 9300 return base_bit + 1;
1c882ea4 9301 case LT: case LTU: case UNGE:
9878760c 9302 return base_bit;
1c882ea4
GK		 9303 case ORDERED: case UNORDERED:
9304 return base_bit + 3;
9878760c
RK		 9305
9306 case GE: case GEU:
39a10a29 9307 /* If scc, we will have done a cror to put the bit in the
9878760c
RK		 9308 unordered position. So test that bit. For integer, this is ! LT
9309 unless this is an scc insn. */
39a10a29 9310 return scc_p ? base_bit + 3 : base_bit;
9878760c
RK		 9311
9312 case LE: case LEU:
39a10a29 9313 return scc_p ? base_bit + 3 : base_bit + 1;
1c882ea4 9314
9878760c 9315 default:
37409796 9316 gcc_unreachable ();
9878760c
RK		 9317 }
9318}
1ff7789b 9319\f
8d30c4ee 9320/* Return the GOT register. */
1ff7789b 9321
9390387d 9322rtx
a2369ed3 9323rs6000_got_register (rtx value ATTRIBUTE_UNUSED)
1ff7789b 9324{
a4f6c312
SS		 9325 /* The second flow pass currently (June 1999) can't update
9326 regs_ever_live without disturbing other parts of the compiler, so
9327 update it here to make the prolog/epilogue code happy. */
1db02437
FS		 9328 if (no_new_pseudos && ! regs_ever_live[RS6000_PIC_OFFSET_TABLE_REGNUM])
9329 regs_ever_live[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
1ff7789b 9330
8d30c4ee 9331 current_function_uses_pic_offset_table = 1;
3cb999d8 9332
1ff7789b
MM		 9333 return pic_offset_table_rtx;
9334}
a7df97e6 9335\f
e2500fed
GK		 9336/* Function to init struct machine_function.
9337 This will be called, via a pointer variable,
9338 from push_function_context. */
a7df97e6 9339
e2500fed 9340static struct machine_function *
863d938c 9341rs6000_init_machine_status (void)
a7df97e6 9342{
e2500fed 9343 return ggc_alloc_cleared (sizeof (machine_function));
a7df97e6 9344}
9878760c 9345\f
0ba1b2ff
AM		 9346/* These macros test for integers and extract the low-order bits. */
9347#define INT_P(X) \
9348((GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST_DOUBLE) \
9349 && GET_MODE (X) == VOIDmode)
9350
9351#define INT_LOWPART(X) \
9352 (GET_CODE (X) == CONST_INT ? INTVAL (X) : CONST_DOUBLE_LOW (X))
9353
9354int
a2369ed3 9355extract_MB (rtx op)
0ba1b2ff
AM		 9356{
9357 int i;
9358 unsigned long val = INT_LOWPART (op);
9359
9360 /* If the high bit is zero, the value is the first 1 bit we find
9361 from the left. */
9362 if ((val & 0x80000000) == 0)
9363 {
37409796 9364 gcc_assert (val & 0xffffffff);
0ba1b2ff
AM		 9365
9366 i = 1;
9367 while (((val <<= 1) & 0x80000000) == 0)
9368 ++i;
9369 return i;
9370 }
9371
9372 /* If the high bit is set and the low bit is not, or the mask is all
9373 1's, the value is zero. */
9374 if ((val & 1) == 0 || (val & 0xffffffff) == 0xffffffff)
9375 return 0;
9376
9377 /* Otherwise we have a wrap-around mask. Look for the first 0 bit
9378 from the right. */
9379 i = 31;
9380 while (((val >>= 1) & 1) != 0)
9381 --i;
9382
9383 return i;
9384}
9385
9386int
a2369ed3 9387extract_ME (rtx op)
0ba1b2ff
AM		 9388{
9389 int i;
9390 unsigned long val = INT_LOWPART (op);
9391
9392 /* If the low bit is zero, the value is the first 1 bit we find from
9393 the right. */
9394 if ((val & 1) == 0)
9395 {
37409796 9396 gcc_assert (val & 0xffffffff);
0ba1b2ff
AM		 9397
9398 i = 30;
9399 while (((val >>= 1) & 1) == 0)
9400 --i;
9401
9402 return i;
9403 }
9404
9405 /* If the low bit is set and the high bit is not, or the mask is all
9406 1's, the value is 31. */
9407 if ((val & 0x80000000) == 0 || (val & 0xffffffff) == 0xffffffff)
9408 return 31;
9409
9410 /* Otherwise we have a wrap-around mask. Look for the first 0 bit
9411 from the left. */
9412 i = 0;
9413 while (((val <<= 1) & 0x80000000) != 0)
9414 ++i;
9415
9416 return i;
9417}
9418
c4501e62
JJ		 9419/* Locate some local-dynamic symbol still in use by this function
9420 so that we can print its name in some tls_ld pattern. */
9421
9422static const char *
863d938c 9423rs6000_get_some_local_dynamic_name (void)
c4501e62
JJ		 9424{
9425 rtx insn;
9426
9427 if (cfun->machine->some_ld_name)
9428 return cfun->machine->some_ld_name;
9429
9430 for (insn = get_insns (); insn ; insn = NEXT_INSN (insn))
9431 if (INSN_P (insn)
9432 && for_each_rtx (&PATTERN (insn),
9433 rs6000_get_some_local_dynamic_name_1, 0))
9434 return cfun->machine->some_ld_name;
9435
37409796 9436 gcc_unreachable ();
c4501e62
JJ		 9437}
9438
9439/* Helper function for rs6000_get_some_local_dynamic_name. */
9440
9441static int
a2369ed3 9442rs6000_get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
c4501e62
JJ		 9443{
9444 rtx x = *px;
9445
9446 if (GET_CODE (x) == SYMBOL_REF)
9447 {
9448 const char *str = XSTR (x, 0);
9449 if (SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC)
9450 {
9451 cfun->machine->some_ld_name = str;
9452 return 1;
9453 }
9454 }
9455
9456 return 0;
9457}
9458
85b776df
AM		 9459/* Write out a function code label. */
9460
9461void
9462rs6000_output_function_entry (FILE *file, const char *fname)
9463{
9464 if (fname[0] != '.')
9465 {
9466 switch (DEFAULT_ABI)
9467 {
9468 default:
37409796 9469 gcc_unreachable ();
85b776df
AM		 9470
9471 case ABI_AIX:
9472 if (DOT_SYMBOLS)
9473 putc ('.', file);
9474 else
9475 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "L.");
9476 break;
9477
9478 case ABI_V4:
9479 case ABI_DARWIN:
9480 break;
9481 }
9482 }
9483 if (TARGET_AIX)
9484 RS6000_OUTPUT_BASENAME (file, fname);
9485 else
9486 assemble_name (file, fname);
9487}
9488
9878760c
RK		 9489/* Print an operand. Recognize special options, documented below. */
9490
38c1f2d7 9491#if TARGET_ELF
d9407988 9492#define SMALL_DATA_RELOC ((rs6000_sdata == SDATA_EABI) ? "sda21" : "sdarel")
8fbd2dc7 9493#define SMALL_DATA_REG ((rs6000_sdata == SDATA_EABI) ? 0 : 13)
ba5e43aa
MM		 9494#else
9495#define SMALL_DATA_RELOC "sda21"
8fbd2dc7 9496#define SMALL_DATA_REG 0
ba5e43aa
MM		 9497#endif
9498
9878760c 9499void
a2369ed3 9500print_operand (FILE *file, rtx x, int code)
9878760c
RK		 9501{
9502 int i;
a260abc9 9503 HOST_WIDE_INT val;
0ba1b2ff 9504 unsigned HOST_WIDE_INT uval;
9878760c
RK		 9505
9506 switch (code)
9507 {
a8b3aeda 9508 case '.':
a85d226b
RK		 9509 /* Write out an instruction after the call which may be replaced
9510 with glue code by the loader. This depends on the AIX version. */
9511 asm_fprintf (file, RS6000_CALL_GLUE);
a8b3aeda
RK		 9512 return;
9513
81eace42
GK		 9514 /* %a is output_address. */
9515
9854d9ed
RK		 9516 case 'A':
9517 /* If X is a constant integer whose low-order 5 bits are zero,
9518 write 'l'. Otherwise, write 'r'. This is a kludge to fix a bug
76229ac8 9519 in the AIX assembler where "sri" with a zero shift count
20e26713 9520 writes a trash instruction. */
9854d9ed 9521 if (GET_CODE (x) == CONST_INT && (INTVAL (x) & 31) == 0)
76229ac8 9522 putc ('l', file);
9854d9ed 9523 else
76229ac8 9524 putc ('r', file);
9854d9ed
RK		 9525 return;
9526
9527 case 'b':
e2c953b6
DE		 9528 /* If constant, low-order 16 bits of constant, unsigned.
9529 Otherwise, write normally. */
9530 if (INT_P (x))
9531 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 0xffff);
9532 else
9533 print_operand (file, x, 0);
cad12a8d
RK		 9534 return;
9535
a260abc9
DE		 9536 case 'B':
9537 /* If the low-order bit is zero, write 'r'; otherwise, write 'l'
9538 for 64-bit mask direction. */
9390387d 9539 putc (((INT_LOWPART (x) & 1) == 0 ? 'r' : 'l'), file);
a238cd8b 9540 return;
a260abc9 9541
81eace42
GK		 9542 /* %c is output_addr_const if a CONSTANT_ADDRESS_P, otherwise
9543 output_operand. */
9544
423c1189
AH		 9545 case 'c':
9546 /* X is a CR register. Print the number of the GT bit of the CR. */
9547 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
9548 output_operand_lossage ("invalid %%E value");
9549 else
9550 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO) + 1);
9551 return;
9552
9553 case 'D':
6b1fedc3 9554 /* Like 'J' but get to the EQ bit. */
37409796 9555 gcc_assert (GET_CODE (x) == REG);
423c1189 9556
6b1fedc3
AH		 9557 /* Bit 1 is EQ bit. */
9558 i = 4 * (REGNO (x) - CR0_REGNO) + 2;
423c1189 9559
64022b5d 9560 fprintf (file, "%d", i);
423c1189
AH		 9561 return;
9562
9854d9ed 9563 case 'E':
39a10a29 9564 /* X is a CR register. Print the number of the EQ bit of the CR */
9854d9ed
RK		 9565 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
9566 output_operand_lossage ("invalid %%E value");
78fbdbf7 9567 else
39a10a29 9568 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO) + 2);
a85d226b 9569 return;
9854d9ed
RK		 9570
9571 case 'f':
9572 /* X is a CR register. Print the shift count needed to move it
9573 to the high-order four bits. */
9574 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
9575 output_operand_lossage ("invalid %%f value");
9576 else
9ebbca7d 9577 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO));
9854d9ed
RK		 9578 return;
9579
9580 case 'F':
9581 /* Similar, but print the count for the rotate in the opposite
9582 direction. */
9583 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
9584 output_operand_lossage ("invalid %%F value");
9585 else
9ebbca7d 9586 fprintf (file, "%d", 32 - 4 * (REGNO (x) - CR0_REGNO));
9854d9ed
RK		 9587 return;
9588
9589 case 'G':
9590 /* X is a constant integer. If it is negative, print "m",
43aa4e05 9591 otherwise print "z". This is to make an aze or ame insn. */
9854d9ed
RK		 9592 if (GET_CODE (x) != CONST_INT)
9593 output_operand_lossage ("invalid %%G value");
9594 else if (INTVAL (x) >= 0)
76229ac8 9595 putc ('z', file);
9854d9ed 9596 else
76229ac8 9597 putc ('m', file);
9854d9ed 9598 return;
e2c953b6 9599
9878760c 9600 case 'h':
a4f6c312
SS		 9601 /* If constant, output low-order five bits. Otherwise, write
9602 normally. */
9878760c 9603 if (INT_P (x))
5f59ecb7 9604 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 31);
9878760c
RK		 9605 else
9606 print_operand (file, x, 0);
9607 return;
9608
64305719 9609 case 'H':
a4f6c312
SS		 9610 /* If constant, output low-order six bits. Otherwise, write
9611 normally. */
64305719 9612 if (INT_P (x))
5f59ecb7 9613 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 63);
64305719
DE		 9614 else
9615 print_operand (file, x, 0);
9616 return;
9617
9854d9ed
RK		 9618 case 'I':
9619 /* Print `i' if this is a constant, else nothing. */
9878760c 9620 if (INT_P (x))
76229ac8 9621 putc ('i', file);
9878760c
RK		 9622 return;
9623
9854d9ed
RK		 9624 case 'j':
9625 /* Write the bit number in CCR for jump. */
9626 i = ccr_bit (x, 0);
9627 if (i == -1)
9628 output_operand_lossage ("invalid %%j code");
9878760c 9629 else
9854d9ed 9630 fprintf (file, "%d", i);
9878760c
RK		 9631 return;
9632
9854d9ed
RK		 9633 case 'J':
9634 /* Similar, but add one for shift count in rlinm for scc and pass
9635 scc flag to `ccr_bit'. */
9636 i = ccr_bit (x, 1);
9637 if (i == -1)
9638 output_operand_lossage ("invalid %%J code");
9639 else
a0466a68
RK		 9640 /* If we want bit 31, write a shift count of zero, not 32. */
9641 fprintf (file, "%d", i == 31 ? 0 : i + 1);
9878760c
RK		 9642 return;
9643
9854d9ed
RK		 9644 case 'k':
9645 /* X must be a constant. Write the 1's complement of the
9646 constant. */
9878760c 9647 if (! INT_P (x))
9854d9ed 9648 output_operand_lossage ("invalid %%k value");
e2c953b6
DE		 9649 else
9650 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ~ INT_LOWPART (x));
9878760c
RK		 9651 return;
9652
81eace42 9653 case 'K':
9ebbca7d
GK		 9654 /* X must be a symbolic constant on ELF. Write an
9655 expression suitable for an 'addi' that adds in the low 16
9656 bits of the MEM. */
9657 if (GET_CODE (x) != CONST)
9658 {
9659 print_operand_address (file, x);
9660 fputs ("@l", file);
9661 }
9662 else
9663 {
9664 if (GET_CODE (XEXP (x, 0)) != PLUS
9665 || (GET_CODE (XEXP (XEXP (x, 0), 0)) != SYMBOL_REF
9666 && GET_CODE (XEXP (XEXP (x, 0), 0)) != LABEL_REF)
9667 || GET_CODE (XEXP (XEXP (x, 0), 1)) != CONST_INT)
53cd5d6c 9668 output_operand_lossage ("invalid %%K value");
9ebbca7d
GK		 9669 print_operand_address (file, XEXP (XEXP (x, 0), 0));
9670 fputs ("@l", file);
ed8d2920
MM		 9671 /* For GNU as, there must be a non-alphanumeric character
9672 between 'l' and the number. The '-' is added by
9673 print_operand() already. */
9674 if (INTVAL (XEXP (XEXP (x, 0), 1)) >= 0)
9675 fputs ("+", file);
9ebbca7d
GK		 9676 print_operand (file, XEXP (XEXP (x, 0), 1), 0);
9677 }
81eace42
GK		 9678 return;
9679
9680 /* %l is output_asm_label. */
9ebbca7d 9681
9854d9ed
RK		 9682 case 'L':
9683 /* Write second word of DImode or DFmode reference. Works on register
9684 or non-indexed memory only. */
9685 if (GET_CODE (x) == REG)
fb5c67a7 9686 fputs (reg_names[REGNO (x) + 1], file);
9854d9ed
RK		 9687 else if (GET_CODE (x) == MEM)
9688 {
9689 /* Handle possible auto-increment. Since it is pre-increment and
1427100a 9690 we have already done it, we can just use an offset of word. */
9854d9ed
RK		 9691 if (GET_CODE (XEXP (x, 0)) == PRE_INC
9692 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
ed8908e7
RK		 9693 output_address (plus_constant (XEXP (XEXP (x, 0), 0),
9694 UNITS_PER_WORD));
9854d9ed 9695 else
d7624dc0
RK		 9696 output_address (XEXP (adjust_address_nv (x, SImode,
9697 UNITS_PER_WORD),
9698 0));
ed8908e7 9699
ba5e43aa 9700 if (small_data_operand (x, GET_MODE (x)))
8fbd2dc7
MM		 9701 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
9702 reg_names[SMALL_DATA_REG]);
9854d9ed 9703 }
9878760c 9704 return;
f676971a 9705
9878760c
RK		 9706 case 'm':
9707 /* MB value for a mask operand. */
b1765bde 9708 if (! mask_operand (x, SImode))
9878760c
RK		 9709 output_operand_lossage ("invalid %%m value");
9710
0ba1b2ff 9711 fprintf (file, "%d", extract_MB (x));
9878760c
RK		 9712 return;
9713
9714 case 'M':
9715 /* ME value for a mask operand. */
b1765bde 9716 if (! mask_operand (x, SImode))
a260abc9 9717 output_operand_lossage ("invalid %%M value");
9878760c 9718
0ba1b2ff 9719 fprintf (file, "%d", extract_ME (x));
9878760c
RK		 9720 return;
9721
81eace42
GK		 9722 /* %n outputs the negative of its operand. */
9723
9878760c
RK		 9724 case 'N':
9725 /* Write the number of elements in the vector times 4. */
9726 if (GET_CODE (x) != PARALLEL)
9727 output_operand_lossage ("invalid %%N value");
e2c953b6
DE		 9728 else
9729 fprintf (file, "%d", XVECLEN (x, 0) * 4);
9878760c
RK		 9730 return;
9731
9732 case 'O':
9733 /* Similar, but subtract 1 first. */
9734 if (GET_CODE (x) != PARALLEL)
1427100a 9735 output_operand_lossage ("invalid %%O value");
e2c953b6
DE		 9736 else
9737 fprintf (file, "%d", (XVECLEN (x, 0) - 1) * 4);
9878760c
RK		 9738 return;
9739
9854d9ed
RK		 9740 case 'p':
9741 /* X is a CONST_INT that is a power of two. Output the logarithm. */
9742 if (! INT_P (x)
2bfcf297 9743 || INT_LOWPART (x) < 0
9854d9ed
RK		 9744 || (i = exact_log2 (INT_LOWPART (x))) < 0)
9745 output_operand_lossage ("invalid %%p value");
e2c953b6
DE		 9746 else
9747 fprintf (file, "%d", i);
9854d9ed
RK		 9748 return;
9749
9878760c
RK		 9750 case 'P':
9751 /* The operand must be an indirect memory reference. The result
8bb418a3 9752 is the register name. */
9878760c
RK		 9753 if (GET_CODE (x) != MEM || GET_CODE (XEXP (x, 0)) != REG
9754 || REGNO (XEXP (x, 0)) >= 32)
9755 output_operand_lossage ("invalid %%P value");
e2c953b6 9756 else
fb5c67a7 9757 fputs (reg_names[REGNO (XEXP (x, 0))], file);
9878760c
RK		 9758 return;
9759
dfbdccdb
GK		 9760 case 'q':
9761 /* This outputs the logical code corresponding to a boolean
9762 expression. The expression may have one or both operands
39a10a29 9763 negated (if one, only the first one). For condition register
c4ad648e
AM		 9764 logical operations, it will also treat the negated
9765 CR codes as NOTs, but not handle NOTs of them. */
dfbdccdb 9766 {
63bc1d05 9767 const char *const *t = 0;
dfbdccdb
GK		 9768 const char *s;
9769 enum rtx_code code = GET_CODE (x);
9770 static const char * const tbl[3][3] = {
9771 { "and", "andc", "nor" },
9772 { "or", "orc", "nand" },
9773 { "xor", "eqv", "xor" } };
9774
9775 if (code == AND)
9776 t = tbl[0];
9777 else if (code == IOR)
9778 t = tbl[1];
9779 else if (code == XOR)
9780 t = tbl[2];
9781 else
9782 output_operand_lossage ("invalid %%q value");
9783
9784 if (GET_CODE (XEXP (x, 0)) != NOT)
9785 s = t[0];
9786 else
9787 {
9788 if (GET_CODE (XEXP (x, 1)) == NOT)
9789 s = t[2];
9790 else
9791 s = t[1];
9792 }
f676971a 9793
dfbdccdb
GK		 9794 fputs (s, file);
9795 }
9796 return;
9797
2c4a9cff
DE		 9798 case 'Q':
9799 if (TARGET_MFCRF)
3b6ce0af 9800 fputc (',', file);
5efb1046 9801 /* FALLTHRU */
2c4a9cff
DE		 9802 else
9803 return;
9804
9854d9ed
RK		 9805 case 'R':
9806 /* X is a CR register. Print the mask for `mtcrf'. */
9807 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
9808 output_operand_lossage ("invalid %%R value");
9809 else
9ebbca7d 9810 fprintf (file, "%d", 128 >> (REGNO (x) - CR0_REGNO));
9878760c 9811 return;
9854d9ed
RK		 9812
9813 case 's':
9814 /* Low 5 bits of 32 - value */
9815 if (! INT_P (x))
9816 output_operand_lossage ("invalid %%s value");
e2c953b6
DE		 9817 else
9818 fprintf (file, HOST_WIDE_INT_PRINT_DEC, (32 - INT_LOWPART (x)) & 31);
9878760c 9819 return;
9854d9ed 9820
a260abc9 9821 case 'S':
0ba1b2ff 9822 /* PowerPC64 mask position. All 0's is excluded.
a260abc9
DE		 9823 CONST_INT 32-bit mask is considered sign-extended so any
9824 transition must occur within the CONST_INT, not on the boundary. */
b1765bde 9825 if (! mask64_operand (x, DImode))
a260abc9
DE		 9826 output_operand_lossage ("invalid %%S value");
9827
0ba1b2ff 9828 uval = INT_LOWPART (x);
a260abc9 9829
0ba1b2ff 9830 if (uval & 1) /* Clear Left */
a260abc9 9831 {
f099d360
GK		 9832#if HOST_BITS_PER_WIDE_INT > 64
9833 uval &= ((unsigned HOST_WIDE_INT) 1 << 64) - 1;
9834#endif
0ba1b2ff 9835 i = 64;
a260abc9 9836 }
0ba1b2ff 9837 else /* Clear Right */
a260abc9 9838 {
0ba1b2ff 9839 uval = ~uval;
f099d360
GK		 9840#if HOST_BITS_PER_WIDE_INT > 64
9841 uval &= ((unsigned HOST_WIDE_INT) 1 << 64) - 1;
9842#endif
0ba1b2ff 9843 i = 63;
a260abc9 9844 }
0ba1b2ff
AM		 9845 while (uval != 0)
9846 --i, uval >>= 1;
37409796 9847 gcc_assert (i >= 0);
0ba1b2ff
AM		 9848 fprintf (file, "%d", i);
9849 return;
a260abc9 9850
a3170dc6
AH		 9851 case 't':
9852 /* Like 'J' but get to the OVERFLOW/UNORDERED bit. */
37409796 9853 gcc_assert (GET_CODE (x) == REG && GET_MODE (x) == CCmode);
a3170dc6
AH		 9854
9855 /* Bit 3 is OV bit. */
9856 i = 4 * (REGNO (x) - CR0_REGNO) + 3;
9857
9858 /* If we want bit 31, write a shift count of zero, not 32. */
9859 fprintf (file, "%d", i == 31 ? 0 : i + 1);
9860 return;
9861
cccf3bdc
DE		 9862 case 'T':
9863 /* Print the symbolic name of a branch target register. */
9864 if (GET_CODE (x) != REG || (REGNO (x) != LINK_REGISTER_REGNUM
9865 && REGNO (x) != COUNT_REGISTER_REGNUM))
9866 output_operand_lossage ("invalid %%T value");
e2c953b6 9867 else if (REGNO (x) == LINK_REGISTER_REGNUM)
cccf3bdc
DE		 9868 fputs (TARGET_NEW_MNEMONICS ? "lr" : "r", file);
9869 else
9870 fputs ("ctr", file);
9871 return;
9872
9854d9ed 9873 case 'u':
802a0058 9874 /* High-order 16 bits of constant for use in unsigned operand. */
9854d9ed
RK		 9875 if (! INT_P (x))
9876 output_operand_lossage ("invalid %%u value");
e2c953b6 9877 else
f676971a 9878 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
e2c953b6 9879 (INT_LOWPART (x) >> 16) & 0xffff);
9878760c
RK		 9880 return;
9881
802a0058
MM		 9882 case 'v':
9883 /* High-order 16 bits of constant for use in signed operand. */
9884 if (! INT_P (x))
9885 output_operand_lossage ("invalid %%v value");
e2c953b6 9886 else
134c32f6
DE		 9887 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
9888 (INT_LOWPART (x) >> 16) & 0xffff);
9889 return;
802a0058 9890
9854d9ed
RK		 9891 case 'U':
9892 /* Print `u' if this has an auto-increment or auto-decrement. */
9893 if (GET_CODE (x) == MEM
9894 && (GET_CODE (XEXP (x, 0)) == PRE_INC
9895 || GET_CODE (XEXP (x, 0)) == PRE_DEC))
76229ac8 9896 putc ('u', file);
9854d9ed 9897 return;
9878760c 9898
e0cd0770
JC		 9899 case 'V':
9900 /* Print the trap code for this operand. */
9901 switch (GET_CODE (x))
9902 {
9903 case EQ:
9904 fputs ("eq", file); /* 4 */
9905 break;
9906 case NE:
9907 fputs ("ne", file); /* 24 */
9908 break;
9909 case LT:
9910 fputs ("lt", file); /* 16 */
9911 break;
9912 case LE:
9913 fputs ("le", file); /* 20 */
9914 break;
9915 case GT:
9916 fputs ("gt", file); /* 8 */
9917 break;
9918 case GE:
9919 fputs ("ge", file); /* 12 */
9920 break;
9921 case LTU:
9922 fputs ("llt", file); /* 2 */
9923 break;
9924 case LEU:
9925 fputs ("lle", file); /* 6 */
9926 break;
9927 case GTU:
9928 fputs ("lgt", file); /* 1 */
9929 break;
9930 case GEU:
9931 fputs ("lge", file); /* 5 */
9932 break;
9933 default:
37409796 9934 gcc_unreachable ();
e0cd0770
JC		 9935 }
9936 break;
9937
9854d9ed
RK		 9938 case 'w':
9939 /* If constant, low-order 16 bits of constant, signed. Otherwise, write
9940 normally. */
9941 if (INT_P (x))
f676971a 9942 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
5f59ecb7 9943 ((INT_LOWPART (x) & 0xffff) ^ 0x8000) - 0x8000);
9854d9ed
RK		 9944 else
9945 print_operand (file, x, 0);
9878760c
RK		 9946 return;
9947
9854d9ed 9948 case 'W':
e2c953b6 9949 /* MB value for a PowerPC64 rldic operand. */
e2c953b6
DE		 9950 val = (GET_CODE (x) == CONST_INT
9951 ? INTVAL (x) : CONST_DOUBLE_HIGH (x));
9952
9953 if (val < 0)
9954 i = -1;
9854d9ed 9955 else
e2c953b6
DE		 9956 for (i = 0; i < HOST_BITS_PER_WIDE_INT; i++)
9957 if ((val <<= 1) < 0)
9958 break;
9959
9960#if HOST_BITS_PER_WIDE_INT == 32
9961 if (GET_CODE (x) == CONST_INT && i >= 0)
9962 i += 32; /* zero-extend high-part was all 0's */
9963 else if (GET_CODE (x) == CONST_DOUBLE && i == 32)
9964 {
9965 val = CONST_DOUBLE_LOW (x);
9966
37409796
NS		 9967 gcc_assert (val);
9968 if (val < 0)
e2c953b6
DE		 9969 --i;
9970 else
9971 for ( ; i < 64; i++)
9972 if ((val <<= 1) < 0)
9973 break;
9974 }
9975#endif
9976
9977 fprintf (file, "%d", i + 1);
9854d9ed 9978 return;
9878760c 9979
9854d9ed
RK		 9980 case 'X':
9981 if (GET_CODE (x) == MEM
4d588c14 9982 && legitimate_indexed_address_p (XEXP (x, 0), 0))
76229ac8 9983 putc ('x', file);
9854d9ed 9984 return;
9878760c 9985
9854d9ed
RK		 9986 case 'Y':
9987 /* Like 'L', for third word of TImode */
9988 if (GET_CODE (x) == REG)
fb5c67a7 9989 fputs (reg_names[REGNO (x) + 2], file);
9854d9ed 9990 else if (GET_CODE (x) == MEM)
9878760c 9991 {
9854d9ed
RK		 9992 if (GET_CODE (XEXP (x, 0)) == PRE_INC
9993 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
a54d04b7 9994 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 8));
9854d9ed 9995 else
d7624dc0 9996 output_address (XEXP (adjust_address_nv (x, SImode, 8), 0));
ba5e43aa 9997 if (small_data_operand (x, GET_MODE (x)))
8fbd2dc7
MM		 9998 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
9999 reg_names[SMALL_DATA_REG]);
9878760c
RK		 10000 }
10001 return;
f676971a 10002
9878760c 10003 case 'z':
b4ac57ab
RS		 10004 /* X is a SYMBOL_REF. Write out the name preceded by a
10005 period and without any trailing data in brackets. Used for function
4d30c363
MM		 10006 names. If we are configured for System V (or the embedded ABI) on
10007 the PowerPC, do not emit the period, since those systems do not use
10008 TOCs and the like. */
37409796 10009 gcc_assert (GET_CODE (x) == SYMBOL_REF);
9878760c 10010
c4ad648e
AM		 10011 /* Mark the decl as referenced so that cgraph will output the
10012 function. */
9bf6462a 10013 if (SYMBOL_REF_DECL (x))
c4ad648e 10014 mark_decl_referenced (SYMBOL_REF_DECL (x));
9bf6462a 10015
85b776df 10016 /* For macho, check to see if we need a stub. */
f9da97f0
AP		 10017 if (TARGET_MACHO)
10018 {
10019 const char *name = XSTR (x, 0);
a031e781 10020#if TARGET_MACHO
3b48085e 10021 if (MACHOPIC_INDIRECT
11abc112
MM		 10022 && machopic_classify_symbol (x) == MACHOPIC_UNDEFINED_FUNCTION)
10023 name = machopic_indirection_name (x, /*stub_p=*/true);
f9da97f0
AP		 10024#endif
10025 assemble_name (file, name);
10026 }
85b776df 10027 else if (!DOT_SYMBOLS)
9739c90c 10028 assemble_name (file, XSTR (x, 0));
85b776df
AM		 10029 else
10030 rs6000_output_function_entry (file, XSTR (x, 0));
9878760c
RK		 10031 return;
10032
9854d9ed
RK		 10033 case 'Z':
10034 /* Like 'L', for last word of TImode. */
10035 if (GET_CODE (x) == REG)
fb5c67a7 10036 fputs (reg_names[REGNO (x) + 3], file);
9854d9ed
RK		 10037 else if (GET_CODE (x) == MEM)
10038 {
10039 if (GET_CODE (XEXP (x, 0)) == PRE_INC
10040 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
a54d04b7 10041 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 12));
9854d9ed 10042 else
d7624dc0 10043 output_address (XEXP (adjust_address_nv (x, SImode, 12), 0));
ba5e43aa 10044 if (small_data_operand (x, GET_MODE (x)))
8fbd2dc7
MM		 10045 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
10046 reg_names[SMALL_DATA_REG]);
9854d9ed 10047 }
5c23c401 10048 return;
0ac081f6 10049
a3170dc6 10050 /* Print AltiVec or SPE memory operand. */
0ac081f6
AH		 10051 case 'y':
10052 {
10053 rtx tmp;
10054
37409796 10055 gcc_assert (GET_CODE (x) == MEM);
0ac081f6
AH		 10056
10057 tmp = XEXP (x, 0);
10058
993f19a8 10059 if (TARGET_E500)
a3170dc6
AH		 10060 {
10061 /* Handle [reg]. */
10062 if (GET_CODE (tmp) == REG)
10063 {
10064 fprintf (file, "0(%s)", reg_names[REGNO (tmp)]);
10065 break;
10066 }
10067 /* Handle [reg+UIMM]. */
10068 else if (GET_CODE (tmp) == PLUS &&
10069 GET_CODE (XEXP (tmp, 1)) == CONST_INT)
10070 {
10071 int x;
10072
37409796 10073 gcc_assert (GET_CODE (XEXP (tmp, 0)) == REG);
a3170dc6
AH		 10074
10075 x = INTVAL (XEXP (tmp, 1));
10076 fprintf (file, "%d(%s)", x, reg_names[REGNO (XEXP (tmp, 0))]);
10077 break;
10078 }
10079
10080 /* Fall through. Must be [reg+reg]. */
10081 }
850e8d3d
DN		 10082 if (TARGET_ALTIVEC
10083 && GET_CODE (tmp) == AND
10084 && GET_CODE (XEXP (tmp, 1)) == CONST_INT
10085 && INTVAL (XEXP (tmp, 1)) == -16)
10086 tmp = XEXP (tmp, 0);
0ac081f6 10087 if (GET_CODE (tmp) == REG)
c62f2db5 10088 fprintf (file, "0,%s", reg_names[REGNO (tmp)]);
37409796 10089 else
0ac081f6 10090 {
37409796
NS		 10091 gcc_assert (GET_CODE (tmp) == PLUS
10092 && GET_CODE (XEXP (tmp, 1)) == REG);
10093
0ac081f6
AH		 10094 if (REGNO (XEXP (tmp, 0)) == 0)
10095 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 1)) ],
10096 reg_names[ REGNO (XEXP (tmp, 0)) ]);
10097 else
10098 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 0)) ],
10099 reg_names[ REGNO (XEXP (tmp, 1)) ]);
10100 }
0ac081f6
AH		 10101 break;
10102 }
f676971a 10103
9878760c
RK		 10104 case 0:
10105 if (GET_CODE (x) == REG)
10106 fprintf (file, "%s", reg_names[REGNO (x)]);
10107 else if (GET_CODE (x) == MEM)
10108 {
10109 /* We need to handle PRE_INC and PRE_DEC here, since we need to
10110 know the width from the mode. */
10111 if (GET_CODE (XEXP (x, 0)) == PRE_INC)
79ba6d34
MM		 10112 fprintf (file, "%d(%s)", GET_MODE_SIZE (GET_MODE (x)),
10113 reg_names[REGNO (XEXP (XEXP (x, 0), 0))]);
9878760c 10114 else if (GET_CODE (XEXP (x, 0)) == PRE_DEC)
79ba6d34
MM		 10115 fprintf (file, "%d(%s)", - GET_MODE_SIZE (GET_MODE (x)),
10116 reg_names[REGNO (XEXP (XEXP (x, 0), 0))]);
9878760c 10117 else
a54d04b7 10118 output_address (XEXP (x, 0));
9878760c
RK		 10119 }
10120 else
a54d04b7 10121 output_addr_const (file, x);
a85d226b 10122 return;
9878760c 10123
c4501e62
JJ		 10124 case '&':
10125 assemble_name (file, rs6000_get_some_local_dynamic_name ());
10126 return;
10127
9878760c
RK		 10128 default:
10129 output_operand_lossage ("invalid %%xn code");
10130 }
10131}
10132\f
10133/* Print the address of an operand. */
10134
10135void
a2369ed3 10136print_operand_address (FILE *file, rtx x)
9878760c
RK		 10137{
10138 if (GET_CODE (x) == REG)
4697a36c 10139 fprintf (file, "0(%s)", reg_names[ REGNO (x) ]);
9ebbca7d
GK		 10140 else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST
10141 || GET_CODE (x) == LABEL_REF)
9878760c
RK		 10142 {
10143 output_addr_const (file, x);
ba5e43aa 10144 if (small_data_operand (x, GET_MODE (x)))
8fbd2dc7
MM		 10145 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
10146 reg_names[SMALL_DATA_REG]);
37409796
NS		 10147 else
10148 gcc_assert (!TARGET_TOC);
9878760c
RK		 10149 }
10150 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == REG)
10151 {
10152 if (REGNO (XEXP (x, 0)) == 0)
4697a36c
MM		 10153 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 1)) ],
10154 reg_names[ REGNO (XEXP (x, 0)) ]);
9878760c 10155 else
4697a36c
MM		 10156 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 0)) ],
10157 reg_names[ REGNO (XEXP (x, 1)) ]);
9878760c
RK		 10158 }
10159 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT)
4a0a75dd
KG		 10160 fprintf (file, HOST_WIDE_INT_PRINT_DEC "(%s)",
10161 INTVAL (XEXP (x, 1)), reg_names[ REGNO (XEXP (x, 0)) ]);
3cb999d8
DE		 10162#if TARGET_ELF
10163 else if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 0)) == REG
c4ad648e 10164 && CONSTANT_P (XEXP (x, 1)))
4697a36c
MM		 10165 {
10166 output_addr_const (file, XEXP (x, 1));
10167 fprintf (file, "@l(%s)", reg_names[ REGNO (XEXP (x, 0)) ]);
10168 }
c859cda6
DJ		 10169#endif
10170#if TARGET_MACHO
10171 else if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 0)) == REG
c4ad648e 10172 && CONSTANT_P (XEXP (x, 1)))
c859cda6
DJ		 10173 {
10174 fprintf (file, "lo16(");
10175 output_addr_const (file, XEXP (x, 1));
10176 fprintf (file, ")(%s)", reg_names[ REGNO (XEXP (x, 0)) ]);
10177 }
3cb999d8 10178#endif
4d588c14 10179 else if (legitimate_constant_pool_address_p (x))
9ebbca7d 10180 {
2bfcf297 10181 if (TARGET_AIX && (!TARGET_ELF || !TARGET_MINIMAL_TOC))
9ebbca7d 10182 {
2bfcf297
DB		 10183 rtx contains_minus = XEXP (x, 1);
10184 rtx minus, symref;
10185 const char *name;
f676971a 10186
9ebbca7d 10187 /* Find the (minus (sym) (toc)) buried in X, and temporarily
a4f6c312 10188 turn it into (sym) for output_addr_const. */
9ebbca7d
GK		 10189 while (GET_CODE (XEXP (contains_minus, 0)) != MINUS)
10190 contains_minus = XEXP (contains_minus, 0);
10191
2bfcf297
DB		 10192 minus = XEXP (contains_minus, 0);
10193 symref = XEXP (minus, 0);
10194 XEXP (contains_minus, 0) = symref;
10195 if (TARGET_ELF)
10196 {
10197 char *newname;
10198
10199 name = XSTR (symref, 0);
10200 newname = alloca (strlen (name) + sizeof ("@toc"));
10201 strcpy (newname, name);
10202 strcat (newname, "@toc");
10203 XSTR (symref, 0) = newname;
10204 }
10205 output_addr_const (file, XEXP (x, 1));
10206 if (TARGET_ELF)
10207 XSTR (symref, 0) = name;
9ebbca7d
GK		 10208 XEXP (contains_minus, 0) = minus;
10209 }
10210 else
10211 output_addr_const (file, XEXP (x, 1));
10212
10213 fprintf (file, "(%s)", reg_names[REGNO (XEXP (x, 0))]);
10214 }
9878760c 10215 else
37409796 10216 gcc_unreachable ();
9878760c
RK		 10217}
10218\f
88cad84b 10219/* Target hook for assembling integer objects. The PowerPC version has
301d03af
RS		 10220 to handle fixup entries for relocatable code if RELOCATABLE_NEEDS_FIXUP
10221 is defined. It also needs to handle DI-mode objects on 64-bit
10222 targets. */
10223
10224static bool
a2369ed3 10225rs6000_assemble_integer (rtx x, unsigned int size, int aligned_p)
301d03af 10226{
f4f4921e 10227#ifdef RELOCATABLE_NEEDS_FIXUP
301d03af 10228 /* Special handling for SI values. */
84dcde01 10229 if (RELOCATABLE_NEEDS_FIXUP && size == 4 && aligned_p)
301d03af 10230 {
a2369ed3 10231 extern int in_toc_section (void);
301d03af 10232 static int recurse = 0;
f676971a 10233
301d03af
RS		 10234 /* For -mrelocatable, we mark all addresses that need to be fixed up
10235 in the .fixup section. */
10236 if (TARGET_RELOCATABLE
10237 && !in_toc_section ()
10238 && !in_text_section ()
642af3be 10239 && !in_unlikely_text_section ()
301d03af
RS		 10240 && !recurse
10241 && GET_CODE (x) != CONST_INT
10242 && GET_CODE (x) != CONST_DOUBLE
10243 && CONSTANT_P (x))
10244 {
10245 char buf[256];
10246
10247 recurse = 1;
10248 ASM_GENERATE_INTERNAL_LABEL (buf, "LCP", fixuplabelno);
10249 fixuplabelno++;
10250 ASM_OUTPUT_LABEL (asm_out_file, buf);
10251 fprintf (asm_out_file, "\t.long\t(");
10252 output_addr_const (asm_out_file, x);
10253 fprintf (asm_out_file, ")@fixup\n");
10254 fprintf (asm_out_file, "\t.section\t\".fixup\",\"aw\"\n");
10255 ASM_OUTPUT_ALIGN (asm_out_file, 2);
10256 fprintf (asm_out_file, "\t.long\t");
10257 assemble_name (asm_out_file, buf);
10258 fprintf (asm_out_file, "\n\t.previous\n");
10259 recurse = 0;
10260 return true;
10261 }
10262 /* Remove initial .'s to turn a -mcall-aixdesc function
10263 address into the address of the descriptor, not the function
10264 itself. */
10265 else if (GET_CODE (x) == SYMBOL_REF
10266 && XSTR (x, 0)[0] == '.'
10267 && DEFAULT_ABI == ABI_AIX)
10268 {
10269 const char *name = XSTR (x, 0);
10270 while (*name == '.')
10271 name++;
10272
10273 fprintf (asm_out_file, "\t.long\t%s\n", name);
10274 return true;
10275 }
10276 }
f4f4921e 10277#endif /* RELOCATABLE_NEEDS_FIXUP */
301d03af
RS		 10278 return default_assemble_integer (x, size, aligned_p);
10279}
93638d7a
AM		 10280
10281#ifdef HAVE_GAS_HIDDEN
10282/* Emit an assembler directive to set symbol visibility for DECL to
10283 VISIBILITY_TYPE. */
10284
5add3202 10285static void
a2369ed3 10286rs6000_assemble_visibility (tree decl, int vis)
93638d7a 10287{
93638d7a
AM		 10288 /* Functions need to have their entry point symbol visibility set as
10289 well as their descriptor symbol visibility. */
85b776df
AM		 10290 if (DEFAULT_ABI == ABI_AIX
10291 && DOT_SYMBOLS
10292 && TREE_CODE (decl) == FUNCTION_DECL)
93638d7a 10293 {
25fdb4dc 10294 static const char * const visibility_types[] = {
c4ad648e 10295 NULL, "internal", "hidden", "protected"
25fdb4dc
RH		 10296 };
10297
10298 const char *name, *type;
93638d7a
AM		 10299
10300 name = ((* targetm.strip_name_encoding)
10301 (IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl))));
25fdb4dc 10302 type = visibility_types[vis];
93638d7a 10303
25fdb4dc
RH		 10304 fprintf (asm_out_file, "\t.%s\t%s\n", type, name);
10305 fprintf (asm_out_file, "\t.%s\t.%s\n", type, name);
93638d7a 10306 }
25fdb4dc
RH		 10307 else
10308 default_assemble_visibility (decl, vis);
93638d7a
AM		 10309}
10310#endif
301d03af 10311\f
39a10a29 10312enum rtx_code
a2369ed3 10313rs6000_reverse_condition (enum machine_mode mode, enum rtx_code code)
39a10a29
GK		 10314{
10315 /* Reversal of FP compares takes care -- an ordered compare
10316 becomes an unordered compare and vice versa. */
f676971a 10317 if (mode == CCFPmode
bc9ec0e0
GK		 10318 && (!flag_finite_math_only
10319 || code == UNLT || code == UNLE || code == UNGT || code == UNGE
10320 || code == UNEQ || code == LTGT))
bab6226b 10321 return reverse_condition_maybe_unordered (code);
39a10a29 10322 else
bab6226b 10323 return reverse_condition (code);
39a10a29
GK		 10324}
10325
39a10a29
GK		 10326/* Generate a compare for CODE. Return a brand-new rtx that
10327 represents the result of the compare. */
a4f6c312 10328
39a10a29 10329static rtx
a2369ed3 10330rs6000_generate_compare (enum rtx_code code)
39a10a29
GK		 10331{
10332 enum machine_mode comp_mode;
10333 rtx compare_result;
10334
10335 if (rs6000_compare_fp_p)
10336 comp_mode = CCFPmode;
10337 else if (code == GTU || code == LTU
c4ad648e 10338 || code == GEU || code == LEU)
39a10a29 10339 comp_mode = CCUNSmode;
60934f9c
NS		 10340 else if ((code == EQ || code == NE)
10341 && GET_CODE (rs6000_compare_op0) == SUBREG
10342 && GET_CODE (rs6000_compare_op1) == SUBREG
10343 && SUBREG_PROMOTED_UNSIGNED_P (rs6000_compare_op0)
10344 && SUBREG_PROMOTED_UNSIGNED_P (rs6000_compare_op1))
10345 /* These are unsigned values, perhaps there will be a later
10346 ordering compare that can be shared with this one.
10347 Unfortunately we cannot detect the signedness of the operands
10348 for non-subregs. */
10349 comp_mode = CCUNSmode;
39a10a29
GK		 10350 else
10351 comp_mode = CCmode;
10352
10353 /* First, the compare. */
10354 compare_result = gen_reg_rtx (comp_mode);
a3170dc6
AH		 10355
10356 /* SPE FP compare instructions on the GPRs. Yuck! */
993f19a8
AH		 10357 if ((TARGET_E500 && !TARGET_FPRS && TARGET_HARD_FLOAT)
10358 && rs6000_compare_fp_p)
a3170dc6 10359 {
64022b5d 10360 rtx cmp, or_result, compare_result2;
4d4cbc0e
AH		 10361 enum machine_mode op_mode = GET_MODE (rs6000_compare_op0);
10362
10363 if (op_mode == VOIDmode)
10364 op_mode = GET_MODE (rs6000_compare_op1);
a3170dc6 10365
423c1189
AH		 10366 /* Note: The E500 comparison instructions set the GT bit (x +
10367 1), on success. This explains the mess. */
10368
a3170dc6
AH		 10369 switch (code)
10370 {
423c1189 10371 case EQ: case UNEQ: case NE: case LTGT:
37409796
NS		 10372 switch (op_mode)
10373 {
10374 case SFmode:
10375 cmp = flag_unsafe_math_optimizations
10376 ? gen_tstsfeq_gpr (compare_result, rs6000_compare_op0,
10377 rs6000_compare_op1)
10378 : gen_cmpsfeq_gpr (compare_result, rs6000_compare_op0,
10379 rs6000_compare_op1);
10380 break;
10381
10382 case DFmode:
10383 cmp = flag_unsafe_math_optimizations
10384 ? gen_tstdfeq_gpr (compare_result, rs6000_compare_op0,
10385 rs6000_compare_op1)
10386 : gen_cmpdfeq_gpr (compare_result, rs6000_compare_op0,
10387 rs6000_compare_op1);
10388 break;
10389
10390 default:
10391 gcc_unreachable ();
10392 }
a3170dc6 10393 break;
37409796 10394
423c1189 10395 case GT: case GTU: case UNGT: case UNGE: case GE: case GEU:
37409796
NS		 10396 switch (op_mode)
10397 {
10398 case SFmode:
10399 cmp = flag_unsafe_math_optimizations
10400 ? gen_tstsfgt_gpr (compare_result, rs6000_compare_op0,
10401 rs6000_compare_op1)
10402 : gen_cmpsfgt_gpr (compare_result, rs6000_compare_op0,
10403 rs6000_compare_op1);
10404 break;
10405
10406 case DFmode:
10407 cmp = flag_unsafe_math_optimizations
10408 ? gen_tstdfgt_gpr (compare_result, rs6000_compare_op0,
10409 rs6000_compare_op1)
10410 : gen_cmpdfgt_gpr (compare_result, rs6000_compare_op0,
10411 rs6000_compare_op1);
10412 break;
10413
10414 default:
10415 gcc_unreachable ();
10416 }
a3170dc6 10417 break;
37409796 10418
423c1189 10419 case LT: case LTU: case UNLT: case UNLE: case LE: case LEU:
37409796
NS		 10420 switch (op_mode)
10421 {
10422 case SFmode:
10423 cmp = flag_unsafe_math_optimizations
10424 ? gen_tstsflt_gpr (compare_result, rs6000_compare_op0,
10425 rs6000_compare_op1)
10426 : gen_cmpsflt_gpr (compare_result, rs6000_compare_op0,
10427 rs6000_compare_op1);
10428 break;
10429
10430 case DFmode:
10431 cmp = flag_unsafe_math_optimizations
10432 ? gen_tstdflt_gpr (compare_result, rs6000_compare_op0,
10433 rs6000_compare_op1)
10434 : gen_cmpdflt_gpr (compare_result, rs6000_compare_op0,
10435 rs6000_compare_op1);
10436 break;
10437
10438 default:
10439 gcc_unreachable ();
10440 }
a3170dc6 10441 break;
4d4cbc0e 10442 default:
37409796 10443 gcc_unreachable ();
a3170dc6
AH		 10444 }
10445
10446 /* Synthesize LE and GE from LT/GT || EQ. */
10447 if (code == LE || code == GE || code == LEU || code == GEU)
10448 {
a3170dc6
AH		 10449 emit_insn (cmp);
10450
10451 switch (code)
10452 {
10453 case LE: code = LT; break;
10454 case GE: code = GT; break;
10455 case LEU: code = LT; break;
10456 case GEU: code = GT; break;
37409796 10457 default: gcc_unreachable ();
a3170dc6
AH		 10458 }
10459
a3170dc6
AH		 10460 compare_result2 = gen_reg_rtx (CCFPmode);
10461
10462 /* Do the EQ. */
37409796
NS		 10463 switch (op_mode)
10464 {
10465 case SFmode:
10466 cmp = flag_unsafe_math_optimizations
10467 ? gen_tstsfeq_gpr (compare_result2, rs6000_compare_op0,
10468 rs6000_compare_op1)
10469 : gen_cmpsfeq_gpr (compare_result2, rs6000_compare_op0,
10470 rs6000_compare_op1);
10471 break;
10472
10473 case DFmode:
10474 cmp = flag_unsafe_math_optimizations
10475 ? gen_tstdfeq_gpr (compare_result2, rs6000_compare_op0,
10476 rs6000_compare_op1)
10477 : gen_cmpdfeq_gpr (compare_result2, rs6000_compare_op0,
10478 rs6000_compare_op1);
10479 break;
10480
10481 default:
10482 gcc_unreachable ();
10483 }
a3170dc6
AH		 10484 emit_insn (cmp);
10485
a3170dc6 10486 /* OR them together. */
64022b5d
AH		 10487 or_result = gen_reg_rtx (CCFPmode);
10488 cmp = gen_e500_cr_ior_compare (or_result, compare_result,
10489 compare_result2);
a3170dc6
AH		 10490 compare_result = or_result;
10491 code = EQ;
10492 }
10493 else
10494 {
a3170dc6 10495 if (code == NE || code == LTGT)
a3170dc6 10496 code = NE;
423c1189
AH		 10497 else
10498 code = EQ;
a3170dc6
AH		 10499 }
10500
10501 emit_insn (cmp);
10502 }
10503 else
de17c25f
DE		 10504 {
10505 /* Generate XLC-compatible TFmode compare as PARALLEL with extra
10506 CLOBBERs to match cmptf_internal2 pattern. */
10507 if (comp_mode == CCFPmode && TARGET_XL_COMPAT
10508 && GET_MODE (rs6000_compare_op0) == TFmode
10509 && (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
10510 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128)
10511 emit_insn (gen_rtx_PARALLEL (VOIDmode,
10512 gen_rtvec (9,
10513 gen_rtx_SET (VOIDmode,
10514 compare_result,
10515 gen_rtx_COMPARE (comp_mode,
10516 rs6000_compare_op0,
10517 rs6000_compare_op1)),
10518 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
10519 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
10520 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
10521 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
10522 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
10523 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
10524 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
10525 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)))));
10526 else
10527 emit_insn (gen_rtx_SET (VOIDmode, compare_result,
10528 gen_rtx_COMPARE (comp_mode,
10529 rs6000_compare_op0,
10530 rs6000_compare_op1)));
10531 }
f676971a 10532
ca5adc63 10533 /* Some kinds of FP comparisons need an OR operation;
e7108df9 10534 under flag_finite_math_only we don't bother. */
39a10a29 10535 if (rs6000_compare_fp_p
e7108df9
DE		 10536 && !flag_finite_math_only
10537 && !(TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS)
39a10a29
GK		 10538 && (code == LE || code == GE
10539 || code == UNEQ || code == LTGT
10540 || code == UNGT || code == UNLT))
10541 {
10542 enum rtx_code or1, or2;
10543 rtx or1_rtx, or2_rtx, compare2_rtx;
10544 rtx or_result = gen_reg_rtx (CCEQmode);
f676971a 10545
39a10a29
GK		 10546 switch (code)
10547 {
10548 case LE: or1 = LT; or2 = EQ; break;
10549 case GE: or1 = GT; or2 = EQ; break;
10550 case UNEQ: or1 = UNORDERED; or2 = EQ; break;
10551 case LTGT: or1 = LT; or2 = GT; break;
10552 case UNGT: or1 = UNORDERED; or2 = GT; break;
10553 case UNLT: or1 = UNORDERED; or2 = LT; break;
37409796 10554 default: gcc_unreachable ();
39a10a29
GK		 10555 }
10556 validate_condition_mode (or1, comp_mode);
10557 validate_condition_mode (or2, comp_mode);
1c563bed
KH		 10558 or1_rtx = gen_rtx_fmt_ee (or1, SImode, compare_result, const0_rtx);
10559 or2_rtx = gen_rtx_fmt_ee (or2, SImode, compare_result, const0_rtx);
39a10a29
GK		 10560 compare2_rtx = gen_rtx_COMPARE (CCEQmode,
10561 gen_rtx_IOR (SImode, or1_rtx, or2_rtx),
10562 const_true_rtx);
10563 emit_insn (gen_rtx_SET (VOIDmode, or_result, compare2_rtx));
10564
10565 compare_result = or_result;
10566 code = EQ;
10567 }
10568
10569 validate_condition_mode (code, GET_MODE (compare_result));
f676971a 10570
1c563bed 10571 return gen_rtx_fmt_ee (code, VOIDmode, compare_result, const0_rtx);
39a10a29
GK		 10572}
10573
10574
10575/* Emit the RTL for an sCOND pattern. */
10576
10577void
a2369ed3 10578rs6000_emit_sCOND (enum rtx_code code, rtx result)
39a10a29
GK		 10579{
10580 rtx condition_rtx;
10581 enum machine_mode op_mode;
b7053a3f 10582 enum rtx_code cond_code;
39a10a29
GK		 10583
10584 condition_rtx = rs6000_generate_compare (code);
b7053a3f
GK		 10585 cond_code = GET_CODE (condition_rtx);
10586
423c1189
AH		 10587 if (TARGET_E500 && rs6000_compare_fp_p
10588 && !TARGET_FPRS && TARGET_HARD_FLOAT)
10589 {
10590 rtx t;
10591
10592 PUT_MODE (condition_rtx, SImode);
10593 t = XEXP (condition_rtx, 0);
10594
37409796 10595 gcc_assert (cond_code == NE || cond_code == EQ);
423c1189
AH		 10596
10597 if (cond_code == NE)
64022b5d 10598 emit_insn (gen_e500_flip_gt_bit (t, t));
423c1189 10599
64022b5d 10600 emit_insn (gen_move_from_CR_gt_bit (result, t));
423c1189
AH		 10601 return;
10602 }
10603
b7053a3f
GK		 10604 if (cond_code == NE
10605 || cond_code == GE || cond_code == LE
10606 || cond_code == GEU || cond_code == LEU
10607 || cond_code == ORDERED || cond_code == UNGE || cond_code == UNLE)
10608 {
10609 rtx not_result = gen_reg_rtx (CCEQmode);
10610 rtx not_op, rev_cond_rtx;
10611 enum machine_mode cc_mode;
f676971a 10612
b7053a3f
GK		 10613 cc_mode = GET_MODE (XEXP (condition_rtx, 0));
10614
1c563bed 10615 rev_cond_rtx = gen_rtx_fmt_ee (rs6000_reverse_condition (cc_mode, cond_code),
0f4c242b 10616 SImode, XEXP (condition_rtx, 0), const0_rtx);
b7053a3f
GK		 10617 not_op = gen_rtx_COMPARE (CCEQmode, rev_cond_rtx, const0_rtx);
10618 emit_insn (gen_rtx_SET (VOIDmode, not_result, not_op));
10619 condition_rtx = gen_rtx_EQ (VOIDmode, not_result, const0_rtx);
10620 }
39a10a29
GK		 10621
10622 op_mode = GET_MODE (rs6000_compare_op0);
10623 if (op_mode == VOIDmode)
10624 op_mode = GET_MODE (rs6000_compare_op1);
10625
10626 if (TARGET_POWERPC64 && (op_mode == DImode || rs6000_compare_fp_p))
10627 {
10628 PUT_MODE (condition_rtx, DImode);
10629 convert_move (result, condition_rtx, 0);
10630 }
10631 else
10632 {
10633 PUT_MODE (condition_rtx, SImode);
10634 emit_insn (gen_rtx_SET (VOIDmode, result, condition_rtx));
10635 }
10636}
10637
39a10a29
GK		 10638/* Emit a branch of kind CODE to location LOC. */
10639
10640void
a2369ed3 10641rs6000_emit_cbranch (enum rtx_code code, rtx loc)
39a10a29
GK		 10642{
10643 rtx condition_rtx, loc_ref;
10644
10645 condition_rtx = rs6000_generate_compare (code);
10646 loc_ref = gen_rtx_LABEL_REF (VOIDmode, loc);
10647 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
10648 gen_rtx_IF_THEN_ELSE (VOIDmode, condition_rtx,
10649 loc_ref, pc_rtx)));
10650}
10651
12a4e8c5
GK		 10652/* Return the string to output a conditional branch to LABEL, which is
10653 the operand number of the label, or -1 if the branch is really a
f676971a 10654 conditional return.
12a4e8c5
GK		 10655
10656 OP is the conditional expression. XEXP (OP, 0) is assumed to be a
10657 condition code register and its mode specifies what kind of
10658 comparison we made.
10659
a0ab749a 10660 REVERSED is nonzero if we should reverse the sense of the comparison.
12a4e8c5
GK		 10661
10662 INSN is the insn. */
10663
10664char *
a2369ed3 10665output_cbranch (rtx op, const char *label, int reversed, rtx insn)
12a4e8c5
GK		 10666{
10667 static char string[64];
10668 enum rtx_code code = GET_CODE (op);
10669 rtx cc_reg = XEXP (op, 0);
10670 enum machine_mode mode = GET_MODE (cc_reg);
10671 int cc_regno = REGNO (cc_reg) - CR0_REGNO;
39a10a29 10672 int need_longbranch = label != NULL && get_attr_length (insn) == 8;
12a4e8c5
GK		 10673 int really_reversed = reversed ^ need_longbranch;
10674 char *s = string;
10675 const char *ccode;
10676 const char *pred;
10677 rtx note;
10678
39a10a29
GK		 10679 validate_condition_mode (code, mode);
10680
10681 /* Work out which way this really branches. We could use
10682 reverse_condition_maybe_unordered here always but this
10683 makes the resulting assembler clearer. */
12a4e8c5 10684 if (really_reversed)
de40e1df
DJ		 10685 {
10686 /* Reversal of FP compares takes care -- an ordered compare
10687 becomes an unordered compare and vice versa. */
10688 if (mode == CCFPmode)
10689 code = reverse_condition_maybe_unordered (code);
10690 else
10691 code = reverse_condition (code);
10692 }
12a4e8c5 10693
993f19a8 10694 if ((TARGET_E500 && !TARGET_FPRS && TARGET_HARD_FLOAT) && mode == CCFPmode)
a3170dc6
AH		 10695 {
10696 /* The efscmp/tst* instructions twiddle bit 2, which maps nicely
10697 to the GT bit. */
37409796
NS		 10698 switch (code)
10699 {
10700 case EQ:
10701 /* Opposite of GT. */
10702 code = GT;
10703 break;
10704
10705 case NE:
10706 code = UNLE;
10707 break;
10708
10709 default:
10710 gcc_unreachable ();
10711 }
a3170dc6
AH		 10712 }
10713
39a10a29 10714 switch (code)
12a4e8c5
GK		 10715 {
10716 /* Not all of these are actually distinct opcodes, but
10717 we distinguish them for clarity of the resulting assembler. */
50a0b056
GK		 10718 case NE: case LTGT:
10719 ccode = "ne"; break;
10720 case EQ: case UNEQ:
10721 ccode = "eq"; break;
f676971a 10722 case GE: case GEU:
50a0b056 10723 ccode = "ge"; break;
f676971a 10724 case GT: case GTU: case UNGT:
50a0b056 10725 ccode = "gt"; break;
f676971a 10726 case LE: case LEU:
50a0b056 10727 ccode = "le"; break;
f676971a 10728 case LT: case LTU: case UNLT:
50a0b056 10729 ccode = "lt"; break;
12a4e8c5
GK		 10730 case UNORDERED: ccode = "un"; break;
10731 case ORDERED: ccode = "nu"; break;
10732 case UNGE: ccode = "nl"; break;
10733 case UNLE: ccode = "ng"; break;
10734 default:
37409796 10735 gcc_unreachable ();
12a4e8c5 10736 }
f676971a
EC		 10737
10738 /* Maybe we have a guess as to how likely the branch is.
94a54f47 10739 The old mnemonics don't have a way to specify this information. */
f4857b9b 10740 pred = "";
12a4e8c5
GK		 10741 note = find_reg_note (insn, REG_BR_PROB, NULL_RTX);
10742 if (note != NULL_RTX)
10743 {
10744 /* PROB is the difference from 50%. */
10745 int prob = INTVAL (XEXP (note, 0)) - REG_BR_PROB_BASE / 2;
f4857b9b
AM		 10746
10747 /* Only hint for highly probable/improbable branches on newer
10748 cpus as static prediction overrides processor dynamic
10749 prediction. For older cpus we may as well always hint, but
10750 assume not taken for branches that are very close to 50% as a
10751 mispredicted taken branch is more expensive than a
f676971a 10752 mispredicted not-taken branch. */
ec507f2d 10753 if (rs6000_always_hint
f4857b9b
AM		 10754 || abs (prob) > REG_BR_PROB_BASE / 100 * 48)
10755 {
10756 if (abs (prob) > REG_BR_PROB_BASE / 20
10757 && ((prob > 0) ^ need_longbranch))
c4ad648e 10758 pred = "+";
f4857b9b
AM		 10759 else
10760 pred = "-";
10761 }
12a4e8c5 10762 }
12a4e8c5
GK		 10763
10764 if (label == NULL)
94a54f47 10765 s += sprintf (s, "{b%sr|b%slr%s} ", ccode, ccode, pred);
12a4e8c5 10766 else
94a54f47 10767 s += sprintf (s, "{b%s|b%s%s} ", ccode, ccode, pred);
12a4e8c5 10768
37c67319 10769 /* We need to escape any '%' characters in the reg_names string.
a3c9585f 10770 Assume they'd only be the first character.... */
37c67319
GK		 10771 if (reg_names[cc_regno + CR0_REGNO][0] == '%')
10772 *s++ = '%';
94a54f47 10773 s += sprintf (s, "%s", reg_names[cc_regno + CR0_REGNO]);
12a4e8c5
GK		 10774
10775 if (label != NULL)
10776 {
10777 /* If the branch distance was too far, we may have to use an
10778 unconditional branch to go the distance. */
10779 if (need_longbranch)
44518ddd 10780 s += sprintf (s, ",$+8\n\tb %s", label);
12a4e8c5
GK		 10781 else
10782 s += sprintf (s, ",%s", label);
10783 }
10784
10785 return string;
10786}
50a0b056 10787
64022b5d 10788/* Return the string to flip the GT bit on a CR. */
423c1189 10789char *
64022b5d 10790output_e500_flip_gt_bit (rtx dst, rtx src)
423c1189
AH		 10791{
10792 static char string[64];
10793 int a, b;
10794
37409796
NS		 10795 gcc_assert (GET_CODE (dst) == REG && CR_REGNO_P (REGNO (dst))
10796 && GET_CODE (src) == REG && CR_REGNO_P (REGNO (src)));
423c1189 10797
64022b5d
AH		 10798 /* GT bit. */
10799 a = 4 * (REGNO (dst) - CR0_REGNO) + 1;
10800 b = 4 * (REGNO (src) - CR0_REGNO) + 1;
423c1189
AH		 10801
10802 sprintf (string, "crnot %d,%d", a, b);
10803 return string;
10804}
10805
21213b4c
DP		 10806/* Return insn index for the vector compare instruction for given CODE,
10807 and DEST_MODE, OP_MODE. Return INSN_NOT_AVAILABLE if valid insn is
10808 not available. */
10809
10810static int
94ff898d 10811get_vec_cmp_insn (enum rtx_code code,
21213b4c
DP		 10812 enum machine_mode dest_mode,
10813 enum machine_mode op_mode)
10814{
10815 if (!TARGET_ALTIVEC)
10816 return INSN_NOT_AVAILABLE;
10817
10818 switch (code)
10819 {
10820 case EQ:
10821 if (dest_mode == V16QImode && op_mode == V16QImode)
10822 return UNSPEC_VCMPEQUB;
10823 if (dest_mode == V8HImode && op_mode == V8HImode)
10824 return UNSPEC_VCMPEQUH;
10825 if (dest_mode == V4SImode && op_mode == V4SImode)
10826 return UNSPEC_VCMPEQUW;
10827 if (dest_mode == V4SImode && op_mode == V4SFmode)
10828 return UNSPEC_VCMPEQFP;
10829 break;
10830 case GE:
10831 if (dest_mode == V4SImode && op_mode == V4SFmode)
10832 return UNSPEC_VCMPGEFP;
10833 case GT:
10834 if (dest_mode == V16QImode && op_mode == V16QImode)
10835 return UNSPEC_VCMPGTSB;
10836 if (dest_mode == V8HImode && op_mode == V8HImode)
10837 return UNSPEC_VCMPGTSH;
10838 if (dest_mode == V4SImode && op_mode == V4SImode)
10839 return UNSPEC_VCMPGTSW;
10840 if (dest_mode == V4SImode && op_mode == V4SFmode)
10841 return UNSPEC_VCMPGTFP;
10842 break;
10843 case GTU:
10844 if (dest_mode == V16QImode && op_mode == V16QImode)
10845 return UNSPEC_VCMPGTUB;
10846 if (dest_mode == V8HImode && op_mode == V8HImode)
10847 return UNSPEC_VCMPGTUH;
10848 if (dest_mode == V4SImode && op_mode == V4SImode)
10849 return UNSPEC_VCMPGTUW;
10850 break;
10851 default:
10852 break;
10853 }
10854 return INSN_NOT_AVAILABLE;
10855}
10856
10857/* Emit vector compare for operands OP0 and OP1 using code RCODE.
10858 DMODE is expected destination mode. This is a recursive function. */
10859
10860static rtx
10861rs6000_emit_vector_compare (enum rtx_code rcode,
10862 rtx op0, rtx op1,
10863 enum machine_mode dmode)
10864{
10865 int vec_cmp_insn;
10866 rtx mask;
10867 enum machine_mode dest_mode;
10868 enum machine_mode op_mode = GET_MODE (op1);
10869
37409796
NS		 10870 gcc_assert (TARGET_ALTIVEC);
10871 gcc_assert (GET_MODE (op0) == GET_MODE (op1));
21213b4c
DP		 10872
10873 /* Floating point vector compare instructions uses destination V4SImode.
10874 Move destination to appropriate mode later. */
10875 if (dmode == V4SFmode)
10876 dest_mode = V4SImode;
10877 else
10878 dest_mode = dmode;
10879
10880 mask = gen_reg_rtx (dest_mode);
10881 vec_cmp_insn = get_vec_cmp_insn (rcode, dest_mode, op_mode);
10882
10883 if (vec_cmp_insn == INSN_NOT_AVAILABLE)
10884 {
10885 bool swap_operands = false;
10886 bool try_again = false;
10887 switch (rcode)
10888 {
10889 case LT:
10890 rcode = GT;
10891 swap_operands = true;
10892 try_again = true;
10893 break;
10894 case LTU:
10895 rcode = GTU;
10896 swap_operands = true;
10897 try_again = true;
10898 break;
10899 case NE:
10900 /* Treat A != B as ~(A==B). */
10901 {
10902 enum insn_code nor_code;
10903 rtx eq_rtx = rs6000_emit_vector_compare (EQ, op0, op1,
10904 dest_mode);
94ff898d 10905
21213b4c 10906 nor_code = one_cmpl_optab->handlers[(int)dest_mode].insn_code;
37409796 10907 gcc_assert (nor_code != CODE_FOR_nothing);
21213b4c
DP		 10908 emit_insn (GEN_FCN (nor_code) (mask, eq_rtx));
10909
10910 if (dmode != dest_mode)
10911 {
10912 rtx temp = gen_reg_rtx (dest_mode);
10913 convert_move (temp, mask, 0);
10914 return temp;
10915 }
10916 return mask;
10917 }
10918 break;
10919 case GE:
10920 case GEU:
10921 case LE:
10922 case LEU:
10923 /* Try GT/GTU/LT/LTU OR EQ */
10924 {
10925 rtx c_rtx, eq_rtx;
10926 enum insn_code ior_code;
10927 enum rtx_code new_code;
10928
37409796
NS		 10929 switch (rcode)
10930 {
10931 case GE:
10932 new_code = GT;
10933 break;
10934
10935 case GEU:
10936 new_code = GTU;
10937 break;
10938
10939 case LE:
10940 new_code = LT;
10941 break;
10942
10943 case LEU:
10944 new_code = LTU;
10945 break;
10946
10947 default:
10948 gcc_unreachable ();
10949 }
21213b4c
DP		 10950
10951 c_rtx = rs6000_emit_vector_compare (new_code,
10952 op0, op1, dest_mode);
10953 eq_rtx = rs6000_emit_vector_compare (EQ, op0, op1,
10954 dest_mode);
10955
10956 ior_code = ior_optab->handlers[(int)dest_mode].insn_code;
37409796 10957 gcc_assert (ior_code != CODE_FOR_nothing);
21213b4c
DP		 10958 emit_insn (GEN_FCN (ior_code) (mask, c_rtx, eq_rtx));
10959 if (dmode != dest_mode)
10960 {
10961 rtx temp = gen_reg_rtx (dest_mode);
10962 convert_move (temp, mask, 0);
10963 return temp;
10964 }
10965 return mask;
10966 }
10967 break;
10968 default:
37409796 10969 gcc_unreachable ();
21213b4c
DP		 10970 }
10971
10972 if (try_again)
10973 {
10974 vec_cmp_insn = get_vec_cmp_insn (rcode, dest_mode, op_mode);
37409796
NS		 10975 /* You only get two chances. */
10976 gcc_assert (vec_cmp_insn != INSN_NOT_AVAILABLE);
21213b4c
DP		 10977 }
10978
10979 if (swap_operands)
10980 {
10981 rtx tmp;
10982 tmp = op0;
10983 op0 = op1;
10984 op1 = tmp;
10985 }
10986 }
10987
915167f5
GK		 10988 emit_insn (gen_rtx_SET (VOIDmode, mask,
10989 gen_rtx_UNSPEC (dest_mode,
10990 gen_rtvec (2, op0, op1),
10991 vec_cmp_insn)));
21213b4c
DP		 10992 if (dmode != dest_mode)
10993 {
10994 rtx temp = gen_reg_rtx (dest_mode);
10995 convert_move (temp, mask, 0);
10996 return temp;
10997 }
10998 return mask;
10999}
11000
11001/* Return vector select instruction for MODE. Return INSN_NOT_AVAILABLE, if
11002 valid insn doesn exist for given mode. */
11003
11004static int
11005get_vsel_insn (enum machine_mode mode)
11006{
11007 switch (mode)
11008 {
11009 case V4SImode:
11010 return UNSPEC_VSEL4SI;
11011 break;
11012 case V4SFmode:
11013 return UNSPEC_VSEL4SF;
11014 break;
11015 case V8HImode:
11016 return UNSPEC_VSEL8HI;
11017 break;
11018 case V16QImode:
11019 return UNSPEC_VSEL16QI;
11020 break;
11021 default:
11022 return INSN_NOT_AVAILABLE;
11023 break;
11024 }
11025 return INSN_NOT_AVAILABLE;
11026}
11027
11028/* Emit vector select insn where DEST is destination using
11029 operands OP1, OP2 and MASK. */
11030
11031static void
11032rs6000_emit_vector_select (rtx dest, rtx op1, rtx op2, rtx mask)
11033{
11034 rtx t, temp;
11035 enum machine_mode dest_mode = GET_MODE (dest);
11036 int vsel_insn_index = get_vsel_insn (GET_MODE (dest));
11037
11038 temp = gen_reg_rtx (dest_mode);
94ff898d 11039
19f1ebc7
DP		 11040 /* For each vector element, select op1 when mask is 1 otherwise
11041 select op2. */
915167f5
GK		 11042 t = gen_rtx_SET (VOIDmode, temp,
11043 gen_rtx_UNSPEC (dest_mode,
11044 gen_rtvec (3, op2, op1, mask),
11045 vsel_insn_index));
21213b4c
DP		 11046 emit_insn (t);
11047 emit_move_insn (dest, temp);
11048 return;
11049}
11050
94ff898d 11051/* Emit vector conditional expression.
21213b4c
DP		 11052 DEST is destination. OP1 and OP2 are two VEC_COND_EXPR operands.
11053 CC_OP0 and CC_OP1 are the two operands for the relation operation COND. */
11054
11055int
11056rs6000_emit_vector_cond_expr (rtx dest, rtx op1, rtx op2,
11057 rtx cond, rtx cc_op0, rtx cc_op1)
11058{
11059 enum machine_mode dest_mode = GET_MODE (dest);
11060 enum rtx_code rcode = GET_CODE (cond);
11061 rtx mask;
11062
11063 if (!TARGET_ALTIVEC)
11064 return 0;
11065
11066 /* Get the vector mask for the given relational operations. */
11067 mask = rs6000_emit_vector_compare (rcode, cc_op0, cc_op1, dest_mode);
11068
11069 rs6000_emit_vector_select (dest, op1, op2, mask);
11070
11071 return 1;
11072}
11073
50a0b056
GK		 11074/* Emit a conditional move: move TRUE_COND to DEST if OP of the
11075 operands of the last comparison is nonzero/true, FALSE_COND if it
11076 is zero/false. Return 0 if the hardware has no such operation. */
a4f6c312 11077
50a0b056 11078int
a2369ed3 11079rs6000_emit_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond)
50a0b056
GK		 11080{
11081 enum rtx_code code = GET_CODE (op);
11082 rtx op0 = rs6000_compare_op0;
11083 rtx op1 = rs6000_compare_op1;
11084 REAL_VALUE_TYPE c1;
3148ad6d
DJ		 11085 enum machine_mode compare_mode = GET_MODE (op0);
11086 enum machine_mode result_mode = GET_MODE (dest);
50a0b056 11087 rtx temp;
add2402e 11088 bool is_against_zero;
50a0b056 11089
a3c9585f 11090 /* These modes should always match. */
a3170dc6
AH		 11091 if (GET_MODE (op1) != compare_mode
11092 /* In the isel case however, we can use a compare immediate, so
11093 op1 may be a small constant. */
11094 && (!TARGET_ISEL || !short_cint_operand (op1, VOIDmode)))
3148ad6d 11095 return 0;
178c3eff 11096 if (GET_MODE (true_cond) != result_mode)
3148ad6d 11097 return 0;
178c3eff 11098 if (GET_MODE (false_cond) != result_mode)
3148ad6d
DJ		 11099 return 0;
11100
50a0b056 11101 /* First, work out if the hardware can do this at all, or
a3c9585f 11102 if it's too slow.... */
50a0b056 11103 if (! rs6000_compare_fp_p)
a3170dc6
AH		 11104 {
11105 if (TARGET_ISEL)
11106 return rs6000_emit_int_cmove (dest, op, true_cond, false_cond);
11107 return 0;
11108 }
fef98bf2
AH		 11109 else if (TARGET_E500 && TARGET_HARD_FLOAT && !TARGET_FPRS
11110 && GET_MODE_CLASS (compare_mode) == MODE_FLOAT)
11111 return 0;
50a0b056 11112
add2402e 11113 is_against_zero = op1 == CONST0_RTX (compare_mode);
94ff898d 11114
add2402e
GK		 11115 /* A floating-point subtract might overflow, underflow, or produce
11116 an inexact result, thus changing the floating-point flags, so it
11117 can't be generated if we care about that. It's safe if one side
11118 of the construct is zero, since then no subtract will be
11119 generated. */
11120 if (GET_MODE_CLASS (compare_mode) == MODE_FLOAT
11121 && flag_trapping_math && ! is_against_zero)
11122 return 0;
11123
50a0b056
GK		 11124 /* Eliminate half of the comparisons by switching operands, this
11125 makes the remaining code simpler. */
11126 if (code == UNLT || code == UNGT || code == UNORDERED || code == NE
bc9ec0e0 11127 || code == LTGT || code == LT || code == UNLE)
50a0b056
GK		 11128 {
11129 code = reverse_condition_maybe_unordered (code);
11130 temp = true_cond;
11131 true_cond = false_cond;
11132 false_cond = temp;
11133 }
11134
11135 /* UNEQ and LTGT take four instructions for a comparison with zero,
11136 it'll probably be faster to use a branch here too. */
bc9ec0e0 11137 if (code == UNEQ && HONOR_NANS (compare_mode))
50a0b056 11138 return 0;
f676971a 11139
50a0b056
GK		 11140 if (GET_CODE (op1) == CONST_DOUBLE)
11141 REAL_VALUE_FROM_CONST_DOUBLE (c1, op1);
f676971a 11142
b6d08ca1 11143 /* We're going to try to implement comparisons by performing
50a0b056
GK		 11144 a subtract, then comparing against zero. Unfortunately,
11145 Inf - Inf is NaN which is not zero, and so if we don't
27d30956 11146 know that the operand is finite and the comparison
50a0b056 11147 would treat EQ different to UNORDERED, we can't do it. */
bc9ec0e0 11148 if (HONOR_INFINITIES (compare_mode)
50a0b056 11149 && code != GT && code != UNGE
045572c7 11150 && (GET_CODE (op1) != CONST_DOUBLE || real_isinf (&c1))
50a0b056
GK		 11151 /* Constructs of the form (a OP b ? a : b) are safe. */
11152 && ((! rtx_equal_p (op0, false_cond) && ! rtx_equal_p (op1, false_cond))
f676971a 11153 || (! rtx_equal_p (op0, true_cond)
50a0b056
GK		 11154 && ! rtx_equal_p (op1, true_cond))))
11155 return 0;
add2402e 11156
50a0b056
GK		 11157 /* At this point we know we can use fsel. */
11158
11159 /* Reduce the comparison to a comparison against zero. */
add2402e
GK		 11160 if (! is_against_zero)
11161 {
11162 temp = gen_reg_rtx (compare_mode);
11163 emit_insn (gen_rtx_SET (VOIDmode, temp,
11164 gen_rtx_MINUS (compare_mode, op0, op1)));
11165 op0 = temp;
11166 op1 = CONST0_RTX (compare_mode);
11167 }
50a0b056
GK		 11168
11169 /* If we don't care about NaNs we can reduce some of the comparisons
11170 down to faster ones. */
bc9ec0e0 11171 if (! HONOR_NANS (compare_mode))
50a0b056
GK		 11172 switch (code)
11173 {
11174 case GT:
11175 code = LE;
11176 temp = true_cond;
11177 true_cond = false_cond;
11178 false_cond = temp;
11179 break;
11180 case UNGE:
11181 code = GE;
11182 break;
11183 case UNEQ:
11184 code = EQ;
11185 break;
11186 default:
11187 break;
11188 }
11189
11190 /* Now, reduce everything down to a GE. */
11191 switch (code)
11192 {
11193 case GE:
11194 break;
11195
11196 case LE:
3148ad6d
DJ		 11197 temp = gen_reg_rtx (compare_mode);
11198 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
50a0b056
GK		 11199 op0 = temp;
11200 break;
11201
11202 case ORDERED:
3148ad6d
DJ		 11203 temp = gen_reg_rtx (compare_mode);
11204 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_ABS (compare_mode, op0)));
50a0b056
GK		 11205 op0 = temp;
11206 break;
11207
11208 case EQ:
3148ad6d 11209 temp = gen_reg_rtx (compare_mode);
f676971a 11210 emit_insn (gen_rtx_SET (VOIDmode, temp,
3148ad6d
DJ		 11211 gen_rtx_NEG (compare_mode,
11212 gen_rtx_ABS (compare_mode, op0))));
50a0b056
GK		 11213 op0 = temp;
11214 break;
11215
11216 case UNGE:
bc9ec0e0 11217 /* a UNGE 0 <-> (a GE 0 || -a UNLT 0) */
3148ad6d 11218 temp = gen_reg_rtx (result_mode);
50a0b056 11219 emit_insn (gen_rtx_SET (VOIDmode, temp,
3148ad6d 11220 gen_rtx_IF_THEN_ELSE (result_mode,
50a0b056
GK		 11221 gen_rtx_GE (VOIDmode,
11222 op0, op1),
11223 true_cond, false_cond)));
bc9ec0e0
GK		 11224 false_cond = true_cond;
11225 true_cond = temp;
50a0b056 11226
3148ad6d
DJ		 11227 temp = gen_reg_rtx (compare_mode);
11228 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
50a0b056
GK		 11229 op0 = temp;
11230 break;
11231
11232 case GT:
bc9ec0e0 11233 /* a GT 0 <-> (a GE 0 && -a UNLT 0) */
3148ad6d 11234 temp = gen_reg_rtx (result_mode);
50a0b056 11235 emit_insn (gen_rtx_SET (VOIDmode, temp,
f676971a 11236 gen_rtx_IF_THEN_ELSE (result_mode,
50a0b056
GK		 11237 gen_rtx_GE (VOIDmode,
11238 op0, op1),
11239 true_cond, false_cond)));
bc9ec0e0
GK		 11240 true_cond = false_cond;
11241 false_cond = temp;
50a0b056 11242
3148ad6d
DJ		 11243 temp = gen_reg_rtx (compare_mode);
11244 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
50a0b056
GK		 11245 op0 = temp;
11246 break;
11247
11248 default:
37409796 11249 gcc_unreachable ();
50a0b056
GK		 11250 }
11251
11252 emit_insn (gen_rtx_SET (VOIDmode, dest,
3148ad6d 11253 gen_rtx_IF_THEN_ELSE (result_mode,
50a0b056
GK		 11254 gen_rtx_GE (VOIDmode,
11255 op0, op1),
11256 true_cond, false_cond)));
11257 return 1;
11258}
11259
a3170dc6
AH		 11260/* Same as above, but for ints (isel). */
11261
11262static int
a2369ed3 11263rs6000_emit_int_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond)
a3170dc6
AH		 11264{
11265 rtx condition_rtx, cr;
11266
11267 /* All isel implementations thus far are 32-bits. */
11268 if (GET_MODE (rs6000_compare_op0) != SImode)
11269 return 0;
11270
11271 /* We still have to do the compare, because isel doesn't do a
11272 compare, it just looks at the CRx bits set by a previous compare
11273 instruction. */
11274 condition_rtx = rs6000_generate_compare (GET_CODE (op));
11275 cr = XEXP (condition_rtx, 0);
11276
11277 if (GET_MODE (cr) == CCmode)
11278 emit_insn (gen_isel_signed (dest, condition_rtx,
11279 true_cond, false_cond, cr));
11280 else
11281 emit_insn (gen_isel_unsigned (dest, condition_rtx,
11282 true_cond, false_cond, cr));
11283
11284 return 1;
11285}
11286
11287const char *
a2369ed3 11288output_isel (rtx *operands)
a3170dc6
AH		 11289{
11290 enum rtx_code code;
11291
11292 code = GET_CODE (operands[1]);
11293 if (code == GE || code == GEU || code == LE || code == LEU || code == NE)
11294 {
11295 PUT_CODE (operands[1], reverse_condition (code));
11296 return "isel %0,%3,%2,%j1";
11297 }
11298 else
11299 return "isel %0,%2,%3,%j1";
11300}
11301
50a0b056 11302void
a2369ed3 11303rs6000_emit_minmax (rtx dest, enum rtx_code code, rtx op0, rtx op1)
50a0b056
GK		 11304{
11305 enum machine_mode mode = GET_MODE (op0);
5dc8d536 11306 enum rtx_code c;
50a0b056 11307 rtx target;
5dc8d536
AH		 11308
11309 if (code == SMAX || code == SMIN)
11310 c = GE;
11311 else
11312 c = GEU;
11313
50a0b056 11314 if (code == SMAX || code == UMAX)
f676971a 11315 target = emit_conditional_move (dest, c, op0, op1, mode,
50a0b056
GK		 11316 op0, op1, mode, 0);
11317 else
f676971a 11318 target = emit_conditional_move (dest, c, op0, op1, mode,
50a0b056 11319 op1, op0, mode, 0);
37409796 11320 gcc_assert (target);
50a0b056
GK		 11321 if (target != dest)
11322 emit_move_insn (dest, target);
11323}
46c07df8 11324
915167f5
GK		 11325/* Emit instructions to perform a load-reserved/store-conditional operation.
11326 The operation performed is an atomic
11327 (set M (CODE:MODE M OP))
11328 If not NULL, BEFORE is atomically set to M before the operation, and
11329 AFTER is set to M after the operation (that is, (CODE:MODE M OP)).
11330 If SYNC_P then a memory barrier is emitted before the operation.
11331 Either OP or M may be wrapped in a NOT operation. */
11332
11333void
11334rs6000_emit_sync (enum rtx_code code, enum machine_mode mode,
11335 rtx m, rtx op, rtx before_param, rtx after_param,
11336 bool sync_p)
11337{
11338 enum machine_mode used_mode;
11339 rtx the_op, set_before, set_after, set_atomic, cc_scratch, before, after;
11340 rtx used_m;
11341 rtvec vec;
11342 HOST_WIDE_INT imask = GET_MODE_MASK (mode);
11343 rtx shift = NULL_RTX;
11344
11345 if (sync_p)
11346 emit_insn (gen_memory_barrier ());
11347
11348 if (GET_CODE (m) == NOT)
11349 used_m = XEXP (m, 0);
11350 else
11351 used_m = m;
11352
11353 /* If this is smaller than SImode, we'll have to use SImode with
11354 adjustments. */
11355 if (mode == QImode || mode == HImode)
11356 {
11357 rtx newop, oldop;
11358
11359 if (MEM_ALIGN (used_m) >= 32)
11360 {
11361 int ishift = 0;
11362 if (BYTES_BIG_ENDIAN)
11363 ishift = GET_MODE_BITSIZE (SImode) - GET_MODE_BITSIZE (mode);
11364
11365 shift = GEN_INT (ishift);
11366 }
11367 else
11368 {
11369 rtx addrSI, aligned_addr;
11370
11371 addrSI = force_reg (SImode, gen_lowpart_common (SImode,
11372 XEXP (used_m, 0)));
11373 shift = gen_reg_rtx (SImode);
11374
11375 emit_insn (gen_rlwinm (shift, addrSI, GEN_INT (3),
11376 GEN_INT (0x18)));
11377
11378 aligned_addr = expand_binop (Pmode, and_optab,
11379 XEXP (used_m, 0),
11380 GEN_INT (-4), NULL_RTX,
11381 1, OPTAB_LIB_WIDEN);
11382 used_m = change_address (used_m, SImode, aligned_addr);
11383 set_mem_align (used_m, 32);
11384 /* It's safe to keep the old alias set of USED_M, because
11385 the operation is atomic and only affects the original
11386 USED_M. */
11387 if (GET_CODE (m) == NOT)
11388 m = gen_rtx_NOT (SImode, used_m);
11389 else
11390 m = used_m;
11391 }
11392
11393 if (GET_CODE (op) == NOT)
11394 {
11395 oldop = lowpart_subreg (SImode, XEXP (op, 0), mode);
11396 oldop = gen_rtx_NOT (SImode, oldop);
11397 }
11398 else
11399 oldop = lowpart_subreg (SImode, op, mode);
11400 switch (code)
11401 {
11402 case IOR:
11403 case XOR:
11404 newop = expand_binop (SImode, and_optab,
11405 oldop, GEN_INT (imask), NULL_RTX,
11406 1, OPTAB_LIB_WIDEN);
11407 emit_insn (gen_ashlsi3 (newop, newop, shift));
11408 break;
11409
11410 case AND:
11411 newop = expand_binop (SImode, ior_optab,
11412 oldop, GEN_INT (~imask), NULL_RTX,
11413 1, OPTAB_LIB_WIDEN);
11414 emit_insn (gen_ashlsi3 (newop, newop, shift));
11415 break;
11416
11417 case PLUS:
11418 {
11419 rtx mask;
11420
11421 newop = expand_binop (SImode, and_optab,
11422 oldop, GEN_INT (imask), NULL_RTX,
11423 1, OPTAB_LIB_WIDEN);
11424 emit_insn (gen_ashlsi3 (newop, newop, shift));
11425
11426 mask = gen_reg_rtx (SImode);
11427 emit_move_insn (mask, GEN_INT (imask));
11428 emit_insn (gen_ashlsi3 (mask, mask, shift));
11429
11430 newop = gen_rtx_AND (SImode, gen_rtx_PLUS (SImode, m, newop),
11431 mask);
11432 newop = gen_rtx_IOR (SImode, newop,
11433 gen_rtx_AND (SImode,
11434 gen_rtx_NOT (SImode, mask),
11435 m));
11436 break;
11437 }
11438
11439 default:
11440 gcc_unreachable ();
11441 }
11442
11443 op = newop;
11444 used_mode = SImode;
11445 before = gen_reg_rtx (used_mode);
11446 after = gen_reg_rtx (used_mode);
11447 }
11448 else
11449 {
11450 used_mode = mode;
11451 before = before_param;
11452 after = after_param;
11453
11454 if (before == NULL_RTX)
11455 before = gen_reg_rtx (used_mode);
11456 if (after == NULL_RTX)
11457 after = gen_reg_rtx (used_mode);
11458 }
11459
11460 if (code == PLUS && used_mode != mode)
11461 the_op = op; /* Computed above. */
11462 else if (GET_CODE (op) == NOT && GET_CODE (m) != NOT)
11463 the_op = gen_rtx_fmt_ee (code, used_mode, op, m);
11464 else
11465 the_op = gen_rtx_fmt_ee (code, used_mode, m, op);
11466
11467 set_after = gen_rtx_SET (VOIDmode, after, the_op);
11468 set_before = gen_rtx_SET (VOIDmode, before, used_m);
11469 set_atomic = gen_rtx_SET (VOIDmode, used_m,
11470 gen_rtx_UNSPEC (used_mode, gen_rtvec (1, the_op),
11471 UNSPEC_SYNC_OP));
11472 cc_scratch = gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (CCmode));
11473
11474 if (code == PLUS && used_mode != mode)
11475 vec = gen_rtvec (5, set_after, set_before, set_atomic, cc_scratch,
11476 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (SImode)));
11477 else
11478 vec = gen_rtvec (4, set_after, set_before, set_atomic, cc_scratch);
11479 emit_insn (gen_rtx_PARALLEL (VOIDmode, vec));
11480
11481 /* Shift and mask the return values properly. */
11482 if (used_mode != mode && before_param)
11483 {
11484 emit_insn (gen_lshrsi3 (before, before, shift));
11485 convert_move (before_param, before, 1);
11486 }
11487
11488 if (used_mode != mode && after_param)
11489 {
11490 emit_insn (gen_lshrsi3 (after, after, shift));
11491 convert_move (after_param, after, 1);
11492 }
11493
11494 /* The previous sequence will end with a branch that's dependent on
11495 the conditional store, so placing an isync will ensure that no
11496 other instructions (especially, no load or store instructions)
11497 can start before the atomic operation completes. */
11498 if (sync_p)
11499 emit_insn (gen_isync ());
11500}
11501
a9baceb1
GK		 11502/* Emit instructions to move SRC to DST. Called by splitters for
11503 multi-register moves. It will emit at most one instruction for
11504 each register that is accessed; that is, it won't emit li/lis pairs
11505 (or equivalent for 64-bit code). One of SRC or DST must be a hard
11506 register. */
46c07df8 11507
46c07df8 11508void
a9baceb1 11509rs6000_split_multireg_move (rtx dst, rtx src)
46c07df8 11510{
a9baceb1
GK		 11511 /* The register number of the first register being moved. */
11512 int reg;
11513 /* The mode that is to be moved. */
11514 enum machine_mode mode;
11515 /* The mode that the move is being done in, and its size. */
11516 enum machine_mode reg_mode;
11517 int reg_mode_size;
11518 /* The number of registers that will be moved. */
11519 int nregs;
11520
11521 reg = REG_P (dst) ? REGNO (dst) : REGNO (src);
11522 mode = GET_MODE (dst);
11523 nregs = HARD_REGNO_NREGS (reg, mode);
11524 if (FP_REGNO_P (reg))
11525 reg_mode = DFmode;
11526 else if (ALTIVEC_REGNO_P (reg))
11527 reg_mode = V16QImode;
11528 else
11529 reg_mode = word_mode;
11530 reg_mode_size = GET_MODE_SIZE (reg_mode);
f676971a 11531
37409796 11532 gcc_assert (reg_mode_size * nregs == GET_MODE_SIZE (mode));
f676971a 11533
a9baceb1
GK		 11534 if (REG_P (src) && REG_P (dst) && (REGNO (src) < REGNO (dst)))
11535 {
11536 /* Move register range backwards, if we might have destructive
11537 overlap. */
11538 int i;
11539 for (i = nregs - 1; i >= 0; i--)
f676971a 11540 emit_insn (gen_rtx_SET (VOIDmode,
a9baceb1
GK		 11541 simplify_gen_subreg (reg_mode, dst, mode,
11542 i * reg_mode_size),
11543 simplify_gen_subreg (reg_mode, src, mode,
11544 i * reg_mode_size)));
11545 }
46c07df8
HP		 11546 else
11547 {
a9baceb1
GK		 11548 int i;
11549 int j = -1;
11550 bool used_update = false;
46c07df8 11551
c1e55850 11552 if (MEM_P (src) && INT_REGNO_P (reg))
c4ad648e
AM		 11553 {
11554 rtx breg;
3a1f863f 11555
a9baceb1
GK		 11556 if (GET_CODE (XEXP (src, 0)) == PRE_INC
11557 || GET_CODE (XEXP (src, 0)) == PRE_DEC)
3a1f863f
DE		 11558 {
11559 rtx delta_rtx;
a9baceb1 11560 breg = XEXP (XEXP (src, 0), 0);
c4ad648e
AM		 11561 delta_rtx = (GET_CODE (XEXP (src, 0)) == PRE_INC
11562 ? GEN_INT (GET_MODE_SIZE (GET_MODE (src)))
11563 : GEN_INT (-GET_MODE_SIZE (GET_MODE (src))));
a9baceb1
GK		 11564 emit_insn (TARGET_32BIT
11565 ? gen_addsi3 (breg, breg, delta_rtx)
11566 : gen_adddi3 (breg, breg, delta_rtx));
3a1f863f
DE		 11567 src = gen_rtx_MEM (mode, breg);
11568 }
c1e55850
GK		 11569 else if (! offsettable_memref_p (src))
11570 {
11571 rtx newsrc, basereg;
11572 basereg = gen_rtx_REG (Pmode, reg);
11573 emit_insn (gen_rtx_SET (VOIDmode, basereg, XEXP (src, 0)));
11574 newsrc = gen_rtx_MEM (GET_MODE (src), basereg);
11575 MEM_COPY_ATTRIBUTES (newsrc, src);
11576 src = newsrc;
11577 }
3a1f863f 11578
0423421f
AM		 11579 breg = XEXP (src, 0);
11580 if (GET_CODE (breg) == PLUS || GET_CODE (breg) == LO_SUM)
11581 breg = XEXP (breg, 0);
11582
11583 /* If the base register we are using to address memory is
11584 also a destination reg, then change that register last. */
11585 if (REG_P (breg)
11586 && REGNO (breg) >= REGNO (dst)
3a1f863f
DE		 11587 && REGNO (breg) < REGNO (dst) + nregs)
11588 j = REGNO (breg) - REGNO (dst);
c4ad648e 11589 }
46c07df8 11590
a9baceb1 11591 if (GET_CODE (dst) == MEM && INT_REGNO_P (reg))
3a1f863f
DE		 11592 {
11593 rtx breg;
11594
a9baceb1
GK		 11595 if (GET_CODE (XEXP (dst, 0)) == PRE_INC
11596 || GET_CODE (XEXP (dst, 0)) == PRE_DEC)
3a1f863f
DE		 11597 {
11598 rtx delta_rtx;
a9baceb1 11599 breg = XEXP (XEXP (dst, 0), 0);
c4ad648e
AM		 11600 delta_rtx = (GET_CODE (XEXP (dst, 0)) == PRE_INC
11601 ? GEN_INT (GET_MODE_SIZE (GET_MODE (dst)))
11602 : GEN_INT (-GET_MODE_SIZE (GET_MODE (dst))));
3a1f863f
DE		 11603
11604 /* We have to update the breg before doing the store.
11605 Use store with update, if available. */
11606
11607 if (TARGET_UPDATE)
11608 {
a9baceb1 11609 rtx nsrc = simplify_gen_subreg (reg_mode, src, mode, 0);
c4ad648e
AM		 11610 emit_insn (TARGET_32BIT
11611 ? (TARGET_POWERPC64
11612 ? gen_movdi_si_update (breg, breg, delta_rtx, nsrc)
11613 : gen_movsi_update (breg, breg, delta_rtx, nsrc))
11614 : gen_movdi_di_update (breg, breg, delta_rtx, nsrc));
a9baceb1 11615 used_update = true;
3a1f863f
DE		 11616 }
11617 else
a9baceb1
GK		 11618 emit_insn (TARGET_32BIT
11619 ? gen_addsi3 (breg, breg, delta_rtx)
11620 : gen_adddi3 (breg, breg, delta_rtx));
3a1f863f
DE		 11621 dst = gen_rtx_MEM (mode, breg);
11622 }
37409796
NS		 11623 else
11624 gcc_assert (offsettable_memref_p (dst));
3a1f863f
DE		 11625 }
11626
46c07df8 11627 for (i = 0; i < nregs; i++)
f676971a 11628 {
3a1f863f
DE		 11629 /* Calculate index to next subword. */
11630 ++j;
f676971a 11631 if (j == nregs)
3a1f863f 11632 j = 0;
46c07df8 11633
112cdef5 11634 /* If compiler already emitted move of first word by
a9baceb1 11635 store with update, no need to do anything. */
3a1f863f 11636 if (j == 0 && used_update)
a9baceb1 11637 continue;
f676971a 11638
a9baceb1
GK		 11639 emit_insn (gen_rtx_SET (VOIDmode,
11640 simplify_gen_subreg (reg_mode, dst, mode,
11641 j * reg_mode_size),
11642 simplify_gen_subreg (reg_mode, src, mode,
11643 j * reg_mode_size)));
3a1f863f 11644 }
46c07df8
HP		 11645 }
11646}
11647
12a4e8c5 11648\f
a4f6c312
SS		 11649/* This page contains routines that are used to determine what the
11650 function prologue and epilogue code will do and write them out. */
9878760c 11651
a4f6c312
SS		 11652/* Return the first fixed-point register that is required to be
11653 saved. 32 if none. */
9878760c
RK		 11654
11655int
863d938c 11656first_reg_to_save (void)
9878760c
RK		 11657{
11658 int first_reg;
11659
11660 /* Find lowest numbered live register. */
11661 for (first_reg = 13; first_reg <= 31; first_reg++)
f676971a 11662 if (regs_ever_live[first_reg]
a38d360d 11663 && (! call_used_regs[first_reg]
1db02437 11664 || (first_reg == RS6000_PIC_OFFSET_TABLE_REGNUM
14f00213 11665 && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0)
b4db40bf
JJ		 11666 || (DEFAULT_ABI == ABI_DARWIN && flag_pic)
11667 || (TARGET_TOC && TARGET_MINIMAL_TOC)))))
9878760c
RK		 11668 break;
11669
ee890fe2 11670#if TARGET_MACHO
93638d7a
AM		 11671 if (flag_pic
11672 && current_function_uses_pic_offset_table
11673 && first_reg > RS6000_PIC_OFFSET_TABLE_REGNUM)
1db02437 11674 return RS6000_PIC_OFFSET_TABLE_REGNUM;
ee890fe2
SS		 11675#endif
11676
9878760c
RK		 11677 return first_reg;
11678}
11679
11680/* Similar, for FP regs. */
11681
11682int
863d938c 11683first_fp_reg_to_save (void)
9878760c
RK		 11684{
11685 int first_reg;
11686
11687 /* Find lowest numbered live register. */
11688 for (first_reg = 14 + 32; first_reg <= 63; first_reg++)
11689 if (regs_ever_live[first_reg])
11690 break;
11691
11692 return first_reg;
11693}
00b960c7
AH		 11694
11695/* Similar, for AltiVec regs. */
11696
11697static int
863d938c 11698first_altivec_reg_to_save (void)
00b960c7
AH		 11699{
11700 int i;
11701
11702 /* Stack frame remains as is unless we are in AltiVec ABI. */
11703 if (! TARGET_ALTIVEC_ABI)
11704 return LAST_ALTIVEC_REGNO + 1;
11705
11706 /* Find lowest numbered live register. */
11707 for (i = FIRST_ALTIVEC_REGNO + 20; i <= LAST_ALTIVEC_REGNO; ++i)
11708 if (regs_ever_live[i])
11709 break;
11710
11711 return i;
11712}
11713
11714/* Return a 32-bit mask of the AltiVec registers we need to set in
11715 VRSAVE. Bit n of the return value is 1 if Vn is live. The MSB in
11716 the 32-bit word is 0. */
11717
11718static unsigned int
863d938c 11719compute_vrsave_mask (void)
00b960c7
AH		 11720{
11721 unsigned int i, mask = 0;
11722
11723 /* First, find out if we use _any_ altivec registers. */
11724 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
11725 if (regs_ever_live[i])
11726 mask |= ALTIVEC_REG_BIT (i);
11727
11728 if (mask == 0)
11729 return mask;
11730
00b960c7
AH		 11731 /* Next, remove the argument registers from the set. These must
11732 be in the VRSAVE mask set by the caller, so we don't need to add
11733 them in again. More importantly, the mask we compute here is
11734 used to generate CLOBBERs in the set_vrsave insn, and we do not
11735 wish the argument registers to die. */
a6cf80f2 11736 for (i = cfun->args_info.vregno - 1; i >= ALTIVEC_ARG_MIN_REG; --i)
00b960c7
AH		 11737 mask &= ~ALTIVEC_REG_BIT (i);
11738
11739 /* Similarly, remove the return value from the set. */
11740 {
11741 bool yes = false;
11742 diddle_return_value (is_altivec_return_reg, &yes);
11743 if (yes)
11744 mask &= ~ALTIVEC_REG_BIT (ALTIVEC_ARG_RETURN);
11745 }
11746
11747 return mask;
11748}
11749
d62294f5 11750/* For a very restricted set of circumstances, we can cut down the
f57fe068
AM		 11751 size of prologues/epilogues by calling our own save/restore-the-world
11752 routines. */
d62294f5
FJ		 11753
11754static void
f57fe068
AM		 11755compute_save_world_info (rs6000_stack_t *info_ptr)
11756{
11757 info_ptr->world_save_p = 1;
11758 info_ptr->world_save_p
11759 = (WORLD_SAVE_P (info_ptr)
11760 && DEFAULT_ABI == ABI_DARWIN
11761 && ! (current_function_calls_setjmp && flag_exceptions)
11762 && info_ptr->first_fp_reg_save == FIRST_SAVED_FP_REGNO
11763 && info_ptr->first_gp_reg_save == FIRST_SAVED_GP_REGNO
11764 && info_ptr->first_altivec_reg_save == FIRST_SAVED_ALTIVEC_REGNO
11765 && info_ptr->cr_save_p);
f676971a 11766
d62294f5
FJ		 11767 /* This will not work in conjunction with sibcalls. Make sure there
11768 are none. (This check is expensive, but seldom executed.) */
f57fe068 11769 if (WORLD_SAVE_P (info_ptr))
f676971a 11770 {
d62294f5
FJ		 11771 rtx insn;
11772 for ( insn = get_last_insn_anywhere (); insn; insn = PREV_INSN (insn))
c4ad648e
AM		 11773 if ( GET_CODE (insn) == CALL_INSN
11774 && SIBLING_CALL_P (insn))
11775 {
11776 info_ptr->world_save_p = 0;
11777 break;
11778 }
d62294f5 11779 }
f676971a 11780
f57fe068 11781 if (WORLD_SAVE_P (info_ptr))
d62294f5
FJ		 11782 {
11783 /* Even if we're not touching VRsave, make sure there's room on the
11784 stack for it, if it looks like we're calling SAVE_WORLD, which
c4ad648e 11785 will attempt to save it. */
d62294f5
FJ		 11786 info_ptr->vrsave_size = 4;
11787
11788 /* "Save" the VRsave register too if we're saving the world. */
11789 if (info_ptr->vrsave_mask == 0)
c4ad648e 11790 info_ptr->vrsave_mask = compute_vrsave_mask ();
d62294f5
FJ		 11791
11792 /* Because the Darwin register save/restore routines only handle
c4ad648e 11793 F14 .. F31 and V20 .. V31 as per the ABI, perform a consistency
992d08b1 11794 check. */
37409796
NS		 11795 gcc_assert (info_ptr->first_fp_reg_save >= FIRST_SAVED_FP_REGNO
11796 && (info_ptr->first_altivec_reg_save
11797 >= FIRST_SAVED_ALTIVEC_REGNO));
d62294f5 11798 }
f676971a 11799 return;
d62294f5
FJ		 11800}
11801
11802
00b960c7 11803static void
a2369ed3 11804is_altivec_return_reg (rtx reg, void *xyes)
00b960c7
AH		 11805{
11806 bool *yes = (bool *) xyes;
11807 if (REGNO (reg) == ALTIVEC_ARG_RETURN)
11808 *yes = true;
11809}
11810
4697a36c
MM		 11811\f
11812/* Calculate the stack information for the current function. This is
11813 complicated by having two separate calling sequences, the AIX calling
11814 sequence and the V.4 calling sequence.
11815
592696dd 11816 AIX (and Darwin/Mac OS X) stack frames look like:
a260abc9 11817 32-bit 64-bit
4697a36c 11818 SP----> +---------------------------------------+
a260abc9 11819 | back chain to caller | 0 0
4697a36c 11820 +---------------------------------------+
a260abc9 11821 | saved CR | 4 8 (8-11)
4697a36c 11822 +---------------------------------------+
a260abc9 11823 | saved LR | 8 16
4697a36c 11824 +---------------------------------------+
a260abc9 11825 | reserved for compilers | 12 24
4697a36c 11826 +---------------------------------------+
a260abc9 11827 | reserved for binders | 16 32
4697a36c 11828 +---------------------------------------+
a260abc9 11829 | saved TOC pointer | 20 40
4697a36c 11830 +---------------------------------------+
a260abc9 11831 | Parameter save area (P) | 24 48
4697a36c 11832 +---------------------------------------+
a260abc9 11833 | Alloca space (A) | 24+P etc.
802a0058 11834 +---------------------------------------+
a7df97e6 11835 | Local variable space (L) | 24+P+A
4697a36c 11836 +---------------------------------------+
a7df97e6 11837 | Float/int conversion temporary (X) | 24+P+A+L
4697a36c 11838 +---------------------------------------+
00b960c7
AH		 11839 | Save area for AltiVec registers (W) | 24+P+A+L+X
11840 +---------------------------------------+
11841 | AltiVec alignment padding (Y) | 24+P+A+L+X+W
11842 +---------------------------------------+
11843 | Save area for VRSAVE register (Z) | 24+P+A+L+X+W+Y
4697a36c 11844 +---------------------------------------+
00b960c7
AH		 11845 | Save area for GP registers (G) | 24+P+A+X+L+X+W+Y+Z
11846 +---------------------------------------+
11847 | Save area for FP registers (F) | 24+P+A+X+L+X+W+Y+Z+G
4697a36c
MM		 11848 +---------------------------------------+
11849 old SP->| back chain to caller's caller |
11850 +---------------------------------------+
11851
5376a30c
KR		 11852 The required alignment for AIX configurations is two words (i.e., 8
11853 or 16 bytes).
11854
11855
4697a36c
MM		 11856 V.4 stack frames look like:
11857
11858 SP----> +---------------------------------------+
11859 | back chain to caller | 0
11860 +---------------------------------------+
5eb387b8 11861 | caller's saved LR | 4
4697a36c
MM		 11862 +---------------------------------------+
11863 | Parameter save area (P) | 8
11864 +---------------------------------------+
a7df97e6 11865 | Alloca space (A) | 8+P
f676971a 11866 +---------------------------------------+
a7df97e6 11867 | Varargs save area (V) | 8+P+A
f676971a 11868 +---------------------------------------+
a7df97e6 11869 | Local variable space (L) | 8+P+A+V
f676971a 11870 +---------------------------------------+
a7df97e6 11871 | Float/int conversion temporary (X) | 8+P+A+V+L
4697a36c 11872 +---------------------------------------+
00b960c7
AH		 11873 | Save area for AltiVec registers (W) | 8+P+A+V+L+X
11874 +---------------------------------------+
11875 | AltiVec alignment padding (Y) | 8+P+A+V+L+X+W
11876 +---------------------------------------+
11877 | Save area for VRSAVE register (Z) | 8+P+A+V+L+X+W+Y
11878 +---------------------------------------+
c4ad648e
AM		 11879 | SPE: area for 64-bit GP registers |
11880 +---------------------------------------+
11881 | SPE alignment padding |
11882 +---------------------------------------+
00b960c7 11883 | saved CR (C) | 8+P+A+V+L+X+W+Y+Z
f676971a 11884 +---------------------------------------+
00b960c7 11885 | Save area for GP registers (G) | 8+P+A+V+L+X+W+Y+Z+C
f676971a 11886 +---------------------------------------+
00b960c7 11887 | Save area for FP registers (F) | 8+P+A+V+L+X+W+Y+Z+C+G
4697a36c
MM		 11888 +---------------------------------------+
11889 old SP->| back chain to caller's caller |
11890 +---------------------------------------+
b6c9286a 11891
5376a30c
KR		 11892 The required alignment for V.4 is 16 bytes, or 8 bytes if -meabi is
11893 given. (But note below and in sysv4.h that we require only 8 and
11894 may round up the size of our stack frame anyways. The historical
11895 reason is early versions of powerpc-linux which didn't properly
11896 align the stack at program startup. A happy side-effect is that
11897 -mno-eabi libraries can be used with -meabi programs.)
11898
50d440bc 11899 The EABI configuration defaults to the V.4 layout. However,
5376a30c
KR		 11900 the stack alignment requirements may differ. If -mno-eabi is not
11901 given, the required stack alignment is 8 bytes; if -mno-eabi is
11902 given, the required alignment is 16 bytes. (But see V.4 comment
11903 above.) */
4697a36c 11904
61b2fbe7
MM		 11905#ifndef ABI_STACK_BOUNDARY
11906#define ABI_STACK_BOUNDARY STACK_BOUNDARY
11907#endif
11908
d1d0c603 11909static rs6000_stack_t *
863d938c 11910rs6000_stack_info (void)
4697a36c
MM		 11911{
11912 static rs6000_stack_t info, zero_info;
11913 rs6000_stack_t *info_ptr = &info;
327e5343 11914 int reg_size = TARGET_32BIT ? 4 : 8;
83720594 11915 int ehrd_size;
64045029 11916 int save_align;
44688022 11917 HOST_WIDE_INT non_fixed_size;
4697a36c 11918
a4f6c312 11919 /* Zero all fields portably. */
4697a36c
MM		 11920 info = zero_info;
11921
c19de7aa
AH		 11922 if (TARGET_SPE)
11923 {
11924 /* Cache value so we don't rescan instruction chain over and over. */
9b7b447f 11925 if (cfun->machine->insn_chain_scanned_p == 0)
b5a5beb9
AH		 11926 cfun->machine->insn_chain_scanned_p
11927 = spe_func_has_64bit_regs_p () + 1;
11928 info_ptr->spe_64bit_regs_used = cfun->machine->insn_chain_scanned_p - 1;
c19de7aa
AH		 11929 }
11930
a4f6c312 11931 /* Select which calling sequence. */
178274da 11932 info_ptr->abi = DEFAULT_ABI;
9878760c 11933
a4f6c312 11934 /* Calculate which registers need to be saved & save area size. */
4697a36c 11935 info_ptr->first_gp_reg_save = first_reg_to_save ();
f676971a 11936 /* Assume that we will have to save RS6000_PIC_OFFSET_TABLE_REGNUM,
906fb125 11937 even if it currently looks like we won't. */
2bfcf297 11938 if (((TARGET_TOC && TARGET_MINIMAL_TOC)
178274da
AM		 11939 || (flag_pic == 1 && DEFAULT_ABI == ABI_V4)
11940 || (flag_pic && DEFAULT_ABI == ABI_DARWIN))
1db02437
FS		 11941 && info_ptr->first_gp_reg_save > RS6000_PIC_OFFSET_TABLE_REGNUM)
11942 info_ptr->gp_size = reg_size * (32 - RS6000_PIC_OFFSET_TABLE_REGNUM);
906fb125
GK		 11943 else
11944 info_ptr->gp_size = reg_size * (32 - info_ptr->first_gp_reg_save);
4697a36c 11945
a3170dc6
AH		 11946 /* For the SPE, we have an additional upper 32-bits on each GPR.
11947 Ideally we should save the entire 64-bits only when the upper
11948 half is used in SIMD instructions. Since we only record
11949 registers live (not the size they are used in), this proves
11950 difficult because we'd have to traverse the instruction chain at
11951 the right time, taking reload into account. This is a real pain,
c19de7aa
AH		 11952 so we opt to save the GPRs in 64-bits always if but one register
11953 gets used in 64-bits. Otherwise, all the registers in the frame
11954 get saved in 32-bits.
a3170dc6 11955
c19de7aa 11956 So... since when we save all GPRs (except the SP) in 64-bits, the
a3170dc6 11957 traditional GP save area will be empty. */
c19de7aa 11958 if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
a3170dc6
AH		 11959 info_ptr->gp_size = 0;
11960
4697a36c
MM		 11961 info_ptr->first_fp_reg_save = first_fp_reg_to_save ();
11962 info_ptr->fp_size = 8 * (64 - info_ptr->first_fp_reg_save);
11963
00b960c7
AH		 11964 info_ptr->first_altivec_reg_save = first_altivec_reg_to_save ();
11965 info_ptr->altivec_size = 16 * (LAST_ALTIVEC_REGNO + 1
11966 - info_ptr->first_altivec_reg_save);
11967
592696dd 11968 /* Does this function call anything? */
71f123ca
FS		 11969 info_ptr->calls_p = (! current_function_is_leaf
11970 || cfun->machine->ra_needs_full_frame);
b6c9286a 11971
a4f6c312 11972 /* Determine if we need to save the link register. */
71f123ca 11973 if (rs6000_ra_ever_killed ()
ffcfcb5f
AM		 11974 || (DEFAULT_ABI == ABI_AIX
11975 && current_function_profile
11976 && !TARGET_PROFILE_KERNEL)
4697a36c
MM		 11977#ifdef TARGET_RELOCATABLE
11978 || (TARGET_RELOCATABLE && (get_pool_size () != 0))
11979#endif
11980 || (info_ptr->first_fp_reg_save != 64
11981 && !FP_SAVE_INLINE (info_ptr->first_fp_reg_save))
00b960c7 11982 || info_ptr->first_altivec_reg_save <= LAST_ALTIVEC_REGNO
178274da 11983 || (DEFAULT_ABI == ABI_V4 && current_function_calls_alloca)
a4f6c312
SS		 11984 || (DEFAULT_ABI == ABI_DARWIN
11985 && flag_pic
11986 && current_function_uses_pic_offset_table)
4697a36c
MM		 11987 || info_ptr->calls_p)
11988 {
11989 info_ptr->lr_save_p = 1;
9ebbca7d 11990 regs_ever_live[LINK_REGISTER_REGNUM] = 1;
4697a36c
MM		 11991 }
11992
9ebbca7d 11993 /* Determine if we need to save the condition code registers. */
f676971a 11994 if (regs_ever_live[CR2_REGNO]
9ebbca7d
GK		 11995 || regs_ever_live[CR3_REGNO]
11996 || regs_ever_live[CR4_REGNO])
4697a36c
MM		 11997 {
11998 info_ptr->cr_save_p = 1;
178274da 11999 if (DEFAULT_ABI == ABI_V4)
4697a36c
MM		 12000 info_ptr->cr_size = reg_size;
12001 }
12002
83720594
RH		 12003 /* If the current function calls __builtin_eh_return, then we need
12004 to allocate stack space for registers that will hold data for
12005 the exception handler. */
12006 if (current_function_calls_eh_return)
12007 {
12008 unsigned int i;
12009 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; ++i)
12010 continue;
a3170dc6
AH		 12011
12012 /* SPE saves EH registers in 64-bits. */
c19de7aa
AH		 12013 ehrd_size = i * (TARGET_SPE_ABI
12014 && info_ptr->spe_64bit_regs_used != 0
12015 ? UNITS_PER_SPE_WORD : UNITS_PER_WORD);
83720594
RH		 12016 }
12017 else
12018 ehrd_size = 0;
12019
592696dd 12020 /* Determine various sizes. */
4697a36c
MM		 12021 info_ptr->reg_size = reg_size;
12022 info_ptr->fixed_size = RS6000_SAVE_AREA;
12023 info_ptr->varargs_size = RS6000_VARARGS_AREA;
189e03e3 12024 info_ptr->vars_size = RS6000_ALIGN (get_frame_size (), 8);
a4f6c312 12025 info_ptr->parm_size = RS6000_ALIGN (current_function_outgoing_args_size,
03e007d7 12026 TARGET_ALTIVEC ? 16 : 8);
00b960c7 12027
c19de7aa 12028 if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
a3170dc6
AH		 12029 info_ptr->spe_gp_size = 8 * (32 - info_ptr->first_gp_reg_save);
12030 else
12031 info_ptr->spe_gp_size = 0;
12032
4d774ff8
HP		 12033 if (TARGET_ALTIVEC_ABI)
12034 info_ptr->vrsave_mask = compute_vrsave_mask ();
00b960c7 12035 else
4d774ff8
HP		 12036 info_ptr->vrsave_mask = 0;
12037
12038 if (TARGET_ALTIVEC_VRSAVE && info_ptr->vrsave_mask)
12039 info_ptr->vrsave_size = 4;
12040 else
12041 info_ptr->vrsave_size = 0;
b6c9286a 12042
d62294f5
FJ		 12043 compute_save_world_info (info_ptr);
12044
592696dd 12045 /* Calculate the offsets. */
178274da 12046 switch (DEFAULT_ABI)
4697a36c 12047 {
b6c9286a 12048 case ABI_NONE:
24d304eb 12049 default:
37409796 12050 gcc_unreachable ();
b6c9286a
MM		 12051
12052 case ABI_AIX:
ee890fe2 12053 case ABI_DARWIN:
b6c9286a
MM		 12054 info_ptr->fp_save_offset = - info_ptr->fp_size;
12055 info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size;
00b960c7
AH		 12056
12057 if (TARGET_ALTIVEC_ABI)
12058 {
12059 info_ptr->vrsave_save_offset
12060 = info_ptr->gp_save_offset - info_ptr->vrsave_size;
12061
12062 /* Align stack so vector save area is on a quadword boundary. */
12063 if (info_ptr->altivec_size != 0)
12064 info_ptr->altivec_padding_size
12065 = 16 - (-info_ptr->vrsave_save_offset % 16);
12066 else
12067 info_ptr->altivec_padding_size = 0;
12068
12069 info_ptr->altivec_save_offset
12070 = info_ptr->vrsave_save_offset
12071 - info_ptr->altivec_padding_size
12072 - info_ptr->altivec_size;
12073
12074 /* Adjust for AltiVec case. */
12075 info_ptr->ehrd_offset = info_ptr->altivec_save_offset - ehrd_size;
12076 }
12077 else
12078 info_ptr->ehrd_offset = info_ptr->gp_save_offset - ehrd_size;
a260abc9
DE		 12079 info_ptr->cr_save_offset = reg_size; /* first word when 64-bit. */
12080 info_ptr->lr_save_offset = 2*reg_size;
24d304eb
RK		 12081 break;
12082
12083 case ABI_V4:
b6c9286a
MM		 12084 info_ptr->fp_save_offset = - info_ptr->fp_size;
12085 info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size;
a7df97e6 12086 info_ptr->cr_save_offset = info_ptr->gp_save_offset - info_ptr->cr_size;
00b960c7 12087
c19de7aa 12088 if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
c4ad648e
AM		 12089 {
12090 /* Align stack so SPE GPR save area is aligned on a
12091 double-word boundary. */
12092 if (info_ptr->spe_gp_size != 0)
12093 info_ptr->spe_padding_size
12094 = 8 - (-info_ptr->cr_save_offset % 8);
12095 else
12096 info_ptr->spe_padding_size = 0;
12097
12098 info_ptr->spe_gp_save_offset
12099 = info_ptr->cr_save_offset
12100 - info_ptr->spe_padding_size
12101 - info_ptr->spe_gp_size;
12102
12103 /* Adjust for SPE case. */
12104 info_ptr->toc_save_offset
12105 = info_ptr->spe_gp_save_offset - info_ptr->toc_size;
12106 }
a3170dc6 12107 else if (TARGET_ALTIVEC_ABI)
00b960c7
AH		 12108 {
12109 info_ptr->vrsave_save_offset
12110 = info_ptr->cr_save_offset - info_ptr->vrsave_size;
12111
12112 /* Align stack so vector save area is on a quadword boundary. */
12113 if (info_ptr->altivec_size != 0)
12114 info_ptr->altivec_padding_size
12115 = 16 - (-info_ptr->vrsave_save_offset % 16);
12116 else
12117 info_ptr->altivec_padding_size = 0;
12118
12119 info_ptr->altivec_save_offset
12120 = info_ptr->vrsave_save_offset
12121 - info_ptr->altivec_padding_size
12122 - info_ptr->altivec_size;
12123
12124 /* Adjust for AltiVec case. */
12125 info_ptr->toc_save_offset
12126 = info_ptr->altivec_save_offset - info_ptr->toc_size;
12127 }
12128 else
12129 info_ptr->toc_save_offset = info_ptr->cr_save_offset - info_ptr->toc_size;
83720594 12130 info_ptr->ehrd_offset = info_ptr->toc_save_offset - ehrd_size;
b6c9286a
MM		 12131 info_ptr->lr_save_offset = reg_size;
12132 break;
4697a36c
MM		 12133 }
12134
64045029 12135 save_align = (TARGET_ALTIVEC_ABI || DEFAULT_ABI == ABI_DARWIN) ? 16 : 8;
00b960c7
AH		 12136 info_ptr->save_size = RS6000_ALIGN (info_ptr->fp_size
12137 + info_ptr->gp_size
12138 + info_ptr->altivec_size
12139 + info_ptr->altivec_padding_size
a3170dc6
AH		 12140 + info_ptr->spe_gp_size
12141 + info_ptr->spe_padding_size
00b960c7
AH		 12142 + ehrd_size
12143 + info_ptr->cr_size
12144 + info_ptr->lr_size
12145 + info_ptr->vrsave_size
12146 + info_ptr->toc_size,
64045029 12147 save_align);
00b960c7 12148
44688022 12149 non_fixed_size = (info_ptr->vars_size
ff381587 12150 + info_ptr->parm_size
ff381587 12151 + info_ptr->save_size
44688022 12152 + info_ptr->varargs_size);
ff381587 12153
44688022
AM		 12154 info_ptr->total_size = RS6000_ALIGN (non_fixed_size + info_ptr->fixed_size,
12155 ABI_STACK_BOUNDARY / BITS_PER_UNIT);
ff381587
MM		 12156
12157 /* Determine if we need to allocate any stack frame:
12158
a4f6c312
SS		 12159 For AIX we need to push the stack if a frame pointer is needed
12160 (because the stack might be dynamically adjusted), if we are
12161 debugging, if we make calls, or if the sum of fp_save, gp_save,
12162 and local variables are more than the space needed to save all
12163 non-volatile registers: 32-bit: 18*8 + 19*4 = 220 or 64-bit: 18*8
12164 + 18*8 = 288 (GPR13 reserved).
ff381587 12165
a4f6c312
SS		 12166 For V.4 we don't have the stack cushion that AIX uses, but assume
12167 that the debugger can handle stackless frames. */
ff381587
MM		 12168
12169 if (info_ptr->calls_p)
12170 info_ptr->push_p = 1;
12171
178274da 12172 else if (DEFAULT_ABI == ABI_V4)
44688022 12173 info_ptr->push_p = non_fixed_size != 0;
ff381587 12174
178274da
AM		 12175 else if (frame_pointer_needed)
12176 info_ptr->push_p = 1;
12177
12178 else if (TARGET_XCOFF && write_symbols != NO_DEBUG)
12179 info_ptr->push_p = 1;
12180
ff381587 12181 else
44688022 12182 info_ptr->push_p = non_fixed_size > (TARGET_32BIT ? 220 : 288);
ff381587 12183
a4f6c312 12184 /* Zero offsets if we're not saving those registers. */
8dda1a21 12185 if (info_ptr->fp_size == 0)
4697a36c
MM		 12186 info_ptr->fp_save_offset = 0;
12187
8dda1a21 12188 if (info_ptr->gp_size == 0)
4697a36c
MM		 12189 info_ptr->gp_save_offset = 0;
12190
00b960c7
AH		 12191 if (! TARGET_ALTIVEC_ABI || info_ptr->altivec_size == 0)
12192 info_ptr->altivec_save_offset = 0;
12193
12194 if (! TARGET_ALTIVEC_ABI || info_ptr->vrsave_mask == 0)
12195 info_ptr->vrsave_save_offset = 0;
12196
c19de7aa
AH		 12197 if (! TARGET_SPE_ABI
12198 || info_ptr->spe_64bit_regs_used == 0
12199 || info_ptr->spe_gp_size == 0)
a3170dc6
AH		 12200 info_ptr->spe_gp_save_offset = 0;
12201
c81fc13e 12202 if (! info_ptr->lr_save_p)
4697a36c
MM		 12203 info_ptr->lr_save_offset = 0;
12204
c81fc13e 12205 if (! info_ptr->cr_save_p)
4697a36c
MM		 12206 info_ptr->cr_save_offset = 0;
12207
c81fc13e 12208 if (! info_ptr->toc_save_p)
b6c9286a
MM		 12209 info_ptr->toc_save_offset = 0;
12210
4697a36c
MM		 12211 return info_ptr;
12212}
12213
c19de7aa
AH		 12214/* Return true if the current function uses any GPRs in 64-bit SIMD
12215 mode. */
12216
12217static bool
863d938c 12218spe_func_has_64bit_regs_p (void)
c19de7aa
AH		 12219{
12220 rtx insns, insn;
12221
12222 /* Functions that save and restore all the call-saved registers will
12223 need to save/restore the registers in 64-bits. */
12224 if (current_function_calls_eh_return
12225 || current_function_calls_setjmp
12226 || current_function_has_nonlocal_goto)
12227 return true;
12228
12229 insns = get_insns ();
12230
12231 for (insn = NEXT_INSN (insns); insn != NULL_RTX; insn = NEXT_INSN (insn))
12232 {
12233 if (INSN_P (insn))
12234 {
12235 rtx i;
12236
b5a5beb9
AH		 12237 /* FIXME: This should be implemented with attributes...
12238
12239 (set_attr "spe64" "true")....then,
12240 if (get_spe64(insn)) return true;
12241
12242 It's the only reliable way to do the stuff below. */
12243
c19de7aa 12244 i = PATTERN (insn);
f82f556d
AH		 12245 if (GET_CODE (i) == SET)
12246 {
12247 enum machine_mode mode = GET_MODE (SET_SRC (i));
12248
12249 if (SPE_VECTOR_MODE (mode))
12250 return true;
12251 if (TARGET_E500_DOUBLE && mode == DFmode)
12252 return true;
12253 }
c19de7aa
AH		 12254 }
12255 }
12256
12257 return false;
12258}
12259
d1d0c603 12260static void
a2369ed3 12261debug_stack_info (rs6000_stack_t *info)
9878760c 12262{
d330fd93 12263 const char *abi_string;
24d304eb 12264
c81fc13e 12265 if (! info)
4697a36c
MM		 12266 info = rs6000_stack_info ();
12267
12268 fprintf (stderr, "\nStack information for function %s:\n",
12269 ((current_function_decl && DECL_NAME (current_function_decl))
12270 ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl))
12271 : "<unknown>"));
12272
24d304eb
RK		 12273 switch (info->abi)
12274 {
b6c9286a
MM		 12275 default: abi_string = "Unknown"; break;
12276 case ABI_NONE: abi_string = "NONE"; break;
50d440bc 12277 case ABI_AIX: abi_string = "AIX"; break;
ee890fe2 12278 case ABI_DARWIN: abi_string = "Darwin"; break;
b6c9286a 12279 case ABI_V4: abi_string = "V.4"; break;
24d304eb
RK		 12280 }
12281
12282 fprintf (stderr, "\tABI = %5s\n", abi_string);
12283
00b960c7
AH		 12284 if (TARGET_ALTIVEC_ABI)
12285 fprintf (stderr, "\tALTIVEC ABI extensions enabled.\n");
12286
a3170dc6
AH		 12287 if (TARGET_SPE_ABI)
12288 fprintf (stderr, "\tSPE ABI extensions enabled.\n");
12289
4697a36c
MM		 12290 if (info->first_gp_reg_save != 32)
12291 fprintf (stderr, "\tfirst_gp_reg_save = %5d\n", info->first_gp_reg_save);
12292
12293 if (info->first_fp_reg_save != 64)
12294 fprintf (stderr, "\tfirst_fp_reg_save = %5d\n", info->first_fp_reg_save);
9878760c 12295
00b960c7
AH		 12296 if (info->first_altivec_reg_save <= LAST_ALTIVEC_REGNO)
12297 fprintf (stderr, "\tfirst_altivec_reg_save = %5d\n",
12298 info->first_altivec_reg_save);
12299
4697a36c
MM		 12300 if (info->lr_save_p)
12301 fprintf (stderr, "\tlr_save_p = %5d\n", info->lr_save_p);
9878760c 12302
4697a36c
MM		 12303 if (info->cr_save_p)
12304 fprintf (stderr, "\tcr_save_p = %5d\n", info->cr_save_p);
12305
b6c9286a
MM		 12306 if (info->toc_save_p)
12307 fprintf (stderr, "\ttoc_save_p = %5d\n", info->toc_save_p);
12308
00b960c7
AH		 12309 if (info->vrsave_mask)
12310 fprintf (stderr, "\tvrsave_mask = 0x%x\n", info->vrsave_mask);
12311
4697a36c
MM		 12312 if (info->push_p)
12313 fprintf (stderr, "\tpush_p = %5d\n", info->push_p);
12314
12315 if (info->calls_p)
12316 fprintf (stderr, "\tcalls_p = %5d\n", info->calls_p);
12317
4697a36c
MM		 12318 if (info->gp_save_offset)
12319 fprintf (stderr, "\tgp_save_offset = %5d\n", info->gp_save_offset);
12320
12321 if (info->fp_save_offset)
12322 fprintf (stderr, "\tfp_save_offset = %5d\n", info->fp_save_offset);
12323
00b960c7
AH		 12324 if (info->altivec_save_offset)
12325 fprintf (stderr, "\taltivec_save_offset = %5d\n",
12326 info->altivec_save_offset);
12327
a3170dc6
AH		 12328 if (info->spe_gp_save_offset)
12329 fprintf (stderr, "\tspe_gp_save_offset = %5d\n",
12330 info->spe_gp_save_offset);
12331
00b960c7
AH		 12332 if (info->vrsave_save_offset)
12333 fprintf (stderr, "\tvrsave_save_offset = %5d\n",
12334 info->vrsave_save_offset);
12335
4697a36c
MM		 12336 if (info->lr_save_offset)
12337 fprintf (stderr, "\tlr_save_offset = %5d\n", info->lr_save_offset);
12338
12339 if (info->cr_save_offset)
12340 fprintf (stderr, "\tcr_save_offset = %5d\n", info->cr_save_offset);
12341
b6c9286a
MM		 12342 if (info->toc_save_offset)
12343 fprintf (stderr, "\ttoc_save_offset = %5d\n", info->toc_save_offset);
12344
4697a36c
MM		 12345 if (info->varargs_save_offset)
12346 fprintf (stderr, "\tvarargs_save_offset = %5d\n", info->varargs_save_offset);
12347
12348 if (info->total_size)
d1d0c603
JJ		 12349 fprintf (stderr, "\ttotal_size = "HOST_WIDE_INT_PRINT_DEC"\n",
12350 info->total_size);
4697a36c
MM		 12351
12352 if (info->varargs_size)
12353 fprintf (stderr, "\tvarargs_size = %5d\n", info->varargs_size);
12354
12355 if (info->vars_size)
d1d0c603
JJ		 12356 fprintf (stderr, "\tvars_size = "HOST_WIDE_INT_PRINT_DEC"\n",
12357 info->vars_size);
4697a36c
MM		 12358
12359 if (info->parm_size)
12360 fprintf (stderr, "\tparm_size = %5d\n", info->parm_size);
12361
12362 if (info->fixed_size)
12363 fprintf (stderr, "\tfixed_size = %5d\n", info->fixed_size);
12364
12365 if (info->gp_size)
12366 fprintf (stderr, "\tgp_size = %5d\n", info->gp_size);
12367
a3170dc6
AH		 12368 if (info->spe_gp_size)
12369 fprintf (stderr, "\tspe_gp_size = %5d\n", info->spe_gp_size);
12370
4697a36c
MM		 12371 if (info->fp_size)
12372 fprintf (stderr, "\tfp_size = %5d\n", info->fp_size);
12373
00b960c7
AH		 12374 if (info->altivec_size)
12375 fprintf (stderr, "\taltivec_size = %5d\n", info->altivec_size);
12376
12377 if (info->vrsave_size)
12378 fprintf (stderr, "\tvrsave_size = %5d\n", info->vrsave_size);
12379
12380 if (info->altivec_padding_size)
12381 fprintf (stderr, "\taltivec_padding_size= %5d\n",
12382 info->altivec_padding_size);
12383
a3170dc6
AH		 12384 if (info->spe_padding_size)
12385 fprintf (stderr, "\tspe_padding_size = %5d\n",
12386 info->spe_padding_size);
12387
a4f6c312 12388 if (info->lr_size)
ed947a96 12389 fprintf (stderr, "\tlr_size = %5d\n", info->lr_size);
b6c9286a 12390
4697a36c
MM		 12391 if (info->cr_size)
12392 fprintf (stderr, "\tcr_size = %5d\n", info->cr_size);
12393
a4f6c312 12394 if (info->toc_size)
b6c9286a
MM		 12395 fprintf (stderr, "\ttoc_size = %5d\n", info->toc_size);
12396
4697a36c
MM		 12397 if (info->save_size)
12398 fprintf (stderr, "\tsave_size = %5d\n", info->save_size);
12399
12400 if (info->reg_size != 4)
12401 fprintf (stderr, "\treg_size = %5d\n", info->reg_size);
12402
12403 fprintf (stderr, "\n");
9878760c 12404}
71f123ca
FS		 12405
12406rtx
a2369ed3 12407rs6000_return_addr (int count, rtx frame)
71f123ca 12408{
a4f6c312
SS		 12409 /* Currently we don't optimize very well between prolog and body
12410 code and for PIC code the code can be actually quite bad, so
12411 don't try to be too clever here. */
f1384257 12412 if (count != 0 || (DEFAULT_ABI != ABI_AIX && flag_pic))
71f123ca
FS		 12413 {
12414 cfun->machine->ra_needs_full_frame = 1;
8ac61af7
RK		 12415
12416 return
12417 gen_rtx_MEM
12418 (Pmode,
12419 memory_address
12420 (Pmode,
12421 plus_constant (copy_to_reg
12422 (gen_rtx_MEM (Pmode,
12423 memory_address (Pmode, frame))),
12424 RETURN_ADDRESS_OFFSET)));
71f123ca
FS		 12425 }
12426
8c29550d 12427 cfun->machine->ra_need_lr = 1;
9e2f7ec7 12428 return get_hard_reg_initial_val (Pmode, LINK_REGISTER_REGNUM);
71f123ca
FS		 12429}
12430
5e1bf043
DJ		 12431/* Say whether a function is a candidate for sibcall handling or not.
12432 We do not allow indirect calls to be optimized into sibling calls.
12433 Also, we can't do it if there are any vector parameters; there's
12434 nowhere to put the VRsave code so it works; note that functions with
12435 vector parameters are required to have a prototype, so the argument
12436 type info must be available here. (The tail recursion case can work
12437 with vector parameters, but there's no way to distinguish here.) */
4977bab6 12438static bool
a2369ed3 12439rs6000_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
5e1bf043
DJ		 12440{
12441 tree type;
4977bab6 12442 if (decl)
5e1bf043
DJ		 12443 {
12444 if (TARGET_ALTIVEC_VRSAVE)
c4ad648e 12445 {
4977bab6 12446 for (type = TYPE_ARG_TYPES (TREE_TYPE (decl));
5e1bf043
DJ		 12447 type; type = TREE_CHAIN (type))
12448 {
c15b529f 12449 if (TREE_CODE (TREE_VALUE (type)) == VECTOR_TYPE)
4977bab6 12450 return false;
5e1bf043 12451 }
c4ad648e 12452 }
5e1bf043 12453 if (DEFAULT_ABI == ABI_DARWIN
4977bab6 12454 || (*targetm.binds_local_p) (decl))
2bcc50d0 12455 {
4977bab6 12456 tree attr_list = TYPE_ATTRIBUTES (TREE_TYPE (decl));
2bcc50d0
AM		 12457
12458 if (!lookup_attribute ("longcall", attr_list)
12459 || lookup_attribute ("shortcall", attr_list))
4977bab6 12460 return true;
2bcc50d0 12461 }
5e1bf043 12462 }
4977bab6 12463 return false;
5e1bf043
DJ		 12464}
12465
71f123ca 12466static int
863d938c 12467rs6000_ra_ever_killed (void)
71f123ca
FS		 12468{
12469 rtx top;
5e1bf043
DJ		 12470 rtx reg;
12471 rtx insn;
71f123ca 12472
dd292d0a 12473 if (current_function_is_thunk)
71f123ca 12474 return 0;
eb0424da 12475
36f7e964
AH		 12476 /* regs_ever_live has LR marked as used if any sibcalls are present,
12477 but this should not force saving and restoring in the
12478 pro/epilogue. Likewise, reg_set_between_p thinks a sibcall
a3c9585f 12479 clobbers LR, so that is inappropriate. */
36f7e964 12480
5e1bf043
DJ		 12481 /* Also, the prologue can generate a store into LR that
12482 doesn't really count, like this:
36f7e964 12483
5e1bf043
DJ		 12484 move LR->R0
12485 bcl to set PIC register
12486 move LR->R31
12487 move R0->LR
36f7e964
AH		 12488
12489 When we're called from the epilogue, we need to avoid counting
12490 this as a store. */
f676971a 12491
71f123ca
FS		 12492 push_topmost_sequence ();
12493 top = get_insns ();
12494 pop_topmost_sequence ();
5e1bf043 12495 reg = gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM);
71f123ca 12496
5e1bf043
DJ		 12497 for (insn = NEXT_INSN (top); insn != NULL_RTX; insn = NEXT_INSN (insn))
12498 {
12499 if (INSN_P (insn))
12500 {
12501 if (FIND_REG_INC_NOTE (insn, reg))
12502 return 1;
f676971a 12503 else if (GET_CODE (insn) == CALL_INSN
c15b529f 12504 && !SIBLING_CALL_P (insn))
5e1bf043 12505 return 1;
36f7e964
AH		 12506 else if (set_of (reg, insn) != NULL_RTX
12507 && !prologue_epilogue_contains (insn))
5e1bf043
DJ		 12508 return 1;
12509 }
12510 }
12511 return 0;
71f123ca 12512}
4697a36c 12513\f
8cd8f856
GK		 12514/* Add a REG_MAYBE_DEAD note to the insn. */
12515static void
a2369ed3 12516rs6000_maybe_dead (rtx insn)
8cd8f856
GK		 12517{
12518 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD,
12519 const0_rtx,
12520 REG_NOTES (insn));
12521}
12522
9ebbca7d 12523/* Emit instructions needed to load the TOC register.
c7ca610e 12524 This is only needed when TARGET_TOC, TARGET_MINIMAL_TOC, and there is
9ebbca7d 12525 a constant pool; or for SVR4 -fpic. */
c7ca610e
RK		 12526
12527void
a2369ed3 12528rs6000_emit_load_toc_table (int fromprolog)
c7ca610e 12529{
027fbf43 12530 rtx dest, insn;
1db02437 12531 dest = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
c7ca610e 12532
20b71b17
AM		 12533 if (TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 1)
12534 {
12535 rtx temp = (fromprolog
12536 ? gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)
12537 : gen_reg_rtx (Pmode));
027fbf43
JJ		 12538 insn = emit_insn (gen_load_toc_v4_pic_si (temp));
12539 if (fromprolog)
12540 rs6000_maybe_dead (insn);
12541 insn = emit_move_insn (dest, temp);
12542 if (fromprolog)
12543 rs6000_maybe_dead (insn);
20b71b17
AM		 12544 }
12545 else if (TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2)
12546 {
12547 char buf[30];
12548 rtx tempLR = (fromprolog
12549 ? gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)
12550 : gen_reg_rtx (Pmode));
12551 rtx temp0 = (fromprolog
12552 ? gen_rtx_REG (Pmode, 0)
12553 : gen_reg_rtx (Pmode));
20b71b17 12554
20b71b17
AM		 12555 if (fromprolog)
12556 {
ccbca5e4 12557 rtx symF, symL;
38c1f2d7 12558
20b71b17
AM		 12559 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
12560 symF = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
9ebbca7d 12561
20b71b17
AM		 12562 ASM_GENERATE_INTERNAL_LABEL (buf, "LCL", rs6000_pic_labelno);
12563 symL = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
12564
12565 rs6000_maybe_dead (emit_insn (gen_load_toc_v4_PIC_1 (tempLR,
12566 symF)));
12567 rs6000_maybe_dead (emit_move_insn (dest, tempLR));
12568 rs6000_maybe_dead (emit_insn (gen_load_toc_v4_PIC_2 (temp0, dest,
12569 symL,
12570 symF)));
9ebbca7d
GK		 12571 }
12572 else
20b71b17
AM		 12573 {
12574 rtx tocsym;
20b71b17
AM		 12575
12576 tocsym = gen_rtx_SYMBOL_REF (Pmode, toc_label_name);
ccbca5e4 12577 emit_insn (gen_load_toc_v4_PIC_1b (tempLR, tocsym));
027fbf43
JJ		 12578 emit_move_insn (dest, tempLR);
12579 emit_move_insn (temp0, gen_rtx_MEM (Pmode, dest));
20b71b17 12580 }
027fbf43
JJ		 12581 insn = emit_insn (gen_addsi3 (dest, temp0, dest));
12582 if (fromprolog)
12583 rs6000_maybe_dead (insn);
9ebbca7d 12584 }
20b71b17
AM		 12585 else if (TARGET_ELF && !TARGET_AIX && flag_pic == 0 && TARGET_MINIMAL_TOC)
12586 {
12587 /* This is for AIX code running in non-PIC ELF32. */
12588 char buf[30];
12589 rtx realsym;
12590 ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1);
12591 realsym = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
12592
027fbf43
JJ		 12593 insn = emit_insn (gen_elf_high (dest, realsym));
12594 if (fromprolog)
12595 rs6000_maybe_dead (insn);
12596 insn = emit_insn (gen_elf_low (dest, dest, realsym));
12597 if (fromprolog)
12598 rs6000_maybe_dead (insn);
20b71b17 12599 }
37409796 12600 else
9ebbca7d 12601 {
37409796
NS		 12602 gcc_assert (DEFAULT_ABI == ABI_AIX);
12603
9ebbca7d 12604 if (TARGET_32BIT)
027fbf43 12605 insn = emit_insn (gen_load_toc_aix_si (dest));
9ebbca7d 12606 else
027fbf43
JJ		 12607 insn = emit_insn (gen_load_toc_aix_di (dest));
12608 if (fromprolog)
12609 rs6000_maybe_dead (insn);
9ebbca7d
GK		 12610 }
12611}
12612
d1d0c603
JJ		 12613/* Emit instructions to restore the link register after determining where
12614 its value has been stored. */
12615
12616void
12617rs6000_emit_eh_reg_restore (rtx source, rtx scratch)
12618{
12619 rs6000_stack_t *info = rs6000_stack_info ();
12620 rtx operands[2];
12621
12622 operands[0] = source;
12623 operands[1] = scratch;
12624
12625 if (info->lr_save_p)
12626 {
12627 rtx frame_rtx = stack_pointer_rtx;
12628 HOST_WIDE_INT sp_offset = 0;
12629 rtx tmp;
12630
12631 if (frame_pointer_needed
12632 || current_function_calls_alloca
12633 || info->total_size > 32767)
12634 {
12635 emit_move_insn (operands[1], gen_rtx_MEM (Pmode, frame_rtx));
12636 frame_rtx = operands[1];
12637 }
12638 else if (info->push_p)
12639 sp_offset = info->total_size;
12640
12641 tmp = plus_constant (frame_rtx, info->lr_save_offset + sp_offset);
12642 tmp = gen_rtx_MEM (Pmode, tmp);
12643 emit_move_insn (tmp, operands[0]);
12644 }
12645 else
12646 emit_move_insn (gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM), operands[0]);
12647}
12648
f103e34d
GK		 12649static GTY(()) int set = -1;
12650
f676971a 12651int
863d938c 12652get_TOC_alias_set (void)
9ebbca7d 12653{
f103e34d
GK		 12654 if (set == -1)
12655 set = new_alias_set ();
12656 return set;
f676971a 12657}
9ebbca7d 12658
c1207243 12659/* This returns nonzero if the current function uses the TOC. This is
3c9eb5f4
AM		 12660 determined by the presence of (use (unspec ... UNSPEC_TOC)), which
12661 is generated by the ABI_V4 load_toc_* patterns. */
c954844a 12662#if TARGET_ELF
3c9eb5f4 12663static int
f676971a 12664uses_TOC (void)
9ebbca7d 12665{
c4501e62 12666 rtx insn;
38c1f2d7 12667
c4501e62
JJ		 12668 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
12669 if (INSN_P (insn))
12670 {
12671 rtx pat = PATTERN (insn);
12672 int i;
9ebbca7d 12673
f676971a 12674 if (GET_CODE (pat) == PARALLEL)
c4501e62
JJ		 12675 for (i = 0; i < XVECLEN (pat, 0); i++)
12676 {
12677 rtx sub = XVECEXP (pat, 0, i);
12678 if (GET_CODE (sub) == USE)
12679 {
12680 sub = XEXP (sub, 0);
12681 if (GET_CODE (sub) == UNSPEC
12682 && XINT (sub, 1) == UNSPEC_TOC)
12683 return 1;
12684 }
12685 }
12686 }
12687 return 0;
9ebbca7d 12688}
c954844a 12689#endif
38c1f2d7 12690
9ebbca7d 12691rtx
f676971a 12692create_TOC_reference (rtx symbol)
9ebbca7d 12693{
f676971a 12694 return gen_rtx_PLUS (Pmode,
a8a05998 12695 gen_rtx_REG (Pmode, TOC_REGISTER),
f676971a
EC		 12696 gen_rtx_CONST (Pmode,
12697 gen_rtx_MINUS (Pmode, symbol,
b999aaeb 12698 gen_rtx_SYMBOL_REF (Pmode, toc_label_name))));
9ebbca7d 12699}
38c1f2d7 12700
fc4767bb
JJ		 12701/* If _Unwind_* has been called from within the same module,
12702 toc register is not guaranteed to be saved to 40(1) on function
12703 entry. Save it there in that case. */
c7ca610e 12704
9ebbca7d 12705void
863d938c 12706rs6000_aix_emit_builtin_unwind_init (void)
9ebbca7d
GK		 12707{
12708 rtx mem;
12709 rtx stack_top = gen_reg_rtx (Pmode);
12710 rtx opcode_addr = gen_reg_rtx (Pmode);
fc4767bb
JJ		 12711 rtx opcode = gen_reg_rtx (SImode);
12712 rtx tocompare = gen_reg_rtx (SImode);
12713 rtx no_toc_save_needed = gen_label_rtx ();
9ebbca7d
GK		 12714
12715 mem = gen_rtx_MEM (Pmode, hard_frame_pointer_rtx);
12716 emit_move_insn (stack_top, mem);
12717
fc4767bb
JJ		 12718 mem = gen_rtx_MEM (Pmode,
12719 gen_rtx_PLUS (Pmode, stack_top,
9ebbca7d
GK		 12720 GEN_INT (2 * GET_MODE_SIZE (Pmode))));
12721 emit_move_insn (opcode_addr, mem);
fc4767bb
JJ		 12722 emit_move_insn (opcode, gen_rtx_MEM (SImode, opcode_addr));
12723 emit_move_insn (tocompare, gen_int_mode (TARGET_32BIT ? 0x80410014
2496c7bd 12724 : 0xE8410028, SImode));
9ebbca7d 12725
fc4767bb 12726 do_compare_rtx_and_jump (opcode, tocompare, EQ, 1,
06f4e019 12727 SImode, NULL_RTX, NULL_RTX,
fc4767bb 12728 no_toc_save_needed);
9ebbca7d 12729
fc4767bb
JJ		 12730 mem = gen_rtx_MEM (Pmode,
12731 gen_rtx_PLUS (Pmode, stack_top,
12732 GEN_INT (5 * GET_MODE_SIZE (Pmode))));
12733 emit_move_insn (mem, gen_rtx_REG (Pmode, 2));
12734 emit_label (no_toc_save_needed);
9ebbca7d 12735}
38c1f2d7 12736\f
ba4828e0
RK		 12737/* This ties together stack memory (MEM with an alias set of
12738 rs6000_sr_alias_set) and the change to the stack pointer. */
12739
9ebbca7d 12740static void
863d938c 12741rs6000_emit_stack_tie (void)
9ebbca7d 12742{
ba4828e0
RK		 12743 rtx mem = gen_rtx_MEM (BLKmode, gen_rtx_REG (Pmode, STACK_POINTER_REGNUM));
12744
12745 set_mem_alias_set (mem, rs6000_sr_alias_set);
9ebbca7d
GK		 12746 emit_insn (gen_stack_tie (mem));
12747}
38c1f2d7 12748
9ebbca7d
GK		 12749/* Emit the correct code for allocating stack space, as insns.
12750 If COPY_R12, make sure a copy of the old frame is left in r12.
12751 The generated code may use hard register 0 as a temporary. */
12752
12753static void
a2369ed3 12754rs6000_emit_allocate_stack (HOST_WIDE_INT size, int copy_r12)
38c1f2d7 12755{
9ebbca7d
GK		 12756 rtx insn;
12757 rtx stack_reg = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
12758 rtx tmp_reg = gen_rtx_REG (Pmode, 0);
61168ff1
RS		 12759 rtx todec = gen_int_mode (-size, Pmode);
12760
12761 if (INTVAL (todec) != -size)
12762 {
d4ee4d25 12763 warning (0, "stack frame too large");
61168ff1
RS		 12764 emit_insn (gen_trap ());
12765 return;
12766 }
a157febd
GK		 12767
12768 if (current_function_limit_stack)
12769 {
12770 if (REG_P (stack_limit_rtx)
f676971a 12771 && REGNO (stack_limit_rtx) > 1
a157febd
GK		 12772 && REGNO (stack_limit_rtx) <= 31)
12773 {
5b71a4e7 12774 emit_insn (TARGET_32BIT
9ebbca7d
GK		 12775 ? gen_addsi3 (tmp_reg,
12776 stack_limit_rtx,
12777 GEN_INT (size))
12778 : gen_adddi3 (tmp_reg,
12779 stack_limit_rtx,
12780 GEN_INT (size)));
5b71a4e7 12781
9ebbca7d
GK		 12782 emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg,
12783 const0_rtx));
a157febd
GK		 12784 }
12785 else if (GET_CODE (stack_limit_rtx) == SYMBOL_REF
9ebbca7d 12786 && TARGET_32BIT
f607bc57 12787 && DEFAULT_ABI == ABI_V4)
a157febd 12788 {
9ebbca7d 12789 rtx toload = gen_rtx_CONST (VOIDmode,
f676971a
EC		 12790 gen_rtx_PLUS (Pmode,
12791 stack_limit_rtx,
9ebbca7d 12792 GEN_INT (size)));
5b71a4e7 12793
9ebbca7d
GK		 12794 emit_insn (gen_elf_high (tmp_reg, toload));
12795 emit_insn (gen_elf_low (tmp_reg, tmp_reg, toload));
12796 emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg,
12797 const0_rtx));
a157febd
GK		 12798 }
12799 else
d4ee4d25 12800 warning (0, "stack limit expression is not supported");
a157febd
GK		 12801 }
12802
9ebbca7d
GK		 12803 if (copy_r12 || ! TARGET_UPDATE)
12804 emit_move_insn (gen_rtx_REG (Pmode, 12), stack_reg);
12805
38c1f2d7
MM		 12806 if (TARGET_UPDATE)
12807 {
9ebbca7d 12808 if (size > 32767)
38c1f2d7 12809 {
9ebbca7d 12810 /* Need a note here so that try_split doesn't get confused. */
9390387d 12811 if (get_last_insn () == NULL_RTX)
2e040219 12812 emit_note (NOTE_INSN_DELETED);
9ebbca7d
GK		 12813 insn = emit_move_insn (tmp_reg, todec);
12814 try_split (PATTERN (insn), insn, 0);
12815 todec = tmp_reg;
38c1f2d7 12816 }
5b71a4e7
DE		 12817
12818 insn = emit_insn (TARGET_32BIT
12819 ? gen_movsi_update (stack_reg, stack_reg,
12820 todec, stack_reg)
c4ad648e 12821 : gen_movdi_di_update (stack_reg, stack_reg,
9ebbca7d 12822 todec, stack_reg));
38c1f2d7
MM		 12823 }
12824 else
12825 {
5b71a4e7
DE		 12826 insn = emit_insn (TARGET_32BIT
12827 ? gen_addsi3 (stack_reg, stack_reg, todec)
12828 : gen_adddi3 (stack_reg, stack_reg, todec));
9ebbca7d
GK		 12829 emit_move_insn (gen_rtx_MEM (Pmode, stack_reg),
12830 gen_rtx_REG (Pmode, 12));
12831 }
f676971a 12832
9ebbca7d 12833 RTX_FRAME_RELATED_P (insn) = 1;
f676971a 12834 REG_NOTES (insn) =
9ebbca7d 12835 gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
f676971a 12836 gen_rtx_SET (VOIDmode, stack_reg,
9ebbca7d
GK		 12837 gen_rtx_PLUS (Pmode, stack_reg,
12838 GEN_INT (-size))),
12839 REG_NOTES (insn));
12840}
12841
a4f6c312
SS		 12842/* Add to 'insn' a note which is PATTERN (INSN) but with REG replaced
12843 with (plus:P (reg 1) VAL), and with REG2 replaced with RREG if REG2
12844 is not NULL. It would be nice if dwarf2out_frame_debug_expr could
12845 deduce these equivalences by itself so it wasn't necessary to hold
12846 its hand so much. */
9ebbca7d
GK		 12847
12848static void
f676971a 12849rs6000_frame_related (rtx insn, rtx reg, HOST_WIDE_INT val,
a2369ed3 12850 rtx reg2, rtx rreg)
9ebbca7d
GK		 12851{
12852 rtx real, temp;
12853
e56c4463
JL		 12854 /* copy_rtx will not make unique copies of registers, so we need to
12855 ensure we don't have unwanted sharing here. */
12856 if (reg == reg2)
12857 reg = gen_raw_REG (GET_MODE (reg), REGNO (reg));
12858
12859 if (reg == rreg)
12860 reg = gen_raw_REG (GET_MODE (reg), REGNO (reg));
12861
9ebbca7d
GK		 12862 real = copy_rtx (PATTERN (insn));
12863
89e7058f
AH		 12864 if (reg2 != NULL_RTX)
12865 real = replace_rtx (real, reg2, rreg);
f676971a
EC		 12866
12867 real = replace_rtx (real, reg,
9ebbca7d
GK		 12868 gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode,
12869 STACK_POINTER_REGNUM),
12870 GEN_INT (val)));
f676971a 12871
9ebbca7d
GK		 12872 /* We expect that 'real' is either a SET or a PARALLEL containing
12873 SETs (and possibly other stuff). In a PARALLEL, all the SETs
12874 are important so they all have to be marked RTX_FRAME_RELATED_P. */
12875
12876 if (GET_CODE (real) == SET)
12877 {
12878 rtx set = real;
f676971a 12879
9ebbca7d
GK		 12880 temp = simplify_rtx (SET_SRC (set));
12881 if (temp)
12882 SET_SRC (set) = temp;
12883 temp = simplify_rtx (SET_DEST (set));
12884 if (temp)
12885 SET_DEST (set) = temp;
12886 if (GET_CODE (SET_DEST (set)) == MEM)
38c1f2d7 12887 {
9ebbca7d
GK		 12888 temp = simplify_rtx (XEXP (SET_DEST (set), 0));
12889 if (temp)
12890 XEXP (SET_DEST (set), 0) = temp;
38c1f2d7 12891 }
38c1f2d7 12892 }
37409796 12893 else
9ebbca7d
GK		 12894 {
12895 int i;
37409796
NS		 12896
12897 gcc_assert (GET_CODE (real) == PARALLEL);
9ebbca7d
GK		 12898 for (i = 0; i < XVECLEN (real, 0); i++)
12899 if (GET_CODE (XVECEXP (real, 0, i)) == SET)
12900 {
12901 rtx set = XVECEXP (real, 0, i);
f676971a 12902
9ebbca7d
GK		 12903 temp = simplify_rtx (SET_SRC (set));
12904 if (temp)
12905 SET_SRC (set) = temp;
12906 temp = simplify_rtx (SET_DEST (set));
12907 if (temp)
12908 SET_DEST (set) = temp;
12909 if (GET_CODE (SET_DEST (set)) == MEM)
12910 {
12911 temp = simplify_rtx (XEXP (SET_DEST (set), 0));
12912 if (temp)
12913 XEXP (SET_DEST (set), 0) = temp;
12914 }
12915 RTX_FRAME_RELATED_P (set) = 1;
12916 }
12917 }
c19de7aa
AH		 12918
12919 if (TARGET_SPE)
12920 real = spe_synthesize_frame_save (real);
12921
9ebbca7d
GK		 12922 RTX_FRAME_RELATED_P (insn) = 1;
12923 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
12924 real,
12925 REG_NOTES (insn));
38c1f2d7
MM		 12926}
12927
c19de7aa
AH		 12928/* Given an SPE frame note, return a PARALLEL of SETs with the
12929 original note, plus a synthetic register save. */
12930
12931static rtx
a2369ed3 12932spe_synthesize_frame_save (rtx real)
c19de7aa
AH		 12933{
12934 rtx synth, offset, reg, real2;
12935
12936 if (GET_CODE (real) != SET
12937 || GET_MODE (SET_SRC (real)) != V2SImode)
12938 return real;
12939
12940 /* For the SPE, registers saved in 64-bits, get a PARALLEL for their
12941 frame related note. The parallel contains a set of the register
41f3a930 12942 being saved, and another set to a synthetic register (n+1200).
c19de7aa
AH		 12943 This is so we can differentiate between 64-bit and 32-bit saves.
12944 Words cannot describe this nastiness. */
12945
37409796
NS		 12946 gcc_assert (GET_CODE (SET_DEST (real)) == MEM
12947 && GET_CODE (XEXP (SET_DEST (real), 0)) == PLUS
12948 && GET_CODE (SET_SRC (real)) == REG);
c19de7aa
AH		 12949
12950 /* Transform:
12951 (set (mem (plus (reg x) (const y)))
12952 (reg z))
12953 into:
12954 (set (mem (plus (reg x) (const y+4)))
41f3a930 12955 (reg z+1200))
c19de7aa
AH		 12956 */
12957
12958 real2 = copy_rtx (real);
12959 PUT_MODE (SET_DEST (real2), SImode);
12960 reg = SET_SRC (real2);
12961 real2 = replace_rtx (real2, reg, gen_rtx_REG (SImode, REGNO (reg)));
12962 synth = copy_rtx (real2);
12963
12964 if (BYTES_BIG_ENDIAN)
12965 {
12966 offset = XEXP (XEXP (SET_DEST (real2), 0), 1);
12967 real2 = replace_rtx (real2, offset, GEN_INT (INTVAL (offset) + 4));
12968 }
12969
12970 reg = SET_SRC (synth);
41f3a930 12971
c19de7aa 12972 synth = replace_rtx (synth, reg,
41f3a930 12973 gen_rtx_REG (SImode, REGNO (reg) + 1200));
c19de7aa
AH		 12974
12975 offset = XEXP (XEXP (SET_DEST (synth), 0), 1);
12976 synth = replace_rtx (synth, offset,
12977 GEN_INT (INTVAL (offset)
12978 + (BYTES_BIG_ENDIAN ? 0 : 4)));
12979
12980 RTX_FRAME_RELATED_P (synth) = 1;
12981 RTX_FRAME_RELATED_P (real2) = 1;
12982 if (BYTES_BIG_ENDIAN)
12983 real = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, synth, real2));
12984 else
12985 real = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, real2, synth));
12986
12987 return real;
12988}
12989
00b960c7
AH		 12990/* Returns an insn that has a vrsave set operation with the
12991 appropriate CLOBBERs. */
12992
12993static rtx
a2369ed3 12994generate_set_vrsave (rtx reg, rs6000_stack_t *info, int epiloguep)
00b960c7
AH		 12995{
12996 int nclobs, i;
12997 rtx insn, clobs[TOTAL_ALTIVEC_REGS + 1];
a004eb82 12998 rtx vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO);
00b960c7 12999
a004eb82
AH		 13000 clobs[0]
13001 = gen_rtx_SET (VOIDmode,
13002 vrsave,
13003 gen_rtx_UNSPEC_VOLATILE (SImode,
13004 gen_rtvec (2, reg, vrsave),
13005 30));
00b960c7
AH		 13006
13007 nclobs = 1;
13008
9aa86737
AH		 13009 /* We need to clobber the registers in the mask so the scheduler
13010 does not move sets to VRSAVE before sets of AltiVec registers.
13011
13012 However, if the function receives nonlocal gotos, reload will set
13013 all call saved registers live. We will end up with:
13014
13015 (set (reg 999) (mem))
13016 (parallel [ (set (reg vrsave) (unspec blah))
13017 (clobber (reg 999))])
13018
13019 The clobber will cause the store into reg 999 to be dead, and
13020 flow will attempt to delete an epilogue insn. In this case, we
13021 need an unspec use/set of the register. */
00b960c7
AH		 13022
13023 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
44688022 13024 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
9aa86737
AH		 13025 {
13026 if (!epiloguep || call_used_regs [i])
13027 clobs[nclobs++] = gen_rtx_CLOBBER (VOIDmode,
13028 gen_rtx_REG (V4SImode, i));
13029 else
13030 {
13031 rtx reg = gen_rtx_REG (V4SImode, i);
9aa86737
AH		 13032
13033 clobs[nclobs++]
a004eb82
AH		 13034 = gen_rtx_SET (VOIDmode,
13035 reg,
13036 gen_rtx_UNSPEC (V4SImode,
13037 gen_rtvec (1, reg), 27));
9aa86737
AH		 13038 }
13039 }
00b960c7
AH		 13040
13041 insn = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (nclobs));
13042
13043 for (i = 0; i < nclobs; ++i)
13044 XVECEXP (insn, 0, i) = clobs[i];
13045
13046 return insn;
13047}
13048
89e7058f
AH		 13049/* Save a register into the frame, and emit RTX_FRAME_RELATED_P notes.
13050 Save REGNO into [FRAME_REG + OFFSET] in mode MODE. */
13051
13052static void
f676971a 13053emit_frame_save (rtx frame_reg, rtx frame_ptr, enum machine_mode mode,
d1d0c603 13054 unsigned int regno, int offset, HOST_WIDE_INT total_size)
89e7058f
AH		 13055{
13056 rtx reg, offset_rtx, insn, mem, addr, int_rtx;
13057 rtx replacea, replaceb;
13058
13059 int_rtx = GEN_INT (offset);
13060
13061 /* Some cases that need register indexed addressing. */
13062 if ((TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
4d4cbc0e 13063 || (TARGET_E500_DOUBLE && mode == DFmode)
a3170dc6
AH		 13064 || (TARGET_SPE_ABI
13065 && SPE_VECTOR_MODE (mode)
13066 && !SPE_CONST_OFFSET_OK (offset)))
89e7058f
AH		 13067 {
13068 /* Whomever calls us must make sure r11 is available in the
c4ad648e 13069 flow path of instructions in the prologue. */
89e7058f
AH		 13070 offset_rtx = gen_rtx_REG (Pmode, 11);
13071 emit_move_insn (offset_rtx, int_rtx);
13072
13073 replacea = offset_rtx;
13074 replaceb = int_rtx;
13075 }
13076 else
13077 {
13078 offset_rtx = int_rtx;
13079 replacea = NULL_RTX;
13080 replaceb = NULL_RTX;
13081 }
13082
13083 reg = gen_rtx_REG (mode, regno);
13084 addr = gen_rtx_PLUS (Pmode, frame_reg, offset_rtx);
13085 mem = gen_rtx_MEM (mode, addr);
13086 set_mem_alias_set (mem, rs6000_sr_alias_set);
13087
13088 insn = emit_move_insn (mem, reg);
13089
13090 rs6000_frame_related (insn, frame_ptr, total_size, replacea, replaceb);
13091}
13092
a3170dc6
AH		 13093/* Emit an offset memory reference suitable for a frame store, while
13094 converting to a valid addressing mode. */
13095
13096static rtx
a2369ed3 13097gen_frame_mem_offset (enum machine_mode mode, rtx reg, int offset)
a3170dc6
AH		 13098{
13099 rtx int_rtx, offset_rtx;
13100
13101 int_rtx = GEN_INT (offset);
13102
4d4cbc0e
AH		 13103 if ((TARGET_SPE_ABI && SPE_VECTOR_MODE (mode))
13104 || (TARGET_E500_DOUBLE && mode == DFmode))
a3170dc6
AH		 13105 {
13106 offset_rtx = gen_rtx_REG (Pmode, FIXED_SCRATCH);
13107 emit_move_insn (offset_rtx, int_rtx);
13108 }
13109 else
13110 offset_rtx = int_rtx;
13111
13112 return gen_rtx_MEM (mode, gen_rtx_PLUS (Pmode, reg, offset_rtx));
13113}
13114
699c914a
MS		 13115#ifndef TARGET_FIX_AND_CONTINUE
13116#define TARGET_FIX_AND_CONTINUE 0
13117#endif
13118
9ebbca7d
GK		 13119/* Emit function prologue as insns. */
13120
9878760c 13121void
863d938c 13122rs6000_emit_prologue (void)
9878760c 13123{
4697a36c 13124 rs6000_stack_t *info = rs6000_stack_info ();
0e67400a 13125 enum machine_mode reg_mode = Pmode;
327e5343 13126 int reg_size = TARGET_32BIT ? 4 : 8;
9ebbca7d
GK		 13127 rtx sp_reg_rtx = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
13128 rtx frame_ptr_rtx = gen_rtx_REG (Pmode, 12);
13129 rtx frame_reg_rtx = sp_reg_rtx;
b78d48dd 13130 rtx cr_save_rtx = NULL_RTX;
9ebbca7d
GK		 13131 rtx insn;
13132 int saving_FPRs_inline;
13133 int using_store_multiple;
13134 HOST_WIDE_INT sp_offset = 0;
f676971a 13135
699c914a
MS		 13136 if (TARGET_FIX_AND_CONTINUE)
13137 {
13138 /* gdb on darwin arranges to forward a function from the old
de2ab0ca 13139 address by modifying the first 5 instructions of the function
699c914a
MS		 13140 to branch to the overriding function. This is necessary to
13141 permit function pointers that point to the old function to
13142 actually forward to the new function. */
13143 emit_insn (gen_nop ());
13144 emit_insn (gen_nop ());
de2ab0ca 13145 emit_insn (gen_nop ());
699c914a
MS		 13146 emit_insn (gen_nop ());
13147 emit_insn (gen_nop ());
13148 }
13149
13150 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
13151 {
13152 reg_mode = V2SImode;
13153 reg_size = 8;
13154 }
a3170dc6 13155
9ebbca7d 13156 using_store_multiple = (TARGET_MULTIPLE && ! TARGET_POWERPC64
c19de7aa
AH		 13157 && (!TARGET_SPE_ABI
13158 || info->spe_64bit_regs_used == 0)
9ebbca7d
GK		 13159 && info->first_gp_reg_save < 31);
13160 saving_FPRs_inline = (info->first_fp_reg_save == 64
8c29550d 13161 || FP_SAVE_INLINE (info->first_fp_reg_save)
acd0b319 13162 || current_function_calls_eh_return
8c29550d 13163 || cfun->machine->ra_need_lr);
9ebbca7d
GK		 13164
13165 /* For V.4, update stack before we do any saving and set back pointer. */
fc4767bb 13166 if (info->push_p
acd0b319
AM		 13167 && (DEFAULT_ABI == ABI_V4
13168 || current_function_calls_eh_return))
9ebbca7d
GK		 13169 {
13170 if (info->total_size < 32767)
13171 sp_offset = info->total_size;
13172 else
13173 frame_reg_rtx = frame_ptr_rtx;
f676971a 13174 rs6000_emit_allocate_stack (info->total_size,
9ebbca7d
GK		 13175 (frame_reg_rtx != sp_reg_rtx
13176 && (info->cr_save_p
13177 || info->lr_save_p
13178 || info->first_fp_reg_save < 64
13179 || info->first_gp_reg_save < 32
13180 )));
13181 if (frame_reg_rtx != sp_reg_rtx)
13182 rs6000_emit_stack_tie ();
13183 }
13184
d62294f5 13185 /* Handle world saves specially here. */
f57fe068 13186 if (WORLD_SAVE_P (info))
d62294f5
FJ		 13187 {
13188 int i, j, sz;
13189 rtx treg;
13190 rtvec p;
13191
13192 /* save_world expects lr in r0. */
13193 if (info->lr_save_p)
c4ad648e
AM		 13194 {
13195 insn = emit_move_insn (gen_rtx_REG (Pmode, 0),
13196 gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM));
13197 RTX_FRAME_RELATED_P (insn) = 1;
13198 }
d62294f5
FJ		 13199
13200 /* The SAVE_WORLD and RESTORE_WORLD routines make a number of
c4ad648e 13201 assumptions about the offsets of various bits of the stack
992d08b1 13202 frame. */
37409796
NS		 13203 gcc_assert (info->gp_save_offset == -220
13204 && info->fp_save_offset == -144
13205 && info->lr_save_offset == 8
13206 && info->cr_save_offset == 4
13207 && info->push_p
13208 && info->lr_save_p
13209 && (!current_function_calls_eh_return
13210 || info->ehrd_offset == -432)
13211 && info->vrsave_save_offset == -224
13212 && info->altivec_save_offset == (-224 -16 -192));
d62294f5
FJ		 13213
13214 treg = gen_rtx_REG (SImode, 11);
13215 emit_move_insn (treg, GEN_INT (-info->total_size));
13216
13217 /* SAVE_WORLD takes the caller's LR in R0 and the frame size
c4ad648e 13218 in R11. It also clobbers R12, so beware! */
d62294f5
FJ		 13219
13220 /* Preserve CR2 for save_world prologues */
13221 sz = 6;
13222 sz += 32 - info->first_gp_reg_save;
13223 sz += 64 - info->first_fp_reg_save;
13224 sz += LAST_ALTIVEC_REGNO - info->first_altivec_reg_save + 1;
13225 p = rtvec_alloc (sz);
13226 j = 0;
13227 RTVEC_ELT (p, j++) = gen_rtx_CLOBBER (VOIDmode,
c4ad648e
AM		 13228 gen_rtx_REG (Pmode,
13229 LINK_REGISTER_REGNUM));
d62294f5 13230 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode,
c4ad648e
AM		 13231 gen_rtx_SYMBOL_REF (Pmode,
13232 "*save_world"));
d62294f5 13233 /* We do floats first so that the instruction pattern matches
c4ad648e
AM		 13234 properly. */
13235 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
13236 {
13237 rtx reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i);
13238 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13239 GEN_INT (info->fp_save_offset
13240 + sp_offset + 8 * i));
13241 rtx mem = gen_rtx_MEM (DFmode, addr);
13242 set_mem_alias_set (mem, rs6000_sr_alias_set);
13243
13244 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
13245 }
d62294f5 13246 for (i = 0; info->first_altivec_reg_save + i <= LAST_ALTIVEC_REGNO; i++)
c4ad648e
AM		 13247 {
13248 rtx reg = gen_rtx_REG (V4SImode, info->first_altivec_reg_save + i);
13249 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13250 GEN_INT (info->altivec_save_offset
13251 + sp_offset + 16 * i));
13252 rtx mem = gen_rtx_MEM (V4SImode, addr);
13253 set_mem_alias_set (mem, rs6000_sr_alias_set);
13254
13255 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
13256 }
d62294f5 13257 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
c4ad648e
AM		 13258 {
13259 rtx reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
13260 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13261 GEN_INT (info->gp_save_offset
13262 + sp_offset + reg_size * i));
13263 rtx mem = gen_rtx_MEM (reg_mode, addr);
13264 set_mem_alias_set (mem, rs6000_sr_alias_set);
13265
13266 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
13267 }
13268
13269 {
13270 /* CR register traditionally saved as CR2. */
13271 rtx reg = gen_rtx_REG (reg_mode, CR2_REGNO);
13272 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13273 GEN_INT (info->cr_save_offset
13274 + sp_offset));
13275 rtx mem = gen_rtx_MEM (reg_mode, addr);
13276 set_mem_alias_set (mem, rs6000_sr_alias_set);
13277
13278 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
13279 }
d62294f5
FJ		 13280 /* Prevent any attempt to delete the setting of r0 and treg! */
13281 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode, gen_rtx_REG (Pmode, 0));
13282 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode, treg);
13283 RTVEC_ELT (p, j++) = gen_rtx_CLOBBER (VOIDmode, sp_reg_rtx);
13284
13285 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
13286 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
c4ad648e 13287 NULL_RTX, NULL_RTX);
d62294f5
FJ		 13288
13289 if (current_function_calls_eh_return)
c4ad648e
AM		 13290 {
13291 unsigned int i;
13292 for (i = 0; ; ++i)
13293 {
13294 unsigned int regno = EH_RETURN_DATA_REGNO (i);
13295 if (regno == INVALID_REGNUM)
13296 break;
13297 emit_frame_save (frame_reg_rtx, frame_ptr_rtx, reg_mode, regno,
13298 info->ehrd_offset + sp_offset
13299 + reg_size * (int) i,
13300 info->total_size);
13301 }
13302 }
d62294f5
FJ		 13303 }
13304
9aa86737 13305 /* Save AltiVec registers if needed. */
f57fe068 13306 if (!WORLD_SAVE_P (info) && TARGET_ALTIVEC_ABI && info->altivec_size != 0)
9aa86737
AH		 13307 {
13308 int i;
13309
13310 /* There should be a non inline version of this, for when we
13311 are saving lots of vector registers. */
13312 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
13313 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
13314 {
13315 rtx areg, savereg, mem;
13316 int offset;
13317
13318 offset = info->altivec_save_offset + sp_offset
13319 + 16 * (i - info->first_altivec_reg_save);
13320
13321 savereg = gen_rtx_REG (V4SImode, i);
13322
13323 areg = gen_rtx_REG (Pmode, 0);
13324 emit_move_insn (areg, GEN_INT (offset));
13325
13326 /* AltiVec addressing mode is [reg+reg]. */
13327 mem = gen_rtx_MEM (V4SImode,
13328 gen_rtx_PLUS (Pmode, frame_reg_rtx, areg));
f676971a 13329
9aa86737
AH		 13330 set_mem_alias_set (mem, rs6000_sr_alias_set);
13331
13332 insn = emit_move_insn (mem, savereg);
13333
5c242421
SB		 13334 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
13335 areg, GEN_INT (offset));
9aa86737
AH		 13336 }
13337 }
13338
13339 /* VRSAVE is a bit vector representing which AltiVec registers
13340 are used. The OS uses this to determine which vector
13341 registers to save on a context switch. We need to save
13342 VRSAVE on the stack frame, add whatever AltiVec registers we
13343 used in this function, and do the corresponding magic in the
13344 epilogue. */
13345
4d774ff8 13346 if (TARGET_ALTIVEC && TARGET_ALTIVEC_VRSAVE
bcb604b6 13347 && info->vrsave_mask != 0)
9aa86737 13348 {
a004eb82 13349 rtx reg, mem, vrsave;
9aa86737
AH		 13350 int offset;
13351
eab97e44
AM		 13352 /* Get VRSAVE onto a GPR. Note that ABI_V4 might be using r12
13353 as frame_reg_rtx and r11 as the static chain pointer for
13354 nested functions. */
13355 reg = gen_rtx_REG (SImode, 0);
a004eb82 13356 vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO);
b188f760
AH		 13357 if (TARGET_MACHO)
13358 emit_insn (gen_get_vrsave_internal (reg));
13359 else
13360 emit_insn (gen_rtx_SET (VOIDmode, reg, vrsave));
9aa86737 13361
bcb604b6
FJ		 13362 if (!WORLD_SAVE_P (info))
13363 {
13364 /* Save VRSAVE. */
13365 offset = info->vrsave_save_offset + sp_offset;
13366 mem
13367 = gen_rtx_MEM (SImode,
13368 gen_rtx_PLUS (Pmode, frame_reg_rtx, GEN_INT (offset)));
13369 set_mem_alias_set (mem, rs6000_sr_alias_set);
13370 insn = emit_move_insn (mem, reg);
13371 }
9aa86737
AH		 13372
13373 /* Include the registers in the mask. */
13374 emit_insn (gen_iorsi3 (reg, reg, GEN_INT ((int) info->vrsave_mask)));
13375
13376 insn = emit_insn (generate_set_vrsave (reg, info, 0));
13377 }
13378
9ebbca7d 13379 /* If we use the link register, get it into r0. */
f57fe068 13380 if (!WORLD_SAVE_P (info) && info->lr_save_p)
f8a57be8
GK		 13381 {
13382 insn = emit_move_insn (gen_rtx_REG (Pmode, 0),
13383 gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM));
13384 RTX_FRAME_RELATED_P (insn) = 1;
13385 }
9ebbca7d
GK		 13386
13387 /* If we need to save CR, put it into r12. */
f57fe068 13388 if (!WORLD_SAVE_P (info) && info->cr_save_p && frame_reg_rtx != frame_ptr_rtx)
9ebbca7d 13389 {
f8a57be8 13390 rtx set;
f676971a 13391
9ebbca7d 13392 cr_save_rtx = gen_rtx_REG (SImode, 12);
f8a57be8
GK		 13393 insn = emit_insn (gen_movesi_from_cr (cr_save_rtx));
13394 RTX_FRAME_RELATED_P (insn) = 1;
13395 /* Now, there's no way that dwarf2out_frame_debug_expr is going
13396 to understand '(unspec:SI [(reg:CC 68) ...] UNSPEC_MOVESI_FROM_CR)'.
13397 But that's OK. All we have to do is specify that _one_ condition
13398 code register is saved in this stack slot. The thrower's epilogue
13399 will then restore all the call-saved registers.
13400 We use CR2_REGNO (70) to be compatible with gcc-2.95 on Linux. */
13401 set = gen_rtx_SET (VOIDmode, cr_save_rtx,
13402 gen_rtx_REG (SImode, CR2_REGNO));
13403 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
13404 set,
13405 REG_NOTES (insn));
9ebbca7d
GK		 13406 }
13407
a4f6c312
SS		 13408 /* Do any required saving of fpr's. If only one or two to save, do
13409 it ourselves. Otherwise, call function. */
f57fe068 13410 if (!WORLD_SAVE_P (info) && saving_FPRs_inline)
9ebbca7d
GK		 13411 {
13412 int i;
13413 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
f676971a 13414 if ((regs_ever_live[info->first_fp_reg_save+i]
9ebbca7d 13415 && ! call_used_regs[info->first_fp_reg_save+i]))
89e7058f
AH		 13416 emit_frame_save (frame_reg_rtx, frame_ptr_rtx, DFmode,
13417 info->first_fp_reg_save + i,
13418 info->fp_save_offset + sp_offset + 8 * i,
13419 info->total_size);
9ebbca7d 13420 }
f57fe068 13421 else if (!WORLD_SAVE_P (info) && info->first_fp_reg_save != 64)
9ebbca7d
GK		 13422 {
13423 int i;
13424 char rname[30];
520a57c8 13425 const char *alloc_rname;
9ebbca7d
GK		 13426 rtvec p;
13427 p = rtvec_alloc (2 + 64 - info->first_fp_reg_save);
f676971a
EC		 13428
13429 RTVEC_ELT (p, 0) = gen_rtx_CLOBBER (VOIDmode,
13430 gen_rtx_REG (Pmode,
9ebbca7d
GK		 13431 LINK_REGISTER_REGNUM));
13432 sprintf (rname, "%s%d%s", SAVE_FP_PREFIX,
13433 info->first_fp_reg_save - 32, SAVE_FP_SUFFIX);
a8a05998 13434 alloc_rname = ggc_strdup (rname);
9ebbca7d
GK		 13435 RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode,
13436 gen_rtx_SYMBOL_REF (Pmode,
13437 alloc_rname));
13438 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
13439 {
13440 rtx addr, reg, mem;
13441 reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i);
13442 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
f676971a 13443 GEN_INT (info->fp_save_offset
9ebbca7d
GK		 13444 + sp_offset + 8*i));
13445 mem = gen_rtx_MEM (DFmode, addr);
ba4828e0 13446 set_mem_alias_set (mem, rs6000_sr_alias_set);
9ebbca7d
GK		 13447
13448 RTVEC_ELT (p, i + 2) = gen_rtx_SET (VOIDmode, mem, reg);
13449 }
13450 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
f676971a 13451 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
9ebbca7d
GK		 13452 NULL_RTX, NULL_RTX);
13453 }
b6c9286a 13454
9ebbca7d
GK		 13455 /* Save GPRs. This is done as a PARALLEL if we are using
13456 the store-multiple instructions. */
f57fe068 13457 if (!WORLD_SAVE_P (info) && using_store_multiple)
b6c9286a 13458 {
308c142a 13459 rtvec p;
9ebbca7d
GK		 13460 int i;
13461 p = rtvec_alloc (32 - info->first_gp_reg_save);
9ebbca7d
GK		 13462 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
13463 {
13464 rtx addr, reg, mem;
13465 reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
f676971a
EC		 13466 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13467 GEN_INT (info->gp_save_offset
13468 + sp_offset
9ebbca7d
GK		 13469 + reg_size * i));
13470 mem = gen_rtx_MEM (reg_mode, addr);
ba4828e0 13471 set_mem_alias_set (mem, rs6000_sr_alias_set);
9ebbca7d
GK		 13472
13473 RTVEC_ELT (p, i) = gen_rtx_SET (VOIDmode, mem, reg);
13474 }
13475 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
f676971a 13476 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
9ebbca7d 13477 NULL_RTX, NULL_RTX);
b6c9286a 13478 }
f57fe068 13479 else if (!WORLD_SAVE_P (info))
b6c9286a 13480 {
9ebbca7d
GK		 13481 int i;
13482 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
f676971a 13483 if ((regs_ever_live[info->first_gp_reg_save+i]
b4db40bf
JJ		 13484 && (! call_used_regs[info->first_gp_reg_save+i]
13485 || (i+info->first_gp_reg_save
13486 == RS6000_PIC_OFFSET_TABLE_REGNUM
13487 && TARGET_TOC && TARGET_MINIMAL_TOC)))
1db02437 13488 || (i+info->first_gp_reg_save == RS6000_PIC_OFFSET_TABLE_REGNUM
14f00213 13489 && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0)
f607bc57 13490 || (DEFAULT_ABI == ABI_DARWIN && flag_pic))))
a3170dc6
AH		 13491 {
13492 rtx addr, reg, mem;
13493 reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
13494
c19de7aa 13495 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
a3170dc6
AH		 13496 {
13497 int offset = info->spe_gp_save_offset + sp_offset + 8 * i;
13498 rtx b;
13499
13500 if (!SPE_CONST_OFFSET_OK (offset))
13501 {
13502 b = gen_rtx_REG (Pmode, FIXED_SCRATCH);
13503 emit_move_insn (b, GEN_INT (offset));
13504 }
13505 else
13506 b = GEN_INT (offset);
13507
13508 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, b);
13509 mem = gen_rtx_MEM (V2SImode, addr);
13510 set_mem_alias_set (mem, rs6000_sr_alias_set);
13511 insn = emit_move_insn (mem, reg);
13512
13513 if (GET_CODE (b) == CONST_INT)
13514 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
13515 NULL_RTX, NULL_RTX);
13516 else
13517 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
13518 b, GEN_INT (offset));
13519 }
13520 else
13521 {
f676971a
EC		 13522 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13523 GEN_INT (info->gp_save_offset
13524 + sp_offset
a3170dc6
AH		 13525 + reg_size * i));
13526 mem = gen_rtx_MEM (reg_mode, addr);
13527 set_mem_alias_set (mem, rs6000_sr_alias_set);
13528
13529 insn = emit_move_insn (mem, reg);
f676971a 13530 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
a3170dc6
AH		 13531 NULL_RTX, NULL_RTX);
13532 }
13533 }
9ebbca7d
GK		 13534 }
13535
83720594
RH		 13536 /* ??? There's no need to emit actual instructions here, but it's the
13537 easiest way to get the frame unwind information emitted. */
f57fe068 13538 if (!WORLD_SAVE_P (info) && current_function_calls_eh_return)
83720594 13539 {
78e1b90d
DE		 13540 unsigned int i, regno;
13541
fc4767bb
JJ		 13542 /* In AIX ABI we need to pretend we save r2 here. */
13543 if (TARGET_AIX)
13544 {
13545 rtx addr, reg, mem;
13546
13547 reg = gen_rtx_REG (reg_mode, 2);
13548 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13549 GEN_INT (sp_offset + 5 * reg_size));
13550 mem = gen_rtx_MEM (reg_mode, addr);
13551 set_mem_alias_set (mem, rs6000_sr_alias_set);
13552
13553 insn = emit_move_insn (mem, reg);
f676971a 13554 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
fc4767bb
JJ		 13555 NULL_RTX, NULL_RTX);
13556 PATTERN (insn) = gen_blockage ();
13557 }
13558
83720594
RH		 13559 for (i = 0; ; ++i)
13560 {
83720594
RH		 13561 regno = EH_RETURN_DATA_REGNO (i);
13562 if (regno == INVALID_REGNUM)
13563 break;
13564
89e7058f
AH		 13565 emit_frame_save (frame_reg_rtx, frame_ptr_rtx, reg_mode, regno,
13566 info->ehrd_offset + sp_offset
13567 + reg_size * (int) i,
13568 info->total_size);
83720594
RH		 13569 }
13570 }
13571
9ebbca7d 13572 /* Save lr if we used it. */
f57fe068 13573 if (!WORLD_SAVE_P (info) && info->lr_save_p)
9ebbca7d
GK		 13574 {
13575 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13576 GEN_INT (info->lr_save_offset + sp_offset));
13577 rtx reg = gen_rtx_REG (Pmode, 0);
13578 rtx mem = gen_rtx_MEM (Pmode, addr);
13579 /* This should not be of rs6000_sr_alias_set, because of
13580 __builtin_return_address. */
f676971a 13581
9ebbca7d 13582 insn = emit_move_insn (mem, reg);
f676971a 13583 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
f8a57be8 13584 NULL_RTX, NULL_RTX);
9ebbca7d
GK		 13585 }
13586
13587 /* Save CR if we use any that must be preserved. */
f57fe068 13588 if (!WORLD_SAVE_P (info) && info->cr_save_p)
9ebbca7d
GK		 13589 {
13590 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13591 GEN_INT (info->cr_save_offset + sp_offset));
13592 rtx mem = gen_rtx_MEM (SImode, addr);
f8a57be8
GK		 13593 /* See the large comment above about why CR2_REGNO is used. */
13594 rtx magic_eh_cr_reg = gen_rtx_REG (SImode, CR2_REGNO);
ba4828e0
RK		 13595
13596 set_mem_alias_set (mem, rs6000_sr_alias_set);
9ebbca7d
GK		 13597
13598 /* If r12 was used to hold the original sp, copy cr into r0 now
13599 that it's free. */
13600 if (REGNO (frame_reg_rtx) == 12)
13601 {
f8a57be8
GK		 13602 rtx set;
13603
9ebbca7d 13604 cr_save_rtx = gen_rtx_REG (SImode, 0);
f8a57be8
GK		 13605 insn = emit_insn (gen_movesi_from_cr (cr_save_rtx));
13606 RTX_FRAME_RELATED_P (insn) = 1;
13607 set = gen_rtx_SET (VOIDmode, cr_save_rtx, magic_eh_cr_reg);
13608 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
13609 set,
13610 REG_NOTES (insn));
f676971a 13611
9ebbca7d
GK		 13612 }
13613 insn = emit_move_insn (mem, cr_save_rtx);
13614
f676971a 13615 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
f8a57be8 13616 NULL_RTX, NULL_RTX);
9ebbca7d
GK		 13617 }
13618
f676971a 13619 /* Update stack and set back pointer unless this is V.4,
9ebbca7d 13620 for which it was done previously. */
f57fe068 13621 if (!WORLD_SAVE_P (info) && info->push_p
fc4767bb 13622 && !(DEFAULT_ABI == ABI_V4 || current_function_calls_eh_return))
9ebbca7d
GK		 13623 rs6000_emit_allocate_stack (info->total_size, FALSE);
13624
13625 /* Set frame pointer, if needed. */
13626 if (frame_pointer_needed)
13627 {
f676971a 13628 insn = emit_move_insn (gen_rtx_REG (Pmode, FRAME_POINTER_REGNUM),
9ebbca7d
GK		 13629 sp_reg_rtx);
13630 RTX_FRAME_RELATED_P (insn) = 1;
b6c9286a 13631 }
9878760c 13632
1db02437 13633 /* If we are using RS6000_PIC_OFFSET_TABLE_REGNUM, we need to set it up. */
9ebbca7d 13634 if ((TARGET_TOC && TARGET_MINIMAL_TOC && get_pool_size () != 0)
f607bc57 13635 || (DEFAULT_ABI == ABI_V4 && flag_pic == 1
1db02437 13636 && regs_ever_live[RS6000_PIC_OFFSET_TABLE_REGNUM]))
c4ad648e
AM		 13637 {
13638 /* If emit_load_toc_table will use the link register, we need to save
13639 it. We use R12 for this purpose because emit_load_toc_table
13640 can use register 0. This allows us to use a plain 'blr' to return
13641 from the procedure more often. */
13642 int save_LR_around_toc_setup = (TARGET_ELF
13643 && DEFAULT_ABI != ABI_AIX
13644 && flag_pic
13645 && ! info->lr_save_p
13646 && EDGE_COUNT (EXIT_BLOCK_PTR->preds) > 0);
13647 if (save_LR_around_toc_setup)
13648 {
13649 rtx lr = gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM);
f8a57be8 13650
c4ad648e
AM		 13651 insn = emit_move_insn (frame_ptr_rtx, lr);
13652 rs6000_maybe_dead (insn);
13653 RTX_FRAME_RELATED_P (insn) = 1;
f8a57be8 13654
c4ad648e 13655 rs6000_emit_load_toc_table (TRUE);
f8a57be8 13656
c4ad648e
AM		 13657 insn = emit_move_insn (lr, frame_ptr_rtx);
13658 rs6000_maybe_dead (insn);
13659 RTX_FRAME_RELATED_P (insn) = 1;
13660 }
13661 else
13662 rs6000_emit_load_toc_table (TRUE);
13663 }
ee890fe2 13664
fcce224d 13665#if TARGET_MACHO
ee890fe2
SS		 13666 if (DEFAULT_ABI == ABI_DARWIN
13667 && flag_pic && current_function_uses_pic_offset_table)
13668 {
f8a57be8 13669 rtx lr = gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM);
11abc112 13670 rtx src = machopic_function_base_sym ();
ee890fe2 13671
f8a57be8 13672 rs6000_maybe_dead (emit_insn (gen_load_macho_picbase (lr, src)));
ee890fe2 13673
f676971a 13674 insn = emit_move_insn (gen_rtx_REG (Pmode,
f8a57be8
GK		 13675 RS6000_PIC_OFFSET_TABLE_REGNUM),
13676 lr);
13677 rs6000_maybe_dead (insn);
ee890fe2 13678 }
fcce224d 13679#endif
9ebbca7d
GK		 13680}
13681
9ebbca7d 13682/* Write function prologue. */
a4f6c312 13683
08c148a8 13684static void
f676971a 13685rs6000_output_function_prologue (FILE *file,
a2369ed3 13686 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
9ebbca7d
GK		 13687{
13688 rs6000_stack_t *info = rs6000_stack_info ();
13689
4697a36c
MM		 13690 if (TARGET_DEBUG_STACK)
13691 debug_stack_info (info);
9878760c 13692
a4f6c312
SS		 13693 /* Write .extern for any function we will call to save and restore
13694 fp values. */
13695 if (info->first_fp_reg_save < 64
13696 && !FP_SAVE_INLINE (info->first_fp_reg_save))
4d30c363 13697 fprintf (file, "\t.extern %s%d%s\n\t.extern %s%d%s\n",
4697a36c 13698 SAVE_FP_PREFIX, info->first_fp_reg_save - 32, SAVE_FP_SUFFIX,
a4f6c312
SS		 13699 RESTORE_FP_PREFIX, info->first_fp_reg_save - 32,
13700 RESTORE_FP_SUFFIX);
9878760c 13701
c764f757
RK		 13702 /* Write .extern for AIX common mode routines, if needed. */
13703 if (! TARGET_POWER && ! TARGET_POWERPC && ! common_mode_defined)
13704 {
f6709c70
JW		 13705 fputs ("\t.extern __mulh\n", file);
13706 fputs ("\t.extern __mull\n", file);
13707 fputs ("\t.extern __divss\n", file);
13708 fputs ("\t.extern __divus\n", file);
13709 fputs ("\t.extern __quoss\n", file);
13710 fputs ("\t.extern __quous\n", file);
c764f757
RK		 13711 common_mode_defined = 1;
13712 }
9878760c 13713
9ebbca7d 13714 if (! HAVE_prologue)
979721f8 13715 {
9ebbca7d 13716 start_sequence ();
9dda4cc8 13717
a4f6c312
SS		 13718 /* A NOTE_INSN_DELETED is supposed to be at the start and end of
13719 the "toplevel" insn chain. */
2e040219 13720 emit_note (NOTE_INSN_DELETED);
9ebbca7d 13721 rs6000_emit_prologue ();
2e040219 13722 emit_note (NOTE_INSN_DELETED);
178c3eff 13723
a3c9585f 13724 /* Expand INSN_ADDRESSES so final() doesn't crash. */
178c3eff
DJ		 13725 {
13726 rtx insn;
13727 unsigned addr = 0;
13728 for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
13729 {
13730 INSN_ADDRESSES_NEW (insn, addr);
13731 addr += 4;
13732 }
13733 }
9dda4cc8 13734
9ebbca7d 13735 if (TARGET_DEBUG_STACK)
a4f6c312 13736 debug_rtx_list (get_insns (), 100);
c9d691e9 13737 final (get_insns (), file, FALSE);
9ebbca7d 13738 end_sequence ();
979721f8
MM		 13739 }
13740
9ebbca7d
GK		 13741 rs6000_pic_labelno++;
13742}
f676971a 13743
9ebbca7d 13744/* Emit function epilogue as insns.
9878760c 13745
9ebbca7d
GK		 13746 At present, dwarf2out_frame_debug_expr doesn't understand
13747 register restores, so we don't bother setting RTX_FRAME_RELATED_P
13748 anywhere in the epilogue. Most of the insns below would in any case
13749 need special notes to explain where r11 is in relation to the stack. */
9878760c 13750
9ebbca7d 13751void
a2369ed3 13752rs6000_emit_epilogue (int sibcall)
9ebbca7d
GK		 13753{
13754 rs6000_stack_t *info;
13755 int restoring_FPRs_inline;
13756 int using_load_multiple;
13757 int using_mfcr_multiple;
13758 int use_backchain_to_restore_sp;
13759 int sp_offset = 0;
13760 rtx sp_reg_rtx = gen_rtx_REG (Pmode, 1);
13761 rtx frame_reg_rtx = sp_reg_rtx;
0e67400a 13762 enum machine_mode reg_mode = Pmode;
327e5343 13763 int reg_size = TARGET_32BIT ? 4 : 8;
9ebbca7d
GK		 13764 int i;
13765
c19de7aa
AH		 13766 info = rs6000_stack_info ();
13767
13768 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
a3170dc6
AH		 13769 {
13770 reg_mode = V2SImode;
13771 reg_size = 8;
13772 }
13773
9ebbca7d 13774 using_load_multiple = (TARGET_MULTIPLE && ! TARGET_POWERPC64
c19de7aa
AH		 13775 && (!TARGET_SPE_ABI
13776 || info->spe_64bit_regs_used == 0)
9ebbca7d
GK		 13777 && info->first_gp_reg_save < 31);
13778 restoring_FPRs_inline = (sibcall
83720594 13779 || current_function_calls_eh_return
9ebbca7d
GK		 13780 || info->first_fp_reg_save == 64
13781 || FP_SAVE_INLINE (info->first_fp_reg_save));
f676971a 13782 use_backchain_to_restore_sp = (frame_pointer_needed
9ebbca7d
GK		 13783 || current_function_calls_alloca
13784 || info->total_size > 32767);
13785 using_mfcr_multiple = (rs6000_cpu == PROCESSOR_PPC601
13786 || rs6000_cpu == PROCESSOR_PPC603
13787 || rs6000_cpu == PROCESSOR_PPC750
13788 || optimize_size);
13789
f57fe068 13790 if (WORLD_SAVE_P (info))
d62294f5
FJ		 13791 {
13792 int i, j;
13793 char rname[30];
13794 const char *alloc_rname;
13795 rtvec p;
13796
13797 /* eh_rest_world_r10 will return to the location saved in the LR
c4ad648e
AM		 13798 stack slot (which is not likely to be our caller.)
13799 Input: R10 -- stack adjustment. Clobbers R0, R11, R12, R7, R8.
13800 rest_world is similar, except any R10 parameter is ignored.
13801 The exception-handling stuff that was here in 2.95 is no
13802 longer necessary. */
d62294f5
FJ		 13803
13804 p = rtvec_alloc (9
13805 + 1
f676971a 13806 + 32 - info->first_gp_reg_save
c4ad648e
AM		 13807 + LAST_ALTIVEC_REGNO + 1 - info->first_altivec_reg_save
13808 + 63 + 1 - info->first_fp_reg_save);
d62294f5 13809
c4ad648e
AM		 13810 strcpy (rname, ((current_function_calls_eh_return) ?
13811 "*eh_rest_world_r10" : "*rest_world"));
d62294f5
FJ		 13812 alloc_rname = ggc_strdup (rname);
13813
13814 j = 0;
13815 RTVEC_ELT (p, j++) = gen_rtx_RETURN (VOIDmode);
13816 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode,
c4ad648e
AM		 13817 gen_rtx_REG (Pmode,
13818 LINK_REGISTER_REGNUM));
d62294f5 13819 RTVEC_ELT (p, j++)
c4ad648e 13820 = gen_rtx_USE (VOIDmode, gen_rtx_SYMBOL_REF (Pmode, alloc_rname));
d62294f5 13821 /* The instruction pattern requires a clobber here;
c4ad648e 13822 it is shared with the restVEC helper. */
d62294f5 13823 RTVEC_ELT (p, j++)
c4ad648e 13824 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 11));
d62294f5
FJ		 13825
13826 {
c4ad648e
AM		 13827 /* CR register traditionally saved as CR2. */
13828 rtx reg = gen_rtx_REG (reg_mode, CR2_REGNO);
13829 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13830 GEN_INT (info->cr_save_offset));
13831 rtx mem = gen_rtx_MEM (reg_mode, addr);
13832 set_mem_alias_set (mem, rs6000_sr_alias_set);
13833
13834 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
d62294f5
FJ		 13835 }
13836
13837 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
c4ad648e
AM		 13838 {
13839 rtx reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
13840 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13841 GEN_INT (info->gp_save_offset
13842 + reg_size * i));
13843 rtx mem = gen_rtx_MEM (reg_mode, addr);
13844 set_mem_alias_set (mem, rs6000_sr_alias_set);
13845
13846 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
13847 }
d62294f5 13848 for (i = 0; info->first_altivec_reg_save + i <= LAST_ALTIVEC_REGNO; i++)
c4ad648e
AM		 13849 {
13850 rtx reg = gen_rtx_REG (V4SImode, info->first_altivec_reg_save + i);
13851 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13852 GEN_INT (info->altivec_save_offset
13853 + 16 * i));
13854 rtx mem = gen_rtx_MEM (V4SImode, addr);
13855 set_mem_alias_set (mem, rs6000_sr_alias_set);
13856
13857 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
13858 }
d62294f5 13859 for (i = 0; info->first_fp_reg_save + i <= 63; i++)
c4ad648e
AM		 13860 {
13861 rtx reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i);
13862 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13863 GEN_INT (info->fp_save_offset
13864 + 8 * i));
13865 rtx mem = gen_rtx_MEM (DFmode, addr);
13866 set_mem_alias_set (mem, rs6000_sr_alias_set);
13867
13868 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
13869 }
d62294f5 13870 RTVEC_ELT (p, j++)
c4ad648e 13871 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 0));
d62294f5 13872 RTVEC_ELT (p, j++)
c4ad648e 13873 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 12));
d62294f5 13874 RTVEC_ELT (p, j++)
c4ad648e 13875 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 7));
d62294f5 13876 RTVEC_ELT (p, j++)
c4ad648e 13877 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 8));
d62294f5 13878 RTVEC_ELT (p, j++)
c4ad648e 13879 = gen_rtx_USE (VOIDmode, gen_rtx_REG (SImode, 10));
d62294f5
FJ		 13880 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
13881
13882 return;
13883 }
13884
9ebbca7d
GK		 13885 /* If we have a frame pointer, a call to alloca, or a large stack
13886 frame, restore the old stack pointer using the backchain. Otherwise,
13887 we know what size to update it with. */
13888 if (use_backchain_to_restore_sp)
bacbde18 13889 {
9ebbca7d
GK		 13890 /* Under V.4, don't reset the stack pointer until after we're done
13891 loading the saved registers. */
f607bc57 13892 if (DEFAULT_ABI == ABI_V4)
9ebbca7d 13893 frame_reg_rtx = gen_rtx_REG (Pmode, 11);
4697a36c 13894
9ebbca7d
GK		 13895 emit_move_insn (frame_reg_rtx,
13896 gen_rtx_MEM (Pmode, sp_reg_rtx));
f676971a 13897
bacbde18 13898 }
9ebbca7d 13899 else if (info->push_p)
85638c0d 13900 {
fc4767bb
JJ		 13901 if (DEFAULT_ABI == ABI_V4
13902 || current_function_calls_eh_return)
9ebbca7d
GK		 13903 sp_offset = info->total_size;
13904 else
13905 {
13906 emit_insn (TARGET_32BIT
13907 ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx,
13908 GEN_INT (info->total_size))
13909 : gen_adddi3 (sp_reg_rtx, sp_reg_rtx,
13910 GEN_INT (info->total_size)));
13911 }
85638c0d 13912 }
f676971a 13913
9aa86737
AH		 13914 /* Restore AltiVec registers if needed. */
13915 if (TARGET_ALTIVEC_ABI && info->altivec_size != 0)
13916 {
13917 int i;
13918
13919 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
13920 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
13921 {
13922 rtx addr, areg, mem;
13923
13924 areg = gen_rtx_REG (Pmode, 0);
13925 emit_move_insn
13926 (areg, GEN_INT (info->altivec_save_offset
13927 + sp_offset
13928 + 16 * (i - info->first_altivec_reg_save)));
13929
13930 /* AltiVec addressing mode is [reg+reg]. */
13931 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, areg);
13932 mem = gen_rtx_MEM (V4SImode, addr);
13933 set_mem_alias_set (mem, rs6000_sr_alias_set);
13934
13935 emit_move_insn (gen_rtx_REG (V4SImode, i), mem);
13936 }
13937 }
13938
13939 /* Restore VRSAVE if needed. */
44688022 13940 if (TARGET_ALTIVEC && TARGET_ALTIVEC_VRSAVE
4d774ff8 13941 && info->vrsave_mask != 0)
9aa86737
AH		 13942 {
13943 rtx addr, mem, reg;
13944
13945 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13946 GEN_INT (info->vrsave_save_offset + sp_offset));
13947 mem = gen_rtx_MEM (SImode, addr);
13948 set_mem_alias_set (mem, rs6000_sr_alias_set);
13949 reg = gen_rtx_REG (SImode, 12);
13950 emit_move_insn (reg, mem);
13951
13952 emit_insn (generate_set_vrsave (reg, info, 1));
13953 }
13954
9ebbca7d
GK		 13955 /* Get the old lr if we saved it. */
13956 if (info->lr_save_p)
b6c9286a 13957 {
a3170dc6
AH		 13958 rtx mem = gen_frame_mem_offset (Pmode, frame_reg_rtx,
13959 info->lr_save_offset + sp_offset);
ba4828e0
RK		 13960
13961 set_mem_alias_set (mem, rs6000_sr_alias_set);
b6c9286a 13962
9ebbca7d 13963 emit_move_insn (gen_rtx_REG (Pmode, 0), mem);
b6c9286a 13964 }
f676971a 13965
9ebbca7d
GK		 13966 /* Get the old cr if we saved it. */
13967 if (info->cr_save_p)
13968 {
13969 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13970 GEN_INT (info->cr_save_offset + sp_offset));
13971 rtx mem = gen_rtx_MEM (SImode, addr);
ba4828e0
RK		 13972
13973 set_mem_alias_set (mem, rs6000_sr_alias_set);
b6c9286a 13974
9ebbca7d
GK		 13975 emit_move_insn (gen_rtx_REG (SImode, 12), mem);
13976 }
f676971a 13977
9ebbca7d 13978 /* Set LR here to try to overlap restores below. */
4697a36c 13979 if (info->lr_save_p)
9ebbca7d
GK		 13980 emit_move_insn (gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM),
13981 gen_rtx_REG (Pmode, 0));
f676971a 13982
83720594
RH		 13983 /* Load exception handler data registers, if needed. */
13984 if (current_function_calls_eh_return)
13985 {
78e1b90d
DE		 13986 unsigned int i, regno;
13987
fc4767bb
JJ		 13988 if (TARGET_AIX)
13989 {
13990 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13991 GEN_INT (sp_offset + 5 * reg_size));
13992 rtx mem = gen_rtx_MEM (reg_mode, addr);
13993
13994 set_mem_alias_set (mem, rs6000_sr_alias_set);
13995
13996 emit_move_insn (gen_rtx_REG (reg_mode, 2), mem);
13997 }
13998
83720594
RH		 13999 for (i = 0; ; ++i)
14000 {
a3170dc6 14001 rtx mem;
83720594
RH		 14002
14003 regno = EH_RETURN_DATA_REGNO (i);
14004 if (regno == INVALID_REGNUM)
14005 break;
14006
a3170dc6
AH		 14007 mem = gen_frame_mem_offset (reg_mode, frame_reg_rtx,
14008 info->ehrd_offset + sp_offset
14009 + reg_size * (int) i);
ba4828e0 14010 set_mem_alias_set (mem, rs6000_sr_alias_set);
83720594
RH		 14011
14012 emit_move_insn (gen_rtx_REG (reg_mode, regno), mem);
14013 }
14014 }
f676971a 14015
9ebbca7d
GK		 14016 /* Restore GPRs. This is done as a PARALLEL if we are using
14017 the load-multiple instructions. */
14018 if (using_load_multiple)
979721f8 14019 {
9ebbca7d
GK		 14020 rtvec p;
14021 p = rtvec_alloc (32 - info->first_gp_reg_save);
14022 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
979721f8 14023 {
f676971a
EC		 14024 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14025 GEN_INT (info->gp_save_offset
14026 + sp_offset
9ebbca7d
GK		 14027 + reg_size * i));
14028 rtx mem = gen_rtx_MEM (reg_mode, addr);
ba4828e0
RK		 14029
14030 set_mem_alias_set (mem, rs6000_sr_alias_set);
9ebbca7d 14031
f676971a 14032 RTVEC_ELT (p, i) =
9ebbca7d
GK		 14033 gen_rtx_SET (VOIDmode,
14034 gen_rtx_REG (reg_mode, info->first_gp_reg_save + i),
14035 mem);
979721f8 14036 }
9ebbca7d 14037 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
979721f8 14038 }
9ebbca7d
GK		 14039 else
14040 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
f676971a 14041 if ((regs_ever_live[info->first_gp_reg_save+i]
b4db40bf
JJ		 14042 && (! call_used_regs[info->first_gp_reg_save+i]
14043 || (i+info->first_gp_reg_save == RS6000_PIC_OFFSET_TABLE_REGNUM
14044 && TARGET_TOC && TARGET_MINIMAL_TOC)))
1db02437 14045 || (i+info->first_gp_reg_save == RS6000_PIC_OFFSET_TABLE_REGNUM
14f00213 14046 && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0)
f607bc57 14047 || (DEFAULT_ABI == ABI_DARWIN && flag_pic))))
9ebbca7d 14048 {
f676971a
EC		 14049 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14050 GEN_INT (info->gp_save_offset
14051 + sp_offset
9ebbca7d
GK		 14052 + reg_size * i));
14053 rtx mem = gen_rtx_MEM (reg_mode, addr);
ba4828e0 14054
a3170dc6 14055 /* Restore 64-bit quantities for SPE. */
c19de7aa 14056 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
a3170dc6
AH		 14057 {
14058 int offset = info->spe_gp_save_offset + sp_offset + 8 * i;
14059 rtx b;
14060
14061 if (!SPE_CONST_OFFSET_OK (offset))
14062 {
14063 b = gen_rtx_REG (Pmode, FIXED_SCRATCH);
14064 emit_move_insn (b, GEN_INT (offset));
14065 }
14066 else
14067 b = GEN_INT (offset);
14068
14069 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, b);
14070 mem = gen_rtx_MEM (V2SImode, addr);
14071 }
14072
ba4828e0 14073 set_mem_alias_set (mem, rs6000_sr_alias_set);
9ebbca7d 14074
f676971a 14075 emit_move_insn (gen_rtx_REG (reg_mode,
a3170dc6 14076 info->first_gp_reg_save + i), mem);
9ebbca7d 14077 }
9878760c 14078
9ebbca7d
GK		 14079 /* Restore fpr's if we need to do it without calling a function. */
14080 if (restoring_FPRs_inline)
14081 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
f676971a 14082 if ((regs_ever_live[info->first_fp_reg_save+i]
9ebbca7d
GK		 14083 && ! call_used_regs[info->first_fp_reg_save+i]))
14084 {
14085 rtx addr, mem;
14086 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
f676971a
EC		 14087 GEN_INT (info->fp_save_offset
14088 + sp_offset
a4f6c312 14089 + 8 * i));
9ebbca7d 14090 mem = gen_rtx_MEM (DFmode, addr);
ba4828e0 14091 set_mem_alias_set (mem, rs6000_sr_alias_set);
9ebbca7d 14092
f676971a 14093 emit_move_insn (gen_rtx_REG (DFmode,
9ebbca7d
GK		 14094 info->first_fp_reg_save + i),
14095 mem);
14096 }
8d30c4ee 14097
9ebbca7d
GK		 14098 /* If we saved cr, restore it here. Just those that were used. */
14099 if (info->cr_save_p)
979721f8 14100 {
9ebbca7d 14101 rtx r12_rtx = gen_rtx_REG (SImode, 12);
e35b9579 14102 int count = 0;
f676971a 14103
9ebbca7d 14104 if (using_mfcr_multiple)
979721f8 14105 {
9ebbca7d
GK		 14106 for (i = 0; i < 8; i++)
14107 if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i])
e35b9579 14108 count++;
37409796 14109 gcc_assert (count);
e35b9579
GK		 14110 }
14111
14112 if (using_mfcr_multiple && count > 1)
14113 {
14114 rtvec p;
14115 int ndx;
f676971a 14116
e35b9579 14117 p = rtvec_alloc (count);
9ebbca7d 14118
e35b9579 14119 ndx = 0;
9ebbca7d
GK		 14120 for (i = 0; i < 8; i++)
14121 if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i])
14122 {
14123 rtvec r = rtvec_alloc (2);
14124 RTVEC_ELT (r, 0) = r12_rtx;
14125 RTVEC_ELT (r, 1) = GEN_INT (1 << (7-i));
e35b9579 14126 RTVEC_ELT (p, ndx) =
f676971a 14127 gen_rtx_SET (VOIDmode, gen_rtx_REG (CCmode, CR0_REGNO+i),
615158e2 14128 gen_rtx_UNSPEC (CCmode, r, UNSPEC_MOVESI_TO_CR));
e35b9579 14129 ndx++;
9ebbca7d
GK		 14130 }
14131 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
37409796 14132 gcc_assert (ndx == count);
979721f8
MM		 14133 }
14134 else
9ebbca7d
GK		 14135 for (i = 0; i < 8; i++)
14136 if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i])
979721f8 14137 {
f676971a 14138 emit_insn (gen_movsi_to_cr_one (gen_rtx_REG (CCmode,
9ebbca7d
GK		 14139 CR0_REGNO+i),
14140 r12_rtx));
979721f8 14141 }
979721f8
MM		 14142 }
14143
9ebbca7d
GK		 14144 /* If this is V.4, unwind the stack pointer after all of the loads
14145 have been done. We need to emit a block here so that sched
14146 doesn't decide to move the sp change before the register restores
14147 (which may not have any obvious dependency on the stack). This
14148 doesn't hurt performance, because there is no scheduling that can
14149 be done after this point. */
fc4767bb
JJ		 14150 if (DEFAULT_ABI == ABI_V4
14151 || current_function_calls_eh_return)
b6c9286a 14152 {
9ebbca7d 14153 if (frame_reg_rtx != sp_reg_rtx)
c4ad648e 14154 rs6000_emit_stack_tie ();
b6c9286a 14155
9ebbca7d 14156 if (use_backchain_to_restore_sp)
b6c9286a 14157 {
9ebbca7d 14158 emit_move_insn (sp_reg_rtx, frame_reg_rtx);
b6c9286a 14159 }
9ebbca7d 14160 else if (sp_offset != 0)
13f1623b 14161 {
5b71a4e7 14162 emit_insn (TARGET_32BIT
9ebbca7d
GK		 14163 ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx,
14164 GEN_INT (sp_offset))
14165 : gen_adddi3 (sp_reg_rtx, sp_reg_rtx,
14166 GEN_INT (sp_offset)));
13f1623b 14167 }
9ebbca7d 14168 }
b6c9286a 14169
83720594
RH		 14170 if (current_function_calls_eh_return)
14171 {
14172 rtx sa = EH_RETURN_STACKADJ_RTX;
5b71a4e7 14173 emit_insn (TARGET_32BIT
83720594
RH		 14174 ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx, sa)
14175 : gen_adddi3 (sp_reg_rtx, sp_reg_rtx, sa));
14176 }
14177
9ebbca7d
GK		 14178 if (!sibcall)
14179 {
14180 rtvec p;
14181 if (! restoring_FPRs_inline)
14182 p = rtvec_alloc (3 + 64 - info->first_fp_reg_save);
14183 else
14184 p = rtvec_alloc (2);
b6c9286a 14185
e35b9579 14186 RTVEC_ELT (p, 0) = gen_rtx_RETURN (VOIDmode);
f676971a
EC		 14187 RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode,
14188 gen_rtx_REG (Pmode,
9ebbca7d 14189 LINK_REGISTER_REGNUM));
9ebbca7d
GK		 14190
14191 /* If we have to restore more than two FP registers, branch to the
14192 restore function. It will return to our caller. */
14193 if (! restoring_FPRs_inline)
14194 {
14195 int i;
14196 char rname[30];
520a57c8 14197 const char *alloc_rname;
979721f8 14198
f676971a 14199 sprintf (rname, "%s%d%s", RESTORE_FP_PREFIX,
9ebbca7d 14200 info->first_fp_reg_save - 32, RESTORE_FP_SUFFIX);
a8a05998 14201 alloc_rname = ggc_strdup (rname);
9ebbca7d
GK		 14202 RTVEC_ELT (p, 2) = gen_rtx_USE (VOIDmode,
14203 gen_rtx_SYMBOL_REF (Pmode,
14204 alloc_rname));
b6c9286a 14205
9ebbca7d
GK		 14206 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
14207 {
14208 rtx addr, mem;
14209 addr = gen_rtx_PLUS (Pmode, sp_reg_rtx,
14210 GEN_INT (info->fp_save_offset + 8*i));
14211 mem = gen_rtx_MEM (DFmode, addr);
ba4828e0 14212 set_mem_alias_set (mem, rs6000_sr_alias_set);
9ebbca7d 14213
f676971a 14214 RTVEC_ELT (p, i+3) =
9ebbca7d
GK		 14215 gen_rtx_SET (VOIDmode,
14216 gen_rtx_REG (DFmode, info->first_fp_reg_save + i),
14217 mem);
b6c9286a
MM		 14218 }
14219 }
f676971a 14220
9ebbca7d 14221 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
3daf36a4 14222 }
9878760c
RK		 14223}
14224
14225/* Write function epilogue. */
14226
08c148a8 14227static void
f676971a 14228rs6000_output_function_epilogue (FILE *file,
a2369ed3 14229 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
9878760c 14230{
4697a36c 14231 rs6000_stack_t *info = rs6000_stack_info ();
9878760c 14232
9ebbca7d 14233 if (! HAVE_epilogue)
9878760c 14234 {
9ebbca7d
GK		 14235 rtx insn = get_last_insn ();
14236 /* If the last insn was a BARRIER, we don't have to write anything except
14237 the trace table. */
14238 if (GET_CODE (insn) == NOTE)
14239 insn = prev_nonnote_insn (insn);
14240 if (insn == 0 || GET_CODE (insn) != BARRIER)
4697a36c 14241 {
9ebbca7d
GK		 14242 /* This is slightly ugly, but at least we don't have two
14243 copies of the epilogue-emitting code. */
14244 start_sequence ();
14245
14246 /* A NOTE_INSN_DELETED is supposed to be at the start
14247 and end of the "toplevel" insn chain. */
2e040219 14248 emit_note (NOTE_INSN_DELETED);
9ebbca7d 14249 rs6000_emit_epilogue (FALSE);
2e040219 14250 emit_note (NOTE_INSN_DELETED);
9ebbca7d 14251
a3c9585f 14252 /* Expand INSN_ADDRESSES so final() doesn't crash. */
178c3eff
DJ		 14253 {
14254 rtx insn;
14255 unsigned addr = 0;
14256 for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
14257 {
14258 INSN_ADDRESSES_NEW (insn, addr);
14259 addr += 4;
14260 }
14261 }
14262
9ebbca7d 14263 if (TARGET_DEBUG_STACK)
a4f6c312 14264 debug_rtx_list (get_insns (), 100);
c9d691e9 14265 final (get_insns (), file, FALSE);
9ebbca7d 14266 end_sequence ();
4697a36c 14267 }
9878760c 14268 }
b4ac57ab 14269
efdba735
SH		 14270#if TARGET_MACHO
14271 macho_branch_islands ();
0e5da0be
GK		 14272 /* Mach-O doesn't support labels at the end of objects, so if
14273 it looks like we might want one, insert a NOP. */
14274 {
14275 rtx insn = get_last_insn ();
14276 while (insn
14277 && NOTE_P (insn)
14278 && NOTE_LINE_NUMBER (insn) != NOTE_INSN_DELETED_LABEL)
14279 insn = PREV_INSN (insn);
f676971a
EC		 14280 if (insn
14281 && (LABEL_P (insn)
0e5da0be
GK		 14282 || (NOTE_P (insn)
14283 && NOTE_LINE_NUMBER (insn) == NOTE_INSN_DELETED_LABEL)))
14284 fputs ("\tnop\n", file);
14285 }
14286#endif
14287
9b30bae2 14288 /* Output a traceback table here. See /usr/include/sys/debug.h for info
314fc5a9
ILT		 14289 on its format.
14290
14291 We don't output a traceback table if -finhibit-size-directive was
14292 used. The documentation for -finhibit-size-directive reads
14293 ``don't output a @code{.size} assembler directive, or anything
14294 else that would cause trouble if the function is split in the
14295 middle, and the two halves are placed at locations far apart in
14296 memory.'' The traceback table has this property, since it
14297 includes the offset from the start of the function to the
4d30c363
MM		 14298 traceback table itself.
14299
14300 System V.4 Powerpc's (and the embedded ABI derived from it) use a
b6c9286a 14301 different traceback table. */
57ac7be9
AM		 14302 if (DEFAULT_ABI == ABI_AIX && ! flag_inhibit_size_directive
14303 && rs6000_traceback != traceback_none)
9b30bae2 14304 {
69c75916 14305 const char *fname = NULL;
3ac88239 14306 const char *language_string = lang_hooks.name;
6041bf2f 14307 int fixed_parms = 0, float_parms = 0, parm_info = 0;
314fc5a9 14308 int i;
57ac7be9
AM		 14309 int optional_tbtab;
14310
14311 if (rs6000_traceback == traceback_full)
14312 optional_tbtab = 1;
14313 else if (rs6000_traceback == traceback_part)
14314 optional_tbtab = 0;
14315 else
14316 optional_tbtab = !optimize_size && !TARGET_ELF;
314fc5a9 14317
69c75916
AM		 14318 if (optional_tbtab)
14319 {
14320 fname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
14321 while (*fname == '.') /* V.4 encodes . in the name */
14322 fname++;
14323
14324 /* Need label immediately before tbtab, so we can compute
14325 its offset from the function start. */
14326 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT");
14327 ASM_OUTPUT_LABEL (file, fname);
14328 }
314fc5a9
ILT		 14329
14330 /* The .tbtab pseudo-op can only be used for the first eight
14331 expressions, since it can't handle the possibly variable
14332 length fields that follow. However, if you omit the optional
14333 fields, the assembler outputs zeros for all optional fields
14334 anyways, giving each variable length field is minimum length
14335 (as defined in sys/debug.h). Thus we can not use the .tbtab
14336 pseudo-op at all. */
14337
14338 /* An all-zero word flags the start of the tbtab, for debuggers
14339 that have to find it by searching forward from the entry
14340 point or from the current pc. */
19d2d16f 14341 fputs ("\t.long 0\n", file);
314fc5a9
ILT		 14342
14343 /* Tbtab format type. Use format type 0. */
19d2d16f 14344 fputs ("\t.byte 0,", file);
314fc5a9 14345
5fc921c1
DE		 14346 /* Language type. Unfortunately, there does not seem to be any
14347 official way to discover the language being compiled, so we
14348 use language_string.
14349 C is 0. Fortran is 1. Pascal is 2. Ada is 3. C++ is 9.
14350 Java is 13. Objective-C is 14. */
14351 if (! strcmp (language_string, "GNU C"))
314fc5a9 14352 i = 0;
6de9cd9a
DN		 14353 else if (! strcmp (language_string, "GNU F77")
14354 || ! strcmp (language_string, "GNU F95"))
314fc5a9 14355 i = 1;
8b83775b 14356 else if (! strcmp (language_string, "GNU Pascal"))
314fc5a9 14357 i = 2;
5fc921c1
DE		 14358 else if (! strcmp (language_string, "GNU Ada"))
14359 i = 3;
314fc5a9
ILT		 14360 else if (! strcmp (language_string, "GNU C++"))
14361 i = 9;
9517ead8
AG		 14362 else if (! strcmp (language_string, "GNU Java"))
14363 i = 13;
5fc921c1
DE		 14364 else if (! strcmp (language_string, "GNU Objective-C"))
14365 i = 14;
314fc5a9 14366 else
37409796 14367 gcc_unreachable ();
314fc5a9
ILT		 14368 fprintf (file, "%d,", i);
14369
14370 /* 8 single bit fields: global linkage (not set for C extern linkage,
14371 apparently a PL/I convention?), out-of-line epilogue/prologue, offset
14372 from start of procedure stored in tbtab, internal function, function
14373 has controlled storage, function has no toc, function uses fp,
14374 function logs/aborts fp operations. */
14375 /* Assume that fp operations are used if any fp reg must be saved. */
6041bf2f
DE		 14376 fprintf (file, "%d,",
14377 (optional_tbtab << 5) | ((info->first_fp_reg_save != 64) << 1));
314fc5a9
ILT		 14378
14379 /* 6 bitfields: function is interrupt handler, name present in
14380 proc table, function calls alloca, on condition directives
14381 (controls stack walks, 3 bits), saves condition reg, saves
14382 link reg. */
14383 /* The `function calls alloca' bit seems to be set whenever reg 31 is
14384 set up as a frame pointer, even when there is no alloca call. */
14385 fprintf (file, "%d,",
6041bf2f
DE		 14386 ((optional_tbtab << 6)
14387 | ((optional_tbtab & frame_pointer_needed) << 5)
14388 | (info->cr_save_p << 1)
14389 | (info->lr_save_p)));
314fc5a9 14390
6041bf2f 14391 /* 3 bitfields: saves backchain, fixup code, number of fpr saved
314fc5a9
ILT		 14392 (6 bits). */
14393 fprintf (file, "%d,",
4697a36c 14394 (info->push_p << 7) | (64 - info->first_fp_reg_save));
314fc5a9
ILT		 14395
14396 /* 2 bitfields: spare bits (2 bits), number of gpr saved (6 bits). */
14397 fprintf (file, "%d,", (32 - first_reg_to_save ()));
14398
6041bf2f
DE		 14399 if (optional_tbtab)
14400 {
14401 /* Compute the parameter info from the function decl argument
14402 list. */
14403 tree decl;
14404 int next_parm_info_bit = 31;
314fc5a9 14405
6041bf2f
DE		 14406 for (decl = DECL_ARGUMENTS (current_function_decl);
14407 decl; decl = TREE_CHAIN (decl))
14408 {
14409 rtx parameter = DECL_INCOMING_RTL (decl);
14410 enum machine_mode mode = GET_MODE (parameter);
314fc5a9 14411
6041bf2f
DE		 14412 if (GET_CODE (parameter) == REG)
14413 {
14414 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
14415 {
14416 int bits;
14417
14418 float_parms++;
14419
37409796
NS		 14420 switch (mode)
14421 {
14422 case SFmode:
14423 bits = 0x2;
14424 break;
14425
14426 case DFmode:
14427 case TFmode:
14428 bits = 0x3;
14429 break;
14430
14431 default:
14432 gcc_unreachable ();
14433 }
6041bf2f
DE		 14434
14435 /* If only one bit will fit, don't or in this entry. */
14436 if (next_parm_info_bit > 0)
14437 parm_info |= (bits << (next_parm_info_bit - 1));
14438 next_parm_info_bit -= 2;
14439 }
14440 else
14441 {
14442 fixed_parms += ((GET_MODE_SIZE (mode)
14443 + (UNITS_PER_WORD - 1))
14444 / UNITS_PER_WORD);
14445 next_parm_info_bit -= 1;
14446 }
14447 }
14448 }
14449 }
314fc5a9
ILT		 14450
14451 /* Number of fixed point parameters. */
14452 /* This is actually the number of words of fixed point parameters; thus
14453 an 8 byte struct counts as 2; and thus the maximum value is 8. */
14454 fprintf (file, "%d,", fixed_parms);
14455
14456 /* 2 bitfields: number of floating point parameters (7 bits), parameters
14457 all on stack. */
14458 /* This is actually the number of fp registers that hold parameters;
14459 and thus the maximum value is 13. */
14460 /* Set parameters on stack bit if parameters are not in their original
14461 registers, regardless of whether they are on the stack? Xlc
14462 seems to set the bit when not optimizing. */
14463 fprintf (file, "%d\n", ((float_parms << 1) | (! optimize)));
14464
6041bf2f
DE		 14465 if (! optional_tbtab)
14466 return;
14467
314fc5a9
ILT		 14468 /* Optional fields follow. Some are variable length. */
14469
14470 /* Parameter types, left adjusted bit fields: 0 fixed, 10 single float,
14471 11 double float. */
14472 /* There is an entry for each parameter in a register, in the order that
14473 they occur in the parameter list. Any intervening arguments on the
14474 stack are ignored. If the list overflows a long (max possible length
14475 34 bits) then completely leave off all elements that don't fit. */
14476 /* Only emit this long if there was at least one parameter. */
14477 if (fixed_parms || float_parms)
14478 fprintf (file, "\t.long %d\n", parm_info);
14479
14480 /* Offset from start of code to tb table. */
19d2d16f 14481 fputs ("\t.long ", file);
314fc5a9 14482 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT");
85b776df
AM		 14483 if (TARGET_AIX)
14484 RS6000_OUTPUT_BASENAME (file, fname);
14485 else
14486 assemble_name (file, fname);
14487 putc ('-', file);
14488 rs6000_output_function_entry (file, fname);
19d2d16f 14489 putc ('\n', file);
314fc5a9
ILT		 14490
14491 /* Interrupt handler mask. */
14492 /* Omit this long, since we never set the interrupt handler bit
14493 above. */
14494
14495 /* Number of CTL (controlled storage) anchors. */
14496 /* Omit this long, since the has_ctl bit is never set above. */
14497
14498 /* Displacement into stack of each CTL anchor. */
14499 /* Omit this list of longs, because there are no CTL anchors. */
14500
14501 /* Length of function name. */
69c75916
AM		 14502 if (*fname == '*')
14503 ++fname;
296b8152 14504 fprintf (file, "\t.short %d\n", (int) strlen (fname));
314fc5a9
ILT		 14505
14506 /* Function name. */
14507 assemble_string (fname, strlen (fname));
14508
14509 /* Register for alloca automatic storage; this is always reg 31.
14510 Only emit this if the alloca bit was set above. */
14511 if (frame_pointer_needed)
19d2d16f 14512 fputs ("\t.byte 31\n", file);
b1765bde
DE		 14513
14514 fputs ("\t.align 2\n", file);
9b30bae2 14515 }
9878760c 14516}
17167fd8 14517\f
a4f6c312
SS		 14518/* A C compound statement that outputs the assembler code for a thunk
14519 function, used to implement C++ virtual function calls with
14520 multiple inheritance. The thunk acts as a wrapper around a virtual
14521 function, adjusting the implicit object parameter before handing
14522 control off to the real function.
14523
14524 First, emit code to add the integer DELTA to the location that
14525 contains the incoming first argument. Assume that this argument
14526 contains a pointer, and is the one used to pass the `this' pointer
14527 in C++. This is the incoming argument *before* the function
14528 prologue, e.g. `%o0' on a sparc. The addition must preserve the
14529 values of all other incoming arguments.
17167fd8
MM		 14530
14531 After the addition, emit code to jump to FUNCTION, which is a
a4f6c312
SS		 14532 `FUNCTION_DECL'. This is a direct pure jump, not a call, and does
14533 not touch the return address. Hence returning from FUNCTION will
14534 return to whoever called the current `thunk'.
17167fd8 14535
a4f6c312
SS		 14536 The effect must be as if FUNCTION had been called directly with the
14537 adjusted first argument. This macro is responsible for emitting
14538 all of the code for a thunk function; output_function_prologue()
14539 and output_function_epilogue() are not invoked.
17167fd8 14540
a4f6c312
SS		 14541 The THUNK_FNDECL is redundant. (DELTA and FUNCTION have already
14542 been extracted from it.) It might possibly be useful on some
14543 targets, but probably not.
17167fd8 14544
a4f6c312
SS		 14545 If you do not define this macro, the target-independent code in the
14546 C++ frontend will generate a less efficient heavyweight thunk that
14547 calls FUNCTION instead of jumping to it. The generic approach does
14548 not support varargs. */
17167fd8 14549
3961e8fe 14550static void
f676971a
EC		 14551rs6000_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
14552 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
a2369ed3 14553 tree function)
17167fd8 14554{
5b71a4e7 14555 rtx this, insn, funexp;
17167fd8 14556
5b71a4e7 14557 reload_completed = 1;
fe3ad572 14558 epilogue_completed = 1;
5b71a4e7 14559 no_new_pseudos = 1;
6429e3be 14560 reset_block_changes ();
56a7189a 14561
5b71a4e7 14562 /* Mark the end of the (empty) prologue. */
2e040219 14563 emit_note (NOTE_INSN_PROLOGUE_END);
17167fd8 14564
5b71a4e7
DE		 14565 /* Find the "this" pointer. If the function returns a structure,
14566 the structure return pointer is in r3. */
61f71b34 14567 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
5b71a4e7 14568 this = gen_rtx_REG (Pmode, 4);
56a7189a 14569 else
5b71a4e7 14570 this = gen_rtx_REG (Pmode, 3);
17167fd8 14571
5b71a4e7
DE		 14572 /* Apply the constant offset, if required. */
14573 if (delta)
14574 {
14575 rtx delta_rtx = GEN_INT (delta);
14576 emit_insn (TARGET_32BIT
14577 ? gen_addsi3 (this, this, delta_rtx)
14578 : gen_adddi3 (this, this, delta_rtx));
17167fd8
MM		 14579 }
14580
5b71a4e7
DE		 14581 /* Apply the offset from the vtable, if required. */
14582 if (vcall_offset)
17167fd8 14583 {
5b71a4e7
DE		 14584 rtx vcall_offset_rtx = GEN_INT (vcall_offset);
14585 rtx tmp = gen_rtx_REG (Pmode, 12);
17167fd8 14586
5b71a4e7 14587 emit_move_insn (tmp, gen_rtx_MEM (Pmode, this));
eeff9307
JJ		 14588 if (((unsigned HOST_WIDE_INT) vcall_offset) + 0x8000 >= 0x10000)
14589 {
14590 emit_insn (TARGET_32BIT
14591 ? gen_addsi3 (tmp, tmp, vcall_offset_rtx)
14592 : gen_adddi3 (tmp, tmp, vcall_offset_rtx));
14593 emit_move_insn (tmp, gen_rtx_MEM (Pmode, tmp));
14594 }
14595 else
14596 {
14597 rtx loc = gen_rtx_PLUS (Pmode, tmp, vcall_offset_rtx);
14598
14599 emit_move_insn (tmp, gen_rtx_MEM (Pmode, loc));
14600 }
5b71a4e7
DE		 14601 emit_insn (TARGET_32BIT
14602 ? gen_addsi3 (this, this, tmp)
14603 : gen_adddi3 (this, this, tmp));
17167fd8
MM		 14604 }
14605
5b71a4e7
DE		 14606 /* Generate a tail call to the target function. */
14607 if (!TREE_USED (function))
14608 {
14609 assemble_external (function);
14610 TREE_USED (function) = 1;
14611 }
14612 funexp = XEXP (DECL_RTL (function), 0);
5b71a4e7 14613 funexp = gen_rtx_MEM (FUNCTION_MODE, funexp);
ee890fe2
SS		 14614
14615#if TARGET_MACHO
ab82a49f 14616 if (MACHOPIC_INDIRECT)
5b71a4e7 14617 funexp = machopic_indirect_call_target (funexp);
ee890fe2 14618#endif
5b71a4e7
DE		 14619
14620 /* gen_sibcall expects reload to convert scratch pseudo to LR so we must
992d08b1 14621 generate sibcall RTL explicitly. */
5b71a4e7
DE		 14622 insn = emit_call_insn (
14623 gen_rtx_PARALLEL (VOIDmode,
14624 gen_rtvec (4,
14625 gen_rtx_CALL (VOIDmode,
14626 funexp, const0_rtx),
14627 gen_rtx_USE (VOIDmode, const0_rtx),
14628 gen_rtx_USE (VOIDmode,
14629 gen_rtx_REG (SImode,
14630 LINK_REGISTER_REGNUM)),
14631 gen_rtx_RETURN (VOIDmode))));
14632 SIBLING_CALL_P (insn) = 1;
14633 emit_barrier ();
14634
14635 /* Run just enough of rest_of_compilation to get the insns emitted.
14636 There's not really enough bulk here to make other passes such as
14637 instruction scheduling worth while. Note that use_thunk calls
14638 assemble_start_function and assemble_end_function. */
14639 insn = get_insns ();
a2855205 14640 insn_locators_initialize ();
5b71a4e7
DE		 14641 shorten_branches (insn);
14642 final_start_function (insn, file, 1);
c9d691e9 14643 final (insn, file, 1);
5b71a4e7
DE		 14644 final_end_function ();
14645
14646 reload_completed = 0;
fe3ad572 14647 epilogue_completed = 0;
5b71a4e7 14648 no_new_pseudos = 0;
9ebbca7d 14649}
9ebbca7d
GK		 14650\f
14651/* A quick summary of the various types of 'constant-pool tables'
14652 under PowerPC:
14653
f676971a 14654 Target Flags Name One table per
9ebbca7d
GK		 14655 AIX (none) AIX TOC object file
14656 AIX -mfull-toc AIX TOC object file
14657 AIX -mminimal-toc AIX minimal TOC translation unit
14658 SVR4/EABI (none) SVR4 SDATA object file
14659 SVR4/EABI -fpic SVR4 pic object file
14660 SVR4/EABI -fPIC SVR4 PIC translation unit
14661 SVR4/EABI -mrelocatable EABI TOC function
14662 SVR4/EABI -maix AIX TOC object file
f676971a 14663 SVR4/EABI -maix -mminimal-toc
9ebbca7d
GK		 14664 AIX minimal TOC translation unit
14665
14666 Name Reg. Set by entries contains:
14667 made by addrs? fp? sum?
14668
14669 AIX TOC 2 crt0 as Y option option
14670 AIX minimal TOC 30 prolog gcc Y Y option
14671 SVR4 SDATA 13 crt0 gcc N Y N
14672 SVR4 pic 30 prolog ld Y not yet N
14673 SVR4 PIC 30 prolog gcc Y option option
14674 EABI TOC 30 prolog gcc Y option option
14675
14676*/
14677
9ebbca7d
GK		 14678/* Hash functions for the hash table. */
14679
14680static unsigned
a2369ed3 14681rs6000_hash_constant (rtx k)
9ebbca7d 14682{
46b33600
RH		 14683 enum rtx_code code = GET_CODE (k);
14684 enum machine_mode mode = GET_MODE (k);
14685 unsigned result = (code << 3) ^ mode;
14686 const char *format;
14687 int flen, fidx;
f676971a 14688
46b33600
RH		 14689 format = GET_RTX_FORMAT (code);
14690 flen = strlen (format);
14691 fidx = 0;
9ebbca7d 14692
46b33600
RH		 14693 switch (code)
14694 {
14695 case LABEL_REF:
14696 return result * 1231 + (unsigned) INSN_UID (XEXP (k, 0));
14697
14698 case CONST_DOUBLE:
14699 if (mode != VOIDmode)
14700 return real_hash (CONST_DOUBLE_REAL_VALUE (k)) * result;
14701 flen = 2;
14702 break;
14703
14704 case CODE_LABEL:
14705 fidx = 3;
14706 break;
14707
14708 default:
14709 break;
14710 }
9ebbca7d
GK		 14711
14712 for (; fidx < flen; fidx++)
14713 switch (format[fidx])
14714 {
14715 case 's':
14716 {
14717 unsigned i, len;
14718 const char *str = XSTR (k, fidx);
14719 len = strlen (str);
14720 result = result * 613 + len;
14721 for (i = 0; i < len; i++)
14722 result = result * 613 + (unsigned) str[i];
17167fd8
MM		 14723 break;
14724 }
9ebbca7d
GK		 14725 case 'u':
14726 case 'e':
14727 result = result * 1231 + rs6000_hash_constant (XEXP (k, fidx));
14728 break;
14729 case 'i':
14730 case 'n':
14731 result = result * 613 + (unsigned) XINT (k, fidx);
14732 break;
14733 case 'w':
14734 if (sizeof (unsigned) >= sizeof (HOST_WIDE_INT))
14735 result = result * 613 + (unsigned) XWINT (k, fidx);
14736 else
14737 {
14738 size_t i;
9390387d 14739 for (i = 0; i < sizeof (HOST_WIDE_INT) / sizeof (unsigned); i++)
9ebbca7d
GK		 14740 result = result * 613 + (unsigned) (XWINT (k, fidx)
14741 >> CHAR_BIT * i);
14742 }
14743 break;
09501938
DE		 14744 case '0':
14745 break;
9ebbca7d 14746 default:
37409796 14747 gcc_unreachable ();
9ebbca7d 14748 }
46b33600 14749
9ebbca7d
GK		 14750 return result;
14751}
14752
14753static unsigned
a2369ed3 14754toc_hash_function (const void *hash_entry)
9ebbca7d 14755{
f676971a 14756 const struct toc_hash_struct *thc =
a9098fd0
GK		 14757 (const struct toc_hash_struct *) hash_entry;
14758 return rs6000_hash_constant (thc->key) ^ thc->key_mode;
9ebbca7d
GK		 14759}
14760
14761/* Compare H1 and H2 for equivalence. */
14762
14763static int
a2369ed3 14764toc_hash_eq (const void *h1, const void *h2)
9ebbca7d
GK		 14765{
14766 rtx r1 = ((const struct toc_hash_struct *) h1)->key;
14767 rtx r2 = ((const struct toc_hash_struct *) h2)->key;
14768
a9098fd0
GK		 14769 if (((const struct toc_hash_struct *) h1)->key_mode
14770 != ((const struct toc_hash_struct *) h2)->key_mode)
14771 return 0;
14772
5692c7bc 14773 return rtx_equal_p (r1, r2);
9ebbca7d
GK		 14774}
14775
28e510bd
MM		 14776/* These are the names given by the C++ front-end to vtables, and
14777 vtable-like objects. Ideally, this logic should not be here;
14778 instead, there should be some programmatic way of inquiring as
14779 to whether or not an object is a vtable. */
14780
14781#define VTABLE_NAME_P(NAME) \
9390387d 14782 (strncmp ("_vt.", name, strlen ("_vt.")) == 0 \
28e510bd
MM		 14783 || strncmp ("_ZTV", name, strlen ("_ZTV")) == 0 \
14784 || strncmp ("_ZTT", name, strlen ("_ZTT")) == 0 \
26be75db 14785 || strncmp ("_ZTI", name, strlen ("_ZTI")) == 0 \
f676971a 14786 || strncmp ("_ZTC", name, strlen ("_ZTC")) == 0)
28e510bd
MM		 14787
14788void
a2369ed3 14789rs6000_output_symbol_ref (FILE *file, rtx x)
28e510bd
MM		 14790{
14791 /* Currently C++ toc references to vtables can be emitted before it
14792 is decided whether the vtable is public or private. If this is
14793 the case, then the linker will eventually complain that there is
f676971a 14794 a reference to an unknown section. Thus, for vtables only,
28e510bd
MM		 14795 we emit the TOC reference to reference the symbol and not the
14796 section. */
14797 const char *name = XSTR (x, 0);
54ee9799 14798
f676971a 14799 if (VTABLE_NAME_P (name))
54ee9799
DE		 14800 {
14801 RS6000_OUTPUT_BASENAME (file, name);
14802 }
14803 else
14804 assemble_name (file, name);
28e510bd
MM		 14805}
14806
a4f6c312
SS		 14807/* Output a TOC entry. We derive the entry name from what is being
14808 written. */
9878760c
RK		 14809
14810void
a2369ed3 14811output_toc (FILE *file, rtx x, int labelno, enum machine_mode mode)
9878760c
RK		 14812{
14813 char buf[256];
3cce094d 14814 const char *name = buf;
ec940faa 14815 const char *real_name;
9878760c
RK		 14816 rtx base = x;
14817 int offset = 0;
14818
37409796 14819 gcc_assert (!TARGET_NO_TOC);
4697a36c 14820
9ebbca7d
GK		 14821 /* When the linker won't eliminate them, don't output duplicate
14822 TOC entries (this happens on AIX if there is any kind of TOC,
17211ab5
GK		 14823 and on SVR4 under -fPIC or -mrelocatable). Don't do this for
14824 CODE_LABELs. */
14825 if (TARGET_TOC && GET_CODE (x) != LABEL_REF)
9ebbca7d
GK		 14826 {
14827 struct toc_hash_struct *h;
14828 void * * found;
f676971a 14829
17211ab5 14830 /* Create toc_hash_table. This can't be done at OVERRIDE_OPTIONS
c4ad648e 14831 time because GGC is not initialized at that point. */
17211ab5 14832 if (toc_hash_table == NULL)
f676971a 14833 toc_hash_table = htab_create_ggc (1021, toc_hash_function,
17211ab5
GK		 14834 toc_hash_eq, NULL);
14835
9ebbca7d
GK		 14836 h = ggc_alloc (sizeof (*h));
14837 h->key = x;
a9098fd0 14838 h->key_mode = mode;
9ebbca7d 14839 h->labelno = labelno;
f676971a 14840
9ebbca7d
GK		 14841 found = htab_find_slot (toc_hash_table, h, 1);
14842 if (*found == NULL)
14843 *found = h;
f676971a 14844 else /* This is indeed a duplicate.
9ebbca7d
GK		 14845 Set this label equal to that label. */
14846 {
14847 fputs ("\t.set ", file);
14848 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC");
14849 fprintf (file, "%d,", labelno);
14850 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC");
f676971a 14851 fprintf (file, "%d\n", ((*(const struct toc_hash_struct **)
9ebbca7d
GK		 14852 found)->labelno));
14853 return;
14854 }
14855 }
14856
14857 /* If we're going to put a double constant in the TOC, make sure it's
14858 aligned properly when strict alignment is on. */
ff1720ed
RK		 14859 if (GET_CODE (x) == CONST_DOUBLE
14860 && STRICT_ALIGNMENT
a9098fd0 14861 && GET_MODE_BITSIZE (mode) >= 64
ff1720ed
RK		 14862 && ! (TARGET_NO_FP_IN_TOC && ! TARGET_MINIMAL_TOC)) {
14863 ASM_OUTPUT_ALIGN (file, 3);
14864 }
14865
4977bab6 14866 (*targetm.asm_out.internal_label) (file, "LC", labelno);
9878760c 14867
37c37a57
RK		 14868 /* Handle FP constants specially. Note that if we have a minimal
14869 TOC, things we put here aren't actually in the TOC, so we can allow
14870 FP constants. */
fcce224d
DE		 14871 if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == TFmode)
14872 {
14873 REAL_VALUE_TYPE rv;
14874 long k[4];
14875
14876 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
14877 REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv, k);
14878
14879 if (TARGET_64BIT)
14880 {
14881 if (TARGET_MINIMAL_TOC)
14882 fputs (DOUBLE_INT_ASM_OP, file);
14883 else
14884 fprintf (file, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
14885 k[0] & 0xffffffff, k[1] & 0xffffffff,
14886 k[2] & 0xffffffff, k[3] & 0xffffffff);
14887 fprintf (file, "0x%lx%08lx,0x%lx%08lx\n",
14888 k[0] & 0xffffffff, k[1] & 0xffffffff,
14889 k[2] & 0xffffffff, k[3] & 0xffffffff);
14890 return;
14891 }
14892 else
14893 {
14894 if (TARGET_MINIMAL_TOC)
14895 fputs ("\t.long ", file);
14896 else
14897 fprintf (file, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
14898 k[0] & 0xffffffff, k[1] & 0xffffffff,
14899 k[2] & 0xffffffff, k[3] & 0xffffffff);
14900 fprintf (file, "0x%lx,0x%lx,0x%lx,0x%lx\n",
14901 k[0] & 0xffffffff, k[1] & 0xffffffff,
14902 k[2] & 0xffffffff, k[3] & 0xffffffff);
14903 return;
14904 }
14905 }
14906 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == DFmode)
9878760c 14907 {
042259f2
DE		 14908 REAL_VALUE_TYPE rv;
14909 long k[2];
0adc764e 14910
042259f2
DE		 14911 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
14912 REAL_VALUE_TO_TARGET_DOUBLE (rv, k);
31bfaa0b 14913
13ded975
DE		 14914 if (TARGET_64BIT)
14915 {
14916 if (TARGET_MINIMAL_TOC)
2bfcf297 14917 fputs (DOUBLE_INT_ASM_OP, file);
13ded975 14918 else
2f0552b6
AM		 14919 fprintf (file, "\t.tc FD_%lx_%lx[TC],",
14920 k[0] & 0xffffffff, k[1] & 0xffffffff);
14921 fprintf (file, "0x%lx%08lx\n",
14922 k[0] & 0xffffffff, k[1] & 0xffffffff);
13ded975
DE		 14923 return;
14924 }
1875cc88 14925 else
13ded975
DE		 14926 {
14927 if (TARGET_MINIMAL_TOC)
2bfcf297 14928 fputs ("\t.long ", file);
13ded975 14929 else
2f0552b6
AM		 14930 fprintf (file, "\t.tc FD_%lx_%lx[TC],",
14931 k[0] & 0xffffffff, k[1] & 0xffffffff);
14932 fprintf (file, "0x%lx,0x%lx\n",
14933 k[0] & 0xffffffff, k[1] & 0xffffffff);
13ded975
DE		 14934 return;
14935 }
9878760c 14936 }
a9098fd0 14937 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == SFmode)
9878760c 14938 {
042259f2
DE		 14939 REAL_VALUE_TYPE rv;
14940 long l;
9878760c 14941
042259f2
DE		 14942 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
14943 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
14944
31bfaa0b
DE		 14945 if (TARGET_64BIT)
14946 {
14947 if (TARGET_MINIMAL_TOC)
2bfcf297 14948 fputs (DOUBLE_INT_ASM_OP, file);
31bfaa0b 14949 else
2f0552b6
AM		 14950 fprintf (file, "\t.tc FS_%lx[TC],", l & 0xffffffff);
14951 fprintf (file, "0x%lx00000000\n", l & 0xffffffff);
31bfaa0b
DE		 14952 return;
14953 }
042259f2 14954 else
31bfaa0b
DE		 14955 {
14956 if (TARGET_MINIMAL_TOC)
2bfcf297 14957 fputs ("\t.long ", file);
31bfaa0b 14958 else
2f0552b6
AM		 14959 fprintf (file, "\t.tc FS_%lx[TC],", l & 0xffffffff);
14960 fprintf (file, "0x%lx\n", l & 0xffffffff);
31bfaa0b
DE		 14961 return;
14962 }
042259f2 14963 }
f176e826 14964 else if (GET_MODE (x) == VOIDmode
a9098fd0 14965 && (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE))
042259f2 14966 {
e2c953b6 14967 unsigned HOST_WIDE_INT low;
042259f2
DE		 14968 HOST_WIDE_INT high;
14969
14970 if (GET_CODE (x) == CONST_DOUBLE)
14971 {
14972 low = CONST_DOUBLE_LOW (x);
14973 high = CONST_DOUBLE_HIGH (x);
14974 }
14975 else
14976#if HOST_BITS_PER_WIDE_INT == 32
14977 {
14978 low = INTVAL (x);
0858c623 14979 high = (low & 0x80000000) ? ~0 : 0;
042259f2
DE		 14980 }
14981#else
14982 {
c4ad648e
AM		 14983 low = INTVAL (x) & 0xffffffff;
14984 high = (HOST_WIDE_INT) INTVAL (x) >> 32;
042259f2
DE		 14985 }
14986#endif
9878760c 14987
a9098fd0
GK		 14988 /* TOC entries are always Pmode-sized, but since this
14989 is a bigendian machine then if we're putting smaller
14990 integer constants in the TOC we have to pad them.
14991 (This is still a win over putting the constants in
14992 a separate constant pool, because then we'd have
02a4ec28
FS		 14993 to have both a TOC entry _and_ the actual constant.)
14994
14995 For a 32-bit target, CONST_INT values are loaded and shifted
14996 entirely within `low' and can be stored in one TOC entry. */
14997
37409796
NS		 14998 /* It would be easy to make this work, but it doesn't now. */
14999 gcc_assert (!TARGET_64BIT || POINTER_SIZE >= GET_MODE_BITSIZE (mode));
02a4ec28
FS		 15000
15001 if (POINTER_SIZE > GET_MODE_BITSIZE (mode))
fb52d8de
AM		 15002 {
15003#if HOST_BITS_PER_WIDE_INT == 32
15004 lshift_double (low, high, POINTER_SIZE - GET_MODE_BITSIZE (mode),
15005 POINTER_SIZE, &low, &high, 0);
15006#else
15007 low |= high << 32;
15008 low <<= POINTER_SIZE - GET_MODE_BITSIZE (mode);
15009 high = (HOST_WIDE_INT) low >> 32;
15010 low &= 0xffffffff;
15011#endif
15012 }
a9098fd0 15013
13ded975
DE		 15014 if (TARGET_64BIT)
15015 {
15016 if (TARGET_MINIMAL_TOC)
2bfcf297 15017 fputs (DOUBLE_INT_ASM_OP, file);
13ded975 15018 else
2f0552b6
AM		 15019 fprintf (file, "\t.tc ID_%lx_%lx[TC],",
15020 (long) high & 0xffffffff, (long) low & 0xffffffff);
15021 fprintf (file, "0x%lx%08lx\n",
15022 (long) high & 0xffffffff, (long) low & 0xffffffff);
13ded975
DE		 15023 return;
15024 }
1875cc88 15025 else
13ded975 15026 {
02a4ec28
FS		 15027 if (POINTER_SIZE < GET_MODE_BITSIZE (mode))
15028 {
15029 if (TARGET_MINIMAL_TOC)
2bfcf297 15030 fputs ("\t.long ", file);
02a4ec28 15031 else
2bfcf297 15032 fprintf (file, "\t.tc ID_%lx_%lx[TC],",
2f0552b6
AM		 15033 (long) high & 0xffffffff, (long) low & 0xffffffff);
15034 fprintf (file, "0x%lx,0x%lx\n",
15035 (long) high & 0xffffffff, (long) low & 0xffffffff);
02a4ec28 15036 }
13ded975 15037 else
02a4ec28
FS		 15038 {
15039 if (TARGET_MINIMAL_TOC)
2bfcf297 15040 fputs ("\t.long ", file);
02a4ec28 15041 else
2f0552b6
AM		 15042 fprintf (file, "\t.tc IS_%lx[TC],", (long) low & 0xffffffff);
15043 fprintf (file, "0x%lx\n", (long) low & 0xffffffff);
02a4ec28 15044 }
13ded975
DE		 15045 return;
15046 }
9878760c
RK		 15047 }
15048
15049 if (GET_CODE (x) == CONST)
15050 {
37409796 15051 gcc_assert (GET_CODE (XEXP (x, 0)) == PLUS);
2bfcf297 15052
9878760c
RK		 15053 base = XEXP (XEXP (x, 0), 0);
15054 offset = INTVAL (XEXP (XEXP (x, 0), 1));
15055 }
f676971a 15056
37409796
NS		 15057 switch (GET_CODE (base))
15058 {
15059 case SYMBOL_REF:
15060 name = XSTR (base, 0);
15061 break;
15062
15063 case LABEL_REF:
15064 ASM_GENERATE_INTERNAL_LABEL (buf, "L",
15065 CODE_LABEL_NUMBER (XEXP (base, 0)));
15066 break;
15067
15068 case CODE_LABEL:
15069 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (base));
15070 break;
15071
15072 default:
15073 gcc_unreachable ();
15074 }
9878760c 15075
772c5265 15076 real_name = (*targetm.strip_name_encoding) (name);
1875cc88 15077 if (TARGET_MINIMAL_TOC)
2bfcf297 15078 fputs (TARGET_32BIT ? "\t.long " : DOUBLE_INT_ASM_OP, file);
1875cc88
JW		 15079 else
15080 {
b6c9286a 15081 fprintf (file, "\t.tc %s", real_name);
9878760c 15082
1875cc88
JW		 15083 if (offset < 0)
15084 fprintf (file, ".N%d", - offset);
15085 else if (offset)
15086 fprintf (file, ".P%d", offset);
9878760c 15087
19d2d16f 15088 fputs ("[TC],", file);
1875cc88 15089 }
581bc4de
MM		 15090
15091 /* Currently C++ toc references to vtables can be emitted before it
15092 is decided whether the vtable is public or private. If this is
15093 the case, then the linker will eventually complain that there is
15094 a TOC reference to an unknown section. Thus, for vtables only,
15095 we emit the TOC reference to reference the symbol and not the
15096 section. */
28e510bd 15097 if (VTABLE_NAME_P (name))
581bc4de 15098 {
54ee9799 15099 RS6000_OUTPUT_BASENAME (file, name);
581bc4de
MM		 15100 if (offset < 0)
15101 fprintf (file, "%d", offset);
15102 else if (offset > 0)
15103 fprintf (file, "+%d", offset);
15104 }
15105 else
15106 output_addr_const (file, x);
19d2d16f 15107 putc ('\n', file);
9878760c
RK		 15108}
15109\f
15110/* Output an assembler pseudo-op to write an ASCII string of N characters
15111 starting at P to FILE.
15112
15113 On the RS/6000, we have to do this using the .byte operation and
15114 write out special characters outside the quoted string.
15115 Also, the assembler is broken; very long strings are truncated,
a4f6c312 15116 so we must artificially break them up early. */
9878760c
RK		 15117
15118void
a2369ed3 15119output_ascii (FILE *file, const char *p, int n)
9878760c
RK		 15120{
15121 char c;
15122 int i, count_string;
d330fd93
KG		 15123 const char *for_string = "\t.byte \"";
15124 const char *for_decimal = "\t.byte ";
15125 const char *to_close = NULL;
9878760c
RK		 15126
15127 count_string = 0;
15128 for (i = 0; i < n; i++)
15129 {
15130 c = *p++;
15131 if (c >= ' ' && c < 0177)
15132 {
15133 if (for_string)
15134 fputs (for_string, file);
15135 putc (c, file);
15136
15137 /* Write two quotes to get one. */
15138 if (c == '"')
15139 {
15140 putc (c, file);
15141 ++count_string;
15142 }
15143
15144 for_string = NULL;
15145 for_decimal = "\"\n\t.byte ";
15146 to_close = "\"\n";
15147 ++count_string;
15148
15149 if (count_string >= 512)
15150 {
15151 fputs (to_close, file);
15152
15153 for_string = "\t.byte \"";
15154 for_decimal = "\t.byte ";
15155 to_close = NULL;
15156 count_string = 0;
15157 }
15158 }
15159 else
15160 {
15161 if (for_decimal)
15162 fputs (for_decimal, file);
15163 fprintf (file, "%d", c);
15164
15165 for_string = "\n\t.byte \"";
15166 for_decimal = ", ";
15167 to_close = "\n";
15168 count_string = 0;
15169 }
15170 }
15171
15172 /* Now close the string if we have written one. Then end the line. */
15173 if (to_close)
9ebbca7d 15174 fputs (to_close, file);
9878760c
RK		 15175}
15176\f
15177/* Generate a unique section name for FILENAME for a section type
15178 represented by SECTION_DESC. Output goes into BUF.
15179
15180 SECTION_DESC can be any string, as long as it is different for each
15181 possible section type.
15182
15183 We name the section in the same manner as xlc. The name begins with an
15184 underscore followed by the filename (after stripping any leading directory
11e5fe42
RK		 15185 names) with the last period replaced by the string SECTION_DESC. If
15186 FILENAME does not contain a period, SECTION_DESC is appended to the end of
15187 the name. */
9878760c
RK		 15188
15189void
f676971a 15190rs6000_gen_section_name (char **buf, const char *filename,
c4ad648e 15191 const char *section_desc)
9878760c 15192{
9ebbca7d 15193 const char *q, *after_last_slash, *last_period = 0;
9878760c
RK		 15194 char *p;
15195 int len;
9878760c
RK		 15196
15197 after_last_slash = filename;
15198 for (q = filename; *q; q++)
11e5fe42
RK		 15199 {
15200 if (*q == '/')
15201 after_last_slash = q + 1;
15202 else if (*q == '.')
15203 last_period = q;
15204 }
9878760c 15205
11e5fe42 15206 len = strlen (after_last_slash) + strlen (section_desc) + 2;
6d9f628e 15207 *buf = (char *) xmalloc (len);
9878760c
RK		 15208
15209 p = *buf;
15210 *p++ = '_';
15211
15212 for (q = after_last_slash; *q; q++)
15213 {
11e5fe42 15214 if (q == last_period)
c4ad648e 15215 {
9878760c
RK		 15216 strcpy (p, section_desc);
15217 p += strlen (section_desc);
e3981aab 15218 break;
c4ad648e 15219 }
9878760c 15220
e9a780ec 15221 else if (ISALNUM (*q))
c4ad648e 15222 *p++ = *q;
9878760c
RK		 15223 }
15224
11e5fe42 15225 if (last_period == 0)
9878760c
RK		 15226 strcpy (p, section_desc);
15227 else
15228 *p = '\0';
15229}
e165f3f0 15230\f
a4f6c312 15231/* Emit profile function. */
411707f4 15232
411707f4 15233void
a2369ed3 15234output_profile_hook (int labelno ATTRIBUTE_UNUSED)
411707f4 15235{
858081ad
AH		 15236 /* Non-standard profiling for kernels, which just saves LR then calls
15237 _mcount without worrying about arg saves. The idea is to change
15238 the function prologue as little as possible as it isn't easy to
15239 account for arg save/restore code added just for _mcount. */
ffcfcb5f
AM		 15240 if (TARGET_PROFILE_KERNEL)
15241 return;
15242
8480e480
CC		 15243 if (DEFAULT_ABI == ABI_AIX)
15244 {
9739c90c
JJ		 15245#ifndef NO_PROFILE_COUNTERS
15246# define NO_PROFILE_COUNTERS 0
15247#endif
f676971a 15248 if (NO_PROFILE_COUNTERS)
9739c90c
JJ		 15249 emit_library_call (init_one_libfunc (RS6000_MCOUNT), 0, VOIDmode, 0);
15250 else
15251 {
15252 char buf[30];
15253 const char *label_name;
15254 rtx fun;
411707f4 15255
9739c90c
JJ		 15256 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
15257 label_name = (*targetm.strip_name_encoding) (ggc_strdup (buf));
15258 fun = gen_rtx_SYMBOL_REF (Pmode, label_name);
411707f4 15259
9739c90c
JJ		 15260 emit_library_call (init_one_libfunc (RS6000_MCOUNT), 0, VOIDmode, 1,
15261 fun, Pmode);
15262 }
8480e480 15263 }
ee890fe2
SS		 15264 else if (DEFAULT_ABI == ABI_DARWIN)
15265 {
d5fa86ba 15266 const char *mcount_name = RS6000_MCOUNT;
ee890fe2
SS		 15267 int caller_addr_regno = LINK_REGISTER_REGNUM;
15268
15269 /* Be conservative and always set this, at least for now. */
15270 current_function_uses_pic_offset_table = 1;
15271
15272#if TARGET_MACHO
15273 /* For PIC code, set up a stub and collect the caller's address
15274 from r0, which is where the prologue puts it. */
11abc112
MM		 15275 if (MACHOPIC_INDIRECT
15276 && current_function_uses_pic_offset_table)
15277 caller_addr_regno = 0;
ee890fe2
SS		 15278#endif
15279 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mcount_name),
15280 0, VOIDmode, 1,
15281 gen_rtx_REG (Pmode, caller_addr_regno), Pmode);
15282 }
411707f4
CC		 15283}
15284
a4f6c312 15285/* Write function profiler code. */
e165f3f0
RK		 15286
15287void
a2369ed3 15288output_function_profiler (FILE *file, int labelno)
e165f3f0 15289{
3daf36a4 15290 char buf[100];
09eeeacb 15291 int save_lr = 8;
e165f3f0 15292
38c1f2d7 15293 switch (DEFAULT_ABI)
3daf36a4 15294 {
38c1f2d7 15295 default:
37409796 15296 gcc_unreachable ();
38c1f2d7
MM		 15297
15298 case ABI_V4:
09eeeacb 15299 save_lr = 4;
09eeeacb
AM		 15300 if (!TARGET_32BIT)
15301 {
d4ee4d25 15302 warning (0, "no profiling of 64-bit code for this ABI");
09eeeacb
AM		 15303 return;
15304 }
ffcfcb5f 15305 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
38c1f2d7
MM		 15306 fprintf (file, "\tmflr %s\n", reg_names[0]);
15307 if (flag_pic == 1)
15308 {
dfdfa60f 15309 fputs ("\tbl _GLOBAL_OFFSET_TABLE_@local-4\n", file);
09eeeacb
AM		 15310 asm_fprintf (file, "\t{st|stw} %s,%d(%s)\n",
15311 reg_names[0], save_lr, reg_names[1]);
17167fd8 15312 asm_fprintf (file, "\tmflr %s\n", reg_names[12]);
dfdfa60f 15313 asm_fprintf (file, "\t{l|lwz} %s,", reg_names[0]);
38c1f2d7 15314 assemble_name (file, buf);
17167fd8 15315 asm_fprintf (file, "@got(%s)\n", reg_names[12]);
38c1f2d7 15316 }
9ebbca7d 15317 else if (flag_pic > 1)
38c1f2d7 15318 {
09eeeacb
AM		 15319 asm_fprintf (file, "\t{st|stw} %s,%d(%s)\n",
15320 reg_names[0], save_lr, reg_names[1]);
9ebbca7d
GK		 15321 /* Now, we need to get the address of the label. */
15322 fputs ("\tbl 1f\n\t.long ", file);
034e84c4 15323 assemble_name (file, buf);
9ebbca7d
GK		 15324 fputs ("-.\n1:", file);
15325 asm_fprintf (file, "\tmflr %s\n", reg_names[11]);
f676971a 15326 asm_fprintf (file, "\t{l|lwz} %s,0(%s)\n",
9ebbca7d
GK		 15327 reg_names[0], reg_names[11]);
15328 asm_fprintf (file, "\t{cax|add} %s,%s,%s\n",
15329 reg_names[0], reg_names[0], reg_names[11]);
38c1f2d7 15330 }
38c1f2d7
MM		 15331 else
15332 {
17167fd8 15333 asm_fprintf (file, "\t{liu|lis} %s,", reg_names[12]);
38c1f2d7 15334 assemble_name (file, buf);
dfdfa60f 15335 fputs ("@ha\n", file);
09eeeacb
AM		 15336 asm_fprintf (file, "\t{st|stw} %s,%d(%s)\n",
15337 reg_names[0], save_lr, reg_names[1]);
a260abc9 15338 asm_fprintf (file, "\t{cal|la} %s,", reg_names[0]);
38c1f2d7 15339 assemble_name (file, buf);
17167fd8 15340 asm_fprintf (file, "@l(%s)\n", reg_names[12]);
38c1f2d7
MM		 15341 }
15342
50d440bc 15343 /* ABI_V4 saves the static chain reg with ASM_OUTPUT_REG_PUSH. */
3b6ce0af
DE		 15344 fprintf (file, "\tbl %s%s\n",
15345 RS6000_MCOUNT, flag_pic ? "@plt" : "");
38c1f2d7
MM		 15346 break;
15347
15348 case ABI_AIX:
ee890fe2 15349 case ABI_DARWIN:
ffcfcb5f
AM		 15350 if (!TARGET_PROFILE_KERNEL)
15351 {
a3c9585f 15352 /* Don't do anything, done in output_profile_hook (). */
ffcfcb5f
AM		 15353 }
15354 else
15355 {
37409796 15356 gcc_assert (!TARGET_32BIT);
ffcfcb5f
AM		 15357
15358 asm_fprintf (file, "\tmflr %s\n", reg_names[0]);
15359 asm_fprintf (file, "\tstd %s,16(%s)\n", reg_names[0], reg_names[1]);
15360
6de9cd9a 15361 if (cfun->static_chain_decl != NULL)
ffcfcb5f
AM		 15362 {
15363 asm_fprintf (file, "\tstd %s,24(%s)\n",
15364 reg_names[STATIC_CHAIN_REGNUM], reg_names[1]);
15365 fprintf (file, "\tbl %s\n", RS6000_MCOUNT);
15366 asm_fprintf (file, "\tld %s,24(%s)\n",
15367 reg_names[STATIC_CHAIN_REGNUM], reg_names[1]);
15368 }
15369 else
15370 fprintf (file, "\tbl %s\n", RS6000_MCOUNT);
15371 }
38c1f2d7
MM		 15372 break;
15373 }
e165f3f0 15374}
a251ffd0 15375
b54cf83a 15376\f
b54cf83a
DE		 15377/* Power4 load update and store update instructions are cracked into a
15378 load or store and an integer insn which are executed in the same cycle.
15379 Branches have their own dispatch slot which does not count against the
15380 GCC issue rate, but it changes the program flow so there are no other
15381 instructions to issue in this cycle. */
15382
15383static int
f676971a
EC		 15384rs6000_variable_issue (FILE *stream ATTRIBUTE_UNUSED,
15385 int verbose ATTRIBUTE_UNUSED,
a2369ed3 15386 rtx insn, int more)
b54cf83a
DE		 15387{
15388 if (GET_CODE (PATTERN (insn)) == USE
15389 || GET_CODE (PATTERN (insn)) == CLOBBER)
15390 return more;
15391
ec507f2d 15392 if (rs6000_sched_groups)
b54cf83a 15393 {
cbe26ab8 15394 if (is_microcoded_insn (insn))
c4ad648e 15395 return 0;
cbe26ab8 15396 else if (is_cracked_insn (insn))
c4ad648e 15397 return more > 2 ? more - 2 : 0;
b54cf83a 15398 }
165b263e
DE		 15399
15400 return more - 1;
b54cf83a
DE		 15401}
15402
a251ffd0
TG		 15403/* Adjust the cost of a scheduling dependency. Return the new cost of
15404 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
15405
c237e94a 15406static int
0a4f0294 15407rs6000_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
a251ffd0
TG		 15408{
15409 if (! recog_memoized (insn))
15410 return 0;
15411
15412 if (REG_NOTE_KIND (link) != 0)
15413 return 0;
15414
15415 if (REG_NOTE_KIND (link) == 0)
15416 {
ed947a96
DJ		 15417 /* Data dependency; DEP_INSN writes a register that INSN reads
15418 some cycles later. */
c9dbf840
DE		 15419
15420 /* Separate a load from a narrower, dependent store. */
15421 if (rs6000_sched_groups
15422 && GET_CODE (PATTERN (insn)) == SET
15423 && GET_CODE (PATTERN (dep_insn)) == SET
15424 && GET_CODE (XEXP (PATTERN (insn), 1)) == MEM
15425 && GET_CODE (XEXP (PATTERN (dep_insn), 0)) == MEM
15426 && (GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (insn), 1)))
15427 > GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (dep_insn), 0)))))
15428 return cost + 14;
15429
ed947a96
DJ		 15430 switch (get_attr_type (insn))
15431 {
15432 case TYPE_JMPREG:
309323c2 15433 /* Tell the first scheduling pass about the latency between
ed947a96
DJ		 15434 a mtctr and bctr (and mtlr and br/blr). The first
15435 scheduling pass will not know about this latency since
15436 the mtctr instruction, which has the latency associated
15437 to it, will be generated by reload. */
309323c2 15438 return TARGET_POWER ? 5 : 4;
ed947a96
DJ		 15439 case TYPE_BRANCH:
15440 /* Leave some extra cycles between a compare and its
15441 dependent branch, to inhibit expensive mispredicts. */
309323c2
DE		 15442 if ((rs6000_cpu_attr == CPU_PPC603
15443 || rs6000_cpu_attr == CPU_PPC604
15444 || rs6000_cpu_attr == CPU_PPC604E
15445 || rs6000_cpu_attr == CPU_PPC620
15446 || rs6000_cpu_attr == CPU_PPC630
15447 || rs6000_cpu_attr == CPU_PPC750
15448 || rs6000_cpu_attr == CPU_PPC7400
15449 || rs6000_cpu_attr == CPU_PPC7450
ec507f2d
DE		 15450 || rs6000_cpu_attr == CPU_POWER4
15451 || rs6000_cpu_attr == CPU_POWER5)
ed947a96
DJ		 15452 && recog_memoized (dep_insn)
15453 && (INSN_CODE (dep_insn) >= 0)
b54cf83a
DE		 15454 && (get_attr_type (dep_insn) == TYPE_CMP
15455 || get_attr_type (dep_insn) == TYPE_COMPARE
ed947a96 15456 || get_attr_type (dep_insn) == TYPE_DELAYED_COMPARE
9259f3b0
DE		 15457 || get_attr_type (dep_insn) == TYPE_IMUL_COMPARE
15458 || get_attr_type (dep_insn) == TYPE_LMUL_COMPARE
ed947a96 15459 || get_attr_type (dep_insn) == TYPE_FPCOMPARE
b54cf83a
DE		 15460 || get_attr_type (dep_insn) == TYPE_CR_LOGICAL
15461 || get_attr_type (dep_insn) == TYPE_DELAYED_CR))
ed947a96
DJ		 15462 return cost + 2;
15463 default:
15464 break;
15465 }
a251ffd0
TG		 15466 /* Fall out to return default cost. */
15467 }
15468
15469 return cost;
15470}
b6c9286a 15471
cbe26ab8 15472/* The function returns a true if INSN is microcoded.
839a4992 15473 Return false otherwise. */
cbe26ab8
DN		 15474
15475static bool
15476is_microcoded_insn (rtx insn)
15477{
15478 if (!insn || !INSN_P (insn)
15479 || GET_CODE (PATTERN (insn)) == USE
15480 || GET_CODE (PATTERN (insn)) == CLOBBER)
15481 return false;
15482
ec507f2d 15483 if (rs6000_sched_groups)
cbe26ab8
DN		 15484 {
15485 enum attr_type type = get_attr_type (insn);
15486 if (type == TYPE_LOAD_EXT_U
15487 || type == TYPE_LOAD_EXT_UX
15488 || type == TYPE_LOAD_UX
15489 || type == TYPE_STORE_UX
15490 || type == TYPE_MFCR)
c4ad648e 15491 return true;
cbe26ab8
DN		 15492 }
15493
15494 return false;
15495}
15496
5c425df5 15497/* The function returns a nonzero value if INSN can be scheduled only
cbe26ab8
DN		 15498 as the first insn in a dispatch group ("dispatch-slot restricted").
15499 In this case, the returned value indicates how many dispatch slots
15500 the insn occupies (at the beginning of the group).
79ae11c4
DN		 15501 Return 0 otherwise. */
15502
cbe26ab8 15503static int
79ae11c4
DN		 15504is_dispatch_slot_restricted (rtx insn)
15505{
15506 enum attr_type type;
15507
ec507f2d 15508 if (!rs6000_sched_groups)
79ae11c4
DN		 15509 return 0;
15510
15511 if (!insn
15512 || insn == NULL_RTX
15513 || GET_CODE (insn) == NOTE
15514 || GET_CODE (PATTERN (insn)) == USE
15515 || GET_CODE (PATTERN (insn)) == CLOBBER)
15516 return 0;
15517
15518 type = get_attr_type (insn);
15519
ec507f2d
DE		 15520 switch (type)
15521 {
15522 case TYPE_MFCR:
15523 case TYPE_MFCRF:
15524 case TYPE_MTCR:
15525 case TYPE_DELAYED_CR:
15526 case TYPE_CR_LOGICAL:
15527 case TYPE_MTJMPR:
15528 case TYPE_MFJMPR:
15529 return 1;
15530 case TYPE_IDIV:
15531 case TYPE_LDIV:
15532 return 2;
15533 default:
15534 if (rs6000_cpu == PROCESSOR_POWER5
15535 && is_cracked_insn (insn))
15536 return 2;
15537 return 0;
15538 }
79ae11c4
DN		 15539}
15540
cbe26ab8
DN		 15541/* The function returns true if INSN is cracked into 2 instructions
15542 by the processor (and therefore occupies 2 issue slots). */
15543
15544static bool
15545is_cracked_insn (rtx insn)
15546{
15547 if (!insn || !INSN_P (insn)
15548 || GET_CODE (PATTERN (insn)) == USE
15549 || GET_CODE (PATTERN (insn)) == CLOBBER)
15550 return false;
15551
ec507f2d 15552 if (rs6000_sched_groups)
cbe26ab8
DN		 15553 {
15554 enum attr_type type = get_attr_type (insn);
15555 if (type == TYPE_LOAD_U || type == TYPE_STORE_U
c4ad648e
AM		 15556 || type == TYPE_FPLOAD_U || type == TYPE_FPSTORE_U
15557 || type == TYPE_FPLOAD_UX || type == TYPE_FPSTORE_UX
15558 || type == TYPE_LOAD_EXT || type == TYPE_DELAYED_CR
15559 || type == TYPE_COMPARE || type == TYPE_DELAYED_COMPARE
15560 || type == TYPE_IMUL_COMPARE || type == TYPE_LMUL_COMPARE
15561 || type == TYPE_IDIV || type == TYPE_LDIV
15562 || type == TYPE_INSERT_WORD)
15563 return true;
cbe26ab8
DN		 15564 }
15565
15566 return false;
15567}
15568
15569/* The function returns true if INSN can be issued only from
a3c9585f 15570 the branch slot. */
cbe26ab8
DN		 15571
15572static bool
15573is_branch_slot_insn (rtx insn)
15574{
15575 if (!insn || !INSN_P (insn)
15576 || GET_CODE (PATTERN (insn)) == USE
15577 || GET_CODE (PATTERN (insn)) == CLOBBER)
15578 return false;
15579
ec507f2d 15580 if (rs6000_sched_groups)
cbe26ab8
DN		 15581 {
15582 enum attr_type type = get_attr_type (insn);
15583 if (type == TYPE_BRANCH || type == TYPE_JMPREG)
f676971a 15584 return true;
cbe26ab8
DN		 15585 return false;
15586 }
15587
15588 return false;
15589}
79ae11c4 15590
a4f6c312 15591/* A C statement (sans semicolon) to update the integer scheduling
79ae11c4
DN		 15592 priority INSN_PRIORITY (INSN). Increase the priority to execute the
15593 INSN earlier, reduce the priority to execute INSN later. Do not
a4f6c312
SS		 15594 define this macro if you do not need to adjust the scheduling
15595 priorities of insns. */
bef84347 15596
c237e94a 15597static int
a2369ed3 15598rs6000_adjust_priority (rtx insn ATTRIBUTE_UNUSED, int priority)
bef84347 15599{
a4f6c312
SS		 15600 /* On machines (like the 750) which have asymmetric integer units,
15601 where one integer unit can do multiply and divides and the other
15602 can't, reduce the priority of multiply/divide so it is scheduled
15603 before other integer operations. */
bef84347
VM		 15604
15605#if 0
2c3c49de 15606 if (! INSN_P (insn))
bef84347
VM		 15607 return priority;
15608
15609 if (GET_CODE (PATTERN (insn)) == USE)
15610 return priority;
15611
15612 switch (rs6000_cpu_attr) {
15613 case CPU_PPC750:
15614 switch (get_attr_type (insn))
15615 {
15616 default:
15617 break;
15618
15619 case TYPE_IMUL:
15620 case TYPE_IDIV:
3cb999d8
DE		 15621 fprintf (stderr, "priority was %#x (%d) before adjustment\n",
15622 priority, priority);
bef84347
VM		 15623 if (priority >= 0 && priority < 0x01000000)
15624 priority >>= 3;
15625 break;
15626 }
15627 }
15628#endif
15629
79ae11c4
DN		 15630 if (is_dispatch_slot_restricted (insn)
15631 && reload_completed
f676971a 15632 && current_sched_info->sched_max_insns_priority
79ae11c4
DN		 15633 && rs6000_sched_restricted_insns_priority)
15634 {
15635
c4ad648e
AM		 15636 /* Prioritize insns that can be dispatched only in the first
15637 dispatch slot. */
79ae11c4 15638 if (rs6000_sched_restricted_insns_priority == 1)
f676971a
EC		 15639 /* Attach highest priority to insn. This means that in
15640 haifa-sched.c:ready_sort(), dispatch-slot restriction considerations
79ae11c4 15641 precede 'priority' (critical path) considerations. */
f676971a 15642 return current_sched_info->sched_max_insns_priority;
79ae11c4 15643 else if (rs6000_sched_restricted_insns_priority == 2)
f676971a 15644 /* Increase priority of insn by a minimal amount. This means that in
c4ad648e
AM		 15645 haifa-sched.c:ready_sort(), only 'priority' (critical path)
15646 considerations precede dispatch-slot restriction considerations. */
f676971a
EC		 15647 return (priority + 1);
15648 }
79ae11c4 15649
bef84347
VM		 15650 return priority;
15651}
15652
a4f6c312
SS		 15653/* Return how many instructions the machine can issue per cycle. */
15654
c237e94a 15655static int
863d938c 15656rs6000_issue_rate (void)
b6c9286a 15657{
3317bab1
DE		 15658 /* Use issue rate of 1 for first scheduling pass to decrease degradation. */
15659 if (!reload_completed)
15660 return 1;
15661
b6c9286a 15662 switch (rs6000_cpu_attr) {
3cb999d8
DE		 15663 case CPU_RIOS1: /* ? */
15664 case CPU_RS64A:
15665 case CPU_PPC601: /* ? */
ed947a96 15666 case CPU_PPC7450:
3cb999d8 15667 return 3;
b54cf83a 15668 case CPU_PPC440:
b6c9286a 15669 case CPU_PPC603:
bef84347 15670 case CPU_PPC750:
ed947a96 15671 case CPU_PPC7400:
be12c2b0 15672 case CPU_PPC8540:
f676971a 15673 return 2;
3cb999d8 15674 case CPU_RIOS2:
b6c9286a 15675 case CPU_PPC604:
19684119 15676 case CPU_PPC604E:
b6c9286a 15677 case CPU_PPC620:
3cb999d8 15678 case CPU_PPC630:
b6c9286a 15679 return 4;
cbe26ab8 15680 case CPU_POWER4:
ec507f2d 15681 case CPU_POWER5:
cbe26ab8 15682 return 5;
b6c9286a
MM		 15683 default:
15684 return 1;
15685 }
15686}
15687
be12c2b0
VM		 15688/* Return how many instructions to look ahead for better insn
15689 scheduling. */
15690
15691static int
863d938c 15692rs6000_use_sched_lookahead (void)
be12c2b0
VM		 15693{
15694 if (rs6000_cpu_attr == CPU_PPC8540)
15695 return 4;
15696 return 0;
15697}
15698
569fa502
DN		 15699/* Determine is PAT refers to memory. */
15700
15701static bool
15702is_mem_ref (rtx pat)
15703{
15704 const char * fmt;
15705 int i, j;
15706 bool ret = false;
15707
15708 if (GET_CODE (pat) == MEM)
15709 return true;
15710
15711 /* Recursively process the pattern. */
15712 fmt = GET_RTX_FORMAT (GET_CODE (pat));
15713
15714 for (i = GET_RTX_LENGTH (GET_CODE (pat)) - 1; i >= 0 && !ret; i--)
15715 {
15716 if (fmt[i] == 'e')
15717 ret |= is_mem_ref (XEXP (pat, i));
15718 else if (fmt[i] == 'E')
15719 for (j = XVECLEN (pat, i) - 1; j >= 0; j--)
15720 ret |= is_mem_ref (XVECEXP (pat, i, j));
15721 }
15722
15723 return ret;
15724}
15725
15726/* Determine if PAT is a PATTERN of a load insn. */
f676971a 15727
569fa502
DN		 15728static bool
15729is_load_insn1 (rtx pat)
15730{
15731 if (!pat || pat == NULL_RTX)
15732 return false;
15733
15734 if (GET_CODE (pat) == SET)
15735 return is_mem_ref (SET_SRC (pat));
15736
15737 if (GET_CODE (pat) == PARALLEL)
15738 {
15739 int i;
15740
15741 for (i = 0; i < XVECLEN (pat, 0); i++)
15742 if (is_load_insn1 (XVECEXP (pat, 0, i)))
15743 return true;
15744 }
15745
15746 return false;
15747}
15748
15749/* Determine if INSN loads from memory. */
15750
15751static bool
15752is_load_insn (rtx insn)
15753{
15754 if (!insn || !INSN_P (insn))
15755 return false;
15756
15757 if (GET_CODE (insn) == CALL_INSN)
15758 return false;
15759
15760 return is_load_insn1 (PATTERN (insn));
15761}
15762
15763/* Determine if PAT is a PATTERN of a store insn. */
15764
15765static bool
15766is_store_insn1 (rtx pat)
15767{
15768 if (!pat || pat == NULL_RTX)
15769 return false;
15770
15771 if (GET_CODE (pat) == SET)
15772 return is_mem_ref (SET_DEST (pat));
15773
15774 if (GET_CODE (pat) == PARALLEL)
15775 {
15776 int i;
15777
15778 for (i = 0; i < XVECLEN (pat, 0); i++)
15779 if (is_store_insn1 (XVECEXP (pat, 0, i)))
15780 return true;
15781 }
15782
15783 return false;
15784}
15785
15786/* Determine if INSN stores to memory. */
15787
15788static bool
15789is_store_insn (rtx insn)
15790{
15791 if (!insn || !INSN_P (insn))
15792 return false;
15793
15794 return is_store_insn1 (PATTERN (insn));
15795}
15796
15797/* Returns whether the dependence between INSN and NEXT is considered
15798 costly by the given target. */
15799
15800static bool
c4ad648e
AM		 15801rs6000_is_costly_dependence (rtx insn, rtx next, rtx link, int cost,
15802 int distance)
f676971a 15803{
aabcd309 15804 /* If the flag is not enabled - no dependence is considered costly;
f676971a 15805 allow all dependent insns in the same group.
569fa502
DN		 15806 This is the most aggressive option. */
15807 if (rs6000_sched_costly_dep == no_dep_costly)
15808 return false;
15809
f676971a 15810 /* If the flag is set to 1 - a dependence is always considered costly;
569fa502
DN		 15811 do not allow dependent instructions in the same group.
15812 This is the most conservative option. */
15813 if (rs6000_sched_costly_dep == all_deps_costly)
f676971a 15814 return true;
569fa502 15815
f676971a
EC		 15816 if (rs6000_sched_costly_dep == store_to_load_dep_costly
15817 && is_load_insn (next)
569fa502
DN		 15818 && is_store_insn (insn))
15819 /* Prevent load after store in the same group. */
15820 return true;
15821
15822 if (rs6000_sched_costly_dep == true_store_to_load_dep_costly
f676971a 15823 && is_load_insn (next)
569fa502
DN		 15824 && is_store_insn (insn)
15825 && (!link || (int) REG_NOTE_KIND (link) == 0))
c4ad648e
AM		 15826 /* Prevent load after store in the same group if it is a true
15827 dependence. */
569fa502 15828 return true;
f676971a
EC		 15829
15830 /* The flag is set to X; dependences with latency >= X are considered costly,
569fa502
DN		 15831 and will not be scheduled in the same group. */
15832 if (rs6000_sched_costly_dep <= max_dep_latency
15833 && ((cost - distance) >= (int)rs6000_sched_costly_dep))
15834 return true;
15835
15836 return false;
15837}
15838
f676971a 15839/* Return the next insn after INSN that is found before TAIL is reached,
cbe26ab8
DN		 15840 skipping any "non-active" insns - insns that will not actually occupy
15841 an issue slot. Return NULL_RTX if such an insn is not found. */
15842
15843static rtx
15844get_next_active_insn (rtx insn, rtx tail)
15845{
15846 rtx next_insn;
15847
15848 if (!insn || insn == tail)
15849 return NULL_RTX;
15850
15851 next_insn = NEXT_INSN (insn);
15852
15853 while (next_insn
15854 && next_insn != tail
9390387d 15855 && (GET_CODE (next_insn) == NOTE
cbe26ab8
DN		 15856 || GET_CODE (PATTERN (next_insn)) == USE
15857 || GET_CODE (PATTERN (next_insn)) == CLOBBER))
15858 {
15859 next_insn = NEXT_INSN (next_insn);
15860 }
15861
15862 if (!next_insn || next_insn == tail)
15863 return NULL_RTX;
15864
15865 return next_insn;
15866}
15867
839a4992 15868/* Return whether the presence of INSN causes a dispatch group termination
cbe26ab8
DN		 15869 of group WHICH_GROUP.
15870
15871 If WHICH_GROUP == current_group, this function will return true if INSN
15872 causes the termination of the current group (i.e, the dispatch group to
15873 which INSN belongs). This means that INSN will be the last insn in the
15874 group it belongs to.
15875
15876 If WHICH_GROUP == previous_group, this function will return true if INSN
15877 causes the termination of the previous group (i.e, the dispatch group that
15878 precedes the group to which INSN belongs). This means that INSN will be
15879 the first insn in the group it belongs to). */
15880
15881static bool
15882insn_terminates_group_p (rtx insn, enum group_termination which_group)
15883{
15884 enum attr_type type;
15885
15886 if (! insn)
15887 return false;
569fa502 15888
cbe26ab8
DN		 15889 type = get_attr_type (insn);
15890
15891 if (is_microcoded_insn (insn))
15892 return true;
15893
15894 if (which_group == current_group)
15895 {
15896 if (is_branch_slot_insn (insn))
c4ad648e 15897 return true;
cbe26ab8
DN		 15898 return false;
15899 }
15900 else if (which_group == previous_group)
15901 {
15902 if (is_dispatch_slot_restricted (insn))
c4ad648e 15903 return true;
cbe26ab8
DN		 15904 return false;
15905 }
15906
15907 return false;
15908}
15909
839a4992 15910/* Return true if it is recommended to keep NEXT_INSN "far" (in a separate
cbe26ab8
DN		 15911 dispatch group) from the insns in GROUP_INSNS. Return false otherwise. */
15912
15913static bool
15914is_costly_group (rtx *group_insns, rtx next_insn)
15915{
15916 int i;
15917 rtx link;
15918 int cost;
15919 int issue_rate = rs6000_issue_rate ();
15920
15921 for (i = 0; i < issue_rate; i++)
15922 {
15923 rtx insn = group_insns[i];
15924 if (!insn)
c4ad648e 15925 continue;
cbe26ab8 15926 for (link = INSN_DEPEND (insn); link != 0; link = XEXP (link, 1))
c4ad648e
AM		 15927 {
15928 rtx next = XEXP (link, 0);
15929 if (next == next_insn)
15930 {
15931 cost = insn_cost (insn, link, next_insn);
15932 if (rs6000_is_costly_dependence (insn, next_insn, link, cost, 0))
15933 return true;
15934 }
15935 }
cbe26ab8
DN		 15936 }
15937
15938 return false;
15939}
15940
f676971a 15941/* Utility of the function redefine_groups.
cbe26ab8
DN		 15942 Check if it is too costly to schedule NEXT_INSN together with GROUP_INSNS
15943 in the same dispatch group. If so, insert nops before NEXT_INSN, in order
15944 to keep it "far" (in a separate group) from GROUP_INSNS, following
15945 one of the following schemes, depending on the value of the flag
15946 -minsert_sched_nops = X:
15947 (1) X == sched_finish_regroup_exact: insert exactly as many nops as needed
839a4992 15948 in order to force NEXT_INSN into a separate group.
f676971a
EC		 15949 (2) X < sched_finish_regroup_exact: insert exactly X nops.
15950 GROUP_END, CAN_ISSUE_MORE and GROUP_COUNT record the state after nop
cbe26ab8
DN		 15951 insertion (has a group just ended, how many vacant issue slots remain in the
15952 last group, and how many dispatch groups were encountered so far). */
15953
f676971a 15954static int
c4ad648e
AM		 15955force_new_group (int sched_verbose, FILE *dump, rtx *group_insns,
15956 rtx next_insn, bool *group_end, int can_issue_more,
15957 int *group_count)
cbe26ab8
DN		 15958{
15959 rtx nop;
15960 bool force;
15961 int issue_rate = rs6000_issue_rate ();
15962 bool end = *group_end;
15963 int i;
15964
15965 if (next_insn == NULL_RTX)
15966 return can_issue_more;
15967
15968 if (rs6000_sched_insert_nops > sched_finish_regroup_exact)
15969 return can_issue_more;
15970
15971 force = is_costly_group (group_insns, next_insn);
15972 if (!force)
15973 return can_issue_more;
15974
15975 if (sched_verbose > 6)
15976 fprintf (dump,"force: group count = %d, can_issue_more = %d\n",
c4ad648e 15977 *group_count ,can_issue_more);
cbe26ab8
DN		 15978
15979 if (rs6000_sched_insert_nops == sched_finish_regroup_exact)
15980 {
15981 if (*group_end)
c4ad648e 15982 can_issue_more = 0;
cbe26ab8
DN		 15983
15984 /* Since only a branch can be issued in the last issue_slot, it is
15985 sufficient to insert 'can_issue_more - 1' nops if next_insn is not
15986 a branch. If next_insn is a branch, we insert 'can_issue_more' nops;
c4ad648e
AM		 15987 in this case the last nop will start a new group and the branch
15988 will be forced to the new group. */
cbe26ab8 15989 if (can_issue_more && !is_branch_slot_insn (next_insn))
c4ad648e 15990 can_issue_more--;
cbe26ab8
DN		 15991
15992 while (can_issue_more > 0)
c4ad648e 15993 {
9390387d 15994 nop = gen_nop ();
c4ad648e
AM		 15995 emit_insn_before (nop, next_insn);
15996 can_issue_more--;
15997 }
cbe26ab8
DN		 15998
15999 *group_end = true;
16000 return 0;
f676971a 16001 }
cbe26ab8
DN		 16002
16003 if (rs6000_sched_insert_nops < sched_finish_regroup_exact)
16004 {
16005 int n_nops = rs6000_sched_insert_nops;
16006
f676971a 16007 /* Nops can't be issued from the branch slot, so the effective
c4ad648e 16008 issue_rate for nops is 'issue_rate - 1'. */
cbe26ab8 16009 if (can_issue_more == 0)
c4ad648e 16010 can_issue_more = issue_rate;
cbe26ab8
DN		 16011 can_issue_more--;
16012 if (can_issue_more == 0)
c4ad648e
AM		 16013 {
16014 can_issue_more = issue_rate - 1;
16015 (*group_count)++;
16016 end = true;
16017 for (i = 0; i < issue_rate; i++)
16018 {
16019 group_insns[i] = 0;
16020 }
16021 }
cbe26ab8
DN		 16022
16023 while (n_nops > 0)
c4ad648e
AM		 16024 {
16025 nop = gen_nop ();
16026 emit_insn_before (nop, next_insn);
16027 if (can_issue_more == issue_rate - 1) /* new group begins */
16028 end = false;
16029 can_issue_more--;
16030 if (can_issue_more == 0)
16031 {
16032 can_issue_more = issue_rate - 1;
16033 (*group_count)++;
16034 end = true;
16035 for (i = 0; i < issue_rate; i++)
16036 {
16037 group_insns[i] = 0;
16038 }
16039 }
16040 n_nops--;
16041 }
cbe26ab8
DN		 16042
16043 /* Scale back relative to 'issue_rate' (instead of 'issue_rate - 1'). */
f676971a 16044 can_issue_more++;
cbe26ab8 16045
c4ad648e
AM		 16046 /* Is next_insn going to start a new group? */
16047 *group_end
16048 = (end
cbe26ab8
DN		 16049 || (can_issue_more == 1 && !is_branch_slot_insn (next_insn))
16050 || (can_issue_more <= 2 && is_cracked_insn (next_insn))
16051 || (can_issue_more < issue_rate &&
c4ad648e 16052 insn_terminates_group_p (next_insn, previous_group)));
cbe26ab8 16053 if (*group_end && end)
c4ad648e 16054 (*group_count)--;
cbe26ab8
DN		 16055
16056 if (sched_verbose > 6)
c4ad648e
AM		 16057 fprintf (dump, "done force: group count = %d, can_issue_more = %d\n",
16058 *group_count, can_issue_more);
f676971a
EC		 16059 return can_issue_more;
16060 }
cbe26ab8
DN		 16061
16062 return can_issue_more;
16063}
16064
16065/* This function tries to synch the dispatch groups that the compiler "sees"
f676971a 16066 with the dispatch groups that the processor dispatcher is expected to
cbe26ab8
DN		 16067 form in practice. It tries to achieve this synchronization by forcing the
16068 estimated processor grouping on the compiler (as opposed to the function
16069 'pad_goups' which tries to force the scheduler's grouping on the processor).
16070
16071 The function scans the insn sequence between PREV_HEAD_INSN and TAIL and
16072 examines the (estimated) dispatch groups that will be formed by the processor
16073 dispatcher. It marks these group boundaries to reflect the estimated
16074 processor grouping, overriding the grouping that the scheduler had marked.
16075 Depending on the value of the flag '-minsert-sched-nops' this function can
16076 force certain insns into separate groups or force a certain distance between
16077 them by inserting nops, for example, if there exists a "costly dependence"
16078 between the insns.
16079
16080 The function estimates the group boundaries that the processor will form as
16081 folllows: It keeps track of how many vacant issue slots are available after
16082 each insn. A subsequent insn will start a new group if one of the following
16083 4 cases applies:
16084 - no more vacant issue slots remain in the current dispatch group.
16085 - only the last issue slot, which is the branch slot, is vacant, but the next
16086 insn is not a branch.
16087 - only the last 2 or less issue slots, including the branch slot, are vacant,
16088 which means that a cracked insn (which occupies two issue slots) can't be
16089 issued in this group.
f676971a 16090 - less than 'issue_rate' slots are vacant, and the next insn always needs to
cbe26ab8
DN		 16091 start a new group. */
16092
16093static int
16094redefine_groups (FILE *dump, int sched_verbose, rtx prev_head_insn, rtx tail)
16095{
16096 rtx insn, next_insn;
16097 int issue_rate;
16098 int can_issue_more;
16099 int slot, i;
16100 bool group_end;
16101 int group_count = 0;
16102 rtx *group_insns;
16103
16104 /* Initialize. */
16105 issue_rate = rs6000_issue_rate ();
16106 group_insns = alloca (issue_rate * sizeof (rtx));
f676971a 16107 for (i = 0; i < issue_rate; i++)
cbe26ab8
DN		 16108 {
16109 group_insns[i] = 0;
16110 }
16111 can_issue_more = issue_rate;
16112 slot = 0;
16113 insn = get_next_active_insn (prev_head_insn, tail);
16114 group_end = false;
16115
16116 while (insn != NULL_RTX)
16117 {
16118 slot = (issue_rate - can_issue_more);
16119 group_insns[slot] = insn;
16120 can_issue_more =
c4ad648e 16121 rs6000_variable_issue (dump, sched_verbose, insn, can_issue_more);
cbe26ab8 16122 if (insn_terminates_group_p (insn, current_group))
c4ad648e 16123 can_issue_more = 0;
cbe26ab8
DN		 16124
16125 next_insn = get_next_active_insn (insn, tail);
16126 if (next_insn == NULL_RTX)
c4ad648e 16127 return group_count + 1;
cbe26ab8 16128
c4ad648e
AM		 16129 /* Is next_insn going to start a new group? */
16130 group_end
16131 = (can_issue_more == 0
16132 || (can_issue_more == 1 && !is_branch_slot_insn (next_insn))
16133 || (can_issue_more <= 2 && is_cracked_insn (next_insn))
16134 || (can_issue_more < issue_rate &&
16135 insn_terminates_group_p (next_insn, previous_group)));
cbe26ab8 16136
f676971a 16137 can_issue_more = force_new_group (sched_verbose, dump, group_insns,
c4ad648e
AM		 16138 next_insn, &group_end, can_issue_more,
16139 &group_count);
cbe26ab8
DN		 16140
16141 if (group_end)
c4ad648e
AM		 16142 {
16143 group_count++;
16144 can_issue_more = 0;
16145 for (i = 0; i < issue_rate; i++)
16146 {
16147 group_insns[i] = 0;
16148 }
16149 }
cbe26ab8
DN		 16150
16151 if (GET_MODE (next_insn) == TImode && can_issue_more)
9390387d 16152 PUT_MODE (next_insn, VOIDmode);
cbe26ab8 16153 else if (!can_issue_more && GET_MODE (next_insn) != TImode)
c4ad648e 16154 PUT_MODE (next_insn, TImode);
cbe26ab8
DN		 16155
16156 insn = next_insn;
16157 if (can_issue_more == 0)
c4ad648e
AM		 16158 can_issue_more = issue_rate;
16159 } /* while */
cbe26ab8
DN		 16160
16161 return group_count;
16162}
16163
16164/* Scan the insn sequence between PREV_HEAD_INSN and TAIL and examine the
16165 dispatch group boundaries that the scheduler had marked. Pad with nops
16166 any dispatch groups which have vacant issue slots, in order to force the
16167 scheduler's grouping on the processor dispatcher. The function
16168 returns the number of dispatch groups found. */
16169
16170static int
16171pad_groups (FILE *dump, int sched_verbose, rtx prev_head_insn, rtx tail)
16172{
16173 rtx insn, next_insn;
16174 rtx nop;
16175 int issue_rate;
16176 int can_issue_more;
16177 int group_end;
16178 int group_count = 0;
16179
16180 /* Initialize issue_rate. */
16181 issue_rate = rs6000_issue_rate ();
16182 can_issue_more = issue_rate;
16183
16184 insn = get_next_active_insn (prev_head_insn, tail);
16185 next_insn = get_next_active_insn (insn, tail);
16186
16187 while (insn != NULL_RTX)
16188 {
16189 can_issue_more =
16190 rs6000_variable_issue (dump, sched_verbose, insn, can_issue_more);
16191
16192 group_end = (next_insn == NULL_RTX || GET_MODE (next_insn) == TImode);
16193
16194 if (next_insn == NULL_RTX)
c4ad648e 16195 break;
cbe26ab8
DN		 16196
16197 if (group_end)
c4ad648e
AM		 16198 {
16199 /* If the scheduler had marked group termination at this location
16200 (between insn and next_indn), and neither insn nor next_insn will
16201 force group termination, pad the group with nops to force group
16202 termination. */
16203 if (can_issue_more
16204 && (rs6000_sched_insert_nops == sched_finish_pad_groups)
16205 && !insn_terminates_group_p (insn, current_group)
16206 && !insn_terminates_group_p (next_insn, previous_group))
16207 {
9390387d 16208 if (!is_branch_slot_insn (next_insn))
c4ad648e
AM		 16209 can_issue_more--;
16210
16211 while (can_issue_more)
16212 {
16213 nop = gen_nop ();
16214 emit_insn_before (nop, next_insn);
16215 can_issue_more--;
16216 }
16217 }
16218
16219 can_issue_more = issue_rate;
16220 group_count++;
16221 }
cbe26ab8
DN		 16222
16223 insn = next_insn;
16224 next_insn = get_next_active_insn (insn, tail);
16225 }
16226
16227 return group_count;
16228}
16229
16230/* The following function is called at the end of scheduling BB.
16231 After reload, it inserts nops at insn group bundling. */
16232
16233static void
38f391a5 16234rs6000_sched_finish (FILE *dump, int sched_verbose)
cbe26ab8
DN		 16235{
16236 int n_groups;
16237
16238 if (sched_verbose)
16239 fprintf (dump, "=== Finishing schedule.\n");
16240
ec507f2d 16241 if (reload_completed && rs6000_sched_groups)
cbe26ab8
DN		 16242 {
16243 if (rs6000_sched_insert_nops == sched_finish_none)
c4ad648e 16244 return;
cbe26ab8
DN		 16245
16246 if (rs6000_sched_insert_nops == sched_finish_pad_groups)
c4ad648e
AM		 16247 n_groups = pad_groups (dump, sched_verbose,
16248 current_sched_info->prev_head,
16249 current_sched_info->next_tail);
cbe26ab8 16250 else
c4ad648e
AM		 16251 n_groups = redefine_groups (dump, sched_verbose,
16252 current_sched_info->prev_head,
16253 current_sched_info->next_tail);
cbe26ab8
DN		 16254
16255 if (sched_verbose >= 6)
16256 {
16257 fprintf (dump, "ngroups = %d\n", n_groups);
16258 print_rtl (dump, current_sched_info->prev_head);
16259 fprintf (dump, "Done finish_sched\n");
16260 }
16261 }
16262}
b6c9286a 16263\f
b6c9286a
MM		 16264/* Length in units of the trampoline for entering a nested function. */
16265
16266int
863d938c 16267rs6000_trampoline_size (void)
b6c9286a
MM		 16268{
16269 int ret = 0;
16270
16271 switch (DEFAULT_ABI)
16272 {
16273 default:
37409796 16274 gcc_unreachable ();
b6c9286a
MM		 16275
16276 case ABI_AIX:
8f802bfb 16277 ret = (TARGET_32BIT) ? 12 : 24;
b6c9286a
MM		 16278 break;
16279
4dabc42d 16280 case ABI_DARWIN:
b6c9286a 16281 case ABI_V4:
03a7e1a5 16282 ret = (TARGET_32BIT) ? 40 : 48;
b6c9286a 16283 break;
b6c9286a
MM		 16284 }
16285
16286 return ret;
16287}
16288
16289/* Emit RTL insns to initialize the variable parts of a trampoline.
16290 FNADDR is an RTX for the address of the function's pure code.
16291 CXT is an RTX for the static chain value for the function. */
16292
16293void
a2369ed3 16294rs6000_initialize_trampoline (rtx addr, rtx fnaddr, rtx cxt)
b6c9286a 16295{
ac2a93a1 16296 enum machine_mode pmode = Pmode;
8bd04c56
MM		 16297 int regsize = (TARGET_32BIT) ? 4 : 8;
16298 rtx ctx_reg = force_reg (pmode, cxt);
b6c9286a
MM		 16299
16300 switch (DEFAULT_ABI)
16301 {
16302 default:
37409796 16303 gcc_unreachable ();
b6c9286a 16304
8bd04c56 16305/* Macros to shorten the code expansions below. */
39403d82 16306#define MEM_DEREF(addr) gen_rtx_MEM (pmode, memory_address (pmode, addr))
c5c76735
JL		 16307#define MEM_PLUS(addr,offset) \
16308 gen_rtx_MEM (pmode, memory_address (pmode, plus_constant (addr, offset)))
7c59dc5d 16309
b6c9286a
MM		 16310 /* Under AIX, just build the 3 word function descriptor */
16311 case ABI_AIX:
8bd04c56
MM		 16312 {
16313 rtx fn_reg = gen_reg_rtx (pmode);
16314 rtx toc_reg = gen_reg_rtx (pmode);
16315 emit_move_insn (fn_reg, MEM_DEREF (fnaddr));
1cb18e3c 16316 emit_move_insn (toc_reg, MEM_PLUS (fnaddr, regsize));
8bd04c56
MM		 16317 emit_move_insn (MEM_DEREF (addr), fn_reg);
16318 emit_move_insn (MEM_PLUS (addr, regsize), toc_reg);
16319 emit_move_insn (MEM_PLUS (addr, 2*regsize), ctx_reg);
16320 }
b6c9286a
MM		 16321 break;
16322
4dabc42d
TC		 16323 /* Under V.4/eabi/darwin, __trampoline_setup does the real work. */
16324 case ABI_DARWIN:
b6c9286a 16325 case ABI_V4:
39403d82 16326 emit_library_call (gen_rtx_SYMBOL_REF (SImode, "__trampoline_setup"),
eaf1bcf1
MM		 16327 FALSE, VOIDmode, 4,
16328 addr, pmode,
16329 GEN_INT (rs6000_trampoline_size ()), SImode,
16330 fnaddr, pmode,
16331 ctx_reg, pmode);
b6c9286a 16332 break;
b6c9286a
MM		 16333 }
16334
16335 return;
16336}
7509c759
MM		 16337
16338\f
91d231cb 16339/* Table of valid machine attributes. */
a4f6c312 16340
91d231cb 16341const struct attribute_spec rs6000_attribute_table[] =
7509c759 16342{
91d231cb 16343 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
8bb418a3 16344 { "altivec", 1, 1, false, true, false, rs6000_handle_altivec_attribute },
a5c76ee6
ZW		 16345 { "longcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute },
16346 { "shortcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute },
005c1a13
GK		 16347#ifdef SUBTARGET_ATTRIBUTE_TABLE
16348 SUBTARGET_ATTRIBUTE_TABLE,
16349#endif
a5c76ee6 16350 { NULL, 0, 0, false, false, false, NULL }
91d231cb 16351};
7509c759 16352
8bb418a3
ZL		 16353/* Handle the "altivec" attribute. The attribute may have
16354 arguments as follows:
f676971a 16355
8bb418a3
ZL		 16356 __attribute__((altivec(vector__)))
16357 __attribute__((altivec(pixel__))) (always followed by 'unsigned short')
16358 __attribute__((altivec(bool__))) (always followed by 'unsigned')
16359
16360 and may appear more than once (e.g., 'vector bool char') in a
16361 given declaration. */
16362
16363static tree
f90ac3f0
UP		 16364rs6000_handle_altivec_attribute (tree *node,
16365 tree name ATTRIBUTE_UNUSED,
16366 tree args,
8bb418a3
ZL		 16367 int flags ATTRIBUTE_UNUSED,
16368 bool *no_add_attrs)
16369{
16370 tree type = *node, result = NULL_TREE;
16371 enum machine_mode mode;
16372 int unsigned_p;
16373 char altivec_type
16374 = ((args && TREE_CODE (args) == TREE_LIST && TREE_VALUE (args)
16375 && TREE_CODE (TREE_VALUE (args)) == IDENTIFIER_NODE)
16376 ? *IDENTIFIER_POINTER (TREE_VALUE (args))
f676971a 16377 : '?');
8bb418a3
ZL		 16378
16379 while (POINTER_TYPE_P (type)
16380 || TREE_CODE (type) == FUNCTION_TYPE
16381 || TREE_CODE (type) == METHOD_TYPE
16382 || TREE_CODE (type) == ARRAY_TYPE)
16383 type = TREE_TYPE (type);
16384
16385 mode = TYPE_MODE (type);
16386
f90ac3f0
UP		 16387 /* Check for invalid AltiVec type qualifiers. */
16388 if (type == long_unsigned_type_node || type == long_integer_type_node)
16389 {
16390 if (TARGET_64BIT)
16391 error ("use of %<long%> in AltiVec types is invalid for 64-bit code");
16392 else if (rs6000_warn_altivec_long)
d4ee4d25 16393 warning (0, "use of %<long%> in AltiVec types is deprecated; use %<int%>");
f90ac3f0
UP		 16394 }
16395 else if (type == long_long_unsigned_type_node
16396 || type == long_long_integer_type_node)
16397 error ("use of %<long long%> in AltiVec types is invalid");
16398 else if (type == double_type_node)
16399 error ("use of %<double%> in AltiVec types is invalid");
16400 else if (type == long_double_type_node)
16401 error ("use of %<long double%> in AltiVec types is invalid");
16402 else if (type == boolean_type_node)
16403 error ("use of boolean types in AltiVec types is invalid");
16404 else if (TREE_CODE (type) == COMPLEX_TYPE)
16405 error ("use of %<complex%> in AltiVec types is invalid");
8bb418a3
ZL		 16406
16407 switch (altivec_type)
16408 {
16409 case 'v':
8df83eae 16410 unsigned_p = TYPE_UNSIGNED (type);
8bb418a3
ZL		 16411 switch (mode)
16412 {
c4ad648e
AM		 16413 case SImode:
16414 result = (unsigned_p ? unsigned_V4SI_type_node : V4SI_type_node);
16415 break;
16416 case HImode:
16417 result = (unsigned_p ? unsigned_V8HI_type_node : V8HI_type_node);
16418 break;
16419 case QImode:
16420 result = (unsigned_p ? unsigned_V16QI_type_node : V16QI_type_node);
16421 break;
16422 case SFmode: result = V4SF_type_node; break;
16423 /* If the user says 'vector int bool', we may be handed the 'bool'
16424 attribute _before_ the 'vector' attribute, and so select the
16425 proper type in the 'b' case below. */
16426 case V4SImode: case V8HImode: case V16QImode: case V4SFmode:
16427 result = type;
16428 default: break;
8bb418a3
ZL		 16429 }
16430 break;
16431 case 'b':
16432 switch (mode)
16433 {
c4ad648e
AM		 16434 case SImode: case V4SImode: result = bool_V4SI_type_node; break;
16435 case HImode: case V8HImode: result = bool_V8HI_type_node; break;
16436 case QImode: case V16QImode: result = bool_V16QI_type_node;
16437 default: break;
8bb418a3
ZL		 16438 }
16439 break;
16440 case 'p':
16441 switch (mode)
16442 {
c4ad648e
AM		 16443 case V8HImode: result = pixel_V8HI_type_node;
16444 default: break;
8bb418a3
ZL		 16445 }
16446 default: break;
16447 }
16448
7958a2a6
FJ		 16449 if (result && result != type && TYPE_READONLY (type))
16450 result = build_qualified_type (result, TYPE_QUAL_CONST);
16451
8bb418a3
ZL		 16452 *no_add_attrs = true; /* No need to hang on to the attribute. */
16453
f90ac3f0 16454 if (result)
8bb418a3
ZL		 16455 *node = reconstruct_complex_type (*node, result);
16456
16457 return NULL_TREE;
16458}
16459
f18eca82
ZL		 16460/* AltiVec defines four built-in scalar types that serve as vector
16461 elements; we must teach the compiler how to mangle them. */
16462
16463static const char *
16464rs6000_mangle_fundamental_type (tree type)
16465{
16466 if (type == bool_char_type_node) return "U6__boolc";
16467 if (type == bool_short_type_node) return "U6__bools";
16468 if (type == pixel_type_node) return "u7__pixel";
16469 if (type == bool_int_type_node) return "U6__booli";
16470
16471 /* For all other types, use normal C++ mangling. */
16472 return NULL;
16473}
16474
a5c76ee6
ZW		 16475/* Handle a "longcall" or "shortcall" attribute; arguments as in
16476 struct attribute_spec.handler. */
a4f6c312 16477
91d231cb 16478static tree
f676971a
EC		 16479rs6000_handle_longcall_attribute (tree *node, tree name,
16480 tree args ATTRIBUTE_UNUSED,
16481 int flags ATTRIBUTE_UNUSED,
a2369ed3 16482 bool *no_add_attrs)
91d231cb
JM		 16483{
16484 if (TREE_CODE (*node) != FUNCTION_TYPE
16485 && TREE_CODE (*node) != FIELD_DECL
16486 && TREE_CODE (*node) != TYPE_DECL)
16487 {
d4ee4d25 16488 warning (0, "%qs attribute only applies to functions",
91d231cb
JM		 16489 IDENTIFIER_POINTER (name));
16490 *no_add_attrs = true;
16491 }
6a4cee5f 16492
91d231cb 16493 return NULL_TREE;
7509c759
MM		 16494}
16495
a5c76ee6
ZW		 16496/* Set longcall attributes on all functions declared when
16497 rs6000_default_long_calls is true. */
16498static void
a2369ed3 16499rs6000_set_default_type_attributes (tree type)
a5c76ee6
ZW		 16500{
16501 if (rs6000_default_long_calls
16502 && (TREE_CODE (type) == FUNCTION_TYPE
16503 || TREE_CODE (type) == METHOD_TYPE))
16504 TYPE_ATTRIBUTES (type) = tree_cons (get_identifier ("longcall"),
16505 NULL_TREE,
16506 TYPE_ATTRIBUTES (type));
16507}
16508
3cb999d8
DE		 16509/* Return a reference suitable for calling a function with the
16510 longcall attribute. */
a4f6c312 16511
9390387d 16512rtx
a2369ed3 16513rs6000_longcall_ref (rtx call_ref)
6a4cee5f 16514{
d330fd93 16515 const char *call_name;
6a4cee5f
MM		 16516 tree node;
16517
16518 if (GET_CODE (call_ref) != SYMBOL_REF)
16519 return call_ref;
16520
16521 /* System V adds '.' to the internal name, so skip them. */
16522 call_name = XSTR (call_ref, 0);
16523 if (*call_name == '.')
16524 {
16525 while (*call_name == '.')
16526 call_name++;
16527
16528 node = get_identifier (call_name);
39403d82 16529 call_ref = gen_rtx_SYMBOL_REF (VOIDmode, IDENTIFIER_POINTER (node));
6a4cee5f
MM		 16530 }
16531
16532 return force_reg (Pmode, call_ref);
16533}
7509c759 16534\f
b64a1b53
RH		 16535#ifdef USING_ELFOS_H
16536
7509c759
MM		 16537/* A C statement or statements to switch to the appropriate section
16538 for output of RTX in mode MODE. You can assume that RTX is some
16539 kind of constant in RTL. The argument MODE is redundant except in
16540 the case of a `const_int' rtx. Select the section by calling
16541 `text_section' or one of the alternatives for other sections.
16542
16543 Do not define this macro if you put all constants in the read-only
16544 data section. */
16545
b64a1b53 16546static void
f676971a 16547rs6000_elf_select_rtx_section (enum machine_mode mode, rtx x,
a2369ed3 16548 unsigned HOST_WIDE_INT align)
7509c759 16549{
a9098fd0 16550 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode))
7509c759 16551 toc_section ();
7509c759 16552 else
b64a1b53 16553 default_elf_select_rtx_section (mode, x, align);
7509c759
MM		 16554}
16555
16556/* A C statement or statements to switch to the appropriate
16557 section for output of DECL. DECL is either a `VAR_DECL' node
16558 or a constant of some sort. RELOC indicates whether forming
16559 the initial value of DECL requires link-time relocations. */
16560
ae46c4e0 16561static void
f676971a 16562rs6000_elf_select_section (tree decl, int reloc,
a2369ed3 16563 unsigned HOST_WIDE_INT align)
7509c759 16564{
f1384257
AM		 16565 /* Pretend that we're always building for a shared library when
16566 ABI_AIX, because otherwise we end up with dynamic relocations
16567 in read-only sections. This happens for function pointers,
16568 references to vtables in typeinfo, and probably other cases. */
0e5dbd9b
DE		 16569 default_elf_select_section_1 (decl, reloc, align,
16570 flag_pic || DEFAULT_ABI == ABI_AIX);
63019373
GK		 16571}
16572
16573/* A C statement to build up a unique section name, expressed as a
16574 STRING_CST node, and assign it to DECL_SECTION_NAME (decl).
16575 RELOC indicates whether the initial value of EXP requires
16576 link-time relocations. If you do not define this macro, GCC will use
16577 the symbol name prefixed by `.' as the section name. Note - this
f5143c46 16578 macro can now be called for uninitialized data items as well as
4912a07c 16579 initialized data and functions. */
63019373 16580
ae46c4e0 16581static void
a2369ed3 16582rs6000_elf_unique_section (tree decl, int reloc)
63019373 16583{
f1384257
AM		 16584 /* As above, pretend that we're always building for a shared library
16585 when ABI_AIX, to avoid dynamic relocations in read-only sections. */
0e5dbd9b
DE		 16586 default_unique_section_1 (decl, reloc,
16587 flag_pic || DEFAULT_ABI == ABI_AIX);
7509c759 16588}
d9407988 16589\f
d1908feb
JJ		 16590/* For a SYMBOL_REF, set generic flags and then perform some
16591 target-specific processing.
16592
d1908feb
JJ		 16593 When the AIX ABI is requested on a non-AIX system, replace the
16594 function name with the real name (with a leading .) rather than the
16595 function descriptor name. This saves a lot of overriding code to
16596 read the prefixes. */
d9407988 16597
fb49053f 16598static void
a2369ed3 16599rs6000_elf_encode_section_info (tree decl, rtx rtl, int first)
d9407988 16600{
d1908feb 16601 default_encode_section_info (decl, rtl, first);
b2003250 16602
d1908feb
JJ		 16603 if (first
16604 && TREE_CODE (decl) == FUNCTION_DECL
16605 && !TARGET_AIX
16606 && DEFAULT_ABI == ABI_AIX)
d9407988 16607 {
c6a2438a 16608 rtx sym_ref = XEXP (rtl, 0);
d1908feb
JJ		 16609 size_t len = strlen (XSTR (sym_ref, 0));
16610 char *str = alloca (len + 2);
16611 str[0] = '.';
16612 memcpy (str + 1, XSTR (sym_ref, 0), len + 1);
16613 XSTR (sym_ref, 0) = ggc_alloc_string (str, len + 1);
d9407988 16614 }
d9407988
MM		 16615}
16616
0e5dbd9b 16617static bool
a2369ed3 16618rs6000_elf_in_small_data_p (tree decl)
0e5dbd9b
DE		 16619{
16620 if (rs6000_sdata == SDATA_NONE)
16621 return false;
16622
7482ad25
AF		 16623 /* We want to merge strings, so we never consider them small data. */
16624 if (TREE_CODE (decl) == STRING_CST)
16625 return false;
16626
16627 /* Functions are never in the small data area. */
16628 if (TREE_CODE (decl) == FUNCTION_DECL)
16629 return false;
16630
0e5dbd9b
DE		 16631 if (TREE_CODE (decl) == VAR_DECL && DECL_SECTION_NAME (decl))
16632 {
16633 const char *section = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
16634 if (strcmp (section, ".sdata") == 0
16635 || strcmp (section, ".sdata2") == 0
20bfcd69
GK		 16636 || strcmp (section, ".sbss") == 0
16637 || strcmp (section, ".sbss2") == 0
16638 || strcmp (section, ".PPC.EMB.sdata0") == 0
16639 || strcmp (section, ".PPC.EMB.sbss0") == 0)
0e5dbd9b
DE		 16640 return true;
16641 }
16642 else
16643 {
16644 HOST_WIDE_INT size = int_size_in_bytes (TREE_TYPE (decl));
16645
16646 if (size > 0
307b599c 16647 && (unsigned HOST_WIDE_INT) size <= g_switch_value
20bfcd69
GK		 16648 /* If it's not public, and we're not going to reference it there,
16649 there's no need to put it in the small data section. */
0e5dbd9b
DE		 16650 && (rs6000_sdata != SDATA_DATA || TREE_PUBLIC (decl)))
16651 return true;
16652 }
16653
16654 return false;
16655}
16656
b91da81f 16657#endif /* USING_ELFOS_H */
000034eb 16658
a6c2a102 16659\f
000034eb 16660/* Return a REG that occurs in ADDR with coefficient 1.
02441cd6
JL		 16661 ADDR can be effectively incremented by incrementing REG.
16662
16663 r0 is special and we must not select it as an address
16664 register by this routine since our caller will try to
16665 increment the returned register via an "la" instruction. */
000034eb 16666
9390387d 16667rtx
a2369ed3 16668find_addr_reg (rtx addr)
000034eb
DE		 16669{
16670 while (GET_CODE (addr) == PLUS)
16671 {
02441cd6
JL		 16672 if (GET_CODE (XEXP (addr, 0)) == REG
16673 && REGNO (XEXP (addr, 0)) != 0)
000034eb 16674 addr = XEXP (addr, 0);
02441cd6
JL		 16675 else if (GET_CODE (XEXP (addr, 1)) == REG
16676 && REGNO (XEXP (addr, 1)) != 0)
000034eb
DE		 16677 addr = XEXP (addr, 1);
16678 else if (CONSTANT_P (XEXP (addr, 0)))
16679 addr = XEXP (addr, 1);
16680 else if (CONSTANT_P (XEXP (addr, 1)))
16681 addr = XEXP (addr, 0);
16682 else
37409796 16683 gcc_unreachable ();
000034eb 16684 }
37409796
NS		 16685 gcc_assert (GET_CODE (addr) == REG && REGNO (addr) != 0);
16686 return addr;
000034eb
DE		 16687}
16688
a6c2a102 16689void
a2369ed3 16690rs6000_fatal_bad_address (rtx op)
a6c2a102
DE		 16691{
16692 fatal_insn ("bad address", op);
16693}
c8023011 16694
ee890fe2
SS		 16695#if TARGET_MACHO
16696
efdba735 16697static tree branch_island_list = 0;
ee890fe2 16698
efdba735
SH		 16699/* Remember to generate a branch island for far calls to the given
16700 function. */
ee890fe2 16701
f676971a 16702static void
c4ad648e
AM		 16703add_compiler_branch_island (tree label_name, tree function_name,
16704 int line_number)
ee890fe2 16705{
efdba735 16706 tree branch_island = build_tree_list (function_name, label_name);
7d60be94 16707 TREE_TYPE (branch_island) = build_int_cst (NULL_TREE, line_number);
efdba735
SH		 16708 TREE_CHAIN (branch_island) = branch_island_list;
16709 branch_island_list = branch_island;
ee890fe2
SS		 16710}
16711
efdba735
SH		 16712#define BRANCH_ISLAND_LABEL_NAME(BRANCH_ISLAND) TREE_VALUE (BRANCH_ISLAND)
16713#define BRANCH_ISLAND_FUNCTION_NAME(BRANCH_ISLAND) TREE_PURPOSE (BRANCH_ISLAND)
16714#define BRANCH_ISLAND_LINE_NUMBER(BRANCH_ISLAND) \
16715 TREE_INT_CST_LOW (TREE_TYPE (BRANCH_ISLAND))
ee890fe2 16716
efdba735
SH		 16717/* Generate far-jump branch islands for everything on the
16718 branch_island_list. Invoked immediately after the last instruction
16719 of the epilogue has been emitted; the branch-islands must be
16720 appended to, and contiguous with, the function body. Mach-O stubs
16721 are generated in machopic_output_stub(). */
ee890fe2 16722
efdba735
SH		 16723static void
16724macho_branch_islands (void)
16725{
16726 char tmp_buf[512];
16727 tree branch_island;
16728
16729 for (branch_island = branch_island_list;
16730 branch_island;
16731 branch_island = TREE_CHAIN (branch_island))
16732 {
16733 const char *label =
16734 IDENTIFIER_POINTER (BRANCH_ISLAND_LABEL_NAME (branch_island));
16735 const char *name =
11abc112 16736 IDENTIFIER_POINTER (BRANCH_ISLAND_FUNCTION_NAME (branch_island));
efdba735
SH		 16737 char name_buf[512];
16738 /* Cheap copy of the details from the Darwin ASM_OUTPUT_LABELREF(). */
16739 if (name[0] == '*' || name[0] == '&')
16740 strcpy (name_buf, name+1);
16741 else
16742 {
16743 name_buf[0] = '_';
16744 strcpy (name_buf+1, name);
16745 }
16746 strcpy (tmp_buf, "\n");
16747 strcat (tmp_buf, label);
ee890fe2 16748#if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
efdba735 16749 if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG)
93a27b7b 16750 dbxout_stabd (N_SLINE, BRANCH_ISLAND_LINE_NUMBER (branch_island));
ee890fe2 16751#endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
efdba735
SH		 16752 if (flag_pic)
16753 {
16754 strcat (tmp_buf, ":\n\tmflr r0\n\tbcl 20,31,");
16755 strcat (tmp_buf, label);
16756 strcat (tmp_buf, "_pic\n");
16757 strcat (tmp_buf, label);
16758 strcat (tmp_buf, "_pic:\n\tmflr r11\n");
f676971a 16759
efdba735
SH		 16760 strcat (tmp_buf, "\taddis r11,r11,ha16(");
16761 strcat (tmp_buf, name_buf);
16762 strcat (tmp_buf, " - ");
16763 strcat (tmp_buf, label);
16764 strcat (tmp_buf, "_pic)\n");
f676971a 16765
efdba735 16766 strcat (tmp_buf, "\tmtlr r0\n");
f676971a 16767
efdba735
SH		 16768 strcat (tmp_buf, "\taddi r12,r11,lo16(");
16769 strcat (tmp_buf, name_buf);
16770 strcat (tmp_buf, " - ");
16771 strcat (tmp_buf, label);
16772 strcat (tmp_buf, "_pic)\n");
f676971a 16773
efdba735
SH		 16774 strcat (tmp_buf, "\tmtctr r12\n\tbctr\n");
16775 }
16776 else
16777 {
16778 strcat (tmp_buf, ":\nlis r12,hi16(");
16779 strcat (tmp_buf, name_buf);
16780 strcat (tmp_buf, ")\n\tori r12,r12,lo16(");
16781 strcat (tmp_buf, name_buf);
16782 strcat (tmp_buf, ")\n\tmtctr r12\n\tbctr");
16783 }
16784 output_asm_insn (tmp_buf, 0);
ee890fe2 16785#if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
efdba735 16786 if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG)
93a27b7b 16787 dbxout_stabd (N_SLINE, BRANCH_ISLAND_LINE_NUMBER (branch_island));
ee890fe2 16788#endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
efdba735 16789 }
ee890fe2 16790
efdba735 16791 branch_island_list = 0;
ee890fe2
SS		 16792}
16793
16794/* NO_PREVIOUS_DEF checks in the link list whether the function name is
16795 already there or not. */
16796
efdba735 16797static int
a2369ed3 16798no_previous_def (tree function_name)
ee890fe2 16799{
efdba735
SH		 16800 tree branch_island;
16801 for (branch_island = branch_island_list;
16802 branch_island;
16803 branch_island = TREE_CHAIN (branch_island))
16804 if (function_name == BRANCH_ISLAND_FUNCTION_NAME (branch_island))
ee890fe2
SS		 16805 return 0;
16806 return 1;
16807}
16808
16809/* GET_PREV_LABEL gets the label name from the previous definition of
16810 the function. */
16811
efdba735 16812static tree
a2369ed3 16813get_prev_label (tree function_name)
ee890fe2 16814{
efdba735
SH		 16815 tree branch_island;
16816 for (branch_island = branch_island_list;
16817 branch_island;
16818 branch_island = TREE_CHAIN (branch_island))
16819 if (function_name == BRANCH_ISLAND_FUNCTION_NAME (branch_island))
16820 return BRANCH_ISLAND_LABEL_NAME (branch_island);
ee890fe2
SS		 16821 return 0;
16822}
16823
16824/* INSN is either a function call or a millicode call. It may have an
f676971a 16825 unconditional jump in its delay slot.
ee890fe2
SS		 16826
16827 CALL_DEST is the routine we are calling. */
16828
16829char *
c4ad648e
AM		 16830output_call (rtx insn, rtx *operands, int dest_operand_number,
16831 int cookie_operand_number)
ee890fe2
SS		 16832{
16833 static char buf[256];
efdba735
SH		 16834 if (GET_CODE (operands[dest_operand_number]) == SYMBOL_REF
16835 && (INTVAL (operands[cookie_operand_number]) & CALL_LONG))
ee890fe2
SS		 16836 {
16837 tree labelname;
efdba735 16838 tree funname = get_identifier (XSTR (operands[dest_operand_number], 0));
f676971a 16839
ee890fe2
SS		 16840 if (no_previous_def (funname))
16841 {
308c142a 16842 int line_number = 0;
ee890fe2
SS		 16843 rtx label_rtx = gen_label_rtx ();
16844 char *label_buf, temp_buf[256];
16845 ASM_GENERATE_INTERNAL_LABEL (temp_buf, "L",
16846 CODE_LABEL_NUMBER (label_rtx));
16847 label_buf = temp_buf[0] == '*' ? temp_buf + 1 : temp_buf;
16848 labelname = get_identifier (label_buf);
16849 for (; insn && GET_CODE (insn) != NOTE; insn = PREV_INSN (insn));
16850 if (insn)
16851 line_number = NOTE_LINE_NUMBER (insn);
efdba735 16852 add_compiler_branch_island (labelname, funname, line_number);
ee890fe2
SS		 16853 }
16854 else
16855 labelname = get_prev_label (funname);
16856
efdba735
SH		 16857 /* "jbsr foo, L42" is Mach-O for "Link as 'bl foo' if a 'bl'
16858 instruction will reach 'foo', otherwise link as 'bl L42'".
16859 "L42" should be a 'branch island', that will do a far jump to
16860 'foo'. Branch islands are generated in
16861 macho_branch_islands(). */
ee890fe2 16862 sprintf (buf, "jbsr %%z%d,%.246s",
efdba735 16863 dest_operand_number, IDENTIFIER_POINTER (labelname));
ee890fe2
SS		 16864 }
16865 else
efdba735
SH		 16866 sprintf (buf, "bl %%z%d", dest_operand_number);
16867 return buf;
ee890fe2
SS		 16868}
16869
ee890fe2
SS		 16870/* Generate PIC and indirect symbol stubs. */
16871
16872void
a2369ed3 16873machopic_output_stub (FILE *file, const char *symb, const char *stub)
ee890fe2
SS		 16874{
16875 unsigned int length;
a4f6c312
SS		 16876 char *symbol_name, *lazy_ptr_name;
16877 char *local_label_0;
ee890fe2
SS		 16878 static int label = 0;
16879
df56a27f 16880 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
772c5265 16881 symb = (*targetm.strip_name_encoding) (symb);
df56a27f 16882
ee890fe2 16883
ee890fe2
SS		 16884 length = strlen (symb);
16885 symbol_name = alloca (length + 32);
16886 GEN_SYMBOL_NAME_FOR_SYMBOL (symbol_name, symb, length);
16887
16888 lazy_ptr_name = alloca (length + 32);
16889 GEN_LAZY_PTR_NAME_FOR_SYMBOL (lazy_ptr_name, symb, length);
16890
ee890fe2 16891 if (flag_pic == 2)
d3c300d2 16892 machopic_picsymbol_stub1_section ();
ee890fe2 16893 else
d3c300d2 16894 machopic_symbol_stub1_section ();
ee890fe2
SS		 16895
16896 if (flag_pic == 2)
16897 {
d974312d
DJ		 16898 fprintf (file, "\t.align 5\n");
16899
16900 fprintf (file, "%s:\n", stub);
16901 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
16902
876455fa 16903 label++;
89da1f32 16904 local_label_0 = alloca (sizeof ("\"L00000000000$spb\""));
876455fa 16905 sprintf (local_label_0, "\"L%011d$spb\"", label);
f676971a 16906
ee890fe2
SS		 16907 fprintf (file, "\tmflr r0\n");
16908 fprintf (file, "\tbcl 20,31,%s\n", local_label_0);
16909 fprintf (file, "%s:\n\tmflr r11\n", local_label_0);
16910 fprintf (file, "\taddis r11,r11,ha16(%s-%s)\n",
16911 lazy_ptr_name, local_label_0);
16912 fprintf (file, "\tmtlr r0\n");
3d0e2d58
SS		 16913 fprintf (file, "\t%s r12,lo16(%s-%s)(r11)\n",
16914 (TARGET_64BIT ? "ldu" : "lwzu"),
ee890fe2
SS		 16915 lazy_ptr_name, local_label_0);
16916 fprintf (file, "\tmtctr r12\n");
ee890fe2
SS		 16917 fprintf (file, "\tbctr\n");
16918 }
16919 else
d974312d
DJ		 16920 {
16921 fprintf (file, "\t.align 4\n");
16922
16923 fprintf (file, "%s:\n", stub);
16924 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
16925
16926 fprintf (file, "\tlis r11,ha16(%s)\n", lazy_ptr_name);
d9e4e4f5
SS		 16927 fprintf (file, "\t%s r12,lo16(%s)(r11)\n",
16928 (TARGET_64BIT ? "ldu" : "lwzu"),
16929 lazy_ptr_name);
d974312d
DJ		 16930 fprintf (file, "\tmtctr r12\n");
16931 fprintf (file, "\tbctr\n");
16932 }
f676971a 16933
ee890fe2
SS		 16934 machopic_lazy_symbol_ptr_section ();
16935 fprintf (file, "%s:\n", lazy_ptr_name);
16936 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
49bd1d27
SS		 16937 fprintf (file, "%sdyld_stub_binding_helper\n",
16938 (TARGET_64BIT ? DOUBLE_INT_ASM_OP : "\t.long\t"));
ee890fe2
SS		 16939}
16940
16941/* Legitimize PIC addresses. If the address is already
16942 position-independent, we return ORIG. Newly generated
16943 position-independent addresses go into a reg. This is REG if non
16944 zero, otherwise we allocate register(s) as necessary. */
16945
9390387d 16946#define SMALL_INT(X) ((unsigned) (INTVAL (X) + 0x8000) < 0x10000)
ee890fe2
SS		 16947
16948rtx
f676971a 16949rs6000_machopic_legitimize_pic_address (rtx orig, enum machine_mode mode,
a2369ed3 16950 rtx reg)
ee890fe2
SS		 16951{
16952 rtx base, offset;
16953
16954 if (reg == NULL && ! reload_in_progress && ! reload_completed)
16955 reg = gen_reg_rtx (Pmode);
16956
16957 if (GET_CODE (orig) == CONST)
16958 {
37409796
NS		 16959 rtx reg_temp;
16960
ee890fe2
SS		 16961 if (GET_CODE (XEXP (orig, 0)) == PLUS
16962 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
16963 return orig;
16964
37409796
NS		 16965 gcc_assert (GET_CODE (XEXP (orig, 0)) == PLUS);
16966
16967 /* Use a different reg for the intermediate value, as
16968 it will be marked UNCHANGING. */
16969 reg_temp = no_new_pseudos ? reg : gen_reg_rtx (Pmode);
16970 base = rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 0),
16971 Pmode, reg_temp);
16972 offset =
16973 rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 1),
16974 Pmode, reg);
16975
ee890fe2
SS		 16976 if (GET_CODE (offset) == CONST_INT)
16977 {
16978 if (SMALL_INT (offset))
ed8908e7 16979 return plus_constant (base, INTVAL (offset));
ee890fe2
SS		 16980 else if (! reload_in_progress && ! reload_completed)
16981 offset = force_reg (Pmode, offset);
16982 else
c859cda6
DJ		 16983 {
16984 rtx mem = force_const_mem (Pmode, orig);
16985 return machopic_legitimize_pic_address (mem, Pmode, reg);
16986 }
ee890fe2 16987 }
f1c25d3b 16988 return gen_rtx_PLUS (Pmode, base, offset);
ee890fe2
SS		 16989 }
16990
16991 /* Fall back on generic machopic code. */
16992 return machopic_legitimize_pic_address (orig, mode, reg);
16993}
16994
16995/* This is just a placeholder to make linking work without having to
16996 add this to the generic Darwin EXTRA_SECTIONS. If -mcall-aix is
16997 ever needed for Darwin (not too likely!) this would have to get a
16998 real definition. */
16999
17000void
863d938c 17001toc_section (void)
ee890fe2
SS		 17002{
17003}
17004
c4e18b1c
GK		 17005/* Output a .machine directive for the Darwin assembler, and call
17006 the generic start_file routine. */
17007
17008static void
17009rs6000_darwin_file_start (void)
17010{
94ff898d 17011 static const struct
c4e18b1c
GK		 17012 {
17013 const char *arg;
17014 const char *name;
17015 int if_set;
17016 } mapping[] = {
55dbfb48 17017 { "ppc64", "ppc64", MASK_64BIT },
c4e18b1c
GK		 17018 { "970", "ppc970", MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64 },
17019 { "power4", "ppc970", 0 },
17020 { "G5", "ppc970", 0 },
17021 { "7450", "ppc7450", 0 },
17022 { "7400", "ppc7400", MASK_ALTIVEC },
17023 { "G4", "ppc7400", 0 },
17024 { "750", "ppc750", 0 },
17025 { "740", "ppc750", 0 },
17026 { "G3", "ppc750", 0 },
17027 { "604e", "ppc604e", 0 },
17028 { "604", "ppc604", 0 },
17029 { "603e", "ppc603", 0 },
17030 { "603", "ppc603", 0 },
17031 { "601", "ppc601", 0 },
17032 { NULL, "ppc", 0 } };
17033 const char *cpu_id = "";
17034 size_t i;
94ff898d 17035
9390387d 17036 rs6000_file_start ();
c4e18b1c
GK		 17037
17038 /* Determine the argument to -mcpu=. Default to G3 if not specified. */
17039 for (i = 0; i < ARRAY_SIZE (rs6000_select); i++)
17040 if (rs6000_select[i].set_arch_p && rs6000_select[i].string
17041 && rs6000_select[i].string[0] != '\0')
17042 cpu_id = rs6000_select[i].string;
17043
17044 /* Look through the mapping array. Pick the first name that either
17045 matches the argument, has a bit set in IF_SET that is also set
17046 in the target flags, or has a NULL name. */
17047
17048 i = 0;
17049 while (mapping[i].arg != NULL
17050 && strcmp (mapping[i].arg, cpu_id) != 0
17051 && (mapping[i].if_set & target_flags) == 0)
17052 i++;
17053
17054 fprintf (asm_out_file, "\t.machine %s\n", mapping[i].name);
17055}
17056
ee890fe2 17057#endif /* TARGET_MACHO */
7c262518
RH		 17058
17059#if TARGET_ELF
17060static unsigned int
a2369ed3 17061rs6000_elf_section_type_flags (tree decl, const char *name, int reloc)
7c262518 17062{
1ff8f81a
AM		 17063 return default_section_type_flags_1 (decl, name, reloc,
17064 flag_pic || DEFAULT_ABI == ABI_AIX);
7c262518 17065}
d9f6800d
RH		 17066
17067/* Record an element in the table of global constructors. SYMBOL is
17068 a SYMBOL_REF of the function to be called; PRIORITY is a number
17069 between 0 and MAX_INIT_PRIORITY.
17070
17071 This differs from default_named_section_asm_out_constructor in
17072 that we have special handling for -mrelocatable. */
17073
17074static void
a2369ed3 17075rs6000_elf_asm_out_constructor (rtx symbol, int priority)
d9f6800d
RH		 17076{
17077 const char *section = ".ctors";
17078 char buf[16];
17079
17080 if (priority != DEFAULT_INIT_PRIORITY)
17081 {
17082 sprintf (buf, ".ctors.%.5u",
c4ad648e
AM		 17083 /* Invert the numbering so the linker puts us in the proper
17084 order; constructors are run from right to left, and the
17085 linker sorts in increasing order. */
17086 MAX_INIT_PRIORITY - priority);
d9f6800d
RH		 17087 section = buf;
17088 }
17089
715bdd29
RH		 17090 named_section_flags (section, SECTION_WRITE);
17091 assemble_align (POINTER_SIZE);
d9f6800d
RH		 17092
17093 if (TARGET_RELOCATABLE)
17094 {
17095 fputs ("\t.long (", asm_out_file);
17096 output_addr_const (asm_out_file, symbol);
17097 fputs (")@fixup\n", asm_out_file);
17098 }
17099 else
c8af3574 17100 assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1);
d9f6800d
RH		 17101}
17102
17103static void
a2369ed3 17104rs6000_elf_asm_out_destructor (rtx symbol, int priority)
d9f6800d
RH		 17105{
17106 const char *section = ".dtors";
17107 char buf[16];
17108
17109 if (priority != DEFAULT_INIT_PRIORITY)
17110 {
17111 sprintf (buf, ".dtors.%.5u",
c4ad648e
AM		 17112 /* Invert the numbering so the linker puts us in the proper
17113 order; constructors are run from right to left, and the
17114 linker sorts in increasing order. */
17115 MAX_INIT_PRIORITY - priority);
d9f6800d
RH		 17116 section = buf;
17117 }
17118
715bdd29
RH		 17119 named_section_flags (section, SECTION_WRITE);
17120 assemble_align (POINTER_SIZE);
d9f6800d
RH		 17121
17122 if (TARGET_RELOCATABLE)
17123 {
17124 fputs ("\t.long (", asm_out_file);
17125 output_addr_const (asm_out_file, symbol);
17126 fputs (")@fixup\n", asm_out_file);
17127 }
17128 else
c8af3574 17129 assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1);
d9f6800d 17130}
9739c90c
JJ		 17131
17132void
a2369ed3 17133rs6000_elf_declare_function_name (FILE *file, const char *name, tree decl)
9739c90c
JJ		 17134{
17135 if (TARGET_64BIT)
17136 {
17137 fputs ("\t.section\t\".opd\",\"aw\"\n\t.align 3\n", file);
17138 ASM_OUTPUT_LABEL (file, name);
17139 fputs (DOUBLE_INT_ASM_OP, file);
85b776df
AM		 17140 rs6000_output_function_entry (file, name);
17141 fputs (",.TOC.@tocbase,0\n\t.previous\n", file);
17142 if (DOT_SYMBOLS)
9739c90c 17143 {
85b776df 17144 fputs ("\t.size\t", file);
9739c90c 17145 assemble_name (file, name);
85b776df
AM		 17146 fputs (",24\n\t.type\t.", file);
17147 assemble_name (file, name);
17148 fputs (",@function\n", file);
17149 if (TREE_PUBLIC (decl) && ! DECL_WEAK (decl))
17150 {
17151 fputs ("\t.globl\t.", file);
17152 assemble_name (file, name);
17153 putc ('\n', file);
17154 }
9739c90c 17155 }
85b776df
AM		 17156 else
17157 ASM_OUTPUT_TYPE_DIRECTIVE (file, name, "function");
9739c90c 17158 ASM_DECLARE_RESULT (file, DECL_RESULT (decl));
85b776df
AM		 17159 rs6000_output_function_entry (file, name);
17160 fputs (":\n", file);
9739c90c
JJ		 17161 return;
17162 }
17163
17164 if (TARGET_RELOCATABLE
17165 && (get_pool_size () != 0 || current_function_profile)
3c9eb5f4 17166 && uses_TOC ())
9739c90c
JJ		 17167 {
17168 char buf[256];
17169
17170 (*targetm.asm_out.internal_label) (file, "LCL", rs6000_pic_labelno);
17171
17172 ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1);
17173 fprintf (file, "\t.long ");
17174 assemble_name (file, buf);
17175 putc ('-', file);
17176 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
17177 assemble_name (file, buf);
17178 putc ('\n', file);
17179 }
17180
17181 ASM_OUTPUT_TYPE_DIRECTIVE (file, name, "function");
17182 ASM_DECLARE_RESULT (file, DECL_RESULT (decl));
17183
17184 if (DEFAULT_ABI == ABI_AIX)
17185 {
17186 const char *desc_name, *orig_name;
17187
17188 orig_name = (*targetm.strip_name_encoding) (name);
17189 desc_name = orig_name;
17190 while (*desc_name == '.')
17191 desc_name++;
17192
17193 if (TREE_PUBLIC (decl))
17194 fprintf (file, "\t.globl %s\n", desc_name);
17195
17196 fprintf (file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
17197 fprintf (file, "%s:\n", desc_name);
17198 fprintf (file, "\t.long %s\n", orig_name);
17199 fputs ("\t.long _GLOBAL_OFFSET_TABLE_\n", file);
17200 if (DEFAULT_ABI == ABI_AIX)
17201 fputs ("\t.long 0\n", file);
17202 fprintf (file, "\t.previous\n");
17203 }
17204 ASM_OUTPUT_LABEL (file, name);
17205}
1334b570
AM		 17206
17207static void
17208rs6000_elf_end_indicate_exec_stack (void)
17209{
17210 if (TARGET_32BIT)
17211 file_end_indicate_exec_stack ();
17212}
7c262518
RH		 17213#endif
17214
cbaaba19 17215#if TARGET_XCOFF
7c262518 17216static void
a2369ed3 17217rs6000_xcoff_asm_globalize_label (FILE *stream, const char *name)
b275d088
DE		 17218{
17219 fputs (GLOBAL_ASM_OP, stream);
17220 RS6000_OUTPUT_BASENAME (stream, name);
17221 putc ('\n', stream);
17222}
17223
17224static void
c18a5b6c
MM		 17225rs6000_xcoff_asm_named_section (const char *name, unsigned int flags,
17226 tree decl ATTRIBUTE_UNUSED)
7c262518 17227{
0e5dbd9b
DE		 17228 int smclass;
17229 static const char * const suffix[3] = { "PR", "RO", "RW" };
17230
17231 if (flags & SECTION_CODE)
17232 smclass = 0;
17233 else if (flags & SECTION_WRITE)
17234 smclass = 2;
17235 else
17236 smclass = 1;
17237
5b5198f7 17238 fprintf (asm_out_file, "\t.csect %s%s[%s],%u\n",
0e5dbd9b 17239 (flags & SECTION_CODE) ? "." : "",
5b5198f7 17240 name, suffix[smclass], flags & SECTION_ENTSIZE);
7c262518 17241}
ae46c4e0
RH		 17242
17243static void
f676971a 17244rs6000_xcoff_select_section (tree decl, int reloc,
c4ad648e 17245 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
ae46c4e0 17246{
5add3202 17247 if (decl_readonly_section_1 (decl, reloc, 1))
ae46c4e0 17248 {
0e5dbd9b 17249 if (TREE_PUBLIC (decl))
c4ad648e 17250 read_only_data_section ();
ae46c4e0 17251 else
c4ad648e 17252 read_only_private_data_section ();
ae46c4e0
RH		 17253 }
17254 else
17255 {
0e5dbd9b 17256 if (TREE_PUBLIC (decl))
c4ad648e 17257 data_section ();
ae46c4e0 17258 else
c4ad648e 17259 private_data_section ();
ae46c4e0
RH		 17260 }
17261}
17262
17263static void
a2369ed3 17264rs6000_xcoff_unique_section (tree decl, int reloc ATTRIBUTE_UNUSED)
ae46c4e0
RH		 17265{
17266 const char *name;
ae46c4e0 17267
5b5198f7
DE		 17268 /* Use select_section for private and uninitialized data. */
17269 if (!TREE_PUBLIC (decl)
17270 || DECL_COMMON (decl)
0e5dbd9b
DE		 17271 || DECL_INITIAL (decl) == NULL_TREE
17272 || DECL_INITIAL (decl) == error_mark_node
17273 || (flag_zero_initialized_in_bss
17274 && initializer_zerop (DECL_INITIAL (decl))))
17275 return;
17276
17277 name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
17278 name = (*targetm.strip_name_encoding) (name);
17279 DECL_SECTION_NAME (decl) = build_string (strlen (name), name);
ae46c4e0 17280}
b64a1b53 17281
fb49053f
RH		 17282/* Select section for constant in constant pool.
17283
17284 On RS/6000, all constants are in the private read-only data area.
17285 However, if this is being placed in the TOC it must be output as a
17286 toc entry. */
17287
b64a1b53 17288static void
f676971a 17289rs6000_xcoff_select_rtx_section (enum machine_mode mode, rtx x,
c4ad648e 17290 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
b64a1b53
RH		 17291{
17292 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode))
17293 toc_section ();
17294 else
17295 read_only_private_data_section ();
17296}
772c5265
RH		 17297
17298/* Remove any trailing [DS] or the like from the symbol name. */
17299
17300static const char *
a2369ed3 17301rs6000_xcoff_strip_name_encoding (const char *name)
772c5265
RH		 17302{
17303 size_t len;
17304 if (*name == '*')
17305 name++;
17306 len = strlen (name);
17307 if (name[len - 1] == ']')
17308 return ggc_alloc_string (name, len - 4);
17309 else
17310 return name;
17311}
17312
5add3202
DE		 17313/* Section attributes. AIX is always PIC. */
17314
17315static unsigned int
a2369ed3 17316rs6000_xcoff_section_type_flags (tree decl, const char *name, int reloc)
5add3202 17317{
5b5198f7
DE		 17318 unsigned int align;
17319 unsigned int flags = default_section_type_flags_1 (decl, name, reloc, 1);
17320
17321 /* Align to at least UNIT size. */
17322 if (flags & SECTION_CODE)
17323 align = MIN_UNITS_PER_WORD;
17324 else
17325 /* Increase alignment of large objects if not already stricter. */
17326 align = MAX ((DECL_ALIGN (decl) / BITS_PER_UNIT),
17327 int_size_in_bytes (TREE_TYPE (decl)) > MIN_UNITS_PER_WORD
17328 ? UNITS_PER_FP_WORD : MIN_UNITS_PER_WORD);
17329
17330 return flags | (exact_log2 (align) & SECTION_ENTSIZE);
5add3202 17331}
a5fe455b 17332
1bc7c5b6
ZW		 17333/* Output at beginning of assembler file.
17334
17335 Initialize the section names for the RS/6000 at this point.
17336
17337 Specify filename, including full path, to assembler.
17338
17339 We want to go into the TOC section so at least one .toc will be emitted.
17340 Also, in order to output proper .bs/.es pairs, we need at least one static
17341 [RW] section emitted.
17342
17343 Finally, declare mcount when profiling to make the assembler happy. */
17344
17345static void
863d938c 17346rs6000_xcoff_file_start (void)
1bc7c5b6
ZW		 17347{
17348 rs6000_gen_section_name (&xcoff_bss_section_name,
17349 main_input_filename, ".bss_");
17350 rs6000_gen_section_name (&xcoff_private_data_section_name,
17351 main_input_filename, ".rw_");
17352 rs6000_gen_section_name (&xcoff_read_only_section_name,
17353 main_input_filename, ".ro_");
17354
17355 fputs ("\t.file\t", asm_out_file);
17356 output_quoted_string (asm_out_file, main_input_filename);
17357 fputc ('\n', asm_out_file);
1bc7c5b6
ZW		 17358 if (write_symbols != NO_DEBUG)
17359 private_data_section ();
17360 text_section ();
17361 if (profile_flag)
17362 fprintf (asm_out_file, "\t.extern %s\n", RS6000_MCOUNT);
17363 rs6000_file_start ();
17364}
17365
a5fe455b
ZW		 17366/* Output at end of assembler file.
17367 On the RS/6000, referencing data should automatically pull in text. */
17368
17369static void
863d938c 17370rs6000_xcoff_file_end (void)
a5fe455b
ZW		 17371{
17372 text_section ();
17373 fputs ("_section_.text:\n", asm_out_file);
17374 data_section ();
17375 fputs (TARGET_32BIT
17376 ? "\t.long _section_.text\n" : "\t.llong _section_.text\n",
17377 asm_out_file);
17378}
f1384257 17379#endif /* TARGET_XCOFF */
0e5dbd9b 17380
f1384257
AM		 17381#if TARGET_MACHO
17382/* Cross-module name binding. Darwin does not support overriding
7f3d8013 17383 functions at dynamic-link time. */
0e5dbd9b 17384
2bcc50d0 17385static bool
a2369ed3 17386rs6000_binds_local_p (tree decl)
0e5dbd9b 17387{
f1384257 17388 return default_binds_local_p_1 (decl, 0);
0e5dbd9b 17389}
f1384257 17390#endif
34bb030a 17391
3c50106f
RH		 17392/* Compute a (partial) cost for rtx X. Return true if the complete
17393 cost has been computed, and false if subexpressions should be
17394 scanned. In either case, *TOTAL contains the cost result. */
17395
17396static bool
1494c534 17397rs6000_rtx_costs (rtx x, int code, int outer_code, int *total)
3c50106f 17398{
f0517163
RS		 17399 enum machine_mode mode = GET_MODE (x);
17400
3c50106f
RH		 17401 switch (code)
17402 {
30a555d9 17403 /* On the RS/6000, if it is valid in the insn, it is free. */
3c50106f 17404 case CONST_INT:
066cd967
DE		 17405 if (((outer_code == SET
17406 || outer_code == PLUS
17407 || outer_code == MINUS)
17408 && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'I')
17409 || CONST_OK_FOR_LETTER_P (INTVAL (x), 'L')))
066cd967
DE		 17410 || (outer_code == AND
17411 && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'K')
22e54023
DE		 17412 || (CONST_OK_FOR_LETTER_P (INTVAL (x),
17413 mode == SImode ? 'L' : 'J'))
d5861a7a 17414 || mask_operand (x, VOIDmode)))
22e54023
DE		 17415 || ((outer_code == IOR || outer_code == XOR)
17416 && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'K')
17417 || (CONST_OK_FOR_LETTER_P (INTVAL (x),
17418 mode == SImode ? 'L' : 'J'))))
066cd967
DE		 17419 || outer_code == ASHIFT
17420 || outer_code == ASHIFTRT
17421 || outer_code == LSHIFTRT
17422 || outer_code == ROTATE
17423 || outer_code == ROTATERT
d5861a7a 17424 || outer_code == ZERO_EXTRACT
066cd967
DE		 17425 || (outer_code == MULT
17426 && CONST_OK_FOR_LETTER_P (INTVAL (x), 'I'))
22e54023
DE		 17427 || ((outer_code == DIV || outer_code == UDIV
17428 || outer_code == MOD || outer_code == UMOD)
17429 && exact_log2 (INTVAL (x)) >= 0)
066cd967
DE		 17430 || (outer_code == COMPARE
17431 && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'I')
22e54023
DE		 17432 || CONST_OK_FOR_LETTER_P (INTVAL (x), 'K')))
17433 || (outer_code == EQ
17434 && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'I')
17435 || CONST_OK_FOR_LETTER_P (INTVAL (x), 'K')
17436 || (CONST_OK_FOR_LETTER_P (INTVAL (x),
17437 mode == SImode ? 'L' : 'J'))))
17438 || (outer_code == GTU
17439 && CONST_OK_FOR_LETTER_P (INTVAL (x), 'I'))
17440 || (outer_code == LTU
17441 && CONST_OK_FOR_LETTER_P (INTVAL (x), 'P')))
066cd967
DE		 17442 {
17443 *total = 0;
17444 return true;
17445 }
17446 else if ((outer_code == PLUS
17447 && reg_or_add_cint64_operand (x, VOIDmode))
17448 || (outer_code == MINUS
17449 && reg_or_sub_cint64_operand (x, VOIDmode))
17450 || ((outer_code == SET
17451 || outer_code == IOR
17452 || outer_code == XOR)
17453 && (INTVAL (x)
17454 & ~ (unsigned HOST_WIDE_INT) 0xffffffff) == 0))
17455 {
17456 *total = COSTS_N_INSNS (1);
17457 return true;
17458 }
17459 /* FALLTHRU */
17460
17461 case CONST_DOUBLE:
17462 if (mode == DImode
17463 && ((outer_code == AND
17464 && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'K')
17465 || CONST_OK_FOR_LETTER_P (INTVAL (x), 'L')
d5861a7a 17466 || mask64_operand (x, DImode)))
066cd967
DE		 17467 || ((outer_code == IOR || outer_code == XOR)
17468 && CONST_DOUBLE_HIGH (x) == 0
17469 && (CONST_DOUBLE_LOW (x)
17470 & ~ (unsigned HOST_WIDE_INT) 0xffff) == 0)))
17471 {
17472 *total = 0;
17473 return true;
17474 }
17475 else if (mode == DImode
17476 && (outer_code == SET
17477 || outer_code == IOR
17478 || outer_code == XOR)
17479 && CONST_DOUBLE_HIGH (x) == 0)
17480 {
17481 *total = COSTS_N_INSNS (1);
17482 return true;
17483 }
17484 /* FALLTHRU */
17485
3c50106f 17486 case CONST:
066cd967 17487 case HIGH:
3c50106f 17488 case SYMBOL_REF:
066cd967
DE		 17489 case MEM:
17490 /* When optimizing for size, MEM should be slightly more expensive
17491 than generating address, e.g., (plus (reg) (const)).
c112cf2b 17492 L1 cache latency is about two instructions. */
066cd967 17493 *total = optimize_size ? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (2);
3c50106f
RH		 17494 return true;
17495
30a555d9
DE		 17496 case LABEL_REF:
17497 *total = 0;
17498 return true;
17499
3c50106f 17500 case PLUS:
f0517163 17501 if (mode == DFmode)
066cd967
DE		 17502 {
17503 if (GET_CODE (XEXP (x, 0)) == MULT)
17504 {
17505 /* FNMA accounted in outer NEG. */
17506 if (outer_code == NEG)
17507 *total = rs6000_cost->dmul - rs6000_cost->fp;
17508 else
17509 *total = rs6000_cost->dmul;
17510 }
17511 else
17512 *total = rs6000_cost->fp;
17513 }
f0517163 17514 else if (mode == SFmode)
066cd967
DE		 17515 {
17516 /* FNMA accounted in outer NEG. */
17517 if (outer_code == NEG && GET_CODE (XEXP (x, 0)) == MULT)
17518 *total = 0;
17519 else
17520 *total = rs6000_cost->fp;
17521 }
938bf747
RS		 17522 else if (GET_CODE (XEXP (x, 0)) == MULT)
17523 {
17524 /* The rs6000 doesn't have shift-and-add instructions. */
17525 rs6000_rtx_costs (XEXP (x, 0), MULT, PLUS, total);
17526 *total += COSTS_N_INSNS (1);
17527 }
f0517163 17528 else
066cd967
DE		 17529 *total = COSTS_N_INSNS (1);
17530 return false;
3c50106f 17531
52190329 17532 case MINUS:
f0517163 17533 if (mode == DFmode)
066cd967
DE		 17534 {
17535 if (GET_CODE (XEXP (x, 0)) == MULT)
17536 {
17537 /* FNMA accounted in outer NEG. */
17538 if (outer_code == NEG)
17539 *total = 0;
17540 else
17541 *total = rs6000_cost->dmul;
17542 }
17543 else
17544 *total = rs6000_cost->fp;
17545 }
f0517163 17546 else if (mode == SFmode)
066cd967
DE		 17547 {
17548 /* FNMA accounted in outer NEG. */
17549 if (outer_code == NEG && GET_CODE (XEXP (x, 0)) == MULT)
17550 *total = 0;
17551 else
17552 *total = rs6000_cost->fp;
17553 }
938bf747
RS		 17554 else if (GET_CODE (XEXP (x, 0)) == MULT)
17555 {
17556 /* The rs6000 doesn't have shift-and-sub instructions. */
17557 rs6000_rtx_costs (XEXP (x, 0), MULT, MINUS, total);
17558 *total += COSTS_N_INSNS (1);
17559 }
f0517163 17560 else
c4ad648e 17561 *total = COSTS_N_INSNS (1);
066cd967 17562 return false;
3c50106f
RH		 17563
17564 case MULT:
c9dbf840
DE		 17565 if (GET_CODE (XEXP (x, 1)) == CONST_INT
17566 && CONST_OK_FOR_LETTER_P (INTVAL (XEXP (x, 1)), 'I'))
3c50106f 17567 {
8b897cfa
RS		 17568 if (INTVAL (XEXP (x, 1)) >= -256
17569 && INTVAL (XEXP (x, 1)) <= 255)
06a67bdd 17570 *total = rs6000_cost->mulsi_const9;
8b897cfa 17571 else
06a67bdd 17572 *total = rs6000_cost->mulsi_const;
3c50106f 17573 }
066cd967
DE		 17574 /* FMA accounted in outer PLUS/MINUS. */
17575 else if ((mode == DFmode || mode == SFmode)
17576 && (outer_code == PLUS || outer_code == MINUS))
17577 *total = 0;
f0517163 17578 else if (mode == DFmode)
06a67bdd 17579 *total = rs6000_cost->dmul;
f0517163 17580 else if (mode == SFmode)
06a67bdd 17581 *total = rs6000_cost->fp;
f0517163 17582 else if (mode == DImode)
06a67bdd 17583 *total = rs6000_cost->muldi;
8b897cfa 17584 else
06a67bdd 17585 *total = rs6000_cost->mulsi;
066cd967 17586 return false;
3c50106f
RH		 17587
17588 case DIV:
17589 case MOD:
f0517163
RS		 17590 if (FLOAT_MODE_P (mode))
17591 {
06a67bdd
RS		 17592 *total = mode == DFmode ? rs6000_cost->ddiv
17593 : rs6000_cost->sdiv;
066cd967 17594 return false;
f0517163 17595 }
5efb1046 17596 /* FALLTHRU */
3c50106f
RH		 17597
17598 case UDIV:
17599 case UMOD:
627b6fe2
DJ		 17600 if (GET_CODE (XEXP (x, 1)) == CONST_INT
17601 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0)
17602 {
17603 if (code == DIV || code == MOD)
17604 /* Shift, addze */
17605 *total = COSTS_N_INSNS (2);
17606 else
17607 /* Shift */
17608 *total = COSTS_N_INSNS (1);
17609 }
c4ad648e 17610 else
627b6fe2
DJ		 17611 {
17612 if (GET_MODE (XEXP (x, 1)) == DImode)
17613 *total = rs6000_cost->divdi;
17614 else
17615 *total = rs6000_cost->divsi;
17616 }
17617 /* Add in shift and subtract for MOD. */
17618 if (code == MOD || code == UMOD)
17619 *total += COSTS_N_INSNS (2);
066cd967 17620 return false;
3c50106f
RH		 17621
17622 case FFS:
17623 *total = COSTS_N_INSNS (4);
066cd967 17624 return false;
3c50106f 17625
06a67bdd 17626 case NOT:
066cd967
DE		 17627 if (outer_code == AND || outer_code == IOR || outer_code == XOR)
17628 {
17629 *total = 0;
17630 return false;
17631 }
17632 /* FALLTHRU */
17633
17634 case AND:
17635 case IOR:
17636 case XOR:
d5861a7a
DE		 17637 case ZERO_EXTRACT:
17638 *total = COSTS_N_INSNS (1);
17639 return false;
17640
066cd967
DE		 17641 case ASHIFT:
17642 case ASHIFTRT:
17643 case LSHIFTRT:
17644 case ROTATE:
17645 case ROTATERT:
d5861a7a 17646 /* Handle mul_highpart. */
066cd967
DE		 17647 if (outer_code == TRUNCATE
17648 && GET_CODE (XEXP (x, 0)) == MULT)
17649 {
17650 if (mode == DImode)
17651 *total = rs6000_cost->muldi;
17652 else
17653 *total = rs6000_cost->mulsi;
17654 return true;
17655 }
d5861a7a
DE		 17656 else if (outer_code == AND)
17657 *total = 0;
17658 else
17659 *total = COSTS_N_INSNS (1);
17660 return false;
17661
17662 case SIGN_EXTEND:
17663 case ZERO_EXTEND:
17664 if (GET_CODE (XEXP (x, 0)) == MEM)
17665 *total = 0;
17666 else
17667 *total = COSTS_N_INSNS (1);
066cd967 17668 return false;
06a67bdd 17669
066cd967
DE		 17670 case COMPARE:
17671 case NEG:
17672 case ABS:
17673 if (!FLOAT_MODE_P (mode))
17674 {
17675 *total = COSTS_N_INSNS (1);
17676 return false;
17677 }
17678 /* FALLTHRU */
17679
17680 case FLOAT:
17681 case UNSIGNED_FLOAT:
17682 case FIX:
17683 case UNSIGNED_FIX:
17684 case FLOAT_EXTEND:
06a67bdd
RS		 17685 case FLOAT_TRUNCATE:
17686 *total = rs6000_cost->fp;
066cd967 17687 return false;
06a67bdd
RS		 17688
17689 case UNSPEC:
17690 switch (XINT (x, 1))
17691 {
17692 case UNSPEC_FRSP:
17693 *total = rs6000_cost->fp;
17694 return true;
17695
17696 default:
17697 break;
17698 }
17699 break;
17700
17701 case CALL:
17702 case IF_THEN_ELSE:
17703 if (optimize_size)
17704 {
17705 *total = COSTS_N_INSNS (1);
17706 return true;
17707 }
066cd967
DE		 17708 else if (FLOAT_MODE_P (mode)
17709 && TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS)
17710 {
17711 *total = rs6000_cost->fp;
17712 return false;
17713 }
06a67bdd
RS		 17714 break;
17715
c0600ecd
DE		 17716 case EQ:
17717 case GTU:
17718 case LTU:
22e54023
DE		 17719 /* Carry bit requires mode == Pmode.
17720 NEG or PLUS already counted so only add one. */
17721 if (mode == Pmode
17722 && (outer_code == NEG || outer_code == PLUS))
c0600ecd 17723 {
22e54023
DE		 17724 *total = COSTS_N_INSNS (1);
17725 return true;
17726 }
17727 if (outer_code == SET)
17728 {
17729 if (XEXP (x, 1) == const0_rtx)
c0600ecd 17730 {
22e54023 17731 *total = COSTS_N_INSNS (2);
c0600ecd 17732 return true;
c0600ecd 17733 }
22e54023
DE		 17734 else if (mode == Pmode)
17735 {
17736 *total = COSTS_N_INSNS (3);
17737 return false;
17738 }
17739 }
17740 /* FALLTHRU */
17741
17742 case GT:
17743 case LT:
17744 case UNORDERED:
17745 if (outer_code == SET && (XEXP (x, 1) == const0_rtx))
17746 {
17747 *total = COSTS_N_INSNS (2);
17748 return true;
c0600ecd 17749 }
22e54023
DE		 17750 /* CC COMPARE. */
17751 if (outer_code == COMPARE)
17752 {
17753 *total = 0;
17754 return true;
17755 }
17756 break;
c0600ecd 17757
3c50106f 17758 default:
06a67bdd 17759 break;
3c50106f 17760 }
06a67bdd
RS		 17761
17762 return false;
3c50106f
RH		 17763}
17764
34bb030a
DE		 17765/* A C expression returning the cost of moving data from a register of class
17766 CLASS1 to one of CLASS2. */
17767
17768int
f676971a 17769rs6000_register_move_cost (enum machine_mode mode,
a2369ed3 17770 enum reg_class from, enum reg_class to)
34bb030a
DE		 17771{
17772 /* Moves from/to GENERAL_REGS. */
17773 if (reg_classes_intersect_p (to, GENERAL_REGS)
17774 || reg_classes_intersect_p (from, GENERAL_REGS))
17775 {
17776 if (! reg_classes_intersect_p (to, GENERAL_REGS))
17777 from = to;
17778
17779 if (from == FLOAT_REGS || from == ALTIVEC_REGS)
17780 return (rs6000_memory_move_cost (mode, from, 0)
17781 + rs6000_memory_move_cost (mode, GENERAL_REGS, 0));
17782
c4ad648e
AM		 17783 /* It's more expensive to move CR_REGS than CR0_REGS because of the
17784 shift. */
34bb030a
DE		 17785 else if (from == CR_REGS)
17786 return 4;
17787
17788 else
c4ad648e 17789 /* A move will cost one instruction per GPR moved. */
34bb030a
DE		 17790 return 2 * HARD_REGNO_NREGS (0, mode);
17791 }
17792
c4ad648e 17793 /* Moving between two similar registers is just one instruction. */
34bb030a
DE		 17794 else if (reg_classes_intersect_p (to, from))
17795 return mode == TFmode ? 4 : 2;
17796
c4ad648e 17797 /* Everything else has to go through GENERAL_REGS. */
34bb030a 17798 else
f676971a 17799 return (rs6000_register_move_cost (mode, GENERAL_REGS, to)
34bb030a
DE		 17800 + rs6000_register_move_cost (mode, from, GENERAL_REGS));
17801}
17802
17803/* A C expressions returning the cost of moving data of MODE from a register to
17804 or from memory. */
17805
17806int
f676971a 17807rs6000_memory_move_cost (enum machine_mode mode, enum reg_class class,
a2369ed3 17808 int in ATTRIBUTE_UNUSED)
34bb030a
DE		 17809{
17810 if (reg_classes_intersect_p (class, GENERAL_REGS))
17811 return 4 * HARD_REGNO_NREGS (0, mode);
17812 else if (reg_classes_intersect_p (class, FLOAT_REGS))
17813 return 4 * HARD_REGNO_NREGS (32, mode);
17814 else if (reg_classes_intersect_p (class, ALTIVEC_REGS))
17815 return 4 * HARD_REGNO_NREGS (FIRST_ALTIVEC_REGNO, mode);
17816 else
17817 return 4 + rs6000_register_move_cost (mode, class, GENERAL_REGS);
17818}
17819
ded9bf77
AH		 17820/* Return an RTX representing where to find the function value of a
17821 function returning MODE. */
17822static rtx
17823rs6000_complex_function_value (enum machine_mode mode)
17824{
17825 unsigned int regno;
17826 rtx r1, r2;
17827 enum machine_mode inner = GET_MODE_INNER (mode);
fb7e4164 17828 unsigned int inner_bytes = GET_MODE_SIZE (inner);
ded9bf77 17829
18f63bfa
AH		 17830 if (FLOAT_MODE_P (mode) && TARGET_HARD_FLOAT && TARGET_FPRS)
17831 regno = FP_ARG_RETURN;
354ed18f
AH		 17832 else
17833 {
18f63bfa 17834 regno = GP_ARG_RETURN;
ded9bf77 17835
18f63bfa
AH		 17836 /* 32-bit is OK since it'll go in r3/r4. */
17837 if (TARGET_32BIT && inner_bytes >= 4)
ded9bf77
AH		 17838 return gen_rtx_REG (mode, regno);
17839 }
17840
18f63bfa
AH		 17841 if (inner_bytes >= 8)
17842 return gen_rtx_REG (mode, regno);
17843
ded9bf77
AH		 17844 r1 = gen_rtx_EXPR_LIST (inner, gen_rtx_REG (inner, regno),
17845 const0_rtx);
17846 r2 = gen_rtx_EXPR_LIST (inner, gen_rtx_REG (inner, regno + 1),
fb7e4164 17847 GEN_INT (inner_bytes));
ded9bf77
AH		 17848 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r2));
17849}
17850
a6ebc39a
AH		 17851/* Define how to find the value returned by a function.
17852 VALTYPE is the data type of the value (as a tree).
17853 If the precise function being called is known, FUNC is its FUNCTION_DECL;
17854 otherwise, FUNC is 0.
17855
17856 On the SPE, both FPs and vectors are returned in r3.
17857
17858 On RS/6000 an integer value is in r3 and a floating-point value is in
17859 fp1, unless -msoft-float. */
17860
17861rtx
17862rs6000_function_value (tree valtype, tree func ATTRIBUTE_UNUSED)
17863{
17864 enum machine_mode mode;
2a8fa26c 17865 unsigned int regno;
a6ebc39a 17866
594a51fe
SS		 17867 /* Special handling for structs in darwin64. */
17868 if (rs6000_darwin64_abi
17869 && TYPE_MODE (valtype) == BLKmode
0b5383eb
DJ		 17870 && TREE_CODE (valtype) == RECORD_TYPE
17871 && int_size_in_bytes (valtype) > 0)
594a51fe
SS		 17872 {
17873 CUMULATIVE_ARGS valcum;
17874 rtx valret;
17875
0b5383eb 17876 valcum.words = 0;
594a51fe
SS		 17877 valcum.fregno = FP_ARG_MIN_REG;
17878 valcum.vregno = ALTIVEC_ARG_MIN_REG;
0b5383eb
DJ		 17879 /* Do a trial code generation as if this were going to be passed as
17880 an argument; if any part goes in memory, we return NULL. */
17881 valret = rs6000_darwin64_record_arg (&valcum, valtype, 1, true);
594a51fe
SS		 17882 if (valret)
17883 return valret;
17884 /* Otherwise fall through to standard ABI rules. */
17885 }
17886
0e67400a
FJ		 17887 if (TARGET_32BIT && TARGET_POWERPC64 && TYPE_MODE (valtype) == DImode)
17888 {
17889 /* Long long return value need be split in -mpowerpc64, 32bit ABI. */
17890 return gen_rtx_PARALLEL (DImode,
17891 gen_rtvec (2,
17892 gen_rtx_EXPR_LIST (VOIDmode,
17893 gen_rtx_REG (SImode, GP_ARG_RETURN),
17894 const0_rtx),
17895 gen_rtx_EXPR_LIST (VOIDmode,
17896 gen_rtx_REG (SImode,
17897 GP_ARG_RETURN + 1),
17898 GEN_INT (4))));
17899 }
17900
a6ebc39a
AH		 17901 if ((INTEGRAL_TYPE_P (valtype)
17902 && TYPE_PRECISION (valtype) < BITS_PER_WORD)
17903 || POINTER_TYPE_P (valtype))
b78d48dd 17904 mode = TARGET_32BIT ? SImode : DImode;
a6ebc39a
AH		 17905 else
17906 mode = TYPE_MODE (valtype);
17907
4ed78545 17908 if (SCALAR_FLOAT_TYPE_P (valtype) && TARGET_HARD_FLOAT && TARGET_FPRS)
2a8fa26c 17909 regno = FP_ARG_RETURN;
ded9bf77 17910 else if (TREE_CODE (valtype) == COMPLEX_TYPE
42ba5130 17911 && targetm.calls.split_complex_arg)
ded9bf77 17912 return rs6000_complex_function_value (mode);
44688022 17913 else if (TREE_CODE (valtype) == VECTOR_TYPE
d0b2079e 17914 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI
23ba09f0 17915 && ALTIVEC_VECTOR_MODE (mode))
a6ebc39a 17916 regno = ALTIVEC_ARG_RETURN;
18f63bfa
AH		 17917 else if (TARGET_E500_DOUBLE && TARGET_HARD_FLOAT
17918 && (mode == DFmode || mode == DCmode))
17919 return spe_build_register_parallel (mode, GP_ARG_RETURN);
a6ebc39a
AH		 17920 else
17921 regno = GP_ARG_RETURN;
17922
17923 return gen_rtx_REG (mode, regno);
17924}
17925
ded9bf77
AH		 17926/* Define how to find the value returned by a library function
17927 assuming the value has mode MODE. */
17928rtx
17929rs6000_libcall_value (enum machine_mode mode)
17930{
17931 unsigned int regno;
17932
2e6c9641
FJ		 17933 if (TARGET_32BIT && TARGET_POWERPC64 && mode == DImode)
17934 {
17935 /* Long long return value need be split in -mpowerpc64, 32bit ABI. */
17936 return gen_rtx_PARALLEL (DImode,
17937 gen_rtvec (2,
17938 gen_rtx_EXPR_LIST (VOIDmode,
17939 gen_rtx_REG (SImode, GP_ARG_RETURN),
17940 const0_rtx),
17941 gen_rtx_EXPR_LIST (VOIDmode,
17942 gen_rtx_REG (SImode,
17943 GP_ARG_RETURN + 1),
17944 GEN_INT (4))));
17945 }
17946
ded9bf77
AH		 17947 if (GET_MODE_CLASS (mode) == MODE_FLOAT
17948 && TARGET_HARD_FLOAT && TARGET_FPRS)
17949 regno = FP_ARG_RETURN;
44688022
AM		 17950 else if (ALTIVEC_VECTOR_MODE (mode)
17951 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI)
ded9bf77 17952 regno = ALTIVEC_ARG_RETURN;
42ba5130 17953 else if (COMPLEX_MODE_P (mode) && targetm.calls.split_complex_arg)
ded9bf77 17954 return rs6000_complex_function_value (mode);
18f63bfa
AH		 17955 else if (TARGET_E500_DOUBLE && TARGET_HARD_FLOAT
17956 && (mode == DFmode || mode == DCmode))
17957 return spe_build_register_parallel (mode, GP_ARG_RETURN);
ded9bf77
AH		 17958 else
17959 regno = GP_ARG_RETURN;
17960
17961 return gen_rtx_REG (mode, regno);
17962}
17963
d1d0c603
JJ		 17964/* Define the offset between two registers, FROM to be eliminated and its
17965 replacement TO, at the start of a routine. */
17966HOST_WIDE_INT
17967rs6000_initial_elimination_offset (int from, int to)
17968{
17969 rs6000_stack_t *info = rs6000_stack_info ();
17970 HOST_WIDE_INT offset;
17971
17972 if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
17973 offset = info->push_p ? 0 : -info->total_size;
17974 else if (from == ARG_POINTER_REGNUM && to == FRAME_POINTER_REGNUM)
17975 offset = info->total_size;
17976 else if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
17977 offset = info->push_p ? info->total_size : 0;
17978 else if (from == RS6000_PIC_OFFSET_TABLE_REGNUM)
17979 offset = 0;
17980 else
37409796 17981 gcc_unreachable ();
d1d0c603
JJ		 17982
17983 return offset;
17984}
17985
58646b77 17986/* Return true if TYPE is a SPE or AltiVec opaque type. */
62e1dfcf 17987
c8e4f0e9 17988static bool
58646b77 17989rs6000_is_opaque_type (tree type)
62e1dfcf 17990{
58646b77 17991 return (type == opaque_V2SI_type_node
2abe3e28 17992 || type == opaque_V2SF_type_node
58646b77
PB		 17993 || type == opaque_p_V2SI_type_node
17994 || type == opaque_V4SI_type_node);
62e1dfcf
NC		 17995}
17996
96714395 17997static rtx
a2369ed3 17998rs6000_dwarf_register_span (rtx reg)
96714395
AH		 17999{
18000 unsigned regno;
18001
4d4cbc0e
AH		 18002 if (TARGET_SPE
18003 && (SPE_VECTOR_MODE (GET_MODE (reg))
18004 || (TARGET_E500_DOUBLE && GET_MODE (reg) == DFmode)))
18005 ;
18006 else
96714395
AH		 18007 return NULL_RTX;
18008
18009 regno = REGNO (reg);
18010
18011 /* The duality of the SPE register size wreaks all kinds of havoc.
18012 This is a way of distinguishing r0 in 32-bits from r0 in
18013 64-bits. */
18014 return
18015 gen_rtx_PARALLEL (VOIDmode,
3bd104d1
AH		 18016 BYTES_BIG_ENDIAN
18017 ? gen_rtvec (2,
18018 gen_rtx_REG (SImode, regno + 1200),
18019 gen_rtx_REG (SImode, regno))
18020 : gen_rtvec (2,
18021 gen_rtx_REG (SImode, regno),
18022 gen_rtx_REG (SImode, regno + 1200)));
96714395
AH		 18023}
18024
93c9d1ba
AM		 18025/* Map internal gcc register numbers to DWARF2 register numbers. */
18026
18027unsigned int
18028rs6000_dbx_register_number (unsigned int regno)
18029{
18030 if (regno <= 63 || write_symbols != DWARF2_DEBUG)
18031 return regno;
18032 if (regno == MQ_REGNO)
18033 return 100;
18034 if (regno == LINK_REGISTER_REGNUM)
18035 return 108;
18036 if (regno == COUNT_REGISTER_REGNUM)
18037 return 109;
18038 if (CR_REGNO_P (regno))
18039 return regno - CR0_REGNO + 86;
18040 if (regno == XER_REGNO)
18041 return 101;
18042 if (ALTIVEC_REGNO_P (regno))
18043 return regno - FIRST_ALTIVEC_REGNO + 1124;
18044 if (regno == VRSAVE_REGNO)
18045 return 356;
18046 if (regno == VSCR_REGNO)
18047 return 67;
18048 if (regno == SPE_ACC_REGNO)
18049 return 99;
18050 if (regno == SPEFSCR_REGNO)
18051 return 612;
18052 /* SPE high reg number. We get these values of regno from
18053 rs6000_dwarf_register_span. */
37409796
NS		 18054 gcc_assert (regno >= 1200 && regno < 1232);
18055 return regno;
93c9d1ba
AM		 18056}
18057
93f90be6 18058/* target hook eh_return_filter_mode */
f676971a 18059static enum machine_mode
93f90be6
FJ		 18060rs6000_eh_return_filter_mode (void)
18061{
18062 return TARGET_32BIT ? SImode : word_mode;
18063}
18064
f676971a
EC		 18065/* Target hook for vector_mode_supported_p. */
18066static bool
18067rs6000_vector_mode_supported_p (enum machine_mode mode)
18068{
18069
18070 if (TARGET_SPE && SPE_VECTOR_MODE (mode))
18071 return true;
18072
18073 else if (TARGET_ALTIVEC && ALTIVEC_VECTOR_MODE (mode))
18074 return true;
18075
18076 else
18077 return false;
18078}
18079
4d3e6fae
FJ		 18080/* Target hook for invalid_arg_for_unprototyped_fn. */
18081static const char *
18082invalid_arg_for_unprototyped_fn (tree typelist, tree funcdecl, tree val)
18083{
18084 return (!rs6000_darwin64_abi
18085 && typelist == 0
18086 && TREE_CODE (TREE_TYPE (val)) == VECTOR_TYPE
18087 && (funcdecl == NULL_TREE
18088 || (TREE_CODE (funcdecl) == FUNCTION_DECL
18089 && DECL_BUILT_IN_CLASS (funcdecl) != BUILT_IN_MD)))
18090 ? N_("AltiVec argument passed to unprototyped function")
18091 : NULL;
18092}
18093
17211ab5 18094#include "gt-rs6000.h"
Mirror of https://gcc.gnu.org/git/gcc.git