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f045b2c9 | 1 | /* Definitions of target machine for GNU compiler, for IBM RS/6000. |
9ebbca7d | 2 | Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, |
93c9d1ba | 3 | 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc. |
6a7ec0a7 | 4 | Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu) |
f045b2c9 | 5 | |
5de601cf | 6 | This file is part of GCC. |
f045b2c9 | 7 | |
5de601cf NC |
8 | GCC is free software; you can redistribute it and/or modify it |
9 | under the terms of the GNU General Public License as published | |
10 | by the Free Software Foundation; either version 2, or (at your | |
11 | option) any later version. | |
f045b2c9 | 12 | |
5de601cf NC |
13 | GCC is distributed in the hope that it will be useful, but WITHOUT |
14 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
15 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
16 | License for more details. | |
f045b2c9 | 17 | |
5de601cf NC |
18 | You should have received a copy of the GNU General Public License |
19 | along with GCC; see the file COPYING. If not, write to the | |
20 | Free Software Foundation, 59 Temple Place - Suite 330, Boston, | |
21 | MA 02111-1307, USA. */ | |
f045b2c9 RS |
22 | |
23 | /* Note that some other tm.h files include this one and then override | |
9ebbca7d | 24 | many of the definitions. */ |
f045b2c9 | 25 | |
9ebbca7d GK |
26 | /* Definitions for the object file format. These are set at |
27 | compile-time. */ | |
f045b2c9 | 28 | |
9ebbca7d GK |
29 | #define OBJECT_XCOFF 1 |
30 | #define OBJECT_ELF 2 | |
31 | #define OBJECT_PEF 3 | |
ee890fe2 | 32 | #define OBJECT_MACHO 4 |
f045b2c9 | 33 | |
9ebbca7d | 34 | #define TARGET_ELF (TARGET_OBJECT_FORMAT == OBJECT_ELF) |
2bfcf297 | 35 | #define TARGET_XCOFF (TARGET_OBJECT_FORMAT == OBJECT_XCOFF) |
9ebbca7d | 36 | #define TARGET_MACOS (TARGET_OBJECT_FORMAT == OBJECT_PEF) |
ee890fe2 | 37 | #define TARGET_MACHO (TARGET_OBJECT_FORMAT == OBJECT_MACHO) |
f045b2c9 | 38 | |
2bfcf297 DB |
39 | #ifndef TARGET_AIX |
40 | #define TARGET_AIX 0 | |
41 | #endif | |
42 | ||
8e3f41e7 MM |
43 | /* Default string to use for cpu if not specified. */ |
44 | #ifndef TARGET_CPU_DEFAULT | |
45 | #define TARGET_CPU_DEFAULT ((char *)0) | |
46 | #endif | |
47 | ||
f984d8df DB |
48 | /* Common ASM definitions used by ASM_SPEC among the various targets |
49 | for handling -mcpu=xxx switches. */ | |
50 | #define ASM_CPU_SPEC \ | |
51 | "%{!mcpu*: \ | |
52 | %{mpower: %{!mpower2: -mpwr}} \ | |
53 | %{mpower2: -mpwrx} \ | |
93ae5495 AM |
54 | %{mpowerpc64*: -mppc64} \ |
55 | %{!mpowerpc64*: %{mpowerpc*: -mppc}} \ | |
f984d8df | 56 | %{mno-power: %{!mpowerpc*: -mcom}} \ |
93ae5495 | 57 | %{!mno-power: %{!mpower*: %(asm_default)}}} \ |
f984d8df DB |
58 | %{mcpu=common: -mcom} \ |
59 | %{mcpu=power: -mpwr} \ | |
60 | %{mcpu=power2: -mpwrx} \ | |
93ae5495 | 61 | %{mcpu=power3: -mppc64} \ |
957e9e48 | 62 | %{mcpu=power4: -mpower4} \ |
93ae5495 | 63 | %{mcpu=power5: -mpower4} \ |
f984d8df DB |
64 | %{mcpu=powerpc: -mppc} \ |
65 | %{mcpu=rios: -mpwr} \ | |
66 | %{mcpu=rios1: -mpwr} \ | |
67 | %{mcpu=rios2: -mpwrx} \ | |
68 | %{mcpu=rsc: -mpwr} \ | |
69 | %{mcpu=rsc1: -mpwr} \ | |
93ae5495 | 70 | %{mcpu=rs64a: -mppc64} \ |
f984d8df | 71 | %{mcpu=401: -mppc} \ |
61a8515c JS |
72 | %{mcpu=403: -m403} \ |
73 | %{mcpu=405: -m405} \ | |
2c9d95ef DE |
74 | %{mcpu=405fp: -m405} \ |
75 | %{mcpu=440: -m440} \ | |
76 | %{mcpu=440fp: -m440} \ | |
f984d8df DB |
77 | %{mcpu=505: -mppc} \ |
78 | %{mcpu=601: -m601} \ | |
79 | %{mcpu=602: -mppc} \ | |
80 | %{mcpu=603: -mppc} \ | |
81 | %{mcpu=603e: -mppc} \ | |
82 | %{mcpu=ec603e: -mppc} \ | |
83 | %{mcpu=604: -mppc} \ | |
84 | %{mcpu=604e: -mppc} \ | |
93ae5495 AM |
85 | %{mcpu=620: -mppc64} \ |
86 | %{mcpu=630: -mppc64} \ | |
f984d8df DB |
87 | %{mcpu=740: -mppc} \ |
88 | %{mcpu=750: -mppc} \ | |
49ffe578 | 89 | %{mcpu=G3: -mppc} \ |
93ae5495 AM |
90 | %{mcpu=7400: -mppc -maltivec} \ |
91 | %{mcpu=7450: -mppc -maltivec} \ | |
92 | %{mcpu=G4: -mppc -maltivec} \ | |
f984d8df DB |
93 | %{mcpu=801: -mppc} \ |
94 | %{mcpu=821: -mppc} \ | |
95 | %{mcpu=823: -mppc} \ | |
775db490 | 96 | %{mcpu=860: -mppc} \ |
93ae5495 AM |
97 | %{mcpu=970: -mpower4 -maltivec} \ |
98 | %{mcpu=G5: -mpower4 -maltivec} \ | |
a3170dc6 | 99 | %{mcpu=8540: -me500} \ |
93ae5495 AM |
100 | %{maltivec: -maltivec} \ |
101 | -many" | |
f984d8df DB |
102 | |
103 | #define CPP_DEFAULT_SPEC "" | |
104 | ||
105 | #define ASM_DEFAULT_SPEC "" | |
106 | ||
841faeed MM |
107 | /* This macro defines names of additional specifications to put in the specs |
108 | that can be used in various specifications like CC1_SPEC. Its definition | |
109 | is an initializer with a subgrouping for each command option. | |
110 | ||
111 | Each subgrouping contains a string constant, that defines the | |
5de601cf | 112 | specification name, and a string constant that used by the GCC driver |
841faeed MM |
113 | program. |
114 | ||
115 | Do not define this macro if it does not need to do anything. */ | |
116 | ||
7509c759 | 117 | #define SUBTARGET_EXTRA_SPECS |
7509c759 | 118 | |
c81bebd7 | 119 | #define EXTRA_SPECS \ |
c81bebd7 | 120 | { "cpp_default", CPP_DEFAULT_SPEC }, \ |
c81bebd7 MM |
121 | { "asm_cpu", ASM_CPU_SPEC }, \ |
122 | { "asm_default", ASM_DEFAULT_SPEC }, \ | |
7509c759 MM |
123 | SUBTARGET_EXTRA_SPECS |
124 | ||
fb623df5 | 125 | /* Architecture type. */ |
f045b2c9 | 126 | |
fb623df5 RK |
127 | extern int target_flags; |
128 | ||
129 | /* Use POWER architecture instructions and MQ register. */ | |
38c1f2d7 | 130 | #define MASK_POWER 0x00000001 |
fb623df5 | 131 | |
6febd581 | 132 | /* Use POWER2 extensions to POWER architecture. */ |
38c1f2d7 | 133 | #define MASK_POWER2 0x00000002 |
6febd581 | 134 | |
fb623df5 | 135 | /* Use PowerPC architecture instructions. */ |
38c1f2d7 | 136 | #define MASK_POWERPC 0x00000004 |
6febd581 | 137 | |
583cf4db | 138 | /* Use PowerPC General Purpose group optional instructions, e.g. fsqrt. */ |
38c1f2d7 | 139 | #define MASK_PPC_GPOPT 0x00000008 |
583cf4db RK |
140 | |
141 | /* Use PowerPC Graphics group optional instructions, e.g. fsel. */ | |
38c1f2d7 | 142 | #define MASK_PPC_GFXOPT 0x00000010 |
f045b2c9 | 143 | |
fb623df5 | 144 | /* Use PowerPC-64 architecture instructions. */ |
38c1f2d7 | 145 | #define MASK_POWERPC64 0x00000020 |
f045b2c9 | 146 | |
fb623df5 | 147 | /* Use revised mnemonic names defined for PowerPC architecture. */ |
38c1f2d7 | 148 | #define MASK_NEW_MNEMONICS 0x00000040 |
fb623df5 RK |
149 | |
150 | /* Disable placing fp constants in the TOC; can be turned on when the | |
151 | TOC overflows. */ | |
38c1f2d7 | 152 | #define MASK_NO_FP_IN_TOC 0x00000080 |
fb623df5 | 153 | |
0b9ccabc RK |
154 | /* Disable placing symbol+offset constants in the TOC; can be turned on when |
155 | the TOC overflows. */ | |
38c1f2d7 | 156 | #define MASK_NO_SUM_IN_TOC 0x00000100 |
0b9ccabc | 157 | |
fb623df5 | 158 | /* Output only one TOC entry per module. Normally linking fails if |
642a35f1 JW |
159 | there are more than 16K unique variables/constants in an executable. With |
160 | this option, linking fails only if there are more than 16K modules, or | |
161 | if there are more than 16K unique variables/constant in a single module. | |
162 | ||
163 | This is at the cost of having 2 extra loads and one extra store per | |
956d6950 | 164 | function, and one less allocable register. */ |
38c1f2d7 | 165 | #define MASK_MINIMAL_TOC 0x00000200 |
642a35f1 | 166 | |
7ddb6568 AM |
167 | /* Nonzero for the 64 bit ABIs: longs and pointers are 64 bits. The |
168 | chip is running in "64-bit mode", in which CR0 is set in dot | |
169 | operations based on all 64 bits of the register, bdnz works on 64-bit | |
170 | ctr, lr is 64 bits, and so on. Requires MASK_POWERPC64. */ | |
38c1f2d7 | 171 | #define MASK_64BIT 0x00000400 |
9e654916 | 172 | |
f85f4585 | 173 | /* Disable use of FPRs. */ |
38c1f2d7 | 174 | #define MASK_SOFT_FLOAT 0x00000800 |
f85f4585 | 175 | |
88cad84b | 176 | /* Enable load/store multiple, even on PowerPC */ |
b21fb038 | 177 | #define MASK_MULTIPLE 0x00001000 |
4d30c363 | 178 | |
7e69e155 | 179 | /* Use string instructions for block moves */ |
b21fb038 | 180 | #define MASK_STRING 0x00002000 |
7e69e155 | 181 | |
38c1f2d7 | 182 | /* Disable update form of load/store */ |
b21fb038 | 183 | #define MASK_NO_UPDATE 0x00004000 |
38c1f2d7 MM |
184 | |
185 | /* Disable fused multiply/add operations */ | |
b21fb038 | 186 | #define MASK_NO_FUSED_MADD 0x00008000 |
4697a36c | 187 | |
9ebbca7d | 188 | /* Nonzero if we need to schedule the prolog and epilog. */ |
b21fb038 | 189 | #define MASK_SCHED_PROLOG 0x00010000 |
9ebbca7d | 190 | |
0ac081f6 | 191 | /* Use AltiVec instructions. */ |
b21fb038 | 192 | #define MASK_ALTIVEC 0x00020000 |
0ac081f6 | 193 | |
6fa3f289 | 194 | /* Return small structures in memory (as the AIX ABI requires). */ |
b21fb038 | 195 | #define MASK_AIX_STRUCT_RET 0x00040000 |
0ac081f6 | 196 | |
ffa22984 DE |
197 | /* Use single field mfcr instruction. */ |
198 | #define MASK_MFCRF 0x00080000 | |
199 | ||
895ea8f0 AM |
200 | /* The only remaining free bits are 0x00600000. linux64.h uses |
201 | 0x00100000, and sysv4.h uses 0x00800000 -> 0x40000000. | |
202 | 0x80000000 is not available because target_flags is signed. */ | |
06f4e019 | 203 | |
7e69e155 MM |
204 | #define TARGET_POWER (target_flags & MASK_POWER) |
205 | #define TARGET_POWER2 (target_flags & MASK_POWER2) | |
206 | #define TARGET_POWERPC (target_flags & MASK_POWERPC) | |
207 | #define TARGET_PPC_GPOPT (target_flags & MASK_PPC_GPOPT) | |
208 | #define TARGET_PPC_GFXOPT (target_flags & MASK_PPC_GFXOPT) | |
7e69e155 MM |
209 | #define TARGET_NEW_MNEMONICS (target_flags & MASK_NEW_MNEMONICS) |
210 | #define TARGET_NO_FP_IN_TOC (target_flags & MASK_NO_FP_IN_TOC) | |
211 | #define TARGET_NO_SUM_IN_TOC (target_flags & MASK_NO_SUM_IN_TOC) | |
212 | #define TARGET_MINIMAL_TOC (target_flags & MASK_MINIMAL_TOC) | |
213 | #define TARGET_64BIT (target_flags & MASK_64BIT) | |
214 | #define TARGET_SOFT_FLOAT (target_flags & MASK_SOFT_FLOAT) | |
b21fb038 | 215 | #define TARGET_MULTIPLE (target_flags & MASK_MULTIPLE) |
7e69e155 | 216 | #define TARGET_STRING (target_flags & MASK_STRING) |
38c1f2d7 MM |
217 | #define TARGET_NO_UPDATE (target_flags & MASK_NO_UPDATE) |
218 | #define TARGET_NO_FUSED_MADD (target_flags & MASK_NO_FUSED_MADD) | |
9ebbca7d | 219 | #define TARGET_SCHED_PROLOG (target_flags & MASK_SCHED_PROLOG) |
0ac081f6 | 220 | #define TARGET_ALTIVEC (target_flags & MASK_ALTIVEC) |
6fa3f289 | 221 | #define TARGET_AIX_STRUCT_RET (target_flags & MASK_AIX_STRUCT_RET) |
7e69e155 | 222 | |
ffa22984 DE |
223 | /* Define TARGET_MFCRF if the target assembler supports the optional |
224 | field operand for mfcr and the target processor supports the | |
225 | instruction. */ | |
226 | ||
227 | #ifdef HAVE_AS_MFCRF | |
228 | #define TARGET_MFCRF (target_flags & MASK_MFCRF) | |
229 | #else | |
230 | #define TARGET_MFCRF 0 | |
231 | #endif | |
232 | ||
233 | ||
2f3e5814 | 234 | #define TARGET_32BIT (! TARGET_64BIT) |
7e69e155 | 235 | #define TARGET_HARD_FLOAT (! TARGET_SOFT_FLOAT) |
38c1f2d7 MM |
236 | #define TARGET_UPDATE (! TARGET_NO_UPDATE) |
237 | #define TARGET_FUSED_MADD (! TARGET_NO_FUSED_MADD) | |
d14a6d05 | 238 | |
c973d557 JJ |
239 | /* Emit a dtp-relative reference to a TLS variable. */ |
240 | ||
241 | #ifdef HAVE_AS_TLS | |
242 | #define ASM_OUTPUT_DWARF_DTPREL(FILE, SIZE, X) \ | |
243 | rs6000_output_dwarf_dtprel (FILE, SIZE, X) | |
244 | #endif | |
245 | ||
c4501e62 JJ |
246 | #ifndef HAVE_AS_TLS |
247 | #define HAVE_AS_TLS 0 | |
248 | #endif | |
249 | ||
996ed075 JJ |
250 | #ifdef IN_LIBGCC2 |
251 | /* For libgcc2 we make sure this is a compile time constant */ | |
0134bf2d | 252 | #if defined (__64BIT__) || defined (__powerpc64__) |
996ed075 JJ |
253 | #define TARGET_POWERPC64 1 |
254 | #else | |
255 | #define TARGET_POWERPC64 0 | |
256 | #endif | |
b6c9286a | 257 | #else |
9ebbca7d | 258 | #define TARGET_POWERPC64 (target_flags & MASK_POWERPC64) |
b6c9286a MM |
259 | #endif |
260 | ||
a3950905 | 261 | #define TARGET_XL_CALL 0 |
a3950905 | 262 | |
fb623df5 | 263 | /* Run-time compilation parameters selecting different hardware subsets. |
f045b2c9 | 264 | |
fb623df5 | 265 | Macro to define tables used to set the flags. |
f045b2c9 RS |
266 | This is a list in braces of pairs in braces, |
267 | each pair being { "NAME", VALUE } | |
268 | where VALUE is the bits to set or minus the bits to clear. | |
269 | An empty string NAME is used to identify the default VALUE. */ | |
270 | ||
938937d8 | 271 | #define TARGET_SWITCHES \ |
9ebbca7d | 272 | {{"power", MASK_POWER | MASK_MULTIPLE | MASK_STRING, \ |
047142d3 | 273 | N_("Use POWER instruction set")}, \ |
938937d8 | 274 | {"power2", (MASK_POWER | MASK_MULTIPLE | MASK_STRING \ |
9ebbca7d | 275 | | MASK_POWER2), \ |
047142d3 | 276 | N_("Use POWER2 instruction set")}, \ |
9ebbca7d | 277 | {"no-power2", - MASK_POWER2, \ |
047142d3 | 278 | N_("Do not use POWER2 instruction set")}, \ |
938937d8 | 279 | {"no-power", - (MASK_POWER | MASK_POWER2 | MASK_MULTIPLE \ |
9ebbca7d | 280 | | MASK_STRING), \ |
047142d3 | 281 | N_("Do not use POWER instruction set")}, \ |
9ebbca7d | 282 | {"powerpc", MASK_POWERPC, \ |
047142d3 | 283 | N_("Use PowerPC instruction set")}, \ |
938937d8 | 284 | {"no-powerpc", - (MASK_POWERPC | MASK_PPC_GPOPT \ |
9ebbca7d | 285 | | MASK_PPC_GFXOPT | MASK_POWERPC64), \ |
047142d3 | 286 | N_("Do not use PowerPC instruction set")}, \ |
9ebbca7d | 287 | {"powerpc-gpopt", MASK_POWERPC | MASK_PPC_GPOPT, \ |
047142d3 | 288 | N_("Use PowerPC General Purpose group optional instructions")},\ |
9ebbca7d | 289 | {"no-powerpc-gpopt", - MASK_PPC_GPOPT, \ |
ffa22984 | 290 | N_("Do not use PowerPC General Purpose group optional instructions")},\ |
9ebbca7d | 291 | {"powerpc-gfxopt", MASK_POWERPC | MASK_PPC_GFXOPT, \ |
047142d3 | 292 | N_("Use PowerPC Graphics group optional instructions")},\ |
9ebbca7d | 293 | {"no-powerpc-gfxopt", - MASK_PPC_GFXOPT, \ |
ffa22984 | 294 | N_("Do not use PowerPC Graphics group optional instructions")},\ |
9ebbca7d | 295 | {"powerpc64", MASK_POWERPC64, \ |
047142d3 | 296 | N_("Use PowerPC-64 instruction set")}, \ |
9ebbca7d | 297 | {"no-powerpc64", - MASK_POWERPC64, \ |
ffa22984 | 298 | N_("Do not use PowerPC-64 instruction set")}, \ |
f18c054f | 299 | {"altivec", MASK_ALTIVEC , \ |
c725bd79 | 300 | N_("Use AltiVec instructions")}, \ |
f18c054f | 301 | {"no-altivec", - MASK_ALTIVEC , \ |
ffa22984 | 302 | N_("Do not use AltiVec instructions")}, \ |
9ebbca7d | 303 | {"new-mnemonics", MASK_NEW_MNEMONICS, \ |
047142d3 | 304 | N_("Use new mnemonics for PowerPC architecture")},\ |
9ebbca7d | 305 | {"old-mnemonics", -MASK_NEW_MNEMONICS, \ |
047142d3 | 306 | N_("Use old mnemonics for PowerPC architecture")},\ |
938937d8 | 307 | {"full-toc", - (MASK_NO_FP_IN_TOC | MASK_NO_SUM_IN_TOC \ |
9ebbca7d | 308 | | MASK_MINIMAL_TOC), \ |
047142d3 | 309 | N_("Put everything in the regular TOC")}, \ |
9ebbca7d | 310 | {"fp-in-toc", - MASK_NO_FP_IN_TOC, \ |
047142d3 | 311 | N_("Place floating point constants in TOC")}, \ |
9ebbca7d | 312 | {"no-fp-in-toc", MASK_NO_FP_IN_TOC, \ |
ffa22984 | 313 | N_("Do not place floating point constants in TOC")},\ |
9ebbca7d | 314 | {"sum-in-toc", - MASK_NO_SUM_IN_TOC, \ |
047142d3 | 315 | N_("Place symbol+offset constants in TOC")}, \ |
9ebbca7d | 316 | {"no-sum-in-toc", MASK_NO_SUM_IN_TOC, \ |
ffa22984 | 317 | N_("Do not place symbol+offset constants in TOC")},\ |
9ebbca7d GK |
318 | {"minimal-toc", MASK_MINIMAL_TOC, \ |
319 | "Use only one TOC entry per procedure"}, \ | |
320 | {"minimal-toc", - (MASK_NO_FP_IN_TOC | MASK_NO_SUM_IN_TOC), \ | |
047142d3 | 321 | ""}, \ |
9ebbca7d | 322 | {"no-minimal-toc", - MASK_MINIMAL_TOC, \ |
047142d3 | 323 | N_("Place variable addresses in the regular TOC")},\ |
9ebbca7d | 324 | {"hard-float", - MASK_SOFT_FLOAT, \ |
ffa22984 | 325 | N_("Use hardware floating point")}, \ |
9ebbca7d | 326 | {"soft-float", MASK_SOFT_FLOAT, \ |
ffa22984 | 327 | N_("Do not use hardware floating point")}, \ |
b21fb038 | 328 | {"multiple", MASK_MULTIPLE, \ |
047142d3 | 329 | N_("Generate load/store multiple instructions")}, \ |
9ebbca7d | 330 | {"no-multiple", - MASK_MULTIPLE, \ |
047142d3 | 331 | N_("Do not generate load/store multiple instructions")},\ |
b21fb038 | 332 | {"string", MASK_STRING, \ |
047142d3 | 333 | N_("Generate string instructions for block moves")},\ |
9ebbca7d | 334 | {"no-string", - MASK_STRING, \ |
047142d3 | 335 | N_("Do not generate string instructions for block moves")},\ |
9ebbca7d | 336 | {"update", - MASK_NO_UPDATE, \ |
047142d3 | 337 | N_("Generate load/store with update instructions")},\ |
9ebbca7d | 338 | {"no-update", MASK_NO_UPDATE, \ |
047142d3 | 339 | N_("Do not generate load/store with update instructions")},\ |
9ebbca7d | 340 | {"fused-madd", - MASK_NO_FUSED_MADD, \ |
047142d3 | 341 | N_("Generate fused multiply/add instructions")},\ |
9ebbca7d | 342 | {"no-fused-madd", MASK_NO_FUSED_MADD, \ |
ffa22984 | 343 | N_("Do not generate fused multiply/add instructions")},\ |
9ebbca7d GK |
344 | {"sched-prolog", MASK_SCHED_PROLOG, \ |
345 | ""}, \ | |
346 | {"no-sched-prolog", -MASK_SCHED_PROLOG, \ | |
ffa22984 | 347 | N_("Do not schedule the start and end of the procedure")},\ |
9ebbca7d GK |
348 | {"sched-epilog", MASK_SCHED_PROLOG, \ |
349 | ""}, \ | |
350 | {"no-sched-epilog", -MASK_SCHED_PROLOG, \ | |
351 | ""}, \ | |
b21fb038 | 352 | {"aix-struct-return", MASK_AIX_STRUCT_RET, \ |
6fa3f289 | 353 | N_("Return all structures in memory (AIX default)")},\ |
b21fb038 | 354 | {"svr4-struct-return", - MASK_AIX_STRUCT_RET, \ |
6fa3f289 | 355 | N_("Return small structures in registers (SVR4 default)")},\ |
b21fb038 | 356 | {"no-aix-struct-return", - MASK_AIX_STRUCT_RET, \ |
ffa22984 | 357 | ""}, \ |
b21fb038 | 358 | {"no-svr4-struct-return", MASK_AIX_STRUCT_RET, \ |
ffa22984 DE |
359 | ""}, \ |
360 | {"mfcrf", MASK_MFCRF, \ | |
361 | N_("Generate single field mfcr instruction")}, \ | |
362 | {"no-mfcrf", - MASK_MFCRF, \ | |
363 | N_("Do not generate single field mfcr instruction")},\ | |
938937d8 | 364 | SUBTARGET_SWITCHES \ |
9ebbca7d GK |
365 | {"", TARGET_DEFAULT | MASK_SCHED_PROLOG, \ |
366 | ""}} | |
fb623df5 | 367 | |
938937d8 | 368 | #define TARGET_DEFAULT (MASK_POWER | MASK_MULTIPLE | MASK_STRING) |
9ebbca7d GK |
369 | |
370 | /* This is meant to be redefined in the host dependent files */ | |
371 | #define SUBTARGET_SWITCHES | |
fb623df5 | 372 | |
cac8ce95 | 373 | /* Processor type. Order must match cpu attribute in MD file. */ |
fb623df5 | 374 | enum processor_type |
bef84347 VM |
375 | { |
376 | PROCESSOR_RIOS1, | |
377 | PROCESSOR_RIOS2, | |
3cb999d8 | 378 | PROCESSOR_RS64A, |
bef84347 VM |
379 | PROCESSOR_MPCCORE, |
380 | PROCESSOR_PPC403, | |
fe7f5677 | 381 | PROCESSOR_PPC405, |
b54cf83a | 382 | PROCESSOR_PPC440, |
bef84347 VM |
383 | PROCESSOR_PPC601, |
384 | PROCESSOR_PPC603, | |
385 | PROCESSOR_PPC604, | |
386 | PROCESSOR_PPC604e, | |
387 | PROCESSOR_PPC620, | |
3cb999d8 | 388 | PROCESSOR_PPC630, |
ed947a96 DJ |
389 | PROCESSOR_PPC750, |
390 | PROCESSOR_PPC7400, | |
309323c2 | 391 | PROCESSOR_PPC7450, |
a3170dc6 | 392 | PROCESSOR_PPC8540, |
ec507f2d DE |
393 | PROCESSOR_POWER4, |
394 | PROCESSOR_POWER5 | |
bef84347 | 395 | }; |
fb623df5 RK |
396 | |
397 | extern enum processor_type rs6000_cpu; | |
398 | ||
399 | /* Recast the processor type to the cpu attribute. */ | |
400 | #define rs6000_cpu_attr ((enum attr_cpu)rs6000_cpu) | |
401 | ||
8482e358 | 402 | /* Define generic processor types based upon current deployment. */ |
3cb999d8 DE |
403 | #define PROCESSOR_COMMON PROCESSOR_PPC601 |
404 | #define PROCESSOR_POWER PROCESSOR_RIOS1 | |
405 | #define PROCESSOR_POWERPC PROCESSOR_PPC604 | |
406 | #define PROCESSOR_POWERPC64 PROCESSOR_RS64A | |
6e151478 | 407 | |
fb623df5 | 408 | /* Define the default processor. This is overridden by other tm.h files. */ |
3cb999d8 DE |
409 | #define PROCESSOR_DEFAULT PROCESSOR_RIOS1 |
410 | #define PROCESSOR_DEFAULT64 PROCESSOR_RS64A | |
fb623df5 | 411 | |
6febd581 RK |
412 | /* Specify the dialect of assembler to use. New mnemonics is dialect one |
413 | and the old mnemonics are dialect zero. */ | |
9ebbca7d | 414 | #define ASSEMBLER_DIALECT (TARGET_NEW_MNEMONICS ? 1 : 0) |
6febd581 | 415 | |
569fa502 DN |
416 | /* Types of costly dependences. */ |
417 | enum rs6000_dependence_cost | |
418 | { | |
419 | max_dep_latency = 1000, | |
420 | no_dep_costly, | |
421 | all_deps_costly, | |
422 | true_store_to_load_dep_costly, | |
423 | store_to_load_dep_costly | |
424 | }; | |
425 | ||
cbe26ab8 DN |
426 | /* Types of nop insertion schemes in sched target hook sched_finish. */ |
427 | enum rs6000_nop_insertion | |
428 | { | |
429 | sched_finish_regroup_exact = 1000, | |
430 | sched_finish_pad_groups, | |
431 | sched_finish_none | |
432 | }; | |
433 | ||
434 | /* Dispatch group termination caused by an insn. */ | |
435 | enum group_termination | |
436 | { | |
437 | current_group, | |
438 | previous_group | |
439 | }; | |
440 | ||
956d6950 | 441 | /* This is meant to be overridden in target specific files. */ |
b6c9286a | 442 | #define SUBTARGET_OPTIONS |
b6c9286a | 443 | |
9ebbca7d GK |
444 | #define TARGET_OPTIONS \ |
445 | { \ | |
047142d3 | 446 | {"cpu=", &rs6000_select[1].string, \ |
c409ea0d | 447 | N_("Use features of and schedule code for given CPU"), 0}, \ |
047142d3 | 448 | {"tune=", &rs6000_select[2].string, \ |
c409ea0d DD |
449 | N_("Schedule code for given CPU"), 0}, \ |
450 | {"debug=", &rs6000_debug_name, N_("Enable debug output"), 0}, \ | |
57ac7be9 | 451 | {"traceback=", &rs6000_traceback_name, \ |
c409ea0d DD |
452 | N_("Select full, part, or no traceback table"), 0}, \ |
453 | {"abi=", &rs6000_abi_string, N_("Specify ABI to use"), 0}, \ | |
6fa3f289 | 454 | {"long-double-", &rs6000_long_double_size_string, \ |
c409ea0d | 455 | N_("Specify size of long double (64 or 128 bits)"), 0}, \ |
a3170dc6 | 456 | {"isel=", &rs6000_isel_string, \ |
c409ea0d | 457 | N_("Specify yes/no if isel instructions should be generated"), 0}, \ |
993f19a8 | 458 | {"spe=", &rs6000_spe_string, \ |
c409ea0d | 459 | N_("Specify yes/no if SPE SIMD instructions should be generated"), 0},\ |
5da702b1 | 460 | {"float-gprs=", &rs6000_float_gprs_string, \ |
c409ea0d DD |
461 | N_("Specify yes/no if using floating point in the GPRs"), 0}, \ |
462 | {"vrsave=", &rs6000_altivec_vrsave_string, \ | |
463 | N_("Specify yes/no if VRSAVE instructions should be generated for AltiVec"), 0}, \ | |
a5c76ee6 | 464 | {"longcall", &rs6000_longcall_switch, \ |
c409ea0d DD |
465 | N_("Avoid all range limits on call instructions"), 0}, \ |
466 | {"no-longcall", &rs6000_longcall_switch, "", 0}, \ | |
8bb418a3 ZL |
467 | {"warn-altivec-long", &rs6000_warn_altivec_long_switch, \ |
468 | N_("Warn about deprecated 'vector long ...' AltiVec type usage"), 0}, \ | |
469 | {"no-warn-altivec-long", &rs6000_warn_altivec_long_switch, "", 0}, \ | |
569fa502 | 470 | {"sched-costly-dep=", &rs6000_sched_costly_dep_str, \ |
cbe26ab8 DN |
471 | N_("Determine which dependences between insns are considered costly"), 0}, \ |
472 | {"insert-sched-nops=", &rs6000_sched_insert_nops_str, \ | |
473 | N_("Specify which post scheduling nop insertion scheme to apply"), 0}, \ | |
025d9908 KH |
474 | {"align-", &rs6000_alignment_string, \ |
475 | N_("Specify alignment of structure fields default/natural"), 0}, \ | |
79ae11c4 DN |
476 | {"prioritize-restricted-insns=", &rs6000_sched_restricted_insns_priority_str, \ |
477 | N_("Specify scheduling priority for dispatch slot restricted insns"), 0}, \ | |
9ebbca7d | 478 | SUBTARGET_OPTIONS \ |
b6c9286a | 479 | } |
fb623df5 | 480 | |
7816bea0 DJ |
481 | /* Support for a compile-time default CPU, et cetera. The rules are: |
482 | --with-cpu is ignored if -mcpu is specified. | |
483 | --with-tune is ignored if -mtune is specified. | |
484 | --with-float is ignored if -mhard-float or -msoft-float are | |
485 | specified. */ | |
486 | #define OPTION_DEFAULT_SPECS \ | |
487 | {"cpu", "%{!mcpu=*:-mcpu=%(VALUE)}" }, \ | |
488 | {"tune", "%{!mtune=*:-mtune=%(VALUE)}" }, \ | |
489 | {"float", "%{!msoft-float:%{!mhard-float:-m%(VALUE)-float}}" } | |
490 | ||
ff222560 | 491 | /* rs6000_select[0] is reserved for the default cpu defined via --with-cpu */ |
8e3f41e7 MM |
492 | struct rs6000_cpu_select |
493 | { | |
815cdc52 MM |
494 | const char *string; |
495 | const char *name; | |
8e3f41e7 MM |
496 | int set_tune_p; |
497 | int set_arch_p; | |
498 | }; | |
499 | ||
500 | extern struct rs6000_cpu_select rs6000_select[]; | |
fb623df5 | 501 | |
38c1f2d7 | 502 | /* Debug support */ |
0ac081f6 | 503 | extern const char *rs6000_debug_name; /* Name for -mdebug-xxxx option */ |
f607bc57 | 504 | extern const char *rs6000_abi_string; /* for -mabi={sysv,darwin,eabi,aix,altivec} */ |
38c1f2d7 MM |
505 | extern int rs6000_debug_stack; /* debug stack applications */ |
506 | extern int rs6000_debug_arg; /* debug argument handling */ | |
507 | ||
508 | #define TARGET_DEBUG_STACK rs6000_debug_stack | |
509 | #define TARGET_DEBUG_ARG rs6000_debug_arg | |
510 | ||
57ac7be9 AM |
511 | extern const char *rs6000_traceback_name; /* Type of traceback table. */ |
512 | ||
6fa3f289 ZW |
513 | /* These are separate from target_flags because we've run out of bits |
514 | there. */ | |
515 | extern const char *rs6000_long_double_size_string; | |
516 | extern int rs6000_long_double_type_size; | |
517 | extern int rs6000_altivec_abi; | |
a3170dc6 AH |
518 | extern int rs6000_spe_abi; |
519 | extern int rs6000_isel; | |
993f19a8 | 520 | extern int rs6000_spe; |
5da702b1 AH |
521 | extern int rs6000_float_gprs; |
522 | extern const char *rs6000_float_gprs_string; | |
a3170dc6 | 523 | extern const char *rs6000_isel_string; |
993f19a8 | 524 | extern const char *rs6000_spe_string; |
08b57fb3 AH |
525 | extern const char *rs6000_altivec_vrsave_string; |
526 | extern int rs6000_altivec_vrsave; | |
a5c76ee6 ZW |
527 | extern const char *rs6000_longcall_switch; |
528 | extern int rs6000_default_long_calls; | |
025d9908 KH |
529 | extern const char* rs6000_alignment_string; |
530 | extern int rs6000_alignment_flags; | |
79ae11c4 DN |
531 | extern const char *rs6000_sched_restricted_insns_priority_str; |
532 | extern int rs6000_sched_restricted_insns_priority; | |
569fa502 DN |
533 | extern const char *rs6000_sched_costly_dep_str; |
534 | extern enum rs6000_dependence_cost rs6000_sched_costly_dep; | |
cbe26ab8 DN |
535 | extern const char *rs6000_sched_insert_nops_str; |
536 | extern enum rs6000_nop_insertion rs6000_sched_insert_nops; | |
025d9908 | 537 | |
8bb418a3 ZL |
538 | extern int rs6000_warn_altivec_long; |
539 | extern const char *rs6000_warn_altivec_long_switch; | |
540 | ||
025d9908 KH |
541 | /* Alignment options for fields in structures for sub-targets following |
542 | AIX-like ABI. | |
543 | ALIGN_POWER word-aligns FP doubles (default AIX ABI). | |
544 | ALIGN_NATURAL doubleword-aligns FP doubles (align to object size). | |
545 | ||
546 | Override the macro definitions when compiling libobjc to avoid undefined | |
547 | reference to rs6000_alignment_flags due to library's use of GCC alignment | |
548 | macros which use the macros below. */ | |
549 | ||
550 | #ifndef IN_TARGET_LIBS | |
551 | #define MASK_ALIGN_POWER 0x00000000 | |
552 | #define MASK_ALIGN_NATURAL 0x00000001 | |
553 | #define TARGET_ALIGN_NATURAL (rs6000_alignment_flags & MASK_ALIGN_NATURAL) | |
554 | #else | |
555 | #define TARGET_ALIGN_NATURAL 0 | |
556 | #endif | |
6fa3f289 ZW |
557 | |
558 | #define TARGET_LONG_DOUBLE_128 (rs6000_long_double_type_size == 128) | |
559 | #define TARGET_ALTIVEC_ABI rs6000_altivec_abi | |
08b57fb3 | 560 | #define TARGET_ALTIVEC_VRSAVE rs6000_altivec_vrsave |
6fa3f289 | 561 | |
a3170dc6 AH |
562 | #define TARGET_SPE_ABI 0 |
563 | #define TARGET_SPE 0 | |
993f19a8 | 564 | #define TARGET_E500 0 |
a3170dc6 AH |
565 | #define TARGET_ISEL 0 |
566 | #define TARGET_FPRS 1 | |
567 | ||
fb623df5 RK |
568 | /* Sometimes certain combinations of command options do not make sense |
569 | on a particular target machine. You can define a macro | |
570 | `OVERRIDE_OPTIONS' to take account of this. This macro, if | |
571 | defined, is executed once just after all the command options have | |
572 | been parsed. | |
573 | ||
ffa22984 | 574 | Do not use this macro to turn on various extra optimizations for |
5accd822 DE |
575 | `-O'. That is what `OPTIMIZATION_OPTIONS' is for. |
576 | ||
fb623df5 RK |
577 | On the RS/6000 this is used to define the target cpu type. */ |
578 | ||
8e3f41e7 | 579 | #define OVERRIDE_OPTIONS rs6000_override_options (TARGET_CPU_DEFAULT) |
f045b2c9 | 580 | |
5accd822 DE |
581 | /* Define this to change the optimizations performed by default. */ |
582 | #define OPTIMIZATION_OPTIONS(LEVEL,SIZE) optimization_options(LEVEL,SIZE) | |
583 | ||
4c4eb375 GK |
584 | /* Show we can debug even without a frame pointer. */ |
585 | #define CAN_DEBUG_WITHOUT_FP | |
586 | ||
a5c76ee6 | 587 | /* Target pragma. */ |
c58b209a NB |
588 | #define REGISTER_TARGET_PRAGMAS() do { \ |
589 | c_register_pragma (0, "longcall", rs6000_pragma_longcall); \ | |
a5c76ee6 ZW |
590 | } while (0) |
591 | ||
4c4eb375 GK |
592 | /* Target #defines. */ |
593 | #define TARGET_CPU_CPP_BUILTINS() \ | |
594 | rs6000_cpu_cpp_builtins (pfile) | |
647d340d JT |
595 | |
596 | /* This is used by rs6000_cpu_cpp_builtins to indicate the byte order | |
597 | we're compiling for. Some configurations may need to override it. */ | |
598 | #define RS6000_CPU_CPP_ENDIAN_BUILTINS() \ | |
599 | do \ | |
600 | { \ | |
601 | if (BYTES_BIG_ENDIAN) \ | |
602 | { \ | |
603 | builtin_define ("__BIG_ENDIAN__"); \ | |
604 | builtin_define ("_BIG_ENDIAN"); \ | |
605 | builtin_assert ("machine=bigendian"); \ | |
606 | } \ | |
607 | else \ | |
608 | { \ | |
609 | builtin_define ("__LITTLE_ENDIAN__"); \ | |
610 | builtin_define ("_LITTLE_ENDIAN"); \ | |
611 | builtin_assert ("machine=littleendian"); \ | |
612 | } \ | |
613 | } \ | |
614 | while (0) | |
f045b2c9 | 615 | \f |
4c4eb375 | 616 | /* Target machine storage layout. */ |
f045b2c9 | 617 | |
13d39dbc | 618 | /* Define this macro if it is advisable to hold scalars in registers |
c81bebd7 | 619 | in a wider mode than that declared by the program. In such cases, |
ef457bda RK |
620 | the value is constrained to be within the bounds of the declared |
621 | type, but kept valid in the wider mode. The signedness of the | |
622 | extension may differ from that of the type. */ | |
623 | ||
39403d82 DE |
624 | #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \ |
625 | if (GET_MODE_CLASS (MODE) == MODE_INT \ | |
626 | && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \ | |
b78d48dd | 627 | (MODE) = TARGET_32BIT ? SImode : DImode; |
39403d82 | 628 | |
f045b2c9 | 629 | /* Define this if most significant bit is lowest numbered |
82e41834 KH |
630 | in instructions that operate on numbered bit-fields. */ |
631 | /* That is true on RS/6000. */ | |
f045b2c9 RS |
632 | #define BITS_BIG_ENDIAN 1 |
633 | ||
634 | /* Define this if most significant byte of a word is the lowest numbered. */ | |
635 | /* That is true on RS/6000. */ | |
636 | #define BYTES_BIG_ENDIAN 1 | |
637 | ||
638 | /* Define this if most significant word of a multiword number is lowest | |
c81bebd7 | 639 | numbered. |
f045b2c9 RS |
640 | |
641 | For RS/6000 we can decide arbitrarily since there are no machine | |
82e41834 | 642 | instructions for them. Might as well be consistent with bits and bytes. */ |
f045b2c9 RS |
643 | #define WORDS_BIG_ENDIAN 1 |
644 | ||
2e360ab3 | 645 | #define MAX_BITS_PER_WORD 64 |
f045b2c9 RS |
646 | |
647 | /* Width of a word, in units (bytes). */ | |
c1aa3958 | 648 | #define UNITS_PER_WORD (! TARGET_POWERPC64 ? 4 : 8) |
f34fc46e DE |
649 | #ifdef IN_LIBGCC2 |
650 | #define MIN_UNITS_PER_WORD UNITS_PER_WORD | |
651 | #else | |
ef0e53ce | 652 | #define MIN_UNITS_PER_WORD 4 |
f34fc46e | 653 | #endif |
2e360ab3 | 654 | #define UNITS_PER_FP_WORD 8 |
0ac081f6 | 655 | #define UNITS_PER_ALTIVEC_WORD 16 |
a3170dc6 | 656 | #define UNITS_PER_SPE_WORD 8 |
f045b2c9 | 657 | |
915f619f JW |
658 | /* Type used for ptrdiff_t, as a string used in a declaration. */ |
659 | #define PTRDIFF_TYPE "int" | |
660 | ||
058ef853 DE |
661 | /* Type used for size_t, as a string used in a declaration. */ |
662 | #define SIZE_TYPE "long unsigned int" | |
663 | ||
f045b2c9 RS |
664 | /* Type used for wchar_t, as a string used in a declaration. */ |
665 | #define WCHAR_TYPE "short unsigned int" | |
666 | ||
667 | /* Width of wchar_t in bits. */ | |
668 | #define WCHAR_TYPE_SIZE 16 | |
669 | ||
9e654916 RK |
670 | /* A C expression for the size in bits of the type `short' on the |
671 | target machine. If you don't define this, the default is half a | |
672 | word. (If this would be less than one storage unit, it is | |
673 | rounded up to one unit.) */ | |
674 | #define SHORT_TYPE_SIZE 16 | |
675 | ||
676 | /* A C expression for the size in bits of the type `int' on the | |
677 | target machine. If you don't define this, the default is one | |
678 | word. */ | |
19d2d16f | 679 | #define INT_TYPE_SIZE 32 |
9e654916 RK |
680 | |
681 | /* A C expression for the size in bits of the type `long' on the | |
682 | target machine. If you don't define this, the default is one | |
683 | word. */ | |
2f3e5814 | 684 | #define LONG_TYPE_SIZE (TARGET_32BIT ? 32 : 64) |
9e654916 RK |
685 | |
686 | /* A C expression for the size in bits of the type `long long' on the | |
687 | target machine. If you don't define this, the default is two | |
688 | words. */ | |
689 | #define LONG_LONG_TYPE_SIZE 64 | |
690 | ||
9e654916 RK |
691 | /* A C expression for the size in bits of the type `float' on the |
692 | target machine. If you don't define this, the default is one | |
693 | word. */ | |
694 | #define FLOAT_TYPE_SIZE 32 | |
695 | ||
696 | /* A C expression for the size in bits of the type `double' on the | |
697 | target machine. If you don't define this, the default is two | |
698 | words. */ | |
699 | #define DOUBLE_TYPE_SIZE 64 | |
700 | ||
701 | /* A C expression for the size in bits of the type `long double' on | |
702 | the target machine. If you don't define this, the default is two | |
703 | words. */ | |
6fa3f289 | 704 | #define LONG_DOUBLE_TYPE_SIZE rs6000_long_double_type_size |
06f4e019 | 705 | |
06f4e019 DE |
706 | /* Define this to set long double type size to use in libgcc2.c, which can |
707 | not depend on target_flags. */ | |
708 | #ifdef __LONG_DOUBLE_128__ | |
709 | #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128 | |
710 | #else | |
711 | #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64 | |
712 | #endif | |
9e654916 | 713 | |
5b8f5865 DE |
714 | /* Work around rs6000_long_double_type_size dependency in ada/targtyps.c. */ |
715 | #define WIDEST_HARDWARE_FP_SIZE 64 | |
716 | ||
f045b2c9 RS |
717 | /* Width in bits of a pointer. |
718 | See also the macro `Pmode' defined below. */ | |
2f3e5814 | 719 | #define POINTER_SIZE (TARGET_32BIT ? 32 : 64) |
f045b2c9 RS |
720 | |
721 | /* Allocation boundary (in *bits*) for storing arguments in argument list. */ | |
2f3e5814 | 722 | #define PARM_BOUNDARY (TARGET_32BIT ? 32 : 64) |
f045b2c9 RS |
723 | |
724 | /* Boundary (in *bits*) on which stack pointer should be aligned. */ | |
19fb36e3 AM |
725 | #define STACK_BOUNDARY \ |
726 | ((TARGET_32BIT && !TARGET_ALTIVEC && !TARGET_ALTIVEC_ABI) ? 64 : 128) | |
f045b2c9 RS |
727 | |
728 | /* Allocation boundary (in *bits*) for the code of a function. */ | |
729 | #define FUNCTION_BOUNDARY 32 | |
730 | ||
731 | /* No data type wants to be aligned rounder than this. */ | |
0ac081f6 AH |
732 | #define BIGGEST_ALIGNMENT 128 |
733 | ||
734 | /* A C expression to compute the alignment for a variables in the | |
735 | local store. TYPE is the data type, and ALIGN is the alignment | |
736 | that the object would ordinarily have. */ | |
737 | #define LOCAL_ALIGNMENT(TYPE, ALIGN) \ | |
a3170dc6 AH |
738 | ((TARGET_ALTIVEC && TREE_CODE (TYPE) == VECTOR_TYPE) ? 128 : \ |
739 | (TARGET_SPE && TREE_CODE (TYPE) == VECTOR_TYPE) ? 64 : ALIGN) | |
b73fd26c | 740 | |
f045b2c9 RS |
741 | /* Alignment of field after `int : 0' in a structure. */ |
742 | #define EMPTY_FIELD_BOUNDARY 32 | |
743 | ||
744 | /* Every structure's size must be a multiple of this. */ | |
745 | #define STRUCTURE_SIZE_BOUNDARY 8 | |
746 | ||
a3170dc6 AH |
747 | /* Return 1 if a structure or array containing FIELD should be |
748 | accessed using `BLKMODE'. | |
749 | ||
750 | For the SPE, simd types are V2SI, and gcc can be tempted to put the | |
751 | entire thing in a DI and use subregs to access the internals. | |
752 | store_bit_field() will force (subreg:DI (reg:V2SI x))'s to the | |
753 | back-end. Because a single GPR can hold a V2SI, but not a DI, the | |
754 | best thing to do is set structs to BLKmode and avoid Severe Tire | |
755 | Damage. */ | |
756 | #define MEMBER_TYPE_FORCES_BLK(FIELD, MODE) \ | |
757 | (TARGET_SPE && TREE_CODE (TREE_TYPE (FIELD)) == VECTOR_TYPE) | |
758 | ||
43a88a8c | 759 | /* A bit-field declared as `int' forces `int' alignment for the struct. */ |
f045b2c9 RS |
760 | #define PCC_BITFIELD_TYPE_MATTERS 1 |
761 | ||
69ef87e2 AH |
762 | /* Make strings word-aligned so strcpy from constants will be faster. |
763 | Make vector constants quadword aligned. */ | |
764 | #define CONSTANT_ALIGNMENT(EXP, ALIGN) \ | |
765 | (TREE_CODE (EXP) == STRING_CST \ | |
766 | && (ALIGN) < BITS_PER_WORD \ | |
767 | ? BITS_PER_WORD \ | |
768 | : (ALIGN)) | |
f045b2c9 | 769 | |
0ac081f6 AH |
770 | /* Make arrays of chars word-aligned for the same reasons. |
771 | Align vectors to 128 bits. */ | |
f045b2c9 | 772 | #define DATA_ALIGNMENT(TYPE, ALIGN) \ |
a3170dc6 | 773 | (TREE_CODE (TYPE) == VECTOR_TYPE ? (TARGET_SPE_ABI ? 64 : 128) \ |
0ac081f6 | 774 | : TREE_CODE (TYPE) == ARRAY_TYPE \ |
f045b2c9 RS |
775 | && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \ |
776 | && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN)) | |
777 | ||
a0ab749a | 778 | /* Nonzero if move instructions will actually fail to work |
f045b2c9 | 779 | when given unaligned data. */ |
fdaff8ba | 780 | #define STRICT_ALIGNMENT 0 |
e1565e65 DE |
781 | |
782 | /* Define this macro to be the value 1 if unaligned accesses have a cost | |
783 | many times greater than aligned accesses, for example if they are | |
784 | emulated in a trap handler. */ | |
41543739 GK |
785 | #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) \ |
786 | (STRICT_ALIGNMENT \ | |
fcce224d DE |
787 | || (((MODE) == SFmode || (MODE) == DFmode || (MODE) == TFmode \ |
788 | || (MODE) == DImode) \ | |
41543739 | 789 | && (ALIGN) < 32)) |
f045b2c9 RS |
790 | \f |
791 | /* Standard register usage. */ | |
792 | ||
793 | /* Number of actual hardware registers. | |
794 | The hardware registers are assigned numbers for the compiler | |
795 | from 0 to just below FIRST_PSEUDO_REGISTER. | |
796 | All registers that the compiler knows about must be given numbers, | |
797 | even those that are not normally considered general registers. | |
798 | ||
799 | RS/6000 has 32 fixed-point registers, 32 floating-point registers, | |
800 | an MQ register, a count register, a link register, and 8 condition | |
07488f32 ZW |
801 | register fields, which we view here as separate registers. AltiVec |
802 | adds 32 vector registers and a VRsave register. | |
f045b2c9 RS |
803 | |
804 | In addition, the difference between the frame and argument pointers is | |
805 | a function of the number of registers saved, so we need to have a | |
806 | register for AP that will later be eliminated in favor of SP or FP. | |
802a0058 | 807 | This is a normal register, but it is fixed. |
f045b2c9 | 808 | |
802a0058 MM |
809 | We also create a pseudo register for float/int conversions, that will |
810 | really represent the memory location used. It is represented here as | |
811 | a register, in order to work around problems in allocating stack storage | |
812 | in inline functions. */ | |
813 | ||
a3170dc6 | 814 | #define FIRST_PSEUDO_REGISTER 113 |
f045b2c9 | 815 | |
d6a7951f | 816 | /* This must be included for pre gcc 3.0 glibc compatibility. */ |
7d5f33bc | 817 | #define PRE_GCC3_DWARF_FRAME_REGISTERS 77 |
62153b61 | 818 | |
93c9d1ba | 819 | /* Add 32 dwarf columns for synthetic SPE registers. */ |
c19de7aa AH |
820 | #define DWARF_FRAME_REGISTERS (FIRST_PSEUDO_REGISTER + 32) |
821 | ||
93c9d1ba AM |
822 | /* The SPE has an additional 32 synthetic registers, with DWARF debug |
823 | info numbering for these registers starting at 1200. While eh_frame | |
824 | register numbering need not be the same as the debug info numbering, | |
825 | we choose to number these regs for eh_frame at 1200 too. This allows | |
826 | future versions of the rs6000 backend to add hard registers and | |
827 | continue to use the gcc hard register numbering for eh_frame. If the | |
828 | extra SPE registers in eh_frame were numbered starting from the | |
829 | current value of FIRST_PSEUDO_REGISTER, then if FIRST_PSEUDO_REGISTER | |
830 | changed we'd need to introduce a mapping in DWARF_FRAME_REGNUM to | |
831 | avoid invalidating older SPE eh_frame info. | |
832 | ||
833 | We must map them here to avoid huge unwinder tables mostly consisting | |
834 | of unused space. */ | |
835 | #define DWARF_REG_TO_UNWIND_COLUMN(r) \ | |
836 | ((r) > 1200 ? ((r) - 1200 + FIRST_PSEUDO_REGISTER) : (r)) | |
837 | ||
838 | /* Use gcc hard register numbering for eh_frame. */ | |
839 | #define DWARF_FRAME_REGNUM(REGNO) (REGNO) | |
41f3a930 | 840 | |
f045b2c9 RS |
841 | /* 1 for registers that have pervasive standard uses |
842 | and are not available for the register allocator. | |
843 | ||
5dead3e5 DJ |
844 | On RS/6000, r1 is used for the stack. On Darwin, r2 is available |
845 | as a local register; for all other OS's r2 is the TOC pointer. | |
f045b2c9 | 846 | |
a127c4e5 RK |
847 | cr5 is not supposed to be used. |
848 | ||
849 | On System V implementations, r13 is fixed and not available for use. */ | |
850 | ||
f045b2c9 | 851 | #define FIXED_REGISTERS \ |
5dead3e5 | 852 | {0, 1, FIXED_R2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, FIXED_R13, 0, 0, \ |
f045b2c9 RS |
853 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ |
854 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
855 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
0ac081f6 AH |
856 | 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 1, \ |
857 | /* AltiVec registers. */ \ | |
858 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
859 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
5f004351 | 860 | 1, 1 \ |
a3170dc6 | 861 | , 1, 1 \ |
0ac081f6 | 862 | } |
f045b2c9 RS |
863 | |
864 | /* 1 for registers not available across function calls. | |
865 | These must include the FIXED_REGISTERS and also any | |
866 | registers that can be used without being saved. | |
867 | The latter must include the registers where values are returned | |
868 | and the register where structure-value addresses are passed. | |
869 | Aside from that, you can include as many other registers as you like. */ | |
870 | ||
871 | #define CALL_USED_REGISTERS \ | |
a127c4e5 | 872 | {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, FIXED_R13, 0, 0, \ |
f045b2c9 RS |
873 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ |
874 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, \ | |
875 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
0ac081f6 AH |
876 | 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, \ |
877 | /* AltiVec registers. */ \ | |
878 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
879 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
5f004351 | 880 | 1, 1 \ |
a3170dc6 | 881 | , 1, 1 \ |
0ac081f6 AH |
882 | } |
883 | ||
289e96b2 AH |
884 | /* Like `CALL_USED_REGISTERS' except this macro doesn't require that |
885 | the entire set of `FIXED_REGISTERS' be included. | |
886 | (`CALL_USED_REGISTERS' must be a superset of `FIXED_REGISTERS'). | |
887 | This macro is optional. If not specified, it defaults to the value | |
888 | of `CALL_USED_REGISTERS'. */ | |
889 | ||
890 | #define CALL_REALLY_USED_REGISTERS \ | |
891 | {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, FIXED_R13, 0, 0, \ | |
892 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
893 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, \ | |
894 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
895 | 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, \ | |
896 | /* AltiVec registers. */ \ | |
897 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
898 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
5f004351 | 899 | 0, 0 \ |
a3170dc6 | 900 | , 0, 0 \ |
289e96b2 | 901 | } |
f045b2c9 | 902 | |
9ebbca7d GK |
903 | #define MQ_REGNO 64 |
904 | #define CR0_REGNO 68 | |
905 | #define CR1_REGNO 69 | |
906 | #define CR2_REGNO 70 | |
907 | #define CR3_REGNO 71 | |
908 | #define CR4_REGNO 72 | |
909 | #define MAX_CR_REGNO 75 | |
910 | #define XER_REGNO 76 | |
0ac081f6 AH |
911 | #define FIRST_ALTIVEC_REGNO 77 |
912 | #define LAST_ALTIVEC_REGNO 108 | |
28bcfd4d | 913 | #define TOTAL_ALTIVEC_REGS (LAST_ALTIVEC_REGNO - FIRST_ALTIVEC_REGNO + 1) |
0ac081f6 | 914 | #define VRSAVE_REGNO 109 |
5f004351 | 915 | #define VSCR_REGNO 110 |
a3170dc6 AH |
916 | #define SPE_ACC_REGNO 111 |
917 | #define SPEFSCR_REGNO 112 | |
9ebbca7d | 918 | |
f045b2c9 RS |
919 | /* List the order in which to allocate registers. Each register must be |
920 | listed once, even those in FIXED_REGISTERS. | |
921 | ||
922 | We allocate in the following order: | |
923 | fp0 (not saved or used for anything) | |
924 | fp13 - fp2 (not saved; incoming fp arg registers) | |
925 | fp1 (not saved; return value) | |
926 | fp31 - fp14 (saved; order given to save least number) | |
5accd822 DE |
927 | cr7, cr6 (not saved or special) |
928 | cr1 (not saved, but used for FP operations) | |
f045b2c9 | 929 | cr0 (not saved, but used for arithmetic operations) |
5accd822 | 930 | cr4, cr3, cr2 (saved) |
f045b2c9 RS |
931 | r0 (not saved; cannot be base reg) |
932 | r9 (not saved; best for TImode) | |
933 | r11, r10, r8-r4 (not saved; highest used first to make less conflict) | |
934 | r3 (not saved; return value register) | |
935 | r31 - r13 (saved; order given to save least number) | |
936 | r12 (not saved; if used for DImode or DFmode would use r13) | |
937 | mq (not saved; best to use it if we can) | |
938 | ctr (not saved; when we have the choice ctr is better) | |
939 | lr (saved) | |
5f004351 | 940 | cr5, r1, r2, ap, xer, vrsave, vscr (fixed) |
a3170dc6 | 941 | spe_acc, spefscr (fixed) |
0ac081f6 AH |
942 | |
943 | AltiVec registers: | |
944 | v0 - v1 (not saved or used for anything) | |
945 | v13 - v3 (not saved; incoming vector arg registers) | |
946 | v2 (not saved; incoming vector arg reg; return value) | |
947 | v19 - v14 (not saved or used for anything) | |
948 | v31 - v20 (saved; order given to save least number) | |
949 | */ | |
950 | ||
6b13641d DJ |
951 | #if FIXED_R2 == 1 |
952 | #define MAYBE_R2_AVAILABLE | |
953 | #define MAYBE_R2_FIXED 2, | |
954 | #else | |
955 | #define MAYBE_R2_AVAILABLE 2, | |
956 | #define MAYBE_R2_FIXED | |
957 | #endif | |
f045b2c9 RS |
958 | |
959 | #define REG_ALLOC_ORDER \ | |
960 | {32, \ | |
961 | 45, 44, 43, 42, 41, 40, 39, 38, 37, 36, 35, 34, \ | |
962 | 33, \ | |
963 | 63, 62, 61, 60, 59, 58, 57, 56, 55, 54, 53, 52, 51, \ | |
964 | 50, 49, 48, 47, 46, \ | |
5accd822 | 965 | 75, 74, 69, 68, 72, 71, 70, \ |
6b13641d | 966 | 0, MAYBE_R2_AVAILABLE \ |
f045b2c9 RS |
967 | 9, 11, 10, 8, 7, 6, 5, 4, \ |
968 | 3, \ | |
969 | 31, 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, 20, 19, \ | |
970 | 18, 17, 16, 15, 14, 13, 12, \ | |
971 | 64, 66, 65, \ | |
6b13641d | 972 | 73, 1, MAYBE_R2_FIXED 67, 76, \ |
0ac081f6 AH |
973 | /* AltiVec registers. */ \ |
974 | 77, 78, \ | |
975 | 90, 89, 88, 87, 86, 85, 84, 83, 82, 81, 80, \ | |
976 | 79, \ | |
977 | 96, 95, 94, 93, 92, 91, \ | |
58568475 | 978 | 108, 107, 106, 105, 104, 103, 102, 101, 100, 99, 98, \ |
5f004351 | 979 | 97, 109, 110 \ |
a3170dc6 | 980 | , 111, 112 \ |
0ac081f6 | 981 | } |
f045b2c9 RS |
982 | |
983 | /* True if register is floating-point. */ | |
984 | #define FP_REGNO_P(N) ((N) >= 32 && (N) <= 63) | |
985 | ||
986 | /* True if register is a condition register. */ | |
987 | #define CR_REGNO_P(N) ((N) >= 68 && (N) <= 75) | |
988 | ||
815cdc52 MM |
989 | /* True if register is a condition register, but not cr0. */ |
990 | #define CR_REGNO_NOT_CR0_P(N) ((N) >= 69 && (N) <= 75) | |
991 | ||
f045b2c9 | 992 | /* True if register is an integer register. */ |
9ebbca7d | 993 | #define INT_REGNO_P(N) ((N) <= 31 || (N) == ARG_POINTER_REGNUM) |
f045b2c9 | 994 | |
a3170dc6 AH |
995 | /* SPE SIMD registers are just the GPRs. */ |
996 | #define SPE_SIMD_REGNO_P(N) ((N) <= 31) | |
997 | ||
0d86f538 | 998 | /* True if register is the XER register. */ |
9ebbca7d | 999 | #define XER_REGNO_P(N) ((N) == XER_REGNO) |
802a0058 | 1000 | |
0ac081f6 AH |
1001 | /* True if register is an AltiVec register. */ |
1002 | #define ALTIVEC_REGNO_P(N) ((N) >= FIRST_ALTIVEC_REGNO && (N) <= LAST_ALTIVEC_REGNO) | |
1003 | ||
f045b2c9 | 1004 | /* Return number of consecutive hard regs needed starting at reg REGNO |
d8ecbcdb AH |
1005 | to hold something of mode MODE. */ |
1006 | ||
1007 | #define HARD_REGNO_NREGS(REGNO, MODE) rs6000_hard_regno_nregs ((REGNO), (MODE)) | |
0e67400a FJ |
1008 | |
1009 | #define HARD_REGNO_CALL_PART_CLOBBERED(REGNO, MODE) \ | |
1010 | ((TARGET_32BIT && TARGET_POWERPC64 \ | |
1011 | && (MODE == DImode || MODE == DFmode) \ | |
1012 | && INT_REGNO_P (REGNO)) ? 1 : 0) | |
f045b2c9 | 1013 | |
0ac081f6 | 1014 | #define ALTIVEC_VECTOR_MODE(MODE) \ |
cb2a532e AH |
1015 | ((MODE) == V16QImode \ |
1016 | || (MODE) == V8HImode \ | |
1017 | || (MODE) == V4SFmode \ | |
6e1f54e2 | 1018 | || (MODE) == V4SImode) |
0ac081f6 | 1019 | |
a3170dc6 AH |
1020 | #define SPE_VECTOR_MODE(MODE) \ |
1021 | ((MODE) == V4HImode \ | |
1022 | || (MODE) == V2SFmode \ | |
00a892b8 | 1023 | || (MODE) == V1DImode \ |
a3170dc6 AH |
1024 | || (MODE) == V2SImode) |
1025 | ||
0ac081f6 AH |
1026 | /* Define this macro to be nonzero if the port is prepared to handle |
1027 | insns involving vector mode MODE. At the very least, it must have | |
1028 | move patterns for this mode. */ | |
1029 | ||
a3170dc6 AH |
1030 | #define VECTOR_MODE_SUPPORTED_P(MODE) \ |
1031 | ((TARGET_SPE && SPE_VECTOR_MODE (MODE)) \ | |
1032 | || (TARGET_ALTIVEC && ALTIVEC_VECTOR_MODE (MODE))) | |
0ac081f6 | 1033 | |
0d1fbc8c AH |
1034 | /* Value is TRUE if hard register REGNO can hold a value of |
1035 | machine-mode MODE. */ | |
1036 | #define HARD_REGNO_MODE_OK(REGNO, MODE) \ | |
1037 | rs6000_hard_regno_mode_ok_p[(int)(MODE)][REGNO] | |
f045b2c9 RS |
1038 | |
1039 | /* Value is 1 if it is a good idea to tie two pseudo registers | |
1040 | when one has mode MODE1 and one has mode MODE2. | |
1041 | If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, | |
1042 | for any hard reg, then this must be 0 for correct output. */ | |
1043 | #define MODES_TIEABLE_P(MODE1, MODE2) \ | |
1044 | (GET_MODE_CLASS (MODE1) == MODE_FLOAT \ | |
1045 | ? GET_MODE_CLASS (MODE2) == MODE_FLOAT \ | |
1046 | : GET_MODE_CLASS (MODE2) == MODE_FLOAT \ | |
1047 | ? GET_MODE_CLASS (MODE1) == MODE_FLOAT \ | |
1048 | : GET_MODE_CLASS (MODE1) == MODE_CC \ | |
1049 | ? GET_MODE_CLASS (MODE2) == MODE_CC \ | |
1050 | : GET_MODE_CLASS (MODE2) == MODE_CC \ | |
1051 | ? GET_MODE_CLASS (MODE1) == MODE_CC \ | |
4dcc01f3 AH |
1052 | : SPE_VECTOR_MODE (MODE1) \ |
1053 | ? SPE_VECTOR_MODE (MODE2) \ | |
1054 | : SPE_VECTOR_MODE (MODE2) \ | |
1055 | ? SPE_VECTOR_MODE (MODE1) \ | |
0ac081f6 AH |
1056 | : ALTIVEC_VECTOR_MODE (MODE1) \ |
1057 | ? ALTIVEC_VECTOR_MODE (MODE2) \ | |
1058 | : ALTIVEC_VECTOR_MODE (MODE2) \ | |
1059 | ? ALTIVEC_VECTOR_MODE (MODE1) \ | |
f045b2c9 RS |
1060 | : 1) |
1061 | ||
c8ae788f SB |
1062 | /* Post-reload, we can't use any new AltiVec registers, as we already |
1063 | emitted the vrsave mask. */ | |
1064 | ||
1065 | #define HARD_REGNO_RENAME_OK(SRC, DST) \ | |
1066 | (! ALTIVEC_REGNO_P (DST) || regs_ever_live[DST]) | |
1067 | ||
f045b2c9 | 1068 | /* A C expression returning the cost of moving data from a register of class |
34bb030a | 1069 | CLASS1 to one of CLASS2. */ |
f045b2c9 | 1070 | |
34bb030a | 1071 | #define REGISTER_MOVE_COST rs6000_register_move_cost |
f045b2c9 | 1072 | |
34bb030a DE |
1073 | /* A C expressions returning the cost of moving data of MODE from a register to |
1074 | or from memory. */ | |
f045b2c9 | 1075 | |
34bb030a | 1076 | #define MEMORY_MOVE_COST rs6000_memory_move_cost |
f045b2c9 RS |
1077 | |
1078 | /* Specify the cost of a branch insn; roughly the number of extra insns that | |
1079 | should be added to avoid a branch. | |
1080 | ||
ef457bda | 1081 | Set this to 3 on the RS/6000 since that is roughly the average cost of an |
f045b2c9 RS |
1082 | unscheduled conditional branch. */ |
1083 | ||
ef457bda | 1084 | #define BRANCH_COST 3 |
f045b2c9 | 1085 | |
85e50b6b DE |
1086 | /* Override BRANCH_COST heuristic which empirically produces worse |
1087 | performance for fold_range_test(). */ | |
1088 | ||
1089 | #define RANGE_TEST_NON_SHORT_CIRCUIT 0 | |
a3170dc6 AH |
1090 | |
1091 | /* A fixed register used at prologue and epilogue generation to fix | |
1092 | addressing modes. The SPE needs heavy addressing fixes at the last | |
1093 | minute, and it's best to save a register for it. | |
1094 | ||
1095 | AltiVec also needs fixes, but we've gotten around using r11, which | |
1096 | is actually wrong because when use_backchain_to_restore_sp is true, | |
1097 | we end up clobbering r11. | |
1098 | ||
1099 | The AltiVec case needs to be fixed. Dunno if we should break ABI | |
b6d08ca1 | 1100 | compatibility and reserve a register for it as well.. */ |
a3170dc6 AH |
1101 | |
1102 | #define FIXED_SCRATCH (TARGET_SPE ? 14 : 11) | |
1103 | ||
2aa4498c AH |
1104 | /* Define this macro to change register usage conditional on target |
1105 | flags. */ | |
f85f4585 | 1106 | |
2aa4498c | 1107 | #define CONDITIONAL_REGISTER_USAGE rs6000_conditional_register_usage () |
6febd581 | 1108 | |
f045b2c9 RS |
1109 | /* Specify the registers used for certain standard purposes. |
1110 | The values of these macros are register numbers. */ | |
1111 | ||
1112 | /* RS/6000 pc isn't overloaded on a register that the compiler knows about. */ | |
1113 | /* #define PC_REGNUM */ | |
1114 | ||
1115 | /* Register to use for pushing function arguments. */ | |
1116 | #define STACK_POINTER_REGNUM 1 | |
1117 | ||
1118 | /* Base register for access to local variables of the function. */ | |
1119 | #define FRAME_POINTER_REGNUM 31 | |
1120 | ||
1121 | /* Value should be nonzero if functions must have frame pointers. | |
1122 | Zero means the frame pointer need not be set up (and parms | |
1123 | may be accessed via the stack pointer) in functions that seem suitable. | |
1124 | This is computed in `reload', in reload1.c. */ | |
1125 | #define FRAME_POINTER_REQUIRED 0 | |
1126 | ||
1127 | /* Base register for access to arguments of the function. */ | |
1128 | #define ARG_POINTER_REGNUM 67 | |
1129 | ||
1130 | /* Place to put static chain when calling a function that requires it. */ | |
1131 | #define STATIC_CHAIN_REGNUM 11 | |
1132 | ||
82e41834 | 1133 | /* Link register number. */ |
9ebbca7d | 1134 | #define LINK_REGISTER_REGNUM 65 |
b6c9286a | 1135 | |
82e41834 | 1136 | /* Count register number. */ |
9ebbca7d | 1137 | #define COUNT_REGISTER_REGNUM 66 |
f045b2c9 RS |
1138 | \f |
1139 | /* Define the classes of registers for register constraints in the | |
1140 | machine description. Also define ranges of constants. | |
1141 | ||
1142 | One of the classes must always be named ALL_REGS and include all hard regs. | |
1143 | If there is more than one class, another class must be named NO_REGS | |
1144 | and contain no registers. | |
1145 | ||
1146 | The name GENERAL_REGS must be the name of a class (or an alias for | |
1147 | another name such as ALL_REGS). This is the class of registers | |
1148 | that is allowed by "g" or "r" in a register constraint. | |
1149 | Also, registers outside this class are allocated only when | |
1150 | instructions express preferences for them. | |
1151 | ||
1152 | The classes must be numbered in nondecreasing order; that is, | |
1153 | a larger-numbered class must never be contained completely | |
1154 | in a smaller-numbered class. | |
1155 | ||
1156 | For any two classes, it is very desirable that there be another | |
1157 | class that represents their union. */ | |
c81bebd7 | 1158 | |
f045b2c9 RS |
1159 | /* The RS/6000 has three types of registers, fixed-point, floating-point, |
1160 | and condition registers, plus three special registers, MQ, CTR, and the | |
07488f32 | 1161 | link register. AltiVec adds a vector register class. |
f045b2c9 RS |
1162 | |
1163 | However, r0 is special in that it cannot be used as a base register. | |
1164 | So make a class for registers valid as base registers. | |
1165 | ||
1166 | Also, cr0 is the only condition code register that can be used in | |
0d86f538 | 1167 | arithmetic insns, so make a separate class for it. */ |
f045b2c9 | 1168 | |
ebedb4dd MM |
1169 | enum reg_class |
1170 | { | |
1171 | NO_REGS, | |
ebedb4dd MM |
1172 | BASE_REGS, |
1173 | GENERAL_REGS, | |
1174 | FLOAT_REGS, | |
0ac081f6 AH |
1175 | ALTIVEC_REGS, |
1176 | VRSAVE_REGS, | |
5f004351 | 1177 | VSCR_REGS, |
a3170dc6 AH |
1178 | SPE_ACC_REGS, |
1179 | SPEFSCR_REGS, | |
ebedb4dd MM |
1180 | NON_SPECIAL_REGS, |
1181 | MQ_REGS, | |
1182 | LINK_REGS, | |
1183 | CTR_REGS, | |
1184 | LINK_OR_CTR_REGS, | |
1185 | SPECIAL_REGS, | |
1186 | SPEC_OR_GEN_REGS, | |
1187 | CR0_REGS, | |
ebedb4dd MM |
1188 | CR_REGS, |
1189 | NON_FLOAT_REGS, | |
9ebbca7d | 1190 | XER_REGS, |
ebedb4dd MM |
1191 | ALL_REGS, |
1192 | LIM_REG_CLASSES | |
1193 | }; | |
f045b2c9 RS |
1194 | |
1195 | #define N_REG_CLASSES (int) LIM_REG_CLASSES | |
1196 | ||
82e41834 | 1197 | /* Give names of register classes as strings for dump file. */ |
f045b2c9 | 1198 | |
ebedb4dd MM |
1199 | #define REG_CLASS_NAMES \ |
1200 | { \ | |
1201 | "NO_REGS", \ | |
ebedb4dd MM |
1202 | "BASE_REGS", \ |
1203 | "GENERAL_REGS", \ | |
1204 | "FLOAT_REGS", \ | |
0ac081f6 AH |
1205 | "ALTIVEC_REGS", \ |
1206 | "VRSAVE_REGS", \ | |
5f004351 | 1207 | "VSCR_REGS", \ |
a3170dc6 AH |
1208 | "SPE_ACC_REGS", \ |
1209 | "SPEFSCR_REGS", \ | |
ebedb4dd MM |
1210 | "NON_SPECIAL_REGS", \ |
1211 | "MQ_REGS", \ | |
1212 | "LINK_REGS", \ | |
1213 | "CTR_REGS", \ | |
1214 | "LINK_OR_CTR_REGS", \ | |
1215 | "SPECIAL_REGS", \ | |
1216 | "SPEC_OR_GEN_REGS", \ | |
1217 | "CR0_REGS", \ | |
ebedb4dd MM |
1218 | "CR_REGS", \ |
1219 | "NON_FLOAT_REGS", \ | |
9ebbca7d | 1220 | "XER_REGS", \ |
ebedb4dd MM |
1221 | "ALL_REGS" \ |
1222 | } | |
f045b2c9 RS |
1223 | |
1224 | /* Define which registers fit in which classes. | |
1225 | This is an initializer for a vector of HARD_REG_SET | |
1226 | of length N_REG_CLASSES. */ | |
1227 | ||
0ac081f6 AH |
1228 | #define REG_CLASS_CONTENTS \ |
1229 | { \ | |
1230 | { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \ | |
1231 | { 0xfffffffe, 0x00000000, 0x00000008, 0x00000000 }, /* BASE_REGS */ \ | |
1232 | { 0xffffffff, 0x00000000, 0x00000008, 0x00000000 }, /* GENERAL_REGS */ \ | |
1233 | { 0x00000000, 0xffffffff, 0x00000000, 0x00000000 }, /* FLOAT_REGS */ \ | |
089a05b8 SS |
1234 | { 0x00000000, 0x00000000, 0xffffe000, 0x00001fff }, /* ALTIVEC_REGS */ \ |
1235 | { 0x00000000, 0x00000000, 0x00000000, 0x00002000 }, /* VRSAVE_REGS */ \ | |
5f004351 | 1236 | { 0x00000000, 0x00000000, 0x00000000, 0x00004000 }, /* VSCR_REGS */ \ |
a3170dc6 AH |
1237 | { 0x00000000, 0x00000000, 0x00000000, 0x00008000 }, /* SPE_ACC_REGS */ \ |
1238 | { 0x00000000, 0x00000000, 0x00000000, 0x00010000 }, /* SPEFSCR_REGS */ \ | |
0ac081f6 AH |
1239 | { 0xffffffff, 0xffffffff, 0x00000008, 0x00000000 }, /* NON_SPECIAL_REGS */ \ |
1240 | { 0x00000000, 0x00000000, 0x00000001, 0x00000000 }, /* MQ_REGS */ \ | |
1241 | { 0x00000000, 0x00000000, 0x00000002, 0x00000000 }, /* LINK_REGS */ \ | |
1242 | { 0x00000000, 0x00000000, 0x00000004, 0x00000000 }, /* CTR_REGS */ \ | |
1243 | { 0x00000000, 0x00000000, 0x00000006, 0x00000000 }, /* LINK_OR_CTR_REGS */ \ | |
a004eb82 | 1244 | { 0x00000000, 0x00000000, 0x00000007, 0x00002000 }, /* SPECIAL_REGS */ \ |
0ac081f6 AH |
1245 | { 0xffffffff, 0x00000000, 0x0000000f, 0x00000000 }, /* SPEC_OR_GEN_REGS */ \ |
1246 | { 0x00000000, 0x00000000, 0x00000010, 0x00000000 }, /* CR0_REGS */ \ | |
1247 | { 0x00000000, 0x00000000, 0x00000ff0, 0x00000000 }, /* CR_REGS */ \ | |
089a05b8 SS |
1248 | { 0xffffffff, 0x00000000, 0x0000efff, 0x00000000 }, /* NON_FLOAT_REGS */ \ |
1249 | { 0x00000000, 0x00000000, 0x00001000, 0x00000000 }, /* XER_REGS */ \ | |
1250 | { 0xffffffff, 0xffffffff, 0xffffffff, 0x00003fff } /* ALL_REGS */ \ | |
ebedb4dd | 1251 | } |
f045b2c9 RS |
1252 | |
1253 | /* The same information, inverted: | |
1254 | Return the class number of the smallest class containing | |
1255 | reg number REGNO. This could be a conditional expression | |
1256 | or could index an array. */ | |
1257 | ||
0d86f538 GK |
1258 | #define REGNO_REG_CLASS(REGNO) \ |
1259 | ((REGNO) == 0 ? GENERAL_REGS \ | |
1260 | : (REGNO) < 32 ? BASE_REGS \ | |
1261 | : FP_REGNO_P (REGNO) ? FLOAT_REGS \ | |
0ac081f6 | 1262 | : ALTIVEC_REGNO_P (REGNO) ? ALTIVEC_REGS \ |
0d86f538 GK |
1263 | : (REGNO) == CR0_REGNO ? CR0_REGS \ |
1264 | : CR_REGNO_P (REGNO) ? CR_REGS \ | |
1265 | : (REGNO) == MQ_REGNO ? MQ_REGS \ | |
1266 | : (REGNO) == LINK_REGISTER_REGNUM ? LINK_REGS \ | |
1267 | : (REGNO) == COUNT_REGISTER_REGNUM ? CTR_REGS \ | |
1268 | : (REGNO) == ARG_POINTER_REGNUM ? BASE_REGS \ | |
1269 | : (REGNO) == XER_REGNO ? XER_REGS \ | |
0ac081f6 | 1270 | : (REGNO) == VRSAVE_REGNO ? VRSAVE_REGS \ |
5f004351 | 1271 | : (REGNO) == VSCR_REGNO ? VRSAVE_REGS \ |
a3170dc6 AH |
1272 | : (REGNO) == SPE_ACC_REGNO ? SPE_ACC_REGS \ |
1273 | : (REGNO) == SPEFSCR_REGNO ? SPEFSCR_REGS \ | |
f045b2c9 RS |
1274 | : NO_REGS) |
1275 | ||
1276 | /* The class value for index registers, and the one for base regs. */ | |
1277 | #define INDEX_REG_CLASS GENERAL_REGS | |
1278 | #define BASE_REG_CLASS BASE_REGS | |
1279 | ||
1280 | /* Get reg_class from a letter such as appears in the machine description. */ | |
1281 | ||
1282 | #define REG_CLASS_FROM_LETTER(C) \ | |
1283 | ((C) == 'f' ? FLOAT_REGS \ | |
1284 | : (C) == 'b' ? BASE_REGS \ | |
1285 | : (C) == 'h' ? SPECIAL_REGS \ | |
1286 | : (C) == 'q' ? MQ_REGS \ | |
1287 | : (C) == 'c' ? CTR_REGS \ | |
1288 | : (C) == 'l' ? LINK_REGS \ | |
0ac081f6 | 1289 | : (C) == 'v' ? ALTIVEC_REGS \ |
f045b2c9 RS |
1290 | : (C) == 'x' ? CR0_REGS \ |
1291 | : (C) == 'y' ? CR_REGS \ | |
9ebbca7d | 1292 | : (C) == 'z' ? XER_REGS \ |
f045b2c9 RS |
1293 | : NO_REGS) |
1294 | ||
1295 | /* The letters I, J, K, L, M, N, and P in a register constraint string | |
1296 | can be used to stand for particular ranges of immediate operands. | |
1297 | This macro defines what the ranges are. | |
1298 | C is the letter, and VALUE is a constant value. | |
1299 | Return 1 if VALUE is in the range specified by C. | |
1300 | ||
9615f239 | 1301 | `I' is a signed 16-bit constant |
a0ab749a KH |
1302 | `J' is a constant with only the high-order 16 bits nonzero |
1303 | `K' is a constant with only the low-order 16 bits nonzero | |
9615f239 | 1304 | `L' is a signed 16-bit constant shifted left 16 bits |
f045b2c9 | 1305 | `M' is a constant that is greater than 31 |
2bfcf297 | 1306 | `N' is a positive constant that is an exact power of two |
f045b2c9 RS |
1307 | `O' is the constant zero |
1308 | `P' is a constant whose negation is a signed 16-bit constant */ | |
1309 | ||
5b6f7b96 RK |
1310 | #define CONST_OK_FOR_LETTER_P(VALUE, C) \ |
1311 | ( (C) == 'I' ? (unsigned HOST_WIDE_INT) ((VALUE) + 0x8000) < 0x10000 \ | |
0858c623 | 1312 | : (C) == 'J' ? ((VALUE) & (~ (unsigned HOST_WIDE_INT) 0xffff0000)) == 0 \ |
a260abc9 | 1313 | : (C) == 'K' ? ((VALUE) & (~ (HOST_WIDE_INT) 0xffff)) == 0 \ |
9615f239 DE |
1314 | : (C) == 'L' ? (((VALUE) & 0xffff) == 0 \ |
1315 | && ((VALUE) >> 31 == -1 || (VALUE) >> 31 == 0)) \ | |
5b6f7b96 | 1316 | : (C) == 'M' ? (VALUE) > 31 \ |
2bfcf297 | 1317 | : (C) == 'N' ? (VALUE) > 0 && exact_log2 (VALUE) >= 0 \ |
5b6f7b96 | 1318 | : (C) == 'O' ? (VALUE) == 0 \ |
9615f239 | 1319 | : (C) == 'P' ? (unsigned HOST_WIDE_INT) ((- (VALUE)) + 0x8000) < 0x10000 \ |
f045b2c9 RS |
1320 | : 0) |
1321 | ||
1322 | /* Similar, but for floating constants, and defining letters G and H. | |
1323 | Here VALUE is the CONST_DOUBLE rtx itself. | |
1324 | ||
1325 | We flag for special constants when we can copy the constant into | |
4e74d8ec | 1326 | a general register in two insns for DF/DI and one insn for SF. |
f045b2c9 | 1327 | |
c4c40373 | 1328 | 'H' is used for DI/DF constants that take 3 insns. */ |
4e74d8ec MM |
1329 | |
1330 | #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \ | |
c4c40373 MM |
1331 | ( (C) == 'G' ? (num_insns_constant (VALUE, GET_MODE (VALUE)) \ |
1332 | == ((GET_MODE (VALUE) == SFmode) ? 1 : 2)) \ | |
1333 | : (C) == 'H' ? (num_insns_constant (VALUE, GET_MODE (VALUE)) == 3) \ | |
1334 | : 0) | |
f045b2c9 RS |
1335 | |
1336 | /* Optional extra constraints for this machine. | |
1337 | ||
b6c9286a MM |
1338 | 'Q' means that is a memory operand that is just an offset from a reg. |
1339 | 'R' is for AIX TOC entries. | |
a260abc9 | 1340 | 'S' is a constant that can be placed into a 64-bit mask operand |
b1765bde | 1341 | 'T' is a constant that can be placed into a 32-bit mask operand |
0ba1b2ff | 1342 | 'U' is for V.4 small data references. |
d744e06e | 1343 | 'W' is a vector constant that can be easily generated (no mem refs). |
d2288d5d | 1344 | 'Y' is a indexed or word-aligned displacement memory operand. |
0ba1b2ff | 1345 | 't' is for AND masks that can be performed by two rldic{l,r} insns. */ |
f045b2c9 | 1346 | |
e8a8bc24 RK |
1347 | #define EXTRA_CONSTRAINT(OP, C) \ |
1348 | ((C) == 'Q' ? GET_CODE (OP) == MEM && GET_CODE (XEXP (OP, 0)) == REG \ | |
4d588c14 | 1349 | : (C) == 'R' ? legitimate_constant_pool_address_p (OP) \ |
b1765bde DE |
1350 | : (C) == 'S' ? mask64_operand (OP, DImode) \ |
1351 | : (C) == 'T' ? mask_operand (OP, SImode) \ | |
f607bc57 | 1352 | : (C) == 'U' ? (DEFAULT_ABI == ABI_V4 \ |
c81bebd7 | 1353 | && small_data_operand (OP, GET_MODE (OP))) \ |
0ba1b2ff AM |
1354 | : (C) == 't' ? (mask64_2_operand (OP, DImode) \ |
1355 | && (fixed_regs[CR0_REGNO] \ | |
1356 | || !logical_operand (OP, DImode)) \ | |
1357 | && !mask64_operand (OP, DImode)) \ | |
d744e06e | 1358 | : (C) == 'W' ? (easy_vector_constant (OP, GET_MODE (OP))) \ |
d2288d5d | 1359 | : (C) == 'Y' ? (word_offset_memref_operand (OP, GET_MODE (OP))) \ |
e8a8bc24 | 1360 | : 0) |
f045b2c9 | 1361 | |
59b9a953 | 1362 | /* Define which constraints are memory constraints. Tell reload |
d2288d5d HP |
1363 | that any memory address can be reloaded by copying the |
1364 | memory address into a base register if required. */ | |
1365 | ||
1366 | #define EXTRA_MEMORY_CONSTRAINT(C, STR) \ | |
1367 | ((C) == 'Q' || (C) == 'Y') | |
1368 | ||
f045b2c9 RS |
1369 | /* Given an rtx X being reloaded into a reg required to be |
1370 | in class CLASS, return the class of reg to actually use. | |
1371 | In general this is just CLASS; but on some machines | |
c81bebd7 | 1372 | in some cases it is preferable to use a more restrictive class. |
f045b2c9 RS |
1373 | |
1374 | On the RS/6000, we have to return NO_REGS when we want to reload a | |
1e66d555 GK |
1375 | floating-point CONST_DOUBLE to force it to be copied to memory. |
1376 | ||
1377 | We also don't want to reload integer values into floating-point | |
1378 | registers if we can at all help it. In fact, this can | |
1379 | cause reload to abort, if it tries to generate a reload of CTR | |
1380 | into a FP register and discovers it doesn't have the memory location | |
1381 | required. | |
1382 | ||
1383 | ??? Would it be a good idea to have reload do the converse, that is | |
1384 | try to reload floating modes into FP registers if possible? | |
1385 | */ | |
f045b2c9 | 1386 | |
802a0058 | 1387 | #define PREFERRED_RELOAD_CLASS(X,CLASS) \ |
1e66d555 GK |
1388 | (((GET_CODE (X) == CONST_DOUBLE \ |
1389 | && GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT) \ | |
1390 | ? NO_REGS \ | |
1391 | : (GET_MODE_CLASS (GET_MODE (X)) == MODE_INT \ | |
1392 | && (CLASS) == NON_SPECIAL_REGS) \ | |
1393 | ? GENERAL_REGS \ | |
1394 | : (CLASS))) | |
c81bebd7 | 1395 | |
f045b2c9 RS |
1396 | /* Return the register class of a scratch register needed to copy IN into |
1397 | or out of a register in CLASS in MODE. If it can be done directly, | |
1398 | NO_REGS is returned. */ | |
1399 | ||
1400 | #define SECONDARY_RELOAD_CLASS(CLASS,MODE,IN) \ | |
1401 | secondary_reload_class (CLASS, MODE, IN) | |
1402 | ||
0ac081f6 AH |
1403 | /* If we are copying between FP or AltiVec registers and anything |
1404 | else, we need a memory location. */ | |
7ea555a4 | 1405 | |
0ac081f6 AH |
1406 | #define SECONDARY_MEMORY_NEEDED(CLASS1,CLASS2,MODE) \ |
1407 | ((CLASS1) != (CLASS2) && ((CLASS1) == FLOAT_REGS \ | |
1408 | || (CLASS2) == FLOAT_REGS \ | |
1409 | || (CLASS1) == ALTIVEC_REGS \ | |
1410 | || (CLASS2) == ALTIVEC_REGS)) | |
7ea555a4 | 1411 | |
f045b2c9 RS |
1412 | /* Return the maximum number of consecutive registers |
1413 | needed to represent mode MODE in a register of class CLASS. | |
1414 | ||
1415 | On RS/6000, this is the size of MODE in words, | |
1416 | except in the FP regs, where a single reg is enough for two words. */ | |
802a0058 | 1417 | #define CLASS_MAX_NREGS(CLASS, MODE) \ |
9ebbca7d | 1418 | (((CLASS) == FLOAT_REGS) \ |
2e360ab3 | 1419 | ? ((GET_MODE_SIZE (MODE) + UNITS_PER_FP_WORD - 1) / UNITS_PER_FP_WORD) \ |
c1aa3958 | 1420 | : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) |
580d3230 | 1421 | |
580d3230 | 1422 | |
cff9f8d5 | 1423 | /* Return a class of registers that cannot change FROM mode to TO mode. */ |
02188693 | 1424 | |
a9baceb1 GK |
1425 | #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \ |
1426 | (((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) \ | |
1427 | && GET_MODE_SIZE (FROM) >= 8 && GET_MODE_SIZE (TO) >= 8) \ | |
1428 | ? 0 \ | |
1429 | : GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \ | |
1430 | ? reg_classes_intersect_p (FLOAT_REGS, CLASS) \ | |
28636c6e | 1431 | : (TARGET_SPE && (SPE_VECTOR_MODE (FROM) + SPE_VECTOR_MODE (TO)) == 1) \ |
a9baceb1 | 1432 | ? reg_classes_intersect_p (GENERAL_REGS, CLASS) \ |
b0c42aed | 1433 | : 0) |
02188693 | 1434 | |
f045b2c9 RS |
1435 | /* Stack layout; function entry, exit and calling. */ |
1436 | ||
6b67933e RK |
1437 | /* Enumeration to give which calling sequence to use. */ |
1438 | enum rs6000_abi { | |
1439 | ABI_NONE, | |
1440 | ABI_AIX, /* IBM's AIX */ | |
b6c9286a | 1441 | ABI_V4, /* System V.4/eabi */ |
ee890fe2 | 1442 | ABI_DARWIN /* Apple's Darwin (OS X kernel) */ |
6b67933e RK |
1443 | }; |
1444 | ||
b6c9286a MM |
1445 | extern enum rs6000_abi rs6000_current_abi; /* available for use by subtarget */ |
1446 | ||
f045b2c9 RS |
1447 | /* Define this if pushing a word on the stack |
1448 | makes the stack pointer a smaller address. */ | |
1449 | #define STACK_GROWS_DOWNWARD | |
1450 | ||
327e5343 FJ |
1451 | /* Offsets recorded in opcodes are a multiple of this alignment factor. */ |
1452 | #define DWARF_CIE_DATA_ALIGNMENT (-((int) (TARGET_32BIT ? 4 : 8))) | |
1453 | ||
f045b2c9 RS |
1454 | /* Define this if the nominal address of the stack frame |
1455 | is at the high-address end of the local variables; | |
1456 | that is, each additional local variable allocated | |
1457 | goes at a more negative offset in the frame. | |
1458 | ||
1459 | On the RS/6000, we grow upwards, from the area after the outgoing | |
1460 | arguments. */ | |
1461 | /* #define FRAME_GROWS_DOWNWARD */ | |
1462 | ||
4697a36c | 1463 | /* Size of the outgoing register save area */ |
9ebbca7d | 1464 | #define RS6000_REG_SAVE ((DEFAULT_ABI == ABI_AIX \ |
ee890fe2 | 1465 | || DEFAULT_ABI == ABI_DARWIN) \ |
9ebbca7d GK |
1466 | ? (TARGET_64BIT ? 64 : 32) \ |
1467 | : 0) | |
4697a36c MM |
1468 | |
1469 | /* Size of the fixed area on the stack */ | |
9ebbca7d | 1470 | #define RS6000_SAVE_AREA \ |
50d440bc | 1471 | (((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) ? 24 : 8) \ |
9ebbca7d | 1472 | << (TARGET_64BIT ? 1 : 0)) |
4697a36c | 1473 | |
97f6e72f DE |
1474 | /* MEM representing address to save the TOC register */ |
1475 | #define RS6000_SAVE_TOC gen_rtx_MEM (Pmode, \ | |
1476 | plus_constant (stack_pointer_rtx, \ | |
1477 | (TARGET_32BIT ? 20 : 40))) | |
b6c9286a | 1478 | |
4697a36c MM |
1479 | /* Size of the V.4 varargs area if needed */ |
1480 | #define RS6000_VARARGS_AREA 0 | |
1481 | ||
4697a36c | 1482 | /* Align an address */ |
ed33106f | 1483 | #define RS6000_ALIGN(n,a) (((n) + (a) - 1) & ~((a) - 1)) |
4697a36c MM |
1484 | |
1485 | /* Size of V.4 varargs area in bytes */ | |
1486 | #define RS6000_VARARGS_SIZE \ | |
2f3e5814 | 1487 | ((GP_ARG_NUM_REG * (TARGET_32BIT ? 4 : 8)) + (FP_ARG_NUM_REG * 8) + 8) |
4697a36c | 1488 | |
f045b2c9 RS |
1489 | /* Offset within stack frame to start allocating local variables at. |
1490 | If FRAME_GROWS_DOWNWARD, this is the offset to the END of the | |
1491 | first local allocated. Otherwise, it is the offset to the BEGINNING | |
c81bebd7 | 1492 | of the first local allocated. |
f045b2c9 RS |
1493 | |
1494 | On the RS/6000, the frame pointer is the same as the stack pointer, | |
1495 | except for dynamic allocations. So we start after the fixed area and | |
1496 | outgoing parameter area. */ | |
1497 | ||
802a0058 | 1498 | #define STARTING_FRAME_OFFSET \ |
7b094d6e AH |
1499 | (RS6000_ALIGN (current_function_outgoing_args_size, \ |
1500 | TARGET_ALTIVEC ? 16 : 8) \ | |
802a0058 MM |
1501 | + RS6000_VARARGS_AREA \ |
1502 | + RS6000_SAVE_AREA) | |
1503 | ||
1504 | /* Offset from the stack pointer register to an item dynamically | |
1505 | allocated on the stack, e.g., by `alloca'. | |
1506 | ||
1507 | The default value for this macro is `STACK_POINTER_OFFSET' plus the | |
1508 | length of the outgoing arguments. The default is correct for most | |
1509 | machines. See `function.c' for details. */ | |
1510 | #define STACK_DYNAMIC_OFFSET(FUNDECL) \ | |
7b094d6e AH |
1511 | (RS6000_ALIGN (current_function_outgoing_args_size, \ |
1512 | TARGET_ALTIVEC ? 16 : 8) \ | |
802a0058 | 1513 | + (STACK_POINTER_OFFSET)) |
f045b2c9 RS |
1514 | |
1515 | /* If we generate an insn to push BYTES bytes, | |
1516 | this says how many the stack pointer really advances by. | |
1517 | On RS/6000, don't define this because there are no push insns. */ | |
1518 | /* #define PUSH_ROUNDING(BYTES) */ | |
1519 | ||
1520 | /* Offset of first parameter from the argument pointer register value. | |
1521 | On the RS/6000, we define the argument pointer to the start of the fixed | |
1522 | area. */ | |
4697a36c | 1523 | #define FIRST_PARM_OFFSET(FNDECL) RS6000_SAVE_AREA |
f045b2c9 | 1524 | |
62153b61 JM |
1525 | /* Offset from the argument pointer register value to the top of |
1526 | stack. This is different from FIRST_PARM_OFFSET because of the | |
1527 | register save area. */ | |
1528 | #define ARG_POINTER_CFA_OFFSET(FNDECL) 0 | |
1529 | ||
f045b2c9 RS |
1530 | /* Define this if stack space is still allocated for a parameter passed |
1531 | in a register. The value is the number of bytes allocated to this | |
1532 | area. */ | |
4697a36c | 1533 | #define REG_PARM_STACK_SPACE(FNDECL) RS6000_REG_SAVE |
f045b2c9 RS |
1534 | |
1535 | /* Define this if the above stack space is to be considered part of the | |
1536 | space allocated by the caller. */ | |
1537 | #define OUTGOING_REG_PARM_STACK_SPACE | |
1538 | ||
1539 | /* This is the difference between the logical top of stack and the actual sp. | |
1540 | ||
82e41834 | 1541 | For the RS/6000, sp points past the fixed area. */ |
4697a36c | 1542 | #define STACK_POINTER_OFFSET RS6000_SAVE_AREA |
f045b2c9 RS |
1543 | |
1544 | /* Define this if the maximum size of all the outgoing args is to be | |
1545 | accumulated and pushed during the prologue. The amount can be | |
1546 | found in the variable current_function_outgoing_args_size. */ | |
f73ad30e | 1547 | #define ACCUMULATE_OUTGOING_ARGS 1 |
f045b2c9 RS |
1548 | |
1549 | /* Value is the number of bytes of arguments automatically | |
1550 | popped when returning from a subroutine call. | |
8b109b37 | 1551 | FUNDECL is the declaration node of the function (as a tree), |
f045b2c9 RS |
1552 | FUNTYPE is the data type of the function (as a tree), |
1553 | or for a library call it is an identifier node for the subroutine name. | |
1554 | SIZE is the number of bytes of arguments passed on the stack. */ | |
1555 | ||
8b109b37 | 1556 | #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0 |
f045b2c9 RS |
1557 | |
1558 | /* Define how to find the value returned by a function. | |
1559 | VALTYPE is the data type of the value (as a tree). | |
1560 | If the precise function being called is known, FUNC is its FUNCTION_DECL; | |
a6ebc39a AH |
1561 | otherwise, FUNC is 0. */ |
1562 | ||
1563 | #define FUNCTION_VALUE(VALTYPE, FUNC) rs6000_function_value ((VALTYPE), (FUNC)) | |
f045b2c9 RS |
1564 | |
1565 | /* Define how to find the value returned by a library function | |
1566 | assuming the value has mode MODE. */ | |
1567 | ||
ded9bf77 | 1568 | #define LIBCALL_VALUE(MODE) rs6000_libcall_value ((MODE)) |
f045b2c9 | 1569 | |
6fa3f289 ZW |
1570 | /* DRAFT_V4_STRUCT_RET defaults off. */ |
1571 | #define DRAFT_V4_STRUCT_RET 0 | |
f607bc57 | 1572 | |
bd5bd7ac | 1573 | /* Let TARGET_RETURN_IN_MEMORY control what happens. */ |
f607bc57 | 1574 | #define DEFAULT_PCC_STRUCT_RETURN 0 |
f045b2c9 | 1575 | |
a260abc9 | 1576 | /* Mode of stack savearea. |
dfdfa60f DE |
1577 | FUNCTION is VOIDmode because calling convention maintains SP. |
1578 | BLOCK needs Pmode for SP. | |
a260abc9 DE |
1579 | NONLOCAL needs twice Pmode to maintain both backchain and SP. */ |
1580 | #define STACK_SAVEAREA_MODE(LEVEL) \ | |
dfdfa60f DE |
1581 | (LEVEL == SAVE_FUNCTION ? VOIDmode \ |
1582 | : LEVEL == SAVE_NONLOCAL ? (TARGET_32BIT ? DImode : TImode) : Pmode) | |
a260abc9 | 1583 | |
4697a36c MM |
1584 | /* Minimum and maximum general purpose registers used to hold arguments. */ |
1585 | #define GP_ARG_MIN_REG 3 | |
1586 | #define GP_ARG_MAX_REG 10 | |
1587 | #define GP_ARG_NUM_REG (GP_ARG_MAX_REG - GP_ARG_MIN_REG + 1) | |
1588 | ||
1589 | /* Minimum and maximum floating point registers used to hold arguments. */ | |
1590 | #define FP_ARG_MIN_REG 33 | |
7509c759 MM |
1591 | #define FP_ARG_AIX_MAX_REG 45 |
1592 | #define FP_ARG_V4_MAX_REG 40 | |
9ebbca7d | 1593 | #define FP_ARG_MAX_REG ((DEFAULT_ABI == ABI_AIX \ |
ee890fe2 | 1594 | || DEFAULT_ABI == ABI_DARWIN) \ |
9ebbca7d | 1595 | ? FP_ARG_AIX_MAX_REG : FP_ARG_V4_MAX_REG) |
4697a36c MM |
1596 | #define FP_ARG_NUM_REG (FP_ARG_MAX_REG - FP_ARG_MIN_REG + 1) |
1597 | ||
0ac081f6 AH |
1598 | /* Minimum and maximum AltiVec registers used to hold arguments. */ |
1599 | #define ALTIVEC_ARG_MIN_REG (FIRST_ALTIVEC_REGNO + 2) | |
1600 | #define ALTIVEC_ARG_MAX_REG (ALTIVEC_ARG_MIN_REG + 11) | |
1601 | #define ALTIVEC_ARG_NUM_REG (ALTIVEC_ARG_MAX_REG - ALTIVEC_ARG_MIN_REG + 1) | |
1602 | ||
4697a36c MM |
1603 | /* Return registers */ |
1604 | #define GP_ARG_RETURN GP_ARG_MIN_REG | |
1605 | #define FP_ARG_RETURN FP_ARG_MIN_REG | |
0ac081f6 | 1606 | #define ALTIVEC_ARG_RETURN (FIRST_ALTIVEC_REGNO + 2) |
4697a36c | 1607 | |
7509c759 | 1608 | /* Flags for the call/call_value rtl operations set up by function_arg */ |
6a4cee5f | 1609 | #define CALL_NORMAL 0x00000000 /* no special processing */ |
9ebbca7d | 1610 | /* Bits in 0x00000001 are unused. */ |
6a4cee5f MM |
1611 | #define CALL_V4_CLEAR_FP_ARGS 0x00000002 /* V.4, no FP args passed */ |
1612 | #define CALL_V4_SET_FP_ARGS 0x00000004 /* V.4, FP args were passed */ | |
1613 | #define CALL_LONG 0x00000008 /* always call indirect */ | |
b9599e46 | 1614 | #define CALL_LIBCALL 0x00000010 /* libcall */ |
7509c759 | 1615 | |
f045b2c9 RS |
1616 | /* 1 if N is a possible register number for a function value |
1617 | as seen by the caller. | |
1618 | ||
0ac081f6 | 1619 | On RS/6000, this is r3, fp1, and v2 (for AltiVec). */ |
e87a88d3 AM |
1620 | #define FUNCTION_VALUE_REGNO_P(N) \ |
1621 | ((N) == GP_ARG_RETURN \ | |
1622 | || ((N) == FP_ARG_RETURN && TARGET_HARD_FLOAT) \ | |
44688022 | 1623 | || ((N) == ALTIVEC_ARG_RETURN && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI)) |
f045b2c9 RS |
1624 | |
1625 | /* 1 if N is a possible register number for function argument passing. | |
0ac081f6 AH |
1626 | On RS/6000, these are r3-r10 and fp1-fp13. |
1627 | On AltiVec, v2 - v13 are used for passing vectors. */ | |
4697a36c | 1628 | #define FUNCTION_ARG_REGNO_P(N) \ |
e87a88d3 AM |
1629 | ((unsigned) (N) - GP_ARG_MIN_REG < GP_ARG_NUM_REG \ |
1630 | || ((unsigned) (N) - ALTIVEC_ARG_MIN_REG < ALTIVEC_ARG_NUM_REG \ | |
44688022 | 1631 | && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI) \ |
e87a88d3 AM |
1632 | || ((unsigned) (N) - FP_ARG_MIN_REG < FP_ARG_NUM_REG \ |
1633 | && TARGET_HARD_FLOAT)) | |
f045b2c9 | 1634 | \f |
00dba523 NC |
1635 | /* A C structure for machine-specific, per-function data. |
1636 | This is added to the cfun structure. */ | |
e2500fed | 1637 | typedef struct machine_function GTY(()) |
00dba523 NC |
1638 | { |
1639 | /* Whether a System V.4 varargs area was created. */ | |
1640 | int sysv_varargs_p; | |
71f123ca FS |
1641 | /* Flags if __builtin_return_address (n) with n >= 1 was used. */ |
1642 | int ra_needs_full_frame; | |
c4501e62 JJ |
1643 | /* Some local-dynamic symbol. */ |
1644 | const char *some_ld_name; | |
9b7b447f AH |
1645 | /* Whether the instruction chain has been scanned already. */ |
1646 | int insn_chain_scanned_p; | |
8c29550d JJ |
1647 | /* Flags if __builtin_return_address (0) was used. */ |
1648 | int ra_need_lr; | |
00dba523 NC |
1649 | } machine_function; |
1650 | ||
f045b2c9 RS |
1651 | /* Define a data type for recording info about an argument list |
1652 | during the scan of that argument list. This data type should | |
1653 | hold all necessary information about the function itself | |
1654 | and about the args processed so far, enough to enable macros | |
1655 | such as FUNCTION_ARG to determine where the next arg should go. | |
1656 | ||
1657 | On the RS/6000, this is a structure. The first element is the number of | |
1658 | total argument words, the second is used to store the next | |
1659 | floating-point register number, and the third says how many more args we | |
4697a36c MM |
1660 | have prototype types for. |
1661 | ||
4cc833b7 | 1662 | For ABI_V4, we treat these slightly differently -- `sysv_gregno' is |
07488f32 | 1663 | the next available GP register, `fregno' is the next available FP |
4cc833b7 RH |
1664 | register, and `words' is the number of words used on the stack. |
1665 | ||
bd227acc | 1666 | The varargs/stdarg support requires that this structure's size |
4cc833b7 | 1667 | be a multiple of sizeof(int). */ |
4697a36c MM |
1668 | |
1669 | typedef struct rs6000_args | |
1670 | { | |
4cc833b7 | 1671 | int words; /* # words used for passing GP registers */ |
6a4cee5f | 1672 | int fregno; /* next available FP register */ |
0ac081f6 | 1673 | int vregno; /* next available AltiVec register */ |
6a4cee5f | 1674 | int nargs_prototype; /* # args left in the current prototype */ |
6a4cee5f | 1675 | int prototype; /* Whether a prototype was defined */ |
a6c9bed4 | 1676 | int stdarg; /* Whether function is a stdarg function. */ |
6a4cee5f | 1677 | int call_cookie; /* Do special things for this call */ |
4cc833b7 | 1678 | int sysv_gregno; /* next available GP register */ |
4697a36c | 1679 | } CUMULATIVE_ARGS; |
f045b2c9 | 1680 | |
f045b2c9 RS |
1681 | /* Initialize a variable CUM of type CUMULATIVE_ARGS |
1682 | for a call to a function whose data type is FNTYPE. | |
1683 | For a library call, FNTYPE is 0. */ | |
1684 | ||
0f6937fe AM |
1685 | #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \ |
1686 | init_cumulative_args (&CUM, FNTYPE, LIBNAME, FALSE, FALSE, N_NAMED_ARGS) | |
f045b2c9 RS |
1687 | |
1688 | /* Similar, but when scanning the definition of a procedure. We always | |
1689 | set NARGS_PROTOTYPE large so we never return an EXPR_LIST. */ | |
1690 | ||
0f6937fe AM |
1691 | #define INIT_CUMULATIVE_INCOMING_ARGS(CUM, FNTYPE, LIBNAME) \ |
1692 | init_cumulative_args (&CUM, FNTYPE, LIBNAME, TRUE, FALSE, 1000) | |
b9599e46 FS |
1693 | |
1694 | /* Like INIT_CUMULATIVE_ARGS' but only used for outgoing libcalls. */ | |
1695 | ||
1696 | #define INIT_CUMULATIVE_LIBCALL_ARGS(CUM, MODE, LIBNAME) \ | |
0f6937fe | 1697 | init_cumulative_args (&CUM, NULL_TREE, LIBNAME, FALSE, TRUE, 0) |
f045b2c9 RS |
1698 | |
1699 | /* Update the data in CUM to advance over an argument | |
1700 | of mode MODE and data type TYPE. | |
1701 | (TYPE is null for libcalls where that information may not be available.) */ | |
1702 | ||
1703 | #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ | |
4697a36c | 1704 | function_arg_advance (&CUM, MODE, TYPE, NAMED) |
f045b2c9 | 1705 | |
f045b2c9 RS |
1706 | /* Determine where to put an argument to a function. |
1707 | Value is zero to push the argument on the stack, | |
1708 | or a hard register in which to store the argument. | |
1709 | ||
1710 | MODE is the argument's machine mode. | |
1711 | TYPE is the data type of the argument (as a tree). | |
1712 | This is null for libcalls where that information may | |
1713 | not be available. | |
1714 | CUM is a variable of type CUMULATIVE_ARGS which gives info about | |
1715 | the preceding args and about the function being called. | |
1716 | NAMED is nonzero if this argument is a named parameter | |
1717 | (otherwise it is an extra parameter matching an ellipsis). | |
1718 | ||
1719 | On RS/6000 the first eight words of non-FP are normally in registers | |
1720 | and the rest are pushed. The first 13 FP args are in registers. | |
1721 | ||
1722 | If this is floating-point and no prototype is specified, we use | |
4d6697ca RK |
1723 | both an FP and integer register (or possibly FP reg and stack). Library |
1724 | functions (when TYPE is zero) always have the proper types for args, | |
1725 | so we can pass the FP value just in one register. emit_library_function | |
1726 | doesn't support EXPR_LIST anyway. */ | |
f045b2c9 | 1727 | |
4697a36c MM |
1728 | #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ |
1729 | function_arg (&CUM, MODE, TYPE, NAMED) | |
f045b2c9 RS |
1730 | |
1731 | /* For an arg passed partly in registers and partly in memory, | |
1732 | this is the number of registers used. | |
1733 | For args passed entirely in registers or entirely in memory, zero. */ | |
1734 | ||
4697a36c MM |
1735 | #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \ |
1736 | function_arg_partial_nregs (&CUM, MODE, TYPE, NAMED) | |
1737 | ||
c229cba9 DE |
1738 | /* If defined, a C expression which determines whether, and in which |
1739 | direction, to pad out an argument with extra space. The value | |
1740 | should be of type `enum direction': either `upward' to pad above | |
1741 | the argument, `downward' to pad below, or `none' to inhibit | |
1742 | padding. */ | |
1743 | ||
9ebbca7d | 1744 | #define FUNCTION_ARG_PADDING(MODE, TYPE) function_arg_padding (MODE, TYPE) |
c229cba9 | 1745 | |
b6c9286a | 1746 | /* If defined, a C expression that gives the alignment boundary, in bits, |
c81bebd7 | 1747 | of an argument with the specified mode and type. If it is not defined, |
b6c9286a MM |
1748 | PARM_BOUNDARY is used for all arguments. */ |
1749 | ||
1750 | #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \ | |
1751 | function_arg_boundary (MODE, TYPE) | |
1752 | ||
dfafc897 | 1753 | /* Implement `va_start' for varargs and stdarg. */ |
e5faf155 ZW |
1754 | #define EXPAND_BUILTIN_VA_START(valist, nextarg) \ |
1755 | rs6000_va_start (valist, nextarg) | |
dfafc897 | 1756 | |
6e985040 AM |
1757 | #define PAD_VARARGS_DOWN \ |
1758 | (FUNCTION_ARG_PADDING (TYPE_MODE (type), type) == downward) | |
2a55fd42 | 1759 | |
f045b2c9 | 1760 | /* Output assembler code to FILE to increment profiler label # LABELNO |
58a39e45 | 1761 | for profiling a function entry. */ |
f045b2c9 RS |
1762 | |
1763 | #define FUNCTION_PROFILER(FILE, LABELNO) \ | |
58a39e45 | 1764 | output_function_profiler ((FILE), (LABELNO)); |
f045b2c9 RS |
1765 | |
1766 | /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, | |
1767 | the stack pointer does not matter. No definition is equivalent to | |
1768 | always zero. | |
1769 | ||
a0ab749a | 1770 | On the RS/6000, this is nonzero because we can restore the stack from |
f045b2c9 RS |
1771 | its backpointer, which we maintain. */ |
1772 | #define EXIT_IGNORE_STACK 1 | |
1773 | ||
a701949a FS |
1774 | /* Define this macro as a C expression that is nonzero for registers |
1775 | that are used by the epilogue or the return' pattern. The stack | |
1776 | and frame pointer registers are already be assumed to be used as | |
1777 | needed. */ | |
1778 | ||
83720594 RH |
1779 | #define EPILOGUE_USES(REGNO) \ |
1780 | ((reload_completed && (REGNO) == LINK_REGISTER_REGNUM) \ | |
b1765bde | 1781 | || (TARGET_ALTIVEC && (REGNO) == VRSAVE_REGNO) \ |
83720594 | 1782 | || (current_function_calls_eh_return \ |
3553b09d | 1783 | && TARGET_AIX \ |
ff3867ae | 1784 | && (REGNO) == 2)) |
2bfcf297 | 1785 | |
f045b2c9 | 1786 | \f |
eaf1bcf1 | 1787 | /* TRAMPOLINE_TEMPLATE deleted */ |
f045b2c9 RS |
1788 | |
1789 | /* Length in units of the trampoline for entering a nested function. */ | |
1790 | ||
b6c9286a | 1791 | #define TRAMPOLINE_SIZE rs6000_trampoline_size () |
f045b2c9 RS |
1792 | |
1793 | /* Emit RTL insns to initialize the variable parts of a trampoline. | |
1794 | FNADDR is an RTX for the address of the function's pure code. | |
1795 | CXT is an RTX for the static chain value for the function. */ | |
1796 | ||
1797 | #define INITIALIZE_TRAMPOLINE(ADDR, FNADDR, CXT) \ | |
b6c9286a | 1798 | rs6000_initialize_trampoline (ADDR, FNADDR, CXT) |
f045b2c9 | 1799 | \f |
f33985c6 MS |
1800 | /* Definitions for __builtin_return_address and __builtin_frame_address. |
1801 | __builtin_return_address (0) should give link register (65), enable | |
82e41834 | 1802 | this. */ |
f33985c6 MS |
1803 | /* This should be uncommented, so that the link register is used, but |
1804 | currently this would result in unmatched insns and spilling fixed | |
1805 | registers so we'll leave it for another day. When these problems are | |
1806 | taken care of one additional fetch will be necessary in RETURN_ADDR_RTX. | |
1807 | (mrs) */ | |
1808 | /* #define RETURN_ADDR_IN_PREVIOUS_FRAME */ | |
f09d4c33 | 1809 | |
b6c9286a MM |
1810 | /* Number of bytes into the frame return addresses can be found. See |
1811 | rs6000_stack_info in rs6000.c for more information on how the different | |
1812 | abi's store the return address. */ | |
1813 | #define RETURN_ADDRESS_OFFSET \ | |
1814 | ((DEFAULT_ABI == ABI_AIX \ | |
50d440bc | 1815 | || DEFAULT_ABI == ABI_DARWIN) ? (TARGET_32BIT ? 8 : 16) : \ |
3b370352 | 1816 | (DEFAULT_ABI == ABI_V4) ? 4 : \ |
c4636dd1 | 1817 | (internal_error ("RETURN_ADDRESS_OFFSET not supported"), 0)) |
f09d4c33 | 1818 | |
f33985c6 MS |
1819 | /* The current return address is in link register (65). The return address |
1820 | of anything farther back is accessed normally at an offset of 8 from the | |
1821 | frame pointer. */ | |
71f123ca FS |
1822 | #define RETURN_ADDR_RTX(COUNT, FRAME) \ |
1823 | (rs6000_return_addr (COUNT, FRAME)) | |
1824 | ||
f33985c6 | 1825 | \f |
f045b2c9 RS |
1826 | /* Definitions for register eliminations. |
1827 | ||
1828 | We have two registers that can be eliminated on the RS/6000. First, the | |
1829 | frame pointer register can often be eliminated in favor of the stack | |
1830 | pointer register. Secondly, the argument pointer register can always be | |
642a35f1 JW |
1831 | eliminated; it is replaced with either the stack or frame pointer. |
1832 | ||
1833 | In addition, we use the elimination mechanism to see if r30 is needed | |
1834 | Initially we assume that it isn't. If it is, we spill it. This is done | |
1835 | by making it an eliminable register. We replace it with itself so that | |
1836 | if it isn't needed, then existing uses won't be modified. */ | |
f045b2c9 RS |
1837 | |
1838 | /* This is an array of structures. Each structure initializes one pair | |
1839 | of eliminable registers. The "from" register number is given first, | |
1840 | followed by "to". Eliminations of the same "from" register are listed | |
1841 | in order of preference. */ | |
1842 | #define ELIMINABLE_REGS \ | |
1843 | {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ | |
1844 | { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ | |
642a35f1 | 1845 | { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \ |
97b23853 | 1846 | { RS6000_PIC_OFFSET_TABLE_REGNUM, RS6000_PIC_OFFSET_TABLE_REGNUM } } |
f045b2c9 RS |
1847 | |
1848 | /* Given FROM and TO register numbers, say whether this elimination is allowed. | |
1849 | Frame pointer elimination is automatically handled. | |
1850 | ||
1851 | For the RS/6000, if frame pointer elimination is being done, we would like | |
642a35f1 JW |
1852 | to convert ap into fp, not sp. |
1853 | ||
abc95ed3 | 1854 | We need r30 if -mminimal-toc was specified, and there are constant pool |
642a35f1 | 1855 | references. */ |
f045b2c9 | 1856 | |
97b23853 GK |
1857 | #define CAN_ELIMINATE(FROM, TO) \ |
1858 | ((FROM) == ARG_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM \ | |
1859 | ? ! frame_pointer_needed \ | |
1860 | : (FROM) == RS6000_PIC_OFFSET_TABLE_REGNUM \ | |
1861 | ? ! TARGET_MINIMAL_TOC || TARGET_NO_TOC || get_pool_size () == 0 \ | |
f045b2c9 RS |
1862 | : 1) |
1863 | ||
1864 | /* Define the offset between two registers, one to be eliminated, and the other | |
1865 | its replacement, at the start of a routine. */ | |
d1d0c603 JJ |
1866 | #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ |
1867 | ((OFFSET) = rs6000_initial_elimination_offset(FROM, TO)) | |
f045b2c9 RS |
1868 | \f |
1869 | /* Addressing modes, and classification of registers for them. */ | |
1870 | ||
940da324 JL |
1871 | #define HAVE_PRE_DECREMENT 1 |
1872 | #define HAVE_PRE_INCREMENT 1 | |
f045b2c9 RS |
1873 | |
1874 | /* Macros to check register numbers against specific register classes. */ | |
1875 | ||
1876 | /* These assume that REGNO is a hard or pseudo reg number. | |
1877 | They give nonzero only if REGNO is a hard reg of the suitable class | |
1878 | or a pseudo reg currently allocated to a suitable hard reg. | |
1879 | Since they use reg_renumber, they are safe only once reg_renumber | |
1880 | has been allocated, which happens in local-alloc.c. */ | |
1881 | ||
1882 | #define REGNO_OK_FOR_INDEX_P(REGNO) \ | |
1883 | ((REGNO) < FIRST_PSEUDO_REGISTER \ | |
1884 | ? (REGNO) <= 31 || (REGNO) == 67 \ | |
1885 | : (reg_renumber[REGNO] >= 0 \ | |
1886 | && (reg_renumber[REGNO] <= 31 || reg_renumber[REGNO] == 67))) | |
1887 | ||
1888 | #define REGNO_OK_FOR_BASE_P(REGNO) \ | |
1889 | ((REGNO) < FIRST_PSEUDO_REGISTER \ | |
1890 | ? ((REGNO) > 0 && (REGNO) <= 31) || (REGNO) == 67 \ | |
1891 | : (reg_renumber[REGNO] > 0 \ | |
1892 | && (reg_renumber[REGNO] <= 31 || reg_renumber[REGNO] == 67))) | |
1893 | \f | |
1894 | /* Maximum number of registers that can appear in a valid memory address. */ | |
1895 | ||
1896 | #define MAX_REGS_PER_ADDRESS 2 | |
1897 | ||
1898 | /* Recognize any constant value that is a valid address. */ | |
1899 | ||
6eff269e BK |
1900 | #define CONSTANT_ADDRESS_P(X) \ |
1901 | (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \ | |
1902 | || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \ | |
1903 | || GET_CODE (X) == HIGH) | |
f045b2c9 RS |
1904 | |
1905 | /* Nonzero if the constant value X is a legitimate general operand. | |
1906 | It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. | |
1907 | ||
1908 | On the RS/6000, all integer constants are acceptable, most won't be valid | |
1909 | for particular insns, though. Only easy FP constants are | |
1910 | acceptable. */ | |
1911 | ||
1912 | #define LEGITIMATE_CONSTANT_P(X) \ | |
49a2166f AH |
1913 | (((GET_CODE (X) != CONST_DOUBLE \ |
1914 | && GET_CODE (X) != CONST_VECTOR) \ | |
1915 | || GET_MODE (X) == VOIDmode \ | |
c4501e62 | 1916 | || (TARGET_POWERPC64 && GET_MODE (X) == DImode) \ |
49a2166f AH |
1917 | || easy_fp_constant (X, GET_MODE (X)) \ |
1918 | || easy_vector_constant (X, GET_MODE (X))) \ | |
c4501e62 | 1919 | && !rs6000_tls_referenced_p (X)) |
f045b2c9 RS |
1920 | |
1921 | /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx | |
1922 | and check its validity for a certain class. | |
1923 | We have two alternate definitions for each of them. | |
1924 | The usual definition accepts all pseudo regs; the other rejects | |
1925 | them unless they have been allocated suitable hard regs. | |
1926 | The symbol REG_OK_STRICT causes the latter definition to be used. | |
1927 | ||
1928 | Most source files want to accept pseudo regs in the hope that | |
1929 | they will get allocated to the class that the insn wants them to be in. | |
1930 | Source files for reload pass need to be strict. | |
1931 | After reload, it makes no difference, since pseudo regs have | |
1932 | been eliminated by then. */ | |
1933 | ||
258bfae2 FS |
1934 | #ifdef REG_OK_STRICT |
1935 | # define REG_OK_STRICT_FLAG 1 | |
1936 | #else | |
1937 | # define REG_OK_STRICT_FLAG 0 | |
1938 | #endif | |
f045b2c9 RS |
1939 | |
1940 | /* Nonzero if X is a hard reg that can be used as an index | |
258bfae2 FS |
1941 | or if it is a pseudo reg in the non-strict case. */ |
1942 | #define INT_REG_OK_FOR_INDEX_P(X, STRICT) \ | |
1943 | ((! (STRICT) \ | |
1944 | && (REGNO (X) <= 31 \ | |
1945 | || REGNO (X) == ARG_POINTER_REGNUM \ | |
1946 | || REGNO (X) >= FIRST_PSEUDO_REGISTER)) \ | |
1947 | || ((STRICT) && REGNO_OK_FOR_INDEX_P (REGNO (X)))) | |
f045b2c9 RS |
1948 | |
1949 | /* Nonzero if X is a hard reg that can be used as a base reg | |
258bfae2 FS |
1950 | or if it is a pseudo reg in the non-strict case. */ |
1951 | #define INT_REG_OK_FOR_BASE_P(X, STRICT) \ | |
1952 | (REGNO (X) > 0 && INT_REG_OK_FOR_INDEX_P (X, (STRICT))) | |
f045b2c9 | 1953 | |
258bfae2 FS |
1954 | #define REG_OK_FOR_INDEX_P(X) INT_REG_OK_FOR_INDEX_P (X, REG_OK_STRICT_FLAG) |
1955 | #define REG_OK_FOR_BASE_P(X) INT_REG_OK_FOR_BASE_P (X, REG_OK_STRICT_FLAG) | |
f045b2c9 RS |
1956 | \f |
1957 | /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression | |
1958 | that is a valid memory address for an instruction. | |
1959 | The MODE argument is the machine mode for the MEM expression | |
1960 | that wants to use this address. | |
1961 | ||
1962 | On the RS/6000, there are four valid address: a SYMBOL_REF that | |
1963 | refers to a constant pool entry of an address (or the sum of it | |
1964 | plus a constant), a short (16-bit signed) constant plus a register, | |
1965 | the sum of two registers, or a register indirect, possibly with an | |
5bdc5878 | 1966 | auto-increment. For DFmode and DImode with a constant plus register, |
2f3e5814 | 1967 | we must ensure that both words are addressable or PowerPC64 with offset |
1427100a DE |
1968 | word aligned. |
1969 | ||
1970 | For modes spanning multiple registers (DFmode in 32-bit GPRs, | |
1971 | 32-bit DImode, TImode), indexed addressing cannot be used because | |
1972 | adjacent memory cells are accessed by adding word-sized offsets | |
1973 | during assembly output. */ | |
f045b2c9 | 1974 | |
258bfae2 FS |
1975 | #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ |
1976 | { if (rs6000_legitimate_address (MODE, X, REG_OK_STRICT_FLAG)) \ | |
1977 | goto ADDR; \ | |
f045b2c9 RS |
1978 | } |
1979 | \f | |
1980 | /* Try machine-dependent ways of modifying an illegitimate address | |
1981 | to be legitimate. If we find one, return the new, valid address. | |
1982 | This macro is used in only one place: `memory_address' in explow.c. | |
1983 | ||
1984 | OLDX is the address as it was before break_out_memory_refs was called. | |
1985 | In some cases it is useful to look at this to decide what needs to be done. | |
1986 | ||
1987 | MODE and WIN are passed so that this macro can use | |
1988 | GO_IF_LEGITIMATE_ADDRESS. | |
1989 | ||
1990 | It is always safe for this macro to do nothing. It exists to recognize | |
1991 | opportunities to optimize the output. | |
1992 | ||
1993 | On RS/6000, first check for the sum of a register with a constant | |
1994 | integer that is out of range. If so, generate code to add the | |
1995 | constant with the low-order 16 bits masked to the register and force | |
1996 | this result into another register (this can be done with `cau'). | |
c81bebd7 | 1997 | Then generate an address of REG+(CONST&0xffff), allowing for the |
f045b2c9 RS |
1998 | possibility of bit 16 being a one. |
1999 | ||
2000 | Then check for the sum of a register and something not constant, try to | |
2001 | load the other things into a register and return the sum. */ | |
2002 | ||
9ebbca7d GK |
2003 | #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \ |
2004 | { rtx result = rs6000_legitimize_address (X, OLDX, MODE); \ | |
2005 | if (result != NULL_RTX) \ | |
2006 | { \ | |
2007 | (X) = result; \ | |
2008 | goto WIN; \ | |
2009 | } \ | |
f045b2c9 RS |
2010 | } |
2011 | ||
a260abc9 DE |
2012 | /* Try a machine-dependent way of reloading an illegitimate address |
2013 | operand. If we find one, push the reload and jump to WIN. This | |
2014 | macro is used in only one place: `find_reloads_address' in reload.c. | |
2015 | ||
24ea750e DJ |
2016 | Implemented on rs6000 by rs6000_legitimize_reload_address. |
2017 | Note that (X) is evaluated twice; this is safe in current usage. */ | |
a260abc9 | 2018 | |
a9098fd0 GK |
2019 | #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \ |
2020 | do { \ | |
24ea750e DJ |
2021 | int win; \ |
2022 | (X) = rs6000_legitimize_reload_address ((X), (MODE), (OPNUM), \ | |
2023 | (int)(TYPE), (IND_LEVELS), &win); \ | |
2024 | if ( win ) \ | |
2025 | goto WIN; \ | |
a260abc9 DE |
2026 | } while (0) |
2027 | ||
f045b2c9 | 2028 | /* Go to LABEL if ADDR (a legitimate address expression) |
4d588c14 | 2029 | has an effect that depends on the machine mode it is used for. */ |
f045b2c9 RS |
2030 | |
2031 | #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \ | |
4d588c14 RH |
2032 | do { \ |
2033 | if (rs6000_mode_dependent_address (ADDR)) \ | |
f045b2c9 | 2034 | goto LABEL; \ |
4d588c14 | 2035 | } while (0) |
766a866c MM |
2036 | \f |
2037 | /* The register number of the register used to address a table of | |
2038 | static data addresses in memory. In some cases this register is | |
2039 | defined by a processor's "application binary interface" (ABI). | |
2040 | When this macro is defined, RTL is generated for this register | |
2041 | once, as with the stack pointer and frame pointer registers. If | |
2042 | this macro is not defined, it is up to the machine-dependent files | |
2043 | to allocate such a register (if necessary). */ | |
2044 | ||
1db02437 FS |
2045 | #define RS6000_PIC_OFFSET_TABLE_REGNUM 30 |
2046 | #define PIC_OFFSET_TABLE_REGNUM (flag_pic ? RS6000_PIC_OFFSET_TABLE_REGNUM : INVALID_REGNUM) | |
766a866c | 2047 | |
97b23853 | 2048 | #define TOC_REGISTER (TARGET_MINIMAL_TOC ? RS6000_PIC_OFFSET_TABLE_REGNUM : 2) |
9ebbca7d | 2049 | |
766a866c MM |
2050 | /* Define this macro if the register defined by |
2051 | `PIC_OFFSET_TABLE_REGNUM' is clobbered by calls. Do not define | |
089a05b8 | 2052 | this macro if `PIC_OFFSET_TABLE_REGNUM' is not defined. */ |
766a866c MM |
2053 | |
2054 | /* #define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED */ | |
2055 | ||
2056 | /* By generating position-independent code, when two different | |
2057 | programs (A and B) share a common library (libC.a), the text of | |
2058 | the library can be shared whether or not the library is linked at | |
2059 | the same address for both programs. In some of these | |
2060 | environments, position-independent code requires not only the use | |
2061 | of different addressing modes, but also special code to enable the | |
2062 | use of these addressing modes. | |
2063 | ||
2064 | The `FINALIZE_PIC' macro serves as a hook to emit these special | |
2065 | codes once the function is being compiled into assembly code, but | |
2066 | not before. (It is not done before, because in the case of | |
2067 | compiling an inline function, it would lead to multiple PIC | |
2068 | prologues being included in functions which used inline functions | |
2069 | and were compiled to assembly language.) */ | |
2070 | ||
8d30c4ee | 2071 | /* #define FINALIZE_PIC */ |
766a866c | 2072 | |
766a866c MM |
2073 | /* A C expression that is nonzero if X is a legitimate immediate |
2074 | operand on the target machine when generating position independent | |
2075 | code. You can assume that X satisfies `CONSTANT_P', so you need | |
2076 | not check this. You can also assume FLAG_PIC is true, so you need | |
2077 | not check it either. You need not define this macro if all | |
2078 | constants (including `SYMBOL_REF') can be immediate operands when | |
2079 | generating position independent code. */ | |
2080 | ||
2081 | /* #define LEGITIMATE_PIC_OPERAND_P (X) */ | |
f045b2c9 RS |
2082 | \f |
2083 | /* Define this if some processing needs to be done immediately before | |
4255474b | 2084 | emitting code for an insn. */ |
f045b2c9 | 2085 | |
4255474b | 2086 | /* #define FINAL_PRESCAN_INSN(INSN,OPERANDS,NOPERANDS) */ |
f045b2c9 RS |
2087 | |
2088 | /* Specify the machine mode that this machine uses | |
2089 | for the index in the tablejump instruction. */ | |
e1565e65 | 2090 | #define CASE_VECTOR_MODE SImode |
f045b2c9 | 2091 | |
18543a22 ILT |
2092 | /* Define as C expression which evaluates to nonzero if the tablejump |
2093 | instruction expects the table to contain offsets from the address of the | |
2094 | table. | |
82e41834 | 2095 | Do not define this if the table should contain absolute addresses. */ |
18543a22 | 2096 | #define CASE_VECTOR_PC_RELATIVE 1 |
f045b2c9 | 2097 | |
f045b2c9 RS |
2098 | /* Define this as 1 if `char' should by default be signed; else as 0. */ |
2099 | #define DEFAULT_SIGNED_CHAR 0 | |
2100 | ||
2101 | /* This flag, if defined, says the same insns that convert to a signed fixnum | |
2102 | also convert validly to an unsigned one. */ | |
2103 | ||
2104 | /* #define FIXUNS_TRUNC_LIKE_FIX_TRUNC */ | |
2105 | ||
2106 | /* Max number of bytes we can move from memory to memory | |
2107 | in one reasonably fast instruction. */ | |
2f3e5814 | 2108 | #define MOVE_MAX (! TARGET_POWERPC64 ? 4 : 8) |
7e69e155 | 2109 | #define MAX_MOVE_MAX 8 |
f045b2c9 RS |
2110 | |
2111 | /* Nonzero if access to memory by bytes is no faster than for words. | |
a0ab749a | 2112 | Also nonzero if doing byte operations (specifically shifts) in registers |
f045b2c9 RS |
2113 | is undesirable. */ |
2114 | #define SLOW_BYTE_ACCESS 1 | |
2115 | ||
9a63901f RK |
2116 | /* Define if operations between registers always perform the operation |
2117 | on the full register even if a narrower mode is specified. */ | |
2118 | #define WORD_REGISTER_OPERATIONS | |
2119 | ||
2120 | /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD | |
2121 | will either zero-extend or sign-extend. The value of this macro should | |
2122 | be the code that says which one of the two operations is implicitly | |
2123 | done, NIL if none. */ | |
2124 | #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND | |
225211e2 RK |
2125 | |
2126 | /* Define if loading short immediate values into registers sign extends. */ | |
2127 | #define SHORT_IMMEDIATES_SIGN_EXTEND | |
fdaff8ba | 2128 | \f |
f045b2c9 RS |
2129 | /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits |
2130 | is done just by pretending it is already truncated. */ | |
2131 | #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 | |
2132 | ||
94993909 | 2133 | /* The cntlzw and cntlzd instructions return 32 and 64 for input of zero. */ |
d865b122 DE |
2134 | #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \ |
2135 | ((VALUE) = ((MODE) == SImode ? 32 : 64)) | |
2136 | ||
94993909 DE |
2137 | /* The CTZ patterns return -1 for input of zero. */ |
2138 | #define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = -1) | |
2139 | ||
f045b2c9 RS |
2140 | /* Specify the machine mode that pointers have. |
2141 | After generation of rtl, the compiler makes no further distinction | |
2142 | between pointers and any other objects of this machine mode. */ | |
2f3e5814 | 2143 | #define Pmode (TARGET_32BIT ? SImode : DImode) |
f045b2c9 | 2144 | |
a3c9585f | 2145 | /* Supply definition of STACK_SIZE_MODE for allocate_dynamic_stack_space. */ |
4c81e946 FJ |
2146 | #define STACK_SIZE_MODE (TARGET_32BIT ? SImode : DImode) |
2147 | ||
f045b2c9 | 2148 | /* Mode of a function address in a call instruction (for indexing purposes). |
f045b2c9 | 2149 | Doesn't matter on RS/6000. */ |
5b71a4e7 | 2150 | #define FUNCTION_MODE SImode |
f045b2c9 RS |
2151 | |
2152 | /* Define this if addresses of constant functions | |
2153 | shouldn't be put through pseudo regs where they can be cse'd. | |
2154 | Desirable on machines where ordinary constants are expensive | |
2155 | but a CALL with constant address is cheap. */ | |
2156 | #define NO_FUNCTION_CSE | |
2157 | ||
d969caf8 | 2158 | /* Define this to be nonzero if shift instructions ignore all but the low-order |
6febd581 RK |
2159 | few bits. |
2160 | ||
2161 | The sle and sre instructions which allow SHIFT_COUNT_TRUNCATED | |
2162 | have been dropped from the PowerPC architecture. */ | |
2163 | ||
4697a36c | 2164 | #define SHIFT_COUNT_TRUNCATED (TARGET_POWER ? 1 : 0) |
f045b2c9 | 2165 | |
f045b2c9 RS |
2166 | /* Adjust the length of an INSN. LENGTH is the currently-computed length and |
2167 | should be adjusted to reflect any required changes. This macro is used when | |
2168 | there is some systematic length adjustment required that would be difficult | |
2169 | to express in the length attribute. */ | |
2170 | ||
2171 | /* #define ADJUST_INSN_LENGTH(X,LENGTH) */ | |
2172 | ||
39a10a29 GK |
2173 | /* Given a comparison code (EQ, NE, etc.) and the first operand of a |
2174 | COMPARE, return the mode to be used for the comparison. For | |
2175 | floating-point, CCFPmode should be used. CCUNSmode should be used | |
2176 | for unsigned comparisons. CCEQmode should be used when we are | |
2177 | doing an inequality comparison on the result of a | |
2178 | comparison. CCmode should be used in all other cases. */ | |
c5defebb | 2179 | |
b565a316 | 2180 | #define SELECT_CC_MODE(OP,X,Y) \ |
f045b2c9 | 2181 | (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT ? CCFPmode \ |
c5defebb | 2182 | : (OP) == GTU || (OP) == LTU || (OP) == GEU || (OP) == LEU ? CCUNSmode \ |
ec8e098d | 2183 | : (((OP) == EQ || (OP) == NE) && COMPARISON_P (X) \ |
c5defebb | 2184 | ? CCEQmode : CCmode)) |
f045b2c9 | 2185 | |
b39358e1 GK |
2186 | /* Can the condition code MODE be safely reversed? This is safe in |
2187 | all cases on this port, because at present it doesn't use the | |
2188 | trapping FP comparisons (fcmpo). */ | |
2189 | #define REVERSIBLE_CC_MODE(MODE) 1 | |
2190 | ||
2191 | /* Given a condition code and a mode, return the inverse condition. */ | |
2192 | #define REVERSE_CONDITION(CODE, MODE) rs6000_reverse_condition (MODE, CODE) | |
2193 | ||
f045b2c9 | 2194 | /* Define the information needed to generate branch and scc insns. This is |
b39358e1 | 2195 | stored from the compare operation. */ |
f045b2c9 | 2196 | |
e2500fed GK |
2197 | extern GTY(()) rtx rs6000_compare_op0; |
2198 | extern GTY(()) rtx rs6000_compare_op1; | |
f045b2c9 | 2199 | extern int rs6000_compare_fp_p; |
f045b2c9 RS |
2200 | \f |
2201 | /* Control the assembler format that we output. */ | |
2202 | ||
1b279f39 DE |
2203 | /* A C string constant describing how to begin a comment in the target |
2204 | assembler language. The compiler assumes that the comment will end at | |
2205 | the end of the line. */ | |
2206 | #define ASM_COMMENT_START " #" | |
6b67933e | 2207 | |
38c1f2d7 MM |
2208 | /* Flag to say the TOC is initialized */ |
2209 | extern int toc_initialized; | |
2210 | ||
f045b2c9 RS |
2211 | /* Macro to output a special constant pool entry. Go to WIN if we output |
2212 | it. Otherwise, it is written the usual way. | |
2213 | ||
2214 | On the RS/6000, toc entries are handled this way. */ | |
2215 | ||
a9098fd0 GK |
2216 | #define ASM_OUTPUT_SPECIAL_POOL_ENTRY(FILE, X, MODE, ALIGN, LABELNO, WIN) \ |
2217 | { if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (X, MODE)) \ | |
2218 | { \ | |
2219 | output_toc (FILE, X, LABELNO, MODE); \ | |
2220 | goto WIN; \ | |
2221 | } \ | |
f045b2c9 RS |
2222 | } |
2223 | ||
ebd97b96 DE |
2224 | #ifdef HAVE_GAS_WEAK |
2225 | #define RS6000_WEAK 1 | |
2226 | #else | |
2227 | #define RS6000_WEAK 0 | |
2228 | #endif | |
290ad355 | 2229 | |
79c4e63f AM |
2230 | #if RS6000_WEAK |
2231 | /* Used in lieu of ASM_WEAKEN_LABEL. */ | |
2232 | #define ASM_WEAKEN_DECL(FILE, DECL, NAME, VAL) \ | |
2233 | do \ | |
2234 | { \ | |
2235 | fputs ("\t.weak\t", (FILE)); \ | |
cbaaba19 | 2236 | RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \ |
79c4e63f AM |
2237 | if ((DECL) && TREE_CODE (DECL) == FUNCTION_DECL \ |
2238 | && DEFAULT_ABI == ABI_AIX) \ | |
2239 | { \ | |
cbaaba19 DE |
2240 | if (TARGET_XCOFF) \ |
2241 | fputs ("[DS]", (FILE)); \ | |
ca734b39 | 2242 | fputs ("\n\t.weak\t.", (FILE)); \ |
cbaaba19 | 2243 | RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \ |
79c4e63f AM |
2244 | } \ |
2245 | fputc ('\n', (FILE)); \ | |
2246 | if (VAL) \ | |
2247 | { \ | |
2248 | ASM_OUTPUT_DEF ((FILE), (NAME), (VAL)); \ | |
2249 | if ((DECL) && TREE_CODE (DECL) == FUNCTION_DECL \ | |
2250 | && DEFAULT_ABI == ABI_AIX) \ | |
2251 | { \ | |
2252 | fputs ("\t.set\t.", (FILE)); \ | |
cbaaba19 | 2253 | RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \ |
79c4e63f | 2254 | fputs (",.", (FILE)); \ |
cbaaba19 | 2255 | RS6000_OUTPUT_BASENAME ((FILE), (VAL)); \ |
79c4e63f AM |
2256 | fputc ('\n', (FILE)); \ |
2257 | } \ | |
2258 | } \ | |
2259 | } \ | |
2260 | while (0) | |
2261 | #endif | |
2262 | ||
2263 | /* This implements the `alias' attribute. */ | |
2264 | #undef ASM_OUTPUT_DEF_FROM_DECLS | |
2265 | #define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL, TARGET) \ | |
2266 | do \ | |
2267 | { \ | |
2268 | const char *alias = XSTR (XEXP (DECL_RTL (DECL), 0), 0); \ | |
2269 | const char *name = IDENTIFIER_POINTER (TARGET); \ | |
2270 | if (TREE_CODE (DECL) == FUNCTION_DECL \ | |
2271 | && DEFAULT_ABI == ABI_AIX) \ | |
2272 | { \ | |
2273 | if (TREE_PUBLIC (DECL)) \ | |
2274 | { \ | |
2275 | if (!RS6000_WEAK || !DECL_WEAK (DECL)) \ | |
2276 | { \ | |
2277 | fputs ("\t.globl\t.", FILE); \ | |
cbaaba19 | 2278 | RS6000_OUTPUT_BASENAME (FILE, alias); \ |
79c4e63f AM |
2279 | putc ('\n', FILE); \ |
2280 | } \ | |
2281 | } \ | |
2282 | else if (TARGET_XCOFF) \ | |
2283 | { \ | |
2284 | fputs ("\t.lglobl\t.", FILE); \ | |
cbaaba19 | 2285 | RS6000_OUTPUT_BASENAME (FILE, alias); \ |
79c4e63f AM |
2286 | putc ('\n', FILE); \ |
2287 | } \ | |
2288 | fputs ("\t.set\t.", FILE); \ | |
cbaaba19 | 2289 | RS6000_OUTPUT_BASENAME (FILE, alias); \ |
79c4e63f | 2290 | fputs (",.", FILE); \ |
cbaaba19 | 2291 | RS6000_OUTPUT_BASENAME (FILE, name); \ |
79c4e63f AM |
2292 | fputc ('\n', FILE); \ |
2293 | } \ | |
2294 | ASM_OUTPUT_DEF (FILE, alias, name); \ | |
2295 | } \ | |
2296 | while (0) | |
290ad355 | 2297 | |
1bc7c5b6 ZW |
2298 | #define TARGET_ASM_FILE_START rs6000_file_start |
2299 | ||
f045b2c9 RS |
2300 | /* Output to assembler file text saying following lines |
2301 | may contain character constants, extra white space, comments, etc. */ | |
2302 | ||
2303 | #define ASM_APP_ON "" | |
2304 | ||
2305 | /* Output to assembler file text saying following lines | |
2306 | no longer contain unusual constructs. */ | |
2307 | ||
2308 | #define ASM_APP_OFF "" | |
2309 | ||
f045b2c9 RS |
2310 | /* How to refer to registers in assembler output. |
2311 | This sequence is indexed by compiler's hard-register-number (see above). */ | |
2312 | ||
82e41834 | 2313 | extern char rs6000_reg_names[][8]; /* register names (0 vs. %r0). */ |
c81bebd7 MM |
2314 | |
2315 | #define REGISTER_NAMES \ | |
2316 | { \ | |
2317 | &rs6000_reg_names[ 0][0], /* r0 */ \ | |
2318 | &rs6000_reg_names[ 1][0], /* r1 */ \ | |
2319 | &rs6000_reg_names[ 2][0], /* r2 */ \ | |
2320 | &rs6000_reg_names[ 3][0], /* r3 */ \ | |
2321 | &rs6000_reg_names[ 4][0], /* r4 */ \ | |
2322 | &rs6000_reg_names[ 5][0], /* r5 */ \ | |
2323 | &rs6000_reg_names[ 6][0], /* r6 */ \ | |
2324 | &rs6000_reg_names[ 7][0], /* r7 */ \ | |
2325 | &rs6000_reg_names[ 8][0], /* r8 */ \ | |
2326 | &rs6000_reg_names[ 9][0], /* r9 */ \ | |
2327 | &rs6000_reg_names[10][0], /* r10 */ \ | |
2328 | &rs6000_reg_names[11][0], /* r11 */ \ | |
2329 | &rs6000_reg_names[12][0], /* r12 */ \ | |
2330 | &rs6000_reg_names[13][0], /* r13 */ \ | |
2331 | &rs6000_reg_names[14][0], /* r14 */ \ | |
2332 | &rs6000_reg_names[15][0], /* r15 */ \ | |
2333 | &rs6000_reg_names[16][0], /* r16 */ \ | |
2334 | &rs6000_reg_names[17][0], /* r17 */ \ | |
2335 | &rs6000_reg_names[18][0], /* r18 */ \ | |
2336 | &rs6000_reg_names[19][0], /* r19 */ \ | |
2337 | &rs6000_reg_names[20][0], /* r20 */ \ | |
2338 | &rs6000_reg_names[21][0], /* r21 */ \ | |
2339 | &rs6000_reg_names[22][0], /* r22 */ \ | |
2340 | &rs6000_reg_names[23][0], /* r23 */ \ | |
2341 | &rs6000_reg_names[24][0], /* r24 */ \ | |
2342 | &rs6000_reg_names[25][0], /* r25 */ \ | |
2343 | &rs6000_reg_names[26][0], /* r26 */ \ | |
2344 | &rs6000_reg_names[27][0], /* r27 */ \ | |
2345 | &rs6000_reg_names[28][0], /* r28 */ \ | |
2346 | &rs6000_reg_names[29][0], /* r29 */ \ | |
2347 | &rs6000_reg_names[30][0], /* r30 */ \ | |
2348 | &rs6000_reg_names[31][0], /* r31 */ \ | |
2349 | \ | |
2350 | &rs6000_reg_names[32][0], /* fr0 */ \ | |
2351 | &rs6000_reg_names[33][0], /* fr1 */ \ | |
2352 | &rs6000_reg_names[34][0], /* fr2 */ \ | |
2353 | &rs6000_reg_names[35][0], /* fr3 */ \ | |
2354 | &rs6000_reg_names[36][0], /* fr4 */ \ | |
2355 | &rs6000_reg_names[37][0], /* fr5 */ \ | |
2356 | &rs6000_reg_names[38][0], /* fr6 */ \ | |
2357 | &rs6000_reg_names[39][0], /* fr7 */ \ | |
2358 | &rs6000_reg_names[40][0], /* fr8 */ \ | |
2359 | &rs6000_reg_names[41][0], /* fr9 */ \ | |
2360 | &rs6000_reg_names[42][0], /* fr10 */ \ | |
2361 | &rs6000_reg_names[43][0], /* fr11 */ \ | |
2362 | &rs6000_reg_names[44][0], /* fr12 */ \ | |
2363 | &rs6000_reg_names[45][0], /* fr13 */ \ | |
2364 | &rs6000_reg_names[46][0], /* fr14 */ \ | |
2365 | &rs6000_reg_names[47][0], /* fr15 */ \ | |
2366 | &rs6000_reg_names[48][0], /* fr16 */ \ | |
2367 | &rs6000_reg_names[49][0], /* fr17 */ \ | |
2368 | &rs6000_reg_names[50][0], /* fr18 */ \ | |
2369 | &rs6000_reg_names[51][0], /* fr19 */ \ | |
2370 | &rs6000_reg_names[52][0], /* fr20 */ \ | |
2371 | &rs6000_reg_names[53][0], /* fr21 */ \ | |
2372 | &rs6000_reg_names[54][0], /* fr22 */ \ | |
2373 | &rs6000_reg_names[55][0], /* fr23 */ \ | |
2374 | &rs6000_reg_names[56][0], /* fr24 */ \ | |
2375 | &rs6000_reg_names[57][0], /* fr25 */ \ | |
2376 | &rs6000_reg_names[58][0], /* fr26 */ \ | |
2377 | &rs6000_reg_names[59][0], /* fr27 */ \ | |
2378 | &rs6000_reg_names[60][0], /* fr28 */ \ | |
2379 | &rs6000_reg_names[61][0], /* fr29 */ \ | |
2380 | &rs6000_reg_names[62][0], /* fr30 */ \ | |
2381 | &rs6000_reg_names[63][0], /* fr31 */ \ | |
2382 | \ | |
2383 | &rs6000_reg_names[64][0], /* mq */ \ | |
2384 | &rs6000_reg_names[65][0], /* lr */ \ | |
2385 | &rs6000_reg_names[66][0], /* ctr */ \ | |
2386 | &rs6000_reg_names[67][0], /* ap */ \ | |
2387 | \ | |
2388 | &rs6000_reg_names[68][0], /* cr0 */ \ | |
2389 | &rs6000_reg_names[69][0], /* cr1 */ \ | |
2390 | &rs6000_reg_names[70][0], /* cr2 */ \ | |
2391 | &rs6000_reg_names[71][0], /* cr3 */ \ | |
2392 | &rs6000_reg_names[72][0], /* cr4 */ \ | |
2393 | &rs6000_reg_names[73][0], /* cr5 */ \ | |
2394 | &rs6000_reg_names[74][0], /* cr6 */ \ | |
2395 | &rs6000_reg_names[75][0], /* cr7 */ \ | |
802a0058 | 2396 | \ |
9ebbca7d | 2397 | &rs6000_reg_names[76][0], /* xer */ \ |
0ac081f6 AH |
2398 | \ |
2399 | &rs6000_reg_names[77][0], /* v0 */ \ | |
2400 | &rs6000_reg_names[78][0], /* v1 */ \ | |
2401 | &rs6000_reg_names[79][0], /* v2 */ \ | |
2402 | &rs6000_reg_names[80][0], /* v3 */ \ | |
2403 | &rs6000_reg_names[81][0], /* v4 */ \ | |
2404 | &rs6000_reg_names[82][0], /* v5 */ \ | |
2405 | &rs6000_reg_names[83][0], /* v6 */ \ | |
2406 | &rs6000_reg_names[84][0], /* v7 */ \ | |
2407 | &rs6000_reg_names[85][0], /* v8 */ \ | |
2408 | &rs6000_reg_names[86][0], /* v9 */ \ | |
2409 | &rs6000_reg_names[87][0], /* v10 */ \ | |
2410 | &rs6000_reg_names[88][0], /* v11 */ \ | |
2411 | &rs6000_reg_names[89][0], /* v12 */ \ | |
2412 | &rs6000_reg_names[90][0], /* v13 */ \ | |
2413 | &rs6000_reg_names[91][0], /* v14 */ \ | |
2414 | &rs6000_reg_names[92][0], /* v15 */ \ | |
2415 | &rs6000_reg_names[93][0], /* v16 */ \ | |
2416 | &rs6000_reg_names[94][0], /* v17 */ \ | |
2417 | &rs6000_reg_names[95][0], /* v18 */ \ | |
2418 | &rs6000_reg_names[96][0], /* v19 */ \ | |
2419 | &rs6000_reg_names[97][0], /* v20 */ \ | |
2420 | &rs6000_reg_names[98][0], /* v21 */ \ | |
2421 | &rs6000_reg_names[99][0], /* v22 */ \ | |
2422 | &rs6000_reg_names[100][0], /* v23 */ \ | |
2423 | &rs6000_reg_names[101][0], /* v24 */ \ | |
2424 | &rs6000_reg_names[102][0], /* v25 */ \ | |
2425 | &rs6000_reg_names[103][0], /* v26 */ \ | |
2426 | &rs6000_reg_names[104][0], /* v27 */ \ | |
2427 | &rs6000_reg_names[105][0], /* v28 */ \ | |
2428 | &rs6000_reg_names[106][0], /* v29 */ \ | |
2429 | &rs6000_reg_names[107][0], /* v30 */ \ | |
2430 | &rs6000_reg_names[108][0], /* v31 */ \ | |
2431 | &rs6000_reg_names[109][0], /* vrsave */ \ | |
5f004351 | 2432 | &rs6000_reg_names[110][0], /* vscr */ \ |
a3170dc6 AH |
2433 | &rs6000_reg_names[111][0], /* spe_acc */ \ |
2434 | &rs6000_reg_names[112][0], /* spefscr */ \ | |
c81bebd7 MM |
2435 | } |
2436 | ||
f045b2c9 RS |
2437 | /* Table of additional register names to use in user input. */ |
2438 | ||
2439 | #define ADDITIONAL_REGISTER_NAMES \ | |
c4d38ccb MM |
2440 | {{"r0", 0}, {"r1", 1}, {"r2", 2}, {"r3", 3}, \ |
2441 | {"r4", 4}, {"r5", 5}, {"r6", 6}, {"r7", 7}, \ | |
2442 | {"r8", 8}, {"r9", 9}, {"r10", 10}, {"r11", 11}, \ | |
2443 | {"r12", 12}, {"r13", 13}, {"r14", 14}, {"r15", 15}, \ | |
2444 | {"r16", 16}, {"r17", 17}, {"r18", 18}, {"r19", 19}, \ | |
2445 | {"r20", 20}, {"r21", 21}, {"r22", 22}, {"r23", 23}, \ | |
2446 | {"r24", 24}, {"r25", 25}, {"r26", 26}, {"r27", 27}, \ | |
2447 | {"r28", 28}, {"r29", 29}, {"r30", 30}, {"r31", 31}, \ | |
2448 | {"fr0", 32}, {"fr1", 33}, {"fr2", 34}, {"fr3", 35}, \ | |
2449 | {"fr4", 36}, {"fr5", 37}, {"fr6", 38}, {"fr7", 39}, \ | |
2450 | {"fr8", 40}, {"fr9", 41}, {"fr10", 42}, {"fr11", 43}, \ | |
2451 | {"fr12", 44}, {"fr13", 45}, {"fr14", 46}, {"fr15", 47}, \ | |
2452 | {"fr16", 48}, {"fr17", 49}, {"fr18", 50}, {"fr19", 51}, \ | |
2453 | {"fr20", 52}, {"fr21", 53}, {"fr22", 54}, {"fr23", 55}, \ | |
2454 | {"fr24", 56}, {"fr25", 57}, {"fr26", 58}, {"fr27", 59}, \ | |
2455 | {"fr28", 60}, {"fr29", 61}, {"fr30", 62}, {"fr31", 63}, \ | |
0ac081f6 AH |
2456 | {"v0", 77}, {"v1", 78}, {"v2", 79}, {"v3", 80}, \ |
2457 | {"v4", 81}, {"v5", 82}, {"v6", 83}, {"v7", 84}, \ | |
2458 | {"v8", 85}, {"v9", 86}, {"v10", 87}, {"v11", 88}, \ | |
2459 | {"v12", 89}, {"v13", 90}, {"v14", 91}, {"v15", 92}, \ | |
2460 | {"v16", 93}, {"v17", 94}, {"v18", 95}, {"v19", 96}, \ | |
2461 | {"v20", 97}, {"v21", 98}, {"v22", 99}, {"v23", 100}, \ | |
2462 | {"v24", 101},{"v25", 102},{"v26", 103},{"v27", 104}, \ | |
2463 | {"v28", 105},{"v29", 106},{"v30", 107},{"v31", 108}, \ | |
5f004351 | 2464 | {"vrsave", 109}, {"vscr", 110}, \ |
a3170dc6 | 2465 | {"spe_acc", 111}, {"spefscr", 112}, \ |
c4d38ccb MM |
2466 | /* no additional names for: mq, lr, ctr, ap */ \ |
2467 | {"cr0", 68}, {"cr1", 69}, {"cr2", 70}, {"cr3", 71}, \ | |
2468 | {"cr4", 72}, {"cr5", 73}, {"cr6", 74}, {"cr7", 75}, \ | |
2469 | {"cc", 68}, {"sp", 1}, {"toc", 2} } | |
f045b2c9 | 2470 | |
0da40b09 RK |
2471 | /* Text to write out after a CALL that may be replaced by glue code by |
2472 | the loader. This depends on the AIX version. */ | |
2473 | #define RS6000_CALL_GLUE "cror 31,31,31" | |
11117bb9 | 2474 | |
f045b2c9 RS |
2475 | /* This is how to output an element of a case-vector that is relative. */ |
2476 | ||
e1565e65 | 2477 | #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ |
3daf36a4 | 2478 | do { char buf[100]; \ |
e1565e65 | 2479 | fputs ("\t.long ", FILE); \ |
3daf36a4 ILT |
2480 | ASM_GENERATE_INTERNAL_LABEL (buf, "L", VALUE); \ |
2481 | assemble_name (FILE, buf); \ | |
19d2d16f | 2482 | putc ('-', FILE); \ |
3daf36a4 ILT |
2483 | ASM_GENERATE_INTERNAL_LABEL (buf, "L", REL); \ |
2484 | assemble_name (FILE, buf); \ | |
19d2d16f | 2485 | putc ('\n', FILE); \ |
3daf36a4 | 2486 | } while (0) |
f045b2c9 RS |
2487 | |
2488 | /* This is how to output an assembler line | |
2489 | that says to advance the location counter | |
2490 | to a multiple of 2**LOG bytes. */ | |
2491 | ||
2492 | #define ASM_OUTPUT_ALIGN(FILE,LOG) \ | |
2493 | if ((LOG) != 0) \ | |
2494 | fprintf (FILE, "\t.align %d\n", (LOG)) | |
2495 | ||
9ebbca7d GK |
2496 | /* Pick up the return address upon entry to a procedure. Used for |
2497 | dwarf2 unwind information. This also enables the table driven | |
2498 | mechanism. */ | |
2499 | ||
2500 | #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM) | |
8034da37 | 2501 | #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LINK_REGISTER_REGNUM) |
9ebbca7d | 2502 | |
83720594 RH |
2503 | /* Describe how we implement __builtin_eh_return. */ |
2504 | #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 3 : INVALID_REGNUM) | |
2505 | #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 10) | |
2506 | ||
f045b2c9 RS |
2507 | /* Print operand X (an rtx) in assembler syntax to file FILE. |
2508 | CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. | |
2509 | For `%' followed by punctuation, CODE is the punctuation and X is null. */ | |
2510 | ||
2511 | #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE) | |
2512 | ||
2513 | /* Define which CODE values are valid. */ | |
2514 | ||
c81bebd7 | 2515 | #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \ |
c4501e62 | 2516 | ((CODE) == '.' || (CODE) == '&') |
f045b2c9 RS |
2517 | |
2518 | /* Print a memory address as an operand to reference that memory location. */ | |
2519 | ||
2520 | #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR) | |
2521 | ||
2522 | /* Define the codes that are matched by predicates in rs6000.c. */ | |
2523 | ||
39a10a29 | 2524 | #define PREDICATE_CODES \ |
a65c591c | 2525 | {"any_operand", {CONST_INT, CONST_DOUBLE, CONST, SYMBOL_REF, \ |
df15fbc7 | 2526 | LABEL_REF, SUBREG, REG, MEM, PARALLEL}}, \ |
a65c591c DE |
2527 | {"zero_constant", {CONST_INT, CONST_DOUBLE, CONST, SYMBOL_REF, \ |
2528 | LABEL_REF, SUBREG, REG, MEM}}, \ | |
39a10a29 GK |
2529 | {"short_cint_operand", {CONST_INT}}, \ |
2530 | {"u_short_cint_operand", {CONST_INT}}, \ | |
2531 | {"non_short_cint_operand", {CONST_INT}}, \ | |
2bfcf297 | 2532 | {"exact_log2_cint_operand", {CONST_INT}}, \ |
39a10a29 GK |
2533 | {"gpc_reg_operand", {SUBREG, REG}}, \ |
2534 | {"cc_reg_operand", {SUBREG, REG}}, \ | |
2535 | {"cc_reg_not_cr0_operand", {SUBREG, REG}}, \ | |
2536 | {"reg_or_short_operand", {SUBREG, REG, CONST_INT}}, \ | |
2537 | {"reg_or_neg_short_operand", {SUBREG, REG, CONST_INT}}, \ | |
768070a0 | 2538 | {"reg_or_aligned_short_operand", {SUBREG, REG, CONST_INT}}, \ |
39a10a29 GK |
2539 | {"reg_or_u_short_operand", {SUBREG, REG, CONST_INT}}, \ |
2540 | {"reg_or_cint_operand", {SUBREG, REG, CONST_INT}}, \ | |
2541 | {"reg_or_arith_cint_operand", {SUBREG, REG, CONST_INT}}, \ | |
2bfcf297 DB |
2542 | {"reg_or_add_cint64_operand", {SUBREG, REG, CONST_INT}}, \ |
2543 | {"reg_or_sub_cint64_operand", {SUBREG, REG, CONST_INT}}, \ | |
1d328b19 | 2544 | {"reg_or_logical_cint_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \ |
39a10a29 GK |
2545 | {"got_operand", {SYMBOL_REF, CONST, LABEL_REF}}, \ |
2546 | {"got_no_const_operand", {SYMBOL_REF, LABEL_REF}}, \ | |
2547 | {"easy_fp_constant", {CONST_DOUBLE}}, \ | |
d744e06e AH |
2548 | {"easy_vector_constant", {CONST_VECTOR}}, \ |
2549 | {"easy_vector_constant_add_self", {CONST_VECTOR}}, \ | |
50a0b056 | 2550 | {"zero_fp_constant", {CONST_DOUBLE}}, \ |
39a10a29 GK |
2551 | {"reg_or_mem_operand", {SUBREG, MEM, REG}}, \ |
2552 | {"lwa_operand", {SUBREG, MEM, REG}}, \ | |
2553 | {"volatile_mem_operand", {MEM}}, \ | |
2554 | {"offsettable_mem_operand", {MEM}}, \ | |
2555 | {"mem_or_easy_const_operand", {SUBREG, MEM, CONST_DOUBLE}}, \ | |
2556 | {"add_operand", {SUBREG, REG, CONST_INT}}, \ | |
2557 | {"non_add_cint_operand", {CONST_INT}}, \ | |
2558 | {"and_operand", {SUBREG, REG, CONST_INT}}, \ | |
2559 | {"and64_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \ | |
0ba1b2ff | 2560 | {"and64_2_operand", {SUBREG, REG, CONST_INT}}, \ |
39a10a29 GK |
2561 | {"logical_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \ |
2562 | {"non_logical_cint_operand", {CONST_INT, CONST_DOUBLE}}, \ | |
2563 | {"mask_operand", {CONST_INT}}, \ | |
0ba1b2ff AM |
2564 | {"mask_operand_wrap", {CONST_INT}}, \ |
2565 | {"mask64_operand", {CONST_INT}}, \ | |
2566 | {"mask64_2_operand", {CONST_INT}}, \ | |
39a10a29 GK |
2567 | {"count_register_operand", {REG}}, \ |
2568 | {"xer_operand", {REG}}, \ | |
cc4d5fec | 2569 | {"symbol_ref_operand", {SYMBOL_REF}}, \ |
c4501e62 | 2570 | {"rs6000_tls_symbol_ref", {SYMBOL_REF}}, \ |
39a10a29 GK |
2571 | {"call_operand", {SYMBOL_REF, REG}}, \ |
2572 | {"current_file_function_operand", {SYMBOL_REF}}, \ | |
2573 | {"input_operand", {SUBREG, MEM, REG, CONST_INT, \ | |
2574 | CONST_DOUBLE, SYMBOL_REF}}, \ | |
2575 | {"load_multiple_operation", {PARALLEL}}, \ | |
2576 | {"store_multiple_operation", {PARALLEL}}, \ | |
00b960c7 | 2577 | {"vrsave_operation", {PARALLEL}}, \ |
39a10a29 GK |
2578 | {"branch_comparison_operator", {EQ, NE, LE, LT, GE, \ |
2579 | GT, LEU, LTU, GEU, GTU, \ | |
2580 | UNORDERED, ORDERED, \ | |
2581 | UNGE, UNLE }}, \ | |
2582 | {"branch_positive_comparison_operator", {EQ, LT, GT, LTU, GTU, \ | |
2583 | UNORDERED }}, \ | |
2584 | {"scc_comparison_operator", {EQ, NE, LE, LT, GE, \ | |
2585 | GT, LEU, LTU, GEU, GTU, \ | |
2586 | UNORDERED, ORDERED, \ | |
2587 | UNGE, UNLE }}, \ | |
2588 | {"trap_comparison_operator", {EQ, NE, LE, LT, GE, \ | |
2589 | GT, LEU, LTU, GEU, GTU}}, \ | |
2590 | {"boolean_operator", {AND, IOR, XOR}}, \ | |
50a0b056 | 2591 | {"boolean_or_operator", {IOR, XOR}}, \ |
0ec4e2a8 | 2592 | {"altivec_register_operand", {REG}}, \ |
50a0b056 | 2593 | {"min_max_operator", {SMIN, SMAX, UMIN, UMAX}}, |
75814ad4 | 2594 | |
b6c9286a MM |
2595 | /* uncomment for disabling the corresponding default options */ |
2596 | /* #define MACHINE_no_sched_interblock */ | |
2597 | /* #define MACHINE_no_sched_speculative */ | |
2598 | /* #define MACHINE_no_sched_speculative_load */ | |
2599 | ||
766a866c MM |
2600 | /* General flags. */ |
2601 | extern int flag_pic; | |
354b734b MM |
2602 | extern int optimize; |
2603 | extern int flag_expensive_optimizations; | |
a7df97e6 | 2604 | extern int frame_pointer_needed; |
0ac081f6 AH |
2605 | |
2606 | enum rs6000_builtins | |
2607 | { | |
2608 | /* AltiVec builtins. */ | |
f18c054f DB |
2609 | ALTIVEC_BUILTIN_ST_INTERNAL_4si, |
2610 | ALTIVEC_BUILTIN_LD_INTERNAL_4si, | |
2611 | ALTIVEC_BUILTIN_ST_INTERNAL_8hi, | |
2612 | ALTIVEC_BUILTIN_LD_INTERNAL_8hi, | |
2613 | ALTIVEC_BUILTIN_ST_INTERNAL_16qi, | |
2614 | ALTIVEC_BUILTIN_LD_INTERNAL_16qi, | |
2615 | ALTIVEC_BUILTIN_ST_INTERNAL_4sf, | |
2616 | ALTIVEC_BUILTIN_LD_INTERNAL_4sf, | |
0ac081f6 AH |
2617 | ALTIVEC_BUILTIN_VADDUBM, |
2618 | ALTIVEC_BUILTIN_VADDUHM, | |
2619 | ALTIVEC_BUILTIN_VADDUWM, | |
2620 | ALTIVEC_BUILTIN_VADDFP, | |
2621 | ALTIVEC_BUILTIN_VADDCUW, | |
2622 | ALTIVEC_BUILTIN_VADDUBS, | |
2623 | ALTIVEC_BUILTIN_VADDSBS, | |
2624 | ALTIVEC_BUILTIN_VADDUHS, | |
2625 | ALTIVEC_BUILTIN_VADDSHS, | |
2626 | ALTIVEC_BUILTIN_VADDUWS, | |
2627 | ALTIVEC_BUILTIN_VADDSWS, | |
2628 | ALTIVEC_BUILTIN_VAND, | |
2629 | ALTIVEC_BUILTIN_VANDC, | |
2630 | ALTIVEC_BUILTIN_VAVGUB, | |
2631 | ALTIVEC_BUILTIN_VAVGSB, | |
2632 | ALTIVEC_BUILTIN_VAVGUH, | |
2633 | ALTIVEC_BUILTIN_VAVGSH, | |
2634 | ALTIVEC_BUILTIN_VAVGUW, | |
2635 | ALTIVEC_BUILTIN_VAVGSW, | |
617e0e1d DB |
2636 | ALTIVEC_BUILTIN_VCFUX, |
2637 | ALTIVEC_BUILTIN_VCFSX, | |
2638 | ALTIVEC_BUILTIN_VCTSXS, | |
2639 | ALTIVEC_BUILTIN_VCTUXS, | |
0ac081f6 AH |
2640 | ALTIVEC_BUILTIN_VCMPBFP, |
2641 | ALTIVEC_BUILTIN_VCMPEQUB, | |
2642 | ALTIVEC_BUILTIN_VCMPEQUH, | |
2643 | ALTIVEC_BUILTIN_VCMPEQUW, | |
2644 | ALTIVEC_BUILTIN_VCMPEQFP, | |
2645 | ALTIVEC_BUILTIN_VCMPGEFP, | |
2646 | ALTIVEC_BUILTIN_VCMPGTUB, | |
2647 | ALTIVEC_BUILTIN_VCMPGTSB, | |
2648 | ALTIVEC_BUILTIN_VCMPGTUH, | |
2649 | ALTIVEC_BUILTIN_VCMPGTSH, | |
2650 | ALTIVEC_BUILTIN_VCMPGTUW, | |
2651 | ALTIVEC_BUILTIN_VCMPGTSW, | |
2652 | ALTIVEC_BUILTIN_VCMPGTFP, | |
617e0e1d DB |
2653 | ALTIVEC_BUILTIN_VEXPTEFP, |
2654 | ALTIVEC_BUILTIN_VLOGEFP, | |
2212663f | 2655 | ALTIVEC_BUILTIN_VMADDFP, |
0ac081f6 AH |
2656 | ALTIVEC_BUILTIN_VMAXUB, |
2657 | ALTIVEC_BUILTIN_VMAXSB, | |
2658 | ALTIVEC_BUILTIN_VMAXUH, | |
2659 | ALTIVEC_BUILTIN_VMAXSH, | |
2660 | ALTIVEC_BUILTIN_VMAXUW, | |
2661 | ALTIVEC_BUILTIN_VMAXSW, | |
2662 | ALTIVEC_BUILTIN_VMAXFP, | |
2212663f DB |
2663 | ALTIVEC_BUILTIN_VMHADDSHS, |
2664 | ALTIVEC_BUILTIN_VMHRADDSHS, | |
2665 | ALTIVEC_BUILTIN_VMLADDUHM, | |
0ac081f6 AH |
2666 | ALTIVEC_BUILTIN_VMRGHB, |
2667 | ALTIVEC_BUILTIN_VMRGHH, | |
2668 | ALTIVEC_BUILTIN_VMRGHW, | |
2669 | ALTIVEC_BUILTIN_VMRGLB, | |
2670 | ALTIVEC_BUILTIN_VMRGLH, | |
2671 | ALTIVEC_BUILTIN_VMRGLW, | |
2212663f DB |
2672 | ALTIVEC_BUILTIN_VMSUMUBM, |
2673 | ALTIVEC_BUILTIN_VMSUMMBM, | |
2674 | ALTIVEC_BUILTIN_VMSUMUHM, | |
2675 | ALTIVEC_BUILTIN_VMSUMSHM, | |
2676 | ALTIVEC_BUILTIN_VMSUMUHS, | |
2677 | ALTIVEC_BUILTIN_VMSUMSHS, | |
0ac081f6 AH |
2678 | ALTIVEC_BUILTIN_VMINUB, |
2679 | ALTIVEC_BUILTIN_VMINSB, | |
2680 | ALTIVEC_BUILTIN_VMINUH, | |
2681 | ALTIVEC_BUILTIN_VMINSH, | |
2682 | ALTIVEC_BUILTIN_VMINUW, | |
2683 | ALTIVEC_BUILTIN_VMINSW, | |
2684 | ALTIVEC_BUILTIN_VMINFP, | |
2685 | ALTIVEC_BUILTIN_VMULEUB, | |
2686 | ALTIVEC_BUILTIN_VMULESB, | |
2687 | ALTIVEC_BUILTIN_VMULEUH, | |
2688 | ALTIVEC_BUILTIN_VMULESH, | |
2689 | ALTIVEC_BUILTIN_VMULOUB, | |
2690 | ALTIVEC_BUILTIN_VMULOSB, | |
2691 | ALTIVEC_BUILTIN_VMULOUH, | |
2692 | ALTIVEC_BUILTIN_VMULOSH, | |
2212663f | 2693 | ALTIVEC_BUILTIN_VNMSUBFP, |
0ac081f6 AH |
2694 | ALTIVEC_BUILTIN_VNOR, |
2695 | ALTIVEC_BUILTIN_VOR, | |
617e0e1d DB |
2696 | ALTIVEC_BUILTIN_VSEL_4SI, |
2697 | ALTIVEC_BUILTIN_VSEL_4SF, | |
2698 | ALTIVEC_BUILTIN_VSEL_8HI, | |
2699 | ALTIVEC_BUILTIN_VSEL_16QI, | |
2212663f DB |
2700 | ALTIVEC_BUILTIN_VPERM_4SI, |
2701 | ALTIVEC_BUILTIN_VPERM_4SF, | |
2702 | ALTIVEC_BUILTIN_VPERM_8HI, | |
2703 | ALTIVEC_BUILTIN_VPERM_16QI, | |
0ac081f6 AH |
2704 | ALTIVEC_BUILTIN_VPKUHUM, |
2705 | ALTIVEC_BUILTIN_VPKUWUM, | |
2706 | ALTIVEC_BUILTIN_VPKPX, | |
2707 | ALTIVEC_BUILTIN_VPKUHSS, | |
2708 | ALTIVEC_BUILTIN_VPKSHSS, | |
2709 | ALTIVEC_BUILTIN_VPKUWSS, | |
2710 | ALTIVEC_BUILTIN_VPKSWSS, | |
2711 | ALTIVEC_BUILTIN_VPKUHUS, | |
2712 | ALTIVEC_BUILTIN_VPKSHUS, | |
2713 | ALTIVEC_BUILTIN_VPKUWUS, | |
2714 | ALTIVEC_BUILTIN_VPKSWUS, | |
617e0e1d DB |
2715 | ALTIVEC_BUILTIN_VREFP, |
2716 | ALTIVEC_BUILTIN_VRFIM, | |
2717 | ALTIVEC_BUILTIN_VRFIN, | |
2718 | ALTIVEC_BUILTIN_VRFIP, | |
2719 | ALTIVEC_BUILTIN_VRFIZ, | |
0ac081f6 AH |
2720 | ALTIVEC_BUILTIN_VRLB, |
2721 | ALTIVEC_BUILTIN_VRLH, | |
2722 | ALTIVEC_BUILTIN_VRLW, | |
617e0e1d | 2723 | ALTIVEC_BUILTIN_VRSQRTEFP, |
0ac081f6 AH |
2724 | ALTIVEC_BUILTIN_VSLB, |
2725 | ALTIVEC_BUILTIN_VSLH, | |
2726 | ALTIVEC_BUILTIN_VSLW, | |
2727 | ALTIVEC_BUILTIN_VSL, | |
2728 | ALTIVEC_BUILTIN_VSLO, | |
2212663f DB |
2729 | ALTIVEC_BUILTIN_VSPLTB, |
2730 | ALTIVEC_BUILTIN_VSPLTH, | |
2731 | ALTIVEC_BUILTIN_VSPLTW, | |
2732 | ALTIVEC_BUILTIN_VSPLTISB, | |
2733 | ALTIVEC_BUILTIN_VSPLTISH, | |
2734 | ALTIVEC_BUILTIN_VSPLTISW, | |
0ac081f6 | 2735 | ALTIVEC_BUILTIN_VSRB, |
f18c054f DB |
2736 | ALTIVEC_BUILTIN_VSRH, |
2737 | ALTIVEC_BUILTIN_VSRW, | |
0ac081f6 AH |
2738 | ALTIVEC_BUILTIN_VSRAB, |
2739 | ALTIVEC_BUILTIN_VSRAH, | |
2740 | ALTIVEC_BUILTIN_VSRAW, | |
2741 | ALTIVEC_BUILTIN_VSR, | |
2742 | ALTIVEC_BUILTIN_VSRO, | |
2743 | ALTIVEC_BUILTIN_VSUBUBM, | |
2744 | ALTIVEC_BUILTIN_VSUBUHM, | |
2745 | ALTIVEC_BUILTIN_VSUBUWM, | |
2746 | ALTIVEC_BUILTIN_VSUBFP, | |
2747 | ALTIVEC_BUILTIN_VSUBCUW, | |
2748 | ALTIVEC_BUILTIN_VSUBUBS, | |
2749 | ALTIVEC_BUILTIN_VSUBSBS, | |
2750 | ALTIVEC_BUILTIN_VSUBUHS, | |
2751 | ALTIVEC_BUILTIN_VSUBSHS, | |
2752 | ALTIVEC_BUILTIN_VSUBUWS, | |
2753 | ALTIVEC_BUILTIN_VSUBSWS, | |
2754 | ALTIVEC_BUILTIN_VSUM4UBS, | |
2755 | ALTIVEC_BUILTIN_VSUM4SBS, | |
2756 | ALTIVEC_BUILTIN_VSUM4SHS, | |
2757 | ALTIVEC_BUILTIN_VSUM2SWS, | |
2758 | ALTIVEC_BUILTIN_VSUMSWS, | |
24408032 AH |
2759 | ALTIVEC_BUILTIN_VXOR, |
2760 | ALTIVEC_BUILTIN_VSLDOI_16QI, | |
2761 | ALTIVEC_BUILTIN_VSLDOI_8HI, | |
2762 | ALTIVEC_BUILTIN_VSLDOI_4SI, | |
20e26713 AH |
2763 | ALTIVEC_BUILTIN_VSLDOI_4SF, |
2764 | ALTIVEC_BUILTIN_VUPKHSB, | |
2765 | ALTIVEC_BUILTIN_VUPKHPX, | |
2766 | ALTIVEC_BUILTIN_VUPKHSH, | |
2767 | ALTIVEC_BUILTIN_VUPKLSB, | |
2768 | ALTIVEC_BUILTIN_VUPKLPX, | |
fa066a23 | 2769 | ALTIVEC_BUILTIN_VUPKLSH, |
95385cbb AH |
2770 | ALTIVEC_BUILTIN_MTVSCR, |
2771 | ALTIVEC_BUILTIN_MFVSCR, | |
2772 | ALTIVEC_BUILTIN_DSSALL, | |
2773 | ALTIVEC_BUILTIN_DSS, | |
2774 | ALTIVEC_BUILTIN_LVSL, | |
2775 | ALTIVEC_BUILTIN_LVSR, | |
2776 | ALTIVEC_BUILTIN_DSTT, | |
2777 | ALTIVEC_BUILTIN_DSTST, | |
2778 | ALTIVEC_BUILTIN_DSTSTT, | |
6525c0e7 AH |
2779 | ALTIVEC_BUILTIN_DST, |
2780 | ALTIVEC_BUILTIN_LVEBX, | |
2781 | ALTIVEC_BUILTIN_LVEHX, | |
2782 | ALTIVEC_BUILTIN_LVEWX, | |
2783 | ALTIVEC_BUILTIN_LVXL, | |
2784 | ALTIVEC_BUILTIN_LVX, | |
2785 | ALTIVEC_BUILTIN_STVX, | |
2786 | ALTIVEC_BUILTIN_STVEBX, | |
2787 | ALTIVEC_BUILTIN_STVEHX, | |
2788 | ALTIVEC_BUILTIN_STVEWX, | |
ae4b4a02 AH |
2789 | ALTIVEC_BUILTIN_STVXL, |
2790 | ALTIVEC_BUILTIN_VCMPBFP_P, | |
2791 | ALTIVEC_BUILTIN_VCMPEQFP_P, | |
2792 | ALTIVEC_BUILTIN_VCMPEQUB_P, | |
2793 | ALTIVEC_BUILTIN_VCMPEQUH_P, | |
2794 | ALTIVEC_BUILTIN_VCMPEQUW_P, | |
2795 | ALTIVEC_BUILTIN_VCMPGEFP_P, | |
2796 | ALTIVEC_BUILTIN_VCMPGTFP_P, | |
2797 | ALTIVEC_BUILTIN_VCMPGTSB_P, | |
2798 | ALTIVEC_BUILTIN_VCMPGTSH_P, | |
2799 | ALTIVEC_BUILTIN_VCMPGTSW_P, | |
2800 | ALTIVEC_BUILTIN_VCMPGTUB_P, | |
2801 | ALTIVEC_BUILTIN_VCMPGTUH_P, | |
100c4561 AH |
2802 | ALTIVEC_BUILTIN_VCMPGTUW_P, |
2803 | ALTIVEC_BUILTIN_ABSS_V4SI, | |
2804 | ALTIVEC_BUILTIN_ABSS_V8HI, | |
2805 | ALTIVEC_BUILTIN_ABSS_V16QI, | |
2806 | ALTIVEC_BUILTIN_ABS_V4SI, | |
2807 | ALTIVEC_BUILTIN_ABS_V4SF, | |
2808 | ALTIVEC_BUILTIN_ABS_V8HI, | |
8bb418a3 ZL |
2809 | ALTIVEC_BUILTIN_ABS_V16QI, |
2810 | ALTIVEC_BUILTIN_COMPILETIME_ERROR, | |
2811 | ||
a3170dc6 | 2812 | /* SPE builtins. */ |
8bb418a3 | 2813 | SPE_BUILTIN_EVADDW, |
a3170dc6 AH |
2814 | SPE_BUILTIN_EVAND, |
2815 | SPE_BUILTIN_EVANDC, | |
2816 | SPE_BUILTIN_EVDIVWS, | |
2817 | SPE_BUILTIN_EVDIVWU, | |
2818 | SPE_BUILTIN_EVEQV, | |
2819 | SPE_BUILTIN_EVFSADD, | |
2820 | SPE_BUILTIN_EVFSDIV, | |
2821 | SPE_BUILTIN_EVFSMUL, | |
2822 | SPE_BUILTIN_EVFSSUB, | |
2823 | SPE_BUILTIN_EVLDDX, | |
2824 | SPE_BUILTIN_EVLDHX, | |
2825 | SPE_BUILTIN_EVLDWX, | |
2826 | SPE_BUILTIN_EVLHHESPLATX, | |
2827 | SPE_BUILTIN_EVLHHOSSPLATX, | |
2828 | SPE_BUILTIN_EVLHHOUSPLATX, | |
2829 | SPE_BUILTIN_EVLWHEX, | |
2830 | SPE_BUILTIN_EVLWHOSX, | |
2831 | SPE_BUILTIN_EVLWHOUX, | |
2832 | SPE_BUILTIN_EVLWHSPLATX, | |
2833 | SPE_BUILTIN_EVLWWSPLATX, | |
2834 | SPE_BUILTIN_EVMERGEHI, | |
2835 | SPE_BUILTIN_EVMERGEHILO, | |
2836 | SPE_BUILTIN_EVMERGELO, | |
2837 | SPE_BUILTIN_EVMERGELOHI, | |
2838 | SPE_BUILTIN_EVMHEGSMFAA, | |
2839 | SPE_BUILTIN_EVMHEGSMFAN, | |
2840 | SPE_BUILTIN_EVMHEGSMIAA, | |
2841 | SPE_BUILTIN_EVMHEGSMIAN, | |
2842 | SPE_BUILTIN_EVMHEGUMIAA, | |
2843 | SPE_BUILTIN_EVMHEGUMIAN, | |
2844 | SPE_BUILTIN_EVMHESMF, | |
2845 | SPE_BUILTIN_EVMHESMFA, | |
2846 | SPE_BUILTIN_EVMHESMFAAW, | |
2847 | SPE_BUILTIN_EVMHESMFANW, | |
2848 | SPE_BUILTIN_EVMHESMI, | |
2849 | SPE_BUILTIN_EVMHESMIA, | |
2850 | SPE_BUILTIN_EVMHESMIAAW, | |
2851 | SPE_BUILTIN_EVMHESMIANW, | |
2852 | SPE_BUILTIN_EVMHESSF, | |
2853 | SPE_BUILTIN_EVMHESSFA, | |
2854 | SPE_BUILTIN_EVMHESSFAAW, | |
2855 | SPE_BUILTIN_EVMHESSFANW, | |
2856 | SPE_BUILTIN_EVMHESSIAAW, | |
2857 | SPE_BUILTIN_EVMHESSIANW, | |
2858 | SPE_BUILTIN_EVMHEUMI, | |
2859 | SPE_BUILTIN_EVMHEUMIA, | |
2860 | SPE_BUILTIN_EVMHEUMIAAW, | |
2861 | SPE_BUILTIN_EVMHEUMIANW, | |
2862 | SPE_BUILTIN_EVMHEUSIAAW, | |
2863 | SPE_BUILTIN_EVMHEUSIANW, | |
2864 | SPE_BUILTIN_EVMHOGSMFAA, | |
2865 | SPE_BUILTIN_EVMHOGSMFAN, | |
2866 | SPE_BUILTIN_EVMHOGSMIAA, | |
2867 | SPE_BUILTIN_EVMHOGSMIAN, | |
2868 | SPE_BUILTIN_EVMHOGUMIAA, | |
2869 | SPE_BUILTIN_EVMHOGUMIAN, | |
2870 | SPE_BUILTIN_EVMHOSMF, | |
2871 | SPE_BUILTIN_EVMHOSMFA, | |
2872 | SPE_BUILTIN_EVMHOSMFAAW, | |
2873 | SPE_BUILTIN_EVMHOSMFANW, | |
2874 | SPE_BUILTIN_EVMHOSMI, | |
2875 | SPE_BUILTIN_EVMHOSMIA, | |
2876 | SPE_BUILTIN_EVMHOSMIAAW, | |
2877 | SPE_BUILTIN_EVMHOSMIANW, | |
2878 | SPE_BUILTIN_EVMHOSSF, | |
2879 | SPE_BUILTIN_EVMHOSSFA, | |
2880 | SPE_BUILTIN_EVMHOSSFAAW, | |
2881 | SPE_BUILTIN_EVMHOSSFANW, | |
2882 | SPE_BUILTIN_EVMHOSSIAAW, | |
2883 | SPE_BUILTIN_EVMHOSSIANW, | |
2884 | SPE_BUILTIN_EVMHOUMI, | |
2885 | SPE_BUILTIN_EVMHOUMIA, | |
2886 | SPE_BUILTIN_EVMHOUMIAAW, | |
2887 | SPE_BUILTIN_EVMHOUMIANW, | |
2888 | SPE_BUILTIN_EVMHOUSIAAW, | |
2889 | SPE_BUILTIN_EVMHOUSIANW, | |
2890 | SPE_BUILTIN_EVMWHSMF, | |
2891 | SPE_BUILTIN_EVMWHSMFA, | |
2892 | SPE_BUILTIN_EVMWHSMI, | |
2893 | SPE_BUILTIN_EVMWHSMIA, | |
2894 | SPE_BUILTIN_EVMWHSSF, | |
2895 | SPE_BUILTIN_EVMWHSSFA, | |
2896 | SPE_BUILTIN_EVMWHUMI, | |
2897 | SPE_BUILTIN_EVMWHUMIA, | |
a3170dc6 AH |
2898 | SPE_BUILTIN_EVMWLSMIAAW, |
2899 | SPE_BUILTIN_EVMWLSMIANW, | |
a3170dc6 AH |
2900 | SPE_BUILTIN_EVMWLSSIAAW, |
2901 | SPE_BUILTIN_EVMWLSSIANW, | |
2902 | SPE_BUILTIN_EVMWLUMI, | |
2903 | SPE_BUILTIN_EVMWLUMIA, | |
2904 | SPE_BUILTIN_EVMWLUMIAAW, | |
2905 | SPE_BUILTIN_EVMWLUMIANW, | |
2906 | SPE_BUILTIN_EVMWLUSIAAW, | |
2907 | SPE_BUILTIN_EVMWLUSIANW, | |
2908 | SPE_BUILTIN_EVMWSMF, | |
2909 | SPE_BUILTIN_EVMWSMFA, | |
2910 | SPE_BUILTIN_EVMWSMFAA, | |
2911 | SPE_BUILTIN_EVMWSMFAN, | |
2912 | SPE_BUILTIN_EVMWSMI, | |
2913 | SPE_BUILTIN_EVMWSMIA, | |
2914 | SPE_BUILTIN_EVMWSMIAA, | |
2915 | SPE_BUILTIN_EVMWSMIAN, | |
2916 | SPE_BUILTIN_EVMWHSSFAA, | |
2917 | SPE_BUILTIN_EVMWSSF, | |
2918 | SPE_BUILTIN_EVMWSSFA, | |
2919 | SPE_BUILTIN_EVMWSSFAA, | |
2920 | SPE_BUILTIN_EVMWSSFAN, | |
2921 | SPE_BUILTIN_EVMWUMI, | |
2922 | SPE_BUILTIN_EVMWUMIA, | |
2923 | SPE_BUILTIN_EVMWUMIAA, | |
2924 | SPE_BUILTIN_EVMWUMIAN, | |
2925 | SPE_BUILTIN_EVNAND, | |
2926 | SPE_BUILTIN_EVNOR, | |
2927 | SPE_BUILTIN_EVOR, | |
2928 | SPE_BUILTIN_EVORC, | |
2929 | SPE_BUILTIN_EVRLW, | |
2930 | SPE_BUILTIN_EVSLW, | |
2931 | SPE_BUILTIN_EVSRWS, | |
2932 | SPE_BUILTIN_EVSRWU, | |
2933 | SPE_BUILTIN_EVSTDDX, | |
2934 | SPE_BUILTIN_EVSTDHX, | |
2935 | SPE_BUILTIN_EVSTDWX, | |
2936 | SPE_BUILTIN_EVSTWHEX, | |
2937 | SPE_BUILTIN_EVSTWHOX, | |
2938 | SPE_BUILTIN_EVSTWWEX, | |
2939 | SPE_BUILTIN_EVSTWWOX, | |
2940 | SPE_BUILTIN_EVSUBFW, | |
2941 | SPE_BUILTIN_EVXOR, | |
2942 | SPE_BUILTIN_EVABS, | |
2943 | SPE_BUILTIN_EVADDSMIAAW, | |
2944 | SPE_BUILTIN_EVADDSSIAAW, | |
2945 | SPE_BUILTIN_EVADDUMIAAW, | |
2946 | SPE_BUILTIN_EVADDUSIAAW, | |
2947 | SPE_BUILTIN_EVCNTLSW, | |
2948 | SPE_BUILTIN_EVCNTLZW, | |
2949 | SPE_BUILTIN_EVEXTSB, | |
2950 | SPE_BUILTIN_EVEXTSH, | |
2951 | SPE_BUILTIN_EVFSABS, | |
2952 | SPE_BUILTIN_EVFSCFSF, | |
2953 | SPE_BUILTIN_EVFSCFSI, | |
2954 | SPE_BUILTIN_EVFSCFUF, | |
2955 | SPE_BUILTIN_EVFSCFUI, | |
2956 | SPE_BUILTIN_EVFSCTSF, | |
2957 | SPE_BUILTIN_EVFSCTSI, | |
2958 | SPE_BUILTIN_EVFSCTSIZ, | |
2959 | SPE_BUILTIN_EVFSCTUF, | |
2960 | SPE_BUILTIN_EVFSCTUI, | |
2961 | SPE_BUILTIN_EVFSCTUIZ, | |
2962 | SPE_BUILTIN_EVFSNABS, | |
2963 | SPE_BUILTIN_EVFSNEG, | |
2964 | SPE_BUILTIN_EVMRA, | |
2965 | SPE_BUILTIN_EVNEG, | |
2966 | SPE_BUILTIN_EVRNDW, | |
2967 | SPE_BUILTIN_EVSUBFSMIAAW, | |
2968 | SPE_BUILTIN_EVSUBFSSIAAW, | |
2969 | SPE_BUILTIN_EVSUBFUMIAAW, | |
2970 | SPE_BUILTIN_EVSUBFUSIAAW, | |
2971 | SPE_BUILTIN_EVADDIW, | |
2972 | SPE_BUILTIN_EVLDD, | |
2973 | SPE_BUILTIN_EVLDH, | |
2974 | SPE_BUILTIN_EVLDW, | |
2975 | SPE_BUILTIN_EVLHHESPLAT, | |
2976 | SPE_BUILTIN_EVLHHOSSPLAT, | |
2977 | SPE_BUILTIN_EVLHHOUSPLAT, | |
2978 | SPE_BUILTIN_EVLWHE, | |
2979 | SPE_BUILTIN_EVLWHOS, | |
2980 | SPE_BUILTIN_EVLWHOU, | |
2981 | SPE_BUILTIN_EVLWHSPLAT, | |
2982 | SPE_BUILTIN_EVLWWSPLAT, | |
2983 | SPE_BUILTIN_EVRLWI, | |
2984 | SPE_BUILTIN_EVSLWI, | |
2985 | SPE_BUILTIN_EVSRWIS, | |
2986 | SPE_BUILTIN_EVSRWIU, | |
2987 | SPE_BUILTIN_EVSTDD, | |
2988 | SPE_BUILTIN_EVSTDH, | |
2989 | SPE_BUILTIN_EVSTDW, | |
2990 | SPE_BUILTIN_EVSTWHE, | |
2991 | SPE_BUILTIN_EVSTWHO, | |
2992 | SPE_BUILTIN_EVSTWWE, | |
2993 | SPE_BUILTIN_EVSTWWO, | |
2994 | SPE_BUILTIN_EVSUBIFW, | |
2995 | ||
2996 | /* Compares. */ | |
2997 | SPE_BUILTIN_EVCMPEQ, | |
2998 | SPE_BUILTIN_EVCMPGTS, | |
2999 | SPE_BUILTIN_EVCMPGTU, | |
3000 | SPE_BUILTIN_EVCMPLTS, | |
3001 | SPE_BUILTIN_EVCMPLTU, | |
3002 | SPE_BUILTIN_EVFSCMPEQ, | |
3003 | SPE_BUILTIN_EVFSCMPGT, | |
3004 | SPE_BUILTIN_EVFSCMPLT, | |
3005 | SPE_BUILTIN_EVFSTSTEQ, | |
3006 | SPE_BUILTIN_EVFSTSTGT, | |
3007 | SPE_BUILTIN_EVFSTSTLT, | |
3008 | ||
3009 | /* EVSEL compares. */ | |
3010 | SPE_BUILTIN_EVSEL_CMPEQ, | |
3011 | SPE_BUILTIN_EVSEL_CMPGTS, | |
3012 | SPE_BUILTIN_EVSEL_CMPGTU, | |
3013 | SPE_BUILTIN_EVSEL_CMPLTS, | |
3014 | SPE_BUILTIN_EVSEL_CMPLTU, | |
3015 | SPE_BUILTIN_EVSEL_FSCMPEQ, | |
3016 | SPE_BUILTIN_EVSEL_FSCMPGT, | |
3017 | SPE_BUILTIN_EVSEL_FSCMPLT, | |
3018 | SPE_BUILTIN_EVSEL_FSTSTEQ, | |
3019 | SPE_BUILTIN_EVSEL_FSTSTGT, | |
3020 | SPE_BUILTIN_EVSEL_FSTSTLT, | |
3021 | ||
3022 | SPE_BUILTIN_EVSPLATFI, | |
3023 | SPE_BUILTIN_EVSPLATI, | |
3024 | SPE_BUILTIN_EVMWHSSMAA, | |
3025 | SPE_BUILTIN_EVMWHSMFAA, | |
3026 | SPE_BUILTIN_EVMWHSMIAA, | |
3027 | SPE_BUILTIN_EVMWHUSIAA, | |
3028 | SPE_BUILTIN_EVMWHUMIAA, | |
3029 | SPE_BUILTIN_EVMWHSSFAN, | |
3030 | SPE_BUILTIN_EVMWHSSIAN, | |
3031 | SPE_BUILTIN_EVMWHSMFAN, | |
3032 | SPE_BUILTIN_EVMWHSMIAN, | |
3033 | SPE_BUILTIN_EVMWHUSIAN, | |
3034 | SPE_BUILTIN_EVMWHUMIAN, | |
3035 | SPE_BUILTIN_EVMWHGSSFAA, | |
3036 | SPE_BUILTIN_EVMWHGSMFAA, | |
3037 | SPE_BUILTIN_EVMWHGSMIAA, | |
3038 | SPE_BUILTIN_EVMWHGUMIAA, | |
3039 | SPE_BUILTIN_EVMWHGSSFAN, | |
3040 | SPE_BUILTIN_EVMWHGSMFAN, | |
3041 | SPE_BUILTIN_EVMWHGSMIAN, | |
3042 | SPE_BUILTIN_EVMWHGUMIAN, | |
3043 | SPE_BUILTIN_MTSPEFSCR, | |
3044 | SPE_BUILTIN_MFSPEFSCR, | |
3045 | SPE_BUILTIN_BRINC | |
0ac081f6 | 3046 | }; |