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f045b2c9 | 1 | /* Definitions of target machine for GNU compiler, for IBM RS/6000. |
d1e082c2 | 2 | Copyright (C) 1992-2013 Free Software Foundation, Inc. |
6a7ec0a7 | 3 | Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu) |
f045b2c9 | 4 | |
5de601cf | 5 | This file is part of GCC. |
f045b2c9 | 6 | |
5de601cf NC |
7 | GCC is free software; you can redistribute it and/or modify it |
8 | under the terms of the GNU General Public License as published | |
2f83c7d6 | 9 | by the Free Software Foundation; either version 3, or (at your |
5de601cf | 10 | option) any later version. |
f045b2c9 | 11 | |
5de601cf NC |
12 | GCC is distributed in the hope that it will be useful, but WITHOUT |
13 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
14 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
15 | License for more details. | |
f045b2c9 | 16 | |
748086b7 JJ |
17 | Under Section 7 of GPL version 3, you are granted additional |
18 | permissions described in the GCC Runtime Library Exception, version | |
19 | 3.1, as published by the Free Software Foundation. | |
20 | ||
21 | You should have received a copy of the GNU General Public License and | |
22 | a copy of the GCC Runtime Library Exception along with this program; | |
23 | see the files COPYING3 and COPYING.RUNTIME respectively. If not, see | |
2f83c7d6 | 24 | <http://www.gnu.org/licenses/>. */ |
f045b2c9 RS |
25 | |
26 | /* Note that some other tm.h files include this one and then override | |
9ebbca7d | 27 | many of the definitions. */ |
f045b2c9 | 28 | |
fd438373 MM |
29 | #ifndef RS6000_OPTS_H |
30 | #include "config/rs6000/rs6000-opts.h" | |
31 | #endif | |
32 | ||
9ebbca7d GK |
33 | /* Definitions for the object file format. These are set at |
34 | compile-time. */ | |
f045b2c9 | 35 | |
9ebbca7d GK |
36 | #define OBJECT_XCOFF 1 |
37 | #define OBJECT_ELF 2 | |
38 | #define OBJECT_PEF 3 | |
ee890fe2 | 39 | #define OBJECT_MACHO 4 |
f045b2c9 | 40 | |
9ebbca7d | 41 | #define TARGET_ELF (TARGET_OBJECT_FORMAT == OBJECT_ELF) |
2bfcf297 | 42 | #define TARGET_XCOFF (TARGET_OBJECT_FORMAT == OBJECT_XCOFF) |
9ebbca7d | 43 | #define TARGET_MACOS (TARGET_OBJECT_FORMAT == OBJECT_PEF) |
ee890fe2 | 44 | #define TARGET_MACHO (TARGET_OBJECT_FORMAT == OBJECT_MACHO) |
f045b2c9 | 45 | |
2bfcf297 DB |
46 | #ifndef TARGET_AIX |
47 | #define TARGET_AIX 0 | |
48 | #endif | |
49 | ||
78009d9f MM |
50 | #ifndef TARGET_AIX_OS |
51 | #define TARGET_AIX_OS 0 | |
52 | #endif | |
53 | ||
85b776df AM |
54 | /* Control whether function entry points use a "dot" symbol when |
55 | ABI_AIX. */ | |
56 | #define DOT_SYMBOLS 1 | |
57 | ||
8e3f41e7 MM |
58 | /* Default string to use for cpu if not specified. */ |
59 | #ifndef TARGET_CPU_DEFAULT | |
60 | #define TARGET_CPU_DEFAULT ((char *)0) | |
61 | #endif | |
62 | ||
f565b0a1 | 63 | /* If configured for PPC405, support PPC405CR Erratum77. */ |
b0bfee6e | 64 | #ifdef CONFIG_PPC405CR |
f565b0a1 DE |
65 | #define PPC405_ERRATUM77 (rs6000_cpu == PROCESSOR_PPC405) |
66 | #else | |
67 | #define PPC405_ERRATUM77 0 | |
68 | #endif | |
69 | ||
96038623 DE |
70 | #ifndef TARGET_PAIRED_FLOAT |
71 | #define TARGET_PAIRED_FLOAT 0 | |
72 | #endif | |
73 | ||
cd679487 BE |
74 | #ifdef HAVE_AS_POPCNTB |
75 | #define ASM_CPU_POWER5_SPEC "-mpower5" | |
76 | #else | |
77 | #define ASM_CPU_POWER5_SPEC "-mpower4" | |
78 | #endif | |
79 | ||
80 | #ifdef HAVE_AS_DFP | |
81 | #define ASM_CPU_POWER6_SPEC "-mpower6 -maltivec" | |
82 | #else | |
83 | #define ASM_CPU_POWER6_SPEC "-mpower4 -maltivec" | |
84 | #endif | |
85 | ||
cacf1ca8 | 86 | #ifdef HAVE_AS_POPCNTD |
d40c9e33 PB |
87 | #define ASM_CPU_POWER7_SPEC "-mpower7" |
88 | #else | |
89 | #define ASM_CPU_POWER7_SPEC "-mpower4 -maltivec" | |
90 | #endif | |
91 | ||
428bffcb PB |
92 | #ifdef HAVE_AS_POWER8 |
93 | #define ASM_CPU_POWER8_SPEC "-mpower8" | |
94 | #else | |
f62511da | 95 | #define ASM_CPU_POWER8_SPEC ASM_CPU_POWER7_SPEC |
428bffcb PB |
96 | #endif |
97 | ||
47f67e51 PB |
98 | #ifdef HAVE_AS_DCI |
99 | #define ASM_CPU_476_SPEC "-m476" | |
100 | #else | |
101 | #define ASM_CPU_476_SPEC "-mpower4" | |
102 | #endif | |
103 | ||
cacf1ca8 MM |
104 | /* Common ASM definitions used by ASM_SPEC among the various targets for |
105 | handling -mcpu=xxx switches. There is a parallel list in driver-rs6000.c to | |
106 | provide the default assembler options if the user uses -mcpu=native, so if | |
107 | you make changes here, make them also there. */ | |
f984d8df DB |
108 | #define ASM_CPU_SPEC \ |
109 | "%{!mcpu*: \ | |
93ae5495 | 110 | %{mpowerpc64*: -mppc64} \ |
a441dedb | 111 | %{!mpowerpc64*: %(asm_default)}} \ |
cacf1ca8 | 112 | %{mcpu=native: %(asm_cpu_native)} \ |
d296e02e | 113 | %{mcpu=cell: -mcell} \ |
93ae5495 | 114 | %{mcpu=power3: -mppc64} \ |
957e9e48 | 115 | %{mcpu=power4: -mpower4} \ |
cd679487 BE |
116 | %{mcpu=power5: %(asm_cpu_power5)} \ |
117 | %{mcpu=power5+: %(asm_cpu_power5)} \ | |
118 | %{mcpu=power6: %(asm_cpu_power6) -maltivec} \ | |
119 | %{mcpu=power6x: %(asm_cpu_power6) -maltivec} \ | |
d40c9e33 | 120 | %{mcpu=power7: %(asm_cpu_power7)} \ |
428bffcb | 121 | %{mcpu=power8: %(asm_cpu_power8)} \ |
ebde32fd | 122 | %{mcpu=a2: -ma2} \ |
f984d8df | 123 | %{mcpu=powerpc: -mppc} \ |
93ae5495 | 124 | %{mcpu=rs64a: -mppc64} \ |
f984d8df | 125 | %{mcpu=401: -mppc} \ |
61a8515c JS |
126 | %{mcpu=403: -m403} \ |
127 | %{mcpu=405: -m405} \ | |
2c9d95ef DE |
128 | %{mcpu=405fp: -m405} \ |
129 | %{mcpu=440: -m440} \ | |
130 | %{mcpu=440fp: -m440} \ | |
4adf8008 PB |
131 | %{mcpu=464: -m440} \ |
132 | %{mcpu=464fp: -m440} \ | |
47f67e51 PB |
133 | %{mcpu=476: %(asm_cpu_476)} \ |
134 | %{mcpu=476fp: %(asm_cpu_476)} \ | |
f984d8df DB |
135 | %{mcpu=505: -mppc} \ |
136 | %{mcpu=601: -m601} \ | |
137 | %{mcpu=602: -mppc} \ | |
138 | %{mcpu=603: -mppc} \ | |
139 | %{mcpu=603e: -mppc} \ | |
140 | %{mcpu=ec603e: -mppc} \ | |
141 | %{mcpu=604: -mppc} \ | |
142 | %{mcpu=604e: -mppc} \ | |
93ae5495 AM |
143 | %{mcpu=620: -mppc64} \ |
144 | %{mcpu=630: -mppc64} \ | |
f984d8df DB |
145 | %{mcpu=740: -mppc} \ |
146 | %{mcpu=750: -mppc} \ | |
49ffe578 | 147 | %{mcpu=G3: -mppc} \ |
93ae5495 AM |
148 | %{mcpu=7400: -mppc -maltivec} \ |
149 | %{mcpu=7450: -mppc -maltivec} \ | |
150 | %{mcpu=G4: -mppc -maltivec} \ | |
f984d8df DB |
151 | %{mcpu=801: -mppc} \ |
152 | %{mcpu=821: -mppc} \ | |
153 | %{mcpu=823: -mppc} \ | |
775db490 | 154 | %{mcpu=860: -mppc} \ |
93ae5495 AM |
155 | %{mcpu=970: -mpower4 -maltivec} \ |
156 | %{mcpu=G5: -mpower4 -maltivec} \ | |
a3170dc6 | 157 | %{mcpu=8540: -me500} \ |
5ca0373f | 158 | %{mcpu=8548: -me500} \ |
fa41c305 EW |
159 | %{mcpu=e300c2: -me300} \ |
160 | %{mcpu=e300c3: -me300} \ | |
edae5fe3 | 161 | %{mcpu=e500mc: -me500mc} \ |
b17f98b1 | 162 | %{mcpu=e500mc64: -me500mc64} \ |
683ed19e EW |
163 | %{mcpu=e5500: -me5500} \ |
164 | %{mcpu=e6500: -me6500} \ | |
93ae5495 | 165 | %{maltivec: -maltivec} \ |
2c9ccc21 | 166 | %{mvsx: -mvsx %{!maltivec: -maltivec} %{!mcpu*: %(asm_cpu_power7)}} \ |
f62511da | 167 | %{mpower8-vector|mcrypto|mdirect-move: %{!mcpu*: %(asm_cpu_power8)}} \ |
93ae5495 | 168 | -many" |
f984d8df DB |
169 | |
170 | #define CPP_DEFAULT_SPEC "" | |
171 | ||
172 | #define ASM_DEFAULT_SPEC "" | |
173 | ||
841faeed MM |
174 | /* This macro defines names of additional specifications to put in the specs |
175 | that can be used in various specifications like CC1_SPEC. Its definition | |
176 | is an initializer with a subgrouping for each command option. | |
177 | ||
178 | Each subgrouping contains a string constant, that defines the | |
5de601cf | 179 | specification name, and a string constant that used by the GCC driver |
841faeed MM |
180 | program. |
181 | ||
182 | Do not define this macro if it does not need to do anything. */ | |
183 | ||
7509c759 | 184 | #define SUBTARGET_EXTRA_SPECS |
7509c759 | 185 | |
c81bebd7 | 186 | #define EXTRA_SPECS \ |
c81bebd7 | 187 | { "cpp_default", CPP_DEFAULT_SPEC }, \ |
c81bebd7 | 188 | { "asm_cpu", ASM_CPU_SPEC }, \ |
cacf1ca8 | 189 | { "asm_cpu_native", ASM_CPU_NATIVE_SPEC }, \ |
c81bebd7 | 190 | { "asm_default", ASM_DEFAULT_SPEC }, \ |
0eab6840 | 191 | { "cc1_cpu", CC1_CPU_SPEC }, \ |
cd679487 BE |
192 | { "asm_cpu_power5", ASM_CPU_POWER5_SPEC }, \ |
193 | { "asm_cpu_power6", ASM_CPU_POWER6_SPEC }, \ | |
d40c9e33 | 194 | { "asm_cpu_power7", ASM_CPU_POWER7_SPEC }, \ |
428bffcb | 195 | { "asm_cpu_power8", ASM_CPU_POWER8_SPEC }, \ |
47f67e51 | 196 | { "asm_cpu_476", ASM_CPU_476_SPEC }, \ |
7509c759 MM |
197 | SUBTARGET_EXTRA_SPECS |
198 | ||
0eab6840 DE |
199 | /* -mcpu=native handling only makes sense with compiler running on |
200 | an PowerPC chip. If changing this condition, also change | |
201 | the condition in driver-rs6000.c. */ | |
202 | #if defined(__powerpc__) || defined(__POWERPC__) || defined(_AIX) | |
203 | /* In driver-rs6000.c. */ | |
204 | extern const char *host_detect_local_cpu (int argc, const char **argv); | |
205 | #define EXTRA_SPEC_FUNCTIONS \ | |
206 | { "local_cpu_detect", host_detect_local_cpu }, | |
207 | #define HAVE_LOCAL_CPU_DETECT | |
cacf1ca8 MM |
208 | #define ASM_CPU_NATIVE_SPEC "%:local_cpu_detect(asm)" |
209 | ||
210 | #else | |
211 | #define ASM_CPU_NATIVE_SPEC "%(asm_default)" | |
0eab6840 DE |
212 | #endif |
213 | ||
ee7caeb3 DE |
214 | #ifndef CC1_CPU_SPEC |
215 | #ifdef HAVE_LOCAL_CPU_DETECT | |
0eab6840 DE |
216 | #define CC1_CPU_SPEC \ |
217 | "%{mcpu=native:%<mcpu=native %:local_cpu_detect(cpu)} \ | |
218 | %{mtune=native:%<mtune=native %:local_cpu_detect(tune)}" | |
ee7caeb3 DE |
219 | #else |
220 | #define CC1_CPU_SPEC "" | |
221 | #endif | |
0eab6840 DE |
222 | #endif |
223 | ||
fb623df5 | 224 | /* Architecture type. */ |
f045b2c9 | 225 | |
bb22512c | 226 | /* Define TARGET_MFCRF if the target assembler does not support the |
78f5898b | 227 | optional field operand for mfcr. */ |
fb623df5 | 228 | |
78f5898b | 229 | #ifndef HAVE_AS_MFCRF |
432218ba | 230 | #undef TARGET_MFCRF |
ffa22984 DE |
231 | #define TARGET_MFCRF 0 |
232 | #endif | |
233 | ||
0fa2e4df | 234 | /* Define TARGET_POPCNTB if the target assembler does not support the |
432218ba DE |
235 | popcount byte instruction. */ |
236 | ||
237 | #ifndef HAVE_AS_POPCNTB | |
238 | #undef TARGET_POPCNTB | |
239 | #define TARGET_POPCNTB 0 | |
240 | #endif | |
241 | ||
9719f3b7 DE |
242 | /* Define TARGET_FPRND if the target assembler does not support the |
243 | fp rounding instructions. */ | |
244 | ||
245 | #ifndef HAVE_AS_FPRND | |
246 | #undef TARGET_FPRND | |
247 | #define TARGET_FPRND 0 | |
248 | #endif | |
249 | ||
b639c3c2 JJ |
250 | /* Define TARGET_CMPB if the target assembler does not support the |
251 | cmpb instruction. */ | |
252 | ||
253 | #ifndef HAVE_AS_CMPB | |
254 | #undef TARGET_CMPB | |
255 | #define TARGET_CMPB 0 | |
256 | #endif | |
257 | ||
44cd321e PS |
258 | /* Define TARGET_MFPGPR if the target assembler does not support the |
259 | mffpr and mftgpr instructions. */ | |
260 | ||
261 | #ifndef HAVE_AS_MFPGPR | |
262 | #undef TARGET_MFPGPR | |
263 | #define TARGET_MFPGPR 0 | |
264 | #endif | |
265 | ||
b639c3c2 JJ |
266 | /* Define TARGET_DFP if the target assembler does not support decimal |
267 | floating point instructions. */ | |
268 | #ifndef HAVE_AS_DFP | |
269 | #undef TARGET_DFP | |
270 | #define TARGET_DFP 0 | |
271 | #endif | |
272 | ||
cacf1ca8 MM |
273 | /* Define TARGET_POPCNTD if the target assembler does not support the |
274 | popcount word and double word instructions. */ | |
275 | ||
276 | #ifndef HAVE_AS_POPCNTD | |
277 | #undef TARGET_POPCNTD | |
278 | #define TARGET_POPCNTD 0 | |
279 | #endif | |
280 | ||
f62511da MM |
281 | /* Define the ISA 2.07 flags as 0 if the target assembler does not support the |
282 | waitasecond instruction. Allow -mpower8-fusion, since it does not add new | |
283 | instructions. */ | |
284 | ||
285 | #ifndef HAVE_AS_POWER8 | |
286 | #undef TARGET_DIRECT_MOVE | |
287 | #undef TARGET_CRYPTO | |
288 | #undef TARGET_P8_VECTOR | |
289 | #define TARGET_DIRECT_MOVE 0 | |
290 | #define TARGET_CRYPTO 0 | |
291 | #define TARGET_P8_VECTOR 0 | |
292 | #endif | |
293 | ||
cacf1ca8 MM |
294 | /* Define TARGET_LWSYNC_INSTRUCTION if the assembler knows about lwsync. If |
295 | not, generate the lwsync code as an integer constant. */ | |
296 | #ifdef HAVE_AS_LWSYNC | |
297 | #define TARGET_LWSYNC_INSTRUCTION 1 | |
298 | #else | |
299 | #define TARGET_LWSYNC_INSTRUCTION 0 | |
300 | #endif | |
301 | ||
9752c4ad AM |
302 | /* Define TARGET_TLS_MARKERS if the target assembler does not support |
303 | arg markers for __tls_get_addr calls. */ | |
304 | #ifndef HAVE_AS_TLS_MARKERS | |
305 | #undef TARGET_TLS_MARKERS | |
306 | #define TARGET_TLS_MARKERS 0 | |
307 | #else | |
308 | #define TARGET_TLS_MARKERS tls_markers | |
309 | #endif | |
310 | ||
7f970b70 AM |
311 | #ifndef TARGET_SECURE_PLT |
312 | #define TARGET_SECURE_PLT 0 | |
313 | #endif | |
314 | ||
070b27da AM |
315 | #ifndef TARGET_CMODEL |
316 | #define TARGET_CMODEL CMODEL_SMALL | |
317 | #endif | |
318 | ||
2f3e5814 | 319 | #define TARGET_32BIT (! TARGET_64BIT) |
d14a6d05 | 320 | |
c4501e62 JJ |
321 | #ifndef HAVE_AS_TLS |
322 | #define HAVE_AS_TLS 0 | |
323 | #endif | |
324 | ||
be26142a PB |
325 | #ifndef TARGET_LINK_STACK |
326 | #define TARGET_LINK_STACK 0 | |
327 | #endif | |
328 | ||
329 | #ifndef SET_TARGET_LINK_STACK | |
330 | #define SET_TARGET_LINK_STACK(X) do { } while (0) | |
331 | #endif | |
332 | ||
48d72335 DE |
333 | /* Return 1 for a symbol ref for a thread-local storage symbol. */ |
334 | #define RS6000_SYMBOL_REF_TLS_P(RTX) \ | |
335 | (GET_CODE (RTX) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (RTX) != 0) | |
336 | ||
996ed075 JJ |
337 | #ifdef IN_LIBGCC2 |
338 | /* For libgcc2 we make sure this is a compile time constant */ | |
67796c1f | 339 | #if defined (__64BIT__) || defined (__powerpc64__) || defined (__ppc64__) |
78f5898b | 340 | #undef TARGET_POWERPC64 |
996ed075 JJ |
341 | #define TARGET_POWERPC64 1 |
342 | #else | |
78f5898b | 343 | #undef TARGET_POWERPC64 |
996ed075 JJ |
344 | #define TARGET_POWERPC64 0 |
345 | #endif | |
b6c9286a | 346 | #else |
78f5898b | 347 | /* The option machinery will define this. */ |
b6c9286a MM |
348 | #endif |
349 | ||
c28a7c24 | 350 | #define TARGET_DEFAULT (MASK_MULTIPLE | MASK_STRING) |
9ebbca7d | 351 | |
696e45ba ME |
352 | /* FPU operations supported. |
353 | Each use of TARGET_SINGLE_FLOAT or TARGET_DOUBLE_FLOAT must | |
354 | also test TARGET_HARD_FLOAT. */ | |
355 | #define TARGET_SINGLE_FLOAT 1 | |
356 | #define TARGET_DOUBLE_FLOAT 1 | |
357 | #define TARGET_SINGLE_FPU 0 | |
358 | #define TARGET_SIMPLE_FPU 0 | |
0bb7b92e | 359 | #define TARGET_XILINX_FPU 0 |
696e45ba | 360 | |
fb623df5 RK |
361 | /* Recast the processor type to the cpu attribute. */ |
362 | #define rs6000_cpu_attr ((enum attr_cpu)rs6000_cpu) | |
363 | ||
8482e358 | 364 | /* Define generic processor types based upon current deployment. */ |
3cb999d8 | 365 | #define PROCESSOR_COMMON PROCESSOR_PPC601 |
3cb999d8 DE |
366 | #define PROCESSOR_POWERPC PROCESSOR_PPC604 |
367 | #define PROCESSOR_POWERPC64 PROCESSOR_RS64A | |
6e151478 | 368 | |
fb623df5 | 369 | /* Define the default processor. This is overridden by other tm.h files. */ |
f3061fa4 | 370 | #define PROCESSOR_DEFAULT PROCESSOR_PPC603 |
3cb999d8 | 371 | #define PROCESSOR_DEFAULT64 PROCESSOR_RS64A |
fb623df5 | 372 | |
59ac9a55 JJ |
373 | /* Specify the dialect of assembler to use. Only new mnemonics are supported |
374 | starting with GCC 4.8, i.e. just one dialect, but for backwards | |
375 | compatibility with older inline asm ASSEMBLER_DIALECT needs to be | |
376 | defined. */ | |
377 | #define ASSEMBLER_DIALECT 1 | |
378 | ||
38c1f2d7 | 379 | /* Debug support */ |
fd438373 MM |
380 | #define MASK_DEBUG_STACK 0x01 /* debug stack applications */ |
381 | #define MASK_DEBUG_ARG 0x02 /* debug argument handling */ | |
382 | #define MASK_DEBUG_REG 0x04 /* debug register handling */ | |
383 | #define MASK_DEBUG_ADDR 0x08 /* debug memory addressing */ | |
384 | #define MASK_DEBUG_COST 0x10 /* debug rtx codes */ | |
385 | #define MASK_DEBUG_TARGET 0x20 /* debug target attribute/pragma */ | |
7fa14a01 | 386 | #define MASK_DEBUG_BUILTIN 0x40 /* debug builtins */ |
fd438373 MM |
387 | #define MASK_DEBUG_ALL (MASK_DEBUG_STACK \ |
388 | | MASK_DEBUG_ARG \ | |
389 | | MASK_DEBUG_REG \ | |
390 | | MASK_DEBUG_ADDR \ | |
391 | | MASK_DEBUG_COST \ | |
7fa14a01 MM |
392 | | MASK_DEBUG_TARGET \ |
393 | | MASK_DEBUG_BUILTIN) | |
fd438373 MM |
394 | |
395 | #define TARGET_DEBUG_STACK (rs6000_debug & MASK_DEBUG_STACK) | |
396 | #define TARGET_DEBUG_ARG (rs6000_debug & MASK_DEBUG_ARG) | |
397 | #define TARGET_DEBUG_REG (rs6000_debug & MASK_DEBUG_REG) | |
398 | #define TARGET_DEBUG_ADDR (rs6000_debug & MASK_DEBUG_ADDR) | |
399 | #define TARGET_DEBUG_COST (rs6000_debug & MASK_DEBUG_COST) | |
400 | #define TARGET_DEBUG_TARGET (rs6000_debug & MASK_DEBUG_TARGET) | |
7fa14a01 | 401 | #define TARGET_DEBUG_BUILTIN (rs6000_debug & MASK_DEBUG_BUILTIN) |
cacf1ca8 | 402 | |
f62511da | 403 | /* Describe the vector unit used for arithmetic operations. */ |
cacf1ca8 MM |
404 | extern enum rs6000_vector rs6000_vector_unit[]; |
405 | ||
406 | #define VECTOR_UNIT_NONE_P(MODE) \ | |
407 | (rs6000_vector_unit[(MODE)] == VECTOR_NONE) | |
408 | ||
409 | #define VECTOR_UNIT_VSX_P(MODE) \ | |
410 | (rs6000_vector_unit[(MODE)] == VECTOR_VSX) | |
411 | ||
f62511da MM |
412 | #define VECTOR_UNIT_P8_VECTOR_P(MODE) \ |
413 | (rs6000_vector_unit[(MODE)] == VECTOR_P8_VECTOR) | |
414 | ||
cacf1ca8 MM |
415 | #define VECTOR_UNIT_ALTIVEC_P(MODE) \ |
416 | (rs6000_vector_unit[(MODE)] == VECTOR_ALTIVEC) | |
417 | ||
f62511da MM |
418 | #define VECTOR_UNIT_VSX_OR_P8_VECTOR_P(MODE) \ |
419 | (IN_RANGE ((int)rs6000_vector_unit[(MODE)], \ | |
420 | (int)VECTOR_VSX, \ | |
421 | (int)VECTOR_P8_VECTOR)) | |
422 | ||
423 | /* VECTOR_UNIT_ALTIVEC_OR_VSX_P is used in places where we are using either | |
424 | altivec (VMX) or VSX vector instructions. P8 vector support is upwards | |
425 | compatible, so allow it as well, rather than changing all of the uses of the | |
426 | macro. */ | |
cacf1ca8 | 427 | #define VECTOR_UNIT_ALTIVEC_OR_VSX_P(MODE) \ |
f62511da MM |
428 | (IN_RANGE ((int)rs6000_vector_unit[(MODE)], \ |
429 | (int)VECTOR_ALTIVEC, \ | |
430 | (int)VECTOR_P8_VECTOR)) | |
cacf1ca8 MM |
431 | |
432 | /* Describe whether to use VSX loads or Altivec loads. For now, just use the | |
433 | same unit as the vector unit we are using, but we may want to migrate to | |
434 | using VSX style loads even for types handled by altivec. */ | |
435 | extern enum rs6000_vector rs6000_vector_mem[]; | |
436 | ||
437 | #define VECTOR_MEM_NONE_P(MODE) \ | |
438 | (rs6000_vector_mem[(MODE)] == VECTOR_NONE) | |
439 | ||
440 | #define VECTOR_MEM_VSX_P(MODE) \ | |
441 | (rs6000_vector_mem[(MODE)] == VECTOR_VSX) | |
442 | ||
f62511da MM |
443 | #define VECTOR_MEM_P8_VECTOR_P(MODE) \ |
444 | (rs6000_vector_mem[(MODE)] == VECTOR_VSX) | |
445 | ||
cacf1ca8 MM |
446 | #define VECTOR_MEM_ALTIVEC_P(MODE) \ |
447 | (rs6000_vector_mem[(MODE)] == VECTOR_ALTIVEC) | |
448 | ||
f62511da MM |
449 | #define VECTOR_MEM_VSX_OR_P8_VECTOR_P(MODE) \ |
450 | (IN_RANGE ((int)rs6000_vector_mem[(MODE)], \ | |
451 | (int)VECTOR_VSX, \ | |
452 | (int)VECTOR_P8_VECTOR)) | |
453 | ||
cacf1ca8 | 454 | #define VECTOR_MEM_ALTIVEC_OR_VSX_P(MODE) \ |
f62511da MM |
455 | (IN_RANGE ((int)rs6000_vector_mem[(MODE)], \ |
456 | (int)VECTOR_ALTIVEC, \ | |
457 | (int)VECTOR_P8_VECTOR)) | |
cacf1ca8 MM |
458 | |
459 | /* Return the alignment of a given vector type, which is set based on the | |
460 | vector unit use. VSX for instance can load 32 or 64 bit aligned words | |
461 | without problems, while Altivec requires 128-bit aligned vectors. */ | |
462 | extern int rs6000_vector_align[]; | |
463 | ||
464 | #define VECTOR_ALIGN(MODE) \ | |
465 | ((rs6000_vector_align[(MODE)] != 0) \ | |
466 | ? rs6000_vector_align[(MODE)] \ | |
467 | : (int)GET_MODE_BITSIZE ((MODE))) | |
468 | ||
025d9908 KH |
469 | /* Alignment options for fields in structures for sub-targets following |
470 | AIX-like ABI. | |
471 | ALIGN_POWER word-aligns FP doubles (default AIX ABI). | |
472 | ALIGN_NATURAL doubleword-aligns FP doubles (align to object size). | |
473 | ||
474 | Override the macro definitions when compiling libobjc to avoid undefined | |
475 | reference to rs6000_alignment_flags due to library's use of GCC alignment | |
476 | macros which use the macros below. */ | |
f676971a | 477 | |
025d9908 KH |
478 | #ifndef IN_TARGET_LIBS |
479 | #define MASK_ALIGN_POWER 0x00000000 | |
480 | #define MASK_ALIGN_NATURAL 0x00000001 | |
481 | #define TARGET_ALIGN_NATURAL (rs6000_alignment_flags & MASK_ALIGN_NATURAL) | |
482 | #else | |
483 | #define TARGET_ALIGN_NATURAL 0 | |
484 | #endif | |
6fa3f289 ZW |
485 | |
486 | #define TARGET_LONG_DOUBLE_128 (rs6000_long_double_type_size == 128) | |
602ea4d3 | 487 | #define TARGET_IEEEQUAD rs6000_ieeequad |
6fa3f289 | 488 | #define TARGET_ALTIVEC_ABI rs6000_altivec_abi |
cacf1ca8 | 489 | #define TARGET_LDBRX (TARGET_POPCNTD || rs6000_cpu == PROCESSOR_CELL) |
6fa3f289 | 490 | |
a3170dc6 AH |
491 | #define TARGET_SPE_ABI 0 |
492 | #define TARGET_SPE 0 | |
cacf1ca8 | 493 | #define TARGET_ISEL64 (TARGET_ISEL && TARGET_POWERPC64) |
a3170dc6 | 494 | #define TARGET_FPRS 1 |
4d4cbc0e AH |
495 | #define TARGET_E500_SINGLE 0 |
496 | #define TARGET_E500_DOUBLE 0 | |
eca0d5e8 | 497 | #define CHECK_E500_OPTIONS do { } while (0) |
a3170dc6 | 498 | |
7042fe5e MM |
499 | /* ISA 2.01 allowed FCFID to be done in 32-bit, previously it was 64-bit only. |
500 | Enable 32-bit fcfid's on any of the switches for newer ISA machines or | |
501 | XILINX. */ | |
c3f8384f MM |
502 | #define TARGET_FCFID (TARGET_POWERPC64 \ |
503 | || TARGET_PPC_GPOPT /* 970/power4 */ \ | |
504 | || TARGET_POPCNTB /* ISA 2.02 */ \ | |
505 | || TARGET_CMPB /* ISA 2.05 */ \ | |
506 | || TARGET_POPCNTD /* ISA 2.06 */ \ | |
7042fe5e MM |
507 | || TARGET_XILINX_FPU) |
508 | ||
509 | #define TARGET_FCTIDZ TARGET_FCFID | |
510 | #define TARGET_STFIWX TARGET_PPC_GFXOPT | |
511 | #define TARGET_LFIWAX TARGET_CMPB | |
512 | #define TARGET_LFIWZX TARGET_POPCNTD | |
513 | #define TARGET_FCFIDS TARGET_POPCNTD | |
514 | #define TARGET_FCFIDU TARGET_POPCNTD | |
515 | #define TARGET_FCFIDUS TARGET_POPCNTD | |
516 | #define TARGET_FCTIDUZ TARGET_POPCNTD | |
517 | #define TARGET_FCTIWUZ TARGET_POPCNTD | |
518 | ||
f62511da MM |
519 | #define TARGET_XSCVDPSPN (TARGET_DIRECT_MOVE || TARGET_P8_VECTOR) |
520 | #define TARGET_XSCVSPDPN (TARGET_DIRECT_MOVE || TARGET_P8_VECTOR) | |
521 | ||
522 | /* Byte/char syncs were added as phased in for ISA 2.06B, but are not present | |
523 | in power7, so conditionalize them on p8 features. TImode syncs need quad | |
524 | memory support. */ | |
525 | #define TARGET_SYNC_HI_QI (TARGET_QUAD_MEMORY || TARGET_DIRECT_MOVE) | |
526 | #define TARGET_SYNC_TI TARGET_QUAD_MEMORY | |
527 | ||
c6d5ff83 MM |
528 | /* Power7 has both 32-bit load and store integer for the FPRs, so we don't need |
529 | to allocate the SDmode stack slot to get the value into the proper location | |
530 | in the register. */ | |
531 | #define TARGET_NO_SDMODE_STACK (TARGET_LFIWZX && TARGET_STFIWX && TARGET_DFP) | |
532 | ||
4d967549 MM |
533 | /* In switching from using target_flags to using rs6000_isa_flags, the options |
534 | machinery creates OPTION_MASK_<xxx> instead of MASK_<xxx>. For now map | |
535 | OPTION_MASK_<xxx> back into MASK_<xxx>. */ | |
536 | #define MASK_ALTIVEC OPTION_MASK_ALTIVEC | |
537 | #define MASK_CMPB OPTION_MASK_CMPB | |
f62511da | 538 | #define MASK_CRYPTO OPTION_MASK_CRYPTO |
4d967549 | 539 | #define MASK_DFP OPTION_MASK_DFP |
f62511da | 540 | #define MASK_DIRECT_MOVE OPTION_MASK_DIRECT_MOVE |
4d967549 MM |
541 | #define MASK_DLMZB OPTION_MASK_DLMZB |
542 | #define MASK_EABI OPTION_MASK_EABI | |
543 | #define MASK_FPRND OPTION_MASK_FPRND | |
f62511da | 544 | #define MASK_P8_FUSION OPTION_MASK_P8_FUSION |
4d967549 MM |
545 | #define MASK_HARD_FLOAT OPTION_MASK_HARD_FLOAT |
546 | #define MASK_ISEL OPTION_MASK_ISEL | |
547 | #define MASK_MFCRF OPTION_MASK_MFCRF | |
548 | #define MASK_MFPGPR OPTION_MASK_MFPGPR | |
549 | #define MASK_MULHW OPTION_MASK_MULHW | |
550 | #define MASK_MULTIPLE OPTION_MASK_MULTIPLE | |
551 | #define MASK_NO_UPDATE OPTION_MASK_NO_UPDATE | |
f62511da | 552 | #define MASK_P8_VECTOR OPTION_MASK_P8_VECTOR |
4d967549 MM |
553 | #define MASK_POPCNTB OPTION_MASK_POPCNTB |
554 | #define MASK_POPCNTD OPTION_MASK_POPCNTD | |
555 | #define MASK_PPC_GFXOPT OPTION_MASK_PPC_GFXOPT | |
556 | #define MASK_PPC_GPOPT OPTION_MASK_PPC_GPOPT | |
557 | #define MASK_RECIP_PRECISION OPTION_MASK_RECIP_PRECISION | |
558 | #define MASK_SOFT_FLOAT OPTION_MASK_SOFT_FLOAT | |
559 | #define MASK_STRICT_ALIGN OPTION_MASK_STRICT_ALIGN | |
560 | #define MASK_STRING OPTION_MASK_STRING | |
561 | #define MASK_UPDATE OPTION_MASK_UPDATE | |
562 | #define MASK_VSX OPTION_MASK_VSX | |
c6d5ff83 | 563 | #define MASK_VSX_TIMODE OPTION_MASK_VSX_TIMODE |
4d967549 MM |
564 | |
565 | #ifndef IN_LIBGCC2 | |
566 | #define MASK_POWERPC64 OPTION_MASK_POWERPC64 | |
567 | #endif | |
568 | ||
569 | #ifdef TARGET_64BIT | |
570 | #define MASK_64BIT OPTION_MASK_64BIT | |
571 | #endif | |
572 | ||
573 | #ifdef TARGET_RELOCATABLE | |
574 | #define MASK_RELOCATABLE OPTION_MASK_RELOCATABLE | |
575 | #endif | |
576 | ||
577 | #ifdef TARGET_LITTLE_ENDIAN | |
578 | #define MASK_LITTLE_ENDIAN OPTION_MASK_LITTLE_ENDIAN | |
579 | #endif | |
580 | ||
581 | #ifdef TARGET_MINIMAL_TOC | |
582 | #define MASK_MINIMAL_TOC OPTION_MASK_MINIMAL_TOC | |
583 | #endif | |
584 | ||
585 | #ifdef TARGET_REGNAMES | |
586 | #define MASK_REGNAMES OPTION_MASK_REGNAMES | |
587 | #endif | |
588 | ||
589 | #ifdef TARGET_PROTOTYPE | |
590 | #define MASK_PROTOTYPE OPTION_MASK_PROTOTYPE | |
591 | #endif | |
592 | ||
593 | /* Explicit ISA options that were set. */ | |
594 | #define rs6000_isa_flags_explicit global_options_set.x_rs6000_isa_flags | |
595 | ||
7fa14a01 MM |
596 | /* For power systems, we want to enable Altivec and VSX builtins even if the |
597 | user did not use -maltivec or -mvsx to allow the builtins to be used inside | |
598 | of #pragma GCC target or the target attribute to change the code level for a | |
599 | given system. The SPE and Paired builtins are only enabled if you configure | |
600 | the compiler for those builtins, and those machines don't support altivec or | |
601 | VSX. */ | |
602 | ||
603 | #define TARGET_EXTRA_BUILTINS (!TARGET_SPE && !TARGET_PAIRED_FLOAT \ | |
604 | && ((TARGET_POWERPC64 \ | |
c3f8384f | 605 | || TARGET_PPC_GPOPT /* 970/power4 */ \ |
7fa14a01 MM |
606 | || TARGET_POPCNTB /* ISA 2.02 */ \ |
607 | || TARGET_CMPB /* ISA 2.05 */ \ | |
608 | || TARGET_POPCNTD /* ISA 2.06 */ \ | |
609 | || TARGET_ALTIVEC \ | |
610 | || TARGET_VSX))) | |
611 | ||
a7c6c6d6 OH |
612 | /* E500 cores only support plain "sync", not lwsync. */ |
613 | #define TARGET_NO_LWSYNC (rs6000_cpu == PROCESSOR_PPC8540 \ | |
614 | || rs6000_cpu == PROCESSOR_PPC8548) | |
7fa14a01 MM |
615 | |
616 | ||
92902797 MM |
617 | /* Which machine supports the various reciprocal estimate instructions. */ |
618 | #define TARGET_FRES (TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT \ | |
619 | && TARGET_FPRS && TARGET_SINGLE_FLOAT) | |
620 | ||
621 | #define TARGET_FRE (TARGET_HARD_FLOAT && TARGET_FPRS \ | |
622 | && TARGET_DOUBLE_FLOAT \ | |
623 | && (TARGET_POPCNTB || VECTOR_UNIT_VSX_P (DFmode))) | |
624 | ||
625 | #define TARGET_FRSQRTES (TARGET_HARD_FLOAT && TARGET_POPCNTB \ | |
626 | && TARGET_FPRS && TARGET_SINGLE_FLOAT) | |
627 | ||
628 | #define TARGET_FRSQRTE (TARGET_HARD_FLOAT && TARGET_FPRS \ | |
629 | && TARGET_DOUBLE_FLOAT \ | |
630 | && (TARGET_PPC_GFXOPT || VECTOR_UNIT_VSX_P (DFmode))) | |
631 | ||
632 | /* Whether the various reciprocal divide/square root estimate instructions | |
633 | exist, and whether we should automatically generate code for the instruction | |
634 | by default. */ | |
635 | #define RS6000_RECIP_MASK_HAVE_RE 0x1 /* have RE instruction. */ | |
636 | #define RS6000_RECIP_MASK_AUTO_RE 0x2 /* generate RE by default. */ | |
637 | #define RS6000_RECIP_MASK_HAVE_RSQRTE 0x4 /* have RSQRTE instruction. */ | |
638 | #define RS6000_RECIP_MASK_AUTO_RSQRTE 0x8 /* gen. RSQRTE by default. */ | |
639 | ||
640 | extern unsigned char rs6000_recip_bits[]; | |
641 | ||
642 | #define RS6000_RECIP_HAVE_RE_P(MODE) \ | |
643 | (rs6000_recip_bits[(int)(MODE)] & RS6000_RECIP_MASK_HAVE_RE) | |
644 | ||
645 | #define RS6000_RECIP_AUTO_RE_P(MODE) \ | |
646 | (rs6000_recip_bits[(int)(MODE)] & RS6000_RECIP_MASK_AUTO_RE) | |
647 | ||
648 | #define RS6000_RECIP_HAVE_RSQRTE_P(MODE) \ | |
649 | (rs6000_recip_bits[(int)(MODE)] & RS6000_RECIP_MASK_HAVE_RSQRTE) | |
650 | ||
651 | #define RS6000_RECIP_AUTO_RSQRTE_P(MODE) \ | |
652 | (rs6000_recip_bits[(int)(MODE)] & RS6000_RECIP_MASK_AUTO_RSQRTE) | |
653 | ||
c5387660 JM |
654 | /* The default CPU for TARGET_OPTION_OVERRIDE. */ |
655 | #define OPTION_TARGET_CPU_DEFAULT TARGET_CPU_DEFAULT | |
f045b2c9 | 656 | |
a5c76ee6 | 657 | /* Target pragma. */ |
c58b209a NB |
658 | #define REGISTER_TARGET_PRAGMAS() do { \ |
659 | c_register_pragma (0, "longcall", rs6000_pragma_longcall); \ | |
fd438373 | 660 | targetm.target_option.pragma_parse = rs6000_pragma_target_parse; \ |
2fab365e | 661 | targetm.resolve_overloaded_builtin = altivec_resolve_overloaded_builtin; \ |
7fa14a01 | 662 | rs6000_target_modify_macros_ptr = rs6000_target_modify_macros; \ |
a5c76ee6 ZW |
663 | } while (0) |
664 | ||
4c4eb375 GK |
665 | /* Target #defines. */ |
666 | #define TARGET_CPU_CPP_BUILTINS() \ | |
667 | rs6000_cpu_cpp_builtins (pfile) | |
647d340d JT |
668 | |
669 | /* This is used by rs6000_cpu_cpp_builtins to indicate the byte order | |
670 | we're compiling for. Some configurations may need to override it. */ | |
671 | #define RS6000_CPU_CPP_ENDIAN_BUILTINS() \ | |
672 | do \ | |
673 | { \ | |
674 | if (BYTES_BIG_ENDIAN) \ | |
675 | { \ | |
676 | builtin_define ("__BIG_ENDIAN__"); \ | |
677 | builtin_define ("_BIG_ENDIAN"); \ | |
678 | builtin_assert ("machine=bigendian"); \ | |
679 | } \ | |
680 | else \ | |
681 | { \ | |
682 | builtin_define ("__LITTLE_ENDIAN__"); \ | |
683 | builtin_define ("_LITTLE_ENDIAN"); \ | |
684 | builtin_assert ("machine=littleendian"); \ | |
685 | } \ | |
686 | } \ | |
687 | while (0) | |
f045b2c9 | 688 | \f |
4c4eb375 | 689 | /* Target machine storage layout. */ |
f045b2c9 | 690 | |
13d39dbc | 691 | /* Define this macro if it is advisable to hold scalars in registers |
c81bebd7 | 692 | in a wider mode than that declared by the program. In such cases, |
ef457bda RK |
693 | the value is constrained to be within the bounds of the declared |
694 | type, but kept valid in the wider mode. The signedness of the | |
695 | extension may differ from that of the type. */ | |
696 | ||
39403d82 DE |
697 | #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \ |
698 | if (GET_MODE_CLASS (MODE) == MODE_INT \ | |
699 | && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \ | |
b78d48dd | 700 | (MODE) = TARGET_32BIT ? SImode : DImode; |
39403d82 | 701 | |
f045b2c9 | 702 | /* Define this if most significant bit is lowest numbered |
82e41834 KH |
703 | in instructions that operate on numbered bit-fields. */ |
704 | /* That is true on RS/6000. */ | |
f045b2c9 RS |
705 | #define BITS_BIG_ENDIAN 1 |
706 | ||
707 | /* Define this if most significant byte of a word is the lowest numbered. */ | |
708 | /* That is true on RS/6000. */ | |
709 | #define BYTES_BIG_ENDIAN 1 | |
710 | ||
711 | /* Define this if most significant word of a multiword number is lowest | |
c81bebd7 | 712 | numbered. |
f045b2c9 RS |
713 | |
714 | For RS/6000 we can decide arbitrarily since there are no machine | |
82e41834 | 715 | instructions for them. Might as well be consistent with bits and bytes. */ |
f045b2c9 RS |
716 | #define WORDS_BIG_ENDIAN 1 |
717 | ||
50751417 AM |
718 | /* This says that for the IBM long double the larger magnitude double |
719 | comes first. It's really a two element double array, and arrays | |
720 | don't index differently between little- and big-endian. */ | |
721 | #define LONG_DOUBLE_LARGE_FIRST 1 | |
722 | ||
2e360ab3 | 723 | #define MAX_BITS_PER_WORD 64 |
f045b2c9 RS |
724 | |
725 | /* Width of a word, in units (bytes). */ | |
c1aa3958 | 726 | #define UNITS_PER_WORD (! TARGET_POWERPC64 ? 4 : 8) |
f34fc46e DE |
727 | #ifdef IN_LIBGCC2 |
728 | #define MIN_UNITS_PER_WORD UNITS_PER_WORD | |
729 | #else | |
ef0e53ce | 730 | #define MIN_UNITS_PER_WORD 4 |
f34fc46e | 731 | #endif |
2e360ab3 | 732 | #define UNITS_PER_FP_WORD 8 |
0ac081f6 | 733 | #define UNITS_PER_ALTIVEC_WORD 16 |
cacf1ca8 | 734 | #define UNITS_PER_VSX_WORD 16 |
a3170dc6 | 735 | #define UNITS_PER_SPE_WORD 8 |
96038623 | 736 | #define UNITS_PER_PAIRED_WORD 8 |
f045b2c9 | 737 | |
915f619f JW |
738 | /* Type used for ptrdiff_t, as a string used in a declaration. */ |
739 | #define PTRDIFF_TYPE "int" | |
740 | ||
058ef853 DE |
741 | /* Type used for size_t, as a string used in a declaration. */ |
742 | #define SIZE_TYPE "long unsigned int" | |
743 | ||
f045b2c9 RS |
744 | /* Type used for wchar_t, as a string used in a declaration. */ |
745 | #define WCHAR_TYPE "short unsigned int" | |
746 | ||
747 | /* Width of wchar_t in bits. */ | |
748 | #define WCHAR_TYPE_SIZE 16 | |
749 | ||
9e654916 RK |
750 | /* A C expression for the size in bits of the type `short' on the |
751 | target machine. If you don't define this, the default is half a | |
752 | word. (If this would be less than one storage unit, it is | |
753 | rounded up to one unit.) */ | |
754 | #define SHORT_TYPE_SIZE 16 | |
755 | ||
756 | /* A C expression for the size in bits of the type `int' on the | |
757 | target machine. If you don't define this, the default is one | |
758 | word. */ | |
19d2d16f | 759 | #define INT_TYPE_SIZE 32 |
9e654916 RK |
760 | |
761 | /* A C expression for the size in bits of the type `long' on the | |
762 | target machine. If you don't define this, the default is one | |
763 | word. */ | |
2f3e5814 | 764 | #define LONG_TYPE_SIZE (TARGET_32BIT ? 32 : 64) |
9e654916 RK |
765 | |
766 | /* A C expression for the size in bits of the type `long long' on the | |
767 | target machine. If you don't define this, the default is two | |
768 | words. */ | |
769 | #define LONG_LONG_TYPE_SIZE 64 | |
770 | ||
9e654916 RK |
771 | /* A C expression for the size in bits of the type `float' on the |
772 | target machine. If you don't define this, the default is one | |
773 | word. */ | |
774 | #define FLOAT_TYPE_SIZE 32 | |
775 | ||
776 | /* A C expression for the size in bits of the type `double' on the | |
777 | target machine. If you don't define this, the default is two | |
778 | words. */ | |
779 | #define DOUBLE_TYPE_SIZE 64 | |
780 | ||
781 | /* A C expression for the size in bits of the type `long double' on | |
782 | the target machine. If you don't define this, the default is two | |
783 | words. */ | |
6fa3f289 | 784 | #define LONG_DOUBLE_TYPE_SIZE rs6000_long_double_type_size |
06f4e019 | 785 | |
06f4e019 DE |
786 | /* Define this to set long double type size to use in libgcc2.c, which can |
787 | not depend on target_flags. */ | |
788 | #ifdef __LONG_DOUBLE_128__ | |
789 | #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128 | |
790 | #else | |
791 | #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64 | |
792 | #endif | |
9e654916 | 793 | |
5b8f5865 DE |
794 | /* Work around rs6000_long_double_type_size dependency in ada/targtyps.c. */ |
795 | #define WIDEST_HARDWARE_FP_SIZE 64 | |
796 | ||
f045b2c9 RS |
797 | /* Width in bits of a pointer. |
798 | See also the macro `Pmode' defined below. */ | |
cacf1ca8 MM |
799 | extern unsigned rs6000_pointer_size; |
800 | #define POINTER_SIZE rs6000_pointer_size | |
f045b2c9 RS |
801 | |
802 | /* Allocation boundary (in *bits*) for storing arguments in argument list. */ | |
2f3e5814 | 803 | #define PARM_BOUNDARY (TARGET_32BIT ? 32 : 64) |
f045b2c9 RS |
804 | |
805 | /* Boundary (in *bits*) on which stack pointer should be aligned. */ | |
cacf1ca8 MM |
806 | #define STACK_BOUNDARY \ |
807 | ((TARGET_32BIT && !TARGET_ALTIVEC && !TARGET_ALTIVEC_ABI && !TARGET_VSX) \ | |
808 | ? 64 : 128) | |
f045b2c9 RS |
809 | |
810 | /* Allocation boundary (in *bits*) for the code of a function. */ | |
811 | #define FUNCTION_BOUNDARY 32 | |
812 | ||
813 | /* No data type wants to be aligned rounder than this. */ | |
0ac081f6 AH |
814 | #define BIGGEST_ALIGNMENT 128 |
815 | ||
816 | /* A C expression to compute the alignment for a variables in the | |
817 | local store. TYPE is the data type, and ALIGN is the alignment | |
818 | that the object would ordinarily have. */ | |
819 | #define LOCAL_ALIGNMENT(TYPE, ALIGN) \ | |
777a3a6a | 820 | DATA_ALIGNMENT (TYPE, ALIGN) |
b73fd26c | 821 | |
f045b2c9 RS |
822 | /* Alignment of field after `int : 0' in a structure. */ |
823 | #define EMPTY_FIELD_BOUNDARY 32 | |
824 | ||
825 | /* Every structure's size must be a multiple of this. */ | |
826 | #define STRUCTURE_SIZE_BOUNDARY 8 | |
827 | ||
43a88a8c | 828 | /* A bit-field declared as `int' forces `int' alignment for the struct. */ |
f045b2c9 RS |
829 | #define PCC_BITFIELD_TYPE_MATTERS 1 |
830 | ||
69ef87e2 AH |
831 | /* Make strings word-aligned so strcpy from constants will be faster. |
832 | Make vector constants quadword aligned. */ | |
833 | #define CONSTANT_ALIGNMENT(EXP, ALIGN) \ | |
834 | (TREE_CODE (EXP) == STRING_CST \ | |
153fbec8 | 835 | && (STRICT_ALIGNMENT || !optimize_size) \ |
69ef87e2 AH |
836 | && (ALIGN) < BITS_PER_WORD \ |
837 | ? BITS_PER_WORD \ | |
838 | : (ALIGN)) | |
f045b2c9 | 839 | |
0ac081f6 | 840 | /* Make arrays of chars word-aligned for the same reasons. |
f82f556d AH |
841 | Align vectors to 128 bits. Align SPE vectors and E500 v2 doubles to |
842 | 64 bits. */ | |
b851135c NF |
843 | #define DATA_ALIGNMENT(TYPE, ALIGN) \ |
844 | (TREE_CODE (TYPE) == VECTOR_TYPE \ | |
845 | ? (((TARGET_SPE && SPE_VECTOR_MODE (TYPE_MODE (TYPE))) \ | |
846 | || (TARGET_PAIRED_FLOAT && PAIRED_VECTOR_MODE (TYPE_MODE (TYPE)))) \ | |
847 | ? 64 : 128) \ | |
848 | : ((TARGET_E500_DOUBLE \ | |
849 | && TREE_CODE (TYPE) == REAL_TYPE \ | |
850 | && TYPE_MODE (TYPE) == DFmode) \ | |
851 | ? 64 \ | |
852 | : (TREE_CODE (TYPE) == ARRAY_TYPE \ | |
853 | && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \ | |
854 | && (ALIGN) < BITS_PER_WORD) ? BITS_PER_WORD : (ALIGN))) | |
f045b2c9 | 855 | |
a0ab749a | 856 | /* Nonzero if move instructions will actually fail to work |
f045b2c9 | 857 | when given unaligned data. */ |
fdaff8ba | 858 | #define STRICT_ALIGNMENT 0 |
e1565e65 DE |
859 | |
860 | /* Define this macro to be the value 1 if unaligned accesses have a cost | |
861 | many times greater than aligned accesses, for example if they are | |
862 | emulated in a trap handler. */ | |
cacf1ca8 MM |
863 | /* Altivec vector memory instructions simply ignore the low bits; SPE vector |
864 | memory instructions trap on unaligned accesses; VSX memory instructions are | |
865 | aligned to 4 or 8 bytes. */ | |
41543739 GK |
866 | #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) \ |
867 | (STRICT_ALIGNMENT \ | |
fcce224d | 868 | || (((MODE) == SFmode || (MODE) == DFmode || (MODE) == TFmode \ |
9f89e66e | 869 | || (MODE) == SDmode || (MODE) == DDmode || (MODE) == TDmode) \ |
54ce9cc2 | 870 | && (ALIGN) < 32) \ |
cacf1ca8 MM |
871 | || (VECTOR_MODE_P ((MODE)) && (((int)(ALIGN)) < VECTOR_ALIGN (MODE)))) |
872 | ||
f045b2c9 RS |
873 | \f |
874 | /* Standard register usage. */ | |
875 | ||
876 | /* Number of actual hardware registers. | |
877 | The hardware registers are assigned numbers for the compiler | |
878 | from 0 to just below FIRST_PSEUDO_REGISTER. | |
879 | All registers that the compiler knows about must be given numbers, | |
880 | even those that are not normally considered general registers. | |
881 | ||
882 | RS/6000 has 32 fixed-point registers, 32 floating-point registers, | |
462f7901 SB |
883 | a count register, a link register, and 8 condition register fields, |
884 | which we view here as separate registers. AltiVec adds 32 vector | |
885 | registers and a VRsave register. | |
f045b2c9 RS |
886 | |
887 | In addition, the difference between the frame and argument pointers is | |
888 | a function of the number of registers saved, so we need to have a | |
889 | register for AP that will later be eliminated in favor of SP or FP. | |
802a0058 | 890 | This is a normal register, but it is fixed. |
f045b2c9 | 891 | |
802a0058 MM |
892 | We also create a pseudo register for float/int conversions, that will |
893 | really represent the memory location used. It is represented here as | |
894 | a register, in order to work around problems in allocating stack storage | |
7d5175e1 | 895 | in inline functions. |
802a0058 | 896 | |
7d5175e1 JJ |
897 | Another pseudo (not included in DWARF_FRAME_REGISTERS) is soft frame |
898 | pointer, which is eventually eliminated in favor of SP or FP. */ | |
899 | ||
900 | #define FIRST_PSEUDO_REGISTER 114 | |
f045b2c9 | 901 | |
d6a7951f | 902 | /* This must be included for pre gcc 3.0 glibc compatibility. */ |
7d5f33bc | 903 | #define PRE_GCC3_DWARF_FRAME_REGISTERS 77 |
62153b61 | 904 | |
93c9d1ba | 905 | /* Add 32 dwarf columns for synthetic SPE registers. */ |
7d5175e1 | 906 | #define DWARF_FRAME_REGISTERS ((FIRST_PSEUDO_REGISTER - 1) + 32) |
c19de7aa | 907 | |
93c9d1ba AM |
908 | /* The SPE has an additional 32 synthetic registers, with DWARF debug |
909 | info numbering for these registers starting at 1200. While eh_frame | |
910 | register numbering need not be the same as the debug info numbering, | |
911 | we choose to number these regs for eh_frame at 1200 too. This allows | |
912 | future versions of the rs6000 backend to add hard registers and | |
913 | continue to use the gcc hard register numbering for eh_frame. If the | |
914 | extra SPE registers in eh_frame were numbered starting from the | |
915 | current value of FIRST_PSEUDO_REGISTER, then if FIRST_PSEUDO_REGISTER | |
916 | changed we'd need to introduce a mapping in DWARF_FRAME_REGNUM to | |
917 | avoid invalidating older SPE eh_frame info. | |
918 | ||
919 | We must map them here to avoid huge unwinder tables mostly consisting | |
f676971a | 920 | of unused space. */ |
93c9d1ba | 921 | #define DWARF_REG_TO_UNWIND_COLUMN(r) \ |
7d5175e1 | 922 | ((r) > 1200 ? ((r) - 1200 + FIRST_PSEUDO_REGISTER - 1) : (r)) |
93c9d1ba | 923 | |
ed1cf8ff GK |
924 | /* Use standard DWARF numbering for DWARF debugging information. */ |
925 | #define DBX_REGISTER_NUMBER(REGNO) rs6000_dbx_register_number (REGNO) | |
926 | ||
93c9d1ba AM |
927 | /* Use gcc hard register numbering for eh_frame. */ |
928 | #define DWARF_FRAME_REGNUM(REGNO) (REGNO) | |
41f3a930 | 929 | |
ed1cf8ff GK |
930 | /* Map register numbers held in the call frame info that gcc has |
931 | collected using DWARF_FRAME_REGNUM to those that should be output in | |
932 | .debug_frame and .eh_frame. We continue to use gcc hard reg numbers | |
933 | for .eh_frame, but use the numbers mandated by the various ABIs for | |
934 | .debug_frame. rs6000_emit_prologue has translated any combination of | |
935 | CR2, CR3, CR4 saves to a save of CR2. The actual code emitted saves | |
936 | the whole of CR, so we map CR2_REGNO to the DWARF reg for CR. */ | |
937 | #define DWARF2_FRAME_REG_OUT(REGNO, FOR_EH) \ | |
938 | ((FOR_EH) ? (REGNO) \ | |
939 | : (REGNO) == CR2_REGNO ? 64 \ | |
940 | : DBX_REGISTER_NUMBER (REGNO)) | |
941 | ||
f045b2c9 RS |
942 | /* 1 for registers that have pervasive standard uses |
943 | and are not available for the register allocator. | |
944 | ||
5dead3e5 DJ |
945 | On RS/6000, r1 is used for the stack. On Darwin, r2 is available |
946 | as a local register; for all other OS's r2 is the TOC pointer. | |
f045b2c9 | 947 | |
a127c4e5 RK |
948 | cr5 is not supposed to be used. |
949 | ||
950 | On System V implementations, r13 is fixed and not available for use. */ | |
951 | ||
f045b2c9 | 952 | #define FIXED_REGISTERS \ |
5dead3e5 | 953 | {0, 1, FIXED_R2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, FIXED_R13, 0, 0, \ |
f045b2c9 RS |
954 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ |
955 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
956 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
0ac081f6 AH |
957 | 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 1, \ |
958 | /* AltiVec registers. */ \ | |
959 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
960 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
5f004351 | 961 | 1, 1 \ |
7d5175e1 | 962 | , 1, 1, 1 \ |
0ac081f6 | 963 | } |
f045b2c9 RS |
964 | |
965 | /* 1 for registers not available across function calls. | |
966 | These must include the FIXED_REGISTERS and also any | |
967 | registers that can be used without being saved. | |
968 | The latter must include the registers where values are returned | |
969 | and the register where structure-value addresses are passed. | |
970 | Aside from that, you can include as many other registers as you like. */ | |
971 | ||
972 | #define CALL_USED_REGISTERS \ | |
a127c4e5 | 973 | {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, FIXED_R13, 0, 0, \ |
f045b2c9 RS |
974 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ |
975 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, \ | |
976 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
0ac081f6 AH |
977 | 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, \ |
978 | /* AltiVec registers. */ \ | |
979 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
980 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
5f004351 | 981 | 1, 1 \ |
7d5175e1 | 982 | , 1, 1, 1 \ |
0ac081f6 AH |
983 | } |
984 | ||
289e96b2 AH |
985 | /* Like `CALL_USED_REGISTERS' except this macro doesn't require that |
986 | the entire set of `FIXED_REGISTERS' be included. | |
987 | (`CALL_USED_REGISTERS' must be a superset of `FIXED_REGISTERS'). | |
988 | This macro is optional. If not specified, it defaults to the value | |
989 | of `CALL_USED_REGISTERS'. */ | |
f676971a | 990 | |
289e96b2 AH |
991 | #define CALL_REALLY_USED_REGISTERS \ |
992 | {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, FIXED_R13, 0, 0, \ | |
993 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
994 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, \ | |
995 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
996 | 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, \ | |
997 | /* AltiVec registers. */ \ | |
998 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
999 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
5f004351 | 1000 | 0, 0 \ |
7d5175e1 | 1001 | , 0, 0, 0 \ |
289e96b2 | 1002 | } |
f045b2c9 | 1003 | |
28bcfd4d | 1004 | #define TOTAL_ALTIVEC_REGS (LAST_ALTIVEC_REGNO - FIRST_ALTIVEC_REGNO + 1) |
9ebbca7d | 1005 | |
d62294f5 | 1006 | #define FIRST_SAVED_ALTIVEC_REGNO (FIRST_ALTIVEC_REGNO+20) |
b427dd7a AM |
1007 | #define FIRST_SAVED_FP_REGNO (14+32) |
1008 | #define FIRST_SAVED_GP_REGNO (FIXED_R13 ? 14 : 13) | |
d62294f5 | 1009 | |
f045b2c9 RS |
1010 | /* List the order in which to allocate registers. Each register must be |
1011 | listed once, even those in FIXED_REGISTERS. | |
1012 | ||
1013 | We allocate in the following order: | |
1014 | fp0 (not saved or used for anything) | |
1015 | fp13 - fp2 (not saved; incoming fp arg registers) | |
1016 | fp1 (not saved; return value) | |
9390387d | 1017 | fp31 - fp14 (saved; order given to save least number) |
5accd822 DE |
1018 | cr7, cr6 (not saved or special) |
1019 | cr1 (not saved, but used for FP operations) | |
f045b2c9 | 1020 | cr0 (not saved, but used for arithmetic operations) |
5accd822 | 1021 | cr4, cr3, cr2 (saved) |
f045b2c9 | 1022 | r9 (not saved; best for TImode) |
d44b26bd | 1023 | r10, r8-r4 (not saved; highest first for less conflict with params) |
9390387d | 1024 | r3 (not saved; return value register) |
d44b26bd AM |
1025 | r11 (not saved; later alloc to help shrink-wrap) |
1026 | r0 (not saved; cannot be base reg) | |
f045b2c9 RS |
1027 | r31 - r13 (saved; order given to save least number) |
1028 | r12 (not saved; if used for DImode or DFmode would use r13) | |
f045b2c9 RS |
1029 | ctr (not saved; when we have the choice ctr is better) |
1030 | lr (saved) | |
f6b5d695 | 1031 | cr5, r1, r2, ap, ca (fixed) |
9390387d AM |
1032 | v0 - v1 (not saved or used for anything) |
1033 | v13 - v3 (not saved; incoming vector arg registers) | |
1034 | v2 (not saved; incoming vector arg reg; return value) | |
1035 | v19 - v14 (not saved or used for anything) | |
1036 | v31 - v20 (saved; order given to save least number) | |
1037 | vrsave, vscr (fixed) | |
a3170dc6 | 1038 | spe_acc, spefscr (fixed) |
7d5175e1 | 1039 | sfp (fixed) |
0ac081f6 | 1040 | */ |
f676971a | 1041 | |
6b13641d DJ |
1042 | #if FIXED_R2 == 1 |
1043 | #define MAYBE_R2_AVAILABLE | |
1044 | #define MAYBE_R2_FIXED 2, | |
1045 | #else | |
1046 | #define MAYBE_R2_AVAILABLE 2, | |
1047 | #define MAYBE_R2_FIXED | |
1048 | #endif | |
f045b2c9 | 1049 | |
d44b26bd AM |
1050 | #if FIXED_R13 == 1 |
1051 | #define EARLY_R12 12, | |
1052 | #define LATE_R12 | |
1053 | #else | |
1054 | #define EARLY_R12 | |
1055 | #define LATE_R12 12, | |
1056 | #endif | |
1057 | ||
9390387d AM |
1058 | #define REG_ALLOC_ORDER \ |
1059 | {32, \ | |
f62511da MM |
1060 | /* move fr13 (ie 45) later, so if we need TFmode, it does */ \ |
1061 | /* not use fr14 which is a saved register. */ \ | |
1062 | 44, 43, 42, 41, 40, 39, 38, 37, 36, 35, 34, 45, \ | |
9390387d AM |
1063 | 33, \ |
1064 | 63, 62, 61, 60, 59, 58, 57, 56, 55, 54, 53, 52, 51, \ | |
1065 | 50, 49, 48, 47, 46, \ | |
1066 | 75, 74, 69, 68, 72, 71, 70, \ | |
d44b26bd AM |
1067 | MAYBE_R2_AVAILABLE \ |
1068 | 9, 10, 8, 7, 6, 5, 4, \ | |
1069 | 3, EARLY_R12 11, 0, \ | |
9390387d | 1070 | 31, 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, 20, 19, \ |
d44b26bd | 1071 | 18, 17, 16, 15, 14, 13, LATE_R12 \ |
462f7901 | 1072 | 66, 65, \ |
9390387d AM |
1073 | 73, 1, MAYBE_R2_FIXED 67, 76, \ |
1074 | /* AltiVec registers. */ \ | |
1075 | 77, 78, \ | |
1076 | 90, 89, 88, 87, 86, 85, 84, 83, 82, 81, 80, \ | |
1077 | 79, \ | |
1078 | 96, 95, 94, 93, 92, 91, \ | |
1079 | 108, 107, 106, 105, 104, 103, 102, 101, 100, 99, 98, 97, \ | |
1080 | 109, 110, \ | |
7d5175e1 | 1081 | 111, 112, 113 \ |
0ac081f6 | 1082 | } |
f045b2c9 RS |
1083 | |
1084 | /* True if register is floating-point. */ | |
1085 | #define FP_REGNO_P(N) ((N) >= 32 && (N) <= 63) | |
1086 | ||
1087 | /* True if register is a condition register. */ | |
1de43f85 | 1088 | #define CR_REGNO_P(N) ((N) >= CR0_REGNO && (N) <= CR7_REGNO) |
f045b2c9 | 1089 | |
815cdc52 | 1090 | /* True if register is a condition register, but not cr0. */ |
1de43f85 | 1091 | #define CR_REGNO_NOT_CR0_P(N) ((N) >= CR1_REGNO && (N) <= CR7_REGNO) |
815cdc52 | 1092 | |
f045b2c9 | 1093 | /* True if register is an integer register. */ |
7d5175e1 JJ |
1094 | #define INT_REGNO_P(N) \ |
1095 | ((N) <= 31 || (N) == ARG_POINTER_REGNUM || (N) == FRAME_POINTER_REGNUM) | |
f045b2c9 | 1096 | |
a3170dc6 AH |
1097 | /* SPE SIMD registers are just the GPRs. */ |
1098 | #define SPE_SIMD_REGNO_P(N) ((N) <= 31) | |
1099 | ||
96038623 DE |
1100 | /* PAIRED SIMD registers are just the FPRs. */ |
1101 | #define PAIRED_SIMD_REGNO_P(N) ((N) >= 32 && (N) <= 63) | |
1102 | ||
f6b5d695 SB |
1103 | /* True if register is the CA register. */ |
1104 | #define CA_REGNO_P(N) ((N) == CA_REGNO) | |
802a0058 | 1105 | |
0ac081f6 AH |
1106 | /* True if register is an AltiVec register. */ |
1107 | #define ALTIVEC_REGNO_P(N) ((N) >= FIRST_ALTIVEC_REGNO && (N) <= LAST_ALTIVEC_REGNO) | |
1108 | ||
cacf1ca8 MM |
1109 | /* True if register is a VSX register. */ |
1110 | #define VSX_REGNO_P(N) (FP_REGNO_P (N) || ALTIVEC_REGNO_P (N)) | |
1111 | ||
1112 | /* Alternate name for any vector register supporting floating point, no matter | |
1113 | which instruction set(s) are available. */ | |
1114 | #define VFLOAT_REGNO_P(N) \ | |
1115 | (ALTIVEC_REGNO_P (N) || (TARGET_VSX && FP_REGNO_P (N))) | |
1116 | ||
1117 | /* Alternate name for any vector register supporting integer, no matter which | |
1118 | instruction set(s) are available. */ | |
1119 | #define VINT_REGNO_P(N) ALTIVEC_REGNO_P (N) | |
1120 | ||
1121 | /* Alternate name for any vector register supporting logical operations, no | |
0bd62dca MM |
1122 | matter which instruction set(s) are available. For 64-bit mode, we also |
1123 | allow logical operations in the GPRS. This is to allow atomic quad word | |
1124 | builtins not to need the VSX registers for lqarx/stqcx. It also helps with | |
1125 | __int128_t arguments that are passed in GPRs. */ | |
f62511da MM |
1126 | #define VLOGICAL_REGNO_P(N) \ |
1127 | (ALTIVEC_REGNO_P (N) \ | |
1128 | || (TARGET_VSX && FP_REGNO_P (N)) \ | |
1129 | || (TARGET_VSX && TARGET_POWERPC64 && INT_REGNO_P (N))) | |
cacf1ca8 | 1130 | |
f045b2c9 | 1131 | /* Return number of consecutive hard regs needed starting at reg REGNO |
d8ecbcdb AH |
1132 | to hold something of mode MODE. */ |
1133 | ||
cacf1ca8 | 1134 | #define HARD_REGNO_NREGS(REGNO, MODE) rs6000_hard_regno_nregs[(MODE)][(REGNO)] |
0e67400a | 1135 | |
79eefb0d | 1136 | /* When setting up caller-save slots (MODE == VOIDmode) ensure we allocate |
5ec6aff2 MM |
1137 | enough space to account for vectors in FP regs. However, TFmode/TDmode |
1138 | should not use VSX instructions to do a caller save. */ | |
dbcc9f08 MM |
1139 | #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \ |
1140 | (TARGET_VSX \ | |
1141 | && ((MODE) == VOIDmode || ALTIVEC_OR_VSX_VECTOR_MODE (MODE)) \ | |
5ec6aff2 MM |
1142 | && FP_REGNO_P (REGNO) \ |
1143 | ? V2DFmode \ | |
1144 | : ((MODE) == TFmode && FP_REGNO_P (REGNO)) \ | |
1145 | ? DFmode \ | |
1146 | : ((MODE) == TDmode && FP_REGNO_P (REGNO)) \ | |
1147 | ? DImode \ | |
79eefb0d PH |
1148 | : choose_hard_reg_mode ((REGNO), (NREGS), false)) |
1149 | ||
3fc841c8 MM |
1150 | #define HARD_REGNO_CALL_PART_CLOBBERED(REGNO, MODE) \ |
1151 | (((TARGET_32BIT && TARGET_POWERPC64 \ | |
1152 | && (GET_MODE_SIZE (MODE) > 4) \ | |
1153 | && INT_REGNO_P (REGNO)) ? 1 : 0) \ | |
1154 | || (TARGET_VSX && FP_REGNO_P (REGNO) \ | |
5ec6aff2 MM |
1155 | && GET_MODE_SIZE (MODE) > 8 && ((MODE) != TDmode) \ |
1156 | && ((MODE) != TFmode))) | |
f045b2c9 | 1157 | |
cacf1ca8 MM |
1158 | #define VSX_VECTOR_MODE(MODE) \ |
1159 | ((MODE) == V4SFmode \ | |
1160 | || (MODE) == V2DFmode) \ | |
1161 | ||
0ac081f6 | 1162 | #define ALTIVEC_VECTOR_MODE(MODE) \ |
cb2a532e AH |
1163 | ((MODE) == V16QImode \ |
1164 | || (MODE) == V8HImode \ | |
1165 | || (MODE) == V4SFmode \ | |
6e1f54e2 | 1166 | || (MODE) == V4SImode) |
0ac081f6 | 1167 | |
dbcc9f08 MM |
1168 | #define ALTIVEC_OR_VSX_VECTOR_MODE(MODE) \ |
1169 | (ALTIVEC_VECTOR_MODE (MODE) || VSX_VECTOR_MODE (MODE) \ | |
1170 | || (MODE) == V2DImode) | |
1171 | ||
a3170dc6 AH |
1172 | #define SPE_VECTOR_MODE(MODE) \ |
1173 | ((MODE) == V4HImode \ | |
1174 | || (MODE) == V2SFmode \ | |
00a892b8 | 1175 | || (MODE) == V1DImode \ |
a3170dc6 AH |
1176 | || (MODE) == V2SImode) |
1177 | ||
96038623 DE |
1178 | #define PAIRED_VECTOR_MODE(MODE) \ |
1179 | ((MODE) == V2SFmode) | |
1180 | ||
0d1fbc8c AH |
1181 | /* Value is TRUE if hard register REGNO can hold a value of |
1182 | machine-mode MODE. */ | |
1183 | #define HARD_REGNO_MODE_OK(REGNO, MODE) \ | |
1184 | rs6000_hard_regno_mode_ok_p[(int)(MODE)][REGNO] | |
f045b2c9 RS |
1185 | |
1186 | /* Value is 1 if it is a good idea to tie two pseudo registers | |
1187 | when one has mode MODE1 and one has mode MODE2. | |
1188 | If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, | |
1189 | for any hard reg, then this must be 0 for correct output. */ | |
f62511da | 1190 | #define MODES_TIEABLE_P(MODE1, MODE2) \ |
ebb109ad BE |
1191 | (SCALAR_FLOAT_MODE_P (MODE1) \ |
1192 | ? SCALAR_FLOAT_MODE_P (MODE2) \ | |
1193 | : SCALAR_FLOAT_MODE_P (MODE2) \ | |
1194 | ? SCALAR_FLOAT_MODE_P (MODE1) \ | |
f045b2c9 RS |
1195 | : GET_MODE_CLASS (MODE1) == MODE_CC \ |
1196 | ? GET_MODE_CLASS (MODE2) == MODE_CC \ | |
1197 | : GET_MODE_CLASS (MODE2) == MODE_CC \ | |
1198 | ? GET_MODE_CLASS (MODE1) == MODE_CC \ | |
4dcc01f3 AH |
1199 | : SPE_VECTOR_MODE (MODE1) \ |
1200 | ? SPE_VECTOR_MODE (MODE2) \ | |
1201 | : SPE_VECTOR_MODE (MODE2) \ | |
1202 | ? SPE_VECTOR_MODE (MODE1) \ | |
dbcc9f08 MM |
1203 | : ALTIVEC_OR_VSX_VECTOR_MODE (MODE1) \ |
1204 | ? ALTIVEC_OR_VSX_VECTOR_MODE (MODE2) \ | |
1205 | : ALTIVEC_OR_VSX_VECTOR_MODE (MODE2) \ | |
1206 | ? ALTIVEC_OR_VSX_VECTOR_MODE (MODE1) \ | |
f62511da MM |
1207 | : ALTIVEC_VECTOR_MODE (MODE1) \ |
1208 | ? ALTIVEC_VECTOR_MODE (MODE2) \ | |
1209 | : ALTIVEC_VECTOR_MODE (MODE2) \ | |
1210 | ? ALTIVEC_VECTOR_MODE (MODE1) \ | |
f045b2c9 RS |
1211 | : 1) |
1212 | ||
c8ae788f SB |
1213 | /* Post-reload, we can't use any new AltiVec registers, as we already |
1214 | emitted the vrsave mask. */ | |
1215 | ||
1216 | #define HARD_REGNO_RENAME_OK(SRC, DST) \ | |
6fb5fa3c | 1217 | (! ALTIVEC_REGNO_P (DST) || df_regs_ever_live_p (DST)) |
c8ae788f | 1218 | |
f045b2c9 RS |
1219 | /* Specify the cost of a branch insn; roughly the number of extra insns that |
1220 | should be added to avoid a branch. | |
1221 | ||
ef457bda | 1222 | Set this to 3 on the RS/6000 since that is roughly the average cost of an |
f045b2c9 RS |
1223 | unscheduled conditional branch. */ |
1224 | ||
3a4fd356 | 1225 | #define BRANCH_COST(speed_p, predictable_p) 3 |
f045b2c9 | 1226 | |
85e50b6b | 1227 | /* Override BRANCH_COST heuristic which empirically produces worse |
b8610a53 | 1228 | performance for removing short circuiting from the logical ops. */ |
85e50b6b | 1229 | |
b8610a53 | 1230 | #define LOGICAL_OP_NON_SHORT_CIRCUIT 0 |
a3170dc6 | 1231 | |
52ff33d0 NF |
1232 | /* A fixed register used at epilogue generation to address SPE registers |
1233 | with negative offsets. The 64-bit load/store instructions on the SPE | |
1234 | only take positive offsets (and small ones at that), so we need to | |
1235 | reserve a register for consing up negative offsets. */ | |
a3170dc6 | 1236 | |
52ff33d0 | 1237 | #define FIXED_SCRATCH 0 |
a3170dc6 | 1238 | |
f045b2c9 RS |
1239 | /* Specify the registers used for certain standard purposes. |
1240 | The values of these macros are register numbers. */ | |
1241 | ||
1242 | /* RS/6000 pc isn't overloaded on a register that the compiler knows about. */ | |
1243 | /* #define PC_REGNUM */ | |
1244 | ||
1245 | /* Register to use for pushing function arguments. */ | |
1246 | #define STACK_POINTER_REGNUM 1 | |
1247 | ||
1248 | /* Base register for access to local variables of the function. */ | |
7d5175e1 JJ |
1249 | #define HARD_FRAME_POINTER_REGNUM 31 |
1250 | ||
1251 | /* Base register for access to local variables of the function. */ | |
1252 | #define FRAME_POINTER_REGNUM 113 | |
f045b2c9 | 1253 | |
f045b2c9 RS |
1254 | /* Base register for access to arguments of the function. */ |
1255 | #define ARG_POINTER_REGNUM 67 | |
1256 | ||
1257 | /* Place to put static chain when calling a function that requires it. */ | |
1258 | #define STATIC_CHAIN_REGNUM 11 | |
1259 | ||
f045b2c9 RS |
1260 | \f |
1261 | /* Define the classes of registers for register constraints in the | |
1262 | machine description. Also define ranges of constants. | |
1263 | ||
1264 | One of the classes must always be named ALL_REGS and include all hard regs. | |
1265 | If there is more than one class, another class must be named NO_REGS | |
1266 | and contain no registers. | |
1267 | ||
1268 | The name GENERAL_REGS must be the name of a class (or an alias for | |
1269 | another name such as ALL_REGS). This is the class of registers | |
1270 | that is allowed by "g" or "r" in a register constraint. | |
1271 | Also, registers outside this class are allocated only when | |
1272 | instructions express preferences for them. | |
1273 | ||
1274 | The classes must be numbered in nondecreasing order; that is, | |
1275 | a larger-numbered class must never be contained completely | |
1276 | in a smaller-numbered class. | |
1277 | ||
1278 | For any two classes, it is very desirable that there be another | |
1279 | class that represents their union. */ | |
c81bebd7 | 1280 | |
cacf1ca8 | 1281 | /* The RS/6000 has three types of registers, fixed-point, floating-point, and |
462f7901 | 1282 | condition registers, plus three special registers, CTR, and the link |
cacf1ca8 MM |
1283 | register. AltiVec adds a vector register class. VSX registers overlap the |
1284 | FPR registers and the Altivec registers. | |
f045b2c9 RS |
1285 | |
1286 | However, r0 is special in that it cannot be used as a base register. | |
1287 | So make a class for registers valid as base registers. | |
1288 | ||
1289 | Also, cr0 is the only condition code register that can be used in | |
0d86f538 | 1290 | arithmetic insns, so make a separate class for it. */ |
f045b2c9 | 1291 | |
ebedb4dd MM |
1292 | enum reg_class |
1293 | { | |
1294 | NO_REGS, | |
ebedb4dd MM |
1295 | BASE_REGS, |
1296 | GENERAL_REGS, | |
1297 | FLOAT_REGS, | |
0ac081f6 | 1298 | ALTIVEC_REGS, |
8beb65e3 | 1299 | VSX_REGS, |
0ac081f6 | 1300 | VRSAVE_REGS, |
5f004351 | 1301 | VSCR_REGS, |
a3170dc6 AH |
1302 | SPE_ACC_REGS, |
1303 | SPEFSCR_REGS, | |
ebedb4dd | 1304 | NON_SPECIAL_REGS, |
ebedb4dd MM |
1305 | LINK_REGS, |
1306 | CTR_REGS, | |
1307 | LINK_OR_CTR_REGS, | |
1308 | SPECIAL_REGS, | |
1309 | SPEC_OR_GEN_REGS, | |
1310 | CR0_REGS, | |
ebedb4dd MM |
1311 | CR_REGS, |
1312 | NON_FLOAT_REGS, | |
f6b5d695 | 1313 | CA_REGS, |
ebedb4dd MM |
1314 | ALL_REGS, |
1315 | LIM_REG_CLASSES | |
1316 | }; | |
f045b2c9 RS |
1317 | |
1318 | #define N_REG_CLASSES (int) LIM_REG_CLASSES | |
1319 | ||
82e41834 | 1320 | /* Give names of register classes as strings for dump file. */ |
f045b2c9 | 1321 | |
ebedb4dd MM |
1322 | #define REG_CLASS_NAMES \ |
1323 | { \ | |
1324 | "NO_REGS", \ | |
ebedb4dd MM |
1325 | "BASE_REGS", \ |
1326 | "GENERAL_REGS", \ | |
1327 | "FLOAT_REGS", \ | |
0ac081f6 | 1328 | "ALTIVEC_REGS", \ |
8beb65e3 | 1329 | "VSX_REGS", \ |
0ac081f6 | 1330 | "VRSAVE_REGS", \ |
5f004351 | 1331 | "VSCR_REGS", \ |
a3170dc6 AH |
1332 | "SPE_ACC_REGS", \ |
1333 | "SPEFSCR_REGS", \ | |
ebedb4dd | 1334 | "NON_SPECIAL_REGS", \ |
ebedb4dd MM |
1335 | "LINK_REGS", \ |
1336 | "CTR_REGS", \ | |
1337 | "LINK_OR_CTR_REGS", \ | |
1338 | "SPECIAL_REGS", \ | |
1339 | "SPEC_OR_GEN_REGS", \ | |
1340 | "CR0_REGS", \ | |
ebedb4dd MM |
1341 | "CR_REGS", \ |
1342 | "NON_FLOAT_REGS", \ | |
f6b5d695 | 1343 | "CA_REGS", \ |
ebedb4dd MM |
1344 | "ALL_REGS" \ |
1345 | } | |
f045b2c9 RS |
1346 | |
1347 | /* Define which registers fit in which classes. | |
1348 | This is an initializer for a vector of HARD_REG_SET | |
1349 | of length N_REG_CLASSES. */ | |
1350 | ||
0ac081f6 AH |
1351 | #define REG_CLASS_CONTENTS \ |
1352 | { \ | |
1353 | { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \ | |
7d5175e1 JJ |
1354 | { 0xfffffffe, 0x00000000, 0x00000008, 0x00020000 }, /* BASE_REGS */ \ |
1355 | { 0xffffffff, 0x00000000, 0x00000008, 0x00020000 }, /* GENERAL_REGS */ \ | |
0ac081f6 | 1356 | { 0x00000000, 0xffffffff, 0x00000000, 0x00000000 }, /* FLOAT_REGS */ \ |
089a05b8 | 1357 | { 0x00000000, 0x00000000, 0xffffe000, 0x00001fff }, /* ALTIVEC_REGS */ \ |
8beb65e3 | 1358 | { 0x00000000, 0xffffffff, 0xffffe000, 0x00001fff }, /* VSX_REGS */ \ |
089a05b8 | 1359 | { 0x00000000, 0x00000000, 0x00000000, 0x00002000 }, /* VRSAVE_REGS */ \ |
5f004351 | 1360 | { 0x00000000, 0x00000000, 0x00000000, 0x00004000 }, /* VSCR_REGS */ \ |
a3170dc6 AH |
1361 | { 0x00000000, 0x00000000, 0x00000000, 0x00008000 }, /* SPE_ACC_REGS */ \ |
1362 | { 0x00000000, 0x00000000, 0x00000000, 0x00010000 }, /* SPEFSCR_REGS */ \ | |
7d5175e1 | 1363 | { 0xffffffff, 0xffffffff, 0x00000008, 0x00020000 }, /* NON_SPECIAL_REGS */ \ |
0ac081f6 AH |
1364 | { 0x00000000, 0x00000000, 0x00000002, 0x00000000 }, /* LINK_REGS */ \ |
1365 | { 0x00000000, 0x00000000, 0x00000004, 0x00000000 }, /* CTR_REGS */ \ | |
1366 | { 0x00000000, 0x00000000, 0x00000006, 0x00000000 }, /* LINK_OR_CTR_REGS */ \ | |
462f7901 SB |
1367 | { 0x00000000, 0x00000000, 0x00000006, 0x00002000 }, /* SPECIAL_REGS */ \ |
1368 | { 0xffffffff, 0x00000000, 0x0000000e, 0x00022000 }, /* SPEC_OR_GEN_REGS */ \ | |
0ac081f6 AH |
1369 | { 0x00000000, 0x00000000, 0x00000010, 0x00000000 }, /* CR0_REGS */ \ |
1370 | { 0x00000000, 0x00000000, 0x00000ff0, 0x00000000 }, /* CR_REGS */ \ | |
462f7901 | 1371 | { 0xffffffff, 0x00000000, 0x00000ffe, 0x00020000 }, /* NON_FLOAT_REGS */ \ |
f6b5d695 | 1372 | { 0x00000000, 0x00000000, 0x00001000, 0x00000000 }, /* CA_REGS */ \ |
462f7901 | 1373 | { 0xffffffff, 0xffffffff, 0xfffffffe, 0x0003ffff } /* ALL_REGS */ \ |
ebedb4dd | 1374 | } |
f045b2c9 RS |
1375 | |
1376 | /* The same information, inverted: | |
1377 | Return the class number of the smallest class containing | |
1378 | reg number REGNO. This could be a conditional expression | |
1379 | or could index an array. */ | |
1380 | ||
cacf1ca8 MM |
1381 | extern enum reg_class rs6000_regno_regclass[FIRST_PSEUDO_REGISTER]; |
1382 | ||
1383 | #if ENABLE_CHECKING | |
1384 | #define REGNO_REG_CLASS(REGNO) \ | |
1385 | (gcc_assert (IN_RANGE ((REGNO), 0, FIRST_PSEUDO_REGISTER-1)), \ | |
1386 | rs6000_regno_regclass[(REGNO)]) | |
1387 | ||
1388 | #else | |
1389 | #define REGNO_REG_CLASS(REGNO) rs6000_regno_regclass[(REGNO)] | |
1390 | #endif | |
1391 | ||
a72c65c7 MM |
1392 | /* Register classes for various constraints that are based on the target |
1393 | switches. */ | |
1394 | enum r6000_reg_class_enum { | |
1395 | RS6000_CONSTRAINT_d, /* fpr registers for double values */ | |
1396 | RS6000_CONSTRAINT_f, /* fpr registers for single values */ | |
1397 | RS6000_CONSTRAINT_v, /* Altivec registers */ | |
1398 | RS6000_CONSTRAINT_wa, /* Any VSX register */ | |
1399 | RS6000_CONSTRAINT_wd, /* VSX register for V2DF */ | |
c6d5ff83 | 1400 | RS6000_CONSTRAINT_wg, /* FPR register for -mmfpgpr */ |
a72c65c7 | 1401 | RS6000_CONSTRAINT_wf, /* VSX register for V4SF */ |
c6d5ff83 | 1402 | RS6000_CONSTRAINT_wl, /* FPR register for LFIWAX */ |
f62511da MM |
1403 | RS6000_CONSTRAINT_wm, /* VSX register for direct move */ |
1404 | RS6000_CONSTRAINT_wr, /* GPR register if 64-bit */ | |
a72c65c7 | 1405 | RS6000_CONSTRAINT_ws, /* VSX register for DF */ |
c6d5ff83 | 1406 | RS6000_CONSTRAINT_wt, /* VSX register for TImode */ |
f62511da | 1407 | RS6000_CONSTRAINT_wv, /* Altivec register for power8 vector */ |
c6d5ff83 MM |
1408 | RS6000_CONSTRAINT_wx, /* FPR register for STFIWX */ |
1409 | RS6000_CONSTRAINT_wz, /* FPR register for LFIWZX */ | |
a72c65c7 MM |
1410 | RS6000_CONSTRAINT_MAX |
1411 | }; | |
1412 | ||
1413 | extern enum reg_class rs6000_constraints[RS6000_CONSTRAINT_MAX]; | |
f045b2c9 RS |
1414 | |
1415 | /* The class value for index registers, and the one for base regs. */ | |
1416 | #define INDEX_REG_CLASS GENERAL_REGS | |
1417 | #define BASE_REG_CLASS BASE_REGS | |
1418 | ||
cacf1ca8 MM |
1419 | /* Return whether a given register class can hold VSX objects. */ |
1420 | #define VSX_REG_CLASS_P(CLASS) \ | |
1421 | ((CLASS) == VSX_REGS || (CLASS) == FLOAT_REGS || (CLASS) == ALTIVEC_REGS) | |
1422 | ||
f045b2c9 RS |
1423 | /* Given an rtx X being reloaded into a reg required to be |
1424 | in class CLASS, return the class of reg to actually use. | |
1425 | In general this is just CLASS; but on some machines | |
c81bebd7 | 1426 | in some cases it is preferable to use a more restrictive class. |
f045b2c9 RS |
1427 | |
1428 | On the RS/6000, we have to return NO_REGS when we want to reload a | |
f676971a | 1429 | floating-point CONST_DOUBLE to force it to be copied to memory. |
1e66d555 GK |
1430 | |
1431 | We also don't want to reload integer values into floating-point | |
1432 | registers if we can at all help it. In fact, this can | |
37409796 | 1433 | cause reload to die, if it tries to generate a reload of CTR |
1e66d555 GK |
1434 | into a FP register and discovers it doesn't have the memory location |
1435 | required. | |
1436 | ||
1437 | ??? Would it be a good idea to have reload do the converse, that is | |
1438 | try to reload floating modes into FP registers if possible? | |
1439 | */ | |
f045b2c9 | 1440 | |
802a0058 | 1441 | #define PREFERRED_RELOAD_CLASS(X,CLASS) \ |
8beb65e3 | 1442 | rs6000_preferred_reload_class_ptr (X, CLASS) |
c81bebd7 | 1443 | |
f045b2c9 RS |
1444 | /* Return the register class of a scratch register needed to copy IN into |
1445 | or out of a register in CLASS in MODE. If it can be done directly, | |
1446 | NO_REGS is returned. */ | |
1447 | ||
1448 | #define SECONDARY_RELOAD_CLASS(CLASS,MODE,IN) \ | |
8beb65e3 | 1449 | rs6000_secondary_reload_class_ptr (CLASS, MODE, IN) |
f045b2c9 | 1450 | |
0ac081f6 | 1451 | /* If we are copying between FP or AltiVec registers and anything |
44cd321e PS |
1452 | else, we need a memory location. The exception is when we are |
1453 | targeting ppc64 and the move to/from fpr to gpr instructions | |
1454 | are available.*/ | |
1455 | ||
1456 | #define SECONDARY_MEMORY_NEEDED(CLASS1,CLASS2,MODE) \ | |
8beb65e3 | 1457 | rs6000_secondary_memory_needed_ptr (CLASS1, CLASS2, MODE) |
7ea555a4 | 1458 | |
e41b2a33 PB |
1459 | /* For cpus that cannot load/store SDmode values from the 64-bit |
1460 | FP registers without using a full 64-bit load/store, we need | |
1461 | to allocate a full 64-bit stack slot for them. */ | |
1462 | ||
1463 | #define SECONDARY_MEMORY_NEEDED_RTX(MODE) \ | |
1464 | rs6000_secondary_memory_needed_rtx (MODE) | |
1465 | ||
f045b2c9 RS |
1466 | /* Return the maximum number of consecutive registers |
1467 | needed to represent mode MODE in a register of class CLASS. | |
1468 | ||
cacf1ca8 MM |
1469 | On RS/6000, this is the size of MODE in words, except in the FP regs, where |
1470 | a single reg is enough for two words, unless we have VSX, where the FP | |
1471 | registers can hold 128 bits. */ | |
1472 | #define CLASS_MAX_NREGS(CLASS, MODE) rs6000_class_max_nregs[(MODE)][(CLASS)] | |
580d3230 | 1473 | |
ca0e79d9 AM |
1474 | /* Return nonzero if for CLASS a mode change from FROM to TO is invalid. */ |
1475 | ||
1476 | #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \ | |
8beb65e3 | 1477 | rs6000_cannot_change_mode_class_ptr (FROM, TO, CLASS) |
02188693 | 1478 | |
f045b2c9 RS |
1479 | /* Stack layout; function entry, exit and calling. */ |
1480 | ||
1481 | /* Define this if pushing a word on the stack | |
1482 | makes the stack pointer a smaller address. */ | |
1483 | #define STACK_GROWS_DOWNWARD | |
1484 | ||
327e5343 FJ |
1485 | /* Offsets recorded in opcodes are a multiple of this alignment factor. */ |
1486 | #define DWARF_CIE_DATA_ALIGNMENT (-((int) (TARGET_32BIT ? 4 : 8))) | |
1487 | ||
a4d05547 | 1488 | /* Define this to nonzero if the nominal address of the stack frame |
f045b2c9 RS |
1489 | is at the high-address end of the local variables; |
1490 | that is, each additional local variable allocated | |
1491 | goes at a more negative offset in the frame. | |
1492 | ||
1493 | On the RS/6000, we grow upwards, from the area after the outgoing | |
1494 | arguments. */ | |
957fee09 | 1495 | #define FRAME_GROWS_DOWNWARD (flag_stack_protect != 0 || flag_asan != 0) |
f045b2c9 | 1496 | |
4697a36c | 1497 | /* Size of the outgoing register save area */ |
9ebbca7d | 1498 | #define RS6000_REG_SAVE ((DEFAULT_ABI == ABI_AIX \ |
ee890fe2 | 1499 | || DEFAULT_ABI == ABI_DARWIN) \ |
9ebbca7d GK |
1500 | ? (TARGET_64BIT ? 64 : 32) \ |
1501 | : 0) | |
4697a36c MM |
1502 | |
1503 | /* Size of the fixed area on the stack */ | |
9ebbca7d | 1504 | #define RS6000_SAVE_AREA \ |
50d440bc | 1505 | (((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) ? 24 : 8) \ |
9ebbca7d | 1506 | << (TARGET_64BIT ? 1 : 0)) |
4697a36c | 1507 | |
97f6e72f DE |
1508 | /* MEM representing address to save the TOC register */ |
1509 | #define RS6000_SAVE_TOC gen_rtx_MEM (Pmode, \ | |
0a81f074 | 1510 | plus_constant (Pmode, stack_pointer_rtx, \ |
97f6e72f | 1511 | (TARGET_32BIT ? 20 : 40))) |
b6c9286a | 1512 | |
4697a36c | 1513 | /* Align an address */ |
ed33106f | 1514 | #define RS6000_ALIGN(n,a) (((n) + (a) - 1) & ~((a) - 1)) |
4697a36c | 1515 | |
f045b2c9 RS |
1516 | /* Offset within stack frame to start allocating local variables at. |
1517 | If FRAME_GROWS_DOWNWARD, this is the offset to the END of the | |
1518 | first local allocated. Otherwise, it is the offset to the BEGINNING | |
c81bebd7 | 1519 | of the first local allocated. |
f045b2c9 RS |
1520 | |
1521 | On the RS/6000, the frame pointer is the same as the stack pointer, | |
1522 | except for dynamic allocations. So we start after the fixed area and | |
1523 | outgoing parameter area. */ | |
1524 | ||
802a0058 | 1525 | #define STARTING_FRAME_OFFSET \ |
7d5175e1 JJ |
1526 | (FRAME_GROWS_DOWNWARD \ |
1527 | ? 0 \ | |
cacf1ca8 MM |
1528 | : (RS6000_ALIGN (crtl->outgoing_args_size, \ |
1529 | (TARGET_ALTIVEC || TARGET_VSX) ? 16 : 8) \ | |
7d5175e1 | 1530 | + RS6000_SAVE_AREA)) |
802a0058 MM |
1531 | |
1532 | /* Offset from the stack pointer register to an item dynamically | |
1533 | allocated on the stack, e.g., by `alloca'. | |
1534 | ||
1535 | The default value for this macro is `STACK_POINTER_OFFSET' plus the | |
1536 | length of the outgoing arguments. The default is correct for most | |
1537 | machines. See `function.c' for details. */ | |
1538 | #define STACK_DYNAMIC_OFFSET(FUNDECL) \ | |
cacf1ca8 MM |
1539 | (RS6000_ALIGN (crtl->outgoing_args_size, \ |
1540 | (TARGET_ALTIVEC || TARGET_VSX) ? 16 : 8) \ | |
802a0058 | 1541 | + (STACK_POINTER_OFFSET)) |
f045b2c9 RS |
1542 | |
1543 | /* If we generate an insn to push BYTES bytes, | |
1544 | this says how many the stack pointer really advances by. | |
1545 | On RS/6000, don't define this because there are no push insns. */ | |
1546 | /* #define PUSH_ROUNDING(BYTES) */ | |
1547 | ||
1548 | /* Offset of first parameter from the argument pointer register value. | |
1549 | On the RS/6000, we define the argument pointer to the start of the fixed | |
1550 | area. */ | |
4697a36c | 1551 | #define FIRST_PARM_OFFSET(FNDECL) RS6000_SAVE_AREA |
f045b2c9 | 1552 | |
62153b61 JM |
1553 | /* Offset from the argument pointer register value to the top of |
1554 | stack. This is different from FIRST_PARM_OFFSET because of the | |
1555 | register save area. */ | |
1556 | #define ARG_POINTER_CFA_OFFSET(FNDECL) 0 | |
1557 | ||
f045b2c9 RS |
1558 | /* Define this if stack space is still allocated for a parameter passed |
1559 | in a register. The value is the number of bytes allocated to this | |
1560 | area. */ | |
4697a36c | 1561 | #define REG_PARM_STACK_SPACE(FNDECL) RS6000_REG_SAVE |
f045b2c9 RS |
1562 | |
1563 | /* Define this if the above stack space is to be considered part of the | |
1564 | space allocated by the caller. */ | |
81464b2c | 1565 | #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1 |
f045b2c9 RS |
1566 | |
1567 | /* This is the difference between the logical top of stack and the actual sp. | |
1568 | ||
82e41834 | 1569 | For the RS/6000, sp points past the fixed area. */ |
4697a36c | 1570 | #define STACK_POINTER_OFFSET RS6000_SAVE_AREA |
f045b2c9 RS |
1571 | |
1572 | /* Define this if the maximum size of all the outgoing args is to be | |
1573 | accumulated and pushed during the prologue. The amount can be | |
38173d38 | 1574 | found in the variable crtl->outgoing_args_size. */ |
f73ad30e | 1575 | #define ACCUMULATE_OUTGOING_ARGS 1 |
f045b2c9 | 1576 | |
f045b2c9 RS |
1577 | /* Define how to find the value returned by a library function |
1578 | assuming the value has mode MODE. */ | |
1579 | ||
ded9bf77 | 1580 | #define LIBCALL_VALUE(MODE) rs6000_libcall_value ((MODE)) |
f045b2c9 | 1581 | |
6fa3f289 ZW |
1582 | /* DRAFT_V4_STRUCT_RET defaults off. */ |
1583 | #define DRAFT_V4_STRUCT_RET 0 | |
f607bc57 | 1584 | |
bd5bd7ac | 1585 | /* Let TARGET_RETURN_IN_MEMORY control what happens. */ |
f607bc57 | 1586 | #define DEFAULT_PCC_STRUCT_RETURN 0 |
f045b2c9 | 1587 | |
a260abc9 | 1588 | /* Mode of stack savearea. |
dfdfa60f DE |
1589 | FUNCTION is VOIDmode because calling convention maintains SP. |
1590 | BLOCK needs Pmode for SP. | |
a260abc9 DE |
1591 | NONLOCAL needs twice Pmode to maintain both backchain and SP. */ |
1592 | #define STACK_SAVEAREA_MODE(LEVEL) \ | |
dfdfa60f | 1593 | (LEVEL == SAVE_FUNCTION ? VOIDmode \ |
c6d5ff83 | 1594 | : LEVEL == SAVE_NONLOCAL ? (TARGET_32BIT ? DImode : PTImode) : Pmode) |
a260abc9 | 1595 | |
4697a36c MM |
1596 | /* Minimum and maximum general purpose registers used to hold arguments. */ |
1597 | #define GP_ARG_MIN_REG 3 | |
1598 | #define GP_ARG_MAX_REG 10 | |
1599 | #define GP_ARG_NUM_REG (GP_ARG_MAX_REG - GP_ARG_MIN_REG + 1) | |
1600 | ||
1601 | /* Minimum and maximum floating point registers used to hold arguments. */ | |
1602 | #define FP_ARG_MIN_REG 33 | |
7509c759 MM |
1603 | #define FP_ARG_AIX_MAX_REG 45 |
1604 | #define FP_ARG_V4_MAX_REG 40 | |
9ebbca7d | 1605 | #define FP_ARG_MAX_REG ((DEFAULT_ABI == ABI_AIX \ |
ee890fe2 | 1606 | || DEFAULT_ABI == ABI_DARWIN) \ |
9ebbca7d | 1607 | ? FP_ARG_AIX_MAX_REG : FP_ARG_V4_MAX_REG) |
4697a36c MM |
1608 | #define FP_ARG_NUM_REG (FP_ARG_MAX_REG - FP_ARG_MIN_REG + 1) |
1609 | ||
0ac081f6 AH |
1610 | /* Minimum and maximum AltiVec registers used to hold arguments. */ |
1611 | #define ALTIVEC_ARG_MIN_REG (FIRST_ALTIVEC_REGNO + 2) | |
1612 | #define ALTIVEC_ARG_MAX_REG (ALTIVEC_ARG_MIN_REG + 11) | |
1613 | #define ALTIVEC_ARG_NUM_REG (ALTIVEC_ARG_MAX_REG - ALTIVEC_ARG_MIN_REG + 1) | |
1614 | ||
4697a36c MM |
1615 | /* Return registers */ |
1616 | #define GP_ARG_RETURN GP_ARG_MIN_REG | |
1617 | #define FP_ARG_RETURN FP_ARG_MIN_REG | |
0ac081f6 | 1618 | #define ALTIVEC_ARG_RETURN (FIRST_ALTIVEC_REGNO + 2) |
4697a36c | 1619 | |
7509c759 | 1620 | /* Flags for the call/call_value rtl operations set up by function_arg */ |
6a4cee5f | 1621 | #define CALL_NORMAL 0x00000000 /* no special processing */ |
9ebbca7d | 1622 | /* Bits in 0x00000001 are unused. */ |
6a4cee5f MM |
1623 | #define CALL_V4_CLEAR_FP_ARGS 0x00000002 /* V.4, no FP args passed */ |
1624 | #define CALL_V4_SET_FP_ARGS 0x00000004 /* V.4, FP args were passed */ | |
1625 | #define CALL_LONG 0x00000008 /* always call indirect */ | |
b9599e46 | 1626 | #define CALL_LIBCALL 0x00000010 /* libcall */ |
7509c759 | 1627 | |
f57fe068 AM |
1628 | /* We don't have prologue and epilogue functions to save/restore |
1629 | everything for most ABIs. */ | |
1630 | #define WORLD_SAVE_P(INFO) 0 | |
1631 | ||
f045b2c9 RS |
1632 | /* 1 if N is a possible register number for a function value |
1633 | as seen by the caller. | |
1634 | ||
0ac081f6 | 1635 | On RS/6000, this is r3, fp1, and v2 (for AltiVec). */ |
e87a88d3 AM |
1636 | #define FUNCTION_VALUE_REGNO_P(N) \ |
1637 | ((N) == GP_ARG_RETURN \ | |
b2df7d08 | 1638 | || ((N) == FP_ARG_RETURN && TARGET_HARD_FLOAT && TARGET_FPRS) \ |
44688022 | 1639 | || ((N) == ALTIVEC_ARG_RETURN && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI)) |
f045b2c9 RS |
1640 | |
1641 | /* 1 if N is a possible register number for function argument passing. | |
0ac081f6 AH |
1642 | On RS/6000, these are r3-r10 and fp1-fp13. |
1643 | On AltiVec, v2 - v13 are used for passing vectors. */ | |
4697a36c | 1644 | #define FUNCTION_ARG_REGNO_P(N) \ |
e87a88d3 AM |
1645 | ((unsigned) (N) - GP_ARG_MIN_REG < GP_ARG_NUM_REG \ |
1646 | || ((unsigned) (N) - ALTIVEC_ARG_MIN_REG < ALTIVEC_ARG_NUM_REG \ | |
44688022 | 1647 | && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI) \ |
e87a88d3 | 1648 | || ((unsigned) (N) - FP_ARG_MIN_REG < FP_ARG_NUM_REG \ |
b2df7d08 | 1649 | && TARGET_HARD_FLOAT && TARGET_FPRS)) |
f045b2c9 RS |
1650 | \f |
1651 | /* Define a data type for recording info about an argument list | |
1652 | during the scan of that argument list. This data type should | |
1653 | hold all necessary information about the function itself | |
1654 | and about the args processed so far, enough to enable macros | |
1655 | such as FUNCTION_ARG to determine where the next arg should go. | |
1656 | ||
1657 | On the RS/6000, this is a structure. The first element is the number of | |
1658 | total argument words, the second is used to store the next | |
1659 | floating-point register number, and the third says how many more args we | |
4697a36c MM |
1660 | have prototype types for. |
1661 | ||
4cc833b7 | 1662 | For ABI_V4, we treat these slightly differently -- `sysv_gregno' is |
07488f32 | 1663 | the next available GP register, `fregno' is the next available FP |
4cc833b7 RH |
1664 | register, and `words' is the number of words used on the stack. |
1665 | ||
bd227acc | 1666 | The varargs/stdarg support requires that this structure's size |
4cc833b7 | 1667 | be a multiple of sizeof(int). */ |
4697a36c MM |
1668 | |
1669 | typedef struct rs6000_args | |
1670 | { | |
4cc833b7 | 1671 | int words; /* # words used for passing GP registers */ |
6a4cee5f | 1672 | int fregno; /* next available FP register */ |
0ac081f6 | 1673 | int vregno; /* next available AltiVec register */ |
6a4cee5f | 1674 | int nargs_prototype; /* # args left in the current prototype */ |
6a4cee5f | 1675 | int prototype; /* Whether a prototype was defined */ |
a6c9bed4 | 1676 | int stdarg; /* Whether function is a stdarg function. */ |
6a4cee5f | 1677 | int call_cookie; /* Do special things for this call */ |
4cc833b7 | 1678 | int sysv_gregno; /* next available GP register */ |
0b5383eb DJ |
1679 | int intoffset; /* running offset in struct (darwin64) */ |
1680 | int use_stack; /* any part of struct on stack (darwin64) */ | |
a9ab25e2 IS |
1681 | int floats_in_gpr; /* count of SFmode floats taking up |
1682 | GPR space (darwin64) */ | |
0b5383eb | 1683 | int named; /* false for varargs params */ |
617718f7 | 1684 | int escapes; /* if function visible outside tu */ |
4697a36c | 1685 | } CUMULATIVE_ARGS; |
f045b2c9 | 1686 | |
f045b2c9 RS |
1687 | /* Initialize a variable CUM of type CUMULATIVE_ARGS |
1688 | for a call to a function whose data type is FNTYPE. | |
1689 | For a library call, FNTYPE is 0. */ | |
1690 | ||
617718f7 AM |
1691 | #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \ |
1692 | init_cumulative_args (&CUM, FNTYPE, LIBNAME, FALSE, FALSE, \ | |
1693 | N_NAMED_ARGS, FNDECL, VOIDmode) | |
f045b2c9 RS |
1694 | |
1695 | /* Similar, but when scanning the definition of a procedure. We always | |
1696 | set NARGS_PROTOTYPE large so we never return an EXPR_LIST. */ | |
1697 | ||
0f6937fe | 1698 | #define INIT_CUMULATIVE_INCOMING_ARGS(CUM, FNTYPE, LIBNAME) \ |
617718f7 AM |
1699 | init_cumulative_args (&CUM, FNTYPE, LIBNAME, TRUE, FALSE, \ |
1700 | 1000, current_function_decl, VOIDmode) | |
b9599e46 FS |
1701 | |
1702 | /* Like INIT_CUMULATIVE_ARGS' but only used for outgoing libcalls. */ | |
1703 | ||
1704 | #define INIT_CUMULATIVE_LIBCALL_ARGS(CUM, MODE, LIBNAME) \ | |
617718f7 AM |
1705 | init_cumulative_args (&CUM, NULL_TREE, LIBNAME, FALSE, TRUE, \ |
1706 | 0, NULL_TREE, MODE) | |
f045b2c9 | 1707 | |
c229cba9 DE |
1708 | /* If defined, a C expression which determines whether, and in which |
1709 | direction, to pad out an argument with extra space. The value | |
1710 | should be of type `enum direction': either `upward' to pad above | |
1711 | the argument, `downward' to pad below, or `none' to inhibit | |
1712 | padding. */ | |
1713 | ||
9ebbca7d | 1714 | #define FUNCTION_ARG_PADDING(MODE, TYPE) function_arg_padding (MODE, TYPE) |
c229cba9 | 1715 | |
6e985040 AM |
1716 | #define PAD_VARARGS_DOWN \ |
1717 | (FUNCTION_ARG_PADDING (TYPE_MODE (type), type) == downward) | |
2a55fd42 | 1718 | |
f045b2c9 | 1719 | /* Output assembler code to FILE to increment profiler label # LABELNO |
58a39e45 | 1720 | for profiling a function entry. */ |
f045b2c9 RS |
1721 | |
1722 | #define FUNCTION_PROFILER(FILE, LABELNO) \ | |
58a39e45 | 1723 | output_function_profiler ((FILE), (LABELNO)); |
f045b2c9 RS |
1724 | |
1725 | /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, | |
1726 | the stack pointer does not matter. No definition is equivalent to | |
1727 | always zero. | |
1728 | ||
a0ab749a | 1729 | On the RS/6000, this is nonzero because we can restore the stack from |
f045b2c9 RS |
1730 | its backpointer, which we maintain. */ |
1731 | #define EXIT_IGNORE_STACK 1 | |
1732 | ||
a701949a FS |
1733 | /* Define this macro as a C expression that is nonzero for registers |
1734 | that are used by the epilogue or the return' pattern. The stack | |
1735 | and frame pointer registers are already be assumed to be used as | |
1736 | needed. */ | |
1737 | ||
83720594 | 1738 | #define EPILOGUE_USES(REGNO) \ |
1de43f85 | 1739 | ((reload_completed && (REGNO) == LR_REGNO) \ |
b1765bde | 1740 | || (TARGET_ALTIVEC && (REGNO) == VRSAVE_REGNO) \ |
cacf1ca8 | 1741 | || (crtl->calls_eh_return \ |
3553b09d | 1742 | && TARGET_AIX \ |
ff3867ae | 1743 | && (REGNO) == 2)) |
2bfcf297 | 1744 | |
f045b2c9 | 1745 | \f |
f045b2c9 RS |
1746 | /* Length in units of the trampoline for entering a nested function. */ |
1747 | ||
b6c9286a | 1748 | #define TRAMPOLINE_SIZE rs6000_trampoline_size () |
f045b2c9 | 1749 | \f |
f33985c6 MS |
1750 | /* Definitions for __builtin_return_address and __builtin_frame_address. |
1751 | __builtin_return_address (0) should give link register (65), enable | |
82e41834 | 1752 | this. */ |
f33985c6 MS |
1753 | /* This should be uncommented, so that the link register is used, but |
1754 | currently this would result in unmatched insns and spilling fixed | |
1755 | registers so we'll leave it for another day. When these problems are | |
1756 | taken care of one additional fetch will be necessary in RETURN_ADDR_RTX. | |
1757 | (mrs) */ | |
1758 | /* #define RETURN_ADDR_IN_PREVIOUS_FRAME */ | |
f09d4c33 | 1759 | |
b6c9286a MM |
1760 | /* Number of bytes into the frame return addresses can be found. See |
1761 | rs6000_stack_info in rs6000.c for more information on how the different | |
1762 | abi's store the return address. */ | |
1763 | #define RETURN_ADDRESS_OFFSET \ | |
1764 | ((DEFAULT_ABI == ABI_AIX \ | |
50d440bc | 1765 | || DEFAULT_ABI == ABI_DARWIN) ? (TARGET_32BIT ? 8 : 16) : \ |
3b370352 | 1766 | (DEFAULT_ABI == ABI_V4) ? 4 : \ |
c4636dd1 | 1767 | (internal_error ("RETURN_ADDRESS_OFFSET not supported"), 0)) |
f09d4c33 | 1768 | |
f33985c6 MS |
1769 | /* The current return address is in link register (65). The return address |
1770 | of anything farther back is accessed normally at an offset of 8 from the | |
1771 | frame pointer. */ | |
71f123ca FS |
1772 | #define RETURN_ADDR_RTX(COUNT, FRAME) \ |
1773 | (rs6000_return_addr (COUNT, FRAME)) | |
1774 | ||
f33985c6 | 1775 | \f |
f045b2c9 RS |
1776 | /* Definitions for register eliminations. |
1777 | ||
1778 | We have two registers that can be eliminated on the RS/6000. First, the | |
1779 | frame pointer register can often be eliminated in favor of the stack | |
1780 | pointer register. Secondly, the argument pointer register can always be | |
642a35f1 JW |
1781 | eliminated; it is replaced with either the stack or frame pointer. |
1782 | ||
1783 | In addition, we use the elimination mechanism to see if r30 is needed | |
1784 | Initially we assume that it isn't. If it is, we spill it. This is done | |
1785 | by making it an eliminable register. We replace it with itself so that | |
1786 | if it isn't needed, then existing uses won't be modified. */ | |
f045b2c9 RS |
1787 | |
1788 | /* This is an array of structures. Each structure initializes one pair | |
1789 | of eliminable registers. The "from" register number is given first, | |
1790 | followed by "to". Eliminations of the same "from" register are listed | |
1791 | in order of preference. */ | |
7d5175e1 JJ |
1792 | #define ELIMINABLE_REGS \ |
1793 | {{ HARD_FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ | |
1794 | { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ | |
1795 | { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ | |
1796 | { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ | |
1797 | { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ | |
97b23853 | 1798 | { RS6000_PIC_OFFSET_TABLE_REGNUM, RS6000_PIC_OFFSET_TABLE_REGNUM } } |
f045b2c9 | 1799 | |
f045b2c9 RS |
1800 | /* Define the offset between two registers, one to be eliminated, and the other |
1801 | its replacement, at the start of a routine. */ | |
d1d0c603 JJ |
1802 | #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ |
1803 | ((OFFSET) = rs6000_initial_elimination_offset(FROM, TO)) | |
f045b2c9 RS |
1804 | \f |
1805 | /* Addressing modes, and classification of registers for them. */ | |
1806 | ||
940da324 JL |
1807 | #define HAVE_PRE_DECREMENT 1 |
1808 | #define HAVE_PRE_INCREMENT 1 | |
6fb5fa3c DB |
1809 | #define HAVE_PRE_MODIFY_DISP 1 |
1810 | #define HAVE_PRE_MODIFY_REG 1 | |
f045b2c9 RS |
1811 | |
1812 | /* Macros to check register numbers against specific register classes. */ | |
1813 | ||
1814 | /* These assume that REGNO is a hard or pseudo reg number. | |
1815 | They give nonzero only if REGNO is a hard reg of the suitable class | |
1816 | or a pseudo reg currently allocated to a suitable hard reg. | |
1817 | Since they use reg_renumber, they are safe only once reg_renumber | |
aeb9f7cf SB |
1818 | has been allocated, which happens in reginfo.c during register |
1819 | allocation. */ | |
f045b2c9 RS |
1820 | |
1821 | #define REGNO_OK_FOR_INDEX_P(REGNO) \ | |
1822 | ((REGNO) < FIRST_PSEUDO_REGISTER \ | |
1823 | ? (REGNO) <= 31 || (REGNO) == 67 \ | |
7d5175e1 | 1824 | || (REGNO) == FRAME_POINTER_REGNUM \ |
f045b2c9 | 1825 | : (reg_renumber[REGNO] >= 0 \ |
7d5175e1 JJ |
1826 | && (reg_renumber[REGNO] <= 31 || reg_renumber[REGNO] == 67 \ |
1827 | || reg_renumber[REGNO] == FRAME_POINTER_REGNUM))) | |
f045b2c9 RS |
1828 | |
1829 | #define REGNO_OK_FOR_BASE_P(REGNO) \ | |
1830 | ((REGNO) < FIRST_PSEUDO_REGISTER \ | |
1831 | ? ((REGNO) > 0 && (REGNO) <= 31) || (REGNO) == 67 \ | |
7d5175e1 | 1832 | || (REGNO) == FRAME_POINTER_REGNUM \ |
f045b2c9 | 1833 | : (reg_renumber[REGNO] > 0 \ |
7d5175e1 JJ |
1834 | && (reg_renumber[REGNO] <= 31 || reg_renumber[REGNO] == 67 \ |
1835 | || reg_renumber[REGNO] == FRAME_POINTER_REGNUM))) | |
c6c3dba9 PB |
1836 | |
1837 | /* Nonzero if X is a hard reg that can be used as an index | |
1838 | or if it is a pseudo reg in the non-strict case. */ | |
1839 | #define INT_REG_OK_FOR_INDEX_P(X, STRICT) \ | |
1840 | ((!(STRICT) && REGNO (X) >= FIRST_PSEUDO_REGISTER) \ | |
1841 | || REGNO_OK_FOR_INDEX_P (REGNO (X))) | |
1842 | ||
1843 | /* Nonzero if X is a hard reg that can be used as a base reg | |
1844 | or if it is a pseudo reg in the non-strict case. */ | |
1845 | #define INT_REG_OK_FOR_BASE_P(X, STRICT) \ | |
1846 | ((!(STRICT) && REGNO (X) >= FIRST_PSEUDO_REGISTER) \ | |
1847 | || REGNO_OK_FOR_BASE_P (REGNO (X))) | |
1848 | ||
f045b2c9 RS |
1849 | \f |
1850 | /* Maximum number of registers that can appear in a valid memory address. */ | |
1851 | ||
1852 | #define MAX_REGS_PER_ADDRESS 2 | |
1853 | ||
1854 | /* Recognize any constant value that is a valid address. */ | |
1855 | ||
6eff269e BK |
1856 | #define CONSTANT_ADDRESS_P(X) \ |
1857 | (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \ | |
1858 | || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \ | |
1859 | || GET_CODE (X) == HIGH) | |
f045b2c9 | 1860 | |
48d72335 | 1861 | #define EASY_VECTOR_15(n) ((n) >= -16 && (n) <= 15) |
66180ff3 | 1862 | #define EASY_VECTOR_15_ADD_SELF(n) (!EASY_VECTOR_15((n)) \ |
76492753 PB |
1863 | && EASY_VECTOR_15((n) >> 1) \ |
1864 | && ((n) & 1) == 0) | |
48d72335 | 1865 | |
29e6733c MM |
1866 | #define EASY_VECTOR_MSB(n,mode) \ |
1867 | (((unsigned HOST_WIDE_INT)n) == \ | |
1868 | ((((unsigned HOST_WIDE_INT)GET_MODE_MASK (mode)) + 1) >> 1)) | |
1869 | ||
f045b2c9 | 1870 | \f |
a260abc9 DE |
1871 | /* Try a machine-dependent way of reloading an illegitimate address |
1872 | operand. If we find one, push the reload and jump to WIN. This | |
1873 | macro is used in only one place: `find_reloads_address' in reload.c. | |
1874 | ||
f676971a | 1875 | Implemented on rs6000 by rs6000_legitimize_reload_address. |
24ea750e | 1876 | Note that (X) is evaluated twice; this is safe in current usage. */ |
f676971a | 1877 | |
a9098fd0 GK |
1878 | #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \ |
1879 | do { \ | |
24ea750e | 1880 | int win; \ |
8beb65e3 | 1881 | (X) = rs6000_legitimize_reload_address_ptr ((X), (MODE), (OPNUM), \ |
24ea750e DJ |
1882 | (int)(TYPE), (IND_LEVELS), &win); \ |
1883 | if ( win ) \ | |
1884 | goto WIN; \ | |
a260abc9 DE |
1885 | } while (0) |
1886 | ||
944258eb | 1887 | #define FIND_BASE_TERM rs6000_find_base_term |
766a866c MM |
1888 | \f |
1889 | /* The register number of the register used to address a table of | |
1890 | static data addresses in memory. In some cases this register is | |
1891 | defined by a processor's "application binary interface" (ABI). | |
1892 | When this macro is defined, RTL is generated for this register | |
1893 | once, as with the stack pointer and frame pointer registers. If | |
1894 | this macro is not defined, it is up to the machine-dependent files | |
1895 | to allocate such a register (if necessary). */ | |
1896 | ||
1db02437 FS |
1897 | #define RS6000_PIC_OFFSET_TABLE_REGNUM 30 |
1898 | #define PIC_OFFSET_TABLE_REGNUM (flag_pic ? RS6000_PIC_OFFSET_TABLE_REGNUM : INVALID_REGNUM) | |
766a866c | 1899 | |
97b23853 | 1900 | #define TOC_REGISTER (TARGET_MINIMAL_TOC ? RS6000_PIC_OFFSET_TABLE_REGNUM : 2) |
9ebbca7d | 1901 | |
766a866c MM |
1902 | /* Define this macro if the register defined by |
1903 | `PIC_OFFSET_TABLE_REGNUM' is clobbered by calls. Do not define | |
089a05b8 | 1904 | this macro if `PIC_OFFSET_TABLE_REGNUM' is not defined. */ |
766a866c MM |
1905 | |
1906 | /* #define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED */ | |
1907 | ||
766a866c MM |
1908 | /* A C expression that is nonzero if X is a legitimate immediate |
1909 | operand on the target machine when generating position independent | |
1910 | code. You can assume that X satisfies `CONSTANT_P', so you need | |
1911 | not check this. You can also assume FLAG_PIC is true, so you need | |
1912 | not check it either. You need not define this macro if all | |
1913 | constants (including `SYMBOL_REF') can be immediate operands when | |
1914 | generating position independent code. */ | |
1915 | ||
1916 | /* #define LEGITIMATE_PIC_OPERAND_P (X) */ | |
f045b2c9 RS |
1917 | \f |
1918 | /* Define this if some processing needs to be done immediately before | |
4255474b | 1919 | emitting code for an insn. */ |
f045b2c9 | 1920 | |
c921bad8 AP |
1921 | #define FINAL_PRESCAN_INSN(INSN,OPERANDS,NOPERANDS) \ |
1922 | rs6000_final_prescan_insn (INSN, OPERANDS, NOPERANDS) | |
f045b2c9 RS |
1923 | |
1924 | /* Specify the machine mode that this machine uses | |
1925 | for the index in the tablejump instruction. */ | |
e1565e65 | 1926 | #define CASE_VECTOR_MODE SImode |
f045b2c9 | 1927 | |
18543a22 ILT |
1928 | /* Define as C expression which evaluates to nonzero if the tablejump |
1929 | instruction expects the table to contain offsets from the address of the | |
1930 | table. | |
82e41834 | 1931 | Do not define this if the table should contain absolute addresses. */ |
18543a22 | 1932 | #define CASE_VECTOR_PC_RELATIVE 1 |
f045b2c9 | 1933 | |
f045b2c9 RS |
1934 | /* Define this as 1 if `char' should by default be signed; else as 0. */ |
1935 | #define DEFAULT_SIGNED_CHAR 0 | |
1936 | ||
c1618c0c DE |
1937 | /* An integer expression for the size in bits of the largest integer machine |
1938 | mode that should actually be used. */ | |
1939 | ||
1940 | /* Allow pairs of registers to be used, which is the intent of the default. */ | |
1941 | #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TARGET_POWERPC64 ? TImode : DImode) | |
1942 | ||
f045b2c9 RS |
1943 | /* Max number of bytes we can move from memory to memory |
1944 | in one reasonably fast instruction. */ | |
2f3e5814 | 1945 | #define MOVE_MAX (! TARGET_POWERPC64 ? 4 : 8) |
7e69e155 | 1946 | #define MAX_MOVE_MAX 8 |
f045b2c9 RS |
1947 | |
1948 | /* Nonzero if access to memory by bytes is no faster than for words. | |
a0ab749a | 1949 | Also nonzero if doing byte operations (specifically shifts) in registers |
f045b2c9 RS |
1950 | is undesirable. */ |
1951 | #define SLOW_BYTE_ACCESS 1 | |
1952 | ||
9a63901f RK |
1953 | /* Define if operations between registers always perform the operation |
1954 | on the full register even if a narrower mode is specified. */ | |
1955 | #define WORD_REGISTER_OPERATIONS | |
1956 | ||
1957 | /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD | |
1958 | will either zero-extend or sign-extend. The value of this macro should | |
1959 | be the code that says which one of the two operations is implicitly | |
f822d252 | 1960 | done, UNKNOWN if none. */ |
9a63901f | 1961 | #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND |
225211e2 RK |
1962 | |
1963 | /* Define if loading short immediate values into registers sign extends. */ | |
1964 | #define SHORT_IMMEDIATES_SIGN_EXTEND | |
fdaff8ba | 1965 | \f |
f045b2c9 RS |
1966 | /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits |
1967 | is done just by pretending it is already truncated. */ | |
1968 | #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 | |
1969 | ||
94993909 | 1970 | /* The cntlzw and cntlzd instructions return 32 and 64 for input of zero. */ |
d865b122 | 1971 | #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \ |
14670a74 | 1972 | ((VALUE) = ((MODE) == SImode ? 32 : 64), 1) |
d865b122 | 1973 | |
94993909 | 1974 | /* The CTZ patterns return -1 for input of zero. */ |
14670a74 | 1975 | #define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = -1, 1) |
94993909 | 1976 | |
f045b2c9 RS |
1977 | /* Specify the machine mode that pointers have. |
1978 | After generation of rtl, the compiler makes no further distinction | |
1979 | between pointers and any other objects of this machine mode. */ | |
cacf1ca8 MM |
1980 | extern unsigned rs6000_pmode; |
1981 | #define Pmode ((enum machine_mode)rs6000_pmode) | |
f045b2c9 | 1982 | |
a3c9585f | 1983 | /* Supply definition of STACK_SIZE_MODE for allocate_dynamic_stack_space. */ |
4c81e946 FJ |
1984 | #define STACK_SIZE_MODE (TARGET_32BIT ? SImode : DImode) |
1985 | ||
f045b2c9 | 1986 | /* Mode of a function address in a call instruction (for indexing purposes). |
f045b2c9 | 1987 | Doesn't matter on RS/6000. */ |
5b71a4e7 | 1988 | #define FUNCTION_MODE SImode |
f045b2c9 RS |
1989 | |
1990 | /* Define this if addresses of constant functions | |
1991 | shouldn't be put through pseudo regs where they can be cse'd. | |
1992 | Desirable on machines where ordinary constants are expensive | |
1993 | but a CALL with constant address is cheap. */ | |
1994 | #define NO_FUNCTION_CSE | |
1995 | ||
d969caf8 | 1996 | /* Define this to be nonzero if shift instructions ignore all but the low-order |
6febd581 RK |
1997 | few bits. |
1998 | ||
1999 | The sle and sre instructions which allow SHIFT_COUNT_TRUNCATED | |
2000 | have been dropped from the PowerPC architecture. */ | |
c28a7c24 | 2001 | #define SHIFT_COUNT_TRUNCATED 0 |
f045b2c9 | 2002 | |
f045b2c9 RS |
2003 | /* Adjust the length of an INSN. LENGTH is the currently-computed length and |
2004 | should be adjusted to reflect any required changes. This macro is used when | |
2005 | there is some systematic length adjustment required that would be difficult | |
2006 | to express in the length attribute. */ | |
2007 | ||
2008 | /* #define ADJUST_INSN_LENGTH(X,LENGTH) */ | |
2009 | ||
39a10a29 GK |
2010 | /* Given a comparison code (EQ, NE, etc.) and the first operand of a |
2011 | COMPARE, return the mode to be used for the comparison. For | |
2012 | floating-point, CCFPmode should be used. CCUNSmode should be used | |
2013 | for unsigned comparisons. CCEQmode should be used when we are | |
2014 | doing an inequality comparison on the result of a | |
2015 | comparison. CCmode should be used in all other cases. */ | |
c5defebb | 2016 | |
b565a316 | 2017 | #define SELECT_CC_MODE(OP,X,Y) \ |
ebb109ad | 2018 | (SCALAR_FLOAT_MODE_P (GET_MODE (X)) ? CCFPmode \ |
c5defebb | 2019 | : (OP) == GTU || (OP) == LTU || (OP) == GEU || (OP) == LEU ? CCUNSmode \ |
ec8e098d | 2020 | : (((OP) == EQ || (OP) == NE) && COMPARISON_P (X) \ |
c5defebb | 2021 | ? CCEQmode : CCmode)) |
f045b2c9 | 2022 | |
b39358e1 GK |
2023 | /* Can the condition code MODE be safely reversed? This is safe in |
2024 | all cases on this port, because at present it doesn't use the | |
2025 | trapping FP comparisons (fcmpo). */ | |
2026 | #define REVERSIBLE_CC_MODE(MODE) 1 | |
2027 | ||
2028 | /* Given a condition code and a mode, return the inverse condition. */ | |
2029 | #define REVERSE_CONDITION(CODE, MODE) rs6000_reverse_condition (MODE, CODE) | |
2030 | ||
f045b2c9 RS |
2031 | \f |
2032 | /* Control the assembler format that we output. */ | |
2033 | ||
1b279f39 DE |
2034 | /* A C string constant describing how to begin a comment in the target |
2035 | assembler language. The compiler assumes that the comment will end at | |
2036 | the end of the line. */ | |
2037 | #define ASM_COMMENT_START " #" | |
6b67933e | 2038 | |
38c1f2d7 MM |
2039 | /* Flag to say the TOC is initialized */ |
2040 | extern int toc_initialized; | |
2041 | ||
f045b2c9 RS |
2042 | /* Macro to output a special constant pool entry. Go to WIN if we output |
2043 | it. Otherwise, it is written the usual way. | |
2044 | ||
2045 | On the RS/6000, toc entries are handled this way. */ | |
2046 | ||
a9098fd0 GK |
2047 | #define ASM_OUTPUT_SPECIAL_POOL_ENTRY(FILE, X, MODE, ALIGN, LABELNO, WIN) \ |
2048 | { if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (X, MODE)) \ | |
2049 | { \ | |
2050 | output_toc (FILE, X, LABELNO, MODE); \ | |
2051 | goto WIN; \ | |
2052 | } \ | |
f045b2c9 RS |
2053 | } |
2054 | ||
ebd97b96 DE |
2055 | #ifdef HAVE_GAS_WEAK |
2056 | #define RS6000_WEAK 1 | |
2057 | #else | |
2058 | #define RS6000_WEAK 0 | |
2059 | #endif | |
290ad355 | 2060 | |
79c4e63f AM |
2061 | #if RS6000_WEAK |
2062 | /* Used in lieu of ASM_WEAKEN_LABEL. */ | |
2063 | #define ASM_WEAKEN_DECL(FILE, DECL, NAME, VAL) \ | |
2064 | do \ | |
2065 | { \ | |
2066 | fputs ("\t.weak\t", (FILE)); \ | |
85b776df | 2067 | RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \ |
79c4e63f | 2068 | if ((DECL) && TREE_CODE (DECL) == FUNCTION_DECL \ |
85b776df | 2069 | && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS) \ |
79c4e63f | 2070 | { \ |
cbaaba19 DE |
2071 | if (TARGET_XCOFF) \ |
2072 | fputs ("[DS]", (FILE)); \ | |
ca734b39 | 2073 | fputs ("\n\t.weak\t.", (FILE)); \ |
cbaaba19 | 2074 | RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \ |
79c4e63f AM |
2075 | } \ |
2076 | fputc ('\n', (FILE)); \ | |
2077 | if (VAL) \ | |
2078 | { \ | |
2079 | ASM_OUTPUT_DEF ((FILE), (NAME), (VAL)); \ | |
2080 | if ((DECL) && TREE_CODE (DECL) == FUNCTION_DECL \ | |
85b776df | 2081 | && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS) \ |
79c4e63f AM |
2082 | { \ |
2083 | fputs ("\t.set\t.", (FILE)); \ | |
cbaaba19 | 2084 | RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \ |
79c4e63f | 2085 | fputs (",.", (FILE)); \ |
cbaaba19 | 2086 | RS6000_OUTPUT_BASENAME ((FILE), (VAL)); \ |
79c4e63f AM |
2087 | fputc ('\n', (FILE)); \ |
2088 | } \ | |
2089 | } \ | |
2090 | } \ | |
2091 | while (0) | |
2092 | #endif | |
2093 | ||
ff2d10c1 AO |
2094 | #if HAVE_GAS_WEAKREF |
2095 | #define ASM_OUTPUT_WEAKREF(FILE, DECL, NAME, VALUE) \ | |
2096 | do \ | |
2097 | { \ | |
2098 | fputs ("\t.weakref\t", (FILE)); \ | |
2099 | RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \ | |
2100 | fputs (", ", (FILE)); \ | |
2101 | RS6000_OUTPUT_BASENAME ((FILE), (VALUE)); \ | |
2102 | if ((DECL) && TREE_CODE (DECL) == FUNCTION_DECL \ | |
2103 | && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS) \ | |
2104 | { \ | |
2105 | fputs ("\n\t.weakref\t.", (FILE)); \ | |
2106 | RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \ | |
2107 | fputs (", .", (FILE)); \ | |
2108 | RS6000_OUTPUT_BASENAME ((FILE), (VALUE)); \ | |
2109 | } \ | |
2110 | fputc ('\n', (FILE)); \ | |
2111 | } while (0) | |
2112 | #endif | |
2113 | ||
79c4e63f AM |
2114 | /* This implements the `alias' attribute. */ |
2115 | #undef ASM_OUTPUT_DEF_FROM_DECLS | |
2116 | #define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL, TARGET) \ | |
2117 | do \ | |
2118 | { \ | |
2119 | const char *alias = XSTR (XEXP (DECL_RTL (DECL), 0), 0); \ | |
2120 | const char *name = IDENTIFIER_POINTER (TARGET); \ | |
2121 | if (TREE_CODE (DECL) == FUNCTION_DECL \ | |
85b776df | 2122 | && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS) \ |
79c4e63f AM |
2123 | { \ |
2124 | if (TREE_PUBLIC (DECL)) \ | |
2125 | { \ | |
2126 | if (!RS6000_WEAK || !DECL_WEAK (DECL)) \ | |
2127 | { \ | |
2128 | fputs ("\t.globl\t.", FILE); \ | |
cbaaba19 | 2129 | RS6000_OUTPUT_BASENAME (FILE, alias); \ |
79c4e63f AM |
2130 | putc ('\n', FILE); \ |
2131 | } \ | |
2132 | } \ | |
2133 | else if (TARGET_XCOFF) \ | |
2134 | { \ | |
2135 | fputs ("\t.lglobl\t.", FILE); \ | |
cbaaba19 | 2136 | RS6000_OUTPUT_BASENAME (FILE, alias); \ |
79c4e63f AM |
2137 | putc ('\n', FILE); \ |
2138 | } \ | |
2139 | fputs ("\t.set\t.", FILE); \ | |
cbaaba19 | 2140 | RS6000_OUTPUT_BASENAME (FILE, alias); \ |
79c4e63f | 2141 | fputs (",.", FILE); \ |
cbaaba19 | 2142 | RS6000_OUTPUT_BASENAME (FILE, name); \ |
79c4e63f AM |
2143 | fputc ('\n', FILE); \ |
2144 | } \ | |
2145 | ASM_OUTPUT_DEF (FILE, alias, name); \ | |
2146 | } \ | |
2147 | while (0) | |
290ad355 | 2148 | |
1bc7c5b6 ZW |
2149 | #define TARGET_ASM_FILE_START rs6000_file_start |
2150 | ||
f045b2c9 RS |
2151 | /* Output to assembler file text saying following lines |
2152 | may contain character constants, extra white space, comments, etc. */ | |
2153 | ||
2154 | #define ASM_APP_ON "" | |
2155 | ||
2156 | /* Output to assembler file text saying following lines | |
2157 | no longer contain unusual constructs. */ | |
2158 | ||
2159 | #define ASM_APP_OFF "" | |
2160 | ||
f045b2c9 RS |
2161 | /* How to refer to registers in assembler output. |
2162 | This sequence is indexed by compiler's hard-register-number (see above). */ | |
2163 | ||
82e41834 | 2164 | extern char rs6000_reg_names[][8]; /* register names (0 vs. %r0). */ |
c81bebd7 MM |
2165 | |
2166 | #define REGISTER_NAMES \ | |
2167 | { \ | |
2168 | &rs6000_reg_names[ 0][0], /* r0 */ \ | |
2169 | &rs6000_reg_names[ 1][0], /* r1 */ \ | |
2170 | &rs6000_reg_names[ 2][0], /* r2 */ \ | |
2171 | &rs6000_reg_names[ 3][0], /* r3 */ \ | |
2172 | &rs6000_reg_names[ 4][0], /* r4 */ \ | |
2173 | &rs6000_reg_names[ 5][0], /* r5 */ \ | |
2174 | &rs6000_reg_names[ 6][0], /* r6 */ \ | |
2175 | &rs6000_reg_names[ 7][0], /* r7 */ \ | |
2176 | &rs6000_reg_names[ 8][0], /* r8 */ \ | |
2177 | &rs6000_reg_names[ 9][0], /* r9 */ \ | |
2178 | &rs6000_reg_names[10][0], /* r10 */ \ | |
2179 | &rs6000_reg_names[11][0], /* r11 */ \ | |
2180 | &rs6000_reg_names[12][0], /* r12 */ \ | |
2181 | &rs6000_reg_names[13][0], /* r13 */ \ | |
2182 | &rs6000_reg_names[14][0], /* r14 */ \ | |
2183 | &rs6000_reg_names[15][0], /* r15 */ \ | |
2184 | &rs6000_reg_names[16][0], /* r16 */ \ | |
2185 | &rs6000_reg_names[17][0], /* r17 */ \ | |
2186 | &rs6000_reg_names[18][0], /* r18 */ \ | |
2187 | &rs6000_reg_names[19][0], /* r19 */ \ | |
2188 | &rs6000_reg_names[20][0], /* r20 */ \ | |
2189 | &rs6000_reg_names[21][0], /* r21 */ \ | |
2190 | &rs6000_reg_names[22][0], /* r22 */ \ | |
2191 | &rs6000_reg_names[23][0], /* r23 */ \ | |
2192 | &rs6000_reg_names[24][0], /* r24 */ \ | |
2193 | &rs6000_reg_names[25][0], /* r25 */ \ | |
2194 | &rs6000_reg_names[26][0], /* r26 */ \ | |
2195 | &rs6000_reg_names[27][0], /* r27 */ \ | |
2196 | &rs6000_reg_names[28][0], /* r28 */ \ | |
2197 | &rs6000_reg_names[29][0], /* r29 */ \ | |
2198 | &rs6000_reg_names[30][0], /* r30 */ \ | |
2199 | &rs6000_reg_names[31][0], /* r31 */ \ | |
2200 | \ | |
2201 | &rs6000_reg_names[32][0], /* fr0 */ \ | |
2202 | &rs6000_reg_names[33][0], /* fr1 */ \ | |
2203 | &rs6000_reg_names[34][0], /* fr2 */ \ | |
2204 | &rs6000_reg_names[35][0], /* fr3 */ \ | |
2205 | &rs6000_reg_names[36][0], /* fr4 */ \ | |
2206 | &rs6000_reg_names[37][0], /* fr5 */ \ | |
2207 | &rs6000_reg_names[38][0], /* fr6 */ \ | |
2208 | &rs6000_reg_names[39][0], /* fr7 */ \ | |
2209 | &rs6000_reg_names[40][0], /* fr8 */ \ | |
2210 | &rs6000_reg_names[41][0], /* fr9 */ \ | |
2211 | &rs6000_reg_names[42][0], /* fr10 */ \ | |
2212 | &rs6000_reg_names[43][0], /* fr11 */ \ | |
2213 | &rs6000_reg_names[44][0], /* fr12 */ \ | |
2214 | &rs6000_reg_names[45][0], /* fr13 */ \ | |
2215 | &rs6000_reg_names[46][0], /* fr14 */ \ | |
2216 | &rs6000_reg_names[47][0], /* fr15 */ \ | |
2217 | &rs6000_reg_names[48][0], /* fr16 */ \ | |
2218 | &rs6000_reg_names[49][0], /* fr17 */ \ | |
2219 | &rs6000_reg_names[50][0], /* fr18 */ \ | |
2220 | &rs6000_reg_names[51][0], /* fr19 */ \ | |
2221 | &rs6000_reg_names[52][0], /* fr20 */ \ | |
2222 | &rs6000_reg_names[53][0], /* fr21 */ \ | |
2223 | &rs6000_reg_names[54][0], /* fr22 */ \ | |
2224 | &rs6000_reg_names[55][0], /* fr23 */ \ | |
2225 | &rs6000_reg_names[56][0], /* fr24 */ \ | |
2226 | &rs6000_reg_names[57][0], /* fr25 */ \ | |
2227 | &rs6000_reg_names[58][0], /* fr26 */ \ | |
2228 | &rs6000_reg_names[59][0], /* fr27 */ \ | |
2229 | &rs6000_reg_names[60][0], /* fr28 */ \ | |
2230 | &rs6000_reg_names[61][0], /* fr29 */ \ | |
2231 | &rs6000_reg_names[62][0], /* fr30 */ \ | |
2232 | &rs6000_reg_names[63][0], /* fr31 */ \ | |
2233 | \ | |
462f7901 | 2234 | &rs6000_reg_names[64][0], /* was mq */ \ |
c81bebd7 MM |
2235 | &rs6000_reg_names[65][0], /* lr */ \ |
2236 | &rs6000_reg_names[66][0], /* ctr */ \ | |
2237 | &rs6000_reg_names[67][0], /* ap */ \ | |
2238 | \ | |
2239 | &rs6000_reg_names[68][0], /* cr0 */ \ | |
2240 | &rs6000_reg_names[69][0], /* cr1 */ \ | |
2241 | &rs6000_reg_names[70][0], /* cr2 */ \ | |
2242 | &rs6000_reg_names[71][0], /* cr3 */ \ | |
2243 | &rs6000_reg_names[72][0], /* cr4 */ \ | |
2244 | &rs6000_reg_names[73][0], /* cr5 */ \ | |
2245 | &rs6000_reg_names[74][0], /* cr6 */ \ | |
2246 | &rs6000_reg_names[75][0], /* cr7 */ \ | |
802a0058 | 2247 | \ |
f6b5d695 | 2248 | &rs6000_reg_names[76][0], /* ca */ \ |
0ac081f6 AH |
2249 | \ |
2250 | &rs6000_reg_names[77][0], /* v0 */ \ | |
2251 | &rs6000_reg_names[78][0], /* v1 */ \ | |
2252 | &rs6000_reg_names[79][0], /* v2 */ \ | |
2253 | &rs6000_reg_names[80][0], /* v3 */ \ | |
2254 | &rs6000_reg_names[81][0], /* v4 */ \ | |
2255 | &rs6000_reg_names[82][0], /* v5 */ \ | |
2256 | &rs6000_reg_names[83][0], /* v6 */ \ | |
2257 | &rs6000_reg_names[84][0], /* v7 */ \ | |
2258 | &rs6000_reg_names[85][0], /* v8 */ \ | |
2259 | &rs6000_reg_names[86][0], /* v9 */ \ | |
2260 | &rs6000_reg_names[87][0], /* v10 */ \ | |
2261 | &rs6000_reg_names[88][0], /* v11 */ \ | |
2262 | &rs6000_reg_names[89][0], /* v12 */ \ | |
2263 | &rs6000_reg_names[90][0], /* v13 */ \ | |
2264 | &rs6000_reg_names[91][0], /* v14 */ \ | |
2265 | &rs6000_reg_names[92][0], /* v15 */ \ | |
2266 | &rs6000_reg_names[93][0], /* v16 */ \ | |
2267 | &rs6000_reg_names[94][0], /* v17 */ \ | |
2268 | &rs6000_reg_names[95][0], /* v18 */ \ | |
2269 | &rs6000_reg_names[96][0], /* v19 */ \ | |
2270 | &rs6000_reg_names[97][0], /* v20 */ \ | |
2271 | &rs6000_reg_names[98][0], /* v21 */ \ | |
2272 | &rs6000_reg_names[99][0], /* v22 */ \ | |
2273 | &rs6000_reg_names[100][0], /* v23 */ \ | |
2274 | &rs6000_reg_names[101][0], /* v24 */ \ | |
2275 | &rs6000_reg_names[102][0], /* v25 */ \ | |
2276 | &rs6000_reg_names[103][0], /* v26 */ \ | |
2277 | &rs6000_reg_names[104][0], /* v27 */ \ | |
2278 | &rs6000_reg_names[105][0], /* v28 */ \ | |
2279 | &rs6000_reg_names[106][0], /* v29 */ \ | |
2280 | &rs6000_reg_names[107][0], /* v30 */ \ | |
2281 | &rs6000_reg_names[108][0], /* v31 */ \ | |
2282 | &rs6000_reg_names[109][0], /* vrsave */ \ | |
5f004351 | 2283 | &rs6000_reg_names[110][0], /* vscr */ \ |
a3170dc6 AH |
2284 | &rs6000_reg_names[111][0], /* spe_acc */ \ |
2285 | &rs6000_reg_names[112][0], /* spefscr */ \ | |
7d5175e1 | 2286 | &rs6000_reg_names[113][0], /* sfp */ \ |
c81bebd7 MM |
2287 | } |
2288 | ||
f045b2c9 RS |
2289 | /* Table of additional register names to use in user input. */ |
2290 | ||
2291 | #define ADDITIONAL_REGISTER_NAMES \ | |
c4d38ccb MM |
2292 | {{"r0", 0}, {"r1", 1}, {"r2", 2}, {"r3", 3}, \ |
2293 | {"r4", 4}, {"r5", 5}, {"r6", 6}, {"r7", 7}, \ | |
2294 | {"r8", 8}, {"r9", 9}, {"r10", 10}, {"r11", 11}, \ | |
2295 | {"r12", 12}, {"r13", 13}, {"r14", 14}, {"r15", 15}, \ | |
2296 | {"r16", 16}, {"r17", 17}, {"r18", 18}, {"r19", 19}, \ | |
2297 | {"r20", 20}, {"r21", 21}, {"r22", 22}, {"r23", 23}, \ | |
2298 | {"r24", 24}, {"r25", 25}, {"r26", 26}, {"r27", 27}, \ | |
2299 | {"r28", 28}, {"r29", 29}, {"r30", 30}, {"r31", 31}, \ | |
2300 | {"fr0", 32}, {"fr1", 33}, {"fr2", 34}, {"fr3", 35}, \ | |
2301 | {"fr4", 36}, {"fr5", 37}, {"fr6", 38}, {"fr7", 39}, \ | |
2302 | {"fr8", 40}, {"fr9", 41}, {"fr10", 42}, {"fr11", 43}, \ | |
2303 | {"fr12", 44}, {"fr13", 45}, {"fr14", 46}, {"fr15", 47}, \ | |
2304 | {"fr16", 48}, {"fr17", 49}, {"fr18", 50}, {"fr19", 51}, \ | |
2305 | {"fr20", 52}, {"fr21", 53}, {"fr22", 54}, {"fr23", 55}, \ | |
2306 | {"fr24", 56}, {"fr25", 57}, {"fr26", 58}, {"fr27", 59}, \ | |
2307 | {"fr28", 60}, {"fr29", 61}, {"fr30", 62}, {"fr31", 63}, \ | |
0ac081f6 AH |
2308 | {"v0", 77}, {"v1", 78}, {"v2", 79}, {"v3", 80}, \ |
2309 | {"v4", 81}, {"v5", 82}, {"v6", 83}, {"v7", 84}, \ | |
2310 | {"v8", 85}, {"v9", 86}, {"v10", 87}, {"v11", 88}, \ | |
2311 | {"v12", 89}, {"v13", 90}, {"v14", 91}, {"v15", 92}, \ | |
2312 | {"v16", 93}, {"v17", 94}, {"v18", 95}, {"v19", 96}, \ | |
2313 | {"v20", 97}, {"v21", 98}, {"v22", 99}, {"v23", 100}, \ | |
2314 | {"v24", 101},{"v25", 102},{"v26", 103},{"v27", 104}, \ | |
2315 | {"v28", 105},{"v29", 106},{"v30", 107},{"v31", 108}, \ | |
5f004351 | 2316 | {"vrsave", 109}, {"vscr", 110}, \ |
a3170dc6 | 2317 | {"spe_acc", 111}, {"spefscr", 112}, \ |
462f7901 | 2318 | /* no additional names for: lr, ctr, ap */ \ |
c4d38ccb MM |
2319 | {"cr0", 68}, {"cr1", 69}, {"cr2", 70}, {"cr3", 71}, \ |
2320 | {"cr4", 72}, {"cr5", 73}, {"cr6", 74}, {"cr7", 75}, \ | |
cacf1ca8 | 2321 | {"cc", 68}, {"sp", 1}, {"toc", 2}, \ |
f6b5d695 SB |
2322 | /* CA is only part of XER, but we do not model the other parts (yet). */ \ |
2323 | {"xer", 76}, \ | |
cacf1ca8 MM |
2324 | /* VSX registers overlaid on top of FR, Altivec registers */ \ |
2325 | {"vs0", 32}, {"vs1", 33}, {"vs2", 34}, {"vs3", 35}, \ | |
2326 | {"vs4", 36}, {"vs5", 37}, {"vs6", 38}, {"vs7", 39}, \ | |
2327 | {"vs8", 40}, {"vs9", 41}, {"vs10", 42}, {"vs11", 43}, \ | |
2328 | {"vs12", 44}, {"vs13", 45}, {"vs14", 46}, {"vs15", 47}, \ | |
2329 | {"vs16", 48}, {"vs17", 49}, {"vs18", 50}, {"vs19", 51}, \ | |
2330 | {"vs20", 52}, {"vs21", 53}, {"vs22", 54}, {"vs23", 55}, \ | |
2331 | {"vs24", 56}, {"vs25", 57}, {"vs26", 58}, {"vs27", 59}, \ | |
2332 | {"vs28", 60}, {"vs29", 61}, {"vs30", 62}, {"vs31", 63}, \ | |
2333 | {"vs32", 77}, {"vs33", 78}, {"vs34", 79}, {"vs35", 80}, \ | |
2334 | {"vs36", 81}, {"vs37", 82}, {"vs38", 83}, {"vs39", 84}, \ | |
2335 | {"vs40", 85}, {"vs41", 86}, {"vs42", 87}, {"vs43", 88}, \ | |
2336 | {"vs44", 89}, {"vs45", 90}, {"vs46", 91}, {"vs47", 92}, \ | |
2337 | {"vs48", 93}, {"vs49", 94}, {"vs50", 95}, {"vs51", 96}, \ | |
2338 | {"vs52", 97}, {"vs53", 98}, {"vs54", 99}, {"vs55", 100}, \ | |
2339 | {"vs56", 101},{"vs57", 102},{"vs58", 103},{"vs59", 104}, \ | |
2340 | {"vs60", 105},{"vs61", 106},{"vs62", 107},{"vs63", 108} } | |
f045b2c9 | 2341 | |
f045b2c9 RS |
2342 | /* This is how to output an element of a case-vector that is relative. */ |
2343 | ||
e1565e65 | 2344 | #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ |
3daf36a4 | 2345 | do { char buf[100]; \ |
e1565e65 | 2346 | fputs ("\t.long ", FILE); \ |
3daf36a4 ILT |
2347 | ASM_GENERATE_INTERNAL_LABEL (buf, "L", VALUE); \ |
2348 | assemble_name (FILE, buf); \ | |
19d2d16f | 2349 | putc ('-', FILE); \ |
3daf36a4 ILT |
2350 | ASM_GENERATE_INTERNAL_LABEL (buf, "L", REL); \ |
2351 | assemble_name (FILE, buf); \ | |
19d2d16f | 2352 | putc ('\n', FILE); \ |
3daf36a4 | 2353 | } while (0) |
f045b2c9 RS |
2354 | |
2355 | /* This is how to output an assembler line | |
2356 | that says to advance the location counter | |
2357 | to a multiple of 2**LOG bytes. */ | |
2358 | ||
2359 | #define ASM_OUTPUT_ALIGN(FILE,LOG) \ | |
2360 | if ((LOG) != 0) \ | |
2361 | fprintf (FILE, "\t.align %d\n", (LOG)) | |
2362 | ||
58082ff6 PH |
2363 | /* How to align the given loop. */ |
2364 | #define LOOP_ALIGN(LABEL) rs6000_loop_align(LABEL) | |
2365 | ||
d28073d4 BS |
2366 | /* Alignment guaranteed by __builtin_malloc. */ |
2367 | /* FIXME: 128-bit alignment is guaranteed by glibc for TARGET_64BIT. | |
2368 | However, specifying the stronger guarantee currently leads to | |
2369 | a regression in SPEC CPU2006 437.leslie3d. The stronger | |
2370 | guarantee should be implemented here once that's fixed. */ | |
2371 | #define MALLOC_ABI_ALIGNMENT (64) | |
2372 | ||
9ebbca7d GK |
2373 | /* Pick up the return address upon entry to a procedure. Used for |
2374 | dwarf2 unwind information. This also enables the table driven | |
2375 | mechanism. */ | |
2376 | ||
1de43f85 DE |
2377 | #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNO) |
2378 | #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNO) | |
9ebbca7d | 2379 | |
83720594 RH |
2380 | /* Describe how we implement __builtin_eh_return. */ |
2381 | #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 3 : INVALID_REGNUM) | |
2382 | #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 10) | |
2383 | ||
f045b2c9 RS |
2384 | /* Print operand X (an rtx) in assembler syntax to file FILE. |
2385 | CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. | |
2386 | For `%' followed by punctuation, CODE is the punctuation and X is null. */ | |
2387 | ||
2388 | #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE) | |
2389 | ||
2390 | /* Define which CODE values are valid. */ | |
2391 | ||
3cf437d4 | 2392 | #define PRINT_OPERAND_PUNCT_VALID_P(CODE) ((CODE) == '&') |
f045b2c9 RS |
2393 | |
2394 | /* Print a memory address as an operand to reference that memory location. */ | |
2395 | ||
2396 | #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR) | |
2397 | ||
b6c9286a MM |
2398 | /* uncomment for disabling the corresponding default options */ |
2399 | /* #define MACHINE_no_sched_interblock */ | |
2400 | /* #define MACHINE_no_sched_speculative */ | |
2401 | /* #define MACHINE_no_sched_speculative_load */ | |
2402 | ||
766a866c | 2403 | /* General flags. */ |
a7df97e6 | 2404 | extern int frame_pointer_needed; |
0ac081f6 | 2405 | |
7fa14a01 MM |
2406 | /* Classification of the builtin functions as to which switches enable the |
2407 | builtin, and what attributes it should have. We used to use the target | |
2408 | flags macros, but we've run out of bits, so we now map the options into new | |
2409 | settings used here. */ | |
2410 | ||
2411 | /* Builtin attributes. */ | |
2412 | #define RS6000_BTC_SPECIAL 0x00000000 /* Special function. */ | |
2413 | #define RS6000_BTC_UNARY 0x00000001 /* normal unary function. */ | |
2414 | #define RS6000_BTC_BINARY 0x00000002 /* normal binary function. */ | |
2415 | #define RS6000_BTC_TERNARY 0x00000003 /* normal ternary function. */ | |
2416 | #define RS6000_BTC_PREDICATE 0x00000004 /* predicate function. */ | |
2417 | #define RS6000_BTC_ABS 0x00000005 /* Altivec/VSX ABS function. */ | |
2418 | #define RS6000_BTC_EVSEL 0x00000006 /* SPE EVSEL function. */ | |
2419 | #define RS6000_BTC_DST 0x00000007 /* Altivec DST function. */ | |
2420 | #define RS6000_BTC_TYPE_MASK 0x0000000f /* Mask to isolate types */ | |
2421 | ||
2422 | #define RS6000_BTC_MISC 0x00000000 /* No special attributes. */ | |
2423 | #define RS6000_BTC_CONST 0x00000100 /* uses no global state. */ | |
2424 | #define RS6000_BTC_PURE 0x00000200 /* reads global state/mem. */ | |
2425 | #define RS6000_BTC_FP 0x00000400 /* depends on rounding mode. */ | |
2426 | #define RS6000_BTC_ATTR_MASK 0x00000700 /* Mask of the attributes. */ | |
2427 | ||
2428 | /* Miscellaneous information. */ | |
2429 | #define RS6000_BTC_OVERLOADED 0x4000000 /* function is overloaded. */ | |
1c9df37c MM |
2430 | |
2431 | /* Convenience macros to document the instruction type. */ | |
7fa14a01 MM |
2432 | #define RS6000_BTC_MEM RS6000_BTC_MISC /* load/store touches mem. */ |
2433 | #define RS6000_BTC_SAT RS6000_BTC_MISC /* saturate sets VSCR. */ | |
2434 | ||
2435 | /* Builtin targets. For now, we reuse the masks for those options that are in | |
2436 | target flags, and pick two random bits for SPE and paired which aren't in | |
2437 | target_flags. */ | |
4b705221 | 2438 | #define RS6000_BTM_ALWAYS 0 /* Always enabled. */ |
7fa14a01 MM |
2439 | #define RS6000_BTM_ALTIVEC MASK_ALTIVEC /* VMX/altivec vectors. */ |
2440 | #define RS6000_BTM_VSX MASK_VSX /* VSX (vector/scalar). */ | |
f62511da MM |
2441 | #define RS6000_BTM_P8_VECTOR MASK_P8_VECTOR /* ISA 2.07 vector. */ |
2442 | #define RS6000_BTM_CRYPTO MASK_CRYPTO /* crypto funcs. */ | |
7fa14a01 MM |
2443 | #define RS6000_BTM_SPE MASK_STRING /* E500 */ |
2444 | #define RS6000_BTM_PAIRED MASK_MULHW /* 750CL paired insns. */ | |
2445 | #define RS6000_BTM_FRE MASK_POPCNTB /* FRE instruction. */ | |
2446 | #define RS6000_BTM_FRES MASK_PPC_GFXOPT /* FRES instruction. */ | |
2447 | #define RS6000_BTM_FRSQRTE MASK_PPC_GFXOPT /* FRSQRTE instruction. */ | |
2448 | #define RS6000_BTM_FRSQRTES MASK_POPCNTB /* FRSQRTES instruction. */ | |
2449 | #define RS6000_BTM_POPCNTD MASK_POPCNTD /* Target supports ISA 2.06. */ | |
7fa14a01 MM |
2450 | #define RS6000_BTM_CELL MASK_FPRND /* Target is cell powerpc. */ |
2451 | ||
2452 | #define RS6000_BTM_COMMON (RS6000_BTM_ALTIVEC \ | |
2453 | | RS6000_BTM_VSX \ | |
f62511da MM |
2454 | | RS6000_BTM_P8_VECTOR \ |
2455 | | RS6000_BTM_CRYPTO \ | |
7fa14a01 MM |
2456 | | RS6000_BTM_FRE \ |
2457 | | RS6000_BTM_FRES \ | |
2458 | | RS6000_BTM_FRSQRTE \ | |
2459 | | RS6000_BTM_FRSQRTES \ | |
2460 | | RS6000_BTM_POPCNTD \ | |
7fa14a01 MM |
2461 | | RS6000_BTM_CELL) |
2462 | ||
2463 | /* Define builtin enum index. */ | |
2464 | ||
2465 | #undef RS6000_BUILTIN_1 | |
2466 | #undef RS6000_BUILTIN_2 | |
2467 | #undef RS6000_BUILTIN_3 | |
2468 | #undef RS6000_BUILTIN_A | |
2469 | #undef RS6000_BUILTIN_D | |
2470 | #undef RS6000_BUILTIN_E | |
2471 | #undef RS6000_BUILTIN_P | |
2472 | #undef RS6000_BUILTIN_Q | |
2473 | #undef RS6000_BUILTIN_S | |
2474 | #undef RS6000_BUILTIN_X | |
2475 | ||
2476 | #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE) ENUM, | |
2477 | #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE) ENUM, | |
2478 | #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE) ENUM, | |
2479 | #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) ENUM, | |
2480 | #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) ENUM, | |
2481 | #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE) ENUM, | |
2482 | #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) ENUM, | |
2483 | #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE) ENUM, | |
2484 | #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE) ENUM, | |
2485 | #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE) ENUM, | |
1c9df37c | 2486 | |
0ac081f6 AH |
2487 | enum rs6000_builtins |
2488 | { | |
1c9df37c | 2489 | #include "rs6000-builtin.def" |
a72c65c7 | 2490 | |
58646b77 PB |
2491 | RS6000_BUILTIN_COUNT |
2492 | }; | |
2493 | ||
7fa14a01 MM |
2494 | #undef RS6000_BUILTIN_1 |
2495 | #undef RS6000_BUILTIN_2 | |
2496 | #undef RS6000_BUILTIN_3 | |
2497 | #undef RS6000_BUILTIN_A | |
2498 | #undef RS6000_BUILTIN_D | |
2499 | #undef RS6000_BUILTIN_E | |
2500 | #undef RS6000_BUILTIN_P | |
2501 | #undef RS6000_BUILTIN_Q | |
2502 | #undef RS6000_BUILTIN_S | |
2503 | #undef RS6000_BUILTIN_X | |
1c9df37c | 2504 | |
58646b77 PB |
2505 | enum rs6000_builtin_type_index |
2506 | { | |
2507 | RS6000_BTI_NOT_OPAQUE, | |
2508 | RS6000_BTI_opaque_V2SI, | |
2509 | RS6000_BTI_opaque_V2SF, | |
2510 | RS6000_BTI_opaque_p_V2SI, | |
2511 | RS6000_BTI_opaque_V4SI, | |
2512 | RS6000_BTI_V16QI, | |
2513 | RS6000_BTI_V2SI, | |
2514 | RS6000_BTI_V2SF, | |
a72c65c7 MM |
2515 | RS6000_BTI_V2DI, |
2516 | RS6000_BTI_V2DF, | |
58646b77 PB |
2517 | RS6000_BTI_V4HI, |
2518 | RS6000_BTI_V4SI, | |
2519 | RS6000_BTI_V4SF, | |
2520 | RS6000_BTI_V8HI, | |
2521 | RS6000_BTI_unsigned_V16QI, | |
2522 | RS6000_BTI_unsigned_V8HI, | |
2523 | RS6000_BTI_unsigned_V4SI, | |
a72c65c7 | 2524 | RS6000_BTI_unsigned_V2DI, |
58646b77 PB |
2525 | RS6000_BTI_bool_char, /* __bool char */ |
2526 | RS6000_BTI_bool_short, /* __bool short */ | |
2527 | RS6000_BTI_bool_int, /* __bool int */ | |
a72c65c7 | 2528 | RS6000_BTI_bool_long, /* __bool long */ |
58646b77 PB |
2529 | RS6000_BTI_pixel, /* __pixel */ |
2530 | RS6000_BTI_bool_V16QI, /* __vector __bool char */ | |
2531 | RS6000_BTI_bool_V8HI, /* __vector __bool short */ | |
2532 | RS6000_BTI_bool_V4SI, /* __vector __bool int */ | |
a72c65c7 | 2533 | RS6000_BTI_bool_V2DI, /* __vector __bool long */ |
58646b77 PB |
2534 | RS6000_BTI_pixel_V8HI, /* __vector __pixel */ |
2535 | RS6000_BTI_long, /* long_integer_type_node */ | |
2536 | RS6000_BTI_unsigned_long, /* long_unsigned_type_node */ | |
c9485473 MM |
2537 | RS6000_BTI_long_long, /* long_long_integer_type_node */ |
2538 | RS6000_BTI_unsigned_long_long, /* long_long_unsigned_type_node */ | |
58646b77 PB |
2539 | RS6000_BTI_INTQI, /* intQI_type_node */ |
2540 | RS6000_BTI_UINTQI, /* unsigned_intQI_type_node */ | |
2541 | RS6000_BTI_INTHI, /* intHI_type_node */ | |
2542 | RS6000_BTI_UINTHI, /* unsigned_intHI_type_node */ | |
2543 | RS6000_BTI_INTSI, /* intSI_type_node */ | |
2544 | RS6000_BTI_UINTSI, /* unsigned_intSI_type_node */ | |
a72c65c7 MM |
2545 | RS6000_BTI_INTDI, /* intDI_type_node */ |
2546 | RS6000_BTI_UINTDI, /* unsigned_intDI_type_node */ | |
58646b77 | 2547 | RS6000_BTI_float, /* float_type_node */ |
a72c65c7 | 2548 | RS6000_BTI_double, /* double_type_node */ |
58646b77 PB |
2549 | RS6000_BTI_void, /* void_type_node */ |
2550 | RS6000_BTI_MAX | |
0ac081f6 | 2551 | }; |
58646b77 PB |
2552 | |
2553 | ||
2554 | #define opaque_V2SI_type_node (rs6000_builtin_types[RS6000_BTI_opaque_V2SI]) | |
2555 | #define opaque_V2SF_type_node (rs6000_builtin_types[RS6000_BTI_opaque_V2SF]) | |
2556 | #define opaque_p_V2SI_type_node (rs6000_builtin_types[RS6000_BTI_opaque_p_V2SI]) | |
2557 | #define opaque_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_opaque_V4SI]) | |
2558 | #define V16QI_type_node (rs6000_builtin_types[RS6000_BTI_V16QI]) | |
a72c65c7 MM |
2559 | #define V2DI_type_node (rs6000_builtin_types[RS6000_BTI_V2DI]) |
2560 | #define V2DF_type_node (rs6000_builtin_types[RS6000_BTI_V2DF]) | |
58646b77 PB |
2561 | #define V2SI_type_node (rs6000_builtin_types[RS6000_BTI_V2SI]) |
2562 | #define V2SF_type_node (rs6000_builtin_types[RS6000_BTI_V2SF]) | |
2563 | #define V4HI_type_node (rs6000_builtin_types[RS6000_BTI_V4HI]) | |
2564 | #define V4SI_type_node (rs6000_builtin_types[RS6000_BTI_V4SI]) | |
2565 | #define V4SF_type_node (rs6000_builtin_types[RS6000_BTI_V4SF]) | |
2566 | #define V8HI_type_node (rs6000_builtin_types[RS6000_BTI_V8HI]) | |
2567 | #define unsigned_V16QI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V16QI]) | |
2568 | #define unsigned_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V8HI]) | |
2569 | #define unsigned_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V4SI]) | |
a72c65c7 | 2570 | #define unsigned_V2DI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V2DI]) |
58646b77 PB |
2571 | #define bool_char_type_node (rs6000_builtin_types[RS6000_BTI_bool_char]) |
2572 | #define bool_short_type_node (rs6000_builtin_types[RS6000_BTI_bool_short]) | |
2573 | #define bool_int_type_node (rs6000_builtin_types[RS6000_BTI_bool_int]) | |
a72c65c7 | 2574 | #define bool_long_type_node (rs6000_builtin_types[RS6000_BTI_bool_long]) |
58646b77 PB |
2575 | #define pixel_type_node (rs6000_builtin_types[RS6000_BTI_pixel]) |
2576 | #define bool_V16QI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V16QI]) | |
2577 | #define bool_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V8HI]) | |
2578 | #define bool_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V4SI]) | |
a72c65c7 | 2579 | #define bool_V2DI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V2DI]) |
58646b77 PB |
2580 | #define pixel_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_pixel_V8HI]) |
2581 | ||
c9485473 MM |
2582 | #define long_long_integer_type_internal_node (rs6000_builtin_types[RS6000_BTI_long_long]) |
2583 | #define long_long_unsigned_type_internal_node (rs6000_builtin_types[RS6000_BTI_unsigned_long_long]) | |
58646b77 PB |
2584 | #define long_integer_type_internal_node (rs6000_builtin_types[RS6000_BTI_long]) |
2585 | #define long_unsigned_type_internal_node (rs6000_builtin_types[RS6000_BTI_unsigned_long]) | |
2586 | #define intQI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTQI]) | |
2587 | #define uintQI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTQI]) | |
2588 | #define intHI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTHI]) | |
2589 | #define uintHI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTHI]) | |
2590 | #define intSI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTSI]) | |
2591 | #define uintSI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTSI]) | |
a72c65c7 MM |
2592 | #define intDI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTDI]) |
2593 | #define uintDI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTDI]) | |
58646b77 | 2594 | #define float_type_internal_node (rs6000_builtin_types[RS6000_BTI_float]) |
a72c65c7 | 2595 | #define double_type_internal_node (rs6000_builtin_types[RS6000_BTI_double]) |
58646b77 PB |
2596 | #define void_type_internal_node (rs6000_builtin_types[RS6000_BTI_void]) |
2597 | ||
2598 | extern GTY(()) tree rs6000_builtin_types[RS6000_BTI_MAX]; | |
2599 | extern GTY(()) tree rs6000_builtin_decls[RS6000_BUILTIN_COUNT]; | |
2600 |